From: Luke Kenneth Casson Leighton Date: Sat, 27 Mar 2021 17:38:26 +0000 (+0000) Subject: really weird error "unsupported direction for eint" which makes no sense X-Git-Tag: LS180_RC3~166^2~7 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3b9977b35d15a6b60130719a36a44d16168311ba;p=soclayout.git really weird error "unsupported direction for eint" which makes no sense --- diff --git a/experiments9/non_generated/full_core_ls180.il b/experiments9/non_generated/full_core_ls180.il index 6344194..486d090 100644 --- a/experiments9/non_generated/full_core_ls180.il +++ b/experiments9/non_generated/full_core_ls180.il @@ -1,5 +1,5 @@ -# Generated by Yosys 0.9+3578 (git sha1 c6ff947f, clang 9.0.1-12 -fPIC -Os) -autoidx 15046 +# Generated by Yosys 0.9+3981 (git sha1 a3528649, clang 9.0.1-12 -fPIC -Os) +autoidx 15032 attribute \src "libresoc.v:5.1-335.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec.ALU_dec19" @@ -29747,60 +29747,60 @@ module \SPR_dec31_dec_sub19 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:20720.1-20992.10" +attribute \src "libresoc.v:20720.1-21040.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.jtag._fsm" attribute \generator "nMigen" module \_fsm - attribute \src "libresoc.v:20840.3-20954.6" + attribute \src "libresoc.v:20864.3-20978.6" wire width 4 $0\fsm_state$next[3:0]$464 attribute \src "libresoc.v:20806.3-20807.35" wire width 4 $0\fsm_state[3:0] attribute \src "libresoc.v:20721.7-20721.20" wire $0\initial[0:0] - attribute \src "libresoc.v:20812.3-20839.6" + attribute \src "libresoc.v:20812.3-20863.6" wire $0\isdr$next[0:0]$460 attribute \src "libresoc.v:20808.3-20809.25" wire $0\isdr[0:0] - attribute \src "libresoc.v:20955.3-20982.6" + attribute \src "libresoc.v:20979.3-21030.6" wire $0\isir$next[0:0]$477 attribute \src "libresoc.v:20810.3-20811.25" wire $0\isir[0:0] - attribute \src "libresoc.v:20840.3-20954.6" + attribute \src "libresoc.v:20864.3-20978.6" wire width 4 $10\fsm_state$next[3:0]$474 - attribute \src "libresoc.v:20840.3-20954.6" + attribute \src "libresoc.v:20864.3-20978.6" wire width 4 $11\fsm_state$next[3:0]$475 - attribute \src "libresoc.v:20840.3-20954.6" + attribute \src "libresoc.v:20864.3-20978.6" wire width 4 $1\fsm_state$next[3:0]$465 attribute \src "libresoc.v:20761.13-20761.29" wire width 4 $1\fsm_state[3:0] - attribute \src "libresoc.v:20812.3-20839.6" + attribute \src "libresoc.v:20812.3-20863.6" wire $1\isdr$next[0:0]$461 attribute \src "libresoc.v:20766.7-20766.18" wire $1\isdr[0:0] - attribute \src "libresoc.v:20955.3-20982.6" + attribute \src "libresoc.v:20979.3-21030.6" wire $1\isir$next[0:0]$478 attribute \src "libresoc.v:20771.7-20771.18" wire $1\isir[0:0] - attribute \src "libresoc.v:20840.3-20954.6" + attribute \src "libresoc.v:20864.3-20978.6" wire width 4 $2\fsm_state$next[3:0]$466 - attribute \src "libresoc.v:20812.3-20839.6" + attribute \src "libresoc.v:20812.3-20863.6" wire $2\isdr$next[0:0]$462 - attribute \src "libresoc.v:20955.3-20982.6" + attribute \src "libresoc.v:20979.3-21030.6" wire $2\isir$next[0:0]$479 - attribute \src "libresoc.v:20840.3-20954.6" + attribute \src "libresoc.v:20864.3-20978.6" wire width 4 $3\fsm_state$next[3:0]$467 - attribute \src "libresoc.v:20840.3-20954.6" + attribute \src "libresoc.v:20864.3-20978.6" wire width 4 $4\fsm_state$next[3:0]$468 - attribute \src "libresoc.v:20840.3-20954.6" + attribute \src "libresoc.v:20864.3-20978.6" wire width 4 $5\fsm_state$next[3:0]$469 - attribute \src "libresoc.v:20840.3-20954.6" + attribute \src "libresoc.v:20864.3-20978.6" wire width 4 $6\fsm_state$next[3:0]$470 - attribute \src "libresoc.v:20840.3-20954.6" + attribute \src "libresoc.v:20864.3-20978.6" wire width 4 $7\fsm_state$next[3:0]$471 - attribute \src "libresoc.v:20840.3-20954.6" + attribute \src "libresoc.v:20864.3-20978.6" wire width 4 $8\fsm_state$next[3:0]$472 - attribute \src "libresoc.v:20840.3-20954.6" + attribute \src "libresoc.v:20864.3-20978.6" wire width 4 $9\fsm_state$next[3:0]$473 attribute \src "libresoc.v:20790.17-20790.110" wire $eq$libresoc.v:20790$440_Y @@ -30131,7 +30131,7 @@ module \_fsm sync posedge \local_clk update \isir $0\isir[0:0] end - attribute \src "libresoc.v:20812.3-20839.6" + attribute \src "libresoc.v:20812.3-20863.6" process $proc$libresoc.v:20812$459 assign { } { } assign { } { } @@ -30166,6 +30166,24 @@ module \_fsm assign $2\isdr$next[0:0]$462 \isdr end attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\isdr$next[0:0]$461 \isdr + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\isdr$next[0:0]$461 \isdr + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\isdr$next[0:0]$461 \isdr + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign $1\isdr$next[0:0]$461 \isdr + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign $1\isdr$next[0:0]$461 \isdr + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign $1\isdr$next[0:0]$461 \isdr + attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\isdr$next[0:0]$461 1'0 @@ -30175,14 +30193,14 @@ module \_fsm sync always update \isdr$next $0\isdr$next[0:0]$460 end - attribute \src "libresoc.v:20840.3-20954.6" - process $proc$libresoc.v:20840$463 + attribute \src "libresoc.v:20864.3-20978.6" + process $proc$libresoc.v:20864$463 assign { } { } assign { } { } assign $0\fsm_state$next[3:0]$464 $1\fsm_state$next[3:0]$465 - attribute \src "libresoc.v:20841.5-20841.29" + attribute \src "libresoc.v:20865.5-20865.29" switch \initial - attribute \src "libresoc.v:20841.9-20841.17" + attribute \src "libresoc.v:20865.9-20865.17" case 1'1 case end @@ -30336,14 +30354,14 @@ module \_fsm sync always update \fsm_state$next $0\fsm_state$next[3:0]$464 end - attribute \src "libresoc.v:20955.3-20982.6" - process $proc$libresoc.v:20955$476 + attribute \src "libresoc.v:20979.3-21030.6" + process $proc$libresoc.v:20979$476 assign { } { } assign { } { } assign $0\isir$next[0:0]$477 $1\isir$next[0:0]$478 - attribute \src "libresoc.v:20956.5-20956.29" + attribute \src "libresoc.v:20980.5-20980.29" switch \initial - attribute \src "libresoc.v:20956.9-20956.17" + attribute \src "libresoc.v:20980.9-20980.17" case 1'1 case end @@ -30358,6 +30376,9 @@ module \_fsm assign { } { } assign $1\isir$next[0:0]$478 1'0 attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\isir$next[0:0]$478 \isir + attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\isir$next[0:0]$478 $2\isir$next[0:0]$479 @@ -30371,6 +30392,21 @@ module \_fsm assign $2\isir$next[0:0]$479 \isir end attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\isir$next[0:0]$478 \isir + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\isir$next[0:0]$478 \isir + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign $1\isir$next[0:0]$478 \isir + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign $1\isir$next[0:0]$478 \isir + attribute \src "libresoc.v:0.0-0.0" + case 4'1001 + assign $1\isir$next[0:0]$478 \isir + attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\isir$next[0:0]$478 1'0 @@ -30406,29 +30442,29 @@ module \_fsm connect \posjtag_rst \rst connect \posjtag_clk \TAP_bus__tck end -attribute \src "libresoc.v:20996.1-21068.10" +attribute \src "libresoc.v:21044.1-21116.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.jtag._idblock" attribute \generator "nMigen" module \_idblock - attribute \src "libresoc.v:21041.3-21061.6" + attribute \src "libresoc.v:21089.3-21109.6" wire width 32 $0\TAP_id_sr$next[31:0]$489 - attribute \src "libresoc.v:21039.3-21040.35" + attribute \src "libresoc.v:21087.3-21088.35" wire width 32 $0\TAP_id_sr[31:0] - attribute \src "libresoc.v:20997.7-20997.20" + attribute \src "libresoc.v:21045.7-21045.20" wire $0\initial[0:0] - attribute \src "libresoc.v:21041.3-21061.6" + attribute \src "libresoc.v:21089.3-21109.6" wire width 32 $1\TAP_id_sr$next[31:0]$490 - attribute \src "libresoc.v:21007.14-21007.31" + attribute \src "libresoc.v:21055.14-21055.31" wire width 32 $1\TAP_id_sr[31:0] - attribute \src "libresoc.v:21041.3-21061.6" + attribute \src "libresoc.v:21089.3-21109.6" wire width 32 $2\TAP_id_sr$next[31:0]$491 - attribute \src "libresoc.v:21036.17-21036.110" - wire $and$libresoc.v:21036$484_Y - attribute \src "libresoc.v:21037.17-21037.108" - wire $and$libresoc.v:21037$485_Y - attribute \src "libresoc.v:21038.17-21038.109" - wire $and$libresoc.v:21038$486_Y + attribute \src "libresoc.v:21084.17-21084.110" + wire $and$libresoc.v:21084$484_Y + attribute \src "libresoc.v:21085.17-21085.108" + wire $and$libresoc.v:21085$485_Y + attribute \src "libresoc.v:21086.17-21086.109" + wire $and$libresoc.v:21086$486_Y attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" wire \$1 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" @@ -30457,7 +30493,7 @@ module \_idblock wire input 2 \capture attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:375" wire input 1 \id_bypass - attribute \src "libresoc.v:20997.7-20997.15" + attribute \src "libresoc.v:21045.7-21045.15" wire \initial attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" wire input 8 \posjtag_clk @@ -30470,7 +30506,7 @@ module \_idblock attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" wire input 4 \update attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:383" - cell $and $and$libresoc.v:21036$484 + cell $and $and$libresoc.v:21084$484 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30478,10 +30514,10 @@ module \_idblock parameter \Y_WIDTH 1 connect \A \select_id connect \B \capture - connect \Y $and$libresoc.v:21036$484_Y + connect \Y $and$libresoc.v:21084$484_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:384" - cell $and $and$libresoc.v:21037$485 + cell $and $and$libresoc.v:21085$485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30489,10 +30525,10 @@ module \_idblock parameter \Y_WIDTH 1 connect \A \select_id connect \B \shift - connect \Y $and$libresoc.v:21037$485_Y + connect \Y $and$libresoc.v:21085$485_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:385" - cell $and $and$libresoc.v:21038$486 + cell $and $and$libresoc.v:21086$486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30500,39 +30536,39 @@ module \_idblock parameter \Y_WIDTH 1 connect \A \select_id connect \B \update - connect \Y $and$libresoc.v:21038$486_Y + connect \Y $and$libresoc.v:21086$486_Y end - attribute \src "libresoc.v:20997.7-20997.20" - process $proc$libresoc.v:20997$492 + attribute \src "libresoc.v:21045.7-21045.20" + process $proc$libresoc.v:21045$492 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:21007.14-21007.31" - process $proc$libresoc.v:21007$493 + attribute \src "libresoc.v:21055.14-21055.31" + process $proc$libresoc.v:21055$493 assign { } { } assign $1\TAP_id_sr[31:0] 0 sync always sync init update \TAP_id_sr $1\TAP_id_sr[31:0] end - attribute \src "libresoc.v:21039.3-21040.35" - process $proc$libresoc.v:21039$487 + attribute \src "libresoc.v:21087.3-21088.35" + process $proc$libresoc.v:21087$487 assign { } { } assign $0\TAP_id_sr[31:0] \TAP_id_sr$next sync posedge \posjtag_clk update \TAP_id_sr $0\TAP_id_sr[31:0] end - attribute \src "libresoc.v:21041.3-21061.6" - process $proc$libresoc.v:21041$488 + attribute \src "libresoc.v:21089.3-21109.6" + process $proc$libresoc.v:21089$488 assign { } { } assign { } { } assign $0\TAP_id_sr$next[31:0]$489 $1\TAP_id_sr$next[31:0]$490 - attribute \src "libresoc.v:21042.5-21042.29" + attribute \src "libresoc.v:21090.5-21090.29" switch \initial - attribute \src "libresoc.v:21042.9-21042.17" + attribute \src "libresoc.v:21090.9-21090.17" case 1'1 case end @@ -30563,9 +30599,9 @@ module \_idblock sync always update \TAP_id_sr$next $0\TAP_id_sr$next[31:0]$489 end - connect \$1 $and$libresoc.v:21036$484_Y - connect \$3 $and$libresoc.v:21037$485_Y - connect \$5 $and$libresoc.v:21038$486_Y + connect \$1 $and$libresoc.v:21084$484_Y + connect \$3 $and$libresoc.v:21085$485_Y + connect \$5 $and$libresoc.v:21086$486_Y connect \TAP_id_tdo \TAP_id_sr [0] connect \_bypass \id_bypass connect \_update \$5 @@ -30573,43 +30609,43 @@ module \_idblock connect \_capture \$1 connect \_tdi \TAP_bus__tdi end -attribute \src "libresoc.v:21072.1-21156.10" +attribute \src "libresoc.v:21120.1-21204.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.jtag._irblock" attribute \generator "nMigen" module \_irblock - attribute \src "libresoc.v:21073.7-21073.20" + attribute \src "libresoc.v:21121.7-21121.20" wire $0\initial[0:0] - attribute \src "libresoc.v:21134.3-21154.6" + attribute \src "libresoc.v:21182.3-21202.6" wire width 4 $0\ir$next[3:0]$506 - attribute \src "libresoc.v:21117.3-21118.21" + attribute \src "libresoc.v:21165.3-21166.21" wire width 4 $0\ir[3:0] - attribute \src "libresoc.v:21121.3-21133.6" + attribute \src "libresoc.v:21169.3-21181.6" wire width 4 $0\shift_ir$next[3:0]$503 - attribute \src "libresoc.v:21119.3-21120.33" + attribute \src "libresoc.v:21167.3-21168.33" wire width 4 $0\shift_ir[3:0] - attribute \src "libresoc.v:21134.3-21154.6" + attribute \src "libresoc.v:21182.3-21202.6" wire width 4 $1\ir$next[3:0]$507 - attribute \src "libresoc.v:21092.13-21092.22" + attribute \src "libresoc.v:21140.13-21140.22" wire width 4 $1\ir[3:0] - attribute \src "libresoc.v:21121.3-21133.6" + attribute \src "libresoc.v:21169.3-21181.6" wire width 4 $1\shift_ir$next[3:0]$504 - attribute \src "libresoc.v:21104.13-21104.28" + attribute \src "libresoc.v:21152.13-21152.28" wire width 4 $1\shift_ir[3:0] - attribute \src "libresoc.v:21134.3-21154.6" + attribute \src "libresoc.v:21182.3-21202.6" wire width 4 $2\ir$next[3:0]$508 - attribute \src "libresoc.v:21111.17-21111.103" - wire $and$libresoc.v:21111$494_Y - attribute \src "libresoc.v:21112.18-21112.105" - wire $and$libresoc.v:21112$495_Y - attribute \src "libresoc.v:21113.17-21113.105" - wire $and$libresoc.v:21113$496_Y - attribute \src "libresoc.v:21114.17-21114.103" - wire $and$libresoc.v:21114$497_Y - attribute \src "libresoc.v:21115.17-21115.104" - wire $and$libresoc.v:21115$498_Y - attribute \src "libresoc.v:21116.17-21116.105" - wire $and$libresoc.v:21116$499_Y + attribute \src "libresoc.v:21159.17-21159.103" + wire $and$libresoc.v:21159$494_Y + attribute \src "libresoc.v:21160.18-21160.105" + wire $and$libresoc.v:21160$495_Y + attribute \src "libresoc.v:21161.17-21161.105" + wire $and$libresoc.v:21161$496_Y + attribute \src "libresoc.v:21162.17-21162.103" + wire $and$libresoc.v:21162$497_Y + attribute \src "libresoc.v:21163.17-21163.104" + wire $and$libresoc.v:21163$498_Y + attribute \src "libresoc.v:21164.17-21164.105" + wire $and$libresoc.v:21164$499_Y attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" wire \$1 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" @@ -30626,7 +30662,7 @@ module \_irblock wire input 4 \TAP_bus__tdi attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" wire input 1 \capture - attribute \src "libresoc.v:21073.7-21073.15" + attribute \src "libresoc.v:21121.7-21121.15" wire \initial attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:127" wire width 4 output 9 \ir @@ -30649,7 +30685,7 @@ module \_irblock attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:26" wire input 3 \update attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" - cell $and $and$libresoc.v:21111$494 + cell $and $and$libresoc.v:21159$494 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30657,10 +30693,10 @@ module \_irblock parameter \Y_WIDTH 1 connect \A \isir connect \B \shift - connect \Y $and$libresoc.v:21111$494_Y + connect \Y $and$libresoc.v:21159$494_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" - cell $and $and$libresoc.v:21112$495 + cell $and $and$libresoc.v:21160$495 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30668,10 +30704,10 @@ module \_irblock parameter \Y_WIDTH 1 connect \A \isir connect \B \update - connect \Y $and$libresoc.v:21112$495_Y + connect \Y $and$libresoc.v:21160$495_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" - cell $and $and$libresoc.v:21113$496 + cell $and $and$libresoc.v:21161$496 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30679,10 +30715,10 @@ module \_irblock parameter \Y_WIDTH 1 connect \A \isir connect \B \capture - connect \Y $and$libresoc.v:21113$496_Y + connect \Y $and$libresoc.v:21161$496_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:367" - cell $and $and$libresoc.v:21114$497 + cell $and $and$libresoc.v:21162$497 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30690,10 +30726,10 @@ module \_irblock parameter \Y_WIDTH 1 connect \A \isir connect \B \shift - connect \Y $and$libresoc.v:21114$497_Y + connect \Y $and$libresoc.v:21162$497_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:368" - cell $and $and$libresoc.v:21115$498 + cell $and $and$libresoc.v:21163$498 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30701,10 +30737,10 @@ module \_irblock parameter \Y_WIDTH 1 connect \A \isir connect \B \update - connect \Y $and$libresoc.v:21115$498_Y + connect \Y $and$libresoc.v:21163$498_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:366" - cell $and $and$libresoc.v:21116$499 + cell $and $and$libresoc.v:21164$499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30712,54 +30748,54 @@ module \_irblock parameter \Y_WIDTH 1 connect \A \isir connect \B \capture - connect \Y $and$libresoc.v:21116$499_Y + connect \Y $and$libresoc.v:21164$499_Y end - attribute \src "libresoc.v:21073.7-21073.20" - process $proc$libresoc.v:21073$509 + attribute \src "libresoc.v:21121.7-21121.20" + process $proc$libresoc.v:21121$509 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:21092.13-21092.22" - process $proc$libresoc.v:21092$510 + attribute \src "libresoc.v:21140.13-21140.22" + process $proc$libresoc.v:21140$510 assign { } { } assign $1\ir[3:0] 4'0001 sync always sync init update \ir $1\ir[3:0] end - attribute \src "libresoc.v:21104.13-21104.28" - process $proc$libresoc.v:21104$511 + attribute \src "libresoc.v:21152.13-21152.28" + process $proc$libresoc.v:21152$511 assign { } { } assign $1\shift_ir[3:0] 4'0000 sync always sync init update \shift_ir $1\shift_ir[3:0] end - attribute \src "libresoc.v:21117.3-21118.21" - process $proc$libresoc.v:21117$500 + attribute \src "libresoc.v:21165.3-21166.21" + process $proc$libresoc.v:21165$500 assign { } { } assign $0\ir[3:0] \ir$next sync posedge \posjtag_clk update \ir $0\ir[3:0] end - attribute \src "libresoc.v:21119.3-21120.33" - process $proc$libresoc.v:21119$501 + attribute \src "libresoc.v:21167.3-21168.33" + process $proc$libresoc.v:21167$501 assign { } { } assign $0\shift_ir[3:0] \shift_ir$next sync posedge \posjtag_clk update \shift_ir $0\shift_ir[3:0] end - attribute \src "libresoc.v:21121.3-21133.6" - process $proc$libresoc.v:21121$502 + attribute \src "libresoc.v:21169.3-21181.6" + process $proc$libresoc.v:21169$502 assign { } { } assign { } { } assign $0\shift_ir$next[3:0]$503 $1\shift_ir$next[3:0]$504 - attribute \src "libresoc.v:21122.5-21122.29" + attribute \src "libresoc.v:21170.5-21170.29" switch \initial - attribute \src "libresoc.v:21122.9-21122.17" + attribute \src "libresoc.v:21170.9-21170.17" case 1'1 case end @@ -30779,15 +30815,15 @@ module \_irblock sync always update \shift_ir$next $0\shift_ir$next[3:0]$503 end - attribute \src "libresoc.v:21134.3-21154.6" - process $proc$libresoc.v:21134$505 + attribute \src "libresoc.v:21182.3-21202.6" + process $proc$libresoc.v:21182$505 assign { } { } assign { } { } assign { } { } assign $0\ir$next[3:0]$506 $2\ir$next[3:0]$508 - attribute \src "libresoc.v:21135.5-21135.29" + attribute \src "libresoc.v:21183.5-21183.29" switch \initial - attribute \src "libresoc.v:21135.9-21135.17" + attribute \src "libresoc.v:21183.9-21183.17" case 1'1 case end @@ -30818,45 +30854,45 @@ module \_irblock sync always update \ir$next $0\ir$next[3:0]$506 end - connect \$9 $and$libresoc.v:21111$494_Y - connect \$11 $and$libresoc.v:21112$495_Y - connect \$1 $and$libresoc.v:21113$496_Y - connect \$3 $and$libresoc.v:21114$497_Y - connect \$5 $and$libresoc.v:21115$498_Y - connect \$7 $and$libresoc.v:21116$499_Y + connect \$9 $and$libresoc.v:21159$494_Y + connect \$11 $and$libresoc.v:21160$495_Y + connect \$1 $and$libresoc.v:21161$496_Y + connect \$3 $and$libresoc.v:21162$497_Y + connect \$5 $and$libresoc.v:21163$498_Y + connect \$7 $and$libresoc.v:21164$499_Y connect \tdo \ir [0] end -attribute \src "libresoc.v:21160.1-21218.10" +attribute \src "libresoc.v:21208.1-21266.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.adr_l" attribute \generator "nMigen" module \adr_l - attribute \src "libresoc.v:21161.7-21161.20" + attribute \src "libresoc.v:21209.7-21209.20" wire $0\initial[0:0] - attribute \src "libresoc.v:21206.3-21214.6" + attribute \src "libresoc.v:21254.3-21262.6" wire $0\q_int$next[0:0]$522 - attribute \src "libresoc.v:21204.3-21205.27" + attribute \src "libresoc.v:21252.3-21253.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:21206.3-21214.6" + attribute \src "libresoc.v:21254.3-21262.6" wire $1\q_int$next[0:0]$523 - attribute \src "libresoc.v:21185.7-21185.19" + attribute \src "libresoc.v:21233.7-21233.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:21196.17-21196.96" - wire $and$libresoc.v:21196$512_Y - attribute \src "libresoc.v:21201.17-21201.96" - wire $and$libresoc.v:21201$517_Y - attribute \src "libresoc.v:21198.18-21198.93" - wire $not$libresoc.v:21198$514_Y - attribute \src "libresoc.v:21200.17-21200.92" - wire $not$libresoc.v:21200$516_Y - attribute \src "libresoc.v:21203.17-21203.92" - wire $not$libresoc.v:21203$519_Y - attribute \src "libresoc.v:21197.18-21197.98" - wire $or$libresoc.v:21197$513_Y - attribute \src "libresoc.v:21199.18-21199.99" - wire $or$libresoc.v:21199$515_Y - attribute \src "libresoc.v:21202.17-21202.97" - wire $or$libresoc.v:21202$518_Y + attribute \src "libresoc.v:21244.17-21244.96" + wire $and$libresoc.v:21244$512_Y + attribute \src "libresoc.v:21249.17-21249.96" + wire $and$libresoc.v:21249$517_Y + attribute \src "libresoc.v:21246.18-21246.93" + wire $not$libresoc.v:21246$514_Y + attribute \src "libresoc.v:21248.17-21248.92" + wire $not$libresoc.v:21248$516_Y + attribute \src "libresoc.v:21251.17-21251.92" + wire $not$libresoc.v:21251$519_Y + attribute \src "libresoc.v:21245.18-21245.98" + wire $or$libresoc.v:21245$513_Y + attribute \src "libresoc.v:21247.18-21247.99" + wire $or$libresoc.v:21247$515_Y + attribute \src "libresoc.v:21250.17-21250.97" + wire $or$libresoc.v:21250$518_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -30873,11 +30909,11 @@ module \adr_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:21161.7-21161.15" + attribute \src "libresoc.v:21209.7-21209.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_adr @@ -30894,7 +30930,7 @@ module \adr_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_adr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:21196$512 + cell $and $and$libresoc.v:21244$512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30902,10 +30938,10 @@ module \adr_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:21196$512_Y + connect \Y $and$libresoc.v:21244$512_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:21201$517 + cell $and $and$libresoc.v:21249$517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30913,34 +30949,34 @@ module \adr_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:21201$517_Y + connect \Y $and$libresoc.v:21249$517_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:21198$514 + cell $not $not$libresoc.v:21246$514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_adr - connect \Y $not$libresoc.v:21198$514_Y + connect \Y $not$libresoc.v:21246$514_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:21200$516 + cell $not $not$libresoc.v:21248$516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_adr - connect \Y $not$libresoc.v:21200$516_Y + connect \Y $not$libresoc.v:21248$516_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:21203$519 + cell $not $not$libresoc.v:21251$519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_adr - connect \Y $not$libresoc.v:21203$519_Y + connect \Y $not$libresoc.v:21251$519_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:21197$513 + cell $or $or$libresoc.v:21245$513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30948,10 +30984,10 @@ module \adr_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_adr - connect \Y $or$libresoc.v:21197$513_Y + connect \Y $or$libresoc.v:21245$513_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:21199$515 + cell $or $or$libresoc.v:21247$515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30959,10 +30995,10 @@ module \adr_l parameter \Y_WIDTH 1 connect \A \q_adr connect \B \q_int - connect \Y $or$libresoc.v:21199$515_Y + connect \Y $or$libresoc.v:21247$515_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:21202$518 + cell $or $or$libresoc.v:21250$518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -30970,39 +31006,39 @@ module \adr_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_adr - connect \Y $or$libresoc.v:21202$518_Y + connect \Y $or$libresoc.v:21250$518_Y end - attribute \src "libresoc.v:21161.7-21161.20" - process $proc$libresoc.v:21161$524 + attribute \src "libresoc.v:21209.7-21209.20" + process $proc$libresoc.v:21209$524 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:21185.7-21185.19" - process $proc$libresoc.v:21185$525 + attribute \src "libresoc.v:21233.7-21233.19" + process $proc$libresoc.v:21233$525 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:21204.3-21205.27" - process $proc$libresoc.v:21204$520 + attribute \src "libresoc.v:21252.3-21253.27" + process $proc$libresoc.v:21252$520 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:21206.3-21214.6" - process $proc$libresoc.v:21206$521 + attribute \src "libresoc.v:21254.3-21262.6" + process $proc$libresoc.v:21254$521 assign { } { } assign { } { } assign $0\q_int$next[0:0]$522 $1\q_int$next[0:0]$523 - attribute \src "libresoc.v:21207.5-21207.29" + attribute \src "libresoc.v:21255.5-21255.29" switch \initial - attribute \src "libresoc.v:21207.9-21207.17" + attribute \src "libresoc.v:21255.9-21255.17" case 1'1 case end @@ -31018,49 +31054,49 @@ module \adr_l sync always update \q_int$next $0\q_int$next[0:0]$522 end - connect \$9 $and$libresoc.v:21196$512_Y - connect \$11 $or$libresoc.v:21197$513_Y - connect \$13 $not$libresoc.v:21198$514_Y - connect \$15 $or$libresoc.v:21199$515_Y - connect \$1 $not$libresoc.v:21200$516_Y - connect \$3 $and$libresoc.v:21201$517_Y - connect \$5 $or$libresoc.v:21202$518_Y - connect \$7 $not$libresoc.v:21203$519_Y + connect \$9 $and$libresoc.v:21244$512_Y + connect \$11 $or$libresoc.v:21245$513_Y + connect \$13 $not$libresoc.v:21246$514_Y + connect \$15 $or$libresoc.v:21247$515_Y + connect \$1 $not$libresoc.v:21248$516_Y + connect \$3 $and$libresoc.v:21249$517_Y + connect \$5 $or$libresoc.v:21250$518_Y + connect \$7 $not$libresoc.v:21251$519_Y connect \qlq_adr \$15 connect \qn_adr \$13 connect \q_adr \$11 end -attribute \src "libresoc.v:21222.1-21280.10" +attribute \src "libresoc.v:21270.1-21328.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.adrok_l" attribute \generator "nMigen" module \adrok_l - attribute \src "libresoc.v:21223.7-21223.20" + attribute \src "libresoc.v:21271.7-21271.20" wire $0\initial[0:0] - attribute \src "libresoc.v:21268.3-21276.6" + attribute \src "libresoc.v:21316.3-21324.6" wire $0\q_int$next[0:0]$536 - attribute \src "libresoc.v:21266.3-21267.27" + attribute \src "libresoc.v:21314.3-21315.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:21268.3-21276.6" + attribute \src "libresoc.v:21316.3-21324.6" wire $1\q_int$next[0:0]$537 - attribute \src "libresoc.v:21247.7-21247.19" + attribute \src "libresoc.v:21295.7-21295.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:21258.17-21258.96" - wire $and$libresoc.v:21258$526_Y - attribute \src "libresoc.v:21263.17-21263.96" - wire $and$libresoc.v:21263$531_Y - attribute \src "libresoc.v:21260.18-21260.100" - wire $not$libresoc.v:21260$528_Y - attribute \src "libresoc.v:21262.17-21262.99" - wire $not$libresoc.v:21262$530_Y - attribute \src "libresoc.v:21265.17-21265.99" - wire $not$libresoc.v:21265$533_Y - attribute \src "libresoc.v:21259.18-21259.105" - wire $or$libresoc.v:21259$527_Y - attribute \src "libresoc.v:21261.18-21261.106" - wire $or$libresoc.v:21261$529_Y - attribute \src "libresoc.v:21264.17-21264.104" - wire $or$libresoc.v:21264$532_Y + attribute \src "libresoc.v:21306.17-21306.96" + wire $and$libresoc.v:21306$526_Y + attribute \src "libresoc.v:21311.17-21311.96" + wire $and$libresoc.v:21311$531_Y + attribute \src "libresoc.v:21308.18-21308.100" + wire $not$libresoc.v:21308$528_Y + attribute \src "libresoc.v:21310.17-21310.99" + wire $not$libresoc.v:21310$530_Y + attribute \src "libresoc.v:21313.17-21313.99" + wire $not$libresoc.v:21313$533_Y + attribute \src "libresoc.v:21307.18-21307.105" + wire $or$libresoc.v:21307$527_Y + attribute \src "libresoc.v:21309.18-21309.106" + wire $or$libresoc.v:21309$529_Y + attribute \src "libresoc.v:21312.17-21312.104" + wire $or$libresoc.v:21312$532_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -31077,11 +31113,11 @@ module \adrok_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 6 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:21223.7-21223.15" + attribute \src "libresoc.v:21271.7-21271.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 5 \q_addr_acked @@ -31098,7 +31134,7 @@ module \adrok_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_addr_acked attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:21258$526 + cell $and $and$libresoc.v:21306$526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -31106,10 +31142,10 @@ module \adrok_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:21258$526_Y + connect \Y $and$libresoc.v:21306$526_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:21263$531 + cell $and $and$libresoc.v:21311$531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -31117,34 +31153,34 @@ module \adrok_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:21263$531_Y + connect \Y $and$libresoc.v:21311$531_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:21260$528 + cell $not $not$libresoc.v:21308$528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_addr_acked - connect \Y $not$libresoc.v:21260$528_Y + connect \Y $not$libresoc.v:21308$528_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:21262$530 + cell $not $not$libresoc.v:21310$530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_addr_acked - connect \Y $not$libresoc.v:21262$530_Y + connect \Y $not$libresoc.v:21310$530_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:21265$533 + cell $not $not$libresoc.v:21313$533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_addr_acked - connect \Y $not$libresoc.v:21265$533_Y + connect \Y $not$libresoc.v:21313$533_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:21259$527 + cell $or $or$libresoc.v:21307$527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -31152,10 +31188,10 @@ module \adrok_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_addr_acked - connect \Y $or$libresoc.v:21259$527_Y + connect \Y $or$libresoc.v:21307$527_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:21261$529 + cell $or $or$libresoc.v:21309$529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -31163,10 +31199,10 @@ module \adrok_l parameter \Y_WIDTH 1 connect \A \q_addr_acked connect \B \q_int - connect \Y $or$libresoc.v:21261$529_Y + connect \Y $or$libresoc.v:21309$529_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:21264$532 + cell $or $or$libresoc.v:21312$532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -31174,39 +31210,39 @@ module \adrok_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_addr_acked - connect \Y $or$libresoc.v:21264$532_Y + connect \Y $or$libresoc.v:21312$532_Y end - attribute \src "libresoc.v:21223.7-21223.20" - process $proc$libresoc.v:21223$538 + attribute \src "libresoc.v:21271.7-21271.20" + process $proc$libresoc.v:21271$538 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:21247.7-21247.19" - process $proc$libresoc.v:21247$539 + attribute \src "libresoc.v:21295.7-21295.19" + process $proc$libresoc.v:21295$539 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:21266.3-21267.27" - process $proc$libresoc.v:21266$534 + attribute \src "libresoc.v:21314.3-21315.27" + process $proc$libresoc.v:21314$534 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:21268.3-21276.6" - process $proc$libresoc.v:21268$535 + attribute \src "libresoc.v:21316.3-21324.6" + process $proc$libresoc.v:21316$535 assign { } { } assign { } { } assign $0\q_int$next[0:0]$536 $1\q_int$next[0:0]$537 - attribute \src "libresoc.v:21269.5-21269.29" + attribute \src "libresoc.v:21317.5-21317.29" switch \initial - attribute \src "libresoc.v:21269.9-21269.17" + attribute \src "libresoc.v:21317.9-21317.17" case 1'1 case end @@ -31222,593 +31258,593 @@ module \adrok_l sync always update \q_int$next $0\q_int$next[0:0]$536 end - connect \$9 $and$libresoc.v:21258$526_Y - connect \$11 $or$libresoc.v:21259$527_Y - connect \$13 $not$libresoc.v:21260$528_Y - connect \$15 $or$libresoc.v:21261$529_Y - connect \$1 $not$libresoc.v:21262$530_Y - connect \$3 $and$libresoc.v:21263$531_Y - connect \$5 $or$libresoc.v:21264$532_Y - connect \$7 $not$libresoc.v:21265$533_Y + connect \$9 $and$libresoc.v:21306$526_Y + connect \$11 $or$libresoc.v:21307$527_Y + connect \$13 $not$libresoc.v:21308$528_Y + connect \$15 $or$libresoc.v:21309$529_Y + connect \$1 $not$libresoc.v:21310$530_Y + connect \$3 $and$libresoc.v:21311$531_Y + connect \$5 $or$libresoc.v:21312$532_Y + connect \$7 $not$libresoc.v:21313$533_Y connect \qlq_addr_acked \$15 connect \qn_addr_acked \$13 connect \q_addr_acked \$11 end -attribute \src "libresoc.v:21284.1-22615.10" +attribute \src "libresoc.v:21332.1-22663.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0" attribute \generator "nMigen" module \alu0 - attribute \src "libresoc.v:22126.3-22127.25" + attribute \src "libresoc.v:22174.3-22175.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire width 4 $0\alu_alu0_alu_op__data_len$next[3:0]$686 - attribute \src "libresoc.v:22098.3-22099.67" + attribute \src "libresoc.v:22146.3-22147.67" wire width 4 $0\alu_alu0_alu_op__data_len[3:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire width 14 $0\alu_alu0_alu_op__fn_unit$next[13:0]$687 - attribute \src "libresoc.v:22068.3-22069.65" + attribute \src "libresoc.v:22116.3-22117.65" wire width 14 $0\alu_alu0_alu_op__fn_unit[13:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire width 64 $0\alu_alu0_alu_op__imm_data__data$next[63:0]$688 - attribute \src "libresoc.v:22070.3-22071.79" + attribute \src "libresoc.v:22118.3-22119.79" wire width 64 $0\alu_alu0_alu_op__imm_data__data[63:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $0\alu_alu0_alu_op__imm_data__ok$next[0:0]$689 - attribute \src "libresoc.v:22072.3-22073.75" + attribute \src "libresoc.v:22120.3-22121.75" wire $0\alu_alu0_alu_op__imm_data__ok[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire width 2 $0\alu_alu0_alu_op__input_carry$next[1:0]$690 - attribute \src "libresoc.v:22090.3-22091.73" + attribute \src "libresoc.v:22138.3-22139.73" wire width 2 $0\alu_alu0_alu_op__input_carry[1:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire width 32 $0\alu_alu0_alu_op__insn$next[31:0]$691 - attribute \src "libresoc.v:22100.3-22101.59" + attribute \src "libresoc.v:22148.3-22149.59" wire width 32 $0\alu_alu0_alu_op__insn[31:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire width 7 $0\alu_alu0_alu_op__insn_type$next[6:0]$692 - attribute \src "libresoc.v:22066.3-22067.69" + attribute \src "libresoc.v:22114.3-22115.69" wire width 7 $0\alu_alu0_alu_op__insn_type[6:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $0\alu_alu0_alu_op__invert_in$next[0:0]$693 - attribute \src "libresoc.v:22082.3-22083.69" + attribute \src "libresoc.v:22130.3-22131.69" wire $0\alu_alu0_alu_op__invert_in[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $0\alu_alu0_alu_op__invert_out$next[0:0]$694 - attribute \src "libresoc.v:22086.3-22087.71" + attribute \src "libresoc.v:22134.3-22135.71" wire $0\alu_alu0_alu_op__invert_out[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $0\alu_alu0_alu_op__is_32bit$next[0:0]$695 - attribute \src "libresoc.v:22094.3-22095.67" + attribute \src "libresoc.v:22142.3-22143.67" wire $0\alu_alu0_alu_op__is_32bit[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $0\alu_alu0_alu_op__is_signed$next[0:0]$696 - attribute \src "libresoc.v:22096.3-22097.69" + attribute \src "libresoc.v:22144.3-22145.69" wire $0\alu_alu0_alu_op__is_signed[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $0\alu_alu0_alu_op__oe__oe$next[0:0]$697 - attribute \src "libresoc.v:22078.3-22079.63" + attribute \src "libresoc.v:22126.3-22127.63" wire $0\alu_alu0_alu_op__oe__oe[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $0\alu_alu0_alu_op__oe__ok$next[0:0]$698 - attribute \src "libresoc.v:22080.3-22081.63" + attribute \src "libresoc.v:22128.3-22129.63" wire $0\alu_alu0_alu_op__oe__ok[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $0\alu_alu0_alu_op__output_carry$next[0:0]$699 - attribute \src "libresoc.v:22092.3-22093.75" + attribute \src "libresoc.v:22140.3-22141.75" wire $0\alu_alu0_alu_op__output_carry[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $0\alu_alu0_alu_op__rc__ok$next[0:0]$700 - attribute \src "libresoc.v:22076.3-22077.63" + attribute \src "libresoc.v:22124.3-22125.63" wire $0\alu_alu0_alu_op__rc__ok[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $0\alu_alu0_alu_op__rc__rc$next[0:0]$701 - attribute \src "libresoc.v:22074.3-22075.63" + attribute \src "libresoc.v:22122.3-22123.63" wire $0\alu_alu0_alu_op__rc__rc[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $0\alu_alu0_alu_op__write_cr0$next[0:0]$702 - attribute \src "libresoc.v:22088.3-22089.69" + attribute \src "libresoc.v:22136.3-22137.69" wire $0\alu_alu0_alu_op__write_cr0[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $0\alu_alu0_alu_op__zero_a$next[0:0]$703 - attribute \src "libresoc.v:22084.3-22085.63" + attribute \src "libresoc.v:22132.3-22133.63" wire $0\alu_alu0_alu_op__zero_a[0:0] - attribute \src "libresoc.v:22124.3-22125.40" + attribute \src "libresoc.v:22172.3-22173.40" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:22514.3-22522.6" + attribute \src "libresoc.v:22562.3-22570.6" wire $0\alu_l_r_alu$next[0:0]$784 - attribute \src "libresoc.v:22034.3-22035.39" + attribute \src "libresoc.v:22082.3-22083.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:22505.3-22513.6" + attribute \src "libresoc.v:22553.3-22561.6" wire $0\alui_l_r_alui$next[0:0]$781 - attribute \src "libresoc.v:22036.3-22037.43" + attribute \src "libresoc.v:22084.3-22085.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:22355.3-22376.6" + attribute \src "libresoc.v:22403.3-22424.6" wire width 64 $0\data_r0__o$next[63:0]$729 - attribute \src "libresoc.v:22062.3-22063.37" + attribute \src "libresoc.v:22110.3-22111.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:22355.3-22376.6" + attribute \src "libresoc.v:22403.3-22424.6" wire $0\data_r0__o_ok$next[0:0]$730 - attribute \src "libresoc.v:22064.3-22065.43" + attribute \src "libresoc.v:22112.3-22113.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:22377.3-22398.6" + attribute \src "libresoc.v:22425.3-22446.6" wire width 4 $0\data_r1__cr_a$next[3:0]$737 - attribute \src "libresoc.v:22058.3-22059.43" + attribute \src "libresoc.v:22106.3-22107.43" wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:22377.3-22398.6" + attribute \src "libresoc.v:22425.3-22446.6" wire $0\data_r1__cr_a_ok$next[0:0]$738 - attribute \src "libresoc.v:22060.3-22061.49" + attribute \src "libresoc.v:22108.3-22109.49" wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:22399.3-22420.6" + attribute \src "libresoc.v:22447.3-22468.6" wire width 2 $0\data_r2__xer_ca$next[1:0]$745 - attribute \src "libresoc.v:22054.3-22055.47" + attribute \src "libresoc.v:22102.3-22103.47" wire width 2 $0\data_r2__xer_ca[1:0] - attribute \src "libresoc.v:22399.3-22420.6" + attribute \src "libresoc.v:22447.3-22468.6" wire $0\data_r2__xer_ca_ok$next[0:0]$746 - attribute \src "libresoc.v:22056.3-22057.53" + attribute \src "libresoc.v:22104.3-22105.53" wire $0\data_r2__xer_ca_ok[0:0] - attribute \src "libresoc.v:22421.3-22442.6" + attribute \src "libresoc.v:22469.3-22490.6" wire width 2 $0\data_r3__xer_ov$next[1:0]$753 - attribute \src "libresoc.v:22050.3-22051.47" + attribute \src "libresoc.v:22098.3-22099.47" wire width 2 $0\data_r3__xer_ov[1:0] - attribute \src "libresoc.v:22421.3-22442.6" + attribute \src "libresoc.v:22469.3-22490.6" wire $0\data_r3__xer_ov_ok$next[0:0]$754 - attribute \src "libresoc.v:22052.3-22053.53" + attribute \src "libresoc.v:22100.3-22101.53" wire $0\data_r3__xer_ov_ok[0:0] - attribute \src "libresoc.v:22443.3-22464.6" + attribute \src "libresoc.v:22491.3-22512.6" wire $0\data_r4__xer_so$next[0:0]$761 - attribute \src "libresoc.v:22046.3-22047.47" + attribute \src "libresoc.v:22094.3-22095.47" wire $0\data_r4__xer_so[0:0] - attribute \src "libresoc.v:22443.3-22464.6" + attribute \src "libresoc.v:22491.3-22512.6" wire $0\data_r4__xer_so_ok$next[0:0]$762 - attribute \src "libresoc.v:22048.3-22049.53" + attribute \src "libresoc.v:22096.3-22097.53" wire $0\data_r4__xer_so_ok[0:0] - attribute \src "libresoc.v:22523.3-22532.6" + attribute \src "libresoc.v:22571.3-22580.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:22533.3-22542.6" + attribute \src "libresoc.v:22581.3-22590.6" wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:22543.3-22552.6" + attribute \src "libresoc.v:22591.3-22600.6" wire width 2 $0\dest3_o[1:0] - attribute \src "libresoc.v:22553.3-22562.6" + attribute \src "libresoc.v:22601.3-22610.6" wire width 2 $0\dest4_o[1:0] - attribute \src "libresoc.v:22563.3-22572.6" + attribute \src "libresoc.v:22611.3-22620.6" wire $0\dest5_o[0:0] - attribute \src "libresoc.v:21285.7-21285.20" + attribute \src "libresoc.v:21333.7-21333.20" wire $0\initial[0:0] - attribute \src "libresoc.v:22271.3-22279.6" + attribute \src "libresoc.v:22319.3-22327.6" wire $0\opc_l_r_opc$next[0:0]$671 - attribute \src "libresoc.v:22110.3-22111.39" + attribute \src "libresoc.v:22158.3-22159.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:22262.3-22270.6" + attribute \src "libresoc.v:22310.3-22318.6" wire $0\opc_l_s_opc$next[0:0]$668 - attribute \src "libresoc.v:22112.3-22113.39" + attribute \src "libresoc.v:22160.3-22161.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:22573.3-22581.6" + attribute \src "libresoc.v:22621.3-22629.6" wire width 5 $0\prev_wr_go$next[4:0]$792 - attribute \src "libresoc.v:22122.3-22123.37" + attribute \src "libresoc.v:22170.3-22171.37" wire width 5 $0\prev_wr_go[4:0] - attribute \src "libresoc.v:22216.3-22225.6" + attribute \src "libresoc.v:22264.3-22273.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:22307.3-22315.6" + attribute \src "libresoc.v:22355.3-22363.6" wire width 5 $0\req_l_r_req$next[4:0]$683 - attribute \src "libresoc.v:22102.3-22103.39" + attribute \src "libresoc.v:22150.3-22151.39" wire width 5 $0\req_l_r_req[4:0] - attribute \src "libresoc.v:22298.3-22306.6" + attribute \src "libresoc.v:22346.3-22354.6" wire width 5 $0\req_l_s_req$next[4:0]$680 - attribute \src "libresoc.v:22104.3-22105.39" + attribute \src "libresoc.v:22152.3-22153.39" wire width 5 $0\req_l_s_req[4:0] - attribute \src "libresoc.v:22235.3-22243.6" + attribute \src "libresoc.v:22283.3-22291.6" wire $0\rok_l_r_rdok$next[0:0]$659 - attribute \src "libresoc.v:22118.3-22119.41" + attribute \src "libresoc.v:22166.3-22167.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:22226.3-22234.6" + attribute \src "libresoc.v:22274.3-22282.6" wire $0\rok_l_s_rdok$next[0:0]$656 - attribute \src "libresoc.v:22120.3-22121.41" + attribute \src "libresoc.v:22168.3-22169.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:22253.3-22261.6" + attribute \src "libresoc.v:22301.3-22309.6" wire $0\rst_l_r_rst$next[0:0]$665 - attribute \src "libresoc.v:22114.3-22115.39" + attribute \src "libresoc.v:22162.3-22163.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:22244.3-22252.6" + attribute \src "libresoc.v:22292.3-22300.6" wire $0\rst_l_s_rst$next[0:0]$662 - attribute \src "libresoc.v:22116.3-22117.39" + attribute \src "libresoc.v:22164.3-22165.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:22289.3-22297.6" + attribute \src "libresoc.v:22337.3-22345.6" wire width 4 $0\src_l_r_src$next[3:0]$677 - attribute \src "libresoc.v:22106.3-22107.39" + attribute \src "libresoc.v:22154.3-22155.39" wire width 4 $0\src_l_r_src[3:0] - attribute \src "libresoc.v:22280.3-22288.6" + attribute \src "libresoc.v:22328.3-22336.6" wire width 4 $0\src_l_s_src$next[3:0]$674 - attribute \src "libresoc.v:22108.3-22109.39" + attribute \src "libresoc.v:22156.3-22157.39" wire width 4 $0\src_l_s_src[3:0] - attribute \src "libresoc.v:22465.3-22474.6" + attribute \src "libresoc.v:22513.3-22522.6" wire width 64 $0\src_r0$next[63:0]$769 - attribute \src "libresoc.v:22044.3-22045.29" + attribute \src "libresoc.v:22092.3-22093.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:22475.3-22484.6" + attribute \src "libresoc.v:22523.3-22532.6" wire width 64 $0\src_r1$next[63:0]$772 - attribute \src "libresoc.v:22042.3-22043.29" + attribute \src "libresoc.v:22090.3-22091.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:22485.3-22494.6" + attribute \src "libresoc.v:22533.3-22542.6" wire $0\src_r2$next[0:0]$775 - attribute \src "libresoc.v:22040.3-22041.29" + attribute \src "libresoc.v:22088.3-22089.29" wire $0\src_r2[0:0] - attribute \src "libresoc.v:22495.3-22504.6" + attribute \src "libresoc.v:22543.3-22552.6" wire width 2 $0\src_r3$next[1:0]$778 - attribute \src "libresoc.v:22038.3-22039.29" + attribute \src "libresoc.v:22086.3-22087.29" wire width 2 $0\src_r3[1:0] - attribute \src "libresoc.v:21423.7-21423.24" + attribute \src "libresoc.v:21471.7-21471.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire width 4 $1\alu_alu0_alu_op__data_len$next[3:0]$704 - attribute \src "libresoc.v:21431.13-21431.45" + attribute \src "libresoc.v:21479.13-21479.45" wire width 4 $1\alu_alu0_alu_op__data_len[3:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire width 14 $1\alu_alu0_alu_op__fn_unit$next[13:0]$705 - attribute \src "libresoc.v:21450.14-21450.49" + attribute \src "libresoc.v:21498.14-21498.49" wire width 14 $1\alu_alu0_alu_op__fn_unit[13:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire width 64 $1\alu_alu0_alu_op__imm_data__data$next[63:0]$706 - attribute \src "libresoc.v:21454.14-21454.68" + attribute \src "libresoc.v:21502.14-21502.68" wire width 64 $1\alu_alu0_alu_op__imm_data__data[63:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$707 - attribute \src "libresoc.v:21458.7-21458.43" + attribute \src "libresoc.v:21506.7-21506.43" wire $1\alu_alu0_alu_op__imm_data__ok[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire width 2 $1\alu_alu0_alu_op__input_carry$next[1:0]$708 - attribute \src "libresoc.v:21466.13-21466.48" + attribute \src "libresoc.v:21514.13-21514.48" wire width 2 $1\alu_alu0_alu_op__input_carry[1:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire width 32 $1\alu_alu0_alu_op__insn$next[31:0]$709 - attribute \src "libresoc.v:21470.14-21470.43" + attribute \src "libresoc.v:21518.14-21518.43" wire width 32 $1\alu_alu0_alu_op__insn[31:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire width 7 $1\alu_alu0_alu_op__insn_type$next[6:0]$710 - attribute \src "libresoc.v:21549.13-21549.47" + attribute \src "libresoc.v:21597.13-21597.47" wire width 7 $1\alu_alu0_alu_op__insn_type[6:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $1\alu_alu0_alu_op__invert_in$next[0:0]$711 - attribute \src "libresoc.v:21553.7-21553.40" + attribute \src "libresoc.v:21601.7-21601.40" wire $1\alu_alu0_alu_op__invert_in[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $1\alu_alu0_alu_op__invert_out$next[0:0]$712 - attribute \src "libresoc.v:21557.7-21557.41" + attribute \src "libresoc.v:21605.7-21605.41" wire $1\alu_alu0_alu_op__invert_out[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $1\alu_alu0_alu_op__is_32bit$next[0:0]$713 - attribute \src "libresoc.v:21561.7-21561.39" + attribute \src "libresoc.v:21609.7-21609.39" wire $1\alu_alu0_alu_op__is_32bit[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $1\alu_alu0_alu_op__is_signed$next[0:0]$714 - attribute \src "libresoc.v:21565.7-21565.40" + attribute \src "libresoc.v:21613.7-21613.40" wire $1\alu_alu0_alu_op__is_signed[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $1\alu_alu0_alu_op__oe__oe$next[0:0]$715 - attribute \src "libresoc.v:21569.7-21569.37" + attribute \src "libresoc.v:21617.7-21617.37" wire $1\alu_alu0_alu_op__oe__oe[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $1\alu_alu0_alu_op__oe__ok$next[0:0]$716 - attribute \src "libresoc.v:21573.7-21573.37" + attribute \src "libresoc.v:21621.7-21621.37" wire $1\alu_alu0_alu_op__oe__ok[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $1\alu_alu0_alu_op__output_carry$next[0:0]$717 - attribute \src "libresoc.v:21577.7-21577.43" + attribute \src "libresoc.v:21625.7-21625.43" wire $1\alu_alu0_alu_op__output_carry[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $1\alu_alu0_alu_op__rc__ok$next[0:0]$718 - attribute \src "libresoc.v:21581.7-21581.37" + attribute \src "libresoc.v:21629.7-21629.37" wire $1\alu_alu0_alu_op__rc__ok[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $1\alu_alu0_alu_op__rc__rc$next[0:0]$719 - attribute \src "libresoc.v:21585.7-21585.37" + attribute \src "libresoc.v:21633.7-21633.37" wire $1\alu_alu0_alu_op__rc__rc[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $1\alu_alu0_alu_op__write_cr0$next[0:0]$720 - attribute \src "libresoc.v:21589.7-21589.40" + attribute \src "libresoc.v:21637.7-21637.40" wire $1\alu_alu0_alu_op__write_cr0[0:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $1\alu_alu0_alu_op__zero_a$next[0:0]$721 - attribute \src "libresoc.v:21593.7-21593.37" + attribute \src "libresoc.v:21641.7-21641.37" wire $1\alu_alu0_alu_op__zero_a[0:0] - attribute \src "libresoc.v:21625.7-21625.26" + attribute \src "libresoc.v:21673.7-21673.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:22514.3-22522.6" + attribute \src "libresoc.v:22562.3-22570.6" wire $1\alu_l_r_alu$next[0:0]$785 - attribute \src "libresoc.v:21633.7-21633.25" + attribute \src "libresoc.v:21681.7-21681.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:22505.3-22513.6" + attribute \src "libresoc.v:22553.3-22561.6" wire $1\alui_l_r_alui$next[0:0]$782 - attribute \src "libresoc.v:21645.7-21645.27" + attribute \src "libresoc.v:21693.7-21693.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:22355.3-22376.6" + attribute \src "libresoc.v:22403.3-22424.6" wire width 64 $1\data_r0__o$next[63:0]$731 - attribute \src "libresoc.v:21679.14-21679.47" + attribute \src "libresoc.v:21727.14-21727.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:22355.3-22376.6" + attribute \src "libresoc.v:22403.3-22424.6" wire $1\data_r0__o_ok$next[0:0]$732 - attribute \src "libresoc.v:21683.7-21683.27" + attribute \src "libresoc.v:21731.7-21731.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:22377.3-22398.6" + attribute \src "libresoc.v:22425.3-22446.6" wire width 4 $1\data_r1__cr_a$next[3:0]$739 - attribute \src "libresoc.v:21687.13-21687.33" + attribute \src "libresoc.v:21735.13-21735.33" wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:22377.3-22398.6" + attribute \src "libresoc.v:22425.3-22446.6" wire $1\data_r1__cr_a_ok$next[0:0]$740 - attribute \src "libresoc.v:21691.7-21691.30" + attribute \src "libresoc.v:21739.7-21739.30" wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:22399.3-22420.6" + attribute \src "libresoc.v:22447.3-22468.6" wire width 2 $1\data_r2__xer_ca$next[1:0]$747 - attribute \src "libresoc.v:21695.13-21695.35" + attribute \src "libresoc.v:21743.13-21743.35" wire width 2 $1\data_r2__xer_ca[1:0] - attribute \src "libresoc.v:22399.3-22420.6" + attribute \src "libresoc.v:22447.3-22468.6" wire $1\data_r2__xer_ca_ok$next[0:0]$748 - attribute \src "libresoc.v:21699.7-21699.32" + attribute \src "libresoc.v:21747.7-21747.32" wire $1\data_r2__xer_ca_ok[0:0] - attribute \src "libresoc.v:22421.3-22442.6" + attribute \src "libresoc.v:22469.3-22490.6" wire width 2 $1\data_r3__xer_ov$next[1:0]$755 - attribute \src "libresoc.v:21703.13-21703.35" + attribute \src "libresoc.v:21751.13-21751.35" wire width 2 $1\data_r3__xer_ov[1:0] - attribute \src "libresoc.v:22421.3-22442.6" + attribute \src "libresoc.v:22469.3-22490.6" wire $1\data_r3__xer_ov_ok$next[0:0]$756 - attribute \src "libresoc.v:21707.7-21707.32" + attribute \src "libresoc.v:21755.7-21755.32" wire $1\data_r3__xer_ov_ok[0:0] - attribute \src "libresoc.v:22443.3-22464.6" + attribute \src "libresoc.v:22491.3-22512.6" wire $1\data_r4__xer_so$next[0:0]$763 - attribute \src "libresoc.v:21711.7-21711.29" + attribute \src "libresoc.v:21759.7-21759.29" wire $1\data_r4__xer_so[0:0] - attribute \src "libresoc.v:22443.3-22464.6" + attribute \src "libresoc.v:22491.3-22512.6" wire $1\data_r4__xer_so_ok$next[0:0]$764 - attribute \src "libresoc.v:21715.7-21715.32" + attribute \src "libresoc.v:21763.7-21763.32" wire $1\data_r4__xer_so_ok[0:0] - attribute \src "libresoc.v:22523.3-22532.6" + attribute \src "libresoc.v:22571.3-22580.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:22533.3-22542.6" + attribute \src "libresoc.v:22581.3-22590.6" wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:22543.3-22552.6" + attribute \src "libresoc.v:22591.3-22600.6" wire width 2 $1\dest3_o[1:0] - attribute \src "libresoc.v:22553.3-22562.6" + attribute \src "libresoc.v:22601.3-22610.6" wire width 2 $1\dest4_o[1:0] - attribute \src "libresoc.v:22563.3-22572.6" + attribute \src "libresoc.v:22611.3-22620.6" wire $1\dest5_o[0:0] - attribute \src "libresoc.v:22271.3-22279.6" + attribute \src "libresoc.v:22319.3-22327.6" wire $1\opc_l_r_opc$next[0:0]$672 - attribute \src "libresoc.v:21738.7-21738.25" + attribute \src "libresoc.v:21786.7-21786.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:22262.3-22270.6" + attribute \src "libresoc.v:22310.3-22318.6" wire $1\opc_l_s_opc$next[0:0]$669 - attribute \src "libresoc.v:21742.7-21742.25" + attribute \src "libresoc.v:21790.7-21790.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:22573.3-22581.6" + attribute \src "libresoc.v:22621.3-22629.6" wire width 5 $1\prev_wr_go$next[4:0]$793 - attribute \src "libresoc.v:21876.13-21876.31" + attribute \src "libresoc.v:21924.13-21924.31" wire width 5 $1\prev_wr_go[4:0] - attribute \src "libresoc.v:22216.3-22225.6" + attribute \src "libresoc.v:22264.3-22273.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:22307.3-22315.6" + attribute \src "libresoc.v:22355.3-22363.6" wire width 5 $1\req_l_r_req$next[4:0]$684 - attribute \src "libresoc.v:21884.13-21884.32" + attribute \src "libresoc.v:21932.13-21932.32" wire width 5 $1\req_l_r_req[4:0] - attribute \src "libresoc.v:22298.3-22306.6" + attribute \src "libresoc.v:22346.3-22354.6" wire width 5 $1\req_l_s_req$next[4:0]$681 - attribute \src "libresoc.v:21888.13-21888.32" + attribute \src "libresoc.v:21936.13-21936.32" wire width 5 $1\req_l_s_req[4:0] - attribute \src "libresoc.v:22235.3-22243.6" + attribute \src "libresoc.v:22283.3-22291.6" wire $1\rok_l_r_rdok$next[0:0]$660 - attribute \src "libresoc.v:21900.7-21900.26" + attribute \src "libresoc.v:21948.7-21948.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:22226.3-22234.6" + attribute \src "libresoc.v:22274.3-22282.6" wire $1\rok_l_s_rdok$next[0:0]$657 - attribute \src "libresoc.v:21904.7-21904.26" + attribute \src "libresoc.v:21952.7-21952.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:22253.3-22261.6" + attribute \src "libresoc.v:22301.3-22309.6" wire $1\rst_l_r_rst$next[0:0]$666 - attribute \src "libresoc.v:21908.7-21908.25" + attribute \src "libresoc.v:21956.7-21956.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:22244.3-22252.6" + attribute \src "libresoc.v:22292.3-22300.6" wire $1\rst_l_s_rst$next[0:0]$663 - attribute \src "libresoc.v:21912.7-21912.25" + attribute \src "libresoc.v:21960.7-21960.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:22289.3-22297.6" + attribute \src "libresoc.v:22337.3-22345.6" wire width 4 $1\src_l_r_src$next[3:0]$678 - attribute \src "libresoc.v:21928.13-21928.31" + attribute \src "libresoc.v:21976.13-21976.31" wire width 4 $1\src_l_r_src[3:0] - attribute \src "libresoc.v:22280.3-22288.6" + attribute \src "libresoc.v:22328.3-22336.6" wire width 4 $1\src_l_s_src$next[3:0]$675 - attribute \src "libresoc.v:21932.13-21932.31" + attribute \src "libresoc.v:21980.13-21980.31" wire width 4 $1\src_l_s_src[3:0] - attribute \src "libresoc.v:22465.3-22474.6" + attribute \src "libresoc.v:22513.3-22522.6" wire width 64 $1\src_r0$next[63:0]$770 - attribute \src "libresoc.v:21940.14-21940.43" + attribute \src "libresoc.v:21988.14-21988.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:22475.3-22484.6" + attribute \src "libresoc.v:22523.3-22532.6" wire width 64 $1\src_r1$next[63:0]$773 - attribute \src "libresoc.v:21944.14-21944.43" + attribute \src "libresoc.v:21992.14-21992.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:22485.3-22494.6" + attribute \src "libresoc.v:22533.3-22542.6" wire $1\src_r2$next[0:0]$776 - attribute \src "libresoc.v:21948.7-21948.20" + attribute \src "libresoc.v:21996.7-21996.20" wire $1\src_r2[0:0] - attribute \src "libresoc.v:22495.3-22504.6" + attribute \src "libresoc.v:22543.3-22552.6" wire width 2 $1\src_r3$next[1:0]$779 - attribute \src "libresoc.v:21952.13-21952.26" + attribute \src "libresoc.v:22000.13-22000.26" wire width 2 $1\src_r3[1:0] - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire width 64 $2\alu_alu0_alu_op__imm_data__data$next[63:0]$722 - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $2\alu_alu0_alu_op__imm_data__ok$next[0:0]$723 - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $2\alu_alu0_alu_op__oe__oe$next[0:0]$724 - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $2\alu_alu0_alu_op__oe__ok$next[0:0]$725 - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $2\alu_alu0_alu_op__rc__ok$next[0:0]$726 - attribute \src "libresoc.v:22316.3-22354.6" + attribute \src "libresoc.v:22364.3-22402.6" wire $2\alu_alu0_alu_op__rc__rc$next[0:0]$727 - attribute \src "libresoc.v:22355.3-22376.6" + attribute \src "libresoc.v:22403.3-22424.6" wire width 64 $2\data_r0__o$next[63:0]$733 - attribute \src "libresoc.v:22355.3-22376.6" + attribute \src "libresoc.v:22403.3-22424.6" wire $2\data_r0__o_ok$next[0:0]$734 - attribute \src "libresoc.v:22377.3-22398.6" + attribute \src "libresoc.v:22425.3-22446.6" wire width 4 $2\data_r1__cr_a$next[3:0]$741 - attribute \src "libresoc.v:22377.3-22398.6" + attribute \src "libresoc.v:22425.3-22446.6" wire $2\data_r1__cr_a_ok$next[0:0]$742 - attribute \src "libresoc.v:22399.3-22420.6" + attribute \src "libresoc.v:22447.3-22468.6" wire width 2 $2\data_r2__xer_ca$next[1:0]$749 - attribute \src "libresoc.v:22399.3-22420.6" + attribute \src "libresoc.v:22447.3-22468.6" wire $2\data_r2__xer_ca_ok$next[0:0]$750 - attribute \src "libresoc.v:22421.3-22442.6" + attribute \src "libresoc.v:22469.3-22490.6" wire width 2 $2\data_r3__xer_ov$next[1:0]$757 - attribute \src "libresoc.v:22421.3-22442.6" + attribute \src "libresoc.v:22469.3-22490.6" wire $2\data_r3__xer_ov_ok$next[0:0]$758 - attribute \src "libresoc.v:22443.3-22464.6" + attribute \src "libresoc.v:22491.3-22512.6" wire $2\data_r4__xer_so$next[0:0]$765 - attribute \src "libresoc.v:22443.3-22464.6" + attribute \src "libresoc.v:22491.3-22512.6" wire $2\data_r4__xer_so_ok$next[0:0]$766 - attribute \src "libresoc.v:22355.3-22376.6" + attribute \src "libresoc.v:22403.3-22424.6" wire $3\data_r0__o_ok$next[0:0]$735 - attribute \src "libresoc.v:22377.3-22398.6" + attribute \src "libresoc.v:22425.3-22446.6" wire $3\data_r1__cr_a_ok$next[0:0]$743 - attribute \src "libresoc.v:22399.3-22420.6" + attribute \src "libresoc.v:22447.3-22468.6" wire $3\data_r2__xer_ca_ok$next[0:0]$751 - attribute \src "libresoc.v:22421.3-22442.6" + attribute \src "libresoc.v:22469.3-22490.6" wire $3\data_r3__xer_ov_ok$next[0:0]$759 - attribute \src "libresoc.v:22443.3-22464.6" + attribute \src "libresoc.v:22491.3-22512.6" wire $3\data_r4__xer_so_ok$next[0:0]$767 - attribute \src "libresoc.v:21968.18-21968.134" - wire $and$libresoc.v:21968$541_Y - attribute \src "libresoc.v:21969.19-21969.133" - wire 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attribute \src "libresoc.v:21984.19-21984.127" - wire $and$libresoc.v:21984$557_Y - attribute \src "libresoc.v:21985.19-21985.127" - wire $and$libresoc.v:21985$558_Y - attribute \src "libresoc.v:21986.19-21986.127" - wire $and$libresoc.v:21986$559_Y - attribute \src "libresoc.v:21987.19-21987.127" - wire $and$libresoc.v:21987$560_Y - attribute \src "libresoc.v:21988.19-21988.127" - wire $and$libresoc.v:21988$561_Y - attribute \src "libresoc.v:21990.18-21990.98" - wire $and$libresoc.v:21990$563_Y - attribute \src "libresoc.v:21992.18-21992.100" - wire $and$libresoc.v:21992$565_Y - attribute \src "libresoc.v:21993.18-21993.171" - wire width 5 $and$libresoc.v:21993$566_Y - attribute \src "libresoc.v:21995.18-21995.119" - wire width 5 $and$libresoc.v:21995$568_Y - attribute \src "libresoc.v:21998.18-21998.116" - wire $and$libresoc.v:21998$571_Y - attribute \src "libresoc.v:22002.17-22002.123" - wire $and$libresoc.v:22002$575_Y - attribute \src "libresoc.v:22004.18-22004.113" - wire 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$or$libresoc.v:22049$574_Y + attribute \src "libresoc.v:22060.18-22060.122" + wire $or$libresoc.v:22060$585_Y + attribute \src "libresoc.v:22061.18-22061.124" + wire $or$libresoc.v:22061$586_Y + attribute \src "libresoc.v:22062.18-22062.181" + wire width 5 $or$libresoc.v:22062$587_Y + attribute \src "libresoc.v:22063.18-22063.168" + wire width 4 $or$libresoc.v:22063$588_Y + attribute \src "libresoc.v:22067.18-22067.120" + wire width 5 $or$libresoc.v:22067$592_Y + attribute \src "libresoc.v:22076.17-22076.117" + wire width 4 $or$libresoc.v:22076$601_Y + attribute \src "libresoc.v:22015.17-22015.104" + wire $reduce_and$libresoc.v:22015$540_Y + attribute \src "libresoc.v:22044.18-22044.106" + wire $reduce_or$libresoc.v:22044$569_Y + attribute \src "libresoc.v:22047.18-22047.113" + wire $reduce_or$libresoc.v:22047$572_Y + attribute \src "libresoc.v:22048.18-22048.112" + wire $reduce_or$libresoc.v:22048$573_Y + attribute \src "libresoc.v:22073.18-22073.154" + wire $ternary$libresoc.v:22073$598_Y + attribute \src "libresoc.v:22074.18-22074.155" + wire width 64 $ternary$libresoc.v:22074$599_Y + attribute \src "libresoc.v:22075.18-22075.160" + wire $ternary$libresoc.v:22075$600_Y + attribute \src "libresoc.v:22077.18-22077.172" + wire width 64 $ternary$libresoc.v:22077$602_Y + attribute \src "libresoc.v:22078.18-22078.115" + wire width 64 $ternary$libresoc.v:22078$603_Y + attribute \src "libresoc.v:22079.18-22079.125" + wire width 64 $ternary$libresoc.v:22079$604_Y + attribute \src "libresoc.v:22080.18-22080.118" + wire $ternary$libresoc.v:22080$605_Y + attribute \src "libresoc.v:22081.18-22081.118" + wire width 2 $ternary$libresoc.v:22081$606_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -32173,9 +32209,9 @@ module \alu0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 41 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 33 \cr_a_ok @@ -32251,7 +32287,7 @@ module \alu0 wire width 2 output 38 \dest4_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire output 40 \dest5_o - attribute \src "libresoc.v:21285.7-21285.15" + attribute \src "libresoc.v:21333.7-21333.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 29 \o_ok @@ -32488,7 +32524,7 @@ module \alu0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 39 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:21968$541 + cell $and $and$libresoc.v:22016$541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32496,10 +32532,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \alu_alu0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:21968$541_Y + connect \Y $and$libresoc.v:22016$541_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:21969$542 + cell $and $and$libresoc.v:22017$542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32507,10 +32543,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \alu_alu0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:21969$542_Y + connect \Y $and$libresoc.v:22017$542_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:21970$543 + cell $and $and$libresoc.v:22018$543 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -32518,10 +32554,10 @@ module \alu0 parameter \Y_WIDTH 4 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:21970$543_Y + connect \Y $and$libresoc.v:22018$543_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:21973$546 + cell $and $and$libresoc.v:22021$546 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -32529,10 +32565,10 @@ module \alu0 parameter \Y_WIDTH 4 connect \A \$103 connect \B { 2'11 \$107 \$105 } - connect \Y $and$libresoc.v:21973$546_Y + connect \Y $and$libresoc.v:22021$546_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:21975$548 + cell $and $and$libresoc.v:22023$548 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -32540,10 +32576,10 @@ module \alu0 parameter \Y_WIDTH 4 connect \A \$109 connect \B \$111 - connect \Y $and$libresoc.v:21975$548_Y + connect \Y $and$libresoc.v:22023$548_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:21976$549 + cell $and $and$libresoc.v:22024$549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32551,10 +32587,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:21976$549_Y + connect \Y $and$libresoc.v:22024$549_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:21977$550 + cell $and $and$libresoc.v:22025$550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32562,10 +32598,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:21977$550_Y + connect \Y $and$libresoc.v:22025$550_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:21978$551 + cell $and $and$libresoc.v:22026$551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32573,10 +32609,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 - connect \Y $and$libresoc.v:21978$551_Y + connect \Y $and$libresoc.v:22026$551_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:21979$552 + cell $and $and$libresoc.v:22027$552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32584,10 +32620,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:21979$552_Y + connect \Y $and$libresoc.v:22027$552_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:21980$553 + cell $and $and$libresoc.v:22028$553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32595,10 +32631,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:21980$553_Y + connect \Y $and$libresoc.v:22028$553_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:21981$554 + cell $and $and$libresoc.v:22029$554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32606,10 +32642,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:21981$554_Y + connect \Y $and$libresoc.v:22029$554_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:21982$555 + cell $and $and$libresoc.v:22030$555 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32617,10 +32653,10 @@ module \alu0 parameter \Y_WIDTH 5 connect \A \req_l_q_req connect \B { \$115 \$117 \$119 \$121 \$123 } - connect \Y $and$libresoc.v:21982$555_Y + connect \Y $and$libresoc.v:22030$555_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:21983$556 + cell $and $and$libresoc.v:22031$556 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32628,10 +32664,10 @@ module \alu0 parameter \Y_WIDTH 5 connect \A \$125 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:21983$556_Y + connect \Y $and$libresoc.v:22031$556_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:21984$557 + cell $and $and$libresoc.v:22032$557 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32639,10 +32675,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:21984$557_Y + connect \Y $and$libresoc.v:22032$557_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:21985$558 + cell $and $and$libresoc.v:22033$558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32650,10 +32686,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:21985$558_Y + connect \Y $and$libresoc.v:22033$558_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:21986$559 + cell $and $and$libresoc.v:22034$559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32661,10 +32697,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:21986$559_Y + connect \Y $and$libresoc.v:22034$559_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:21987$560 + cell $and $and$libresoc.v:22035$560 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32672,10 +32708,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o - connect \Y $and$libresoc.v:21987$560_Y + connect \Y $and$libresoc.v:22035$560_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:21988$561 + cell $and $and$libresoc.v:22036$561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32683,10 +32719,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [4] connect \B \cu_busy_o - connect \Y $and$libresoc.v:21988$561_Y + connect \Y $and$libresoc.v:22036$561_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:21990$563 + cell $and $and$libresoc.v:22038$563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32694,10 +32730,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$13 - connect \Y $and$libresoc.v:21990$563_Y + connect \Y $and$libresoc.v:22038$563_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:21992$565 + cell $and $and$libresoc.v:22040$565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32705,10 +32741,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$17 - connect \Y $and$libresoc.v:21992$565_Y + connect \Y $and$libresoc.v:22040$565_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:21993$566 + cell $and $and$libresoc.v:22041$566 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32716,10 +32752,10 @@ module \alu0 parameter \Y_WIDTH 5 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:21993$566_Y + connect \Y $and$libresoc.v:22041$566_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:21995$568 + cell $and $and$libresoc.v:22043$568 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32727,10 +32763,10 @@ module \alu0 parameter \Y_WIDTH 5 connect \A \cu_wr__rel_o connect \B \$25 - connect \Y $and$libresoc.v:21995$568_Y + connect \Y $and$libresoc.v:22043$568_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:21998$571 + cell $and $and$libresoc.v:22046$571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32738,10 +32774,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$23 - connect \Y $and$libresoc.v:21998$571_Y + connect \Y $and$libresoc.v:22046$571_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:22002$575 + cell $and $and$libresoc.v:22050$575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32749,10 +32785,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:22002$575_Y + connect \Y $and$libresoc.v:22050$575_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:22004$577 + cell $and $and$libresoc.v:22052$577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32760,10 +32796,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$39 - connect \Y $and$libresoc.v:22004$577_Y + connect \Y $and$libresoc.v:22052$577_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:22005$578 + cell $and $and$libresoc.v:22053$578 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32771,10 +32807,10 @@ module \alu0 parameter \Y_WIDTH 5 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:22005$578_Y + connect \Y $and$libresoc.v:22053$578_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:22007$580 + cell $and $and$libresoc.v:22055$580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32782,10 +32818,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \$41 connect \B \$45 - connect \Y $and$libresoc.v:22007$580_Y + connect \Y $and$libresoc.v:22055$580_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:22009$582 + cell $and $and$libresoc.v:22057$582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32793,10 +32829,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_alu0_n_ready_i - connect \Y $and$libresoc.v:22009$582_Y + connect \Y $and$libresoc.v:22057$582_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:22010$583 + cell $and $and$libresoc.v:22058$583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32804,10 +32840,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \$51 connect \B \alu_alu0_n_valid_o - connect \Y $and$libresoc.v:22010$583_Y + connect \Y $and$libresoc.v:22058$583_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:22011$584 + cell $and $and$libresoc.v:22059$584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32815,10 +32851,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \$53 connect \B \cu_busy_o - connect \Y $and$libresoc.v:22011$584_Y + connect \Y $and$libresoc.v:22059$584_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:22016$589 + cell $and $and$libresoc.v:22064$589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32826,10 +32862,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \alu_alu0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:22016$589_Y + connect \Y $and$libresoc.v:22064$589_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:22017$590 + cell $and $and$libresoc.v:22065$590 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32837,10 +32873,10 @@ module \alu0 parameter \Y_WIDTH 5 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:22017$590_Y + connect \Y $and$libresoc.v:22065$590_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:22020$593 + cell $and $and$libresoc.v:22068$593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32848,10 +32884,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:22020$593_Y + connect \Y $and$libresoc.v:22068$593_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:22021$594 + cell $and $and$libresoc.v:22069$594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32859,10 +32895,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:22021$594_Y + connect \Y $and$libresoc.v:22069$594_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:22022$595 + cell $and $and$libresoc.v:22070$595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32870,10 +32906,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \xer_ca_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:22022$595_Y + connect \Y $and$libresoc.v:22070$595_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:22023$596 + cell $and $and$libresoc.v:22071$596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32881,10 +32917,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \xer_ov_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:22023$596_Y + connect \Y $and$libresoc.v:22071$596_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:22024$597 + cell $and $and$libresoc.v:22072$597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32892,10 +32928,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \xer_so_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:22024$597_Y + connect \Y $and$libresoc.v:22072$597_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:22006$579 + cell $eq $eq$libresoc.v:22054$579 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32903,10 +32939,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \$43 connect \B 1'0 - connect \Y $eq$libresoc.v:22006$579_Y + connect \Y $eq$libresoc.v:22054$579_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:22008$581 + cell $eq $eq$libresoc.v:22056$581 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -32914,82 +32950,82 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:22008$581_Y + connect \Y $eq$libresoc.v:22056$581_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:21971$544 + cell $not $not$libresoc.v:22019$544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_alu0_alu_op__zero_a - connect \Y $not$libresoc.v:21971$544_Y + connect \Y $not$libresoc.v:22019$544_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:21972$545 + cell $not $not$libresoc.v:22020$545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_alu0_alu_op__imm_data__ok - connect \Y $not$libresoc.v:21972$545_Y + connect \Y $not$libresoc.v:22020$545_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:21974$547 + cell $not $not$libresoc.v:22022$547 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:21974$547_Y + connect \Y $not$libresoc.v:22022$547_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:21989$562 + cell $not $not$libresoc.v:22037$562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:21989$562_Y + connect \Y $not$libresoc.v:22037$562_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:21991$564 + cell $not $not$libresoc.v:22039$564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:21991$564_Y + connect \Y $not$libresoc.v:22039$564_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:21994$567 + cell $not $not$libresoc.v:22042$567 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:21994$567_Y + connect \Y $not$libresoc.v:22042$567_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:21997$570 + cell $not $not$libresoc.v:22045$570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:21997$570_Y + connect \Y $not$libresoc.v:22045$570_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:22003$576 + cell $not $not$libresoc.v:22051$576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_alu0_n_ready_i - connect \Y $not$libresoc.v:22003$576_Y + connect \Y $not$libresoc.v:22051$576_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:22018$591 + cell $not $not$libresoc.v:22066$591 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:22018$591_Y + connect \Y $not$libresoc.v:22066$591_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:22001$574 + cell $or $or$libresoc.v:22049$574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -32997,10 +33033,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \$33 connect \B \$35 - connect \Y $or$libresoc.v:22001$574_Y + connect \Y $or$libresoc.v:22049$574_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:22012$585 + cell $or $or$libresoc.v:22060$585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -33008,10 +33044,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:22012$585_Y + connect \Y $or$libresoc.v:22060$585_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:22013$586 + cell $or $or$libresoc.v:22061$586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -33019,10 +33055,10 @@ module \alu0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:22013$586_Y + connect \Y $or$libresoc.v:22061$586_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:22014$587 + cell $or $or$libresoc.v:22062$587 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -33030,10 +33066,10 @@ module \alu0 parameter \Y_WIDTH 5 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:22014$587_Y + connect \Y $or$libresoc.v:22062$587_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:22015$588 + cell $or $or$libresoc.v:22063$588 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -33041,10 +33077,10 @@ module \alu0 parameter \Y_WIDTH 4 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:22015$588_Y + connect \Y $or$libresoc.v:22063$588_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:22019$592 + cell $or $or$libresoc.v:22067$592 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -33052,10 +33088,10 @@ module \alu0 parameter \Y_WIDTH 5 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:22019$592_Y + connect \Y $or$libresoc.v:22067$592_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:22028$601 + cell $or $or$libresoc.v:22076$601 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -33063,106 +33099,106 @@ module \alu0 parameter \Y_WIDTH 4 connect \A \$6 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:22028$601_Y + connect \Y $or$libresoc.v:22076$601_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:21967$540 + cell $reduce_and $reduce_and$libresoc.v:22015$540 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $reduce_and$libresoc.v:21967$540_Y + connect \Y $reduce_and$libresoc.v:22015$540_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:21996$569 + cell $reduce_or $reduce_or$libresoc.v:22044$569 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \$27 - connect \Y $reduce_or$libresoc.v:21996$569_Y + connect \Y $reduce_or$libresoc.v:22044$569_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:21999$572 + cell $reduce_or $reduce_or$libresoc.v:22047$572 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:21999$572_Y + connect \Y $reduce_or$libresoc.v:22047$572_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:22000$573 + cell $reduce_or $reduce_or$libresoc.v:22048$573 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:22000$573_Y + connect \Y $reduce_or$libresoc.v:22048$573_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:22025$598 + cell $mux $ternary$libresoc.v:22073$598 parameter \WIDTH 1 connect \A \src_l_q_src [0] connect \B \opc_l_q_opc connect \S \alu_alu0_alu_op__zero_a - connect \Y $ternary$libresoc.v:22025$598_Y + connect \Y $ternary$libresoc.v:22073$598_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:22026$599 + cell $mux $ternary$libresoc.v:22074$599 parameter \WIDTH 64 connect \A \src1_i connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 connect \S \alu_alu0_alu_op__zero_a - connect \Y $ternary$libresoc.v:22026$599_Y + connect \Y $ternary$libresoc.v:22074$599_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:22027$600 + cell $mux $ternary$libresoc.v:22075$600 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_alu0_alu_op__imm_data__ok - connect \Y $ternary$libresoc.v:22027$600_Y + connect \Y $ternary$libresoc.v:22075$600_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:22029$602 + cell $mux $ternary$libresoc.v:22077$602 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_alu0_alu_op__imm_data__data connect \S \alu_alu0_alu_op__imm_data__ok - connect \Y $ternary$libresoc.v:22029$602_Y + connect \Y $ternary$libresoc.v:22077$602_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:22030$603 + cell $mux $ternary$libresoc.v:22078$603 parameter \WIDTH 64 connect \A \src_r0 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:22030$603_Y + connect \Y $ternary$libresoc.v:22078$603_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:22031$604 + cell $mux $ternary$libresoc.v:22079$604 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm$88 connect \S \src_sel$85 - connect \Y $ternary$libresoc.v:22031$604_Y + connect \Y $ternary$libresoc.v:22079$604_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:22032$605 + cell $mux $ternary$libresoc.v:22080$605 parameter \WIDTH 1 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:22032$605_Y + connect \Y $ternary$libresoc.v:22080$605_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:22033$606 + cell $mux $ternary$libresoc.v:22081$606 parameter \WIDTH 2 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:22033$606_Y + connect \Y $ternary$libresoc.v:22081$606_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:22128.12-22167.4" + attribute \src "libresoc.v:22176.12-22215.4" cell \alu_alu0 \alu_alu0 connect \alu_op__data_len \alu_alu0_alu_op__data_len connect \alu_op__fn_unit \alu_alu0_alu_op__fn_unit @@ -33204,7 +33240,7 @@ module \alu0 connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:22168.9-22174.4" + attribute \src "libresoc.v:22216.9-22222.4" cell \alu_l \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -33213,7 +33249,7 @@ module \alu0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:22175.10-22181.4" + attribute \src "libresoc.v:22223.10-22229.4" cell \alui_l \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -33222,7 +33258,7 @@ module \alu0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:22182.9-22188.4" + attribute \src "libresoc.v:22230.9-22236.4" cell \opc_l \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -33231,7 +33267,7 @@ module \alu0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:22189.9-22195.4" + attribute \src "libresoc.v:22237.9-22243.4" cell \req_l \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -33240,7 +33276,7 @@ module \alu0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:22196.9-22202.4" + attribute \src "libresoc.v:22244.9-22250.4" cell \rok_l \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -33249,7 +33285,7 @@ module \alu0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:22203.9-22208.4" + attribute \src "libresoc.v:22251.9-22256.4" cell \rst_l \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -33257,7 +33293,7 @@ module \alu0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:22209.9-22215.4" + attribute \src "libresoc.v:22257.9-22263.4" cell \src_l \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -33265,727 +33301,727 @@ module \alu0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:21285.7-21285.20" - process $proc$libresoc.v:21285$794 + attribute \src "libresoc.v:21333.7-21333.20" + process $proc$libresoc.v:21333$794 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:21423.7-21423.24" - process $proc$libresoc.v:21423$795 + attribute \src "libresoc.v:21471.7-21471.24" + process $proc$libresoc.v:21471$795 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:21431.13-21431.45" - process $proc$libresoc.v:21431$796 + attribute \src "libresoc.v:21479.13-21479.45" + process $proc$libresoc.v:21479$796 assign { } { } assign $1\alu_alu0_alu_op__data_len[3:0] 4'0000 sync always sync init update \alu_alu0_alu_op__data_len $1\alu_alu0_alu_op__data_len[3:0] end - attribute \src "libresoc.v:21450.14-21450.49" - process $proc$libresoc.v:21450$797 + attribute \src "libresoc.v:21498.14-21498.49" + process $proc$libresoc.v:21498$797 assign { } { } assign $1\alu_alu0_alu_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_alu0_alu_op__fn_unit $1\alu_alu0_alu_op__fn_unit[13:0] end - attribute \src "libresoc.v:21454.14-21454.68" - process $proc$libresoc.v:21454$798 + attribute \src "libresoc.v:21502.14-21502.68" + process $proc$libresoc.v:21502$798 assign { } { } assign $1\alu_alu0_alu_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_alu0_alu_op__imm_data__data $1\alu_alu0_alu_op__imm_data__data[63:0] end - attribute \src "libresoc.v:21458.7-21458.43" - process $proc$libresoc.v:21458$799 + attribute \src "libresoc.v:21506.7-21506.43" + process $proc$libresoc.v:21506$799 assign { } { } assign $1\alu_alu0_alu_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__imm_data__ok $1\alu_alu0_alu_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:21466.13-21466.48" - process $proc$libresoc.v:21466$800 + attribute \src "libresoc.v:21514.13-21514.48" + process $proc$libresoc.v:21514$800 assign { } { } assign $1\alu_alu0_alu_op__input_carry[1:0] 2'00 sync always sync init update \alu_alu0_alu_op__input_carry $1\alu_alu0_alu_op__input_carry[1:0] end - attribute \src "libresoc.v:21470.14-21470.43" - process $proc$libresoc.v:21470$801 + attribute \src "libresoc.v:21518.14-21518.43" + process $proc$libresoc.v:21518$801 assign { } { } assign $1\alu_alu0_alu_op__insn[31:0] 0 sync always sync init update \alu_alu0_alu_op__insn $1\alu_alu0_alu_op__insn[31:0] end - attribute \src "libresoc.v:21549.13-21549.47" - process $proc$libresoc.v:21549$802 + attribute \src "libresoc.v:21597.13-21597.47" + process $proc$libresoc.v:21597$802 assign { } { } assign $1\alu_alu0_alu_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_alu0_alu_op__insn_type $1\alu_alu0_alu_op__insn_type[6:0] end - attribute \src "libresoc.v:21553.7-21553.40" - process $proc$libresoc.v:21553$803 + attribute \src "libresoc.v:21601.7-21601.40" + process $proc$libresoc.v:21601$803 assign { } { } assign $1\alu_alu0_alu_op__invert_in[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__invert_in $1\alu_alu0_alu_op__invert_in[0:0] end - attribute \src "libresoc.v:21557.7-21557.41" - process $proc$libresoc.v:21557$804 + attribute \src "libresoc.v:21605.7-21605.41" + process $proc$libresoc.v:21605$804 assign { } { } assign $1\alu_alu0_alu_op__invert_out[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__invert_out $1\alu_alu0_alu_op__invert_out[0:0] end - attribute \src "libresoc.v:21561.7-21561.39" - process $proc$libresoc.v:21561$805 + attribute \src "libresoc.v:21609.7-21609.39" + process $proc$libresoc.v:21609$805 assign { } { } assign $1\alu_alu0_alu_op__is_32bit[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__is_32bit $1\alu_alu0_alu_op__is_32bit[0:0] end - attribute \src "libresoc.v:21565.7-21565.40" - process $proc$libresoc.v:21565$806 + attribute \src "libresoc.v:21613.7-21613.40" + process $proc$libresoc.v:21613$806 assign { } { } assign $1\alu_alu0_alu_op__is_signed[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__is_signed $1\alu_alu0_alu_op__is_signed[0:0] end - attribute \src "libresoc.v:21569.7-21569.37" - process $proc$libresoc.v:21569$807 + attribute \src "libresoc.v:21617.7-21617.37" + process $proc$libresoc.v:21617$807 assign { } { } assign $1\alu_alu0_alu_op__oe__oe[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__oe__oe $1\alu_alu0_alu_op__oe__oe[0:0] end - attribute \src "libresoc.v:21573.7-21573.37" - process $proc$libresoc.v:21573$808 + attribute \src "libresoc.v:21621.7-21621.37" + process $proc$libresoc.v:21621$808 assign { } { } assign $1\alu_alu0_alu_op__oe__ok[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__oe__ok $1\alu_alu0_alu_op__oe__ok[0:0] end - attribute \src "libresoc.v:21577.7-21577.43" - process $proc$libresoc.v:21577$809 + attribute \src "libresoc.v:21625.7-21625.43" + process $proc$libresoc.v:21625$809 assign { } { } assign $1\alu_alu0_alu_op__output_carry[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__output_carry $1\alu_alu0_alu_op__output_carry[0:0] end - attribute \src "libresoc.v:21581.7-21581.37" - process $proc$libresoc.v:21581$810 + attribute \src "libresoc.v:21629.7-21629.37" + process $proc$libresoc.v:21629$810 assign { } { } assign $1\alu_alu0_alu_op__rc__ok[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__rc__ok $1\alu_alu0_alu_op__rc__ok[0:0] end - attribute \src "libresoc.v:21585.7-21585.37" - process $proc$libresoc.v:21585$811 + attribute \src "libresoc.v:21633.7-21633.37" + process $proc$libresoc.v:21633$811 assign { } { } assign $1\alu_alu0_alu_op__rc__rc[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__rc__rc $1\alu_alu0_alu_op__rc__rc[0:0] end - attribute \src "libresoc.v:21589.7-21589.40" - process $proc$libresoc.v:21589$812 + attribute \src "libresoc.v:21637.7-21637.40" + process $proc$libresoc.v:21637$812 assign { } { } assign $1\alu_alu0_alu_op__write_cr0[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__write_cr0 $1\alu_alu0_alu_op__write_cr0[0:0] end - attribute \src "libresoc.v:21593.7-21593.37" - process $proc$libresoc.v:21593$813 + attribute \src "libresoc.v:21641.7-21641.37" + process $proc$libresoc.v:21641$813 assign { } { } assign $1\alu_alu0_alu_op__zero_a[0:0] 1'0 sync always sync init update \alu_alu0_alu_op__zero_a $1\alu_alu0_alu_op__zero_a[0:0] end - attribute \src "libresoc.v:21625.7-21625.26" - process $proc$libresoc.v:21625$814 + attribute \src "libresoc.v:21673.7-21673.26" + process $proc$libresoc.v:21673$814 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:21633.7-21633.25" - process $proc$libresoc.v:21633$815 + attribute \src "libresoc.v:21681.7-21681.25" + process $proc$libresoc.v:21681$815 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:21645.7-21645.27" - process $proc$libresoc.v:21645$816 + attribute \src "libresoc.v:21693.7-21693.27" + process $proc$libresoc.v:21693$816 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:21679.14-21679.47" - process $proc$libresoc.v:21679$817 + attribute \src "libresoc.v:21727.14-21727.47" + process $proc$libresoc.v:21727$817 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:21683.7-21683.27" - process $proc$libresoc.v:21683$818 + attribute \src "libresoc.v:21731.7-21731.27" + process $proc$libresoc.v:21731$818 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:21687.13-21687.33" - process $proc$libresoc.v:21687$819 + attribute \src "libresoc.v:21735.13-21735.33" + process $proc$libresoc.v:21735$819 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:21691.7-21691.30" - process $proc$libresoc.v:21691$820 + attribute \src "libresoc.v:21739.7-21739.30" + process $proc$libresoc.v:21739$820 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:21695.13-21695.35" - process $proc$libresoc.v:21695$821 + attribute \src "libresoc.v:21743.13-21743.35" + process $proc$libresoc.v:21743$821 assign { } { } assign $1\data_r2__xer_ca[1:0] 2'00 sync always sync init update \data_r2__xer_ca $1\data_r2__xer_ca[1:0] end - attribute \src "libresoc.v:21699.7-21699.32" - process $proc$libresoc.v:21699$822 + attribute \src "libresoc.v:21747.7-21747.32" + process $proc$libresoc.v:21747$822 assign { } { } assign $1\data_r2__xer_ca_ok[0:0] 1'0 sync always sync init update \data_r2__xer_ca_ok $1\data_r2__xer_ca_ok[0:0] end - attribute \src "libresoc.v:21703.13-21703.35" - process $proc$libresoc.v:21703$823 + attribute \src "libresoc.v:21751.13-21751.35" + process $proc$libresoc.v:21751$823 assign { } { } assign $1\data_r3__xer_ov[1:0] 2'00 sync always sync init update \data_r3__xer_ov $1\data_r3__xer_ov[1:0] end - attribute \src "libresoc.v:21707.7-21707.32" - process $proc$libresoc.v:21707$824 + attribute \src "libresoc.v:21755.7-21755.32" + process $proc$libresoc.v:21755$824 assign { } { } assign $1\data_r3__xer_ov_ok[0:0] 1'0 sync always sync init update \data_r3__xer_ov_ok $1\data_r3__xer_ov_ok[0:0] end - attribute \src "libresoc.v:21711.7-21711.29" - process $proc$libresoc.v:21711$825 + attribute \src "libresoc.v:21759.7-21759.29" + process $proc$libresoc.v:21759$825 assign { } { } assign $1\data_r4__xer_so[0:0] 1'0 sync always sync init update \data_r4__xer_so $1\data_r4__xer_so[0:0] end - attribute \src "libresoc.v:21715.7-21715.32" - process $proc$libresoc.v:21715$826 + attribute \src "libresoc.v:21763.7-21763.32" + process $proc$libresoc.v:21763$826 assign { } { } assign $1\data_r4__xer_so_ok[0:0] 1'0 sync always sync init update \data_r4__xer_so_ok $1\data_r4__xer_so_ok[0:0] end - attribute \src "libresoc.v:21738.7-21738.25" - process $proc$libresoc.v:21738$827 + attribute \src "libresoc.v:21786.7-21786.25" + process $proc$libresoc.v:21786$827 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:21742.7-21742.25" - process $proc$libresoc.v:21742$828 + attribute \src "libresoc.v:21790.7-21790.25" + process $proc$libresoc.v:21790$828 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:21876.13-21876.31" - process $proc$libresoc.v:21876$829 + attribute \src "libresoc.v:21924.13-21924.31" + process $proc$libresoc.v:21924$829 assign { } { } assign $1\prev_wr_go[4:0] 5'00000 sync always sync init update \prev_wr_go $1\prev_wr_go[4:0] end - attribute \src "libresoc.v:21884.13-21884.32" - process $proc$libresoc.v:21884$830 + attribute \src "libresoc.v:21932.13-21932.32" + process $proc$libresoc.v:21932$830 assign { } { } assign $1\req_l_r_req[4:0] 5'11111 sync always sync init update \req_l_r_req $1\req_l_r_req[4:0] end - attribute \src "libresoc.v:21888.13-21888.32" - process $proc$libresoc.v:21888$831 + attribute \src "libresoc.v:21936.13-21936.32" + process $proc$libresoc.v:21936$831 assign { } { } assign $1\req_l_s_req[4:0] 5'00000 sync always sync init update \req_l_s_req $1\req_l_s_req[4:0] end - attribute \src "libresoc.v:21900.7-21900.26" - process $proc$libresoc.v:21900$832 + attribute \src "libresoc.v:21948.7-21948.26" + process $proc$libresoc.v:21948$832 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:21904.7-21904.26" - process $proc$libresoc.v:21904$833 + attribute \src "libresoc.v:21952.7-21952.26" + process $proc$libresoc.v:21952$833 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:21908.7-21908.25" - process $proc$libresoc.v:21908$834 + attribute \src "libresoc.v:21956.7-21956.25" + process $proc$libresoc.v:21956$834 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:21912.7-21912.25" - process $proc$libresoc.v:21912$835 + attribute \src "libresoc.v:21960.7-21960.25" + process $proc$libresoc.v:21960$835 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:21928.13-21928.31" - process $proc$libresoc.v:21928$836 + attribute \src "libresoc.v:21976.13-21976.31" + process $proc$libresoc.v:21976$836 assign { } { } assign $1\src_l_r_src[3:0] 4'1111 sync always sync init update \src_l_r_src $1\src_l_r_src[3:0] end - attribute \src "libresoc.v:21932.13-21932.31" - process $proc$libresoc.v:21932$837 + attribute \src "libresoc.v:21980.13-21980.31" + process $proc$libresoc.v:21980$837 assign { } { } assign $1\src_l_s_src[3:0] 4'0000 sync always sync init update \src_l_s_src $1\src_l_s_src[3:0] end - attribute \src "libresoc.v:21940.14-21940.43" - process $proc$libresoc.v:21940$838 + attribute \src "libresoc.v:21988.14-21988.43" + process $proc$libresoc.v:21988$838 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:21944.14-21944.43" - process $proc$libresoc.v:21944$839 + attribute \src "libresoc.v:21992.14-21992.43" + process $proc$libresoc.v:21992$839 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:21948.7-21948.20" - process $proc$libresoc.v:21948$840 + attribute \src "libresoc.v:21996.7-21996.20" + process $proc$libresoc.v:21996$840 assign { } { } assign $1\src_r2[0:0] 1'0 sync always sync init update \src_r2 $1\src_r2[0:0] end - attribute \src "libresoc.v:21952.13-21952.26" - process $proc$libresoc.v:21952$841 + attribute \src "libresoc.v:22000.13-22000.26" + process $proc$libresoc.v:22000$841 assign { } { } assign $1\src_r3[1:0] 2'00 sync always sync init update \src_r3 $1\src_r3[1:0] end - attribute \src "libresoc.v:22034.3-22035.39" - process $proc$libresoc.v:22034$607 + attribute \src "libresoc.v:22082.3-22083.39" + process $proc$libresoc.v:22082$607 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:22036.3-22037.43" - process $proc$libresoc.v:22036$608 + attribute \src "libresoc.v:22084.3-22085.43" + process $proc$libresoc.v:22084$608 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:22038.3-22039.29" - process $proc$libresoc.v:22038$609 + attribute \src "libresoc.v:22086.3-22087.29" + process $proc$libresoc.v:22086$609 assign { } { } assign $0\src_r3[1:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[1:0] end - attribute \src "libresoc.v:22040.3-22041.29" - process $proc$libresoc.v:22040$610 + attribute \src "libresoc.v:22088.3-22089.29" + process $proc$libresoc.v:22088$610 assign { } { } assign $0\src_r2[0:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[0:0] end - attribute \src "libresoc.v:22042.3-22043.29" - process $proc$libresoc.v:22042$611 + attribute \src "libresoc.v:22090.3-22091.29" + process $proc$libresoc.v:22090$611 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:22044.3-22045.29" - process $proc$libresoc.v:22044$612 + attribute \src "libresoc.v:22092.3-22093.29" + process $proc$libresoc.v:22092$612 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:22046.3-22047.47" - process $proc$libresoc.v:22046$613 + attribute \src "libresoc.v:22094.3-22095.47" + process $proc$libresoc.v:22094$613 assign { } { } assign $0\data_r4__xer_so[0:0] \data_r4__xer_so$next sync posedge \coresync_clk update \data_r4__xer_so $0\data_r4__xer_so[0:0] end - attribute \src "libresoc.v:22048.3-22049.53" - process $proc$libresoc.v:22048$614 + attribute \src "libresoc.v:22096.3-22097.53" + process $proc$libresoc.v:22096$614 assign { } { } assign $0\data_r4__xer_so_ok[0:0] \data_r4__xer_so_ok$next sync posedge \coresync_clk update \data_r4__xer_so_ok $0\data_r4__xer_so_ok[0:0] end - attribute \src "libresoc.v:22050.3-22051.47" - process $proc$libresoc.v:22050$615 + attribute \src "libresoc.v:22098.3-22099.47" + process $proc$libresoc.v:22098$615 assign { } { } assign $0\data_r3__xer_ov[1:0] \data_r3__xer_ov$next sync posedge \coresync_clk update \data_r3__xer_ov $0\data_r3__xer_ov[1:0] end - attribute \src "libresoc.v:22052.3-22053.53" - process $proc$libresoc.v:22052$616 + attribute \src "libresoc.v:22100.3-22101.53" + process $proc$libresoc.v:22100$616 assign { } { } assign $0\data_r3__xer_ov_ok[0:0] \data_r3__xer_ov_ok$next sync posedge \coresync_clk update \data_r3__xer_ov_ok $0\data_r3__xer_ov_ok[0:0] end - attribute \src "libresoc.v:22054.3-22055.47" - process $proc$libresoc.v:22054$617 + attribute \src "libresoc.v:22102.3-22103.47" + process $proc$libresoc.v:22102$617 assign { } { } assign $0\data_r2__xer_ca[1:0] \data_r2__xer_ca$next sync posedge \coresync_clk update \data_r2__xer_ca $0\data_r2__xer_ca[1:0] end - attribute \src "libresoc.v:22056.3-22057.53" - process $proc$libresoc.v:22056$618 + attribute \src "libresoc.v:22104.3-22105.53" + process $proc$libresoc.v:22104$618 assign { } { } assign $0\data_r2__xer_ca_ok[0:0] \data_r2__xer_ca_ok$next sync posedge \coresync_clk update \data_r2__xer_ca_ok $0\data_r2__xer_ca_ok[0:0] end - attribute \src "libresoc.v:22058.3-22059.43" - process $proc$libresoc.v:22058$619 + attribute \src "libresoc.v:22106.3-22107.43" + process $proc$libresoc.v:22106$619 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:22060.3-22061.49" - process $proc$libresoc.v:22060$620 + attribute \src "libresoc.v:22108.3-22109.49" + process $proc$libresoc.v:22108$620 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:22062.3-22063.37" - process $proc$libresoc.v:22062$621 + attribute \src "libresoc.v:22110.3-22111.37" + process $proc$libresoc.v:22110$621 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:22064.3-22065.43" - process $proc$libresoc.v:22064$622 + attribute \src "libresoc.v:22112.3-22113.43" + process $proc$libresoc.v:22112$622 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:22066.3-22067.69" - process $proc$libresoc.v:22066$623 + attribute \src "libresoc.v:22114.3-22115.69" + process $proc$libresoc.v:22114$623 assign { } { } assign $0\alu_alu0_alu_op__insn_type[6:0] \alu_alu0_alu_op__insn_type$next sync posedge \coresync_clk update \alu_alu0_alu_op__insn_type $0\alu_alu0_alu_op__insn_type[6:0] end - attribute \src "libresoc.v:22068.3-22069.65" - process $proc$libresoc.v:22068$624 + attribute \src "libresoc.v:22116.3-22117.65" + process $proc$libresoc.v:22116$624 assign { } { } assign $0\alu_alu0_alu_op__fn_unit[13:0] \alu_alu0_alu_op__fn_unit$next sync posedge \coresync_clk update \alu_alu0_alu_op__fn_unit $0\alu_alu0_alu_op__fn_unit[13:0] end - attribute \src "libresoc.v:22070.3-22071.79" - process $proc$libresoc.v:22070$625 + attribute \src "libresoc.v:22118.3-22119.79" + process $proc$libresoc.v:22118$625 assign { } { } assign $0\alu_alu0_alu_op__imm_data__data[63:0] \alu_alu0_alu_op__imm_data__data$next sync posedge \coresync_clk update \alu_alu0_alu_op__imm_data__data $0\alu_alu0_alu_op__imm_data__data[63:0] end - attribute \src "libresoc.v:22072.3-22073.75" - process $proc$libresoc.v:22072$626 + attribute \src "libresoc.v:22120.3-22121.75" + process $proc$libresoc.v:22120$626 assign { } { } assign $0\alu_alu0_alu_op__imm_data__ok[0:0] \alu_alu0_alu_op__imm_data__ok$next sync posedge \coresync_clk update \alu_alu0_alu_op__imm_data__ok $0\alu_alu0_alu_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:22074.3-22075.63" - process $proc$libresoc.v:22074$627 + attribute \src "libresoc.v:22122.3-22123.63" + process $proc$libresoc.v:22122$627 assign { } { } assign $0\alu_alu0_alu_op__rc__rc[0:0] \alu_alu0_alu_op__rc__rc$next sync posedge \coresync_clk update \alu_alu0_alu_op__rc__rc $0\alu_alu0_alu_op__rc__rc[0:0] end - attribute \src "libresoc.v:22076.3-22077.63" - process $proc$libresoc.v:22076$628 + attribute \src "libresoc.v:22124.3-22125.63" + process $proc$libresoc.v:22124$628 assign { } { } assign $0\alu_alu0_alu_op__rc__ok[0:0] \alu_alu0_alu_op__rc__ok$next sync posedge \coresync_clk update \alu_alu0_alu_op__rc__ok $0\alu_alu0_alu_op__rc__ok[0:0] end - attribute \src "libresoc.v:22078.3-22079.63" - process $proc$libresoc.v:22078$629 + attribute \src "libresoc.v:22126.3-22127.63" + process $proc$libresoc.v:22126$629 assign { } { } assign $0\alu_alu0_alu_op__oe__oe[0:0] \alu_alu0_alu_op__oe__oe$next sync posedge \coresync_clk update \alu_alu0_alu_op__oe__oe $0\alu_alu0_alu_op__oe__oe[0:0] end - attribute \src "libresoc.v:22080.3-22081.63" - process $proc$libresoc.v:22080$630 + attribute \src "libresoc.v:22128.3-22129.63" + process $proc$libresoc.v:22128$630 assign { } { } assign $0\alu_alu0_alu_op__oe__ok[0:0] \alu_alu0_alu_op__oe__ok$next sync posedge \coresync_clk update \alu_alu0_alu_op__oe__ok $0\alu_alu0_alu_op__oe__ok[0:0] end - attribute \src "libresoc.v:22082.3-22083.69" - process $proc$libresoc.v:22082$631 + attribute \src "libresoc.v:22130.3-22131.69" + process $proc$libresoc.v:22130$631 assign { } { } assign $0\alu_alu0_alu_op__invert_in[0:0] \alu_alu0_alu_op__invert_in$next sync posedge \coresync_clk update \alu_alu0_alu_op__invert_in $0\alu_alu0_alu_op__invert_in[0:0] end - attribute \src "libresoc.v:22084.3-22085.63" - process $proc$libresoc.v:22084$632 + attribute \src "libresoc.v:22132.3-22133.63" + process $proc$libresoc.v:22132$632 assign { } { } assign $0\alu_alu0_alu_op__zero_a[0:0] \alu_alu0_alu_op__zero_a$next sync posedge \coresync_clk update \alu_alu0_alu_op__zero_a $0\alu_alu0_alu_op__zero_a[0:0] end - attribute \src "libresoc.v:22086.3-22087.71" - process $proc$libresoc.v:22086$633 + attribute \src "libresoc.v:22134.3-22135.71" + process $proc$libresoc.v:22134$633 assign { } { } assign $0\alu_alu0_alu_op__invert_out[0:0] \alu_alu0_alu_op__invert_out$next sync posedge \coresync_clk update \alu_alu0_alu_op__invert_out $0\alu_alu0_alu_op__invert_out[0:0] end - attribute \src "libresoc.v:22088.3-22089.69" - process $proc$libresoc.v:22088$634 + attribute \src "libresoc.v:22136.3-22137.69" + process $proc$libresoc.v:22136$634 assign { } { } assign $0\alu_alu0_alu_op__write_cr0[0:0] \alu_alu0_alu_op__write_cr0$next sync posedge \coresync_clk update \alu_alu0_alu_op__write_cr0 $0\alu_alu0_alu_op__write_cr0[0:0] end - attribute \src "libresoc.v:22090.3-22091.73" - process $proc$libresoc.v:22090$635 + attribute \src "libresoc.v:22138.3-22139.73" + process $proc$libresoc.v:22138$635 assign { } { } assign $0\alu_alu0_alu_op__input_carry[1:0] \alu_alu0_alu_op__input_carry$next sync posedge \coresync_clk update \alu_alu0_alu_op__input_carry $0\alu_alu0_alu_op__input_carry[1:0] end - attribute \src "libresoc.v:22092.3-22093.75" - process $proc$libresoc.v:22092$636 + attribute \src "libresoc.v:22140.3-22141.75" + process $proc$libresoc.v:22140$636 assign { } { } assign $0\alu_alu0_alu_op__output_carry[0:0] \alu_alu0_alu_op__output_carry$next sync posedge \coresync_clk update \alu_alu0_alu_op__output_carry $0\alu_alu0_alu_op__output_carry[0:0] end - attribute \src "libresoc.v:22094.3-22095.67" - process $proc$libresoc.v:22094$637 + attribute \src "libresoc.v:22142.3-22143.67" + process $proc$libresoc.v:22142$637 assign { } { } assign $0\alu_alu0_alu_op__is_32bit[0:0] \alu_alu0_alu_op__is_32bit$next sync posedge \coresync_clk update \alu_alu0_alu_op__is_32bit $0\alu_alu0_alu_op__is_32bit[0:0] end - attribute \src "libresoc.v:22096.3-22097.69" - process $proc$libresoc.v:22096$638 + attribute \src "libresoc.v:22144.3-22145.69" + process $proc$libresoc.v:22144$638 assign { } { } assign $0\alu_alu0_alu_op__is_signed[0:0] \alu_alu0_alu_op__is_signed$next sync posedge \coresync_clk update \alu_alu0_alu_op__is_signed $0\alu_alu0_alu_op__is_signed[0:0] end - attribute \src "libresoc.v:22098.3-22099.67" - process $proc$libresoc.v:22098$639 + attribute \src "libresoc.v:22146.3-22147.67" + process $proc$libresoc.v:22146$639 assign { } { } assign $0\alu_alu0_alu_op__data_len[3:0] \alu_alu0_alu_op__data_len$next sync posedge \coresync_clk update \alu_alu0_alu_op__data_len $0\alu_alu0_alu_op__data_len[3:0] end - attribute \src "libresoc.v:22100.3-22101.59" - process $proc$libresoc.v:22100$640 + attribute \src "libresoc.v:22148.3-22149.59" + process $proc$libresoc.v:22148$640 assign { } { } assign $0\alu_alu0_alu_op__insn[31:0] \alu_alu0_alu_op__insn$next sync posedge \coresync_clk update \alu_alu0_alu_op__insn $0\alu_alu0_alu_op__insn[31:0] end - attribute \src "libresoc.v:22102.3-22103.39" - process $proc$libresoc.v:22102$641 + attribute \src "libresoc.v:22150.3-22151.39" + process $proc$libresoc.v:22150$641 assign { } { } assign $0\req_l_r_req[4:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[4:0] end - attribute \src "libresoc.v:22104.3-22105.39" - process $proc$libresoc.v:22104$642 + attribute \src "libresoc.v:22152.3-22153.39" + process $proc$libresoc.v:22152$642 assign { } { } assign $0\req_l_s_req[4:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[4:0] end - attribute \src "libresoc.v:22106.3-22107.39" - process $proc$libresoc.v:22106$643 + attribute \src "libresoc.v:22154.3-22155.39" + process $proc$libresoc.v:22154$643 assign { } { } assign $0\src_l_r_src[3:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[3:0] end - attribute \src "libresoc.v:22108.3-22109.39" - process $proc$libresoc.v:22108$644 + attribute \src "libresoc.v:22156.3-22157.39" + process $proc$libresoc.v:22156$644 assign { } { } assign $0\src_l_s_src[3:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[3:0] end - attribute \src "libresoc.v:22110.3-22111.39" - process $proc$libresoc.v:22110$645 + attribute \src "libresoc.v:22158.3-22159.39" + process $proc$libresoc.v:22158$645 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:22112.3-22113.39" - process $proc$libresoc.v:22112$646 + attribute \src "libresoc.v:22160.3-22161.39" + process $proc$libresoc.v:22160$646 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:22114.3-22115.39" - process $proc$libresoc.v:22114$647 + attribute \src "libresoc.v:22162.3-22163.39" + process $proc$libresoc.v:22162$647 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:22116.3-22117.39" - process $proc$libresoc.v:22116$648 + attribute \src "libresoc.v:22164.3-22165.39" + process $proc$libresoc.v:22164$648 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:22118.3-22119.41" - process $proc$libresoc.v:22118$649 + attribute \src "libresoc.v:22166.3-22167.41" + process $proc$libresoc.v:22166$649 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:22120.3-22121.41" - process $proc$libresoc.v:22120$650 + attribute \src "libresoc.v:22168.3-22169.41" + process $proc$libresoc.v:22168$650 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:22122.3-22123.37" - process $proc$libresoc.v:22122$651 + attribute \src "libresoc.v:22170.3-22171.37" + process $proc$libresoc.v:22170$651 assign { } { } assign $0\prev_wr_go[4:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[4:0] end - attribute \src "libresoc.v:22124.3-22125.40" - process $proc$libresoc.v:22124$652 + attribute \src "libresoc.v:22172.3-22173.40" + process $proc$libresoc.v:22172$652 assign { } { } assign $0\alu_done_dly[0:0] \alu_alu0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:22126.3-22127.25" - process $proc$libresoc.v:22126$653 + attribute \src "libresoc.v:22174.3-22175.25" + process $proc$libresoc.v:22174$653 assign { } { } assign $0\all_rd_dly[0:0] \$11 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:22216.3-22225.6" - process $proc$libresoc.v:22216$654 + attribute \src "libresoc.v:22264.3-22273.6" + process $proc$libresoc.v:22264$654 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:22217.5-22217.29" + attribute \src "libresoc.v:22265.5-22265.29" switch \initial - attribute \src "libresoc.v:22217.9-22217.17" + attribute \src "libresoc.v:22265.9-22265.17" case 1'1 case end @@ -34001,14 +34037,14 @@ module \alu0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:22226.3-22234.6" - process $proc$libresoc.v:22226$655 + attribute \src "libresoc.v:22274.3-22282.6" + process $proc$libresoc.v:22274$655 assign { } { } assign { } { } assign $0\rok_l_s_rdok$next[0:0]$656 $1\rok_l_s_rdok$next[0:0]$657 - attribute \src "libresoc.v:22227.5-22227.29" + attribute \src "libresoc.v:22275.5-22275.29" switch \initial - attribute \src "libresoc.v:22227.9-22227.17" + attribute \src "libresoc.v:22275.9-22275.17" case 1'1 case end @@ -34024,14 +34060,14 @@ module \alu0 sync always update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$656 end - attribute \src "libresoc.v:22235.3-22243.6" - process $proc$libresoc.v:22235$658 + attribute \src "libresoc.v:22283.3-22291.6" + process $proc$libresoc.v:22283$658 assign { } { } assign { } { } assign $0\rok_l_r_rdok$next[0:0]$659 $1\rok_l_r_rdok$next[0:0]$660 - attribute \src "libresoc.v:22236.5-22236.29" + attribute \src "libresoc.v:22284.5-22284.29" switch \initial - attribute \src "libresoc.v:22236.9-22236.17" + attribute \src "libresoc.v:22284.9-22284.17" case 1'1 case end @@ -34047,14 +34083,14 @@ module \alu0 sync always update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$659 end - attribute \src "libresoc.v:22244.3-22252.6" - process $proc$libresoc.v:22244$661 + attribute \src "libresoc.v:22292.3-22300.6" + process $proc$libresoc.v:22292$661 assign { } { } assign { } { } assign $0\rst_l_s_rst$next[0:0]$662 $1\rst_l_s_rst$next[0:0]$663 - attribute \src "libresoc.v:22245.5-22245.29" + attribute \src "libresoc.v:22293.5-22293.29" switch \initial - attribute \src "libresoc.v:22245.9-22245.17" + attribute \src "libresoc.v:22293.9-22293.17" case 1'1 case end @@ -34070,14 +34106,14 @@ module \alu0 sync always update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$662 end - attribute \src "libresoc.v:22253.3-22261.6" - process $proc$libresoc.v:22253$664 + attribute \src "libresoc.v:22301.3-22309.6" + process $proc$libresoc.v:22301$664 assign { } { } assign { } { } assign $0\rst_l_r_rst$next[0:0]$665 $1\rst_l_r_rst$next[0:0]$666 - attribute \src "libresoc.v:22254.5-22254.29" + attribute \src "libresoc.v:22302.5-22302.29" switch \initial - attribute \src "libresoc.v:22254.9-22254.17" + attribute \src "libresoc.v:22302.9-22302.17" case 1'1 case end @@ -34093,14 +34129,14 @@ module \alu0 sync always update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$665 end - attribute \src "libresoc.v:22262.3-22270.6" - process $proc$libresoc.v:22262$667 + attribute \src "libresoc.v:22310.3-22318.6" + process $proc$libresoc.v:22310$667 assign { } { } assign { } { } assign $0\opc_l_s_opc$next[0:0]$668 $1\opc_l_s_opc$next[0:0]$669 - attribute \src "libresoc.v:22263.5-22263.29" + attribute \src "libresoc.v:22311.5-22311.29" switch \initial - attribute \src "libresoc.v:22263.9-22263.17" + attribute \src "libresoc.v:22311.9-22311.17" case 1'1 case end @@ -34116,14 +34152,14 @@ module \alu0 sync always update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$668 end - attribute \src "libresoc.v:22271.3-22279.6" - process $proc$libresoc.v:22271$670 + attribute \src "libresoc.v:22319.3-22327.6" + process $proc$libresoc.v:22319$670 assign { } { } assign { } { } assign $0\opc_l_r_opc$next[0:0]$671 $1\opc_l_r_opc$next[0:0]$672 - attribute \src "libresoc.v:22272.5-22272.29" + attribute \src "libresoc.v:22320.5-22320.29" switch \initial - attribute \src "libresoc.v:22272.9-22272.17" + attribute \src "libresoc.v:22320.9-22320.17" case 1'1 case end @@ -34139,14 +34175,14 @@ module \alu0 sync always update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$671 end - attribute \src "libresoc.v:22280.3-22288.6" - process $proc$libresoc.v:22280$673 + attribute \src "libresoc.v:22328.3-22336.6" + process $proc$libresoc.v:22328$673 assign { } { } assign { } { } assign $0\src_l_s_src$next[3:0]$674 $1\src_l_s_src$next[3:0]$675 - attribute \src "libresoc.v:22281.5-22281.29" + attribute \src "libresoc.v:22329.5-22329.29" switch \initial - attribute \src "libresoc.v:22281.9-22281.17" + attribute \src "libresoc.v:22329.9-22329.17" case 1'1 case end @@ -34162,14 +34198,14 @@ module \alu0 sync always update \src_l_s_src$next $0\src_l_s_src$next[3:0]$674 end - attribute \src "libresoc.v:22289.3-22297.6" - process $proc$libresoc.v:22289$676 + attribute \src "libresoc.v:22337.3-22345.6" + process $proc$libresoc.v:22337$676 assign { } { } assign { } { } assign $0\src_l_r_src$next[3:0]$677 $1\src_l_r_src$next[3:0]$678 - attribute \src "libresoc.v:22290.5-22290.29" + attribute \src "libresoc.v:22338.5-22338.29" switch \initial - attribute \src "libresoc.v:22290.9-22290.17" + attribute \src "libresoc.v:22338.9-22338.17" case 1'1 case end @@ -34185,14 +34221,14 @@ module \alu0 sync always update \src_l_r_src$next $0\src_l_r_src$next[3:0]$677 end - attribute \src "libresoc.v:22298.3-22306.6" - process $proc$libresoc.v:22298$679 + attribute \src "libresoc.v:22346.3-22354.6" + process $proc$libresoc.v:22346$679 assign { } { } assign { } { } assign $0\req_l_s_req$next[4:0]$680 $1\req_l_s_req$next[4:0]$681 - attribute \src "libresoc.v:22299.5-22299.29" + attribute \src "libresoc.v:22347.5-22347.29" switch \initial - attribute \src "libresoc.v:22299.9-22299.17" + attribute \src "libresoc.v:22347.9-22347.17" case 1'1 case end @@ -34208,14 +34244,14 @@ module \alu0 sync always update \req_l_s_req$next $0\req_l_s_req$next[4:0]$680 end - attribute \src "libresoc.v:22307.3-22315.6" - process $proc$libresoc.v:22307$682 + attribute \src "libresoc.v:22355.3-22363.6" + process $proc$libresoc.v:22355$682 assign { } { } assign { } { } assign $0\req_l_r_req$next[4:0]$683 $1\req_l_r_req$next[4:0]$684 - attribute \src "libresoc.v:22308.5-22308.29" + attribute \src "libresoc.v:22356.5-22356.29" switch \initial - attribute \src "libresoc.v:22308.9-22308.17" + attribute \src "libresoc.v:22356.9-22356.17" case 1'1 case end @@ -34231,8 +34267,8 @@ module \alu0 sync always update \req_l_r_req$next $0\req_l_r_req$next[4:0]$683 end - attribute \src "libresoc.v:22316.3-22354.6" - process $proc$libresoc.v:22316$685 + attribute \src "libresoc.v:22364.3-22402.6" + process $proc$libresoc.v:22364$685 assign { } { } assign { } { } assign { } { } @@ -34293,9 +34329,9 @@ module \alu0 assign $0\alu_alu0_alu_op__oe__ok$next[0:0]$698 $2\alu_alu0_alu_op__oe__ok$next[0:0]$725 assign $0\alu_alu0_alu_op__rc__ok$next[0:0]$700 $2\alu_alu0_alu_op__rc__ok$next[0:0]$726 assign $0\alu_alu0_alu_op__rc__rc$next[0:0]$701 $2\alu_alu0_alu_op__rc__rc$next[0:0]$727 - attribute \src "libresoc.v:22317.5-22317.29" + attribute \src "libresoc.v:22365.5-22365.29" switch \initial - attribute \src "libresoc.v:22317.9-22317.17" + attribute \src "libresoc.v:22365.9-22365.17" case 1'1 case end @@ -34386,8 +34422,8 @@ module \alu0 update \alu_alu0_alu_op__write_cr0$next $0\alu_alu0_alu_op__write_cr0$next[0:0]$702 update \alu_alu0_alu_op__zero_a$next $0\alu_alu0_alu_op__zero_a$next[0:0]$703 end - attribute \src "libresoc.v:22355.3-22376.6" - process $proc$libresoc.v:22355$728 + attribute \src "libresoc.v:22403.3-22424.6" + process $proc$libresoc.v:22403$728 assign { } { } assign { } { } assign { } { } @@ -34397,9 +34433,9 @@ module \alu0 assign $0\data_r0__o$next[63:0]$729 $2\data_r0__o$next[63:0]$733 assign { } { } assign $0\data_r0__o_ok$next[0:0]$730 $3\data_r0__o_ok$next[0:0]$735 - attribute \src "libresoc.v:22356.5-22356.29" + attribute \src "libresoc.v:22404.5-22404.29" switch \initial - attribute \src "libresoc.v:22356.9-22356.17" + attribute \src "libresoc.v:22404.9-22404.17" case 1'1 case end @@ -34438,8 +34474,8 @@ module \alu0 update \data_r0__o$next $0\data_r0__o$next[63:0]$729 update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$730 end - attribute \src "libresoc.v:22377.3-22398.6" - process $proc$libresoc.v:22377$736 + attribute \src "libresoc.v:22425.3-22446.6" + process $proc$libresoc.v:22425$736 assign { } { } assign { } { } assign { } { } @@ -34449,9 +34485,9 @@ module \alu0 assign $0\data_r1__cr_a$next[3:0]$737 $2\data_r1__cr_a$next[3:0]$741 assign { } { } assign $0\data_r1__cr_a_ok$next[0:0]$738 $3\data_r1__cr_a_ok$next[0:0]$743 - attribute \src "libresoc.v:22378.5-22378.29" + attribute \src "libresoc.v:22426.5-22426.29" switch \initial - attribute \src "libresoc.v:22378.9-22378.17" + attribute \src "libresoc.v:22426.9-22426.17" case 1'1 case end @@ -34490,8 +34526,8 @@ module \alu0 update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$737 update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$738 end - attribute \src "libresoc.v:22399.3-22420.6" - process $proc$libresoc.v:22399$744 + attribute \src "libresoc.v:22447.3-22468.6" + process $proc$libresoc.v:22447$744 assign { } { } assign { } { } assign { } { } @@ -34501,9 +34537,9 @@ module \alu0 assign $0\data_r2__xer_ca$next[1:0]$745 $2\data_r2__xer_ca$next[1:0]$749 assign { } { } assign $0\data_r2__xer_ca_ok$next[0:0]$746 $3\data_r2__xer_ca_ok$next[0:0]$751 - attribute \src "libresoc.v:22400.5-22400.29" + attribute \src "libresoc.v:22448.5-22448.29" switch \initial - attribute \src "libresoc.v:22400.9-22400.17" + attribute \src "libresoc.v:22448.9-22448.17" case 1'1 case end @@ -34542,8 +34578,8 @@ module \alu0 update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$745 update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$746 end - attribute \src "libresoc.v:22421.3-22442.6" - process $proc$libresoc.v:22421$752 + attribute \src "libresoc.v:22469.3-22490.6" + process $proc$libresoc.v:22469$752 assign { } { } assign { } { } assign { } { } @@ -34553,9 +34589,9 @@ module \alu0 assign $0\data_r3__xer_ov$next[1:0]$753 $2\data_r3__xer_ov$next[1:0]$757 assign { } { } assign $0\data_r3__xer_ov_ok$next[0:0]$754 $3\data_r3__xer_ov_ok$next[0:0]$759 - attribute \src "libresoc.v:22422.5-22422.29" + attribute \src "libresoc.v:22470.5-22470.29" switch \initial - attribute \src "libresoc.v:22422.9-22422.17" + attribute \src "libresoc.v:22470.9-22470.17" case 1'1 case end @@ -34594,8 +34630,8 @@ module \alu0 update \data_r3__xer_ov$next $0\data_r3__xer_ov$next[1:0]$753 update \data_r3__xer_ov_ok$next $0\data_r3__xer_ov_ok$next[0:0]$754 end - attribute \src "libresoc.v:22443.3-22464.6" - process $proc$libresoc.v:22443$760 + attribute \src "libresoc.v:22491.3-22512.6" + process $proc$libresoc.v:22491$760 assign { } { } assign { } { } assign { } { } @@ -34605,9 +34641,9 @@ module \alu0 assign $0\data_r4__xer_so$next[0:0]$761 $2\data_r4__xer_so$next[0:0]$765 assign { } { } assign $0\data_r4__xer_so_ok$next[0:0]$762 $3\data_r4__xer_so_ok$next[0:0]$767 - attribute \src "libresoc.v:22444.5-22444.29" + attribute \src "libresoc.v:22492.5-22492.29" switch \initial - attribute \src "libresoc.v:22444.9-22444.17" + attribute \src "libresoc.v:22492.9-22492.17" case 1'1 case end @@ -34646,14 +34682,14 @@ module \alu0 update \data_r4__xer_so$next $0\data_r4__xer_so$next[0:0]$761 update \data_r4__xer_so_ok$next $0\data_r4__xer_so_ok$next[0:0]$762 end - attribute \src "libresoc.v:22465.3-22474.6" - process $proc$libresoc.v:22465$768 + attribute \src "libresoc.v:22513.3-22522.6" + process $proc$libresoc.v:22513$768 assign { } { } assign { } { } assign $0\src_r0$next[63:0]$769 $1\src_r0$next[63:0]$770 - attribute \src "libresoc.v:22466.5-22466.29" + attribute \src "libresoc.v:22514.5-22514.29" switch \initial - attribute \src "libresoc.v:22466.9-22466.17" + attribute \src "libresoc.v:22514.9-22514.17" case 1'1 case end @@ -34669,14 +34705,14 @@ module \alu0 sync always update \src_r0$next $0\src_r0$next[63:0]$769 end - attribute \src "libresoc.v:22475.3-22484.6" - process $proc$libresoc.v:22475$771 + attribute \src "libresoc.v:22523.3-22532.6" + process $proc$libresoc.v:22523$771 assign { } { } assign { } { } assign $0\src_r1$next[63:0]$772 $1\src_r1$next[63:0]$773 - attribute \src "libresoc.v:22476.5-22476.29" + attribute \src "libresoc.v:22524.5-22524.29" switch \initial - attribute \src "libresoc.v:22476.9-22476.17" + attribute \src "libresoc.v:22524.9-22524.17" case 1'1 case end @@ -34692,14 +34728,14 @@ module \alu0 sync always update \src_r1$next $0\src_r1$next[63:0]$772 end - attribute \src "libresoc.v:22485.3-22494.6" - process $proc$libresoc.v:22485$774 + attribute \src "libresoc.v:22533.3-22542.6" + process $proc$libresoc.v:22533$774 assign { } { } assign { } { } assign $0\src_r2$next[0:0]$775 $1\src_r2$next[0:0]$776 - attribute \src "libresoc.v:22486.5-22486.29" + attribute \src "libresoc.v:22534.5-22534.29" switch \initial - attribute \src "libresoc.v:22486.9-22486.17" + attribute \src "libresoc.v:22534.9-22534.17" case 1'1 case end @@ -34715,14 +34751,14 @@ module \alu0 sync always update \src_r2$next $0\src_r2$next[0:0]$775 end - attribute \src "libresoc.v:22495.3-22504.6" - process $proc$libresoc.v:22495$777 + attribute \src "libresoc.v:22543.3-22552.6" + process $proc$libresoc.v:22543$777 assign { } { } assign { } { } assign $0\src_r3$next[1:0]$778 $1\src_r3$next[1:0]$779 - attribute \src "libresoc.v:22496.5-22496.29" + attribute \src "libresoc.v:22544.5-22544.29" switch \initial - attribute \src "libresoc.v:22496.9-22496.17" + attribute \src "libresoc.v:22544.9-22544.17" case 1'1 case end @@ -34738,14 +34774,14 @@ module \alu0 sync always update \src_r3$next $0\src_r3$next[1:0]$778 end - attribute \src "libresoc.v:22505.3-22513.6" - process $proc$libresoc.v:22505$780 + attribute \src "libresoc.v:22553.3-22561.6" + process $proc$libresoc.v:22553$780 assign { } { } assign { } { } assign $0\alui_l_r_alui$next[0:0]$781 $1\alui_l_r_alui$next[0:0]$782 - attribute \src "libresoc.v:22506.5-22506.29" + attribute \src "libresoc.v:22554.5-22554.29" switch \initial - attribute \src "libresoc.v:22506.9-22506.17" + attribute \src "libresoc.v:22554.9-22554.17" case 1'1 case end @@ -34761,14 +34797,14 @@ module \alu0 sync always update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$781 end - attribute \src "libresoc.v:22514.3-22522.6" - process $proc$libresoc.v:22514$783 + attribute \src "libresoc.v:22562.3-22570.6" + process $proc$libresoc.v:22562$783 assign { } { } assign { } { } assign $0\alu_l_r_alu$next[0:0]$784 $1\alu_l_r_alu$next[0:0]$785 - attribute \src "libresoc.v:22515.5-22515.29" + attribute \src "libresoc.v:22563.5-22563.29" switch \initial - attribute \src "libresoc.v:22515.9-22515.17" + attribute \src "libresoc.v:22563.9-22563.17" case 1'1 case end @@ -34784,14 +34820,14 @@ module \alu0 sync always update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$784 end - attribute \src "libresoc.v:22523.3-22532.6" - process $proc$libresoc.v:22523$786 + attribute \src "libresoc.v:22571.3-22580.6" + process $proc$libresoc.v:22571$786 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:22524.5-22524.29" + attribute \src "libresoc.v:22572.5-22572.29" switch \initial - attribute \src "libresoc.v:22524.9-22524.17" + attribute \src "libresoc.v:22572.9-22572.17" case 1'1 case end @@ -34807,14 +34843,14 @@ module \alu0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:22533.3-22542.6" - process $proc$libresoc.v:22533$787 + attribute \src "libresoc.v:22581.3-22590.6" + process $proc$libresoc.v:22581$787 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:22534.5-22534.29" + attribute \src "libresoc.v:22582.5-22582.29" switch \initial - attribute \src "libresoc.v:22534.9-22534.17" + attribute \src "libresoc.v:22582.9-22582.17" case 1'1 case end @@ -34830,14 +34866,14 @@ module \alu0 sync always update \dest2_o $0\dest2_o[3:0] end - attribute \src "libresoc.v:22543.3-22552.6" - process $proc$libresoc.v:22543$788 + attribute \src "libresoc.v:22591.3-22600.6" + process $proc$libresoc.v:22591$788 assign { } { } assign { } { } assign $0\dest3_o[1:0] $1\dest3_o[1:0] - attribute \src "libresoc.v:22544.5-22544.29" + attribute \src "libresoc.v:22592.5-22592.29" switch \initial - attribute \src "libresoc.v:22544.9-22544.17" + attribute \src "libresoc.v:22592.9-22592.17" case 1'1 case end @@ -34853,14 +34889,14 @@ module \alu0 sync always update \dest3_o $0\dest3_o[1:0] end - attribute \src "libresoc.v:22553.3-22562.6" - process $proc$libresoc.v:22553$789 + attribute \src "libresoc.v:22601.3-22610.6" + process $proc$libresoc.v:22601$789 assign { } { } assign { } { } assign $0\dest4_o[1:0] $1\dest4_o[1:0] - attribute \src "libresoc.v:22554.5-22554.29" + attribute \src "libresoc.v:22602.5-22602.29" switch \initial - attribute \src "libresoc.v:22554.9-22554.17" + attribute \src "libresoc.v:22602.9-22602.17" case 1'1 case end @@ -34876,14 +34912,14 @@ module \alu0 sync always update \dest4_o $0\dest4_o[1:0] end - attribute \src "libresoc.v:22563.3-22572.6" - process $proc$libresoc.v:22563$790 + attribute \src "libresoc.v:22611.3-22620.6" + process $proc$libresoc.v:22611$790 assign { } { } assign { } { } assign $0\dest5_o[0:0] $1\dest5_o[0:0] - attribute \src "libresoc.v:22564.5-22564.29" + attribute \src "libresoc.v:22612.5-22612.29" switch \initial - attribute \src "libresoc.v:22564.9-22564.17" + attribute \src "libresoc.v:22612.9-22612.17" case 1'1 case end @@ -34899,14 +34935,14 @@ module \alu0 sync always update \dest5_o $0\dest5_o[0:0] end - attribute \src "libresoc.v:22573.3-22581.6" - process $proc$libresoc.v:22573$791 + attribute \src "libresoc.v:22621.3-22629.6" + process $proc$libresoc.v:22621$791 assign { } { } assign { } { } assign $0\prev_wr_go$next[4:0]$792 $1\prev_wr_go$next[4:0]$793 - attribute \src "libresoc.v:22574.5-22574.29" + attribute \src "libresoc.v:22622.5-22622.29" switch \initial - attribute \src "libresoc.v:22574.9-22574.17" + attribute \src "libresoc.v:22622.9-22622.17" case 1'1 case end @@ -34922,73 +34958,73 @@ module \alu0 sync always update \prev_wr_go$next $0\prev_wr_go$next[4:0]$792 end - connect \$5 $reduce_and$libresoc.v:21967$540_Y - connect \$99 $and$libresoc.v:21968$541_Y - connect \$101 $and$libresoc.v:21969$542_Y - connect \$103 $and$libresoc.v:21970$543_Y - connect \$105 $not$libresoc.v:21971$544_Y - connect \$107 $not$libresoc.v:21972$545_Y - connect \$109 $and$libresoc.v:21973$546_Y - connect \$111 $not$libresoc.v:21974$547_Y - connect \$113 $and$libresoc.v:21975$548_Y - connect \$115 $and$libresoc.v:21976$549_Y - connect \$117 $and$libresoc.v:21977$550_Y - connect \$11 $and$libresoc.v:21978$551_Y - connect \$119 $and$libresoc.v:21979$552_Y - connect \$121 $and$libresoc.v:21980$553_Y - connect \$123 $and$libresoc.v:21981$554_Y - connect \$125 $and$libresoc.v:21982$555_Y - connect \$127 $and$libresoc.v:21983$556_Y - connect \$129 $and$libresoc.v:21984$557_Y - connect \$131 $and$libresoc.v:21985$558_Y - connect \$133 $and$libresoc.v:21986$559_Y - connect \$135 $and$libresoc.v:21987$560_Y - connect \$137 $and$libresoc.v:21988$561_Y - connect \$13 $not$libresoc.v:21989$562_Y - connect \$15 $and$libresoc.v:21990$563_Y - connect \$17 $not$libresoc.v:21991$564_Y - connect \$19 $and$libresoc.v:21992$565_Y - connect \$21 $and$libresoc.v:21993$566_Y - connect \$25 $not$libresoc.v:21994$567_Y - connect \$27 $and$libresoc.v:21995$568_Y - connect \$24 $reduce_or$libresoc.v:21996$569_Y - connect \$23 $not$libresoc.v:21997$570_Y - connect \$31 $and$libresoc.v:21998$571_Y - connect \$33 $reduce_or$libresoc.v:21999$572_Y - connect \$35 $reduce_or$libresoc.v:22000$573_Y - connect \$37 $or$libresoc.v:22001$574_Y - connect \$3 $and$libresoc.v:22002$575_Y - connect \$39 $not$libresoc.v:22003$576_Y - connect \$41 $and$libresoc.v:22004$577_Y - connect \$43 $and$libresoc.v:22005$578_Y - connect \$45 $eq$libresoc.v:22006$579_Y - connect \$47 $and$libresoc.v:22007$580_Y - connect \$49 $eq$libresoc.v:22008$581_Y - connect \$51 $and$libresoc.v:22009$582_Y - connect \$53 $and$libresoc.v:22010$583_Y - connect \$55 $and$libresoc.v:22011$584_Y - connect \$57 $or$libresoc.v:22012$585_Y - connect \$59 $or$libresoc.v:22013$586_Y - connect \$61 $or$libresoc.v:22014$587_Y - connect \$63 $or$libresoc.v:22015$588_Y - connect \$65 $and$libresoc.v:22016$589_Y - connect \$67 $and$libresoc.v:22017$590_Y - connect \$6 $not$libresoc.v:22018$591_Y - connect \$69 $or$libresoc.v:22019$592_Y - connect \$71 $and$libresoc.v:22020$593_Y - connect \$73 $and$libresoc.v:22021$594_Y - connect \$75 $and$libresoc.v:22022$595_Y - connect \$77 $and$libresoc.v:22023$596_Y - connect \$79 $and$libresoc.v:22024$597_Y - connect \$81 $ternary$libresoc.v:22025$598_Y - connect \$83 $ternary$libresoc.v:22026$599_Y - connect \$86 $ternary$libresoc.v:22027$600_Y - connect \$8 $or$libresoc.v:22028$601_Y - connect \$89 $ternary$libresoc.v:22029$602_Y - connect \$91 $ternary$libresoc.v:22030$603_Y - connect \$93 $ternary$libresoc.v:22031$604_Y - connect \$95 $ternary$libresoc.v:22032$605_Y - connect \$97 $ternary$libresoc.v:22033$606_Y + connect \$5 $reduce_and$libresoc.v:22015$540_Y + connect \$99 $and$libresoc.v:22016$541_Y + connect \$101 $and$libresoc.v:22017$542_Y + connect \$103 $and$libresoc.v:22018$543_Y + connect \$105 $not$libresoc.v:22019$544_Y + connect \$107 $not$libresoc.v:22020$545_Y + connect \$109 $and$libresoc.v:22021$546_Y + connect \$111 $not$libresoc.v:22022$547_Y + connect \$113 $and$libresoc.v:22023$548_Y + connect \$115 $and$libresoc.v:22024$549_Y + connect \$117 $and$libresoc.v:22025$550_Y + connect \$11 $and$libresoc.v:22026$551_Y + connect \$119 $and$libresoc.v:22027$552_Y + connect \$121 $and$libresoc.v:22028$553_Y + connect \$123 $and$libresoc.v:22029$554_Y + connect \$125 $and$libresoc.v:22030$555_Y + connect \$127 $and$libresoc.v:22031$556_Y + connect \$129 $and$libresoc.v:22032$557_Y + connect \$131 $and$libresoc.v:22033$558_Y + connect \$133 $and$libresoc.v:22034$559_Y + connect \$135 $and$libresoc.v:22035$560_Y + connect \$137 $and$libresoc.v:22036$561_Y + connect \$13 $not$libresoc.v:22037$562_Y + connect \$15 $and$libresoc.v:22038$563_Y + connect \$17 $not$libresoc.v:22039$564_Y + connect \$19 $and$libresoc.v:22040$565_Y + connect \$21 $and$libresoc.v:22041$566_Y + connect \$25 $not$libresoc.v:22042$567_Y + connect \$27 $and$libresoc.v:22043$568_Y + connect \$24 $reduce_or$libresoc.v:22044$569_Y + connect \$23 $not$libresoc.v:22045$570_Y + connect \$31 $and$libresoc.v:22046$571_Y + connect \$33 $reduce_or$libresoc.v:22047$572_Y + connect \$35 $reduce_or$libresoc.v:22048$573_Y + connect \$37 $or$libresoc.v:22049$574_Y + connect \$3 $and$libresoc.v:22050$575_Y + connect \$39 $not$libresoc.v:22051$576_Y + connect \$41 $and$libresoc.v:22052$577_Y + connect \$43 $and$libresoc.v:22053$578_Y + connect \$45 $eq$libresoc.v:22054$579_Y + connect \$47 $and$libresoc.v:22055$580_Y + connect \$49 $eq$libresoc.v:22056$581_Y + connect \$51 $and$libresoc.v:22057$582_Y + connect \$53 $and$libresoc.v:22058$583_Y + connect \$55 $and$libresoc.v:22059$584_Y + connect \$57 $or$libresoc.v:22060$585_Y + connect \$59 $or$libresoc.v:22061$586_Y + connect \$61 $or$libresoc.v:22062$587_Y + connect \$63 $or$libresoc.v:22063$588_Y + connect \$65 $and$libresoc.v:22064$589_Y + connect \$67 $and$libresoc.v:22065$590_Y + connect \$6 $not$libresoc.v:22066$591_Y + connect \$69 $or$libresoc.v:22067$592_Y + connect \$71 $and$libresoc.v:22068$593_Y + connect \$73 $and$libresoc.v:22069$594_Y + connect \$75 $and$libresoc.v:22070$595_Y + connect \$77 $and$libresoc.v:22071$596_Y + connect \$79 $and$libresoc.v:22072$597_Y + connect \$81 $ternary$libresoc.v:22073$598_Y + connect \$83 $ternary$libresoc.v:22074$599_Y + connect \$86 $ternary$libresoc.v:22075$600_Y + connect \$8 $or$libresoc.v:22076$601_Y + connect \$89 $ternary$libresoc.v:22077$602_Y + connect \$91 $ternary$libresoc.v:22078$603_Y + connect \$93 $ternary$libresoc.v:22079$604_Y + connect \$95 $ternary$libresoc.v:22080$605_Y + connect \$97 $ternary$libresoc.v:22081$606_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$127 @@ -35023,7 +35059,7 @@ module \alu0 connect \all_rd_dly$next \all_rd connect \all_rd \$11 end -attribute \src "libresoc.v:22619.1-23697.10" +attribute \src "libresoc.v:22667.1-23745.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0" attribute \generator "nMigen" @@ -35288,9 +35324,9 @@ module \alu_alu0 wire input 18 \alu_op__zero_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__zero_a$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 38 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 28 \cr_a @@ -35945,19 +35981,19 @@ module \alu_alu0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 6 \xer_so_ok attribute \module_not_derived 1 - attribute \src "libresoc.v:23536.5-23539.4" + attribute \src "libresoc.v:23584.5-23587.4" cell \n \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:23540.5-23543.4" + attribute \src "libresoc.v:23588.5-23591.4" cell \p \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:23544.9-23603.4" + attribute \src "libresoc.v:23592.9-23651.4" cell \pipe1 \pipe1 connect \alu_op__data_len \pipe1_alu_op__data_len connect \alu_op__data_len$18 \pipe1_alu_op__data_len$20 @@ -36019,7 +36055,7 @@ module \alu_alu0 connect \xer_so_ok \pipe1_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:23604.9-23669.4" + attribute \src "libresoc.v:23652.9-23717.4" cell \pipe2 \pipe2 connect \alu_op__data_len \pipe2_alu_op__data_len connect \alu_op__data_len$18 \pipe2_alu_op__data_len$41 @@ -36114,7 +36150,7 @@ module \alu_alu0 connect \pipe1_n_ready_i \pipe2_p_ready_o connect \pipe2_p_valid_i \pipe1_n_valid_o end -attribute \src "libresoc.v:23701.1-24248.10" +attribute \src "libresoc.v:23749.1-24296.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0" attribute \generator "nMigen" @@ -36331,9 +36367,9 @@ module \alu_branch0 wire input 13 \br_op__lk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \br_op__lk$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 23 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 20 \cr_a @@ -36608,19 +36644,19 @@ module \alu_branch0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:159" wire \pipe_p_valid_i attribute \module_not_derived 1 - attribute \src "libresoc.v:24190.10-24193.4" + attribute \src "libresoc.v:24238.10-24241.4" cell \n$18 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:24194.10-24197.4" + attribute \src "libresoc.v:24242.10-24245.4" cell \p$17 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:24198.13-24232.4" + attribute \src "libresoc.v:24246.13-24280.4" cell \pipe$19 \pipe connect \br_op__cia \pipe_br_op__cia connect \br_op__cia$2 \pipe_br_op__cia$4 @@ -36672,14 +36708,14 @@ module \alu_branch0 connect \p_ready_o \pipe_p_ready_o connect \pipe_p_valid_i \p_valid_i end -attribute \src "libresoc.v:24252.1-24767.10" +attribute \src "libresoc.v:24300.1-24815.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0" attribute \generator "nMigen" module \alu_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 21 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 12 \cr_a @@ -37138,19 +37174,19 @@ module \alu_cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 14 \rb attribute \module_not_derived 1 - attribute \src "libresoc.v:24713.9-24716.4" + attribute \src "libresoc.v:24761.9-24764.4" cell \n$6 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:24717.9-24720.4" + attribute \src "libresoc.v:24765.9-24768.4" cell \p$5 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:24721.8-24748.4" + attribute \src "libresoc.v:24769.8-24796.4" cell \pipe \pipe connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -37198,14 +37234,14 @@ module \alu_cr0 connect \p_ready_o \pipe_p_ready_o connect \pipe_p_valid_i \p_valid_i end -attribute \src "libresoc.v:24771.1-26236.10" +attribute \src "libresoc.v:24819.1-26284.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0" attribute \generator "nMigen" module \alu_div0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 35 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 27 \cr_a @@ -38424,19 +38460,19 @@ module \alu_div0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 5 \xer_so_ok attribute \module_not_derived 1 - attribute \src "libresoc.v:25992.10-25995.4" + attribute \src "libresoc.v:26040.10-26043.4" cell \n$75 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:25996.10-25999.4" + attribute \src "libresoc.v:26044.10-26047.4" cell \p$74 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:26000.12-26063.4" + attribute \src "libresoc.v:26048.12-26111.4" cell \pipe_end \pipe_end connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -38502,7 +38538,7 @@ module \alu_div0 connect \xer_so_ok \pipe_end_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:26064.17-26130.4" + attribute \src "libresoc.v:26112.17-26178.4" cell \pipe_middle_0 \pipe_middle_0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -38571,7 +38607,7 @@ module \alu_div0 connect \xer_so$22 \pipe_middle_0_xer_so$45 end attribute \module_not_derived 1 - attribute \src "libresoc.v:26131.14-26190.4" + attribute \src "libresoc.v:26179.14-26238.4" cell \pipe_start \pipe_start connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -38678,37 +38714,37 @@ module \alu_div0 connect \pipe_start_n_ready_i \pipe_middle_0_p_ready_o connect \pipe_middle_0_p_valid_i \pipe_start_n_valid_o end -attribute \src "libresoc.v:26240.1-26298.10" +attribute \src "libresoc.v:26288.1-26346.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_l" attribute \generator "nMigen" module \alu_l - attribute \src "libresoc.v:26241.7-26241.20" + attribute \src "libresoc.v:26289.7-26289.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26286.3-26294.6" + attribute \src "libresoc.v:26334.3-26342.6" wire $0\q_int$next[0:0]$852 - attribute \src "libresoc.v:26284.3-26285.27" + attribute \src "libresoc.v:26332.3-26333.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26286.3-26294.6" + attribute \src "libresoc.v:26334.3-26342.6" wire $1\q_int$next[0:0]$853 - attribute \src "libresoc.v:26265.7-26265.19" + attribute \src "libresoc.v:26313.7-26313.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26276.17-26276.96" - wire $and$libresoc.v:26276$842_Y - attribute \src "libresoc.v:26281.17-26281.96" - wire $and$libresoc.v:26281$847_Y - attribute \src "libresoc.v:26278.18-26278.93" - wire $not$libresoc.v:26278$844_Y - attribute \src "libresoc.v:26280.17-26280.92" - wire $not$libresoc.v:26280$846_Y - attribute \src "libresoc.v:26283.17-26283.92" - wire $not$libresoc.v:26283$849_Y - attribute \src "libresoc.v:26277.18-26277.98" - wire $or$libresoc.v:26277$843_Y - attribute \src "libresoc.v:26279.18-26279.99" - wire $or$libresoc.v:26279$845_Y - attribute \src "libresoc.v:26282.17-26282.97" - wire $or$libresoc.v:26282$848_Y + attribute \src "libresoc.v:26324.17-26324.96" + wire $and$libresoc.v:26324$842_Y + attribute \src "libresoc.v:26329.17-26329.96" + wire $and$libresoc.v:26329$847_Y + attribute \src "libresoc.v:26326.18-26326.93" + wire $not$libresoc.v:26326$844_Y + attribute \src "libresoc.v:26328.17-26328.92" + wire $not$libresoc.v:26328$846_Y + attribute \src "libresoc.v:26331.17-26331.92" + wire $not$libresoc.v:26331$849_Y + attribute \src "libresoc.v:26325.18-26325.98" + wire $or$libresoc.v:26325$843_Y + attribute \src "libresoc.v:26327.18-26327.99" + wire $or$libresoc.v:26327$845_Y + attribute \src "libresoc.v:26330.17-26330.97" + wire $or$libresoc.v:26330$848_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -38725,11 +38761,11 @@ module \alu_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:26241.7-26241.15" + attribute \src "libresoc.v:26289.7-26289.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu @@ -38746,7 +38782,7 @@ module \alu_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:26276$842 + cell $and $and$libresoc.v:26324$842 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38754,10 +38790,10 @@ module \alu_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26276$842_Y + connect \Y $and$libresoc.v:26324$842_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:26281$847 + cell $and $and$libresoc.v:26329$847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38765,34 +38801,34 @@ module \alu_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26281$847_Y + connect \Y $and$libresoc.v:26329$847_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:26278$844 + cell $not $not$libresoc.v:26326$844 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26278$844_Y + connect \Y $not$libresoc.v:26326$844_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:26280$846 + cell $not $not$libresoc.v:26328$846 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26280$846_Y + connect \Y $not$libresoc.v:26328$846_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:26283$849 + cell $not $not$libresoc.v:26331$849 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26283$849_Y + connect \Y $not$libresoc.v:26331$849_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:26277$843 + cell $or $or$libresoc.v:26325$843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38800,10 +38836,10 @@ module \alu_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26277$843_Y + connect \Y $or$libresoc.v:26325$843_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:26279$845 + cell $or $or$libresoc.v:26327$845 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38811,10 +38847,10 @@ module \alu_l parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26279$845_Y + connect \Y $or$libresoc.v:26327$845_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:26282$848 + cell $or $or$libresoc.v:26330$848 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38822,39 +38858,39 @@ module \alu_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26282$848_Y + connect \Y $or$libresoc.v:26330$848_Y end - attribute \src "libresoc.v:26241.7-26241.20" - process $proc$libresoc.v:26241$854 + attribute \src "libresoc.v:26289.7-26289.20" + process $proc$libresoc.v:26289$854 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26265.7-26265.19" - process $proc$libresoc.v:26265$855 + attribute \src "libresoc.v:26313.7-26313.19" + process $proc$libresoc.v:26313$855 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26284.3-26285.27" - process $proc$libresoc.v:26284$850 + attribute \src "libresoc.v:26332.3-26333.27" + process $proc$libresoc.v:26332$850 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26286.3-26294.6" - process $proc$libresoc.v:26286$851 + attribute \src "libresoc.v:26334.3-26342.6" + process $proc$libresoc.v:26334$851 assign { } { } assign { } { } assign $0\q_int$next[0:0]$852 $1\q_int$next[0:0]$853 - attribute \src "libresoc.v:26287.5-26287.29" + attribute \src "libresoc.v:26335.5-26335.29" switch \initial - attribute \src "libresoc.v:26287.9-26287.17" + attribute \src "libresoc.v:26335.9-26335.17" case 1'1 case end @@ -38870,49 +38906,49 @@ module \alu_l sync always update \q_int$next $0\q_int$next[0:0]$852 end - connect \$9 $and$libresoc.v:26276$842_Y - connect \$11 $or$libresoc.v:26277$843_Y - connect \$13 $not$libresoc.v:26278$844_Y - connect \$15 $or$libresoc.v:26279$845_Y - connect \$1 $not$libresoc.v:26280$846_Y - connect \$3 $and$libresoc.v:26281$847_Y - connect \$5 $or$libresoc.v:26282$848_Y - connect \$7 $not$libresoc.v:26283$849_Y + connect \$9 $and$libresoc.v:26324$842_Y + connect \$11 $or$libresoc.v:26325$843_Y + connect \$13 $not$libresoc.v:26326$844_Y + connect \$15 $or$libresoc.v:26327$845_Y + connect \$1 $not$libresoc.v:26328$846_Y + connect \$3 $and$libresoc.v:26329$847_Y + connect \$5 $or$libresoc.v:26330$848_Y + connect \$7 $not$libresoc.v:26331$849_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26302.1-26360.10" +attribute \src "libresoc.v:26350.1-26408.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_l" attribute \generator "nMigen" module \alu_l$107 - attribute \src "libresoc.v:26303.7-26303.20" + attribute \src "libresoc.v:26351.7-26351.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26348.3-26356.6" + attribute \src "libresoc.v:26396.3-26404.6" wire $0\q_int$next[0:0]$866 - attribute \src "libresoc.v:26346.3-26347.27" + attribute \src "libresoc.v:26394.3-26395.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26348.3-26356.6" + attribute \src "libresoc.v:26396.3-26404.6" wire $1\q_int$next[0:0]$867 - attribute \src "libresoc.v:26327.7-26327.19" + attribute \src "libresoc.v:26375.7-26375.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26338.17-26338.96" - wire $and$libresoc.v:26338$856_Y - attribute \src "libresoc.v:26343.17-26343.96" - wire $and$libresoc.v:26343$861_Y - attribute \src "libresoc.v:26340.18-26340.93" - wire $not$libresoc.v:26340$858_Y - attribute \src "libresoc.v:26342.17-26342.92" - wire $not$libresoc.v:26342$860_Y - attribute \src "libresoc.v:26345.17-26345.92" - wire $not$libresoc.v:26345$863_Y - attribute \src "libresoc.v:26339.18-26339.98" - wire $or$libresoc.v:26339$857_Y - attribute \src "libresoc.v:26341.18-26341.99" - wire $or$libresoc.v:26341$859_Y - attribute \src "libresoc.v:26344.17-26344.97" - wire $or$libresoc.v:26344$862_Y + attribute \src "libresoc.v:26386.17-26386.96" + wire $and$libresoc.v:26386$856_Y + attribute \src "libresoc.v:26391.17-26391.96" + wire $and$libresoc.v:26391$861_Y + attribute \src "libresoc.v:26388.18-26388.93" + wire $not$libresoc.v:26388$858_Y + attribute \src "libresoc.v:26390.17-26390.92" + wire $not$libresoc.v:26390$860_Y + attribute \src "libresoc.v:26393.17-26393.92" + wire $not$libresoc.v:26393$863_Y + attribute \src "libresoc.v:26387.18-26387.98" + wire $or$libresoc.v:26387$857_Y + attribute \src "libresoc.v:26389.18-26389.99" + wire $or$libresoc.v:26389$859_Y + attribute \src "libresoc.v:26392.17-26392.97" + wire $or$libresoc.v:26392$862_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -38929,11 +38965,11 @@ module \alu_l$107 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:26303.7-26303.15" + attribute \src "libresoc.v:26351.7-26351.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu @@ -38950,7 +38986,7 @@ module \alu_l$107 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:26338$856 + cell $and $and$libresoc.v:26386$856 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38958,10 +38994,10 @@ module \alu_l$107 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26338$856_Y + connect \Y $and$libresoc.v:26386$856_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:26343$861 + cell $and $and$libresoc.v:26391$861 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -38969,34 +39005,34 @@ module \alu_l$107 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26343$861_Y + connect \Y $and$libresoc.v:26391$861_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:26340$858 + cell $not $not$libresoc.v:26388$858 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26340$858_Y + connect \Y $not$libresoc.v:26388$858_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:26342$860 + cell $not $not$libresoc.v:26390$860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26342$860_Y + connect \Y $not$libresoc.v:26390$860_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:26345$863 + cell $not $not$libresoc.v:26393$863 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26345$863_Y + connect \Y $not$libresoc.v:26393$863_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:26339$857 + cell $or $or$libresoc.v:26387$857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39004,10 +39040,10 @@ module \alu_l$107 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26339$857_Y + connect \Y $or$libresoc.v:26387$857_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:26341$859 + cell $or $or$libresoc.v:26389$859 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39015,10 +39051,10 @@ module \alu_l$107 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26341$859_Y + connect \Y $or$libresoc.v:26389$859_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:26344$862 + cell $or $or$libresoc.v:26392$862 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39026,39 +39062,39 @@ module \alu_l$107 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26344$862_Y + connect \Y $or$libresoc.v:26392$862_Y end - attribute \src "libresoc.v:26303.7-26303.20" - process $proc$libresoc.v:26303$868 + attribute \src "libresoc.v:26351.7-26351.20" + process $proc$libresoc.v:26351$868 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26327.7-26327.19" - process $proc$libresoc.v:26327$869 + attribute \src "libresoc.v:26375.7-26375.19" + process $proc$libresoc.v:26375$869 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26346.3-26347.27" - process $proc$libresoc.v:26346$864 + attribute \src "libresoc.v:26394.3-26395.27" + process $proc$libresoc.v:26394$864 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26348.3-26356.6" - process $proc$libresoc.v:26348$865 + attribute \src "libresoc.v:26396.3-26404.6" + process $proc$libresoc.v:26396$865 assign { } { } assign { } { } assign $0\q_int$next[0:0]$866 $1\q_int$next[0:0]$867 - attribute \src "libresoc.v:26349.5-26349.29" + attribute \src "libresoc.v:26397.5-26397.29" switch \initial - attribute \src "libresoc.v:26349.9-26349.17" + attribute \src "libresoc.v:26397.9-26397.17" case 1'1 case end @@ -39074,49 +39110,49 @@ module \alu_l$107 sync always update \q_int$next $0\q_int$next[0:0]$866 end - connect \$9 $and$libresoc.v:26338$856_Y - connect \$11 $or$libresoc.v:26339$857_Y - connect \$13 $not$libresoc.v:26340$858_Y - connect \$15 $or$libresoc.v:26341$859_Y - connect \$1 $not$libresoc.v:26342$860_Y - connect \$3 $and$libresoc.v:26343$861_Y - connect \$5 $or$libresoc.v:26344$862_Y - connect \$7 $not$libresoc.v:26345$863_Y + connect \$9 $and$libresoc.v:26386$856_Y + connect \$11 $or$libresoc.v:26387$857_Y + connect \$13 $not$libresoc.v:26388$858_Y + connect \$15 $or$libresoc.v:26389$859_Y + connect \$1 $not$libresoc.v:26390$860_Y + connect \$3 $and$libresoc.v:26391$861_Y + connect \$5 $or$libresoc.v:26392$862_Y + connect \$7 $not$libresoc.v:26393$863_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26364.1-26422.10" +attribute \src "libresoc.v:26412.1-26470.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_l" attribute \generator "nMigen" module \alu_l$125 - attribute \src "libresoc.v:26365.7-26365.20" + attribute \src "libresoc.v:26413.7-26413.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26410.3-26418.6" + attribute \src "libresoc.v:26458.3-26466.6" wire $0\q_int$next[0:0]$880 - attribute \src "libresoc.v:26408.3-26409.27" + attribute \src "libresoc.v:26456.3-26457.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26410.3-26418.6" + attribute \src "libresoc.v:26458.3-26466.6" wire $1\q_int$next[0:0]$881 - attribute \src "libresoc.v:26389.7-26389.19" + attribute \src "libresoc.v:26437.7-26437.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26400.17-26400.96" - wire $and$libresoc.v:26400$870_Y - attribute \src "libresoc.v:26405.17-26405.96" - wire $and$libresoc.v:26405$875_Y - attribute \src "libresoc.v:26402.18-26402.93" - wire $not$libresoc.v:26402$872_Y - attribute \src "libresoc.v:26404.17-26404.92" - wire $not$libresoc.v:26404$874_Y - attribute \src "libresoc.v:26407.17-26407.92" - wire $not$libresoc.v:26407$877_Y - attribute \src "libresoc.v:26401.18-26401.98" - wire $or$libresoc.v:26401$871_Y - attribute \src "libresoc.v:26403.18-26403.99" - wire $or$libresoc.v:26403$873_Y - attribute \src "libresoc.v:26406.17-26406.97" - wire $or$libresoc.v:26406$876_Y + attribute \src "libresoc.v:26448.17-26448.96" + wire $and$libresoc.v:26448$870_Y + attribute \src "libresoc.v:26453.17-26453.96" + wire $and$libresoc.v:26453$875_Y + attribute \src "libresoc.v:26450.18-26450.93" + wire $not$libresoc.v:26450$872_Y + attribute \src "libresoc.v:26452.17-26452.92" + wire $not$libresoc.v:26452$874_Y + attribute \src "libresoc.v:26455.17-26455.92" + wire $not$libresoc.v:26455$877_Y + attribute \src "libresoc.v:26449.18-26449.98" + wire $or$libresoc.v:26449$871_Y + attribute \src "libresoc.v:26451.18-26451.99" + wire $or$libresoc.v:26451$873_Y + attribute \src "libresoc.v:26454.17-26454.97" + wire $or$libresoc.v:26454$876_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -39133,11 +39169,11 @@ module \alu_l$125 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:26365.7-26365.15" + attribute \src "libresoc.v:26413.7-26413.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu @@ -39154,7 +39190,7 @@ module \alu_l$125 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:26400$870 + cell $and $and$libresoc.v:26448$870 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39162,10 +39198,10 @@ module \alu_l$125 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26400$870_Y + connect \Y $and$libresoc.v:26448$870_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:26405$875 + cell $and $and$libresoc.v:26453$875 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39173,34 +39209,34 @@ module \alu_l$125 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26405$875_Y + connect \Y $and$libresoc.v:26453$875_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:26402$872 + cell $not $not$libresoc.v:26450$872 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26402$872_Y + connect \Y $not$libresoc.v:26450$872_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:26404$874 + cell $not $not$libresoc.v:26452$874 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26404$874_Y + connect \Y $not$libresoc.v:26452$874_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:26407$877 + cell $not $not$libresoc.v:26455$877 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26407$877_Y + connect \Y $not$libresoc.v:26455$877_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:26401$871 + cell $or $or$libresoc.v:26449$871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39208,10 +39244,10 @@ module \alu_l$125 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26401$871_Y + connect \Y $or$libresoc.v:26449$871_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:26403$873 + cell $or $or$libresoc.v:26451$873 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39219,10 +39255,10 @@ module \alu_l$125 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26403$873_Y + connect \Y $or$libresoc.v:26451$873_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:26406$876 + cell $or $or$libresoc.v:26454$876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39230,39 +39266,39 @@ module \alu_l$125 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26406$876_Y + connect \Y $or$libresoc.v:26454$876_Y end - attribute \src "libresoc.v:26365.7-26365.20" - process $proc$libresoc.v:26365$882 + attribute \src "libresoc.v:26413.7-26413.20" + process $proc$libresoc.v:26413$882 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26389.7-26389.19" - process $proc$libresoc.v:26389$883 + attribute \src "libresoc.v:26437.7-26437.19" + process $proc$libresoc.v:26437$883 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26408.3-26409.27" - process $proc$libresoc.v:26408$878 + attribute \src "libresoc.v:26456.3-26457.27" + process $proc$libresoc.v:26456$878 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26410.3-26418.6" - process $proc$libresoc.v:26410$879 + attribute \src "libresoc.v:26458.3-26466.6" + process $proc$libresoc.v:26458$879 assign { } { } assign { } { } assign $0\q_int$next[0:0]$880 $1\q_int$next[0:0]$881 - attribute \src "libresoc.v:26411.5-26411.29" + attribute \src "libresoc.v:26459.5-26459.29" switch \initial - attribute \src "libresoc.v:26411.9-26411.17" + attribute \src "libresoc.v:26459.9-26459.17" case 1'1 case end @@ -39278,49 +39314,49 @@ module \alu_l$125 sync always update \q_int$next $0\q_int$next[0:0]$880 end - connect \$9 $and$libresoc.v:26400$870_Y - connect \$11 $or$libresoc.v:26401$871_Y - connect \$13 $not$libresoc.v:26402$872_Y - connect \$15 $or$libresoc.v:26403$873_Y - connect \$1 $not$libresoc.v:26404$874_Y - connect \$3 $and$libresoc.v:26405$875_Y - connect \$5 $or$libresoc.v:26406$876_Y - connect \$7 $not$libresoc.v:26407$877_Y + connect \$9 $and$libresoc.v:26448$870_Y + connect \$11 $or$libresoc.v:26449$871_Y + connect \$13 $not$libresoc.v:26450$872_Y + connect \$15 $or$libresoc.v:26451$873_Y + connect \$1 $not$libresoc.v:26452$874_Y + connect \$3 $and$libresoc.v:26453$875_Y + connect \$5 $or$libresoc.v:26454$876_Y + connect \$7 $not$libresoc.v:26455$877_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26426.1-26484.10" +attribute \src "libresoc.v:26474.1-26532.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.alu_l" attribute \generator "nMigen" module \alu_l$128 - attribute \src "libresoc.v:26427.7-26427.20" + attribute \src "libresoc.v:26475.7-26475.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26472.3-26480.6" + attribute \src "libresoc.v:26520.3-26528.6" wire $0\q_int$next[0:0]$894 - attribute \src "libresoc.v:26470.3-26471.27" + attribute \src "libresoc.v:26518.3-26519.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26472.3-26480.6" + attribute \src "libresoc.v:26520.3-26528.6" wire $1\q_int$next[0:0]$895 - attribute \src "libresoc.v:26451.7-26451.19" + attribute \src "libresoc.v:26499.7-26499.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26462.17-26462.96" - wire $and$libresoc.v:26462$884_Y - attribute \src "libresoc.v:26467.17-26467.96" - wire $and$libresoc.v:26467$889_Y - attribute \src "libresoc.v:26464.18-26464.93" - wire $not$libresoc.v:26464$886_Y - attribute \src "libresoc.v:26466.17-26466.92" - wire $not$libresoc.v:26466$888_Y - attribute \src "libresoc.v:26469.17-26469.92" - wire $not$libresoc.v:26469$891_Y - attribute \src "libresoc.v:26463.18-26463.98" - wire $or$libresoc.v:26463$885_Y - attribute \src "libresoc.v:26465.18-26465.99" - wire $or$libresoc.v:26465$887_Y - attribute \src "libresoc.v:26468.17-26468.97" - wire $or$libresoc.v:26468$890_Y + attribute \src "libresoc.v:26510.17-26510.96" + wire $and$libresoc.v:26510$884_Y + attribute \src "libresoc.v:26515.17-26515.96" + wire $and$libresoc.v:26515$889_Y + attribute \src "libresoc.v:26512.18-26512.93" + wire $not$libresoc.v:26512$886_Y + attribute \src "libresoc.v:26514.17-26514.92" + wire $not$libresoc.v:26514$888_Y + attribute \src "libresoc.v:26517.17-26517.92" + wire $not$libresoc.v:26517$891_Y + attribute \src "libresoc.v:26511.18-26511.98" + wire $or$libresoc.v:26511$885_Y + attribute \src "libresoc.v:26513.18-26513.99" + wire $or$libresoc.v:26513$887_Y + attribute \src "libresoc.v:26516.17-26516.97" + wire $or$libresoc.v:26516$890_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -39337,11 +39373,11 @@ module \alu_l$128 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:26427.7-26427.15" + attribute \src "libresoc.v:26475.7-26475.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_alu @@ -39358,7 +39394,7 @@ module \alu_l$128 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:26462$884 + cell $and $and$libresoc.v:26510$884 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39366,10 +39402,10 @@ module \alu_l$128 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26462$884_Y + connect \Y $and$libresoc.v:26510$884_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:26467$889 + cell $and $and$libresoc.v:26515$889 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39377,34 +39413,34 @@ module \alu_l$128 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26467$889_Y + connect \Y $and$libresoc.v:26515$889_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:26464$886 + cell $not $not$libresoc.v:26512$886 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26464$886_Y + connect \Y $not$libresoc.v:26512$886_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:26466$888 + cell $not $not$libresoc.v:26514$888 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26466$888_Y + connect \Y $not$libresoc.v:26514$888_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:26469$891 + cell $not $not$libresoc.v:26517$891 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26469$891_Y + connect \Y $not$libresoc.v:26517$891_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:26463$885 + cell $or $or$libresoc.v:26511$885 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39412,10 +39448,10 @@ module \alu_l$128 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26463$885_Y + connect \Y $or$libresoc.v:26511$885_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:26465$887 + cell $or $or$libresoc.v:26513$887 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39423,10 +39459,10 @@ module \alu_l$128 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26465$887_Y + connect \Y $or$libresoc.v:26513$887_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:26468$890 + cell $or $or$libresoc.v:26516$890 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39434,39 +39470,39 @@ module \alu_l$128 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26468$890_Y + connect \Y $or$libresoc.v:26516$890_Y end - attribute \src "libresoc.v:26427.7-26427.20" - process $proc$libresoc.v:26427$896 + attribute \src "libresoc.v:26475.7-26475.20" + process $proc$libresoc.v:26475$896 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26451.7-26451.19" - process $proc$libresoc.v:26451$897 + attribute \src "libresoc.v:26499.7-26499.19" + process $proc$libresoc.v:26499$897 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26470.3-26471.27" - process $proc$libresoc.v:26470$892 + attribute \src "libresoc.v:26518.3-26519.27" + process $proc$libresoc.v:26518$892 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26472.3-26480.6" - process $proc$libresoc.v:26472$893 + attribute \src "libresoc.v:26520.3-26528.6" + process $proc$libresoc.v:26520$893 assign { } { } assign { } { } assign $0\q_int$next[0:0]$894 $1\q_int$next[0:0]$895 - attribute \src "libresoc.v:26473.5-26473.29" + attribute \src "libresoc.v:26521.5-26521.29" switch \initial - attribute \src "libresoc.v:26473.9-26473.17" + attribute \src "libresoc.v:26521.9-26521.17" case 1'1 case end @@ -39482,49 +39518,49 @@ module \alu_l$128 sync always update \q_int$next $0\q_int$next[0:0]$894 end - connect \$9 $and$libresoc.v:26462$884_Y - connect \$11 $or$libresoc.v:26463$885_Y - connect \$13 $not$libresoc.v:26464$886_Y - connect \$15 $or$libresoc.v:26465$887_Y - connect \$1 $not$libresoc.v:26466$888_Y - connect \$3 $and$libresoc.v:26467$889_Y - connect \$5 $or$libresoc.v:26468$890_Y - connect \$7 $not$libresoc.v:26469$891_Y + connect \$9 $and$libresoc.v:26510$884_Y + connect \$11 $or$libresoc.v:26511$885_Y + connect \$13 $not$libresoc.v:26512$886_Y + connect \$15 $or$libresoc.v:26513$887_Y + connect \$1 $not$libresoc.v:26514$888_Y + connect \$3 $and$libresoc.v:26515$889_Y + connect \$5 $or$libresoc.v:26516$890_Y + connect \$7 $not$libresoc.v:26517$891_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26488.1-26546.10" +attribute \src "libresoc.v:26536.1-26594.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_l" attribute \generator "nMigen" module \alu_l$16 - attribute \src "libresoc.v:26489.7-26489.20" + attribute \src "libresoc.v:26537.7-26537.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26534.3-26542.6" + attribute \src "libresoc.v:26582.3-26590.6" wire $0\q_int$next[0:0]$908 - attribute \src "libresoc.v:26532.3-26533.27" + attribute \src "libresoc.v:26580.3-26581.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26534.3-26542.6" + attribute \src "libresoc.v:26582.3-26590.6" wire $1\q_int$next[0:0]$909 - attribute \src "libresoc.v:26513.7-26513.19" + attribute \src "libresoc.v:26561.7-26561.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26524.17-26524.96" - wire $and$libresoc.v:26524$898_Y - attribute \src "libresoc.v:26529.17-26529.96" - wire $and$libresoc.v:26529$903_Y - attribute \src "libresoc.v:26526.18-26526.93" - wire $not$libresoc.v:26526$900_Y - attribute \src "libresoc.v:26528.17-26528.92" - wire $not$libresoc.v:26528$902_Y - attribute \src "libresoc.v:26531.17-26531.92" - wire $not$libresoc.v:26531$905_Y - attribute \src "libresoc.v:26525.18-26525.98" - wire $or$libresoc.v:26525$899_Y - attribute \src "libresoc.v:26527.18-26527.99" - wire $or$libresoc.v:26527$901_Y - attribute \src "libresoc.v:26530.17-26530.97" - wire $or$libresoc.v:26530$904_Y + attribute \src "libresoc.v:26572.17-26572.96" + wire $and$libresoc.v:26572$898_Y + attribute \src "libresoc.v:26577.17-26577.96" + wire $and$libresoc.v:26577$903_Y + attribute \src "libresoc.v:26574.18-26574.93" + wire $not$libresoc.v:26574$900_Y + attribute \src "libresoc.v:26576.17-26576.92" + wire $not$libresoc.v:26576$902_Y + attribute \src "libresoc.v:26579.17-26579.92" + wire $not$libresoc.v:26579$905_Y + attribute \src "libresoc.v:26573.18-26573.98" + wire $or$libresoc.v:26573$899_Y + attribute \src "libresoc.v:26575.18-26575.99" + wire $or$libresoc.v:26575$901_Y + attribute \src "libresoc.v:26578.17-26578.97" + wire $or$libresoc.v:26578$904_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -39541,11 +39577,11 @@ module \alu_l$16 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:26489.7-26489.15" + attribute \src "libresoc.v:26537.7-26537.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu @@ -39562,7 +39598,7 @@ module \alu_l$16 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:26524$898 + cell $and $and$libresoc.v:26572$898 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39570,10 +39606,10 @@ module \alu_l$16 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26524$898_Y + connect \Y $and$libresoc.v:26572$898_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:26529$903 + cell $and $and$libresoc.v:26577$903 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39581,34 +39617,34 @@ module \alu_l$16 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26529$903_Y + connect \Y $and$libresoc.v:26577$903_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:26526$900 + cell $not $not$libresoc.v:26574$900 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26526$900_Y + connect \Y $not$libresoc.v:26574$900_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:26528$902 + cell $not $not$libresoc.v:26576$902 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26528$902_Y + connect \Y $not$libresoc.v:26576$902_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:26531$905 + cell $not $not$libresoc.v:26579$905 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26531$905_Y + connect \Y $not$libresoc.v:26579$905_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:26525$899 + cell $or $or$libresoc.v:26573$899 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39616,10 +39652,10 @@ module \alu_l$16 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26525$899_Y + connect \Y $or$libresoc.v:26573$899_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:26527$901 + cell $or $or$libresoc.v:26575$901 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39627,10 +39663,10 @@ module \alu_l$16 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26527$901_Y + connect \Y $or$libresoc.v:26575$901_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:26530$904 + cell $or $or$libresoc.v:26578$904 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39638,39 +39674,39 @@ module \alu_l$16 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26530$904_Y + connect \Y $or$libresoc.v:26578$904_Y end - attribute \src "libresoc.v:26489.7-26489.20" - process $proc$libresoc.v:26489$910 + attribute \src "libresoc.v:26537.7-26537.20" + process $proc$libresoc.v:26537$910 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26513.7-26513.19" - process $proc$libresoc.v:26513$911 + attribute \src "libresoc.v:26561.7-26561.19" + process $proc$libresoc.v:26561$911 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26532.3-26533.27" - process $proc$libresoc.v:26532$906 + attribute \src "libresoc.v:26580.3-26581.27" + process $proc$libresoc.v:26580$906 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26534.3-26542.6" - process $proc$libresoc.v:26534$907 + attribute \src "libresoc.v:26582.3-26590.6" + process $proc$libresoc.v:26582$907 assign { } { } assign { } { } assign $0\q_int$next[0:0]$908 $1\q_int$next[0:0]$909 - attribute \src "libresoc.v:26535.5-26535.29" + attribute \src "libresoc.v:26583.5-26583.29" switch \initial - attribute \src "libresoc.v:26535.9-26535.17" + attribute \src "libresoc.v:26583.9-26583.17" case 1'1 case end @@ -39686,49 +39722,49 @@ module \alu_l$16 sync always update \q_int$next $0\q_int$next[0:0]$908 end - connect \$9 $and$libresoc.v:26524$898_Y - connect \$11 $or$libresoc.v:26525$899_Y - connect \$13 $not$libresoc.v:26526$900_Y - connect \$15 $or$libresoc.v:26527$901_Y - connect \$1 $not$libresoc.v:26528$902_Y - connect \$3 $and$libresoc.v:26529$903_Y - connect \$5 $or$libresoc.v:26530$904_Y - connect \$7 $not$libresoc.v:26531$905_Y + connect \$9 $and$libresoc.v:26572$898_Y + connect \$11 $or$libresoc.v:26573$899_Y + connect \$13 $not$libresoc.v:26574$900_Y + connect \$15 $or$libresoc.v:26575$901_Y + connect \$1 $not$libresoc.v:26576$902_Y + connect \$3 $and$libresoc.v:26577$903_Y + connect \$5 $or$libresoc.v:26578$904_Y + connect \$7 $not$libresoc.v:26579$905_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26550.1-26608.10" +attribute \src "libresoc.v:26598.1-26656.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_l" attribute \generator "nMigen" module \alu_l$29 - attribute \src "libresoc.v:26551.7-26551.20" + attribute \src "libresoc.v:26599.7-26599.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26596.3-26604.6" + attribute \src "libresoc.v:26644.3-26652.6" wire $0\q_int$next[0:0]$922 - attribute \src "libresoc.v:26594.3-26595.27" + attribute \src "libresoc.v:26642.3-26643.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26596.3-26604.6" + attribute \src "libresoc.v:26644.3-26652.6" wire $1\q_int$next[0:0]$923 - attribute \src "libresoc.v:26575.7-26575.19" + attribute \src "libresoc.v:26623.7-26623.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26586.17-26586.96" - wire $and$libresoc.v:26586$912_Y - attribute \src "libresoc.v:26591.17-26591.96" - wire $and$libresoc.v:26591$917_Y - attribute \src "libresoc.v:26588.18-26588.93" - wire $not$libresoc.v:26588$914_Y - attribute \src "libresoc.v:26590.17-26590.92" - wire $not$libresoc.v:26590$916_Y - attribute \src "libresoc.v:26593.17-26593.92" - wire $not$libresoc.v:26593$919_Y - attribute \src "libresoc.v:26587.18-26587.98" - wire $or$libresoc.v:26587$913_Y - attribute \src "libresoc.v:26589.18-26589.99" - wire $or$libresoc.v:26589$915_Y - attribute \src "libresoc.v:26592.17-26592.97" - wire $or$libresoc.v:26592$918_Y + attribute \src "libresoc.v:26634.17-26634.96" + wire $and$libresoc.v:26634$912_Y + attribute \src "libresoc.v:26639.17-26639.96" + wire $and$libresoc.v:26639$917_Y + attribute \src "libresoc.v:26636.18-26636.93" + wire $not$libresoc.v:26636$914_Y + attribute \src "libresoc.v:26638.17-26638.92" + wire $not$libresoc.v:26638$916_Y + attribute \src "libresoc.v:26641.17-26641.92" + wire $not$libresoc.v:26641$919_Y + attribute \src "libresoc.v:26635.18-26635.98" + wire $or$libresoc.v:26635$913_Y + attribute \src "libresoc.v:26637.18-26637.99" + wire $or$libresoc.v:26637$915_Y + attribute \src "libresoc.v:26640.17-26640.97" + wire $or$libresoc.v:26640$918_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -39745,11 +39781,11 @@ module \alu_l$29 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:26551.7-26551.15" + attribute \src "libresoc.v:26599.7-26599.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu @@ -39766,7 +39802,7 @@ module \alu_l$29 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:26586$912 + cell $and $and$libresoc.v:26634$912 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39774,10 +39810,10 @@ module \alu_l$29 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26586$912_Y + connect \Y $and$libresoc.v:26634$912_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:26591$917 + cell $and $and$libresoc.v:26639$917 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39785,34 +39821,34 @@ module \alu_l$29 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26591$917_Y + connect \Y $and$libresoc.v:26639$917_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:26588$914 + cell $not $not$libresoc.v:26636$914 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26588$914_Y + connect \Y $not$libresoc.v:26636$914_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:26590$916 + cell $not $not$libresoc.v:26638$916 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26590$916_Y + connect \Y $not$libresoc.v:26638$916_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:26593$919 + cell $not $not$libresoc.v:26641$919 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26593$919_Y + connect \Y $not$libresoc.v:26641$919_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:26587$913 + cell $or $or$libresoc.v:26635$913 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39820,10 +39856,10 @@ module \alu_l$29 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26587$913_Y + connect \Y $or$libresoc.v:26635$913_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:26589$915 + cell $or $or$libresoc.v:26637$915 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39831,10 +39867,10 @@ module \alu_l$29 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26589$915_Y + connect \Y $or$libresoc.v:26637$915_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:26592$918 + cell $or $or$libresoc.v:26640$918 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39842,39 +39878,39 @@ module \alu_l$29 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26592$918_Y + connect \Y $or$libresoc.v:26640$918_Y end - attribute \src "libresoc.v:26551.7-26551.20" - process $proc$libresoc.v:26551$924 + attribute \src "libresoc.v:26599.7-26599.20" + process $proc$libresoc.v:26599$924 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26575.7-26575.19" - process $proc$libresoc.v:26575$925 + attribute \src "libresoc.v:26623.7-26623.19" + process $proc$libresoc.v:26623$925 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26594.3-26595.27" - process $proc$libresoc.v:26594$920 + attribute \src "libresoc.v:26642.3-26643.27" + process $proc$libresoc.v:26642$920 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26596.3-26604.6" - process $proc$libresoc.v:26596$921 + attribute \src "libresoc.v:26644.3-26652.6" + process $proc$libresoc.v:26644$921 assign { } { } assign { } { } assign $0\q_int$next[0:0]$922 $1\q_int$next[0:0]$923 - attribute \src "libresoc.v:26597.5-26597.29" + attribute \src "libresoc.v:26645.5-26645.29" switch \initial - attribute \src "libresoc.v:26597.9-26597.17" + attribute \src "libresoc.v:26645.9-26645.17" case 1'1 case end @@ -39890,49 +39926,49 @@ module \alu_l$29 sync always update \q_int$next $0\q_int$next[0:0]$922 end - connect \$9 $and$libresoc.v:26586$912_Y - connect \$11 $or$libresoc.v:26587$913_Y - connect \$13 $not$libresoc.v:26588$914_Y - connect \$15 $or$libresoc.v:26589$915_Y - connect \$1 $not$libresoc.v:26590$916_Y - connect \$3 $and$libresoc.v:26591$917_Y - connect \$5 $or$libresoc.v:26592$918_Y - connect \$7 $not$libresoc.v:26593$919_Y + connect \$9 $and$libresoc.v:26634$912_Y + connect \$11 $or$libresoc.v:26635$913_Y + connect \$13 $not$libresoc.v:26636$914_Y + connect \$15 $or$libresoc.v:26637$915_Y + connect \$1 $not$libresoc.v:26638$916_Y + connect \$3 $and$libresoc.v:26639$917_Y + connect \$5 $or$libresoc.v:26640$918_Y + connect \$7 $not$libresoc.v:26641$919_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26612.1-26670.10" +attribute \src "libresoc.v:26660.1-26718.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_l" attribute \generator "nMigen" module \alu_l$45 - attribute \src "libresoc.v:26613.7-26613.20" + attribute \src "libresoc.v:26661.7-26661.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26658.3-26666.6" + attribute \src "libresoc.v:26706.3-26714.6" wire $0\q_int$next[0:0]$936 - attribute \src "libresoc.v:26656.3-26657.27" + attribute \src "libresoc.v:26704.3-26705.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26658.3-26666.6" + attribute \src "libresoc.v:26706.3-26714.6" wire $1\q_int$next[0:0]$937 - attribute \src "libresoc.v:26637.7-26637.19" + attribute \src "libresoc.v:26685.7-26685.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26648.17-26648.96" - wire $and$libresoc.v:26648$926_Y - attribute \src "libresoc.v:26653.17-26653.96" - wire $and$libresoc.v:26653$931_Y - attribute \src "libresoc.v:26650.18-26650.93" - wire $not$libresoc.v:26650$928_Y - attribute \src "libresoc.v:26652.17-26652.92" - wire $not$libresoc.v:26652$930_Y - attribute \src "libresoc.v:26655.17-26655.92" - wire $not$libresoc.v:26655$933_Y - attribute \src "libresoc.v:26649.18-26649.98" - wire $or$libresoc.v:26649$927_Y - attribute \src "libresoc.v:26651.18-26651.99" - wire $or$libresoc.v:26651$929_Y - attribute \src "libresoc.v:26654.17-26654.97" - wire $or$libresoc.v:26654$932_Y + attribute \src "libresoc.v:26696.17-26696.96" + wire $and$libresoc.v:26696$926_Y + attribute \src "libresoc.v:26701.17-26701.96" + wire $and$libresoc.v:26701$931_Y + attribute \src "libresoc.v:26698.18-26698.93" + wire $not$libresoc.v:26698$928_Y + attribute \src "libresoc.v:26700.17-26700.92" + wire $not$libresoc.v:26700$930_Y + attribute \src "libresoc.v:26703.17-26703.92" + wire $not$libresoc.v:26703$933_Y + attribute \src "libresoc.v:26697.18-26697.98" + wire $or$libresoc.v:26697$927_Y + attribute \src "libresoc.v:26699.18-26699.99" + wire $or$libresoc.v:26699$929_Y + attribute \src "libresoc.v:26702.17-26702.97" + wire $or$libresoc.v:26702$932_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -39949,11 +39985,11 @@ module \alu_l$45 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:26613.7-26613.15" + attribute \src "libresoc.v:26661.7-26661.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu @@ -39970,7 +40006,7 @@ module \alu_l$45 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:26648$926 + cell $and $and$libresoc.v:26696$926 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39978,10 +40014,10 @@ module \alu_l$45 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26648$926_Y + connect \Y $and$libresoc.v:26696$926_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:26653$931 + cell $and $and$libresoc.v:26701$931 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -39989,34 +40025,34 @@ module \alu_l$45 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26653$931_Y + connect \Y $and$libresoc.v:26701$931_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:26650$928 + cell $not $not$libresoc.v:26698$928 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26650$928_Y + connect \Y $not$libresoc.v:26698$928_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:26652$930 + cell $not $not$libresoc.v:26700$930 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26652$930_Y + connect \Y $not$libresoc.v:26700$930_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:26655$933 + cell $not $not$libresoc.v:26703$933 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26655$933_Y + connect \Y $not$libresoc.v:26703$933_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:26649$927 + cell $or $or$libresoc.v:26697$927 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40024,10 +40060,10 @@ module \alu_l$45 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26649$927_Y + connect \Y $or$libresoc.v:26697$927_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:26651$929 + cell $or $or$libresoc.v:26699$929 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40035,10 +40071,10 @@ module \alu_l$45 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26651$929_Y + connect \Y $or$libresoc.v:26699$929_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:26654$932 + cell $or $or$libresoc.v:26702$932 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40046,39 +40082,39 @@ module \alu_l$45 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26654$932_Y + connect \Y $or$libresoc.v:26702$932_Y end - attribute \src "libresoc.v:26613.7-26613.20" - process $proc$libresoc.v:26613$938 + attribute \src "libresoc.v:26661.7-26661.20" + process $proc$libresoc.v:26661$938 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26637.7-26637.19" - process $proc$libresoc.v:26637$939 + attribute \src "libresoc.v:26685.7-26685.19" + process $proc$libresoc.v:26685$939 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26656.3-26657.27" - process $proc$libresoc.v:26656$934 + attribute \src "libresoc.v:26704.3-26705.27" + process $proc$libresoc.v:26704$934 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26658.3-26666.6" - process $proc$libresoc.v:26658$935 + attribute \src "libresoc.v:26706.3-26714.6" + process $proc$libresoc.v:26706$935 assign { } { } assign { } { } assign $0\q_int$next[0:0]$936 $1\q_int$next[0:0]$937 - attribute \src "libresoc.v:26659.5-26659.29" + attribute \src "libresoc.v:26707.5-26707.29" switch \initial - attribute \src "libresoc.v:26659.9-26659.17" + attribute \src "libresoc.v:26707.9-26707.17" case 1'1 case end @@ -40094,49 +40130,49 @@ module \alu_l$45 sync always update \q_int$next $0\q_int$next[0:0]$936 end - connect \$9 $and$libresoc.v:26648$926_Y - connect \$11 $or$libresoc.v:26649$927_Y - connect \$13 $not$libresoc.v:26650$928_Y - connect \$15 $or$libresoc.v:26651$929_Y - connect \$1 $not$libresoc.v:26652$930_Y - connect \$3 $and$libresoc.v:26653$931_Y - connect \$5 $or$libresoc.v:26654$932_Y - connect \$7 $not$libresoc.v:26655$933_Y + connect \$9 $and$libresoc.v:26696$926_Y + connect \$11 $or$libresoc.v:26697$927_Y + connect \$13 $not$libresoc.v:26698$928_Y + connect \$15 $or$libresoc.v:26699$929_Y + connect \$1 $not$libresoc.v:26700$930_Y + connect \$3 $and$libresoc.v:26701$931_Y + connect \$5 $or$libresoc.v:26702$932_Y + connect \$7 $not$libresoc.v:26703$933_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26674.1-26732.10" +attribute \src "libresoc.v:26722.1-26780.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_l" attribute \generator "nMigen" module \alu_l$61 - attribute \src "libresoc.v:26675.7-26675.20" + attribute \src "libresoc.v:26723.7-26723.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26720.3-26728.6" + attribute \src "libresoc.v:26768.3-26776.6" wire $0\q_int$next[0:0]$950 - attribute \src "libresoc.v:26718.3-26719.27" + attribute \src "libresoc.v:26766.3-26767.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26720.3-26728.6" + attribute \src "libresoc.v:26768.3-26776.6" wire $1\q_int$next[0:0]$951 - attribute \src "libresoc.v:26699.7-26699.19" + attribute \src "libresoc.v:26747.7-26747.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26710.17-26710.96" - wire $and$libresoc.v:26710$940_Y - attribute \src "libresoc.v:26715.17-26715.96" - wire $and$libresoc.v:26715$945_Y - attribute \src "libresoc.v:26712.18-26712.93" - wire $not$libresoc.v:26712$942_Y - attribute \src "libresoc.v:26714.17-26714.92" - wire $not$libresoc.v:26714$944_Y - attribute \src "libresoc.v:26717.17-26717.92" - wire $not$libresoc.v:26717$947_Y - attribute \src "libresoc.v:26711.18-26711.98" - wire $or$libresoc.v:26711$941_Y - attribute \src "libresoc.v:26713.18-26713.99" - wire $or$libresoc.v:26713$943_Y - attribute \src "libresoc.v:26716.17-26716.97" - wire $or$libresoc.v:26716$946_Y + attribute \src "libresoc.v:26758.17-26758.96" + wire $and$libresoc.v:26758$940_Y + attribute \src "libresoc.v:26763.17-26763.96" + wire $and$libresoc.v:26763$945_Y + attribute \src "libresoc.v:26760.18-26760.93" + wire $not$libresoc.v:26760$942_Y + attribute \src "libresoc.v:26762.17-26762.92" + wire $not$libresoc.v:26762$944_Y + attribute \src "libresoc.v:26765.17-26765.92" + wire $not$libresoc.v:26765$947_Y + attribute \src "libresoc.v:26759.18-26759.98" + wire $or$libresoc.v:26759$941_Y + attribute \src "libresoc.v:26761.18-26761.99" + wire $or$libresoc.v:26761$943_Y + attribute \src "libresoc.v:26764.17-26764.97" + wire $or$libresoc.v:26764$946_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -40153,11 +40189,11 @@ module \alu_l$61 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:26675.7-26675.15" + attribute \src "libresoc.v:26723.7-26723.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu @@ -40174,7 +40210,7 @@ module \alu_l$61 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:26710$940 + cell $and $and$libresoc.v:26758$940 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40182,10 +40218,10 @@ module \alu_l$61 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26710$940_Y + connect \Y $and$libresoc.v:26758$940_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:26715$945 + cell $and $and$libresoc.v:26763$945 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40193,34 +40229,34 @@ module \alu_l$61 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26715$945_Y + connect \Y $and$libresoc.v:26763$945_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:26712$942 + cell $not $not$libresoc.v:26760$942 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26712$942_Y + connect \Y $not$libresoc.v:26760$942_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:26714$944 + cell $not $not$libresoc.v:26762$944 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26714$944_Y + connect \Y $not$libresoc.v:26762$944_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:26717$947 + cell $not $not$libresoc.v:26765$947 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26717$947_Y + connect \Y $not$libresoc.v:26765$947_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:26711$941 + cell $or $or$libresoc.v:26759$941 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40228,10 +40264,10 @@ module \alu_l$61 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26711$941_Y + connect \Y $or$libresoc.v:26759$941_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:26713$943 + cell $or $or$libresoc.v:26761$943 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40239,10 +40275,10 @@ module \alu_l$61 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26713$943_Y + connect \Y $or$libresoc.v:26761$943_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:26716$946 + cell $or $or$libresoc.v:26764$946 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40250,39 +40286,39 @@ module \alu_l$61 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26716$946_Y + connect \Y $or$libresoc.v:26764$946_Y end - attribute \src "libresoc.v:26675.7-26675.20" - process $proc$libresoc.v:26675$952 + attribute \src "libresoc.v:26723.7-26723.20" + process $proc$libresoc.v:26723$952 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26699.7-26699.19" - process $proc$libresoc.v:26699$953 + attribute \src "libresoc.v:26747.7-26747.19" + process $proc$libresoc.v:26747$953 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26718.3-26719.27" - process $proc$libresoc.v:26718$948 + attribute \src "libresoc.v:26766.3-26767.27" + process $proc$libresoc.v:26766$948 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26720.3-26728.6" - process $proc$libresoc.v:26720$949 + attribute \src "libresoc.v:26768.3-26776.6" + process $proc$libresoc.v:26768$949 assign { } { } assign { } { } assign $0\q_int$next[0:0]$950 $1\q_int$next[0:0]$951 - attribute \src "libresoc.v:26721.5-26721.29" + attribute \src "libresoc.v:26769.5-26769.29" switch \initial - attribute \src "libresoc.v:26721.9-26721.17" + attribute \src "libresoc.v:26769.9-26769.17" case 1'1 case end @@ -40298,49 +40334,49 @@ module \alu_l$61 sync always update \q_int$next $0\q_int$next[0:0]$950 end - connect \$9 $and$libresoc.v:26710$940_Y - connect \$11 $or$libresoc.v:26711$941_Y - connect \$13 $not$libresoc.v:26712$942_Y - connect \$15 $or$libresoc.v:26713$943_Y - connect \$1 $not$libresoc.v:26714$944_Y - connect \$3 $and$libresoc.v:26715$945_Y - connect \$5 $or$libresoc.v:26716$946_Y - connect \$7 $not$libresoc.v:26717$947_Y + connect \$9 $and$libresoc.v:26758$940_Y + connect \$11 $or$libresoc.v:26759$941_Y + connect \$13 $not$libresoc.v:26760$942_Y + connect \$15 $or$libresoc.v:26761$943_Y + connect \$1 $not$libresoc.v:26762$944_Y + connect \$3 $and$libresoc.v:26763$945_Y + connect \$5 $or$libresoc.v:26764$946_Y + connect \$7 $not$libresoc.v:26765$947_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26736.1-26794.10" +attribute \src "libresoc.v:26784.1-26842.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_l" attribute \generator "nMigen" module \alu_l$73 - attribute \src "libresoc.v:26737.7-26737.20" + attribute \src "libresoc.v:26785.7-26785.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26782.3-26790.6" + attribute \src "libresoc.v:26830.3-26838.6" wire $0\q_int$next[0:0]$964 - attribute \src "libresoc.v:26780.3-26781.27" + attribute \src "libresoc.v:26828.3-26829.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26782.3-26790.6" + attribute \src "libresoc.v:26830.3-26838.6" wire $1\q_int$next[0:0]$965 - attribute \src "libresoc.v:26761.7-26761.19" + attribute \src "libresoc.v:26809.7-26809.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26772.17-26772.96" - wire $and$libresoc.v:26772$954_Y - attribute \src "libresoc.v:26777.17-26777.96" - wire $and$libresoc.v:26777$959_Y - attribute \src "libresoc.v:26774.18-26774.93" - wire $not$libresoc.v:26774$956_Y - attribute \src "libresoc.v:26776.17-26776.92" - wire $not$libresoc.v:26776$958_Y - attribute \src "libresoc.v:26779.17-26779.92" - wire $not$libresoc.v:26779$961_Y - attribute \src "libresoc.v:26773.18-26773.98" - wire $or$libresoc.v:26773$955_Y - attribute \src "libresoc.v:26775.18-26775.99" - wire $or$libresoc.v:26775$957_Y - attribute \src "libresoc.v:26778.17-26778.97" - wire $or$libresoc.v:26778$960_Y + attribute \src "libresoc.v:26820.17-26820.96" + wire $and$libresoc.v:26820$954_Y + attribute \src "libresoc.v:26825.17-26825.96" + wire $and$libresoc.v:26825$959_Y + attribute \src "libresoc.v:26822.18-26822.93" + wire $not$libresoc.v:26822$956_Y + attribute \src "libresoc.v:26824.17-26824.92" + wire $not$libresoc.v:26824$958_Y + attribute \src "libresoc.v:26827.17-26827.92" + wire $not$libresoc.v:26827$961_Y + attribute \src "libresoc.v:26821.18-26821.98" + wire $or$libresoc.v:26821$955_Y + attribute \src "libresoc.v:26823.18-26823.99" + wire $or$libresoc.v:26823$957_Y + attribute \src "libresoc.v:26826.17-26826.97" + wire $or$libresoc.v:26826$960_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -40357,11 +40393,11 @@ module \alu_l$73 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:26737.7-26737.15" + attribute \src "libresoc.v:26785.7-26785.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu @@ -40378,7 +40414,7 @@ module \alu_l$73 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:26772$954 + cell $and $and$libresoc.v:26820$954 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40386,10 +40422,10 @@ module \alu_l$73 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26772$954_Y + connect \Y $and$libresoc.v:26820$954_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:26777$959 + cell $and $and$libresoc.v:26825$959 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40397,34 +40433,34 @@ module \alu_l$73 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26777$959_Y + connect \Y $and$libresoc.v:26825$959_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:26774$956 + cell $not $not$libresoc.v:26822$956 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26774$956_Y + connect \Y $not$libresoc.v:26822$956_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:26776$958 + cell $not $not$libresoc.v:26824$958 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26776$958_Y + connect \Y $not$libresoc.v:26824$958_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:26779$961 + cell $not $not$libresoc.v:26827$961 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26779$961_Y + connect \Y $not$libresoc.v:26827$961_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:26773$955 + cell $or $or$libresoc.v:26821$955 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40432,10 +40468,10 @@ module \alu_l$73 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26773$955_Y + connect \Y $or$libresoc.v:26821$955_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:26775$957 + cell $or $or$libresoc.v:26823$957 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40443,10 +40479,10 @@ module \alu_l$73 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26775$957_Y + connect \Y $or$libresoc.v:26823$957_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:26778$960 + cell $or $or$libresoc.v:26826$960 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40454,39 +40490,39 @@ module \alu_l$73 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26778$960_Y + connect \Y $or$libresoc.v:26826$960_Y end - attribute \src "libresoc.v:26737.7-26737.20" - process $proc$libresoc.v:26737$966 + attribute \src "libresoc.v:26785.7-26785.20" + process $proc$libresoc.v:26785$966 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26761.7-26761.19" - process $proc$libresoc.v:26761$967 + attribute \src "libresoc.v:26809.7-26809.19" + process $proc$libresoc.v:26809$967 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26780.3-26781.27" - process $proc$libresoc.v:26780$962 + attribute \src "libresoc.v:26828.3-26829.27" + process $proc$libresoc.v:26828$962 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26782.3-26790.6" - process $proc$libresoc.v:26782$963 + attribute \src "libresoc.v:26830.3-26838.6" + process $proc$libresoc.v:26830$963 assign { } { } assign { } { } assign $0\q_int$next[0:0]$964 $1\q_int$next[0:0]$965 - attribute \src "libresoc.v:26783.5-26783.29" + attribute \src "libresoc.v:26831.5-26831.29" switch \initial - attribute \src "libresoc.v:26783.9-26783.17" + attribute \src "libresoc.v:26831.9-26831.17" case 1'1 case end @@ -40502,49 +40538,49 @@ module \alu_l$73 sync always update \q_int$next $0\q_int$next[0:0]$964 end - connect \$9 $and$libresoc.v:26772$954_Y - connect \$11 $or$libresoc.v:26773$955_Y - connect \$13 $not$libresoc.v:26774$956_Y - connect \$15 $or$libresoc.v:26775$957_Y - connect \$1 $not$libresoc.v:26776$958_Y - connect \$3 $and$libresoc.v:26777$959_Y - connect \$5 $or$libresoc.v:26778$960_Y - connect \$7 $not$libresoc.v:26779$961_Y + connect \$9 $and$libresoc.v:26820$954_Y + connect \$11 $or$libresoc.v:26821$955_Y + connect \$13 $not$libresoc.v:26822$956_Y + connect \$15 $or$libresoc.v:26823$957_Y + connect \$1 $not$libresoc.v:26824$958_Y + connect \$3 $and$libresoc.v:26825$959_Y + connect \$5 $or$libresoc.v:26826$960_Y + connect \$7 $not$libresoc.v:26827$961_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26798.1-26856.10" +attribute \src "libresoc.v:26846.1-26904.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_l" attribute \generator "nMigen" module \alu_l$90 - attribute \src "libresoc.v:26799.7-26799.20" + attribute \src "libresoc.v:26847.7-26847.20" wire $0\initial[0:0] - attribute \src "libresoc.v:26844.3-26852.6" + attribute \src "libresoc.v:26892.3-26900.6" wire $0\q_int$next[0:0]$978 - attribute \src "libresoc.v:26842.3-26843.27" + attribute \src "libresoc.v:26890.3-26891.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:26844.3-26852.6" + attribute \src "libresoc.v:26892.3-26900.6" wire $1\q_int$next[0:0]$979 - attribute \src "libresoc.v:26823.7-26823.19" + attribute \src "libresoc.v:26871.7-26871.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:26834.17-26834.96" - wire $and$libresoc.v:26834$968_Y - attribute \src "libresoc.v:26839.17-26839.96" - wire $and$libresoc.v:26839$973_Y - attribute \src "libresoc.v:26836.18-26836.93" - wire $not$libresoc.v:26836$970_Y - attribute \src "libresoc.v:26838.17-26838.92" - wire $not$libresoc.v:26838$972_Y - attribute \src "libresoc.v:26841.17-26841.92" - wire $not$libresoc.v:26841$975_Y - attribute \src "libresoc.v:26835.18-26835.98" - wire $or$libresoc.v:26835$969_Y - attribute \src "libresoc.v:26837.18-26837.99" - wire $or$libresoc.v:26837$971_Y - attribute \src "libresoc.v:26840.17-26840.97" - wire $or$libresoc.v:26840$974_Y + attribute \src "libresoc.v:26882.17-26882.96" + wire $and$libresoc.v:26882$968_Y + attribute \src "libresoc.v:26887.17-26887.96" + wire $and$libresoc.v:26887$973_Y + attribute \src "libresoc.v:26884.18-26884.93" + wire $not$libresoc.v:26884$970_Y + attribute \src "libresoc.v:26886.17-26886.92" + wire $not$libresoc.v:26886$972_Y + attribute \src "libresoc.v:26889.17-26889.92" + wire $not$libresoc.v:26889$975_Y + attribute \src "libresoc.v:26883.18-26883.98" + wire $or$libresoc.v:26883$969_Y + attribute \src "libresoc.v:26885.18-26885.99" + wire $or$libresoc.v:26885$971_Y + attribute \src "libresoc.v:26888.17-26888.97" + wire $or$libresoc.v:26888$974_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -40561,11 +40597,11 @@ module \alu_l$90 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:26799.7-26799.15" + attribute \src "libresoc.v:26847.7-26847.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alu @@ -40582,7 +40618,7 @@ module \alu_l$90 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alu attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:26834$968 + cell $and $and$libresoc.v:26882$968 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40590,10 +40626,10 @@ module \alu_l$90 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:26834$968_Y + connect \Y $and$libresoc.v:26882$968_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:26839$973 + cell $and $and$libresoc.v:26887$973 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40601,34 +40637,34 @@ module \alu_l$90 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:26839$973_Y + connect \Y $and$libresoc.v:26887$973_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:26836$970 + cell $not $not$libresoc.v:26884$970 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alu - connect \Y $not$libresoc.v:26836$970_Y + connect \Y $not$libresoc.v:26884$970_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:26838$972 + cell $not $not$libresoc.v:26886$972 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26838$972_Y + connect \Y $not$libresoc.v:26886$972_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:26841$975 + cell $not $not$libresoc.v:26889$975 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alu - connect \Y $not$libresoc.v:26841$975_Y + connect \Y $not$libresoc.v:26889$975_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:26835$969 + cell $or $or$libresoc.v:26883$969 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40636,10 +40672,10 @@ module \alu_l$90 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alu - connect \Y $or$libresoc.v:26835$969_Y + connect \Y $or$libresoc.v:26883$969_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:26837$971 + cell $or $or$libresoc.v:26885$971 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40647,10 +40683,10 @@ module \alu_l$90 parameter \Y_WIDTH 1 connect \A \q_alu connect \B \q_int - connect \Y $or$libresoc.v:26837$971_Y + connect \Y $or$libresoc.v:26885$971_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:26840$974 + cell $or $or$libresoc.v:26888$974 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -40658,39 +40694,39 @@ module \alu_l$90 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alu - connect \Y $or$libresoc.v:26840$974_Y + connect \Y $or$libresoc.v:26888$974_Y end - attribute \src "libresoc.v:26799.7-26799.20" - process $proc$libresoc.v:26799$980 + attribute \src "libresoc.v:26847.7-26847.20" + process $proc$libresoc.v:26847$980 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:26823.7-26823.19" - process $proc$libresoc.v:26823$981 + attribute \src "libresoc.v:26871.7-26871.19" + process $proc$libresoc.v:26871$981 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:26842.3-26843.27" - process $proc$libresoc.v:26842$976 + attribute \src "libresoc.v:26890.3-26891.27" + process $proc$libresoc.v:26890$976 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:26844.3-26852.6" - process $proc$libresoc.v:26844$977 + attribute \src "libresoc.v:26892.3-26900.6" + process $proc$libresoc.v:26892$977 assign { } { } assign { } { } assign $0\q_int$next[0:0]$978 $1\q_int$next[0:0]$979 - attribute \src "libresoc.v:26845.5-26845.29" + attribute \src "libresoc.v:26893.5-26893.29" switch \initial - attribute \src "libresoc.v:26845.9-26845.17" + attribute \src "libresoc.v:26893.9-26893.17" case 1'1 case end @@ -40706,26 +40742,26 @@ module \alu_l$90 sync always update \q_int$next $0\q_int$next[0:0]$978 end - connect \$9 $and$libresoc.v:26834$968_Y - connect \$11 $or$libresoc.v:26835$969_Y - connect \$13 $not$libresoc.v:26836$970_Y - connect \$15 $or$libresoc.v:26837$971_Y - connect \$1 $not$libresoc.v:26838$972_Y - connect \$3 $and$libresoc.v:26839$973_Y - connect \$5 $or$libresoc.v:26840$974_Y - connect \$7 $not$libresoc.v:26841$975_Y + connect \$9 $and$libresoc.v:26882$968_Y + connect \$11 $or$libresoc.v:26883$969_Y + connect \$13 $not$libresoc.v:26884$970_Y + connect \$15 $or$libresoc.v:26885$971_Y + connect \$1 $not$libresoc.v:26886$972_Y + connect \$3 $and$libresoc.v:26887$973_Y + connect \$5 $or$libresoc.v:26888$974_Y + connect \$7 $not$libresoc.v:26889$975_Y connect \qlq_alu \$15 connect \qn_alu \$13 connect \q_alu \$11 end -attribute \src "libresoc.v:26860.1-27873.10" +attribute \src "libresoc.v:26908.1-27921.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0" attribute \generator "nMigen" module \alu_logical0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 31 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 25 \cr_a @@ -41596,7 +41632,7 @@ module \alu_logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 28 \xer_so attribute \module_not_derived 1 - attribute \src "libresoc.v:27733.17-27787.4" + attribute \src "libresoc.v:27781.17-27835.4" cell \logical_pipe1 \logical_pipe1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -41653,7 +41689,7 @@ module \alu_logical0 connect \xer_so_ok \logical_pipe1_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:27788.17-27843.4" + attribute \src "libresoc.v:27836.17-27891.4" cell \logical_pipe2 \logical_pipe2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -41711,13 +41747,13 @@ module \alu_logical0 connect \xer_so_ok \logical_pipe2_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:27844.10-27847.4" + attribute \src "libresoc.v:27892.10-27895.4" cell \n$47 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:27848.10-27851.4" + attribute \src "libresoc.v:27896.10-27899.4" cell \p$46 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i @@ -41744,14 +41780,14 @@ module \alu_logical0 connect \logical_pipe1_n_ready_i \logical_pipe2_p_ready_o connect \logical_pipe2_p_valid_i \logical_pipe1_n_valid_o end -attribute \src "libresoc.v:27877.1-29094.10" +attribute \src "libresoc.v:27925.1-29142.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0" attribute \generator "nMigen" module \alu_mul0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 29 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 21 \cr_a @@ -42794,7 +42830,7 @@ module \alu_mul0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 5 \xer_so_ok attribute \module_not_derived 1 - attribute \src "libresoc.v:28922.13-28963.4" + attribute \src "libresoc.v:28970.13-29011.4" cell \mul_pipe1 \mul_pipe1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -42838,7 +42874,7 @@ module \alu_mul0 connect \xer_so$16 \mul_pipe1_xer_so$17 end attribute \module_not_derived 1 - attribute \src "libresoc.v:28964.13-29006.4" + attribute \src "libresoc.v:29012.13-29054.4" cell \mul_pipe2 \mul_pipe2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -42883,7 +42919,7 @@ module \alu_mul0 connect \xer_so$14 \mul_pipe2_xer_so$31 end attribute \module_not_derived 1 - attribute \src "libresoc.v:29007.13-29052.4" + attribute \src "libresoc.v:29055.13-29100.4" cell \mul_pipe3 \mul_pipe3 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -42931,13 +42967,13 @@ module \alu_mul0 connect \xer_so_ok \mul_pipe3_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:29053.10-29056.4" + attribute \src "libresoc.v:29101.10-29104.4" cell \n$92 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:29057.10-29060.4" + attribute \src "libresoc.v:29105.10-29108.4" cell \p$91 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i @@ -42976,14 +43012,14 @@ module \alu_mul0 connect \mul_pipe1_n_ready_i \mul_pipe2_p_ready_o connect \mul_pipe2_p_valid_i \mul_pipe1_n_valid_o end -attribute \src "libresoc.v:29098.1-30131.10" +attribute \src "libresoc.v:29146.1-30179.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0" attribute \generator "nMigen" module \alu_shift_rot0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 34 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 25 \cr_a @@ -43866,19 +43902,19 @@ module \alu_shift_rot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire input 30 \xer_so attribute \module_not_derived 1 - attribute \src "libresoc.v:29983.11-29986.4" + attribute \src "libresoc.v:30031.11-30034.4" cell \n$109 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:29987.11-29990.4" + attribute \src "libresoc.v:30035.11-30038.4" cell \p$108 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:29991.15-30047.4" + attribute \src "libresoc.v:30039.15-30095.4" cell \pipe1$110 \pipe1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -43937,7 +43973,7 @@ module \alu_shift_rot0 connect \xer_so_ok \pipe1_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:30048.15-30105.4" + attribute \src "libresoc.v:30096.15-30153.4" cell \pipe2$115 \pipe2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -44022,14 +44058,14 @@ module \alu_shift_rot0 connect \pipe1_n_ready_i \pipe2_p_ready_o connect \pipe2_p_valid_i \pipe1_n_valid_o end -attribute \src "libresoc.v:30135.1-30693.10" +attribute \src "libresoc.v:30183.1-30741.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0" attribute \generator "nMigen" module \alu_spr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 28 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 16 \fast1 @@ -44520,19 +44556,19 @@ module \alu_spr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 5 \xer_so_ok attribute \module_not_derived 1 - attribute \src "libresoc.v:30628.10-30631.4" + attribute \src "libresoc.v:30676.10-30679.4" cell \n$63 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:30632.10-30635.4" + attribute \src "libresoc.v:30680.10-30683.4" cell \p$62 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:30636.13-30671.4" + attribute \src "libresoc.v:30684.13-30719.4" cell \pipe$64 \pipe connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -44591,14 +44627,14 @@ module \alu_spr0 connect \p_ready_o \pipe_p_ready_o connect \pipe_p_valid_i \p_valid_i end -attribute \src "libresoc.v:30697.1-31570.10" +attribute \src "libresoc.v:30745.1-31618.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0" attribute \generator "nMigen" module \alu_trap0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 29 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 output 19 \fast1 @@ -45357,19 +45393,19 @@ module \alu_trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \trap_op__traptype$36 attribute \module_not_derived 1 - attribute \src "libresoc.v:31458.10-31461.4" + attribute \src "libresoc.v:31506.10-31509.4" cell \n$31 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:31462.10-31465.4" + attribute \src "libresoc.v:31510.10-31513.4" cell \p$30 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:31466.14-31501.4" + attribute \src "libresoc.v:31514.14-31549.4" cell \pipe1$32 \pipe1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -45407,7 +45443,7 @@ module \alu_trap0 connect \trap_op__traptype$8 \pipe1_trap_op__traptype$10 end attribute \module_not_derived 1 - attribute \src "libresoc.v:31502.14-31543.4" + attribute \src "libresoc.v:31550.14-31591.4" cell \pipe2$35 \pipe2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -45477,37 +45513,37 @@ module \alu_trap0 connect \pipe1_n_ready_i \pipe2_p_ready_o connect \pipe2_p_valid_i \pipe1_n_valid_o end -attribute \src "libresoc.v:31574.1-31632.10" +attribute \src "libresoc.v:31622.1-31680.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alui_l" attribute \generator "nMigen" module \alui_l - attribute \src "libresoc.v:31575.7-31575.20" + attribute \src "libresoc.v:31623.7-31623.20" wire $0\initial[0:0] - attribute \src "libresoc.v:31620.3-31628.6" + attribute \src "libresoc.v:31668.3-31676.6" wire $0\q_int$next[0:0]$992 - attribute \src "libresoc.v:31618.3-31619.27" + attribute \src "libresoc.v:31666.3-31667.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:31620.3-31628.6" + attribute \src "libresoc.v:31668.3-31676.6" wire $1\q_int$next[0:0]$993 - attribute \src "libresoc.v:31599.7-31599.19" + attribute \src "libresoc.v:31647.7-31647.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:31610.17-31610.96" - wire $and$libresoc.v:31610$982_Y - attribute \src "libresoc.v:31615.17-31615.96" - wire $and$libresoc.v:31615$987_Y - attribute \src "libresoc.v:31612.18-31612.94" - wire $not$libresoc.v:31612$984_Y - attribute \src "libresoc.v:31614.17-31614.93" - wire $not$libresoc.v:31614$986_Y - attribute \src "libresoc.v:31617.17-31617.93" - wire $not$libresoc.v:31617$989_Y - attribute \src "libresoc.v:31611.18-31611.99" - wire $or$libresoc.v:31611$983_Y - attribute \src "libresoc.v:31613.18-31613.100" - wire $or$libresoc.v:31613$985_Y - attribute \src "libresoc.v:31616.17-31616.98" - wire $or$libresoc.v:31616$988_Y + attribute \src "libresoc.v:31658.17-31658.96" + wire $and$libresoc.v:31658$982_Y + attribute \src "libresoc.v:31663.17-31663.96" + wire $and$libresoc.v:31663$987_Y + attribute \src "libresoc.v:31660.18-31660.94" + wire $not$libresoc.v:31660$984_Y + attribute \src "libresoc.v:31662.17-31662.93" + wire $not$libresoc.v:31662$986_Y + attribute \src "libresoc.v:31665.17-31665.93" + wire $not$libresoc.v:31665$989_Y + attribute \src "libresoc.v:31659.18-31659.99" + wire $or$libresoc.v:31659$983_Y + attribute \src "libresoc.v:31661.18-31661.100" + wire $or$libresoc.v:31661$985_Y + attribute \src "libresoc.v:31664.17-31664.98" + wire $or$libresoc.v:31664$988_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -45524,11 +45560,11 @@ module \alui_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:31575.7-31575.15" + attribute \src "libresoc.v:31623.7-31623.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui @@ -45545,7 +45581,7 @@ module \alui_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:31610$982 + cell $and $and$libresoc.v:31658$982 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45553,10 +45589,10 @@ module \alui_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:31610$982_Y + connect \Y $and$libresoc.v:31658$982_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:31615$987 + cell $and $and$libresoc.v:31663$987 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45564,34 +45600,34 @@ module \alui_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:31615$987_Y + connect \Y $and$libresoc.v:31663$987_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:31612$984 + cell $not $not$libresoc.v:31660$984 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:31612$984_Y + connect \Y $not$libresoc.v:31660$984_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:31614$986 + cell $not $not$libresoc.v:31662$986 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31614$986_Y + connect \Y $not$libresoc.v:31662$986_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:31617$989 + cell $not $not$libresoc.v:31665$989 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31617$989_Y + connect \Y $not$libresoc.v:31665$989_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:31611$983 + cell $or $or$libresoc.v:31659$983 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45599,10 +45635,10 @@ module \alui_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:31611$983_Y + connect \Y $or$libresoc.v:31659$983_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:31613$985 + cell $or $or$libresoc.v:31661$985 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45610,10 +45646,10 @@ module \alui_l parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:31613$985_Y + connect \Y $or$libresoc.v:31661$985_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:31616$988 + cell $or $or$libresoc.v:31664$988 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45621,39 +45657,39 @@ module \alui_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:31616$988_Y + connect \Y $or$libresoc.v:31664$988_Y end - attribute \src "libresoc.v:31575.7-31575.20" - process $proc$libresoc.v:31575$994 + attribute \src "libresoc.v:31623.7-31623.20" + process $proc$libresoc.v:31623$994 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:31599.7-31599.19" - process $proc$libresoc.v:31599$995 + attribute \src "libresoc.v:31647.7-31647.19" + process $proc$libresoc.v:31647$995 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:31618.3-31619.27" - process $proc$libresoc.v:31618$990 + attribute \src "libresoc.v:31666.3-31667.27" + process $proc$libresoc.v:31666$990 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:31620.3-31628.6" - process $proc$libresoc.v:31620$991 + attribute \src "libresoc.v:31668.3-31676.6" + process $proc$libresoc.v:31668$991 assign { } { } assign { } { } assign $0\q_int$next[0:0]$992 $1\q_int$next[0:0]$993 - attribute \src "libresoc.v:31621.5-31621.29" + attribute \src "libresoc.v:31669.5-31669.29" switch \initial - attribute \src "libresoc.v:31621.9-31621.17" + attribute \src "libresoc.v:31669.9-31669.17" case 1'1 case end @@ -45669,49 +45705,49 @@ module \alui_l sync always update \q_int$next $0\q_int$next[0:0]$992 end - connect \$9 $and$libresoc.v:31610$982_Y - connect \$11 $or$libresoc.v:31611$983_Y - connect \$13 $not$libresoc.v:31612$984_Y - connect \$15 $or$libresoc.v:31613$985_Y - connect \$1 $not$libresoc.v:31614$986_Y - connect \$3 $and$libresoc.v:31615$987_Y - connect \$5 $or$libresoc.v:31616$988_Y - connect \$7 $not$libresoc.v:31617$989_Y + connect \$9 $and$libresoc.v:31658$982_Y + connect \$11 $or$libresoc.v:31659$983_Y + connect \$13 $not$libresoc.v:31660$984_Y + connect \$15 $or$libresoc.v:31661$985_Y + connect \$1 $not$libresoc.v:31662$986_Y + connect \$3 $and$libresoc.v:31663$987_Y + connect \$5 $or$libresoc.v:31664$988_Y + connect \$7 $not$libresoc.v:31665$989_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:31636.1-31694.10" +attribute \src "libresoc.v:31684.1-31742.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alui_l" attribute \generator "nMigen" module \alui_l$106 - attribute \src "libresoc.v:31637.7-31637.20" + attribute \src "libresoc.v:31685.7-31685.20" wire $0\initial[0:0] - attribute \src "libresoc.v:31682.3-31690.6" + attribute \src "libresoc.v:31730.3-31738.6" wire $0\q_int$next[0:0]$1006 - attribute \src "libresoc.v:31680.3-31681.27" + attribute \src "libresoc.v:31728.3-31729.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:31682.3-31690.6" + attribute \src "libresoc.v:31730.3-31738.6" wire $1\q_int$next[0:0]$1007 - attribute \src "libresoc.v:31661.7-31661.19" + attribute \src "libresoc.v:31709.7-31709.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:31672.17-31672.96" - wire $and$libresoc.v:31672$996_Y - attribute \src "libresoc.v:31677.17-31677.96" - wire $and$libresoc.v:31677$1001_Y - attribute \src "libresoc.v:31674.18-31674.94" - wire $not$libresoc.v:31674$998_Y - attribute \src "libresoc.v:31676.17-31676.93" - wire $not$libresoc.v:31676$1000_Y - attribute \src "libresoc.v:31679.17-31679.93" - wire $not$libresoc.v:31679$1003_Y - attribute \src "libresoc.v:31673.18-31673.99" - wire $or$libresoc.v:31673$997_Y - attribute \src "libresoc.v:31675.18-31675.100" - wire $or$libresoc.v:31675$999_Y - attribute \src "libresoc.v:31678.17-31678.98" - wire $or$libresoc.v:31678$1002_Y + attribute \src "libresoc.v:31720.17-31720.96" + wire $and$libresoc.v:31720$996_Y + attribute \src "libresoc.v:31725.17-31725.96" + wire $and$libresoc.v:31725$1001_Y + attribute \src "libresoc.v:31722.18-31722.94" + wire $not$libresoc.v:31722$998_Y + attribute \src "libresoc.v:31724.17-31724.93" + wire $not$libresoc.v:31724$1000_Y + attribute \src "libresoc.v:31727.17-31727.93" + wire $not$libresoc.v:31727$1003_Y + attribute \src "libresoc.v:31721.18-31721.99" + wire $or$libresoc.v:31721$997_Y + attribute \src "libresoc.v:31723.18-31723.100" + wire $or$libresoc.v:31723$999_Y + attribute \src "libresoc.v:31726.17-31726.98" + wire $or$libresoc.v:31726$1002_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -45728,11 +45764,11 @@ module \alui_l$106 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:31637.7-31637.15" + attribute \src "libresoc.v:31685.7-31685.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui @@ -45749,7 +45785,7 @@ module \alui_l$106 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:31672$996 + cell $and $and$libresoc.v:31720$996 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45757,10 +45793,10 @@ module \alui_l$106 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:31672$996_Y + connect \Y $and$libresoc.v:31720$996_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:31677$1001 + cell $and $and$libresoc.v:31725$1001 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45768,34 +45804,34 @@ module \alui_l$106 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:31677$1001_Y + connect \Y $and$libresoc.v:31725$1001_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:31674$998 + cell $not $not$libresoc.v:31722$998 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:31674$998_Y + connect \Y $not$libresoc.v:31722$998_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:31676$1000 + cell $not $not$libresoc.v:31724$1000 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31676$1000_Y + connect \Y $not$libresoc.v:31724$1000_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:31679$1003 + cell $not $not$libresoc.v:31727$1003 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31679$1003_Y + connect \Y $not$libresoc.v:31727$1003_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:31673$997 + cell $or $or$libresoc.v:31721$997 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45803,10 +45839,10 @@ module \alui_l$106 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:31673$997_Y + connect \Y $or$libresoc.v:31721$997_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:31675$999 + cell $or $or$libresoc.v:31723$999 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45814,10 +45850,10 @@ module \alui_l$106 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:31675$999_Y + connect \Y $or$libresoc.v:31723$999_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:31678$1002 + cell $or $or$libresoc.v:31726$1002 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45825,39 +45861,39 @@ module \alui_l$106 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:31678$1002_Y + connect \Y $or$libresoc.v:31726$1002_Y end - attribute \src "libresoc.v:31637.7-31637.20" - process $proc$libresoc.v:31637$1008 + attribute \src "libresoc.v:31685.7-31685.20" + process $proc$libresoc.v:31685$1008 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:31661.7-31661.19" - process $proc$libresoc.v:31661$1009 + attribute \src "libresoc.v:31709.7-31709.19" + process $proc$libresoc.v:31709$1009 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:31680.3-31681.27" - process $proc$libresoc.v:31680$1004 + attribute \src "libresoc.v:31728.3-31729.27" + process $proc$libresoc.v:31728$1004 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:31682.3-31690.6" - process $proc$libresoc.v:31682$1005 + attribute \src "libresoc.v:31730.3-31738.6" + process $proc$libresoc.v:31730$1005 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1006 $1\q_int$next[0:0]$1007 - attribute \src "libresoc.v:31683.5-31683.29" + attribute \src "libresoc.v:31731.5-31731.29" switch \initial - attribute \src "libresoc.v:31683.9-31683.17" + attribute \src "libresoc.v:31731.9-31731.17" case 1'1 case end @@ -45873,49 +45909,49 @@ module \alui_l$106 sync always update \q_int$next $0\q_int$next[0:0]$1006 end - connect \$9 $and$libresoc.v:31672$996_Y - connect \$11 $or$libresoc.v:31673$997_Y - connect \$13 $not$libresoc.v:31674$998_Y - connect \$15 $or$libresoc.v:31675$999_Y - connect \$1 $not$libresoc.v:31676$1000_Y - connect \$3 $and$libresoc.v:31677$1001_Y - connect \$5 $or$libresoc.v:31678$1002_Y - connect \$7 $not$libresoc.v:31679$1003_Y + connect \$9 $and$libresoc.v:31720$996_Y + connect \$11 $or$libresoc.v:31721$997_Y + connect \$13 $not$libresoc.v:31722$998_Y + connect \$15 $or$libresoc.v:31723$999_Y + connect \$1 $not$libresoc.v:31724$1000_Y + connect \$3 $and$libresoc.v:31725$1001_Y + connect \$5 $or$libresoc.v:31726$1002_Y + connect \$7 $not$libresoc.v:31727$1003_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:31698.1-31756.10" +attribute \src "libresoc.v:31746.1-31804.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alui_l" attribute \generator "nMigen" module \alui_l$124 - attribute \src "libresoc.v:31699.7-31699.20" + attribute \src "libresoc.v:31747.7-31747.20" wire $0\initial[0:0] - attribute \src "libresoc.v:31744.3-31752.6" + attribute \src "libresoc.v:31792.3-31800.6" wire $0\q_int$next[0:0]$1020 - attribute \src "libresoc.v:31742.3-31743.27" + attribute \src "libresoc.v:31790.3-31791.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:31744.3-31752.6" + attribute \src "libresoc.v:31792.3-31800.6" wire $1\q_int$next[0:0]$1021 - attribute \src "libresoc.v:31723.7-31723.19" + attribute \src "libresoc.v:31771.7-31771.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:31734.17-31734.96" - wire $and$libresoc.v:31734$1010_Y - attribute \src "libresoc.v:31739.17-31739.96" - wire $and$libresoc.v:31739$1015_Y - attribute \src "libresoc.v:31736.18-31736.94" - wire $not$libresoc.v:31736$1012_Y - attribute \src "libresoc.v:31738.17-31738.93" - wire $not$libresoc.v:31738$1014_Y - attribute \src "libresoc.v:31741.17-31741.93" - wire $not$libresoc.v:31741$1017_Y - attribute \src "libresoc.v:31735.18-31735.99" - wire $or$libresoc.v:31735$1011_Y - attribute \src "libresoc.v:31737.18-31737.100" - wire $or$libresoc.v:31737$1013_Y - attribute \src "libresoc.v:31740.17-31740.98" - wire $or$libresoc.v:31740$1016_Y + attribute \src "libresoc.v:31782.17-31782.96" + wire $and$libresoc.v:31782$1010_Y + attribute \src "libresoc.v:31787.17-31787.96" + wire $and$libresoc.v:31787$1015_Y + attribute \src "libresoc.v:31784.18-31784.94" + wire $not$libresoc.v:31784$1012_Y + attribute \src "libresoc.v:31786.17-31786.93" + wire $not$libresoc.v:31786$1014_Y + attribute \src "libresoc.v:31789.17-31789.93" + wire $not$libresoc.v:31789$1017_Y + attribute \src "libresoc.v:31783.18-31783.99" + wire $or$libresoc.v:31783$1011_Y + attribute \src "libresoc.v:31785.18-31785.100" + wire $or$libresoc.v:31785$1013_Y + attribute \src "libresoc.v:31788.17-31788.98" + wire $or$libresoc.v:31788$1016_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -45932,11 +45968,11 @@ module \alui_l$124 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:31699.7-31699.15" + attribute \src "libresoc.v:31747.7-31747.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui @@ -45953,7 +45989,7 @@ module \alui_l$124 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:31734$1010 + cell $and $and$libresoc.v:31782$1010 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45961,10 +45997,10 @@ module \alui_l$124 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:31734$1010_Y + connect \Y $and$libresoc.v:31782$1010_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:31739$1015 + cell $and $and$libresoc.v:31787$1015 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -45972,34 +46008,34 @@ module \alui_l$124 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:31739$1015_Y + connect \Y $and$libresoc.v:31787$1015_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:31736$1012 + cell $not $not$libresoc.v:31784$1012 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:31736$1012_Y + connect \Y $not$libresoc.v:31784$1012_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:31738$1014 + cell $not $not$libresoc.v:31786$1014 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31738$1014_Y + connect \Y $not$libresoc.v:31786$1014_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:31741$1017 + cell $not $not$libresoc.v:31789$1017 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31741$1017_Y + connect \Y $not$libresoc.v:31789$1017_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:31735$1011 + cell $or $or$libresoc.v:31783$1011 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46007,10 +46043,10 @@ module \alui_l$124 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:31735$1011_Y + connect \Y $or$libresoc.v:31783$1011_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:31737$1013 + cell $or $or$libresoc.v:31785$1013 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46018,10 +46054,10 @@ module \alui_l$124 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:31737$1013_Y + connect \Y $or$libresoc.v:31785$1013_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:31740$1016 + cell $or $or$libresoc.v:31788$1016 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46029,39 +46065,39 @@ module \alui_l$124 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:31740$1016_Y + connect \Y $or$libresoc.v:31788$1016_Y end - attribute \src "libresoc.v:31699.7-31699.20" - process $proc$libresoc.v:31699$1022 + attribute \src "libresoc.v:31747.7-31747.20" + process $proc$libresoc.v:31747$1022 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:31723.7-31723.19" - process $proc$libresoc.v:31723$1023 + attribute \src "libresoc.v:31771.7-31771.19" + process $proc$libresoc.v:31771$1023 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:31742.3-31743.27" - process $proc$libresoc.v:31742$1018 + attribute \src "libresoc.v:31790.3-31791.27" + process $proc$libresoc.v:31790$1018 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:31744.3-31752.6" - process $proc$libresoc.v:31744$1019 + attribute \src "libresoc.v:31792.3-31800.6" + process $proc$libresoc.v:31792$1019 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1020 $1\q_int$next[0:0]$1021 - attribute \src "libresoc.v:31745.5-31745.29" + attribute \src "libresoc.v:31793.5-31793.29" switch \initial - attribute \src "libresoc.v:31745.9-31745.17" + attribute \src "libresoc.v:31793.9-31793.17" case 1'1 case end @@ -46077,49 +46113,49 @@ module \alui_l$124 sync always update \q_int$next $0\q_int$next[0:0]$1020 end - connect \$9 $and$libresoc.v:31734$1010_Y - connect \$11 $or$libresoc.v:31735$1011_Y - connect \$13 $not$libresoc.v:31736$1012_Y - connect \$15 $or$libresoc.v:31737$1013_Y - connect \$1 $not$libresoc.v:31738$1014_Y - connect \$3 $and$libresoc.v:31739$1015_Y - connect \$5 $or$libresoc.v:31740$1016_Y - connect \$7 $not$libresoc.v:31741$1017_Y + connect \$9 $and$libresoc.v:31782$1010_Y + connect \$11 $or$libresoc.v:31783$1011_Y + connect \$13 $not$libresoc.v:31784$1012_Y + connect \$15 $or$libresoc.v:31785$1013_Y + connect \$1 $not$libresoc.v:31786$1014_Y + connect \$3 $and$libresoc.v:31787$1015_Y + connect \$5 $or$libresoc.v:31788$1016_Y + connect \$7 $not$libresoc.v:31789$1017_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:31760.1-31818.10" +attribute \src "libresoc.v:31808.1-31866.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alui_l" attribute \generator "nMigen" module \alui_l$15 - attribute \src "libresoc.v:31761.7-31761.20" + attribute \src "libresoc.v:31809.7-31809.20" wire $0\initial[0:0] - attribute \src "libresoc.v:31806.3-31814.6" + attribute \src "libresoc.v:31854.3-31862.6" wire $0\q_int$next[0:0]$1034 - attribute \src "libresoc.v:31804.3-31805.27" + attribute \src "libresoc.v:31852.3-31853.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:31806.3-31814.6" + attribute \src "libresoc.v:31854.3-31862.6" wire $1\q_int$next[0:0]$1035 - attribute \src "libresoc.v:31785.7-31785.19" + attribute \src "libresoc.v:31833.7-31833.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:31796.17-31796.96" - wire $and$libresoc.v:31796$1024_Y - attribute \src "libresoc.v:31801.17-31801.96" - wire $and$libresoc.v:31801$1029_Y - attribute \src "libresoc.v:31798.18-31798.94" - wire $not$libresoc.v:31798$1026_Y - attribute \src "libresoc.v:31800.17-31800.93" - wire $not$libresoc.v:31800$1028_Y - attribute \src "libresoc.v:31803.17-31803.93" - wire $not$libresoc.v:31803$1031_Y - attribute \src "libresoc.v:31797.18-31797.99" - wire $or$libresoc.v:31797$1025_Y - attribute \src "libresoc.v:31799.18-31799.100" - wire $or$libresoc.v:31799$1027_Y - attribute \src "libresoc.v:31802.17-31802.98" - wire $or$libresoc.v:31802$1030_Y + attribute \src "libresoc.v:31844.17-31844.96" + wire $and$libresoc.v:31844$1024_Y + attribute \src "libresoc.v:31849.17-31849.96" + wire $and$libresoc.v:31849$1029_Y + attribute \src "libresoc.v:31846.18-31846.94" + wire $not$libresoc.v:31846$1026_Y + attribute \src "libresoc.v:31848.17-31848.93" + wire $not$libresoc.v:31848$1028_Y + attribute \src "libresoc.v:31851.17-31851.93" + wire $not$libresoc.v:31851$1031_Y + attribute \src "libresoc.v:31845.18-31845.99" + wire $or$libresoc.v:31845$1025_Y + attribute \src "libresoc.v:31847.18-31847.100" + wire $or$libresoc.v:31847$1027_Y + attribute \src "libresoc.v:31850.17-31850.98" + wire $or$libresoc.v:31850$1030_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -46136,11 +46172,11 @@ module \alui_l$15 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:31761.7-31761.15" + attribute \src "libresoc.v:31809.7-31809.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui @@ -46157,7 +46193,7 @@ module \alui_l$15 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:31796$1024 + cell $and $and$libresoc.v:31844$1024 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46165,10 +46201,10 @@ module \alui_l$15 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:31796$1024_Y + connect \Y $and$libresoc.v:31844$1024_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:31801$1029 + cell $and $and$libresoc.v:31849$1029 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46176,34 +46212,34 @@ module \alui_l$15 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:31801$1029_Y + connect \Y $and$libresoc.v:31849$1029_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:31798$1026 + cell $not $not$libresoc.v:31846$1026 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:31798$1026_Y + connect \Y $not$libresoc.v:31846$1026_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:31800$1028 + cell $not $not$libresoc.v:31848$1028 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31800$1028_Y + connect \Y $not$libresoc.v:31848$1028_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:31803$1031 + cell $not $not$libresoc.v:31851$1031 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31803$1031_Y + connect \Y $not$libresoc.v:31851$1031_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:31797$1025 + cell $or $or$libresoc.v:31845$1025 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46211,10 +46247,10 @@ module \alui_l$15 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:31797$1025_Y + connect \Y $or$libresoc.v:31845$1025_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:31799$1027 + cell $or $or$libresoc.v:31847$1027 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46222,10 +46258,10 @@ module \alui_l$15 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:31799$1027_Y + connect \Y $or$libresoc.v:31847$1027_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:31802$1030 + cell $or $or$libresoc.v:31850$1030 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46233,39 +46269,39 @@ module \alui_l$15 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:31802$1030_Y + connect \Y $or$libresoc.v:31850$1030_Y end - attribute \src "libresoc.v:31761.7-31761.20" - process $proc$libresoc.v:31761$1036 + attribute \src "libresoc.v:31809.7-31809.20" + process $proc$libresoc.v:31809$1036 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:31785.7-31785.19" - process $proc$libresoc.v:31785$1037 + attribute \src "libresoc.v:31833.7-31833.19" + process $proc$libresoc.v:31833$1037 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:31804.3-31805.27" - process $proc$libresoc.v:31804$1032 + attribute \src "libresoc.v:31852.3-31853.27" + process $proc$libresoc.v:31852$1032 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:31806.3-31814.6" - process $proc$libresoc.v:31806$1033 + attribute \src "libresoc.v:31854.3-31862.6" + process $proc$libresoc.v:31854$1033 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1034 $1\q_int$next[0:0]$1035 - attribute \src "libresoc.v:31807.5-31807.29" + attribute \src "libresoc.v:31855.5-31855.29" switch \initial - attribute \src "libresoc.v:31807.9-31807.17" + attribute \src "libresoc.v:31855.9-31855.17" case 1'1 case end @@ -46281,49 +46317,49 @@ module \alui_l$15 sync always update \q_int$next $0\q_int$next[0:0]$1034 end - connect \$9 $and$libresoc.v:31796$1024_Y - connect \$11 $or$libresoc.v:31797$1025_Y - connect \$13 $not$libresoc.v:31798$1026_Y - connect \$15 $or$libresoc.v:31799$1027_Y - connect \$1 $not$libresoc.v:31800$1028_Y - connect \$3 $and$libresoc.v:31801$1029_Y - connect \$5 $or$libresoc.v:31802$1030_Y - connect \$7 $not$libresoc.v:31803$1031_Y + connect \$9 $and$libresoc.v:31844$1024_Y + connect \$11 $or$libresoc.v:31845$1025_Y + connect \$13 $not$libresoc.v:31846$1026_Y + connect \$15 $or$libresoc.v:31847$1027_Y + connect \$1 $not$libresoc.v:31848$1028_Y + connect \$3 $and$libresoc.v:31849$1029_Y + connect \$5 $or$libresoc.v:31850$1030_Y + connect \$7 $not$libresoc.v:31851$1031_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:31822.1-31880.10" +attribute \src "libresoc.v:31870.1-31928.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alui_l" attribute \generator "nMigen" module \alui_l$28 - attribute \src "libresoc.v:31823.7-31823.20" + attribute \src "libresoc.v:31871.7-31871.20" wire $0\initial[0:0] - attribute \src "libresoc.v:31868.3-31876.6" + attribute \src "libresoc.v:31916.3-31924.6" wire $0\q_int$next[0:0]$1048 - attribute \src "libresoc.v:31866.3-31867.27" + attribute \src "libresoc.v:31914.3-31915.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:31868.3-31876.6" + attribute \src "libresoc.v:31916.3-31924.6" wire $1\q_int$next[0:0]$1049 - attribute \src "libresoc.v:31847.7-31847.19" + attribute \src "libresoc.v:31895.7-31895.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:31858.17-31858.96" - wire $and$libresoc.v:31858$1038_Y - attribute \src "libresoc.v:31863.17-31863.96" - wire $and$libresoc.v:31863$1043_Y - attribute \src "libresoc.v:31860.18-31860.94" - wire $not$libresoc.v:31860$1040_Y - attribute \src "libresoc.v:31862.17-31862.93" - wire $not$libresoc.v:31862$1042_Y - attribute \src "libresoc.v:31865.17-31865.93" - wire $not$libresoc.v:31865$1045_Y - attribute \src "libresoc.v:31859.18-31859.99" - wire $or$libresoc.v:31859$1039_Y - attribute \src "libresoc.v:31861.18-31861.100" - wire $or$libresoc.v:31861$1041_Y - attribute \src "libresoc.v:31864.17-31864.98" - wire $or$libresoc.v:31864$1044_Y + attribute \src "libresoc.v:31906.17-31906.96" + wire $and$libresoc.v:31906$1038_Y + attribute \src "libresoc.v:31911.17-31911.96" + wire $and$libresoc.v:31911$1043_Y + attribute \src "libresoc.v:31908.18-31908.94" + wire $not$libresoc.v:31908$1040_Y + attribute \src "libresoc.v:31910.17-31910.93" + wire $not$libresoc.v:31910$1042_Y + attribute \src "libresoc.v:31913.17-31913.93" + wire $not$libresoc.v:31913$1045_Y + attribute \src "libresoc.v:31907.18-31907.99" + wire $or$libresoc.v:31907$1039_Y + attribute \src "libresoc.v:31909.18-31909.100" + wire $or$libresoc.v:31909$1041_Y + attribute \src "libresoc.v:31912.17-31912.98" + wire $or$libresoc.v:31912$1044_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -46340,11 +46376,11 @@ module \alui_l$28 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:31823.7-31823.15" + attribute \src "libresoc.v:31871.7-31871.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui @@ -46361,7 +46397,7 @@ module \alui_l$28 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:31858$1038 + cell $and $and$libresoc.v:31906$1038 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46369,10 +46405,10 @@ module \alui_l$28 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:31858$1038_Y + connect \Y $and$libresoc.v:31906$1038_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:31863$1043 + cell $and $and$libresoc.v:31911$1043 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46380,34 +46416,34 @@ module \alui_l$28 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:31863$1043_Y + connect \Y $and$libresoc.v:31911$1043_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:31860$1040 + cell $not $not$libresoc.v:31908$1040 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:31860$1040_Y + connect \Y $not$libresoc.v:31908$1040_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:31862$1042 + cell $not $not$libresoc.v:31910$1042 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31862$1042_Y + connect \Y $not$libresoc.v:31910$1042_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:31865$1045 + cell $not $not$libresoc.v:31913$1045 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31865$1045_Y + connect \Y $not$libresoc.v:31913$1045_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:31859$1039 + cell $or $or$libresoc.v:31907$1039 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46415,10 +46451,10 @@ module \alui_l$28 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:31859$1039_Y + connect \Y $or$libresoc.v:31907$1039_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:31861$1041 + cell $or $or$libresoc.v:31909$1041 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46426,10 +46462,10 @@ module \alui_l$28 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:31861$1041_Y + connect \Y $or$libresoc.v:31909$1041_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:31864$1044 + cell $or $or$libresoc.v:31912$1044 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46437,39 +46473,39 @@ module \alui_l$28 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:31864$1044_Y + connect \Y $or$libresoc.v:31912$1044_Y end - attribute \src "libresoc.v:31823.7-31823.20" - process $proc$libresoc.v:31823$1050 + attribute \src "libresoc.v:31871.7-31871.20" + process $proc$libresoc.v:31871$1050 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:31847.7-31847.19" - process $proc$libresoc.v:31847$1051 + attribute \src "libresoc.v:31895.7-31895.19" + process $proc$libresoc.v:31895$1051 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:31866.3-31867.27" - process $proc$libresoc.v:31866$1046 + attribute \src "libresoc.v:31914.3-31915.27" + process $proc$libresoc.v:31914$1046 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:31868.3-31876.6" - process $proc$libresoc.v:31868$1047 + attribute \src "libresoc.v:31916.3-31924.6" + process $proc$libresoc.v:31916$1047 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1048 $1\q_int$next[0:0]$1049 - attribute \src "libresoc.v:31869.5-31869.29" + attribute \src "libresoc.v:31917.5-31917.29" switch \initial - attribute \src "libresoc.v:31869.9-31869.17" + attribute \src "libresoc.v:31917.9-31917.17" case 1'1 case end @@ -46485,49 +46521,49 @@ module \alui_l$28 sync always update \q_int$next $0\q_int$next[0:0]$1048 end - connect \$9 $and$libresoc.v:31858$1038_Y - connect \$11 $or$libresoc.v:31859$1039_Y - connect \$13 $not$libresoc.v:31860$1040_Y - connect \$15 $or$libresoc.v:31861$1041_Y - connect \$1 $not$libresoc.v:31862$1042_Y - connect \$3 $and$libresoc.v:31863$1043_Y - connect \$5 $or$libresoc.v:31864$1044_Y - connect \$7 $not$libresoc.v:31865$1045_Y + connect \$9 $and$libresoc.v:31906$1038_Y + connect \$11 $or$libresoc.v:31907$1039_Y + connect \$13 $not$libresoc.v:31908$1040_Y + connect \$15 $or$libresoc.v:31909$1041_Y + connect \$1 $not$libresoc.v:31910$1042_Y + connect \$3 $and$libresoc.v:31911$1043_Y + connect \$5 $or$libresoc.v:31912$1044_Y + connect \$7 $not$libresoc.v:31913$1045_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:31884.1-31942.10" +attribute \src "libresoc.v:31932.1-31990.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alui_l" attribute \generator "nMigen" module \alui_l$44 - attribute \src "libresoc.v:31885.7-31885.20" + attribute \src "libresoc.v:31933.7-31933.20" wire $0\initial[0:0] - attribute \src "libresoc.v:31930.3-31938.6" + attribute \src "libresoc.v:31978.3-31986.6" wire $0\q_int$next[0:0]$1062 - attribute \src "libresoc.v:31928.3-31929.27" + attribute \src "libresoc.v:31976.3-31977.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:31930.3-31938.6" + attribute \src "libresoc.v:31978.3-31986.6" wire $1\q_int$next[0:0]$1063 - attribute \src "libresoc.v:31909.7-31909.19" + attribute \src "libresoc.v:31957.7-31957.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:31920.17-31920.96" - wire $and$libresoc.v:31920$1052_Y - attribute \src "libresoc.v:31925.17-31925.96" - wire $and$libresoc.v:31925$1057_Y - attribute \src "libresoc.v:31922.18-31922.94" - wire $not$libresoc.v:31922$1054_Y - attribute \src "libresoc.v:31924.17-31924.93" - wire $not$libresoc.v:31924$1056_Y - attribute \src "libresoc.v:31927.17-31927.93" - wire $not$libresoc.v:31927$1059_Y - attribute \src "libresoc.v:31921.18-31921.99" - wire $or$libresoc.v:31921$1053_Y - attribute \src "libresoc.v:31923.18-31923.100" - wire $or$libresoc.v:31923$1055_Y - attribute \src "libresoc.v:31926.17-31926.98" - wire $or$libresoc.v:31926$1058_Y + attribute \src "libresoc.v:31968.17-31968.96" + wire $and$libresoc.v:31968$1052_Y + attribute \src "libresoc.v:31973.17-31973.96" + wire $and$libresoc.v:31973$1057_Y + attribute \src "libresoc.v:31970.18-31970.94" + wire $not$libresoc.v:31970$1054_Y + attribute \src "libresoc.v:31972.17-31972.93" + wire $not$libresoc.v:31972$1056_Y + attribute \src "libresoc.v:31975.17-31975.93" + wire $not$libresoc.v:31975$1059_Y + attribute \src "libresoc.v:31969.18-31969.99" + wire $or$libresoc.v:31969$1053_Y + attribute \src "libresoc.v:31971.18-31971.100" + wire $or$libresoc.v:31971$1055_Y + attribute \src "libresoc.v:31974.17-31974.98" + wire $or$libresoc.v:31974$1058_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -46544,11 +46580,11 @@ module \alui_l$44 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:31885.7-31885.15" + attribute \src "libresoc.v:31933.7-31933.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui @@ -46565,7 +46601,7 @@ module \alui_l$44 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:31920$1052 + cell $and $and$libresoc.v:31968$1052 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46573,10 +46609,10 @@ module \alui_l$44 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:31920$1052_Y + connect \Y $and$libresoc.v:31968$1052_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:31925$1057 + cell $and $and$libresoc.v:31973$1057 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46584,34 +46620,34 @@ module \alui_l$44 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:31925$1057_Y + connect \Y $and$libresoc.v:31973$1057_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:31922$1054 + cell $not $not$libresoc.v:31970$1054 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:31922$1054_Y + connect \Y $not$libresoc.v:31970$1054_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:31924$1056 + cell $not $not$libresoc.v:31972$1056 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31924$1056_Y + connect \Y $not$libresoc.v:31972$1056_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:31927$1059 + cell $not $not$libresoc.v:31975$1059 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31927$1059_Y + connect \Y $not$libresoc.v:31975$1059_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:31921$1053 + cell $or $or$libresoc.v:31969$1053 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46619,10 +46655,10 @@ module \alui_l$44 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:31921$1053_Y + connect \Y $or$libresoc.v:31969$1053_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:31923$1055 + cell $or $or$libresoc.v:31971$1055 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46630,10 +46666,10 @@ module \alui_l$44 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:31923$1055_Y + connect \Y $or$libresoc.v:31971$1055_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:31926$1058 + cell $or $or$libresoc.v:31974$1058 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46641,39 +46677,39 @@ module \alui_l$44 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:31926$1058_Y + connect \Y $or$libresoc.v:31974$1058_Y end - attribute \src "libresoc.v:31885.7-31885.20" - process $proc$libresoc.v:31885$1064 + attribute \src "libresoc.v:31933.7-31933.20" + process $proc$libresoc.v:31933$1064 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:31909.7-31909.19" - process $proc$libresoc.v:31909$1065 + attribute \src "libresoc.v:31957.7-31957.19" + process $proc$libresoc.v:31957$1065 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:31928.3-31929.27" - process $proc$libresoc.v:31928$1060 + attribute \src "libresoc.v:31976.3-31977.27" + process $proc$libresoc.v:31976$1060 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:31930.3-31938.6" - process $proc$libresoc.v:31930$1061 + attribute \src "libresoc.v:31978.3-31986.6" + process $proc$libresoc.v:31978$1061 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1062 $1\q_int$next[0:0]$1063 - attribute \src "libresoc.v:31931.5-31931.29" + attribute \src "libresoc.v:31979.5-31979.29" switch \initial - attribute \src "libresoc.v:31931.9-31931.17" + attribute \src "libresoc.v:31979.9-31979.17" case 1'1 case end @@ -46689,49 +46725,49 @@ module \alui_l$44 sync always update \q_int$next $0\q_int$next[0:0]$1062 end - connect \$9 $and$libresoc.v:31920$1052_Y - connect \$11 $or$libresoc.v:31921$1053_Y - connect \$13 $not$libresoc.v:31922$1054_Y - connect \$15 $or$libresoc.v:31923$1055_Y - connect \$1 $not$libresoc.v:31924$1056_Y - connect \$3 $and$libresoc.v:31925$1057_Y - connect \$5 $or$libresoc.v:31926$1058_Y - connect \$7 $not$libresoc.v:31927$1059_Y + connect \$9 $and$libresoc.v:31968$1052_Y + connect \$11 $or$libresoc.v:31969$1053_Y + connect \$13 $not$libresoc.v:31970$1054_Y + connect \$15 $or$libresoc.v:31971$1055_Y + connect \$1 $not$libresoc.v:31972$1056_Y + connect \$3 $and$libresoc.v:31973$1057_Y + connect \$5 $or$libresoc.v:31974$1058_Y + connect \$7 $not$libresoc.v:31975$1059_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:31946.1-32004.10" +attribute \src "libresoc.v:31994.1-32052.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alui_l" attribute \generator "nMigen" module \alui_l$60 - attribute \src "libresoc.v:31947.7-31947.20" + attribute \src "libresoc.v:31995.7-31995.20" wire $0\initial[0:0] - attribute \src "libresoc.v:31992.3-32000.6" + attribute \src "libresoc.v:32040.3-32048.6" wire $0\q_int$next[0:0]$1076 - attribute \src "libresoc.v:31990.3-31991.27" + attribute \src "libresoc.v:32038.3-32039.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:31992.3-32000.6" + attribute \src "libresoc.v:32040.3-32048.6" wire $1\q_int$next[0:0]$1077 - attribute \src "libresoc.v:31971.7-31971.19" + attribute \src "libresoc.v:32019.7-32019.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:31982.17-31982.96" - wire $and$libresoc.v:31982$1066_Y - attribute \src "libresoc.v:31987.17-31987.96" - wire $and$libresoc.v:31987$1071_Y - attribute \src "libresoc.v:31984.18-31984.94" - wire $not$libresoc.v:31984$1068_Y - attribute \src "libresoc.v:31986.17-31986.93" - wire $not$libresoc.v:31986$1070_Y - attribute \src "libresoc.v:31989.17-31989.93" - wire $not$libresoc.v:31989$1073_Y - attribute \src "libresoc.v:31983.18-31983.99" - wire $or$libresoc.v:31983$1067_Y - attribute \src "libresoc.v:31985.18-31985.100" - wire $or$libresoc.v:31985$1069_Y - attribute \src "libresoc.v:31988.17-31988.98" - wire $or$libresoc.v:31988$1072_Y + attribute \src "libresoc.v:32030.17-32030.96" + wire $and$libresoc.v:32030$1066_Y + attribute \src "libresoc.v:32035.17-32035.96" + wire $and$libresoc.v:32035$1071_Y + attribute \src "libresoc.v:32032.18-32032.94" + wire $not$libresoc.v:32032$1068_Y + attribute \src "libresoc.v:32034.17-32034.93" + wire $not$libresoc.v:32034$1070_Y + attribute \src "libresoc.v:32037.17-32037.93" + wire $not$libresoc.v:32037$1073_Y + attribute \src "libresoc.v:32031.18-32031.99" + wire $or$libresoc.v:32031$1067_Y + attribute \src "libresoc.v:32033.18-32033.100" + wire $or$libresoc.v:32033$1069_Y + attribute \src "libresoc.v:32036.17-32036.98" + wire $or$libresoc.v:32036$1072_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -46748,11 +46784,11 @@ module \alui_l$60 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:31947.7-31947.15" + attribute \src "libresoc.v:31995.7-31995.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui @@ -46769,7 +46805,7 @@ module \alui_l$60 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:31982$1066 + cell $and $and$libresoc.v:32030$1066 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46777,10 +46813,10 @@ module \alui_l$60 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:31982$1066_Y + connect \Y $and$libresoc.v:32030$1066_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:31987$1071 + cell $and $and$libresoc.v:32035$1071 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46788,34 +46824,34 @@ module \alui_l$60 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:31987$1071_Y + connect \Y $and$libresoc.v:32035$1071_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:31984$1068 + cell $not $not$libresoc.v:32032$1068 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:31984$1068_Y + connect \Y $not$libresoc.v:32032$1068_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:31986$1070 + cell $not $not$libresoc.v:32034$1070 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31986$1070_Y + connect \Y $not$libresoc.v:32034$1070_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:31989$1073 + cell $not $not$libresoc.v:32037$1073 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:31989$1073_Y + connect \Y $not$libresoc.v:32037$1073_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:31983$1067 + cell $or $or$libresoc.v:32031$1067 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46823,10 +46859,10 @@ module \alui_l$60 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:31983$1067_Y + connect \Y $or$libresoc.v:32031$1067_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:31985$1069 + cell $or $or$libresoc.v:32033$1069 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46834,10 +46870,10 @@ module \alui_l$60 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:31985$1069_Y + connect \Y $or$libresoc.v:32033$1069_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:31988$1072 + cell $or $or$libresoc.v:32036$1072 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46845,39 +46881,39 @@ module \alui_l$60 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:31988$1072_Y + connect \Y $or$libresoc.v:32036$1072_Y end - attribute \src "libresoc.v:31947.7-31947.20" - process $proc$libresoc.v:31947$1078 + attribute \src "libresoc.v:31995.7-31995.20" + process $proc$libresoc.v:31995$1078 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:31971.7-31971.19" - process $proc$libresoc.v:31971$1079 + attribute \src "libresoc.v:32019.7-32019.19" + process $proc$libresoc.v:32019$1079 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:31990.3-31991.27" - process $proc$libresoc.v:31990$1074 + attribute \src "libresoc.v:32038.3-32039.27" + process $proc$libresoc.v:32038$1074 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:31992.3-32000.6" - process $proc$libresoc.v:31992$1075 + attribute \src "libresoc.v:32040.3-32048.6" + process $proc$libresoc.v:32040$1075 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1076 $1\q_int$next[0:0]$1077 - attribute \src "libresoc.v:31993.5-31993.29" + attribute \src "libresoc.v:32041.5-32041.29" switch \initial - attribute \src "libresoc.v:31993.9-31993.17" + attribute \src "libresoc.v:32041.9-32041.17" case 1'1 case end @@ -46893,49 +46929,49 @@ module \alui_l$60 sync always update \q_int$next $0\q_int$next[0:0]$1076 end - connect \$9 $and$libresoc.v:31982$1066_Y - connect \$11 $or$libresoc.v:31983$1067_Y - connect \$13 $not$libresoc.v:31984$1068_Y - connect \$15 $or$libresoc.v:31985$1069_Y - connect \$1 $not$libresoc.v:31986$1070_Y - connect \$3 $and$libresoc.v:31987$1071_Y - connect \$5 $or$libresoc.v:31988$1072_Y - connect \$7 $not$libresoc.v:31989$1073_Y + connect \$9 $and$libresoc.v:32030$1066_Y + connect \$11 $or$libresoc.v:32031$1067_Y + connect \$13 $not$libresoc.v:32032$1068_Y + connect \$15 $or$libresoc.v:32033$1069_Y + connect \$1 $not$libresoc.v:32034$1070_Y + connect \$3 $and$libresoc.v:32035$1071_Y + connect \$5 $or$libresoc.v:32036$1072_Y + connect \$7 $not$libresoc.v:32037$1073_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:32008.1-32066.10" +attribute \src "libresoc.v:32056.1-32114.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alui_l" attribute \generator "nMigen" module \alui_l$72 - attribute \src "libresoc.v:32009.7-32009.20" + attribute \src "libresoc.v:32057.7-32057.20" wire $0\initial[0:0] - attribute \src "libresoc.v:32054.3-32062.6" + attribute \src "libresoc.v:32102.3-32110.6" wire $0\q_int$next[0:0]$1090 - attribute \src "libresoc.v:32052.3-32053.27" + attribute \src "libresoc.v:32100.3-32101.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:32054.3-32062.6" + attribute \src "libresoc.v:32102.3-32110.6" wire $1\q_int$next[0:0]$1091 - attribute \src "libresoc.v:32033.7-32033.19" + attribute \src "libresoc.v:32081.7-32081.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:32044.17-32044.96" - wire $and$libresoc.v:32044$1080_Y - attribute \src "libresoc.v:32049.17-32049.96" - wire $and$libresoc.v:32049$1085_Y - attribute \src "libresoc.v:32046.18-32046.94" - wire $not$libresoc.v:32046$1082_Y - attribute \src "libresoc.v:32048.17-32048.93" - wire $not$libresoc.v:32048$1084_Y - attribute \src "libresoc.v:32051.17-32051.93" - wire $not$libresoc.v:32051$1087_Y - attribute \src "libresoc.v:32045.18-32045.99" - wire $or$libresoc.v:32045$1081_Y - attribute \src "libresoc.v:32047.18-32047.100" - wire $or$libresoc.v:32047$1083_Y - attribute \src "libresoc.v:32050.17-32050.98" - wire $or$libresoc.v:32050$1086_Y + attribute \src "libresoc.v:32092.17-32092.96" + wire $and$libresoc.v:32092$1080_Y + attribute \src "libresoc.v:32097.17-32097.96" + wire $and$libresoc.v:32097$1085_Y + attribute \src "libresoc.v:32094.18-32094.94" + wire $not$libresoc.v:32094$1082_Y + attribute \src "libresoc.v:32096.17-32096.93" + wire $not$libresoc.v:32096$1084_Y + attribute \src "libresoc.v:32099.17-32099.93" + wire $not$libresoc.v:32099$1087_Y + attribute \src "libresoc.v:32093.18-32093.99" + wire $or$libresoc.v:32093$1081_Y + attribute \src "libresoc.v:32095.18-32095.100" + wire $or$libresoc.v:32095$1083_Y + attribute \src "libresoc.v:32098.17-32098.98" + wire $or$libresoc.v:32098$1086_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -46952,11 +46988,11 @@ module \alui_l$72 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:32009.7-32009.15" + attribute \src "libresoc.v:32057.7-32057.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui @@ -46973,7 +47009,7 @@ module \alui_l$72 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:32044$1080 + cell $and $and$libresoc.v:32092$1080 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46981,10 +47017,10 @@ module \alui_l$72 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:32044$1080_Y + connect \Y $and$libresoc.v:32092$1080_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:32049$1085 + cell $and $and$libresoc.v:32097$1085 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -46992,34 +47028,34 @@ module \alui_l$72 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:32049$1085_Y + connect \Y $and$libresoc.v:32097$1085_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:32046$1082 + cell $not $not$libresoc.v:32094$1082 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:32046$1082_Y + connect \Y $not$libresoc.v:32094$1082_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:32048$1084 + cell $not $not$libresoc.v:32096$1084 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:32048$1084_Y + connect \Y $not$libresoc.v:32096$1084_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:32051$1087 + cell $not $not$libresoc.v:32099$1087 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:32051$1087_Y + connect \Y $not$libresoc.v:32099$1087_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:32045$1081 + cell $or $or$libresoc.v:32093$1081 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -47027,10 +47063,10 @@ module \alui_l$72 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:32045$1081_Y + connect \Y $or$libresoc.v:32093$1081_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:32047$1083 + cell $or $or$libresoc.v:32095$1083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -47038,10 +47074,10 @@ module \alui_l$72 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:32047$1083_Y + connect \Y $or$libresoc.v:32095$1083_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:32050$1086 + cell $or $or$libresoc.v:32098$1086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -47049,39 +47085,39 @@ module \alui_l$72 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:32050$1086_Y + connect \Y $or$libresoc.v:32098$1086_Y end - attribute \src "libresoc.v:32009.7-32009.20" - process $proc$libresoc.v:32009$1092 + attribute \src "libresoc.v:32057.7-32057.20" + process $proc$libresoc.v:32057$1092 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:32033.7-32033.19" - process $proc$libresoc.v:32033$1093 + attribute \src "libresoc.v:32081.7-32081.19" + process $proc$libresoc.v:32081$1093 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:32052.3-32053.27" - process $proc$libresoc.v:32052$1088 + attribute \src "libresoc.v:32100.3-32101.27" + process $proc$libresoc.v:32100$1088 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:32054.3-32062.6" - process $proc$libresoc.v:32054$1089 + attribute \src "libresoc.v:32102.3-32110.6" + process $proc$libresoc.v:32102$1089 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1090 $1\q_int$next[0:0]$1091 - attribute \src "libresoc.v:32055.5-32055.29" + attribute \src "libresoc.v:32103.5-32103.29" switch \initial - attribute \src "libresoc.v:32055.9-32055.17" + attribute \src "libresoc.v:32103.9-32103.17" case 1'1 case end @@ -47097,49 +47133,49 @@ module \alui_l$72 sync always update \q_int$next $0\q_int$next[0:0]$1090 end - connect \$9 $and$libresoc.v:32044$1080_Y - connect \$11 $or$libresoc.v:32045$1081_Y - connect \$13 $not$libresoc.v:32046$1082_Y - connect \$15 $or$libresoc.v:32047$1083_Y - connect \$1 $not$libresoc.v:32048$1084_Y - connect \$3 $and$libresoc.v:32049$1085_Y - connect \$5 $or$libresoc.v:32050$1086_Y - connect \$7 $not$libresoc.v:32051$1087_Y + connect \$9 $and$libresoc.v:32092$1080_Y + connect \$11 $or$libresoc.v:32093$1081_Y + connect \$13 $not$libresoc.v:32094$1082_Y + connect \$15 $or$libresoc.v:32095$1083_Y + connect \$1 $not$libresoc.v:32096$1084_Y + connect \$3 $and$libresoc.v:32097$1085_Y + connect \$5 $or$libresoc.v:32098$1086_Y + connect \$7 $not$libresoc.v:32099$1087_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:32070.1-32128.10" +attribute \src "libresoc.v:32118.1-32176.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alui_l" attribute \generator "nMigen" module \alui_l$89 - attribute \src "libresoc.v:32071.7-32071.20" + attribute \src "libresoc.v:32119.7-32119.20" wire $0\initial[0:0] - attribute \src "libresoc.v:32116.3-32124.6" + attribute \src "libresoc.v:32164.3-32172.6" wire $0\q_int$next[0:0]$1104 - attribute \src "libresoc.v:32114.3-32115.27" + attribute \src "libresoc.v:32162.3-32163.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:32116.3-32124.6" + attribute \src "libresoc.v:32164.3-32172.6" wire $1\q_int$next[0:0]$1105 - attribute \src "libresoc.v:32095.7-32095.19" + attribute \src "libresoc.v:32143.7-32143.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:32106.17-32106.96" - wire $and$libresoc.v:32106$1094_Y - attribute \src "libresoc.v:32111.17-32111.96" - wire $and$libresoc.v:32111$1099_Y - attribute \src "libresoc.v:32108.18-32108.94" - wire $not$libresoc.v:32108$1096_Y - attribute \src "libresoc.v:32110.17-32110.93" - wire $not$libresoc.v:32110$1098_Y - attribute \src "libresoc.v:32113.17-32113.93" - wire $not$libresoc.v:32113$1101_Y - attribute \src "libresoc.v:32107.18-32107.99" - wire $or$libresoc.v:32107$1095_Y - attribute \src "libresoc.v:32109.18-32109.100" - wire $or$libresoc.v:32109$1097_Y - attribute \src "libresoc.v:32112.17-32112.98" - wire $or$libresoc.v:32112$1100_Y + attribute \src "libresoc.v:32154.17-32154.96" + wire $and$libresoc.v:32154$1094_Y + attribute \src "libresoc.v:32159.17-32159.96" + wire $and$libresoc.v:32159$1099_Y + attribute \src "libresoc.v:32156.18-32156.94" + wire $not$libresoc.v:32156$1096_Y + attribute \src "libresoc.v:32158.17-32158.93" + wire $not$libresoc.v:32158$1098_Y + attribute \src "libresoc.v:32161.17-32161.93" + wire $not$libresoc.v:32161$1101_Y + attribute \src "libresoc.v:32155.18-32155.99" + wire $or$libresoc.v:32155$1095_Y + attribute \src "libresoc.v:32157.18-32157.100" + wire $or$libresoc.v:32157$1097_Y + attribute \src "libresoc.v:32160.17-32160.98" + wire $or$libresoc.v:32160$1100_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -47156,11 +47192,11 @@ module \alui_l$89 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:32071.7-32071.15" + attribute \src "libresoc.v:32119.7-32119.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_alui @@ -47177,7 +47213,7 @@ module \alui_l$89 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 4 \s_alui attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:32106$1094 + cell $and $and$libresoc.v:32154$1094 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -47185,10 +47221,10 @@ module \alui_l$89 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:32106$1094_Y + connect \Y $and$libresoc.v:32154$1094_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:32111$1099 + cell $and $and$libresoc.v:32159$1099 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -47196,34 +47232,34 @@ module \alui_l$89 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:32111$1099_Y + connect \Y $and$libresoc.v:32159$1099_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:32108$1096 + cell $not $not$libresoc.v:32156$1096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_alui - connect \Y $not$libresoc.v:32108$1096_Y + connect \Y $not$libresoc.v:32156$1096_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:32110$1098 + cell $not $not$libresoc.v:32158$1098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:32110$1098_Y + connect \Y $not$libresoc.v:32158$1098_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:32113$1101 + cell $not $not$libresoc.v:32161$1101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_alui - connect \Y $not$libresoc.v:32113$1101_Y + connect \Y $not$libresoc.v:32161$1101_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:32107$1095 + cell $or $or$libresoc.v:32155$1095 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -47231,10 +47267,10 @@ module \alui_l$89 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_alui - connect \Y $or$libresoc.v:32107$1095_Y + connect \Y $or$libresoc.v:32155$1095_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:32109$1097 + cell $or $or$libresoc.v:32157$1097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -47242,10 +47278,10 @@ module \alui_l$89 parameter \Y_WIDTH 1 connect \A \q_alui connect \B \q_int - connect \Y $or$libresoc.v:32109$1097_Y + connect \Y $or$libresoc.v:32157$1097_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:32112$1100 + cell $or $or$libresoc.v:32160$1100 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -47253,39 +47289,39 @@ module \alui_l$89 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_alui - connect \Y $or$libresoc.v:32112$1100_Y + connect \Y $or$libresoc.v:32160$1100_Y end - attribute \src "libresoc.v:32071.7-32071.20" - process $proc$libresoc.v:32071$1106 + attribute \src "libresoc.v:32119.7-32119.20" + process $proc$libresoc.v:32119$1106 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:32095.7-32095.19" - process $proc$libresoc.v:32095$1107 + attribute \src "libresoc.v:32143.7-32143.19" + process $proc$libresoc.v:32143$1107 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:32114.3-32115.27" - process $proc$libresoc.v:32114$1102 + attribute \src "libresoc.v:32162.3-32163.27" + process $proc$libresoc.v:32162$1102 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:32116.3-32124.6" - process $proc$libresoc.v:32116$1103 + attribute \src "libresoc.v:32164.3-32172.6" + process $proc$libresoc.v:32164$1103 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1104 $1\q_int$next[0:0]$1105 - attribute \src "libresoc.v:32117.5-32117.29" + attribute \src "libresoc.v:32165.5-32165.29" switch \initial - attribute \src "libresoc.v:32117.9-32117.17" + attribute \src "libresoc.v:32165.9-32165.17" case 1'1 case end @@ -47301,75 +47337,75 @@ module \alui_l$89 sync always update \q_int$next $0\q_int$next[0:0]$1104 end - connect \$9 $and$libresoc.v:32106$1094_Y - connect \$11 $or$libresoc.v:32107$1095_Y - connect \$13 $not$libresoc.v:32108$1096_Y - connect \$15 $or$libresoc.v:32109$1097_Y - connect \$1 $not$libresoc.v:32110$1098_Y - connect \$3 $and$libresoc.v:32111$1099_Y - connect \$5 $or$libresoc.v:32112$1100_Y - connect \$7 $not$libresoc.v:32113$1101_Y + connect \$9 $and$libresoc.v:32154$1094_Y + connect \$11 $or$libresoc.v:32155$1095_Y + connect \$13 $not$libresoc.v:32156$1096_Y + connect \$15 $or$libresoc.v:32157$1097_Y + connect \$1 $not$libresoc.v:32158$1098_Y + connect \$3 $and$libresoc.v:32159$1099_Y + connect \$5 $or$libresoc.v:32160$1100_Y + connect \$7 $not$libresoc.v:32161$1101_Y connect \qlq_alui \$15 connect \qn_alui \$13 connect \q_alui \$11 end -attribute \src "libresoc.v:32132.1-33476.10" +attribute \src "libresoc.v:32180.1-33524.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main.bpermd" attribute \generator "nMigen" module \bpermd - attribute \src "libresoc.v:32133.7-32133.20" + attribute \src "libresoc.v:32181.7-32181.20" wire $0\initial[0:0] - attribute \src "libresoc.v:32310.3-33401.6" + attribute \src "libresoc.v:32358.3-33449.6" wire width 64 $0\perm[63:0] - attribute \src "libresoc.v:32310.3-33401.6" + attribute \src "libresoc.v:32358.3-33449.6" wire $10\perm[4:4] - attribute \src "libresoc.v:32310.3-33401.6" + attribute \src "libresoc.v:32358.3-33449.6" wire $11\perm[5:5] - attribute \src "libresoc.v:32310.3-33401.6" + attribute \src "libresoc.v:32358.3-33449.6" wire $12\perm[5:5] - attribute \src "libresoc.v:32310.3-33401.6" + attribute \src "libresoc.v:32358.3-33449.6" wire $13\perm[6:6] - attribute \src "libresoc.v:32310.3-33401.6" + attribute \src "libresoc.v:32358.3-33449.6" wire $14\perm[6:6] - attribute \src "libresoc.v:32310.3-33401.6" + attribute \src "libresoc.v:32358.3-33449.6" wire $15\perm[7:7] - attribute \src "libresoc.v:32310.3-33401.6" + attribute \src "libresoc.v:32358.3-33449.6" wire $16\perm[7:7] - attribute \src "libresoc.v:32310.3-33401.6" + attribute \src "libresoc.v:32358.3-33449.6" wire $1\perm[0:0] - attribute \src "libresoc.v:32310.3-33401.6" + attribute \src "libresoc.v:32358.3-33449.6" wire $2\perm[0:0] - attribute \src "libresoc.v:32310.3-33401.6" + attribute \src "libresoc.v:32358.3-33449.6" wire $3\perm[1:1] - attribute \src "libresoc.v:32310.3-33401.6" + attribute \src "libresoc.v:32358.3-33449.6" wire $4\perm[1:1] - attribute \src "libresoc.v:32310.3-33401.6" + attribute \src "libresoc.v:32358.3-33449.6" wire $5\perm[2:2] - attribute \src "libresoc.v:32310.3-33401.6" + attribute \src "libresoc.v:32358.3-33449.6" wire $6\perm[2:2] - attribute \src "libresoc.v:32310.3-33401.6" + attribute \src "libresoc.v:32358.3-33449.6" wire $7\perm[3:3] - attribute \src "libresoc.v:32310.3-33401.6" + attribute \src "libresoc.v:32358.3-33449.6" wire $8\perm[3:3] - attribute \src "libresoc.v:32310.3-33401.6" + attribute \src "libresoc.v:32358.3-33449.6" wire $9\perm[4:4] - attribute \src "libresoc.v:32302.17-32302.104" - wire $lt$libresoc.v:32302$1108_Y - attribute \src "libresoc.v:32303.18-32303.105" - wire $lt$libresoc.v:32303$1109_Y - attribute \src "libresoc.v:32304.18-32304.105" - wire $lt$libresoc.v:32304$1110_Y - attribute \src "libresoc.v:32305.18-32305.105" - wire $lt$libresoc.v:32305$1111_Y - attribute \src "libresoc.v:32306.17-32306.104" - wire $lt$libresoc.v:32306$1112_Y - attribute \src "libresoc.v:32307.17-32307.104" - wire $lt$libresoc.v:32307$1113_Y - attribute \src "libresoc.v:32308.17-32308.104" - wire $lt$libresoc.v:32308$1114_Y - attribute \src "libresoc.v:32309.17-32309.104" - wire $lt$libresoc.v:32309$1115_Y + attribute \src "libresoc.v:32350.17-32350.104" + wire $lt$libresoc.v:32350$1108_Y + attribute \src "libresoc.v:32351.18-32351.105" + wire $lt$libresoc.v:32351$1109_Y + attribute \src "libresoc.v:32352.18-32352.105" + wire $lt$libresoc.v:32352$1110_Y + attribute \src "libresoc.v:32353.18-32353.105" + wire $lt$libresoc.v:32353$1111_Y + attribute \src "libresoc.v:32354.17-32354.104" + wire $lt$libresoc.v:32354$1112_Y + attribute \src "libresoc.v:32355.17-32355.104" + wire $lt$libresoc.v:32355$1113_Y + attribute \src "libresoc.v:32356.17-32356.104" + wire $lt$libresoc.v:32356$1114_Y + attribute \src "libresoc.v:32357.17-32357.104" + wire $lt$libresoc.v:32357$1115_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" @@ -47402,7 +47438,7 @@ module \bpermd wire width 8 \idx_6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" wire width 8 \idx_7 - attribute \src "libresoc.v:32133.7-32133.15" + attribute \src "libresoc.v:32181.7-32181.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:60" wire width 64 \perm @@ -47541,7 +47577,7 @@ module \bpermd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:54" wire width 64 input 3 \rs attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:32302$1108 + cell $lt $lt$libresoc.v:32350$1108 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -47549,10 +47585,10 @@ module \bpermd parameter \Y_WIDTH 1 connect \A \idx_4 connect \B 7'1000000 - connect \Y $lt$libresoc.v:32302$1108_Y + connect \Y $lt$libresoc.v:32350$1108_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:32303$1109 + cell $lt $lt$libresoc.v:32351$1109 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -47560,10 +47596,10 @@ module \bpermd parameter \Y_WIDTH 1 connect \A \idx_5 connect \B 7'1000000 - connect \Y $lt$libresoc.v:32303$1109_Y + connect \Y $lt$libresoc.v:32351$1109_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:32304$1110 + cell $lt $lt$libresoc.v:32352$1110 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -47571,10 +47607,10 @@ module \bpermd parameter \Y_WIDTH 1 connect \A \idx_6 connect \B 7'1000000 - connect \Y $lt$libresoc.v:32304$1110_Y + connect \Y $lt$libresoc.v:32352$1110_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:32305$1111 + cell $lt $lt$libresoc.v:32353$1111 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -47582,10 +47618,10 @@ module \bpermd parameter \Y_WIDTH 1 connect \A \idx_7 connect \B 7'1000000 - connect \Y $lt$libresoc.v:32305$1111_Y + connect \Y $lt$libresoc.v:32353$1111_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:32306$1112 + cell $lt $lt$libresoc.v:32354$1112 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -47593,10 +47629,10 @@ module \bpermd parameter \Y_WIDTH 1 connect \A \idx_0 connect \B 7'1000000 - connect \Y $lt$libresoc.v:32306$1112_Y + connect \Y $lt$libresoc.v:32354$1112_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:32307$1113 + cell $lt $lt$libresoc.v:32355$1113 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -47604,10 +47640,10 @@ module \bpermd parameter \Y_WIDTH 1 connect \A \idx_1 connect \B 7'1000000 - connect \Y $lt$libresoc.v:32307$1113_Y + connect \Y $lt$libresoc.v:32355$1113_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:32308$1114 + cell $lt $lt$libresoc.v:32356$1114 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -47615,10 +47651,10 @@ module \bpermd parameter \Y_WIDTH 1 connect \A \idx_2 connect \B 7'1000000 - connect \Y $lt$libresoc.v:32308$1114_Y + connect \Y $lt$libresoc.v:32356$1114_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $lt$libresoc.v:32309$1115 + cell $lt $lt$libresoc.v:32357$1115 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -47626,18 +47662,18 @@ module \bpermd parameter \Y_WIDTH 1 connect \A \idx_3 connect \B 7'1000000 - connect \Y $lt$libresoc.v:32309$1115_Y + connect \Y $lt$libresoc.v:32357$1115_Y end - attribute \src "libresoc.v:32133.7-32133.20" - process $proc$libresoc.v:32133$1117 + attribute \src "libresoc.v:32181.7-32181.20" + process $proc$libresoc.v:32181$1117 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:32310.3-33401.6" - process $proc$libresoc.v:32310$1116 + attribute \src "libresoc.v:32358.3-33449.6" + process $proc$libresoc.v:32358$1116 assign { } { } assign $0\perm[63:0] [63:8] 56'00000000000000000000000000000000000000000000000000000000 assign $0\perm[63:0] [0] $1\perm[0:0] @@ -47648,9 +47684,9 @@ module \bpermd assign $0\perm[63:0] [5] $11\perm[5:5] assign $0\perm[63:0] [6] $13\perm[6:6] assign $0\perm[63:0] [7] $15\perm[7:7] - attribute \src "libresoc.v:32311.5-32311.29" + attribute \src "libresoc.v:32359.5-32359.29" switch \initial - attribute \src "libresoc.v:32311.9-32311.17" + attribute \src "libresoc.v:32359.9-32359.17" case 1'1 case end @@ -49817,14 +49853,14 @@ module \bpermd sync always update \perm $0\perm[63:0] end - connect \$9 $lt$libresoc.v:32302$1108_Y - connect \$11 $lt$libresoc.v:32303$1109_Y - connect \$13 $lt$libresoc.v:32304$1110_Y - connect \$15 $lt$libresoc.v:32305$1111_Y - connect \$1 $lt$libresoc.v:32306$1112_Y - connect \$3 $lt$libresoc.v:32307$1113_Y - connect \$5 $lt$libresoc.v:32308$1114_Y - connect \$7 $lt$libresoc.v:32309$1115_Y + connect \$9 $lt$libresoc.v:32350$1108_Y + connect \$11 $lt$libresoc.v:32351$1109_Y + connect \$13 $lt$libresoc.v:32352$1110_Y + connect \$15 $lt$libresoc.v:32353$1111_Y + connect \$1 $lt$libresoc.v:32354$1112_Y + connect \$3 $lt$libresoc.v:32355$1113_Y + connect \$5 $lt$libresoc.v:32356$1114_Y + connect \$7 $lt$libresoc.v:32357$1115_Y connect \ra [7:0] \perm [7:0] connect \ra [63:8] 56'00000000000000000000000000000000000000000000000000000000 connect \idx_7 \rs [63:56] @@ -49900,413 +49936,413 @@ module \bpermd connect \rb64_1 \rb [62] connect \rb64_0 \rb [63] end -attribute \src "libresoc.v:33480.1-34535.10" +attribute \src "libresoc.v:33528.1-34583.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0" attribute \generator "nMigen" module \branch0 - attribute \src "libresoc.v:34152.3-34153.25" + attribute \src "libresoc.v:34200.3-34201.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:34327.3-34351.6" + attribute \src "libresoc.v:34375.3-34399.6" wire width 64 $0\alu_branch0_br_op__cia$next[63:0]$1239 - attribute \src "libresoc.v:34112.3-34113.61" + attribute \src "libresoc.v:34160.3-34161.61" wire width 64 $0\alu_branch0_br_op__cia[63:0] - attribute \src "libresoc.v:34327.3-34351.6" + attribute \src "libresoc.v:34375.3-34399.6" wire width 14 $0\alu_branch0_br_op__fn_unit$next[13:0]$1240 - attribute \src "libresoc.v:34116.3-34117.69" + attribute \src "libresoc.v:34164.3-34165.69" wire width 14 $0\alu_branch0_br_op__fn_unit[13:0] - attribute \src "libresoc.v:34327.3-34351.6" + attribute \src "libresoc.v:34375.3-34399.6" wire width 64 $0\alu_branch0_br_op__imm_data__data$next[63:0]$1241 - attribute \src "libresoc.v:34120.3-34121.83" + attribute \src "libresoc.v:34168.3-34169.83" wire width 64 $0\alu_branch0_br_op__imm_data__data[63:0] - attribute \src "libresoc.v:34327.3-34351.6" + attribute \src "libresoc.v:34375.3-34399.6" wire $0\alu_branch0_br_op__imm_data__ok$next[0:0]$1242 - attribute \src "libresoc.v:34122.3-34123.79" + attribute \src "libresoc.v:34170.3-34171.79" wire $0\alu_branch0_br_op__imm_data__ok[0:0] - attribute \src "libresoc.v:34327.3-34351.6" + attribute \src "libresoc.v:34375.3-34399.6" wire width 32 $0\alu_branch0_br_op__insn$next[31:0]$1243 - attribute \src "libresoc.v:34118.3-34119.63" + attribute \src "libresoc.v:34166.3-34167.63" wire width 32 $0\alu_branch0_br_op__insn[31:0] - attribute \src "libresoc.v:34327.3-34351.6" + attribute \src "libresoc.v:34375.3-34399.6" wire width 7 $0\alu_branch0_br_op__insn_type$next[6:0]$1244 - attribute \src "libresoc.v:34114.3-34115.73" + attribute \src "libresoc.v:34162.3-34163.73" wire width 7 $0\alu_branch0_br_op__insn_type[6:0] - attribute \src "libresoc.v:34327.3-34351.6" + attribute \src "libresoc.v:34375.3-34399.6" wire $0\alu_branch0_br_op__is_32bit$next[0:0]$1245 - attribute \src "libresoc.v:34126.3-34127.71" + attribute \src "libresoc.v:34174.3-34175.71" wire $0\alu_branch0_br_op__is_32bit[0:0] - attribute \src "libresoc.v:34327.3-34351.6" + attribute \src "libresoc.v:34375.3-34399.6" wire $0\alu_branch0_br_op__lk$next[0:0]$1246 - attribute \src "libresoc.v:34124.3-34125.59" + attribute \src "libresoc.v:34172.3-34173.59" wire $0\alu_branch0_br_op__lk[0:0] - attribute \src "libresoc.v:34150.3-34151.43" + attribute \src "libresoc.v:34198.3-34199.43" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:34457.3-34465.6" + attribute \src "libresoc.v:34505.3-34513.6" wire $0\alu_l_r_alu$next[0:0]$1294 - attribute \src "libresoc.v:34090.3-34091.39" + attribute \src "libresoc.v:34138.3-34139.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:34448.3-34456.6" + attribute \src "libresoc.v:34496.3-34504.6" wire $0\alui_l_r_alui$next[0:0]$1291 - attribute \src "libresoc.v:34092.3-34093.43" + attribute \src "libresoc.v:34140.3-34141.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:34352.3-34373.6" + attribute \src "libresoc.v:34400.3-34421.6" wire width 64 $0\data_r0__fast1$next[63:0]$1258 - attribute \src "libresoc.v:34108.3-34109.45" + attribute \src "libresoc.v:34156.3-34157.45" wire width 64 $0\data_r0__fast1[63:0] - attribute \src "libresoc.v:34352.3-34373.6" + attribute \src "libresoc.v:34400.3-34421.6" wire $0\data_r0__fast1_ok$next[0:0]$1259 - attribute \src "libresoc.v:34110.3-34111.51" + attribute \src "libresoc.v:34158.3-34159.51" wire $0\data_r0__fast1_ok[0:0] - attribute \src "libresoc.v:34374.3-34395.6" + attribute \src "libresoc.v:34422.3-34443.6" wire width 64 $0\data_r1__fast2$next[63:0]$1266 - attribute \src "libresoc.v:34104.3-34105.45" + attribute \src "libresoc.v:34152.3-34153.45" wire width 64 $0\data_r1__fast2[63:0] - attribute \src "libresoc.v:34374.3-34395.6" + attribute \src "libresoc.v:34422.3-34443.6" wire $0\data_r1__fast2_ok$next[0:0]$1267 - attribute \src "libresoc.v:34106.3-34107.51" + attribute \src "libresoc.v:34154.3-34155.51" wire $0\data_r1__fast2_ok[0:0] - attribute \src "libresoc.v:34396.3-34417.6" + attribute \src "libresoc.v:34444.3-34465.6" wire width 64 $0\data_r2__nia$next[63:0]$1274 - attribute \src "libresoc.v:34100.3-34101.41" + attribute \src "libresoc.v:34148.3-34149.41" wire width 64 $0\data_r2__nia[63:0] - attribute \src "libresoc.v:34396.3-34417.6" + attribute \src "libresoc.v:34444.3-34465.6" wire $0\data_r2__nia_ok$next[0:0]$1275 - attribute \src "libresoc.v:34102.3-34103.47" + attribute \src "libresoc.v:34150.3-34151.47" wire $0\data_r2__nia_ok[0:0] - attribute \src "libresoc.v:34466.3-34475.6" + attribute \src "libresoc.v:34514.3-34523.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:34476.3-34485.6" + attribute \src "libresoc.v:34524.3-34533.6" wire width 64 $0\dest2_o[63:0] - attribute \src "libresoc.v:34486.3-34495.6" + attribute \src "libresoc.v:34534.3-34543.6" wire width 64 $0\dest3_o[63:0] - attribute \src "libresoc.v:33481.7-33481.20" + attribute \src "libresoc.v:33529.7-33529.20" wire $0\initial[0:0] - attribute \src "libresoc.v:34282.3-34290.6" + attribute \src "libresoc.v:34330.3-34338.6" wire $0\opc_l_r_opc$next[0:0]$1224 - attribute \src "libresoc.v:34136.3-34137.39" + attribute \src "libresoc.v:34184.3-34185.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:34273.3-34281.6" + attribute \src "libresoc.v:34321.3-34329.6" wire $0\opc_l_s_opc$next[0:0]$1221 - attribute \src "libresoc.v:34138.3-34139.39" + attribute \src "libresoc.v:34186.3-34187.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:34496.3-34504.6" + attribute \src "libresoc.v:34544.3-34552.6" wire width 3 $0\prev_wr_go$next[2:0]$1300 - attribute \src "libresoc.v:34148.3-34149.37" + attribute \src "libresoc.v:34196.3-34197.37" wire width 3 $0\prev_wr_go[2:0] - attribute \src "libresoc.v:34227.3-34236.6" + attribute \src "libresoc.v:34275.3-34284.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:34318.3-34326.6" + attribute \src "libresoc.v:34366.3-34374.6" wire width 3 $0\req_l_r_req$next[2:0]$1236 - attribute \src "libresoc.v:34128.3-34129.39" + attribute \src "libresoc.v:34176.3-34177.39" wire width 3 $0\req_l_r_req[2:0] - attribute \src "libresoc.v:34309.3-34317.6" + attribute \src "libresoc.v:34357.3-34365.6" wire width 3 $0\req_l_s_req$next[2:0]$1233 - attribute \src "libresoc.v:34130.3-34131.39" + attribute \src "libresoc.v:34178.3-34179.39" wire width 3 $0\req_l_s_req[2:0] - attribute \src "libresoc.v:34246.3-34254.6" + attribute \src "libresoc.v:34294.3-34302.6" wire $0\rok_l_r_rdok$next[0:0]$1212 - attribute \src "libresoc.v:34144.3-34145.41" + attribute \src "libresoc.v:34192.3-34193.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:34237.3-34245.6" + attribute \src "libresoc.v:34285.3-34293.6" wire $0\rok_l_s_rdok$next[0:0]$1209 - attribute \src "libresoc.v:34146.3-34147.41" + attribute \src "libresoc.v:34194.3-34195.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:34264.3-34272.6" + attribute \src "libresoc.v:34312.3-34320.6" wire $0\rst_l_r_rst$next[0:0]$1218 - attribute \src "libresoc.v:34140.3-34141.39" + attribute \src "libresoc.v:34188.3-34189.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:34255.3-34263.6" + attribute \src "libresoc.v:34303.3-34311.6" wire $0\rst_l_s_rst$next[0:0]$1215 - attribute \src "libresoc.v:34142.3-34143.39" + attribute \src "libresoc.v:34190.3-34191.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:34300.3-34308.6" + attribute \src "libresoc.v:34348.3-34356.6" wire width 3 $0\src_l_r_src$next[2:0]$1230 - attribute \src "libresoc.v:34132.3-34133.39" + attribute \src "libresoc.v:34180.3-34181.39" wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:34291.3-34299.6" + attribute \src "libresoc.v:34339.3-34347.6" wire width 3 $0\src_l_s_src$next[2:0]$1227 - attribute \src "libresoc.v:34134.3-34135.39" + attribute \src "libresoc.v:34182.3-34183.39" wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:34418.3-34427.6" + attribute \src "libresoc.v:34466.3-34475.6" wire width 64 $0\src_r0$next[63:0]$1282 - attribute \src "libresoc.v:34098.3-34099.29" + attribute \src "libresoc.v:34146.3-34147.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:34428.3-34437.6" + attribute \src "libresoc.v:34476.3-34485.6" wire width 64 $0\src_r1$next[63:0]$1285 - attribute \src "libresoc.v:34096.3-34097.29" + attribute \src "libresoc.v:34144.3-34145.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:34438.3-34447.6" + attribute \src "libresoc.v:34486.3-34495.6" wire width 4 $0\src_r2$next[3:0]$1288 - attribute \src "libresoc.v:34094.3-34095.29" + attribute \src "libresoc.v:34142.3-34143.29" wire width 4 $0\src_r2[3:0] - attribute \src "libresoc.v:33599.7-33599.24" + attribute \src "libresoc.v:33647.7-33647.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:34327.3-34351.6" + attribute \src "libresoc.v:34375.3-34399.6" wire width 64 $1\alu_branch0_br_op__cia$next[63:0]$1247 - attribute \src "libresoc.v:33607.14-33607.59" + attribute \src "libresoc.v:33655.14-33655.59" wire width 64 $1\alu_branch0_br_op__cia[63:0] - attribute \src "libresoc.v:34327.3-34351.6" + attribute \src "libresoc.v:34375.3-34399.6" wire width 14 $1\alu_branch0_br_op__fn_unit$next[13:0]$1248 - attribute \src "libresoc.v:33626.14-33626.51" + attribute \src "libresoc.v:33674.14-33674.51" wire width 14 $1\alu_branch0_br_op__fn_unit[13:0] - attribute \src "libresoc.v:34327.3-34351.6" + attribute \src "libresoc.v:34375.3-34399.6" wire width 64 $1\alu_branch0_br_op__imm_data__data$next[63:0]$1249 - attribute \src "libresoc.v:33630.14-33630.70" + attribute \src "libresoc.v:33678.14-33678.70" wire width 64 $1\alu_branch0_br_op__imm_data__data[63:0] - attribute \src "libresoc.v:34327.3-34351.6" + attribute \src "libresoc.v:34375.3-34399.6" wire $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1250 - attribute \src "libresoc.v:33634.7-33634.45" + attribute \src "libresoc.v:33682.7-33682.45" wire $1\alu_branch0_br_op__imm_data__ok[0:0] - attribute \src "libresoc.v:34327.3-34351.6" + attribute \src "libresoc.v:34375.3-34399.6" wire width 32 $1\alu_branch0_br_op__insn$next[31:0]$1251 - attribute \src "libresoc.v:33638.14-33638.45" + attribute \src "libresoc.v:33686.14-33686.45" wire width 32 $1\alu_branch0_br_op__insn[31:0] - attribute \src "libresoc.v:34327.3-34351.6" + attribute \src "libresoc.v:34375.3-34399.6" wire width 7 $1\alu_branch0_br_op__insn_type$next[6:0]$1252 - attribute \src "libresoc.v:33717.13-33717.49" + attribute \src "libresoc.v:33765.13-33765.49" wire width 7 $1\alu_branch0_br_op__insn_type[6:0] - attribute \src "libresoc.v:34327.3-34351.6" + attribute \src "libresoc.v:34375.3-34399.6" wire $1\alu_branch0_br_op__is_32bit$next[0:0]$1253 - attribute \src "libresoc.v:33721.7-33721.41" + attribute \src "libresoc.v:33769.7-33769.41" wire $1\alu_branch0_br_op__is_32bit[0:0] - attribute \src "libresoc.v:34327.3-34351.6" + attribute \src "libresoc.v:34375.3-34399.6" wire $1\alu_branch0_br_op__lk$next[0:0]$1254 - attribute \src "libresoc.v:33725.7-33725.35" + attribute \src "libresoc.v:33773.7-33773.35" wire $1\alu_branch0_br_op__lk[0:0] - attribute \src "libresoc.v:33751.7-33751.26" + attribute \src "libresoc.v:33799.7-33799.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:34457.3-34465.6" + attribute \src "libresoc.v:34505.3-34513.6" wire $1\alu_l_r_alu$next[0:0]$1295 - attribute \src "libresoc.v:33759.7-33759.25" + attribute \src "libresoc.v:33807.7-33807.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:34448.3-34456.6" + attribute \src "libresoc.v:34496.3-34504.6" wire $1\alui_l_r_alui$next[0:0]$1292 - attribute \src "libresoc.v:33771.7-33771.27" + attribute \src "libresoc.v:33819.7-33819.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:34352.3-34373.6" + attribute \src "libresoc.v:34400.3-34421.6" wire width 64 $1\data_r0__fast1$next[63:0]$1260 - attribute \src "libresoc.v:33803.14-33803.51" + attribute \src "libresoc.v:33851.14-33851.51" wire width 64 $1\data_r0__fast1[63:0] - attribute \src "libresoc.v:34352.3-34373.6" + attribute \src "libresoc.v:34400.3-34421.6" wire $1\data_r0__fast1_ok$next[0:0]$1261 - attribute \src "libresoc.v:33807.7-33807.31" + attribute \src "libresoc.v:33855.7-33855.31" wire $1\data_r0__fast1_ok[0:0] - attribute \src "libresoc.v:34374.3-34395.6" + attribute \src "libresoc.v:34422.3-34443.6" wire width 64 $1\data_r1__fast2$next[63:0]$1268 - attribute \src "libresoc.v:33811.14-33811.51" + attribute \src "libresoc.v:33859.14-33859.51" wire width 64 $1\data_r1__fast2[63:0] - attribute \src "libresoc.v:34374.3-34395.6" + attribute \src "libresoc.v:34422.3-34443.6" wire $1\data_r1__fast2_ok$next[0:0]$1269 - attribute \src "libresoc.v:33815.7-33815.31" + attribute \src "libresoc.v:33863.7-33863.31" wire $1\data_r1__fast2_ok[0:0] - attribute \src "libresoc.v:34396.3-34417.6" + attribute \src "libresoc.v:34444.3-34465.6" wire width 64 $1\data_r2__nia$next[63:0]$1276 - attribute \src "libresoc.v:33819.14-33819.49" + attribute \src "libresoc.v:33867.14-33867.49" wire width 64 $1\data_r2__nia[63:0] - attribute \src "libresoc.v:34396.3-34417.6" + attribute \src "libresoc.v:34444.3-34465.6" wire $1\data_r2__nia_ok$next[0:0]$1277 - attribute \src "libresoc.v:33823.7-33823.29" + attribute \src "libresoc.v:33871.7-33871.29" wire $1\data_r2__nia_ok[0:0] - attribute \src "libresoc.v:34466.3-34475.6" + attribute \src "libresoc.v:34514.3-34523.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:34476.3-34485.6" + attribute \src "libresoc.v:34524.3-34533.6" wire width 64 $1\dest2_o[63:0] - attribute \src "libresoc.v:34486.3-34495.6" + attribute \src "libresoc.v:34534.3-34543.6" wire width 64 $1\dest3_o[63:0] - attribute \src "libresoc.v:34282.3-34290.6" + attribute \src "libresoc.v:34330.3-34338.6" wire $1\opc_l_r_opc$next[0:0]$1225 - attribute \src "libresoc.v:33844.7-33844.25" + attribute \src "libresoc.v:33892.7-33892.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:34273.3-34281.6" + attribute \src "libresoc.v:34321.3-34329.6" wire $1\opc_l_s_opc$next[0:0]$1222 - attribute \src "libresoc.v:33848.7-33848.25" + attribute \src "libresoc.v:33896.7-33896.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:34496.3-34504.6" + attribute \src "libresoc.v:34544.3-34552.6" wire width 3 $1\prev_wr_go$next[2:0]$1301 - attribute \src "libresoc.v:33958.13-33958.30" + attribute \src "libresoc.v:34006.13-34006.30" wire width 3 $1\prev_wr_go[2:0] - attribute \src "libresoc.v:34227.3-34236.6" + attribute \src "libresoc.v:34275.3-34284.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:34318.3-34326.6" + attribute \src "libresoc.v:34366.3-34374.6" wire width 3 $1\req_l_r_req$next[2:0]$1237 - attribute \src "libresoc.v:33966.13-33966.31" + attribute \src "libresoc.v:34014.13-34014.31" wire width 3 $1\req_l_r_req[2:0] - attribute \src "libresoc.v:34309.3-34317.6" + attribute \src "libresoc.v:34357.3-34365.6" wire width 3 $1\req_l_s_req$next[2:0]$1234 - attribute \src "libresoc.v:33970.13-33970.31" + attribute \src "libresoc.v:34018.13-34018.31" wire width 3 $1\req_l_s_req[2:0] - attribute \src "libresoc.v:34246.3-34254.6" + attribute \src "libresoc.v:34294.3-34302.6" wire $1\rok_l_r_rdok$next[0:0]$1213 - attribute \src "libresoc.v:33982.7-33982.26" + attribute \src "libresoc.v:34030.7-34030.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:34237.3-34245.6" + attribute \src "libresoc.v:34285.3-34293.6" wire $1\rok_l_s_rdok$next[0:0]$1210 - attribute \src "libresoc.v:33986.7-33986.26" + attribute \src "libresoc.v:34034.7-34034.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:34264.3-34272.6" + attribute \src "libresoc.v:34312.3-34320.6" wire $1\rst_l_r_rst$next[0:0]$1219 - attribute \src "libresoc.v:33990.7-33990.25" + attribute \src "libresoc.v:34038.7-34038.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:34255.3-34263.6" + attribute \src "libresoc.v:34303.3-34311.6" wire $1\rst_l_s_rst$next[0:0]$1216 - attribute \src "libresoc.v:33994.7-33994.25" + attribute \src "libresoc.v:34042.7-34042.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:34300.3-34308.6" + attribute \src "libresoc.v:34348.3-34356.6" wire width 3 $1\src_l_r_src$next[2:0]$1231 - attribute \src "libresoc.v:34008.13-34008.31" + attribute \src "libresoc.v:34056.13-34056.31" wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:34291.3-34299.6" + attribute \src "libresoc.v:34339.3-34347.6" wire width 3 $1\src_l_s_src$next[2:0]$1228 - attribute \src "libresoc.v:34012.13-34012.31" + attribute \src "libresoc.v:34060.13-34060.31" wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:34418.3-34427.6" + attribute \src "libresoc.v:34466.3-34475.6" wire width 64 $1\src_r0$next[63:0]$1283 - attribute \src "libresoc.v:34018.14-34018.43" + attribute \src "libresoc.v:34066.14-34066.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:34428.3-34437.6" + attribute \src "libresoc.v:34476.3-34485.6" wire width 64 $1\src_r1$next[63:0]$1286 - attribute \src "libresoc.v:34022.14-34022.43" + attribute \src "libresoc.v:34070.14-34070.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:34438.3-34447.6" + attribute \src "libresoc.v:34486.3-34495.6" wire width 4 $1\src_r2$next[3:0]$1289 - attribute \src "libresoc.v:34026.13-34026.26" + attribute \src "libresoc.v:34074.13-34074.26" wire width 4 $1\src_r2[3:0] - attribute \src "libresoc.v:34327.3-34351.6" + attribute \src "libresoc.v:34375.3-34399.6" wire width 64 $2\alu_branch0_br_op__imm_data__data$next[63:0]$1255 - attribute \src "libresoc.v:34327.3-34351.6" + attribute \src "libresoc.v:34375.3-34399.6" wire $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1256 - attribute \src "libresoc.v:34352.3-34373.6" + attribute \src "libresoc.v:34400.3-34421.6" wire width 64 $2\data_r0__fast1$next[63:0]$1262 - attribute \src "libresoc.v:34352.3-34373.6" + attribute \src "libresoc.v:34400.3-34421.6" wire $2\data_r0__fast1_ok$next[0:0]$1263 - attribute \src "libresoc.v:34374.3-34395.6" + attribute \src "libresoc.v:34422.3-34443.6" wire width 64 $2\data_r1__fast2$next[63:0]$1270 - attribute \src "libresoc.v:34374.3-34395.6" + attribute \src "libresoc.v:34422.3-34443.6" wire $2\data_r1__fast2_ok$next[0:0]$1271 - attribute \src "libresoc.v:34396.3-34417.6" + attribute \src "libresoc.v:34444.3-34465.6" wire width 64 $2\data_r2__nia$next[63:0]$1278 - attribute \src "libresoc.v:34396.3-34417.6" + attribute \src "libresoc.v:34444.3-34465.6" wire $2\data_r2__nia_ok$next[0:0]$1279 - attribute \src "libresoc.v:34352.3-34373.6" + attribute \src "libresoc.v:34400.3-34421.6" wire $3\data_r0__fast1_ok$next[0:0]$1264 - attribute \src "libresoc.v:34374.3-34395.6" + attribute \src "libresoc.v:34422.3-34443.6" wire $3\data_r1__fast2_ok$next[0:0]$1272 - attribute \src "libresoc.v:34396.3-34417.6" + attribute \src "libresoc.v:34444.3-34465.6" wire $3\data_r2__nia_ok$next[0:0]$1280 - attribute \src "libresoc.v:34034.18-34034.112" - wire width 3 $and$libresoc.v:34034$1119_Y - attribute \src "libresoc.v:34035.19-34035.125" - wire $and$libresoc.v:34035$1120_Y - attribute \src "libresoc.v:34036.19-34036.125" - wire $and$libresoc.v:34036$1121_Y - attribute \src "libresoc.v:34037.19-34037.125" - wire $and$libresoc.v:34037$1122_Y - attribute \src "libresoc.v:34038.19-34038.141" - wire width 3 $and$libresoc.v:34038$1123_Y - attribute \src "libresoc.v:34039.19-34039.121" - wire width 3 $and$libresoc.v:34039$1124_Y - attribute \src "libresoc.v:34040.19-34040.127" - wire $and$libresoc.v:34040$1125_Y - attribute \src "libresoc.v:34041.19-34041.127" - wire $and$libresoc.v:34041$1126_Y - attribute \src "libresoc.v:34042.19-34042.127" - wire $and$libresoc.v:34042$1127_Y - attribute \src "libresoc.v:34043.18-34043.110" - wire $and$libresoc.v:34043$1128_Y - attribute \src "libresoc.v:34045.18-34045.98" - wire $and$libresoc.v:34045$1130_Y - attribute \src "libresoc.v:34047.18-34047.100" - wire $and$libresoc.v:34047$1132_Y - attribute \src "libresoc.v:34048.18-34048.149" - wire width 3 $and$libresoc.v:34048$1133_Y - attribute \src "libresoc.v:34050.18-34050.119" - wire width 3 $and$libresoc.v:34050$1135_Y - attribute \src "libresoc.v:34053.18-34053.116" - wire $and$libresoc.v:34053$1138_Y - attribute \src "libresoc.v:34057.17-34057.123" - wire $and$libresoc.v:34057$1142_Y - attribute \src "libresoc.v:34059.18-34059.113" - wire $and$libresoc.v:34059$1144_Y - attribute \src "libresoc.v:34060.18-34060.125" - wire width 3 $and$libresoc.v:34060$1145_Y - attribute \src "libresoc.v:34062.18-34062.112" - wire $and$libresoc.v:34062$1147_Y - attribute \src "libresoc.v:34064.18-34064.129" - wire $and$libresoc.v:34064$1149_Y - attribute \src "libresoc.v:34065.18-34065.129" - wire $and$libresoc.v:34065$1150_Y - attribute \src "libresoc.v:34066.18-34066.117" - wire $and$libresoc.v:34066$1151_Y - attribute \src "libresoc.v:34071.18-34071.133" - wire $and$libresoc.v:34071$1156_Y - attribute \src "libresoc.v:34072.18-34072.124" - wire width 3 $and$libresoc.v:34072$1157_Y - attribute \src "libresoc.v:34075.18-34075.120" - wire $and$libresoc.v:34075$1160_Y - attribute \src "libresoc.v:34076.18-34076.120" - wire $and$libresoc.v:34076$1161_Y - attribute \src "libresoc.v:34077.18-34077.118" - wire $and$libresoc.v:34077$1162_Y - attribute \src "libresoc.v:34083.18-34083.137" - wire $and$libresoc.v:34083$1168_Y - attribute \src "libresoc.v:34085.18-34085.135" - wire $and$libresoc.v:34085$1170_Y - attribute \src "libresoc.v:34086.18-34086.149" - wire width 3 $and$libresoc.v:34086$1171_Y - attribute \src "libresoc.v:34088.18-34088.129" - wire width 3 $and$libresoc.v:34088$1173_Y - attribute \src "libresoc.v:34061.18-34061.113" - wire $eq$libresoc.v:34061$1146_Y - attribute \src "libresoc.v:34063.18-34063.119" - wire $eq$libresoc.v:34063$1148_Y - attribute \src "libresoc.v:34044.18-34044.97" - wire $not$libresoc.v:34044$1129_Y - attribute \src "libresoc.v:34046.18-34046.99" - wire $not$libresoc.v:34046$1131_Y - attribute \src "libresoc.v:34049.18-34049.113" - wire width 3 $not$libresoc.v:34049$1134_Y - attribute \src "libresoc.v:34052.18-34052.106" - wire $not$libresoc.v:34052$1137_Y - attribute \src "libresoc.v:34058.18-34058.123" - wire $not$libresoc.v:34058$1143_Y - attribute \src "libresoc.v:34073.17-34073.113" - wire width 3 $not$libresoc.v:34073$1158_Y - attribute \src "libresoc.v:34087.18-34087.133" - wire $not$libresoc.v:34087$1172_Y - attribute \src "libresoc.v:34089.18-34089.114" - wire width 3 $not$libresoc.v:34089$1174_Y - attribute \src "libresoc.v:34056.18-34056.112" - wire $or$libresoc.v:34056$1141_Y - attribute \src "libresoc.v:34067.18-34067.122" - wire $or$libresoc.v:34067$1152_Y - attribute \src "libresoc.v:34068.18-34068.124" - wire $or$libresoc.v:34068$1153_Y - attribute \src "libresoc.v:34069.18-34069.155" - wire width 3 $or$libresoc.v:34069$1154_Y - attribute \src "libresoc.v:34070.18-34070.155" - wire width 3 $or$libresoc.v:34070$1155_Y - attribute \src "libresoc.v:34074.18-34074.120" - wire width 3 $or$libresoc.v:34074$1159_Y - attribute \src "libresoc.v:34084.17-34084.117" - wire width 3 $or$libresoc.v:34084$1169_Y - attribute \src "libresoc.v:34033.17-34033.104" - wire $reduce_and$libresoc.v:34033$1118_Y - attribute \src "libresoc.v:34051.18-34051.106" - wire $reduce_or$libresoc.v:34051$1136_Y - attribute \src "libresoc.v:34054.18-34054.113" - wire $reduce_or$libresoc.v:34054$1139_Y - attribute \src "libresoc.v:34055.18-34055.112" - wire $reduce_or$libresoc.v:34055$1140_Y - attribute \src "libresoc.v:34078.18-34078.162" - wire $ternary$libresoc.v:34078$1163_Y - attribute \src "libresoc.v:34079.18-34079.176" - wire width 64 $ternary$libresoc.v:34079$1164_Y - attribute \src "libresoc.v:34080.18-34080.118" - wire width 64 $ternary$libresoc.v:34080$1165_Y - attribute \src "libresoc.v:34081.18-34081.115" - wire width 64 $ternary$libresoc.v:34081$1166_Y - attribute \src "libresoc.v:34082.18-34082.118" - wire width 4 $ternary$libresoc.v:34082$1167_Y + attribute \src "libresoc.v:34082.18-34082.112" + wire width 3 $and$libresoc.v:34082$1119_Y + attribute \src "libresoc.v:34083.19-34083.125" + wire $and$libresoc.v:34083$1120_Y + attribute \src "libresoc.v:34084.19-34084.125" + wire $and$libresoc.v:34084$1121_Y + attribute \src "libresoc.v:34085.19-34085.125" + wire $and$libresoc.v:34085$1122_Y + attribute \src "libresoc.v:34086.19-34086.141" + wire width 3 $and$libresoc.v:34086$1123_Y + attribute \src "libresoc.v:34087.19-34087.121" + wire width 3 $and$libresoc.v:34087$1124_Y + attribute \src "libresoc.v:34088.19-34088.127" + wire $and$libresoc.v:34088$1125_Y + attribute \src "libresoc.v:34089.19-34089.127" + wire $and$libresoc.v:34089$1126_Y + attribute \src "libresoc.v:34090.19-34090.127" + wire $and$libresoc.v:34090$1127_Y + attribute \src "libresoc.v:34091.18-34091.110" + wire $and$libresoc.v:34091$1128_Y + attribute \src "libresoc.v:34093.18-34093.98" + wire $and$libresoc.v:34093$1130_Y + attribute \src "libresoc.v:34095.18-34095.100" + wire $and$libresoc.v:34095$1132_Y + attribute \src "libresoc.v:34096.18-34096.149" + wire width 3 $and$libresoc.v:34096$1133_Y + attribute \src "libresoc.v:34098.18-34098.119" + wire width 3 $and$libresoc.v:34098$1135_Y + attribute \src "libresoc.v:34101.18-34101.116" + wire $and$libresoc.v:34101$1138_Y + attribute \src "libresoc.v:34105.17-34105.123" + wire $and$libresoc.v:34105$1142_Y + attribute \src "libresoc.v:34107.18-34107.113" + wire $and$libresoc.v:34107$1144_Y + attribute \src "libresoc.v:34108.18-34108.125" + wire width 3 $and$libresoc.v:34108$1145_Y + attribute \src "libresoc.v:34110.18-34110.112" + wire $and$libresoc.v:34110$1147_Y + attribute \src "libresoc.v:34112.18-34112.129" + wire $and$libresoc.v:34112$1149_Y + attribute \src "libresoc.v:34113.18-34113.129" + wire $and$libresoc.v:34113$1150_Y + attribute \src "libresoc.v:34114.18-34114.117" + wire $and$libresoc.v:34114$1151_Y + attribute \src "libresoc.v:34119.18-34119.133" + wire $and$libresoc.v:34119$1156_Y + attribute \src "libresoc.v:34120.18-34120.124" + wire width 3 $and$libresoc.v:34120$1157_Y + attribute \src "libresoc.v:34123.18-34123.120" + wire $and$libresoc.v:34123$1160_Y + attribute \src "libresoc.v:34124.18-34124.120" + wire $and$libresoc.v:34124$1161_Y + attribute \src "libresoc.v:34125.18-34125.118" + wire $and$libresoc.v:34125$1162_Y + attribute \src "libresoc.v:34131.18-34131.137" + wire $and$libresoc.v:34131$1168_Y + attribute \src "libresoc.v:34133.18-34133.135" + wire $and$libresoc.v:34133$1170_Y + attribute \src "libresoc.v:34134.18-34134.149" + wire width 3 $and$libresoc.v:34134$1171_Y + attribute \src "libresoc.v:34136.18-34136.129" + wire width 3 $and$libresoc.v:34136$1173_Y + attribute \src "libresoc.v:34109.18-34109.113" + wire $eq$libresoc.v:34109$1146_Y + attribute \src "libresoc.v:34111.18-34111.119" + wire $eq$libresoc.v:34111$1148_Y + attribute \src "libresoc.v:34092.18-34092.97" + wire $not$libresoc.v:34092$1129_Y + attribute \src "libresoc.v:34094.18-34094.99" + wire $not$libresoc.v:34094$1131_Y + attribute \src "libresoc.v:34097.18-34097.113" + wire width 3 $not$libresoc.v:34097$1134_Y + attribute \src "libresoc.v:34100.18-34100.106" + wire $not$libresoc.v:34100$1137_Y + attribute \src "libresoc.v:34106.18-34106.123" + wire $not$libresoc.v:34106$1143_Y + attribute \src "libresoc.v:34121.17-34121.113" + wire width 3 $not$libresoc.v:34121$1158_Y + attribute \src "libresoc.v:34135.18-34135.133" + wire $not$libresoc.v:34135$1172_Y + attribute \src "libresoc.v:34137.18-34137.114" + wire width 3 $not$libresoc.v:34137$1174_Y + attribute \src "libresoc.v:34104.18-34104.112" + wire $or$libresoc.v:34104$1141_Y + attribute \src "libresoc.v:34115.18-34115.122" + wire $or$libresoc.v:34115$1152_Y + attribute \src "libresoc.v:34116.18-34116.124" + wire $or$libresoc.v:34116$1153_Y + attribute \src "libresoc.v:34117.18-34117.155" + wire width 3 $or$libresoc.v:34117$1154_Y + attribute \src "libresoc.v:34118.18-34118.155" + wire width 3 $or$libresoc.v:34118$1155_Y + attribute \src "libresoc.v:34122.18-34122.120" + wire width 3 $or$libresoc.v:34122$1159_Y + attribute \src "libresoc.v:34132.17-34132.117" + wire width 3 $or$libresoc.v:34132$1169_Y + attribute \src "libresoc.v:34081.17-34081.104" + wire $reduce_and$libresoc.v:34081$1118_Y + attribute \src "libresoc.v:34099.18-34099.106" + wire $reduce_or$libresoc.v:34099$1136_Y + attribute \src "libresoc.v:34102.18-34102.113" + wire $reduce_or$libresoc.v:34102$1139_Y + attribute \src "libresoc.v:34103.18-34103.112" + wire $reduce_or$libresoc.v:34103$1140_Y + attribute \src "libresoc.v:34126.18-34126.162" + wire $ternary$libresoc.v:34126$1163_Y + attribute \src "libresoc.v:34127.18-34127.176" + wire width 64 $ternary$libresoc.v:34127$1164_Y + attribute \src "libresoc.v:34128.18-34128.118" + wire width 64 $ternary$libresoc.v:34128$1165_Y + attribute \src "libresoc.v:34129.18-34129.115" + wire width 64 $ternary$libresoc.v:34129$1166_Y + attribute \src "libresoc.v:34130.18-34130.118" + wire width 4 $ternary$libresoc.v:34130$1167_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" @@ -50601,9 +50637,9 @@ module \branch0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 26 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 11 \cu_busy_o @@ -50661,7 +50697,7 @@ module \branch0 wire output 18 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 21 \fast2_ok - attribute \src "libresoc.v:33481.7-33481.15" + attribute \src "libresoc.v:33529.7-33529.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 24 \nia_ok @@ -50858,7 +50894,7 @@ module \branch0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:34034$1119 + cell $and $and$libresoc.v:34082$1119 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50866,10 +50902,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \$95 connect \B \$97 - connect \Y $and$libresoc.v:34034$1119_Y + connect \Y $and$libresoc.v:34082$1119_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:34035$1120 + cell $and $and$libresoc.v:34083$1120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50877,10 +50913,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:34035$1120_Y + connect \Y $and$libresoc.v:34083$1120_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:34036$1121 + cell $and $and$libresoc.v:34084$1121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50888,10 +50924,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:34036$1121_Y + connect \Y $and$libresoc.v:34084$1121_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:34037$1122 + cell $and $and$libresoc.v:34085$1122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50899,10 +50935,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:34037$1122_Y + connect \Y $and$libresoc.v:34085$1122_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:34038$1123 + cell $and $and$libresoc.v:34086$1123 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50910,10 +50946,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B { \$101 \$103 \$105 } - connect \Y $and$libresoc.v:34038$1123_Y + connect \Y $and$libresoc.v:34086$1123_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:34039$1124 + cell $and $and$libresoc.v:34087$1124 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50921,10 +50957,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \$107 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:34039$1124_Y + connect \Y $and$libresoc.v:34087$1124_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:34040$1125 + cell $and $and$libresoc.v:34088$1125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50932,10 +50968,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:34040$1125_Y + connect \Y $and$libresoc.v:34088$1125_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:34041$1126 + cell $and $and$libresoc.v:34089$1126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50943,10 +50979,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:34041$1126_Y + connect \Y $and$libresoc.v:34089$1126_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:34042$1127 + cell $and $and$libresoc.v:34090$1127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50954,10 +50990,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:34042$1127_Y + connect \Y $and$libresoc.v:34090$1127_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:34043$1128 + cell $and $and$libresoc.v:34091$1128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50965,10 +51001,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 - connect \Y $and$libresoc.v:34043$1128_Y + connect \Y $and$libresoc.v:34091$1128_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:34045$1130 + cell $and $and$libresoc.v:34093$1130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50976,10 +51012,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$13 - connect \Y $and$libresoc.v:34045$1130_Y + connect \Y $and$libresoc.v:34093$1130_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:34047$1132 + cell $and $and$libresoc.v:34095$1132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -50987,10 +51023,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$17 - connect \Y $and$libresoc.v:34047$1132_Y + connect \Y $and$libresoc.v:34095$1132_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:34048$1133 + cell $and $and$libresoc.v:34096$1133 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -50998,10 +51034,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:34048$1133_Y + connect \Y $and$libresoc.v:34096$1133_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:34050$1135 + cell $and $and$libresoc.v:34098$1135 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -51009,10 +51045,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \cu_wr__rel_o connect \B \$25 - connect \Y $and$libresoc.v:34050$1135_Y + connect \Y $and$libresoc.v:34098$1135_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:34053$1138 + cell $and $and$libresoc.v:34101$1138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -51020,10 +51056,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$23 - connect \Y $and$libresoc.v:34053$1138_Y + connect \Y $and$libresoc.v:34101$1138_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:34057$1142 + cell $and $and$libresoc.v:34105$1142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -51031,10 +51067,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:34057$1142_Y + connect \Y $and$libresoc.v:34105$1142_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:34059$1144 + cell $and $and$libresoc.v:34107$1144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -51042,10 +51078,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$39 - connect \Y $and$libresoc.v:34059$1144_Y + connect \Y $and$libresoc.v:34107$1144_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:34060$1145 + cell $and $and$libresoc.v:34108$1145 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -51053,10 +51089,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:34060$1145_Y + connect \Y $and$libresoc.v:34108$1145_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:34062$1147 + cell $and $and$libresoc.v:34110$1147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -51064,10 +51100,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \$41 connect \B \$45 - connect \Y $and$libresoc.v:34062$1147_Y + connect \Y $and$libresoc.v:34110$1147_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:34064$1149 + cell $and $and$libresoc.v:34112$1149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -51075,10 +51111,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_branch0_n_ready_i - connect \Y $and$libresoc.v:34064$1149_Y + connect \Y $and$libresoc.v:34112$1149_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:34065$1150 + cell $and $and$libresoc.v:34113$1150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -51086,10 +51122,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \$51 connect \B \alu_branch0_n_valid_o - connect \Y $and$libresoc.v:34065$1150_Y + connect \Y $and$libresoc.v:34113$1150_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:34066$1151 + cell $and $and$libresoc.v:34114$1151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -51097,10 +51133,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \$53 connect \B \cu_busy_o - connect \Y $and$libresoc.v:34066$1151_Y + connect \Y $and$libresoc.v:34114$1151_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:34071$1156 + cell $and $and$libresoc.v:34119$1156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -51108,10 +51144,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \alu_branch0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:34071$1156_Y + connect \Y $and$libresoc.v:34119$1156_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:34072$1157 + cell $and $and$libresoc.v:34120$1157 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -51119,10 +51155,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:34072$1157_Y + connect \Y $and$libresoc.v:34120$1157_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:34075$1160 + cell $and $and$libresoc.v:34123$1160 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -51130,10 +51166,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \fast1_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:34075$1160_Y + connect \Y $and$libresoc.v:34123$1160_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:34076$1161 + cell $and $and$libresoc.v:34124$1161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -51141,10 +51177,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \fast2_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:34076$1161_Y + connect \Y $and$libresoc.v:34124$1161_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:34077$1162 + cell $and $and$libresoc.v:34125$1162 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -51152,10 +51188,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \nia_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:34077$1162_Y + connect \Y $and$libresoc.v:34125$1162_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:34083$1168 + cell $and $and$libresoc.v:34131$1168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -51163,10 +51199,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \alu_branch0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:34083$1168_Y + connect \Y $and$libresoc.v:34131$1168_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:34085$1170 + cell $and $and$libresoc.v:34133$1170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -51174,10 +51210,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \alu_branch0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:34085$1170_Y + connect \Y $and$libresoc.v:34133$1170_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:34086$1171 + cell $and $and$libresoc.v:34134$1171 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -51185,10 +51221,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:34086$1171_Y + connect \Y $and$libresoc.v:34134$1171_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:34088$1173 + cell $and $and$libresoc.v:34136$1173 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -51196,10 +51232,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \$91 connect \B { 1'1 \$93 1'1 } - connect \Y $and$libresoc.v:34088$1173_Y + connect \Y $and$libresoc.v:34136$1173_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:34061$1146 + cell $eq $eq$libresoc.v:34109$1146 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -51207,10 +51243,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \$43 connect \B 1'0 - connect \Y $eq$libresoc.v:34061$1146_Y + connect \Y $eq$libresoc.v:34109$1146_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:34063$1148 + cell $eq $eq$libresoc.v:34111$1148 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -51218,74 +51254,74 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:34063$1148_Y + connect \Y $eq$libresoc.v:34111$1148_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:34044$1129 + cell $not $not$libresoc.v:34092$1129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:34044$1129_Y + connect \Y $not$libresoc.v:34092$1129_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:34046$1131 + cell $not $not$libresoc.v:34094$1131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:34046$1131_Y + connect \Y $not$libresoc.v:34094$1131_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:34049$1134 + cell $not $not$libresoc.v:34097$1134 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:34049$1134_Y + connect \Y $not$libresoc.v:34097$1134_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:34052$1137 + cell $not $not$libresoc.v:34100$1137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:34052$1137_Y + connect \Y $not$libresoc.v:34100$1137_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:34058$1143 + cell $not $not$libresoc.v:34106$1143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_branch0_n_ready_i - connect \Y $not$libresoc.v:34058$1143_Y + connect \Y $not$libresoc.v:34106$1143_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:34073$1158 + cell $not $not$libresoc.v:34121$1158 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:34073$1158_Y + connect \Y $not$libresoc.v:34121$1158_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:34087$1172 + cell $not $not$libresoc.v:34135$1172 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_branch0_br_op__imm_data__ok - connect \Y $not$libresoc.v:34087$1172_Y + connect \Y $not$libresoc.v:34135$1172_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:34089$1174 + cell $not $not$libresoc.v:34137$1174 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:34089$1174_Y + connect \Y $not$libresoc.v:34137$1174_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:34056$1141 + cell $or $or$libresoc.v:34104$1141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -51293,10 +51329,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \$33 connect \B \$35 - connect \Y $or$libresoc.v:34056$1141_Y + connect \Y $or$libresoc.v:34104$1141_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:34067$1152 + cell $or $or$libresoc.v:34115$1152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -51304,10 +51340,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:34067$1152_Y + connect \Y $or$libresoc.v:34115$1152_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:34068$1153 + cell $or $or$libresoc.v:34116$1153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -51315,10 +51351,10 @@ module \branch0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:34068$1153_Y + connect \Y $or$libresoc.v:34116$1153_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:34069$1154 + cell $or $or$libresoc.v:34117$1154 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -51326,10 +51362,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:34069$1154_Y + connect \Y $or$libresoc.v:34117$1154_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:34070$1155 + cell $or $or$libresoc.v:34118$1155 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -51337,10 +51373,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:34070$1155_Y + connect \Y $or$libresoc.v:34118$1155_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:34074$1159 + cell $or $or$libresoc.v:34122$1159 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -51348,10 +51384,10 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:34074$1159_Y + connect \Y $or$libresoc.v:34122$1159_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:34084$1169 + cell $or $or$libresoc.v:34132$1169 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -51359,82 +51395,82 @@ module \branch0 parameter \Y_WIDTH 3 connect \A \$6 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:34084$1169_Y + connect \Y $or$libresoc.v:34132$1169_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:34033$1118 + cell $reduce_and $reduce_and$libresoc.v:34081$1118 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $reduce_and$libresoc.v:34033$1118_Y + connect \Y $reduce_and$libresoc.v:34081$1118_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:34051$1136 + cell $reduce_or $reduce_or$libresoc.v:34099$1136 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$27 - connect \Y $reduce_or$libresoc.v:34051$1136_Y + connect \Y $reduce_or$libresoc.v:34099$1136_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:34054$1139 + cell $reduce_or $reduce_or$libresoc.v:34102$1139 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:34054$1139_Y + connect \Y $reduce_or$libresoc.v:34102$1139_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:34055$1140 + cell $reduce_or $reduce_or$libresoc.v:34103$1140 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:34055$1140_Y + connect \Y $reduce_or$libresoc.v:34103$1140_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:34078$1163 + cell $mux $ternary$libresoc.v:34126$1163 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_branch0_br_op__imm_data__ok - connect \Y $ternary$libresoc.v:34078$1163_Y + connect \Y $ternary$libresoc.v:34126$1163_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:34079$1164 + cell $mux $ternary$libresoc.v:34127$1164 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_branch0_br_op__imm_data__data connect \S \alu_branch0_br_op__imm_data__ok - connect \Y $ternary$libresoc.v:34079$1164_Y + connect \Y $ternary$libresoc.v:34127$1164_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:34080$1165 + cell $mux $ternary$libresoc.v:34128$1165 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:34080$1165_Y + connect \Y $ternary$libresoc.v:34128$1165_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:34081$1166 + cell $mux $ternary$libresoc.v:34129$1166 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:34081$1166_Y + connect \Y $ternary$libresoc.v:34129$1166_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:34082$1167 + cell $mux $ternary$libresoc.v:34130$1167 parameter \WIDTH 4 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:34082$1167_Y + connect \Y $ternary$libresoc.v:34130$1167_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:34154.15-34178.4" + attribute \src "libresoc.v:34202.15-34226.4" cell \alu_branch0 \alu_branch0 connect \br_op__cia \alu_branch0_br_op__cia connect \br_op__fn_unit \alu_branch0_br_op__fn_unit @@ -51461,7 +51497,7 @@ module \branch0 connect \p_valid_i \alu_branch0_p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:34179.14-34185.4" + attribute \src "libresoc.v:34227.14-34233.4" cell \alu_l$29 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -51470,7 +51506,7 @@ module \branch0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:34186.15-34192.4" + attribute \src "libresoc.v:34234.15-34240.4" cell \alui_l$28 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -51479,7 +51515,7 @@ module \branch0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:34193.14-34199.4" + attribute \src "libresoc.v:34241.14-34247.4" cell \opc_l$24 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -51488,7 +51524,7 @@ module \branch0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:34200.14-34206.4" + attribute \src "libresoc.v:34248.14-34254.4" cell \req_l$25 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -51497,7 +51533,7 @@ module \branch0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:34207.14-34213.4" + attribute \src "libresoc.v:34255.14-34261.4" cell \rok_l$27 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -51506,7 +51542,7 @@ module \branch0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:34214.14-34219.4" + attribute \src "libresoc.v:34262.14-34267.4" cell \rst_l$26 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -51514,7 +51550,7 @@ module \branch0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:34220.14-34226.4" + attribute \src "libresoc.v:34268.14-34274.4" cell \src_l$23 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -51522,502 +51558,502 @@ module \branch0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:33481.7-33481.20" - process $proc$libresoc.v:33481$1302 + attribute \src "libresoc.v:33529.7-33529.20" + process $proc$libresoc.v:33529$1302 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:33599.7-33599.24" - process $proc$libresoc.v:33599$1303 + attribute \src "libresoc.v:33647.7-33647.24" + process $proc$libresoc.v:33647$1303 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:33607.14-33607.59" - process $proc$libresoc.v:33607$1304 + attribute \src "libresoc.v:33655.14-33655.59" + process $proc$libresoc.v:33655$1304 assign { } { } assign $1\alu_branch0_br_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_branch0_br_op__cia $1\alu_branch0_br_op__cia[63:0] end - attribute \src "libresoc.v:33626.14-33626.51" - process $proc$libresoc.v:33626$1305 + attribute \src "libresoc.v:33674.14-33674.51" + process $proc$libresoc.v:33674$1305 assign { } { } assign $1\alu_branch0_br_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_branch0_br_op__fn_unit $1\alu_branch0_br_op__fn_unit[13:0] end - attribute \src "libresoc.v:33630.14-33630.70" - process $proc$libresoc.v:33630$1306 + attribute \src "libresoc.v:33678.14-33678.70" + process $proc$libresoc.v:33678$1306 assign { } { } assign $1\alu_branch0_br_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_branch0_br_op__imm_data__data $1\alu_branch0_br_op__imm_data__data[63:0] end - attribute \src "libresoc.v:33634.7-33634.45" - process $proc$libresoc.v:33634$1307 + attribute \src "libresoc.v:33682.7-33682.45" + process $proc$libresoc.v:33682$1307 assign { } { } assign $1\alu_branch0_br_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_branch0_br_op__imm_data__ok $1\alu_branch0_br_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:33638.14-33638.45" - process $proc$libresoc.v:33638$1308 + attribute \src "libresoc.v:33686.14-33686.45" + process $proc$libresoc.v:33686$1308 assign { } { } assign $1\alu_branch0_br_op__insn[31:0] 0 sync always sync init update \alu_branch0_br_op__insn $1\alu_branch0_br_op__insn[31:0] end - attribute \src "libresoc.v:33717.13-33717.49" - process $proc$libresoc.v:33717$1309 + attribute \src "libresoc.v:33765.13-33765.49" + process $proc$libresoc.v:33765$1309 assign { } { } assign $1\alu_branch0_br_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_branch0_br_op__insn_type $1\alu_branch0_br_op__insn_type[6:0] end - attribute \src "libresoc.v:33721.7-33721.41" - process $proc$libresoc.v:33721$1310 + attribute \src "libresoc.v:33769.7-33769.41" + process $proc$libresoc.v:33769$1310 assign { } { } assign $1\alu_branch0_br_op__is_32bit[0:0] 1'0 sync always sync init update \alu_branch0_br_op__is_32bit $1\alu_branch0_br_op__is_32bit[0:0] end - attribute \src "libresoc.v:33725.7-33725.35" - process $proc$libresoc.v:33725$1311 + attribute \src "libresoc.v:33773.7-33773.35" + process $proc$libresoc.v:33773$1311 assign { } { } assign $1\alu_branch0_br_op__lk[0:0] 1'0 sync always sync init update \alu_branch0_br_op__lk $1\alu_branch0_br_op__lk[0:0] end - attribute \src "libresoc.v:33751.7-33751.26" - process $proc$libresoc.v:33751$1312 + attribute \src "libresoc.v:33799.7-33799.26" + process $proc$libresoc.v:33799$1312 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:33759.7-33759.25" - process $proc$libresoc.v:33759$1313 + attribute \src "libresoc.v:33807.7-33807.25" + process $proc$libresoc.v:33807$1313 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:33771.7-33771.27" - process $proc$libresoc.v:33771$1314 + attribute \src "libresoc.v:33819.7-33819.27" + process $proc$libresoc.v:33819$1314 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:33803.14-33803.51" - process $proc$libresoc.v:33803$1315 + attribute \src "libresoc.v:33851.14-33851.51" + process $proc$libresoc.v:33851$1315 assign { } { } assign $1\data_r0__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__fast1 $1\data_r0__fast1[63:0] end - attribute \src "libresoc.v:33807.7-33807.31" - process $proc$libresoc.v:33807$1316 + attribute \src "libresoc.v:33855.7-33855.31" + process $proc$libresoc.v:33855$1316 assign { } { } assign $1\data_r0__fast1_ok[0:0] 1'0 sync always sync init update \data_r0__fast1_ok $1\data_r0__fast1_ok[0:0] end - attribute \src "libresoc.v:33811.14-33811.51" - process $proc$libresoc.v:33811$1317 + attribute \src "libresoc.v:33859.14-33859.51" + process $proc$libresoc.v:33859$1317 assign { } { } assign $1\data_r1__fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r1__fast2 $1\data_r1__fast2[63:0] end - attribute \src "libresoc.v:33815.7-33815.31" - process $proc$libresoc.v:33815$1318 + attribute \src "libresoc.v:33863.7-33863.31" + process $proc$libresoc.v:33863$1318 assign { } { } assign $1\data_r1__fast2_ok[0:0] 1'0 sync always sync init update \data_r1__fast2_ok $1\data_r1__fast2_ok[0:0] end - attribute \src "libresoc.v:33819.14-33819.49" - process $proc$libresoc.v:33819$1319 + attribute \src "libresoc.v:33867.14-33867.49" + process $proc$libresoc.v:33867$1319 assign { } { } assign $1\data_r2__nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r2__nia $1\data_r2__nia[63:0] end - attribute \src "libresoc.v:33823.7-33823.29" - process $proc$libresoc.v:33823$1320 + attribute \src "libresoc.v:33871.7-33871.29" + process $proc$libresoc.v:33871$1320 assign { } { } assign $1\data_r2__nia_ok[0:0] 1'0 sync always sync init update \data_r2__nia_ok $1\data_r2__nia_ok[0:0] end - attribute \src "libresoc.v:33844.7-33844.25" - process $proc$libresoc.v:33844$1321 + attribute \src "libresoc.v:33892.7-33892.25" + process $proc$libresoc.v:33892$1321 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:33848.7-33848.25" - process $proc$libresoc.v:33848$1322 + attribute \src "libresoc.v:33896.7-33896.25" + process $proc$libresoc.v:33896$1322 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:33958.13-33958.30" - process $proc$libresoc.v:33958$1323 + attribute \src "libresoc.v:34006.13-34006.30" + process $proc$libresoc.v:34006$1323 assign { } { } assign $1\prev_wr_go[2:0] 3'000 sync always sync init update \prev_wr_go $1\prev_wr_go[2:0] end - attribute \src "libresoc.v:33966.13-33966.31" - process $proc$libresoc.v:33966$1324 + attribute \src "libresoc.v:34014.13-34014.31" + process $proc$libresoc.v:34014$1324 assign { } { } assign $1\req_l_r_req[2:0] 3'111 sync always sync init update \req_l_r_req $1\req_l_r_req[2:0] end - attribute \src "libresoc.v:33970.13-33970.31" - process $proc$libresoc.v:33970$1325 + attribute \src "libresoc.v:34018.13-34018.31" + process $proc$libresoc.v:34018$1325 assign { } { } assign $1\req_l_s_req[2:0] 3'000 sync always sync init update \req_l_s_req $1\req_l_s_req[2:0] end - attribute \src "libresoc.v:33982.7-33982.26" - process $proc$libresoc.v:33982$1326 + attribute \src "libresoc.v:34030.7-34030.26" + process $proc$libresoc.v:34030$1326 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:33986.7-33986.26" - process $proc$libresoc.v:33986$1327 + attribute \src "libresoc.v:34034.7-34034.26" + process $proc$libresoc.v:34034$1327 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:33990.7-33990.25" - process $proc$libresoc.v:33990$1328 + attribute \src "libresoc.v:34038.7-34038.25" + process $proc$libresoc.v:34038$1328 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:33994.7-33994.25" - process $proc$libresoc.v:33994$1329 + attribute \src "libresoc.v:34042.7-34042.25" + process $proc$libresoc.v:34042$1329 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:34008.13-34008.31" - process $proc$libresoc.v:34008$1330 + attribute \src "libresoc.v:34056.13-34056.31" + process $proc$libresoc.v:34056$1330 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end - attribute \src "libresoc.v:34012.13-34012.31" - process $proc$libresoc.v:34012$1331 + attribute \src "libresoc.v:34060.13-34060.31" + process $proc$libresoc.v:34060$1331 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end - attribute \src "libresoc.v:34018.14-34018.43" - process $proc$libresoc.v:34018$1332 + attribute \src "libresoc.v:34066.14-34066.43" + process $proc$libresoc.v:34066$1332 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:34022.14-34022.43" - process $proc$libresoc.v:34022$1333 + attribute \src "libresoc.v:34070.14-34070.43" + process $proc$libresoc.v:34070$1333 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:34026.13-34026.26" - process $proc$libresoc.v:34026$1334 + attribute \src "libresoc.v:34074.13-34074.26" + process $proc$libresoc.v:34074$1334 assign { } { } assign $1\src_r2[3:0] 4'0000 sync always sync init update \src_r2 $1\src_r2[3:0] end - attribute \src "libresoc.v:34090.3-34091.39" - process $proc$libresoc.v:34090$1175 + attribute \src "libresoc.v:34138.3-34139.39" + process $proc$libresoc.v:34138$1175 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:34092.3-34093.43" - process $proc$libresoc.v:34092$1176 + attribute \src "libresoc.v:34140.3-34141.43" + process $proc$libresoc.v:34140$1176 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:34094.3-34095.29" - process $proc$libresoc.v:34094$1177 + attribute \src "libresoc.v:34142.3-34143.29" + process $proc$libresoc.v:34142$1177 assign { } { } assign $0\src_r2[3:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[3:0] end - attribute \src "libresoc.v:34096.3-34097.29" - process $proc$libresoc.v:34096$1178 + attribute \src "libresoc.v:34144.3-34145.29" + process $proc$libresoc.v:34144$1178 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:34098.3-34099.29" - process $proc$libresoc.v:34098$1179 + attribute \src "libresoc.v:34146.3-34147.29" + process $proc$libresoc.v:34146$1179 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:34100.3-34101.41" - process $proc$libresoc.v:34100$1180 + attribute \src "libresoc.v:34148.3-34149.41" + process $proc$libresoc.v:34148$1180 assign { } { } assign $0\data_r2__nia[63:0] \data_r2__nia$next sync posedge \coresync_clk update \data_r2__nia $0\data_r2__nia[63:0] end - attribute \src "libresoc.v:34102.3-34103.47" - process $proc$libresoc.v:34102$1181 + attribute \src "libresoc.v:34150.3-34151.47" + process $proc$libresoc.v:34150$1181 assign { } { } assign $0\data_r2__nia_ok[0:0] \data_r2__nia_ok$next sync posedge \coresync_clk update \data_r2__nia_ok $0\data_r2__nia_ok[0:0] end - attribute \src "libresoc.v:34104.3-34105.45" - process $proc$libresoc.v:34104$1182 + attribute \src "libresoc.v:34152.3-34153.45" + process $proc$libresoc.v:34152$1182 assign { } { } assign $0\data_r1__fast2[63:0] \data_r1__fast2$next sync posedge \coresync_clk update \data_r1__fast2 $0\data_r1__fast2[63:0] end - attribute \src "libresoc.v:34106.3-34107.51" - process $proc$libresoc.v:34106$1183 + attribute \src "libresoc.v:34154.3-34155.51" + process $proc$libresoc.v:34154$1183 assign { } { } assign $0\data_r1__fast2_ok[0:0] \data_r1__fast2_ok$next sync posedge \coresync_clk update \data_r1__fast2_ok $0\data_r1__fast2_ok[0:0] end - attribute \src "libresoc.v:34108.3-34109.45" - process $proc$libresoc.v:34108$1184 + attribute \src "libresoc.v:34156.3-34157.45" + process $proc$libresoc.v:34156$1184 assign { } { } assign $0\data_r0__fast1[63:0] \data_r0__fast1$next sync posedge \coresync_clk update \data_r0__fast1 $0\data_r0__fast1[63:0] end - attribute \src "libresoc.v:34110.3-34111.51" - process $proc$libresoc.v:34110$1185 + attribute \src "libresoc.v:34158.3-34159.51" + process $proc$libresoc.v:34158$1185 assign { } { } assign $0\data_r0__fast1_ok[0:0] \data_r0__fast1_ok$next sync posedge \coresync_clk update \data_r0__fast1_ok $0\data_r0__fast1_ok[0:0] end - attribute \src "libresoc.v:34112.3-34113.61" - process $proc$libresoc.v:34112$1186 + attribute \src "libresoc.v:34160.3-34161.61" + process $proc$libresoc.v:34160$1186 assign { } { } assign $0\alu_branch0_br_op__cia[63:0] \alu_branch0_br_op__cia$next sync posedge \coresync_clk update \alu_branch0_br_op__cia $0\alu_branch0_br_op__cia[63:0] end - attribute \src "libresoc.v:34114.3-34115.73" - process $proc$libresoc.v:34114$1187 + attribute \src "libresoc.v:34162.3-34163.73" + process $proc$libresoc.v:34162$1187 assign { } { } assign $0\alu_branch0_br_op__insn_type[6:0] \alu_branch0_br_op__insn_type$next sync posedge \coresync_clk update \alu_branch0_br_op__insn_type $0\alu_branch0_br_op__insn_type[6:0] end - attribute \src "libresoc.v:34116.3-34117.69" - process $proc$libresoc.v:34116$1188 + attribute \src "libresoc.v:34164.3-34165.69" + process $proc$libresoc.v:34164$1188 assign { } { } assign $0\alu_branch0_br_op__fn_unit[13:0] \alu_branch0_br_op__fn_unit$next sync posedge \coresync_clk update \alu_branch0_br_op__fn_unit $0\alu_branch0_br_op__fn_unit[13:0] end - attribute \src "libresoc.v:34118.3-34119.63" - process $proc$libresoc.v:34118$1189 + attribute \src "libresoc.v:34166.3-34167.63" + process $proc$libresoc.v:34166$1189 assign { } { } assign $0\alu_branch0_br_op__insn[31:0] \alu_branch0_br_op__insn$next sync posedge \coresync_clk update \alu_branch0_br_op__insn $0\alu_branch0_br_op__insn[31:0] end - attribute \src "libresoc.v:34120.3-34121.83" - process $proc$libresoc.v:34120$1190 + attribute \src "libresoc.v:34168.3-34169.83" + process $proc$libresoc.v:34168$1190 assign { } { } assign $0\alu_branch0_br_op__imm_data__data[63:0] \alu_branch0_br_op__imm_data__data$next sync posedge \coresync_clk update \alu_branch0_br_op__imm_data__data $0\alu_branch0_br_op__imm_data__data[63:0] end - attribute \src "libresoc.v:34122.3-34123.79" - process $proc$libresoc.v:34122$1191 + attribute \src "libresoc.v:34170.3-34171.79" + process $proc$libresoc.v:34170$1191 assign { } { } assign $0\alu_branch0_br_op__imm_data__ok[0:0] \alu_branch0_br_op__imm_data__ok$next sync posedge \coresync_clk update \alu_branch0_br_op__imm_data__ok $0\alu_branch0_br_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:34124.3-34125.59" - process $proc$libresoc.v:34124$1192 + attribute \src "libresoc.v:34172.3-34173.59" + process $proc$libresoc.v:34172$1192 assign { } { } assign $0\alu_branch0_br_op__lk[0:0] \alu_branch0_br_op__lk$next sync posedge \coresync_clk update \alu_branch0_br_op__lk $0\alu_branch0_br_op__lk[0:0] end - attribute \src "libresoc.v:34126.3-34127.71" - process $proc$libresoc.v:34126$1193 + attribute \src "libresoc.v:34174.3-34175.71" + process $proc$libresoc.v:34174$1193 assign { } { } assign $0\alu_branch0_br_op__is_32bit[0:0] \alu_branch0_br_op__is_32bit$next sync posedge \coresync_clk update \alu_branch0_br_op__is_32bit $0\alu_branch0_br_op__is_32bit[0:0] end - attribute \src "libresoc.v:34128.3-34129.39" - process $proc$libresoc.v:34128$1194 + attribute \src "libresoc.v:34176.3-34177.39" + process $proc$libresoc.v:34176$1194 assign { } { } assign $0\req_l_r_req[2:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[2:0] end - attribute \src "libresoc.v:34130.3-34131.39" - process $proc$libresoc.v:34130$1195 + attribute \src "libresoc.v:34178.3-34179.39" + process $proc$libresoc.v:34178$1195 assign { } { } assign $0\req_l_s_req[2:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[2:0] end - attribute \src "libresoc.v:34132.3-34133.39" - process $proc$libresoc.v:34132$1196 + attribute \src "libresoc.v:34180.3-34181.39" + process $proc$libresoc.v:34180$1196 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "libresoc.v:34134.3-34135.39" - process $proc$libresoc.v:34134$1197 + attribute \src "libresoc.v:34182.3-34183.39" + process $proc$libresoc.v:34182$1197 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:34136.3-34137.39" - process $proc$libresoc.v:34136$1198 + attribute \src "libresoc.v:34184.3-34185.39" + process $proc$libresoc.v:34184$1198 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:34138.3-34139.39" - process $proc$libresoc.v:34138$1199 + attribute \src "libresoc.v:34186.3-34187.39" + process $proc$libresoc.v:34186$1199 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:34140.3-34141.39" - process $proc$libresoc.v:34140$1200 + attribute \src "libresoc.v:34188.3-34189.39" + process $proc$libresoc.v:34188$1200 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:34142.3-34143.39" - process $proc$libresoc.v:34142$1201 + attribute \src "libresoc.v:34190.3-34191.39" + process $proc$libresoc.v:34190$1201 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:34144.3-34145.41" - process $proc$libresoc.v:34144$1202 + attribute \src "libresoc.v:34192.3-34193.41" + process $proc$libresoc.v:34192$1202 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:34146.3-34147.41" - process $proc$libresoc.v:34146$1203 + attribute \src "libresoc.v:34194.3-34195.41" + process $proc$libresoc.v:34194$1203 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:34148.3-34149.37" - process $proc$libresoc.v:34148$1204 + attribute \src "libresoc.v:34196.3-34197.37" + process $proc$libresoc.v:34196$1204 assign { } { } assign $0\prev_wr_go[2:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[2:0] end - attribute \src "libresoc.v:34150.3-34151.43" - process $proc$libresoc.v:34150$1205 + attribute \src "libresoc.v:34198.3-34199.43" + process $proc$libresoc.v:34198$1205 assign { } { } assign $0\alu_done_dly[0:0] \alu_branch0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:34152.3-34153.25" - process $proc$libresoc.v:34152$1206 + attribute \src "libresoc.v:34200.3-34201.25" + process $proc$libresoc.v:34200$1206 assign { } { } assign $0\all_rd_dly[0:0] \$11 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:34227.3-34236.6" - process $proc$libresoc.v:34227$1207 + attribute \src "libresoc.v:34275.3-34284.6" + process $proc$libresoc.v:34275$1207 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:34228.5-34228.29" + attribute \src "libresoc.v:34276.5-34276.29" switch \initial - attribute \src "libresoc.v:34228.9-34228.17" + attribute \src "libresoc.v:34276.9-34276.17" case 1'1 case end @@ -52033,14 +52069,14 @@ module \branch0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:34237.3-34245.6" - process $proc$libresoc.v:34237$1208 + attribute \src "libresoc.v:34285.3-34293.6" + process $proc$libresoc.v:34285$1208 assign { } { } assign { } { } assign $0\rok_l_s_rdok$next[0:0]$1209 $1\rok_l_s_rdok$next[0:0]$1210 - attribute \src "libresoc.v:34238.5-34238.29" + attribute \src "libresoc.v:34286.5-34286.29" switch \initial - attribute \src "libresoc.v:34238.9-34238.17" + attribute \src "libresoc.v:34286.9-34286.17" case 1'1 case end @@ -52056,14 +52092,14 @@ module \branch0 sync always update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$1209 end - attribute \src "libresoc.v:34246.3-34254.6" - process $proc$libresoc.v:34246$1211 + attribute \src "libresoc.v:34294.3-34302.6" + process $proc$libresoc.v:34294$1211 assign { } { } assign { } { } assign $0\rok_l_r_rdok$next[0:0]$1212 $1\rok_l_r_rdok$next[0:0]$1213 - attribute \src "libresoc.v:34247.5-34247.29" + attribute \src "libresoc.v:34295.5-34295.29" switch \initial - attribute \src "libresoc.v:34247.9-34247.17" + attribute \src "libresoc.v:34295.9-34295.17" case 1'1 case end @@ -52079,14 +52115,14 @@ module \branch0 sync always update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$1212 end - attribute \src "libresoc.v:34255.3-34263.6" - process $proc$libresoc.v:34255$1214 + attribute \src "libresoc.v:34303.3-34311.6" + process $proc$libresoc.v:34303$1214 assign { } { } assign { } { } assign $0\rst_l_s_rst$next[0:0]$1215 $1\rst_l_s_rst$next[0:0]$1216 - attribute \src "libresoc.v:34256.5-34256.29" + attribute \src "libresoc.v:34304.5-34304.29" switch \initial - attribute \src "libresoc.v:34256.9-34256.17" + attribute \src "libresoc.v:34304.9-34304.17" case 1'1 case end @@ -52102,14 +52138,14 @@ module \branch0 sync always update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$1215 end - attribute \src "libresoc.v:34264.3-34272.6" - process $proc$libresoc.v:34264$1217 + attribute \src "libresoc.v:34312.3-34320.6" + process $proc$libresoc.v:34312$1217 assign { } { } assign { } { } assign $0\rst_l_r_rst$next[0:0]$1218 $1\rst_l_r_rst$next[0:0]$1219 - attribute \src "libresoc.v:34265.5-34265.29" + attribute \src "libresoc.v:34313.5-34313.29" switch \initial - attribute \src "libresoc.v:34265.9-34265.17" + attribute \src "libresoc.v:34313.9-34313.17" case 1'1 case end @@ -52125,14 +52161,14 @@ module \branch0 sync always update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$1218 end - attribute \src "libresoc.v:34273.3-34281.6" - process $proc$libresoc.v:34273$1220 + attribute \src "libresoc.v:34321.3-34329.6" + process $proc$libresoc.v:34321$1220 assign { } { } assign { } { } assign $0\opc_l_s_opc$next[0:0]$1221 $1\opc_l_s_opc$next[0:0]$1222 - attribute \src "libresoc.v:34274.5-34274.29" + attribute \src "libresoc.v:34322.5-34322.29" switch \initial - attribute \src "libresoc.v:34274.9-34274.17" + attribute \src "libresoc.v:34322.9-34322.17" case 1'1 case end @@ -52148,14 +52184,14 @@ module \branch0 sync always update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$1221 end - attribute \src "libresoc.v:34282.3-34290.6" - process $proc$libresoc.v:34282$1223 + attribute \src "libresoc.v:34330.3-34338.6" + process $proc$libresoc.v:34330$1223 assign { } { } assign { } { } assign $0\opc_l_r_opc$next[0:0]$1224 $1\opc_l_r_opc$next[0:0]$1225 - attribute \src "libresoc.v:34283.5-34283.29" + attribute \src "libresoc.v:34331.5-34331.29" switch \initial - attribute \src "libresoc.v:34283.9-34283.17" + attribute \src "libresoc.v:34331.9-34331.17" case 1'1 case end @@ -52171,14 +52207,14 @@ module \branch0 sync always update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$1224 end - attribute \src "libresoc.v:34291.3-34299.6" - process $proc$libresoc.v:34291$1226 + attribute \src "libresoc.v:34339.3-34347.6" + process $proc$libresoc.v:34339$1226 assign { } { } assign { } { } assign $0\src_l_s_src$next[2:0]$1227 $1\src_l_s_src$next[2:0]$1228 - attribute \src "libresoc.v:34292.5-34292.29" + attribute \src "libresoc.v:34340.5-34340.29" switch \initial - attribute \src "libresoc.v:34292.9-34292.17" + attribute \src "libresoc.v:34340.9-34340.17" case 1'1 case end @@ -52194,14 +52230,14 @@ module \branch0 sync always update \src_l_s_src$next $0\src_l_s_src$next[2:0]$1227 end - attribute \src "libresoc.v:34300.3-34308.6" - process $proc$libresoc.v:34300$1229 + attribute \src "libresoc.v:34348.3-34356.6" + process $proc$libresoc.v:34348$1229 assign { } { } assign { } { } assign $0\src_l_r_src$next[2:0]$1230 $1\src_l_r_src$next[2:0]$1231 - attribute \src "libresoc.v:34301.5-34301.29" + attribute \src "libresoc.v:34349.5-34349.29" switch \initial - attribute \src "libresoc.v:34301.9-34301.17" + attribute \src "libresoc.v:34349.9-34349.17" case 1'1 case end @@ -52217,14 +52253,14 @@ module \branch0 sync always update \src_l_r_src$next $0\src_l_r_src$next[2:0]$1230 end - attribute \src "libresoc.v:34309.3-34317.6" - process $proc$libresoc.v:34309$1232 + attribute \src "libresoc.v:34357.3-34365.6" + process $proc$libresoc.v:34357$1232 assign { } { } assign { } { } assign $0\req_l_s_req$next[2:0]$1233 $1\req_l_s_req$next[2:0]$1234 - attribute \src "libresoc.v:34310.5-34310.29" + attribute \src "libresoc.v:34358.5-34358.29" switch \initial - attribute \src "libresoc.v:34310.9-34310.17" + attribute \src "libresoc.v:34358.9-34358.17" case 1'1 case end @@ -52240,14 +52276,14 @@ module \branch0 sync always update \req_l_s_req$next $0\req_l_s_req$next[2:0]$1233 end - attribute \src "libresoc.v:34318.3-34326.6" - process $proc$libresoc.v:34318$1235 + attribute \src "libresoc.v:34366.3-34374.6" + process $proc$libresoc.v:34366$1235 assign { } { } assign { } { } assign $0\req_l_r_req$next[2:0]$1236 $1\req_l_r_req$next[2:0]$1237 - attribute \src "libresoc.v:34319.5-34319.29" + attribute \src "libresoc.v:34367.5-34367.29" switch \initial - attribute \src "libresoc.v:34319.9-34319.17" + attribute \src "libresoc.v:34367.9-34367.17" case 1'1 case end @@ -52263,8 +52299,8 @@ module \branch0 sync always update \req_l_r_req$next $0\req_l_r_req$next[2:0]$1236 end - attribute \src "libresoc.v:34327.3-34351.6" - process $proc$libresoc.v:34327$1238 + attribute \src "libresoc.v:34375.3-34399.6" + process $proc$libresoc.v:34375$1238 assign { } { } assign { } { } assign { } { } @@ -52291,9 +52327,9 @@ module \branch0 assign $0\alu_branch0_br_op__lk$next[0:0]$1246 $1\alu_branch0_br_op__lk$next[0:0]$1254 assign $0\alu_branch0_br_op__imm_data__data$next[63:0]$1241 $2\alu_branch0_br_op__imm_data__data$next[63:0]$1255 assign $0\alu_branch0_br_op__imm_data__ok$next[0:0]$1242 $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1256 - attribute \src "libresoc.v:34328.5-34328.29" + attribute \src "libresoc.v:34376.5-34376.29" switch \initial - attribute \src "libresoc.v:34328.9-34328.17" + attribute \src "libresoc.v:34376.9-34376.17" case 1'1 case end @@ -52342,8 +52378,8 @@ module \branch0 update \alu_branch0_br_op__is_32bit$next $0\alu_branch0_br_op__is_32bit$next[0:0]$1245 update \alu_branch0_br_op__lk$next $0\alu_branch0_br_op__lk$next[0:0]$1246 end - attribute \src "libresoc.v:34352.3-34373.6" - process $proc$libresoc.v:34352$1257 + attribute \src "libresoc.v:34400.3-34421.6" + process $proc$libresoc.v:34400$1257 assign { } { } assign { } { } assign { } { } @@ -52353,9 +52389,9 @@ module \branch0 assign $0\data_r0__fast1$next[63:0]$1258 $2\data_r0__fast1$next[63:0]$1262 assign { } { } assign $0\data_r0__fast1_ok$next[0:0]$1259 $3\data_r0__fast1_ok$next[0:0]$1264 - attribute \src "libresoc.v:34353.5-34353.29" + attribute \src "libresoc.v:34401.5-34401.29" switch \initial - attribute \src "libresoc.v:34353.9-34353.17" + attribute \src "libresoc.v:34401.9-34401.17" case 1'1 case end @@ -52394,8 +52430,8 @@ module \branch0 update \data_r0__fast1$next $0\data_r0__fast1$next[63:0]$1258 update \data_r0__fast1_ok$next $0\data_r0__fast1_ok$next[0:0]$1259 end - attribute \src "libresoc.v:34374.3-34395.6" - process $proc$libresoc.v:34374$1265 + attribute \src "libresoc.v:34422.3-34443.6" + process $proc$libresoc.v:34422$1265 assign { } { } assign { } { } assign { } { } @@ -52405,9 +52441,9 @@ module \branch0 assign $0\data_r1__fast2$next[63:0]$1266 $2\data_r1__fast2$next[63:0]$1270 assign { } { } assign $0\data_r1__fast2_ok$next[0:0]$1267 $3\data_r1__fast2_ok$next[0:0]$1272 - attribute \src "libresoc.v:34375.5-34375.29" + attribute \src "libresoc.v:34423.5-34423.29" switch \initial - attribute \src "libresoc.v:34375.9-34375.17" + attribute \src "libresoc.v:34423.9-34423.17" case 1'1 case end @@ -52446,8 +52482,8 @@ module \branch0 update \data_r1__fast2$next $0\data_r1__fast2$next[63:0]$1266 update \data_r1__fast2_ok$next $0\data_r1__fast2_ok$next[0:0]$1267 end - attribute \src "libresoc.v:34396.3-34417.6" - process $proc$libresoc.v:34396$1273 + attribute \src "libresoc.v:34444.3-34465.6" + process $proc$libresoc.v:34444$1273 assign { } { } assign { } { } assign { } { } @@ -52457,9 +52493,9 @@ module \branch0 assign $0\data_r2__nia$next[63:0]$1274 $2\data_r2__nia$next[63:0]$1278 assign { } { } assign $0\data_r2__nia_ok$next[0:0]$1275 $3\data_r2__nia_ok$next[0:0]$1280 - attribute \src "libresoc.v:34397.5-34397.29" + attribute \src "libresoc.v:34445.5-34445.29" switch \initial - attribute \src "libresoc.v:34397.9-34397.17" + attribute \src "libresoc.v:34445.9-34445.17" case 1'1 case end @@ -52498,14 +52534,14 @@ module \branch0 update \data_r2__nia$next $0\data_r2__nia$next[63:0]$1274 update \data_r2__nia_ok$next $0\data_r2__nia_ok$next[0:0]$1275 end - attribute \src "libresoc.v:34418.3-34427.6" - process $proc$libresoc.v:34418$1281 + attribute \src "libresoc.v:34466.3-34475.6" + process $proc$libresoc.v:34466$1281 assign { } { } assign { } { } assign $0\src_r0$next[63:0]$1282 $1\src_r0$next[63:0]$1283 - attribute \src "libresoc.v:34419.5-34419.29" + attribute \src "libresoc.v:34467.5-34467.29" switch \initial - attribute \src "libresoc.v:34419.9-34419.17" + attribute \src "libresoc.v:34467.9-34467.17" case 1'1 case end @@ -52521,14 +52557,14 @@ module \branch0 sync always update \src_r0$next $0\src_r0$next[63:0]$1282 end - attribute \src "libresoc.v:34428.3-34437.6" - process $proc$libresoc.v:34428$1284 + attribute \src "libresoc.v:34476.3-34485.6" + process $proc$libresoc.v:34476$1284 assign { } { } assign { } { } assign $0\src_r1$next[63:0]$1285 $1\src_r1$next[63:0]$1286 - attribute \src "libresoc.v:34429.5-34429.29" + attribute \src "libresoc.v:34477.5-34477.29" switch \initial - attribute \src "libresoc.v:34429.9-34429.17" + attribute \src "libresoc.v:34477.9-34477.17" case 1'1 case end @@ -52544,14 +52580,14 @@ module \branch0 sync always update \src_r1$next $0\src_r1$next[63:0]$1285 end - attribute \src "libresoc.v:34438.3-34447.6" - process $proc$libresoc.v:34438$1287 + attribute \src "libresoc.v:34486.3-34495.6" + process $proc$libresoc.v:34486$1287 assign { } { } assign { } { } assign $0\src_r2$next[3:0]$1288 $1\src_r2$next[3:0]$1289 - attribute \src "libresoc.v:34439.5-34439.29" + attribute \src "libresoc.v:34487.5-34487.29" switch \initial - attribute \src "libresoc.v:34439.9-34439.17" + attribute \src "libresoc.v:34487.9-34487.17" case 1'1 case end @@ -52567,14 +52603,14 @@ module \branch0 sync always update \src_r2$next $0\src_r2$next[3:0]$1288 end - attribute \src "libresoc.v:34448.3-34456.6" - process $proc$libresoc.v:34448$1290 + attribute \src "libresoc.v:34496.3-34504.6" + process $proc$libresoc.v:34496$1290 assign { } { } assign { } { } assign $0\alui_l_r_alui$next[0:0]$1291 $1\alui_l_r_alui$next[0:0]$1292 - attribute \src "libresoc.v:34449.5-34449.29" + attribute \src "libresoc.v:34497.5-34497.29" switch \initial - attribute \src "libresoc.v:34449.9-34449.17" + attribute \src "libresoc.v:34497.9-34497.17" case 1'1 case end @@ -52590,14 +52626,14 @@ module \branch0 sync always update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$1291 end - attribute \src "libresoc.v:34457.3-34465.6" - process $proc$libresoc.v:34457$1293 + attribute \src "libresoc.v:34505.3-34513.6" + process $proc$libresoc.v:34505$1293 assign { } { } assign { } { } assign $0\alu_l_r_alu$next[0:0]$1294 $1\alu_l_r_alu$next[0:0]$1295 - attribute \src "libresoc.v:34458.5-34458.29" + attribute \src "libresoc.v:34506.5-34506.29" switch \initial - attribute \src "libresoc.v:34458.9-34458.17" + attribute \src "libresoc.v:34506.9-34506.17" case 1'1 case end @@ -52613,14 +52649,14 @@ module \branch0 sync always update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$1294 end - attribute \src "libresoc.v:34466.3-34475.6" - process $proc$libresoc.v:34466$1296 + attribute \src "libresoc.v:34514.3-34523.6" + process $proc$libresoc.v:34514$1296 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:34467.5-34467.29" + attribute \src "libresoc.v:34515.5-34515.29" switch \initial - attribute \src "libresoc.v:34467.9-34467.17" + attribute \src "libresoc.v:34515.9-34515.17" case 1'1 case end @@ -52636,14 +52672,14 @@ module \branch0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:34476.3-34485.6" - process $proc$libresoc.v:34476$1297 + attribute \src "libresoc.v:34524.3-34533.6" + process $proc$libresoc.v:34524$1297 assign { } { } assign { } { } assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "libresoc.v:34477.5-34477.29" + attribute \src "libresoc.v:34525.5-34525.29" switch \initial - attribute \src "libresoc.v:34477.9-34477.17" + attribute \src "libresoc.v:34525.9-34525.17" case 1'1 case end @@ -52659,14 +52695,14 @@ module \branch0 sync always update \dest2_o $0\dest2_o[63:0] end - attribute \src "libresoc.v:34486.3-34495.6" - process $proc$libresoc.v:34486$1298 + attribute \src "libresoc.v:34534.3-34543.6" + process $proc$libresoc.v:34534$1298 assign { } { } assign { } { } assign $0\dest3_o[63:0] $1\dest3_o[63:0] - attribute \src "libresoc.v:34487.5-34487.29" + attribute \src "libresoc.v:34535.5-34535.29" switch \initial - attribute \src "libresoc.v:34487.9-34487.17" + attribute \src "libresoc.v:34535.9-34535.17" case 1'1 case end @@ -52682,14 +52718,14 @@ module \branch0 sync always update \dest3_o $0\dest3_o[63:0] end - attribute \src "libresoc.v:34496.3-34504.6" - process $proc$libresoc.v:34496$1299 + attribute \src "libresoc.v:34544.3-34552.6" + process $proc$libresoc.v:34544$1299 assign { } { } assign { } { } assign $0\prev_wr_go$next[2:0]$1300 $1\prev_wr_go$next[2:0]$1301 - attribute \src "libresoc.v:34497.5-34497.29" + attribute \src "libresoc.v:34545.5-34545.29" switch \initial - attribute \src "libresoc.v:34497.9-34497.17" + attribute \src "libresoc.v:34545.9-34545.17" case 1'1 case end @@ -52705,63 +52741,63 @@ module \branch0 sync always update \prev_wr_go$next $0\prev_wr_go$next[2:0]$1300 end - connect \$5 $reduce_and$libresoc.v:34033$1118_Y - connect \$99 $and$libresoc.v:34034$1119_Y - connect \$101 $and$libresoc.v:34035$1120_Y - connect \$103 $and$libresoc.v:34036$1121_Y - connect \$105 $and$libresoc.v:34037$1122_Y - connect \$107 $and$libresoc.v:34038$1123_Y - connect \$109 $and$libresoc.v:34039$1124_Y - connect \$111 $and$libresoc.v:34040$1125_Y - connect \$113 $and$libresoc.v:34041$1126_Y - connect \$115 $and$libresoc.v:34042$1127_Y - connect \$11 $and$libresoc.v:34043$1128_Y - connect \$13 $not$libresoc.v:34044$1129_Y - connect \$15 $and$libresoc.v:34045$1130_Y - connect \$17 $not$libresoc.v:34046$1131_Y - connect \$19 $and$libresoc.v:34047$1132_Y - connect \$21 $and$libresoc.v:34048$1133_Y - connect \$25 $not$libresoc.v:34049$1134_Y - connect \$27 $and$libresoc.v:34050$1135_Y - connect \$24 $reduce_or$libresoc.v:34051$1136_Y - connect \$23 $not$libresoc.v:34052$1137_Y - connect \$31 $and$libresoc.v:34053$1138_Y - connect \$33 $reduce_or$libresoc.v:34054$1139_Y - connect \$35 $reduce_or$libresoc.v:34055$1140_Y - connect \$37 $or$libresoc.v:34056$1141_Y - connect \$3 $and$libresoc.v:34057$1142_Y - connect \$39 $not$libresoc.v:34058$1143_Y - connect \$41 $and$libresoc.v:34059$1144_Y - connect \$43 $and$libresoc.v:34060$1145_Y - connect \$45 $eq$libresoc.v:34061$1146_Y - connect \$47 $and$libresoc.v:34062$1147_Y - connect \$49 $eq$libresoc.v:34063$1148_Y - connect \$51 $and$libresoc.v:34064$1149_Y - connect \$53 $and$libresoc.v:34065$1150_Y - connect \$55 $and$libresoc.v:34066$1151_Y - connect \$57 $or$libresoc.v:34067$1152_Y - connect \$59 $or$libresoc.v:34068$1153_Y - connect \$61 $or$libresoc.v:34069$1154_Y - connect \$63 $or$libresoc.v:34070$1155_Y - connect \$65 $and$libresoc.v:34071$1156_Y - connect \$67 $and$libresoc.v:34072$1157_Y - connect \$6 $not$libresoc.v:34073$1158_Y - connect \$69 $or$libresoc.v:34074$1159_Y - connect \$71 $and$libresoc.v:34075$1160_Y - connect \$73 $and$libresoc.v:34076$1161_Y - connect \$75 $and$libresoc.v:34077$1162_Y - connect \$77 $ternary$libresoc.v:34078$1163_Y - connect \$79 $ternary$libresoc.v:34079$1164_Y - connect \$81 $ternary$libresoc.v:34080$1165_Y - connect \$83 $ternary$libresoc.v:34081$1166_Y - connect \$85 $ternary$libresoc.v:34082$1167_Y - connect \$87 $and$libresoc.v:34083$1168_Y - connect \$8 $or$libresoc.v:34084$1169_Y - connect \$89 $and$libresoc.v:34085$1170_Y - connect \$91 $and$libresoc.v:34086$1171_Y - connect \$93 $not$libresoc.v:34087$1172_Y - connect \$95 $and$libresoc.v:34088$1173_Y - connect \$97 $not$libresoc.v:34089$1174_Y + connect \$5 $reduce_and$libresoc.v:34081$1118_Y + connect \$99 $and$libresoc.v:34082$1119_Y + connect \$101 $and$libresoc.v:34083$1120_Y + connect \$103 $and$libresoc.v:34084$1121_Y + connect \$105 $and$libresoc.v:34085$1122_Y + connect \$107 $and$libresoc.v:34086$1123_Y + connect \$109 $and$libresoc.v:34087$1124_Y + connect \$111 $and$libresoc.v:34088$1125_Y + connect \$113 $and$libresoc.v:34089$1126_Y + connect \$115 $and$libresoc.v:34090$1127_Y + connect \$11 $and$libresoc.v:34091$1128_Y + connect \$13 $not$libresoc.v:34092$1129_Y + connect \$15 $and$libresoc.v:34093$1130_Y + connect \$17 $not$libresoc.v:34094$1131_Y + connect \$19 $and$libresoc.v:34095$1132_Y + connect \$21 $and$libresoc.v:34096$1133_Y + connect \$25 $not$libresoc.v:34097$1134_Y + connect \$27 $and$libresoc.v:34098$1135_Y + connect \$24 $reduce_or$libresoc.v:34099$1136_Y + connect \$23 $not$libresoc.v:34100$1137_Y + connect \$31 $and$libresoc.v:34101$1138_Y + connect \$33 $reduce_or$libresoc.v:34102$1139_Y + connect \$35 $reduce_or$libresoc.v:34103$1140_Y + connect \$37 $or$libresoc.v:34104$1141_Y + connect \$3 $and$libresoc.v:34105$1142_Y + connect \$39 $not$libresoc.v:34106$1143_Y + connect \$41 $and$libresoc.v:34107$1144_Y + connect \$43 $and$libresoc.v:34108$1145_Y + connect \$45 $eq$libresoc.v:34109$1146_Y + connect \$47 $and$libresoc.v:34110$1147_Y + connect \$49 $eq$libresoc.v:34111$1148_Y + connect \$51 $and$libresoc.v:34112$1149_Y + connect \$53 $and$libresoc.v:34113$1150_Y + connect \$55 $and$libresoc.v:34114$1151_Y + connect \$57 $or$libresoc.v:34115$1152_Y + connect \$59 $or$libresoc.v:34116$1153_Y + connect \$61 $or$libresoc.v:34117$1154_Y + connect \$63 $or$libresoc.v:34118$1155_Y + connect \$65 $and$libresoc.v:34119$1156_Y + connect \$67 $and$libresoc.v:34120$1157_Y + connect \$6 $not$libresoc.v:34121$1158_Y + connect \$69 $or$libresoc.v:34122$1159_Y + connect \$71 $and$libresoc.v:34123$1160_Y + connect \$73 $and$libresoc.v:34124$1161_Y + connect \$75 $and$libresoc.v:34125$1162_Y + connect \$77 $ternary$libresoc.v:34126$1163_Y + connect \$79 $ternary$libresoc.v:34127$1164_Y + connect \$81 $ternary$libresoc.v:34128$1165_Y + connect \$83 $ternary$libresoc.v:34129$1166_Y + connect \$85 $ternary$libresoc.v:34130$1167_Y + connect \$87 $and$libresoc.v:34131$1168_Y + connect \$8 $or$libresoc.v:34132$1169_Y + connect \$89 $and$libresoc.v:34133$1170_Y + connect \$91 $and$libresoc.v:34134$1171_Y + connect \$93 $not$libresoc.v:34135$1172_Y + connect \$95 $and$libresoc.v:34136$1173_Y + connect \$97 $not$libresoc.v:34137$1174_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$109 @@ -52793,37 +52829,37 @@ module \branch0 connect \all_rd_dly$next \all_rd connect \all_rd \$11 end -attribute \src "libresoc.v:34539.1-34597.10" +attribute \src "libresoc.v:34587.1-34645.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.busy_l" attribute \generator "nMigen" module \busy_l - attribute \src "libresoc.v:34540.7-34540.20" + attribute \src "libresoc.v:34588.7-34588.20" wire $0\initial[0:0] - attribute \src "libresoc.v:34585.3-34593.6" + attribute \src "libresoc.v:34633.3-34641.6" wire $0\q_int$next[0:0]$1345 - attribute \src "libresoc.v:34583.3-34584.27" + attribute \src "libresoc.v:34631.3-34632.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:34585.3-34593.6" + attribute \src "libresoc.v:34633.3-34641.6" wire $1\q_int$next[0:0]$1346 - attribute \src "libresoc.v:34564.7-34564.19" + attribute \src "libresoc.v:34612.7-34612.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:34575.17-34575.96" - wire $and$libresoc.v:34575$1335_Y - attribute \src "libresoc.v:34580.17-34580.96" - wire $and$libresoc.v:34580$1340_Y - attribute \src "libresoc.v:34577.18-34577.94" - wire $not$libresoc.v:34577$1337_Y - attribute \src "libresoc.v:34579.17-34579.93" - wire $not$libresoc.v:34579$1339_Y - attribute \src "libresoc.v:34582.17-34582.93" - wire $not$libresoc.v:34582$1342_Y - attribute \src "libresoc.v:34576.18-34576.99" - wire $or$libresoc.v:34576$1336_Y - attribute \src "libresoc.v:34578.18-34578.100" - wire $or$libresoc.v:34578$1338_Y - attribute \src "libresoc.v:34581.17-34581.98" - wire $or$libresoc.v:34581$1341_Y + attribute \src "libresoc.v:34623.17-34623.96" + wire $and$libresoc.v:34623$1335_Y + attribute \src "libresoc.v:34628.17-34628.96" + wire $and$libresoc.v:34628$1340_Y + attribute \src "libresoc.v:34625.18-34625.94" + wire $not$libresoc.v:34625$1337_Y + attribute \src "libresoc.v:34627.17-34627.93" + wire $not$libresoc.v:34627$1339_Y + attribute \src "libresoc.v:34630.17-34630.93" + wire $not$libresoc.v:34630$1342_Y + attribute \src "libresoc.v:34624.18-34624.99" + wire $or$libresoc.v:34624$1336_Y + attribute \src "libresoc.v:34626.18-34626.100" + wire $or$libresoc.v:34626$1338_Y + attribute \src "libresoc.v:34629.17-34629.98" + wire $or$libresoc.v:34629$1341_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -52840,11 +52876,11 @@ module \busy_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:34540.7-34540.15" + attribute \src "libresoc.v:34588.7-34588.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_busy @@ -52861,7 +52897,7 @@ module \busy_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:34575$1335 + cell $and $and$libresoc.v:34623$1335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -52869,10 +52905,10 @@ module \busy_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:34575$1335_Y + connect \Y $and$libresoc.v:34623$1335_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:34580$1340 + cell $and $and$libresoc.v:34628$1340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -52880,34 +52916,34 @@ module \busy_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:34580$1340_Y + connect \Y $and$libresoc.v:34628$1340_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:34577$1337 + cell $not $not$libresoc.v:34625$1337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_busy - connect \Y $not$libresoc.v:34577$1337_Y + connect \Y $not$libresoc.v:34625$1337_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:34579$1339 + cell $not $not$libresoc.v:34627$1339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_busy - connect \Y $not$libresoc.v:34579$1339_Y + connect \Y $not$libresoc.v:34627$1339_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:34582$1342 + cell $not $not$libresoc.v:34630$1342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_busy - connect \Y $not$libresoc.v:34582$1342_Y + connect \Y $not$libresoc.v:34630$1342_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:34576$1336 + cell $or $or$libresoc.v:34624$1336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -52915,10 +52951,10 @@ module \busy_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_busy - connect \Y $or$libresoc.v:34576$1336_Y + connect \Y $or$libresoc.v:34624$1336_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:34578$1338 + cell $or $or$libresoc.v:34626$1338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -52926,10 +52962,10 @@ module \busy_l parameter \Y_WIDTH 1 connect \A \q_busy connect \B \q_int - connect \Y $or$libresoc.v:34578$1338_Y + connect \Y $or$libresoc.v:34626$1338_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:34581$1341 + cell $or $or$libresoc.v:34629$1341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -52937,39 +52973,39 @@ module \busy_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_busy - connect \Y $or$libresoc.v:34581$1341_Y + connect \Y $or$libresoc.v:34629$1341_Y end - attribute \src "libresoc.v:34540.7-34540.20" - process $proc$libresoc.v:34540$1347 + attribute \src "libresoc.v:34588.7-34588.20" + process $proc$libresoc.v:34588$1347 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:34564.7-34564.19" - process $proc$libresoc.v:34564$1348 + attribute \src "libresoc.v:34612.7-34612.19" + process $proc$libresoc.v:34612$1348 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:34583.3-34584.27" - process $proc$libresoc.v:34583$1343 + attribute \src "libresoc.v:34631.3-34632.27" + process $proc$libresoc.v:34631$1343 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:34585.3-34593.6" - process $proc$libresoc.v:34585$1344 + attribute \src "libresoc.v:34633.3-34641.6" + process $proc$libresoc.v:34633$1344 assign { } { } assign { } { } assign $0\q_int$next[0:0]$1345 $1\q_int$next[0:0]$1346 - attribute \src "libresoc.v:34586.5-34586.29" + attribute \src "libresoc.v:34634.5-34634.29" switch \initial - attribute \src "libresoc.v:34586.9-34586.17" + attribute \src "libresoc.v:34634.9-34634.17" case 1'1 case end @@ -52985,525 +53021,525 @@ module \busy_l sync always update \q_int$next $0\q_int$next[0:0]$1345 end - connect \$9 $and$libresoc.v:34575$1335_Y - connect \$11 $or$libresoc.v:34576$1336_Y - connect \$13 $not$libresoc.v:34577$1337_Y - connect \$15 $or$libresoc.v:34578$1338_Y - connect \$1 $not$libresoc.v:34579$1339_Y - connect \$3 $and$libresoc.v:34580$1340_Y - connect \$5 $or$libresoc.v:34581$1341_Y - connect \$7 $not$libresoc.v:34582$1342_Y + connect \$9 $and$libresoc.v:34623$1335_Y + connect \$11 $or$libresoc.v:34624$1336_Y + connect \$13 $not$libresoc.v:34625$1337_Y + connect \$15 $or$libresoc.v:34626$1338_Y + connect \$1 $not$libresoc.v:34627$1339_Y + connect \$3 $and$libresoc.v:34628$1340_Y + connect \$5 $or$libresoc.v:34629$1341_Y + connect \$7 $not$libresoc.v:34630$1342_Y connect \qlq_busy \$15 connect \qn_busy \$13 connect \q_busy \$11 end -attribute \src "libresoc.v:34601.1-36209.10" +attribute \src "libresoc.v:34649.1-36257.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main.clz" attribute \generator "nMigen" module \clz - attribute \src "libresoc.v:35076.3-35090.6" + attribute \src "libresoc.v:35124.3-35138.6" wire width 2 $0\cnt_1_0[1:0] - attribute \src "libresoc.v:35166.3-35180.6" + attribute \src "libresoc.v:35214.3-35228.6" wire width 2 $0\cnt_1_10[1:0] - attribute \src "libresoc.v:35181.3-35195.6" + attribute \src "libresoc.v:35229.3-35243.6" wire width 2 $0\cnt_1_11[1:0] - attribute \src "libresoc.v:35196.3-35210.6" + attribute \src "libresoc.v:35244.3-35258.6" wire width 2 $0\cnt_1_12[1:0] - attribute \src "libresoc.v:35211.3-35225.6" + attribute \src "libresoc.v:35259.3-35273.6" wire width 2 $0\cnt_1_13[1:0] - attribute \src "libresoc.v:35226.3-35240.6" + attribute \src "libresoc.v:35274.3-35288.6" wire width 2 $0\cnt_1_14[1:0] - attribute \src "libresoc.v:35256.3-35270.6" + attribute \src "libresoc.v:35304.3-35318.6" wire width 2 $0\cnt_1_15[1:0] - attribute \src "libresoc.v:35271.3-35285.6" + attribute \src "libresoc.v:35319.3-35333.6" wire width 2 $0\cnt_1_16[1:0] - attribute \src "libresoc.v:35286.3-35300.6" + attribute \src "libresoc.v:35334.3-35348.6" wire width 2 $0\cnt_1_17[1:0] - attribute \src "libresoc.v:35301.3-35315.6" + attribute \src "libresoc.v:35349.3-35363.6" wire width 2 $0\cnt_1_18[1:0] - attribute \src "libresoc.v:35316.3-35330.6" + attribute \src "libresoc.v:35364.3-35378.6" wire width 2 $0\cnt_1_19[1:0] - attribute \src "libresoc.v:35241.3-35255.6" + attribute \src "libresoc.v:35289.3-35303.6" wire width 2 $0\cnt_1_1[1:0] - attribute \src "libresoc.v:35331.3-35345.6" + attribute \src "libresoc.v:35379.3-35393.6" wire width 2 $0\cnt_1_20[1:0] - attribute \src "libresoc.v:35346.3-35360.6" + attribute \src "libresoc.v:35394.3-35408.6" wire width 2 $0\cnt_1_21[1:0] - attribute \src "libresoc.v:35361.3-35375.6" + attribute \src "libresoc.v:35409.3-35423.6" wire width 2 $0\cnt_1_22[1:0] - attribute \src "libresoc.v:35376.3-35390.6" + attribute \src "libresoc.v:35424.3-35438.6" wire width 2 $0\cnt_1_23[1:0] - attribute \src "libresoc.v:35391.3-35405.6" + attribute \src "libresoc.v:35439.3-35453.6" wire width 2 $0\cnt_1_24[1:0] - attribute \src "libresoc.v:35421.3-35435.6" + attribute \src "libresoc.v:35469.3-35483.6" wire width 2 $0\cnt_1_25[1:0] - attribute \src "libresoc.v:35436.3-35450.6" + attribute \src "libresoc.v:35484.3-35498.6" wire width 2 $0\cnt_1_26[1:0] - attribute \src "libresoc.v:35451.3-35465.6" + attribute \src "libresoc.v:35499.3-35513.6" wire width 2 $0\cnt_1_27[1:0] - attribute \src "libresoc.v:35466.3-35480.6" + attribute \src "libresoc.v:35514.3-35528.6" wire width 2 $0\cnt_1_28[1:0] - attribute \src "libresoc.v:35481.3-35495.6" + attribute \src "libresoc.v:35529.3-35543.6" wire width 2 $0\cnt_1_29[1:0] - attribute \src "libresoc.v:35406.3-35420.6" + attribute \src "libresoc.v:35454.3-35468.6" wire width 2 $0\cnt_1_2[1:0] - attribute \src "libresoc.v:35496.3-35510.6" + attribute \src "libresoc.v:35544.3-35558.6" wire width 2 $0\cnt_1_30[1:0] - attribute \src "libresoc.v:35511.3-35525.6" + attribute \src "libresoc.v:35559.3-35573.6" wire width 2 $0\cnt_1_31[1:0] - attribute \src "libresoc.v:35646.3-35660.6" + attribute \src "libresoc.v:35694.3-35708.6" wire width 2 $0\cnt_1_3[1:0] - attribute \src "libresoc.v:36061.3-36075.6" + attribute \src "libresoc.v:36109.3-36123.6" wire width 2 $0\cnt_1_4[1:0] - attribute \src "libresoc.v:35091.3-35105.6" + attribute \src "libresoc.v:35139.3-35153.6" wire width 2 $0\cnt_1_5[1:0] - attribute \src "libresoc.v:35106.3-35120.6" + attribute \src "libresoc.v:35154.3-35168.6" wire width 2 $0\cnt_1_6[1:0] - attribute \src "libresoc.v:35121.3-35135.6" + attribute \src "libresoc.v:35169.3-35183.6" wire width 2 $0\cnt_1_7[1:0] - attribute \src "libresoc.v:35136.3-35150.6" + attribute \src "libresoc.v:35184.3-35198.6" wire width 2 $0\cnt_1_8[1:0] - attribute \src "libresoc.v:35151.3-35165.6" + attribute \src "libresoc.v:35199.3-35213.6" wire width 2 $0\cnt_1_9[1:0] - attribute \src "libresoc.v:35526.3-35545.6" + attribute \src "libresoc.v:35574.3-35593.6" wire width 3 $0\cnt_2_0[2:0] - attribute \src "libresoc.v:35626.3-35645.6" + attribute \src "libresoc.v:35674.3-35693.6" wire width 3 $0\cnt_2_10[2:0] - attribute \src "libresoc.v:35661.3-35680.6" + attribute \src "libresoc.v:35709.3-35728.6" wire width 3 $0\cnt_2_12[2:0] - attribute \src "libresoc.v:35681.3-35700.6" + attribute \src "libresoc.v:35729.3-35748.6" wire width 3 $0\cnt_2_14[2:0] - attribute \src "libresoc.v:35701.3-35720.6" + attribute \src "libresoc.v:35749.3-35768.6" wire width 3 $0\cnt_2_16[2:0] - attribute \src "libresoc.v:35721.3-35740.6" + attribute \src "libresoc.v:35769.3-35788.6" wire width 3 $0\cnt_2_18[2:0] - attribute \src "libresoc.v:35741.3-35760.6" + attribute \src "libresoc.v:35789.3-35808.6" wire width 3 $0\cnt_2_20[2:0] - attribute \src "libresoc.v:35761.3-35780.6" + attribute \src "libresoc.v:35809.3-35828.6" wire width 3 $0\cnt_2_22[2:0] - attribute \src "libresoc.v:35781.3-35800.6" + attribute \src "libresoc.v:35829.3-35848.6" wire width 3 $0\cnt_2_24[2:0] - attribute \src "libresoc.v:35801.3-35820.6" + attribute \src "libresoc.v:35849.3-35868.6" wire width 3 $0\cnt_2_26[2:0] - attribute \src "libresoc.v:35821.3-35840.6" + attribute \src "libresoc.v:35869.3-35888.6" wire width 3 $0\cnt_2_28[2:0] - attribute \src "libresoc.v:35546.3-35565.6" + attribute \src "libresoc.v:35594.3-35613.6" wire width 3 $0\cnt_2_2[2:0] - attribute \src "libresoc.v:35841.3-35860.6" + attribute \src "libresoc.v:35889.3-35908.6" wire width 3 $0\cnt_2_30[2:0] - attribute \src "libresoc.v:35566.3-35585.6" + attribute \src "libresoc.v:35614.3-35633.6" wire width 3 $0\cnt_2_4[2:0] - attribute \src "libresoc.v:35586.3-35605.6" + attribute \src "libresoc.v:35634.3-35653.6" wire width 3 $0\cnt_2_6[2:0] - attribute \src "libresoc.v:35606.3-35625.6" + attribute \src "libresoc.v:35654.3-35673.6" wire width 3 $0\cnt_2_8[2:0] - attribute \src "libresoc.v:35861.3-35880.6" + attribute \src "libresoc.v:35909.3-35928.6" wire width 4 $0\cnt_3_0[3:0] - attribute \src "libresoc.v:35961.3-35980.6" + attribute \src "libresoc.v:36009.3-36028.6" wire width 4 $0\cnt_3_10[3:0] - attribute \src "libresoc.v:35981.3-36000.6" + attribute \src "libresoc.v:36029.3-36048.6" wire width 4 $0\cnt_3_12[3:0] - attribute \src "libresoc.v:36001.3-36020.6" + attribute \src "libresoc.v:36049.3-36068.6" wire width 4 $0\cnt_3_14[3:0] - attribute \src "libresoc.v:35881.3-35900.6" + attribute \src "libresoc.v:35929.3-35948.6" wire width 4 $0\cnt_3_2[3:0] - attribute \src "libresoc.v:35901.3-35920.6" + attribute \src "libresoc.v:35949.3-35968.6" wire width 4 $0\cnt_3_4[3:0] - attribute \src "libresoc.v:35921.3-35940.6" + attribute \src "libresoc.v:35969.3-35988.6" wire width 4 $0\cnt_3_6[3:0] - attribute \src "libresoc.v:35941.3-35960.6" + attribute \src "libresoc.v:35989.3-36008.6" wire width 4 $0\cnt_3_8[3:0] - attribute \src "libresoc.v:36021.3-36040.6" + attribute \src "libresoc.v:36069.3-36088.6" wire width 5 $0\cnt_4_0[4:0] - attribute \src "libresoc.v:36041.3-36060.6" + attribute \src "libresoc.v:36089.3-36108.6" wire width 5 $0\cnt_4_2[4:0] - attribute \src "libresoc.v:36076.3-36095.6" + attribute \src "libresoc.v:36124.3-36143.6" wire width 5 $0\cnt_4_4[4:0] - attribute \src "libresoc.v:36096.3-36115.6" + attribute \src "libresoc.v:36144.3-36163.6" wire width 5 $0\cnt_4_6[4:0] - attribute \src "libresoc.v:36116.3-36135.6" + attribute \src "libresoc.v:36164.3-36183.6" wire width 6 $0\cnt_5_0[5:0] - attribute \src "libresoc.v:36136.3-36155.6" + attribute \src "libresoc.v:36184.3-36203.6" wire width 6 $0\cnt_5_2[5:0] - attribute \src "libresoc.v:36156.3-36175.6" + attribute \src "libresoc.v:36204.3-36223.6" wire width 7 $0\cnt_6_0[6:0] - attribute \src "libresoc.v:34602.7-34602.20" + attribute \src "libresoc.v:34650.7-34650.20" wire $0\initial[0:0] - attribute \src "libresoc.v:35076.3-35090.6" + attribute \src "libresoc.v:35124.3-35138.6" wire width 2 $1\cnt_1_0[1:0] - attribute \src "libresoc.v:35166.3-35180.6" + attribute \src "libresoc.v:35214.3-35228.6" wire width 2 $1\cnt_1_10[1:0] - attribute \src "libresoc.v:35181.3-35195.6" + attribute \src "libresoc.v:35229.3-35243.6" wire width 2 $1\cnt_1_11[1:0] - attribute \src "libresoc.v:35196.3-35210.6" + attribute \src "libresoc.v:35244.3-35258.6" wire width 2 $1\cnt_1_12[1:0] - attribute \src "libresoc.v:35211.3-35225.6" + attribute \src "libresoc.v:35259.3-35273.6" wire width 2 $1\cnt_1_13[1:0] - attribute \src "libresoc.v:35226.3-35240.6" + attribute \src "libresoc.v:35274.3-35288.6" wire width 2 $1\cnt_1_14[1:0] - attribute \src "libresoc.v:35256.3-35270.6" + attribute \src "libresoc.v:35304.3-35318.6" wire width 2 $1\cnt_1_15[1:0] - attribute \src "libresoc.v:35271.3-35285.6" + attribute \src "libresoc.v:35319.3-35333.6" wire width 2 $1\cnt_1_16[1:0] - attribute \src "libresoc.v:35286.3-35300.6" + attribute \src "libresoc.v:35334.3-35348.6" wire width 2 $1\cnt_1_17[1:0] - attribute \src "libresoc.v:35301.3-35315.6" + attribute \src "libresoc.v:35349.3-35363.6" wire width 2 $1\cnt_1_18[1:0] - attribute \src "libresoc.v:35316.3-35330.6" + attribute \src "libresoc.v:35364.3-35378.6" wire width 2 $1\cnt_1_19[1:0] - attribute \src "libresoc.v:35241.3-35255.6" + attribute \src "libresoc.v:35289.3-35303.6" wire width 2 $1\cnt_1_1[1:0] - attribute \src "libresoc.v:35331.3-35345.6" + attribute \src "libresoc.v:35379.3-35393.6" wire width 2 $1\cnt_1_20[1:0] - attribute \src "libresoc.v:35346.3-35360.6" + attribute \src "libresoc.v:35394.3-35408.6" wire width 2 $1\cnt_1_21[1:0] - attribute \src "libresoc.v:35361.3-35375.6" + attribute \src "libresoc.v:35409.3-35423.6" wire width 2 $1\cnt_1_22[1:0] - attribute \src "libresoc.v:35376.3-35390.6" + attribute \src "libresoc.v:35424.3-35438.6" wire width 2 $1\cnt_1_23[1:0] - attribute \src "libresoc.v:35391.3-35405.6" + attribute \src "libresoc.v:35439.3-35453.6" wire width 2 $1\cnt_1_24[1:0] - attribute \src "libresoc.v:35421.3-35435.6" + attribute \src "libresoc.v:35469.3-35483.6" wire width 2 $1\cnt_1_25[1:0] - attribute \src "libresoc.v:35436.3-35450.6" + attribute \src "libresoc.v:35484.3-35498.6" wire width 2 $1\cnt_1_26[1:0] - attribute \src "libresoc.v:35451.3-35465.6" + attribute \src "libresoc.v:35499.3-35513.6" wire width 2 $1\cnt_1_27[1:0] - attribute \src "libresoc.v:35466.3-35480.6" + attribute \src "libresoc.v:35514.3-35528.6" wire width 2 $1\cnt_1_28[1:0] - attribute \src "libresoc.v:35481.3-35495.6" + attribute \src "libresoc.v:35529.3-35543.6" wire width 2 $1\cnt_1_29[1:0] - attribute \src "libresoc.v:35406.3-35420.6" + attribute \src "libresoc.v:35454.3-35468.6" wire width 2 $1\cnt_1_2[1:0] - attribute \src "libresoc.v:35496.3-35510.6" + attribute \src "libresoc.v:35544.3-35558.6" wire width 2 $1\cnt_1_30[1:0] - attribute \src "libresoc.v:35511.3-35525.6" + attribute \src "libresoc.v:35559.3-35573.6" wire width 2 $1\cnt_1_31[1:0] - attribute \src "libresoc.v:35646.3-35660.6" + attribute \src "libresoc.v:35694.3-35708.6" wire width 2 $1\cnt_1_3[1:0] - attribute \src "libresoc.v:36061.3-36075.6" + attribute \src "libresoc.v:36109.3-36123.6" wire width 2 $1\cnt_1_4[1:0] - attribute \src "libresoc.v:35091.3-35105.6" + attribute \src "libresoc.v:35139.3-35153.6" wire width 2 $1\cnt_1_5[1:0] - attribute \src "libresoc.v:35106.3-35120.6" + attribute \src "libresoc.v:35154.3-35168.6" wire width 2 $1\cnt_1_6[1:0] - attribute \src "libresoc.v:35121.3-35135.6" + attribute \src "libresoc.v:35169.3-35183.6" wire width 2 $1\cnt_1_7[1:0] - attribute \src "libresoc.v:35136.3-35150.6" + attribute \src "libresoc.v:35184.3-35198.6" wire width 2 $1\cnt_1_8[1:0] - attribute \src "libresoc.v:35151.3-35165.6" + attribute \src "libresoc.v:35199.3-35213.6" wire width 2 $1\cnt_1_9[1:0] - attribute \src "libresoc.v:35526.3-35545.6" + attribute \src "libresoc.v:35574.3-35593.6" wire width 3 $1\cnt_2_0[2:0] - attribute \src "libresoc.v:35626.3-35645.6" + attribute \src "libresoc.v:35674.3-35693.6" wire width 3 $1\cnt_2_10[2:0] - attribute \src "libresoc.v:35661.3-35680.6" + attribute \src "libresoc.v:35709.3-35728.6" wire width 3 $1\cnt_2_12[2:0] - attribute \src "libresoc.v:35681.3-35700.6" + attribute \src "libresoc.v:35729.3-35748.6" wire width 3 $1\cnt_2_14[2:0] - attribute \src "libresoc.v:35701.3-35720.6" + attribute \src "libresoc.v:35749.3-35768.6" wire width 3 $1\cnt_2_16[2:0] - attribute \src "libresoc.v:35721.3-35740.6" + attribute \src "libresoc.v:35769.3-35788.6" wire width 3 $1\cnt_2_18[2:0] - attribute \src "libresoc.v:35741.3-35760.6" + attribute \src "libresoc.v:35789.3-35808.6" wire width 3 $1\cnt_2_20[2:0] - attribute \src "libresoc.v:35761.3-35780.6" + attribute \src "libresoc.v:35809.3-35828.6" wire width 3 $1\cnt_2_22[2:0] - attribute \src "libresoc.v:35781.3-35800.6" + attribute \src "libresoc.v:35829.3-35848.6" wire width 3 $1\cnt_2_24[2:0] - attribute \src "libresoc.v:35801.3-35820.6" + attribute \src "libresoc.v:35849.3-35868.6" wire width 3 $1\cnt_2_26[2:0] - attribute \src "libresoc.v:35821.3-35840.6" + attribute \src "libresoc.v:35869.3-35888.6" wire width 3 $1\cnt_2_28[2:0] - attribute \src "libresoc.v:35546.3-35565.6" + attribute \src "libresoc.v:35594.3-35613.6" wire width 3 $1\cnt_2_2[2:0] - attribute \src "libresoc.v:35841.3-35860.6" + attribute \src "libresoc.v:35889.3-35908.6" wire width 3 $1\cnt_2_30[2:0] - attribute \src "libresoc.v:35566.3-35585.6" + attribute \src "libresoc.v:35614.3-35633.6" wire width 3 $1\cnt_2_4[2:0] - attribute \src "libresoc.v:35586.3-35605.6" + attribute \src "libresoc.v:35634.3-35653.6" wire width 3 $1\cnt_2_6[2:0] - attribute \src "libresoc.v:35606.3-35625.6" + attribute \src "libresoc.v:35654.3-35673.6" wire width 3 $1\cnt_2_8[2:0] - attribute \src "libresoc.v:35861.3-35880.6" + attribute \src "libresoc.v:35909.3-35928.6" wire width 4 $1\cnt_3_0[3:0] - attribute \src "libresoc.v:35961.3-35980.6" + attribute \src "libresoc.v:36009.3-36028.6" wire width 4 $1\cnt_3_10[3:0] - attribute \src "libresoc.v:35981.3-36000.6" + attribute \src "libresoc.v:36029.3-36048.6" wire width 4 $1\cnt_3_12[3:0] - attribute \src "libresoc.v:36001.3-36020.6" + attribute \src "libresoc.v:36049.3-36068.6" wire width 4 $1\cnt_3_14[3:0] - attribute \src "libresoc.v:35881.3-35900.6" + attribute \src "libresoc.v:35929.3-35948.6" wire width 4 $1\cnt_3_2[3:0] - attribute \src "libresoc.v:35901.3-35920.6" + attribute \src "libresoc.v:35949.3-35968.6" wire width 4 $1\cnt_3_4[3:0] - attribute \src "libresoc.v:35921.3-35940.6" + attribute \src "libresoc.v:35969.3-35988.6" wire width 4 $1\cnt_3_6[3:0] - attribute \src "libresoc.v:35941.3-35960.6" + attribute \src "libresoc.v:35989.3-36008.6" wire width 4 $1\cnt_3_8[3:0] - attribute \src "libresoc.v:36021.3-36040.6" + attribute \src "libresoc.v:36069.3-36088.6" wire width 5 $1\cnt_4_0[4:0] - attribute \src "libresoc.v:36041.3-36060.6" + attribute \src "libresoc.v:36089.3-36108.6" wire width 5 $1\cnt_4_2[4:0] - attribute \src "libresoc.v:36076.3-36095.6" + attribute \src "libresoc.v:36124.3-36143.6" wire width 5 $1\cnt_4_4[4:0] - attribute \src "libresoc.v:36096.3-36115.6" + attribute \src "libresoc.v:36144.3-36163.6" wire width 5 $1\cnt_4_6[4:0] - attribute \src "libresoc.v:36116.3-36135.6" + attribute \src "libresoc.v:36164.3-36183.6" wire width 6 $1\cnt_5_0[5:0] - attribute \src "libresoc.v:36136.3-36155.6" + attribute \src "libresoc.v:36184.3-36203.6" wire width 6 $1\cnt_5_2[5:0] - attribute \src "libresoc.v:36156.3-36175.6" + attribute \src "libresoc.v:36204.3-36223.6" wire width 7 $1\cnt_6_0[6:0] - attribute \src "libresoc.v:35526.3-35545.6" + attribute \src "libresoc.v:35574.3-35593.6" wire width 3 $2\cnt_2_0[2:0] - attribute \src "libresoc.v:35626.3-35645.6" + attribute \src "libresoc.v:35674.3-35693.6" wire width 3 $2\cnt_2_10[2:0] - attribute \src "libresoc.v:35661.3-35680.6" + attribute \src "libresoc.v:35709.3-35728.6" wire width 3 $2\cnt_2_12[2:0] - attribute \src "libresoc.v:35681.3-35700.6" + attribute \src "libresoc.v:35729.3-35748.6" wire width 3 $2\cnt_2_14[2:0] - attribute \src "libresoc.v:35701.3-35720.6" + attribute \src "libresoc.v:35749.3-35768.6" wire width 3 $2\cnt_2_16[2:0] - attribute \src "libresoc.v:35721.3-35740.6" + attribute \src "libresoc.v:35769.3-35788.6" wire width 3 $2\cnt_2_18[2:0] - attribute \src "libresoc.v:35741.3-35760.6" + attribute \src "libresoc.v:35789.3-35808.6" wire width 3 $2\cnt_2_20[2:0] - attribute \src "libresoc.v:35761.3-35780.6" + attribute \src "libresoc.v:35809.3-35828.6" wire width 3 $2\cnt_2_22[2:0] - attribute \src "libresoc.v:35781.3-35800.6" + attribute \src "libresoc.v:35829.3-35848.6" wire width 3 $2\cnt_2_24[2:0] - attribute \src "libresoc.v:35801.3-35820.6" + attribute \src "libresoc.v:35849.3-35868.6" wire width 3 $2\cnt_2_26[2:0] - attribute \src "libresoc.v:35821.3-35840.6" + attribute \src "libresoc.v:35869.3-35888.6" wire width 3 $2\cnt_2_28[2:0] - attribute \src "libresoc.v:35546.3-35565.6" + attribute \src "libresoc.v:35594.3-35613.6" wire width 3 $2\cnt_2_2[2:0] - attribute \src "libresoc.v:35841.3-35860.6" + attribute \src "libresoc.v:35889.3-35908.6" wire width 3 $2\cnt_2_30[2:0] - attribute \src "libresoc.v:35566.3-35585.6" + attribute \src "libresoc.v:35614.3-35633.6" wire width 3 $2\cnt_2_4[2:0] - attribute \src "libresoc.v:35586.3-35605.6" + attribute \src "libresoc.v:35634.3-35653.6" wire width 3 $2\cnt_2_6[2:0] - attribute \src "libresoc.v:35606.3-35625.6" + attribute \src "libresoc.v:35654.3-35673.6" wire width 3 $2\cnt_2_8[2:0] - attribute \src "libresoc.v:35861.3-35880.6" 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attribute \src "libresoc.v:35120.18-35120.103" + wire $eq$libresoc.v:35120$1438_Y + attribute \src "libresoc.v:35121.18-35121.103" + wire $eq$libresoc.v:35121$1439_Y + attribute \src "libresoc.v:35123.18-35123.102" + wire $eq$libresoc.v:35123$1441_Y + attribute \src "libresoc.v:35033.19-35033.109" + wire width 4 $pos$libresoc.v:35033$1351_Y + attribute \src "libresoc.v:35036.19-35036.109" + wire width 4 $pos$libresoc.v:35036$1354_Y + attribute \src "libresoc.v:35039.19-35039.109" + wire width 4 $pos$libresoc.v:35039$1357_Y + attribute \src "libresoc.v:35042.18-35042.106" + wire width 3 $pos$libresoc.v:35042$1360_Y + attribute \src "libresoc.v:35043.19-35043.110" + wire width 4 $pos$libresoc.v:35043$1361_Y + attribute \src "libresoc.v:35046.19-35046.110" + wire width 4 $pos$libresoc.v:35046$1364_Y + attribute \src "libresoc.v:35049.19-35049.110" + wire width 4 $pos$libresoc.v:35049$1367_Y + attribute \src "libresoc.v:35052.19-35052.110" + wire width 4 $pos$libresoc.v:35052$1370_Y + attribute \src "libresoc.v:35056.19-35056.110" + wire width 4 $pos$libresoc.v:35056$1374_Y + attribute \src "libresoc.v:35059.19-35059.109" + wire width 5 $pos$libresoc.v:35059$1377_Y + attribute \src "libresoc.v:35062.19-35062.109" + wire width 5 $pos$libresoc.v:35062$1380_Y + attribute \src "libresoc.v:35066.19-35066.109" + wire width 5 $pos$libresoc.v:35066$1384_Y + attribute \src "libresoc.v:35069.19-35069.110" + wire width 5 $pos$libresoc.v:35069$1387_Y + attribute \src "libresoc.v:35072.19-35072.109" + wire width 6 $pos$libresoc.v:35072$1390_Y + attribute \src "libresoc.v:35075.18-35075.106" + wire width 3 $pos$libresoc.v:35075$1393_Y + attribute \src "libresoc.v:35076.19-35076.109" + wire width 6 $pos$libresoc.v:35076$1394_Y + attribute \src "libresoc.v:35079.19-35079.109" + wire width 7 $pos$libresoc.v:35079$1397_Y + attribute \src "libresoc.v:35083.18-35083.106" + wire width 3 $pos$libresoc.v:35083$1401_Y + attribute \src "libresoc.v:35086.18-35086.106" + wire width 3 $pos$libresoc.v:35086$1404_Y + attribute \src "libresoc.v:35089.18-35089.107" + wire width 3 $pos$libresoc.v:35089$1407_Y + attribute \src "libresoc.v:35093.18-35093.107" + wire width 3 $pos$libresoc.v:35093$1411_Y + attribute \src "libresoc.v:35096.18-35096.107" + wire width 3 $pos$libresoc.v:35096$1414_Y + attribute \src "libresoc.v:35099.18-35099.107" + wire width 3 $pos$libresoc.v:35099$1417_Y + attribute \src "libresoc.v:35102.17-35102.105" + wire width 3 $pos$libresoc.v:35102$1420_Y + attribute \src "libresoc.v:35103.18-35103.107" + wire width 3 $pos$libresoc.v:35103$1421_Y + attribute \src "libresoc.v:35106.18-35106.107" + wire width 3 $pos$libresoc.v:35106$1424_Y + attribute \src "libresoc.v:35109.18-35109.107" + wire width 3 $pos$libresoc.v:35109$1427_Y + attribute \src "libresoc.v:35112.18-35112.107" + wire width 3 $pos$libresoc.v:35112$1430_Y + attribute \src "libresoc.v:35116.18-35116.107" + wire width 3 $pos$libresoc.v:35116$1434_Y + attribute \src "libresoc.v:35119.18-35119.107" + wire width 3 $pos$libresoc.v:35119$1437_Y + attribute \src "libresoc.v:35122.18-35122.107" + wire width 3 $pos$libresoc.v:35122$1440_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" @@ -53816,7 +53852,7 @@ module \clz wire width 6 \cnt_5_2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" wire width 7 \cnt_6_0 - attribute \src "libresoc.v:34602.7-34602.15" + attribute \src "libresoc.v:34650.7-34650.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" wire width 7 output 1 \lz @@ -53887,7 +53923,7 @@ module \clz attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:16" wire width 64 input 2 \sig_in attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34983$1349 + cell $eq $eq$libresoc.v:35031$1349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53895,10 +53931,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_2 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:34983$1349_Y + connect \Y $eq$libresoc.v:35031$1349_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34984$1350 + cell $eq $eq$libresoc.v:35032$1350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53906,10 +53942,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_0 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34984$1350_Y + connect \Y $eq$libresoc.v:35032$1350_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:34986$1352 + cell $eq $eq$libresoc.v:35034$1352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53917,10 +53953,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_6 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34986$1352_Y + connect \Y $eq$libresoc.v:35034$1352_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34987$1353 + cell $eq $eq$libresoc.v:35035$1353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53928,10 +53964,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_4 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34987$1353_Y + connect \Y $eq$libresoc.v:35035$1353_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:34989$1355 + cell $eq $eq$libresoc.v:35037$1355 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53939,10 +53975,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_10 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34989$1355_Y + connect \Y $eq$libresoc.v:35037$1355_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34990$1356 + cell $eq $eq$libresoc.v:35038$1356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53950,10 +53986,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_8 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34990$1356_Y + connect \Y $eq$libresoc.v:35038$1356_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:34992$1358 + cell $eq $eq$libresoc.v:35040$1358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53961,10 +53997,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_14 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34992$1358_Y + connect \Y $eq$libresoc.v:35040$1358_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34993$1359 + cell $eq $eq$libresoc.v:35041$1359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53972,10 +54008,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_12 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34993$1359_Y + connect \Y $eq$libresoc.v:35041$1359_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:34996$1362 + cell $eq $eq$libresoc.v:35044$1362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53983,10 +54019,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_18 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34996$1362_Y + connect \Y $eq$libresoc.v:35044$1362_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:34997$1363 + cell $eq $eq$libresoc.v:35045$1363 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -53994,10 +54030,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_16 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34997$1363_Y + connect \Y $eq$libresoc.v:35045$1363_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:34999$1365 + cell $eq $eq$libresoc.v:35047$1365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54005,10 +54041,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_22 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:34999$1365_Y + connect \Y $eq$libresoc.v:35047$1365_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35000$1366 + cell $eq $eq$libresoc.v:35048$1366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54016,10 +54052,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_20 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:35000$1366_Y + connect \Y $eq$libresoc.v:35048$1366_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35002$1368 + cell $eq $eq$libresoc.v:35050$1368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54027,10 +54063,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_26 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:35002$1368_Y + connect \Y $eq$libresoc.v:35050$1368_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35003$1369 + cell $eq $eq$libresoc.v:35051$1369 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54038,10 +54074,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_24 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:35003$1369_Y + connect \Y $eq$libresoc.v:35051$1369_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35005$1371 + cell $eq $eq$libresoc.v:35053$1371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54049,10 +54085,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_5 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35005$1371_Y + connect \Y $eq$libresoc.v:35053$1371_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35006$1372 + cell $eq $eq$libresoc.v:35054$1372 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54060,10 +54096,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_30 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:35006$1372_Y + connect \Y $eq$libresoc.v:35054$1372_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35007$1373 + cell $eq $eq$libresoc.v:35055$1373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54071,10 +54107,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_28 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:35007$1373_Y + connect \Y $eq$libresoc.v:35055$1373_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35009$1375 + cell $eq $eq$libresoc.v:35057$1375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54082,10 +54118,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_3_2 [3] connect \B 1'1 - connect \Y $eq$libresoc.v:35009$1375_Y + connect \Y $eq$libresoc.v:35057$1375_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35010$1376 + cell $eq $eq$libresoc.v:35058$1376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54093,10 +54129,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_3_0 [3] connect \B 1'1 - connect \Y $eq$libresoc.v:35010$1376_Y + connect \Y $eq$libresoc.v:35058$1376_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35012$1378 + cell $eq $eq$libresoc.v:35060$1378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54104,10 +54140,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_3_6 [3] connect \B 1'1 - connect \Y $eq$libresoc.v:35012$1378_Y + connect \Y $eq$libresoc.v:35060$1378_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35013$1379 + cell $eq $eq$libresoc.v:35061$1379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54115,10 +54151,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_3_4 [3] connect \B 1'1 - connect \Y $eq$libresoc.v:35013$1379_Y + connect \Y $eq$libresoc.v:35061$1379_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35015$1381 + cell $eq $eq$libresoc.v:35063$1381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54126,10 +54162,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_3_10 [3] connect \B 1'1 - connect \Y $eq$libresoc.v:35015$1381_Y + connect \Y $eq$libresoc.v:35063$1381_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35016$1382 + cell $eq $eq$libresoc.v:35064$1382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54137,10 +54173,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_4 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35016$1382_Y + connect \Y $eq$libresoc.v:35064$1382_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35017$1383 + cell $eq $eq$libresoc.v:35065$1383 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54148,10 +54184,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_3_8 [3] connect \B 1'1 - connect \Y $eq$libresoc.v:35017$1383_Y + connect \Y $eq$libresoc.v:35065$1383_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35019$1385 + cell $eq $eq$libresoc.v:35067$1385 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54159,10 +54195,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_3_14 [3] connect \B 1'1 - connect \Y $eq$libresoc.v:35019$1385_Y + connect \Y $eq$libresoc.v:35067$1385_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35020$1386 + cell $eq $eq$libresoc.v:35068$1386 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54170,10 +54206,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_3_12 [3] connect \B 1'1 - connect \Y $eq$libresoc.v:35020$1386_Y + connect \Y $eq$libresoc.v:35068$1386_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35022$1388 + cell $eq $eq$libresoc.v:35070$1388 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54181,10 +54217,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_4_2 [4] connect \B 1'1 - connect \Y $eq$libresoc.v:35022$1388_Y + connect \Y $eq$libresoc.v:35070$1388_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35023$1389 + cell $eq $eq$libresoc.v:35071$1389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54192,10 +54228,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_4_0 [4] connect \B 1'1 - connect \Y $eq$libresoc.v:35023$1389_Y + connect \Y $eq$libresoc.v:35071$1389_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35025$1391 + cell $eq $eq$libresoc.v:35073$1391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54203,10 +54239,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_4_6 [4] connect \B 1'1 - connect \Y $eq$libresoc.v:35025$1391_Y + connect \Y $eq$libresoc.v:35073$1391_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35026$1392 + cell $eq $eq$libresoc.v:35074$1392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54214,10 +54250,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_4_4 [4] connect \B 1'1 - connect \Y $eq$libresoc.v:35026$1392_Y + connect \Y $eq$libresoc.v:35074$1392_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35029$1395 + cell $eq $eq$libresoc.v:35077$1395 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54225,10 +54261,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_5_2 [5] connect \B 1'1 - connect \Y $eq$libresoc.v:35029$1395_Y + connect \Y $eq$libresoc.v:35077$1395_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35030$1396 + cell $eq $eq$libresoc.v:35078$1396 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54236,10 +54272,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_5_0 [5] connect \B 1'1 - connect \Y $eq$libresoc.v:35030$1396_Y + connect \Y $eq$libresoc.v:35078$1396_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35032$1398 + cell $eq $eq$libresoc.v:35080$1398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54247,10 +54283,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_1 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35032$1398_Y + connect \Y $eq$libresoc.v:35080$1398_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35033$1399 + cell $eq $eq$libresoc.v:35081$1399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54258,10 +54294,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_7 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35033$1399_Y + connect \Y $eq$libresoc.v:35081$1399_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35034$1400 + cell $eq $eq$libresoc.v:35082$1400 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54269,10 +54305,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_6 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35034$1400_Y + connect \Y $eq$libresoc.v:35082$1400_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35036$1402 + cell $eq $eq$libresoc.v:35084$1402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54280,10 +54316,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_9 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35036$1402_Y + connect \Y $eq$libresoc.v:35084$1402_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35037$1403 + cell $eq $eq$libresoc.v:35085$1403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54291,10 +54327,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_8 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35037$1403_Y + connect \Y $eq$libresoc.v:35085$1403_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35039$1405 + cell $eq $eq$libresoc.v:35087$1405 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54302,10 +54338,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_11 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35039$1405_Y + connect \Y $eq$libresoc.v:35087$1405_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35040$1406 + cell $eq $eq$libresoc.v:35088$1406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54313,10 +54349,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_10 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35040$1406_Y + connect \Y $eq$libresoc.v:35088$1406_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35042$1408 + cell $eq $eq$libresoc.v:35090$1408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54324,10 +54360,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_13 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35042$1408_Y + connect \Y $eq$libresoc.v:35090$1408_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35043$1409 + cell $eq $eq$libresoc.v:35091$1409 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54335,10 +54371,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_0 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35043$1409_Y + connect \Y $eq$libresoc.v:35091$1409_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35044$1410 + cell $eq $eq$libresoc.v:35092$1410 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54346,10 +54382,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_12 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35044$1410_Y + connect \Y $eq$libresoc.v:35092$1410_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35046$1412 + cell $eq $eq$libresoc.v:35094$1412 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54357,10 +54393,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_15 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35046$1412_Y + connect \Y $eq$libresoc.v:35094$1412_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35047$1413 + cell $eq $eq$libresoc.v:35095$1413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54368,10 +54404,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_14 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35047$1413_Y + connect \Y $eq$libresoc.v:35095$1413_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35049$1415 + cell $eq $eq$libresoc.v:35097$1415 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54379,10 +54415,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_17 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35049$1415_Y + connect \Y $eq$libresoc.v:35097$1415_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35050$1416 + cell $eq $eq$libresoc.v:35098$1416 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54390,10 +54426,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_16 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35050$1416_Y + connect \Y $eq$libresoc.v:35098$1416_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35052$1418 + cell $eq $eq$libresoc.v:35100$1418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54401,10 +54437,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_19 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35052$1418_Y + connect \Y $eq$libresoc.v:35100$1418_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35053$1419 + cell $eq $eq$libresoc.v:35101$1419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54412,10 +54448,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_18 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35053$1419_Y + connect \Y $eq$libresoc.v:35101$1419_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35056$1422 + cell $eq $eq$libresoc.v:35104$1422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54423,10 +54459,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_21 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35056$1422_Y + connect \Y $eq$libresoc.v:35104$1422_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35057$1423 + cell $eq $eq$libresoc.v:35105$1423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54434,10 +54470,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_20 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35057$1423_Y + connect \Y $eq$libresoc.v:35105$1423_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35059$1425 + cell $eq $eq$libresoc.v:35107$1425 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54445,10 +54481,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_23 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35059$1425_Y + connect \Y $eq$libresoc.v:35107$1425_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35060$1426 + cell $eq $eq$libresoc.v:35108$1426 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54456,10 +54492,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_22 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35060$1426_Y + connect \Y $eq$libresoc.v:35108$1426_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35062$1428 + cell $eq $eq$libresoc.v:35110$1428 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54467,10 +54503,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_25 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35062$1428_Y + connect \Y $eq$libresoc.v:35110$1428_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35063$1429 + cell $eq $eq$libresoc.v:35111$1429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54478,10 +54514,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_24 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35063$1429_Y + connect \Y $eq$libresoc.v:35111$1429_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35065$1431 + cell $eq $eq$libresoc.v:35113$1431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54489,10 +54525,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_3 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35065$1431_Y + connect \Y $eq$libresoc.v:35113$1431_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35066$1432 + cell $eq $eq$libresoc.v:35114$1432 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54500,10 +54536,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_27 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35066$1432_Y + connect \Y $eq$libresoc.v:35114$1432_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35067$1433 + cell $eq $eq$libresoc.v:35115$1433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54511,10 +54547,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_26 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35067$1433_Y + connect \Y $eq$libresoc.v:35115$1433_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35069$1435 + cell $eq $eq$libresoc.v:35117$1435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54522,10 +54558,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_29 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35069$1435_Y + connect \Y $eq$libresoc.v:35117$1435_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35070$1436 + cell $eq $eq$libresoc.v:35118$1436 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54533,10 +54569,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_28 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35070$1436_Y + connect \Y $eq$libresoc.v:35118$1436_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35072$1438 + cell $eq $eq$libresoc.v:35120$1438 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54544,10 +54580,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_31 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35072$1438_Y + connect \Y $eq$libresoc.v:35120$1438_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:61" - cell $eq $eq$libresoc.v:35073$1439 + cell $eq $eq$libresoc.v:35121$1439 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54555,10 +54591,10 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_1_30 [1] connect \B 1'1 - connect \Y $eq$libresoc.v:35073$1439_Y + connect \Y $eq$libresoc.v:35121$1439_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - cell $eq $eq$libresoc.v:35075$1441 + cell $eq $eq$libresoc.v:35123$1441 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -54566,271 +54602,271 @@ module \clz parameter \Y_WIDTH 1 connect \A \cnt_2_2 [2] connect \B 1'1 - connect \Y $eq$libresoc.v:35075$1441_Y + connect \Y $eq$libresoc.v:35123$1441_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34985$1351 + cell $pos $pos$libresoc.v:35033$1351 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_0 [1:0] } - connect \Y $pos$libresoc.v:34985$1351_Y + connect \Y $pos$libresoc.v:35033$1351_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34988$1354 + cell $pos $pos$libresoc.v:35036$1354 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_4 [1:0] } - connect \Y $pos$libresoc.v:34988$1354_Y + connect \Y $pos$libresoc.v:35036$1354_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34991$1357 + cell $pos $pos$libresoc.v:35039$1357 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_8 [1:0] } - connect \Y $pos$libresoc.v:34991$1357_Y + connect \Y $pos$libresoc.v:35039$1357_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34994$1360 + cell $pos $pos$libresoc.v:35042$1360 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_2 [0] } - connect \Y $pos$libresoc.v:34994$1360_Y + connect \Y $pos$libresoc.v:35042$1360_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34995$1361 + cell $pos $pos$libresoc.v:35043$1361 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_12 [1:0] } - connect \Y $pos$libresoc.v:34995$1361_Y + connect \Y $pos$libresoc.v:35043$1361_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:34998$1364 + cell $pos $pos$libresoc.v:35046$1364 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_16 [1:0] } - connect \Y $pos$libresoc.v:34998$1364_Y + connect \Y $pos$libresoc.v:35046$1364_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35001$1367 + cell $pos $pos$libresoc.v:35049$1367 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_20 [1:0] } - connect \Y $pos$libresoc.v:35001$1367_Y + connect \Y $pos$libresoc.v:35049$1367_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35004$1370 + cell $pos $pos$libresoc.v:35052$1370 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_24 [1:0] } - connect \Y $pos$libresoc.v:35004$1370_Y + connect \Y $pos$libresoc.v:35052$1370_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35008$1374 + cell $pos $pos$libresoc.v:35056$1374 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A { 2'01 \cnt_2_28 [1:0] } - connect \Y $pos$libresoc.v:35008$1374_Y + connect \Y $pos$libresoc.v:35056$1374_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35011$1377 + cell $pos $pos$libresoc.v:35059$1377 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A { 2'01 \cnt_3_0 [2:0] } - connect \Y $pos$libresoc.v:35011$1377_Y + connect \Y $pos$libresoc.v:35059$1377_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35014$1380 + cell $pos $pos$libresoc.v:35062$1380 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A { 2'01 \cnt_3_4 [2:0] } - connect \Y $pos$libresoc.v:35014$1380_Y + connect \Y $pos$libresoc.v:35062$1380_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35018$1384 + cell $pos $pos$libresoc.v:35066$1384 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A { 2'01 \cnt_3_8 [2:0] } - connect \Y $pos$libresoc.v:35018$1384_Y + connect \Y $pos$libresoc.v:35066$1384_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35021$1387 + cell $pos $pos$libresoc.v:35069$1387 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A { 2'01 \cnt_3_12 [2:0] } - connect \Y $pos$libresoc.v:35021$1387_Y + connect \Y $pos$libresoc.v:35069$1387_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35024$1390 + cell $pos $pos$libresoc.v:35072$1390 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A { 2'01 \cnt_4_0 [3:0] } - connect \Y $pos$libresoc.v:35024$1390_Y + connect \Y $pos$libresoc.v:35072$1390_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35027$1393 + cell $pos $pos$libresoc.v:35075$1393 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_4 [0] } - connect \Y $pos$libresoc.v:35027$1393_Y + connect \Y $pos$libresoc.v:35075$1393_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35028$1394 + cell $pos $pos$libresoc.v:35076$1394 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A { 2'01 \cnt_4_4 [3:0] } - connect \Y $pos$libresoc.v:35028$1394_Y + connect \Y $pos$libresoc.v:35076$1394_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35031$1397 + cell $pos $pos$libresoc.v:35079$1397 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 connect \A { 2'01 \cnt_5_0 [4:0] } - connect \Y $pos$libresoc.v:35031$1397_Y + connect \Y $pos$libresoc.v:35079$1397_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35035$1401 + cell $pos $pos$libresoc.v:35083$1401 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_6 [0] } - connect \Y $pos$libresoc.v:35035$1401_Y + connect \Y $pos$libresoc.v:35083$1401_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35038$1404 + cell $pos $pos$libresoc.v:35086$1404 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_8 [0] } - connect \Y $pos$libresoc.v:35038$1404_Y + connect \Y $pos$libresoc.v:35086$1404_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35041$1407 + cell $pos $pos$libresoc.v:35089$1407 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_10 [0] } - connect \Y $pos$libresoc.v:35041$1407_Y + connect \Y $pos$libresoc.v:35089$1407_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35045$1411 + cell $pos $pos$libresoc.v:35093$1411 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_12 [0] } - connect \Y $pos$libresoc.v:35045$1411_Y + connect \Y $pos$libresoc.v:35093$1411_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35048$1414 + cell $pos $pos$libresoc.v:35096$1414 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_14 [0] } - connect \Y $pos$libresoc.v:35048$1414_Y + connect \Y $pos$libresoc.v:35096$1414_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35051$1417 + cell $pos $pos$libresoc.v:35099$1417 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_16 [0] } - connect \Y $pos$libresoc.v:35051$1417_Y + connect \Y $pos$libresoc.v:35099$1417_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35054$1420 + cell $pos $pos$libresoc.v:35102$1420 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_0 [0] } - connect \Y $pos$libresoc.v:35054$1420_Y + connect \Y $pos$libresoc.v:35102$1420_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35055$1421 + cell $pos $pos$libresoc.v:35103$1421 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_18 [0] } - connect \Y $pos$libresoc.v:35055$1421_Y + connect \Y $pos$libresoc.v:35103$1421_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35058$1424 + cell $pos $pos$libresoc.v:35106$1424 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_20 [0] } - connect \Y $pos$libresoc.v:35058$1424_Y + connect \Y $pos$libresoc.v:35106$1424_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35061$1427 + cell $pos $pos$libresoc.v:35109$1427 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_22 [0] } - connect \Y $pos$libresoc.v:35061$1427_Y + connect \Y $pos$libresoc.v:35109$1427_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35064$1430 + cell $pos $pos$libresoc.v:35112$1430 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_24 [0] } - connect \Y $pos$libresoc.v:35064$1430_Y + connect \Y $pos$libresoc.v:35112$1430_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35068$1434 + cell $pos $pos$libresoc.v:35116$1434 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_26 [0] } - connect \Y $pos$libresoc.v:35068$1434_Y + connect \Y $pos$libresoc.v:35116$1434_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35071$1437 + cell $pos $pos$libresoc.v:35119$1437 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_28 [0] } - connect \Y $pos$libresoc.v:35071$1437_Y + connect \Y $pos$libresoc.v:35119$1437_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:64" - cell $pos $pos$libresoc.v:35074$1440 + cell $pos $pos$libresoc.v:35122$1440 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A { 2'01 \cnt_1_30 [0] } - connect \Y $pos$libresoc.v:35074$1440_Y + connect \Y $pos$libresoc.v:35122$1440_Y end - attribute \src "libresoc.v:34602.7-34602.20" - process $proc$libresoc.v:34602$1505 + attribute \src "libresoc.v:34650.7-34650.20" + process $proc$libresoc.v:34650$1505 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:35076.3-35090.6" - process $proc$libresoc.v:35076$1442 + attribute \src "libresoc.v:35124.3-35138.6" + process $proc$libresoc.v:35124$1442 assign { } { } assign $0\cnt_1_0[1:0] $1\cnt_1_0[1:0] - attribute \src "libresoc.v:35077.5-35077.29" + attribute \src "libresoc.v:35125.5-35125.29" switch \initial - attribute \src "libresoc.v:35077.9-35077.17" + attribute \src "libresoc.v:35125.9-35125.17" case 1'1 case end @@ -54852,13 +54888,13 @@ module \clz sync always update \cnt_1_0 $0\cnt_1_0[1:0] end - attribute \src "libresoc.v:35091.3-35105.6" - process $proc$libresoc.v:35091$1443 + attribute \src "libresoc.v:35139.3-35153.6" + process $proc$libresoc.v:35139$1443 assign { } { } assign $0\cnt_1_5[1:0] $1\cnt_1_5[1:0] - attribute \src "libresoc.v:35092.5-35092.29" + attribute \src "libresoc.v:35140.5-35140.29" switch \initial - attribute \src "libresoc.v:35092.9-35092.17" + attribute \src "libresoc.v:35140.9-35140.17" case 1'1 case end @@ -54880,13 +54916,13 @@ module \clz sync always update \cnt_1_5 $0\cnt_1_5[1:0] end - attribute \src "libresoc.v:35106.3-35120.6" - process $proc$libresoc.v:35106$1444 + attribute \src "libresoc.v:35154.3-35168.6" + process $proc$libresoc.v:35154$1444 assign { } { } assign $0\cnt_1_6[1:0] $1\cnt_1_6[1:0] - attribute \src "libresoc.v:35107.5-35107.29" + attribute \src "libresoc.v:35155.5-35155.29" switch \initial - attribute \src "libresoc.v:35107.9-35107.17" + attribute \src "libresoc.v:35155.9-35155.17" case 1'1 case end @@ -54908,13 +54944,13 @@ module \clz sync always update \cnt_1_6 $0\cnt_1_6[1:0] end - attribute \src "libresoc.v:35121.3-35135.6" - process $proc$libresoc.v:35121$1445 + attribute \src "libresoc.v:35169.3-35183.6" + process $proc$libresoc.v:35169$1445 assign { } { } assign $0\cnt_1_7[1:0] $1\cnt_1_7[1:0] - attribute \src "libresoc.v:35122.5-35122.29" + attribute \src "libresoc.v:35170.5-35170.29" switch \initial - attribute \src "libresoc.v:35122.9-35122.17" + attribute \src "libresoc.v:35170.9-35170.17" case 1'1 case end @@ -54936,13 +54972,13 @@ module \clz sync always update \cnt_1_7 $0\cnt_1_7[1:0] end - attribute \src "libresoc.v:35136.3-35150.6" - process $proc$libresoc.v:35136$1446 + attribute \src "libresoc.v:35184.3-35198.6" + process $proc$libresoc.v:35184$1446 assign { } { } assign $0\cnt_1_8[1:0] $1\cnt_1_8[1:0] - attribute \src "libresoc.v:35137.5-35137.29" + attribute \src "libresoc.v:35185.5-35185.29" switch \initial - attribute \src "libresoc.v:35137.9-35137.17" + attribute \src "libresoc.v:35185.9-35185.17" case 1'1 case end @@ -54964,13 +55000,13 @@ module \clz sync always update \cnt_1_8 $0\cnt_1_8[1:0] end - attribute \src "libresoc.v:35151.3-35165.6" - process $proc$libresoc.v:35151$1447 + attribute \src "libresoc.v:35199.3-35213.6" + process $proc$libresoc.v:35199$1447 assign { } { } assign $0\cnt_1_9[1:0] $1\cnt_1_9[1:0] - attribute \src "libresoc.v:35152.5-35152.29" + attribute \src "libresoc.v:35200.5-35200.29" switch \initial - attribute \src "libresoc.v:35152.9-35152.17" + attribute \src "libresoc.v:35200.9-35200.17" case 1'1 case end @@ -54992,13 +55028,13 @@ module \clz sync always update \cnt_1_9 $0\cnt_1_9[1:0] end - attribute \src "libresoc.v:35166.3-35180.6" - process $proc$libresoc.v:35166$1448 + attribute \src "libresoc.v:35214.3-35228.6" + process $proc$libresoc.v:35214$1448 assign { } { } assign $0\cnt_1_10[1:0] $1\cnt_1_10[1:0] - attribute \src "libresoc.v:35167.5-35167.29" + attribute \src "libresoc.v:35215.5-35215.29" switch \initial - attribute \src "libresoc.v:35167.9-35167.17" + attribute \src "libresoc.v:35215.9-35215.17" case 1'1 case end @@ -55020,13 +55056,13 @@ module \clz sync always update \cnt_1_10 $0\cnt_1_10[1:0] end - attribute \src "libresoc.v:35181.3-35195.6" - process $proc$libresoc.v:35181$1449 + attribute \src "libresoc.v:35229.3-35243.6" + process $proc$libresoc.v:35229$1449 assign { } { } assign $0\cnt_1_11[1:0] $1\cnt_1_11[1:0] - attribute \src "libresoc.v:35182.5-35182.29" + attribute \src "libresoc.v:35230.5-35230.29" switch \initial - attribute \src "libresoc.v:35182.9-35182.17" + attribute \src "libresoc.v:35230.9-35230.17" case 1'1 case end @@ -55048,13 +55084,13 @@ module \clz sync always update \cnt_1_11 $0\cnt_1_11[1:0] end - attribute \src "libresoc.v:35196.3-35210.6" - process $proc$libresoc.v:35196$1450 + attribute \src "libresoc.v:35244.3-35258.6" + process $proc$libresoc.v:35244$1450 assign { } { } assign $0\cnt_1_12[1:0] $1\cnt_1_12[1:0] - attribute \src "libresoc.v:35197.5-35197.29" + attribute \src "libresoc.v:35245.5-35245.29" switch \initial - attribute \src "libresoc.v:35197.9-35197.17" + attribute \src "libresoc.v:35245.9-35245.17" case 1'1 case end @@ -55076,13 +55112,13 @@ module \clz sync always update \cnt_1_12 $0\cnt_1_12[1:0] end - attribute \src "libresoc.v:35211.3-35225.6" - process $proc$libresoc.v:35211$1451 + attribute \src "libresoc.v:35259.3-35273.6" + process $proc$libresoc.v:35259$1451 assign { } { } assign $0\cnt_1_13[1:0] $1\cnt_1_13[1:0] - attribute \src "libresoc.v:35212.5-35212.29" + attribute \src "libresoc.v:35260.5-35260.29" switch \initial - attribute \src "libresoc.v:35212.9-35212.17" + attribute \src "libresoc.v:35260.9-35260.17" case 1'1 case end @@ -55104,13 +55140,13 @@ module \clz sync always update \cnt_1_13 $0\cnt_1_13[1:0] end - attribute \src "libresoc.v:35226.3-35240.6" - process $proc$libresoc.v:35226$1452 + attribute \src "libresoc.v:35274.3-35288.6" + process $proc$libresoc.v:35274$1452 assign { } { } assign $0\cnt_1_14[1:0] $1\cnt_1_14[1:0] - attribute \src "libresoc.v:35227.5-35227.29" + attribute \src "libresoc.v:35275.5-35275.29" switch \initial - attribute \src "libresoc.v:35227.9-35227.17" + attribute \src "libresoc.v:35275.9-35275.17" case 1'1 case end @@ -55132,13 +55168,13 @@ module \clz sync always update \cnt_1_14 $0\cnt_1_14[1:0] end - attribute \src "libresoc.v:35241.3-35255.6" - process $proc$libresoc.v:35241$1453 + attribute \src "libresoc.v:35289.3-35303.6" + process $proc$libresoc.v:35289$1453 assign { } { } assign $0\cnt_1_1[1:0] $1\cnt_1_1[1:0] - attribute \src "libresoc.v:35242.5-35242.29" + attribute \src "libresoc.v:35290.5-35290.29" switch \initial - attribute \src "libresoc.v:35242.9-35242.17" + attribute \src "libresoc.v:35290.9-35290.17" case 1'1 case end @@ -55160,13 +55196,13 @@ module \clz sync always update \cnt_1_1 $0\cnt_1_1[1:0] end - attribute \src "libresoc.v:35256.3-35270.6" - process $proc$libresoc.v:35256$1454 + attribute \src "libresoc.v:35304.3-35318.6" + process $proc$libresoc.v:35304$1454 assign { } { } assign $0\cnt_1_15[1:0] $1\cnt_1_15[1:0] - attribute \src "libresoc.v:35257.5-35257.29" + attribute \src "libresoc.v:35305.5-35305.29" switch \initial - attribute \src "libresoc.v:35257.9-35257.17" + attribute \src "libresoc.v:35305.9-35305.17" case 1'1 case end @@ -55188,13 +55224,13 @@ module \clz sync always update \cnt_1_15 $0\cnt_1_15[1:0] end - attribute \src "libresoc.v:35271.3-35285.6" - process $proc$libresoc.v:35271$1455 + attribute \src "libresoc.v:35319.3-35333.6" + process $proc$libresoc.v:35319$1455 assign { } { } assign $0\cnt_1_16[1:0] $1\cnt_1_16[1:0] - attribute \src "libresoc.v:35272.5-35272.29" + attribute \src "libresoc.v:35320.5-35320.29" switch \initial - attribute \src "libresoc.v:35272.9-35272.17" + attribute \src "libresoc.v:35320.9-35320.17" case 1'1 case end @@ -55216,13 +55252,13 @@ module \clz sync always update \cnt_1_16 $0\cnt_1_16[1:0] end - attribute \src "libresoc.v:35286.3-35300.6" - process $proc$libresoc.v:35286$1456 + attribute \src "libresoc.v:35334.3-35348.6" + process $proc$libresoc.v:35334$1456 assign { } { } assign $0\cnt_1_17[1:0] $1\cnt_1_17[1:0] - attribute \src "libresoc.v:35287.5-35287.29" + attribute \src "libresoc.v:35335.5-35335.29" switch \initial - attribute \src "libresoc.v:35287.9-35287.17" + attribute \src "libresoc.v:35335.9-35335.17" case 1'1 case end @@ -55244,13 +55280,13 @@ module \clz sync always update \cnt_1_17 $0\cnt_1_17[1:0] end - attribute \src "libresoc.v:35301.3-35315.6" - process $proc$libresoc.v:35301$1457 + attribute \src "libresoc.v:35349.3-35363.6" + process $proc$libresoc.v:35349$1457 assign { } { } assign $0\cnt_1_18[1:0] $1\cnt_1_18[1:0] - attribute \src "libresoc.v:35302.5-35302.29" + attribute \src "libresoc.v:35350.5-35350.29" switch \initial - attribute \src "libresoc.v:35302.9-35302.17" + attribute \src "libresoc.v:35350.9-35350.17" case 1'1 case end @@ -55272,13 +55308,13 @@ module \clz sync always update \cnt_1_18 $0\cnt_1_18[1:0] end - attribute \src "libresoc.v:35316.3-35330.6" - process $proc$libresoc.v:35316$1458 + attribute \src "libresoc.v:35364.3-35378.6" + process $proc$libresoc.v:35364$1458 assign { } { } assign $0\cnt_1_19[1:0] $1\cnt_1_19[1:0] - attribute \src "libresoc.v:35317.5-35317.29" + attribute \src "libresoc.v:35365.5-35365.29" switch \initial - attribute \src "libresoc.v:35317.9-35317.17" + attribute \src "libresoc.v:35365.9-35365.17" case 1'1 case end @@ -55300,13 +55336,13 @@ module \clz sync always update \cnt_1_19 $0\cnt_1_19[1:0] end - attribute \src "libresoc.v:35331.3-35345.6" - process $proc$libresoc.v:35331$1459 + attribute \src "libresoc.v:35379.3-35393.6" + process $proc$libresoc.v:35379$1459 assign { } { } assign $0\cnt_1_20[1:0] $1\cnt_1_20[1:0] - attribute \src "libresoc.v:35332.5-35332.29" + attribute \src "libresoc.v:35380.5-35380.29" switch \initial - attribute \src "libresoc.v:35332.9-35332.17" + attribute \src "libresoc.v:35380.9-35380.17" case 1'1 case end @@ -55328,13 +55364,13 @@ module \clz sync always update \cnt_1_20 $0\cnt_1_20[1:0] end - attribute \src "libresoc.v:35346.3-35360.6" - process $proc$libresoc.v:35346$1460 + attribute \src "libresoc.v:35394.3-35408.6" + process $proc$libresoc.v:35394$1460 assign { } { } assign $0\cnt_1_21[1:0] $1\cnt_1_21[1:0] - attribute \src "libresoc.v:35347.5-35347.29" + attribute \src "libresoc.v:35395.5-35395.29" switch \initial - attribute \src "libresoc.v:35347.9-35347.17" + attribute \src "libresoc.v:35395.9-35395.17" case 1'1 case end @@ -55356,13 +55392,13 @@ module \clz sync always update \cnt_1_21 $0\cnt_1_21[1:0] end - attribute \src "libresoc.v:35361.3-35375.6" - process $proc$libresoc.v:35361$1461 + attribute \src "libresoc.v:35409.3-35423.6" + process $proc$libresoc.v:35409$1461 assign { } { } assign $0\cnt_1_22[1:0] $1\cnt_1_22[1:0] - attribute \src "libresoc.v:35362.5-35362.29" + attribute \src "libresoc.v:35410.5-35410.29" switch \initial - attribute \src "libresoc.v:35362.9-35362.17" + attribute \src "libresoc.v:35410.9-35410.17" case 1'1 case end @@ -55384,13 +55420,13 @@ module \clz sync always update \cnt_1_22 $0\cnt_1_22[1:0] end - attribute \src "libresoc.v:35376.3-35390.6" - process $proc$libresoc.v:35376$1462 + attribute \src "libresoc.v:35424.3-35438.6" + process $proc$libresoc.v:35424$1462 assign { } { } assign $0\cnt_1_23[1:0] $1\cnt_1_23[1:0] - attribute \src "libresoc.v:35377.5-35377.29" + attribute \src "libresoc.v:35425.5-35425.29" switch \initial - attribute \src "libresoc.v:35377.9-35377.17" + attribute \src "libresoc.v:35425.9-35425.17" case 1'1 case end @@ -55412,13 +55448,13 @@ module \clz sync always update \cnt_1_23 $0\cnt_1_23[1:0] end - attribute \src "libresoc.v:35391.3-35405.6" - process $proc$libresoc.v:35391$1463 + attribute \src "libresoc.v:35439.3-35453.6" + process $proc$libresoc.v:35439$1463 assign { } { } assign $0\cnt_1_24[1:0] $1\cnt_1_24[1:0] - attribute \src "libresoc.v:35392.5-35392.29" + attribute \src "libresoc.v:35440.5-35440.29" switch \initial - attribute \src "libresoc.v:35392.9-35392.17" + attribute \src "libresoc.v:35440.9-35440.17" case 1'1 case end @@ -55440,13 +55476,13 @@ module \clz sync always update \cnt_1_24 $0\cnt_1_24[1:0] end - attribute \src "libresoc.v:35406.3-35420.6" - process $proc$libresoc.v:35406$1464 + attribute \src "libresoc.v:35454.3-35468.6" + process $proc$libresoc.v:35454$1464 assign { } { } assign $0\cnt_1_2[1:0] $1\cnt_1_2[1:0] - attribute \src "libresoc.v:35407.5-35407.29" + attribute \src "libresoc.v:35455.5-35455.29" switch \initial - attribute \src "libresoc.v:35407.9-35407.17" + attribute \src "libresoc.v:35455.9-35455.17" case 1'1 case end @@ -55468,13 +55504,13 @@ module \clz sync always update \cnt_1_2 $0\cnt_1_2[1:0] end - attribute \src "libresoc.v:35421.3-35435.6" - process $proc$libresoc.v:35421$1465 + attribute \src "libresoc.v:35469.3-35483.6" + process $proc$libresoc.v:35469$1465 assign { } { } assign $0\cnt_1_25[1:0] $1\cnt_1_25[1:0] - attribute \src "libresoc.v:35422.5-35422.29" + attribute \src "libresoc.v:35470.5-35470.29" switch \initial - attribute \src "libresoc.v:35422.9-35422.17" + attribute \src "libresoc.v:35470.9-35470.17" case 1'1 case end @@ -55496,13 +55532,13 @@ module \clz sync always update \cnt_1_25 $0\cnt_1_25[1:0] end - attribute \src "libresoc.v:35436.3-35450.6" - process $proc$libresoc.v:35436$1466 + attribute \src "libresoc.v:35484.3-35498.6" + process $proc$libresoc.v:35484$1466 assign { } { } assign $0\cnt_1_26[1:0] $1\cnt_1_26[1:0] - attribute \src "libresoc.v:35437.5-35437.29" + attribute \src "libresoc.v:35485.5-35485.29" switch \initial - attribute \src "libresoc.v:35437.9-35437.17" + attribute \src "libresoc.v:35485.9-35485.17" case 1'1 case end @@ -55524,13 +55560,13 @@ module \clz sync always update \cnt_1_26 $0\cnt_1_26[1:0] end - attribute \src "libresoc.v:35451.3-35465.6" - process $proc$libresoc.v:35451$1467 + attribute \src "libresoc.v:35499.3-35513.6" + process $proc$libresoc.v:35499$1467 assign { } { } assign $0\cnt_1_27[1:0] $1\cnt_1_27[1:0] - attribute \src "libresoc.v:35452.5-35452.29" + attribute \src "libresoc.v:35500.5-35500.29" switch \initial - attribute \src "libresoc.v:35452.9-35452.17" + attribute \src "libresoc.v:35500.9-35500.17" case 1'1 case end @@ -55552,13 +55588,13 @@ module \clz sync always update \cnt_1_27 $0\cnt_1_27[1:0] end - attribute \src "libresoc.v:35466.3-35480.6" - process $proc$libresoc.v:35466$1468 + attribute \src "libresoc.v:35514.3-35528.6" + process $proc$libresoc.v:35514$1468 assign { } { } assign $0\cnt_1_28[1:0] $1\cnt_1_28[1:0] - attribute \src "libresoc.v:35467.5-35467.29" + attribute \src "libresoc.v:35515.5-35515.29" switch \initial - attribute \src "libresoc.v:35467.9-35467.17" + attribute \src "libresoc.v:35515.9-35515.17" case 1'1 case end @@ -55580,13 +55616,13 @@ module \clz sync always update \cnt_1_28 $0\cnt_1_28[1:0] end - attribute \src "libresoc.v:35481.3-35495.6" - process $proc$libresoc.v:35481$1469 + attribute \src "libresoc.v:35529.3-35543.6" + process $proc$libresoc.v:35529$1469 assign { } { } assign $0\cnt_1_29[1:0] $1\cnt_1_29[1:0] - attribute \src "libresoc.v:35482.5-35482.29" + attribute \src "libresoc.v:35530.5-35530.29" switch \initial - attribute \src "libresoc.v:35482.9-35482.17" + attribute \src "libresoc.v:35530.9-35530.17" case 1'1 case end @@ -55608,13 +55644,13 @@ module \clz sync always update \cnt_1_29 $0\cnt_1_29[1:0] end - attribute \src "libresoc.v:35496.3-35510.6" - process $proc$libresoc.v:35496$1470 + attribute \src "libresoc.v:35544.3-35558.6" + process $proc$libresoc.v:35544$1470 assign { } { } assign $0\cnt_1_30[1:0] $1\cnt_1_30[1:0] - attribute \src "libresoc.v:35497.5-35497.29" + attribute \src "libresoc.v:35545.5-35545.29" switch \initial - attribute \src "libresoc.v:35497.9-35497.17" + attribute \src "libresoc.v:35545.9-35545.17" case 1'1 case end @@ -55636,13 +55672,13 @@ module \clz sync always update \cnt_1_30 $0\cnt_1_30[1:0] end - attribute \src "libresoc.v:35511.3-35525.6" - process $proc$libresoc.v:35511$1471 + attribute \src "libresoc.v:35559.3-35573.6" + process $proc$libresoc.v:35559$1471 assign { } { } assign $0\cnt_1_31[1:0] $1\cnt_1_31[1:0] - attribute \src "libresoc.v:35512.5-35512.29" + attribute \src "libresoc.v:35560.5-35560.29" switch \initial - attribute \src "libresoc.v:35512.9-35512.17" + attribute \src "libresoc.v:35560.9-35560.17" case 1'1 case end @@ -55664,13 +55700,13 @@ module \clz sync always update \cnt_1_31 $0\cnt_1_31[1:0] end - attribute \src "libresoc.v:35526.3-35545.6" - process $proc$libresoc.v:35526$1472 + attribute \src "libresoc.v:35574.3-35593.6" + process $proc$libresoc.v:35574$1472 assign { } { } assign $0\cnt_2_0[2:0] $1\cnt_2_0[2:0] - attribute \src "libresoc.v:35527.5-35527.29" + attribute \src "libresoc.v:35575.5-35575.29" switch \initial - attribute \src "libresoc.v:35527.9-35527.17" + attribute \src "libresoc.v:35575.9-35575.17" case 1'1 case end @@ -55699,13 +55735,13 @@ module \clz sync always update \cnt_2_0 $0\cnt_2_0[2:0] end - attribute \src "libresoc.v:35546.3-35565.6" - process $proc$libresoc.v:35546$1473 + attribute \src "libresoc.v:35594.3-35613.6" + process $proc$libresoc.v:35594$1473 assign { } { } assign $0\cnt_2_2[2:0] $1\cnt_2_2[2:0] - attribute \src "libresoc.v:35547.5-35547.29" + attribute \src "libresoc.v:35595.5-35595.29" switch \initial - attribute \src "libresoc.v:35547.9-35547.17" + attribute \src "libresoc.v:35595.9-35595.17" case 1'1 case end @@ -55734,13 +55770,13 @@ module \clz sync always update \cnt_2_2 $0\cnt_2_2[2:0] end - attribute \src "libresoc.v:35566.3-35585.6" - process $proc$libresoc.v:35566$1474 + attribute \src "libresoc.v:35614.3-35633.6" + process $proc$libresoc.v:35614$1474 assign { } { } assign $0\cnt_2_4[2:0] $1\cnt_2_4[2:0] - attribute \src "libresoc.v:35567.5-35567.29" + attribute \src "libresoc.v:35615.5-35615.29" switch \initial - attribute \src "libresoc.v:35567.9-35567.17" + attribute \src "libresoc.v:35615.9-35615.17" case 1'1 case end @@ -55769,13 +55805,13 @@ module \clz sync always update \cnt_2_4 $0\cnt_2_4[2:0] end - attribute \src "libresoc.v:35586.3-35605.6" - process $proc$libresoc.v:35586$1475 + attribute \src "libresoc.v:35634.3-35653.6" + process $proc$libresoc.v:35634$1475 assign { } { } assign $0\cnt_2_6[2:0] $1\cnt_2_6[2:0] - attribute \src "libresoc.v:35587.5-35587.29" + attribute \src "libresoc.v:35635.5-35635.29" switch \initial - attribute \src "libresoc.v:35587.9-35587.17" + attribute \src "libresoc.v:35635.9-35635.17" case 1'1 case end @@ -55804,13 +55840,13 @@ module \clz sync always update \cnt_2_6 $0\cnt_2_6[2:0] end - attribute \src "libresoc.v:35606.3-35625.6" - process $proc$libresoc.v:35606$1476 + attribute \src "libresoc.v:35654.3-35673.6" + process $proc$libresoc.v:35654$1476 assign { } { } assign $0\cnt_2_8[2:0] $1\cnt_2_8[2:0] - attribute \src "libresoc.v:35607.5-35607.29" + attribute \src "libresoc.v:35655.5-35655.29" switch \initial - attribute \src "libresoc.v:35607.9-35607.17" + attribute \src "libresoc.v:35655.9-35655.17" case 1'1 case end @@ -55839,13 +55875,13 @@ module \clz sync always update \cnt_2_8 $0\cnt_2_8[2:0] end - attribute \src "libresoc.v:35626.3-35645.6" - process $proc$libresoc.v:35626$1477 + attribute \src "libresoc.v:35674.3-35693.6" + process $proc$libresoc.v:35674$1477 assign { } { } assign $0\cnt_2_10[2:0] $1\cnt_2_10[2:0] - attribute \src "libresoc.v:35627.5-35627.29" + attribute \src "libresoc.v:35675.5-35675.29" switch \initial - attribute \src "libresoc.v:35627.9-35627.17" + attribute \src "libresoc.v:35675.9-35675.17" case 1'1 case end @@ -55874,13 +55910,13 @@ module \clz sync always update \cnt_2_10 $0\cnt_2_10[2:0] end - attribute \src "libresoc.v:35646.3-35660.6" - process $proc$libresoc.v:35646$1478 + attribute \src "libresoc.v:35694.3-35708.6" + process $proc$libresoc.v:35694$1478 assign { } { } assign $0\cnt_1_3[1:0] $1\cnt_1_3[1:0] - attribute \src "libresoc.v:35647.5-35647.29" + attribute \src "libresoc.v:35695.5-35695.29" switch \initial - attribute \src "libresoc.v:35647.9-35647.17" + attribute \src "libresoc.v:35695.9-35695.17" case 1'1 case end @@ -55902,13 +55938,13 @@ module \clz sync always update \cnt_1_3 $0\cnt_1_3[1:0] end - attribute \src "libresoc.v:35661.3-35680.6" - process $proc$libresoc.v:35661$1479 + attribute \src "libresoc.v:35709.3-35728.6" + process $proc$libresoc.v:35709$1479 assign { } { } assign $0\cnt_2_12[2:0] $1\cnt_2_12[2:0] - attribute \src "libresoc.v:35662.5-35662.29" + attribute \src "libresoc.v:35710.5-35710.29" switch \initial - attribute \src "libresoc.v:35662.9-35662.17" + attribute \src "libresoc.v:35710.9-35710.17" case 1'1 case end @@ -55937,13 +55973,13 @@ module \clz sync always update \cnt_2_12 $0\cnt_2_12[2:0] end - attribute \src "libresoc.v:35681.3-35700.6" - process $proc$libresoc.v:35681$1480 + attribute \src "libresoc.v:35729.3-35748.6" + process $proc$libresoc.v:35729$1480 assign { } { } assign $0\cnt_2_14[2:0] $1\cnt_2_14[2:0] - attribute \src "libresoc.v:35682.5-35682.29" + attribute \src "libresoc.v:35730.5-35730.29" switch \initial - attribute \src "libresoc.v:35682.9-35682.17" + attribute \src "libresoc.v:35730.9-35730.17" case 1'1 case end @@ -55972,13 +56008,13 @@ module \clz sync always update \cnt_2_14 $0\cnt_2_14[2:0] end - attribute \src "libresoc.v:35701.3-35720.6" - process $proc$libresoc.v:35701$1481 + attribute \src "libresoc.v:35749.3-35768.6" + process $proc$libresoc.v:35749$1481 assign { } { } assign $0\cnt_2_16[2:0] $1\cnt_2_16[2:0] - attribute \src "libresoc.v:35702.5-35702.29" + attribute \src "libresoc.v:35750.5-35750.29" switch \initial - attribute \src "libresoc.v:35702.9-35702.17" + attribute \src "libresoc.v:35750.9-35750.17" case 1'1 case end @@ -56007,13 +56043,13 @@ module \clz sync always update \cnt_2_16 $0\cnt_2_16[2:0] end - attribute \src "libresoc.v:35721.3-35740.6" - process $proc$libresoc.v:35721$1482 + attribute \src "libresoc.v:35769.3-35788.6" + process $proc$libresoc.v:35769$1482 assign { } { } assign $0\cnt_2_18[2:0] $1\cnt_2_18[2:0] - attribute \src "libresoc.v:35722.5-35722.29" + attribute \src "libresoc.v:35770.5-35770.29" switch \initial - attribute \src "libresoc.v:35722.9-35722.17" + attribute \src "libresoc.v:35770.9-35770.17" case 1'1 case end @@ -56042,13 +56078,13 @@ module \clz sync always update \cnt_2_18 $0\cnt_2_18[2:0] end - attribute \src "libresoc.v:35741.3-35760.6" - process $proc$libresoc.v:35741$1483 + attribute \src "libresoc.v:35789.3-35808.6" + process $proc$libresoc.v:35789$1483 assign { } { } assign $0\cnt_2_20[2:0] $1\cnt_2_20[2:0] - attribute \src "libresoc.v:35742.5-35742.29" + attribute \src "libresoc.v:35790.5-35790.29" switch \initial - attribute \src "libresoc.v:35742.9-35742.17" + attribute \src "libresoc.v:35790.9-35790.17" case 1'1 case end @@ -56077,13 +56113,13 @@ module \clz sync always update \cnt_2_20 $0\cnt_2_20[2:0] end - attribute \src "libresoc.v:35761.3-35780.6" - process $proc$libresoc.v:35761$1484 + attribute \src "libresoc.v:35809.3-35828.6" + process $proc$libresoc.v:35809$1484 assign { } { } assign $0\cnt_2_22[2:0] $1\cnt_2_22[2:0] - attribute \src "libresoc.v:35762.5-35762.29" + attribute \src "libresoc.v:35810.5-35810.29" switch \initial - attribute \src "libresoc.v:35762.9-35762.17" + attribute \src "libresoc.v:35810.9-35810.17" case 1'1 case end @@ -56112,13 +56148,13 @@ module \clz sync always update \cnt_2_22 $0\cnt_2_22[2:0] end - attribute \src "libresoc.v:35781.3-35800.6" - process $proc$libresoc.v:35781$1485 + attribute \src "libresoc.v:35829.3-35848.6" + process $proc$libresoc.v:35829$1485 assign { } { } assign $0\cnt_2_24[2:0] $1\cnt_2_24[2:0] - attribute \src "libresoc.v:35782.5-35782.29" + attribute \src "libresoc.v:35830.5-35830.29" switch \initial - attribute \src "libresoc.v:35782.9-35782.17" + attribute \src "libresoc.v:35830.9-35830.17" case 1'1 case end @@ -56147,13 +56183,13 @@ module \clz sync always update \cnt_2_24 $0\cnt_2_24[2:0] end - attribute \src "libresoc.v:35801.3-35820.6" - process $proc$libresoc.v:35801$1486 + attribute \src "libresoc.v:35849.3-35868.6" + process $proc$libresoc.v:35849$1486 assign { } { } assign $0\cnt_2_26[2:0] $1\cnt_2_26[2:0] - attribute \src "libresoc.v:35802.5-35802.29" + attribute \src "libresoc.v:35850.5-35850.29" switch \initial - attribute \src "libresoc.v:35802.9-35802.17" + attribute \src "libresoc.v:35850.9-35850.17" case 1'1 case end @@ -56182,13 +56218,13 @@ module \clz sync always update \cnt_2_26 $0\cnt_2_26[2:0] end - attribute \src "libresoc.v:35821.3-35840.6" - process $proc$libresoc.v:35821$1487 + attribute \src "libresoc.v:35869.3-35888.6" + process $proc$libresoc.v:35869$1487 assign { } { } assign $0\cnt_2_28[2:0] $1\cnt_2_28[2:0] - attribute \src "libresoc.v:35822.5-35822.29" + attribute \src "libresoc.v:35870.5-35870.29" switch \initial - attribute \src "libresoc.v:35822.9-35822.17" + attribute \src "libresoc.v:35870.9-35870.17" case 1'1 case end @@ -56217,13 +56253,13 @@ module \clz sync always update \cnt_2_28 $0\cnt_2_28[2:0] end - attribute \src "libresoc.v:35841.3-35860.6" - process $proc$libresoc.v:35841$1488 + attribute \src "libresoc.v:35889.3-35908.6" + process $proc$libresoc.v:35889$1488 assign { } { } assign $0\cnt_2_30[2:0] $1\cnt_2_30[2:0] - attribute \src "libresoc.v:35842.5-35842.29" + attribute \src "libresoc.v:35890.5-35890.29" switch \initial - attribute \src "libresoc.v:35842.9-35842.17" + attribute \src "libresoc.v:35890.9-35890.17" case 1'1 case end @@ -56252,13 +56288,13 @@ module \clz sync always update \cnt_2_30 $0\cnt_2_30[2:0] end - attribute \src "libresoc.v:35861.3-35880.6" - process $proc$libresoc.v:35861$1489 + attribute \src "libresoc.v:35909.3-35928.6" + process $proc$libresoc.v:35909$1489 assign { } { } assign $0\cnt_3_0[3:0] $1\cnt_3_0[3:0] - attribute \src "libresoc.v:35862.5-35862.29" + attribute \src "libresoc.v:35910.5-35910.29" switch \initial - attribute \src "libresoc.v:35862.9-35862.17" + attribute \src "libresoc.v:35910.9-35910.17" case 1'1 case end @@ -56287,13 +56323,13 @@ module \clz sync always update \cnt_3_0 $0\cnt_3_0[3:0] end - attribute \src "libresoc.v:35881.3-35900.6" - process $proc$libresoc.v:35881$1490 + attribute \src "libresoc.v:35929.3-35948.6" + process $proc$libresoc.v:35929$1490 assign { } { } assign $0\cnt_3_2[3:0] $1\cnt_3_2[3:0] - attribute \src "libresoc.v:35882.5-35882.29" + attribute \src "libresoc.v:35930.5-35930.29" switch \initial - attribute \src "libresoc.v:35882.9-35882.17" + attribute \src "libresoc.v:35930.9-35930.17" case 1'1 case end @@ -56322,13 +56358,13 @@ module \clz sync always update \cnt_3_2 $0\cnt_3_2[3:0] end - attribute \src "libresoc.v:35901.3-35920.6" - process $proc$libresoc.v:35901$1491 + attribute \src "libresoc.v:35949.3-35968.6" + process $proc$libresoc.v:35949$1491 assign { } { } assign $0\cnt_3_4[3:0] $1\cnt_3_4[3:0] - attribute \src "libresoc.v:35902.5-35902.29" + attribute \src "libresoc.v:35950.5-35950.29" switch \initial - attribute \src "libresoc.v:35902.9-35902.17" + attribute \src "libresoc.v:35950.9-35950.17" case 1'1 case end @@ -56357,13 +56393,13 @@ module \clz sync always update \cnt_3_4 $0\cnt_3_4[3:0] end - attribute \src "libresoc.v:35921.3-35940.6" - process $proc$libresoc.v:35921$1492 + attribute \src "libresoc.v:35969.3-35988.6" + process $proc$libresoc.v:35969$1492 assign { } { } assign $0\cnt_3_6[3:0] $1\cnt_3_6[3:0] - attribute \src "libresoc.v:35922.5-35922.29" + attribute \src "libresoc.v:35970.5-35970.29" switch \initial - attribute \src "libresoc.v:35922.9-35922.17" + attribute \src "libresoc.v:35970.9-35970.17" case 1'1 case end @@ -56392,13 +56428,13 @@ module \clz sync always update \cnt_3_6 $0\cnt_3_6[3:0] end - attribute \src "libresoc.v:35941.3-35960.6" - process $proc$libresoc.v:35941$1493 + attribute \src "libresoc.v:35989.3-36008.6" + process $proc$libresoc.v:35989$1493 assign { } { } assign $0\cnt_3_8[3:0] $1\cnt_3_8[3:0] - attribute \src "libresoc.v:35942.5-35942.29" + attribute \src "libresoc.v:35990.5-35990.29" switch \initial - attribute \src "libresoc.v:35942.9-35942.17" + attribute \src "libresoc.v:35990.9-35990.17" case 1'1 case end @@ -56427,13 +56463,13 @@ module \clz sync always update \cnt_3_8 $0\cnt_3_8[3:0] end - attribute \src "libresoc.v:35961.3-35980.6" - process $proc$libresoc.v:35961$1494 + attribute \src "libresoc.v:36009.3-36028.6" + process $proc$libresoc.v:36009$1494 assign { } { } assign $0\cnt_3_10[3:0] $1\cnt_3_10[3:0] - attribute \src "libresoc.v:35962.5-35962.29" + attribute \src "libresoc.v:36010.5-36010.29" switch \initial - attribute \src "libresoc.v:35962.9-35962.17" + attribute \src "libresoc.v:36010.9-36010.17" case 1'1 case end @@ -56462,13 +56498,13 @@ module \clz sync always update \cnt_3_10 $0\cnt_3_10[3:0] end - attribute \src "libresoc.v:35981.3-36000.6" - process $proc$libresoc.v:35981$1495 + attribute \src "libresoc.v:36029.3-36048.6" + process $proc$libresoc.v:36029$1495 assign { } { } assign $0\cnt_3_12[3:0] $1\cnt_3_12[3:0] - attribute \src "libresoc.v:35982.5-35982.29" + attribute \src "libresoc.v:36030.5-36030.29" switch \initial - attribute \src "libresoc.v:35982.9-35982.17" + attribute \src "libresoc.v:36030.9-36030.17" case 1'1 case end @@ -56497,13 +56533,13 @@ module \clz sync always update \cnt_3_12 $0\cnt_3_12[3:0] end - attribute \src "libresoc.v:36001.3-36020.6" - process $proc$libresoc.v:36001$1496 + attribute \src "libresoc.v:36049.3-36068.6" + process $proc$libresoc.v:36049$1496 assign { } { } assign $0\cnt_3_14[3:0] $1\cnt_3_14[3:0] - attribute \src "libresoc.v:36002.5-36002.29" + attribute \src "libresoc.v:36050.5-36050.29" switch \initial - attribute \src "libresoc.v:36002.9-36002.17" + attribute \src "libresoc.v:36050.9-36050.17" case 1'1 case end @@ -56532,13 +56568,13 @@ module \clz sync always update \cnt_3_14 $0\cnt_3_14[3:0] end - attribute \src "libresoc.v:36021.3-36040.6" - process $proc$libresoc.v:36021$1497 + attribute \src "libresoc.v:36069.3-36088.6" + process $proc$libresoc.v:36069$1497 assign { } { } assign $0\cnt_4_0[4:0] $1\cnt_4_0[4:0] - attribute \src "libresoc.v:36022.5-36022.29" + attribute \src "libresoc.v:36070.5-36070.29" switch \initial - attribute \src "libresoc.v:36022.9-36022.17" + attribute \src "libresoc.v:36070.9-36070.17" case 1'1 case end @@ -56567,13 +56603,13 @@ module \clz sync always update \cnt_4_0 $0\cnt_4_0[4:0] end - attribute \src "libresoc.v:36041.3-36060.6" - process $proc$libresoc.v:36041$1498 + attribute \src "libresoc.v:36089.3-36108.6" + process $proc$libresoc.v:36089$1498 assign { } { } assign $0\cnt_4_2[4:0] $1\cnt_4_2[4:0] - attribute \src "libresoc.v:36042.5-36042.29" + attribute \src "libresoc.v:36090.5-36090.29" switch \initial - attribute \src "libresoc.v:36042.9-36042.17" + attribute \src "libresoc.v:36090.9-36090.17" case 1'1 case end @@ -56602,13 +56638,13 @@ module \clz sync always update \cnt_4_2 $0\cnt_4_2[4:0] end - attribute \src "libresoc.v:36061.3-36075.6" - process $proc$libresoc.v:36061$1499 + attribute \src "libresoc.v:36109.3-36123.6" + process $proc$libresoc.v:36109$1499 assign { } { } assign $0\cnt_1_4[1:0] $1\cnt_1_4[1:0] - attribute \src "libresoc.v:36062.5-36062.29" + attribute \src "libresoc.v:36110.5-36110.29" switch \initial - attribute \src "libresoc.v:36062.9-36062.17" + attribute \src "libresoc.v:36110.9-36110.17" case 1'1 case end @@ -56630,13 +56666,13 @@ module \clz sync always update \cnt_1_4 $0\cnt_1_4[1:0] end - attribute \src "libresoc.v:36076.3-36095.6" - process $proc$libresoc.v:36076$1500 + attribute \src "libresoc.v:36124.3-36143.6" + process $proc$libresoc.v:36124$1500 assign { } { } assign $0\cnt_4_4[4:0] $1\cnt_4_4[4:0] - attribute \src "libresoc.v:36077.5-36077.29" + attribute \src "libresoc.v:36125.5-36125.29" switch \initial - attribute \src "libresoc.v:36077.9-36077.17" + attribute \src "libresoc.v:36125.9-36125.17" case 1'1 case end @@ -56665,13 +56701,13 @@ module \clz sync always update \cnt_4_4 $0\cnt_4_4[4:0] end - attribute \src "libresoc.v:36096.3-36115.6" - process $proc$libresoc.v:36096$1501 + attribute \src "libresoc.v:36144.3-36163.6" + process $proc$libresoc.v:36144$1501 assign { } { } assign $0\cnt_4_6[4:0] $1\cnt_4_6[4:0] - attribute \src "libresoc.v:36097.5-36097.29" + attribute \src "libresoc.v:36145.5-36145.29" switch \initial - attribute \src "libresoc.v:36097.9-36097.17" + attribute \src "libresoc.v:36145.9-36145.17" case 1'1 case end @@ -56700,13 +56736,13 @@ module \clz sync always update \cnt_4_6 $0\cnt_4_6[4:0] end - attribute \src "libresoc.v:36116.3-36135.6" - process $proc$libresoc.v:36116$1502 + attribute \src "libresoc.v:36164.3-36183.6" + process $proc$libresoc.v:36164$1502 assign { } { } assign $0\cnt_5_0[5:0] $1\cnt_5_0[5:0] - attribute \src "libresoc.v:36117.5-36117.29" + attribute \src "libresoc.v:36165.5-36165.29" switch \initial - attribute \src "libresoc.v:36117.9-36117.17" + attribute \src "libresoc.v:36165.9-36165.17" case 1'1 case end @@ -56735,13 +56771,13 @@ module \clz sync always update \cnt_5_0 $0\cnt_5_0[5:0] end - attribute \src "libresoc.v:36136.3-36155.6" - process $proc$libresoc.v:36136$1503 + attribute \src "libresoc.v:36184.3-36203.6" + process $proc$libresoc.v:36184$1503 assign { } { } assign $0\cnt_5_2[5:0] $1\cnt_5_2[5:0] - attribute \src "libresoc.v:36137.5-36137.29" + attribute \src "libresoc.v:36185.5-36185.29" switch \initial - attribute \src "libresoc.v:36137.9-36137.17" + attribute \src "libresoc.v:36185.9-36185.17" case 1'1 case end @@ -56770,13 +56806,13 @@ module \clz sync always update \cnt_5_2 $0\cnt_5_2[5:0] end - attribute \src "libresoc.v:36156.3-36175.6" - process $proc$libresoc.v:36156$1504 + attribute \src "libresoc.v:36204.3-36223.6" + process $proc$libresoc.v:36204$1504 assign { } { } assign $0\cnt_6_0[6:0] $1\cnt_6_0[6:0] - attribute \src "libresoc.v:36157.5-36157.29" + attribute \src "libresoc.v:36205.5-36205.29" switch \initial - attribute \src "libresoc.v:36157.9-36157.17" + attribute \src "libresoc.v:36205.9-36205.17" case 1'1 case end @@ -56805,99 +56841,99 @@ module \clz sync always update \cnt_6_0 $0\cnt_6_0[6:0] end - connect \$9 $eq$libresoc.v:34983$1349_Y - connect \$99 $eq$libresoc.v:34984$1350_Y - connect \$101 $pos$libresoc.v:34985$1351_Y - connect \$103 $eq$libresoc.v:34986$1352_Y - connect \$105 $eq$libresoc.v:34987$1353_Y - connect \$107 $pos$libresoc.v:34988$1354_Y - connect \$109 $eq$libresoc.v:34989$1355_Y - connect \$111 $eq$libresoc.v:34990$1356_Y - connect \$113 $pos$libresoc.v:34991$1357_Y - connect \$115 $eq$libresoc.v:34992$1358_Y - connect \$117 $eq$libresoc.v:34993$1359_Y - connect \$11 $pos$libresoc.v:34994$1360_Y - connect \$119 $pos$libresoc.v:34995$1361_Y - connect \$121 $eq$libresoc.v:34996$1362_Y - connect \$123 $eq$libresoc.v:34997$1363_Y - connect \$125 $pos$libresoc.v:34998$1364_Y - connect \$127 $eq$libresoc.v:34999$1365_Y - connect \$129 $eq$libresoc.v:35000$1366_Y - connect \$131 $pos$libresoc.v:35001$1367_Y - connect \$133 $eq$libresoc.v:35002$1368_Y - connect \$135 $eq$libresoc.v:35003$1369_Y - connect \$137 $pos$libresoc.v:35004$1370_Y - connect \$13 $eq$libresoc.v:35005$1371_Y - connect \$139 $eq$libresoc.v:35006$1372_Y - connect \$141 $eq$libresoc.v:35007$1373_Y - connect \$143 $pos$libresoc.v:35008$1374_Y - connect \$145 $eq$libresoc.v:35009$1375_Y - connect \$147 $eq$libresoc.v:35010$1376_Y - connect \$149 $pos$libresoc.v:35011$1377_Y - connect \$151 $eq$libresoc.v:35012$1378_Y - connect \$153 $eq$libresoc.v:35013$1379_Y - connect \$155 $pos$libresoc.v:35014$1380_Y - connect \$157 $eq$libresoc.v:35015$1381_Y - connect \$15 $eq$libresoc.v:35016$1382_Y - connect \$159 $eq$libresoc.v:35017$1383_Y - connect \$161 $pos$libresoc.v:35018$1384_Y - connect \$163 $eq$libresoc.v:35019$1385_Y - connect \$165 $eq$libresoc.v:35020$1386_Y - connect \$167 $pos$libresoc.v:35021$1387_Y - connect \$169 $eq$libresoc.v:35022$1388_Y - connect \$171 $eq$libresoc.v:35023$1389_Y - connect \$173 $pos$libresoc.v:35024$1390_Y - connect \$175 $eq$libresoc.v:35025$1391_Y - connect \$177 $eq$libresoc.v:35026$1392_Y - connect \$17 $pos$libresoc.v:35027$1393_Y - connect \$179 $pos$libresoc.v:35028$1394_Y - connect \$181 $eq$libresoc.v:35029$1395_Y - connect \$183 $eq$libresoc.v:35030$1396_Y - connect \$185 $pos$libresoc.v:35031$1397_Y - connect \$1 $eq$libresoc.v:35032$1398_Y - connect \$19 $eq$libresoc.v:35033$1399_Y - connect \$21 $eq$libresoc.v:35034$1400_Y - connect \$23 $pos$libresoc.v:35035$1401_Y - connect \$25 $eq$libresoc.v:35036$1402_Y - connect \$27 $eq$libresoc.v:35037$1403_Y - connect \$29 $pos$libresoc.v:35038$1404_Y - connect \$31 $eq$libresoc.v:35039$1405_Y - connect \$33 $eq$libresoc.v:35040$1406_Y - connect \$35 $pos$libresoc.v:35041$1407_Y - connect \$37 $eq$libresoc.v:35042$1408_Y - connect \$3 $eq$libresoc.v:35043$1409_Y - connect \$39 $eq$libresoc.v:35044$1410_Y - connect \$41 $pos$libresoc.v:35045$1411_Y - connect \$43 $eq$libresoc.v:35046$1412_Y - connect \$45 $eq$libresoc.v:35047$1413_Y - connect \$47 $pos$libresoc.v:35048$1414_Y - connect \$49 $eq$libresoc.v:35049$1415_Y - connect \$51 $eq$libresoc.v:35050$1416_Y - connect \$53 $pos$libresoc.v:35051$1417_Y - connect \$55 $eq$libresoc.v:35052$1418_Y - connect \$57 $eq$libresoc.v:35053$1419_Y - connect \$5 $pos$libresoc.v:35054$1420_Y - connect \$59 $pos$libresoc.v:35055$1421_Y - connect \$61 $eq$libresoc.v:35056$1422_Y - connect \$63 $eq$libresoc.v:35057$1423_Y - connect \$65 $pos$libresoc.v:35058$1424_Y - connect \$67 $eq$libresoc.v:35059$1425_Y - connect \$69 $eq$libresoc.v:35060$1426_Y - connect \$71 $pos$libresoc.v:35061$1427_Y - connect \$73 $eq$libresoc.v:35062$1428_Y - connect \$75 $eq$libresoc.v:35063$1429_Y - connect \$77 $pos$libresoc.v:35064$1430_Y - connect \$7 $eq$libresoc.v:35065$1431_Y - connect \$79 $eq$libresoc.v:35066$1432_Y - connect \$81 $eq$libresoc.v:35067$1433_Y - connect \$83 $pos$libresoc.v:35068$1434_Y - connect \$85 $eq$libresoc.v:35069$1435_Y - connect \$87 $eq$libresoc.v:35070$1436_Y - connect \$89 $pos$libresoc.v:35071$1437_Y - connect \$91 $eq$libresoc.v:35072$1438_Y - connect \$93 $eq$libresoc.v:35073$1439_Y - connect \$95 $pos$libresoc.v:35074$1440_Y - connect \$97 $eq$libresoc.v:35075$1441_Y + connect \$9 $eq$libresoc.v:35031$1349_Y + connect \$99 $eq$libresoc.v:35032$1350_Y + connect \$101 $pos$libresoc.v:35033$1351_Y + connect \$103 $eq$libresoc.v:35034$1352_Y + connect \$105 $eq$libresoc.v:35035$1353_Y + connect \$107 $pos$libresoc.v:35036$1354_Y + connect \$109 $eq$libresoc.v:35037$1355_Y + connect \$111 $eq$libresoc.v:35038$1356_Y + connect \$113 $pos$libresoc.v:35039$1357_Y + connect \$115 $eq$libresoc.v:35040$1358_Y + connect \$117 $eq$libresoc.v:35041$1359_Y + connect \$11 $pos$libresoc.v:35042$1360_Y + connect \$119 $pos$libresoc.v:35043$1361_Y + connect \$121 $eq$libresoc.v:35044$1362_Y + connect \$123 $eq$libresoc.v:35045$1363_Y + connect \$125 $pos$libresoc.v:35046$1364_Y + connect \$127 $eq$libresoc.v:35047$1365_Y + connect \$129 $eq$libresoc.v:35048$1366_Y + connect \$131 $pos$libresoc.v:35049$1367_Y + connect \$133 $eq$libresoc.v:35050$1368_Y + connect \$135 $eq$libresoc.v:35051$1369_Y + connect \$137 $pos$libresoc.v:35052$1370_Y + connect \$13 $eq$libresoc.v:35053$1371_Y + connect \$139 $eq$libresoc.v:35054$1372_Y + connect \$141 $eq$libresoc.v:35055$1373_Y + connect \$143 $pos$libresoc.v:35056$1374_Y + connect \$145 $eq$libresoc.v:35057$1375_Y + connect \$147 $eq$libresoc.v:35058$1376_Y + connect \$149 $pos$libresoc.v:35059$1377_Y + connect \$151 $eq$libresoc.v:35060$1378_Y + connect \$153 $eq$libresoc.v:35061$1379_Y + connect \$155 $pos$libresoc.v:35062$1380_Y + connect \$157 $eq$libresoc.v:35063$1381_Y + connect \$15 $eq$libresoc.v:35064$1382_Y + connect \$159 $eq$libresoc.v:35065$1383_Y + connect \$161 $pos$libresoc.v:35066$1384_Y + connect \$163 $eq$libresoc.v:35067$1385_Y + connect \$165 $eq$libresoc.v:35068$1386_Y + connect \$167 $pos$libresoc.v:35069$1387_Y + connect \$169 $eq$libresoc.v:35070$1388_Y + connect \$171 $eq$libresoc.v:35071$1389_Y + connect \$173 $pos$libresoc.v:35072$1390_Y + connect \$175 $eq$libresoc.v:35073$1391_Y + connect \$177 $eq$libresoc.v:35074$1392_Y + connect \$17 $pos$libresoc.v:35075$1393_Y + connect \$179 $pos$libresoc.v:35076$1394_Y + connect \$181 $eq$libresoc.v:35077$1395_Y + connect \$183 $eq$libresoc.v:35078$1396_Y + connect \$185 $pos$libresoc.v:35079$1397_Y + connect \$1 $eq$libresoc.v:35080$1398_Y + connect \$19 $eq$libresoc.v:35081$1399_Y + connect \$21 $eq$libresoc.v:35082$1400_Y + connect \$23 $pos$libresoc.v:35083$1401_Y + connect \$25 $eq$libresoc.v:35084$1402_Y + connect \$27 $eq$libresoc.v:35085$1403_Y + connect \$29 $pos$libresoc.v:35086$1404_Y + connect \$31 $eq$libresoc.v:35087$1405_Y + connect \$33 $eq$libresoc.v:35088$1406_Y + connect \$35 $pos$libresoc.v:35089$1407_Y + connect \$37 $eq$libresoc.v:35090$1408_Y + connect \$3 $eq$libresoc.v:35091$1409_Y + connect \$39 $eq$libresoc.v:35092$1410_Y + connect \$41 $pos$libresoc.v:35093$1411_Y + connect \$43 $eq$libresoc.v:35094$1412_Y + connect \$45 $eq$libresoc.v:35095$1413_Y + connect \$47 $pos$libresoc.v:35096$1414_Y + connect \$49 $eq$libresoc.v:35097$1415_Y + connect \$51 $eq$libresoc.v:35098$1416_Y + connect \$53 $pos$libresoc.v:35099$1417_Y + connect \$55 $eq$libresoc.v:35100$1418_Y + connect \$57 $eq$libresoc.v:35101$1419_Y + connect \$5 $pos$libresoc.v:35102$1420_Y + connect \$59 $pos$libresoc.v:35103$1421_Y + connect \$61 $eq$libresoc.v:35104$1422_Y + connect \$63 $eq$libresoc.v:35105$1423_Y + connect \$65 $pos$libresoc.v:35106$1424_Y + connect \$67 $eq$libresoc.v:35107$1425_Y + connect \$69 $eq$libresoc.v:35108$1426_Y + connect \$71 $pos$libresoc.v:35109$1427_Y + connect \$73 $eq$libresoc.v:35110$1428_Y + connect \$75 $eq$libresoc.v:35111$1429_Y + connect \$77 $pos$libresoc.v:35112$1430_Y + connect \$7 $eq$libresoc.v:35113$1431_Y + connect \$79 $eq$libresoc.v:35114$1432_Y + connect \$81 $eq$libresoc.v:35115$1433_Y + connect \$83 $pos$libresoc.v:35116$1434_Y + connect \$85 $eq$libresoc.v:35117$1435_Y + connect \$87 $eq$libresoc.v:35118$1436_Y + connect \$89 $pos$libresoc.v:35119$1437_Y + connect \$91 $eq$libresoc.v:35120$1438_Y + connect \$93 $eq$libresoc.v:35121$1439_Y + connect \$95 $pos$libresoc.v:35122$1440_Y + connect \$97 $eq$libresoc.v:35123$1441_Y connect \lz \cnt_6_0 connect \pair62 \sig_in [63:62] connect \pair60 \sig_in [61:60] @@ -56932,3451 +56968,3451 @@ module \clz connect \pair2 \sig_in [3:2] connect \pair0 \sig_in [1:0] end -attribute \src "libresoc.v:36213.1-49141.10" +attribute \src "libresoc.v:36261.1-49193.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core" attribute \generator "nMigen" module \core - attribute \src "libresoc.v:46587.3-46607.6" + attribute \src "libresoc.v:46639.3-46659.6" wire $0\core_terminate_o$next[0:0]$2673 - attribute \src "libresoc.v:42982.3-42983.49" + attribute \src "libresoc.v:43030.3-43031.49" wire $0\core_terminate_o[0:0] - attribute \src "libresoc.v:46477.3-46567.6" + attribute \src "libresoc.v:46529.3-46619.6" wire $0\corebusy_o[0:0] - attribute \src "libresoc.v:46431.3-46457.6" + attribute \src "libresoc.v:46479.3-46509.6" wire width 2 $0\counter$next[1:0]$2654 - attribute \src "libresoc.v:42984.3-42985.31" + attribute \src "libresoc.v:43032.3-43033.31" wire width 2 $0\counter[1:0] - attribute \src "libresoc.v:46412.3-46420.6" + attribute \src "libresoc.v:46460.3-46468.6" wire $0\dp_CR_cr_a_branch0_1$next[0:0]$2648 - attribute \src "libresoc.v:42918.3-42919.57" + attribute \src "libresoc.v:42966.3-42967.57" wire $0\dp_CR_cr_a_branch0_1[0:0] - attribute \src "libresoc.v:46393.3-46401.6" + attribute \src "libresoc.v:46441.3-46449.6" wire $0\dp_CR_cr_a_cr0_0$next[0:0]$2642 - attribute \src "libresoc.v:42920.3-42921.49" + attribute \src "libresoc.v:42968.3-42969.49" wire $0\dp_CR_cr_a_cr0_0[0:0] - attribute \src "libresoc.v:46458.3-46466.6" + attribute \src "libresoc.v:46510.3-46518.6" wire $0\dp_CR_cr_b_cr0_0$next[0:0]$2660 - attribute \src "libresoc.v:42916.3-42917.49" + attribute \src "libresoc.v:42964.3-42965.49" wire $0\dp_CR_cr_b_cr0_0[0:0] - attribute \src "libresoc.v:46568.3-46576.6" + attribute \src "libresoc.v:46620.3-46628.6" wire $0\dp_CR_cr_c_cr0_0$next[0:0]$2667 - attribute \src "libresoc.v:42914.3-42915.49" + attribute \src "libresoc.v:42962.3-42963.49" wire $0\dp_CR_cr_c_cr0_0[0:0] - attribute \src "libresoc.v:46374.3-46382.6" + attribute \src "libresoc.v:46422.3-46430.6" wire $0\dp_CR_full_cr_cr0_0$next[0:0]$2636 - attribute \src "libresoc.v:42922.3-42923.55" + attribute \src "libresoc.v:42970.3-42971.55" wire $0\dp_CR_full_cr_cr0_0[0:0] - attribute \src "libresoc.v:46608.3-46616.6" + attribute \src "libresoc.v:46660.3-46668.6" wire $0\dp_FAST_fast1_branch0_0$next[0:0]$2678 - attribute \src "libresoc.v:42912.3-42913.63" + attribute \src "libresoc.v:42960.3-42961.63" wire $0\dp_FAST_fast1_branch0_0[0:0] - attribute \src "libresoc.v:46675.3-46683.6" + attribute \src "libresoc.v:46727.3-46735.6" wire $0\dp_FAST_fast1_spr0_2$next[0:0]$2691 - attribute \src "libresoc.v:42908.3-42909.57" + attribute \src "libresoc.v:42956.3-42957.57" wire $0\dp_FAST_fast1_spr0_2[0:0] - attribute \src "libresoc.v:46627.3-46635.6" + attribute \src "libresoc.v:46679.3-46687.6" wire $0\dp_FAST_fast1_trap0_1$next[0:0]$2684 - attribute \src "libresoc.v:42910.3-42911.59" + attribute \src "libresoc.v:42958.3-42959.59" wire $0\dp_FAST_fast1_trap0_1[0:0] - attribute \src "libresoc.v:46723.3-46731.6" + attribute \src "libresoc.v:46775.3-46783.6" wire $0\dp_FAST_fast2_branch0_0$next[0:0]$2698 - attribute \src "libresoc.v:42906.3-42907.63" + attribute \src "libresoc.v:42954.3-42955.63" wire $0\dp_FAST_fast2_branch0_0[0:0] - attribute \src "libresoc.v:46742.3-46750.6" + attribute \src "libresoc.v:46794.3-46802.6" wire $0\dp_FAST_fast2_trap0_1$next[0:0]$2704 - attribute \src "libresoc.v:42904.3-42905.59" + attribute \src "libresoc.v:42952.3-42953.59" wire $0\dp_FAST_fast2_trap0_1[0:0] - attribute \src "libresoc.v:45823.3-45831.6" + attribute \src "libresoc.v:45871.3-45879.6" wire $0\dp_INT_ra_alu0_0$next[0:0]$2474 - attribute \src "libresoc.v:42980.3-42981.49" + attribute \src "libresoc.v:43028.3-43029.49" wire $0\dp_INT_ra_alu0_0[0:0] - attribute \src "libresoc.v:45842.3-45850.6" + attribute \src "libresoc.v:45890.3-45898.6" wire $0\dp_INT_ra_cr0_1$next[0:0]$2478 - attribute \src "libresoc.v:42978.3-42979.47" + attribute \src "libresoc.v:43026.3-43027.47" wire $0\dp_INT_ra_cr0_1[0:0] - attribute \src "libresoc.v:45918.3-45926.6" + attribute \src "libresoc.v:45966.3-45974.6" wire $0\dp_INT_ra_div0_5$next[0:0]$2502 - attribute \src "libresoc.v:42970.3-42971.49" + attribute \src "libresoc.v:43018.3-43019.49" wire $0\dp_INT_ra_div0_5[0:0] - attribute \src "libresoc.v:45975.3-45983.6" + attribute \src "libresoc.v:46023.3-46031.6" wire $0\dp_INT_ra_ldst0_8$next[0:0]$2520 - attribute \src "libresoc.v:42964.3-42965.51" + attribute \src "libresoc.v:43012.3-43013.51" wire $0\dp_INT_ra_ldst0_8[0:0] - attribute \src "libresoc.v:45880.3-45888.6" + attribute \src "libresoc.v:45928.3-45936.6" wire $0\dp_INT_ra_logical0_3$next[0:0]$2490 - attribute \src "libresoc.v:42974.3-42975.57" + attribute \src "libresoc.v:43022.3-43023.57" wire $0\dp_INT_ra_logical0_3[0:0] - attribute \src "libresoc.v:45937.3-45945.6" + attribute \src "libresoc.v:45985.3-45993.6" wire $0\dp_INT_ra_mul0_6$next[0:0]$2508 - attribute \src "libresoc.v:42968.3-42969.49" + attribute \src "libresoc.v:43016.3-43017.49" wire $0\dp_INT_ra_mul0_6[0:0] - attribute \src "libresoc.v:45956.3-45964.6" + attribute \src "libresoc.v:46004.3-46012.6" wire $0\dp_INT_ra_shiftrot0_7$next[0:0]$2514 - attribute \src "libresoc.v:42966.3-42967.59" + attribute \src "libresoc.v:43014.3-43015.59" wire $0\dp_INT_ra_shiftrot0_7[0:0] - attribute \src "libresoc.v:45899.3-45907.6" + attribute \src "libresoc.v:45947.3-45955.6" wire $0\dp_INT_ra_spr0_4$next[0:0]$2496 - attribute \src "libresoc.v:42972.3-42973.49" + attribute \src "libresoc.v:43020.3-43021.49" wire $0\dp_INT_ra_spr0_4[0:0] - attribute \src "libresoc.v:45861.3-45869.6" + attribute \src "libresoc.v:45909.3-45917.6" wire $0\dp_INT_ra_trap0_2$next[0:0]$2484 - attribute \src "libresoc.v:42976.3-42977.51" + attribute \src "libresoc.v:43024.3-43025.51" wire $0\dp_INT_ra_trap0_2[0:0] - attribute \src "libresoc.v:45994.3-46002.6" + attribute \src "libresoc.v:46042.3-46050.6" wire $0\dp_INT_rb_alu0_0$next[0:0]$2526 - attribute \src "libresoc.v:42962.3-42963.49" + attribute \src "libresoc.v:43010.3-43011.49" wire $0\dp_INT_rb_alu0_0[0:0] - attribute \src "libresoc.v:46013.3-46021.6" + attribute \src "libresoc.v:46061.3-46069.6" wire $0\dp_INT_rb_cr0_1$next[0:0]$2530 - attribute \src "libresoc.v:42960.3-42961.47" + attribute \src "libresoc.v:43008.3-43009.47" wire $0\dp_INT_rb_cr0_1[0:0] - attribute \src "libresoc.v:46070.3-46078.6" + attribute \src "libresoc.v:46118.3-46126.6" wire $0\dp_INT_rb_div0_4$next[0:0]$2548 - attribute \src "libresoc.v:42954.3-42955.49" + attribute \src "libresoc.v:43002.3-43003.49" wire $0\dp_INT_rb_div0_4[0:0] - attribute \src "libresoc.v:46127.3-46135.6" + attribute \src "libresoc.v:46175.3-46183.6" wire $0\dp_INT_rb_ldst0_7$next[0:0]$2566 - attribute \src "libresoc.v:42948.3-42949.51" + attribute \src "libresoc.v:42996.3-42997.51" wire $0\dp_INT_rb_ldst0_7[0:0] - attribute \src "libresoc.v:46051.3-46059.6" + attribute \src "libresoc.v:46099.3-46107.6" wire $0\dp_INT_rb_logical0_3$next[0:0]$2542 - attribute \src "libresoc.v:42956.3-42957.57" + attribute \src "libresoc.v:43004.3-43005.57" wire $0\dp_INT_rb_logical0_3[0:0] - attribute \src "libresoc.v:46089.3-46097.6" + attribute \src "libresoc.v:46137.3-46145.6" wire $0\dp_INT_rb_mul0_5$next[0:0]$2554 - attribute \src "libresoc.v:42952.3-42953.49" + attribute \src "libresoc.v:43000.3-43001.49" wire $0\dp_INT_rb_mul0_5[0:0] - attribute \src "libresoc.v:46108.3-46116.6" + attribute \src "libresoc.v:46156.3-46164.6" wire $0\dp_INT_rb_shiftrot0_6$next[0:0]$2560 - attribute \src "libresoc.v:42950.3-42951.59" + attribute \src "libresoc.v:42998.3-42999.59" wire $0\dp_INT_rb_shiftrot0_6[0:0] - attribute \src "libresoc.v:46032.3-46040.6" + attribute \src "libresoc.v:46080.3-46088.6" wire $0\dp_INT_rb_trap0_2$next[0:0]$2536 - attribute \src "libresoc.v:42958.3-42959.51" + attribute \src "libresoc.v:43006.3-43007.51" wire $0\dp_INT_rb_trap0_2[0:0] - attribute \src "libresoc.v:46165.3-46173.6" + attribute \src "libresoc.v:46213.3-46221.6" wire $0\dp_INT_rc_ldst0_1$next[0:0]$2576 - attribute \src "libresoc.v:42944.3-42945.51" + attribute \src "libresoc.v:42992.3-42993.51" wire $0\dp_INT_rc_ldst0_1[0:0] - attribute \src "libresoc.v:46146.3-46154.6" + attribute \src "libresoc.v:46194.3-46202.6" wire $0\dp_INT_rc_shiftrot0_0$next[0:0]$2572 - attribute \src "libresoc.v:42946.3-42947.59" + attribute \src "libresoc.v:42994.3-42995.59" wire $0\dp_INT_rc_shiftrot0_0[0:0] - attribute \src "libresoc.v:46791.3-46799.6" + attribute \src "libresoc.v:46843.3-46851.6" wire $0\dp_SPR_spr1_spr0_0$next[0:0]$2711 - attribute \src "libresoc.v:42902.3-42903.53" + attribute \src "libresoc.v:42950.3-42951.53" wire $0\dp_SPR_spr1_spr0_0[0:0] - attribute \src "libresoc.v:46298.3-46306.6" + attribute \src "libresoc.v:46346.3-46354.6" wire $0\dp_XER_xer_ca_alu0_0$next[0:0]$2616 - attribute \src "libresoc.v:42930.3-42931.57" + attribute \src "libresoc.v:42978.3-42979.57" wire $0\dp_XER_xer_ca_alu0_0[0:0] - attribute \src "libresoc.v:46336.3-46344.6" + attribute \src "libresoc.v:46384.3-46392.6" wire $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2626 - attribute \src "libresoc.v:42926.3-42927.67" + attribute \src "libresoc.v:42974.3-42975.67" wire $0\dp_XER_xer_ca_shiftrot0_2[0:0] - attribute \src "libresoc.v:46317.3-46325.6" + attribute \src "libresoc.v:46365.3-46373.6" wire $0\dp_XER_xer_ca_spr0_1$next[0:0]$2622 - attribute \src "libresoc.v:42928.3-42929.57" + attribute \src "libresoc.v:42976.3-42977.57" wire $0\dp_XER_xer_ca_spr0_1[0:0] - attribute \src "libresoc.v:46355.3-46363.6" + attribute \src "libresoc.v:46403.3-46411.6" wire $0\dp_XER_xer_ov_spr0_0$next[0:0]$2630 - attribute \src "libresoc.v:42924.3-42925.57" + attribute \src "libresoc.v:42972.3-42973.57" wire $0\dp_XER_xer_ov_spr0_0[0:0] - attribute \src "libresoc.v:46184.3-46192.6" + attribute \src "libresoc.v:46232.3-46240.6" wire $0\dp_XER_xer_so_alu0_0$next[0:0]$2582 - attribute \src "libresoc.v:42942.3-42943.57" + attribute \src "libresoc.v:42990.3-42991.57" wire $0\dp_XER_xer_so_alu0_0[0:0] - attribute \src "libresoc.v:46241.3-46249.6" + attribute \src "libresoc.v:46289.3-46297.6" wire $0\dp_XER_xer_so_div0_3$next[0:0]$2598 - attribute \src "libresoc.v:42936.3-42937.57" + attribute \src "libresoc.v:42984.3-42985.57" wire $0\dp_XER_xer_so_div0_3[0:0] - attribute \src "libresoc.v:46203.3-46211.6" + attribute \src "libresoc.v:46251.3-46259.6" wire $0\dp_XER_xer_so_logical0_1$next[0:0]$2588 - attribute \src "libresoc.v:42940.3-42941.65" + attribute \src "libresoc.v:42988.3-42989.65" wire $0\dp_XER_xer_so_logical0_1[0:0] - attribute \src "libresoc.v:46260.3-46268.6" + attribute \src "libresoc.v:46308.3-46316.6" wire $0\dp_XER_xer_so_mul0_4$next[0:0]$2604 - attribute \src "libresoc.v:42934.3-42935.57" + attribute \src "libresoc.v:42982.3-42983.57" wire $0\dp_XER_xer_so_mul0_4[0:0] - attribute \src "libresoc.v:46279.3-46287.6" + attribute \src "libresoc.v:46327.3-46335.6" wire $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2610 - attribute \src "libresoc.v:42932.3-42933.67" + attribute \src "libresoc.v:42980.3-42981.67" wire $0\dp_XER_xer_so_shiftrot0_5[0:0] - attribute \src "libresoc.v:46222.3-46230.6" + attribute \src "libresoc.v:46270.3-46278.6" wire $0\dp_XER_xer_so_spr0_2$next[0:0]$2594 - attribute \src "libresoc.v:42938.3-42939.57" + attribute \src "libresoc.v:42986.3-42987.57" wire $0\dp_XER_xer_so_spr0_2[0:0] - attribute \src "libresoc.v:47566.3-47594.6" + attribute \src "libresoc.v:47618.3-47646.6" wire $0\fus_cu_issue_i$13[0:0]$2821 - attribute \src "libresoc.v:47900.3-47928.6" + attribute \src "libresoc.v:47952.3-47980.6" wire $0\fus_cu_issue_i$16[0:0]$2862 - attribute \src "libresoc.v:48219.3-48247.6" + attribute \src "libresoc.v:48271.3-48299.6" wire $0\fus_cu_issue_i$19[0:0]$2881 - attribute \src "libresoc.v:43868.3-43896.6" + attribute \src "libresoc.v:43916.3-43944.6" wire $0\fus_cu_issue_i$22[0:0]$2359 - attribute \src "libresoc.v:44042.3-44070.6" + attribute \src "libresoc.v:44090.3-44118.6" wire $0\fus_cu_issue_i$25[0:0]$2373 - attribute \src "libresoc.v:44538.3-44566.6" + attribute \src "libresoc.v:44586.3-44614.6" wire $0\fus_cu_issue_i$28[0:0]$2398 - attribute \src "libresoc.v:44860.3-44888.6" + attribute \src "libresoc.v:44908.3-44936.6" wire $0\fus_cu_issue_i$31[0:0]$2417 - attribute \src "libresoc.v:45327.3-45355.6" + attribute \src "libresoc.v:45375.3-45403.6" wire $0\fus_cu_issue_i$34[0:0]$2441 - attribute \src "libresoc.v:45765.3-45793.6" + attribute \src "libresoc.v:45813.3-45841.6" wire $0\fus_cu_issue_i$37[0:0]$2464 - attribute \src "libresoc.v:47349.3-47377.6" + attribute \src "libresoc.v:47401.3-47429.6" wire $0\fus_cu_issue_i[0:0] - attribute \src "libresoc.v:47604.3-47632.6" + attribute \src "libresoc.v:47656.3-47684.6" wire width 6 $0\fus_cu_rdmaskn_i$15[5:0]$2829 - attribute \src "libresoc.v:47929.3-47957.6" + attribute \src "libresoc.v:47981.3-48009.6" wire width 3 $0\fus_cu_rdmaskn_i$18[2:0]$2867 - attribute \src "libresoc.v:48248.3-48276.6" + attribute \src "libresoc.v:48300.3-48328.6" wire width 4 $0\fus_cu_rdmaskn_i$21[3:0]$2886 - attribute \src "libresoc.v:43897.3-43925.6" + attribute \src "libresoc.v:43945.3-43973.6" wire width 3 $0\fus_cu_rdmaskn_i$24[2:0]$2364 - attribute \src "libresoc.v:44071.3-44099.6" + attribute \src "libresoc.v:44119.3-44147.6" wire width 6 $0\fus_cu_rdmaskn_i$27[5:0]$2378 - attribute \src "libresoc.v:44567.3-44595.6" + attribute \src "libresoc.v:44615.3-44643.6" wire width 3 $0\fus_cu_rdmaskn_i$30[2:0]$2403 - attribute \src "libresoc.v:44889.3-44917.6" + attribute \src "libresoc.v:44937.3-44965.6" wire width 3 $0\fus_cu_rdmaskn_i$33[2:0]$2422 - attribute \src "libresoc.v:45356.3-45384.6" + attribute \src "libresoc.v:45404.3-45432.6" wire width 5 $0\fus_cu_rdmaskn_i$36[4:0]$2446 - attribute \src "libresoc.v:45794.3-45822.6" + attribute \src "libresoc.v:45842.3-45870.6" wire width 3 $0\fus_cu_rdmaskn_i$39[2:0]$2469 - attribute \src "libresoc.v:47396.3-47424.6" + attribute \src "libresoc.v:47448.3-47476.6" wire width 4 $0\fus_cu_rdmaskn_i[3:0] - attribute \src "libresoc.v:47273.3-47301.6" + attribute \src "libresoc.v:47325.3-47353.6" wire width 4 $0\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "libresoc.v:46694.3-46722.6" + attribute \src "libresoc.v:46746.3-46774.6" wire width 14 $0\fus_oper_i_alu_alu0__fn_unit[13:0] - attribute \src "libresoc.v:46761.3-46790.6" + attribute \src "libresoc.v:46813.3-46842.6" wire width 64 $0\fus_oper_i_alu_alu0__imm_data__data[63:0] - attribute \src "libresoc.v:46761.3-46790.6" + attribute \src "libresoc.v:46813.3-46842.6" wire $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "libresoc.v:47094.3-47122.6" + attribute \src "libresoc.v:47146.3-47174.6" wire width 2 $0\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "libresoc.v:47311.3-47339.6" + attribute \src "libresoc.v:47363.3-47391.6" wire width 32 $0\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "libresoc.v:46646.3-46674.6" + attribute \src "libresoc.v:46698.3-46726.6" wire width 7 $0\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "libresoc.v:46933.3-46961.6" + attribute \src "libresoc.v:46985.3-47013.6" wire $0\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "libresoc.v:47018.3-47046.6" + attribute \src "libresoc.v:47070.3-47098.6" wire $0\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "libresoc.v:47188.3-47216.6" + attribute \src "libresoc.v:47240.3-47268.6" wire $0\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "libresoc.v:47226.3-47254.6" + attribute \src "libresoc.v:47278.3-47306.6" wire $0\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "libresoc.v:46876.3-46905.6" + attribute \src "libresoc.v:46928.3-46957.6" wire $0\fus_oper_i_alu_alu0__oe__oe[0:0] - attribute \src "libresoc.v:46876.3-46905.6" + attribute \src "libresoc.v:46928.3-46957.6" wire $0\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "libresoc.v:47141.3-47169.6" + attribute \src "libresoc.v:47193.3-47221.6" wire $0\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "libresoc.v:46828.3-46857.6" + attribute \src "libresoc.v:46880.3-46909.6" wire $0\fus_oper_i_alu_alu0__rc__ok[0:0] - attribute \src "libresoc.v:46828.3-46857.6" + attribute \src "libresoc.v:46880.3-46909.6" wire $0\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "libresoc.v:47056.3-47084.6" + attribute \src "libresoc.v:47108.3-47136.6" wire $0\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "libresoc.v:46980.3-47008.6" + attribute \src "libresoc.v:47032.3-47060.6" wire $0\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "libresoc.v:47651.3-47679.6" + attribute \src "libresoc.v:47703.3-47731.6" wire width 64 $0\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "libresoc.v:47736.3-47764.6" + attribute \src "libresoc.v:47788.3-47816.6" wire width 14 $0\fus_oper_i_alu_branch0__fn_unit[13:0] - attribute \src "libresoc.v:47812.3-47841.6" + attribute \src "libresoc.v:47864.3-47893.6" wire width 64 $0\fus_oper_i_alu_branch0__imm_data__data[63:0] - attribute \src "libresoc.v:47812.3-47841.6" + attribute \src "libresoc.v:47864.3-47893.6" wire $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "libresoc.v:47774.3-47802.6" + attribute \src "libresoc.v:47826.3-47854.6" wire width 32 $0\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "libresoc.v:47689.3-47717.6" + attribute \src "libresoc.v:47741.3-47769.6" wire width 7 $0\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "libresoc.v:47871.3-47899.6" + attribute \src "libresoc.v:47923.3-47951.6" wire $0\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "libresoc.v:47842.3-47870.6" + attribute \src "libresoc.v:47894.3-47922.6" wire $0\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "libresoc.v:47481.3-47509.6" + attribute \src "libresoc.v:47533.3-47561.6" wire width 14 $0\fus_oper_i_alu_cr0__fn_unit[13:0] - attribute \src "libresoc.v:47528.3-47556.6" + attribute \src "libresoc.v:47580.3-47608.6" wire width 32 $0\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "libresoc.v:47434.3-47462.6" + attribute \src "libresoc.v:47486.3-47514.6" wire width 7 $0\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "libresoc.v:44480.3-44508.6" + attribute \src "libresoc.v:44528.3-44556.6" wire width 4 $0\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "libresoc.v:44129.3-44157.6" + attribute \src "libresoc.v:44177.3-44205.6" wire width 14 $0\fus_oper_i_alu_div0__fn_unit[13:0] - attribute \src "libresoc.v:44158.3-44187.6" + attribute \src "libresoc.v:44206.3-44235.6" wire width 64 $0\fus_oper_i_alu_div0__imm_data__data[63:0] - attribute \src "libresoc.v:44158.3-44187.6" + attribute \src "libresoc.v:44206.3-44235.6" wire $0\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "libresoc.v:44306.3-44334.6" + attribute \src "libresoc.v:44354.3-44382.6" wire width 2 $0\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "libresoc.v:44509.3-44537.6" + attribute \src "libresoc.v:44557.3-44585.6" wire width 32 $0\fus_oper_i_alu_div0__insn[31:0] - attribute \src "libresoc.v:44100.3-44128.6" + attribute \src "libresoc.v:44148.3-44176.6" wire width 7 $0\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "libresoc.v:44248.3-44276.6" + attribute \src "libresoc.v:44296.3-44324.6" wire $0\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "libresoc.v:44335.3-44363.6" + attribute \src "libresoc.v:44383.3-44411.6" wire $0\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "libresoc.v:44422.3-44450.6" + attribute \src "libresoc.v:44470.3-44498.6" wire $0\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "libresoc.v:44451.3-44479.6" + attribute \src "libresoc.v:44499.3-44527.6" wire $0\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "libresoc.v:44218.3-44247.6" + attribute \src "libresoc.v:44266.3-44295.6" wire $0\fus_oper_i_alu_div0__oe__oe[0:0] - attribute \src "libresoc.v:44218.3-44247.6" + attribute \src "libresoc.v:44266.3-44295.6" wire $0\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "libresoc.v:44393.3-44421.6" + attribute \src "libresoc.v:44441.3-44469.6" wire $0\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "libresoc.v:44188.3-44217.6" + attribute \src "libresoc.v:44236.3-44265.6" wire $0\fus_oper_i_alu_div0__rc__ok[0:0] - attribute \src "libresoc.v:44188.3-44217.6" + attribute \src "libresoc.v:44236.3-44265.6" wire $0\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "libresoc.v:44364.3-44392.6" + attribute \src "libresoc.v:44412.3-44440.6" wire $0\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "libresoc.v:44277.3-44305.6" + attribute \src "libresoc.v:44325.3-44353.6" wire $0\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "libresoc.v:43810.3-43838.6" + attribute \src "libresoc.v:43858.3-43886.6" wire width 4 $0\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "libresoc.v:48306.3-48334.6" + attribute \src "libresoc.v:48358.3-48386.6" wire width 14 $0\fus_oper_i_alu_logical0__fn_unit[13:0] - attribute \src "libresoc.v:48335.3-48364.6" + attribute \src "libresoc.v:48387.3-48416.6" wire width 64 $0\fus_oper_i_alu_logical0__imm_data__data[63:0] - attribute \src "libresoc.v:48335.3-48364.6" + attribute \src "libresoc.v:48387.3-48416.6" wire $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "libresoc.v:48483.3-48511.6" + attribute \src "libresoc.v:48535.3-48563.6" wire width 2 $0\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "libresoc.v:43839.3-43867.6" + attribute \src "libresoc.v:43887.3-43915.6" wire width 32 $0\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "libresoc.v:48277.3-48305.6" + attribute \src "libresoc.v:48329.3-48357.6" wire width 7 $0\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "libresoc.v:48425.3-48453.6" + attribute \src "libresoc.v:48477.3-48505.6" wire $0\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "libresoc.v:48512.3-48540.6" + attribute \src "libresoc.v:48564.3-48592.6" wire $0\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "libresoc.v:43752.3-43780.6" + attribute \src "libresoc.v:43800.3-43828.6" wire $0\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "libresoc.v:43781.3-43809.6" + attribute \src "libresoc.v:43829.3-43857.6" wire $0\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "libresoc.v:48395.3-48424.6" + attribute \src "libresoc.v:48447.3-48476.6" wire $0\fus_oper_i_alu_logical0__oe__oe[0:0] - attribute \src "libresoc.v:48395.3-48424.6" + attribute \src "libresoc.v:48447.3-48476.6" wire $0\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "libresoc.v:43723.3-43751.6" + attribute \src "libresoc.v:43771.3-43799.6" wire $0\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "libresoc.v:48365.3-48394.6" + attribute \src "libresoc.v:48417.3-48446.6" wire $0\fus_oper_i_alu_logical0__rc__ok[0:0] - attribute \src "libresoc.v:48365.3-48394.6" + attribute \src "libresoc.v:48417.3-48446.6" wire $0\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "libresoc.v:48541.3-48569.6" + attribute \src "libresoc.v:48593.3-48621.6" wire $0\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "libresoc.v:48454.3-48482.6" + attribute \src "libresoc.v:48506.3-48534.6" wire $0\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "libresoc.v:44625.3-44653.6" + attribute \src "libresoc.v:44673.3-44701.6" wire width 14 $0\fus_oper_i_alu_mul0__fn_unit[13:0] - attribute \src "libresoc.v:44654.3-44683.6" + attribute \src "libresoc.v:44702.3-44731.6" wire width 64 $0\fus_oper_i_alu_mul0__imm_data__data[63:0] - attribute \src "libresoc.v:44654.3-44683.6" + attribute \src "libresoc.v:44702.3-44731.6" wire $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "libresoc.v:44831.3-44859.6" + attribute \src "libresoc.v:44879.3-44907.6" wire width 32 $0\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "libresoc.v:44596.3-44624.6" + attribute \src "libresoc.v:44644.3-44672.6" wire width 7 $0\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "libresoc.v:44773.3-44801.6" + attribute \src "libresoc.v:44821.3-44849.6" wire $0\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "libresoc.v:44802.3-44830.6" + attribute \src "libresoc.v:44850.3-44878.6" wire $0\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "libresoc.v:44714.3-44743.6" + attribute \src "libresoc.v:44762.3-44791.6" wire $0\fus_oper_i_alu_mul0__oe__oe[0:0] - attribute \src "libresoc.v:44714.3-44743.6" + attribute \src "libresoc.v:44762.3-44791.6" wire $0\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "libresoc.v:44684.3-44713.6" + attribute \src "libresoc.v:44732.3-44761.6" wire $0\fus_oper_i_alu_mul0__rc__ok[0:0] - attribute \src "libresoc.v:44684.3-44713.6" + attribute \src "libresoc.v:44732.3-44761.6" wire $0\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "libresoc.v:44744.3-44772.6" + attribute \src "libresoc.v:44792.3-44820.6" wire $0\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "libresoc.v:44947.3-44975.6" + attribute \src "libresoc.v:44995.3-45023.6" wire width 14 $0\fus_oper_i_alu_shift_rot0__fn_unit[13:0] - attribute \src "libresoc.v:44976.3-45005.6" + attribute \src "libresoc.v:45024.3-45053.6" wire width 64 $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] - attribute \src "libresoc.v:44976.3-45005.6" + attribute \src "libresoc.v:45024.3-45053.6" wire $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "libresoc.v:45124.3-45152.6" + attribute \src "libresoc.v:45172.3-45200.6" wire width 2 $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "libresoc.v:45182.3-45210.6" + attribute \src "libresoc.v:45230.3-45258.6" wire $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "libresoc.v:45298.3-45326.6" + attribute \src "libresoc.v:45346.3-45374.6" wire width 32 $0\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "libresoc.v:44918.3-44946.6" + attribute \src "libresoc.v:44966.3-44994.6" wire width 7 $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "libresoc.v:45095.3-45123.6" + attribute \src "libresoc.v:45143.3-45171.6" wire $0\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "libresoc.v:45240.3-45268.6" + attribute \src "libresoc.v:45288.3-45316.6" wire $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "libresoc.v:45269.3-45297.6" + attribute \src "libresoc.v:45317.3-45345.6" wire $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "libresoc.v:45036.3-45065.6" + attribute \src "libresoc.v:45084.3-45113.6" wire $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] - attribute \src "libresoc.v:45036.3-45065.6" + attribute \src "libresoc.v:45084.3-45113.6" wire $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "libresoc.v:45153.3-45181.6" + attribute \src "libresoc.v:45201.3-45229.6" wire $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "libresoc.v:45211.3-45239.6" + attribute \src "libresoc.v:45259.3-45287.6" wire $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "libresoc.v:45006.3-45035.6" + attribute \src "libresoc.v:45054.3-45083.6" wire $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] - attribute \src "libresoc.v:45006.3-45035.6" + attribute \src "libresoc.v:45054.3-45083.6" wire $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "libresoc.v:45066.3-45094.6" + attribute \src "libresoc.v:45114.3-45142.6" wire $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "libresoc.v:43955.3-43983.6" + attribute \src "libresoc.v:44003.3-44031.6" wire width 14 $0\fus_oper_i_alu_spr0__fn_unit[13:0] - attribute \src "libresoc.v:43984.3-44012.6" + attribute \src "libresoc.v:44032.3-44060.6" wire width 32 $0\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "libresoc.v:43926.3-43954.6" + attribute \src "libresoc.v:43974.3-44002.6" wire width 7 $0\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "libresoc.v:44013.3-44041.6" + attribute \src "libresoc.v:44061.3-44089.6" wire $0\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "libresoc.v:48074.3-48102.6" + attribute \src "libresoc.v:48126.3-48154.6" wire width 64 $0\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "libresoc.v:47987.3-48015.6" + attribute \src "libresoc.v:48039.3-48067.6" wire width 14 $0\fus_oper_i_alu_trap0__fn_unit[13:0] - attribute \src "libresoc.v:48016.3-48044.6" + attribute \src "libresoc.v:48068.3-48096.6" wire width 32 $0\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "libresoc.v:47958.3-47986.6" + attribute \src "libresoc.v:48010.3-48038.6" wire width 7 $0\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "libresoc.v:48103.3-48131.6" + attribute \src "libresoc.v:48155.3-48183.6" wire $0\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "libresoc.v:48190.3-48218.6" + attribute \src "libresoc.v:48242.3-48270.6" wire width 8 $0\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "libresoc.v:48045.3-48073.6" + attribute \src "libresoc.v:48097.3-48125.6" wire width 64 $0\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "libresoc.v:48161.3-48189.6" + attribute \src "libresoc.v:48213.3-48241.6" wire width 13 $0\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "libresoc.v:48132.3-48160.6" + attribute \src "libresoc.v:48184.3-48212.6" wire width 8 $0\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "libresoc.v:45649.3-45677.6" + attribute \src "libresoc.v:45697.3-45725.6" wire $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "libresoc.v:45620.3-45648.6" + attribute \src "libresoc.v:45668.3-45696.6" wire width 4 $0\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "libresoc.v:45414.3-45442.6" + attribute \src "libresoc.v:45462.3-45490.6" wire width 14 $0\fus_oper_i_ldst_ldst0__fn_unit[13:0] - attribute \src "libresoc.v:45443.3-45472.6" + attribute \src "libresoc.v:45491.3-45520.6" wire width 64 $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] - attribute \src "libresoc.v:45443.3-45472.6" + attribute \src "libresoc.v:45491.3-45520.6" wire $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "libresoc.v:45736.3-45764.6" + attribute \src "libresoc.v:45784.3-45812.6" wire width 32 $0\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "libresoc.v:45385.3-45413.6" + attribute \src "libresoc.v:45433.3-45461.6" wire width 7 $0\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "libresoc.v:45562.3-45590.6" + attribute \src "libresoc.v:45610.3-45638.6" wire $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "libresoc.v:45591.3-45619.6" + attribute \src "libresoc.v:45639.3-45667.6" wire $0\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "libresoc.v:45707.3-45735.6" + attribute \src "libresoc.v:45755.3-45783.6" wire width 2 $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "libresoc.v:45532.3-45561.6" + attribute \src "libresoc.v:45580.3-45609.6" wire $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] - attribute \src "libresoc.v:45532.3-45561.6" + attribute \src "libresoc.v:45580.3-45609.6" wire $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "libresoc.v:45502.3-45531.6" + attribute \src "libresoc.v:45550.3-45579.6" wire $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] - attribute \src "libresoc.v:45502.3-45531.6" + attribute \src "libresoc.v:45550.3-45579.6" wire $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "libresoc.v:45678.3-45706.6" + attribute \src "libresoc.v:45726.3-45754.6" wire $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "libresoc.v:45473.3-45501.6" + attribute \src "libresoc.v:45521.3-45549.6" wire $0\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "libresoc.v:45851.3-45860.6" + attribute \src "libresoc.v:45899.3-45908.6" wire width 64 $0\fus_src1_i$42[63:0]$2481 - attribute \src "libresoc.v:45870.3-45879.6" + attribute \src "libresoc.v:45918.3-45927.6" wire width 64 $0\fus_src1_i$45[63:0]$2487 - attribute \src "libresoc.v:45889.3-45898.6" + attribute \src "libresoc.v:45937.3-45946.6" wire width 64 $0\fus_src1_i$48[63:0]$2493 - attribute \src "libresoc.v:45908.3-45917.6" + attribute \src "libresoc.v:45956.3-45965.6" wire width 64 $0\fus_src1_i$51[63:0]$2499 - attribute \src "libresoc.v:45927.3-45936.6" + attribute \src "libresoc.v:45975.3-45984.6" wire width 64 $0\fus_src1_i$54[63:0]$2505 - attribute \src "libresoc.v:45946.3-45955.6" + attribute \src "libresoc.v:45994.3-46003.6" wire width 64 $0\fus_src1_i$57[63:0]$2511 - attribute \src "libresoc.v:45965.3-45974.6" + attribute \src "libresoc.v:46013.3-46022.6" wire width 64 $0\fus_src1_i$60[63:0]$2517 - attribute \src "libresoc.v:45984.3-45993.6" + attribute \src "libresoc.v:46032.3-46041.6" wire width 64 $0\fus_src1_i$63[63:0]$2523 - attribute \src "libresoc.v:46617.3-46626.6" + attribute \src "libresoc.v:46669.3-46678.6" wire width 64 $0\fus_src1_i$86[63:0]$2681 - attribute \src "libresoc.v:45832.3-45841.6" + attribute \src "libresoc.v:45880.3-45889.6" wire width 64 $0\fus_src1_i[63:0] - attribute \src "libresoc.v:46022.3-46031.6" + attribute \src "libresoc.v:46070.3-46079.6" wire width 64 $0\fus_src2_i$64[63:0]$2533 - attribute \src "libresoc.v:46041.3-46050.6" + attribute \src "libresoc.v:46089.3-46098.6" wire width 64 $0\fus_src2_i$65[63:0]$2539 - attribute \src "libresoc.v:46060.3-46069.6" + attribute \src "libresoc.v:46108.3-46117.6" wire width 64 $0\fus_src2_i$66[63:0]$2545 - attribute \src "libresoc.v:46079.3-46088.6" + attribute \src "libresoc.v:46127.3-46136.6" wire width 64 $0\fus_src2_i$67[63:0]$2551 - attribute \src "libresoc.v:46098.3-46107.6" + attribute \src "libresoc.v:46146.3-46155.6" wire width 64 $0\fus_src2_i$68[63:0]$2557 - attribute \src "libresoc.v:46117.3-46126.6" + attribute \src "libresoc.v:46165.3-46174.6" wire width 64 $0\fus_src2_i$69[63:0]$2563 - attribute \src "libresoc.v:46136.3-46145.6" + attribute \src "libresoc.v:46184.3-46193.6" wire width 64 $0\fus_src2_i$70[63:0]$2569 - attribute \src "libresoc.v:46732.3-46741.6" + attribute \src "libresoc.v:46784.3-46793.6" wire width 64 $0\fus_src2_i$89[63:0]$2701 - attribute \src "libresoc.v:46800.3-46809.6" + attribute \src "libresoc.v:46852.3-46861.6" wire width 64 $0\fus_src2_i$91[63:0]$2714 - attribute \src "libresoc.v:46003.3-46012.6" + attribute \src "libresoc.v:46051.3-46060.6" wire width 64 $0\fus_src2_i[63:0] - attribute \src "libresoc.v:46174.3-46183.6" + attribute \src "libresoc.v:46222.3-46231.6" wire width 64 $0\fus_src3_i$71[63:0]$2579 - attribute \src "libresoc.v:46193.3-46202.6" + attribute \src "libresoc.v:46241.3-46250.6" wire $0\fus_src3_i$72[0:0]$2585 - attribute \src "libresoc.v:46212.3-46221.6" + attribute \src "libresoc.v:46260.3-46269.6" wire $0\fus_src3_i$73[0:0]$2591 - attribute \src "libresoc.v:46250.3-46259.6" + attribute \src "libresoc.v:46298.3-46307.6" wire $0\fus_src3_i$74[0:0]$2601 - attribute \src "libresoc.v:46269.3-46278.6" + attribute \src "libresoc.v:46317.3-46326.6" wire $0\fus_src3_i$75[0:0]$2607 - attribute \src "libresoc.v:46383.3-46392.6" + attribute \src "libresoc.v:46431.3-46440.6" wire width 32 $0\fus_src3_i$79[31:0]$2639 - attribute \src "libresoc.v:46421.3-46430.6" + attribute \src "libresoc.v:46469.3-46478.6" wire width 4 $0\fus_src3_i$83[3:0]$2651 - attribute \src "libresoc.v:46636.3-46645.6" + attribute \src "libresoc.v:46688.3-46697.6" wire width 64 $0\fus_src3_i$87[63:0]$2687 - attribute \src "libresoc.v:46684.3-46693.6" + attribute \src "libresoc.v:46736.3-46745.6" wire width 64 $0\fus_src3_i$88[63:0]$2694 - attribute \src "libresoc.v:46155.3-46164.6" + attribute \src "libresoc.v:46203.3-46212.6" wire width 64 $0\fus_src3_i[63:0] - attribute \src "libresoc.v:46288.3-46297.6" + attribute \src "libresoc.v:46336.3-46345.6" wire $0\fus_src4_i$76[0:0]$2613 - attribute \src "libresoc.v:46307.3-46316.6" + attribute \src "libresoc.v:46355.3-46364.6" wire width 2 $0\fus_src4_i$77[1:0]$2619 - attribute \src "libresoc.v:46402.3-46411.6" + attribute \src "libresoc.v:46450.3-46459.6" wire width 4 $0\fus_src4_i$80[3:0]$2645 - attribute \src "libresoc.v:46751.3-46760.6" + attribute \src "libresoc.v:46803.3-46812.6" wire width 64 $0\fus_src4_i$90[63:0]$2707 - attribute \src "libresoc.v:46231.3-46240.6" + attribute \src "libresoc.v:46279.3-46288.6" wire $0\fus_src4_i[0:0] - attribute \src "libresoc.v:46364.3-46373.6" + attribute \src "libresoc.v:46412.3-46421.6" wire width 2 $0\fus_src5_i$78[1:0]$2633 - attribute \src "libresoc.v:46467.3-46476.6" + attribute \src "libresoc.v:46519.3-46528.6" wire width 4 $0\fus_src5_i$84[3:0]$2663 - attribute \src "libresoc.v:46345.3-46354.6" + attribute \src "libresoc.v:46393.3-46402.6" wire width 2 $0\fus_src5_i[1:0] - attribute \src "libresoc.v:46577.3-46586.6" + attribute \src "libresoc.v:46629.3-46638.6" wire width 4 $0\fus_src6_i$85[3:0]$2670 - attribute \src "libresoc.v:46326.3-46335.6" + attribute \src "libresoc.v:46374.3-46383.6" wire width 2 $0\fus_src6_i[1:0] - attribute \src "libresoc.v:36214.7-36214.20" + attribute \src "libresoc.v:36262.7-36262.20" wire $0\initial[0:0] - attribute \src "libresoc.v:46858.3-46866.6" + attribute \src "libresoc.v:46910.3-46918.6" wire $0\wr_pick_dly$1010$next[0:0]$2724 - attribute \src "libresoc.v:42896.3-42897.51" + attribute \src "libresoc.v:42944.3-42945.51" wire $0\wr_pick_dly$1010[0:0]$2307 - attribute \src "libresoc.v:41726.7-41726.32" + attribute \src "libresoc.v:41774.7-41774.32" wire $0\wr_pick_dly$1010[0:0]$2945 - attribute \src "libresoc.v:46867.3-46875.6" + attribute \src "libresoc.v:46919.3-46927.6" wire $0\wr_pick_dly$1031$next[0:0]$2727 - attribute \src "libresoc.v:42894.3-42895.51" + attribute \src "libresoc.v:42942.3-42943.51" wire $0\wr_pick_dly$1031[0:0]$2305 - attribute \src "libresoc.v:41730.7-41730.32" + attribute \src "libresoc.v:41778.7-41778.32" wire $0\wr_pick_dly$1031[0:0]$2947 - attribute \src "libresoc.v:46906.3-46914.6" + attribute \src "libresoc.v:46958.3-46966.6" wire $0\wr_pick_dly$1049$next[0:0]$2731 - attribute \src "libresoc.v:42892.3-42893.51" + attribute \src "libresoc.v:42940.3-42941.51" wire $0\wr_pick_dly$1049[0:0]$2303 - attribute \src "libresoc.v:41734.7-41734.32" + attribute \src "libresoc.v:41782.7-41782.32" wire $0\wr_pick_dly$1049[0:0]$2949 - attribute \src "libresoc.v:46915.3-46923.6" + attribute \src "libresoc.v:46967.3-46975.6" wire $0\wr_pick_dly$1071$next[0:0]$2734 - attribute \src "libresoc.v:42890.3-42891.51" + attribute \src "libresoc.v:42938.3-42939.51" wire $0\wr_pick_dly$1071[0:0]$2301 - attribute \src "libresoc.v:41738.7-41738.32" + attribute \src "libresoc.v:41786.7-41786.32" wire $0\wr_pick_dly$1071[0:0]$2951 - attribute \src "libresoc.v:46924.3-46932.6" + attribute \src "libresoc.v:46976.3-46984.6" wire $0\wr_pick_dly$1091$next[0:0]$2737 - attribute \src "libresoc.v:42888.3-42889.51" + attribute \src "libresoc.v:42936.3-42937.51" wire $0\wr_pick_dly$1091[0:0]$2299 - attribute \src "libresoc.v:41742.7-41742.32" + attribute \src "libresoc.v:41790.7-41790.32" wire $0\wr_pick_dly$1091[0:0]$2953 - attribute \src "libresoc.v:46962.3-46970.6" + attribute \src "libresoc.v:47014.3-47022.6" wire $0\wr_pick_dly$1111$next[0:0]$2741 - attribute \src "libresoc.v:42886.3-42887.51" + attribute \src "libresoc.v:42934.3-42935.51" wire $0\wr_pick_dly$1111[0:0]$2297 - attribute \src "libresoc.v:41746.7-41746.32" + attribute \src "libresoc.v:41794.7-41794.32" wire $0\wr_pick_dly$1111[0:0]$2955 - attribute \src "libresoc.v:46971.3-46979.6" + attribute \src "libresoc.v:47023.3-47031.6" wire $0\wr_pick_dly$1130$next[0:0]$2744 - attribute \src "libresoc.v:42884.3-42885.51" + attribute \src "libresoc.v:42932.3-42933.51" wire $0\wr_pick_dly$1130[0:0]$2295 - attribute \src "libresoc.v:41750.7-41750.32" + attribute \src "libresoc.v:41798.7-41798.32" wire $0\wr_pick_dly$1130[0:0]$2957 - attribute \src "libresoc.v:47009.3-47017.6" + attribute \src "libresoc.v:47061.3-47069.6" wire $0\wr_pick_dly$1148$next[0:0]$2748 - attribute \src "libresoc.v:42882.3-42883.51" + attribute \src "libresoc.v:42930.3-42931.51" wire $0\wr_pick_dly$1148[0:0]$2293 - attribute \src "libresoc.v:41754.7-41754.32" + attribute \src "libresoc.v:41802.7-41802.32" wire $0\wr_pick_dly$1148[0:0]$2959 - attribute \src "libresoc.v:47047.3-47055.6" + attribute \src "libresoc.v:47099.3-47107.6" wire $0\wr_pick_dly$1222$next[0:0]$2752 - attribute \src "libresoc.v:42880.3-42881.51" + attribute \src "libresoc.v:42928.3-42929.51" wire $0\wr_pick_dly$1222[0:0]$2291 - attribute \src "libresoc.v:41758.7-41758.32" + attribute \src "libresoc.v:41806.7-41806.32" wire $0\wr_pick_dly$1222[0:0]$2961 - attribute \src "libresoc.v:47085.3-47093.6" + attribute \src "libresoc.v:47137.3-47145.6" wire $0\wr_pick_dly$1250$next[0:0]$2756 - attribute \src "libresoc.v:42878.3-42879.51" + attribute \src "libresoc.v:42926.3-42927.51" wire $0\wr_pick_dly$1250[0:0]$2289 - attribute \src "libresoc.v:41762.7-41762.32" + attribute \src "libresoc.v:41810.7-41810.32" wire $0\wr_pick_dly$1250[0:0]$2963 - attribute \src "libresoc.v:47123.3-47131.6" + attribute \src "libresoc.v:47175.3-47183.6" wire $0\wr_pick_dly$1270$next[0:0]$2760 - attribute \src "libresoc.v:42876.3-42877.51" + attribute \src "libresoc.v:42924.3-42925.51" wire $0\wr_pick_dly$1270[0:0]$2287 - attribute \src "libresoc.v:41766.7-41766.32" + attribute \src "libresoc.v:41814.7-41814.32" wire $0\wr_pick_dly$1270[0:0]$2965 - attribute \src "libresoc.v:47132.3-47140.6" + attribute \src "libresoc.v:47184.3-47192.6" wire $0\wr_pick_dly$1290$next[0:0]$2763 - attribute \src "libresoc.v:42874.3-42875.51" + attribute \src "libresoc.v:42922.3-42923.51" wire $0\wr_pick_dly$1290[0:0]$2285 - attribute \src "libresoc.v:41770.7-41770.32" + attribute \src "libresoc.v:41818.7-41818.32" wire $0\wr_pick_dly$1290[0:0]$2967 - attribute \src "libresoc.v:47170.3-47178.6" + attribute \src "libresoc.v:47222.3-47230.6" wire $0\wr_pick_dly$1310$next[0:0]$2767 - attribute \src "libresoc.v:42872.3-42873.51" + attribute \src "libresoc.v:42920.3-42921.51" wire $0\wr_pick_dly$1310[0:0]$2283 - attribute \src "libresoc.v:41774.7-41774.32" + attribute \src "libresoc.v:41822.7-41822.32" wire $0\wr_pick_dly$1310[0:0]$2969 - attribute \src "libresoc.v:47179.3-47187.6" + attribute \src "libresoc.v:47231.3-47239.6" wire $0\wr_pick_dly$1330$next[0:0]$2770 - attribute \src "libresoc.v:42870.3-42871.51" + attribute \src "libresoc.v:42918.3-42919.51" wire $0\wr_pick_dly$1330[0:0]$2281 - attribute \src "libresoc.v:41778.7-41778.32" + attribute \src "libresoc.v:41826.7-41826.32" wire $0\wr_pick_dly$1330[0:0]$2971 - attribute \src "libresoc.v:47217.3-47225.6" + attribute \src "libresoc.v:47269.3-47277.6" wire $0\wr_pick_dly$1350$next[0:0]$2774 - attribute \src "libresoc.v:42868.3-42869.51" + attribute \src "libresoc.v:42916.3-42917.51" wire $0\wr_pick_dly$1350[0:0]$2279 - attribute \src "libresoc.v:41782.7-41782.32" + attribute \src "libresoc.v:41830.7-41830.32" wire $0\wr_pick_dly$1350[0:0]$2973 - attribute \src "libresoc.v:47255.3-47263.6" + attribute \src "libresoc.v:47307.3-47315.6" wire $0\wr_pick_dly$1397$next[0:0]$2778 - attribute \src "libresoc.v:42866.3-42867.51" + attribute \src "libresoc.v:42914.3-42915.51" wire $0\wr_pick_dly$1397[0:0]$2277 - attribute \src "libresoc.v:41786.7-41786.32" + attribute \src "libresoc.v:41834.7-41834.32" wire $0\wr_pick_dly$1397[0:0]$2975 - attribute \src "libresoc.v:47264.3-47272.6" + attribute \src "libresoc.v:47316.3-47324.6" wire $0\wr_pick_dly$1413$next[0:0]$2781 - attribute \src "libresoc.v:42864.3-42865.51" + attribute \src "libresoc.v:42912.3-42913.51" wire $0\wr_pick_dly$1413[0:0]$2275 - attribute \src "libresoc.v:41790.7-41790.32" + attribute \src "libresoc.v:41838.7-41838.32" wire $0\wr_pick_dly$1413[0:0]$2977 - attribute \src "libresoc.v:47302.3-47310.6" + attribute \src "libresoc.v:47354.3-47362.6" wire $0\wr_pick_dly$1429$next[0:0]$2785 - attribute \src "libresoc.v:42862.3-42863.51" + attribute \src "libresoc.v:42910.3-42911.51" wire $0\wr_pick_dly$1429[0:0]$2273 - attribute \src "libresoc.v:41794.7-41794.32" + attribute \src "libresoc.v:41842.7-41842.32" wire $0\wr_pick_dly$1429[0:0]$2979 - attribute \src "libresoc.v:47340.3-47348.6" + attribute \src "libresoc.v:47392.3-47400.6" wire $0\wr_pick_dly$1463$next[0:0]$2789 - attribute \src "libresoc.v:42860.3-42861.51" + attribute \src "libresoc.v:42908.3-42909.51" wire $0\wr_pick_dly$1463[0:0]$2271 - attribute \src "libresoc.v:41798.7-41798.32" + attribute \src "libresoc.v:41846.7-41846.32" wire $0\wr_pick_dly$1463[0:0]$2981 - attribute \src "libresoc.v:47378.3-47386.6" + attribute \src "libresoc.v:47430.3-47438.6" wire $0\wr_pick_dly$1479$next[0:0]$2793 - attribute \src "libresoc.v:42858.3-42859.51" + attribute \src "libresoc.v:42906.3-42907.51" wire $0\wr_pick_dly$1479[0:0]$2269 - attribute \src "libresoc.v:41802.7-41802.32" + attribute \src "libresoc.v:41850.7-41850.32" wire $0\wr_pick_dly$1479[0:0]$2983 - attribute \src "libresoc.v:47387.3-47395.6" + attribute \src "libresoc.v:47439.3-47447.6" wire $0\wr_pick_dly$1495$next[0:0]$2796 - attribute \src "libresoc.v:42856.3-42857.51" + attribute \src "libresoc.v:42904.3-42905.51" wire $0\wr_pick_dly$1495[0:0]$2267 - attribute \src "libresoc.v:41806.7-41806.32" + attribute \src "libresoc.v:41854.7-41854.32" wire $0\wr_pick_dly$1495[0:0]$2985 - attribute \src "libresoc.v:47425.3-47433.6" + attribute \src "libresoc.v:47477.3-47485.6" wire $0\wr_pick_dly$1511$next[0:0]$2800 - attribute \src "libresoc.v:42854.3-42855.51" + attribute \src "libresoc.v:42902.3-42903.51" wire $0\wr_pick_dly$1511[0:0]$2265 - attribute \src "libresoc.v:41810.7-41810.32" + attribute \src "libresoc.v:41858.7-41858.32" wire $0\wr_pick_dly$1511[0:0]$2987 - attribute \src "libresoc.v:47463.3-47471.6" + attribute \src "libresoc.v:47515.3-47523.6" wire $0\wr_pick_dly$1547$next[0:0]$2804 - attribute \src "libresoc.v:42852.3-42853.51" + attribute \src "libresoc.v:42900.3-42901.51" wire $0\wr_pick_dly$1547[0:0]$2263 - attribute \src "libresoc.v:41814.7-41814.32" + attribute \src "libresoc.v:41862.7-41862.32" wire $0\wr_pick_dly$1547[0:0]$2989 - attribute \src "libresoc.v:47472.3-47480.6" + attribute \src "libresoc.v:47524.3-47532.6" wire $0\wr_pick_dly$1563$next[0:0]$2807 - attribute \src "libresoc.v:42850.3-42851.51" + attribute \src "libresoc.v:42898.3-42899.51" wire $0\wr_pick_dly$1563[0:0]$2261 - attribute \src "libresoc.v:41818.7-41818.32" + attribute \src "libresoc.v:41866.7-41866.32" wire $0\wr_pick_dly$1563[0:0]$2991 - attribute \src "libresoc.v:47510.3-47518.6" + attribute \src "libresoc.v:47562.3-47570.6" wire $0\wr_pick_dly$1579$next[0:0]$2811 - attribute \src "libresoc.v:42848.3-42849.51" + attribute \src "libresoc.v:42896.3-42897.51" wire $0\wr_pick_dly$1579[0:0]$2259 - attribute \src "libresoc.v:41822.7-41822.32" + attribute \src "libresoc.v:41870.7-41870.32" wire $0\wr_pick_dly$1579[0:0]$2993 - attribute \src "libresoc.v:47519.3-47527.6" + attribute \src "libresoc.v:47571.3-47579.6" wire $0\wr_pick_dly$1595$next[0:0]$2814 - attribute \src "libresoc.v:42846.3-42847.51" + attribute \src "libresoc.v:42894.3-42895.51" wire $0\wr_pick_dly$1595[0:0]$2257 - attribute \src "libresoc.v:41826.7-41826.32" + attribute \src "libresoc.v:41874.7-41874.32" wire $0\wr_pick_dly$1595[0:0]$2995 - attribute \src "libresoc.v:47557.3-47565.6" + attribute \src "libresoc.v:47609.3-47617.6" wire $0\wr_pick_dly$1637$next[0:0]$2818 - attribute \src "libresoc.v:42844.3-42845.51" + attribute \src "libresoc.v:42892.3-42893.51" wire $0\wr_pick_dly$1637[0:0]$2255 - attribute \src "libresoc.v:41830.7-41830.32" + attribute \src "libresoc.v:41878.7-41878.32" wire $0\wr_pick_dly$1637[0:0]$2997 - attribute \src "libresoc.v:47595.3-47603.6" + attribute \src "libresoc.v:47647.3-47655.6" wire $0\wr_pick_dly$1656$next[0:0]$2826 - attribute \src "libresoc.v:42842.3-42843.51" + attribute \src "libresoc.v:42890.3-42891.51" wire $0\wr_pick_dly$1656[0:0]$2253 - attribute \src "libresoc.v:41834.7-41834.32" + attribute \src "libresoc.v:41882.7-41882.32" wire $0\wr_pick_dly$1656[0:0]$2999 - attribute \src "libresoc.v:47633.3-47641.6" + attribute \src "libresoc.v:47685.3-47693.6" wire $0\wr_pick_dly$1672$next[0:0]$2834 - attribute \src "libresoc.v:42840.3-42841.51" + attribute \src "libresoc.v:42888.3-42889.51" wire $0\wr_pick_dly$1672[0:0]$2251 - attribute \src "libresoc.v:41838.7-41838.32" + attribute \src "libresoc.v:41886.7-41886.32" wire $0\wr_pick_dly$1672[0:0]$3001 - attribute \src "libresoc.v:47642.3-47650.6" + attribute \src "libresoc.v:47694.3-47702.6" wire $0\wr_pick_dly$1688$next[0:0]$2837 - attribute \src "libresoc.v:42838.3-42839.51" + attribute \src "libresoc.v:42886.3-42887.51" wire $0\wr_pick_dly$1688[0:0]$2249 - attribute \src "libresoc.v:41842.7-41842.32" + attribute \src "libresoc.v:41890.7-41890.32" wire $0\wr_pick_dly$1688[0:0]$3003 - attribute \src "libresoc.v:47680.3-47688.6" + attribute \src "libresoc.v:47732.3-47740.6" wire $0\wr_pick_dly$1704$next[0:0]$2841 - attribute \src "libresoc.v:42836.3-42837.51" + attribute \src "libresoc.v:42884.3-42885.51" wire $0\wr_pick_dly$1704[0:0]$2247 - attribute \src "libresoc.v:41846.7-41846.32" + attribute \src "libresoc.v:41894.7-41894.32" wire $0\wr_pick_dly$1704[0:0]$3005 - attribute \src "libresoc.v:47718.3-47726.6" + attribute \src "libresoc.v:47770.3-47778.6" wire $0\wr_pick_dly$1748$next[0:0]$2845 - attribute \src "libresoc.v:42834.3-42835.51" + attribute \src "libresoc.v:42882.3-42883.51" wire $0\wr_pick_dly$1748[0:0]$2245 - attribute \src "libresoc.v:41850.7-41850.32" + attribute \src "libresoc.v:41898.7-41898.32" wire $0\wr_pick_dly$1748[0:0]$3007 - attribute \src "libresoc.v:47727.3-47735.6" + attribute \src "libresoc.v:47779.3-47787.6" wire $0\wr_pick_dly$1764$next[0:0]$2848 - attribute \src "libresoc.v:42832.3-42833.51" + attribute \src "libresoc.v:42880.3-42881.51" wire $0\wr_pick_dly$1764[0:0]$2243 - attribute \src "libresoc.v:41854.7-41854.32" + attribute \src "libresoc.v:41902.7-41902.32" wire $0\wr_pick_dly$1764[0:0]$3009 - attribute \src "libresoc.v:47765.3-47773.6" + attribute \src "libresoc.v:47817.3-47825.6" wire $0\wr_pick_dly$1788$next[0:0]$2852 - attribute \src "libresoc.v:42830.3-42831.51" + attribute \src "libresoc.v:42878.3-42879.51" wire $0\wr_pick_dly$1788[0:0]$2241 - attribute \src "libresoc.v:41858.7-41858.32" + attribute \src "libresoc.v:41906.7-41906.32" wire $0\wr_pick_dly$1788[0:0]$3011 - attribute \src "libresoc.v:47803.3-47811.6" + attribute \src "libresoc.v:47855.3-47863.6" wire $0\wr_pick_dly$1808$next[0:0]$2856 - attribute \src "libresoc.v:42828.3-42829.51" + attribute \src "libresoc.v:42876.3-42877.51" wire $0\wr_pick_dly$1808[0:0]$2239 - attribute \src "libresoc.v:41862.7-41862.32" + attribute \src "libresoc.v:41910.7-41910.32" wire $0\wr_pick_dly$1808[0:0]$3013 - attribute \src "libresoc.v:46819.3-46827.6" + attribute \src "libresoc.v:46871.3-46879.6" wire $0\wr_pick_dly$991$next[0:0]$2720 - attribute \src "libresoc.v:42898.3-42899.49" + attribute \src "libresoc.v:42946.3-42947.49" wire $0\wr_pick_dly$991[0:0]$2309 - attribute \src "libresoc.v:41866.7-41866.31" + attribute \src "libresoc.v:41914.7-41914.31" wire $0\wr_pick_dly$991[0:0]$3015 - attribute \src "libresoc.v:46810.3-46818.6" + attribute \src "libresoc.v:46862.3-46870.6" wire $0\wr_pick_dly$next[0:0]$2717 - attribute \src "libresoc.v:42900.3-42901.39" + attribute \src "libresoc.v:42948.3-42949.39" wire $0\wr_pick_dly[0:0] - attribute \src "libresoc.v:46477.3-46567.6" + attribute \src "libresoc.v:46529.3-46619.6" wire $10\corebusy_o[0:0] - attribute \src "libresoc.v:46477.3-46567.6" + attribute \src "libresoc.v:46529.3-46619.6" wire $11\corebusy_o[0:0] - attribute \src "libresoc.v:46477.3-46567.6" + attribute \src "libresoc.v:46529.3-46619.6" wire $12\corebusy_o[0:0] - attribute \src "libresoc.v:46477.3-46567.6" + attribute \src "libresoc.v:46529.3-46619.6" wire $13\corebusy_o[0:0] - attribute \src "libresoc.v:46587.3-46607.6" + attribute \src "libresoc.v:46639.3-46659.6" wire $1\core_terminate_o$next[0:0]$2674 - attribute \src "libresoc.v:38263.7-38263.30" + attribute \src "libresoc.v:38311.7-38311.30" wire $1\core_terminate_o[0:0] - attribute \src "libresoc.v:46477.3-46567.6" + attribute \src "libresoc.v:46529.3-46619.6" wire $1\corebusy_o[0:0] - attribute \src "libresoc.v:46431.3-46457.6" + attribute \src "libresoc.v:46479.3-46509.6" wire width 2 $1\counter$next[1:0]$2655 - attribute \src "libresoc.v:38276.13-38276.27" + attribute \src "libresoc.v:38324.13-38324.27" wire width 2 $1\counter[1:0] - attribute \src "libresoc.v:46412.3-46420.6" + attribute \src "libresoc.v:46460.3-46468.6" wire $1\dp_CR_cr_a_branch0_1$next[0:0]$2649 - attribute \src "libresoc.v:39443.7-39443.34" + attribute \src "libresoc.v:39491.7-39491.34" wire $1\dp_CR_cr_a_branch0_1[0:0] - attribute \src "libresoc.v:46393.3-46401.6" + attribute \src "libresoc.v:46441.3-46449.6" wire $1\dp_CR_cr_a_cr0_0$next[0:0]$2643 - attribute \src "libresoc.v:39447.7-39447.30" + attribute \src "libresoc.v:39495.7-39495.30" wire $1\dp_CR_cr_a_cr0_0[0:0] - attribute \src "libresoc.v:46458.3-46466.6" + attribute \src "libresoc.v:46510.3-46518.6" wire $1\dp_CR_cr_b_cr0_0$next[0:0]$2661 - attribute \src "libresoc.v:39451.7-39451.30" + attribute \src "libresoc.v:39499.7-39499.30" wire $1\dp_CR_cr_b_cr0_0[0:0] - attribute \src "libresoc.v:46568.3-46576.6" + attribute \src "libresoc.v:46620.3-46628.6" wire $1\dp_CR_cr_c_cr0_0$next[0:0]$2668 - attribute \src "libresoc.v:39455.7-39455.30" + attribute \src "libresoc.v:39503.7-39503.30" wire $1\dp_CR_cr_c_cr0_0[0:0] - attribute \src "libresoc.v:46374.3-46382.6" + attribute \src "libresoc.v:46422.3-46430.6" wire $1\dp_CR_full_cr_cr0_0$next[0:0]$2637 - attribute \src "libresoc.v:39459.7-39459.33" + attribute \src "libresoc.v:39507.7-39507.33" wire $1\dp_CR_full_cr_cr0_0[0:0] - attribute \src "libresoc.v:46608.3-46616.6" + attribute \src "libresoc.v:46660.3-46668.6" wire $1\dp_FAST_fast1_branch0_0$next[0:0]$2679 - attribute \src "libresoc.v:39463.7-39463.37" + attribute \src "libresoc.v:39511.7-39511.37" wire $1\dp_FAST_fast1_branch0_0[0:0] - attribute \src "libresoc.v:46675.3-46683.6" + attribute \src "libresoc.v:46727.3-46735.6" wire $1\dp_FAST_fast1_spr0_2$next[0:0]$2692 - attribute \src "libresoc.v:39467.7-39467.34" + attribute \src "libresoc.v:39515.7-39515.34" wire $1\dp_FAST_fast1_spr0_2[0:0] - attribute \src "libresoc.v:46627.3-46635.6" + attribute \src "libresoc.v:46679.3-46687.6" wire $1\dp_FAST_fast1_trap0_1$next[0:0]$2685 - attribute \src "libresoc.v:39471.7-39471.35" + attribute \src "libresoc.v:39519.7-39519.35" wire $1\dp_FAST_fast1_trap0_1[0:0] - attribute \src "libresoc.v:46723.3-46731.6" + attribute \src "libresoc.v:46775.3-46783.6" wire $1\dp_FAST_fast2_branch0_0$next[0:0]$2699 - attribute \src "libresoc.v:39475.7-39475.37" + attribute \src "libresoc.v:39523.7-39523.37" wire $1\dp_FAST_fast2_branch0_0[0:0] - attribute \src "libresoc.v:46742.3-46750.6" + attribute \src "libresoc.v:46794.3-46802.6" wire $1\dp_FAST_fast2_trap0_1$next[0:0]$2705 - attribute \src "libresoc.v:39479.7-39479.35" + attribute \src "libresoc.v:39527.7-39527.35" wire $1\dp_FAST_fast2_trap0_1[0:0] - attribute \src "libresoc.v:45823.3-45831.6" + attribute \src "libresoc.v:45871.3-45879.6" wire $1\dp_INT_ra_alu0_0$next[0:0]$2475 - attribute \src "libresoc.v:39483.7-39483.30" + attribute \src "libresoc.v:39531.7-39531.30" wire $1\dp_INT_ra_alu0_0[0:0] - attribute \src "libresoc.v:45842.3-45850.6" + attribute \src "libresoc.v:45890.3-45898.6" wire $1\dp_INT_ra_cr0_1$next[0:0]$2479 - attribute \src "libresoc.v:39487.7-39487.29" + attribute \src "libresoc.v:39535.7-39535.29" wire $1\dp_INT_ra_cr0_1[0:0] - attribute \src "libresoc.v:45918.3-45926.6" + attribute \src "libresoc.v:45966.3-45974.6" wire $1\dp_INT_ra_div0_5$next[0:0]$2503 - attribute \src "libresoc.v:39491.7-39491.30" + attribute \src "libresoc.v:39539.7-39539.30" wire $1\dp_INT_ra_div0_5[0:0] - attribute \src "libresoc.v:45975.3-45983.6" + attribute \src "libresoc.v:46023.3-46031.6" wire $1\dp_INT_ra_ldst0_8$next[0:0]$2521 - attribute \src "libresoc.v:39495.7-39495.31" + attribute \src "libresoc.v:39543.7-39543.31" wire $1\dp_INT_ra_ldst0_8[0:0] - attribute \src "libresoc.v:45880.3-45888.6" + attribute \src "libresoc.v:45928.3-45936.6" wire $1\dp_INT_ra_logical0_3$next[0:0]$2491 - attribute \src "libresoc.v:39499.7-39499.34" + attribute \src "libresoc.v:39547.7-39547.34" wire $1\dp_INT_ra_logical0_3[0:0] - attribute \src "libresoc.v:45937.3-45945.6" + attribute \src "libresoc.v:45985.3-45993.6" wire $1\dp_INT_ra_mul0_6$next[0:0]$2509 - attribute \src "libresoc.v:39503.7-39503.30" + attribute \src "libresoc.v:39551.7-39551.30" wire $1\dp_INT_ra_mul0_6[0:0] - attribute \src "libresoc.v:45956.3-45964.6" + attribute \src "libresoc.v:46004.3-46012.6" wire $1\dp_INT_ra_shiftrot0_7$next[0:0]$2515 - attribute \src "libresoc.v:39507.7-39507.35" + attribute \src "libresoc.v:39555.7-39555.35" wire $1\dp_INT_ra_shiftrot0_7[0:0] - attribute \src "libresoc.v:45899.3-45907.6" + attribute \src "libresoc.v:45947.3-45955.6" wire $1\dp_INT_ra_spr0_4$next[0:0]$2497 - attribute \src "libresoc.v:39511.7-39511.30" + attribute \src "libresoc.v:39559.7-39559.30" wire $1\dp_INT_ra_spr0_4[0:0] - attribute \src "libresoc.v:45861.3-45869.6" + attribute \src "libresoc.v:45909.3-45917.6" wire $1\dp_INT_ra_trap0_2$next[0:0]$2485 - attribute \src "libresoc.v:39515.7-39515.31" + attribute \src "libresoc.v:39563.7-39563.31" wire $1\dp_INT_ra_trap0_2[0:0] - attribute \src "libresoc.v:45994.3-46002.6" + attribute \src "libresoc.v:46042.3-46050.6" wire $1\dp_INT_rb_alu0_0$next[0:0]$2527 - attribute \src "libresoc.v:39519.7-39519.30" + attribute \src "libresoc.v:39567.7-39567.30" wire $1\dp_INT_rb_alu0_0[0:0] - attribute \src "libresoc.v:46013.3-46021.6" + attribute \src "libresoc.v:46061.3-46069.6" wire $1\dp_INT_rb_cr0_1$next[0:0]$2531 - attribute \src "libresoc.v:39523.7-39523.29" + attribute \src "libresoc.v:39571.7-39571.29" wire $1\dp_INT_rb_cr0_1[0:0] - attribute \src "libresoc.v:46070.3-46078.6" + attribute \src "libresoc.v:46118.3-46126.6" wire $1\dp_INT_rb_div0_4$next[0:0]$2549 - attribute \src "libresoc.v:39527.7-39527.30" + attribute \src "libresoc.v:39575.7-39575.30" wire $1\dp_INT_rb_div0_4[0:0] - attribute \src "libresoc.v:46127.3-46135.6" + attribute \src "libresoc.v:46175.3-46183.6" wire $1\dp_INT_rb_ldst0_7$next[0:0]$2567 - attribute \src "libresoc.v:39531.7-39531.31" + attribute \src "libresoc.v:39579.7-39579.31" wire $1\dp_INT_rb_ldst0_7[0:0] - attribute \src "libresoc.v:46051.3-46059.6" + attribute \src "libresoc.v:46099.3-46107.6" wire $1\dp_INT_rb_logical0_3$next[0:0]$2543 - attribute \src "libresoc.v:39535.7-39535.34" + attribute \src "libresoc.v:39583.7-39583.34" wire $1\dp_INT_rb_logical0_3[0:0] - attribute \src "libresoc.v:46089.3-46097.6" + attribute \src "libresoc.v:46137.3-46145.6" wire $1\dp_INT_rb_mul0_5$next[0:0]$2555 - attribute \src "libresoc.v:39539.7-39539.30" + attribute \src "libresoc.v:39587.7-39587.30" wire $1\dp_INT_rb_mul0_5[0:0] - attribute \src "libresoc.v:46108.3-46116.6" + attribute \src "libresoc.v:46156.3-46164.6" wire $1\dp_INT_rb_shiftrot0_6$next[0:0]$2561 - attribute \src "libresoc.v:39543.7-39543.35" + attribute \src "libresoc.v:39591.7-39591.35" wire $1\dp_INT_rb_shiftrot0_6[0:0] - attribute \src "libresoc.v:46032.3-46040.6" + attribute \src "libresoc.v:46080.3-46088.6" wire $1\dp_INT_rb_trap0_2$next[0:0]$2537 - attribute \src "libresoc.v:39547.7-39547.31" + attribute \src "libresoc.v:39595.7-39595.31" wire $1\dp_INT_rb_trap0_2[0:0] - attribute \src "libresoc.v:46165.3-46173.6" + attribute \src "libresoc.v:46213.3-46221.6" wire $1\dp_INT_rc_ldst0_1$next[0:0]$2577 - attribute \src "libresoc.v:39551.7-39551.31" + attribute \src "libresoc.v:39599.7-39599.31" wire $1\dp_INT_rc_ldst0_1[0:0] - attribute \src "libresoc.v:46146.3-46154.6" + attribute \src "libresoc.v:46194.3-46202.6" wire $1\dp_INT_rc_shiftrot0_0$next[0:0]$2573 - attribute \src "libresoc.v:39555.7-39555.35" + attribute \src "libresoc.v:39603.7-39603.35" wire $1\dp_INT_rc_shiftrot0_0[0:0] - attribute \src "libresoc.v:46791.3-46799.6" + attribute \src "libresoc.v:46843.3-46851.6" wire $1\dp_SPR_spr1_spr0_0$next[0:0]$2712 - attribute \src "libresoc.v:39559.7-39559.32" + attribute \src "libresoc.v:39607.7-39607.32" wire $1\dp_SPR_spr1_spr0_0[0:0] - attribute \src "libresoc.v:46298.3-46306.6" + attribute \src "libresoc.v:46346.3-46354.6" wire $1\dp_XER_xer_ca_alu0_0$next[0:0]$2617 - attribute \src "libresoc.v:39563.7-39563.34" + attribute \src "libresoc.v:39611.7-39611.34" wire $1\dp_XER_xer_ca_alu0_0[0:0] - attribute \src "libresoc.v:46336.3-46344.6" + attribute \src "libresoc.v:46384.3-46392.6" wire $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2627 - attribute \src "libresoc.v:39567.7-39567.39" + attribute \src "libresoc.v:39615.7-39615.39" wire $1\dp_XER_xer_ca_shiftrot0_2[0:0] - attribute \src "libresoc.v:46317.3-46325.6" + attribute \src "libresoc.v:46365.3-46373.6" wire $1\dp_XER_xer_ca_spr0_1$next[0:0]$2623 - attribute \src "libresoc.v:39571.7-39571.34" + attribute \src "libresoc.v:39619.7-39619.34" wire $1\dp_XER_xer_ca_spr0_1[0:0] - attribute \src "libresoc.v:46355.3-46363.6" + attribute \src "libresoc.v:46403.3-46411.6" wire $1\dp_XER_xer_ov_spr0_0$next[0:0]$2631 - attribute \src "libresoc.v:39575.7-39575.34" + attribute \src "libresoc.v:39623.7-39623.34" wire $1\dp_XER_xer_ov_spr0_0[0:0] - attribute \src "libresoc.v:46184.3-46192.6" + attribute \src "libresoc.v:46232.3-46240.6" wire $1\dp_XER_xer_so_alu0_0$next[0:0]$2583 - attribute \src "libresoc.v:39579.7-39579.34" + attribute \src "libresoc.v:39627.7-39627.34" wire $1\dp_XER_xer_so_alu0_0[0:0] - attribute \src "libresoc.v:46241.3-46249.6" + attribute \src "libresoc.v:46289.3-46297.6" wire $1\dp_XER_xer_so_div0_3$next[0:0]$2599 - attribute \src "libresoc.v:39583.7-39583.34" + attribute \src "libresoc.v:39631.7-39631.34" wire $1\dp_XER_xer_so_div0_3[0:0] - attribute \src "libresoc.v:46203.3-46211.6" + attribute \src "libresoc.v:46251.3-46259.6" wire $1\dp_XER_xer_so_logical0_1$next[0:0]$2589 - attribute \src "libresoc.v:39587.7-39587.38" + attribute \src "libresoc.v:39635.7-39635.38" wire $1\dp_XER_xer_so_logical0_1[0:0] - attribute \src "libresoc.v:46260.3-46268.6" + attribute \src "libresoc.v:46308.3-46316.6" wire $1\dp_XER_xer_so_mul0_4$next[0:0]$2605 - attribute \src "libresoc.v:39591.7-39591.34" + attribute \src "libresoc.v:39639.7-39639.34" wire $1\dp_XER_xer_so_mul0_4[0:0] - attribute \src "libresoc.v:46279.3-46287.6" + attribute \src "libresoc.v:46327.3-46335.6" wire $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2611 - attribute \src "libresoc.v:39595.7-39595.39" + attribute \src "libresoc.v:39643.7-39643.39" wire $1\dp_XER_xer_so_shiftrot0_5[0:0] - attribute \src "libresoc.v:46222.3-46230.6" + attribute \src "libresoc.v:46270.3-46278.6" wire $1\dp_XER_xer_so_spr0_2$next[0:0]$2595 - attribute \src "libresoc.v:39599.7-39599.34" + attribute \src "libresoc.v:39647.7-39647.34" wire $1\dp_XER_xer_so_spr0_2[0:0] - attribute \src "libresoc.v:47566.3-47594.6" + attribute \src "libresoc.v:47618.3-47646.6" wire $1\fus_cu_issue_i$13[0:0]$2822 - attribute \src "libresoc.v:47900.3-47928.6" + attribute \src "libresoc.v:47952.3-47980.6" wire $1\fus_cu_issue_i$16[0:0]$2863 - attribute \src "libresoc.v:48219.3-48247.6" + attribute \src "libresoc.v:48271.3-48299.6" wire $1\fus_cu_issue_i$19[0:0]$2882 - attribute \src "libresoc.v:43868.3-43896.6" + attribute \src "libresoc.v:43916.3-43944.6" wire $1\fus_cu_issue_i$22[0:0]$2360 - attribute \src "libresoc.v:44042.3-44070.6" + attribute \src "libresoc.v:44090.3-44118.6" wire $1\fus_cu_issue_i$25[0:0]$2374 - attribute \src "libresoc.v:44538.3-44566.6" + attribute \src "libresoc.v:44586.3-44614.6" wire $1\fus_cu_issue_i$28[0:0]$2399 - attribute \src "libresoc.v:44860.3-44888.6" + attribute \src "libresoc.v:44908.3-44936.6" wire $1\fus_cu_issue_i$31[0:0]$2418 - attribute \src "libresoc.v:45327.3-45355.6" + attribute \src "libresoc.v:45375.3-45403.6" wire $1\fus_cu_issue_i$34[0:0]$2442 - attribute \src "libresoc.v:45765.3-45793.6" + attribute \src "libresoc.v:45813.3-45841.6" wire $1\fus_cu_issue_i$37[0:0]$2465 - attribute \src "libresoc.v:47349.3-47377.6" + attribute \src "libresoc.v:47401.3-47429.6" wire $1\fus_cu_issue_i[0:0] - attribute \src "libresoc.v:47604.3-47632.6" + attribute \src "libresoc.v:47656.3-47684.6" wire width 6 $1\fus_cu_rdmaskn_i$15[5:0]$2830 - attribute \src "libresoc.v:47929.3-47957.6" + attribute \src "libresoc.v:47981.3-48009.6" wire width 3 $1\fus_cu_rdmaskn_i$18[2:0]$2868 - attribute \src "libresoc.v:48248.3-48276.6" + attribute \src "libresoc.v:48300.3-48328.6" wire width 4 $1\fus_cu_rdmaskn_i$21[3:0]$2887 - attribute \src "libresoc.v:43897.3-43925.6" + attribute \src "libresoc.v:43945.3-43973.6" wire width 3 $1\fus_cu_rdmaskn_i$24[2:0]$2365 - attribute \src "libresoc.v:44071.3-44099.6" + attribute \src "libresoc.v:44119.3-44147.6" wire width 6 $1\fus_cu_rdmaskn_i$27[5:0]$2379 - attribute \src "libresoc.v:44567.3-44595.6" + attribute \src "libresoc.v:44615.3-44643.6" wire width 3 $1\fus_cu_rdmaskn_i$30[2:0]$2404 - attribute \src "libresoc.v:44889.3-44917.6" + attribute \src "libresoc.v:44937.3-44965.6" wire width 3 $1\fus_cu_rdmaskn_i$33[2:0]$2423 - attribute \src "libresoc.v:45356.3-45384.6" + attribute \src "libresoc.v:45404.3-45432.6" wire width 5 $1\fus_cu_rdmaskn_i$36[4:0]$2447 - attribute \src "libresoc.v:45794.3-45822.6" + attribute \src "libresoc.v:45842.3-45870.6" wire width 3 $1\fus_cu_rdmaskn_i$39[2:0]$2470 - attribute \src "libresoc.v:47396.3-47424.6" + attribute \src "libresoc.v:47448.3-47476.6" wire width 4 $1\fus_cu_rdmaskn_i[3:0] - attribute \src "libresoc.v:47273.3-47301.6" + attribute \src "libresoc.v:47325.3-47353.6" wire width 4 $1\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "libresoc.v:46694.3-46722.6" + attribute \src "libresoc.v:46746.3-46774.6" wire width 14 $1\fus_oper_i_alu_alu0__fn_unit[13:0] - attribute \src "libresoc.v:46761.3-46790.6" + attribute \src "libresoc.v:46813.3-46842.6" wire width 64 $1\fus_oper_i_alu_alu0__imm_data__data[63:0] - attribute \src "libresoc.v:46761.3-46790.6" + attribute \src "libresoc.v:46813.3-46842.6" wire $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "libresoc.v:47094.3-47122.6" + attribute \src "libresoc.v:47146.3-47174.6" wire width 2 $1\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "libresoc.v:47311.3-47339.6" + attribute \src "libresoc.v:47363.3-47391.6" wire width 32 $1\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "libresoc.v:46646.3-46674.6" + attribute \src "libresoc.v:46698.3-46726.6" wire width 7 $1\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "libresoc.v:46933.3-46961.6" + attribute \src "libresoc.v:46985.3-47013.6" wire $1\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "libresoc.v:47018.3-47046.6" + attribute \src "libresoc.v:47070.3-47098.6" wire $1\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "libresoc.v:47188.3-47216.6" + attribute \src "libresoc.v:47240.3-47268.6" wire $1\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "libresoc.v:47226.3-47254.6" + attribute \src "libresoc.v:47278.3-47306.6" wire $1\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "libresoc.v:46876.3-46905.6" + attribute \src "libresoc.v:46928.3-46957.6" wire $1\fus_oper_i_alu_alu0__oe__oe[0:0] - attribute \src "libresoc.v:46876.3-46905.6" + attribute \src "libresoc.v:46928.3-46957.6" wire $1\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "libresoc.v:47141.3-47169.6" + attribute \src "libresoc.v:47193.3-47221.6" wire $1\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "libresoc.v:46828.3-46857.6" + attribute \src "libresoc.v:46880.3-46909.6" wire $1\fus_oper_i_alu_alu0__rc__ok[0:0] - attribute \src "libresoc.v:46828.3-46857.6" + attribute \src "libresoc.v:46880.3-46909.6" wire $1\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "libresoc.v:47056.3-47084.6" + attribute \src "libresoc.v:47108.3-47136.6" wire $1\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "libresoc.v:46980.3-47008.6" + attribute \src "libresoc.v:47032.3-47060.6" wire $1\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "libresoc.v:47651.3-47679.6" + attribute \src "libresoc.v:47703.3-47731.6" wire width 64 $1\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "libresoc.v:47736.3-47764.6" + attribute \src "libresoc.v:47788.3-47816.6" wire width 14 $1\fus_oper_i_alu_branch0__fn_unit[13:0] - attribute \src "libresoc.v:47812.3-47841.6" + attribute \src "libresoc.v:47864.3-47893.6" wire width 64 $1\fus_oper_i_alu_branch0__imm_data__data[63:0] - attribute \src "libresoc.v:47812.3-47841.6" + attribute \src "libresoc.v:47864.3-47893.6" wire $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "libresoc.v:47774.3-47802.6" + attribute \src "libresoc.v:47826.3-47854.6" wire width 32 $1\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "libresoc.v:47689.3-47717.6" + attribute \src "libresoc.v:47741.3-47769.6" wire width 7 $1\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "libresoc.v:47871.3-47899.6" + attribute \src "libresoc.v:47923.3-47951.6" wire $1\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "libresoc.v:47842.3-47870.6" + attribute \src "libresoc.v:47894.3-47922.6" wire $1\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "libresoc.v:47481.3-47509.6" + attribute \src "libresoc.v:47533.3-47561.6" wire width 14 $1\fus_oper_i_alu_cr0__fn_unit[13:0] - attribute \src "libresoc.v:47528.3-47556.6" + attribute \src "libresoc.v:47580.3-47608.6" wire width 32 $1\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "libresoc.v:47434.3-47462.6" + attribute \src "libresoc.v:47486.3-47514.6" wire width 7 $1\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "libresoc.v:44480.3-44508.6" + attribute \src "libresoc.v:44528.3-44556.6" wire width 4 $1\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "libresoc.v:44129.3-44157.6" + attribute \src "libresoc.v:44177.3-44205.6" wire width 14 $1\fus_oper_i_alu_div0__fn_unit[13:0] - attribute \src "libresoc.v:44158.3-44187.6" + attribute \src "libresoc.v:44206.3-44235.6" wire width 64 $1\fus_oper_i_alu_div0__imm_data__data[63:0] - attribute \src "libresoc.v:44158.3-44187.6" + attribute \src "libresoc.v:44206.3-44235.6" wire $1\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "libresoc.v:44306.3-44334.6" + attribute \src "libresoc.v:44354.3-44382.6" wire width 2 $1\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "libresoc.v:44509.3-44537.6" + attribute \src "libresoc.v:44557.3-44585.6" wire width 32 $1\fus_oper_i_alu_div0__insn[31:0] - attribute \src "libresoc.v:44100.3-44128.6" + attribute \src "libresoc.v:44148.3-44176.6" wire width 7 $1\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "libresoc.v:44248.3-44276.6" + attribute \src "libresoc.v:44296.3-44324.6" wire $1\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "libresoc.v:44335.3-44363.6" + attribute \src "libresoc.v:44383.3-44411.6" wire $1\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "libresoc.v:44422.3-44450.6" + attribute \src "libresoc.v:44470.3-44498.6" wire $1\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "libresoc.v:44451.3-44479.6" + attribute \src "libresoc.v:44499.3-44527.6" wire $1\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "libresoc.v:44218.3-44247.6" + attribute \src "libresoc.v:44266.3-44295.6" wire $1\fus_oper_i_alu_div0__oe__oe[0:0] - attribute \src "libresoc.v:44218.3-44247.6" + attribute \src "libresoc.v:44266.3-44295.6" wire $1\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "libresoc.v:44393.3-44421.6" + attribute \src "libresoc.v:44441.3-44469.6" wire $1\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "libresoc.v:44188.3-44217.6" + attribute \src "libresoc.v:44236.3-44265.6" wire $1\fus_oper_i_alu_div0__rc__ok[0:0] - attribute \src "libresoc.v:44188.3-44217.6" + attribute \src "libresoc.v:44236.3-44265.6" wire $1\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "libresoc.v:44364.3-44392.6" + attribute \src "libresoc.v:44412.3-44440.6" wire $1\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "libresoc.v:44277.3-44305.6" + attribute \src "libresoc.v:44325.3-44353.6" wire $1\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "libresoc.v:43810.3-43838.6" + attribute \src "libresoc.v:43858.3-43886.6" wire width 4 $1\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "libresoc.v:48306.3-48334.6" + attribute \src "libresoc.v:48358.3-48386.6" wire width 14 $1\fus_oper_i_alu_logical0__fn_unit[13:0] - attribute \src "libresoc.v:48335.3-48364.6" + attribute \src "libresoc.v:48387.3-48416.6" wire width 64 $1\fus_oper_i_alu_logical0__imm_data__data[63:0] - attribute \src "libresoc.v:48335.3-48364.6" + attribute \src "libresoc.v:48387.3-48416.6" wire $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "libresoc.v:48483.3-48511.6" + attribute \src "libresoc.v:48535.3-48563.6" wire width 2 $1\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "libresoc.v:43839.3-43867.6" + attribute \src "libresoc.v:43887.3-43915.6" wire width 32 $1\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "libresoc.v:48277.3-48305.6" + attribute \src "libresoc.v:48329.3-48357.6" wire width 7 $1\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "libresoc.v:48425.3-48453.6" + attribute \src "libresoc.v:48477.3-48505.6" wire $1\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "libresoc.v:48512.3-48540.6" + attribute \src "libresoc.v:48564.3-48592.6" wire $1\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "libresoc.v:43752.3-43780.6" + attribute \src "libresoc.v:43800.3-43828.6" wire $1\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "libresoc.v:43781.3-43809.6" + attribute \src "libresoc.v:43829.3-43857.6" wire $1\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "libresoc.v:48395.3-48424.6" + attribute \src "libresoc.v:48447.3-48476.6" wire $1\fus_oper_i_alu_logical0__oe__oe[0:0] - attribute \src "libresoc.v:48395.3-48424.6" + attribute \src "libresoc.v:48447.3-48476.6" wire $1\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "libresoc.v:43723.3-43751.6" + attribute \src "libresoc.v:43771.3-43799.6" wire $1\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "libresoc.v:48365.3-48394.6" + attribute \src "libresoc.v:48417.3-48446.6" wire $1\fus_oper_i_alu_logical0__rc__ok[0:0] - attribute \src "libresoc.v:48365.3-48394.6" + attribute \src "libresoc.v:48417.3-48446.6" wire $1\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "libresoc.v:48541.3-48569.6" + attribute \src "libresoc.v:48593.3-48621.6" wire $1\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "libresoc.v:48454.3-48482.6" + attribute \src "libresoc.v:48506.3-48534.6" wire $1\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "libresoc.v:44625.3-44653.6" + attribute \src "libresoc.v:44673.3-44701.6" wire width 14 $1\fus_oper_i_alu_mul0__fn_unit[13:0] - attribute \src "libresoc.v:44654.3-44683.6" + attribute \src "libresoc.v:44702.3-44731.6" wire width 64 $1\fus_oper_i_alu_mul0__imm_data__data[63:0] - attribute \src "libresoc.v:44654.3-44683.6" + attribute \src "libresoc.v:44702.3-44731.6" wire $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "libresoc.v:44831.3-44859.6" + attribute \src "libresoc.v:44879.3-44907.6" wire width 32 $1\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "libresoc.v:44596.3-44624.6" + attribute \src "libresoc.v:44644.3-44672.6" wire width 7 $1\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "libresoc.v:44773.3-44801.6" + attribute \src "libresoc.v:44821.3-44849.6" wire $1\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "libresoc.v:44802.3-44830.6" + attribute \src "libresoc.v:44850.3-44878.6" wire $1\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "libresoc.v:44714.3-44743.6" + attribute \src "libresoc.v:44762.3-44791.6" wire $1\fus_oper_i_alu_mul0__oe__oe[0:0] - attribute \src "libresoc.v:44714.3-44743.6" + attribute \src "libresoc.v:44762.3-44791.6" wire $1\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "libresoc.v:44684.3-44713.6" + attribute \src "libresoc.v:44732.3-44761.6" wire $1\fus_oper_i_alu_mul0__rc__ok[0:0] - attribute \src "libresoc.v:44684.3-44713.6" + attribute \src "libresoc.v:44732.3-44761.6" wire $1\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "libresoc.v:44744.3-44772.6" + attribute \src "libresoc.v:44792.3-44820.6" wire $1\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "libresoc.v:44947.3-44975.6" + attribute \src "libresoc.v:44995.3-45023.6" wire width 14 $1\fus_oper_i_alu_shift_rot0__fn_unit[13:0] - attribute \src "libresoc.v:44976.3-45005.6" + attribute \src "libresoc.v:45024.3-45053.6" wire width 64 $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] - attribute \src "libresoc.v:44976.3-45005.6" + attribute \src "libresoc.v:45024.3-45053.6" wire $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "libresoc.v:45124.3-45152.6" + attribute \src "libresoc.v:45172.3-45200.6" wire width 2 $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "libresoc.v:45182.3-45210.6" + attribute \src "libresoc.v:45230.3-45258.6" wire $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "libresoc.v:45298.3-45326.6" + attribute \src "libresoc.v:45346.3-45374.6" wire width 32 $1\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "libresoc.v:44918.3-44946.6" + attribute \src "libresoc.v:44966.3-44994.6" wire width 7 $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "libresoc.v:45095.3-45123.6" + attribute \src "libresoc.v:45143.3-45171.6" wire $1\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "libresoc.v:45240.3-45268.6" + attribute \src "libresoc.v:45288.3-45316.6" wire $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "libresoc.v:45269.3-45297.6" + attribute \src "libresoc.v:45317.3-45345.6" wire $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "libresoc.v:45036.3-45065.6" + attribute \src "libresoc.v:45084.3-45113.6" wire $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] - attribute \src "libresoc.v:45036.3-45065.6" + attribute \src "libresoc.v:45084.3-45113.6" wire $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "libresoc.v:45153.3-45181.6" + attribute \src "libresoc.v:45201.3-45229.6" wire $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "libresoc.v:45211.3-45239.6" + attribute \src "libresoc.v:45259.3-45287.6" wire $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "libresoc.v:45006.3-45035.6" + attribute \src "libresoc.v:45054.3-45083.6" wire $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] - attribute \src "libresoc.v:45006.3-45035.6" + attribute \src "libresoc.v:45054.3-45083.6" wire $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "libresoc.v:45066.3-45094.6" + attribute \src "libresoc.v:45114.3-45142.6" wire $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "libresoc.v:43955.3-43983.6" + attribute \src "libresoc.v:44003.3-44031.6" wire width 14 $1\fus_oper_i_alu_spr0__fn_unit[13:0] - attribute \src "libresoc.v:43984.3-44012.6" + attribute \src "libresoc.v:44032.3-44060.6" wire width 32 $1\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "libresoc.v:43926.3-43954.6" + attribute \src "libresoc.v:43974.3-44002.6" wire width 7 $1\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "libresoc.v:44013.3-44041.6" + attribute \src "libresoc.v:44061.3-44089.6" wire $1\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "libresoc.v:48074.3-48102.6" + attribute \src "libresoc.v:48126.3-48154.6" wire width 64 $1\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "libresoc.v:47987.3-48015.6" + attribute \src "libresoc.v:48039.3-48067.6" wire width 14 $1\fus_oper_i_alu_trap0__fn_unit[13:0] - attribute \src "libresoc.v:48016.3-48044.6" + attribute \src "libresoc.v:48068.3-48096.6" wire width 32 $1\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "libresoc.v:47958.3-47986.6" + attribute \src "libresoc.v:48010.3-48038.6" wire width 7 $1\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "libresoc.v:48103.3-48131.6" + attribute \src "libresoc.v:48155.3-48183.6" wire $1\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "libresoc.v:48190.3-48218.6" + attribute \src "libresoc.v:48242.3-48270.6" wire width 8 $1\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "libresoc.v:48045.3-48073.6" + attribute \src "libresoc.v:48097.3-48125.6" wire width 64 $1\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "libresoc.v:48161.3-48189.6" + attribute \src "libresoc.v:48213.3-48241.6" wire width 13 $1\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "libresoc.v:48132.3-48160.6" + attribute \src "libresoc.v:48184.3-48212.6" wire width 8 $1\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "libresoc.v:45649.3-45677.6" + attribute \src "libresoc.v:45697.3-45725.6" wire $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "libresoc.v:45620.3-45648.6" + attribute \src "libresoc.v:45668.3-45696.6" wire width 4 $1\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "libresoc.v:45414.3-45442.6" + attribute \src "libresoc.v:45462.3-45490.6" wire width 14 $1\fus_oper_i_ldst_ldst0__fn_unit[13:0] - attribute \src "libresoc.v:45443.3-45472.6" + attribute \src "libresoc.v:45491.3-45520.6" wire width 64 $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] - attribute \src "libresoc.v:45443.3-45472.6" + attribute \src "libresoc.v:45491.3-45520.6" wire $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "libresoc.v:45736.3-45764.6" + attribute \src "libresoc.v:45784.3-45812.6" wire width 32 $1\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "libresoc.v:45385.3-45413.6" + attribute \src "libresoc.v:45433.3-45461.6" wire width 7 $1\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "libresoc.v:45562.3-45590.6" + attribute \src "libresoc.v:45610.3-45638.6" wire $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "libresoc.v:45591.3-45619.6" + attribute \src "libresoc.v:45639.3-45667.6" wire $1\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "libresoc.v:45707.3-45735.6" + attribute \src "libresoc.v:45755.3-45783.6" wire width 2 $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "libresoc.v:45532.3-45561.6" + attribute \src "libresoc.v:45580.3-45609.6" wire $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] - attribute \src "libresoc.v:45532.3-45561.6" + attribute \src "libresoc.v:45580.3-45609.6" wire $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "libresoc.v:45502.3-45531.6" + attribute \src "libresoc.v:45550.3-45579.6" wire $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] - attribute \src "libresoc.v:45502.3-45531.6" + attribute \src "libresoc.v:45550.3-45579.6" wire $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "libresoc.v:45678.3-45706.6" + attribute \src "libresoc.v:45726.3-45754.6" wire $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "libresoc.v:45473.3-45501.6" + attribute \src "libresoc.v:45521.3-45549.6" wire $1\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "libresoc.v:45851.3-45860.6" + attribute \src "libresoc.v:45899.3-45908.6" wire width 64 $1\fus_src1_i$42[63:0]$2482 - attribute \src "libresoc.v:45870.3-45879.6" + attribute \src "libresoc.v:45918.3-45927.6" wire width 64 $1\fus_src1_i$45[63:0]$2488 - attribute \src "libresoc.v:45889.3-45898.6" + attribute \src "libresoc.v:45937.3-45946.6" wire width 64 $1\fus_src1_i$48[63:0]$2494 - attribute \src "libresoc.v:45908.3-45917.6" + attribute \src "libresoc.v:45956.3-45965.6" wire width 64 $1\fus_src1_i$51[63:0]$2500 - attribute \src "libresoc.v:45927.3-45936.6" + attribute \src "libresoc.v:45975.3-45984.6" wire width 64 $1\fus_src1_i$54[63:0]$2506 - attribute \src "libresoc.v:45946.3-45955.6" + attribute \src "libresoc.v:45994.3-46003.6" wire width 64 $1\fus_src1_i$57[63:0]$2512 - attribute \src "libresoc.v:45965.3-45974.6" + attribute \src "libresoc.v:46013.3-46022.6" wire width 64 $1\fus_src1_i$60[63:0]$2518 - attribute \src "libresoc.v:45984.3-45993.6" + attribute \src "libresoc.v:46032.3-46041.6" wire width 64 $1\fus_src1_i$63[63:0]$2524 - attribute \src "libresoc.v:46617.3-46626.6" + attribute \src "libresoc.v:46669.3-46678.6" wire width 64 $1\fus_src1_i$86[63:0]$2682 - attribute \src "libresoc.v:45832.3-45841.6" + attribute \src "libresoc.v:45880.3-45889.6" wire width 64 $1\fus_src1_i[63:0] - attribute \src "libresoc.v:46022.3-46031.6" + attribute \src "libresoc.v:46070.3-46079.6" wire width 64 $1\fus_src2_i$64[63:0]$2534 - attribute \src "libresoc.v:46041.3-46050.6" + attribute \src "libresoc.v:46089.3-46098.6" wire width 64 $1\fus_src2_i$65[63:0]$2540 - attribute \src "libresoc.v:46060.3-46069.6" + attribute \src "libresoc.v:46108.3-46117.6" wire width 64 $1\fus_src2_i$66[63:0]$2546 - attribute \src "libresoc.v:46079.3-46088.6" + attribute \src "libresoc.v:46127.3-46136.6" wire width 64 $1\fus_src2_i$67[63:0]$2552 - attribute \src "libresoc.v:46098.3-46107.6" + attribute \src "libresoc.v:46146.3-46155.6" wire width 64 $1\fus_src2_i$68[63:0]$2558 - attribute \src "libresoc.v:46117.3-46126.6" + attribute \src "libresoc.v:46165.3-46174.6" wire width 64 $1\fus_src2_i$69[63:0]$2564 - attribute \src "libresoc.v:46136.3-46145.6" + attribute \src "libresoc.v:46184.3-46193.6" wire width 64 $1\fus_src2_i$70[63:0]$2570 - attribute \src "libresoc.v:46732.3-46741.6" + attribute \src "libresoc.v:46784.3-46793.6" wire width 64 $1\fus_src2_i$89[63:0]$2702 - attribute \src "libresoc.v:46800.3-46809.6" + attribute \src "libresoc.v:46852.3-46861.6" wire width 64 $1\fus_src2_i$91[63:0]$2715 - attribute \src "libresoc.v:46003.3-46012.6" + attribute \src "libresoc.v:46051.3-46060.6" wire width 64 $1\fus_src2_i[63:0] - attribute \src "libresoc.v:46174.3-46183.6" + attribute \src "libresoc.v:46222.3-46231.6" wire width 64 $1\fus_src3_i$71[63:0]$2580 - attribute \src "libresoc.v:46193.3-46202.6" + attribute \src "libresoc.v:46241.3-46250.6" wire $1\fus_src3_i$72[0:0]$2586 - attribute \src "libresoc.v:46212.3-46221.6" + attribute \src "libresoc.v:46260.3-46269.6" wire $1\fus_src3_i$73[0:0]$2592 - attribute \src "libresoc.v:46250.3-46259.6" + attribute \src "libresoc.v:46298.3-46307.6" wire $1\fus_src3_i$74[0:0]$2602 - attribute \src "libresoc.v:46269.3-46278.6" + attribute \src "libresoc.v:46317.3-46326.6" wire $1\fus_src3_i$75[0:0]$2608 - attribute \src "libresoc.v:46383.3-46392.6" + attribute \src "libresoc.v:46431.3-46440.6" wire width 32 $1\fus_src3_i$79[31:0]$2640 - attribute \src "libresoc.v:46421.3-46430.6" + attribute \src "libresoc.v:46469.3-46478.6" wire width 4 $1\fus_src3_i$83[3:0]$2652 - attribute \src "libresoc.v:46636.3-46645.6" + attribute \src "libresoc.v:46688.3-46697.6" wire width 64 $1\fus_src3_i$87[63:0]$2688 - attribute \src "libresoc.v:46684.3-46693.6" + attribute \src "libresoc.v:46736.3-46745.6" wire width 64 $1\fus_src3_i$88[63:0]$2695 - attribute \src "libresoc.v:46155.3-46164.6" + attribute \src "libresoc.v:46203.3-46212.6" wire width 64 $1\fus_src3_i[63:0] - attribute \src "libresoc.v:46288.3-46297.6" + attribute \src "libresoc.v:46336.3-46345.6" wire $1\fus_src4_i$76[0:0]$2614 - attribute \src "libresoc.v:46307.3-46316.6" + attribute \src "libresoc.v:46355.3-46364.6" wire width 2 $1\fus_src4_i$77[1:0]$2620 - attribute \src "libresoc.v:46402.3-46411.6" + attribute \src "libresoc.v:46450.3-46459.6" wire width 4 $1\fus_src4_i$80[3:0]$2646 - attribute \src "libresoc.v:46751.3-46760.6" + attribute \src "libresoc.v:46803.3-46812.6" wire width 64 $1\fus_src4_i$90[63:0]$2708 - attribute \src "libresoc.v:46231.3-46240.6" + attribute \src "libresoc.v:46279.3-46288.6" wire $1\fus_src4_i[0:0] - attribute \src "libresoc.v:46364.3-46373.6" + attribute \src "libresoc.v:46412.3-46421.6" wire width 2 $1\fus_src5_i$78[1:0]$2634 - attribute \src "libresoc.v:46467.3-46476.6" + attribute \src "libresoc.v:46519.3-46528.6" wire width 4 $1\fus_src5_i$84[3:0]$2664 - attribute \src "libresoc.v:46345.3-46354.6" + attribute \src "libresoc.v:46393.3-46402.6" wire width 2 $1\fus_src5_i[1:0] - attribute \src "libresoc.v:46577.3-46586.6" + attribute \src "libresoc.v:46629.3-46638.6" wire width 4 $1\fus_src6_i$85[3:0]$2671 - attribute \src "libresoc.v:46326.3-46335.6" + attribute \src "libresoc.v:46374.3-46383.6" wire width 2 $1\fus_src6_i[1:0] - attribute \src "libresoc.v:46858.3-46866.6" + attribute \src "libresoc.v:46910.3-46918.6" wire $1\wr_pick_dly$1010$next[0:0]$2725 - attribute \src "libresoc.v:46867.3-46875.6" + attribute \src "libresoc.v:46919.3-46927.6" wire $1\wr_pick_dly$1031$next[0:0]$2728 - attribute \src "libresoc.v:46906.3-46914.6" + attribute \src "libresoc.v:46958.3-46966.6" wire $1\wr_pick_dly$1049$next[0:0]$2732 - attribute \src "libresoc.v:46915.3-46923.6" + attribute \src "libresoc.v:46967.3-46975.6" wire $1\wr_pick_dly$1071$next[0:0]$2735 - attribute \src "libresoc.v:46924.3-46932.6" + attribute \src "libresoc.v:46976.3-46984.6" wire $1\wr_pick_dly$1091$next[0:0]$2738 - attribute \src "libresoc.v:46962.3-46970.6" + attribute \src "libresoc.v:47014.3-47022.6" wire $1\wr_pick_dly$1111$next[0:0]$2742 - attribute \src "libresoc.v:46971.3-46979.6" + attribute \src "libresoc.v:47023.3-47031.6" wire $1\wr_pick_dly$1130$next[0:0]$2745 - attribute \src "libresoc.v:47009.3-47017.6" + attribute \src "libresoc.v:47061.3-47069.6" wire $1\wr_pick_dly$1148$next[0:0]$2749 - attribute \src "libresoc.v:47047.3-47055.6" + attribute \src "libresoc.v:47099.3-47107.6" wire $1\wr_pick_dly$1222$next[0:0]$2753 - attribute \src "libresoc.v:47085.3-47093.6" + attribute \src "libresoc.v:47137.3-47145.6" wire $1\wr_pick_dly$1250$next[0:0]$2757 - attribute \src "libresoc.v:47123.3-47131.6" + attribute \src "libresoc.v:47175.3-47183.6" wire $1\wr_pick_dly$1270$next[0:0]$2761 - attribute \src "libresoc.v:47132.3-47140.6" + attribute \src "libresoc.v:47184.3-47192.6" wire $1\wr_pick_dly$1290$next[0:0]$2764 - attribute \src "libresoc.v:47170.3-47178.6" + attribute \src "libresoc.v:47222.3-47230.6" wire $1\wr_pick_dly$1310$next[0:0]$2768 - attribute \src "libresoc.v:47179.3-47187.6" + attribute \src "libresoc.v:47231.3-47239.6" wire $1\wr_pick_dly$1330$next[0:0]$2771 - attribute \src "libresoc.v:47217.3-47225.6" + attribute \src "libresoc.v:47269.3-47277.6" wire $1\wr_pick_dly$1350$next[0:0]$2775 - attribute \src "libresoc.v:47255.3-47263.6" + attribute \src "libresoc.v:47307.3-47315.6" wire $1\wr_pick_dly$1397$next[0:0]$2779 - attribute \src "libresoc.v:47264.3-47272.6" + attribute \src "libresoc.v:47316.3-47324.6" wire $1\wr_pick_dly$1413$next[0:0]$2782 - attribute \src "libresoc.v:47302.3-47310.6" + attribute \src "libresoc.v:47354.3-47362.6" wire $1\wr_pick_dly$1429$next[0:0]$2786 - attribute \src "libresoc.v:47340.3-47348.6" + attribute \src "libresoc.v:47392.3-47400.6" wire $1\wr_pick_dly$1463$next[0:0]$2790 - attribute \src "libresoc.v:47378.3-47386.6" + attribute \src "libresoc.v:47430.3-47438.6" wire $1\wr_pick_dly$1479$next[0:0]$2794 - attribute \src "libresoc.v:47387.3-47395.6" + attribute \src "libresoc.v:47439.3-47447.6" wire $1\wr_pick_dly$1495$next[0:0]$2797 - attribute \src "libresoc.v:47425.3-47433.6" + attribute \src "libresoc.v:47477.3-47485.6" wire $1\wr_pick_dly$1511$next[0:0]$2801 - attribute \src "libresoc.v:47463.3-47471.6" + attribute \src "libresoc.v:47515.3-47523.6" wire $1\wr_pick_dly$1547$next[0:0]$2805 - attribute \src "libresoc.v:47472.3-47480.6" + attribute \src "libresoc.v:47524.3-47532.6" wire $1\wr_pick_dly$1563$next[0:0]$2808 - attribute \src "libresoc.v:47510.3-47518.6" + attribute \src "libresoc.v:47562.3-47570.6" wire $1\wr_pick_dly$1579$next[0:0]$2812 - attribute \src "libresoc.v:47519.3-47527.6" + attribute \src "libresoc.v:47571.3-47579.6" wire $1\wr_pick_dly$1595$next[0:0]$2815 - attribute \src "libresoc.v:47557.3-47565.6" + attribute \src "libresoc.v:47609.3-47617.6" wire $1\wr_pick_dly$1637$next[0:0]$2819 - attribute \src "libresoc.v:47595.3-47603.6" + attribute \src "libresoc.v:47647.3-47655.6" wire $1\wr_pick_dly$1656$next[0:0]$2827 - attribute \src "libresoc.v:47633.3-47641.6" + attribute \src "libresoc.v:47685.3-47693.6" wire $1\wr_pick_dly$1672$next[0:0]$2835 - attribute \src "libresoc.v:47642.3-47650.6" + attribute \src "libresoc.v:47694.3-47702.6" wire $1\wr_pick_dly$1688$next[0:0]$2838 - attribute \src "libresoc.v:47680.3-47688.6" + attribute \src "libresoc.v:47732.3-47740.6" wire $1\wr_pick_dly$1704$next[0:0]$2842 - attribute \src "libresoc.v:47718.3-47726.6" + attribute \src "libresoc.v:47770.3-47778.6" wire $1\wr_pick_dly$1748$next[0:0]$2846 - attribute \src "libresoc.v:47727.3-47735.6" + attribute \src "libresoc.v:47779.3-47787.6" wire $1\wr_pick_dly$1764$next[0:0]$2849 - attribute \src "libresoc.v:47765.3-47773.6" + attribute \src "libresoc.v:47817.3-47825.6" wire $1\wr_pick_dly$1788$next[0:0]$2853 - attribute \src "libresoc.v:47803.3-47811.6" + attribute \src "libresoc.v:47855.3-47863.6" wire $1\wr_pick_dly$1808$next[0:0]$2857 - attribute \src "libresoc.v:46819.3-46827.6" + attribute \src "libresoc.v:46871.3-46879.6" wire $1\wr_pick_dly$991$next[0:0]$2721 - attribute \src "libresoc.v:46810.3-46818.6" + attribute \src "libresoc.v:46862.3-46870.6" wire $1\wr_pick_dly$next[0:0]$2718 - attribute \src "libresoc.v:41724.7-41724.25" + attribute \src "libresoc.v:41772.7-41772.25" wire $1\wr_pick_dly[0:0] - attribute \src "libresoc.v:46587.3-46607.6" + attribute \src "libresoc.v:46639.3-46659.6" wire $2\core_terminate_o$next[0:0]$2675 - attribute \src "libresoc.v:46477.3-46567.6" + attribute \src "libresoc.v:46529.3-46619.6" wire $2\corebusy_o[0:0] - attribute \src "libresoc.v:46431.3-46457.6" + attribute \src "libresoc.v:46479.3-46509.6" wire width 2 $2\counter$next[1:0]$2656 - attribute \src "libresoc.v:47566.3-47594.6" + attribute \src "libresoc.v:47618.3-47646.6" wire $2\fus_cu_issue_i$13[0:0]$2823 - attribute \src "libresoc.v:47900.3-47928.6" + attribute \src "libresoc.v:47952.3-47980.6" wire $2\fus_cu_issue_i$16[0:0]$2864 - attribute \src "libresoc.v:48219.3-48247.6" + attribute \src "libresoc.v:48271.3-48299.6" wire $2\fus_cu_issue_i$19[0:0]$2883 - attribute \src "libresoc.v:43868.3-43896.6" + attribute \src "libresoc.v:43916.3-43944.6" wire $2\fus_cu_issue_i$22[0:0]$2361 - attribute \src "libresoc.v:44042.3-44070.6" + attribute \src "libresoc.v:44090.3-44118.6" wire $2\fus_cu_issue_i$25[0:0]$2375 - attribute \src "libresoc.v:44538.3-44566.6" + attribute \src "libresoc.v:44586.3-44614.6" wire $2\fus_cu_issue_i$28[0:0]$2400 - attribute \src "libresoc.v:44860.3-44888.6" + attribute \src "libresoc.v:44908.3-44936.6" wire $2\fus_cu_issue_i$31[0:0]$2419 - attribute \src "libresoc.v:45327.3-45355.6" + attribute \src "libresoc.v:45375.3-45403.6" wire $2\fus_cu_issue_i$34[0:0]$2443 - attribute \src "libresoc.v:45765.3-45793.6" + attribute \src "libresoc.v:45813.3-45841.6" wire $2\fus_cu_issue_i$37[0:0]$2466 - attribute \src "libresoc.v:47349.3-47377.6" + attribute \src "libresoc.v:47401.3-47429.6" wire $2\fus_cu_issue_i[0:0] - attribute \src "libresoc.v:47604.3-47632.6" + attribute \src "libresoc.v:47656.3-47684.6" wire width 6 $2\fus_cu_rdmaskn_i$15[5:0]$2831 - attribute \src "libresoc.v:47929.3-47957.6" + attribute \src "libresoc.v:47981.3-48009.6" wire width 3 $2\fus_cu_rdmaskn_i$18[2:0]$2869 - attribute \src "libresoc.v:48248.3-48276.6" + attribute \src "libresoc.v:48300.3-48328.6" wire width 4 $2\fus_cu_rdmaskn_i$21[3:0]$2888 - attribute \src "libresoc.v:43897.3-43925.6" + attribute \src "libresoc.v:43945.3-43973.6" wire width 3 $2\fus_cu_rdmaskn_i$24[2:0]$2366 - attribute \src "libresoc.v:44071.3-44099.6" + attribute \src "libresoc.v:44119.3-44147.6" wire width 6 $2\fus_cu_rdmaskn_i$27[5:0]$2380 - attribute \src "libresoc.v:44567.3-44595.6" + attribute \src "libresoc.v:44615.3-44643.6" wire width 3 $2\fus_cu_rdmaskn_i$30[2:0]$2405 - attribute \src "libresoc.v:44889.3-44917.6" + attribute \src "libresoc.v:44937.3-44965.6" wire width 3 $2\fus_cu_rdmaskn_i$33[2:0]$2424 - attribute \src "libresoc.v:45356.3-45384.6" + attribute \src "libresoc.v:45404.3-45432.6" wire width 5 $2\fus_cu_rdmaskn_i$36[4:0]$2448 - attribute \src "libresoc.v:45794.3-45822.6" + attribute \src "libresoc.v:45842.3-45870.6" wire width 3 $2\fus_cu_rdmaskn_i$39[2:0]$2471 - attribute \src "libresoc.v:47396.3-47424.6" + attribute \src "libresoc.v:47448.3-47476.6" wire width 4 $2\fus_cu_rdmaskn_i[3:0] - attribute \src "libresoc.v:47273.3-47301.6" + attribute \src "libresoc.v:47325.3-47353.6" wire width 4 $2\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "libresoc.v:46694.3-46722.6" + attribute \src "libresoc.v:46746.3-46774.6" wire width 14 $2\fus_oper_i_alu_alu0__fn_unit[13:0] - attribute \src "libresoc.v:46761.3-46790.6" + attribute \src "libresoc.v:46813.3-46842.6" wire width 64 $2\fus_oper_i_alu_alu0__imm_data__data[63:0] - attribute \src "libresoc.v:46761.3-46790.6" + attribute \src "libresoc.v:46813.3-46842.6" wire $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "libresoc.v:47094.3-47122.6" + attribute \src "libresoc.v:47146.3-47174.6" wire width 2 $2\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "libresoc.v:47311.3-47339.6" + attribute \src "libresoc.v:47363.3-47391.6" wire width 32 $2\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "libresoc.v:46646.3-46674.6" + attribute \src "libresoc.v:46698.3-46726.6" wire width 7 $2\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "libresoc.v:46933.3-46961.6" + attribute \src "libresoc.v:46985.3-47013.6" wire $2\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "libresoc.v:47018.3-47046.6" + attribute \src "libresoc.v:47070.3-47098.6" wire $2\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "libresoc.v:47188.3-47216.6" + attribute \src "libresoc.v:47240.3-47268.6" wire $2\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "libresoc.v:47226.3-47254.6" + attribute \src "libresoc.v:47278.3-47306.6" wire $2\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "libresoc.v:46876.3-46905.6" + attribute \src "libresoc.v:46928.3-46957.6" wire $2\fus_oper_i_alu_alu0__oe__oe[0:0] - attribute \src "libresoc.v:46876.3-46905.6" + attribute \src "libresoc.v:46928.3-46957.6" wire $2\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "libresoc.v:47141.3-47169.6" + attribute \src "libresoc.v:47193.3-47221.6" wire $2\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "libresoc.v:46828.3-46857.6" + attribute \src "libresoc.v:46880.3-46909.6" wire $2\fus_oper_i_alu_alu0__rc__ok[0:0] - attribute \src "libresoc.v:46828.3-46857.6" + attribute \src "libresoc.v:46880.3-46909.6" wire $2\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "libresoc.v:47056.3-47084.6" + attribute \src "libresoc.v:47108.3-47136.6" wire $2\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "libresoc.v:46980.3-47008.6" + attribute \src "libresoc.v:47032.3-47060.6" wire $2\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "libresoc.v:47651.3-47679.6" + attribute \src "libresoc.v:47703.3-47731.6" wire width 64 $2\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "libresoc.v:47736.3-47764.6" + attribute \src "libresoc.v:47788.3-47816.6" wire width 14 $2\fus_oper_i_alu_branch0__fn_unit[13:0] - attribute \src "libresoc.v:47812.3-47841.6" + attribute \src "libresoc.v:47864.3-47893.6" wire width 64 $2\fus_oper_i_alu_branch0__imm_data__data[63:0] - attribute \src "libresoc.v:47812.3-47841.6" + attribute \src "libresoc.v:47864.3-47893.6" wire $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "libresoc.v:47774.3-47802.6" + attribute \src "libresoc.v:47826.3-47854.6" wire width 32 $2\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "libresoc.v:47689.3-47717.6" + attribute \src "libresoc.v:47741.3-47769.6" wire width 7 $2\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "libresoc.v:47871.3-47899.6" + attribute \src "libresoc.v:47923.3-47951.6" wire $2\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "libresoc.v:47842.3-47870.6" + attribute \src "libresoc.v:47894.3-47922.6" wire $2\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "libresoc.v:47481.3-47509.6" + attribute \src "libresoc.v:47533.3-47561.6" wire width 14 $2\fus_oper_i_alu_cr0__fn_unit[13:0] - attribute \src "libresoc.v:47528.3-47556.6" + attribute \src "libresoc.v:47580.3-47608.6" wire width 32 $2\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "libresoc.v:47434.3-47462.6" + attribute \src "libresoc.v:47486.3-47514.6" wire width 7 $2\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "libresoc.v:44480.3-44508.6" + attribute \src "libresoc.v:44528.3-44556.6" wire width 4 $2\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "libresoc.v:44129.3-44157.6" + attribute \src "libresoc.v:44177.3-44205.6" wire width 14 $2\fus_oper_i_alu_div0__fn_unit[13:0] - attribute \src "libresoc.v:44158.3-44187.6" + attribute \src "libresoc.v:44206.3-44235.6" wire width 64 $2\fus_oper_i_alu_div0__imm_data__data[63:0] - attribute \src "libresoc.v:44158.3-44187.6" + attribute \src "libresoc.v:44206.3-44235.6" wire $2\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "libresoc.v:44306.3-44334.6" + attribute \src "libresoc.v:44354.3-44382.6" wire width 2 $2\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "libresoc.v:44509.3-44537.6" + attribute \src "libresoc.v:44557.3-44585.6" wire width 32 $2\fus_oper_i_alu_div0__insn[31:0] - attribute \src "libresoc.v:44100.3-44128.6" + attribute \src "libresoc.v:44148.3-44176.6" wire width 7 $2\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "libresoc.v:44248.3-44276.6" + attribute \src "libresoc.v:44296.3-44324.6" wire $2\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "libresoc.v:44335.3-44363.6" + attribute \src "libresoc.v:44383.3-44411.6" wire $2\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "libresoc.v:44422.3-44450.6" + attribute \src "libresoc.v:44470.3-44498.6" wire $2\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "libresoc.v:44451.3-44479.6" + attribute \src "libresoc.v:44499.3-44527.6" wire $2\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "libresoc.v:44218.3-44247.6" + attribute \src "libresoc.v:44266.3-44295.6" wire $2\fus_oper_i_alu_div0__oe__oe[0:0] - attribute \src "libresoc.v:44218.3-44247.6" + attribute \src "libresoc.v:44266.3-44295.6" wire $2\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "libresoc.v:44393.3-44421.6" + attribute \src "libresoc.v:44441.3-44469.6" wire $2\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "libresoc.v:44188.3-44217.6" + attribute \src "libresoc.v:44236.3-44265.6" wire $2\fus_oper_i_alu_div0__rc__ok[0:0] - attribute \src "libresoc.v:44188.3-44217.6" + attribute \src "libresoc.v:44236.3-44265.6" wire $2\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "libresoc.v:44364.3-44392.6" + attribute \src "libresoc.v:44412.3-44440.6" wire $2\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "libresoc.v:44277.3-44305.6" + attribute \src "libresoc.v:44325.3-44353.6" wire $2\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "libresoc.v:43810.3-43838.6" + attribute \src "libresoc.v:43858.3-43886.6" wire width 4 $2\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "libresoc.v:48306.3-48334.6" + attribute \src "libresoc.v:48358.3-48386.6" wire width 14 $2\fus_oper_i_alu_logical0__fn_unit[13:0] - attribute \src "libresoc.v:48335.3-48364.6" + attribute \src "libresoc.v:48387.3-48416.6" wire width 64 $2\fus_oper_i_alu_logical0__imm_data__data[63:0] - attribute \src "libresoc.v:48335.3-48364.6" + attribute \src "libresoc.v:48387.3-48416.6" wire $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "libresoc.v:48483.3-48511.6" + attribute \src "libresoc.v:48535.3-48563.6" wire width 2 $2\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "libresoc.v:43839.3-43867.6" + attribute \src "libresoc.v:43887.3-43915.6" wire width 32 $2\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "libresoc.v:48277.3-48305.6" + attribute \src "libresoc.v:48329.3-48357.6" wire width 7 $2\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "libresoc.v:48425.3-48453.6" + attribute \src "libresoc.v:48477.3-48505.6" wire $2\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "libresoc.v:48512.3-48540.6" + attribute \src "libresoc.v:48564.3-48592.6" wire $2\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "libresoc.v:43752.3-43780.6" + attribute \src "libresoc.v:43800.3-43828.6" wire $2\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "libresoc.v:43781.3-43809.6" + attribute \src "libresoc.v:43829.3-43857.6" wire $2\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "libresoc.v:48395.3-48424.6" + attribute \src "libresoc.v:48447.3-48476.6" wire $2\fus_oper_i_alu_logical0__oe__oe[0:0] - attribute \src "libresoc.v:48395.3-48424.6" + attribute \src "libresoc.v:48447.3-48476.6" wire $2\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "libresoc.v:43723.3-43751.6" + attribute \src "libresoc.v:43771.3-43799.6" wire $2\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "libresoc.v:48365.3-48394.6" + attribute \src "libresoc.v:48417.3-48446.6" wire $2\fus_oper_i_alu_logical0__rc__ok[0:0] - attribute \src "libresoc.v:48365.3-48394.6" + attribute \src "libresoc.v:48417.3-48446.6" wire $2\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "libresoc.v:48541.3-48569.6" + attribute \src "libresoc.v:48593.3-48621.6" wire $2\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "libresoc.v:48454.3-48482.6" + attribute \src "libresoc.v:48506.3-48534.6" wire $2\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "libresoc.v:44625.3-44653.6" + attribute \src "libresoc.v:44673.3-44701.6" wire width 14 $2\fus_oper_i_alu_mul0__fn_unit[13:0] - attribute \src "libresoc.v:44654.3-44683.6" + attribute \src "libresoc.v:44702.3-44731.6" wire width 64 $2\fus_oper_i_alu_mul0__imm_data__data[63:0] - attribute \src "libresoc.v:44654.3-44683.6" + attribute \src "libresoc.v:44702.3-44731.6" wire $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "libresoc.v:44831.3-44859.6" + attribute \src "libresoc.v:44879.3-44907.6" wire width 32 $2\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "libresoc.v:44596.3-44624.6" + attribute \src "libresoc.v:44644.3-44672.6" wire width 7 $2\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "libresoc.v:44773.3-44801.6" + attribute \src "libresoc.v:44821.3-44849.6" wire $2\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "libresoc.v:44802.3-44830.6" + attribute \src "libresoc.v:44850.3-44878.6" wire $2\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "libresoc.v:44714.3-44743.6" + attribute \src "libresoc.v:44762.3-44791.6" wire $2\fus_oper_i_alu_mul0__oe__oe[0:0] - attribute \src "libresoc.v:44714.3-44743.6" + attribute \src "libresoc.v:44762.3-44791.6" wire $2\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "libresoc.v:44684.3-44713.6" + attribute \src "libresoc.v:44732.3-44761.6" wire $2\fus_oper_i_alu_mul0__rc__ok[0:0] - attribute \src "libresoc.v:44684.3-44713.6" + attribute \src "libresoc.v:44732.3-44761.6" wire $2\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "libresoc.v:44744.3-44772.6" + attribute \src "libresoc.v:44792.3-44820.6" wire $2\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "libresoc.v:44947.3-44975.6" + attribute \src "libresoc.v:44995.3-45023.6" wire width 14 $2\fus_oper_i_alu_shift_rot0__fn_unit[13:0] - attribute \src "libresoc.v:44976.3-45005.6" + attribute \src "libresoc.v:45024.3-45053.6" wire width 64 $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] - attribute \src "libresoc.v:44976.3-45005.6" + attribute \src "libresoc.v:45024.3-45053.6" wire $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "libresoc.v:45124.3-45152.6" + attribute \src "libresoc.v:45172.3-45200.6" wire width 2 $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "libresoc.v:45182.3-45210.6" + attribute \src "libresoc.v:45230.3-45258.6" wire $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "libresoc.v:45298.3-45326.6" + attribute \src "libresoc.v:45346.3-45374.6" wire width 32 $2\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "libresoc.v:44918.3-44946.6" + attribute \src "libresoc.v:44966.3-44994.6" wire width 7 $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "libresoc.v:45095.3-45123.6" + attribute \src "libresoc.v:45143.3-45171.6" wire $2\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "libresoc.v:45240.3-45268.6" + attribute \src "libresoc.v:45288.3-45316.6" wire $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "libresoc.v:45269.3-45297.6" + attribute \src "libresoc.v:45317.3-45345.6" wire $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "libresoc.v:45036.3-45065.6" + attribute \src "libresoc.v:45084.3-45113.6" wire $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] - attribute \src "libresoc.v:45036.3-45065.6" + attribute \src "libresoc.v:45084.3-45113.6" wire $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "libresoc.v:45153.3-45181.6" + attribute \src "libresoc.v:45201.3-45229.6" wire $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "libresoc.v:45211.3-45239.6" + attribute \src "libresoc.v:45259.3-45287.6" wire $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "libresoc.v:45006.3-45035.6" + attribute \src "libresoc.v:45054.3-45083.6" wire $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] - attribute \src "libresoc.v:45006.3-45035.6" + attribute \src "libresoc.v:45054.3-45083.6" wire $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "libresoc.v:45066.3-45094.6" + attribute \src "libresoc.v:45114.3-45142.6" wire $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "libresoc.v:43955.3-43983.6" + attribute \src "libresoc.v:44003.3-44031.6" wire width 14 $2\fus_oper_i_alu_spr0__fn_unit[13:0] - attribute \src "libresoc.v:43984.3-44012.6" + attribute \src "libresoc.v:44032.3-44060.6" wire width 32 $2\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "libresoc.v:43926.3-43954.6" + attribute \src "libresoc.v:43974.3-44002.6" wire width 7 $2\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "libresoc.v:44013.3-44041.6" + attribute \src "libresoc.v:44061.3-44089.6" wire $2\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "libresoc.v:48074.3-48102.6" + attribute \src "libresoc.v:48126.3-48154.6" wire width 64 $2\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "libresoc.v:47987.3-48015.6" + attribute \src "libresoc.v:48039.3-48067.6" wire width 14 $2\fus_oper_i_alu_trap0__fn_unit[13:0] - attribute \src "libresoc.v:48016.3-48044.6" + attribute \src "libresoc.v:48068.3-48096.6" wire width 32 $2\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "libresoc.v:47958.3-47986.6" + attribute \src "libresoc.v:48010.3-48038.6" wire width 7 $2\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "libresoc.v:48103.3-48131.6" + attribute \src "libresoc.v:48155.3-48183.6" wire $2\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "libresoc.v:48190.3-48218.6" + attribute \src "libresoc.v:48242.3-48270.6" wire width 8 $2\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "libresoc.v:48045.3-48073.6" + attribute \src "libresoc.v:48097.3-48125.6" wire width 64 $2\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "libresoc.v:48161.3-48189.6" + attribute \src "libresoc.v:48213.3-48241.6" wire width 13 $2\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "libresoc.v:48132.3-48160.6" + attribute \src "libresoc.v:48184.3-48212.6" wire width 8 $2\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "libresoc.v:45649.3-45677.6" + attribute \src "libresoc.v:45697.3-45725.6" wire $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "libresoc.v:45620.3-45648.6" + attribute \src "libresoc.v:45668.3-45696.6" wire width 4 $2\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "libresoc.v:45414.3-45442.6" + attribute \src "libresoc.v:45462.3-45490.6" wire width 14 $2\fus_oper_i_ldst_ldst0__fn_unit[13:0] - attribute \src "libresoc.v:45443.3-45472.6" + attribute \src "libresoc.v:45491.3-45520.6" wire width 64 $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] - attribute \src "libresoc.v:45443.3-45472.6" + attribute \src "libresoc.v:45491.3-45520.6" wire $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "libresoc.v:45736.3-45764.6" + attribute \src "libresoc.v:45784.3-45812.6" wire width 32 $2\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "libresoc.v:45385.3-45413.6" + attribute \src "libresoc.v:45433.3-45461.6" wire width 7 $2\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "libresoc.v:45562.3-45590.6" + attribute \src "libresoc.v:45610.3-45638.6" wire $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "libresoc.v:45591.3-45619.6" + attribute \src "libresoc.v:45639.3-45667.6" wire $2\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "libresoc.v:45707.3-45735.6" + attribute \src "libresoc.v:45755.3-45783.6" wire width 2 $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "libresoc.v:45532.3-45561.6" + attribute \src "libresoc.v:45580.3-45609.6" wire $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] - attribute \src "libresoc.v:45532.3-45561.6" + attribute \src "libresoc.v:45580.3-45609.6" wire $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "libresoc.v:45502.3-45531.6" + attribute \src "libresoc.v:45550.3-45579.6" wire $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] - attribute \src "libresoc.v:45502.3-45531.6" + attribute \src "libresoc.v:45550.3-45579.6" wire $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "libresoc.v:45678.3-45706.6" + attribute \src "libresoc.v:45726.3-45754.6" wire $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "libresoc.v:45473.3-45501.6" + attribute \src "libresoc.v:45521.3-45549.6" wire $2\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "libresoc.v:46587.3-46607.6" + attribute \src "libresoc.v:46639.3-46659.6" wire $3\core_terminate_o$next[0:0]$2676 - attribute \src "libresoc.v:46477.3-46567.6" + attribute \src "libresoc.v:46529.3-46619.6" wire $3\corebusy_o[0:0] - attribute \src "libresoc.v:46431.3-46457.6" + attribute \src "libresoc.v:46479.3-46509.6" wire width 2 $3\counter$next[1:0]$2657 - attribute \src "libresoc.v:47566.3-47594.6" + attribute \src "libresoc.v:47618.3-47646.6" wire $3\fus_cu_issue_i$13[0:0]$2824 - attribute \src "libresoc.v:47900.3-47928.6" + attribute \src "libresoc.v:47952.3-47980.6" wire $3\fus_cu_issue_i$16[0:0]$2865 - attribute \src "libresoc.v:48219.3-48247.6" + attribute \src "libresoc.v:48271.3-48299.6" wire $3\fus_cu_issue_i$19[0:0]$2884 - attribute \src "libresoc.v:43868.3-43896.6" + attribute \src "libresoc.v:43916.3-43944.6" wire $3\fus_cu_issue_i$22[0:0]$2362 - attribute \src "libresoc.v:44042.3-44070.6" + attribute \src "libresoc.v:44090.3-44118.6" wire $3\fus_cu_issue_i$25[0:0]$2376 - attribute \src "libresoc.v:44538.3-44566.6" + attribute \src "libresoc.v:44586.3-44614.6" wire $3\fus_cu_issue_i$28[0:0]$2401 - attribute \src "libresoc.v:44860.3-44888.6" + attribute \src "libresoc.v:44908.3-44936.6" wire $3\fus_cu_issue_i$31[0:0]$2420 - attribute \src "libresoc.v:45327.3-45355.6" + attribute \src "libresoc.v:45375.3-45403.6" wire $3\fus_cu_issue_i$34[0:0]$2444 - attribute \src "libresoc.v:45765.3-45793.6" + attribute \src "libresoc.v:45813.3-45841.6" wire $3\fus_cu_issue_i$37[0:0]$2467 - attribute \src "libresoc.v:47349.3-47377.6" + attribute \src "libresoc.v:47401.3-47429.6" wire $3\fus_cu_issue_i[0:0] - attribute \src "libresoc.v:47604.3-47632.6" + attribute \src "libresoc.v:47656.3-47684.6" wire width 6 $3\fus_cu_rdmaskn_i$15[5:0]$2832 - attribute \src "libresoc.v:47929.3-47957.6" + attribute \src "libresoc.v:47981.3-48009.6" wire width 3 $3\fus_cu_rdmaskn_i$18[2:0]$2870 - attribute \src "libresoc.v:48248.3-48276.6" + attribute \src "libresoc.v:48300.3-48328.6" wire width 4 $3\fus_cu_rdmaskn_i$21[3:0]$2889 - attribute \src "libresoc.v:43897.3-43925.6" + attribute \src "libresoc.v:43945.3-43973.6" wire width 3 $3\fus_cu_rdmaskn_i$24[2:0]$2367 - attribute \src "libresoc.v:44071.3-44099.6" + attribute \src "libresoc.v:44119.3-44147.6" wire width 6 $3\fus_cu_rdmaskn_i$27[5:0]$2381 - attribute \src "libresoc.v:44567.3-44595.6" + attribute \src "libresoc.v:44615.3-44643.6" wire width 3 $3\fus_cu_rdmaskn_i$30[2:0]$2406 - attribute \src "libresoc.v:44889.3-44917.6" + attribute \src "libresoc.v:44937.3-44965.6" wire width 3 $3\fus_cu_rdmaskn_i$33[2:0]$2425 - attribute \src "libresoc.v:45356.3-45384.6" + attribute \src "libresoc.v:45404.3-45432.6" wire width 5 $3\fus_cu_rdmaskn_i$36[4:0]$2449 - attribute \src "libresoc.v:45794.3-45822.6" + attribute \src "libresoc.v:45842.3-45870.6" wire width 3 $3\fus_cu_rdmaskn_i$39[2:0]$2472 - attribute \src "libresoc.v:47396.3-47424.6" + attribute \src "libresoc.v:47448.3-47476.6" wire width 4 $3\fus_cu_rdmaskn_i[3:0] - attribute \src "libresoc.v:47273.3-47301.6" + attribute \src "libresoc.v:47325.3-47353.6" wire width 4 $3\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "libresoc.v:46694.3-46722.6" + attribute \src "libresoc.v:46746.3-46774.6" wire width 14 $3\fus_oper_i_alu_alu0__fn_unit[13:0] - attribute \src "libresoc.v:46761.3-46790.6" + attribute \src "libresoc.v:46813.3-46842.6" wire width 64 $3\fus_oper_i_alu_alu0__imm_data__data[63:0] - attribute \src "libresoc.v:46761.3-46790.6" + attribute \src "libresoc.v:46813.3-46842.6" wire $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "libresoc.v:47094.3-47122.6" + attribute \src "libresoc.v:47146.3-47174.6" wire width 2 $3\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "libresoc.v:47311.3-47339.6" + attribute \src "libresoc.v:47363.3-47391.6" wire width 32 $3\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "libresoc.v:46646.3-46674.6" + attribute \src "libresoc.v:46698.3-46726.6" wire width 7 $3\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "libresoc.v:46933.3-46961.6" + attribute \src "libresoc.v:46985.3-47013.6" wire $3\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "libresoc.v:47018.3-47046.6" + attribute \src "libresoc.v:47070.3-47098.6" wire $3\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "libresoc.v:47188.3-47216.6" + attribute \src "libresoc.v:47240.3-47268.6" wire $3\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "libresoc.v:47226.3-47254.6" + attribute \src "libresoc.v:47278.3-47306.6" wire $3\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "libresoc.v:46876.3-46905.6" + attribute \src "libresoc.v:46928.3-46957.6" wire $3\fus_oper_i_alu_alu0__oe__oe[0:0] - attribute \src "libresoc.v:46876.3-46905.6" + attribute \src "libresoc.v:46928.3-46957.6" wire $3\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "libresoc.v:47141.3-47169.6" + attribute \src "libresoc.v:47193.3-47221.6" wire $3\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "libresoc.v:46828.3-46857.6" + attribute \src "libresoc.v:46880.3-46909.6" wire $3\fus_oper_i_alu_alu0__rc__ok[0:0] - attribute \src "libresoc.v:46828.3-46857.6" + attribute \src "libresoc.v:46880.3-46909.6" wire $3\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "libresoc.v:47056.3-47084.6" + attribute \src "libresoc.v:47108.3-47136.6" wire $3\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "libresoc.v:46980.3-47008.6" + attribute \src "libresoc.v:47032.3-47060.6" wire $3\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "libresoc.v:47651.3-47679.6" + attribute \src "libresoc.v:47703.3-47731.6" wire width 64 $3\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "libresoc.v:47736.3-47764.6" + attribute \src "libresoc.v:47788.3-47816.6" wire width 14 $3\fus_oper_i_alu_branch0__fn_unit[13:0] - attribute \src "libresoc.v:47812.3-47841.6" + attribute \src "libresoc.v:47864.3-47893.6" wire width 64 $3\fus_oper_i_alu_branch0__imm_data__data[63:0] - attribute \src "libresoc.v:47812.3-47841.6" + attribute \src "libresoc.v:47864.3-47893.6" wire $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "libresoc.v:47774.3-47802.6" + attribute \src "libresoc.v:47826.3-47854.6" wire width 32 $3\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "libresoc.v:47689.3-47717.6" + attribute \src "libresoc.v:47741.3-47769.6" wire width 7 $3\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "libresoc.v:47871.3-47899.6" + attribute \src "libresoc.v:47923.3-47951.6" wire $3\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "libresoc.v:47842.3-47870.6" + attribute \src "libresoc.v:47894.3-47922.6" wire $3\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "libresoc.v:47481.3-47509.6" + attribute \src "libresoc.v:47533.3-47561.6" wire width 14 $3\fus_oper_i_alu_cr0__fn_unit[13:0] - attribute \src "libresoc.v:47528.3-47556.6" + attribute \src "libresoc.v:47580.3-47608.6" wire width 32 $3\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "libresoc.v:47434.3-47462.6" + attribute \src "libresoc.v:47486.3-47514.6" wire width 7 $3\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "libresoc.v:44480.3-44508.6" + attribute \src "libresoc.v:44528.3-44556.6" wire width 4 $3\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "libresoc.v:44129.3-44157.6" + attribute \src "libresoc.v:44177.3-44205.6" wire width 14 $3\fus_oper_i_alu_div0__fn_unit[13:0] - attribute \src "libresoc.v:44158.3-44187.6" + attribute \src "libresoc.v:44206.3-44235.6" wire width 64 $3\fus_oper_i_alu_div0__imm_data__data[63:0] - attribute \src "libresoc.v:44158.3-44187.6" + attribute \src "libresoc.v:44206.3-44235.6" wire $3\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "libresoc.v:44306.3-44334.6" + attribute \src "libresoc.v:44354.3-44382.6" wire width 2 $3\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "libresoc.v:44509.3-44537.6" + attribute \src "libresoc.v:44557.3-44585.6" wire width 32 $3\fus_oper_i_alu_div0__insn[31:0] - attribute \src "libresoc.v:44100.3-44128.6" + attribute \src "libresoc.v:44148.3-44176.6" wire width 7 $3\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "libresoc.v:44248.3-44276.6" + attribute \src "libresoc.v:44296.3-44324.6" wire $3\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "libresoc.v:44335.3-44363.6" + attribute \src "libresoc.v:44383.3-44411.6" wire $3\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "libresoc.v:44422.3-44450.6" + attribute \src "libresoc.v:44470.3-44498.6" wire $3\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "libresoc.v:44451.3-44479.6" + attribute \src "libresoc.v:44499.3-44527.6" wire $3\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "libresoc.v:44218.3-44247.6" + attribute \src "libresoc.v:44266.3-44295.6" wire $3\fus_oper_i_alu_div0__oe__oe[0:0] - attribute \src "libresoc.v:44218.3-44247.6" + attribute \src "libresoc.v:44266.3-44295.6" wire $3\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "libresoc.v:44393.3-44421.6" + attribute \src "libresoc.v:44441.3-44469.6" wire $3\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "libresoc.v:44188.3-44217.6" + attribute \src "libresoc.v:44236.3-44265.6" wire $3\fus_oper_i_alu_div0__rc__ok[0:0] - attribute \src "libresoc.v:44188.3-44217.6" + attribute \src "libresoc.v:44236.3-44265.6" wire $3\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "libresoc.v:44364.3-44392.6" + attribute \src "libresoc.v:44412.3-44440.6" wire $3\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "libresoc.v:44277.3-44305.6" + attribute \src "libresoc.v:44325.3-44353.6" wire $3\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "libresoc.v:43810.3-43838.6" + attribute \src "libresoc.v:43858.3-43886.6" wire width 4 $3\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "libresoc.v:48306.3-48334.6" + attribute \src "libresoc.v:48358.3-48386.6" wire width 14 $3\fus_oper_i_alu_logical0__fn_unit[13:0] - attribute \src "libresoc.v:48335.3-48364.6" + attribute \src "libresoc.v:48387.3-48416.6" wire width 64 $3\fus_oper_i_alu_logical0__imm_data__data[63:0] - attribute \src "libresoc.v:48335.3-48364.6" + attribute \src "libresoc.v:48387.3-48416.6" wire $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "libresoc.v:48483.3-48511.6" + attribute \src "libresoc.v:48535.3-48563.6" wire width 2 $3\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "libresoc.v:43839.3-43867.6" + attribute \src "libresoc.v:43887.3-43915.6" wire width 32 $3\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "libresoc.v:48277.3-48305.6" + attribute \src "libresoc.v:48329.3-48357.6" wire width 7 $3\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "libresoc.v:48425.3-48453.6" + attribute \src "libresoc.v:48477.3-48505.6" wire $3\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "libresoc.v:48512.3-48540.6" + attribute \src "libresoc.v:48564.3-48592.6" wire $3\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "libresoc.v:43752.3-43780.6" + attribute \src "libresoc.v:43800.3-43828.6" wire $3\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "libresoc.v:43781.3-43809.6" + attribute \src "libresoc.v:43829.3-43857.6" wire $3\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "libresoc.v:48395.3-48424.6" + attribute \src "libresoc.v:48447.3-48476.6" wire $3\fus_oper_i_alu_logical0__oe__oe[0:0] - attribute \src "libresoc.v:48395.3-48424.6" + attribute \src "libresoc.v:48447.3-48476.6" wire $3\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "libresoc.v:43723.3-43751.6" + attribute \src "libresoc.v:43771.3-43799.6" wire $3\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "libresoc.v:48365.3-48394.6" + attribute \src "libresoc.v:48417.3-48446.6" wire $3\fus_oper_i_alu_logical0__rc__ok[0:0] - attribute \src "libresoc.v:48365.3-48394.6" + attribute \src "libresoc.v:48417.3-48446.6" wire $3\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "libresoc.v:48541.3-48569.6" + attribute \src "libresoc.v:48593.3-48621.6" wire $3\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "libresoc.v:48454.3-48482.6" + attribute \src "libresoc.v:48506.3-48534.6" wire $3\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "libresoc.v:44625.3-44653.6" + attribute \src "libresoc.v:44673.3-44701.6" wire width 14 $3\fus_oper_i_alu_mul0__fn_unit[13:0] - attribute \src "libresoc.v:44654.3-44683.6" + attribute \src "libresoc.v:44702.3-44731.6" wire width 64 $3\fus_oper_i_alu_mul0__imm_data__data[63:0] - attribute \src "libresoc.v:44654.3-44683.6" + attribute \src "libresoc.v:44702.3-44731.6" wire $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "libresoc.v:44831.3-44859.6" + attribute \src "libresoc.v:44879.3-44907.6" wire width 32 $3\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "libresoc.v:44596.3-44624.6" + attribute \src "libresoc.v:44644.3-44672.6" wire width 7 $3\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "libresoc.v:44773.3-44801.6" + attribute \src "libresoc.v:44821.3-44849.6" wire $3\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "libresoc.v:44802.3-44830.6" + attribute \src "libresoc.v:44850.3-44878.6" wire $3\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "libresoc.v:44714.3-44743.6" + attribute \src "libresoc.v:44762.3-44791.6" wire $3\fus_oper_i_alu_mul0__oe__oe[0:0] - attribute \src "libresoc.v:44714.3-44743.6" + attribute \src "libresoc.v:44762.3-44791.6" wire $3\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "libresoc.v:44684.3-44713.6" + attribute \src "libresoc.v:44732.3-44761.6" wire $3\fus_oper_i_alu_mul0__rc__ok[0:0] - attribute \src "libresoc.v:44684.3-44713.6" + attribute \src "libresoc.v:44732.3-44761.6" wire $3\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "libresoc.v:44744.3-44772.6" + attribute \src "libresoc.v:44792.3-44820.6" wire $3\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "libresoc.v:44947.3-44975.6" + attribute \src "libresoc.v:44995.3-45023.6" wire width 14 $3\fus_oper_i_alu_shift_rot0__fn_unit[13:0] - attribute \src "libresoc.v:44976.3-45005.6" + attribute \src "libresoc.v:45024.3-45053.6" wire width 64 $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] - attribute \src "libresoc.v:44976.3-45005.6" + attribute \src "libresoc.v:45024.3-45053.6" wire $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "libresoc.v:45124.3-45152.6" + attribute \src "libresoc.v:45172.3-45200.6" wire width 2 $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "libresoc.v:45182.3-45210.6" + attribute \src "libresoc.v:45230.3-45258.6" wire $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "libresoc.v:45298.3-45326.6" + attribute \src "libresoc.v:45346.3-45374.6" wire width 32 $3\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "libresoc.v:44918.3-44946.6" + attribute \src "libresoc.v:44966.3-44994.6" wire width 7 $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "libresoc.v:45095.3-45123.6" + attribute \src "libresoc.v:45143.3-45171.6" wire $3\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "libresoc.v:45240.3-45268.6" + attribute \src "libresoc.v:45288.3-45316.6" wire $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "libresoc.v:45269.3-45297.6" + attribute \src "libresoc.v:45317.3-45345.6" wire $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "libresoc.v:45036.3-45065.6" + attribute \src "libresoc.v:45084.3-45113.6" wire $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] - attribute \src "libresoc.v:45036.3-45065.6" + attribute \src "libresoc.v:45084.3-45113.6" wire $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "libresoc.v:45153.3-45181.6" + attribute \src "libresoc.v:45201.3-45229.6" wire $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "libresoc.v:45211.3-45239.6" + attribute \src "libresoc.v:45259.3-45287.6" wire $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "libresoc.v:45006.3-45035.6" + attribute \src "libresoc.v:45054.3-45083.6" wire $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] - attribute \src "libresoc.v:45006.3-45035.6" + attribute \src "libresoc.v:45054.3-45083.6" wire $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "libresoc.v:45066.3-45094.6" + attribute \src "libresoc.v:45114.3-45142.6" wire $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "libresoc.v:43955.3-43983.6" + attribute \src "libresoc.v:44003.3-44031.6" wire width 14 $3\fus_oper_i_alu_spr0__fn_unit[13:0] - attribute \src "libresoc.v:43984.3-44012.6" + attribute \src "libresoc.v:44032.3-44060.6" wire width 32 $3\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "libresoc.v:43926.3-43954.6" + attribute \src "libresoc.v:43974.3-44002.6" wire width 7 $3\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "libresoc.v:44013.3-44041.6" + attribute \src "libresoc.v:44061.3-44089.6" wire $3\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "libresoc.v:48074.3-48102.6" + attribute \src "libresoc.v:48126.3-48154.6" wire width 64 $3\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "libresoc.v:47987.3-48015.6" + attribute \src "libresoc.v:48039.3-48067.6" wire width 14 $3\fus_oper_i_alu_trap0__fn_unit[13:0] - attribute \src "libresoc.v:48016.3-48044.6" + attribute \src "libresoc.v:48068.3-48096.6" wire width 32 $3\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "libresoc.v:47958.3-47986.6" + attribute \src "libresoc.v:48010.3-48038.6" wire width 7 $3\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "libresoc.v:48103.3-48131.6" + attribute \src "libresoc.v:48155.3-48183.6" wire $3\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "libresoc.v:48190.3-48218.6" + attribute \src "libresoc.v:48242.3-48270.6" wire width 8 $3\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "libresoc.v:48045.3-48073.6" + attribute \src "libresoc.v:48097.3-48125.6" wire width 64 $3\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "libresoc.v:48161.3-48189.6" + attribute \src "libresoc.v:48213.3-48241.6" wire width 13 $3\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "libresoc.v:48132.3-48160.6" + attribute \src "libresoc.v:48184.3-48212.6" wire width 8 $3\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "libresoc.v:45649.3-45677.6" + attribute \src "libresoc.v:45697.3-45725.6" wire $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "libresoc.v:45620.3-45648.6" + attribute \src "libresoc.v:45668.3-45696.6" wire width 4 $3\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "libresoc.v:45414.3-45442.6" + attribute \src "libresoc.v:45462.3-45490.6" wire width 14 $3\fus_oper_i_ldst_ldst0__fn_unit[13:0] - attribute \src "libresoc.v:45443.3-45472.6" + attribute \src "libresoc.v:45491.3-45520.6" wire width 64 $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] - attribute \src "libresoc.v:45443.3-45472.6" + attribute \src "libresoc.v:45491.3-45520.6" wire $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "libresoc.v:45736.3-45764.6" + attribute \src "libresoc.v:45784.3-45812.6" wire width 32 $3\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "libresoc.v:45385.3-45413.6" + attribute \src "libresoc.v:45433.3-45461.6" wire width 7 $3\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "libresoc.v:45562.3-45590.6" + attribute \src "libresoc.v:45610.3-45638.6" wire $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "libresoc.v:45591.3-45619.6" + attribute \src "libresoc.v:45639.3-45667.6" wire $3\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "libresoc.v:45707.3-45735.6" + attribute \src "libresoc.v:45755.3-45783.6" wire width 2 $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "libresoc.v:45532.3-45561.6" + attribute \src "libresoc.v:45580.3-45609.6" wire $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] - attribute \src "libresoc.v:45532.3-45561.6" + attribute \src "libresoc.v:45580.3-45609.6" wire $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "libresoc.v:45502.3-45531.6" + attribute \src "libresoc.v:45550.3-45579.6" wire $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] - attribute \src "libresoc.v:45502.3-45531.6" + attribute \src "libresoc.v:45550.3-45579.6" wire $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "libresoc.v:45678.3-45706.6" + attribute \src "libresoc.v:45726.3-45754.6" wire $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "libresoc.v:45473.3-45501.6" + attribute \src "libresoc.v:45521.3-45549.6" wire $3\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "libresoc.v:46477.3-46567.6" + attribute \src "libresoc.v:46529.3-46619.6" wire $4\corebusy_o[0:0] - attribute \src "libresoc.v:46431.3-46457.6" + attribute \src "libresoc.v:46479.3-46509.6" wire width 2 $4\counter$next[1:0]$2658 - attribute \src "libresoc.v:46477.3-46567.6" + attribute \src "libresoc.v:46529.3-46619.6" wire $5\corebusy_o[0:0] - attribute \src "libresoc.v:46477.3-46567.6" + attribute \src "libresoc.v:46529.3-46619.6" wire $6\corebusy_o[0:0] - attribute \src "libresoc.v:46477.3-46567.6" + attribute \src "libresoc.v:46529.3-46619.6" wire $7\corebusy_o[0:0] - attribute \src "libresoc.v:46477.3-46567.6" + attribute \src "libresoc.v:46529.3-46619.6" wire $8\corebusy_o[0:0] - attribute \src "libresoc.v:46477.3-46567.6" + attribute \src "libresoc.v:46529.3-46619.6" wire $9\corebusy_o[0:0] - attribute \src "libresoc.v:42103.20-42103.122" - wire $and$libresoc.v:42103$1506_Y - attribute \src "libresoc.v:42105.20-42105.122" - wire $and$libresoc.v:42105$1508_Y - attribute \src "libresoc.v:42106.20-42106.126" - wire $and$libresoc.v:42106$1509_Y - attribute \src "libresoc.v:42108.20-42108.110" - wire $and$libresoc.v:42108$1511_Y - attribute \src "libresoc.v:42109.20-42109.123" - wire $and$libresoc.v:42109$1512_Y - attribute \src "libresoc.v:42111.20-42111.122" - wire $and$libresoc.v:42111$1514_Y - attribute \src "libresoc.v:42112.20-42112.126" - wire $and$libresoc.v:42112$1515_Y - attribute \src "libresoc.v:42114.20-42114.110" - wire $and$libresoc.v:42114$1517_Y - attribute \src "libresoc.v:42115.20-42115.123" - wire $and$libresoc.v:42115$1518_Y - attribute \src "libresoc.v:42117.20-42117.123" - wire $and$libresoc.v:42117$1520_Y - attribute \src "libresoc.v:42118.20-42118.126" - wire $and$libresoc.v:42118$1521_Y - attribute \src "libresoc.v:42120.20-42120.110" - wire $and$libresoc.v:42120$1523_Y - attribute \src "libresoc.v:42121.20-42121.123" - wire $and$libresoc.v:42121$1524_Y - attribute \src "libresoc.v:42123.20-42123.123" - wire $and$libresoc.v:42123$1526_Y - attribute \src "libresoc.v:42124.20-42124.126" - wire $and$libresoc.v:42124$1527_Y - attribute \src "libresoc.v:42126.20-42126.110" - wire $and$libresoc.v:42126$1529_Y - attribute \src "libresoc.v:42127.20-42127.123" - wire $and$libresoc.v:42127$1530_Y - attribute \src "libresoc.v:42129.20-42129.123" - wire $and$libresoc.v:42129$1532_Y - attribute \src "libresoc.v:42130.20-42130.126" - wire $and$libresoc.v:42130$1533_Y - attribute \src "libresoc.v:42132.20-42132.110" - wire $and$libresoc.v:42132$1535_Y - attribute \src "libresoc.v:42133.20-42133.123" - wire $and$libresoc.v:42133$1536_Y - attribute \src "libresoc.v:42135.20-42135.123" - wire $and$libresoc.v:42135$1538_Y - attribute \src "libresoc.v:42136.20-42136.126" - wire $and$libresoc.v:42136$1539_Y - attribute \src "libresoc.v:42138.20-42138.110" - wire $and$libresoc.v:42138$1541_Y - attribute \src "libresoc.v:42139.20-42139.123" - wire $and$libresoc.v:42139$1542_Y - attribute \src "libresoc.v:42141.20-42141.113" - wire $and$libresoc.v:42141$1544_Y - attribute \src "libresoc.v:42142.20-42142.126" - wire $and$libresoc.v:42142$1545_Y - attribute \src "libresoc.v:42144.20-42144.110" - wire $and$libresoc.v:42144$1547_Y - attribute \src "libresoc.v:42145.20-42145.123" - wire $and$libresoc.v:42145$1548_Y - attribute \src "libresoc.v:42147.20-42147.114" - wire $and$libresoc.v:42147$1550_Y - attribute \src "libresoc.v:42148.20-42148.126" - wire $and$libresoc.v:42148$1551_Y - attribute \src "libresoc.v:42150.20-42150.110" - wire $and$libresoc.v:42150$1553_Y - attribute \src "libresoc.v:42151.20-42151.123" - wire $and$libresoc.v:42151$1554_Y - attribute \src "libresoc.v:42180.20-42180.123" - wire $and$libresoc.v:42180$1583_Y - attribute \src "libresoc.v:42181.20-42181.128" - wire $and$libresoc.v:42181$1584_Y - attribute \src "libresoc.v:42182.20-42182.133" - wire $and$libresoc.v:42182$1585_Y - attribute \src "libresoc.v:42184.20-42184.110" - wire $and$libresoc.v:42184$1587_Y - attribute \src "libresoc.v:42185.20-42185.128" - wire $and$libresoc.v:42185$1588_Y - attribute \src "libresoc.v:42187.20-42187.116" - wire $and$libresoc.v:42187$1590_Y - attribute \src "libresoc.v:42188.20-42188.123" - wire $and$libresoc.v:42188$1591_Y - attribute \src "libresoc.v:42189.20-42189.128" - wire $and$libresoc.v:42189$1592_Y - attribute \src "libresoc.v:42190.20-42190.128" - wire $and$libresoc.v:42190$1593_Y - attribute \src "libresoc.v:42191.20-42191.129" - wire $and$libresoc.v:42191$1594_Y - attribute \src "libresoc.v:42192.20-42192.129" - wire $and$libresoc.v:42192$1595_Y - attribute \src "libresoc.v:42193.20-42193.129" - wire $and$libresoc.v:42193$1596_Y - attribute \src "libresoc.v:42194.20-42194.130" - wire $and$libresoc.v:42194$1597_Y - attribute \src "libresoc.v:42196.20-42196.110" - wire $and$libresoc.v:42196$1599_Y - attribute \src "libresoc.v:42197.20-42197.125" - wire $and$libresoc.v:42197$1600_Y - attribute \src "libresoc.v:42201.20-42201.126" - wire $and$libresoc.v:42201$1604_Y - attribute \src "libresoc.v:42202.20-42202.130" - wire $and$libresoc.v:42202$1605_Y - attribute \src "libresoc.v:42204.20-42204.110" - wire $and$libresoc.v:42204$1607_Y - attribute \src "libresoc.v:42205.20-42205.125" - wire $and$libresoc.v:42205$1608_Y - attribute \src "libresoc.v:42209.20-42209.126" - wire $and$libresoc.v:42209$1612_Y - attribute \src "libresoc.v:42210.20-42210.130" - wire $and$libresoc.v:42210$1613_Y - attribute \src "libresoc.v:42212.20-42212.110" - wire $and$libresoc.v:42212$1615_Y - attribute \src "libresoc.v:42213.20-42213.125" - wire $and$libresoc.v:42213$1616_Y - attribute \src "libresoc.v:42217.20-42217.126" - wire $and$libresoc.v:42217$1620_Y - attribute \src "libresoc.v:42218.20-42218.130" - wire $and$libresoc.v:42218$1621_Y - attribute \src "libresoc.v:42220.20-42220.110" - wire $and$libresoc.v:42220$1623_Y - attribute \src "libresoc.v:42221.20-42221.125" - wire $and$libresoc.v:42221$1624_Y - attribute \src "libresoc.v:42225.20-42225.126" - wire $and$libresoc.v:42225$1628_Y - attribute \src "libresoc.v:42226.20-42226.130" - wire $and$libresoc.v:42226$1629_Y - attribute \src "libresoc.v:42228.20-42228.110" - wire $and$libresoc.v:42228$1631_Y - attribute \src "libresoc.v:42229.20-42229.125" - wire $and$libresoc.v:42229$1632_Y - attribute \src "libresoc.v:42233.20-42233.126" - wire $and$libresoc.v:42233$1636_Y - attribute \src "libresoc.v:42234.20-42234.130" - wire $and$libresoc.v:42234$1637_Y - attribute \src "libresoc.v:42236.20-42236.110" - wire $and$libresoc.v:42236$1639_Y - attribute \src "libresoc.v:42237.20-42237.125" - wire $and$libresoc.v:42237$1640_Y - attribute \src "libresoc.v:42251.20-42251.118" - wire $and$libresoc.v:42251$1654_Y - attribute \src "libresoc.v:42252.20-42252.123" - wire $and$libresoc.v:42252$1655_Y - attribute \src "libresoc.v:42253.20-42253.129" - wire $and$libresoc.v:42253$1656_Y - attribute \src "libresoc.v:42254.20-42254.129" - wire $and$libresoc.v:42254$1657_Y - attribute \src "libresoc.v:42255.20-42255.136" - wire $and$libresoc.v:42255$1658_Y - attribute \src "libresoc.v:42257.20-42257.110" - wire $and$libresoc.v:42257$1660_Y - attribute \src "libresoc.v:42258.20-42258.128" - wire $and$libresoc.v:42258$1661_Y - attribute \src "libresoc.v:42260.20-42260.128" - wire $and$libresoc.v:42260$1663_Y - attribute \src "libresoc.v:42261.20-42261.136" - wire $and$libresoc.v:42261$1664_Y - attribute \src "libresoc.v:42263.20-42263.110" - wire $and$libresoc.v:42263$1666_Y - attribute \src "libresoc.v:42264.20-42264.128" - wire $and$libresoc.v:42264$1667_Y - attribute \src "libresoc.v:42266.20-42266.128" - wire $and$libresoc.v:42266$1669_Y - attribute \src "libresoc.v:42267.20-42267.136" - wire $and$libresoc.v:42267$1670_Y - attribute \src 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$and$libresoc.v:42537$1897_Y + attribute \src "libresoc.v:42540.19-42540.131" + wire $and$libresoc.v:42540$1900_Y + attribute \src "libresoc.v:42541.19-42541.119" + wire width 3 $and$libresoc.v:42541$1901_Y + attribute \src "libresoc.v:42544.19-42544.131" + wire $and$libresoc.v:42544$1904_Y + attribute \src "libresoc.v:42547.19-42547.131" + wire $and$libresoc.v:42547$1907_Y + attribute \src "libresoc.v:42548.19-42548.119" + wire width 3 $and$libresoc.v:42548$1908_Y + attribute \src "libresoc.v:42551.19-42551.131" + wire $and$libresoc.v:42551$1911_Y + attribute \src "libresoc.v:42554.19-42554.119" + wire width 3 $and$libresoc.v:42554$1914_Y + attribute \src "libresoc.v:42559.19-42559.122" + wire $and$libresoc.v:42559$1919_Y attribute \src "libresoc.v:42560.19-42560.112" - wire $and$libresoc.v:42560$1968_Y + wire $and$libresoc.v:42560$1920_Y attribute \src "libresoc.v:42562.19-42562.102" - wire $and$libresoc.v:42562$1970_Y + wire $and$libresoc.v:42562$1922_Y attribute \src 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$and$libresoc.v:42589$1997_Y - attribute \src "libresoc.v:42590.19-42590.127" - wire $and$libresoc.v:42590$1998_Y - attribute \src "libresoc.v:42592.19-42592.127" - wire $and$libresoc.v:42592$2000_Y - attribute \src "libresoc.v:42593.19-42593.112" - wire $and$libresoc.v:42593$2001_Y - attribute \src "libresoc.v:42595.19-42595.102" - wire $and$libresoc.v:42595$2003_Y - attribute \src "libresoc.v:42596.19-42596.127" - wire $and$libresoc.v:42596$2004_Y - attribute \src "libresoc.v:42598.19-42598.127" - wire $and$libresoc.v:42598$2006_Y - attribute \src "libresoc.v:42599.19-42599.112" - wire $and$libresoc.v:42599$2007_Y - attribute \src "libresoc.v:42601.19-42601.102" - wire $and$libresoc.v:42601$2009_Y - attribute \src "libresoc.v:42602.19-42602.127" - wire $and$libresoc.v:42602$2010_Y - attribute \src "libresoc.v:42604.19-42604.127" - wire $and$libresoc.v:42604$2012_Y - attribute \src "libresoc.v:42605.19-42605.112" - wire $and$libresoc.v:42605$2013_Y - attribute \src "libresoc.v:42607.19-42607.102" - wire $and$libresoc.v:42607$2015_Y - attribute \src "libresoc.v:42608.19-42608.127" - wire $and$libresoc.v:42608$2016_Y - attribute \src "libresoc.v:42610.19-42610.127" - wire $and$libresoc.v:42610$2018_Y - attribute \src "libresoc.v:42611.19-42611.112" - wire $and$libresoc.v:42611$2019_Y - attribute \src "libresoc.v:42613.19-42613.102" - wire $and$libresoc.v:42613$2021_Y - attribute \src "libresoc.v:42614.19-42614.127" - wire $and$libresoc.v:42614$2022_Y - attribute \src "libresoc.v:42616.19-42616.127" - wire $and$libresoc.v:42616$2024_Y - attribute \src "libresoc.v:42617.19-42617.112" - wire $and$libresoc.v:42617$2025_Y - attribute \src "libresoc.v:42619.19-42619.102" - wire $and$libresoc.v:42619$2027_Y - attribute \src "libresoc.v:42620.19-42620.127" - wire $and$libresoc.v:42620$2028_Y - attribute \src "libresoc.v:42630.19-42630.127" - wire $and$libresoc.v:42630$2038_Y - attribute \src "libresoc.v:42631.19-42631.112" - wire $and$libresoc.v:42631$2039_Y - attribute \src "libresoc.v:42633.19-42633.102" - wire $and$libresoc.v:42633$2041_Y + wire $and$libresoc.v:42563$1923_Y + attribute \src "libresoc.v:42565.19-42565.127" + wire $and$libresoc.v:42565$1925_Y + attribute \src "libresoc.v:42566.19-42566.112" + wire $and$libresoc.v:42566$1926_Y + attribute \src "libresoc.v:42568.19-42568.102" + wire $and$libresoc.v:42568$1928_Y + attribute \src "libresoc.v:42569.19-42569.127" + wire $and$libresoc.v:42569$1929_Y + attribute \src "libresoc.v:42571.19-42571.127" + wire $and$libresoc.v:42571$1931_Y + attribute \src "libresoc.v:42572.19-42572.112" + wire $and$libresoc.v:42572$1932_Y + attribute \src "libresoc.v:42574.19-42574.102" + wire $and$libresoc.v:42574$1934_Y + attribute \src "libresoc.v:42575.19-42575.127" + wire $and$libresoc.v:42575$1935_Y + attribute \src "libresoc.v:42577.19-42577.127" + wire $and$libresoc.v:42577$1937_Y + attribute \src "libresoc.v:42578.19-42578.112" + wire $and$libresoc.v:42578$1938_Y + attribute \src "libresoc.v:42580.19-42580.102" + wire $and$libresoc.v:42580$1940_Y + attribute \src "libresoc.v:42581.19-42581.127" + wire $and$libresoc.v:42581$1941_Y + attribute \src "libresoc.v:42583.19-42583.127" + wire $and$libresoc.v:42583$1943_Y + attribute \src "libresoc.v:42584.19-42584.112" + wire $and$libresoc.v:42584$1944_Y + attribute \src "libresoc.v:42586.19-42586.102" + wire $and$libresoc.v:42586$1946_Y + attribute \src "libresoc.v:42587.19-42587.127" + wire $and$libresoc.v:42587$1947_Y + attribute \src "libresoc.v:42589.19-42589.127" + wire $and$libresoc.v:42589$1949_Y + attribute \src "libresoc.v:42590.19-42590.112" + wire $and$libresoc.v:42590$1950_Y + attribute \src "libresoc.v:42592.19-42592.102" + wire $and$libresoc.v:42592$1952_Y + attribute \src "libresoc.v:42593.19-42593.127" + wire $and$libresoc.v:42593$1953_Y + attribute \src "libresoc.v:42595.19-42595.127" + wire $and$libresoc.v:42595$1955_Y + attribute \src "libresoc.v:42596.19-42596.112" + wire $and$libresoc.v:42596$1956_Y + attribute \src "libresoc.v:42598.19-42598.102" + wire $and$libresoc.v:42598$1958_Y + attribute \src "libresoc.v:42599.19-42599.127" + wire $and$libresoc.v:42599$1959_Y + attribute \src "libresoc.v:42601.19-42601.127" + wire $and$libresoc.v:42601$1961_Y + attribute \src "libresoc.v:42602.19-42602.112" + wire $and$libresoc.v:42602$1962_Y + attribute \src "libresoc.v:42604.19-42604.102" + wire $and$libresoc.v:42604$1964_Y + attribute \src "libresoc.v:42605.19-42605.127" + wire $and$libresoc.v:42605$1965_Y + attribute \src "libresoc.v:42607.19-42607.127" + wire $and$libresoc.v:42607$1967_Y + attribute \src "libresoc.v:42608.19-42608.112" + wire $and$libresoc.v:42608$1968_Y + attribute \src "libresoc.v:42610.19-42610.102" + wire $and$libresoc.v:42610$1970_Y + attribute \src "libresoc.v:42611.19-42611.127" + wire $and$libresoc.v:42611$1971_Y + attribute \src "libresoc.v:42622.19-42622.122" + wire $and$libresoc.v:42622$1982_Y + attribute \src "libresoc.v:42623.19-42623.112" + wire $and$libresoc.v:42623$1983_Y + attribute \src "libresoc.v:42625.19-42625.102" + wire $and$libresoc.v:42625$1985_Y + attribute \src "libresoc.v:42626.19-42626.127" + wire $and$libresoc.v:42626$1986_Y + attribute \src "libresoc.v:42628.19-42628.127" + wire $and$libresoc.v:42628$1988_Y + attribute \src "libresoc.v:42629.19-42629.112" + wire $and$libresoc.v:42629$1989_Y + attribute \src "libresoc.v:42631.19-42631.102" + wire $and$libresoc.v:42631$1991_Y + attribute \src "libresoc.v:42632.19-42632.127" + wire $and$libresoc.v:42632$1992_Y attribute \src "libresoc.v:42634.19-42634.127" - wire $and$libresoc.v:42634$2042_Y - attribute \src "libresoc.v:42636.19-42636.127" - wire $and$libresoc.v:42636$2044_Y - attribute \src "libresoc.v:42637.19-42637.112" - wire $and$libresoc.v:42637$2045_Y - attribute \src "libresoc.v:42639.19-42639.102" - wire $and$libresoc.v:42639$2047_Y + wire $and$libresoc.v:42634$1994_Y + attribute \src "libresoc.v:42635.19-42635.112" + wire $and$libresoc.v:42635$1995_Y + attribute \src "libresoc.v:42637.19-42637.102" + wire $and$libresoc.v:42637$1997_Y + attribute \src "libresoc.v:42638.19-42638.127" + wire $and$libresoc.v:42638$1998_Y attribute \src "libresoc.v:42640.19-42640.127" - wire $and$libresoc.v:42640$2048_Y - attribute \src "libresoc.v:42644.19-42644.131" - wire $and$libresoc.v:42644$2052_Y - attribute \src "libresoc.v:42645.19-42645.119" - wire width 3 $and$libresoc.v:42645$2053_Y - attribute \src "libresoc.v:42648.19-42648.131" - wire $and$libresoc.v:42648$2056_Y - attribute \src "libresoc.v:42650.19-42650.122" - wire $and$libresoc.v:42650$2058_Y - attribute \src "libresoc.v:42651.19-42651.116" - wire $and$libresoc.v:42651$2059_Y - attribute \src "libresoc.v:42653.19-42653.102" - wire $and$libresoc.v:42653$2061_Y - attribute \src "libresoc.v:42654.19-42654.135" - wire $and$libresoc.v:42654$2062_Y + wire $and$libresoc.v:42640$2000_Y + attribute \src "libresoc.v:42641.19-42641.112" + wire $and$libresoc.v:42641$2001_Y + attribute \src "libresoc.v:42643.19-42643.102" + wire $and$libresoc.v:42643$2003_Y + attribute \src "libresoc.v:42644.19-42644.127" + wire $and$libresoc.v:42644$2004_Y + attribute \src "libresoc.v:42646.19-42646.127" + wire $and$libresoc.v:42646$2006_Y + attribute \src "libresoc.v:42647.19-42647.112" + wire $and$libresoc.v:42647$2007_Y + attribute \src "libresoc.v:42649.19-42649.102" + wire $and$libresoc.v:42649$2009_Y + attribute \src "libresoc.v:42650.19-42650.127" + wire $and$libresoc.v:42650$2010_Y + attribute \src "libresoc.v:42652.19-42652.127" + wire $and$libresoc.v:42652$2012_Y + attribute \src "libresoc.v:42653.19-42653.112" + wire $and$libresoc.v:42653$2013_Y + attribute \src "libresoc.v:42655.19-42655.102" + wire $and$libresoc.v:42655$2015_Y attribute \src "libresoc.v:42656.19-42656.127" - wire $and$libresoc.v:42656$2064_Y - attribute \src "libresoc.v:42657.19-42657.116" - wire $and$libresoc.v:42657$2065_Y - attribute \src "libresoc.v:42659.19-42659.102" - wire $and$libresoc.v:42659$2067_Y - attribute \src "libresoc.v:42660.19-42660.135" - wire $and$libresoc.v:42660$2068_Y + wire $and$libresoc.v:42656$2016_Y + attribute \src "libresoc.v:42658.19-42658.127" + wire $and$libresoc.v:42658$2018_Y + attribute \src "libresoc.v:42659.19-42659.112" + wire $and$libresoc.v:42659$2019_Y + attribute \src "libresoc.v:42661.19-42661.102" + wire $and$libresoc.v:42661$2021_Y attribute \src "libresoc.v:42662.19-42662.127" - wire $and$libresoc.v:42662$2070_Y - attribute \src "libresoc.v:42663.19-42663.116" - wire $and$libresoc.v:42663$2071_Y - attribute \src "libresoc.v:42665.19-42665.102" - wire $and$libresoc.v:42665$2073_Y - attribute \src "libresoc.v:42666.19-42666.135" - wire $and$libresoc.v:42666$2074_Y + wire $and$libresoc.v:42662$2022_Y + attribute \src "libresoc.v:42664.19-42664.127" + wire $and$libresoc.v:42664$2024_Y + attribute \src "libresoc.v:42665.19-42665.112" + wire $and$libresoc.v:42665$2025_Y + attribute \src "libresoc.v:42667.19-42667.102" + wire $and$libresoc.v:42667$2027_Y attribute \src "libresoc.v:42668.19-42668.127" - wire $and$libresoc.v:42668$2076_Y - attribute \src "libresoc.v:42669.19-42669.116" - wire $and$libresoc.v:42669$2077_Y - attribute \src "libresoc.v:42671.19-42671.102" - wire $and$libresoc.v:42671$2079_Y - attribute \src "libresoc.v:42672.19-42672.135" - wire $and$libresoc.v:42672$2080_Y - attribute \src "libresoc.v:42674.19-42674.127" - wire $and$libresoc.v:42674$2082_Y - attribute \src "libresoc.v:42675.19-42675.116" - wire $and$libresoc.v:42675$2083_Y - attribute \src "libresoc.v:42677.19-42677.102" - wire $and$libresoc.v:42677$2085_Y - attribute \src "libresoc.v:42678.19-42678.135" - wire $and$libresoc.v:42678$2086_Y - attribute \src "libresoc.v:42680.19-42680.127" - wire $and$libresoc.v:42680$2088_Y - attribute \src "libresoc.v:42681.19-42681.116" - wire $and$libresoc.v:42681$2089_Y - attribute \src "libresoc.v:42683.19-42683.102" - wire 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$sub$libresoc.v:42270$1625_Y + attribute \src "libresoc.v:42278.20-42278.121" + wire width 8 $sub$libresoc.v:42278$1633_Y + attribute \src "libresoc.v:42286.20-42286.121" + wire width 8 $sub$libresoc.v:42286$1641_Y + attribute \src "libresoc.v:42495.19-42495.102" + wire width 3 $sub$libresoc.v:42495$1855_Y + attribute \src "libresoc.v:42786.19-42786.119" + wire width 8 $sub$libresoc.v:42786$2148_Y + attribute \src "libresoc.v:42794.19-42794.119" + wire width 8 $sub$libresoc.v:42794$2156_Y + attribute \src "libresoc.v:42803.19-42803.119" + wire width 8 $sub$libresoc.v:42803$2165_Y + attribute \src "libresoc.v:42811.19-42811.122" + wire width 8 $sub$libresoc.v:42811$2173_Y + attribute \src "libresoc.v:42152.20-42152.117" + wire width 7 $ternary$libresoc.v:42152$1507_Y + attribute \src "libresoc.v:42158.20-42158.118" + wire width 7 $ternary$libresoc.v:42158$1513_Y + attribute \src "libresoc.v:42164.20-42164.118" + wire width 7 $ternary$libresoc.v:42164$1519_Y + attribute \src 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"libresoc.v:42272.20-42272.180" + wire width 256 $ternary$libresoc.v:42272$1627_Y + attribute \src "libresoc.v:42280.20-42280.180" + wire width 256 $ternary$libresoc.v:42280$1635_Y + attribute \src "libresoc.v:42288.20-42288.180" + wire width 256 $ternary$libresoc.v:42288$1643_Y + attribute \src "libresoc.v:42307.20-42307.112" + wire width 2 $ternary$libresoc.v:42307$1662_Y + attribute \src "libresoc.v:42313.20-42313.112" + wire width 2 $ternary$libresoc.v:42313$1668_Y + attribute \src "libresoc.v:42319.20-42319.112" + wire width 2 $ternary$libresoc.v:42319$1674_Y + attribute \src "libresoc.v:42334.20-42334.112" + wire width 3 $ternary$libresoc.v:42334$1690_Y + attribute \src "libresoc.v:42340.20-42340.112" + wire width 3 $ternary$libresoc.v:42340$1696_Y + attribute \src "libresoc.v:42346.20-42346.112" + wire width 3 $ternary$libresoc.v:42346$1702_Y + attribute \src "libresoc.v:42352.20-42352.112" + wire width 3 $ternary$libresoc.v:42352$1708_Y + attribute \src "libresoc.v:42368.20-42368.112" + wire $ternary$libresoc.v:42368$1724_Y + attribute \src "libresoc.v:42374.20-42374.112" + wire $ternary$libresoc.v:42374$1730_Y + attribute \src "libresoc.v:42380.20-42380.112" + wire $ternary$libresoc.v:42380$1736_Y + attribute \src "libresoc.v:42386.20-42386.112" + wire $ternary$libresoc.v:42386$1742_Y + attribute \src "libresoc.v:42405.20-42405.119" + wire width 3 $ternary$libresoc.v:42405$1763_Y + attribute \src "libresoc.v:42411.20-42411.119" + wire width 3 $ternary$libresoc.v:42411$1769_Y + attribute \src "libresoc.v:42417.20-42417.119" + wire width 3 $ternary$libresoc.v:42417$1775_Y + attribute \src "libresoc.v:42423.20-42423.119" + wire width 3 $ternary$libresoc.v:42423$1781_Y + attribute \src "libresoc.v:42429.20-42429.119" + wire width 3 $ternary$libresoc.v:42429$1787_Y + attribute \src "libresoc.v:42449.20-42449.112" + wire $ternary$libresoc.v:42449$1807_Y + attribute \src "libresoc.v:42455.20-42455.112" + wire $ternary$libresoc.v:42455$1813_Y + attribute \src "libresoc.v:42465.20-42465.112" + wire width 2 $ternary$libresoc.v:42465$1824_Y + attribute \src "libresoc.v:42473.20-42473.120" + wire width 10 $ternary$libresoc.v:42473$1833_Y + attribute \src "libresoc.v:42564.19-42564.124" + wire width 7 $ternary$libresoc.v:42564$1924_Y + attribute \src "libresoc.v:42570.19-42570.123" + wire width 7 $ternary$libresoc.v:42570$1930_Y + attribute \src "libresoc.v:42576.19-42576.125" + wire width 7 $ternary$libresoc.v:42576$1936_Y + attribute \src "libresoc.v:42582.19-42582.128" + wire width 7 $ternary$libresoc.v:42582$1942_Y + attribute \src "libresoc.v:42588.19-42588.124" + wire width 7 $ternary$libresoc.v:42588$1948_Y + attribute \src "libresoc.v:42594.19-42594.124" + wire width 7 $ternary$libresoc.v:42594$1954_Y + attribute \src "libresoc.v:42600.19-42600.124" + wire width 7 $ternary$libresoc.v:42600$1960_Y + attribute \src "libresoc.v:42606.19-42606.129" + wire width 7 $ternary$libresoc.v:42606$1966_Y + attribute \src "libresoc.v:42612.19-42612.125" + wire width 7 $ternary$libresoc.v:42612$1972_Y + attribute \src "libresoc.v:42627.19-42627.124" + wire width 7 $ternary$libresoc.v:42627$1987_Y + attribute \src "libresoc.v:42633.19-42633.123" + wire width 7 $ternary$libresoc.v:42633$1993_Y + attribute \src "libresoc.v:42639.19-42639.125" + wire width 7 $ternary$libresoc.v:42639$1999_Y + attribute \src "libresoc.v:42645.19-42645.128" + wire width 7 $ternary$libresoc.v:42645$2005_Y + attribute \src "libresoc.v:42651.19-42651.124" + wire width 7 $ternary$libresoc.v:42651$2011_Y + attribute \src "libresoc.v:42657.19-42657.124" + wire width 7 $ternary$libresoc.v:42657$2017_Y + attribute \src "libresoc.v:42663.19-42663.129" + wire width 7 $ternary$libresoc.v:42663$2023_Y + attribute \src "libresoc.v:42669.19-42669.125" + wire width 7 $ternary$libresoc.v:42669$2029_Y + attribute \src "libresoc.v:42683.19-42683.129" + wire width 7 $ternary$libresoc.v:42683$2043_Y + attribute \src "libresoc.v:42689.19-42689.125" + wire width 7 $ternary$libresoc.v:42689$2049_Y + attribute \src "libresoc.v:42703.19-42703.122" + wire $ternary$libresoc.v:42703$2063_Y + attribute \src "libresoc.v:42709.19-42709.126" + wire $ternary$libresoc.v:42709$2069_Y + attribute \src "libresoc.v:42715.19-42715.122" + wire $ternary$libresoc.v:42715$2075_Y + attribute \src "libresoc.v:42721.19-42721.122" + wire $ternary$libresoc.v:42721$2081_Y + attribute \src "libresoc.v:42727.19-42727.122" + wire $ternary$libresoc.v:42727$2087_Y + attribute \src "libresoc.v:42733.19-42733.127" + wire $ternary$libresoc.v:42733$2093_Y + attribute \src "libresoc.v:42749.19-42749.122" + wire width 2 $ternary$libresoc.v:42749$2110_Y + attribute \src "libresoc.v:42755.19-42755.122" + wire width 2 $ternary$libresoc.v:42755$2116_Y + attribute \src "libresoc.v:42761.19-42761.127" + wire width 2 $ternary$libresoc.v:42761$2122_Y + attribute \src "libresoc.v:42774.19-42774.122" + wire width 3 $ternary$libresoc.v:42774$2136_Y + attribute \src "libresoc.v:42780.19-42780.133" + wire width 8 $ternary$libresoc.v:42780$2142_Y + attribute \src "libresoc.v:42788.19-42788.185" + wire width 256 $ternary$libresoc.v:42788$2150_Y + attribute \src "libresoc.v:42796.19-42796.189" + wire width 256 $ternary$libresoc.v:42796$2158_Y + attribute \src "libresoc.v:42805.19-42805.185" + wire width 256 $ternary$libresoc.v:42805$2167_Y + attribute \src "libresoc.v:42813.19-42813.185" + wire width 256 $ternary$libresoc.v:42813$2175_Y + attribute \src "libresoc.v:42819.19-42819.131" + wire width 3 $ternary$libresoc.v:42819$2181_Y + attribute \src "libresoc.v:42825.19-42825.129" + wire width 3 $ternary$libresoc.v:42825$2187_Y + attribute \src "libresoc.v:42831.19-42831.128" + wire width 3 $ternary$libresoc.v:42831$2193_Y + attribute \src "libresoc.v:42840.19-42840.131" + wire width 3 $ternary$libresoc.v:42840$2202_Y + attribute \src "libresoc.v:42846.19-42846.129" + wire width 3 $ternary$libresoc.v:42846$2208_Y + attribute \src "libresoc.v:42854.19-42854.128" + wire width 10 $ternary$libresoc.v:42854$2216_Y + attribute \src "libresoc.v:42871.19-42871.110" + wire width 7 $ternary$libresoc.v:42871$2233_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" wire \$1000 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" @@ -62431,9 +62467,9 @@ module \core wire width 3 input 27 \core_xer_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:99" wire output 2 \corebusy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 97 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:188" wire width 2 \counter @@ -65381,7 +65417,7 @@ module \core wire \fus_xer_so_ok$142 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fus_xer_so_ok$143 - attribute \src "libresoc.v:36214.7-36214.15" + attribute \src "libresoc.v:36262.7-36262.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 5 \int_dest1__addr @@ -66266,7 +66302,7 @@ module \core attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \xer_wen$173 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42103$1506 + cell $and $and$libresoc.v:42151$1506 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66274,10 +66310,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$988 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42103$1506_Y + connect \Y $and$libresoc.v:42151$1506_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42105$1508 + cell $and $and$libresoc.v:42153$1508 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66285,10 +66321,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok$95 connect \B \fus_cu_busy_o$20 - connect \Y $and$libresoc.v:42105$1508_Y + connect \Y $and$libresoc.v:42153$1508_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42106$1509 + cell $and $and$libresoc.v:42154$1509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66296,10 +66332,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [2] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42106$1509_Y + connect \Y $and$libresoc.v:42154$1509_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42108$1511 + cell $and $and$libresoc.v:42156$1511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66307,10 +66343,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1007 connect \B \$1012 - connect \Y $and$libresoc.v:42108$1511_Y + connect \Y $and$libresoc.v:42156$1511_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42109$1512 + cell $and $and$libresoc.v:42157$1512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66318,10 +66354,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1007 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42109$1512_Y + connect \Y $and$libresoc.v:42157$1512_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42111$1514 + cell $and $and$libresoc.v:42159$1514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66329,10 +66365,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok$98 connect \B \fus_cu_busy_o$23 - connect \Y $and$libresoc.v:42111$1514_Y + connect \Y $and$libresoc.v:42159$1514_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42112$1515 + cell $and $and$libresoc.v:42160$1515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66340,10 +66376,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [3] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42112$1515_Y + connect \Y $and$libresoc.v:42160$1515_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42114$1517 + cell $and $and$libresoc.v:42162$1517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66351,10 +66387,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1028 connect \B \$1033 - connect \Y $and$libresoc.v:42114$1517_Y + connect \Y $and$libresoc.v:42162$1517_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42115$1518 + cell $and $and$libresoc.v:42163$1518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66362,10 +66398,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1028 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42115$1518_Y + connect \Y $and$libresoc.v:42163$1518_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42117$1520 + cell $and $and$libresoc.v:42165$1520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66373,10 +66409,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok$101 connect \B \fus_cu_busy_o$26 - connect \Y $and$libresoc.v:42117$1520_Y + connect \Y $and$libresoc.v:42165$1520_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42118$1521 + cell $and $and$libresoc.v:42166$1521 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66384,10 +66420,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [4] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42118$1521_Y + connect \Y $and$libresoc.v:42166$1521_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42120$1523 + cell $and $and$libresoc.v:42168$1523 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66395,10 +66431,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1046 connect \B \$1051 - connect \Y $and$libresoc.v:42120$1523_Y + connect \Y $and$libresoc.v:42168$1523_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42121$1524 + cell $and $and$libresoc.v:42169$1524 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66406,10 +66442,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1046 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42121$1524_Y + connect \Y $and$libresoc.v:42169$1524_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42123$1526 + cell $and $and$libresoc.v:42171$1526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66417,10 +66453,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok$104 connect \B \fus_cu_busy_o$29 - connect \Y $and$libresoc.v:42123$1526_Y + connect \Y $and$libresoc.v:42171$1526_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42124$1527 + cell $and $and$libresoc.v:42172$1527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66428,10 +66464,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [5] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42124$1527_Y + connect \Y $and$libresoc.v:42172$1527_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42126$1529 + cell $and $and$libresoc.v:42174$1529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66439,10 +66475,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1068 connect \B \$1073 - connect \Y $and$libresoc.v:42126$1529_Y + connect \Y $and$libresoc.v:42174$1529_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42127$1530 + cell $and $and$libresoc.v:42175$1530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66450,10 +66486,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1068 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42127$1530_Y + connect \Y $and$libresoc.v:42175$1530_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42129$1532 + cell $and $and$libresoc.v:42177$1532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66461,10 +66497,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok$107 connect \B \fus_cu_busy_o$32 - connect \Y $and$libresoc.v:42129$1532_Y + connect \Y $and$libresoc.v:42177$1532_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42130$1533 + cell $and $and$libresoc.v:42178$1533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66472,10 +66508,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [6] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42130$1533_Y + connect \Y $and$libresoc.v:42178$1533_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42132$1535 + cell $and $and$libresoc.v:42180$1535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66483,10 +66519,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1088 connect \B \$1093 - connect \Y $and$libresoc.v:42132$1535_Y + connect \Y $and$libresoc.v:42180$1535_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42133$1536 + cell $and $and$libresoc.v:42181$1536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66494,10 +66530,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1088 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42133$1536_Y + connect \Y $and$libresoc.v:42181$1536_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42135$1538 + cell $and $and$libresoc.v:42183$1538 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66505,10 +66541,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok$110 connect \B \fus_cu_busy_o$35 - connect \Y $and$libresoc.v:42135$1538_Y + connect \Y $and$libresoc.v:42183$1538_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42136$1539 + cell $and $and$libresoc.v:42184$1539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66516,10 +66552,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [7] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42136$1539_Y + connect \Y $and$libresoc.v:42184$1539_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42138$1541 + cell $and $and$libresoc.v:42186$1541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66527,10 +66563,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1108 connect \B \$1113 - connect \Y $and$libresoc.v:42138$1541_Y + connect \Y $and$libresoc.v:42186$1541_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42139$1542 + cell $and $and$libresoc.v:42187$1542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66538,10 +66574,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1108 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42139$1542_Y + connect \Y $and$libresoc.v:42187$1542_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42141$1544 + cell $and $and$libresoc.v:42189$1544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66549,10 +66585,10 @@ module \core parameter \Y_WIDTH 1 connect \A \o_ok connect \B \fus_cu_busy_o$38 - connect \Y $and$libresoc.v:42141$1544_Y + connect \Y $and$libresoc.v:42189$1544_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42142$1545 + cell $and $and$libresoc.v:42190$1545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66560,10 +66596,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [8] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42142$1545_Y + connect \Y $and$libresoc.v:42190$1545_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42144$1547 + cell $and $and$libresoc.v:42192$1547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66571,10 +66607,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1127 connect \B \$1132 - connect \Y $and$libresoc.v:42144$1547_Y + connect \Y $and$libresoc.v:42192$1547_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42145$1548 + cell $and $and$libresoc.v:42193$1548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66582,10 +66618,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1127 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42145$1548_Y + connect \Y $and$libresoc.v:42193$1548_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42147$1550 + cell $and $and$libresoc.v:42195$1550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66593,10 +66629,10 @@ module \core parameter \Y_WIDTH 1 connect \A \ea_ok connect \B \fus_cu_busy_o$38 - connect \Y $and$libresoc.v:42147$1550_Y + connect \Y $and$libresoc.v:42195$1550_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42148$1551 + cell $and $and$libresoc.v:42196$1551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66604,10 +66640,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [9] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42148$1551_Y + connect \Y $and$libresoc.v:42196$1551_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42150$1553 + cell $and $and$libresoc.v:42198$1553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66615,10 +66651,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1145 connect \B \$1149 - connect \Y $and$libresoc.v:42150$1553_Y + connect \Y $and$libresoc.v:42198$1553_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42151$1554 + cell $and $and$libresoc.v:42199$1554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66626,10 +66662,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1145 connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42151$1554_Y + connect \Y $and$libresoc.v:42199$1554_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42180$1583 + cell $and $and$libresoc.v:42228$1583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66637,10 +66673,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_full_cr_ok connect \B \fus_cu_busy_o$14 - connect \Y $and$libresoc.v:42180$1583_Y + connect \Y $and$libresoc.v:42228$1583_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42181$1584 + cell $and $and$libresoc.v:42229$1584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66648,10 +66684,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$93 [1] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42181$1584_Y + connect \Y $and$libresoc.v:42229$1584_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42182$1585 + cell $and $and$libresoc.v:42230$1585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66659,10 +66695,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_full_cr_o connect \B \wrpick_CR_full_cr_en_o - connect \Y $and$libresoc.v:42182$1585_Y + connect \Y $and$libresoc.v:42230$1585_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42184$1587 + cell $and $and$libresoc.v:42232$1587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66670,10 +66706,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1219 connect \B \$1223 - connect \Y $and$libresoc.v:42184$1587_Y + connect \Y $and$libresoc.v:42232$1587_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42185$1588 + cell $and $and$libresoc.v:42233$1588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66681,10 +66717,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1219 connect \B \wrpick_CR_full_cr_en_o - connect \Y $and$libresoc.v:42185$1588_Y + connect \Y $and$libresoc.v:42233$1588_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42187$1590 + cell $and $and$libresoc.v:42235$1590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66692,10 +66728,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok connect \B \fus_cu_busy_o - connect \Y $and$libresoc.v:42187$1590_Y + connect \Y $and$libresoc.v:42235$1590_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42188$1591 + cell $and $and$libresoc.v:42236$1591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66703,10 +66739,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [1] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42188$1591_Y + connect \Y $and$libresoc.v:42236$1591_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42189$1592 + cell $and $and$libresoc.v:42237$1592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66714,10 +66750,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$93 [2] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42189$1592_Y + connect \Y $and$libresoc.v:42237$1592_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42190$1593 + cell $and $and$libresoc.v:42238$1593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66725,10 +66761,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$99 [1] connect \B \fu_enable [4] - connect \Y $and$libresoc.v:42190$1593_Y + connect \Y $and$libresoc.v:42238$1593_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42191$1594 + cell $and $and$libresoc.v:42239$1594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66736,10 +66772,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$105 [1] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:42191$1594_Y + connect \Y $and$libresoc.v:42239$1594_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42192$1595 + cell $and $and$libresoc.v:42240$1595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66747,10 +66783,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$108 [1] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:42192$1595_Y + connect \Y $and$libresoc.v:42240$1595_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42193$1596 + cell $and $and$libresoc.v:42241$1596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66758,10 +66794,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$111 [1] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:42193$1596_Y + connect \Y $and$libresoc.v:42241$1596_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42194$1597 + cell $and $and$libresoc.v:42242$1597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66769,10 +66805,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [0] connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42194$1597_Y + connect \Y $and$libresoc.v:42242$1597_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42196$1599 + cell $and $and$libresoc.v:42244$1599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66780,10 +66816,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1247 connect \B \$1251 - connect \Y $and$libresoc.v:42196$1599_Y + connect \Y $and$libresoc.v:42244$1599_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42197$1600 + cell $and $and$libresoc.v:42245$1600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66791,10 +66827,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1247 connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42197$1600_Y + connect \Y $and$libresoc.v:42245$1600_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42201$1604 + cell $and $and$libresoc.v:42249$1604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66802,10 +66838,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok$122 connect \B \fus_cu_busy_o$14 - connect \Y $and$libresoc.v:42201$1604_Y + connect \Y $and$libresoc.v:42249$1604_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42202$1605 + cell $and $and$libresoc.v:42250$1605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66813,10 +66849,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [1] connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42202$1605_Y + connect \Y $and$libresoc.v:42250$1605_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42204$1607 + cell $and $and$libresoc.v:42252$1607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66824,10 +66860,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1267 connect \B \$1271 - connect \Y $and$libresoc.v:42204$1607_Y + connect \Y $and$libresoc.v:42252$1607_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42205$1608 + cell $and $and$libresoc.v:42253$1608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66835,10 +66871,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1267 connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42205$1608_Y + connect \Y $and$libresoc.v:42253$1608_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42209$1612 + cell $and $and$libresoc.v:42257$1612 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66846,10 +66882,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok$123 connect \B \fus_cu_busy_o$23 - connect \Y $and$libresoc.v:42209$1612_Y + connect \Y $and$libresoc.v:42257$1612_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42210$1613 + cell $and $and$libresoc.v:42258$1613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66857,10 +66893,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [2] connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42210$1613_Y + connect \Y $and$libresoc.v:42258$1613_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42212$1615 + cell $and $and$libresoc.v:42260$1615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66868,10 +66904,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1287 connect \B \$1291 - connect \Y $and$libresoc.v:42212$1615_Y + connect \Y $and$libresoc.v:42260$1615_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42213$1616 + cell $and $and$libresoc.v:42261$1616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66879,10 +66915,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1287 connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42213$1616_Y + connect \Y $and$libresoc.v:42261$1616_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42217$1620 + cell $and $and$libresoc.v:42265$1620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66890,10 +66926,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok$124 connect \B \fus_cu_busy_o$29 - connect \Y $and$libresoc.v:42217$1620_Y + connect \Y $and$libresoc.v:42265$1620_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42218$1621 + cell $and $and$libresoc.v:42266$1621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66901,10 +66937,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [3] connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42218$1621_Y + connect \Y $and$libresoc.v:42266$1621_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42220$1623 + cell $and $and$libresoc.v:42268$1623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66912,10 +66948,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1307 connect \B \$1311 - connect \Y $and$libresoc.v:42220$1623_Y + connect \Y $and$libresoc.v:42268$1623_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42221$1624 + cell $and $and$libresoc.v:42269$1624 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66923,10 +66959,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1307 connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42221$1624_Y + connect \Y $and$libresoc.v:42269$1624_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42225$1628 + cell $and $and$libresoc.v:42273$1628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66934,10 +66970,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok$125 connect \B \fus_cu_busy_o$32 - connect \Y $and$libresoc.v:42225$1628_Y + connect \Y $and$libresoc.v:42273$1628_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42226$1629 + cell $and $and$libresoc.v:42274$1629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66945,10 +66981,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [4] connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42226$1629_Y + connect \Y $and$libresoc.v:42274$1629_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42228$1631 + cell $and $and$libresoc.v:42276$1631 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66956,10 +66992,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1327 connect \B \$1331 - connect \Y $and$libresoc.v:42228$1631_Y + connect \Y $and$libresoc.v:42276$1631_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42229$1632 + cell $and $and$libresoc.v:42277$1632 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66967,10 +67003,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1327 connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42229$1632_Y + connect \Y $and$libresoc.v:42277$1632_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42233$1636 + cell $and $and$libresoc.v:42281$1636 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66978,10 +67014,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cr_a_ok$126 connect \B \fus_cu_busy_o$35 - connect \Y $and$libresoc.v:42233$1636_Y + connect \Y $and$libresoc.v:42281$1636_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42234$1637 + cell $and $and$libresoc.v:42282$1637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -66989,10 +67025,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_CR_cr_a_o [5] connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42234$1637_Y + connect \Y $and$libresoc.v:42282$1637_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42236$1639 + cell $and $and$libresoc.v:42284$1639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67000,10 +67036,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1347 connect \B \$1351 - connect \Y $and$libresoc.v:42236$1639_Y + connect \Y $and$libresoc.v:42284$1639_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42237$1640 + cell $and $and$libresoc.v:42285$1640 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67011,10 +67047,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1347 connect \B \wrpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42237$1640_Y + connect \Y $and$libresoc.v:42285$1640_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42251$1654 + cell $and $and$libresoc.v:42299$1654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67022,10 +67058,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ca_ok connect \B \fus_cu_busy_o - connect \Y $and$libresoc.v:42251$1654_Y + connect \Y $and$libresoc.v:42299$1654_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42252$1655 + cell $and $and$libresoc.v:42300$1655 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67033,10 +67069,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [2] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42252$1655_Y + connect \Y $and$libresoc.v:42300$1655_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42253$1656 + cell $and $and$libresoc.v:42301$1656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67044,10 +67080,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$102 [5] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42253$1656_Y + connect \Y $and$libresoc.v:42301$1656_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42254$1657 + cell $and $and$libresoc.v:42302$1657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67055,10 +67091,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$111 [2] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:42254$1657_Y + connect \Y $and$libresoc.v:42302$1657_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42255$1658 + cell $and $and$libresoc.v:42303$1658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67066,10 +67102,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ca_o [0] connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:42255$1658_Y + connect \Y $and$libresoc.v:42303$1658_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42257$1660 + cell $and $and$libresoc.v:42305$1660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67077,10 +67113,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1394 connect \B \$1398 - connect \Y $and$libresoc.v:42257$1660_Y + connect \Y $and$libresoc.v:42305$1660_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42258$1661 + cell $and $and$libresoc.v:42306$1661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67088,10 +67124,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1394 connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:42258$1661_Y + connect \Y $and$libresoc.v:42306$1661_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42260$1663 + cell $and $and$libresoc.v:42308$1663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67099,10 +67135,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ca_ok$132 connect \B \fus_cu_busy_o$26 - connect \Y $and$libresoc.v:42260$1663_Y + connect \Y $and$libresoc.v:42308$1663_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42261$1664 + cell $and $and$libresoc.v:42309$1664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67110,10 +67146,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ca_o [1] connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:42261$1664_Y + connect \Y $and$libresoc.v:42309$1664_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42263$1666 + cell $and $and$libresoc.v:42311$1666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67121,10 +67157,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1410 connect \B \$1414 - connect \Y $and$libresoc.v:42263$1666_Y + connect \Y $and$libresoc.v:42311$1666_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42264$1667 + cell $and $and$libresoc.v:42312$1667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67132,10 +67168,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1410 connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:42264$1667_Y + connect \Y $and$libresoc.v:42312$1667_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42266$1669 + cell $and $and$libresoc.v:42314$1669 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67143,10 +67179,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ca_ok$133 connect \B \fus_cu_busy_o$35 - connect \Y $and$libresoc.v:42266$1669_Y + connect \Y $and$libresoc.v:42314$1669_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42267$1670 + cell $and $and$libresoc.v:42315$1670 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67154,10 +67190,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ca_o [2] connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:42267$1670_Y + connect \Y $and$libresoc.v:42315$1670_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42269$1672 + cell $and $and$libresoc.v:42317$1672 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67165,10 +67201,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1426 connect \B \$1430 - connect \Y $and$libresoc.v:42269$1672_Y + connect \Y $and$libresoc.v:42317$1672_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42270$1673 + cell $and $and$libresoc.v:42318$1673 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67176,10 +67212,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1426 connect \B \wrpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:42270$1673_Y + connect \Y $and$libresoc.v:42318$1673_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42277$1681 + cell $and $and$libresoc.v:42325$1681 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67187,10 +67223,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ov_ok connect \B \fus_cu_busy_o - connect \Y $and$libresoc.v:42277$1681_Y + connect \Y $and$libresoc.v:42325$1681_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42278$1682 + cell $and $and$libresoc.v:42326$1682 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67198,10 +67234,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [3] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42278$1682_Y + connect \Y $and$libresoc.v:42326$1682_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42279$1683 + cell $and $and$libresoc.v:42327$1683 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67209,10 +67245,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$102 [4] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42279$1683_Y + connect \Y $and$libresoc.v:42327$1683_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42280$1684 + cell $and $and$libresoc.v:42328$1684 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67220,10 +67256,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$105 [2] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:42280$1684_Y + connect \Y $and$libresoc.v:42328$1684_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42281$1685 + cell $and $and$libresoc.v:42329$1685 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67231,10 +67267,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$108 [2] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:42281$1685_Y + connect \Y $and$libresoc.v:42329$1685_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42282$1686 + cell $and $and$libresoc.v:42330$1686 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67242,10 +67278,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ov_o [0] connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:42282$1686_Y + connect \Y $and$libresoc.v:42330$1686_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42284$1688 + cell $and $and$libresoc.v:42332$1688 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67253,10 +67289,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1460 connect \B \$1464 - connect \Y $and$libresoc.v:42284$1688_Y + connect \Y $and$libresoc.v:42332$1688_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42285$1689 + cell $and $and$libresoc.v:42333$1689 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67264,10 +67300,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1460 connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:42285$1689_Y + connect \Y $and$libresoc.v:42333$1689_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42287$1691 + cell $and $and$libresoc.v:42335$1691 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67275,10 +67311,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ov_ok$136 connect \B \fus_cu_busy_o$26 - connect \Y $and$libresoc.v:42287$1691_Y + connect \Y $and$libresoc.v:42335$1691_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42288$1692 + cell $and $and$libresoc.v:42336$1692 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67286,10 +67322,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ov_o [1] connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:42288$1692_Y + connect \Y $and$libresoc.v:42336$1692_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42290$1694 + cell $and $and$libresoc.v:42338$1694 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67297,10 +67333,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1476 connect \B \$1480 - connect \Y $and$libresoc.v:42290$1694_Y + connect \Y $and$libresoc.v:42338$1694_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42291$1695 + cell $and $and$libresoc.v:42339$1695 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67308,10 +67344,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1476 connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:42291$1695_Y + connect \Y $and$libresoc.v:42339$1695_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42293$1697 + cell $and $and$libresoc.v:42341$1697 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67319,10 +67355,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ov_ok$137 connect \B \fus_cu_busy_o$29 - connect \Y $and$libresoc.v:42293$1697_Y + connect \Y $and$libresoc.v:42341$1697_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42294$1698 + cell $and $and$libresoc.v:42342$1698 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67330,10 +67366,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ov_o [2] connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:42294$1698_Y + connect \Y $and$libresoc.v:42342$1698_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42296$1700 + cell $and $and$libresoc.v:42344$1700 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67341,10 +67377,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1492 connect \B \$1496 - connect \Y $and$libresoc.v:42296$1700_Y + connect \Y $and$libresoc.v:42344$1700_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42297$1701 + cell $and $and$libresoc.v:42345$1701 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67352,10 +67388,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1492 connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:42297$1701_Y + connect \Y $and$libresoc.v:42345$1701_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42299$1703 + cell $and $and$libresoc.v:42347$1703 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67363,10 +67399,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_ov_ok$138 connect \B \fus_cu_busy_o$32 - connect \Y $and$libresoc.v:42299$1703_Y + connect \Y $and$libresoc.v:42347$1703_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42300$1704 + cell $and $and$libresoc.v:42348$1704 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67374,10 +67410,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_ov_o [3] connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:42300$1704_Y + connect \Y $and$libresoc.v:42348$1704_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42302$1706 + cell $and $and$libresoc.v:42350$1706 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67385,10 +67421,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1508 connect \B \$1512 - connect \Y $and$libresoc.v:42302$1706_Y + connect \Y $and$libresoc.v:42350$1706_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42303$1707 + cell $and $and$libresoc.v:42351$1707 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67396,10 +67432,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1508 connect \B \wrpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:42303$1707_Y + connect \Y $and$libresoc.v:42351$1707_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42311$1715 + cell $and $and$libresoc.v:42359$1715 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67407,10 +67443,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_so_ok connect \B \fus_cu_busy_o - connect \Y $and$libresoc.v:42311$1715_Y + connect \Y $and$libresoc.v:42359$1715_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42312$1716 + cell $and $and$libresoc.v:42360$1716 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67418,10 +67454,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [4] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42312$1716_Y + connect \Y $and$libresoc.v:42360$1716_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42313$1717 + cell $and $and$libresoc.v:42361$1717 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67429,10 +67465,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$102 [3] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42313$1717_Y + connect \Y $and$libresoc.v:42361$1717_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42314$1718 + cell $and $and$libresoc.v:42362$1718 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67440,10 +67476,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$105 [3] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:42314$1718_Y + connect \Y $and$libresoc.v:42362$1718_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42315$1719 + cell $and $and$libresoc.v:42363$1719 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67451,10 +67487,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$108 [3] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:42315$1719_Y + connect \Y $and$libresoc.v:42363$1719_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42316$1720 + cell $and $and$libresoc.v:42364$1720 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67462,10 +67498,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_so_o [0] connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42316$1720_Y + connect \Y $and$libresoc.v:42364$1720_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42318$1722 + cell $and $and$libresoc.v:42366$1722 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67473,10 +67509,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1544 connect \B \$1548 - connect \Y $and$libresoc.v:42318$1722_Y + connect \Y $and$libresoc.v:42366$1722_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42319$1723 + cell $and $and$libresoc.v:42367$1723 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67484,10 +67520,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1544 connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42319$1723_Y + connect \Y $and$libresoc.v:42367$1723_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42321$1725 + cell $and $and$libresoc.v:42369$1725 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67495,10 +67531,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_so_ok$141 connect \B \fus_cu_busy_o$26 - connect \Y $and$libresoc.v:42321$1725_Y + connect \Y $and$libresoc.v:42369$1725_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42322$1726 + cell $and $and$libresoc.v:42370$1726 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67506,10 +67542,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_so_o [1] connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42322$1726_Y + connect \Y $and$libresoc.v:42370$1726_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42324$1728 + cell $and $and$libresoc.v:42372$1728 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67517,10 +67553,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1560 connect \B \$1564 - connect \Y $and$libresoc.v:42324$1728_Y + connect \Y $and$libresoc.v:42372$1728_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42325$1729 + cell $and $and$libresoc.v:42373$1729 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67528,10 +67564,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1560 connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42325$1729_Y + connect \Y $and$libresoc.v:42373$1729_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42327$1731 + cell $and $and$libresoc.v:42375$1731 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67539,10 +67575,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_so_ok$142 connect \B \fus_cu_busy_o$29 - connect \Y $and$libresoc.v:42327$1731_Y + connect \Y $and$libresoc.v:42375$1731_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42328$1732 + cell $and $and$libresoc.v:42376$1732 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67550,10 +67586,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_so_o [2] connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42328$1732_Y + connect \Y $and$libresoc.v:42376$1732_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42330$1734 + cell $and $and$libresoc.v:42378$1734 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67561,10 +67597,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1576 connect \B \$1580 - connect \Y $and$libresoc.v:42330$1734_Y + connect \Y $and$libresoc.v:42378$1734_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42331$1735 + cell $and $and$libresoc.v:42379$1735 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67572,10 +67608,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1576 connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42331$1735_Y + connect \Y $and$libresoc.v:42379$1735_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42333$1737 + cell $and $and$libresoc.v:42381$1737 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67583,10 +67619,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_xer_so_ok$143 connect \B \fus_cu_busy_o$32 - connect \Y $and$libresoc.v:42333$1737_Y + connect \Y $and$libresoc.v:42381$1737_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42334$1738 + cell $and $and$libresoc.v:42382$1738 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67594,10 +67630,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_XER_xer_so_o [3] connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42334$1738_Y + connect \Y $and$libresoc.v:42382$1738_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42336$1740 + cell $and $and$libresoc.v:42384$1740 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67605,10 +67641,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1592 connect \B \$1596 - connect \Y $and$libresoc.v:42336$1740_Y + connect \Y $and$libresoc.v:42384$1740_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42337$1741 + cell $and $and$libresoc.v:42385$1741 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67616,10 +67652,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1592 connect \B \wrpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42337$1741_Y + connect \Y $and$libresoc.v:42385$1741_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42347$1753 + cell $and $and$libresoc.v:42395$1753 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67627,10 +67663,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_fast1_ok connect \B \fus_cu_busy_o$17 - connect \Y $and$libresoc.v:42347$1753_Y + connect \Y $and$libresoc.v:42395$1753_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42348$1754 + cell $and $and$libresoc.v:42396$1754 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67638,10 +67674,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$148 [0] connect \B \fu_enable [2] - connect \Y $and$libresoc.v:42348$1754_Y + connect \Y $and$libresoc.v:42396$1754_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42349$1755 + cell $and $and$libresoc.v:42397$1755 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67649,10 +67685,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$96 [1] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42349$1755_Y + connect \Y $and$libresoc.v:42397$1755_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42350$1756 + cell $and $and$libresoc.v:42398$1756 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67660,10 +67696,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$102 [2] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42350$1756_Y + connect \Y $and$libresoc.v:42398$1756_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42351$1757 + cell $and $and$libresoc.v:42399$1757 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67671,10 +67707,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$148 [1] connect \B \fu_enable [2] - connect \Y $and$libresoc.v:42351$1757_Y + connect \Y $and$libresoc.v:42399$1757_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42352$1758 + cell $and $and$libresoc.v:42400$1758 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67682,10 +67718,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$96 [2] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42352$1758_Y + connect \Y $and$libresoc.v:42400$1758_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42353$1759 + cell $and $and$libresoc.v:42401$1759 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67693,10 +67729,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [0] connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42353$1759_Y + connect \Y $and$libresoc.v:42401$1759_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42355$1761 + cell $and $and$libresoc.v:42403$1761 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67704,10 +67740,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1634 connect \B \$1639 - connect \Y $and$libresoc.v:42355$1761_Y + connect \Y $and$libresoc.v:42403$1761_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42356$1762 + cell $and $and$libresoc.v:42404$1762 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67715,10 +67751,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1634 connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42356$1762_Y + connect \Y $and$libresoc.v:42404$1762_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42358$1764 + cell $and $and$libresoc.v:42406$1764 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67726,10 +67762,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_fast1_ok$150 connect \B \fus_cu_busy_o$20 - connect \Y $and$libresoc.v:42358$1764_Y + connect \Y $and$libresoc.v:42406$1764_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42359$1765 + cell $and $and$libresoc.v:42407$1765 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67737,10 +67773,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [1] connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42359$1765_Y + connect \Y $and$libresoc.v:42407$1765_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42361$1767 + cell $and $and$libresoc.v:42409$1767 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67748,10 +67784,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1653 connect \B \$1657 - connect \Y $and$libresoc.v:42361$1767_Y + connect \Y $and$libresoc.v:42409$1767_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42362$1768 + cell $and $and$libresoc.v:42410$1768 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67759,10 +67795,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1653 connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42362$1768_Y + connect \Y $and$libresoc.v:42410$1768_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42364$1770 + cell $and $and$libresoc.v:42412$1770 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67770,10 +67806,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_fast1_ok$151 connect \B \fus_cu_busy_o$26 - connect \Y $and$libresoc.v:42364$1770_Y + connect \Y $and$libresoc.v:42412$1770_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42365$1771 + cell $and $and$libresoc.v:42413$1771 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67781,10 +67817,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [2] connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42365$1771_Y + connect \Y $and$libresoc.v:42413$1771_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42367$1773 + cell $and $and$libresoc.v:42415$1773 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67792,10 +67828,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1669 connect \B \$1673 - connect \Y $and$libresoc.v:42367$1773_Y + connect \Y $and$libresoc.v:42415$1773_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42368$1774 + cell $and $and$libresoc.v:42416$1774 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67803,10 +67839,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1669 connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42368$1774_Y + connect \Y $and$libresoc.v:42416$1774_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42370$1776 + cell $and $and$libresoc.v:42418$1776 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67814,10 +67850,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_fast2_ok connect \B \fus_cu_busy_o$17 - connect \Y $and$libresoc.v:42370$1776_Y + connect \Y $and$libresoc.v:42418$1776_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42371$1777 + cell $and $and$libresoc.v:42419$1777 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67825,10 +67861,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [3] connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42371$1777_Y + connect \Y $and$libresoc.v:42419$1777_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42373$1779 + cell $and $and$libresoc.v:42421$1779 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67836,10 +67872,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1685 connect \B \$1689 - connect \Y $and$libresoc.v:42373$1779_Y + connect \Y $and$libresoc.v:42421$1779_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42374$1780 + cell $and $and$libresoc.v:42422$1780 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67847,10 +67883,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1685 connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42374$1780_Y + connect \Y $and$libresoc.v:42422$1780_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42376$1782 + cell $and $and$libresoc.v:42424$1782 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67858,10 +67894,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_fast2_ok$152 connect \B \fus_cu_busy_o$20 - connect \Y $and$libresoc.v:42376$1782_Y + connect \Y $and$libresoc.v:42424$1782_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42377$1783 + cell $and $and$libresoc.v:42425$1783 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67869,10 +67905,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_FAST_fast1_o [4] connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42377$1783_Y + connect \Y $and$libresoc.v:42425$1783_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42379$1785 + cell $and $and$libresoc.v:42427$1785 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67880,10 +67916,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1701 connect \B \$1705 - connect \Y $and$libresoc.v:42379$1785_Y + connect \Y $and$libresoc.v:42427$1785_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42380$1786 + cell $and $and$libresoc.v:42428$1786 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67891,10 +67927,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1701 connect \B \wrpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42380$1786_Y + connect \Y $and$libresoc.v:42428$1786_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42394$1800 + cell $and $and$libresoc.v:42442$1800 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67902,10 +67938,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_nia_ok connect \B \fus_cu_busy_o$17 - connect \Y $and$libresoc.v:42394$1800_Y + connect \Y $and$libresoc.v:42442$1800_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42395$1801 + cell $and $and$libresoc.v:42443$1801 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67913,10 +67949,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$148 [2] connect \B \fu_enable [2] - connect \Y $and$libresoc.v:42395$1801_Y + connect \Y $and$libresoc.v:42443$1801_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42396$1802 + cell $and $and$libresoc.v:42444$1802 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67924,10 +67960,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$96 [3] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42396$1802_Y + connect \Y $and$libresoc.v:42444$1802_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42397$1803 + cell $and $and$libresoc.v:42445$1803 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67935,10 +67971,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_STATE_nia_o [0] connect \B \wrpick_STATE_nia_en_o - connect \Y $and$libresoc.v:42397$1803_Y + connect \Y $and$libresoc.v:42445$1803_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42399$1805 + cell $and $and$libresoc.v:42447$1805 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67946,10 +67982,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1745 connect \B \$1749 - connect \Y $and$libresoc.v:42399$1805_Y + connect \Y $and$libresoc.v:42447$1805_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42400$1806 + cell $and $and$libresoc.v:42448$1806 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67957,10 +67993,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1745 connect \B \wrpick_STATE_nia_en_o - connect \Y $and$libresoc.v:42400$1806_Y + connect \Y $and$libresoc.v:42448$1806_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42402$1808 + cell $and $and$libresoc.v:42450$1808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67968,10 +68004,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_nia_ok$158 connect \B \fus_cu_busy_o$20 - connect \Y $and$libresoc.v:42402$1808_Y + connect \Y $and$libresoc.v:42450$1808_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42403$1809 + cell $and $and$libresoc.v:42451$1809 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67979,10 +68015,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_STATE_nia_o [1] connect \B \wrpick_STATE_nia_en_o - connect \Y $and$libresoc.v:42403$1809_Y + connect \Y $and$libresoc.v:42451$1809_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42405$1811 + cell $and $and$libresoc.v:42453$1811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -67990,10 +68026,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1761 connect \B \$1765 - connect \Y $and$libresoc.v:42405$1811_Y + connect \Y $and$libresoc.v:42453$1811_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42406$1812 + cell $and $and$libresoc.v:42454$1812 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68001,10 +68037,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1761 connect \B \wrpick_STATE_nia_en_o - connect \Y $and$libresoc.v:42406$1812_Y + connect \Y $and$libresoc.v:42454$1812_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42411$1818 + cell $and $and$libresoc.v:42459$1818 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68012,10 +68048,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_msr_ok connect \B \fus_cu_busy_o$20 - connect \Y $and$libresoc.v:42411$1818_Y + connect \Y $and$libresoc.v:42459$1818_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42412$1819 + cell $and $and$libresoc.v:42460$1819 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68023,10 +68059,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$96 [4] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42412$1819_Y + connect \Y $and$libresoc.v:42460$1819_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42413$1820 + cell $and $and$libresoc.v:42461$1820 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68034,10 +68070,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_STATE_msr_o connect \B \wrpick_STATE_msr_en_o - connect \Y $and$libresoc.v:42413$1820_Y + connect \Y $and$libresoc.v:42461$1820_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42415$1822 + cell $and $and$libresoc.v:42463$1822 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68045,10 +68081,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1785 connect \B \$1789 - connect \Y $and$libresoc.v:42415$1822_Y + connect \Y $and$libresoc.v:42463$1822_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42416$1823 + cell $and $and$libresoc.v:42464$1823 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68056,10 +68092,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1785 connect \B \wrpick_STATE_msr_en_o - connect \Y $and$libresoc.v:42416$1823_Y + connect \Y $and$libresoc.v:42464$1823_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42419$1827 + cell $and $and$libresoc.v:42467$1827 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68067,10 +68103,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_spr1_ok connect \B \fus_cu_busy_o$26 - connect \Y $and$libresoc.v:42419$1827_Y + connect \Y $and$libresoc.v:42467$1827_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42420$1828 + cell $and $and$libresoc.v:42468$1828 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68078,10 +68114,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$102 [1] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42420$1828_Y + connect \Y $and$libresoc.v:42468$1828_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42421$1829 + cell $and $and$libresoc.v:42469$1829 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68089,10 +68125,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_SPR_spr1_o connect \B \wrpick_SPR_spr1_en_o - connect \Y $and$libresoc.v:42421$1829_Y + connect \Y $and$libresoc.v:42469$1829_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42423$1831 + cell $and $and$libresoc.v:42471$1831 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68100,10 +68136,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1805 connect \B \$1809 - connect \Y $and$libresoc.v:42423$1831_Y + connect \Y $and$libresoc.v:42471$1831_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42424$1832 + cell $and $and$libresoc.v:42472$1832 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68111,10 +68147,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$1805 connect \B \wrpick_SPR_spr1_en_o - connect \Y $and$libresoc.v:42424$1832_Y + connect \Y $and$libresoc.v:42472$1832_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $and $and$libresoc.v:42426$1834 + cell $and $and$libresoc.v:42474$1834 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -68122,10 +68158,10 @@ module \core parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 2'10 - connect \Y $and$libresoc.v:42426$1834_Y + connect \Y $and$libresoc.v:42474$1834_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $and $and$libresoc.v:42428$1836 + cell $and $and$libresoc.v:42476$1836 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -68133,10 +68169,10 @@ module \core parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 7'1000000 - connect \Y $and$libresoc.v:42428$1836_Y + connect \Y $and$libresoc.v:42476$1836_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $and $and$libresoc.v:42430$1838 + cell $and $and$libresoc.v:42478$1838 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -68144,10 +68180,10 @@ module \core parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 6'100000 - connect \Y $and$libresoc.v:42430$1838_Y + connect \Y $and$libresoc.v:42478$1838_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $and $and$libresoc.v:42432$1840 + cell $and $and$libresoc.v:42480$1840 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -68155,10 +68191,10 @@ module \core parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 8'10000000 - connect \Y $and$libresoc.v:42432$1840_Y + connect \Y $and$libresoc.v:42480$1840_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $and $and$libresoc.v:42434$1842 + cell $and $and$libresoc.v:42482$1842 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -68166,10 +68202,10 @@ module \core parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 5'10000 - connect \Y $and$libresoc.v:42434$1842_Y + connect \Y $and$libresoc.v:42482$1842_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $and $and$libresoc.v:42436$1844 + cell $and $and$libresoc.v:42484$1844 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -68177,10 +68213,10 @@ module \core parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 11'10000000000 - connect \Y $and$libresoc.v:42436$1844_Y + connect \Y $and$libresoc.v:42484$1844_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $and $and$libresoc.v:42438$1846 + cell $and $and$libresoc.v:42486$1846 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -68188,10 +68224,10 @@ module \core parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 10'1000000000 - connect \Y $and$libresoc.v:42438$1846_Y + connect \Y $and$libresoc.v:42486$1846_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $and $and$libresoc.v:42440$1848 + cell $and $and$libresoc.v:42488$1848 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -68199,10 +68235,10 @@ module \core parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 9'100000000 - connect \Y $and$libresoc.v:42440$1848_Y + connect \Y $and$libresoc.v:42488$1848_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $and $and$libresoc.v:42442$1850 + cell $and $and$libresoc.v:42490$1850 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -68210,10 +68246,10 @@ module \core parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 4'1000 - connect \Y $and$libresoc.v:42442$1850_Y + connect \Y $and$libresoc.v:42490$1850_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $and $and$libresoc.v:42444$1852 + cell $and $and$libresoc.v:42492$1852 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -68221,10 +68257,10 @@ module \core parameter \Y_WIDTH 14 connect \A \core_core_fn_unit connect \B 3'100 - connect \Y $and$libresoc.v:42444$1852_Y + connect \Y $and$libresoc.v:42492$1852_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42449$1857 + cell $and $and$libresoc.v:42497$1857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68232,10 +68268,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42449$1857_Y + connect \Y $and$libresoc.v:42497$1857_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42450$1858 + cell $and $and$libresoc.v:42498$1858 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68243,10 +68279,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:42450$1858_Y + connect \Y $and$libresoc.v:42498$1858_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:42453$1861 + cell $and $and$libresoc.v:42501$1861 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68254,10 +68290,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:42453$1861_Y + connect \Y $and$libresoc.v:42501$1861_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $and $and$libresoc.v:42456$1864 + cell $and $and$libresoc.v:42504$1864 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68265,10 +68301,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 3'100 - connect \Y $and$libresoc.v:42456$1864_Y + connect \Y $and$libresoc.v:42504$1864_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42463$1871 + cell $and $and$libresoc.v:42511$1871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68276,10 +68312,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42463$1871_Y + connect \Y $and$libresoc.v:42511$1871_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42464$1872 + cell $and $and$libresoc.v:42512$1872 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68287,10 +68323,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:42464$1872_Y + connect \Y $and$libresoc.v:42512$1872_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:42467$1875 + cell $and $and$libresoc.v:42515$1875 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68298,10 +68334,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:42467$1875_Y + connect \Y $and$libresoc.v:42515$1875_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42470$1878 + cell $and $and$libresoc.v:42518$1878 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68309,10 +68345,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42470$1878_Y + connect \Y $and$libresoc.v:42518$1878_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42471$1879 + cell $and $and$libresoc.v:42519$1879 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68320,10 +68356,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:42471$1879_Y + connect \Y $and$libresoc.v:42519$1879_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:42474$1882 + cell $and $and$libresoc.v:42522$1882 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68331,10 +68367,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:42474$1882_Y + connect \Y $and$libresoc.v:42522$1882_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - cell $and $and$libresoc.v:42476$1884 + cell $and $and$libresoc.v:42524$1884 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68342,10 +68378,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42476$1884_Y + connect \Y $and$libresoc.v:42524$1884_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $and $and$libresoc.v:42477$1885 + cell $and $and$libresoc.v:42525$1885 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68353,10 +68389,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 2'10 - connect \Y $and$libresoc.v:42477$1885_Y + connect \Y $and$libresoc.v:42525$1885_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $and $and$libresoc.v:42481$1889 + cell $and $and$libresoc.v:42529$1889 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68364,10 +68400,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 3'100 - connect \Y $and$libresoc.v:42481$1889_Y + connect \Y $and$libresoc.v:42529$1889_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42485$1893 + cell $and $and$libresoc.v:42533$1893 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68375,10 +68411,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42485$1893_Y + connect \Y $and$libresoc.v:42533$1893_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42486$1894 + cell $and $and$libresoc.v:42534$1894 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68386,10 +68422,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:42486$1894_Y + connect \Y $and$libresoc.v:42534$1894_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:42489$1897 + cell $and $and$libresoc.v:42537$1897 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68397,10 +68433,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:42489$1897_Y + connect \Y $and$libresoc.v:42537$1897_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42492$1900 + cell $and $and$libresoc.v:42540$1900 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68408,10 +68444,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42492$1900_Y + connect \Y $and$libresoc.v:42540$1900_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42493$1901 + cell $and $and$libresoc.v:42541$1901 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68419,10 +68455,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:42493$1901_Y + connect \Y $and$libresoc.v:42541$1901_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:42496$1904 + cell $and $and$libresoc.v:42544$1904 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68430,10 +68466,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:42496$1904_Y + connect \Y $and$libresoc.v:42544$1904_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42499$1907 + cell $and $and$libresoc.v:42547$1907 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68441,10 +68477,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42499$1907_Y + connect \Y $and$libresoc.v:42547$1907_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42500$1908 + cell $and $and$libresoc.v:42548$1908 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68452,10 +68488,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:42500$1908_Y + connect \Y $and$libresoc.v:42548$1908_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:42503$1911 + cell $and $and$libresoc.v:42551$1911 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68463,10 +68499,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:42503$1911_Y + connect \Y $and$libresoc.v:42551$1911_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $and $and$libresoc.v:42506$1914 + cell $and $and$libresoc.v:42554$1914 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -68474,10 +68510,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 3'100 - connect \Y $and$libresoc.v:42506$1914_Y + connect \Y $and$libresoc.v:42554$1914_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42511$1919 + cell $and $and$libresoc.v:42559$1919 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68485,10 +68521,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o [0] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42511$1919_Y + connect \Y $and$libresoc.v:42559$1919_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42512$1920 + cell $and $and$libresoc.v:42560$1920 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68496,10 +68532,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$352 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:42512$1920_Y + connect \Y $and$libresoc.v:42560$1920_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42514$1922 + cell $and $and$libresoc.v:42562$1922 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68507,10 +68543,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$354 connect \B \$356 - connect \Y $and$libresoc.v:42514$1922_Y + connect \Y $and$libresoc.v:42562$1922_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42515$1923 + cell $and $and$libresoc.v:42563$1923 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68518,10 +68554,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [0] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:42515$1923_Y + connect \Y $and$libresoc.v:42563$1923_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42517$1925 + cell $and $and$libresoc.v:42565$1925 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68529,10 +68565,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$40 [0] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42517$1925_Y + connect \Y $and$libresoc.v:42565$1925_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42518$1926 + cell $and $and$libresoc.v:42566$1926 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68540,10 +68576,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$364 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:42518$1926_Y + connect \Y $and$libresoc.v:42566$1926_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42520$1928 + cell $and $and$libresoc.v:42568$1928 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68551,10 +68587,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$366 connect \B \$368 - connect \Y $and$libresoc.v:42520$1928_Y + connect \Y $and$libresoc.v:42568$1928_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42521$1929 + cell $and $and$libresoc.v:42569$1929 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68562,10 +68598,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [1] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:42521$1929_Y + connect \Y $and$libresoc.v:42569$1929_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42523$1931 + cell $and $and$libresoc.v:42571$1931 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68573,10 +68609,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$43 [0] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42523$1931_Y + connect \Y $and$libresoc.v:42571$1931_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42524$1932 + cell $and $and$libresoc.v:42572$1932 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68584,10 +68620,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$376 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:42524$1932_Y + connect \Y $and$libresoc.v:42572$1932_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42526$1934 + cell $and $and$libresoc.v:42574$1934 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68595,10 +68631,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$378 connect \B \$380 - connect \Y $and$libresoc.v:42526$1934_Y + connect \Y $and$libresoc.v:42574$1934_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42527$1935 + cell $and $and$libresoc.v:42575$1935 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68606,10 +68642,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [2] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:42527$1935_Y + connect \Y $and$libresoc.v:42575$1935_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42529$1937 + cell $and $and$libresoc.v:42577$1937 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68617,10 +68653,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$46 [0] connect \B \fu_enable [4] - connect \Y $and$libresoc.v:42529$1937_Y + connect \Y $and$libresoc.v:42577$1937_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42530$1938 + cell $and $and$libresoc.v:42578$1938 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68628,10 +68664,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$388 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:42530$1938_Y + connect \Y $and$libresoc.v:42578$1938_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42532$1940 + cell $and $and$libresoc.v:42580$1940 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68639,10 +68675,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$390 connect \B \$392 - connect \Y $and$libresoc.v:42532$1940_Y + connect \Y $and$libresoc.v:42580$1940_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42533$1941 + cell $and $and$libresoc.v:42581$1941 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68650,10 +68686,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [3] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:42533$1941_Y + connect \Y $and$libresoc.v:42581$1941_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42535$1943 + cell $and $and$libresoc.v:42583$1943 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68661,10 +68697,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$49 [0] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42535$1943_Y + connect \Y $and$libresoc.v:42583$1943_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42536$1944 + cell $and $and$libresoc.v:42584$1944 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68672,10 +68708,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$400 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:42536$1944_Y + connect \Y $and$libresoc.v:42584$1944_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42538$1946 + cell $and $and$libresoc.v:42586$1946 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68683,10 +68719,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$402 connect \B \$404 - connect \Y $and$libresoc.v:42538$1946_Y + connect \Y $and$libresoc.v:42586$1946_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42539$1947 + cell $and $and$libresoc.v:42587$1947 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68694,10 +68730,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [4] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:42539$1947_Y + connect \Y $and$libresoc.v:42587$1947_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42541$1949 + cell $and $and$libresoc.v:42589$1949 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68705,10 +68741,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$52 [0] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:42541$1949_Y + connect \Y $and$libresoc.v:42589$1949_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42542$1950 + cell $and $and$libresoc.v:42590$1950 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68716,10 +68752,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$412 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:42542$1950_Y + connect \Y $and$libresoc.v:42590$1950_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42544$1952 + cell $and $and$libresoc.v:42592$1952 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68727,10 +68763,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$414 connect \B \$416 - connect \Y $and$libresoc.v:42544$1952_Y + connect \Y $and$libresoc.v:42592$1952_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42545$1953 + cell $and $and$libresoc.v:42593$1953 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68738,10 +68774,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [5] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:42545$1953_Y + connect \Y $and$libresoc.v:42593$1953_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42547$1955 + cell $and $and$libresoc.v:42595$1955 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68749,10 +68785,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$55 [0] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:42547$1955_Y + connect \Y $and$libresoc.v:42595$1955_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42548$1956 + cell $and $and$libresoc.v:42596$1956 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68760,10 +68796,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$424 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:42548$1956_Y + connect \Y $and$libresoc.v:42596$1956_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42550$1958 + cell $and $and$libresoc.v:42598$1958 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68771,10 +68807,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$426 connect \B \$428 - connect \Y $and$libresoc.v:42550$1958_Y + connect \Y $and$libresoc.v:42598$1958_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42551$1959 + cell $and $and$libresoc.v:42599$1959 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68782,10 +68818,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [6] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:42551$1959_Y + connect \Y $and$libresoc.v:42599$1959_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42553$1961 + cell $and $and$libresoc.v:42601$1961 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68793,10 +68829,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$58 [0] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:42553$1961_Y + connect \Y $and$libresoc.v:42601$1961_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42554$1962 + cell $and $and$libresoc.v:42602$1962 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68804,10 +68840,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$436 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:42554$1962_Y + connect \Y $and$libresoc.v:42602$1962_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42556$1964 + cell $and $and$libresoc.v:42604$1964 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68815,10 +68851,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$438 connect \B \$440 - connect \Y $and$libresoc.v:42556$1964_Y + connect \Y $and$libresoc.v:42604$1964_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42557$1965 + cell $and $and$libresoc.v:42605$1965 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68826,10 +68862,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [7] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:42557$1965_Y + connect \Y $and$libresoc.v:42605$1965_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42559$1967 + cell $and $and$libresoc.v:42607$1967 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68837,10 +68873,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$61 [0] connect \B \fu_enable [9] - connect \Y $and$libresoc.v:42559$1967_Y + connect \Y $and$libresoc.v:42607$1967_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42560$1968 + cell $and $and$libresoc.v:42608$1968 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68848,10 +68884,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$448 connect \B \rdflag_INT_ra_0 - connect \Y $and$libresoc.v:42560$1968_Y + connect \Y $and$libresoc.v:42608$1968_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42562$1970 + cell $and $and$libresoc.v:42610$1970 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68859,10 +68895,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$450 connect \B \$452 - connect \Y $and$libresoc.v:42562$1970_Y + connect \Y $and$libresoc.v:42610$1970_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42563$1971 + cell $and $and$libresoc.v:42611$1971 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68870,10 +68906,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_ra_o [8] connect \B \rdpick_INT_ra_en_o - connect \Y $and$libresoc.v:42563$1971_Y + connect \Y $and$libresoc.v:42611$1971_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42574$1982 + cell $and $and$libresoc.v:42622$1982 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68881,10 +68917,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o [1] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42574$1982_Y + connect \Y $and$libresoc.v:42622$1982_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42575$1983 + cell $and $and$libresoc.v:42623$1983 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68892,10 +68928,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$479 connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:42575$1983_Y + connect \Y $and$libresoc.v:42623$1983_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42577$1985 + cell $and $and$libresoc.v:42625$1985 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68903,10 +68939,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$481 connect \B \$483 - connect \Y $and$libresoc.v:42577$1985_Y + connect \Y $and$libresoc.v:42625$1985_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42578$1986 + cell $and $and$libresoc.v:42626$1986 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68914,10 +68950,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [0] connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:42578$1986_Y + connect \Y $and$libresoc.v:42626$1986_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42580$1988 + cell $and $and$libresoc.v:42628$1988 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68925,10 +68961,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$40 [1] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42580$1988_Y + connect \Y $and$libresoc.v:42628$1988_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42581$1989 + cell $and $and$libresoc.v:42629$1989 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68936,10 +68972,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$491 connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:42581$1989_Y + connect \Y $and$libresoc.v:42629$1989_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42583$1991 + cell $and $and$libresoc.v:42631$1991 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68947,10 +68983,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$493 connect \B \$495 - connect \Y $and$libresoc.v:42583$1991_Y + connect \Y $and$libresoc.v:42631$1991_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42584$1992 + cell $and $and$libresoc.v:42632$1992 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68958,10 +68994,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [1] connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:42584$1992_Y + connect \Y $and$libresoc.v:42632$1992_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42586$1994 + cell $and $and$libresoc.v:42634$1994 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68969,10 +69005,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$43 [1] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42586$1994_Y + connect \Y $and$libresoc.v:42634$1994_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42587$1995 + cell $and $and$libresoc.v:42635$1995 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68980,10 +69016,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$503 connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:42587$1995_Y + connect \Y $and$libresoc.v:42635$1995_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42589$1997 + cell $and $and$libresoc.v:42637$1997 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -68991,10 +69027,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$505 connect \B \$507 - connect \Y $and$libresoc.v:42589$1997_Y + connect \Y $and$libresoc.v:42637$1997_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42590$1998 + cell $and $and$libresoc.v:42638$1998 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69002,10 +69038,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [2] connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:42590$1998_Y + connect \Y $and$libresoc.v:42638$1998_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42592$2000 + cell $and $and$libresoc.v:42640$2000 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69013,10 +69049,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$46 [1] connect \B \fu_enable [4] - connect \Y $and$libresoc.v:42592$2000_Y + connect \Y $and$libresoc.v:42640$2000_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42593$2001 + cell $and $and$libresoc.v:42641$2001 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69024,10 +69060,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$515 connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:42593$2001_Y + connect \Y $and$libresoc.v:42641$2001_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42595$2003 + cell $and $and$libresoc.v:42643$2003 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69035,10 +69071,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$517 connect \B \$519 - connect \Y $and$libresoc.v:42595$2003_Y + connect \Y $and$libresoc.v:42643$2003_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42596$2004 + cell $and $and$libresoc.v:42644$2004 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69046,10 +69082,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [3] connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:42596$2004_Y + connect \Y $and$libresoc.v:42644$2004_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42598$2006 + cell $and $and$libresoc.v:42646$2006 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69057,10 +69093,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$52 [1] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:42598$2006_Y + connect \Y $and$libresoc.v:42646$2006_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42599$2007 + cell $and $and$libresoc.v:42647$2007 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69068,10 +69104,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$527 connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:42599$2007_Y + connect \Y $and$libresoc.v:42647$2007_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42601$2009 + cell $and $and$libresoc.v:42649$2009 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69079,10 +69115,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$529 connect \B \$531 - connect \Y $and$libresoc.v:42601$2009_Y + connect \Y $and$libresoc.v:42649$2009_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42602$2010 + cell $and $and$libresoc.v:42650$2010 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69090,10 +69126,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [4] connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:42602$2010_Y + connect \Y $and$libresoc.v:42650$2010_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42604$2012 + cell $and $and$libresoc.v:42652$2012 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69101,10 +69137,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$55 [1] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:42604$2012_Y + connect \Y $and$libresoc.v:42652$2012_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42605$2013 + cell $and $and$libresoc.v:42653$2013 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69112,10 +69148,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$539 connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:42605$2013_Y + connect \Y $and$libresoc.v:42653$2013_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42607$2015 + cell $and $and$libresoc.v:42655$2015 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69123,10 +69159,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$541 connect \B \$543 - connect \Y $and$libresoc.v:42607$2015_Y + connect \Y $and$libresoc.v:42655$2015_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42608$2016 + cell $and $and$libresoc.v:42656$2016 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69134,10 +69170,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [5] connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:42608$2016_Y + connect \Y $and$libresoc.v:42656$2016_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42610$2018 + cell $and $and$libresoc.v:42658$2018 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69145,10 +69181,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$58 [1] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:42610$2018_Y + connect \Y $and$libresoc.v:42658$2018_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42611$2019 + cell $and $and$libresoc.v:42659$2019 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69156,10 +69192,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$551 connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:42611$2019_Y + connect \Y $and$libresoc.v:42659$2019_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42613$2021 + cell $and $and$libresoc.v:42661$2021 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69167,10 +69203,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$553 connect \B \$555 - connect \Y $and$libresoc.v:42613$2021_Y + connect \Y $and$libresoc.v:42661$2021_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42614$2022 + cell $and $and$libresoc.v:42662$2022 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69178,10 +69214,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [6] connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:42614$2022_Y + connect \Y $and$libresoc.v:42662$2022_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42616$2024 + cell $and $and$libresoc.v:42664$2024 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69189,10 +69225,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$61 [1] connect \B \fu_enable [9] - connect \Y $and$libresoc.v:42616$2024_Y + connect \Y $and$libresoc.v:42664$2024_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42617$2025 + cell $and $and$libresoc.v:42665$2025 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69200,10 +69236,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$563 connect \B \rdflag_INT_rb_0 - connect \Y $and$libresoc.v:42617$2025_Y + connect \Y $and$libresoc.v:42665$2025_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42619$2027 + cell $and $and$libresoc.v:42667$2027 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69211,10 +69247,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$565 connect \B \$567 - connect \Y $and$libresoc.v:42619$2027_Y + connect \Y $and$libresoc.v:42667$2027_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42620$2028 + cell $and $and$libresoc.v:42668$2028 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69222,10 +69258,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rb_o [7] connect \B \rdpick_INT_rb_en_o - connect \Y $and$libresoc.v:42620$2028_Y + connect \Y $and$libresoc.v:42668$2028_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42630$2038 + cell $and $and$libresoc.v:42678$2038 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69233,10 +69269,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$58 [2] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:42630$2038_Y + connect \Y $and$libresoc.v:42678$2038_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42631$2039 + cell $and $and$libresoc.v:42679$2039 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69244,10 +69280,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$592 connect \B \rdflag_INT_rc_0 - connect \Y $and$libresoc.v:42631$2039_Y + connect \Y $and$libresoc.v:42679$2039_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42633$2041 + cell $and $and$libresoc.v:42681$2041 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69255,10 +69291,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$594 connect \B \$596 - connect \Y $and$libresoc.v:42633$2041_Y + connect \Y $and$libresoc.v:42681$2041_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42634$2042 + cell $and $and$libresoc.v:42682$2042 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69266,10 +69302,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rc_o [0] connect \B \rdpick_INT_rc_en_o - connect \Y $and$libresoc.v:42634$2042_Y + connect \Y $and$libresoc.v:42682$2042_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42636$2044 + cell $and $and$libresoc.v:42684$2044 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69277,10 +69313,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$61 [2] connect \B \fu_enable [9] - connect \Y $and$libresoc.v:42636$2044_Y + connect \Y $and$libresoc.v:42684$2044_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42637$2045 + cell $and $and$libresoc.v:42685$2045 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69288,10 +69324,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$604 connect \B \rdflag_INT_rc_0 - connect \Y $and$libresoc.v:42637$2045_Y + connect \Y $and$libresoc.v:42685$2045_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42639$2047 + cell $and $and$libresoc.v:42687$2047 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69299,10 +69335,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$606 connect \B \$608 - connect \Y $and$libresoc.v:42639$2047_Y + connect \Y $and$libresoc.v:42687$2047_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42640$2048 + cell $and $and$libresoc.v:42688$2048 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69310,10 +69346,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_INT_rc_o [1] connect \B \rdpick_INT_rc_en_o - connect \Y $and$libresoc.v:42640$2048_Y + connect \Y $and$libresoc.v:42688$2048_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42644$2052 + cell $and $and$libresoc.v:42692$2052 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69321,10 +69357,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42644$2052_Y + connect \Y $and$libresoc.v:42692$2052_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $and$libresoc.v:42645$2053 + cell $and $and$libresoc.v:42693$2053 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -69332,10 +69368,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 1'1 - connect \Y $and$libresoc.v:42645$2053_Y + connect \Y $and$libresoc.v:42693$2053_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $and$libresoc.v:42648$2056 + cell $and $and$libresoc.v:42696$2056 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69343,10 +69379,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_rc connect \B \core_core_rc_ok - connect \Y $and$libresoc.v:42648$2056_Y + connect \Y $and$libresoc.v:42696$2056_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42650$2058 + cell $and $and$libresoc.v:42698$2058 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69354,10 +69390,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o [2] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42650$2058_Y + connect \Y $and$libresoc.v:42698$2058_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42651$2059 + cell $and $and$libresoc.v:42699$2059 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69365,10 +69401,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$633 connect \B \rdflag_XER_xer_so_0 - connect \Y $and$libresoc.v:42651$2059_Y + connect \Y $and$libresoc.v:42699$2059_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42653$2061 + cell $and $and$libresoc.v:42701$2061 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69376,10 +69412,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$635 connect \B \$637 - connect \Y $and$libresoc.v:42653$2061_Y + connect \Y $and$libresoc.v:42701$2061_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42654$2062 + cell $and $and$libresoc.v:42702$2062 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69387,10 +69423,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [0] connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42654$2062_Y + connect \Y $and$libresoc.v:42702$2062_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42656$2064 + cell $and $and$libresoc.v:42704$2064 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69398,10 +69434,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$46 [2] connect \B \fu_enable [4] - connect \Y $and$libresoc.v:42656$2064_Y + connect \Y $and$libresoc.v:42704$2064_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42657$2065 + cell $and $and$libresoc.v:42705$2065 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69409,10 +69445,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$645 connect \B \rdflag_XER_xer_so_0 - connect \Y $and$libresoc.v:42657$2065_Y + connect \Y $and$libresoc.v:42705$2065_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42659$2067 + cell $and $and$libresoc.v:42707$2067 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69420,10 +69456,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$647 connect \B \$649 - connect \Y $and$libresoc.v:42659$2067_Y + connect \Y $and$libresoc.v:42707$2067_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42660$2068 + cell $and $and$libresoc.v:42708$2068 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69431,10 +69467,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [1] connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42660$2068_Y + connect \Y $and$libresoc.v:42708$2068_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42662$2070 + cell $and $and$libresoc.v:42710$2070 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69442,10 +69478,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$49 [3] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42662$2070_Y + connect \Y $and$libresoc.v:42710$2070_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42663$2071 + cell $and $and$libresoc.v:42711$2071 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69453,10 +69489,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$657 connect \B \rdflag_XER_xer_so_0 - connect \Y $and$libresoc.v:42663$2071_Y + connect \Y $and$libresoc.v:42711$2071_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42665$2073 + cell $and $and$libresoc.v:42713$2073 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69464,10 +69500,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$659 connect \B \$661 - connect \Y $and$libresoc.v:42665$2073_Y + connect \Y $and$libresoc.v:42713$2073_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42666$2074 + cell $and $and$libresoc.v:42714$2074 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69475,10 +69511,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [2] connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42666$2074_Y + connect \Y $and$libresoc.v:42714$2074_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42668$2076 + cell $and $and$libresoc.v:42716$2076 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69486,10 +69522,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$52 [2] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:42668$2076_Y + connect \Y $and$libresoc.v:42716$2076_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42669$2077 + cell $and $and$libresoc.v:42717$2077 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69497,10 +69533,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$669 connect \B \rdflag_XER_xer_so_0 - connect \Y $and$libresoc.v:42669$2077_Y + connect \Y $and$libresoc.v:42717$2077_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42671$2079 + cell $and $and$libresoc.v:42719$2079 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69508,10 +69544,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$671 connect \B \$673 - connect \Y $and$libresoc.v:42671$2079_Y + connect \Y $and$libresoc.v:42719$2079_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42672$2080 + cell $and $and$libresoc.v:42720$2080 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69519,10 +69555,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [3] connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42672$2080_Y + connect \Y $and$libresoc.v:42720$2080_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42674$2082 + cell $and $and$libresoc.v:42722$2082 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69530,10 +69566,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$55 [2] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:42674$2082_Y + connect \Y $and$libresoc.v:42722$2082_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42675$2083 + cell $and $and$libresoc.v:42723$2083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69541,10 +69577,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$681 connect \B \rdflag_XER_xer_so_0 - connect \Y $and$libresoc.v:42675$2083_Y + connect \Y $and$libresoc.v:42723$2083_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42677$2085 + cell $and $and$libresoc.v:42725$2085 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69552,10 +69588,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$683 connect \B \$685 - connect \Y $and$libresoc.v:42677$2085_Y + connect \Y $and$libresoc.v:42725$2085_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42678$2086 + cell $and $and$libresoc.v:42726$2086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69563,10 +69599,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [4] connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42678$2086_Y + connect \Y $and$libresoc.v:42726$2086_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42680$2088 + cell $and $and$libresoc.v:42728$2088 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69574,10 +69610,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$58 [3] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:42680$2088_Y + connect \Y $and$libresoc.v:42728$2088_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42681$2089 + cell $and $and$libresoc.v:42729$2089 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69585,10 +69621,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$693 connect \B \rdflag_XER_xer_so_0 - connect \Y $and$libresoc.v:42681$2089_Y + connect \Y $and$libresoc.v:42729$2089_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42683$2091 + cell $and $and$libresoc.v:42731$2091 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69596,10 +69632,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$695 connect \B \$697 - connect \Y $and$libresoc.v:42683$2091_Y + connect \Y $and$libresoc.v:42731$2091_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42684$2092 + cell $and $and$libresoc.v:42732$2092 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69607,10 +69643,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_so_o [5] connect \B \rdpick_XER_xer_so_en_o - connect \Y $and$libresoc.v:42684$2092_Y + connect \Y $and$libresoc.v:42732$2092_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $and $and$libresoc.v:42693$2102 + cell $and $and$libresoc.v:42741$2102 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -69618,10 +69654,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 3'100 - connect \Y $and$libresoc.v:42693$2102_Y + connect \Y $and$libresoc.v:42741$2102_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42696$2105 + cell $and $and$libresoc.v:42744$2105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69629,10 +69665,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o [3] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42696$2105_Y + connect \Y $and$libresoc.v:42744$2105_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42697$2106 + cell $and $and$libresoc.v:42745$2106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69640,10 +69676,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$725 connect \B \rdflag_XER_xer_ca_0 - connect \Y $and$libresoc.v:42697$2106_Y + connect \Y $and$libresoc.v:42745$2106_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42699$2108 + cell $and $and$libresoc.v:42747$2108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69651,10 +69687,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$727 connect \B \$729 - connect \Y $and$libresoc.v:42699$2108_Y + connect \Y $and$libresoc.v:42747$2108_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42700$2109 + cell $and $and$libresoc.v:42748$2109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69662,10 +69698,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_ca_o [0] connect \B \rdpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:42700$2109_Y + connect \Y $and$libresoc.v:42748$2109_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42702$2111 + cell $and $and$libresoc.v:42750$2111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69673,10 +69709,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$49 [5] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42702$2111_Y + connect \Y $and$libresoc.v:42750$2111_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42703$2112 + cell $and $and$libresoc.v:42751$2112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69684,10 +69720,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$737 connect \B \rdflag_XER_xer_ca_0 - connect \Y $and$libresoc.v:42703$2112_Y + connect \Y $and$libresoc.v:42751$2112_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42705$2114 + cell $and $and$libresoc.v:42753$2114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69695,10 +69731,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$739 connect \B \$741 - connect \Y $and$libresoc.v:42705$2114_Y + connect \Y $and$libresoc.v:42753$2114_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42706$2115 + cell $and $and$libresoc.v:42754$2115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69706,10 +69742,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_ca_o [1] connect \B \rdpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:42706$2115_Y + connect \Y $and$libresoc.v:42754$2115_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42708$2117 + cell $and $and$libresoc.v:42756$2117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69717,10 +69753,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$58 [4] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:42708$2117_Y + connect \Y $and$libresoc.v:42756$2117_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42709$2118 + cell $and $and$libresoc.v:42757$2118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69728,10 +69764,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$749 connect \B \rdflag_XER_xer_ca_0 - connect \Y $and$libresoc.v:42709$2118_Y + connect \Y $and$libresoc.v:42757$2118_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42711$2120 + cell $and $and$libresoc.v:42759$2120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69739,10 +69775,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$751 connect \B \$753 - connect \Y $and$libresoc.v:42711$2120_Y + connect \Y $and$libresoc.v:42759$2120_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42712$2121 + cell $and $and$libresoc.v:42760$2121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69750,10 +69786,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_ca_o [2] connect \B \rdpick_XER_xer_ca_en_o - connect \Y $and$libresoc.v:42712$2121_Y + connect \Y $and$libresoc.v:42760$2121_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - cell $and $and$libresoc.v:42717$2127 + cell $and $and$libresoc.v:42765$2127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69761,10 +69797,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_oe connect \B \core_core_oe_ok - connect \Y $and$libresoc.v:42717$2127_Y + connect \Y $and$libresoc.v:42765$2127_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $and $and$libresoc.v:42718$2128 + cell $and $and$libresoc.v:42766$2128 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -69772,10 +69808,10 @@ module \core parameter \Y_WIDTH 3 connect \A \core_xer_in connect \B 2'10 - connect \Y $and$libresoc.v:42718$2128_Y + connect \Y $and$libresoc.v:42766$2128_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42721$2131 + cell $and $and$libresoc.v:42769$2131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69783,10 +69819,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$49 [4] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42721$2131_Y + connect \Y $and$libresoc.v:42769$2131_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42722$2132 + cell $and $and$libresoc.v:42770$2132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69794,10 +69830,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$775 connect \B \rdflag_XER_xer_ov_0 - connect \Y $and$libresoc.v:42722$2132_Y + connect \Y $and$libresoc.v:42770$2132_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42724$2134 + cell $and $and$libresoc.v:42772$2134 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69805,10 +69841,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$777 connect \B \$779 - connect \Y $and$libresoc.v:42724$2134_Y + connect \Y $and$libresoc.v:42772$2134_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42725$2135 + cell $and $and$libresoc.v:42773$2135 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69816,10 +69852,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_XER_xer_ov_o connect \B \rdpick_XER_xer_ov_en_o - connect \Y $and$libresoc.v:42725$2135_Y + connect \Y $and$libresoc.v:42773$2135_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42727$2137 + cell $and $and$libresoc.v:42775$2137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69827,10 +69863,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$40 [2] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42727$2137_Y + connect \Y $and$libresoc.v:42775$2137_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42728$2138 + cell $and $and$libresoc.v:42776$2138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69838,10 +69874,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$787 connect \B \rdflag_CR_full_cr_0 - connect \Y $and$libresoc.v:42728$2138_Y + connect \Y $and$libresoc.v:42776$2138_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42730$2140 + cell $and $and$libresoc.v:42778$2140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69849,10 +69885,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$789 connect \B \$791 - connect \Y $and$libresoc.v:42730$2140_Y + connect \Y $and$libresoc.v:42778$2140_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42731$2141 + cell $and $and$libresoc.v:42779$2141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69860,10 +69896,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_full_cr_o connect \B \rdpick_CR_full_cr_en_o - connect \Y $and$libresoc.v:42731$2141_Y + connect \Y $and$libresoc.v:42779$2141_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42733$2143 + cell $and $and$libresoc.v:42781$2143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69871,10 +69907,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$40 [3] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42733$2143_Y + connect \Y $and$libresoc.v:42781$2143_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42734$2144 + cell $and $and$libresoc.v:42782$2144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69882,10 +69918,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$799 connect \B \rdflag_CR_cr_a_0 - connect \Y $and$libresoc.v:42734$2144_Y + connect \Y $and$libresoc.v:42782$2144_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42736$2146 + cell $and $and$libresoc.v:42784$2146 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69893,10 +69929,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$801 connect \B \$803 - connect \Y $and$libresoc.v:42736$2146_Y + connect \Y $and$libresoc.v:42784$2146_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42737$2147 + cell $and $and$libresoc.v:42785$2147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69904,10 +69940,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_cr_a_o [0] connect \B \rdpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42737$2147_Y + connect \Y $and$libresoc.v:42785$2147_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42741$2151 + cell $and $and$libresoc.v:42789$2151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69915,10 +69951,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$81 [2] connect \B \fu_enable [2] - connect \Y $and$libresoc.v:42741$2151_Y + connect \Y $and$libresoc.v:42789$2151_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42742$2152 + cell $and $and$libresoc.v:42790$2152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69926,10 +69962,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$815 connect \B \rdflag_CR_cr_a_0 - connect \Y $and$libresoc.v:42742$2152_Y + connect \Y $and$libresoc.v:42790$2152_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42744$2154 + cell $and $and$libresoc.v:42792$2154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69937,10 +69973,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$817 connect \B \$819 - connect \Y $and$libresoc.v:42744$2154_Y + connect \Y $and$libresoc.v:42792$2154_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42745$2155 + cell $and $and$libresoc.v:42793$2155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69948,10 +69984,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_cr_a_o [1] connect \B \rdpick_CR_cr_a_en_o - connect \Y $and$libresoc.v:42745$2155_Y + connect \Y $and$libresoc.v:42793$2155_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42750$2160 + cell $and $and$libresoc.v:42798$2160 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69959,10 +69995,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$40 [4] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42750$2160_Y + connect \Y $and$libresoc.v:42798$2160_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42751$2161 + cell $and $and$libresoc.v:42799$2161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69970,10 +70006,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$834 connect \B \rdflag_CR_cr_b_0 - connect \Y $and$libresoc.v:42751$2161_Y + connect \Y $and$libresoc.v:42799$2161_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42753$2163 + cell $and $and$libresoc.v:42801$2163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69981,10 +70017,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$836 connect \B \$838 - connect \Y $and$libresoc.v:42753$2163_Y + connect \Y $and$libresoc.v:42801$2163_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42754$2164 + cell $and $and$libresoc.v:42802$2164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -69992,10 +70028,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_cr_b_o connect \B \rdpick_CR_cr_b_en_o - connect \Y $and$libresoc.v:42754$2164_Y + connect \Y $and$libresoc.v:42802$2164_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42758$2168 + cell $and $and$libresoc.v:42806$2168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70003,10 +70039,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$40 [5] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42758$2168_Y + connect \Y $and$libresoc.v:42806$2168_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42759$2169 + cell $and $and$libresoc.v:42807$2169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70014,10 +70050,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$850 connect \B \rdflag_CR_cr_c_0 - connect \Y $and$libresoc.v:42759$2169_Y + connect \Y $and$libresoc.v:42807$2169_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42761$2171 + cell $and $and$libresoc.v:42809$2171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70025,10 +70061,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$852 connect \B \$854 - connect \Y $and$libresoc.v:42761$2171_Y + connect \Y $and$libresoc.v:42809$2171_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42762$2172 + cell $and $and$libresoc.v:42810$2172 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70036,10 +70072,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_CR_cr_c_o connect \B \rdpick_CR_cr_c_en_o - connect \Y $and$libresoc.v:42762$2172_Y + connect \Y $and$libresoc.v:42810$2172_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42766$2176 + cell $and $and$libresoc.v:42814$2176 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70047,10 +70083,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$81 [0] connect \B \fu_enable [2] - connect \Y $and$libresoc.v:42766$2176_Y + connect \Y $and$libresoc.v:42814$2176_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42767$2177 + cell $and $and$libresoc.v:42815$2177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70058,10 +70094,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$866 connect \B \rdflag_FAST_fast1_0 - connect \Y $and$libresoc.v:42767$2177_Y + connect \Y $and$libresoc.v:42815$2177_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42769$2179 + cell $and $and$libresoc.v:42817$2179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70069,10 +70105,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$868 connect \B \$870 - connect \Y $and$libresoc.v:42769$2179_Y + connect \Y $and$libresoc.v:42817$2179_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42770$2180 + cell $and $and$libresoc.v:42818$2180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70080,10 +70116,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast1_o [0] connect \B \rdpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42770$2180_Y + connect \Y $and$libresoc.v:42818$2180_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42772$2182 + cell $and $and$libresoc.v:42820$2182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70091,10 +70127,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$43 [2] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42772$2182_Y + connect \Y $and$libresoc.v:42820$2182_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42773$2183 + cell $and $and$libresoc.v:42821$2183 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70102,10 +70138,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$878 connect \B \rdflag_FAST_fast1_0 - connect \Y $and$libresoc.v:42773$2183_Y + connect \Y $and$libresoc.v:42821$2183_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42775$2185 + cell $and $and$libresoc.v:42823$2185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70113,10 +70149,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$880 connect \B \$882 - connect \Y $and$libresoc.v:42775$2185_Y + connect \Y $and$libresoc.v:42823$2185_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42776$2186 + cell $and $and$libresoc.v:42824$2186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70124,10 +70160,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast1_o [1] connect \B \rdpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42776$2186_Y + connect \Y $and$libresoc.v:42824$2186_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42778$2188 + cell $and $and$libresoc.v:42826$2188 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70135,10 +70171,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$49 [2] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42778$2188_Y + connect \Y $and$libresoc.v:42826$2188_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42779$2189 + cell $and $and$libresoc.v:42827$2189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70146,10 +70182,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$890 connect \B \rdflag_FAST_fast1_0 - connect \Y $and$libresoc.v:42779$2189_Y + connect \Y $and$libresoc.v:42827$2189_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42781$2191 + cell $and $and$libresoc.v:42829$2191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70157,10 +70193,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$892 connect \B \$894 - connect \Y $and$libresoc.v:42781$2191_Y + connect \Y $and$libresoc.v:42829$2191_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42782$2192 + cell $and $and$libresoc.v:42830$2192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70168,10 +70204,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast1_o [2] connect \B \rdpick_FAST_fast1_en_o - connect \Y $and$libresoc.v:42782$2192_Y + connect \Y $and$libresoc.v:42830$2192_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42787$2197 + cell $and $and$libresoc.v:42835$2197 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70179,10 +70215,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$81 [1] connect \B \fu_enable [2] - connect \Y $and$libresoc.v:42787$2197_Y + connect \Y $and$libresoc.v:42835$2197_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42788$2198 + cell $and $and$libresoc.v:42836$2198 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70190,10 +70226,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$908 connect \B \rdflag_FAST_fast2_0 - connect \Y $and$libresoc.v:42788$2198_Y + connect \Y $and$libresoc.v:42836$2198_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42790$2200 + cell $and $and$libresoc.v:42838$2200 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70201,10 +70237,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$910 connect \B \$912 - connect \Y $and$libresoc.v:42790$2200_Y + connect \Y $and$libresoc.v:42838$2200_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42791$2201 + cell $and $and$libresoc.v:42839$2201 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70212,10 +70248,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast2_o [0] connect \B \rdpick_FAST_fast2_en_o - connect \Y $and$libresoc.v:42791$2201_Y + connect \Y $and$libresoc.v:42839$2201_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42793$2203 + cell $and $and$libresoc.v:42841$2203 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70223,10 +70259,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$43 [3] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42793$2203_Y + connect \Y $and$libresoc.v:42841$2203_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42794$2204 + cell $and $and$libresoc.v:42842$2204 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70234,10 +70270,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$920 connect \B \rdflag_FAST_fast2_0 - connect \Y $and$libresoc.v:42794$2204_Y + connect \Y $and$libresoc.v:42842$2204_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42796$2206 + cell $and $and$libresoc.v:42844$2206 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70245,10 +70281,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$922 connect \B \$924 - connect \Y $and$libresoc.v:42796$2206_Y + connect \Y $and$libresoc.v:42844$2206_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42797$2207 + cell $and $and$libresoc.v:42845$2207 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70256,10 +70292,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_FAST_fast2_o [1] connect \B \rdpick_FAST_fast2_en_o - connect \Y $and$libresoc.v:42797$2207_Y + connect \Y $and$libresoc.v:42845$2207_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42801$2211 + cell $and $and$libresoc.v:42849$2211 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70267,10 +70303,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_rd__rel_o$49 [1] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42801$2211_Y + connect \Y $and$libresoc.v:42849$2211_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281" - cell $and $and$libresoc.v:42802$2212 + cell $and $and$libresoc.v:42850$2212 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70278,10 +70314,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$936 connect \B \rdflag_SPR_spr1_0 - connect \Y $and$libresoc.v:42802$2212_Y + connect \Y $and$libresoc.v:42850$2212_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $and $and$libresoc.v:42804$2214 + cell $and $and$libresoc.v:42852$2214 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70289,10 +70325,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$938 connect \B \$940 - connect \Y $and$libresoc.v:42804$2214_Y + connect \Y $and$libresoc.v:42852$2214_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:287" - cell $and $and$libresoc.v:42805$2215 + cell $and $and$libresoc.v:42853$2215 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70300,10 +70336,10 @@ module \core parameter \Y_WIDTH 1 connect \A \rdpick_SPR_spr1_o connect \B \rdpick_SPR_spr1_en_o - connect \Y $and$libresoc.v:42805$2215_Y + connect \Y $and$libresoc.v:42853$2215_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42808$2218 + cell $and $and$libresoc.v:42856$2218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70311,10 +70347,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok connect \B \fus_cu_busy_o - connect \Y $and$libresoc.v:42808$2218_Y + connect \Y $and$libresoc.v:42856$2218_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42809$2219 + cell $and $and$libresoc.v:42857$2219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70322,10 +70358,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o [0] connect \B \fu_enable [0] - connect \Y $and$libresoc.v:42809$2219_Y + connect \Y $and$libresoc.v:42857$2219_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42810$2220 + cell $and $and$libresoc.v:42858$2220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70333,10 +70369,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$93 [0] connect \B \fu_enable [1] - connect \Y $and$libresoc.v:42810$2220_Y + connect \Y $and$libresoc.v:42858$2220_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42811$2221 + cell $and $and$libresoc.v:42859$2221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70344,10 +70380,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$96 [0] connect \B \fu_enable [3] - connect \Y $and$libresoc.v:42811$2221_Y + connect \Y $and$libresoc.v:42859$2221_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42812$2222 + cell $and $and$libresoc.v:42860$2222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70355,10 +70391,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$99 [0] connect \B \fu_enable [4] - connect \Y $and$libresoc.v:42812$2222_Y + connect \Y $and$libresoc.v:42860$2222_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42813$2223 + cell $and $and$libresoc.v:42861$2223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70366,10 +70402,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$102 [0] connect \B \fu_enable [5] - connect \Y $and$libresoc.v:42813$2223_Y + connect \Y $and$libresoc.v:42861$2223_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42814$2224 + cell $and $and$libresoc.v:42862$2224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70377,10 +70413,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$105 [0] connect \B \fu_enable [6] - connect \Y $and$libresoc.v:42814$2224_Y + connect \Y $and$libresoc.v:42862$2224_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42815$2225 + cell $and $and$libresoc.v:42863$2225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70388,10 +70424,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$108 [0] connect \B \fu_enable [7] - connect \Y $and$libresoc.v:42815$2225_Y + connect \Y $and$libresoc.v:42863$2225_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42816$2226 + cell $and $and$libresoc.v:42864$2226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70399,10 +70435,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$111 [0] connect \B \fu_enable [8] - connect \Y $and$libresoc.v:42816$2226_Y + connect \Y $and$libresoc.v:42864$2226_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42817$2227 + cell $and $and$libresoc.v:42865$2227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70410,10 +70446,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$113 [0] connect \B \fu_enable [9] - connect \Y $and$libresoc.v:42817$2227_Y + connect \Y $and$libresoc.v:42865$2227_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $and$libresoc.v:42818$2228 + cell $and $and$libresoc.v:42866$2228 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70421,10 +70457,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_cu_wr__rel_o$113 [1] connect \B \fu_enable [9] - connect \Y $and$libresoc.v:42818$2228_Y + connect \Y $and$libresoc.v:42866$2228_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42819$2229 + cell $and $and$libresoc.v:42867$2229 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70432,10 +70468,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [0] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42819$2229_Y + connect \Y $and$libresoc.v:42867$2229_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42821$2231 + cell $and $and$libresoc.v:42869$2231 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70443,10 +70479,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick connect \B \$974 - connect \Y $and$libresoc.v:42821$2231_Y + connect \Y $and$libresoc.v:42869$2231_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:419" - cell $and $and$libresoc.v:42822$2232 + cell $and $and$libresoc.v:42870$2232 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70454,10 +70490,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42822$2232_Y + connect \Y $and$libresoc.v:42870$2232_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:403" - cell $and $and$libresoc.v:42824$2234 + cell $and $and$libresoc.v:42872$2234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70465,10 +70501,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_o_ok$92 connect \B \fus_cu_busy_o$14 - connect \Y $and$libresoc.v:42824$2234_Y + connect \Y $and$libresoc.v:42872$2234_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:411" - cell $and $and$libresoc.v:42825$2235 + cell $and $and$libresoc.v:42873$2235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70476,10 +70512,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wrpick_INT_o_o [1] connect \B \wrpick_INT_o_en_o - connect \Y $and$libresoc.v:42825$2235_Y + connect \Y $and$libresoc.v:42873$2235_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:42827$2237 + cell $and $and$libresoc.v:42875$2237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -70487,10 +70523,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wr_pick$988 connect \B \$993 - connect \Y $and$libresoc.v:42827$2237_Y + connect \Y $and$libresoc.v:42875$2237_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:42451$1859 + cell $eq $eq$libresoc.v:42499$1859 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70498,10 +70534,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$231 connect \B 1'1 - connect \Y $eq$libresoc.v:42451$1859_Y + connect \Y $eq$libresoc.v:42499$1859_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - cell $eq $eq$libresoc.v:42455$1863 + cell $eq $eq$libresoc.v:42503$1863 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -70509,10 +70545,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_input_carry connect \B 2'10 - connect \Y $eq$libresoc.v:42455$1863_Y + connect \Y $eq$libresoc.v:42503$1863_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $eq $eq$libresoc.v:42457$1865 + cell $eq $eq$libresoc.v:42505$1865 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70520,10 +70556,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$243 connect \B 3'100 - connect \Y $eq$libresoc.v:42457$1865_Y + connect \Y $eq$libresoc.v:42505$1865_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:42465$1873 + cell $eq $eq$libresoc.v:42513$1873 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70531,10 +70567,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$259 connect \B 1'1 - connect \Y $eq$libresoc.v:42465$1873_Y + connect \Y $eq$libresoc.v:42513$1873_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:42472$1880 + cell $eq $eq$libresoc.v:42520$1880 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70542,10 +70578,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$273 connect \B 1'1 - connect \Y $eq$libresoc.v:42472$1880_Y + connect \Y $eq$libresoc.v:42520$1880_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $eq $eq$libresoc.v:42478$1886 + cell $eq $eq$libresoc.v:42526$1886 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70553,10 +70589,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$285 connect \B 2'10 - connect \Y $eq$libresoc.v:42478$1886_Y + connect \Y $eq$libresoc.v:42526$1886_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - cell $eq $eq$libresoc.v:42480$1888 + cell $eq $eq$libresoc.v:42528$1888 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -70564,10 +70600,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_input_carry connect \B 2'10 - connect \Y $eq$libresoc.v:42480$1888_Y + connect \Y $eq$libresoc.v:42528$1888_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $eq $eq$libresoc.v:42482$1890 + cell $eq $eq$libresoc.v:42530$1890 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70575,10 +70611,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$293 connect \B 3'100 - connect \Y $eq$libresoc.v:42482$1890_Y + connect \Y $eq$libresoc.v:42530$1890_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:42487$1895 + cell $eq $eq$libresoc.v:42535$1895 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70586,10 +70622,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$303 connect \B 1'1 - connect \Y $eq$libresoc.v:42487$1895_Y + connect \Y $eq$libresoc.v:42535$1895_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:42494$1902 + cell $eq $eq$libresoc.v:42542$1902 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70597,10 +70633,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$317 connect \B 1'1 - connect \Y $eq$libresoc.v:42494$1902_Y + connect \Y $eq$libresoc.v:42542$1902_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:42501$1909 + cell $eq $eq$libresoc.v:42549$1909 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70608,10 +70644,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$331 connect \B 1'1 - connect \Y $eq$libresoc.v:42501$1909_Y + connect \Y $eq$libresoc.v:42549$1909_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - cell $eq $eq$libresoc.v:42505$1913 + cell $eq $eq$libresoc.v:42553$1913 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -70619,10 +70655,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_input_carry connect \B 2'10 - connect \Y $eq$libresoc.v:42505$1913_Y + connect \Y $eq$libresoc.v:42553$1913_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $eq $eq$libresoc.v:42507$1915 + cell $eq $eq$libresoc.v:42555$1915 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70630,10 +70666,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$343 connect \B 3'100 - connect \Y $eq$libresoc.v:42507$1915_Y + connect \Y $eq$libresoc.v:42555$1915_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $eq$libresoc.v:42646$2054 + cell $eq $eq$libresoc.v:42694$2054 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70641,10 +70677,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$623 connect \B 1'1 - connect \Y $eq$libresoc.v:42646$2054_Y + connect \Y $eq$libresoc.v:42694$2054_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - cell $eq $eq$libresoc.v:42692$2101 + cell $eq $eq$libresoc.v:42740$2101 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -70652,10 +70688,10 @@ module \core parameter \Y_WIDTH 1 connect \A \core_core_input_carry connect \B 2'10 - connect \Y $eq$libresoc.v:42692$2101_Y + connect \Y $eq$libresoc.v:42740$2101_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $eq $eq$libresoc.v:42694$2103 + cell $eq $eq$libresoc.v:42742$2103 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70663,10 +70699,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$719 connect \B 3'100 - connect \Y $eq$libresoc.v:42694$2103_Y + connect \Y $eq$libresoc.v:42742$2103_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $eq $eq$libresoc.v:42719$2129 + cell $eq $eq$libresoc.v:42767$2129 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -70674,66 +70710,66 @@ module \core parameter \Y_WIDTH 1 connect \A \$769 connect \B 2'10 - connect \Y $eq$libresoc.v:42719$2129_Y + connect \Y $eq$libresoc.v:42767$2129_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $extend$libresoc.v:42276$1679 + cell $pos $extend$libresoc.v:42324$1679 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 3 connect \A \$1447 - connect \Y $extend$libresoc.v:42276$1679_Y + connect \Y $extend$libresoc.v:42324$1679_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $extend$libresoc.v:42342$1746 + cell $pos $extend$libresoc.v:42390$1746 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 2 connect \A \$1611 - connect \Y $extend$libresoc.v:42342$1746_Y + connect \Y $extend$libresoc.v:42390$1746_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $extend$libresoc.v:42346$1751 + cell $pos $extend$libresoc.v:42394$1751 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 3 connect \A \$1619 - connect \Y $extend$libresoc.v:42346$1751_Y + connect \Y $extend$libresoc.v:42394$1751_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $pos $extend$libresoc.v:42410$1816 + cell $pos $extend$libresoc.v:42458$1816 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 3 connect \A \$1778 - connect \Y $extend$libresoc.v:42410$1816_Y + connect \Y $extend$libresoc.v:42458$1816_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" - cell $pos $extend$libresoc.v:42418$1825 + cell $pos $extend$libresoc.v:42466$1825 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 3 connect \A \addr_en$1796 - connect \Y $extend$libresoc.v:42418$1825_Y + connect \Y $extend$libresoc.v:42466$1825_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $extend$libresoc.v:42691$2099 + cell $pos $extend$libresoc.v:42739$2099 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 3 connect \A \$714 - connect \Y $extend$libresoc.v:42691$2099_Y + connect \Y $extend$libresoc.v:42739$2099_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $extend$libresoc.v:42716$2125 + cell $pos $extend$libresoc.v:42764$2125 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 3 connect \A \$764 - connect \Y $extend$libresoc.v:42716$2125_Y + connect \Y $extend$libresoc.v:42764$2125_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - cell $ne $ne$libresoc.v:42446$1854 + cell $ne $ne$libresoc.v:42494$1854 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -70741,10 +70777,10 @@ module \core parameter \Y_WIDTH 1 connect \A \counter connect \B 1'0 - connect \Y $ne$libresoc.v:42446$1854_Y + connect \Y $ne$libresoc.v:42494$1854_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:189" - cell $ne $ne$libresoc.v:42448$1856 + cell $ne $ne$libresoc.v:42496$1856 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -70752,706 +70788,706 @@ module \core parameter \Y_WIDTH 1 connect \A \counter connect \B 1'0 - connect \Y $ne$libresoc.v:42448$1856_Y + connect \Y $ne$libresoc.v:42496$1856_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42107$1510 + cell $not $not$libresoc.v:42155$1510 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1010 - connect \Y $not$libresoc.v:42107$1510_Y + connect \Y $not$libresoc.v:42155$1510_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42113$1516 + cell $not $not$libresoc.v:42161$1516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1031 - connect \Y $not$libresoc.v:42113$1516_Y + connect \Y $not$libresoc.v:42161$1516_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42119$1522 + cell $not $not$libresoc.v:42167$1522 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1049 - connect \Y $not$libresoc.v:42119$1522_Y + connect \Y $not$libresoc.v:42167$1522_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42125$1528 + cell $not $not$libresoc.v:42173$1528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1071 - connect \Y $not$libresoc.v:42125$1528_Y + connect \Y $not$libresoc.v:42173$1528_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42131$1534 + cell $not $not$libresoc.v:42179$1534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1091 - connect \Y $not$libresoc.v:42131$1534_Y + connect \Y $not$libresoc.v:42179$1534_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42137$1540 + cell $not $not$libresoc.v:42185$1540 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1111 - connect \Y $not$libresoc.v:42137$1540_Y + connect \Y $not$libresoc.v:42185$1540_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42143$1546 + cell $not $not$libresoc.v:42191$1546 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1130 - connect \Y $not$libresoc.v:42143$1546_Y + connect \Y $not$libresoc.v:42191$1546_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42149$1552 + cell $not $not$libresoc.v:42197$1552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1148 - connect \Y $not$libresoc.v:42149$1552_Y + connect \Y $not$libresoc.v:42197$1552_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42183$1586 + cell $not $not$libresoc.v:42231$1586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1222 - connect \Y $not$libresoc.v:42183$1586_Y + connect \Y $not$libresoc.v:42231$1586_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42195$1598 + cell $not $not$libresoc.v:42243$1598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1250 - connect \Y $not$libresoc.v:42195$1598_Y + connect \Y $not$libresoc.v:42243$1598_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42203$1606 + cell $not $not$libresoc.v:42251$1606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1270 - connect \Y $not$libresoc.v:42203$1606_Y + connect \Y $not$libresoc.v:42251$1606_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42211$1614 + cell $not $not$libresoc.v:42259$1614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1290 - connect \Y $not$libresoc.v:42211$1614_Y + connect \Y $not$libresoc.v:42259$1614_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42219$1622 + cell $not $not$libresoc.v:42267$1622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1310 - connect \Y $not$libresoc.v:42219$1622_Y + connect \Y $not$libresoc.v:42267$1622_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42227$1630 + cell $not $not$libresoc.v:42275$1630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1330 - connect \Y $not$libresoc.v:42227$1630_Y + connect \Y $not$libresoc.v:42275$1630_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42235$1638 + cell $not $not$libresoc.v:42283$1638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1350 - connect \Y $not$libresoc.v:42235$1638_Y + connect \Y $not$libresoc.v:42283$1638_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42256$1659 + cell $not $not$libresoc.v:42304$1659 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1397 - connect \Y $not$libresoc.v:42256$1659_Y + connect \Y $not$libresoc.v:42304$1659_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42262$1665 + cell $not $not$libresoc.v:42310$1665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1413 - connect \Y $not$libresoc.v:42262$1665_Y + connect \Y $not$libresoc.v:42310$1665_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42268$1671 + cell $not $not$libresoc.v:42316$1671 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1429 - connect \Y $not$libresoc.v:42268$1671_Y + connect \Y $not$libresoc.v:42316$1671_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42283$1687 + cell $not $not$libresoc.v:42331$1687 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1463 - connect \Y $not$libresoc.v:42283$1687_Y + connect \Y $not$libresoc.v:42331$1687_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42289$1693 + cell $not $not$libresoc.v:42337$1693 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1479 - connect \Y $not$libresoc.v:42289$1693_Y + connect \Y $not$libresoc.v:42337$1693_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42295$1699 + cell $not $not$libresoc.v:42343$1699 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1495 - connect \Y $not$libresoc.v:42295$1699_Y + connect \Y $not$libresoc.v:42343$1699_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42301$1705 + cell $not $not$libresoc.v:42349$1705 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1511 - connect \Y $not$libresoc.v:42301$1705_Y + connect \Y $not$libresoc.v:42349$1705_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42317$1721 + cell $not $not$libresoc.v:42365$1721 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1547 - connect \Y $not$libresoc.v:42317$1721_Y + connect \Y $not$libresoc.v:42365$1721_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42323$1727 + cell $not $not$libresoc.v:42371$1727 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$1563 - connect \Y $not$libresoc.v:42323$1727_Y + connect \Y $not$libresoc.v:42371$1727_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42329$1733 + cell $not $not$libresoc.v:42377$1733 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A 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$not$libresoc.v:42777$2139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_CR_full_cr_cr0_0 - connect \Y $not$libresoc.v:42729$2139_Y + connect \Y $not$libresoc.v:42777$2139_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $not $not$libresoc.v:42735$2145 + cell $not $not$libresoc.v:42783$2145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_CR_cr_a_cr0_0 - connect \Y $not$libresoc.v:42735$2145_Y + connect \Y $not$libresoc.v:42783$2145_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $not $not$libresoc.v:42743$2153 + cell $not $not$libresoc.v:42791$2153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_CR_cr_a_branch0_1 - connect \Y $not$libresoc.v:42743$2153_Y + connect \Y $not$libresoc.v:42791$2153_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $not $not$libresoc.v:42752$2162 + cell $not $not$libresoc.v:42800$2162 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_CR_cr_b_cr0_0 - connect \Y $not$libresoc.v:42752$2162_Y + connect \Y $not$libresoc.v:42800$2162_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $not $not$libresoc.v:42760$2170 + cell $not $not$libresoc.v:42808$2170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_CR_cr_c_cr0_0 - connect \Y $not$libresoc.v:42760$2170_Y + connect \Y $not$libresoc.v:42808$2170_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $not $not$libresoc.v:42768$2178 + cell $not $not$libresoc.v:42816$2178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_FAST_fast1_branch0_0 - connect \Y $not$libresoc.v:42768$2178_Y + connect \Y $not$libresoc.v:42816$2178_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $not $not$libresoc.v:42774$2184 + cell $not $not$libresoc.v:42822$2184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_FAST_fast1_trap0_1 - connect \Y $not$libresoc.v:42774$2184_Y + connect \Y $not$libresoc.v:42822$2184_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $not $not$libresoc.v:42780$2190 + cell $not $not$libresoc.v:42828$2190 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_FAST_fast1_spr0_2 - connect \Y $not$libresoc.v:42780$2190_Y + connect \Y $not$libresoc.v:42828$2190_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $not $not$libresoc.v:42789$2199 + cell $not $not$libresoc.v:42837$2199 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_FAST_fast2_branch0_0 - connect \Y $not$libresoc.v:42789$2199_Y + connect \Y $not$libresoc.v:42837$2199_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $not $not$libresoc.v:42795$2205 + cell $not $not$libresoc.v:42843$2205 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_FAST_fast2_trap0_1 - connect \Y $not$libresoc.v:42795$2205_Y + connect \Y $not$libresoc.v:42843$2205_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:282" - cell $not $not$libresoc.v:42803$2213 + cell $not $not$libresoc.v:42851$2213 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dp_SPR_spr1_spr0_0 - connect \Y $not$libresoc.v:42803$2213_Y + connect \Y $not$libresoc.v:42851$2213_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42820$2230 + cell $not $not$libresoc.v:42868$2230 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly - connect \Y $not$libresoc.v:42820$2230_Y + connect \Y $not$libresoc.v:42868$2230_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:42826$2236 + cell $not $not$libresoc.v:42874$2236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_pick_dly$991 - connect \Y $not$libresoc.v:42826$2236_Y + connect \Y $not$libresoc.v:42874$2236_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42153$1556 + cell $or $or$libresoc.v:42201$1556 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -71459,10 +71495,10 @@ module \core parameter \Y_WIDTH 64 connect \A \fus_dest1_o connect \B \fus_dest1_o$115 - connect \Y $or$libresoc.v:42153$1556_Y + connect \Y $or$libresoc.v:42201$1556_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42154$1557 + cell $or $or$libresoc.v:42202$1557 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -71470,10 +71506,10 @@ module \core parameter \Y_WIDTH 64 connect \A \fus_dest1_o$117 connect \B \fus_dest1_o$118 - connect \Y $or$libresoc.v:42154$1557_Y + connect \Y $or$libresoc.v:42202$1557_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42155$1558 + cell $or $or$libresoc.v:42203$1558 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -71481,10 +71517,10 @@ module \core parameter \Y_WIDTH 64 connect \A \fus_dest1_o$116 connect \B \$1162 - connect \Y $or$libresoc.v:42155$1558_Y + connect \Y $or$libresoc.v:42203$1558_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42156$1559 + cell $or $or$libresoc.v:42204$1559 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -71492,10 +71528,10 @@ module \core parameter \Y_WIDTH 64 connect \A \$1160 connect \B \$1164 - connect \Y $or$libresoc.v:42156$1559_Y + connect \Y $or$libresoc.v:42204$1559_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42157$1560 + cell $or $or$libresoc.v:42205$1560 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -71503,10 +71539,10 @@ module \core parameter \Y_WIDTH 64 connect \A \fus_dest1_o$119 connect \B \fus_dest1_o$120 - connect \Y $or$libresoc.v:42157$1560_Y + connect \Y $or$libresoc.v:42205$1560_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42158$1561 + cell $or $or$libresoc.v:42206$1561 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \B_SIGNED 0 @@ -71514,10 +71550,10 @@ module \core parameter \Y_WIDTH 65 connect \A { \o_ok \fus_o } connect \B { \ea_ok \fus_ea } - connect \Y $or$libresoc.v:42158$1561_Y + connect \Y $or$libresoc.v:42206$1561_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42159$1562 + cell $or $or$libresoc.v:42207$1562 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -71525,10 +71561,10 @@ module \core parameter \Y_WIDTH 65 connect \A \fus_dest1_o$121 connect \B \$1170 - connect \Y $or$libresoc.v:42159$1562_Y + connect \Y $or$libresoc.v:42207$1562_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42160$1563 + cell $or $or$libresoc.v:42208$1563 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -71536,10 +71572,10 @@ module \core parameter \Y_WIDTH 65 connect \A \$1168 connect \B \$1172 - connect \Y $or$libresoc.v:42160$1563_Y + connect \Y $or$libresoc.v:42208$1563_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42161$1564 + cell $or $or$libresoc.v:42209$1564 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -71547,10 +71583,10 @@ module \core parameter \Y_WIDTH 65 connect \A \$1166 connect \B \$1174 - connect \Y $or$libresoc.v:42161$1564_Y + connect \Y $or$libresoc.v:42209$1564_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42162$1565 + cell $or $or$libresoc.v:42210$1565 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -71558,10 +71594,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en connect \B \addr_en$1002 - connect \Y $or$libresoc.v:42162$1565_Y + connect \Y $or$libresoc.v:42210$1565_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42163$1566 + cell $or $or$libresoc.v:42211$1566 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -71569,10 +71605,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en$1041 connect \B \addr_en$1063 - connect \Y $or$libresoc.v:42163$1566_Y + connect \Y $or$libresoc.v:42211$1566_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42164$1567 + cell $or $or$libresoc.v:42212$1567 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -71580,10 +71616,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en$1023 connect \B \$1181 - connect \Y $or$libresoc.v:42164$1567_Y + connect \Y $or$libresoc.v:42212$1567_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42165$1568 + cell $or $or$libresoc.v:42213$1568 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -71591,10 +71627,10 @@ module \core parameter \Y_WIDTH 7 connect \A \$1179 connect \B \$1183 - connect \Y $or$libresoc.v:42165$1568_Y + connect \Y $or$libresoc.v:42213$1568_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42166$1569 + cell $or $or$libresoc.v:42214$1569 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -71602,10 +71638,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en$1083 connect \B \addr_en$1103 - connect \Y $or$libresoc.v:42166$1569_Y + connect \Y $or$libresoc.v:42214$1569_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42167$1570 + cell $or $or$libresoc.v:42215$1570 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -71613,10 +71649,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en$1140 connect \B \addr_en$1156 - connect \Y $or$libresoc.v:42167$1570_Y + connect \Y $or$libresoc.v:42215$1570_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42168$1571 + cell $or $or$libresoc.v:42216$1571 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -71624,10 +71660,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en$1122 connect \B \$1189 - connect \Y $or$libresoc.v:42168$1571_Y + connect \Y $or$libresoc.v:42216$1571_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42169$1572 + cell $or $or$libresoc.v:42217$1572 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -71635,10 +71671,10 @@ module \core parameter \Y_WIDTH 7 connect \A \$1187 connect \B \$1191 - connect \Y $or$libresoc.v:42169$1572_Y + connect \Y $or$libresoc.v:42217$1572_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42170$1573 + cell $or $or$libresoc.v:42218$1573 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -71646,10 +71682,10 @@ module \core parameter \Y_WIDTH 7 connect \A \$1185 connect \B \$1193 - connect \Y $or$libresoc.v:42170$1573_Y + connect \Y $or$libresoc.v:42218$1573_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42171$1574 + cell $or $or$libresoc.v:42219$1574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71657,10 +71693,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wp connect \B \wp$999 - connect \Y $or$libresoc.v:42171$1574_Y + connect \Y $or$libresoc.v:42219$1574_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42172$1575 + cell $or $or$libresoc.v:42220$1575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71668,10 +71704,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wp$1038 connect \B \wp$1060 - connect \Y $or$libresoc.v:42172$1575_Y + connect \Y $or$libresoc.v:42220$1575_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42173$1576 + cell $or $or$libresoc.v:42221$1576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71679,10 +71715,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wp$1020 connect \B \$1199 - connect \Y $or$libresoc.v:42173$1576_Y + connect \Y $or$libresoc.v:42221$1576_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42174$1577 + cell $or $or$libresoc.v:42222$1577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71690,10 +71726,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$1197 connect \B \$1201 - connect \Y $or$libresoc.v:42174$1577_Y + connect \Y $or$libresoc.v:42222$1577_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42175$1578 + cell $or $or$libresoc.v:42223$1578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71701,10 +71737,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wp$1080 connect \B \wp$1100 - connect \Y $or$libresoc.v:42175$1578_Y + connect \Y $or$libresoc.v:42223$1578_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42176$1579 + cell $or $or$libresoc.v:42224$1579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71712,10 +71748,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wp$1137 connect \B \wp$1153 - connect \Y $or$libresoc.v:42176$1579_Y + connect \Y $or$libresoc.v:42224$1579_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42177$1580 + cell $or $or$libresoc.v:42225$1580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71723,10 +71759,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wp$1119 connect \B \$1207 - connect \Y $or$libresoc.v:42177$1580_Y + connect \Y $or$libresoc.v:42225$1580_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42178$1581 + cell $or $or$libresoc.v:42226$1581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71734,10 +71770,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$1205 connect \B \$1209 - connect \Y $or$libresoc.v:42178$1581_Y + connect \Y $or$libresoc.v:42226$1581_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42179$1582 + cell $or $or$libresoc.v:42227$1582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71745,10 +71781,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$1203 connect \B \$1211 - connect \Y $or$libresoc.v:42179$1582_Y + connect \Y $or$libresoc.v:42227$1582_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42241$1644 + cell $or $or$libresoc.v:42289$1644 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -71756,10 +71792,10 @@ module \core parameter \Y_WIDTH 4 connect \A \fus_dest3_o connect \B \fus_dest2_o$128 - connect \Y $or$libresoc.v:42241$1644_Y + connect \Y $or$libresoc.v:42289$1644_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42242$1645 + cell $or $or$libresoc.v:42290$1645 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -71767,10 +71803,10 @@ module \core parameter \Y_WIDTH 4 connect \A \fus_dest2_o$127 connect \B \$1365 - connect \Y $or$libresoc.v:42242$1645_Y + connect \Y $or$libresoc.v:42290$1645_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42243$1646 + cell $or $or$libresoc.v:42291$1646 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -71778,10 +71814,10 @@ module \core parameter \Y_WIDTH 4 connect \A \fus_dest2_o$130 connect \B \fus_dest2_o$131 - connect \Y $or$libresoc.v:42243$1646_Y + connect \Y $or$libresoc.v:42291$1646_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42244$1647 + cell $or $or$libresoc.v:42292$1647 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -71789,10 +71825,10 @@ module \core parameter \Y_WIDTH 4 connect \A \fus_dest2_o$129 connect \B \$1369 - connect \Y $or$libresoc.v:42244$1647_Y + connect \Y $or$libresoc.v:42292$1647_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42245$1648 + cell $or $or$libresoc.v:42293$1648 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -71800,10 +71836,10 @@ module \core parameter \Y_WIDTH 4 connect \A \$1367 connect \B \$1371 - connect \Y $or$libresoc.v:42245$1648_Y + connect \Y $or$libresoc.v:42293$1648_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42246$1649 + cell $or $or$libresoc.v:42294$1649 parameter \A_SIGNED 0 parameter \A_WIDTH 256 parameter \B_SIGNED 0 @@ -71811,10 +71847,10 @@ module \core parameter \Y_WIDTH 256 connect \A \addr_en$1278 connect \B \addr_en$1298 - connect \Y $or$libresoc.v:42246$1649_Y + connect \Y $or$libresoc.v:42294$1649_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42247$1650 + cell $or $or$libresoc.v:42295$1650 parameter \A_SIGNED 0 parameter \A_WIDTH 256 parameter \B_SIGNED 0 @@ -71822,10 +71858,10 @@ module \core parameter \Y_WIDTH 256 connect \A \addr_en$1258 connect \B \$1376 - connect \Y $or$libresoc.v:42247$1650_Y + connect \Y $or$libresoc.v:42295$1650_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42248$1651 + cell $or $or$libresoc.v:42296$1651 parameter \A_SIGNED 0 parameter \A_WIDTH 256 parameter \B_SIGNED 0 @@ -71833,10 +71869,10 @@ module \core parameter \Y_WIDTH 256 connect \A \addr_en$1338 connect \B \addr_en$1358 - connect \Y $or$libresoc.v:42248$1651_Y + connect \Y $or$libresoc.v:42296$1651_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42249$1652 + cell $or $or$libresoc.v:42297$1652 parameter \A_SIGNED 0 parameter \A_WIDTH 256 parameter \B_SIGNED 0 @@ -71844,10 +71880,10 @@ module \core parameter \Y_WIDTH 256 connect \A \addr_en$1318 connect \B \$1380 - connect \Y $or$libresoc.v:42249$1652_Y + connect \Y $or$libresoc.v:42297$1652_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42250$1653 + cell $or $or$libresoc.v:42298$1653 parameter \A_SIGNED 0 parameter \A_WIDTH 256 parameter \B_SIGNED 0 @@ -71855,10 +71891,10 @@ module \core parameter \Y_WIDTH 256 connect \A \$1378 connect \B \$1382 - connect \Y $or$libresoc.v:42250$1653_Y + connect \Y $or$libresoc.v:42298$1653_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42272$1675 + cell $or $or$libresoc.v:42320$1675 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -71866,10 +71902,10 @@ module \core parameter \Y_WIDTH 2 connect \A \fus_dest6_o connect \B \fus_dest3_o$135 - connect \Y $or$libresoc.v:42272$1675_Y + connect \Y $or$libresoc.v:42320$1675_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42273$1676 + cell $or $or$libresoc.v:42321$1676 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -71877,10 +71913,10 @@ module \core parameter \Y_WIDTH 2 connect \A \fus_dest3_o$134 connect \B \$1440 - connect \Y $or$libresoc.v:42273$1676_Y + connect \Y $or$libresoc.v:42321$1676_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42274$1677 + cell $or $or$libresoc.v:42322$1677 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -71888,10 +71924,10 @@ module \core parameter \Y_WIDTH 2 connect \A \addr_en$1421 connect \B \addr_en$1437 - connect \Y $or$libresoc.v:42274$1677_Y + connect \Y $or$libresoc.v:42322$1677_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42275$1678 + cell $or $or$libresoc.v:42323$1678 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -71899,10 +71935,10 @@ module \core parameter \Y_WIDTH 2 connect \A \addr_en$1405 connect \B \$1445 - connect \Y $or$libresoc.v:42275$1678_Y + connect \Y $or$libresoc.v:42323$1678_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42305$1709 + cell $or $or$libresoc.v:42353$1709 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -71910,10 +71946,10 @@ module \core parameter \Y_WIDTH 2 connect \A \fus_dest4_o connect \B \fus_dest5_o - connect \Y $or$libresoc.v:42305$1709_Y + connect \Y $or$libresoc.v:42353$1709_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42306$1710 + cell $or $or$libresoc.v:42354$1710 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -71921,10 +71957,10 @@ module \core parameter \Y_WIDTH 2 connect \A \fus_dest3_o$139 connect \B \fus_dest3_o$140 - connect \Y $or$libresoc.v:42306$1710_Y + connect \Y $or$libresoc.v:42354$1710_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42307$1711 + cell $or $or$libresoc.v:42355$1711 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -71932,10 +71968,10 @@ module \core parameter \Y_WIDTH 2 connect \A \$1522 connect \B \$1524 - connect \Y $or$libresoc.v:42307$1711_Y + connect \Y $or$libresoc.v:42355$1711_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42308$1712 + cell $or $or$libresoc.v:42356$1712 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -71943,10 +71979,10 @@ module \core parameter \Y_WIDTH 3 connect \A \addr_en$1471 connect \B \addr_en$1487 - connect \Y $or$libresoc.v:42308$1712_Y + connect \Y $or$libresoc.v:42356$1712_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42309$1713 + cell $or $or$libresoc.v:42357$1713 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -71954,10 +71990,10 @@ module \core parameter \Y_WIDTH 3 connect \A \addr_en$1503 connect \B \addr_en$1519 - connect \Y $or$libresoc.v:42309$1713_Y + connect \Y $or$libresoc.v:42357$1713_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42310$1714 + cell $or $or$libresoc.v:42358$1714 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -71965,10 +72001,10 @@ module \core parameter \Y_WIDTH 3 connect \A \$1528 connect \B \$1530 - connect \Y $or$libresoc.v:42310$1714_Y + connect \Y $or$libresoc.v:42358$1714_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42339$1743 + cell $or $or$libresoc.v:42387$1743 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71976,10 +72012,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_dest5_o$144 connect \B \fus_dest4_o$145 - connect \Y $or$libresoc.v:42339$1743_Y + connect \Y $or$libresoc.v:42387$1743_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42340$1744 + cell $or $or$libresoc.v:42388$1744 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71987,10 +72023,10 @@ module \core parameter \Y_WIDTH 1 connect \A \fus_dest4_o$146 connect \B \fus_dest4_o$147 - connect \Y $or$libresoc.v:42340$1744_Y + connect \Y $or$libresoc.v:42388$1744_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42341$1745 + cell $or $or$libresoc.v:42389$1745 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -71998,10 +72034,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$1607 connect \B \$1609 - connect \Y $or$libresoc.v:42341$1745_Y + connect \Y $or$libresoc.v:42389$1745_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42343$1748 + cell $or $or$libresoc.v:42391$1748 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72009,10 +72045,10 @@ module \core parameter \Y_WIDTH 1 connect \A \addr_en$1555 connect \B \addr_en$1571 - connect \Y $or$libresoc.v:42343$1748_Y + connect \Y $or$libresoc.v:42391$1748_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42344$1749 + cell $or $or$libresoc.v:42392$1749 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72020,10 +72056,10 @@ module \core parameter \Y_WIDTH 1 connect \A \addr_en$1587 connect \B \addr_en$1603 - connect \Y $or$libresoc.v:42344$1749_Y + connect \Y $or$libresoc.v:42392$1749_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42345$1750 + cell $or $or$libresoc.v:42393$1750 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72031,10 +72067,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$1615 connect \B \$1617 - connect \Y $or$libresoc.v:42345$1750_Y + connect \Y $or$libresoc.v:42393$1750_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42382$1788 + cell $or $or$libresoc.v:42430$1788 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -72042,10 +72078,10 @@ module \core parameter \Y_WIDTH 64 connect \A \fus_dest1_o$153 connect \B \fus_dest2_o$154 - connect \Y $or$libresoc.v:42382$1788_Y + connect \Y $or$libresoc.v:42430$1788_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42383$1789 + cell $or $or$libresoc.v:42431$1789 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -72053,10 +72089,10 @@ module \core parameter \Y_WIDTH 64 connect \A \fus_dest2_o$156 connect \B \fus_dest3_o$157 - connect \Y $or$libresoc.v:42383$1789_Y + connect \Y $or$libresoc.v:42431$1789_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42384$1790 + cell $or $or$libresoc.v:42432$1790 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -72064,10 +72100,10 @@ module \core parameter \Y_WIDTH 64 connect \A \fus_dest3_o$155 connect \B \$1717 - connect \Y $or$libresoc.v:42384$1790_Y + connect \Y $or$libresoc.v:42432$1790_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42385$1791 + cell $or $or$libresoc.v:42433$1791 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -72075,10 +72111,10 @@ module \core parameter \Y_WIDTH 64 connect \A \$1715 connect \B \$1719 - connect \Y $or$libresoc.v:42385$1791_Y + connect \Y $or$libresoc.v:42433$1791_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42386$1792 + cell $or $or$libresoc.v:42434$1792 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72086,10 +72122,10 @@ module \core parameter \Y_WIDTH 3 connect \A \addr_en$1648 connect \B \addr_en$1664 - connect \Y $or$libresoc.v:42386$1792_Y + connect \Y $or$libresoc.v:42434$1792_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42387$1793 + cell $or $or$libresoc.v:42435$1793 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72097,10 +72133,10 @@ module \core parameter \Y_WIDTH 3 connect \A \addr_en$1696 connect \B \addr_en$1712 - connect \Y $or$libresoc.v:42387$1793_Y + connect \Y $or$libresoc.v:42435$1793_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42388$1794 + cell $or $or$libresoc.v:42436$1794 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72108,10 +72144,10 @@ module \core parameter \Y_WIDTH 3 connect \A \addr_en$1680 connect \B \$1725 - connect \Y $or$libresoc.v:42388$1794_Y + connect \Y $or$libresoc.v:42436$1794_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42389$1795 + cell $or $or$libresoc.v:42437$1795 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72119,10 +72155,10 @@ module \core parameter \Y_WIDTH 3 connect \A \$1723 connect \B \$1727 - connect \Y $or$libresoc.v:42389$1795_Y + connect \Y $or$libresoc.v:42437$1795_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42390$1796 + cell $or $or$libresoc.v:42438$1796 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72130,10 +72166,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wp$1645 connect \B \wp$1661 - connect \Y $or$libresoc.v:42390$1796_Y + connect \Y $or$libresoc.v:42438$1796_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42391$1797 + cell $or $or$libresoc.v:42439$1797 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72141,10 +72177,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wp$1693 connect \B \wp$1709 - connect \Y $or$libresoc.v:42391$1797_Y + connect \Y $or$libresoc.v:42439$1797_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42392$1798 + cell $or $or$libresoc.v:42440$1798 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72152,10 +72188,10 @@ module \core parameter \Y_WIDTH 1 connect \A \wp$1677 connect \B \$1733 - connect \Y $or$libresoc.v:42392$1798_Y + connect \Y $or$libresoc.v:42440$1798_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42393$1799 + cell $or $or$libresoc.v:42441$1799 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72163,10 +72199,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$1731 connect \B \$1735 - connect \Y $or$libresoc.v:42393$1799_Y + connect \Y $or$libresoc.v:42441$1799_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42408$1814 + cell $or $or$libresoc.v:42456$1814 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -72174,10 +72210,10 @@ module \core parameter \Y_WIDTH 64 connect \A \fus_dest3_o$159 connect \B \fus_dest4_o$160 - connect \Y $or$libresoc.v:42408$1814_Y + connect \Y $or$libresoc.v:42456$1814_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42409$1815 + cell $or $or$libresoc.v:42457$1815 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72185,10 +72221,10 @@ module \core parameter \Y_WIDTH 1 connect \A \addr_en$1756 connect \B \addr_en$1772 - connect \Y $or$libresoc.v:42409$1815_Y + connect \Y $or$libresoc.v:42457$1815_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:42452$1860 + cell $or $or$libresoc.v:42500$1860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72196,10 +72232,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$229 connect \B \$233 - connect \Y $or$libresoc.v:42452$1860_Y + connect \Y $or$libresoc.v:42500$1860_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:42454$1862 + cell $or $or$libresoc.v:42502$1862 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72207,10 +72243,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$235 connect \B \$237 - connect \Y $or$libresoc.v:42454$1862_Y + connect \Y $or$libresoc.v:42502$1862_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $or $or$libresoc.v:42458$1866 + cell $or $or$libresoc.v:42506$1866 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72218,10 +72254,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$241 connect \B \$245 - connect \Y $or$libresoc.v:42458$1866_Y + connect \Y $or$libresoc.v:42506$1866_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:42466$1874 + cell $or $or$libresoc.v:42514$1874 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72229,10 +72265,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$257 connect \B \$261 - connect \Y $or$libresoc.v:42466$1874_Y + connect \Y $or$libresoc.v:42514$1874_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:42468$1876 + cell $or $or$libresoc.v:42516$1876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72240,10 +72276,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$263 connect \B \$265 - connect \Y $or$libresoc.v:42468$1876_Y + connect \Y $or$libresoc.v:42516$1876_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:42473$1881 + cell $or $or$libresoc.v:42521$1881 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72251,10 +72287,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$271 connect \B \$275 - connect \Y $or$libresoc.v:42473$1881_Y + connect \Y $or$libresoc.v:42521$1881_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:42475$1883 + cell $or $or$libresoc.v:42523$1883 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72262,10 +72298,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$277 connect \B \$279 - connect \Y $or$libresoc.v:42475$1883_Y + connect \Y $or$libresoc.v:42523$1883_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $or $or$libresoc.v:42479$1887 + cell $or $or$libresoc.v:42527$1887 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72273,10 +72309,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$283 connect \B \$287 - connect \Y $or$libresoc.v:42479$1887_Y + connect \Y $or$libresoc.v:42527$1887_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $or $or$libresoc.v:42483$1891 + cell $or $or$libresoc.v:42531$1891 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72284,10 +72320,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$291 connect \B \$295 - connect \Y $or$libresoc.v:42483$1891_Y + connect \Y $or$libresoc.v:42531$1891_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:42488$1896 + cell $or $or$libresoc.v:42536$1896 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72295,10 +72331,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$301 connect \B \$305 - connect \Y $or$libresoc.v:42488$1896_Y + connect \Y $or$libresoc.v:42536$1896_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:42490$1898 + cell $or $or$libresoc.v:42538$1898 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72306,10 +72342,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$307 connect \B \$309 - connect \Y $or$libresoc.v:42490$1898_Y + connect \Y $or$libresoc.v:42538$1898_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:42495$1903 + cell $or $or$libresoc.v:42543$1903 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72317,10 +72353,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$315 connect \B \$319 - connect \Y $or$libresoc.v:42495$1903_Y + connect \Y $or$libresoc.v:42543$1903_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:42497$1905 + cell $or $or$libresoc.v:42545$1905 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72328,10 +72364,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$321 connect \B \$323 - connect \Y $or$libresoc.v:42497$1905_Y + connect \Y $or$libresoc.v:42545$1905_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:42502$1910 + cell $or $or$libresoc.v:42550$1910 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72339,10 +72375,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$329 connect \B \$333 - connect \Y $or$libresoc.v:42502$1910_Y + connect \Y $or$libresoc.v:42550$1910_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:42504$1912 + cell $or $or$libresoc.v:42552$1912 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72350,10 +72386,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$335 connect \B \$337 - connect \Y $or$libresoc.v:42504$1912_Y + connect \Y $or$libresoc.v:42552$1912_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $or $or$libresoc.v:42508$1916 + cell $or $or$libresoc.v:42556$1916 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72361,10 +72397,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$341 connect \B \$345 - connect \Y $or$libresoc.v:42508$1916_Y + connect \Y $or$libresoc.v:42556$1916_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42565$1973 + cell $or $or$libresoc.v:42613$1973 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72372,10 +72408,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en_INT_ra_alu0_0 connect \B \addr_en_INT_ra_cr0_1 - connect \Y $or$libresoc.v:42565$1973_Y + connect \Y $or$libresoc.v:42613$1973_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42566$1974 + cell $or $or$libresoc.v:42614$1974 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72383,10 +72419,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en_INT_ra_trap0_2 connect \B \addr_en_INT_ra_logical0_3 - connect \Y $or$libresoc.v:42566$1974_Y + connect \Y $or$libresoc.v:42614$1974_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42567$1975 + cell $or $or$libresoc.v:42615$1975 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72394,10 +72430,10 @@ module \core parameter \Y_WIDTH 7 connect \A \$461 connect \B \$463 - connect \Y $or$libresoc.v:42567$1975_Y + connect \Y $or$libresoc.v:42615$1975_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42568$1976 + cell $or $or$libresoc.v:42616$1976 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72405,10 +72441,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en_INT_ra_spr0_4 connect \B \addr_en_INT_ra_div0_5 - connect \Y $or$libresoc.v:42568$1976_Y + connect \Y $or$libresoc.v:42616$1976_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42569$1977 + cell $or $or$libresoc.v:42617$1977 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72416,10 +72452,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en_INT_ra_shiftrot0_7 connect \B \addr_en_INT_ra_ldst0_8 - connect \Y $or$libresoc.v:42569$1977_Y + connect \Y $or$libresoc.v:42617$1977_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42570$1978 + cell $or $or$libresoc.v:42618$1978 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72427,10 +72463,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en_INT_ra_mul0_6 connect \B \$469 - connect \Y $or$libresoc.v:42570$1978_Y + connect \Y $or$libresoc.v:42618$1978_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42571$1979 + cell $or $or$libresoc.v:42619$1979 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72438,10 +72474,10 @@ module \core parameter \Y_WIDTH 7 connect \A \$467 connect \B \$471 - connect \Y $or$libresoc.v:42571$1979_Y + connect \Y $or$libresoc.v:42619$1979_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42572$1980 + cell $or $or$libresoc.v:42620$1980 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72449,10 +72485,10 @@ module \core parameter \Y_WIDTH 7 connect \A \$465 connect \B \$473 - connect \Y $or$libresoc.v:42572$1980_Y + connect \Y $or$libresoc.v:42620$1980_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42622$2030 + cell $or $or$libresoc.v:42670$2030 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72460,10 +72496,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en_INT_rb_alu0_0 connect \B \addr_en_INT_rb_cr0_1 - connect \Y $or$libresoc.v:42622$2030_Y + connect \Y $or$libresoc.v:42670$2030_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42623$2031 + cell $or $or$libresoc.v:42671$2031 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72471,10 +72507,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en_INT_rb_trap0_2 connect \B \addr_en_INT_rb_logical0_3 - connect \Y $or$libresoc.v:42623$2031_Y + connect \Y $or$libresoc.v:42671$2031_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42624$2032 + cell $or $or$libresoc.v:42672$2032 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72482,10 +72518,10 @@ module \core parameter \Y_WIDTH 7 connect \A \$576 connect \B \$578 - connect \Y $or$libresoc.v:42624$2032_Y + connect \Y $or$libresoc.v:42672$2032_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42625$2033 + cell $or $or$libresoc.v:42673$2033 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72493,10 +72529,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en_INT_rb_div0_4 connect \B \addr_en_INT_rb_mul0_5 - connect \Y $or$libresoc.v:42625$2033_Y + connect \Y $or$libresoc.v:42673$2033_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42626$2034 + cell $or $or$libresoc.v:42674$2034 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72504,10 +72540,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en_INT_rb_shiftrot0_6 connect \B \addr_en_INT_rb_ldst0_7 - connect \Y $or$libresoc.v:42626$2034_Y + connect \Y $or$libresoc.v:42674$2034_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42627$2035 + cell $or $or$libresoc.v:42675$2035 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72515,10 +72551,10 @@ module \core parameter \Y_WIDTH 7 connect \A \$582 connect \B \$584 - connect \Y $or$libresoc.v:42627$2035_Y + connect \Y $or$libresoc.v:42675$2035_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42628$2036 + cell $or $or$libresoc.v:42676$2036 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72526,10 +72562,10 @@ module \core parameter \Y_WIDTH 7 connect \A \$580 connect \B \$586 - connect \Y $or$libresoc.v:42628$2036_Y + connect \Y $or$libresoc.v:42676$2036_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42642$2050 + cell $or $or$libresoc.v:42690$2050 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -72537,10 +72573,10 @@ module \core parameter \Y_WIDTH 7 connect \A \addr_en_INT_rc_shiftrot0_0 connect \B \addr_en_INT_rc_ldst0_1 - connect \Y $or$libresoc.v:42642$2050_Y + connect \Y $or$libresoc.v:42690$2050_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $or$libresoc.v:42647$2055 + cell $or $or$libresoc.v:42695$2055 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72548,10 +72584,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$621 connect \B \$625 - connect \Y $or$libresoc.v:42647$2055_Y + connect \Y $or$libresoc.v:42695$2055_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $or$libresoc.v:42649$2057 + cell $or $or$libresoc.v:42697$2057 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72559,10 +72595,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$627 connect \B \$629 - connect \Y $or$libresoc.v:42649$2057_Y + connect \Y $or$libresoc.v:42697$2057_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42686$2094 + cell $or $or$libresoc.v:42734$2094 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72570,10 +72606,10 @@ module \core parameter \Y_WIDTH 1 connect \A \addr_en_XER_xer_so_logical0_1 connect \B \addr_en_XER_xer_so_spr0_2 - connect \Y $or$libresoc.v:42686$2094_Y + connect \Y $or$libresoc.v:42734$2094_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42687$2095 + cell $or $or$libresoc.v:42735$2095 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72581,10 +72617,10 @@ module \core parameter \Y_WIDTH 1 connect \A \addr_en_XER_xer_so_alu0_0 connect \B \$706 - connect \Y $or$libresoc.v:42687$2095_Y + connect \Y $or$libresoc.v:42735$2095_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42688$2096 + cell $or $or$libresoc.v:42736$2096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72592,10 +72628,10 @@ module \core parameter \Y_WIDTH 1 connect \A \addr_en_XER_xer_so_mul0_4 connect \B \addr_en_XER_xer_so_shiftrot0_5 - connect \Y $or$libresoc.v:42688$2096_Y + connect \Y $or$libresoc.v:42736$2096_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42689$2097 + cell $or $or$libresoc.v:42737$2097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72603,10 +72639,10 @@ module \core parameter \Y_WIDTH 1 connect \A \addr_en_XER_xer_so_div0_3 connect \B \$710 - connect \Y $or$libresoc.v:42689$2097_Y + connect \Y $or$libresoc.v:42737$2097_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42690$2098 + cell $or $or$libresoc.v:42738$2098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72614,10 +72650,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$708 connect \B \$712 - connect \Y $or$libresoc.v:42690$2098_Y + connect \Y $or$libresoc.v:42738$2098_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $or $or$libresoc.v:42695$2104 + cell $or $or$libresoc.v:42743$2104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72625,10 +72661,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$717 connect \B \$721 - connect \Y $or$libresoc.v:42695$2104_Y + connect \Y $or$libresoc.v:42743$2104_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42714$2123 + cell $or $or$libresoc.v:42762$2123 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -72636,10 +72672,10 @@ module \core parameter \Y_WIDTH 2 connect \A \addr_en_XER_xer_ca_spr0_1 connect \B \addr_en_XER_xer_ca_shiftrot0_2 - connect \Y $or$libresoc.v:42714$2123_Y + connect \Y $or$libresoc.v:42762$2123_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42715$2124 + cell $or $or$libresoc.v:42763$2124 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -72647,10 +72683,10 @@ module \core parameter \Y_WIDTH 2 connect \A \addr_en_XER_xer_ca_alu0_0 connect \B \$762 - connect \Y $or$libresoc.v:42715$2124_Y + connect \Y $or$libresoc.v:42763$2124_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $or $or$libresoc.v:42720$2130 + cell $or $or$libresoc.v:42768$2130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72658,10 +72694,10 @@ module \core parameter \Y_WIDTH 1 connect \A \$767 connect \B \$771 - connect \Y $or$libresoc.v:42720$2130_Y + connect \Y $or$libresoc.v:42768$2130_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42749$2159 + cell $or $or$libresoc.v:42797$2159 parameter \A_SIGNED 0 parameter \A_WIDTH 256 parameter \B_SIGNED 0 @@ -72669,10 +72705,10 @@ module \core parameter \Y_WIDTH 256 connect \A \addr_en_CR_cr_a_cr0_0 connect \B \addr_en_CR_cr_a_branch0_1 - connect \Y $or$libresoc.v:42749$2159_Y + connect \Y $or$libresoc.v:42797$2159_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42784$2194 + cell $or $or$libresoc.v:42832$2194 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72680,10 +72716,10 @@ module \core parameter \Y_WIDTH 3 connect \A \addr_en_FAST_fast1_trap0_1 connect \B \addr_en_FAST_fast1_spr0_2 - connect \Y $or$libresoc.v:42784$2194_Y + connect \Y $or$libresoc.v:42832$2194_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:42785$2195 + cell $or $or$libresoc.v:42833$2195 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72691,10 +72727,10 @@ module \core parameter \Y_WIDTH 3 connect \A \addr_en_FAST_fast1_branch0_0 connect \B \$902 - connect \Y $or$libresoc.v:42785$2195_Y + connect \Y $or$libresoc.v:42833$2195_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:42799$2209 + cell $or $or$libresoc.v:42847$2209 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -72702,194 +72738,194 @@ module \core parameter \Y_WIDTH 3 connect \A \addr_en_FAST_fast2_branch0_0 connect \B \addr_en_FAST_fast2_trap0_1 - connect \Y $or$libresoc.v:42799$2209_Y + connect \Y $or$libresoc.v:42847$2209_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $pos$libresoc.v:42276$1680 + cell $pos $pos$libresoc.v:42324$1680 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $extend$libresoc.v:42276$1679_Y - connect \Y $pos$libresoc.v:42276$1680_Y + connect \A $extend$libresoc.v:42324$1679_Y + connect \Y $pos$libresoc.v:42324$1680_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $pos$libresoc.v:42342$1747 + cell $pos $pos$libresoc.v:42390$1747 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 - connect \A $extend$libresoc.v:42342$1746_Y - connect \Y $pos$libresoc.v:42342$1747_Y + connect \A $extend$libresoc.v:42390$1746_Y + connect \Y $pos$libresoc.v:42390$1747_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $pos$libresoc.v:42346$1752 + cell $pos $pos$libresoc.v:42394$1752 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $extend$libresoc.v:42346$1751_Y - connect \Y $pos$libresoc.v:42346$1752_Y + connect \A $extend$libresoc.v:42394$1751_Y + connect \Y $pos$libresoc.v:42394$1752_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $pos $pos$libresoc.v:42410$1817 + cell $pos $pos$libresoc.v:42458$1817 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $extend$libresoc.v:42410$1816_Y - connect \Y $pos$libresoc.v:42410$1817_Y + connect \A $extend$libresoc.v:42458$1816_Y + connect \Y $pos$libresoc.v:42458$1817_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:417" - cell $pos $pos$libresoc.v:42418$1826 + cell $pos $pos$libresoc.v:42466$1826 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $extend$libresoc.v:42418$1825_Y - connect \Y $pos$libresoc.v:42418$1826_Y + connect \A $extend$libresoc.v:42466$1825_Y + connect \Y $pos$libresoc.v:42466$1826_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $pos$libresoc.v:42691$2100 + cell $pos $pos$libresoc.v:42739$2100 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $extend$libresoc.v:42691$2099_Y - connect \Y $pos$libresoc.v:42691$2100_Y + connect \A $extend$libresoc.v:42739$2099_Y + connect \Y $pos$libresoc.v:42739$2100_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $pos $pos$libresoc.v:42716$2126 + cell $pos $pos$libresoc.v:42764$2126 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 - connect \A $extend$libresoc.v:42716$2125_Y - connect \Y $pos$libresoc.v:42716$2126_Y + connect \A $extend$libresoc.v:42764$2125_Y + connect \Y $pos$libresoc.v:42764$2126_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $reduce_or $reduce_or$libresoc.v:42427$1835 + cell $reduce_or $reduce_or$libresoc.v:42475$1835 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \Y_WIDTH 1 connect \A \$182 - connect \Y $reduce_or$libresoc.v:42427$1835_Y + connect \Y $reduce_or$libresoc.v:42475$1835_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $reduce_or $reduce_or$libresoc.v:42429$1837 + cell $reduce_or $reduce_or$libresoc.v:42477$1837 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \Y_WIDTH 1 connect \A \$186 - connect \Y $reduce_or$libresoc.v:42429$1837_Y + connect \Y $reduce_or$libresoc.v:42477$1837_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $reduce_or $reduce_or$libresoc.v:42431$1839 + cell $reduce_or $reduce_or$libresoc.v:42479$1839 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \Y_WIDTH 1 connect \A \$190 - connect \Y $reduce_or$libresoc.v:42431$1839_Y + connect \Y $reduce_or$libresoc.v:42479$1839_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $reduce_or $reduce_or$libresoc.v:42433$1841 + cell $reduce_or $reduce_or$libresoc.v:42481$1841 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \Y_WIDTH 1 connect \A \$194 - connect \Y $reduce_or$libresoc.v:42433$1841_Y + connect \Y $reduce_or$libresoc.v:42481$1841_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $reduce_or $reduce_or$libresoc.v:42435$1843 + cell $reduce_or $reduce_or$libresoc.v:42483$1843 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \Y_WIDTH 1 connect \A \$198 - connect \Y $reduce_or$libresoc.v:42435$1843_Y + connect \Y $reduce_or$libresoc.v:42483$1843_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $reduce_or $reduce_or$libresoc.v:42437$1845 + cell $reduce_or $reduce_or$libresoc.v:42485$1845 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \Y_WIDTH 1 connect \A \$202 - connect \Y $reduce_or$libresoc.v:42437$1845_Y + connect \Y $reduce_or$libresoc.v:42485$1845_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $reduce_or $reduce_or$libresoc.v:42439$1847 + cell $reduce_or $reduce_or$libresoc.v:42487$1847 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \Y_WIDTH 1 connect \A \$206 - connect \Y $reduce_or$libresoc.v:42439$1847_Y + connect \Y $reduce_or$libresoc.v:42487$1847_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $reduce_or $reduce_or$libresoc.v:42441$1849 + cell $reduce_or $reduce_or$libresoc.v:42489$1849 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \Y_WIDTH 1 connect \A \$210 - connect \Y $reduce_or$libresoc.v:42441$1849_Y + connect \Y $reduce_or$libresoc.v:42489$1849_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $reduce_or $reduce_or$libresoc.v:42443$1851 + cell $reduce_or $reduce_or$libresoc.v:42491$1851 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \Y_WIDTH 1 connect \A \$214 - connect \Y $reduce_or$libresoc.v:42443$1851_Y + connect \Y $reduce_or$libresoc.v:42491$1851_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - cell $reduce_or $reduce_or$libresoc.v:42445$1853 + cell $reduce_or $reduce_or$libresoc.v:42493$1853 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \Y_WIDTH 1 connect \A \$218 - connect \Y $reduce_or$libresoc.v:42445$1853_Y + connect \Y $reduce_or$libresoc.v:42493$1853_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" - cell $reduce_or $reduce_or$libresoc.v:42573$1981 + cell $reduce_or $reduce_or$libresoc.v:42621$1981 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 1 connect \A { \rp_INT_ra_ldst0_8 \rp_INT_ra_shiftrot0_7 \rp_INT_ra_mul0_6 \rp_INT_ra_div0_5 \rp_INT_ra_spr0_4 \rp_INT_ra_logical0_3 \rp_INT_ra_trap0_2 \rp_INT_ra_cr0_1 \rp_INT_ra_alu0_0 } - connect \Y $reduce_or$libresoc.v:42573$1981_Y + connect \Y $reduce_or$libresoc.v:42621$1981_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" - cell $reduce_or $reduce_or$libresoc.v:42629$2037 + cell $reduce_or $reduce_or$libresoc.v:42677$2037 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \rp_INT_rb_ldst0_7 \rp_INT_rb_shiftrot0_6 \rp_INT_rb_mul0_5 \rp_INT_rb_div0_4 \rp_INT_rb_logical0_3 \rp_INT_rb_trap0_2 \rp_INT_rb_cr0_1 \rp_INT_rb_alu0_0 } - connect \Y $reduce_or$libresoc.v:42629$2037_Y + connect \Y $reduce_or$libresoc.v:42677$2037_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" - cell $reduce_or $reduce_or$libresoc.v:42643$2051 + cell $reduce_or $reduce_or$libresoc.v:42691$2051 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \rp_INT_rc_ldst0_1 \rp_INT_rc_shiftrot0_0 } - connect \Y $reduce_or$libresoc.v:42643$2051_Y + connect \Y $reduce_or$libresoc.v:42691$2051_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" - cell $reduce_or $reduce_or$libresoc.v:42786$2196 + cell $reduce_or $reduce_or$libresoc.v:42834$2196 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \rp_FAST_fast1_spr0_2 \rp_FAST_fast1_trap0_1 \rp_FAST_fast1_branch0_0 } - connect \Y $reduce_or$libresoc.v:42786$2196_Y + connect \Y $reduce_or$libresoc.v:42834$2196_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" - cell $reduce_or $reduce_or$libresoc.v:42800$2210 + cell $reduce_or $reduce_or$libresoc.v:42848$2210 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \rp_FAST_fast2_trap0_1 \rp_FAST_fast2_branch0_0 } - connect \Y $reduce_or$libresoc.v:42800$2210_Y + connect \Y $reduce_or$libresoc.v:42848$2210_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:316" - cell $reduce_or $reduce_or$libresoc.v:42807$2217 + cell $reduce_or $reduce_or$libresoc.v:42855$2217 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rp_SPR_spr1_spr0_0 - connect \Y $reduce_or$libresoc.v:42807$2217_Y + connect \Y $reduce_or$libresoc.v:42855$2217_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$libresoc.v:42199$1602 + cell $sshl $sshl$libresoc.v:42247$1602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72897,10 +72933,10 @@ module \core parameter \Y_WIDTH 256 connect \A 1'1 connect \B \$1259 - connect \Y $sshl$libresoc.v:42199$1602_Y + connect \Y $sshl$libresoc.v:42247$1602_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$libresoc.v:42207$1610 + cell $sshl $sshl$libresoc.v:42255$1610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72908,10 +72944,10 @@ module \core parameter \Y_WIDTH 256 connect \A 1'1 connect \B \$1279 - connect \Y $sshl$libresoc.v:42207$1610_Y + connect \Y $sshl$libresoc.v:42255$1610_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$libresoc.v:42215$1618 + cell $sshl $sshl$libresoc.v:42263$1618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72919,10 +72955,10 @@ module \core parameter \Y_WIDTH 256 connect \A 1'1 connect \B \$1299 - connect \Y $sshl$libresoc.v:42215$1618_Y + connect \Y $sshl$libresoc.v:42263$1618_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$libresoc.v:42223$1626 + cell $sshl $sshl$libresoc.v:42271$1626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72930,10 +72966,10 @@ module \core parameter \Y_WIDTH 256 connect \A 1'1 connect \B \$1319 - connect \Y $sshl$libresoc.v:42223$1626_Y + connect \Y $sshl$libresoc.v:42271$1626_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$libresoc.v:42231$1634 + cell $sshl $sshl$libresoc.v:42279$1634 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72941,10 +72977,10 @@ module \core parameter \Y_WIDTH 256 connect \A 1'1 connect \B \$1339 - connect \Y $sshl$libresoc.v:42231$1634_Y + connect \Y $sshl$libresoc.v:42279$1634_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $sshl$libresoc.v:42239$1642 + cell $sshl $sshl$libresoc.v:42287$1642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72952,10 +72988,10 @@ module \core parameter \Y_WIDTH 256 connect \A 1'1 connect \B \$1359 - connect \Y $sshl$libresoc.v:42239$1642_Y + connect \Y $sshl$libresoc.v:42287$1642_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" - cell $sshl $sshl$libresoc.v:42739$2149 + cell $sshl $sshl$libresoc.v:42787$2149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72963,10 +72999,10 @@ module \core parameter \Y_WIDTH 256 connect \A 1'1 connect \B \$809 - connect \Y $sshl$libresoc.v:42739$2149_Y + connect \Y $sshl$libresoc.v:42787$2149_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" - cell $sshl $sshl$libresoc.v:42747$2157 + cell $sshl $sshl$libresoc.v:42795$2157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72974,10 +73010,10 @@ module \core parameter \Y_WIDTH 256 connect \A 1'1 connect \B \$825 - connect \Y $sshl$libresoc.v:42747$2157_Y + connect \Y $sshl$libresoc.v:42795$2157_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" - cell $sshl $sshl$libresoc.v:42756$2166 + cell $sshl $sshl$libresoc.v:42804$2166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72985,10 +73021,10 @@ module \core parameter \Y_WIDTH 256 connect \A 1'1 connect \B \$844 - connect \Y $sshl$libresoc.v:42756$2166_Y + connect \Y $sshl$libresoc.v:42804$2166_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" - cell $sshl $sshl$libresoc.v:42764$2174 + cell $sshl $sshl$libresoc.v:42812$2174 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -72996,10 +73032,10 @@ module \core parameter \Y_WIDTH 256 connect \A 1'1 connect \B \$860 - connect \Y $sshl$libresoc.v:42764$2174_Y + connect \Y $sshl$libresoc.v:42812$2174_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$libresoc.v:42198$1601 + cell $sub $sub$libresoc.v:42246$1601 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -73007,10 +73043,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_out - connect \Y $sub$libresoc.v:42198$1601_Y + connect \Y $sub$libresoc.v:42246$1601_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$libresoc.v:42206$1609 + cell $sub $sub$libresoc.v:42254$1609 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -73018,10 +73054,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_out - connect \Y $sub$libresoc.v:42206$1609_Y + connect \Y $sub$libresoc.v:42254$1609_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$libresoc.v:42214$1617 + cell $sub $sub$libresoc.v:42262$1617 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -73029,10 +73065,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_out - connect \Y $sub$libresoc.v:42214$1617_Y + connect \Y $sub$libresoc.v:42262$1617_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$libresoc.v:42222$1625 + cell $sub $sub$libresoc.v:42270$1625 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -73040,10 +73076,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_out - connect \Y $sub$libresoc.v:42222$1625_Y + connect \Y $sub$libresoc.v:42270$1625_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$libresoc.v:42230$1633 + cell $sub $sub$libresoc.v:42278$1633 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -73051,10 +73087,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_out - connect \Y $sub$libresoc.v:42230$1633_Y + connect \Y $sub$libresoc.v:42278$1633_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $sub$libresoc.v:42238$1641 + cell $sub $sub$libresoc.v:42286$1641 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -73062,10 +73098,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_out - connect \Y $sub$libresoc.v:42238$1641_Y + connect \Y $sub$libresoc.v:42286$1641_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:190" - cell $sub $sub$libresoc.v:42447$1855 + cell $sub $sub$libresoc.v:42495$1855 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -73073,10 +73109,10 @@ module \core parameter \Y_WIDTH 3 connect \A \counter connect \B 1'1 - connect \Y $sub$libresoc.v:42447$1855_Y + connect \Y $sub$libresoc.v:42495$1855_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" - cell $sub $sub$libresoc.v:42738$2148 + cell $sub $sub$libresoc.v:42786$2148 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -73084,10 +73120,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_in1 - connect \Y $sub$libresoc.v:42738$2148_Y + connect \Y $sub$libresoc.v:42786$2148_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" - cell $sub $sub$libresoc.v:42746$2156 + cell $sub $sub$libresoc.v:42794$2156 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -73095,10 +73131,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_in1 - connect \Y $sub$libresoc.v:42746$2156_Y + connect \Y $sub$libresoc.v:42794$2156_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" - cell $sub $sub$libresoc.v:42755$2165 + cell $sub $sub$libresoc.v:42803$2165 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -73106,10 +73142,10 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_in2 - connect \Y $sub$libresoc.v:42755$2165_Y + connect \Y $sub$libresoc.v:42803$2165_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" - cell $sub $sub$libresoc.v:42763$2173 + cell $sub $sub$libresoc.v:42811$2173 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -73117,626 +73153,626 @@ module \core parameter \Y_WIDTH 8 connect \A 3'111 connect \B \core_cr_in2$1 - connect \Y $sub$libresoc.v:42763$2173_Y + connect \Y $sub$libresoc.v:42811$2173_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42104$1507 + cell $mux $ternary$libresoc.v:42152$1507 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego connect \S \wp$999 - connect \Y $ternary$libresoc.v:42104$1507_Y + connect \Y $ternary$libresoc.v:42152$1507_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42110$1513 + cell $mux $ternary$libresoc.v:42158$1513 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego connect \S \wp$1020 - connect \Y $ternary$libresoc.v:42110$1513_Y + connect \Y $ternary$libresoc.v:42158$1513_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42116$1519 + cell $mux $ternary$libresoc.v:42164$1519 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego connect \S \wp$1038 - connect \Y $ternary$libresoc.v:42116$1519_Y + connect \Y $ternary$libresoc.v:42164$1519_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42122$1525 + cell $mux $ternary$libresoc.v:42170$1525 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego connect \S \wp$1060 - connect \Y $ternary$libresoc.v:42122$1525_Y + connect \Y $ternary$libresoc.v:42170$1525_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42128$1531 + cell $mux $ternary$libresoc.v:42176$1531 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego connect \S \wp$1080 - connect \Y $ternary$libresoc.v:42128$1531_Y + connect \Y $ternary$libresoc.v:42176$1531_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42134$1537 + cell $mux $ternary$libresoc.v:42182$1537 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego connect \S \wp$1100 - connect \Y $ternary$libresoc.v:42134$1537_Y + connect \Y $ternary$libresoc.v:42182$1537_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42140$1543 + cell $mux $ternary$libresoc.v:42188$1543 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego connect \S \wp$1119 - connect \Y $ternary$libresoc.v:42140$1543_Y + connect \Y $ternary$libresoc.v:42188$1543_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42146$1549 + cell $mux $ternary$libresoc.v:42194$1549 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego connect \S \wp$1137 - connect \Y $ternary$libresoc.v:42146$1549_Y + connect \Y $ternary$libresoc.v:42194$1549_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42152$1555 + cell $mux $ternary$libresoc.v:42200$1555 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_ea connect \S \wp$1153 - connect \Y $ternary$libresoc.v:42152$1555_Y + connect \Y $ternary$libresoc.v:42200$1555_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42186$1589 + cell $mux $ternary$libresoc.v:42234$1589 parameter \WIDTH 8 connect \A 8'00000000 connect \B \core_core_cr_wr connect \S \wp$1227 - connect \Y $ternary$libresoc.v:42186$1589_Y + connect \Y $ternary$libresoc.v:42234$1589_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42200$1603 + cell $mux $ternary$libresoc.v:42248$1603 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 connect \B \$1261 connect \S \wp$1255 - connect \Y $ternary$libresoc.v:42200$1603_Y + connect \Y $ternary$libresoc.v:42248$1603_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42208$1611 + cell $mux $ternary$libresoc.v:42256$1611 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 connect \B \$1281 connect \S \wp$1275 - connect \Y $ternary$libresoc.v:42208$1611_Y + connect \Y $ternary$libresoc.v:42256$1611_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42216$1619 + cell $mux $ternary$libresoc.v:42264$1619 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 connect \B \$1301 connect \S \wp$1295 - connect \Y $ternary$libresoc.v:42216$1619_Y + connect \Y $ternary$libresoc.v:42264$1619_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42224$1627 + cell $mux $ternary$libresoc.v:42272$1627 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 connect \B \$1321 connect \S \wp$1315 - connect \Y $ternary$libresoc.v:42224$1627_Y + connect \Y $ternary$libresoc.v:42272$1627_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42232$1635 + cell $mux $ternary$libresoc.v:42280$1635 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 connect \B \$1341 connect \S \wp$1335 - connect \Y $ternary$libresoc.v:42232$1635_Y + connect \Y $ternary$libresoc.v:42280$1635_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42240$1643 + cell $mux $ternary$libresoc.v:42288$1643 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 connect \B \$1361 connect \S \wp$1355 - connect \Y $ternary$libresoc.v:42240$1643_Y + connect \Y $ternary$libresoc.v:42288$1643_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42259$1662 + cell $mux $ternary$libresoc.v:42307$1662 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \wp$1402 - connect \Y $ternary$libresoc.v:42259$1662_Y + connect \Y $ternary$libresoc.v:42307$1662_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42265$1668 + cell $mux $ternary$libresoc.v:42313$1668 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \wp$1418 - connect \Y $ternary$libresoc.v:42265$1668_Y + connect \Y $ternary$libresoc.v:42313$1668_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42271$1674 + cell $mux $ternary$libresoc.v:42319$1674 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \wp$1434 - connect \Y $ternary$libresoc.v:42271$1674_Y + connect \Y $ternary$libresoc.v:42319$1674_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42286$1690 + cell $mux $ternary$libresoc.v:42334$1690 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 connect \S \wp$1468 - connect \Y $ternary$libresoc.v:42286$1690_Y + connect \Y $ternary$libresoc.v:42334$1690_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42292$1696 + cell $mux $ternary$libresoc.v:42340$1696 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 connect \S \wp$1484 - connect \Y $ternary$libresoc.v:42292$1696_Y + connect \Y $ternary$libresoc.v:42340$1696_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42298$1702 + cell $mux $ternary$libresoc.v:42346$1702 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 connect \S \wp$1500 - connect \Y $ternary$libresoc.v:42298$1702_Y + connect \Y $ternary$libresoc.v:42346$1702_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42304$1708 + cell $mux $ternary$libresoc.v:42352$1708 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 connect \S \wp$1516 - connect \Y $ternary$libresoc.v:42304$1708_Y + connect \Y $ternary$libresoc.v:42352$1708_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42320$1724 + cell $mux $ternary$libresoc.v:42368$1724 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \wp$1552 - connect \Y $ternary$libresoc.v:42320$1724_Y + connect \Y $ternary$libresoc.v:42368$1724_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42326$1730 + cell $mux $ternary$libresoc.v:42374$1730 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \wp$1568 - connect \Y $ternary$libresoc.v:42326$1730_Y + connect \Y $ternary$libresoc.v:42374$1730_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42332$1736 + cell $mux $ternary$libresoc.v:42380$1736 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \wp$1584 - connect \Y $ternary$libresoc.v:42332$1736_Y + connect \Y $ternary$libresoc.v:42380$1736_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42338$1742 + cell $mux $ternary$libresoc.v:42386$1742 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \wp$1600 - connect \Y $ternary$libresoc.v:42338$1742_Y + connect \Y $ternary$libresoc.v:42386$1742_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42357$1763 + cell $mux $ternary$libresoc.v:42405$1763 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fasto1 connect \S \wp$1645 - connect \Y $ternary$libresoc.v:42357$1763_Y + connect \Y $ternary$libresoc.v:42405$1763_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42363$1769 + cell $mux $ternary$libresoc.v:42411$1769 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fasto1 connect \S \wp$1661 - connect \Y $ternary$libresoc.v:42363$1769_Y + connect \Y $ternary$libresoc.v:42411$1769_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42369$1775 + cell $mux $ternary$libresoc.v:42417$1775 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fasto1 connect \S \wp$1677 - connect \Y $ternary$libresoc.v:42369$1775_Y + connect \Y $ternary$libresoc.v:42417$1775_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42375$1781 + cell $mux $ternary$libresoc.v:42423$1781 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fasto2 connect \S \wp$1693 - connect \Y $ternary$libresoc.v:42375$1781_Y + connect \Y $ternary$libresoc.v:42423$1781_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42381$1787 + cell $mux $ternary$libresoc.v:42429$1787 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fasto2 connect \S \wp$1709 - connect \Y $ternary$libresoc.v:42381$1787_Y + connect \Y $ternary$libresoc.v:42429$1787_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42401$1807 + cell $mux $ternary$libresoc.v:42449$1807 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \wp$1753 - connect \Y $ternary$libresoc.v:42401$1807_Y + connect \Y $ternary$libresoc.v:42449$1807_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42407$1813 + cell $mux $ternary$libresoc.v:42455$1813 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \wp$1769 - connect \Y $ternary$libresoc.v:42407$1813_Y + connect \Y $ternary$libresoc.v:42455$1813_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42417$1824 + cell $mux $ternary$libresoc.v:42465$1824 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \wp$1793 - connect \Y $ternary$libresoc.v:42417$1824_Y + connect \Y $ternary$libresoc.v:42465$1824_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42425$1833 + cell $mux $ternary$libresoc.v:42473$1833 parameter \WIDTH 10 connect \A 10'0000000000 connect \B \core_spro connect \S \wp$1813 - connect \Y $ternary$libresoc.v:42425$1833_Y + connect \Y $ternary$libresoc.v:42473$1833_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42516$1924 + cell $mux $ternary$libresoc.v:42564$1924 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_ra_alu0_0 - connect \Y $ternary$libresoc.v:42516$1924_Y + connect \Y $ternary$libresoc.v:42564$1924_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42522$1930 + cell $mux $ternary$libresoc.v:42570$1930 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_ra_cr0_1 - connect \Y $ternary$libresoc.v:42522$1930_Y + connect \Y $ternary$libresoc.v:42570$1930_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42528$1936 + cell $mux $ternary$libresoc.v:42576$1936 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_ra_trap0_2 - connect \Y $ternary$libresoc.v:42528$1936_Y + connect \Y $ternary$libresoc.v:42576$1936_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42534$1942 + cell $mux $ternary$libresoc.v:42582$1942 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_ra_logical0_3 - connect \Y $ternary$libresoc.v:42534$1942_Y + connect \Y $ternary$libresoc.v:42582$1942_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42540$1948 + cell $mux $ternary$libresoc.v:42588$1948 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_ra_spr0_4 - connect \Y $ternary$libresoc.v:42540$1948_Y + connect \Y $ternary$libresoc.v:42588$1948_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42546$1954 + cell $mux $ternary$libresoc.v:42594$1954 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_ra_div0_5 - connect \Y $ternary$libresoc.v:42546$1954_Y + connect \Y $ternary$libresoc.v:42594$1954_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42552$1960 + cell $mux $ternary$libresoc.v:42600$1960 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_ra_mul0_6 - connect \Y $ternary$libresoc.v:42552$1960_Y + connect \Y $ternary$libresoc.v:42600$1960_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42558$1966 + cell $mux $ternary$libresoc.v:42606$1966 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_ra_shiftrot0_7 - connect \Y $ternary$libresoc.v:42558$1966_Y + connect \Y $ternary$libresoc.v:42606$1966_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42564$1972 + cell $mux $ternary$libresoc.v:42612$1972 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg1 connect \S \rp_INT_ra_ldst0_8 - connect \Y $ternary$libresoc.v:42564$1972_Y + connect \Y $ternary$libresoc.v:42612$1972_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42579$1987 + cell $mux $ternary$libresoc.v:42627$1987 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rb_alu0_0 - connect \Y $ternary$libresoc.v:42579$1987_Y + connect \Y $ternary$libresoc.v:42627$1987_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42585$1993 + cell $mux $ternary$libresoc.v:42633$1993 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rb_cr0_1 - connect \Y $ternary$libresoc.v:42585$1993_Y + connect \Y $ternary$libresoc.v:42633$1993_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42591$1999 + cell $mux $ternary$libresoc.v:42639$1999 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rb_trap0_2 - connect \Y $ternary$libresoc.v:42591$1999_Y + connect \Y $ternary$libresoc.v:42639$1999_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42597$2005 + cell $mux $ternary$libresoc.v:42645$2005 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rb_logical0_3 - connect \Y $ternary$libresoc.v:42597$2005_Y + connect \Y $ternary$libresoc.v:42645$2005_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42603$2011 + cell $mux $ternary$libresoc.v:42651$2011 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rb_div0_4 - connect \Y $ternary$libresoc.v:42603$2011_Y + connect \Y $ternary$libresoc.v:42651$2011_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42609$2017 + cell $mux $ternary$libresoc.v:42657$2017 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rb_mul0_5 - connect \Y $ternary$libresoc.v:42609$2017_Y + connect \Y $ternary$libresoc.v:42657$2017_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42615$2023 + cell $mux $ternary$libresoc.v:42663$2023 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rb_shiftrot0_6 - connect \Y $ternary$libresoc.v:42615$2023_Y + connect \Y $ternary$libresoc.v:42663$2023_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42621$2029 + cell $mux $ternary$libresoc.v:42669$2029 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg2 connect \S \rp_INT_rb_ldst0_7 - connect \Y $ternary$libresoc.v:42621$2029_Y + connect \Y $ternary$libresoc.v:42669$2029_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42635$2043 + cell $mux $ternary$libresoc.v:42683$2043 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg3 connect \S \rp_INT_rc_shiftrot0_0 - connect \Y $ternary$libresoc.v:42635$2043_Y + connect \Y $ternary$libresoc.v:42683$2043_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42641$2049 + cell $mux $ternary$libresoc.v:42689$2049 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_reg3 connect \S \rp_INT_rc_ldst0_1 - connect \Y $ternary$libresoc.v:42641$2049_Y + connect \Y $ternary$libresoc.v:42689$2049_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42655$2063 + cell $mux $ternary$libresoc.v:42703$2063 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_alu0_0 - connect \Y $ternary$libresoc.v:42655$2063_Y + connect \Y $ternary$libresoc.v:42703$2063_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42661$2069 + cell $mux $ternary$libresoc.v:42709$2069 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_logical0_1 - connect \Y $ternary$libresoc.v:42661$2069_Y + connect \Y $ternary$libresoc.v:42709$2069_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42667$2075 + cell $mux $ternary$libresoc.v:42715$2075 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_spr0_2 - connect \Y $ternary$libresoc.v:42667$2075_Y + connect \Y $ternary$libresoc.v:42715$2075_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42673$2081 + cell $mux $ternary$libresoc.v:42721$2081 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_div0_3 - connect \Y $ternary$libresoc.v:42673$2081_Y + connect \Y $ternary$libresoc.v:42721$2081_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42679$2087 + cell $mux $ternary$libresoc.v:42727$2087 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_mul0_4 - connect \Y $ternary$libresoc.v:42679$2087_Y + connect \Y $ternary$libresoc.v:42727$2087_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42685$2093 + cell $mux $ternary$libresoc.v:42733$2093 parameter \WIDTH 1 connect \A 1'0 connect \B 1'1 connect \S \rp_XER_xer_so_shiftrot0_5 - connect \Y $ternary$libresoc.v:42685$2093_Y + connect \Y $ternary$libresoc.v:42733$2093_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42701$2110 + cell $mux $ternary$libresoc.v:42749$2110 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \rp_XER_xer_ca_alu0_0 - connect \Y $ternary$libresoc.v:42701$2110_Y + connect \Y $ternary$libresoc.v:42749$2110_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42707$2116 + cell $mux $ternary$libresoc.v:42755$2116 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \rp_XER_xer_ca_spr0_1 - connect \Y $ternary$libresoc.v:42707$2116_Y + connect \Y $ternary$libresoc.v:42755$2116_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42713$2122 + cell $mux $ternary$libresoc.v:42761$2122 parameter \WIDTH 2 connect \A 2'00 connect \B 2'10 connect \S \rp_XER_xer_ca_shiftrot0_2 - connect \Y $ternary$libresoc.v:42713$2122_Y + connect \Y $ternary$libresoc.v:42761$2122_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42726$2136 + cell $mux $ternary$libresoc.v:42774$2136 parameter \WIDTH 3 connect \A 3'000 connect \B 3'100 connect \S \rp_XER_xer_ov_spr0_0 - connect \Y $ternary$libresoc.v:42726$2136_Y + connect \Y $ternary$libresoc.v:42774$2136_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42732$2142 + cell $mux $ternary$libresoc.v:42780$2142 parameter \WIDTH 8 connect \A 8'00000000 connect \B \core_core_cr_rd connect \S \rp_CR_full_cr_cr0_0 - connect \Y $ternary$libresoc.v:42732$2142_Y + connect \Y $ternary$libresoc.v:42780$2142_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42740$2150 + cell $mux $ternary$libresoc.v:42788$2150 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 connect \B \$811 connect \S \rp_CR_cr_a_cr0_0 - connect \Y $ternary$libresoc.v:42740$2150_Y + connect \Y $ternary$libresoc.v:42788$2150_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42748$2158 + cell $mux $ternary$libresoc.v:42796$2158 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 connect \B \$827 connect \S \rp_CR_cr_a_branch0_1 - connect \Y $ternary$libresoc.v:42748$2158_Y + connect \Y $ternary$libresoc.v:42796$2158_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42757$2167 + cell $mux $ternary$libresoc.v:42805$2167 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 connect \B \$846 connect \S \rp_CR_cr_b_cr0_0 - connect \Y $ternary$libresoc.v:42757$2167_Y + connect \Y $ternary$libresoc.v:42805$2167_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42765$2175 + cell $mux $ternary$libresoc.v:42813$2175 parameter \WIDTH 256 connect \A 256'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 connect \B \$862 connect \S \rp_CR_cr_c_cr0_0 - connect \Y $ternary$libresoc.v:42765$2175_Y + connect \Y $ternary$libresoc.v:42813$2175_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42771$2181 + cell $mux $ternary$libresoc.v:42819$2181 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fast1 connect \S \rp_FAST_fast1_branch0_0 - connect \Y $ternary$libresoc.v:42771$2181_Y + connect \Y $ternary$libresoc.v:42819$2181_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42777$2187 + cell $mux $ternary$libresoc.v:42825$2187 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fast1 connect \S \rp_FAST_fast1_trap0_1 - connect \Y $ternary$libresoc.v:42777$2187_Y + connect \Y $ternary$libresoc.v:42825$2187_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42783$2193 + cell $mux $ternary$libresoc.v:42831$2193 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fast1 connect \S \rp_FAST_fast1_spr0_2 - connect \Y $ternary$libresoc.v:42783$2193_Y + connect \Y $ternary$libresoc.v:42831$2193_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42792$2202 + cell $mux $ternary$libresoc.v:42840$2202 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fast2 connect \S \rp_FAST_fast2_branch0_0 - connect \Y $ternary$libresoc.v:42792$2202_Y + connect \Y $ternary$libresoc.v:42840$2202_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42798$2208 + cell $mux $ternary$libresoc.v:42846$2208 parameter \WIDTH 3 connect \A 3'000 connect \B \core_fast2 connect \S \rp_FAST_fast2_trap0_1 - connect \Y $ternary$libresoc.v:42798$2208_Y + connect \Y $ternary$libresoc.v:42846$2208_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289" - cell $mux $ternary$libresoc.v:42806$2216 + cell $mux $ternary$libresoc.v:42854$2216 parameter \WIDTH 10 connect \A 10'0000000000 connect \B \core_spr1 connect \S \rp_SPR_spr1_spr0_0 - connect \Y $ternary$libresoc.v:42806$2216_Y + connect \Y $ternary$libresoc.v:42854$2216_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:420" - cell $mux $ternary$libresoc.v:42823$2233 + cell $mux $ternary$libresoc.v:42871$2233 parameter \WIDTH 7 connect \A 7'0000000 connect \B \core_rego connect \S \wp - connect \Y $ternary$libresoc.v:42823$2233_Y + connect \Y $ternary$libresoc.v:42871$2233_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:42986.6-43003.4" + attribute \src "libresoc.v:43034.6-43051.4" cell \cr \cr connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -73756,7 +73792,7 @@ module \core connect \wen \cr_wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:43004.11-43026.4" + attribute \src "libresoc.v:43052.11-43074.4" cell \dec_ALU \dec_ALU connect \ALU__data_len \dec_ALU_ALU__data_len connect \ALU__fn_unit \dec_ALU_ALU__fn_unit @@ -73781,7 +73817,7 @@ module \core connect \sv_a_nz \dec_ALU_sv_a_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:43027.14-43039.4" + attribute \src "libresoc.v:43075.14-43087.4" cell \dec_BRANCH \dec_BRANCH connect \BRANCH__cia \dec_BRANCH_BRANCH__cia connect \BRANCH__fn_unit \dec_BRANCH_BRANCH__fn_unit @@ -73796,7 +73832,7 @@ module \core connect \raw_opcode_in \dec_BRANCH_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:43040.10-43046.4" + attribute \src "libresoc.v:43088.10-43094.4" cell \dec_CR \dec_CR connect \CR__fn_unit \dec_CR_CR__fn_unit connect \CR__insn \dec_CR_CR__insn @@ -73805,7 +73841,7 @@ module \core connect \raw_opcode_in \dec_CR_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:43047.11-43069.4" + attribute \src "libresoc.v:43095.11-43117.4" cell \dec_DIV \dec_DIV connect \DIV__data_len \dec_DIV_DIV__data_len connect \DIV__fn_unit \dec_DIV_DIV__fn_unit @@ -73830,7 +73866,7 @@ module \core connect \sv_a_nz \dec_DIV_sv_a_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:43070.12-43090.4" + attribute \src "libresoc.v:43118.12-43138.4" cell \dec_LDST \dec_LDST connect \LDST__byte_reverse \dec_LDST_LDST__byte_reverse connect \LDST__data_len \dec_LDST_LDST__data_len @@ -73853,7 +73889,7 @@ module \core connect \sv_a_nz \dec_LDST_sv_a_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:43091.15-43113.4" + attribute \src "libresoc.v:43139.15-43161.4" cell \dec_LOGICAL \dec_LOGICAL connect \LOGICAL__data_len \dec_LOGICAL_LOGICAL__data_len connect \LOGICAL__fn_unit \dec_LOGICAL_LOGICAL__fn_unit @@ -73878,7 +73914,7 @@ module \core connect \sv_a_nz \dec_LOGICAL_sv_a_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:43114.11-43129.4" + attribute \src "libresoc.v:43162.11-43177.4" cell \dec_MUL \dec_MUL connect \MUL__fn_unit \dec_MUL_MUL__fn_unit connect \MUL__imm_data__data \dec_MUL_MUL__imm_data__data @@ -73896,7 +73932,7 @@ module \core connect \raw_opcode_in \dec_MUL_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:43130.17-43150.4" + attribute \src "libresoc.v:43178.17-43198.4" cell \dec_SHIFT_ROT \dec_SHIFT_ROT connect \SHIFT_ROT__fn_unit \dec_SHIFT_ROT_SHIFT_ROT__fn_unit connect \SHIFT_ROT__imm_data__data \dec_SHIFT_ROT_SHIFT_ROT__imm_data__data @@ -73919,7 +73955,7 @@ module \core connect \raw_opcode_in \dec_SHIFT_ROT_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:43151.11-43158.4" + attribute \src "libresoc.v:43199.11-43206.4" cell \dec_SPR \dec_SPR connect \SPR__fn_unit \dec_SPR_SPR__fn_unit connect \SPR__insn \dec_SPR_SPR__insn @@ -73929,7 +73965,7 @@ module \core connect \raw_opcode_in \dec_SPR_raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:43159.8-43177.4" + attribute \src "libresoc.v:43207.8-43225.4" cell \fast \fast connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -73950,7 +73986,7 @@ module \core connect \src2__ren \fast_src2__ren end attribute \module_not_derived 1 - attribute \src "libresoc.v:43178.7-43509.4" + attribute \src "libresoc.v:43226.7-43557.4" cell \fus \fus connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -74284,7 +74320,7 @@ module \core connect \xer_so_ok$131 \fus_xer_so_ok$143 end attribute \module_not_derived 1 - attribute \src "libresoc.v:43510.9-43528.4" + attribute \src "libresoc.v:43558.9-43576.4" cell \int \int connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -74305,7 +74341,7 @@ module \core connect \src3__ren \int_src3__ren end attribute \module_not_derived 1 - attribute \src "libresoc.v:43529.6-43561.4" + attribute \src "libresoc.v:43577.6-43609.4" cell \l0 \l0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -74340,98 +74376,98 @@ module \core connect \wb_dcache_en \wb_dcache_en end attribute \module_not_derived 1 - attribute \src "libresoc.v:43562.18-43566.4" + attribute \src "libresoc.v:43610.18-43614.4" cell \rdpick_CR_cr_a \rdpick_CR_cr_a connect \en_o \rdpick_CR_cr_a_en_o connect \i \rdpick_CR_cr_a_i connect \o \rdpick_CR_cr_a_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43567.18-43571.4" + attribute \src "libresoc.v:43615.18-43619.4" cell \rdpick_CR_cr_b \rdpick_CR_cr_b connect \en_o \rdpick_CR_cr_b_en_o connect \i \rdpick_CR_cr_b_i connect \o \rdpick_CR_cr_b_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43572.18-43576.4" + attribute \src "libresoc.v:43620.18-43624.4" cell \rdpick_CR_cr_c \rdpick_CR_cr_c connect \en_o \rdpick_CR_cr_c_en_o connect \i \rdpick_CR_cr_c_i connect \o \rdpick_CR_cr_c_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43577.21-43581.4" + attribute \src "libresoc.v:43625.21-43629.4" cell \rdpick_CR_full_cr \rdpick_CR_full_cr connect \en_o \rdpick_CR_full_cr_en_o connect \i \rdpick_CR_full_cr_i connect \o \rdpick_CR_full_cr_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43582.21-43586.4" + attribute \src "libresoc.v:43630.21-43634.4" cell \rdpick_FAST_fast1 \rdpick_FAST_fast1 connect \en_o \rdpick_FAST_fast1_en_o connect \i \rdpick_FAST_fast1_i connect \o \rdpick_FAST_fast1_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43587.21-43591.4" + attribute \src "libresoc.v:43635.21-43639.4" cell \rdpick_FAST_fast2 \rdpick_FAST_fast2 connect \en_o \rdpick_FAST_fast2_en_o connect \i \rdpick_FAST_fast2_i connect \o \rdpick_FAST_fast2_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43592.17-43596.4" + attribute \src "libresoc.v:43640.17-43644.4" cell \rdpick_INT_ra \rdpick_INT_ra connect \en_o \rdpick_INT_ra_en_o connect \i \rdpick_INT_ra_i connect \o \rdpick_INT_ra_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43597.17-43601.4" + attribute \src "libresoc.v:43645.17-43649.4" cell \rdpick_INT_rb \rdpick_INT_rb connect \en_o \rdpick_INT_rb_en_o connect \i \rdpick_INT_rb_i connect \o \rdpick_INT_rb_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43602.17-43606.4" + attribute \src "libresoc.v:43650.17-43654.4" cell \rdpick_INT_rc \rdpick_INT_rc connect \en_o \rdpick_INT_rc_en_o connect \i \rdpick_INT_rc_i connect \o \rdpick_INT_rc_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43607.19-43611.4" + attribute \src "libresoc.v:43655.19-43659.4" cell \rdpick_SPR_spr1 \rdpick_SPR_spr1 connect \en_o \rdpick_SPR_spr1_en_o connect \i \rdpick_SPR_spr1_i connect \o \rdpick_SPR_spr1_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43612.21-43616.4" + attribute \src "libresoc.v:43660.21-43664.4" cell \rdpick_XER_xer_ca \rdpick_XER_xer_ca connect \en_o \rdpick_XER_xer_ca_en_o connect \i \rdpick_XER_xer_ca_i connect \o \rdpick_XER_xer_ca_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43617.21-43621.4" + attribute \src "libresoc.v:43665.21-43669.4" cell \rdpick_XER_xer_ov \rdpick_XER_xer_ov connect \en_o \rdpick_XER_xer_ov_en_o connect \i \rdpick_XER_xer_ov_i connect \o \rdpick_XER_xer_ov_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43622.21-43626.4" + attribute \src "libresoc.v:43670.21-43674.4" cell \rdpick_XER_xer_so \rdpick_XER_xer_so connect \en_o \rdpick_XER_xer_so_en_o connect \i \rdpick_XER_xer_so_i connect \o \rdpick_XER_xer_so_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43627.7-43636.4" + attribute \src "libresoc.v:43675.7-43684.4" cell \spr \spr connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -74443,7 +74479,7 @@ module \core connect \spr1__wen \spr_spr1__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:43637.9-43654.4" + attribute \src "libresoc.v:43685.9-43702.4" cell \state \state connect \cia__data_o \cia__data_o connect \cia__ren \cia__ren @@ -74463,77 +74499,77 @@ module \core connect \wen$5 \state_wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:43655.18-43659.4" + attribute \src "libresoc.v:43703.18-43707.4" cell \wrpick_CR_cr_a \wrpick_CR_cr_a connect \en_o \wrpick_CR_cr_a_en_o connect \i \wrpick_CR_cr_a_i connect \o \wrpick_CR_cr_a_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43660.21-43664.4" + attribute \src "libresoc.v:43708.21-43712.4" cell \wrpick_CR_full_cr \wrpick_CR_full_cr connect \en_o \wrpick_CR_full_cr_en_o connect \i \wrpick_CR_full_cr_i connect \o \wrpick_CR_full_cr_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43665.21-43669.4" + attribute \src "libresoc.v:43713.21-43717.4" cell \wrpick_FAST_fast1 \wrpick_FAST_fast1 connect \en_o \wrpick_FAST_fast1_en_o connect \i \wrpick_FAST_fast1_i connect \o \wrpick_FAST_fast1_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43670.16-43674.4" + attribute \src "libresoc.v:43718.16-43722.4" cell \wrpick_INT_o \wrpick_INT_o connect \en_o \wrpick_INT_o_en_o connect \i \wrpick_INT_o_i connect \o \wrpick_INT_o_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43675.19-43679.4" + attribute \src "libresoc.v:43723.19-43727.4" cell \wrpick_SPR_spr1 \wrpick_SPR_spr1 connect \en_o \wrpick_SPR_spr1_en_o connect \i \wrpick_SPR_spr1_i connect \o \wrpick_SPR_spr1_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43680.20-43684.4" + attribute \src "libresoc.v:43728.20-43732.4" cell \wrpick_STATE_msr \wrpick_STATE_msr connect \en_o \wrpick_STATE_msr_en_o connect \i \wrpick_STATE_msr_i connect \o \wrpick_STATE_msr_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43685.20-43689.4" + attribute \src "libresoc.v:43733.20-43737.4" cell \wrpick_STATE_nia \wrpick_STATE_nia connect \en_o \wrpick_STATE_nia_en_o connect \i \wrpick_STATE_nia_i connect \o \wrpick_STATE_nia_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43690.21-43694.4" + attribute \src "libresoc.v:43738.21-43742.4" cell \wrpick_XER_xer_ca \wrpick_XER_xer_ca connect \en_o \wrpick_XER_xer_ca_en_o connect \i \wrpick_XER_xer_ca_i connect \o \wrpick_XER_xer_ca_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43695.21-43699.4" + attribute \src "libresoc.v:43743.21-43747.4" cell \wrpick_XER_xer_ov \wrpick_XER_xer_ov connect \en_o \wrpick_XER_xer_ov_en_o connect \i \wrpick_XER_xer_ov_i connect \o \wrpick_XER_xer_ov_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43700.21-43704.4" + attribute \src "libresoc.v:43748.21-43752.4" cell \wrpick_XER_xer_so \wrpick_XER_xer_so connect \en_o \wrpick_XER_xer_so_en_o connect \i \wrpick_XER_xer_so_i connect \o \wrpick_XER_xer_so_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:43705.7-43722.4" + attribute \src "libresoc.v:43753.7-43770.4" cell \xer \xer connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -74552,1207 +74588,1207 @@ module \core connect \wen$2 \xer_wen$171 connect \wen$4 \xer_wen$173 end - attribute \src "libresoc.v:36214.7-36214.20" - process $proc$libresoc.v:36214$2900 + attribute \src "libresoc.v:36262.7-36262.20" + process $proc$libresoc.v:36262$2900 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:38263.7-38263.30" - process $proc$libresoc.v:38263$2901 + attribute \src "libresoc.v:38311.7-38311.30" + process $proc$libresoc.v:38311$2901 assign { } { } assign $1\core_terminate_o[0:0] 1'0 sync always sync init update \core_terminate_o $1\core_terminate_o[0:0] end - attribute \src "libresoc.v:38276.13-38276.27" - process $proc$libresoc.v:38276$2902 + attribute \src "libresoc.v:38324.13-38324.27" + process $proc$libresoc.v:38324$2902 assign { } { } assign $1\counter[1:0] 2'00 sync always sync init update \counter $1\counter[1:0] end - attribute \src "libresoc.v:39443.7-39443.34" - process $proc$libresoc.v:39443$2903 + attribute \src "libresoc.v:39491.7-39491.34" + process $proc$libresoc.v:39491$2903 assign { } { } assign $1\dp_CR_cr_a_branch0_1[0:0] 1'0 sync always sync init update \dp_CR_cr_a_branch0_1 $1\dp_CR_cr_a_branch0_1[0:0] end - attribute \src "libresoc.v:39447.7-39447.30" - process $proc$libresoc.v:39447$2904 + attribute \src "libresoc.v:39495.7-39495.30" + process $proc$libresoc.v:39495$2904 assign { } { } assign $1\dp_CR_cr_a_cr0_0[0:0] 1'0 sync always sync init update \dp_CR_cr_a_cr0_0 $1\dp_CR_cr_a_cr0_0[0:0] end - attribute \src "libresoc.v:39451.7-39451.30" - process $proc$libresoc.v:39451$2905 + attribute \src "libresoc.v:39499.7-39499.30" + process $proc$libresoc.v:39499$2905 assign { } { } assign $1\dp_CR_cr_b_cr0_0[0:0] 1'0 sync always sync init update \dp_CR_cr_b_cr0_0 $1\dp_CR_cr_b_cr0_0[0:0] end - attribute \src "libresoc.v:39455.7-39455.30" - process $proc$libresoc.v:39455$2906 + attribute \src "libresoc.v:39503.7-39503.30" + process $proc$libresoc.v:39503$2906 assign { } { } assign $1\dp_CR_cr_c_cr0_0[0:0] 1'0 sync always sync init update \dp_CR_cr_c_cr0_0 $1\dp_CR_cr_c_cr0_0[0:0] end - attribute \src "libresoc.v:39459.7-39459.33" - process $proc$libresoc.v:39459$2907 + attribute \src "libresoc.v:39507.7-39507.33" + process $proc$libresoc.v:39507$2907 assign { } { } assign $1\dp_CR_full_cr_cr0_0[0:0] 1'0 sync always sync init update \dp_CR_full_cr_cr0_0 $1\dp_CR_full_cr_cr0_0[0:0] end - attribute \src "libresoc.v:39463.7-39463.37" - process $proc$libresoc.v:39463$2908 + attribute \src "libresoc.v:39511.7-39511.37" + process $proc$libresoc.v:39511$2908 assign { } { } assign $1\dp_FAST_fast1_branch0_0[0:0] 1'0 sync always sync init update \dp_FAST_fast1_branch0_0 $1\dp_FAST_fast1_branch0_0[0:0] end - attribute \src "libresoc.v:39467.7-39467.34" - process $proc$libresoc.v:39467$2909 + attribute \src "libresoc.v:39515.7-39515.34" + process $proc$libresoc.v:39515$2909 assign { } { } assign $1\dp_FAST_fast1_spr0_2[0:0] 1'0 sync always sync init update \dp_FAST_fast1_spr0_2 $1\dp_FAST_fast1_spr0_2[0:0] end - attribute \src "libresoc.v:39471.7-39471.35" - process $proc$libresoc.v:39471$2910 + attribute \src "libresoc.v:39519.7-39519.35" + process $proc$libresoc.v:39519$2910 assign { } { } assign $1\dp_FAST_fast1_trap0_1[0:0] 1'0 sync always sync init update \dp_FAST_fast1_trap0_1 $1\dp_FAST_fast1_trap0_1[0:0] end - attribute \src "libresoc.v:39475.7-39475.37" - process $proc$libresoc.v:39475$2911 + attribute \src "libresoc.v:39523.7-39523.37" + process $proc$libresoc.v:39523$2911 assign { } { } assign $1\dp_FAST_fast2_branch0_0[0:0] 1'0 sync always sync init update \dp_FAST_fast2_branch0_0 $1\dp_FAST_fast2_branch0_0[0:0] end - attribute \src "libresoc.v:39479.7-39479.35" - process $proc$libresoc.v:39479$2912 + attribute \src "libresoc.v:39527.7-39527.35" + process $proc$libresoc.v:39527$2912 assign { } { } assign $1\dp_FAST_fast2_trap0_1[0:0] 1'0 sync always sync init update \dp_FAST_fast2_trap0_1 $1\dp_FAST_fast2_trap0_1[0:0] end - attribute \src "libresoc.v:39483.7-39483.30" - process $proc$libresoc.v:39483$2913 + attribute \src "libresoc.v:39531.7-39531.30" + process $proc$libresoc.v:39531$2913 assign { } { } assign $1\dp_INT_ra_alu0_0[0:0] 1'0 sync always sync init update \dp_INT_ra_alu0_0 $1\dp_INT_ra_alu0_0[0:0] end - attribute \src "libresoc.v:39487.7-39487.29" - process $proc$libresoc.v:39487$2914 + attribute \src "libresoc.v:39535.7-39535.29" + process $proc$libresoc.v:39535$2914 assign { } { } assign $1\dp_INT_ra_cr0_1[0:0] 1'0 sync always sync init update \dp_INT_ra_cr0_1 $1\dp_INT_ra_cr0_1[0:0] end - attribute \src "libresoc.v:39491.7-39491.30" - process $proc$libresoc.v:39491$2915 + attribute \src "libresoc.v:39539.7-39539.30" + process $proc$libresoc.v:39539$2915 assign { } { } assign $1\dp_INT_ra_div0_5[0:0] 1'0 sync always sync init update \dp_INT_ra_div0_5 $1\dp_INT_ra_div0_5[0:0] end - attribute \src "libresoc.v:39495.7-39495.31" - process $proc$libresoc.v:39495$2916 + attribute \src "libresoc.v:39543.7-39543.31" + process $proc$libresoc.v:39543$2916 assign { } { } assign $1\dp_INT_ra_ldst0_8[0:0] 1'0 sync always sync init update \dp_INT_ra_ldst0_8 $1\dp_INT_ra_ldst0_8[0:0] end - attribute \src "libresoc.v:39499.7-39499.34" - process $proc$libresoc.v:39499$2917 + attribute \src "libresoc.v:39547.7-39547.34" + process $proc$libresoc.v:39547$2917 assign { } { } assign $1\dp_INT_ra_logical0_3[0:0] 1'0 sync always sync init update \dp_INT_ra_logical0_3 $1\dp_INT_ra_logical0_3[0:0] end - attribute \src "libresoc.v:39503.7-39503.30" - process $proc$libresoc.v:39503$2918 + attribute \src "libresoc.v:39551.7-39551.30" + process $proc$libresoc.v:39551$2918 assign { } { } assign $1\dp_INT_ra_mul0_6[0:0] 1'0 sync always sync init update \dp_INT_ra_mul0_6 $1\dp_INT_ra_mul0_6[0:0] end - attribute \src "libresoc.v:39507.7-39507.35" - process $proc$libresoc.v:39507$2919 + attribute \src "libresoc.v:39555.7-39555.35" + process $proc$libresoc.v:39555$2919 assign { } { } assign $1\dp_INT_ra_shiftrot0_7[0:0] 1'0 sync always sync init update \dp_INT_ra_shiftrot0_7 $1\dp_INT_ra_shiftrot0_7[0:0] end - attribute \src "libresoc.v:39511.7-39511.30" - process $proc$libresoc.v:39511$2920 + attribute \src "libresoc.v:39559.7-39559.30" + process $proc$libresoc.v:39559$2920 assign { } { } assign $1\dp_INT_ra_spr0_4[0:0] 1'0 sync always sync init update \dp_INT_ra_spr0_4 $1\dp_INT_ra_spr0_4[0:0] end - attribute \src "libresoc.v:39515.7-39515.31" - process $proc$libresoc.v:39515$2921 + attribute \src "libresoc.v:39563.7-39563.31" + process $proc$libresoc.v:39563$2921 assign { } { } assign $1\dp_INT_ra_trap0_2[0:0] 1'0 sync always sync init update \dp_INT_ra_trap0_2 $1\dp_INT_ra_trap0_2[0:0] end - attribute \src "libresoc.v:39519.7-39519.30" - process $proc$libresoc.v:39519$2922 + attribute \src "libresoc.v:39567.7-39567.30" + process $proc$libresoc.v:39567$2922 assign { } { } assign $1\dp_INT_rb_alu0_0[0:0] 1'0 sync always sync init update \dp_INT_rb_alu0_0 $1\dp_INT_rb_alu0_0[0:0] end - attribute \src "libresoc.v:39523.7-39523.29" - process $proc$libresoc.v:39523$2923 + attribute \src "libresoc.v:39571.7-39571.29" + process $proc$libresoc.v:39571$2923 assign { } { } assign $1\dp_INT_rb_cr0_1[0:0] 1'0 sync always sync init update \dp_INT_rb_cr0_1 $1\dp_INT_rb_cr0_1[0:0] end - attribute \src "libresoc.v:39527.7-39527.30" - process $proc$libresoc.v:39527$2924 + attribute \src "libresoc.v:39575.7-39575.30" + process $proc$libresoc.v:39575$2924 assign { } { } assign $1\dp_INT_rb_div0_4[0:0] 1'0 sync always sync init update \dp_INT_rb_div0_4 $1\dp_INT_rb_div0_4[0:0] end - attribute \src "libresoc.v:39531.7-39531.31" - process $proc$libresoc.v:39531$2925 + attribute \src "libresoc.v:39579.7-39579.31" + process $proc$libresoc.v:39579$2925 assign { } { } assign $1\dp_INT_rb_ldst0_7[0:0] 1'0 sync always sync init update \dp_INT_rb_ldst0_7 $1\dp_INT_rb_ldst0_7[0:0] end - attribute \src "libresoc.v:39535.7-39535.34" - process $proc$libresoc.v:39535$2926 + attribute \src "libresoc.v:39583.7-39583.34" + process $proc$libresoc.v:39583$2926 assign { } { } assign $1\dp_INT_rb_logical0_3[0:0] 1'0 sync always sync init update \dp_INT_rb_logical0_3 $1\dp_INT_rb_logical0_3[0:0] end - attribute \src "libresoc.v:39539.7-39539.30" - process $proc$libresoc.v:39539$2927 + attribute \src "libresoc.v:39587.7-39587.30" + process $proc$libresoc.v:39587$2927 assign { } { } assign $1\dp_INT_rb_mul0_5[0:0] 1'0 sync always sync init update \dp_INT_rb_mul0_5 $1\dp_INT_rb_mul0_5[0:0] end - attribute \src "libresoc.v:39543.7-39543.35" - process $proc$libresoc.v:39543$2928 + attribute \src "libresoc.v:39591.7-39591.35" + process $proc$libresoc.v:39591$2928 assign { } { } assign $1\dp_INT_rb_shiftrot0_6[0:0] 1'0 sync always sync init update \dp_INT_rb_shiftrot0_6 $1\dp_INT_rb_shiftrot0_6[0:0] end - attribute \src "libresoc.v:39547.7-39547.31" - process $proc$libresoc.v:39547$2929 + attribute \src "libresoc.v:39595.7-39595.31" + process $proc$libresoc.v:39595$2929 assign { } { } assign $1\dp_INT_rb_trap0_2[0:0] 1'0 sync always sync init update \dp_INT_rb_trap0_2 $1\dp_INT_rb_trap0_2[0:0] end - attribute \src "libresoc.v:39551.7-39551.31" - process $proc$libresoc.v:39551$2930 + attribute \src "libresoc.v:39599.7-39599.31" + process $proc$libresoc.v:39599$2930 assign { } { } assign $1\dp_INT_rc_ldst0_1[0:0] 1'0 sync always sync init update \dp_INT_rc_ldst0_1 $1\dp_INT_rc_ldst0_1[0:0] end - attribute \src "libresoc.v:39555.7-39555.35" - process $proc$libresoc.v:39555$2931 + attribute \src "libresoc.v:39603.7-39603.35" + process $proc$libresoc.v:39603$2931 assign { } { } assign $1\dp_INT_rc_shiftrot0_0[0:0] 1'0 sync always sync init update \dp_INT_rc_shiftrot0_0 $1\dp_INT_rc_shiftrot0_0[0:0] end - attribute \src "libresoc.v:39559.7-39559.32" - process $proc$libresoc.v:39559$2932 + attribute \src "libresoc.v:39607.7-39607.32" + process $proc$libresoc.v:39607$2932 assign { } { } assign $1\dp_SPR_spr1_spr0_0[0:0] 1'0 sync always sync init update \dp_SPR_spr1_spr0_0 $1\dp_SPR_spr1_spr0_0[0:0] end - attribute \src "libresoc.v:39563.7-39563.34" - process $proc$libresoc.v:39563$2933 + attribute \src "libresoc.v:39611.7-39611.34" + process $proc$libresoc.v:39611$2933 assign { } { } assign $1\dp_XER_xer_ca_alu0_0[0:0] 1'0 sync always sync init update \dp_XER_xer_ca_alu0_0 $1\dp_XER_xer_ca_alu0_0[0:0] end - attribute \src "libresoc.v:39567.7-39567.39" - process $proc$libresoc.v:39567$2934 + attribute \src "libresoc.v:39615.7-39615.39" + process $proc$libresoc.v:39615$2934 assign { } { } assign $1\dp_XER_xer_ca_shiftrot0_2[0:0] 1'0 sync always sync init update \dp_XER_xer_ca_shiftrot0_2 $1\dp_XER_xer_ca_shiftrot0_2[0:0] end - attribute \src "libresoc.v:39571.7-39571.34" - process $proc$libresoc.v:39571$2935 + attribute \src "libresoc.v:39619.7-39619.34" + process $proc$libresoc.v:39619$2935 assign { } { } assign $1\dp_XER_xer_ca_spr0_1[0:0] 1'0 sync always sync init update \dp_XER_xer_ca_spr0_1 $1\dp_XER_xer_ca_spr0_1[0:0] end - attribute \src "libresoc.v:39575.7-39575.34" - process $proc$libresoc.v:39575$2936 + attribute \src "libresoc.v:39623.7-39623.34" + process $proc$libresoc.v:39623$2936 assign { } { } assign $1\dp_XER_xer_ov_spr0_0[0:0] 1'0 sync always sync init update \dp_XER_xer_ov_spr0_0 $1\dp_XER_xer_ov_spr0_0[0:0] end - attribute \src "libresoc.v:39579.7-39579.34" - process $proc$libresoc.v:39579$2937 + attribute \src "libresoc.v:39627.7-39627.34" + process $proc$libresoc.v:39627$2937 assign { } { } assign $1\dp_XER_xer_so_alu0_0[0:0] 1'0 sync always sync init update \dp_XER_xer_so_alu0_0 $1\dp_XER_xer_so_alu0_0[0:0] end - attribute \src "libresoc.v:39583.7-39583.34" - process $proc$libresoc.v:39583$2938 + attribute \src "libresoc.v:39631.7-39631.34" + process $proc$libresoc.v:39631$2938 assign { } { } assign $1\dp_XER_xer_so_div0_3[0:0] 1'0 sync always sync init update \dp_XER_xer_so_div0_3 $1\dp_XER_xer_so_div0_3[0:0] end - attribute \src "libresoc.v:39587.7-39587.38" - process $proc$libresoc.v:39587$2939 + attribute \src "libresoc.v:39635.7-39635.38" + process $proc$libresoc.v:39635$2939 assign { } { } assign $1\dp_XER_xer_so_logical0_1[0:0] 1'0 sync always sync init update \dp_XER_xer_so_logical0_1 $1\dp_XER_xer_so_logical0_1[0:0] end - attribute \src "libresoc.v:39591.7-39591.34" - process $proc$libresoc.v:39591$2940 + attribute \src "libresoc.v:39639.7-39639.34" + process $proc$libresoc.v:39639$2940 assign { } { } assign $1\dp_XER_xer_so_mul0_4[0:0] 1'0 sync always sync init update \dp_XER_xer_so_mul0_4 $1\dp_XER_xer_so_mul0_4[0:0] end - attribute \src "libresoc.v:39595.7-39595.39" - process $proc$libresoc.v:39595$2941 + attribute \src "libresoc.v:39643.7-39643.39" + process $proc$libresoc.v:39643$2941 assign { } { } assign $1\dp_XER_xer_so_shiftrot0_5[0:0] 1'0 sync always sync init update \dp_XER_xer_so_shiftrot0_5 $1\dp_XER_xer_so_shiftrot0_5[0:0] end - attribute \src "libresoc.v:39599.7-39599.34" - process $proc$libresoc.v:39599$2942 + attribute \src "libresoc.v:39647.7-39647.34" + process $proc$libresoc.v:39647$2942 assign { } { } assign $1\dp_XER_xer_so_spr0_2[0:0] 1'0 sync always sync init update \dp_XER_xer_so_spr0_2 $1\dp_XER_xer_so_spr0_2[0:0] end - attribute \src "libresoc.v:41724.7-41724.25" - process $proc$libresoc.v:41724$2943 + attribute \src "libresoc.v:41772.7-41772.25" + process $proc$libresoc.v:41772$2943 assign { } { } assign $1\wr_pick_dly[0:0] 1'0 sync always sync init update \wr_pick_dly $1\wr_pick_dly[0:0] end - attribute \src "libresoc.v:41726.7-41726.32" - process $proc$libresoc.v:41726$2944 + attribute \src "libresoc.v:41774.7-41774.32" + process $proc$libresoc.v:41774$2944 assign { } { } assign $0\wr_pick_dly$1010[0:0]$2945 1'0 sync always sync init update \wr_pick_dly$1010 $0\wr_pick_dly$1010[0:0]$2945 end - attribute \src "libresoc.v:41730.7-41730.32" - process $proc$libresoc.v:41730$2946 + attribute \src "libresoc.v:41778.7-41778.32" + process $proc$libresoc.v:41778$2946 assign { } { } assign $0\wr_pick_dly$1031[0:0]$2947 1'0 sync always sync init update \wr_pick_dly$1031 $0\wr_pick_dly$1031[0:0]$2947 end - attribute \src "libresoc.v:41734.7-41734.32" - process $proc$libresoc.v:41734$2948 + attribute \src "libresoc.v:41782.7-41782.32" + process $proc$libresoc.v:41782$2948 assign { } { } assign $0\wr_pick_dly$1049[0:0]$2949 1'0 sync always sync init update \wr_pick_dly$1049 $0\wr_pick_dly$1049[0:0]$2949 end - attribute \src "libresoc.v:41738.7-41738.32" - process $proc$libresoc.v:41738$2950 + attribute \src "libresoc.v:41786.7-41786.32" + process $proc$libresoc.v:41786$2950 assign { } { } assign $0\wr_pick_dly$1071[0:0]$2951 1'0 sync always sync init update \wr_pick_dly$1071 $0\wr_pick_dly$1071[0:0]$2951 end - attribute \src "libresoc.v:41742.7-41742.32" - process $proc$libresoc.v:41742$2952 + attribute \src "libresoc.v:41790.7-41790.32" + process $proc$libresoc.v:41790$2952 assign { } { } assign $0\wr_pick_dly$1091[0:0]$2953 1'0 sync always sync init update \wr_pick_dly$1091 $0\wr_pick_dly$1091[0:0]$2953 end - attribute \src "libresoc.v:41746.7-41746.32" - process $proc$libresoc.v:41746$2954 + attribute \src "libresoc.v:41794.7-41794.32" + process $proc$libresoc.v:41794$2954 assign { } { } assign $0\wr_pick_dly$1111[0:0]$2955 1'0 sync always sync init update \wr_pick_dly$1111 $0\wr_pick_dly$1111[0:0]$2955 end - attribute \src "libresoc.v:41750.7-41750.32" - process $proc$libresoc.v:41750$2956 + attribute \src "libresoc.v:41798.7-41798.32" + process $proc$libresoc.v:41798$2956 assign { } { } assign $0\wr_pick_dly$1130[0:0]$2957 1'0 sync always sync init update \wr_pick_dly$1130 $0\wr_pick_dly$1130[0:0]$2957 end - attribute \src "libresoc.v:41754.7-41754.32" - process $proc$libresoc.v:41754$2958 + attribute \src "libresoc.v:41802.7-41802.32" + process $proc$libresoc.v:41802$2958 assign { } { } assign $0\wr_pick_dly$1148[0:0]$2959 1'0 sync always sync init update \wr_pick_dly$1148 $0\wr_pick_dly$1148[0:0]$2959 end - attribute \src "libresoc.v:41758.7-41758.32" - process $proc$libresoc.v:41758$2960 + attribute \src "libresoc.v:41806.7-41806.32" + process $proc$libresoc.v:41806$2960 assign { } { } assign $0\wr_pick_dly$1222[0:0]$2961 1'0 sync always sync init update \wr_pick_dly$1222 $0\wr_pick_dly$1222[0:0]$2961 end - attribute \src "libresoc.v:41762.7-41762.32" - process $proc$libresoc.v:41762$2962 + attribute \src "libresoc.v:41810.7-41810.32" + process $proc$libresoc.v:41810$2962 assign { } { } assign $0\wr_pick_dly$1250[0:0]$2963 1'0 sync always sync init update \wr_pick_dly$1250 $0\wr_pick_dly$1250[0:0]$2963 end - attribute \src "libresoc.v:41766.7-41766.32" - process $proc$libresoc.v:41766$2964 + attribute \src "libresoc.v:41814.7-41814.32" + process $proc$libresoc.v:41814$2964 assign { } { } assign $0\wr_pick_dly$1270[0:0]$2965 1'0 sync always sync init update \wr_pick_dly$1270 $0\wr_pick_dly$1270[0:0]$2965 end - attribute \src "libresoc.v:41770.7-41770.32" - process $proc$libresoc.v:41770$2966 + attribute \src "libresoc.v:41818.7-41818.32" + process $proc$libresoc.v:41818$2966 assign { } { } assign $0\wr_pick_dly$1290[0:0]$2967 1'0 sync always sync init update \wr_pick_dly$1290 $0\wr_pick_dly$1290[0:0]$2967 end - attribute \src "libresoc.v:41774.7-41774.32" - process $proc$libresoc.v:41774$2968 + attribute \src "libresoc.v:41822.7-41822.32" + process $proc$libresoc.v:41822$2968 assign { } { } assign $0\wr_pick_dly$1310[0:0]$2969 1'0 sync always sync init update \wr_pick_dly$1310 $0\wr_pick_dly$1310[0:0]$2969 end - attribute \src "libresoc.v:41778.7-41778.32" - process $proc$libresoc.v:41778$2970 + attribute \src "libresoc.v:41826.7-41826.32" + process $proc$libresoc.v:41826$2970 assign { } { } assign $0\wr_pick_dly$1330[0:0]$2971 1'0 sync always sync init update \wr_pick_dly$1330 $0\wr_pick_dly$1330[0:0]$2971 end - attribute \src "libresoc.v:41782.7-41782.32" - process $proc$libresoc.v:41782$2972 + attribute \src "libresoc.v:41830.7-41830.32" + process $proc$libresoc.v:41830$2972 assign { } { } assign $0\wr_pick_dly$1350[0:0]$2973 1'0 sync always sync init update \wr_pick_dly$1350 $0\wr_pick_dly$1350[0:0]$2973 end - attribute \src "libresoc.v:41786.7-41786.32" - process $proc$libresoc.v:41786$2974 + attribute \src "libresoc.v:41834.7-41834.32" + process $proc$libresoc.v:41834$2974 assign { } { } assign $0\wr_pick_dly$1397[0:0]$2975 1'0 sync always sync init update \wr_pick_dly$1397 $0\wr_pick_dly$1397[0:0]$2975 end - attribute \src "libresoc.v:41790.7-41790.32" - process $proc$libresoc.v:41790$2976 + attribute \src "libresoc.v:41838.7-41838.32" + process $proc$libresoc.v:41838$2976 assign { } { } assign $0\wr_pick_dly$1413[0:0]$2977 1'0 sync always sync init update \wr_pick_dly$1413 $0\wr_pick_dly$1413[0:0]$2977 end - attribute \src "libresoc.v:41794.7-41794.32" - process $proc$libresoc.v:41794$2978 + attribute \src "libresoc.v:41842.7-41842.32" + process $proc$libresoc.v:41842$2978 assign { } { } assign $0\wr_pick_dly$1429[0:0]$2979 1'0 sync always sync init update \wr_pick_dly$1429 $0\wr_pick_dly$1429[0:0]$2979 end - attribute \src "libresoc.v:41798.7-41798.32" - process $proc$libresoc.v:41798$2980 + attribute \src "libresoc.v:41846.7-41846.32" + process $proc$libresoc.v:41846$2980 assign { } { } assign $0\wr_pick_dly$1463[0:0]$2981 1'0 sync always sync init update \wr_pick_dly$1463 $0\wr_pick_dly$1463[0:0]$2981 end - attribute \src "libresoc.v:41802.7-41802.32" - process $proc$libresoc.v:41802$2982 + attribute \src "libresoc.v:41850.7-41850.32" + process $proc$libresoc.v:41850$2982 assign { } { } assign $0\wr_pick_dly$1479[0:0]$2983 1'0 sync always sync init update \wr_pick_dly$1479 $0\wr_pick_dly$1479[0:0]$2983 end - attribute \src "libresoc.v:41806.7-41806.32" - process $proc$libresoc.v:41806$2984 + attribute \src "libresoc.v:41854.7-41854.32" + process $proc$libresoc.v:41854$2984 assign { } { } assign $0\wr_pick_dly$1495[0:0]$2985 1'0 sync always sync init update \wr_pick_dly$1495 $0\wr_pick_dly$1495[0:0]$2985 end - attribute \src "libresoc.v:41810.7-41810.32" - process $proc$libresoc.v:41810$2986 + attribute \src "libresoc.v:41858.7-41858.32" + process $proc$libresoc.v:41858$2986 assign { } { } assign $0\wr_pick_dly$1511[0:0]$2987 1'0 sync always sync init update \wr_pick_dly$1511 $0\wr_pick_dly$1511[0:0]$2987 end - attribute \src "libresoc.v:41814.7-41814.32" - process $proc$libresoc.v:41814$2988 + attribute \src "libresoc.v:41862.7-41862.32" + process $proc$libresoc.v:41862$2988 assign { } { } assign $0\wr_pick_dly$1547[0:0]$2989 1'0 sync always sync init update \wr_pick_dly$1547 $0\wr_pick_dly$1547[0:0]$2989 end - attribute \src "libresoc.v:41818.7-41818.32" - process $proc$libresoc.v:41818$2990 + attribute \src "libresoc.v:41866.7-41866.32" + process $proc$libresoc.v:41866$2990 assign { } { } assign $0\wr_pick_dly$1563[0:0]$2991 1'0 sync always sync init update \wr_pick_dly$1563 $0\wr_pick_dly$1563[0:0]$2991 end - attribute \src "libresoc.v:41822.7-41822.32" - process $proc$libresoc.v:41822$2992 + attribute \src "libresoc.v:41870.7-41870.32" + process $proc$libresoc.v:41870$2992 assign { } { } assign $0\wr_pick_dly$1579[0:0]$2993 1'0 sync always sync init update \wr_pick_dly$1579 $0\wr_pick_dly$1579[0:0]$2993 end - attribute \src "libresoc.v:41826.7-41826.32" - process $proc$libresoc.v:41826$2994 + attribute \src "libresoc.v:41874.7-41874.32" + process $proc$libresoc.v:41874$2994 assign { } { } assign $0\wr_pick_dly$1595[0:0]$2995 1'0 sync always sync init update \wr_pick_dly$1595 $0\wr_pick_dly$1595[0:0]$2995 end - attribute \src "libresoc.v:41830.7-41830.32" - process $proc$libresoc.v:41830$2996 + attribute \src "libresoc.v:41878.7-41878.32" + process $proc$libresoc.v:41878$2996 assign { } { } assign $0\wr_pick_dly$1637[0:0]$2997 1'0 sync always sync init update \wr_pick_dly$1637 $0\wr_pick_dly$1637[0:0]$2997 end - attribute \src "libresoc.v:41834.7-41834.32" - process $proc$libresoc.v:41834$2998 + attribute \src "libresoc.v:41882.7-41882.32" + process $proc$libresoc.v:41882$2998 assign { } { } assign $0\wr_pick_dly$1656[0:0]$2999 1'0 sync always sync init update \wr_pick_dly$1656 $0\wr_pick_dly$1656[0:0]$2999 end - attribute \src "libresoc.v:41838.7-41838.32" - process $proc$libresoc.v:41838$3000 + attribute \src "libresoc.v:41886.7-41886.32" + process $proc$libresoc.v:41886$3000 assign { } { } assign $0\wr_pick_dly$1672[0:0]$3001 1'0 sync always sync init update \wr_pick_dly$1672 $0\wr_pick_dly$1672[0:0]$3001 end - attribute \src "libresoc.v:41842.7-41842.32" - process $proc$libresoc.v:41842$3002 + attribute \src "libresoc.v:41890.7-41890.32" + process $proc$libresoc.v:41890$3002 assign { } { } assign $0\wr_pick_dly$1688[0:0]$3003 1'0 sync always sync init update \wr_pick_dly$1688 $0\wr_pick_dly$1688[0:0]$3003 end - attribute \src "libresoc.v:41846.7-41846.32" - process $proc$libresoc.v:41846$3004 + attribute \src "libresoc.v:41894.7-41894.32" + process $proc$libresoc.v:41894$3004 assign { } { } assign $0\wr_pick_dly$1704[0:0]$3005 1'0 sync always sync init update \wr_pick_dly$1704 $0\wr_pick_dly$1704[0:0]$3005 end - attribute \src "libresoc.v:41850.7-41850.32" - process $proc$libresoc.v:41850$3006 + attribute \src "libresoc.v:41898.7-41898.32" + process $proc$libresoc.v:41898$3006 assign { } { } assign $0\wr_pick_dly$1748[0:0]$3007 1'0 sync always sync init update \wr_pick_dly$1748 $0\wr_pick_dly$1748[0:0]$3007 end - attribute \src "libresoc.v:41854.7-41854.32" - process $proc$libresoc.v:41854$3008 + attribute \src "libresoc.v:41902.7-41902.32" + process $proc$libresoc.v:41902$3008 assign { } { } assign $0\wr_pick_dly$1764[0:0]$3009 1'0 sync always sync init update \wr_pick_dly$1764 $0\wr_pick_dly$1764[0:0]$3009 end - attribute \src "libresoc.v:41858.7-41858.32" - process $proc$libresoc.v:41858$3010 + attribute \src "libresoc.v:41906.7-41906.32" + process $proc$libresoc.v:41906$3010 assign { } { } assign $0\wr_pick_dly$1788[0:0]$3011 1'0 sync always sync init update \wr_pick_dly$1788 $0\wr_pick_dly$1788[0:0]$3011 end - attribute \src "libresoc.v:41862.7-41862.32" - process $proc$libresoc.v:41862$3012 + attribute \src "libresoc.v:41910.7-41910.32" + process $proc$libresoc.v:41910$3012 assign { } { } assign $0\wr_pick_dly$1808[0:0]$3013 1'0 sync always sync init update \wr_pick_dly$1808 $0\wr_pick_dly$1808[0:0]$3013 end - attribute \src "libresoc.v:41866.7-41866.31" - process $proc$libresoc.v:41866$3014 + attribute \src "libresoc.v:41914.7-41914.31" + process $proc$libresoc.v:41914$3014 assign { } { } assign $0\wr_pick_dly$991[0:0]$3015 1'0 sync always sync init update \wr_pick_dly$991 $0\wr_pick_dly$991[0:0]$3015 end - attribute \src "libresoc.v:42828.3-42829.51" - process $proc$libresoc.v:42828$2238 + attribute \src "libresoc.v:42876.3-42877.51" + process $proc$libresoc.v:42876$2238 assign { } { } assign $0\wr_pick_dly$1808[0:0]$2239 \wr_pick_dly$1808$next sync posedge \coresync_clk update \wr_pick_dly$1808 $0\wr_pick_dly$1808[0:0]$2239 end - attribute \src "libresoc.v:42830.3-42831.51" - process $proc$libresoc.v:42830$2240 + attribute \src "libresoc.v:42878.3-42879.51" + process $proc$libresoc.v:42878$2240 assign { } { } assign $0\wr_pick_dly$1788[0:0]$2241 \wr_pick_dly$1788$next sync posedge \coresync_clk update \wr_pick_dly$1788 $0\wr_pick_dly$1788[0:0]$2241 end - attribute \src "libresoc.v:42832.3-42833.51" - process $proc$libresoc.v:42832$2242 + attribute \src "libresoc.v:42880.3-42881.51" + process $proc$libresoc.v:42880$2242 assign { } { } assign $0\wr_pick_dly$1764[0:0]$2243 \wr_pick_dly$1764$next sync posedge \coresync_clk update \wr_pick_dly$1764 $0\wr_pick_dly$1764[0:0]$2243 end - attribute \src "libresoc.v:42834.3-42835.51" - process $proc$libresoc.v:42834$2244 + attribute \src "libresoc.v:42882.3-42883.51" + process $proc$libresoc.v:42882$2244 assign { } { } assign $0\wr_pick_dly$1748[0:0]$2245 \wr_pick_dly$1748$next sync posedge \coresync_clk update \wr_pick_dly$1748 $0\wr_pick_dly$1748[0:0]$2245 end - attribute \src "libresoc.v:42836.3-42837.51" - process $proc$libresoc.v:42836$2246 + attribute \src "libresoc.v:42884.3-42885.51" + process $proc$libresoc.v:42884$2246 assign { } { } assign $0\wr_pick_dly$1704[0:0]$2247 \wr_pick_dly$1704$next sync posedge \coresync_clk update \wr_pick_dly$1704 $0\wr_pick_dly$1704[0:0]$2247 end - attribute \src "libresoc.v:42838.3-42839.51" - process $proc$libresoc.v:42838$2248 + attribute \src "libresoc.v:42886.3-42887.51" + process $proc$libresoc.v:42886$2248 assign { } { } assign $0\wr_pick_dly$1688[0:0]$2249 \wr_pick_dly$1688$next sync posedge \coresync_clk update \wr_pick_dly$1688 $0\wr_pick_dly$1688[0:0]$2249 end - attribute \src "libresoc.v:42840.3-42841.51" - process $proc$libresoc.v:42840$2250 + attribute \src "libresoc.v:42888.3-42889.51" + process $proc$libresoc.v:42888$2250 assign { } { } assign $0\wr_pick_dly$1672[0:0]$2251 \wr_pick_dly$1672$next sync posedge \coresync_clk update \wr_pick_dly$1672 $0\wr_pick_dly$1672[0:0]$2251 end - attribute \src "libresoc.v:42842.3-42843.51" - process $proc$libresoc.v:42842$2252 + attribute \src "libresoc.v:42890.3-42891.51" + process $proc$libresoc.v:42890$2252 assign { } { } assign $0\wr_pick_dly$1656[0:0]$2253 \wr_pick_dly$1656$next sync posedge \coresync_clk update \wr_pick_dly$1656 $0\wr_pick_dly$1656[0:0]$2253 end - attribute \src "libresoc.v:42844.3-42845.51" - process $proc$libresoc.v:42844$2254 + attribute \src "libresoc.v:42892.3-42893.51" + process $proc$libresoc.v:42892$2254 assign { } { } assign $0\wr_pick_dly$1637[0:0]$2255 \wr_pick_dly$1637$next sync posedge \coresync_clk update \wr_pick_dly$1637 $0\wr_pick_dly$1637[0:0]$2255 end - attribute \src "libresoc.v:42846.3-42847.51" - process $proc$libresoc.v:42846$2256 + attribute \src "libresoc.v:42894.3-42895.51" + process $proc$libresoc.v:42894$2256 assign { } { } assign $0\wr_pick_dly$1595[0:0]$2257 \wr_pick_dly$1595$next sync posedge \coresync_clk update \wr_pick_dly$1595 $0\wr_pick_dly$1595[0:0]$2257 end - attribute \src "libresoc.v:42848.3-42849.51" - process $proc$libresoc.v:42848$2258 + attribute \src "libresoc.v:42896.3-42897.51" + process $proc$libresoc.v:42896$2258 assign { } { } assign $0\wr_pick_dly$1579[0:0]$2259 \wr_pick_dly$1579$next sync posedge \coresync_clk update \wr_pick_dly$1579 $0\wr_pick_dly$1579[0:0]$2259 end - attribute \src "libresoc.v:42850.3-42851.51" - process $proc$libresoc.v:42850$2260 + attribute \src "libresoc.v:42898.3-42899.51" + process $proc$libresoc.v:42898$2260 assign { } { } assign $0\wr_pick_dly$1563[0:0]$2261 \wr_pick_dly$1563$next sync posedge \coresync_clk update \wr_pick_dly$1563 $0\wr_pick_dly$1563[0:0]$2261 end - attribute \src "libresoc.v:42852.3-42853.51" - process $proc$libresoc.v:42852$2262 + attribute \src "libresoc.v:42900.3-42901.51" + process $proc$libresoc.v:42900$2262 assign { } { } assign $0\wr_pick_dly$1547[0:0]$2263 \wr_pick_dly$1547$next sync posedge \coresync_clk update \wr_pick_dly$1547 $0\wr_pick_dly$1547[0:0]$2263 end - attribute \src "libresoc.v:42854.3-42855.51" - process $proc$libresoc.v:42854$2264 + attribute \src "libresoc.v:42902.3-42903.51" + process $proc$libresoc.v:42902$2264 assign { } { } assign $0\wr_pick_dly$1511[0:0]$2265 \wr_pick_dly$1511$next sync posedge \coresync_clk update \wr_pick_dly$1511 $0\wr_pick_dly$1511[0:0]$2265 end - attribute \src "libresoc.v:42856.3-42857.51" - process $proc$libresoc.v:42856$2266 + attribute \src "libresoc.v:42904.3-42905.51" + process $proc$libresoc.v:42904$2266 assign { } { } assign $0\wr_pick_dly$1495[0:0]$2267 \wr_pick_dly$1495$next sync posedge \coresync_clk update \wr_pick_dly$1495 $0\wr_pick_dly$1495[0:0]$2267 end - attribute \src "libresoc.v:42858.3-42859.51" - process $proc$libresoc.v:42858$2268 + attribute \src "libresoc.v:42906.3-42907.51" + process $proc$libresoc.v:42906$2268 assign { } { } assign $0\wr_pick_dly$1479[0:0]$2269 \wr_pick_dly$1479$next sync posedge \coresync_clk update \wr_pick_dly$1479 $0\wr_pick_dly$1479[0:0]$2269 end - attribute \src "libresoc.v:42860.3-42861.51" - process $proc$libresoc.v:42860$2270 + attribute \src "libresoc.v:42908.3-42909.51" + process $proc$libresoc.v:42908$2270 assign { } { } assign $0\wr_pick_dly$1463[0:0]$2271 \wr_pick_dly$1463$next sync posedge \coresync_clk update \wr_pick_dly$1463 $0\wr_pick_dly$1463[0:0]$2271 end - attribute \src "libresoc.v:42862.3-42863.51" - process $proc$libresoc.v:42862$2272 + attribute \src "libresoc.v:42910.3-42911.51" + process $proc$libresoc.v:42910$2272 assign { } { } assign $0\wr_pick_dly$1429[0:0]$2273 \wr_pick_dly$1429$next sync posedge \coresync_clk update \wr_pick_dly$1429 $0\wr_pick_dly$1429[0:0]$2273 end - attribute \src "libresoc.v:42864.3-42865.51" - process $proc$libresoc.v:42864$2274 + attribute \src "libresoc.v:42912.3-42913.51" + process $proc$libresoc.v:42912$2274 assign { } { } assign $0\wr_pick_dly$1413[0:0]$2275 \wr_pick_dly$1413$next sync posedge \coresync_clk update \wr_pick_dly$1413 $0\wr_pick_dly$1413[0:0]$2275 end - attribute \src "libresoc.v:42866.3-42867.51" - process $proc$libresoc.v:42866$2276 + attribute \src "libresoc.v:42914.3-42915.51" + process $proc$libresoc.v:42914$2276 assign { } { } assign $0\wr_pick_dly$1397[0:0]$2277 \wr_pick_dly$1397$next sync posedge \coresync_clk update \wr_pick_dly$1397 $0\wr_pick_dly$1397[0:0]$2277 end - attribute \src "libresoc.v:42868.3-42869.51" - process $proc$libresoc.v:42868$2278 + attribute \src "libresoc.v:42916.3-42917.51" + process $proc$libresoc.v:42916$2278 assign { } { } assign $0\wr_pick_dly$1350[0:0]$2279 \wr_pick_dly$1350$next sync posedge \coresync_clk update \wr_pick_dly$1350 $0\wr_pick_dly$1350[0:0]$2279 end - attribute \src "libresoc.v:42870.3-42871.51" - process $proc$libresoc.v:42870$2280 + attribute \src "libresoc.v:42918.3-42919.51" + process $proc$libresoc.v:42918$2280 assign { } { } assign $0\wr_pick_dly$1330[0:0]$2281 \wr_pick_dly$1330$next sync posedge \coresync_clk update \wr_pick_dly$1330 $0\wr_pick_dly$1330[0:0]$2281 end - attribute \src "libresoc.v:42872.3-42873.51" - process $proc$libresoc.v:42872$2282 + attribute \src "libresoc.v:42920.3-42921.51" + process $proc$libresoc.v:42920$2282 assign { } { } assign $0\wr_pick_dly$1310[0:0]$2283 \wr_pick_dly$1310$next sync posedge \coresync_clk update \wr_pick_dly$1310 $0\wr_pick_dly$1310[0:0]$2283 end - attribute \src "libresoc.v:42874.3-42875.51" - process $proc$libresoc.v:42874$2284 + attribute \src "libresoc.v:42922.3-42923.51" + process $proc$libresoc.v:42922$2284 assign { } { } assign $0\wr_pick_dly$1290[0:0]$2285 \wr_pick_dly$1290$next sync posedge \coresync_clk update \wr_pick_dly$1290 $0\wr_pick_dly$1290[0:0]$2285 end - attribute \src "libresoc.v:42876.3-42877.51" - process $proc$libresoc.v:42876$2286 + attribute \src "libresoc.v:42924.3-42925.51" + process $proc$libresoc.v:42924$2286 assign { } { } assign $0\wr_pick_dly$1270[0:0]$2287 \wr_pick_dly$1270$next sync posedge \coresync_clk update \wr_pick_dly$1270 $0\wr_pick_dly$1270[0:0]$2287 end - attribute \src "libresoc.v:42878.3-42879.51" - process $proc$libresoc.v:42878$2288 + attribute \src "libresoc.v:42926.3-42927.51" + process $proc$libresoc.v:42926$2288 assign { } { } assign $0\wr_pick_dly$1250[0:0]$2289 \wr_pick_dly$1250$next sync posedge \coresync_clk update \wr_pick_dly$1250 $0\wr_pick_dly$1250[0:0]$2289 end - attribute \src "libresoc.v:42880.3-42881.51" - process $proc$libresoc.v:42880$2290 + attribute \src "libresoc.v:42928.3-42929.51" + process $proc$libresoc.v:42928$2290 assign { } { } assign $0\wr_pick_dly$1222[0:0]$2291 \wr_pick_dly$1222$next sync posedge \coresync_clk update \wr_pick_dly$1222 $0\wr_pick_dly$1222[0:0]$2291 end - attribute \src "libresoc.v:42882.3-42883.51" - process $proc$libresoc.v:42882$2292 + attribute \src "libresoc.v:42930.3-42931.51" + process $proc$libresoc.v:42930$2292 assign { } { } assign $0\wr_pick_dly$1148[0:0]$2293 \wr_pick_dly$1148$next sync posedge \coresync_clk update \wr_pick_dly$1148 $0\wr_pick_dly$1148[0:0]$2293 end - attribute \src "libresoc.v:42884.3-42885.51" - process $proc$libresoc.v:42884$2294 + attribute \src "libresoc.v:42932.3-42933.51" + process $proc$libresoc.v:42932$2294 assign { } { } assign $0\wr_pick_dly$1130[0:0]$2295 \wr_pick_dly$1130$next sync posedge \coresync_clk update \wr_pick_dly$1130 $0\wr_pick_dly$1130[0:0]$2295 end - attribute \src "libresoc.v:42886.3-42887.51" - process $proc$libresoc.v:42886$2296 + attribute \src "libresoc.v:42934.3-42935.51" + process $proc$libresoc.v:42934$2296 assign { } { } assign $0\wr_pick_dly$1111[0:0]$2297 \wr_pick_dly$1111$next sync posedge \coresync_clk update \wr_pick_dly$1111 $0\wr_pick_dly$1111[0:0]$2297 end - attribute \src "libresoc.v:42888.3-42889.51" - process $proc$libresoc.v:42888$2298 + attribute \src "libresoc.v:42936.3-42937.51" + process $proc$libresoc.v:42936$2298 assign { } { } assign $0\wr_pick_dly$1091[0:0]$2299 \wr_pick_dly$1091$next sync posedge \coresync_clk update \wr_pick_dly$1091 $0\wr_pick_dly$1091[0:0]$2299 end - attribute \src "libresoc.v:42890.3-42891.51" - process $proc$libresoc.v:42890$2300 + attribute \src "libresoc.v:42938.3-42939.51" + process $proc$libresoc.v:42938$2300 assign { } { } assign $0\wr_pick_dly$1071[0:0]$2301 \wr_pick_dly$1071$next sync posedge \coresync_clk update \wr_pick_dly$1071 $0\wr_pick_dly$1071[0:0]$2301 end - attribute \src "libresoc.v:42892.3-42893.51" - process $proc$libresoc.v:42892$2302 + attribute \src "libresoc.v:42940.3-42941.51" + process $proc$libresoc.v:42940$2302 assign { } { } assign $0\wr_pick_dly$1049[0:0]$2303 \wr_pick_dly$1049$next sync posedge \coresync_clk update \wr_pick_dly$1049 $0\wr_pick_dly$1049[0:0]$2303 end - attribute \src "libresoc.v:42894.3-42895.51" - process $proc$libresoc.v:42894$2304 + attribute \src "libresoc.v:42942.3-42943.51" + process $proc$libresoc.v:42942$2304 assign { } { } assign $0\wr_pick_dly$1031[0:0]$2305 \wr_pick_dly$1031$next sync posedge \coresync_clk update \wr_pick_dly$1031 $0\wr_pick_dly$1031[0:0]$2305 end - attribute \src "libresoc.v:42896.3-42897.51" - process $proc$libresoc.v:42896$2306 + attribute \src "libresoc.v:42944.3-42945.51" + process $proc$libresoc.v:42944$2306 assign { } { } assign $0\wr_pick_dly$1010[0:0]$2307 \wr_pick_dly$1010$next sync posedge \coresync_clk update \wr_pick_dly$1010 $0\wr_pick_dly$1010[0:0]$2307 end - attribute \src "libresoc.v:42898.3-42899.49" - process $proc$libresoc.v:42898$2308 + attribute \src "libresoc.v:42946.3-42947.49" + process $proc$libresoc.v:42946$2308 assign { } { } assign $0\wr_pick_dly$991[0:0]$2309 \wr_pick_dly$991$next sync posedge \coresync_clk update \wr_pick_dly$991 $0\wr_pick_dly$991[0:0]$2309 end - attribute \src "libresoc.v:42900.3-42901.39" - process $proc$libresoc.v:42900$2310 + attribute \src "libresoc.v:42948.3-42949.39" + process $proc$libresoc.v:42948$2310 assign { } { } assign $0\wr_pick_dly[0:0] \wr_pick_dly$next sync posedge \coresync_clk update \wr_pick_dly $0\wr_pick_dly[0:0] end - attribute \src "libresoc.v:42902.3-42903.53" - process $proc$libresoc.v:42902$2311 + attribute \src "libresoc.v:42950.3-42951.53" + process $proc$libresoc.v:42950$2311 assign { } { } assign $0\dp_SPR_spr1_spr0_0[0:0] \dp_SPR_spr1_spr0_0$next sync posedge \coresync_clk update \dp_SPR_spr1_spr0_0 $0\dp_SPR_spr1_spr0_0[0:0] end - attribute \src "libresoc.v:42904.3-42905.59" - process $proc$libresoc.v:42904$2312 + attribute \src "libresoc.v:42952.3-42953.59" + process $proc$libresoc.v:42952$2312 assign { } { } assign $0\dp_FAST_fast2_trap0_1[0:0] \dp_FAST_fast2_trap0_1$next sync posedge \coresync_clk update \dp_FAST_fast2_trap0_1 $0\dp_FAST_fast2_trap0_1[0:0] end - attribute \src "libresoc.v:42906.3-42907.63" - process $proc$libresoc.v:42906$2313 + attribute \src "libresoc.v:42954.3-42955.63" + process $proc$libresoc.v:42954$2313 assign { } { } assign $0\dp_FAST_fast2_branch0_0[0:0] \dp_FAST_fast2_branch0_0$next sync posedge \coresync_clk update \dp_FAST_fast2_branch0_0 $0\dp_FAST_fast2_branch0_0[0:0] end - attribute \src "libresoc.v:42908.3-42909.57" - process $proc$libresoc.v:42908$2314 + attribute \src "libresoc.v:42956.3-42957.57" + process $proc$libresoc.v:42956$2314 assign { } { } assign $0\dp_FAST_fast1_spr0_2[0:0] \dp_FAST_fast1_spr0_2$next sync posedge \coresync_clk update \dp_FAST_fast1_spr0_2 $0\dp_FAST_fast1_spr0_2[0:0] end - attribute \src "libresoc.v:42910.3-42911.59" - process $proc$libresoc.v:42910$2315 + attribute \src "libresoc.v:42958.3-42959.59" + process $proc$libresoc.v:42958$2315 assign { } { } assign $0\dp_FAST_fast1_trap0_1[0:0] \dp_FAST_fast1_trap0_1$next sync posedge \coresync_clk update \dp_FAST_fast1_trap0_1 $0\dp_FAST_fast1_trap0_1[0:0] end - attribute \src "libresoc.v:42912.3-42913.63" - process $proc$libresoc.v:42912$2316 + attribute \src "libresoc.v:42960.3-42961.63" + process $proc$libresoc.v:42960$2316 assign { } { } assign $0\dp_FAST_fast1_branch0_0[0:0] \dp_FAST_fast1_branch0_0$next sync posedge \coresync_clk update \dp_FAST_fast1_branch0_0 $0\dp_FAST_fast1_branch0_0[0:0] end - attribute \src "libresoc.v:42914.3-42915.49" - process $proc$libresoc.v:42914$2317 + attribute \src "libresoc.v:42962.3-42963.49" + process $proc$libresoc.v:42962$2317 assign { } { } assign $0\dp_CR_cr_c_cr0_0[0:0] \dp_CR_cr_c_cr0_0$next sync posedge \coresync_clk update \dp_CR_cr_c_cr0_0 $0\dp_CR_cr_c_cr0_0[0:0] end - attribute \src "libresoc.v:42916.3-42917.49" - process $proc$libresoc.v:42916$2318 + attribute \src "libresoc.v:42964.3-42965.49" + process $proc$libresoc.v:42964$2318 assign { } { } assign $0\dp_CR_cr_b_cr0_0[0:0] \dp_CR_cr_b_cr0_0$next sync posedge \coresync_clk update \dp_CR_cr_b_cr0_0 $0\dp_CR_cr_b_cr0_0[0:0] end - attribute \src "libresoc.v:42918.3-42919.57" - process $proc$libresoc.v:42918$2319 + attribute \src "libresoc.v:42966.3-42967.57" + process $proc$libresoc.v:42966$2319 assign { } { } assign $0\dp_CR_cr_a_branch0_1[0:0] \dp_CR_cr_a_branch0_1$next sync posedge \coresync_clk update \dp_CR_cr_a_branch0_1 $0\dp_CR_cr_a_branch0_1[0:0] end - attribute \src "libresoc.v:42920.3-42921.49" - process $proc$libresoc.v:42920$2320 + attribute \src "libresoc.v:42968.3-42969.49" + process $proc$libresoc.v:42968$2320 assign { } { } assign $0\dp_CR_cr_a_cr0_0[0:0] \dp_CR_cr_a_cr0_0$next sync posedge \coresync_clk update \dp_CR_cr_a_cr0_0 $0\dp_CR_cr_a_cr0_0[0:0] end - attribute \src "libresoc.v:42922.3-42923.55" - process $proc$libresoc.v:42922$2321 + attribute \src "libresoc.v:42970.3-42971.55" + process $proc$libresoc.v:42970$2321 assign { } { } assign $0\dp_CR_full_cr_cr0_0[0:0] \dp_CR_full_cr_cr0_0$next sync posedge \coresync_clk update \dp_CR_full_cr_cr0_0 $0\dp_CR_full_cr_cr0_0[0:0] end - attribute \src "libresoc.v:42924.3-42925.57" - process $proc$libresoc.v:42924$2322 + attribute \src "libresoc.v:42972.3-42973.57" + process $proc$libresoc.v:42972$2322 assign { } { } assign $0\dp_XER_xer_ov_spr0_0[0:0] \dp_XER_xer_ov_spr0_0$next sync posedge \coresync_clk update \dp_XER_xer_ov_spr0_0 $0\dp_XER_xer_ov_spr0_0[0:0] end - attribute \src "libresoc.v:42926.3-42927.67" - process $proc$libresoc.v:42926$2323 + attribute \src "libresoc.v:42974.3-42975.67" + process $proc$libresoc.v:42974$2323 assign { } { } assign $0\dp_XER_xer_ca_shiftrot0_2[0:0] \dp_XER_xer_ca_shiftrot0_2$next sync posedge \coresync_clk update \dp_XER_xer_ca_shiftrot0_2 $0\dp_XER_xer_ca_shiftrot0_2[0:0] end - attribute \src "libresoc.v:42928.3-42929.57" - process $proc$libresoc.v:42928$2324 + attribute \src "libresoc.v:42976.3-42977.57" + process $proc$libresoc.v:42976$2324 assign { } { } assign $0\dp_XER_xer_ca_spr0_1[0:0] \dp_XER_xer_ca_spr0_1$next sync posedge \coresync_clk update \dp_XER_xer_ca_spr0_1 $0\dp_XER_xer_ca_spr0_1[0:0] end - attribute \src "libresoc.v:42930.3-42931.57" - process $proc$libresoc.v:42930$2325 + attribute \src "libresoc.v:42978.3-42979.57" + process $proc$libresoc.v:42978$2325 assign { } { } assign $0\dp_XER_xer_ca_alu0_0[0:0] \dp_XER_xer_ca_alu0_0$next sync posedge \coresync_clk update \dp_XER_xer_ca_alu0_0 $0\dp_XER_xer_ca_alu0_0[0:0] end - attribute \src "libresoc.v:42932.3-42933.67" - process $proc$libresoc.v:42932$2326 + attribute \src "libresoc.v:42980.3-42981.67" + process $proc$libresoc.v:42980$2326 assign { } { } assign $0\dp_XER_xer_so_shiftrot0_5[0:0] \dp_XER_xer_so_shiftrot0_5$next sync posedge \coresync_clk update \dp_XER_xer_so_shiftrot0_5 $0\dp_XER_xer_so_shiftrot0_5[0:0] end - attribute \src "libresoc.v:42934.3-42935.57" - process $proc$libresoc.v:42934$2327 + attribute \src "libresoc.v:42982.3-42983.57" + process $proc$libresoc.v:42982$2327 assign { } { } assign $0\dp_XER_xer_so_mul0_4[0:0] \dp_XER_xer_so_mul0_4$next sync posedge \coresync_clk update \dp_XER_xer_so_mul0_4 $0\dp_XER_xer_so_mul0_4[0:0] end - attribute \src "libresoc.v:42936.3-42937.57" - process $proc$libresoc.v:42936$2328 + attribute \src "libresoc.v:42984.3-42985.57" + process $proc$libresoc.v:42984$2328 assign { } { } assign $0\dp_XER_xer_so_div0_3[0:0] \dp_XER_xer_so_div0_3$next sync posedge \coresync_clk update \dp_XER_xer_so_div0_3 $0\dp_XER_xer_so_div0_3[0:0] end - attribute \src "libresoc.v:42938.3-42939.57" - process $proc$libresoc.v:42938$2329 + attribute \src "libresoc.v:42986.3-42987.57" + process $proc$libresoc.v:42986$2329 assign { } { } assign $0\dp_XER_xer_so_spr0_2[0:0] \dp_XER_xer_so_spr0_2$next sync posedge \coresync_clk update \dp_XER_xer_so_spr0_2 $0\dp_XER_xer_so_spr0_2[0:0] end - attribute \src "libresoc.v:42940.3-42941.65" - process $proc$libresoc.v:42940$2330 + attribute \src "libresoc.v:42988.3-42989.65" + process $proc$libresoc.v:42988$2330 assign { } { } assign $0\dp_XER_xer_so_logical0_1[0:0] \dp_XER_xer_so_logical0_1$next sync posedge \coresync_clk update \dp_XER_xer_so_logical0_1 $0\dp_XER_xer_so_logical0_1[0:0] end - attribute \src "libresoc.v:42942.3-42943.57" - process $proc$libresoc.v:42942$2331 + attribute \src "libresoc.v:42990.3-42991.57" + process $proc$libresoc.v:42990$2331 assign { } { } assign $0\dp_XER_xer_so_alu0_0[0:0] \dp_XER_xer_so_alu0_0$next sync posedge \coresync_clk update \dp_XER_xer_so_alu0_0 $0\dp_XER_xer_so_alu0_0[0:0] end - attribute \src "libresoc.v:42944.3-42945.51" - process $proc$libresoc.v:42944$2332 + attribute \src "libresoc.v:42992.3-42993.51" + process $proc$libresoc.v:42992$2332 assign { } { } assign $0\dp_INT_rc_ldst0_1[0:0] \dp_INT_rc_ldst0_1$next sync posedge \coresync_clk update \dp_INT_rc_ldst0_1 $0\dp_INT_rc_ldst0_1[0:0] end - attribute \src "libresoc.v:42946.3-42947.59" - process $proc$libresoc.v:42946$2333 + attribute \src "libresoc.v:42994.3-42995.59" + process $proc$libresoc.v:42994$2333 assign { } { } assign $0\dp_INT_rc_shiftrot0_0[0:0] \dp_INT_rc_shiftrot0_0$next sync posedge \coresync_clk update \dp_INT_rc_shiftrot0_0 $0\dp_INT_rc_shiftrot0_0[0:0] end - attribute \src "libresoc.v:42948.3-42949.51" - process $proc$libresoc.v:42948$2334 + attribute \src "libresoc.v:42996.3-42997.51" + process $proc$libresoc.v:42996$2334 assign { } { } assign $0\dp_INT_rb_ldst0_7[0:0] \dp_INT_rb_ldst0_7$next sync posedge \coresync_clk update \dp_INT_rb_ldst0_7 $0\dp_INT_rb_ldst0_7[0:0] end - attribute \src "libresoc.v:42950.3-42951.59" - process $proc$libresoc.v:42950$2335 + attribute \src "libresoc.v:42998.3-42999.59" + process $proc$libresoc.v:42998$2335 assign { } { } assign $0\dp_INT_rb_shiftrot0_6[0:0] \dp_INT_rb_shiftrot0_6$next sync posedge \coresync_clk update \dp_INT_rb_shiftrot0_6 $0\dp_INT_rb_shiftrot0_6[0:0] end - attribute \src "libresoc.v:42952.3-42953.49" - process $proc$libresoc.v:42952$2336 + attribute \src "libresoc.v:43000.3-43001.49" + process $proc$libresoc.v:43000$2336 assign { } { } assign $0\dp_INT_rb_mul0_5[0:0] \dp_INT_rb_mul0_5$next sync posedge \coresync_clk update \dp_INT_rb_mul0_5 $0\dp_INT_rb_mul0_5[0:0] end - attribute \src "libresoc.v:42954.3-42955.49" - process $proc$libresoc.v:42954$2337 + attribute \src "libresoc.v:43002.3-43003.49" + process $proc$libresoc.v:43002$2337 assign { } { } assign $0\dp_INT_rb_div0_4[0:0] \dp_INT_rb_div0_4$next sync posedge \coresync_clk update \dp_INT_rb_div0_4 $0\dp_INT_rb_div0_4[0:0] end - attribute \src "libresoc.v:42956.3-42957.57" - process $proc$libresoc.v:42956$2338 + attribute \src "libresoc.v:43004.3-43005.57" + process $proc$libresoc.v:43004$2338 assign { } { } assign $0\dp_INT_rb_logical0_3[0:0] \dp_INT_rb_logical0_3$next sync posedge \coresync_clk update \dp_INT_rb_logical0_3 $0\dp_INT_rb_logical0_3[0:0] end - attribute \src "libresoc.v:42958.3-42959.51" - process $proc$libresoc.v:42958$2339 + attribute \src "libresoc.v:43006.3-43007.51" + process $proc$libresoc.v:43006$2339 assign { } { } assign $0\dp_INT_rb_trap0_2[0:0] \dp_INT_rb_trap0_2$next sync posedge \coresync_clk update \dp_INT_rb_trap0_2 $0\dp_INT_rb_trap0_2[0:0] end - attribute \src "libresoc.v:42960.3-42961.47" - process $proc$libresoc.v:42960$2340 + attribute \src "libresoc.v:43008.3-43009.47" + process $proc$libresoc.v:43008$2340 assign { } { } assign $0\dp_INT_rb_cr0_1[0:0] \dp_INT_rb_cr0_1$next sync posedge \coresync_clk update \dp_INT_rb_cr0_1 $0\dp_INT_rb_cr0_1[0:0] end - attribute \src "libresoc.v:42962.3-42963.49" - process $proc$libresoc.v:42962$2341 + attribute \src "libresoc.v:43010.3-43011.49" + process $proc$libresoc.v:43010$2341 assign { } { } assign $0\dp_INT_rb_alu0_0[0:0] \dp_INT_rb_alu0_0$next sync posedge \coresync_clk update \dp_INT_rb_alu0_0 $0\dp_INT_rb_alu0_0[0:0] end - attribute \src "libresoc.v:42964.3-42965.51" - process $proc$libresoc.v:42964$2342 + attribute \src "libresoc.v:43012.3-43013.51" + process $proc$libresoc.v:43012$2342 assign { } { } assign $0\dp_INT_ra_ldst0_8[0:0] \dp_INT_ra_ldst0_8$next sync posedge \coresync_clk update \dp_INT_ra_ldst0_8 $0\dp_INT_ra_ldst0_8[0:0] end - attribute \src "libresoc.v:42966.3-42967.59" - process $proc$libresoc.v:42966$2343 + attribute \src "libresoc.v:43014.3-43015.59" + process $proc$libresoc.v:43014$2343 assign { } { } assign $0\dp_INT_ra_shiftrot0_7[0:0] \dp_INT_ra_shiftrot0_7$next sync posedge \coresync_clk update \dp_INT_ra_shiftrot0_7 $0\dp_INT_ra_shiftrot0_7[0:0] end - attribute \src "libresoc.v:42968.3-42969.49" - process $proc$libresoc.v:42968$2344 + attribute \src "libresoc.v:43016.3-43017.49" + process $proc$libresoc.v:43016$2344 assign { } { } assign $0\dp_INT_ra_mul0_6[0:0] \dp_INT_ra_mul0_6$next sync posedge \coresync_clk update \dp_INT_ra_mul0_6 $0\dp_INT_ra_mul0_6[0:0] end - attribute \src "libresoc.v:42970.3-42971.49" - process $proc$libresoc.v:42970$2345 + attribute \src "libresoc.v:43018.3-43019.49" + process $proc$libresoc.v:43018$2345 assign { } { } assign $0\dp_INT_ra_div0_5[0:0] \dp_INT_ra_div0_5$next sync posedge \coresync_clk update \dp_INT_ra_div0_5 $0\dp_INT_ra_div0_5[0:0] end - attribute \src "libresoc.v:42972.3-42973.49" - process $proc$libresoc.v:42972$2346 + attribute \src "libresoc.v:43020.3-43021.49" + process $proc$libresoc.v:43020$2346 assign { } { } assign $0\dp_INT_ra_spr0_4[0:0] \dp_INT_ra_spr0_4$next sync posedge \coresync_clk update \dp_INT_ra_spr0_4 $0\dp_INT_ra_spr0_4[0:0] end - attribute \src "libresoc.v:42974.3-42975.57" - process $proc$libresoc.v:42974$2347 + attribute \src "libresoc.v:43022.3-43023.57" + process $proc$libresoc.v:43022$2347 assign { } { } assign $0\dp_INT_ra_logical0_3[0:0] \dp_INT_ra_logical0_3$next sync posedge \coresync_clk update \dp_INT_ra_logical0_3 $0\dp_INT_ra_logical0_3[0:0] end - attribute \src "libresoc.v:42976.3-42977.51" - process $proc$libresoc.v:42976$2348 + attribute \src "libresoc.v:43024.3-43025.51" + process $proc$libresoc.v:43024$2348 assign { } { } assign $0\dp_INT_ra_trap0_2[0:0] \dp_INT_ra_trap0_2$next sync posedge \coresync_clk update \dp_INT_ra_trap0_2 $0\dp_INT_ra_trap0_2[0:0] end - attribute \src "libresoc.v:42978.3-42979.47" - process $proc$libresoc.v:42978$2349 + attribute \src "libresoc.v:43026.3-43027.47" + process $proc$libresoc.v:43026$2349 assign { } { } assign $0\dp_INT_ra_cr0_1[0:0] \dp_INT_ra_cr0_1$next sync posedge \coresync_clk update \dp_INT_ra_cr0_1 $0\dp_INT_ra_cr0_1[0:0] end - attribute \src "libresoc.v:42980.3-42981.49" - process $proc$libresoc.v:42980$2350 + attribute \src "libresoc.v:43028.3-43029.49" + process $proc$libresoc.v:43028$2350 assign { } { } assign $0\dp_INT_ra_alu0_0[0:0] \dp_INT_ra_alu0_0$next sync posedge \coresync_clk update \dp_INT_ra_alu0_0 $0\dp_INT_ra_alu0_0[0:0] end - attribute \src "libresoc.v:42982.3-42983.49" - process $proc$libresoc.v:42982$2351 + attribute \src "libresoc.v:43030.3-43031.49" + process $proc$libresoc.v:43030$2351 assign { } { } assign $0\core_terminate_o[0:0] \core_terminate_o$next sync posedge \coresync_clk update \core_terminate_o $0\core_terminate_o[0:0] end - attribute \src "libresoc.v:42984.3-42985.31" - process $proc$libresoc.v:42984$2352 + attribute \src "libresoc.v:43032.3-43033.31" + process $proc$libresoc.v:43032$2352 assign { } { } assign $0\counter[1:0] \counter$next sync posedge \coresync_clk update \counter $0\counter[1:0] end - attribute \src "libresoc.v:43723.3-43751.6" - process $proc$libresoc.v:43723$2353 + attribute \src "libresoc.v:43771.3-43799.6" + process $proc$libresoc.v:43771$2353 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__output_carry[0:0] $1\fus_oper_i_alu_logical0__output_carry[0:0] - attribute \src "libresoc.v:43724.5-43724.29" + attribute \src "libresoc.v:43772.5-43772.29" switch \initial - attribute \src "libresoc.v:43724.9-43724.17" + attribute \src "libresoc.v:43772.9-43772.17" case 1'1 case end @@ -75790,14 +75826,14 @@ module \core sync always update \fus_oper_i_alu_logical0__output_carry $0\fus_oper_i_alu_logical0__output_carry[0:0] end - attribute \src "libresoc.v:43752.3-43780.6" - process $proc$libresoc.v:43752$2354 + attribute \src "libresoc.v:43800.3-43828.6" + process $proc$libresoc.v:43800$2354 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__is_32bit[0:0] $1\fus_oper_i_alu_logical0__is_32bit[0:0] - attribute \src "libresoc.v:43753.5-43753.29" + attribute \src "libresoc.v:43801.5-43801.29" switch \initial - attribute \src "libresoc.v:43753.9-43753.17" + attribute \src "libresoc.v:43801.9-43801.17" case 1'1 case end @@ -75835,14 +75871,14 @@ module \core sync always update \fus_oper_i_alu_logical0__is_32bit $0\fus_oper_i_alu_logical0__is_32bit[0:0] end - attribute \src "libresoc.v:43781.3-43809.6" - process $proc$libresoc.v:43781$2355 + attribute \src "libresoc.v:43829.3-43857.6" + process $proc$libresoc.v:43829$2355 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__is_signed[0:0] $1\fus_oper_i_alu_logical0__is_signed[0:0] - attribute \src "libresoc.v:43782.5-43782.29" + attribute \src "libresoc.v:43830.5-43830.29" switch \initial - attribute \src "libresoc.v:43782.9-43782.17" + attribute \src "libresoc.v:43830.9-43830.17" case 1'1 case end @@ -75880,14 +75916,14 @@ module \core sync always update \fus_oper_i_alu_logical0__is_signed $0\fus_oper_i_alu_logical0__is_signed[0:0] end - attribute \src "libresoc.v:43810.3-43838.6" - process $proc$libresoc.v:43810$2356 + attribute \src "libresoc.v:43858.3-43886.6" + process $proc$libresoc.v:43858$2356 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__data_len[3:0] $1\fus_oper_i_alu_logical0__data_len[3:0] - attribute \src "libresoc.v:43811.5-43811.29" + attribute \src "libresoc.v:43859.5-43859.29" switch \initial - attribute \src "libresoc.v:43811.9-43811.17" + attribute \src "libresoc.v:43859.9-43859.17" case 1'1 case end @@ -75925,14 +75961,14 @@ module \core sync always update \fus_oper_i_alu_logical0__data_len $0\fus_oper_i_alu_logical0__data_len[3:0] end - attribute \src "libresoc.v:43839.3-43867.6" - process $proc$libresoc.v:43839$2357 + attribute \src "libresoc.v:43887.3-43915.6" + process $proc$libresoc.v:43887$2357 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__insn[31:0] $1\fus_oper_i_alu_logical0__insn[31:0] - attribute \src "libresoc.v:43840.5-43840.29" + attribute \src "libresoc.v:43888.5-43888.29" switch \initial - attribute \src "libresoc.v:43840.9-43840.17" + attribute \src "libresoc.v:43888.9-43888.17" case 1'1 case end @@ -75970,14 +76006,14 @@ module \core sync always update \fus_oper_i_alu_logical0__insn $0\fus_oper_i_alu_logical0__insn[31:0] end - attribute \src "libresoc.v:43868.3-43896.6" - process $proc$libresoc.v:43868$2358 + attribute \src "libresoc.v:43916.3-43944.6" + process $proc$libresoc.v:43916$2358 assign { } { } assign { } { } assign $0\fus_cu_issue_i$22[0:0]$2359 $1\fus_cu_issue_i$22[0:0]$2360 - attribute \src "libresoc.v:43869.5-43869.29" + attribute \src "libresoc.v:43917.5-43917.29" switch \initial - attribute \src "libresoc.v:43869.9-43869.17" + attribute \src "libresoc.v:43917.9-43917.17" case 1'1 case end @@ -76015,14 +76051,14 @@ module \core sync always update \fus_cu_issue_i$22 $0\fus_cu_issue_i$22[0:0]$2359 end - attribute \src "libresoc.v:43897.3-43925.6" - process $proc$libresoc.v:43897$2363 + attribute \src "libresoc.v:43945.3-43973.6" + process $proc$libresoc.v:43945$2363 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$24[2:0]$2364 $1\fus_cu_rdmaskn_i$24[2:0]$2365 - attribute \src "libresoc.v:43898.5-43898.29" + attribute \src "libresoc.v:43946.5-43946.29" switch \initial - attribute \src "libresoc.v:43898.9-43898.17" + attribute \src "libresoc.v:43946.9-43946.17" case 1'1 case end @@ -76060,14 +76096,14 @@ module \core sync always update \fus_cu_rdmaskn_i$24 $0\fus_cu_rdmaskn_i$24[2:0]$2364 end - attribute \src "libresoc.v:43926.3-43954.6" - process $proc$libresoc.v:43926$2368 + attribute \src "libresoc.v:43974.3-44002.6" + process $proc$libresoc.v:43974$2368 assign { } { } assign { } { } assign $0\fus_oper_i_alu_spr0__insn_type[6:0] $1\fus_oper_i_alu_spr0__insn_type[6:0] - attribute \src "libresoc.v:43927.5-43927.29" + attribute \src "libresoc.v:43975.5-43975.29" switch \initial - attribute \src "libresoc.v:43927.9-43927.17" + attribute \src "libresoc.v:43975.9-43975.17" case 1'1 case end @@ -76105,14 +76141,14 @@ module \core sync always update \fus_oper_i_alu_spr0__insn_type $0\fus_oper_i_alu_spr0__insn_type[6:0] end - attribute \src "libresoc.v:43955.3-43983.6" - process $proc$libresoc.v:43955$2369 + attribute \src "libresoc.v:44003.3-44031.6" + process $proc$libresoc.v:44003$2369 assign { } { } assign { } { } assign $0\fus_oper_i_alu_spr0__fn_unit[13:0] $1\fus_oper_i_alu_spr0__fn_unit[13:0] - attribute \src "libresoc.v:43956.5-43956.29" + attribute \src "libresoc.v:44004.5-44004.29" switch \initial - attribute \src "libresoc.v:43956.9-43956.17" + attribute \src "libresoc.v:44004.9-44004.17" case 1'1 case end @@ -76150,14 +76186,14 @@ module \core sync always update \fus_oper_i_alu_spr0__fn_unit $0\fus_oper_i_alu_spr0__fn_unit[13:0] end - attribute \src "libresoc.v:43984.3-44012.6" - process $proc$libresoc.v:43984$2370 + attribute \src "libresoc.v:44032.3-44060.6" + process $proc$libresoc.v:44032$2370 assign { } { } assign { } { } assign $0\fus_oper_i_alu_spr0__insn[31:0] $1\fus_oper_i_alu_spr0__insn[31:0] - attribute \src "libresoc.v:43985.5-43985.29" + attribute \src "libresoc.v:44033.5-44033.29" switch \initial - attribute \src "libresoc.v:43985.9-43985.17" + attribute \src "libresoc.v:44033.9-44033.17" case 1'1 case end @@ -76195,14 +76231,14 @@ module \core sync always update \fus_oper_i_alu_spr0__insn $0\fus_oper_i_alu_spr0__insn[31:0] end - attribute \src "libresoc.v:44013.3-44041.6" - process $proc$libresoc.v:44013$2371 + attribute \src "libresoc.v:44061.3-44089.6" + process $proc$libresoc.v:44061$2371 assign { } { } assign { } { } assign $0\fus_oper_i_alu_spr0__is_32bit[0:0] $1\fus_oper_i_alu_spr0__is_32bit[0:0] - attribute \src "libresoc.v:44014.5-44014.29" + attribute \src "libresoc.v:44062.5-44062.29" switch \initial - attribute \src "libresoc.v:44014.9-44014.17" + attribute \src "libresoc.v:44062.9-44062.17" case 1'1 case end @@ -76240,14 +76276,14 @@ module \core sync always update \fus_oper_i_alu_spr0__is_32bit $0\fus_oper_i_alu_spr0__is_32bit[0:0] end - attribute \src "libresoc.v:44042.3-44070.6" - process $proc$libresoc.v:44042$2372 + attribute \src "libresoc.v:44090.3-44118.6" + process $proc$libresoc.v:44090$2372 assign { } { } assign { } { } assign $0\fus_cu_issue_i$25[0:0]$2373 $1\fus_cu_issue_i$25[0:0]$2374 - attribute \src "libresoc.v:44043.5-44043.29" + attribute \src "libresoc.v:44091.5-44091.29" switch \initial - attribute \src "libresoc.v:44043.9-44043.17" + attribute \src "libresoc.v:44091.9-44091.17" case 1'1 case end @@ -76285,14 +76321,14 @@ module \core sync always update \fus_cu_issue_i$25 $0\fus_cu_issue_i$25[0:0]$2373 end - attribute \src "libresoc.v:44071.3-44099.6" - process $proc$libresoc.v:44071$2377 + attribute \src "libresoc.v:44119.3-44147.6" + process $proc$libresoc.v:44119$2377 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$27[5:0]$2378 $1\fus_cu_rdmaskn_i$27[5:0]$2379 - attribute \src "libresoc.v:44072.5-44072.29" + attribute \src "libresoc.v:44120.5-44120.29" switch \initial - attribute \src "libresoc.v:44072.9-44072.17" + attribute \src "libresoc.v:44120.9-44120.17" case 1'1 case end @@ -76330,14 +76366,14 @@ module \core sync always update \fus_cu_rdmaskn_i$27 $0\fus_cu_rdmaskn_i$27[5:0]$2378 end - attribute \src "libresoc.v:44100.3-44128.6" - process $proc$libresoc.v:44100$2382 + attribute \src "libresoc.v:44148.3-44176.6" + process $proc$libresoc.v:44148$2382 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__insn_type[6:0] $1\fus_oper_i_alu_div0__insn_type[6:0] - attribute \src "libresoc.v:44101.5-44101.29" + attribute \src "libresoc.v:44149.5-44149.29" switch \initial - attribute \src "libresoc.v:44101.9-44101.17" + attribute \src "libresoc.v:44149.9-44149.17" case 1'1 case end @@ -76375,14 +76411,14 @@ module \core sync always update \fus_oper_i_alu_div0__insn_type $0\fus_oper_i_alu_div0__insn_type[6:0] end - attribute \src "libresoc.v:44129.3-44157.6" - process $proc$libresoc.v:44129$2383 + attribute \src "libresoc.v:44177.3-44205.6" + process $proc$libresoc.v:44177$2383 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__fn_unit[13:0] $1\fus_oper_i_alu_div0__fn_unit[13:0] - attribute \src "libresoc.v:44130.5-44130.29" + attribute \src "libresoc.v:44178.5-44178.29" switch \initial - attribute \src "libresoc.v:44130.9-44130.17" + attribute \src "libresoc.v:44178.9-44178.17" case 1'1 case end @@ -76420,17 +76456,17 @@ module \core sync always update \fus_oper_i_alu_div0__fn_unit $0\fus_oper_i_alu_div0__fn_unit[13:0] end - attribute \src "libresoc.v:44158.3-44187.6" - process $proc$libresoc.v:44158$2384 + attribute \src "libresoc.v:44206.3-44235.6" + process $proc$libresoc.v:44206$2384 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__imm_data__data[63:0] $1\fus_oper_i_alu_div0__imm_data__data[63:0] assign $0\fus_oper_i_alu_div0__imm_data__ok[0:0] $1\fus_oper_i_alu_div0__imm_data__ok[0:0] - attribute \src "libresoc.v:44159.5-44159.29" + attribute \src "libresoc.v:44207.5-44207.29" switch \initial - attribute \src "libresoc.v:44159.9-44159.17" + attribute \src "libresoc.v:44207.9-44207.17" case 1'1 case end @@ -76478,17 +76514,17 @@ module \core update \fus_oper_i_alu_div0__imm_data__data $0\fus_oper_i_alu_div0__imm_data__data[63:0] update \fus_oper_i_alu_div0__imm_data__ok $0\fus_oper_i_alu_div0__imm_data__ok[0:0] end - attribute \src "libresoc.v:44188.3-44217.6" - process $proc$libresoc.v:44188$2385 + attribute \src "libresoc.v:44236.3-44265.6" + process $proc$libresoc.v:44236$2385 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__rc__ok[0:0] $1\fus_oper_i_alu_div0__rc__ok[0:0] assign $0\fus_oper_i_alu_div0__rc__rc[0:0] $1\fus_oper_i_alu_div0__rc__rc[0:0] - attribute \src "libresoc.v:44189.5-44189.29" + attribute \src "libresoc.v:44237.5-44237.29" switch \initial - attribute \src "libresoc.v:44189.9-44189.17" + attribute \src "libresoc.v:44237.9-44237.17" case 1'1 case end @@ -76536,17 +76572,17 @@ module \core update \fus_oper_i_alu_div0__rc__ok $0\fus_oper_i_alu_div0__rc__ok[0:0] update \fus_oper_i_alu_div0__rc__rc $0\fus_oper_i_alu_div0__rc__rc[0:0] end - attribute \src "libresoc.v:44218.3-44247.6" - process $proc$libresoc.v:44218$2386 + attribute \src "libresoc.v:44266.3-44295.6" + process $proc$libresoc.v:44266$2386 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__oe__oe[0:0] $1\fus_oper_i_alu_div0__oe__oe[0:0] assign $0\fus_oper_i_alu_div0__oe__ok[0:0] $1\fus_oper_i_alu_div0__oe__ok[0:0] - attribute \src "libresoc.v:44219.5-44219.29" + attribute \src "libresoc.v:44267.5-44267.29" switch \initial - attribute \src "libresoc.v:44219.9-44219.17" + attribute \src "libresoc.v:44267.9-44267.17" case 1'1 case end @@ -76594,14 +76630,14 @@ module \core update \fus_oper_i_alu_div0__oe__oe $0\fus_oper_i_alu_div0__oe__oe[0:0] update \fus_oper_i_alu_div0__oe__ok $0\fus_oper_i_alu_div0__oe__ok[0:0] end - attribute \src "libresoc.v:44248.3-44276.6" - process $proc$libresoc.v:44248$2387 + attribute \src "libresoc.v:44296.3-44324.6" + process $proc$libresoc.v:44296$2387 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__invert_in[0:0] $1\fus_oper_i_alu_div0__invert_in[0:0] - attribute \src "libresoc.v:44249.5-44249.29" + attribute \src "libresoc.v:44297.5-44297.29" switch \initial - attribute \src "libresoc.v:44249.9-44249.17" + attribute \src "libresoc.v:44297.9-44297.17" case 1'1 case end @@ -76639,14 +76675,14 @@ module \core sync always update \fus_oper_i_alu_div0__invert_in $0\fus_oper_i_alu_div0__invert_in[0:0] end - attribute \src "libresoc.v:44277.3-44305.6" - process $proc$libresoc.v:44277$2388 + attribute \src "libresoc.v:44325.3-44353.6" + process $proc$libresoc.v:44325$2388 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__zero_a[0:0] $1\fus_oper_i_alu_div0__zero_a[0:0] - attribute \src "libresoc.v:44278.5-44278.29" + attribute \src "libresoc.v:44326.5-44326.29" switch \initial - attribute \src "libresoc.v:44278.9-44278.17" + attribute \src "libresoc.v:44326.9-44326.17" case 1'1 case end @@ -76684,14 +76720,14 @@ module \core sync always update \fus_oper_i_alu_div0__zero_a $0\fus_oper_i_alu_div0__zero_a[0:0] end - attribute \src "libresoc.v:44306.3-44334.6" - process $proc$libresoc.v:44306$2389 + attribute \src "libresoc.v:44354.3-44382.6" + process $proc$libresoc.v:44354$2389 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__input_carry[1:0] $1\fus_oper_i_alu_div0__input_carry[1:0] - attribute \src "libresoc.v:44307.5-44307.29" + attribute \src "libresoc.v:44355.5-44355.29" switch \initial - attribute \src "libresoc.v:44307.9-44307.17" + attribute \src "libresoc.v:44355.9-44355.17" case 1'1 case end @@ -76729,14 +76765,14 @@ module \core sync always update \fus_oper_i_alu_div0__input_carry $0\fus_oper_i_alu_div0__input_carry[1:0] end - attribute \src "libresoc.v:44335.3-44363.6" - process $proc$libresoc.v:44335$2390 + attribute \src "libresoc.v:44383.3-44411.6" + process $proc$libresoc.v:44383$2390 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__invert_out[0:0] $1\fus_oper_i_alu_div0__invert_out[0:0] - attribute \src "libresoc.v:44336.5-44336.29" + attribute \src "libresoc.v:44384.5-44384.29" switch \initial - attribute \src "libresoc.v:44336.9-44336.17" + attribute \src "libresoc.v:44384.9-44384.17" case 1'1 case end @@ -76774,14 +76810,14 @@ module \core sync always update \fus_oper_i_alu_div0__invert_out $0\fus_oper_i_alu_div0__invert_out[0:0] end - attribute \src "libresoc.v:44364.3-44392.6" - process $proc$libresoc.v:44364$2391 + attribute \src "libresoc.v:44412.3-44440.6" + process $proc$libresoc.v:44412$2391 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__write_cr0[0:0] $1\fus_oper_i_alu_div0__write_cr0[0:0] - attribute \src "libresoc.v:44365.5-44365.29" + attribute \src "libresoc.v:44413.5-44413.29" switch \initial - attribute \src "libresoc.v:44365.9-44365.17" + attribute \src "libresoc.v:44413.9-44413.17" case 1'1 case end @@ -76819,14 +76855,14 @@ module \core sync always update \fus_oper_i_alu_div0__write_cr0 $0\fus_oper_i_alu_div0__write_cr0[0:0] end - attribute \src "libresoc.v:44393.3-44421.6" - process $proc$libresoc.v:44393$2392 + attribute \src "libresoc.v:44441.3-44469.6" + process $proc$libresoc.v:44441$2392 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__output_carry[0:0] $1\fus_oper_i_alu_div0__output_carry[0:0] - attribute \src "libresoc.v:44394.5-44394.29" + attribute \src "libresoc.v:44442.5-44442.29" switch \initial - attribute \src "libresoc.v:44394.9-44394.17" + attribute \src "libresoc.v:44442.9-44442.17" case 1'1 case end @@ -76864,14 +76900,14 @@ module \core sync always update \fus_oper_i_alu_div0__output_carry $0\fus_oper_i_alu_div0__output_carry[0:0] end - attribute \src "libresoc.v:44422.3-44450.6" - process $proc$libresoc.v:44422$2393 + attribute \src "libresoc.v:44470.3-44498.6" + process $proc$libresoc.v:44470$2393 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__is_32bit[0:0] $1\fus_oper_i_alu_div0__is_32bit[0:0] - attribute \src "libresoc.v:44423.5-44423.29" + attribute \src "libresoc.v:44471.5-44471.29" switch \initial - attribute \src "libresoc.v:44423.9-44423.17" + attribute \src "libresoc.v:44471.9-44471.17" case 1'1 case end @@ -76909,14 +76945,14 @@ module \core sync always update \fus_oper_i_alu_div0__is_32bit $0\fus_oper_i_alu_div0__is_32bit[0:0] end - attribute \src "libresoc.v:44451.3-44479.6" - process $proc$libresoc.v:44451$2394 + attribute \src "libresoc.v:44499.3-44527.6" + process $proc$libresoc.v:44499$2394 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__is_signed[0:0] $1\fus_oper_i_alu_div0__is_signed[0:0] - attribute \src "libresoc.v:44452.5-44452.29" + attribute \src "libresoc.v:44500.5-44500.29" switch \initial - attribute \src "libresoc.v:44452.9-44452.17" + attribute \src "libresoc.v:44500.9-44500.17" case 1'1 case end @@ -76954,14 +76990,14 @@ module \core sync always update \fus_oper_i_alu_div0__is_signed $0\fus_oper_i_alu_div0__is_signed[0:0] end - attribute \src "libresoc.v:44480.3-44508.6" - process $proc$libresoc.v:44480$2395 + attribute \src "libresoc.v:44528.3-44556.6" + process $proc$libresoc.v:44528$2395 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__data_len[3:0] $1\fus_oper_i_alu_div0__data_len[3:0] - attribute \src "libresoc.v:44481.5-44481.29" + attribute \src "libresoc.v:44529.5-44529.29" switch \initial - attribute \src "libresoc.v:44481.9-44481.17" + attribute \src "libresoc.v:44529.9-44529.17" case 1'1 case end @@ -76999,14 +77035,14 @@ module \core sync always update \fus_oper_i_alu_div0__data_len $0\fus_oper_i_alu_div0__data_len[3:0] end - attribute \src "libresoc.v:44509.3-44537.6" - process $proc$libresoc.v:44509$2396 + attribute \src "libresoc.v:44557.3-44585.6" + process $proc$libresoc.v:44557$2396 assign { } { } assign { } { } assign $0\fus_oper_i_alu_div0__insn[31:0] $1\fus_oper_i_alu_div0__insn[31:0] - attribute \src "libresoc.v:44510.5-44510.29" + attribute \src "libresoc.v:44558.5-44558.29" switch \initial - attribute \src "libresoc.v:44510.9-44510.17" + attribute \src "libresoc.v:44558.9-44558.17" case 1'1 case end @@ -77044,14 +77080,14 @@ module \core sync always update \fus_oper_i_alu_div0__insn $0\fus_oper_i_alu_div0__insn[31:0] end - attribute \src "libresoc.v:44538.3-44566.6" - process $proc$libresoc.v:44538$2397 + attribute \src "libresoc.v:44586.3-44614.6" + process $proc$libresoc.v:44586$2397 assign { } { } assign { } { } assign $0\fus_cu_issue_i$28[0:0]$2398 $1\fus_cu_issue_i$28[0:0]$2399 - attribute \src "libresoc.v:44539.5-44539.29" + attribute \src "libresoc.v:44587.5-44587.29" switch \initial - attribute \src "libresoc.v:44539.9-44539.17" + attribute \src "libresoc.v:44587.9-44587.17" case 1'1 case end @@ -77089,14 +77125,14 @@ module \core sync always update \fus_cu_issue_i$28 $0\fus_cu_issue_i$28[0:0]$2398 end - attribute \src "libresoc.v:44567.3-44595.6" - process $proc$libresoc.v:44567$2402 + attribute \src "libresoc.v:44615.3-44643.6" + process $proc$libresoc.v:44615$2402 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$30[2:0]$2403 $1\fus_cu_rdmaskn_i$30[2:0]$2404 - attribute \src "libresoc.v:44568.5-44568.29" + attribute \src "libresoc.v:44616.5-44616.29" switch \initial - attribute \src "libresoc.v:44568.9-44568.17" + attribute \src "libresoc.v:44616.9-44616.17" case 1'1 case end @@ -77134,14 +77170,14 @@ module \core sync always update \fus_cu_rdmaskn_i$30 $0\fus_cu_rdmaskn_i$30[2:0]$2403 end - attribute \src "libresoc.v:44596.3-44624.6" - process $proc$libresoc.v:44596$2407 + attribute \src "libresoc.v:44644.3-44672.6" + process $proc$libresoc.v:44644$2407 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__insn_type[6:0] $1\fus_oper_i_alu_mul0__insn_type[6:0] - attribute \src "libresoc.v:44597.5-44597.29" + attribute \src "libresoc.v:44645.5-44645.29" switch \initial - attribute \src "libresoc.v:44597.9-44597.17" + attribute \src "libresoc.v:44645.9-44645.17" case 1'1 case end @@ -77179,14 +77215,14 @@ module \core sync always update \fus_oper_i_alu_mul0__insn_type $0\fus_oper_i_alu_mul0__insn_type[6:0] end - attribute \src "libresoc.v:44625.3-44653.6" - process $proc$libresoc.v:44625$2408 + attribute \src "libresoc.v:44673.3-44701.6" + process $proc$libresoc.v:44673$2408 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__fn_unit[13:0] $1\fus_oper_i_alu_mul0__fn_unit[13:0] - attribute \src "libresoc.v:44626.5-44626.29" + attribute \src "libresoc.v:44674.5-44674.29" switch \initial - attribute \src "libresoc.v:44626.9-44626.17" + attribute \src "libresoc.v:44674.9-44674.17" case 1'1 case end @@ -77224,17 +77260,17 @@ module \core sync always update \fus_oper_i_alu_mul0__fn_unit $0\fus_oper_i_alu_mul0__fn_unit[13:0] end - attribute \src "libresoc.v:44654.3-44683.6" - process $proc$libresoc.v:44654$2409 + attribute \src "libresoc.v:44702.3-44731.6" + process $proc$libresoc.v:44702$2409 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__imm_data__data[63:0] $1\fus_oper_i_alu_mul0__imm_data__data[63:0] assign $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] - attribute \src "libresoc.v:44655.5-44655.29" + attribute \src "libresoc.v:44703.5-44703.29" switch \initial - attribute \src "libresoc.v:44655.9-44655.17" + attribute \src "libresoc.v:44703.9-44703.17" case 1'1 case end @@ -77282,17 +77318,17 @@ module \core update \fus_oper_i_alu_mul0__imm_data__data $0\fus_oper_i_alu_mul0__imm_data__data[63:0] update \fus_oper_i_alu_mul0__imm_data__ok $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] end - attribute \src "libresoc.v:44684.3-44713.6" - process $proc$libresoc.v:44684$2410 + attribute \src "libresoc.v:44732.3-44761.6" + process $proc$libresoc.v:44732$2410 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__rc__ok[0:0] $1\fus_oper_i_alu_mul0__rc__ok[0:0] assign $0\fus_oper_i_alu_mul0__rc__rc[0:0] $1\fus_oper_i_alu_mul0__rc__rc[0:0] - attribute \src "libresoc.v:44685.5-44685.29" + attribute \src "libresoc.v:44733.5-44733.29" switch \initial - attribute \src "libresoc.v:44685.9-44685.17" + attribute \src "libresoc.v:44733.9-44733.17" case 1'1 case end @@ -77340,17 +77376,17 @@ module \core update \fus_oper_i_alu_mul0__rc__ok $0\fus_oper_i_alu_mul0__rc__ok[0:0] update \fus_oper_i_alu_mul0__rc__rc $0\fus_oper_i_alu_mul0__rc__rc[0:0] end - attribute \src "libresoc.v:44714.3-44743.6" - process $proc$libresoc.v:44714$2411 + attribute \src "libresoc.v:44762.3-44791.6" + process $proc$libresoc.v:44762$2411 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__oe__oe[0:0] $1\fus_oper_i_alu_mul0__oe__oe[0:0] assign $0\fus_oper_i_alu_mul0__oe__ok[0:0] $1\fus_oper_i_alu_mul0__oe__ok[0:0] - attribute \src "libresoc.v:44715.5-44715.29" + attribute \src "libresoc.v:44763.5-44763.29" switch \initial - attribute \src "libresoc.v:44715.9-44715.17" + attribute \src "libresoc.v:44763.9-44763.17" case 1'1 case end @@ -77398,14 +77434,14 @@ module \core update \fus_oper_i_alu_mul0__oe__oe $0\fus_oper_i_alu_mul0__oe__oe[0:0] update \fus_oper_i_alu_mul0__oe__ok $0\fus_oper_i_alu_mul0__oe__ok[0:0] end - attribute \src "libresoc.v:44744.3-44772.6" - process $proc$libresoc.v:44744$2412 + attribute \src "libresoc.v:44792.3-44820.6" + process $proc$libresoc.v:44792$2412 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__write_cr0[0:0] $1\fus_oper_i_alu_mul0__write_cr0[0:0] - attribute \src "libresoc.v:44745.5-44745.29" + attribute \src "libresoc.v:44793.5-44793.29" switch \initial - attribute \src "libresoc.v:44745.9-44745.17" + attribute \src "libresoc.v:44793.9-44793.17" case 1'1 case end @@ -77443,14 +77479,14 @@ module \core sync always update \fus_oper_i_alu_mul0__write_cr0 $0\fus_oper_i_alu_mul0__write_cr0[0:0] end - attribute \src "libresoc.v:44773.3-44801.6" - process $proc$libresoc.v:44773$2413 + attribute \src "libresoc.v:44821.3-44849.6" + process $proc$libresoc.v:44821$2413 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__is_32bit[0:0] $1\fus_oper_i_alu_mul0__is_32bit[0:0] - attribute \src "libresoc.v:44774.5-44774.29" + attribute \src "libresoc.v:44822.5-44822.29" switch \initial - attribute \src "libresoc.v:44774.9-44774.17" + attribute \src "libresoc.v:44822.9-44822.17" case 1'1 case end @@ -77488,14 +77524,14 @@ module \core sync always update \fus_oper_i_alu_mul0__is_32bit $0\fus_oper_i_alu_mul0__is_32bit[0:0] end - attribute \src "libresoc.v:44802.3-44830.6" - process $proc$libresoc.v:44802$2414 + attribute \src "libresoc.v:44850.3-44878.6" + process $proc$libresoc.v:44850$2414 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__is_signed[0:0] $1\fus_oper_i_alu_mul0__is_signed[0:0] - attribute \src "libresoc.v:44803.5-44803.29" + attribute \src "libresoc.v:44851.5-44851.29" switch \initial - attribute \src "libresoc.v:44803.9-44803.17" + attribute \src "libresoc.v:44851.9-44851.17" case 1'1 case end @@ -77533,14 +77569,14 @@ module \core sync always update \fus_oper_i_alu_mul0__is_signed $0\fus_oper_i_alu_mul0__is_signed[0:0] end - attribute \src "libresoc.v:44831.3-44859.6" - process $proc$libresoc.v:44831$2415 + attribute \src "libresoc.v:44879.3-44907.6" + process $proc$libresoc.v:44879$2415 assign { } { } assign { } { } assign $0\fus_oper_i_alu_mul0__insn[31:0] $1\fus_oper_i_alu_mul0__insn[31:0] - attribute \src "libresoc.v:44832.5-44832.29" + attribute \src "libresoc.v:44880.5-44880.29" switch \initial - attribute \src "libresoc.v:44832.9-44832.17" + attribute \src "libresoc.v:44880.9-44880.17" case 1'1 case end @@ -77578,14 +77614,14 @@ module \core sync always update \fus_oper_i_alu_mul0__insn $0\fus_oper_i_alu_mul0__insn[31:0] end - attribute \src "libresoc.v:44860.3-44888.6" - process $proc$libresoc.v:44860$2416 + attribute \src "libresoc.v:44908.3-44936.6" + process $proc$libresoc.v:44908$2416 assign { } { } assign { } { } assign $0\fus_cu_issue_i$31[0:0]$2417 $1\fus_cu_issue_i$31[0:0]$2418 - attribute \src "libresoc.v:44861.5-44861.29" + attribute \src "libresoc.v:44909.5-44909.29" switch \initial - attribute \src "libresoc.v:44861.9-44861.17" + attribute \src "libresoc.v:44909.9-44909.17" case 1'1 case end @@ -77623,14 +77659,14 @@ module \core sync always update \fus_cu_issue_i$31 $0\fus_cu_issue_i$31[0:0]$2417 end - attribute \src "libresoc.v:44889.3-44917.6" - process $proc$libresoc.v:44889$2421 + attribute \src "libresoc.v:44937.3-44965.6" + process $proc$libresoc.v:44937$2421 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$33[2:0]$2422 $1\fus_cu_rdmaskn_i$33[2:0]$2423 - attribute \src "libresoc.v:44890.5-44890.29" + attribute \src "libresoc.v:44938.5-44938.29" switch \initial - attribute \src "libresoc.v:44890.9-44890.17" + attribute \src "libresoc.v:44938.9-44938.17" case 1'1 case end @@ -77668,14 +77704,14 @@ module \core sync always update \fus_cu_rdmaskn_i$33 $0\fus_cu_rdmaskn_i$33[2:0]$2422 end - attribute \src "libresoc.v:44918.3-44946.6" - process $proc$libresoc.v:44918$2426 + attribute \src "libresoc.v:44966.3-44994.6" + process $proc$libresoc.v:44966$2426 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] - attribute \src "libresoc.v:44919.5-44919.29" + attribute \src "libresoc.v:44967.5-44967.29" switch \initial - attribute \src "libresoc.v:44919.9-44919.17" + attribute \src "libresoc.v:44967.9-44967.17" case 1'1 case end @@ -77713,14 +77749,14 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__insn_type $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] end - attribute \src "libresoc.v:44947.3-44975.6" - process $proc$libresoc.v:44947$2427 + attribute \src "libresoc.v:44995.3-45023.6" + process $proc$libresoc.v:44995$2427 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__fn_unit[13:0] $1\fus_oper_i_alu_shift_rot0__fn_unit[13:0] - attribute \src "libresoc.v:44948.5-44948.29" + attribute \src "libresoc.v:44996.5-44996.29" switch \initial - attribute \src "libresoc.v:44948.9-44948.17" + attribute \src "libresoc.v:44996.9-44996.17" case 1'1 case end @@ -77758,17 +77794,17 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__fn_unit $0\fus_oper_i_alu_shift_rot0__fn_unit[13:0] end - attribute \src "libresoc.v:44976.3-45005.6" - process $proc$libresoc.v:44976$2428 + attribute \src "libresoc.v:45024.3-45053.6" + process $proc$libresoc.v:45024$2428 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] assign $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] - attribute \src "libresoc.v:44977.5-44977.29" + attribute \src "libresoc.v:45025.5-45025.29" switch \initial - attribute \src "libresoc.v:44977.9-44977.17" + attribute \src "libresoc.v:45025.9-45025.17" case 1'1 case end @@ -77816,17 +77852,17 @@ module \core update \fus_oper_i_alu_shift_rot0__imm_data__data $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] update \fus_oper_i_alu_shift_rot0__imm_data__ok $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] end - attribute \src "libresoc.v:45006.3-45035.6" - process $proc$libresoc.v:45006$2429 + attribute \src "libresoc.v:45054.3-45083.6" + process $proc$libresoc.v:45054$2429 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] assign $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] - attribute \src "libresoc.v:45007.5-45007.29" + attribute \src "libresoc.v:45055.5-45055.29" switch \initial - attribute \src "libresoc.v:45007.9-45007.17" + attribute \src "libresoc.v:45055.9-45055.17" case 1'1 case end @@ -77874,17 +77910,17 @@ module \core update \fus_oper_i_alu_shift_rot0__rc__ok $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] update \fus_oper_i_alu_shift_rot0__rc__rc $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] end - attribute \src "libresoc.v:45036.3-45065.6" - process $proc$libresoc.v:45036$2430 + attribute \src "libresoc.v:45084.3-45113.6" + process $proc$libresoc.v:45084$2430 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] assign $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] - attribute \src "libresoc.v:45037.5-45037.29" + attribute \src "libresoc.v:45085.5-45085.29" switch \initial - attribute \src "libresoc.v:45037.9-45037.17" + attribute \src "libresoc.v:45085.9-45085.17" case 1'1 case end @@ -77932,14 +77968,14 @@ module \core update \fus_oper_i_alu_shift_rot0__oe__oe $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] update \fus_oper_i_alu_shift_rot0__oe__ok $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] end - attribute \src "libresoc.v:45066.3-45094.6" - process $proc$libresoc.v:45066$2431 + attribute \src "libresoc.v:45114.3-45142.6" + process $proc$libresoc.v:45114$2431 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] - attribute \src "libresoc.v:45067.5-45067.29" + attribute \src "libresoc.v:45115.5-45115.29" switch \initial - attribute \src "libresoc.v:45067.9-45067.17" + attribute \src "libresoc.v:45115.9-45115.17" case 1'1 case end @@ -77977,14 +78013,14 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__write_cr0 $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] end - attribute \src "libresoc.v:45095.3-45123.6" - process $proc$libresoc.v:45095$2432 + attribute \src "libresoc.v:45143.3-45171.6" + process $proc$libresoc.v:45143$2432 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__invert_in[0:0] $1\fus_oper_i_alu_shift_rot0__invert_in[0:0] - attribute \src "libresoc.v:45096.5-45096.29" + attribute \src "libresoc.v:45144.5-45144.29" switch \initial - attribute \src "libresoc.v:45096.9-45096.17" + attribute \src "libresoc.v:45144.9-45144.17" case 1'1 case end @@ -78022,14 +78058,14 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__invert_in $0\fus_oper_i_alu_shift_rot0__invert_in[0:0] end - attribute \src "libresoc.v:45124.3-45152.6" - process $proc$libresoc.v:45124$2433 + attribute \src "libresoc.v:45172.3-45200.6" + process $proc$libresoc.v:45172$2433 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] - attribute \src "libresoc.v:45125.5-45125.29" + attribute \src "libresoc.v:45173.5-45173.29" switch \initial - attribute \src "libresoc.v:45125.9-45125.17" + attribute \src "libresoc.v:45173.9-45173.17" case 1'1 case end @@ -78067,14 +78103,14 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__input_carry $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] end - attribute \src "libresoc.v:45153.3-45181.6" - process $proc$libresoc.v:45153$2434 + attribute \src "libresoc.v:45201.3-45229.6" + process $proc$libresoc.v:45201$2434 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] - attribute \src "libresoc.v:45154.5-45154.29" + attribute \src "libresoc.v:45202.5-45202.29" switch \initial - attribute \src "libresoc.v:45154.9-45154.17" + attribute \src "libresoc.v:45202.9-45202.17" case 1'1 case end @@ -78112,14 +78148,14 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__output_carry $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] end - attribute \src "libresoc.v:45182.3-45210.6" - process $proc$libresoc.v:45182$2435 + attribute \src "libresoc.v:45230.3-45258.6" + process $proc$libresoc.v:45230$2435 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] - attribute \src "libresoc.v:45183.5-45183.29" + attribute \src "libresoc.v:45231.5-45231.29" switch \initial - attribute \src "libresoc.v:45183.9-45183.17" + attribute \src "libresoc.v:45231.9-45231.17" case 1'1 case end @@ -78157,14 +78193,14 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__input_cr $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] end - attribute \src "libresoc.v:45211.3-45239.6" - process $proc$libresoc.v:45211$2436 + attribute \src "libresoc.v:45259.3-45287.6" + process $proc$libresoc.v:45259$2436 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] - attribute \src "libresoc.v:45212.5-45212.29" + attribute \src "libresoc.v:45260.5-45260.29" switch \initial - attribute \src "libresoc.v:45212.9-45212.17" + attribute \src "libresoc.v:45260.9-45260.17" case 1'1 case end @@ -78202,14 +78238,14 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__output_cr $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] end - attribute \src "libresoc.v:45240.3-45268.6" - process $proc$libresoc.v:45240$2437 + attribute \src "libresoc.v:45288.3-45316.6" + process $proc$libresoc.v:45288$2437 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] - attribute \src "libresoc.v:45241.5-45241.29" + attribute \src "libresoc.v:45289.5-45289.29" switch \initial - attribute \src "libresoc.v:45241.9-45241.17" + attribute \src "libresoc.v:45289.9-45289.17" case 1'1 case end @@ -78247,14 +78283,14 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__is_32bit $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] end - attribute \src "libresoc.v:45269.3-45297.6" - process $proc$libresoc.v:45269$2438 + attribute \src "libresoc.v:45317.3-45345.6" + process $proc$libresoc.v:45317$2438 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] - attribute \src "libresoc.v:45270.5-45270.29" + attribute \src "libresoc.v:45318.5-45318.29" switch \initial - attribute \src "libresoc.v:45270.9-45270.17" + attribute \src "libresoc.v:45318.9-45318.17" case 1'1 case end @@ -78292,14 +78328,14 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__is_signed $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] end - attribute \src "libresoc.v:45298.3-45326.6" - process $proc$libresoc.v:45298$2439 + attribute \src "libresoc.v:45346.3-45374.6" + process $proc$libresoc.v:45346$2439 assign { } { } assign { } { } assign $0\fus_oper_i_alu_shift_rot0__insn[31:0] $1\fus_oper_i_alu_shift_rot0__insn[31:0] - attribute \src "libresoc.v:45299.5-45299.29" + attribute \src "libresoc.v:45347.5-45347.29" switch \initial - attribute \src "libresoc.v:45299.9-45299.17" + attribute \src "libresoc.v:45347.9-45347.17" case 1'1 case end @@ -78337,14 +78373,14 @@ module \core sync always update \fus_oper_i_alu_shift_rot0__insn $0\fus_oper_i_alu_shift_rot0__insn[31:0] end - attribute \src "libresoc.v:45327.3-45355.6" - process $proc$libresoc.v:45327$2440 + attribute \src "libresoc.v:45375.3-45403.6" + process $proc$libresoc.v:45375$2440 assign { } { } assign { } { } assign $0\fus_cu_issue_i$34[0:0]$2441 $1\fus_cu_issue_i$34[0:0]$2442 - attribute \src "libresoc.v:45328.5-45328.29" + attribute \src "libresoc.v:45376.5-45376.29" switch \initial - attribute \src "libresoc.v:45328.9-45328.17" + attribute \src "libresoc.v:45376.9-45376.17" case 1'1 case end @@ -78382,14 +78418,14 @@ module \core sync always update \fus_cu_issue_i$34 $0\fus_cu_issue_i$34[0:0]$2441 end - attribute \src "libresoc.v:45356.3-45384.6" - process $proc$libresoc.v:45356$2445 + attribute \src "libresoc.v:45404.3-45432.6" + process $proc$libresoc.v:45404$2445 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$36[4:0]$2446 $1\fus_cu_rdmaskn_i$36[4:0]$2447 - attribute \src "libresoc.v:45357.5-45357.29" + attribute \src "libresoc.v:45405.5-45405.29" switch \initial - attribute \src "libresoc.v:45357.9-45357.17" + attribute \src "libresoc.v:45405.9-45405.17" case 1'1 case end @@ -78427,14 +78463,14 @@ module \core sync always update \fus_cu_rdmaskn_i$36 $0\fus_cu_rdmaskn_i$36[4:0]$2446 end - attribute \src "libresoc.v:45385.3-45413.6" - process $proc$libresoc.v:45385$2450 + attribute \src "libresoc.v:45433.3-45461.6" + process $proc$libresoc.v:45433$2450 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__insn_type[6:0] $1\fus_oper_i_ldst_ldst0__insn_type[6:0] - attribute \src "libresoc.v:45386.5-45386.29" + attribute \src "libresoc.v:45434.5-45434.29" switch \initial - attribute \src "libresoc.v:45386.9-45386.17" + attribute \src "libresoc.v:45434.9-45434.17" case 1'1 case end @@ -78472,14 +78508,14 @@ module \core sync always update \fus_oper_i_ldst_ldst0__insn_type $0\fus_oper_i_ldst_ldst0__insn_type[6:0] end - attribute \src "libresoc.v:45414.3-45442.6" - process $proc$libresoc.v:45414$2451 + attribute \src "libresoc.v:45462.3-45490.6" + process $proc$libresoc.v:45462$2451 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__fn_unit[13:0] $1\fus_oper_i_ldst_ldst0__fn_unit[13:0] - attribute \src "libresoc.v:45415.5-45415.29" + attribute \src "libresoc.v:45463.5-45463.29" switch \initial - attribute \src "libresoc.v:45415.9-45415.17" + attribute \src "libresoc.v:45463.9-45463.17" case 1'1 case end @@ -78517,17 +78553,17 @@ module \core sync always update \fus_oper_i_ldst_ldst0__fn_unit $0\fus_oper_i_ldst_ldst0__fn_unit[13:0] end - attribute \src "libresoc.v:45443.3-45472.6" - process $proc$libresoc.v:45443$2452 + attribute \src "libresoc.v:45491.3-45520.6" + process $proc$libresoc.v:45491$2452 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] assign $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] - attribute \src "libresoc.v:45444.5-45444.29" + attribute \src "libresoc.v:45492.5-45492.29" switch \initial - attribute \src "libresoc.v:45444.9-45444.17" + attribute \src "libresoc.v:45492.9-45492.17" case 1'1 case end @@ -78575,14 +78611,14 @@ module \core update \fus_oper_i_ldst_ldst0__imm_data__data $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] update \fus_oper_i_ldst_ldst0__imm_data__ok $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] end - attribute \src "libresoc.v:45473.3-45501.6" - process $proc$libresoc.v:45473$2453 + attribute \src "libresoc.v:45521.3-45549.6" + process $proc$libresoc.v:45521$2453 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__zero_a[0:0] $1\fus_oper_i_ldst_ldst0__zero_a[0:0] - attribute \src "libresoc.v:45474.5-45474.29" + attribute \src "libresoc.v:45522.5-45522.29" switch \initial - attribute \src "libresoc.v:45474.9-45474.17" + attribute \src "libresoc.v:45522.9-45522.17" case 1'1 case end @@ -78620,17 +78656,17 @@ module \core sync always update \fus_oper_i_ldst_ldst0__zero_a $0\fus_oper_i_ldst_ldst0__zero_a[0:0] end - attribute \src "libresoc.v:45502.3-45531.6" - process $proc$libresoc.v:45502$2454 + attribute \src "libresoc.v:45550.3-45579.6" + process $proc$libresoc.v:45550$2454 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] assign $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] - attribute \src "libresoc.v:45503.5-45503.29" + attribute \src "libresoc.v:45551.5-45551.29" switch \initial - attribute \src "libresoc.v:45503.9-45503.17" + attribute \src "libresoc.v:45551.9-45551.17" case 1'1 case end @@ -78678,17 +78714,17 @@ module \core update \fus_oper_i_ldst_ldst0__rc__ok $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] update \fus_oper_i_ldst_ldst0__rc__rc $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] end - attribute \src "libresoc.v:45532.3-45561.6" - process $proc$libresoc.v:45532$2455 + attribute \src "libresoc.v:45580.3-45609.6" + process $proc$libresoc.v:45580$2455 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] assign $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] - attribute \src "libresoc.v:45533.5-45533.29" + attribute \src "libresoc.v:45581.5-45581.29" switch \initial - attribute \src "libresoc.v:45533.9-45533.17" + attribute \src "libresoc.v:45581.9-45581.17" case 1'1 case end @@ -78736,14 +78772,14 @@ module \core update \fus_oper_i_ldst_ldst0__oe__oe $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] update \fus_oper_i_ldst_ldst0__oe__ok $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] end - attribute \src "libresoc.v:45562.3-45590.6" - process $proc$libresoc.v:45562$2456 + attribute \src "libresoc.v:45610.3-45638.6" + process $proc$libresoc.v:45610$2456 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] - attribute \src "libresoc.v:45563.5-45563.29" + attribute \src "libresoc.v:45611.5-45611.29" switch \initial - attribute \src "libresoc.v:45563.9-45563.17" + attribute \src "libresoc.v:45611.9-45611.17" case 1'1 case end @@ -78781,14 +78817,14 @@ module \core sync always update \fus_oper_i_ldst_ldst0__is_32bit $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] end - attribute \src "libresoc.v:45591.3-45619.6" - process $proc$libresoc.v:45591$2457 + attribute \src "libresoc.v:45639.3-45667.6" + process $proc$libresoc.v:45639$2457 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__is_signed[0:0] $1\fus_oper_i_ldst_ldst0__is_signed[0:0] - attribute \src "libresoc.v:45592.5-45592.29" + attribute \src "libresoc.v:45640.5-45640.29" switch \initial - attribute \src "libresoc.v:45592.9-45592.17" + attribute \src "libresoc.v:45640.9-45640.17" case 1'1 case end @@ -78826,14 +78862,14 @@ module \core sync always update \fus_oper_i_ldst_ldst0__is_signed $0\fus_oper_i_ldst_ldst0__is_signed[0:0] end - attribute \src "libresoc.v:45620.3-45648.6" - process $proc$libresoc.v:45620$2458 + attribute \src "libresoc.v:45668.3-45696.6" + process $proc$libresoc.v:45668$2458 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__data_len[3:0] $1\fus_oper_i_ldst_ldst0__data_len[3:0] - attribute \src "libresoc.v:45621.5-45621.29" + attribute \src "libresoc.v:45669.5-45669.29" switch \initial - attribute \src "libresoc.v:45621.9-45621.17" + attribute \src "libresoc.v:45669.9-45669.17" case 1'1 case end @@ -78871,14 +78907,14 @@ module \core sync always update \fus_oper_i_ldst_ldst0__data_len $0\fus_oper_i_ldst_ldst0__data_len[3:0] end - attribute \src "libresoc.v:45649.3-45677.6" - process $proc$libresoc.v:45649$2459 + attribute \src "libresoc.v:45697.3-45725.6" + process $proc$libresoc.v:45697$2459 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] - attribute \src "libresoc.v:45650.5-45650.29" + attribute \src "libresoc.v:45698.5-45698.29" switch \initial - attribute \src "libresoc.v:45650.9-45650.17" + attribute \src "libresoc.v:45698.9-45698.17" case 1'1 case end @@ -78916,14 +78952,14 @@ module \core sync always update \fus_oper_i_ldst_ldst0__byte_reverse $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] end - attribute \src "libresoc.v:45678.3-45706.6" - process $proc$libresoc.v:45678$2460 + attribute \src "libresoc.v:45726.3-45754.6" + process $proc$libresoc.v:45726$2460 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] - attribute \src "libresoc.v:45679.5-45679.29" + attribute \src "libresoc.v:45727.5-45727.29" switch \initial - attribute \src "libresoc.v:45679.9-45679.17" + attribute \src "libresoc.v:45727.9-45727.17" case 1'1 case end @@ -78961,14 +78997,14 @@ module \core sync always update \fus_oper_i_ldst_ldst0__sign_extend $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] end - attribute \src "libresoc.v:45707.3-45735.6" - process $proc$libresoc.v:45707$2461 + attribute \src "libresoc.v:45755.3-45783.6" + process $proc$libresoc.v:45755$2461 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] - attribute \src "libresoc.v:45708.5-45708.29" + attribute \src "libresoc.v:45756.5-45756.29" switch \initial - attribute \src "libresoc.v:45708.9-45708.17" + attribute \src "libresoc.v:45756.9-45756.17" case 1'1 case end @@ -79006,14 +79042,14 @@ module \core sync always update \fus_oper_i_ldst_ldst0__ldst_mode $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] end - attribute \src "libresoc.v:45736.3-45764.6" - process $proc$libresoc.v:45736$2462 + attribute \src "libresoc.v:45784.3-45812.6" + process $proc$libresoc.v:45784$2462 assign { } { } assign { } { } assign $0\fus_oper_i_ldst_ldst0__insn[31:0] $1\fus_oper_i_ldst_ldst0__insn[31:0] - attribute \src "libresoc.v:45737.5-45737.29" + attribute \src "libresoc.v:45785.5-45785.29" switch \initial - attribute \src "libresoc.v:45737.9-45737.17" + attribute \src "libresoc.v:45785.9-45785.17" case 1'1 case end @@ -79051,14 +79087,14 @@ module \core sync always update \fus_oper_i_ldst_ldst0__insn $0\fus_oper_i_ldst_ldst0__insn[31:0] end - attribute \src "libresoc.v:45765.3-45793.6" - process $proc$libresoc.v:45765$2463 + attribute \src "libresoc.v:45813.3-45841.6" + process $proc$libresoc.v:45813$2463 assign { } { } assign { } { } assign $0\fus_cu_issue_i$37[0:0]$2464 $1\fus_cu_issue_i$37[0:0]$2465 - attribute \src "libresoc.v:45766.5-45766.29" + attribute \src "libresoc.v:45814.5-45814.29" switch \initial - attribute \src "libresoc.v:45766.9-45766.17" + attribute \src "libresoc.v:45814.9-45814.17" case 1'1 case end @@ -79096,14 +79132,14 @@ module \core sync always update \fus_cu_issue_i$37 $0\fus_cu_issue_i$37[0:0]$2464 end - attribute \src "libresoc.v:45794.3-45822.6" - process $proc$libresoc.v:45794$2468 + attribute \src "libresoc.v:45842.3-45870.6" + process $proc$libresoc.v:45842$2468 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$39[2:0]$2469 $1\fus_cu_rdmaskn_i$39[2:0]$2470 - attribute \src "libresoc.v:45795.5-45795.29" + attribute \src "libresoc.v:45843.5-45843.29" switch \initial - attribute \src "libresoc.v:45795.9-45795.17" + attribute \src "libresoc.v:45843.9-45843.17" case 1'1 case end @@ -79141,14 +79177,14 @@ module \core sync always update \fus_cu_rdmaskn_i$39 $0\fus_cu_rdmaskn_i$39[2:0]$2469 end - attribute \src "libresoc.v:45823.3-45831.6" - process $proc$libresoc.v:45823$2473 + attribute \src "libresoc.v:45871.3-45879.6" + process $proc$libresoc.v:45871$2473 assign { } { } assign { } { } assign $0\dp_INT_ra_alu0_0$next[0:0]$2474 $1\dp_INT_ra_alu0_0$next[0:0]$2475 - attribute \src "libresoc.v:45824.5-45824.29" + attribute \src "libresoc.v:45872.5-45872.29" switch \initial - attribute \src "libresoc.v:45824.9-45824.17" + attribute \src "libresoc.v:45872.9-45872.17" case 1'1 case end @@ -79164,14 +79200,14 @@ module \core sync always update \dp_INT_ra_alu0_0$next $0\dp_INT_ra_alu0_0$next[0:0]$2474 end - attribute \src "libresoc.v:45832.3-45841.6" - process $proc$libresoc.v:45832$2476 + attribute \src "libresoc.v:45880.3-45889.6" + process $proc$libresoc.v:45880$2476 assign { } { } assign { } { } assign $0\fus_src1_i[63:0] $1\fus_src1_i[63:0] - attribute \src "libresoc.v:45833.5-45833.29" + attribute \src "libresoc.v:45881.5-45881.29" switch \initial - attribute \src "libresoc.v:45833.9-45833.17" + attribute \src "libresoc.v:45881.9-45881.17" case 1'1 case end @@ -79187,14 +79223,14 @@ module \core sync always update \fus_src1_i $0\fus_src1_i[63:0] end - attribute \src "libresoc.v:45842.3-45850.6" - process $proc$libresoc.v:45842$2477 + attribute \src "libresoc.v:45890.3-45898.6" + process $proc$libresoc.v:45890$2477 assign { } { } assign { } { } assign $0\dp_INT_ra_cr0_1$next[0:0]$2478 $1\dp_INT_ra_cr0_1$next[0:0]$2479 - attribute \src "libresoc.v:45843.5-45843.29" + attribute \src "libresoc.v:45891.5-45891.29" switch \initial - attribute \src "libresoc.v:45843.9-45843.17" + attribute \src "libresoc.v:45891.9-45891.17" case 1'1 case end @@ -79210,14 +79246,14 @@ module \core sync always update \dp_INT_ra_cr0_1$next $0\dp_INT_ra_cr0_1$next[0:0]$2478 end - attribute \src "libresoc.v:45851.3-45860.6" - process $proc$libresoc.v:45851$2480 + attribute \src "libresoc.v:45899.3-45908.6" + process $proc$libresoc.v:45899$2480 assign { } { } assign { } { } assign $0\fus_src1_i$42[63:0]$2481 $1\fus_src1_i$42[63:0]$2482 - attribute \src "libresoc.v:45852.5-45852.29" + attribute \src "libresoc.v:45900.5-45900.29" switch \initial - attribute \src "libresoc.v:45852.9-45852.17" + attribute \src "libresoc.v:45900.9-45900.17" case 1'1 case end @@ -79233,14 +79269,14 @@ module \core sync always update \fus_src1_i$42 $0\fus_src1_i$42[63:0]$2481 end - attribute \src "libresoc.v:45861.3-45869.6" - process $proc$libresoc.v:45861$2483 + attribute \src "libresoc.v:45909.3-45917.6" + process $proc$libresoc.v:45909$2483 assign { } { } assign { } { } assign $0\dp_INT_ra_trap0_2$next[0:0]$2484 $1\dp_INT_ra_trap0_2$next[0:0]$2485 - attribute \src "libresoc.v:45862.5-45862.29" + attribute \src "libresoc.v:45910.5-45910.29" switch \initial - attribute \src "libresoc.v:45862.9-45862.17" + attribute \src "libresoc.v:45910.9-45910.17" case 1'1 case end @@ -79256,14 +79292,14 @@ module \core sync always update \dp_INT_ra_trap0_2$next $0\dp_INT_ra_trap0_2$next[0:0]$2484 end - attribute \src "libresoc.v:45870.3-45879.6" - process $proc$libresoc.v:45870$2486 + attribute \src "libresoc.v:45918.3-45927.6" + process $proc$libresoc.v:45918$2486 assign { } { } assign { } { } assign $0\fus_src1_i$45[63:0]$2487 $1\fus_src1_i$45[63:0]$2488 - attribute \src "libresoc.v:45871.5-45871.29" + attribute \src "libresoc.v:45919.5-45919.29" switch \initial - attribute \src "libresoc.v:45871.9-45871.17" + attribute \src "libresoc.v:45919.9-45919.17" case 1'1 case end @@ -79279,14 +79315,14 @@ module \core sync always update \fus_src1_i$45 $0\fus_src1_i$45[63:0]$2487 end - attribute \src "libresoc.v:45880.3-45888.6" - process $proc$libresoc.v:45880$2489 + attribute \src "libresoc.v:45928.3-45936.6" + process $proc$libresoc.v:45928$2489 assign { } { } assign { } { } assign $0\dp_INT_ra_logical0_3$next[0:0]$2490 $1\dp_INT_ra_logical0_3$next[0:0]$2491 - attribute \src "libresoc.v:45881.5-45881.29" + attribute \src "libresoc.v:45929.5-45929.29" switch \initial - attribute \src "libresoc.v:45881.9-45881.17" + attribute \src "libresoc.v:45929.9-45929.17" case 1'1 case end @@ -79302,14 +79338,14 @@ module \core sync always update \dp_INT_ra_logical0_3$next $0\dp_INT_ra_logical0_3$next[0:0]$2490 end - attribute \src "libresoc.v:45889.3-45898.6" - process $proc$libresoc.v:45889$2492 + attribute \src "libresoc.v:45937.3-45946.6" + process $proc$libresoc.v:45937$2492 assign { } { } assign { } { } assign $0\fus_src1_i$48[63:0]$2493 $1\fus_src1_i$48[63:0]$2494 - attribute \src "libresoc.v:45890.5-45890.29" + attribute \src "libresoc.v:45938.5-45938.29" switch \initial - attribute \src "libresoc.v:45890.9-45890.17" + attribute \src "libresoc.v:45938.9-45938.17" case 1'1 case end @@ -79325,14 +79361,14 @@ module \core sync always update \fus_src1_i$48 $0\fus_src1_i$48[63:0]$2493 end - attribute \src "libresoc.v:45899.3-45907.6" - process $proc$libresoc.v:45899$2495 + attribute \src "libresoc.v:45947.3-45955.6" + process $proc$libresoc.v:45947$2495 assign { } { } assign { } { } assign $0\dp_INT_ra_spr0_4$next[0:0]$2496 $1\dp_INT_ra_spr0_4$next[0:0]$2497 - attribute \src "libresoc.v:45900.5-45900.29" + attribute \src "libresoc.v:45948.5-45948.29" switch \initial - attribute \src "libresoc.v:45900.9-45900.17" + attribute \src "libresoc.v:45948.9-45948.17" case 1'1 case end @@ -79348,14 +79384,14 @@ module \core sync always update \dp_INT_ra_spr0_4$next $0\dp_INT_ra_spr0_4$next[0:0]$2496 end - attribute \src "libresoc.v:45908.3-45917.6" - process $proc$libresoc.v:45908$2498 + attribute \src "libresoc.v:45956.3-45965.6" + process $proc$libresoc.v:45956$2498 assign { } { } assign { } { } assign $0\fus_src1_i$51[63:0]$2499 $1\fus_src1_i$51[63:0]$2500 - attribute \src "libresoc.v:45909.5-45909.29" + attribute \src "libresoc.v:45957.5-45957.29" switch \initial - attribute \src "libresoc.v:45909.9-45909.17" + attribute \src "libresoc.v:45957.9-45957.17" case 1'1 case end @@ -79371,14 +79407,14 @@ module \core sync always update \fus_src1_i$51 $0\fus_src1_i$51[63:0]$2499 end - attribute \src "libresoc.v:45918.3-45926.6" - process $proc$libresoc.v:45918$2501 + attribute \src "libresoc.v:45966.3-45974.6" + process $proc$libresoc.v:45966$2501 assign { } { } assign { } { } assign $0\dp_INT_ra_div0_5$next[0:0]$2502 $1\dp_INT_ra_div0_5$next[0:0]$2503 - attribute \src "libresoc.v:45919.5-45919.29" + attribute \src "libresoc.v:45967.5-45967.29" switch \initial - attribute \src "libresoc.v:45919.9-45919.17" + attribute \src "libresoc.v:45967.9-45967.17" case 1'1 case end @@ -79394,14 +79430,14 @@ module \core sync always update \dp_INT_ra_div0_5$next $0\dp_INT_ra_div0_5$next[0:0]$2502 end - attribute \src "libresoc.v:45927.3-45936.6" - process $proc$libresoc.v:45927$2504 + attribute \src "libresoc.v:45975.3-45984.6" + process $proc$libresoc.v:45975$2504 assign { } { } assign { } { } assign $0\fus_src1_i$54[63:0]$2505 $1\fus_src1_i$54[63:0]$2506 - attribute \src "libresoc.v:45928.5-45928.29" + attribute \src "libresoc.v:45976.5-45976.29" switch \initial - attribute \src "libresoc.v:45928.9-45928.17" + attribute \src "libresoc.v:45976.9-45976.17" case 1'1 case end @@ -79417,14 +79453,14 @@ module \core sync always update \fus_src1_i$54 $0\fus_src1_i$54[63:0]$2505 end - attribute \src "libresoc.v:45937.3-45945.6" - process $proc$libresoc.v:45937$2507 + attribute \src "libresoc.v:45985.3-45993.6" + process $proc$libresoc.v:45985$2507 assign { } { } assign { } { } assign $0\dp_INT_ra_mul0_6$next[0:0]$2508 $1\dp_INT_ra_mul0_6$next[0:0]$2509 - attribute \src "libresoc.v:45938.5-45938.29" + attribute \src "libresoc.v:45986.5-45986.29" switch \initial - attribute \src "libresoc.v:45938.9-45938.17" + attribute \src "libresoc.v:45986.9-45986.17" case 1'1 case end @@ -79440,14 +79476,14 @@ module \core sync always update \dp_INT_ra_mul0_6$next $0\dp_INT_ra_mul0_6$next[0:0]$2508 end - attribute \src "libresoc.v:45946.3-45955.6" - process $proc$libresoc.v:45946$2510 + attribute \src "libresoc.v:45994.3-46003.6" + process $proc$libresoc.v:45994$2510 assign { } { } assign { } { } assign $0\fus_src1_i$57[63:0]$2511 $1\fus_src1_i$57[63:0]$2512 - attribute \src "libresoc.v:45947.5-45947.29" + attribute \src "libresoc.v:45995.5-45995.29" switch \initial - attribute \src "libresoc.v:45947.9-45947.17" + attribute \src "libresoc.v:45995.9-45995.17" case 1'1 case end @@ -79463,14 +79499,14 @@ module \core sync always update \fus_src1_i$57 $0\fus_src1_i$57[63:0]$2511 end - attribute \src "libresoc.v:45956.3-45964.6" - process $proc$libresoc.v:45956$2513 + attribute \src "libresoc.v:46004.3-46012.6" + process $proc$libresoc.v:46004$2513 assign { } { } assign { } { } assign $0\dp_INT_ra_shiftrot0_7$next[0:0]$2514 $1\dp_INT_ra_shiftrot0_7$next[0:0]$2515 - attribute \src "libresoc.v:45957.5-45957.29" + attribute \src "libresoc.v:46005.5-46005.29" switch \initial - attribute \src "libresoc.v:45957.9-45957.17" + attribute \src "libresoc.v:46005.9-46005.17" case 1'1 case end @@ -79486,14 +79522,14 @@ module \core sync always update \dp_INT_ra_shiftrot0_7$next $0\dp_INT_ra_shiftrot0_7$next[0:0]$2514 end - attribute \src "libresoc.v:45965.3-45974.6" - process $proc$libresoc.v:45965$2516 + attribute \src "libresoc.v:46013.3-46022.6" + process $proc$libresoc.v:46013$2516 assign { } { } assign { } { } assign $0\fus_src1_i$60[63:0]$2517 $1\fus_src1_i$60[63:0]$2518 - attribute \src "libresoc.v:45966.5-45966.29" + attribute \src "libresoc.v:46014.5-46014.29" switch \initial - attribute \src "libresoc.v:45966.9-45966.17" + attribute \src "libresoc.v:46014.9-46014.17" case 1'1 case end @@ -79509,14 +79545,14 @@ module \core sync always update \fus_src1_i$60 $0\fus_src1_i$60[63:0]$2517 end - attribute \src "libresoc.v:45975.3-45983.6" - process $proc$libresoc.v:45975$2519 + attribute \src "libresoc.v:46023.3-46031.6" + process $proc$libresoc.v:46023$2519 assign { } { } assign { } { } assign $0\dp_INT_ra_ldst0_8$next[0:0]$2520 $1\dp_INT_ra_ldst0_8$next[0:0]$2521 - attribute \src "libresoc.v:45976.5-45976.29" + attribute \src "libresoc.v:46024.5-46024.29" switch \initial - attribute \src "libresoc.v:45976.9-45976.17" + attribute \src "libresoc.v:46024.9-46024.17" case 1'1 case end @@ -79532,14 +79568,14 @@ module \core sync always update \dp_INT_ra_ldst0_8$next $0\dp_INT_ra_ldst0_8$next[0:0]$2520 end - attribute \src "libresoc.v:45984.3-45993.6" - process $proc$libresoc.v:45984$2522 + attribute \src "libresoc.v:46032.3-46041.6" + process $proc$libresoc.v:46032$2522 assign { } { } assign { } { } assign $0\fus_src1_i$63[63:0]$2523 $1\fus_src1_i$63[63:0]$2524 - attribute \src "libresoc.v:45985.5-45985.29" + attribute \src "libresoc.v:46033.5-46033.29" switch \initial - attribute \src "libresoc.v:45985.9-45985.17" + attribute \src "libresoc.v:46033.9-46033.17" case 1'1 case end @@ -79555,14 +79591,14 @@ module \core sync always update \fus_src1_i$63 $0\fus_src1_i$63[63:0]$2523 end - attribute \src "libresoc.v:45994.3-46002.6" - process $proc$libresoc.v:45994$2525 + attribute \src "libresoc.v:46042.3-46050.6" + process $proc$libresoc.v:46042$2525 assign { } { } assign { } { } assign $0\dp_INT_rb_alu0_0$next[0:0]$2526 $1\dp_INT_rb_alu0_0$next[0:0]$2527 - attribute \src "libresoc.v:45995.5-45995.29" + attribute \src "libresoc.v:46043.5-46043.29" switch \initial - attribute \src "libresoc.v:45995.9-45995.17" + attribute \src "libresoc.v:46043.9-46043.17" case 1'1 case end @@ -79578,14 +79614,14 @@ module \core sync always update \dp_INT_rb_alu0_0$next $0\dp_INT_rb_alu0_0$next[0:0]$2526 end - attribute \src "libresoc.v:46003.3-46012.6" - process $proc$libresoc.v:46003$2528 + attribute \src "libresoc.v:46051.3-46060.6" + process $proc$libresoc.v:46051$2528 assign { } { } assign { } { } assign $0\fus_src2_i[63:0] $1\fus_src2_i[63:0] - attribute \src "libresoc.v:46004.5-46004.29" + attribute \src "libresoc.v:46052.5-46052.29" switch \initial - attribute \src "libresoc.v:46004.9-46004.17" + attribute \src "libresoc.v:46052.9-46052.17" case 1'1 case end @@ -79601,14 +79637,14 @@ module \core sync always update \fus_src2_i $0\fus_src2_i[63:0] end - attribute \src "libresoc.v:46013.3-46021.6" - process $proc$libresoc.v:46013$2529 + attribute \src "libresoc.v:46061.3-46069.6" + process $proc$libresoc.v:46061$2529 assign { } { } assign { } { } assign $0\dp_INT_rb_cr0_1$next[0:0]$2530 $1\dp_INT_rb_cr0_1$next[0:0]$2531 - attribute \src "libresoc.v:46014.5-46014.29" + attribute \src "libresoc.v:46062.5-46062.29" switch \initial - attribute \src "libresoc.v:46014.9-46014.17" + attribute \src "libresoc.v:46062.9-46062.17" case 1'1 case end @@ -79624,14 +79660,14 @@ module \core sync always update \dp_INT_rb_cr0_1$next $0\dp_INT_rb_cr0_1$next[0:0]$2530 end - attribute \src "libresoc.v:46022.3-46031.6" - process $proc$libresoc.v:46022$2532 + attribute \src "libresoc.v:46070.3-46079.6" + process $proc$libresoc.v:46070$2532 assign { } { } assign { } { } assign $0\fus_src2_i$64[63:0]$2533 $1\fus_src2_i$64[63:0]$2534 - attribute \src "libresoc.v:46023.5-46023.29" + attribute \src "libresoc.v:46071.5-46071.29" switch \initial - attribute \src "libresoc.v:46023.9-46023.17" + attribute \src "libresoc.v:46071.9-46071.17" case 1'1 case end @@ -79647,14 +79683,14 @@ module \core sync always update \fus_src2_i$64 $0\fus_src2_i$64[63:0]$2533 end - attribute \src "libresoc.v:46032.3-46040.6" - process $proc$libresoc.v:46032$2535 + attribute \src "libresoc.v:46080.3-46088.6" + process $proc$libresoc.v:46080$2535 assign { } { } assign { } { } assign $0\dp_INT_rb_trap0_2$next[0:0]$2536 $1\dp_INT_rb_trap0_2$next[0:0]$2537 - attribute \src "libresoc.v:46033.5-46033.29" + attribute \src "libresoc.v:46081.5-46081.29" switch \initial - attribute \src "libresoc.v:46033.9-46033.17" + attribute \src "libresoc.v:46081.9-46081.17" case 1'1 case end @@ -79670,14 +79706,14 @@ module \core sync always update \dp_INT_rb_trap0_2$next $0\dp_INT_rb_trap0_2$next[0:0]$2536 end - attribute \src "libresoc.v:46041.3-46050.6" - process $proc$libresoc.v:46041$2538 + attribute \src "libresoc.v:46089.3-46098.6" + process $proc$libresoc.v:46089$2538 assign { } { } assign { } { } assign $0\fus_src2_i$65[63:0]$2539 $1\fus_src2_i$65[63:0]$2540 - attribute \src "libresoc.v:46042.5-46042.29" + attribute \src "libresoc.v:46090.5-46090.29" switch \initial - attribute \src "libresoc.v:46042.9-46042.17" + attribute \src "libresoc.v:46090.9-46090.17" case 1'1 case end @@ -79693,14 +79729,14 @@ module \core sync always update \fus_src2_i$65 $0\fus_src2_i$65[63:0]$2539 end - attribute \src "libresoc.v:46051.3-46059.6" - process $proc$libresoc.v:46051$2541 + attribute \src "libresoc.v:46099.3-46107.6" + process $proc$libresoc.v:46099$2541 assign { } { } assign { } { } assign $0\dp_INT_rb_logical0_3$next[0:0]$2542 $1\dp_INT_rb_logical0_3$next[0:0]$2543 - attribute \src "libresoc.v:46052.5-46052.29" + attribute \src "libresoc.v:46100.5-46100.29" switch \initial - attribute \src "libresoc.v:46052.9-46052.17" + attribute \src "libresoc.v:46100.9-46100.17" case 1'1 case end @@ -79716,14 +79752,14 @@ module \core sync always update \dp_INT_rb_logical0_3$next $0\dp_INT_rb_logical0_3$next[0:0]$2542 end - attribute \src "libresoc.v:46060.3-46069.6" - process $proc$libresoc.v:46060$2544 + attribute \src "libresoc.v:46108.3-46117.6" + process $proc$libresoc.v:46108$2544 assign { } { } assign { } { } assign $0\fus_src2_i$66[63:0]$2545 $1\fus_src2_i$66[63:0]$2546 - attribute \src "libresoc.v:46061.5-46061.29" + attribute \src "libresoc.v:46109.5-46109.29" switch \initial - attribute \src "libresoc.v:46061.9-46061.17" + attribute \src "libresoc.v:46109.9-46109.17" case 1'1 case end @@ -79739,14 +79775,14 @@ module \core sync always update \fus_src2_i$66 $0\fus_src2_i$66[63:0]$2545 end - attribute \src "libresoc.v:46070.3-46078.6" - process $proc$libresoc.v:46070$2547 + attribute \src "libresoc.v:46118.3-46126.6" + process $proc$libresoc.v:46118$2547 assign { } { } assign { } { } assign $0\dp_INT_rb_div0_4$next[0:0]$2548 $1\dp_INT_rb_div0_4$next[0:0]$2549 - attribute \src "libresoc.v:46071.5-46071.29" + attribute \src "libresoc.v:46119.5-46119.29" switch \initial - attribute \src "libresoc.v:46071.9-46071.17" + attribute \src "libresoc.v:46119.9-46119.17" case 1'1 case end @@ -79762,14 +79798,14 @@ module \core sync always update \dp_INT_rb_div0_4$next $0\dp_INT_rb_div0_4$next[0:0]$2548 end - attribute \src "libresoc.v:46079.3-46088.6" - process $proc$libresoc.v:46079$2550 + attribute \src "libresoc.v:46127.3-46136.6" + process $proc$libresoc.v:46127$2550 assign { } { } assign { } { } assign $0\fus_src2_i$67[63:0]$2551 $1\fus_src2_i$67[63:0]$2552 - attribute \src "libresoc.v:46080.5-46080.29" + attribute \src "libresoc.v:46128.5-46128.29" switch \initial - attribute \src "libresoc.v:46080.9-46080.17" + attribute \src "libresoc.v:46128.9-46128.17" case 1'1 case end @@ -79785,14 +79821,14 @@ module \core sync always update \fus_src2_i$67 $0\fus_src2_i$67[63:0]$2551 end - attribute \src "libresoc.v:46089.3-46097.6" - process $proc$libresoc.v:46089$2553 + attribute \src "libresoc.v:46137.3-46145.6" + process $proc$libresoc.v:46137$2553 assign { } { } assign { } { } assign $0\dp_INT_rb_mul0_5$next[0:0]$2554 $1\dp_INT_rb_mul0_5$next[0:0]$2555 - attribute \src "libresoc.v:46090.5-46090.29" + attribute \src "libresoc.v:46138.5-46138.29" switch \initial - attribute \src "libresoc.v:46090.9-46090.17" + attribute \src "libresoc.v:46138.9-46138.17" case 1'1 case end @@ -79808,14 +79844,14 @@ module \core sync always update \dp_INT_rb_mul0_5$next $0\dp_INT_rb_mul0_5$next[0:0]$2554 end - attribute \src "libresoc.v:46098.3-46107.6" - process $proc$libresoc.v:46098$2556 + attribute \src "libresoc.v:46146.3-46155.6" + process $proc$libresoc.v:46146$2556 assign { } { } assign { } { } assign $0\fus_src2_i$68[63:0]$2557 $1\fus_src2_i$68[63:0]$2558 - attribute \src "libresoc.v:46099.5-46099.29" + attribute \src "libresoc.v:46147.5-46147.29" switch \initial - attribute \src "libresoc.v:46099.9-46099.17" + attribute \src "libresoc.v:46147.9-46147.17" case 1'1 case end @@ -79831,14 +79867,14 @@ module \core sync always update \fus_src2_i$68 $0\fus_src2_i$68[63:0]$2557 end - attribute \src "libresoc.v:46108.3-46116.6" - process $proc$libresoc.v:46108$2559 + attribute \src "libresoc.v:46156.3-46164.6" + process $proc$libresoc.v:46156$2559 assign { } { } assign { } { } assign $0\dp_INT_rb_shiftrot0_6$next[0:0]$2560 $1\dp_INT_rb_shiftrot0_6$next[0:0]$2561 - attribute \src "libresoc.v:46109.5-46109.29" + attribute \src "libresoc.v:46157.5-46157.29" switch \initial - attribute \src "libresoc.v:46109.9-46109.17" + attribute \src "libresoc.v:46157.9-46157.17" case 1'1 case end @@ -79854,14 +79890,14 @@ module \core sync always update \dp_INT_rb_shiftrot0_6$next $0\dp_INT_rb_shiftrot0_6$next[0:0]$2560 end - attribute \src "libresoc.v:46117.3-46126.6" - process $proc$libresoc.v:46117$2562 + attribute \src "libresoc.v:46165.3-46174.6" + process $proc$libresoc.v:46165$2562 assign { } { } assign { } { } assign $0\fus_src2_i$69[63:0]$2563 $1\fus_src2_i$69[63:0]$2564 - attribute \src "libresoc.v:46118.5-46118.29" + attribute \src "libresoc.v:46166.5-46166.29" switch \initial - attribute \src "libresoc.v:46118.9-46118.17" + attribute \src "libresoc.v:46166.9-46166.17" case 1'1 case end @@ -79877,14 +79913,14 @@ module \core sync always update \fus_src2_i$69 $0\fus_src2_i$69[63:0]$2563 end - attribute \src "libresoc.v:46127.3-46135.6" - process $proc$libresoc.v:46127$2565 + attribute \src "libresoc.v:46175.3-46183.6" + process $proc$libresoc.v:46175$2565 assign { } { } assign { } { } assign $0\dp_INT_rb_ldst0_7$next[0:0]$2566 $1\dp_INT_rb_ldst0_7$next[0:0]$2567 - attribute \src "libresoc.v:46128.5-46128.29" + attribute \src "libresoc.v:46176.5-46176.29" switch \initial - attribute \src "libresoc.v:46128.9-46128.17" + attribute \src "libresoc.v:46176.9-46176.17" case 1'1 case end @@ -79900,14 +79936,14 @@ module \core sync always update \dp_INT_rb_ldst0_7$next $0\dp_INT_rb_ldst0_7$next[0:0]$2566 end - attribute \src "libresoc.v:46136.3-46145.6" - process $proc$libresoc.v:46136$2568 + attribute \src "libresoc.v:46184.3-46193.6" + process $proc$libresoc.v:46184$2568 assign { } { } assign { } { } assign $0\fus_src2_i$70[63:0]$2569 $1\fus_src2_i$70[63:0]$2570 - attribute \src "libresoc.v:46137.5-46137.29" + attribute \src "libresoc.v:46185.5-46185.29" switch \initial - attribute \src "libresoc.v:46137.9-46137.17" + attribute \src "libresoc.v:46185.9-46185.17" case 1'1 case end @@ -79923,14 +79959,14 @@ module \core sync always update \fus_src2_i$70 $0\fus_src2_i$70[63:0]$2569 end - attribute \src "libresoc.v:46146.3-46154.6" - process $proc$libresoc.v:46146$2571 + attribute \src "libresoc.v:46194.3-46202.6" + process $proc$libresoc.v:46194$2571 assign { } { } assign { } { } assign $0\dp_INT_rc_shiftrot0_0$next[0:0]$2572 $1\dp_INT_rc_shiftrot0_0$next[0:0]$2573 - attribute \src "libresoc.v:46147.5-46147.29" + attribute \src "libresoc.v:46195.5-46195.29" switch \initial - attribute \src "libresoc.v:46147.9-46147.17" + attribute \src "libresoc.v:46195.9-46195.17" case 1'1 case end @@ -79946,14 +79982,14 @@ module \core sync always update \dp_INT_rc_shiftrot0_0$next $0\dp_INT_rc_shiftrot0_0$next[0:0]$2572 end - attribute \src "libresoc.v:46155.3-46164.6" - process $proc$libresoc.v:46155$2574 + attribute \src "libresoc.v:46203.3-46212.6" + process $proc$libresoc.v:46203$2574 assign { } { } assign { } { } assign $0\fus_src3_i[63:0] $1\fus_src3_i[63:0] - attribute \src "libresoc.v:46156.5-46156.29" + attribute \src "libresoc.v:46204.5-46204.29" switch \initial - attribute \src "libresoc.v:46156.9-46156.17" + attribute \src "libresoc.v:46204.9-46204.17" case 1'1 case end @@ -79969,14 +80005,14 @@ module \core sync always update \fus_src3_i $0\fus_src3_i[63:0] end - attribute \src "libresoc.v:46165.3-46173.6" - process $proc$libresoc.v:46165$2575 + attribute \src "libresoc.v:46213.3-46221.6" + process $proc$libresoc.v:46213$2575 assign { } { } assign { } { } assign $0\dp_INT_rc_ldst0_1$next[0:0]$2576 $1\dp_INT_rc_ldst0_1$next[0:0]$2577 - attribute \src "libresoc.v:46166.5-46166.29" + attribute \src "libresoc.v:46214.5-46214.29" switch \initial - attribute \src "libresoc.v:46166.9-46166.17" + attribute \src "libresoc.v:46214.9-46214.17" case 1'1 case end @@ -79992,14 +80028,14 @@ module \core sync always update \dp_INT_rc_ldst0_1$next $0\dp_INT_rc_ldst0_1$next[0:0]$2576 end - attribute \src "libresoc.v:46174.3-46183.6" - process $proc$libresoc.v:46174$2578 + attribute \src "libresoc.v:46222.3-46231.6" + process $proc$libresoc.v:46222$2578 assign { } { } assign { } { } assign $0\fus_src3_i$71[63:0]$2579 $1\fus_src3_i$71[63:0]$2580 - attribute \src "libresoc.v:46175.5-46175.29" + attribute \src "libresoc.v:46223.5-46223.29" switch \initial - attribute \src "libresoc.v:46175.9-46175.17" + attribute \src "libresoc.v:46223.9-46223.17" case 1'1 case end @@ -80015,14 +80051,14 @@ module \core sync always update \fus_src3_i$71 $0\fus_src3_i$71[63:0]$2579 end - attribute \src "libresoc.v:46184.3-46192.6" - process $proc$libresoc.v:46184$2581 + attribute \src "libresoc.v:46232.3-46240.6" + process $proc$libresoc.v:46232$2581 assign { } { } assign { } { } assign $0\dp_XER_xer_so_alu0_0$next[0:0]$2582 $1\dp_XER_xer_so_alu0_0$next[0:0]$2583 - attribute \src "libresoc.v:46185.5-46185.29" + attribute \src "libresoc.v:46233.5-46233.29" switch \initial - attribute \src "libresoc.v:46185.9-46185.17" + attribute \src "libresoc.v:46233.9-46233.17" case 1'1 case end @@ -80038,14 +80074,14 @@ module \core sync always update \dp_XER_xer_so_alu0_0$next $0\dp_XER_xer_so_alu0_0$next[0:0]$2582 end - attribute \src "libresoc.v:46193.3-46202.6" - process $proc$libresoc.v:46193$2584 + attribute \src "libresoc.v:46241.3-46250.6" + process $proc$libresoc.v:46241$2584 assign { } { } assign { } { } assign $0\fus_src3_i$72[0:0]$2585 $1\fus_src3_i$72[0:0]$2586 - attribute \src "libresoc.v:46194.5-46194.29" + attribute \src "libresoc.v:46242.5-46242.29" switch \initial - attribute \src "libresoc.v:46194.9-46194.17" + attribute \src "libresoc.v:46242.9-46242.17" case 1'1 case end @@ -80061,14 +80097,14 @@ module \core sync always update \fus_src3_i$72 $0\fus_src3_i$72[0:0]$2585 end - attribute \src "libresoc.v:46203.3-46211.6" - process $proc$libresoc.v:46203$2587 + attribute \src "libresoc.v:46251.3-46259.6" + process $proc$libresoc.v:46251$2587 assign { } { } assign { } { } assign $0\dp_XER_xer_so_logical0_1$next[0:0]$2588 $1\dp_XER_xer_so_logical0_1$next[0:0]$2589 - attribute \src "libresoc.v:46204.5-46204.29" + attribute \src "libresoc.v:46252.5-46252.29" switch \initial - attribute \src "libresoc.v:46204.9-46204.17" + attribute \src "libresoc.v:46252.9-46252.17" case 1'1 case end @@ -80084,14 +80120,14 @@ module \core sync always update \dp_XER_xer_so_logical0_1$next $0\dp_XER_xer_so_logical0_1$next[0:0]$2588 end - attribute \src "libresoc.v:46212.3-46221.6" - process $proc$libresoc.v:46212$2590 + attribute \src "libresoc.v:46260.3-46269.6" + process $proc$libresoc.v:46260$2590 assign { } { } assign { } { } assign $0\fus_src3_i$73[0:0]$2591 $1\fus_src3_i$73[0:0]$2592 - attribute \src "libresoc.v:46213.5-46213.29" + attribute \src "libresoc.v:46261.5-46261.29" switch \initial - attribute \src "libresoc.v:46213.9-46213.17" + attribute \src "libresoc.v:46261.9-46261.17" case 1'1 case end @@ -80107,14 +80143,14 @@ module \core sync always update \fus_src3_i$73 $0\fus_src3_i$73[0:0]$2591 end - attribute \src "libresoc.v:46222.3-46230.6" - process $proc$libresoc.v:46222$2593 + attribute \src "libresoc.v:46270.3-46278.6" + process $proc$libresoc.v:46270$2593 assign { } { } assign { } { } assign $0\dp_XER_xer_so_spr0_2$next[0:0]$2594 $1\dp_XER_xer_so_spr0_2$next[0:0]$2595 - attribute \src "libresoc.v:46223.5-46223.29" + attribute \src "libresoc.v:46271.5-46271.29" switch \initial - attribute \src "libresoc.v:46223.9-46223.17" + attribute \src "libresoc.v:46271.9-46271.17" case 1'1 case end @@ -80130,14 +80166,14 @@ module \core sync always update \dp_XER_xer_so_spr0_2$next $0\dp_XER_xer_so_spr0_2$next[0:0]$2594 end - attribute \src "libresoc.v:46231.3-46240.6" - process $proc$libresoc.v:46231$2596 + attribute \src "libresoc.v:46279.3-46288.6" + process $proc$libresoc.v:46279$2596 assign { } { } assign { } { } assign $0\fus_src4_i[0:0] $1\fus_src4_i[0:0] - attribute \src "libresoc.v:46232.5-46232.29" + attribute \src "libresoc.v:46280.5-46280.29" switch \initial - attribute \src "libresoc.v:46232.9-46232.17" + attribute \src "libresoc.v:46280.9-46280.17" case 1'1 case end @@ -80153,14 +80189,14 @@ module \core sync always update \fus_src4_i $0\fus_src4_i[0:0] end - attribute \src "libresoc.v:46241.3-46249.6" - process $proc$libresoc.v:46241$2597 + attribute \src "libresoc.v:46289.3-46297.6" + process $proc$libresoc.v:46289$2597 assign { } { } assign { } { } assign $0\dp_XER_xer_so_div0_3$next[0:0]$2598 $1\dp_XER_xer_so_div0_3$next[0:0]$2599 - attribute \src "libresoc.v:46242.5-46242.29" + attribute \src "libresoc.v:46290.5-46290.29" switch \initial - attribute \src "libresoc.v:46242.9-46242.17" + attribute \src "libresoc.v:46290.9-46290.17" case 1'1 case end @@ -80176,14 +80212,14 @@ module \core sync always update \dp_XER_xer_so_div0_3$next $0\dp_XER_xer_so_div0_3$next[0:0]$2598 end - attribute \src "libresoc.v:46250.3-46259.6" - process $proc$libresoc.v:46250$2600 + attribute \src "libresoc.v:46298.3-46307.6" + process $proc$libresoc.v:46298$2600 assign { } { } assign { } { } assign $0\fus_src3_i$74[0:0]$2601 $1\fus_src3_i$74[0:0]$2602 - attribute \src "libresoc.v:46251.5-46251.29" + attribute \src "libresoc.v:46299.5-46299.29" switch \initial - attribute \src "libresoc.v:46251.9-46251.17" + attribute \src "libresoc.v:46299.9-46299.17" case 1'1 case end @@ -80199,14 +80235,14 @@ module \core sync always update \fus_src3_i$74 $0\fus_src3_i$74[0:0]$2601 end - attribute \src "libresoc.v:46260.3-46268.6" - process $proc$libresoc.v:46260$2603 + attribute \src "libresoc.v:46308.3-46316.6" + process $proc$libresoc.v:46308$2603 assign { } { } assign { } { } assign $0\dp_XER_xer_so_mul0_4$next[0:0]$2604 $1\dp_XER_xer_so_mul0_4$next[0:0]$2605 - attribute \src "libresoc.v:46261.5-46261.29" + attribute \src "libresoc.v:46309.5-46309.29" switch \initial - attribute \src "libresoc.v:46261.9-46261.17" + attribute \src "libresoc.v:46309.9-46309.17" case 1'1 case end @@ -80222,14 +80258,14 @@ module \core sync always update \dp_XER_xer_so_mul0_4$next $0\dp_XER_xer_so_mul0_4$next[0:0]$2604 end - attribute \src "libresoc.v:46269.3-46278.6" - process $proc$libresoc.v:46269$2606 + attribute \src "libresoc.v:46317.3-46326.6" + process $proc$libresoc.v:46317$2606 assign { } { } assign { } { } assign $0\fus_src3_i$75[0:0]$2607 $1\fus_src3_i$75[0:0]$2608 - attribute \src "libresoc.v:46270.5-46270.29" + attribute \src "libresoc.v:46318.5-46318.29" switch \initial - attribute \src "libresoc.v:46270.9-46270.17" + attribute \src "libresoc.v:46318.9-46318.17" case 1'1 case end @@ -80245,14 +80281,14 @@ module \core sync always update \fus_src3_i$75 $0\fus_src3_i$75[0:0]$2607 end - attribute \src "libresoc.v:46279.3-46287.6" - process $proc$libresoc.v:46279$2609 + attribute \src "libresoc.v:46327.3-46335.6" + process $proc$libresoc.v:46327$2609 assign { } { } assign { } { } assign $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2610 $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2611 - attribute \src "libresoc.v:46280.5-46280.29" + attribute \src "libresoc.v:46328.5-46328.29" switch \initial - attribute \src "libresoc.v:46280.9-46280.17" + attribute \src "libresoc.v:46328.9-46328.17" case 1'1 case end @@ -80268,14 +80304,14 @@ module \core sync always update \dp_XER_xer_so_shiftrot0_5$next $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2610 end - attribute \src "libresoc.v:46288.3-46297.6" - process $proc$libresoc.v:46288$2612 + attribute \src "libresoc.v:46336.3-46345.6" + process $proc$libresoc.v:46336$2612 assign { } { } assign { } { } assign $0\fus_src4_i$76[0:0]$2613 $1\fus_src4_i$76[0:0]$2614 - attribute \src "libresoc.v:46289.5-46289.29" + attribute \src "libresoc.v:46337.5-46337.29" switch \initial - attribute \src "libresoc.v:46289.9-46289.17" + attribute \src "libresoc.v:46337.9-46337.17" case 1'1 case end @@ -80291,14 +80327,14 @@ module \core sync always update \fus_src4_i$76 $0\fus_src4_i$76[0:0]$2613 end - attribute \src "libresoc.v:46298.3-46306.6" - process $proc$libresoc.v:46298$2615 + attribute \src "libresoc.v:46346.3-46354.6" + process $proc$libresoc.v:46346$2615 assign { } { } assign { } { } assign $0\dp_XER_xer_ca_alu0_0$next[0:0]$2616 $1\dp_XER_xer_ca_alu0_0$next[0:0]$2617 - attribute \src "libresoc.v:46299.5-46299.29" + attribute \src "libresoc.v:46347.5-46347.29" switch \initial - attribute \src "libresoc.v:46299.9-46299.17" + attribute \src "libresoc.v:46347.9-46347.17" case 1'1 case end @@ -80314,14 +80350,14 @@ module \core sync always update \dp_XER_xer_ca_alu0_0$next $0\dp_XER_xer_ca_alu0_0$next[0:0]$2616 end - attribute \src "libresoc.v:46307.3-46316.6" - process $proc$libresoc.v:46307$2618 + attribute \src "libresoc.v:46355.3-46364.6" + process $proc$libresoc.v:46355$2618 assign { } { } assign { } { } assign $0\fus_src4_i$77[1:0]$2619 $1\fus_src4_i$77[1:0]$2620 - attribute \src "libresoc.v:46308.5-46308.29" + attribute \src "libresoc.v:46356.5-46356.29" switch \initial - attribute \src "libresoc.v:46308.9-46308.17" + attribute \src "libresoc.v:46356.9-46356.17" case 1'1 case end @@ -80337,14 +80373,14 @@ module \core sync always update \fus_src4_i$77 $0\fus_src4_i$77[1:0]$2619 end - attribute \src "libresoc.v:46317.3-46325.6" - process $proc$libresoc.v:46317$2621 + attribute \src "libresoc.v:46365.3-46373.6" + process $proc$libresoc.v:46365$2621 assign { } { } assign { } { } assign $0\dp_XER_xer_ca_spr0_1$next[0:0]$2622 $1\dp_XER_xer_ca_spr0_1$next[0:0]$2623 - attribute \src "libresoc.v:46318.5-46318.29" + attribute \src "libresoc.v:46366.5-46366.29" switch \initial - attribute \src "libresoc.v:46318.9-46318.17" + attribute \src "libresoc.v:46366.9-46366.17" case 1'1 case end @@ -80360,14 +80396,14 @@ module \core sync always update \dp_XER_xer_ca_spr0_1$next $0\dp_XER_xer_ca_spr0_1$next[0:0]$2622 end - attribute \src "libresoc.v:46326.3-46335.6" - process $proc$libresoc.v:46326$2624 + attribute \src "libresoc.v:46374.3-46383.6" + process $proc$libresoc.v:46374$2624 assign { } { } assign { } { } assign $0\fus_src6_i[1:0] $1\fus_src6_i[1:0] - attribute \src "libresoc.v:46327.5-46327.29" + attribute \src "libresoc.v:46375.5-46375.29" switch \initial - attribute \src "libresoc.v:46327.9-46327.17" + attribute \src "libresoc.v:46375.9-46375.17" case 1'1 case end @@ -80383,14 +80419,14 @@ module \core sync always update \fus_src6_i $0\fus_src6_i[1:0] end - attribute \src "libresoc.v:46336.3-46344.6" - process $proc$libresoc.v:46336$2625 + attribute \src "libresoc.v:46384.3-46392.6" + process $proc$libresoc.v:46384$2625 assign { } { } assign { } { } assign $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2626 $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2627 - attribute \src "libresoc.v:46337.5-46337.29" + attribute \src "libresoc.v:46385.5-46385.29" switch \initial - attribute \src "libresoc.v:46337.9-46337.17" + attribute \src "libresoc.v:46385.9-46385.17" case 1'1 case end @@ -80406,14 +80442,14 @@ module \core sync always update \dp_XER_xer_ca_shiftrot0_2$next $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2626 end - attribute \src "libresoc.v:46345.3-46354.6" - process $proc$libresoc.v:46345$2628 + attribute \src "libresoc.v:46393.3-46402.6" + process $proc$libresoc.v:46393$2628 assign { } { } assign { } { } assign $0\fus_src5_i[1:0] $1\fus_src5_i[1:0] - attribute \src "libresoc.v:46346.5-46346.29" + attribute \src "libresoc.v:46394.5-46394.29" switch \initial - attribute \src "libresoc.v:46346.9-46346.17" + attribute \src "libresoc.v:46394.9-46394.17" case 1'1 case end @@ -80429,14 +80465,14 @@ module \core sync always update \fus_src5_i $0\fus_src5_i[1:0] end - attribute \src "libresoc.v:46355.3-46363.6" - process $proc$libresoc.v:46355$2629 + attribute \src "libresoc.v:46403.3-46411.6" + process $proc$libresoc.v:46403$2629 assign { } { } assign { } { } assign $0\dp_XER_xer_ov_spr0_0$next[0:0]$2630 $1\dp_XER_xer_ov_spr0_0$next[0:0]$2631 - attribute \src "libresoc.v:46356.5-46356.29" + attribute \src "libresoc.v:46404.5-46404.29" switch \initial - attribute \src "libresoc.v:46356.9-46356.17" + attribute \src "libresoc.v:46404.9-46404.17" case 1'1 case end @@ -80452,14 +80488,14 @@ module \core sync always update \dp_XER_xer_ov_spr0_0$next $0\dp_XER_xer_ov_spr0_0$next[0:0]$2630 end - attribute \src "libresoc.v:46364.3-46373.6" - process $proc$libresoc.v:46364$2632 + attribute \src "libresoc.v:46412.3-46421.6" + process $proc$libresoc.v:46412$2632 assign { } { } assign { } { } assign $0\fus_src5_i$78[1:0]$2633 $1\fus_src5_i$78[1:0]$2634 - attribute \src "libresoc.v:46365.5-46365.29" + attribute \src "libresoc.v:46413.5-46413.29" switch \initial - attribute \src "libresoc.v:46365.9-46365.17" + attribute \src "libresoc.v:46413.9-46413.17" case 1'1 case end @@ -80475,14 +80511,14 @@ module \core sync always update \fus_src5_i$78 $0\fus_src5_i$78[1:0]$2633 end - attribute \src "libresoc.v:46374.3-46382.6" - process $proc$libresoc.v:46374$2635 + attribute \src "libresoc.v:46422.3-46430.6" + process $proc$libresoc.v:46422$2635 assign { } { } assign { } { } assign $0\dp_CR_full_cr_cr0_0$next[0:0]$2636 $1\dp_CR_full_cr_cr0_0$next[0:0]$2637 - attribute \src "libresoc.v:46375.5-46375.29" + attribute \src "libresoc.v:46423.5-46423.29" switch \initial - attribute \src "libresoc.v:46375.9-46375.17" + attribute \src "libresoc.v:46423.9-46423.17" case 1'1 case end @@ -80498,14 +80534,14 @@ module \core sync always update \dp_CR_full_cr_cr0_0$next $0\dp_CR_full_cr_cr0_0$next[0:0]$2636 end - attribute \src "libresoc.v:46383.3-46392.6" - process $proc$libresoc.v:46383$2638 + attribute \src "libresoc.v:46431.3-46440.6" + process $proc$libresoc.v:46431$2638 assign { } { } assign { } { } assign $0\fus_src3_i$79[31:0]$2639 $1\fus_src3_i$79[31:0]$2640 - attribute \src "libresoc.v:46384.5-46384.29" + attribute \src "libresoc.v:46432.5-46432.29" switch \initial - attribute \src "libresoc.v:46384.9-46384.17" + attribute \src "libresoc.v:46432.9-46432.17" case 1'1 case end @@ -80521,14 +80557,14 @@ module \core sync always update \fus_src3_i$79 $0\fus_src3_i$79[31:0]$2639 end - attribute \src "libresoc.v:46393.3-46401.6" - process $proc$libresoc.v:46393$2641 + attribute \src "libresoc.v:46441.3-46449.6" + process $proc$libresoc.v:46441$2641 assign { } { } assign { } { } assign $0\dp_CR_cr_a_cr0_0$next[0:0]$2642 $1\dp_CR_cr_a_cr0_0$next[0:0]$2643 - attribute \src "libresoc.v:46394.5-46394.29" + attribute \src "libresoc.v:46442.5-46442.29" switch \initial - attribute \src "libresoc.v:46394.9-46394.17" + attribute \src "libresoc.v:46442.9-46442.17" case 1'1 case end @@ -80544,14 +80580,14 @@ module \core sync always update \dp_CR_cr_a_cr0_0$next $0\dp_CR_cr_a_cr0_0$next[0:0]$2642 end - attribute \src "libresoc.v:46402.3-46411.6" - process $proc$libresoc.v:46402$2644 + attribute \src "libresoc.v:46450.3-46459.6" + process $proc$libresoc.v:46450$2644 assign { } { } assign { } { } assign $0\fus_src4_i$80[3:0]$2645 $1\fus_src4_i$80[3:0]$2646 - attribute \src "libresoc.v:46403.5-46403.29" + attribute \src "libresoc.v:46451.5-46451.29" switch \initial - attribute \src "libresoc.v:46403.9-46403.17" + attribute \src "libresoc.v:46451.9-46451.17" case 1'1 case end @@ -80567,14 +80603,14 @@ module \core sync always update \fus_src4_i$80 $0\fus_src4_i$80[3:0]$2645 end - attribute \src "libresoc.v:46412.3-46420.6" - process $proc$libresoc.v:46412$2647 + attribute \src "libresoc.v:46460.3-46468.6" + process $proc$libresoc.v:46460$2647 assign { } { } assign { } { } assign $0\dp_CR_cr_a_branch0_1$next[0:0]$2648 $1\dp_CR_cr_a_branch0_1$next[0:0]$2649 - attribute \src "libresoc.v:46413.5-46413.29" + attribute \src "libresoc.v:46461.5-46461.29" switch \initial - attribute \src "libresoc.v:46413.9-46413.17" + attribute \src "libresoc.v:46461.9-46461.17" case 1'1 case end @@ -80590,14 +80626,14 @@ module \core sync always update \dp_CR_cr_a_branch0_1$next $0\dp_CR_cr_a_branch0_1$next[0:0]$2648 end - attribute \src "libresoc.v:46421.3-46430.6" - process $proc$libresoc.v:46421$2650 + attribute \src "libresoc.v:46469.3-46478.6" + process $proc$libresoc.v:46469$2650 assign { } { } assign { } { } assign $0\fus_src3_i$83[3:0]$2651 $1\fus_src3_i$83[3:0]$2652 - attribute \src "libresoc.v:46422.5-46422.29" + attribute \src "libresoc.v:46470.5-46470.29" switch \initial - attribute \src "libresoc.v:46422.9-46422.17" + attribute \src "libresoc.v:46470.9-46470.17" case 1'1 case end @@ -80613,16 +80649,16 @@ module \core sync always update \fus_src3_i$83 $0\fus_src3_i$83[3:0]$2651 end - attribute \src "libresoc.v:46431.3-46457.6" - process $proc$libresoc.v:46431$2653 + attribute \src "libresoc.v:46479.3-46509.6" + process $proc$libresoc.v:46479$2653 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\counter$next[1:0]$2654 $4\counter$next[1:0]$2658 - attribute \src "libresoc.v:46432.5-46432.29" + attribute \src "libresoc.v:46480.5-46480.29" switch \initial - attribute \src "libresoc.v:46432.9-46432.17" + attribute \src "libresoc.v:46480.9-46480.17" case 1'1 case end @@ -80644,6 +80680,9 @@ module \core attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:194" switch \core_core_insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0000101 + assign $3\counter$next[1:0]$2657 $1\counter$next[1:0]$2655 + attribute \src "libresoc.v:0.0-0.0" case 7'0000001 assign { } { } assign $3\counter$next[1:0]$2657 2'10 @@ -80665,14 +80704,14 @@ module \core sync always update \counter$next $0\counter$next[1:0]$2654 end - attribute \src "libresoc.v:46458.3-46466.6" - process $proc$libresoc.v:46458$2659 + attribute \src "libresoc.v:46510.3-46518.6" + process $proc$libresoc.v:46510$2659 assign { } { } assign { } { } assign $0\dp_CR_cr_b_cr0_0$next[0:0]$2660 $1\dp_CR_cr_b_cr0_0$next[0:0]$2661 - attribute \src "libresoc.v:46459.5-46459.29" + attribute \src "libresoc.v:46511.5-46511.29" switch \initial - attribute \src "libresoc.v:46459.9-46459.17" + attribute \src "libresoc.v:46511.9-46511.17" case 1'1 case end @@ -80688,14 +80727,14 @@ module \core sync always update \dp_CR_cr_b_cr0_0$next $0\dp_CR_cr_b_cr0_0$next[0:0]$2660 end - attribute \src "libresoc.v:46467.3-46476.6" - process $proc$libresoc.v:46467$2662 + attribute \src "libresoc.v:46519.3-46528.6" + process $proc$libresoc.v:46519$2662 assign { } { } assign { } { } assign $0\fus_src5_i$84[3:0]$2663 $1\fus_src5_i$84[3:0]$2664 - attribute \src "libresoc.v:46468.5-46468.29" + attribute \src "libresoc.v:46520.5-46520.29" switch \initial - attribute \src "libresoc.v:46468.9-46468.17" + attribute \src "libresoc.v:46520.9-46520.17" case 1'1 case end @@ -80711,15 +80750,15 @@ module \core sync always update \fus_src5_i$84 $0\fus_src5_i$84[3:0]$2663 end - attribute \src "libresoc.v:46477.3-46567.6" - process $proc$libresoc.v:46477$2665 + attribute \src "libresoc.v:46529.3-46619.6" + process $proc$libresoc.v:46529$2665 assign { } { } assign { } { } assign { } { } assign $0\corebusy_o[0:0] $2\corebusy_o[0:0] - attribute \src "libresoc.v:46478.5-46478.29" + attribute \src "libresoc.v:46530.5-46530.29" switch \initial - attribute \src "libresoc.v:46478.9-46478.17" + attribute \src "libresoc.v:46530.9-46530.17" case 1'1 case end @@ -80857,14 +80896,14 @@ module \core sync always update \corebusy_o $0\corebusy_o[0:0] end - attribute \src "libresoc.v:46568.3-46576.6" - process $proc$libresoc.v:46568$2666 + attribute \src "libresoc.v:46620.3-46628.6" + process $proc$libresoc.v:46620$2666 assign { } { } assign { } { } assign $0\dp_CR_cr_c_cr0_0$next[0:0]$2667 $1\dp_CR_cr_c_cr0_0$next[0:0]$2668 - attribute \src "libresoc.v:46569.5-46569.29" + attribute \src "libresoc.v:46621.5-46621.29" switch \initial - attribute \src "libresoc.v:46569.9-46569.17" + attribute \src "libresoc.v:46621.9-46621.17" case 1'1 case end @@ -80880,14 +80919,14 @@ module \core sync always update \dp_CR_cr_c_cr0_0$next $0\dp_CR_cr_c_cr0_0$next[0:0]$2667 end - attribute \src "libresoc.v:46577.3-46586.6" - process $proc$libresoc.v:46577$2669 + attribute \src "libresoc.v:46629.3-46638.6" + process $proc$libresoc.v:46629$2669 assign { } { } assign { } { } assign $0\fus_src6_i$85[3:0]$2670 $1\fus_src6_i$85[3:0]$2671 - attribute \src "libresoc.v:46578.5-46578.29" + attribute \src "libresoc.v:46630.5-46630.29" switch \initial - attribute \src "libresoc.v:46578.9-46578.17" + attribute \src "libresoc.v:46630.9-46630.17" case 1'1 case end @@ -80903,15 +80942,15 @@ module \core sync always update \fus_src6_i$85 $0\fus_src6_i$85[3:0]$2670 end - attribute \src "libresoc.v:46587.3-46607.6" - process $proc$libresoc.v:46587$2672 + attribute \src "libresoc.v:46639.3-46659.6" + process $proc$libresoc.v:46639$2672 assign { } { } assign { } { } assign { } { } assign $0\core_terminate_o$next[0:0]$2673 $3\core_terminate_o$next[0:0]$2676 - attribute \src "libresoc.v:46588.5-46588.29" + attribute \src "libresoc.v:46640.5-46640.29" switch \initial - attribute \src "libresoc.v:46588.9-46588.17" + attribute \src "libresoc.v:46640.9-46640.17" case 1'1 case end @@ -80945,14 +80984,14 @@ module \core sync always update \core_terminate_o$next $0\core_terminate_o$next[0:0]$2673 end - attribute \src "libresoc.v:46608.3-46616.6" - process $proc$libresoc.v:46608$2677 + attribute \src "libresoc.v:46660.3-46668.6" + process $proc$libresoc.v:46660$2677 assign { } { } assign { } { } assign $0\dp_FAST_fast1_branch0_0$next[0:0]$2678 $1\dp_FAST_fast1_branch0_0$next[0:0]$2679 - attribute \src "libresoc.v:46609.5-46609.29" + attribute \src "libresoc.v:46661.5-46661.29" switch \initial - attribute \src "libresoc.v:46609.9-46609.17" + attribute \src "libresoc.v:46661.9-46661.17" case 1'1 case end @@ -80968,14 +81007,14 @@ module \core sync always update \dp_FAST_fast1_branch0_0$next $0\dp_FAST_fast1_branch0_0$next[0:0]$2678 end - attribute \src "libresoc.v:46617.3-46626.6" - process $proc$libresoc.v:46617$2680 + attribute \src "libresoc.v:46669.3-46678.6" + process $proc$libresoc.v:46669$2680 assign { } { } assign { } { } assign $0\fus_src1_i$86[63:0]$2681 $1\fus_src1_i$86[63:0]$2682 - attribute \src "libresoc.v:46618.5-46618.29" + attribute \src "libresoc.v:46670.5-46670.29" switch \initial - attribute \src "libresoc.v:46618.9-46618.17" + attribute \src "libresoc.v:46670.9-46670.17" case 1'1 case end @@ -80991,14 +81030,14 @@ module \core sync always update \fus_src1_i$86 $0\fus_src1_i$86[63:0]$2681 end - attribute \src "libresoc.v:46627.3-46635.6" - process $proc$libresoc.v:46627$2683 + attribute \src "libresoc.v:46679.3-46687.6" + process $proc$libresoc.v:46679$2683 assign { } { } assign { } { } assign $0\dp_FAST_fast1_trap0_1$next[0:0]$2684 $1\dp_FAST_fast1_trap0_1$next[0:0]$2685 - attribute \src "libresoc.v:46628.5-46628.29" + attribute \src "libresoc.v:46680.5-46680.29" switch \initial - attribute \src "libresoc.v:46628.9-46628.17" + attribute \src "libresoc.v:46680.9-46680.17" case 1'1 case end @@ -81014,14 +81053,14 @@ module \core sync always update \dp_FAST_fast1_trap0_1$next $0\dp_FAST_fast1_trap0_1$next[0:0]$2684 end - attribute \src "libresoc.v:46636.3-46645.6" - process $proc$libresoc.v:46636$2686 + attribute \src "libresoc.v:46688.3-46697.6" + process $proc$libresoc.v:46688$2686 assign { } { } assign { } { } assign $0\fus_src3_i$87[63:0]$2687 $1\fus_src3_i$87[63:0]$2688 - attribute \src "libresoc.v:46637.5-46637.29" + attribute \src "libresoc.v:46689.5-46689.29" switch \initial - attribute \src "libresoc.v:46637.9-46637.17" + attribute \src "libresoc.v:46689.9-46689.17" case 1'1 case end @@ -81037,14 +81076,14 @@ module \core sync always update \fus_src3_i$87 $0\fus_src3_i$87[63:0]$2687 end - attribute \src "libresoc.v:46646.3-46674.6" - process $proc$libresoc.v:46646$2689 + attribute \src "libresoc.v:46698.3-46726.6" + process $proc$libresoc.v:46698$2689 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__insn_type[6:0] $1\fus_oper_i_alu_alu0__insn_type[6:0] - attribute \src "libresoc.v:46647.5-46647.29" + attribute \src "libresoc.v:46699.5-46699.29" switch \initial - attribute \src "libresoc.v:46647.9-46647.17" + attribute \src "libresoc.v:46699.9-46699.17" case 1'1 case end @@ -81082,14 +81121,14 @@ module \core sync always update \fus_oper_i_alu_alu0__insn_type $0\fus_oper_i_alu_alu0__insn_type[6:0] end - attribute \src "libresoc.v:46675.3-46683.6" - process $proc$libresoc.v:46675$2690 + attribute \src "libresoc.v:46727.3-46735.6" + process $proc$libresoc.v:46727$2690 assign { } { } assign { } { } assign $0\dp_FAST_fast1_spr0_2$next[0:0]$2691 $1\dp_FAST_fast1_spr0_2$next[0:0]$2692 - attribute \src "libresoc.v:46676.5-46676.29" + attribute \src "libresoc.v:46728.5-46728.29" switch \initial - attribute \src "libresoc.v:46676.9-46676.17" + attribute \src "libresoc.v:46728.9-46728.17" case 1'1 case end @@ -81105,14 +81144,14 @@ module \core sync always update \dp_FAST_fast1_spr0_2$next $0\dp_FAST_fast1_spr0_2$next[0:0]$2691 end - attribute \src "libresoc.v:46684.3-46693.6" - process $proc$libresoc.v:46684$2693 + attribute \src "libresoc.v:46736.3-46745.6" + process $proc$libresoc.v:46736$2693 assign { } { } assign { } { } assign $0\fus_src3_i$88[63:0]$2694 $1\fus_src3_i$88[63:0]$2695 - attribute \src "libresoc.v:46685.5-46685.29" + attribute \src "libresoc.v:46737.5-46737.29" switch \initial - attribute \src "libresoc.v:46685.9-46685.17" + attribute \src "libresoc.v:46737.9-46737.17" case 1'1 case end @@ -81128,14 +81167,14 @@ module \core sync always update \fus_src3_i$88 $0\fus_src3_i$88[63:0]$2694 end - attribute \src "libresoc.v:46694.3-46722.6" - process $proc$libresoc.v:46694$2696 + attribute \src "libresoc.v:46746.3-46774.6" + process $proc$libresoc.v:46746$2696 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__fn_unit[13:0] $1\fus_oper_i_alu_alu0__fn_unit[13:0] - attribute \src "libresoc.v:46695.5-46695.29" + attribute \src "libresoc.v:46747.5-46747.29" switch \initial - attribute \src "libresoc.v:46695.9-46695.17" + attribute \src "libresoc.v:46747.9-46747.17" case 1'1 case end @@ -81173,14 +81212,14 @@ module \core sync always update \fus_oper_i_alu_alu0__fn_unit $0\fus_oper_i_alu_alu0__fn_unit[13:0] end - attribute \src "libresoc.v:46723.3-46731.6" - process $proc$libresoc.v:46723$2697 + attribute \src "libresoc.v:46775.3-46783.6" + process $proc$libresoc.v:46775$2697 assign { } { } assign { } { } assign $0\dp_FAST_fast2_branch0_0$next[0:0]$2698 $1\dp_FAST_fast2_branch0_0$next[0:0]$2699 - attribute \src "libresoc.v:46724.5-46724.29" + attribute \src "libresoc.v:46776.5-46776.29" switch \initial - attribute \src "libresoc.v:46724.9-46724.17" + attribute \src "libresoc.v:46776.9-46776.17" case 1'1 case end @@ -81196,14 +81235,14 @@ module \core sync always update \dp_FAST_fast2_branch0_0$next $0\dp_FAST_fast2_branch0_0$next[0:0]$2698 end - attribute \src "libresoc.v:46732.3-46741.6" - process $proc$libresoc.v:46732$2700 + attribute \src "libresoc.v:46784.3-46793.6" + process $proc$libresoc.v:46784$2700 assign { } { } assign { } { } assign $0\fus_src2_i$89[63:0]$2701 $1\fus_src2_i$89[63:0]$2702 - attribute \src "libresoc.v:46733.5-46733.29" + attribute \src "libresoc.v:46785.5-46785.29" switch \initial - attribute \src "libresoc.v:46733.9-46733.17" + attribute \src "libresoc.v:46785.9-46785.17" case 1'1 case end @@ -81219,14 +81258,14 @@ module \core sync always update \fus_src2_i$89 $0\fus_src2_i$89[63:0]$2701 end - attribute \src "libresoc.v:46742.3-46750.6" - process $proc$libresoc.v:46742$2703 + attribute \src "libresoc.v:46794.3-46802.6" + process $proc$libresoc.v:46794$2703 assign { } { } assign { } { } assign $0\dp_FAST_fast2_trap0_1$next[0:0]$2704 $1\dp_FAST_fast2_trap0_1$next[0:0]$2705 - attribute \src "libresoc.v:46743.5-46743.29" + attribute \src "libresoc.v:46795.5-46795.29" switch \initial - attribute \src "libresoc.v:46743.9-46743.17" + attribute \src "libresoc.v:46795.9-46795.17" case 1'1 case end @@ -81242,14 +81281,14 @@ module \core sync always update \dp_FAST_fast2_trap0_1$next $0\dp_FAST_fast2_trap0_1$next[0:0]$2704 end - attribute \src "libresoc.v:46751.3-46760.6" - process $proc$libresoc.v:46751$2706 + attribute \src "libresoc.v:46803.3-46812.6" + process $proc$libresoc.v:46803$2706 assign { } { } assign { } { } assign $0\fus_src4_i$90[63:0]$2707 $1\fus_src4_i$90[63:0]$2708 - attribute \src "libresoc.v:46752.5-46752.29" + attribute \src "libresoc.v:46804.5-46804.29" switch \initial - attribute \src "libresoc.v:46752.9-46752.17" + attribute \src "libresoc.v:46804.9-46804.17" case 1'1 case end @@ -81265,17 +81304,17 @@ module \core sync always update \fus_src4_i$90 $0\fus_src4_i$90[63:0]$2707 end - attribute \src "libresoc.v:46761.3-46790.6" - process $proc$libresoc.v:46761$2709 + attribute \src "libresoc.v:46813.3-46842.6" + process $proc$libresoc.v:46813$2709 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__imm_data__data[63:0] $1\fus_oper_i_alu_alu0__imm_data__data[63:0] assign $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] - attribute \src "libresoc.v:46762.5-46762.29" + attribute \src "libresoc.v:46814.5-46814.29" switch \initial - attribute \src "libresoc.v:46762.9-46762.17" + attribute \src "libresoc.v:46814.9-46814.17" case 1'1 case end @@ -81323,14 +81362,14 @@ module \core update \fus_oper_i_alu_alu0__imm_data__data $0\fus_oper_i_alu_alu0__imm_data__data[63:0] update \fus_oper_i_alu_alu0__imm_data__ok $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] end - attribute \src "libresoc.v:46791.3-46799.6" - process $proc$libresoc.v:46791$2710 + attribute \src "libresoc.v:46843.3-46851.6" + process $proc$libresoc.v:46843$2710 assign { } { } assign { } { } assign $0\dp_SPR_spr1_spr0_0$next[0:0]$2711 $1\dp_SPR_spr1_spr0_0$next[0:0]$2712 - attribute \src "libresoc.v:46792.5-46792.29" + attribute \src "libresoc.v:46844.5-46844.29" switch \initial - attribute \src "libresoc.v:46792.9-46792.17" + attribute \src "libresoc.v:46844.9-46844.17" case 1'1 case end @@ -81346,14 +81385,14 @@ module \core sync always update \dp_SPR_spr1_spr0_0$next $0\dp_SPR_spr1_spr0_0$next[0:0]$2711 end - attribute \src "libresoc.v:46800.3-46809.6" - process $proc$libresoc.v:46800$2713 + attribute \src "libresoc.v:46852.3-46861.6" + process $proc$libresoc.v:46852$2713 assign { } { } assign { } { } assign $0\fus_src2_i$91[63:0]$2714 $1\fus_src2_i$91[63:0]$2715 - attribute \src "libresoc.v:46801.5-46801.29" + attribute \src "libresoc.v:46853.5-46853.29" switch \initial - attribute \src "libresoc.v:46801.9-46801.17" + attribute \src "libresoc.v:46853.9-46853.17" case 1'1 case end @@ -81369,14 +81408,14 @@ module \core sync always update \fus_src2_i$91 $0\fus_src2_i$91[63:0]$2714 end - attribute \src "libresoc.v:46810.3-46818.6" - process $proc$libresoc.v:46810$2716 + attribute \src "libresoc.v:46862.3-46870.6" + process $proc$libresoc.v:46862$2716 assign { } { } assign { } { } assign $0\wr_pick_dly$next[0:0]$2717 $1\wr_pick_dly$next[0:0]$2718 - attribute \src "libresoc.v:46811.5-46811.29" + attribute \src "libresoc.v:46863.5-46863.29" switch \initial - attribute \src "libresoc.v:46811.9-46811.17" + attribute \src "libresoc.v:46863.9-46863.17" case 1'1 case end @@ -81392,14 +81431,14 @@ module \core sync always update \wr_pick_dly$next $0\wr_pick_dly$next[0:0]$2717 end - attribute \src "libresoc.v:46819.3-46827.6" - process $proc$libresoc.v:46819$2719 + attribute \src "libresoc.v:46871.3-46879.6" + process $proc$libresoc.v:46871$2719 assign { } { } assign { } { } assign $0\wr_pick_dly$991$next[0:0]$2720 $1\wr_pick_dly$991$next[0:0]$2721 - attribute \src "libresoc.v:46820.5-46820.29" + attribute \src "libresoc.v:46872.5-46872.29" switch \initial - attribute \src "libresoc.v:46820.9-46820.17" + attribute \src "libresoc.v:46872.9-46872.17" case 1'1 case end @@ -81415,17 +81454,17 @@ module \core sync always update \wr_pick_dly$991$next $0\wr_pick_dly$991$next[0:0]$2720 end - attribute \src "libresoc.v:46828.3-46857.6" - process $proc$libresoc.v:46828$2722 + attribute \src "libresoc.v:46880.3-46909.6" + process $proc$libresoc.v:46880$2722 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__rc__ok[0:0] $1\fus_oper_i_alu_alu0__rc__ok[0:0] assign $0\fus_oper_i_alu_alu0__rc__rc[0:0] $1\fus_oper_i_alu_alu0__rc__rc[0:0] - attribute \src "libresoc.v:46829.5-46829.29" + attribute \src "libresoc.v:46881.5-46881.29" switch \initial - attribute \src "libresoc.v:46829.9-46829.17" + attribute \src "libresoc.v:46881.9-46881.17" case 1'1 case end @@ -81473,14 +81512,14 @@ module \core update \fus_oper_i_alu_alu0__rc__ok $0\fus_oper_i_alu_alu0__rc__ok[0:0] update \fus_oper_i_alu_alu0__rc__rc $0\fus_oper_i_alu_alu0__rc__rc[0:0] end - attribute \src "libresoc.v:46858.3-46866.6" - process $proc$libresoc.v:46858$2723 + attribute \src "libresoc.v:46910.3-46918.6" + process $proc$libresoc.v:46910$2723 assign { } { } assign { } { } assign $0\wr_pick_dly$1010$next[0:0]$2724 $1\wr_pick_dly$1010$next[0:0]$2725 - attribute \src "libresoc.v:46859.5-46859.29" + attribute \src "libresoc.v:46911.5-46911.29" switch \initial - attribute \src "libresoc.v:46859.9-46859.17" + attribute \src "libresoc.v:46911.9-46911.17" case 1'1 case end @@ -81496,14 +81535,14 @@ module \core sync always update \wr_pick_dly$1010$next $0\wr_pick_dly$1010$next[0:0]$2724 end - attribute \src "libresoc.v:46867.3-46875.6" - process $proc$libresoc.v:46867$2726 + attribute \src "libresoc.v:46919.3-46927.6" + process $proc$libresoc.v:46919$2726 assign { } { } assign { } { } assign $0\wr_pick_dly$1031$next[0:0]$2727 $1\wr_pick_dly$1031$next[0:0]$2728 - attribute \src "libresoc.v:46868.5-46868.29" + attribute \src "libresoc.v:46920.5-46920.29" switch \initial - attribute \src "libresoc.v:46868.9-46868.17" + attribute \src "libresoc.v:46920.9-46920.17" case 1'1 case end @@ -81519,17 +81558,17 @@ module \core sync always update \wr_pick_dly$1031$next $0\wr_pick_dly$1031$next[0:0]$2727 end - attribute \src "libresoc.v:46876.3-46905.6" - process $proc$libresoc.v:46876$2729 + attribute \src "libresoc.v:46928.3-46957.6" + process $proc$libresoc.v:46928$2729 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__oe__oe[0:0] $1\fus_oper_i_alu_alu0__oe__oe[0:0] assign $0\fus_oper_i_alu_alu0__oe__ok[0:0] $1\fus_oper_i_alu_alu0__oe__ok[0:0] - attribute \src "libresoc.v:46877.5-46877.29" + attribute \src "libresoc.v:46929.5-46929.29" switch \initial - attribute \src "libresoc.v:46877.9-46877.17" + attribute \src "libresoc.v:46929.9-46929.17" case 1'1 case end @@ -81577,14 +81616,14 @@ module \core update \fus_oper_i_alu_alu0__oe__oe $0\fus_oper_i_alu_alu0__oe__oe[0:0] update \fus_oper_i_alu_alu0__oe__ok $0\fus_oper_i_alu_alu0__oe__ok[0:0] end - attribute \src "libresoc.v:46906.3-46914.6" - process $proc$libresoc.v:46906$2730 + attribute \src "libresoc.v:46958.3-46966.6" + process $proc$libresoc.v:46958$2730 assign { } { } assign { } { } assign $0\wr_pick_dly$1049$next[0:0]$2731 $1\wr_pick_dly$1049$next[0:0]$2732 - attribute \src "libresoc.v:46907.5-46907.29" + attribute \src "libresoc.v:46959.5-46959.29" switch \initial - attribute \src "libresoc.v:46907.9-46907.17" + attribute \src "libresoc.v:46959.9-46959.17" case 1'1 case end @@ -81600,14 +81639,14 @@ module \core sync always update \wr_pick_dly$1049$next $0\wr_pick_dly$1049$next[0:0]$2731 end - attribute \src "libresoc.v:46915.3-46923.6" - process $proc$libresoc.v:46915$2733 + attribute \src "libresoc.v:46967.3-46975.6" + process $proc$libresoc.v:46967$2733 assign { } { } assign { } { } assign $0\wr_pick_dly$1071$next[0:0]$2734 $1\wr_pick_dly$1071$next[0:0]$2735 - attribute \src "libresoc.v:46916.5-46916.29" + attribute \src "libresoc.v:46968.5-46968.29" switch \initial - attribute \src "libresoc.v:46916.9-46916.17" + attribute \src "libresoc.v:46968.9-46968.17" case 1'1 case end @@ -81623,14 +81662,14 @@ module \core sync always update \wr_pick_dly$1071$next $0\wr_pick_dly$1071$next[0:0]$2734 end - attribute \src "libresoc.v:46924.3-46932.6" - process $proc$libresoc.v:46924$2736 + attribute \src "libresoc.v:46976.3-46984.6" + process $proc$libresoc.v:46976$2736 assign { } { } assign { } { } assign $0\wr_pick_dly$1091$next[0:0]$2737 $1\wr_pick_dly$1091$next[0:0]$2738 - attribute \src "libresoc.v:46925.5-46925.29" + attribute \src "libresoc.v:46977.5-46977.29" switch \initial - attribute \src "libresoc.v:46925.9-46925.17" + attribute \src "libresoc.v:46977.9-46977.17" case 1'1 case end @@ -81646,14 +81685,14 @@ module \core sync always update \wr_pick_dly$1091$next $0\wr_pick_dly$1091$next[0:0]$2737 end - attribute \src "libresoc.v:46933.3-46961.6" - process $proc$libresoc.v:46933$2739 + attribute \src "libresoc.v:46985.3-47013.6" + process $proc$libresoc.v:46985$2739 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__invert_in[0:0] $1\fus_oper_i_alu_alu0__invert_in[0:0] - attribute \src "libresoc.v:46934.5-46934.29" + attribute \src "libresoc.v:46986.5-46986.29" switch \initial - attribute \src "libresoc.v:46934.9-46934.17" + attribute \src "libresoc.v:46986.9-46986.17" case 1'1 case end @@ -81691,14 +81730,14 @@ module \core sync always update \fus_oper_i_alu_alu0__invert_in $0\fus_oper_i_alu_alu0__invert_in[0:0] end - attribute \src "libresoc.v:46962.3-46970.6" - process $proc$libresoc.v:46962$2740 + attribute \src "libresoc.v:47014.3-47022.6" + process $proc$libresoc.v:47014$2740 assign { } { } assign { } { } assign $0\wr_pick_dly$1111$next[0:0]$2741 $1\wr_pick_dly$1111$next[0:0]$2742 - attribute \src "libresoc.v:46963.5-46963.29" + attribute \src "libresoc.v:47015.5-47015.29" switch \initial - attribute \src "libresoc.v:46963.9-46963.17" + attribute \src "libresoc.v:47015.9-47015.17" case 1'1 case end @@ -81714,14 +81753,14 @@ module \core sync always update \wr_pick_dly$1111$next $0\wr_pick_dly$1111$next[0:0]$2741 end - attribute \src "libresoc.v:46971.3-46979.6" - process $proc$libresoc.v:46971$2743 + attribute \src "libresoc.v:47023.3-47031.6" + process $proc$libresoc.v:47023$2743 assign { } { } assign { } { } assign $0\wr_pick_dly$1130$next[0:0]$2744 $1\wr_pick_dly$1130$next[0:0]$2745 - attribute \src "libresoc.v:46972.5-46972.29" + attribute \src "libresoc.v:47024.5-47024.29" switch \initial - attribute \src "libresoc.v:46972.9-46972.17" + attribute \src "libresoc.v:47024.9-47024.17" case 1'1 case end @@ -81737,14 +81776,14 @@ module \core sync always update \wr_pick_dly$1130$next $0\wr_pick_dly$1130$next[0:0]$2744 end - attribute \src "libresoc.v:46980.3-47008.6" - process $proc$libresoc.v:46980$2746 + attribute \src "libresoc.v:47032.3-47060.6" + process $proc$libresoc.v:47032$2746 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__zero_a[0:0] $1\fus_oper_i_alu_alu0__zero_a[0:0] - attribute \src "libresoc.v:46981.5-46981.29" + attribute \src "libresoc.v:47033.5-47033.29" switch \initial - attribute \src "libresoc.v:46981.9-46981.17" + attribute \src "libresoc.v:47033.9-47033.17" case 1'1 case end @@ -81782,14 +81821,14 @@ module \core sync always update \fus_oper_i_alu_alu0__zero_a $0\fus_oper_i_alu_alu0__zero_a[0:0] end - attribute \src "libresoc.v:47009.3-47017.6" - process $proc$libresoc.v:47009$2747 + attribute \src "libresoc.v:47061.3-47069.6" + process $proc$libresoc.v:47061$2747 assign { } { } assign { } { } assign $0\wr_pick_dly$1148$next[0:0]$2748 $1\wr_pick_dly$1148$next[0:0]$2749 - attribute \src "libresoc.v:47010.5-47010.29" + attribute \src "libresoc.v:47062.5-47062.29" switch \initial - attribute \src "libresoc.v:47010.9-47010.17" + attribute \src "libresoc.v:47062.9-47062.17" case 1'1 case end @@ -81805,14 +81844,14 @@ module \core sync always update \wr_pick_dly$1148$next $0\wr_pick_dly$1148$next[0:0]$2748 end - attribute \src "libresoc.v:47018.3-47046.6" - process $proc$libresoc.v:47018$2750 + attribute \src "libresoc.v:47070.3-47098.6" + process $proc$libresoc.v:47070$2750 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__invert_out[0:0] $1\fus_oper_i_alu_alu0__invert_out[0:0] - attribute \src "libresoc.v:47019.5-47019.29" + attribute \src "libresoc.v:47071.5-47071.29" switch \initial - attribute \src "libresoc.v:47019.9-47019.17" + attribute \src "libresoc.v:47071.9-47071.17" case 1'1 case end @@ -81850,14 +81889,14 @@ module \core sync always update \fus_oper_i_alu_alu0__invert_out $0\fus_oper_i_alu_alu0__invert_out[0:0] end - attribute \src "libresoc.v:47047.3-47055.6" - process $proc$libresoc.v:47047$2751 + attribute \src "libresoc.v:47099.3-47107.6" + process $proc$libresoc.v:47099$2751 assign { } { } assign { } { } assign $0\wr_pick_dly$1222$next[0:0]$2752 $1\wr_pick_dly$1222$next[0:0]$2753 - attribute \src "libresoc.v:47048.5-47048.29" + attribute \src "libresoc.v:47100.5-47100.29" switch \initial - attribute \src "libresoc.v:47048.9-47048.17" + attribute \src "libresoc.v:47100.9-47100.17" case 1'1 case end @@ -81873,14 +81912,14 @@ module \core sync always update \wr_pick_dly$1222$next $0\wr_pick_dly$1222$next[0:0]$2752 end - attribute \src "libresoc.v:47056.3-47084.6" - process $proc$libresoc.v:47056$2754 + attribute \src "libresoc.v:47108.3-47136.6" + process $proc$libresoc.v:47108$2754 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__write_cr0[0:0] $1\fus_oper_i_alu_alu0__write_cr0[0:0] - attribute \src "libresoc.v:47057.5-47057.29" + attribute \src "libresoc.v:47109.5-47109.29" switch \initial - attribute \src "libresoc.v:47057.9-47057.17" + attribute \src "libresoc.v:47109.9-47109.17" case 1'1 case end @@ -81918,14 +81957,14 @@ module \core sync always update \fus_oper_i_alu_alu0__write_cr0 $0\fus_oper_i_alu_alu0__write_cr0[0:0] end - attribute \src "libresoc.v:47085.3-47093.6" - process $proc$libresoc.v:47085$2755 + attribute \src "libresoc.v:47137.3-47145.6" + process $proc$libresoc.v:47137$2755 assign { } { } assign { } { } assign $0\wr_pick_dly$1250$next[0:0]$2756 $1\wr_pick_dly$1250$next[0:0]$2757 - attribute \src "libresoc.v:47086.5-47086.29" + attribute \src "libresoc.v:47138.5-47138.29" switch \initial - attribute \src "libresoc.v:47086.9-47086.17" + attribute \src "libresoc.v:47138.9-47138.17" case 1'1 case end @@ -81941,14 +81980,14 @@ module \core sync always update \wr_pick_dly$1250$next $0\wr_pick_dly$1250$next[0:0]$2756 end - attribute \src "libresoc.v:47094.3-47122.6" - process $proc$libresoc.v:47094$2758 + attribute \src "libresoc.v:47146.3-47174.6" + process $proc$libresoc.v:47146$2758 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__input_carry[1:0] $1\fus_oper_i_alu_alu0__input_carry[1:0] - attribute \src "libresoc.v:47095.5-47095.29" + attribute \src "libresoc.v:47147.5-47147.29" switch \initial - attribute \src "libresoc.v:47095.9-47095.17" + attribute \src "libresoc.v:47147.9-47147.17" case 1'1 case end @@ -81986,14 +82025,14 @@ module \core sync always update \fus_oper_i_alu_alu0__input_carry $0\fus_oper_i_alu_alu0__input_carry[1:0] end - attribute \src "libresoc.v:47123.3-47131.6" - process $proc$libresoc.v:47123$2759 + attribute \src "libresoc.v:47175.3-47183.6" + process $proc$libresoc.v:47175$2759 assign { } { } assign { } { } assign $0\wr_pick_dly$1270$next[0:0]$2760 $1\wr_pick_dly$1270$next[0:0]$2761 - attribute \src "libresoc.v:47124.5-47124.29" + attribute \src "libresoc.v:47176.5-47176.29" switch \initial - attribute \src "libresoc.v:47124.9-47124.17" + attribute \src "libresoc.v:47176.9-47176.17" case 1'1 case end @@ -82009,14 +82048,14 @@ module \core sync always update \wr_pick_dly$1270$next $0\wr_pick_dly$1270$next[0:0]$2760 end - attribute \src "libresoc.v:47132.3-47140.6" - process $proc$libresoc.v:47132$2762 + attribute \src "libresoc.v:47184.3-47192.6" + process $proc$libresoc.v:47184$2762 assign { } { } assign { } { } assign $0\wr_pick_dly$1290$next[0:0]$2763 $1\wr_pick_dly$1290$next[0:0]$2764 - attribute \src "libresoc.v:47133.5-47133.29" + attribute \src "libresoc.v:47185.5-47185.29" switch \initial - attribute \src "libresoc.v:47133.9-47133.17" + attribute \src "libresoc.v:47185.9-47185.17" case 1'1 case end @@ -82032,14 +82071,14 @@ module \core sync always update \wr_pick_dly$1290$next $0\wr_pick_dly$1290$next[0:0]$2763 end - attribute \src "libresoc.v:47141.3-47169.6" - process $proc$libresoc.v:47141$2765 + attribute \src "libresoc.v:47193.3-47221.6" + process $proc$libresoc.v:47193$2765 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__output_carry[0:0] $1\fus_oper_i_alu_alu0__output_carry[0:0] - attribute \src "libresoc.v:47142.5-47142.29" + attribute \src "libresoc.v:47194.5-47194.29" switch \initial - attribute \src "libresoc.v:47142.9-47142.17" + attribute \src "libresoc.v:47194.9-47194.17" case 1'1 case end @@ -82077,14 +82116,14 @@ module \core sync always update \fus_oper_i_alu_alu0__output_carry $0\fus_oper_i_alu_alu0__output_carry[0:0] end - attribute \src "libresoc.v:47170.3-47178.6" - process $proc$libresoc.v:47170$2766 + attribute \src "libresoc.v:47222.3-47230.6" + process $proc$libresoc.v:47222$2766 assign { } { } assign { } { } assign $0\wr_pick_dly$1310$next[0:0]$2767 $1\wr_pick_dly$1310$next[0:0]$2768 - attribute \src "libresoc.v:47171.5-47171.29" + attribute \src "libresoc.v:47223.5-47223.29" switch \initial - attribute \src "libresoc.v:47171.9-47171.17" + attribute \src "libresoc.v:47223.9-47223.17" case 1'1 case end @@ -82100,14 +82139,14 @@ module \core sync always update \wr_pick_dly$1310$next $0\wr_pick_dly$1310$next[0:0]$2767 end - attribute \src "libresoc.v:47179.3-47187.6" - process $proc$libresoc.v:47179$2769 + attribute \src "libresoc.v:47231.3-47239.6" + process $proc$libresoc.v:47231$2769 assign { } { } assign { } { } assign $0\wr_pick_dly$1330$next[0:0]$2770 $1\wr_pick_dly$1330$next[0:0]$2771 - attribute \src "libresoc.v:47180.5-47180.29" + attribute \src "libresoc.v:47232.5-47232.29" switch \initial - attribute \src "libresoc.v:47180.9-47180.17" + attribute \src "libresoc.v:47232.9-47232.17" case 1'1 case end @@ -82123,14 +82162,14 @@ module \core sync always update \wr_pick_dly$1330$next $0\wr_pick_dly$1330$next[0:0]$2770 end - attribute \src "libresoc.v:47188.3-47216.6" - process $proc$libresoc.v:47188$2772 + attribute \src "libresoc.v:47240.3-47268.6" + process $proc$libresoc.v:47240$2772 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__is_32bit[0:0] $1\fus_oper_i_alu_alu0__is_32bit[0:0] - attribute \src "libresoc.v:47189.5-47189.29" + attribute \src "libresoc.v:47241.5-47241.29" switch \initial - attribute \src "libresoc.v:47189.9-47189.17" + attribute \src "libresoc.v:47241.9-47241.17" case 1'1 case end @@ -82168,14 +82207,14 @@ module \core sync always update \fus_oper_i_alu_alu0__is_32bit $0\fus_oper_i_alu_alu0__is_32bit[0:0] end - attribute \src "libresoc.v:47217.3-47225.6" - process $proc$libresoc.v:47217$2773 + attribute \src "libresoc.v:47269.3-47277.6" + process $proc$libresoc.v:47269$2773 assign { } { } assign { } { } assign $0\wr_pick_dly$1350$next[0:0]$2774 $1\wr_pick_dly$1350$next[0:0]$2775 - attribute \src "libresoc.v:47218.5-47218.29" + attribute \src "libresoc.v:47270.5-47270.29" switch \initial - attribute \src "libresoc.v:47218.9-47218.17" + attribute \src "libresoc.v:47270.9-47270.17" case 1'1 case end @@ -82191,14 +82230,14 @@ module \core sync always update \wr_pick_dly$1350$next $0\wr_pick_dly$1350$next[0:0]$2774 end - attribute \src "libresoc.v:47226.3-47254.6" - process $proc$libresoc.v:47226$2776 + attribute \src "libresoc.v:47278.3-47306.6" + process $proc$libresoc.v:47278$2776 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__is_signed[0:0] $1\fus_oper_i_alu_alu0__is_signed[0:0] - attribute \src "libresoc.v:47227.5-47227.29" + attribute \src "libresoc.v:47279.5-47279.29" switch \initial - attribute \src "libresoc.v:47227.9-47227.17" + attribute \src "libresoc.v:47279.9-47279.17" case 1'1 case end @@ -82236,14 +82275,14 @@ module \core sync always update \fus_oper_i_alu_alu0__is_signed $0\fus_oper_i_alu_alu0__is_signed[0:0] end - attribute \src "libresoc.v:47255.3-47263.6" - process $proc$libresoc.v:47255$2777 + attribute \src "libresoc.v:47307.3-47315.6" + process $proc$libresoc.v:47307$2777 assign { } { } assign { } { } assign $0\wr_pick_dly$1397$next[0:0]$2778 $1\wr_pick_dly$1397$next[0:0]$2779 - attribute \src "libresoc.v:47256.5-47256.29" + attribute \src "libresoc.v:47308.5-47308.29" switch \initial - attribute \src "libresoc.v:47256.9-47256.17" + attribute \src "libresoc.v:47308.9-47308.17" case 1'1 case end @@ -82259,14 +82298,14 @@ module \core sync always update \wr_pick_dly$1397$next $0\wr_pick_dly$1397$next[0:0]$2778 end - attribute \src "libresoc.v:47264.3-47272.6" - process $proc$libresoc.v:47264$2780 + attribute \src "libresoc.v:47316.3-47324.6" + process $proc$libresoc.v:47316$2780 assign { } { } assign { } { } assign $0\wr_pick_dly$1413$next[0:0]$2781 $1\wr_pick_dly$1413$next[0:0]$2782 - attribute \src "libresoc.v:47265.5-47265.29" + attribute \src "libresoc.v:47317.5-47317.29" switch \initial - attribute \src "libresoc.v:47265.9-47265.17" + attribute \src "libresoc.v:47317.9-47317.17" case 1'1 case end @@ -82282,14 +82321,14 @@ module \core sync always update \wr_pick_dly$1413$next $0\wr_pick_dly$1413$next[0:0]$2781 end - attribute \src "libresoc.v:47273.3-47301.6" - process $proc$libresoc.v:47273$2783 + attribute \src "libresoc.v:47325.3-47353.6" + process $proc$libresoc.v:47325$2783 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__data_len[3:0] $1\fus_oper_i_alu_alu0__data_len[3:0] - attribute \src "libresoc.v:47274.5-47274.29" + attribute \src "libresoc.v:47326.5-47326.29" switch \initial - attribute \src "libresoc.v:47274.9-47274.17" + attribute \src "libresoc.v:47326.9-47326.17" case 1'1 case end @@ -82327,14 +82366,14 @@ module \core sync always update \fus_oper_i_alu_alu0__data_len $0\fus_oper_i_alu_alu0__data_len[3:0] end - attribute \src "libresoc.v:47302.3-47310.6" - process $proc$libresoc.v:47302$2784 + attribute \src "libresoc.v:47354.3-47362.6" + process $proc$libresoc.v:47354$2784 assign { } { } assign { } { } assign $0\wr_pick_dly$1429$next[0:0]$2785 $1\wr_pick_dly$1429$next[0:0]$2786 - attribute \src "libresoc.v:47303.5-47303.29" + attribute \src "libresoc.v:47355.5-47355.29" switch \initial - attribute \src "libresoc.v:47303.9-47303.17" + attribute \src "libresoc.v:47355.9-47355.17" case 1'1 case end @@ -82350,14 +82389,14 @@ module \core sync always update \wr_pick_dly$1429$next $0\wr_pick_dly$1429$next[0:0]$2785 end - attribute \src "libresoc.v:47311.3-47339.6" - process $proc$libresoc.v:47311$2787 + attribute \src "libresoc.v:47363.3-47391.6" + process $proc$libresoc.v:47363$2787 assign { } { } assign { } { } assign $0\fus_oper_i_alu_alu0__insn[31:0] $1\fus_oper_i_alu_alu0__insn[31:0] - attribute \src "libresoc.v:47312.5-47312.29" + attribute \src "libresoc.v:47364.5-47364.29" switch \initial - attribute \src "libresoc.v:47312.9-47312.17" + attribute \src "libresoc.v:47364.9-47364.17" case 1'1 case end @@ -82395,14 +82434,14 @@ module \core sync always update \fus_oper_i_alu_alu0__insn $0\fus_oper_i_alu_alu0__insn[31:0] end - attribute \src "libresoc.v:47340.3-47348.6" - process $proc$libresoc.v:47340$2788 + attribute \src "libresoc.v:47392.3-47400.6" + process $proc$libresoc.v:47392$2788 assign { } { } assign { } { } assign $0\wr_pick_dly$1463$next[0:0]$2789 $1\wr_pick_dly$1463$next[0:0]$2790 - attribute \src "libresoc.v:47341.5-47341.29" + attribute \src "libresoc.v:47393.5-47393.29" switch \initial - attribute \src "libresoc.v:47341.9-47341.17" + attribute \src "libresoc.v:47393.9-47393.17" case 1'1 case end @@ -82418,14 +82457,14 @@ module \core sync always update \wr_pick_dly$1463$next $0\wr_pick_dly$1463$next[0:0]$2789 end - attribute \src "libresoc.v:47349.3-47377.6" - process $proc$libresoc.v:47349$2791 + attribute \src "libresoc.v:47401.3-47429.6" + process $proc$libresoc.v:47401$2791 assign { } { } assign { } { } assign $0\fus_cu_issue_i[0:0] $1\fus_cu_issue_i[0:0] - attribute \src "libresoc.v:47350.5-47350.29" + attribute \src "libresoc.v:47402.5-47402.29" switch \initial - attribute \src "libresoc.v:47350.9-47350.17" + attribute \src "libresoc.v:47402.9-47402.17" case 1'1 case end @@ -82463,14 +82502,14 @@ module \core sync always update \fus_cu_issue_i $0\fus_cu_issue_i[0:0] end - attribute \src "libresoc.v:47378.3-47386.6" - process $proc$libresoc.v:47378$2792 + attribute \src "libresoc.v:47430.3-47438.6" + process $proc$libresoc.v:47430$2792 assign { } { } assign { } { } assign $0\wr_pick_dly$1479$next[0:0]$2793 $1\wr_pick_dly$1479$next[0:0]$2794 - attribute \src "libresoc.v:47379.5-47379.29" + attribute \src "libresoc.v:47431.5-47431.29" switch \initial - attribute \src "libresoc.v:47379.9-47379.17" + attribute \src "libresoc.v:47431.9-47431.17" case 1'1 case end @@ -82486,14 +82525,14 @@ module \core sync always update \wr_pick_dly$1479$next $0\wr_pick_dly$1479$next[0:0]$2793 end - attribute \src "libresoc.v:47387.3-47395.6" - process $proc$libresoc.v:47387$2795 + attribute \src "libresoc.v:47439.3-47447.6" + process $proc$libresoc.v:47439$2795 assign { } { } assign { } { } assign $0\wr_pick_dly$1495$next[0:0]$2796 $1\wr_pick_dly$1495$next[0:0]$2797 - attribute \src "libresoc.v:47388.5-47388.29" + attribute \src "libresoc.v:47440.5-47440.29" switch \initial - attribute \src "libresoc.v:47388.9-47388.17" + attribute \src "libresoc.v:47440.9-47440.17" case 1'1 case end @@ -82509,14 +82548,14 @@ module \core sync always update \wr_pick_dly$1495$next $0\wr_pick_dly$1495$next[0:0]$2796 end - attribute \src "libresoc.v:47396.3-47424.6" - process $proc$libresoc.v:47396$2798 + attribute \src "libresoc.v:47448.3-47476.6" + process $proc$libresoc.v:47448$2798 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i[3:0] $1\fus_cu_rdmaskn_i[3:0] - attribute \src "libresoc.v:47397.5-47397.29" + attribute \src "libresoc.v:47449.5-47449.29" switch \initial - attribute \src "libresoc.v:47397.9-47397.17" + attribute \src "libresoc.v:47449.9-47449.17" case 1'1 case end @@ -82554,14 +82593,14 @@ module \core sync always update \fus_cu_rdmaskn_i $0\fus_cu_rdmaskn_i[3:0] end - attribute \src "libresoc.v:47425.3-47433.6" - process $proc$libresoc.v:47425$2799 + attribute \src "libresoc.v:47477.3-47485.6" + process $proc$libresoc.v:47477$2799 assign { } { } assign { } { } assign $0\wr_pick_dly$1511$next[0:0]$2800 $1\wr_pick_dly$1511$next[0:0]$2801 - attribute \src "libresoc.v:47426.5-47426.29" + attribute \src "libresoc.v:47478.5-47478.29" switch \initial - attribute \src "libresoc.v:47426.9-47426.17" + attribute \src "libresoc.v:47478.9-47478.17" case 1'1 case end @@ -82577,14 +82616,14 @@ module \core sync always update \wr_pick_dly$1511$next $0\wr_pick_dly$1511$next[0:0]$2800 end - attribute \src "libresoc.v:47434.3-47462.6" - process $proc$libresoc.v:47434$2802 + attribute \src "libresoc.v:47486.3-47514.6" + process $proc$libresoc.v:47486$2802 assign { } { } assign { } { } assign $0\fus_oper_i_alu_cr0__insn_type[6:0] $1\fus_oper_i_alu_cr0__insn_type[6:0] - attribute \src "libresoc.v:47435.5-47435.29" + attribute \src "libresoc.v:47487.5-47487.29" switch \initial - attribute \src "libresoc.v:47435.9-47435.17" + attribute \src "libresoc.v:47487.9-47487.17" case 1'1 case end @@ -82622,14 +82661,14 @@ module \core sync always update \fus_oper_i_alu_cr0__insn_type $0\fus_oper_i_alu_cr0__insn_type[6:0] end - attribute \src "libresoc.v:47463.3-47471.6" - process $proc$libresoc.v:47463$2803 + attribute \src "libresoc.v:47515.3-47523.6" + process $proc$libresoc.v:47515$2803 assign { } { } assign { } { } assign $0\wr_pick_dly$1547$next[0:0]$2804 $1\wr_pick_dly$1547$next[0:0]$2805 - attribute \src "libresoc.v:47464.5-47464.29" + attribute \src "libresoc.v:47516.5-47516.29" switch \initial - attribute \src "libresoc.v:47464.9-47464.17" + attribute \src "libresoc.v:47516.9-47516.17" case 1'1 case end @@ -82645,14 +82684,14 @@ module \core sync always update \wr_pick_dly$1547$next $0\wr_pick_dly$1547$next[0:0]$2804 end - attribute \src "libresoc.v:47472.3-47480.6" - process $proc$libresoc.v:47472$2806 + attribute \src "libresoc.v:47524.3-47532.6" + process $proc$libresoc.v:47524$2806 assign { } { } assign { } { } assign $0\wr_pick_dly$1563$next[0:0]$2807 $1\wr_pick_dly$1563$next[0:0]$2808 - attribute \src "libresoc.v:47473.5-47473.29" + attribute \src "libresoc.v:47525.5-47525.29" switch \initial - attribute \src "libresoc.v:47473.9-47473.17" + attribute \src "libresoc.v:47525.9-47525.17" case 1'1 case end @@ -82668,14 +82707,14 @@ module \core sync always update \wr_pick_dly$1563$next $0\wr_pick_dly$1563$next[0:0]$2807 end - attribute \src "libresoc.v:47481.3-47509.6" - process $proc$libresoc.v:47481$2809 + attribute \src "libresoc.v:47533.3-47561.6" + process $proc$libresoc.v:47533$2809 assign { } { } assign { } { } assign $0\fus_oper_i_alu_cr0__fn_unit[13:0] $1\fus_oper_i_alu_cr0__fn_unit[13:0] - attribute \src "libresoc.v:47482.5-47482.29" + attribute \src "libresoc.v:47534.5-47534.29" switch \initial - attribute \src "libresoc.v:47482.9-47482.17" + attribute \src "libresoc.v:47534.9-47534.17" case 1'1 case end @@ -82713,14 +82752,14 @@ module \core sync always update \fus_oper_i_alu_cr0__fn_unit $0\fus_oper_i_alu_cr0__fn_unit[13:0] end - attribute \src "libresoc.v:47510.3-47518.6" - process $proc$libresoc.v:47510$2810 + attribute \src "libresoc.v:47562.3-47570.6" + process $proc$libresoc.v:47562$2810 assign { } { } assign { } { } assign $0\wr_pick_dly$1579$next[0:0]$2811 $1\wr_pick_dly$1579$next[0:0]$2812 - attribute \src "libresoc.v:47511.5-47511.29" + attribute \src "libresoc.v:47563.5-47563.29" switch \initial - attribute \src "libresoc.v:47511.9-47511.17" + attribute \src "libresoc.v:47563.9-47563.17" case 1'1 case end @@ -82736,14 +82775,14 @@ module \core sync always update \wr_pick_dly$1579$next $0\wr_pick_dly$1579$next[0:0]$2811 end - attribute \src "libresoc.v:47519.3-47527.6" - process $proc$libresoc.v:47519$2813 + attribute \src "libresoc.v:47571.3-47579.6" + process $proc$libresoc.v:47571$2813 assign { } { } assign { } { } assign $0\wr_pick_dly$1595$next[0:0]$2814 $1\wr_pick_dly$1595$next[0:0]$2815 - attribute \src "libresoc.v:47520.5-47520.29" + attribute \src "libresoc.v:47572.5-47572.29" switch \initial - attribute \src "libresoc.v:47520.9-47520.17" + attribute \src "libresoc.v:47572.9-47572.17" case 1'1 case end @@ -82759,14 +82798,14 @@ module \core sync always update \wr_pick_dly$1595$next $0\wr_pick_dly$1595$next[0:0]$2814 end - attribute \src "libresoc.v:47528.3-47556.6" - process $proc$libresoc.v:47528$2816 + attribute \src "libresoc.v:47580.3-47608.6" + process $proc$libresoc.v:47580$2816 assign { } { } assign { } { } assign $0\fus_oper_i_alu_cr0__insn[31:0] $1\fus_oper_i_alu_cr0__insn[31:0] - attribute \src "libresoc.v:47529.5-47529.29" + attribute \src "libresoc.v:47581.5-47581.29" switch \initial - attribute \src "libresoc.v:47529.9-47529.17" + attribute \src "libresoc.v:47581.9-47581.17" case 1'1 case end @@ -82804,14 +82843,14 @@ module \core sync always update \fus_oper_i_alu_cr0__insn $0\fus_oper_i_alu_cr0__insn[31:0] end - attribute \src "libresoc.v:47557.3-47565.6" - process $proc$libresoc.v:47557$2817 + attribute \src "libresoc.v:47609.3-47617.6" + process $proc$libresoc.v:47609$2817 assign { } { } assign { } { } assign $0\wr_pick_dly$1637$next[0:0]$2818 $1\wr_pick_dly$1637$next[0:0]$2819 - attribute \src "libresoc.v:47558.5-47558.29" + attribute \src "libresoc.v:47610.5-47610.29" switch \initial - attribute \src "libresoc.v:47558.9-47558.17" + attribute \src "libresoc.v:47610.9-47610.17" case 1'1 case end @@ -82827,14 +82866,14 @@ module \core sync always update \wr_pick_dly$1637$next $0\wr_pick_dly$1637$next[0:0]$2818 end - attribute \src "libresoc.v:47566.3-47594.6" - process $proc$libresoc.v:47566$2820 + attribute \src "libresoc.v:47618.3-47646.6" + process $proc$libresoc.v:47618$2820 assign { } { } assign { } { } assign $0\fus_cu_issue_i$13[0:0]$2821 $1\fus_cu_issue_i$13[0:0]$2822 - attribute \src "libresoc.v:47567.5-47567.29" + attribute \src "libresoc.v:47619.5-47619.29" switch \initial - attribute \src "libresoc.v:47567.9-47567.17" + attribute \src "libresoc.v:47619.9-47619.17" case 1'1 case end @@ -82872,14 +82911,14 @@ module \core sync always update \fus_cu_issue_i$13 $0\fus_cu_issue_i$13[0:0]$2821 end - attribute \src "libresoc.v:47595.3-47603.6" - process $proc$libresoc.v:47595$2825 + attribute \src "libresoc.v:47647.3-47655.6" + process $proc$libresoc.v:47647$2825 assign { } { } assign { } { } assign $0\wr_pick_dly$1656$next[0:0]$2826 $1\wr_pick_dly$1656$next[0:0]$2827 - attribute \src "libresoc.v:47596.5-47596.29" + attribute \src "libresoc.v:47648.5-47648.29" switch \initial - attribute \src "libresoc.v:47596.9-47596.17" + attribute \src "libresoc.v:47648.9-47648.17" case 1'1 case end @@ -82895,14 +82934,14 @@ module \core sync always update \wr_pick_dly$1656$next $0\wr_pick_dly$1656$next[0:0]$2826 end - attribute \src "libresoc.v:47604.3-47632.6" - process $proc$libresoc.v:47604$2828 + attribute \src "libresoc.v:47656.3-47684.6" + process $proc$libresoc.v:47656$2828 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$15[5:0]$2829 $1\fus_cu_rdmaskn_i$15[5:0]$2830 - attribute \src "libresoc.v:47605.5-47605.29" + attribute \src "libresoc.v:47657.5-47657.29" switch \initial - attribute \src "libresoc.v:47605.9-47605.17" + attribute \src "libresoc.v:47657.9-47657.17" case 1'1 case end @@ -82940,14 +82979,14 @@ module \core sync always update \fus_cu_rdmaskn_i$15 $0\fus_cu_rdmaskn_i$15[5:0]$2829 end - attribute \src "libresoc.v:47633.3-47641.6" - process $proc$libresoc.v:47633$2833 + attribute \src "libresoc.v:47685.3-47693.6" + process $proc$libresoc.v:47685$2833 assign { } { } assign { } { } assign $0\wr_pick_dly$1672$next[0:0]$2834 $1\wr_pick_dly$1672$next[0:0]$2835 - attribute \src "libresoc.v:47634.5-47634.29" + attribute \src "libresoc.v:47686.5-47686.29" switch \initial - attribute \src "libresoc.v:47634.9-47634.17" + attribute \src "libresoc.v:47686.9-47686.17" case 1'1 case end @@ -82963,14 +83002,14 @@ module \core sync always update \wr_pick_dly$1672$next $0\wr_pick_dly$1672$next[0:0]$2834 end - attribute \src "libresoc.v:47642.3-47650.6" - process $proc$libresoc.v:47642$2836 + attribute \src "libresoc.v:47694.3-47702.6" + process $proc$libresoc.v:47694$2836 assign { } { } assign { } { } assign $0\wr_pick_dly$1688$next[0:0]$2837 $1\wr_pick_dly$1688$next[0:0]$2838 - attribute \src "libresoc.v:47643.5-47643.29" + attribute \src "libresoc.v:47695.5-47695.29" switch \initial - attribute \src "libresoc.v:47643.9-47643.17" + attribute \src "libresoc.v:47695.9-47695.17" case 1'1 case end @@ -82986,14 +83025,14 @@ module \core sync always update \wr_pick_dly$1688$next $0\wr_pick_dly$1688$next[0:0]$2837 end - attribute \src "libresoc.v:47651.3-47679.6" - process $proc$libresoc.v:47651$2839 + attribute \src "libresoc.v:47703.3-47731.6" + process $proc$libresoc.v:47703$2839 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__cia[63:0] $1\fus_oper_i_alu_branch0__cia[63:0] - attribute \src "libresoc.v:47652.5-47652.29" + attribute \src "libresoc.v:47704.5-47704.29" switch \initial - attribute \src "libresoc.v:47652.9-47652.17" + attribute \src "libresoc.v:47704.9-47704.17" case 1'1 case end @@ -83031,14 +83070,14 @@ module \core sync always update \fus_oper_i_alu_branch0__cia $0\fus_oper_i_alu_branch0__cia[63:0] end - attribute \src "libresoc.v:47680.3-47688.6" - process $proc$libresoc.v:47680$2840 + attribute \src "libresoc.v:47732.3-47740.6" + process $proc$libresoc.v:47732$2840 assign { } { } assign { } { } assign $0\wr_pick_dly$1704$next[0:0]$2841 $1\wr_pick_dly$1704$next[0:0]$2842 - attribute \src "libresoc.v:47681.5-47681.29" + attribute \src "libresoc.v:47733.5-47733.29" switch \initial - attribute \src "libresoc.v:47681.9-47681.17" + attribute \src "libresoc.v:47733.9-47733.17" case 1'1 case end @@ -83054,14 +83093,14 @@ module \core sync always update \wr_pick_dly$1704$next $0\wr_pick_dly$1704$next[0:0]$2841 end - attribute \src "libresoc.v:47689.3-47717.6" - process $proc$libresoc.v:47689$2843 + attribute \src "libresoc.v:47741.3-47769.6" + process $proc$libresoc.v:47741$2843 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__insn_type[6:0] $1\fus_oper_i_alu_branch0__insn_type[6:0] - attribute \src "libresoc.v:47690.5-47690.29" + attribute \src "libresoc.v:47742.5-47742.29" switch \initial - attribute \src "libresoc.v:47690.9-47690.17" + attribute \src "libresoc.v:47742.9-47742.17" case 1'1 case end @@ -83099,14 +83138,14 @@ module \core sync always update \fus_oper_i_alu_branch0__insn_type $0\fus_oper_i_alu_branch0__insn_type[6:0] end - attribute \src "libresoc.v:47718.3-47726.6" - process $proc$libresoc.v:47718$2844 + attribute \src "libresoc.v:47770.3-47778.6" + process $proc$libresoc.v:47770$2844 assign { } { } assign { } { } assign $0\wr_pick_dly$1748$next[0:0]$2845 $1\wr_pick_dly$1748$next[0:0]$2846 - attribute \src "libresoc.v:47719.5-47719.29" + attribute \src "libresoc.v:47771.5-47771.29" switch \initial - attribute \src "libresoc.v:47719.9-47719.17" + attribute \src "libresoc.v:47771.9-47771.17" case 1'1 case end @@ -83122,14 +83161,14 @@ module \core sync always update \wr_pick_dly$1748$next $0\wr_pick_dly$1748$next[0:0]$2845 end - attribute \src "libresoc.v:47727.3-47735.6" - process $proc$libresoc.v:47727$2847 + attribute \src "libresoc.v:47779.3-47787.6" + process $proc$libresoc.v:47779$2847 assign { } { } assign { } { } assign $0\wr_pick_dly$1764$next[0:0]$2848 $1\wr_pick_dly$1764$next[0:0]$2849 - attribute \src "libresoc.v:47728.5-47728.29" + attribute \src "libresoc.v:47780.5-47780.29" switch \initial - attribute \src "libresoc.v:47728.9-47728.17" + attribute \src "libresoc.v:47780.9-47780.17" case 1'1 case end @@ -83145,14 +83184,14 @@ module \core sync always update \wr_pick_dly$1764$next $0\wr_pick_dly$1764$next[0:0]$2848 end - attribute \src "libresoc.v:47736.3-47764.6" - process $proc$libresoc.v:47736$2850 + attribute \src "libresoc.v:47788.3-47816.6" + process $proc$libresoc.v:47788$2850 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__fn_unit[13:0] $1\fus_oper_i_alu_branch0__fn_unit[13:0] - attribute \src "libresoc.v:47737.5-47737.29" + attribute \src "libresoc.v:47789.5-47789.29" switch \initial - attribute \src "libresoc.v:47737.9-47737.17" + attribute \src "libresoc.v:47789.9-47789.17" case 1'1 case end @@ -83190,14 +83229,14 @@ module \core sync always update \fus_oper_i_alu_branch0__fn_unit $0\fus_oper_i_alu_branch0__fn_unit[13:0] end - attribute \src "libresoc.v:47765.3-47773.6" - process $proc$libresoc.v:47765$2851 + attribute \src "libresoc.v:47817.3-47825.6" + process $proc$libresoc.v:47817$2851 assign { } { } assign { } { } assign $0\wr_pick_dly$1788$next[0:0]$2852 $1\wr_pick_dly$1788$next[0:0]$2853 - attribute \src "libresoc.v:47766.5-47766.29" + attribute \src "libresoc.v:47818.5-47818.29" switch \initial - attribute \src "libresoc.v:47766.9-47766.17" + attribute \src "libresoc.v:47818.9-47818.17" case 1'1 case end @@ -83213,14 +83252,14 @@ module \core sync always update \wr_pick_dly$1788$next $0\wr_pick_dly$1788$next[0:0]$2852 end - attribute \src "libresoc.v:47774.3-47802.6" - process $proc$libresoc.v:47774$2854 + attribute \src "libresoc.v:47826.3-47854.6" + process $proc$libresoc.v:47826$2854 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__insn[31:0] $1\fus_oper_i_alu_branch0__insn[31:0] - attribute \src "libresoc.v:47775.5-47775.29" + attribute \src "libresoc.v:47827.5-47827.29" switch \initial - attribute \src "libresoc.v:47775.9-47775.17" + attribute \src "libresoc.v:47827.9-47827.17" case 1'1 case end @@ -83258,14 +83297,14 @@ module \core sync always update \fus_oper_i_alu_branch0__insn $0\fus_oper_i_alu_branch0__insn[31:0] end - attribute \src "libresoc.v:47803.3-47811.6" - process $proc$libresoc.v:47803$2855 + attribute \src "libresoc.v:47855.3-47863.6" + process $proc$libresoc.v:47855$2855 assign { } { } assign { } { } assign $0\wr_pick_dly$1808$next[0:0]$2856 $1\wr_pick_dly$1808$next[0:0]$2857 - attribute \src "libresoc.v:47804.5-47804.29" + attribute \src "libresoc.v:47856.5-47856.29" switch \initial - attribute \src "libresoc.v:47804.9-47804.17" + attribute \src "libresoc.v:47856.9-47856.17" case 1'1 case end @@ -83281,17 +83320,17 @@ module \core sync always update \wr_pick_dly$1808$next $0\wr_pick_dly$1808$next[0:0]$2856 end - attribute \src "libresoc.v:47812.3-47841.6" - process $proc$libresoc.v:47812$2858 + attribute \src "libresoc.v:47864.3-47893.6" + process $proc$libresoc.v:47864$2858 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__imm_data__data[63:0] $1\fus_oper_i_alu_branch0__imm_data__data[63:0] assign $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] - attribute \src "libresoc.v:47813.5-47813.29" + attribute \src "libresoc.v:47865.5-47865.29" switch \initial - attribute \src "libresoc.v:47813.9-47813.17" + attribute \src "libresoc.v:47865.9-47865.17" case 1'1 case end @@ -83339,14 +83378,14 @@ module \core update \fus_oper_i_alu_branch0__imm_data__data $0\fus_oper_i_alu_branch0__imm_data__data[63:0] update \fus_oper_i_alu_branch0__imm_data__ok $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] end - attribute \src "libresoc.v:47842.3-47870.6" - process $proc$libresoc.v:47842$2859 + attribute \src "libresoc.v:47894.3-47922.6" + process $proc$libresoc.v:47894$2859 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__lk[0:0] $1\fus_oper_i_alu_branch0__lk[0:0] - attribute \src "libresoc.v:47843.5-47843.29" + attribute \src "libresoc.v:47895.5-47895.29" switch \initial - attribute \src "libresoc.v:47843.9-47843.17" + attribute \src "libresoc.v:47895.9-47895.17" case 1'1 case end @@ -83384,14 +83423,14 @@ module \core sync always update \fus_oper_i_alu_branch0__lk $0\fus_oper_i_alu_branch0__lk[0:0] end - attribute \src "libresoc.v:47871.3-47899.6" - process $proc$libresoc.v:47871$2860 + attribute \src "libresoc.v:47923.3-47951.6" + process $proc$libresoc.v:47923$2860 assign { } { } assign { } { } assign $0\fus_oper_i_alu_branch0__is_32bit[0:0] $1\fus_oper_i_alu_branch0__is_32bit[0:0] - attribute \src "libresoc.v:47872.5-47872.29" + attribute \src "libresoc.v:47924.5-47924.29" switch \initial - attribute \src "libresoc.v:47872.9-47872.17" + attribute \src "libresoc.v:47924.9-47924.17" case 1'1 case end @@ -83429,14 +83468,14 @@ module \core sync always update \fus_oper_i_alu_branch0__is_32bit $0\fus_oper_i_alu_branch0__is_32bit[0:0] end - attribute \src "libresoc.v:47900.3-47928.6" - process $proc$libresoc.v:47900$2861 + attribute \src "libresoc.v:47952.3-47980.6" + process $proc$libresoc.v:47952$2861 assign { } { } assign { } { } assign $0\fus_cu_issue_i$16[0:0]$2862 $1\fus_cu_issue_i$16[0:0]$2863 - attribute \src "libresoc.v:47901.5-47901.29" + attribute \src "libresoc.v:47953.5-47953.29" switch \initial - attribute \src "libresoc.v:47901.9-47901.17" + attribute \src "libresoc.v:47953.9-47953.17" case 1'1 case end @@ -83474,14 +83513,14 @@ module \core sync always update \fus_cu_issue_i$16 $0\fus_cu_issue_i$16[0:0]$2862 end - attribute \src "libresoc.v:47929.3-47957.6" - process $proc$libresoc.v:47929$2866 + attribute \src "libresoc.v:47981.3-48009.6" + process $proc$libresoc.v:47981$2866 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$18[2:0]$2867 $1\fus_cu_rdmaskn_i$18[2:0]$2868 - attribute \src "libresoc.v:47930.5-47930.29" + attribute \src "libresoc.v:47982.5-47982.29" switch \initial - attribute \src "libresoc.v:47930.9-47930.17" + attribute \src "libresoc.v:47982.9-47982.17" case 1'1 case end @@ -83519,14 +83558,14 @@ module \core sync always update \fus_cu_rdmaskn_i$18 $0\fus_cu_rdmaskn_i$18[2:0]$2867 end - attribute \src "libresoc.v:47958.3-47986.6" - process $proc$libresoc.v:47958$2871 + attribute \src "libresoc.v:48010.3-48038.6" + process $proc$libresoc.v:48010$2871 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__insn_type[6:0] $1\fus_oper_i_alu_trap0__insn_type[6:0] - attribute \src "libresoc.v:47959.5-47959.29" + attribute \src "libresoc.v:48011.5-48011.29" switch \initial - attribute \src "libresoc.v:47959.9-47959.17" + attribute \src "libresoc.v:48011.9-48011.17" case 1'1 case end @@ -83564,14 +83603,14 @@ module \core sync always update \fus_oper_i_alu_trap0__insn_type $0\fus_oper_i_alu_trap0__insn_type[6:0] end - attribute \src "libresoc.v:47987.3-48015.6" - process $proc$libresoc.v:47987$2872 + attribute \src "libresoc.v:48039.3-48067.6" + process $proc$libresoc.v:48039$2872 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__fn_unit[13:0] $1\fus_oper_i_alu_trap0__fn_unit[13:0] - attribute \src "libresoc.v:47988.5-47988.29" + attribute \src "libresoc.v:48040.5-48040.29" switch \initial - attribute \src "libresoc.v:47988.9-47988.17" + attribute \src "libresoc.v:48040.9-48040.17" case 1'1 case end @@ -83609,14 +83648,14 @@ module \core sync always update \fus_oper_i_alu_trap0__fn_unit $0\fus_oper_i_alu_trap0__fn_unit[13:0] end - attribute \src "libresoc.v:48016.3-48044.6" - process $proc$libresoc.v:48016$2873 + attribute \src "libresoc.v:48068.3-48096.6" + process $proc$libresoc.v:48068$2873 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__insn[31:0] $1\fus_oper_i_alu_trap0__insn[31:0] - attribute \src "libresoc.v:48017.5-48017.29" + attribute \src "libresoc.v:48069.5-48069.29" switch \initial - attribute \src "libresoc.v:48017.9-48017.17" + attribute \src "libresoc.v:48069.9-48069.17" case 1'1 case end @@ -83654,14 +83693,14 @@ module \core sync always update \fus_oper_i_alu_trap0__insn $0\fus_oper_i_alu_trap0__insn[31:0] end - attribute \src "libresoc.v:48045.3-48073.6" - process $proc$libresoc.v:48045$2874 + attribute \src "libresoc.v:48097.3-48125.6" + process $proc$libresoc.v:48097$2874 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__msr[63:0] $1\fus_oper_i_alu_trap0__msr[63:0] - attribute \src "libresoc.v:48046.5-48046.29" + attribute \src "libresoc.v:48098.5-48098.29" switch \initial - attribute \src "libresoc.v:48046.9-48046.17" + attribute \src "libresoc.v:48098.9-48098.17" case 1'1 case end @@ -83699,14 +83738,14 @@ module \core sync always update \fus_oper_i_alu_trap0__msr $0\fus_oper_i_alu_trap0__msr[63:0] end - attribute \src "libresoc.v:48074.3-48102.6" - process $proc$libresoc.v:48074$2875 + attribute \src "libresoc.v:48126.3-48154.6" + process $proc$libresoc.v:48126$2875 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__cia[63:0] $1\fus_oper_i_alu_trap0__cia[63:0] - attribute \src "libresoc.v:48075.5-48075.29" + attribute \src "libresoc.v:48127.5-48127.29" switch \initial - attribute \src "libresoc.v:48075.9-48075.17" + attribute \src "libresoc.v:48127.9-48127.17" case 1'1 case end @@ -83744,14 +83783,14 @@ module \core sync always update \fus_oper_i_alu_trap0__cia $0\fus_oper_i_alu_trap0__cia[63:0] end - attribute \src "libresoc.v:48103.3-48131.6" - process $proc$libresoc.v:48103$2876 + attribute \src "libresoc.v:48155.3-48183.6" + process $proc$libresoc.v:48155$2876 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__is_32bit[0:0] $1\fus_oper_i_alu_trap0__is_32bit[0:0] - attribute \src "libresoc.v:48104.5-48104.29" + attribute \src "libresoc.v:48156.5-48156.29" switch \initial - attribute \src "libresoc.v:48104.9-48104.17" + attribute \src "libresoc.v:48156.9-48156.17" case 1'1 case end @@ -83789,14 +83828,14 @@ module \core sync always update \fus_oper_i_alu_trap0__is_32bit $0\fus_oper_i_alu_trap0__is_32bit[0:0] end - attribute \src "libresoc.v:48132.3-48160.6" - process $proc$libresoc.v:48132$2877 + attribute \src "libresoc.v:48184.3-48212.6" + process $proc$libresoc.v:48184$2877 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__traptype[7:0] $1\fus_oper_i_alu_trap0__traptype[7:0] - attribute \src "libresoc.v:48133.5-48133.29" + attribute \src "libresoc.v:48185.5-48185.29" switch \initial - attribute \src "libresoc.v:48133.9-48133.17" + attribute \src "libresoc.v:48185.9-48185.17" case 1'1 case end @@ -83834,14 +83873,14 @@ module \core sync always update \fus_oper_i_alu_trap0__traptype $0\fus_oper_i_alu_trap0__traptype[7:0] end - attribute \src "libresoc.v:48161.3-48189.6" - process $proc$libresoc.v:48161$2878 + attribute \src "libresoc.v:48213.3-48241.6" + process $proc$libresoc.v:48213$2878 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__trapaddr[12:0] $1\fus_oper_i_alu_trap0__trapaddr[12:0] - attribute \src "libresoc.v:48162.5-48162.29" + attribute \src "libresoc.v:48214.5-48214.29" switch \initial - attribute \src "libresoc.v:48162.9-48162.17" + attribute \src "libresoc.v:48214.9-48214.17" case 1'1 case end @@ -83879,14 +83918,14 @@ module \core sync always update \fus_oper_i_alu_trap0__trapaddr $0\fus_oper_i_alu_trap0__trapaddr[12:0] end - attribute \src "libresoc.v:48190.3-48218.6" - process $proc$libresoc.v:48190$2879 + attribute \src "libresoc.v:48242.3-48270.6" + process $proc$libresoc.v:48242$2879 assign { } { } assign { } { } assign $0\fus_oper_i_alu_trap0__ldst_exc[7:0] $1\fus_oper_i_alu_trap0__ldst_exc[7:0] - attribute \src "libresoc.v:48191.5-48191.29" + attribute \src "libresoc.v:48243.5-48243.29" switch \initial - attribute \src "libresoc.v:48191.9-48191.17" + attribute \src "libresoc.v:48243.9-48243.17" case 1'1 case end @@ -83924,14 +83963,14 @@ module \core sync always update \fus_oper_i_alu_trap0__ldst_exc $0\fus_oper_i_alu_trap0__ldst_exc[7:0] end - attribute \src "libresoc.v:48219.3-48247.6" - process $proc$libresoc.v:48219$2880 + attribute \src "libresoc.v:48271.3-48299.6" + process $proc$libresoc.v:48271$2880 assign { } { } assign { } { } assign $0\fus_cu_issue_i$19[0:0]$2881 $1\fus_cu_issue_i$19[0:0]$2882 - attribute \src "libresoc.v:48220.5-48220.29" + attribute \src "libresoc.v:48272.5-48272.29" switch \initial - attribute \src "libresoc.v:48220.9-48220.17" + attribute \src "libresoc.v:48272.9-48272.17" case 1'1 case end @@ -83969,14 +84008,14 @@ module \core sync always update \fus_cu_issue_i$19 $0\fus_cu_issue_i$19[0:0]$2881 end - attribute \src "libresoc.v:48248.3-48276.6" - process $proc$libresoc.v:48248$2885 + attribute \src "libresoc.v:48300.3-48328.6" + process $proc$libresoc.v:48300$2885 assign { } { } assign { } { } assign $0\fus_cu_rdmaskn_i$21[3:0]$2886 $1\fus_cu_rdmaskn_i$21[3:0]$2887 - attribute \src "libresoc.v:48249.5-48249.29" + attribute \src "libresoc.v:48301.5-48301.29" switch \initial - attribute \src "libresoc.v:48249.9-48249.17" + attribute \src "libresoc.v:48301.9-48301.17" case 1'1 case end @@ -84014,14 +84053,14 @@ module \core sync always update \fus_cu_rdmaskn_i$21 $0\fus_cu_rdmaskn_i$21[3:0]$2886 end - attribute \src "libresoc.v:48277.3-48305.6" - process $proc$libresoc.v:48277$2890 + attribute \src "libresoc.v:48329.3-48357.6" + process $proc$libresoc.v:48329$2890 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__insn_type[6:0] $1\fus_oper_i_alu_logical0__insn_type[6:0] - attribute \src "libresoc.v:48278.5-48278.29" + attribute \src "libresoc.v:48330.5-48330.29" switch \initial - attribute \src "libresoc.v:48278.9-48278.17" + attribute \src "libresoc.v:48330.9-48330.17" case 1'1 case end @@ -84059,14 +84098,14 @@ module \core sync always update \fus_oper_i_alu_logical0__insn_type $0\fus_oper_i_alu_logical0__insn_type[6:0] end - attribute \src "libresoc.v:48306.3-48334.6" - process $proc$libresoc.v:48306$2891 + attribute \src "libresoc.v:48358.3-48386.6" + process $proc$libresoc.v:48358$2891 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__fn_unit[13:0] $1\fus_oper_i_alu_logical0__fn_unit[13:0] - attribute \src "libresoc.v:48307.5-48307.29" + attribute \src "libresoc.v:48359.5-48359.29" switch \initial - attribute \src "libresoc.v:48307.9-48307.17" + attribute \src "libresoc.v:48359.9-48359.17" case 1'1 case end @@ -84104,17 +84143,17 @@ module \core sync always update \fus_oper_i_alu_logical0__fn_unit $0\fus_oper_i_alu_logical0__fn_unit[13:0] end - attribute \src "libresoc.v:48335.3-48364.6" - process $proc$libresoc.v:48335$2892 + attribute \src "libresoc.v:48387.3-48416.6" + process $proc$libresoc.v:48387$2892 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__imm_data__data[63:0] $1\fus_oper_i_alu_logical0__imm_data__data[63:0] assign $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] - attribute \src "libresoc.v:48336.5-48336.29" + attribute \src "libresoc.v:48388.5-48388.29" switch \initial - attribute \src "libresoc.v:48336.9-48336.17" + attribute \src "libresoc.v:48388.9-48388.17" case 1'1 case end @@ -84162,17 +84201,17 @@ module \core update \fus_oper_i_alu_logical0__imm_data__data $0\fus_oper_i_alu_logical0__imm_data__data[63:0] update \fus_oper_i_alu_logical0__imm_data__ok $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] end - attribute \src "libresoc.v:48365.3-48394.6" - process $proc$libresoc.v:48365$2893 + attribute \src "libresoc.v:48417.3-48446.6" + process $proc$libresoc.v:48417$2893 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__rc__ok[0:0] $1\fus_oper_i_alu_logical0__rc__ok[0:0] assign $0\fus_oper_i_alu_logical0__rc__rc[0:0] $1\fus_oper_i_alu_logical0__rc__rc[0:0] - attribute \src "libresoc.v:48366.5-48366.29" + attribute \src "libresoc.v:48418.5-48418.29" switch \initial - attribute \src "libresoc.v:48366.9-48366.17" + attribute \src "libresoc.v:48418.9-48418.17" case 1'1 case end @@ -84220,17 +84259,17 @@ module \core update \fus_oper_i_alu_logical0__rc__ok $0\fus_oper_i_alu_logical0__rc__ok[0:0] update \fus_oper_i_alu_logical0__rc__rc $0\fus_oper_i_alu_logical0__rc__rc[0:0] end - attribute \src "libresoc.v:48395.3-48424.6" - process $proc$libresoc.v:48395$2894 + attribute \src "libresoc.v:48447.3-48476.6" + process $proc$libresoc.v:48447$2894 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__oe__oe[0:0] $1\fus_oper_i_alu_logical0__oe__oe[0:0] assign $0\fus_oper_i_alu_logical0__oe__ok[0:0] $1\fus_oper_i_alu_logical0__oe__ok[0:0] - attribute \src "libresoc.v:48396.5-48396.29" + attribute \src "libresoc.v:48448.5-48448.29" switch \initial - attribute \src "libresoc.v:48396.9-48396.17" + attribute \src "libresoc.v:48448.9-48448.17" case 1'1 case end @@ -84278,14 +84317,14 @@ module \core update \fus_oper_i_alu_logical0__oe__oe $0\fus_oper_i_alu_logical0__oe__oe[0:0] update \fus_oper_i_alu_logical0__oe__ok $0\fus_oper_i_alu_logical0__oe__ok[0:0] end - attribute \src "libresoc.v:48425.3-48453.6" - process $proc$libresoc.v:48425$2895 + attribute \src "libresoc.v:48477.3-48505.6" + process $proc$libresoc.v:48477$2895 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__invert_in[0:0] $1\fus_oper_i_alu_logical0__invert_in[0:0] - attribute \src "libresoc.v:48426.5-48426.29" + attribute \src "libresoc.v:48478.5-48478.29" switch \initial - attribute \src "libresoc.v:48426.9-48426.17" + attribute \src "libresoc.v:48478.9-48478.17" case 1'1 case end @@ -84323,14 +84362,14 @@ module \core sync always update \fus_oper_i_alu_logical0__invert_in $0\fus_oper_i_alu_logical0__invert_in[0:0] end - attribute \src "libresoc.v:48454.3-48482.6" - process $proc$libresoc.v:48454$2896 + attribute \src "libresoc.v:48506.3-48534.6" + process $proc$libresoc.v:48506$2896 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__zero_a[0:0] $1\fus_oper_i_alu_logical0__zero_a[0:0] - attribute \src "libresoc.v:48455.5-48455.29" + attribute \src "libresoc.v:48507.5-48507.29" switch \initial - attribute \src "libresoc.v:48455.9-48455.17" + attribute \src "libresoc.v:48507.9-48507.17" case 1'1 case end @@ -84368,14 +84407,14 @@ module \core sync always update \fus_oper_i_alu_logical0__zero_a $0\fus_oper_i_alu_logical0__zero_a[0:0] end - attribute \src "libresoc.v:48483.3-48511.6" - process $proc$libresoc.v:48483$2897 + attribute \src "libresoc.v:48535.3-48563.6" + process $proc$libresoc.v:48535$2897 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__input_carry[1:0] $1\fus_oper_i_alu_logical0__input_carry[1:0] - attribute \src "libresoc.v:48484.5-48484.29" + attribute \src "libresoc.v:48536.5-48536.29" switch \initial - attribute \src "libresoc.v:48484.9-48484.17" + attribute \src "libresoc.v:48536.9-48536.17" case 1'1 case end @@ -84413,14 +84452,14 @@ module \core sync always update \fus_oper_i_alu_logical0__input_carry $0\fus_oper_i_alu_logical0__input_carry[1:0] end - attribute \src "libresoc.v:48512.3-48540.6" - process $proc$libresoc.v:48512$2898 + attribute \src "libresoc.v:48564.3-48592.6" + process $proc$libresoc.v:48564$2898 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__invert_out[0:0] $1\fus_oper_i_alu_logical0__invert_out[0:0] - attribute \src "libresoc.v:48513.5-48513.29" + attribute \src "libresoc.v:48565.5-48565.29" switch \initial - attribute \src "libresoc.v:48513.9-48513.17" + attribute \src "libresoc.v:48565.9-48565.17" case 1'1 case end @@ -84458,14 +84497,14 @@ module \core sync always update \fus_oper_i_alu_logical0__invert_out $0\fus_oper_i_alu_logical0__invert_out[0:0] end - attribute \src "libresoc.v:48541.3-48569.6" - process $proc$libresoc.v:48541$2899 + attribute \src "libresoc.v:48593.3-48621.6" + process $proc$libresoc.v:48593$2899 assign { } { } assign { } { } assign $0\fus_oper_i_alu_logical0__write_cr0[0:0] $1\fus_oper_i_alu_logical0__write_cr0[0:0] - attribute \src "libresoc.v:48542.5-48542.29" + attribute \src "libresoc.v:48594.5-48594.29" switch \initial - attribute \src "libresoc.v:48542.9-48542.17" + attribute \src "libresoc.v:48594.9-48594.17" case 1'1 case end @@ -84503,731 +84542,731 @@ module \core sync always update \fus_oper_i_alu_logical0__write_cr0 $0\fus_oper_i_alu_logical0__write_cr0[0:0] end - connect \$1000 $and$libresoc.v:42103$1506_Y - connect \$1003 $ternary$libresoc.v:42104$1507_Y - connect \$1005 $and$libresoc.v:42105$1508_Y - connect \$1008 $and$libresoc.v:42106$1509_Y - connect \$1012 $not$libresoc.v:42107$1510_Y - connect \$1014 $and$libresoc.v:42108$1511_Y - connect \$1021 $and$libresoc.v:42109$1512_Y - connect \$1024 $ternary$libresoc.v:42110$1513_Y - connect \$1026 $and$libresoc.v:42111$1514_Y - connect \$1029 $and$libresoc.v:42112$1515_Y - connect \$1033 $not$libresoc.v:42113$1516_Y - connect \$1035 $and$libresoc.v:42114$1517_Y - connect \$1039 $and$libresoc.v:42115$1518_Y - connect \$1042 $ternary$libresoc.v:42116$1519_Y - connect \$1044 $and$libresoc.v:42117$1520_Y - connect \$1047 $and$libresoc.v:42118$1521_Y - connect \$1051 $not$libresoc.v:42119$1522_Y - connect \$1053 $and$libresoc.v:42120$1523_Y - connect \$1061 $and$libresoc.v:42121$1524_Y - connect \$1064 $ternary$libresoc.v:42122$1525_Y - connect \$1066 $and$libresoc.v:42123$1526_Y - connect \$1069 $and$libresoc.v:42124$1527_Y - connect \$1073 $not$libresoc.v:42125$1528_Y - connect \$1075 $and$libresoc.v:42126$1529_Y - connect \$1081 $and$libresoc.v:42127$1530_Y - connect \$1084 $ternary$libresoc.v:42128$1531_Y - connect \$1086 $and$libresoc.v:42129$1532_Y - connect \$1089 $and$libresoc.v:42130$1533_Y - connect \$1093 $not$libresoc.v:42131$1534_Y - connect \$1095 $and$libresoc.v:42132$1535_Y - connect \$1101 $and$libresoc.v:42133$1536_Y - connect \$1104 $ternary$libresoc.v:42134$1537_Y - connect \$1106 $and$libresoc.v:42135$1538_Y - connect \$1109 $and$libresoc.v:42136$1539_Y - connect \$1113 $not$libresoc.v:42137$1540_Y - connect \$1115 $and$libresoc.v:42138$1541_Y - connect \$1120 $and$libresoc.v:42139$1542_Y - connect \$1123 $ternary$libresoc.v:42140$1543_Y - connect \$1125 $and$libresoc.v:42141$1544_Y - connect \$1128 $and$libresoc.v:42142$1545_Y - connect \$1132 $not$libresoc.v:42143$1546_Y - connect \$1134 $and$libresoc.v:42144$1547_Y - connect \$1138 $and$libresoc.v:42145$1548_Y - connect \$1141 $ternary$libresoc.v:42146$1549_Y - connect \$1143 $and$libresoc.v:42147$1550_Y - connect \$1146 $and$libresoc.v:42148$1551_Y - connect \$1149 $not$libresoc.v:42149$1552_Y - connect \$1151 $and$libresoc.v:42150$1553_Y - connect \$1154 $and$libresoc.v:42151$1554_Y - connect \$1157 $ternary$libresoc.v:42152$1555_Y - connect \$1160 $or$libresoc.v:42153$1556_Y - connect \$1162 $or$libresoc.v:42154$1557_Y - connect \$1164 $or$libresoc.v:42155$1558_Y - connect \$1166 $or$libresoc.v:42156$1559_Y - connect \$1168 $or$libresoc.v:42157$1560_Y - connect \$1170 $or$libresoc.v:42158$1561_Y - connect \$1172 $or$libresoc.v:42159$1562_Y - connect \$1174 $or$libresoc.v:42160$1563_Y - connect \$1176 $or$libresoc.v:42161$1564_Y - connect \$1179 $or$libresoc.v:42162$1565_Y - connect \$1181 $or$libresoc.v:42163$1566_Y - connect \$1183 $or$libresoc.v:42164$1567_Y - connect \$1185 $or$libresoc.v:42165$1568_Y - connect \$1187 $or$libresoc.v:42166$1569_Y - connect \$1189 $or$libresoc.v:42167$1570_Y - connect \$1191 $or$libresoc.v:42168$1571_Y - connect \$1193 $or$libresoc.v:42169$1572_Y - connect \$1195 $or$libresoc.v:42170$1573_Y - connect \$1197 $or$libresoc.v:42171$1574_Y - connect \$1199 $or$libresoc.v:42172$1575_Y - connect \$1201 $or$libresoc.v:42173$1576_Y - connect \$1203 $or$libresoc.v:42174$1577_Y - connect \$1205 $or$libresoc.v:42175$1578_Y - connect \$1207 $or$libresoc.v:42176$1579_Y - connect \$1209 $or$libresoc.v:42177$1580_Y - connect \$1211 $or$libresoc.v:42178$1581_Y - connect \$1213 $or$libresoc.v:42179$1582_Y - connect \$1215 $and$libresoc.v:42180$1583_Y - connect \$1217 $and$libresoc.v:42181$1584_Y - connect \$1220 $and$libresoc.v:42182$1585_Y - connect \$1223 $not$libresoc.v:42183$1586_Y - connect \$1225 $and$libresoc.v:42184$1587_Y - connect \$1228 $and$libresoc.v:42185$1588_Y - connect \$1231 $ternary$libresoc.v:42186$1589_Y - connect \$1233 $and$libresoc.v:42187$1590_Y - connect \$1235 $and$libresoc.v:42188$1591_Y - connect \$1237 $and$libresoc.v:42189$1592_Y - connect \$1239 $and$libresoc.v:42190$1593_Y - connect \$1241 $and$libresoc.v:42191$1594_Y - connect \$1243 $and$libresoc.v:42192$1595_Y - connect \$1245 $and$libresoc.v:42193$1596_Y - connect \$1248 $and$libresoc.v:42194$1597_Y - connect \$1251 $not$libresoc.v:42195$1598_Y - connect \$1253 $and$libresoc.v:42196$1599_Y - connect \$1256 $and$libresoc.v:42197$1600_Y - connect \$1259 $sub$libresoc.v:42198$1601_Y - connect \$1261 $sshl$libresoc.v:42199$1602_Y - connect \$1263 $ternary$libresoc.v:42200$1603_Y - connect \$1265 $and$libresoc.v:42201$1604_Y - connect \$1268 $and$libresoc.v:42202$1605_Y - connect \$1271 $not$libresoc.v:42203$1606_Y - connect \$1273 $and$libresoc.v:42204$1607_Y - connect \$1276 $and$libresoc.v:42205$1608_Y - connect \$1279 $sub$libresoc.v:42206$1609_Y - connect \$1281 $sshl$libresoc.v:42207$1610_Y - connect \$1283 $ternary$libresoc.v:42208$1611_Y - connect \$1285 $and$libresoc.v:42209$1612_Y - connect \$1288 $and$libresoc.v:42210$1613_Y - connect \$1291 $not$libresoc.v:42211$1614_Y - connect \$1293 $and$libresoc.v:42212$1615_Y - connect \$1296 $and$libresoc.v:42213$1616_Y - connect \$1299 $sub$libresoc.v:42214$1617_Y - connect \$1301 $sshl$libresoc.v:42215$1618_Y - connect \$1303 $ternary$libresoc.v:42216$1619_Y - connect \$1305 $and$libresoc.v:42217$1620_Y - connect \$1308 $and$libresoc.v:42218$1621_Y - connect \$1311 $not$libresoc.v:42219$1622_Y - connect \$1313 $and$libresoc.v:42220$1623_Y - connect \$1316 $and$libresoc.v:42221$1624_Y - connect \$1319 $sub$libresoc.v:42222$1625_Y - connect \$1321 $sshl$libresoc.v:42223$1626_Y - connect \$1323 $ternary$libresoc.v:42224$1627_Y - connect \$1325 $and$libresoc.v:42225$1628_Y - connect \$1328 $and$libresoc.v:42226$1629_Y - connect \$1331 $not$libresoc.v:42227$1630_Y - connect \$1333 $and$libresoc.v:42228$1631_Y - connect \$1336 $and$libresoc.v:42229$1632_Y - connect \$1339 $sub$libresoc.v:42230$1633_Y - connect \$1341 $sshl$libresoc.v:42231$1634_Y - connect \$1343 $ternary$libresoc.v:42232$1635_Y - connect \$1345 $and$libresoc.v:42233$1636_Y - connect \$1348 $and$libresoc.v:42234$1637_Y - connect \$1351 $not$libresoc.v:42235$1638_Y - connect \$1353 $and$libresoc.v:42236$1639_Y - connect \$1356 $and$libresoc.v:42237$1640_Y - connect \$1359 $sub$libresoc.v:42238$1641_Y - connect \$1361 $sshl$libresoc.v:42239$1642_Y - connect \$1363 $ternary$libresoc.v:42240$1643_Y - connect \$1365 $or$libresoc.v:42241$1644_Y - connect \$1367 $or$libresoc.v:42242$1645_Y - connect \$1369 $or$libresoc.v:42243$1646_Y - connect \$1371 $or$libresoc.v:42244$1647_Y - connect \$1373 $or$libresoc.v:42245$1648_Y - connect \$1376 $or$libresoc.v:42246$1649_Y - connect \$1378 $or$libresoc.v:42247$1650_Y - connect \$1380 $or$libresoc.v:42248$1651_Y - connect \$1382 $or$libresoc.v:42249$1652_Y - connect \$1384 $or$libresoc.v:42250$1653_Y - connect \$1386 $and$libresoc.v:42251$1654_Y - connect \$1388 $and$libresoc.v:42252$1655_Y - connect \$1390 $and$libresoc.v:42253$1656_Y - connect \$1392 $and$libresoc.v:42254$1657_Y - connect \$1395 $and$libresoc.v:42255$1658_Y - connect \$1398 $not$libresoc.v:42256$1659_Y - connect \$1400 $and$libresoc.v:42257$1660_Y - connect \$1403 $and$libresoc.v:42258$1661_Y - connect \$1406 $ternary$libresoc.v:42259$1662_Y - connect \$1408 $and$libresoc.v:42260$1663_Y - connect \$1411 $and$libresoc.v:42261$1664_Y - connect \$1414 $not$libresoc.v:42262$1665_Y - connect \$1416 $and$libresoc.v:42263$1666_Y - connect \$1419 $and$libresoc.v:42264$1667_Y - connect \$1422 $ternary$libresoc.v:42265$1668_Y - connect \$1424 $and$libresoc.v:42266$1669_Y - connect \$1427 $and$libresoc.v:42267$1670_Y - connect \$1430 $not$libresoc.v:42268$1671_Y - connect \$1432 $and$libresoc.v:42269$1672_Y - connect \$1435 $and$libresoc.v:42270$1673_Y - connect \$1438 $ternary$libresoc.v:42271$1674_Y - connect \$1440 $or$libresoc.v:42272$1675_Y - connect \$1442 $or$libresoc.v:42273$1676_Y - connect \$1445 $or$libresoc.v:42274$1677_Y - connect \$1447 $or$libresoc.v:42275$1678_Y - connect \$1444 $pos$libresoc.v:42276$1680_Y - connect \$1450 $and$libresoc.v:42277$1681_Y - connect \$1452 $and$libresoc.v:42278$1682_Y - connect \$1454 $and$libresoc.v:42279$1683_Y - connect \$1456 $and$libresoc.v:42280$1684_Y - connect \$1458 $and$libresoc.v:42281$1685_Y - connect \$1461 $and$libresoc.v:42282$1686_Y - connect \$1464 $not$libresoc.v:42283$1687_Y - connect \$1466 $and$libresoc.v:42284$1688_Y - connect \$1469 $and$libresoc.v:42285$1689_Y - connect \$1472 $ternary$libresoc.v:42286$1690_Y - connect \$1474 $and$libresoc.v:42287$1691_Y - connect \$1477 $and$libresoc.v:42288$1692_Y - connect \$1480 $not$libresoc.v:42289$1693_Y - connect \$1482 $and$libresoc.v:42290$1694_Y - connect \$1485 $and$libresoc.v:42291$1695_Y - connect \$1488 $ternary$libresoc.v:42292$1696_Y - connect \$1490 $and$libresoc.v:42293$1697_Y - connect \$1493 $and$libresoc.v:42294$1698_Y - connect \$1496 $not$libresoc.v:42295$1699_Y - connect \$1498 $and$libresoc.v:42296$1700_Y - connect \$1501 $and$libresoc.v:42297$1701_Y - connect \$1504 $ternary$libresoc.v:42298$1702_Y - connect \$1506 $and$libresoc.v:42299$1703_Y - connect \$1509 $and$libresoc.v:42300$1704_Y - connect \$1512 $not$libresoc.v:42301$1705_Y - connect \$1514 $and$libresoc.v:42302$1706_Y - connect \$1517 $and$libresoc.v:42303$1707_Y - connect \$1520 $ternary$libresoc.v:42304$1708_Y - connect \$1522 $or$libresoc.v:42305$1709_Y - connect \$1524 $or$libresoc.v:42306$1710_Y - connect \$1526 $or$libresoc.v:42307$1711_Y - connect \$1528 $or$libresoc.v:42308$1712_Y - connect \$1530 $or$libresoc.v:42309$1713_Y - connect \$1532 $or$libresoc.v:42310$1714_Y - connect \$1534 $and$libresoc.v:42311$1715_Y - connect \$1536 $and$libresoc.v:42312$1716_Y - connect \$1538 $and$libresoc.v:42313$1717_Y - connect \$1540 $and$libresoc.v:42314$1718_Y - connect \$1542 $and$libresoc.v:42315$1719_Y - connect \$1545 $and$libresoc.v:42316$1720_Y - connect \$1548 $not$libresoc.v:42317$1721_Y - connect \$1550 $and$libresoc.v:42318$1722_Y - connect \$1553 $and$libresoc.v:42319$1723_Y - connect \$1556 $ternary$libresoc.v:42320$1724_Y - connect \$1558 $and$libresoc.v:42321$1725_Y - connect \$1561 $and$libresoc.v:42322$1726_Y - connect \$1564 $not$libresoc.v:42323$1727_Y - connect \$1566 $and$libresoc.v:42324$1728_Y - connect \$1569 $and$libresoc.v:42325$1729_Y - connect \$1572 $ternary$libresoc.v:42326$1730_Y - connect \$1574 $and$libresoc.v:42327$1731_Y - connect \$1577 $and$libresoc.v:42328$1732_Y - connect \$1580 $not$libresoc.v:42329$1733_Y - connect \$1582 $and$libresoc.v:42330$1734_Y - connect \$1585 $and$libresoc.v:42331$1735_Y - connect \$1588 $ternary$libresoc.v:42332$1736_Y - connect \$1590 $and$libresoc.v:42333$1737_Y - connect \$1593 $and$libresoc.v:42334$1738_Y - connect \$1596 $not$libresoc.v:42335$1739_Y - connect \$1598 $and$libresoc.v:42336$1740_Y - connect \$1601 $and$libresoc.v:42337$1741_Y - connect \$1604 $ternary$libresoc.v:42338$1742_Y - connect \$1607 $or$libresoc.v:42339$1743_Y - connect \$1609 $or$libresoc.v:42340$1744_Y - connect \$1611 $or$libresoc.v:42341$1745_Y - connect \$1606 $pos$libresoc.v:42342$1747_Y - connect \$1615 $or$libresoc.v:42343$1748_Y - connect \$1617 $or$libresoc.v:42344$1749_Y - connect \$1619 $or$libresoc.v:42345$1750_Y - connect \$1614 $pos$libresoc.v:42346$1752_Y - connect \$1622 $and$libresoc.v:42347$1753_Y - connect \$1624 $and$libresoc.v:42348$1754_Y - connect \$1626 $and$libresoc.v:42349$1755_Y - connect \$1628 $and$libresoc.v:42350$1756_Y - connect \$1630 $and$libresoc.v:42351$1757_Y - connect \$1632 $and$libresoc.v:42352$1758_Y - connect \$1635 $and$libresoc.v:42353$1759_Y - connect \$1639 $not$libresoc.v:42354$1760_Y - connect \$1641 $and$libresoc.v:42355$1761_Y - connect \$1646 $and$libresoc.v:42356$1762_Y - connect \$1649 $ternary$libresoc.v:42357$1763_Y - connect \$1651 $and$libresoc.v:42358$1764_Y - connect \$1654 $and$libresoc.v:42359$1765_Y - connect \$1657 $not$libresoc.v:42360$1766_Y - connect \$1659 $and$libresoc.v:42361$1767_Y - connect \$1662 $and$libresoc.v:42362$1768_Y - connect \$1665 $ternary$libresoc.v:42363$1769_Y - connect \$1667 $and$libresoc.v:42364$1770_Y - connect \$1670 $and$libresoc.v:42365$1771_Y - connect \$1673 $not$libresoc.v:42366$1772_Y - connect \$1675 $and$libresoc.v:42367$1773_Y - connect \$1678 $and$libresoc.v:42368$1774_Y - connect \$1681 $ternary$libresoc.v:42369$1775_Y - connect \$1683 $and$libresoc.v:42370$1776_Y - connect \$1686 $and$libresoc.v:42371$1777_Y - connect \$1689 $not$libresoc.v:42372$1778_Y - connect \$1691 $and$libresoc.v:42373$1779_Y - connect \$1694 $and$libresoc.v:42374$1780_Y - connect \$1697 $ternary$libresoc.v:42375$1781_Y - connect \$1699 $and$libresoc.v:42376$1782_Y - connect \$1702 $and$libresoc.v:42377$1783_Y - connect \$1705 $not$libresoc.v:42378$1784_Y - connect \$1707 $and$libresoc.v:42379$1785_Y - connect \$1710 $and$libresoc.v:42380$1786_Y - connect \$1713 $ternary$libresoc.v:42381$1787_Y - connect \$1715 $or$libresoc.v:42382$1788_Y - connect \$1717 $or$libresoc.v:42383$1789_Y - connect \$1719 $or$libresoc.v:42384$1790_Y - connect \$1721 $or$libresoc.v:42385$1791_Y - connect \$1723 $or$libresoc.v:42386$1792_Y - connect \$1725 $or$libresoc.v:42387$1793_Y - connect \$1727 $or$libresoc.v:42388$1794_Y - connect \$1729 $or$libresoc.v:42389$1795_Y - connect \$1731 $or$libresoc.v:42390$1796_Y - connect \$1733 $or$libresoc.v:42391$1797_Y - connect \$1735 $or$libresoc.v:42392$1798_Y - connect \$1737 $or$libresoc.v:42393$1799_Y - connect \$1739 $and$libresoc.v:42394$1800_Y - connect \$1741 $and$libresoc.v:42395$1801_Y - connect \$1743 $and$libresoc.v:42396$1802_Y - connect \$1746 $and$libresoc.v:42397$1803_Y - connect \$1749 $not$libresoc.v:42398$1804_Y - connect \$1751 $and$libresoc.v:42399$1805_Y - connect \$1754 $and$libresoc.v:42400$1806_Y - connect \$1757 $ternary$libresoc.v:42401$1807_Y - connect \$1759 $and$libresoc.v:42402$1808_Y - connect \$1762 $and$libresoc.v:42403$1809_Y - connect \$1765 $not$libresoc.v:42404$1810_Y - connect \$1767 $and$libresoc.v:42405$1811_Y - connect \$1770 $and$libresoc.v:42406$1812_Y - connect \$1773 $ternary$libresoc.v:42407$1813_Y - connect \$1775 $or$libresoc.v:42408$1814_Y - connect \$1778 $or$libresoc.v:42409$1815_Y - connect \$1777 $pos$libresoc.v:42410$1817_Y - connect \$1781 $and$libresoc.v:42411$1818_Y - connect \$1783 $and$libresoc.v:42412$1819_Y - connect \$1786 $and$libresoc.v:42413$1820_Y - connect \$1789 $not$libresoc.v:42414$1821_Y - connect \$1791 $and$libresoc.v:42415$1822_Y - connect \$1794 $and$libresoc.v:42416$1823_Y - connect \$1797 $ternary$libresoc.v:42417$1824_Y - connect \$1799 $pos$libresoc.v:42418$1826_Y - connect \$1801 $and$libresoc.v:42419$1827_Y - connect \$1803 $and$libresoc.v:42420$1828_Y - connect \$1806 $and$libresoc.v:42421$1829_Y - connect \$1809 $not$libresoc.v:42422$1830_Y - connect \$1811 $and$libresoc.v:42423$1831_Y - connect \$1814 $and$libresoc.v:42424$1832_Y - connect \$1817 $ternary$libresoc.v:42425$1833_Y - connect \$182 $and$libresoc.v:42426$1834_Y - connect \$181 $reduce_or$libresoc.v:42427$1835_Y - connect \$186 $and$libresoc.v:42428$1836_Y - connect \$185 $reduce_or$libresoc.v:42429$1837_Y - connect \$190 $and$libresoc.v:42430$1838_Y - connect \$189 $reduce_or$libresoc.v:42431$1839_Y - connect \$194 $and$libresoc.v:42432$1840_Y - connect \$193 $reduce_or$libresoc.v:42433$1841_Y - connect \$198 $and$libresoc.v:42434$1842_Y - connect \$197 $reduce_or$libresoc.v:42435$1843_Y - connect \$202 $and$libresoc.v:42436$1844_Y - connect \$201 $reduce_or$libresoc.v:42437$1845_Y - connect \$206 $and$libresoc.v:42438$1846_Y - connect \$205 $reduce_or$libresoc.v:42439$1847_Y - connect \$210 $and$libresoc.v:42440$1848_Y - connect \$209 $reduce_or$libresoc.v:42441$1849_Y - connect \$214 $and$libresoc.v:42442$1850_Y - connect \$213 $reduce_or$libresoc.v:42443$1851_Y - connect \$218 $and$libresoc.v:42444$1852_Y - connect \$217 $reduce_or$libresoc.v:42445$1853_Y - connect \$221 $ne$libresoc.v:42446$1854_Y - connect \$224 $sub$libresoc.v:42447$1855_Y - connect \$226 $ne$libresoc.v:42448$1856_Y - connect \$229 $and$libresoc.v:42449$1857_Y - connect \$231 $and$libresoc.v:42450$1858_Y - connect \$233 $eq$libresoc.v:42451$1859_Y - connect \$235 $or$libresoc.v:42452$1860_Y - connect \$237 $and$libresoc.v:42453$1861_Y - connect \$239 $or$libresoc.v:42454$1862_Y - connect \$241 $eq$libresoc.v:42455$1863_Y - connect \$243 $and$libresoc.v:42456$1864_Y - connect \$245 $eq$libresoc.v:42457$1865_Y - connect \$247 $or$libresoc.v:42458$1866_Y - connect \$228 $not$libresoc.v:42459$1867_Y - connect \$250 $not$libresoc.v:42460$1868_Y - connect \$252 $not$libresoc.v:42461$1869_Y - connect \$254 $not$libresoc.v:42462$1870_Y - connect \$257 $and$libresoc.v:42463$1871_Y - connect \$259 $and$libresoc.v:42464$1872_Y - connect \$261 $eq$libresoc.v:42465$1873_Y - connect \$263 $or$libresoc.v:42466$1874_Y - connect \$265 $and$libresoc.v:42467$1875_Y - connect \$267 $or$libresoc.v:42468$1876_Y - connect \$256 $not$libresoc.v:42469$1877_Y - connect \$271 $and$libresoc.v:42470$1878_Y - connect \$273 $and$libresoc.v:42471$1879_Y - connect \$275 $eq$libresoc.v:42472$1880_Y - connect \$277 $or$libresoc.v:42473$1881_Y - connect \$279 $and$libresoc.v:42474$1882_Y - connect \$281 $or$libresoc.v:42475$1883_Y - connect \$283 $and$libresoc.v:42476$1884_Y - connect \$285 $and$libresoc.v:42477$1885_Y - connect \$287 $eq$libresoc.v:42478$1886_Y - connect \$289 $or$libresoc.v:42479$1887_Y - connect \$291 $eq$libresoc.v:42480$1888_Y - connect \$293 $and$libresoc.v:42481$1889_Y - connect \$295 $eq$libresoc.v:42482$1890_Y - connect \$297 $or$libresoc.v:42483$1891_Y - connect \$270 $not$libresoc.v:42484$1892_Y - connect \$301 $and$libresoc.v:42485$1893_Y - connect \$303 $and$libresoc.v:42486$1894_Y - connect \$305 $eq$libresoc.v:42487$1895_Y - connect \$307 $or$libresoc.v:42488$1896_Y - connect \$309 $and$libresoc.v:42489$1897_Y - connect \$311 $or$libresoc.v:42490$1898_Y - connect \$300 $not$libresoc.v:42491$1899_Y - connect \$315 $and$libresoc.v:42492$1900_Y - connect \$317 $and$libresoc.v:42493$1901_Y - connect \$319 $eq$libresoc.v:42494$1902_Y - connect \$321 $or$libresoc.v:42495$1903_Y - connect \$323 $and$libresoc.v:42496$1904_Y - connect \$325 $or$libresoc.v:42497$1905_Y - connect \$314 $not$libresoc.v:42498$1906_Y - connect \$329 $and$libresoc.v:42499$1907_Y - connect \$331 $and$libresoc.v:42500$1908_Y - connect \$333 $eq$libresoc.v:42501$1909_Y - connect \$335 $or$libresoc.v:42502$1910_Y - connect \$337 $and$libresoc.v:42503$1911_Y - connect \$339 $or$libresoc.v:42504$1912_Y - connect \$341 $eq$libresoc.v:42505$1913_Y - connect \$343 $and$libresoc.v:42506$1914_Y - connect \$345 $eq$libresoc.v:42507$1915_Y - connect \$347 $or$libresoc.v:42508$1916_Y - connect \$328 $not$libresoc.v:42509$1917_Y - connect \$350 $not$libresoc.v:42510$1918_Y - connect \$352 $and$libresoc.v:42511$1919_Y - connect \$354 $and$libresoc.v:42512$1920_Y - connect \$356 $not$libresoc.v:42513$1921_Y - connect \$358 $and$libresoc.v:42514$1922_Y - connect \$360 $and$libresoc.v:42515$1923_Y - connect \$362 $ternary$libresoc.v:42516$1924_Y - connect \$364 $and$libresoc.v:42517$1925_Y - connect \$366 $and$libresoc.v:42518$1926_Y - connect \$368 $not$libresoc.v:42519$1927_Y - connect \$370 $and$libresoc.v:42520$1928_Y - connect \$372 $and$libresoc.v:42521$1929_Y - connect \$374 $ternary$libresoc.v:42522$1930_Y - connect \$376 $and$libresoc.v:42523$1931_Y - connect \$378 $and$libresoc.v:42524$1932_Y - connect \$380 $not$libresoc.v:42525$1933_Y - connect \$382 $and$libresoc.v:42526$1934_Y - connect \$384 $and$libresoc.v:42527$1935_Y - connect \$386 $ternary$libresoc.v:42528$1936_Y - connect \$388 $and$libresoc.v:42529$1937_Y - connect \$390 $and$libresoc.v:42530$1938_Y - connect \$392 $not$libresoc.v:42531$1939_Y - connect \$394 $and$libresoc.v:42532$1940_Y - connect \$396 $and$libresoc.v:42533$1941_Y - connect \$398 $ternary$libresoc.v:42534$1942_Y - connect \$400 $and$libresoc.v:42535$1943_Y - connect \$402 $and$libresoc.v:42536$1944_Y - connect \$404 $not$libresoc.v:42537$1945_Y - connect \$406 $and$libresoc.v:42538$1946_Y - connect \$408 $and$libresoc.v:42539$1947_Y - connect \$410 $ternary$libresoc.v:42540$1948_Y - connect \$412 $and$libresoc.v:42541$1949_Y - connect \$414 $and$libresoc.v:42542$1950_Y - connect \$416 $not$libresoc.v:42543$1951_Y - connect \$418 $and$libresoc.v:42544$1952_Y - connect \$420 $and$libresoc.v:42545$1953_Y - connect \$422 $ternary$libresoc.v:42546$1954_Y - connect \$424 $and$libresoc.v:42547$1955_Y - connect \$426 $and$libresoc.v:42548$1956_Y - connect \$428 $not$libresoc.v:42549$1957_Y - connect \$430 $and$libresoc.v:42550$1958_Y - connect \$432 $and$libresoc.v:42551$1959_Y - connect \$434 $ternary$libresoc.v:42552$1960_Y - connect \$436 $and$libresoc.v:42553$1961_Y - connect \$438 $and$libresoc.v:42554$1962_Y - connect \$440 $not$libresoc.v:42555$1963_Y - connect \$442 $and$libresoc.v:42556$1964_Y - connect \$444 $and$libresoc.v:42557$1965_Y - connect \$446 $ternary$libresoc.v:42558$1966_Y - connect \$448 $and$libresoc.v:42559$1967_Y - connect \$450 $and$libresoc.v:42560$1968_Y - connect \$452 $not$libresoc.v:42561$1969_Y - connect \$454 $and$libresoc.v:42562$1970_Y - connect \$456 $and$libresoc.v:42563$1971_Y - connect \$458 $ternary$libresoc.v:42564$1972_Y - connect \$461 $or$libresoc.v:42565$1973_Y - connect \$463 $or$libresoc.v:42566$1974_Y - connect \$465 $or$libresoc.v:42567$1975_Y - connect \$467 $or$libresoc.v:42568$1976_Y - connect \$469 $or$libresoc.v:42569$1977_Y - connect \$471 $or$libresoc.v:42570$1978_Y - connect \$473 $or$libresoc.v:42571$1979_Y - connect \$475 $or$libresoc.v:42572$1980_Y - connect \$477 $reduce_or$libresoc.v:42573$1981_Y - connect \$479 $and$libresoc.v:42574$1982_Y - connect \$481 $and$libresoc.v:42575$1983_Y - connect \$483 $not$libresoc.v:42576$1984_Y - connect \$485 $and$libresoc.v:42577$1985_Y - connect \$487 $and$libresoc.v:42578$1986_Y - connect \$489 $ternary$libresoc.v:42579$1987_Y - connect \$491 $and$libresoc.v:42580$1988_Y - connect \$493 $and$libresoc.v:42581$1989_Y - connect \$495 $not$libresoc.v:42582$1990_Y - connect \$497 $and$libresoc.v:42583$1991_Y - connect \$499 $and$libresoc.v:42584$1992_Y - connect \$501 $ternary$libresoc.v:42585$1993_Y - connect \$503 $and$libresoc.v:42586$1994_Y - connect \$505 $and$libresoc.v:42587$1995_Y - connect \$507 $not$libresoc.v:42588$1996_Y - connect \$509 $and$libresoc.v:42589$1997_Y - connect \$511 $and$libresoc.v:42590$1998_Y - connect \$513 $ternary$libresoc.v:42591$1999_Y - connect \$515 $and$libresoc.v:42592$2000_Y - connect \$517 $and$libresoc.v:42593$2001_Y - connect \$519 $not$libresoc.v:42594$2002_Y - connect \$521 $and$libresoc.v:42595$2003_Y - connect \$523 $and$libresoc.v:42596$2004_Y - connect \$525 $ternary$libresoc.v:42597$2005_Y - connect \$527 $and$libresoc.v:42598$2006_Y - connect \$529 $and$libresoc.v:42599$2007_Y - connect \$531 $not$libresoc.v:42600$2008_Y - connect \$533 $and$libresoc.v:42601$2009_Y - connect \$535 $and$libresoc.v:42602$2010_Y - connect \$537 $ternary$libresoc.v:42603$2011_Y - connect \$539 $and$libresoc.v:42604$2012_Y - connect \$541 $and$libresoc.v:42605$2013_Y - connect \$543 $not$libresoc.v:42606$2014_Y - connect \$545 $and$libresoc.v:42607$2015_Y - connect \$547 $and$libresoc.v:42608$2016_Y - connect \$549 $ternary$libresoc.v:42609$2017_Y - connect \$551 $and$libresoc.v:42610$2018_Y - connect \$553 $and$libresoc.v:42611$2019_Y - connect \$555 $not$libresoc.v:42612$2020_Y - connect \$557 $and$libresoc.v:42613$2021_Y - connect \$559 $and$libresoc.v:42614$2022_Y - connect \$561 $ternary$libresoc.v:42615$2023_Y - connect \$563 $and$libresoc.v:42616$2024_Y - connect \$565 $and$libresoc.v:42617$2025_Y - connect \$567 $not$libresoc.v:42618$2026_Y - connect \$569 $and$libresoc.v:42619$2027_Y - connect \$571 $and$libresoc.v:42620$2028_Y - connect \$573 $ternary$libresoc.v:42621$2029_Y - connect \$576 $or$libresoc.v:42622$2030_Y - connect \$578 $or$libresoc.v:42623$2031_Y - connect \$580 $or$libresoc.v:42624$2032_Y - connect \$582 $or$libresoc.v:42625$2033_Y - connect \$584 $or$libresoc.v:42626$2034_Y - connect \$586 $or$libresoc.v:42627$2035_Y - connect \$588 $or$libresoc.v:42628$2036_Y - connect \$590 $reduce_or$libresoc.v:42629$2037_Y - connect \$592 $and$libresoc.v:42630$2038_Y - connect \$594 $and$libresoc.v:42631$2039_Y - connect \$596 $not$libresoc.v:42632$2040_Y - connect \$598 $and$libresoc.v:42633$2041_Y - connect \$600 $and$libresoc.v:42634$2042_Y - connect \$602 $ternary$libresoc.v:42635$2043_Y - connect \$604 $and$libresoc.v:42636$2044_Y - connect \$606 $and$libresoc.v:42637$2045_Y - connect \$608 $not$libresoc.v:42638$2046_Y - connect \$610 $and$libresoc.v:42639$2047_Y - connect \$612 $and$libresoc.v:42640$2048_Y - connect \$614 $ternary$libresoc.v:42641$2049_Y - connect \$617 $or$libresoc.v:42642$2050_Y - connect \$619 $reduce_or$libresoc.v:42643$2051_Y - connect \$621 $and$libresoc.v:42644$2052_Y - connect \$623 $and$libresoc.v:42645$2053_Y - connect \$625 $eq$libresoc.v:42646$2054_Y - connect \$627 $or$libresoc.v:42647$2055_Y - connect \$629 $and$libresoc.v:42648$2056_Y - connect \$631 $or$libresoc.v:42649$2057_Y - connect \$633 $and$libresoc.v:42650$2058_Y - connect \$635 $and$libresoc.v:42651$2059_Y - connect \$637 $not$libresoc.v:42652$2060_Y - connect \$639 $and$libresoc.v:42653$2061_Y - connect \$641 $and$libresoc.v:42654$2062_Y - connect \$643 $ternary$libresoc.v:42655$2063_Y - connect \$645 $and$libresoc.v:42656$2064_Y - connect \$647 $and$libresoc.v:42657$2065_Y - connect \$649 $not$libresoc.v:42658$2066_Y - connect \$651 $and$libresoc.v:42659$2067_Y - connect \$653 $and$libresoc.v:42660$2068_Y - connect \$655 $ternary$libresoc.v:42661$2069_Y - connect \$657 $and$libresoc.v:42662$2070_Y - connect \$659 $and$libresoc.v:42663$2071_Y - connect \$661 $not$libresoc.v:42664$2072_Y - connect \$663 $and$libresoc.v:42665$2073_Y - connect \$665 $and$libresoc.v:42666$2074_Y - connect \$667 $ternary$libresoc.v:42667$2075_Y - connect \$669 $and$libresoc.v:42668$2076_Y - connect \$671 $and$libresoc.v:42669$2077_Y - connect \$673 $not$libresoc.v:42670$2078_Y - connect \$675 $and$libresoc.v:42671$2079_Y - connect \$677 $and$libresoc.v:42672$2080_Y - connect \$679 $ternary$libresoc.v:42673$2081_Y - connect \$681 $and$libresoc.v:42674$2082_Y - connect \$683 $and$libresoc.v:42675$2083_Y - connect \$685 $not$libresoc.v:42676$2084_Y - connect \$687 $and$libresoc.v:42677$2085_Y - connect \$689 $and$libresoc.v:42678$2086_Y - connect \$691 $ternary$libresoc.v:42679$2087_Y - connect \$693 $and$libresoc.v:42680$2088_Y - connect \$695 $and$libresoc.v:42681$2089_Y - connect \$697 $not$libresoc.v:42682$2090_Y - connect \$699 $and$libresoc.v:42683$2091_Y - connect \$701 $and$libresoc.v:42684$2092_Y - connect \$703 $ternary$libresoc.v:42685$2093_Y - connect \$706 $or$libresoc.v:42686$2094_Y - connect \$708 $or$libresoc.v:42687$2095_Y - connect \$710 $or$libresoc.v:42688$2096_Y - connect \$712 $or$libresoc.v:42689$2097_Y - connect \$714 $or$libresoc.v:42690$2098_Y - connect \$705 $pos$libresoc.v:42691$2100_Y - connect \$717 $eq$libresoc.v:42692$2101_Y - connect \$719 $and$libresoc.v:42693$2102_Y - connect \$721 $eq$libresoc.v:42694$2103_Y - connect \$723 $or$libresoc.v:42695$2104_Y - connect \$725 $and$libresoc.v:42696$2105_Y - connect \$727 $and$libresoc.v:42697$2106_Y - connect \$729 $not$libresoc.v:42698$2107_Y - connect \$731 $and$libresoc.v:42699$2108_Y - connect \$733 $and$libresoc.v:42700$2109_Y - connect \$735 $ternary$libresoc.v:42701$2110_Y - connect \$737 $and$libresoc.v:42702$2111_Y - connect \$739 $and$libresoc.v:42703$2112_Y - connect \$741 $not$libresoc.v:42704$2113_Y - connect \$743 $and$libresoc.v:42705$2114_Y - connect \$745 $and$libresoc.v:42706$2115_Y - connect \$747 $ternary$libresoc.v:42707$2116_Y - connect \$749 $and$libresoc.v:42708$2117_Y - connect \$751 $and$libresoc.v:42709$2118_Y - connect \$753 $not$libresoc.v:42710$2119_Y - connect \$755 $and$libresoc.v:42711$2120_Y - connect \$757 $and$libresoc.v:42712$2121_Y - connect \$759 $ternary$libresoc.v:42713$2122_Y - connect \$762 $or$libresoc.v:42714$2123_Y - connect \$764 $or$libresoc.v:42715$2124_Y - connect \$761 $pos$libresoc.v:42716$2126_Y - connect \$767 $and$libresoc.v:42717$2127_Y - connect \$769 $and$libresoc.v:42718$2128_Y - connect \$771 $eq$libresoc.v:42719$2129_Y - connect \$773 $or$libresoc.v:42720$2130_Y - connect \$775 $and$libresoc.v:42721$2131_Y - connect \$777 $and$libresoc.v:42722$2132_Y - connect \$779 $not$libresoc.v:42723$2133_Y - connect \$781 $and$libresoc.v:42724$2134_Y - connect \$783 $and$libresoc.v:42725$2135_Y - connect \$785 $ternary$libresoc.v:42726$2136_Y - connect \$787 $and$libresoc.v:42727$2137_Y - connect \$789 $and$libresoc.v:42728$2138_Y - connect \$791 $not$libresoc.v:42729$2139_Y - connect \$793 $and$libresoc.v:42730$2140_Y - connect \$795 $and$libresoc.v:42731$2141_Y - connect \$797 $ternary$libresoc.v:42732$2142_Y - connect \$799 $and$libresoc.v:42733$2143_Y - connect \$801 $and$libresoc.v:42734$2144_Y - connect \$803 $not$libresoc.v:42735$2145_Y - connect \$805 $and$libresoc.v:42736$2146_Y - connect \$807 $and$libresoc.v:42737$2147_Y - connect \$809 $sub$libresoc.v:42738$2148_Y - connect \$811 $sshl$libresoc.v:42739$2149_Y - connect \$813 $ternary$libresoc.v:42740$2150_Y - connect \$815 $and$libresoc.v:42741$2151_Y - connect \$817 $and$libresoc.v:42742$2152_Y - connect \$819 $not$libresoc.v:42743$2153_Y - connect \$821 $and$libresoc.v:42744$2154_Y - connect \$823 $and$libresoc.v:42745$2155_Y - connect \$825 $sub$libresoc.v:42746$2156_Y - connect \$827 $sshl$libresoc.v:42747$2157_Y - connect \$829 $ternary$libresoc.v:42748$2158_Y - connect \$832 $or$libresoc.v:42749$2159_Y - connect \$834 $and$libresoc.v:42750$2160_Y - connect \$836 $and$libresoc.v:42751$2161_Y - connect \$838 $not$libresoc.v:42752$2162_Y - connect \$840 $and$libresoc.v:42753$2163_Y - connect \$842 $and$libresoc.v:42754$2164_Y - connect \$844 $sub$libresoc.v:42755$2165_Y - connect \$846 $sshl$libresoc.v:42756$2166_Y - connect \$848 $ternary$libresoc.v:42757$2167_Y - connect \$850 $and$libresoc.v:42758$2168_Y - connect \$852 $and$libresoc.v:42759$2169_Y - connect \$854 $not$libresoc.v:42760$2170_Y - connect \$856 $and$libresoc.v:42761$2171_Y - connect \$858 $and$libresoc.v:42762$2172_Y - connect \$860 $sub$libresoc.v:42763$2173_Y - connect \$862 $sshl$libresoc.v:42764$2174_Y - connect \$864 $ternary$libresoc.v:42765$2175_Y - connect \$866 $and$libresoc.v:42766$2176_Y - connect \$868 $and$libresoc.v:42767$2177_Y - connect \$870 $not$libresoc.v:42768$2178_Y - connect \$872 $and$libresoc.v:42769$2179_Y - connect \$874 $and$libresoc.v:42770$2180_Y - connect \$876 $ternary$libresoc.v:42771$2181_Y - connect \$878 $and$libresoc.v:42772$2182_Y - connect \$880 $and$libresoc.v:42773$2183_Y - connect \$882 $not$libresoc.v:42774$2184_Y - connect \$884 $and$libresoc.v:42775$2185_Y - connect \$886 $and$libresoc.v:42776$2186_Y - connect \$888 $ternary$libresoc.v:42777$2187_Y - connect \$890 $and$libresoc.v:42778$2188_Y - connect \$892 $and$libresoc.v:42779$2189_Y - connect \$894 $not$libresoc.v:42780$2190_Y - connect \$896 $and$libresoc.v:42781$2191_Y - connect \$898 $and$libresoc.v:42782$2192_Y - connect \$900 $ternary$libresoc.v:42783$2193_Y - connect \$902 $or$libresoc.v:42784$2194_Y - connect \$904 $or$libresoc.v:42785$2195_Y - connect \$906 $reduce_or$libresoc.v:42786$2196_Y - connect \$908 $and$libresoc.v:42787$2197_Y - connect \$910 $and$libresoc.v:42788$2198_Y - connect \$912 $not$libresoc.v:42789$2199_Y - connect \$914 $and$libresoc.v:42790$2200_Y - connect \$916 $and$libresoc.v:42791$2201_Y - connect \$918 $ternary$libresoc.v:42792$2202_Y - connect \$920 $and$libresoc.v:42793$2203_Y - connect \$922 $and$libresoc.v:42794$2204_Y - connect \$924 $not$libresoc.v:42795$2205_Y - connect \$926 $and$libresoc.v:42796$2206_Y - connect \$928 $and$libresoc.v:42797$2207_Y - connect \$930 $ternary$libresoc.v:42798$2208_Y - connect \$932 $or$libresoc.v:42799$2209_Y - connect \$934 $reduce_or$libresoc.v:42800$2210_Y - connect \$936 $and$libresoc.v:42801$2211_Y - connect \$938 $and$libresoc.v:42802$2212_Y - connect \$940 $not$libresoc.v:42803$2213_Y - connect \$942 $and$libresoc.v:42804$2214_Y - connect \$944 $and$libresoc.v:42805$2215_Y - connect \$946 $ternary$libresoc.v:42806$2216_Y - connect \$948 $reduce_or$libresoc.v:42807$2217_Y - connect \$950 $and$libresoc.v:42808$2218_Y - connect \$952 $and$libresoc.v:42809$2219_Y - connect \$954 $and$libresoc.v:42810$2220_Y - connect \$956 $and$libresoc.v:42811$2221_Y - connect \$958 $and$libresoc.v:42812$2222_Y - connect \$960 $and$libresoc.v:42813$2223_Y - connect \$962 $and$libresoc.v:42814$2224_Y - connect \$964 $and$libresoc.v:42815$2225_Y - connect \$966 $and$libresoc.v:42816$2226_Y - connect \$968 $and$libresoc.v:42817$2227_Y - connect \$970 $and$libresoc.v:42818$2228_Y - connect \$972 $and$libresoc.v:42819$2229_Y - connect \$974 $not$libresoc.v:42820$2230_Y - connect \$976 $and$libresoc.v:42821$2231_Y - connect \$982 $and$libresoc.v:42822$2232_Y - connect \$984 $ternary$libresoc.v:42823$2233_Y - connect \$986 $and$libresoc.v:42824$2234_Y - connect \$989 $and$libresoc.v:42825$2235_Y - connect \$993 $not$libresoc.v:42826$2236_Y - connect \$995 $and$libresoc.v:42827$2237_Y + connect \$1000 $and$libresoc.v:42151$1506_Y + connect \$1003 $ternary$libresoc.v:42152$1507_Y + connect \$1005 $and$libresoc.v:42153$1508_Y + connect \$1008 $and$libresoc.v:42154$1509_Y + connect \$1012 $not$libresoc.v:42155$1510_Y + connect \$1014 $and$libresoc.v:42156$1511_Y + connect \$1021 $and$libresoc.v:42157$1512_Y + connect \$1024 $ternary$libresoc.v:42158$1513_Y + connect \$1026 $and$libresoc.v:42159$1514_Y + connect \$1029 $and$libresoc.v:42160$1515_Y + connect \$1033 $not$libresoc.v:42161$1516_Y + connect \$1035 $and$libresoc.v:42162$1517_Y + connect \$1039 $and$libresoc.v:42163$1518_Y + connect \$1042 $ternary$libresoc.v:42164$1519_Y + connect \$1044 $and$libresoc.v:42165$1520_Y + connect \$1047 $and$libresoc.v:42166$1521_Y + connect \$1051 $not$libresoc.v:42167$1522_Y + connect \$1053 $and$libresoc.v:42168$1523_Y + connect \$1061 $and$libresoc.v:42169$1524_Y + connect \$1064 $ternary$libresoc.v:42170$1525_Y + connect \$1066 $and$libresoc.v:42171$1526_Y + connect \$1069 $and$libresoc.v:42172$1527_Y + connect \$1073 $not$libresoc.v:42173$1528_Y + connect \$1075 $and$libresoc.v:42174$1529_Y + connect \$1081 $and$libresoc.v:42175$1530_Y + connect \$1084 $ternary$libresoc.v:42176$1531_Y + connect \$1086 $and$libresoc.v:42177$1532_Y + connect \$1089 $and$libresoc.v:42178$1533_Y + connect \$1093 $not$libresoc.v:42179$1534_Y + connect \$1095 $and$libresoc.v:42180$1535_Y + connect \$1101 $and$libresoc.v:42181$1536_Y + connect \$1104 $ternary$libresoc.v:42182$1537_Y + connect \$1106 $and$libresoc.v:42183$1538_Y + connect \$1109 $and$libresoc.v:42184$1539_Y + connect \$1113 $not$libresoc.v:42185$1540_Y + connect \$1115 $and$libresoc.v:42186$1541_Y + connect \$1120 $and$libresoc.v:42187$1542_Y + connect \$1123 $ternary$libresoc.v:42188$1543_Y + connect \$1125 $and$libresoc.v:42189$1544_Y + connect \$1128 $and$libresoc.v:42190$1545_Y + connect \$1132 $not$libresoc.v:42191$1546_Y + connect \$1134 $and$libresoc.v:42192$1547_Y + connect \$1138 $and$libresoc.v:42193$1548_Y + connect \$1141 $ternary$libresoc.v:42194$1549_Y + connect \$1143 $and$libresoc.v:42195$1550_Y + connect \$1146 $and$libresoc.v:42196$1551_Y + connect \$1149 $not$libresoc.v:42197$1552_Y + connect \$1151 $and$libresoc.v:42198$1553_Y + connect \$1154 $and$libresoc.v:42199$1554_Y + connect \$1157 $ternary$libresoc.v:42200$1555_Y + connect \$1160 $or$libresoc.v:42201$1556_Y + connect \$1162 $or$libresoc.v:42202$1557_Y + connect \$1164 $or$libresoc.v:42203$1558_Y + connect \$1166 $or$libresoc.v:42204$1559_Y + connect \$1168 $or$libresoc.v:42205$1560_Y + connect \$1170 $or$libresoc.v:42206$1561_Y + connect \$1172 $or$libresoc.v:42207$1562_Y + connect \$1174 $or$libresoc.v:42208$1563_Y + connect \$1176 $or$libresoc.v:42209$1564_Y + connect \$1179 $or$libresoc.v:42210$1565_Y + connect \$1181 $or$libresoc.v:42211$1566_Y + connect \$1183 $or$libresoc.v:42212$1567_Y + connect \$1185 $or$libresoc.v:42213$1568_Y + connect \$1187 $or$libresoc.v:42214$1569_Y + connect \$1189 $or$libresoc.v:42215$1570_Y + connect \$1191 $or$libresoc.v:42216$1571_Y + connect \$1193 $or$libresoc.v:42217$1572_Y + connect \$1195 $or$libresoc.v:42218$1573_Y + connect \$1197 $or$libresoc.v:42219$1574_Y + connect \$1199 $or$libresoc.v:42220$1575_Y + connect \$1201 $or$libresoc.v:42221$1576_Y + connect \$1203 $or$libresoc.v:42222$1577_Y + connect \$1205 $or$libresoc.v:42223$1578_Y + connect \$1207 $or$libresoc.v:42224$1579_Y + connect \$1209 $or$libresoc.v:42225$1580_Y + connect \$1211 $or$libresoc.v:42226$1581_Y + connect \$1213 $or$libresoc.v:42227$1582_Y + connect \$1215 $and$libresoc.v:42228$1583_Y + connect \$1217 $and$libresoc.v:42229$1584_Y + connect \$1220 $and$libresoc.v:42230$1585_Y + connect \$1223 $not$libresoc.v:42231$1586_Y + connect \$1225 $and$libresoc.v:42232$1587_Y + connect \$1228 $and$libresoc.v:42233$1588_Y + connect \$1231 $ternary$libresoc.v:42234$1589_Y + connect \$1233 $and$libresoc.v:42235$1590_Y + connect \$1235 $and$libresoc.v:42236$1591_Y + connect \$1237 $and$libresoc.v:42237$1592_Y + connect \$1239 $and$libresoc.v:42238$1593_Y + connect \$1241 $and$libresoc.v:42239$1594_Y + connect \$1243 $and$libresoc.v:42240$1595_Y + connect \$1245 $and$libresoc.v:42241$1596_Y + connect \$1248 $and$libresoc.v:42242$1597_Y + connect \$1251 $not$libresoc.v:42243$1598_Y + connect \$1253 $and$libresoc.v:42244$1599_Y + connect \$1256 $and$libresoc.v:42245$1600_Y + connect \$1259 $sub$libresoc.v:42246$1601_Y + connect \$1261 $sshl$libresoc.v:42247$1602_Y + connect \$1263 $ternary$libresoc.v:42248$1603_Y + connect \$1265 $and$libresoc.v:42249$1604_Y + connect \$1268 $and$libresoc.v:42250$1605_Y + connect \$1271 $not$libresoc.v:42251$1606_Y + connect \$1273 $and$libresoc.v:42252$1607_Y + connect \$1276 $and$libresoc.v:42253$1608_Y + connect \$1279 $sub$libresoc.v:42254$1609_Y + connect \$1281 $sshl$libresoc.v:42255$1610_Y + connect \$1283 $ternary$libresoc.v:42256$1611_Y + connect \$1285 $and$libresoc.v:42257$1612_Y + connect \$1288 $and$libresoc.v:42258$1613_Y + connect \$1291 $not$libresoc.v:42259$1614_Y + connect \$1293 $and$libresoc.v:42260$1615_Y + connect \$1296 $and$libresoc.v:42261$1616_Y + connect \$1299 $sub$libresoc.v:42262$1617_Y + connect \$1301 $sshl$libresoc.v:42263$1618_Y + connect \$1303 $ternary$libresoc.v:42264$1619_Y + connect \$1305 $and$libresoc.v:42265$1620_Y + connect \$1308 $and$libresoc.v:42266$1621_Y + connect \$1311 $not$libresoc.v:42267$1622_Y + connect \$1313 $and$libresoc.v:42268$1623_Y + connect \$1316 $and$libresoc.v:42269$1624_Y + connect \$1319 $sub$libresoc.v:42270$1625_Y + connect \$1321 $sshl$libresoc.v:42271$1626_Y + connect \$1323 $ternary$libresoc.v:42272$1627_Y + connect \$1325 $and$libresoc.v:42273$1628_Y + connect \$1328 $and$libresoc.v:42274$1629_Y + connect \$1331 $not$libresoc.v:42275$1630_Y + connect \$1333 $and$libresoc.v:42276$1631_Y + connect \$1336 $and$libresoc.v:42277$1632_Y + connect \$1339 $sub$libresoc.v:42278$1633_Y + connect \$1341 $sshl$libresoc.v:42279$1634_Y + connect \$1343 $ternary$libresoc.v:42280$1635_Y + connect \$1345 $and$libresoc.v:42281$1636_Y + connect \$1348 $and$libresoc.v:42282$1637_Y + connect \$1351 $not$libresoc.v:42283$1638_Y + connect \$1353 $and$libresoc.v:42284$1639_Y + connect \$1356 $and$libresoc.v:42285$1640_Y + connect \$1359 $sub$libresoc.v:42286$1641_Y + connect \$1361 $sshl$libresoc.v:42287$1642_Y + connect \$1363 $ternary$libresoc.v:42288$1643_Y + connect \$1365 $or$libresoc.v:42289$1644_Y + connect \$1367 $or$libresoc.v:42290$1645_Y + connect \$1369 $or$libresoc.v:42291$1646_Y + connect \$1371 $or$libresoc.v:42292$1647_Y + connect \$1373 $or$libresoc.v:42293$1648_Y + connect \$1376 $or$libresoc.v:42294$1649_Y + connect \$1378 $or$libresoc.v:42295$1650_Y + connect \$1380 $or$libresoc.v:42296$1651_Y + connect \$1382 $or$libresoc.v:42297$1652_Y + connect \$1384 $or$libresoc.v:42298$1653_Y + connect \$1386 $and$libresoc.v:42299$1654_Y + connect \$1388 $and$libresoc.v:42300$1655_Y + connect \$1390 $and$libresoc.v:42301$1656_Y + connect \$1392 $and$libresoc.v:42302$1657_Y + connect \$1395 $and$libresoc.v:42303$1658_Y + connect \$1398 $not$libresoc.v:42304$1659_Y + connect \$1400 $and$libresoc.v:42305$1660_Y + connect \$1403 $and$libresoc.v:42306$1661_Y + connect \$1406 $ternary$libresoc.v:42307$1662_Y + connect \$1408 $and$libresoc.v:42308$1663_Y + connect \$1411 $and$libresoc.v:42309$1664_Y + connect \$1414 $not$libresoc.v:42310$1665_Y + connect \$1416 $and$libresoc.v:42311$1666_Y + connect \$1419 $and$libresoc.v:42312$1667_Y + connect \$1422 $ternary$libresoc.v:42313$1668_Y + connect \$1424 $and$libresoc.v:42314$1669_Y + connect \$1427 $and$libresoc.v:42315$1670_Y + connect \$1430 $not$libresoc.v:42316$1671_Y + connect \$1432 $and$libresoc.v:42317$1672_Y + connect \$1435 $and$libresoc.v:42318$1673_Y + connect \$1438 $ternary$libresoc.v:42319$1674_Y + connect \$1440 $or$libresoc.v:42320$1675_Y + connect \$1442 $or$libresoc.v:42321$1676_Y + connect \$1445 $or$libresoc.v:42322$1677_Y + connect \$1447 $or$libresoc.v:42323$1678_Y + connect \$1444 $pos$libresoc.v:42324$1680_Y + connect \$1450 $and$libresoc.v:42325$1681_Y + connect \$1452 $and$libresoc.v:42326$1682_Y + connect \$1454 $and$libresoc.v:42327$1683_Y + connect \$1456 $and$libresoc.v:42328$1684_Y + connect \$1458 $and$libresoc.v:42329$1685_Y + connect \$1461 $and$libresoc.v:42330$1686_Y + connect \$1464 $not$libresoc.v:42331$1687_Y + connect \$1466 $and$libresoc.v:42332$1688_Y + connect \$1469 $and$libresoc.v:42333$1689_Y + connect \$1472 $ternary$libresoc.v:42334$1690_Y + connect \$1474 $and$libresoc.v:42335$1691_Y + connect \$1477 $and$libresoc.v:42336$1692_Y + connect \$1480 $not$libresoc.v:42337$1693_Y + connect \$1482 $and$libresoc.v:42338$1694_Y + connect \$1485 $and$libresoc.v:42339$1695_Y + connect \$1488 $ternary$libresoc.v:42340$1696_Y + connect \$1490 $and$libresoc.v:42341$1697_Y + connect \$1493 $and$libresoc.v:42342$1698_Y + connect \$1496 $not$libresoc.v:42343$1699_Y + connect \$1498 $and$libresoc.v:42344$1700_Y + connect \$1501 $and$libresoc.v:42345$1701_Y + connect \$1504 $ternary$libresoc.v:42346$1702_Y + connect \$1506 $and$libresoc.v:42347$1703_Y + connect \$1509 $and$libresoc.v:42348$1704_Y + connect \$1512 $not$libresoc.v:42349$1705_Y + connect \$1514 $and$libresoc.v:42350$1706_Y + connect \$1517 $and$libresoc.v:42351$1707_Y + connect \$1520 $ternary$libresoc.v:42352$1708_Y + connect \$1522 $or$libresoc.v:42353$1709_Y + connect \$1524 $or$libresoc.v:42354$1710_Y + connect \$1526 $or$libresoc.v:42355$1711_Y + connect \$1528 $or$libresoc.v:42356$1712_Y + connect \$1530 $or$libresoc.v:42357$1713_Y + connect \$1532 $or$libresoc.v:42358$1714_Y + connect \$1534 $and$libresoc.v:42359$1715_Y + connect \$1536 $and$libresoc.v:42360$1716_Y + connect \$1538 $and$libresoc.v:42361$1717_Y + connect \$1540 $and$libresoc.v:42362$1718_Y + connect \$1542 $and$libresoc.v:42363$1719_Y + connect \$1545 $and$libresoc.v:42364$1720_Y + connect \$1548 $not$libresoc.v:42365$1721_Y + connect \$1550 $and$libresoc.v:42366$1722_Y + connect \$1553 $and$libresoc.v:42367$1723_Y + connect \$1556 $ternary$libresoc.v:42368$1724_Y + connect \$1558 $and$libresoc.v:42369$1725_Y + connect \$1561 $and$libresoc.v:42370$1726_Y + connect \$1564 $not$libresoc.v:42371$1727_Y + connect \$1566 $and$libresoc.v:42372$1728_Y + connect \$1569 $and$libresoc.v:42373$1729_Y + connect \$1572 $ternary$libresoc.v:42374$1730_Y + connect \$1574 $and$libresoc.v:42375$1731_Y + connect \$1577 $and$libresoc.v:42376$1732_Y + connect \$1580 $not$libresoc.v:42377$1733_Y + connect \$1582 $and$libresoc.v:42378$1734_Y + connect \$1585 $and$libresoc.v:42379$1735_Y + connect \$1588 $ternary$libresoc.v:42380$1736_Y + connect \$1590 $and$libresoc.v:42381$1737_Y + connect \$1593 $and$libresoc.v:42382$1738_Y + connect \$1596 $not$libresoc.v:42383$1739_Y + connect \$1598 $and$libresoc.v:42384$1740_Y + connect \$1601 $and$libresoc.v:42385$1741_Y + connect \$1604 $ternary$libresoc.v:42386$1742_Y + connect \$1607 $or$libresoc.v:42387$1743_Y + connect \$1609 $or$libresoc.v:42388$1744_Y + connect \$1611 $or$libresoc.v:42389$1745_Y + connect \$1606 $pos$libresoc.v:42390$1747_Y + connect \$1615 $or$libresoc.v:42391$1748_Y + connect \$1617 $or$libresoc.v:42392$1749_Y + connect \$1619 $or$libresoc.v:42393$1750_Y + connect \$1614 $pos$libresoc.v:42394$1752_Y + connect \$1622 $and$libresoc.v:42395$1753_Y + connect \$1624 $and$libresoc.v:42396$1754_Y + connect \$1626 $and$libresoc.v:42397$1755_Y + connect \$1628 $and$libresoc.v:42398$1756_Y + connect \$1630 $and$libresoc.v:42399$1757_Y + connect \$1632 $and$libresoc.v:42400$1758_Y + connect \$1635 $and$libresoc.v:42401$1759_Y + connect \$1639 $not$libresoc.v:42402$1760_Y + connect \$1641 $and$libresoc.v:42403$1761_Y + connect \$1646 $and$libresoc.v:42404$1762_Y + connect \$1649 $ternary$libresoc.v:42405$1763_Y + connect \$1651 $and$libresoc.v:42406$1764_Y + connect \$1654 $and$libresoc.v:42407$1765_Y + connect \$1657 $not$libresoc.v:42408$1766_Y + connect \$1659 $and$libresoc.v:42409$1767_Y + connect \$1662 $and$libresoc.v:42410$1768_Y + connect \$1665 $ternary$libresoc.v:42411$1769_Y + connect \$1667 $and$libresoc.v:42412$1770_Y + connect \$1670 $and$libresoc.v:42413$1771_Y + connect \$1673 $not$libresoc.v:42414$1772_Y + connect \$1675 $and$libresoc.v:42415$1773_Y + connect \$1678 $and$libresoc.v:42416$1774_Y + connect \$1681 $ternary$libresoc.v:42417$1775_Y + connect \$1683 $and$libresoc.v:42418$1776_Y + connect \$1686 $and$libresoc.v:42419$1777_Y + connect \$1689 $not$libresoc.v:42420$1778_Y + connect \$1691 $and$libresoc.v:42421$1779_Y + connect \$1694 $and$libresoc.v:42422$1780_Y + connect \$1697 $ternary$libresoc.v:42423$1781_Y + connect \$1699 $and$libresoc.v:42424$1782_Y + connect \$1702 $and$libresoc.v:42425$1783_Y + connect \$1705 $not$libresoc.v:42426$1784_Y + connect \$1707 $and$libresoc.v:42427$1785_Y + connect \$1710 $and$libresoc.v:42428$1786_Y + connect \$1713 $ternary$libresoc.v:42429$1787_Y + connect \$1715 $or$libresoc.v:42430$1788_Y + connect \$1717 $or$libresoc.v:42431$1789_Y + connect \$1719 $or$libresoc.v:42432$1790_Y + connect \$1721 $or$libresoc.v:42433$1791_Y + connect \$1723 $or$libresoc.v:42434$1792_Y + connect \$1725 $or$libresoc.v:42435$1793_Y + connect \$1727 $or$libresoc.v:42436$1794_Y + connect \$1729 $or$libresoc.v:42437$1795_Y + connect \$1731 $or$libresoc.v:42438$1796_Y + connect \$1733 $or$libresoc.v:42439$1797_Y + connect \$1735 $or$libresoc.v:42440$1798_Y + connect \$1737 $or$libresoc.v:42441$1799_Y + connect \$1739 $and$libresoc.v:42442$1800_Y + connect \$1741 $and$libresoc.v:42443$1801_Y + connect \$1743 $and$libresoc.v:42444$1802_Y + connect \$1746 $and$libresoc.v:42445$1803_Y + connect \$1749 $not$libresoc.v:42446$1804_Y + connect \$1751 $and$libresoc.v:42447$1805_Y + connect \$1754 $and$libresoc.v:42448$1806_Y + connect \$1757 $ternary$libresoc.v:42449$1807_Y + connect \$1759 $and$libresoc.v:42450$1808_Y + connect \$1762 $and$libresoc.v:42451$1809_Y + connect \$1765 $not$libresoc.v:42452$1810_Y + connect \$1767 $and$libresoc.v:42453$1811_Y + connect \$1770 $and$libresoc.v:42454$1812_Y + connect \$1773 $ternary$libresoc.v:42455$1813_Y + connect \$1775 $or$libresoc.v:42456$1814_Y + connect \$1778 $or$libresoc.v:42457$1815_Y + connect \$1777 $pos$libresoc.v:42458$1817_Y + connect \$1781 $and$libresoc.v:42459$1818_Y + connect \$1783 $and$libresoc.v:42460$1819_Y + connect \$1786 $and$libresoc.v:42461$1820_Y + connect \$1789 $not$libresoc.v:42462$1821_Y + connect \$1791 $and$libresoc.v:42463$1822_Y + connect \$1794 $and$libresoc.v:42464$1823_Y + connect \$1797 $ternary$libresoc.v:42465$1824_Y + connect \$1799 $pos$libresoc.v:42466$1826_Y + connect \$1801 $and$libresoc.v:42467$1827_Y + connect \$1803 $and$libresoc.v:42468$1828_Y + connect \$1806 $and$libresoc.v:42469$1829_Y + connect \$1809 $not$libresoc.v:42470$1830_Y + connect \$1811 $and$libresoc.v:42471$1831_Y + connect \$1814 $and$libresoc.v:42472$1832_Y + connect \$1817 $ternary$libresoc.v:42473$1833_Y + connect \$182 $and$libresoc.v:42474$1834_Y + connect \$181 $reduce_or$libresoc.v:42475$1835_Y + connect \$186 $and$libresoc.v:42476$1836_Y + connect \$185 $reduce_or$libresoc.v:42477$1837_Y + connect \$190 $and$libresoc.v:42478$1838_Y + connect \$189 $reduce_or$libresoc.v:42479$1839_Y + connect \$194 $and$libresoc.v:42480$1840_Y + connect \$193 $reduce_or$libresoc.v:42481$1841_Y + connect \$198 $and$libresoc.v:42482$1842_Y + connect \$197 $reduce_or$libresoc.v:42483$1843_Y + connect \$202 $and$libresoc.v:42484$1844_Y + connect \$201 $reduce_or$libresoc.v:42485$1845_Y + connect \$206 $and$libresoc.v:42486$1846_Y + connect \$205 $reduce_or$libresoc.v:42487$1847_Y + connect \$210 $and$libresoc.v:42488$1848_Y + connect \$209 $reduce_or$libresoc.v:42489$1849_Y + connect \$214 $and$libresoc.v:42490$1850_Y + connect \$213 $reduce_or$libresoc.v:42491$1851_Y + connect \$218 $and$libresoc.v:42492$1852_Y + connect \$217 $reduce_or$libresoc.v:42493$1853_Y + connect \$221 $ne$libresoc.v:42494$1854_Y + connect \$224 $sub$libresoc.v:42495$1855_Y + connect \$226 $ne$libresoc.v:42496$1856_Y + connect \$229 $and$libresoc.v:42497$1857_Y + connect \$231 $and$libresoc.v:42498$1858_Y + connect \$233 $eq$libresoc.v:42499$1859_Y + connect \$235 $or$libresoc.v:42500$1860_Y + connect \$237 $and$libresoc.v:42501$1861_Y + connect \$239 $or$libresoc.v:42502$1862_Y + connect \$241 $eq$libresoc.v:42503$1863_Y + connect \$243 $and$libresoc.v:42504$1864_Y + connect \$245 $eq$libresoc.v:42505$1865_Y + connect \$247 $or$libresoc.v:42506$1866_Y + connect \$228 $not$libresoc.v:42507$1867_Y + connect \$250 $not$libresoc.v:42508$1868_Y + connect \$252 $not$libresoc.v:42509$1869_Y + connect \$254 $not$libresoc.v:42510$1870_Y + connect \$257 $and$libresoc.v:42511$1871_Y + connect \$259 $and$libresoc.v:42512$1872_Y + connect \$261 $eq$libresoc.v:42513$1873_Y + connect \$263 $or$libresoc.v:42514$1874_Y + connect \$265 $and$libresoc.v:42515$1875_Y + connect \$267 $or$libresoc.v:42516$1876_Y + connect \$256 $not$libresoc.v:42517$1877_Y + connect \$271 $and$libresoc.v:42518$1878_Y + connect \$273 $and$libresoc.v:42519$1879_Y + connect \$275 $eq$libresoc.v:42520$1880_Y + connect \$277 $or$libresoc.v:42521$1881_Y + connect \$279 $and$libresoc.v:42522$1882_Y + connect \$281 $or$libresoc.v:42523$1883_Y + connect \$283 $and$libresoc.v:42524$1884_Y + connect \$285 $and$libresoc.v:42525$1885_Y + connect \$287 $eq$libresoc.v:42526$1886_Y + connect \$289 $or$libresoc.v:42527$1887_Y + connect \$291 $eq$libresoc.v:42528$1888_Y + connect \$293 $and$libresoc.v:42529$1889_Y + connect \$295 $eq$libresoc.v:42530$1890_Y + connect \$297 $or$libresoc.v:42531$1891_Y + connect \$270 $not$libresoc.v:42532$1892_Y + connect \$301 $and$libresoc.v:42533$1893_Y + connect \$303 $and$libresoc.v:42534$1894_Y + connect \$305 $eq$libresoc.v:42535$1895_Y + connect \$307 $or$libresoc.v:42536$1896_Y + connect \$309 $and$libresoc.v:42537$1897_Y + connect \$311 $or$libresoc.v:42538$1898_Y + connect \$300 $not$libresoc.v:42539$1899_Y + connect \$315 $and$libresoc.v:42540$1900_Y + connect \$317 $and$libresoc.v:42541$1901_Y + connect \$319 $eq$libresoc.v:42542$1902_Y + connect \$321 $or$libresoc.v:42543$1903_Y + connect \$323 $and$libresoc.v:42544$1904_Y + connect \$325 $or$libresoc.v:42545$1905_Y + connect \$314 $not$libresoc.v:42546$1906_Y + connect \$329 $and$libresoc.v:42547$1907_Y + connect \$331 $and$libresoc.v:42548$1908_Y + connect \$333 $eq$libresoc.v:42549$1909_Y + connect \$335 $or$libresoc.v:42550$1910_Y + connect \$337 $and$libresoc.v:42551$1911_Y + connect \$339 $or$libresoc.v:42552$1912_Y + connect \$341 $eq$libresoc.v:42553$1913_Y + connect \$343 $and$libresoc.v:42554$1914_Y + connect \$345 $eq$libresoc.v:42555$1915_Y + connect \$347 $or$libresoc.v:42556$1916_Y + connect \$328 $not$libresoc.v:42557$1917_Y + connect \$350 $not$libresoc.v:42558$1918_Y + connect \$352 $and$libresoc.v:42559$1919_Y + connect \$354 $and$libresoc.v:42560$1920_Y + connect \$356 $not$libresoc.v:42561$1921_Y + connect \$358 $and$libresoc.v:42562$1922_Y + connect \$360 $and$libresoc.v:42563$1923_Y + connect \$362 $ternary$libresoc.v:42564$1924_Y + connect \$364 $and$libresoc.v:42565$1925_Y + connect \$366 $and$libresoc.v:42566$1926_Y + connect \$368 $not$libresoc.v:42567$1927_Y + connect \$370 $and$libresoc.v:42568$1928_Y + connect \$372 $and$libresoc.v:42569$1929_Y + connect \$374 $ternary$libresoc.v:42570$1930_Y + connect \$376 $and$libresoc.v:42571$1931_Y + connect \$378 $and$libresoc.v:42572$1932_Y + connect \$380 $not$libresoc.v:42573$1933_Y + connect \$382 $and$libresoc.v:42574$1934_Y + connect \$384 $and$libresoc.v:42575$1935_Y + connect \$386 $ternary$libresoc.v:42576$1936_Y + connect \$388 $and$libresoc.v:42577$1937_Y + connect \$390 $and$libresoc.v:42578$1938_Y + connect \$392 $not$libresoc.v:42579$1939_Y + connect \$394 $and$libresoc.v:42580$1940_Y + connect \$396 $and$libresoc.v:42581$1941_Y + connect \$398 $ternary$libresoc.v:42582$1942_Y + connect \$400 $and$libresoc.v:42583$1943_Y + connect \$402 $and$libresoc.v:42584$1944_Y + connect \$404 $not$libresoc.v:42585$1945_Y + connect \$406 $and$libresoc.v:42586$1946_Y + connect \$408 $and$libresoc.v:42587$1947_Y + connect \$410 $ternary$libresoc.v:42588$1948_Y + connect \$412 $and$libresoc.v:42589$1949_Y + connect \$414 $and$libresoc.v:42590$1950_Y + connect \$416 $not$libresoc.v:42591$1951_Y + connect \$418 $and$libresoc.v:42592$1952_Y + connect \$420 $and$libresoc.v:42593$1953_Y + connect \$422 $ternary$libresoc.v:42594$1954_Y + connect \$424 $and$libresoc.v:42595$1955_Y + connect \$426 $and$libresoc.v:42596$1956_Y + connect \$428 $not$libresoc.v:42597$1957_Y + connect \$430 $and$libresoc.v:42598$1958_Y + connect \$432 $and$libresoc.v:42599$1959_Y + connect \$434 $ternary$libresoc.v:42600$1960_Y + connect \$436 $and$libresoc.v:42601$1961_Y + connect \$438 $and$libresoc.v:42602$1962_Y + connect \$440 $not$libresoc.v:42603$1963_Y + connect \$442 $and$libresoc.v:42604$1964_Y + connect \$444 $and$libresoc.v:42605$1965_Y + connect \$446 $ternary$libresoc.v:42606$1966_Y + connect \$448 $and$libresoc.v:42607$1967_Y + connect \$450 $and$libresoc.v:42608$1968_Y + connect \$452 $not$libresoc.v:42609$1969_Y + connect \$454 $and$libresoc.v:42610$1970_Y + connect \$456 $and$libresoc.v:42611$1971_Y + connect \$458 $ternary$libresoc.v:42612$1972_Y + connect \$461 $or$libresoc.v:42613$1973_Y + connect \$463 $or$libresoc.v:42614$1974_Y + connect \$465 $or$libresoc.v:42615$1975_Y + connect \$467 $or$libresoc.v:42616$1976_Y + connect \$469 $or$libresoc.v:42617$1977_Y + connect \$471 $or$libresoc.v:42618$1978_Y + connect \$473 $or$libresoc.v:42619$1979_Y + connect \$475 $or$libresoc.v:42620$1980_Y + connect \$477 $reduce_or$libresoc.v:42621$1981_Y + connect \$479 $and$libresoc.v:42622$1982_Y + connect \$481 $and$libresoc.v:42623$1983_Y + connect \$483 $not$libresoc.v:42624$1984_Y + connect \$485 $and$libresoc.v:42625$1985_Y + connect \$487 $and$libresoc.v:42626$1986_Y + connect \$489 $ternary$libresoc.v:42627$1987_Y + connect \$491 $and$libresoc.v:42628$1988_Y + connect \$493 $and$libresoc.v:42629$1989_Y + connect \$495 $not$libresoc.v:42630$1990_Y + connect \$497 $and$libresoc.v:42631$1991_Y + connect \$499 $and$libresoc.v:42632$1992_Y + connect \$501 $ternary$libresoc.v:42633$1993_Y + connect \$503 $and$libresoc.v:42634$1994_Y + connect \$505 $and$libresoc.v:42635$1995_Y + connect \$507 $not$libresoc.v:42636$1996_Y + connect \$509 $and$libresoc.v:42637$1997_Y + connect \$511 $and$libresoc.v:42638$1998_Y + connect \$513 $ternary$libresoc.v:42639$1999_Y + connect \$515 $and$libresoc.v:42640$2000_Y + connect \$517 $and$libresoc.v:42641$2001_Y + connect \$519 $not$libresoc.v:42642$2002_Y + connect \$521 $and$libresoc.v:42643$2003_Y + connect \$523 $and$libresoc.v:42644$2004_Y + connect \$525 $ternary$libresoc.v:42645$2005_Y + connect \$527 $and$libresoc.v:42646$2006_Y + connect \$529 $and$libresoc.v:42647$2007_Y + connect \$531 $not$libresoc.v:42648$2008_Y + connect \$533 $and$libresoc.v:42649$2009_Y + connect \$535 $and$libresoc.v:42650$2010_Y + connect \$537 $ternary$libresoc.v:42651$2011_Y + connect \$539 $and$libresoc.v:42652$2012_Y + connect \$541 $and$libresoc.v:42653$2013_Y + connect \$543 $not$libresoc.v:42654$2014_Y + connect \$545 $and$libresoc.v:42655$2015_Y + connect \$547 $and$libresoc.v:42656$2016_Y + connect \$549 $ternary$libresoc.v:42657$2017_Y + connect \$551 $and$libresoc.v:42658$2018_Y + connect \$553 $and$libresoc.v:42659$2019_Y + connect \$555 $not$libresoc.v:42660$2020_Y + connect \$557 $and$libresoc.v:42661$2021_Y + connect \$559 $and$libresoc.v:42662$2022_Y + connect \$561 $ternary$libresoc.v:42663$2023_Y + connect \$563 $and$libresoc.v:42664$2024_Y + connect \$565 $and$libresoc.v:42665$2025_Y + connect \$567 $not$libresoc.v:42666$2026_Y + connect \$569 $and$libresoc.v:42667$2027_Y + connect \$571 $and$libresoc.v:42668$2028_Y + connect \$573 $ternary$libresoc.v:42669$2029_Y + connect \$576 $or$libresoc.v:42670$2030_Y + connect \$578 $or$libresoc.v:42671$2031_Y + connect \$580 $or$libresoc.v:42672$2032_Y + connect \$582 $or$libresoc.v:42673$2033_Y + connect \$584 $or$libresoc.v:42674$2034_Y + connect \$586 $or$libresoc.v:42675$2035_Y + connect \$588 $or$libresoc.v:42676$2036_Y + connect \$590 $reduce_or$libresoc.v:42677$2037_Y + connect \$592 $and$libresoc.v:42678$2038_Y + connect \$594 $and$libresoc.v:42679$2039_Y + connect \$596 $not$libresoc.v:42680$2040_Y + connect \$598 $and$libresoc.v:42681$2041_Y + connect \$600 $and$libresoc.v:42682$2042_Y + connect \$602 $ternary$libresoc.v:42683$2043_Y + connect \$604 $and$libresoc.v:42684$2044_Y + connect \$606 $and$libresoc.v:42685$2045_Y + connect \$608 $not$libresoc.v:42686$2046_Y + connect \$610 $and$libresoc.v:42687$2047_Y + connect \$612 $and$libresoc.v:42688$2048_Y + connect \$614 $ternary$libresoc.v:42689$2049_Y + connect \$617 $or$libresoc.v:42690$2050_Y + connect \$619 $reduce_or$libresoc.v:42691$2051_Y + connect \$621 $and$libresoc.v:42692$2052_Y + connect \$623 $and$libresoc.v:42693$2053_Y + connect \$625 $eq$libresoc.v:42694$2054_Y + connect \$627 $or$libresoc.v:42695$2055_Y + connect \$629 $and$libresoc.v:42696$2056_Y + connect \$631 $or$libresoc.v:42697$2057_Y + connect \$633 $and$libresoc.v:42698$2058_Y + connect \$635 $and$libresoc.v:42699$2059_Y + connect \$637 $not$libresoc.v:42700$2060_Y + connect \$639 $and$libresoc.v:42701$2061_Y + connect \$641 $and$libresoc.v:42702$2062_Y + connect \$643 $ternary$libresoc.v:42703$2063_Y + connect \$645 $and$libresoc.v:42704$2064_Y + connect \$647 $and$libresoc.v:42705$2065_Y + connect \$649 $not$libresoc.v:42706$2066_Y + connect \$651 $and$libresoc.v:42707$2067_Y + connect \$653 $and$libresoc.v:42708$2068_Y + connect \$655 $ternary$libresoc.v:42709$2069_Y + connect \$657 $and$libresoc.v:42710$2070_Y + connect \$659 $and$libresoc.v:42711$2071_Y + connect \$661 $not$libresoc.v:42712$2072_Y + connect \$663 $and$libresoc.v:42713$2073_Y + connect \$665 $and$libresoc.v:42714$2074_Y + connect \$667 $ternary$libresoc.v:42715$2075_Y + connect \$669 $and$libresoc.v:42716$2076_Y + connect \$671 $and$libresoc.v:42717$2077_Y + connect \$673 $not$libresoc.v:42718$2078_Y + connect \$675 $and$libresoc.v:42719$2079_Y + connect \$677 $and$libresoc.v:42720$2080_Y + connect \$679 $ternary$libresoc.v:42721$2081_Y + connect \$681 $and$libresoc.v:42722$2082_Y + connect \$683 $and$libresoc.v:42723$2083_Y + connect \$685 $not$libresoc.v:42724$2084_Y + connect \$687 $and$libresoc.v:42725$2085_Y + connect \$689 $and$libresoc.v:42726$2086_Y + connect \$691 $ternary$libresoc.v:42727$2087_Y + connect \$693 $and$libresoc.v:42728$2088_Y + connect \$695 $and$libresoc.v:42729$2089_Y + connect \$697 $not$libresoc.v:42730$2090_Y + connect \$699 $and$libresoc.v:42731$2091_Y + connect \$701 $and$libresoc.v:42732$2092_Y + connect \$703 $ternary$libresoc.v:42733$2093_Y + connect \$706 $or$libresoc.v:42734$2094_Y + connect \$708 $or$libresoc.v:42735$2095_Y + connect \$710 $or$libresoc.v:42736$2096_Y + connect \$712 $or$libresoc.v:42737$2097_Y + connect \$714 $or$libresoc.v:42738$2098_Y + connect \$705 $pos$libresoc.v:42739$2100_Y + connect \$717 $eq$libresoc.v:42740$2101_Y + connect \$719 $and$libresoc.v:42741$2102_Y + connect \$721 $eq$libresoc.v:42742$2103_Y + connect \$723 $or$libresoc.v:42743$2104_Y + connect \$725 $and$libresoc.v:42744$2105_Y + connect \$727 $and$libresoc.v:42745$2106_Y + connect \$729 $not$libresoc.v:42746$2107_Y + connect \$731 $and$libresoc.v:42747$2108_Y + connect \$733 $and$libresoc.v:42748$2109_Y + connect \$735 $ternary$libresoc.v:42749$2110_Y + connect \$737 $and$libresoc.v:42750$2111_Y + connect \$739 $and$libresoc.v:42751$2112_Y + connect \$741 $not$libresoc.v:42752$2113_Y + connect \$743 $and$libresoc.v:42753$2114_Y + connect \$745 $and$libresoc.v:42754$2115_Y + connect \$747 $ternary$libresoc.v:42755$2116_Y + connect \$749 $and$libresoc.v:42756$2117_Y + connect \$751 $and$libresoc.v:42757$2118_Y + connect \$753 $not$libresoc.v:42758$2119_Y + connect \$755 $and$libresoc.v:42759$2120_Y + connect \$757 $and$libresoc.v:42760$2121_Y + connect \$759 $ternary$libresoc.v:42761$2122_Y + connect \$762 $or$libresoc.v:42762$2123_Y + connect \$764 $or$libresoc.v:42763$2124_Y + connect \$761 $pos$libresoc.v:42764$2126_Y + connect \$767 $and$libresoc.v:42765$2127_Y + connect \$769 $and$libresoc.v:42766$2128_Y + connect \$771 $eq$libresoc.v:42767$2129_Y + connect \$773 $or$libresoc.v:42768$2130_Y + connect \$775 $and$libresoc.v:42769$2131_Y + connect \$777 $and$libresoc.v:42770$2132_Y + connect \$779 $not$libresoc.v:42771$2133_Y + connect \$781 $and$libresoc.v:42772$2134_Y + connect \$783 $and$libresoc.v:42773$2135_Y + connect \$785 $ternary$libresoc.v:42774$2136_Y + connect \$787 $and$libresoc.v:42775$2137_Y + connect \$789 $and$libresoc.v:42776$2138_Y + connect \$791 $not$libresoc.v:42777$2139_Y + connect \$793 $and$libresoc.v:42778$2140_Y + connect \$795 $and$libresoc.v:42779$2141_Y + connect \$797 $ternary$libresoc.v:42780$2142_Y + connect \$799 $and$libresoc.v:42781$2143_Y + connect \$801 $and$libresoc.v:42782$2144_Y + connect \$803 $not$libresoc.v:42783$2145_Y + connect \$805 $and$libresoc.v:42784$2146_Y + connect \$807 $and$libresoc.v:42785$2147_Y + connect \$809 $sub$libresoc.v:42786$2148_Y + connect \$811 $sshl$libresoc.v:42787$2149_Y + connect \$813 $ternary$libresoc.v:42788$2150_Y + connect \$815 $and$libresoc.v:42789$2151_Y + connect \$817 $and$libresoc.v:42790$2152_Y + connect \$819 $not$libresoc.v:42791$2153_Y + connect \$821 $and$libresoc.v:42792$2154_Y + connect \$823 $and$libresoc.v:42793$2155_Y + connect \$825 $sub$libresoc.v:42794$2156_Y + connect \$827 $sshl$libresoc.v:42795$2157_Y + connect \$829 $ternary$libresoc.v:42796$2158_Y + connect \$832 $or$libresoc.v:42797$2159_Y + connect \$834 $and$libresoc.v:42798$2160_Y + connect \$836 $and$libresoc.v:42799$2161_Y + connect \$838 $not$libresoc.v:42800$2162_Y + connect \$840 $and$libresoc.v:42801$2163_Y + connect \$842 $and$libresoc.v:42802$2164_Y + connect \$844 $sub$libresoc.v:42803$2165_Y + connect \$846 $sshl$libresoc.v:42804$2166_Y + connect \$848 $ternary$libresoc.v:42805$2167_Y + connect \$850 $and$libresoc.v:42806$2168_Y + connect \$852 $and$libresoc.v:42807$2169_Y + connect \$854 $not$libresoc.v:42808$2170_Y + connect \$856 $and$libresoc.v:42809$2171_Y + connect \$858 $and$libresoc.v:42810$2172_Y + connect \$860 $sub$libresoc.v:42811$2173_Y + connect \$862 $sshl$libresoc.v:42812$2174_Y + connect \$864 $ternary$libresoc.v:42813$2175_Y + connect \$866 $and$libresoc.v:42814$2176_Y + connect \$868 $and$libresoc.v:42815$2177_Y + connect \$870 $not$libresoc.v:42816$2178_Y + connect \$872 $and$libresoc.v:42817$2179_Y + connect \$874 $and$libresoc.v:42818$2180_Y + connect \$876 $ternary$libresoc.v:42819$2181_Y + connect \$878 $and$libresoc.v:42820$2182_Y + connect \$880 $and$libresoc.v:42821$2183_Y + connect \$882 $not$libresoc.v:42822$2184_Y + connect \$884 $and$libresoc.v:42823$2185_Y + connect \$886 $and$libresoc.v:42824$2186_Y + connect \$888 $ternary$libresoc.v:42825$2187_Y + connect \$890 $and$libresoc.v:42826$2188_Y + connect \$892 $and$libresoc.v:42827$2189_Y + connect \$894 $not$libresoc.v:42828$2190_Y + connect \$896 $and$libresoc.v:42829$2191_Y + connect \$898 $and$libresoc.v:42830$2192_Y + connect \$900 $ternary$libresoc.v:42831$2193_Y + connect \$902 $or$libresoc.v:42832$2194_Y + connect \$904 $or$libresoc.v:42833$2195_Y + connect \$906 $reduce_or$libresoc.v:42834$2196_Y + connect \$908 $and$libresoc.v:42835$2197_Y + connect \$910 $and$libresoc.v:42836$2198_Y + connect \$912 $not$libresoc.v:42837$2199_Y + connect \$914 $and$libresoc.v:42838$2200_Y + connect \$916 $and$libresoc.v:42839$2201_Y + connect \$918 $ternary$libresoc.v:42840$2202_Y + connect \$920 $and$libresoc.v:42841$2203_Y + connect \$922 $and$libresoc.v:42842$2204_Y + connect \$924 $not$libresoc.v:42843$2205_Y + connect \$926 $and$libresoc.v:42844$2206_Y + connect \$928 $and$libresoc.v:42845$2207_Y + connect \$930 $ternary$libresoc.v:42846$2208_Y + connect \$932 $or$libresoc.v:42847$2209_Y + connect \$934 $reduce_or$libresoc.v:42848$2210_Y + connect \$936 $and$libresoc.v:42849$2211_Y + connect \$938 $and$libresoc.v:42850$2212_Y + connect \$940 $not$libresoc.v:42851$2213_Y + connect \$942 $and$libresoc.v:42852$2214_Y + connect \$944 $and$libresoc.v:42853$2215_Y + connect \$946 $ternary$libresoc.v:42854$2216_Y + connect \$948 $reduce_or$libresoc.v:42855$2217_Y + connect \$950 $and$libresoc.v:42856$2218_Y + connect \$952 $and$libresoc.v:42857$2219_Y + connect \$954 $and$libresoc.v:42858$2220_Y + connect \$956 $and$libresoc.v:42859$2221_Y + connect \$958 $and$libresoc.v:42860$2222_Y + connect \$960 $and$libresoc.v:42861$2223_Y + connect \$962 $and$libresoc.v:42862$2224_Y + connect \$964 $and$libresoc.v:42863$2225_Y + connect \$966 $and$libresoc.v:42864$2226_Y + connect \$968 $and$libresoc.v:42865$2227_Y + connect \$970 $and$libresoc.v:42866$2228_Y + connect \$972 $and$libresoc.v:42867$2229_Y + connect \$974 $not$libresoc.v:42868$2230_Y + connect \$976 $and$libresoc.v:42869$2231_Y + connect \$982 $and$libresoc.v:42870$2232_Y + connect \$984 $ternary$libresoc.v:42871$2233_Y + connect \$986 $and$libresoc.v:42872$2234_Y + connect \$989 $and$libresoc.v:42873$2235_Y + connect \$993 $not$libresoc.v:42874$2236_Y + connect \$995 $and$libresoc.v:42875$2237_Y connect \$223 \$224 connect \$460 \$475 connect \$575 \$588 @@ -85800,125 +85839,125 @@ module \core connect \dec_ALU_bigendian \bigendian_i connect \dec_ALU_raw_opcode_in \raw_insn_i end -attribute \src "libresoc.v:49145.1-49881.10" +attribute \src "libresoc.v:49197.1-49933.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr" attribute \generator "nMigen" module \cr - attribute \src "libresoc.v:49840.3-49849.6" + attribute \src "libresoc.v:49892.3-49901.6" wire width 4 $0\cr_pred__data_o[3:0] - attribute \src "libresoc.v:49146.7-49146.20" + attribute \src "libresoc.v:49198.7-49198.20" wire $0\initial[0:0] - attribute \src "libresoc.v:49774.3-49782.6" + attribute \src "libresoc.v:49826.3-49834.6" wire width 8 $0\ren_delay$17$next[7:0]$3056 - attribute \src "libresoc.v:49594.3-49595.43" + attribute \src "libresoc.v:49646.3-49647.43" wire width 8 $0\ren_delay$17[7:0]$3053 - attribute \src "libresoc.v:49526.13-49526.35" + attribute \src "libresoc.v:49578.13-49578.35" wire width 8 $0\ren_delay$17[7:0]$3074 - attribute \src "libresoc.v:49793.3-49801.6" + attribute \src "libresoc.v:49845.3-49853.6" wire width 8 $0\ren_delay$34$next[7:0]$3060 - attribute \src "libresoc.v:49592.3-49593.43" + attribute \src "libresoc.v:49644.3-49645.43" wire width 8 $0\ren_delay$34[7:0]$3051 - attribute \src "libresoc.v:49530.13-49530.35" + attribute \src "libresoc.v:49582.13-49582.35" wire width 8 $0\ren_delay$34[7:0]$3076 - attribute \src "libresoc.v:49812.3-49820.6" + attribute \src "libresoc.v:49864.3-49872.6" wire width 8 $0\ren_delay$51$next[7:0]$3064 - attribute \src "libresoc.v:49590.3-49591.43" + attribute \src "libresoc.v:49642.3-49643.43" wire width 8 $0\ren_delay$51[7:0]$3049 - attribute \src "libresoc.v:49534.13-49534.35" + attribute \src "libresoc.v:49586.13-49586.35" wire width 8 $0\ren_delay$51[7:0]$3078 - attribute \src "libresoc.v:49831.3-49839.6" + attribute \src "libresoc.v:49883.3-49891.6" wire width 8 $0\ren_delay$next[7:0]$3068 - attribute \src "libresoc.v:49596.3-49597.35" + attribute \src "libresoc.v:49648.3-49649.35" wire width 8 $0\ren_delay[7:0] - attribute \src "libresoc.v:49783.3-49792.6" + attribute \src "libresoc.v:49835.3-49844.6" wire width 4 $0\src1__data_o[3:0] - attribute \src "libresoc.v:49802.3-49811.6" + attribute \src "libresoc.v:49854.3-49863.6" wire width 4 $0\src2__data_o[3:0] - attribute \src "libresoc.v:49821.3-49830.6" + attribute \src "libresoc.v:49873.3-49882.6" wire width 4 $0\src3__data_o[3:0] - attribute \src "libresoc.v:49840.3-49849.6" + attribute \src "libresoc.v:49892.3-49901.6" wire width 4 $1\cr_pred__data_o[3:0] - attribute \src "libresoc.v:49774.3-49782.6" + attribute \src "libresoc.v:49826.3-49834.6" wire width 8 $1\ren_delay$17$next[7:0]$3057 - attribute \src "libresoc.v:49793.3-49801.6" + attribute \src "libresoc.v:49845.3-49853.6" wire width 8 $1\ren_delay$34$next[7:0]$3061 - attribute \src "libresoc.v:49812.3-49820.6" + attribute \src "libresoc.v:49864.3-49872.6" wire width 8 $1\ren_delay$51$next[7:0]$3065 - attribute \src "libresoc.v:49831.3-49839.6" + attribute \src "libresoc.v:49883.3-49891.6" wire width 8 $1\ren_delay$next[7:0]$3069 - attribute \src "libresoc.v:49524.13-49524.30" + attribute \src "libresoc.v:49576.13-49576.30" wire width 8 $1\ren_delay[7:0] - attribute \src "libresoc.v:49783.3-49792.6" + attribute \src "libresoc.v:49835.3-49844.6" wire width 4 $1\src1__data_o[3:0] - attribute \src "libresoc.v:49802.3-49811.6" + attribute \src "libresoc.v:49854.3-49863.6" wire width 4 $1\src2__data_o[3:0] - attribute \src "libresoc.v:49821.3-49830.6" + attribute \src "libresoc.v:49873.3-49882.6" wire width 4 $1\src3__data_o[3:0] - attribute \src "libresoc.v:49558.17-49558.131" - wire width 4 $or$libresoc.v:49558$3016_Y - attribute \src "libresoc.v:49559.18-49559.132" - wire width 4 $or$libresoc.v:49559$3017_Y - attribute \src "libresoc.v:49560.18-49560.96" - wire width 4 $or$libresoc.v:49560$3018_Y - attribute \src "libresoc.v:49561.18-49561.96" - wire width 4 $or$libresoc.v:49561$3019_Y - attribute \src "libresoc.v:49564.18-49564.126" - wire width 4 $or$libresoc.v:49564$3022_Y - attribute \src "libresoc.v:49565.18-49565.126" - wire width 4 $or$libresoc.v:49565$3023_Y - attribute \src "libresoc.v:49566.18-49566.97" - wire width 4 $or$libresoc.v:49566$3024_Y - attribute \src "libresoc.v:49567.18-49567.126" - wire width 4 $or$libresoc.v:49567$3025_Y - attribute \src "libresoc.v:49568.18-49568.126" - wire width 4 $or$libresoc.v:49568$3026_Y - attribute \src "libresoc.v:49569.18-49569.97" - wire width 4 $or$libresoc.v:49569$3027_Y - attribute \src "libresoc.v:49570.18-49570.97" - wire width 4 $or$libresoc.v:49570$3028_Y - attribute \src "libresoc.v:49572.18-49572.126" - wire width 4 $or$libresoc.v:49572$3030_Y - attribute \src "libresoc.v:49573.17-49573.131" - wire width 4 $or$libresoc.v:49573$3031_Y - attribute \src "libresoc.v:49574.18-49574.126" - wire width 4 $or$libresoc.v:49574$3032_Y - attribute \src "libresoc.v:49575.18-49575.97" - wire width 4 $or$libresoc.v:49575$3033_Y - attribute \src "libresoc.v:49576.18-49576.126" - wire width 4 $or$libresoc.v:49576$3034_Y - attribute \src "libresoc.v:49577.18-49577.126" - wire width 4 $or$libresoc.v:49577$3035_Y - attribute \src "libresoc.v:49578.18-49578.97" - wire width 4 $or$libresoc.v:49578$3036_Y - attribute \src "libresoc.v:49579.18-49579.97" - wire width 4 $or$libresoc.v:49579$3037_Y - attribute \src "libresoc.v:49581.18-49581.126" - wire width 4 $or$libresoc.v:49581$3039_Y - attribute \src "libresoc.v:49582.18-49582.126" - wire width 4 $or$libresoc.v:49582$3040_Y - attribute \src "libresoc.v:49583.18-49583.97" - wire width 4 $or$libresoc.v:49583$3041_Y - attribute \src "libresoc.v:49584.17-49584.131" - wire width 4 $or$libresoc.v:49584$3042_Y - attribute \src "libresoc.v:49585.18-49585.126" - wire width 4 $or$libresoc.v:49585$3043_Y - attribute \src "libresoc.v:49586.18-49586.126" - wire width 4 $or$libresoc.v:49586$3044_Y - attribute \src "libresoc.v:49587.18-49587.97" - wire width 4 $or$libresoc.v:49587$3045_Y - attribute \src "libresoc.v:49588.18-49588.97" - wire width 4 $or$libresoc.v:49588$3046_Y - attribute \src "libresoc.v:49589.17-49589.94" - wire width 4 $or$libresoc.v:49589$3047_Y - attribute \src "libresoc.v:49562.18-49562.100" - wire $reduce_or$libresoc.v:49562$3020_Y - attribute \src "libresoc.v:49563.17-49563.95" - wire $reduce_or$libresoc.v:49563$3021_Y - attribute \src "libresoc.v:49571.18-49571.100" - wire $reduce_or$libresoc.v:49571$3029_Y - attribute \src "libresoc.v:49580.18-49580.100" - wire $reduce_or$libresoc.v:49580$3038_Y + attribute \src "libresoc.v:49610.17-49610.131" + wire width 4 $or$libresoc.v:49610$3016_Y + attribute \src "libresoc.v:49611.18-49611.132" + wire width 4 $or$libresoc.v:49611$3017_Y + attribute \src "libresoc.v:49612.18-49612.96" + wire width 4 $or$libresoc.v:49612$3018_Y + attribute \src "libresoc.v:49613.18-49613.96" + wire width 4 $or$libresoc.v:49613$3019_Y + attribute \src "libresoc.v:49616.18-49616.126" + wire width 4 $or$libresoc.v:49616$3022_Y + attribute \src "libresoc.v:49617.18-49617.126" + wire width 4 $or$libresoc.v:49617$3023_Y + attribute \src "libresoc.v:49618.18-49618.97" + wire width 4 $or$libresoc.v:49618$3024_Y + attribute \src "libresoc.v:49619.18-49619.126" + wire width 4 $or$libresoc.v:49619$3025_Y + attribute \src "libresoc.v:49620.18-49620.126" + wire width 4 $or$libresoc.v:49620$3026_Y + attribute \src "libresoc.v:49621.18-49621.97" + wire width 4 $or$libresoc.v:49621$3027_Y + attribute \src "libresoc.v:49622.18-49622.97" + wire width 4 $or$libresoc.v:49622$3028_Y + attribute \src "libresoc.v:49624.18-49624.126" + wire width 4 $or$libresoc.v:49624$3030_Y + attribute \src "libresoc.v:49625.17-49625.131" + wire width 4 $or$libresoc.v:49625$3031_Y + attribute \src "libresoc.v:49626.18-49626.126" + wire width 4 $or$libresoc.v:49626$3032_Y + attribute \src "libresoc.v:49627.18-49627.97" + wire width 4 $or$libresoc.v:49627$3033_Y + attribute \src "libresoc.v:49628.18-49628.126" + wire width 4 $or$libresoc.v:49628$3034_Y + attribute \src "libresoc.v:49629.18-49629.126" + wire width 4 $or$libresoc.v:49629$3035_Y + attribute \src "libresoc.v:49630.18-49630.97" + wire width 4 $or$libresoc.v:49630$3036_Y + attribute \src "libresoc.v:49631.18-49631.97" + wire width 4 $or$libresoc.v:49631$3037_Y + attribute \src "libresoc.v:49633.18-49633.126" + wire width 4 $or$libresoc.v:49633$3039_Y + attribute \src "libresoc.v:49634.18-49634.126" + wire width 4 $or$libresoc.v:49634$3040_Y + attribute \src "libresoc.v:49635.18-49635.97" + wire width 4 $or$libresoc.v:49635$3041_Y + attribute \src "libresoc.v:49636.17-49636.131" + wire width 4 $or$libresoc.v:49636$3042_Y + attribute \src "libresoc.v:49637.18-49637.126" + wire width 4 $or$libresoc.v:49637$3043_Y + attribute \src "libresoc.v:49638.18-49638.126" + wire width 4 $or$libresoc.v:49638$3044_Y + attribute \src "libresoc.v:49639.18-49639.97" + wire width 4 $or$libresoc.v:49639$3045_Y + attribute \src "libresoc.v:49640.18-49640.97" + wire width 4 $or$libresoc.v:49640$3046_Y + attribute \src "libresoc.v:49641.17-49641.94" + wire width 4 $or$libresoc.v:49641$3047_Y + attribute \src "libresoc.v:49614.18-49614.100" + wire $reduce_or$libresoc.v:49614$3020_Y + attribute \src "libresoc.v:49615.17-49615.95" + wire $reduce_or$libresoc.v:49615$3021_Y + attribute \src "libresoc.v:49623.18-49623.100" + wire $reduce_or$libresoc.v:49623$3029_Y + attribute \src "libresoc.v:49632.18-49632.100" + wire $reduce_or$libresoc.v:49632$3038_Y attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" @@ -85983,9 +86022,9 @@ module \cr wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \cr_pred__data_o @@ -86007,7 +86046,7 @@ module \cr wire width 32 input 12 \full_wr__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 input 13 \full_wr__wen - attribute \src "libresoc.v:49146.7-49146.15" + attribute \src "libresoc.v:49198.7-49198.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 \reg_0_cr_pred0__data_o @@ -86330,7 +86369,7 @@ module \cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 8 \wen$68 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49558$3016 + cell $or $or$libresoc.v:49610$3016 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86338,10 +86377,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_4_cr_pred4__data_o connect \B \reg_5_cr_pred5__data_o - connect \Y $or$libresoc.v:49558$3016_Y + connect \Y $or$libresoc.v:49610$3016_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49559$3017 + cell $or $or$libresoc.v:49611$3017 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86349,10 +86388,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_6_cr_pred6__data_o connect \B \reg_7_cr_pred7__data_o - connect \Y $or$libresoc.v:49559$3017_Y + connect \Y $or$libresoc.v:49611$3017_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49560$3018 + cell $or $or$libresoc.v:49612$3018 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86360,10 +86399,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$9 connect \B \$11 - connect \Y $or$libresoc.v:49560$3018_Y + connect \Y $or$libresoc.v:49612$3018_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49561$3019 + cell $or $or$libresoc.v:49613$3019 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86371,10 +86410,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$7 connect \B \$13 - connect \Y $or$libresoc.v:49561$3019_Y + connect \Y $or$libresoc.v:49613$3019_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49564$3022 + cell $or $or$libresoc.v:49616$3022 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86382,10 +86421,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_0_src10__data_o connect \B \reg_1_src11__data_o - connect \Y $or$libresoc.v:49564$3022_Y + connect \Y $or$libresoc.v:49616$3022_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49565$3023 + cell $or $or$libresoc.v:49617$3023 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86393,10 +86432,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_2_src12__data_o connect \B \reg_3_src13__data_o - connect \Y $or$libresoc.v:49565$3023_Y + connect \Y $or$libresoc.v:49617$3023_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49566$3024 + cell $or $or$libresoc.v:49618$3024 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86404,10 +86443,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$20 connect \B \$22 - connect \Y $or$libresoc.v:49566$3024_Y + connect \Y $or$libresoc.v:49618$3024_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49567$3025 + cell $or $or$libresoc.v:49619$3025 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86415,10 +86454,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_4_src14__data_o connect \B \reg_5_src15__data_o - connect \Y $or$libresoc.v:49567$3025_Y + connect \Y $or$libresoc.v:49619$3025_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49568$3026 + cell $or $or$libresoc.v:49620$3026 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86426,10 +86465,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_6_src16__data_o connect \B \reg_7_src17__data_o - connect \Y $or$libresoc.v:49568$3026_Y + connect \Y $or$libresoc.v:49620$3026_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49569$3027 + cell $or $or$libresoc.v:49621$3027 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86437,10 +86476,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:49569$3027_Y + connect \Y $or$libresoc.v:49621$3027_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49570$3028 + cell $or $or$libresoc.v:49622$3028 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86448,10 +86487,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$24 connect \B \$30 - connect \Y $or$libresoc.v:49570$3028_Y + connect \Y $or$libresoc.v:49622$3028_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49572$3030 + cell $or $or$libresoc.v:49624$3030 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86459,10 +86498,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_0_src20__data_o connect \B \reg_1_src21__data_o - connect \Y $or$libresoc.v:49572$3030_Y + connect \Y $or$libresoc.v:49624$3030_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49573$3031 + cell $or $or$libresoc.v:49625$3031 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86470,10 +86509,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_0_cr_pred0__data_o connect \B \reg_1_cr_pred1__data_o - connect \Y $or$libresoc.v:49573$3031_Y + connect \Y $or$libresoc.v:49625$3031_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49574$3032 + cell $or $or$libresoc.v:49626$3032 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86481,10 +86520,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_2_src22__data_o connect \B \reg_3_src23__data_o - connect \Y $or$libresoc.v:49574$3032_Y + connect \Y $or$libresoc.v:49626$3032_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49575$3033 + cell $or $or$libresoc.v:49627$3033 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86492,10 +86531,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$37 connect \B \$39 - connect \Y $or$libresoc.v:49575$3033_Y + connect \Y $or$libresoc.v:49627$3033_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49576$3034 + cell $or $or$libresoc.v:49628$3034 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86503,10 +86542,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_4_src24__data_o connect \B \reg_5_src25__data_o - connect \Y $or$libresoc.v:49576$3034_Y + connect \Y $or$libresoc.v:49628$3034_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49577$3035 + cell $or $or$libresoc.v:49629$3035 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86514,10 +86553,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_6_src26__data_o connect \B \reg_7_src27__data_o - connect \Y $or$libresoc.v:49577$3035_Y + connect \Y $or$libresoc.v:49629$3035_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49578$3036 + cell $or $or$libresoc.v:49630$3036 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86525,10 +86564,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$43 connect \B \$45 - connect \Y $or$libresoc.v:49578$3036_Y + connect \Y $or$libresoc.v:49630$3036_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49579$3037 + cell $or $or$libresoc.v:49631$3037 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86536,10 +86575,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$41 connect \B \$47 - connect \Y $or$libresoc.v:49579$3037_Y + connect \Y $or$libresoc.v:49631$3037_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49581$3039 + cell $or $or$libresoc.v:49633$3039 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86547,10 +86586,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_0_src30__data_o connect \B \reg_1_src31__data_o - connect \Y $or$libresoc.v:49581$3039_Y + connect \Y $or$libresoc.v:49633$3039_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49582$3040 + cell $or $or$libresoc.v:49634$3040 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86558,10 +86597,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_2_src32__data_o connect \B \reg_3_src33__data_o - connect \Y $or$libresoc.v:49582$3040_Y + connect \Y $or$libresoc.v:49634$3040_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49583$3041 + cell $or $or$libresoc.v:49635$3041 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86569,10 +86608,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$54 connect \B \$56 - connect \Y $or$libresoc.v:49583$3041_Y + connect \Y $or$libresoc.v:49635$3041_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49584$3042 + cell $or $or$libresoc.v:49636$3042 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86580,10 +86619,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_2_cr_pred2__data_o connect \B \reg_3_cr_pred3__data_o - connect \Y $or$libresoc.v:49584$3042_Y + connect \Y $or$libresoc.v:49636$3042_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49585$3043 + cell $or $or$libresoc.v:49637$3043 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86591,10 +86630,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_4_src34__data_o connect \B \reg_5_src35__data_o - connect \Y $or$libresoc.v:49585$3043_Y + connect \Y $or$libresoc.v:49637$3043_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:49586$3044 + cell $or $or$libresoc.v:49638$3044 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86602,10 +86641,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \reg_6_src36__data_o connect \B \reg_7_src37__data_o - connect \Y $or$libresoc.v:49586$3044_Y + connect \Y $or$libresoc.v:49638$3044_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49587$3045 + cell $or $or$libresoc.v:49639$3045 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86613,10 +86652,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$60 connect \B \$62 - connect \Y $or$libresoc.v:49587$3045_Y + connect \Y $or$libresoc.v:49639$3045_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49588$3046 + cell $or $or$libresoc.v:49640$3046 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86624,10 +86663,10 @@ module \cr parameter \Y_WIDTH 4 connect \A \$58 connect \B \$64 - connect \Y $or$libresoc.v:49588$3046_Y + connect \Y $or$libresoc.v:49640$3046_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:49589$3047 + cell $or $or$libresoc.v:49641$3047 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -86635,42 +86674,42 @@ module \cr parameter \Y_WIDTH 4 connect \A \$3 connect \B \$5 - connect \Y $or$libresoc.v:49589$3047_Y + connect \Y $or$libresoc.v:49641$3047_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:49562$3020 + cell $reduce_or $reduce_or$libresoc.v:49614$3020 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ren_delay$17 - connect \Y $reduce_or$libresoc.v:49562$3020_Y + connect \Y $reduce_or$libresoc.v:49614$3020_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:49563$3021 + cell $reduce_or $reduce_or$libresoc.v:49615$3021 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ren_delay - connect \Y $reduce_or$libresoc.v:49563$3021_Y + connect \Y $reduce_or$libresoc.v:49615$3021_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:49571$3029 + cell $reduce_or $reduce_or$libresoc.v:49623$3029 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ren_delay$34 - connect \Y $reduce_or$libresoc.v:49571$3029_Y + connect \Y $reduce_or$libresoc.v:49623$3029_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:49580$3038 + cell $reduce_or $reduce_or$libresoc.v:49632$3038 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \ren_delay$51 - connect \Y $reduce_or$libresoc.v:49580$3038_Y + connect \Y $reduce_or$libresoc.v:49632$3038_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:49598.9-49619.4" + attribute \src "libresoc.v:49650.9-49671.4" cell \reg_0 \reg_0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -86694,7 +86733,7 @@ module \cr connect \w0__wen \reg_0_w0__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49620.9-49641.4" + attribute \src "libresoc.v:49672.9-49693.4" cell \reg_1 \reg_1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -86718,7 +86757,7 @@ module \cr connect \w1__wen \reg_1_w1__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49642.9-49663.4" + attribute \src "libresoc.v:49694.9-49715.4" cell \reg_2 \reg_2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -86742,7 +86781,7 @@ module \cr connect \w2__wen \reg_2_w2__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49664.9-49685.4" + attribute \src "libresoc.v:49716.9-49737.4" cell \reg_3 \reg_3 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -86766,7 +86805,7 @@ module \cr connect \w3__wen \reg_3_w3__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49686.9-49707.4" + attribute \src "libresoc.v:49738.9-49759.4" cell \reg_4 \reg_4 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -86790,7 +86829,7 @@ module \cr connect \w4__wen \reg_4_w4__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49708.9-49729.4" + attribute \src "libresoc.v:49760.9-49781.4" cell \reg_5 \reg_5 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -86814,7 +86853,7 @@ module \cr connect \w5__wen \reg_5_w5__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49730.9-49751.4" + attribute \src "libresoc.v:49782.9-49803.4" cell \reg_6 \reg_6 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -86838,7 +86877,7 @@ module \cr connect \w6__wen \reg_6_w6__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:49752.9-49773.4" + attribute \src "libresoc.v:49804.9-49825.4" cell \reg_7 \reg_7 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -86861,82 +86900,82 @@ module \cr connect \w7__data_i \reg_7_w7__data_i connect \w7__wen \reg_7_w7__wen end - attribute \src "libresoc.v:49146.7-49146.20" - process $proc$libresoc.v:49146$3071 + attribute \src "libresoc.v:49198.7-49198.20" + process $proc$libresoc.v:49198$3071 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:49524.13-49524.30" - process $proc$libresoc.v:49524$3072 + attribute \src "libresoc.v:49576.13-49576.30" + process $proc$libresoc.v:49576$3072 assign { } { } assign $1\ren_delay[7:0] 8'00000000 sync always sync init update \ren_delay $1\ren_delay[7:0] end - attribute \src "libresoc.v:49526.13-49526.35" - process $proc$libresoc.v:49526$3073 + attribute \src "libresoc.v:49578.13-49578.35" + process $proc$libresoc.v:49578$3073 assign { } { } assign $0\ren_delay$17[7:0]$3074 8'00000000 sync always sync init update \ren_delay$17 $0\ren_delay$17[7:0]$3074 end - attribute \src "libresoc.v:49530.13-49530.35" - process $proc$libresoc.v:49530$3075 + attribute \src "libresoc.v:49582.13-49582.35" + process $proc$libresoc.v:49582$3075 assign { } { } assign $0\ren_delay$34[7:0]$3076 8'00000000 sync always sync init update \ren_delay$34 $0\ren_delay$34[7:0]$3076 end - attribute \src "libresoc.v:49534.13-49534.35" - process $proc$libresoc.v:49534$3077 + attribute \src "libresoc.v:49586.13-49586.35" + process $proc$libresoc.v:49586$3077 assign { } { } assign $0\ren_delay$51[7:0]$3078 8'00000000 sync always sync init update \ren_delay$51 $0\ren_delay$51[7:0]$3078 end - attribute \src "libresoc.v:49590.3-49591.43" - process $proc$libresoc.v:49590$3048 + attribute \src "libresoc.v:49642.3-49643.43" + process $proc$libresoc.v:49642$3048 assign { } { } assign $0\ren_delay$51[7:0]$3049 \ren_delay$51$next sync posedge \coresync_clk update \ren_delay$51 $0\ren_delay$51[7:0]$3049 end - attribute \src "libresoc.v:49592.3-49593.43" - process $proc$libresoc.v:49592$3050 + attribute \src "libresoc.v:49644.3-49645.43" + process $proc$libresoc.v:49644$3050 assign { } { } assign $0\ren_delay$34[7:0]$3051 \ren_delay$34$next sync posedge \coresync_clk update \ren_delay$34 $0\ren_delay$34[7:0]$3051 end - attribute \src "libresoc.v:49594.3-49595.43" - process $proc$libresoc.v:49594$3052 + attribute \src "libresoc.v:49646.3-49647.43" + process $proc$libresoc.v:49646$3052 assign { } { } assign $0\ren_delay$17[7:0]$3053 \ren_delay$17$next sync posedge \coresync_clk update \ren_delay$17 $0\ren_delay$17[7:0]$3053 end - attribute \src "libresoc.v:49596.3-49597.35" - process $proc$libresoc.v:49596$3054 + attribute \src "libresoc.v:49648.3-49649.35" + process $proc$libresoc.v:49648$3054 assign { } { } assign $0\ren_delay[7:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[7:0] end - attribute \src "libresoc.v:49774.3-49782.6" - process $proc$libresoc.v:49774$3055 + attribute \src "libresoc.v:49826.3-49834.6" + process $proc$libresoc.v:49826$3055 assign { } { } assign { } { } assign $0\ren_delay$17$next[7:0]$3056 $1\ren_delay$17$next[7:0]$3057 - attribute \src "libresoc.v:49775.5-49775.29" + attribute \src "libresoc.v:49827.5-49827.29" switch \initial - attribute \src "libresoc.v:49775.9-49775.17" + attribute \src "libresoc.v:49827.9-49827.17" case 1'1 case end @@ -86952,14 +86991,14 @@ module \cr sync always update \ren_delay$17$next $0\ren_delay$17$next[7:0]$3056 end - attribute \src "libresoc.v:49783.3-49792.6" - process $proc$libresoc.v:49783$3058 + attribute \src "libresoc.v:49835.3-49844.6" + process $proc$libresoc.v:49835$3058 assign { } { } assign { } { } assign $0\src1__data_o[3:0] $1\src1__data_o[3:0] - attribute \src "libresoc.v:49784.5-49784.29" + attribute \src "libresoc.v:49836.5-49836.29" switch \initial - attribute \src "libresoc.v:49784.9-49784.17" + attribute \src "libresoc.v:49836.9-49836.17" case 1'1 case end @@ -86975,14 +87014,14 @@ module \cr sync always update \src1__data_o $0\src1__data_o[3:0] end - attribute \src "libresoc.v:49793.3-49801.6" - process $proc$libresoc.v:49793$3059 + attribute \src "libresoc.v:49845.3-49853.6" + process $proc$libresoc.v:49845$3059 assign { } { } assign { } { } assign $0\ren_delay$34$next[7:0]$3060 $1\ren_delay$34$next[7:0]$3061 - attribute \src "libresoc.v:49794.5-49794.29" + attribute \src "libresoc.v:49846.5-49846.29" switch \initial - attribute \src "libresoc.v:49794.9-49794.17" + attribute \src "libresoc.v:49846.9-49846.17" case 1'1 case end @@ -86998,14 +87037,14 @@ module \cr sync always update \ren_delay$34$next $0\ren_delay$34$next[7:0]$3060 end - attribute \src "libresoc.v:49802.3-49811.6" - process $proc$libresoc.v:49802$3062 + attribute \src "libresoc.v:49854.3-49863.6" + process $proc$libresoc.v:49854$3062 assign { } { } assign { } { } assign $0\src2__data_o[3:0] $1\src2__data_o[3:0] - attribute \src "libresoc.v:49803.5-49803.29" + attribute \src "libresoc.v:49855.5-49855.29" switch \initial - attribute \src "libresoc.v:49803.9-49803.17" + attribute \src "libresoc.v:49855.9-49855.17" case 1'1 case end @@ -87021,14 +87060,14 @@ module \cr sync always update \src2__data_o $0\src2__data_o[3:0] end - attribute \src "libresoc.v:49812.3-49820.6" - process $proc$libresoc.v:49812$3063 + attribute \src "libresoc.v:49864.3-49872.6" + process $proc$libresoc.v:49864$3063 assign { } { } assign { } { } assign $0\ren_delay$51$next[7:0]$3064 $1\ren_delay$51$next[7:0]$3065 - attribute \src "libresoc.v:49813.5-49813.29" + attribute \src "libresoc.v:49865.5-49865.29" switch \initial - attribute \src "libresoc.v:49813.9-49813.17" + attribute \src "libresoc.v:49865.9-49865.17" case 1'1 case end @@ -87044,14 +87083,14 @@ module \cr sync always update \ren_delay$51$next $0\ren_delay$51$next[7:0]$3064 end - attribute \src "libresoc.v:49821.3-49830.6" - process $proc$libresoc.v:49821$3066 + attribute \src "libresoc.v:49873.3-49882.6" + process $proc$libresoc.v:49873$3066 assign { } { } assign { } { } assign $0\src3__data_o[3:0] $1\src3__data_o[3:0] - attribute \src "libresoc.v:49822.5-49822.29" + attribute \src "libresoc.v:49874.5-49874.29" switch \initial - attribute \src "libresoc.v:49822.9-49822.17" + attribute \src "libresoc.v:49874.9-49874.17" case 1'1 case end @@ -87067,14 +87106,14 @@ module \cr sync always update \src3__data_o $0\src3__data_o[3:0] end - attribute \src "libresoc.v:49831.3-49839.6" - process $proc$libresoc.v:49831$3067 + attribute \src "libresoc.v:49883.3-49891.6" + process $proc$libresoc.v:49883$3067 assign { } { } assign { } { } assign $0\ren_delay$next[7:0]$3068 $1\ren_delay$next[7:0]$3069 - attribute \src "libresoc.v:49832.5-49832.29" + attribute \src "libresoc.v:49884.5-49884.29" switch \initial - attribute \src "libresoc.v:49832.9-49832.17" + attribute \src "libresoc.v:49884.9-49884.17" case 1'1 case end @@ -87090,14 +87129,14 @@ module \cr sync always update \ren_delay$next $0\ren_delay$next[7:0]$3068 end - attribute \src "libresoc.v:49840.3-49849.6" - process $proc$libresoc.v:49840$3070 + attribute \src "libresoc.v:49892.3-49901.6" + process $proc$libresoc.v:49892$3070 assign { } { } assign { } { } assign $0\cr_pred__data_o[3:0] $1\cr_pred__data_o[3:0] - attribute \src "libresoc.v:49841.5-49841.29" + attribute \src "libresoc.v:49893.5-49893.29" switch \initial - attribute \src "libresoc.v:49841.9-49841.17" + attribute \src "libresoc.v:49893.9-49893.17" case 1'1 case end @@ -87113,38 +87152,38 @@ module \cr sync always update \cr_pred__data_o $0\cr_pred__data_o[3:0] end - connect \$9 $or$libresoc.v:49558$3016_Y - connect \$11 $or$libresoc.v:49559$3017_Y - connect \$13 $or$libresoc.v:49560$3018_Y - connect \$15 $or$libresoc.v:49561$3019_Y - connect \$18 $reduce_or$libresoc.v:49562$3020_Y - connect \$1 $reduce_or$libresoc.v:49563$3021_Y - connect \$20 $or$libresoc.v:49564$3022_Y - connect \$22 $or$libresoc.v:49565$3023_Y - connect \$24 $or$libresoc.v:49566$3024_Y - connect \$26 $or$libresoc.v:49567$3025_Y - connect \$28 $or$libresoc.v:49568$3026_Y - connect \$30 $or$libresoc.v:49569$3027_Y - connect \$32 $or$libresoc.v:49570$3028_Y - connect \$35 $reduce_or$libresoc.v:49571$3029_Y - connect \$37 $or$libresoc.v:49572$3030_Y - connect \$3 $or$libresoc.v:49573$3031_Y - connect \$39 $or$libresoc.v:49574$3032_Y - connect \$41 $or$libresoc.v:49575$3033_Y - connect \$43 $or$libresoc.v:49576$3034_Y - connect \$45 $or$libresoc.v:49577$3035_Y - connect \$47 $or$libresoc.v:49578$3036_Y - connect \$49 $or$libresoc.v:49579$3037_Y - connect \$52 $reduce_or$libresoc.v:49580$3038_Y - connect \$54 $or$libresoc.v:49581$3039_Y - connect \$56 $or$libresoc.v:49582$3040_Y - connect \$58 $or$libresoc.v:49583$3041_Y - connect \$5 $or$libresoc.v:49584$3042_Y - connect \$60 $or$libresoc.v:49585$3043_Y - connect \$62 $or$libresoc.v:49586$3044_Y - connect \$64 $or$libresoc.v:49587$3045_Y - connect \$66 $or$libresoc.v:49588$3046_Y - connect \$7 $or$libresoc.v:49589$3047_Y + connect \$9 $or$libresoc.v:49610$3016_Y + connect \$11 $or$libresoc.v:49611$3017_Y + connect \$13 $or$libresoc.v:49612$3018_Y + connect \$15 $or$libresoc.v:49613$3019_Y + connect \$18 $reduce_or$libresoc.v:49614$3020_Y + connect \$1 $reduce_or$libresoc.v:49615$3021_Y + connect \$20 $or$libresoc.v:49616$3022_Y + connect \$22 $or$libresoc.v:49617$3023_Y + connect \$24 $or$libresoc.v:49618$3024_Y + connect \$26 $or$libresoc.v:49619$3025_Y + connect \$28 $or$libresoc.v:49620$3026_Y + connect \$30 $or$libresoc.v:49621$3027_Y + connect \$32 $or$libresoc.v:49622$3028_Y + connect \$35 $reduce_or$libresoc.v:49623$3029_Y + connect \$37 $or$libresoc.v:49624$3030_Y + connect \$3 $or$libresoc.v:49625$3031_Y + connect \$39 $or$libresoc.v:49626$3032_Y + connect \$41 $or$libresoc.v:49627$3033_Y + connect \$43 $or$libresoc.v:49628$3034_Y + connect \$45 $or$libresoc.v:49629$3035_Y + connect \$47 $or$libresoc.v:49630$3036_Y + connect \$49 $or$libresoc.v:49631$3037_Y + connect \$52 $reduce_or$libresoc.v:49632$3038_Y + connect \$54 $or$libresoc.v:49633$3039_Y + connect \$56 $or$libresoc.v:49634$3040_Y + connect \$58 $or$libresoc.v:49635$3041_Y + connect \$5 $or$libresoc.v:49636$3042_Y + connect \$60 $or$libresoc.v:49637$3043_Y + connect \$62 $or$libresoc.v:49638$3044_Y + connect \$64 $or$libresoc.v:49639$3045_Y + connect \$66 $or$libresoc.v:49640$3046_Y + connect \$7 $or$libresoc.v:49641$3047_Y connect \cr_pred__ren 8'00000000 connect \wen$68 8'00000000 connect \data_i$69 4'0000 @@ -87177,393 +87216,393 @@ module \cr connect { \reg_7_src17__ren \reg_6_src16__ren \reg_5_src15__ren \reg_4_src14__ren \reg_3_src13__ren \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren connect { \reg_7_cr_pred7__ren \reg_6_cr_pred6__ren \reg_5_cr_pred5__ren \reg_4_cr_pred4__ren \reg_3_cr_pred3__ren \reg_2_cr_pred2__ren \reg_1_cr_pred1__ren \reg_0_cr_pred0__ren } 8'00000000 end -attribute \src "libresoc.v:49885.1-50942.10" +attribute \src "libresoc.v:49937.1-50994.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0" attribute \generator "nMigen" module \cr0 - attribute \src "libresoc.v:50543.3-50544.25" + attribute \src "libresoc.v:50595.3-50596.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:50716.3-50727.6" + attribute \src "libresoc.v:50768.3-50779.6" wire width 14 $0\alu_cr0_cr_op__fn_unit$next[13:0]$3198 - attribute \src "libresoc.v:50515.3-50516.61" + attribute \src "libresoc.v:50567.3-50568.61" wire width 14 $0\alu_cr0_cr_op__fn_unit[13:0] - attribute \src "libresoc.v:50716.3-50727.6" + attribute \src "libresoc.v:50768.3-50779.6" wire width 32 $0\alu_cr0_cr_op__insn$next[31:0]$3199 - attribute \src "libresoc.v:50517.3-50518.55" + attribute \src "libresoc.v:50569.3-50570.55" wire width 32 $0\alu_cr0_cr_op__insn[31:0] - attribute \src "libresoc.v:50716.3-50727.6" + attribute \src "libresoc.v:50768.3-50779.6" wire width 7 $0\alu_cr0_cr_op__insn_type$next[6:0]$3200 - attribute \src "libresoc.v:50513.3-50514.65" + attribute \src "libresoc.v:50565.3-50566.65" wire width 7 $0\alu_cr0_cr_op__insn_type[6:0] - attribute \src "libresoc.v:50541.3-50542.39" + attribute \src "libresoc.v:50593.3-50594.39" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:50863.3-50871.6" + attribute \src "libresoc.v:50915.3-50923.6" wire $0\alu_l_r_alu$next[0:0]$3250 - attribute \src "libresoc.v:50485.3-50486.39" + attribute \src "libresoc.v:50537.3-50538.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:50854.3-50862.6" + attribute \src "libresoc.v:50906.3-50914.6" wire $0\alui_l_r_alui$next[0:0]$3247 - attribute \src "libresoc.v:50487.3-50488.43" + attribute \src "libresoc.v:50539.3-50540.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:50728.3-50749.6" + attribute \src "libresoc.v:50780.3-50801.6" wire width 64 $0\data_r0__o$next[63:0]$3205 - attribute \src "libresoc.v:50509.3-50510.37" + attribute \src "libresoc.v:50561.3-50562.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:50728.3-50749.6" + attribute \src "libresoc.v:50780.3-50801.6" wire $0\data_r0__o_ok$next[0:0]$3206 - attribute \src "libresoc.v:50511.3-50512.43" + attribute \src "libresoc.v:50563.3-50564.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:50750.3-50771.6" + attribute \src "libresoc.v:50802.3-50823.6" wire width 32 $0\data_r1__full_cr$next[31:0]$3213 - attribute \src "libresoc.v:50505.3-50506.49" + attribute \src "libresoc.v:50557.3-50558.49" wire width 32 $0\data_r1__full_cr[31:0] - attribute \src "libresoc.v:50750.3-50771.6" + attribute \src "libresoc.v:50802.3-50823.6" wire $0\data_r1__full_cr_ok$next[0:0]$3214 - attribute \src "libresoc.v:50507.3-50508.55" + attribute \src "libresoc.v:50559.3-50560.55" wire $0\data_r1__full_cr_ok[0:0] - attribute \src "libresoc.v:50772.3-50793.6" + attribute \src "libresoc.v:50824.3-50845.6" wire width 4 $0\data_r2__cr_a$next[3:0]$3221 - attribute \src "libresoc.v:50501.3-50502.43" + attribute \src "libresoc.v:50553.3-50554.43" wire width 4 $0\data_r2__cr_a[3:0] - attribute \src "libresoc.v:50772.3-50793.6" + attribute \src "libresoc.v:50824.3-50845.6" wire $0\data_r2__cr_a_ok$next[0:0]$3222 - attribute \src "libresoc.v:50503.3-50504.49" + attribute \src "libresoc.v:50555.3-50556.49" wire $0\data_r2__cr_a_ok[0:0] - attribute \src "libresoc.v:50872.3-50881.6" + attribute \src "libresoc.v:50924.3-50933.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:50882.3-50891.6" + attribute \src "libresoc.v:50934.3-50943.6" wire width 32 $0\dest2_o[31:0] - attribute \src "libresoc.v:50892.3-50901.6" + attribute \src "libresoc.v:50944.3-50953.6" wire width 4 $0\dest3_o[3:0] - attribute \src "libresoc.v:49886.7-49886.20" + attribute \src "libresoc.v:49938.7-49938.20" wire $0\initial[0:0] - attribute \src "libresoc.v:50671.3-50679.6" + attribute \src "libresoc.v:50723.3-50731.6" wire $0\opc_l_r_opc$next[0:0]$3183 - attribute \src "libresoc.v:50527.3-50528.39" + attribute \src "libresoc.v:50579.3-50580.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:50662.3-50670.6" + attribute \src "libresoc.v:50714.3-50722.6" wire $0\opc_l_s_opc$next[0:0]$3180 - attribute \src "libresoc.v:50529.3-50530.39" + attribute \src "libresoc.v:50581.3-50582.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:50902.3-50910.6" + attribute \src "libresoc.v:50954.3-50962.6" wire width 3 $0\prev_wr_go$next[2:0]$3256 - attribute \src "libresoc.v:50539.3-50540.37" + attribute \src "libresoc.v:50591.3-50592.37" wire width 3 $0\prev_wr_go[2:0] - attribute \src "libresoc.v:50616.3-50625.6" + attribute \src "libresoc.v:50668.3-50677.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:50707.3-50715.6" + attribute \src "libresoc.v:50759.3-50767.6" wire width 3 $0\req_l_r_req$next[2:0]$3195 - attribute \src "libresoc.v:50519.3-50520.39" + attribute \src "libresoc.v:50571.3-50572.39" wire width 3 $0\req_l_r_req[2:0] - attribute \src "libresoc.v:50698.3-50706.6" + attribute \src "libresoc.v:50750.3-50758.6" wire width 3 $0\req_l_s_req$next[2:0]$3192 - attribute \src "libresoc.v:50521.3-50522.39" + attribute \src "libresoc.v:50573.3-50574.39" wire width 3 $0\req_l_s_req[2:0] - attribute \src "libresoc.v:50635.3-50643.6" + attribute \src "libresoc.v:50687.3-50695.6" wire $0\rok_l_r_rdok$next[0:0]$3171 - attribute \src "libresoc.v:50535.3-50536.41" + attribute \src "libresoc.v:50587.3-50588.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:50626.3-50634.6" + attribute \src "libresoc.v:50678.3-50686.6" wire $0\rok_l_s_rdok$next[0:0]$3168 - attribute \src "libresoc.v:50537.3-50538.41" + attribute \src "libresoc.v:50589.3-50590.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:50653.3-50661.6" + attribute \src "libresoc.v:50705.3-50713.6" wire $0\rst_l_r_rst$next[0:0]$3177 - attribute \src "libresoc.v:50531.3-50532.39" + attribute \src "libresoc.v:50583.3-50584.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:50644.3-50652.6" + attribute \src "libresoc.v:50696.3-50704.6" wire $0\rst_l_s_rst$next[0:0]$3174 - attribute \src "libresoc.v:50533.3-50534.39" + attribute \src "libresoc.v:50585.3-50586.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:50689.3-50697.6" + attribute \src "libresoc.v:50741.3-50749.6" wire width 6 $0\src_l_r_src$next[5:0]$3189 - attribute \src "libresoc.v:50523.3-50524.39" + attribute \src "libresoc.v:50575.3-50576.39" wire width 6 $0\src_l_r_src[5:0] - attribute \src "libresoc.v:50680.3-50688.6" + attribute \src "libresoc.v:50732.3-50740.6" wire width 6 $0\src_l_s_src$next[5:0]$3186 - attribute \src "libresoc.v:50525.3-50526.39" + attribute \src "libresoc.v:50577.3-50578.39" wire width 6 $0\src_l_s_src[5:0] - attribute \src "libresoc.v:50794.3-50803.6" + attribute \src "libresoc.v:50846.3-50855.6" wire width 64 $0\src_r0$next[63:0]$3229 - attribute \src "libresoc.v:50499.3-50500.29" + attribute \src "libresoc.v:50551.3-50552.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:50804.3-50813.6" + attribute \src "libresoc.v:50856.3-50865.6" wire width 64 $0\src_r1$next[63:0]$3232 - attribute \src "libresoc.v:50497.3-50498.29" + attribute \src "libresoc.v:50549.3-50550.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:50814.3-50823.6" + attribute \src "libresoc.v:50866.3-50875.6" wire width 32 $0\src_r2$next[31:0]$3235 - attribute \src "libresoc.v:50495.3-50496.29" + attribute \src "libresoc.v:50547.3-50548.29" wire width 32 $0\src_r2[31:0] - attribute \src "libresoc.v:50824.3-50833.6" + attribute \src "libresoc.v:50876.3-50885.6" wire width 4 $0\src_r3$next[3:0]$3238 - attribute \src "libresoc.v:50493.3-50494.29" + attribute \src "libresoc.v:50545.3-50546.29" wire width 4 $0\src_r3[3:0] - attribute \src "libresoc.v:50834.3-50843.6" + attribute \src "libresoc.v:50886.3-50895.6" wire width 4 $0\src_r4$next[3:0]$3241 - attribute \src "libresoc.v:50491.3-50492.29" + attribute \src "libresoc.v:50543.3-50544.29" wire width 4 $0\src_r4[3:0] - attribute \src "libresoc.v:50844.3-50853.6" + attribute \src "libresoc.v:50896.3-50905.6" wire width 4 $0\src_r5$next[3:0]$3244 - attribute \src "libresoc.v:50489.3-50490.29" + attribute \src "libresoc.v:50541.3-50542.29" wire width 4 $0\src_r5[3:0] - attribute \src "libresoc.v:50004.7-50004.24" + attribute \src "libresoc.v:50056.7-50056.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:50716.3-50727.6" + attribute \src "libresoc.v:50768.3-50779.6" wire width 14 $1\alu_cr0_cr_op__fn_unit$next[13:0]$3201 - attribute \src "libresoc.v:50035.14-50035.47" + attribute \src "libresoc.v:50087.14-50087.47" wire width 14 $1\alu_cr0_cr_op__fn_unit[13:0] - attribute \src "libresoc.v:50716.3-50727.6" + attribute \src "libresoc.v:50768.3-50779.6" wire width 32 $1\alu_cr0_cr_op__insn$next[31:0]$3202 - attribute \src "libresoc.v:50039.14-50039.41" + attribute \src "libresoc.v:50091.14-50091.41" wire width 32 $1\alu_cr0_cr_op__insn[31:0] - attribute \src "libresoc.v:50716.3-50727.6" + attribute \src "libresoc.v:50768.3-50779.6" wire width 7 $1\alu_cr0_cr_op__insn_type$next[6:0]$3203 - attribute \src "libresoc.v:50118.13-50118.45" + attribute \src "libresoc.v:50170.13-50170.45" wire width 7 $1\alu_cr0_cr_op__insn_type[6:0] - attribute \src "libresoc.v:50142.7-50142.26" + attribute \src "libresoc.v:50194.7-50194.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:50863.3-50871.6" + attribute \src "libresoc.v:50915.3-50923.6" wire $1\alu_l_r_alu$next[0:0]$3251 - attribute \src "libresoc.v:50150.7-50150.25" + attribute \src "libresoc.v:50202.7-50202.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:50854.3-50862.6" + attribute \src "libresoc.v:50906.3-50914.6" wire $1\alui_l_r_alui$next[0:0]$3248 - attribute \src "libresoc.v:50162.7-50162.27" + attribute \src "libresoc.v:50214.7-50214.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:50728.3-50749.6" + attribute \src "libresoc.v:50780.3-50801.6" wire width 64 $1\data_r0__o$next[63:0]$3207 - attribute \src "libresoc.v:50196.14-50196.47" + attribute \src "libresoc.v:50248.14-50248.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:50728.3-50749.6" + attribute \src "libresoc.v:50780.3-50801.6" wire $1\data_r0__o_ok$next[0:0]$3208 - attribute \src "libresoc.v:50200.7-50200.27" + attribute \src "libresoc.v:50252.7-50252.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:50750.3-50771.6" + attribute \src "libresoc.v:50802.3-50823.6" wire width 32 $1\data_r1__full_cr$next[31:0]$3215 - attribute \src "libresoc.v:50204.14-50204.38" + attribute \src "libresoc.v:50256.14-50256.38" wire width 32 $1\data_r1__full_cr[31:0] - attribute \src "libresoc.v:50750.3-50771.6" + attribute \src "libresoc.v:50802.3-50823.6" wire $1\data_r1__full_cr_ok$next[0:0]$3216 - attribute \src "libresoc.v:50208.7-50208.33" + attribute \src "libresoc.v:50260.7-50260.33" wire $1\data_r1__full_cr_ok[0:0] - attribute \src "libresoc.v:50772.3-50793.6" + attribute \src "libresoc.v:50824.3-50845.6" wire width 4 $1\data_r2__cr_a$next[3:0]$3223 - attribute \src "libresoc.v:50212.13-50212.33" + attribute \src "libresoc.v:50264.13-50264.33" wire width 4 $1\data_r2__cr_a[3:0] - attribute \src "libresoc.v:50772.3-50793.6" + attribute \src "libresoc.v:50824.3-50845.6" wire $1\data_r2__cr_a_ok$next[0:0]$3224 - attribute \src "libresoc.v:50216.7-50216.30" + attribute \src "libresoc.v:50268.7-50268.30" wire $1\data_r2__cr_a_ok[0:0] - attribute \src "libresoc.v:50872.3-50881.6" + attribute \src "libresoc.v:50924.3-50933.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:50882.3-50891.6" + attribute \src "libresoc.v:50934.3-50943.6" wire width 32 $1\dest2_o[31:0] - attribute \src "libresoc.v:50892.3-50901.6" + attribute \src "libresoc.v:50944.3-50953.6" wire width 4 $1\dest3_o[3:0] - attribute \src "libresoc.v:50671.3-50679.6" + attribute \src "libresoc.v:50723.3-50731.6" wire $1\opc_l_r_opc$next[0:0]$3184 - attribute \src "libresoc.v:50235.7-50235.25" + attribute \src "libresoc.v:50287.7-50287.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:50662.3-50670.6" + attribute \src "libresoc.v:50714.3-50722.6" wire $1\opc_l_s_opc$next[0:0]$3181 - attribute \src "libresoc.v:50239.7-50239.25" + attribute \src "libresoc.v:50291.7-50291.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:50902.3-50910.6" + attribute \src "libresoc.v:50954.3-50962.6" wire width 3 $1\prev_wr_go$next[2:0]$3257 - attribute \src "libresoc.v:50339.13-50339.30" + attribute \src "libresoc.v:50391.13-50391.30" wire width 3 $1\prev_wr_go[2:0] - attribute \src "libresoc.v:50616.3-50625.6" + attribute \src "libresoc.v:50668.3-50677.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:50707.3-50715.6" + attribute \src "libresoc.v:50759.3-50767.6" wire width 3 $1\req_l_r_req$next[2:0]$3196 - attribute \src "libresoc.v:50347.13-50347.31" + attribute \src "libresoc.v:50399.13-50399.31" wire width 3 $1\req_l_r_req[2:0] - attribute \src "libresoc.v:50698.3-50706.6" + attribute \src "libresoc.v:50750.3-50758.6" wire width 3 $1\req_l_s_req$next[2:0]$3193 - attribute \src "libresoc.v:50351.13-50351.31" + attribute \src "libresoc.v:50403.13-50403.31" wire width 3 $1\req_l_s_req[2:0] - attribute \src "libresoc.v:50635.3-50643.6" + attribute \src "libresoc.v:50687.3-50695.6" wire $1\rok_l_r_rdok$next[0:0]$3172 - attribute \src "libresoc.v:50363.7-50363.26" + attribute \src "libresoc.v:50415.7-50415.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:50626.3-50634.6" + attribute \src "libresoc.v:50678.3-50686.6" wire $1\rok_l_s_rdok$next[0:0]$3169 - attribute \src "libresoc.v:50367.7-50367.26" + attribute \src "libresoc.v:50419.7-50419.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:50653.3-50661.6" + attribute \src "libresoc.v:50705.3-50713.6" wire $1\rst_l_r_rst$next[0:0]$3178 - attribute \src "libresoc.v:50371.7-50371.25" + attribute \src "libresoc.v:50423.7-50423.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:50644.3-50652.6" + attribute \src "libresoc.v:50696.3-50704.6" wire $1\rst_l_s_rst$next[0:0]$3175 - attribute \src "libresoc.v:50375.7-50375.25" + attribute \src "libresoc.v:50427.7-50427.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:50689.3-50697.6" + attribute \src "libresoc.v:50741.3-50749.6" wire width 6 $1\src_l_r_src$next[5:0]$3190 - attribute \src "libresoc.v:50395.13-50395.32" + attribute \src "libresoc.v:50447.13-50447.32" wire width 6 $1\src_l_r_src[5:0] - attribute \src "libresoc.v:50680.3-50688.6" + attribute \src "libresoc.v:50732.3-50740.6" wire width 6 $1\src_l_s_src$next[5:0]$3187 - attribute \src "libresoc.v:50399.13-50399.32" + attribute \src "libresoc.v:50451.13-50451.32" wire width 6 $1\src_l_s_src[5:0] - attribute \src "libresoc.v:50794.3-50803.6" + attribute \src "libresoc.v:50846.3-50855.6" wire width 64 $1\src_r0$next[63:0]$3230 - attribute \src "libresoc.v:50403.14-50403.43" + attribute \src "libresoc.v:50455.14-50455.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:50804.3-50813.6" + attribute \src "libresoc.v:50856.3-50865.6" wire width 64 $1\src_r1$next[63:0]$3233 - attribute \src "libresoc.v:50407.14-50407.43" + attribute \src "libresoc.v:50459.14-50459.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:50814.3-50823.6" + attribute \src "libresoc.v:50866.3-50875.6" wire width 32 $1\src_r2$next[31:0]$3236 - attribute \src "libresoc.v:50411.14-50411.28" + attribute \src "libresoc.v:50463.14-50463.28" wire width 32 $1\src_r2[31:0] - attribute \src "libresoc.v:50824.3-50833.6" + attribute \src "libresoc.v:50876.3-50885.6" wire width 4 $1\src_r3$next[3:0]$3239 - attribute \src "libresoc.v:50415.13-50415.26" + attribute \src "libresoc.v:50467.13-50467.26" wire width 4 $1\src_r3[3:0] - attribute \src "libresoc.v:50834.3-50843.6" + attribute \src "libresoc.v:50886.3-50895.6" wire width 4 $1\src_r4$next[3:0]$3242 - attribute \src "libresoc.v:50419.13-50419.26" + attribute \src "libresoc.v:50471.13-50471.26" wire width 4 $1\src_r4[3:0] - attribute \src "libresoc.v:50844.3-50853.6" + attribute \src "libresoc.v:50896.3-50905.6" wire width 4 $1\src_r5$next[3:0]$3245 - attribute \src "libresoc.v:50423.13-50423.26" + attribute \src "libresoc.v:50475.13-50475.26" wire width 4 $1\src_r5[3:0] - attribute \src "libresoc.v:50728.3-50749.6" + attribute \src "libresoc.v:50780.3-50801.6" wire width 64 $2\data_r0__o$next[63:0]$3209 - attribute \src "libresoc.v:50728.3-50749.6" + attribute \src "libresoc.v:50780.3-50801.6" wire $2\data_r0__o_ok$next[0:0]$3210 - attribute \src "libresoc.v:50750.3-50771.6" + attribute \src "libresoc.v:50802.3-50823.6" wire width 32 $2\data_r1__full_cr$next[31:0]$3217 - attribute \src "libresoc.v:50750.3-50771.6" + attribute \src "libresoc.v:50802.3-50823.6" wire $2\data_r1__full_cr_ok$next[0:0]$3218 - attribute \src "libresoc.v:50772.3-50793.6" + attribute \src "libresoc.v:50824.3-50845.6" wire width 4 $2\data_r2__cr_a$next[3:0]$3225 - attribute \src "libresoc.v:50772.3-50793.6" + attribute \src "libresoc.v:50824.3-50845.6" wire $2\data_r2__cr_a_ok$next[0:0]$3226 - attribute \src "libresoc.v:50728.3-50749.6" + attribute \src "libresoc.v:50780.3-50801.6" wire $3\data_r0__o_ok$next[0:0]$3211 - attribute \src "libresoc.v:50750.3-50771.6" + attribute \src "libresoc.v:50802.3-50823.6" wire $3\data_r1__full_cr_ok$next[0:0]$3219 - attribute \src "libresoc.v:50772.3-50793.6" + attribute \src "libresoc.v:50824.3-50845.6" wire $3\data_r2__cr_a_ok$next[0:0]$3227 - attribute \src "libresoc.v:50429.18-50429.112" - wire width 6 $and$libresoc.v:50429$3080_Y - attribute \src "libresoc.v:50430.19-50430.125" - wire $and$libresoc.v:50430$3081_Y - attribute \src "libresoc.v:50431.19-50431.125" - wire $and$libresoc.v:50431$3082_Y - attribute \src "libresoc.v:50432.19-50432.125" - wire $and$libresoc.v:50432$3083_Y - attribute \src "libresoc.v:50433.19-50433.141" - wire width 3 $and$libresoc.v:50433$3084_Y - attribute \src "libresoc.v:50434.19-50434.121" - wire width 3 $and$libresoc.v:50434$3085_Y - attribute \src "libresoc.v:50435.19-50435.127" - wire $and$libresoc.v:50435$3086_Y - attribute \src "libresoc.v:50436.19-50436.127" - wire $and$libresoc.v:50436$3087_Y - attribute \src "libresoc.v:50437.19-50437.127" - wire $and$libresoc.v:50437$3088_Y - attribute \src "libresoc.v:50438.18-50438.110" - wire $and$libresoc.v:50438$3089_Y - attribute \src "libresoc.v:50440.18-50440.98" - wire $and$libresoc.v:50440$3091_Y - attribute \src "libresoc.v:50442.18-50442.100" - wire $and$libresoc.v:50442$3093_Y - attribute \src "libresoc.v:50443.18-50443.149" - wire width 3 $and$libresoc.v:50443$3094_Y - attribute \src "libresoc.v:50445.18-50445.119" - wire width 3 $and$libresoc.v:50445$3096_Y - attribute \src "libresoc.v:50448.18-50448.116" - wire $and$libresoc.v:50448$3099_Y - attribute \src "libresoc.v:50452.17-50452.123" - wire $and$libresoc.v:50452$3103_Y - attribute \src "libresoc.v:50454.18-50454.113" - wire $and$libresoc.v:50454$3105_Y - attribute \src "libresoc.v:50455.18-50455.125" - wire width 3 $and$libresoc.v:50455$3106_Y - attribute \src "libresoc.v:50457.18-50457.112" - wire $and$libresoc.v:50457$3108_Y - attribute \src "libresoc.v:50459.18-50459.125" - wire $and$libresoc.v:50459$3110_Y - attribute \src "libresoc.v:50460.18-50460.125" - wire $and$libresoc.v:50460$3111_Y - attribute \src "libresoc.v:50461.18-50461.117" - wire $and$libresoc.v:50461$3112_Y - attribute \src "libresoc.v:50466.18-50466.129" - wire $and$libresoc.v:50466$3117_Y - attribute \src "libresoc.v:50467.18-50467.124" - wire width 3 $and$libresoc.v:50467$3118_Y - attribute \src "libresoc.v:50470.18-50470.116" - wire $and$libresoc.v:50470$3121_Y - attribute \src "libresoc.v:50471.18-50471.122" - wire $and$libresoc.v:50471$3122_Y - attribute \src "libresoc.v:50472.18-50472.119" - wire $and$libresoc.v:50472$3123_Y - attribute \src "libresoc.v:50480.18-50480.133" - wire $and$libresoc.v:50480$3131_Y - attribute \src "libresoc.v:50481.18-50481.131" - wire $and$libresoc.v:50481$3132_Y - attribute \src "libresoc.v:50482.18-50482.182" - wire width 6 $and$libresoc.v:50482$3133_Y - attribute \src "libresoc.v:50483.18-50483.113" - wire width 6 $and$libresoc.v:50483$3134_Y - attribute \src "libresoc.v:50456.18-50456.113" - wire $eq$libresoc.v:50456$3107_Y - attribute \src "libresoc.v:50458.18-50458.119" - wire $eq$libresoc.v:50458$3109_Y - attribute \src "libresoc.v:50439.18-50439.97" - wire $not$libresoc.v:50439$3090_Y - attribute \src "libresoc.v:50441.18-50441.99" - wire $not$libresoc.v:50441$3092_Y - attribute \src "libresoc.v:50444.18-50444.113" - wire width 3 $not$libresoc.v:50444$3095_Y - attribute \src "libresoc.v:50447.18-50447.106" - wire $not$libresoc.v:50447$3098_Y - attribute \src "libresoc.v:50453.18-50453.119" - wire $not$libresoc.v:50453$3104_Y - attribute \src "libresoc.v:50468.17-50468.113" - wire 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$reduce_or$libresoc.v:50449$3100_Y - attribute \src "libresoc.v:50450.18-50450.112" - wire $reduce_or$libresoc.v:50450$3101_Y - attribute \src "libresoc.v:50473.18-50473.118" - wire width 64 $ternary$libresoc.v:50473$3124_Y - attribute \src "libresoc.v:50474.18-50474.118" - wire width 64 $ternary$libresoc.v:50474$3125_Y - attribute \src "libresoc.v:50475.18-50475.118" - wire width 32 $ternary$libresoc.v:50475$3126_Y - attribute \src "libresoc.v:50476.18-50476.118" - wire width 4 $ternary$libresoc.v:50476$3127_Y - attribute \src "libresoc.v:50477.18-50477.118" - wire width 4 $ternary$libresoc.v:50477$3128_Y - attribute \src "libresoc.v:50478.18-50478.118" - wire width 4 $ternary$libresoc.v:50478$3129_Y + attribute \src "libresoc.v:50481.18-50481.112" + wire width 6 $and$libresoc.v:50481$3080_Y + attribute \src "libresoc.v:50482.19-50482.125" + wire $and$libresoc.v:50482$3081_Y + attribute \src "libresoc.v:50483.19-50483.125" + wire $and$libresoc.v:50483$3082_Y + attribute \src "libresoc.v:50484.19-50484.125" + wire $and$libresoc.v:50484$3083_Y + attribute \src "libresoc.v:50485.19-50485.141" + wire width 3 $and$libresoc.v:50485$3084_Y + attribute \src "libresoc.v:50486.19-50486.121" + wire width 3 $and$libresoc.v:50486$3085_Y + attribute \src "libresoc.v:50487.19-50487.127" + wire $and$libresoc.v:50487$3086_Y + attribute \src "libresoc.v:50488.19-50488.127" + wire $and$libresoc.v:50488$3087_Y + attribute \src "libresoc.v:50489.19-50489.127" + wire $and$libresoc.v:50489$3088_Y + attribute \src "libresoc.v:50490.18-50490.110" + wire $and$libresoc.v:50490$3089_Y + attribute \src "libresoc.v:50492.18-50492.98" + wire $and$libresoc.v:50492$3091_Y + attribute \src "libresoc.v:50494.18-50494.100" + wire $and$libresoc.v:50494$3093_Y + attribute \src "libresoc.v:50495.18-50495.149" + wire width 3 $and$libresoc.v:50495$3094_Y + attribute \src "libresoc.v:50497.18-50497.119" + wire width 3 $and$libresoc.v:50497$3096_Y + attribute \src "libresoc.v:50500.18-50500.116" + wire $and$libresoc.v:50500$3099_Y + attribute \src "libresoc.v:50504.17-50504.123" + wire $and$libresoc.v:50504$3103_Y + attribute \src "libresoc.v:50506.18-50506.113" + wire $and$libresoc.v:50506$3105_Y + attribute \src "libresoc.v:50507.18-50507.125" + wire width 3 $and$libresoc.v:50507$3106_Y + attribute \src "libresoc.v:50509.18-50509.112" + wire $and$libresoc.v:50509$3108_Y + attribute \src "libresoc.v:50511.18-50511.125" + wire $and$libresoc.v:50511$3110_Y + attribute \src "libresoc.v:50512.18-50512.125" + wire $and$libresoc.v:50512$3111_Y + attribute \src "libresoc.v:50513.18-50513.117" + wire $and$libresoc.v:50513$3112_Y + attribute \src "libresoc.v:50518.18-50518.129" + wire $and$libresoc.v:50518$3117_Y + attribute \src "libresoc.v:50519.18-50519.124" + wire width 3 $and$libresoc.v:50519$3118_Y + attribute \src "libresoc.v:50522.18-50522.116" + wire $and$libresoc.v:50522$3121_Y + attribute \src "libresoc.v:50523.18-50523.122" + wire $and$libresoc.v:50523$3122_Y + attribute \src "libresoc.v:50524.18-50524.119" + wire $and$libresoc.v:50524$3123_Y + attribute \src "libresoc.v:50532.18-50532.133" + wire $and$libresoc.v:50532$3131_Y + attribute \src "libresoc.v:50533.18-50533.131" + wire $and$libresoc.v:50533$3132_Y + attribute \src "libresoc.v:50534.18-50534.182" + wire width 6 $and$libresoc.v:50534$3133_Y + attribute \src "libresoc.v:50535.18-50535.113" + wire width 6 $and$libresoc.v:50535$3134_Y + attribute \src "libresoc.v:50508.18-50508.113" + wire $eq$libresoc.v:50508$3107_Y + attribute \src "libresoc.v:50510.18-50510.119" + wire $eq$libresoc.v:50510$3109_Y + attribute \src "libresoc.v:50491.18-50491.97" + wire $not$libresoc.v:50491$3090_Y + attribute \src "libresoc.v:50493.18-50493.99" + wire $not$libresoc.v:50493$3092_Y + attribute \src "libresoc.v:50496.18-50496.113" + wire width 3 $not$libresoc.v:50496$3095_Y + attribute \src "libresoc.v:50499.18-50499.106" + wire $not$libresoc.v:50499$3098_Y + attribute \src "libresoc.v:50505.18-50505.119" + wire $not$libresoc.v:50505$3104_Y + attribute \src "libresoc.v:50520.17-50520.113" + wire width 6 $not$libresoc.v:50520$3119_Y + attribute \src "libresoc.v:50536.18-50536.114" + wire width 6 $not$libresoc.v:50536$3135_Y + attribute \src "libresoc.v:50503.18-50503.112" + wire $or$libresoc.v:50503$3102_Y + attribute \src "libresoc.v:50514.18-50514.122" + wire $or$libresoc.v:50514$3113_Y + attribute \src "libresoc.v:50515.18-50515.124" + wire $or$libresoc.v:50515$3114_Y + attribute \src "libresoc.v:50516.18-50516.155" + wire width 3 $or$libresoc.v:50516$3115_Y + attribute \src "libresoc.v:50517.18-50517.194" + wire width 6 $or$libresoc.v:50517$3116_Y + attribute \src "libresoc.v:50521.18-50521.120" + wire width 3 $or$libresoc.v:50521$3120_Y + attribute \src "libresoc.v:50531.17-50531.117" + wire width 6 $or$libresoc.v:50531$3130_Y + attribute \src "libresoc.v:50480.17-50480.104" + wire $reduce_and$libresoc.v:50480$3079_Y + attribute \src "libresoc.v:50498.18-50498.106" + wire $reduce_or$libresoc.v:50498$3097_Y + attribute \src "libresoc.v:50501.18-50501.113" + wire $reduce_or$libresoc.v:50501$3100_Y + attribute \src "libresoc.v:50502.18-50502.112" + wire $reduce_or$libresoc.v:50502$3101_Y + attribute \src "libresoc.v:50525.18-50525.118" + wire width 64 $ternary$libresoc.v:50525$3124_Y + attribute \src "libresoc.v:50526.18-50526.118" + wire width 64 $ternary$libresoc.v:50526$3125_Y + attribute \src "libresoc.v:50527.18-50527.118" + wire width 32 $ternary$libresoc.v:50527$3126_Y + attribute \src "libresoc.v:50528.18-50528.118" + wire width 4 $ternary$libresoc.v:50528$3127_Y + attribute \src "libresoc.v:50529.18-50529.118" + wire width 4 $ternary$libresoc.v:50529$3128_Y + attribute \src "libresoc.v:50530.18-50530.118" + wire width 4 $ternary$libresoc.v:50530$3129_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" @@ -87844,9 +87883,9 @@ module \cr0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 24 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 22 \cr_a_ok @@ -87904,7 +87943,7 @@ module \cr0 wire width 4 output 23 \dest3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 20 \full_cr_ok - attribute \src "libresoc.v:49886.7-49886.15" + attribute \src "libresoc.v:49938.7-49938.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 16 \o_ok @@ -88105,7 +88144,7 @@ module \cr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:50429$3080 + cell $and $and$libresoc.v:50481$3080 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -88113,10 +88152,10 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \$95 connect \B \$97 - connect \Y $and$libresoc.v:50429$3080_Y + connect \Y $and$libresoc.v:50481$3080_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:50430$3081 + cell $and $and$libresoc.v:50482$3081 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88124,10 +88163,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:50430$3081_Y + connect \Y $and$libresoc.v:50482$3081_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:50431$3082 + cell $and $and$libresoc.v:50483$3082 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88135,10 +88174,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:50431$3082_Y + connect \Y $and$libresoc.v:50483$3082_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:50432$3083 + cell $and $and$libresoc.v:50484$3083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88146,10 +88185,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:50432$3083_Y + connect \Y $and$libresoc.v:50484$3083_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:50433$3084 + cell $and $and$libresoc.v:50485$3084 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88157,10 +88196,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B { \$101 \$103 \$105 } - connect \Y $and$libresoc.v:50433$3084_Y + connect \Y $and$libresoc.v:50485$3084_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:50434$3085 + cell $and $and$libresoc.v:50486$3085 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88168,10 +88207,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \$107 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:50434$3085_Y + connect \Y $and$libresoc.v:50486$3085_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:50435$3086 + cell $and $and$libresoc.v:50487$3086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88179,10 +88218,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:50435$3086_Y + connect \Y $and$libresoc.v:50487$3086_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:50436$3087 + cell $and $and$libresoc.v:50488$3087 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88190,10 +88229,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:50436$3087_Y + connect \Y $and$libresoc.v:50488$3087_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:50437$3088 + cell $and $and$libresoc.v:50489$3088 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88201,10 +88240,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:50437$3088_Y + connect \Y $and$libresoc.v:50489$3088_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:50438$3089 + cell $and $and$libresoc.v:50490$3089 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88212,10 +88251,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 - connect \Y $and$libresoc.v:50438$3089_Y + connect \Y $and$libresoc.v:50490$3089_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:50440$3091 + cell $and $and$libresoc.v:50492$3091 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88223,10 +88262,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$13 - connect \Y $and$libresoc.v:50440$3091_Y + connect \Y $and$libresoc.v:50492$3091_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:50442$3093 + cell $and $and$libresoc.v:50494$3093 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88234,10 +88273,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$17 - connect \Y $and$libresoc.v:50442$3093_Y + connect \Y $and$libresoc.v:50494$3093_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:50443$3094 + cell $and $and$libresoc.v:50495$3094 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88245,10 +88284,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:50443$3094_Y + connect \Y $and$libresoc.v:50495$3094_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:50445$3096 + cell $and $and$libresoc.v:50497$3096 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88256,10 +88295,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \cu_wr__rel_o connect \B \$25 - connect \Y $and$libresoc.v:50445$3096_Y + connect \Y $and$libresoc.v:50497$3096_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:50448$3099 + cell $and $and$libresoc.v:50500$3099 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88267,10 +88306,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$23 - connect \Y $and$libresoc.v:50448$3099_Y + connect \Y $and$libresoc.v:50500$3099_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:50452$3103 + cell $and $and$libresoc.v:50504$3103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88278,10 +88317,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:50452$3103_Y + connect \Y $and$libresoc.v:50504$3103_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:50454$3105 + cell $and $and$libresoc.v:50506$3105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88289,10 +88328,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$39 - connect \Y $and$libresoc.v:50454$3105_Y + connect \Y $and$libresoc.v:50506$3105_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:50455$3106 + cell $and $and$libresoc.v:50507$3106 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88300,10 +88339,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:50455$3106_Y + connect \Y $and$libresoc.v:50507$3106_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:50457$3108 + cell $and $and$libresoc.v:50509$3108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88311,10 +88350,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$41 connect \B \$45 - connect \Y $and$libresoc.v:50457$3108_Y + connect \Y $and$libresoc.v:50509$3108_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:50459$3110 + cell $and $and$libresoc.v:50511$3110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88322,10 +88361,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_cr0_n_ready_i - connect \Y $and$libresoc.v:50459$3110_Y + connect \Y $and$libresoc.v:50511$3110_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:50460$3111 + cell $and $and$libresoc.v:50512$3111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88333,10 +88372,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$51 connect \B \alu_cr0_n_valid_o - connect \Y $and$libresoc.v:50460$3111_Y + connect \Y $and$libresoc.v:50512$3111_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:50461$3112 + cell $and $and$libresoc.v:50513$3112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88344,10 +88383,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$53 connect \B \cu_busy_o - connect \Y $and$libresoc.v:50461$3112_Y + connect \Y $and$libresoc.v:50513$3112_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:50466$3117 + cell $and $and$libresoc.v:50518$3117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88355,10 +88394,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \alu_cr0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:50466$3117_Y + connect \Y $and$libresoc.v:50518$3117_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:50467$3118 + cell $and $and$libresoc.v:50519$3118 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88366,10 +88405,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:50467$3118_Y + connect \Y $and$libresoc.v:50519$3118_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:50470$3121 + cell $and $and$libresoc.v:50522$3121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88377,10 +88416,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:50470$3121_Y + connect \Y $and$libresoc.v:50522$3121_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:50471$3122 + cell $and $and$libresoc.v:50523$3122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88388,10 +88427,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \full_cr_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:50471$3122_Y + connect \Y $and$libresoc.v:50523$3122_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:50472$3123 + cell $and $and$libresoc.v:50524$3123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88399,10 +88438,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:50472$3123_Y + connect \Y $and$libresoc.v:50524$3123_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:50480$3131 + cell $and $and$libresoc.v:50532$3131 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88410,10 +88449,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \alu_cr0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:50480$3131_Y + connect \Y $and$libresoc.v:50532$3131_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:50481$3132 + cell $and $and$libresoc.v:50533$3132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88421,10 +88460,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \alu_cr0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:50481$3132_Y + connect \Y $and$libresoc.v:50533$3132_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:50482$3133 + cell $and $and$libresoc.v:50534$3133 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -88432,10 +88471,10 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:50482$3133_Y + connect \Y $and$libresoc.v:50534$3133_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:50483$3134 + cell $and $and$libresoc.v:50535$3134 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -88443,10 +88482,10 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \$93 connect \B 6'111111 - connect \Y $and$libresoc.v:50483$3134_Y + connect \Y $and$libresoc.v:50535$3134_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:50456$3107 + cell $eq $eq$libresoc.v:50508$3107 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88454,10 +88493,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$43 connect \B 1'0 - connect \Y $eq$libresoc.v:50456$3107_Y + connect \Y $eq$libresoc.v:50508$3107_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:50458$3109 + cell $eq $eq$libresoc.v:50510$3109 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88465,66 +88504,66 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:50458$3109_Y + connect \Y $eq$libresoc.v:50510$3109_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:50439$3090 + cell $not $not$libresoc.v:50491$3090 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:50439$3090_Y + connect \Y $not$libresoc.v:50491$3090_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:50441$3092 + cell $not $not$libresoc.v:50493$3092 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:50441$3092_Y + connect \Y $not$libresoc.v:50493$3092_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:50444$3095 + cell $not $not$libresoc.v:50496$3095 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:50444$3095_Y + connect \Y $not$libresoc.v:50496$3095_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:50447$3098 + cell $not $not$libresoc.v:50499$3098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:50447$3098_Y + connect \Y $not$libresoc.v:50499$3098_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:50453$3104 + cell $not $not$libresoc.v:50505$3104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_cr0_n_ready_i - connect \Y $not$libresoc.v:50453$3104_Y + connect \Y $not$libresoc.v:50505$3104_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:50468$3119 + cell $not $not$libresoc.v:50520$3119 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:50468$3119_Y + connect \Y $not$libresoc.v:50520$3119_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:50484$3135 + cell $not $not$libresoc.v:50536$3135 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:50484$3135_Y + connect \Y $not$libresoc.v:50536$3135_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:50451$3102 + cell $or $or$libresoc.v:50503$3102 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88532,10 +88571,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \$33 connect \B \$35 - connect \Y $or$libresoc.v:50451$3102_Y + connect \Y $or$libresoc.v:50503$3102_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:50462$3113 + cell $or $or$libresoc.v:50514$3113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88543,10 +88582,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:50462$3113_Y + connect \Y $or$libresoc.v:50514$3113_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:50463$3114 + cell $or $or$libresoc.v:50515$3114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -88554,10 +88593,10 @@ module \cr0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:50463$3114_Y + connect \Y $or$libresoc.v:50515$3114_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:50464$3115 + cell $or $or$libresoc.v:50516$3115 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88565,10 +88604,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:50464$3115_Y + connect \Y $or$libresoc.v:50516$3115_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:50465$3116 + cell $or $or$libresoc.v:50517$3116 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -88576,10 +88615,10 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:50465$3116_Y + connect \Y $or$libresoc.v:50517$3116_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:50469$3120 + cell $or $or$libresoc.v:50521$3120 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -88587,10 +88626,10 @@ module \cr0 parameter \Y_WIDTH 3 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:50469$3120_Y + connect \Y $or$libresoc.v:50521$3120_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:50479$3130 + cell $or $or$libresoc.v:50531$3130 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -88598,90 +88637,90 @@ module \cr0 parameter \Y_WIDTH 6 connect \A \$6 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:50479$3130_Y + connect \Y $or$libresoc.v:50531$3130_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:50428$3079 + cell $reduce_and $reduce_and$libresoc.v:50480$3079 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $reduce_and$libresoc.v:50428$3079_Y + connect \Y $reduce_and$libresoc.v:50480$3079_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:50446$3097 + cell $reduce_or $reduce_or$libresoc.v:50498$3097 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$27 - connect \Y $reduce_or$libresoc.v:50446$3097_Y + connect \Y $reduce_or$libresoc.v:50498$3097_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:50449$3100 + cell $reduce_or $reduce_or$libresoc.v:50501$3100 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:50449$3100_Y + connect \Y $reduce_or$libresoc.v:50501$3100_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:50450$3101 + cell $reduce_or $reduce_or$libresoc.v:50502$3101 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:50450$3101_Y + connect \Y $reduce_or$libresoc.v:50502$3101_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:50473$3124 + cell $mux $ternary$libresoc.v:50525$3124 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:50473$3124_Y + connect \Y $ternary$libresoc.v:50525$3124_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:50474$3125 + cell $mux $ternary$libresoc.v:50526$3125 parameter \WIDTH 64 connect \A \src_r1 connect \B \src2_i connect \S \src_l_q_src [1] - connect \Y $ternary$libresoc.v:50474$3125_Y + connect \Y $ternary$libresoc.v:50526$3125_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:50475$3126 + cell $mux $ternary$libresoc.v:50527$3126 parameter \WIDTH 32 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:50475$3126_Y + connect \Y $ternary$libresoc.v:50527$3126_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:50476$3127 + cell $mux $ternary$libresoc.v:50528$3127 parameter \WIDTH 4 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:50476$3127_Y + connect \Y $ternary$libresoc.v:50528$3127_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:50477$3128 + cell $mux $ternary$libresoc.v:50529$3128 parameter \WIDTH 4 connect \A \src_r4 connect \B \src5_i connect \S \src_l_q_src [4] - connect \Y $ternary$libresoc.v:50477$3128_Y + connect \Y $ternary$libresoc.v:50529$3128_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:50478$3129 + cell $mux $ternary$libresoc.v:50530$3129 parameter \WIDTH 4 connect \A \src_r5 connect \B \src6_i connect \S \src_l_q_src [5] - connect \Y $ternary$libresoc.v:50478$3129_Y + connect \Y $ternary$libresoc.v:50530$3129_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:50545.11-50567.4" + attribute \src "libresoc.v:50597.11-50619.4" cell \alu_cr0 \alu_cr0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88706,7 +88745,7 @@ module \cr0 connect \rb \alu_cr0_rb end attribute \module_not_derived 1 - attribute \src "libresoc.v:50568.14-50574.4" + attribute \src "libresoc.v:50620.14-50626.4" cell \alu_l$16 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88715,7 +88754,7 @@ module \cr0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:50575.15-50581.4" + attribute \src "libresoc.v:50627.15-50633.4" cell \alui_l$15 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88724,7 +88763,7 @@ module \cr0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:50582.14-50588.4" + attribute \src "libresoc.v:50634.14-50640.4" cell \opc_l$11 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88733,7 +88772,7 @@ module \cr0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:50589.14-50595.4" + attribute \src "libresoc.v:50641.14-50647.4" cell \req_l$12 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88742,7 +88781,7 @@ module \cr0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:50596.14-50602.4" + attribute \src "libresoc.v:50648.14-50654.4" cell \rok_l$14 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88751,7 +88790,7 @@ module \cr0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:50603.14-50608.4" + attribute \src "libresoc.v:50655.14-50660.4" cell \rst_l$13 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88759,7 +88798,7 @@ module \cr0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:50609.14-50615.4" + attribute \src "libresoc.v:50661.14-50667.4" cell \src_l$10 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -88767,472 +88806,472 @@ module \cr0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:49886.7-49886.20" - process $proc$libresoc.v:49886$3258 + attribute \src "libresoc.v:49938.7-49938.20" + process $proc$libresoc.v:49938$3258 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:50004.7-50004.24" - process $proc$libresoc.v:50004$3259 + attribute \src "libresoc.v:50056.7-50056.24" + process $proc$libresoc.v:50056$3259 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:50035.14-50035.47" - process $proc$libresoc.v:50035$3260 + attribute \src "libresoc.v:50087.14-50087.47" + process $proc$libresoc.v:50087$3260 assign { } { } assign $1\alu_cr0_cr_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_cr0_cr_op__fn_unit $1\alu_cr0_cr_op__fn_unit[13:0] end - attribute \src "libresoc.v:50039.14-50039.41" - process $proc$libresoc.v:50039$3261 + attribute \src "libresoc.v:50091.14-50091.41" + process $proc$libresoc.v:50091$3261 assign { } { } assign $1\alu_cr0_cr_op__insn[31:0] 0 sync always sync init update \alu_cr0_cr_op__insn $1\alu_cr0_cr_op__insn[31:0] end - attribute \src "libresoc.v:50118.13-50118.45" - process $proc$libresoc.v:50118$3262 + attribute \src "libresoc.v:50170.13-50170.45" + process $proc$libresoc.v:50170$3262 assign { } { } assign $1\alu_cr0_cr_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_cr0_cr_op__insn_type $1\alu_cr0_cr_op__insn_type[6:0] end - attribute \src "libresoc.v:50142.7-50142.26" - process $proc$libresoc.v:50142$3263 + attribute \src "libresoc.v:50194.7-50194.26" + process $proc$libresoc.v:50194$3263 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:50150.7-50150.25" - process $proc$libresoc.v:50150$3264 + attribute \src "libresoc.v:50202.7-50202.25" + process $proc$libresoc.v:50202$3264 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:50162.7-50162.27" - process $proc$libresoc.v:50162$3265 + attribute \src "libresoc.v:50214.7-50214.27" + process $proc$libresoc.v:50214$3265 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:50196.14-50196.47" - process $proc$libresoc.v:50196$3266 + attribute \src "libresoc.v:50248.14-50248.47" + process $proc$libresoc.v:50248$3266 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:50200.7-50200.27" - process $proc$libresoc.v:50200$3267 + attribute \src "libresoc.v:50252.7-50252.27" + process $proc$libresoc.v:50252$3267 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:50204.14-50204.38" - process $proc$libresoc.v:50204$3268 + attribute \src "libresoc.v:50256.14-50256.38" + process $proc$libresoc.v:50256$3268 assign { } { } assign $1\data_r1__full_cr[31:0] 0 sync always sync init update \data_r1__full_cr $1\data_r1__full_cr[31:0] end - attribute \src "libresoc.v:50208.7-50208.33" - process $proc$libresoc.v:50208$3269 + attribute \src "libresoc.v:50260.7-50260.33" + process $proc$libresoc.v:50260$3269 assign { } { } assign $1\data_r1__full_cr_ok[0:0] 1'0 sync always sync init update \data_r1__full_cr_ok $1\data_r1__full_cr_ok[0:0] end - attribute \src "libresoc.v:50212.13-50212.33" - process $proc$libresoc.v:50212$3270 + attribute \src "libresoc.v:50264.13-50264.33" + process $proc$libresoc.v:50264$3270 assign { } { } assign $1\data_r2__cr_a[3:0] 4'0000 sync always sync init update \data_r2__cr_a $1\data_r2__cr_a[3:0] end - attribute \src "libresoc.v:50216.7-50216.30" - process $proc$libresoc.v:50216$3271 + attribute \src "libresoc.v:50268.7-50268.30" + process $proc$libresoc.v:50268$3271 assign { } { } assign $1\data_r2__cr_a_ok[0:0] 1'0 sync always sync init update \data_r2__cr_a_ok $1\data_r2__cr_a_ok[0:0] end - attribute \src "libresoc.v:50235.7-50235.25" - process $proc$libresoc.v:50235$3272 + attribute \src "libresoc.v:50287.7-50287.25" + process $proc$libresoc.v:50287$3272 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:50239.7-50239.25" - process $proc$libresoc.v:50239$3273 + attribute \src "libresoc.v:50291.7-50291.25" + process $proc$libresoc.v:50291$3273 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:50339.13-50339.30" - process $proc$libresoc.v:50339$3274 + attribute \src "libresoc.v:50391.13-50391.30" + process $proc$libresoc.v:50391$3274 assign { } { } assign $1\prev_wr_go[2:0] 3'000 sync always sync init update \prev_wr_go $1\prev_wr_go[2:0] end - attribute \src "libresoc.v:50347.13-50347.31" - process $proc$libresoc.v:50347$3275 + attribute \src "libresoc.v:50399.13-50399.31" + process $proc$libresoc.v:50399$3275 assign { } { } assign $1\req_l_r_req[2:0] 3'111 sync always sync init update \req_l_r_req $1\req_l_r_req[2:0] end - attribute \src "libresoc.v:50351.13-50351.31" - process $proc$libresoc.v:50351$3276 + attribute \src "libresoc.v:50403.13-50403.31" + process $proc$libresoc.v:50403$3276 assign { } { } assign $1\req_l_s_req[2:0] 3'000 sync always sync init update \req_l_s_req $1\req_l_s_req[2:0] end - attribute \src "libresoc.v:50363.7-50363.26" - process $proc$libresoc.v:50363$3277 + attribute \src "libresoc.v:50415.7-50415.26" + process $proc$libresoc.v:50415$3277 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:50367.7-50367.26" - process $proc$libresoc.v:50367$3278 + attribute \src "libresoc.v:50419.7-50419.26" + process $proc$libresoc.v:50419$3278 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:50371.7-50371.25" - process $proc$libresoc.v:50371$3279 + attribute \src "libresoc.v:50423.7-50423.25" + process $proc$libresoc.v:50423$3279 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:50375.7-50375.25" - process $proc$libresoc.v:50375$3280 + attribute \src "libresoc.v:50427.7-50427.25" + process $proc$libresoc.v:50427$3280 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:50395.13-50395.32" - process $proc$libresoc.v:50395$3281 + attribute \src "libresoc.v:50447.13-50447.32" + process $proc$libresoc.v:50447$3281 assign { } { } assign $1\src_l_r_src[5:0] 6'111111 sync always sync init update \src_l_r_src $1\src_l_r_src[5:0] end - attribute \src "libresoc.v:50399.13-50399.32" - process $proc$libresoc.v:50399$3282 + attribute \src "libresoc.v:50451.13-50451.32" + process $proc$libresoc.v:50451$3282 assign { } { } assign $1\src_l_s_src[5:0] 6'000000 sync always sync init update \src_l_s_src $1\src_l_s_src[5:0] end - attribute \src "libresoc.v:50403.14-50403.43" - process $proc$libresoc.v:50403$3283 + attribute \src "libresoc.v:50455.14-50455.43" + process $proc$libresoc.v:50455$3283 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:50407.14-50407.43" - process $proc$libresoc.v:50407$3284 + attribute \src "libresoc.v:50459.14-50459.43" + process $proc$libresoc.v:50459$3284 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:50411.14-50411.28" - process $proc$libresoc.v:50411$3285 + attribute \src "libresoc.v:50463.14-50463.28" + process $proc$libresoc.v:50463$3285 assign { } { } assign $1\src_r2[31:0] 0 sync always sync init update \src_r2 $1\src_r2[31:0] end - attribute \src "libresoc.v:50415.13-50415.26" - process $proc$libresoc.v:50415$3286 + attribute \src "libresoc.v:50467.13-50467.26" + process $proc$libresoc.v:50467$3286 assign { } { } assign $1\src_r3[3:0] 4'0000 sync always sync init update \src_r3 $1\src_r3[3:0] end - attribute \src "libresoc.v:50419.13-50419.26" - process $proc$libresoc.v:50419$3287 + attribute \src "libresoc.v:50471.13-50471.26" + process $proc$libresoc.v:50471$3287 assign { } { } assign $1\src_r4[3:0] 4'0000 sync always sync init update \src_r4 $1\src_r4[3:0] end - attribute \src "libresoc.v:50423.13-50423.26" - process $proc$libresoc.v:50423$3288 + attribute \src "libresoc.v:50475.13-50475.26" + process $proc$libresoc.v:50475$3288 assign { } { } assign $1\src_r5[3:0] 4'0000 sync always sync init update \src_r5 $1\src_r5[3:0] end - attribute \src "libresoc.v:50485.3-50486.39" - process $proc$libresoc.v:50485$3136 + attribute \src "libresoc.v:50537.3-50538.39" + process $proc$libresoc.v:50537$3136 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:50487.3-50488.43" - process $proc$libresoc.v:50487$3137 + attribute \src "libresoc.v:50539.3-50540.43" + process $proc$libresoc.v:50539$3137 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:50489.3-50490.29" - process $proc$libresoc.v:50489$3138 + attribute \src "libresoc.v:50541.3-50542.29" + process $proc$libresoc.v:50541$3138 assign { } { } assign $0\src_r5[3:0] \src_r5$next sync posedge \coresync_clk update \src_r5 $0\src_r5[3:0] end - attribute \src "libresoc.v:50491.3-50492.29" - process $proc$libresoc.v:50491$3139 + attribute \src "libresoc.v:50543.3-50544.29" + process $proc$libresoc.v:50543$3139 assign { } { } assign $0\src_r4[3:0] \src_r4$next sync posedge \coresync_clk update \src_r4 $0\src_r4[3:0] end - attribute \src "libresoc.v:50493.3-50494.29" - process $proc$libresoc.v:50493$3140 + attribute \src "libresoc.v:50545.3-50546.29" + process $proc$libresoc.v:50545$3140 assign { } { } assign $0\src_r3[3:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[3:0] end - attribute \src "libresoc.v:50495.3-50496.29" - process $proc$libresoc.v:50495$3141 + attribute \src "libresoc.v:50547.3-50548.29" + process $proc$libresoc.v:50547$3141 assign { } { } assign $0\src_r2[31:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[31:0] end - attribute \src "libresoc.v:50497.3-50498.29" - process $proc$libresoc.v:50497$3142 + attribute \src "libresoc.v:50549.3-50550.29" + process $proc$libresoc.v:50549$3142 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:50499.3-50500.29" - process $proc$libresoc.v:50499$3143 + attribute \src "libresoc.v:50551.3-50552.29" + process $proc$libresoc.v:50551$3143 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:50501.3-50502.43" - process $proc$libresoc.v:50501$3144 + attribute \src "libresoc.v:50553.3-50554.43" + process $proc$libresoc.v:50553$3144 assign { } { } assign $0\data_r2__cr_a[3:0] \data_r2__cr_a$next sync posedge \coresync_clk update \data_r2__cr_a $0\data_r2__cr_a[3:0] end - attribute \src "libresoc.v:50503.3-50504.49" - process $proc$libresoc.v:50503$3145 + attribute \src "libresoc.v:50555.3-50556.49" + process $proc$libresoc.v:50555$3145 assign { } { } assign $0\data_r2__cr_a_ok[0:0] \data_r2__cr_a_ok$next sync posedge \coresync_clk update \data_r2__cr_a_ok $0\data_r2__cr_a_ok[0:0] end - attribute \src "libresoc.v:50505.3-50506.49" - process $proc$libresoc.v:50505$3146 + attribute \src "libresoc.v:50557.3-50558.49" + process $proc$libresoc.v:50557$3146 assign { } { } assign $0\data_r1__full_cr[31:0] \data_r1__full_cr$next sync posedge \coresync_clk update \data_r1__full_cr $0\data_r1__full_cr[31:0] end - attribute \src "libresoc.v:50507.3-50508.55" - process $proc$libresoc.v:50507$3147 + attribute \src "libresoc.v:50559.3-50560.55" + process $proc$libresoc.v:50559$3147 assign { } { } assign $0\data_r1__full_cr_ok[0:0] \data_r1__full_cr_ok$next sync posedge \coresync_clk update \data_r1__full_cr_ok $0\data_r1__full_cr_ok[0:0] end - attribute \src "libresoc.v:50509.3-50510.37" - process $proc$libresoc.v:50509$3148 + attribute \src "libresoc.v:50561.3-50562.37" + process $proc$libresoc.v:50561$3148 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:50511.3-50512.43" - process $proc$libresoc.v:50511$3149 + attribute \src "libresoc.v:50563.3-50564.43" + process $proc$libresoc.v:50563$3149 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:50513.3-50514.65" - process $proc$libresoc.v:50513$3150 + attribute \src "libresoc.v:50565.3-50566.65" + process $proc$libresoc.v:50565$3150 assign { } { } assign $0\alu_cr0_cr_op__insn_type[6:0] \alu_cr0_cr_op__insn_type$next sync posedge \coresync_clk update \alu_cr0_cr_op__insn_type $0\alu_cr0_cr_op__insn_type[6:0] end - attribute \src "libresoc.v:50515.3-50516.61" - process $proc$libresoc.v:50515$3151 + attribute \src "libresoc.v:50567.3-50568.61" + process $proc$libresoc.v:50567$3151 assign { } { } assign $0\alu_cr0_cr_op__fn_unit[13:0] \alu_cr0_cr_op__fn_unit$next sync posedge \coresync_clk update \alu_cr0_cr_op__fn_unit $0\alu_cr0_cr_op__fn_unit[13:0] end - attribute \src "libresoc.v:50517.3-50518.55" - process $proc$libresoc.v:50517$3152 + attribute \src "libresoc.v:50569.3-50570.55" + process $proc$libresoc.v:50569$3152 assign { } { } assign $0\alu_cr0_cr_op__insn[31:0] \alu_cr0_cr_op__insn$next sync posedge \coresync_clk update \alu_cr0_cr_op__insn $0\alu_cr0_cr_op__insn[31:0] end - attribute \src "libresoc.v:50519.3-50520.39" - process $proc$libresoc.v:50519$3153 + attribute \src "libresoc.v:50571.3-50572.39" + process $proc$libresoc.v:50571$3153 assign { } { } assign $0\req_l_r_req[2:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[2:0] end - attribute \src "libresoc.v:50521.3-50522.39" - process $proc$libresoc.v:50521$3154 + attribute \src "libresoc.v:50573.3-50574.39" + process $proc$libresoc.v:50573$3154 assign { } { } assign $0\req_l_s_req[2:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[2:0] end - attribute \src "libresoc.v:50523.3-50524.39" - process $proc$libresoc.v:50523$3155 + attribute \src "libresoc.v:50575.3-50576.39" + process $proc$libresoc.v:50575$3155 assign { } { } assign $0\src_l_r_src[5:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[5:0] end - attribute \src "libresoc.v:50525.3-50526.39" - process $proc$libresoc.v:50525$3156 + attribute \src "libresoc.v:50577.3-50578.39" + process $proc$libresoc.v:50577$3156 assign { } { } assign $0\src_l_s_src[5:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[5:0] end - attribute \src "libresoc.v:50527.3-50528.39" - process $proc$libresoc.v:50527$3157 + attribute \src "libresoc.v:50579.3-50580.39" + process $proc$libresoc.v:50579$3157 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:50529.3-50530.39" - process $proc$libresoc.v:50529$3158 + attribute \src "libresoc.v:50581.3-50582.39" + process $proc$libresoc.v:50581$3158 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:50531.3-50532.39" - process $proc$libresoc.v:50531$3159 + attribute \src "libresoc.v:50583.3-50584.39" + process $proc$libresoc.v:50583$3159 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:50533.3-50534.39" - process $proc$libresoc.v:50533$3160 + attribute \src "libresoc.v:50585.3-50586.39" + process $proc$libresoc.v:50585$3160 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:50535.3-50536.41" - process $proc$libresoc.v:50535$3161 + attribute \src "libresoc.v:50587.3-50588.41" + process $proc$libresoc.v:50587$3161 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:50537.3-50538.41" - process $proc$libresoc.v:50537$3162 + attribute \src "libresoc.v:50589.3-50590.41" + process $proc$libresoc.v:50589$3162 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:50539.3-50540.37" - process $proc$libresoc.v:50539$3163 + attribute \src "libresoc.v:50591.3-50592.37" + process $proc$libresoc.v:50591$3163 assign { } { } assign $0\prev_wr_go[2:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[2:0] end - attribute \src "libresoc.v:50541.3-50542.39" - process $proc$libresoc.v:50541$3164 + attribute \src "libresoc.v:50593.3-50594.39" + process $proc$libresoc.v:50593$3164 assign { } { } assign $0\alu_done_dly[0:0] \alu_cr0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:50543.3-50544.25" - process $proc$libresoc.v:50543$3165 + attribute \src "libresoc.v:50595.3-50596.25" + process $proc$libresoc.v:50595$3165 assign { } { } assign $0\all_rd_dly[0:0] \$11 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:50616.3-50625.6" - process $proc$libresoc.v:50616$3166 + attribute \src "libresoc.v:50668.3-50677.6" + process $proc$libresoc.v:50668$3166 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:50617.5-50617.29" + attribute \src "libresoc.v:50669.5-50669.29" switch \initial - attribute \src "libresoc.v:50617.9-50617.17" + attribute \src "libresoc.v:50669.9-50669.17" case 1'1 case end @@ -89248,14 +89287,14 @@ module \cr0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:50626.3-50634.6" - process $proc$libresoc.v:50626$3167 + attribute \src "libresoc.v:50678.3-50686.6" + process $proc$libresoc.v:50678$3167 assign { } { } assign { } { } assign $0\rok_l_s_rdok$next[0:0]$3168 $1\rok_l_s_rdok$next[0:0]$3169 - attribute \src "libresoc.v:50627.5-50627.29" + attribute \src "libresoc.v:50679.5-50679.29" switch \initial - attribute \src "libresoc.v:50627.9-50627.17" + attribute \src "libresoc.v:50679.9-50679.17" case 1'1 case end @@ -89271,14 +89310,14 @@ module \cr0 sync always update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$3168 end - attribute \src "libresoc.v:50635.3-50643.6" - process $proc$libresoc.v:50635$3170 + attribute \src "libresoc.v:50687.3-50695.6" + process $proc$libresoc.v:50687$3170 assign { } { } assign { } { } assign $0\rok_l_r_rdok$next[0:0]$3171 $1\rok_l_r_rdok$next[0:0]$3172 - attribute \src "libresoc.v:50636.5-50636.29" + attribute \src "libresoc.v:50688.5-50688.29" switch \initial - attribute \src "libresoc.v:50636.9-50636.17" + attribute \src "libresoc.v:50688.9-50688.17" case 1'1 case end @@ -89294,14 +89333,14 @@ module \cr0 sync always update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$3171 end - attribute \src "libresoc.v:50644.3-50652.6" - process $proc$libresoc.v:50644$3173 + attribute \src "libresoc.v:50696.3-50704.6" + process $proc$libresoc.v:50696$3173 assign { } { } assign { } { } assign $0\rst_l_s_rst$next[0:0]$3174 $1\rst_l_s_rst$next[0:0]$3175 - attribute \src "libresoc.v:50645.5-50645.29" + attribute \src "libresoc.v:50697.5-50697.29" switch \initial - attribute \src "libresoc.v:50645.9-50645.17" + attribute \src "libresoc.v:50697.9-50697.17" case 1'1 case end @@ -89317,14 +89356,14 @@ module \cr0 sync always update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$3174 end - attribute \src "libresoc.v:50653.3-50661.6" - process $proc$libresoc.v:50653$3176 + attribute \src "libresoc.v:50705.3-50713.6" + process $proc$libresoc.v:50705$3176 assign { } { } assign { } { } assign $0\rst_l_r_rst$next[0:0]$3177 $1\rst_l_r_rst$next[0:0]$3178 - attribute \src "libresoc.v:50654.5-50654.29" + attribute \src "libresoc.v:50706.5-50706.29" switch \initial - attribute \src "libresoc.v:50654.9-50654.17" + attribute \src "libresoc.v:50706.9-50706.17" case 1'1 case end @@ -89340,14 +89379,14 @@ module \cr0 sync always update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$3177 end - attribute \src "libresoc.v:50662.3-50670.6" - process $proc$libresoc.v:50662$3179 + attribute \src "libresoc.v:50714.3-50722.6" + process $proc$libresoc.v:50714$3179 assign { } { } assign { } { } assign $0\opc_l_s_opc$next[0:0]$3180 $1\opc_l_s_opc$next[0:0]$3181 - attribute \src "libresoc.v:50663.5-50663.29" + attribute \src "libresoc.v:50715.5-50715.29" switch \initial - attribute \src "libresoc.v:50663.9-50663.17" + attribute \src "libresoc.v:50715.9-50715.17" case 1'1 case end @@ -89363,14 +89402,14 @@ module \cr0 sync always update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$3180 end - attribute \src "libresoc.v:50671.3-50679.6" - process $proc$libresoc.v:50671$3182 + attribute \src "libresoc.v:50723.3-50731.6" + process $proc$libresoc.v:50723$3182 assign { } { } assign { } { } assign $0\opc_l_r_opc$next[0:0]$3183 $1\opc_l_r_opc$next[0:0]$3184 - attribute \src "libresoc.v:50672.5-50672.29" + attribute \src "libresoc.v:50724.5-50724.29" switch \initial - attribute \src "libresoc.v:50672.9-50672.17" + attribute \src "libresoc.v:50724.9-50724.17" case 1'1 case end @@ -89386,14 +89425,14 @@ module \cr0 sync always update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$3183 end - attribute \src "libresoc.v:50680.3-50688.6" - process $proc$libresoc.v:50680$3185 + attribute \src "libresoc.v:50732.3-50740.6" + process $proc$libresoc.v:50732$3185 assign { } { } assign { } { } assign $0\src_l_s_src$next[5:0]$3186 $1\src_l_s_src$next[5:0]$3187 - attribute \src "libresoc.v:50681.5-50681.29" + attribute \src "libresoc.v:50733.5-50733.29" switch \initial - attribute \src "libresoc.v:50681.9-50681.17" + attribute \src "libresoc.v:50733.9-50733.17" case 1'1 case end @@ -89409,14 +89448,14 @@ module \cr0 sync always update \src_l_s_src$next $0\src_l_s_src$next[5:0]$3186 end - attribute \src "libresoc.v:50689.3-50697.6" - process $proc$libresoc.v:50689$3188 + attribute \src "libresoc.v:50741.3-50749.6" + process $proc$libresoc.v:50741$3188 assign { } { } assign { } { } assign $0\src_l_r_src$next[5:0]$3189 $1\src_l_r_src$next[5:0]$3190 - attribute \src "libresoc.v:50690.5-50690.29" + attribute \src "libresoc.v:50742.5-50742.29" switch \initial - attribute \src "libresoc.v:50690.9-50690.17" + attribute \src "libresoc.v:50742.9-50742.17" case 1'1 case end @@ -89432,14 +89471,14 @@ module \cr0 sync always update \src_l_r_src$next $0\src_l_r_src$next[5:0]$3189 end - attribute \src "libresoc.v:50698.3-50706.6" - process $proc$libresoc.v:50698$3191 + attribute \src "libresoc.v:50750.3-50758.6" + process $proc$libresoc.v:50750$3191 assign { } { } assign { } { } assign $0\req_l_s_req$next[2:0]$3192 $1\req_l_s_req$next[2:0]$3193 - attribute \src "libresoc.v:50699.5-50699.29" + attribute \src "libresoc.v:50751.5-50751.29" switch \initial - attribute \src "libresoc.v:50699.9-50699.17" + attribute \src "libresoc.v:50751.9-50751.17" case 1'1 case end @@ -89455,14 +89494,14 @@ module \cr0 sync always update \req_l_s_req$next $0\req_l_s_req$next[2:0]$3192 end - attribute \src "libresoc.v:50707.3-50715.6" - process $proc$libresoc.v:50707$3194 + attribute \src "libresoc.v:50759.3-50767.6" + process $proc$libresoc.v:50759$3194 assign { } { } assign { } { } assign $0\req_l_r_req$next[2:0]$3195 $1\req_l_r_req$next[2:0]$3196 - attribute \src "libresoc.v:50708.5-50708.29" + attribute \src "libresoc.v:50760.5-50760.29" switch \initial - attribute \src "libresoc.v:50708.9-50708.17" + attribute \src "libresoc.v:50760.9-50760.17" case 1'1 case end @@ -89478,8 +89517,8 @@ module \cr0 sync always update \req_l_r_req$next $0\req_l_r_req$next[2:0]$3195 end - attribute \src "libresoc.v:50716.3-50727.6" - process $proc$libresoc.v:50716$3197 + attribute \src "libresoc.v:50768.3-50779.6" + process $proc$libresoc.v:50768$3197 assign { } { } assign { } { } assign { } { } @@ -89489,9 +89528,9 @@ module \cr0 assign $0\alu_cr0_cr_op__fn_unit$next[13:0]$3198 $1\alu_cr0_cr_op__fn_unit$next[13:0]$3201 assign $0\alu_cr0_cr_op__insn$next[31:0]$3199 $1\alu_cr0_cr_op__insn$next[31:0]$3202 assign $0\alu_cr0_cr_op__insn_type$next[6:0]$3200 $1\alu_cr0_cr_op__insn_type$next[6:0]$3203 - attribute \src "libresoc.v:50717.5-50717.29" + attribute \src "libresoc.v:50769.5-50769.29" switch \initial - attribute \src "libresoc.v:50717.9-50717.17" + attribute \src "libresoc.v:50769.9-50769.17" case 1'1 case end @@ -89513,8 +89552,8 @@ module \cr0 update \alu_cr0_cr_op__insn$next $0\alu_cr0_cr_op__insn$next[31:0]$3199 update \alu_cr0_cr_op__insn_type$next $0\alu_cr0_cr_op__insn_type$next[6:0]$3200 end - attribute \src "libresoc.v:50728.3-50749.6" - process $proc$libresoc.v:50728$3204 + attribute \src "libresoc.v:50780.3-50801.6" + process $proc$libresoc.v:50780$3204 assign { } { } assign { } { } assign { } { } @@ -89524,9 +89563,9 @@ module \cr0 assign $0\data_r0__o$next[63:0]$3205 $2\data_r0__o$next[63:0]$3209 assign { } { } assign $0\data_r0__o_ok$next[0:0]$3206 $3\data_r0__o_ok$next[0:0]$3211 - attribute \src "libresoc.v:50729.5-50729.29" + attribute \src "libresoc.v:50781.5-50781.29" switch \initial - attribute \src "libresoc.v:50729.9-50729.17" + attribute \src "libresoc.v:50781.9-50781.17" case 1'1 case end @@ -89565,8 +89604,8 @@ module \cr0 update \data_r0__o$next $0\data_r0__o$next[63:0]$3205 update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$3206 end - attribute \src "libresoc.v:50750.3-50771.6" - process $proc$libresoc.v:50750$3212 + attribute \src "libresoc.v:50802.3-50823.6" + process $proc$libresoc.v:50802$3212 assign { } { } assign { } { } assign { } { } @@ -89576,9 +89615,9 @@ module \cr0 assign $0\data_r1__full_cr$next[31:0]$3213 $2\data_r1__full_cr$next[31:0]$3217 assign { } { } assign $0\data_r1__full_cr_ok$next[0:0]$3214 $3\data_r1__full_cr_ok$next[0:0]$3219 - attribute \src "libresoc.v:50751.5-50751.29" + attribute \src "libresoc.v:50803.5-50803.29" switch \initial - attribute \src "libresoc.v:50751.9-50751.17" + attribute \src "libresoc.v:50803.9-50803.17" case 1'1 case end @@ -89617,8 +89656,8 @@ module \cr0 update \data_r1__full_cr$next $0\data_r1__full_cr$next[31:0]$3213 update \data_r1__full_cr_ok$next $0\data_r1__full_cr_ok$next[0:0]$3214 end - attribute \src "libresoc.v:50772.3-50793.6" - process $proc$libresoc.v:50772$3220 + attribute \src "libresoc.v:50824.3-50845.6" + process $proc$libresoc.v:50824$3220 assign { } { } assign { } { } assign { } { } @@ -89628,9 +89667,9 @@ module \cr0 assign $0\data_r2__cr_a$next[3:0]$3221 $2\data_r2__cr_a$next[3:0]$3225 assign { } { } assign $0\data_r2__cr_a_ok$next[0:0]$3222 $3\data_r2__cr_a_ok$next[0:0]$3227 - attribute \src "libresoc.v:50773.5-50773.29" + attribute \src "libresoc.v:50825.5-50825.29" switch \initial - attribute \src "libresoc.v:50773.9-50773.17" + attribute \src "libresoc.v:50825.9-50825.17" case 1'1 case end @@ -89669,14 +89708,14 @@ module \cr0 update \data_r2__cr_a$next $0\data_r2__cr_a$next[3:0]$3221 update \data_r2__cr_a_ok$next $0\data_r2__cr_a_ok$next[0:0]$3222 end - attribute \src "libresoc.v:50794.3-50803.6" - process $proc$libresoc.v:50794$3228 + attribute \src "libresoc.v:50846.3-50855.6" + process $proc$libresoc.v:50846$3228 assign { } { } assign { } { } assign $0\src_r0$next[63:0]$3229 $1\src_r0$next[63:0]$3230 - attribute \src "libresoc.v:50795.5-50795.29" + attribute \src "libresoc.v:50847.5-50847.29" switch \initial - attribute \src "libresoc.v:50795.9-50795.17" + attribute \src "libresoc.v:50847.9-50847.17" case 1'1 case end @@ -89692,14 +89731,14 @@ module \cr0 sync always update \src_r0$next $0\src_r0$next[63:0]$3229 end - attribute \src "libresoc.v:50804.3-50813.6" - process $proc$libresoc.v:50804$3231 + attribute \src "libresoc.v:50856.3-50865.6" + process $proc$libresoc.v:50856$3231 assign { } { } assign { } { } assign $0\src_r1$next[63:0]$3232 $1\src_r1$next[63:0]$3233 - attribute \src "libresoc.v:50805.5-50805.29" + attribute \src "libresoc.v:50857.5-50857.29" switch \initial - attribute \src "libresoc.v:50805.9-50805.17" + attribute \src "libresoc.v:50857.9-50857.17" case 1'1 case end @@ -89715,14 +89754,14 @@ module \cr0 sync always update \src_r1$next $0\src_r1$next[63:0]$3232 end - attribute \src "libresoc.v:50814.3-50823.6" - process $proc$libresoc.v:50814$3234 + attribute \src "libresoc.v:50866.3-50875.6" + process $proc$libresoc.v:50866$3234 assign { } { } assign { } { } assign $0\src_r2$next[31:0]$3235 $1\src_r2$next[31:0]$3236 - attribute \src "libresoc.v:50815.5-50815.29" + attribute \src "libresoc.v:50867.5-50867.29" switch \initial - attribute \src "libresoc.v:50815.9-50815.17" + attribute \src "libresoc.v:50867.9-50867.17" case 1'1 case end @@ -89738,14 +89777,14 @@ module \cr0 sync always update \src_r2$next $0\src_r2$next[31:0]$3235 end - attribute \src "libresoc.v:50824.3-50833.6" - process $proc$libresoc.v:50824$3237 + attribute \src "libresoc.v:50876.3-50885.6" + process $proc$libresoc.v:50876$3237 assign { } { } assign { } { } assign $0\src_r3$next[3:0]$3238 $1\src_r3$next[3:0]$3239 - attribute \src "libresoc.v:50825.5-50825.29" + attribute \src "libresoc.v:50877.5-50877.29" switch \initial - attribute \src "libresoc.v:50825.9-50825.17" + attribute \src "libresoc.v:50877.9-50877.17" case 1'1 case end @@ -89761,14 +89800,14 @@ module \cr0 sync always update \src_r3$next $0\src_r3$next[3:0]$3238 end - attribute \src "libresoc.v:50834.3-50843.6" - process $proc$libresoc.v:50834$3240 + attribute \src "libresoc.v:50886.3-50895.6" + process $proc$libresoc.v:50886$3240 assign { } { } assign { } { } assign $0\src_r4$next[3:0]$3241 $1\src_r4$next[3:0]$3242 - attribute \src "libresoc.v:50835.5-50835.29" + attribute \src "libresoc.v:50887.5-50887.29" switch \initial - attribute \src "libresoc.v:50835.9-50835.17" + attribute \src "libresoc.v:50887.9-50887.17" case 1'1 case end @@ -89784,14 +89823,14 @@ module \cr0 sync always update \src_r4$next $0\src_r4$next[3:0]$3241 end - attribute \src "libresoc.v:50844.3-50853.6" - process $proc$libresoc.v:50844$3243 + attribute \src "libresoc.v:50896.3-50905.6" + process $proc$libresoc.v:50896$3243 assign { } { } assign { } { } assign $0\src_r5$next[3:0]$3244 $1\src_r5$next[3:0]$3245 - attribute \src "libresoc.v:50845.5-50845.29" + attribute \src "libresoc.v:50897.5-50897.29" switch \initial - attribute \src "libresoc.v:50845.9-50845.17" + attribute \src "libresoc.v:50897.9-50897.17" case 1'1 case end @@ -89807,14 +89846,14 @@ module \cr0 sync always update \src_r5$next $0\src_r5$next[3:0]$3244 end - attribute \src "libresoc.v:50854.3-50862.6" - process $proc$libresoc.v:50854$3246 + attribute \src "libresoc.v:50906.3-50914.6" + process $proc$libresoc.v:50906$3246 assign { } { } assign { } { } assign $0\alui_l_r_alui$next[0:0]$3247 $1\alui_l_r_alui$next[0:0]$3248 - attribute \src "libresoc.v:50855.5-50855.29" + attribute \src "libresoc.v:50907.5-50907.29" switch \initial - attribute \src "libresoc.v:50855.9-50855.17" + attribute \src "libresoc.v:50907.9-50907.17" case 1'1 case end @@ -89830,14 +89869,14 @@ module \cr0 sync always update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$3247 end - attribute \src "libresoc.v:50863.3-50871.6" - process $proc$libresoc.v:50863$3249 + attribute \src "libresoc.v:50915.3-50923.6" + process $proc$libresoc.v:50915$3249 assign { } { } assign { } { } assign $0\alu_l_r_alu$next[0:0]$3250 $1\alu_l_r_alu$next[0:0]$3251 - attribute \src "libresoc.v:50864.5-50864.29" + attribute \src "libresoc.v:50916.5-50916.29" switch \initial - attribute \src "libresoc.v:50864.9-50864.17" + attribute \src "libresoc.v:50916.9-50916.17" case 1'1 case end @@ -89853,14 +89892,14 @@ module \cr0 sync always update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$3250 end - attribute \src "libresoc.v:50872.3-50881.6" - process $proc$libresoc.v:50872$3252 + attribute \src "libresoc.v:50924.3-50933.6" + process $proc$libresoc.v:50924$3252 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:50873.5-50873.29" + attribute \src "libresoc.v:50925.5-50925.29" switch \initial - attribute \src "libresoc.v:50873.9-50873.17" + attribute \src "libresoc.v:50925.9-50925.17" case 1'1 case end @@ -89876,14 +89915,14 @@ module \cr0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:50882.3-50891.6" - process $proc$libresoc.v:50882$3253 + attribute \src "libresoc.v:50934.3-50943.6" + process $proc$libresoc.v:50934$3253 assign { } { } assign { } { } assign $0\dest2_o[31:0] $1\dest2_o[31:0] - attribute \src "libresoc.v:50883.5-50883.29" + attribute \src "libresoc.v:50935.5-50935.29" switch \initial - attribute \src "libresoc.v:50883.9-50883.17" + attribute \src "libresoc.v:50935.9-50935.17" case 1'1 case end @@ -89899,14 +89938,14 @@ module \cr0 sync always update \dest2_o $0\dest2_o[31:0] end - attribute \src "libresoc.v:50892.3-50901.6" - process $proc$libresoc.v:50892$3254 + attribute \src "libresoc.v:50944.3-50953.6" + process $proc$libresoc.v:50944$3254 assign { } { } assign { } { } assign $0\dest3_o[3:0] $1\dest3_o[3:0] - attribute \src "libresoc.v:50893.5-50893.29" + attribute \src "libresoc.v:50945.5-50945.29" switch \initial - attribute \src "libresoc.v:50893.9-50893.17" + attribute \src "libresoc.v:50945.9-50945.17" case 1'1 case end @@ -89922,14 +89961,14 @@ module \cr0 sync always update \dest3_o $0\dest3_o[3:0] end - attribute \src "libresoc.v:50902.3-50910.6" - process $proc$libresoc.v:50902$3255 + attribute \src "libresoc.v:50954.3-50962.6" + process $proc$libresoc.v:50954$3255 assign { } { } assign { } { } assign $0\prev_wr_go$next[2:0]$3256 $1\prev_wr_go$next[2:0]$3257 - attribute \src "libresoc.v:50903.5-50903.29" + attribute \src "libresoc.v:50955.5-50955.29" switch \initial - attribute \src "libresoc.v:50903.9-50903.17" + attribute \src "libresoc.v:50955.9-50955.17" case 1'1 case end @@ -89945,63 +89984,63 @@ module \cr0 sync always update \prev_wr_go$next $0\prev_wr_go$next[2:0]$3256 end - connect \$5 $reduce_and$libresoc.v:50428$3079_Y - connect \$99 $and$libresoc.v:50429$3080_Y - connect \$101 $and$libresoc.v:50430$3081_Y - connect \$103 $and$libresoc.v:50431$3082_Y - connect \$105 $and$libresoc.v:50432$3083_Y - connect \$107 $and$libresoc.v:50433$3084_Y - connect \$109 $and$libresoc.v:50434$3085_Y - connect \$111 $and$libresoc.v:50435$3086_Y - connect \$113 $and$libresoc.v:50436$3087_Y - connect \$115 $and$libresoc.v:50437$3088_Y - connect \$11 $and$libresoc.v:50438$3089_Y - connect \$13 $not$libresoc.v:50439$3090_Y - connect \$15 $and$libresoc.v:50440$3091_Y - connect \$17 $not$libresoc.v:50441$3092_Y - connect \$19 $and$libresoc.v:50442$3093_Y - connect \$21 $and$libresoc.v:50443$3094_Y - connect \$25 $not$libresoc.v:50444$3095_Y - connect \$27 $and$libresoc.v:50445$3096_Y - connect \$24 $reduce_or$libresoc.v:50446$3097_Y - connect \$23 $not$libresoc.v:50447$3098_Y - connect \$31 $and$libresoc.v:50448$3099_Y - connect \$33 $reduce_or$libresoc.v:50449$3100_Y - connect \$35 $reduce_or$libresoc.v:50450$3101_Y - connect \$37 $or$libresoc.v:50451$3102_Y - connect \$3 $and$libresoc.v:50452$3103_Y - connect \$39 $not$libresoc.v:50453$3104_Y - connect \$41 $and$libresoc.v:50454$3105_Y - connect \$43 $and$libresoc.v:50455$3106_Y - connect \$45 $eq$libresoc.v:50456$3107_Y - connect \$47 $and$libresoc.v:50457$3108_Y - connect \$49 $eq$libresoc.v:50458$3109_Y - connect \$51 $and$libresoc.v:50459$3110_Y - connect \$53 $and$libresoc.v:50460$3111_Y - connect \$55 $and$libresoc.v:50461$3112_Y - connect \$57 $or$libresoc.v:50462$3113_Y - connect \$59 $or$libresoc.v:50463$3114_Y - connect \$61 $or$libresoc.v:50464$3115_Y - connect \$63 $or$libresoc.v:50465$3116_Y - connect \$65 $and$libresoc.v:50466$3117_Y - connect \$67 $and$libresoc.v:50467$3118_Y - connect \$6 $not$libresoc.v:50468$3119_Y - connect \$69 $or$libresoc.v:50469$3120_Y - connect \$71 $and$libresoc.v:50470$3121_Y - connect \$73 $and$libresoc.v:50471$3122_Y - connect \$75 $and$libresoc.v:50472$3123_Y - connect \$77 $ternary$libresoc.v:50473$3124_Y - connect \$79 $ternary$libresoc.v:50474$3125_Y - connect \$81 $ternary$libresoc.v:50475$3126_Y - connect \$83 $ternary$libresoc.v:50476$3127_Y - connect \$85 $ternary$libresoc.v:50477$3128_Y - connect \$87 $ternary$libresoc.v:50478$3129_Y - connect \$8 $or$libresoc.v:50479$3130_Y - connect \$89 $and$libresoc.v:50480$3131_Y - connect \$91 $and$libresoc.v:50481$3132_Y - connect \$93 $and$libresoc.v:50482$3133_Y - connect \$95 $and$libresoc.v:50483$3134_Y - connect \$97 $not$libresoc.v:50484$3135_Y + connect \$5 $reduce_and$libresoc.v:50480$3079_Y + connect \$99 $and$libresoc.v:50481$3080_Y + connect \$101 $and$libresoc.v:50482$3081_Y + connect \$103 $and$libresoc.v:50483$3082_Y + connect \$105 $and$libresoc.v:50484$3083_Y + connect \$107 $and$libresoc.v:50485$3084_Y + connect \$109 $and$libresoc.v:50486$3085_Y + connect \$111 $and$libresoc.v:50487$3086_Y + connect \$113 $and$libresoc.v:50488$3087_Y + connect \$115 $and$libresoc.v:50489$3088_Y + connect \$11 $and$libresoc.v:50490$3089_Y + connect \$13 $not$libresoc.v:50491$3090_Y + connect \$15 $and$libresoc.v:50492$3091_Y + connect \$17 $not$libresoc.v:50493$3092_Y + connect \$19 $and$libresoc.v:50494$3093_Y + connect \$21 $and$libresoc.v:50495$3094_Y + connect \$25 $not$libresoc.v:50496$3095_Y + connect \$27 $and$libresoc.v:50497$3096_Y + connect \$24 $reduce_or$libresoc.v:50498$3097_Y + connect \$23 $not$libresoc.v:50499$3098_Y + connect \$31 $and$libresoc.v:50500$3099_Y + connect \$33 $reduce_or$libresoc.v:50501$3100_Y + connect \$35 $reduce_or$libresoc.v:50502$3101_Y + connect \$37 $or$libresoc.v:50503$3102_Y + connect \$3 $and$libresoc.v:50504$3103_Y + connect \$39 $not$libresoc.v:50505$3104_Y + connect \$41 $and$libresoc.v:50506$3105_Y + connect \$43 $and$libresoc.v:50507$3106_Y + connect \$45 $eq$libresoc.v:50508$3107_Y + connect \$47 $and$libresoc.v:50509$3108_Y + connect \$49 $eq$libresoc.v:50510$3109_Y + connect \$51 $and$libresoc.v:50511$3110_Y + connect \$53 $and$libresoc.v:50512$3111_Y + connect \$55 $and$libresoc.v:50513$3112_Y + connect \$57 $or$libresoc.v:50514$3113_Y + connect \$59 $or$libresoc.v:50515$3114_Y + connect \$61 $or$libresoc.v:50516$3115_Y + connect \$63 $or$libresoc.v:50517$3116_Y + connect \$65 $and$libresoc.v:50518$3117_Y + connect \$67 $and$libresoc.v:50519$3118_Y + connect \$6 $not$libresoc.v:50520$3119_Y + connect \$69 $or$libresoc.v:50521$3120_Y + connect \$71 $and$libresoc.v:50522$3121_Y + connect \$73 $and$libresoc.v:50523$3122_Y + connect \$75 $and$libresoc.v:50524$3123_Y + connect \$77 $ternary$libresoc.v:50525$3124_Y + connect \$79 $ternary$libresoc.v:50526$3125_Y + connect \$81 $ternary$libresoc.v:50527$3126_Y + connect \$83 $ternary$libresoc.v:50528$3127_Y + connect \$85 $ternary$libresoc.v:50529$3128_Y + connect \$87 $ternary$libresoc.v:50530$3129_Y + connect \$8 $or$libresoc.v:50531$3130_Y + connect \$89 $and$libresoc.v:50532$3131_Y + connect \$91 $and$libresoc.v:50533$3132_Y + connect \$93 $and$libresoc.v:50534$3133_Y + connect \$95 $and$libresoc.v:50535$3134_Y + connect \$97 $not$libresoc.v:50536$3135_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$109 @@ -90034,31 +90073,31 @@ module \cr0 connect \all_rd_dly$next \all_rd connect \all_rd \$11 end -attribute \src "libresoc.v:50946.1-50995.10" +attribute \src "libresoc.v:50998.1-51047.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.cyc_l" attribute \generator "nMigen" module \cyc_l - attribute \src "libresoc.v:50947.7-50947.20" + attribute \src "libresoc.v:50999.7-50999.20" wire $0\initial[0:0] - attribute \src "libresoc.v:50983.3-50991.6" + attribute \src "libresoc.v:51035.3-51043.6" wire $0\q_int$next[0:0]$3296 - attribute \src "libresoc.v:50981.3-50982.27" + attribute \src "libresoc.v:51033.3-51034.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:50983.3-50991.6" + attribute \src "libresoc.v:51035.3-51043.6" wire $1\q_int$next[0:0]$3297 - attribute \src "libresoc.v:50965.7-50965.19" + attribute \src "libresoc.v:51017.7-51017.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:50978.17-50978.96" - wire $and$libresoc.v:50978$3291_Y - attribute \src "libresoc.v:50977.17-50977.92" - wire $not$libresoc.v:50977$3290_Y - attribute \src "libresoc.v:50980.17-50980.92" - wire $not$libresoc.v:50980$3293_Y - attribute \src "libresoc.v:50976.17-50976.98" - wire $or$libresoc.v:50976$3289_Y - attribute \src "libresoc.v:50979.17-50979.97" - wire $or$libresoc.v:50979$3292_Y + attribute \src "libresoc.v:51030.17-51030.96" + wire $and$libresoc.v:51030$3291_Y + attribute \src "libresoc.v:51029.17-51029.92" + wire $not$libresoc.v:51029$3290_Y + attribute \src "libresoc.v:51032.17-51032.92" + wire $not$libresoc.v:51032$3293_Y + attribute \src "libresoc.v:51028.17-51028.98" + wire $or$libresoc.v:51028$3289_Y + attribute \src "libresoc.v:51031.17-51031.97" + wire $or$libresoc.v:51031$3292_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" @@ -90069,11 +90108,11 @@ module \cyc_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:50947.7-50947.15" + attribute \src "libresoc.v:50999.7-50999.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 4 \q_cyc @@ -90090,7 +90129,7 @@ module \cyc_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_cyc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:50978$3291 + cell $and $and$libresoc.v:51030$3291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90098,26 +90137,26 @@ module \cyc_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:50978$3291_Y + connect \Y $and$libresoc.v:51030$3291_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:50977$3290 + cell $not $not$libresoc.v:51029$3290 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_cyc - connect \Y $not$libresoc.v:50977$3290_Y + connect \Y $not$libresoc.v:51029$3290_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:50980$3293 + cell $not $not$libresoc.v:51032$3293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_cyc - connect \Y $not$libresoc.v:50980$3293_Y + connect \Y $not$libresoc.v:51032$3293_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:50976$3289 + cell $or $or$libresoc.v:51028$3289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90125,10 +90164,10 @@ module \cyc_l parameter \Y_WIDTH 1 connect \A \q_cyc connect \B \q_int - connect \Y $or$libresoc.v:50976$3289_Y + connect \Y $or$libresoc.v:51028$3289_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:50979$3292 + cell $or $or$libresoc.v:51031$3292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90136,39 +90175,39 @@ module \cyc_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_cyc - connect \Y $or$libresoc.v:50979$3292_Y + connect \Y $or$libresoc.v:51031$3292_Y end - attribute \src "libresoc.v:50947.7-50947.20" - process $proc$libresoc.v:50947$3298 + attribute \src "libresoc.v:50999.7-50999.20" + process $proc$libresoc.v:50999$3298 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:50965.7-50965.19" - process $proc$libresoc.v:50965$3299 + attribute \src "libresoc.v:51017.7-51017.19" + process $proc$libresoc.v:51017$3299 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:50981.3-50982.27" - process $proc$libresoc.v:50981$3294 + attribute \src "libresoc.v:51033.3-51034.27" + process $proc$libresoc.v:51033$3294 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:50983.3-50991.6" - process $proc$libresoc.v:50983$3295 + attribute \src "libresoc.v:51035.3-51043.6" + process $proc$libresoc.v:51035$3295 assign { } { } assign { } { } assign $0\q_int$next[0:0]$3296 $1\q_int$next[0:0]$3297 - attribute \src "libresoc.v:50984.5-50984.29" + attribute \src "libresoc.v:51036.5-51036.29" switch \initial - attribute \src "libresoc.v:50984.9-50984.17" + attribute \src "libresoc.v:51036.9-51036.17" case 1'1 case end @@ -90184,324 +90223,324 @@ module \cyc_l sync always update \q_int$next $0\q_int$next[0:0]$3296 end - connect \$9 $or$libresoc.v:50976$3289_Y - connect \$1 $not$libresoc.v:50977$3290_Y - connect \$3 $and$libresoc.v:50978$3291_Y - connect \$5 $or$libresoc.v:50979$3292_Y - connect \$7 $not$libresoc.v:50980$3293_Y + connect \$9 $or$libresoc.v:51028$3289_Y + connect \$1 $not$libresoc.v:51029$3290_Y + connect \$3 $and$libresoc.v:51030$3291_Y + connect \$5 $or$libresoc.v:51031$3292_Y + connect \$7 $not$libresoc.v:51032$3293_Y connect \qlq_cyc \$9 connect \qn_cyc \$7 connect \q_cyc \q_int end -attribute \src "libresoc.v:50999.1-51731.10" +attribute \src "libresoc.v:51051.1-51792.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dbg" attribute \generator "nMigen" module \dbg - attribute \src "libresoc.v:51544.3-51553.6" + attribute \src "libresoc.v:51596.3-51608.6" wire $0\d_cr_req[0:0] - attribute \src "libresoc.v:51351.3-51360.6" + attribute \src "libresoc.v:51403.3-51412.6" wire $0\d_gpr_req[0:0] - attribute \src "libresoc.v:51554.3-51563.6" + attribute \src "libresoc.v:51609.3-51624.6" wire $0\d_xer_req[0:0] - attribute \src "libresoc.v:51333.3-51350.6" + attribute \src "libresoc.v:51385.3-51402.6" wire $0\dmi_ack_o[0:0] - attribute \src "libresoc.v:51564.3-51597.6" + attribute \src "libresoc.v:51625.3-51658.6" wire width 64 $0\dmi_dout[63:0] - attribute \src "libresoc.v:51535.3-51543.6" + attribute \src "libresoc.v:51587.3-51595.6" wire $0\dmi_read_log_data$next[0:0]$3414 - attribute \src "libresoc.v:51311.3-51312.51" + attribute \src "libresoc.v:51363.3-51364.51" wire $0\dmi_read_log_data[0:0] - attribute \src "libresoc.v:51526.3-51534.6" + attribute \src "libresoc.v:51578.3-51586.6" wire $0\dmi_read_log_data_1$next[0:0]$3411 - attribute \src "libresoc.v:51313.3-51314.55" + attribute \src "libresoc.v:51365.3-51366.55" wire $0\dmi_read_log_data_1[0:0] - attribute \src "libresoc.v:51361.3-51369.6" + attribute \src "libresoc.v:51413.3-51421.6" wire $0\dmi_req_i_1$next[0:0]$3377 - attribute \src "libresoc.v:51323.3-51324.39" + attribute \src "libresoc.v:51375.3-51376.39" wire $0\dmi_req_i_1[0:0] - attribute \src "libresoc.v:51688.3-51721.6" + attribute \src "libresoc.v:51749.3-51782.6" wire $0\do_dmi_log_rd$next[0:0]$3441 - attribute \src "libresoc.v:51325.3-51326.43" + attribute \src "libresoc.v:51377.3-51378.43" wire $0\do_dmi_log_rd[0:0] - attribute \src "libresoc.v:51658.3-51687.6" + attribute \src "libresoc.v:51719.3-51748.6" wire $0\do_icreset$next[0:0]$3434 - attribute \src "libresoc.v:51327.3-51328.37" + attribute \src "libresoc.v:51379.3-51380.37" wire $0\do_icreset[0:0] - attribute \src "libresoc.v:51628.3-51657.6" + attribute \src "libresoc.v:51689.3-51718.6" wire $0\do_reset$next[0:0]$3427 - attribute \src "libresoc.v:51329.3-51330.33" + attribute \src "libresoc.v:51381.3-51382.33" wire $0\do_reset[0:0] - attribute \src "libresoc.v:51598.3-51627.6" + attribute \src "libresoc.v:51659.3-51688.6" wire $0\do_step$next[0:0]$3420 - attribute \src "libresoc.v:51331.3-51332.31" + attribute \src "libresoc.v:51383.3-51384.31" wire $0\do_step[0:0] - attribute \src "libresoc.v:51464.3-51491.6" + attribute \src "libresoc.v:51516.3-51543.6" wire width 7 $0\gspr_index$next[6:0]$3399 - attribute \src "libresoc.v:51317.3-51318.37" + attribute \src "libresoc.v:51369.3-51370.37" wire width 7 $0\gspr_index[6:0] - attribute \src "libresoc.v:51000.7-51000.20" + attribute \src "libresoc.v:51052.7-51052.20" wire $0\initial[0:0] - attribute \src "libresoc.v:51492.3-51525.6" + attribute \src "libresoc.v:51544.3-51577.6" wire width 32 $0\log_dmi_addr$next[31:0]$3405 - attribute \src "libresoc.v:51315.3-51316.41" + attribute \src "libresoc.v:51367.3-51368.41" wire width 32 $0\log_dmi_addr[31:0] - attribute \src "libresoc.v:51420.3-51463.6" + attribute \src "libresoc.v:51472.3-51515.6" wire $0\stopping$next[0:0]$3390 - attribute \src "libresoc.v:51319.3-51320.33" + attribute \src "libresoc.v:51371.3-51372.33" wire $0\stopping[0:0] - attribute \src "libresoc.v:51370.3-51419.6" + attribute \src "libresoc.v:51422.3-51471.6" wire $0\terminated$next[0:0]$3380 - attribute \src "libresoc.v:51321.3-51322.37" + attribute \src "libresoc.v:51373.3-51374.37" wire $0\terminated[0:0] - attribute \src "libresoc.v:51544.3-51553.6" + attribute \src "libresoc.v:51596.3-51608.6" wire $1\d_cr_req[0:0] - attribute \src "libresoc.v:51351.3-51360.6" + attribute \src "libresoc.v:51403.3-51412.6" wire $1\d_gpr_req[0:0] - attribute \src "libresoc.v:51554.3-51563.6" + attribute \src "libresoc.v:51609.3-51624.6" wire $1\d_xer_req[0:0] - attribute \src "libresoc.v:51333.3-51350.6" + attribute \src "libresoc.v:51385.3-51402.6" wire $1\dmi_ack_o[0:0] - attribute \src "libresoc.v:51564.3-51597.6" + attribute \src "libresoc.v:51625.3-51658.6" wire width 64 $1\dmi_dout[63:0] - attribute \src "libresoc.v:51535.3-51543.6" + attribute \src "libresoc.v:51587.3-51595.6" wire $1\dmi_read_log_data$next[0:0]$3415 - attribute \src "libresoc.v:51187.7-51187.31" + attribute \src "libresoc.v:51239.7-51239.31" wire $1\dmi_read_log_data[0:0] - attribute \src "libresoc.v:51526.3-51534.6" + attribute \src "libresoc.v:51578.3-51586.6" wire $1\dmi_read_log_data_1$next[0:0]$3412 - attribute \src "libresoc.v:51191.7-51191.33" + attribute \src "libresoc.v:51243.7-51243.33" wire $1\dmi_read_log_data_1[0:0] - attribute \src "libresoc.v:51361.3-51369.6" + attribute \src "libresoc.v:51413.3-51421.6" wire $1\dmi_req_i_1$next[0:0]$3378 - attribute \src "libresoc.v:51197.7-51197.25" + attribute \src "libresoc.v:51249.7-51249.25" wire $1\dmi_req_i_1[0:0] - attribute \src "libresoc.v:51688.3-51721.6" + attribute \src "libresoc.v:51749.3-51782.6" wire $1\do_dmi_log_rd$next[0:0]$3442 - attribute \src "libresoc.v:51203.7-51203.27" + attribute \src "libresoc.v:51255.7-51255.27" wire $1\do_dmi_log_rd[0:0] - attribute \src "libresoc.v:51658.3-51687.6" + attribute \src "libresoc.v:51719.3-51748.6" wire $1\do_icreset$next[0:0]$3435 - attribute \src "libresoc.v:51207.7-51207.24" + attribute \src "libresoc.v:51259.7-51259.24" wire $1\do_icreset[0:0] - attribute \src "libresoc.v:51628.3-51657.6" + attribute \src "libresoc.v:51689.3-51718.6" wire $1\do_reset$next[0:0]$3428 - attribute \src "libresoc.v:51211.7-51211.22" + attribute \src "libresoc.v:51263.7-51263.22" wire $1\do_reset[0:0] - attribute \src "libresoc.v:51598.3-51627.6" + attribute \src "libresoc.v:51659.3-51688.6" wire $1\do_step$next[0:0]$3421 - attribute \src "libresoc.v:51215.7-51215.21" + attribute \src "libresoc.v:51267.7-51267.21" wire $1\do_step[0:0] - attribute \src "libresoc.v:51464.3-51491.6" + attribute \src "libresoc.v:51516.3-51543.6" wire width 7 $1\gspr_index$next[6:0]$3400 - attribute \src "libresoc.v:51219.13-51219.31" + attribute \src "libresoc.v:51271.13-51271.31" wire width 7 $1\gspr_index[6:0] - attribute \src "libresoc.v:51492.3-51525.6" + attribute \src "libresoc.v:51544.3-51577.6" wire width 32 $1\log_dmi_addr$next[31:0]$3406 - attribute \src "libresoc.v:51225.14-51225.34" + attribute \src "libresoc.v:51277.14-51277.34" wire width 32 $1\log_dmi_addr[31:0] - attribute \src "libresoc.v:51420.3-51463.6" + attribute \src "libresoc.v:51472.3-51515.6" wire $1\stopping$next[0:0]$3391 - attribute \src "libresoc.v:51237.7-51237.22" + attribute \src "libresoc.v:51289.7-51289.22" wire $1\stopping[0:0] - attribute \src "libresoc.v:51370.3-51419.6" + attribute \src "libresoc.v:51422.3-51471.6" wire $1\terminated$next[0:0]$3381 - attribute \src "libresoc.v:51243.7-51243.24" + attribute \src "libresoc.v:51295.7-51295.24" wire $1\terminated[0:0] - attribute \src "libresoc.v:51688.3-51721.6" + attribute \src "libresoc.v:51749.3-51782.6" wire $2\do_dmi_log_rd$next[0:0]$3443 - attribute \src "libresoc.v:51658.3-51687.6" + attribute \src "libresoc.v:51719.3-51748.6" wire $2\do_icreset$next[0:0]$3436 - attribute \src "libresoc.v:51628.3-51657.6" + attribute \src "libresoc.v:51689.3-51718.6" wire $2\do_reset$next[0:0]$3429 - attribute \src "libresoc.v:51598.3-51627.6" + attribute \src "libresoc.v:51659.3-51688.6" wire $2\do_step$next[0:0]$3422 - attribute \src "libresoc.v:51464.3-51491.6" + attribute \src "libresoc.v:51516.3-51543.6" wire width 7 $2\gspr_index$next[6:0]$3401 - attribute \src "libresoc.v:51492.3-51525.6" + attribute \src "libresoc.v:51544.3-51577.6" wire width 32 $2\log_dmi_addr$next[31:0]$3407 - attribute \src "libresoc.v:51420.3-51463.6" + attribute \src "libresoc.v:51472.3-51515.6" wire $2\stopping$next[0:0]$3392 - attribute \src "libresoc.v:51370.3-51419.6" + attribute \src "libresoc.v:51422.3-51471.6" wire $2\terminated$next[0:0]$3382 - attribute \src "libresoc.v:51688.3-51721.6" + attribute \src "libresoc.v:51749.3-51782.6" wire $3\do_dmi_log_rd$next[0:0]$3444 - attribute \src "libresoc.v:51658.3-51687.6" + attribute \src "libresoc.v:51719.3-51748.6" wire $3\do_icreset$next[0:0]$3437 - attribute \src "libresoc.v:51628.3-51657.6" + attribute \src "libresoc.v:51689.3-51718.6" wire $3\do_reset$next[0:0]$3430 - attribute \src "libresoc.v:51598.3-51627.6" + attribute \src "libresoc.v:51659.3-51688.6" wire $3\do_step$next[0:0]$3423 - attribute \src "libresoc.v:51464.3-51491.6" + attribute \src "libresoc.v:51516.3-51543.6" wire width 7 $3\gspr_index$next[6:0]$3402 - attribute \src "libresoc.v:51492.3-51525.6" + attribute \src "libresoc.v:51544.3-51577.6" wire width 32 $3\log_dmi_addr$next[31:0]$3408 - attribute \src "libresoc.v:51420.3-51463.6" + attribute \src "libresoc.v:51472.3-51515.6" wire $3\stopping$next[0:0]$3393 - attribute \src "libresoc.v:51370.3-51419.6" + attribute \src "libresoc.v:51422.3-51471.6" wire $3\terminated$next[0:0]$3383 - attribute \src "libresoc.v:51688.3-51721.6" + attribute \src "libresoc.v:51749.3-51782.6" wire $4\do_dmi_log_rd$next[0:0]$3445 - attribute \src "libresoc.v:51658.3-51687.6" + attribute \src "libresoc.v:51719.3-51748.6" wire $4\do_icreset$next[0:0]$3438 - attribute \src "libresoc.v:51628.3-51657.6" + attribute \src "libresoc.v:51689.3-51718.6" wire $4\do_reset$next[0:0]$3431 - attribute \src "libresoc.v:51598.3-51627.6" + attribute \src "libresoc.v:51659.3-51688.6" wire $4\do_step$next[0:0]$3424 - attribute \src "libresoc.v:51464.3-51491.6" + attribute \src "libresoc.v:51516.3-51543.6" wire width 7 $4\gspr_index$next[6:0]$3403 - attribute \src "libresoc.v:51492.3-51525.6" + attribute \src "libresoc.v:51544.3-51577.6" wire width 32 $4\log_dmi_addr$next[31:0]$3409 - attribute \src "libresoc.v:51420.3-51463.6" + attribute \src "libresoc.v:51472.3-51515.6" wire $4\stopping$next[0:0]$3394 - attribute \src "libresoc.v:51370.3-51419.6" + attribute \src "libresoc.v:51422.3-51471.6" wire $4\terminated$next[0:0]$3384 - attribute \src "libresoc.v:51658.3-51687.6" + attribute \src "libresoc.v:51719.3-51748.6" wire $5\do_icreset$next[0:0]$3439 - attribute \src "libresoc.v:51628.3-51657.6" + attribute \src "libresoc.v:51689.3-51718.6" wire $5\do_reset$next[0:0]$3432 - attribute \src "libresoc.v:51598.3-51627.6" + attribute \src "libresoc.v:51659.3-51688.6" wire $5\do_step$next[0:0]$3425 - attribute \src "libresoc.v:51420.3-51463.6" + attribute \src "libresoc.v:51472.3-51515.6" wire $5\stopping$next[0:0]$3395 - attribute \src "libresoc.v:51370.3-51419.6" + attribute \src "libresoc.v:51422.3-51471.6" wire $5\terminated$next[0:0]$3385 - attribute \src "libresoc.v:51420.3-51463.6" + attribute \src "libresoc.v:51472.3-51515.6" wire $6\stopping$next[0:0]$3396 - attribute \src "libresoc.v:51370.3-51419.6" + attribute \src "libresoc.v:51422.3-51471.6" wire $6\terminated$next[0:0]$3386 - attribute \src "libresoc.v:51420.3-51463.6" + attribute \src "libresoc.v:51472.3-51515.6" wire $7\stopping$next[0:0]$3397 - attribute \src "libresoc.v:51370.3-51419.6" + attribute \src "libresoc.v:51422.3-51471.6" wire $7\terminated$next[0:0]$3387 - attribute \src "libresoc.v:51370.3-51419.6" + attribute \src "libresoc.v:51422.3-51471.6" wire $8\terminated$next[0:0]$3388 - attribute \src "libresoc.v:51258.19-51258.110" - wire width 3 $add$libresoc.v:51258$3310_Y - attribute \src "libresoc.v:51252.19-51252.103" - wire $and$libresoc.v:51252$3304_Y - attribute \src "libresoc.v:51254.19-51254.113" - wire $and$libresoc.v:51254$3306_Y - attribute \src "libresoc.v:51259.18-51259.110" - wire $and$libresoc.v:51259$3311_Y - attribute \src "libresoc.v:51261.19-51261.103" - wire $and$libresoc.v:51261$3313_Y - attribute \src "libresoc.v:51263.19-51263.102" - wire $and$libresoc.v:51263$3315_Y - attribute \src "libresoc.v:51269.18-51269.101" - wire $and$libresoc.v:51269$3321_Y - attribute \src "libresoc.v:51271.18-51271.111" - wire $and$libresoc.v:51271$3323_Y - attribute \src "libresoc.v:51276.18-51276.101" - wire $and$libresoc.v:51276$3328_Y - attribute \src "libresoc.v:51279.18-51279.111" - wire $and$libresoc.v:51279$3331_Y - attribute \src "libresoc.v:51284.18-51284.101" - wire $and$libresoc.v:51284$3336_Y - attribute \src "libresoc.v:51286.18-51286.111" - wire $and$libresoc.v:51286$3338_Y - attribute \src "libresoc.v:51292.18-51292.101" - wire $and$libresoc.v:51292$3344_Y - attribute \src "libresoc.v:51294.18-51294.111" - wire $and$libresoc.v:51294$3346_Y - attribute \src "libresoc.v:51299.18-51299.101" - wire $and$libresoc.v:51299$3351_Y - attribute \src "libresoc.v:51300.17-51300.99" - wire $and$libresoc.v:51300$3352_Y - attribute \src "libresoc.v:51302.18-51302.111" - wire $and$libresoc.v:51302$3354_Y - attribute \src "libresoc.v:51307.18-51307.101" - wire $and$libresoc.v:51307$3359_Y - attribute \src "libresoc.v:51309.18-51309.111" - wire $and$libresoc.v:51309$3361_Y - attribute \src "libresoc.v:51249.18-51249.103" - wire $eq$libresoc.v:51249$3301_Y - attribute \src "libresoc.v:51250.19-51250.104" - wire $eq$libresoc.v:51250$3302_Y - attribute \src "libresoc.v:51255.19-51255.104" - wire $eq$libresoc.v:51255$3307_Y - attribute \src "libresoc.v:51256.19-51256.104" - wire $eq$libresoc.v:51256$3308_Y - attribute \src "libresoc.v:51257.19-51257.104" - wire $eq$libresoc.v:51257$3309_Y - attribute \src "libresoc.v:51260.19-51260.104" - wire $eq$libresoc.v:51260$3312_Y - attribute \src "libresoc.v:51264.18-51264.103" - wire $eq$libresoc.v:51264$3316_Y - attribute \src "libresoc.v:51265.18-51265.103" - wire $eq$libresoc.v:51265$3317_Y - attribute \src "libresoc.v:51266.18-51266.103" - wire $eq$libresoc.v:51266$3318_Y - attribute \src "libresoc.v:51272.18-51272.103" - wire $eq$libresoc.v:51272$3324_Y - attribute \src "libresoc.v:51273.18-51273.103" - wire $eq$libresoc.v:51273$3325_Y - attribute \src "libresoc.v:51274.18-51274.103" - wire $eq$libresoc.v:51274$3326_Y - attribute \src "libresoc.v:51280.18-51280.103" - wire $eq$libresoc.v:51280$3332_Y - attribute \src "libresoc.v:51281.18-51281.103" - wire $eq$libresoc.v:51281$3333_Y - attribute \src "libresoc.v:51282.18-51282.103" - wire $eq$libresoc.v:51282$3334_Y - attribute \src "libresoc.v:51287.18-51287.103" - wire $eq$libresoc.v:51287$3339_Y - attribute \src "libresoc.v:51288.18-51288.103" - wire $eq$libresoc.v:51288$3340_Y - attribute \src "libresoc.v:51290.18-51290.103" - wire $eq$libresoc.v:51290$3342_Y - attribute \src "libresoc.v:51295.18-51295.103" - wire $eq$libresoc.v:51295$3347_Y - attribute \src "libresoc.v:51296.18-51296.103" - wire $eq$libresoc.v:51296$3348_Y - attribute \src "libresoc.v:51297.18-51297.103" - wire $eq$libresoc.v:51297$3349_Y - attribute \src "libresoc.v:51303.18-51303.103" - wire $eq$libresoc.v:51303$3355_Y - attribute \src "libresoc.v:51304.18-51304.103" - wire $eq$libresoc.v:51304$3356_Y - attribute \src "libresoc.v:51305.18-51305.103" - wire $eq$libresoc.v:51305$3357_Y - attribute \src "libresoc.v:51310.18-51310.103" - wire $eq$libresoc.v:51310$3362_Y - attribute \src "libresoc.v:51248.17-51248.103" - wire $not$libresoc.v:51248$3300_Y - attribute \src "libresoc.v:51251.19-51251.99" - wire $not$libresoc.v:51251$3303_Y - attribute \src "libresoc.v:51253.19-51253.105" - wire $not$libresoc.v:51253$3305_Y - attribute \src "libresoc.v:51262.19-51262.95" - wire $not$libresoc.v:51262$3314_Y - attribute \src "libresoc.v:51268.18-51268.98" - wire $not$libresoc.v:51268$3320_Y - attribute \src "libresoc.v:51270.18-51270.104" - wire $not$libresoc.v:51270$3322_Y - attribute \src "libresoc.v:51275.18-51275.98" - wire $not$libresoc.v:51275$3327_Y - attribute \src "libresoc.v:51277.18-51277.104" - wire $not$libresoc.v:51277$3329_Y - attribute \src "libresoc.v:51283.18-51283.98" - wire $not$libresoc.v:51283$3335_Y - attribute \src "libresoc.v:51285.18-51285.104" - wire $not$libresoc.v:51285$3337_Y - attribute \src "libresoc.v:51289.17-51289.97" - wire $not$libresoc.v:51289$3341_Y - attribute \src "libresoc.v:51291.18-51291.98" - wire $not$libresoc.v:51291$3343_Y - attribute \src "libresoc.v:51293.18-51293.104" - wire $not$libresoc.v:51293$3345_Y - attribute \src "libresoc.v:51298.18-51298.98" - wire $not$libresoc.v:51298$3350_Y - attribute \src "libresoc.v:51301.18-51301.104" - wire $not$libresoc.v:51301$3353_Y - attribute \src "libresoc.v:51306.18-51306.98" - wire $not$libresoc.v:51306$3358_Y - attribute \src "libresoc.v:51308.18-51308.104" - wire $not$libresoc.v:51308$3360_Y - attribute \src "libresoc.v:51267.17-51267.126" - wire width 64 $pos$libresoc.v:51267$3319_Y - attribute \src "libresoc.v:51278.17-51278.245" - wire width 64 $pos$libresoc.v:51278$3330_Y + attribute \src "libresoc.v:51310.19-51310.110" + wire width 3 $add$libresoc.v:51310$3310_Y + attribute \src "libresoc.v:51304.19-51304.103" + wire $and$libresoc.v:51304$3304_Y + attribute \src "libresoc.v:51306.19-51306.113" + wire $and$libresoc.v:51306$3306_Y + attribute \src "libresoc.v:51311.18-51311.110" + wire $and$libresoc.v:51311$3311_Y + attribute \src "libresoc.v:51313.19-51313.103" + wire $and$libresoc.v:51313$3313_Y + attribute \src "libresoc.v:51315.19-51315.102" + wire $and$libresoc.v:51315$3315_Y + attribute \src "libresoc.v:51321.18-51321.101" + wire $and$libresoc.v:51321$3321_Y + attribute \src "libresoc.v:51323.18-51323.111" + wire $and$libresoc.v:51323$3323_Y + attribute \src "libresoc.v:51328.18-51328.101" + wire $and$libresoc.v:51328$3328_Y + attribute \src "libresoc.v:51331.18-51331.111" + wire $and$libresoc.v:51331$3331_Y + attribute \src "libresoc.v:51336.18-51336.101" + wire $and$libresoc.v:51336$3336_Y + attribute \src "libresoc.v:51338.18-51338.111" + wire $and$libresoc.v:51338$3338_Y + attribute \src "libresoc.v:51344.18-51344.101" + wire $and$libresoc.v:51344$3344_Y + attribute \src "libresoc.v:51346.18-51346.111" + wire $and$libresoc.v:51346$3346_Y + attribute \src "libresoc.v:51351.18-51351.101" + wire $and$libresoc.v:51351$3351_Y + attribute \src "libresoc.v:51352.17-51352.99" + wire $and$libresoc.v:51352$3352_Y + attribute \src "libresoc.v:51354.18-51354.111" + wire $and$libresoc.v:51354$3354_Y + attribute \src "libresoc.v:51359.18-51359.101" + wire $and$libresoc.v:51359$3359_Y + attribute \src "libresoc.v:51361.18-51361.111" + wire $and$libresoc.v:51361$3361_Y + attribute \src "libresoc.v:51301.18-51301.103" + wire $eq$libresoc.v:51301$3301_Y + attribute \src "libresoc.v:51302.19-51302.104" + wire $eq$libresoc.v:51302$3302_Y + attribute \src "libresoc.v:51307.19-51307.104" + wire $eq$libresoc.v:51307$3307_Y + attribute \src "libresoc.v:51308.19-51308.104" + wire $eq$libresoc.v:51308$3308_Y + attribute \src "libresoc.v:51309.19-51309.104" + wire $eq$libresoc.v:51309$3309_Y + attribute \src "libresoc.v:51312.19-51312.104" + wire $eq$libresoc.v:51312$3312_Y + attribute \src "libresoc.v:51316.18-51316.103" + wire $eq$libresoc.v:51316$3316_Y + attribute \src "libresoc.v:51317.18-51317.103" + wire $eq$libresoc.v:51317$3317_Y + attribute \src "libresoc.v:51318.18-51318.103" + wire $eq$libresoc.v:51318$3318_Y + attribute \src "libresoc.v:51324.18-51324.103" + wire $eq$libresoc.v:51324$3324_Y + attribute \src "libresoc.v:51325.18-51325.103" + wire $eq$libresoc.v:51325$3325_Y + attribute \src "libresoc.v:51326.18-51326.103" + wire $eq$libresoc.v:51326$3326_Y + attribute \src "libresoc.v:51332.18-51332.103" + wire $eq$libresoc.v:51332$3332_Y + attribute \src "libresoc.v:51333.18-51333.103" + wire $eq$libresoc.v:51333$3333_Y + attribute \src "libresoc.v:51334.18-51334.103" + wire $eq$libresoc.v:51334$3334_Y + attribute \src "libresoc.v:51339.18-51339.103" + wire $eq$libresoc.v:51339$3339_Y + attribute \src "libresoc.v:51340.18-51340.103" + wire $eq$libresoc.v:51340$3340_Y + attribute \src "libresoc.v:51342.18-51342.103" + wire $eq$libresoc.v:51342$3342_Y + attribute \src "libresoc.v:51347.18-51347.103" + wire $eq$libresoc.v:51347$3347_Y + attribute \src "libresoc.v:51348.18-51348.103" + wire $eq$libresoc.v:51348$3348_Y + attribute \src "libresoc.v:51349.18-51349.103" + wire $eq$libresoc.v:51349$3349_Y + attribute \src "libresoc.v:51355.18-51355.103" + wire $eq$libresoc.v:51355$3355_Y + attribute \src "libresoc.v:51356.18-51356.103" + wire $eq$libresoc.v:51356$3356_Y + attribute \src "libresoc.v:51357.18-51357.103" + wire $eq$libresoc.v:51357$3357_Y + attribute \src "libresoc.v:51362.18-51362.103" + wire $eq$libresoc.v:51362$3362_Y + attribute \src "libresoc.v:51300.17-51300.103" + wire $not$libresoc.v:51300$3300_Y + attribute \src "libresoc.v:51303.19-51303.99" + wire $not$libresoc.v:51303$3303_Y + attribute \src "libresoc.v:51305.19-51305.105" + wire $not$libresoc.v:51305$3305_Y + attribute \src "libresoc.v:51314.19-51314.95" + wire $not$libresoc.v:51314$3314_Y + attribute \src "libresoc.v:51320.18-51320.98" + wire $not$libresoc.v:51320$3320_Y + attribute \src "libresoc.v:51322.18-51322.104" + wire $not$libresoc.v:51322$3322_Y + attribute \src "libresoc.v:51327.18-51327.98" + wire $not$libresoc.v:51327$3327_Y + attribute \src "libresoc.v:51329.18-51329.104" + wire $not$libresoc.v:51329$3329_Y + attribute \src "libresoc.v:51335.18-51335.98" + wire $not$libresoc.v:51335$3335_Y + attribute \src "libresoc.v:51337.18-51337.104" + wire $not$libresoc.v:51337$3337_Y + attribute \src "libresoc.v:51341.17-51341.97" + wire $not$libresoc.v:51341$3341_Y + attribute \src "libresoc.v:51343.18-51343.98" + wire $not$libresoc.v:51343$3343_Y + attribute \src "libresoc.v:51345.18-51345.104" + wire $not$libresoc.v:51345$3345_Y + attribute \src "libresoc.v:51350.18-51350.98" + wire $not$libresoc.v:51350$3350_Y + attribute \src "libresoc.v:51353.18-51353.104" + wire $not$libresoc.v:51353$3353_Y + attribute \src "libresoc.v:51358.18-51358.98" + wire $not$libresoc.v:51358$3358_Y + attribute \src "libresoc.v:51360.18-51360.104" + wire $not$libresoc.v:51360$3360_Y + attribute \src "libresoc.v:51319.17-51319.126" + wire width 64 $pos$libresoc.v:51319$3319_Y + attribute \src "libresoc.v:51330.17-51330.245" + wire width 64 $pos$libresoc.v:51330$3330_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" @@ -90630,7 +90669,7 @@ module \dbg wire \$97 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" wire \$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 30 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" wire width 7 input 13 \core_dbg_core_dbg_dststep @@ -90720,7 +90759,7 @@ module \dbg wire width 7 \gspr_index$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:100" wire \icache_rst_o - attribute \src "libresoc.v:51000.7-51000.15" + attribute \src "libresoc.v:51052.7-51052.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:146" wire width 32 \log_dmi_addr @@ -90730,7 +90769,7 @@ module \dbg wire width 64 \log_dmi_data attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:120" wire width 32 \log_write_addr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:135" wire width 64 \stat_reg @@ -90747,7 +90786,7 @@ module \dbg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:123" wire \terminated_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:240" - cell $add $add$libresoc.v:51258$3310 + cell $add $add$libresoc.v:51310$3310 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -90755,10 +90794,10 @@ module \dbg parameter \Y_WIDTH 3 connect \A \log_dmi_addr [1:0] connect \B 1'1 - connect \Y $add$libresoc.v:51258$3310_Y + connect \Y $add$libresoc.v:51310$3310_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:51252$3304 + cell $and $and$libresoc.v:51304$3304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90766,10 +90805,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$103 - connect \Y $and$libresoc.v:51252$3304_Y + connect \Y $and$libresoc.v:51304$3304_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:51254$3306 + cell $and $and$libresoc.v:51306$3306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90777,10 +90816,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$107 - connect \Y $and$libresoc.v:51254$3306_Y + connect \Y $and$libresoc.v:51306$3306_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:51259$3311 + cell $and $and$libresoc.v:51311$3311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90788,10 +90827,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$9 - connect \Y $and$libresoc.v:51259$3311_Y + connect \Y $and$libresoc.v:51311$3311_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:245" - cell $and $and$libresoc.v:51261$3313 + cell $and $and$libresoc.v:51313$3313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90799,10 +90838,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$120 - connect \Y $and$libresoc.v:51261$3313_Y + connect \Y $and$libresoc.v:51313$3313_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:257" - cell $and $and$libresoc.v:51263$3315 + cell $and $and$libresoc.v:51315$3315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90810,10 +90849,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \stopping connect \B \$124 - connect \Y $and$libresoc.v:51263$3315_Y + connect \Y $and$libresoc.v:51315$3315_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:51269$3321 + cell $and $and$libresoc.v:51321$3321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90821,10 +90860,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$19 - connect \Y $and$libresoc.v:51269$3321_Y + connect \Y $and$libresoc.v:51321$3321_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:51271$3323 + cell $and $and$libresoc.v:51323$3323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90832,10 +90871,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$23 - connect \Y $and$libresoc.v:51271$3323_Y + connect \Y $and$libresoc.v:51323$3323_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:51276$3328 + cell $and $and$libresoc.v:51328$3328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90843,10 +90882,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$33 - connect \Y $and$libresoc.v:51276$3328_Y + connect \Y $and$libresoc.v:51328$3328_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:51279$3331 + cell $and $and$libresoc.v:51331$3331 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90854,10 +90893,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$37 - connect \Y $and$libresoc.v:51279$3331_Y + connect \Y $and$libresoc.v:51331$3331_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:51284$3336 + cell $and $and$libresoc.v:51336$3336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90865,10 +90904,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$47 - connect \Y $and$libresoc.v:51284$3336_Y + connect \Y $and$libresoc.v:51336$3336_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:51286$3338 + cell $and $and$libresoc.v:51338$3338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90876,10 +90915,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$51 - connect \Y $and$libresoc.v:51286$3338_Y + connect \Y $and$libresoc.v:51338$3338_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:51292$3344 + cell $and $and$libresoc.v:51344$3344 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90887,10 +90926,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$61 - connect \Y $and$libresoc.v:51292$3344_Y + connect \Y $and$libresoc.v:51344$3344_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:51294$3346 + cell $and $and$libresoc.v:51346$3346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90898,10 +90937,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$65 - connect \Y $and$libresoc.v:51294$3346_Y + connect \Y $and$libresoc.v:51346$3346_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:51299$3351 + cell $and $and$libresoc.v:51351$3351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90909,10 +90948,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$75 - connect \Y $and$libresoc.v:51299$3351_Y + connect \Y $and$libresoc.v:51351$3351_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:51300$3352 + cell $and $and$libresoc.v:51352$3352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90920,10 +90959,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$5 - connect \Y $and$libresoc.v:51300$3352_Y + connect \Y $and$libresoc.v:51352$3352_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:51302$3354 + cell $and $and$libresoc.v:51354$3354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90931,10 +90970,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$79 - connect \Y $and$libresoc.v:51302$3354_Y + connect \Y $and$libresoc.v:51354$3354_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $and $and$libresoc.v:51307$3359 + cell $and $and$libresoc.v:51359$3359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90942,10 +90981,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_req_i connect \B \$89 - connect \Y $and$libresoc.v:51307$3359_Y + connect \Y $and$libresoc.v:51359$3359_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $and $and$libresoc.v:51309$3361 + cell $and $and$libresoc.v:51361$3361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -90953,10 +90992,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_read_log_data_1 connect \B \$93 - connect \Y $and$libresoc.v:51309$3361_Y + connect \Y $and$libresoc.v:51361$3361_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:51249$3301 + cell $eq $eq$libresoc.v:51301$3301 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90964,10 +91003,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51249$3301_Y + connect \Y $eq$libresoc.v:51301$3301_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:51250$3302 + cell $eq $eq$libresoc.v:51302$3302 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90975,10 +91014,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51250$3302_Y + connect \Y $eq$libresoc.v:51302$3302_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:51255$3307 + cell $eq $eq$libresoc.v:51307$3307 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90986,10 +91025,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51255$3307_Y + connect \Y $eq$libresoc.v:51307$3307_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:51256$3308 + cell $eq $eq$libresoc.v:51308$3308 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -90997,10 +91036,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51256$3308_Y + connect \Y $eq$libresoc.v:51308$3308_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:51257$3309 + cell $eq $eq$libresoc.v:51309$3309 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91008,10 +91047,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51257$3309_Y + connect \Y $eq$libresoc.v:51309$3309_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:245" - cell $eq $eq$libresoc.v:51260$3312 + cell $eq $eq$libresoc.v:51312$3312 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91019,10 +91058,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'111 - connect \Y $eq$libresoc.v:51260$3312_Y + connect \Y $eq$libresoc.v:51312$3312_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:51264$3316 + cell $eq $eq$libresoc.v:51316$3316 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91030,10 +91069,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51264$3316_Y + connect \Y $eq$libresoc.v:51316$3316_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:51265$3317 + cell $eq $eq$libresoc.v:51317$3317 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91041,10 +91080,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51265$3317_Y + connect \Y $eq$libresoc.v:51317$3317_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:51266$3318 + cell $eq $eq$libresoc.v:51318$3318 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91052,10 +91091,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51266$3318_Y + connect \Y $eq$libresoc.v:51318$3318_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:51272$3324 + cell $eq $eq$libresoc.v:51324$3324 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91063,10 +91102,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51272$3324_Y + connect \Y $eq$libresoc.v:51324$3324_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:51273$3325 + cell $eq $eq$libresoc.v:51325$3325 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91074,10 +91113,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51273$3325_Y + connect \Y $eq$libresoc.v:51325$3325_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:51274$3326 + cell $eq $eq$libresoc.v:51326$3326 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91085,10 +91124,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51274$3326_Y + connect \Y $eq$libresoc.v:51326$3326_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:51280$3332 + cell $eq $eq$libresoc.v:51332$3332 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91096,10 +91135,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51280$3332_Y + connect \Y $eq$libresoc.v:51332$3332_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:51281$3333 + cell $eq $eq$libresoc.v:51333$3333 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91107,10 +91146,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51281$3333_Y + connect \Y $eq$libresoc.v:51333$3333_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:51282$3334 + cell $eq $eq$libresoc.v:51334$3334 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91118,10 +91157,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51282$3334_Y + connect \Y $eq$libresoc.v:51334$3334_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:51287$3339 + cell $eq $eq$libresoc.v:51339$3339 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91129,10 +91168,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51287$3339_Y + connect \Y $eq$libresoc.v:51339$3339_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:51288$3340 + cell $eq $eq$libresoc.v:51340$3340 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91140,10 +91179,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51288$3340_Y + connect \Y $eq$libresoc.v:51340$3340_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:51290$3342 + cell $eq $eq$libresoc.v:51342$3342 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91151,10 +91190,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51290$3342_Y + connect \Y $eq$libresoc.v:51342$3342_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:51295$3347 + cell $eq $eq$libresoc.v:51347$3347 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91162,10 +91201,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51295$3347_Y + connect \Y $eq$libresoc.v:51347$3347_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:51296$3348 + cell $eq $eq$libresoc.v:51348$3348 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91173,10 +91212,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51296$3348_Y + connect \Y $eq$libresoc.v:51348$3348_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:51297$3349 + cell $eq $eq$libresoc.v:51349$3349 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91184,10 +91223,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51297$3349_Y + connect \Y $eq$libresoc.v:51349$3349_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:51303$3355 + cell $eq $eq$libresoc.v:51355$3355 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91195,10 +91234,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51303$3355_Y + connect \Y $eq$libresoc.v:51355$3355_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $eq $eq$libresoc.v:51304$3356 + cell $eq $eq$libresoc.v:51356$3356 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91206,10 +91245,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'100 - connect \Y $eq$libresoc.v:51304$3356_Y + connect \Y $eq$libresoc.v:51356$3356_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:230" - cell $eq $eq$libresoc.v:51305$3357 + cell $eq $eq$libresoc.v:51357$3357 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91217,10 +91256,10 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 3'110 - connect \Y $eq$libresoc.v:51305$3357_Y + connect \Y $eq$libresoc.v:51357$3357_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - cell $eq $eq$libresoc.v:51310$3362 + cell $eq $eq$libresoc.v:51362$3362 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -91228,340 +91267,340 @@ module \dbg parameter \Y_WIDTH 1 connect \A \dmi_addr_i connect \B 1'0 - connect \Y $eq$libresoc.v:51310$3362_Y + connect \Y $eq$libresoc.v:51362$3362_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:51248$3300 + cell $not $not$libresoc.v:51300$3300 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51248$3300_Y + connect \Y $not$libresoc.v:51300$3300_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:51251$3303 + cell $not $not$libresoc.v:51303$3303 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51251$3303_Y + connect \Y $not$libresoc.v:51303$3303_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:51253$3305 + cell $not $not$libresoc.v:51305$3305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51253$3305_Y + connect \Y $not$libresoc.v:51305$3305_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:257" - cell $not $not$libresoc.v:51262$3314 + cell $not $not$libresoc.v:51314$3314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \do_step - connect \Y $not$libresoc.v:51262$3314_Y + connect \Y $not$libresoc.v:51314$3314_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:51268$3320 + cell $not $not$libresoc.v:51320$3320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51268$3320_Y + connect \Y $not$libresoc.v:51320$3320_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:51270$3322 + cell $not $not$libresoc.v:51322$3322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51270$3322_Y + connect \Y $not$libresoc.v:51322$3322_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:51275$3327 + cell $not $not$libresoc.v:51327$3327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51275$3327_Y + connect \Y $not$libresoc.v:51327$3327_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:51277$3329 + cell $not $not$libresoc.v:51329$3329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51277$3329_Y + connect \Y $not$libresoc.v:51329$3329_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:51283$3335 + cell $not $not$libresoc.v:51335$3335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51283$3335_Y + connect \Y $not$libresoc.v:51335$3335_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:51285$3337 + cell $not $not$libresoc.v:51337$3337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51285$3337_Y + connect \Y $not$libresoc.v:51337$3337_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:51289$3341 + cell $not $not$libresoc.v:51341$3341 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51289$3341_Y + connect \Y $not$libresoc.v:51341$3341_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:51291$3343 + cell $not $not$libresoc.v:51343$3343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51291$3343_Y + connect \Y $not$libresoc.v:51343$3343_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:51293$3345 + cell $not $not$libresoc.v:51345$3345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51293$3345_Y + connect \Y $not$libresoc.v:51345$3345_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:51298$3350 + cell $not $not$libresoc.v:51350$3350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51298$3350_Y + connect \Y $not$libresoc.v:51350$3350_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:51301$3353 + cell $not $not$libresoc.v:51353$3353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51301$3353_Y + connect \Y $not$libresoc.v:51353$3353_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - cell $not $not$libresoc.v:51306$3358 + cell $not $not$libresoc.v:51358$3358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_req_i_1 - connect \Y $not$libresoc.v:51306$3358_Y + connect \Y $not$libresoc.v:51358$3358_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:237" - cell $not $not$libresoc.v:51308$3360 + cell $not $not$libresoc.v:51360$3360 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi_read_log_data - connect \Y $not$libresoc.v:51308$3360_Y + connect \Y $not$libresoc.v:51360$3360_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171" - cell $pos $pos$libresoc.v:51267$3319 + cell $pos $pos$libresoc.v:51319$3319 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 61'0000000000000000000000000000000000000000000000000000000000000 \terminated \core_stopped_i \stopping } - connect \Y $pos$libresoc.v:51267$3319_Y + connect \Y $pos$libresoc.v:51319$3319_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $pos$libresoc.v:51278$3330 + cell $pos $pos$libresoc.v:51330$3330 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \core_dbg_core_dbg_maxvl \core_dbg_core_dbg_vl \core_dbg_core_dbg_srcstep \core_dbg_core_dbg_dststep \core_dbg_core_dbg_subvl \core_dbg_core_dbg_svstep } - connect \Y $pos$libresoc.v:51278$3330_Y + connect \Y $pos$libresoc.v:51330$3330_Y end - attribute \src "libresoc.v:51000.7-51000.20" - process $proc$libresoc.v:51000$3446 + attribute \src "libresoc.v:51052.7-51052.20" + process $proc$libresoc.v:51052$3446 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:51187.7-51187.31" - process $proc$libresoc.v:51187$3447 + attribute \src "libresoc.v:51239.7-51239.31" + process $proc$libresoc.v:51239$3447 assign { } { } assign $1\dmi_read_log_data[0:0] 1'0 sync always sync init update \dmi_read_log_data $1\dmi_read_log_data[0:0] end - attribute \src "libresoc.v:51191.7-51191.33" - process $proc$libresoc.v:51191$3448 + attribute \src "libresoc.v:51243.7-51243.33" + process $proc$libresoc.v:51243$3448 assign { } { } assign $1\dmi_read_log_data_1[0:0] 1'0 sync always sync init update \dmi_read_log_data_1 $1\dmi_read_log_data_1[0:0] end - attribute \src "libresoc.v:51197.7-51197.25" - process $proc$libresoc.v:51197$3449 + attribute \src "libresoc.v:51249.7-51249.25" + process $proc$libresoc.v:51249$3449 assign { } { } assign $1\dmi_req_i_1[0:0] 1'0 sync always sync init update \dmi_req_i_1 $1\dmi_req_i_1[0:0] end - attribute \src "libresoc.v:51203.7-51203.27" - process $proc$libresoc.v:51203$3450 + attribute \src "libresoc.v:51255.7-51255.27" + process $proc$libresoc.v:51255$3450 assign { } { } assign $1\do_dmi_log_rd[0:0] 1'0 sync always sync init update \do_dmi_log_rd $1\do_dmi_log_rd[0:0] end - attribute \src "libresoc.v:51207.7-51207.24" - process $proc$libresoc.v:51207$3451 + attribute \src "libresoc.v:51259.7-51259.24" + process $proc$libresoc.v:51259$3451 assign { } { } assign $1\do_icreset[0:0] 1'0 sync always sync init update \do_icreset $1\do_icreset[0:0] end - attribute \src "libresoc.v:51211.7-51211.22" - process $proc$libresoc.v:51211$3452 + attribute \src "libresoc.v:51263.7-51263.22" + process $proc$libresoc.v:51263$3452 assign { } { } assign $1\do_reset[0:0] 1'0 sync always sync init update \do_reset $1\do_reset[0:0] end - attribute \src "libresoc.v:51215.7-51215.21" - process $proc$libresoc.v:51215$3453 + attribute \src "libresoc.v:51267.7-51267.21" + process $proc$libresoc.v:51267$3453 assign { } { } assign $1\do_step[0:0] 1'0 sync always sync init update \do_step $1\do_step[0:0] end - attribute \src "libresoc.v:51219.13-51219.31" - process $proc$libresoc.v:51219$3454 + attribute \src "libresoc.v:51271.13-51271.31" + process $proc$libresoc.v:51271$3454 assign { } { } assign $1\gspr_index[6:0] 7'0000000 sync always sync init update \gspr_index $1\gspr_index[6:0] end - attribute \src "libresoc.v:51225.14-51225.34" - process $proc$libresoc.v:51225$3455 + attribute \src "libresoc.v:51277.14-51277.34" + process $proc$libresoc.v:51277$3455 assign { } { } assign $1\log_dmi_addr[31:0] 0 sync always sync init update \log_dmi_addr $1\log_dmi_addr[31:0] end - attribute \src "libresoc.v:51237.7-51237.22" - process $proc$libresoc.v:51237$3456 + attribute \src "libresoc.v:51289.7-51289.22" + process $proc$libresoc.v:51289$3456 assign { } { } assign $1\stopping[0:0] 1'0 sync always sync init update \stopping $1\stopping[0:0] end - attribute \src "libresoc.v:51243.7-51243.24" - process $proc$libresoc.v:51243$3457 + attribute \src "libresoc.v:51295.7-51295.24" + process $proc$libresoc.v:51295$3457 assign { } { } assign $1\terminated[0:0] 1'0 sync always sync init update \terminated $1\terminated[0:0] end - attribute \src "libresoc.v:51311.3-51312.51" - process $proc$libresoc.v:51311$3363 + attribute \src "libresoc.v:51363.3-51364.51" + process $proc$libresoc.v:51363$3363 assign { } { } assign $0\dmi_read_log_data[0:0] \dmi_read_log_data$next sync posedge \clk update \dmi_read_log_data $0\dmi_read_log_data[0:0] end - attribute \src "libresoc.v:51313.3-51314.55" - process $proc$libresoc.v:51313$3364 + attribute \src "libresoc.v:51365.3-51366.55" + process $proc$libresoc.v:51365$3364 assign { } { } assign $0\dmi_read_log_data_1[0:0] \dmi_read_log_data_1$next sync posedge \clk update \dmi_read_log_data_1 $0\dmi_read_log_data_1[0:0] end - attribute \src "libresoc.v:51315.3-51316.41" - process $proc$libresoc.v:51315$3365 + attribute \src "libresoc.v:51367.3-51368.41" + process $proc$libresoc.v:51367$3365 assign { } { } assign $0\log_dmi_addr[31:0] \log_dmi_addr$next sync posedge \clk update \log_dmi_addr $0\log_dmi_addr[31:0] end - attribute \src "libresoc.v:51317.3-51318.37" - process $proc$libresoc.v:51317$3366 + attribute \src "libresoc.v:51369.3-51370.37" + process $proc$libresoc.v:51369$3366 assign { } { } assign $0\gspr_index[6:0] \gspr_index$next sync posedge \clk update \gspr_index $0\gspr_index[6:0] end - attribute \src "libresoc.v:51319.3-51320.33" - process $proc$libresoc.v:51319$3367 + attribute \src "libresoc.v:51371.3-51372.33" + process $proc$libresoc.v:51371$3367 assign { } { } assign $0\stopping[0:0] \stopping$next sync posedge \clk update \stopping $0\stopping[0:0] end - attribute \src "libresoc.v:51321.3-51322.37" - process $proc$libresoc.v:51321$3368 + attribute \src "libresoc.v:51373.3-51374.37" + process $proc$libresoc.v:51373$3368 assign { } { } assign $0\terminated[0:0] \terminated$next sync posedge \clk update \terminated $0\terminated[0:0] end - attribute \src "libresoc.v:51323.3-51324.39" - process $proc$libresoc.v:51323$3369 + attribute \src "libresoc.v:51375.3-51376.39" + process $proc$libresoc.v:51375$3369 assign { } { } assign $0\dmi_req_i_1[0:0] \dmi_req_i_1$next sync posedge \clk update \dmi_req_i_1 $0\dmi_req_i_1[0:0] end - attribute \src "libresoc.v:51325.3-51326.43" - process $proc$libresoc.v:51325$3370 + attribute \src "libresoc.v:51377.3-51378.43" + process $proc$libresoc.v:51377$3370 assign { } { } assign $0\do_dmi_log_rd[0:0] \do_dmi_log_rd$next sync posedge \clk update \do_dmi_log_rd $0\do_dmi_log_rd[0:0] end - attribute \src "libresoc.v:51327.3-51328.37" - process $proc$libresoc.v:51327$3371 + attribute \src "libresoc.v:51379.3-51380.37" + process $proc$libresoc.v:51379$3371 assign { } { } assign $0\do_icreset[0:0] \do_icreset$next sync posedge \clk update \do_icreset $0\do_icreset[0:0] end - attribute \src "libresoc.v:51329.3-51330.33" - process $proc$libresoc.v:51329$3372 + attribute \src "libresoc.v:51381.3-51382.33" + process $proc$libresoc.v:51381$3372 assign { } { } assign $0\do_reset[0:0] \do_reset$next sync posedge \clk update \do_reset $0\do_reset[0:0] end - attribute \src "libresoc.v:51331.3-51332.31" - process $proc$libresoc.v:51331$3373 + attribute \src "libresoc.v:51383.3-51384.31" + process $proc$libresoc.v:51383$3373 assign { } { } assign $0\do_step[0:0] \do_step$next sync posedge \clk update \do_step $0\do_step[0:0] end - attribute \src "libresoc.v:51333.3-51350.6" - process $proc$libresoc.v:51333$3374 + attribute \src "libresoc.v:51385.3-51402.6" + process $proc$libresoc.v:51385$3374 assign { } { } assign $0\dmi_ack_o[0:0] $1\dmi_ack_o[0:0] - attribute \src "libresoc.v:51334.5-51334.29" + attribute \src "libresoc.v:51386.5-51386.29" switch \initial - attribute \src "libresoc.v:51334.9-51334.17" + attribute \src "libresoc.v:51386.9-51386.17" case 1'1 case end @@ -91587,14 +91626,14 @@ module \dbg sync always update \dmi_ack_o $0\dmi_ack_o[0:0] end - attribute \src "libresoc.v:51351.3-51360.6" - process $proc$libresoc.v:51351$3375 + attribute \src "libresoc.v:51403.3-51412.6" + process $proc$libresoc.v:51403$3375 assign { } { } assign { } { } assign $0\d_gpr_req[0:0] $1\d_gpr_req[0:0] - attribute \src "libresoc.v:51352.5-51352.29" + attribute \src "libresoc.v:51404.5-51404.29" switch \initial - attribute \src "libresoc.v:51352.9-51352.17" + attribute \src "libresoc.v:51404.9-51404.17" case 1'1 case end @@ -91610,14 +91649,14 @@ module \dbg sync always update \d_gpr_req $0\d_gpr_req[0:0] end - attribute \src "libresoc.v:51361.3-51369.6" - process $proc$libresoc.v:51361$3376 + attribute \src "libresoc.v:51413.3-51421.6" + process $proc$libresoc.v:51413$3376 assign { } { } assign { } { } assign $0\dmi_req_i_1$next[0:0]$3377 $1\dmi_req_i_1$next[0:0]$3378 - attribute \src "libresoc.v:51362.5-51362.29" + attribute \src "libresoc.v:51414.5-51414.29" switch \initial - attribute \src "libresoc.v:51362.9-51362.17" + attribute \src "libresoc.v:51414.9-51414.17" case 1'1 case end @@ -91633,16 +91672,16 @@ module \dbg sync always update \dmi_req_i_1$next $0\dmi_req_i_1$next[0:0]$3377 end - attribute \src "libresoc.v:51370.3-51419.6" - process $proc$libresoc.v:51370$3379 + attribute \src "libresoc.v:51422.3-51471.6" + process $proc$libresoc.v:51422$3379 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\terminated$next[0:0]$3380 $8\terminated$next[0:0]$3388 - attribute \src "libresoc.v:51371.5-51371.29" + attribute \src "libresoc.v:51423.5-51423.29" switch \initial - attribute \src "libresoc.v:51371.9-51371.17" + attribute \src "libresoc.v:51423.9-51423.17" case 1'1 case end @@ -91723,16 +91762,16 @@ module \dbg sync always update \terminated$next $0\terminated$next[0:0]$3380 end - attribute \src "libresoc.v:51420.3-51463.6" - process $proc$libresoc.v:51420$3389 + attribute \src "libresoc.v:51472.3-51515.6" + process $proc$libresoc.v:51472$3389 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\stopping$next[0:0]$3390 $7\stopping$next[0:0]$3397 - attribute \src "libresoc.v:51421.5-51421.29" + attribute \src "libresoc.v:51473.5-51473.29" switch \initial - attribute \src "libresoc.v:51421.9-51421.17" + attribute \src "libresoc.v:51473.9-51473.17" case 1'1 case end @@ -91803,15 +91842,15 @@ module \dbg sync always update \stopping$next $0\stopping$next[0:0]$3390 end - attribute \src "libresoc.v:51464.3-51491.6" - process $proc$libresoc.v:51464$3398 + attribute \src "libresoc.v:51516.3-51543.6" + process $proc$libresoc.v:51516$3398 assign { } { } assign { } { } assign { } { } assign $0\gspr_index$next[6:0]$3399 $4\gspr_index$next[6:0]$3403 - attribute \src "libresoc.v:51465.5-51465.29" + attribute \src "libresoc.v:51517.5-51517.29" switch \initial - attribute \src "libresoc.v:51465.9-51465.17" + attribute \src "libresoc.v:51517.9-51517.17" case 1'1 case end @@ -91857,15 +91896,15 @@ module \dbg sync always update \gspr_index$next $0\gspr_index$next[6:0]$3399 end - attribute \src "libresoc.v:51492.3-51525.6" - process $proc$libresoc.v:51492$3404 + attribute \src "libresoc.v:51544.3-51577.6" + process $proc$libresoc.v:51544$3404 assign { } { } assign { } { } assign { } { } assign $0\log_dmi_addr$next[31:0]$3405 $4\log_dmi_addr$next[31:0]$3409 - attribute \src "libresoc.v:51493.5-51493.29" + attribute \src "libresoc.v:51545.5-51545.29" switch \initial - attribute \src "libresoc.v:51493.9-51493.17" + attribute \src "libresoc.v:51545.9-51545.17" case 1'1 case end @@ -91918,14 +91957,14 @@ module \dbg sync always update \log_dmi_addr$next $0\log_dmi_addr$next[31:0]$3405 end - attribute \src "libresoc.v:51526.3-51534.6" - process $proc$libresoc.v:51526$3410 + attribute \src "libresoc.v:51578.3-51586.6" + process $proc$libresoc.v:51578$3410 assign { } { } assign { } { } assign $0\dmi_read_log_data_1$next[0:0]$3411 $1\dmi_read_log_data_1$next[0:0]$3412 - attribute \src "libresoc.v:51527.5-51527.29" + attribute \src "libresoc.v:51579.5-51579.29" switch \initial - attribute \src "libresoc.v:51527.9-51527.17" + attribute \src "libresoc.v:51579.9-51579.17" case 1'1 case end @@ -91941,14 +91980,14 @@ module \dbg sync always update \dmi_read_log_data_1$next $0\dmi_read_log_data_1$next[0:0]$3411 end - attribute \src "libresoc.v:51535.3-51543.6" - process $proc$libresoc.v:51535$3413 + attribute \src "libresoc.v:51587.3-51595.6" + process $proc$libresoc.v:51587$3413 assign { } { } assign { } { } assign $0\dmi_read_log_data$next[0:0]$3414 $1\dmi_read_log_data$next[0:0]$3415 - attribute \src "libresoc.v:51536.5-51536.29" + attribute \src "libresoc.v:51588.5-51588.29" switch \initial - attribute \src "libresoc.v:51536.9-51536.17" + attribute \src "libresoc.v:51588.9-51588.17" case 1'1 case end @@ -91964,20 +92003,23 @@ module \dbg sync always update \dmi_read_log_data$next $0\dmi_read_log_data$next[0:0]$3414 end - attribute \src "libresoc.v:51544.3-51553.6" - process $proc$libresoc.v:51544$3416 + attribute \src "libresoc.v:51596.3-51608.6" + process $proc$libresoc.v:51596$3416 assign { } { } assign { } { } assign $0\d_cr_req[0:0] $1\d_cr_req[0:0] - attribute \src "libresoc.v:51545.5-51545.29" + attribute \src "libresoc.v:51597.5-51597.29" switch \initial - attribute \src "libresoc.v:51545.9-51545.17" + attribute \src "libresoc.v:51597.9-51597.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:155" switch \dmi_addr_i attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\d_cr_req[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\d_cr_req[0:0] \dmi_req_i @@ -91987,20 +92029,26 @@ module \dbg sync always update \d_cr_req $0\d_cr_req[0:0] end - attribute \src "libresoc.v:51554.3-51563.6" - process $proc$libresoc.v:51554$3417 + attribute \src "libresoc.v:51609.3-51624.6" + process $proc$libresoc.v:51609$3417 assign { } { } assign { } { } assign $0\d_xer_req[0:0] $1\d_xer_req[0:0] - attribute \src "libresoc.v:51555.5-51555.29" + attribute \src "libresoc.v:51610.5-51610.29" switch \initial - attribute \src "libresoc.v:51555.9-51555.17" + attribute \src "libresoc.v:51610.9-51610.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:155" switch \dmi_addr_i attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\d_xer_req[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 4'1000 + assign $1\d_xer_req[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 4'1001 assign { } { } assign $1\d_xer_req[0:0] \dmi_req_i @@ -92010,14 +92058,14 @@ module \dbg sync always update \d_xer_req $0\d_xer_req[0:0] end - attribute \src "libresoc.v:51564.3-51597.6" - process $proc$libresoc.v:51564$3418 + attribute \src "libresoc.v:51625.3-51658.6" + process $proc$libresoc.v:51625$3418 assign { } { } assign { } { } assign $0\dmi_dout[63:0] $1\dmi_dout[63:0] - attribute \src "libresoc.v:51565.5-51565.29" + attribute \src "libresoc.v:51626.5-51626.29" switch \initial - attribute \src "libresoc.v:51565.9-51565.17" + attribute \src "libresoc.v:51626.9-51626.17" case 1'1 case end @@ -92065,15 +92113,15 @@ module \dbg sync always update \dmi_dout $0\dmi_dout[63:0] end - attribute \src "libresoc.v:51598.3-51627.6" - process $proc$libresoc.v:51598$3419 + attribute \src "libresoc.v:51659.3-51688.6" + process $proc$libresoc.v:51659$3419 assign { } { } assign { } { } assign { } { } assign $0\do_step$next[0:0]$3420 $5\do_step$next[0:0]$3425 - attribute \src "libresoc.v:51599.5-51599.29" + attribute \src "libresoc.v:51660.5-51660.29" switch \initial - attribute \src "libresoc.v:51599.9-51599.17" + attribute \src "libresoc.v:51660.9-51660.17" case 1'1 case end @@ -92125,15 +92173,15 @@ module \dbg sync always update \do_step$next $0\do_step$next[0:0]$3420 end - attribute \src "libresoc.v:51628.3-51657.6" - process $proc$libresoc.v:51628$3426 + attribute \src "libresoc.v:51689.3-51718.6" + process $proc$libresoc.v:51689$3426 assign { } { } assign { } { } assign { } { } assign $0\do_reset$next[0:0]$3427 $5\do_reset$next[0:0]$3432 - attribute \src "libresoc.v:51629.5-51629.29" + attribute \src "libresoc.v:51690.5-51690.29" switch \initial - attribute \src "libresoc.v:51629.9-51629.17" + attribute \src "libresoc.v:51690.9-51690.17" case 1'1 case end @@ -92185,15 +92233,15 @@ module \dbg sync always update \do_reset$next $0\do_reset$next[0:0]$3427 end - attribute \src "libresoc.v:51658.3-51687.6" - process $proc$libresoc.v:51658$3433 + attribute \src "libresoc.v:51719.3-51748.6" + process $proc$libresoc.v:51719$3433 assign { } { } assign { } { } assign { } { } assign $0\do_icreset$next[0:0]$3434 $5\do_icreset$next[0:0]$3439 - attribute \src "libresoc.v:51659.5-51659.29" + attribute \src "libresoc.v:51720.5-51720.29" switch \initial - attribute \src "libresoc.v:51659.9-51659.17" + attribute \src "libresoc.v:51720.9-51720.17" case 1'1 case end @@ -92245,15 +92293,15 @@ module \dbg sync always update \do_icreset$next $0\do_icreset$next[0:0]$3434 end - attribute \src "libresoc.v:51688.3-51721.6" - process $proc$libresoc.v:51688$3440 + attribute \src "libresoc.v:51749.3-51782.6" + process $proc$libresoc.v:51749$3440 assign { } { } assign { } { } assign { } { } assign $0\do_dmi_log_rd$next[0:0]$3441 $4\do_dmi_log_rd$next[0:0]$3445 - attribute \src "libresoc.v:51689.5-51689.29" + attribute \src "libresoc.v:51750.5-51750.29" switch \initial - attribute \src "libresoc.v:51689.9-51689.17" + attribute \src "libresoc.v:51750.9-51750.17" case 1'1 case end @@ -92306,69 +92354,69 @@ module \dbg sync always update \do_dmi_log_rd$next $0\do_dmi_log_rd$next[0:0]$3441 end - connect \$9 $not$libresoc.v:51248$3300_Y - connect \$99 $eq$libresoc.v:51249$3301_Y - connect \$101 $eq$libresoc.v:51250$3302_Y - connect \$103 $not$libresoc.v:51251$3303_Y - connect \$105 $and$libresoc.v:51252$3304_Y - connect \$107 $not$libresoc.v:51253$3305_Y - connect \$109 $and$libresoc.v:51254$3306_Y - connect \$111 $eq$libresoc.v:51255$3307_Y - connect \$113 $eq$libresoc.v:51256$3308_Y - connect \$115 $eq$libresoc.v:51257$3309_Y - connect \$118 $add$libresoc.v:51258$3310_Y - connect \$11 $and$libresoc.v:51259$3311_Y - connect \$120 $eq$libresoc.v:51260$3312_Y - connect \$122 $and$libresoc.v:51261$3313_Y - connect \$124 $not$libresoc.v:51262$3314_Y - connect \$126 $and$libresoc.v:51263$3315_Y - connect \$13 $eq$libresoc.v:51264$3316_Y - connect \$15 $eq$libresoc.v:51265$3317_Y - connect \$17 $eq$libresoc.v:51266$3318_Y - connect \$1 $pos$libresoc.v:51267$3319_Y - connect \$19 $not$libresoc.v:51268$3320_Y - connect \$21 $and$libresoc.v:51269$3321_Y - connect \$23 $not$libresoc.v:51270$3322_Y - connect \$25 $and$libresoc.v:51271$3323_Y - connect \$27 $eq$libresoc.v:51272$3324_Y - connect \$29 $eq$libresoc.v:51273$3325_Y - connect \$31 $eq$libresoc.v:51274$3326_Y - connect \$33 $not$libresoc.v:51275$3327_Y - connect \$35 $and$libresoc.v:51276$3328_Y - connect \$37 $not$libresoc.v:51277$3329_Y - connect \$3 $pos$libresoc.v:51278$3330_Y - connect \$39 $and$libresoc.v:51279$3331_Y - connect \$41 $eq$libresoc.v:51280$3332_Y - connect \$43 $eq$libresoc.v:51281$3333_Y - connect \$45 $eq$libresoc.v:51282$3334_Y - connect \$47 $not$libresoc.v:51283$3335_Y - connect \$49 $and$libresoc.v:51284$3336_Y - connect \$51 $not$libresoc.v:51285$3337_Y - connect \$53 $and$libresoc.v:51286$3338_Y - connect \$55 $eq$libresoc.v:51287$3339_Y - connect \$57 $eq$libresoc.v:51288$3340_Y - connect \$5 $not$libresoc.v:51289$3341_Y - connect \$59 $eq$libresoc.v:51290$3342_Y - connect \$61 $not$libresoc.v:51291$3343_Y - connect \$63 $and$libresoc.v:51292$3344_Y - connect \$65 $not$libresoc.v:51293$3345_Y - connect \$67 $and$libresoc.v:51294$3346_Y - connect \$69 $eq$libresoc.v:51295$3347_Y - connect \$71 $eq$libresoc.v:51296$3348_Y - connect \$73 $eq$libresoc.v:51297$3349_Y - connect \$75 $not$libresoc.v:51298$3350_Y - connect \$77 $and$libresoc.v:51299$3351_Y - connect \$7 $and$libresoc.v:51300$3352_Y - connect \$79 $not$libresoc.v:51301$3353_Y - connect \$81 $and$libresoc.v:51302$3354_Y - connect \$83 $eq$libresoc.v:51303$3355_Y - connect \$85 $eq$libresoc.v:51304$3356_Y - connect \$87 $eq$libresoc.v:51305$3357_Y - connect \$89 $not$libresoc.v:51306$3358_Y - connect \$91 $and$libresoc.v:51307$3359_Y - connect \$93 $not$libresoc.v:51308$3360_Y - connect \$95 $and$libresoc.v:51309$3361_Y - connect \$97 $eq$libresoc.v:51310$3362_Y + connect \$9 $not$libresoc.v:51300$3300_Y + connect \$99 $eq$libresoc.v:51301$3301_Y + connect \$101 $eq$libresoc.v:51302$3302_Y + connect \$103 $not$libresoc.v:51303$3303_Y + connect \$105 $and$libresoc.v:51304$3304_Y + connect \$107 $not$libresoc.v:51305$3305_Y + connect \$109 $and$libresoc.v:51306$3306_Y + connect \$111 $eq$libresoc.v:51307$3307_Y + connect \$113 $eq$libresoc.v:51308$3308_Y + connect \$115 $eq$libresoc.v:51309$3309_Y + connect \$118 $add$libresoc.v:51310$3310_Y + connect \$11 $and$libresoc.v:51311$3311_Y + connect \$120 $eq$libresoc.v:51312$3312_Y + connect \$122 $and$libresoc.v:51313$3313_Y + connect \$124 $not$libresoc.v:51314$3314_Y + connect \$126 $and$libresoc.v:51315$3315_Y + connect \$13 $eq$libresoc.v:51316$3316_Y + connect \$15 $eq$libresoc.v:51317$3317_Y + connect \$17 $eq$libresoc.v:51318$3318_Y + connect \$1 $pos$libresoc.v:51319$3319_Y + connect \$19 $not$libresoc.v:51320$3320_Y + connect \$21 $and$libresoc.v:51321$3321_Y + connect \$23 $not$libresoc.v:51322$3322_Y + connect \$25 $and$libresoc.v:51323$3323_Y + connect \$27 $eq$libresoc.v:51324$3324_Y + connect \$29 $eq$libresoc.v:51325$3325_Y + connect \$31 $eq$libresoc.v:51326$3326_Y + connect \$33 $not$libresoc.v:51327$3327_Y + connect \$35 $and$libresoc.v:51328$3328_Y + connect \$37 $not$libresoc.v:51329$3329_Y + connect \$3 $pos$libresoc.v:51330$3330_Y + connect \$39 $and$libresoc.v:51331$3331_Y + connect \$41 $eq$libresoc.v:51332$3332_Y + connect \$43 $eq$libresoc.v:51333$3333_Y + connect \$45 $eq$libresoc.v:51334$3334_Y + connect \$47 $not$libresoc.v:51335$3335_Y + connect \$49 $and$libresoc.v:51336$3336_Y + connect \$51 $not$libresoc.v:51337$3337_Y + connect \$53 $and$libresoc.v:51338$3338_Y + connect \$55 $eq$libresoc.v:51339$3339_Y + connect \$57 $eq$libresoc.v:51340$3340_Y + connect \$5 $not$libresoc.v:51341$3341_Y + connect \$59 $eq$libresoc.v:51342$3342_Y + connect \$61 $not$libresoc.v:51343$3343_Y + connect \$63 $and$libresoc.v:51344$3344_Y + connect \$65 $not$libresoc.v:51345$3345_Y + connect \$67 $and$libresoc.v:51346$3346_Y + connect \$69 $eq$libresoc.v:51347$3347_Y + connect \$71 $eq$libresoc.v:51348$3348_Y + connect \$73 $eq$libresoc.v:51349$3349_Y + connect \$75 $not$libresoc.v:51350$3350_Y + connect \$77 $and$libresoc.v:51351$3351_Y + connect \$7 $and$libresoc.v:51352$3352_Y + connect \$79 $not$libresoc.v:51353$3353_Y + connect \$81 $and$libresoc.v:51354$3354_Y + connect \$83 $eq$libresoc.v:51355$3355_Y + connect \$85 $eq$libresoc.v:51356$3356_Y + connect \$87 $eq$libresoc.v:51357$3357_Y + connect \$89 $not$libresoc.v:51358$3358_Y + connect \$91 $and$libresoc.v:51359$3359_Y + connect \$93 $not$libresoc.v:51360$3360_Y + connect \$95 $and$libresoc.v:51361$3361_Y + connect \$97 $eq$libresoc.v:51362$3362_Y connect \$117 \$118 connect \log_write_addr_o 0 connect \log_dmi_data 64'0000000000000000000000000000000000000000000000000000000000000000 @@ -92379,71 +92427,71 @@ module \dbg connect \d_gpr_addr \gspr_index connect \stat_reg \$1 end -attribute \src "libresoc.v:51735.1-53785.10" +attribute \src "libresoc.v:51796.1-53846.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec" attribute \generator "nMigen" module \dec - attribute \src "libresoc.v:53346.3-53379.6" + attribute \src "libresoc.v:53407.3-53440.6" wire width 3 $0\ALU_cr_in[2:0] - attribute \src "libresoc.v:53380.3-53413.6" + attribute \src "libresoc.v:53441.3-53474.6" wire width 3 $0\ALU_cr_out[2:0] - attribute \src "libresoc.v:53006.3-53039.6" + attribute \src "libresoc.v:53067.3-53100.6" wire width 2 $0\ALU_cry_in[1:0] - attribute \src "libresoc.v:53108.3-53141.6" + attribute \src "libresoc.v:53169.3-53202.6" wire $0\ALU_cry_out[0:0] - attribute \src "libresoc.v:53210.3-53243.6" + attribute \src "libresoc.v:53271.3-53304.6" wire width 14 $0\ALU_function_unit[13:0] - attribute \src "libresoc.v:53278.3-53311.6" + attribute \src "libresoc.v:53339.3-53372.6" wire width 3 $0\ALU_in1_sel[2:0] - attribute \src "libresoc.v:53312.3-53345.6" + attribute \src "libresoc.v:53373.3-53406.6" wire width 4 $0\ALU_in2_sel[3:0] - attribute \src "libresoc.v:53244.3-53277.6" + attribute \src "libresoc.v:53305.3-53338.6" wire width 7 $0\ALU_internal_op[6:0] - attribute \src "libresoc.v:53040.3-53073.6" + attribute \src "libresoc.v:53101.3-53134.6" wire $0\ALU_inv_a[0:0] - attribute \src "libresoc.v:53074.3-53107.6" + attribute \src "libresoc.v:53135.3-53168.6" wire $0\ALU_inv_out[0:0] - attribute \src "libresoc.v:53142.3-53175.6" + attribute \src "libresoc.v:53203.3-53236.6" wire $0\ALU_is_32b[0:0] - attribute \src "libresoc.v:53414.3-53447.6" + attribute \src "libresoc.v:53475.3-53508.6" wire width 4 $0\ALU_ldst_len[3:0] - attribute \src "libresoc.v:52972.3-53005.6" + attribute \src "libresoc.v:53033.3-53066.6" wire width 2 $0\ALU_rc_sel[1:0] - attribute \src "libresoc.v:53176.3-53209.6" + attribute \src "libresoc.v:53237.3-53270.6" wire $0\ALU_sgn[0:0] - attribute \src "libresoc.v:51736.7-51736.20" + attribute \src "libresoc.v:51797.7-51797.20" wire $0\initial[0:0] - attribute \src "libresoc.v:53346.3-53379.6" + attribute \src "libresoc.v:53407.3-53440.6" wire width 3 $1\ALU_cr_in[2:0] - attribute \src "libresoc.v:53380.3-53413.6" + attribute \src "libresoc.v:53441.3-53474.6" wire width 3 $1\ALU_cr_out[2:0] - attribute \src "libresoc.v:53006.3-53039.6" + attribute \src "libresoc.v:53067.3-53100.6" wire width 2 $1\ALU_cry_in[1:0] - attribute \src "libresoc.v:53108.3-53141.6" + attribute \src "libresoc.v:53169.3-53202.6" wire $1\ALU_cry_out[0:0] - attribute \src "libresoc.v:53210.3-53243.6" + attribute \src "libresoc.v:53271.3-53304.6" wire width 14 $1\ALU_function_unit[13:0] - attribute \src "libresoc.v:53278.3-53311.6" + attribute \src "libresoc.v:53339.3-53372.6" wire width 3 $1\ALU_in1_sel[2:0] - attribute \src "libresoc.v:53312.3-53345.6" + attribute \src "libresoc.v:53373.3-53406.6" wire width 4 $1\ALU_in2_sel[3:0] - attribute \src "libresoc.v:53244.3-53277.6" + attribute \src "libresoc.v:53305.3-53338.6" wire width 7 $1\ALU_internal_op[6:0] - attribute \src "libresoc.v:53040.3-53073.6" + attribute \src "libresoc.v:53101.3-53134.6" wire $1\ALU_inv_a[0:0] - attribute \src "libresoc.v:53074.3-53107.6" + attribute \src "libresoc.v:53135.3-53168.6" wire $1\ALU_inv_out[0:0] - attribute \src "libresoc.v:53142.3-53175.6" + attribute \src "libresoc.v:53203.3-53236.6" wire $1\ALU_is_32b[0:0] - attribute \src "libresoc.v:53414.3-53447.6" + attribute \src "libresoc.v:53475.3-53508.6" wire width 4 $1\ALU_ldst_len[3:0] - attribute \src "libresoc.v:52972.3-53005.6" + attribute \src "libresoc.v:53033.3-53066.6" wire width 2 $1\ALU_rc_sel[1:0] - attribute \src "libresoc.v:53176.3-53209.6" + attribute \src "libresoc.v:53237.3-53270.6" wire $1\ALU_sgn[0:0] - attribute \src "libresoc.v:52937.17-52937.211" - wire width 32 $ternary$libresoc.v:52937$3458_Y + attribute \src "libresoc.v:52998.17-52998.211" + wire width 32 $ternary$libresoc.v:52998$3458_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" @@ -93625,7 +93673,7 @@ module \dec wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:51736.7-51736.15" + attribute \src "libresoc.v:51797.7-51797.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in @@ -93634,15 +93682,15 @@ module \dec attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 27 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" - cell $mux $ternary$libresoc.v:52937$3458 + cell $mux $ternary$libresoc.v:52998$3458 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:52937$3458_Y + connect \Y $ternary$libresoc.v:52998$3458_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:52938.13-52954.4" + attribute \src "libresoc.v:52999.13-53015.4" cell \ALU_dec19 \ALU_dec19 connect \ALU_dec19_cr_in \ALU_dec19_ALU_dec19_cr_in connect \ALU_dec19_cr_out \ALU_dec19_ALU_dec19_cr_out @@ -93661,7 +93709,7 @@ module \dec connect \opcode_in \ALU_dec19_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:52955.13-52971.4" + attribute \src "libresoc.v:53016.13-53032.4" cell \ALU_dec31 \ALU_dec31 connect \ALU_dec31_cr_in \ALU_dec31_ALU_dec31_cr_in connect \ALU_dec31_cr_out \ALU_dec31_ALU_dec31_cr_out @@ -93679,22 +93727,22 @@ module \dec connect \ALU_dec31_sgn \ALU_dec31_ALU_dec31_sgn connect \opcode_in \ALU_dec31_opcode_in end - attribute \src "libresoc.v:51736.7-51736.20" - process $proc$libresoc.v:51736$3473 + attribute \src "libresoc.v:51797.7-51797.20" + process $proc$libresoc.v:51797$3473 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:52972.3-53005.6" - process $proc$libresoc.v:52972$3459 + attribute \src "libresoc.v:53033.3-53066.6" + process $proc$libresoc.v:53033$3459 assign { } { } assign { } { } assign $0\ALU_rc_sel[1:0] $1\ALU_rc_sel[1:0] - attribute \src "libresoc.v:52973.5-52973.29" + attribute \src "libresoc.v:53034.5-53034.29" switch \initial - attribute \src "libresoc.v:52973.9-52973.17" + attribute \src "libresoc.v:53034.9-53034.17" case 1'1 case end @@ -93742,14 +93790,14 @@ module \dec sync always update \ALU_rc_sel $0\ALU_rc_sel[1:0] end - attribute \src "libresoc.v:53006.3-53039.6" - process $proc$libresoc.v:53006$3460 + attribute \src "libresoc.v:53067.3-53100.6" + process $proc$libresoc.v:53067$3460 assign { } { } assign { } { } assign $0\ALU_cry_in[1:0] $1\ALU_cry_in[1:0] - attribute \src "libresoc.v:53007.5-53007.29" + attribute \src "libresoc.v:53068.5-53068.29" switch \initial - attribute \src "libresoc.v:53007.9-53007.17" + attribute \src "libresoc.v:53068.9-53068.17" case 1'1 case end @@ -93797,14 +93845,14 @@ module \dec sync always update \ALU_cry_in $0\ALU_cry_in[1:0] end - attribute \src "libresoc.v:53040.3-53073.6" - process $proc$libresoc.v:53040$3461 + attribute \src "libresoc.v:53101.3-53134.6" + process $proc$libresoc.v:53101$3461 assign { } { } assign { } { } assign $0\ALU_inv_a[0:0] $1\ALU_inv_a[0:0] - attribute \src "libresoc.v:53041.5-53041.29" + attribute \src "libresoc.v:53102.5-53102.29" switch \initial - attribute \src "libresoc.v:53041.9-53041.17" + attribute \src "libresoc.v:53102.9-53102.17" case 1'1 case end @@ -93852,14 +93900,14 @@ module \dec sync always update \ALU_inv_a $0\ALU_inv_a[0:0] end - attribute \src "libresoc.v:53074.3-53107.6" - process $proc$libresoc.v:53074$3462 + attribute \src "libresoc.v:53135.3-53168.6" + process $proc$libresoc.v:53135$3462 assign { } { } assign { } { } assign $0\ALU_inv_out[0:0] $1\ALU_inv_out[0:0] - attribute \src "libresoc.v:53075.5-53075.29" + attribute \src "libresoc.v:53136.5-53136.29" switch \initial - attribute \src "libresoc.v:53075.9-53075.17" + attribute \src "libresoc.v:53136.9-53136.17" case 1'1 case end @@ -93907,14 +93955,14 @@ module \dec sync always update \ALU_inv_out $0\ALU_inv_out[0:0] end - attribute \src "libresoc.v:53108.3-53141.6" - process $proc$libresoc.v:53108$3463 + attribute \src "libresoc.v:53169.3-53202.6" + process $proc$libresoc.v:53169$3463 assign { } { } assign { } { } assign $0\ALU_cry_out[0:0] $1\ALU_cry_out[0:0] - attribute \src "libresoc.v:53109.5-53109.29" + attribute \src "libresoc.v:53170.5-53170.29" switch \initial - attribute \src "libresoc.v:53109.9-53109.17" + attribute \src "libresoc.v:53170.9-53170.17" case 1'1 case end @@ -93962,14 +94010,14 @@ module \dec sync always update \ALU_cry_out $0\ALU_cry_out[0:0] end - attribute \src "libresoc.v:53142.3-53175.6" - process $proc$libresoc.v:53142$3464 + attribute \src "libresoc.v:53203.3-53236.6" + process $proc$libresoc.v:53203$3464 assign { } { } assign { } { } assign $0\ALU_is_32b[0:0] $1\ALU_is_32b[0:0] - attribute \src "libresoc.v:53143.5-53143.29" + attribute \src "libresoc.v:53204.5-53204.29" switch \initial - attribute \src "libresoc.v:53143.9-53143.17" + attribute \src "libresoc.v:53204.9-53204.17" case 1'1 case end @@ -94017,14 +94065,14 @@ module \dec sync always update \ALU_is_32b $0\ALU_is_32b[0:0] end - attribute \src "libresoc.v:53176.3-53209.6" - process $proc$libresoc.v:53176$3465 + attribute \src "libresoc.v:53237.3-53270.6" + process $proc$libresoc.v:53237$3465 assign { } { } assign { } { } assign $0\ALU_sgn[0:0] $1\ALU_sgn[0:0] - attribute \src "libresoc.v:53177.5-53177.29" + attribute \src "libresoc.v:53238.5-53238.29" switch \initial - attribute \src "libresoc.v:53177.9-53177.17" + attribute \src "libresoc.v:53238.9-53238.17" case 1'1 case end @@ -94072,14 +94120,14 @@ module \dec sync always update \ALU_sgn $0\ALU_sgn[0:0] end - attribute \src "libresoc.v:53210.3-53243.6" - process $proc$libresoc.v:53210$3466 + attribute \src "libresoc.v:53271.3-53304.6" + process $proc$libresoc.v:53271$3466 assign { } { } assign { } { } assign $0\ALU_function_unit[13:0] $1\ALU_function_unit[13:0] - attribute \src "libresoc.v:53211.5-53211.29" + attribute \src "libresoc.v:53272.5-53272.29" switch \initial - attribute \src "libresoc.v:53211.9-53211.17" + attribute \src "libresoc.v:53272.9-53272.17" case 1'1 case end @@ -94127,14 +94175,14 @@ module \dec sync always update \ALU_function_unit $0\ALU_function_unit[13:0] end - attribute \src "libresoc.v:53244.3-53277.6" - process $proc$libresoc.v:53244$3467 + attribute \src "libresoc.v:53305.3-53338.6" + process $proc$libresoc.v:53305$3467 assign { } { } assign { } { } assign $0\ALU_internal_op[6:0] $1\ALU_internal_op[6:0] - attribute \src "libresoc.v:53245.5-53245.29" + attribute \src "libresoc.v:53306.5-53306.29" switch \initial - attribute \src "libresoc.v:53245.9-53245.17" + attribute \src "libresoc.v:53306.9-53306.17" case 1'1 case end @@ -94182,14 +94230,14 @@ module \dec sync always update \ALU_internal_op $0\ALU_internal_op[6:0] end - attribute \src "libresoc.v:53278.3-53311.6" - process $proc$libresoc.v:53278$3468 + attribute \src "libresoc.v:53339.3-53372.6" + process $proc$libresoc.v:53339$3468 assign { } { } assign { } { } assign $0\ALU_in1_sel[2:0] $1\ALU_in1_sel[2:0] - attribute \src "libresoc.v:53279.5-53279.29" + attribute \src "libresoc.v:53340.5-53340.29" switch \initial - attribute \src "libresoc.v:53279.9-53279.17" + attribute \src "libresoc.v:53340.9-53340.17" case 1'1 case end @@ -94237,14 +94285,14 @@ module \dec sync always update \ALU_in1_sel $0\ALU_in1_sel[2:0] end - attribute \src "libresoc.v:53312.3-53345.6" - process $proc$libresoc.v:53312$3469 + attribute \src "libresoc.v:53373.3-53406.6" + process $proc$libresoc.v:53373$3469 assign { } { } assign { } { } assign $0\ALU_in2_sel[3:0] $1\ALU_in2_sel[3:0] - attribute \src "libresoc.v:53313.5-53313.29" + attribute \src "libresoc.v:53374.5-53374.29" switch \initial - attribute \src "libresoc.v:53313.9-53313.17" + attribute \src "libresoc.v:53374.9-53374.17" case 1'1 case end @@ -94292,14 +94340,14 @@ module \dec sync always update \ALU_in2_sel $0\ALU_in2_sel[3:0] end - attribute \src "libresoc.v:53346.3-53379.6" - process $proc$libresoc.v:53346$3470 + attribute \src "libresoc.v:53407.3-53440.6" + process $proc$libresoc.v:53407$3470 assign { } { } assign { } { } assign $0\ALU_cr_in[2:0] $1\ALU_cr_in[2:0] - attribute \src "libresoc.v:53347.5-53347.29" + attribute \src "libresoc.v:53408.5-53408.29" switch \initial - attribute \src "libresoc.v:53347.9-53347.17" + attribute \src "libresoc.v:53408.9-53408.17" case 1'1 case end @@ -94347,14 +94395,14 @@ module \dec sync always update \ALU_cr_in $0\ALU_cr_in[2:0] end - attribute \src "libresoc.v:53380.3-53413.6" - process $proc$libresoc.v:53380$3471 + attribute \src "libresoc.v:53441.3-53474.6" + process $proc$libresoc.v:53441$3471 assign { } { } assign { } { } assign $0\ALU_cr_out[2:0] $1\ALU_cr_out[2:0] - attribute \src "libresoc.v:53381.5-53381.29" + attribute \src "libresoc.v:53442.5-53442.29" switch \initial - attribute \src "libresoc.v:53381.9-53381.17" + attribute \src "libresoc.v:53442.9-53442.17" case 1'1 case end @@ -94402,14 +94450,14 @@ module \dec sync always update \ALU_cr_out $0\ALU_cr_out[2:0] end - attribute \src "libresoc.v:53414.3-53447.6" - process $proc$libresoc.v:53414$3472 + attribute \src "libresoc.v:53475.3-53508.6" + process $proc$libresoc.v:53475$3472 assign { } { } assign { } { } assign $0\ALU_ldst_len[3:0] $1\ALU_ldst_len[3:0] - attribute \src "libresoc.v:53415.5-53415.29" + attribute \src "libresoc.v:53476.5-53476.29" switch \initial - attribute \src "libresoc.v:53415.9-53415.17" + attribute \src "libresoc.v:53476.9-53476.17" case 1'1 case end @@ -94457,7 +94505,7 @@ module \dec sync always update \ALU_ldst_len $0\ALU_ldst_len[3:0] end - connect \$1 $ternary$libresoc.v:52937$3458_Y + connect \$1 $ternary$libresoc.v:52998$3458_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -94796,35 +94844,35 @@ module \dec connect \ALU_dec19_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:53789.1-55254.10" +attribute \src "libresoc.v:53850.1-55315.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec" attribute \generator "nMigen" module \dec$138 - attribute \src "libresoc.v:54878.3-54890.6" + attribute \src "libresoc.v:54939.3-54951.6" wire width 3 $0\CR_cr_in[2:0] - attribute \src "libresoc.v:54891.3-54903.6" + attribute \src "libresoc.v:54952.3-54964.6" wire width 3 $0\CR_cr_out[2:0] - attribute \src "libresoc.v:54852.3-54864.6" + attribute \src "libresoc.v:54913.3-54925.6" wire width 14 $0\CR_function_unit[13:0] - attribute \src "libresoc.v:54865.3-54877.6" + attribute \src "libresoc.v:54926.3-54938.6" wire width 7 $0\CR_internal_op[6:0] - attribute \src "libresoc.v:54904.3-54916.6" + attribute \src "libresoc.v:54965.3-54977.6" wire width 2 $0\CR_rc_sel[1:0] - attribute \src "libresoc.v:53790.7-53790.20" + attribute \src "libresoc.v:53851.7-53851.20" wire $0\initial[0:0] - attribute \src "libresoc.v:54878.3-54890.6" + attribute \src "libresoc.v:54939.3-54951.6" wire width 3 $1\CR_cr_in[2:0] - attribute \src "libresoc.v:54891.3-54903.6" + attribute \src "libresoc.v:54952.3-54964.6" wire width 3 $1\CR_cr_out[2:0] - attribute \src "libresoc.v:54852.3-54864.6" + attribute \src "libresoc.v:54913.3-54925.6" wire width 14 $1\CR_function_unit[13:0] - attribute \src "libresoc.v:54865.3-54877.6" + attribute \src "libresoc.v:54926.3-54938.6" wire width 7 $1\CR_internal_op[6:0] - attribute \src "libresoc.v:54904.3-54916.6" + attribute \src "libresoc.v:54965.3-54977.6" wire width 2 $1\CR_rc_sel[1:0] - attribute \src "libresoc.v:54835.17-54835.211" - wire width 32 $ternary$libresoc.v:54835$3474_Y + attribute \src "libresoc.v:54896.17-54896.211" + wire width 32 $ternary$libresoc.v:54896$3474_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" @@ -95859,7 +95907,7 @@ module \dec$138 wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:53790.7-53790.15" + attribute \src "libresoc.v:53851.7-53851.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in @@ -95868,15 +95916,15 @@ module \dec$138 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 10 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" - cell $mux $ternary$libresoc.v:54835$3474 + cell $mux $ternary$libresoc.v:54896$3474 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:54835$3474_Y + connect \Y $ternary$libresoc.v:54896$3474_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:54836.12-54843.4" + attribute \src "libresoc.v:54897.12-54904.4" cell \CR_dec19 \CR_dec19 connect \CR_dec19_cr_in \CR_dec19_CR_dec19_cr_in connect \CR_dec19_cr_out \CR_dec19_CR_dec19_cr_out @@ -95886,7 +95934,7 @@ module \dec$138 connect \opcode_in \CR_dec19_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:54844.12-54851.4" + attribute \src "libresoc.v:54905.12-54912.4" cell \CR_dec31 \CR_dec31 connect \CR_dec31_cr_in \CR_dec31_CR_dec31_cr_in connect \CR_dec31_cr_out \CR_dec31_CR_dec31_cr_out @@ -95895,22 +95943,22 @@ module \dec$138 connect \CR_dec31_rc_sel \CR_dec31_CR_dec31_rc_sel connect \opcode_in \CR_dec31_opcode_in end - attribute \src "libresoc.v:53790.7-53790.20" - process $proc$libresoc.v:53790$3480 + attribute \src "libresoc.v:53851.7-53851.20" + process $proc$libresoc.v:53851$3480 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:54852.3-54864.6" - process $proc$libresoc.v:54852$3475 + attribute \src "libresoc.v:54913.3-54925.6" + process $proc$libresoc.v:54913$3475 assign { } { } assign { } { } assign $0\CR_function_unit[13:0] $1\CR_function_unit[13:0] - attribute \src "libresoc.v:54853.5-54853.29" + attribute \src "libresoc.v:54914.5-54914.29" switch \initial - attribute \src "libresoc.v:54853.9-54853.17" + attribute \src "libresoc.v:54914.9-54914.17" case 1'1 case end @@ -95930,14 +95978,14 @@ module \dec$138 sync always update \CR_function_unit $0\CR_function_unit[13:0] end - attribute \src "libresoc.v:54865.3-54877.6" - process $proc$libresoc.v:54865$3476 + attribute \src "libresoc.v:54926.3-54938.6" + process $proc$libresoc.v:54926$3476 assign { } { } assign { } { } assign $0\CR_internal_op[6:0] $1\CR_internal_op[6:0] - attribute \src "libresoc.v:54866.5-54866.29" + attribute \src "libresoc.v:54927.5-54927.29" switch \initial - attribute \src "libresoc.v:54866.9-54866.17" + attribute \src "libresoc.v:54927.9-54927.17" case 1'1 case end @@ -95957,14 +96005,14 @@ module \dec$138 sync always update \CR_internal_op $0\CR_internal_op[6:0] end - attribute \src "libresoc.v:54878.3-54890.6" - process $proc$libresoc.v:54878$3477 + attribute \src "libresoc.v:54939.3-54951.6" + process $proc$libresoc.v:54939$3477 assign { } { } assign { } { } assign $0\CR_cr_in[2:0] $1\CR_cr_in[2:0] - attribute \src "libresoc.v:54879.5-54879.29" + attribute \src "libresoc.v:54940.5-54940.29" switch \initial - attribute \src "libresoc.v:54879.9-54879.17" + attribute \src "libresoc.v:54940.9-54940.17" case 1'1 case end @@ -95984,14 +96032,14 @@ module \dec$138 sync always update \CR_cr_in $0\CR_cr_in[2:0] end - attribute \src "libresoc.v:54891.3-54903.6" - process $proc$libresoc.v:54891$3478 + attribute \src "libresoc.v:54952.3-54964.6" + process $proc$libresoc.v:54952$3478 assign { } { } assign { } { } assign $0\CR_cr_out[2:0] $1\CR_cr_out[2:0] - attribute \src "libresoc.v:54892.5-54892.29" + attribute \src "libresoc.v:54953.5-54953.29" switch \initial - attribute \src "libresoc.v:54892.9-54892.17" + attribute \src "libresoc.v:54953.9-54953.17" case 1'1 case end @@ -96011,14 +96059,14 @@ module \dec$138 sync always update \CR_cr_out $0\CR_cr_out[2:0] end - attribute \src "libresoc.v:54904.3-54916.6" - process $proc$libresoc.v:54904$3479 + attribute \src "libresoc.v:54965.3-54977.6" + process $proc$libresoc.v:54965$3479 assign { } { } assign { } { } assign $0\CR_rc_sel[1:0] $1\CR_rc_sel[1:0] - attribute \src "libresoc.v:54905.5-54905.29" + attribute \src "libresoc.v:54966.5-54966.29" switch \initial - attribute \src "libresoc.v:54905.9-54905.17" + attribute \src "libresoc.v:54966.9-54966.17" case 1'1 case end @@ -96038,7 +96086,7 @@ module \dec$138 sync always update \CR_rc_sel $0\CR_rc_sel[1:0] end - connect \$1 $ternary$libresoc.v:54835$3474_Y + connect \$1 $ternary$libresoc.v:54896$3474_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -96377,47 +96425,47 @@ module \dec$138 connect \CR_dec19_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:55258.1-56703.10" +attribute \src "libresoc.v:55319.1-56764.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec" attribute \generator "nMigen" module \dec$141 - attribute \src "libresoc.v:56287.3-56302.6" + attribute \src "libresoc.v:56348.3-56363.6" wire width 3 $0\BRANCH_cr_in[2:0] - attribute \src "libresoc.v:56303.3-56318.6" + attribute \src "libresoc.v:56364.3-56379.6" wire width 3 $0\BRANCH_cr_out[2:0] - attribute \src "libresoc.v:56239.3-56254.6" + attribute \src "libresoc.v:56300.3-56315.6" wire width 14 $0\BRANCH_function_unit[13:0] - attribute \src "libresoc.v:56271.3-56286.6" + attribute \src "libresoc.v:56332.3-56347.6" wire width 4 $0\BRANCH_in2_sel[3:0] - attribute \src "libresoc.v:56255.3-56270.6" + attribute \src "libresoc.v:56316.3-56331.6" wire width 7 $0\BRANCH_internal_op[6:0] - attribute \src "libresoc.v:56335.3-56350.6" + attribute \src "libresoc.v:56396.3-56411.6" wire $0\BRANCH_is_32b[0:0] - attribute \src "libresoc.v:56351.3-56366.6" + attribute \src "libresoc.v:56412.3-56427.6" wire $0\BRANCH_lk[0:0] - attribute \src "libresoc.v:56319.3-56334.6" + attribute \src "libresoc.v:56380.3-56395.6" wire width 2 $0\BRANCH_rc_sel[1:0] - attribute \src "libresoc.v:55259.7-55259.20" + attribute \src "libresoc.v:55320.7-55320.20" wire $0\initial[0:0] - attribute \src "libresoc.v:56287.3-56302.6" + attribute \src "libresoc.v:56348.3-56363.6" wire width 3 $1\BRANCH_cr_in[2:0] - attribute \src "libresoc.v:56303.3-56318.6" + attribute \src "libresoc.v:56364.3-56379.6" wire width 3 $1\BRANCH_cr_out[2:0] - attribute \src "libresoc.v:56239.3-56254.6" + attribute \src "libresoc.v:56300.3-56315.6" wire width 14 $1\BRANCH_function_unit[13:0] - attribute \src "libresoc.v:56271.3-56286.6" + attribute \src "libresoc.v:56332.3-56347.6" wire width 4 $1\BRANCH_in2_sel[3:0] - attribute \src "libresoc.v:56255.3-56270.6" + attribute \src "libresoc.v:56316.3-56331.6" wire width 7 $1\BRANCH_internal_op[6:0] - attribute \src "libresoc.v:56335.3-56350.6" + attribute \src "libresoc.v:56396.3-56411.6" wire $1\BRANCH_is_32b[0:0] - attribute \src "libresoc.v:56351.3-56366.6" + attribute \src "libresoc.v:56412.3-56427.6" wire $1\BRANCH_lk[0:0] - attribute \src "libresoc.v:56319.3-56334.6" + attribute \src "libresoc.v:56380.3-56395.6" wire width 2 $1\BRANCH_rc_sel[1:0] - attribute \src "libresoc.v:56227.17-56227.211" - wire width 32 $ternary$libresoc.v:56227$3481_Y + attribute \src "libresoc.v:56288.17-56288.211" + wire width 32 $ternary$libresoc.v:56288$3481_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" @@ -97372,7 +97420,7 @@ module \dec$141 wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:55259.7-55259.15" + attribute \src "libresoc.v:55320.7-55320.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in @@ -97381,15 +97429,15 @@ module \dec$141 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 21 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" - cell $mux $ternary$libresoc.v:56227$3481 + cell $mux $ternary$libresoc.v:56288$3481 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:56227$3481_Y + connect \Y $ternary$libresoc.v:56288$3481_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:56228.16-56238.4" + attribute \src "libresoc.v:56289.16-56299.4" cell \BRANCH_dec19 \BRANCH_dec19 connect \BRANCH_dec19_cr_in \BRANCH_dec19_BRANCH_dec19_cr_in connect \BRANCH_dec19_cr_out \BRANCH_dec19_BRANCH_dec19_cr_out @@ -97401,22 +97449,22 @@ module \dec$141 connect \BRANCH_dec19_rc_sel \BRANCH_dec19_BRANCH_dec19_rc_sel connect \opcode_in \BRANCH_dec19_opcode_in end - attribute \src "libresoc.v:55259.7-55259.20" - process $proc$libresoc.v:55259$3490 + attribute \src "libresoc.v:55320.7-55320.20" + process $proc$libresoc.v:55320$3490 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:56239.3-56254.6" - process $proc$libresoc.v:56239$3482 + attribute \src "libresoc.v:56300.3-56315.6" + process $proc$libresoc.v:56300$3482 assign { } { } assign { } { } assign $0\BRANCH_function_unit[13:0] $1\BRANCH_function_unit[13:0] - attribute \src "libresoc.v:56240.5-56240.29" + attribute \src "libresoc.v:56301.5-56301.29" switch \initial - attribute \src "libresoc.v:56240.9-56240.17" + attribute \src "libresoc.v:56301.9-56301.17" case 1'1 case end @@ -97440,14 +97488,14 @@ module \dec$141 sync always update \BRANCH_function_unit $0\BRANCH_function_unit[13:0] end - attribute \src "libresoc.v:56255.3-56270.6" - process $proc$libresoc.v:56255$3483 + attribute \src "libresoc.v:56316.3-56331.6" + process $proc$libresoc.v:56316$3483 assign { } { } assign { } { } assign $0\BRANCH_internal_op[6:0] $1\BRANCH_internal_op[6:0] - attribute \src "libresoc.v:56256.5-56256.29" + attribute \src "libresoc.v:56317.5-56317.29" switch \initial - attribute \src "libresoc.v:56256.9-56256.17" + attribute \src "libresoc.v:56317.9-56317.17" case 1'1 case end @@ -97471,14 +97519,14 @@ module \dec$141 sync always update \BRANCH_internal_op $0\BRANCH_internal_op[6:0] end - attribute \src "libresoc.v:56271.3-56286.6" - process $proc$libresoc.v:56271$3484 + attribute \src "libresoc.v:56332.3-56347.6" + process $proc$libresoc.v:56332$3484 assign { } { } assign { } { } assign $0\BRANCH_in2_sel[3:0] $1\BRANCH_in2_sel[3:0] - attribute \src "libresoc.v:56272.5-56272.29" + attribute \src "libresoc.v:56333.5-56333.29" switch \initial - attribute \src "libresoc.v:56272.9-56272.17" + attribute \src "libresoc.v:56333.9-56333.17" case 1'1 case end @@ -97502,14 +97550,14 @@ module \dec$141 sync always update \BRANCH_in2_sel $0\BRANCH_in2_sel[3:0] end - attribute \src "libresoc.v:56287.3-56302.6" - process $proc$libresoc.v:56287$3485 + attribute \src "libresoc.v:56348.3-56363.6" + process $proc$libresoc.v:56348$3485 assign { } { } assign { } { } assign $0\BRANCH_cr_in[2:0] $1\BRANCH_cr_in[2:0] - attribute \src "libresoc.v:56288.5-56288.29" + attribute \src "libresoc.v:56349.5-56349.29" switch \initial - attribute \src "libresoc.v:56288.9-56288.17" + attribute \src "libresoc.v:56349.9-56349.17" case 1'1 case end @@ -97533,14 +97581,14 @@ module \dec$141 sync always update \BRANCH_cr_in $0\BRANCH_cr_in[2:0] end - attribute \src "libresoc.v:56303.3-56318.6" - process $proc$libresoc.v:56303$3486 + attribute \src "libresoc.v:56364.3-56379.6" + process $proc$libresoc.v:56364$3486 assign { } { } assign { } { } assign $0\BRANCH_cr_out[2:0] $1\BRANCH_cr_out[2:0] - attribute \src "libresoc.v:56304.5-56304.29" + attribute \src "libresoc.v:56365.5-56365.29" switch \initial - attribute \src "libresoc.v:56304.9-56304.17" + attribute \src "libresoc.v:56365.9-56365.17" case 1'1 case end @@ -97564,14 +97612,14 @@ module \dec$141 sync always update \BRANCH_cr_out $0\BRANCH_cr_out[2:0] end - attribute \src "libresoc.v:56319.3-56334.6" - process $proc$libresoc.v:56319$3487 + attribute \src "libresoc.v:56380.3-56395.6" + process $proc$libresoc.v:56380$3487 assign { } { } assign { } { } assign $0\BRANCH_rc_sel[1:0] $1\BRANCH_rc_sel[1:0] - attribute \src "libresoc.v:56320.5-56320.29" + attribute \src "libresoc.v:56381.5-56381.29" switch \initial - attribute \src "libresoc.v:56320.9-56320.17" + attribute \src "libresoc.v:56381.9-56381.17" case 1'1 case end @@ -97595,14 +97643,14 @@ module \dec$141 sync always update \BRANCH_rc_sel $0\BRANCH_rc_sel[1:0] end - attribute \src "libresoc.v:56335.3-56350.6" - process $proc$libresoc.v:56335$3488 + attribute \src "libresoc.v:56396.3-56411.6" + process $proc$libresoc.v:56396$3488 assign { } { } assign { } { } assign $0\BRANCH_is_32b[0:0] $1\BRANCH_is_32b[0:0] - attribute \src "libresoc.v:56336.5-56336.29" + attribute \src "libresoc.v:56397.5-56397.29" switch \initial - attribute \src "libresoc.v:56336.9-56336.17" + attribute \src "libresoc.v:56397.9-56397.17" case 1'1 case end @@ -97626,14 +97674,14 @@ module \dec$141 sync always update \BRANCH_is_32b $0\BRANCH_is_32b[0:0] end - attribute \src "libresoc.v:56351.3-56366.6" - process $proc$libresoc.v:56351$3489 + attribute \src "libresoc.v:56412.3-56427.6" + process $proc$libresoc.v:56412$3489 assign { } { } assign { } { } assign $0\BRANCH_lk[0:0] $1\BRANCH_lk[0:0] - attribute \src "libresoc.v:56352.5-56352.29" + attribute \src "libresoc.v:56413.5-56413.29" switch \initial - attribute \src "libresoc.v:56352.9-56352.17" + attribute \src "libresoc.v:56413.9-56413.17" case 1'1 case end @@ -97657,7 +97705,7 @@ module \dec$141 sync always update \BRANCH_lk $0\BRANCH_lk[0:0] end - connect \$1 $ternary$libresoc.v:56227$3481_Y + connect \$1 $ternary$libresoc.v:56288$3481_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -97995,71 +98043,71 @@ module \dec$141 connect \BRANCH_dec19_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:56707.1-58484.10" +attribute \src "libresoc.v:56768.1-58545.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec" attribute \generator "nMigen" module \dec$145 - attribute \src "libresoc.v:58036.3-58063.6" + attribute \src "libresoc.v:58097.3-58124.6" wire width 3 $0\LOGICAL_cr_in[2:0] - attribute \src "libresoc.v:58064.3-58091.6" + attribute \src "libresoc.v:58125.3-58152.6" wire width 3 $0\LOGICAL_cr_out[2:0] - attribute \src "libresoc.v:57756.3-57783.6" + attribute \src "libresoc.v:57817.3-57844.6" wire width 2 $0\LOGICAL_cry_in[1:0] - attribute \src "libresoc.v:57840.3-57867.6" + attribute \src "libresoc.v:57901.3-57928.6" wire $0\LOGICAL_cry_out[0:0] - attribute \src "libresoc.v:57924.3-57951.6" + attribute \src "libresoc.v:57985.3-58012.6" wire width 14 $0\LOGICAL_function_unit[13:0] - attribute \src "libresoc.v:57980.3-58007.6" + attribute \src "libresoc.v:58041.3-58068.6" wire width 3 $0\LOGICAL_in1_sel[2:0] - attribute \src "libresoc.v:58008.3-58035.6" + attribute \src "libresoc.v:58069.3-58096.6" wire width 4 $0\LOGICAL_in2_sel[3:0] - attribute \src "libresoc.v:57952.3-57979.6" + attribute \src "libresoc.v:58013.3-58040.6" wire width 7 $0\LOGICAL_internal_op[6:0] - attribute \src "libresoc.v:57784.3-57811.6" + attribute \src "libresoc.v:57845.3-57872.6" wire $0\LOGICAL_inv_a[0:0] - attribute \src "libresoc.v:57812.3-57839.6" + attribute \src "libresoc.v:57873.3-57900.6" wire $0\LOGICAL_inv_out[0:0] - attribute \src "libresoc.v:57868.3-57895.6" + attribute \src "libresoc.v:57929.3-57956.6" wire $0\LOGICAL_is_32b[0:0] - attribute \src "libresoc.v:58092.3-58119.6" + attribute \src "libresoc.v:58153.3-58180.6" wire width 4 $0\LOGICAL_ldst_len[3:0] - attribute \src "libresoc.v:58120.3-58147.6" + attribute \src "libresoc.v:58181.3-58208.6" wire width 2 $0\LOGICAL_rc_sel[1:0] - attribute \src "libresoc.v:57896.3-57923.6" + attribute \src "libresoc.v:57957.3-57984.6" wire $0\LOGICAL_sgn[0:0] - attribute \src "libresoc.v:56708.7-56708.20" + attribute \src "libresoc.v:56769.7-56769.20" wire $0\initial[0:0] - attribute \src "libresoc.v:58036.3-58063.6" + attribute \src "libresoc.v:58097.3-58124.6" wire width 3 $1\LOGICAL_cr_in[2:0] - attribute \src "libresoc.v:58064.3-58091.6" + attribute \src "libresoc.v:58125.3-58152.6" wire width 3 $1\LOGICAL_cr_out[2:0] - attribute \src "libresoc.v:57756.3-57783.6" + attribute \src "libresoc.v:57817.3-57844.6" wire width 2 $1\LOGICAL_cry_in[1:0] - attribute \src "libresoc.v:57840.3-57867.6" + attribute \src "libresoc.v:57901.3-57928.6" wire $1\LOGICAL_cry_out[0:0] - attribute \src "libresoc.v:57924.3-57951.6" + attribute \src "libresoc.v:57985.3-58012.6" wire width 14 $1\LOGICAL_function_unit[13:0] - attribute \src "libresoc.v:57980.3-58007.6" + attribute \src "libresoc.v:58041.3-58068.6" wire width 3 $1\LOGICAL_in1_sel[2:0] - attribute \src "libresoc.v:58008.3-58035.6" + attribute \src "libresoc.v:58069.3-58096.6" wire width 4 $1\LOGICAL_in2_sel[3:0] - attribute \src "libresoc.v:57952.3-57979.6" + attribute \src "libresoc.v:58013.3-58040.6" wire width 7 $1\LOGICAL_internal_op[6:0] - attribute \src "libresoc.v:57784.3-57811.6" + attribute \src "libresoc.v:57845.3-57872.6" wire $1\LOGICAL_inv_a[0:0] - attribute \src "libresoc.v:57812.3-57839.6" + attribute \src "libresoc.v:57873.3-57900.6" wire $1\LOGICAL_inv_out[0:0] - attribute \src "libresoc.v:57868.3-57895.6" + attribute \src "libresoc.v:57929.3-57956.6" wire $1\LOGICAL_is_32b[0:0] - attribute \src "libresoc.v:58092.3-58119.6" + attribute \src "libresoc.v:58153.3-58180.6" wire width 4 $1\LOGICAL_ldst_len[3:0] - attribute \src "libresoc.v:58120.3-58147.6" + attribute \src "libresoc.v:58181.3-58208.6" wire width 2 $1\LOGICAL_rc_sel[1:0] - attribute \src "libresoc.v:57896.3-57923.6" + attribute \src "libresoc.v:57957.3-57984.6" wire $1\LOGICAL_sgn[0:0] - attribute \src "libresoc.v:57738.17-57738.211" - wire width 32 $ternary$libresoc.v:57738$3491_Y + attribute \src "libresoc.v:57799.17-57799.211" + wire width 32 $ternary$libresoc.v:57799$3491_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" @@ -99070,7 +99118,7 @@ module \dec$145 wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:56708.7-56708.15" + attribute \src "libresoc.v:56769.7-56769.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in @@ -99079,15 +99127,15 @@ module \dec$145 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 27 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" - cell $mux $ternary$libresoc.v:57738$3491 + cell $mux $ternary$libresoc.v:57799$3491 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:57738$3491_Y + connect \Y $ternary$libresoc.v:57799$3491_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:57739.17-57755.4" + attribute \src "libresoc.v:57800.17-57816.4" cell \LOGICAL_dec31 \LOGICAL_dec31 connect \LOGICAL_dec31_cr_in \LOGICAL_dec31_LOGICAL_dec31_cr_in connect \LOGICAL_dec31_cr_out \LOGICAL_dec31_LOGICAL_dec31_cr_out @@ -99105,22 +99153,22 @@ module \dec$145 connect \LOGICAL_dec31_sgn \LOGICAL_dec31_LOGICAL_dec31_sgn connect \opcode_in \LOGICAL_dec31_opcode_in end - attribute \src "libresoc.v:56708.7-56708.20" - process $proc$libresoc.v:56708$3506 + attribute \src "libresoc.v:56769.7-56769.20" + process $proc$libresoc.v:56769$3506 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:57756.3-57783.6" - process $proc$libresoc.v:57756$3492 + attribute \src "libresoc.v:57817.3-57844.6" + process $proc$libresoc.v:57817$3492 assign { } { } assign { } { } assign $0\LOGICAL_cry_in[1:0] $1\LOGICAL_cry_in[1:0] - attribute \src "libresoc.v:57757.5-57757.29" + attribute \src "libresoc.v:57818.5-57818.29" switch \initial - attribute \src "libresoc.v:57757.9-57757.17" + attribute \src "libresoc.v:57818.9-57818.17" case 1'1 case end @@ -99160,14 +99208,14 @@ module \dec$145 sync always update \LOGICAL_cry_in $0\LOGICAL_cry_in[1:0] end - attribute \src "libresoc.v:57784.3-57811.6" - process $proc$libresoc.v:57784$3493 + attribute \src "libresoc.v:57845.3-57872.6" + process $proc$libresoc.v:57845$3493 assign { } { } assign { } { } assign $0\LOGICAL_inv_a[0:0] $1\LOGICAL_inv_a[0:0] - attribute \src "libresoc.v:57785.5-57785.29" + attribute \src "libresoc.v:57846.5-57846.29" switch \initial - attribute \src "libresoc.v:57785.9-57785.17" + attribute \src "libresoc.v:57846.9-57846.17" case 1'1 case end @@ -99207,14 +99255,14 @@ module \dec$145 sync always update \LOGICAL_inv_a $0\LOGICAL_inv_a[0:0] end - attribute \src "libresoc.v:57812.3-57839.6" - process $proc$libresoc.v:57812$3494 + attribute \src "libresoc.v:57873.3-57900.6" + process $proc$libresoc.v:57873$3494 assign { } { } assign { } { } assign $0\LOGICAL_inv_out[0:0] $1\LOGICAL_inv_out[0:0] - attribute \src "libresoc.v:57813.5-57813.29" + attribute \src "libresoc.v:57874.5-57874.29" switch \initial - attribute \src "libresoc.v:57813.9-57813.17" + attribute \src "libresoc.v:57874.9-57874.17" case 1'1 case end @@ -99254,14 +99302,14 @@ module \dec$145 sync always update \LOGICAL_inv_out $0\LOGICAL_inv_out[0:0] end - attribute \src "libresoc.v:57840.3-57867.6" - process $proc$libresoc.v:57840$3495 + attribute \src "libresoc.v:57901.3-57928.6" + process $proc$libresoc.v:57901$3495 assign { } { } assign { } { } assign $0\LOGICAL_cry_out[0:0] $1\LOGICAL_cry_out[0:0] - attribute \src "libresoc.v:57841.5-57841.29" + attribute \src "libresoc.v:57902.5-57902.29" switch \initial - attribute \src "libresoc.v:57841.9-57841.17" + attribute \src "libresoc.v:57902.9-57902.17" case 1'1 case end @@ -99301,14 +99349,14 @@ module \dec$145 sync always update \LOGICAL_cry_out $0\LOGICAL_cry_out[0:0] end - attribute \src "libresoc.v:57868.3-57895.6" - process $proc$libresoc.v:57868$3496 + attribute \src "libresoc.v:57929.3-57956.6" + process $proc$libresoc.v:57929$3496 assign { } { } assign { } { } assign $0\LOGICAL_is_32b[0:0] $1\LOGICAL_is_32b[0:0] - attribute \src "libresoc.v:57869.5-57869.29" + attribute \src "libresoc.v:57930.5-57930.29" switch \initial - attribute \src "libresoc.v:57869.9-57869.17" + attribute \src "libresoc.v:57930.9-57930.17" case 1'1 case end @@ -99348,14 +99396,14 @@ module \dec$145 sync always update \LOGICAL_is_32b $0\LOGICAL_is_32b[0:0] end - attribute \src "libresoc.v:57896.3-57923.6" - process $proc$libresoc.v:57896$3497 + attribute \src "libresoc.v:57957.3-57984.6" + process $proc$libresoc.v:57957$3497 assign { } { } assign { } { } assign $0\LOGICAL_sgn[0:0] $1\LOGICAL_sgn[0:0] - attribute \src "libresoc.v:57897.5-57897.29" + attribute \src "libresoc.v:57958.5-57958.29" switch \initial - attribute \src "libresoc.v:57897.9-57897.17" + attribute \src "libresoc.v:57958.9-57958.17" case 1'1 case end @@ -99395,14 +99443,14 @@ module \dec$145 sync always update \LOGICAL_sgn $0\LOGICAL_sgn[0:0] end - attribute \src "libresoc.v:57924.3-57951.6" - process $proc$libresoc.v:57924$3498 + attribute \src "libresoc.v:57985.3-58012.6" + process $proc$libresoc.v:57985$3498 assign { } { } assign { } { } assign $0\LOGICAL_function_unit[13:0] $1\LOGICAL_function_unit[13:0] - attribute \src "libresoc.v:57925.5-57925.29" + attribute \src "libresoc.v:57986.5-57986.29" switch \initial - attribute \src "libresoc.v:57925.9-57925.17" + attribute \src "libresoc.v:57986.9-57986.17" case 1'1 case end @@ -99442,14 +99490,14 @@ module \dec$145 sync always update \LOGICAL_function_unit $0\LOGICAL_function_unit[13:0] end - attribute \src "libresoc.v:57952.3-57979.6" - process $proc$libresoc.v:57952$3499 + attribute \src "libresoc.v:58013.3-58040.6" + process $proc$libresoc.v:58013$3499 assign { } { } assign { } { } assign $0\LOGICAL_internal_op[6:0] $1\LOGICAL_internal_op[6:0] - attribute \src "libresoc.v:57953.5-57953.29" + attribute \src "libresoc.v:58014.5-58014.29" switch \initial - attribute \src "libresoc.v:57953.9-57953.17" + attribute \src "libresoc.v:58014.9-58014.17" case 1'1 case end @@ -99489,14 +99537,14 @@ module \dec$145 sync always update \LOGICAL_internal_op $0\LOGICAL_internal_op[6:0] end - attribute \src "libresoc.v:57980.3-58007.6" - process $proc$libresoc.v:57980$3500 + attribute \src "libresoc.v:58041.3-58068.6" + process $proc$libresoc.v:58041$3500 assign { } { } assign { } { } assign $0\LOGICAL_in1_sel[2:0] $1\LOGICAL_in1_sel[2:0] - attribute \src "libresoc.v:57981.5-57981.29" + attribute \src "libresoc.v:58042.5-58042.29" switch \initial - attribute \src "libresoc.v:57981.9-57981.17" + attribute \src "libresoc.v:58042.9-58042.17" case 1'1 case end @@ -99536,14 +99584,14 @@ module \dec$145 sync always update \LOGICAL_in1_sel $0\LOGICAL_in1_sel[2:0] end - attribute \src "libresoc.v:58008.3-58035.6" - process $proc$libresoc.v:58008$3501 + attribute \src "libresoc.v:58069.3-58096.6" + process $proc$libresoc.v:58069$3501 assign { } { } assign { } { } assign $0\LOGICAL_in2_sel[3:0] $1\LOGICAL_in2_sel[3:0] - attribute \src "libresoc.v:58009.5-58009.29" + attribute \src "libresoc.v:58070.5-58070.29" switch \initial - attribute \src "libresoc.v:58009.9-58009.17" + attribute \src "libresoc.v:58070.9-58070.17" case 1'1 case end @@ -99583,14 +99631,14 @@ module \dec$145 sync always update \LOGICAL_in2_sel $0\LOGICAL_in2_sel[3:0] end - attribute \src "libresoc.v:58036.3-58063.6" - process $proc$libresoc.v:58036$3502 + attribute \src "libresoc.v:58097.3-58124.6" + process $proc$libresoc.v:58097$3502 assign { } { } assign { } { } assign $0\LOGICAL_cr_in[2:0] $1\LOGICAL_cr_in[2:0] - attribute \src "libresoc.v:58037.5-58037.29" + attribute \src "libresoc.v:58098.5-58098.29" switch \initial - attribute \src "libresoc.v:58037.9-58037.17" + attribute \src "libresoc.v:58098.9-58098.17" case 1'1 case end @@ -99630,14 +99678,14 @@ module \dec$145 sync always update \LOGICAL_cr_in $0\LOGICAL_cr_in[2:0] end - attribute \src "libresoc.v:58064.3-58091.6" - process $proc$libresoc.v:58064$3503 + attribute \src "libresoc.v:58125.3-58152.6" + process $proc$libresoc.v:58125$3503 assign { } { } assign { } { } assign $0\LOGICAL_cr_out[2:0] $1\LOGICAL_cr_out[2:0] - attribute \src "libresoc.v:58065.5-58065.29" + attribute \src "libresoc.v:58126.5-58126.29" switch \initial - attribute \src "libresoc.v:58065.9-58065.17" + attribute \src "libresoc.v:58126.9-58126.17" case 1'1 case end @@ -99677,14 +99725,14 @@ module \dec$145 sync always update \LOGICAL_cr_out $0\LOGICAL_cr_out[2:0] end - attribute \src "libresoc.v:58092.3-58119.6" - process $proc$libresoc.v:58092$3504 + attribute \src "libresoc.v:58153.3-58180.6" + process $proc$libresoc.v:58153$3504 assign { } { } assign { } { } assign $0\LOGICAL_ldst_len[3:0] $1\LOGICAL_ldst_len[3:0] - attribute \src "libresoc.v:58093.5-58093.29" + attribute \src "libresoc.v:58154.5-58154.29" switch \initial - attribute \src "libresoc.v:58093.9-58093.17" + attribute \src "libresoc.v:58154.9-58154.17" case 1'1 case end @@ -99724,14 +99772,14 @@ module \dec$145 sync always update \LOGICAL_ldst_len $0\LOGICAL_ldst_len[3:0] end - attribute \src "libresoc.v:58120.3-58147.6" - process $proc$libresoc.v:58120$3505 + attribute \src "libresoc.v:58181.3-58208.6" + process $proc$libresoc.v:58181$3505 assign { } { } assign { } { } assign $0\LOGICAL_rc_sel[1:0] $1\LOGICAL_rc_sel[1:0] - attribute \src "libresoc.v:58121.5-58121.29" + attribute \src "libresoc.v:58182.5-58182.29" switch \initial - attribute \src "libresoc.v:58121.9-58121.17" + attribute \src "libresoc.v:58182.9-58182.17" case 1'1 case end @@ -99771,7 +99819,7 @@ module \dec$145 sync always update \LOGICAL_rc_sel $0\LOGICAL_rc_sel[1:0] end - connect \$1 $ternary$libresoc.v:57738$3491_Y + connect \$1 $ternary$libresoc.v:57799$3491_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -100109,39 +100157,39 @@ module \dec$145 connect \LOGICAL_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:58488.1-59823.10" +attribute \src "libresoc.v:58549.1-59884.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec" attribute \generator "nMigen" module \dec$150 - attribute \src "libresoc.v:59447.3-59456.6" + attribute \src "libresoc.v:59508.3-59517.6" wire width 3 $0\SPR_cr_in[2:0] - attribute \src "libresoc.v:59457.3-59466.6" + attribute \src "libresoc.v:59518.3-59527.6" wire width 3 $0\SPR_cr_out[2:0] - attribute \src "libresoc.v:59427.3-59436.6" + attribute \src "libresoc.v:59488.3-59497.6" wire width 14 $0\SPR_function_unit[13:0] - attribute \src "libresoc.v:59437.3-59446.6" + attribute \src "libresoc.v:59498.3-59507.6" wire width 7 $0\SPR_internal_op[6:0] - attribute \src "libresoc.v:59477.3-59486.6" + attribute \src "libresoc.v:59538.3-59547.6" wire $0\SPR_is_32b[0:0] - attribute \src "libresoc.v:59467.3-59476.6" + attribute \src "libresoc.v:59528.3-59537.6" wire width 2 $0\SPR_rc_sel[1:0] - attribute \src "libresoc.v:58489.7-58489.20" + attribute \src "libresoc.v:58550.7-58550.20" wire $0\initial[0:0] - attribute \src "libresoc.v:59447.3-59456.6" + attribute \src "libresoc.v:59508.3-59517.6" wire width 3 $1\SPR_cr_in[2:0] - attribute \src "libresoc.v:59457.3-59466.6" + attribute \src "libresoc.v:59518.3-59527.6" wire width 3 $1\SPR_cr_out[2:0] - attribute \src "libresoc.v:59427.3-59436.6" + attribute \src "libresoc.v:59488.3-59497.6" wire width 14 $1\SPR_function_unit[13:0] - attribute \src "libresoc.v:59437.3-59446.6" + attribute \src "libresoc.v:59498.3-59507.6" wire width 7 $1\SPR_internal_op[6:0] - attribute \src "libresoc.v:59477.3-59486.6" + attribute \src "libresoc.v:59538.3-59547.6" wire $1\SPR_is_32b[0:0] - attribute \src "libresoc.v:59467.3-59476.6" + attribute \src "libresoc.v:59528.3-59537.6" wire width 2 $1\SPR_rc_sel[1:0] - attribute \src "libresoc.v:59417.17-59417.211" - wire width 32 $ternary$libresoc.v:59417$3507_Y + attribute \src "libresoc.v:59478.17-59478.211" + wire width 32 $ternary$libresoc.v:59478$3507_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" @@ -101058,7 +101106,7 @@ module \dec$150 wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:58489.7-58489.15" + attribute \src "libresoc.v:58550.7-58550.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in @@ -101067,15 +101115,15 @@ module \dec$150 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 11 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" - cell $mux $ternary$libresoc.v:59417$3507 + cell $mux $ternary$libresoc.v:59478$3507 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:59417$3507_Y + connect \Y $ternary$libresoc.v:59478$3507_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:59418.13-59426.4" + attribute \src "libresoc.v:59479.13-59487.4" cell \SPR_dec31 \SPR_dec31 connect \SPR_dec31_cr_in \SPR_dec31_SPR_dec31_cr_in connect \SPR_dec31_cr_out \SPR_dec31_SPR_dec31_cr_out @@ -101085,22 +101133,22 @@ module \dec$150 connect \SPR_dec31_rc_sel \SPR_dec31_SPR_dec31_rc_sel connect \opcode_in \SPR_dec31_opcode_in end - attribute \src "libresoc.v:58489.7-58489.20" - process $proc$libresoc.v:58489$3514 + attribute \src "libresoc.v:58550.7-58550.20" + process $proc$libresoc.v:58550$3514 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:59427.3-59436.6" - process $proc$libresoc.v:59427$3508 + attribute \src "libresoc.v:59488.3-59497.6" + process $proc$libresoc.v:59488$3508 assign { } { } assign { } { } assign $0\SPR_function_unit[13:0] $1\SPR_function_unit[13:0] - attribute \src "libresoc.v:59428.5-59428.29" + attribute \src "libresoc.v:59489.5-59489.29" switch \initial - attribute \src "libresoc.v:59428.9-59428.17" + attribute \src "libresoc.v:59489.9-59489.17" case 1'1 case end @@ -101116,14 +101164,14 @@ module \dec$150 sync always update \SPR_function_unit $0\SPR_function_unit[13:0] end - attribute \src "libresoc.v:59437.3-59446.6" - process $proc$libresoc.v:59437$3509 + attribute \src "libresoc.v:59498.3-59507.6" + process $proc$libresoc.v:59498$3509 assign { } { } assign { } { } assign $0\SPR_internal_op[6:0] $1\SPR_internal_op[6:0] - attribute \src "libresoc.v:59438.5-59438.29" + attribute \src "libresoc.v:59499.5-59499.29" switch \initial - attribute \src "libresoc.v:59438.9-59438.17" + attribute \src "libresoc.v:59499.9-59499.17" case 1'1 case end @@ -101139,14 +101187,14 @@ module \dec$150 sync always update \SPR_internal_op $0\SPR_internal_op[6:0] end - attribute \src "libresoc.v:59447.3-59456.6" - process $proc$libresoc.v:59447$3510 + attribute \src "libresoc.v:59508.3-59517.6" + process $proc$libresoc.v:59508$3510 assign { } { } assign { } { } assign $0\SPR_cr_in[2:0] $1\SPR_cr_in[2:0] - attribute \src "libresoc.v:59448.5-59448.29" + attribute \src "libresoc.v:59509.5-59509.29" switch \initial - attribute \src "libresoc.v:59448.9-59448.17" + attribute \src "libresoc.v:59509.9-59509.17" case 1'1 case end @@ -101162,14 +101210,14 @@ module \dec$150 sync always update \SPR_cr_in $0\SPR_cr_in[2:0] end - attribute \src "libresoc.v:59457.3-59466.6" - process $proc$libresoc.v:59457$3511 + attribute \src "libresoc.v:59518.3-59527.6" + process $proc$libresoc.v:59518$3511 assign { } { } assign { } { } assign $0\SPR_cr_out[2:0] $1\SPR_cr_out[2:0] - attribute \src "libresoc.v:59458.5-59458.29" + attribute \src "libresoc.v:59519.5-59519.29" switch \initial - attribute \src "libresoc.v:59458.9-59458.17" + attribute \src "libresoc.v:59519.9-59519.17" case 1'1 case end @@ -101185,14 +101233,14 @@ module \dec$150 sync always update \SPR_cr_out $0\SPR_cr_out[2:0] end - attribute \src "libresoc.v:59467.3-59476.6" - process $proc$libresoc.v:59467$3512 + attribute \src "libresoc.v:59528.3-59537.6" + process $proc$libresoc.v:59528$3512 assign { } { } assign { } { } assign $0\SPR_rc_sel[1:0] $1\SPR_rc_sel[1:0] - attribute \src "libresoc.v:59468.5-59468.29" + attribute \src "libresoc.v:59529.5-59529.29" switch \initial - attribute \src "libresoc.v:59468.9-59468.17" + attribute \src "libresoc.v:59529.9-59529.17" case 1'1 case end @@ -101208,14 +101256,14 @@ module \dec$150 sync always update \SPR_rc_sel $0\SPR_rc_sel[1:0] end - attribute \src "libresoc.v:59477.3-59486.6" - process $proc$libresoc.v:59477$3513 + attribute \src "libresoc.v:59538.3-59547.6" + process $proc$libresoc.v:59538$3513 assign { } { } assign { } { } assign $0\SPR_is_32b[0:0] $1\SPR_is_32b[0:0] - attribute \src "libresoc.v:59478.5-59478.29" + attribute \src "libresoc.v:59539.5-59539.29" switch \initial - attribute \src "libresoc.v:59478.9-59478.17" + attribute \src "libresoc.v:59539.9-59539.17" case 1'1 case end @@ -101231,7 +101279,7 @@ module \dec$150 sync always update \SPR_is_32b $0\SPR_is_32b[0:0] end - connect \$1 $ternary$libresoc.v:59417$3507_Y + connect \$1 $ternary$libresoc.v:59478$3507_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -101569,71 +101617,71 @@ module \dec$150 connect \SPR_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:59827.1-61352.10" +attribute \src "libresoc.v:59888.1-61413.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec" attribute \generator "nMigen" module \dec$153 - attribute \src "libresoc.v:60976.3-60985.6" + attribute \src "libresoc.v:61037.3-61046.6" wire width 3 $0\DIV_cr_in[2:0] - attribute \src "libresoc.v:60986.3-60995.6" + attribute \src "libresoc.v:61047.3-61056.6" wire width 3 $0\DIV_cr_out[2:0] - attribute \src "libresoc.v:60876.3-60885.6" + attribute \src "libresoc.v:60937.3-60946.6" wire width 2 $0\DIV_cry_in[1:0] - attribute \src "libresoc.v:60906.3-60915.6" + attribute \src "libresoc.v:60967.3-60976.6" wire $0\DIV_cry_out[0:0] - attribute \src "libresoc.v:60936.3-60945.6" + attribute \src "libresoc.v:60997.3-61006.6" wire width 14 $0\DIV_function_unit[13:0] - attribute \src "libresoc.v:60956.3-60965.6" + attribute \src "libresoc.v:61017.3-61026.6" wire width 3 $0\DIV_in1_sel[2:0] - attribute \src "libresoc.v:60966.3-60975.6" + attribute \src "libresoc.v:61027.3-61036.6" wire width 4 $0\DIV_in2_sel[3:0] - attribute \src "libresoc.v:60946.3-60955.6" + attribute \src "libresoc.v:61007.3-61016.6" wire width 7 $0\DIV_internal_op[6:0] - attribute \src "libresoc.v:60886.3-60895.6" + attribute \src "libresoc.v:60947.3-60956.6" wire $0\DIV_inv_a[0:0] - attribute \src "libresoc.v:60896.3-60905.6" + attribute \src "libresoc.v:60957.3-60966.6" wire $0\DIV_inv_out[0:0] - attribute \src "libresoc.v:60916.3-60925.6" + attribute \src "libresoc.v:60977.3-60986.6" wire $0\DIV_is_32b[0:0] - attribute \src "libresoc.v:60996.3-61005.6" + attribute \src "libresoc.v:61057.3-61066.6" wire width 4 $0\DIV_ldst_len[3:0] - attribute \src "libresoc.v:61006.3-61015.6" + attribute \src "libresoc.v:61067.3-61076.6" wire width 2 $0\DIV_rc_sel[1:0] - attribute \src "libresoc.v:60926.3-60935.6" + attribute \src "libresoc.v:60987.3-60996.6" wire $0\DIV_sgn[0:0] - attribute \src "libresoc.v:59828.7-59828.20" + attribute \src "libresoc.v:59889.7-59889.20" wire $0\initial[0:0] - attribute \src "libresoc.v:60976.3-60985.6" + attribute \src "libresoc.v:61037.3-61046.6" wire width 3 $1\DIV_cr_in[2:0] - attribute \src "libresoc.v:60986.3-60995.6" + attribute \src "libresoc.v:61047.3-61056.6" wire width 3 $1\DIV_cr_out[2:0] - attribute \src "libresoc.v:60876.3-60885.6" + attribute \src "libresoc.v:60937.3-60946.6" wire width 2 $1\DIV_cry_in[1:0] - attribute \src "libresoc.v:60906.3-60915.6" + attribute \src "libresoc.v:60967.3-60976.6" wire $1\DIV_cry_out[0:0] - attribute \src "libresoc.v:60936.3-60945.6" + attribute \src "libresoc.v:60997.3-61006.6" wire width 14 $1\DIV_function_unit[13:0] - attribute \src "libresoc.v:60956.3-60965.6" + attribute \src "libresoc.v:61017.3-61026.6" wire width 3 $1\DIV_in1_sel[2:0] - attribute \src "libresoc.v:60966.3-60975.6" + attribute \src "libresoc.v:61027.3-61036.6" wire width 4 $1\DIV_in2_sel[3:0] - attribute \src "libresoc.v:60946.3-60955.6" + attribute \src "libresoc.v:61007.3-61016.6" wire width 7 $1\DIV_internal_op[6:0] - attribute \src "libresoc.v:60886.3-60895.6" + attribute \src "libresoc.v:60947.3-60956.6" wire $1\DIV_inv_a[0:0] - attribute \src "libresoc.v:60896.3-60905.6" + attribute \src "libresoc.v:60957.3-60966.6" wire $1\DIV_inv_out[0:0] - attribute \src "libresoc.v:60916.3-60925.6" + attribute \src "libresoc.v:60977.3-60986.6" wire $1\DIV_is_32b[0:0] - attribute \src "libresoc.v:60996.3-61005.6" + attribute \src "libresoc.v:61057.3-61066.6" wire width 4 $1\DIV_ldst_len[3:0] - attribute \src "libresoc.v:61006.3-61015.6" + attribute \src "libresoc.v:61067.3-61076.6" wire width 2 $1\DIV_rc_sel[1:0] - attribute \src "libresoc.v:60926.3-60935.6" + attribute \src "libresoc.v:60987.3-60996.6" wire $1\DIV_sgn[0:0] - attribute \src "libresoc.v:60858.17-60858.211" - wire width 32 $ternary$libresoc.v:60858$3515_Y + attribute \src "libresoc.v:60919.17-60919.211" + wire width 32 $ternary$libresoc.v:60919$3515_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" @@ -102644,7 +102692,7 @@ module \dec$153 wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:59828.7-59828.15" + attribute \src "libresoc.v:59889.7-59889.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in @@ -102653,15 +102701,15 @@ module \dec$153 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 27 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" - cell $mux $ternary$libresoc.v:60858$3515 + cell $mux $ternary$libresoc.v:60919$3515 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:60858$3515_Y + connect \Y $ternary$libresoc.v:60919$3515_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:60859.13-60875.4" + attribute \src "libresoc.v:60920.13-60936.4" cell \DIV_dec31 \DIV_dec31 connect \DIV_dec31_cr_in \DIV_dec31_DIV_dec31_cr_in connect \DIV_dec31_cr_out \DIV_dec31_DIV_dec31_cr_out @@ -102679,22 +102727,22 @@ module \dec$153 connect \DIV_dec31_sgn \DIV_dec31_DIV_dec31_sgn connect \opcode_in \DIV_dec31_opcode_in end - attribute \src "libresoc.v:59828.7-59828.20" - process $proc$libresoc.v:59828$3530 + attribute \src "libresoc.v:59889.7-59889.20" + process $proc$libresoc.v:59889$3530 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:60876.3-60885.6" - process $proc$libresoc.v:60876$3516 + attribute \src "libresoc.v:60937.3-60946.6" + process $proc$libresoc.v:60937$3516 assign { } { } assign { } { } assign $0\DIV_cry_in[1:0] $1\DIV_cry_in[1:0] - attribute \src "libresoc.v:60877.5-60877.29" + attribute \src "libresoc.v:60938.5-60938.29" switch \initial - attribute \src "libresoc.v:60877.9-60877.17" + attribute \src "libresoc.v:60938.9-60938.17" case 1'1 case end @@ -102710,14 +102758,14 @@ module \dec$153 sync always update \DIV_cry_in $0\DIV_cry_in[1:0] end - attribute \src "libresoc.v:60886.3-60895.6" - process $proc$libresoc.v:60886$3517 + attribute \src "libresoc.v:60947.3-60956.6" + process $proc$libresoc.v:60947$3517 assign { } { } assign { } { } assign $0\DIV_inv_a[0:0] $1\DIV_inv_a[0:0] - attribute \src "libresoc.v:60887.5-60887.29" + attribute \src "libresoc.v:60948.5-60948.29" switch \initial - attribute \src "libresoc.v:60887.9-60887.17" + attribute \src "libresoc.v:60948.9-60948.17" case 1'1 case end @@ -102733,14 +102781,14 @@ module \dec$153 sync always update \DIV_inv_a $0\DIV_inv_a[0:0] end - attribute \src "libresoc.v:60896.3-60905.6" - process $proc$libresoc.v:60896$3518 + attribute \src "libresoc.v:60957.3-60966.6" + process $proc$libresoc.v:60957$3518 assign { } { } assign { } { } assign $0\DIV_inv_out[0:0] $1\DIV_inv_out[0:0] - attribute \src "libresoc.v:60897.5-60897.29" + attribute \src "libresoc.v:60958.5-60958.29" switch \initial - attribute \src "libresoc.v:60897.9-60897.17" + attribute \src "libresoc.v:60958.9-60958.17" case 1'1 case end @@ -102756,14 +102804,14 @@ module \dec$153 sync always update \DIV_inv_out $0\DIV_inv_out[0:0] end - attribute \src "libresoc.v:60906.3-60915.6" - process $proc$libresoc.v:60906$3519 + attribute \src "libresoc.v:60967.3-60976.6" + process $proc$libresoc.v:60967$3519 assign { } { } assign { } { } assign $0\DIV_cry_out[0:0] $1\DIV_cry_out[0:0] - attribute \src "libresoc.v:60907.5-60907.29" + attribute \src "libresoc.v:60968.5-60968.29" switch \initial - attribute \src "libresoc.v:60907.9-60907.17" + attribute \src "libresoc.v:60968.9-60968.17" case 1'1 case end @@ -102779,14 +102827,14 @@ module \dec$153 sync always update \DIV_cry_out $0\DIV_cry_out[0:0] end - attribute \src "libresoc.v:60916.3-60925.6" - process $proc$libresoc.v:60916$3520 + attribute \src "libresoc.v:60977.3-60986.6" + process $proc$libresoc.v:60977$3520 assign { } { } assign { } { } assign $0\DIV_is_32b[0:0] $1\DIV_is_32b[0:0] - attribute \src "libresoc.v:60917.5-60917.29" + attribute \src "libresoc.v:60978.5-60978.29" switch \initial - attribute \src "libresoc.v:60917.9-60917.17" + attribute \src "libresoc.v:60978.9-60978.17" case 1'1 case end @@ -102802,14 +102850,14 @@ module \dec$153 sync always update \DIV_is_32b $0\DIV_is_32b[0:0] end - attribute \src "libresoc.v:60926.3-60935.6" - process $proc$libresoc.v:60926$3521 + attribute \src "libresoc.v:60987.3-60996.6" + process $proc$libresoc.v:60987$3521 assign { } { } assign { } { } assign $0\DIV_sgn[0:0] $1\DIV_sgn[0:0] - attribute \src "libresoc.v:60927.5-60927.29" + attribute \src "libresoc.v:60988.5-60988.29" switch \initial - attribute \src "libresoc.v:60927.9-60927.17" + attribute \src "libresoc.v:60988.9-60988.17" case 1'1 case end @@ -102825,14 +102873,14 @@ module \dec$153 sync always update \DIV_sgn $0\DIV_sgn[0:0] end - attribute \src "libresoc.v:60936.3-60945.6" - process $proc$libresoc.v:60936$3522 + attribute \src "libresoc.v:60997.3-61006.6" + process $proc$libresoc.v:60997$3522 assign { } { } assign { } { } assign $0\DIV_function_unit[13:0] $1\DIV_function_unit[13:0] - attribute \src "libresoc.v:60937.5-60937.29" + attribute \src "libresoc.v:60998.5-60998.29" switch \initial - attribute \src "libresoc.v:60937.9-60937.17" + attribute \src "libresoc.v:60998.9-60998.17" case 1'1 case end @@ -102848,14 +102896,14 @@ module \dec$153 sync always update \DIV_function_unit $0\DIV_function_unit[13:0] end - attribute \src "libresoc.v:60946.3-60955.6" - process $proc$libresoc.v:60946$3523 + attribute \src "libresoc.v:61007.3-61016.6" + process $proc$libresoc.v:61007$3523 assign { } { } assign { } { } assign $0\DIV_internal_op[6:0] $1\DIV_internal_op[6:0] - attribute \src "libresoc.v:60947.5-60947.29" + attribute \src "libresoc.v:61008.5-61008.29" switch \initial - attribute \src "libresoc.v:60947.9-60947.17" + attribute \src "libresoc.v:61008.9-61008.17" case 1'1 case end @@ -102871,14 +102919,14 @@ module \dec$153 sync always update \DIV_internal_op $0\DIV_internal_op[6:0] end - attribute \src "libresoc.v:60956.3-60965.6" - process $proc$libresoc.v:60956$3524 + attribute \src "libresoc.v:61017.3-61026.6" + process $proc$libresoc.v:61017$3524 assign { } { } assign { } { } assign $0\DIV_in1_sel[2:0] $1\DIV_in1_sel[2:0] - attribute \src "libresoc.v:60957.5-60957.29" + attribute \src "libresoc.v:61018.5-61018.29" switch \initial - attribute \src "libresoc.v:60957.9-60957.17" + attribute \src "libresoc.v:61018.9-61018.17" case 1'1 case end @@ -102894,14 +102942,14 @@ module \dec$153 sync always update \DIV_in1_sel $0\DIV_in1_sel[2:0] end - attribute \src "libresoc.v:60966.3-60975.6" - process $proc$libresoc.v:60966$3525 + attribute \src "libresoc.v:61027.3-61036.6" + process $proc$libresoc.v:61027$3525 assign { } { } assign { } { } assign $0\DIV_in2_sel[3:0] $1\DIV_in2_sel[3:0] - attribute \src "libresoc.v:60967.5-60967.29" + attribute \src "libresoc.v:61028.5-61028.29" switch \initial - attribute \src "libresoc.v:60967.9-60967.17" + attribute \src "libresoc.v:61028.9-61028.17" case 1'1 case end @@ -102917,14 +102965,14 @@ module \dec$153 sync always update \DIV_in2_sel $0\DIV_in2_sel[3:0] end - attribute \src "libresoc.v:60976.3-60985.6" - process $proc$libresoc.v:60976$3526 + attribute \src "libresoc.v:61037.3-61046.6" + process $proc$libresoc.v:61037$3526 assign { } { } assign { } { } assign $0\DIV_cr_in[2:0] $1\DIV_cr_in[2:0] - attribute \src "libresoc.v:60977.5-60977.29" + attribute \src "libresoc.v:61038.5-61038.29" switch \initial - attribute \src "libresoc.v:60977.9-60977.17" + attribute \src "libresoc.v:61038.9-61038.17" case 1'1 case end @@ -102940,14 +102988,14 @@ module \dec$153 sync always update \DIV_cr_in $0\DIV_cr_in[2:0] end - attribute \src "libresoc.v:60986.3-60995.6" - process $proc$libresoc.v:60986$3527 + attribute \src "libresoc.v:61047.3-61056.6" + process $proc$libresoc.v:61047$3527 assign { } { } assign { } { } assign $0\DIV_cr_out[2:0] $1\DIV_cr_out[2:0] - attribute \src "libresoc.v:60987.5-60987.29" + attribute \src "libresoc.v:61048.5-61048.29" switch \initial - attribute \src "libresoc.v:60987.9-60987.17" + attribute \src "libresoc.v:61048.9-61048.17" case 1'1 case end @@ -102963,14 +103011,14 @@ module \dec$153 sync always update \DIV_cr_out $0\DIV_cr_out[2:0] end - attribute \src "libresoc.v:60996.3-61005.6" - process $proc$libresoc.v:60996$3528 + attribute \src "libresoc.v:61057.3-61066.6" + process $proc$libresoc.v:61057$3528 assign { } { } assign { } { } assign $0\DIV_ldst_len[3:0] $1\DIV_ldst_len[3:0] - attribute \src "libresoc.v:60997.5-60997.29" + attribute \src "libresoc.v:61058.5-61058.29" switch \initial - attribute \src "libresoc.v:60997.9-60997.17" + attribute \src "libresoc.v:61058.9-61058.17" case 1'1 case end @@ -102986,14 +103034,14 @@ module \dec$153 sync always update \DIV_ldst_len $0\DIV_ldst_len[3:0] end - attribute \src "libresoc.v:61006.3-61015.6" - process $proc$libresoc.v:61006$3529 + attribute \src "libresoc.v:61067.3-61076.6" + process $proc$libresoc.v:61067$3529 assign { } { } assign { } { } assign $0\DIV_rc_sel[1:0] $1\DIV_rc_sel[1:0] - attribute \src "libresoc.v:61007.5-61007.29" + attribute \src "libresoc.v:61068.5-61068.29" switch \initial - attribute \src "libresoc.v:61007.9-61007.17" + attribute \src "libresoc.v:61068.9-61068.17" case 1'1 case end @@ -103009,7 +103057,7 @@ module \dec$153 sync always update \DIV_rc_sel $0\DIV_rc_sel[1:0] end - connect \$1 $ternary$libresoc.v:60858$3515_Y + connect \$1 $ternary$libresoc.v:60919$3515_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -103347,47 +103395,47 @@ module \dec$153 connect \DIV_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:61356.1-62777.10" +attribute \src "libresoc.v:61417.1-62838.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec" attribute \generator "nMigen" module \dec$158 - attribute \src "libresoc.v:62376.3-62388.6" + attribute \src "libresoc.v:62437.3-62449.6" wire width 3 $0\MUL_cr_in[2:0] - attribute \src "libresoc.v:62389.3-62401.6" + attribute \src "libresoc.v:62450.3-62462.6" wire width 3 $0\MUL_cr_out[2:0] - attribute \src "libresoc.v:62337.3-62349.6" + attribute \src "libresoc.v:62398.3-62410.6" wire width 14 $0\MUL_function_unit[13:0] - attribute \src "libresoc.v:62363.3-62375.6" + attribute \src "libresoc.v:62424.3-62436.6" wire width 4 $0\MUL_in2_sel[3:0] - attribute \src "libresoc.v:62350.3-62362.6" + attribute \src "libresoc.v:62411.3-62423.6" wire width 7 $0\MUL_internal_op[6:0] - attribute \src "libresoc.v:62415.3-62427.6" + attribute \src "libresoc.v:62476.3-62488.6" wire $0\MUL_is_32b[0:0] - attribute \src "libresoc.v:62402.3-62414.6" + attribute \src "libresoc.v:62463.3-62475.6" wire width 2 $0\MUL_rc_sel[1:0] - attribute \src "libresoc.v:62428.3-62440.6" + attribute \src "libresoc.v:62489.3-62501.6" wire $0\MUL_sgn[0:0] - attribute \src "libresoc.v:61357.7-61357.20" + attribute \src "libresoc.v:61418.7-61418.20" wire $0\initial[0:0] - attribute \src "libresoc.v:62376.3-62388.6" + attribute \src "libresoc.v:62437.3-62449.6" wire width 3 $1\MUL_cr_in[2:0] - attribute \src "libresoc.v:62389.3-62401.6" + attribute \src "libresoc.v:62450.3-62462.6" wire width 3 $1\MUL_cr_out[2:0] - attribute \src "libresoc.v:62337.3-62349.6" + attribute \src "libresoc.v:62398.3-62410.6" wire width 14 $1\MUL_function_unit[13:0] - attribute \src "libresoc.v:62363.3-62375.6" + attribute \src "libresoc.v:62424.3-62436.6" wire width 4 $1\MUL_in2_sel[3:0] - attribute \src "libresoc.v:62350.3-62362.6" + attribute \src "libresoc.v:62411.3-62423.6" wire width 7 $1\MUL_internal_op[6:0] - attribute \src "libresoc.v:62415.3-62427.6" + attribute \src "libresoc.v:62476.3-62488.6" wire $1\MUL_is_32b[0:0] - attribute \src "libresoc.v:62402.3-62414.6" + attribute \src "libresoc.v:62463.3-62475.6" wire width 2 $1\MUL_rc_sel[1:0] - attribute \src "libresoc.v:62428.3-62440.6" + attribute \src "libresoc.v:62489.3-62501.6" wire $1\MUL_sgn[0:0] - attribute \src "libresoc.v:62325.17-62325.211" - wire width 32 $ternary$libresoc.v:62325$3531_Y + attribute \src "libresoc.v:62386.17-62386.211" + wire width 32 $ternary$libresoc.v:62386$3531_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" @@ -104342,7 +104390,7 @@ module \dec$158 wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:61357.7-61357.15" + attribute \src "libresoc.v:61418.7-61418.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in @@ -104351,15 +104399,15 @@ module \dec$158 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 20 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" - cell $mux $ternary$libresoc.v:62325$3531 + cell $mux $ternary$libresoc.v:62386$3531 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:62325$3531_Y + connect \Y $ternary$libresoc.v:62386$3531_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:62326.13-62336.4" + attribute \src "libresoc.v:62387.13-62397.4" cell \MUL_dec31 \MUL_dec31 connect \MUL_dec31_cr_in \MUL_dec31_MUL_dec31_cr_in connect \MUL_dec31_cr_out \MUL_dec31_MUL_dec31_cr_out @@ -104371,22 +104419,22 @@ module \dec$158 connect \MUL_dec31_sgn \MUL_dec31_MUL_dec31_sgn connect \opcode_in \MUL_dec31_opcode_in end - attribute \src "libresoc.v:61357.7-61357.20" - process $proc$libresoc.v:61357$3540 + attribute \src "libresoc.v:61418.7-61418.20" + process $proc$libresoc.v:61418$3540 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:62337.3-62349.6" - process $proc$libresoc.v:62337$3532 + attribute \src "libresoc.v:62398.3-62410.6" + process $proc$libresoc.v:62398$3532 assign { } { } assign { } { } assign $0\MUL_function_unit[13:0] $1\MUL_function_unit[13:0] - attribute \src "libresoc.v:62338.5-62338.29" + attribute \src "libresoc.v:62399.5-62399.29" switch \initial - attribute \src "libresoc.v:62338.9-62338.17" + attribute \src "libresoc.v:62399.9-62399.17" case 1'1 case end @@ -104406,14 +104454,14 @@ module \dec$158 sync always update \MUL_function_unit $0\MUL_function_unit[13:0] end - attribute \src "libresoc.v:62350.3-62362.6" - process $proc$libresoc.v:62350$3533 + attribute \src "libresoc.v:62411.3-62423.6" + process $proc$libresoc.v:62411$3533 assign { } { } assign { } { } assign $0\MUL_internal_op[6:0] $1\MUL_internal_op[6:0] - attribute \src "libresoc.v:62351.5-62351.29" + attribute \src "libresoc.v:62412.5-62412.29" switch \initial - attribute \src "libresoc.v:62351.9-62351.17" + attribute \src "libresoc.v:62412.9-62412.17" case 1'1 case end @@ -104433,14 +104481,14 @@ module \dec$158 sync always update \MUL_internal_op $0\MUL_internal_op[6:0] end - attribute \src "libresoc.v:62363.3-62375.6" - process $proc$libresoc.v:62363$3534 + attribute \src "libresoc.v:62424.3-62436.6" + process $proc$libresoc.v:62424$3534 assign { } { } assign { } { } assign $0\MUL_in2_sel[3:0] $1\MUL_in2_sel[3:0] - attribute \src "libresoc.v:62364.5-62364.29" + attribute \src "libresoc.v:62425.5-62425.29" switch \initial - attribute \src "libresoc.v:62364.9-62364.17" + attribute \src "libresoc.v:62425.9-62425.17" case 1'1 case end @@ -104460,14 +104508,14 @@ module \dec$158 sync always update \MUL_in2_sel $0\MUL_in2_sel[3:0] end - attribute \src "libresoc.v:62376.3-62388.6" - process $proc$libresoc.v:62376$3535 + attribute \src "libresoc.v:62437.3-62449.6" + process $proc$libresoc.v:62437$3535 assign { } { } assign { } { } assign $0\MUL_cr_in[2:0] $1\MUL_cr_in[2:0] - attribute \src "libresoc.v:62377.5-62377.29" + attribute \src "libresoc.v:62438.5-62438.29" switch \initial - attribute \src "libresoc.v:62377.9-62377.17" + attribute \src "libresoc.v:62438.9-62438.17" case 1'1 case end @@ -104487,14 +104535,14 @@ module \dec$158 sync always update \MUL_cr_in $0\MUL_cr_in[2:0] end - attribute \src "libresoc.v:62389.3-62401.6" - process $proc$libresoc.v:62389$3536 + attribute \src "libresoc.v:62450.3-62462.6" + process $proc$libresoc.v:62450$3536 assign { } { } assign { } { } assign $0\MUL_cr_out[2:0] $1\MUL_cr_out[2:0] - attribute \src "libresoc.v:62390.5-62390.29" + attribute \src "libresoc.v:62451.5-62451.29" switch \initial - attribute \src "libresoc.v:62390.9-62390.17" + attribute \src "libresoc.v:62451.9-62451.17" case 1'1 case end @@ -104514,14 +104562,14 @@ module \dec$158 sync always update \MUL_cr_out $0\MUL_cr_out[2:0] end - attribute \src "libresoc.v:62402.3-62414.6" - process $proc$libresoc.v:62402$3537 + attribute \src "libresoc.v:62463.3-62475.6" + process $proc$libresoc.v:62463$3537 assign { } { } assign { } { } assign $0\MUL_rc_sel[1:0] $1\MUL_rc_sel[1:0] - attribute \src "libresoc.v:62403.5-62403.29" + attribute \src "libresoc.v:62464.5-62464.29" switch \initial - attribute \src "libresoc.v:62403.9-62403.17" + attribute \src "libresoc.v:62464.9-62464.17" case 1'1 case end @@ -104541,14 +104589,14 @@ module \dec$158 sync always update \MUL_rc_sel $0\MUL_rc_sel[1:0] end - attribute \src "libresoc.v:62415.3-62427.6" - process $proc$libresoc.v:62415$3538 + attribute \src "libresoc.v:62476.3-62488.6" + process $proc$libresoc.v:62476$3538 assign { } { } assign { } { } assign $0\MUL_is_32b[0:0] $1\MUL_is_32b[0:0] - attribute \src "libresoc.v:62416.5-62416.29" + attribute \src "libresoc.v:62477.5-62477.29" switch \initial - attribute \src "libresoc.v:62416.9-62416.17" + attribute \src "libresoc.v:62477.9-62477.17" case 1'1 case end @@ -104568,14 +104616,14 @@ module \dec$158 sync always update \MUL_is_32b $0\MUL_is_32b[0:0] end - attribute \src "libresoc.v:62428.3-62440.6" - process $proc$libresoc.v:62428$3539 + attribute \src "libresoc.v:62489.3-62501.6" + process $proc$libresoc.v:62489$3539 assign { } { } assign { } { } assign $0\MUL_sgn[0:0] $1\MUL_sgn[0:0] - attribute \src "libresoc.v:62429.5-62429.29" + attribute \src "libresoc.v:62490.5-62490.29" switch \initial - attribute \src "libresoc.v:62429.9-62429.17" + attribute \src "libresoc.v:62490.9-62490.17" case 1'1 case end @@ -104595,7 +104643,7 @@ module \dec$158 sync always update \MUL_sgn $0\MUL_sgn[0:0] end - connect \$1 $ternary$libresoc.v:62325$3531_Y + connect \$1 $ternary$libresoc.v:62386$3531_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -104933,59 +104981,59 @@ module \dec$158 connect \MUL_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:62781.1-64535.10" +attribute \src "libresoc.v:62842.1-64596.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec" attribute \generator "nMigen" module \dec$162 - attribute \src "libresoc.v:64110.3-64131.6" + attribute \src "libresoc.v:64171.3-64192.6" wire width 3 $0\SHIFT_ROT_cr_in[2:0] - attribute \src "libresoc.v:64132.3-64153.6" + attribute \src "libresoc.v:64193.3-64214.6" wire width 3 $0\SHIFT_ROT_cr_out[2:0] - attribute \src "libresoc.v:64176.3-64197.6" + attribute \src "libresoc.v:64237.3-64258.6" wire width 2 $0\SHIFT_ROT_cry_in[1:0] - attribute \src "libresoc.v:63978.3-63999.6" + attribute \src "libresoc.v:64039.3-64060.6" wire $0\SHIFT_ROT_cry_out[0:0] - attribute \src "libresoc.v:64044.3-64065.6" + attribute \src "libresoc.v:64105.3-64126.6" wire width 14 $0\SHIFT_ROT_function_unit[13:0] - attribute \src "libresoc.v:64088.3-64109.6" + attribute \src "libresoc.v:64149.3-64170.6" wire width 4 $0\SHIFT_ROT_in2_sel[3:0] - attribute \src "libresoc.v:64066.3-64087.6" + attribute \src "libresoc.v:64127.3-64148.6" wire width 7 $0\SHIFT_ROT_internal_op[6:0] - attribute \src "libresoc.v:63956.3-63977.6" + attribute \src "libresoc.v:64017.3-64038.6" wire $0\SHIFT_ROT_inv_a[0:0] - attribute \src "libresoc.v:64000.3-64021.6" + attribute \src "libresoc.v:64061.3-64082.6" wire $0\SHIFT_ROT_is_32b[0:0] - attribute \src "libresoc.v:64154.3-64175.6" + attribute \src "libresoc.v:64215.3-64236.6" wire width 2 $0\SHIFT_ROT_rc_sel[1:0] - attribute \src "libresoc.v:64022.3-64043.6" + attribute \src "libresoc.v:64083.3-64104.6" wire $0\SHIFT_ROT_sgn[0:0] - attribute \src "libresoc.v:62782.7-62782.20" + attribute \src "libresoc.v:62843.7-62843.20" wire $0\initial[0:0] - attribute \src "libresoc.v:64110.3-64131.6" + attribute \src "libresoc.v:64171.3-64192.6" wire width 3 $1\SHIFT_ROT_cr_in[2:0] - attribute \src "libresoc.v:64132.3-64153.6" + attribute \src "libresoc.v:64193.3-64214.6" wire width 3 $1\SHIFT_ROT_cr_out[2:0] - attribute \src "libresoc.v:64176.3-64197.6" + attribute \src "libresoc.v:64237.3-64258.6" wire width 2 $1\SHIFT_ROT_cry_in[1:0] - attribute \src "libresoc.v:63978.3-63999.6" + attribute \src "libresoc.v:64039.3-64060.6" wire $1\SHIFT_ROT_cry_out[0:0] - attribute \src "libresoc.v:64044.3-64065.6" + attribute \src "libresoc.v:64105.3-64126.6" wire width 14 $1\SHIFT_ROT_function_unit[13:0] - attribute \src "libresoc.v:64088.3-64109.6" + attribute \src "libresoc.v:64149.3-64170.6" wire width 4 $1\SHIFT_ROT_in2_sel[3:0] - attribute \src "libresoc.v:64066.3-64087.6" + attribute \src "libresoc.v:64127.3-64148.6" wire width 7 $1\SHIFT_ROT_internal_op[6:0] - attribute \src "libresoc.v:63956.3-63977.6" + attribute \src "libresoc.v:64017.3-64038.6" wire $1\SHIFT_ROT_inv_a[0:0] - attribute \src "libresoc.v:64000.3-64021.6" + attribute \src "libresoc.v:64061.3-64082.6" wire $1\SHIFT_ROT_is_32b[0:0] - attribute \src "libresoc.v:64154.3-64175.6" + attribute \src "libresoc.v:64215.3-64236.6" wire width 2 $1\SHIFT_ROT_rc_sel[1:0] - attribute \src "libresoc.v:64022.3-64043.6" + attribute \src "libresoc.v:64083.3-64104.6" wire $1\SHIFT_ROT_sgn[0:0] - attribute \src "libresoc.v:63927.17-63927.211" - wire width 32 $ternary$libresoc.v:63927$3541_Y + attribute \src "libresoc.v:63988.17-63988.211" + wire width 32 $ternary$libresoc.v:63988$3541_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" @@ -106113,7 +106161,7 @@ module \dec$162 wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:62782.7-62782.15" + attribute \src "libresoc.v:62843.7-62843.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in @@ -106122,15 +106170,15 @@ module \dec$162 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 24 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" - cell $mux $ternary$libresoc.v:63927$3541 + cell $mux $ternary$libresoc.v:63988$3541 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:63927$3541_Y + connect \Y $ternary$libresoc.v:63988$3541_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:63928.19-63941.4" + attribute \src "libresoc.v:63989.19-64002.4" cell \SHIFT_ROT_dec30 \SHIFT_ROT_dec30 connect \SHIFT_ROT_dec30_cr_in \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in connect \SHIFT_ROT_dec30_cr_out \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out @@ -106146,7 +106194,7 @@ module \dec$162 connect \opcode_in \SHIFT_ROT_dec30_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:63942.19-63955.4" + attribute \src "libresoc.v:64003.19-64016.4" cell \SHIFT_ROT_dec31 \SHIFT_ROT_dec31 connect \SHIFT_ROT_dec31_cr_in \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in connect \SHIFT_ROT_dec31_cr_out \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out @@ -106161,22 +106209,22 @@ module \dec$162 connect \SHIFT_ROT_dec31_sgn \SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn connect \opcode_in \SHIFT_ROT_dec31_opcode_in end - attribute \src "libresoc.v:62782.7-62782.20" - process $proc$libresoc.v:62782$3553 + attribute \src "libresoc.v:62843.7-62843.20" + process $proc$libresoc.v:62843$3553 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:63956.3-63977.6" - process $proc$libresoc.v:63956$3542 + attribute \src "libresoc.v:64017.3-64038.6" + process $proc$libresoc.v:64017$3542 assign { } { } assign { } { } assign $0\SHIFT_ROT_inv_a[0:0] $1\SHIFT_ROT_inv_a[0:0] - attribute \src "libresoc.v:63957.5-63957.29" + attribute \src "libresoc.v:64018.5-64018.29" switch \initial - attribute \src "libresoc.v:63957.9-63957.17" + attribute \src "libresoc.v:64018.9-64018.17" case 1'1 case end @@ -106208,14 +106256,14 @@ module \dec$162 sync always update \SHIFT_ROT_inv_a $0\SHIFT_ROT_inv_a[0:0] end - attribute \src "libresoc.v:63978.3-63999.6" - process $proc$libresoc.v:63978$3543 + attribute \src "libresoc.v:64039.3-64060.6" + process $proc$libresoc.v:64039$3543 assign { } { } assign { } { } assign $0\SHIFT_ROT_cry_out[0:0] $1\SHIFT_ROT_cry_out[0:0] - attribute \src "libresoc.v:63979.5-63979.29" + attribute \src "libresoc.v:64040.5-64040.29" switch \initial - attribute \src "libresoc.v:63979.9-63979.17" + attribute \src "libresoc.v:64040.9-64040.17" case 1'1 case end @@ -106247,14 +106295,14 @@ module \dec$162 sync always update \SHIFT_ROT_cry_out $0\SHIFT_ROT_cry_out[0:0] end - attribute \src "libresoc.v:64000.3-64021.6" - process $proc$libresoc.v:64000$3544 + attribute \src "libresoc.v:64061.3-64082.6" + process $proc$libresoc.v:64061$3544 assign { } { } assign { } { } assign $0\SHIFT_ROT_is_32b[0:0] $1\SHIFT_ROT_is_32b[0:0] - attribute \src "libresoc.v:64001.5-64001.29" + attribute \src "libresoc.v:64062.5-64062.29" switch \initial - attribute \src "libresoc.v:64001.9-64001.17" + attribute \src "libresoc.v:64062.9-64062.17" case 1'1 case end @@ -106286,14 +106334,14 @@ module \dec$162 sync always update \SHIFT_ROT_is_32b $0\SHIFT_ROT_is_32b[0:0] end - attribute \src "libresoc.v:64022.3-64043.6" - process $proc$libresoc.v:64022$3545 + attribute \src "libresoc.v:64083.3-64104.6" + process $proc$libresoc.v:64083$3545 assign { } { } assign { } { } assign $0\SHIFT_ROT_sgn[0:0] $1\SHIFT_ROT_sgn[0:0] - attribute \src "libresoc.v:64023.5-64023.29" + attribute \src "libresoc.v:64084.5-64084.29" switch \initial - attribute \src "libresoc.v:64023.9-64023.17" + attribute \src "libresoc.v:64084.9-64084.17" case 1'1 case end @@ -106325,14 +106373,14 @@ module \dec$162 sync always update \SHIFT_ROT_sgn $0\SHIFT_ROT_sgn[0:0] end - attribute \src "libresoc.v:64044.3-64065.6" - process $proc$libresoc.v:64044$3546 + attribute \src "libresoc.v:64105.3-64126.6" + process $proc$libresoc.v:64105$3546 assign { } { } assign { } { } assign $0\SHIFT_ROT_function_unit[13:0] $1\SHIFT_ROT_function_unit[13:0] - attribute \src "libresoc.v:64045.5-64045.29" + attribute \src "libresoc.v:64106.5-64106.29" switch \initial - attribute \src "libresoc.v:64045.9-64045.17" + attribute \src "libresoc.v:64106.9-64106.17" case 1'1 case end @@ -106364,14 +106412,14 @@ module \dec$162 sync always update \SHIFT_ROT_function_unit $0\SHIFT_ROT_function_unit[13:0] end - attribute \src "libresoc.v:64066.3-64087.6" - process $proc$libresoc.v:64066$3547 + attribute \src "libresoc.v:64127.3-64148.6" + process $proc$libresoc.v:64127$3547 assign { } { } assign { } { } assign $0\SHIFT_ROT_internal_op[6:0] $1\SHIFT_ROT_internal_op[6:0] - attribute \src "libresoc.v:64067.5-64067.29" + attribute \src "libresoc.v:64128.5-64128.29" switch \initial - attribute \src "libresoc.v:64067.9-64067.17" + attribute \src "libresoc.v:64128.9-64128.17" case 1'1 case end @@ -106403,14 +106451,14 @@ module \dec$162 sync always update \SHIFT_ROT_internal_op $0\SHIFT_ROT_internal_op[6:0] end - attribute \src "libresoc.v:64088.3-64109.6" - process $proc$libresoc.v:64088$3548 + attribute \src "libresoc.v:64149.3-64170.6" + process $proc$libresoc.v:64149$3548 assign { } { } assign { } { } assign $0\SHIFT_ROT_in2_sel[3:0] $1\SHIFT_ROT_in2_sel[3:0] - attribute \src "libresoc.v:64089.5-64089.29" + attribute \src "libresoc.v:64150.5-64150.29" switch \initial - attribute \src "libresoc.v:64089.9-64089.17" + attribute \src "libresoc.v:64150.9-64150.17" case 1'1 case end @@ -106442,14 +106490,14 @@ module \dec$162 sync always update \SHIFT_ROT_in2_sel $0\SHIFT_ROT_in2_sel[3:0] end - attribute \src "libresoc.v:64110.3-64131.6" - process $proc$libresoc.v:64110$3549 + attribute \src "libresoc.v:64171.3-64192.6" + process $proc$libresoc.v:64171$3549 assign { } { } assign { } { } assign $0\SHIFT_ROT_cr_in[2:0] $1\SHIFT_ROT_cr_in[2:0] - attribute \src "libresoc.v:64111.5-64111.29" + attribute \src "libresoc.v:64172.5-64172.29" switch \initial - attribute \src "libresoc.v:64111.9-64111.17" + attribute \src "libresoc.v:64172.9-64172.17" case 1'1 case end @@ -106481,14 +106529,14 @@ module \dec$162 sync always update \SHIFT_ROT_cr_in $0\SHIFT_ROT_cr_in[2:0] end - attribute \src "libresoc.v:64132.3-64153.6" - process $proc$libresoc.v:64132$3550 + attribute \src "libresoc.v:64193.3-64214.6" + process $proc$libresoc.v:64193$3550 assign { } { } assign { } { } assign $0\SHIFT_ROT_cr_out[2:0] $1\SHIFT_ROT_cr_out[2:0] - attribute \src "libresoc.v:64133.5-64133.29" + attribute \src "libresoc.v:64194.5-64194.29" switch \initial - attribute \src "libresoc.v:64133.9-64133.17" + attribute \src "libresoc.v:64194.9-64194.17" case 1'1 case end @@ -106520,14 +106568,14 @@ module \dec$162 sync always update \SHIFT_ROT_cr_out $0\SHIFT_ROT_cr_out[2:0] end - attribute \src "libresoc.v:64154.3-64175.6" - process $proc$libresoc.v:64154$3551 + attribute \src "libresoc.v:64215.3-64236.6" + process $proc$libresoc.v:64215$3551 assign { } { } assign { } { } assign $0\SHIFT_ROT_rc_sel[1:0] $1\SHIFT_ROT_rc_sel[1:0] - attribute \src "libresoc.v:64155.5-64155.29" + attribute \src "libresoc.v:64216.5-64216.29" switch \initial - attribute \src "libresoc.v:64155.9-64155.17" + attribute \src "libresoc.v:64216.9-64216.17" case 1'1 case end @@ -106559,14 +106607,14 @@ module \dec$162 sync always update \SHIFT_ROT_rc_sel $0\SHIFT_ROT_rc_sel[1:0] end - attribute \src "libresoc.v:64176.3-64197.6" - process $proc$libresoc.v:64176$3552 + attribute \src "libresoc.v:64237.3-64258.6" + process $proc$libresoc.v:64237$3552 assign { } { } assign { } { } assign $0\SHIFT_ROT_cry_in[1:0] $1\SHIFT_ROT_cry_in[1:0] - attribute \src "libresoc.v:64177.5-64177.29" + attribute \src "libresoc.v:64238.5-64238.29" switch \initial - attribute \src "libresoc.v:64177.9-64177.17" + attribute \src "libresoc.v:64238.9-64238.17" case 1'1 case end @@ -106598,7 +106646,7 @@ module \dec$162 sync always update \SHIFT_ROT_cry_in $0\SHIFT_ROT_cry_in[1:0] end - connect \$1 $ternary$libresoc.v:63927$3541_Y + connect \$1 $ternary$libresoc.v:63988$3541_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -106937,67 +106985,67 @@ module \dec$162 connect \SHIFT_ROT_dec30_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:64539.1-67048.10" +attribute \src "libresoc.v:64600.1-67109.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec" attribute \generator "nMigen" module \dec$166 - attribute \src "libresoc.v:66130.3-66187.6" + attribute \src "libresoc.v:66191.3-66248.6" wire $0\LDST_br[0:0] - attribute \src "libresoc.v:66594.3-66651.6" + attribute \src "libresoc.v:66655.3-66712.6" wire width 3 $0\LDST_cr_in[2:0] - attribute \src "libresoc.v:66652.3-66709.6" + attribute \src "libresoc.v:66713.3-66770.6" wire width 3 $0\LDST_cr_out[2:0] - attribute \src "libresoc.v:66362.3-66419.6" + attribute \src "libresoc.v:66423.3-66480.6" wire width 14 $0\LDST_function_unit[13:0] - attribute \src "libresoc.v:66478.3-66535.6" + attribute \src "libresoc.v:66539.3-66596.6" wire width 3 $0\LDST_in1_sel[2:0] - attribute \src "libresoc.v:66536.3-66593.6" + attribute \src "libresoc.v:66597.3-66654.6" wire width 4 $0\LDST_in2_sel[3:0] - attribute \src "libresoc.v:66420.3-66477.6" + attribute \src "libresoc.v:66481.3-66538.6" wire width 7 $0\LDST_internal_op[6:0] - attribute \src "libresoc.v:66246.3-66303.6" + attribute \src "libresoc.v:66307.3-66364.6" wire $0\LDST_is_32b[0:0] - attribute \src "libresoc.v:65956.3-66013.6" + attribute \src "libresoc.v:66017.3-66074.6" wire width 4 $0\LDST_ldst_len[3:0] - attribute \src "libresoc.v:66072.3-66129.6" + attribute \src "libresoc.v:66133.3-66190.6" wire width 2 $0\LDST_rc_sel[1:0] - attribute \src "libresoc.v:66304.3-66361.6" + attribute \src "libresoc.v:66365.3-66422.6" wire $0\LDST_sgn[0:0] - attribute \src "libresoc.v:66188.3-66245.6" + attribute \src "libresoc.v:66249.3-66306.6" wire $0\LDST_sgn_ext[0:0] - attribute \src "libresoc.v:66014.3-66071.6" + attribute \src "libresoc.v:66075.3-66132.6" wire width 2 $0\LDST_upd[1:0] - attribute \src "libresoc.v:64540.7-64540.20" + attribute \src "libresoc.v:64601.7-64601.20" wire $0\initial[0:0] - attribute \src "libresoc.v:66130.3-66187.6" + attribute \src "libresoc.v:66191.3-66248.6" wire $1\LDST_br[0:0] - attribute \src "libresoc.v:66594.3-66651.6" + attribute \src "libresoc.v:66655.3-66712.6" wire width 3 $1\LDST_cr_in[2:0] - attribute \src "libresoc.v:66652.3-66709.6" + attribute \src "libresoc.v:66713.3-66770.6" wire width 3 $1\LDST_cr_out[2:0] - attribute \src "libresoc.v:66362.3-66419.6" + attribute \src "libresoc.v:66423.3-66480.6" wire width 14 $1\LDST_function_unit[13:0] - attribute \src "libresoc.v:66478.3-66535.6" + attribute \src "libresoc.v:66539.3-66596.6" wire width 3 $1\LDST_in1_sel[2:0] - attribute \src "libresoc.v:66536.3-66593.6" + attribute \src "libresoc.v:66597.3-66654.6" wire width 4 $1\LDST_in2_sel[3:0] - attribute \src "libresoc.v:66420.3-66477.6" + attribute \src "libresoc.v:66481.3-66538.6" wire width 7 $1\LDST_internal_op[6:0] - attribute \src "libresoc.v:66246.3-66303.6" + attribute \src "libresoc.v:66307.3-66364.6" wire $1\LDST_is_32b[0:0] - attribute \src "libresoc.v:65956.3-66013.6" + attribute \src "libresoc.v:66017.3-66074.6" wire width 4 $1\LDST_ldst_len[3:0] - attribute \src "libresoc.v:66072.3-66129.6" + attribute \src "libresoc.v:66133.3-66190.6" wire width 2 $1\LDST_rc_sel[1:0] - attribute \src "libresoc.v:66304.3-66361.6" + attribute \src "libresoc.v:66365.3-66422.6" wire $1\LDST_sgn[0:0] - attribute \src "libresoc.v:66188.3-66245.6" + attribute \src "libresoc.v:66249.3-66306.6" wire $1\LDST_sgn_ext[0:0] - attribute \src "libresoc.v:66014.3-66071.6" + attribute \src "libresoc.v:66075.3-66132.6" wire width 2 $1\LDST_upd[1:0] - attribute \src "libresoc.v:65907.17-65907.211" - wire width 32 $ternary$libresoc.v:65907$3554_Y + attribute \src "libresoc.v:65968.17-65968.211" + wire width 32 $ternary$libresoc.v:65968$3554_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:483" @@ -108346,7 +108394,7 @@ module \dec$166 wire width 6 \all_PO attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:466" wire input 1 \bigendian - attribute \src "libresoc.v:64540.7-64540.15" + attribute \src "libresoc.v:64601.7-64601.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 output 2 \opcode_in @@ -108355,15 +108403,15 @@ module \dec$166 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:465" wire width 32 input 26 \raw_opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" - cell $mux $ternary$libresoc.v:65907$3554 + cell $mux $ternary$libresoc.v:65968$3554 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:65907$3554_Y + connect \Y $ternary$libresoc.v:65968$3554_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:65908.14-65923.4" + attribute \src "libresoc.v:65969.14-65984.4" cell \LDST_dec31 \LDST_dec31 connect \LDST_dec31_br \LDST_dec31_LDST_dec31_br connect \LDST_dec31_cr_in \LDST_dec31_LDST_dec31_cr_in @@ -108381,7 +108429,7 @@ module \dec$166 connect \opcode_in \LDST_dec31_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:65924.14-65939.4" + attribute \src "libresoc.v:65985.14-66000.4" cell \LDST_dec58 \LDST_dec58 connect \LDST_dec58_br \LDST_dec58_LDST_dec58_br connect \LDST_dec58_cr_in \LDST_dec58_LDST_dec58_cr_in @@ -108399,7 +108447,7 @@ module \dec$166 connect \opcode_in \LDST_dec58_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:65940.14-65955.4" + attribute \src "libresoc.v:66001.14-66016.4" cell \LDST_dec62 \LDST_dec62 connect \LDST_dec62_br \LDST_dec62_LDST_dec62_br connect \LDST_dec62_cr_in \LDST_dec62_LDST_dec62_cr_in @@ -108416,22 +108464,22 @@ module \dec$166 connect \LDST_dec62_upd \LDST_dec62_LDST_dec62_upd connect \opcode_in \LDST_dec62_opcode_in end - attribute \src "libresoc.v:64540.7-64540.20" - process $proc$libresoc.v:64540$3568 + attribute \src "libresoc.v:64601.7-64601.20" + process $proc$libresoc.v:64601$3568 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:65956.3-66013.6" - process $proc$libresoc.v:65956$3555 + attribute \src "libresoc.v:66017.3-66074.6" + process $proc$libresoc.v:66017$3555 assign { } { } assign { } { } assign $0\LDST_ldst_len[3:0] $1\LDST_ldst_len[3:0] - attribute \src "libresoc.v:65957.5-65957.29" + attribute \src "libresoc.v:66018.5-66018.29" switch \initial - attribute \src "libresoc.v:65957.9-65957.17" + attribute \src "libresoc.v:66018.9-66018.17" case 1'1 case end @@ -108511,14 +108559,14 @@ module \dec$166 sync always update \LDST_ldst_len $0\LDST_ldst_len[3:0] end - attribute \src "libresoc.v:66014.3-66071.6" - process $proc$libresoc.v:66014$3556 + attribute \src "libresoc.v:66075.3-66132.6" + process $proc$libresoc.v:66075$3556 assign { } { } assign { } { } assign $0\LDST_upd[1:0] $1\LDST_upd[1:0] - attribute \src "libresoc.v:66015.5-66015.29" + attribute \src "libresoc.v:66076.5-66076.29" switch \initial - attribute \src "libresoc.v:66015.9-66015.17" + attribute \src "libresoc.v:66076.9-66076.17" case 1'1 case end @@ -108598,14 +108646,14 @@ module \dec$166 sync always update \LDST_upd $0\LDST_upd[1:0] end - attribute \src "libresoc.v:66072.3-66129.6" - process $proc$libresoc.v:66072$3557 + attribute \src "libresoc.v:66133.3-66190.6" + process $proc$libresoc.v:66133$3557 assign { } { } assign { } { } assign $0\LDST_rc_sel[1:0] $1\LDST_rc_sel[1:0] - attribute \src "libresoc.v:66073.5-66073.29" + attribute \src "libresoc.v:66134.5-66134.29" switch \initial - attribute \src "libresoc.v:66073.9-66073.17" + attribute \src "libresoc.v:66134.9-66134.17" case 1'1 case end @@ -108685,14 +108733,14 @@ module \dec$166 sync always update \LDST_rc_sel $0\LDST_rc_sel[1:0] end - attribute \src "libresoc.v:66130.3-66187.6" - process $proc$libresoc.v:66130$3558 + attribute \src "libresoc.v:66191.3-66248.6" + process $proc$libresoc.v:66191$3558 assign { } { } assign { } { } assign $0\LDST_br[0:0] $1\LDST_br[0:0] - attribute \src "libresoc.v:66131.5-66131.29" + attribute \src "libresoc.v:66192.5-66192.29" switch \initial - attribute \src "libresoc.v:66131.9-66131.17" + attribute \src "libresoc.v:66192.9-66192.17" case 1'1 case end @@ -108772,14 +108820,14 @@ module \dec$166 sync always update \LDST_br $0\LDST_br[0:0] end - attribute \src "libresoc.v:66188.3-66245.6" - process $proc$libresoc.v:66188$3559 + attribute \src "libresoc.v:66249.3-66306.6" + process $proc$libresoc.v:66249$3559 assign { } { } assign { } { } assign $0\LDST_sgn_ext[0:0] $1\LDST_sgn_ext[0:0] - attribute \src "libresoc.v:66189.5-66189.29" + attribute \src "libresoc.v:66250.5-66250.29" switch \initial - attribute \src "libresoc.v:66189.9-66189.17" + attribute \src "libresoc.v:66250.9-66250.17" case 1'1 case end @@ -108859,14 +108907,14 @@ module \dec$166 sync always update \LDST_sgn_ext $0\LDST_sgn_ext[0:0] end - attribute \src "libresoc.v:66246.3-66303.6" - process $proc$libresoc.v:66246$3560 + attribute \src "libresoc.v:66307.3-66364.6" + process $proc$libresoc.v:66307$3560 assign { } { } assign { } { } assign $0\LDST_is_32b[0:0] $1\LDST_is_32b[0:0] - attribute \src "libresoc.v:66247.5-66247.29" + attribute \src "libresoc.v:66308.5-66308.29" switch \initial - attribute \src "libresoc.v:66247.9-66247.17" + attribute \src "libresoc.v:66308.9-66308.17" case 1'1 case end @@ -108946,14 +108994,14 @@ module \dec$166 sync always update \LDST_is_32b $0\LDST_is_32b[0:0] end - attribute \src "libresoc.v:66304.3-66361.6" - process $proc$libresoc.v:66304$3561 + attribute \src "libresoc.v:66365.3-66422.6" + process $proc$libresoc.v:66365$3561 assign { } { } assign { } { } assign $0\LDST_sgn[0:0] $1\LDST_sgn[0:0] - attribute \src "libresoc.v:66305.5-66305.29" + attribute \src "libresoc.v:66366.5-66366.29" switch \initial - attribute \src "libresoc.v:66305.9-66305.17" + attribute \src "libresoc.v:66366.9-66366.17" case 1'1 case end @@ -109033,14 +109081,14 @@ module \dec$166 sync always update \LDST_sgn $0\LDST_sgn[0:0] end - attribute \src "libresoc.v:66362.3-66419.6" - process $proc$libresoc.v:66362$3562 + attribute \src "libresoc.v:66423.3-66480.6" + process $proc$libresoc.v:66423$3562 assign { } { } assign { } { } assign $0\LDST_function_unit[13:0] $1\LDST_function_unit[13:0] - attribute \src "libresoc.v:66363.5-66363.29" + attribute \src "libresoc.v:66424.5-66424.29" switch \initial - attribute \src "libresoc.v:66363.9-66363.17" + attribute \src "libresoc.v:66424.9-66424.17" case 1'1 case end @@ -109120,14 +109168,14 @@ module \dec$166 sync always update \LDST_function_unit $0\LDST_function_unit[13:0] end - attribute \src "libresoc.v:66420.3-66477.6" - process $proc$libresoc.v:66420$3563 + attribute \src "libresoc.v:66481.3-66538.6" + process $proc$libresoc.v:66481$3563 assign { } { } assign { } { } assign $0\LDST_internal_op[6:0] $1\LDST_internal_op[6:0] - attribute \src "libresoc.v:66421.5-66421.29" + attribute \src "libresoc.v:66482.5-66482.29" switch \initial - attribute \src "libresoc.v:66421.9-66421.17" + attribute \src "libresoc.v:66482.9-66482.17" case 1'1 case end @@ -109207,14 +109255,14 @@ module \dec$166 sync always update \LDST_internal_op $0\LDST_internal_op[6:0] end - attribute \src "libresoc.v:66478.3-66535.6" - process $proc$libresoc.v:66478$3564 + attribute \src "libresoc.v:66539.3-66596.6" + process $proc$libresoc.v:66539$3564 assign { } { } assign { } { } assign $0\LDST_in1_sel[2:0] $1\LDST_in1_sel[2:0] - attribute \src "libresoc.v:66479.5-66479.29" + attribute \src "libresoc.v:66540.5-66540.29" switch \initial - attribute \src "libresoc.v:66479.9-66479.17" + attribute \src "libresoc.v:66540.9-66540.17" case 1'1 case end @@ -109294,14 +109342,14 @@ module \dec$166 sync always update \LDST_in1_sel $0\LDST_in1_sel[2:0] end - attribute \src "libresoc.v:66536.3-66593.6" - process $proc$libresoc.v:66536$3565 + attribute \src "libresoc.v:66597.3-66654.6" + process $proc$libresoc.v:66597$3565 assign { } { } assign { } { } assign $0\LDST_in2_sel[3:0] $1\LDST_in2_sel[3:0] - attribute \src "libresoc.v:66537.5-66537.29" + attribute \src "libresoc.v:66598.5-66598.29" switch \initial - attribute \src "libresoc.v:66537.9-66537.17" + attribute \src "libresoc.v:66598.9-66598.17" case 1'1 case end @@ -109381,14 +109429,14 @@ module \dec$166 sync always update \LDST_in2_sel $0\LDST_in2_sel[3:0] end - attribute \src "libresoc.v:66594.3-66651.6" - process $proc$libresoc.v:66594$3566 + attribute \src "libresoc.v:66655.3-66712.6" + process $proc$libresoc.v:66655$3566 assign { } { } assign { } { } assign $0\LDST_cr_in[2:0] $1\LDST_cr_in[2:0] - attribute \src "libresoc.v:66595.5-66595.29" + attribute \src "libresoc.v:66656.5-66656.29" switch \initial - attribute \src "libresoc.v:66595.9-66595.17" + attribute \src "libresoc.v:66656.9-66656.17" case 1'1 case end @@ -109468,14 +109516,14 @@ module \dec$166 sync always update \LDST_cr_in $0\LDST_cr_in[2:0] end - attribute \src "libresoc.v:66652.3-66709.6" - process $proc$libresoc.v:66652$3567 + attribute \src "libresoc.v:66713.3-66770.6" + process $proc$libresoc.v:66713$3567 assign { } { } assign { } { } assign $0\LDST_cr_out[2:0] $1\LDST_cr_out[2:0] - attribute \src "libresoc.v:66653.5-66653.29" + attribute \src "libresoc.v:66714.5-66714.29" switch \initial - attribute \src "libresoc.v:66653.9-66653.17" + attribute \src "libresoc.v:66714.9-66714.17" case 1'1 case end @@ -109555,7 +109603,7 @@ module \dec$166 sync always update \LDST_cr_out $0\LDST_cr_out[2:0] end - connect \$1 $ternary$libresoc.v:65907$3554_Y + connect \$1 $ternary$libresoc.v:65968$3554_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -109895,213 +109943,213 @@ module \dec$166 connect \LDST_dec31_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:67052.1-75269.10" +attribute \src "libresoc.v:67113.1-75333.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec" attribute \generator "nMigen" module \dec$171 - attribute \src "libresoc.v:70432.3-70576.6" + attribute \src "libresoc.v:70496.3-70640.6" wire width 2 $0\SV_Etype[1:0] - attribute \src "libresoc.v:70577.3-70721.6" + attribute \src "libresoc.v:70641.3-70785.6" wire width 2 $0\SV_Ptype[1:0] - attribute \src "libresoc.v:70290.3-70431.6" + attribute \src "libresoc.v:70351.3-70495.6" wire width 8 $0\asmcode[7:0] - attribute \src "libresoc.v:73622.3-73766.6" + attribute \src "libresoc.v:73686.3-73830.6" wire $0\br[0:0] - attribute \src "libresoc.v:71302.3-71446.6" + attribute \src "libresoc.v:71366.3-71510.6" wire width 3 $0\cr_in[2:0] - attribute \src "libresoc.v:71447.3-71591.6" + attribute \src "libresoc.v:71511.3-71655.6" wire width 3 $0\cr_out[2:0] - attribute \src "libresoc.v:73042.3-73186.6" + attribute \src "libresoc.v:73106.3-73250.6" wire width 2 $0\cry_in[1:0] - attribute \src "libresoc.v:73477.3-73621.6" + attribute \src "libresoc.v:73541.3-73685.6" wire $0\cry_out[0:0] - attribute \src "libresoc.v:70145.3-70289.6" + attribute \src "libresoc.v:70206.3-70350.6" wire width 5 $0\form[4:0] - attribute \src "libresoc.v:74637.3-74781.6" + attribute \src "libresoc.v:74701.3-74845.6" wire width 14 $0\function_unit[13:0] - attribute \src "libresoc.v:70722.3-70866.6" + attribute \src "libresoc.v:70786.3-70930.6" wire width 3 $0\in1_sel[2:0] - attribute \src "libresoc.v:70867.3-71011.6" + attribute \src "libresoc.v:70931.3-71075.6" wire width 4 $0\in2_sel[3:0] - attribute \src "libresoc.v:71012.3-71156.6" + attribute \src "libresoc.v:71076.3-71220.6" wire width 2 $0\in3_sel[1:0] - attribute \src "libresoc.v:67053.7-67053.20" + attribute \src "libresoc.v:67114.7-67114.20" wire $0\initial[0:0] - attribute \src "libresoc.v:74782.3-74926.6" + attribute \src "libresoc.v:74846.3-74990.6" wire width 7 $0\internal_op[6:0] - attribute \src "libresoc.v:73187.3-73331.6" + attribute \src "libresoc.v:73251.3-73395.6" wire $0\inv_a[0:0] - attribute \src "libresoc.v:73332.3-73476.6" + attribute \src "libresoc.v:73396.3-73540.6" wire $0\inv_out[0:0] - attribute \src "libresoc.v:74057.3-74201.6" + attribute \src "libresoc.v:74121.3-74265.6" wire $0\is_32b[0:0] - attribute \src "libresoc.v:72607.3-72751.6" + attribute \src "libresoc.v:72671.3-72815.6" wire width 4 $0\ldst_len[3:0] - attribute \src "libresoc.v:74347.3-74491.6" + attribute \src "libresoc.v:74411.3-74555.6" wire $0\lk[0:0] - attribute \src "libresoc.v:71157.3-71301.6" + attribute \src "libresoc.v:71221.3-71365.6" wire width 3 $0\out_sel[2:0] - attribute \src "libresoc.v:72897.3-73041.6" + attribute \src "libresoc.v:72961.3-73105.6" wire width 2 $0\rc_sel[1:0] - attribute \src "libresoc.v:73912.3-74056.6" + attribute \src "libresoc.v:73976.3-74120.6" wire $0\rsrv[0:0] - attribute \src "libresoc.v:74492.3-74636.6" + attribute \src "libresoc.v:74556.3-74700.6" wire $0\sgl_pipe[0:0] - attribute \src "libresoc.v:74202.3-74346.6" + attribute \src "libresoc.v:74266.3-74410.6" wire $0\sgn[0:0] - attribute \src "libresoc.v:73767.3-73911.6" + attribute \src "libresoc.v:73831.3-73975.6" wire $0\sgn_ext[0:0] - attribute \src "libresoc.v:72317.3-72461.6" + attribute \src "libresoc.v:72381.3-72525.6" wire width 3 $0\sv_cr_in[2:0] - attribute \src "libresoc.v:72462.3-72606.6" + attribute \src "libresoc.v:72526.3-72670.6" wire width 3 $0\sv_cr_out[2:0] - attribute \src "libresoc.v:71592.3-71736.6" + attribute \src "libresoc.v:71656.3-71800.6" wire width 3 $0\sv_in1[2:0] - attribute \src "libresoc.v:71737.3-71881.6" + attribute \src "libresoc.v:71801.3-71945.6" wire width 3 $0\sv_in2[2:0] - attribute \src "libresoc.v:71882.3-72026.6" + attribute \src "libresoc.v:71946.3-72090.6" wire width 3 $0\sv_in3[2:0] - attribute \src "libresoc.v:72172.3-72316.6" + attribute \src "libresoc.v:72236.3-72380.6" wire width 3 $0\sv_out2[2:0] - attribute \src "libresoc.v:72027.3-72171.6" + attribute \src "libresoc.v:72091.3-72235.6" wire width 3 $0\sv_out[2:0] - attribute \src "libresoc.v:72752.3-72896.6" + attribute \src "libresoc.v:72816.3-72960.6" wire width 2 $0\upd[1:0] - attribute \src "libresoc.v:70432.3-70576.6" + attribute \src "libresoc.v:70496.3-70640.6" wire width 2 $1\SV_Etype[1:0] - attribute \src "libresoc.v:70577.3-70721.6" + attribute \src "libresoc.v:70641.3-70785.6" wire width 2 $1\SV_Ptype[1:0] - attribute \src "libresoc.v:70290.3-70431.6" + attribute \src "libresoc.v:70351.3-70495.6" wire width 8 $1\asmcode[7:0] - attribute \src "libresoc.v:73622.3-73766.6" + attribute \src "libresoc.v:73686.3-73830.6" wire $1\br[0:0] - attribute \src "libresoc.v:71302.3-71446.6" + attribute \src "libresoc.v:71366.3-71510.6" wire width 3 $1\cr_in[2:0] - attribute \src "libresoc.v:71447.3-71591.6" + attribute \src "libresoc.v:71511.3-71655.6" wire width 3 $1\cr_out[2:0] - attribute \src "libresoc.v:73042.3-73186.6" + attribute \src "libresoc.v:73106.3-73250.6" wire width 2 $1\cry_in[1:0] - attribute \src "libresoc.v:73477.3-73621.6" + attribute \src "libresoc.v:73541.3-73685.6" wire $1\cry_out[0:0] - attribute \src "libresoc.v:70145.3-70289.6" + attribute \src "libresoc.v:70206.3-70350.6" wire width 5 $1\form[4:0] - attribute \src "libresoc.v:74637.3-74781.6" + attribute \src "libresoc.v:74701.3-74845.6" wire width 14 $1\function_unit[13:0] - attribute \src "libresoc.v:70722.3-70866.6" + attribute \src "libresoc.v:70786.3-70930.6" wire width 3 $1\in1_sel[2:0] - attribute \src "libresoc.v:70867.3-71011.6" + attribute \src "libresoc.v:70931.3-71075.6" wire width 4 $1\in2_sel[3:0] - attribute \src "libresoc.v:71012.3-71156.6" + attribute \src "libresoc.v:71076.3-71220.6" wire width 2 $1\in3_sel[1:0] - attribute \src "libresoc.v:74782.3-74926.6" + attribute \src "libresoc.v:74846.3-74990.6" wire width 7 $1\internal_op[6:0] - attribute \src "libresoc.v:73187.3-73331.6" + attribute \src "libresoc.v:73251.3-73395.6" wire $1\inv_a[0:0] - attribute \src "libresoc.v:73332.3-73476.6" + attribute \src "libresoc.v:73396.3-73540.6" wire $1\inv_out[0:0] - attribute \src "libresoc.v:74057.3-74201.6" + attribute \src "libresoc.v:74121.3-74265.6" wire $1\is_32b[0:0] - attribute \src "libresoc.v:72607.3-72751.6" + attribute \src "libresoc.v:72671.3-72815.6" wire width 4 $1\ldst_len[3:0] - attribute \src "libresoc.v:74347.3-74491.6" + attribute \src "libresoc.v:74411.3-74555.6" wire $1\lk[0:0] - attribute \src "libresoc.v:71157.3-71301.6" + attribute \src "libresoc.v:71221.3-71365.6" wire width 3 $1\out_sel[2:0] - attribute \src "libresoc.v:72897.3-73041.6" + attribute \src "libresoc.v:72961.3-73105.6" wire width 2 $1\rc_sel[1:0] - attribute \src "libresoc.v:73912.3-74056.6" + attribute \src "libresoc.v:73976.3-74120.6" wire $1\rsrv[0:0] - attribute \src "libresoc.v:74492.3-74636.6" + attribute \src "libresoc.v:74556.3-74700.6" wire $1\sgl_pipe[0:0] - attribute \src "libresoc.v:74202.3-74346.6" + attribute \src "libresoc.v:74266.3-74410.6" wire $1\sgn[0:0] - attribute \src "libresoc.v:73767.3-73911.6" + attribute \src "libresoc.v:73831.3-73975.6" wire $1\sgn_ext[0:0] - attribute \src "libresoc.v:72317.3-72461.6" + attribute \src "libresoc.v:72381.3-72525.6" wire width 3 $1\sv_cr_in[2:0] - attribute \src "libresoc.v:72462.3-72606.6" + attribute \src "libresoc.v:72526.3-72670.6" wire width 3 $1\sv_cr_out[2:0] - attribute \src "libresoc.v:71592.3-71736.6" + attribute \src "libresoc.v:71656.3-71800.6" wire width 3 $1\sv_in1[2:0] - attribute \src "libresoc.v:71737.3-71881.6" + attribute \src "libresoc.v:71801.3-71945.6" wire width 3 $1\sv_in2[2:0] - attribute \src "libresoc.v:71882.3-72026.6" + attribute \src "libresoc.v:71946.3-72090.6" wire width 3 $1\sv_in3[2:0] - attribute \src "libresoc.v:72172.3-72316.6" + attribute \src "libresoc.v:72236.3-72380.6" wire width 3 $1\sv_out2[2:0] - attribute \src "libresoc.v:72027.3-72171.6" + attribute \src "libresoc.v:72091.3-72235.6" wire width 3 $1\sv_out[2:0] - attribute \src "libresoc.v:72752.3-72896.6" + attribute \src "libresoc.v:72816.3-72960.6" wire width 2 $1\upd[1:0] - attribute \src "libresoc.v:70432.3-70576.6" + attribute \src "libresoc.v:70496.3-70640.6" wire width 2 $2\SV_Etype[1:0] - attribute \src "libresoc.v:70577.3-70721.6" + attribute \src "libresoc.v:70641.3-70785.6" wire width 2 $2\SV_Ptype[1:0] - attribute \src "libresoc.v:70290.3-70431.6" + attribute \src "libresoc.v:70351.3-70495.6" wire width 8 $2\asmcode[7:0] - attribute \src "libresoc.v:73622.3-73766.6" + attribute \src "libresoc.v:73686.3-73830.6" wire $2\br[0:0] - attribute \src "libresoc.v:71302.3-71446.6" + attribute \src "libresoc.v:71366.3-71510.6" wire width 3 $2\cr_in[2:0] - attribute \src "libresoc.v:71447.3-71591.6" + attribute \src "libresoc.v:71511.3-71655.6" wire width 3 $2\cr_out[2:0] - attribute \src "libresoc.v:73042.3-73186.6" + attribute \src "libresoc.v:73106.3-73250.6" wire width 2 $2\cry_in[1:0] - attribute \src "libresoc.v:73477.3-73621.6" + attribute \src "libresoc.v:73541.3-73685.6" wire $2\cry_out[0:0] - attribute \src "libresoc.v:70145.3-70289.6" + attribute \src "libresoc.v:70206.3-70350.6" wire width 5 $2\form[4:0] - attribute \src "libresoc.v:74637.3-74781.6" + attribute \src "libresoc.v:74701.3-74845.6" wire width 14 $2\function_unit[13:0] - attribute \src "libresoc.v:70722.3-70866.6" + attribute \src "libresoc.v:70786.3-70930.6" wire width 3 $2\in1_sel[2:0] - attribute \src "libresoc.v:70867.3-71011.6" + attribute \src "libresoc.v:70931.3-71075.6" wire width 4 $2\in2_sel[3:0] - attribute \src "libresoc.v:71012.3-71156.6" + attribute \src "libresoc.v:71076.3-71220.6" wire width 2 $2\in3_sel[1:0] - attribute \src "libresoc.v:74782.3-74926.6" + attribute \src "libresoc.v:74846.3-74990.6" wire width 7 $2\internal_op[6:0] - attribute \src "libresoc.v:73187.3-73331.6" + attribute \src "libresoc.v:73251.3-73395.6" wire $2\inv_a[0:0] - attribute \src "libresoc.v:73332.3-73476.6" + attribute \src "libresoc.v:73396.3-73540.6" wire $2\inv_out[0:0] - attribute \src "libresoc.v:74057.3-74201.6" + attribute \src "libresoc.v:74121.3-74265.6" wire $2\is_32b[0:0] - attribute \src "libresoc.v:72607.3-72751.6" + attribute \src "libresoc.v:72671.3-72815.6" wire width 4 $2\ldst_len[3:0] - attribute \src "libresoc.v:74347.3-74491.6" + attribute \src "libresoc.v:74411.3-74555.6" wire $2\lk[0:0] - attribute \src "libresoc.v:71157.3-71301.6" + attribute \src "libresoc.v:71221.3-71365.6" wire width 3 $2\out_sel[2:0] - attribute \src "libresoc.v:72897.3-73041.6" + attribute \src "libresoc.v:72961.3-73105.6" wire width 2 $2\rc_sel[1:0] - attribute \src "libresoc.v:73912.3-74056.6" + attribute \src "libresoc.v:73976.3-74120.6" wire $2\rsrv[0:0] - attribute \src "libresoc.v:74492.3-74636.6" + attribute \src "libresoc.v:74556.3-74700.6" wire $2\sgl_pipe[0:0] - attribute \src "libresoc.v:74202.3-74346.6" + attribute \src "libresoc.v:74266.3-74410.6" wire $2\sgn[0:0] - attribute \src "libresoc.v:73767.3-73911.6" + attribute \src "libresoc.v:73831.3-73975.6" wire $2\sgn_ext[0:0] - attribute \src "libresoc.v:72317.3-72461.6" + attribute \src "libresoc.v:72381.3-72525.6" wire width 3 $2\sv_cr_in[2:0] - attribute \src "libresoc.v:72462.3-72606.6" + attribute \src "libresoc.v:72526.3-72670.6" wire width 3 $2\sv_cr_out[2:0] - attribute \src "libresoc.v:71592.3-71736.6" + attribute \src "libresoc.v:71656.3-71800.6" wire width 3 $2\sv_in1[2:0] - attribute \src "libresoc.v:71737.3-71881.6" + attribute \src "libresoc.v:71801.3-71945.6" wire width 3 $2\sv_in2[2:0] - attribute \src "libresoc.v:71882.3-72026.6" + attribute \src "libresoc.v:71946.3-72090.6" wire width 3 $2\sv_in3[2:0] - attribute \src "libresoc.v:72172.3-72316.6" + attribute \src "libresoc.v:72236.3-72380.6" wire width 3 $2\sv_out2[2:0] - attribute \src "libresoc.v:72027.3-72171.6" + attribute \src "libresoc.v:72091.3-72235.6" wire width 3 $2\sv_out[2:0] - attribute \src "libresoc.v:72752.3-72896.6" + attribute \src "libresoc.v:72816.3-72960.6" wire width 2 $2\upd[1:0] - attribute \src "libresoc.v:69928.17-69928.211" - wire width 32 $ternary$libresoc.v:69928$3569_Y + attribute \src "libresoc.v:69989.17-69989.211" + wire width 32 $ternary$libresoc.v:69989$3569_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" wire width 32 \$2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" @@ -112767,7 +112815,7 @@ module \dec$171 attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 15 \in3_sel - attribute \src "libresoc.v:67053.7-67053.15" + attribute \src "libresoc.v:67114.7-67114.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -112965,15 +113013,15 @@ module \dec$171 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 18 \upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:506" - cell $mux $ternary$libresoc.v:69928$3569 + cell $mux $ternary$libresoc.v:69989$3569 parameter \WIDTH 32 connect \A \raw_opcode_in connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } connect \S \bigendian - connect \Y $ternary$libresoc.v:69928$3569_Y + connect \Y $ternary$libresoc.v:69989$3569_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:69929.9-69964.4" + attribute \src "libresoc.v:69990.9-70025.4" cell \dec19 \dec19 connect \dec19_SV_Etype \dec19_dec19_SV_Etype connect \dec19_SV_Ptype \dec19_dec19_SV_Ptype @@ -113011,7 +113059,7 @@ module \dec$171 connect \opcode_in \dec19_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:69965.9-70000.4" + attribute \src "libresoc.v:70026.9-70061.4" cell \dec22 \dec22 connect \dec22_SV_Etype \dec22_dec22_SV_Etype connect \dec22_SV_Ptype \dec22_dec22_SV_Ptype @@ -113049,7 +113097,7 @@ module \dec$171 connect \opcode_in \dec22_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:70001.9-70036.4" + attribute \src "libresoc.v:70062.9-70097.4" cell \dec30 \dec30 connect \dec30_SV_Etype \dec30_dec30_SV_Etype connect \dec30_SV_Ptype \dec30_dec30_SV_Ptype @@ -113087,7 +113135,7 @@ module \dec$171 connect \opcode_in \dec30_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:70037.9-70072.4" + attribute \src "libresoc.v:70098.9-70133.4" cell \dec31 \dec31 connect \dec31_SV_Etype \dec31_dec31_SV_Etype connect \dec31_SV_Ptype \dec31_dec31_SV_Ptype @@ -113125,7 +113173,7 @@ module \dec$171 connect \opcode_in \dec31_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:70073.9-70108.4" + attribute \src "libresoc.v:70134.9-70169.4" cell \dec58 \dec58 connect \dec58_SV_Etype \dec58_dec58_SV_Etype connect \dec58_SV_Ptype \dec58_dec58_SV_Ptype @@ -113163,7 +113211,7 @@ module \dec$171 connect \opcode_in \dec58_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:70109.9-70144.4" + attribute \src "libresoc.v:70170.9-70205.4" cell \dec62 \dec62 connect \dec62_SV_Etype \dec62_dec62_SV_Etype connect \dec62_SV_Ptype \dec62_dec62_SV_Ptype @@ -113200,23 +113248,23 @@ module \dec$171 connect \dec62_upd \dec62_dec62_upd connect \opcode_in \dec62_opcode_in end - attribute \src "libresoc.v:67053.7-67053.20" - process $proc$libresoc.v:67053$3603 + attribute \src "libresoc.v:67114.7-67114.20" + process $proc$libresoc.v:67114$3603 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:70145.3-70289.6" - process $proc$libresoc.v:70145$3570 + attribute \src "libresoc.v:70206.3-70350.6" + process $proc$libresoc.v:70206$3570 assign { } { } assign { } { } assign { } { } assign $0\form[4:0] $2\form[4:0] - attribute \src "libresoc.v:70146.5-70146.29" + attribute \src "libresoc.v:70207.5-70207.29" switch \initial - attribute \src "libresoc.v:70146.9-70146.17" + attribute \src "libresoc.v:70207.9-70207.17" case 1'1 case end @@ -113413,15 +113461,15 @@ module \dec$171 sync always update \form $0\form[4:0] end - attribute \src "libresoc.v:70290.3-70431.6" - process $proc$libresoc.v:70290$3571 + attribute \src "libresoc.v:70351.3-70495.6" + process $proc$libresoc.v:70351$3571 assign { } { } assign { } { } assign { } { } assign $0\asmcode[7:0] $2\asmcode[7:0] - attribute \src "libresoc.v:70291.5-70291.29" + attribute \src "libresoc.v:70352.5-70352.29" switch \initial - attribute \src "libresoc.v:70291.9-70291.17" + attribute \src "libresoc.v:70352.9-70352.17" case 1'1 case end @@ -113468,6 +113516,9 @@ module \dec$171 assign { } { } assign $1\asmcode[7:0] 8'00001001 attribute \src "libresoc.v:0.0-0.0" + case 6'010001 + assign $1\asmcode[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" case 6'011100 assign { } { } assign $1\asmcode[7:0] 8'00010001 @@ -113614,15 +113665,15 @@ module \dec$171 sync always update \asmcode $0\asmcode[7:0] end - attribute \src "libresoc.v:70432.3-70576.6" - process $proc$libresoc.v:70432$3572 + attribute \src "libresoc.v:70496.3-70640.6" + process $proc$libresoc.v:70496$3572 assign { } { } assign { } { } assign { } { } assign $0\SV_Etype[1:0] $2\SV_Etype[1:0] - attribute \src "libresoc.v:70433.5-70433.29" + attribute \src "libresoc.v:70497.5-70497.29" switch \initial - attribute \src "libresoc.v:70433.9-70433.17" + attribute \src "libresoc.v:70497.9-70497.17" case 1'1 case end @@ -113819,15 +113870,15 @@ module \dec$171 sync always update \SV_Etype $0\SV_Etype[1:0] end - attribute \src "libresoc.v:70577.3-70721.6" - process $proc$libresoc.v:70577$3573 + attribute \src "libresoc.v:70641.3-70785.6" + process $proc$libresoc.v:70641$3573 assign { } { } assign { } { } assign { } { } assign $0\SV_Ptype[1:0] $2\SV_Ptype[1:0] - attribute \src "libresoc.v:70578.5-70578.29" + attribute \src "libresoc.v:70642.5-70642.29" switch \initial - attribute \src "libresoc.v:70578.9-70578.17" + attribute \src "libresoc.v:70642.9-70642.17" case 1'1 case end @@ -114024,15 +114075,15 @@ module \dec$171 sync always update \SV_Ptype $0\SV_Ptype[1:0] end - attribute \src "libresoc.v:70722.3-70866.6" - process $proc$libresoc.v:70722$3574 + attribute \src "libresoc.v:70786.3-70930.6" + process $proc$libresoc.v:70786$3574 assign { } { } assign { } { } assign { } { } assign $0\in1_sel[2:0] $2\in1_sel[2:0] - attribute \src "libresoc.v:70723.5-70723.29" + attribute \src "libresoc.v:70787.5-70787.29" switch \initial - attribute \src "libresoc.v:70723.9-70723.17" + attribute \src "libresoc.v:70787.9-70787.17" case 1'1 case end @@ -114229,15 +114280,15 @@ module \dec$171 sync always update \in1_sel $0\in1_sel[2:0] end - attribute \src "libresoc.v:70867.3-71011.6" - process $proc$libresoc.v:70867$3575 + attribute \src "libresoc.v:70931.3-71075.6" + process $proc$libresoc.v:70931$3575 assign { } { } assign { } { } assign { } { } assign $0\in2_sel[3:0] $2\in2_sel[3:0] - attribute \src "libresoc.v:70868.5-70868.29" + attribute \src "libresoc.v:70932.5-70932.29" switch \initial - attribute \src "libresoc.v:70868.9-70868.17" + attribute \src "libresoc.v:70932.9-70932.17" case 1'1 case end @@ -114434,15 +114485,15 @@ module \dec$171 sync always update \in2_sel $0\in2_sel[3:0] end - attribute \src "libresoc.v:71012.3-71156.6" - process $proc$libresoc.v:71012$3576 + attribute \src "libresoc.v:71076.3-71220.6" + process $proc$libresoc.v:71076$3576 assign { } { } assign { } { } assign { } { } assign $0\in3_sel[1:0] $2\in3_sel[1:0] - attribute \src "libresoc.v:71013.5-71013.29" + attribute \src "libresoc.v:71077.5-71077.29" switch \initial - attribute \src "libresoc.v:71013.9-71013.17" + attribute \src "libresoc.v:71077.9-71077.17" case 1'1 case end @@ -114639,15 +114690,15 @@ module \dec$171 sync always update \in3_sel $0\in3_sel[1:0] end - attribute \src "libresoc.v:71157.3-71301.6" - process $proc$libresoc.v:71157$3577 + attribute \src "libresoc.v:71221.3-71365.6" + process $proc$libresoc.v:71221$3577 assign { } { } assign { } { } assign { } { } assign $0\out_sel[2:0] $2\out_sel[2:0] - attribute \src "libresoc.v:71158.5-71158.29" + attribute \src "libresoc.v:71222.5-71222.29" switch \initial - attribute \src "libresoc.v:71158.9-71158.17" + attribute \src "libresoc.v:71222.9-71222.17" case 1'1 case end @@ -114844,15 +114895,15 @@ module \dec$171 sync always update \out_sel $0\out_sel[2:0] end - attribute \src "libresoc.v:71302.3-71446.6" - process $proc$libresoc.v:71302$3578 + attribute \src "libresoc.v:71366.3-71510.6" + process $proc$libresoc.v:71366$3578 assign { } { } assign { } { } assign { } { } assign $0\cr_in[2:0] $2\cr_in[2:0] - attribute \src "libresoc.v:71303.5-71303.29" + attribute \src "libresoc.v:71367.5-71367.29" switch \initial - attribute \src "libresoc.v:71303.9-71303.17" + attribute \src "libresoc.v:71367.9-71367.17" case 1'1 case end @@ -115049,15 +115100,15 @@ module \dec$171 sync always update \cr_in $0\cr_in[2:0] end - attribute \src "libresoc.v:71447.3-71591.6" - process $proc$libresoc.v:71447$3579 + attribute \src "libresoc.v:71511.3-71655.6" + process $proc$libresoc.v:71511$3579 assign { } { } assign { } { } assign { } { } assign $0\cr_out[2:0] $2\cr_out[2:0] - attribute \src "libresoc.v:71448.5-71448.29" + attribute \src "libresoc.v:71512.5-71512.29" switch \initial - attribute \src "libresoc.v:71448.9-71448.17" + attribute \src "libresoc.v:71512.9-71512.17" case 1'1 case end @@ -115254,15 +115305,15 @@ module \dec$171 sync always update \cr_out $0\cr_out[2:0] end - attribute \src "libresoc.v:71592.3-71736.6" - process $proc$libresoc.v:71592$3580 + attribute \src "libresoc.v:71656.3-71800.6" + process $proc$libresoc.v:71656$3580 assign { } { } assign { } { } assign { } { } assign $0\sv_in1[2:0] $2\sv_in1[2:0] - attribute \src "libresoc.v:71593.5-71593.29" + attribute \src "libresoc.v:71657.5-71657.29" switch \initial - attribute \src "libresoc.v:71593.9-71593.17" + attribute \src "libresoc.v:71657.9-71657.17" case 1'1 case end @@ -115459,15 +115510,15 @@ module \dec$171 sync always update \sv_in1 $0\sv_in1[2:0] end - attribute \src "libresoc.v:71737.3-71881.6" - process $proc$libresoc.v:71737$3581 + attribute \src "libresoc.v:71801.3-71945.6" + process $proc$libresoc.v:71801$3581 assign { } { } assign { } { } assign { } { } assign $0\sv_in2[2:0] $2\sv_in2[2:0] - attribute \src "libresoc.v:71738.5-71738.29" + attribute \src "libresoc.v:71802.5-71802.29" switch \initial - attribute \src "libresoc.v:71738.9-71738.17" + attribute \src "libresoc.v:71802.9-71802.17" case 1'1 case end @@ -115664,15 +115715,15 @@ module \dec$171 sync always update \sv_in2 $0\sv_in2[2:0] end - attribute \src "libresoc.v:71882.3-72026.6" - process $proc$libresoc.v:71882$3582 + attribute \src "libresoc.v:71946.3-72090.6" + process $proc$libresoc.v:71946$3582 assign { } { } assign { } { } assign { } { } assign $0\sv_in3[2:0] $2\sv_in3[2:0] - attribute \src "libresoc.v:71883.5-71883.29" + attribute \src "libresoc.v:71947.5-71947.29" switch \initial - attribute \src "libresoc.v:71883.9-71883.17" + attribute \src "libresoc.v:71947.9-71947.17" case 1'1 case end @@ -115869,15 +115920,15 @@ module \dec$171 sync always update \sv_in3 $0\sv_in3[2:0] end - attribute \src "libresoc.v:72027.3-72171.6" - process $proc$libresoc.v:72027$3583 + attribute \src "libresoc.v:72091.3-72235.6" + process $proc$libresoc.v:72091$3583 assign { } { } assign { } { } assign { } { } assign $0\sv_out[2:0] $2\sv_out[2:0] - attribute \src "libresoc.v:72028.5-72028.29" + attribute \src "libresoc.v:72092.5-72092.29" switch \initial - attribute \src "libresoc.v:72028.9-72028.17" + attribute \src "libresoc.v:72092.9-72092.17" case 1'1 case end @@ -116074,15 +116125,15 @@ module \dec$171 sync always update \sv_out $0\sv_out[2:0] end - attribute \src "libresoc.v:72172.3-72316.6" - process $proc$libresoc.v:72172$3584 + attribute \src "libresoc.v:72236.3-72380.6" + process $proc$libresoc.v:72236$3584 assign { } { } assign { } { } assign { } { } assign $0\sv_out2[2:0] $2\sv_out2[2:0] - attribute \src "libresoc.v:72173.5-72173.29" + attribute \src "libresoc.v:72237.5-72237.29" switch \initial - attribute \src "libresoc.v:72173.9-72173.17" + attribute \src "libresoc.v:72237.9-72237.17" case 1'1 case end @@ -116279,15 +116330,15 @@ module \dec$171 sync always update \sv_out2 $0\sv_out2[2:0] end - attribute \src "libresoc.v:72317.3-72461.6" - process $proc$libresoc.v:72317$3585 + attribute \src "libresoc.v:72381.3-72525.6" + process $proc$libresoc.v:72381$3585 assign { } { } assign { } { } assign { } { } assign $0\sv_cr_in[2:0] $2\sv_cr_in[2:0] - attribute \src "libresoc.v:72318.5-72318.29" + attribute \src "libresoc.v:72382.5-72382.29" switch \initial - attribute \src "libresoc.v:72318.9-72318.17" + attribute \src "libresoc.v:72382.9-72382.17" case 1'1 case end @@ -116484,15 +116535,15 @@ module \dec$171 sync always update \sv_cr_in $0\sv_cr_in[2:0] end - attribute \src "libresoc.v:72462.3-72606.6" - process $proc$libresoc.v:72462$3586 + attribute \src "libresoc.v:72526.3-72670.6" + process $proc$libresoc.v:72526$3586 assign { } { } assign { } { } assign { } { } assign $0\sv_cr_out[2:0] $2\sv_cr_out[2:0] - attribute \src "libresoc.v:72463.5-72463.29" + attribute \src "libresoc.v:72527.5-72527.29" switch \initial - attribute \src "libresoc.v:72463.9-72463.17" + attribute \src "libresoc.v:72527.9-72527.17" case 1'1 case end @@ -116689,15 +116740,15 @@ module \dec$171 sync always update \sv_cr_out $0\sv_cr_out[2:0] end - attribute \src "libresoc.v:72607.3-72751.6" - process $proc$libresoc.v:72607$3587 + attribute \src "libresoc.v:72671.3-72815.6" + process $proc$libresoc.v:72671$3587 assign { } { } assign { } { } assign { } { } assign $0\ldst_len[3:0] $2\ldst_len[3:0] - attribute \src "libresoc.v:72608.5-72608.29" + attribute \src "libresoc.v:72672.5-72672.29" switch \initial - attribute \src "libresoc.v:72608.9-72608.17" + attribute \src "libresoc.v:72672.9-72672.17" case 1'1 case end @@ -116894,15 +116945,15 @@ module \dec$171 sync always update \ldst_len $0\ldst_len[3:0] end - attribute \src "libresoc.v:72752.3-72896.6" - process $proc$libresoc.v:72752$3588 + attribute \src "libresoc.v:72816.3-72960.6" + process $proc$libresoc.v:72816$3588 assign { } { } assign { } { } assign { } { } assign $0\upd[1:0] $2\upd[1:0] - attribute \src "libresoc.v:72753.5-72753.29" + attribute \src "libresoc.v:72817.5-72817.29" switch \initial - attribute \src "libresoc.v:72753.9-72753.17" + attribute \src "libresoc.v:72817.9-72817.17" case 1'1 case end @@ -117099,15 +117150,15 @@ module \dec$171 sync always update \upd $0\upd[1:0] end - attribute \src "libresoc.v:72897.3-73041.6" - process $proc$libresoc.v:72897$3589 + attribute \src "libresoc.v:72961.3-73105.6" + process $proc$libresoc.v:72961$3589 assign { } { } assign { } { } assign { } { } assign $0\rc_sel[1:0] $2\rc_sel[1:0] - attribute \src "libresoc.v:72898.5-72898.29" + attribute \src "libresoc.v:72962.5-72962.29" switch \initial - attribute \src "libresoc.v:72898.9-72898.17" + attribute \src "libresoc.v:72962.9-72962.17" case 1'1 case end @@ -117304,15 +117355,15 @@ module \dec$171 sync always update \rc_sel $0\rc_sel[1:0] end - attribute \src "libresoc.v:73042.3-73186.6" - process $proc$libresoc.v:73042$3590 + attribute \src "libresoc.v:73106.3-73250.6" + process $proc$libresoc.v:73106$3590 assign { } { } assign { } { } assign { } { } assign $0\cry_in[1:0] $2\cry_in[1:0] - attribute \src "libresoc.v:73043.5-73043.29" + attribute \src "libresoc.v:73107.5-73107.29" switch \initial - attribute \src "libresoc.v:73043.9-73043.17" + attribute \src "libresoc.v:73107.9-73107.17" case 1'1 case end @@ -117509,15 +117560,15 @@ module \dec$171 sync always update \cry_in $0\cry_in[1:0] end - attribute \src "libresoc.v:73187.3-73331.6" - process $proc$libresoc.v:73187$3591 + attribute \src "libresoc.v:73251.3-73395.6" + process $proc$libresoc.v:73251$3591 assign { } { } assign { } { } assign { } { } assign $0\inv_a[0:0] $2\inv_a[0:0] - attribute \src "libresoc.v:73188.5-73188.29" + attribute \src "libresoc.v:73252.5-73252.29" switch \initial - attribute \src "libresoc.v:73188.9-73188.17" + attribute \src "libresoc.v:73252.9-73252.17" case 1'1 case end @@ -117714,15 +117765,15 @@ module \dec$171 sync always update \inv_a $0\inv_a[0:0] end - attribute \src "libresoc.v:73332.3-73476.6" - process $proc$libresoc.v:73332$3592 + attribute \src "libresoc.v:73396.3-73540.6" + process $proc$libresoc.v:73396$3592 assign { } { } assign { } { } assign { } { } assign $0\inv_out[0:0] $2\inv_out[0:0] - attribute \src "libresoc.v:73333.5-73333.29" + attribute \src "libresoc.v:73397.5-73397.29" switch \initial - attribute \src "libresoc.v:73333.9-73333.17" + attribute \src "libresoc.v:73397.9-73397.17" case 1'1 case end @@ -117919,15 +117970,15 @@ module \dec$171 sync always update \inv_out $0\inv_out[0:0] end - attribute \src "libresoc.v:73477.3-73621.6" - process $proc$libresoc.v:73477$3593 + attribute \src "libresoc.v:73541.3-73685.6" + process $proc$libresoc.v:73541$3593 assign { } { } assign { } { } assign { } { } assign $0\cry_out[0:0] $2\cry_out[0:0] - attribute \src "libresoc.v:73478.5-73478.29" + attribute \src "libresoc.v:73542.5-73542.29" switch \initial - attribute \src "libresoc.v:73478.9-73478.17" + attribute \src "libresoc.v:73542.9-73542.17" case 1'1 case end @@ -118124,15 +118175,15 @@ module \dec$171 sync always update \cry_out $0\cry_out[0:0] end - attribute \src "libresoc.v:73622.3-73766.6" - process $proc$libresoc.v:73622$3594 + attribute \src "libresoc.v:73686.3-73830.6" + process $proc$libresoc.v:73686$3594 assign { } { } assign { } { } assign { } { } assign $0\br[0:0] $2\br[0:0] - attribute \src "libresoc.v:73623.5-73623.29" + attribute \src "libresoc.v:73687.5-73687.29" switch \initial - attribute \src "libresoc.v:73623.9-73623.17" + attribute \src "libresoc.v:73687.9-73687.17" case 1'1 case end @@ -118329,15 +118380,15 @@ module \dec$171 sync always update \br $0\br[0:0] end - attribute \src "libresoc.v:73767.3-73911.6" - process $proc$libresoc.v:73767$3595 + attribute \src "libresoc.v:73831.3-73975.6" + process $proc$libresoc.v:73831$3595 assign { } { } assign { } { } assign { } { } assign $0\sgn_ext[0:0] $2\sgn_ext[0:0] - attribute \src "libresoc.v:73768.5-73768.29" + attribute \src "libresoc.v:73832.5-73832.29" switch \initial - attribute \src "libresoc.v:73768.9-73768.17" + attribute \src "libresoc.v:73832.9-73832.17" case 1'1 case end @@ -118534,15 +118585,15 @@ module \dec$171 sync always update \sgn_ext $0\sgn_ext[0:0] end - attribute \src "libresoc.v:73912.3-74056.6" - process $proc$libresoc.v:73912$3596 + attribute \src "libresoc.v:73976.3-74120.6" + process $proc$libresoc.v:73976$3596 assign { } { } assign { } { } assign { } { } assign $0\rsrv[0:0] $2\rsrv[0:0] - attribute \src "libresoc.v:73913.5-73913.29" + attribute \src "libresoc.v:73977.5-73977.29" switch \initial - attribute \src "libresoc.v:73913.9-73913.17" + attribute \src "libresoc.v:73977.9-73977.17" case 1'1 case end @@ -118739,15 +118790,15 @@ module \dec$171 sync always update \rsrv $0\rsrv[0:0] end - attribute \src "libresoc.v:74057.3-74201.6" - process $proc$libresoc.v:74057$3597 + attribute \src "libresoc.v:74121.3-74265.6" + process $proc$libresoc.v:74121$3597 assign { } { } assign { } { } assign { } { } assign $0\is_32b[0:0] $2\is_32b[0:0] - attribute \src "libresoc.v:74058.5-74058.29" + attribute \src "libresoc.v:74122.5-74122.29" switch \initial - attribute \src "libresoc.v:74058.9-74058.17" + attribute \src "libresoc.v:74122.9-74122.17" case 1'1 case end @@ -118944,15 +118995,15 @@ module \dec$171 sync always update \is_32b $0\is_32b[0:0] end - attribute \src "libresoc.v:74202.3-74346.6" - process $proc$libresoc.v:74202$3598 + attribute \src "libresoc.v:74266.3-74410.6" + process $proc$libresoc.v:74266$3598 assign { } { } assign { } { } assign { } { } assign $0\sgn[0:0] $2\sgn[0:0] - attribute \src "libresoc.v:74203.5-74203.29" + attribute \src "libresoc.v:74267.5-74267.29" switch \initial - attribute \src "libresoc.v:74203.9-74203.17" + attribute \src "libresoc.v:74267.9-74267.17" case 1'1 case end @@ -119149,15 +119200,15 @@ module \dec$171 sync always update \sgn $0\sgn[0:0] end - attribute \src "libresoc.v:74347.3-74491.6" - process $proc$libresoc.v:74347$3599 + attribute \src "libresoc.v:74411.3-74555.6" + process $proc$libresoc.v:74411$3599 assign { } { } assign { } { } assign { } { } assign $0\lk[0:0] $2\lk[0:0] - attribute \src "libresoc.v:74348.5-74348.29" + attribute \src "libresoc.v:74412.5-74412.29" switch \initial - attribute \src "libresoc.v:74348.9-74348.17" + attribute \src "libresoc.v:74412.9-74412.17" case 1'1 case end @@ -119354,15 +119405,15 @@ module \dec$171 sync always update \lk $0\lk[0:0] end - attribute \src "libresoc.v:74492.3-74636.6" - process $proc$libresoc.v:74492$3600 + attribute \src "libresoc.v:74556.3-74700.6" + process $proc$libresoc.v:74556$3600 assign { } { } assign { } { } assign { } { } assign $0\sgl_pipe[0:0] $2\sgl_pipe[0:0] - attribute \src "libresoc.v:74493.5-74493.29" + attribute \src "libresoc.v:74557.5-74557.29" switch \initial - attribute \src "libresoc.v:74493.9-74493.17" + attribute \src "libresoc.v:74557.9-74557.17" case 1'1 case end @@ -119559,15 +119610,15 @@ module \dec$171 sync always update \sgl_pipe $0\sgl_pipe[0:0] end - attribute \src "libresoc.v:74637.3-74781.6" - process $proc$libresoc.v:74637$3601 + attribute \src "libresoc.v:74701.3-74845.6" + process $proc$libresoc.v:74701$3601 assign { } { } assign { } { } assign { } { } assign $0\function_unit[13:0] $2\function_unit[13:0] - attribute \src "libresoc.v:74638.5-74638.29" + attribute \src "libresoc.v:74702.5-74702.29" switch \initial - attribute \src "libresoc.v:74638.9-74638.17" + attribute \src "libresoc.v:74702.9-74702.17" case 1'1 case end @@ -119764,15 +119815,15 @@ module \dec$171 sync always update \function_unit $0\function_unit[13:0] end - attribute \src "libresoc.v:74782.3-74926.6" - process $proc$libresoc.v:74782$3602 + attribute \src "libresoc.v:74846.3-74990.6" + process $proc$libresoc.v:74846$3602 assign { } { } assign { } { } assign { } { } assign $0\internal_op[6:0] $2\internal_op[6:0] - attribute \src "libresoc.v:74783.5-74783.29" + attribute \src "libresoc.v:74847.5-74847.29" switch \initial - attribute \src "libresoc.v:74783.9-74783.17" + attribute \src "libresoc.v:74847.9-74847.17" case 1'1 case end @@ -119969,7 +120020,7 @@ module \dec$171 sync always update \internal_op $0\internal_op[6:0] end - connect \$2 $ternary$libresoc.v:69928$3569_Y + connect \$2 $ternary$libresoc.v:69989$3569_Y connect \VC_XO \opcode_in [9:0] connect \VC_VRT \opcode_in [25:21] connect \VC_VRB \opcode_in [15:11] @@ -120313,144 +120364,144 @@ module \dec$171 connect \dec19_opcode_in \opcode_in connect \opcode_switch \opcode_in [31:26] end -attribute \src "libresoc.v:75273.1-77339.10" +attribute \src "libresoc.v:75337.1-77403.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec19" attribute \generator "nMigen" module \dec19 - attribute \src "libresoc.v:77026.3-77077.6" + attribute \src "libresoc.v:77090.3-77141.6" wire width 2 $0\dec19_SV_Etype[1:0] - attribute \src "libresoc.v:77078.3-77129.6" + attribute \src "libresoc.v:77142.3-77193.6" wire width 2 $0\dec19_SV_Ptype[1:0] - attribute \src "libresoc.v:76402.3-76453.6" + attribute \src "libresoc.v:76466.3-76517.6" wire width 8 $0\dec19_asmcode[7:0] - attribute \src "libresoc.v:76610.3-76661.6" + attribute \src "libresoc.v:76674.3-76725.6" wire $0\dec19_br[0:0] - attribute \src "libresoc.v:75674.3-75725.6" + attribute \src "libresoc.v:75738.3-75789.6" wire width 3 $0\dec19_cr_in[2:0] - attribute \src "libresoc.v:75726.3-75777.6" + attribute \src "libresoc.v:75790.3-75841.6" wire width 3 $0\dec19_cr_out[2:0] - attribute \src "libresoc.v:76350.3-76401.6" + attribute \src "libresoc.v:76414.3-76465.6" wire width 2 $0\dec19_cry_in[1:0] - attribute \src "libresoc.v:76558.3-76609.6" + attribute \src "libresoc.v:76622.3-76673.6" wire $0\dec19_cry_out[0:0] - attribute \src "libresoc.v:76766.3-76817.6" + attribute \src "libresoc.v:76830.3-76881.6" wire width 5 $0\dec19_form[4:0] - attribute \src "libresoc.v:75622.3-75673.6" + attribute \src "libresoc.v:75686.3-75737.6" wire width 14 $0\dec19_function_unit[13:0] - attribute \src "libresoc.v:77130.3-77181.6" + attribute \src "libresoc.v:77194.3-77245.6" wire width 3 $0\dec19_in1_sel[2:0] - attribute \src "libresoc.v:77182.3-77233.6" + attribute \src "libresoc.v:77246.3-77297.6" wire width 4 $0\dec19_in2_sel[3:0] - attribute \src "libresoc.v:77234.3-77285.6" + attribute \src "libresoc.v:77298.3-77349.6" wire width 2 $0\dec19_in3_sel[1:0] - attribute \src "libresoc.v:76194.3-76245.6" + attribute \src "libresoc.v:76258.3-76309.6" wire width 7 $0\dec19_internal_op[6:0] - attribute \src "libresoc.v:76454.3-76505.6" + attribute \src "libresoc.v:76518.3-76569.6" wire $0\dec19_inv_a[0:0] - attribute \src "libresoc.v:76506.3-76557.6" + attribute \src "libresoc.v:76570.3-76621.6" wire $0\dec19_inv_out[0:0] - attribute \src "libresoc.v:76818.3-76869.6" + attribute \src "libresoc.v:76882.3-76933.6" wire $0\dec19_is_32b[0:0] - attribute \src "libresoc.v:76142.3-76193.6" + attribute \src "libresoc.v:76206.3-76257.6" wire width 4 $0\dec19_ldst_len[3:0] - attribute \src "libresoc.v:76922.3-76973.6" + attribute \src "libresoc.v:76986.3-77037.6" wire $0\dec19_lk[0:0] - attribute \src "libresoc.v:77286.3-77337.6" + attribute \src "libresoc.v:77350.3-77401.6" wire width 3 $0\dec19_out_sel[2:0] - attribute \src "libresoc.v:76298.3-76349.6" + attribute \src "libresoc.v:76362.3-76413.6" wire width 2 $0\dec19_rc_sel[1:0] - attribute \src "libresoc.v:76714.3-76765.6" + attribute \src "libresoc.v:76778.3-76829.6" wire $0\dec19_rsrv[0:0] - attribute \src "libresoc.v:76974.3-77025.6" + attribute \src "libresoc.v:77038.3-77089.6" wire $0\dec19_sgl_pipe[0:0] - attribute \src "libresoc.v:76870.3-76921.6" + attribute \src "libresoc.v:76934.3-76985.6" wire $0\dec19_sgn[0:0] - attribute \src "libresoc.v:76662.3-76713.6" + attribute \src "libresoc.v:76726.3-76777.6" wire $0\dec19_sgn_ext[0:0] - attribute \src "libresoc.v:76038.3-76089.6" + attribute \src "libresoc.v:76102.3-76153.6" wire width 3 $0\dec19_sv_cr_in[2:0] - attribute \src "libresoc.v:76090.3-76141.6" + attribute \src "libresoc.v:76154.3-76205.6" wire width 3 $0\dec19_sv_cr_out[2:0] - attribute \src "libresoc.v:75778.3-75829.6" + attribute \src "libresoc.v:75842.3-75893.6" wire width 3 $0\dec19_sv_in1[2:0] - attribute \src "libresoc.v:75830.3-75881.6" + attribute \src "libresoc.v:75894.3-75945.6" wire width 3 $0\dec19_sv_in2[2:0] - attribute \src "libresoc.v:75882.3-75933.6" + attribute \src "libresoc.v:75946.3-75997.6" wire width 3 $0\dec19_sv_in3[2:0] - attribute \src "libresoc.v:75986.3-76037.6" + attribute \src "libresoc.v:76050.3-76101.6" wire width 3 $0\dec19_sv_out2[2:0] - attribute \src "libresoc.v:75934.3-75985.6" + attribute \src "libresoc.v:75998.3-76049.6" wire width 3 $0\dec19_sv_out[2:0] - attribute \src "libresoc.v:76246.3-76297.6" + attribute \src "libresoc.v:76310.3-76361.6" wire width 2 $0\dec19_upd[1:0] - attribute \src "libresoc.v:75274.7-75274.20" + attribute \src "libresoc.v:75338.7-75338.20" wire $0\initial[0:0] - attribute \src "libresoc.v:77026.3-77077.6" + attribute \src "libresoc.v:77090.3-77141.6" wire width 2 $1\dec19_SV_Etype[1:0] - attribute \src "libresoc.v:77078.3-77129.6" + attribute \src "libresoc.v:77142.3-77193.6" wire width 2 $1\dec19_SV_Ptype[1:0] - attribute \src "libresoc.v:76402.3-76453.6" + attribute \src "libresoc.v:76466.3-76517.6" wire width 8 $1\dec19_asmcode[7:0] - attribute \src "libresoc.v:76610.3-76661.6" + attribute \src "libresoc.v:76674.3-76725.6" wire $1\dec19_br[0:0] - attribute \src "libresoc.v:75674.3-75725.6" + attribute \src "libresoc.v:75738.3-75789.6" wire width 3 $1\dec19_cr_in[2:0] - attribute \src "libresoc.v:75726.3-75777.6" + attribute \src "libresoc.v:75790.3-75841.6" wire width 3 $1\dec19_cr_out[2:0] - attribute \src "libresoc.v:76350.3-76401.6" + attribute \src "libresoc.v:76414.3-76465.6" wire width 2 $1\dec19_cry_in[1:0] - attribute \src "libresoc.v:76558.3-76609.6" + attribute \src "libresoc.v:76622.3-76673.6" wire $1\dec19_cry_out[0:0] - attribute \src "libresoc.v:76766.3-76817.6" + attribute \src "libresoc.v:76830.3-76881.6" wire width 5 $1\dec19_form[4:0] - attribute \src "libresoc.v:75622.3-75673.6" + attribute \src "libresoc.v:75686.3-75737.6" wire width 14 $1\dec19_function_unit[13:0] - attribute \src "libresoc.v:77130.3-77181.6" + attribute \src "libresoc.v:77194.3-77245.6" wire width 3 $1\dec19_in1_sel[2:0] - attribute \src "libresoc.v:77182.3-77233.6" + attribute \src "libresoc.v:77246.3-77297.6" wire width 4 $1\dec19_in2_sel[3:0] - attribute \src "libresoc.v:77234.3-77285.6" + attribute \src "libresoc.v:77298.3-77349.6" wire width 2 $1\dec19_in3_sel[1:0] - attribute \src "libresoc.v:76194.3-76245.6" + attribute \src "libresoc.v:76258.3-76309.6" wire width 7 $1\dec19_internal_op[6:0] - attribute \src "libresoc.v:76454.3-76505.6" + attribute \src "libresoc.v:76518.3-76569.6" wire $1\dec19_inv_a[0:0] - attribute \src "libresoc.v:76506.3-76557.6" + attribute \src "libresoc.v:76570.3-76621.6" wire $1\dec19_inv_out[0:0] - attribute \src "libresoc.v:76818.3-76869.6" + attribute \src "libresoc.v:76882.3-76933.6" wire $1\dec19_is_32b[0:0] - attribute \src "libresoc.v:76142.3-76193.6" + attribute \src "libresoc.v:76206.3-76257.6" wire width 4 $1\dec19_ldst_len[3:0] - attribute \src "libresoc.v:76922.3-76973.6" + attribute \src "libresoc.v:76986.3-77037.6" wire $1\dec19_lk[0:0] - attribute \src "libresoc.v:77286.3-77337.6" + attribute \src "libresoc.v:77350.3-77401.6" wire width 3 $1\dec19_out_sel[2:0] - attribute \src "libresoc.v:76298.3-76349.6" + attribute \src "libresoc.v:76362.3-76413.6" wire width 2 $1\dec19_rc_sel[1:0] - attribute \src "libresoc.v:76714.3-76765.6" + attribute \src "libresoc.v:76778.3-76829.6" wire $1\dec19_rsrv[0:0] - attribute \src "libresoc.v:76974.3-77025.6" + attribute \src "libresoc.v:77038.3-77089.6" wire $1\dec19_sgl_pipe[0:0] - attribute \src "libresoc.v:76870.3-76921.6" + attribute \src "libresoc.v:76934.3-76985.6" wire $1\dec19_sgn[0:0] - attribute \src "libresoc.v:76662.3-76713.6" + attribute \src "libresoc.v:76726.3-76777.6" wire $1\dec19_sgn_ext[0:0] - attribute \src "libresoc.v:76038.3-76089.6" + attribute \src "libresoc.v:76102.3-76153.6" wire width 3 $1\dec19_sv_cr_in[2:0] - attribute \src "libresoc.v:76090.3-76141.6" + attribute \src "libresoc.v:76154.3-76205.6" wire width 3 $1\dec19_sv_cr_out[2:0] - attribute \src "libresoc.v:75778.3-75829.6" + attribute \src "libresoc.v:75842.3-75893.6" wire width 3 $1\dec19_sv_in1[2:0] - attribute \src "libresoc.v:75830.3-75881.6" + attribute \src "libresoc.v:75894.3-75945.6" wire width 3 $1\dec19_sv_in2[2:0] - attribute \src "libresoc.v:75882.3-75933.6" + attribute \src "libresoc.v:75946.3-75997.6" wire width 3 $1\dec19_sv_in3[2:0] - attribute \src "libresoc.v:75986.3-76037.6" + attribute \src "libresoc.v:76050.3-76101.6" wire width 3 $1\dec19_sv_out2[2:0] - attribute \src "libresoc.v:75934.3-75985.6" + attribute \src "libresoc.v:75998.3-76049.6" wire width 3 $1\dec19_sv_out[2:0] - attribute \src "libresoc.v:76246.3-76297.6" + attribute \src "libresoc.v:76310.3-76361.6" wire width 2 $1\dec19_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -120762,28 +120813,28 @@ module \dec19 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec19_upd - attribute \src "libresoc.v:75274.7-75274.15" + attribute \src "libresoc.v:75338.7-75338.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch - attribute \src "libresoc.v:75274.7-75274.20" - process $proc$libresoc.v:75274$3637 + attribute \src "libresoc.v:75338.7-75338.20" + process $proc$libresoc.v:75338$3637 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:75622.3-75673.6" - process $proc$libresoc.v:75622$3604 + attribute \src "libresoc.v:75686.3-75737.6" + process $proc$libresoc.v:75686$3604 assign { } { } assign { } { } assign $0\dec19_function_unit[13:0] $1\dec19_function_unit[13:0] - attribute \src "libresoc.v:75623.5-75623.29" + attribute \src "libresoc.v:75687.5-75687.29" switch \initial - attribute \src "libresoc.v:75623.9-75623.17" + attribute \src "libresoc.v:75687.9-75687.17" case 1'1 case end @@ -120855,14 +120906,14 @@ module \dec19 sync always update \dec19_function_unit $0\dec19_function_unit[13:0] end - attribute \src "libresoc.v:75674.3-75725.6" - process $proc$libresoc.v:75674$3605 + attribute \src "libresoc.v:75738.3-75789.6" + process $proc$libresoc.v:75738$3605 assign { } { } assign { } { } assign $0\dec19_cr_in[2:0] $1\dec19_cr_in[2:0] - attribute \src "libresoc.v:75675.5-75675.29" + attribute \src "libresoc.v:75739.5-75739.29" switch \initial - attribute \src "libresoc.v:75675.9-75675.17" + attribute \src "libresoc.v:75739.9-75739.17" case 1'1 case end @@ -120934,14 +120985,14 @@ module \dec19 sync always update \dec19_cr_in $0\dec19_cr_in[2:0] end - attribute \src "libresoc.v:75726.3-75777.6" - process $proc$libresoc.v:75726$3606 + attribute \src "libresoc.v:75790.3-75841.6" + process $proc$libresoc.v:75790$3606 assign { } { } assign { } { } assign $0\dec19_cr_out[2:0] $1\dec19_cr_out[2:0] - attribute \src "libresoc.v:75727.5-75727.29" + attribute \src "libresoc.v:75791.5-75791.29" switch \initial - attribute \src "libresoc.v:75727.9-75727.17" + attribute \src "libresoc.v:75791.9-75791.17" case 1'1 case end @@ -121013,14 +121064,14 @@ module \dec19 sync always update \dec19_cr_out $0\dec19_cr_out[2:0] end - attribute \src "libresoc.v:75778.3-75829.6" - process $proc$libresoc.v:75778$3607 + attribute \src "libresoc.v:75842.3-75893.6" + process $proc$libresoc.v:75842$3607 assign { } { } assign { } { } assign $0\dec19_sv_in1[2:0] $1\dec19_sv_in1[2:0] - attribute \src "libresoc.v:75779.5-75779.29" + attribute \src "libresoc.v:75843.5-75843.29" switch \initial - attribute \src "libresoc.v:75779.9-75779.17" + attribute \src "libresoc.v:75843.9-75843.17" case 1'1 case end @@ -121092,14 +121143,14 @@ module \dec19 sync always update \dec19_sv_in1 $0\dec19_sv_in1[2:0] end - attribute \src "libresoc.v:75830.3-75881.6" - process $proc$libresoc.v:75830$3608 + attribute \src "libresoc.v:75894.3-75945.6" + process $proc$libresoc.v:75894$3608 assign { } { } assign { } { } assign $0\dec19_sv_in2[2:0] $1\dec19_sv_in2[2:0] - attribute \src "libresoc.v:75831.5-75831.29" + attribute \src "libresoc.v:75895.5-75895.29" switch \initial - attribute \src "libresoc.v:75831.9-75831.17" + attribute \src "libresoc.v:75895.9-75895.17" case 1'1 case end @@ -121171,14 +121222,14 @@ module \dec19 sync always update \dec19_sv_in2 $0\dec19_sv_in2[2:0] end - attribute \src "libresoc.v:75882.3-75933.6" - process $proc$libresoc.v:75882$3609 + attribute \src "libresoc.v:75946.3-75997.6" + process $proc$libresoc.v:75946$3609 assign { } { } assign { } { } assign $0\dec19_sv_in3[2:0] $1\dec19_sv_in3[2:0] - attribute \src "libresoc.v:75883.5-75883.29" + attribute \src "libresoc.v:75947.5-75947.29" switch \initial - attribute \src "libresoc.v:75883.9-75883.17" + attribute \src "libresoc.v:75947.9-75947.17" case 1'1 case end @@ -121250,14 +121301,14 @@ module \dec19 sync always update \dec19_sv_in3 $0\dec19_sv_in3[2:0] end - attribute \src "libresoc.v:75934.3-75985.6" - process $proc$libresoc.v:75934$3610 + attribute \src "libresoc.v:75998.3-76049.6" + process $proc$libresoc.v:75998$3610 assign { } { } assign { } { } assign $0\dec19_sv_out[2:0] $1\dec19_sv_out[2:0] - attribute \src "libresoc.v:75935.5-75935.29" + attribute \src "libresoc.v:75999.5-75999.29" switch \initial - attribute \src "libresoc.v:75935.9-75935.17" + attribute \src "libresoc.v:75999.9-75999.17" case 1'1 case end @@ -121329,14 +121380,14 @@ module \dec19 sync always update \dec19_sv_out $0\dec19_sv_out[2:0] end - attribute \src "libresoc.v:75986.3-76037.6" - process $proc$libresoc.v:75986$3611 + attribute \src "libresoc.v:76050.3-76101.6" + process $proc$libresoc.v:76050$3611 assign { } { } assign { } { } assign $0\dec19_sv_out2[2:0] $1\dec19_sv_out2[2:0] - attribute \src "libresoc.v:75987.5-75987.29" + attribute \src "libresoc.v:76051.5-76051.29" switch \initial - attribute \src "libresoc.v:75987.9-75987.17" + attribute \src "libresoc.v:76051.9-76051.17" case 1'1 case end @@ -121408,14 +121459,14 @@ module \dec19 sync always update \dec19_sv_out2 $0\dec19_sv_out2[2:0] end - attribute \src "libresoc.v:76038.3-76089.6" - process $proc$libresoc.v:76038$3612 + attribute \src "libresoc.v:76102.3-76153.6" + process $proc$libresoc.v:76102$3612 assign { } { } assign { } { } assign $0\dec19_sv_cr_in[2:0] $1\dec19_sv_cr_in[2:0] - attribute \src "libresoc.v:76039.5-76039.29" + attribute \src "libresoc.v:76103.5-76103.29" switch \initial - attribute \src "libresoc.v:76039.9-76039.17" + attribute \src "libresoc.v:76103.9-76103.17" case 1'1 case end @@ -121487,14 +121538,14 @@ module \dec19 sync always update \dec19_sv_cr_in $0\dec19_sv_cr_in[2:0] end - attribute \src "libresoc.v:76090.3-76141.6" - process $proc$libresoc.v:76090$3613 + attribute \src "libresoc.v:76154.3-76205.6" + process $proc$libresoc.v:76154$3613 assign { } { } assign { } { } assign $0\dec19_sv_cr_out[2:0] $1\dec19_sv_cr_out[2:0] - attribute \src "libresoc.v:76091.5-76091.29" + attribute \src "libresoc.v:76155.5-76155.29" switch \initial - attribute \src "libresoc.v:76091.9-76091.17" + attribute \src "libresoc.v:76155.9-76155.17" case 1'1 case end @@ -121566,14 +121617,14 @@ module \dec19 sync always update \dec19_sv_cr_out $0\dec19_sv_cr_out[2:0] end - attribute \src "libresoc.v:76142.3-76193.6" - process $proc$libresoc.v:76142$3614 + attribute \src "libresoc.v:76206.3-76257.6" + process $proc$libresoc.v:76206$3614 assign { } { } assign { } { } assign $0\dec19_ldst_len[3:0] $1\dec19_ldst_len[3:0] - attribute \src "libresoc.v:76143.5-76143.29" + attribute \src "libresoc.v:76207.5-76207.29" switch \initial - attribute \src "libresoc.v:76143.9-76143.17" + attribute \src "libresoc.v:76207.9-76207.17" case 1'1 case end @@ -121645,14 +121696,14 @@ module \dec19 sync always update \dec19_ldst_len $0\dec19_ldst_len[3:0] end - attribute \src "libresoc.v:76194.3-76245.6" - process $proc$libresoc.v:76194$3615 + attribute \src "libresoc.v:76258.3-76309.6" + process $proc$libresoc.v:76258$3615 assign { } { } assign { } { } assign $0\dec19_internal_op[6:0] $1\dec19_internal_op[6:0] - attribute \src "libresoc.v:76195.5-76195.29" + attribute \src "libresoc.v:76259.5-76259.29" switch \initial - attribute \src "libresoc.v:76195.9-76195.17" + attribute \src "libresoc.v:76259.9-76259.17" case 1'1 case end @@ -121724,14 +121775,14 @@ module \dec19 sync always update \dec19_internal_op $0\dec19_internal_op[6:0] end - attribute \src "libresoc.v:76246.3-76297.6" - process $proc$libresoc.v:76246$3616 + attribute \src "libresoc.v:76310.3-76361.6" + process $proc$libresoc.v:76310$3616 assign { } { } assign { } { } assign $0\dec19_upd[1:0] $1\dec19_upd[1:0] - attribute \src "libresoc.v:76247.5-76247.29" + attribute \src "libresoc.v:76311.5-76311.29" switch \initial - attribute \src "libresoc.v:76247.9-76247.17" + attribute \src "libresoc.v:76311.9-76311.17" case 1'1 case end @@ -121803,14 +121854,14 @@ module \dec19 sync always update \dec19_upd $0\dec19_upd[1:0] end - attribute \src "libresoc.v:76298.3-76349.6" - process $proc$libresoc.v:76298$3617 + attribute \src "libresoc.v:76362.3-76413.6" + process $proc$libresoc.v:76362$3617 assign { } { } assign { } { } assign $0\dec19_rc_sel[1:0] $1\dec19_rc_sel[1:0] - attribute \src "libresoc.v:76299.5-76299.29" + attribute \src "libresoc.v:76363.5-76363.29" switch \initial - attribute \src "libresoc.v:76299.9-76299.17" + attribute \src "libresoc.v:76363.9-76363.17" case 1'1 case end @@ -121882,14 +121933,14 @@ module \dec19 sync always update \dec19_rc_sel $0\dec19_rc_sel[1:0] end - attribute \src "libresoc.v:76350.3-76401.6" - process $proc$libresoc.v:76350$3618 + attribute \src "libresoc.v:76414.3-76465.6" + process $proc$libresoc.v:76414$3618 assign { } { } assign { } { } assign $0\dec19_cry_in[1:0] $1\dec19_cry_in[1:0] - attribute \src "libresoc.v:76351.5-76351.29" + attribute \src "libresoc.v:76415.5-76415.29" switch \initial - attribute \src "libresoc.v:76351.9-76351.17" + attribute \src "libresoc.v:76415.9-76415.17" case 1'1 case end @@ -121961,14 +122012,14 @@ module \dec19 sync always update \dec19_cry_in $0\dec19_cry_in[1:0] end - attribute \src "libresoc.v:76402.3-76453.6" - process $proc$libresoc.v:76402$3619 + attribute \src "libresoc.v:76466.3-76517.6" + process $proc$libresoc.v:76466$3619 assign { } { } assign { } { } assign $0\dec19_asmcode[7:0] $1\dec19_asmcode[7:0] - attribute \src "libresoc.v:76403.5-76403.29" + attribute \src "libresoc.v:76467.5-76467.29" switch \initial - attribute \src "libresoc.v:76403.9-76403.17" + attribute \src "libresoc.v:76467.9-76467.17" case 1'1 case end @@ -122040,14 +122091,14 @@ module \dec19 sync always update \dec19_asmcode $0\dec19_asmcode[7:0] end - attribute \src "libresoc.v:76454.3-76505.6" - process $proc$libresoc.v:76454$3620 + attribute \src "libresoc.v:76518.3-76569.6" + process $proc$libresoc.v:76518$3620 assign { } { } assign { } { } assign $0\dec19_inv_a[0:0] $1\dec19_inv_a[0:0] - attribute \src "libresoc.v:76455.5-76455.29" + attribute \src "libresoc.v:76519.5-76519.29" switch \initial - attribute \src "libresoc.v:76455.9-76455.17" + attribute \src "libresoc.v:76519.9-76519.17" case 1'1 case end @@ -122119,14 +122170,14 @@ module \dec19 sync always update \dec19_inv_a $0\dec19_inv_a[0:0] end - attribute \src "libresoc.v:76506.3-76557.6" - process $proc$libresoc.v:76506$3621 + attribute \src "libresoc.v:76570.3-76621.6" + process $proc$libresoc.v:76570$3621 assign { } { } assign { } { } assign $0\dec19_inv_out[0:0] $1\dec19_inv_out[0:0] - attribute \src "libresoc.v:76507.5-76507.29" + attribute \src "libresoc.v:76571.5-76571.29" switch \initial - attribute \src "libresoc.v:76507.9-76507.17" + attribute \src "libresoc.v:76571.9-76571.17" case 1'1 case end @@ -122198,14 +122249,14 @@ module \dec19 sync always update \dec19_inv_out $0\dec19_inv_out[0:0] end - attribute \src "libresoc.v:76558.3-76609.6" - process $proc$libresoc.v:76558$3622 + attribute \src "libresoc.v:76622.3-76673.6" + process $proc$libresoc.v:76622$3622 assign { } { } assign { } { } assign $0\dec19_cry_out[0:0] $1\dec19_cry_out[0:0] - attribute \src "libresoc.v:76559.5-76559.29" + attribute \src "libresoc.v:76623.5-76623.29" switch \initial - attribute \src "libresoc.v:76559.9-76559.17" + attribute \src "libresoc.v:76623.9-76623.17" case 1'1 case end @@ -122277,14 +122328,14 @@ module \dec19 sync always update \dec19_cry_out $0\dec19_cry_out[0:0] end - attribute \src "libresoc.v:76610.3-76661.6" - process $proc$libresoc.v:76610$3623 + attribute \src "libresoc.v:76674.3-76725.6" + process $proc$libresoc.v:76674$3623 assign { } { } assign { } { } assign $0\dec19_br[0:0] $1\dec19_br[0:0] - attribute \src "libresoc.v:76611.5-76611.29" + attribute \src "libresoc.v:76675.5-76675.29" switch \initial - attribute \src "libresoc.v:76611.9-76611.17" + attribute \src "libresoc.v:76675.9-76675.17" case 1'1 case end @@ -122356,14 +122407,14 @@ module \dec19 sync always update \dec19_br $0\dec19_br[0:0] end - attribute \src "libresoc.v:76662.3-76713.6" - process $proc$libresoc.v:76662$3624 + attribute \src "libresoc.v:76726.3-76777.6" + process $proc$libresoc.v:76726$3624 assign { } { } assign { } { } assign $0\dec19_sgn_ext[0:0] $1\dec19_sgn_ext[0:0] - attribute \src "libresoc.v:76663.5-76663.29" + attribute \src "libresoc.v:76727.5-76727.29" switch \initial - attribute \src "libresoc.v:76663.9-76663.17" + attribute \src "libresoc.v:76727.9-76727.17" case 1'1 case end @@ -122435,14 +122486,14 @@ module \dec19 sync always update \dec19_sgn_ext $0\dec19_sgn_ext[0:0] end - attribute \src "libresoc.v:76714.3-76765.6" - process $proc$libresoc.v:76714$3625 + attribute \src "libresoc.v:76778.3-76829.6" + process $proc$libresoc.v:76778$3625 assign { } { } assign { } { } assign $0\dec19_rsrv[0:0] $1\dec19_rsrv[0:0] - attribute \src "libresoc.v:76715.5-76715.29" + attribute \src "libresoc.v:76779.5-76779.29" switch \initial - attribute \src "libresoc.v:76715.9-76715.17" + attribute \src "libresoc.v:76779.9-76779.17" case 1'1 case end @@ -122514,14 +122565,14 @@ module \dec19 sync always update \dec19_rsrv $0\dec19_rsrv[0:0] end - attribute \src "libresoc.v:76766.3-76817.6" - process $proc$libresoc.v:76766$3626 + attribute \src "libresoc.v:76830.3-76881.6" + process $proc$libresoc.v:76830$3626 assign { } { } assign { } { } assign $0\dec19_form[4:0] $1\dec19_form[4:0] - attribute \src "libresoc.v:76767.5-76767.29" + attribute \src "libresoc.v:76831.5-76831.29" switch \initial - attribute \src "libresoc.v:76767.9-76767.17" + attribute \src "libresoc.v:76831.9-76831.17" case 1'1 case end @@ -122593,14 +122644,14 @@ module \dec19 sync always update \dec19_form $0\dec19_form[4:0] end - attribute \src "libresoc.v:76818.3-76869.6" - process $proc$libresoc.v:76818$3627 + attribute \src "libresoc.v:76882.3-76933.6" + process $proc$libresoc.v:76882$3627 assign { } { } assign { } { } assign $0\dec19_is_32b[0:0] $1\dec19_is_32b[0:0] - attribute \src "libresoc.v:76819.5-76819.29" + attribute \src "libresoc.v:76883.5-76883.29" switch \initial - attribute \src "libresoc.v:76819.9-76819.17" + attribute \src "libresoc.v:76883.9-76883.17" case 1'1 case end @@ -122672,14 +122723,14 @@ module \dec19 sync always update \dec19_is_32b $0\dec19_is_32b[0:0] end - attribute \src "libresoc.v:76870.3-76921.6" - process $proc$libresoc.v:76870$3628 + attribute \src "libresoc.v:76934.3-76985.6" + process $proc$libresoc.v:76934$3628 assign { } { } assign { } { } assign $0\dec19_sgn[0:0] $1\dec19_sgn[0:0] - attribute \src "libresoc.v:76871.5-76871.29" + attribute \src "libresoc.v:76935.5-76935.29" switch \initial - attribute \src "libresoc.v:76871.9-76871.17" + attribute \src "libresoc.v:76935.9-76935.17" case 1'1 case end @@ -122751,14 +122802,14 @@ module \dec19 sync always update \dec19_sgn $0\dec19_sgn[0:0] end - attribute \src "libresoc.v:76922.3-76973.6" - process $proc$libresoc.v:76922$3629 + attribute \src "libresoc.v:76986.3-77037.6" + process $proc$libresoc.v:76986$3629 assign { } { } assign { } { } assign $0\dec19_lk[0:0] $1\dec19_lk[0:0] - attribute \src "libresoc.v:76923.5-76923.29" + attribute \src "libresoc.v:76987.5-76987.29" switch \initial - attribute \src "libresoc.v:76923.9-76923.17" + attribute \src "libresoc.v:76987.9-76987.17" case 1'1 case end @@ -122830,14 +122881,14 @@ module \dec19 sync always update \dec19_lk $0\dec19_lk[0:0] end - attribute \src "libresoc.v:76974.3-77025.6" - process $proc$libresoc.v:76974$3630 + attribute \src "libresoc.v:77038.3-77089.6" + process $proc$libresoc.v:77038$3630 assign { } { } assign { } { } assign $0\dec19_sgl_pipe[0:0] $1\dec19_sgl_pipe[0:0] - attribute \src "libresoc.v:76975.5-76975.29" + attribute \src "libresoc.v:77039.5-77039.29" switch \initial - attribute \src "libresoc.v:76975.9-76975.17" + attribute \src "libresoc.v:77039.9-77039.17" case 1'1 case end @@ -122909,14 +122960,14 @@ module \dec19 sync always update \dec19_sgl_pipe $0\dec19_sgl_pipe[0:0] end - attribute \src "libresoc.v:77026.3-77077.6" - process $proc$libresoc.v:77026$3631 + attribute \src "libresoc.v:77090.3-77141.6" + process $proc$libresoc.v:77090$3631 assign { } { } assign { } { } assign $0\dec19_SV_Etype[1:0] $1\dec19_SV_Etype[1:0] - attribute \src "libresoc.v:77027.5-77027.29" + attribute \src "libresoc.v:77091.5-77091.29" switch \initial - attribute \src "libresoc.v:77027.9-77027.17" + attribute \src "libresoc.v:77091.9-77091.17" case 1'1 case end @@ -122988,14 +123039,14 @@ module \dec19 sync always update \dec19_SV_Etype $0\dec19_SV_Etype[1:0] end - attribute \src "libresoc.v:77078.3-77129.6" - process $proc$libresoc.v:77078$3632 + attribute \src "libresoc.v:77142.3-77193.6" + process $proc$libresoc.v:77142$3632 assign { } { } assign { } { } assign $0\dec19_SV_Ptype[1:0] $1\dec19_SV_Ptype[1:0] - attribute \src "libresoc.v:77079.5-77079.29" + attribute \src "libresoc.v:77143.5-77143.29" switch \initial - attribute \src "libresoc.v:77079.9-77079.17" + attribute \src "libresoc.v:77143.9-77143.17" case 1'1 case end @@ -123067,14 +123118,14 @@ module \dec19 sync always update \dec19_SV_Ptype $0\dec19_SV_Ptype[1:0] end - attribute \src "libresoc.v:77130.3-77181.6" - process $proc$libresoc.v:77130$3633 + attribute \src "libresoc.v:77194.3-77245.6" + process $proc$libresoc.v:77194$3633 assign { } { } assign { } { } assign $0\dec19_in1_sel[2:0] $1\dec19_in1_sel[2:0] - attribute \src "libresoc.v:77131.5-77131.29" + attribute \src "libresoc.v:77195.5-77195.29" switch \initial - attribute \src "libresoc.v:77131.9-77131.17" + attribute \src "libresoc.v:77195.9-77195.17" case 1'1 case end @@ -123146,14 +123197,14 @@ module \dec19 sync always update \dec19_in1_sel $0\dec19_in1_sel[2:0] end - attribute \src "libresoc.v:77182.3-77233.6" - process $proc$libresoc.v:77182$3634 + attribute \src "libresoc.v:77246.3-77297.6" + process $proc$libresoc.v:77246$3634 assign { } { } assign { } { } assign $0\dec19_in2_sel[3:0] $1\dec19_in2_sel[3:0] - attribute \src "libresoc.v:77183.5-77183.29" + attribute \src "libresoc.v:77247.5-77247.29" switch \initial - attribute \src "libresoc.v:77183.9-77183.17" + attribute \src "libresoc.v:77247.9-77247.17" case 1'1 case end @@ -123225,14 +123276,14 @@ module \dec19 sync always update \dec19_in2_sel $0\dec19_in2_sel[3:0] end - attribute \src "libresoc.v:77234.3-77285.6" - process $proc$libresoc.v:77234$3635 + attribute \src "libresoc.v:77298.3-77349.6" + process $proc$libresoc.v:77298$3635 assign { } { } assign { } { } assign $0\dec19_in3_sel[1:0] $1\dec19_in3_sel[1:0] - attribute \src "libresoc.v:77235.5-77235.29" + attribute \src "libresoc.v:77299.5-77299.29" switch \initial - attribute \src "libresoc.v:77235.9-77235.17" + attribute \src "libresoc.v:77299.9-77299.17" case 1'1 case end @@ -123304,14 +123355,14 @@ module \dec19 sync always update \dec19_in3_sel $0\dec19_in3_sel[1:0] end - attribute \src "libresoc.v:77286.3-77337.6" - process $proc$libresoc.v:77286$3636 + attribute \src "libresoc.v:77350.3-77401.6" + process $proc$libresoc.v:77350$3636 assign { } { } assign { } { } assign $0\dec19_out_sel[2:0] $1\dec19_out_sel[2:0] - attribute \src "libresoc.v:77287.5-77287.29" + attribute \src "libresoc.v:77351.5-77351.29" switch \initial - attribute \src "libresoc.v:77287.9-77287.17" + attribute \src "libresoc.v:77351.9-77351.17" case 1'1 case end @@ -123385,755 +123436,755 @@ module \dec19 end connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:77343.1-79564.10" +attribute \src "libresoc.v:77407.1-79628.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2" attribute \generator "nMigen" module \dec2 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 8 $0\asmcode[7:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 64 $0\cia[63:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $0\cr_in1[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $0\cr_in1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $0\cr_in2$1[6:0]$3698 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $0\cr_in2[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $0\cr_in2_ok$2[0:0]$3699 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $0\cr_in2_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $0\cr_out[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $0\cr_out_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 8 $0\cr_rd[7:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $0\cr_rd_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 8 $0\cr_wr[7:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $0\cr_wr_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $0\ea[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $0\ea_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $0\exc_$signal$3[0:0]$3701 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $0\exc_$signal$4[0:0]$3702 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $0\exc_$signal$5[0:0]$3703 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $0\exc_$signal$6[0:0]$3704 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $0\exc_$signal$7[0:0]$3705 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $0\exc_$signal$8[0:0]$3706 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $0\exc_$signal$9[0:0]$3707 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $0\exc_$signal[0:0]$3700 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 3 $0\fast1[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 3 $0\fast2[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 3 $0\fasto1[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $0\fasto1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 3 $0\fasto2[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $0\fasto2_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 14 $0\fn_unit[13:0] - attribute \src "libresoc.v:77344.7-77344.20" + attribute \src "libresoc.v:77408.7-77408.20" wire $0\initial[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 2 $0\input_carry[1:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 32 $0\insn[31:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $0\insn_type[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $0\is_32bit[0:0] - attribute \src "libresoc.v:79303.3-79326.6" + attribute \src "libresoc.v:79367.3-79390.6" wire $0\is_priv_insn[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $0\lk[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 64 $0\msr[63:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $0\oe[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $0\rc[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $0\reg1[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $0\reg1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $0\reg2[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $0\reg2_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $0\reg3[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $0\reg3_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $0\rego[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $0\rego_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 10 $0\spr1[9:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $0\spr1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 10 $0\spro[9:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $0\spro_ok[0:0] - attribute \src "libresoc.v:79229.3-79243.6" + attribute \src "libresoc.v:79293.3-79307.6" wire width 14 $0\tmp_tmp_fn_unit[13:0] - attribute \src "libresoc.v:79254.3-79266.6" + attribute \src "libresoc.v:79318.3-79330.6" wire width 7 $0\tmp_tmp_insn_type[6:0] - attribute \src "libresoc.v:79244.3-79253.6" + attribute \src "libresoc.v:79308.3-79317.6" wire $0\tmp_tmp_lk[0:0] - attribute \src "libresoc.v:79293.3-79302.6" + attribute \src "libresoc.v:79357.3-79366.6" wire width 13 $0\tmp_tmp_trapaddr[12:0] - attribute \src "libresoc.v:79267.3-79282.6" + attribute \src "libresoc.v:79331.3-79346.6" wire width 3 $0\tmp_xer_in[2:0] - attribute \src "libresoc.v:79283.3-79292.6" + attribute \src "libresoc.v:79347.3-79356.6" wire $0\tmp_xer_out[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 13 $0\trapaddr[12:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 8 $0\traptype[7:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 3 $0\xer_in[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $0\xer_out[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 8 $1\asmcode[7:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 64 $1\cia[63:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $1\cr_in1[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $1\cr_in1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $1\cr_in2$1[6:0]$3708 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $1\cr_in2[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $1\cr_in2_ok$2[0:0]$3709 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $1\cr_in2_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $1\cr_out[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $1\cr_out_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 8 $1\cr_rd[7:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $1\cr_rd_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 8 $1\cr_wr[7:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $1\cr_wr_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $1\ea[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $1\ea_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $1\exc_$signal$3[0:0]$3711 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $1\exc_$signal$4[0:0]$3712 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $1\exc_$signal$5[0:0]$3713 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $1\exc_$signal$6[0:0]$3714 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $1\exc_$signal$7[0:0]$3715 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $1\exc_$signal$8[0:0]$3716 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $1\exc_$signal$9[0:0]$3717 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $1\exc_$signal[0:0]$3710 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 3 $1\fast1[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 3 $1\fast2[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 3 $1\fasto1[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $1\fasto1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 3 $1\fasto2[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $1\fasto2_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 14 $1\fn_unit[13:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 2 $1\input_carry[1:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 32 $1\insn[31:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $1\insn_type[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $1\is_32bit[0:0] - attribute \src "libresoc.v:79303.3-79326.6" + attribute \src "libresoc.v:79367.3-79390.6" wire $1\is_priv_insn[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $1\lk[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 64 $1\msr[63:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $1\oe[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $1\rc[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $1\rc_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $1\reg1[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $1\reg1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $1\reg2[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $1\reg2_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $1\reg3[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $1\reg3_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $1\rego[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $1\rego_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 10 $1\spr1[9:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $1\spr1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 10 $1\spro[9:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $1\spro_ok[0:0] - attribute \src "libresoc.v:79229.3-79243.6" + attribute \src "libresoc.v:79293.3-79307.6" wire width 14 $1\tmp_tmp_fn_unit[13:0] - attribute \src "libresoc.v:79254.3-79266.6" + attribute \src "libresoc.v:79318.3-79330.6" wire width 7 $1\tmp_tmp_insn_type[6:0] - attribute \src "libresoc.v:79244.3-79253.6" + attribute \src "libresoc.v:79308.3-79317.6" wire $1\tmp_tmp_lk[0:0] - attribute \src "libresoc.v:79293.3-79302.6" + attribute \src "libresoc.v:79357.3-79366.6" wire width 13 $1\tmp_tmp_trapaddr[12:0] - attribute \src "libresoc.v:79267.3-79282.6" + attribute \src "libresoc.v:79331.3-79346.6" wire width 3 $1\tmp_xer_in[2:0] - attribute \src "libresoc.v:79283.3-79292.6" + attribute \src "libresoc.v:79347.3-79356.6" wire $1\tmp_xer_out[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 13 $1\trapaddr[12:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 8 $1\traptype[7:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 3 $1\xer_in[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $1\xer_out[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 8 $2\asmcode[7:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 64 $2\cia[63:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $2\cr_in1[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $2\cr_in1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $2\cr_in2$1[6:0]$3718 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $2\cr_in2[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $2\cr_in2_ok$2[0:0]$3719 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $2\cr_in2_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $2\cr_out[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $2\cr_out_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 8 $2\cr_rd[7:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $2\cr_rd_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 8 $2\cr_wr[7:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $2\cr_wr_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $2\ea[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $2\ea_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $2\exc_$signal$3[0:0]$3721 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $2\exc_$signal$4[0:0]$3722 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $2\exc_$signal$5[0:0]$3723 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $2\exc_$signal$6[0:0]$3724 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $2\exc_$signal$7[0:0]$3725 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $2\exc_$signal$8[0:0]$3726 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $2\exc_$signal$9[0:0]$3727 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $2\exc_$signal[0:0]$3720 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 3 $2\fast1[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $2\fast1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 3 $2\fast2[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $2\fast2_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 3 $2\fasto1[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $2\fasto1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 3 $2\fasto2[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $2\fasto2_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 14 $2\fn_unit[13:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 2 $2\input_carry[1:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 32 $2\insn[31:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $2\insn_type[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $2\is_32bit[0:0] - attribute \src "libresoc.v:79303.3-79326.6" + attribute \src "libresoc.v:79367.3-79390.6" wire $2\is_priv_insn[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $2\lk[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 64 $2\msr[63:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $2\oe[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $2\oe_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $2\rc[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $2\rc_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $2\reg1[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $2\reg1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $2\reg2[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $2\reg2_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $2\reg3[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $2\reg3_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $2\rego[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $2\rego_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 10 $2\spr1[9:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $2\spr1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 10 $2\spro[9:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $2\spro_ok[0:0] - attribute \src "libresoc.v:79267.3-79282.6" + attribute \src "libresoc.v:79331.3-79346.6" wire width 3 $2\tmp_xer_in[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 13 $2\trapaddr[12:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 8 $2\traptype[7:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 3 $2\xer_in[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $2\xer_out[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 8 $3\asmcode[7:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 64 $3\cia[63:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $3\cr_in1[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $3\cr_in1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $3\cr_in2$1[6:0]$3728 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $3\cr_in2[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $3\cr_in2_ok$2[0:0]$3729 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $3\cr_in2_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $3\cr_out[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $3\cr_out_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 8 $3\cr_rd[7:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $3\cr_rd_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 8 $3\cr_wr[7:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $3\cr_wr_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $3\ea[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $3\ea_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $3\exc_$signal$3[0:0]$3731 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $3\exc_$signal$4[0:0]$3732 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $3\exc_$signal$5[0:0]$3733 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $3\exc_$signal$6[0:0]$3734 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $3\exc_$signal$7[0:0]$3735 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $3\exc_$signal$8[0:0]$3736 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $3\exc_$signal$9[0:0]$3737 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $3\exc_$signal[0:0]$3730 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 3 $3\fast1[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $3\fast1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 3 $3\fast2[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $3\fast2_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 3 $3\fasto1[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $3\fasto1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 3 $3\fasto2[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $3\fasto2_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 14 $3\fn_unit[13:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 2 $3\input_carry[1:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 32 $3\insn[31:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $3\insn_type[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $3\is_32bit[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $3\lk[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 64 $3\msr[63:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $3\oe[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $3\oe_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $3\rc[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $3\rc_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $3\reg1[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $3\reg1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $3\reg2[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $3\reg2_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $3\reg3[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $3\reg3_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $3\rego[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $3\rego_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 10 $3\spr1[9:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $3\spr1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 10 $3\spro[9:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $3\spro_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 13 $3\trapaddr[12:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 8 $3\traptype[7:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 3 $3\xer_in[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $3\xer_out[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 8 $4\asmcode[7:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 64 $4\cia[63:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $4\cr_in1[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $4\cr_in1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $4\cr_in2$1[6:0]$3738 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $4\cr_in2[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $4\cr_in2_ok$2[0:0]$3739 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $4\cr_in2_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $4\cr_out[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $4\cr_out_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 8 $4\cr_rd[7:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $4\cr_rd_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 8 $4\cr_wr[7:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $4\cr_wr_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $4\ea[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $4\ea_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $4\exc_$signal$3[0:0]$3741 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $4\exc_$signal$4[0:0]$3742 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $4\exc_$signal$5[0:0]$3743 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $4\exc_$signal$6[0:0]$3744 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $4\exc_$signal$7[0:0]$3745 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $4\exc_$signal$8[0:0]$3746 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $4\exc_$signal$9[0:0]$3747 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $4\exc_$signal[0:0]$3740 - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 3 $4\fast1[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $4\fast1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 3 $4\fast2[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $4\fast2_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 3 $4\fasto1[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $4\fasto1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 3 $4\fasto2[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $4\fasto2_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 14 $4\fn_unit[13:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 2 $4\input_carry[1:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 32 $4\insn[31:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $4\insn_type[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $4\is_32bit[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $4\lk[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 64 $4\msr[63:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $4\oe[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $4\oe_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $4\rc[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $4\rc_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $4\reg1[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $4\reg1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $4\reg2[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $4\reg2_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $4\reg3[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $4\reg3_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 7 $4\rego[6:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $4\rego_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 10 $4\spr1[9:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $4\spr1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 10 $4\spro[9:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $4\spro_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 13 $4\trapaddr[12:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 8 $4\traptype[7:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 3 $4\xer_in[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $4\xer_out[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 3 $5\fast1[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $5\fast1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 3 $5\fast2[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $5\fast2_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 3 $5\fasto1[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $5\fasto1_ok[0:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire width 3 $5\fasto2[2:0] - attribute \src "libresoc.v:79327.3-79484.6" + attribute \src "libresoc.v:79391.3-79548.6" wire $5\fasto2_ok[0:0] - attribute \src "libresoc.v:79050.19-79050.122" - wire $and$libresoc.v:79050$3648_Y - attribute \src "libresoc.v:79051.19-79051.125" - wire $and$libresoc.v:79051$3649_Y - attribute \src "libresoc.v:79052.19-79052.126" - wire $and$libresoc.v:79052$3650_Y - attribute \src "libresoc.v:79059.18-79059.114" - wire $and$libresoc.v:79059$3657_Y - attribute \src "libresoc.v:79060.18-79060.116" - wire $and$libresoc.v:79060$3658_Y - attribute \src "libresoc.v:79062.18-79062.114" - wire $and$libresoc.v:79062$3660_Y - attribute \src "libresoc.v:79064.18-79064.110" - wire $and$libresoc.v:79064$3662_Y - attribute \src "libresoc.v:79076.18-79076.114" - wire $and$libresoc.v:79076$3674_Y - attribute \src "libresoc.v:79077.18-79077.116" - wire $and$libresoc.v:79077$3675_Y - attribute \src "libresoc.v:79079.18-79079.114" - wire $and$libresoc.v:79079$3677_Y - attribute \src "libresoc.v:79081.18-79081.110" - wire $and$libresoc.v:79081$3679_Y - attribute \src "libresoc.v:79046.19-79046.124" - wire $eq$libresoc.v:79046$3644_Y - attribute \src "libresoc.v:79047.19-79047.124" - wire $eq$libresoc.v:79047$3645_Y - attribute \src "libresoc.v:79048.19-79048.124" - wire $eq$libresoc.v:79048$3646_Y - attribute \src "libresoc.v:79049.19-79049.124" - wire $eq$libresoc.v:79049$3647_Y - attribute \src "libresoc.v:79053.19-79053.124" - wire $eq$libresoc.v:79053$3651_Y - attribute \src "libresoc.v:79054.18-79054.117" - wire $eq$libresoc.v:79054$3652_Y - attribute \src "libresoc.v:79055.18-79055.117" - wire $eq$libresoc.v:79055$3653_Y - attribute \src "libresoc.v:79057.18-79057.117" - wire $eq$libresoc.v:79057$3655_Y - attribute \src "libresoc.v:79058.18-79058.127" - wire $eq$libresoc.v:79058$3656_Y - attribute \src "libresoc.v:79061.18-79061.127" - wire $eq$libresoc.v:79061$3659_Y - attribute \src "libresoc.v:79065.18-79065.122" - wire $eq$libresoc.v:79065$3663_Y - attribute \src "libresoc.v:79066.18-79066.122" - wire $eq$libresoc.v:79066$3664_Y - attribute \src "libresoc.v:79068.18-79068.110" - wire $eq$libresoc.v:79068$3666_Y - attribute \src "libresoc.v:79069.18-79069.110" - wire $eq$libresoc.v:79069$3667_Y - attribute \src "libresoc.v:79071.18-79071.112" - wire $eq$libresoc.v:79071$3669_Y - attribute \src "libresoc.v:79073.18-79073.110" - wire $eq$libresoc.v:79073$3671_Y - attribute \src "libresoc.v:79075.18-79075.127" - wire $eq$libresoc.v:79075$3673_Y - attribute \src "libresoc.v:79078.18-79078.127" - wire $eq$libresoc.v:79078$3676_Y - attribute \src "libresoc.v:79043.19-79043.124" - wire width 7 $extend$libresoc.v:79043$3638_Y - attribute \src "libresoc.v:79044.19-79044.124" - wire width 7 $extend$libresoc.v:79044$3640_Y - attribute \src "libresoc.v:79045.19-79045.123" - wire width 7 $extend$libresoc.v:79045$3642_Y - attribute \src "libresoc.v:79082.18-79082.111" - wire width 7 $extend$libresoc.v:79082$3680_Y - attribute \src "libresoc.v:79083.18-79083.111" - wire width 7 $extend$libresoc.v:79083$3682_Y - attribute \src "libresoc.v:79084.18-79084.111" - wire width 7 $extend$libresoc.v:79084$3684_Y - attribute \src "libresoc.v:79085.18-79085.113" - wire width 7 $extend$libresoc.v:79085$3686_Y - attribute \src "libresoc.v:79086.18-79086.121" - wire width 7 $extend$libresoc.v:79086$3688_Y - attribute \src "libresoc.v:79063.18-79063.110" - wire $not$libresoc.v:79063$3661_Y - attribute \src "libresoc.v:79080.18-79080.110" - wire $not$libresoc.v:79080$3678_Y - attribute \src "libresoc.v:79056.18-79056.111" - wire $or$libresoc.v:79056$3654_Y - attribute \src "libresoc.v:79067.18-79067.110" - wire $or$libresoc.v:79067$3665_Y - attribute \src "libresoc.v:79070.18-79070.110" - wire $or$libresoc.v:79070$3668_Y - attribute \src "libresoc.v:79072.18-79072.110" - wire $or$libresoc.v:79072$3670_Y - attribute \src "libresoc.v:79074.18-79074.110" - wire $or$libresoc.v:79074$3672_Y - attribute \src "libresoc.v:79043.19-79043.124" - wire width 7 $pos$libresoc.v:79043$3639_Y - attribute \src "libresoc.v:79044.19-79044.124" - wire width 7 $pos$libresoc.v:79044$3641_Y - attribute \src "libresoc.v:79045.19-79045.123" - wire width 7 $pos$libresoc.v:79045$3643_Y - attribute \src "libresoc.v:79082.18-79082.111" - wire width 7 $pos$libresoc.v:79082$3681_Y - attribute \src "libresoc.v:79083.18-79083.111" - wire width 7 $pos$libresoc.v:79083$3683_Y - attribute \src "libresoc.v:79084.18-79084.111" - wire width 7 $pos$libresoc.v:79084$3685_Y - attribute \src "libresoc.v:79085.18-79085.113" - wire width 7 $pos$libresoc.v:79085$3687_Y - attribute \src "libresoc.v:79086.18-79086.121" - wire width 7 $pos$libresoc.v:79086$3689_Y + attribute \src "libresoc.v:79114.19-79114.122" + wire $and$libresoc.v:79114$3648_Y + attribute \src "libresoc.v:79115.19-79115.125" + wire $and$libresoc.v:79115$3649_Y + attribute \src "libresoc.v:79116.19-79116.126" + wire $and$libresoc.v:79116$3650_Y + attribute \src "libresoc.v:79123.18-79123.114" + wire $and$libresoc.v:79123$3657_Y + attribute \src "libresoc.v:79124.18-79124.116" + wire $and$libresoc.v:79124$3658_Y + attribute \src "libresoc.v:79126.18-79126.114" + wire $and$libresoc.v:79126$3660_Y + attribute \src "libresoc.v:79128.18-79128.110" + wire $and$libresoc.v:79128$3662_Y + attribute \src "libresoc.v:79140.18-79140.114" + wire $and$libresoc.v:79140$3674_Y + attribute \src "libresoc.v:79141.18-79141.116" + wire $and$libresoc.v:79141$3675_Y + attribute \src "libresoc.v:79143.18-79143.114" + wire $and$libresoc.v:79143$3677_Y + attribute \src "libresoc.v:79145.18-79145.110" + wire $and$libresoc.v:79145$3679_Y + attribute \src "libresoc.v:79110.19-79110.124" + wire $eq$libresoc.v:79110$3644_Y + attribute \src "libresoc.v:79111.19-79111.124" + wire $eq$libresoc.v:79111$3645_Y + attribute \src "libresoc.v:79112.19-79112.124" + wire $eq$libresoc.v:79112$3646_Y + attribute \src "libresoc.v:79113.19-79113.124" + wire $eq$libresoc.v:79113$3647_Y + attribute \src "libresoc.v:79117.19-79117.124" + wire $eq$libresoc.v:79117$3651_Y + attribute \src "libresoc.v:79118.18-79118.117" + wire $eq$libresoc.v:79118$3652_Y + attribute \src "libresoc.v:79119.18-79119.117" + wire $eq$libresoc.v:79119$3653_Y + attribute \src "libresoc.v:79121.18-79121.117" + wire $eq$libresoc.v:79121$3655_Y + attribute \src "libresoc.v:79122.18-79122.127" + wire $eq$libresoc.v:79122$3656_Y + attribute \src "libresoc.v:79125.18-79125.127" + wire $eq$libresoc.v:79125$3659_Y + attribute \src "libresoc.v:79129.18-79129.122" + wire $eq$libresoc.v:79129$3663_Y + attribute \src "libresoc.v:79130.18-79130.122" + wire $eq$libresoc.v:79130$3664_Y + attribute \src "libresoc.v:79132.18-79132.110" + wire $eq$libresoc.v:79132$3666_Y + attribute \src "libresoc.v:79133.18-79133.110" + wire $eq$libresoc.v:79133$3667_Y + attribute \src "libresoc.v:79135.18-79135.112" + wire $eq$libresoc.v:79135$3669_Y + attribute \src "libresoc.v:79137.18-79137.110" + wire $eq$libresoc.v:79137$3671_Y + attribute \src "libresoc.v:79139.18-79139.127" + wire $eq$libresoc.v:79139$3673_Y + attribute \src "libresoc.v:79142.18-79142.127" + wire $eq$libresoc.v:79142$3676_Y + attribute \src "libresoc.v:79107.19-79107.124" + wire width 7 $extend$libresoc.v:79107$3638_Y + attribute \src "libresoc.v:79108.19-79108.124" + wire width 7 $extend$libresoc.v:79108$3640_Y + attribute \src "libresoc.v:79109.19-79109.123" + wire width 7 $extend$libresoc.v:79109$3642_Y + attribute \src "libresoc.v:79146.18-79146.111" + wire width 7 $extend$libresoc.v:79146$3680_Y + attribute \src "libresoc.v:79147.18-79147.111" + wire width 7 $extend$libresoc.v:79147$3682_Y + attribute \src "libresoc.v:79148.18-79148.111" + wire width 7 $extend$libresoc.v:79148$3684_Y + attribute \src "libresoc.v:79149.18-79149.113" + wire width 7 $extend$libresoc.v:79149$3686_Y + attribute \src "libresoc.v:79150.18-79150.121" + wire width 7 $extend$libresoc.v:79150$3688_Y + attribute \src "libresoc.v:79127.18-79127.110" + wire $not$libresoc.v:79127$3661_Y + attribute \src "libresoc.v:79144.18-79144.110" + wire $not$libresoc.v:79144$3678_Y + attribute \src "libresoc.v:79120.18-79120.111" + wire $or$libresoc.v:79120$3654_Y + attribute \src "libresoc.v:79131.18-79131.110" + wire $or$libresoc.v:79131$3665_Y + attribute \src "libresoc.v:79134.18-79134.110" + wire $or$libresoc.v:79134$3668_Y + attribute \src "libresoc.v:79136.18-79136.110" + wire $or$libresoc.v:79136$3670_Y + attribute \src "libresoc.v:79138.18-79138.110" + wire $or$libresoc.v:79138$3672_Y + attribute \src "libresoc.v:79107.19-79107.124" + wire width 7 $pos$libresoc.v:79107$3639_Y + attribute \src "libresoc.v:79108.19-79108.124" + wire width 7 $pos$libresoc.v:79108$3641_Y + attribute \src "libresoc.v:79109.19-79109.123" + wire width 7 $pos$libresoc.v:79109$3643_Y + attribute \src "libresoc.v:79146.18-79146.111" + wire width 7 $pos$libresoc.v:79146$3681_Y + attribute \src "libresoc.v:79147.18-79147.111" + wire width 7 $pos$libresoc.v:79147$3683_Y + attribute \src "libresoc.v:79148.18-79148.111" + wire width 7 $pos$libresoc.v:79148$3685_Y + attribute \src "libresoc.v:79149.18-79149.113" + wire width 7 $pos$libresoc.v:79149$3687_Y + attribute \src "libresoc.v:79150.18-79150.121" + wire width 7 $pos$libresoc.v:79150$3689_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 7 \$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" @@ -124938,7 +124989,7 @@ module \dec2 wire width 14 output 42 \fn_unit attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1217" wire \illeg_ok - attribute \src "libresoc.v:77344.7-77344.15" + attribute \src "libresoc.v:77408.7-77408.15" wire \initial attribute \enum_base_type "CryIn" attribute \enum_value_00 "ZERO" @@ -125776,7 +125827,7 @@ module \dec2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" wire output 21 \xer_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1220" - cell $and $and$libresoc.v:79050$3648 + cell $and $and$libresoc.v:79114$3648 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125784,10 +125835,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \cur_eint connect \B \cur_msr [15] - connect \Y $and$libresoc.v:79050$3648_Y + connect \Y $and$libresoc.v:79114$3648_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1221" - cell $and $and$libresoc.v:79051$3649 + cell $and $and$libresoc.v:79115$3649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125795,10 +125846,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \cur_dec [63] connect \B \cur_msr [15] - connect \Y $and$libresoc.v:79051$3649_Y + connect \Y $and$libresoc.v:79115$3649_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1222" - cell $and $and$libresoc.v:79052$3650 + cell $and $and$libresoc.v:79116$3650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125806,10 +125857,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \is_priv_insn connect \B \cur_msr [14] - connect \Y $and$libresoc.v:79052$3650_Y + connect \Y $and$libresoc.v:79116$3650_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:79059$3657 + cell $and $and$libresoc.v:79123$3657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125817,10 +125868,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$37 - connect \Y $and$libresoc.v:79059$3657_Y + connect \Y $and$libresoc.v:79123$3657_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:79060$3658 + cell $and $and$libresoc.v:79124$3658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125828,10 +125879,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$39 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:79060$3658_Y + connect \Y $and$libresoc.v:79124$3658_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:79062$3660 + cell $and $and$libresoc.v:79126$3660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125839,10 +125890,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$43 - connect \Y $and$libresoc.v:79062$3660_Y + connect \Y $and$libresoc.v:79126$3660_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:79064$3662 + cell $and $and$libresoc.v:79128$3662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125850,10 +125901,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$45 connect \B \$47 - connect \Y $and$libresoc.v:79064$3662_Y + connect \Y $and$libresoc.v:79128$3662_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:79076$3674 + cell $and $and$libresoc.v:79140$3674 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125861,10 +125912,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$71 - connect \Y $and$libresoc.v:79076$3674_Y + connect \Y $and$libresoc.v:79140$3674_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:79077$3675 + cell $and $and$libresoc.v:79141$3675 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125872,10 +125923,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$73 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:79077$3675_Y + connect \Y $and$libresoc.v:79141$3675_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:79079$3677 + cell $and $and$libresoc.v:79143$3677 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125883,10 +125934,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$77 - connect \Y $and$libresoc.v:79079$3677_Y + connect \Y $and$libresoc.v:79143$3677_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:79081$3679 + cell $and $and$libresoc.v:79145$3679 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -125894,10 +125945,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$79 connect \B \$81 - connect \Y $and$libresoc.v:79081$3679_Y + connect \Y $and$libresoc.v:79145$3679_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1189" - cell $eq $eq$libresoc.v:79046$3644 + cell $eq $eq$libresoc.v:79110$3644 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125905,10 +125956,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:79046$3644_Y + connect \Y $eq$libresoc.v:79110$3644_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1191" - cell $eq $eq$libresoc.v:79047$3645 + cell $eq $eq$libresoc.v:79111$3645 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125916,10 +125967,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0001010 - connect \Y $eq$libresoc.v:79047$3645_Y + connect \Y $eq$libresoc.v:79111$3645_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1193" - cell $eq $eq$libresoc.v:79048$3646 + cell $eq $eq$libresoc.v:79112$3646 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125927,10 +125978,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:79048$3646_Y + connect \Y $eq$libresoc.v:79112$3646_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1197" - cell $eq $eq$libresoc.v:79049$3647 + cell $eq $eq$libresoc.v:79113$3647 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125938,10 +125989,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0111111 - connect \Y $eq$libresoc.v:79049$3647_Y + connect \Y $eq$libresoc.v:79113$3647_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1223" - cell $eq $eq$libresoc.v:79053$3651 + cell $eq $eq$libresoc.v:79117$3651 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125949,10 +126000,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0000000 - connect \Y $eq$libresoc.v:79053$3651_Y + connect \Y $eq$libresoc.v:79117$3651_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1271" - cell $eq $eq$libresoc.v:79054$3652 + cell $eq $eq$libresoc.v:79118$3652 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125960,10 +126011,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \insn_type connect \B 7'0111111 - connect \Y $eq$libresoc.v:79054$3652_Y + connect \Y $eq$libresoc.v:79118$3652_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1272" - cell $eq $eq$libresoc.v:79055$3653 + cell $eq $eq$libresoc.v:79119$3653 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125971,10 +126022,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \insn_type connect \B 7'1001001 - connect \Y $eq$libresoc.v:79055$3653_Y + connect \Y $eq$libresoc.v:79119$3653_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1281" - cell $eq $eq$libresoc.v:79057$3655 + cell $eq $eq$libresoc.v:79121$3655 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -125982,10 +126033,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \insn_type connect \B 7'1000110 - connect \Y $eq$libresoc.v:79057$3655_Y + connect \Y $eq$libresoc.v:79121$3655_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $eq $eq$libresoc.v:79058$3656 + cell $eq $eq$libresoc.v:79122$3656 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -125993,10 +126044,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:79058$3656_Y + connect \Y $eq$libresoc.v:79122$3656_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $eq $eq$libresoc.v:79061$3659 + cell $eq $eq$libresoc.v:79125$3659 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -126004,10 +126055,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:79061$3659_Y + connect \Y $eq$libresoc.v:79125$3659_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $eq $eq$libresoc.v:79065$3663 + cell $eq $eq$libresoc.v:79129$3663 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -126015,10 +126066,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:79065$3663_Y + connect \Y $eq$libresoc.v:79129$3663_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $eq $eq$libresoc.v:79066$3664 + cell $eq $eq$libresoc.v:79130$3664 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -126026,10 +126077,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:79066$3664_Y + connect \Y $eq$libresoc.v:79130$3664_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:79068$3666 + cell $eq $eq$libresoc.v:79132$3666 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -126037,10 +126088,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:79068$3666_Y + connect \Y $eq$libresoc.v:79132$3666_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:79069$3667 + cell $eq $eq$libresoc.v:79133$3667 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -126048,10 +126099,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:79069$3667_Y + connect \Y $eq$libresoc.v:79133$3667_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:79071$3669 + cell $eq $eq$libresoc.v:79135$3669 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -126059,10 +126110,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:79071$3669_Y + connect \Y $eq$libresoc.v:79135$3669_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $eq $eq$libresoc.v:79073$3671 + cell $eq $eq$libresoc.v:79137$3671 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -126070,10 +126121,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:79073$3671_Y + connect \Y $eq$libresoc.v:79137$3671_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $eq $eq$libresoc.v:79075$3673 + cell $eq $eq$libresoc.v:79139$3673 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -126081,10 +126132,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:79075$3673_Y + connect \Y $eq$libresoc.v:79139$3673_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $eq $eq$libresoc.v:79078$3676 + cell $eq $eq$libresoc.v:79142$3676 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -126092,90 +126143,90 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \dec_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:79078$3676_Y + connect \Y $eq$libresoc.v:79142$3676_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:79043$3638 + cell $pos $extend$libresoc.v:79107$3638 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 7 connect \A \dec_cr_in_cr_bitfield_b - connect \Y $extend$libresoc.v:79043$3638_Y + connect \Y $extend$libresoc.v:79107$3638_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:79044$3640 + cell $pos $extend$libresoc.v:79108$3640 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 7 connect \A \dec_cr_in_cr_bitfield_o - connect \Y $extend$libresoc.v:79044$3640_Y + connect \Y $extend$libresoc.v:79108$3640_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:79045$3642 + cell $pos $extend$libresoc.v:79109$3642 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 7 connect \A \dec_cr_out_cr_bitfield - connect \Y $extend$libresoc.v:79045$3642_Y + connect \Y $extend$libresoc.v:79109$3642_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:79082$3680 + cell $pos $extend$libresoc.v:79146$3680 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \dec_a_reg_a - connect \Y $extend$libresoc.v:79082$3680_Y + connect \Y $extend$libresoc.v:79146$3680_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:79083$3682 + cell $pos $extend$libresoc.v:79147$3682 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \dec_c_reg_c - connect \Y $extend$libresoc.v:79083$3682_Y + connect \Y $extend$libresoc.v:79147$3682_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:79084$3684 + cell $pos $extend$libresoc.v:79148$3684 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \dec_o_reg_o - connect \Y $extend$libresoc.v:79084$3684_Y + connect \Y $extend$libresoc.v:79148$3684_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:79085$3686 + cell $pos $extend$libresoc.v:79149$3686 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \dec_o2_reg_o2 - connect \Y $extend$libresoc.v:79085$3686_Y + connect \Y $extend$libresoc.v:79149$3686_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:79086$3688 + cell $pos $extend$libresoc.v:79150$3688 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 7 connect \A \dec_cr_in_cr_bitfield - connect \Y $extend$libresoc.v:79086$3688_Y + connect \Y $extend$libresoc.v:79150$3688_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $not $not$libresoc.v:79063$3661 + cell $not $not$libresoc.v:79127$3661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:79063$3661_Y + connect \Y $not$libresoc.v:79127$3661_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $not $not$libresoc.v:79080$3678 + cell $not $not$libresoc.v:79144$3678 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:79080$3678_Y + connect \Y $not$libresoc.v:79144$3678_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:1272" - cell $or $or$libresoc.v:79056$3654 + cell $or $or$libresoc.v:79120$3654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -126183,10 +126234,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$28 connect \B \$30 - connect \Y $or$libresoc.v:79056$3654_Y + connect \Y $or$libresoc.v:79120$3654_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $or $or$libresoc.v:79067$3665 + cell $or $or$libresoc.v:79131$3665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -126194,10 +126245,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$51 connect \B \$53 - connect \Y $or$libresoc.v:79067$3665_Y + connect \Y $or$libresoc.v:79131$3665_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:79070$3668 + cell $or $or$libresoc.v:79134$3668 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -126205,10 +126256,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$57 connect \B \$59 - connect \Y $or$libresoc.v:79070$3668_Y + connect \Y $or$libresoc.v:79134$3668_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:79072$3670 + cell $or $or$libresoc.v:79136$3670 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -126216,10 +126267,10 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$61 connect \B \$63 - connect \Y $or$libresoc.v:79072$3670_Y + connect \Y $or$libresoc.v:79136$3670_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $or $or$libresoc.v:79074$3672 + cell $or $or$libresoc.v:79138$3672 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -126227,74 +126278,74 @@ module \dec2 parameter \Y_WIDTH 1 connect \A \$65 connect \B \$67 - connect \Y $or$libresoc.v:79074$3672_Y + connect \Y $or$libresoc.v:79138$3672_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:79043$3639 + cell $pos $pos$libresoc.v:79107$3639 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:79043$3638_Y - connect \Y $pos$libresoc.v:79043$3639_Y + connect \A $extend$libresoc.v:79107$3638_Y + connect \Y $pos$libresoc.v:79107$3639_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:79044$3641 + cell $pos $pos$libresoc.v:79108$3641 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:79044$3640_Y - connect \Y $pos$libresoc.v:79044$3641_Y + connect \A $extend$libresoc.v:79108$3640_Y + connect \Y $pos$libresoc.v:79108$3641_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:79045$3643 + cell $pos $pos$libresoc.v:79109$3643 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:79045$3642_Y - connect \Y $pos$libresoc.v:79045$3643_Y + connect \A $extend$libresoc.v:79109$3642_Y + connect \Y $pos$libresoc.v:79109$3643_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:79082$3681 + cell $pos $pos$libresoc.v:79146$3681 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:79082$3680_Y - connect \Y $pos$libresoc.v:79082$3681_Y + connect \A $extend$libresoc.v:79146$3680_Y + connect \Y $pos$libresoc.v:79146$3681_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:79083$3683 + cell $pos $pos$libresoc.v:79147$3683 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:79083$3682_Y - connect \Y $pos$libresoc.v:79083$3683_Y + connect \A $extend$libresoc.v:79147$3682_Y + connect \Y $pos$libresoc.v:79147$3683_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:79084$3685 + cell $pos $pos$libresoc.v:79148$3685 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:79084$3684_Y - connect \Y $pos$libresoc.v:79084$3685_Y + connect \A $extend$libresoc.v:79148$3684_Y + connect \Y $pos$libresoc.v:79148$3685_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:79085$3687 + cell $pos $pos$libresoc.v:79149$3687 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:79085$3686_Y - connect \Y $pos$libresoc.v:79085$3687_Y + connect \A $extend$libresoc.v:79149$3686_Y + connect \Y $pos$libresoc.v:79149$3687_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:79086$3689 + cell $pos $pos$libresoc.v:79150$3689 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:79086$3688_Y - connect \Y $pos$libresoc.v:79086$3689_Y + connect \A $extend$libresoc.v:79150$3688_Y + connect \Y $pos$libresoc.v:79150$3689_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:79087.13-79124.4" + attribute \src "libresoc.v:79151.13-79188.4" cell \dec$171 \dec connect \BA \dec_BA connect \BB \dec_BB @@ -126334,7 +126385,7 @@ module \dec2 connect \upd \dec_upd end attribute \module_not_derived 1 - attribute \src "libresoc.v:79125.9-79140.4" + attribute \src "libresoc.v:79189.9-79204.4" cell \dec_a \dec_a connect \BO \dec_BO connect \RA \dec_RA @@ -126352,7 +126403,7 @@ module \dec2 connect \sv_nz \dec_a_sv_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:79141.9-79151.4" + attribute \src "libresoc.v:79205.9-79215.4" cell \dec_b \dec_b connect \RB \dec_RB connect \RS \dec_RS @@ -126365,7 +126416,7 @@ module \dec2 connect \sel_in \dec_b_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:79152.9-79158.4" + attribute \src "libresoc.v:79216.9-79222.4" cell \dec_c \dec_c connect \RB \dec_RB connect \RS \dec_RS @@ -126374,7 +126425,7 @@ module \dec2 connect \sel_in \dec_c_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:79159.13-79178.4" + attribute \src "libresoc.v:79223.13-79242.4" cell \dec_cr_in \dec_cr_in$10 connect \BA \dec_BA connect \BB \dec_BB @@ -126396,7 +126447,7 @@ module \dec2 connect \sel_in \dec_cr_in_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:79179.14-79191.4" + attribute \src "libresoc.v:79243.14-79255.4" cell \dec_cr_out \dec_cr_out$11 connect \FXM \dec_FXM connect \XL_BT \dec_XL_BT @@ -126411,7 +126462,7 @@ module \dec2 connect \sel_in \dec_cr_out_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:79192.9-79205.4" + attribute \src "libresoc.v:79256.9-79269.4" cell \dec_o \dec_o connect \BO \dec_BO connect \RA \dec_RA @@ -126427,7 +126478,7 @@ module \dec2 connect \spr_o_ok \dec_o_spr_o_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:79206.10-79215.4" + attribute \src "libresoc.v:79270.10-79279.4" cell \dec_o2 \dec_o2 connect \RA \dec_RA connect \fast_o2 \dec_o2_fast_o2 @@ -126439,7 +126490,7 @@ module \dec2 connect \upd \dec_upd end attribute \module_not_derived 1 - attribute \src "libresoc.v:79216.16-79222.4" + attribute \src "libresoc.v:79280.16-79286.4" cell \dec_oe$173 \dec_oe connect \OE \dec_OE connect \internal_op \dec_internal_op @@ -126448,28 +126499,28 @@ module \dec2 connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:79223.16-79228.4" + attribute \src "libresoc.v:79287.16-79292.4" cell \dec_rc$172 \dec_rc connect \Rc \dec_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:77344.7-77344.20" - process $proc$libresoc.v:77344$3748 + attribute \src "libresoc.v:77408.7-77408.20" + process $proc$libresoc.v:77408$3748 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:79229.3-79243.6" - process $proc$libresoc.v:79229$3690 + attribute \src "libresoc.v:79293.3-79307.6" + process $proc$libresoc.v:79293$3690 assign { } { } assign $0\tmp_tmp_fn_unit[13:0] $1\tmp_tmp_fn_unit[13:0] - attribute \src "libresoc.v:79230.5-79230.29" + attribute \src "libresoc.v:79294.5-79294.29" switch \initial - attribute \src "libresoc.v:79230.9-79230.17" + attribute \src "libresoc.v:79294.9-79294.17" case 1'1 case end @@ -126491,14 +126542,14 @@ module \dec2 sync always update \tmp_tmp_fn_unit $0\tmp_tmp_fn_unit[13:0] end - attribute \src "libresoc.v:79244.3-79253.6" - process $proc$libresoc.v:79244$3691 + attribute \src "libresoc.v:79308.3-79317.6" + process $proc$libresoc.v:79308$3691 assign { } { } assign { } { } assign $0\tmp_tmp_lk[0:0] $1\tmp_tmp_lk[0:0] - attribute \src "libresoc.v:79245.5-79245.29" + attribute \src "libresoc.v:79309.5-79309.29" switch \initial - attribute \src "libresoc.v:79245.9-79245.17" + attribute \src "libresoc.v:79309.9-79309.17" case 1'1 case end @@ -126514,14 +126565,14 @@ module \dec2 sync always update \tmp_tmp_lk $0\tmp_tmp_lk[0:0] end - attribute \src "libresoc.v:79254.3-79266.6" - process $proc$libresoc.v:79254$3692 + attribute \src "libresoc.v:79318.3-79330.6" + process $proc$libresoc.v:79318$3692 assign { } { } assign { } { } assign $0\tmp_tmp_insn_type[6:0] $1\tmp_tmp_insn_type[6:0] - attribute \src "libresoc.v:79255.5-79255.29" + attribute \src "libresoc.v:79319.5-79319.29" switch \initial - attribute \src "libresoc.v:79255.9-79255.17" + attribute \src "libresoc.v:79319.9-79319.17" case 1'1 case end @@ -126541,15 +126592,15 @@ module \dec2 sync always update \tmp_tmp_insn_type $0\tmp_tmp_insn_type[6:0] end - attribute \src "libresoc.v:79267.3-79282.6" - process $proc$libresoc.v:79267$3693 + attribute \src "libresoc.v:79331.3-79346.6" + process $proc$libresoc.v:79331$3693 assign { } { } assign { } { } assign { } { } assign $0\tmp_xer_in[2:0] $2\tmp_xer_in[2:0] - attribute \src "libresoc.v:79268.5-79268.29" + attribute \src "libresoc.v:79332.5-79332.29" switch \initial - attribute \src "libresoc.v:79268.9-79268.17" + attribute \src "libresoc.v:79332.9-79332.17" case 1'1 case end @@ -126574,14 +126625,14 @@ module \dec2 sync always update \tmp_xer_in $0\tmp_xer_in[2:0] end - attribute \src "libresoc.v:79283.3-79292.6" - process $proc$libresoc.v:79283$3694 + attribute \src "libresoc.v:79347.3-79356.6" + process $proc$libresoc.v:79347$3694 assign { } { } assign { } { } assign $0\tmp_xer_out[0:0] $1\tmp_xer_out[0:0] - attribute \src "libresoc.v:79284.5-79284.29" + attribute \src "libresoc.v:79348.5-79348.29" switch \initial - attribute \src "libresoc.v:79284.9-79284.17" + attribute \src "libresoc.v:79348.9-79348.17" case 1'1 case end @@ -126597,14 +126648,14 @@ module \dec2 sync always update \tmp_xer_out $0\tmp_xer_out[0:0] end - attribute \src "libresoc.v:79293.3-79302.6" - process $proc$libresoc.v:79293$3695 + attribute \src "libresoc.v:79357.3-79366.6" + process $proc$libresoc.v:79357$3695 assign { } { } assign { } { } assign $0\tmp_tmp_trapaddr[12:0] $1\tmp_tmp_trapaddr[12:0] - attribute \src "libresoc.v:79294.5-79294.29" + attribute \src "libresoc.v:79358.5-79358.29" switch \initial - attribute \src "libresoc.v:79294.9-79294.17" + attribute \src "libresoc.v:79358.9-79358.17" case 1'1 case end @@ -126620,14 +126671,14 @@ module \dec2 sync always update \tmp_tmp_trapaddr $0\tmp_tmp_trapaddr[12:0] end - attribute \src "libresoc.v:79303.3-79326.6" - process $proc$libresoc.v:79303$3696 + attribute \src "libresoc.v:79367.3-79390.6" + process $proc$libresoc.v:79367$3696 assign { } { } assign { } { } assign $0\is_priv_insn[0:0] $1\is_priv_insn[0:0] - attribute \src "libresoc.v:79304.5-79304.29" + attribute \src "libresoc.v:79368.5-79368.29" switch \initial - attribute \src "libresoc.v:79304.9-79304.17" + attribute \src "libresoc.v:79368.9-79368.17" case 1'1 case end @@ -126660,8 +126711,8 @@ module \dec2 sync always update \is_priv_insn $0\is_priv_insn[0:0] end - attribute \src "libresoc.v:79327.3-79484.6" - process $proc$libresoc.v:79327$3697 + attribute \src "libresoc.v:79391.3-79548.6" + process $proc$libresoc.v:79391$3697 assign { } { } assign { } { } assign { } { } @@ -126789,9 +126840,9 @@ module \dec2 assign $0\fast2[2:0] $5\fast2[2:0] assign $0\fast2_ok[0:0] $5\fast2_ok[0:0] assign $0\asmcode[7:0] \dec_asmcode - attribute \src "libresoc.v:79328.5-79328.29" + attribute \src "libresoc.v:79392.5-79392.29" switch \initial - attribute \src "libresoc.v:79328.9-79328.17" + attribute \src "libresoc.v:79392.9-79392.17" case 1'1 case end @@ -127948,50 +127999,50 @@ module \dec2 update \xer_in $0\xer_in[2:0] update \xer_out $0\xer_out[0:0] end - connect \$100 $pos$libresoc.v:79043$3639_Y - connect \$102 $pos$libresoc.v:79044$3641_Y - connect \$104 $pos$libresoc.v:79045$3643_Y - connect \$106 $eq$libresoc.v:79046$3644_Y - connect \$108 $eq$libresoc.v:79047$3645_Y - connect \$110 $eq$libresoc.v:79048$3646_Y - connect \$112 $eq$libresoc.v:79049$3647_Y - connect \$114 $and$libresoc.v:79050$3648_Y - connect \$116 $and$libresoc.v:79051$3649_Y - connect \$118 $and$libresoc.v:79052$3650_Y - connect \$120 $eq$libresoc.v:79053$3651_Y - connect \$28 $eq$libresoc.v:79054$3652_Y - connect \$30 $eq$libresoc.v:79055$3653_Y - connect \$32 $or$libresoc.v:79056$3654_Y - connect \$34 $eq$libresoc.v:79057$3655_Y - connect \$37 $eq$libresoc.v:79058$3656_Y - connect \$39 $and$libresoc.v:79059$3657_Y - connect \$41 $and$libresoc.v:79060$3658_Y - connect \$43 $eq$libresoc.v:79061$3659_Y - connect \$45 $and$libresoc.v:79062$3660_Y - connect \$47 $not$libresoc.v:79063$3661_Y - connect \$49 $and$libresoc.v:79064$3662_Y - connect \$51 $eq$libresoc.v:79065$3663_Y - connect \$53 $eq$libresoc.v:79066$3664_Y - connect \$55 $or$libresoc.v:79067$3665_Y - connect \$57 $eq$libresoc.v:79068$3666_Y - connect \$59 $eq$libresoc.v:79069$3667_Y - connect \$61 $or$libresoc.v:79070$3668_Y - connect \$63 $eq$libresoc.v:79071$3669_Y - connect \$65 $or$libresoc.v:79072$3670_Y - connect \$67 $eq$libresoc.v:79073$3671_Y - connect \$69 $or$libresoc.v:79074$3672_Y - connect \$71 $eq$libresoc.v:79075$3673_Y - connect \$73 $and$libresoc.v:79076$3674_Y - connect \$75 $and$libresoc.v:79077$3675_Y - connect \$77 $eq$libresoc.v:79078$3676_Y - connect \$79 $and$libresoc.v:79079$3677_Y - connect \$81 $not$libresoc.v:79080$3678_Y - connect \$83 $and$libresoc.v:79081$3679_Y - connect \$90 $pos$libresoc.v:79082$3681_Y - connect \$92 $pos$libresoc.v:79083$3683_Y - connect \$94 $pos$libresoc.v:79084$3685_Y - connect \$96 $pos$libresoc.v:79085$3687_Y - connect \$98 $pos$libresoc.v:79086$3689_Y + connect \$100 $pos$libresoc.v:79107$3639_Y + connect \$102 $pos$libresoc.v:79108$3641_Y + connect \$104 $pos$libresoc.v:79109$3643_Y + connect \$106 $eq$libresoc.v:79110$3644_Y + connect \$108 $eq$libresoc.v:79111$3645_Y + connect \$110 $eq$libresoc.v:79112$3646_Y + connect \$112 $eq$libresoc.v:79113$3647_Y + connect \$114 $and$libresoc.v:79114$3648_Y + connect \$116 $and$libresoc.v:79115$3649_Y + connect \$118 $and$libresoc.v:79116$3650_Y + connect \$120 $eq$libresoc.v:79117$3651_Y + connect \$28 $eq$libresoc.v:79118$3652_Y + connect \$30 $eq$libresoc.v:79119$3653_Y + connect \$32 $or$libresoc.v:79120$3654_Y + connect \$34 $eq$libresoc.v:79121$3655_Y + connect \$37 $eq$libresoc.v:79122$3656_Y + connect \$39 $and$libresoc.v:79123$3657_Y + connect \$41 $and$libresoc.v:79124$3658_Y + connect \$43 $eq$libresoc.v:79125$3659_Y + connect \$45 $and$libresoc.v:79126$3660_Y + connect \$47 $not$libresoc.v:79127$3661_Y + connect \$49 $and$libresoc.v:79128$3662_Y + connect \$51 $eq$libresoc.v:79129$3663_Y + connect \$53 $eq$libresoc.v:79130$3664_Y + connect \$55 $or$libresoc.v:79131$3665_Y + connect \$57 $eq$libresoc.v:79132$3666_Y + connect \$59 $eq$libresoc.v:79133$3667_Y + connect \$61 $or$libresoc.v:79134$3668_Y + connect \$63 $eq$libresoc.v:79135$3669_Y + connect \$65 $or$libresoc.v:79136$3670_Y + connect \$67 $eq$libresoc.v:79137$3671_Y + connect \$69 $or$libresoc.v:79138$3672_Y + connect \$71 $eq$libresoc.v:79139$3673_Y + connect \$73 $and$libresoc.v:79140$3674_Y + connect \$75 $and$libresoc.v:79141$3675_Y + connect \$77 $eq$libresoc.v:79142$3676_Y + connect \$79 $and$libresoc.v:79143$3677_Y + connect \$81 $not$libresoc.v:79144$3678_Y + connect \$83 $and$libresoc.v:79145$3679_Y + connect \$90 $pos$libresoc.v:79146$3681_Y + connect \$92 $pos$libresoc.v:79147$3683_Y + connect \$94 $pos$libresoc.v:79148$3685_Y + connect \$96 $pos$libresoc.v:79149$3687_Y + connect \$98 $pos$libresoc.v:79150$3689_Y connect \dec2_exc_$signal 1'0 connect \dec2_exc_$signal$12 1'0 connect \dec2_exc_$signal$13 1'0 @@ -128072,144 +128123,144 @@ module \dec2 connect \insn_in$36 \dec_opcode_in connect \insn_in \dec_opcode_in end -attribute \src "libresoc.v:79568.1-80248.10" +attribute \src "libresoc.v:79632.1-80312.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec22" attribute \generator "nMigen" module \dec22 - attribute \src "libresoc.v:80187.3-80196.6" + attribute \src "libresoc.v:80251.3-80260.6" wire width 2 $0\dec22_SV_Etype[1:0] - attribute \src "libresoc.v:80197.3-80206.6" + attribute \src "libresoc.v:80261.3-80270.6" wire width 2 $0\dec22_SV_Ptype[1:0] - attribute \src "libresoc.v:80067.3-80076.6" + attribute \src "libresoc.v:80131.3-80140.6" wire width 8 $0\dec22_asmcode[7:0] - attribute \src "libresoc.v:80107.3-80116.6" + attribute \src "libresoc.v:80171.3-80180.6" wire $0\dec22_br[0:0] - attribute \src "libresoc.v:79927.3-79936.6" + attribute \src "libresoc.v:79991.3-80000.6" wire width 3 $0\dec22_cr_in[2:0] - attribute \src "libresoc.v:79937.3-79946.6" + attribute \src "libresoc.v:80001.3-80010.6" wire width 3 $0\dec22_cr_out[2:0] - attribute \src "libresoc.v:80057.3-80066.6" + attribute \src "libresoc.v:80121.3-80130.6" wire width 2 $0\dec22_cry_in[1:0] - attribute \src "libresoc.v:80097.3-80106.6" + attribute \src "libresoc.v:80161.3-80170.6" wire $0\dec22_cry_out[0:0] - attribute \src "libresoc.v:80137.3-80146.6" + attribute \src "libresoc.v:80201.3-80210.6" wire width 5 $0\dec22_form[4:0] - attribute \src "libresoc.v:79917.3-79926.6" + attribute \src "libresoc.v:79981.3-79990.6" wire width 14 $0\dec22_function_unit[13:0] - attribute \src "libresoc.v:80207.3-80216.6" + attribute \src "libresoc.v:80271.3-80280.6" wire width 3 $0\dec22_in1_sel[2:0] - attribute \src "libresoc.v:80217.3-80226.6" + attribute \src "libresoc.v:80281.3-80290.6" wire width 4 $0\dec22_in2_sel[3:0] - attribute \src "libresoc.v:80227.3-80236.6" + attribute \src "libresoc.v:80291.3-80300.6" wire width 2 $0\dec22_in3_sel[1:0] - attribute \src "libresoc.v:80027.3-80036.6" + attribute \src "libresoc.v:80091.3-80100.6" wire width 7 $0\dec22_internal_op[6:0] - attribute \src "libresoc.v:80077.3-80086.6" + attribute \src "libresoc.v:80141.3-80150.6" wire $0\dec22_inv_a[0:0] - attribute \src "libresoc.v:80087.3-80096.6" + attribute \src "libresoc.v:80151.3-80160.6" wire $0\dec22_inv_out[0:0] - attribute \src "libresoc.v:80147.3-80156.6" + attribute \src "libresoc.v:80211.3-80220.6" wire $0\dec22_is_32b[0:0] - attribute \src "libresoc.v:80017.3-80026.6" + attribute \src "libresoc.v:80081.3-80090.6" wire width 4 $0\dec22_ldst_len[3:0] - attribute \src "libresoc.v:80167.3-80176.6" + attribute \src "libresoc.v:80231.3-80240.6" wire $0\dec22_lk[0:0] - attribute \src "libresoc.v:80237.3-80246.6" + attribute \src "libresoc.v:80301.3-80310.6" wire width 3 $0\dec22_out_sel[2:0] - attribute \src "libresoc.v:80047.3-80056.6" + attribute \src "libresoc.v:80111.3-80120.6" wire width 2 $0\dec22_rc_sel[1:0] - attribute \src "libresoc.v:80127.3-80136.6" + attribute \src "libresoc.v:80191.3-80200.6" wire $0\dec22_rsrv[0:0] - attribute \src "libresoc.v:80177.3-80186.6" + attribute \src "libresoc.v:80241.3-80250.6" wire $0\dec22_sgl_pipe[0:0] - attribute \src "libresoc.v:80157.3-80166.6" + attribute \src "libresoc.v:80221.3-80230.6" wire $0\dec22_sgn[0:0] - attribute \src "libresoc.v:80117.3-80126.6" + attribute \src "libresoc.v:80181.3-80190.6" wire $0\dec22_sgn_ext[0:0] - attribute \src "libresoc.v:79997.3-80006.6" + attribute \src "libresoc.v:80061.3-80070.6" wire width 3 $0\dec22_sv_cr_in[2:0] - attribute \src "libresoc.v:80007.3-80016.6" + attribute \src "libresoc.v:80071.3-80080.6" wire width 3 $0\dec22_sv_cr_out[2:0] - attribute \src "libresoc.v:79947.3-79956.6" + attribute \src "libresoc.v:80011.3-80020.6" wire width 3 $0\dec22_sv_in1[2:0] - attribute \src "libresoc.v:79957.3-79966.6" + attribute \src "libresoc.v:80021.3-80030.6" wire width 3 $0\dec22_sv_in2[2:0] - attribute \src "libresoc.v:79967.3-79976.6" + attribute \src "libresoc.v:80031.3-80040.6" wire width 3 $0\dec22_sv_in3[2:0] - attribute \src "libresoc.v:79987.3-79996.6" + attribute \src "libresoc.v:80051.3-80060.6" wire width 3 $0\dec22_sv_out2[2:0] - attribute \src "libresoc.v:79977.3-79986.6" + attribute \src "libresoc.v:80041.3-80050.6" wire width 3 $0\dec22_sv_out[2:0] - attribute \src "libresoc.v:80037.3-80046.6" + attribute \src "libresoc.v:80101.3-80110.6" wire width 2 $0\dec22_upd[1:0] - attribute \src "libresoc.v:79569.7-79569.20" + attribute \src "libresoc.v:79633.7-79633.20" wire $0\initial[0:0] - attribute \src "libresoc.v:80187.3-80196.6" + attribute \src "libresoc.v:80251.3-80260.6" wire width 2 $1\dec22_SV_Etype[1:0] - attribute \src "libresoc.v:80197.3-80206.6" + attribute \src "libresoc.v:80261.3-80270.6" wire width 2 $1\dec22_SV_Ptype[1:0] - attribute \src "libresoc.v:80067.3-80076.6" + attribute \src "libresoc.v:80131.3-80140.6" wire width 8 $1\dec22_asmcode[7:0] - attribute \src "libresoc.v:80107.3-80116.6" + attribute \src "libresoc.v:80171.3-80180.6" wire $1\dec22_br[0:0] - attribute \src "libresoc.v:79927.3-79936.6" + attribute \src "libresoc.v:79991.3-80000.6" wire width 3 $1\dec22_cr_in[2:0] - attribute \src "libresoc.v:79937.3-79946.6" + attribute \src "libresoc.v:80001.3-80010.6" wire width 3 $1\dec22_cr_out[2:0] - attribute \src "libresoc.v:80057.3-80066.6" + attribute \src "libresoc.v:80121.3-80130.6" wire width 2 $1\dec22_cry_in[1:0] - attribute \src "libresoc.v:80097.3-80106.6" + attribute \src "libresoc.v:80161.3-80170.6" wire $1\dec22_cry_out[0:0] - attribute \src "libresoc.v:80137.3-80146.6" + attribute \src "libresoc.v:80201.3-80210.6" wire width 5 $1\dec22_form[4:0] - attribute \src "libresoc.v:79917.3-79926.6" + attribute \src "libresoc.v:79981.3-79990.6" wire width 14 $1\dec22_function_unit[13:0] - attribute \src "libresoc.v:80207.3-80216.6" + attribute \src "libresoc.v:80271.3-80280.6" wire width 3 $1\dec22_in1_sel[2:0] - attribute \src "libresoc.v:80217.3-80226.6" + attribute \src "libresoc.v:80281.3-80290.6" wire width 4 $1\dec22_in2_sel[3:0] - attribute \src "libresoc.v:80227.3-80236.6" + attribute \src "libresoc.v:80291.3-80300.6" wire width 2 $1\dec22_in3_sel[1:0] - attribute \src "libresoc.v:80027.3-80036.6" + attribute \src "libresoc.v:80091.3-80100.6" wire width 7 $1\dec22_internal_op[6:0] - attribute \src "libresoc.v:80077.3-80086.6" + attribute \src "libresoc.v:80141.3-80150.6" wire $1\dec22_inv_a[0:0] - attribute \src "libresoc.v:80087.3-80096.6" + attribute \src "libresoc.v:80151.3-80160.6" wire $1\dec22_inv_out[0:0] - attribute \src "libresoc.v:80147.3-80156.6" + attribute \src "libresoc.v:80211.3-80220.6" wire $1\dec22_is_32b[0:0] - attribute \src "libresoc.v:80017.3-80026.6" + attribute \src "libresoc.v:80081.3-80090.6" wire width 4 $1\dec22_ldst_len[3:0] - attribute \src "libresoc.v:80167.3-80176.6" + attribute \src "libresoc.v:80231.3-80240.6" wire $1\dec22_lk[0:0] - attribute \src "libresoc.v:80237.3-80246.6" + attribute \src "libresoc.v:80301.3-80310.6" wire width 3 $1\dec22_out_sel[2:0] - attribute \src "libresoc.v:80047.3-80056.6" + attribute \src "libresoc.v:80111.3-80120.6" wire width 2 $1\dec22_rc_sel[1:0] - attribute \src "libresoc.v:80127.3-80136.6" + attribute \src "libresoc.v:80191.3-80200.6" wire $1\dec22_rsrv[0:0] - attribute \src "libresoc.v:80177.3-80186.6" + attribute \src "libresoc.v:80241.3-80250.6" wire $1\dec22_sgl_pipe[0:0] - attribute \src "libresoc.v:80157.3-80166.6" + attribute \src "libresoc.v:80221.3-80230.6" wire $1\dec22_sgn[0:0] - attribute \src "libresoc.v:80117.3-80126.6" + attribute \src "libresoc.v:80181.3-80190.6" wire $1\dec22_sgn_ext[0:0] - attribute \src "libresoc.v:79997.3-80006.6" + attribute \src "libresoc.v:80061.3-80070.6" wire width 3 $1\dec22_sv_cr_in[2:0] - attribute \src "libresoc.v:80007.3-80016.6" + attribute \src "libresoc.v:80071.3-80080.6" wire width 3 $1\dec22_sv_cr_out[2:0] - attribute \src "libresoc.v:79947.3-79956.6" + attribute \src "libresoc.v:80011.3-80020.6" wire width 3 $1\dec22_sv_in1[2:0] - attribute \src "libresoc.v:79957.3-79966.6" + attribute \src "libresoc.v:80021.3-80030.6" wire width 3 $1\dec22_sv_in2[2:0] - attribute \src "libresoc.v:79967.3-79976.6" + attribute \src "libresoc.v:80031.3-80040.6" wire width 3 $1\dec22_sv_in3[2:0] - attribute \src "libresoc.v:79987.3-79996.6" + attribute \src "libresoc.v:80051.3-80060.6" wire width 3 $1\dec22_sv_out2[2:0] - attribute \src "libresoc.v:79977.3-79986.6" + attribute \src "libresoc.v:80041.3-80050.6" wire width 3 $1\dec22_sv_out[2:0] - attribute \src "libresoc.v:80037.3-80046.6" + attribute \src "libresoc.v:80101.3-80110.6" wire width 2 $1\dec22_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -128521,28 +128572,28 @@ module \dec22 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec22_upd - attribute \src "libresoc.v:79569.7-79569.15" + attribute \src "libresoc.v:79633.7-79633.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 4 \opcode_switch - attribute \src "libresoc.v:79569.7-79569.20" - process $proc$libresoc.v:79569$3782 + attribute \src "libresoc.v:79633.7-79633.20" + process $proc$libresoc.v:79633$3782 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:79917.3-79926.6" - process $proc$libresoc.v:79917$3749 + attribute \src "libresoc.v:79981.3-79990.6" + process $proc$libresoc.v:79981$3749 assign { } { } assign { } { } assign $0\dec22_function_unit[13:0] $1\dec22_function_unit[13:0] - attribute \src "libresoc.v:79918.5-79918.29" + attribute \src "libresoc.v:79982.5-79982.29" switch \initial - attribute \src "libresoc.v:79918.9-79918.17" + attribute \src "libresoc.v:79982.9-79982.17" case 1'1 case end @@ -128558,14 +128609,14 @@ module \dec22 sync always update \dec22_function_unit $0\dec22_function_unit[13:0] end - attribute \src "libresoc.v:79927.3-79936.6" - process $proc$libresoc.v:79927$3750 + attribute \src "libresoc.v:79991.3-80000.6" + process $proc$libresoc.v:79991$3750 assign { } { } assign { } { } assign $0\dec22_cr_in[2:0] $1\dec22_cr_in[2:0] - attribute \src "libresoc.v:79928.5-79928.29" + attribute \src "libresoc.v:79992.5-79992.29" switch \initial - attribute \src "libresoc.v:79928.9-79928.17" + attribute \src "libresoc.v:79992.9-79992.17" case 1'1 case end @@ -128581,14 +128632,14 @@ module \dec22 sync always update \dec22_cr_in $0\dec22_cr_in[2:0] end - attribute \src "libresoc.v:79937.3-79946.6" - process $proc$libresoc.v:79937$3751 + attribute \src "libresoc.v:80001.3-80010.6" + process $proc$libresoc.v:80001$3751 assign { } { } assign { } { } assign $0\dec22_cr_out[2:0] $1\dec22_cr_out[2:0] - attribute \src "libresoc.v:79938.5-79938.29" + attribute \src "libresoc.v:80002.5-80002.29" switch \initial - attribute \src "libresoc.v:79938.9-79938.17" + attribute \src "libresoc.v:80002.9-80002.17" case 1'1 case end @@ -128604,14 +128655,14 @@ module \dec22 sync always update \dec22_cr_out $0\dec22_cr_out[2:0] end - attribute \src "libresoc.v:79947.3-79956.6" - process $proc$libresoc.v:79947$3752 + attribute \src "libresoc.v:80011.3-80020.6" + process $proc$libresoc.v:80011$3752 assign { } { } assign { } { } assign $0\dec22_sv_in1[2:0] $1\dec22_sv_in1[2:0] - attribute \src "libresoc.v:79948.5-79948.29" + attribute \src "libresoc.v:80012.5-80012.29" switch \initial - attribute \src "libresoc.v:79948.9-79948.17" + attribute \src "libresoc.v:80012.9-80012.17" case 1'1 case end @@ -128627,14 +128678,14 @@ module \dec22 sync always update \dec22_sv_in1 $0\dec22_sv_in1[2:0] end - attribute \src "libresoc.v:79957.3-79966.6" - process $proc$libresoc.v:79957$3753 + attribute \src "libresoc.v:80021.3-80030.6" + process $proc$libresoc.v:80021$3753 assign { } { } assign { } { } assign $0\dec22_sv_in2[2:0] $1\dec22_sv_in2[2:0] - attribute \src "libresoc.v:79958.5-79958.29" + attribute \src "libresoc.v:80022.5-80022.29" switch \initial - attribute \src "libresoc.v:79958.9-79958.17" + attribute \src "libresoc.v:80022.9-80022.17" case 1'1 case end @@ -128650,14 +128701,14 @@ module \dec22 sync always update \dec22_sv_in2 $0\dec22_sv_in2[2:0] end - attribute \src "libresoc.v:79967.3-79976.6" - process $proc$libresoc.v:79967$3754 + attribute \src "libresoc.v:80031.3-80040.6" + process $proc$libresoc.v:80031$3754 assign { } { } assign { } { } assign $0\dec22_sv_in3[2:0] $1\dec22_sv_in3[2:0] - attribute \src "libresoc.v:79968.5-79968.29" + attribute \src "libresoc.v:80032.5-80032.29" switch \initial - attribute \src "libresoc.v:79968.9-79968.17" + attribute \src "libresoc.v:80032.9-80032.17" case 1'1 case end @@ -128673,14 +128724,14 @@ module \dec22 sync always update \dec22_sv_in3 $0\dec22_sv_in3[2:0] end - attribute \src "libresoc.v:79977.3-79986.6" - process $proc$libresoc.v:79977$3755 + attribute \src "libresoc.v:80041.3-80050.6" + process $proc$libresoc.v:80041$3755 assign { } { } assign { } { } assign $0\dec22_sv_out[2:0] $1\dec22_sv_out[2:0] - attribute \src "libresoc.v:79978.5-79978.29" + attribute \src "libresoc.v:80042.5-80042.29" switch \initial - attribute \src "libresoc.v:79978.9-79978.17" + attribute \src "libresoc.v:80042.9-80042.17" case 1'1 case end @@ -128696,14 +128747,14 @@ module \dec22 sync always update \dec22_sv_out $0\dec22_sv_out[2:0] end - attribute \src "libresoc.v:79987.3-79996.6" - process $proc$libresoc.v:79987$3756 + attribute \src "libresoc.v:80051.3-80060.6" + process $proc$libresoc.v:80051$3756 assign { } { } assign { } { } assign $0\dec22_sv_out2[2:0] $1\dec22_sv_out2[2:0] - attribute \src "libresoc.v:79988.5-79988.29" + attribute \src "libresoc.v:80052.5-80052.29" switch \initial - attribute \src "libresoc.v:79988.9-79988.17" + attribute \src "libresoc.v:80052.9-80052.17" case 1'1 case end @@ -128719,14 +128770,14 @@ module \dec22 sync always update \dec22_sv_out2 $0\dec22_sv_out2[2:0] end - attribute \src "libresoc.v:79997.3-80006.6" - process $proc$libresoc.v:79997$3757 + attribute \src "libresoc.v:80061.3-80070.6" + process $proc$libresoc.v:80061$3757 assign { } { } assign { } { } assign $0\dec22_sv_cr_in[2:0] $1\dec22_sv_cr_in[2:0] - attribute \src "libresoc.v:79998.5-79998.29" + attribute \src "libresoc.v:80062.5-80062.29" switch \initial - attribute \src "libresoc.v:79998.9-79998.17" + attribute \src "libresoc.v:80062.9-80062.17" case 1'1 case end @@ -128742,14 +128793,14 @@ module \dec22 sync always update \dec22_sv_cr_in $0\dec22_sv_cr_in[2:0] end - attribute \src "libresoc.v:80007.3-80016.6" - process $proc$libresoc.v:80007$3758 + attribute \src "libresoc.v:80071.3-80080.6" + process $proc$libresoc.v:80071$3758 assign { } { } assign { } { } assign $0\dec22_sv_cr_out[2:0] $1\dec22_sv_cr_out[2:0] - attribute \src "libresoc.v:80008.5-80008.29" + attribute \src "libresoc.v:80072.5-80072.29" switch \initial - attribute \src "libresoc.v:80008.9-80008.17" + attribute \src "libresoc.v:80072.9-80072.17" case 1'1 case end @@ -128765,14 +128816,14 @@ module \dec22 sync always update \dec22_sv_cr_out $0\dec22_sv_cr_out[2:0] end - attribute \src "libresoc.v:80017.3-80026.6" - process $proc$libresoc.v:80017$3759 + attribute \src "libresoc.v:80081.3-80090.6" + process $proc$libresoc.v:80081$3759 assign { } { } assign { } { } assign $0\dec22_ldst_len[3:0] $1\dec22_ldst_len[3:0] - attribute \src "libresoc.v:80018.5-80018.29" + attribute \src "libresoc.v:80082.5-80082.29" switch \initial - attribute \src "libresoc.v:80018.9-80018.17" + attribute \src "libresoc.v:80082.9-80082.17" case 1'1 case end @@ -128788,14 +128839,14 @@ module \dec22 sync always update \dec22_ldst_len $0\dec22_ldst_len[3:0] end - attribute \src "libresoc.v:80027.3-80036.6" - process $proc$libresoc.v:80027$3760 + attribute \src "libresoc.v:80091.3-80100.6" + process $proc$libresoc.v:80091$3760 assign { } { } assign { } { } assign $0\dec22_internal_op[6:0] $1\dec22_internal_op[6:0] - attribute \src "libresoc.v:80028.5-80028.29" + attribute \src "libresoc.v:80092.5-80092.29" switch \initial - attribute \src "libresoc.v:80028.9-80028.17" + attribute \src "libresoc.v:80092.9-80092.17" case 1'1 case end @@ -128811,14 +128862,14 @@ module \dec22 sync always update \dec22_internal_op $0\dec22_internal_op[6:0] end - attribute \src "libresoc.v:80037.3-80046.6" - process $proc$libresoc.v:80037$3761 + attribute \src "libresoc.v:80101.3-80110.6" + process $proc$libresoc.v:80101$3761 assign { } { } assign { } { } assign $0\dec22_upd[1:0] $1\dec22_upd[1:0] - attribute \src "libresoc.v:80038.5-80038.29" + attribute \src "libresoc.v:80102.5-80102.29" switch \initial - attribute \src "libresoc.v:80038.9-80038.17" + attribute \src "libresoc.v:80102.9-80102.17" case 1'1 case end @@ -128834,14 +128885,14 @@ module \dec22 sync always update \dec22_upd $0\dec22_upd[1:0] end - attribute \src "libresoc.v:80047.3-80056.6" - process $proc$libresoc.v:80047$3762 + attribute \src "libresoc.v:80111.3-80120.6" + process $proc$libresoc.v:80111$3762 assign { } { } assign { } { } assign $0\dec22_rc_sel[1:0] $1\dec22_rc_sel[1:0] - attribute \src "libresoc.v:80048.5-80048.29" + attribute \src "libresoc.v:80112.5-80112.29" switch \initial - attribute \src "libresoc.v:80048.9-80048.17" + attribute \src "libresoc.v:80112.9-80112.17" case 1'1 case end @@ -128857,14 +128908,14 @@ module \dec22 sync always update \dec22_rc_sel $0\dec22_rc_sel[1:0] end - attribute \src "libresoc.v:80057.3-80066.6" - process $proc$libresoc.v:80057$3763 + attribute \src "libresoc.v:80121.3-80130.6" + process $proc$libresoc.v:80121$3763 assign { } { } assign { } { } assign $0\dec22_cry_in[1:0] $1\dec22_cry_in[1:0] - attribute \src "libresoc.v:80058.5-80058.29" + attribute \src "libresoc.v:80122.5-80122.29" switch \initial - attribute \src "libresoc.v:80058.9-80058.17" + attribute \src "libresoc.v:80122.9-80122.17" case 1'1 case end @@ -128880,14 +128931,14 @@ module \dec22 sync always update \dec22_cry_in $0\dec22_cry_in[1:0] end - attribute \src "libresoc.v:80067.3-80076.6" - process $proc$libresoc.v:80067$3764 + attribute \src "libresoc.v:80131.3-80140.6" + process $proc$libresoc.v:80131$3764 assign { } { } assign { } { } assign $0\dec22_asmcode[7:0] $1\dec22_asmcode[7:0] - attribute \src "libresoc.v:80068.5-80068.29" + attribute \src "libresoc.v:80132.5-80132.29" switch \initial - attribute \src "libresoc.v:80068.9-80068.17" + attribute \src "libresoc.v:80132.9-80132.17" case 1'1 case end @@ -128903,14 +128954,14 @@ module \dec22 sync always update \dec22_asmcode $0\dec22_asmcode[7:0] end - attribute \src "libresoc.v:80077.3-80086.6" - process $proc$libresoc.v:80077$3765 + attribute \src "libresoc.v:80141.3-80150.6" + process $proc$libresoc.v:80141$3765 assign { } { } assign { } { } assign $0\dec22_inv_a[0:0] $1\dec22_inv_a[0:0] - attribute \src "libresoc.v:80078.5-80078.29" + attribute \src "libresoc.v:80142.5-80142.29" switch \initial - attribute \src "libresoc.v:80078.9-80078.17" + attribute \src "libresoc.v:80142.9-80142.17" case 1'1 case end @@ -128926,14 +128977,14 @@ module \dec22 sync always update \dec22_inv_a $0\dec22_inv_a[0:0] end - attribute \src "libresoc.v:80087.3-80096.6" - process $proc$libresoc.v:80087$3766 + attribute \src "libresoc.v:80151.3-80160.6" + process $proc$libresoc.v:80151$3766 assign { } { } assign { } { } assign $0\dec22_inv_out[0:0] $1\dec22_inv_out[0:0] - attribute \src "libresoc.v:80088.5-80088.29" + attribute \src "libresoc.v:80152.5-80152.29" switch \initial - attribute \src "libresoc.v:80088.9-80088.17" + attribute \src "libresoc.v:80152.9-80152.17" case 1'1 case end @@ -128949,14 +129000,14 @@ module \dec22 sync always update \dec22_inv_out $0\dec22_inv_out[0:0] end - attribute \src "libresoc.v:80097.3-80106.6" - process $proc$libresoc.v:80097$3767 + attribute \src "libresoc.v:80161.3-80170.6" + process $proc$libresoc.v:80161$3767 assign { } { } assign { } { } assign $0\dec22_cry_out[0:0] $1\dec22_cry_out[0:0] - attribute \src "libresoc.v:80098.5-80098.29" + attribute \src "libresoc.v:80162.5-80162.29" switch \initial - attribute \src "libresoc.v:80098.9-80098.17" + attribute \src "libresoc.v:80162.9-80162.17" case 1'1 case end @@ -128972,14 +129023,14 @@ module \dec22 sync always update \dec22_cry_out $0\dec22_cry_out[0:0] end - attribute \src "libresoc.v:80107.3-80116.6" - process $proc$libresoc.v:80107$3768 + attribute \src "libresoc.v:80171.3-80180.6" + process $proc$libresoc.v:80171$3768 assign { } { } assign { } { } assign $0\dec22_br[0:0] $1\dec22_br[0:0] - attribute \src "libresoc.v:80108.5-80108.29" + attribute \src "libresoc.v:80172.5-80172.29" switch \initial - attribute \src "libresoc.v:80108.9-80108.17" + attribute \src "libresoc.v:80172.9-80172.17" case 1'1 case end @@ -128995,14 +129046,14 @@ module \dec22 sync always update \dec22_br $0\dec22_br[0:0] end - attribute \src "libresoc.v:80117.3-80126.6" - process $proc$libresoc.v:80117$3769 + attribute \src "libresoc.v:80181.3-80190.6" + process $proc$libresoc.v:80181$3769 assign { } { } assign { } { } assign $0\dec22_sgn_ext[0:0] $1\dec22_sgn_ext[0:0] - attribute \src "libresoc.v:80118.5-80118.29" + attribute \src "libresoc.v:80182.5-80182.29" switch \initial - attribute \src "libresoc.v:80118.9-80118.17" + attribute \src "libresoc.v:80182.9-80182.17" case 1'1 case end @@ -129018,14 +129069,14 @@ module \dec22 sync always update \dec22_sgn_ext $0\dec22_sgn_ext[0:0] end - attribute \src "libresoc.v:80127.3-80136.6" - process $proc$libresoc.v:80127$3770 + attribute \src "libresoc.v:80191.3-80200.6" + process $proc$libresoc.v:80191$3770 assign { } { } assign { } { } assign $0\dec22_rsrv[0:0] $1\dec22_rsrv[0:0] - attribute \src "libresoc.v:80128.5-80128.29" + attribute \src "libresoc.v:80192.5-80192.29" switch \initial - attribute \src "libresoc.v:80128.9-80128.17" + attribute \src "libresoc.v:80192.9-80192.17" case 1'1 case end @@ -129041,14 +129092,14 @@ module \dec22 sync always update \dec22_rsrv $0\dec22_rsrv[0:0] end - attribute \src "libresoc.v:80137.3-80146.6" - process $proc$libresoc.v:80137$3771 + attribute \src "libresoc.v:80201.3-80210.6" + process $proc$libresoc.v:80201$3771 assign { } { } assign { } { } assign $0\dec22_form[4:0] $1\dec22_form[4:0] - attribute \src "libresoc.v:80138.5-80138.29" + attribute \src "libresoc.v:80202.5-80202.29" switch \initial - attribute \src "libresoc.v:80138.9-80138.17" + attribute \src "libresoc.v:80202.9-80202.17" case 1'1 case end @@ -129064,14 +129115,14 @@ module \dec22 sync always update \dec22_form $0\dec22_form[4:0] end - attribute \src "libresoc.v:80147.3-80156.6" - process $proc$libresoc.v:80147$3772 + attribute \src "libresoc.v:80211.3-80220.6" + process $proc$libresoc.v:80211$3772 assign { } { } assign { } { } assign $0\dec22_is_32b[0:0] $1\dec22_is_32b[0:0] - attribute \src "libresoc.v:80148.5-80148.29" + attribute \src "libresoc.v:80212.5-80212.29" switch \initial - attribute \src "libresoc.v:80148.9-80148.17" + attribute \src "libresoc.v:80212.9-80212.17" case 1'1 case end @@ -129087,14 +129138,14 @@ module \dec22 sync always update \dec22_is_32b $0\dec22_is_32b[0:0] end - attribute \src "libresoc.v:80157.3-80166.6" - process $proc$libresoc.v:80157$3773 + attribute \src "libresoc.v:80221.3-80230.6" + process $proc$libresoc.v:80221$3773 assign { } { } assign { } { } assign $0\dec22_sgn[0:0] $1\dec22_sgn[0:0] - attribute \src "libresoc.v:80158.5-80158.29" + attribute \src "libresoc.v:80222.5-80222.29" switch \initial - attribute \src "libresoc.v:80158.9-80158.17" + attribute \src "libresoc.v:80222.9-80222.17" case 1'1 case end @@ -129110,14 +129161,14 @@ module \dec22 sync always update \dec22_sgn $0\dec22_sgn[0:0] end - attribute \src "libresoc.v:80167.3-80176.6" - process $proc$libresoc.v:80167$3774 + attribute \src "libresoc.v:80231.3-80240.6" + process $proc$libresoc.v:80231$3774 assign { } { } assign { } { } assign $0\dec22_lk[0:0] $1\dec22_lk[0:0] - attribute \src "libresoc.v:80168.5-80168.29" + attribute \src "libresoc.v:80232.5-80232.29" switch \initial - attribute \src "libresoc.v:80168.9-80168.17" + attribute \src "libresoc.v:80232.9-80232.17" case 1'1 case end @@ -129133,14 +129184,14 @@ module \dec22 sync always update \dec22_lk $0\dec22_lk[0:0] end - attribute \src "libresoc.v:80177.3-80186.6" - process $proc$libresoc.v:80177$3775 + attribute \src "libresoc.v:80241.3-80250.6" + process $proc$libresoc.v:80241$3775 assign { } { } assign { } { } assign $0\dec22_sgl_pipe[0:0] $1\dec22_sgl_pipe[0:0] - attribute \src "libresoc.v:80178.5-80178.29" + attribute \src "libresoc.v:80242.5-80242.29" switch \initial - attribute \src "libresoc.v:80178.9-80178.17" + attribute \src "libresoc.v:80242.9-80242.17" case 1'1 case end @@ -129156,14 +129207,14 @@ module \dec22 sync always update \dec22_sgl_pipe $0\dec22_sgl_pipe[0:0] end - attribute \src "libresoc.v:80187.3-80196.6" - process $proc$libresoc.v:80187$3776 + attribute \src "libresoc.v:80251.3-80260.6" + process $proc$libresoc.v:80251$3776 assign { } { } assign { } { } assign $0\dec22_SV_Etype[1:0] $1\dec22_SV_Etype[1:0] - attribute \src "libresoc.v:80188.5-80188.29" + attribute \src "libresoc.v:80252.5-80252.29" switch \initial - attribute \src "libresoc.v:80188.9-80188.17" + attribute \src "libresoc.v:80252.9-80252.17" case 1'1 case end @@ -129179,14 +129230,14 @@ module \dec22 sync always update \dec22_SV_Etype $0\dec22_SV_Etype[1:0] end - attribute \src "libresoc.v:80197.3-80206.6" - process $proc$libresoc.v:80197$3777 + attribute \src "libresoc.v:80261.3-80270.6" + process $proc$libresoc.v:80261$3777 assign { } { } assign { } { } assign $0\dec22_SV_Ptype[1:0] $1\dec22_SV_Ptype[1:0] - attribute \src "libresoc.v:80198.5-80198.29" + attribute \src "libresoc.v:80262.5-80262.29" switch \initial - attribute \src "libresoc.v:80198.9-80198.17" + attribute \src "libresoc.v:80262.9-80262.17" case 1'1 case end @@ -129202,14 +129253,14 @@ module \dec22 sync always update \dec22_SV_Ptype $0\dec22_SV_Ptype[1:0] end - attribute \src "libresoc.v:80207.3-80216.6" - process $proc$libresoc.v:80207$3778 + attribute \src "libresoc.v:80271.3-80280.6" + process $proc$libresoc.v:80271$3778 assign { } { } assign { } { } assign $0\dec22_in1_sel[2:0] $1\dec22_in1_sel[2:0] - attribute \src "libresoc.v:80208.5-80208.29" + attribute \src "libresoc.v:80272.5-80272.29" switch \initial - attribute \src "libresoc.v:80208.9-80208.17" + attribute \src "libresoc.v:80272.9-80272.17" case 1'1 case end @@ -129225,14 +129276,14 @@ module \dec22 sync always update \dec22_in1_sel $0\dec22_in1_sel[2:0] end - attribute \src "libresoc.v:80217.3-80226.6" - process $proc$libresoc.v:80217$3779 + attribute \src "libresoc.v:80281.3-80290.6" + process $proc$libresoc.v:80281$3779 assign { } { } assign { } { } assign $0\dec22_in2_sel[3:0] $1\dec22_in2_sel[3:0] - attribute \src "libresoc.v:80218.5-80218.29" + attribute \src "libresoc.v:80282.5-80282.29" switch \initial - attribute \src "libresoc.v:80218.9-80218.17" + attribute \src "libresoc.v:80282.9-80282.17" case 1'1 case end @@ -129248,14 +129299,14 @@ module \dec22 sync always update \dec22_in2_sel $0\dec22_in2_sel[3:0] end - attribute \src "libresoc.v:80227.3-80236.6" - process $proc$libresoc.v:80227$3780 + attribute \src "libresoc.v:80291.3-80300.6" + process $proc$libresoc.v:80291$3780 assign { } { } assign { } { } assign $0\dec22_in3_sel[1:0] $1\dec22_in3_sel[1:0] - attribute \src "libresoc.v:80228.5-80228.29" + attribute \src "libresoc.v:80292.5-80292.29" switch \initial - attribute \src "libresoc.v:80228.9-80228.17" + attribute \src "libresoc.v:80292.9-80292.17" case 1'1 case end @@ -129271,14 +129322,14 @@ module \dec22 sync always update \dec22_in3_sel $0\dec22_in3_sel[1:0] end - attribute \src "libresoc.v:80237.3-80246.6" - process $proc$libresoc.v:80237$3781 + attribute \src "libresoc.v:80301.3-80310.6" + process $proc$libresoc.v:80301$3781 assign { } { } assign { } { } assign $0\dec22_out_sel[2:0] $1\dec22_out_sel[2:0] - attribute \src "libresoc.v:80238.5-80238.29" + attribute \src "libresoc.v:80302.5-80302.29" switch \initial - attribute \src "libresoc.v:80238.9-80238.17" + attribute \src "libresoc.v:80302.9-80302.17" case 1'1 case end @@ -129296,144 +129347,144 @@ module \dec22 end connect \opcode_switch \opcode_in [4:1] end -attribute \src "libresoc.v:80252.1-81823.10" +attribute \src "libresoc.v:80316.1-81887.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec30" attribute \generator "nMigen" module \dec30 - attribute \src "libresoc.v:81600.3-81636.6" + attribute \src "libresoc.v:81664.3-81700.6" wire width 2 $0\dec30_SV_Etype[1:0] - attribute \src "libresoc.v:81637.3-81673.6" + attribute \src "libresoc.v:81701.3-81737.6" wire width 2 $0\dec30_SV_Ptype[1:0] - attribute \src "libresoc.v:81156.3-81192.6" + attribute \src "libresoc.v:81220.3-81256.6" wire width 8 $0\dec30_asmcode[7:0] - attribute \src "libresoc.v:81304.3-81340.6" + attribute \src "libresoc.v:81368.3-81404.6" wire $0\dec30_br[0:0] - attribute \src "libresoc.v:80638.3-80674.6" + attribute \src "libresoc.v:80702.3-80738.6" wire width 3 $0\dec30_cr_in[2:0] - attribute \src "libresoc.v:80675.3-80711.6" + attribute \src "libresoc.v:80739.3-80775.6" wire width 3 $0\dec30_cr_out[2:0] - attribute \src "libresoc.v:81119.3-81155.6" + attribute \src "libresoc.v:81183.3-81219.6" wire width 2 $0\dec30_cry_in[1:0] - attribute \src "libresoc.v:81267.3-81303.6" + attribute \src "libresoc.v:81331.3-81367.6" wire $0\dec30_cry_out[0:0] - attribute \src "libresoc.v:81415.3-81451.6" + attribute \src "libresoc.v:81479.3-81515.6" wire width 5 $0\dec30_form[4:0] - attribute \src "libresoc.v:80601.3-80637.6" + attribute \src "libresoc.v:80665.3-80701.6" wire width 14 $0\dec30_function_unit[13:0] - attribute \src "libresoc.v:81674.3-81710.6" + attribute \src "libresoc.v:81738.3-81774.6" wire width 3 $0\dec30_in1_sel[2:0] - attribute \src "libresoc.v:81711.3-81747.6" + attribute \src "libresoc.v:81775.3-81811.6" wire width 4 $0\dec30_in2_sel[3:0] - attribute \src "libresoc.v:81748.3-81784.6" + attribute \src "libresoc.v:81812.3-81848.6" wire width 2 $0\dec30_in3_sel[1:0] - attribute \src "libresoc.v:81008.3-81044.6" + attribute \src "libresoc.v:81072.3-81108.6" wire width 7 $0\dec30_internal_op[6:0] - attribute \src "libresoc.v:81193.3-81229.6" + attribute \src "libresoc.v:81257.3-81293.6" wire $0\dec30_inv_a[0:0] - attribute \src "libresoc.v:81230.3-81266.6" + attribute \src "libresoc.v:81294.3-81330.6" wire $0\dec30_inv_out[0:0] - attribute \src "libresoc.v:81452.3-81488.6" + attribute \src "libresoc.v:81516.3-81552.6" wire $0\dec30_is_32b[0:0] - attribute \src "libresoc.v:80971.3-81007.6" + attribute \src "libresoc.v:81035.3-81071.6" wire width 4 $0\dec30_ldst_len[3:0] - attribute \src "libresoc.v:81526.3-81562.6" + attribute \src "libresoc.v:81590.3-81626.6" wire $0\dec30_lk[0:0] - attribute \src "libresoc.v:81785.3-81821.6" + attribute \src "libresoc.v:81849.3-81885.6" wire width 3 $0\dec30_out_sel[2:0] - attribute \src "libresoc.v:81082.3-81118.6" + attribute \src "libresoc.v:81146.3-81182.6" wire width 2 $0\dec30_rc_sel[1:0] - attribute \src "libresoc.v:81378.3-81414.6" + attribute \src "libresoc.v:81442.3-81478.6" wire $0\dec30_rsrv[0:0] - attribute \src "libresoc.v:81563.3-81599.6" + attribute \src "libresoc.v:81627.3-81663.6" wire $0\dec30_sgl_pipe[0:0] - attribute \src "libresoc.v:81489.3-81525.6" + attribute \src "libresoc.v:81553.3-81589.6" wire $0\dec30_sgn[0:0] - attribute \src "libresoc.v:81341.3-81377.6" + attribute \src "libresoc.v:81405.3-81441.6" wire $0\dec30_sgn_ext[0:0] - attribute \src "libresoc.v:80897.3-80933.6" + attribute \src "libresoc.v:80961.3-80997.6" wire width 3 $0\dec30_sv_cr_in[2:0] - attribute \src "libresoc.v:80934.3-80970.6" + attribute \src "libresoc.v:80998.3-81034.6" wire width 3 $0\dec30_sv_cr_out[2:0] - attribute \src "libresoc.v:80712.3-80748.6" + attribute \src "libresoc.v:80776.3-80812.6" wire width 3 $0\dec30_sv_in1[2:0] - attribute \src "libresoc.v:80749.3-80785.6" + attribute \src "libresoc.v:80813.3-80849.6" wire width 3 $0\dec30_sv_in2[2:0] - attribute \src "libresoc.v:80786.3-80822.6" + attribute \src "libresoc.v:80850.3-80886.6" wire width 3 $0\dec30_sv_in3[2:0] - attribute \src "libresoc.v:80860.3-80896.6" + attribute \src "libresoc.v:80924.3-80960.6" wire width 3 $0\dec30_sv_out2[2:0] - attribute \src "libresoc.v:80823.3-80859.6" + attribute \src "libresoc.v:80887.3-80923.6" wire width 3 $0\dec30_sv_out[2:0] - attribute \src "libresoc.v:81045.3-81081.6" + attribute \src "libresoc.v:81109.3-81145.6" wire width 2 $0\dec30_upd[1:0] - attribute \src "libresoc.v:80253.7-80253.20" + attribute \src "libresoc.v:80317.7-80317.20" wire $0\initial[0:0] - attribute \src "libresoc.v:81600.3-81636.6" + attribute \src "libresoc.v:81664.3-81700.6" wire width 2 $1\dec30_SV_Etype[1:0] - attribute \src "libresoc.v:81637.3-81673.6" + attribute \src "libresoc.v:81701.3-81737.6" wire width 2 $1\dec30_SV_Ptype[1:0] - attribute \src "libresoc.v:81156.3-81192.6" + attribute \src "libresoc.v:81220.3-81256.6" wire width 8 $1\dec30_asmcode[7:0] - attribute \src "libresoc.v:81304.3-81340.6" + attribute \src "libresoc.v:81368.3-81404.6" wire $1\dec30_br[0:0] - attribute \src "libresoc.v:80638.3-80674.6" + attribute \src "libresoc.v:80702.3-80738.6" wire width 3 $1\dec30_cr_in[2:0] - attribute \src "libresoc.v:80675.3-80711.6" + attribute \src "libresoc.v:80739.3-80775.6" wire width 3 $1\dec30_cr_out[2:0] - attribute \src "libresoc.v:81119.3-81155.6" + attribute \src "libresoc.v:81183.3-81219.6" wire width 2 $1\dec30_cry_in[1:0] - attribute \src "libresoc.v:81267.3-81303.6" + attribute \src "libresoc.v:81331.3-81367.6" wire $1\dec30_cry_out[0:0] - attribute \src "libresoc.v:81415.3-81451.6" + attribute \src "libresoc.v:81479.3-81515.6" wire width 5 $1\dec30_form[4:0] - attribute \src "libresoc.v:80601.3-80637.6" + attribute \src "libresoc.v:80665.3-80701.6" wire width 14 $1\dec30_function_unit[13:0] - attribute \src "libresoc.v:81674.3-81710.6" + attribute \src "libresoc.v:81738.3-81774.6" wire width 3 $1\dec30_in1_sel[2:0] - attribute \src "libresoc.v:81711.3-81747.6" + attribute \src "libresoc.v:81775.3-81811.6" wire width 4 $1\dec30_in2_sel[3:0] - attribute \src "libresoc.v:81748.3-81784.6" + attribute \src "libresoc.v:81812.3-81848.6" wire width 2 $1\dec30_in3_sel[1:0] - attribute \src "libresoc.v:81008.3-81044.6" + attribute \src "libresoc.v:81072.3-81108.6" wire width 7 $1\dec30_internal_op[6:0] - attribute \src "libresoc.v:81193.3-81229.6" + attribute \src "libresoc.v:81257.3-81293.6" wire $1\dec30_inv_a[0:0] - attribute \src "libresoc.v:81230.3-81266.6" + attribute \src "libresoc.v:81294.3-81330.6" wire $1\dec30_inv_out[0:0] - attribute \src "libresoc.v:81452.3-81488.6" + attribute \src "libresoc.v:81516.3-81552.6" wire $1\dec30_is_32b[0:0] - attribute \src "libresoc.v:80971.3-81007.6" + attribute \src "libresoc.v:81035.3-81071.6" wire width 4 $1\dec30_ldst_len[3:0] - attribute \src "libresoc.v:81526.3-81562.6" + attribute \src "libresoc.v:81590.3-81626.6" wire $1\dec30_lk[0:0] - attribute \src "libresoc.v:81785.3-81821.6" + attribute \src "libresoc.v:81849.3-81885.6" wire width 3 $1\dec30_out_sel[2:0] - attribute \src "libresoc.v:81082.3-81118.6" + attribute \src "libresoc.v:81146.3-81182.6" wire width 2 $1\dec30_rc_sel[1:0] - attribute \src "libresoc.v:81378.3-81414.6" + attribute \src "libresoc.v:81442.3-81478.6" wire $1\dec30_rsrv[0:0] - attribute \src "libresoc.v:81563.3-81599.6" + attribute \src "libresoc.v:81627.3-81663.6" wire $1\dec30_sgl_pipe[0:0] - attribute \src "libresoc.v:81489.3-81525.6" + attribute \src "libresoc.v:81553.3-81589.6" wire $1\dec30_sgn[0:0] - attribute \src "libresoc.v:81341.3-81377.6" + attribute \src "libresoc.v:81405.3-81441.6" wire $1\dec30_sgn_ext[0:0] - attribute \src "libresoc.v:80897.3-80933.6" + attribute \src "libresoc.v:80961.3-80997.6" wire width 3 $1\dec30_sv_cr_in[2:0] - attribute \src "libresoc.v:80934.3-80970.6" + attribute \src "libresoc.v:80998.3-81034.6" wire width 3 $1\dec30_sv_cr_out[2:0] - attribute \src "libresoc.v:80712.3-80748.6" + attribute \src "libresoc.v:80776.3-80812.6" wire width 3 $1\dec30_sv_in1[2:0] - attribute \src "libresoc.v:80749.3-80785.6" + attribute \src "libresoc.v:80813.3-80849.6" wire width 3 $1\dec30_sv_in2[2:0] - attribute \src "libresoc.v:80786.3-80822.6" + attribute \src "libresoc.v:80850.3-80886.6" wire width 3 $1\dec30_sv_in3[2:0] - attribute \src "libresoc.v:80860.3-80896.6" + attribute \src "libresoc.v:80924.3-80960.6" wire width 3 $1\dec30_sv_out2[2:0] - attribute \src "libresoc.v:80823.3-80859.6" + attribute \src "libresoc.v:80887.3-80923.6" wire width 3 $1\dec30_sv_out[2:0] - attribute \src "libresoc.v:81045.3-81081.6" + attribute \src "libresoc.v:81109.3-81145.6" wire width 2 $1\dec30_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -129745,28 +129796,28 @@ module \dec30 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec30_upd - attribute \src "libresoc.v:80253.7-80253.15" + attribute \src "libresoc.v:80317.7-80317.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 4 \opcode_switch - attribute \src "libresoc.v:80253.7-80253.20" - process $proc$libresoc.v:80253$3816 + attribute \src "libresoc.v:80317.7-80317.20" + process $proc$libresoc.v:80317$3816 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:80601.3-80637.6" - process $proc$libresoc.v:80601$3783 + attribute \src "libresoc.v:80665.3-80701.6" + process $proc$libresoc.v:80665$3783 assign { } { } assign { } { } assign $0\dec30_function_unit[13:0] $1\dec30_function_unit[13:0] - attribute \src "libresoc.v:80602.5-80602.29" + attribute \src "libresoc.v:80666.5-80666.29" switch \initial - attribute \src "libresoc.v:80602.9-80602.17" + attribute \src "libresoc.v:80666.9-80666.17" case 1'1 case end @@ -129818,14 +129869,14 @@ module \dec30 sync always update \dec30_function_unit $0\dec30_function_unit[13:0] end - attribute \src "libresoc.v:80638.3-80674.6" - process $proc$libresoc.v:80638$3784 + attribute \src "libresoc.v:80702.3-80738.6" + process $proc$libresoc.v:80702$3784 assign { } { } assign { } { } assign $0\dec30_cr_in[2:0] $1\dec30_cr_in[2:0] - attribute \src "libresoc.v:80639.5-80639.29" + attribute \src "libresoc.v:80703.5-80703.29" switch \initial - attribute \src "libresoc.v:80639.9-80639.17" + attribute \src "libresoc.v:80703.9-80703.17" case 1'1 case end @@ -129877,14 +129928,14 @@ module \dec30 sync always update \dec30_cr_in $0\dec30_cr_in[2:0] end - attribute \src "libresoc.v:80675.3-80711.6" - process $proc$libresoc.v:80675$3785 + attribute \src "libresoc.v:80739.3-80775.6" + process $proc$libresoc.v:80739$3785 assign { } { } assign { } { } assign $0\dec30_cr_out[2:0] $1\dec30_cr_out[2:0] - attribute \src "libresoc.v:80676.5-80676.29" + attribute \src "libresoc.v:80740.5-80740.29" switch \initial - attribute \src "libresoc.v:80676.9-80676.17" + attribute \src "libresoc.v:80740.9-80740.17" case 1'1 case end @@ -129936,14 +129987,14 @@ module \dec30 sync always update \dec30_cr_out $0\dec30_cr_out[2:0] end - attribute \src "libresoc.v:80712.3-80748.6" - process $proc$libresoc.v:80712$3786 + attribute \src "libresoc.v:80776.3-80812.6" + process $proc$libresoc.v:80776$3786 assign { } { } assign { } { } assign $0\dec30_sv_in1[2:0] $1\dec30_sv_in1[2:0] - attribute \src "libresoc.v:80713.5-80713.29" + attribute \src "libresoc.v:80777.5-80777.29" switch \initial - attribute \src "libresoc.v:80713.9-80713.17" + attribute \src "libresoc.v:80777.9-80777.17" case 1'1 case end @@ -129995,14 +130046,14 @@ module \dec30 sync always update \dec30_sv_in1 $0\dec30_sv_in1[2:0] end - attribute \src "libresoc.v:80749.3-80785.6" - process $proc$libresoc.v:80749$3787 + attribute \src "libresoc.v:80813.3-80849.6" + process $proc$libresoc.v:80813$3787 assign { } { } assign { } { } assign $0\dec30_sv_in2[2:0] $1\dec30_sv_in2[2:0] - attribute \src "libresoc.v:80750.5-80750.29" + attribute \src "libresoc.v:80814.5-80814.29" switch \initial - attribute \src "libresoc.v:80750.9-80750.17" + attribute \src "libresoc.v:80814.9-80814.17" case 1'1 case end @@ -130054,14 +130105,14 @@ module \dec30 sync always update \dec30_sv_in2 $0\dec30_sv_in2[2:0] end - attribute \src "libresoc.v:80786.3-80822.6" - process $proc$libresoc.v:80786$3788 + attribute \src "libresoc.v:80850.3-80886.6" + process $proc$libresoc.v:80850$3788 assign { } { } assign { } { } assign $0\dec30_sv_in3[2:0] $1\dec30_sv_in3[2:0] - attribute \src "libresoc.v:80787.5-80787.29" + attribute \src "libresoc.v:80851.5-80851.29" switch \initial - attribute \src "libresoc.v:80787.9-80787.17" + attribute \src "libresoc.v:80851.9-80851.17" case 1'1 case end @@ -130113,14 +130164,14 @@ module \dec30 sync always update \dec30_sv_in3 $0\dec30_sv_in3[2:0] end - attribute \src "libresoc.v:80823.3-80859.6" - process $proc$libresoc.v:80823$3789 + attribute \src "libresoc.v:80887.3-80923.6" + process $proc$libresoc.v:80887$3789 assign { } { } assign { } { } assign $0\dec30_sv_out[2:0] $1\dec30_sv_out[2:0] - attribute \src "libresoc.v:80824.5-80824.29" + attribute \src "libresoc.v:80888.5-80888.29" switch \initial - attribute \src "libresoc.v:80824.9-80824.17" + attribute \src "libresoc.v:80888.9-80888.17" case 1'1 case end @@ -130172,14 +130223,14 @@ module \dec30 sync always update \dec30_sv_out $0\dec30_sv_out[2:0] end - attribute \src "libresoc.v:80860.3-80896.6" - process $proc$libresoc.v:80860$3790 + attribute \src "libresoc.v:80924.3-80960.6" + process $proc$libresoc.v:80924$3790 assign { } { } assign { } { } assign $0\dec30_sv_out2[2:0] $1\dec30_sv_out2[2:0] - attribute \src "libresoc.v:80861.5-80861.29" + attribute \src "libresoc.v:80925.5-80925.29" switch \initial - attribute \src "libresoc.v:80861.9-80861.17" + attribute \src "libresoc.v:80925.9-80925.17" case 1'1 case end @@ -130231,14 +130282,14 @@ module \dec30 sync always update \dec30_sv_out2 $0\dec30_sv_out2[2:0] end - attribute \src "libresoc.v:80897.3-80933.6" - process $proc$libresoc.v:80897$3791 + attribute \src "libresoc.v:80961.3-80997.6" + process $proc$libresoc.v:80961$3791 assign { } { } assign { } { } assign $0\dec30_sv_cr_in[2:0] $1\dec30_sv_cr_in[2:0] - attribute \src "libresoc.v:80898.5-80898.29" + attribute \src "libresoc.v:80962.5-80962.29" switch \initial - attribute \src "libresoc.v:80898.9-80898.17" + attribute \src "libresoc.v:80962.9-80962.17" case 1'1 case end @@ -130290,14 +130341,14 @@ module \dec30 sync always update \dec30_sv_cr_in $0\dec30_sv_cr_in[2:0] end - attribute \src "libresoc.v:80934.3-80970.6" - process $proc$libresoc.v:80934$3792 + attribute \src "libresoc.v:80998.3-81034.6" + process $proc$libresoc.v:80998$3792 assign { } { } assign { } { } assign $0\dec30_sv_cr_out[2:0] $1\dec30_sv_cr_out[2:0] - attribute \src "libresoc.v:80935.5-80935.29" + attribute \src "libresoc.v:80999.5-80999.29" switch \initial - attribute \src "libresoc.v:80935.9-80935.17" + attribute \src "libresoc.v:80999.9-80999.17" case 1'1 case end @@ -130349,14 +130400,14 @@ module \dec30 sync always update \dec30_sv_cr_out $0\dec30_sv_cr_out[2:0] end - attribute \src "libresoc.v:80971.3-81007.6" - process $proc$libresoc.v:80971$3793 + attribute \src "libresoc.v:81035.3-81071.6" + process $proc$libresoc.v:81035$3793 assign { } { } assign { } { } assign $0\dec30_ldst_len[3:0] $1\dec30_ldst_len[3:0] - attribute \src "libresoc.v:80972.5-80972.29" + attribute \src "libresoc.v:81036.5-81036.29" switch \initial - attribute \src "libresoc.v:80972.9-80972.17" + attribute \src "libresoc.v:81036.9-81036.17" case 1'1 case end @@ -130408,14 +130459,14 @@ module \dec30 sync always update \dec30_ldst_len $0\dec30_ldst_len[3:0] end - attribute \src "libresoc.v:81008.3-81044.6" - process $proc$libresoc.v:81008$3794 + attribute \src "libresoc.v:81072.3-81108.6" + process $proc$libresoc.v:81072$3794 assign { } { } assign { } { } assign $0\dec30_internal_op[6:0] $1\dec30_internal_op[6:0] - attribute \src "libresoc.v:81009.5-81009.29" + attribute \src "libresoc.v:81073.5-81073.29" switch \initial - attribute \src "libresoc.v:81009.9-81009.17" + attribute \src "libresoc.v:81073.9-81073.17" case 1'1 case end @@ -130467,14 +130518,14 @@ module \dec30 sync always update \dec30_internal_op $0\dec30_internal_op[6:0] end - attribute \src "libresoc.v:81045.3-81081.6" - process $proc$libresoc.v:81045$3795 + attribute \src "libresoc.v:81109.3-81145.6" + process $proc$libresoc.v:81109$3795 assign { } { } assign { } { } assign $0\dec30_upd[1:0] $1\dec30_upd[1:0] - attribute \src "libresoc.v:81046.5-81046.29" + attribute \src "libresoc.v:81110.5-81110.29" switch \initial - attribute \src "libresoc.v:81046.9-81046.17" + attribute \src "libresoc.v:81110.9-81110.17" case 1'1 case end @@ -130526,14 +130577,14 @@ module \dec30 sync always update \dec30_upd $0\dec30_upd[1:0] end - attribute \src "libresoc.v:81082.3-81118.6" - process $proc$libresoc.v:81082$3796 + attribute \src "libresoc.v:81146.3-81182.6" + process $proc$libresoc.v:81146$3796 assign { } { } assign { } { } assign $0\dec30_rc_sel[1:0] $1\dec30_rc_sel[1:0] - attribute \src "libresoc.v:81083.5-81083.29" + attribute \src "libresoc.v:81147.5-81147.29" switch \initial - attribute \src "libresoc.v:81083.9-81083.17" + attribute \src "libresoc.v:81147.9-81147.17" case 1'1 case end @@ -130585,14 +130636,14 @@ module \dec30 sync always update \dec30_rc_sel $0\dec30_rc_sel[1:0] end - attribute \src "libresoc.v:81119.3-81155.6" - process $proc$libresoc.v:81119$3797 + attribute \src "libresoc.v:81183.3-81219.6" + process $proc$libresoc.v:81183$3797 assign { } { } assign { } { } assign $0\dec30_cry_in[1:0] $1\dec30_cry_in[1:0] - attribute \src "libresoc.v:81120.5-81120.29" + attribute \src "libresoc.v:81184.5-81184.29" switch \initial - attribute \src "libresoc.v:81120.9-81120.17" + attribute \src "libresoc.v:81184.9-81184.17" case 1'1 case end @@ -130644,14 +130695,14 @@ module \dec30 sync always update \dec30_cry_in $0\dec30_cry_in[1:0] end - attribute \src "libresoc.v:81156.3-81192.6" - process $proc$libresoc.v:81156$3798 + attribute \src "libresoc.v:81220.3-81256.6" + process $proc$libresoc.v:81220$3798 assign { } { } assign { } { } assign $0\dec30_asmcode[7:0] $1\dec30_asmcode[7:0] - attribute \src "libresoc.v:81157.5-81157.29" + attribute \src "libresoc.v:81221.5-81221.29" switch \initial - attribute \src "libresoc.v:81157.9-81157.17" + attribute \src "libresoc.v:81221.9-81221.17" case 1'1 case end @@ -130703,14 +130754,14 @@ module \dec30 sync always update \dec30_asmcode $0\dec30_asmcode[7:0] end - attribute \src "libresoc.v:81193.3-81229.6" - process $proc$libresoc.v:81193$3799 + attribute \src "libresoc.v:81257.3-81293.6" + process $proc$libresoc.v:81257$3799 assign { } { } assign { } { } assign $0\dec30_inv_a[0:0] $1\dec30_inv_a[0:0] - attribute \src "libresoc.v:81194.5-81194.29" + attribute \src "libresoc.v:81258.5-81258.29" switch \initial - attribute \src "libresoc.v:81194.9-81194.17" + attribute \src "libresoc.v:81258.9-81258.17" case 1'1 case end @@ -130762,14 +130813,14 @@ module \dec30 sync always update \dec30_inv_a $0\dec30_inv_a[0:0] end - attribute \src "libresoc.v:81230.3-81266.6" - process $proc$libresoc.v:81230$3800 + attribute \src "libresoc.v:81294.3-81330.6" + process $proc$libresoc.v:81294$3800 assign { } { } assign { } { } assign $0\dec30_inv_out[0:0] $1\dec30_inv_out[0:0] - attribute \src "libresoc.v:81231.5-81231.29" + attribute \src "libresoc.v:81295.5-81295.29" switch \initial - attribute \src "libresoc.v:81231.9-81231.17" + attribute \src "libresoc.v:81295.9-81295.17" case 1'1 case end @@ -130821,14 +130872,14 @@ module \dec30 sync always update \dec30_inv_out $0\dec30_inv_out[0:0] end - attribute \src "libresoc.v:81267.3-81303.6" - process $proc$libresoc.v:81267$3801 + attribute \src "libresoc.v:81331.3-81367.6" + process $proc$libresoc.v:81331$3801 assign { } { } assign { } { } assign $0\dec30_cry_out[0:0] $1\dec30_cry_out[0:0] - attribute \src "libresoc.v:81268.5-81268.29" + attribute \src "libresoc.v:81332.5-81332.29" switch \initial - attribute \src "libresoc.v:81268.9-81268.17" + attribute \src "libresoc.v:81332.9-81332.17" case 1'1 case end @@ -130880,14 +130931,14 @@ module \dec30 sync always update \dec30_cry_out $0\dec30_cry_out[0:0] end - attribute \src "libresoc.v:81304.3-81340.6" - process $proc$libresoc.v:81304$3802 + attribute \src "libresoc.v:81368.3-81404.6" + process $proc$libresoc.v:81368$3802 assign { } { } assign { } { } assign $0\dec30_br[0:0] $1\dec30_br[0:0] - attribute \src "libresoc.v:81305.5-81305.29" + attribute \src "libresoc.v:81369.5-81369.29" switch \initial - attribute \src "libresoc.v:81305.9-81305.17" + attribute \src "libresoc.v:81369.9-81369.17" case 1'1 case end @@ -130939,14 +130990,14 @@ module \dec30 sync always update \dec30_br $0\dec30_br[0:0] end - attribute \src "libresoc.v:81341.3-81377.6" - process $proc$libresoc.v:81341$3803 + attribute \src "libresoc.v:81405.3-81441.6" + process $proc$libresoc.v:81405$3803 assign { } { } assign { } { } assign $0\dec30_sgn_ext[0:0] $1\dec30_sgn_ext[0:0] - attribute \src "libresoc.v:81342.5-81342.29" + attribute \src "libresoc.v:81406.5-81406.29" switch \initial - attribute \src "libresoc.v:81342.9-81342.17" + attribute \src "libresoc.v:81406.9-81406.17" case 1'1 case end @@ -130998,14 +131049,14 @@ module \dec30 sync always update \dec30_sgn_ext $0\dec30_sgn_ext[0:0] end - attribute \src "libresoc.v:81378.3-81414.6" - process $proc$libresoc.v:81378$3804 + attribute \src "libresoc.v:81442.3-81478.6" + process $proc$libresoc.v:81442$3804 assign { } { } assign { } { } assign $0\dec30_rsrv[0:0] $1\dec30_rsrv[0:0] - attribute \src "libresoc.v:81379.5-81379.29" + attribute \src "libresoc.v:81443.5-81443.29" switch \initial - attribute \src "libresoc.v:81379.9-81379.17" + attribute \src "libresoc.v:81443.9-81443.17" case 1'1 case end @@ -131057,14 +131108,14 @@ module \dec30 sync always update \dec30_rsrv $0\dec30_rsrv[0:0] end - attribute \src "libresoc.v:81415.3-81451.6" - process $proc$libresoc.v:81415$3805 + attribute \src "libresoc.v:81479.3-81515.6" + process $proc$libresoc.v:81479$3805 assign { } { } assign { } { } assign $0\dec30_form[4:0] $1\dec30_form[4:0] - attribute \src "libresoc.v:81416.5-81416.29" + attribute \src "libresoc.v:81480.5-81480.29" switch \initial - attribute \src "libresoc.v:81416.9-81416.17" + attribute \src "libresoc.v:81480.9-81480.17" case 1'1 case end @@ -131116,14 +131167,14 @@ module \dec30 sync always update \dec30_form $0\dec30_form[4:0] end - attribute \src "libresoc.v:81452.3-81488.6" - process $proc$libresoc.v:81452$3806 + attribute \src "libresoc.v:81516.3-81552.6" + process $proc$libresoc.v:81516$3806 assign { } { } assign { } { } assign $0\dec30_is_32b[0:0] $1\dec30_is_32b[0:0] - attribute \src "libresoc.v:81453.5-81453.29" + attribute \src "libresoc.v:81517.5-81517.29" switch \initial - attribute \src "libresoc.v:81453.9-81453.17" + attribute \src "libresoc.v:81517.9-81517.17" case 1'1 case end @@ -131175,14 +131226,14 @@ module \dec30 sync always update \dec30_is_32b $0\dec30_is_32b[0:0] end - attribute \src "libresoc.v:81489.3-81525.6" - process $proc$libresoc.v:81489$3807 + attribute \src "libresoc.v:81553.3-81589.6" + process $proc$libresoc.v:81553$3807 assign { } { } assign { } { } assign $0\dec30_sgn[0:0] $1\dec30_sgn[0:0] - attribute \src "libresoc.v:81490.5-81490.29" + attribute \src "libresoc.v:81554.5-81554.29" switch \initial - attribute \src "libresoc.v:81490.9-81490.17" + attribute \src "libresoc.v:81554.9-81554.17" case 1'1 case end @@ -131234,14 +131285,14 @@ module \dec30 sync always update \dec30_sgn $0\dec30_sgn[0:0] end - attribute \src "libresoc.v:81526.3-81562.6" - process $proc$libresoc.v:81526$3808 + attribute \src "libresoc.v:81590.3-81626.6" + process $proc$libresoc.v:81590$3808 assign { } { } assign { } { } assign $0\dec30_lk[0:0] $1\dec30_lk[0:0] - attribute \src "libresoc.v:81527.5-81527.29" + attribute \src "libresoc.v:81591.5-81591.29" switch \initial - attribute \src "libresoc.v:81527.9-81527.17" + attribute \src "libresoc.v:81591.9-81591.17" case 1'1 case end @@ -131293,14 +131344,14 @@ module \dec30 sync always update \dec30_lk $0\dec30_lk[0:0] end - attribute \src "libresoc.v:81563.3-81599.6" - process $proc$libresoc.v:81563$3809 + attribute \src "libresoc.v:81627.3-81663.6" + process $proc$libresoc.v:81627$3809 assign { } { } assign { } { } assign $0\dec30_sgl_pipe[0:0] $1\dec30_sgl_pipe[0:0] - attribute \src "libresoc.v:81564.5-81564.29" + attribute \src "libresoc.v:81628.5-81628.29" switch \initial - attribute \src "libresoc.v:81564.9-81564.17" + attribute \src "libresoc.v:81628.9-81628.17" case 1'1 case end @@ -131352,14 +131403,14 @@ module \dec30 sync always update \dec30_sgl_pipe $0\dec30_sgl_pipe[0:0] end - attribute \src "libresoc.v:81600.3-81636.6" - process $proc$libresoc.v:81600$3810 + attribute \src "libresoc.v:81664.3-81700.6" + process $proc$libresoc.v:81664$3810 assign { } { } assign { } { } assign $0\dec30_SV_Etype[1:0] $1\dec30_SV_Etype[1:0] - attribute \src "libresoc.v:81601.5-81601.29" + attribute \src "libresoc.v:81665.5-81665.29" switch \initial - attribute \src "libresoc.v:81601.9-81601.17" + attribute \src "libresoc.v:81665.9-81665.17" case 1'1 case end @@ -131411,14 +131462,14 @@ module \dec30 sync always update \dec30_SV_Etype $0\dec30_SV_Etype[1:0] end - attribute \src "libresoc.v:81637.3-81673.6" - process $proc$libresoc.v:81637$3811 + attribute \src "libresoc.v:81701.3-81737.6" + process $proc$libresoc.v:81701$3811 assign { } { } assign { } { } assign $0\dec30_SV_Ptype[1:0] $1\dec30_SV_Ptype[1:0] - attribute \src "libresoc.v:81638.5-81638.29" + attribute \src "libresoc.v:81702.5-81702.29" switch \initial - attribute \src "libresoc.v:81638.9-81638.17" + attribute \src "libresoc.v:81702.9-81702.17" case 1'1 case end @@ -131470,14 +131521,14 @@ module \dec30 sync always update \dec30_SV_Ptype $0\dec30_SV_Ptype[1:0] end - attribute \src "libresoc.v:81674.3-81710.6" - process $proc$libresoc.v:81674$3812 + attribute \src "libresoc.v:81738.3-81774.6" + process $proc$libresoc.v:81738$3812 assign { } { } assign { } { } assign $0\dec30_in1_sel[2:0] $1\dec30_in1_sel[2:0] - attribute \src "libresoc.v:81675.5-81675.29" + attribute \src "libresoc.v:81739.5-81739.29" switch \initial - attribute \src "libresoc.v:81675.9-81675.17" + attribute \src "libresoc.v:81739.9-81739.17" case 1'1 case end @@ -131529,14 +131580,14 @@ module \dec30 sync always update \dec30_in1_sel $0\dec30_in1_sel[2:0] end - attribute \src "libresoc.v:81711.3-81747.6" - process $proc$libresoc.v:81711$3813 + attribute \src "libresoc.v:81775.3-81811.6" + process $proc$libresoc.v:81775$3813 assign { } { } assign { } { } assign $0\dec30_in2_sel[3:0] $1\dec30_in2_sel[3:0] - attribute \src "libresoc.v:81712.5-81712.29" + attribute \src "libresoc.v:81776.5-81776.29" switch \initial - attribute \src "libresoc.v:81712.9-81712.17" + attribute \src "libresoc.v:81776.9-81776.17" case 1'1 case end @@ -131588,14 +131639,14 @@ module \dec30 sync always update \dec30_in2_sel $0\dec30_in2_sel[3:0] end - attribute \src "libresoc.v:81748.3-81784.6" - process $proc$libresoc.v:81748$3814 + attribute \src "libresoc.v:81812.3-81848.6" + process $proc$libresoc.v:81812$3814 assign { } { } assign { } { } assign $0\dec30_in3_sel[1:0] $1\dec30_in3_sel[1:0] - attribute \src "libresoc.v:81749.5-81749.29" + attribute \src "libresoc.v:81813.5-81813.29" switch \initial - attribute \src "libresoc.v:81749.9-81749.17" + attribute \src "libresoc.v:81813.9-81813.17" case 1'1 case end @@ -131647,14 +131698,14 @@ module \dec30 sync always update \dec30_in3_sel $0\dec30_in3_sel[1:0] end - attribute \src "libresoc.v:81785.3-81821.6" - process $proc$libresoc.v:81785$3815 + attribute \src "libresoc.v:81849.3-81885.6" + process $proc$libresoc.v:81849$3815 assign { } { } assign { } { } assign $0\dec30_out_sel[2:0] $1\dec30_out_sel[2:0] - attribute \src "libresoc.v:81786.5-81786.29" + attribute \src "libresoc.v:81850.5-81850.29" switch \initial - attribute \src "libresoc.v:81786.9-81786.17" + attribute \src "libresoc.v:81850.9-81850.17" case 1'1 case end @@ -131708,144 +131759,144 @@ module \dec30 end connect \opcode_switch \opcode_in [4:1] end -attribute \src "libresoc.v:81827.1-90475.10" +attribute \src "libresoc.v:81891.1-90539.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31" attribute \generator "nMigen" module \dec31 - attribute \src "libresoc.v:88686.3-88746.6" + attribute \src "libresoc.v:88750.3-88810.6" wire width 2 $0\dec31_SV_Etype[1:0] - attribute \src "libresoc.v:88747.3-88807.6" + attribute \src "libresoc.v:88811.3-88871.6" wire width 2 $0\dec31_SV_Ptype[1:0] - attribute \src "libresoc.v:88625.3-88685.6" + attribute \src "libresoc.v:88689.3-88749.6" wire width 8 $0\dec31_asmcode[7:0] - attribute \src "libresoc.v:90028.3-90088.6" + attribute \src "libresoc.v:90092.3-90152.6" wire $0\dec31_br[0:0] - attribute \src "libresoc.v:89052.3-89112.6" + attribute \src "libresoc.v:89116.3-89176.6" wire width 3 $0\dec31_cr_in[2:0] - attribute \src "libresoc.v:89113.3-89173.6" + attribute \src "libresoc.v:89177.3-89237.6" wire width 3 $0\dec31_cr_out[2:0] - attribute \src "libresoc.v:89784.3-89844.6" + attribute \src "libresoc.v:89848.3-89908.6" wire width 2 $0\dec31_cry_in[1:0] - attribute \src "libresoc.v:89967.3-90027.6" + attribute \src "libresoc.v:90031.3-90091.6" wire $0\dec31_cry_out[0:0] - attribute \src "libresoc.v:88564.3-88624.6" + attribute \src "libresoc.v:88628.3-88688.6" wire width 5 $0\dec31_form[4:0] - attribute \src "libresoc.v:88442.3-88502.6" + attribute \src "libresoc.v:88506.3-88566.6" wire width 14 $0\dec31_function_unit[13:0] - attribute \src "libresoc.v:88808.3-88868.6" + attribute \src "libresoc.v:88872.3-88932.6" wire width 3 $0\dec31_in1_sel[2:0] - attribute \src "libresoc.v:88869.3-88929.6" + attribute \src "libresoc.v:88933.3-88993.6" wire width 4 $0\dec31_in2_sel[3:0] - attribute \src "libresoc.v:88930.3-88990.6" + attribute \src "libresoc.v:88994.3-89054.6" wire width 2 $0\dec31_in3_sel[1:0] - attribute \src "libresoc.v:88503.3-88563.6" + attribute \src "libresoc.v:88567.3-88627.6" wire width 7 $0\dec31_internal_op[6:0] - attribute \src "libresoc.v:89845.3-89905.6" + attribute \src "libresoc.v:89909.3-89969.6" wire $0\dec31_inv_a[0:0] - attribute \src "libresoc.v:89906.3-89966.6" + attribute \src "libresoc.v:89970.3-90030.6" wire $0\dec31_inv_out[0:0] - attribute \src "libresoc.v:90211.3-90271.6" + attribute \src "libresoc.v:90275.3-90335.6" wire $0\dec31_is_32b[0:0] - attribute \src "libresoc.v:89601.3-89661.6" + attribute \src "libresoc.v:89665.3-89725.6" wire width 4 $0\dec31_ldst_len[3:0] - attribute \src "libresoc.v:90333.3-90393.6" + attribute \src "libresoc.v:90397.3-90457.6" wire $0\dec31_lk[0:0] - attribute \src "libresoc.v:88991.3-89051.6" + attribute \src "libresoc.v:89055.3-89115.6" wire width 3 $0\dec31_out_sel[2:0] - attribute \src "libresoc.v:89723.3-89783.6" + attribute \src "libresoc.v:89787.3-89847.6" wire width 2 $0\dec31_rc_sel[1:0] - attribute \src "libresoc.v:90150.3-90210.6" + attribute \src "libresoc.v:90214.3-90274.6" wire $0\dec31_rsrv[0:0] - attribute \src "libresoc.v:90394.3-90454.6" + attribute \src "libresoc.v:90458.3-90518.6" wire $0\dec31_sgl_pipe[0:0] - attribute \src "libresoc.v:90272.3-90332.6" + attribute \src "libresoc.v:90336.3-90396.6" wire $0\dec31_sgn[0:0] - attribute \src "libresoc.v:90089.3-90149.6" + attribute \src "libresoc.v:90153.3-90213.6" wire $0\dec31_sgn_ext[0:0] - attribute \src "libresoc.v:89479.3-89539.6" + attribute \src "libresoc.v:89543.3-89603.6" wire width 3 $0\dec31_sv_cr_in[2:0] - attribute \src "libresoc.v:89540.3-89600.6" + attribute \src "libresoc.v:89604.3-89664.6" wire width 3 $0\dec31_sv_cr_out[2:0] - attribute \src "libresoc.v:89174.3-89234.6" + attribute \src "libresoc.v:89238.3-89298.6" wire width 3 $0\dec31_sv_in1[2:0] - attribute \src "libresoc.v:89235.3-89295.6" + attribute \src "libresoc.v:89299.3-89359.6" wire width 3 $0\dec31_sv_in2[2:0] - attribute \src "libresoc.v:89296.3-89356.6" + attribute \src "libresoc.v:89360.3-89420.6" wire width 3 $0\dec31_sv_in3[2:0] - attribute \src "libresoc.v:89418.3-89478.6" + attribute \src "libresoc.v:89482.3-89542.6" wire width 3 $0\dec31_sv_out2[2:0] - attribute \src "libresoc.v:89357.3-89417.6" + attribute \src "libresoc.v:89421.3-89481.6" wire width 3 $0\dec31_sv_out[2:0] - attribute \src "libresoc.v:89662.3-89722.6" + attribute \src "libresoc.v:89726.3-89786.6" wire width 2 $0\dec31_upd[1:0] - attribute \src "libresoc.v:81828.7-81828.20" + attribute \src "libresoc.v:81892.7-81892.20" wire $0\initial[0:0] - attribute \src "libresoc.v:88686.3-88746.6" + attribute \src "libresoc.v:88750.3-88810.6" wire width 2 $1\dec31_SV_Etype[1:0] - attribute \src "libresoc.v:88747.3-88807.6" + attribute \src "libresoc.v:88811.3-88871.6" wire width 2 $1\dec31_SV_Ptype[1:0] - attribute \src "libresoc.v:88625.3-88685.6" + attribute \src "libresoc.v:88689.3-88749.6" wire width 8 $1\dec31_asmcode[7:0] - attribute \src "libresoc.v:90028.3-90088.6" + attribute \src "libresoc.v:90092.3-90152.6" wire $1\dec31_br[0:0] - attribute \src "libresoc.v:89052.3-89112.6" + attribute \src "libresoc.v:89116.3-89176.6" wire width 3 $1\dec31_cr_in[2:0] - attribute \src "libresoc.v:89113.3-89173.6" + attribute \src "libresoc.v:89177.3-89237.6" wire width 3 $1\dec31_cr_out[2:0] - attribute \src "libresoc.v:89784.3-89844.6" + attribute \src "libresoc.v:89848.3-89908.6" wire width 2 $1\dec31_cry_in[1:0] - attribute \src "libresoc.v:89967.3-90027.6" + attribute \src "libresoc.v:90031.3-90091.6" wire $1\dec31_cry_out[0:0] - attribute \src "libresoc.v:88564.3-88624.6" + attribute \src "libresoc.v:88628.3-88688.6" wire width 5 $1\dec31_form[4:0] - attribute \src "libresoc.v:88442.3-88502.6" + attribute \src "libresoc.v:88506.3-88566.6" wire width 14 $1\dec31_function_unit[13:0] - attribute \src "libresoc.v:88808.3-88868.6" + attribute \src "libresoc.v:88872.3-88932.6" wire width 3 $1\dec31_in1_sel[2:0] - attribute \src "libresoc.v:88869.3-88929.6" + attribute \src "libresoc.v:88933.3-88993.6" wire width 4 $1\dec31_in2_sel[3:0] - attribute \src "libresoc.v:88930.3-88990.6" + attribute \src "libresoc.v:88994.3-89054.6" wire width 2 $1\dec31_in3_sel[1:0] - attribute \src "libresoc.v:88503.3-88563.6" + attribute \src "libresoc.v:88567.3-88627.6" wire width 7 $1\dec31_internal_op[6:0] - attribute \src "libresoc.v:89845.3-89905.6" + attribute \src "libresoc.v:89909.3-89969.6" wire $1\dec31_inv_a[0:0] - attribute \src "libresoc.v:89906.3-89966.6" + attribute \src "libresoc.v:89970.3-90030.6" wire $1\dec31_inv_out[0:0] - attribute \src "libresoc.v:90211.3-90271.6" + attribute \src "libresoc.v:90275.3-90335.6" wire $1\dec31_is_32b[0:0] - attribute \src "libresoc.v:89601.3-89661.6" + attribute \src "libresoc.v:89665.3-89725.6" wire width 4 $1\dec31_ldst_len[3:0] - attribute \src "libresoc.v:90333.3-90393.6" + attribute \src "libresoc.v:90397.3-90457.6" wire $1\dec31_lk[0:0] - attribute \src "libresoc.v:88991.3-89051.6" + attribute \src "libresoc.v:89055.3-89115.6" wire width 3 $1\dec31_out_sel[2:0] - attribute \src "libresoc.v:89723.3-89783.6" + attribute \src "libresoc.v:89787.3-89847.6" wire width 2 $1\dec31_rc_sel[1:0] - attribute \src "libresoc.v:90150.3-90210.6" + attribute \src "libresoc.v:90214.3-90274.6" wire $1\dec31_rsrv[0:0] - attribute \src "libresoc.v:90394.3-90454.6" + attribute \src "libresoc.v:90458.3-90518.6" wire $1\dec31_sgl_pipe[0:0] - attribute \src "libresoc.v:90272.3-90332.6" + attribute \src "libresoc.v:90336.3-90396.6" wire $1\dec31_sgn[0:0] - attribute \src "libresoc.v:90089.3-90149.6" + attribute \src "libresoc.v:90153.3-90213.6" wire $1\dec31_sgn_ext[0:0] - attribute \src "libresoc.v:89479.3-89539.6" + attribute \src "libresoc.v:89543.3-89603.6" wire width 3 $1\dec31_sv_cr_in[2:0] - attribute \src "libresoc.v:89540.3-89600.6" + attribute \src "libresoc.v:89604.3-89664.6" wire width 3 $1\dec31_sv_cr_out[2:0] - attribute \src "libresoc.v:89174.3-89234.6" + attribute \src "libresoc.v:89238.3-89298.6" wire width 3 $1\dec31_sv_in1[2:0] - attribute \src "libresoc.v:89235.3-89295.6" + attribute \src "libresoc.v:89299.3-89359.6" wire width 3 $1\dec31_sv_in2[2:0] - attribute \src "libresoc.v:89296.3-89356.6" + attribute \src "libresoc.v:89360.3-89420.6" wire width 3 $1\dec31_sv_in3[2:0] - attribute \src "libresoc.v:89418.3-89478.6" + attribute \src "libresoc.v:89482.3-89542.6" wire width 3 $1\dec31_sv_out2[2:0] - attribute \src "libresoc.v:89357.3-89417.6" + attribute \src "libresoc.v:89421.3-89481.6" wire width 3 $1\dec31_sv_out[2:0] - attribute \src "libresoc.v:89662.3-89722.6" + attribute \src "libresoc.v:89726.3-89786.6" wire width 2 $1\dec31_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -137773,7 +137824,7 @@ module \dec31 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_upd - attribute \src "libresoc.v:81828.7-81828.15" + attribute \src "libresoc.v:81892.7-81892.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:349" wire width 5 \opc_in @@ -137782,7 +137833,7 @@ module \dec31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 10 \opcode_switch attribute \module_not_derived 1 - attribute \src "libresoc.v:87794.18-87829.4" + attribute \src "libresoc.v:87858.18-87893.4" cell \dec31_dec_sub0 \dec31_dec_sub0 connect \dec31_dec_sub0_SV_Etype \dec31_dec_sub0_dec31_dec_sub0_SV_Etype connect \dec31_dec_sub0_SV_Ptype \dec31_dec_sub0_dec31_dec_sub0_SV_Ptype @@ -137820,7 +137871,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub0_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87830.19-87865.4" + attribute \src "libresoc.v:87894.19-87929.4" cell \dec31_dec_sub10 \dec31_dec_sub10 connect \dec31_dec_sub10_SV_Etype \dec31_dec_sub10_dec31_dec_sub10_SV_Etype connect \dec31_dec_sub10_SV_Ptype \dec31_dec_sub10_dec31_dec_sub10_SV_Ptype @@ -137858,7 +137909,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub10_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87866.19-87901.4" + attribute \src "libresoc.v:87930.19-87965.4" cell \dec31_dec_sub11 \dec31_dec_sub11 connect \dec31_dec_sub11_SV_Etype \dec31_dec_sub11_dec31_dec_sub11_SV_Etype connect \dec31_dec_sub11_SV_Ptype \dec31_dec_sub11_dec31_dec_sub11_SV_Ptype @@ -137896,7 +137947,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub11_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87902.19-87937.4" + attribute \src "libresoc.v:87966.19-88001.4" cell \dec31_dec_sub15 \dec31_dec_sub15 connect \dec31_dec_sub15_SV_Etype \dec31_dec_sub15_dec31_dec_sub15_SV_Etype connect \dec31_dec_sub15_SV_Ptype \dec31_dec_sub15_dec31_dec_sub15_SV_Ptype @@ -137934,7 +137985,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub15_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87938.19-87973.4" + attribute \src "libresoc.v:88002.19-88037.4" cell \dec31_dec_sub16 \dec31_dec_sub16 connect \dec31_dec_sub16_SV_Etype \dec31_dec_sub16_dec31_dec_sub16_SV_Etype connect \dec31_dec_sub16_SV_Ptype \dec31_dec_sub16_dec31_dec_sub16_SV_Ptype @@ -137972,7 +138023,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub16_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:87974.19-88009.4" + attribute \src "libresoc.v:88038.19-88073.4" cell \dec31_dec_sub18 \dec31_dec_sub18 connect \dec31_dec_sub18_SV_Etype \dec31_dec_sub18_dec31_dec_sub18_SV_Etype connect \dec31_dec_sub18_SV_Ptype \dec31_dec_sub18_dec31_dec_sub18_SV_Ptype @@ -138010,7 +138061,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub18_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:88010.19-88045.4" + attribute \src "libresoc.v:88074.19-88109.4" cell \dec31_dec_sub19 \dec31_dec_sub19 connect \dec31_dec_sub19_SV_Etype \dec31_dec_sub19_dec31_dec_sub19_SV_Etype connect \dec31_dec_sub19_SV_Ptype \dec31_dec_sub19_dec31_dec_sub19_SV_Ptype @@ -138048,7 +138099,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub19_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:88046.19-88081.4" + attribute \src "libresoc.v:88110.19-88145.4" cell \dec31_dec_sub20 \dec31_dec_sub20 connect \dec31_dec_sub20_SV_Etype \dec31_dec_sub20_dec31_dec_sub20_SV_Etype connect \dec31_dec_sub20_SV_Ptype \dec31_dec_sub20_dec31_dec_sub20_SV_Ptype @@ -138086,7 +138137,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub20_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:88082.19-88117.4" + attribute \src "libresoc.v:88146.19-88181.4" cell \dec31_dec_sub21 \dec31_dec_sub21 connect \dec31_dec_sub21_SV_Etype \dec31_dec_sub21_dec31_dec_sub21_SV_Etype connect \dec31_dec_sub21_SV_Ptype \dec31_dec_sub21_dec31_dec_sub21_SV_Ptype @@ -138124,7 +138175,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub21_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:88118.19-88153.4" + attribute \src "libresoc.v:88182.19-88217.4" cell \dec31_dec_sub22 \dec31_dec_sub22 connect \dec31_dec_sub22_SV_Etype \dec31_dec_sub22_dec31_dec_sub22_SV_Etype connect \dec31_dec_sub22_SV_Ptype \dec31_dec_sub22_dec31_dec_sub22_SV_Ptype @@ -138162,7 +138213,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub22_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:88154.19-88189.4" + attribute \src "libresoc.v:88218.19-88253.4" cell \dec31_dec_sub23 \dec31_dec_sub23 connect \dec31_dec_sub23_SV_Etype \dec31_dec_sub23_dec31_dec_sub23_SV_Etype connect \dec31_dec_sub23_SV_Ptype \dec31_dec_sub23_dec31_dec_sub23_SV_Ptype @@ -138200,7 +138251,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub23_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:88190.19-88225.4" + attribute \src "libresoc.v:88254.19-88289.4" cell \dec31_dec_sub24 \dec31_dec_sub24 connect \dec31_dec_sub24_SV_Etype \dec31_dec_sub24_dec31_dec_sub24_SV_Etype connect \dec31_dec_sub24_SV_Ptype \dec31_dec_sub24_dec31_dec_sub24_SV_Ptype @@ -138238,7 +138289,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub24_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:88226.19-88261.4" + attribute \src "libresoc.v:88290.19-88325.4" cell \dec31_dec_sub26 \dec31_dec_sub26 connect \dec31_dec_sub26_SV_Etype \dec31_dec_sub26_dec31_dec_sub26_SV_Etype connect \dec31_dec_sub26_SV_Ptype \dec31_dec_sub26_dec31_dec_sub26_SV_Ptype @@ -138276,7 +138327,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub26_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:88262.19-88297.4" + attribute \src "libresoc.v:88326.19-88361.4" cell \dec31_dec_sub27 \dec31_dec_sub27 connect \dec31_dec_sub27_SV_Etype \dec31_dec_sub27_dec31_dec_sub27_SV_Etype connect \dec31_dec_sub27_SV_Ptype \dec31_dec_sub27_dec31_dec_sub27_SV_Ptype @@ -138314,7 +138365,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub27_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:88298.19-88333.4" + attribute \src "libresoc.v:88362.19-88397.4" cell \dec31_dec_sub28 \dec31_dec_sub28 connect \dec31_dec_sub28_SV_Etype \dec31_dec_sub28_dec31_dec_sub28_SV_Etype connect \dec31_dec_sub28_SV_Ptype \dec31_dec_sub28_dec31_dec_sub28_SV_Ptype @@ -138352,7 +138403,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub28_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:88334.18-88369.4" + attribute \src "libresoc.v:88398.18-88433.4" cell \dec31_dec_sub4 \dec31_dec_sub4 connect \dec31_dec_sub4_SV_Etype \dec31_dec_sub4_dec31_dec_sub4_SV_Etype connect \dec31_dec_sub4_SV_Ptype \dec31_dec_sub4_dec31_dec_sub4_SV_Ptype @@ -138390,7 +138441,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub4_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:88370.18-88405.4" + attribute \src "libresoc.v:88434.18-88469.4" cell \dec31_dec_sub8 \dec31_dec_sub8 connect \dec31_dec_sub8_SV_Etype \dec31_dec_sub8_dec31_dec_sub8_SV_Etype connect \dec31_dec_sub8_SV_Ptype \dec31_dec_sub8_dec31_dec_sub8_SV_Ptype @@ -138428,7 +138479,7 @@ module \dec31 connect \opcode_in \dec31_dec_sub8_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:88406.18-88441.4" + attribute \src "libresoc.v:88470.18-88505.4" cell \dec31_dec_sub9 \dec31_dec_sub9 connect \dec31_dec_sub9_SV_Etype \dec31_dec_sub9_dec31_dec_sub9_SV_Etype connect \dec31_dec_sub9_SV_Ptype \dec31_dec_sub9_dec31_dec_sub9_SV_Ptype @@ -138465,22 +138516,22 @@ module \dec31 connect \dec31_dec_sub9_upd \dec31_dec_sub9_dec31_dec_sub9_upd connect \opcode_in \dec31_dec_sub9_opcode_in end - attribute \src "libresoc.v:81828.7-81828.20" - process $proc$libresoc.v:81828$3850 + attribute \src "libresoc.v:81892.7-81892.20" + process $proc$libresoc.v:81892$3850 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:88442.3-88502.6" - process $proc$libresoc.v:88442$3817 + attribute \src "libresoc.v:88506.3-88566.6" + process $proc$libresoc.v:88506$3817 assign { } { } assign { } { } assign $0\dec31_function_unit[13:0] $1\dec31_function_unit[13:0] - attribute \src "libresoc.v:88443.5-88443.29" + attribute \src "libresoc.v:88507.5-88507.29" switch \initial - attribute \src "libresoc.v:88443.9-88443.17" + attribute \src "libresoc.v:88507.9-88507.17" case 1'1 case end @@ -138564,14 +138615,14 @@ module \dec31 sync always update \dec31_function_unit $0\dec31_function_unit[13:0] end - attribute \src "libresoc.v:88503.3-88563.6" - process $proc$libresoc.v:88503$3818 + attribute \src "libresoc.v:88567.3-88627.6" + process $proc$libresoc.v:88567$3818 assign { } { } assign { } { } assign $0\dec31_internal_op[6:0] $1\dec31_internal_op[6:0] - attribute \src "libresoc.v:88504.5-88504.29" + attribute \src "libresoc.v:88568.5-88568.29" switch \initial - attribute \src "libresoc.v:88504.9-88504.17" + attribute \src "libresoc.v:88568.9-88568.17" case 1'1 case end @@ -138655,14 +138706,14 @@ module \dec31 sync always update \dec31_internal_op $0\dec31_internal_op[6:0] end - attribute \src "libresoc.v:88564.3-88624.6" - process $proc$libresoc.v:88564$3819 + attribute \src "libresoc.v:88628.3-88688.6" + process $proc$libresoc.v:88628$3819 assign { } { } assign { } { } assign $0\dec31_form[4:0] $1\dec31_form[4:0] - attribute \src "libresoc.v:88565.5-88565.29" + attribute \src "libresoc.v:88629.5-88629.29" switch \initial - attribute \src "libresoc.v:88565.9-88565.17" + attribute \src "libresoc.v:88629.9-88629.17" case 1'1 case end @@ -138746,14 +138797,14 @@ module \dec31 sync always update \dec31_form $0\dec31_form[4:0] end - attribute \src "libresoc.v:88625.3-88685.6" - process $proc$libresoc.v:88625$3820 + attribute \src "libresoc.v:88689.3-88749.6" + process $proc$libresoc.v:88689$3820 assign { } { } assign { } { } assign $0\dec31_asmcode[7:0] $1\dec31_asmcode[7:0] - attribute \src "libresoc.v:88626.5-88626.29" + attribute \src "libresoc.v:88690.5-88690.29" switch \initial - attribute \src "libresoc.v:88626.9-88626.17" + attribute \src "libresoc.v:88690.9-88690.17" case 1'1 case end @@ -138837,14 +138888,14 @@ module \dec31 sync always update \dec31_asmcode $0\dec31_asmcode[7:0] end - attribute \src "libresoc.v:88686.3-88746.6" - process $proc$libresoc.v:88686$3821 + attribute \src "libresoc.v:88750.3-88810.6" + process $proc$libresoc.v:88750$3821 assign { } { } assign { } { } assign $0\dec31_SV_Etype[1:0] $1\dec31_SV_Etype[1:0] - attribute \src "libresoc.v:88687.5-88687.29" + attribute \src "libresoc.v:88751.5-88751.29" switch \initial - attribute \src "libresoc.v:88687.9-88687.17" + attribute \src "libresoc.v:88751.9-88751.17" case 1'1 case end @@ -138928,14 +138979,14 @@ module \dec31 sync always update \dec31_SV_Etype $0\dec31_SV_Etype[1:0] end - attribute \src "libresoc.v:88747.3-88807.6" - process $proc$libresoc.v:88747$3822 + attribute \src "libresoc.v:88811.3-88871.6" + process $proc$libresoc.v:88811$3822 assign { } { } assign { } { } assign $0\dec31_SV_Ptype[1:0] $1\dec31_SV_Ptype[1:0] - attribute \src "libresoc.v:88748.5-88748.29" + attribute \src "libresoc.v:88812.5-88812.29" switch \initial - attribute \src "libresoc.v:88748.9-88748.17" + attribute \src "libresoc.v:88812.9-88812.17" case 1'1 case end @@ -139019,14 +139070,14 @@ module \dec31 sync always update \dec31_SV_Ptype $0\dec31_SV_Ptype[1:0] end - attribute \src "libresoc.v:88808.3-88868.6" - process $proc$libresoc.v:88808$3823 + attribute \src "libresoc.v:88872.3-88932.6" + process $proc$libresoc.v:88872$3823 assign { } { } assign { } { } assign $0\dec31_in1_sel[2:0] $1\dec31_in1_sel[2:0] - attribute \src "libresoc.v:88809.5-88809.29" + attribute \src "libresoc.v:88873.5-88873.29" switch \initial - attribute \src "libresoc.v:88809.9-88809.17" + attribute \src "libresoc.v:88873.9-88873.17" case 1'1 case end @@ -139110,14 +139161,14 @@ module \dec31 sync always update \dec31_in1_sel $0\dec31_in1_sel[2:0] end - attribute \src "libresoc.v:88869.3-88929.6" - process $proc$libresoc.v:88869$3824 + attribute \src "libresoc.v:88933.3-88993.6" + process $proc$libresoc.v:88933$3824 assign { } { } assign { } { } assign $0\dec31_in2_sel[3:0] $1\dec31_in2_sel[3:0] - attribute \src "libresoc.v:88870.5-88870.29" + attribute \src "libresoc.v:88934.5-88934.29" switch \initial - attribute \src "libresoc.v:88870.9-88870.17" + attribute \src "libresoc.v:88934.9-88934.17" case 1'1 case end @@ -139201,14 +139252,14 @@ module \dec31 sync always update \dec31_in2_sel $0\dec31_in2_sel[3:0] end - attribute \src "libresoc.v:88930.3-88990.6" - process $proc$libresoc.v:88930$3825 + attribute \src "libresoc.v:88994.3-89054.6" + process $proc$libresoc.v:88994$3825 assign { } { } assign { } { } assign $0\dec31_in3_sel[1:0] $1\dec31_in3_sel[1:0] - attribute \src "libresoc.v:88931.5-88931.29" + attribute \src "libresoc.v:88995.5-88995.29" switch \initial - attribute \src "libresoc.v:88931.9-88931.17" + attribute \src "libresoc.v:88995.9-88995.17" case 1'1 case end @@ -139292,14 +139343,14 @@ module \dec31 sync always update \dec31_in3_sel $0\dec31_in3_sel[1:0] end - attribute \src "libresoc.v:88991.3-89051.6" - process $proc$libresoc.v:88991$3826 + attribute \src "libresoc.v:89055.3-89115.6" + process $proc$libresoc.v:89055$3826 assign { } { } assign { } { } assign $0\dec31_out_sel[2:0] $1\dec31_out_sel[2:0] - attribute \src "libresoc.v:88992.5-88992.29" + attribute \src "libresoc.v:89056.5-89056.29" switch \initial - attribute \src "libresoc.v:88992.9-88992.17" + attribute \src "libresoc.v:89056.9-89056.17" case 1'1 case end @@ -139383,14 +139434,14 @@ module \dec31 sync always update \dec31_out_sel $0\dec31_out_sel[2:0] end - attribute \src "libresoc.v:89052.3-89112.6" - process $proc$libresoc.v:89052$3827 + attribute \src "libresoc.v:89116.3-89176.6" + process $proc$libresoc.v:89116$3827 assign { } { } assign { } { } assign $0\dec31_cr_in[2:0] $1\dec31_cr_in[2:0] - attribute \src "libresoc.v:89053.5-89053.29" + attribute \src "libresoc.v:89117.5-89117.29" switch \initial - attribute \src "libresoc.v:89053.9-89053.17" + attribute \src "libresoc.v:89117.9-89117.17" case 1'1 case end @@ -139474,14 +139525,14 @@ module \dec31 sync always update \dec31_cr_in $0\dec31_cr_in[2:0] end - attribute \src "libresoc.v:89113.3-89173.6" - process $proc$libresoc.v:89113$3828 + attribute \src "libresoc.v:89177.3-89237.6" + process $proc$libresoc.v:89177$3828 assign { } { } assign { } { } assign $0\dec31_cr_out[2:0] $1\dec31_cr_out[2:0] - attribute \src "libresoc.v:89114.5-89114.29" + attribute \src "libresoc.v:89178.5-89178.29" switch \initial - attribute \src "libresoc.v:89114.9-89114.17" + attribute \src "libresoc.v:89178.9-89178.17" case 1'1 case end @@ -139565,14 +139616,14 @@ module \dec31 sync always update \dec31_cr_out $0\dec31_cr_out[2:0] end - attribute \src "libresoc.v:89174.3-89234.6" - process $proc$libresoc.v:89174$3829 + attribute \src "libresoc.v:89238.3-89298.6" + process $proc$libresoc.v:89238$3829 assign { } { } assign { } { } assign $0\dec31_sv_in1[2:0] $1\dec31_sv_in1[2:0] - attribute \src "libresoc.v:89175.5-89175.29" + attribute \src "libresoc.v:89239.5-89239.29" switch \initial - attribute \src "libresoc.v:89175.9-89175.17" + attribute \src "libresoc.v:89239.9-89239.17" case 1'1 case end @@ -139656,14 +139707,14 @@ module \dec31 sync always update \dec31_sv_in1 $0\dec31_sv_in1[2:0] end - attribute \src "libresoc.v:89235.3-89295.6" - process $proc$libresoc.v:89235$3830 + attribute \src "libresoc.v:89299.3-89359.6" + process $proc$libresoc.v:89299$3830 assign { } { } assign { } { } assign $0\dec31_sv_in2[2:0] $1\dec31_sv_in2[2:0] - attribute \src "libresoc.v:89236.5-89236.29" + attribute \src "libresoc.v:89300.5-89300.29" switch \initial - attribute \src "libresoc.v:89236.9-89236.17" + attribute \src "libresoc.v:89300.9-89300.17" case 1'1 case end @@ -139747,14 +139798,14 @@ module \dec31 sync always update \dec31_sv_in2 $0\dec31_sv_in2[2:0] end - attribute \src "libresoc.v:89296.3-89356.6" - process $proc$libresoc.v:89296$3831 + attribute \src "libresoc.v:89360.3-89420.6" + process $proc$libresoc.v:89360$3831 assign { } { } assign { } { } assign $0\dec31_sv_in3[2:0] $1\dec31_sv_in3[2:0] - attribute \src "libresoc.v:89297.5-89297.29" + attribute \src "libresoc.v:89361.5-89361.29" switch \initial - attribute \src "libresoc.v:89297.9-89297.17" + attribute \src "libresoc.v:89361.9-89361.17" case 1'1 case end @@ -139838,14 +139889,14 @@ module \dec31 sync always update \dec31_sv_in3 $0\dec31_sv_in3[2:0] end - attribute \src "libresoc.v:89357.3-89417.6" - process $proc$libresoc.v:89357$3832 + attribute \src "libresoc.v:89421.3-89481.6" + process $proc$libresoc.v:89421$3832 assign { } { } assign { } { } assign $0\dec31_sv_out[2:0] $1\dec31_sv_out[2:0] - attribute \src "libresoc.v:89358.5-89358.29" + attribute \src "libresoc.v:89422.5-89422.29" switch \initial - attribute \src "libresoc.v:89358.9-89358.17" + attribute \src "libresoc.v:89422.9-89422.17" case 1'1 case end @@ -139929,14 +139980,14 @@ module \dec31 sync always update \dec31_sv_out $0\dec31_sv_out[2:0] end - attribute \src "libresoc.v:89418.3-89478.6" - process $proc$libresoc.v:89418$3833 + attribute \src "libresoc.v:89482.3-89542.6" + process $proc$libresoc.v:89482$3833 assign { } { } assign { } { } assign $0\dec31_sv_out2[2:0] $1\dec31_sv_out2[2:0] - attribute \src "libresoc.v:89419.5-89419.29" + attribute \src "libresoc.v:89483.5-89483.29" switch \initial - attribute \src "libresoc.v:89419.9-89419.17" + attribute \src "libresoc.v:89483.9-89483.17" case 1'1 case end @@ -140020,14 +140071,14 @@ module \dec31 sync always update \dec31_sv_out2 $0\dec31_sv_out2[2:0] end - attribute \src "libresoc.v:89479.3-89539.6" - process $proc$libresoc.v:89479$3834 + attribute \src "libresoc.v:89543.3-89603.6" + process $proc$libresoc.v:89543$3834 assign { } { } assign { } { } assign $0\dec31_sv_cr_in[2:0] $1\dec31_sv_cr_in[2:0] - attribute \src "libresoc.v:89480.5-89480.29" + attribute \src "libresoc.v:89544.5-89544.29" switch \initial - attribute \src "libresoc.v:89480.9-89480.17" + attribute \src "libresoc.v:89544.9-89544.17" case 1'1 case end @@ -140111,14 +140162,14 @@ module \dec31 sync always update \dec31_sv_cr_in $0\dec31_sv_cr_in[2:0] end - attribute \src "libresoc.v:89540.3-89600.6" - process $proc$libresoc.v:89540$3835 + attribute \src "libresoc.v:89604.3-89664.6" + process $proc$libresoc.v:89604$3835 assign { } { } assign { } { } assign $0\dec31_sv_cr_out[2:0] $1\dec31_sv_cr_out[2:0] - attribute \src "libresoc.v:89541.5-89541.29" + attribute \src "libresoc.v:89605.5-89605.29" switch \initial - attribute \src "libresoc.v:89541.9-89541.17" + attribute \src "libresoc.v:89605.9-89605.17" case 1'1 case end @@ -140202,14 +140253,14 @@ module \dec31 sync always update \dec31_sv_cr_out $0\dec31_sv_cr_out[2:0] end - attribute \src "libresoc.v:89601.3-89661.6" - process $proc$libresoc.v:89601$3836 + attribute \src "libresoc.v:89665.3-89725.6" + process $proc$libresoc.v:89665$3836 assign { } { } assign { } { } assign $0\dec31_ldst_len[3:0] $1\dec31_ldst_len[3:0] - attribute \src "libresoc.v:89602.5-89602.29" + attribute \src "libresoc.v:89666.5-89666.29" switch \initial - attribute \src "libresoc.v:89602.9-89602.17" + attribute \src "libresoc.v:89666.9-89666.17" case 1'1 case end @@ -140293,14 +140344,14 @@ module \dec31 sync always update \dec31_ldst_len $0\dec31_ldst_len[3:0] end - attribute \src "libresoc.v:89662.3-89722.6" - process $proc$libresoc.v:89662$3837 + attribute \src "libresoc.v:89726.3-89786.6" + process $proc$libresoc.v:89726$3837 assign { } { } assign { } { } assign $0\dec31_upd[1:0] $1\dec31_upd[1:0] - attribute \src "libresoc.v:89663.5-89663.29" + attribute \src "libresoc.v:89727.5-89727.29" switch \initial - attribute \src "libresoc.v:89663.9-89663.17" + attribute \src "libresoc.v:89727.9-89727.17" case 1'1 case end @@ -140384,14 +140435,14 @@ module \dec31 sync always update \dec31_upd $0\dec31_upd[1:0] end - attribute \src "libresoc.v:89723.3-89783.6" - process $proc$libresoc.v:89723$3838 + attribute \src "libresoc.v:89787.3-89847.6" + process $proc$libresoc.v:89787$3838 assign { } { } assign { } { } assign $0\dec31_rc_sel[1:0] $1\dec31_rc_sel[1:0] - attribute \src "libresoc.v:89724.5-89724.29" + attribute \src "libresoc.v:89788.5-89788.29" switch \initial - attribute \src "libresoc.v:89724.9-89724.17" + attribute \src "libresoc.v:89788.9-89788.17" case 1'1 case end @@ -140475,14 +140526,14 @@ module \dec31 sync always update \dec31_rc_sel $0\dec31_rc_sel[1:0] end - attribute \src "libresoc.v:89784.3-89844.6" - process $proc$libresoc.v:89784$3839 + attribute \src "libresoc.v:89848.3-89908.6" + process $proc$libresoc.v:89848$3839 assign { } { } assign { } { } assign $0\dec31_cry_in[1:0] $1\dec31_cry_in[1:0] - attribute \src "libresoc.v:89785.5-89785.29" + attribute \src "libresoc.v:89849.5-89849.29" switch \initial - attribute \src "libresoc.v:89785.9-89785.17" + attribute \src "libresoc.v:89849.9-89849.17" case 1'1 case end @@ -140566,14 +140617,14 @@ module \dec31 sync always update \dec31_cry_in $0\dec31_cry_in[1:0] end - attribute \src "libresoc.v:89845.3-89905.6" - process $proc$libresoc.v:89845$3840 + attribute \src "libresoc.v:89909.3-89969.6" + process $proc$libresoc.v:89909$3840 assign { } { } assign { } { } assign $0\dec31_inv_a[0:0] $1\dec31_inv_a[0:0] - attribute \src "libresoc.v:89846.5-89846.29" + attribute \src "libresoc.v:89910.5-89910.29" switch \initial - attribute \src "libresoc.v:89846.9-89846.17" + attribute \src "libresoc.v:89910.9-89910.17" case 1'1 case end @@ -140657,14 +140708,14 @@ module \dec31 sync always update \dec31_inv_a $0\dec31_inv_a[0:0] end - attribute \src "libresoc.v:89906.3-89966.6" - process $proc$libresoc.v:89906$3841 + attribute \src "libresoc.v:89970.3-90030.6" + process $proc$libresoc.v:89970$3841 assign { } { } assign { } { } assign $0\dec31_inv_out[0:0] $1\dec31_inv_out[0:0] - attribute \src "libresoc.v:89907.5-89907.29" + attribute \src "libresoc.v:89971.5-89971.29" switch \initial - attribute \src "libresoc.v:89907.9-89907.17" + attribute \src "libresoc.v:89971.9-89971.17" case 1'1 case end @@ -140748,14 +140799,14 @@ module \dec31 sync always update \dec31_inv_out $0\dec31_inv_out[0:0] end - attribute \src "libresoc.v:89967.3-90027.6" - process $proc$libresoc.v:89967$3842 + attribute \src "libresoc.v:90031.3-90091.6" + process $proc$libresoc.v:90031$3842 assign { } { } assign { } { } assign $0\dec31_cry_out[0:0] $1\dec31_cry_out[0:0] - attribute \src "libresoc.v:89968.5-89968.29" + attribute \src "libresoc.v:90032.5-90032.29" switch \initial - attribute \src "libresoc.v:89968.9-89968.17" + attribute \src "libresoc.v:90032.9-90032.17" case 1'1 case end @@ -140839,14 +140890,14 @@ module \dec31 sync always update \dec31_cry_out $0\dec31_cry_out[0:0] end - attribute \src "libresoc.v:90028.3-90088.6" - process $proc$libresoc.v:90028$3843 + attribute \src "libresoc.v:90092.3-90152.6" + process $proc$libresoc.v:90092$3843 assign { } { } assign { } { } assign $0\dec31_br[0:0] $1\dec31_br[0:0] - attribute \src "libresoc.v:90029.5-90029.29" + attribute \src "libresoc.v:90093.5-90093.29" switch \initial - attribute \src "libresoc.v:90029.9-90029.17" + attribute \src "libresoc.v:90093.9-90093.17" case 1'1 case end @@ -140930,14 +140981,14 @@ module \dec31 sync always update \dec31_br $0\dec31_br[0:0] end - attribute \src "libresoc.v:90089.3-90149.6" - process $proc$libresoc.v:90089$3844 + attribute \src "libresoc.v:90153.3-90213.6" + process $proc$libresoc.v:90153$3844 assign { } { } assign { } { } assign $0\dec31_sgn_ext[0:0] $1\dec31_sgn_ext[0:0] - attribute \src "libresoc.v:90090.5-90090.29" + attribute \src "libresoc.v:90154.5-90154.29" switch \initial - attribute \src "libresoc.v:90090.9-90090.17" + attribute \src "libresoc.v:90154.9-90154.17" case 1'1 case end @@ -141021,14 +141072,14 @@ module \dec31 sync always update \dec31_sgn_ext $0\dec31_sgn_ext[0:0] end - attribute \src "libresoc.v:90150.3-90210.6" - process $proc$libresoc.v:90150$3845 + attribute \src "libresoc.v:90214.3-90274.6" + process $proc$libresoc.v:90214$3845 assign { } { } assign { } { } assign $0\dec31_rsrv[0:0] $1\dec31_rsrv[0:0] - attribute \src "libresoc.v:90151.5-90151.29" + attribute \src "libresoc.v:90215.5-90215.29" switch \initial - attribute \src "libresoc.v:90151.9-90151.17" + attribute \src "libresoc.v:90215.9-90215.17" case 1'1 case end @@ -141112,14 +141163,14 @@ module \dec31 sync always update \dec31_rsrv $0\dec31_rsrv[0:0] end - attribute \src "libresoc.v:90211.3-90271.6" - process $proc$libresoc.v:90211$3846 + attribute \src "libresoc.v:90275.3-90335.6" + process $proc$libresoc.v:90275$3846 assign { } { } assign { } { } assign $0\dec31_is_32b[0:0] $1\dec31_is_32b[0:0] - attribute \src "libresoc.v:90212.5-90212.29" + attribute \src "libresoc.v:90276.5-90276.29" switch \initial - attribute \src "libresoc.v:90212.9-90212.17" + attribute \src "libresoc.v:90276.9-90276.17" case 1'1 case end @@ -141203,14 +141254,14 @@ module \dec31 sync always update \dec31_is_32b $0\dec31_is_32b[0:0] end - attribute \src "libresoc.v:90272.3-90332.6" - process $proc$libresoc.v:90272$3847 + attribute \src "libresoc.v:90336.3-90396.6" + process $proc$libresoc.v:90336$3847 assign { } { } assign { } { } assign $0\dec31_sgn[0:0] $1\dec31_sgn[0:0] - attribute \src "libresoc.v:90273.5-90273.29" + attribute \src "libresoc.v:90337.5-90337.29" switch \initial - attribute \src "libresoc.v:90273.9-90273.17" + attribute \src "libresoc.v:90337.9-90337.17" case 1'1 case end @@ -141294,14 +141345,14 @@ module \dec31 sync always update \dec31_sgn $0\dec31_sgn[0:0] end - attribute \src "libresoc.v:90333.3-90393.6" - process $proc$libresoc.v:90333$3848 + attribute \src "libresoc.v:90397.3-90457.6" + process $proc$libresoc.v:90397$3848 assign { } { } assign { } { } assign $0\dec31_lk[0:0] $1\dec31_lk[0:0] - attribute \src "libresoc.v:90334.5-90334.29" + attribute \src "libresoc.v:90398.5-90398.29" switch \initial - attribute \src "libresoc.v:90334.9-90334.17" + attribute \src "libresoc.v:90398.9-90398.17" case 1'1 case end @@ -141385,14 +141436,14 @@ module \dec31 sync always update \dec31_lk $0\dec31_lk[0:0] end - attribute \src "libresoc.v:90394.3-90454.6" - process $proc$libresoc.v:90394$3849 + attribute \src "libresoc.v:90458.3-90518.6" + process $proc$libresoc.v:90458$3849 assign { } { } assign { } { } assign $0\dec31_sgl_pipe[0:0] $1\dec31_sgl_pipe[0:0] - attribute \src "libresoc.v:90395.5-90395.29" + attribute \src "libresoc.v:90459.5-90459.29" switch \initial - attribute \src "libresoc.v:90395.9-90395.17" + attribute \src "libresoc.v:90459.9-90459.17" case 1'1 case end @@ -141497,144 +141548,144 @@ module \dec31 connect \opc_in \opcode_switch [4:0] connect \opcode_switch \opcode_in [10:1] end -attribute \src "libresoc.v:90479.1-91456.10" +attribute \src "libresoc.v:90543.1-91520.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub0" attribute \generator "nMigen" module \dec31_dec_sub0 - attribute \src "libresoc.v:91341.3-91359.6" + attribute \src "libresoc.v:91405.3-91423.6" wire width 2 $0\dec31_dec_sub0_SV_Etype[1:0] - attribute \src "libresoc.v:91360.3-91378.6" + attribute \src "libresoc.v:91424.3-91442.6" wire width 2 $0\dec31_dec_sub0_SV_Ptype[1:0] - attribute \src "libresoc.v:91113.3-91131.6" + attribute \src "libresoc.v:91177.3-91195.6" wire width 8 $0\dec31_dec_sub0_asmcode[7:0] - attribute \src "libresoc.v:91189.3-91207.6" + attribute \src "libresoc.v:91253.3-91271.6" wire $0\dec31_dec_sub0_br[0:0] - attribute \src "libresoc.v:90847.3-90865.6" + attribute \src "libresoc.v:90911.3-90929.6" wire width 3 $0\dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:90866.3-90884.6" + attribute \src "libresoc.v:90930.3-90948.6" wire width 3 $0\dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:91094.3-91112.6" + attribute \src "libresoc.v:91158.3-91176.6" wire width 2 $0\dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:91170.3-91188.6" + attribute \src "libresoc.v:91234.3-91252.6" wire $0\dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:91246.3-91264.6" + attribute \src "libresoc.v:91310.3-91328.6" wire width 5 $0\dec31_dec_sub0_form[4:0] - attribute \src "libresoc.v:90828.3-90846.6" + attribute \src "libresoc.v:90892.3-90910.6" wire width 14 $0\dec31_dec_sub0_function_unit[13:0] - attribute \src "libresoc.v:91379.3-91397.6" + attribute \src "libresoc.v:91443.3-91461.6" wire width 3 $0\dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:91398.3-91416.6" + attribute \src "libresoc.v:91462.3-91480.6" wire width 4 $0\dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:91417.3-91435.6" + attribute \src "libresoc.v:91481.3-91499.6" wire width 2 $0\dec31_dec_sub0_in3_sel[1:0] - attribute \src "libresoc.v:91037.3-91055.6" + attribute \src "libresoc.v:91101.3-91119.6" wire width 7 $0\dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:91132.3-91150.6" + attribute \src "libresoc.v:91196.3-91214.6" wire $0\dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:91151.3-91169.6" + attribute \src "libresoc.v:91215.3-91233.6" wire $0\dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:91265.3-91283.6" + attribute \src "libresoc.v:91329.3-91347.6" wire $0\dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:91018.3-91036.6" + attribute \src "libresoc.v:91082.3-91100.6" wire width 4 $0\dec31_dec_sub0_ldst_len[3:0] - attribute \src "libresoc.v:91303.3-91321.6" + attribute \src "libresoc.v:91367.3-91385.6" wire $0\dec31_dec_sub0_lk[0:0] - attribute \src "libresoc.v:91436.3-91454.6" + attribute \src "libresoc.v:91500.3-91518.6" wire width 3 $0\dec31_dec_sub0_out_sel[2:0] - attribute \src "libresoc.v:91075.3-91093.6" + attribute \src "libresoc.v:91139.3-91157.6" wire width 2 $0\dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:91227.3-91245.6" + attribute \src "libresoc.v:91291.3-91309.6" wire $0\dec31_dec_sub0_rsrv[0:0] - attribute \src "libresoc.v:91322.3-91340.6" + attribute \src "libresoc.v:91386.3-91404.6" wire $0\dec31_dec_sub0_sgl_pipe[0:0] - attribute \src "libresoc.v:91284.3-91302.6" + attribute \src "libresoc.v:91348.3-91366.6" wire $0\dec31_dec_sub0_sgn[0:0] - attribute \src "libresoc.v:91208.3-91226.6" + attribute \src "libresoc.v:91272.3-91290.6" wire $0\dec31_dec_sub0_sgn_ext[0:0] - attribute \src "libresoc.v:90980.3-90998.6" + attribute \src "libresoc.v:91044.3-91062.6" wire width 3 $0\dec31_dec_sub0_sv_cr_in[2:0] - attribute \src "libresoc.v:90999.3-91017.6" + attribute \src "libresoc.v:91063.3-91081.6" wire width 3 $0\dec31_dec_sub0_sv_cr_out[2:0] - attribute \src "libresoc.v:90885.3-90903.6" + attribute \src "libresoc.v:90949.3-90967.6" wire width 3 $0\dec31_dec_sub0_sv_in1[2:0] - attribute \src "libresoc.v:90904.3-90922.6" + attribute \src "libresoc.v:90968.3-90986.6" wire width 3 $0\dec31_dec_sub0_sv_in2[2:0] - attribute \src "libresoc.v:90923.3-90941.6" + attribute \src "libresoc.v:90987.3-91005.6" wire width 3 $0\dec31_dec_sub0_sv_in3[2:0] - attribute \src "libresoc.v:90961.3-90979.6" + attribute \src "libresoc.v:91025.3-91043.6" wire width 3 $0\dec31_dec_sub0_sv_out2[2:0] - attribute \src "libresoc.v:90942.3-90960.6" + attribute \src "libresoc.v:91006.3-91024.6" wire width 3 $0\dec31_dec_sub0_sv_out[2:0] - attribute \src "libresoc.v:91056.3-91074.6" + attribute \src "libresoc.v:91120.3-91138.6" wire width 2 $0\dec31_dec_sub0_upd[1:0] - attribute \src "libresoc.v:90480.7-90480.20" + attribute \src "libresoc.v:90544.7-90544.20" wire $0\initial[0:0] - attribute \src "libresoc.v:91341.3-91359.6" + attribute \src "libresoc.v:91405.3-91423.6" wire width 2 $1\dec31_dec_sub0_SV_Etype[1:0] - attribute \src "libresoc.v:91360.3-91378.6" + attribute \src "libresoc.v:91424.3-91442.6" wire width 2 $1\dec31_dec_sub0_SV_Ptype[1:0] - attribute \src "libresoc.v:91113.3-91131.6" + attribute \src "libresoc.v:91177.3-91195.6" wire width 8 $1\dec31_dec_sub0_asmcode[7:0] - attribute \src "libresoc.v:91189.3-91207.6" + attribute \src "libresoc.v:91253.3-91271.6" wire $1\dec31_dec_sub0_br[0:0] - attribute \src "libresoc.v:90847.3-90865.6" + attribute \src "libresoc.v:90911.3-90929.6" wire width 3 $1\dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:90866.3-90884.6" + attribute \src "libresoc.v:90930.3-90948.6" wire width 3 $1\dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:91094.3-91112.6" + attribute \src "libresoc.v:91158.3-91176.6" wire width 2 $1\dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:91170.3-91188.6" + attribute \src "libresoc.v:91234.3-91252.6" wire $1\dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:91246.3-91264.6" + attribute \src "libresoc.v:91310.3-91328.6" wire width 5 $1\dec31_dec_sub0_form[4:0] - attribute \src "libresoc.v:90828.3-90846.6" + attribute \src "libresoc.v:90892.3-90910.6" wire width 14 $1\dec31_dec_sub0_function_unit[13:0] - attribute \src "libresoc.v:91379.3-91397.6" + attribute \src "libresoc.v:91443.3-91461.6" wire width 3 $1\dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:91398.3-91416.6" + attribute \src "libresoc.v:91462.3-91480.6" wire width 4 $1\dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:91417.3-91435.6" + attribute \src "libresoc.v:91481.3-91499.6" wire width 2 $1\dec31_dec_sub0_in3_sel[1:0] - attribute \src "libresoc.v:91037.3-91055.6" + attribute \src "libresoc.v:91101.3-91119.6" wire width 7 $1\dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:91132.3-91150.6" + attribute \src "libresoc.v:91196.3-91214.6" wire $1\dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:91151.3-91169.6" + attribute \src "libresoc.v:91215.3-91233.6" wire $1\dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:91265.3-91283.6" + attribute \src "libresoc.v:91329.3-91347.6" wire $1\dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:91018.3-91036.6" + attribute \src "libresoc.v:91082.3-91100.6" wire width 4 $1\dec31_dec_sub0_ldst_len[3:0] - attribute \src "libresoc.v:91303.3-91321.6" + attribute \src "libresoc.v:91367.3-91385.6" wire $1\dec31_dec_sub0_lk[0:0] - attribute \src "libresoc.v:91436.3-91454.6" + attribute \src "libresoc.v:91500.3-91518.6" wire width 3 $1\dec31_dec_sub0_out_sel[2:0] - attribute \src "libresoc.v:91075.3-91093.6" + attribute \src "libresoc.v:91139.3-91157.6" wire width 2 $1\dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:91227.3-91245.6" + attribute \src "libresoc.v:91291.3-91309.6" wire $1\dec31_dec_sub0_rsrv[0:0] - attribute \src "libresoc.v:91322.3-91340.6" + attribute \src "libresoc.v:91386.3-91404.6" wire $1\dec31_dec_sub0_sgl_pipe[0:0] - attribute \src "libresoc.v:91284.3-91302.6" + attribute \src "libresoc.v:91348.3-91366.6" wire $1\dec31_dec_sub0_sgn[0:0] - attribute \src "libresoc.v:91208.3-91226.6" + attribute \src "libresoc.v:91272.3-91290.6" wire $1\dec31_dec_sub0_sgn_ext[0:0] - attribute \src "libresoc.v:90980.3-90998.6" + attribute \src "libresoc.v:91044.3-91062.6" wire width 3 $1\dec31_dec_sub0_sv_cr_in[2:0] - attribute \src "libresoc.v:90999.3-91017.6" + attribute \src "libresoc.v:91063.3-91081.6" wire width 3 $1\dec31_dec_sub0_sv_cr_out[2:0] - attribute \src "libresoc.v:90885.3-90903.6" + attribute \src "libresoc.v:90949.3-90967.6" wire width 3 $1\dec31_dec_sub0_sv_in1[2:0] - attribute \src "libresoc.v:90904.3-90922.6" + attribute \src "libresoc.v:90968.3-90986.6" wire width 3 $1\dec31_dec_sub0_sv_in2[2:0] - attribute \src "libresoc.v:90923.3-90941.6" + attribute \src "libresoc.v:90987.3-91005.6" wire width 3 $1\dec31_dec_sub0_sv_in3[2:0] - attribute \src "libresoc.v:90961.3-90979.6" + attribute \src "libresoc.v:91025.3-91043.6" wire width 3 $1\dec31_dec_sub0_sv_out2[2:0] - attribute \src "libresoc.v:90942.3-90960.6" + attribute \src "libresoc.v:91006.3-91024.6" wire width 3 $1\dec31_dec_sub0_sv_out[2:0] - attribute \src "libresoc.v:91056.3-91074.6" + attribute \src "libresoc.v:91120.3-91138.6" wire width 2 $1\dec31_dec_sub0_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -141946,28 +141997,28 @@ module \dec31_dec_sub0 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub0_upd - attribute \src "libresoc.v:90480.7-90480.15" + attribute \src "libresoc.v:90544.7-90544.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:90480.7-90480.20" - process $proc$libresoc.v:90480$3884 + attribute \src "libresoc.v:90544.7-90544.20" + process $proc$libresoc.v:90544$3884 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:90828.3-90846.6" - process $proc$libresoc.v:90828$3851 + attribute \src "libresoc.v:90892.3-90910.6" + process $proc$libresoc.v:90892$3851 assign { } { } assign { } { } assign $0\dec31_dec_sub0_function_unit[13:0] $1\dec31_dec_sub0_function_unit[13:0] - attribute \src "libresoc.v:90829.5-90829.29" + attribute \src "libresoc.v:90893.5-90893.29" switch \initial - attribute \src "libresoc.v:90829.9-90829.17" + attribute \src "libresoc.v:90893.9-90893.17" case 1'1 case end @@ -141995,14 +142046,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_function_unit $0\dec31_dec_sub0_function_unit[13:0] end - attribute \src "libresoc.v:90847.3-90865.6" - process $proc$libresoc.v:90847$3852 + attribute \src "libresoc.v:90911.3-90929.6" + process $proc$libresoc.v:90911$3852 assign { } { } assign { } { } assign $0\dec31_dec_sub0_cr_in[2:0] $1\dec31_dec_sub0_cr_in[2:0] - attribute \src "libresoc.v:90848.5-90848.29" + attribute \src "libresoc.v:90912.5-90912.29" switch \initial - attribute \src "libresoc.v:90848.9-90848.17" + attribute \src "libresoc.v:90912.9-90912.17" case 1'1 case end @@ -142030,14 +142081,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_cr_in $0\dec31_dec_sub0_cr_in[2:0] end - attribute \src "libresoc.v:90866.3-90884.6" - process $proc$libresoc.v:90866$3853 + attribute \src "libresoc.v:90930.3-90948.6" + process $proc$libresoc.v:90930$3853 assign { } { } assign { } { } assign $0\dec31_dec_sub0_cr_out[2:0] $1\dec31_dec_sub0_cr_out[2:0] - attribute \src "libresoc.v:90867.5-90867.29" + attribute \src "libresoc.v:90931.5-90931.29" switch \initial - attribute \src "libresoc.v:90867.9-90867.17" + attribute \src "libresoc.v:90931.9-90931.17" case 1'1 case end @@ -142065,14 +142116,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_cr_out $0\dec31_dec_sub0_cr_out[2:0] end - attribute \src "libresoc.v:90885.3-90903.6" - process $proc$libresoc.v:90885$3854 + attribute \src "libresoc.v:90949.3-90967.6" + process $proc$libresoc.v:90949$3854 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_in1[2:0] $1\dec31_dec_sub0_sv_in1[2:0] - attribute \src "libresoc.v:90886.5-90886.29" + attribute \src "libresoc.v:90950.5-90950.29" switch \initial - attribute \src "libresoc.v:90886.9-90886.17" + attribute \src "libresoc.v:90950.9-90950.17" case 1'1 case end @@ -142100,14 +142151,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_in1 $0\dec31_dec_sub0_sv_in1[2:0] end - attribute \src "libresoc.v:90904.3-90922.6" - process $proc$libresoc.v:90904$3855 + attribute \src "libresoc.v:90968.3-90986.6" + process $proc$libresoc.v:90968$3855 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_in2[2:0] $1\dec31_dec_sub0_sv_in2[2:0] - attribute \src "libresoc.v:90905.5-90905.29" + attribute \src "libresoc.v:90969.5-90969.29" switch \initial - attribute \src "libresoc.v:90905.9-90905.17" + attribute \src "libresoc.v:90969.9-90969.17" case 1'1 case end @@ -142135,14 +142186,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_in2 $0\dec31_dec_sub0_sv_in2[2:0] end - attribute \src "libresoc.v:90923.3-90941.6" - process $proc$libresoc.v:90923$3856 + attribute \src "libresoc.v:90987.3-91005.6" + process $proc$libresoc.v:90987$3856 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_in3[2:0] $1\dec31_dec_sub0_sv_in3[2:0] - attribute \src "libresoc.v:90924.5-90924.29" + attribute \src "libresoc.v:90988.5-90988.29" switch \initial - attribute \src "libresoc.v:90924.9-90924.17" + attribute \src "libresoc.v:90988.9-90988.17" case 1'1 case end @@ -142170,14 +142221,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_in3 $0\dec31_dec_sub0_sv_in3[2:0] end - attribute \src "libresoc.v:90942.3-90960.6" - process $proc$libresoc.v:90942$3857 + attribute \src "libresoc.v:91006.3-91024.6" + process $proc$libresoc.v:91006$3857 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_out[2:0] $1\dec31_dec_sub0_sv_out[2:0] - attribute \src "libresoc.v:90943.5-90943.29" + attribute \src "libresoc.v:91007.5-91007.29" switch \initial - attribute \src "libresoc.v:90943.9-90943.17" + attribute \src "libresoc.v:91007.9-91007.17" case 1'1 case end @@ -142205,14 +142256,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_out $0\dec31_dec_sub0_sv_out[2:0] end - attribute \src "libresoc.v:90961.3-90979.6" - process $proc$libresoc.v:90961$3858 + attribute \src "libresoc.v:91025.3-91043.6" + process $proc$libresoc.v:91025$3858 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_out2[2:0] $1\dec31_dec_sub0_sv_out2[2:0] - attribute \src "libresoc.v:90962.5-90962.29" + attribute \src "libresoc.v:91026.5-91026.29" switch \initial - attribute \src "libresoc.v:90962.9-90962.17" + attribute \src "libresoc.v:91026.9-91026.17" case 1'1 case end @@ -142240,14 +142291,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_out2 $0\dec31_dec_sub0_sv_out2[2:0] end - attribute \src "libresoc.v:90980.3-90998.6" - process $proc$libresoc.v:90980$3859 + attribute \src "libresoc.v:91044.3-91062.6" + process $proc$libresoc.v:91044$3859 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_cr_in[2:0] $1\dec31_dec_sub0_sv_cr_in[2:0] - attribute \src "libresoc.v:90981.5-90981.29" + attribute \src "libresoc.v:91045.5-91045.29" switch \initial - attribute \src "libresoc.v:90981.9-90981.17" + attribute \src "libresoc.v:91045.9-91045.17" case 1'1 case end @@ -142275,14 +142326,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_cr_in $0\dec31_dec_sub0_sv_cr_in[2:0] end - attribute \src "libresoc.v:90999.3-91017.6" - process $proc$libresoc.v:90999$3860 + attribute \src "libresoc.v:91063.3-91081.6" + process $proc$libresoc.v:91063$3860 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sv_cr_out[2:0] $1\dec31_dec_sub0_sv_cr_out[2:0] - attribute \src "libresoc.v:91000.5-91000.29" + attribute \src "libresoc.v:91064.5-91064.29" switch \initial - attribute \src "libresoc.v:91000.9-91000.17" + attribute \src "libresoc.v:91064.9-91064.17" case 1'1 case end @@ -142310,14 +142361,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sv_cr_out $0\dec31_dec_sub0_sv_cr_out[2:0] end - attribute \src "libresoc.v:91018.3-91036.6" - process $proc$libresoc.v:91018$3861 + attribute \src "libresoc.v:91082.3-91100.6" + process $proc$libresoc.v:91082$3861 assign { } { } assign { } { } assign $0\dec31_dec_sub0_ldst_len[3:0] $1\dec31_dec_sub0_ldst_len[3:0] - attribute \src "libresoc.v:91019.5-91019.29" + attribute \src "libresoc.v:91083.5-91083.29" switch \initial - attribute \src "libresoc.v:91019.9-91019.17" + attribute \src "libresoc.v:91083.9-91083.17" case 1'1 case end @@ -142345,14 +142396,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_ldst_len $0\dec31_dec_sub0_ldst_len[3:0] end - attribute \src "libresoc.v:91037.3-91055.6" - process $proc$libresoc.v:91037$3862 + attribute \src "libresoc.v:91101.3-91119.6" + process $proc$libresoc.v:91101$3862 assign { } { } assign { } { } assign $0\dec31_dec_sub0_internal_op[6:0] $1\dec31_dec_sub0_internal_op[6:0] - attribute \src "libresoc.v:91038.5-91038.29" + attribute \src "libresoc.v:91102.5-91102.29" switch \initial - attribute \src "libresoc.v:91038.9-91038.17" + attribute \src "libresoc.v:91102.9-91102.17" case 1'1 case end @@ -142380,14 +142431,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_internal_op $0\dec31_dec_sub0_internal_op[6:0] end - attribute \src "libresoc.v:91056.3-91074.6" - process $proc$libresoc.v:91056$3863 + attribute \src "libresoc.v:91120.3-91138.6" + process $proc$libresoc.v:91120$3863 assign { } { } assign { } { } assign $0\dec31_dec_sub0_upd[1:0] $1\dec31_dec_sub0_upd[1:0] - attribute \src "libresoc.v:91057.5-91057.29" + attribute \src "libresoc.v:91121.5-91121.29" switch \initial - attribute \src "libresoc.v:91057.9-91057.17" + attribute \src "libresoc.v:91121.9-91121.17" case 1'1 case end @@ -142415,14 +142466,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_upd $0\dec31_dec_sub0_upd[1:0] end - attribute \src "libresoc.v:91075.3-91093.6" - process $proc$libresoc.v:91075$3864 + attribute \src "libresoc.v:91139.3-91157.6" + process $proc$libresoc.v:91139$3864 assign { } { } assign { } { } assign $0\dec31_dec_sub0_rc_sel[1:0] $1\dec31_dec_sub0_rc_sel[1:0] - attribute \src "libresoc.v:91076.5-91076.29" + attribute \src "libresoc.v:91140.5-91140.29" switch \initial - attribute \src "libresoc.v:91076.9-91076.17" + attribute \src "libresoc.v:91140.9-91140.17" case 1'1 case end @@ -142450,14 +142501,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_rc_sel $0\dec31_dec_sub0_rc_sel[1:0] end - attribute \src "libresoc.v:91094.3-91112.6" - process $proc$libresoc.v:91094$3865 + attribute \src "libresoc.v:91158.3-91176.6" + process $proc$libresoc.v:91158$3865 assign { } { } assign { } { } assign $0\dec31_dec_sub0_cry_in[1:0] $1\dec31_dec_sub0_cry_in[1:0] - attribute \src "libresoc.v:91095.5-91095.29" + attribute \src "libresoc.v:91159.5-91159.29" switch \initial - attribute \src "libresoc.v:91095.9-91095.17" + attribute \src "libresoc.v:91159.9-91159.17" case 1'1 case end @@ -142485,14 +142536,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_cry_in $0\dec31_dec_sub0_cry_in[1:0] end - attribute \src "libresoc.v:91113.3-91131.6" - process $proc$libresoc.v:91113$3866 + attribute \src "libresoc.v:91177.3-91195.6" + process $proc$libresoc.v:91177$3866 assign { } { } assign { } { } assign $0\dec31_dec_sub0_asmcode[7:0] $1\dec31_dec_sub0_asmcode[7:0] - attribute \src "libresoc.v:91114.5-91114.29" + attribute \src "libresoc.v:91178.5-91178.29" switch \initial - attribute \src "libresoc.v:91114.9-91114.17" + attribute \src "libresoc.v:91178.9-91178.17" case 1'1 case end @@ -142520,14 +142571,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_asmcode $0\dec31_dec_sub0_asmcode[7:0] end - attribute \src "libresoc.v:91132.3-91150.6" - process $proc$libresoc.v:91132$3867 + attribute \src "libresoc.v:91196.3-91214.6" + process $proc$libresoc.v:91196$3867 assign { } { } assign { } { } assign $0\dec31_dec_sub0_inv_a[0:0] $1\dec31_dec_sub0_inv_a[0:0] - attribute \src "libresoc.v:91133.5-91133.29" + attribute \src "libresoc.v:91197.5-91197.29" switch \initial - attribute \src "libresoc.v:91133.9-91133.17" + attribute \src "libresoc.v:91197.9-91197.17" case 1'1 case end @@ -142555,14 +142606,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_inv_a $0\dec31_dec_sub0_inv_a[0:0] end - attribute \src "libresoc.v:91151.3-91169.6" - process $proc$libresoc.v:91151$3868 + attribute \src "libresoc.v:91215.3-91233.6" + process $proc$libresoc.v:91215$3868 assign { } { } assign { } { } assign $0\dec31_dec_sub0_inv_out[0:0] $1\dec31_dec_sub0_inv_out[0:0] - attribute \src "libresoc.v:91152.5-91152.29" + attribute \src "libresoc.v:91216.5-91216.29" switch \initial - attribute \src "libresoc.v:91152.9-91152.17" + attribute \src "libresoc.v:91216.9-91216.17" case 1'1 case end @@ -142590,14 +142641,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_inv_out $0\dec31_dec_sub0_inv_out[0:0] end - attribute \src "libresoc.v:91170.3-91188.6" - process $proc$libresoc.v:91170$3869 + attribute \src "libresoc.v:91234.3-91252.6" + process $proc$libresoc.v:91234$3869 assign { } { } assign { } { } assign $0\dec31_dec_sub0_cry_out[0:0] $1\dec31_dec_sub0_cry_out[0:0] - attribute \src "libresoc.v:91171.5-91171.29" + attribute \src "libresoc.v:91235.5-91235.29" switch \initial - attribute \src "libresoc.v:91171.9-91171.17" + attribute \src "libresoc.v:91235.9-91235.17" case 1'1 case end @@ -142625,14 +142676,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_cry_out $0\dec31_dec_sub0_cry_out[0:0] end - attribute \src "libresoc.v:91189.3-91207.6" - process $proc$libresoc.v:91189$3870 + attribute \src "libresoc.v:91253.3-91271.6" + process $proc$libresoc.v:91253$3870 assign { } { } assign { } { } assign $0\dec31_dec_sub0_br[0:0] $1\dec31_dec_sub0_br[0:0] - attribute \src "libresoc.v:91190.5-91190.29" + attribute \src "libresoc.v:91254.5-91254.29" switch \initial - attribute \src "libresoc.v:91190.9-91190.17" + attribute \src "libresoc.v:91254.9-91254.17" case 1'1 case end @@ -142660,14 +142711,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_br $0\dec31_dec_sub0_br[0:0] end - attribute \src "libresoc.v:91208.3-91226.6" - process $proc$libresoc.v:91208$3871 + attribute \src "libresoc.v:91272.3-91290.6" + process $proc$libresoc.v:91272$3871 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sgn_ext[0:0] $1\dec31_dec_sub0_sgn_ext[0:0] - attribute \src "libresoc.v:91209.5-91209.29" + attribute \src "libresoc.v:91273.5-91273.29" switch \initial - attribute \src "libresoc.v:91209.9-91209.17" + attribute \src "libresoc.v:91273.9-91273.17" case 1'1 case end @@ -142695,14 +142746,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sgn_ext $0\dec31_dec_sub0_sgn_ext[0:0] end - attribute \src "libresoc.v:91227.3-91245.6" - process $proc$libresoc.v:91227$3872 + attribute \src "libresoc.v:91291.3-91309.6" + process $proc$libresoc.v:91291$3872 assign { } { } assign { } { } assign $0\dec31_dec_sub0_rsrv[0:0] $1\dec31_dec_sub0_rsrv[0:0] - attribute \src "libresoc.v:91228.5-91228.29" + attribute \src "libresoc.v:91292.5-91292.29" switch \initial - attribute \src "libresoc.v:91228.9-91228.17" + attribute \src "libresoc.v:91292.9-91292.17" case 1'1 case end @@ -142730,14 +142781,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_rsrv $0\dec31_dec_sub0_rsrv[0:0] end - attribute \src "libresoc.v:91246.3-91264.6" - process $proc$libresoc.v:91246$3873 + attribute \src "libresoc.v:91310.3-91328.6" + process $proc$libresoc.v:91310$3873 assign { } { } assign { } { } assign $0\dec31_dec_sub0_form[4:0] $1\dec31_dec_sub0_form[4:0] - attribute \src "libresoc.v:91247.5-91247.29" + attribute \src "libresoc.v:91311.5-91311.29" switch \initial - attribute \src "libresoc.v:91247.9-91247.17" + attribute \src "libresoc.v:91311.9-91311.17" case 1'1 case end @@ -142765,14 +142816,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_form $0\dec31_dec_sub0_form[4:0] end - attribute \src "libresoc.v:91265.3-91283.6" - process $proc$libresoc.v:91265$3874 + attribute \src "libresoc.v:91329.3-91347.6" + process $proc$libresoc.v:91329$3874 assign { } { } assign { } { } assign $0\dec31_dec_sub0_is_32b[0:0] $1\dec31_dec_sub0_is_32b[0:0] - attribute \src "libresoc.v:91266.5-91266.29" + attribute \src "libresoc.v:91330.5-91330.29" switch \initial - attribute \src "libresoc.v:91266.9-91266.17" + attribute \src "libresoc.v:91330.9-91330.17" case 1'1 case end @@ -142800,14 +142851,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_is_32b $0\dec31_dec_sub0_is_32b[0:0] end - attribute \src "libresoc.v:91284.3-91302.6" - process $proc$libresoc.v:91284$3875 + attribute \src "libresoc.v:91348.3-91366.6" + process $proc$libresoc.v:91348$3875 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sgn[0:0] $1\dec31_dec_sub0_sgn[0:0] - attribute \src "libresoc.v:91285.5-91285.29" + attribute \src "libresoc.v:91349.5-91349.29" switch \initial - attribute \src "libresoc.v:91285.9-91285.17" + attribute \src "libresoc.v:91349.9-91349.17" case 1'1 case end @@ -142835,14 +142886,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sgn $0\dec31_dec_sub0_sgn[0:0] end - attribute \src "libresoc.v:91303.3-91321.6" - process $proc$libresoc.v:91303$3876 + attribute \src "libresoc.v:91367.3-91385.6" + process $proc$libresoc.v:91367$3876 assign { } { } assign { } { } assign $0\dec31_dec_sub0_lk[0:0] $1\dec31_dec_sub0_lk[0:0] - attribute \src "libresoc.v:91304.5-91304.29" + attribute \src "libresoc.v:91368.5-91368.29" switch \initial - attribute \src "libresoc.v:91304.9-91304.17" + attribute \src "libresoc.v:91368.9-91368.17" case 1'1 case end @@ -142870,14 +142921,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_lk $0\dec31_dec_sub0_lk[0:0] end - attribute \src "libresoc.v:91322.3-91340.6" - process $proc$libresoc.v:91322$3877 + attribute \src "libresoc.v:91386.3-91404.6" + process $proc$libresoc.v:91386$3877 assign { } { } assign { } { } assign $0\dec31_dec_sub0_sgl_pipe[0:0] $1\dec31_dec_sub0_sgl_pipe[0:0] - attribute \src "libresoc.v:91323.5-91323.29" + attribute \src "libresoc.v:91387.5-91387.29" switch \initial - attribute \src "libresoc.v:91323.9-91323.17" + attribute \src "libresoc.v:91387.9-91387.17" case 1'1 case end @@ -142905,14 +142956,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_sgl_pipe $0\dec31_dec_sub0_sgl_pipe[0:0] end - attribute \src "libresoc.v:91341.3-91359.6" - process $proc$libresoc.v:91341$3878 + attribute \src "libresoc.v:91405.3-91423.6" + process $proc$libresoc.v:91405$3878 assign { } { } assign { } { } assign $0\dec31_dec_sub0_SV_Etype[1:0] $1\dec31_dec_sub0_SV_Etype[1:0] - attribute \src "libresoc.v:91342.5-91342.29" + attribute \src "libresoc.v:91406.5-91406.29" switch \initial - attribute \src "libresoc.v:91342.9-91342.17" + attribute \src "libresoc.v:91406.9-91406.17" case 1'1 case end @@ -142940,14 +142991,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_SV_Etype $0\dec31_dec_sub0_SV_Etype[1:0] end - attribute \src "libresoc.v:91360.3-91378.6" - process $proc$libresoc.v:91360$3879 + attribute \src "libresoc.v:91424.3-91442.6" + process $proc$libresoc.v:91424$3879 assign { } { } assign { } { } assign $0\dec31_dec_sub0_SV_Ptype[1:0] $1\dec31_dec_sub0_SV_Ptype[1:0] - attribute \src "libresoc.v:91361.5-91361.29" + attribute \src "libresoc.v:91425.5-91425.29" switch \initial - attribute \src "libresoc.v:91361.9-91361.17" + attribute \src "libresoc.v:91425.9-91425.17" case 1'1 case end @@ -142975,14 +143026,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_SV_Ptype $0\dec31_dec_sub0_SV_Ptype[1:0] end - attribute \src "libresoc.v:91379.3-91397.6" - process $proc$libresoc.v:91379$3880 + attribute \src "libresoc.v:91443.3-91461.6" + process $proc$libresoc.v:91443$3880 assign { } { } assign { } { } assign $0\dec31_dec_sub0_in1_sel[2:0] $1\dec31_dec_sub0_in1_sel[2:0] - attribute \src "libresoc.v:91380.5-91380.29" + attribute \src "libresoc.v:91444.5-91444.29" switch \initial - attribute \src "libresoc.v:91380.9-91380.17" + attribute \src "libresoc.v:91444.9-91444.17" case 1'1 case end @@ -143010,14 +143061,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_in1_sel $0\dec31_dec_sub0_in1_sel[2:0] end - attribute \src "libresoc.v:91398.3-91416.6" - process $proc$libresoc.v:91398$3881 + attribute \src "libresoc.v:91462.3-91480.6" + process $proc$libresoc.v:91462$3881 assign { } { } assign { } { } assign $0\dec31_dec_sub0_in2_sel[3:0] $1\dec31_dec_sub0_in2_sel[3:0] - attribute \src "libresoc.v:91399.5-91399.29" + attribute \src "libresoc.v:91463.5-91463.29" switch \initial - attribute \src "libresoc.v:91399.9-91399.17" + attribute \src "libresoc.v:91463.9-91463.17" case 1'1 case end @@ -143045,14 +143096,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_in2_sel $0\dec31_dec_sub0_in2_sel[3:0] end - attribute \src "libresoc.v:91417.3-91435.6" - process $proc$libresoc.v:91417$3882 + attribute \src "libresoc.v:91481.3-91499.6" + process $proc$libresoc.v:91481$3882 assign { } { } assign { } { } assign $0\dec31_dec_sub0_in3_sel[1:0] $1\dec31_dec_sub0_in3_sel[1:0] - attribute \src "libresoc.v:91418.5-91418.29" + attribute \src "libresoc.v:91482.5-91482.29" switch \initial - attribute \src "libresoc.v:91418.9-91418.17" + attribute \src "libresoc.v:91482.9-91482.17" case 1'1 case end @@ -143080,14 +143131,14 @@ module \dec31_dec_sub0 sync always update \dec31_dec_sub0_in3_sel $0\dec31_dec_sub0_in3_sel[1:0] end - attribute \src "libresoc.v:91436.3-91454.6" - process $proc$libresoc.v:91436$3883 + attribute \src "libresoc.v:91500.3-91518.6" + process $proc$libresoc.v:91500$3883 assign { } { } assign { } { } assign $0\dec31_dec_sub0_out_sel[2:0] $1\dec31_dec_sub0_out_sel[2:0] - attribute \src "libresoc.v:91437.5-91437.29" + attribute \src "libresoc.v:91501.5-91501.29" switch \initial - attribute \src "libresoc.v:91437.9-91437.17" + attribute \src "libresoc.v:91501.9-91501.17" case 1'1 case end @@ -143117,144 +143168,144 @@ module \dec31_dec_sub0 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:91460.1-93031.10" +attribute \src "libresoc.v:91524.1-93095.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub10" attribute \generator "nMigen" module \dec31_dec_sub10 - attribute \src "libresoc.v:92808.3-92844.6" + attribute \src "libresoc.v:92872.3-92908.6" wire width 2 $0\dec31_dec_sub10_SV_Etype[1:0] - attribute \src "libresoc.v:92845.3-92881.6" + attribute \src "libresoc.v:92909.3-92945.6" wire width 2 $0\dec31_dec_sub10_SV_Ptype[1:0] - attribute \src "libresoc.v:92364.3-92400.6" + attribute \src "libresoc.v:92428.3-92464.6" wire width 8 $0\dec31_dec_sub10_asmcode[7:0] - attribute \src "libresoc.v:92512.3-92548.6" + attribute \src "libresoc.v:92576.3-92612.6" wire $0\dec31_dec_sub10_br[0:0] - attribute \src "libresoc.v:91846.3-91882.6" + attribute \src "libresoc.v:91910.3-91946.6" wire width 3 $0\dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:91883.3-91919.6" + attribute \src "libresoc.v:91947.3-91983.6" wire width 3 $0\dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:92327.3-92363.6" + attribute \src "libresoc.v:92391.3-92427.6" wire width 2 $0\dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:92475.3-92511.6" + attribute \src "libresoc.v:92539.3-92575.6" wire $0\dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:92623.3-92659.6" + attribute \src "libresoc.v:92687.3-92723.6" wire width 5 $0\dec31_dec_sub10_form[4:0] - attribute \src "libresoc.v:91809.3-91845.6" + attribute \src "libresoc.v:91873.3-91909.6" wire width 14 $0\dec31_dec_sub10_function_unit[13:0] - attribute \src "libresoc.v:92882.3-92918.6" + attribute \src "libresoc.v:92946.3-92982.6" wire width 3 $0\dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:92919.3-92955.6" + attribute \src "libresoc.v:92983.3-93019.6" wire width 4 $0\dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:92956.3-92992.6" + attribute \src "libresoc.v:93020.3-93056.6" wire width 2 $0\dec31_dec_sub10_in3_sel[1:0] - attribute \src "libresoc.v:92216.3-92252.6" + attribute \src "libresoc.v:92280.3-92316.6" wire width 7 $0\dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:92401.3-92437.6" + attribute \src "libresoc.v:92465.3-92501.6" wire $0\dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:92438.3-92474.6" + attribute \src "libresoc.v:92502.3-92538.6" wire $0\dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:92660.3-92696.6" + attribute \src "libresoc.v:92724.3-92760.6" wire $0\dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:92179.3-92215.6" + attribute \src "libresoc.v:92243.3-92279.6" wire width 4 $0\dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:92734.3-92770.6" + attribute \src "libresoc.v:92798.3-92834.6" wire $0\dec31_dec_sub10_lk[0:0] - attribute \src "libresoc.v:92993.3-93029.6" + attribute \src "libresoc.v:93057.3-93093.6" wire width 3 $0\dec31_dec_sub10_out_sel[2:0] - attribute \src "libresoc.v:92290.3-92326.6" + attribute \src "libresoc.v:92354.3-92390.6" wire width 2 $0\dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:92586.3-92622.6" + attribute \src "libresoc.v:92650.3-92686.6" wire $0\dec31_dec_sub10_rsrv[0:0] - attribute \src "libresoc.v:92771.3-92807.6" + attribute \src "libresoc.v:92835.3-92871.6" wire $0\dec31_dec_sub10_sgl_pipe[0:0] - attribute \src "libresoc.v:92697.3-92733.6" + attribute \src "libresoc.v:92761.3-92797.6" wire $0\dec31_dec_sub10_sgn[0:0] - attribute \src "libresoc.v:92549.3-92585.6" + attribute \src "libresoc.v:92613.3-92649.6" wire $0\dec31_dec_sub10_sgn_ext[0:0] - attribute \src "libresoc.v:92105.3-92141.6" + attribute \src "libresoc.v:92169.3-92205.6" wire width 3 $0\dec31_dec_sub10_sv_cr_in[2:0] - attribute \src "libresoc.v:92142.3-92178.6" + attribute \src "libresoc.v:92206.3-92242.6" wire width 3 $0\dec31_dec_sub10_sv_cr_out[2:0] - attribute \src "libresoc.v:91920.3-91956.6" + attribute \src "libresoc.v:91984.3-92020.6" wire width 3 $0\dec31_dec_sub10_sv_in1[2:0] - attribute \src "libresoc.v:91957.3-91993.6" + attribute \src "libresoc.v:92021.3-92057.6" wire width 3 $0\dec31_dec_sub10_sv_in2[2:0] - attribute \src "libresoc.v:91994.3-92030.6" + attribute \src "libresoc.v:92058.3-92094.6" wire width 3 $0\dec31_dec_sub10_sv_in3[2:0] - attribute \src "libresoc.v:92068.3-92104.6" + attribute \src "libresoc.v:92132.3-92168.6" wire width 3 $0\dec31_dec_sub10_sv_out2[2:0] - attribute \src "libresoc.v:92031.3-92067.6" + attribute \src "libresoc.v:92095.3-92131.6" wire width 3 $0\dec31_dec_sub10_sv_out[2:0] - attribute \src "libresoc.v:92253.3-92289.6" + attribute \src "libresoc.v:92317.3-92353.6" wire width 2 $0\dec31_dec_sub10_upd[1:0] - attribute \src "libresoc.v:91461.7-91461.20" + attribute \src "libresoc.v:91525.7-91525.20" wire $0\initial[0:0] - attribute \src "libresoc.v:92808.3-92844.6" + attribute \src "libresoc.v:92872.3-92908.6" wire width 2 $1\dec31_dec_sub10_SV_Etype[1:0] - attribute \src "libresoc.v:92845.3-92881.6" + attribute \src "libresoc.v:92909.3-92945.6" wire width 2 $1\dec31_dec_sub10_SV_Ptype[1:0] - attribute \src "libresoc.v:92364.3-92400.6" + attribute \src "libresoc.v:92428.3-92464.6" wire width 8 $1\dec31_dec_sub10_asmcode[7:0] - attribute \src "libresoc.v:92512.3-92548.6" + attribute \src "libresoc.v:92576.3-92612.6" wire $1\dec31_dec_sub10_br[0:0] - attribute \src "libresoc.v:91846.3-91882.6" + attribute \src "libresoc.v:91910.3-91946.6" wire width 3 $1\dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:91883.3-91919.6" + attribute \src "libresoc.v:91947.3-91983.6" wire width 3 $1\dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:92327.3-92363.6" + attribute \src "libresoc.v:92391.3-92427.6" wire width 2 $1\dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:92475.3-92511.6" + attribute \src "libresoc.v:92539.3-92575.6" wire $1\dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:92623.3-92659.6" + attribute \src "libresoc.v:92687.3-92723.6" wire width 5 $1\dec31_dec_sub10_form[4:0] - attribute \src "libresoc.v:91809.3-91845.6" + attribute \src "libresoc.v:91873.3-91909.6" wire width 14 $1\dec31_dec_sub10_function_unit[13:0] - attribute \src "libresoc.v:92882.3-92918.6" + attribute \src "libresoc.v:92946.3-92982.6" wire width 3 $1\dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:92919.3-92955.6" + attribute \src "libresoc.v:92983.3-93019.6" wire width 4 $1\dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:92956.3-92992.6" + attribute \src "libresoc.v:93020.3-93056.6" wire width 2 $1\dec31_dec_sub10_in3_sel[1:0] - attribute \src "libresoc.v:92216.3-92252.6" + attribute \src "libresoc.v:92280.3-92316.6" wire width 7 $1\dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:92401.3-92437.6" + attribute \src "libresoc.v:92465.3-92501.6" wire $1\dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:92438.3-92474.6" + attribute \src "libresoc.v:92502.3-92538.6" wire $1\dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:92660.3-92696.6" + attribute \src "libresoc.v:92724.3-92760.6" wire $1\dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:92179.3-92215.6" + attribute \src "libresoc.v:92243.3-92279.6" wire width 4 $1\dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:92734.3-92770.6" + attribute \src "libresoc.v:92798.3-92834.6" wire $1\dec31_dec_sub10_lk[0:0] - attribute \src "libresoc.v:92993.3-93029.6" + attribute \src "libresoc.v:93057.3-93093.6" wire width 3 $1\dec31_dec_sub10_out_sel[2:0] - attribute \src "libresoc.v:92290.3-92326.6" + attribute \src "libresoc.v:92354.3-92390.6" wire width 2 $1\dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:92586.3-92622.6" + attribute \src "libresoc.v:92650.3-92686.6" wire $1\dec31_dec_sub10_rsrv[0:0] - attribute \src "libresoc.v:92771.3-92807.6" + attribute \src "libresoc.v:92835.3-92871.6" wire $1\dec31_dec_sub10_sgl_pipe[0:0] - attribute \src "libresoc.v:92697.3-92733.6" + attribute \src "libresoc.v:92761.3-92797.6" wire $1\dec31_dec_sub10_sgn[0:0] - attribute \src "libresoc.v:92549.3-92585.6" + attribute \src "libresoc.v:92613.3-92649.6" wire $1\dec31_dec_sub10_sgn_ext[0:0] - attribute \src "libresoc.v:92105.3-92141.6" + attribute \src "libresoc.v:92169.3-92205.6" wire width 3 $1\dec31_dec_sub10_sv_cr_in[2:0] - attribute \src "libresoc.v:92142.3-92178.6" + attribute \src "libresoc.v:92206.3-92242.6" wire width 3 $1\dec31_dec_sub10_sv_cr_out[2:0] - attribute \src "libresoc.v:91920.3-91956.6" + attribute \src "libresoc.v:91984.3-92020.6" wire width 3 $1\dec31_dec_sub10_sv_in1[2:0] - attribute \src "libresoc.v:91957.3-91993.6" + attribute \src "libresoc.v:92021.3-92057.6" wire width 3 $1\dec31_dec_sub10_sv_in2[2:0] - attribute \src "libresoc.v:91994.3-92030.6" + attribute \src "libresoc.v:92058.3-92094.6" wire width 3 $1\dec31_dec_sub10_sv_in3[2:0] - attribute \src "libresoc.v:92068.3-92104.6" + attribute \src "libresoc.v:92132.3-92168.6" wire width 3 $1\dec31_dec_sub10_sv_out2[2:0] - attribute \src "libresoc.v:92031.3-92067.6" + attribute \src "libresoc.v:92095.3-92131.6" wire width 3 $1\dec31_dec_sub10_sv_out[2:0] - attribute \src "libresoc.v:92253.3-92289.6" + attribute \src "libresoc.v:92317.3-92353.6" wire width 2 $1\dec31_dec_sub10_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -143566,28 +143617,28 @@ module \dec31_dec_sub10 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub10_upd - attribute \src "libresoc.v:91461.7-91461.15" + attribute \src "libresoc.v:91525.7-91525.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:91461.7-91461.20" - process $proc$libresoc.v:91461$3918 + attribute \src "libresoc.v:91525.7-91525.20" + process $proc$libresoc.v:91525$3918 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:91809.3-91845.6" - process $proc$libresoc.v:91809$3885 + attribute \src "libresoc.v:91873.3-91909.6" + process $proc$libresoc.v:91873$3885 assign { } { } assign { } { } assign $0\dec31_dec_sub10_function_unit[13:0] $1\dec31_dec_sub10_function_unit[13:0] - attribute \src "libresoc.v:91810.5-91810.29" + attribute \src "libresoc.v:91874.5-91874.29" switch \initial - attribute \src "libresoc.v:91810.9-91810.17" + attribute \src "libresoc.v:91874.9-91874.17" case 1'1 case end @@ -143639,14 +143690,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_function_unit $0\dec31_dec_sub10_function_unit[13:0] end - attribute \src "libresoc.v:91846.3-91882.6" - process $proc$libresoc.v:91846$3886 + attribute \src "libresoc.v:91910.3-91946.6" + process $proc$libresoc.v:91910$3886 assign { } { } assign { } { } assign $0\dec31_dec_sub10_cr_in[2:0] $1\dec31_dec_sub10_cr_in[2:0] - attribute \src "libresoc.v:91847.5-91847.29" + attribute \src "libresoc.v:91911.5-91911.29" switch \initial - attribute \src "libresoc.v:91847.9-91847.17" + attribute \src "libresoc.v:91911.9-91911.17" case 1'1 case end @@ -143698,14 +143749,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_cr_in $0\dec31_dec_sub10_cr_in[2:0] end - attribute \src "libresoc.v:91883.3-91919.6" - process $proc$libresoc.v:91883$3887 + attribute \src "libresoc.v:91947.3-91983.6" + process $proc$libresoc.v:91947$3887 assign { } { } assign { } { } assign $0\dec31_dec_sub10_cr_out[2:0] $1\dec31_dec_sub10_cr_out[2:0] - attribute \src "libresoc.v:91884.5-91884.29" + attribute \src "libresoc.v:91948.5-91948.29" switch \initial - attribute \src "libresoc.v:91884.9-91884.17" + attribute \src "libresoc.v:91948.9-91948.17" case 1'1 case end @@ -143757,14 +143808,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_cr_out $0\dec31_dec_sub10_cr_out[2:0] end - attribute \src "libresoc.v:91920.3-91956.6" - process $proc$libresoc.v:91920$3888 + attribute \src "libresoc.v:91984.3-92020.6" + process $proc$libresoc.v:91984$3888 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_in1[2:0] $1\dec31_dec_sub10_sv_in1[2:0] - attribute \src "libresoc.v:91921.5-91921.29" + attribute \src "libresoc.v:91985.5-91985.29" switch \initial - attribute \src "libresoc.v:91921.9-91921.17" + attribute \src "libresoc.v:91985.9-91985.17" case 1'1 case end @@ -143816,14 +143867,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_in1 $0\dec31_dec_sub10_sv_in1[2:0] end - attribute \src "libresoc.v:91957.3-91993.6" - process $proc$libresoc.v:91957$3889 + attribute \src "libresoc.v:92021.3-92057.6" + process $proc$libresoc.v:92021$3889 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_in2[2:0] $1\dec31_dec_sub10_sv_in2[2:0] - attribute \src "libresoc.v:91958.5-91958.29" + attribute \src "libresoc.v:92022.5-92022.29" switch \initial - attribute \src "libresoc.v:91958.9-91958.17" + attribute \src "libresoc.v:92022.9-92022.17" case 1'1 case end @@ -143875,14 +143926,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_in2 $0\dec31_dec_sub10_sv_in2[2:0] end - attribute \src "libresoc.v:91994.3-92030.6" - process $proc$libresoc.v:91994$3890 + attribute \src "libresoc.v:92058.3-92094.6" + process $proc$libresoc.v:92058$3890 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_in3[2:0] $1\dec31_dec_sub10_sv_in3[2:0] - attribute \src "libresoc.v:91995.5-91995.29" + attribute \src "libresoc.v:92059.5-92059.29" switch \initial - attribute \src "libresoc.v:91995.9-91995.17" + attribute \src "libresoc.v:92059.9-92059.17" case 1'1 case end @@ -143934,14 +143985,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_in3 $0\dec31_dec_sub10_sv_in3[2:0] end - attribute \src "libresoc.v:92031.3-92067.6" - process $proc$libresoc.v:92031$3891 + attribute \src "libresoc.v:92095.3-92131.6" + process $proc$libresoc.v:92095$3891 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_out[2:0] $1\dec31_dec_sub10_sv_out[2:0] - attribute \src "libresoc.v:92032.5-92032.29" + attribute \src "libresoc.v:92096.5-92096.29" switch \initial - attribute \src "libresoc.v:92032.9-92032.17" + attribute \src "libresoc.v:92096.9-92096.17" case 1'1 case end @@ -143993,14 +144044,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_out $0\dec31_dec_sub10_sv_out[2:0] end - attribute \src "libresoc.v:92068.3-92104.6" - process $proc$libresoc.v:92068$3892 + attribute \src "libresoc.v:92132.3-92168.6" + process $proc$libresoc.v:92132$3892 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_out2[2:0] $1\dec31_dec_sub10_sv_out2[2:0] - attribute \src "libresoc.v:92069.5-92069.29" + attribute \src "libresoc.v:92133.5-92133.29" switch \initial - attribute \src "libresoc.v:92069.9-92069.17" + attribute \src "libresoc.v:92133.9-92133.17" case 1'1 case end @@ -144052,14 +144103,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_out2 $0\dec31_dec_sub10_sv_out2[2:0] end - attribute \src "libresoc.v:92105.3-92141.6" - process $proc$libresoc.v:92105$3893 + attribute \src "libresoc.v:92169.3-92205.6" + process $proc$libresoc.v:92169$3893 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_cr_in[2:0] $1\dec31_dec_sub10_sv_cr_in[2:0] - attribute \src "libresoc.v:92106.5-92106.29" + attribute \src "libresoc.v:92170.5-92170.29" switch \initial - attribute \src "libresoc.v:92106.9-92106.17" + attribute \src "libresoc.v:92170.9-92170.17" case 1'1 case end @@ -144111,14 +144162,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_cr_in $0\dec31_dec_sub10_sv_cr_in[2:0] end - attribute \src "libresoc.v:92142.3-92178.6" - process $proc$libresoc.v:92142$3894 + attribute \src "libresoc.v:92206.3-92242.6" + process $proc$libresoc.v:92206$3894 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sv_cr_out[2:0] $1\dec31_dec_sub10_sv_cr_out[2:0] - attribute \src "libresoc.v:92143.5-92143.29" + attribute \src "libresoc.v:92207.5-92207.29" switch \initial - attribute \src "libresoc.v:92143.9-92143.17" + attribute \src "libresoc.v:92207.9-92207.17" case 1'1 case end @@ -144170,14 +144221,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sv_cr_out $0\dec31_dec_sub10_sv_cr_out[2:0] end - attribute \src "libresoc.v:92179.3-92215.6" - process $proc$libresoc.v:92179$3895 + attribute \src "libresoc.v:92243.3-92279.6" + process $proc$libresoc.v:92243$3895 assign { } { } assign { } { } assign $0\dec31_dec_sub10_ldst_len[3:0] $1\dec31_dec_sub10_ldst_len[3:0] - attribute \src "libresoc.v:92180.5-92180.29" + attribute \src "libresoc.v:92244.5-92244.29" switch \initial - attribute \src "libresoc.v:92180.9-92180.17" + attribute \src "libresoc.v:92244.9-92244.17" case 1'1 case end @@ -144229,14 +144280,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_ldst_len $0\dec31_dec_sub10_ldst_len[3:0] end - attribute \src "libresoc.v:92216.3-92252.6" - process $proc$libresoc.v:92216$3896 + attribute \src "libresoc.v:92280.3-92316.6" + process $proc$libresoc.v:92280$3896 assign { } { } assign { } { } assign $0\dec31_dec_sub10_internal_op[6:0] $1\dec31_dec_sub10_internal_op[6:0] - attribute \src "libresoc.v:92217.5-92217.29" + attribute \src "libresoc.v:92281.5-92281.29" switch \initial - attribute \src "libresoc.v:92217.9-92217.17" + attribute \src "libresoc.v:92281.9-92281.17" case 1'1 case end @@ -144288,14 +144339,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_internal_op $0\dec31_dec_sub10_internal_op[6:0] end - attribute \src "libresoc.v:92253.3-92289.6" - process $proc$libresoc.v:92253$3897 + attribute \src "libresoc.v:92317.3-92353.6" + process $proc$libresoc.v:92317$3897 assign { } { } assign { } { } assign $0\dec31_dec_sub10_upd[1:0] $1\dec31_dec_sub10_upd[1:0] - attribute \src "libresoc.v:92254.5-92254.29" + attribute \src "libresoc.v:92318.5-92318.29" switch \initial - attribute \src "libresoc.v:92254.9-92254.17" + attribute \src "libresoc.v:92318.9-92318.17" case 1'1 case end @@ -144347,14 +144398,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_upd $0\dec31_dec_sub10_upd[1:0] end - attribute \src "libresoc.v:92290.3-92326.6" - process $proc$libresoc.v:92290$3898 + attribute \src "libresoc.v:92354.3-92390.6" + process $proc$libresoc.v:92354$3898 assign { } { } assign { } { } assign $0\dec31_dec_sub10_rc_sel[1:0] $1\dec31_dec_sub10_rc_sel[1:0] - attribute \src "libresoc.v:92291.5-92291.29" + attribute \src "libresoc.v:92355.5-92355.29" switch \initial - attribute \src "libresoc.v:92291.9-92291.17" + attribute \src "libresoc.v:92355.9-92355.17" case 1'1 case end @@ -144406,14 +144457,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_rc_sel $0\dec31_dec_sub10_rc_sel[1:0] end - attribute \src "libresoc.v:92327.3-92363.6" - process $proc$libresoc.v:92327$3899 + attribute \src "libresoc.v:92391.3-92427.6" + process $proc$libresoc.v:92391$3899 assign { } { } assign { } { } assign $0\dec31_dec_sub10_cry_in[1:0] $1\dec31_dec_sub10_cry_in[1:0] - attribute \src "libresoc.v:92328.5-92328.29" + attribute \src "libresoc.v:92392.5-92392.29" switch \initial - attribute \src "libresoc.v:92328.9-92328.17" + attribute \src "libresoc.v:92392.9-92392.17" case 1'1 case end @@ -144465,14 +144516,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_cry_in $0\dec31_dec_sub10_cry_in[1:0] end - attribute \src "libresoc.v:92364.3-92400.6" - process $proc$libresoc.v:92364$3900 + attribute \src "libresoc.v:92428.3-92464.6" + process $proc$libresoc.v:92428$3900 assign { } { } assign { } { } assign $0\dec31_dec_sub10_asmcode[7:0] $1\dec31_dec_sub10_asmcode[7:0] - attribute \src "libresoc.v:92365.5-92365.29" + attribute \src "libresoc.v:92429.5-92429.29" switch \initial - attribute \src "libresoc.v:92365.9-92365.17" + attribute \src "libresoc.v:92429.9-92429.17" case 1'1 case end @@ -144524,14 +144575,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_asmcode $0\dec31_dec_sub10_asmcode[7:0] end - attribute \src "libresoc.v:92401.3-92437.6" - process $proc$libresoc.v:92401$3901 + attribute \src "libresoc.v:92465.3-92501.6" + process $proc$libresoc.v:92465$3901 assign { } { } assign { } { } assign $0\dec31_dec_sub10_inv_a[0:0] $1\dec31_dec_sub10_inv_a[0:0] - attribute \src "libresoc.v:92402.5-92402.29" + attribute \src "libresoc.v:92466.5-92466.29" switch \initial - attribute \src "libresoc.v:92402.9-92402.17" + attribute \src "libresoc.v:92466.9-92466.17" case 1'1 case end @@ -144583,14 +144634,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_inv_a $0\dec31_dec_sub10_inv_a[0:0] end - attribute \src "libresoc.v:92438.3-92474.6" - process $proc$libresoc.v:92438$3902 + attribute \src "libresoc.v:92502.3-92538.6" + process $proc$libresoc.v:92502$3902 assign { } { } assign { } { } assign $0\dec31_dec_sub10_inv_out[0:0] $1\dec31_dec_sub10_inv_out[0:0] - attribute \src "libresoc.v:92439.5-92439.29" + attribute \src "libresoc.v:92503.5-92503.29" switch \initial - attribute \src "libresoc.v:92439.9-92439.17" + attribute \src "libresoc.v:92503.9-92503.17" case 1'1 case end @@ -144642,14 +144693,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_inv_out $0\dec31_dec_sub10_inv_out[0:0] end - attribute \src "libresoc.v:92475.3-92511.6" - process $proc$libresoc.v:92475$3903 + attribute \src "libresoc.v:92539.3-92575.6" + process $proc$libresoc.v:92539$3903 assign { } { } assign { } { } assign $0\dec31_dec_sub10_cry_out[0:0] $1\dec31_dec_sub10_cry_out[0:0] - attribute \src "libresoc.v:92476.5-92476.29" + attribute \src "libresoc.v:92540.5-92540.29" switch \initial - attribute \src "libresoc.v:92476.9-92476.17" + attribute \src "libresoc.v:92540.9-92540.17" case 1'1 case end @@ -144701,14 +144752,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_cry_out $0\dec31_dec_sub10_cry_out[0:0] end - attribute \src "libresoc.v:92512.3-92548.6" - process $proc$libresoc.v:92512$3904 + attribute \src "libresoc.v:92576.3-92612.6" + process $proc$libresoc.v:92576$3904 assign { } { } assign { } { } assign $0\dec31_dec_sub10_br[0:0] $1\dec31_dec_sub10_br[0:0] - attribute \src "libresoc.v:92513.5-92513.29" + attribute \src "libresoc.v:92577.5-92577.29" switch \initial - attribute \src "libresoc.v:92513.9-92513.17" + attribute \src "libresoc.v:92577.9-92577.17" case 1'1 case end @@ -144760,14 +144811,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_br $0\dec31_dec_sub10_br[0:0] end - attribute \src "libresoc.v:92549.3-92585.6" - process $proc$libresoc.v:92549$3905 + attribute \src "libresoc.v:92613.3-92649.6" + process $proc$libresoc.v:92613$3905 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sgn_ext[0:0] $1\dec31_dec_sub10_sgn_ext[0:0] - attribute \src "libresoc.v:92550.5-92550.29" + attribute \src "libresoc.v:92614.5-92614.29" switch \initial - attribute \src "libresoc.v:92550.9-92550.17" + attribute \src "libresoc.v:92614.9-92614.17" case 1'1 case end @@ -144819,14 +144870,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sgn_ext $0\dec31_dec_sub10_sgn_ext[0:0] end - attribute \src "libresoc.v:92586.3-92622.6" - process $proc$libresoc.v:92586$3906 + attribute \src "libresoc.v:92650.3-92686.6" + process $proc$libresoc.v:92650$3906 assign { } { } assign { } { } assign $0\dec31_dec_sub10_rsrv[0:0] $1\dec31_dec_sub10_rsrv[0:0] - attribute \src "libresoc.v:92587.5-92587.29" + attribute \src "libresoc.v:92651.5-92651.29" switch \initial - attribute \src "libresoc.v:92587.9-92587.17" + attribute \src "libresoc.v:92651.9-92651.17" case 1'1 case end @@ -144878,14 +144929,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_rsrv $0\dec31_dec_sub10_rsrv[0:0] end - attribute \src "libresoc.v:92623.3-92659.6" - process $proc$libresoc.v:92623$3907 + attribute \src "libresoc.v:92687.3-92723.6" + process $proc$libresoc.v:92687$3907 assign { } { } assign { } { } assign $0\dec31_dec_sub10_form[4:0] $1\dec31_dec_sub10_form[4:0] - attribute \src "libresoc.v:92624.5-92624.29" + attribute \src "libresoc.v:92688.5-92688.29" switch \initial - attribute \src "libresoc.v:92624.9-92624.17" + attribute \src "libresoc.v:92688.9-92688.17" case 1'1 case end @@ -144937,14 +144988,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_form $0\dec31_dec_sub10_form[4:0] end - attribute \src "libresoc.v:92660.3-92696.6" - process $proc$libresoc.v:92660$3908 + attribute \src "libresoc.v:92724.3-92760.6" + process $proc$libresoc.v:92724$3908 assign { } { } assign { } { } assign $0\dec31_dec_sub10_is_32b[0:0] $1\dec31_dec_sub10_is_32b[0:0] - attribute \src "libresoc.v:92661.5-92661.29" + attribute \src "libresoc.v:92725.5-92725.29" switch \initial - attribute \src "libresoc.v:92661.9-92661.17" + attribute \src "libresoc.v:92725.9-92725.17" case 1'1 case end @@ -144996,14 +145047,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_is_32b $0\dec31_dec_sub10_is_32b[0:0] end - attribute \src "libresoc.v:92697.3-92733.6" - process $proc$libresoc.v:92697$3909 + attribute \src "libresoc.v:92761.3-92797.6" + process $proc$libresoc.v:92761$3909 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sgn[0:0] $1\dec31_dec_sub10_sgn[0:0] - attribute \src "libresoc.v:92698.5-92698.29" + attribute \src "libresoc.v:92762.5-92762.29" switch \initial - attribute \src "libresoc.v:92698.9-92698.17" + attribute \src "libresoc.v:92762.9-92762.17" case 1'1 case end @@ -145055,14 +145106,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sgn $0\dec31_dec_sub10_sgn[0:0] end - attribute \src "libresoc.v:92734.3-92770.6" - process $proc$libresoc.v:92734$3910 + attribute \src "libresoc.v:92798.3-92834.6" + process $proc$libresoc.v:92798$3910 assign { } { } assign { } { } assign $0\dec31_dec_sub10_lk[0:0] $1\dec31_dec_sub10_lk[0:0] - attribute \src "libresoc.v:92735.5-92735.29" + attribute \src "libresoc.v:92799.5-92799.29" switch \initial - attribute \src "libresoc.v:92735.9-92735.17" + attribute \src "libresoc.v:92799.9-92799.17" case 1'1 case end @@ -145114,14 +145165,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_lk $0\dec31_dec_sub10_lk[0:0] end - attribute \src "libresoc.v:92771.3-92807.6" - process $proc$libresoc.v:92771$3911 + attribute \src "libresoc.v:92835.3-92871.6" + process $proc$libresoc.v:92835$3911 assign { } { } assign { } { } assign $0\dec31_dec_sub10_sgl_pipe[0:0] $1\dec31_dec_sub10_sgl_pipe[0:0] - attribute \src "libresoc.v:92772.5-92772.29" + attribute \src "libresoc.v:92836.5-92836.29" switch \initial - attribute \src "libresoc.v:92772.9-92772.17" + attribute \src "libresoc.v:92836.9-92836.17" case 1'1 case end @@ -145173,14 +145224,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_sgl_pipe $0\dec31_dec_sub10_sgl_pipe[0:0] end - attribute \src "libresoc.v:92808.3-92844.6" - process $proc$libresoc.v:92808$3912 + attribute \src "libresoc.v:92872.3-92908.6" + process $proc$libresoc.v:92872$3912 assign { } { } assign { } { } assign $0\dec31_dec_sub10_SV_Etype[1:0] $1\dec31_dec_sub10_SV_Etype[1:0] - attribute \src "libresoc.v:92809.5-92809.29" + attribute \src "libresoc.v:92873.5-92873.29" switch \initial - attribute \src "libresoc.v:92809.9-92809.17" + attribute \src "libresoc.v:92873.9-92873.17" case 1'1 case end @@ -145232,14 +145283,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_SV_Etype $0\dec31_dec_sub10_SV_Etype[1:0] end - attribute \src "libresoc.v:92845.3-92881.6" - process $proc$libresoc.v:92845$3913 + attribute \src "libresoc.v:92909.3-92945.6" + process $proc$libresoc.v:92909$3913 assign { } { } assign { } { } assign $0\dec31_dec_sub10_SV_Ptype[1:0] $1\dec31_dec_sub10_SV_Ptype[1:0] - attribute \src "libresoc.v:92846.5-92846.29" + attribute \src "libresoc.v:92910.5-92910.29" switch \initial - attribute \src "libresoc.v:92846.9-92846.17" + attribute \src "libresoc.v:92910.9-92910.17" case 1'1 case end @@ -145291,14 +145342,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_SV_Ptype $0\dec31_dec_sub10_SV_Ptype[1:0] end - attribute \src "libresoc.v:92882.3-92918.6" - process $proc$libresoc.v:92882$3914 + attribute \src "libresoc.v:92946.3-92982.6" + process $proc$libresoc.v:92946$3914 assign { } { } assign { } { } assign $0\dec31_dec_sub10_in1_sel[2:0] $1\dec31_dec_sub10_in1_sel[2:0] - attribute \src "libresoc.v:92883.5-92883.29" + attribute \src "libresoc.v:92947.5-92947.29" switch \initial - attribute \src "libresoc.v:92883.9-92883.17" + attribute \src "libresoc.v:92947.9-92947.17" case 1'1 case end @@ -145350,14 +145401,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_in1_sel $0\dec31_dec_sub10_in1_sel[2:0] end - attribute \src "libresoc.v:92919.3-92955.6" - process $proc$libresoc.v:92919$3915 + attribute \src "libresoc.v:92983.3-93019.6" + process $proc$libresoc.v:92983$3915 assign { } { } assign { } { } assign $0\dec31_dec_sub10_in2_sel[3:0] $1\dec31_dec_sub10_in2_sel[3:0] - attribute \src "libresoc.v:92920.5-92920.29" + attribute \src "libresoc.v:92984.5-92984.29" switch \initial - attribute \src "libresoc.v:92920.9-92920.17" + attribute \src "libresoc.v:92984.9-92984.17" case 1'1 case end @@ -145409,14 +145460,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_in2_sel $0\dec31_dec_sub10_in2_sel[3:0] end - attribute \src "libresoc.v:92956.3-92992.6" - process $proc$libresoc.v:92956$3916 + attribute \src "libresoc.v:93020.3-93056.6" + process $proc$libresoc.v:93020$3916 assign { } { } assign { } { } assign $0\dec31_dec_sub10_in3_sel[1:0] $1\dec31_dec_sub10_in3_sel[1:0] - attribute \src "libresoc.v:92957.5-92957.29" + attribute \src "libresoc.v:93021.5-93021.29" switch \initial - attribute \src "libresoc.v:92957.9-92957.17" + attribute \src "libresoc.v:93021.9-93021.17" case 1'1 case end @@ -145468,14 +145519,14 @@ module \dec31_dec_sub10 sync always update \dec31_dec_sub10_in3_sel $0\dec31_dec_sub10_in3_sel[1:0] end - attribute \src "libresoc.v:92993.3-93029.6" - process $proc$libresoc.v:92993$3917 + attribute \src "libresoc.v:93057.3-93093.6" + process $proc$libresoc.v:93057$3917 assign { } { } assign { } { } assign $0\dec31_dec_sub10_out_sel[2:0] $1\dec31_dec_sub10_out_sel[2:0] - attribute \src "libresoc.v:92994.5-92994.29" + attribute \src "libresoc.v:93058.5-93058.29" switch \initial - attribute \src "libresoc.v:92994.9-92994.17" + attribute \src "libresoc.v:93058.9-93058.17" case 1'1 case end @@ -145529,144 +145580,144 @@ module \dec31_dec_sub10 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:93035.1-95200.10" +attribute \src "libresoc.v:93099.1-95264.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub11" attribute \generator "nMigen" module \dec31_dec_sub11 - attribute \src "libresoc.v:94869.3-94923.6" + attribute \src "libresoc.v:94933.3-94987.6" wire width 2 $0\dec31_dec_sub11_SV_Etype[1:0] - attribute \src "libresoc.v:94924.3-94978.6" + attribute \src "libresoc.v:94988.3-95042.6" wire width 2 $0\dec31_dec_sub11_SV_Ptype[1:0] - attribute \src "libresoc.v:94209.3-94263.6" + attribute \src "libresoc.v:94273.3-94327.6" wire width 8 $0\dec31_dec_sub11_asmcode[7:0] - attribute \src "libresoc.v:94429.3-94483.6" + attribute \src "libresoc.v:94493.3-94547.6" wire $0\dec31_dec_sub11_br[0:0] - attribute \src "libresoc.v:93439.3-93493.6" + attribute \src "libresoc.v:93503.3-93557.6" wire width 3 $0\dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:93494.3-93548.6" + attribute \src "libresoc.v:93558.3-93612.6" wire width 3 $0\dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:94154.3-94208.6" + attribute \src "libresoc.v:94218.3-94272.6" wire width 2 $0\dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:94374.3-94428.6" + attribute \src "libresoc.v:94438.3-94492.6" wire $0\dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:94594.3-94648.6" + attribute \src "libresoc.v:94658.3-94712.6" wire width 5 $0\dec31_dec_sub11_form[4:0] - attribute \src "libresoc.v:93384.3-93438.6" + attribute \src "libresoc.v:93448.3-93502.6" wire width 14 $0\dec31_dec_sub11_function_unit[13:0] - attribute \src "libresoc.v:94979.3-95033.6" + attribute \src "libresoc.v:95043.3-95097.6" wire width 3 $0\dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:95034.3-95088.6" + attribute \src "libresoc.v:95098.3-95152.6" wire width 4 $0\dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:95089.3-95143.6" + attribute \src "libresoc.v:95153.3-95207.6" wire width 2 $0\dec31_dec_sub11_in3_sel[1:0] - attribute \src "libresoc.v:93989.3-94043.6" + attribute \src "libresoc.v:94053.3-94107.6" wire width 7 $0\dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:94264.3-94318.6" + attribute \src "libresoc.v:94328.3-94382.6" wire $0\dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:94319.3-94373.6" + attribute \src "libresoc.v:94383.3-94437.6" wire $0\dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:94649.3-94703.6" + attribute \src "libresoc.v:94713.3-94767.6" wire $0\dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:93934.3-93988.6" + attribute \src "libresoc.v:93998.3-94052.6" wire width 4 $0\dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:94759.3-94813.6" + attribute \src "libresoc.v:94823.3-94877.6" wire $0\dec31_dec_sub11_lk[0:0] - attribute \src "libresoc.v:95144.3-95198.6" + attribute \src "libresoc.v:95208.3-95262.6" wire width 3 $0\dec31_dec_sub11_out_sel[2:0] - attribute \src "libresoc.v:94099.3-94153.6" + attribute \src "libresoc.v:94163.3-94217.6" wire width 2 $0\dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:94539.3-94593.6" + attribute \src "libresoc.v:94603.3-94657.6" wire $0\dec31_dec_sub11_rsrv[0:0] - attribute \src "libresoc.v:94814.3-94868.6" + attribute \src "libresoc.v:94878.3-94932.6" wire $0\dec31_dec_sub11_sgl_pipe[0:0] - attribute \src "libresoc.v:94704.3-94758.6" + attribute \src "libresoc.v:94768.3-94822.6" wire $0\dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:94484.3-94538.6" + attribute \src "libresoc.v:94548.3-94602.6" wire $0\dec31_dec_sub11_sgn_ext[0:0] - attribute \src "libresoc.v:93824.3-93878.6" + attribute \src "libresoc.v:93888.3-93942.6" wire width 3 $0\dec31_dec_sub11_sv_cr_in[2:0] - attribute \src "libresoc.v:93879.3-93933.6" + attribute \src "libresoc.v:93943.3-93997.6" wire width 3 $0\dec31_dec_sub11_sv_cr_out[2:0] - attribute \src "libresoc.v:93549.3-93603.6" + attribute \src "libresoc.v:93613.3-93667.6" wire width 3 $0\dec31_dec_sub11_sv_in1[2:0] - attribute \src "libresoc.v:93604.3-93658.6" + attribute \src "libresoc.v:93668.3-93722.6" wire width 3 $0\dec31_dec_sub11_sv_in2[2:0] - attribute \src "libresoc.v:93659.3-93713.6" + attribute \src "libresoc.v:93723.3-93777.6" wire width 3 $0\dec31_dec_sub11_sv_in3[2:0] - attribute \src "libresoc.v:93769.3-93823.6" + attribute \src "libresoc.v:93833.3-93887.6" wire width 3 $0\dec31_dec_sub11_sv_out2[2:0] - attribute \src "libresoc.v:93714.3-93768.6" + attribute \src "libresoc.v:93778.3-93832.6" wire width 3 $0\dec31_dec_sub11_sv_out[2:0] - attribute \src "libresoc.v:94044.3-94098.6" + attribute \src "libresoc.v:94108.3-94162.6" wire width 2 $0\dec31_dec_sub11_upd[1:0] - attribute \src "libresoc.v:93036.7-93036.20" + attribute \src "libresoc.v:93100.7-93100.20" wire $0\initial[0:0] - attribute \src "libresoc.v:94869.3-94923.6" + attribute \src "libresoc.v:94933.3-94987.6" wire width 2 $1\dec31_dec_sub11_SV_Etype[1:0] - attribute \src "libresoc.v:94924.3-94978.6" + attribute \src "libresoc.v:94988.3-95042.6" wire width 2 $1\dec31_dec_sub11_SV_Ptype[1:0] - attribute \src "libresoc.v:94209.3-94263.6" + attribute \src "libresoc.v:94273.3-94327.6" wire width 8 $1\dec31_dec_sub11_asmcode[7:0] - attribute \src "libresoc.v:94429.3-94483.6" + attribute \src "libresoc.v:94493.3-94547.6" wire $1\dec31_dec_sub11_br[0:0] - attribute \src "libresoc.v:93439.3-93493.6" + attribute \src "libresoc.v:93503.3-93557.6" wire width 3 $1\dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:93494.3-93548.6" + attribute \src "libresoc.v:93558.3-93612.6" wire width 3 $1\dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:94154.3-94208.6" + attribute \src "libresoc.v:94218.3-94272.6" wire width 2 $1\dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:94374.3-94428.6" + attribute \src "libresoc.v:94438.3-94492.6" wire $1\dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:94594.3-94648.6" + attribute \src "libresoc.v:94658.3-94712.6" wire width 5 $1\dec31_dec_sub11_form[4:0] - attribute \src "libresoc.v:93384.3-93438.6" + attribute \src "libresoc.v:93448.3-93502.6" wire width 14 $1\dec31_dec_sub11_function_unit[13:0] - attribute \src "libresoc.v:94979.3-95033.6" + attribute \src "libresoc.v:95043.3-95097.6" wire width 3 $1\dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:95034.3-95088.6" + attribute \src "libresoc.v:95098.3-95152.6" wire width 4 $1\dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:95089.3-95143.6" + attribute \src "libresoc.v:95153.3-95207.6" wire width 2 $1\dec31_dec_sub11_in3_sel[1:0] - attribute \src "libresoc.v:93989.3-94043.6" + attribute \src "libresoc.v:94053.3-94107.6" wire width 7 $1\dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:94264.3-94318.6" + attribute \src "libresoc.v:94328.3-94382.6" wire $1\dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:94319.3-94373.6" + attribute \src "libresoc.v:94383.3-94437.6" wire $1\dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:94649.3-94703.6" + attribute \src "libresoc.v:94713.3-94767.6" wire $1\dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:93934.3-93988.6" + attribute \src "libresoc.v:93998.3-94052.6" wire width 4 $1\dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:94759.3-94813.6" + attribute \src "libresoc.v:94823.3-94877.6" wire $1\dec31_dec_sub11_lk[0:0] - attribute \src "libresoc.v:95144.3-95198.6" + attribute \src "libresoc.v:95208.3-95262.6" wire width 3 $1\dec31_dec_sub11_out_sel[2:0] - attribute \src "libresoc.v:94099.3-94153.6" + attribute \src "libresoc.v:94163.3-94217.6" wire width 2 $1\dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:94539.3-94593.6" + attribute \src "libresoc.v:94603.3-94657.6" wire $1\dec31_dec_sub11_rsrv[0:0] - attribute \src "libresoc.v:94814.3-94868.6" + attribute \src "libresoc.v:94878.3-94932.6" wire $1\dec31_dec_sub11_sgl_pipe[0:0] - attribute \src "libresoc.v:94704.3-94758.6" + attribute \src "libresoc.v:94768.3-94822.6" wire $1\dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:94484.3-94538.6" + attribute \src "libresoc.v:94548.3-94602.6" wire $1\dec31_dec_sub11_sgn_ext[0:0] - attribute \src "libresoc.v:93824.3-93878.6" + attribute \src "libresoc.v:93888.3-93942.6" wire width 3 $1\dec31_dec_sub11_sv_cr_in[2:0] - attribute \src "libresoc.v:93879.3-93933.6" + attribute \src "libresoc.v:93943.3-93997.6" wire width 3 $1\dec31_dec_sub11_sv_cr_out[2:0] - attribute \src "libresoc.v:93549.3-93603.6" + attribute \src "libresoc.v:93613.3-93667.6" wire width 3 $1\dec31_dec_sub11_sv_in1[2:0] - attribute \src "libresoc.v:93604.3-93658.6" + attribute \src "libresoc.v:93668.3-93722.6" wire width 3 $1\dec31_dec_sub11_sv_in2[2:0] - attribute \src "libresoc.v:93659.3-93713.6" + attribute \src "libresoc.v:93723.3-93777.6" wire width 3 $1\dec31_dec_sub11_sv_in3[2:0] - attribute \src "libresoc.v:93769.3-93823.6" + attribute \src "libresoc.v:93833.3-93887.6" wire width 3 $1\dec31_dec_sub11_sv_out2[2:0] - attribute \src "libresoc.v:93714.3-93768.6" + attribute \src "libresoc.v:93778.3-93832.6" wire width 3 $1\dec31_dec_sub11_sv_out[2:0] - attribute \src "libresoc.v:94044.3-94098.6" + attribute \src "libresoc.v:94108.3-94162.6" wire width 2 $1\dec31_dec_sub11_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -145978,28 +146029,28 @@ module \dec31_dec_sub11 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub11_upd - attribute \src "libresoc.v:93036.7-93036.15" + attribute \src "libresoc.v:93100.7-93100.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:93036.7-93036.20" - process $proc$libresoc.v:93036$3952 + attribute \src "libresoc.v:93100.7-93100.20" + process $proc$libresoc.v:93100$3952 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:93384.3-93438.6" - process $proc$libresoc.v:93384$3919 + attribute \src "libresoc.v:93448.3-93502.6" + process $proc$libresoc.v:93448$3919 assign { } { } assign { } { } assign $0\dec31_dec_sub11_function_unit[13:0] $1\dec31_dec_sub11_function_unit[13:0] - attribute \src "libresoc.v:93385.5-93385.29" + attribute \src "libresoc.v:93449.5-93449.29" switch \initial - attribute \src "libresoc.v:93385.9-93385.17" + attribute \src "libresoc.v:93449.9-93449.17" case 1'1 case end @@ -146075,14 +146126,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_function_unit $0\dec31_dec_sub11_function_unit[13:0] end - attribute \src "libresoc.v:93439.3-93493.6" - process $proc$libresoc.v:93439$3920 + attribute \src "libresoc.v:93503.3-93557.6" + process $proc$libresoc.v:93503$3920 assign { } { } assign { } { } assign $0\dec31_dec_sub11_cr_in[2:0] $1\dec31_dec_sub11_cr_in[2:0] - attribute \src "libresoc.v:93440.5-93440.29" + attribute \src "libresoc.v:93504.5-93504.29" switch \initial - attribute \src "libresoc.v:93440.9-93440.17" + attribute \src "libresoc.v:93504.9-93504.17" case 1'1 case end @@ -146158,14 +146209,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_cr_in $0\dec31_dec_sub11_cr_in[2:0] end - attribute \src "libresoc.v:93494.3-93548.6" - process $proc$libresoc.v:93494$3921 + attribute \src "libresoc.v:93558.3-93612.6" + process $proc$libresoc.v:93558$3921 assign { } { } assign { } { } assign $0\dec31_dec_sub11_cr_out[2:0] $1\dec31_dec_sub11_cr_out[2:0] - attribute \src "libresoc.v:93495.5-93495.29" + attribute \src "libresoc.v:93559.5-93559.29" switch \initial - attribute \src "libresoc.v:93495.9-93495.17" + attribute \src "libresoc.v:93559.9-93559.17" case 1'1 case end @@ -146241,14 +146292,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_cr_out $0\dec31_dec_sub11_cr_out[2:0] end - attribute \src "libresoc.v:93549.3-93603.6" - process $proc$libresoc.v:93549$3922 + attribute \src "libresoc.v:93613.3-93667.6" + process $proc$libresoc.v:93613$3922 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_in1[2:0] $1\dec31_dec_sub11_sv_in1[2:0] - attribute \src "libresoc.v:93550.5-93550.29" + attribute \src "libresoc.v:93614.5-93614.29" switch \initial - attribute \src "libresoc.v:93550.9-93550.17" + attribute \src "libresoc.v:93614.9-93614.17" case 1'1 case end @@ -146324,14 +146375,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_in1 $0\dec31_dec_sub11_sv_in1[2:0] end - attribute \src "libresoc.v:93604.3-93658.6" - process $proc$libresoc.v:93604$3923 + attribute \src "libresoc.v:93668.3-93722.6" + process $proc$libresoc.v:93668$3923 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_in2[2:0] $1\dec31_dec_sub11_sv_in2[2:0] - attribute \src "libresoc.v:93605.5-93605.29" + attribute \src "libresoc.v:93669.5-93669.29" switch \initial - attribute \src "libresoc.v:93605.9-93605.17" + attribute \src "libresoc.v:93669.9-93669.17" case 1'1 case end @@ -146407,14 +146458,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_in2 $0\dec31_dec_sub11_sv_in2[2:0] end - attribute \src "libresoc.v:93659.3-93713.6" - process $proc$libresoc.v:93659$3924 + attribute \src "libresoc.v:93723.3-93777.6" + process $proc$libresoc.v:93723$3924 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_in3[2:0] $1\dec31_dec_sub11_sv_in3[2:0] - attribute \src "libresoc.v:93660.5-93660.29" + attribute \src "libresoc.v:93724.5-93724.29" switch \initial - attribute \src "libresoc.v:93660.9-93660.17" + attribute \src "libresoc.v:93724.9-93724.17" case 1'1 case end @@ -146490,14 +146541,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_in3 $0\dec31_dec_sub11_sv_in3[2:0] end - attribute \src "libresoc.v:93714.3-93768.6" - process $proc$libresoc.v:93714$3925 + attribute \src "libresoc.v:93778.3-93832.6" + process $proc$libresoc.v:93778$3925 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_out[2:0] $1\dec31_dec_sub11_sv_out[2:0] - attribute \src "libresoc.v:93715.5-93715.29" + attribute \src "libresoc.v:93779.5-93779.29" switch \initial - attribute \src "libresoc.v:93715.9-93715.17" + attribute \src "libresoc.v:93779.9-93779.17" case 1'1 case end @@ -146573,14 +146624,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_out $0\dec31_dec_sub11_sv_out[2:0] end - attribute \src "libresoc.v:93769.3-93823.6" - process $proc$libresoc.v:93769$3926 + attribute \src "libresoc.v:93833.3-93887.6" + process $proc$libresoc.v:93833$3926 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_out2[2:0] $1\dec31_dec_sub11_sv_out2[2:0] - attribute \src "libresoc.v:93770.5-93770.29" + attribute \src "libresoc.v:93834.5-93834.29" switch \initial - attribute \src "libresoc.v:93770.9-93770.17" + attribute \src "libresoc.v:93834.9-93834.17" case 1'1 case end @@ -146656,14 +146707,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_out2 $0\dec31_dec_sub11_sv_out2[2:0] end - attribute \src "libresoc.v:93824.3-93878.6" - process $proc$libresoc.v:93824$3927 + attribute \src "libresoc.v:93888.3-93942.6" + process $proc$libresoc.v:93888$3927 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_cr_in[2:0] $1\dec31_dec_sub11_sv_cr_in[2:0] - attribute \src "libresoc.v:93825.5-93825.29" + attribute \src "libresoc.v:93889.5-93889.29" switch \initial - attribute \src "libresoc.v:93825.9-93825.17" + attribute \src "libresoc.v:93889.9-93889.17" case 1'1 case end @@ -146739,14 +146790,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_cr_in $0\dec31_dec_sub11_sv_cr_in[2:0] end - attribute \src "libresoc.v:93879.3-93933.6" - process $proc$libresoc.v:93879$3928 + attribute \src "libresoc.v:93943.3-93997.6" + process $proc$libresoc.v:93943$3928 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sv_cr_out[2:0] $1\dec31_dec_sub11_sv_cr_out[2:0] - attribute \src "libresoc.v:93880.5-93880.29" + attribute \src "libresoc.v:93944.5-93944.29" switch \initial - attribute \src "libresoc.v:93880.9-93880.17" + attribute \src "libresoc.v:93944.9-93944.17" case 1'1 case end @@ -146822,14 +146873,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sv_cr_out $0\dec31_dec_sub11_sv_cr_out[2:0] end - attribute \src "libresoc.v:93934.3-93988.6" - process $proc$libresoc.v:93934$3929 + attribute \src "libresoc.v:93998.3-94052.6" + process $proc$libresoc.v:93998$3929 assign { } { } assign { } { } assign $0\dec31_dec_sub11_ldst_len[3:0] $1\dec31_dec_sub11_ldst_len[3:0] - attribute \src "libresoc.v:93935.5-93935.29" + attribute \src "libresoc.v:93999.5-93999.29" switch \initial - attribute \src "libresoc.v:93935.9-93935.17" + attribute \src "libresoc.v:93999.9-93999.17" case 1'1 case end @@ -146905,14 +146956,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_ldst_len $0\dec31_dec_sub11_ldst_len[3:0] end - attribute \src "libresoc.v:93989.3-94043.6" - process $proc$libresoc.v:93989$3930 + attribute \src "libresoc.v:94053.3-94107.6" + process $proc$libresoc.v:94053$3930 assign { } { } assign { } { } assign $0\dec31_dec_sub11_internal_op[6:0] $1\dec31_dec_sub11_internal_op[6:0] - attribute \src "libresoc.v:93990.5-93990.29" + attribute \src "libresoc.v:94054.5-94054.29" switch \initial - attribute \src "libresoc.v:93990.9-93990.17" + attribute \src "libresoc.v:94054.9-94054.17" case 1'1 case end @@ -146988,14 +147039,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_internal_op $0\dec31_dec_sub11_internal_op[6:0] end - attribute \src "libresoc.v:94044.3-94098.6" - process $proc$libresoc.v:94044$3931 + attribute \src "libresoc.v:94108.3-94162.6" + process $proc$libresoc.v:94108$3931 assign { } { } assign { } { } assign $0\dec31_dec_sub11_upd[1:0] $1\dec31_dec_sub11_upd[1:0] - attribute \src "libresoc.v:94045.5-94045.29" + attribute \src "libresoc.v:94109.5-94109.29" switch \initial - attribute \src "libresoc.v:94045.9-94045.17" + attribute \src "libresoc.v:94109.9-94109.17" case 1'1 case end @@ -147071,14 +147122,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_upd $0\dec31_dec_sub11_upd[1:0] end - attribute \src "libresoc.v:94099.3-94153.6" - process $proc$libresoc.v:94099$3932 + attribute \src "libresoc.v:94163.3-94217.6" + process $proc$libresoc.v:94163$3932 assign { } { } assign { } { } assign $0\dec31_dec_sub11_rc_sel[1:0] $1\dec31_dec_sub11_rc_sel[1:0] - attribute \src "libresoc.v:94100.5-94100.29" + attribute \src "libresoc.v:94164.5-94164.29" switch \initial - attribute \src "libresoc.v:94100.9-94100.17" + attribute \src "libresoc.v:94164.9-94164.17" case 1'1 case end @@ -147154,14 +147205,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_rc_sel $0\dec31_dec_sub11_rc_sel[1:0] end - attribute \src "libresoc.v:94154.3-94208.6" - process $proc$libresoc.v:94154$3933 + attribute \src "libresoc.v:94218.3-94272.6" + process $proc$libresoc.v:94218$3933 assign { } { } assign { } { } assign $0\dec31_dec_sub11_cry_in[1:0] $1\dec31_dec_sub11_cry_in[1:0] - attribute \src "libresoc.v:94155.5-94155.29" + attribute \src "libresoc.v:94219.5-94219.29" switch \initial - attribute \src "libresoc.v:94155.9-94155.17" + attribute \src "libresoc.v:94219.9-94219.17" case 1'1 case end @@ -147237,14 +147288,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_cry_in $0\dec31_dec_sub11_cry_in[1:0] end - attribute \src "libresoc.v:94209.3-94263.6" - process $proc$libresoc.v:94209$3934 + attribute \src "libresoc.v:94273.3-94327.6" + process $proc$libresoc.v:94273$3934 assign { } { } assign { } { } assign $0\dec31_dec_sub11_asmcode[7:0] $1\dec31_dec_sub11_asmcode[7:0] - attribute \src "libresoc.v:94210.5-94210.29" + attribute \src "libresoc.v:94274.5-94274.29" switch \initial - attribute \src "libresoc.v:94210.9-94210.17" + attribute \src "libresoc.v:94274.9-94274.17" case 1'1 case end @@ -147320,14 +147371,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_asmcode $0\dec31_dec_sub11_asmcode[7:0] end - attribute \src "libresoc.v:94264.3-94318.6" - process $proc$libresoc.v:94264$3935 + attribute \src "libresoc.v:94328.3-94382.6" + process $proc$libresoc.v:94328$3935 assign { } { } assign { } { } assign $0\dec31_dec_sub11_inv_a[0:0] $1\dec31_dec_sub11_inv_a[0:0] - attribute \src "libresoc.v:94265.5-94265.29" + attribute \src "libresoc.v:94329.5-94329.29" switch \initial - attribute \src "libresoc.v:94265.9-94265.17" + attribute \src "libresoc.v:94329.9-94329.17" case 1'1 case end @@ -147403,14 +147454,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_inv_a $0\dec31_dec_sub11_inv_a[0:0] end - attribute \src "libresoc.v:94319.3-94373.6" - process $proc$libresoc.v:94319$3936 + attribute \src "libresoc.v:94383.3-94437.6" + process $proc$libresoc.v:94383$3936 assign { } { } assign { } { } assign $0\dec31_dec_sub11_inv_out[0:0] $1\dec31_dec_sub11_inv_out[0:0] - attribute \src "libresoc.v:94320.5-94320.29" + attribute \src "libresoc.v:94384.5-94384.29" switch \initial - attribute \src "libresoc.v:94320.9-94320.17" + attribute \src "libresoc.v:94384.9-94384.17" case 1'1 case end @@ -147486,14 +147537,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_inv_out $0\dec31_dec_sub11_inv_out[0:0] end - attribute \src "libresoc.v:94374.3-94428.6" - process $proc$libresoc.v:94374$3937 + attribute \src "libresoc.v:94438.3-94492.6" + process $proc$libresoc.v:94438$3937 assign { } { } assign { } { } assign $0\dec31_dec_sub11_cry_out[0:0] $1\dec31_dec_sub11_cry_out[0:0] - attribute \src "libresoc.v:94375.5-94375.29" + attribute \src "libresoc.v:94439.5-94439.29" switch \initial - attribute \src "libresoc.v:94375.9-94375.17" + attribute \src "libresoc.v:94439.9-94439.17" case 1'1 case end @@ -147569,14 +147620,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_cry_out $0\dec31_dec_sub11_cry_out[0:0] end - attribute \src "libresoc.v:94429.3-94483.6" - process $proc$libresoc.v:94429$3938 + attribute \src "libresoc.v:94493.3-94547.6" + process $proc$libresoc.v:94493$3938 assign { } { } assign { } { } assign $0\dec31_dec_sub11_br[0:0] $1\dec31_dec_sub11_br[0:0] - attribute \src "libresoc.v:94430.5-94430.29" + attribute \src "libresoc.v:94494.5-94494.29" switch \initial - attribute \src "libresoc.v:94430.9-94430.17" + attribute \src "libresoc.v:94494.9-94494.17" case 1'1 case end @@ -147652,14 +147703,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_br $0\dec31_dec_sub11_br[0:0] end - attribute \src "libresoc.v:94484.3-94538.6" - process $proc$libresoc.v:94484$3939 + attribute \src "libresoc.v:94548.3-94602.6" + process $proc$libresoc.v:94548$3939 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sgn_ext[0:0] $1\dec31_dec_sub11_sgn_ext[0:0] - attribute \src "libresoc.v:94485.5-94485.29" + attribute \src "libresoc.v:94549.5-94549.29" switch \initial - attribute \src "libresoc.v:94485.9-94485.17" + attribute \src "libresoc.v:94549.9-94549.17" case 1'1 case end @@ -147735,14 +147786,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sgn_ext $0\dec31_dec_sub11_sgn_ext[0:0] end - attribute \src "libresoc.v:94539.3-94593.6" - process $proc$libresoc.v:94539$3940 + attribute \src "libresoc.v:94603.3-94657.6" + process $proc$libresoc.v:94603$3940 assign { } { } assign { } { } assign $0\dec31_dec_sub11_rsrv[0:0] $1\dec31_dec_sub11_rsrv[0:0] - attribute \src "libresoc.v:94540.5-94540.29" + attribute \src "libresoc.v:94604.5-94604.29" switch \initial - attribute \src "libresoc.v:94540.9-94540.17" + attribute \src "libresoc.v:94604.9-94604.17" case 1'1 case end @@ -147818,14 +147869,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_rsrv $0\dec31_dec_sub11_rsrv[0:0] end - attribute \src "libresoc.v:94594.3-94648.6" - process $proc$libresoc.v:94594$3941 + attribute \src "libresoc.v:94658.3-94712.6" + process $proc$libresoc.v:94658$3941 assign { } { } assign { } { } assign $0\dec31_dec_sub11_form[4:0] $1\dec31_dec_sub11_form[4:0] - attribute \src "libresoc.v:94595.5-94595.29" + attribute \src "libresoc.v:94659.5-94659.29" switch \initial - attribute \src "libresoc.v:94595.9-94595.17" + attribute \src "libresoc.v:94659.9-94659.17" case 1'1 case end @@ -147901,14 +147952,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_form $0\dec31_dec_sub11_form[4:0] end - attribute \src "libresoc.v:94649.3-94703.6" - process $proc$libresoc.v:94649$3942 + attribute \src "libresoc.v:94713.3-94767.6" + process $proc$libresoc.v:94713$3942 assign { } { } assign { } { } assign $0\dec31_dec_sub11_is_32b[0:0] $1\dec31_dec_sub11_is_32b[0:0] - attribute \src "libresoc.v:94650.5-94650.29" + attribute \src "libresoc.v:94714.5-94714.29" switch \initial - attribute \src "libresoc.v:94650.9-94650.17" + attribute \src "libresoc.v:94714.9-94714.17" case 1'1 case end @@ -147984,14 +148035,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_is_32b $0\dec31_dec_sub11_is_32b[0:0] end - attribute \src "libresoc.v:94704.3-94758.6" - process $proc$libresoc.v:94704$3943 + attribute \src "libresoc.v:94768.3-94822.6" + process $proc$libresoc.v:94768$3943 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sgn[0:0] $1\dec31_dec_sub11_sgn[0:0] - attribute \src "libresoc.v:94705.5-94705.29" + attribute \src "libresoc.v:94769.5-94769.29" switch \initial - attribute \src "libresoc.v:94705.9-94705.17" + attribute \src "libresoc.v:94769.9-94769.17" case 1'1 case end @@ -148067,14 +148118,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sgn $0\dec31_dec_sub11_sgn[0:0] end - attribute \src "libresoc.v:94759.3-94813.6" - process $proc$libresoc.v:94759$3944 + attribute \src "libresoc.v:94823.3-94877.6" + process $proc$libresoc.v:94823$3944 assign { } { } assign { } { } assign $0\dec31_dec_sub11_lk[0:0] $1\dec31_dec_sub11_lk[0:0] - attribute \src "libresoc.v:94760.5-94760.29" + attribute \src "libresoc.v:94824.5-94824.29" switch \initial - attribute \src "libresoc.v:94760.9-94760.17" + attribute \src "libresoc.v:94824.9-94824.17" case 1'1 case end @@ -148150,14 +148201,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_lk $0\dec31_dec_sub11_lk[0:0] end - attribute \src "libresoc.v:94814.3-94868.6" - process $proc$libresoc.v:94814$3945 + attribute \src "libresoc.v:94878.3-94932.6" + process $proc$libresoc.v:94878$3945 assign { } { } assign { } { } assign $0\dec31_dec_sub11_sgl_pipe[0:0] $1\dec31_dec_sub11_sgl_pipe[0:0] - attribute \src "libresoc.v:94815.5-94815.29" + attribute \src "libresoc.v:94879.5-94879.29" switch \initial - attribute \src "libresoc.v:94815.9-94815.17" + attribute \src "libresoc.v:94879.9-94879.17" case 1'1 case end @@ -148233,14 +148284,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_sgl_pipe $0\dec31_dec_sub11_sgl_pipe[0:0] end - attribute \src "libresoc.v:94869.3-94923.6" - process $proc$libresoc.v:94869$3946 + attribute \src "libresoc.v:94933.3-94987.6" + process $proc$libresoc.v:94933$3946 assign { } { } assign { } { } assign $0\dec31_dec_sub11_SV_Etype[1:0] $1\dec31_dec_sub11_SV_Etype[1:0] - attribute \src "libresoc.v:94870.5-94870.29" + attribute \src "libresoc.v:94934.5-94934.29" switch \initial - attribute \src "libresoc.v:94870.9-94870.17" + attribute \src "libresoc.v:94934.9-94934.17" case 1'1 case end @@ -148316,14 +148367,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_SV_Etype $0\dec31_dec_sub11_SV_Etype[1:0] end - attribute \src "libresoc.v:94924.3-94978.6" - process $proc$libresoc.v:94924$3947 + attribute \src "libresoc.v:94988.3-95042.6" + process $proc$libresoc.v:94988$3947 assign { } { } assign { } { } assign $0\dec31_dec_sub11_SV_Ptype[1:0] $1\dec31_dec_sub11_SV_Ptype[1:0] - attribute \src "libresoc.v:94925.5-94925.29" + attribute \src "libresoc.v:94989.5-94989.29" switch \initial - attribute \src "libresoc.v:94925.9-94925.17" + attribute \src "libresoc.v:94989.9-94989.17" case 1'1 case end @@ -148399,14 +148450,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_SV_Ptype $0\dec31_dec_sub11_SV_Ptype[1:0] end - attribute \src "libresoc.v:94979.3-95033.6" - process $proc$libresoc.v:94979$3948 + attribute \src "libresoc.v:95043.3-95097.6" + process $proc$libresoc.v:95043$3948 assign { } { } assign { } { } assign $0\dec31_dec_sub11_in1_sel[2:0] $1\dec31_dec_sub11_in1_sel[2:0] - attribute \src "libresoc.v:94980.5-94980.29" + attribute \src "libresoc.v:95044.5-95044.29" switch \initial - attribute \src "libresoc.v:94980.9-94980.17" + attribute \src "libresoc.v:95044.9-95044.17" case 1'1 case end @@ -148482,14 +148533,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_in1_sel $0\dec31_dec_sub11_in1_sel[2:0] end - attribute \src "libresoc.v:95034.3-95088.6" - process $proc$libresoc.v:95034$3949 + attribute \src "libresoc.v:95098.3-95152.6" + process $proc$libresoc.v:95098$3949 assign { } { } assign { } { } assign $0\dec31_dec_sub11_in2_sel[3:0] $1\dec31_dec_sub11_in2_sel[3:0] - attribute \src "libresoc.v:95035.5-95035.29" + attribute \src "libresoc.v:95099.5-95099.29" switch \initial - attribute \src "libresoc.v:95035.9-95035.17" + attribute \src "libresoc.v:95099.9-95099.17" case 1'1 case end @@ -148565,14 +148616,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_in2_sel $0\dec31_dec_sub11_in2_sel[3:0] end - attribute \src "libresoc.v:95089.3-95143.6" - process $proc$libresoc.v:95089$3950 + attribute \src "libresoc.v:95153.3-95207.6" + process $proc$libresoc.v:95153$3950 assign { } { } assign { } { } assign $0\dec31_dec_sub11_in3_sel[1:0] $1\dec31_dec_sub11_in3_sel[1:0] - attribute \src "libresoc.v:95090.5-95090.29" + attribute \src "libresoc.v:95154.5-95154.29" switch \initial - attribute \src "libresoc.v:95090.9-95090.17" + attribute \src "libresoc.v:95154.9-95154.17" case 1'1 case end @@ -148648,14 +148699,14 @@ module \dec31_dec_sub11 sync always update \dec31_dec_sub11_in3_sel $0\dec31_dec_sub11_in3_sel[1:0] end - attribute \src "libresoc.v:95144.3-95198.6" - process $proc$libresoc.v:95144$3951 + attribute \src "libresoc.v:95208.3-95262.6" + process $proc$libresoc.v:95208$3951 assign { } { } assign { } { } assign $0\dec31_dec_sub11_out_sel[2:0] $1\dec31_dec_sub11_out_sel[2:0] - attribute \src "libresoc.v:95145.5-95145.29" + attribute \src "libresoc.v:95209.5-95209.29" switch \initial - attribute \src "libresoc.v:95145.9-95145.17" + attribute \src "libresoc.v:95209.9-95209.17" case 1'1 case end @@ -148733,144 +148784,144 @@ module \dec31_dec_sub11 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:95204.1-98953.10" +attribute \src "libresoc.v:95268.1-99017.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub15" attribute \generator "nMigen" module \dec31_dec_sub15 - attribute \src "libresoc.v:98334.3-98436.6" + attribute \src "libresoc.v:98398.3-98500.6" wire width 2 $0\dec31_dec_sub15_SV_Etype[1:0] - attribute \src "libresoc.v:98437.3-98539.6" + attribute \src "libresoc.v:98501.3-98603.6" wire width 2 $0\dec31_dec_sub15_SV_Ptype[1:0] - attribute \src "libresoc.v:97098.3-97200.6" + attribute \src "libresoc.v:97162.3-97264.6" wire width 8 $0\dec31_dec_sub15_asmcode[7:0] - attribute \src "libresoc.v:97510.3-97612.6" + attribute \src "libresoc.v:97574.3-97676.6" wire $0\dec31_dec_sub15_br[0:0] - attribute \src "libresoc.v:95656.3-95758.6" + attribute \src "libresoc.v:95720.3-95822.6" wire width 3 $0\dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:95759.3-95861.6" + attribute \src "libresoc.v:95823.3-95925.6" wire width 3 $0\dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:96995.3-97097.6" + attribute \src "libresoc.v:97059.3-97161.6" wire width 2 $0\dec31_dec_sub15_cry_in[1:0] - attribute \src "libresoc.v:97407.3-97509.6" + attribute \src "libresoc.v:97471.3-97573.6" wire $0\dec31_dec_sub15_cry_out[0:0] - attribute \src "libresoc.v:97819.3-97921.6" + attribute \src "libresoc.v:97883.3-97985.6" wire width 5 $0\dec31_dec_sub15_form[4:0] - attribute \src "libresoc.v:95553.3-95655.6" + attribute \src "libresoc.v:95617.3-95719.6" wire width 14 $0\dec31_dec_sub15_function_unit[13:0] - attribute \src "libresoc.v:98540.3-98642.6" + attribute \src "libresoc.v:98604.3-98706.6" wire width 3 $0\dec31_dec_sub15_in1_sel[2:0] - attribute \src "libresoc.v:98643.3-98745.6" + attribute \src "libresoc.v:98707.3-98809.6" wire width 4 $0\dec31_dec_sub15_in2_sel[3:0] - attribute \src "libresoc.v:98746.3-98848.6" + attribute \src "libresoc.v:98810.3-98912.6" wire width 2 $0\dec31_dec_sub15_in3_sel[1:0] - attribute \src "libresoc.v:96686.3-96788.6" + attribute \src "libresoc.v:96750.3-96852.6" wire width 7 $0\dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:97201.3-97303.6" + attribute \src "libresoc.v:97265.3-97367.6" wire $0\dec31_dec_sub15_inv_a[0:0] - attribute \src "libresoc.v:97304.3-97406.6" + attribute \src "libresoc.v:97368.3-97470.6" wire $0\dec31_dec_sub15_inv_out[0:0] - attribute \src "libresoc.v:97922.3-98024.6" + attribute \src "libresoc.v:97986.3-98088.6" wire $0\dec31_dec_sub15_is_32b[0:0] - attribute \src "libresoc.v:96583.3-96685.6" + attribute \src "libresoc.v:96647.3-96749.6" wire width 4 $0\dec31_dec_sub15_ldst_len[3:0] - attribute \src "libresoc.v:98128.3-98230.6" + attribute \src "libresoc.v:98192.3-98294.6" wire $0\dec31_dec_sub15_lk[0:0] - attribute \src "libresoc.v:98849.3-98951.6" + attribute \src "libresoc.v:98913.3-99015.6" wire width 3 $0\dec31_dec_sub15_out_sel[2:0] - attribute \src "libresoc.v:96892.3-96994.6" + attribute \src "libresoc.v:96956.3-97058.6" wire width 2 $0\dec31_dec_sub15_rc_sel[1:0] - attribute \src "libresoc.v:97716.3-97818.6" + attribute \src "libresoc.v:97780.3-97882.6" wire $0\dec31_dec_sub15_rsrv[0:0] - attribute \src "libresoc.v:98231.3-98333.6" + attribute \src "libresoc.v:98295.3-98397.6" wire $0\dec31_dec_sub15_sgl_pipe[0:0] - attribute \src "libresoc.v:98025.3-98127.6" + attribute \src "libresoc.v:98089.3-98191.6" wire $0\dec31_dec_sub15_sgn[0:0] - attribute \src "libresoc.v:97613.3-97715.6" + attribute \src "libresoc.v:97677.3-97779.6" wire $0\dec31_dec_sub15_sgn_ext[0:0] - attribute \src "libresoc.v:96377.3-96479.6" + attribute \src "libresoc.v:96441.3-96543.6" wire width 3 $0\dec31_dec_sub15_sv_cr_in[2:0] - attribute \src "libresoc.v:96480.3-96582.6" + attribute \src "libresoc.v:96544.3-96646.6" wire width 3 $0\dec31_dec_sub15_sv_cr_out[2:0] - attribute \src "libresoc.v:95862.3-95964.6" + attribute \src "libresoc.v:95926.3-96028.6" wire width 3 $0\dec31_dec_sub15_sv_in1[2:0] - attribute \src "libresoc.v:95965.3-96067.6" + attribute \src "libresoc.v:96029.3-96131.6" wire width 3 $0\dec31_dec_sub15_sv_in2[2:0] - attribute \src "libresoc.v:96068.3-96170.6" + attribute \src "libresoc.v:96132.3-96234.6" wire width 3 $0\dec31_dec_sub15_sv_in3[2:0] - attribute \src "libresoc.v:96274.3-96376.6" + attribute \src "libresoc.v:96338.3-96440.6" wire width 3 $0\dec31_dec_sub15_sv_out2[2:0] - attribute \src "libresoc.v:96171.3-96273.6" + attribute \src "libresoc.v:96235.3-96337.6" wire width 3 $0\dec31_dec_sub15_sv_out[2:0] - attribute \src "libresoc.v:96789.3-96891.6" + attribute \src "libresoc.v:96853.3-96955.6" wire width 2 $0\dec31_dec_sub15_upd[1:0] - attribute \src "libresoc.v:95205.7-95205.20" + attribute \src "libresoc.v:95269.7-95269.20" wire $0\initial[0:0] - attribute \src "libresoc.v:98334.3-98436.6" + attribute \src "libresoc.v:98398.3-98500.6" wire width 2 $1\dec31_dec_sub15_SV_Etype[1:0] - attribute \src "libresoc.v:98437.3-98539.6" + attribute \src "libresoc.v:98501.3-98603.6" wire width 2 $1\dec31_dec_sub15_SV_Ptype[1:0] - attribute \src "libresoc.v:97098.3-97200.6" + attribute \src "libresoc.v:97162.3-97264.6" wire width 8 $1\dec31_dec_sub15_asmcode[7:0] - attribute \src "libresoc.v:97510.3-97612.6" + attribute \src "libresoc.v:97574.3-97676.6" wire $1\dec31_dec_sub15_br[0:0] - attribute \src "libresoc.v:95656.3-95758.6" + attribute \src "libresoc.v:95720.3-95822.6" wire width 3 $1\dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:95759.3-95861.6" + attribute \src "libresoc.v:95823.3-95925.6" wire width 3 $1\dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:96995.3-97097.6" + attribute \src "libresoc.v:97059.3-97161.6" wire width 2 $1\dec31_dec_sub15_cry_in[1:0] - attribute \src "libresoc.v:97407.3-97509.6" + attribute \src "libresoc.v:97471.3-97573.6" wire $1\dec31_dec_sub15_cry_out[0:0] - attribute \src "libresoc.v:97819.3-97921.6" + attribute \src "libresoc.v:97883.3-97985.6" wire width 5 $1\dec31_dec_sub15_form[4:0] - attribute \src "libresoc.v:95553.3-95655.6" + attribute \src "libresoc.v:95617.3-95719.6" wire width 14 $1\dec31_dec_sub15_function_unit[13:0] - attribute \src "libresoc.v:98540.3-98642.6" + attribute \src "libresoc.v:98604.3-98706.6" wire width 3 $1\dec31_dec_sub15_in1_sel[2:0] - attribute \src "libresoc.v:98643.3-98745.6" + attribute \src "libresoc.v:98707.3-98809.6" wire width 4 $1\dec31_dec_sub15_in2_sel[3:0] - attribute \src "libresoc.v:98746.3-98848.6" + attribute \src "libresoc.v:98810.3-98912.6" wire width 2 $1\dec31_dec_sub15_in3_sel[1:0] - attribute \src "libresoc.v:96686.3-96788.6" + attribute \src "libresoc.v:96750.3-96852.6" wire width 7 $1\dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:97201.3-97303.6" + attribute \src "libresoc.v:97265.3-97367.6" wire $1\dec31_dec_sub15_inv_a[0:0] - attribute \src "libresoc.v:97304.3-97406.6" + attribute \src "libresoc.v:97368.3-97470.6" wire $1\dec31_dec_sub15_inv_out[0:0] - attribute \src "libresoc.v:97922.3-98024.6" + attribute \src "libresoc.v:97986.3-98088.6" wire $1\dec31_dec_sub15_is_32b[0:0] - attribute \src "libresoc.v:96583.3-96685.6" + attribute \src "libresoc.v:96647.3-96749.6" wire width 4 $1\dec31_dec_sub15_ldst_len[3:0] - attribute \src "libresoc.v:98128.3-98230.6" + attribute \src "libresoc.v:98192.3-98294.6" wire $1\dec31_dec_sub15_lk[0:0] - attribute \src "libresoc.v:98849.3-98951.6" + attribute \src "libresoc.v:98913.3-99015.6" wire width 3 $1\dec31_dec_sub15_out_sel[2:0] - attribute \src "libresoc.v:96892.3-96994.6" + attribute \src "libresoc.v:96956.3-97058.6" wire width 2 $1\dec31_dec_sub15_rc_sel[1:0] - attribute \src "libresoc.v:97716.3-97818.6" + attribute \src "libresoc.v:97780.3-97882.6" wire $1\dec31_dec_sub15_rsrv[0:0] - attribute \src "libresoc.v:98231.3-98333.6" + attribute \src "libresoc.v:98295.3-98397.6" wire $1\dec31_dec_sub15_sgl_pipe[0:0] - attribute \src "libresoc.v:98025.3-98127.6" + attribute \src "libresoc.v:98089.3-98191.6" wire $1\dec31_dec_sub15_sgn[0:0] - attribute \src "libresoc.v:97613.3-97715.6" + attribute \src "libresoc.v:97677.3-97779.6" wire $1\dec31_dec_sub15_sgn_ext[0:0] - attribute \src "libresoc.v:96377.3-96479.6" + attribute \src "libresoc.v:96441.3-96543.6" wire width 3 $1\dec31_dec_sub15_sv_cr_in[2:0] - attribute \src "libresoc.v:96480.3-96582.6" + attribute \src "libresoc.v:96544.3-96646.6" wire width 3 $1\dec31_dec_sub15_sv_cr_out[2:0] - attribute \src "libresoc.v:95862.3-95964.6" + attribute \src "libresoc.v:95926.3-96028.6" wire width 3 $1\dec31_dec_sub15_sv_in1[2:0] - attribute \src "libresoc.v:95965.3-96067.6" + attribute \src "libresoc.v:96029.3-96131.6" wire width 3 $1\dec31_dec_sub15_sv_in2[2:0] - attribute \src "libresoc.v:96068.3-96170.6" + attribute \src "libresoc.v:96132.3-96234.6" wire width 3 $1\dec31_dec_sub15_sv_in3[2:0] - attribute \src "libresoc.v:96274.3-96376.6" + attribute \src "libresoc.v:96338.3-96440.6" wire width 3 $1\dec31_dec_sub15_sv_out2[2:0] - attribute \src "libresoc.v:96171.3-96273.6" + attribute \src "libresoc.v:96235.3-96337.6" wire width 3 $1\dec31_dec_sub15_sv_out[2:0] - attribute \src "libresoc.v:96789.3-96891.6" + attribute \src "libresoc.v:96853.3-96955.6" wire width 2 $1\dec31_dec_sub15_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -149182,28 +149233,28 @@ module \dec31_dec_sub15 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub15_upd - attribute \src "libresoc.v:95205.7-95205.15" + attribute \src "libresoc.v:95269.7-95269.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:95205.7-95205.20" - process $proc$libresoc.v:95205$3986 + attribute \src "libresoc.v:95269.7-95269.20" + process $proc$libresoc.v:95269$3986 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:95553.3-95655.6" - process $proc$libresoc.v:95553$3953 + attribute \src "libresoc.v:95617.3-95719.6" + process $proc$libresoc.v:95617$3953 assign { } { } assign { } { } assign $0\dec31_dec_sub15_function_unit[13:0] $1\dec31_dec_sub15_function_unit[13:0] - attribute \src "libresoc.v:95554.5-95554.29" + attribute \src "libresoc.v:95618.5-95618.29" switch \initial - attribute \src "libresoc.v:95554.9-95554.17" + attribute \src "libresoc.v:95618.9-95618.17" case 1'1 case end @@ -149343,14 +149394,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_function_unit $0\dec31_dec_sub15_function_unit[13:0] end - attribute \src "libresoc.v:95656.3-95758.6" - process $proc$libresoc.v:95656$3954 + attribute \src "libresoc.v:95720.3-95822.6" + process $proc$libresoc.v:95720$3954 assign { } { } assign { } { } assign $0\dec31_dec_sub15_cr_in[2:0] $1\dec31_dec_sub15_cr_in[2:0] - attribute \src "libresoc.v:95657.5-95657.29" + attribute \src "libresoc.v:95721.5-95721.29" switch \initial - attribute \src "libresoc.v:95657.9-95657.17" + attribute \src "libresoc.v:95721.9-95721.17" case 1'1 case end @@ -149490,14 +149541,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_cr_in $0\dec31_dec_sub15_cr_in[2:0] end - attribute \src "libresoc.v:95759.3-95861.6" - process $proc$libresoc.v:95759$3955 + attribute \src "libresoc.v:95823.3-95925.6" + process $proc$libresoc.v:95823$3955 assign { } { } assign { } { } assign $0\dec31_dec_sub15_cr_out[2:0] $1\dec31_dec_sub15_cr_out[2:0] - attribute \src "libresoc.v:95760.5-95760.29" + attribute \src "libresoc.v:95824.5-95824.29" switch \initial - attribute \src "libresoc.v:95760.9-95760.17" + attribute \src "libresoc.v:95824.9-95824.17" case 1'1 case end @@ -149637,14 +149688,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_cr_out $0\dec31_dec_sub15_cr_out[2:0] end - attribute \src "libresoc.v:95862.3-95964.6" - process $proc$libresoc.v:95862$3956 + attribute \src "libresoc.v:95926.3-96028.6" + process $proc$libresoc.v:95926$3956 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_in1[2:0] $1\dec31_dec_sub15_sv_in1[2:0] - attribute \src "libresoc.v:95863.5-95863.29" + attribute \src "libresoc.v:95927.5-95927.29" switch \initial - attribute \src "libresoc.v:95863.9-95863.17" + attribute \src "libresoc.v:95927.9-95927.17" case 1'1 case end @@ -149784,14 +149835,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_in1 $0\dec31_dec_sub15_sv_in1[2:0] end - attribute \src "libresoc.v:95965.3-96067.6" - process $proc$libresoc.v:95965$3957 + attribute \src "libresoc.v:96029.3-96131.6" + process $proc$libresoc.v:96029$3957 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_in2[2:0] $1\dec31_dec_sub15_sv_in2[2:0] - attribute \src "libresoc.v:95966.5-95966.29" + attribute \src "libresoc.v:96030.5-96030.29" switch \initial - attribute \src "libresoc.v:95966.9-95966.17" + attribute \src "libresoc.v:96030.9-96030.17" case 1'1 case end @@ -149931,14 +149982,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_in2 $0\dec31_dec_sub15_sv_in2[2:0] end - attribute \src "libresoc.v:96068.3-96170.6" - process $proc$libresoc.v:96068$3958 + attribute \src "libresoc.v:96132.3-96234.6" + process $proc$libresoc.v:96132$3958 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_in3[2:0] $1\dec31_dec_sub15_sv_in3[2:0] - attribute \src "libresoc.v:96069.5-96069.29" + attribute \src "libresoc.v:96133.5-96133.29" switch \initial - attribute \src "libresoc.v:96069.9-96069.17" + attribute \src "libresoc.v:96133.9-96133.17" case 1'1 case end @@ -150078,14 +150129,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_in3 $0\dec31_dec_sub15_sv_in3[2:0] end - attribute \src "libresoc.v:96171.3-96273.6" - process $proc$libresoc.v:96171$3959 + attribute \src "libresoc.v:96235.3-96337.6" + process $proc$libresoc.v:96235$3959 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_out[2:0] $1\dec31_dec_sub15_sv_out[2:0] - attribute \src "libresoc.v:96172.5-96172.29" + attribute \src "libresoc.v:96236.5-96236.29" switch \initial - attribute \src "libresoc.v:96172.9-96172.17" + attribute \src "libresoc.v:96236.9-96236.17" case 1'1 case end @@ -150225,14 +150276,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_out $0\dec31_dec_sub15_sv_out[2:0] end - attribute \src "libresoc.v:96274.3-96376.6" - process $proc$libresoc.v:96274$3960 + attribute \src "libresoc.v:96338.3-96440.6" + process $proc$libresoc.v:96338$3960 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_out2[2:0] $1\dec31_dec_sub15_sv_out2[2:0] - attribute \src "libresoc.v:96275.5-96275.29" + attribute \src "libresoc.v:96339.5-96339.29" switch \initial - attribute \src "libresoc.v:96275.9-96275.17" + attribute \src "libresoc.v:96339.9-96339.17" case 1'1 case end @@ -150372,14 +150423,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_out2 $0\dec31_dec_sub15_sv_out2[2:0] end - attribute \src "libresoc.v:96377.3-96479.6" - process $proc$libresoc.v:96377$3961 + attribute \src "libresoc.v:96441.3-96543.6" + process $proc$libresoc.v:96441$3961 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_cr_in[2:0] $1\dec31_dec_sub15_sv_cr_in[2:0] - attribute \src "libresoc.v:96378.5-96378.29" + attribute \src "libresoc.v:96442.5-96442.29" switch \initial - attribute \src "libresoc.v:96378.9-96378.17" + attribute \src "libresoc.v:96442.9-96442.17" case 1'1 case end @@ -150519,14 +150570,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_cr_in $0\dec31_dec_sub15_sv_cr_in[2:0] end - attribute \src "libresoc.v:96480.3-96582.6" - process $proc$libresoc.v:96480$3962 + attribute \src "libresoc.v:96544.3-96646.6" + process $proc$libresoc.v:96544$3962 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sv_cr_out[2:0] $1\dec31_dec_sub15_sv_cr_out[2:0] - attribute \src "libresoc.v:96481.5-96481.29" + attribute \src "libresoc.v:96545.5-96545.29" switch \initial - attribute \src "libresoc.v:96481.9-96481.17" + attribute \src "libresoc.v:96545.9-96545.17" case 1'1 case end @@ -150666,14 +150717,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sv_cr_out $0\dec31_dec_sub15_sv_cr_out[2:0] end - attribute \src "libresoc.v:96583.3-96685.6" - process $proc$libresoc.v:96583$3963 + attribute \src "libresoc.v:96647.3-96749.6" + process $proc$libresoc.v:96647$3963 assign { } { } assign { } { } assign $0\dec31_dec_sub15_ldst_len[3:0] $1\dec31_dec_sub15_ldst_len[3:0] - attribute \src "libresoc.v:96584.5-96584.29" + attribute \src "libresoc.v:96648.5-96648.29" switch \initial - attribute \src "libresoc.v:96584.9-96584.17" + attribute \src "libresoc.v:96648.9-96648.17" case 1'1 case end @@ -150813,14 +150864,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_ldst_len $0\dec31_dec_sub15_ldst_len[3:0] end - attribute \src "libresoc.v:96686.3-96788.6" - process $proc$libresoc.v:96686$3964 + attribute \src "libresoc.v:96750.3-96852.6" + process $proc$libresoc.v:96750$3964 assign { } { } assign { } { } assign $0\dec31_dec_sub15_internal_op[6:0] $1\dec31_dec_sub15_internal_op[6:0] - attribute \src "libresoc.v:96687.5-96687.29" + attribute \src "libresoc.v:96751.5-96751.29" switch \initial - attribute \src "libresoc.v:96687.9-96687.17" + attribute \src "libresoc.v:96751.9-96751.17" case 1'1 case end @@ -150960,14 +151011,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_internal_op $0\dec31_dec_sub15_internal_op[6:0] end - attribute \src "libresoc.v:96789.3-96891.6" - process $proc$libresoc.v:96789$3965 + attribute \src "libresoc.v:96853.3-96955.6" + process $proc$libresoc.v:96853$3965 assign { } { } assign { } { } assign $0\dec31_dec_sub15_upd[1:0] $1\dec31_dec_sub15_upd[1:0] - attribute \src "libresoc.v:96790.5-96790.29" + attribute \src "libresoc.v:96854.5-96854.29" switch \initial - attribute \src "libresoc.v:96790.9-96790.17" + attribute \src "libresoc.v:96854.9-96854.17" case 1'1 case end @@ -151107,14 +151158,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_upd $0\dec31_dec_sub15_upd[1:0] end - attribute \src "libresoc.v:96892.3-96994.6" - process $proc$libresoc.v:96892$3966 + attribute \src "libresoc.v:96956.3-97058.6" + process $proc$libresoc.v:96956$3966 assign { } { } assign { } { } assign $0\dec31_dec_sub15_rc_sel[1:0] $1\dec31_dec_sub15_rc_sel[1:0] - attribute \src "libresoc.v:96893.5-96893.29" + attribute \src "libresoc.v:96957.5-96957.29" switch \initial - attribute \src "libresoc.v:96893.9-96893.17" + attribute \src "libresoc.v:96957.9-96957.17" case 1'1 case end @@ -151254,14 +151305,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_rc_sel $0\dec31_dec_sub15_rc_sel[1:0] end - attribute \src "libresoc.v:96995.3-97097.6" - process $proc$libresoc.v:96995$3967 + attribute \src "libresoc.v:97059.3-97161.6" + process $proc$libresoc.v:97059$3967 assign { } { } assign { } { } assign $0\dec31_dec_sub15_cry_in[1:0] $1\dec31_dec_sub15_cry_in[1:0] - attribute \src "libresoc.v:96996.5-96996.29" + attribute \src "libresoc.v:97060.5-97060.29" switch \initial - attribute \src "libresoc.v:96996.9-96996.17" + attribute \src "libresoc.v:97060.9-97060.17" case 1'1 case end @@ -151401,14 +151452,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_cry_in $0\dec31_dec_sub15_cry_in[1:0] end - attribute \src "libresoc.v:97098.3-97200.6" - process $proc$libresoc.v:97098$3968 + attribute \src "libresoc.v:97162.3-97264.6" + process $proc$libresoc.v:97162$3968 assign { } { } assign { } { } assign $0\dec31_dec_sub15_asmcode[7:0] $1\dec31_dec_sub15_asmcode[7:0] - attribute \src "libresoc.v:97099.5-97099.29" + attribute \src "libresoc.v:97163.5-97163.29" switch \initial - attribute \src "libresoc.v:97099.9-97099.17" + attribute \src "libresoc.v:97163.9-97163.17" case 1'1 case end @@ -151548,14 +151599,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_asmcode $0\dec31_dec_sub15_asmcode[7:0] end - attribute \src "libresoc.v:97201.3-97303.6" - process $proc$libresoc.v:97201$3969 + attribute \src "libresoc.v:97265.3-97367.6" + process $proc$libresoc.v:97265$3969 assign { } { } assign { } { } assign $0\dec31_dec_sub15_inv_a[0:0] $1\dec31_dec_sub15_inv_a[0:0] - attribute \src "libresoc.v:97202.5-97202.29" + attribute \src "libresoc.v:97266.5-97266.29" switch \initial - attribute \src "libresoc.v:97202.9-97202.17" + attribute \src "libresoc.v:97266.9-97266.17" case 1'1 case end @@ -151695,14 +151746,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_inv_a $0\dec31_dec_sub15_inv_a[0:0] end - attribute \src "libresoc.v:97304.3-97406.6" - process $proc$libresoc.v:97304$3970 + attribute \src "libresoc.v:97368.3-97470.6" + process $proc$libresoc.v:97368$3970 assign { } { } assign { } { } assign $0\dec31_dec_sub15_inv_out[0:0] $1\dec31_dec_sub15_inv_out[0:0] - attribute \src "libresoc.v:97305.5-97305.29" + attribute \src "libresoc.v:97369.5-97369.29" switch \initial - attribute \src "libresoc.v:97305.9-97305.17" + attribute \src "libresoc.v:97369.9-97369.17" case 1'1 case end @@ -151842,14 +151893,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_inv_out $0\dec31_dec_sub15_inv_out[0:0] end - attribute \src "libresoc.v:97407.3-97509.6" - process $proc$libresoc.v:97407$3971 + attribute \src "libresoc.v:97471.3-97573.6" + process $proc$libresoc.v:97471$3971 assign { } { } assign { } { } assign $0\dec31_dec_sub15_cry_out[0:0] $1\dec31_dec_sub15_cry_out[0:0] - attribute \src "libresoc.v:97408.5-97408.29" + attribute \src "libresoc.v:97472.5-97472.29" switch \initial - attribute \src "libresoc.v:97408.9-97408.17" + attribute \src "libresoc.v:97472.9-97472.17" case 1'1 case end @@ -151989,14 +152040,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_cry_out $0\dec31_dec_sub15_cry_out[0:0] end - attribute \src "libresoc.v:97510.3-97612.6" - process $proc$libresoc.v:97510$3972 + attribute \src "libresoc.v:97574.3-97676.6" + process $proc$libresoc.v:97574$3972 assign { } { } assign { } { } assign $0\dec31_dec_sub15_br[0:0] $1\dec31_dec_sub15_br[0:0] - attribute \src "libresoc.v:97511.5-97511.29" + attribute \src "libresoc.v:97575.5-97575.29" switch \initial - attribute \src "libresoc.v:97511.9-97511.17" + attribute \src "libresoc.v:97575.9-97575.17" case 1'1 case end @@ -152136,14 +152187,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_br $0\dec31_dec_sub15_br[0:0] end - attribute \src "libresoc.v:97613.3-97715.6" - process $proc$libresoc.v:97613$3973 + attribute \src "libresoc.v:97677.3-97779.6" + process $proc$libresoc.v:97677$3973 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sgn_ext[0:0] $1\dec31_dec_sub15_sgn_ext[0:0] - attribute \src "libresoc.v:97614.5-97614.29" + attribute \src "libresoc.v:97678.5-97678.29" switch \initial - attribute \src "libresoc.v:97614.9-97614.17" + attribute \src "libresoc.v:97678.9-97678.17" case 1'1 case end @@ -152283,14 +152334,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sgn_ext $0\dec31_dec_sub15_sgn_ext[0:0] end - attribute \src "libresoc.v:97716.3-97818.6" - process $proc$libresoc.v:97716$3974 + attribute \src "libresoc.v:97780.3-97882.6" + process $proc$libresoc.v:97780$3974 assign { } { } assign { } { } assign $0\dec31_dec_sub15_rsrv[0:0] $1\dec31_dec_sub15_rsrv[0:0] - attribute \src "libresoc.v:97717.5-97717.29" + attribute \src "libresoc.v:97781.5-97781.29" switch \initial - attribute \src "libresoc.v:97717.9-97717.17" + attribute \src "libresoc.v:97781.9-97781.17" case 1'1 case end @@ -152430,14 +152481,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_rsrv $0\dec31_dec_sub15_rsrv[0:0] end - attribute \src "libresoc.v:97819.3-97921.6" - process $proc$libresoc.v:97819$3975 + attribute \src "libresoc.v:97883.3-97985.6" + process $proc$libresoc.v:97883$3975 assign { } { } assign { } { } assign $0\dec31_dec_sub15_form[4:0] $1\dec31_dec_sub15_form[4:0] - attribute \src "libresoc.v:97820.5-97820.29" + attribute \src "libresoc.v:97884.5-97884.29" switch \initial - attribute \src "libresoc.v:97820.9-97820.17" + attribute \src "libresoc.v:97884.9-97884.17" case 1'1 case end @@ -152577,14 +152628,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_form $0\dec31_dec_sub15_form[4:0] end - attribute \src "libresoc.v:97922.3-98024.6" - process $proc$libresoc.v:97922$3976 + attribute \src "libresoc.v:97986.3-98088.6" + process $proc$libresoc.v:97986$3976 assign { } { } assign { } { } assign $0\dec31_dec_sub15_is_32b[0:0] $1\dec31_dec_sub15_is_32b[0:0] - attribute \src "libresoc.v:97923.5-97923.29" + attribute \src "libresoc.v:97987.5-97987.29" switch \initial - attribute \src "libresoc.v:97923.9-97923.17" + attribute \src "libresoc.v:97987.9-97987.17" case 1'1 case end @@ -152724,14 +152775,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_is_32b $0\dec31_dec_sub15_is_32b[0:0] end - attribute \src "libresoc.v:98025.3-98127.6" - process $proc$libresoc.v:98025$3977 + attribute \src "libresoc.v:98089.3-98191.6" + process $proc$libresoc.v:98089$3977 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sgn[0:0] $1\dec31_dec_sub15_sgn[0:0] - attribute \src "libresoc.v:98026.5-98026.29" + attribute \src "libresoc.v:98090.5-98090.29" switch \initial - attribute \src "libresoc.v:98026.9-98026.17" + attribute \src "libresoc.v:98090.9-98090.17" case 1'1 case end @@ -152871,14 +152922,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sgn $0\dec31_dec_sub15_sgn[0:0] end - attribute \src "libresoc.v:98128.3-98230.6" - process $proc$libresoc.v:98128$3978 + attribute \src "libresoc.v:98192.3-98294.6" + process $proc$libresoc.v:98192$3978 assign { } { } assign { } { } assign $0\dec31_dec_sub15_lk[0:0] $1\dec31_dec_sub15_lk[0:0] - attribute \src "libresoc.v:98129.5-98129.29" + attribute \src "libresoc.v:98193.5-98193.29" switch \initial - attribute \src "libresoc.v:98129.9-98129.17" + attribute \src "libresoc.v:98193.9-98193.17" case 1'1 case end @@ -153018,14 +153069,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_lk $0\dec31_dec_sub15_lk[0:0] end - attribute \src "libresoc.v:98231.3-98333.6" - process $proc$libresoc.v:98231$3979 + attribute \src "libresoc.v:98295.3-98397.6" + process $proc$libresoc.v:98295$3979 assign { } { } assign { } { } assign $0\dec31_dec_sub15_sgl_pipe[0:0] $1\dec31_dec_sub15_sgl_pipe[0:0] - attribute \src "libresoc.v:98232.5-98232.29" + attribute \src "libresoc.v:98296.5-98296.29" switch \initial - attribute \src "libresoc.v:98232.9-98232.17" + attribute \src "libresoc.v:98296.9-98296.17" case 1'1 case end @@ -153165,14 +153216,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_sgl_pipe $0\dec31_dec_sub15_sgl_pipe[0:0] end - attribute \src "libresoc.v:98334.3-98436.6" - process $proc$libresoc.v:98334$3980 + attribute \src "libresoc.v:98398.3-98500.6" + process $proc$libresoc.v:98398$3980 assign { } { } assign { } { } assign $0\dec31_dec_sub15_SV_Etype[1:0] $1\dec31_dec_sub15_SV_Etype[1:0] - attribute \src "libresoc.v:98335.5-98335.29" + attribute \src "libresoc.v:98399.5-98399.29" switch \initial - attribute \src "libresoc.v:98335.9-98335.17" + attribute \src "libresoc.v:98399.9-98399.17" case 1'1 case end @@ -153312,14 +153363,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_SV_Etype $0\dec31_dec_sub15_SV_Etype[1:0] end - attribute \src "libresoc.v:98437.3-98539.6" - process $proc$libresoc.v:98437$3981 + attribute \src "libresoc.v:98501.3-98603.6" + process $proc$libresoc.v:98501$3981 assign { } { } assign { } { } assign $0\dec31_dec_sub15_SV_Ptype[1:0] $1\dec31_dec_sub15_SV_Ptype[1:0] - attribute \src "libresoc.v:98438.5-98438.29" + attribute \src "libresoc.v:98502.5-98502.29" switch \initial - attribute \src "libresoc.v:98438.9-98438.17" + attribute \src "libresoc.v:98502.9-98502.17" case 1'1 case end @@ -153459,14 +153510,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_SV_Ptype $0\dec31_dec_sub15_SV_Ptype[1:0] end - attribute \src "libresoc.v:98540.3-98642.6" - process $proc$libresoc.v:98540$3982 + attribute \src "libresoc.v:98604.3-98706.6" + process $proc$libresoc.v:98604$3982 assign { } { } assign { } { } assign $0\dec31_dec_sub15_in1_sel[2:0] $1\dec31_dec_sub15_in1_sel[2:0] - attribute \src "libresoc.v:98541.5-98541.29" + attribute \src "libresoc.v:98605.5-98605.29" switch \initial - attribute \src "libresoc.v:98541.9-98541.17" + attribute \src "libresoc.v:98605.9-98605.17" case 1'1 case end @@ -153606,14 +153657,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_in1_sel $0\dec31_dec_sub15_in1_sel[2:0] end - attribute \src "libresoc.v:98643.3-98745.6" - process $proc$libresoc.v:98643$3983 + attribute \src "libresoc.v:98707.3-98809.6" + process $proc$libresoc.v:98707$3983 assign { } { } assign { } { } assign $0\dec31_dec_sub15_in2_sel[3:0] $1\dec31_dec_sub15_in2_sel[3:0] - attribute \src "libresoc.v:98644.5-98644.29" + attribute \src "libresoc.v:98708.5-98708.29" switch \initial - attribute \src "libresoc.v:98644.9-98644.17" + attribute \src "libresoc.v:98708.9-98708.17" case 1'1 case end @@ -153753,14 +153804,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_in2_sel $0\dec31_dec_sub15_in2_sel[3:0] end - attribute \src "libresoc.v:98746.3-98848.6" - process $proc$libresoc.v:98746$3984 + attribute \src "libresoc.v:98810.3-98912.6" + process $proc$libresoc.v:98810$3984 assign { } { } assign { } { } assign $0\dec31_dec_sub15_in3_sel[1:0] $1\dec31_dec_sub15_in3_sel[1:0] - attribute \src "libresoc.v:98747.5-98747.29" + attribute \src "libresoc.v:98811.5-98811.29" switch \initial - attribute \src "libresoc.v:98747.9-98747.17" + attribute \src "libresoc.v:98811.9-98811.17" case 1'1 case end @@ -153900,14 +153951,14 @@ module \dec31_dec_sub15 sync always update \dec31_dec_sub15_in3_sel $0\dec31_dec_sub15_in3_sel[1:0] end - attribute \src "libresoc.v:98849.3-98951.6" - process $proc$libresoc.v:98849$3985 + attribute \src "libresoc.v:98913.3-99015.6" + process $proc$libresoc.v:98913$3985 assign { } { } assign { } { } assign $0\dec31_dec_sub15_out_sel[2:0] $1\dec31_dec_sub15_out_sel[2:0] - attribute \src "libresoc.v:98850.5-98850.29" + attribute \src "libresoc.v:98914.5-98914.29" switch \initial - attribute \src "libresoc.v:98850.9-98850.17" + attribute \src "libresoc.v:98914.9-98914.17" case 1'1 case end @@ -154049,144 +154100,144 @@ module \dec31_dec_sub15 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:98957.1-99637.10" +attribute \src "libresoc.v:99021.1-99701.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub16" attribute \generator "nMigen" module \dec31_dec_sub16 - attribute \src "libresoc.v:99576.3-99585.6" + attribute \src "libresoc.v:99640.3-99649.6" wire width 2 $0\dec31_dec_sub16_SV_Etype[1:0] - attribute \src "libresoc.v:99586.3-99595.6" + attribute \src "libresoc.v:99650.3-99659.6" wire width 2 $0\dec31_dec_sub16_SV_Ptype[1:0] - attribute \src "libresoc.v:99456.3-99465.6" + attribute \src "libresoc.v:99520.3-99529.6" wire width 8 $0\dec31_dec_sub16_asmcode[7:0] - attribute \src "libresoc.v:99496.3-99505.6" + attribute \src "libresoc.v:99560.3-99569.6" wire $0\dec31_dec_sub16_br[0:0] - attribute \src "libresoc.v:99316.3-99325.6" + attribute \src "libresoc.v:99380.3-99389.6" wire width 3 $0\dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:99326.3-99335.6" + attribute \src "libresoc.v:99390.3-99399.6" wire width 3 $0\dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:99446.3-99455.6" + attribute \src "libresoc.v:99510.3-99519.6" wire width 2 $0\dec31_dec_sub16_cry_in[1:0] - attribute \src "libresoc.v:99486.3-99495.6" + attribute \src "libresoc.v:99550.3-99559.6" wire $0\dec31_dec_sub16_cry_out[0:0] - attribute \src "libresoc.v:99526.3-99535.6" + attribute \src "libresoc.v:99590.3-99599.6" wire width 5 $0\dec31_dec_sub16_form[4:0] - attribute \src "libresoc.v:99306.3-99315.6" + attribute \src "libresoc.v:99370.3-99379.6" wire width 14 $0\dec31_dec_sub16_function_unit[13:0] - attribute \src "libresoc.v:99596.3-99605.6" + attribute \src "libresoc.v:99660.3-99669.6" wire width 3 $0\dec31_dec_sub16_in1_sel[2:0] - attribute \src "libresoc.v:99606.3-99615.6" + attribute \src "libresoc.v:99670.3-99679.6" wire width 4 $0\dec31_dec_sub16_in2_sel[3:0] - attribute \src "libresoc.v:99616.3-99625.6" + attribute \src "libresoc.v:99680.3-99689.6" wire width 2 $0\dec31_dec_sub16_in3_sel[1:0] - attribute \src "libresoc.v:99416.3-99425.6" + attribute \src "libresoc.v:99480.3-99489.6" wire width 7 $0\dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:99466.3-99475.6" + attribute \src "libresoc.v:99530.3-99539.6" wire $0\dec31_dec_sub16_inv_a[0:0] - attribute \src "libresoc.v:99476.3-99485.6" + attribute \src "libresoc.v:99540.3-99549.6" wire $0\dec31_dec_sub16_inv_out[0:0] - attribute \src "libresoc.v:99536.3-99545.6" + attribute \src "libresoc.v:99600.3-99609.6" wire $0\dec31_dec_sub16_is_32b[0:0] - attribute \src "libresoc.v:99406.3-99415.6" + attribute \src "libresoc.v:99470.3-99479.6" wire width 4 $0\dec31_dec_sub16_ldst_len[3:0] - attribute \src "libresoc.v:99556.3-99565.6" + attribute \src "libresoc.v:99620.3-99629.6" wire $0\dec31_dec_sub16_lk[0:0] - attribute \src "libresoc.v:99626.3-99635.6" + attribute \src "libresoc.v:99690.3-99699.6" wire width 3 $0\dec31_dec_sub16_out_sel[2:0] - attribute \src "libresoc.v:99436.3-99445.6" + attribute \src "libresoc.v:99500.3-99509.6" wire width 2 $0\dec31_dec_sub16_rc_sel[1:0] - attribute \src "libresoc.v:99516.3-99525.6" + attribute \src "libresoc.v:99580.3-99589.6" wire $0\dec31_dec_sub16_rsrv[0:0] - attribute \src "libresoc.v:99566.3-99575.6" + attribute \src "libresoc.v:99630.3-99639.6" wire $0\dec31_dec_sub16_sgl_pipe[0:0] - attribute \src "libresoc.v:99546.3-99555.6" + attribute \src "libresoc.v:99610.3-99619.6" wire $0\dec31_dec_sub16_sgn[0:0] - attribute \src "libresoc.v:99506.3-99515.6" + attribute \src "libresoc.v:99570.3-99579.6" wire $0\dec31_dec_sub16_sgn_ext[0:0] - attribute \src "libresoc.v:99386.3-99395.6" + attribute \src "libresoc.v:99450.3-99459.6" wire width 3 $0\dec31_dec_sub16_sv_cr_in[2:0] - attribute \src "libresoc.v:99396.3-99405.6" + attribute \src "libresoc.v:99460.3-99469.6" wire width 3 $0\dec31_dec_sub16_sv_cr_out[2:0] - attribute \src "libresoc.v:99336.3-99345.6" + attribute \src "libresoc.v:99400.3-99409.6" wire width 3 $0\dec31_dec_sub16_sv_in1[2:0] - attribute \src "libresoc.v:99346.3-99355.6" + attribute \src "libresoc.v:99410.3-99419.6" wire width 3 $0\dec31_dec_sub16_sv_in2[2:0] - attribute \src "libresoc.v:99356.3-99365.6" + attribute \src "libresoc.v:99420.3-99429.6" wire width 3 $0\dec31_dec_sub16_sv_in3[2:0] - attribute \src "libresoc.v:99376.3-99385.6" + attribute \src "libresoc.v:99440.3-99449.6" wire width 3 $0\dec31_dec_sub16_sv_out2[2:0] - attribute \src "libresoc.v:99366.3-99375.6" + attribute \src "libresoc.v:99430.3-99439.6" wire width 3 $0\dec31_dec_sub16_sv_out[2:0] - attribute \src "libresoc.v:99426.3-99435.6" + attribute \src "libresoc.v:99490.3-99499.6" wire width 2 $0\dec31_dec_sub16_upd[1:0] - attribute \src "libresoc.v:98958.7-98958.20" + attribute \src "libresoc.v:99022.7-99022.20" wire $0\initial[0:0] - attribute \src "libresoc.v:99576.3-99585.6" + attribute \src "libresoc.v:99640.3-99649.6" wire width 2 $1\dec31_dec_sub16_SV_Etype[1:0] - attribute \src "libresoc.v:99586.3-99595.6" + attribute \src "libresoc.v:99650.3-99659.6" wire width 2 $1\dec31_dec_sub16_SV_Ptype[1:0] - attribute \src "libresoc.v:99456.3-99465.6" + attribute \src "libresoc.v:99520.3-99529.6" wire width 8 $1\dec31_dec_sub16_asmcode[7:0] - attribute \src "libresoc.v:99496.3-99505.6" + attribute \src "libresoc.v:99560.3-99569.6" wire $1\dec31_dec_sub16_br[0:0] - attribute \src "libresoc.v:99316.3-99325.6" + attribute \src "libresoc.v:99380.3-99389.6" wire width 3 $1\dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:99326.3-99335.6" + attribute \src "libresoc.v:99390.3-99399.6" wire width 3 $1\dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:99446.3-99455.6" + attribute \src "libresoc.v:99510.3-99519.6" wire width 2 $1\dec31_dec_sub16_cry_in[1:0] - attribute \src "libresoc.v:99486.3-99495.6" + attribute \src "libresoc.v:99550.3-99559.6" wire $1\dec31_dec_sub16_cry_out[0:0] - attribute \src "libresoc.v:99526.3-99535.6" + attribute \src "libresoc.v:99590.3-99599.6" wire width 5 $1\dec31_dec_sub16_form[4:0] - attribute \src "libresoc.v:99306.3-99315.6" + attribute \src "libresoc.v:99370.3-99379.6" wire width 14 $1\dec31_dec_sub16_function_unit[13:0] - attribute \src "libresoc.v:99596.3-99605.6" + attribute \src "libresoc.v:99660.3-99669.6" wire width 3 $1\dec31_dec_sub16_in1_sel[2:0] - attribute \src "libresoc.v:99606.3-99615.6" + attribute \src "libresoc.v:99670.3-99679.6" wire width 4 $1\dec31_dec_sub16_in2_sel[3:0] - attribute \src "libresoc.v:99616.3-99625.6" + attribute \src "libresoc.v:99680.3-99689.6" wire width 2 $1\dec31_dec_sub16_in3_sel[1:0] - attribute \src "libresoc.v:99416.3-99425.6" + attribute \src "libresoc.v:99480.3-99489.6" wire width 7 $1\dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:99466.3-99475.6" + attribute \src "libresoc.v:99530.3-99539.6" wire $1\dec31_dec_sub16_inv_a[0:0] - attribute \src "libresoc.v:99476.3-99485.6" + attribute \src "libresoc.v:99540.3-99549.6" wire $1\dec31_dec_sub16_inv_out[0:0] - attribute \src "libresoc.v:99536.3-99545.6" + attribute \src "libresoc.v:99600.3-99609.6" wire $1\dec31_dec_sub16_is_32b[0:0] - attribute \src "libresoc.v:99406.3-99415.6" + attribute \src "libresoc.v:99470.3-99479.6" wire width 4 $1\dec31_dec_sub16_ldst_len[3:0] - attribute \src "libresoc.v:99556.3-99565.6" + attribute \src "libresoc.v:99620.3-99629.6" wire $1\dec31_dec_sub16_lk[0:0] - attribute \src "libresoc.v:99626.3-99635.6" + attribute \src "libresoc.v:99690.3-99699.6" wire width 3 $1\dec31_dec_sub16_out_sel[2:0] - attribute \src "libresoc.v:99436.3-99445.6" + attribute \src "libresoc.v:99500.3-99509.6" wire width 2 $1\dec31_dec_sub16_rc_sel[1:0] - attribute \src "libresoc.v:99516.3-99525.6" + attribute \src "libresoc.v:99580.3-99589.6" wire $1\dec31_dec_sub16_rsrv[0:0] - attribute \src "libresoc.v:99566.3-99575.6" + attribute \src "libresoc.v:99630.3-99639.6" wire $1\dec31_dec_sub16_sgl_pipe[0:0] - attribute \src "libresoc.v:99546.3-99555.6" + attribute \src "libresoc.v:99610.3-99619.6" wire $1\dec31_dec_sub16_sgn[0:0] - attribute \src "libresoc.v:99506.3-99515.6" + attribute \src "libresoc.v:99570.3-99579.6" wire $1\dec31_dec_sub16_sgn_ext[0:0] - attribute \src "libresoc.v:99386.3-99395.6" + attribute \src "libresoc.v:99450.3-99459.6" wire width 3 $1\dec31_dec_sub16_sv_cr_in[2:0] - attribute \src "libresoc.v:99396.3-99405.6" + attribute \src "libresoc.v:99460.3-99469.6" wire width 3 $1\dec31_dec_sub16_sv_cr_out[2:0] - attribute \src "libresoc.v:99336.3-99345.6" + attribute \src "libresoc.v:99400.3-99409.6" wire width 3 $1\dec31_dec_sub16_sv_in1[2:0] - attribute \src "libresoc.v:99346.3-99355.6" + attribute \src "libresoc.v:99410.3-99419.6" wire width 3 $1\dec31_dec_sub16_sv_in2[2:0] - attribute \src "libresoc.v:99356.3-99365.6" + attribute \src "libresoc.v:99420.3-99429.6" wire width 3 $1\dec31_dec_sub16_sv_in3[2:0] - attribute \src "libresoc.v:99376.3-99385.6" + attribute \src "libresoc.v:99440.3-99449.6" wire width 3 $1\dec31_dec_sub16_sv_out2[2:0] - attribute \src "libresoc.v:99366.3-99375.6" + attribute \src "libresoc.v:99430.3-99439.6" wire width 3 $1\dec31_dec_sub16_sv_out[2:0] - attribute \src "libresoc.v:99426.3-99435.6" + attribute \src "libresoc.v:99490.3-99499.6" wire width 2 $1\dec31_dec_sub16_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -154498,28 +154549,28 @@ module \dec31_dec_sub16 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub16_upd - attribute \src "libresoc.v:98958.7-98958.15" + attribute \src "libresoc.v:99022.7-99022.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:98958.7-98958.20" - process $proc$libresoc.v:98958$4020 + attribute \src "libresoc.v:99022.7-99022.20" + process $proc$libresoc.v:99022$4020 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:99306.3-99315.6" - process $proc$libresoc.v:99306$3987 + attribute \src "libresoc.v:99370.3-99379.6" + process $proc$libresoc.v:99370$3987 assign { } { } assign { } { } assign $0\dec31_dec_sub16_function_unit[13:0] $1\dec31_dec_sub16_function_unit[13:0] - attribute \src "libresoc.v:99307.5-99307.29" + attribute \src "libresoc.v:99371.5-99371.29" switch \initial - attribute \src "libresoc.v:99307.9-99307.17" + attribute \src "libresoc.v:99371.9-99371.17" case 1'1 case end @@ -154535,14 +154586,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_function_unit $0\dec31_dec_sub16_function_unit[13:0] end - attribute \src "libresoc.v:99316.3-99325.6" - process $proc$libresoc.v:99316$3988 + attribute \src "libresoc.v:99380.3-99389.6" + process $proc$libresoc.v:99380$3988 assign { } { } assign { } { } assign $0\dec31_dec_sub16_cr_in[2:0] $1\dec31_dec_sub16_cr_in[2:0] - attribute \src "libresoc.v:99317.5-99317.29" + attribute \src "libresoc.v:99381.5-99381.29" switch \initial - attribute \src "libresoc.v:99317.9-99317.17" + attribute \src "libresoc.v:99381.9-99381.17" case 1'1 case end @@ -154558,14 +154609,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_cr_in $0\dec31_dec_sub16_cr_in[2:0] end - attribute \src "libresoc.v:99326.3-99335.6" - process $proc$libresoc.v:99326$3989 + attribute \src "libresoc.v:99390.3-99399.6" + process $proc$libresoc.v:99390$3989 assign { } { } assign { } { } assign $0\dec31_dec_sub16_cr_out[2:0] $1\dec31_dec_sub16_cr_out[2:0] - attribute \src "libresoc.v:99327.5-99327.29" + attribute \src "libresoc.v:99391.5-99391.29" switch \initial - attribute \src "libresoc.v:99327.9-99327.17" + attribute \src "libresoc.v:99391.9-99391.17" case 1'1 case end @@ -154581,14 +154632,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_cr_out $0\dec31_dec_sub16_cr_out[2:0] end - attribute \src "libresoc.v:99336.3-99345.6" - process $proc$libresoc.v:99336$3990 + attribute \src "libresoc.v:99400.3-99409.6" + process $proc$libresoc.v:99400$3990 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_in1[2:0] $1\dec31_dec_sub16_sv_in1[2:0] - attribute \src "libresoc.v:99337.5-99337.29" + attribute \src "libresoc.v:99401.5-99401.29" switch \initial - attribute \src "libresoc.v:99337.9-99337.17" + attribute \src "libresoc.v:99401.9-99401.17" case 1'1 case end @@ -154604,14 +154655,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_in1 $0\dec31_dec_sub16_sv_in1[2:0] end - attribute \src "libresoc.v:99346.3-99355.6" - process $proc$libresoc.v:99346$3991 + attribute \src "libresoc.v:99410.3-99419.6" + process $proc$libresoc.v:99410$3991 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_in2[2:0] $1\dec31_dec_sub16_sv_in2[2:0] - attribute \src "libresoc.v:99347.5-99347.29" + attribute \src "libresoc.v:99411.5-99411.29" switch \initial - attribute \src "libresoc.v:99347.9-99347.17" + attribute \src "libresoc.v:99411.9-99411.17" case 1'1 case end @@ -154627,14 +154678,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_in2 $0\dec31_dec_sub16_sv_in2[2:0] end - attribute \src "libresoc.v:99356.3-99365.6" - process $proc$libresoc.v:99356$3992 + attribute \src "libresoc.v:99420.3-99429.6" + process $proc$libresoc.v:99420$3992 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_in3[2:0] $1\dec31_dec_sub16_sv_in3[2:0] - attribute \src "libresoc.v:99357.5-99357.29" + attribute \src "libresoc.v:99421.5-99421.29" switch \initial - attribute \src "libresoc.v:99357.9-99357.17" + attribute \src "libresoc.v:99421.9-99421.17" case 1'1 case end @@ -154650,14 +154701,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_in3 $0\dec31_dec_sub16_sv_in3[2:0] end - attribute \src "libresoc.v:99366.3-99375.6" - process $proc$libresoc.v:99366$3993 + attribute \src "libresoc.v:99430.3-99439.6" + process $proc$libresoc.v:99430$3993 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_out[2:0] $1\dec31_dec_sub16_sv_out[2:0] - attribute \src "libresoc.v:99367.5-99367.29" + attribute \src "libresoc.v:99431.5-99431.29" switch \initial - attribute \src "libresoc.v:99367.9-99367.17" + attribute \src "libresoc.v:99431.9-99431.17" case 1'1 case end @@ -154673,14 +154724,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_out $0\dec31_dec_sub16_sv_out[2:0] end - attribute \src "libresoc.v:99376.3-99385.6" - process $proc$libresoc.v:99376$3994 + attribute \src "libresoc.v:99440.3-99449.6" + process $proc$libresoc.v:99440$3994 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_out2[2:0] $1\dec31_dec_sub16_sv_out2[2:0] - attribute \src "libresoc.v:99377.5-99377.29" + attribute \src "libresoc.v:99441.5-99441.29" switch \initial - attribute \src "libresoc.v:99377.9-99377.17" + attribute \src "libresoc.v:99441.9-99441.17" case 1'1 case end @@ -154696,14 +154747,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_out2 $0\dec31_dec_sub16_sv_out2[2:0] end - attribute \src "libresoc.v:99386.3-99395.6" - process $proc$libresoc.v:99386$3995 + attribute \src "libresoc.v:99450.3-99459.6" + process $proc$libresoc.v:99450$3995 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_cr_in[2:0] $1\dec31_dec_sub16_sv_cr_in[2:0] - attribute \src "libresoc.v:99387.5-99387.29" + attribute \src "libresoc.v:99451.5-99451.29" switch \initial - attribute \src "libresoc.v:99387.9-99387.17" + attribute \src "libresoc.v:99451.9-99451.17" case 1'1 case end @@ -154719,14 +154770,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_cr_in $0\dec31_dec_sub16_sv_cr_in[2:0] end - attribute \src "libresoc.v:99396.3-99405.6" - process $proc$libresoc.v:99396$3996 + attribute \src "libresoc.v:99460.3-99469.6" + process $proc$libresoc.v:99460$3996 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sv_cr_out[2:0] $1\dec31_dec_sub16_sv_cr_out[2:0] - attribute \src "libresoc.v:99397.5-99397.29" + attribute \src "libresoc.v:99461.5-99461.29" switch \initial - attribute \src "libresoc.v:99397.9-99397.17" + attribute \src "libresoc.v:99461.9-99461.17" case 1'1 case end @@ -154742,14 +154793,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sv_cr_out $0\dec31_dec_sub16_sv_cr_out[2:0] end - attribute \src "libresoc.v:99406.3-99415.6" - process $proc$libresoc.v:99406$3997 + attribute \src "libresoc.v:99470.3-99479.6" + process $proc$libresoc.v:99470$3997 assign { } { } assign { } { } assign $0\dec31_dec_sub16_ldst_len[3:0] $1\dec31_dec_sub16_ldst_len[3:0] - attribute \src "libresoc.v:99407.5-99407.29" + attribute \src "libresoc.v:99471.5-99471.29" switch \initial - attribute \src "libresoc.v:99407.9-99407.17" + attribute \src "libresoc.v:99471.9-99471.17" case 1'1 case end @@ -154765,14 +154816,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_ldst_len $0\dec31_dec_sub16_ldst_len[3:0] end - attribute \src "libresoc.v:99416.3-99425.6" - process $proc$libresoc.v:99416$3998 + attribute \src "libresoc.v:99480.3-99489.6" + process $proc$libresoc.v:99480$3998 assign { } { } assign { } { } assign $0\dec31_dec_sub16_internal_op[6:0] $1\dec31_dec_sub16_internal_op[6:0] - attribute \src "libresoc.v:99417.5-99417.29" + attribute \src "libresoc.v:99481.5-99481.29" switch \initial - attribute \src "libresoc.v:99417.9-99417.17" + attribute \src "libresoc.v:99481.9-99481.17" case 1'1 case end @@ -154788,14 +154839,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_internal_op $0\dec31_dec_sub16_internal_op[6:0] end - attribute \src "libresoc.v:99426.3-99435.6" - process $proc$libresoc.v:99426$3999 + attribute \src "libresoc.v:99490.3-99499.6" + process $proc$libresoc.v:99490$3999 assign { } { } assign { } { } assign $0\dec31_dec_sub16_upd[1:0] $1\dec31_dec_sub16_upd[1:0] - attribute \src "libresoc.v:99427.5-99427.29" + attribute \src "libresoc.v:99491.5-99491.29" switch \initial - attribute \src "libresoc.v:99427.9-99427.17" + attribute \src "libresoc.v:99491.9-99491.17" case 1'1 case end @@ -154811,14 +154862,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_upd $0\dec31_dec_sub16_upd[1:0] end - attribute \src "libresoc.v:99436.3-99445.6" - process $proc$libresoc.v:99436$4000 + attribute \src "libresoc.v:99500.3-99509.6" + process $proc$libresoc.v:99500$4000 assign { } { } assign { } { } assign $0\dec31_dec_sub16_rc_sel[1:0] $1\dec31_dec_sub16_rc_sel[1:0] - attribute \src "libresoc.v:99437.5-99437.29" + attribute \src "libresoc.v:99501.5-99501.29" switch \initial - attribute \src "libresoc.v:99437.9-99437.17" + attribute \src "libresoc.v:99501.9-99501.17" case 1'1 case end @@ -154834,14 +154885,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_rc_sel $0\dec31_dec_sub16_rc_sel[1:0] end - attribute \src "libresoc.v:99446.3-99455.6" - process $proc$libresoc.v:99446$4001 + attribute \src "libresoc.v:99510.3-99519.6" + process $proc$libresoc.v:99510$4001 assign { } { } assign { } { } assign $0\dec31_dec_sub16_cry_in[1:0] $1\dec31_dec_sub16_cry_in[1:0] - attribute \src "libresoc.v:99447.5-99447.29" + attribute \src "libresoc.v:99511.5-99511.29" switch \initial - attribute \src "libresoc.v:99447.9-99447.17" + attribute \src "libresoc.v:99511.9-99511.17" case 1'1 case end @@ -154857,14 +154908,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_cry_in $0\dec31_dec_sub16_cry_in[1:0] end - attribute \src "libresoc.v:99456.3-99465.6" - process $proc$libresoc.v:99456$4002 + attribute \src "libresoc.v:99520.3-99529.6" + process $proc$libresoc.v:99520$4002 assign { } { } assign { } { } assign $0\dec31_dec_sub16_asmcode[7:0] $1\dec31_dec_sub16_asmcode[7:0] - attribute \src "libresoc.v:99457.5-99457.29" + attribute \src "libresoc.v:99521.5-99521.29" switch \initial - attribute \src "libresoc.v:99457.9-99457.17" + attribute \src "libresoc.v:99521.9-99521.17" case 1'1 case end @@ -154880,14 +154931,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_asmcode $0\dec31_dec_sub16_asmcode[7:0] end - attribute \src "libresoc.v:99466.3-99475.6" - process $proc$libresoc.v:99466$4003 + attribute \src "libresoc.v:99530.3-99539.6" + process $proc$libresoc.v:99530$4003 assign { } { } assign { } { } assign $0\dec31_dec_sub16_inv_a[0:0] $1\dec31_dec_sub16_inv_a[0:0] - attribute \src "libresoc.v:99467.5-99467.29" + attribute \src "libresoc.v:99531.5-99531.29" switch \initial - attribute \src "libresoc.v:99467.9-99467.17" + attribute \src "libresoc.v:99531.9-99531.17" case 1'1 case end @@ -154903,14 +154954,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_inv_a $0\dec31_dec_sub16_inv_a[0:0] end - attribute \src "libresoc.v:99476.3-99485.6" - process $proc$libresoc.v:99476$4004 + attribute \src "libresoc.v:99540.3-99549.6" + process $proc$libresoc.v:99540$4004 assign { } { } assign { } { } assign $0\dec31_dec_sub16_inv_out[0:0] $1\dec31_dec_sub16_inv_out[0:0] - attribute \src "libresoc.v:99477.5-99477.29" + attribute \src "libresoc.v:99541.5-99541.29" switch \initial - attribute \src "libresoc.v:99477.9-99477.17" + attribute \src "libresoc.v:99541.9-99541.17" case 1'1 case end @@ -154926,14 +154977,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_inv_out $0\dec31_dec_sub16_inv_out[0:0] end - attribute \src "libresoc.v:99486.3-99495.6" - process $proc$libresoc.v:99486$4005 + attribute \src "libresoc.v:99550.3-99559.6" + process $proc$libresoc.v:99550$4005 assign { } { } assign { } { } assign $0\dec31_dec_sub16_cry_out[0:0] $1\dec31_dec_sub16_cry_out[0:0] - attribute \src "libresoc.v:99487.5-99487.29" + attribute \src "libresoc.v:99551.5-99551.29" switch \initial - attribute \src "libresoc.v:99487.9-99487.17" + attribute \src "libresoc.v:99551.9-99551.17" case 1'1 case end @@ -154949,14 +155000,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_cry_out $0\dec31_dec_sub16_cry_out[0:0] end - attribute \src "libresoc.v:99496.3-99505.6" - process $proc$libresoc.v:99496$4006 + attribute \src "libresoc.v:99560.3-99569.6" + process $proc$libresoc.v:99560$4006 assign { } { } assign { } { } assign $0\dec31_dec_sub16_br[0:0] $1\dec31_dec_sub16_br[0:0] - attribute \src "libresoc.v:99497.5-99497.29" + attribute \src "libresoc.v:99561.5-99561.29" switch \initial - attribute \src "libresoc.v:99497.9-99497.17" + attribute \src "libresoc.v:99561.9-99561.17" case 1'1 case end @@ -154972,14 +155023,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_br $0\dec31_dec_sub16_br[0:0] end - attribute \src "libresoc.v:99506.3-99515.6" - process $proc$libresoc.v:99506$4007 + attribute \src "libresoc.v:99570.3-99579.6" + process $proc$libresoc.v:99570$4007 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sgn_ext[0:0] $1\dec31_dec_sub16_sgn_ext[0:0] - attribute \src "libresoc.v:99507.5-99507.29" + attribute \src "libresoc.v:99571.5-99571.29" switch \initial - attribute \src "libresoc.v:99507.9-99507.17" + attribute \src "libresoc.v:99571.9-99571.17" case 1'1 case end @@ -154995,14 +155046,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sgn_ext $0\dec31_dec_sub16_sgn_ext[0:0] end - attribute \src "libresoc.v:99516.3-99525.6" - process $proc$libresoc.v:99516$4008 + attribute \src "libresoc.v:99580.3-99589.6" + process $proc$libresoc.v:99580$4008 assign { } { } assign { } { } assign $0\dec31_dec_sub16_rsrv[0:0] $1\dec31_dec_sub16_rsrv[0:0] - attribute \src "libresoc.v:99517.5-99517.29" + attribute \src "libresoc.v:99581.5-99581.29" switch \initial - attribute \src "libresoc.v:99517.9-99517.17" + attribute \src "libresoc.v:99581.9-99581.17" case 1'1 case end @@ -155018,14 +155069,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_rsrv $0\dec31_dec_sub16_rsrv[0:0] end - attribute \src "libresoc.v:99526.3-99535.6" - process $proc$libresoc.v:99526$4009 + attribute \src "libresoc.v:99590.3-99599.6" + process $proc$libresoc.v:99590$4009 assign { } { } assign { } { } assign $0\dec31_dec_sub16_form[4:0] $1\dec31_dec_sub16_form[4:0] - attribute \src "libresoc.v:99527.5-99527.29" + attribute \src "libresoc.v:99591.5-99591.29" switch \initial - attribute \src "libresoc.v:99527.9-99527.17" + attribute \src "libresoc.v:99591.9-99591.17" case 1'1 case end @@ -155041,14 +155092,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_form $0\dec31_dec_sub16_form[4:0] end - attribute \src "libresoc.v:99536.3-99545.6" - process $proc$libresoc.v:99536$4010 + attribute \src "libresoc.v:99600.3-99609.6" + process $proc$libresoc.v:99600$4010 assign { } { } assign { } { } assign $0\dec31_dec_sub16_is_32b[0:0] $1\dec31_dec_sub16_is_32b[0:0] - attribute \src "libresoc.v:99537.5-99537.29" + attribute \src "libresoc.v:99601.5-99601.29" switch \initial - attribute \src "libresoc.v:99537.9-99537.17" + attribute \src "libresoc.v:99601.9-99601.17" case 1'1 case end @@ -155064,14 +155115,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_is_32b $0\dec31_dec_sub16_is_32b[0:0] end - attribute \src "libresoc.v:99546.3-99555.6" - process $proc$libresoc.v:99546$4011 + attribute \src "libresoc.v:99610.3-99619.6" + process $proc$libresoc.v:99610$4011 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sgn[0:0] $1\dec31_dec_sub16_sgn[0:0] - attribute \src "libresoc.v:99547.5-99547.29" + attribute \src "libresoc.v:99611.5-99611.29" switch \initial - attribute \src "libresoc.v:99547.9-99547.17" + attribute \src "libresoc.v:99611.9-99611.17" case 1'1 case end @@ -155087,14 +155138,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sgn $0\dec31_dec_sub16_sgn[0:0] end - attribute \src "libresoc.v:99556.3-99565.6" - process $proc$libresoc.v:99556$4012 + attribute \src "libresoc.v:99620.3-99629.6" + process $proc$libresoc.v:99620$4012 assign { } { } assign { } { } assign $0\dec31_dec_sub16_lk[0:0] $1\dec31_dec_sub16_lk[0:0] - attribute \src "libresoc.v:99557.5-99557.29" + attribute \src "libresoc.v:99621.5-99621.29" switch \initial - attribute \src "libresoc.v:99557.9-99557.17" + attribute \src "libresoc.v:99621.9-99621.17" case 1'1 case end @@ -155110,14 +155161,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_lk $0\dec31_dec_sub16_lk[0:0] end - attribute \src "libresoc.v:99566.3-99575.6" - process $proc$libresoc.v:99566$4013 + attribute \src "libresoc.v:99630.3-99639.6" + process $proc$libresoc.v:99630$4013 assign { } { } assign { } { } assign $0\dec31_dec_sub16_sgl_pipe[0:0] $1\dec31_dec_sub16_sgl_pipe[0:0] - attribute \src "libresoc.v:99567.5-99567.29" + attribute \src "libresoc.v:99631.5-99631.29" switch \initial - attribute \src "libresoc.v:99567.9-99567.17" + attribute \src "libresoc.v:99631.9-99631.17" case 1'1 case end @@ -155133,14 +155184,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_sgl_pipe $0\dec31_dec_sub16_sgl_pipe[0:0] end - attribute \src "libresoc.v:99576.3-99585.6" - process $proc$libresoc.v:99576$4014 + attribute \src "libresoc.v:99640.3-99649.6" + process $proc$libresoc.v:99640$4014 assign { } { } assign { } { } assign $0\dec31_dec_sub16_SV_Etype[1:0] $1\dec31_dec_sub16_SV_Etype[1:0] - attribute \src "libresoc.v:99577.5-99577.29" + attribute \src "libresoc.v:99641.5-99641.29" switch \initial - attribute \src "libresoc.v:99577.9-99577.17" + attribute \src "libresoc.v:99641.9-99641.17" case 1'1 case end @@ -155156,14 +155207,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_SV_Etype $0\dec31_dec_sub16_SV_Etype[1:0] end - attribute \src "libresoc.v:99586.3-99595.6" - process $proc$libresoc.v:99586$4015 + attribute \src "libresoc.v:99650.3-99659.6" + process $proc$libresoc.v:99650$4015 assign { } { } assign { } { } assign $0\dec31_dec_sub16_SV_Ptype[1:0] $1\dec31_dec_sub16_SV_Ptype[1:0] - attribute \src "libresoc.v:99587.5-99587.29" + attribute \src "libresoc.v:99651.5-99651.29" switch \initial - attribute \src "libresoc.v:99587.9-99587.17" + attribute \src "libresoc.v:99651.9-99651.17" case 1'1 case end @@ -155179,14 +155230,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_SV_Ptype $0\dec31_dec_sub16_SV_Ptype[1:0] end - attribute \src "libresoc.v:99596.3-99605.6" - process $proc$libresoc.v:99596$4016 + attribute \src "libresoc.v:99660.3-99669.6" + process $proc$libresoc.v:99660$4016 assign { } { } assign { } { } assign $0\dec31_dec_sub16_in1_sel[2:0] $1\dec31_dec_sub16_in1_sel[2:0] - attribute \src "libresoc.v:99597.5-99597.29" + attribute \src "libresoc.v:99661.5-99661.29" switch \initial - attribute \src "libresoc.v:99597.9-99597.17" + attribute \src "libresoc.v:99661.9-99661.17" case 1'1 case end @@ -155202,14 +155253,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_in1_sel $0\dec31_dec_sub16_in1_sel[2:0] end - attribute \src "libresoc.v:99606.3-99615.6" - process $proc$libresoc.v:99606$4017 + attribute \src "libresoc.v:99670.3-99679.6" + process $proc$libresoc.v:99670$4017 assign { } { } assign { } { } assign $0\dec31_dec_sub16_in2_sel[3:0] $1\dec31_dec_sub16_in2_sel[3:0] - attribute \src "libresoc.v:99607.5-99607.29" + attribute \src "libresoc.v:99671.5-99671.29" switch \initial - attribute \src "libresoc.v:99607.9-99607.17" + attribute \src "libresoc.v:99671.9-99671.17" case 1'1 case end @@ -155225,14 +155276,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_in2_sel $0\dec31_dec_sub16_in2_sel[3:0] end - attribute \src "libresoc.v:99616.3-99625.6" - process $proc$libresoc.v:99616$4018 + attribute \src "libresoc.v:99680.3-99689.6" + process $proc$libresoc.v:99680$4018 assign { } { } assign { } { } assign $0\dec31_dec_sub16_in3_sel[1:0] $1\dec31_dec_sub16_in3_sel[1:0] - attribute \src "libresoc.v:99617.5-99617.29" + attribute \src "libresoc.v:99681.5-99681.29" switch \initial - attribute \src "libresoc.v:99617.9-99617.17" + attribute \src "libresoc.v:99681.9-99681.17" case 1'1 case end @@ -155248,14 +155299,14 @@ module \dec31_dec_sub16 sync always update \dec31_dec_sub16_in3_sel $0\dec31_dec_sub16_in3_sel[1:0] end - attribute \src "libresoc.v:99626.3-99635.6" - process $proc$libresoc.v:99626$4019 + attribute \src "libresoc.v:99690.3-99699.6" + process $proc$libresoc.v:99690$4019 assign { } { } assign { } { } assign $0\dec31_dec_sub16_out_sel[2:0] $1\dec31_dec_sub16_out_sel[2:0] - attribute \src "libresoc.v:99627.5-99627.29" + attribute \src "libresoc.v:99691.5-99691.29" switch \initial - attribute \src "libresoc.v:99627.9-99627.17" + attribute \src "libresoc.v:99691.9-99691.17" case 1'1 case end @@ -155273,144 +155324,144 @@ module \dec31_dec_sub16 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:99641.1-100717.10" +attribute \src "libresoc.v:99705.1-100781.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub18" attribute \generator "nMigen" module \dec31_dec_sub18 - attribute \src "libresoc.v:100584.3-100605.6" + attribute \src "libresoc.v:100648.3-100669.6" wire width 2 $0\dec31_dec_sub18_SV_Etype[1:0] - attribute \src "libresoc.v:100606.3-100627.6" + attribute \src "libresoc.v:100670.3-100691.6" wire width 2 $0\dec31_dec_sub18_SV_Ptype[1:0] - attribute \src "libresoc.v:100320.3-100341.6" + attribute \src "libresoc.v:100384.3-100405.6" wire width 8 $0\dec31_dec_sub18_asmcode[7:0] - attribute \src "libresoc.v:100408.3-100429.6" + attribute \src "libresoc.v:100472.3-100493.6" wire $0\dec31_dec_sub18_br[0:0] - attribute \src "libresoc.v:100012.3-100033.6" + attribute \src "libresoc.v:100076.3-100097.6" wire width 3 $0\dec31_dec_sub18_cr_in[2:0] - attribute \src "libresoc.v:100034.3-100055.6" + attribute \src "libresoc.v:100098.3-100119.6" wire width 3 $0\dec31_dec_sub18_cr_out[2:0] - attribute \src "libresoc.v:100298.3-100319.6" + attribute \src "libresoc.v:100362.3-100383.6" wire width 2 $0\dec31_dec_sub18_cry_in[1:0] - attribute \src "libresoc.v:100386.3-100407.6" + attribute \src "libresoc.v:100450.3-100471.6" wire $0\dec31_dec_sub18_cry_out[0:0] - attribute \src "libresoc.v:100474.3-100495.6" + attribute \src "libresoc.v:100538.3-100559.6" wire width 5 $0\dec31_dec_sub18_form[4:0] - attribute \src "libresoc.v:99990.3-100011.6" + attribute \src "libresoc.v:100054.3-100075.6" wire width 14 $0\dec31_dec_sub18_function_unit[13:0] - attribute \src "libresoc.v:100628.3-100649.6" + attribute \src "libresoc.v:100692.3-100713.6" wire width 3 $0\dec31_dec_sub18_in1_sel[2:0] - attribute \src "libresoc.v:100650.3-100671.6" + attribute \src "libresoc.v:100714.3-100735.6" wire width 4 $0\dec31_dec_sub18_in2_sel[3:0] - attribute \src "libresoc.v:100672.3-100693.6" + attribute \src "libresoc.v:100736.3-100757.6" wire width 2 $0\dec31_dec_sub18_in3_sel[1:0] - attribute \src "libresoc.v:100232.3-100253.6" + attribute \src "libresoc.v:100296.3-100317.6" wire width 7 $0\dec31_dec_sub18_internal_op[6:0] - attribute \src "libresoc.v:100342.3-100363.6" + attribute \src "libresoc.v:100406.3-100427.6" wire $0\dec31_dec_sub18_inv_a[0:0] - attribute \src "libresoc.v:100364.3-100385.6" + attribute \src "libresoc.v:100428.3-100449.6" wire $0\dec31_dec_sub18_inv_out[0:0] - attribute \src "libresoc.v:100496.3-100517.6" + attribute \src "libresoc.v:100560.3-100581.6" wire $0\dec31_dec_sub18_is_32b[0:0] - attribute \src "libresoc.v:100210.3-100231.6" + attribute \src "libresoc.v:100274.3-100295.6" wire width 4 $0\dec31_dec_sub18_ldst_len[3:0] - attribute \src "libresoc.v:100540.3-100561.6" + attribute \src "libresoc.v:100604.3-100625.6" wire $0\dec31_dec_sub18_lk[0:0] - attribute \src "libresoc.v:100694.3-100715.6" + attribute \src "libresoc.v:100758.3-100779.6" wire width 3 $0\dec31_dec_sub18_out_sel[2:0] - attribute \src "libresoc.v:100276.3-100297.6" + attribute \src "libresoc.v:100340.3-100361.6" wire width 2 $0\dec31_dec_sub18_rc_sel[1:0] - attribute \src "libresoc.v:100452.3-100473.6" + attribute \src "libresoc.v:100516.3-100537.6" wire $0\dec31_dec_sub18_rsrv[0:0] - attribute \src "libresoc.v:100562.3-100583.6" + attribute \src "libresoc.v:100626.3-100647.6" wire $0\dec31_dec_sub18_sgl_pipe[0:0] - attribute \src "libresoc.v:100518.3-100539.6" + attribute \src "libresoc.v:100582.3-100603.6" wire $0\dec31_dec_sub18_sgn[0:0] - attribute \src "libresoc.v:100430.3-100451.6" + attribute \src "libresoc.v:100494.3-100515.6" wire $0\dec31_dec_sub18_sgn_ext[0:0] - attribute \src "libresoc.v:100166.3-100187.6" + attribute \src "libresoc.v:100230.3-100251.6" wire width 3 $0\dec31_dec_sub18_sv_cr_in[2:0] - attribute \src "libresoc.v:100188.3-100209.6" + attribute \src "libresoc.v:100252.3-100273.6" wire width 3 $0\dec31_dec_sub18_sv_cr_out[2:0] - attribute \src "libresoc.v:100056.3-100077.6" + attribute \src "libresoc.v:100120.3-100141.6" wire width 3 $0\dec31_dec_sub18_sv_in1[2:0] - attribute \src "libresoc.v:100078.3-100099.6" + attribute \src "libresoc.v:100142.3-100163.6" wire width 3 $0\dec31_dec_sub18_sv_in2[2:0] - attribute \src "libresoc.v:100100.3-100121.6" + attribute \src "libresoc.v:100164.3-100185.6" wire width 3 $0\dec31_dec_sub18_sv_in3[2:0] - attribute \src "libresoc.v:100144.3-100165.6" + attribute \src "libresoc.v:100208.3-100229.6" wire width 3 $0\dec31_dec_sub18_sv_out2[2:0] - attribute \src "libresoc.v:100122.3-100143.6" + attribute \src "libresoc.v:100186.3-100207.6" wire width 3 $0\dec31_dec_sub18_sv_out[2:0] - attribute \src "libresoc.v:100254.3-100275.6" + attribute \src "libresoc.v:100318.3-100339.6" wire width 2 $0\dec31_dec_sub18_upd[1:0] - attribute \src "libresoc.v:99642.7-99642.20" + attribute \src "libresoc.v:99706.7-99706.20" wire $0\initial[0:0] - attribute \src "libresoc.v:100584.3-100605.6" + attribute \src "libresoc.v:100648.3-100669.6" wire width 2 $1\dec31_dec_sub18_SV_Etype[1:0] - attribute \src "libresoc.v:100606.3-100627.6" + attribute \src "libresoc.v:100670.3-100691.6" wire width 2 $1\dec31_dec_sub18_SV_Ptype[1:0] - attribute \src "libresoc.v:100320.3-100341.6" + attribute \src "libresoc.v:100384.3-100405.6" wire width 8 $1\dec31_dec_sub18_asmcode[7:0] - attribute \src "libresoc.v:100408.3-100429.6" + attribute \src "libresoc.v:100472.3-100493.6" wire $1\dec31_dec_sub18_br[0:0] - attribute \src "libresoc.v:100012.3-100033.6" + attribute \src "libresoc.v:100076.3-100097.6" wire width 3 $1\dec31_dec_sub18_cr_in[2:0] - attribute \src "libresoc.v:100034.3-100055.6" + attribute \src "libresoc.v:100098.3-100119.6" wire width 3 $1\dec31_dec_sub18_cr_out[2:0] - attribute \src "libresoc.v:100298.3-100319.6" + attribute \src "libresoc.v:100362.3-100383.6" wire width 2 $1\dec31_dec_sub18_cry_in[1:0] - attribute \src "libresoc.v:100386.3-100407.6" + attribute \src "libresoc.v:100450.3-100471.6" wire $1\dec31_dec_sub18_cry_out[0:0] - attribute \src "libresoc.v:100474.3-100495.6" + attribute \src "libresoc.v:100538.3-100559.6" wire width 5 $1\dec31_dec_sub18_form[4:0] - attribute \src "libresoc.v:99990.3-100011.6" + attribute \src "libresoc.v:100054.3-100075.6" wire width 14 $1\dec31_dec_sub18_function_unit[13:0] - attribute \src "libresoc.v:100628.3-100649.6" + attribute \src "libresoc.v:100692.3-100713.6" wire width 3 $1\dec31_dec_sub18_in1_sel[2:0] - attribute \src "libresoc.v:100650.3-100671.6" + attribute \src "libresoc.v:100714.3-100735.6" wire width 4 $1\dec31_dec_sub18_in2_sel[3:0] - attribute \src "libresoc.v:100672.3-100693.6" + attribute \src "libresoc.v:100736.3-100757.6" wire width 2 $1\dec31_dec_sub18_in3_sel[1:0] - attribute \src "libresoc.v:100232.3-100253.6" + attribute \src "libresoc.v:100296.3-100317.6" wire width 7 $1\dec31_dec_sub18_internal_op[6:0] - attribute \src "libresoc.v:100342.3-100363.6" + attribute \src "libresoc.v:100406.3-100427.6" wire $1\dec31_dec_sub18_inv_a[0:0] - attribute \src "libresoc.v:100364.3-100385.6" + attribute \src "libresoc.v:100428.3-100449.6" wire $1\dec31_dec_sub18_inv_out[0:0] - attribute \src "libresoc.v:100496.3-100517.6" + attribute \src "libresoc.v:100560.3-100581.6" wire $1\dec31_dec_sub18_is_32b[0:0] - attribute \src "libresoc.v:100210.3-100231.6" + attribute \src "libresoc.v:100274.3-100295.6" wire width 4 $1\dec31_dec_sub18_ldst_len[3:0] - attribute \src "libresoc.v:100540.3-100561.6" + attribute \src "libresoc.v:100604.3-100625.6" wire $1\dec31_dec_sub18_lk[0:0] - attribute \src "libresoc.v:100694.3-100715.6" + attribute \src "libresoc.v:100758.3-100779.6" wire width 3 $1\dec31_dec_sub18_out_sel[2:0] - attribute \src "libresoc.v:100276.3-100297.6" + attribute \src "libresoc.v:100340.3-100361.6" wire width 2 $1\dec31_dec_sub18_rc_sel[1:0] - attribute \src "libresoc.v:100452.3-100473.6" + attribute \src "libresoc.v:100516.3-100537.6" wire $1\dec31_dec_sub18_rsrv[0:0] - attribute \src "libresoc.v:100562.3-100583.6" + attribute \src "libresoc.v:100626.3-100647.6" wire $1\dec31_dec_sub18_sgl_pipe[0:0] - attribute \src "libresoc.v:100518.3-100539.6" + attribute \src "libresoc.v:100582.3-100603.6" wire $1\dec31_dec_sub18_sgn[0:0] - attribute \src "libresoc.v:100430.3-100451.6" + attribute \src "libresoc.v:100494.3-100515.6" wire $1\dec31_dec_sub18_sgn_ext[0:0] - attribute \src "libresoc.v:100166.3-100187.6" + attribute \src "libresoc.v:100230.3-100251.6" wire width 3 $1\dec31_dec_sub18_sv_cr_in[2:0] - attribute \src "libresoc.v:100188.3-100209.6" + attribute \src "libresoc.v:100252.3-100273.6" wire width 3 $1\dec31_dec_sub18_sv_cr_out[2:0] - attribute \src "libresoc.v:100056.3-100077.6" + attribute \src "libresoc.v:100120.3-100141.6" wire width 3 $1\dec31_dec_sub18_sv_in1[2:0] - attribute \src "libresoc.v:100078.3-100099.6" + attribute \src "libresoc.v:100142.3-100163.6" wire width 3 $1\dec31_dec_sub18_sv_in2[2:0] - attribute \src "libresoc.v:100100.3-100121.6" + attribute \src "libresoc.v:100164.3-100185.6" wire width 3 $1\dec31_dec_sub18_sv_in3[2:0] - attribute \src "libresoc.v:100144.3-100165.6" + attribute \src "libresoc.v:100208.3-100229.6" wire width 3 $1\dec31_dec_sub18_sv_out2[2:0] - attribute \src "libresoc.v:100122.3-100143.6" + attribute \src "libresoc.v:100186.3-100207.6" wire width 3 $1\dec31_dec_sub18_sv_out[2:0] - attribute \src "libresoc.v:100254.3-100275.6" + attribute \src "libresoc.v:100318.3-100339.6" wire width 2 $1\dec31_dec_sub18_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -155722,20 +155773,59 @@ module \dec31_dec_sub18 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub18_upd - attribute \src "libresoc.v:99642.7-99642.15" + attribute \src "libresoc.v:99706.7-99706.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:100012.3-100033.6" - process $proc$libresoc.v:100012$4022 + attribute \src "libresoc.v:100054.3-100075.6" + process $proc$libresoc.v:100054$4021 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_function_unit[13:0] $1\dec31_dec_sub18_function_unit[13:0] + attribute \src "libresoc.v:100055.5-100055.29" + switch \initial + attribute \src "libresoc.v:100055.9-100055.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + switch \opcode_switch + attribute \src "libresoc.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[13:0] 14'00000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[13:0] 14'00000010000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[13:0] 14'00100000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[13:0] 14'00100000000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[13:0] 14'00100000000000 + case + assign $1\dec31_dec_sub18_function_unit[13:0] 14'00000000000000 + end + sync always + update \dec31_dec_sub18_function_unit $0\dec31_dec_sub18_function_unit[13:0] + end + attribute \src "libresoc.v:100076.3-100097.6" + process $proc$libresoc.v:100076$4022 assign { } { } assign { } { } assign $0\dec31_dec_sub18_cr_in[2:0] $1\dec31_dec_sub18_cr_in[2:0] - attribute \src "libresoc.v:100013.5-100013.29" + attribute \src "libresoc.v:100077.5-100077.29" switch \initial - attribute \src "libresoc.v:100013.9-100013.17" + attribute \src "libresoc.v:100077.9-100077.17" case 1'1 case end @@ -155767,14 +155857,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_cr_in $0\dec31_dec_sub18_cr_in[2:0] end - attribute \src "libresoc.v:100034.3-100055.6" - process $proc$libresoc.v:100034$4023 + attribute \src "libresoc.v:100098.3-100119.6" + process $proc$libresoc.v:100098$4023 assign { } { } assign { } { } assign $0\dec31_dec_sub18_cr_out[2:0] $1\dec31_dec_sub18_cr_out[2:0] - attribute \src "libresoc.v:100035.5-100035.29" + attribute \src "libresoc.v:100099.5-100099.29" switch \initial - attribute \src "libresoc.v:100035.9-100035.17" + attribute \src "libresoc.v:100099.9-100099.17" case 1'1 case end @@ -155806,14 +155896,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_cr_out $0\dec31_dec_sub18_cr_out[2:0] end - attribute \src "libresoc.v:100056.3-100077.6" - process $proc$libresoc.v:100056$4024 + attribute \src "libresoc.v:100120.3-100141.6" + process $proc$libresoc.v:100120$4024 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sv_in1[2:0] $1\dec31_dec_sub18_sv_in1[2:0] - attribute \src "libresoc.v:100057.5-100057.29" + attribute \src "libresoc.v:100121.5-100121.29" switch \initial - attribute \src "libresoc.v:100057.9-100057.17" + attribute \src "libresoc.v:100121.9-100121.17" case 1'1 case end @@ -155845,14 +155935,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sv_in1 $0\dec31_dec_sub18_sv_in1[2:0] end - attribute \src "libresoc.v:100078.3-100099.6" - process $proc$libresoc.v:100078$4025 + attribute \src "libresoc.v:100142.3-100163.6" + process $proc$libresoc.v:100142$4025 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sv_in2[2:0] $1\dec31_dec_sub18_sv_in2[2:0] - attribute \src "libresoc.v:100079.5-100079.29" + attribute \src "libresoc.v:100143.5-100143.29" switch \initial - attribute \src "libresoc.v:100079.9-100079.17" + attribute \src "libresoc.v:100143.9-100143.17" case 1'1 case end @@ -155884,14 +155974,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sv_in2 $0\dec31_dec_sub18_sv_in2[2:0] end - attribute \src "libresoc.v:100100.3-100121.6" - process $proc$libresoc.v:100100$4026 + attribute \src "libresoc.v:100164.3-100185.6" + process $proc$libresoc.v:100164$4026 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sv_in3[2:0] $1\dec31_dec_sub18_sv_in3[2:0] - attribute \src "libresoc.v:100101.5-100101.29" + attribute \src "libresoc.v:100165.5-100165.29" switch \initial - attribute \src "libresoc.v:100101.9-100101.17" + attribute \src "libresoc.v:100165.9-100165.17" case 1'1 case end @@ -155923,14 +156013,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sv_in3 $0\dec31_dec_sub18_sv_in3[2:0] end - attribute \src "libresoc.v:100122.3-100143.6" - process $proc$libresoc.v:100122$4027 + attribute \src "libresoc.v:100186.3-100207.6" + process $proc$libresoc.v:100186$4027 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sv_out[2:0] $1\dec31_dec_sub18_sv_out[2:0] - attribute \src "libresoc.v:100123.5-100123.29" + attribute \src "libresoc.v:100187.5-100187.29" switch \initial - attribute \src "libresoc.v:100123.9-100123.17" + attribute \src "libresoc.v:100187.9-100187.17" case 1'1 case end @@ -155962,14 +156052,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sv_out $0\dec31_dec_sub18_sv_out[2:0] end - attribute \src "libresoc.v:100144.3-100165.6" - process $proc$libresoc.v:100144$4028 + attribute \src "libresoc.v:100208.3-100229.6" + process $proc$libresoc.v:100208$4028 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sv_out2[2:0] $1\dec31_dec_sub18_sv_out2[2:0] - attribute \src "libresoc.v:100145.5-100145.29" + attribute \src "libresoc.v:100209.5-100209.29" switch \initial - attribute \src "libresoc.v:100145.9-100145.17" + attribute \src "libresoc.v:100209.9-100209.17" case 1'1 case end @@ -156001,14 +156091,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sv_out2 $0\dec31_dec_sub18_sv_out2[2:0] end - attribute \src "libresoc.v:100166.3-100187.6" - process $proc$libresoc.v:100166$4029 + attribute \src "libresoc.v:100230.3-100251.6" + process $proc$libresoc.v:100230$4029 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sv_cr_in[2:0] $1\dec31_dec_sub18_sv_cr_in[2:0] - attribute \src "libresoc.v:100167.5-100167.29" + attribute \src "libresoc.v:100231.5-100231.29" switch \initial - attribute \src "libresoc.v:100167.9-100167.17" + attribute \src "libresoc.v:100231.9-100231.17" case 1'1 case end @@ -156040,14 +156130,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sv_cr_in $0\dec31_dec_sub18_sv_cr_in[2:0] end - attribute \src "libresoc.v:100188.3-100209.6" - process $proc$libresoc.v:100188$4030 + attribute \src "libresoc.v:100252.3-100273.6" + process $proc$libresoc.v:100252$4030 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sv_cr_out[2:0] $1\dec31_dec_sub18_sv_cr_out[2:0] - attribute \src "libresoc.v:100189.5-100189.29" + attribute \src "libresoc.v:100253.5-100253.29" switch \initial - attribute \src "libresoc.v:100189.9-100189.17" + attribute \src "libresoc.v:100253.9-100253.17" case 1'1 case end @@ -156079,14 +156169,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sv_cr_out $0\dec31_dec_sub18_sv_cr_out[2:0] end - attribute \src "libresoc.v:100210.3-100231.6" - process $proc$libresoc.v:100210$4031 + attribute \src "libresoc.v:100274.3-100295.6" + process $proc$libresoc.v:100274$4031 assign { } { } assign { } { } assign $0\dec31_dec_sub18_ldst_len[3:0] $1\dec31_dec_sub18_ldst_len[3:0] - attribute \src "libresoc.v:100211.5-100211.29" + attribute \src "libresoc.v:100275.5-100275.29" switch \initial - attribute \src "libresoc.v:100211.9-100211.17" + attribute \src "libresoc.v:100275.9-100275.17" case 1'1 case end @@ -156118,14 +156208,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_ldst_len $0\dec31_dec_sub18_ldst_len[3:0] end - attribute \src "libresoc.v:100232.3-100253.6" - process $proc$libresoc.v:100232$4032 + attribute \src "libresoc.v:100296.3-100317.6" + process $proc$libresoc.v:100296$4032 assign { } { } assign { } { } assign $0\dec31_dec_sub18_internal_op[6:0] $1\dec31_dec_sub18_internal_op[6:0] - attribute \src "libresoc.v:100233.5-100233.29" + attribute \src "libresoc.v:100297.5-100297.29" switch \initial - attribute \src "libresoc.v:100233.9-100233.17" + attribute \src "libresoc.v:100297.9-100297.17" case 1'1 case end @@ -156157,14 +156247,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_internal_op $0\dec31_dec_sub18_internal_op[6:0] end - attribute \src "libresoc.v:100254.3-100275.6" - process $proc$libresoc.v:100254$4033 + attribute \src "libresoc.v:100318.3-100339.6" + process $proc$libresoc.v:100318$4033 assign { } { } assign { } { } assign $0\dec31_dec_sub18_upd[1:0] $1\dec31_dec_sub18_upd[1:0] - attribute \src "libresoc.v:100255.5-100255.29" + attribute \src "libresoc.v:100319.5-100319.29" switch \initial - attribute \src "libresoc.v:100255.9-100255.17" + attribute \src "libresoc.v:100319.9-100319.17" case 1'1 case end @@ -156196,14 +156286,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_upd $0\dec31_dec_sub18_upd[1:0] end - attribute \src "libresoc.v:100276.3-100297.6" - process $proc$libresoc.v:100276$4034 + attribute \src "libresoc.v:100340.3-100361.6" + process $proc$libresoc.v:100340$4034 assign { } { } assign { } { } assign $0\dec31_dec_sub18_rc_sel[1:0] $1\dec31_dec_sub18_rc_sel[1:0] - attribute \src "libresoc.v:100277.5-100277.29" + attribute \src "libresoc.v:100341.5-100341.29" switch \initial - attribute \src "libresoc.v:100277.9-100277.17" + attribute \src "libresoc.v:100341.9-100341.17" case 1'1 case end @@ -156235,14 +156325,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_rc_sel $0\dec31_dec_sub18_rc_sel[1:0] end - attribute \src "libresoc.v:100298.3-100319.6" - process $proc$libresoc.v:100298$4035 + attribute \src "libresoc.v:100362.3-100383.6" + process $proc$libresoc.v:100362$4035 assign { } { } assign { } { } assign $0\dec31_dec_sub18_cry_in[1:0] $1\dec31_dec_sub18_cry_in[1:0] - attribute \src "libresoc.v:100299.5-100299.29" + attribute \src "libresoc.v:100363.5-100363.29" switch \initial - attribute \src "libresoc.v:100299.9-100299.17" + attribute \src "libresoc.v:100363.9-100363.17" case 1'1 case end @@ -156274,14 +156364,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_cry_in $0\dec31_dec_sub18_cry_in[1:0] end - attribute \src "libresoc.v:100320.3-100341.6" - process $proc$libresoc.v:100320$4036 + attribute \src "libresoc.v:100384.3-100405.6" + process $proc$libresoc.v:100384$4036 assign { } { } assign { } { } assign $0\dec31_dec_sub18_asmcode[7:0] $1\dec31_dec_sub18_asmcode[7:0] - attribute \src "libresoc.v:100321.5-100321.29" + attribute \src "libresoc.v:100385.5-100385.29" switch \initial - attribute \src "libresoc.v:100321.9-100321.17" + attribute \src "libresoc.v:100385.9-100385.17" case 1'1 case end @@ -156313,14 +156403,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_asmcode $0\dec31_dec_sub18_asmcode[7:0] end - attribute \src "libresoc.v:100342.3-100363.6" - process $proc$libresoc.v:100342$4037 + attribute \src "libresoc.v:100406.3-100427.6" + process $proc$libresoc.v:100406$4037 assign { } { } assign { } { } assign $0\dec31_dec_sub18_inv_a[0:0] $1\dec31_dec_sub18_inv_a[0:0] - attribute \src "libresoc.v:100343.5-100343.29" + attribute \src "libresoc.v:100407.5-100407.29" switch \initial - attribute \src "libresoc.v:100343.9-100343.17" + attribute \src "libresoc.v:100407.9-100407.17" case 1'1 case end @@ -156352,14 +156442,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_inv_a $0\dec31_dec_sub18_inv_a[0:0] end - attribute \src "libresoc.v:100364.3-100385.6" - process $proc$libresoc.v:100364$4038 + attribute \src "libresoc.v:100428.3-100449.6" + process $proc$libresoc.v:100428$4038 assign { } { } assign { } { } assign $0\dec31_dec_sub18_inv_out[0:0] $1\dec31_dec_sub18_inv_out[0:0] - attribute \src "libresoc.v:100365.5-100365.29" + attribute \src "libresoc.v:100429.5-100429.29" switch \initial - attribute \src "libresoc.v:100365.9-100365.17" + attribute \src "libresoc.v:100429.9-100429.17" case 1'1 case end @@ -156391,14 +156481,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_inv_out $0\dec31_dec_sub18_inv_out[0:0] end - attribute \src "libresoc.v:100386.3-100407.6" - process $proc$libresoc.v:100386$4039 + attribute \src "libresoc.v:100450.3-100471.6" + process $proc$libresoc.v:100450$4039 assign { } { } assign { } { } assign $0\dec31_dec_sub18_cry_out[0:0] $1\dec31_dec_sub18_cry_out[0:0] - attribute \src "libresoc.v:100387.5-100387.29" + attribute \src "libresoc.v:100451.5-100451.29" switch \initial - attribute \src "libresoc.v:100387.9-100387.17" + attribute \src "libresoc.v:100451.9-100451.17" case 1'1 case end @@ -156430,14 +156520,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_cry_out $0\dec31_dec_sub18_cry_out[0:0] end - attribute \src "libresoc.v:100408.3-100429.6" - process $proc$libresoc.v:100408$4040 + attribute \src "libresoc.v:100472.3-100493.6" + process $proc$libresoc.v:100472$4040 assign { } { } assign { } { } assign $0\dec31_dec_sub18_br[0:0] $1\dec31_dec_sub18_br[0:0] - attribute \src "libresoc.v:100409.5-100409.29" + attribute \src "libresoc.v:100473.5-100473.29" switch \initial - attribute \src "libresoc.v:100409.9-100409.17" + attribute \src "libresoc.v:100473.9-100473.17" case 1'1 case end @@ -156469,14 +156559,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_br $0\dec31_dec_sub18_br[0:0] end - attribute \src "libresoc.v:100430.3-100451.6" - process $proc$libresoc.v:100430$4041 + attribute \src "libresoc.v:100494.3-100515.6" + process $proc$libresoc.v:100494$4041 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sgn_ext[0:0] $1\dec31_dec_sub18_sgn_ext[0:0] - attribute \src "libresoc.v:100431.5-100431.29" + attribute \src "libresoc.v:100495.5-100495.29" switch \initial - attribute \src "libresoc.v:100431.9-100431.17" + attribute \src "libresoc.v:100495.9-100495.17" case 1'1 case end @@ -156508,14 +156598,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sgn_ext $0\dec31_dec_sub18_sgn_ext[0:0] end - attribute \src "libresoc.v:100452.3-100473.6" - process $proc$libresoc.v:100452$4042 + attribute \src "libresoc.v:100516.3-100537.6" + process $proc$libresoc.v:100516$4042 assign { } { } assign { } { } assign $0\dec31_dec_sub18_rsrv[0:0] $1\dec31_dec_sub18_rsrv[0:0] - attribute \src "libresoc.v:100453.5-100453.29" + attribute \src "libresoc.v:100517.5-100517.29" switch \initial - attribute \src "libresoc.v:100453.9-100453.17" + attribute \src "libresoc.v:100517.9-100517.17" case 1'1 case end @@ -156547,14 +156637,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_rsrv $0\dec31_dec_sub18_rsrv[0:0] end - attribute \src "libresoc.v:100474.3-100495.6" - process $proc$libresoc.v:100474$4043 + attribute \src "libresoc.v:100538.3-100559.6" + process $proc$libresoc.v:100538$4043 assign { } { } assign { } { } assign $0\dec31_dec_sub18_form[4:0] $1\dec31_dec_sub18_form[4:0] - attribute \src "libresoc.v:100475.5-100475.29" + attribute \src "libresoc.v:100539.5-100539.29" switch \initial - attribute \src "libresoc.v:100475.9-100475.17" + attribute \src "libresoc.v:100539.9-100539.17" case 1'1 case end @@ -156586,14 +156676,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_form $0\dec31_dec_sub18_form[4:0] end - attribute \src "libresoc.v:100496.3-100517.6" - process $proc$libresoc.v:100496$4044 + attribute \src "libresoc.v:100560.3-100581.6" + process $proc$libresoc.v:100560$4044 assign { } { } assign { } { } assign $0\dec31_dec_sub18_is_32b[0:0] $1\dec31_dec_sub18_is_32b[0:0] - attribute \src "libresoc.v:100497.5-100497.29" + attribute \src "libresoc.v:100561.5-100561.29" switch \initial - attribute \src "libresoc.v:100497.9-100497.17" + attribute \src "libresoc.v:100561.9-100561.17" case 1'1 case end @@ -156625,14 +156715,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_is_32b $0\dec31_dec_sub18_is_32b[0:0] end - attribute \src "libresoc.v:100518.3-100539.6" - process $proc$libresoc.v:100518$4045 + attribute \src "libresoc.v:100582.3-100603.6" + process $proc$libresoc.v:100582$4045 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sgn[0:0] $1\dec31_dec_sub18_sgn[0:0] - attribute \src "libresoc.v:100519.5-100519.29" + attribute \src "libresoc.v:100583.5-100583.29" switch \initial - attribute \src "libresoc.v:100519.9-100519.17" + attribute \src "libresoc.v:100583.9-100583.17" case 1'1 case end @@ -156664,14 +156754,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sgn $0\dec31_dec_sub18_sgn[0:0] end - attribute \src "libresoc.v:100540.3-100561.6" - process $proc$libresoc.v:100540$4046 + attribute \src "libresoc.v:100604.3-100625.6" + process $proc$libresoc.v:100604$4046 assign { } { } assign { } { } assign $0\dec31_dec_sub18_lk[0:0] $1\dec31_dec_sub18_lk[0:0] - attribute \src "libresoc.v:100541.5-100541.29" + attribute \src "libresoc.v:100605.5-100605.29" switch \initial - attribute \src "libresoc.v:100541.9-100541.17" + attribute \src "libresoc.v:100605.9-100605.17" case 1'1 case end @@ -156703,14 +156793,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_lk $0\dec31_dec_sub18_lk[0:0] end - attribute \src "libresoc.v:100562.3-100583.6" - process $proc$libresoc.v:100562$4047 + attribute \src "libresoc.v:100626.3-100647.6" + process $proc$libresoc.v:100626$4047 assign { } { } assign { } { } assign $0\dec31_dec_sub18_sgl_pipe[0:0] $1\dec31_dec_sub18_sgl_pipe[0:0] - attribute \src "libresoc.v:100563.5-100563.29" + attribute \src "libresoc.v:100627.5-100627.29" switch \initial - attribute \src "libresoc.v:100563.9-100563.17" + attribute \src "libresoc.v:100627.9-100627.17" case 1'1 case end @@ -156742,14 +156832,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_sgl_pipe $0\dec31_dec_sub18_sgl_pipe[0:0] end - attribute \src "libresoc.v:100584.3-100605.6" - process $proc$libresoc.v:100584$4048 + attribute \src "libresoc.v:100648.3-100669.6" + process $proc$libresoc.v:100648$4048 assign { } { } assign { } { } assign $0\dec31_dec_sub18_SV_Etype[1:0] $1\dec31_dec_sub18_SV_Etype[1:0] - attribute \src "libresoc.v:100585.5-100585.29" + attribute \src "libresoc.v:100649.5-100649.29" switch \initial - attribute \src "libresoc.v:100585.9-100585.17" + attribute \src "libresoc.v:100649.9-100649.17" case 1'1 case end @@ -156781,14 +156871,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_SV_Etype $0\dec31_dec_sub18_SV_Etype[1:0] end - attribute \src "libresoc.v:100606.3-100627.6" - process $proc$libresoc.v:100606$4049 + attribute \src "libresoc.v:100670.3-100691.6" + process $proc$libresoc.v:100670$4049 assign { } { } assign { } { } assign $0\dec31_dec_sub18_SV_Ptype[1:0] $1\dec31_dec_sub18_SV_Ptype[1:0] - attribute \src "libresoc.v:100607.5-100607.29" + attribute \src "libresoc.v:100671.5-100671.29" switch \initial - attribute \src "libresoc.v:100607.9-100607.17" + attribute \src "libresoc.v:100671.9-100671.17" case 1'1 case end @@ -156820,14 +156910,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_SV_Ptype $0\dec31_dec_sub18_SV_Ptype[1:0] end - attribute \src "libresoc.v:100628.3-100649.6" - process $proc$libresoc.v:100628$4050 + attribute \src "libresoc.v:100692.3-100713.6" + process $proc$libresoc.v:100692$4050 assign { } { } assign { } { } assign $0\dec31_dec_sub18_in1_sel[2:0] $1\dec31_dec_sub18_in1_sel[2:0] - attribute \src "libresoc.v:100629.5-100629.29" + attribute \src "libresoc.v:100693.5-100693.29" switch \initial - attribute \src "libresoc.v:100629.9-100629.17" + attribute \src "libresoc.v:100693.9-100693.17" case 1'1 case end @@ -156859,14 +156949,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_in1_sel $0\dec31_dec_sub18_in1_sel[2:0] end - attribute \src "libresoc.v:100650.3-100671.6" - process $proc$libresoc.v:100650$4051 + attribute \src "libresoc.v:100714.3-100735.6" + process $proc$libresoc.v:100714$4051 assign { } { } assign { } { } assign $0\dec31_dec_sub18_in2_sel[3:0] $1\dec31_dec_sub18_in2_sel[3:0] - attribute \src "libresoc.v:100651.5-100651.29" + attribute \src "libresoc.v:100715.5-100715.29" switch \initial - attribute \src "libresoc.v:100651.9-100651.17" + attribute \src "libresoc.v:100715.9-100715.17" case 1'1 case end @@ -156898,14 +156988,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_in2_sel $0\dec31_dec_sub18_in2_sel[3:0] end - attribute \src "libresoc.v:100672.3-100693.6" - process $proc$libresoc.v:100672$4052 + attribute \src "libresoc.v:100736.3-100757.6" + process $proc$libresoc.v:100736$4052 assign { } { } assign { } { } assign $0\dec31_dec_sub18_in3_sel[1:0] $1\dec31_dec_sub18_in3_sel[1:0] - attribute \src "libresoc.v:100673.5-100673.29" + attribute \src "libresoc.v:100737.5-100737.29" switch \initial - attribute \src "libresoc.v:100673.9-100673.17" + attribute \src "libresoc.v:100737.9-100737.17" case 1'1 case end @@ -156937,14 +157027,14 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_in3_sel $0\dec31_dec_sub18_in3_sel[1:0] end - attribute \src "libresoc.v:100694.3-100715.6" - process $proc$libresoc.v:100694$4053 + attribute \src "libresoc.v:100758.3-100779.6" + process $proc$libresoc.v:100758$4053 assign { } { } assign { } { } assign $0\dec31_dec_sub18_out_sel[2:0] $1\dec31_dec_sub18_out_sel[2:0] - attribute \src "libresoc.v:100695.5-100695.29" + attribute \src "libresoc.v:100759.5-100759.29" switch \initial - attribute \src "libresoc.v:100695.9-100695.17" + attribute \src "libresoc.v:100759.9-100759.17" case 1'1 case end @@ -156976,193 +157066,154 @@ module \dec31_dec_sub18 sync always update \dec31_dec_sub18_out_sel $0\dec31_dec_sub18_out_sel[2:0] end - attribute \src "libresoc.v:99642.7-99642.20" - process $proc$libresoc.v:99642$4054 + attribute \src "libresoc.v:99706.7-99706.20" + process $proc$libresoc.v:99706$4054 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:99990.3-100011.6" - process $proc$libresoc.v:99990$4021 - assign { } { } - assign { } { } - assign $0\dec31_dec_sub18_function_unit[13:0] $1\dec31_dec_sub18_function_unit[13:0] - attribute \src "libresoc.v:99991.5-99991.29" - switch \initial - attribute \src "libresoc.v:99991.9-99991.17" - case 1'1 - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" - switch \opcode_switch - attribute \src "libresoc.v:0.0-0.0" - case 5'00101 - assign { } { } - assign $1\dec31_dec_sub18_function_unit[13:0] 14'00000010000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'00100 - assign { } { } - assign $1\dec31_dec_sub18_function_unit[13:0] 14'00000010000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01111 - assign { } { } - assign $1\dec31_dec_sub18_function_unit[13:0] 14'00100000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01001 - assign { } { } - assign $1\dec31_dec_sub18_function_unit[13:0] 14'00100000000000 - attribute \src "libresoc.v:0.0-0.0" - case 5'01000 - assign { } { } - assign $1\dec31_dec_sub18_function_unit[13:0] 14'00100000000000 - case - assign $1\dec31_dec_sub18_function_unit[13:0] 14'00000000000000 - end - sync always - update \dec31_dec_sub18_function_unit $0\dec31_dec_sub18_function_unit[13:0] - end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:100721.1-101698.10" +attribute \src "libresoc.v:100785.1-101762.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub19" attribute \generator "nMigen" module \dec31_dec_sub19 - attribute \src "libresoc.v:101583.3-101601.6" + attribute \src "libresoc.v:101647.3-101665.6" wire width 2 $0\dec31_dec_sub19_SV_Etype[1:0] - attribute \src "libresoc.v:101602.3-101620.6" + attribute \src "libresoc.v:101666.3-101684.6" wire width 2 $0\dec31_dec_sub19_SV_Ptype[1:0] - attribute \src "libresoc.v:101355.3-101373.6" + attribute \src "libresoc.v:101419.3-101437.6" wire width 8 $0\dec31_dec_sub19_asmcode[7:0] - attribute \src "libresoc.v:101431.3-101449.6" + attribute \src "libresoc.v:101495.3-101513.6" wire $0\dec31_dec_sub19_br[0:0] - attribute \src "libresoc.v:101089.3-101107.6" + attribute \src "libresoc.v:101153.3-101171.6" wire width 3 $0\dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:101108.3-101126.6" + attribute \src "libresoc.v:101172.3-101190.6" wire width 3 $0\dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:101336.3-101354.6" + attribute \src "libresoc.v:101400.3-101418.6" wire width 2 $0\dec31_dec_sub19_cry_in[1:0] - attribute \src "libresoc.v:101412.3-101430.6" + attribute \src "libresoc.v:101476.3-101494.6" wire $0\dec31_dec_sub19_cry_out[0:0] - attribute \src "libresoc.v:101488.3-101506.6" + attribute \src "libresoc.v:101552.3-101570.6" wire width 5 $0\dec31_dec_sub19_form[4:0] - attribute \src "libresoc.v:101070.3-101088.6" + attribute \src "libresoc.v:101134.3-101152.6" wire width 14 $0\dec31_dec_sub19_function_unit[13:0] - attribute \src "libresoc.v:101621.3-101639.6" + attribute \src "libresoc.v:101685.3-101703.6" wire width 3 $0\dec31_dec_sub19_in1_sel[2:0] - attribute \src "libresoc.v:101640.3-101658.6" + attribute \src "libresoc.v:101704.3-101722.6" wire width 4 $0\dec31_dec_sub19_in2_sel[3:0] - attribute \src "libresoc.v:101659.3-101677.6" + attribute \src "libresoc.v:101723.3-101741.6" wire width 2 $0\dec31_dec_sub19_in3_sel[1:0] - attribute \src "libresoc.v:101279.3-101297.6" + attribute \src "libresoc.v:101343.3-101361.6" wire width 7 $0\dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:101374.3-101392.6" + attribute \src "libresoc.v:101438.3-101456.6" wire $0\dec31_dec_sub19_inv_a[0:0] - attribute \src "libresoc.v:101393.3-101411.6" + attribute \src "libresoc.v:101457.3-101475.6" wire $0\dec31_dec_sub19_inv_out[0:0] - attribute \src "libresoc.v:101507.3-101525.6" + attribute \src "libresoc.v:101571.3-101589.6" wire $0\dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:101260.3-101278.6" + attribute \src "libresoc.v:101324.3-101342.6" wire width 4 $0\dec31_dec_sub19_ldst_len[3:0] - attribute \src "libresoc.v:101545.3-101563.6" + attribute \src "libresoc.v:101609.3-101627.6" wire $0\dec31_dec_sub19_lk[0:0] - attribute \src "libresoc.v:101678.3-101696.6" + attribute \src "libresoc.v:101742.3-101760.6" wire width 3 $0\dec31_dec_sub19_out_sel[2:0] - attribute \src "libresoc.v:101317.3-101335.6" + attribute \src "libresoc.v:101381.3-101399.6" wire width 2 $0\dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:101469.3-101487.6" + attribute \src "libresoc.v:101533.3-101551.6" wire $0\dec31_dec_sub19_rsrv[0:0] - attribute \src "libresoc.v:101564.3-101582.6" + attribute \src "libresoc.v:101628.3-101646.6" wire $0\dec31_dec_sub19_sgl_pipe[0:0] - attribute \src "libresoc.v:101526.3-101544.6" + attribute \src "libresoc.v:101590.3-101608.6" wire $0\dec31_dec_sub19_sgn[0:0] - attribute \src "libresoc.v:101450.3-101468.6" + attribute \src "libresoc.v:101514.3-101532.6" wire $0\dec31_dec_sub19_sgn_ext[0:0] - attribute \src "libresoc.v:101222.3-101240.6" + attribute \src "libresoc.v:101286.3-101304.6" wire width 3 $0\dec31_dec_sub19_sv_cr_in[2:0] - attribute \src "libresoc.v:101241.3-101259.6" + attribute \src "libresoc.v:101305.3-101323.6" wire width 3 $0\dec31_dec_sub19_sv_cr_out[2:0] - attribute \src "libresoc.v:101127.3-101145.6" + attribute \src "libresoc.v:101191.3-101209.6" wire width 3 $0\dec31_dec_sub19_sv_in1[2:0] - attribute \src "libresoc.v:101146.3-101164.6" + attribute \src "libresoc.v:101210.3-101228.6" wire width 3 $0\dec31_dec_sub19_sv_in2[2:0] - attribute \src "libresoc.v:101165.3-101183.6" + attribute \src "libresoc.v:101229.3-101247.6" wire width 3 $0\dec31_dec_sub19_sv_in3[2:0] - attribute \src "libresoc.v:101203.3-101221.6" + attribute \src "libresoc.v:101267.3-101285.6" wire width 3 $0\dec31_dec_sub19_sv_out2[2:0] - attribute \src "libresoc.v:101184.3-101202.6" + attribute \src "libresoc.v:101248.3-101266.6" wire width 3 $0\dec31_dec_sub19_sv_out[2:0] - attribute \src "libresoc.v:101298.3-101316.6" + attribute \src "libresoc.v:101362.3-101380.6" wire width 2 $0\dec31_dec_sub19_upd[1:0] - attribute \src "libresoc.v:100722.7-100722.20" + attribute \src "libresoc.v:100786.7-100786.20" wire $0\initial[0:0] - attribute \src "libresoc.v:101583.3-101601.6" + attribute \src "libresoc.v:101647.3-101665.6" wire width 2 $1\dec31_dec_sub19_SV_Etype[1:0] - attribute \src "libresoc.v:101602.3-101620.6" + attribute \src "libresoc.v:101666.3-101684.6" wire width 2 $1\dec31_dec_sub19_SV_Ptype[1:0] - attribute \src "libresoc.v:101355.3-101373.6" + attribute \src "libresoc.v:101419.3-101437.6" wire width 8 $1\dec31_dec_sub19_asmcode[7:0] - attribute \src "libresoc.v:101431.3-101449.6" + attribute \src "libresoc.v:101495.3-101513.6" wire $1\dec31_dec_sub19_br[0:0] - attribute \src "libresoc.v:101089.3-101107.6" + attribute \src "libresoc.v:101153.3-101171.6" wire width 3 $1\dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:101108.3-101126.6" + attribute \src "libresoc.v:101172.3-101190.6" wire width 3 $1\dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:101336.3-101354.6" + attribute \src "libresoc.v:101400.3-101418.6" wire width 2 $1\dec31_dec_sub19_cry_in[1:0] - attribute \src "libresoc.v:101412.3-101430.6" + attribute \src "libresoc.v:101476.3-101494.6" wire $1\dec31_dec_sub19_cry_out[0:0] - attribute \src "libresoc.v:101488.3-101506.6" + attribute \src "libresoc.v:101552.3-101570.6" wire width 5 $1\dec31_dec_sub19_form[4:0] - attribute \src "libresoc.v:101070.3-101088.6" + attribute \src "libresoc.v:101134.3-101152.6" wire width 14 $1\dec31_dec_sub19_function_unit[13:0] - attribute \src "libresoc.v:101621.3-101639.6" + attribute \src "libresoc.v:101685.3-101703.6" wire width 3 $1\dec31_dec_sub19_in1_sel[2:0] - attribute \src "libresoc.v:101640.3-101658.6" + attribute \src "libresoc.v:101704.3-101722.6" wire width 4 $1\dec31_dec_sub19_in2_sel[3:0] - attribute \src "libresoc.v:101659.3-101677.6" + attribute \src "libresoc.v:101723.3-101741.6" wire width 2 $1\dec31_dec_sub19_in3_sel[1:0] - attribute \src "libresoc.v:101279.3-101297.6" + attribute \src "libresoc.v:101343.3-101361.6" wire width 7 $1\dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:101374.3-101392.6" + attribute \src "libresoc.v:101438.3-101456.6" wire $1\dec31_dec_sub19_inv_a[0:0] - attribute \src "libresoc.v:101393.3-101411.6" + attribute \src "libresoc.v:101457.3-101475.6" wire $1\dec31_dec_sub19_inv_out[0:0] - attribute \src "libresoc.v:101507.3-101525.6" + attribute \src "libresoc.v:101571.3-101589.6" wire $1\dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:101260.3-101278.6" + attribute \src "libresoc.v:101324.3-101342.6" wire width 4 $1\dec31_dec_sub19_ldst_len[3:0] - attribute \src "libresoc.v:101545.3-101563.6" + attribute \src "libresoc.v:101609.3-101627.6" wire $1\dec31_dec_sub19_lk[0:0] - attribute \src "libresoc.v:101678.3-101696.6" + attribute \src "libresoc.v:101742.3-101760.6" wire width 3 $1\dec31_dec_sub19_out_sel[2:0] - attribute \src "libresoc.v:101317.3-101335.6" + attribute \src "libresoc.v:101381.3-101399.6" wire width 2 $1\dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:101469.3-101487.6" + attribute \src "libresoc.v:101533.3-101551.6" wire $1\dec31_dec_sub19_rsrv[0:0] - attribute \src "libresoc.v:101564.3-101582.6" + attribute \src "libresoc.v:101628.3-101646.6" wire $1\dec31_dec_sub19_sgl_pipe[0:0] - attribute \src "libresoc.v:101526.3-101544.6" + attribute \src "libresoc.v:101590.3-101608.6" wire $1\dec31_dec_sub19_sgn[0:0] - attribute \src "libresoc.v:101450.3-101468.6" + attribute \src "libresoc.v:101514.3-101532.6" wire $1\dec31_dec_sub19_sgn_ext[0:0] - attribute \src "libresoc.v:101222.3-101240.6" + attribute \src "libresoc.v:101286.3-101304.6" wire width 3 $1\dec31_dec_sub19_sv_cr_in[2:0] - attribute \src "libresoc.v:101241.3-101259.6" + attribute \src "libresoc.v:101305.3-101323.6" wire width 3 $1\dec31_dec_sub19_sv_cr_out[2:0] - attribute \src "libresoc.v:101127.3-101145.6" + attribute \src "libresoc.v:101191.3-101209.6" wire width 3 $1\dec31_dec_sub19_sv_in1[2:0] - attribute \src "libresoc.v:101146.3-101164.6" + attribute \src "libresoc.v:101210.3-101228.6" wire width 3 $1\dec31_dec_sub19_sv_in2[2:0] - attribute \src "libresoc.v:101165.3-101183.6" + attribute \src "libresoc.v:101229.3-101247.6" wire width 3 $1\dec31_dec_sub19_sv_in3[2:0] - attribute \src "libresoc.v:101203.3-101221.6" + attribute \src "libresoc.v:101267.3-101285.6" wire width 3 $1\dec31_dec_sub19_sv_out2[2:0] - attribute \src "libresoc.v:101184.3-101202.6" + attribute \src "libresoc.v:101248.3-101266.6" wire width 3 $1\dec31_dec_sub19_sv_out[2:0] - attribute \src "libresoc.v:101298.3-101316.6" + attribute \src "libresoc.v:101362.3-101380.6" wire width 2 $1\dec31_dec_sub19_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -157474,28 +157525,28 @@ module \dec31_dec_sub19 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub19_upd - attribute \src "libresoc.v:100722.7-100722.15" + attribute \src "libresoc.v:100786.7-100786.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:100722.7-100722.20" - process $proc$libresoc.v:100722$4088 + attribute \src "libresoc.v:100786.7-100786.20" + process $proc$libresoc.v:100786$4088 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:101070.3-101088.6" - process $proc$libresoc.v:101070$4055 + attribute \src "libresoc.v:101134.3-101152.6" + process $proc$libresoc.v:101134$4055 assign { } { } assign { } { } assign $0\dec31_dec_sub19_function_unit[13:0] $1\dec31_dec_sub19_function_unit[13:0] - attribute \src "libresoc.v:101071.5-101071.29" + attribute \src "libresoc.v:101135.5-101135.29" switch \initial - attribute \src "libresoc.v:101071.9-101071.17" + attribute \src "libresoc.v:101135.9-101135.17" case 1'1 case end @@ -157523,14 +157574,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_function_unit $0\dec31_dec_sub19_function_unit[13:0] end - attribute \src "libresoc.v:101089.3-101107.6" - process $proc$libresoc.v:101089$4056 + attribute \src "libresoc.v:101153.3-101171.6" + process $proc$libresoc.v:101153$4056 assign { } { } assign { } { } assign $0\dec31_dec_sub19_cr_in[2:0] $1\dec31_dec_sub19_cr_in[2:0] - attribute \src "libresoc.v:101090.5-101090.29" + attribute \src "libresoc.v:101154.5-101154.29" switch \initial - attribute \src "libresoc.v:101090.9-101090.17" + attribute \src "libresoc.v:101154.9-101154.17" case 1'1 case end @@ -157558,14 +157609,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_cr_in $0\dec31_dec_sub19_cr_in[2:0] end - attribute \src "libresoc.v:101108.3-101126.6" - process $proc$libresoc.v:101108$4057 + attribute \src "libresoc.v:101172.3-101190.6" + process $proc$libresoc.v:101172$4057 assign { } { } assign { } { } assign $0\dec31_dec_sub19_cr_out[2:0] $1\dec31_dec_sub19_cr_out[2:0] - attribute \src "libresoc.v:101109.5-101109.29" + attribute \src "libresoc.v:101173.5-101173.29" switch \initial - attribute \src "libresoc.v:101109.9-101109.17" + attribute \src "libresoc.v:101173.9-101173.17" case 1'1 case end @@ -157593,14 +157644,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_cr_out $0\dec31_dec_sub19_cr_out[2:0] end - attribute \src "libresoc.v:101127.3-101145.6" - process $proc$libresoc.v:101127$4058 + attribute \src "libresoc.v:101191.3-101209.6" + process $proc$libresoc.v:101191$4058 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_in1[2:0] $1\dec31_dec_sub19_sv_in1[2:0] - attribute \src "libresoc.v:101128.5-101128.29" + attribute \src "libresoc.v:101192.5-101192.29" switch \initial - attribute \src "libresoc.v:101128.9-101128.17" + attribute \src "libresoc.v:101192.9-101192.17" case 1'1 case end @@ -157628,14 +157679,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sv_in1 $0\dec31_dec_sub19_sv_in1[2:0] end - attribute \src "libresoc.v:101146.3-101164.6" - process $proc$libresoc.v:101146$4059 + attribute \src "libresoc.v:101210.3-101228.6" + process $proc$libresoc.v:101210$4059 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_in2[2:0] $1\dec31_dec_sub19_sv_in2[2:0] - attribute \src "libresoc.v:101147.5-101147.29" + attribute \src "libresoc.v:101211.5-101211.29" switch \initial - attribute \src "libresoc.v:101147.9-101147.17" + attribute \src "libresoc.v:101211.9-101211.17" case 1'1 case end @@ -157663,14 +157714,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sv_in2 $0\dec31_dec_sub19_sv_in2[2:0] end - attribute \src "libresoc.v:101165.3-101183.6" - process $proc$libresoc.v:101165$4060 + attribute \src "libresoc.v:101229.3-101247.6" + process $proc$libresoc.v:101229$4060 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_in3[2:0] $1\dec31_dec_sub19_sv_in3[2:0] - attribute \src "libresoc.v:101166.5-101166.29" + attribute \src "libresoc.v:101230.5-101230.29" switch \initial - attribute \src "libresoc.v:101166.9-101166.17" + attribute \src "libresoc.v:101230.9-101230.17" case 1'1 case end @@ -157698,14 +157749,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sv_in3 $0\dec31_dec_sub19_sv_in3[2:0] end - attribute \src "libresoc.v:101184.3-101202.6" - process $proc$libresoc.v:101184$4061 + attribute \src "libresoc.v:101248.3-101266.6" + process $proc$libresoc.v:101248$4061 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_out[2:0] $1\dec31_dec_sub19_sv_out[2:0] - attribute \src "libresoc.v:101185.5-101185.29" + attribute \src "libresoc.v:101249.5-101249.29" switch \initial - attribute \src "libresoc.v:101185.9-101185.17" + attribute \src "libresoc.v:101249.9-101249.17" case 1'1 case end @@ -157733,14 +157784,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sv_out $0\dec31_dec_sub19_sv_out[2:0] end - attribute \src "libresoc.v:101203.3-101221.6" - process $proc$libresoc.v:101203$4062 + attribute \src "libresoc.v:101267.3-101285.6" + process $proc$libresoc.v:101267$4062 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_out2[2:0] $1\dec31_dec_sub19_sv_out2[2:0] - attribute \src "libresoc.v:101204.5-101204.29" + attribute \src "libresoc.v:101268.5-101268.29" switch \initial - attribute \src "libresoc.v:101204.9-101204.17" + attribute \src "libresoc.v:101268.9-101268.17" case 1'1 case end @@ -157768,14 +157819,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sv_out2 $0\dec31_dec_sub19_sv_out2[2:0] end - attribute \src "libresoc.v:101222.3-101240.6" - process $proc$libresoc.v:101222$4063 + attribute \src "libresoc.v:101286.3-101304.6" + process $proc$libresoc.v:101286$4063 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_cr_in[2:0] $1\dec31_dec_sub19_sv_cr_in[2:0] - attribute \src "libresoc.v:101223.5-101223.29" + attribute \src "libresoc.v:101287.5-101287.29" switch \initial - attribute \src "libresoc.v:101223.9-101223.17" + attribute \src "libresoc.v:101287.9-101287.17" case 1'1 case end @@ -157803,14 +157854,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sv_cr_in $0\dec31_dec_sub19_sv_cr_in[2:0] end - attribute \src "libresoc.v:101241.3-101259.6" - process $proc$libresoc.v:101241$4064 + attribute \src "libresoc.v:101305.3-101323.6" + process $proc$libresoc.v:101305$4064 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sv_cr_out[2:0] $1\dec31_dec_sub19_sv_cr_out[2:0] - attribute \src "libresoc.v:101242.5-101242.29" + attribute \src "libresoc.v:101306.5-101306.29" switch \initial - attribute \src "libresoc.v:101242.9-101242.17" + attribute \src "libresoc.v:101306.9-101306.17" case 1'1 case end @@ -157838,14 +157889,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sv_cr_out $0\dec31_dec_sub19_sv_cr_out[2:0] end - attribute \src "libresoc.v:101260.3-101278.6" - process $proc$libresoc.v:101260$4065 + attribute \src "libresoc.v:101324.3-101342.6" + process $proc$libresoc.v:101324$4065 assign { } { } assign { } { } assign $0\dec31_dec_sub19_ldst_len[3:0] $1\dec31_dec_sub19_ldst_len[3:0] - attribute \src "libresoc.v:101261.5-101261.29" + attribute \src "libresoc.v:101325.5-101325.29" switch \initial - attribute \src "libresoc.v:101261.9-101261.17" + attribute \src "libresoc.v:101325.9-101325.17" case 1'1 case end @@ -157873,14 +157924,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_ldst_len $0\dec31_dec_sub19_ldst_len[3:0] end - attribute \src "libresoc.v:101279.3-101297.6" - process $proc$libresoc.v:101279$4066 + attribute \src "libresoc.v:101343.3-101361.6" + process $proc$libresoc.v:101343$4066 assign { } { } assign { } { } assign $0\dec31_dec_sub19_internal_op[6:0] $1\dec31_dec_sub19_internal_op[6:0] - attribute \src "libresoc.v:101280.5-101280.29" + attribute \src "libresoc.v:101344.5-101344.29" switch \initial - attribute \src "libresoc.v:101280.9-101280.17" + attribute \src "libresoc.v:101344.9-101344.17" case 1'1 case end @@ -157908,14 +157959,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_internal_op $0\dec31_dec_sub19_internal_op[6:0] end - attribute \src "libresoc.v:101298.3-101316.6" - process $proc$libresoc.v:101298$4067 + attribute \src "libresoc.v:101362.3-101380.6" + process $proc$libresoc.v:101362$4067 assign { } { } assign { } { } assign $0\dec31_dec_sub19_upd[1:0] $1\dec31_dec_sub19_upd[1:0] - attribute \src "libresoc.v:101299.5-101299.29" + attribute \src "libresoc.v:101363.5-101363.29" switch \initial - attribute \src "libresoc.v:101299.9-101299.17" + attribute \src "libresoc.v:101363.9-101363.17" case 1'1 case end @@ -157943,14 +157994,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_upd $0\dec31_dec_sub19_upd[1:0] end - attribute \src "libresoc.v:101317.3-101335.6" - process $proc$libresoc.v:101317$4068 + attribute \src "libresoc.v:101381.3-101399.6" + process $proc$libresoc.v:101381$4068 assign { } { } assign { } { } assign $0\dec31_dec_sub19_rc_sel[1:0] $1\dec31_dec_sub19_rc_sel[1:0] - attribute \src "libresoc.v:101318.5-101318.29" + attribute \src "libresoc.v:101382.5-101382.29" switch \initial - attribute \src "libresoc.v:101318.9-101318.17" + attribute \src "libresoc.v:101382.9-101382.17" case 1'1 case end @@ -157978,14 +158029,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_rc_sel $0\dec31_dec_sub19_rc_sel[1:0] end - attribute \src "libresoc.v:101336.3-101354.6" - process $proc$libresoc.v:101336$4069 + attribute \src "libresoc.v:101400.3-101418.6" + process $proc$libresoc.v:101400$4069 assign { } { } assign { } { } assign $0\dec31_dec_sub19_cry_in[1:0] $1\dec31_dec_sub19_cry_in[1:0] - attribute \src "libresoc.v:101337.5-101337.29" + attribute \src "libresoc.v:101401.5-101401.29" switch \initial - attribute \src "libresoc.v:101337.9-101337.17" + attribute \src "libresoc.v:101401.9-101401.17" case 1'1 case end @@ -158013,14 +158064,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_cry_in $0\dec31_dec_sub19_cry_in[1:0] end - attribute \src "libresoc.v:101355.3-101373.6" - process $proc$libresoc.v:101355$4070 + attribute \src "libresoc.v:101419.3-101437.6" + process $proc$libresoc.v:101419$4070 assign { } { } assign { } { } assign $0\dec31_dec_sub19_asmcode[7:0] $1\dec31_dec_sub19_asmcode[7:0] - attribute \src "libresoc.v:101356.5-101356.29" + attribute \src "libresoc.v:101420.5-101420.29" switch \initial - attribute \src "libresoc.v:101356.9-101356.17" + attribute \src "libresoc.v:101420.9-101420.17" case 1'1 case end @@ -158048,14 +158099,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_asmcode $0\dec31_dec_sub19_asmcode[7:0] end - attribute \src "libresoc.v:101374.3-101392.6" - process $proc$libresoc.v:101374$4071 + attribute \src "libresoc.v:101438.3-101456.6" + process $proc$libresoc.v:101438$4071 assign { } { } assign { } { } assign $0\dec31_dec_sub19_inv_a[0:0] $1\dec31_dec_sub19_inv_a[0:0] - attribute \src "libresoc.v:101375.5-101375.29" + attribute \src "libresoc.v:101439.5-101439.29" switch \initial - attribute \src "libresoc.v:101375.9-101375.17" + attribute \src "libresoc.v:101439.9-101439.17" case 1'1 case end @@ -158083,14 +158134,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_inv_a $0\dec31_dec_sub19_inv_a[0:0] end - attribute \src "libresoc.v:101393.3-101411.6" - process $proc$libresoc.v:101393$4072 + attribute \src "libresoc.v:101457.3-101475.6" + process $proc$libresoc.v:101457$4072 assign { } { } assign { } { } assign $0\dec31_dec_sub19_inv_out[0:0] $1\dec31_dec_sub19_inv_out[0:0] - attribute \src "libresoc.v:101394.5-101394.29" + attribute \src "libresoc.v:101458.5-101458.29" switch \initial - attribute \src "libresoc.v:101394.9-101394.17" + attribute \src "libresoc.v:101458.9-101458.17" case 1'1 case end @@ -158118,14 +158169,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_inv_out $0\dec31_dec_sub19_inv_out[0:0] end - attribute \src "libresoc.v:101412.3-101430.6" - process $proc$libresoc.v:101412$4073 + attribute \src "libresoc.v:101476.3-101494.6" + process $proc$libresoc.v:101476$4073 assign { } { } assign { } { } assign $0\dec31_dec_sub19_cry_out[0:0] $1\dec31_dec_sub19_cry_out[0:0] - attribute \src "libresoc.v:101413.5-101413.29" + attribute \src "libresoc.v:101477.5-101477.29" switch \initial - attribute \src "libresoc.v:101413.9-101413.17" + attribute \src "libresoc.v:101477.9-101477.17" case 1'1 case end @@ -158153,14 +158204,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_cry_out $0\dec31_dec_sub19_cry_out[0:0] end - attribute \src "libresoc.v:101431.3-101449.6" - process $proc$libresoc.v:101431$4074 + attribute \src "libresoc.v:101495.3-101513.6" + process $proc$libresoc.v:101495$4074 assign { } { } assign { } { } assign $0\dec31_dec_sub19_br[0:0] $1\dec31_dec_sub19_br[0:0] - attribute \src "libresoc.v:101432.5-101432.29" + attribute \src "libresoc.v:101496.5-101496.29" switch \initial - attribute \src "libresoc.v:101432.9-101432.17" + attribute \src "libresoc.v:101496.9-101496.17" case 1'1 case end @@ -158188,14 +158239,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_br $0\dec31_dec_sub19_br[0:0] end - attribute \src "libresoc.v:101450.3-101468.6" - process $proc$libresoc.v:101450$4075 + attribute \src "libresoc.v:101514.3-101532.6" + process $proc$libresoc.v:101514$4075 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sgn_ext[0:0] $1\dec31_dec_sub19_sgn_ext[0:0] - attribute \src "libresoc.v:101451.5-101451.29" + attribute \src "libresoc.v:101515.5-101515.29" switch \initial - attribute \src "libresoc.v:101451.9-101451.17" + attribute \src "libresoc.v:101515.9-101515.17" case 1'1 case end @@ -158223,14 +158274,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sgn_ext $0\dec31_dec_sub19_sgn_ext[0:0] end - attribute \src "libresoc.v:101469.3-101487.6" - process $proc$libresoc.v:101469$4076 + attribute \src "libresoc.v:101533.3-101551.6" + process $proc$libresoc.v:101533$4076 assign { } { } assign { } { } assign $0\dec31_dec_sub19_rsrv[0:0] $1\dec31_dec_sub19_rsrv[0:0] - attribute \src "libresoc.v:101470.5-101470.29" + attribute \src "libresoc.v:101534.5-101534.29" switch \initial - attribute \src "libresoc.v:101470.9-101470.17" + attribute \src "libresoc.v:101534.9-101534.17" case 1'1 case end @@ -158258,14 +158309,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_rsrv $0\dec31_dec_sub19_rsrv[0:0] end - attribute \src "libresoc.v:101488.3-101506.6" - process $proc$libresoc.v:101488$4077 + attribute \src "libresoc.v:101552.3-101570.6" + process $proc$libresoc.v:101552$4077 assign { } { } assign { } { } assign $0\dec31_dec_sub19_form[4:0] $1\dec31_dec_sub19_form[4:0] - attribute \src "libresoc.v:101489.5-101489.29" + attribute \src "libresoc.v:101553.5-101553.29" switch \initial - attribute \src "libresoc.v:101489.9-101489.17" + attribute \src "libresoc.v:101553.9-101553.17" case 1'1 case end @@ -158293,14 +158344,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_form $0\dec31_dec_sub19_form[4:0] end - attribute \src "libresoc.v:101507.3-101525.6" - process $proc$libresoc.v:101507$4078 + attribute \src "libresoc.v:101571.3-101589.6" + process $proc$libresoc.v:101571$4078 assign { } { } assign { } { } assign $0\dec31_dec_sub19_is_32b[0:0] $1\dec31_dec_sub19_is_32b[0:0] - attribute \src "libresoc.v:101508.5-101508.29" + attribute \src "libresoc.v:101572.5-101572.29" switch \initial - attribute \src "libresoc.v:101508.9-101508.17" + attribute \src "libresoc.v:101572.9-101572.17" case 1'1 case end @@ -158328,14 +158379,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_is_32b $0\dec31_dec_sub19_is_32b[0:0] end - attribute \src "libresoc.v:101526.3-101544.6" - process $proc$libresoc.v:101526$4079 + attribute \src "libresoc.v:101590.3-101608.6" + process $proc$libresoc.v:101590$4079 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sgn[0:0] $1\dec31_dec_sub19_sgn[0:0] - attribute \src "libresoc.v:101527.5-101527.29" + attribute \src "libresoc.v:101591.5-101591.29" switch \initial - attribute \src "libresoc.v:101527.9-101527.17" + attribute \src "libresoc.v:101591.9-101591.17" case 1'1 case end @@ -158363,14 +158414,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sgn $0\dec31_dec_sub19_sgn[0:0] end - attribute \src "libresoc.v:101545.3-101563.6" - process $proc$libresoc.v:101545$4080 + attribute \src "libresoc.v:101609.3-101627.6" + process $proc$libresoc.v:101609$4080 assign { } { } assign { } { } assign $0\dec31_dec_sub19_lk[0:0] $1\dec31_dec_sub19_lk[0:0] - attribute \src "libresoc.v:101546.5-101546.29" + attribute \src "libresoc.v:101610.5-101610.29" switch \initial - attribute \src "libresoc.v:101546.9-101546.17" + attribute \src "libresoc.v:101610.9-101610.17" case 1'1 case end @@ -158398,14 +158449,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_lk $0\dec31_dec_sub19_lk[0:0] end - attribute \src "libresoc.v:101564.3-101582.6" - process $proc$libresoc.v:101564$4081 + attribute \src "libresoc.v:101628.3-101646.6" + process $proc$libresoc.v:101628$4081 assign { } { } assign { } { } assign $0\dec31_dec_sub19_sgl_pipe[0:0] $1\dec31_dec_sub19_sgl_pipe[0:0] - attribute \src "libresoc.v:101565.5-101565.29" + attribute \src "libresoc.v:101629.5-101629.29" switch \initial - attribute \src "libresoc.v:101565.9-101565.17" + attribute \src "libresoc.v:101629.9-101629.17" case 1'1 case end @@ -158433,14 +158484,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_sgl_pipe $0\dec31_dec_sub19_sgl_pipe[0:0] end - attribute \src "libresoc.v:101583.3-101601.6" - process $proc$libresoc.v:101583$4082 + attribute \src "libresoc.v:101647.3-101665.6" + process $proc$libresoc.v:101647$4082 assign { } { } assign { } { } assign $0\dec31_dec_sub19_SV_Etype[1:0] $1\dec31_dec_sub19_SV_Etype[1:0] - attribute \src "libresoc.v:101584.5-101584.29" + attribute \src "libresoc.v:101648.5-101648.29" switch \initial - attribute \src "libresoc.v:101584.9-101584.17" + attribute \src "libresoc.v:101648.9-101648.17" case 1'1 case end @@ -158468,14 +158519,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_SV_Etype $0\dec31_dec_sub19_SV_Etype[1:0] end - attribute \src "libresoc.v:101602.3-101620.6" - process $proc$libresoc.v:101602$4083 + attribute \src "libresoc.v:101666.3-101684.6" + process $proc$libresoc.v:101666$4083 assign { } { } assign { } { } assign $0\dec31_dec_sub19_SV_Ptype[1:0] $1\dec31_dec_sub19_SV_Ptype[1:0] - attribute \src "libresoc.v:101603.5-101603.29" + attribute \src "libresoc.v:101667.5-101667.29" switch \initial - attribute \src "libresoc.v:101603.9-101603.17" + attribute \src "libresoc.v:101667.9-101667.17" case 1'1 case end @@ -158503,14 +158554,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_SV_Ptype $0\dec31_dec_sub19_SV_Ptype[1:0] end - attribute \src "libresoc.v:101621.3-101639.6" - process $proc$libresoc.v:101621$4084 + attribute \src "libresoc.v:101685.3-101703.6" + process $proc$libresoc.v:101685$4084 assign { } { } assign { } { } assign $0\dec31_dec_sub19_in1_sel[2:0] $1\dec31_dec_sub19_in1_sel[2:0] - attribute \src "libresoc.v:101622.5-101622.29" + attribute \src "libresoc.v:101686.5-101686.29" switch \initial - attribute \src "libresoc.v:101622.9-101622.17" + attribute \src "libresoc.v:101686.9-101686.17" case 1'1 case end @@ -158538,14 +158589,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_in1_sel $0\dec31_dec_sub19_in1_sel[2:0] end - attribute \src "libresoc.v:101640.3-101658.6" - process $proc$libresoc.v:101640$4085 + attribute \src "libresoc.v:101704.3-101722.6" + process $proc$libresoc.v:101704$4085 assign { } { } assign { } { } assign $0\dec31_dec_sub19_in2_sel[3:0] $1\dec31_dec_sub19_in2_sel[3:0] - attribute \src "libresoc.v:101641.5-101641.29" + attribute \src "libresoc.v:101705.5-101705.29" switch \initial - attribute \src "libresoc.v:101641.9-101641.17" + attribute \src "libresoc.v:101705.9-101705.17" case 1'1 case end @@ -158573,14 +158624,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_in2_sel $0\dec31_dec_sub19_in2_sel[3:0] end - attribute \src "libresoc.v:101659.3-101677.6" - process $proc$libresoc.v:101659$4086 + attribute \src "libresoc.v:101723.3-101741.6" + process $proc$libresoc.v:101723$4086 assign { } { } assign { } { } assign $0\dec31_dec_sub19_in3_sel[1:0] $1\dec31_dec_sub19_in3_sel[1:0] - attribute \src "libresoc.v:101660.5-101660.29" + attribute \src "libresoc.v:101724.5-101724.29" switch \initial - attribute \src "libresoc.v:101660.9-101660.17" + attribute \src "libresoc.v:101724.9-101724.17" case 1'1 case end @@ -158608,14 +158659,14 @@ module \dec31_dec_sub19 sync always update \dec31_dec_sub19_in3_sel $0\dec31_dec_sub19_in3_sel[1:0] end - attribute \src "libresoc.v:101678.3-101696.6" - process $proc$libresoc.v:101678$4087 + attribute \src "libresoc.v:101742.3-101760.6" + process $proc$libresoc.v:101742$4087 assign { } { } assign { } { } assign $0\dec31_dec_sub19_out_sel[2:0] $1\dec31_dec_sub19_out_sel[2:0] - attribute \src "libresoc.v:101679.5-101679.29" + attribute \src "libresoc.v:101743.5-101743.29" switch \initial - attribute \src "libresoc.v:101679.9-101679.17" + attribute \src "libresoc.v:101743.9-101743.17" case 1'1 case end @@ -158645,144 +158696,144 @@ module \dec31_dec_sub19 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:101702.1-102877.10" +attribute \src "libresoc.v:101766.1-102941.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub20" attribute \generator "nMigen" module \dec31_dec_sub20 - attribute \src "libresoc.v:102726.3-102750.6" + attribute \src "libresoc.v:102790.3-102814.6" wire width 2 $0\dec31_dec_sub20_SV_Etype[1:0] - attribute \src "libresoc.v:102751.3-102775.6" + attribute \src "libresoc.v:102815.3-102839.6" wire width 2 $0\dec31_dec_sub20_SV_Ptype[1:0] - attribute \src "libresoc.v:102426.3-102450.6" + attribute \src "libresoc.v:102490.3-102514.6" wire width 8 $0\dec31_dec_sub20_asmcode[7:0] - attribute \src "libresoc.v:102526.3-102550.6" + attribute \src "libresoc.v:102590.3-102614.6" wire $0\dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:102076.3-102100.6" + attribute \src "libresoc.v:102140.3-102164.6" wire width 3 $0\dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:102101.3-102125.6" + attribute \src "libresoc.v:102165.3-102189.6" wire width 3 $0\dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:102401.3-102425.6" + attribute \src "libresoc.v:102465.3-102489.6" wire width 2 $0\dec31_dec_sub20_cry_in[1:0] - attribute \src "libresoc.v:102501.3-102525.6" + attribute \src "libresoc.v:102565.3-102589.6" wire $0\dec31_dec_sub20_cry_out[0:0] - attribute \src "libresoc.v:102601.3-102625.6" + attribute \src "libresoc.v:102665.3-102689.6" wire width 5 $0\dec31_dec_sub20_form[4:0] - attribute \src "libresoc.v:102051.3-102075.6" + attribute \src "libresoc.v:102115.3-102139.6" wire width 14 $0\dec31_dec_sub20_function_unit[13:0] - attribute \src "libresoc.v:102776.3-102800.6" + attribute \src "libresoc.v:102840.3-102864.6" wire width 3 $0\dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:102801.3-102825.6" + attribute \src "libresoc.v:102865.3-102889.6" wire width 4 $0\dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:102826.3-102850.6" + attribute \src "libresoc.v:102890.3-102914.6" wire width 2 $0\dec31_dec_sub20_in3_sel[1:0] - attribute \src "libresoc.v:102326.3-102350.6" + attribute \src "libresoc.v:102390.3-102414.6" wire width 7 $0\dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:102451.3-102475.6" + attribute \src "libresoc.v:102515.3-102539.6" wire $0\dec31_dec_sub20_inv_a[0:0] - attribute \src "libresoc.v:102476.3-102500.6" + attribute \src "libresoc.v:102540.3-102564.6" wire $0\dec31_dec_sub20_inv_out[0:0] - attribute \src "libresoc.v:102626.3-102650.6" + attribute \src "libresoc.v:102690.3-102714.6" wire $0\dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:102301.3-102325.6" + attribute \src "libresoc.v:102365.3-102389.6" wire width 4 $0\dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:102676.3-102700.6" + attribute \src "libresoc.v:102740.3-102764.6" wire $0\dec31_dec_sub20_lk[0:0] - attribute \src "libresoc.v:102851.3-102875.6" + attribute \src "libresoc.v:102915.3-102939.6" wire width 3 $0\dec31_dec_sub20_out_sel[2:0] - attribute \src "libresoc.v:102376.3-102400.6" + attribute \src "libresoc.v:102440.3-102464.6" wire width 2 $0\dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:102576.3-102600.6" + attribute \src "libresoc.v:102640.3-102664.6" wire $0\dec31_dec_sub20_rsrv[0:0] - attribute \src "libresoc.v:102701.3-102725.6" + attribute \src "libresoc.v:102765.3-102789.6" wire $0\dec31_dec_sub20_sgl_pipe[0:0] - attribute \src "libresoc.v:102651.3-102675.6" + attribute \src "libresoc.v:102715.3-102739.6" wire $0\dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:102551.3-102575.6" + attribute \src "libresoc.v:102615.3-102639.6" wire $0\dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:102251.3-102275.6" + attribute \src "libresoc.v:102315.3-102339.6" wire width 3 $0\dec31_dec_sub20_sv_cr_in[2:0] - attribute \src "libresoc.v:102276.3-102300.6" + attribute \src "libresoc.v:102340.3-102364.6" wire width 3 $0\dec31_dec_sub20_sv_cr_out[2:0] - attribute \src "libresoc.v:102126.3-102150.6" + attribute \src "libresoc.v:102190.3-102214.6" wire width 3 $0\dec31_dec_sub20_sv_in1[2:0] - attribute \src "libresoc.v:102151.3-102175.6" + attribute \src "libresoc.v:102215.3-102239.6" wire width 3 $0\dec31_dec_sub20_sv_in2[2:0] - attribute \src "libresoc.v:102176.3-102200.6" + attribute \src "libresoc.v:102240.3-102264.6" wire width 3 $0\dec31_dec_sub20_sv_in3[2:0] - attribute \src "libresoc.v:102226.3-102250.6" + attribute \src "libresoc.v:102290.3-102314.6" wire width 3 $0\dec31_dec_sub20_sv_out2[2:0] - attribute \src "libresoc.v:102201.3-102225.6" + attribute \src "libresoc.v:102265.3-102289.6" wire width 3 $0\dec31_dec_sub20_sv_out[2:0] - attribute \src "libresoc.v:102351.3-102375.6" + attribute \src "libresoc.v:102415.3-102439.6" wire width 2 $0\dec31_dec_sub20_upd[1:0] - attribute \src "libresoc.v:101703.7-101703.20" + attribute \src "libresoc.v:101767.7-101767.20" wire $0\initial[0:0] - attribute \src "libresoc.v:102726.3-102750.6" + attribute \src "libresoc.v:102790.3-102814.6" wire width 2 $1\dec31_dec_sub20_SV_Etype[1:0] - attribute \src "libresoc.v:102751.3-102775.6" + attribute \src "libresoc.v:102815.3-102839.6" wire width 2 $1\dec31_dec_sub20_SV_Ptype[1:0] - attribute \src "libresoc.v:102426.3-102450.6" + attribute \src "libresoc.v:102490.3-102514.6" wire width 8 $1\dec31_dec_sub20_asmcode[7:0] - attribute \src "libresoc.v:102526.3-102550.6" + attribute \src "libresoc.v:102590.3-102614.6" wire $1\dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:102076.3-102100.6" + attribute \src "libresoc.v:102140.3-102164.6" wire width 3 $1\dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:102101.3-102125.6" + attribute \src "libresoc.v:102165.3-102189.6" wire width 3 $1\dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:102401.3-102425.6" + attribute \src "libresoc.v:102465.3-102489.6" wire width 2 $1\dec31_dec_sub20_cry_in[1:0] - attribute \src "libresoc.v:102501.3-102525.6" + attribute \src "libresoc.v:102565.3-102589.6" wire $1\dec31_dec_sub20_cry_out[0:0] - attribute \src "libresoc.v:102601.3-102625.6" + attribute \src "libresoc.v:102665.3-102689.6" wire width 5 $1\dec31_dec_sub20_form[4:0] - attribute \src "libresoc.v:102051.3-102075.6" + attribute \src "libresoc.v:102115.3-102139.6" wire width 14 $1\dec31_dec_sub20_function_unit[13:0] - attribute \src "libresoc.v:102776.3-102800.6" + attribute \src "libresoc.v:102840.3-102864.6" wire width 3 $1\dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:102801.3-102825.6" + attribute \src "libresoc.v:102865.3-102889.6" wire width 4 $1\dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:102826.3-102850.6" + attribute \src "libresoc.v:102890.3-102914.6" wire width 2 $1\dec31_dec_sub20_in3_sel[1:0] - attribute \src "libresoc.v:102326.3-102350.6" + attribute \src "libresoc.v:102390.3-102414.6" wire width 7 $1\dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:102451.3-102475.6" + attribute \src "libresoc.v:102515.3-102539.6" wire $1\dec31_dec_sub20_inv_a[0:0] - attribute \src "libresoc.v:102476.3-102500.6" + attribute \src "libresoc.v:102540.3-102564.6" wire $1\dec31_dec_sub20_inv_out[0:0] - attribute \src "libresoc.v:102626.3-102650.6" + attribute \src "libresoc.v:102690.3-102714.6" wire $1\dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:102301.3-102325.6" + attribute \src "libresoc.v:102365.3-102389.6" wire width 4 $1\dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:102676.3-102700.6" + attribute \src "libresoc.v:102740.3-102764.6" wire $1\dec31_dec_sub20_lk[0:0] - attribute \src "libresoc.v:102851.3-102875.6" + attribute \src "libresoc.v:102915.3-102939.6" wire width 3 $1\dec31_dec_sub20_out_sel[2:0] - attribute \src "libresoc.v:102376.3-102400.6" + attribute \src "libresoc.v:102440.3-102464.6" wire width 2 $1\dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:102576.3-102600.6" + attribute \src "libresoc.v:102640.3-102664.6" wire $1\dec31_dec_sub20_rsrv[0:0] - attribute \src "libresoc.v:102701.3-102725.6" + attribute \src "libresoc.v:102765.3-102789.6" wire $1\dec31_dec_sub20_sgl_pipe[0:0] - attribute \src "libresoc.v:102651.3-102675.6" + attribute \src "libresoc.v:102715.3-102739.6" wire $1\dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:102551.3-102575.6" + attribute \src "libresoc.v:102615.3-102639.6" wire $1\dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:102251.3-102275.6" + attribute \src "libresoc.v:102315.3-102339.6" wire width 3 $1\dec31_dec_sub20_sv_cr_in[2:0] - attribute \src "libresoc.v:102276.3-102300.6" + attribute \src "libresoc.v:102340.3-102364.6" wire width 3 $1\dec31_dec_sub20_sv_cr_out[2:0] - attribute \src "libresoc.v:102126.3-102150.6" + attribute \src "libresoc.v:102190.3-102214.6" wire width 3 $1\dec31_dec_sub20_sv_in1[2:0] - attribute \src "libresoc.v:102151.3-102175.6" + attribute \src "libresoc.v:102215.3-102239.6" wire width 3 $1\dec31_dec_sub20_sv_in2[2:0] - attribute \src "libresoc.v:102176.3-102200.6" + attribute \src "libresoc.v:102240.3-102264.6" wire width 3 $1\dec31_dec_sub20_sv_in3[2:0] - attribute \src "libresoc.v:102226.3-102250.6" + attribute \src "libresoc.v:102290.3-102314.6" wire width 3 $1\dec31_dec_sub20_sv_out2[2:0] - attribute \src "libresoc.v:102201.3-102225.6" + attribute \src "libresoc.v:102265.3-102289.6" wire width 3 $1\dec31_dec_sub20_sv_out[2:0] - attribute \src "libresoc.v:102351.3-102375.6" + attribute \src "libresoc.v:102415.3-102439.6" wire width 2 $1\dec31_dec_sub20_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -159094,28 +159145,28 @@ module \dec31_dec_sub20 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub20_upd - attribute \src "libresoc.v:101703.7-101703.15" + attribute \src "libresoc.v:101767.7-101767.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:101703.7-101703.20" - process $proc$libresoc.v:101703$4122 + attribute \src "libresoc.v:101767.7-101767.20" + process $proc$libresoc.v:101767$4122 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:102051.3-102075.6" - process $proc$libresoc.v:102051$4089 + attribute \src "libresoc.v:102115.3-102139.6" + process $proc$libresoc.v:102115$4089 assign { } { } assign { } { } assign $0\dec31_dec_sub20_function_unit[13:0] $1\dec31_dec_sub20_function_unit[13:0] - attribute \src "libresoc.v:102052.5-102052.29" + attribute \src "libresoc.v:102116.5-102116.29" switch \initial - attribute \src "libresoc.v:102052.9-102052.17" + attribute \src "libresoc.v:102116.9-102116.17" case 1'1 case end @@ -159151,14 +159202,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_function_unit $0\dec31_dec_sub20_function_unit[13:0] end - attribute \src "libresoc.v:102076.3-102100.6" - process $proc$libresoc.v:102076$4090 + attribute \src "libresoc.v:102140.3-102164.6" + process $proc$libresoc.v:102140$4090 assign { } { } assign { } { } assign $0\dec31_dec_sub20_cr_in[2:0] $1\dec31_dec_sub20_cr_in[2:0] - attribute \src "libresoc.v:102077.5-102077.29" + attribute \src "libresoc.v:102141.5-102141.29" switch \initial - attribute \src "libresoc.v:102077.9-102077.17" + attribute \src "libresoc.v:102141.9-102141.17" case 1'1 case end @@ -159194,14 +159245,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_cr_in $0\dec31_dec_sub20_cr_in[2:0] end - attribute \src "libresoc.v:102101.3-102125.6" - process $proc$libresoc.v:102101$4091 + attribute \src "libresoc.v:102165.3-102189.6" + process $proc$libresoc.v:102165$4091 assign { } { } assign { } { } assign $0\dec31_dec_sub20_cr_out[2:0] $1\dec31_dec_sub20_cr_out[2:0] - attribute \src "libresoc.v:102102.5-102102.29" + attribute \src "libresoc.v:102166.5-102166.29" switch \initial - attribute \src "libresoc.v:102102.9-102102.17" + attribute \src "libresoc.v:102166.9-102166.17" case 1'1 case end @@ -159237,14 +159288,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_cr_out $0\dec31_dec_sub20_cr_out[2:0] end - attribute \src "libresoc.v:102126.3-102150.6" - process $proc$libresoc.v:102126$4092 + attribute \src "libresoc.v:102190.3-102214.6" + process $proc$libresoc.v:102190$4092 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_in1[2:0] $1\dec31_dec_sub20_sv_in1[2:0] - attribute \src "libresoc.v:102127.5-102127.29" + attribute \src "libresoc.v:102191.5-102191.29" switch \initial - attribute \src "libresoc.v:102127.9-102127.17" + attribute \src "libresoc.v:102191.9-102191.17" case 1'1 case end @@ -159280,14 +159331,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_in1 $0\dec31_dec_sub20_sv_in1[2:0] end - attribute \src "libresoc.v:102151.3-102175.6" - process $proc$libresoc.v:102151$4093 + attribute \src "libresoc.v:102215.3-102239.6" + process $proc$libresoc.v:102215$4093 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_in2[2:0] $1\dec31_dec_sub20_sv_in2[2:0] - attribute \src "libresoc.v:102152.5-102152.29" + attribute \src "libresoc.v:102216.5-102216.29" switch \initial - attribute \src "libresoc.v:102152.9-102152.17" + attribute \src "libresoc.v:102216.9-102216.17" case 1'1 case end @@ -159323,14 +159374,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_in2 $0\dec31_dec_sub20_sv_in2[2:0] end - attribute \src "libresoc.v:102176.3-102200.6" - process $proc$libresoc.v:102176$4094 + attribute \src "libresoc.v:102240.3-102264.6" + process $proc$libresoc.v:102240$4094 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_in3[2:0] $1\dec31_dec_sub20_sv_in3[2:0] - attribute \src "libresoc.v:102177.5-102177.29" + attribute \src "libresoc.v:102241.5-102241.29" switch \initial - attribute \src "libresoc.v:102177.9-102177.17" + attribute \src "libresoc.v:102241.9-102241.17" case 1'1 case end @@ -159366,14 +159417,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_in3 $0\dec31_dec_sub20_sv_in3[2:0] end - attribute \src "libresoc.v:102201.3-102225.6" - process $proc$libresoc.v:102201$4095 + attribute \src "libresoc.v:102265.3-102289.6" + process $proc$libresoc.v:102265$4095 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_out[2:0] $1\dec31_dec_sub20_sv_out[2:0] - attribute \src "libresoc.v:102202.5-102202.29" + attribute \src "libresoc.v:102266.5-102266.29" switch \initial - attribute \src "libresoc.v:102202.9-102202.17" + attribute \src "libresoc.v:102266.9-102266.17" case 1'1 case end @@ -159409,14 +159460,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_out $0\dec31_dec_sub20_sv_out[2:0] end - attribute \src "libresoc.v:102226.3-102250.6" - process $proc$libresoc.v:102226$4096 + attribute \src "libresoc.v:102290.3-102314.6" + process $proc$libresoc.v:102290$4096 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_out2[2:0] $1\dec31_dec_sub20_sv_out2[2:0] - attribute \src "libresoc.v:102227.5-102227.29" + attribute \src "libresoc.v:102291.5-102291.29" switch \initial - attribute \src "libresoc.v:102227.9-102227.17" + attribute \src "libresoc.v:102291.9-102291.17" case 1'1 case end @@ -159452,14 +159503,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_out2 $0\dec31_dec_sub20_sv_out2[2:0] end - attribute \src "libresoc.v:102251.3-102275.6" - process $proc$libresoc.v:102251$4097 + attribute \src "libresoc.v:102315.3-102339.6" + process $proc$libresoc.v:102315$4097 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_cr_in[2:0] $1\dec31_dec_sub20_sv_cr_in[2:0] - attribute \src "libresoc.v:102252.5-102252.29" + attribute \src "libresoc.v:102316.5-102316.29" switch \initial - attribute \src "libresoc.v:102252.9-102252.17" + attribute \src "libresoc.v:102316.9-102316.17" case 1'1 case end @@ -159495,14 +159546,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_cr_in $0\dec31_dec_sub20_sv_cr_in[2:0] end - attribute \src "libresoc.v:102276.3-102300.6" - process $proc$libresoc.v:102276$4098 + attribute \src "libresoc.v:102340.3-102364.6" + process $proc$libresoc.v:102340$4098 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sv_cr_out[2:0] $1\dec31_dec_sub20_sv_cr_out[2:0] - attribute \src "libresoc.v:102277.5-102277.29" + attribute \src "libresoc.v:102341.5-102341.29" switch \initial - attribute \src "libresoc.v:102277.9-102277.17" + attribute \src "libresoc.v:102341.9-102341.17" case 1'1 case end @@ -159538,14 +159589,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sv_cr_out $0\dec31_dec_sub20_sv_cr_out[2:0] end - attribute \src "libresoc.v:102301.3-102325.6" - process $proc$libresoc.v:102301$4099 + attribute \src "libresoc.v:102365.3-102389.6" + process $proc$libresoc.v:102365$4099 assign { } { } assign { } { } assign $0\dec31_dec_sub20_ldst_len[3:0] $1\dec31_dec_sub20_ldst_len[3:0] - attribute \src "libresoc.v:102302.5-102302.29" + attribute \src "libresoc.v:102366.5-102366.29" switch \initial - attribute \src "libresoc.v:102302.9-102302.17" + attribute \src "libresoc.v:102366.9-102366.17" case 1'1 case end @@ -159581,14 +159632,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_ldst_len $0\dec31_dec_sub20_ldst_len[3:0] end - attribute \src "libresoc.v:102326.3-102350.6" - process $proc$libresoc.v:102326$4100 + attribute \src "libresoc.v:102390.3-102414.6" + process $proc$libresoc.v:102390$4100 assign { } { } assign { } { } assign $0\dec31_dec_sub20_internal_op[6:0] $1\dec31_dec_sub20_internal_op[6:0] - attribute \src "libresoc.v:102327.5-102327.29" + attribute \src "libresoc.v:102391.5-102391.29" switch \initial - attribute \src "libresoc.v:102327.9-102327.17" + attribute \src "libresoc.v:102391.9-102391.17" case 1'1 case end @@ -159624,14 +159675,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_internal_op $0\dec31_dec_sub20_internal_op[6:0] end - attribute \src "libresoc.v:102351.3-102375.6" - process $proc$libresoc.v:102351$4101 + attribute \src "libresoc.v:102415.3-102439.6" + process $proc$libresoc.v:102415$4101 assign { } { } assign { } { } assign $0\dec31_dec_sub20_upd[1:0] $1\dec31_dec_sub20_upd[1:0] - attribute \src "libresoc.v:102352.5-102352.29" + attribute \src "libresoc.v:102416.5-102416.29" switch \initial - attribute \src "libresoc.v:102352.9-102352.17" + attribute \src "libresoc.v:102416.9-102416.17" case 1'1 case end @@ -159667,14 +159718,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_upd $0\dec31_dec_sub20_upd[1:0] end - attribute \src "libresoc.v:102376.3-102400.6" - process $proc$libresoc.v:102376$4102 + attribute \src "libresoc.v:102440.3-102464.6" + process $proc$libresoc.v:102440$4102 assign { } { } assign { } { } assign $0\dec31_dec_sub20_rc_sel[1:0] $1\dec31_dec_sub20_rc_sel[1:0] - attribute \src "libresoc.v:102377.5-102377.29" + attribute \src "libresoc.v:102441.5-102441.29" switch \initial - attribute \src "libresoc.v:102377.9-102377.17" + attribute \src "libresoc.v:102441.9-102441.17" case 1'1 case end @@ -159710,14 +159761,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_rc_sel $0\dec31_dec_sub20_rc_sel[1:0] end - attribute \src "libresoc.v:102401.3-102425.6" - process $proc$libresoc.v:102401$4103 + attribute \src "libresoc.v:102465.3-102489.6" + process $proc$libresoc.v:102465$4103 assign { } { } assign { } { } assign $0\dec31_dec_sub20_cry_in[1:0] $1\dec31_dec_sub20_cry_in[1:0] - attribute \src "libresoc.v:102402.5-102402.29" + attribute \src "libresoc.v:102466.5-102466.29" switch \initial - attribute \src "libresoc.v:102402.9-102402.17" + attribute \src "libresoc.v:102466.9-102466.17" case 1'1 case end @@ -159753,14 +159804,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_cry_in $0\dec31_dec_sub20_cry_in[1:0] end - attribute \src "libresoc.v:102426.3-102450.6" - process $proc$libresoc.v:102426$4104 + attribute \src "libresoc.v:102490.3-102514.6" + process $proc$libresoc.v:102490$4104 assign { } { } assign { } { } assign $0\dec31_dec_sub20_asmcode[7:0] $1\dec31_dec_sub20_asmcode[7:0] - attribute \src "libresoc.v:102427.5-102427.29" + attribute \src "libresoc.v:102491.5-102491.29" switch \initial - attribute \src "libresoc.v:102427.9-102427.17" + attribute \src "libresoc.v:102491.9-102491.17" case 1'1 case end @@ -159796,14 +159847,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_asmcode $0\dec31_dec_sub20_asmcode[7:0] end - attribute \src "libresoc.v:102451.3-102475.6" - process $proc$libresoc.v:102451$4105 + attribute \src "libresoc.v:102515.3-102539.6" + process $proc$libresoc.v:102515$4105 assign { } { } assign { } { } assign $0\dec31_dec_sub20_inv_a[0:0] $1\dec31_dec_sub20_inv_a[0:0] - attribute \src "libresoc.v:102452.5-102452.29" + attribute \src "libresoc.v:102516.5-102516.29" switch \initial - attribute \src "libresoc.v:102452.9-102452.17" + attribute \src "libresoc.v:102516.9-102516.17" case 1'1 case end @@ -159839,14 +159890,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_inv_a $0\dec31_dec_sub20_inv_a[0:0] end - attribute \src "libresoc.v:102476.3-102500.6" - process $proc$libresoc.v:102476$4106 + attribute \src "libresoc.v:102540.3-102564.6" + process $proc$libresoc.v:102540$4106 assign { } { } assign { } { } assign $0\dec31_dec_sub20_inv_out[0:0] $1\dec31_dec_sub20_inv_out[0:0] - attribute \src "libresoc.v:102477.5-102477.29" + attribute \src "libresoc.v:102541.5-102541.29" switch \initial - attribute \src "libresoc.v:102477.9-102477.17" + attribute \src "libresoc.v:102541.9-102541.17" case 1'1 case end @@ -159882,14 +159933,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_inv_out $0\dec31_dec_sub20_inv_out[0:0] end - attribute \src "libresoc.v:102501.3-102525.6" - process $proc$libresoc.v:102501$4107 + attribute \src "libresoc.v:102565.3-102589.6" + process $proc$libresoc.v:102565$4107 assign { } { } assign { } { } assign $0\dec31_dec_sub20_cry_out[0:0] $1\dec31_dec_sub20_cry_out[0:0] - attribute \src "libresoc.v:102502.5-102502.29" + attribute \src "libresoc.v:102566.5-102566.29" switch \initial - attribute \src "libresoc.v:102502.9-102502.17" + attribute \src "libresoc.v:102566.9-102566.17" case 1'1 case end @@ -159925,14 +159976,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_cry_out $0\dec31_dec_sub20_cry_out[0:0] end - attribute \src "libresoc.v:102526.3-102550.6" - process $proc$libresoc.v:102526$4108 + attribute \src "libresoc.v:102590.3-102614.6" + process $proc$libresoc.v:102590$4108 assign { } { } assign { } { } assign $0\dec31_dec_sub20_br[0:0] $1\dec31_dec_sub20_br[0:0] - attribute \src "libresoc.v:102527.5-102527.29" + attribute \src "libresoc.v:102591.5-102591.29" switch \initial - attribute \src "libresoc.v:102527.9-102527.17" + attribute \src "libresoc.v:102591.9-102591.17" case 1'1 case end @@ -159968,14 +160019,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_br $0\dec31_dec_sub20_br[0:0] end - attribute \src "libresoc.v:102551.3-102575.6" - process $proc$libresoc.v:102551$4109 + attribute \src "libresoc.v:102615.3-102639.6" + process $proc$libresoc.v:102615$4109 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sgn_ext[0:0] $1\dec31_dec_sub20_sgn_ext[0:0] - attribute \src "libresoc.v:102552.5-102552.29" + attribute \src "libresoc.v:102616.5-102616.29" switch \initial - attribute \src "libresoc.v:102552.9-102552.17" + attribute \src "libresoc.v:102616.9-102616.17" case 1'1 case end @@ -160011,14 +160062,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sgn_ext $0\dec31_dec_sub20_sgn_ext[0:0] end - attribute \src "libresoc.v:102576.3-102600.6" - process $proc$libresoc.v:102576$4110 + attribute \src "libresoc.v:102640.3-102664.6" + process $proc$libresoc.v:102640$4110 assign { } { } assign { } { } assign $0\dec31_dec_sub20_rsrv[0:0] $1\dec31_dec_sub20_rsrv[0:0] - attribute \src "libresoc.v:102577.5-102577.29" + attribute \src "libresoc.v:102641.5-102641.29" switch \initial - attribute \src "libresoc.v:102577.9-102577.17" + attribute \src "libresoc.v:102641.9-102641.17" case 1'1 case end @@ -160054,14 +160105,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_rsrv $0\dec31_dec_sub20_rsrv[0:0] end - attribute \src "libresoc.v:102601.3-102625.6" - process $proc$libresoc.v:102601$4111 + attribute \src "libresoc.v:102665.3-102689.6" + process $proc$libresoc.v:102665$4111 assign { } { } assign { } { } assign $0\dec31_dec_sub20_form[4:0] $1\dec31_dec_sub20_form[4:0] - attribute \src "libresoc.v:102602.5-102602.29" + attribute \src "libresoc.v:102666.5-102666.29" switch \initial - attribute \src "libresoc.v:102602.9-102602.17" + attribute \src "libresoc.v:102666.9-102666.17" case 1'1 case end @@ -160097,14 +160148,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_form $0\dec31_dec_sub20_form[4:0] end - attribute \src "libresoc.v:102626.3-102650.6" - process $proc$libresoc.v:102626$4112 + attribute \src "libresoc.v:102690.3-102714.6" + process $proc$libresoc.v:102690$4112 assign { } { } assign { } { } assign $0\dec31_dec_sub20_is_32b[0:0] $1\dec31_dec_sub20_is_32b[0:0] - attribute \src "libresoc.v:102627.5-102627.29" + attribute \src "libresoc.v:102691.5-102691.29" switch \initial - attribute \src "libresoc.v:102627.9-102627.17" + attribute \src "libresoc.v:102691.9-102691.17" case 1'1 case end @@ -160140,14 +160191,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_is_32b $0\dec31_dec_sub20_is_32b[0:0] end - attribute \src "libresoc.v:102651.3-102675.6" - process $proc$libresoc.v:102651$4113 + attribute \src "libresoc.v:102715.3-102739.6" + process $proc$libresoc.v:102715$4113 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sgn[0:0] $1\dec31_dec_sub20_sgn[0:0] - attribute \src "libresoc.v:102652.5-102652.29" + attribute \src "libresoc.v:102716.5-102716.29" switch \initial - attribute \src "libresoc.v:102652.9-102652.17" + attribute \src "libresoc.v:102716.9-102716.17" case 1'1 case end @@ -160183,14 +160234,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sgn $0\dec31_dec_sub20_sgn[0:0] end - attribute \src "libresoc.v:102676.3-102700.6" - process $proc$libresoc.v:102676$4114 + attribute \src "libresoc.v:102740.3-102764.6" + process $proc$libresoc.v:102740$4114 assign { } { } assign { } { } assign $0\dec31_dec_sub20_lk[0:0] $1\dec31_dec_sub20_lk[0:0] - attribute \src "libresoc.v:102677.5-102677.29" + attribute \src "libresoc.v:102741.5-102741.29" switch \initial - attribute \src "libresoc.v:102677.9-102677.17" + attribute \src "libresoc.v:102741.9-102741.17" case 1'1 case end @@ -160226,14 +160277,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_lk $0\dec31_dec_sub20_lk[0:0] end - attribute \src "libresoc.v:102701.3-102725.6" - process $proc$libresoc.v:102701$4115 + attribute \src "libresoc.v:102765.3-102789.6" + process $proc$libresoc.v:102765$4115 assign { } { } assign { } { } assign $0\dec31_dec_sub20_sgl_pipe[0:0] $1\dec31_dec_sub20_sgl_pipe[0:0] - attribute \src "libresoc.v:102702.5-102702.29" + attribute \src "libresoc.v:102766.5-102766.29" switch \initial - attribute \src "libresoc.v:102702.9-102702.17" + attribute \src "libresoc.v:102766.9-102766.17" case 1'1 case end @@ -160269,14 +160320,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_sgl_pipe $0\dec31_dec_sub20_sgl_pipe[0:0] end - attribute \src "libresoc.v:102726.3-102750.6" - process $proc$libresoc.v:102726$4116 + attribute \src "libresoc.v:102790.3-102814.6" + process $proc$libresoc.v:102790$4116 assign { } { } assign { } { } assign $0\dec31_dec_sub20_SV_Etype[1:0] $1\dec31_dec_sub20_SV_Etype[1:0] - attribute \src "libresoc.v:102727.5-102727.29" + attribute \src "libresoc.v:102791.5-102791.29" switch \initial - attribute \src "libresoc.v:102727.9-102727.17" + attribute \src "libresoc.v:102791.9-102791.17" case 1'1 case end @@ -160312,14 +160363,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_SV_Etype $0\dec31_dec_sub20_SV_Etype[1:0] end - attribute \src "libresoc.v:102751.3-102775.6" - process $proc$libresoc.v:102751$4117 + attribute \src "libresoc.v:102815.3-102839.6" + process $proc$libresoc.v:102815$4117 assign { } { } assign { } { } assign $0\dec31_dec_sub20_SV_Ptype[1:0] $1\dec31_dec_sub20_SV_Ptype[1:0] - attribute \src "libresoc.v:102752.5-102752.29" + attribute \src "libresoc.v:102816.5-102816.29" switch \initial - attribute \src "libresoc.v:102752.9-102752.17" + attribute \src "libresoc.v:102816.9-102816.17" case 1'1 case end @@ -160355,14 +160406,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_SV_Ptype $0\dec31_dec_sub20_SV_Ptype[1:0] end - attribute \src "libresoc.v:102776.3-102800.6" - process $proc$libresoc.v:102776$4118 + attribute \src "libresoc.v:102840.3-102864.6" + process $proc$libresoc.v:102840$4118 assign { } { } assign { } { } assign $0\dec31_dec_sub20_in1_sel[2:0] $1\dec31_dec_sub20_in1_sel[2:0] - attribute \src "libresoc.v:102777.5-102777.29" + attribute \src "libresoc.v:102841.5-102841.29" switch \initial - attribute \src "libresoc.v:102777.9-102777.17" + attribute \src "libresoc.v:102841.9-102841.17" case 1'1 case end @@ -160398,14 +160449,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_in1_sel $0\dec31_dec_sub20_in1_sel[2:0] end - attribute \src "libresoc.v:102801.3-102825.6" - process $proc$libresoc.v:102801$4119 + attribute \src "libresoc.v:102865.3-102889.6" + process $proc$libresoc.v:102865$4119 assign { } { } assign { } { } assign $0\dec31_dec_sub20_in2_sel[3:0] $1\dec31_dec_sub20_in2_sel[3:0] - attribute \src "libresoc.v:102802.5-102802.29" + attribute \src "libresoc.v:102866.5-102866.29" switch \initial - attribute \src "libresoc.v:102802.9-102802.17" + attribute \src "libresoc.v:102866.9-102866.17" case 1'1 case end @@ -160441,14 +160492,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_in2_sel $0\dec31_dec_sub20_in2_sel[3:0] end - attribute \src "libresoc.v:102826.3-102850.6" - process $proc$libresoc.v:102826$4120 + attribute \src "libresoc.v:102890.3-102914.6" + process $proc$libresoc.v:102890$4120 assign { } { } assign { } { } assign $0\dec31_dec_sub20_in3_sel[1:0] $1\dec31_dec_sub20_in3_sel[1:0] - attribute \src "libresoc.v:102827.5-102827.29" + attribute \src "libresoc.v:102891.5-102891.29" switch \initial - attribute \src "libresoc.v:102827.9-102827.17" + attribute \src "libresoc.v:102891.9-102891.17" case 1'1 case end @@ -160484,14 +160535,14 @@ module \dec31_dec_sub20 sync always update \dec31_dec_sub20_in3_sel $0\dec31_dec_sub20_in3_sel[1:0] end - attribute \src "libresoc.v:102851.3-102875.6" - process $proc$libresoc.v:102851$4121 + attribute \src "libresoc.v:102915.3-102939.6" + process $proc$libresoc.v:102915$4121 assign { } { } assign { } { } assign $0\dec31_dec_sub20_out_sel[2:0] $1\dec31_dec_sub20_out_sel[2:0] - attribute \src "libresoc.v:102852.5-102852.29" + attribute \src "libresoc.v:102916.5-102916.29" switch \initial - attribute \src "libresoc.v:102852.9-102852.17" + attribute \src "libresoc.v:102916.9-102916.17" case 1'1 case end @@ -160529,144 +160580,144 @@ module \dec31_dec_sub20 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:102881.1-104830.10" +attribute \src "libresoc.v:102945.1-104906.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub21" attribute \generator "nMigen" module \dec31_dec_sub21 - attribute \src "libresoc.v:104535.3-104583.6" + attribute \src "libresoc.v:104611.3-104659.6" wire width 2 $0\dec31_dec_sub21_SV_Etype[1:0] - attribute \src "libresoc.v:104584.3-104632.6" + attribute \src "libresoc.v:104660.3-104708.6" wire width 2 $0\dec31_dec_sub21_SV_Ptype[1:0] - attribute \src "libresoc.v:104504.3-104534.6" + attribute \src "libresoc.v:104568.3-104610.6" wire width 8 $0\dec31_dec_sub21_asmcode[7:0] - attribute \src "libresoc.v:104112.3-104160.6" + attribute \src "libresoc.v:104176.3-104224.6" wire $0\dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:103279.3-103327.6" + attribute \src "libresoc.v:103343.3-103391.6" wire width 3 $0\dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:103328.3-103376.6" + attribute \src "libresoc.v:103392.3-103440.6" wire width 3 $0\dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:103916.3-103964.6" + attribute \src "libresoc.v:103980.3-104028.6" wire width 2 $0\dec31_dec_sub21_cry_in[1:0] - attribute \src "libresoc.v:104063.3-104111.6" + attribute \src "libresoc.v:104127.3-104175.6" wire $0\dec31_dec_sub21_cry_out[0:0] - attribute \src "libresoc.v:104308.3-104356.6" + attribute \src "libresoc.v:104372.3-104420.6" wire width 5 $0\dec31_dec_sub21_form[4:0] - attribute \src "libresoc.v:103230.3-103278.6" + attribute \src "libresoc.v:103294.3-103342.6" wire width 14 $0\dec31_dec_sub21_function_unit[13:0] - attribute \src "libresoc.v:104633.3-104681.6" + attribute \src "libresoc.v:104709.3-104757.6" wire width 3 $0\dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:104682.3-104730.6" + attribute \src "libresoc.v:104758.3-104806.6" wire width 4 $0\dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:104731.3-104779.6" + attribute \src "libresoc.v:104807.3-104855.6" wire width 2 $0\dec31_dec_sub21_in3_sel[1:0] - attribute \src "libresoc.v:103769.3-103817.6" + attribute \src "libresoc.v:103833.3-103881.6" wire width 7 $0\dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:103965.3-104013.6" + attribute \src "libresoc.v:104029.3-104077.6" wire $0\dec31_dec_sub21_inv_a[0:0] - attribute \src "libresoc.v:104014.3-104062.6" + attribute \src "libresoc.v:104078.3-104126.6" wire $0\dec31_dec_sub21_inv_out[0:0] - attribute \src "libresoc.v:104259.3-104307.6" + attribute \src "libresoc.v:104323.3-104371.6" wire $0\dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:103720.3-103768.6" + attribute \src "libresoc.v:103784.3-103832.6" wire width 4 $0\dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:104406.3-104454.6" + attribute \src "libresoc.v:104470.3-104518.6" wire $0\dec31_dec_sub21_lk[0:0] - attribute \src "libresoc.v:104780.3-104828.6" + attribute \src "libresoc.v:104856.3-104904.6" wire width 3 $0\dec31_dec_sub21_out_sel[2:0] - attribute \src "libresoc.v:103867.3-103915.6" + attribute \src "libresoc.v:103931.3-103979.6" wire width 2 $0\dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:104210.3-104258.6" + attribute \src "libresoc.v:104274.3-104322.6" wire $0\dec31_dec_sub21_rsrv[0:0] - attribute \src "libresoc.v:104455.3-104503.6" + attribute \src "libresoc.v:104519.3-104567.6" wire $0\dec31_dec_sub21_sgl_pipe[0:0] - attribute \src "libresoc.v:104357.3-104405.6" + attribute \src "libresoc.v:104421.3-104469.6" wire $0\dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:104161.3-104209.6" + attribute \src "libresoc.v:104225.3-104273.6" wire $0\dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:103622.3-103670.6" + attribute \src "libresoc.v:103686.3-103734.6" wire width 3 $0\dec31_dec_sub21_sv_cr_in[2:0] - attribute \src "libresoc.v:103671.3-103719.6" + attribute \src "libresoc.v:103735.3-103783.6" wire width 3 $0\dec31_dec_sub21_sv_cr_out[2:0] - attribute \src "libresoc.v:103377.3-103425.6" + attribute \src "libresoc.v:103441.3-103489.6" wire width 3 $0\dec31_dec_sub21_sv_in1[2:0] - attribute \src "libresoc.v:103426.3-103474.6" + attribute \src "libresoc.v:103490.3-103538.6" wire width 3 $0\dec31_dec_sub21_sv_in2[2:0] - attribute \src "libresoc.v:103475.3-103523.6" + attribute \src "libresoc.v:103539.3-103587.6" wire width 3 $0\dec31_dec_sub21_sv_in3[2:0] - attribute \src "libresoc.v:103573.3-103621.6" + attribute \src "libresoc.v:103637.3-103685.6" wire width 3 $0\dec31_dec_sub21_sv_out2[2:0] - attribute \src "libresoc.v:103524.3-103572.6" + attribute \src "libresoc.v:103588.3-103636.6" wire width 3 $0\dec31_dec_sub21_sv_out[2:0] - attribute \src "libresoc.v:103818.3-103866.6" + attribute \src "libresoc.v:103882.3-103930.6" wire width 2 $0\dec31_dec_sub21_upd[1:0] - attribute \src "libresoc.v:102882.7-102882.20" + attribute \src "libresoc.v:102946.7-102946.20" wire $0\initial[0:0] - attribute \src "libresoc.v:104535.3-104583.6" + attribute \src "libresoc.v:104611.3-104659.6" wire width 2 $1\dec31_dec_sub21_SV_Etype[1:0] - attribute \src "libresoc.v:104584.3-104632.6" + attribute \src "libresoc.v:104660.3-104708.6" wire width 2 $1\dec31_dec_sub21_SV_Ptype[1:0] - attribute \src "libresoc.v:104504.3-104534.6" + attribute \src "libresoc.v:104568.3-104610.6" wire width 8 $1\dec31_dec_sub21_asmcode[7:0] - attribute \src "libresoc.v:104112.3-104160.6" + attribute \src "libresoc.v:104176.3-104224.6" wire $1\dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:103279.3-103327.6" + attribute \src "libresoc.v:103343.3-103391.6" wire width 3 $1\dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:103328.3-103376.6" + attribute \src "libresoc.v:103392.3-103440.6" wire width 3 $1\dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:103916.3-103964.6" + attribute \src "libresoc.v:103980.3-104028.6" wire width 2 $1\dec31_dec_sub21_cry_in[1:0] - attribute \src "libresoc.v:104063.3-104111.6" + attribute \src "libresoc.v:104127.3-104175.6" wire $1\dec31_dec_sub21_cry_out[0:0] - attribute \src "libresoc.v:104308.3-104356.6" + attribute \src "libresoc.v:104372.3-104420.6" wire width 5 $1\dec31_dec_sub21_form[4:0] - attribute \src "libresoc.v:103230.3-103278.6" + attribute \src "libresoc.v:103294.3-103342.6" wire width 14 $1\dec31_dec_sub21_function_unit[13:0] - attribute \src "libresoc.v:104633.3-104681.6" + attribute \src "libresoc.v:104709.3-104757.6" wire width 3 $1\dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:104682.3-104730.6" + attribute \src "libresoc.v:104758.3-104806.6" wire width 4 $1\dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:104731.3-104779.6" + attribute \src "libresoc.v:104807.3-104855.6" wire width 2 $1\dec31_dec_sub21_in3_sel[1:0] - attribute \src "libresoc.v:103769.3-103817.6" + attribute \src "libresoc.v:103833.3-103881.6" wire width 7 $1\dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:103965.3-104013.6" + attribute \src "libresoc.v:104029.3-104077.6" wire $1\dec31_dec_sub21_inv_a[0:0] - attribute \src "libresoc.v:104014.3-104062.6" + attribute \src "libresoc.v:104078.3-104126.6" wire $1\dec31_dec_sub21_inv_out[0:0] - attribute \src "libresoc.v:104259.3-104307.6" + attribute \src "libresoc.v:104323.3-104371.6" wire $1\dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:103720.3-103768.6" + attribute \src "libresoc.v:103784.3-103832.6" wire width 4 $1\dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:104406.3-104454.6" + attribute \src "libresoc.v:104470.3-104518.6" wire $1\dec31_dec_sub21_lk[0:0] - attribute \src "libresoc.v:104780.3-104828.6" + attribute \src "libresoc.v:104856.3-104904.6" wire width 3 $1\dec31_dec_sub21_out_sel[2:0] - attribute \src "libresoc.v:103867.3-103915.6" + attribute \src "libresoc.v:103931.3-103979.6" wire width 2 $1\dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:104210.3-104258.6" + attribute \src "libresoc.v:104274.3-104322.6" wire $1\dec31_dec_sub21_rsrv[0:0] - attribute \src "libresoc.v:104455.3-104503.6" + attribute \src "libresoc.v:104519.3-104567.6" wire $1\dec31_dec_sub21_sgl_pipe[0:0] - attribute \src "libresoc.v:104357.3-104405.6" + attribute \src "libresoc.v:104421.3-104469.6" wire $1\dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:104161.3-104209.6" + attribute \src "libresoc.v:104225.3-104273.6" wire $1\dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:103622.3-103670.6" + attribute \src "libresoc.v:103686.3-103734.6" wire width 3 $1\dec31_dec_sub21_sv_cr_in[2:0] - attribute \src "libresoc.v:103671.3-103719.6" + attribute \src "libresoc.v:103735.3-103783.6" wire width 3 $1\dec31_dec_sub21_sv_cr_out[2:0] - attribute \src "libresoc.v:103377.3-103425.6" + attribute \src "libresoc.v:103441.3-103489.6" wire width 3 $1\dec31_dec_sub21_sv_in1[2:0] - attribute \src "libresoc.v:103426.3-103474.6" + attribute \src "libresoc.v:103490.3-103538.6" wire width 3 $1\dec31_dec_sub21_sv_in2[2:0] - attribute \src "libresoc.v:103475.3-103523.6" + attribute \src "libresoc.v:103539.3-103587.6" wire width 3 $1\dec31_dec_sub21_sv_in3[2:0] - attribute \src "libresoc.v:103573.3-103621.6" + attribute \src "libresoc.v:103637.3-103685.6" wire width 3 $1\dec31_dec_sub21_sv_out2[2:0] - attribute \src "libresoc.v:103524.3-103572.6" + attribute \src "libresoc.v:103588.3-103636.6" wire width 3 $1\dec31_dec_sub21_sv_out[2:0] - attribute \src "libresoc.v:103818.3-103866.6" + attribute \src "libresoc.v:103882.3-103930.6" wire width 2 $1\dec31_dec_sub21_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -160978,28 +161029,28 @@ module \dec31_dec_sub21 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub21_upd - attribute \src "libresoc.v:102882.7-102882.15" + attribute \src "libresoc.v:102946.7-102946.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:102882.7-102882.20" - process $proc$libresoc.v:102882$4156 + attribute \src "libresoc.v:102946.7-102946.20" + process $proc$libresoc.v:102946$4156 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:103230.3-103278.6" - process $proc$libresoc.v:103230$4123 + attribute \src "libresoc.v:103294.3-103342.6" + process $proc$libresoc.v:103294$4123 assign { } { } assign { } { } assign $0\dec31_dec_sub21_function_unit[13:0] $1\dec31_dec_sub21_function_unit[13:0] - attribute \src "libresoc.v:103231.5-103231.29" + attribute \src "libresoc.v:103295.5-103295.29" switch \initial - attribute \src "libresoc.v:103231.9-103231.17" + attribute \src "libresoc.v:103295.9-103295.17" case 1'1 case end @@ -161067,14 +161118,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_function_unit $0\dec31_dec_sub21_function_unit[13:0] end - attribute \src "libresoc.v:103279.3-103327.6" - process $proc$libresoc.v:103279$4124 + attribute \src "libresoc.v:103343.3-103391.6" + process $proc$libresoc.v:103343$4124 assign { } { } assign { } { } assign $0\dec31_dec_sub21_cr_in[2:0] $1\dec31_dec_sub21_cr_in[2:0] - attribute \src "libresoc.v:103280.5-103280.29" + attribute \src "libresoc.v:103344.5-103344.29" switch \initial - attribute \src "libresoc.v:103280.9-103280.17" + attribute \src "libresoc.v:103344.9-103344.17" case 1'1 case end @@ -161142,14 +161193,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_cr_in $0\dec31_dec_sub21_cr_in[2:0] end - attribute \src "libresoc.v:103328.3-103376.6" - process $proc$libresoc.v:103328$4125 + attribute \src "libresoc.v:103392.3-103440.6" + process $proc$libresoc.v:103392$4125 assign { } { } assign { } { } assign $0\dec31_dec_sub21_cr_out[2:0] $1\dec31_dec_sub21_cr_out[2:0] - attribute \src "libresoc.v:103329.5-103329.29" + attribute \src "libresoc.v:103393.5-103393.29" switch \initial - attribute \src "libresoc.v:103329.9-103329.17" + attribute \src "libresoc.v:103393.9-103393.17" case 1'1 case end @@ -161217,14 +161268,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_cr_out $0\dec31_dec_sub21_cr_out[2:0] end - attribute \src "libresoc.v:103377.3-103425.6" - process $proc$libresoc.v:103377$4126 + attribute \src "libresoc.v:103441.3-103489.6" + process $proc$libresoc.v:103441$4126 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_in1[2:0] $1\dec31_dec_sub21_sv_in1[2:0] - attribute \src "libresoc.v:103378.5-103378.29" + attribute \src "libresoc.v:103442.5-103442.29" switch \initial - attribute \src "libresoc.v:103378.9-103378.17" + attribute \src "libresoc.v:103442.9-103442.17" case 1'1 case end @@ -161292,14 +161343,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_in1 $0\dec31_dec_sub21_sv_in1[2:0] end - attribute \src "libresoc.v:103426.3-103474.6" - process $proc$libresoc.v:103426$4127 + attribute \src "libresoc.v:103490.3-103538.6" + process $proc$libresoc.v:103490$4127 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_in2[2:0] $1\dec31_dec_sub21_sv_in2[2:0] - attribute \src "libresoc.v:103427.5-103427.29" + attribute \src "libresoc.v:103491.5-103491.29" switch \initial - attribute \src "libresoc.v:103427.9-103427.17" + attribute \src "libresoc.v:103491.9-103491.17" case 1'1 case end @@ -161367,14 +161418,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_in2 $0\dec31_dec_sub21_sv_in2[2:0] end - attribute \src "libresoc.v:103475.3-103523.6" - process $proc$libresoc.v:103475$4128 + attribute \src "libresoc.v:103539.3-103587.6" + process $proc$libresoc.v:103539$4128 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_in3[2:0] $1\dec31_dec_sub21_sv_in3[2:0] - attribute \src "libresoc.v:103476.5-103476.29" + attribute \src "libresoc.v:103540.5-103540.29" switch \initial - attribute \src "libresoc.v:103476.9-103476.17" + attribute \src "libresoc.v:103540.9-103540.17" case 1'1 case end @@ -161442,14 +161493,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_in3 $0\dec31_dec_sub21_sv_in3[2:0] end - attribute \src "libresoc.v:103524.3-103572.6" - process $proc$libresoc.v:103524$4129 + attribute \src "libresoc.v:103588.3-103636.6" + process $proc$libresoc.v:103588$4129 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_out[2:0] $1\dec31_dec_sub21_sv_out[2:0] - attribute \src "libresoc.v:103525.5-103525.29" + attribute \src "libresoc.v:103589.5-103589.29" switch \initial - attribute \src "libresoc.v:103525.9-103525.17" + attribute \src "libresoc.v:103589.9-103589.17" case 1'1 case end @@ -161517,14 +161568,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_out $0\dec31_dec_sub21_sv_out[2:0] end - attribute \src "libresoc.v:103573.3-103621.6" - process $proc$libresoc.v:103573$4130 + attribute \src "libresoc.v:103637.3-103685.6" + process $proc$libresoc.v:103637$4130 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_out2[2:0] $1\dec31_dec_sub21_sv_out2[2:0] - attribute \src "libresoc.v:103574.5-103574.29" + attribute \src "libresoc.v:103638.5-103638.29" switch \initial - attribute \src "libresoc.v:103574.9-103574.17" + attribute \src "libresoc.v:103638.9-103638.17" case 1'1 case end @@ -161592,14 +161643,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_out2 $0\dec31_dec_sub21_sv_out2[2:0] end - attribute \src "libresoc.v:103622.3-103670.6" - process $proc$libresoc.v:103622$4131 + attribute \src "libresoc.v:103686.3-103734.6" + process $proc$libresoc.v:103686$4131 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_cr_in[2:0] $1\dec31_dec_sub21_sv_cr_in[2:0] - attribute \src "libresoc.v:103623.5-103623.29" + attribute \src "libresoc.v:103687.5-103687.29" switch \initial - attribute \src "libresoc.v:103623.9-103623.17" + attribute \src "libresoc.v:103687.9-103687.17" case 1'1 case end @@ -161667,14 +161718,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_cr_in $0\dec31_dec_sub21_sv_cr_in[2:0] end - attribute \src "libresoc.v:103671.3-103719.6" - process $proc$libresoc.v:103671$4132 + attribute \src "libresoc.v:103735.3-103783.6" + process $proc$libresoc.v:103735$4132 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sv_cr_out[2:0] $1\dec31_dec_sub21_sv_cr_out[2:0] - attribute \src "libresoc.v:103672.5-103672.29" + attribute \src "libresoc.v:103736.5-103736.29" switch \initial - attribute \src "libresoc.v:103672.9-103672.17" + attribute \src "libresoc.v:103736.9-103736.17" case 1'1 case end @@ -161742,14 +161793,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sv_cr_out $0\dec31_dec_sub21_sv_cr_out[2:0] end - attribute \src "libresoc.v:103720.3-103768.6" - process $proc$libresoc.v:103720$4133 + attribute \src "libresoc.v:103784.3-103832.6" + process $proc$libresoc.v:103784$4133 assign { } { } assign { } { } assign $0\dec31_dec_sub21_ldst_len[3:0] $1\dec31_dec_sub21_ldst_len[3:0] - attribute \src "libresoc.v:103721.5-103721.29" + attribute \src "libresoc.v:103785.5-103785.29" switch \initial - attribute \src "libresoc.v:103721.9-103721.17" + attribute \src "libresoc.v:103785.9-103785.17" case 1'1 case end @@ -161817,14 +161868,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_ldst_len $0\dec31_dec_sub21_ldst_len[3:0] end - attribute \src "libresoc.v:103769.3-103817.6" - process $proc$libresoc.v:103769$4134 + attribute \src "libresoc.v:103833.3-103881.6" + process $proc$libresoc.v:103833$4134 assign { } { } assign { } { } assign $0\dec31_dec_sub21_internal_op[6:0] $1\dec31_dec_sub21_internal_op[6:0] - attribute \src "libresoc.v:103770.5-103770.29" + attribute \src "libresoc.v:103834.5-103834.29" switch \initial - attribute \src "libresoc.v:103770.9-103770.17" + attribute \src "libresoc.v:103834.9-103834.17" case 1'1 case end @@ -161892,14 +161943,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_internal_op $0\dec31_dec_sub21_internal_op[6:0] end - attribute \src "libresoc.v:103818.3-103866.6" - process $proc$libresoc.v:103818$4135 + attribute \src "libresoc.v:103882.3-103930.6" + process $proc$libresoc.v:103882$4135 assign { } { } assign { } { } assign $0\dec31_dec_sub21_upd[1:0] $1\dec31_dec_sub21_upd[1:0] - attribute \src "libresoc.v:103819.5-103819.29" + attribute \src "libresoc.v:103883.5-103883.29" switch \initial - attribute \src "libresoc.v:103819.9-103819.17" + attribute \src "libresoc.v:103883.9-103883.17" case 1'1 case end @@ -161967,14 +162018,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_upd $0\dec31_dec_sub21_upd[1:0] end - attribute \src "libresoc.v:103867.3-103915.6" - process $proc$libresoc.v:103867$4136 + attribute \src "libresoc.v:103931.3-103979.6" + process $proc$libresoc.v:103931$4136 assign { } { } assign { } { } assign $0\dec31_dec_sub21_rc_sel[1:0] $1\dec31_dec_sub21_rc_sel[1:0] - attribute \src "libresoc.v:103868.5-103868.29" + attribute \src "libresoc.v:103932.5-103932.29" switch \initial - attribute \src "libresoc.v:103868.9-103868.17" + attribute \src "libresoc.v:103932.9-103932.17" case 1'1 case end @@ -162042,14 +162093,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_rc_sel $0\dec31_dec_sub21_rc_sel[1:0] end - attribute \src "libresoc.v:103916.3-103964.6" - process $proc$libresoc.v:103916$4137 + attribute \src "libresoc.v:103980.3-104028.6" + process $proc$libresoc.v:103980$4137 assign { } { } assign { } { } assign $0\dec31_dec_sub21_cry_in[1:0] $1\dec31_dec_sub21_cry_in[1:0] - attribute \src "libresoc.v:103917.5-103917.29" + attribute \src "libresoc.v:103981.5-103981.29" switch \initial - attribute \src "libresoc.v:103917.9-103917.17" + attribute \src "libresoc.v:103981.9-103981.17" case 1'1 case end @@ -162117,14 +162168,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_cry_in $0\dec31_dec_sub21_cry_in[1:0] end - attribute \src "libresoc.v:103965.3-104013.6" - process $proc$libresoc.v:103965$4138 + attribute \src "libresoc.v:104029.3-104077.6" + process $proc$libresoc.v:104029$4138 assign { } { } assign { } { } assign $0\dec31_dec_sub21_inv_a[0:0] $1\dec31_dec_sub21_inv_a[0:0] - attribute \src "libresoc.v:103966.5-103966.29" + attribute \src "libresoc.v:104030.5-104030.29" switch \initial - attribute \src "libresoc.v:103966.9-103966.17" + attribute \src "libresoc.v:104030.9-104030.17" case 1'1 case end @@ -162192,14 +162243,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_inv_a $0\dec31_dec_sub21_inv_a[0:0] end - attribute \src "libresoc.v:104014.3-104062.6" - process $proc$libresoc.v:104014$4139 + attribute \src "libresoc.v:104078.3-104126.6" + process $proc$libresoc.v:104078$4139 assign { } { } assign { } { } assign $0\dec31_dec_sub21_inv_out[0:0] $1\dec31_dec_sub21_inv_out[0:0] - attribute \src "libresoc.v:104015.5-104015.29" + attribute \src "libresoc.v:104079.5-104079.29" switch \initial - attribute \src "libresoc.v:104015.9-104015.17" + attribute \src "libresoc.v:104079.9-104079.17" case 1'1 case end @@ -162267,14 +162318,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_inv_out $0\dec31_dec_sub21_inv_out[0:0] end - attribute \src "libresoc.v:104063.3-104111.6" - process $proc$libresoc.v:104063$4140 + attribute \src "libresoc.v:104127.3-104175.6" + process $proc$libresoc.v:104127$4140 assign { } { } assign { } { } assign $0\dec31_dec_sub21_cry_out[0:0] $1\dec31_dec_sub21_cry_out[0:0] - attribute \src "libresoc.v:104064.5-104064.29" + attribute \src "libresoc.v:104128.5-104128.29" switch \initial - attribute \src "libresoc.v:104064.9-104064.17" + attribute \src "libresoc.v:104128.9-104128.17" case 1'1 case end @@ -162342,14 +162393,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_cry_out $0\dec31_dec_sub21_cry_out[0:0] end - attribute \src "libresoc.v:104112.3-104160.6" - process $proc$libresoc.v:104112$4141 + attribute \src "libresoc.v:104176.3-104224.6" + process $proc$libresoc.v:104176$4141 assign { } { } assign { } { } assign $0\dec31_dec_sub21_br[0:0] $1\dec31_dec_sub21_br[0:0] - attribute \src "libresoc.v:104113.5-104113.29" + attribute \src "libresoc.v:104177.5-104177.29" switch \initial - attribute \src "libresoc.v:104113.9-104113.17" + attribute \src "libresoc.v:104177.9-104177.17" case 1'1 case end @@ -162417,14 +162468,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_br $0\dec31_dec_sub21_br[0:0] end - attribute \src "libresoc.v:104161.3-104209.6" - process $proc$libresoc.v:104161$4142 + attribute \src "libresoc.v:104225.3-104273.6" + process $proc$libresoc.v:104225$4142 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sgn_ext[0:0] $1\dec31_dec_sub21_sgn_ext[0:0] - attribute \src "libresoc.v:104162.5-104162.29" + attribute \src "libresoc.v:104226.5-104226.29" switch \initial - attribute \src "libresoc.v:104162.9-104162.17" + attribute \src "libresoc.v:104226.9-104226.17" case 1'1 case end @@ -162492,14 +162543,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sgn_ext $0\dec31_dec_sub21_sgn_ext[0:0] end - attribute \src "libresoc.v:104210.3-104258.6" - process $proc$libresoc.v:104210$4143 + attribute \src "libresoc.v:104274.3-104322.6" + process $proc$libresoc.v:104274$4143 assign { } { } assign { } { } assign $0\dec31_dec_sub21_rsrv[0:0] $1\dec31_dec_sub21_rsrv[0:0] - attribute \src "libresoc.v:104211.5-104211.29" + attribute \src "libresoc.v:104275.5-104275.29" switch \initial - attribute \src "libresoc.v:104211.9-104211.17" + attribute \src "libresoc.v:104275.9-104275.17" case 1'1 case end @@ -162567,14 +162618,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_rsrv $0\dec31_dec_sub21_rsrv[0:0] end - attribute \src "libresoc.v:104259.3-104307.6" - process $proc$libresoc.v:104259$4144 + attribute \src "libresoc.v:104323.3-104371.6" + process $proc$libresoc.v:104323$4144 assign { } { } assign { } { } assign $0\dec31_dec_sub21_is_32b[0:0] $1\dec31_dec_sub21_is_32b[0:0] - attribute \src "libresoc.v:104260.5-104260.29" + attribute \src "libresoc.v:104324.5-104324.29" switch \initial - attribute \src "libresoc.v:104260.9-104260.17" + attribute \src "libresoc.v:104324.9-104324.17" case 1'1 case end @@ -162642,14 +162693,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_is_32b $0\dec31_dec_sub21_is_32b[0:0] end - attribute \src "libresoc.v:104308.3-104356.6" - process $proc$libresoc.v:104308$4145 + attribute \src "libresoc.v:104372.3-104420.6" + process $proc$libresoc.v:104372$4145 assign { } { } assign { } { } assign $0\dec31_dec_sub21_form[4:0] $1\dec31_dec_sub21_form[4:0] - attribute \src "libresoc.v:104309.5-104309.29" + attribute \src "libresoc.v:104373.5-104373.29" switch \initial - attribute \src "libresoc.v:104309.9-104309.17" + attribute \src "libresoc.v:104373.9-104373.17" case 1'1 case end @@ -162717,14 +162768,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_form $0\dec31_dec_sub21_form[4:0] end - attribute \src "libresoc.v:104357.3-104405.6" - process $proc$libresoc.v:104357$4146 + attribute \src "libresoc.v:104421.3-104469.6" + process $proc$libresoc.v:104421$4146 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sgn[0:0] $1\dec31_dec_sub21_sgn[0:0] - attribute \src "libresoc.v:104358.5-104358.29" + attribute \src "libresoc.v:104422.5-104422.29" switch \initial - attribute \src "libresoc.v:104358.9-104358.17" + attribute \src "libresoc.v:104422.9-104422.17" case 1'1 case end @@ -162792,14 +162843,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sgn $0\dec31_dec_sub21_sgn[0:0] end - attribute \src "libresoc.v:104406.3-104454.6" - process $proc$libresoc.v:104406$4147 + attribute \src "libresoc.v:104470.3-104518.6" + process $proc$libresoc.v:104470$4147 assign { } { } assign { } { } assign $0\dec31_dec_sub21_lk[0:0] $1\dec31_dec_sub21_lk[0:0] - attribute \src "libresoc.v:104407.5-104407.29" + attribute \src "libresoc.v:104471.5-104471.29" switch \initial - attribute \src "libresoc.v:104407.9-104407.17" + attribute \src "libresoc.v:104471.9-104471.17" case 1'1 case end @@ -162867,14 +162918,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_lk $0\dec31_dec_sub21_lk[0:0] end - attribute \src "libresoc.v:104455.3-104503.6" - process $proc$libresoc.v:104455$4148 + attribute \src "libresoc.v:104519.3-104567.6" + process $proc$libresoc.v:104519$4148 assign { } { } assign { } { } assign $0\dec31_dec_sub21_sgl_pipe[0:0] $1\dec31_dec_sub21_sgl_pipe[0:0] - attribute \src "libresoc.v:104456.5-104456.29" + attribute \src "libresoc.v:104520.5-104520.29" switch \initial - attribute \src "libresoc.v:104456.9-104456.17" + attribute \src "libresoc.v:104520.9-104520.17" case 1'1 case end @@ -162942,20 +162993,26 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_sgl_pipe $0\dec31_dec_sub21_sgl_pipe[0:0] end - attribute \src "libresoc.v:104504.3-104534.6" - process $proc$libresoc.v:104504$4149 + attribute \src "libresoc.v:104568.3-104610.6" + process $proc$libresoc.v:104568$4149 assign { } { } assign { } { } assign $0\dec31_dec_sub21_asmcode[7:0] $1\dec31_dec_sub21_asmcode[7:0] - attribute \src "libresoc.v:104505.5-104505.29" + attribute \src "libresoc.v:104569.5-104569.29" switch \initial - attribute \src "libresoc.v:104505.9-104505.17" + attribute \src "libresoc.v:104569.9-104569.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" switch \opcode_switch attribute \src "libresoc.v:0.0-0.0" + case 5'11010 + assign $1\dec31_dec_sub21_asmcode[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 5'11011 + assign $1\dec31_dec_sub21_asmcode[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" case 5'00001 assign { } { } assign $1\dec31_dec_sub21_asmcode[7:0] 8'01010110 @@ -162964,6 +163021,9 @@ module \dec31_dec_sub21 assign { } { } assign $1\dec31_dec_sub21_asmcode[7:0] 8'01010111 attribute \src "libresoc.v:0.0-0.0" + case 5'11001 + assign $1\dec31_dec_sub21_asmcode[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" case 5'01011 assign { } { } assign $1\dec31_dec_sub21_asmcode[7:0] 8'01100100 @@ -162980,6 +163040,9 @@ module \dec31_dec_sub21 assign { } { } assign $1\dec31_dec_sub21_asmcode[7:0] 8'10101000 attribute \src "libresoc.v:0.0-0.0" + case 5'11111 + assign $1\dec31_dec_sub21_asmcode[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" case 5'00101 assign { } { } assign $1\dec31_dec_sub21_asmcode[7:0] 8'10110001 @@ -162993,14 +163056,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_asmcode $0\dec31_dec_sub21_asmcode[7:0] end - attribute \src "libresoc.v:104535.3-104583.6" - process $proc$libresoc.v:104535$4150 + attribute \src "libresoc.v:104611.3-104659.6" + process $proc$libresoc.v:104611$4150 assign { } { } assign { } { } assign $0\dec31_dec_sub21_SV_Etype[1:0] $1\dec31_dec_sub21_SV_Etype[1:0] - attribute \src "libresoc.v:104536.5-104536.29" + attribute \src "libresoc.v:104612.5-104612.29" switch \initial - attribute \src "libresoc.v:104536.9-104536.17" + attribute \src "libresoc.v:104612.9-104612.17" case 1'1 case end @@ -163068,14 +163131,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_SV_Etype $0\dec31_dec_sub21_SV_Etype[1:0] end - attribute \src "libresoc.v:104584.3-104632.6" - process $proc$libresoc.v:104584$4151 + attribute \src "libresoc.v:104660.3-104708.6" + process $proc$libresoc.v:104660$4151 assign { } { } assign { } { } assign $0\dec31_dec_sub21_SV_Ptype[1:0] $1\dec31_dec_sub21_SV_Ptype[1:0] - attribute \src "libresoc.v:104585.5-104585.29" + attribute \src "libresoc.v:104661.5-104661.29" switch \initial - attribute \src "libresoc.v:104585.9-104585.17" + attribute \src "libresoc.v:104661.9-104661.17" case 1'1 case end @@ -163143,14 +163206,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_SV_Ptype $0\dec31_dec_sub21_SV_Ptype[1:0] end - attribute \src "libresoc.v:104633.3-104681.6" - process $proc$libresoc.v:104633$4152 + attribute \src "libresoc.v:104709.3-104757.6" + process $proc$libresoc.v:104709$4152 assign { } { } assign { } { } assign $0\dec31_dec_sub21_in1_sel[2:0] $1\dec31_dec_sub21_in1_sel[2:0] - attribute \src "libresoc.v:104634.5-104634.29" + attribute \src "libresoc.v:104710.5-104710.29" switch \initial - attribute \src "libresoc.v:104634.9-104634.17" + attribute \src "libresoc.v:104710.9-104710.17" case 1'1 case end @@ -163218,14 +163281,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_in1_sel $0\dec31_dec_sub21_in1_sel[2:0] end - attribute \src "libresoc.v:104682.3-104730.6" - process $proc$libresoc.v:104682$4153 + attribute \src "libresoc.v:104758.3-104806.6" + process $proc$libresoc.v:104758$4153 assign { } { } assign { } { } assign $0\dec31_dec_sub21_in2_sel[3:0] $1\dec31_dec_sub21_in2_sel[3:0] - attribute \src "libresoc.v:104683.5-104683.29" + attribute \src "libresoc.v:104759.5-104759.29" switch \initial - attribute \src "libresoc.v:104683.9-104683.17" + attribute \src "libresoc.v:104759.9-104759.17" case 1'1 case end @@ -163293,14 +163356,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_in2_sel $0\dec31_dec_sub21_in2_sel[3:0] end - attribute \src "libresoc.v:104731.3-104779.6" - process $proc$libresoc.v:104731$4154 + attribute \src "libresoc.v:104807.3-104855.6" + process $proc$libresoc.v:104807$4154 assign { } { } assign { } { } assign $0\dec31_dec_sub21_in3_sel[1:0] $1\dec31_dec_sub21_in3_sel[1:0] - attribute \src "libresoc.v:104732.5-104732.29" + attribute \src "libresoc.v:104808.5-104808.29" switch \initial - attribute \src "libresoc.v:104732.9-104732.17" + attribute \src "libresoc.v:104808.9-104808.17" case 1'1 case end @@ -163368,14 +163431,14 @@ module \dec31_dec_sub21 sync always update \dec31_dec_sub21_in3_sel $0\dec31_dec_sub21_in3_sel[1:0] end - attribute \src "libresoc.v:104780.3-104828.6" - process $proc$libresoc.v:104780$4155 + attribute \src "libresoc.v:104856.3-104904.6" + process $proc$libresoc.v:104856$4155 assign { } { } assign { } { } assign $0\dec31_dec_sub21_out_sel[2:0] $1\dec31_dec_sub21_out_sel[2:0] - attribute \src "libresoc.v:104781.5-104781.29" + attribute \src "libresoc.v:104857.5-104857.29" switch \initial - attribute \src "libresoc.v:104781.9-104781.17" + attribute \src "libresoc.v:104857.9-104857.17" case 1'1 case end @@ -163445,144 +163508,144 @@ module \dec31_dec_sub21 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:104834.1-106999.10" +attribute \src "libresoc.v:104910.1-107075.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub22" attribute \generator "nMigen" module \dec31_dec_sub22 - attribute \src "libresoc.v:106668.3-106722.6" + attribute \src "libresoc.v:106744.3-106798.6" wire width 2 $0\dec31_dec_sub22_SV_Etype[1:0] - attribute \src "libresoc.v:106723.3-106777.6" + attribute \src "libresoc.v:106799.3-106853.6" wire width 2 $0\dec31_dec_sub22_SV_Ptype[1:0] - attribute \src "libresoc.v:106008.3-106062.6" + attribute \src "libresoc.v:106084.3-106138.6" wire width 8 $0\dec31_dec_sub22_asmcode[7:0] - attribute \src "libresoc.v:106228.3-106282.6" + attribute \src "libresoc.v:106304.3-106358.6" wire $0\dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:105238.3-105292.6" + attribute \src "libresoc.v:105314.3-105368.6" wire width 3 $0\dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:105293.3-105347.6" + attribute \src "libresoc.v:105369.3-105423.6" wire width 3 $0\dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:105953.3-106007.6" + attribute \src "libresoc.v:106029.3-106083.6" wire width 2 $0\dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:106173.3-106227.6" + attribute \src "libresoc.v:106249.3-106303.6" wire $0\dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:106393.3-106447.6" + attribute \src "libresoc.v:106469.3-106523.6" wire width 5 $0\dec31_dec_sub22_form[4:0] - attribute \src "libresoc.v:105183.3-105237.6" + attribute \src "libresoc.v:105259.3-105313.6" wire width 14 $0\dec31_dec_sub22_function_unit[13:0] - attribute \src "libresoc.v:106778.3-106832.6" + attribute \src "libresoc.v:106854.3-106908.6" wire width 3 $0\dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:106833.3-106887.6" + attribute \src "libresoc.v:106909.3-106963.6" wire width 4 $0\dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:106888.3-106942.6" + attribute \src "libresoc.v:106964.3-107018.6" wire width 2 $0\dec31_dec_sub22_in3_sel[1:0] - attribute \src "libresoc.v:105788.3-105842.6" + attribute \src "libresoc.v:105864.3-105918.6" wire width 7 $0\dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:106063.3-106117.6" + attribute \src "libresoc.v:106139.3-106193.6" wire $0\dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:106118.3-106172.6" + attribute \src "libresoc.v:106194.3-106248.6" wire $0\dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:106448.3-106502.6" + attribute \src "libresoc.v:106524.3-106578.6" wire $0\dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:105733.3-105787.6" + attribute \src "libresoc.v:105809.3-105863.6" wire width 4 $0\dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:106558.3-106612.6" + attribute \src "libresoc.v:106634.3-106688.6" wire $0\dec31_dec_sub22_lk[0:0] - attribute \src "libresoc.v:106943.3-106997.6" + attribute \src "libresoc.v:107019.3-107073.6" wire width 3 $0\dec31_dec_sub22_out_sel[2:0] - attribute \src "libresoc.v:105898.3-105952.6" + attribute \src "libresoc.v:105974.3-106028.6" wire width 2 $0\dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:106338.3-106392.6" + attribute \src "libresoc.v:106414.3-106468.6" wire $0\dec31_dec_sub22_rsrv[0:0] - attribute \src "libresoc.v:106613.3-106667.6" + attribute \src "libresoc.v:106689.3-106743.6" wire $0\dec31_dec_sub22_sgl_pipe[0:0] - attribute \src "libresoc.v:106503.3-106557.6" + attribute \src "libresoc.v:106579.3-106633.6" wire $0\dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:106283.3-106337.6" + attribute \src "libresoc.v:106359.3-106413.6" wire $0\dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:105623.3-105677.6" + attribute \src "libresoc.v:105699.3-105753.6" wire width 3 $0\dec31_dec_sub22_sv_cr_in[2:0] - attribute \src "libresoc.v:105678.3-105732.6" + attribute \src "libresoc.v:105754.3-105808.6" wire width 3 $0\dec31_dec_sub22_sv_cr_out[2:0] - attribute \src "libresoc.v:105348.3-105402.6" + attribute \src "libresoc.v:105424.3-105478.6" wire width 3 $0\dec31_dec_sub22_sv_in1[2:0] - attribute \src "libresoc.v:105403.3-105457.6" + attribute \src "libresoc.v:105479.3-105533.6" wire width 3 $0\dec31_dec_sub22_sv_in2[2:0] - attribute \src "libresoc.v:105458.3-105512.6" + attribute \src "libresoc.v:105534.3-105588.6" wire width 3 $0\dec31_dec_sub22_sv_in3[2:0] - attribute \src "libresoc.v:105568.3-105622.6" + attribute \src "libresoc.v:105644.3-105698.6" wire width 3 $0\dec31_dec_sub22_sv_out2[2:0] - attribute \src "libresoc.v:105513.3-105567.6" + attribute \src "libresoc.v:105589.3-105643.6" wire width 3 $0\dec31_dec_sub22_sv_out[2:0] - attribute \src "libresoc.v:105843.3-105897.6" + attribute \src "libresoc.v:105919.3-105973.6" wire width 2 $0\dec31_dec_sub22_upd[1:0] - attribute \src "libresoc.v:104835.7-104835.20" + attribute \src "libresoc.v:104911.7-104911.20" wire $0\initial[0:0] - attribute \src "libresoc.v:106668.3-106722.6" + attribute \src "libresoc.v:106744.3-106798.6" wire width 2 $1\dec31_dec_sub22_SV_Etype[1:0] - attribute \src "libresoc.v:106723.3-106777.6" + attribute \src "libresoc.v:106799.3-106853.6" wire width 2 $1\dec31_dec_sub22_SV_Ptype[1:0] - attribute \src "libresoc.v:106008.3-106062.6" + attribute \src "libresoc.v:106084.3-106138.6" wire width 8 $1\dec31_dec_sub22_asmcode[7:0] - attribute \src "libresoc.v:106228.3-106282.6" + attribute \src "libresoc.v:106304.3-106358.6" wire $1\dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:105238.3-105292.6" + attribute \src "libresoc.v:105314.3-105368.6" wire width 3 $1\dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:105293.3-105347.6" + attribute \src "libresoc.v:105369.3-105423.6" wire width 3 $1\dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:105953.3-106007.6" + attribute \src "libresoc.v:106029.3-106083.6" wire width 2 $1\dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:106173.3-106227.6" + attribute \src "libresoc.v:106249.3-106303.6" wire $1\dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:106393.3-106447.6" + attribute \src "libresoc.v:106469.3-106523.6" wire width 5 $1\dec31_dec_sub22_form[4:0] - attribute \src "libresoc.v:105183.3-105237.6" + attribute \src "libresoc.v:105259.3-105313.6" wire width 14 $1\dec31_dec_sub22_function_unit[13:0] - attribute \src "libresoc.v:106778.3-106832.6" + attribute \src "libresoc.v:106854.3-106908.6" wire width 3 $1\dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:106833.3-106887.6" + attribute \src "libresoc.v:106909.3-106963.6" wire width 4 $1\dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:106888.3-106942.6" + attribute \src "libresoc.v:106964.3-107018.6" wire width 2 $1\dec31_dec_sub22_in3_sel[1:0] - attribute \src "libresoc.v:105788.3-105842.6" + attribute \src "libresoc.v:105864.3-105918.6" wire width 7 $1\dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:106063.3-106117.6" + attribute \src "libresoc.v:106139.3-106193.6" wire $1\dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:106118.3-106172.6" + attribute \src "libresoc.v:106194.3-106248.6" wire $1\dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:106448.3-106502.6" + attribute \src "libresoc.v:106524.3-106578.6" wire $1\dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:105733.3-105787.6" + attribute \src "libresoc.v:105809.3-105863.6" wire width 4 $1\dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:106558.3-106612.6" + attribute \src "libresoc.v:106634.3-106688.6" wire $1\dec31_dec_sub22_lk[0:0] - attribute \src "libresoc.v:106943.3-106997.6" + attribute \src "libresoc.v:107019.3-107073.6" wire width 3 $1\dec31_dec_sub22_out_sel[2:0] - attribute \src "libresoc.v:105898.3-105952.6" + attribute \src "libresoc.v:105974.3-106028.6" wire width 2 $1\dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:106338.3-106392.6" + attribute \src "libresoc.v:106414.3-106468.6" wire $1\dec31_dec_sub22_rsrv[0:0] - attribute \src "libresoc.v:106613.3-106667.6" + attribute \src "libresoc.v:106689.3-106743.6" wire $1\dec31_dec_sub22_sgl_pipe[0:0] - attribute \src "libresoc.v:106503.3-106557.6" + attribute \src "libresoc.v:106579.3-106633.6" wire $1\dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:106283.3-106337.6" + attribute \src "libresoc.v:106359.3-106413.6" wire $1\dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:105623.3-105677.6" + attribute \src "libresoc.v:105699.3-105753.6" wire width 3 $1\dec31_dec_sub22_sv_cr_in[2:0] - attribute \src "libresoc.v:105678.3-105732.6" + attribute \src "libresoc.v:105754.3-105808.6" wire width 3 $1\dec31_dec_sub22_sv_cr_out[2:0] - attribute \src "libresoc.v:105348.3-105402.6" + attribute \src "libresoc.v:105424.3-105478.6" wire width 3 $1\dec31_dec_sub22_sv_in1[2:0] - attribute \src "libresoc.v:105403.3-105457.6" + attribute \src "libresoc.v:105479.3-105533.6" wire width 3 $1\dec31_dec_sub22_sv_in2[2:0] - attribute \src "libresoc.v:105458.3-105512.6" + attribute \src "libresoc.v:105534.3-105588.6" wire width 3 $1\dec31_dec_sub22_sv_in3[2:0] - attribute \src "libresoc.v:105568.3-105622.6" + attribute \src "libresoc.v:105644.3-105698.6" wire width 3 $1\dec31_dec_sub22_sv_out2[2:0] - attribute \src "libresoc.v:105513.3-105567.6" + attribute \src "libresoc.v:105589.3-105643.6" wire width 3 $1\dec31_dec_sub22_sv_out[2:0] - attribute \src "libresoc.v:105843.3-105897.6" + attribute \src "libresoc.v:105919.3-105973.6" wire width 2 $1\dec31_dec_sub22_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -163894,28 +163957,28 @@ module \dec31_dec_sub22 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub22_upd - attribute \src "libresoc.v:104835.7-104835.15" + attribute \src "libresoc.v:104911.7-104911.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:104835.7-104835.20" - process $proc$libresoc.v:104835$4190 + attribute \src "libresoc.v:104911.7-104911.20" + process $proc$libresoc.v:104911$4190 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:105183.3-105237.6" - process $proc$libresoc.v:105183$4157 + attribute \src "libresoc.v:105259.3-105313.6" + process $proc$libresoc.v:105259$4157 assign { } { } assign { } { } assign $0\dec31_dec_sub22_function_unit[13:0] $1\dec31_dec_sub22_function_unit[13:0] - attribute \src "libresoc.v:105184.5-105184.29" + attribute \src "libresoc.v:105260.5-105260.29" switch \initial - attribute \src "libresoc.v:105184.9-105184.17" + attribute \src "libresoc.v:105260.9-105260.17" case 1'1 case end @@ -163991,14 +164054,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_function_unit $0\dec31_dec_sub22_function_unit[13:0] end - attribute \src "libresoc.v:105238.3-105292.6" - process $proc$libresoc.v:105238$4158 + attribute \src "libresoc.v:105314.3-105368.6" + process $proc$libresoc.v:105314$4158 assign { } { } assign { } { } assign $0\dec31_dec_sub22_cr_in[2:0] $1\dec31_dec_sub22_cr_in[2:0] - attribute \src "libresoc.v:105239.5-105239.29" + attribute \src "libresoc.v:105315.5-105315.29" switch \initial - attribute \src "libresoc.v:105239.9-105239.17" + attribute \src "libresoc.v:105315.9-105315.17" case 1'1 case end @@ -164074,14 +164137,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_cr_in $0\dec31_dec_sub22_cr_in[2:0] end - attribute \src "libresoc.v:105293.3-105347.6" - process $proc$libresoc.v:105293$4159 + attribute \src "libresoc.v:105369.3-105423.6" + process $proc$libresoc.v:105369$4159 assign { } { } assign { } { } assign $0\dec31_dec_sub22_cr_out[2:0] $1\dec31_dec_sub22_cr_out[2:0] - attribute \src "libresoc.v:105294.5-105294.29" + attribute \src "libresoc.v:105370.5-105370.29" switch \initial - attribute \src "libresoc.v:105294.9-105294.17" + attribute \src "libresoc.v:105370.9-105370.17" case 1'1 case end @@ -164157,14 +164220,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_cr_out $0\dec31_dec_sub22_cr_out[2:0] end - attribute \src "libresoc.v:105348.3-105402.6" - process $proc$libresoc.v:105348$4160 + attribute \src "libresoc.v:105424.3-105478.6" + process $proc$libresoc.v:105424$4160 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_in1[2:0] $1\dec31_dec_sub22_sv_in1[2:0] - attribute \src "libresoc.v:105349.5-105349.29" + attribute \src "libresoc.v:105425.5-105425.29" switch \initial - attribute \src "libresoc.v:105349.9-105349.17" + attribute \src "libresoc.v:105425.9-105425.17" case 1'1 case end @@ -164240,14 +164303,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_in1 $0\dec31_dec_sub22_sv_in1[2:0] end - attribute \src "libresoc.v:105403.3-105457.6" - process $proc$libresoc.v:105403$4161 + attribute \src "libresoc.v:105479.3-105533.6" + process $proc$libresoc.v:105479$4161 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_in2[2:0] $1\dec31_dec_sub22_sv_in2[2:0] - attribute \src "libresoc.v:105404.5-105404.29" + attribute \src "libresoc.v:105480.5-105480.29" switch \initial - attribute \src "libresoc.v:105404.9-105404.17" + attribute \src "libresoc.v:105480.9-105480.17" case 1'1 case end @@ -164323,14 +164386,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_in2 $0\dec31_dec_sub22_sv_in2[2:0] end - attribute \src "libresoc.v:105458.3-105512.6" - process $proc$libresoc.v:105458$4162 + attribute \src "libresoc.v:105534.3-105588.6" + process $proc$libresoc.v:105534$4162 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_in3[2:0] $1\dec31_dec_sub22_sv_in3[2:0] - attribute \src "libresoc.v:105459.5-105459.29" + attribute \src "libresoc.v:105535.5-105535.29" switch \initial - attribute \src "libresoc.v:105459.9-105459.17" + attribute \src "libresoc.v:105535.9-105535.17" case 1'1 case end @@ -164406,14 +164469,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_in3 $0\dec31_dec_sub22_sv_in3[2:0] end - attribute \src "libresoc.v:105513.3-105567.6" - process $proc$libresoc.v:105513$4163 + attribute \src "libresoc.v:105589.3-105643.6" + process $proc$libresoc.v:105589$4163 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_out[2:0] $1\dec31_dec_sub22_sv_out[2:0] - attribute \src "libresoc.v:105514.5-105514.29" + attribute \src "libresoc.v:105590.5-105590.29" switch \initial - attribute \src "libresoc.v:105514.9-105514.17" + attribute \src "libresoc.v:105590.9-105590.17" case 1'1 case end @@ -164489,14 +164552,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_out $0\dec31_dec_sub22_sv_out[2:0] end - attribute \src "libresoc.v:105568.3-105622.6" - process $proc$libresoc.v:105568$4164 + attribute \src "libresoc.v:105644.3-105698.6" + process $proc$libresoc.v:105644$4164 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_out2[2:0] $1\dec31_dec_sub22_sv_out2[2:0] - attribute \src "libresoc.v:105569.5-105569.29" + attribute \src "libresoc.v:105645.5-105645.29" switch \initial - attribute \src "libresoc.v:105569.9-105569.17" + attribute \src "libresoc.v:105645.9-105645.17" case 1'1 case end @@ -164572,14 +164635,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_out2 $0\dec31_dec_sub22_sv_out2[2:0] end - attribute \src "libresoc.v:105623.3-105677.6" - process $proc$libresoc.v:105623$4165 + attribute \src "libresoc.v:105699.3-105753.6" + process $proc$libresoc.v:105699$4165 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_cr_in[2:0] $1\dec31_dec_sub22_sv_cr_in[2:0] - attribute \src "libresoc.v:105624.5-105624.29" + attribute \src "libresoc.v:105700.5-105700.29" switch \initial - attribute \src "libresoc.v:105624.9-105624.17" + attribute \src "libresoc.v:105700.9-105700.17" case 1'1 case end @@ -164655,14 +164718,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_cr_in $0\dec31_dec_sub22_sv_cr_in[2:0] end - attribute \src "libresoc.v:105678.3-105732.6" - process $proc$libresoc.v:105678$4166 + attribute \src "libresoc.v:105754.3-105808.6" + process $proc$libresoc.v:105754$4166 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sv_cr_out[2:0] $1\dec31_dec_sub22_sv_cr_out[2:0] - attribute \src "libresoc.v:105679.5-105679.29" + attribute \src "libresoc.v:105755.5-105755.29" switch \initial - attribute \src "libresoc.v:105679.9-105679.17" + attribute \src "libresoc.v:105755.9-105755.17" case 1'1 case end @@ -164738,14 +164801,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sv_cr_out $0\dec31_dec_sub22_sv_cr_out[2:0] end - attribute \src "libresoc.v:105733.3-105787.6" - process $proc$libresoc.v:105733$4167 + attribute \src "libresoc.v:105809.3-105863.6" + process $proc$libresoc.v:105809$4167 assign { } { } assign { } { } assign $0\dec31_dec_sub22_ldst_len[3:0] $1\dec31_dec_sub22_ldst_len[3:0] - attribute \src "libresoc.v:105734.5-105734.29" + attribute \src "libresoc.v:105810.5-105810.29" switch \initial - attribute \src "libresoc.v:105734.9-105734.17" + attribute \src "libresoc.v:105810.9-105810.17" case 1'1 case end @@ -164821,14 +164884,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_ldst_len $0\dec31_dec_sub22_ldst_len[3:0] end - attribute \src "libresoc.v:105788.3-105842.6" - process $proc$libresoc.v:105788$4168 + attribute \src "libresoc.v:105864.3-105918.6" + process $proc$libresoc.v:105864$4168 assign { } { } assign { } { } assign $0\dec31_dec_sub22_internal_op[6:0] $1\dec31_dec_sub22_internal_op[6:0] - attribute \src "libresoc.v:105789.5-105789.29" + attribute \src "libresoc.v:105865.5-105865.29" switch \initial - attribute \src "libresoc.v:105789.9-105789.17" + attribute \src "libresoc.v:105865.9-105865.17" case 1'1 case end @@ -164904,14 +164967,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_internal_op $0\dec31_dec_sub22_internal_op[6:0] end - attribute \src "libresoc.v:105843.3-105897.6" - process $proc$libresoc.v:105843$4169 + attribute \src "libresoc.v:105919.3-105973.6" + process $proc$libresoc.v:105919$4169 assign { } { } assign { } { } assign $0\dec31_dec_sub22_upd[1:0] $1\dec31_dec_sub22_upd[1:0] - attribute \src "libresoc.v:105844.5-105844.29" + attribute \src "libresoc.v:105920.5-105920.29" switch \initial - attribute \src "libresoc.v:105844.9-105844.17" + attribute \src "libresoc.v:105920.9-105920.17" case 1'1 case end @@ -164987,14 +165050,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_upd $0\dec31_dec_sub22_upd[1:0] end - attribute \src "libresoc.v:105898.3-105952.6" - process $proc$libresoc.v:105898$4170 + attribute \src "libresoc.v:105974.3-106028.6" + process $proc$libresoc.v:105974$4170 assign { } { } assign { } { } assign $0\dec31_dec_sub22_rc_sel[1:0] $1\dec31_dec_sub22_rc_sel[1:0] - attribute \src "libresoc.v:105899.5-105899.29" + attribute \src "libresoc.v:105975.5-105975.29" switch \initial - attribute \src "libresoc.v:105899.9-105899.17" + attribute \src "libresoc.v:105975.9-105975.17" case 1'1 case end @@ -165070,14 +165133,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_rc_sel $0\dec31_dec_sub22_rc_sel[1:0] end - attribute \src "libresoc.v:105953.3-106007.6" - process $proc$libresoc.v:105953$4171 + attribute \src "libresoc.v:106029.3-106083.6" + process $proc$libresoc.v:106029$4171 assign { } { } assign { } { } assign $0\dec31_dec_sub22_cry_in[1:0] $1\dec31_dec_sub22_cry_in[1:0] - attribute \src "libresoc.v:105954.5-105954.29" + attribute \src "libresoc.v:106030.5-106030.29" switch \initial - attribute \src "libresoc.v:105954.9-105954.17" + attribute \src "libresoc.v:106030.9-106030.17" case 1'1 case end @@ -165153,14 +165216,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_cry_in $0\dec31_dec_sub22_cry_in[1:0] end - attribute \src "libresoc.v:106008.3-106062.6" - process $proc$libresoc.v:106008$4172 + attribute \src "libresoc.v:106084.3-106138.6" + process $proc$libresoc.v:106084$4172 assign { } { } assign { } { } assign $0\dec31_dec_sub22_asmcode[7:0] $1\dec31_dec_sub22_asmcode[7:0] - attribute \src "libresoc.v:106009.5-106009.29" + attribute \src "libresoc.v:106085.5-106085.29" switch \initial - attribute \src "libresoc.v:106009.9-106009.17" + attribute \src "libresoc.v:106085.9-106085.17" case 1'1 case end @@ -165236,14 +165299,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_asmcode $0\dec31_dec_sub22_asmcode[7:0] end - attribute \src "libresoc.v:106063.3-106117.6" - process $proc$libresoc.v:106063$4173 + attribute \src "libresoc.v:106139.3-106193.6" + process $proc$libresoc.v:106139$4173 assign { } { } assign { } { } assign $0\dec31_dec_sub22_inv_a[0:0] $1\dec31_dec_sub22_inv_a[0:0] - attribute \src "libresoc.v:106064.5-106064.29" + attribute \src "libresoc.v:106140.5-106140.29" switch \initial - attribute \src "libresoc.v:106064.9-106064.17" + attribute \src "libresoc.v:106140.9-106140.17" case 1'1 case end @@ -165319,14 +165382,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_inv_a $0\dec31_dec_sub22_inv_a[0:0] end - attribute \src "libresoc.v:106118.3-106172.6" - process $proc$libresoc.v:106118$4174 + attribute \src "libresoc.v:106194.3-106248.6" + process $proc$libresoc.v:106194$4174 assign { } { } assign { } { } assign $0\dec31_dec_sub22_inv_out[0:0] $1\dec31_dec_sub22_inv_out[0:0] - attribute \src "libresoc.v:106119.5-106119.29" + attribute \src "libresoc.v:106195.5-106195.29" switch \initial - attribute \src "libresoc.v:106119.9-106119.17" + attribute \src "libresoc.v:106195.9-106195.17" case 1'1 case end @@ -165402,14 +165465,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_inv_out $0\dec31_dec_sub22_inv_out[0:0] end - attribute \src "libresoc.v:106173.3-106227.6" - process $proc$libresoc.v:106173$4175 + attribute \src "libresoc.v:106249.3-106303.6" + process $proc$libresoc.v:106249$4175 assign { } { } assign { } { } assign $0\dec31_dec_sub22_cry_out[0:0] $1\dec31_dec_sub22_cry_out[0:0] - attribute \src "libresoc.v:106174.5-106174.29" + attribute \src "libresoc.v:106250.5-106250.29" switch \initial - attribute \src "libresoc.v:106174.9-106174.17" + attribute \src "libresoc.v:106250.9-106250.17" case 1'1 case end @@ -165485,14 +165548,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_cry_out $0\dec31_dec_sub22_cry_out[0:0] end - attribute \src "libresoc.v:106228.3-106282.6" - process $proc$libresoc.v:106228$4176 + attribute \src "libresoc.v:106304.3-106358.6" + process $proc$libresoc.v:106304$4176 assign { } { } assign { } { } assign $0\dec31_dec_sub22_br[0:0] $1\dec31_dec_sub22_br[0:0] - attribute \src "libresoc.v:106229.5-106229.29" + attribute \src "libresoc.v:106305.5-106305.29" switch \initial - attribute \src "libresoc.v:106229.9-106229.17" + attribute \src "libresoc.v:106305.9-106305.17" case 1'1 case end @@ -165568,14 +165631,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_br $0\dec31_dec_sub22_br[0:0] end - attribute \src "libresoc.v:106283.3-106337.6" - process $proc$libresoc.v:106283$4177 + attribute \src "libresoc.v:106359.3-106413.6" + process $proc$libresoc.v:106359$4177 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sgn_ext[0:0] $1\dec31_dec_sub22_sgn_ext[0:0] - attribute \src "libresoc.v:106284.5-106284.29" + attribute \src "libresoc.v:106360.5-106360.29" switch \initial - attribute \src "libresoc.v:106284.9-106284.17" + attribute \src "libresoc.v:106360.9-106360.17" case 1'1 case end @@ -165651,14 +165714,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sgn_ext $0\dec31_dec_sub22_sgn_ext[0:0] end - attribute \src "libresoc.v:106338.3-106392.6" - process $proc$libresoc.v:106338$4178 + attribute \src "libresoc.v:106414.3-106468.6" + process $proc$libresoc.v:106414$4178 assign { } { } assign { } { } assign $0\dec31_dec_sub22_rsrv[0:0] $1\dec31_dec_sub22_rsrv[0:0] - attribute \src "libresoc.v:106339.5-106339.29" + attribute \src "libresoc.v:106415.5-106415.29" switch \initial - attribute \src "libresoc.v:106339.9-106339.17" + attribute \src "libresoc.v:106415.9-106415.17" case 1'1 case end @@ -165734,14 +165797,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_rsrv $0\dec31_dec_sub22_rsrv[0:0] end - attribute \src "libresoc.v:106393.3-106447.6" - process $proc$libresoc.v:106393$4179 + attribute \src "libresoc.v:106469.3-106523.6" + process $proc$libresoc.v:106469$4179 assign { } { } assign { } { } assign $0\dec31_dec_sub22_form[4:0] $1\dec31_dec_sub22_form[4:0] - attribute \src "libresoc.v:106394.5-106394.29" + attribute \src "libresoc.v:106470.5-106470.29" switch \initial - attribute \src "libresoc.v:106394.9-106394.17" + attribute \src "libresoc.v:106470.9-106470.17" case 1'1 case end @@ -165817,14 +165880,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_form $0\dec31_dec_sub22_form[4:0] end - attribute \src "libresoc.v:106448.3-106502.6" - process $proc$libresoc.v:106448$4180 + attribute \src "libresoc.v:106524.3-106578.6" + process $proc$libresoc.v:106524$4180 assign { } { } assign { } { } assign $0\dec31_dec_sub22_is_32b[0:0] $1\dec31_dec_sub22_is_32b[0:0] - attribute \src "libresoc.v:106449.5-106449.29" + attribute \src "libresoc.v:106525.5-106525.29" switch \initial - attribute \src "libresoc.v:106449.9-106449.17" + attribute \src "libresoc.v:106525.9-106525.17" case 1'1 case end @@ -165900,14 +165963,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_is_32b $0\dec31_dec_sub22_is_32b[0:0] end - attribute \src "libresoc.v:106503.3-106557.6" - process $proc$libresoc.v:106503$4181 + attribute \src "libresoc.v:106579.3-106633.6" + process $proc$libresoc.v:106579$4181 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sgn[0:0] $1\dec31_dec_sub22_sgn[0:0] - attribute \src "libresoc.v:106504.5-106504.29" + attribute \src "libresoc.v:106580.5-106580.29" switch \initial - attribute \src "libresoc.v:106504.9-106504.17" + attribute \src "libresoc.v:106580.9-106580.17" case 1'1 case end @@ -165983,14 +166046,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sgn $0\dec31_dec_sub22_sgn[0:0] end - attribute \src "libresoc.v:106558.3-106612.6" - process $proc$libresoc.v:106558$4182 + attribute \src "libresoc.v:106634.3-106688.6" + process $proc$libresoc.v:106634$4182 assign { } { } assign { } { } assign $0\dec31_dec_sub22_lk[0:0] $1\dec31_dec_sub22_lk[0:0] - attribute \src "libresoc.v:106559.5-106559.29" + attribute \src "libresoc.v:106635.5-106635.29" switch \initial - attribute \src "libresoc.v:106559.9-106559.17" + attribute \src "libresoc.v:106635.9-106635.17" case 1'1 case end @@ -166066,14 +166129,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_lk $0\dec31_dec_sub22_lk[0:0] end - attribute \src "libresoc.v:106613.3-106667.6" - process $proc$libresoc.v:106613$4183 + attribute \src "libresoc.v:106689.3-106743.6" + process $proc$libresoc.v:106689$4183 assign { } { } assign { } { } assign $0\dec31_dec_sub22_sgl_pipe[0:0] $1\dec31_dec_sub22_sgl_pipe[0:0] - attribute \src "libresoc.v:106614.5-106614.29" + attribute \src "libresoc.v:106690.5-106690.29" switch \initial - attribute \src "libresoc.v:106614.9-106614.17" + attribute \src "libresoc.v:106690.9-106690.17" case 1'1 case end @@ -166149,14 +166212,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_sgl_pipe $0\dec31_dec_sub22_sgl_pipe[0:0] end - attribute \src "libresoc.v:106668.3-106722.6" - process $proc$libresoc.v:106668$4184 + attribute \src "libresoc.v:106744.3-106798.6" + process $proc$libresoc.v:106744$4184 assign { } { } assign { } { } assign $0\dec31_dec_sub22_SV_Etype[1:0] $1\dec31_dec_sub22_SV_Etype[1:0] - attribute \src "libresoc.v:106669.5-106669.29" + attribute \src "libresoc.v:106745.5-106745.29" switch \initial - attribute \src "libresoc.v:106669.9-106669.17" + attribute \src "libresoc.v:106745.9-106745.17" case 1'1 case end @@ -166232,14 +166295,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_SV_Etype $0\dec31_dec_sub22_SV_Etype[1:0] end - attribute \src "libresoc.v:106723.3-106777.6" - process $proc$libresoc.v:106723$4185 + attribute \src "libresoc.v:106799.3-106853.6" + process $proc$libresoc.v:106799$4185 assign { } { } assign { } { } assign $0\dec31_dec_sub22_SV_Ptype[1:0] $1\dec31_dec_sub22_SV_Ptype[1:0] - attribute \src "libresoc.v:106724.5-106724.29" + attribute \src "libresoc.v:106800.5-106800.29" switch \initial - attribute \src "libresoc.v:106724.9-106724.17" + attribute \src "libresoc.v:106800.9-106800.17" case 1'1 case end @@ -166315,14 +166378,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_SV_Ptype $0\dec31_dec_sub22_SV_Ptype[1:0] end - attribute \src "libresoc.v:106778.3-106832.6" - process $proc$libresoc.v:106778$4186 + attribute \src "libresoc.v:106854.3-106908.6" + process $proc$libresoc.v:106854$4186 assign { } { } assign { } { } assign $0\dec31_dec_sub22_in1_sel[2:0] $1\dec31_dec_sub22_in1_sel[2:0] - attribute \src "libresoc.v:106779.5-106779.29" + attribute \src "libresoc.v:106855.5-106855.29" switch \initial - attribute \src "libresoc.v:106779.9-106779.17" + attribute \src "libresoc.v:106855.9-106855.17" case 1'1 case end @@ -166398,14 +166461,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_in1_sel $0\dec31_dec_sub22_in1_sel[2:0] end - attribute \src "libresoc.v:106833.3-106887.6" - process $proc$libresoc.v:106833$4187 + attribute \src "libresoc.v:106909.3-106963.6" + process $proc$libresoc.v:106909$4187 assign { } { } assign { } { } assign $0\dec31_dec_sub22_in2_sel[3:0] $1\dec31_dec_sub22_in2_sel[3:0] - attribute \src "libresoc.v:106834.5-106834.29" + attribute \src "libresoc.v:106910.5-106910.29" switch \initial - attribute \src "libresoc.v:106834.9-106834.17" + attribute \src "libresoc.v:106910.9-106910.17" case 1'1 case end @@ -166481,14 +166544,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_in2_sel $0\dec31_dec_sub22_in2_sel[3:0] end - attribute \src "libresoc.v:106888.3-106942.6" - process $proc$libresoc.v:106888$4188 + attribute \src "libresoc.v:106964.3-107018.6" + process $proc$libresoc.v:106964$4188 assign { } { } assign { } { } assign $0\dec31_dec_sub22_in3_sel[1:0] $1\dec31_dec_sub22_in3_sel[1:0] - attribute \src "libresoc.v:106889.5-106889.29" + attribute \src "libresoc.v:106965.5-106965.29" switch \initial - attribute \src "libresoc.v:106889.9-106889.17" + attribute \src "libresoc.v:106965.9-106965.17" case 1'1 case end @@ -166564,14 +166627,14 @@ module \dec31_dec_sub22 sync always update \dec31_dec_sub22_in3_sel $0\dec31_dec_sub22_in3_sel[1:0] end - attribute \src "libresoc.v:106943.3-106997.6" - process $proc$libresoc.v:106943$4189 + attribute \src "libresoc.v:107019.3-107073.6" + process $proc$libresoc.v:107019$4189 assign { } { } assign { } { } assign $0\dec31_dec_sub22_out_sel[2:0] $1\dec31_dec_sub22_out_sel[2:0] - attribute \src "libresoc.v:106944.5-106944.29" + attribute \src "libresoc.v:107020.5-107020.29" switch \initial - attribute \src "libresoc.v:106944.9-106944.17" + attribute \src "libresoc.v:107020.9-107020.17" case 1'1 case end @@ -166649,144 +166712,144 @@ module \dec31_dec_sub22 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:107003.1-108970.10" +attribute \src "libresoc.v:107079.1-109046.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub23" attribute \generator "nMigen" module \dec31_dec_sub23 - attribute \src "libresoc.v:108675.3-108723.6" + attribute \src "libresoc.v:108751.3-108799.6" wire width 2 $0\dec31_dec_sub23_SV_Etype[1:0] - attribute \src "libresoc.v:108724.3-108772.6" + attribute \src "libresoc.v:108800.3-108848.6" wire width 2 $0\dec31_dec_sub23_SV_Ptype[1:0] - attribute \src "libresoc.v:108087.3-108135.6" + attribute \src "libresoc.v:108163.3-108211.6" wire width 8 $0\dec31_dec_sub23_asmcode[7:0] - attribute \src "libresoc.v:108283.3-108331.6" + attribute \src "libresoc.v:108359.3-108407.6" wire $0\dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:107401.3-107449.6" + attribute \src "libresoc.v:107477.3-107525.6" wire width 3 $0\dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:107450.3-107498.6" + attribute \src "libresoc.v:107526.3-107574.6" wire width 3 $0\dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:108038.3-108086.6" + attribute \src "libresoc.v:108114.3-108162.6" wire width 2 $0\dec31_dec_sub23_cry_in[1:0] - attribute \src "libresoc.v:108234.3-108282.6" + attribute \src "libresoc.v:108310.3-108358.6" wire $0\dec31_dec_sub23_cry_out[0:0] - attribute \src "libresoc.v:108430.3-108478.6" + attribute \src "libresoc.v:108506.3-108554.6" wire width 5 $0\dec31_dec_sub23_form[4:0] - attribute \src "libresoc.v:107352.3-107400.6" + attribute \src "libresoc.v:107428.3-107476.6" wire width 14 $0\dec31_dec_sub23_function_unit[13:0] - attribute \src "libresoc.v:108773.3-108821.6" + attribute \src "libresoc.v:108849.3-108897.6" wire width 3 $0\dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:108822.3-108870.6" + attribute \src "libresoc.v:108898.3-108946.6" wire width 4 $0\dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:108871.3-108919.6" + attribute \src "libresoc.v:108947.3-108995.6" wire width 2 $0\dec31_dec_sub23_in3_sel[1:0] - attribute \src "libresoc.v:107891.3-107939.6" + attribute \src "libresoc.v:107967.3-108015.6" wire width 7 $0\dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:108136.3-108184.6" + attribute \src "libresoc.v:108212.3-108260.6" wire $0\dec31_dec_sub23_inv_a[0:0] - attribute \src "libresoc.v:108185.3-108233.6" + attribute \src "libresoc.v:108261.3-108309.6" wire $0\dec31_dec_sub23_inv_out[0:0] - attribute \src "libresoc.v:108479.3-108527.6" + attribute \src "libresoc.v:108555.3-108603.6" wire $0\dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:107842.3-107890.6" + attribute \src "libresoc.v:107918.3-107966.6" wire width 4 $0\dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:108577.3-108625.6" + attribute \src "libresoc.v:108653.3-108701.6" wire $0\dec31_dec_sub23_lk[0:0] - attribute \src "libresoc.v:108920.3-108968.6" + attribute \src "libresoc.v:108996.3-109044.6" wire width 3 $0\dec31_dec_sub23_out_sel[2:0] - attribute \src "libresoc.v:107989.3-108037.6" + attribute \src "libresoc.v:108065.3-108113.6" wire width 2 $0\dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:108381.3-108429.6" + attribute \src "libresoc.v:108457.3-108505.6" wire $0\dec31_dec_sub23_rsrv[0:0] - attribute \src "libresoc.v:108626.3-108674.6" + attribute \src "libresoc.v:108702.3-108750.6" wire $0\dec31_dec_sub23_sgl_pipe[0:0] - attribute \src "libresoc.v:108528.3-108576.6" + attribute \src "libresoc.v:108604.3-108652.6" wire $0\dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:108332.3-108380.6" + attribute \src "libresoc.v:108408.3-108456.6" wire $0\dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:107744.3-107792.6" + attribute \src "libresoc.v:107820.3-107868.6" wire width 3 $0\dec31_dec_sub23_sv_cr_in[2:0] - attribute \src "libresoc.v:107793.3-107841.6" + attribute \src "libresoc.v:107869.3-107917.6" wire width 3 $0\dec31_dec_sub23_sv_cr_out[2:0] - attribute \src "libresoc.v:107499.3-107547.6" + attribute \src "libresoc.v:107575.3-107623.6" wire width 3 $0\dec31_dec_sub23_sv_in1[2:0] - attribute \src "libresoc.v:107548.3-107596.6" + attribute \src "libresoc.v:107624.3-107672.6" wire width 3 $0\dec31_dec_sub23_sv_in2[2:0] - attribute \src "libresoc.v:107597.3-107645.6" + attribute \src "libresoc.v:107673.3-107721.6" wire width 3 $0\dec31_dec_sub23_sv_in3[2:0] - attribute \src "libresoc.v:107695.3-107743.6" + attribute \src "libresoc.v:107771.3-107819.6" wire width 3 $0\dec31_dec_sub23_sv_out2[2:0] - attribute \src "libresoc.v:107646.3-107694.6" + attribute \src "libresoc.v:107722.3-107770.6" wire width 3 $0\dec31_dec_sub23_sv_out[2:0] - attribute \src "libresoc.v:107940.3-107988.6" + attribute \src "libresoc.v:108016.3-108064.6" wire width 2 $0\dec31_dec_sub23_upd[1:0] - attribute \src "libresoc.v:107004.7-107004.20" + attribute \src "libresoc.v:107080.7-107080.20" wire $0\initial[0:0] - attribute \src "libresoc.v:108675.3-108723.6" + attribute \src "libresoc.v:108751.3-108799.6" wire width 2 $1\dec31_dec_sub23_SV_Etype[1:0] - attribute \src "libresoc.v:108724.3-108772.6" + attribute \src "libresoc.v:108800.3-108848.6" wire width 2 $1\dec31_dec_sub23_SV_Ptype[1:0] - attribute \src "libresoc.v:108087.3-108135.6" + attribute \src "libresoc.v:108163.3-108211.6" wire width 8 $1\dec31_dec_sub23_asmcode[7:0] - attribute \src "libresoc.v:108283.3-108331.6" + attribute \src "libresoc.v:108359.3-108407.6" wire $1\dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:107401.3-107449.6" + attribute \src "libresoc.v:107477.3-107525.6" wire width 3 $1\dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:107450.3-107498.6" + attribute \src "libresoc.v:107526.3-107574.6" wire width 3 $1\dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:108038.3-108086.6" + attribute \src "libresoc.v:108114.3-108162.6" wire width 2 $1\dec31_dec_sub23_cry_in[1:0] - attribute \src "libresoc.v:108234.3-108282.6" + attribute \src "libresoc.v:108310.3-108358.6" wire $1\dec31_dec_sub23_cry_out[0:0] - attribute \src "libresoc.v:108430.3-108478.6" + attribute \src "libresoc.v:108506.3-108554.6" wire width 5 $1\dec31_dec_sub23_form[4:0] - attribute \src "libresoc.v:107352.3-107400.6" + attribute \src "libresoc.v:107428.3-107476.6" wire width 14 $1\dec31_dec_sub23_function_unit[13:0] - attribute \src "libresoc.v:108773.3-108821.6" + attribute \src "libresoc.v:108849.3-108897.6" wire width 3 $1\dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:108822.3-108870.6" + attribute \src "libresoc.v:108898.3-108946.6" wire width 4 $1\dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:108871.3-108919.6" + attribute \src "libresoc.v:108947.3-108995.6" wire width 2 $1\dec31_dec_sub23_in3_sel[1:0] - attribute \src "libresoc.v:107891.3-107939.6" + attribute \src "libresoc.v:107967.3-108015.6" wire width 7 $1\dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:108136.3-108184.6" + attribute \src "libresoc.v:108212.3-108260.6" wire $1\dec31_dec_sub23_inv_a[0:0] - attribute \src "libresoc.v:108185.3-108233.6" + attribute \src "libresoc.v:108261.3-108309.6" wire $1\dec31_dec_sub23_inv_out[0:0] - attribute \src "libresoc.v:108479.3-108527.6" + attribute \src "libresoc.v:108555.3-108603.6" wire $1\dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:107842.3-107890.6" + attribute \src "libresoc.v:107918.3-107966.6" wire width 4 $1\dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:108577.3-108625.6" + attribute \src "libresoc.v:108653.3-108701.6" wire $1\dec31_dec_sub23_lk[0:0] - attribute \src "libresoc.v:108920.3-108968.6" + attribute \src "libresoc.v:108996.3-109044.6" wire width 3 $1\dec31_dec_sub23_out_sel[2:0] - attribute \src "libresoc.v:107989.3-108037.6" + attribute \src "libresoc.v:108065.3-108113.6" wire width 2 $1\dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:108381.3-108429.6" + attribute \src "libresoc.v:108457.3-108505.6" wire $1\dec31_dec_sub23_rsrv[0:0] - attribute \src "libresoc.v:108626.3-108674.6" + attribute \src "libresoc.v:108702.3-108750.6" wire $1\dec31_dec_sub23_sgl_pipe[0:0] - attribute \src "libresoc.v:108528.3-108576.6" + attribute \src "libresoc.v:108604.3-108652.6" wire $1\dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:108332.3-108380.6" + attribute \src "libresoc.v:108408.3-108456.6" wire $1\dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:107744.3-107792.6" + attribute \src "libresoc.v:107820.3-107868.6" wire width 3 $1\dec31_dec_sub23_sv_cr_in[2:0] - attribute \src "libresoc.v:107793.3-107841.6" + attribute \src "libresoc.v:107869.3-107917.6" wire width 3 $1\dec31_dec_sub23_sv_cr_out[2:0] - attribute \src "libresoc.v:107499.3-107547.6" + attribute \src "libresoc.v:107575.3-107623.6" wire width 3 $1\dec31_dec_sub23_sv_in1[2:0] - attribute \src "libresoc.v:107548.3-107596.6" + attribute \src "libresoc.v:107624.3-107672.6" wire width 3 $1\dec31_dec_sub23_sv_in2[2:0] - attribute \src "libresoc.v:107597.3-107645.6" + attribute \src "libresoc.v:107673.3-107721.6" wire width 3 $1\dec31_dec_sub23_sv_in3[2:0] - attribute \src "libresoc.v:107695.3-107743.6" + attribute \src "libresoc.v:107771.3-107819.6" wire width 3 $1\dec31_dec_sub23_sv_out2[2:0] - attribute \src "libresoc.v:107646.3-107694.6" + attribute \src "libresoc.v:107722.3-107770.6" wire width 3 $1\dec31_dec_sub23_sv_out[2:0] - attribute \src "libresoc.v:107940.3-107988.6" + attribute \src "libresoc.v:108016.3-108064.6" wire width 2 $1\dec31_dec_sub23_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -167098,28 +167161,28 @@ module \dec31_dec_sub23 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub23_upd - attribute \src "libresoc.v:107004.7-107004.15" + attribute \src "libresoc.v:107080.7-107080.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:107004.7-107004.20" - process $proc$libresoc.v:107004$4224 + attribute \src "libresoc.v:107080.7-107080.20" + process $proc$libresoc.v:107080$4224 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:107352.3-107400.6" - process $proc$libresoc.v:107352$4191 + attribute \src "libresoc.v:107428.3-107476.6" + process $proc$libresoc.v:107428$4191 assign { } { } assign { } { } assign $0\dec31_dec_sub23_function_unit[13:0] $1\dec31_dec_sub23_function_unit[13:0] - attribute \src "libresoc.v:107353.5-107353.29" + attribute \src "libresoc.v:107429.5-107429.29" switch \initial - attribute \src "libresoc.v:107353.9-107353.17" + attribute \src "libresoc.v:107429.9-107429.17" case 1'1 case end @@ -167187,14 +167250,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_function_unit $0\dec31_dec_sub23_function_unit[13:0] end - attribute \src "libresoc.v:107401.3-107449.6" - process $proc$libresoc.v:107401$4192 + attribute \src "libresoc.v:107477.3-107525.6" + process $proc$libresoc.v:107477$4192 assign { } { } assign { } { } assign $0\dec31_dec_sub23_cr_in[2:0] $1\dec31_dec_sub23_cr_in[2:0] - attribute \src "libresoc.v:107402.5-107402.29" + attribute \src "libresoc.v:107478.5-107478.29" switch \initial - attribute \src "libresoc.v:107402.9-107402.17" + attribute \src "libresoc.v:107478.9-107478.17" case 1'1 case end @@ -167262,14 +167325,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_cr_in $0\dec31_dec_sub23_cr_in[2:0] end - attribute \src "libresoc.v:107450.3-107498.6" - process $proc$libresoc.v:107450$4193 + attribute \src "libresoc.v:107526.3-107574.6" + process $proc$libresoc.v:107526$4193 assign { } { } assign { } { } assign $0\dec31_dec_sub23_cr_out[2:0] $1\dec31_dec_sub23_cr_out[2:0] - attribute \src "libresoc.v:107451.5-107451.29" + attribute \src "libresoc.v:107527.5-107527.29" switch \initial - attribute \src "libresoc.v:107451.9-107451.17" + attribute \src "libresoc.v:107527.9-107527.17" case 1'1 case end @@ -167337,14 +167400,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_cr_out $0\dec31_dec_sub23_cr_out[2:0] end - attribute \src "libresoc.v:107499.3-107547.6" - process $proc$libresoc.v:107499$4194 + attribute \src "libresoc.v:107575.3-107623.6" + process $proc$libresoc.v:107575$4194 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_in1[2:0] $1\dec31_dec_sub23_sv_in1[2:0] - attribute \src "libresoc.v:107500.5-107500.29" + attribute \src "libresoc.v:107576.5-107576.29" switch \initial - attribute \src "libresoc.v:107500.9-107500.17" + attribute \src "libresoc.v:107576.9-107576.17" case 1'1 case end @@ -167412,14 +167475,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_in1 $0\dec31_dec_sub23_sv_in1[2:0] end - attribute \src "libresoc.v:107548.3-107596.6" - process $proc$libresoc.v:107548$4195 + attribute \src "libresoc.v:107624.3-107672.6" + process $proc$libresoc.v:107624$4195 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_in2[2:0] $1\dec31_dec_sub23_sv_in2[2:0] - attribute \src "libresoc.v:107549.5-107549.29" + attribute \src "libresoc.v:107625.5-107625.29" switch \initial - attribute \src "libresoc.v:107549.9-107549.17" + attribute \src "libresoc.v:107625.9-107625.17" case 1'1 case end @@ -167487,14 +167550,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_in2 $0\dec31_dec_sub23_sv_in2[2:0] end - attribute \src "libresoc.v:107597.3-107645.6" - process $proc$libresoc.v:107597$4196 + attribute \src "libresoc.v:107673.3-107721.6" + process $proc$libresoc.v:107673$4196 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_in3[2:0] $1\dec31_dec_sub23_sv_in3[2:0] - attribute \src "libresoc.v:107598.5-107598.29" + attribute \src "libresoc.v:107674.5-107674.29" switch \initial - attribute \src "libresoc.v:107598.9-107598.17" + attribute \src "libresoc.v:107674.9-107674.17" case 1'1 case end @@ -167562,14 +167625,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_in3 $0\dec31_dec_sub23_sv_in3[2:0] end - attribute \src "libresoc.v:107646.3-107694.6" - process $proc$libresoc.v:107646$4197 + attribute \src "libresoc.v:107722.3-107770.6" + process $proc$libresoc.v:107722$4197 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_out[2:0] $1\dec31_dec_sub23_sv_out[2:0] - attribute \src "libresoc.v:107647.5-107647.29" + attribute \src "libresoc.v:107723.5-107723.29" switch \initial - attribute \src "libresoc.v:107647.9-107647.17" + attribute \src "libresoc.v:107723.9-107723.17" case 1'1 case end @@ -167637,14 +167700,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_out $0\dec31_dec_sub23_sv_out[2:0] end - attribute \src "libresoc.v:107695.3-107743.6" - process $proc$libresoc.v:107695$4198 + attribute \src "libresoc.v:107771.3-107819.6" + process $proc$libresoc.v:107771$4198 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_out2[2:0] $1\dec31_dec_sub23_sv_out2[2:0] - attribute \src "libresoc.v:107696.5-107696.29" + attribute \src "libresoc.v:107772.5-107772.29" switch \initial - attribute \src "libresoc.v:107696.9-107696.17" + attribute \src "libresoc.v:107772.9-107772.17" case 1'1 case end @@ -167712,14 +167775,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_out2 $0\dec31_dec_sub23_sv_out2[2:0] end - attribute \src "libresoc.v:107744.3-107792.6" - process $proc$libresoc.v:107744$4199 + attribute \src "libresoc.v:107820.3-107868.6" + process $proc$libresoc.v:107820$4199 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_cr_in[2:0] $1\dec31_dec_sub23_sv_cr_in[2:0] - attribute \src "libresoc.v:107745.5-107745.29" + attribute \src "libresoc.v:107821.5-107821.29" switch \initial - attribute \src "libresoc.v:107745.9-107745.17" + attribute \src "libresoc.v:107821.9-107821.17" case 1'1 case end @@ -167787,14 +167850,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_cr_in $0\dec31_dec_sub23_sv_cr_in[2:0] end - attribute \src "libresoc.v:107793.3-107841.6" - process $proc$libresoc.v:107793$4200 + attribute \src "libresoc.v:107869.3-107917.6" + process $proc$libresoc.v:107869$4200 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sv_cr_out[2:0] $1\dec31_dec_sub23_sv_cr_out[2:0] - attribute \src "libresoc.v:107794.5-107794.29" + attribute \src "libresoc.v:107870.5-107870.29" switch \initial - attribute \src "libresoc.v:107794.9-107794.17" + attribute \src "libresoc.v:107870.9-107870.17" case 1'1 case end @@ -167862,14 +167925,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sv_cr_out $0\dec31_dec_sub23_sv_cr_out[2:0] end - attribute \src "libresoc.v:107842.3-107890.6" - process $proc$libresoc.v:107842$4201 + attribute \src "libresoc.v:107918.3-107966.6" + process $proc$libresoc.v:107918$4201 assign { } { } assign { } { } assign $0\dec31_dec_sub23_ldst_len[3:0] $1\dec31_dec_sub23_ldst_len[3:0] - attribute \src "libresoc.v:107843.5-107843.29" + attribute \src "libresoc.v:107919.5-107919.29" switch \initial - attribute \src "libresoc.v:107843.9-107843.17" + attribute \src "libresoc.v:107919.9-107919.17" case 1'1 case end @@ -167937,14 +168000,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_ldst_len $0\dec31_dec_sub23_ldst_len[3:0] end - attribute \src "libresoc.v:107891.3-107939.6" - process $proc$libresoc.v:107891$4202 + attribute \src "libresoc.v:107967.3-108015.6" + process $proc$libresoc.v:107967$4202 assign { } { } assign { } { } assign $0\dec31_dec_sub23_internal_op[6:0] $1\dec31_dec_sub23_internal_op[6:0] - attribute \src "libresoc.v:107892.5-107892.29" + attribute \src "libresoc.v:107968.5-107968.29" switch \initial - attribute \src "libresoc.v:107892.9-107892.17" + attribute \src "libresoc.v:107968.9-107968.17" case 1'1 case end @@ -168012,14 +168075,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_internal_op $0\dec31_dec_sub23_internal_op[6:0] end - attribute \src "libresoc.v:107940.3-107988.6" - process $proc$libresoc.v:107940$4203 + attribute \src "libresoc.v:108016.3-108064.6" + process $proc$libresoc.v:108016$4203 assign { } { } assign { } { } assign $0\dec31_dec_sub23_upd[1:0] $1\dec31_dec_sub23_upd[1:0] - attribute \src "libresoc.v:107941.5-107941.29" + attribute \src "libresoc.v:108017.5-108017.29" switch \initial - attribute \src "libresoc.v:107941.9-107941.17" + attribute \src "libresoc.v:108017.9-108017.17" case 1'1 case end @@ -168087,14 +168150,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_upd $0\dec31_dec_sub23_upd[1:0] end - attribute \src "libresoc.v:107989.3-108037.6" - process $proc$libresoc.v:107989$4204 + attribute \src "libresoc.v:108065.3-108113.6" + process $proc$libresoc.v:108065$4204 assign { } { } assign { } { } assign $0\dec31_dec_sub23_rc_sel[1:0] $1\dec31_dec_sub23_rc_sel[1:0] - attribute \src "libresoc.v:107990.5-107990.29" + attribute \src "libresoc.v:108066.5-108066.29" switch \initial - attribute \src "libresoc.v:107990.9-107990.17" + attribute \src "libresoc.v:108066.9-108066.17" case 1'1 case end @@ -168162,14 +168225,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_rc_sel $0\dec31_dec_sub23_rc_sel[1:0] end - attribute \src "libresoc.v:108038.3-108086.6" - process $proc$libresoc.v:108038$4205 + attribute \src "libresoc.v:108114.3-108162.6" + process $proc$libresoc.v:108114$4205 assign { } { } assign { } { } assign $0\dec31_dec_sub23_cry_in[1:0] $1\dec31_dec_sub23_cry_in[1:0] - attribute \src "libresoc.v:108039.5-108039.29" + attribute \src "libresoc.v:108115.5-108115.29" switch \initial - attribute \src "libresoc.v:108039.9-108039.17" + attribute \src "libresoc.v:108115.9-108115.17" case 1'1 case end @@ -168237,14 +168300,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_cry_in $0\dec31_dec_sub23_cry_in[1:0] end - attribute \src "libresoc.v:108087.3-108135.6" - process $proc$libresoc.v:108087$4206 + attribute \src "libresoc.v:108163.3-108211.6" + process $proc$libresoc.v:108163$4206 assign { } { } assign { } { } assign $0\dec31_dec_sub23_asmcode[7:0] $1\dec31_dec_sub23_asmcode[7:0] - attribute \src "libresoc.v:108088.5-108088.29" + attribute \src "libresoc.v:108164.5-108164.29" switch \initial - attribute \src "libresoc.v:108088.9-108088.17" + attribute \src "libresoc.v:108164.9-108164.17" case 1'1 case end @@ -168312,14 +168375,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_asmcode $0\dec31_dec_sub23_asmcode[7:0] end - attribute \src "libresoc.v:108136.3-108184.6" - process $proc$libresoc.v:108136$4207 + attribute \src "libresoc.v:108212.3-108260.6" + process $proc$libresoc.v:108212$4207 assign { } { } assign { } { } assign $0\dec31_dec_sub23_inv_a[0:0] $1\dec31_dec_sub23_inv_a[0:0] - attribute \src "libresoc.v:108137.5-108137.29" + attribute \src "libresoc.v:108213.5-108213.29" switch \initial - attribute \src "libresoc.v:108137.9-108137.17" + attribute \src "libresoc.v:108213.9-108213.17" case 1'1 case end @@ -168387,14 +168450,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_inv_a $0\dec31_dec_sub23_inv_a[0:0] end - attribute \src "libresoc.v:108185.3-108233.6" - process $proc$libresoc.v:108185$4208 + attribute \src "libresoc.v:108261.3-108309.6" + process $proc$libresoc.v:108261$4208 assign { } { } assign { } { } assign $0\dec31_dec_sub23_inv_out[0:0] $1\dec31_dec_sub23_inv_out[0:0] - attribute \src "libresoc.v:108186.5-108186.29" + attribute \src "libresoc.v:108262.5-108262.29" switch \initial - attribute \src "libresoc.v:108186.9-108186.17" + attribute \src "libresoc.v:108262.9-108262.17" case 1'1 case end @@ -168462,14 +168525,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_inv_out $0\dec31_dec_sub23_inv_out[0:0] end - attribute \src "libresoc.v:108234.3-108282.6" - process $proc$libresoc.v:108234$4209 + attribute \src "libresoc.v:108310.3-108358.6" + process $proc$libresoc.v:108310$4209 assign { } { } assign { } { } assign $0\dec31_dec_sub23_cry_out[0:0] $1\dec31_dec_sub23_cry_out[0:0] - attribute \src "libresoc.v:108235.5-108235.29" + attribute \src "libresoc.v:108311.5-108311.29" switch \initial - attribute \src "libresoc.v:108235.9-108235.17" + attribute \src "libresoc.v:108311.9-108311.17" case 1'1 case end @@ -168537,14 +168600,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_cry_out $0\dec31_dec_sub23_cry_out[0:0] end - attribute \src "libresoc.v:108283.3-108331.6" - process $proc$libresoc.v:108283$4210 + attribute \src "libresoc.v:108359.3-108407.6" + process $proc$libresoc.v:108359$4210 assign { } { } assign { } { } assign $0\dec31_dec_sub23_br[0:0] $1\dec31_dec_sub23_br[0:0] - attribute \src "libresoc.v:108284.5-108284.29" + attribute \src "libresoc.v:108360.5-108360.29" switch \initial - attribute \src "libresoc.v:108284.9-108284.17" + attribute \src "libresoc.v:108360.9-108360.17" case 1'1 case end @@ -168612,14 +168675,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_br $0\dec31_dec_sub23_br[0:0] end - attribute \src "libresoc.v:108332.3-108380.6" - process $proc$libresoc.v:108332$4211 + attribute \src "libresoc.v:108408.3-108456.6" + process $proc$libresoc.v:108408$4211 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sgn_ext[0:0] $1\dec31_dec_sub23_sgn_ext[0:0] - attribute \src "libresoc.v:108333.5-108333.29" + attribute \src "libresoc.v:108409.5-108409.29" switch \initial - attribute \src "libresoc.v:108333.9-108333.17" + attribute \src "libresoc.v:108409.9-108409.17" case 1'1 case end @@ -168687,14 +168750,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sgn_ext $0\dec31_dec_sub23_sgn_ext[0:0] end - attribute \src "libresoc.v:108381.3-108429.6" - process $proc$libresoc.v:108381$4212 + attribute \src "libresoc.v:108457.3-108505.6" + process $proc$libresoc.v:108457$4212 assign { } { } assign { } { } assign $0\dec31_dec_sub23_rsrv[0:0] $1\dec31_dec_sub23_rsrv[0:0] - attribute \src "libresoc.v:108382.5-108382.29" + attribute \src "libresoc.v:108458.5-108458.29" switch \initial - attribute \src "libresoc.v:108382.9-108382.17" + attribute \src "libresoc.v:108458.9-108458.17" case 1'1 case end @@ -168762,14 +168825,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_rsrv $0\dec31_dec_sub23_rsrv[0:0] end - attribute \src "libresoc.v:108430.3-108478.6" - process $proc$libresoc.v:108430$4213 + attribute \src "libresoc.v:108506.3-108554.6" + process $proc$libresoc.v:108506$4213 assign { } { } assign { } { } assign $0\dec31_dec_sub23_form[4:0] $1\dec31_dec_sub23_form[4:0] - attribute \src "libresoc.v:108431.5-108431.29" + attribute \src "libresoc.v:108507.5-108507.29" switch \initial - attribute \src "libresoc.v:108431.9-108431.17" + attribute \src "libresoc.v:108507.9-108507.17" case 1'1 case end @@ -168837,14 +168900,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_form $0\dec31_dec_sub23_form[4:0] end - attribute \src "libresoc.v:108479.3-108527.6" - process $proc$libresoc.v:108479$4214 + attribute \src "libresoc.v:108555.3-108603.6" + process $proc$libresoc.v:108555$4214 assign { } { } assign { } { } assign $0\dec31_dec_sub23_is_32b[0:0] $1\dec31_dec_sub23_is_32b[0:0] - attribute \src "libresoc.v:108480.5-108480.29" + attribute \src "libresoc.v:108556.5-108556.29" switch \initial - attribute \src "libresoc.v:108480.9-108480.17" + attribute \src "libresoc.v:108556.9-108556.17" case 1'1 case end @@ -168912,14 +168975,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_is_32b $0\dec31_dec_sub23_is_32b[0:0] end - attribute \src "libresoc.v:108528.3-108576.6" - process $proc$libresoc.v:108528$4215 + attribute \src "libresoc.v:108604.3-108652.6" + process $proc$libresoc.v:108604$4215 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sgn[0:0] $1\dec31_dec_sub23_sgn[0:0] - attribute \src "libresoc.v:108529.5-108529.29" + attribute \src "libresoc.v:108605.5-108605.29" switch \initial - attribute \src "libresoc.v:108529.9-108529.17" + attribute \src "libresoc.v:108605.9-108605.17" case 1'1 case end @@ -168987,14 +169050,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sgn $0\dec31_dec_sub23_sgn[0:0] end - attribute \src "libresoc.v:108577.3-108625.6" - process $proc$libresoc.v:108577$4216 + attribute \src "libresoc.v:108653.3-108701.6" + process $proc$libresoc.v:108653$4216 assign { } { } assign { } { } assign $0\dec31_dec_sub23_lk[0:0] $1\dec31_dec_sub23_lk[0:0] - attribute \src "libresoc.v:108578.5-108578.29" + attribute \src "libresoc.v:108654.5-108654.29" switch \initial - attribute \src "libresoc.v:108578.9-108578.17" + attribute \src "libresoc.v:108654.9-108654.17" case 1'1 case end @@ -169062,14 +169125,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_lk $0\dec31_dec_sub23_lk[0:0] end - attribute \src "libresoc.v:108626.3-108674.6" - process $proc$libresoc.v:108626$4217 + attribute \src "libresoc.v:108702.3-108750.6" + process $proc$libresoc.v:108702$4217 assign { } { } assign { } { } assign $0\dec31_dec_sub23_sgl_pipe[0:0] $1\dec31_dec_sub23_sgl_pipe[0:0] - attribute \src "libresoc.v:108627.5-108627.29" + attribute \src "libresoc.v:108703.5-108703.29" switch \initial - attribute \src "libresoc.v:108627.9-108627.17" + attribute \src "libresoc.v:108703.9-108703.17" case 1'1 case end @@ -169137,14 +169200,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_sgl_pipe $0\dec31_dec_sub23_sgl_pipe[0:0] end - attribute \src "libresoc.v:108675.3-108723.6" - process $proc$libresoc.v:108675$4218 + attribute \src "libresoc.v:108751.3-108799.6" + process $proc$libresoc.v:108751$4218 assign { } { } assign { } { } assign $0\dec31_dec_sub23_SV_Etype[1:0] $1\dec31_dec_sub23_SV_Etype[1:0] - attribute \src "libresoc.v:108676.5-108676.29" + attribute \src "libresoc.v:108752.5-108752.29" switch \initial - attribute \src "libresoc.v:108676.9-108676.17" + attribute \src "libresoc.v:108752.9-108752.17" case 1'1 case end @@ -169212,14 +169275,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_SV_Etype $0\dec31_dec_sub23_SV_Etype[1:0] end - attribute \src "libresoc.v:108724.3-108772.6" - process $proc$libresoc.v:108724$4219 + attribute \src "libresoc.v:108800.3-108848.6" + process $proc$libresoc.v:108800$4219 assign { } { } assign { } { } assign $0\dec31_dec_sub23_SV_Ptype[1:0] $1\dec31_dec_sub23_SV_Ptype[1:0] - attribute \src "libresoc.v:108725.5-108725.29" + attribute \src "libresoc.v:108801.5-108801.29" switch \initial - attribute \src "libresoc.v:108725.9-108725.17" + attribute \src "libresoc.v:108801.9-108801.17" case 1'1 case end @@ -169287,14 +169350,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_SV_Ptype $0\dec31_dec_sub23_SV_Ptype[1:0] end - attribute \src "libresoc.v:108773.3-108821.6" - process $proc$libresoc.v:108773$4220 + attribute \src "libresoc.v:108849.3-108897.6" + process $proc$libresoc.v:108849$4220 assign { } { } assign { } { } assign $0\dec31_dec_sub23_in1_sel[2:0] $1\dec31_dec_sub23_in1_sel[2:0] - attribute \src "libresoc.v:108774.5-108774.29" + attribute \src "libresoc.v:108850.5-108850.29" switch \initial - attribute \src "libresoc.v:108774.9-108774.17" + attribute \src "libresoc.v:108850.9-108850.17" case 1'1 case end @@ -169362,14 +169425,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_in1_sel $0\dec31_dec_sub23_in1_sel[2:0] end - attribute \src "libresoc.v:108822.3-108870.6" - process $proc$libresoc.v:108822$4221 + attribute \src "libresoc.v:108898.3-108946.6" + process $proc$libresoc.v:108898$4221 assign { } { } assign { } { } assign $0\dec31_dec_sub23_in2_sel[3:0] $1\dec31_dec_sub23_in2_sel[3:0] - attribute \src "libresoc.v:108823.5-108823.29" + attribute \src "libresoc.v:108899.5-108899.29" switch \initial - attribute \src "libresoc.v:108823.9-108823.17" + attribute \src "libresoc.v:108899.9-108899.17" case 1'1 case end @@ -169437,14 +169500,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_in2_sel $0\dec31_dec_sub23_in2_sel[3:0] end - attribute \src "libresoc.v:108871.3-108919.6" - process $proc$libresoc.v:108871$4222 + attribute \src "libresoc.v:108947.3-108995.6" + process $proc$libresoc.v:108947$4222 assign { } { } assign { } { } assign $0\dec31_dec_sub23_in3_sel[1:0] $1\dec31_dec_sub23_in3_sel[1:0] - attribute \src "libresoc.v:108872.5-108872.29" + attribute \src "libresoc.v:108948.5-108948.29" switch \initial - attribute \src "libresoc.v:108872.9-108872.17" + attribute \src "libresoc.v:108948.9-108948.17" case 1'1 case end @@ -169512,14 +169575,14 @@ module \dec31_dec_sub23 sync always update \dec31_dec_sub23_in3_sel $0\dec31_dec_sub23_in3_sel[1:0] end - attribute \src "libresoc.v:108920.3-108968.6" - process $proc$libresoc.v:108920$4223 + attribute \src "libresoc.v:108996.3-109044.6" + process $proc$libresoc.v:108996$4223 assign { } { } assign { } { } assign $0\dec31_dec_sub23_out_sel[2:0] $1\dec31_dec_sub23_out_sel[2:0] - attribute \src "libresoc.v:108921.5-108921.29" + attribute \src "libresoc.v:108997.5-108997.29" switch \initial - attribute \src "libresoc.v:108921.9-108921.17" + attribute \src "libresoc.v:108997.9-108997.17" case 1'1 case end @@ -169589,144 +169652,144 @@ module \dec31_dec_sub23 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:108974.1-109951.10" +attribute \src "libresoc.v:109050.1-110027.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub24" attribute \generator "nMigen" module \dec31_dec_sub24 - attribute \src "libresoc.v:109836.3-109854.6" + attribute \src "libresoc.v:109912.3-109930.6" wire width 2 $0\dec31_dec_sub24_SV_Etype[1:0] - attribute \src "libresoc.v:109855.3-109873.6" + attribute \src "libresoc.v:109931.3-109949.6" wire width 2 $0\dec31_dec_sub24_SV_Ptype[1:0] - attribute \src "libresoc.v:109608.3-109626.6" - wire width 8 $0\dec31_dec_sub24_asmcode[7:0] attribute \src "libresoc.v:109684.3-109702.6" + wire width 8 $0\dec31_dec_sub24_asmcode[7:0] + attribute \src "libresoc.v:109760.3-109778.6" wire $0\dec31_dec_sub24_br[0:0] - attribute \src "libresoc.v:109342.3-109360.6" + attribute \src "libresoc.v:109418.3-109436.6" wire width 3 $0\dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:109361.3-109379.6" + attribute \src "libresoc.v:109437.3-109455.6" wire width 3 $0\dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:109589.3-109607.6" - wire width 2 $0\dec31_dec_sub24_cry_in[1:0] attribute \src "libresoc.v:109665.3-109683.6" - wire $0\dec31_dec_sub24_cry_out[0:0] + wire width 2 $0\dec31_dec_sub24_cry_in[1:0] attribute \src "libresoc.v:109741.3-109759.6" + wire $0\dec31_dec_sub24_cry_out[0:0] + attribute \src "libresoc.v:109817.3-109835.6" wire width 5 $0\dec31_dec_sub24_form[4:0] - attribute \src "libresoc.v:109323.3-109341.6" + attribute \src "libresoc.v:109399.3-109417.6" wire width 14 $0\dec31_dec_sub24_function_unit[13:0] - attribute \src "libresoc.v:109874.3-109892.6" + attribute \src "libresoc.v:109950.3-109968.6" wire width 3 $0\dec31_dec_sub24_in1_sel[2:0] - attribute \src "libresoc.v:109893.3-109911.6" + attribute \src "libresoc.v:109969.3-109987.6" wire width 4 $0\dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:109912.3-109930.6" + attribute \src "libresoc.v:109988.3-110006.6" wire width 2 $0\dec31_dec_sub24_in3_sel[1:0] - attribute \src "libresoc.v:109532.3-109550.6" + attribute \src "libresoc.v:109608.3-109626.6" wire width 7 $0\dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:109627.3-109645.6" + attribute \src "libresoc.v:109703.3-109721.6" wire $0\dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:109646.3-109664.6" + attribute \src "libresoc.v:109722.3-109740.6" wire $0\dec31_dec_sub24_inv_out[0:0] - attribute \src "libresoc.v:109760.3-109778.6" + attribute \src "libresoc.v:109836.3-109854.6" wire $0\dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:109513.3-109531.6" + attribute \src "libresoc.v:109589.3-109607.6" wire width 4 $0\dec31_dec_sub24_ldst_len[3:0] - attribute \src "libresoc.v:109798.3-109816.6" + attribute \src "libresoc.v:109874.3-109892.6" wire $0\dec31_dec_sub24_lk[0:0] - attribute \src "libresoc.v:109931.3-109949.6" + attribute \src "libresoc.v:110007.3-110025.6" wire width 3 $0\dec31_dec_sub24_out_sel[2:0] - attribute \src "libresoc.v:109570.3-109588.6" + attribute \src "libresoc.v:109646.3-109664.6" wire width 2 $0\dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:109722.3-109740.6" + attribute \src "libresoc.v:109798.3-109816.6" wire $0\dec31_dec_sub24_rsrv[0:0] - attribute \src "libresoc.v:109817.3-109835.6" + attribute \src "libresoc.v:109893.3-109911.6" wire $0\dec31_dec_sub24_sgl_pipe[0:0] - attribute \src "libresoc.v:109779.3-109797.6" + attribute \src "libresoc.v:109855.3-109873.6" wire $0\dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:109703.3-109721.6" + attribute \src "libresoc.v:109779.3-109797.6" wire $0\dec31_dec_sub24_sgn_ext[0:0] - attribute \src "libresoc.v:109475.3-109493.6" + attribute \src "libresoc.v:109551.3-109569.6" wire width 3 $0\dec31_dec_sub24_sv_cr_in[2:0] - attribute \src "libresoc.v:109494.3-109512.6" + attribute \src "libresoc.v:109570.3-109588.6" wire width 3 $0\dec31_dec_sub24_sv_cr_out[2:0] - attribute \src "libresoc.v:109380.3-109398.6" + attribute \src "libresoc.v:109456.3-109474.6" wire width 3 $0\dec31_dec_sub24_sv_in1[2:0] - attribute \src "libresoc.v:109399.3-109417.6" + attribute \src "libresoc.v:109475.3-109493.6" wire width 3 $0\dec31_dec_sub24_sv_in2[2:0] - attribute \src "libresoc.v:109418.3-109436.6" + attribute \src "libresoc.v:109494.3-109512.6" wire width 3 $0\dec31_dec_sub24_sv_in3[2:0] - attribute \src "libresoc.v:109456.3-109474.6" + attribute \src "libresoc.v:109532.3-109550.6" wire width 3 $0\dec31_dec_sub24_sv_out2[2:0] - attribute \src "libresoc.v:109437.3-109455.6" + attribute \src "libresoc.v:109513.3-109531.6" wire width 3 $0\dec31_dec_sub24_sv_out[2:0] - attribute \src "libresoc.v:109551.3-109569.6" + attribute \src "libresoc.v:109627.3-109645.6" wire width 2 $0\dec31_dec_sub24_upd[1:0] - attribute \src "libresoc.v:108975.7-108975.20" + attribute \src "libresoc.v:109051.7-109051.20" wire $0\initial[0:0] - attribute \src "libresoc.v:109836.3-109854.6" + attribute \src "libresoc.v:109912.3-109930.6" wire width 2 $1\dec31_dec_sub24_SV_Etype[1:0] - attribute \src "libresoc.v:109855.3-109873.6" + attribute \src "libresoc.v:109931.3-109949.6" wire width 2 $1\dec31_dec_sub24_SV_Ptype[1:0] - attribute \src "libresoc.v:109608.3-109626.6" - wire width 8 $1\dec31_dec_sub24_asmcode[7:0] attribute \src "libresoc.v:109684.3-109702.6" + wire width 8 $1\dec31_dec_sub24_asmcode[7:0] + attribute \src "libresoc.v:109760.3-109778.6" wire $1\dec31_dec_sub24_br[0:0] - attribute \src "libresoc.v:109342.3-109360.6" + attribute \src "libresoc.v:109418.3-109436.6" wire width 3 $1\dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:109361.3-109379.6" + attribute \src "libresoc.v:109437.3-109455.6" wire width 3 $1\dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:109589.3-109607.6" - wire width 2 $1\dec31_dec_sub24_cry_in[1:0] attribute \src "libresoc.v:109665.3-109683.6" - wire $1\dec31_dec_sub24_cry_out[0:0] + wire width 2 $1\dec31_dec_sub24_cry_in[1:0] attribute \src "libresoc.v:109741.3-109759.6" + wire $1\dec31_dec_sub24_cry_out[0:0] + attribute \src "libresoc.v:109817.3-109835.6" wire width 5 $1\dec31_dec_sub24_form[4:0] - attribute \src "libresoc.v:109323.3-109341.6" + attribute \src "libresoc.v:109399.3-109417.6" wire width 14 $1\dec31_dec_sub24_function_unit[13:0] - attribute \src "libresoc.v:109874.3-109892.6" + attribute \src "libresoc.v:109950.3-109968.6" wire width 3 $1\dec31_dec_sub24_in1_sel[2:0] - attribute \src "libresoc.v:109893.3-109911.6" + attribute \src "libresoc.v:109969.3-109987.6" wire width 4 $1\dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:109912.3-109930.6" + attribute \src "libresoc.v:109988.3-110006.6" wire width 2 $1\dec31_dec_sub24_in3_sel[1:0] - attribute \src "libresoc.v:109532.3-109550.6" + attribute \src "libresoc.v:109608.3-109626.6" wire width 7 $1\dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:109627.3-109645.6" + attribute \src "libresoc.v:109703.3-109721.6" wire $1\dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:109646.3-109664.6" + attribute \src "libresoc.v:109722.3-109740.6" wire $1\dec31_dec_sub24_inv_out[0:0] - attribute \src "libresoc.v:109760.3-109778.6" + attribute \src "libresoc.v:109836.3-109854.6" wire $1\dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:109513.3-109531.6" + attribute \src "libresoc.v:109589.3-109607.6" wire width 4 $1\dec31_dec_sub24_ldst_len[3:0] - attribute \src "libresoc.v:109798.3-109816.6" + attribute \src "libresoc.v:109874.3-109892.6" wire $1\dec31_dec_sub24_lk[0:0] - attribute \src "libresoc.v:109931.3-109949.6" + attribute \src "libresoc.v:110007.3-110025.6" wire width 3 $1\dec31_dec_sub24_out_sel[2:0] - attribute \src "libresoc.v:109570.3-109588.6" + attribute \src "libresoc.v:109646.3-109664.6" wire width 2 $1\dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:109722.3-109740.6" + attribute \src "libresoc.v:109798.3-109816.6" wire $1\dec31_dec_sub24_rsrv[0:0] - attribute \src "libresoc.v:109817.3-109835.6" + attribute \src "libresoc.v:109893.3-109911.6" wire $1\dec31_dec_sub24_sgl_pipe[0:0] - attribute \src "libresoc.v:109779.3-109797.6" + attribute \src "libresoc.v:109855.3-109873.6" wire $1\dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:109703.3-109721.6" + attribute \src "libresoc.v:109779.3-109797.6" wire $1\dec31_dec_sub24_sgn_ext[0:0] - attribute \src "libresoc.v:109475.3-109493.6" + attribute \src "libresoc.v:109551.3-109569.6" wire width 3 $1\dec31_dec_sub24_sv_cr_in[2:0] - attribute \src "libresoc.v:109494.3-109512.6" + attribute \src "libresoc.v:109570.3-109588.6" wire width 3 $1\dec31_dec_sub24_sv_cr_out[2:0] - attribute \src "libresoc.v:109380.3-109398.6" + attribute \src "libresoc.v:109456.3-109474.6" wire width 3 $1\dec31_dec_sub24_sv_in1[2:0] - attribute \src "libresoc.v:109399.3-109417.6" + attribute \src "libresoc.v:109475.3-109493.6" wire width 3 $1\dec31_dec_sub24_sv_in2[2:0] - attribute \src "libresoc.v:109418.3-109436.6" + attribute \src "libresoc.v:109494.3-109512.6" wire width 3 $1\dec31_dec_sub24_sv_in3[2:0] - attribute \src "libresoc.v:109456.3-109474.6" + attribute \src "libresoc.v:109532.3-109550.6" wire width 3 $1\dec31_dec_sub24_sv_out2[2:0] - attribute \src "libresoc.v:109437.3-109455.6" + attribute \src "libresoc.v:109513.3-109531.6" wire width 3 $1\dec31_dec_sub24_sv_out[2:0] - attribute \src "libresoc.v:109551.3-109569.6" + attribute \src "libresoc.v:109627.3-109645.6" wire width 2 $1\dec31_dec_sub24_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -170038,28 +170101,28 @@ module \dec31_dec_sub24 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub24_upd - attribute \src "libresoc.v:108975.7-108975.15" + attribute \src "libresoc.v:109051.7-109051.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:108975.7-108975.20" - process $proc$libresoc.v:108975$4258 + attribute \src "libresoc.v:109051.7-109051.20" + process $proc$libresoc.v:109051$4258 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:109323.3-109341.6" - process $proc$libresoc.v:109323$4225 + attribute \src "libresoc.v:109399.3-109417.6" + process $proc$libresoc.v:109399$4225 assign { } { } assign { } { } assign $0\dec31_dec_sub24_function_unit[13:0] $1\dec31_dec_sub24_function_unit[13:0] - attribute \src "libresoc.v:109324.5-109324.29" + attribute \src "libresoc.v:109400.5-109400.29" switch \initial - attribute \src "libresoc.v:109324.9-109324.17" + attribute \src "libresoc.v:109400.9-109400.17" case 1'1 case end @@ -170087,14 +170150,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_function_unit $0\dec31_dec_sub24_function_unit[13:0] end - attribute \src "libresoc.v:109342.3-109360.6" - process $proc$libresoc.v:109342$4226 + attribute \src "libresoc.v:109418.3-109436.6" + process $proc$libresoc.v:109418$4226 assign { } { } assign { } { } assign $0\dec31_dec_sub24_cr_in[2:0] $1\dec31_dec_sub24_cr_in[2:0] - attribute \src "libresoc.v:109343.5-109343.29" + attribute \src "libresoc.v:109419.5-109419.29" switch \initial - attribute \src "libresoc.v:109343.9-109343.17" + attribute \src "libresoc.v:109419.9-109419.17" case 1'1 case end @@ -170122,14 +170185,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_cr_in $0\dec31_dec_sub24_cr_in[2:0] end - attribute \src "libresoc.v:109361.3-109379.6" - process $proc$libresoc.v:109361$4227 + attribute \src "libresoc.v:109437.3-109455.6" + process $proc$libresoc.v:109437$4227 assign { } { } assign { } { } assign $0\dec31_dec_sub24_cr_out[2:0] $1\dec31_dec_sub24_cr_out[2:0] - attribute \src "libresoc.v:109362.5-109362.29" + attribute \src "libresoc.v:109438.5-109438.29" switch \initial - attribute \src "libresoc.v:109362.9-109362.17" + attribute \src "libresoc.v:109438.9-109438.17" case 1'1 case end @@ -170157,14 +170220,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_cr_out $0\dec31_dec_sub24_cr_out[2:0] end - attribute \src "libresoc.v:109380.3-109398.6" - process $proc$libresoc.v:109380$4228 + attribute \src "libresoc.v:109456.3-109474.6" + process $proc$libresoc.v:109456$4228 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_in1[2:0] $1\dec31_dec_sub24_sv_in1[2:0] - attribute \src "libresoc.v:109381.5-109381.29" + attribute \src "libresoc.v:109457.5-109457.29" switch \initial - attribute \src "libresoc.v:109381.9-109381.17" + attribute \src "libresoc.v:109457.9-109457.17" case 1'1 case end @@ -170192,14 +170255,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_in1 $0\dec31_dec_sub24_sv_in1[2:0] end - attribute \src "libresoc.v:109399.3-109417.6" - process $proc$libresoc.v:109399$4229 + attribute \src "libresoc.v:109475.3-109493.6" + process $proc$libresoc.v:109475$4229 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_in2[2:0] $1\dec31_dec_sub24_sv_in2[2:0] - attribute \src "libresoc.v:109400.5-109400.29" + attribute \src "libresoc.v:109476.5-109476.29" switch \initial - attribute \src "libresoc.v:109400.9-109400.17" + attribute \src "libresoc.v:109476.9-109476.17" case 1'1 case end @@ -170227,14 +170290,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_in2 $0\dec31_dec_sub24_sv_in2[2:0] end - attribute \src "libresoc.v:109418.3-109436.6" - process $proc$libresoc.v:109418$4230 + attribute \src "libresoc.v:109494.3-109512.6" + process $proc$libresoc.v:109494$4230 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_in3[2:0] $1\dec31_dec_sub24_sv_in3[2:0] - attribute \src "libresoc.v:109419.5-109419.29" + attribute \src "libresoc.v:109495.5-109495.29" switch \initial - attribute \src "libresoc.v:109419.9-109419.17" + attribute \src "libresoc.v:109495.9-109495.17" case 1'1 case end @@ -170262,14 +170325,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_in3 $0\dec31_dec_sub24_sv_in3[2:0] end - attribute \src "libresoc.v:109437.3-109455.6" - process $proc$libresoc.v:109437$4231 + attribute \src "libresoc.v:109513.3-109531.6" + process $proc$libresoc.v:109513$4231 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_out[2:0] $1\dec31_dec_sub24_sv_out[2:0] - attribute \src "libresoc.v:109438.5-109438.29" + attribute \src "libresoc.v:109514.5-109514.29" switch \initial - attribute \src "libresoc.v:109438.9-109438.17" + attribute \src "libresoc.v:109514.9-109514.17" case 1'1 case end @@ -170297,14 +170360,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_out $0\dec31_dec_sub24_sv_out[2:0] end - attribute \src "libresoc.v:109456.3-109474.6" - process $proc$libresoc.v:109456$4232 + attribute \src "libresoc.v:109532.3-109550.6" + process $proc$libresoc.v:109532$4232 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_out2[2:0] $1\dec31_dec_sub24_sv_out2[2:0] - attribute \src "libresoc.v:109457.5-109457.29" + attribute \src "libresoc.v:109533.5-109533.29" switch \initial - attribute \src "libresoc.v:109457.9-109457.17" + attribute \src "libresoc.v:109533.9-109533.17" case 1'1 case end @@ -170332,14 +170395,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_out2 $0\dec31_dec_sub24_sv_out2[2:0] end - attribute \src "libresoc.v:109475.3-109493.6" - process $proc$libresoc.v:109475$4233 + attribute \src "libresoc.v:109551.3-109569.6" + process $proc$libresoc.v:109551$4233 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_cr_in[2:0] $1\dec31_dec_sub24_sv_cr_in[2:0] - attribute \src "libresoc.v:109476.5-109476.29" + attribute \src "libresoc.v:109552.5-109552.29" switch \initial - attribute \src "libresoc.v:109476.9-109476.17" + attribute \src "libresoc.v:109552.9-109552.17" case 1'1 case end @@ -170367,14 +170430,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_cr_in $0\dec31_dec_sub24_sv_cr_in[2:0] end - attribute \src "libresoc.v:109494.3-109512.6" - process $proc$libresoc.v:109494$4234 + attribute \src "libresoc.v:109570.3-109588.6" + process $proc$libresoc.v:109570$4234 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sv_cr_out[2:0] $1\dec31_dec_sub24_sv_cr_out[2:0] - attribute \src "libresoc.v:109495.5-109495.29" + attribute \src "libresoc.v:109571.5-109571.29" switch \initial - attribute \src "libresoc.v:109495.9-109495.17" + attribute \src "libresoc.v:109571.9-109571.17" case 1'1 case end @@ -170402,14 +170465,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sv_cr_out $0\dec31_dec_sub24_sv_cr_out[2:0] end - attribute \src "libresoc.v:109513.3-109531.6" - process $proc$libresoc.v:109513$4235 + attribute \src "libresoc.v:109589.3-109607.6" + process $proc$libresoc.v:109589$4235 assign { } { } assign { } { } assign $0\dec31_dec_sub24_ldst_len[3:0] $1\dec31_dec_sub24_ldst_len[3:0] - attribute \src "libresoc.v:109514.5-109514.29" + attribute \src "libresoc.v:109590.5-109590.29" switch \initial - attribute \src "libresoc.v:109514.9-109514.17" + attribute \src "libresoc.v:109590.9-109590.17" case 1'1 case end @@ -170437,14 +170500,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_ldst_len $0\dec31_dec_sub24_ldst_len[3:0] end - attribute \src "libresoc.v:109532.3-109550.6" - process $proc$libresoc.v:109532$4236 + attribute \src "libresoc.v:109608.3-109626.6" + process $proc$libresoc.v:109608$4236 assign { } { } assign { } { } assign $0\dec31_dec_sub24_internal_op[6:0] $1\dec31_dec_sub24_internal_op[6:0] - attribute \src "libresoc.v:109533.5-109533.29" + attribute \src "libresoc.v:109609.5-109609.29" switch \initial - attribute \src "libresoc.v:109533.9-109533.17" + attribute \src "libresoc.v:109609.9-109609.17" case 1'1 case end @@ -170472,14 +170535,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_internal_op $0\dec31_dec_sub24_internal_op[6:0] end - attribute \src "libresoc.v:109551.3-109569.6" - process $proc$libresoc.v:109551$4237 + attribute \src "libresoc.v:109627.3-109645.6" + process $proc$libresoc.v:109627$4237 assign { } { } assign { } { } assign $0\dec31_dec_sub24_upd[1:0] $1\dec31_dec_sub24_upd[1:0] - attribute \src "libresoc.v:109552.5-109552.29" + attribute \src "libresoc.v:109628.5-109628.29" switch \initial - attribute \src "libresoc.v:109552.9-109552.17" + attribute \src "libresoc.v:109628.9-109628.17" case 1'1 case end @@ -170507,14 +170570,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_upd $0\dec31_dec_sub24_upd[1:0] end - attribute \src "libresoc.v:109570.3-109588.6" - process $proc$libresoc.v:109570$4238 + attribute \src "libresoc.v:109646.3-109664.6" + process $proc$libresoc.v:109646$4238 assign { } { } assign { } { } assign $0\dec31_dec_sub24_rc_sel[1:0] $1\dec31_dec_sub24_rc_sel[1:0] - attribute \src "libresoc.v:109571.5-109571.29" + attribute \src "libresoc.v:109647.5-109647.29" switch \initial - attribute \src "libresoc.v:109571.9-109571.17" + attribute \src "libresoc.v:109647.9-109647.17" case 1'1 case end @@ -170542,14 +170605,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_rc_sel $0\dec31_dec_sub24_rc_sel[1:0] end - attribute \src "libresoc.v:109589.3-109607.6" - process $proc$libresoc.v:109589$4239 + attribute \src "libresoc.v:109665.3-109683.6" + process $proc$libresoc.v:109665$4239 assign { } { } assign { } { } assign $0\dec31_dec_sub24_cry_in[1:0] $1\dec31_dec_sub24_cry_in[1:0] - attribute \src "libresoc.v:109590.5-109590.29" + attribute \src "libresoc.v:109666.5-109666.29" switch \initial - attribute \src "libresoc.v:109590.9-109590.17" + attribute \src "libresoc.v:109666.9-109666.17" case 1'1 case end @@ -170577,14 +170640,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_cry_in $0\dec31_dec_sub24_cry_in[1:0] end - attribute \src "libresoc.v:109608.3-109626.6" - process $proc$libresoc.v:109608$4240 + attribute \src "libresoc.v:109684.3-109702.6" + process $proc$libresoc.v:109684$4240 assign { } { } assign { } { } assign $0\dec31_dec_sub24_asmcode[7:0] $1\dec31_dec_sub24_asmcode[7:0] - attribute \src "libresoc.v:109609.5-109609.29" + attribute \src "libresoc.v:109685.5-109685.29" switch \initial - attribute \src "libresoc.v:109609.9-109609.17" + attribute \src "libresoc.v:109685.9-109685.17" case 1'1 case end @@ -170612,14 +170675,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_asmcode $0\dec31_dec_sub24_asmcode[7:0] end - attribute \src "libresoc.v:109627.3-109645.6" - process $proc$libresoc.v:109627$4241 + attribute \src "libresoc.v:109703.3-109721.6" + process $proc$libresoc.v:109703$4241 assign { } { } assign { } { } assign $0\dec31_dec_sub24_inv_a[0:0] $1\dec31_dec_sub24_inv_a[0:0] - attribute \src "libresoc.v:109628.5-109628.29" + attribute \src "libresoc.v:109704.5-109704.29" switch \initial - attribute \src "libresoc.v:109628.9-109628.17" + attribute \src "libresoc.v:109704.9-109704.17" case 1'1 case end @@ -170647,14 +170710,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_inv_a $0\dec31_dec_sub24_inv_a[0:0] end - attribute \src "libresoc.v:109646.3-109664.6" - process $proc$libresoc.v:109646$4242 + attribute \src "libresoc.v:109722.3-109740.6" + process $proc$libresoc.v:109722$4242 assign { } { } assign { } { } assign $0\dec31_dec_sub24_inv_out[0:0] $1\dec31_dec_sub24_inv_out[0:0] - attribute \src "libresoc.v:109647.5-109647.29" + attribute \src "libresoc.v:109723.5-109723.29" switch \initial - attribute \src "libresoc.v:109647.9-109647.17" + attribute \src "libresoc.v:109723.9-109723.17" case 1'1 case end @@ -170682,14 +170745,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_inv_out $0\dec31_dec_sub24_inv_out[0:0] end - attribute \src "libresoc.v:109665.3-109683.6" - process $proc$libresoc.v:109665$4243 + attribute \src "libresoc.v:109741.3-109759.6" + process $proc$libresoc.v:109741$4243 assign { } { } assign { } { } assign $0\dec31_dec_sub24_cry_out[0:0] $1\dec31_dec_sub24_cry_out[0:0] - attribute \src "libresoc.v:109666.5-109666.29" + attribute \src "libresoc.v:109742.5-109742.29" switch \initial - attribute \src "libresoc.v:109666.9-109666.17" + attribute \src "libresoc.v:109742.9-109742.17" case 1'1 case end @@ -170717,14 +170780,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_cry_out $0\dec31_dec_sub24_cry_out[0:0] end - attribute \src "libresoc.v:109684.3-109702.6" - process $proc$libresoc.v:109684$4244 + attribute \src "libresoc.v:109760.3-109778.6" + process $proc$libresoc.v:109760$4244 assign { } { } assign { } { } assign $0\dec31_dec_sub24_br[0:0] $1\dec31_dec_sub24_br[0:0] - attribute \src "libresoc.v:109685.5-109685.29" + attribute \src "libresoc.v:109761.5-109761.29" switch \initial - attribute \src "libresoc.v:109685.9-109685.17" + attribute \src "libresoc.v:109761.9-109761.17" case 1'1 case end @@ -170752,14 +170815,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_br $0\dec31_dec_sub24_br[0:0] end - attribute \src "libresoc.v:109703.3-109721.6" - process $proc$libresoc.v:109703$4245 + attribute \src "libresoc.v:109779.3-109797.6" + process $proc$libresoc.v:109779$4245 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sgn_ext[0:0] $1\dec31_dec_sub24_sgn_ext[0:0] - attribute \src "libresoc.v:109704.5-109704.29" + attribute \src "libresoc.v:109780.5-109780.29" switch \initial - attribute \src "libresoc.v:109704.9-109704.17" + attribute \src "libresoc.v:109780.9-109780.17" case 1'1 case end @@ -170787,14 +170850,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sgn_ext $0\dec31_dec_sub24_sgn_ext[0:0] end - attribute \src "libresoc.v:109722.3-109740.6" - process $proc$libresoc.v:109722$4246 + attribute \src "libresoc.v:109798.3-109816.6" + process $proc$libresoc.v:109798$4246 assign { } { } assign { } { } assign $0\dec31_dec_sub24_rsrv[0:0] $1\dec31_dec_sub24_rsrv[0:0] - attribute \src "libresoc.v:109723.5-109723.29" + attribute \src "libresoc.v:109799.5-109799.29" switch \initial - attribute \src "libresoc.v:109723.9-109723.17" + attribute \src "libresoc.v:109799.9-109799.17" case 1'1 case end @@ -170822,14 +170885,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_rsrv $0\dec31_dec_sub24_rsrv[0:0] end - attribute \src "libresoc.v:109741.3-109759.6" - process $proc$libresoc.v:109741$4247 + attribute \src "libresoc.v:109817.3-109835.6" + process $proc$libresoc.v:109817$4247 assign { } { } assign { } { } assign $0\dec31_dec_sub24_form[4:0] $1\dec31_dec_sub24_form[4:0] - attribute \src "libresoc.v:109742.5-109742.29" + attribute \src "libresoc.v:109818.5-109818.29" switch \initial - attribute \src "libresoc.v:109742.9-109742.17" + attribute \src "libresoc.v:109818.9-109818.17" case 1'1 case end @@ -170857,14 +170920,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_form $0\dec31_dec_sub24_form[4:0] end - attribute \src "libresoc.v:109760.3-109778.6" - process $proc$libresoc.v:109760$4248 + attribute \src "libresoc.v:109836.3-109854.6" + process $proc$libresoc.v:109836$4248 assign { } { } assign { } { } assign $0\dec31_dec_sub24_is_32b[0:0] $1\dec31_dec_sub24_is_32b[0:0] - attribute \src "libresoc.v:109761.5-109761.29" + attribute \src "libresoc.v:109837.5-109837.29" switch \initial - attribute \src "libresoc.v:109761.9-109761.17" + attribute \src "libresoc.v:109837.9-109837.17" case 1'1 case end @@ -170892,14 +170955,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_is_32b $0\dec31_dec_sub24_is_32b[0:0] end - attribute \src "libresoc.v:109779.3-109797.6" - process $proc$libresoc.v:109779$4249 + attribute \src "libresoc.v:109855.3-109873.6" + process $proc$libresoc.v:109855$4249 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sgn[0:0] $1\dec31_dec_sub24_sgn[0:0] - attribute \src "libresoc.v:109780.5-109780.29" + attribute \src "libresoc.v:109856.5-109856.29" switch \initial - attribute \src "libresoc.v:109780.9-109780.17" + attribute \src "libresoc.v:109856.9-109856.17" case 1'1 case end @@ -170927,14 +170990,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sgn $0\dec31_dec_sub24_sgn[0:0] end - attribute \src "libresoc.v:109798.3-109816.6" - process $proc$libresoc.v:109798$4250 + attribute \src "libresoc.v:109874.3-109892.6" + process $proc$libresoc.v:109874$4250 assign { } { } assign { } { } assign $0\dec31_dec_sub24_lk[0:0] $1\dec31_dec_sub24_lk[0:0] - attribute \src "libresoc.v:109799.5-109799.29" + attribute \src "libresoc.v:109875.5-109875.29" switch \initial - attribute \src "libresoc.v:109799.9-109799.17" + attribute \src "libresoc.v:109875.9-109875.17" case 1'1 case end @@ -170962,14 +171025,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_lk $0\dec31_dec_sub24_lk[0:0] end - attribute \src "libresoc.v:109817.3-109835.6" - process $proc$libresoc.v:109817$4251 + attribute \src "libresoc.v:109893.3-109911.6" + process $proc$libresoc.v:109893$4251 assign { } { } assign { } { } assign $0\dec31_dec_sub24_sgl_pipe[0:0] $1\dec31_dec_sub24_sgl_pipe[0:0] - attribute \src "libresoc.v:109818.5-109818.29" + attribute \src "libresoc.v:109894.5-109894.29" switch \initial - attribute \src "libresoc.v:109818.9-109818.17" + attribute \src "libresoc.v:109894.9-109894.17" case 1'1 case end @@ -170997,14 +171060,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_sgl_pipe $0\dec31_dec_sub24_sgl_pipe[0:0] end - attribute \src "libresoc.v:109836.3-109854.6" - process $proc$libresoc.v:109836$4252 + attribute \src "libresoc.v:109912.3-109930.6" + process $proc$libresoc.v:109912$4252 assign { } { } assign { } { } assign $0\dec31_dec_sub24_SV_Etype[1:0] $1\dec31_dec_sub24_SV_Etype[1:0] - attribute \src "libresoc.v:109837.5-109837.29" + attribute \src "libresoc.v:109913.5-109913.29" switch \initial - attribute \src "libresoc.v:109837.9-109837.17" + attribute \src "libresoc.v:109913.9-109913.17" case 1'1 case end @@ -171032,14 +171095,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_SV_Etype $0\dec31_dec_sub24_SV_Etype[1:0] end - attribute \src "libresoc.v:109855.3-109873.6" - process $proc$libresoc.v:109855$4253 + attribute \src "libresoc.v:109931.3-109949.6" + process $proc$libresoc.v:109931$4253 assign { } { } assign { } { } assign $0\dec31_dec_sub24_SV_Ptype[1:0] $1\dec31_dec_sub24_SV_Ptype[1:0] - attribute \src "libresoc.v:109856.5-109856.29" + attribute \src "libresoc.v:109932.5-109932.29" switch \initial - attribute \src "libresoc.v:109856.9-109856.17" + attribute \src "libresoc.v:109932.9-109932.17" case 1'1 case end @@ -171067,14 +171130,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_SV_Ptype $0\dec31_dec_sub24_SV_Ptype[1:0] end - attribute \src "libresoc.v:109874.3-109892.6" - process $proc$libresoc.v:109874$4254 + attribute \src "libresoc.v:109950.3-109968.6" + process $proc$libresoc.v:109950$4254 assign { } { } assign { } { } assign $0\dec31_dec_sub24_in1_sel[2:0] $1\dec31_dec_sub24_in1_sel[2:0] - attribute \src "libresoc.v:109875.5-109875.29" + attribute \src "libresoc.v:109951.5-109951.29" switch \initial - attribute \src "libresoc.v:109875.9-109875.17" + attribute \src "libresoc.v:109951.9-109951.17" case 1'1 case end @@ -171102,14 +171165,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_in1_sel $0\dec31_dec_sub24_in1_sel[2:0] end - attribute \src "libresoc.v:109893.3-109911.6" - process $proc$libresoc.v:109893$4255 + attribute \src "libresoc.v:109969.3-109987.6" + process $proc$libresoc.v:109969$4255 assign { } { } assign { } { } assign $0\dec31_dec_sub24_in2_sel[3:0] $1\dec31_dec_sub24_in2_sel[3:0] - attribute \src "libresoc.v:109894.5-109894.29" + attribute \src "libresoc.v:109970.5-109970.29" switch \initial - attribute \src "libresoc.v:109894.9-109894.17" + attribute \src "libresoc.v:109970.9-109970.17" case 1'1 case end @@ -171137,14 +171200,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_in2_sel $0\dec31_dec_sub24_in2_sel[3:0] end - attribute \src "libresoc.v:109912.3-109930.6" - process $proc$libresoc.v:109912$4256 + attribute \src "libresoc.v:109988.3-110006.6" + process $proc$libresoc.v:109988$4256 assign { } { } assign { } { } assign $0\dec31_dec_sub24_in3_sel[1:0] $1\dec31_dec_sub24_in3_sel[1:0] - attribute \src "libresoc.v:109913.5-109913.29" + attribute \src "libresoc.v:109989.5-109989.29" switch \initial - attribute \src "libresoc.v:109913.9-109913.17" + attribute \src "libresoc.v:109989.9-109989.17" case 1'1 case end @@ -171172,14 +171235,14 @@ module \dec31_dec_sub24 sync always update \dec31_dec_sub24_in3_sel $0\dec31_dec_sub24_in3_sel[1:0] end - attribute \src "libresoc.v:109931.3-109949.6" - process $proc$libresoc.v:109931$4257 + attribute \src "libresoc.v:110007.3-110025.6" + process $proc$libresoc.v:110007$4257 assign { } { } assign { } { } assign $0\dec31_dec_sub24_out_sel[2:0] $1\dec31_dec_sub24_out_sel[2:0] - attribute \src "libresoc.v:109932.5-109932.29" + attribute \src "libresoc.v:110008.5-110008.29" switch \initial - attribute \src "libresoc.v:109932.9-109932.17" + attribute \src "libresoc.v:110008.9-110008.17" case 1'1 case end @@ -171209,144 +171272,144 @@ module \dec31_dec_sub24 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:109955.1-112021.10" +attribute \src "libresoc.v:110031.1-112097.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub26" attribute \generator "nMigen" module \dec31_dec_sub26 - attribute \src "libresoc.v:111708.3-111759.6" + attribute \src "libresoc.v:111784.3-111835.6" wire width 2 $0\dec31_dec_sub26_SV_Etype[1:0] - attribute \src "libresoc.v:111760.3-111811.6" + attribute \src "libresoc.v:111836.3-111887.6" wire width 2 $0\dec31_dec_sub26_SV_Ptype[1:0] - attribute \src "libresoc.v:111084.3-111135.6" + attribute \src "libresoc.v:111160.3-111211.6" wire width 8 $0\dec31_dec_sub26_asmcode[7:0] - attribute \src "libresoc.v:111292.3-111343.6" + attribute \src "libresoc.v:111368.3-111419.6" wire $0\dec31_dec_sub26_br[0:0] - attribute \src "libresoc.v:110356.3-110407.6" + attribute \src "libresoc.v:110432.3-110483.6" wire width 3 $0\dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:110408.3-110459.6" + attribute \src "libresoc.v:110484.3-110535.6" wire width 3 $0\dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:111032.3-111083.6" + attribute \src "libresoc.v:111108.3-111159.6" wire width 2 $0\dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:111240.3-111291.6" + attribute \src "libresoc.v:111316.3-111367.6" wire $0\dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:111448.3-111499.6" + attribute \src "libresoc.v:111524.3-111575.6" wire width 5 $0\dec31_dec_sub26_form[4:0] - attribute \src "libresoc.v:110304.3-110355.6" + attribute \src "libresoc.v:110380.3-110431.6" wire width 14 $0\dec31_dec_sub26_function_unit[13:0] - attribute \src "libresoc.v:111812.3-111863.6" + attribute \src "libresoc.v:111888.3-111939.6" wire width 3 $0\dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:111864.3-111915.6" + attribute \src "libresoc.v:111940.3-111991.6" wire width 4 $0\dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:111916.3-111967.6" + attribute \src "libresoc.v:111992.3-112043.6" wire width 2 $0\dec31_dec_sub26_in3_sel[1:0] - attribute \src "libresoc.v:110876.3-110927.6" + attribute \src "libresoc.v:110952.3-111003.6" wire width 7 $0\dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:111136.3-111187.6" + attribute \src "libresoc.v:111212.3-111263.6" wire $0\dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:111188.3-111239.6" + attribute \src "libresoc.v:111264.3-111315.6" wire $0\dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:111500.3-111551.6" + attribute \src "libresoc.v:111576.3-111627.6" wire $0\dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:110824.3-110875.6" + attribute \src "libresoc.v:110900.3-110951.6" wire width 4 $0\dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:111604.3-111655.6" + attribute \src "libresoc.v:111680.3-111731.6" wire $0\dec31_dec_sub26_lk[0:0] - attribute \src "libresoc.v:111968.3-112019.6" + attribute \src "libresoc.v:112044.3-112095.6" wire width 3 $0\dec31_dec_sub26_out_sel[2:0] - attribute \src "libresoc.v:110980.3-111031.6" + attribute \src "libresoc.v:111056.3-111107.6" wire width 2 $0\dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:111396.3-111447.6" + attribute \src "libresoc.v:111472.3-111523.6" wire $0\dec31_dec_sub26_rsrv[0:0] - attribute \src "libresoc.v:111656.3-111707.6" + attribute \src "libresoc.v:111732.3-111783.6" wire $0\dec31_dec_sub26_sgl_pipe[0:0] - attribute \src "libresoc.v:111552.3-111603.6" + attribute \src "libresoc.v:111628.3-111679.6" wire $0\dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:111344.3-111395.6" + attribute \src "libresoc.v:111420.3-111471.6" wire $0\dec31_dec_sub26_sgn_ext[0:0] - attribute \src "libresoc.v:110720.3-110771.6" + attribute \src "libresoc.v:110796.3-110847.6" wire width 3 $0\dec31_dec_sub26_sv_cr_in[2:0] - attribute \src "libresoc.v:110772.3-110823.6" + attribute \src "libresoc.v:110848.3-110899.6" wire width 3 $0\dec31_dec_sub26_sv_cr_out[2:0] - attribute \src "libresoc.v:110460.3-110511.6" + attribute \src "libresoc.v:110536.3-110587.6" wire width 3 $0\dec31_dec_sub26_sv_in1[2:0] - attribute \src "libresoc.v:110512.3-110563.6" + attribute \src "libresoc.v:110588.3-110639.6" wire width 3 $0\dec31_dec_sub26_sv_in2[2:0] - attribute \src "libresoc.v:110564.3-110615.6" + attribute \src "libresoc.v:110640.3-110691.6" wire width 3 $0\dec31_dec_sub26_sv_in3[2:0] - attribute \src "libresoc.v:110668.3-110719.6" + attribute \src "libresoc.v:110744.3-110795.6" wire width 3 $0\dec31_dec_sub26_sv_out2[2:0] - attribute \src "libresoc.v:110616.3-110667.6" + attribute \src "libresoc.v:110692.3-110743.6" wire width 3 $0\dec31_dec_sub26_sv_out[2:0] - attribute \src "libresoc.v:110928.3-110979.6" + attribute \src "libresoc.v:111004.3-111055.6" wire width 2 $0\dec31_dec_sub26_upd[1:0] - attribute \src "libresoc.v:109956.7-109956.20" + attribute \src "libresoc.v:110032.7-110032.20" wire $0\initial[0:0] - attribute \src "libresoc.v:111708.3-111759.6" + attribute \src "libresoc.v:111784.3-111835.6" wire width 2 $1\dec31_dec_sub26_SV_Etype[1:0] - attribute \src "libresoc.v:111760.3-111811.6" + attribute \src "libresoc.v:111836.3-111887.6" wire width 2 $1\dec31_dec_sub26_SV_Ptype[1:0] - attribute \src "libresoc.v:111084.3-111135.6" + attribute \src "libresoc.v:111160.3-111211.6" wire width 8 $1\dec31_dec_sub26_asmcode[7:0] - attribute \src "libresoc.v:111292.3-111343.6" + attribute \src "libresoc.v:111368.3-111419.6" wire $1\dec31_dec_sub26_br[0:0] - attribute \src "libresoc.v:110356.3-110407.6" + attribute \src "libresoc.v:110432.3-110483.6" wire width 3 $1\dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:110408.3-110459.6" + attribute \src "libresoc.v:110484.3-110535.6" wire width 3 $1\dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:111032.3-111083.6" + attribute \src "libresoc.v:111108.3-111159.6" wire width 2 $1\dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:111240.3-111291.6" + attribute \src "libresoc.v:111316.3-111367.6" wire $1\dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:111448.3-111499.6" + attribute \src "libresoc.v:111524.3-111575.6" wire width 5 $1\dec31_dec_sub26_form[4:0] - attribute \src "libresoc.v:110304.3-110355.6" + attribute \src "libresoc.v:110380.3-110431.6" wire width 14 $1\dec31_dec_sub26_function_unit[13:0] - attribute \src "libresoc.v:111812.3-111863.6" + attribute \src "libresoc.v:111888.3-111939.6" wire width 3 $1\dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:111864.3-111915.6" + attribute \src "libresoc.v:111940.3-111991.6" wire width 4 $1\dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:111916.3-111967.6" + attribute \src "libresoc.v:111992.3-112043.6" wire width 2 $1\dec31_dec_sub26_in3_sel[1:0] - attribute \src "libresoc.v:110876.3-110927.6" + attribute \src "libresoc.v:110952.3-111003.6" wire width 7 $1\dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:111136.3-111187.6" + attribute \src "libresoc.v:111212.3-111263.6" wire $1\dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:111188.3-111239.6" + attribute \src "libresoc.v:111264.3-111315.6" wire $1\dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:111500.3-111551.6" + attribute \src "libresoc.v:111576.3-111627.6" wire $1\dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:110824.3-110875.6" + attribute \src "libresoc.v:110900.3-110951.6" wire width 4 $1\dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:111604.3-111655.6" + attribute \src "libresoc.v:111680.3-111731.6" wire $1\dec31_dec_sub26_lk[0:0] - attribute \src "libresoc.v:111968.3-112019.6" + attribute \src "libresoc.v:112044.3-112095.6" wire width 3 $1\dec31_dec_sub26_out_sel[2:0] - attribute \src "libresoc.v:110980.3-111031.6" + attribute \src "libresoc.v:111056.3-111107.6" wire width 2 $1\dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:111396.3-111447.6" + attribute \src "libresoc.v:111472.3-111523.6" wire $1\dec31_dec_sub26_rsrv[0:0] - attribute \src "libresoc.v:111656.3-111707.6" + attribute \src "libresoc.v:111732.3-111783.6" wire $1\dec31_dec_sub26_sgl_pipe[0:0] - attribute \src "libresoc.v:111552.3-111603.6" + attribute \src "libresoc.v:111628.3-111679.6" wire $1\dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:111344.3-111395.6" + attribute \src "libresoc.v:111420.3-111471.6" wire $1\dec31_dec_sub26_sgn_ext[0:0] - attribute \src "libresoc.v:110720.3-110771.6" + attribute \src "libresoc.v:110796.3-110847.6" wire width 3 $1\dec31_dec_sub26_sv_cr_in[2:0] - attribute \src "libresoc.v:110772.3-110823.6" + attribute \src "libresoc.v:110848.3-110899.6" wire width 3 $1\dec31_dec_sub26_sv_cr_out[2:0] - attribute \src "libresoc.v:110460.3-110511.6" + attribute \src "libresoc.v:110536.3-110587.6" wire width 3 $1\dec31_dec_sub26_sv_in1[2:0] - attribute \src "libresoc.v:110512.3-110563.6" + attribute \src "libresoc.v:110588.3-110639.6" wire width 3 $1\dec31_dec_sub26_sv_in2[2:0] - attribute \src "libresoc.v:110564.3-110615.6" + attribute \src "libresoc.v:110640.3-110691.6" wire width 3 $1\dec31_dec_sub26_sv_in3[2:0] - attribute \src "libresoc.v:110668.3-110719.6" + attribute \src "libresoc.v:110744.3-110795.6" wire width 3 $1\dec31_dec_sub26_sv_out2[2:0] - attribute \src "libresoc.v:110616.3-110667.6" + attribute \src "libresoc.v:110692.3-110743.6" wire width 3 $1\dec31_dec_sub26_sv_out[2:0] - attribute \src "libresoc.v:110928.3-110979.6" + attribute \src "libresoc.v:111004.3-111055.6" wire width 2 $1\dec31_dec_sub26_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -171658,28 +171721,28 @@ module \dec31_dec_sub26 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub26_upd - attribute \src "libresoc.v:109956.7-109956.15" + attribute \src "libresoc.v:110032.7-110032.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:109956.7-109956.20" - process $proc$libresoc.v:109956$4292 + attribute \src "libresoc.v:110032.7-110032.20" + process $proc$libresoc.v:110032$4292 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:110304.3-110355.6" - process $proc$libresoc.v:110304$4259 + attribute \src "libresoc.v:110380.3-110431.6" + process $proc$libresoc.v:110380$4259 assign { } { } assign { } { } assign $0\dec31_dec_sub26_function_unit[13:0] $1\dec31_dec_sub26_function_unit[13:0] - attribute \src "libresoc.v:110305.5-110305.29" + attribute \src "libresoc.v:110381.5-110381.29" switch \initial - attribute \src "libresoc.v:110305.9-110305.17" + attribute \src "libresoc.v:110381.9-110381.17" case 1'1 case end @@ -171751,14 +171814,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_function_unit $0\dec31_dec_sub26_function_unit[13:0] end - attribute \src "libresoc.v:110356.3-110407.6" - process $proc$libresoc.v:110356$4260 + attribute \src "libresoc.v:110432.3-110483.6" + process $proc$libresoc.v:110432$4260 assign { } { } assign { } { } assign $0\dec31_dec_sub26_cr_in[2:0] $1\dec31_dec_sub26_cr_in[2:0] - attribute \src "libresoc.v:110357.5-110357.29" + attribute \src "libresoc.v:110433.5-110433.29" switch \initial - attribute \src "libresoc.v:110357.9-110357.17" + attribute \src "libresoc.v:110433.9-110433.17" case 1'1 case end @@ -171830,14 +171893,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_cr_in $0\dec31_dec_sub26_cr_in[2:0] end - attribute \src "libresoc.v:110408.3-110459.6" - process $proc$libresoc.v:110408$4261 + attribute \src "libresoc.v:110484.3-110535.6" + process $proc$libresoc.v:110484$4261 assign { } { } assign { } { } assign $0\dec31_dec_sub26_cr_out[2:0] $1\dec31_dec_sub26_cr_out[2:0] - attribute \src "libresoc.v:110409.5-110409.29" + attribute \src "libresoc.v:110485.5-110485.29" switch \initial - attribute \src "libresoc.v:110409.9-110409.17" + attribute \src "libresoc.v:110485.9-110485.17" case 1'1 case end @@ -171909,14 +171972,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_cr_out $0\dec31_dec_sub26_cr_out[2:0] end - attribute \src "libresoc.v:110460.3-110511.6" - process $proc$libresoc.v:110460$4262 + attribute \src "libresoc.v:110536.3-110587.6" + process $proc$libresoc.v:110536$4262 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_in1[2:0] $1\dec31_dec_sub26_sv_in1[2:0] - attribute \src "libresoc.v:110461.5-110461.29" + attribute \src "libresoc.v:110537.5-110537.29" switch \initial - attribute \src "libresoc.v:110461.9-110461.17" + attribute \src "libresoc.v:110537.9-110537.17" case 1'1 case end @@ -171988,14 +172051,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_in1 $0\dec31_dec_sub26_sv_in1[2:0] end - attribute \src "libresoc.v:110512.3-110563.6" - process $proc$libresoc.v:110512$4263 + attribute \src "libresoc.v:110588.3-110639.6" + process $proc$libresoc.v:110588$4263 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_in2[2:0] $1\dec31_dec_sub26_sv_in2[2:0] - attribute \src "libresoc.v:110513.5-110513.29" + attribute \src "libresoc.v:110589.5-110589.29" switch \initial - attribute \src "libresoc.v:110513.9-110513.17" + attribute \src "libresoc.v:110589.9-110589.17" case 1'1 case end @@ -172067,14 +172130,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_in2 $0\dec31_dec_sub26_sv_in2[2:0] end - attribute \src "libresoc.v:110564.3-110615.6" - process $proc$libresoc.v:110564$4264 + attribute \src "libresoc.v:110640.3-110691.6" + process $proc$libresoc.v:110640$4264 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_in3[2:0] $1\dec31_dec_sub26_sv_in3[2:0] - attribute \src "libresoc.v:110565.5-110565.29" + attribute \src "libresoc.v:110641.5-110641.29" switch \initial - attribute \src "libresoc.v:110565.9-110565.17" + attribute \src "libresoc.v:110641.9-110641.17" case 1'1 case end @@ -172146,14 +172209,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_in3 $0\dec31_dec_sub26_sv_in3[2:0] end - attribute \src "libresoc.v:110616.3-110667.6" - process $proc$libresoc.v:110616$4265 + attribute \src "libresoc.v:110692.3-110743.6" + process $proc$libresoc.v:110692$4265 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_out[2:0] $1\dec31_dec_sub26_sv_out[2:0] - attribute \src "libresoc.v:110617.5-110617.29" + attribute \src "libresoc.v:110693.5-110693.29" switch \initial - attribute \src "libresoc.v:110617.9-110617.17" + attribute \src "libresoc.v:110693.9-110693.17" case 1'1 case end @@ -172225,14 +172288,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_out $0\dec31_dec_sub26_sv_out[2:0] end - attribute \src "libresoc.v:110668.3-110719.6" - process $proc$libresoc.v:110668$4266 + attribute \src "libresoc.v:110744.3-110795.6" + process $proc$libresoc.v:110744$4266 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_out2[2:0] $1\dec31_dec_sub26_sv_out2[2:0] - attribute \src "libresoc.v:110669.5-110669.29" + attribute \src "libresoc.v:110745.5-110745.29" switch \initial - attribute \src "libresoc.v:110669.9-110669.17" + attribute \src "libresoc.v:110745.9-110745.17" case 1'1 case end @@ -172304,14 +172367,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_out2 $0\dec31_dec_sub26_sv_out2[2:0] end - attribute \src "libresoc.v:110720.3-110771.6" - process $proc$libresoc.v:110720$4267 + attribute \src "libresoc.v:110796.3-110847.6" + process $proc$libresoc.v:110796$4267 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_cr_in[2:0] $1\dec31_dec_sub26_sv_cr_in[2:0] - attribute \src "libresoc.v:110721.5-110721.29" + attribute \src "libresoc.v:110797.5-110797.29" switch \initial - attribute \src "libresoc.v:110721.9-110721.17" + attribute \src "libresoc.v:110797.9-110797.17" case 1'1 case end @@ -172383,14 +172446,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_cr_in $0\dec31_dec_sub26_sv_cr_in[2:0] end - attribute \src "libresoc.v:110772.3-110823.6" - process $proc$libresoc.v:110772$4268 + attribute \src "libresoc.v:110848.3-110899.6" + process $proc$libresoc.v:110848$4268 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sv_cr_out[2:0] $1\dec31_dec_sub26_sv_cr_out[2:0] - attribute \src "libresoc.v:110773.5-110773.29" + attribute \src "libresoc.v:110849.5-110849.29" switch \initial - attribute \src "libresoc.v:110773.9-110773.17" + attribute \src "libresoc.v:110849.9-110849.17" case 1'1 case end @@ -172462,14 +172525,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sv_cr_out $0\dec31_dec_sub26_sv_cr_out[2:0] end - attribute \src "libresoc.v:110824.3-110875.6" - process $proc$libresoc.v:110824$4269 + attribute \src "libresoc.v:110900.3-110951.6" + process $proc$libresoc.v:110900$4269 assign { } { } assign { } { } assign $0\dec31_dec_sub26_ldst_len[3:0] $1\dec31_dec_sub26_ldst_len[3:0] - attribute \src "libresoc.v:110825.5-110825.29" + attribute \src "libresoc.v:110901.5-110901.29" switch \initial - attribute \src "libresoc.v:110825.9-110825.17" + attribute \src "libresoc.v:110901.9-110901.17" case 1'1 case end @@ -172541,14 +172604,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_ldst_len $0\dec31_dec_sub26_ldst_len[3:0] end - attribute \src "libresoc.v:110876.3-110927.6" - process $proc$libresoc.v:110876$4270 + attribute \src "libresoc.v:110952.3-111003.6" + process $proc$libresoc.v:110952$4270 assign { } { } assign { } { } assign $0\dec31_dec_sub26_internal_op[6:0] $1\dec31_dec_sub26_internal_op[6:0] - attribute \src "libresoc.v:110877.5-110877.29" + attribute \src "libresoc.v:110953.5-110953.29" switch \initial - attribute \src "libresoc.v:110877.9-110877.17" + attribute \src "libresoc.v:110953.9-110953.17" case 1'1 case end @@ -172620,14 +172683,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_internal_op $0\dec31_dec_sub26_internal_op[6:0] end - attribute \src "libresoc.v:110928.3-110979.6" - process $proc$libresoc.v:110928$4271 + attribute \src "libresoc.v:111004.3-111055.6" + process $proc$libresoc.v:111004$4271 assign { } { } assign { } { } assign $0\dec31_dec_sub26_upd[1:0] $1\dec31_dec_sub26_upd[1:0] - attribute \src "libresoc.v:110929.5-110929.29" + attribute \src "libresoc.v:111005.5-111005.29" switch \initial - attribute \src "libresoc.v:110929.9-110929.17" + attribute \src "libresoc.v:111005.9-111005.17" case 1'1 case end @@ -172699,14 +172762,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_upd $0\dec31_dec_sub26_upd[1:0] end - attribute \src "libresoc.v:110980.3-111031.6" - process $proc$libresoc.v:110980$4272 + attribute \src "libresoc.v:111056.3-111107.6" + process $proc$libresoc.v:111056$4272 assign { } { } assign { } { } assign $0\dec31_dec_sub26_rc_sel[1:0] $1\dec31_dec_sub26_rc_sel[1:0] - attribute \src "libresoc.v:110981.5-110981.29" + attribute \src "libresoc.v:111057.5-111057.29" switch \initial - attribute \src "libresoc.v:110981.9-110981.17" + attribute \src "libresoc.v:111057.9-111057.17" case 1'1 case end @@ -172778,14 +172841,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_rc_sel $0\dec31_dec_sub26_rc_sel[1:0] end - attribute \src "libresoc.v:111032.3-111083.6" - process $proc$libresoc.v:111032$4273 + attribute \src "libresoc.v:111108.3-111159.6" + process $proc$libresoc.v:111108$4273 assign { } { } assign { } { } assign $0\dec31_dec_sub26_cry_in[1:0] $1\dec31_dec_sub26_cry_in[1:0] - attribute \src "libresoc.v:111033.5-111033.29" + attribute \src "libresoc.v:111109.5-111109.29" switch \initial - attribute \src "libresoc.v:111033.9-111033.17" + attribute \src "libresoc.v:111109.9-111109.17" case 1'1 case end @@ -172857,14 +172920,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_cry_in $0\dec31_dec_sub26_cry_in[1:0] end - attribute \src "libresoc.v:111084.3-111135.6" - process $proc$libresoc.v:111084$4274 + attribute \src "libresoc.v:111160.3-111211.6" + process $proc$libresoc.v:111160$4274 assign { } { } assign { } { } assign $0\dec31_dec_sub26_asmcode[7:0] $1\dec31_dec_sub26_asmcode[7:0] - attribute \src "libresoc.v:111085.5-111085.29" + attribute \src "libresoc.v:111161.5-111161.29" switch \initial - attribute \src "libresoc.v:111085.9-111085.17" + attribute \src "libresoc.v:111161.9-111161.17" case 1'1 case end @@ -172936,14 +172999,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_asmcode $0\dec31_dec_sub26_asmcode[7:0] end - attribute \src "libresoc.v:111136.3-111187.6" - process $proc$libresoc.v:111136$4275 + attribute \src "libresoc.v:111212.3-111263.6" + process $proc$libresoc.v:111212$4275 assign { } { } assign { } { } assign $0\dec31_dec_sub26_inv_a[0:0] $1\dec31_dec_sub26_inv_a[0:0] - attribute \src "libresoc.v:111137.5-111137.29" + attribute \src "libresoc.v:111213.5-111213.29" switch \initial - attribute \src "libresoc.v:111137.9-111137.17" + attribute \src "libresoc.v:111213.9-111213.17" case 1'1 case end @@ -173015,14 +173078,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_inv_a $0\dec31_dec_sub26_inv_a[0:0] end - attribute \src "libresoc.v:111188.3-111239.6" - process $proc$libresoc.v:111188$4276 + attribute \src "libresoc.v:111264.3-111315.6" + process $proc$libresoc.v:111264$4276 assign { } { } assign { } { } assign $0\dec31_dec_sub26_inv_out[0:0] $1\dec31_dec_sub26_inv_out[0:0] - attribute \src "libresoc.v:111189.5-111189.29" + attribute \src "libresoc.v:111265.5-111265.29" switch \initial - attribute \src "libresoc.v:111189.9-111189.17" + attribute \src "libresoc.v:111265.9-111265.17" case 1'1 case end @@ -173094,14 +173157,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_inv_out $0\dec31_dec_sub26_inv_out[0:0] end - attribute \src "libresoc.v:111240.3-111291.6" - process $proc$libresoc.v:111240$4277 + attribute \src "libresoc.v:111316.3-111367.6" + process $proc$libresoc.v:111316$4277 assign { } { } assign { } { } assign $0\dec31_dec_sub26_cry_out[0:0] $1\dec31_dec_sub26_cry_out[0:0] - attribute \src "libresoc.v:111241.5-111241.29" + attribute \src "libresoc.v:111317.5-111317.29" switch \initial - attribute \src "libresoc.v:111241.9-111241.17" + attribute \src "libresoc.v:111317.9-111317.17" case 1'1 case end @@ -173173,14 +173236,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_cry_out $0\dec31_dec_sub26_cry_out[0:0] end - attribute \src "libresoc.v:111292.3-111343.6" - process $proc$libresoc.v:111292$4278 + attribute \src "libresoc.v:111368.3-111419.6" + process $proc$libresoc.v:111368$4278 assign { } { } assign { } { } assign $0\dec31_dec_sub26_br[0:0] $1\dec31_dec_sub26_br[0:0] - attribute \src "libresoc.v:111293.5-111293.29" + attribute \src "libresoc.v:111369.5-111369.29" switch \initial - attribute \src "libresoc.v:111293.9-111293.17" + attribute \src "libresoc.v:111369.9-111369.17" case 1'1 case end @@ -173252,14 +173315,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_br $0\dec31_dec_sub26_br[0:0] end - attribute \src "libresoc.v:111344.3-111395.6" - process $proc$libresoc.v:111344$4279 + attribute \src "libresoc.v:111420.3-111471.6" + process $proc$libresoc.v:111420$4279 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sgn_ext[0:0] $1\dec31_dec_sub26_sgn_ext[0:0] - attribute \src "libresoc.v:111345.5-111345.29" + attribute \src "libresoc.v:111421.5-111421.29" switch \initial - attribute \src "libresoc.v:111345.9-111345.17" + attribute \src "libresoc.v:111421.9-111421.17" case 1'1 case end @@ -173331,14 +173394,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sgn_ext $0\dec31_dec_sub26_sgn_ext[0:0] end - attribute \src "libresoc.v:111396.3-111447.6" - process $proc$libresoc.v:111396$4280 + attribute \src "libresoc.v:111472.3-111523.6" + process $proc$libresoc.v:111472$4280 assign { } { } assign { } { } assign $0\dec31_dec_sub26_rsrv[0:0] $1\dec31_dec_sub26_rsrv[0:0] - attribute \src "libresoc.v:111397.5-111397.29" + attribute \src "libresoc.v:111473.5-111473.29" switch \initial - attribute \src "libresoc.v:111397.9-111397.17" + attribute \src "libresoc.v:111473.9-111473.17" case 1'1 case end @@ -173410,14 +173473,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_rsrv $0\dec31_dec_sub26_rsrv[0:0] end - attribute \src "libresoc.v:111448.3-111499.6" - process $proc$libresoc.v:111448$4281 + attribute \src "libresoc.v:111524.3-111575.6" + process $proc$libresoc.v:111524$4281 assign { } { } assign { } { } assign $0\dec31_dec_sub26_form[4:0] $1\dec31_dec_sub26_form[4:0] - attribute \src "libresoc.v:111449.5-111449.29" + attribute \src "libresoc.v:111525.5-111525.29" switch \initial - attribute \src "libresoc.v:111449.9-111449.17" + attribute \src "libresoc.v:111525.9-111525.17" case 1'1 case end @@ -173489,14 +173552,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_form $0\dec31_dec_sub26_form[4:0] end - attribute \src "libresoc.v:111500.3-111551.6" - process $proc$libresoc.v:111500$4282 + attribute \src "libresoc.v:111576.3-111627.6" + process $proc$libresoc.v:111576$4282 assign { } { } assign { } { } assign $0\dec31_dec_sub26_is_32b[0:0] $1\dec31_dec_sub26_is_32b[0:0] - attribute \src "libresoc.v:111501.5-111501.29" + attribute \src "libresoc.v:111577.5-111577.29" switch \initial - attribute \src "libresoc.v:111501.9-111501.17" + attribute \src "libresoc.v:111577.9-111577.17" case 1'1 case end @@ -173568,14 +173631,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_is_32b $0\dec31_dec_sub26_is_32b[0:0] end - attribute \src "libresoc.v:111552.3-111603.6" - process $proc$libresoc.v:111552$4283 + attribute \src "libresoc.v:111628.3-111679.6" + process $proc$libresoc.v:111628$4283 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sgn[0:0] $1\dec31_dec_sub26_sgn[0:0] - attribute \src "libresoc.v:111553.5-111553.29" + attribute \src "libresoc.v:111629.5-111629.29" switch \initial - attribute \src "libresoc.v:111553.9-111553.17" + attribute \src "libresoc.v:111629.9-111629.17" case 1'1 case end @@ -173647,14 +173710,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sgn $0\dec31_dec_sub26_sgn[0:0] end - attribute \src "libresoc.v:111604.3-111655.6" - process $proc$libresoc.v:111604$4284 + attribute \src "libresoc.v:111680.3-111731.6" + process $proc$libresoc.v:111680$4284 assign { } { } assign { } { } assign $0\dec31_dec_sub26_lk[0:0] $1\dec31_dec_sub26_lk[0:0] - attribute \src "libresoc.v:111605.5-111605.29" + attribute \src "libresoc.v:111681.5-111681.29" switch \initial - attribute \src "libresoc.v:111605.9-111605.17" + attribute \src "libresoc.v:111681.9-111681.17" case 1'1 case end @@ -173726,14 +173789,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_lk $0\dec31_dec_sub26_lk[0:0] end - attribute \src "libresoc.v:111656.3-111707.6" - process $proc$libresoc.v:111656$4285 + attribute \src "libresoc.v:111732.3-111783.6" + process $proc$libresoc.v:111732$4285 assign { } { } assign { } { } assign $0\dec31_dec_sub26_sgl_pipe[0:0] $1\dec31_dec_sub26_sgl_pipe[0:0] - attribute \src "libresoc.v:111657.5-111657.29" + attribute \src "libresoc.v:111733.5-111733.29" switch \initial - attribute \src "libresoc.v:111657.9-111657.17" + attribute \src "libresoc.v:111733.9-111733.17" case 1'1 case end @@ -173805,14 +173868,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_sgl_pipe $0\dec31_dec_sub26_sgl_pipe[0:0] end - attribute \src "libresoc.v:111708.3-111759.6" - process $proc$libresoc.v:111708$4286 + attribute \src "libresoc.v:111784.3-111835.6" + process $proc$libresoc.v:111784$4286 assign { } { } assign { } { } assign $0\dec31_dec_sub26_SV_Etype[1:0] $1\dec31_dec_sub26_SV_Etype[1:0] - attribute \src "libresoc.v:111709.5-111709.29" + attribute \src "libresoc.v:111785.5-111785.29" switch \initial - attribute \src "libresoc.v:111709.9-111709.17" + attribute \src "libresoc.v:111785.9-111785.17" case 1'1 case end @@ -173884,14 +173947,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_SV_Etype $0\dec31_dec_sub26_SV_Etype[1:0] end - attribute \src "libresoc.v:111760.3-111811.6" - process $proc$libresoc.v:111760$4287 + attribute \src "libresoc.v:111836.3-111887.6" + process $proc$libresoc.v:111836$4287 assign { } { } assign { } { } assign $0\dec31_dec_sub26_SV_Ptype[1:0] $1\dec31_dec_sub26_SV_Ptype[1:0] - attribute \src "libresoc.v:111761.5-111761.29" + attribute \src "libresoc.v:111837.5-111837.29" switch \initial - attribute \src "libresoc.v:111761.9-111761.17" + attribute \src "libresoc.v:111837.9-111837.17" case 1'1 case end @@ -173963,14 +174026,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_SV_Ptype $0\dec31_dec_sub26_SV_Ptype[1:0] end - attribute \src "libresoc.v:111812.3-111863.6" - process $proc$libresoc.v:111812$4288 + attribute \src "libresoc.v:111888.3-111939.6" + process $proc$libresoc.v:111888$4288 assign { } { } assign { } { } assign $0\dec31_dec_sub26_in1_sel[2:0] $1\dec31_dec_sub26_in1_sel[2:0] - attribute \src "libresoc.v:111813.5-111813.29" + attribute \src "libresoc.v:111889.5-111889.29" switch \initial - attribute \src "libresoc.v:111813.9-111813.17" + attribute \src "libresoc.v:111889.9-111889.17" case 1'1 case end @@ -174042,14 +174105,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_in1_sel $0\dec31_dec_sub26_in1_sel[2:0] end - attribute \src "libresoc.v:111864.3-111915.6" - process $proc$libresoc.v:111864$4289 + attribute \src "libresoc.v:111940.3-111991.6" + process $proc$libresoc.v:111940$4289 assign { } { } assign { } { } assign $0\dec31_dec_sub26_in2_sel[3:0] $1\dec31_dec_sub26_in2_sel[3:0] - attribute \src "libresoc.v:111865.5-111865.29" + attribute \src "libresoc.v:111941.5-111941.29" switch \initial - attribute \src "libresoc.v:111865.9-111865.17" + attribute \src "libresoc.v:111941.9-111941.17" case 1'1 case end @@ -174121,14 +174184,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_in2_sel $0\dec31_dec_sub26_in2_sel[3:0] end - attribute \src "libresoc.v:111916.3-111967.6" - process $proc$libresoc.v:111916$4290 + attribute \src "libresoc.v:111992.3-112043.6" + process $proc$libresoc.v:111992$4290 assign { } { } assign { } { } assign $0\dec31_dec_sub26_in3_sel[1:0] $1\dec31_dec_sub26_in3_sel[1:0] - attribute \src "libresoc.v:111917.5-111917.29" + attribute \src "libresoc.v:111993.5-111993.29" switch \initial - attribute \src "libresoc.v:111917.9-111917.17" + attribute \src "libresoc.v:111993.9-111993.17" case 1'1 case end @@ -174200,14 +174263,14 @@ module \dec31_dec_sub26 sync always update \dec31_dec_sub26_in3_sel $0\dec31_dec_sub26_in3_sel[1:0] end - attribute \src "libresoc.v:111968.3-112019.6" - process $proc$libresoc.v:111968$4291 + attribute \src "libresoc.v:112044.3-112095.6" + process $proc$libresoc.v:112044$4291 assign { } { } assign { } { } assign $0\dec31_dec_sub26_out_sel[2:0] $1\dec31_dec_sub26_out_sel[2:0] - attribute \src "libresoc.v:111969.5-111969.29" + attribute \src "libresoc.v:112045.5-112045.29" switch \initial - attribute \src "libresoc.v:111969.9-111969.17" + attribute \src "libresoc.v:112045.9-112045.17" case 1'1 case end @@ -174281,144 +174344,144 @@ module \dec31_dec_sub26 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:112025.1-113002.10" +attribute \src "libresoc.v:112101.1-113078.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub27" attribute \generator "nMigen" module \dec31_dec_sub27 - attribute \src "libresoc.v:112887.3-112905.6" + attribute \src "libresoc.v:112963.3-112981.6" wire width 2 $0\dec31_dec_sub27_SV_Etype[1:0] - attribute \src "libresoc.v:112906.3-112924.6" + attribute \src "libresoc.v:112982.3-113000.6" wire width 2 $0\dec31_dec_sub27_SV_Ptype[1:0] - attribute \src "libresoc.v:112659.3-112677.6" - wire width 8 $0\dec31_dec_sub27_asmcode[7:0] attribute \src "libresoc.v:112735.3-112753.6" + wire width 8 $0\dec31_dec_sub27_asmcode[7:0] + attribute \src "libresoc.v:112811.3-112829.6" wire $0\dec31_dec_sub27_br[0:0] - attribute \src "libresoc.v:112393.3-112411.6" + attribute \src "libresoc.v:112469.3-112487.6" wire width 3 $0\dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:112412.3-112430.6" + attribute \src "libresoc.v:112488.3-112506.6" wire width 3 $0\dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:112640.3-112658.6" - wire width 2 $0\dec31_dec_sub27_cry_in[1:0] attribute \src "libresoc.v:112716.3-112734.6" - wire $0\dec31_dec_sub27_cry_out[0:0] + wire width 2 $0\dec31_dec_sub27_cry_in[1:0] attribute \src "libresoc.v:112792.3-112810.6" + wire $0\dec31_dec_sub27_cry_out[0:0] + attribute \src "libresoc.v:112868.3-112886.6" wire width 5 $0\dec31_dec_sub27_form[4:0] - attribute \src "libresoc.v:112374.3-112392.6" + attribute \src "libresoc.v:112450.3-112468.6" wire width 14 $0\dec31_dec_sub27_function_unit[13:0] - attribute \src "libresoc.v:112925.3-112943.6" + attribute \src "libresoc.v:113001.3-113019.6" wire width 3 $0\dec31_dec_sub27_in1_sel[2:0] - attribute \src "libresoc.v:112944.3-112962.6" + attribute \src "libresoc.v:113020.3-113038.6" wire width 4 $0\dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:112963.3-112981.6" + attribute \src "libresoc.v:113039.3-113057.6" wire width 2 $0\dec31_dec_sub27_in3_sel[1:0] - attribute \src "libresoc.v:112583.3-112601.6" + attribute \src "libresoc.v:112659.3-112677.6" wire width 7 $0\dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:112678.3-112696.6" + attribute \src "libresoc.v:112754.3-112772.6" wire $0\dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:112697.3-112715.6" + attribute \src "libresoc.v:112773.3-112791.6" wire $0\dec31_dec_sub27_inv_out[0:0] - attribute \src "libresoc.v:112811.3-112829.6" + attribute \src "libresoc.v:112887.3-112905.6" wire $0\dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:112564.3-112582.6" + attribute \src "libresoc.v:112640.3-112658.6" wire width 4 $0\dec31_dec_sub27_ldst_len[3:0] - attribute \src "libresoc.v:112849.3-112867.6" + attribute \src "libresoc.v:112925.3-112943.6" wire $0\dec31_dec_sub27_lk[0:0] - attribute \src "libresoc.v:112982.3-113000.6" + attribute \src "libresoc.v:113058.3-113076.6" wire width 3 $0\dec31_dec_sub27_out_sel[2:0] - attribute \src "libresoc.v:112621.3-112639.6" + attribute \src "libresoc.v:112697.3-112715.6" wire width 2 $0\dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:112773.3-112791.6" + attribute \src "libresoc.v:112849.3-112867.6" wire $0\dec31_dec_sub27_rsrv[0:0] - attribute \src "libresoc.v:112868.3-112886.6" + attribute \src "libresoc.v:112944.3-112962.6" wire $0\dec31_dec_sub27_sgl_pipe[0:0] - attribute \src "libresoc.v:112830.3-112848.6" + attribute \src "libresoc.v:112906.3-112924.6" wire $0\dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:112754.3-112772.6" + attribute \src "libresoc.v:112830.3-112848.6" wire $0\dec31_dec_sub27_sgn_ext[0:0] - attribute \src "libresoc.v:112526.3-112544.6" + attribute \src "libresoc.v:112602.3-112620.6" wire width 3 $0\dec31_dec_sub27_sv_cr_in[2:0] - attribute \src "libresoc.v:112545.3-112563.6" + attribute \src "libresoc.v:112621.3-112639.6" wire width 3 $0\dec31_dec_sub27_sv_cr_out[2:0] - attribute \src "libresoc.v:112431.3-112449.6" + attribute \src "libresoc.v:112507.3-112525.6" wire width 3 $0\dec31_dec_sub27_sv_in1[2:0] - attribute \src "libresoc.v:112450.3-112468.6" + attribute \src "libresoc.v:112526.3-112544.6" wire width 3 $0\dec31_dec_sub27_sv_in2[2:0] - attribute \src "libresoc.v:112469.3-112487.6" + attribute \src "libresoc.v:112545.3-112563.6" wire width 3 $0\dec31_dec_sub27_sv_in3[2:0] - attribute \src "libresoc.v:112507.3-112525.6" + attribute \src "libresoc.v:112583.3-112601.6" wire width 3 $0\dec31_dec_sub27_sv_out2[2:0] - attribute \src "libresoc.v:112488.3-112506.6" + attribute \src "libresoc.v:112564.3-112582.6" wire width 3 $0\dec31_dec_sub27_sv_out[2:0] - attribute \src "libresoc.v:112602.3-112620.6" + attribute \src "libresoc.v:112678.3-112696.6" wire width 2 $0\dec31_dec_sub27_upd[1:0] - attribute \src "libresoc.v:112026.7-112026.20" + attribute \src "libresoc.v:112102.7-112102.20" wire $0\initial[0:0] - attribute \src "libresoc.v:112887.3-112905.6" + attribute \src "libresoc.v:112963.3-112981.6" wire width 2 $1\dec31_dec_sub27_SV_Etype[1:0] - attribute \src "libresoc.v:112906.3-112924.6" + attribute \src "libresoc.v:112982.3-113000.6" wire width 2 $1\dec31_dec_sub27_SV_Ptype[1:0] - attribute \src "libresoc.v:112659.3-112677.6" - wire width 8 $1\dec31_dec_sub27_asmcode[7:0] attribute \src "libresoc.v:112735.3-112753.6" + wire width 8 $1\dec31_dec_sub27_asmcode[7:0] + attribute \src "libresoc.v:112811.3-112829.6" wire $1\dec31_dec_sub27_br[0:0] - attribute \src "libresoc.v:112393.3-112411.6" + attribute \src "libresoc.v:112469.3-112487.6" wire width 3 $1\dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:112412.3-112430.6" + attribute \src "libresoc.v:112488.3-112506.6" wire width 3 $1\dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:112640.3-112658.6" - wire width 2 $1\dec31_dec_sub27_cry_in[1:0] attribute \src "libresoc.v:112716.3-112734.6" - wire $1\dec31_dec_sub27_cry_out[0:0] + wire width 2 $1\dec31_dec_sub27_cry_in[1:0] attribute \src "libresoc.v:112792.3-112810.6" + wire $1\dec31_dec_sub27_cry_out[0:0] + attribute \src "libresoc.v:112868.3-112886.6" wire width 5 $1\dec31_dec_sub27_form[4:0] - attribute \src "libresoc.v:112374.3-112392.6" + attribute \src "libresoc.v:112450.3-112468.6" wire width 14 $1\dec31_dec_sub27_function_unit[13:0] - attribute \src "libresoc.v:112925.3-112943.6" + attribute \src "libresoc.v:113001.3-113019.6" wire width 3 $1\dec31_dec_sub27_in1_sel[2:0] - attribute \src "libresoc.v:112944.3-112962.6" + attribute \src "libresoc.v:113020.3-113038.6" wire width 4 $1\dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:112963.3-112981.6" + attribute \src "libresoc.v:113039.3-113057.6" wire width 2 $1\dec31_dec_sub27_in3_sel[1:0] - attribute \src "libresoc.v:112583.3-112601.6" + attribute \src "libresoc.v:112659.3-112677.6" wire width 7 $1\dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:112678.3-112696.6" + attribute \src "libresoc.v:112754.3-112772.6" wire $1\dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:112697.3-112715.6" + attribute \src "libresoc.v:112773.3-112791.6" wire $1\dec31_dec_sub27_inv_out[0:0] - attribute \src "libresoc.v:112811.3-112829.6" + attribute \src "libresoc.v:112887.3-112905.6" wire $1\dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:112564.3-112582.6" + attribute \src "libresoc.v:112640.3-112658.6" wire width 4 $1\dec31_dec_sub27_ldst_len[3:0] - attribute \src "libresoc.v:112849.3-112867.6" + attribute \src "libresoc.v:112925.3-112943.6" wire $1\dec31_dec_sub27_lk[0:0] - attribute \src "libresoc.v:112982.3-113000.6" + attribute \src "libresoc.v:113058.3-113076.6" wire width 3 $1\dec31_dec_sub27_out_sel[2:0] - attribute \src "libresoc.v:112621.3-112639.6" + attribute \src "libresoc.v:112697.3-112715.6" wire width 2 $1\dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:112773.3-112791.6" + attribute \src "libresoc.v:112849.3-112867.6" wire $1\dec31_dec_sub27_rsrv[0:0] - attribute \src "libresoc.v:112868.3-112886.6" + attribute \src "libresoc.v:112944.3-112962.6" wire $1\dec31_dec_sub27_sgl_pipe[0:0] - attribute \src "libresoc.v:112830.3-112848.6" + attribute \src "libresoc.v:112906.3-112924.6" wire $1\dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:112754.3-112772.6" + attribute \src "libresoc.v:112830.3-112848.6" wire $1\dec31_dec_sub27_sgn_ext[0:0] - attribute \src "libresoc.v:112526.3-112544.6" + attribute \src "libresoc.v:112602.3-112620.6" wire width 3 $1\dec31_dec_sub27_sv_cr_in[2:0] - attribute \src "libresoc.v:112545.3-112563.6" + attribute \src "libresoc.v:112621.3-112639.6" wire width 3 $1\dec31_dec_sub27_sv_cr_out[2:0] - attribute \src "libresoc.v:112431.3-112449.6" + attribute \src "libresoc.v:112507.3-112525.6" wire width 3 $1\dec31_dec_sub27_sv_in1[2:0] - attribute \src "libresoc.v:112450.3-112468.6" + attribute \src "libresoc.v:112526.3-112544.6" wire width 3 $1\dec31_dec_sub27_sv_in2[2:0] - attribute \src "libresoc.v:112469.3-112487.6" + attribute \src "libresoc.v:112545.3-112563.6" wire width 3 $1\dec31_dec_sub27_sv_in3[2:0] - attribute \src "libresoc.v:112507.3-112525.6" + attribute \src "libresoc.v:112583.3-112601.6" wire width 3 $1\dec31_dec_sub27_sv_out2[2:0] - attribute \src "libresoc.v:112488.3-112506.6" + attribute \src "libresoc.v:112564.3-112582.6" wire width 3 $1\dec31_dec_sub27_sv_out[2:0] - attribute \src "libresoc.v:112602.3-112620.6" + attribute \src "libresoc.v:112678.3-112696.6" wire width 2 $1\dec31_dec_sub27_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -174730,28 +174793,28 @@ module \dec31_dec_sub27 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub27_upd - attribute \src "libresoc.v:112026.7-112026.15" + attribute \src "libresoc.v:112102.7-112102.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:112026.7-112026.20" - process $proc$libresoc.v:112026$4326 + attribute \src "libresoc.v:112102.7-112102.20" + process $proc$libresoc.v:112102$4326 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:112374.3-112392.6" - process $proc$libresoc.v:112374$4293 + attribute \src "libresoc.v:112450.3-112468.6" + process $proc$libresoc.v:112450$4293 assign { } { } assign { } { } assign $0\dec31_dec_sub27_function_unit[13:0] $1\dec31_dec_sub27_function_unit[13:0] - attribute \src "libresoc.v:112375.5-112375.29" + attribute \src "libresoc.v:112451.5-112451.29" switch \initial - attribute \src "libresoc.v:112375.9-112375.17" + attribute \src "libresoc.v:112451.9-112451.17" case 1'1 case end @@ -174779,14 +174842,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_function_unit $0\dec31_dec_sub27_function_unit[13:0] end - attribute \src "libresoc.v:112393.3-112411.6" - process $proc$libresoc.v:112393$4294 + attribute \src "libresoc.v:112469.3-112487.6" + process $proc$libresoc.v:112469$4294 assign { } { } assign { } { } assign $0\dec31_dec_sub27_cr_in[2:0] $1\dec31_dec_sub27_cr_in[2:0] - attribute \src "libresoc.v:112394.5-112394.29" + attribute \src "libresoc.v:112470.5-112470.29" switch \initial - attribute \src "libresoc.v:112394.9-112394.17" + attribute \src "libresoc.v:112470.9-112470.17" case 1'1 case end @@ -174814,14 +174877,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_cr_in $0\dec31_dec_sub27_cr_in[2:0] end - attribute \src "libresoc.v:112412.3-112430.6" - process $proc$libresoc.v:112412$4295 + attribute \src "libresoc.v:112488.3-112506.6" + process $proc$libresoc.v:112488$4295 assign { } { } assign { } { } assign $0\dec31_dec_sub27_cr_out[2:0] $1\dec31_dec_sub27_cr_out[2:0] - attribute \src "libresoc.v:112413.5-112413.29" + attribute \src "libresoc.v:112489.5-112489.29" switch \initial - attribute \src "libresoc.v:112413.9-112413.17" + attribute \src "libresoc.v:112489.9-112489.17" case 1'1 case end @@ -174849,14 +174912,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_cr_out $0\dec31_dec_sub27_cr_out[2:0] end - attribute \src "libresoc.v:112431.3-112449.6" - process $proc$libresoc.v:112431$4296 + attribute \src "libresoc.v:112507.3-112525.6" + process $proc$libresoc.v:112507$4296 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_in1[2:0] $1\dec31_dec_sub27_sv_in1[2:0] - attribute \src "libresoc.v:112432.5-112432.29" + attribute \src "libresoc.v:112508.5-112508.29" switch \initial - attribute \src "libresoc.v:112432.9-112432.17" + attribute \src "libresoc.v:112508.9-112508.17" case 1'1 case end @@ -174884,14 +174947,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_in1 $0\dec31_dec_sub27_sv_in1[2:0] end - attribute \src "libresoc.v:112450.3-112468.6" - process $proc$libresoc.v:112450$4297 + attribute \src "libresoc.v:112526.3-112544.6" + process $proc$libresoc.v:112526$4297 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_in2[2:0] $1\dec31_dec_sub27_sv_in2[2:0] - attribute \src "libresoc.v:112451.5-112451.29" + attribute \src "libresoc.v:112527.5-112527.29" switch \initial - attribute \src "libresoc.v:112451.9-112451.17" + attribute \src "libresoc.v:112527.9-112527.17" case 1'1 case end @@ -174919,14 +174982,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_in2 $0\dec31_dec_sub27_sv_in2[2:0] end - attribute \src "libresoc.v:112469.3-112487.6" - process $proc$libresoc.v:112469$4298 + attribute \src "libresoc.v:112545.3-112563.6" + process $proc$libresoc.v:112545$4298 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_in3[2:0] $1\dec31_dec_sub27_sv_in3[2:0] - attribute \src "libresoc.v:112470.5-112470.29" + attribute \src "libresoc.v:112546.5-112546.29" switch \initial - attribute \src "libresoc.v:112470.9-112470.17" + attribute \src "libresoc.v:112546.9-112546.17" case 1'1 case end @@ -174954,14 +175017,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_in3 $0\dec31_dec_sub27_sv_in3[2:0] end - attribute \src "libresoc.v:112488.3-112506.6" - process $proc$libresoc.v:112488$4299 + attribute \src "libresoc.v:112564.3-112582.6" + process $proc$libresoc.v:112564$4299 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_out[2:0] $1\dec31_dec_sub27_sv_out[2:0] - attribute \src "libresoc.v:112489.5-112489.29" + attribute \src "libresoc.v:112565.5-112565.29" switch \initial - attribute \src "libresoc.v:112489.9-112489.17" + attribute \src "libresoc.v:112565.9-112565.17" case 1'1 case end @@ -174989,14 +175052,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_out $0\dec31_dec_sub27_sv_out[2:0] end - attribute \src "libresoc.v:112507.3-112525.6" - process $proc$libresoc.v:112507$4300 + attribute \src "libresoc.v:112583.3-112601.6" + process $proc$libresoc.v:112583$4300 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_out2[2:0] $1\dec31_dec_sub27_sv_out2[2:0] - attribute \src "libresoc.v:112508.5-112508.29" + attribute \src "libresoc.v:112584.5-112584.29" switch \initial - attribute \src "libresoc.v:112508.9-112508.17" + attribute \src "libresoc.v:112584.9-112584.17" case 1'1 case end @@ -175024,14 +175087,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_out2 $0\dec31_dec_sub27_sv_out2[2:0] end - attribute \src "libresoc.v:112526.3-112544.6" - process $proc$libresoc.v:112526$4301 + attribute \src "libresoc.v:112602.3-112620.6" + process $proc$libresoc.v:112602$4301 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_cr_in[2:0] $1\dec31_dec_sub27_sv_cr_in[2:0] - attribute \src "libresoc.v:112527.5-112527.29" + attribute \src "libresoc.v:112603.5-112603.29" switch \initial - attribute \src "libresoc.v:112527.9-112527.17" + attribute \src "libresoc.v:112603.9-112603.17" case 1'1 case end @@ -175059,14 +175122,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_cr_in $0\dec31_dec_sub27_sv_cr_in[2:0] end - attribute \src "libresoc.v:112545.3-112563.6" - process $proc$libresoc.v:112545$4302 + attribute \src "libresoc.v:112621.3-112639.6" + process $proc$libresoc.v:112621$4302 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sv_cr_out[2:0] $1\dec31_dec_sub27_sv_cr_out[2:0] - attribute \src "libresoc.v:112546.5-112546.29" + attribute \src "libresoc.v:112622.5-112622.29" switch \initial - attribute \src "libresoc.v:112546.9-112546.17" + attribute \src "libresoc.v:112622.9-112622.17" case 1'1 case end @@ -175094,14 +175157,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sv_cr_out $0\dec31_dec_sub27_sv_cr_out[2:0] end - attribute \src "libresoc.v:112564.3-112582.6" - process $proc$libresoc.v:112564$4303 + attribute \src "libresoc.v:112640.3-112658.6" + process $proc$libresoc.v:112640$4303 assign { } { } assign { } { } assign $0\dec31_dec_sub27_ldst_len[3:0] $1\dec31_dec_sub27_ldst_len[3:0] - attribute \src "libresoc.v:112565.5-112565.29" + attribute \src "libresoc.v:112641.5-112641.29" switch \initial - attribute \src "libresoc.v:112565.9-112565.17" + attribute \src "libresoc.v:112641.9-112641.17" case 1'1 case end @@ -175129,14 +175192,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_ldst_len $0\dec31_dec_sub27_ldst_len[3:0] end - attribute \src "libresoc.v:112583.3-112601.6" - process $proc$libresoc.v:112583$4304 + attribute \src "libresoc.v:112659.3-112677.6" + process $proc$libresoc.v:112659$4304 assign { } { } assign { } { } assign $0\dec31_dec_sub27_internal_op[6:0] $1\dec31_dec_sub27_internal_op[6:0] - attribute \src "libresoc.v:112584.5-112584.29" + attribute \src "libresoc.v:112660.5-112660.29" switch \initial - attribute \src "libresoc.v:112584.9-112584.17" + attribute \src "libresoc.v:112660.9-112660.17" case 1'1 case end @@ -175164,14 +175227,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_internal_op $0\dec31_dec_sub27_internal_op[6:0] end - attribute \src "libresoc.v:112602.3-112620.6" - process $proc$libresoc.v:112602$4305 + attribute \src "libresoc.v:112678.3-112696.6" + process $proc$libresoc.v:112678$4305 assign { } { } assign { } { } assign $0\dec31_dec_sub27_upd[1:0] $1\dec31_dec_sub27_upd[1:0] - attribute \src "libresoc.v:112603.5-112603.29" + attribute \src "libresoc.v:112679.5-112679.29" switch \initial - attribute \src "libresoc.v:112603.9-112603.17" + attribute \src "libresoc.v:112679.9-112679.17" case 1'1 case end @@ -175199,14 +175262,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_upd $0\dec31_dec_sub27_upd[1:0] end - attribute \src "libresoc.v:112621.3-112639.6" - process $proc$libresoc.v:112621$4306 + attribute \src "libresoc.v:112697.3-112715.6" + process $proc$libresoc.v:112697$4306 assign { } { } assign { } { } assign $0\dec31_dec_sub27_rc_sel[1:0] $1\dec31_dec_sub27_rc_sel[1:0] - attribute \src "libresoc.v:112622.5-112622.29" + attribute \src "libresoc.v:112698.5-112698.29" switch \initial - attribute \src "libresoc.v:112622.9-112622.17" + attribute \src "libresoc.v:112698.9-112698.17" case 1'1 case end @@ -175234,14 +175297,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_rc_sel $0\dec31_dec_sub27_rc_sel[1:0] end - attribute \src "libresoc.v:112640.3-112658.6" - process $proc$libresoc.v:112640$4307 + attribute \src "libresoc.v:112716.3-112734.6" + process $proc$libresoc.v:112716$4307 assign { } { } assign { } { } assign $0\dec31_dec_sub27_cry_in[1:0] $1\dec31_dec_sub27_cry_in[1:0] - attribute \src "libresoc.v:112641.5-112641.29" + attribute \src "libresoc.v:112717.5-112717.29" switch \initial - attribute \src "libresoc.v:112641.9-112641.17" + attribute \src "libresoc.v:112717.9-112717.17" case 1'1 case end @@ -175269,14 +175332,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_cry_in $0\dec31_dec_sub27_cry_in[1:0] end - attribute \src "libresoc.v:112659.3-112677.6" - process $proc$libresoc.v:112659$4308 + attribute \src "libresoc.v:112735.3-112753.6" + process $proc$libresoc.v:112735$4308 assign { } { } assign { } { } assign $0\dec31_dec_sub27_asmcode[7:0] $1\dec31_dec_sub27_asmcode[7:0] - attribute \src "libresoc.v:112660.5-112660.29" + attribute \src "libresoc.v:112736.5-112736.29" switch \initial - attribute \src "libresoc.v:112660.9-112660.17" + attribute \src "libresoc.v:112736.9-112736.17" case 1'1 case end @@ -175304,14 +175367,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_asmcode $0\dec31_dec_sub27_asmcode[7:0] end - attribute \src "libresoc.v:112678.3-112696.6" - process $proc$libresoc.v:112678$4309 + attribute \src "libresoc.v:112754.3-112772.6" + process $proc$libresoc.v:112754$4309 assign { } { } assign { } { } assign $0\dec31_dec_sub27_inv_a[0:0] $1\dec31_dec_sub27_inv_a[0:0] - attribute \src "libresoc.v:112679.5-112679.29" + attribute \src "libresoc.v:112755.5-112755.29" switch \initial - attribute \src "libresoc.v:112679.9-112679.17" + attribute \src "libresoc.v:112755.9-112755.17" case 1'1 case end @@ -175339,14 +175402,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_inv_a $0\dec31_dec_sub27_inv_a[0:0] end - attribute \src "libresoc.v:112697.3-112715.6" - process $proc$libresoc.v:112697$4310 + attribute \src "libresoc.v:112773.3-112791.6" + process $proc$libresoc.v:112773$4310 assign { } { } assign { } { } assign $0\dec31_dec_sub27_inv_out[0:0] $1\dec31_dec_sub27_inv_out[0:0] - attribute \src "libresoc.v:112698.5-112698.29" + attribute \src "libresoc.v:112774.5-112774.29" switch \initial - attribute \src "libresoc.v:112698.9-112698.17" + attribute \src "libresoc.v:112774.9-112774.17" case 1'1 case end @@ -175374,14 +175437,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_inv_out $0\dec31_dec_sub27_inv_out[0:0] end - attribute \src "libresoc.v:112716.3-112734.6" - process $proc$libresoc.v:112716$4311 + attribute \src "libresoc.v:112792.3-112810.6" + process $proc$libresoc.v:112792$4311 assign { } { } assign { } { } assign $0\dec31_dec_sub27_cry_out[0:0] $1\dec31_dec_sub27_cry_out[0:0] - attribute \src "libresoc.v:112717.5-112717.29" + attribute \src "libresoc.v:112793.5-112793.29" switch \initial - attribute \src "libresoc.v:112717.9-112717.17" + attribute \src "libresoc.v:112793.9-112793.17" case 1'1 case end @@ -175409,14 +175472,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_cry_out $0\dec31_dec_sub27_cry_out[0:0] end - attribute \src "libresoc.v:112735.3-112753.6" - process $proc$libresoc.v:112735$4312 + attribute \src "libresoc.v:112811.3-112829.6" + process $proc$libresoc.v:112811$4312 assign { } { } assign { } { } assign $0\dec31_dec_sub27_br[0:0] $1\dec31_dec_sub27_br[0:0] - attribute \src "libresoc.v:112736.5-112736.29" + attribute \src "libresoc.v:112812.5-112812.29" switch \initial - attribute \src "libresoc.v:112736.9-112736.17" + attribute \src "libresoc.v:112812.9-112812.17" case 1'1 case end @@ -175444,14 +175507,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_br $0\dec31_dec_sub27_br[0:0] end - attribute \src "libresoc.v:112754.3-112772.6" - process $proc$libresoc.v:112754$4313 + attribute \src "libresoc.v:112830.3-112848.6" + process $proc$libresoc.v:112830$4313 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sgn_ext[0:0] $1\dec31_dec_sub27_sgn_ext[0:0] - attribute \src "libresoc.v:112755.5-112755.29" + attribute \src "libresoc.v:112831.5-112831.29" switch \initial - attribute \src "libresoc.v:112755.9-112755.17" + attribute \src "libresoc.v:112831.9-112831.17" case 1'1 case end @@ -175479,14 +175542,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sgn_ext $0\dec31_dec_sub27_sgn_ext[0:0] end - attribute \src "libresoc.v:112773.3-112791.6" - process $proc$libresoc.v:112773$4314 + attribute \src "libresoc.v:112849.3-112867.6" + process $proc$libresoc.v:112849$4314 assign { } { } assign { } { } assign $0\dec31_dec_sub27_rsrv[0:0] $1\dec31_dec_sub27_rsrv[0:0] - attribute \src "libresoc.v:112774.5-112774.29" + attribute \src "libresoc.v:112850.5-112850.29" switch \initial - attribute \src "libresoc.v:112774.9-112774.17" + attribute \src "libresoc.v:112850.9-112850.17" case 1'1 case end @@ -175514,14 +175577,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_rsrv $0\dec31_dec_sub27_rsrv[0:0] end - attribute \src "libresoc.v:112792.3-112810.6" - process $proc$libresoc.v:112792$4315 + attribute \src "libresoc.v:112868.3-112886.6" + process $proc$libresoc.v:112868$4315 assign { } { } assign { } { } assign $0\dec31_dec_sub27_form[4:0] $1\dec31_dec_sub27_form[4:0] - attribute \src "libresoc.v:112793.5-112793.29" + attribute \src "libresoc.v:112869.5-112869.29" switch \initial - attribute \src "libresoc.v:112793.9-112793.17" + attribute \src "libresoc.v:112869.9-112869.17" case 1'1 case end @@ -175549,14 +175612,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_form $0\dec31_dec_sub27_form[4:0] end - attribute \src "libresoc.v:112811.3-112829.6" - process $proc$libresoc.v:112811$4316 + attribute \src "libresoc.v:112887.3-112905.6" + process $proc$libresoc.v:112887$4316 assign { } { } assign { } { } assign $0\dec31_dec_sub27_is_32b[0:0] $1\dec31_dec_sub27_is_32b[0:0] - attribute \src "libresoc.v:112812.5-112812.29" + attribute \src "libresoc.v:112888.5-112888.29" switch \initial - attribute \src "libresoc.v:112812.9-112812.17" + attribute \src "libresoc.v:112888.9-112888.17" case 1'1 case end @@ -175584,14 +175647,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_is_32b $0\dec31_dec_sub27_is_32b[0:0] end - attribute \src "libresoc.v:112830.3-112848.6" - process $proc$libresoc.v:112830$4317 + attribute \src "libresoc.v:112906.3-112924.6" + process $proc$libresoc.v:112906$4317 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sgn[0:0] $1\dec31_dec_sub27_sgn[0:0] - attribute \src "libresoc.v:112831.5-112831.29" + attribute \src "libresoc.v:112907.5-112907.29" switch \initial - attribute \src "libresoc.v:112831.9-112831.17" + attribute \src "libresoc.v:112907.9-112907.17" case 1'1 case end @@ -175619,14 +175682,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sgn $0\dec31_dec_sub27_sgn[0:0] end - attribute \src "libresoc.v:112849.3-112867.6" - process $proc$libresoc.v:112849$4318 + attribute \src "libresoc.v:112925.3-112943.6" + process $proc$libresoc.v:112925$4318 assign { } { } assign { } { } assign $0\dec31_dec_sub27_lk[0:0] $1\dec31_dec_sub27_lk[0:0] - attribute \src "libresoc.v:112850.5-112850.29" + attribute \src "libresoc.v:112926.5-112926.29" switch \initial - attribute \src "libresoc.v:112850.9-112850.17" + attribute \src "libresoc.v:112926.9-112926.17" case 1'1 case end @@ -175654,14 +175717,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_lk $0\dec31_dec_sub27_lk[0:0] end - attribute \src "libresoc.v:112868.3-112886.6" - process $proc$libresoc.v:112868$4319 + attribute \src "libresoc.v:112944.3-112962.6" + process $proc$libresoc.v:112944$4319 assign { } { } assign { } { } assign $0\dec31_dec_sub27_sgl_pipe[0:0] $1\dec31_dec_sub27_sgl_pipe[0:0] - attribute \src "libresoc.v:112869.5-112869.29" + attribute \src "libresoc.v:112945.5-112945.29" switch \initial - attribute \src "libresoc.v:112869.9-112869.17" + attribute \src "libresoc.v:112945.9-112945.17" case 1'1 case end @@ -175689,14 +175752,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_sgl_pipe $0\dec31_dec_sub27_sgl_pipe[0:0] end - attribute \src "libresoc.v:112887.3-112905.6" - process $proc$libresoc.v:112887$4320 + attribute \src "libresoc.v:112963.3-112981.6" + process $proc$libresoc.v:112963$4320 assign { } { } assign { } { } assign $0\dec31_dec_sub27_SV_Etype[1:0] $1\dec31_dec_sub27_SV_Etype[1:0] - attribute \src "libresoc.v:112888.5-112888.29" + attribute \src "libresoc.v:112964.5-112964.29" switch \initial - attribute \src "libresoc.v:112888.9-112888.17" + attribute \src "libresoc.v:112964.9-112964.17" case 1'1 case end @@ -175724,14 +175787,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_SV_Etype $0\dec31_dec_sub27_SV_Etype[1:0] end - attribute \src "libresoc.v:112906.3-112924.6" - process $proc$libresoc.v:112906$4321 + attribute \src "libresoc.v:112982.3-113000.6" + process $proc$libresoc.v:112982$4321 assign { } { } assign { } { } assign $0\dec31_dec_sub27_SV_Ptype[1:0] $1\dec31_dec_sub27_SV_Ptype[1:0] - attribute \src "libresoc.v:112907.5-112907.29" + attribute \src "libresoc.v:112983.5-112983.29" switch \initial - attribute \src "libresoc.v:112907.9-112907.17" + attribute \src "libresoc.v:112983.9-112983.17" case 1'1 case end @@ -175759,14 +175822,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_SV_Ptype $0\dec31_dec_sub27_SV_Ptype[1:0] end - attribute \src "libresoc.v:112925.3-112943.6" - process $proc$libresoc.v:112925$4322 + attribute \src "libresoc.v:113001.3-113019.6" + process $proc$libresoc.v:113001$4322 assign { } { } assign { } { } assign $0\dec31_dec_sub27_in1_sel[2:0] $1\dec31_dec_sub27_in1_sel[2:0] - attribute \src "libresoc.v:112926.5-112926.29" + attribute \src "libresoc.v:113002.5-113002.29" switch \initial - attribute \src "libresoc.v:112926.9-112926.17" + attribute \src "libresoc.v:113002.9-113002.17" case 1'1 case end @@ -175794,14 +175857,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_in1_sel $0\dec31_dec_sub27_in1_sel[2:0] end - attribute \src "libresoc.v:112944.3-112962.6" - process $proc$libresoc.v:112944$4323 + attribute \src "libresoc.v:113020.3-113038.6" + process $proc$libresoc.v:113020$4323 assign { } { } assign { } { } assign $0\dec31_dec_sub27_in2_sel[3:0] $1\dec31_dec_sub27_in2_sel[3:0] - attribute \src "libresoc.v:112945.5-112945.29" + attribute \src "libresoc.v:113021.5-113021.29" switch \initial - attribute \src "libresoc.v:112945.9-112945.17" + attribute \src "libresoc.v:113021.9-113021.17" case 1'1 case end @@ -175829,14 +175892,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_in2_sel $0\dec31_dec_sub27_in2_sel[3:0] end - attribute \src "libresoc.v:112963.3-112981.6" - process $proc$libresoc.v:112963$4324 + attribute \src "libresoc.v:113039.3-113057.6" + process $proc$libresoc.v:113039$4324 assign { } { } assign { } { } assign $0\dec31_dec_sub27_in3_sel[1:0] $1\dec31_dec_sub27_in3_sel[1:0] - attribute \src "libresoc.v:112964.5-112964.29" + attribute \src "libresoc.v:113040.5-113040.29" switch \initial - attribute \src "libresoc.v:112964.9-112964.17" + attribute \src "libresoc.v:113040.9-113040.17" case 1'1 case end @@ -175864,14 +175927,14 @@ module \dec31_dec_sub27 sync always update \dec31_dec_sub27_in3_sel $0\dec31_dec_sub27_in3_sel[1:0] end - attribute \src "libresoc.v:112982.3-113000.6" - process $proc$libresoc.v:112982$4325 + attribute \src "libresoc.v:113058.3-113076.6" + process $proc$libresoc.v:113058$4325 assign { } { } assign { } { } assign $0\dec31_dec_sub27_out_sel[2:0] $1\dec31_dec_sub27_out_sel[2:0] - attribute \src "libresoc.v:112983.5-112983.29" + attribute \src "libresoc.v:113059.5-113059.29" switch \initial - attribute \src "libresoc.v:112983.9-112983.17" + attribute \src "libresoc.v:113059.9-113059.17" case 1'1 case end @@ -175901,144 +175964,144 @@ module \dec31_dec_sub27 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:113006.1-114577.10" +attribute \src "libresoc.v:113082.1-114653.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub28" attribute \generator "nMigen" module \dec31_dec_sub28 - attribute \src "libresoc.v:114354.3-114390.6" + attribute \src "libresoc.v:114430.3-114466.6" wire width 2 $0\dec31_dec_sub28_SV_Etype[1:0] - attribute \src "libresoc.v:114391.3-114427.6" + attribute \src "libresoc.v:114467.3-114503.6" wire width 2 $0\dec31_dec_sub28_SV_Ptype[1:0] - attribute \src "libresoc.v:113910.3-113946.6" + attribute \src "libresoc.v:113986.3-114022.6" wire width 8 $0\dec31_dec_sub28_asmcode[7:0] - attribute \src "libresoc.v:114058.3-114094.6" + attribute \src "libresoc.v:114134.3-114170.6" wire $0\dec31_dec_sub28_br[0:0] - attribute \src "libresoc.v:113392.3-113428.6" + attribute \src "libresoc.v:113468.3-113504.6" wire width 3 $0\dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:113429.3-113465.6" + attribute \src "libresoc.v:113505.3-113541.6" wire width 3 $0\dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:113873.3-113909.6" + attribute \src "libresoc.v:113949.3-113985.6" wire width 2 $0\dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:114021.3-114057.6" + attribute \src "libresoc.v:114097.3-114133.6" wire $0\dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:114169.3-114205.6" + attribute \src "libresoc.v:114245.3-114281.6" wire width 5 $0\dec31_dec_sub28_form[4:0] - attribute \src "libresoc.v:113355.3-113391.6" + attribute \src "libresoc.v:113431.3-113467.6" wire width 14 $0\dec31_dec_sub28_function_unit[13:0] - attribute \src "libresoc.v:114428.3-114464.6" + attribute \src "libresoc.v:114504.3-114540.6" wire width 3 $0\dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:114465.3-114501.6" + attribute \src "libresoc.v:114541.3-114577.6" wire width 4 $0\dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:114502.3-114538.6" + attribute \src "libresoc.v:114578.3-114614.6" wire width 2 $0\dec31_dec_sub28_in3_sel[1:0] - attribute \src "libresoc.v:113762.3-113798.6" + attribute \src "libresoc.v:113838.3-113874.6" wire width 7 $0\dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:113947.3-113983.6" + attribute \src "libresoc.v:114023.3-114059.6" wire $0\dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:113984.3-114020.6" + attribute \src "libresoc.v:114060.3-114096.6" wire $0\dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:114206.3-114242.6" + attribute \src "libresoc.v:114282.3-114318.6" wire $0\dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:113725.3-113761.6" + attribute \src "libresoc.v:113801.3-113837.6" wire width 4 $0\dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:114280.3-114316.6" + attribute \src "libresoc.v:114356.3-114392.6" wire $0\dec31_dec_sub28_lk[0:0] - attribute \src "libresoc.v:114539.3-114575.6" + attribute \src "libresoc.v:114615.3-114651.6" wire width 3 $0\dec31_dec_sub28_out_sel[2:0] - attribute \src "libresoc.v:113836.3-113872.6" + attribute \src "libresoc.v:113912.3-113948.6" wire width 2 $0\dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:114132.3-114168.6" + attribute \src "libresoc.v:114208.3-114244.6" wire $0\dec31_dec_sub28_rsrv[0:0] - attribute \src "libresoc.v:114317.3-114353.6" + attribute \src "libresoc.v:114393.3-114429.6" wire $0\dec31_dec_sub28_sgl_pipe[0:0] - attribute \src "libresoc.v:114243.3-114279.6" + attribute \src "libresoc.v:114319.3-114355.6" wire $0\dec31_dec_sub28_sgn[0:0] - attribute \src "libresoc.v:114095.3-114131.6" + attribute \src "libresoc.v:114171.3-114207.6" wire $0\dec31_dec_sub28_sgn_ext[0:0] - attribute \src "libresoc.v:113651.3-113687.6" + attribute \src "libresoc.v:113727.3-113763.6" wire width 3 $0\dec31_dec_sub28_sv_cr_in[2:0] - attribute \src "libresoc.v:113688.3-113724.6" + attribute \src "libresoc.v:113764.3-113800.6" wire width 3 $0\dec31_dec_sub28_sv_cr_out[2:0] - attribute \src "libresoc.v:113466.3-113502.6" + attribute \src "libresoc.v:113542.3-113578.6" wire width 3 $0\dec31_dec_sub28_sv_in1[2:0] - attribute \src "libresoc.v:113503.3-113539.6" + attribute \src "libresoc.v:113579.3-113615.6" wire width 3 $0\dec31_dec_sub28_sv_in2[2:0] - attribute \src "libresoc.v:113540.3-113576.6" + attribute \src "libresoc.v:113616.3-113652.6" wire width 3 $0\dec31_dec_sub28_sv_in3[2:0] - attribute \src "libresoc.v:113614.3-113650.6" + attribute \src "libresoc.v:113690.3-113726.6" wire width 3 $0\dec31_dec_sub28_sv_out2[2:0] - attribute \src "libresoc.v:113577.3-113613.6" + attribute \src "libresoc.v:113653.3-113689.6" wire width 3 $0\dec31_dec_sub28_sv_out[2:0] - attribute \src "libresoc.v:113799.3-113835.6" + attribute \src "libresoc.v:113875.3-113911.6" wire width 2 $0\dec31_dec_sub28_upd[1:0] - attribute \src "libresoc.v:113007.7-113007.20" + attribute \src "libresoc.v:113083.7-113083.20" wire $0\initial[0:0] - attribute \src "libresoc.v:114354.3-114390.6" + attribute \src "libresoc.v:114430.3-114466.6" wire width 2 $1\dec31_dec_sub28_SV_Etype[1:0] - attribute \src "libresoc.v:114391.3-114427.6" + attribute \src "libresoc.v:114467.3-114503.6" wire width 2 $1\dec31_dec_sub28_SV_Ptype[1:0] - attribute \src "libresoc.v:113910.3-113946.6" + attribute \src "libresoc.v:113986.3-114022.6" wire width 8 $1\dec31_dec_sub28_asmcode[7:0] - attribute \src "libresoc.v:114058.3-114094.6" + attribute \src "libresoc.v:114134.3-114170.6" wire $1\dec31_dec_sub28_br[0:0] - attribute \src "libresoc.v:113392.3-113428.6" + attribute \src "libresoc.v:113468.3-113504.6" wire width 3 $1\dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:113429.3-113465.6" + attribute \src "libresoc.v:113505.3-113541.6" wire width 3 $1\dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:113873.3-113909.6" + attribute \src "libresoc.v:113949.3-113985.6" wire width 2 $1\dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:114021.3-114057.6" + attribute \src "libresoc.v:114097.3-114133.6" wire $1\dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:114169.3-114205.6" + attribute \src "libresoc.v:114245.3-114281.6" wire width 5 $1\dec31_dec_sub28_form[4:0] - attribute \src "libresoc.v:113355.3-113391.6" + attribute \src "libresoc.v:113431.3-113467.6" wire width 14 $1\dec31_dec_sub28_function_unit[13:0] - attribute \src "libresoc.v:114428.3-114464.6" + attribute \src "libresoc.v:114504.3-114540.6" wire width 3 $1\dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:114465.3-114501.6" + attribute \src "libresoc.v:114541.3-114577.6" wire width 4 $1\dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:114502.3-114538.6" + attribute \src "libresoc.v:114578.3-114614.6" wire width 2 $1\dec31_dec_sub28_in3_sel[1:0] - attribute \src "libresoc.v:113762.3-113798.6" + attribute \src "libresoc.v:113838.3-113874.6" wire width 7 $1\dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:113947.3-113983.6" + attribute \src "libresoc.v:114023.3-114059.6" wire $1\dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:113984.3-114020.6" + attribute \src "libresoc.v:114060.3-114096.6" wire $1\dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:114206.3-114242.6" + attribute \src "libresoc.v:114282.3-114318.6" wire $1\dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:113725.3-113761.6" + attribute \src "libresoc.v:113801.3-113837.6" wire width 4 $1\dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:114280.3-114316.6" + attribute \src "libresoc.v:114356.3-114392.6" wire $1\dec31_dec_sub28_lk[0:0] - attribute \src "libresoc.v:114539.3-114575.6" + attribute \src "libresoc.v:114615.3-114651.6" wire width 3 $1\dec31_dec_sub28_out_sel[2:0] - attribute \src "libresoc.v:113836.3-113872.6" + attribute \src "libresoc.v:113912.3-113948.6" wire width 2 $1\dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:114132.3-114168.6" + attribute \src "libresoc.v:114208.3-114244.6" wire $1\dec31_dec_sub28_rsrv[0:0] - attribute \src "libresoc.v:114317.3-114353.6" + attribute \src "libresoc.v:114393.3-114429.6" wire $1\dec31_dec_sub28_sgl_pipe[0:0] - attribute \src "libresoc.v:114243.3-114279.6" + attribute \src "libresoc.v:114319.3-114355.6" wire $1\dec31_dec_sub28_sgn[0:0] - attribute \src "libresoc.v:114095.3-114131.6" + attribute \src "libresoc.v:114171.3-114207.6" wire $1\dec31_dec_sub28_sgn_ext[0:0] - attribute \src "libresoc.v:113651.3-113687.6" + attribute \src "libresoc.v:113727.3-113763.6" wire width 3 $1\dec31_dec_sub28_sv_cr_in[2:0] - attribute \src "libresoc.v:113688.3-113724.6" + attribute \src "libresoc.v:113764.3-113800.6" wire width 3 $1\dec31_dec_sub28_sv_cr_out[2:0] - attribute \src "libresoc.v:113466.3-113502.6" + attribute \src "libresoc.v:113542.3-113578.6" wire width 3 $1\dec31_dec_sub28_sv_in1[2:0] - attribute \src "libresoc.v:113503.3-113539.6" + attribute \src "libresoc.v:113579.3-113615.6" wire width 3 $1\dec31_dec_sub28_sv_in2[2:0] - attribute \src "libresoc.v:113540.3-113576.6" + attribute \src "libresoc.v:113616.3-113652.6" wire width 3 $1\dec31_dec_sub28_sv_in3[2:0] - attribute \src "libresoc.v:113614.3-113650.6" + attribute \src "libresoc.v:113690.3-113726.6" wire width 3 $1\dec31_dec_sub28_sv_out2[2:0] - attribute \src "libresoc.v:113577.3-113613.6" + attribute \src "libresoc.v:113653.3-113689.6" wire width 3 $1\dec31_dec_sub28_sv_out[2:0] - attribute \src "libresoc.v:113799.3-113835.6" + attribute \src "libresoc.v:113875.3-113911.6" wire width 2 $1\dec31_dec_sub28_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -176350,28 +176413,28 @@ module \dec31_dec_sub28 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub28_upd - attribute \src "libresoc.v:113007.7-113007.15" + attribute \src "libresoc.v:113083.7-113083.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:113007.7-113007.20" - process $proc$libresoc.v:113007$4360 + attribute \src "libresoc.v:113083.7-113083.20" + process $proc$libresoc.v:113083$4360 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:113355.3-113391.6" - process $proc$libresoc.v:113355$4327 + attribute \src "libresoc.v:113431.3-113467.6" + process $proc$libresoc.v:113431$4327 assign { } { } assign { } { } assign $0\dec31_dec_sub28_function_unit[13:0] $1\dec31_dec_sub28_function_unit[13:0] - attribute \src "libresoc.v:113356.5-113356.29" + attribute \src "libresoc.v:113432.5-113432.29" switch \initial - attribute \src "libresoc.v:113356.9-113356.17" + attribute \src "libresoc.v:113432.9-113432.17" case 1'1 case end @@ -176423,14 +176486,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_function_unit $0\dec31_dec_sub28_function_unit[13:0] end - attribute \src "libresoc.v:113392.3-113428.6" - process $proc$libresoc.v:113392$4328 + attribute \src "libresoc.v:113468.3-113504.6" + process $proc$libresoc.v:113468$4328 assign { } { } assign { } { } assign $0\dec31_dec_sub28_cr_in[2:0] $1\dec31_dec_sub28_cr_in[2:0] - attribute \src "libresoc.v:113393.5-113393.29" + attribute \src "libresoc.v:113469.5-113469.29" switch \initial - attribute \src "libresoc.v:113393.9-113393.17" + attribute \src "libresoc.v:113469.9-113469.17" case 1'1 case end @@ -176482,14 +176545,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_cr_in $0\dec31_dec_sub28_cr_in[2:0] end - attribute \src "libresoc.v:113429.3-113465.6" - process $proc$libresoc.v:113429$4329 + attribute \src "libresoc.v:113505.3-113541.6" + process $proc$libresoc.v:113505$4329 assign { } { } assign { } { } assign $0\dec31_dec_sub28_cr_out[2:0] $1\dec31_dec_sub28_cr_out[2:0] - attribute \src "libresoc.v:113430.5-113430.29" + attribute \src "libresoc.v:113506.5-113506.29" switch \initial - attribute \src "libresoc.v:113430.9-113430.17" + attribute \src "libresoc.v:113506.9-113506.17" case 1'1 case end @@ -176541,14 +176604,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_cr_out $0\dec31_dec_sub28_cr_out[2:0] end - attribute \src "libresoc.v:113466.3-113502.6" - process $proc$libresoc.v:113466$4330 + attribute \src "libresoc.v:113542.3-113578.6" + process $proc$libresoc.v:113542$4330 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_in1[2:0] $1\dec31_dec_sub28_sv_in1[2:0] - attribute \src "libresoc.v:113467.5-113467.29" + attribute \src "libresoc.v:113543.5-113543.29" switch \initial - attribute \src "libresoc.v:113467.9-113467.17" + attribute \src "libresoc.v:113543.9-113543.17" case 1'1 case end @@ -176600,14 +176663,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_in1 $0\dec31_dec_sub28_sv_in1[2:0] end - attribute \src "libresoc.v:113503.3-113539.6" - process $proc$libresoc.v:113503$4331 + attribute \src "libresoc.v:113579.3-113615.6" + process $proc$libresoc.v:113579$4331 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_in2[2:0] $1\dec31_dec_sub28_sv_in2[2:0] - attribute \src "libresoc.v:113504.5-113504.29" + attribute \src "libresoc.v:113580.5-113580.29" switch \initial - attribute \src "libresoc.v:113504.9-113504.17" + attribute \src "libresoc.v:113580.9-113580.17" case 1'1 case end @@ -176659,14 +176722,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_in2 $0\dec31_dec_sub28_sv_in2[2:0] end - attribute \src "libresoc.v:113540.3-113576.6" - process $proc$libresoc.v:113540$4332 + attribute \src "libresoc.v:113616.3-113652.6" + process $proc$libresoc.v:113616$4332 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_in3[2:0] $1\dec31_dec_sub28_sv_in3[2:0] - attribute \src "libresoc.v:113541.5-113541.29" + attribute \src "libresoc.v:113617.5-113617.29" switch \initial - attribute \src "libresoc.v:113541.9-113541.17" + attribute \src "libresoc.v:113617.9-113617.17" case 1'1 case end @@ -176718,14 +176781,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_in3 $0\dec31_dec_sub28_sv_in3[2:0] end - attribute \src "libresoc.v:113577.3-113613.6" - process $proc$libresoc.v:113577$4333 + attribute \src "libresoc.v:113653.3-113689.6" + process $proc$libresoc.v:113653$4333 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_out[2:0] $1\dec31_dec_sub28_sv_out[2:0] - attribute \src "libresoc.v:113578.5-113578.29" + attribute \src "libresoc.v:113654.5-113654.29" switch \initial - attribute \src "libresoc.v:113578.9-113578.17" + attribute \src "libresoc.v:113654.9-113654.17" case 1'1 case end @@ -176777,14 +176840,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_out $0\dec31_dec_sub28_sv_out[2:0] end - attribute \src "libresoc.v:113614.3-113650.6" - process $proc$libresoc.v:113614$4334 + attribute \src "libresoc.v:113690.3-113726.6" + process $proc$libresoc.v:113690$4334 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_out2[2:0] $1\dec31_dec_sub28_sv_out2[2:0] - attribute \src "libresoc.v:113615.5-113615.29" + attribute \src "libresoc.v:113691.5-113691.29" switch \initial - attribute \src "libresoc.v:113615.9-113615.17" + attribute \src "libresoc.v:113691.9-113691.17" case 1'1 case end @@ -176836,14 +176899,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_out2 $0\dec31_dec_sub28_sv_out2[2:0] end - attribute \src "libresoc.v:113651.3-113687.6" - process $proc$libresoc.v:113651$4335 + attribute \src "libresoc.v:113727.3-113763.6" + process $proc$libresoc.v:113727$4335 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_cr_in[2:0] $1\dec31_dec_sub28_sv_cr_in[2:0] - attribute \src "libresoc.v:113652.5-113652.29" + attribute \src "libresoc.v:113728.5-113728.29" switch \initial - attribute \src "libresoc.v:113652.9-113652.17" + attribute \src "libresoc.v:113728.9-113728.17" case 1'1 case end @@ -176895,14 +176958,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_cr_in $0\dec31_dec_sub28_sv_cr_in[2:0] end - attribute \src "libresoc.v:113688.3-113724.6" - process $proc$libresoc.v:113688$4336 + attribute \src "libresoc.v:113764.3-113800.6" + process $proc$libresoc.v:113764$4336 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sv_cr_out[2:0] $1\dec31_dec_sub28_sv_cr_out[2:0] - attribute \src "libresoc.v:113689.5-113689.29" + attribute \src "libresoc.v:113765.5-113765.29" switch \initial - attribute \src "libresoc.v:113689.9-113689.17" + attribute \src "libresoc.v:113765.9-113765.17" case 1'1 case end @@ -176954,14 +177017,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sv_cr_out $0\dec31_dec_sub28_sv_cr_out[2:0] end - attribute \src "libresoc.v:113725.3-113761.6" - process $proc$libresoc.v:113725$4337 + attribute \src "libresoc.v:113801.3-113837.6" + process $proc$libresoc.v:113801$4337 assign { } { } assign { } { } assign $0\dec31_dec_sub28_ldst_len[3:0] $1\dec31_dec_sub28_ldst_len[3:0] - attribute \src "libresoc.v:113726.5-113726.29" + attribute \src "libresoc.v:113802.5-113802.29" switch \initial - attribute \src "libresoc.v:113726.9-113726.17" + attribute \src "libresoc.v:113802.9-113802.17" case 1'1 case end @@ -177013,14 +177076,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_ldst_len $0\dec31_dec_sub28_ldst_len[3:0] end - attribute \src "libresoc.v:113762.3-113798.6" - process $proc$libresoc.v:113762$4338 + attribute \src "libresoc.v:113838.3-113874.6" + process $proc$libresoc.v:113838$4338 assign { } { } assign { } { } assign $0\dec31_dec_sub28_internal_op[6:0] $1\dec31_dec_sub28_internal_op[6:0] - attribute \src "libresoc.v:113763.5-113763.29" + attribute \src "libresoc.v:113839.5-113839.29" switch \initial - attribute \src "libresoc.v:113763.9-113763.17" + attribute \src "libresoc.v:113839.9-113839.17" case 1'1 case end @@ -177072,14 +177135,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_internal_op $0\dec31_dec_sub28_internal_op[6:0] end - attribute \src "libresoc.v:113799.3-113835.6" - process $proc$libresoc.v:113799$4339 + attribute \src "libresoc.v:113875.3-113911.6" + process $proc$libresoc.v:113875$4339 assign { } { } assign { } { } assign $0\dec31_dec_sub28_upd[1:0] $1\dec31_dec_sub28_upd[1:0] - attribute \src "libresoc.v:113800.5-113800.29" + attribute \src "libresoc.v:113876.5-113876.29" switch \initial - attribute \src "libresoc.v:113800.9-113800.17" + attribute \src "libresoc.v:113876.9-113876.17" case 1'1 case end @@ -177131,14 +177194,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_upd $0\dec31_dec_sub28_upd[1:0] end - attribute \src "libresoc.v:113836.3-113872.6" - process $proc$libresoc.v:113836$4340 + attribute \src "libresoc.v:113912.3-113948.6" + process $proc$libresoc.v:113912$4340 assign { } { } assign { } { } assign $0\dec31_dec_sub28_rc_sel[1:0] $1\dec31_dec_sub28_rc_sel[1:0] - attribute \src "libresoc.v:113837.5-113837.29" + attribute \src "libresoc.v:113913.5-113913.29" switch \initial - attribute \src "libresoc.v:113837.9-113837.17" + attribute \src "libresoc.v:113913.9-113913.17" case 1'1 case end @@ -177190,14 +177253,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_rc_sel $0\dec31_dec_sub28_rc_sel[1:0] end - attribute \src "libresoc.v:113873.3-113909.6" - process $proc$libresoc.v:113873$4341 + attribute \src "libresoc.v:113949.3-113985.6" + process $proc$libresoc.v:113949$4341 assign { } { } assign { } { } assign $0\dec31_dec_sub28_cry_in[1:0] $1\dec31_dec_sub28_cry_in[1:0] - attribute \src "libresoc.v:113874.5-113874.29" + attribute \src "libresoc.v:113950.5-113950.29" switch \initial - attribute \src "libresoc.v:113874.9-113874.17" + attribute \src "libresoc.v:113950.9-113950.17" case 1'1 case end @@ -177249,14 +177312,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_cry_in $0\dec31_dec_sub28_cry_in[1:0] end - attribute \src "libresoc.v:113910.3-113946.6" - process $proc$libresoc.v:113910$4342 + attribute \src "libresoc.v:113986.3-114022.6" + process $proc$libresoc.v:113986$4342 assign { } { } assign { } { } assign $0\dec31_dec_sub28_asmcode[7:0] $1\dec31_dec_sub28_asmcode[7:0] - attribute \src "libresoc.v:113911.5-113911.29" + attribute \src "libresoc.v:113987.5-113987.29" switch \initial - attribute \src "libresoc.v:113911.9-113911.17" + attribute \src "libresoc.v:113987.9-113987.17" case 1'1 case end @@ -177308,14 +177371,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_asmcode $0\dec31_dec_sub28_asmcode[7:0] end - attribute \src "libresoc.v:113947.3-113983.6" - process $proc$libresoc.v:113947$4343 + attribute \src "libresoc.v:114023.3-114059.6" + process $proc$libresoc.v:114023$4343 assign { } { } assign { } { } assign $0\dec31_dec_sub28_inv_a[0:0] $1\dec31_dec_sub28_inv_a[0:0] - attribute \src "libresoc.v:113948.5-113948.29" + attribute \src "libresoc.v:114024.5-114024.29" switch \initial - attribute \src "libresoc.v:113948.9-113948.17" + attribute \src "libresoc.v:114024.9-114024.17" case 1'1 case end @@ -177367,14 +177430,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_inv_a $0\dec31_dec_sub28_inv_a[0:0] end - attribute \src "libresoc.v:113984.3-114020.6" - process $proc$libresoc.v:113984$4344 + attribute \src "libresoc.v:114060.3-114096.6" + process $proc$libresoc.v:114060$4344 assign { } { } assign { } { } assign $0\dec31_dec_sub28_inv_out[0:0] $1\dec31_dec_sub28_inv_out[0:0] - attribute \src "libresoc.v:113985.5-113985.29" + attribute \src "libresoc.v:114061.5-114061.29" switch \initial - attribute \src "libresoc.v:113985.9-113985.17" + attribute \src "libresoc.v:114061.9-114061.17" case 1'1 case end @@ -177426,14 +177489,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_inv_out $0\dec31_dec_sub28_inv_out[0:0] end - attribute \src "libresoc.v:114021.3-114057.6" - process $proc$libresoc.v:114021$4345 + attribute \src "libresoc.v:114097.3-114133.6" + process $proc$libresoc.v:114097$4345 assign { } { } assign { } { } assign $0\dec31_dec_sub28_cry_out[0:0] $1\dec31_dec_sub28_cry_out[0:0] - attribute \src "libresoc.v:114022.5-114022.29" + attribute \src "libresoc.v:114098.5-114098.29" switch \initial - attribute \src "libresoc.v:114022.9-114022.17" + attribute \src "libresoc.v:114098.9-114098.17" case 1'1 case end @@ -177485,14 +177548,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_cry_out $0\dec31_dec_sub28_cry_out[0:0] end - attribute \src "libresoc.v:114058.3-114094.6" - process $proc$libresoc.v:114058$4346 + attribute \src "libresoc.v:114134.3-114170.6" + process $proc$libresoc.v:114134$4346 assign { } { } assign { } { } assign $0\dec31_dec_sub28_br[0:0] $1\dec31_dec_sub28_br[0:0] - attribute \src "libresoc.v:114059.5-114059.29" + attribute \src "libresoc.v:114135.5-114135.29" switch \initial - attribute \src "libresoc.v:114059.9-114059.17" + attribute \src "libresoc.v:114135.9-114135.17" case 1'1 case end @@ -177544,14 +177607,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_br $0\dec31_dec_sub28_br[0:0] end - attribute \src "libresoc.v:114095.3-114131.6" - process $proc$libresoc.v:114095$4347 + attribute \src "libresoc.v:114171.3-114207.6" + process $proc$libresoc.v:114171$4347 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sgn_ext[0:0] $1\dec31_dec_sub28_sgn_ext[0:0] - attribute \src "libresoc.v:114096.5-114096.29" + attribute \src "libresoc.v:114172.5-114172.29" switch \initial - attribute \src "libresoc.v:114096.9-114096.17" + attribute \src "libresoc.v:114172.9-114172.17" case 1'1 case end @@ -177603,14 +177666,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sgn_ext $0\dec31_dec_sub28_sgn_ext[0:0] end - attribute \src "libresoc.v:114132.3-114168.6" - process $proc$libresoc.v:114132$4348 + attribute \src "libresoc.v:114208.3-114244.6" + process $proc$libresoc.v:114208$4348 assign { } { } assign { } { } assign $0\dec31_dec_sub28_rsrv[0:0] $1\dec31_dec_sub28_rsrv[0:0] - attribute \src "libresoc.v:114133.5-114133.29" + attribute \src "libresoc.v:114209.5-114209.29" switch \initial - attribute \src "libresoc.v:114133.9-114133.17" + attribute \src "libresoc.v:114209.9-114209.17" case 1'1 case end @@ -177662,14 +177725,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_rsrv $0\dec31_dec_sub28_rsrv[0:0] end - attribute \src "libresoc.v:114169.3-114205.6" - process $proc$libresoc.v:114169$4349 + attribute \src "libresoc.v:114245.3-114281.6" + process $proc$libresoc.v:114245$4349 assign { } { } assign { } { } assign $0\dec31_dec_sub28_form[4:0] $1\dec31_dec_sub28_form[4:0] - attribute \src "libresoc.v:114170.5-114170.29" + attribute \src "libresoc.v:114246.5-114246.29" switch \initial - attribute \src "libresoc.v:114170.9-114170.17" + attribute \src "libresoc.v:114246.9-114246.17" case 1'1 case end @@ -177721,14 +177784,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_form $0\dec31_dec_sub28_form[4:0] end - attribute \src "libresoc.v:114206.3-114242.6" - process $proc$libresoc.v:114206$4350 + attribute \src "libresoc.v:114282.3-114318.6" + process $proc$libresoc.v:114282$4350 assign { } { } assign { } { } assign $0\dec31_dec_sub28_is_32b[0:0] $1\dec31_dec_sub28_is_32b[0:0] - attribute \src "libresoc.v:114207.5-114207.29" + attribute \src "libresoc.v:114283.5-114283.29" switch \initial - attribute \src "libresoc.v:114207.9-114207.17" + attribute \src "libresoc.v:114283.9-114283.17" case 1'1 case end @@ -177780,14 +177843,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_is_32b $0\dec31_dec_sub28_is_32b[0:0] end - attribute \src "libresoc.v:114243.3-114279.6" - process $proc$libresoc.v:114243$4351 + attribute \src "libresoc.v:114319.3-114355.6" + process $proc$libresoc.v:114319$4351 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sgn[0:0] $1\dec31_dec_sub28_sgn[0:0] - attribute \src "libresoc.v:114244.5-114244.29" + attribute \src "libresoc.v:114320.5-114320.29" switch \initial - attribute \src "libresoc.v:114244.9-114244.17" + attribute \src "libresoc.v:114320.9-114320.17" case 1'1 case end @@ -177839,14 +177902,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sgn $0\dec31_dec_sub28_sgn[0:0] end - attribute \src "libresoc.v:114280.3-114316.6" - process $proc$libresoc.v:114280$4352 + attribute \src "libresoc.v:114356.3-114392.6" + process $proc$libresoc.v:114356$4352 assign { } { } assign { } { } assign $0\dec31_dec_sub28_lk[0:0] $1\dec31_dec_sub28_lk[0:0] - attribute \src "libresoc.v:114281.5-114281.29" + attribute \src "libresoc.v:114357.5-114357.29" switch \initial - attribute \src "libresoc.v:114281.9-114281.17" + attribute \src "libresoc.v:114357.9-114357.17" case 1'1 case end @@ -177898,14 +177961,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_lk $0\dec31_dec_sub28_lk[0:0] end - attribute \src "libresoc.v:114317.3-114353.6" - process $proc$libresoc.v:114317$4353 + attribute \src "libresoc.v:114393.3-114429.6" + process $proc$libresoc.v:114393$4353 assign { } { } assign { } { } assign $0\dec31_dec_sub28_sgl_pipe[0:0] $1\dec31_dec_sub28_sgl_pipe[0:0] - attribute \src "libresoc.v:114318.5-114318.29" + attribute \src "libresoc.v:114394.5-114394.29" switch \initial - attribute \src "libresoc.v:114318.9-114318.17" + attribute \src "libresoc.v:114394.9-114394.17" case 1'1 case end @@ -177957,14 +178020,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_sgl_pipe $0\dec31_dec_sub28_sgl_pipe[0:0] end - attribute \src "libresoc.v:114354.3-114390.6" - process $proc$libresoc.v:114354$4354 + attribute \src "libresoc.v:114430.3-114466.6" + process $proc$libresoc.v:114430$4354 assign { } { } assign { } { } assign $0\dec31_dec_sub28_SV_Etype[1:0] $1\dec31_dec_sub28_SV_Etype[1:0] - attribute \src "libresoc.v:114355.5-114355.29" + attribute \src "libresoc.v:114431.5-114431.29" switch \initial - attribute \src "libresoc.v:114355.9-114355.17" + attribute \src "libresoc.v:114431.9-114431.17" case 1'1 case end @@ -178016,14 +178079,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_SV_Etype $0\dec31_dec_sub28_SV_Etype[1:0] end - attribute \src "libresoc.v:114391.3-114427.6" - process $proc$libresoc.v:114391$4355 + attribute \src "libresoc.v:114467.3-114503.6" + process $proc$libresoc.v:114467$4355 assign { } { } assign { } { } assign $0\dec31_dec_sub28_SV_Ptype[1:0] $1\dec31_dec_sub28_SV_Ptype[1:0] - attribute \src "libresoc.v:114392.5-114392.29" + attribute \src "libresoc.v:114468.5-114468.29" switch \initial - attribute \src "libresoc.v:114392.9-114392.17" + attribute \src "libresoc.v:114468.9-114468.17" case 1'1 case end @@ -178075,14 +178138,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_SV_Ptype $0\dec31_dec_sub28_SV_Ptype[1:0] end - attribute \src "libresoc.v:114428.3-114464.6" - process $proc$libresoc.v:114428$4356 + attribute \src "libresoc.v:114504.3-114540.6" + process $proc$libresoc.v:114504$4356 assign { } { } assign { } { } assign $0\dec31_dec_sub28_in1_sel[2:0] $1\dec31_dec_sub28_in1_sel[2:0] - attribute \src "libresoc.v:114429.5-114429.29" + attribute \src "libresoc.v:114505.5-114505.29" switch \initial - attribute \src "libresoc.v:114429.9-114429.17" + attribute \src "libresoc.v:114505.9-114505.17" case 1'1 case end @@ -178134,14 +178197,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_in1_sel $0\dec31_dec_sub28_in1_sel[2:0] end - attribute \src "libresoc.v:114465.3-114501.6" - process $proc$libresoc.v:114465$4357 + attribute \src "libresoc.v:114541.3-114577.6" + process $proc$libresoc.v:114541$4357 assign { } { } assign { } { } assign $0\dec31_dec_sub28_in2_sel[3:0] $1\dec31_dec_sub28_in2_sel[3:0] - attribute \src "libresoc.v:114466.5-114466.29" + attribute \src "libresoc.v:114542.5-114542.29" switch \initial - attribute \src "libresoc.v:114466.9-114466.17" + attribute \src "libresoc.v:114542.9-114542.17" case 1'1 case end @@ -178193,14 +178256,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_in2_sel $0\dec31_dec_sub28_in2_sel[3:0] end - attribute \src "libresoc.v:114502.3-114538.6" - process $proc$libresoc.v:114502$4358 + attribute \src "libresoc.v:114578.3-114614.6" + process $proc$libresoc.v:114578$4358 assign { } { } assign { } { } assign $0\dec31_dec_sub28_in3_sel[1:0] $1\dec31_dec_sub28_in3_sel[1:0] - attribute \src "libresoc.v:114503.5-114503.29" + attribute \src "libresoc.v:114579.5-114579.29" switch \initial - attribute \src "libresoc.v:114503.9-114503.17" + attribute \src "libresoc.v:114579.9-114579.17" case 1'1 case end @@ -178252,14 +178315,14 @@ module \dec31_dec_sub28 sync always update \dec31_dec_sub28_in3_sel $0\dec31_dec_sub28_in3_sel[1:0] end - attribute \src "libresoc.v:114539.3-114575.6" - process $proc$libresoc.v:114539$4359 + attribute \src "libresoc.v:114615.3-114651.6" + process $proc$libresoc.v:114615$4359 assign { } { } assign { } { } assign $0\dec31_dec_sub28_out_sel[2:0] $1\dec31_dec_sub28_out_sel[2:0] - attribute \src "libresoc.v:114540.5-114540.29" + attribute \src "libresoc.v:114616.5-114616.29" switch \initial - attribute \src "libresoc.v:114540.9-114540.17" + attribute \src "libresoc.v:114616.9-114616.17" case 1'1 case end @@ -178313,144 +178376,144 @@ module \dec31_dec_sub28 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:114581.1-115360.10" +attribute \src "libresoc.v:114657.1-115436.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub4" attribute \generator "nMigen" module \dec31_dec_sub4 - attribute \src "libresoc.v:115281.3-115293.6" + attribute \src "libresoc.v:115357.3-115369.6" wire width 2 $0\dec31_dec_sub4_SV_Etype[1:0] - attribute \src "libresoc.v:115294.3-115306.6" + attribute \src "libresoc.v:115370.3-115382.6" wire width 2 $0\dec31_dec_sub4_SV_Ptype[1:0] - attribute \src "libresoc.v:115125.3-115137.6" + attribute \src "libresoc.v:115201.3-115213.6" wire width 8 $0\dec31_dec_sub4_asmcode[7:0] - attribute \src "libresoc.v:115177.3-115189.6" + attribute \src "libresoc.v:115253.3-115265.6" wire $0\dec31_dec_sub4_br[0:0] - attribute \src "libresoc.v:114943.3-114955.6" + attribute \src "libresoc.v:115019.3-115031.6" wire width 3 $0\dec31_dec_sub4_cr_in[2:0] - attribute \src "libresoc.v:114956.3-114968.6" + attribute \src "libresoc.v:115032.3-115044.6" wire width 3 $0\dec31_dec_sub4_cr_out[2:0] - attribute \src "libresoc.v:115112.3-115124.6" + attribute \src "libresoc.v:115188.3-115200.6" wire width 2 $0\dec31_dec_sub4_cry_in[1:0] - attribute \src "libresoc.v:115164.3-115176.6" + attribute \src "libresoc.v:115240.3-115252.6" wire $0\dec31_dec_sub4_cry_out[0:0] - attribute \src "libresoc.v:115216.3-115228.6" + attribute \src "libresoc.v:115292.3-115304.6" wire width 5 $0\dec31_dec_sub4_form[4:0] - attribute \src "libresoc.v:114930.3-114942.6" + attribute \src "libresoc.v:115006.3-115018.6" wire width 14 $0\dec31_dec_sub4_function_unit[13:0] - attribute \src "libresoc.v:115307.3-115319.6" + attribute \src "libresoc.v:115383.3-115395.6" wire width 3 $0\dec31_dec_sub4_in1_sel[2:0] - attribute \src "libresoc.v:115320.3-115332.6" + attribute \src "libresoc.v:115396.3-115408.6" wire width 4 $0\dec31_dec_sub4_in2_sel[3:0] - attribute \src "libresoc.v:115333.3-115345.6" + attribute \src "libresoc.v:115409.3-115421.6" wire width 2 $0\dec31_dec_sub4_in3_sel[1:0] - attribute \src "libresoc.v:115073.3-115085.6" + attribute \src "libresoc.v:115149.3-115161.6" wire width 7 $0\dec31_dec_sub4_internal_op[6:0] - attribute \src "libresoc.v:115138.3-115150.6" + attribute \src "libresoc.v:115214.3-115226.6" wire $0\dec31_dec_sub4_inv_a[0:0] - attribute \src "libresoc.v:115151.3-115163.6" + attribute \src "libresoc.v:115227.3-115239.6" wire $0\dec31_dec_sub4_inv_out[0:0] - attribute \src "libresoc.v:115229.3-115241.6" + attribute \src "libresoc.v:115305.3-115317.6" wire $0\dec31_dec_sub4_is_32b[0:0] - attribute \src "libresoc.v:115060.3-115072.6" + attribute \src "libresoc.v:115136.3-115148.6" wire width 4 $0\dec31_dec_sub4_ldst_len[3:0] - attribute \src "libresoc.v:115255.3-115267.6" + attribute \src "libresoc.v:115331.3-115343.6" wire $0\dec31_dec_sub4_lk[0:0] - attribute \src "libresoc.v:115346.3-115358.6" + attribute \src "libresoc.v:115422.3-115434.6" wire width 3 $0\dec31_dec_sub4_out_sel[2:0] - attribute \src "libresoc.v:115099.3-115111.6" + attribute \src "libresoc.v:115175.3-115187.6" wire width 2 $0\dec31_dec_sub4_rc_sel[1:0] - attribute \src "libresoc.v:115203.3-115215.6" + attribute \src "libresoc.v:115279.3-115291.6" wire $0\dec31_dec_sub4_rsrv[0:0] - attribute \src "libresoc.v:115268.3-115280.6" + attribute \src "libresoc.v:115344.3-115356.6" wire $0\dec31_dec_sub4_sgl_pipe[0:0] - attribute \src "libresoc.v:115242.3-115254.6" + attribute \src "libresoc.v:115318.3-115330.6" wire $0\dec31_dec_sub4_sgn[0:0] - attribute \src "libresoc.v:115190.3-115202.6" + attribute \src "libresoc.v:115266.3-115278.6" wire $0\dec31_dec_sub4_sgn_ext[0:0] - attribute \src "libresoc.v:115034.3-115046.6" + attribute \src "libresoc.v:115110.3-115122.6" wire width 3 $0\dec31_dec_sub4_sv_cr_in[2:0] - attribute \src "libresoc.v:115047.3-115059.6" + attribute \src "libresoc.v:115123.3-115135.6" wire width 3 $0\dec31_dec_sub4_sv_cr_out[2:0] - attribute \src "libresoc.v:114969.3-114981.6" + attribute \src "libresoc.v:115045.3-115057.6" wire width 3 $0\dec31_dec_sub4_sv_in1[2:0] - attribute \src "libresoc.v:114982.3-114994.6" + attribute \src "libresoc.v:115058.3-115070.6" wire width 3 $0\dec31_dec_sub4_sv_in2[2:0] - attribute \src "libresoc.v:114995.3-115007.6" + attribute \src "libresoc.v:115071.3-115083.6" wire width 3 $0\dec31_dec_sub4_sv_in3[2:0] - attribute \src "libresoc.v:115021.3-115033.6" + attribute \src "libresoc.v:115097.3-115109.6" wire width 3 $0\dec31_dec_sub4_sv_out2[2:0] - attribute \src "libresoc.v:115008.3-115020.6" + attribute \src "libresoc.v:115084.3-115096.6" wire width 3 $0\dec31_dec_sub4_sv_out[2:0] - attribute \src "libresoc.v:115086.3-115098.6" + attribute \src "libresoc.v:115162.3-115174.6" wire width 2 $0\dec31_dec_sub4_upd[1:0] - attribute \src "libresoc.v:114582.7-114582.20" + attribute \src "libresoc.v:114658.7-114658.20" wire $0\initial[0:0] - attribute \src "libresoc.v:115281.3-115293.6" + attribute \src "libresoc.v:115357.3-115369.6" wire width 2 $1\dec31_dec_sub4_SV_Etype[1:0] - attribute \src "libresoc.v:115294.3-115306.6" + attribute \src "libresoc.v:115370.3-115382.6" wire width 2 $1\dec31_dec_sub4_SV_Ptype[1:0] - attribute \src "libresoc.v:115125.3-115137.6" + attribute \src "libresoc.v:115201.3-115213.6" wire width 8 $1\dec31_dec_sub4_asmcode[7:0] - attribute \src "libresoc.v:115177.3-115189.6" + attribute \src "libresoc.v:115253.3-115265.6" wire $1\dec31_dec_sub4_br[0:0] - attribute \src "libresoc.v:114943.3-114955.6" + attribute \src "libresoc.v:115019.3-115031.6" wire width 3 $1\dec31_dec_sub4_cr_in[2:0] - attribute \src "libresoc.v:114956.3-114968.6" + attribute \src "libresoc.v:115032.3-115044.6" wire width 3 $1\dec31_dec_sub4_cr_out[2:0] - attribute \src "libresoc.v:115112.3-115124.6" + attribute \src "libresoc.v:115188.3-115200.6" wire width 2 $1\dec31_dec_sub4_cry_in[1:0] - attribute \src "libresoc.v:115164.3-115176.6" + attribute \src "libresoc.v:115240.3-115252.6" wire $1\dec31_dec_sub4_cry_out[0:0] - attribute \src "libresoc.v:115216.3-115228.6" + attribute \src "libresoc.v:115292.3-115304.6" wire width 5 $1\dec31_dec_sub4_form[4:0] - attribute \src "libresoc.v:114930.3-114942.6" + attribute \src "libresoc.v:115006.3-115018.6" wire width 14 $1\dec31_dec_sub4_function_unit[13:0] - attribute \src "libresoc.v:115307.3-115319.6" + attribute \src "libresoc.v:115383.3-115395.6" wire width 3 $1\dec31_dec_sub4_in1_sel[2:0] - attribute \src "libresoc.v:115320.3-115332.6" + attribute \src "libresoc.v:115396.3-115408.6" wire width 4 $1\dec31_dec_sub4_in2_sel[3:0] - attribute \src "libresoc.v:115333.3-115345.6" + attribute \src "libresoc.v:115409.3-115421.6" wire width 2 $1\dec31_dec_sub4_in3_sel[1:0] - attribute \src "libresoc.v:115073.3-115085.6" + attribute \src "libresoc.v:115149.3-115161.6" wire width 7 $1\dec31_dec_sub4_internal_op[6:0] - attribute \src "libresoc.v:115138.3-115150.6" + attribute \src "libresoc.v:115214.3-115226.6" wire $1\dec31_dec_sub4_inv_a[0:0] - attribute \src "libresoc.v:115151.3-115163.6" + attribute \src "libresoc.v:115227.3-115239.6" wire $1\dec31_dec_sub4_inv_out[0:0] - attribute \src "libresoc.v:115229.3-115241.6" + attribute \src "libresoc.v:115305.3-115317.6" wire $1\dec31_dec_sub4_is_32b[0:0] - attribute \src "libresoc.v:115060.3-115072.6" + attribute \src "libresoc.v:115136.3-115148.6" wire width 4 $1\dec31_dec_sub4_ldst_len[3:0] - attribute \src "libresoc.v:115255.3-115267.6" + attribute \src "libresoc.v:115331.3-115343.6" wire $1\dec31_dec_sub4_lk[0:0] - attribute \src "libresoc.v:115346.3-115358.6" + attribute \src "libresoc.v:115422.3-115434.6" wire width 3 $1\dec31_dec_sub4_out_sel[2:0] - attribute \src "libresoc.v:115099.3-115111.6" + attribute \src "libresoc.v:115175.3-115187.6" wire width 2 $1\dec31_dec_sub4_rc_sel[1:0] - attribute \src "libresoc.v:115203.3-115215.6" + attribute \src "libresoc.v:115279.3-115291.6" wire $1\dec31_dec_sub4_rsrv[0:0] - attribute \src "libresoc.v:115268.3-115280.6" + attribute \src "libresoc.v:115344.3-115356.6" wire $1\dec31_dec_sub4_sgl_pipe[0:0] - attribute \src "libresoc.v:115242.3-115254.6" + attribute \src "libresoc.v:115318.3-115330.6" wire $1\dec31_dec_sub4_sgn[0:0] - attribute \src "libresoc.v:115190.3-115202.6" + attribute \src "libresoc.v:115266.3-115278.6" wire $1\dec31_dec_sub4_sgn_ext[0:0] - attribute \src "libresoc.v:115034.3-115046.6" + attribute \src "libresoc.v:115110.3-115122.6" wire width 3 $1\dec31_dec_sub4_sv_cr_in[2:0] - attribute \src "libresoc.v:115047.3-115059.6" + attribute \src "libresoc.v:115123.3-115135.6" wire width 3 $1\dec31_dec_sub4_sv_cr_out[2:0] - attribute \src "libresoc.v:114969.3-114981.6" + attribute \src "libresoc.v:115045.3-115057.6" wire width 3 $1\dec31_dec_sub4_sv_in1[2:0] - attribute \src "libresoc.v:114982.3-114994.6" + attribute \src "libresoc.v:115058.3-115070.6" wire width 3 $1\dec31_dec_sub4_sv_in2[2:0] - attribute \src "libresoc.v:114995.3-115007.6" + attribute \src "libresoc.v:115071.3-115083.6" wire width 3 $1\dec31_dec_sub4_sv_in3[2:0] - attribute \src "libresoc.v:115021.3-115033.6" + attribute \src "libresoc.v:115097.3-115109.6" wire width 3 $1\dec31_dec_sub4_sv_out2[2:0] - attribute \src "libresoc.v:115008.3-115020.6" + attribute \src "libresoc.v:115084.3-115096.6" wire width 3 $1\dec31_dec_sub4_sv_out[2:0] - attribute \src "libresoc.v:115086.3-115098.6" + attribute \src "libresoc.v:115162.3-115174.6" wire width 2 $1\dec31_dec_sub4_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -178762,28 +178825,28 @@ module \dec31_dec_sub4 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub4_upd - attribute \src "libresoc.v:114582.7-114582.15" + attribute \src "libresoc.v:114658.7-114658.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:114582.7-114582.20" - process $proc$libresoc.v:114582$4394 + attribute \src "libresoc.v:114658.7-114658.20" + process $proc$libresoc.v:114658$4394 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:114930.3-114942.6" - process $proc$libresoc.v:114930$4361 + attribute \src "libresoc.v:115006.3-115018.6" + process $proc$libresoc.v:115006$4361 assign { } { } assign { } { } assign $0\dec31_dec_sub4_function_unit[13:0] $1\dec31_dec_sub4_function_unit[13:0] - attribute \src "libresoc.v:114931.5-114931.29" + attribute \src "libresoc.v:115007.5-115007.29" switch \initial - attribute \src "libresoc.v:114931.9-114931.17" + attribute \src "libresoc.v:115007.9-115007.17" case 1'1 case end @@ -178803,14 +178866,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_function_unit $0\dec31_dec_sub4_function_unit[13:0] end - attribute \src "libresoc.v:114943.3-114955.6" - process $proc$libresoc.v:114943$4362 + attribute \src "libresoc.v:115019.3-115031.6" + process $proc$libresoc.v:115019$4362 assign { } { } assign { } { } assign $0\dec31_dec_sub4_cr_in[2:0] $1\dec31_dec_sub4_cr_in[2:0] - attribute \src "libresoc.v:114944.5-114944.29" + attribute \src "libresoc.v:115020.5-115020.29" switch \initial - attribute \src "libresoc.v:114944.9-114944.17" + attribute \src "libresoc.v:115020.9-115020.17" case 1'1 case end @@ -178830,14 +178893,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_cr_in $0\dec31_dec_sub4_cr_in[2:0] end - attribute \src "libresoc.v:114956.3-114968.6" - process $proc$libresoc.v:114956$4363 + attribute \src "libresoc.v:115032.3-115044.6" + process $proc$libresoc.v:115032$4363 assign { } { } assign { } { } assign $0\dec31_dec_sub4_cr_out[2:0] $1\dec31_dec_sub4_cr_out[2:0] - attribute \src "libresoc.v:114957.5-114957.29" + attribute \src "libresoc.v:115033.5-115033.29" switch \initial - attribute \src "libresoc.v:114957.9-114957.17" + attribute \src "libresoc.v:115033.9-115033.17" case 1'1 case end @@ -178857,14 +178920,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_cr_out $0\dec31_dec_sub4_cr_out[2:0] end - attribute \src "libresoc.v:114969.3-114981.6" - process $proc$libresoc.v:114969$4364 + attribute \src "libresoc.v:115045.3-115057.6" + process $proc$libresoc.v:115045$4364 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_in1[2:0] $1\dec31_dec_sub4_sv_in1[2:0] - attribute \src "libresoc.v:114970.5-114970.29" + attribute \src "libresoc.v:115046.5-115046.29" switch \initial - attribute \src "libresoc.v:114970.9-114970.17" + attribute \src "libresoc.v:115046.9-115046.17" case 1'1 case end @@ -178884,14 +178947,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_in1 $0\dec31_dec_sub4_sv_in1[2:0] end - attribute \src "libresoc.v:114982.3-114994.6" - process $proc$libresoc.v:114982$4365 + attribute \src "libresoc.v:115058.3-115070.6" + process $proc$libresoc.v:115058$4365 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_in2[2:0] $1\dec31_dec_sub4_sv_in2[2:0] - attribute \src "libresoc.v:114983.5-114983.29" + attribute \src "libresoc.v:115059.5-115059.29" switch \initial - attribute \src "libresoc.v:114983.9-114983.17" + attribute \src "libresoc.v:115059.9-115059.17" case 1'1 case end @@ -178911,14 +178974,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_in2 $0\dec31_dec_sub4_sv_in2[2:0] end - attribute \src "libresoc.v:114995.3-115007.6" - process $proc$libresoc.v:114995$4366 + attribute \src "libresoc.v:115071.3-115083.6" + process $proc$libresoc.v:115071$4366 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_in3[2:0] $1\dec31_dec_sub4_sv_in3[2:0] - attribute \src "libresoc.v:114996.5-114996.29" + attribute \src "libresoc.v:115072.5-115072.29" switch \initial - attribute \src "libresoc.v:114996.9-114996.17" + attribute \src "libresoc.v:115072.9-115072.17" case 1'1 case end @@ -178938,14 +179001,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_in3 $0\dec31_dec_sub4_sv_in3[2:0] end - attribute \src "libresoc.v:115008.3-115020.6" - process $proc$libresoc.v:115008$4367 + attribute \src "libresoc.v:115084.3-115096.6" + process $proc$libresoc.v:115084$4367 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_out[2:0] $1\dec31_dec_sub4_sv_out[2:0] - attribute \src "libresoc.v:115009.5-115009.29" + attribute \src "libresoc.v:115085.5-115085.29" switch \initial - attribute \src "libresoc.v:115009.9-115009.17" + attribute \src "libresoc.v:115085.9-115085.17" case 1'1 case end @@ -178965,14 +179028,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_out $0\dec31_dec_sub4_sv_out[2:0] end - attribute \src "libresoc.v:115021.3-115033.6" - process $proc$libresoc.v:115021$4368 + attribute \src "libresoc.v:115097.3-115109.6" + process $proc$libresoc.v:115097$4368 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_out2[2:0] $1\dec31_dec_sub4_sv_out2[2:0] - attribute \src "libresoc.v:115022.5-115022.29" + attribute \src "libresoc.v:115098.5-115098.29" switch \initial - attribute \src "libresoc.v:115022.9-115022.17" + attribute \src "libresoc.v:115098.9-115098.17" case 1'1 case end @@ -178992,14 +179055,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_out2 $0\dec31_dec_sub4_sv_out2[2:0] end - attribute \src "libresoc.v:115034.3-115046.6" - process $proc$libresoc.v:115034$4369 + attribute \src "libresoc.v:115110.3-115122.6" + process $proc$libresoc.v:115110$4369 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_cr_in[2:0] $1\dec31_dec_sub4_sv_cr_in[2:0] - attribute \src "libresoc.v:115035.5-115035.29" + attribute \src "libresoc.v:115111.5-115111.29" switch \initial - attribute \src "libresoc.v:115035.9-115035.17" + attribute \src "libresoc.v:115111.9-115111.17" case 1'1 case end @@ -179019,14 +179082,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_cr_in $0\dec31_dec_sub4_sv_cr_in[2:0] end - attribute \src "libresoc.v:115047.3-115059.6" - process $proc$libresoc.v:115047$4370 + attribute \src "libresoc.v:115123.3-115135.6" + process $proc$libresoc.v:115123$4370 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sv_cr_out[2:0] $1\dec31_dec_sub4_sv_cr_out[2:0] - attribute \src "libresoc.v:115048.5-115048.29" + attribute \src "libresoc.v:115124.5-115124.29" switch \initial - attribute \src "libresoc.v:115048.9-115048.17" + attribute \src "libresoc.v:115124.9-115124.17" case 1'1 case end @@ -179046,14 +179109,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sv_cr_out $0\dec31_dec_sub4_sv_cr_out[2:0] end - attribute \src "libresoc.v:115060.3-115072.6" - process $proc$libresoc.v:115060$4371 + attribute \src "libresoc.v:115136.3-115148.6" + process $proc$libresoc.v:115136$4371 assign { } { } assign { } { } assign $0\dec31_dec_sub4_ldst_len[3:0] $1\dec31_dec_sub4_ldst_len[3:0] - attribute \src "libresoc.v:115061.5-115061.29" + attribute \src "libresoc.v:115137.5-115137.29" switch \initial - attribute \src "libresoc.v:115061.9-115061.17" + attribute \src "libresoc.v:115137.9-115137.17" case 1'1 case end @@ -179073,14 +179136,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_ldst_len $0\dec31_dec_sub4_ldst_len[3:0] end - attribute \src "libresoc.v:115073.3-115085.6" - process $proc$libresoc.v:115073$4372 + attribute \src "libresoc.v:115149.3-115161.6" + process $proc$libresoc.v:115149$4372 assign { } { } assign { } { } assign $0\dec31_dec_sub4_internal_op[6:0] $1\dec31_dec_sub4_internal_op[6:0] - attribute \src "libresoc.v:115074.5-115074.29" + attribute \src "libresoc.v:115150.5-115150.29" switch \initial - attribute \src "libresoc.v:115074.9-115074.17" + attribute \src "libresoc.v:115150.9-115150.17" case 1'1 case end @@ -179100,14 +179163,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_internal_op $0\dec31_dec_sub4_internal_op[6:0] end - attribute \src "libresoc.v:115086.3-115098.6" - process $proc$libresoc.v:115086$4373 + attribute \src "libresoc.v:115162.3-115174.6" + process $proc$libresoc.v:115162$4373 assign { } { } assign { } { } assign $0\dec31_dec_sub4_upd[1:0] $1\dec31_dec_sub4_upd[1:0] - attribute \src "libresoc.v:115087.5-115087.29" + attribute \src "libresoc.v:115163.5-115163.29" switch \initial - attribute \src "libresoc.v:115087.9-115087.17" + attribute \src "libresoc.v:115163.9-115163.17" case 1'1 case end @@ -179127,14 +179190,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_upd $0\dec31_dec_sub4_upd[1:0] end - attribute \src "libresoc.v:115099.3-115111.6" - process $proc$libresoc.v:115099$4374 + attribute \src "libresoc.v:115175.3-115187.6" + process $proc$libresoc.v:115175$4374 assign { } { } assign { } { } assign $0\dec31_dec_sub4_rc_sel[1:0] $1\dec31_dec_sub4_rc_sel[1:0] - attribute \src "libresoc.v:115100.5-115100.29" + attribute \src "libresoc.v:115176.5-115176.29" switch \initial - attribute \src "libresoc.v:115100.9-115100.17" + attribute \src "libresoc.v:115176.9-115176.17" case 1'1 case end @@ -179154,14 +179217,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_rc_sel $0\dec31_dec_sub4_rc_sel[1:0] end - attribute \src "libresoc.v:115112.3-115124.6" - process $proc$libresoc.v:115112$4375 + attribute \src "libresoc.v:115188.3-115200.6" + process $proc$libresoc.v:115188$4375 assign { } { } assign { } { } assign $0\dec31_dec_sub4_cry_in[1:0] $1\dec31_dec_sub4_cry_in[1:0] - attribute \src "libresoc.v:115113.5-115113.29" + attribute \src "libresoc.v:115189.5-115189.29" switch \initial - attribute \src "libresoc.v:115113.9-115113.17" + attribute \src "libresoc.v:115189.9-115189.17" case 1'1 case end @@ -179181,14 +179244,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_cry_in $0\dec31_dec_sub4_cry_in[1:0] end - attribute \src "libresoc.v:115125.3-115137.6" - process $proc$libresoc.v:115125$4376 + attribute \src "libresoc.v:115201.3-115213.6" + process $proc$libresoc.v:115201$4376 assign { } { } assign { } { } assign $0\dec31_dec_sub4_asmcode[7:0] $1\dec31_dec_sub4_asmcode[7:0] - attribute \src "libresoc.v:115126.5-115126.29" + attribute \src "libresoc.v:115202.5-115202.29" switch \initial - attribute \src "libresoc.v:115126.9-115126.17" + attribute \src "libresoc.v:115202.9-115202.17" case 1'1 case end @@ -179208,14 +179271,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_asmcode $0\dec31_dec_sub4_asmcode[7:0] end - attribute \src "libresoc.v:115138.3-115150.6" - process $proc$libresoc.v:115138$4377 + attribute \src "libresoc.v:115214.3-115226.6" + process $proc$libresoc.v:115214$4377 assign { } { } assign { } { } assign $0\dec31_dec_sub4_inv_a[0:0] $1\dec31_dec_sub4_inv_a[0:0] - attribute \src "libresoc.v:115139.5-115139.29" + attribute \src "libresoc.v:115215.5-115215.29" switch \initial - attribute \src "libresoc.v:115139.9-115139.17" + attribute \src "libresoc.v:115215.9-115215.17" case 1'1 case end @@ -179235,14 +179298,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_inv_a $0\dec31_dec_sub4_inv_a[0:0] end - attribute \src "libresoc.v:115151.3-115163.6" - process $proc$libresoc.v:115151$4378 + attribute \src "libresoc.v:115227.3-115239.6" + process $proc$libresoc.v:115227$4378 assign { } { } assign { } { } assign $0\dec31_dec_sub4_inv_out[0:0] $1\dec31_dec_sub4_inv_out[0:0] - attribute \src "libresoc.v:115152.5-115152.29" + attribute \src "libresoc.v:115228.5-115228.29" switch \initial - attribute \src "libresoc.v:115152.9-115152.17" + attribute \src "libresoc.v:115228.9-115228.17" case 1'1 case end @@ -179262,14 +179325,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_inv_out $0\dec31_dec_sub4_inv_out[0:0] end - attribute \src "libresoc.v:115164.3-115176.6" - process $proc$libresoc.v:115164$4379 + attribute \src "libresoc.v:115240.3-115252.6" + process $proc$libresoc.v:115240$4379 assign { } { } assign { } { } assign $0\dec31_dec_sub4_cry_out[0:0] $1\dec31_dec_sub4_cry_out[0:0] - attribute \src "libresoc.v:115165.5-115165.29" + attribute \src "libresoc.v:115241.5-115241.29" switch \initial - attribute \src "libresoc.v:115165.9-115165.17" + attribute \src "libresoc.v:115241.9-115241.17" case 1'1 case end @@ -179289,14 +179352,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_cry_out $0\dec31_dec_sub4_cry_out[0:0] end - attribute \src "libresoc.v:115177.3-115189.6" - process $proc$libresoc.v:115177$4380 + attribute \src "libresoc.v:115253.3-115265.6" + process $proc$libresoc.v:115253$4380 assign { } { } assign { } { } assign $0\dec31_dec_sub4_br[0:0] $1\dec31_dec_sub4_br[0:0] - attribute \src "libresoc.v:115178.5-115178.29" + attribute \src "libresoc.v:115254.5-115254.29" switch \initial - attribute \src "libresoc.v:115178.9-115178.17" + attribute \src "libresoc.v:115254.9-115254.17" case 1'1 case end @@ -179316,14 +179379,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_br $0\dec31_dec_sub4_br[0:0] end - attribute \src "libresoc.v:115190.3-115202.6" - process $proc$libresoc.v:115190$4381 + attribute \src "libresoc.v:115266.3-115278.6" + process $proc$libresoc.v:115266$4381 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sgn_ext[0:0] $1\dec31_dec_sub4_sgn_ext[0:0] - attribute \src "libresoc.v:115191.5-115191.29" + attribute \src "libresoc.v:115267.5-115267.29" switch \initial - attribute \src "libresoc.v:115191.9-115191.17" + attribute \src "libresoc.v:115267.9-115267.17" case 1'1 case end @@ -179343,14 +179406,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sgn_ext $0\dec31_dec_sub4_sgn_ext[0:0] end - attribute \src "libresoc.v:115203.3-115215.6" - process $proc$libresoc.v:115203$4382 + attribute \src "libresoc.v:115279.3-115291.6" + process $proc$libresoc.v:115279$4382 assign { } { } assign { } { } assign $0\dec31_dec_sub4_rsrv[0:0] $1\dec31_dec_sub4_rsrv[0:0] - attribute \src "libresoc.v:115204.5-115204.29" + attribute \src "libresoc.v:115280.5-115280.29" switch \initial - attribute \src "libresoc.v:115204.9-115204.17" + attribute \src "libresoc.v:115280.9-115280.17" case 1'1 case end @@ -179370,14 +179433,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_rsrv $0\dec31_dec_sub4_rsrv[0:0] end - attribute \src "libresoc.v:115216.3-115228.6" - process $proc$libresoc.v:115216$4383 + attribute \src "libresoc.v:115292.3-115304.6" + process $proc$libresoc.v:115292$4383 assign { } { } assign { } { } assign $0\dec31_dec_sub4_form[4:0] $1\dec31_dec_sub4_form[4:0] - attribute \src "libresoc.v:115217.5-115217.29" + attribute \src "libresoc.v:115293.5-115293.29" switch \initial - attribute \src "libresoc.v:115217.9-115217.17" + attribute \src "libresoc.v:115293.9-115293.17" case 1'1 case end @@ -179397,14 +179460,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_form $0\dec31_dec_sub4_form[4:0] end - attribute \src "libresoc.v:115229.3-115241.6" - process $proc$libresoc.v:115229$4384 + attribute \src "libresoc.v:115305.3-115317.6" + process $proc$libresoc.v:115305$4384 assign { } { } assign { } { } assign $0\dec31_dec_sub4_is_32b[0:0] $1\dec31_dec_sub4_is_32b[0:0] - attribute \src "libresoc.v:115230.5-115230.29" + attribute \src "libresoc.v:115306.5-115306.29" switch \initial - attribute \src "libresoc.v:115230.9-115230.17" + attribute \src "libresoc.v:115306.9-115306.17" case 1'1 case end @@ -179424,14 +179487,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_is_32b $0\dec31_dec_sub4_is_32b[0:0] end - attribute \src "libresoc.v:115242.3-115254.6" - process $proc$libresoc.v:115242$4385 + attribute \src "libresoc.v:115318.3-115330.6" + process $proc$libresoc.v:115318$4385 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sgn[0:0] $1\dec31_dec_sub4_sgn[0:0] - attribute \src "libresoc.v:115243.5-115243.29" + attribute \src "libresoc.v:115319.5-115319.29" switch \initial - attribute \src "libresoc.v:115243.9-115243.17" + attribute \src "libresoc.v:115319.9-115319.17" case 1'1 case end @@ -179451,14 +179514,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sgn $0\dec31_dec_sub4_sgn[0:0] end - attribute \src "libresoc.v:115255.3-115267.6" - process $proc$libresoc.v:115255$4386 + attribute \src "libresoc.v:115331.3-115343.6" + process $proc$libresoc.v:115331$4386 assign { } { } assign { } { } assign $0\dec31_dec_sub4_lk[0:0] $1\dec31_dec_sub4_lk[0:0] - attribute \src "libresoc.v:115256.5-115256.29" + attribute \src "libresoc.v:115332.5-115332.29" switch \initial - attribute \src "libresoc.v:115256.9-115256.17" + attribute \src "libresoc.v:115332.9-115332.17" case 1'1 case end @@ -179478,14 +179541,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_lk $0\dec31_dec_sub4_lk[0:0] end - attribute \src "libresoc.v:115268.3-115280.6" - process $proc$libresoc.v:115268$4387 + attribute \src "libresoc.v:115344.3-115356.6" + process $proc$libresoc.v:115344$4387 assign { } { } assign { } { } assign $0\dec31_dec_sub4_sgl_pipe[0:0] $1\dec31_dec_sub4_sgl_pipe[0:0] - attribute \src "libresoc.v:115269.5-115269.29" + attribute \src "libresoc.v:115345.5-115345.29" switch \initial - attribute \src "libresoc.v:115269.9-115269.17" + attribute \src "libresoc.v:115345.9-115345.17" case 1'1 case end @@ -179505,14 +179568,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_sgl_pipe $0\dec31_dec_sub4_sgl_pipe[0:0] end - attribute \src "libresoc.v:115281.3-115293.6" - process $proc$libresoc.v:115281$4388 + attribute \src "libresoc.v:115357.3-115369.6" + process $proc$libresoc.v:115357$4388 assign { } { } assign { } { } assign $0\dec31_dec_sub4_SV_Etype[1:0] $1\dec31_dec_sub4_SV_Etype[1:0] - attribute \src "libresoc.v:115282.5-115282.29" + attribute \src "libresoc.v:115358.5-115358.29" switch \initial - attribute \src "libresoc.v:115282.9-115282.17" + attribute \src "libresoc.v:115358.9-115358.17" case 1'1 case end @@ -179532,14 +179595,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_SV_Etype $0\dec31_dec_sub4_SV_Etype[1:0] end - attribute \src "libresoc.v:115294.3-115306.6" - process $proc$libresoc.v:115294$4389 + attribute \src "libresoc.v:115370.3-115382.6" + process $proc$libresoc.v:115370$4389 assign { } { } assign { } { } assign $0\dec31_dec_sub4_SV_Ptype[1:0] $1\dec31_dec_sub4_SV_Ptype[1:0] - attribute \src "libresoc.v:115295.5-115295.29" + attribute \src "libresoc.v:115371.5-115371.29" switch \initial - attribute \src "libresoc.v:115295.9-115295.17" + attribute \src "libresoc.v:115371.9-115371.17" case 1'1 case end @@ -179559,14 +179622,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_SV_Ptype $0\dec31_dec_sub4_SV_Ptype[1:0] end - attribute \src "libresoc.v:115307.3-115319.6" - process $proc$libresoc.v:115307$4390 + attribute \src "libresoc.v:115383.3-115395.6" + process $proc$libresoc.v:115383$4390 assign { } { } assign { } { } assign $0\dec31_dec_sub4_in1_sel[2:0] $1\dec31_dec_sub4_in1_sel[2:0] - attribute \src "libresoc.v:115308.5-115308.29" + attribute \src "libresoc.v:115384.5-115384.29" switch \initial - attribute \src "libresoc.v:115308.9-115308.17" + attribute \src "libresoc.v:115384.9-115384.17" case 1'1 case end @@ -179586,14 +179649,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_in1_sel $0\dec31_dec_sub4_in1_sel[2:0] end - attribute \src "libresoc.v:115320.3-115332.6" - process $proc$libresoc.v:115320$4391 + attribute \src "libresoc.v:115396.3-115408.6" + process $proc$libresoc.v:115396$4391 assign { } { } assign { } { } assign $0\dec31_dec_sub4_in2_sel[3:0] $1\dec31_dec_sub4_in2_sel[3:0] - attribute \src "libresoc.v:115321.5-115321.29" + attribute \src "libresoc.v:115397.5-115397.29" switch \initial - attribute \src "libresoc.v:115321.9-115321.17" + attribute \src "libresoc.v:115397.9-115397.17" case 1'1 case end @@ -179613,14 +179676,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_in2_sel $0\dec31_dec_sub4_in2_sel[3:0] end - attribute \src "libresoc.v:115333.3-115345.6" - process $proc$libresoc.v:115333$4392 + attribute \src "libresoc.v:115409.3-115421.6" + process $proc$libresoc.v:115409$4392 assign { } { } assign { } { } assign $0\dec31_dec_sub4_in3_sel[1:0] $1\dec31_dec_sub4_in3_sel[1:0] - attribute \src "libresoc.v:115334.5-115334.29" + attribute \src "libresoc.v:115410.5-115410.29" switch \initial - attribute \src "libresoc.v:115334.9-115334.17" + attribute \src "libresoc.v:115410.9-115410.17" case 1'1 case end @@ -179640,14 +179703,14 @@ module \dec31_dec_sub4 sync always update \dec31_dec_sub4_in3_sel $0\dec31_dec_sub4_in3_sel[1:0] end - attribute \src "libresoc.v:115346.3-115358.6" - process $proc$libresoc.v:115346$4393 + attribute \src "libresoc.v:115422.3-115434.6" + process $proc$libresoc.v:115422$4393 assign { } { } assign { } { } assign $0\dec31_dec_sub4_out_sel[2:0] $1\dec31_dec_sub4_out_sel[2:0] - attribute \src "libresoc.v:115347.5-115347.29" + attribute \src "libresoc.v:115423.5-115423.29" switch \initial - attribute \src "libresoc.v:115347.9-115347.17" + attribute \src "libresoc.v:115423.9-115423.17" case 1'1 case end @@ -179669,144 +179732,144 @@ module \dec31_dec_sub4 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:115364.1-117133.10" +attribute \src "libresoc.v:115440.1-117209.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub8" attribute \generator "nMigen" module \dec31_dec_sub8 - attribute \src "libresoc.v:116874.3-116916.6" + attribute \src "libresoc.v:116950.3-116992.6" wire width 2 $0\dec31_dec_sub8_SV_Etype[1:0] - attribute \src "libresoc.v:116917.3-116959.6" + attribute \src "libresoc.v:116993.3-117035.6" wire width 2 $0\dec31_dec_sub8_SV_Ptype[1:0] - attribute \src "libresoc.v:116358.3-116400.6" + attribute \src "libresoc.v:116434.3-116476.6" wire width 8 $0\dec31_dec_sub8_asmcode[7:0] - attribute \src "libresoc.v:116530.3-116572.6" + attribute \src "libresoc.v:116606.3-116648.6" wire $0\dec31_dec_sub8_br[0:0] - attribute \src "libresoc.v:115756.3-115798.6" + attribute \src "libresoc.v:115832.3-115874.6" wire width 3 $0\dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:115799.3-115841.6" + attribute \src "libresoc.v:115875.3-115917.6" wire width 3 $0\dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:116315.3-116357.6" + attribute \src "libresoc.v:116391.3-116433.6" wire width 2 $0\dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:116487.3-116529.6" + attribute \src "libresoc.v:116563.3-116605.6" wire $0\dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:116659.3-116701.6" + attribute \src "libresoc.v:116735.3-116777.6" wire width 5 $0\dec31_dec_sub8_form[4:0] - attribute \src "libresoc.v:115713.3-115755.6" + attribute \src "libresoc.v:115789.3-115831.6" wire width 14 $0\dec31_dec_sub8_function_unit[13:0] - attribute \src "libresoc.v:116960.3-117002.6" + attribute \src "libresoc.v:117036.3-117078.6" wire width 3 $0\dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:117003.3-117045.6" + attribute \src "libresoc.v:117079.3-117121.6" wire width 4 $0\dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:117046.3-117088.6" + attribute \src "libresoc.v:117122.3-117164.6" wire width 2 $0\dec31_dec_sub8_in3_sel[1:0] - attribute \src "libresoc.v:116186.3-116228.6" + attribute \src "libresoc.v:116262.3-116304.6" wire width 7 $0\dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:116401.3-116443.6" + attribute \src "libresoc.v:116477.3-116519.6" wire $0\dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:116444.3-116486.6" + attribute \src "libresoc.v:116520.3-116562.6" wire $0\dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:116702.3-116744.6" + attribute \src "libresoc.v:116778.3-116820.6" wire $0\dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:116143.3-116185.6" + attribute \src "libresoc.v:116219.3-116261.6" wire width 4 $0\dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:116788.3-116830.6" + attribute \src "libresoc.v:116864.3-116906.6" wire $0\dec31_dec_sub8_lk[0:0] - attribute \src "libresoc.v:117089.3-117131.6" + attribute \src "libresoc.v:117165.3-117207.6" wire width 3 $0\dec31_dec_sub8_out_sel[2:0] - attribute \src "libresoc.v:116272.3-116314.6" + attribute \src "libresoc.v:116348.3-116390.6" wire width 2 $0\dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:116616.3-116658.6" + attribute \src "libresoc.v:116692.3-116734.6" wire $0\dec31_dec_sub8_rsrv[0:0] - attribute \src "libresoc.v:116831.3-116873.6" + attribute \src "libresoc.v:116907.3-116949.6" wire $0\dec31_dec_sub8_sgl_pipe[0:0] - attribute \src "libresoc.v:116745.3-116787.6" + attribute \src "libresoc.v:116821.3-116863.6" wire $0\dec31_dec_sub8_sgn[0:0] - attribute \src "libresoc.v:116573.3-116615.6" + attribute \src "libresoc.v:116649.3-116691.6" wire $0\dec31_dec_sub8_sgn_ext[0:0] - attribute \src "libresoc.v:116057.3-116099.6" + attribute \src "libresoc.v:116133.3-116175.6" wire width 3 $0\dec31_dec_sub8_sv_cr_in[2:0] - attribute \src "libresoc.v:116100.3-116142.6" + attribute \src "libresoc.v:116176.3-116218.6" wire width 3 $0\dec31_dec_sub8_sv_cr_out[2:0] - attribute \src "libresoc.v:115842.3-115884.6" + attribute \src "libresoc.v:115918.3-115960.6" wire width 3 $0\dec31_dec_sub8_sv_in1[2:0] - attribute \src "libresoc.v:115885.3-115927.6" + attribute \src "libresoc.v:115961.3-116003.6" wire width 3 $0\dec31_dec_sub8_sv_in2[2:0] - attribute \src "libresoc.v:115928.3-115970.6" + attribute \src "libresoc.v:116004.3-116046.6" wire width 3 $0\dec31_dec_sub8_sv_in3[2:0] - attribute \src "libresoc.v:116014.3-116056.6" + attribute \src "libresoc.v:116090.3-116132.6" wire width 3 $0\dec31_dec_sub8_sv_out2[2:0] - attribute \src "libresoc.v:115971.3-116013.6" + attribute \src "libresoc.v:116047.3-116089.6" wire width 3 $0\dec31_dec_sub8_sv_out[2:0] - attribute \src "libresoc.v:116229.3-116271.6" + attribute \src "libresoc.v:116305.3-116347.6" wire width 2 $0\dec31_dec_sub8_upd[1:0] - attribute \src "libresoc.v:115365.7-115365.20" + attribute \src "libresoc.v:115441.7-115441.20" wire $0\initial[0:0] - attribute \src "libresoc.v:116874.3-116916.6" + attribute \src "libresoc.v:116950.3-116992.6" wire width 2 $1\dec31_dec_sub8_SV_Etype[1:0] - attribute \src "libresoc.v:116917.3-116959.6" + attribute \src "libresoc.v:116993.3-117035.6" wire width 2 $1\dec31_dec_sub8_SV_Ptype[1:0] - attribute \src "libresoc.v:116358.3-116400.6" + attribute \src "libresoc.v:116434.3-116476.6" wire width 8 $1\dec31_dec_sub8_asmcode[7:0] - attribute \src "libresoc.v:116530.3-116572.6" + attribute \src "libresoc.v:116606.3-116648.6" wire $1\dec31_dec_sub8_br[0:0] - attribute \src "libresoc.v:115756.3-115798.6" + attribute \src "libresoc.v:115832.3-115874.6" wire width 3 $1\dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:115799.3-115841.6" + attribute \src "libresoc.v:115875.3-115917.6" wire width 3 $1\dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:116315.3-116357.6" + attribute \src "libresoc.v:116391.3-116433.6" wire width 2 $1\dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:116487.3-116529.6" + attribute \src "libresoc.v:116563.3-116605.6" wire $1\dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:116659.3-116701.6" + attribute \src "libresoc.v:116735.3-116777.6" wire width 5 $1\dec31_dec_sub8_form[4:0] - attribute \src "libresoc.v:115713.3-115755.6" + attribute \src "libresoc.v:115789.3-115831.6" wire width 14 $1\dec31_dec_sub8_function_unit[13:0] - attribute \src "libresoc.v:116960.3-117002.6" + attribute \src "libresoc.v:117036.3-117078.6" wire width 3 $1\dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:117003.3-117045.6" + attribute \src "libresoc.v:117079.3-117121.6" wire width 4 $1\dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:117046.3-117088.6" + attribute \src "libresoc.v:117122.3-117164.6" wire width 2 $1\dec31_dec_sub8_in3_sel[1:0] - attribute \src "libresoc.v:116186.3-116228.6" + attribute \src "libresoc.v:116262.3-116304.6" wire width 7 $1\dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:116401.3-116443.6" + attribute \src "libresoc.v:116477.3-116519.6" wire $1\dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:116444.3-116486.6" + attribute \src "libresoc.v:116520.3-116562.6" wire $1\dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:116702.3-116744.6" + attribute \src "libresoc.v:116778.3-116820.6" wire $1\dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:116143.3-116185.6" + attribute \src "libresoc.v:116219.3-116261.6" wire width 4 $1\dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:116788.3-116830.6" + attribute \src "libresoc.v:116864.3-116906.6" wire $1\dec31_dec_sub8_lk[0:0] - attribute \src "libresoc.v:117089.3-117131.6" + attribute \src "libresoc.v:117165.3-117207.6" wire width 3 $1\dec31_dec_sub8_out_sel[2:0] - attribute \src "libresoc.v:116272.3-116314.6" + attribute \src "libresoc.v:116348.3-116390.6" wire width 2 $1\dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:116616.3-116658.6" + attribute \src "libresoc.v:116692.3-116734.6" wire $1\dec31_dec_sub8_rsrv[0:0] - attribute \src "libresoc.v:116831.3-116873.6" + attribute \src "libresoc.v:116907.3-116949.6" wire $1\dec31_dec_sub8_sgl_pipe[0:0] - attribute \src "libresoc.v:116745.3-116787.6" + attribute \src "libresoc.v:116821.3-116863.6" wire $1\dec31_dec_sub8_sgn[0:0] - attribute \src "libresoc.v:116573.3-116615.6" + attribute \src "libresoc.v:116649.3-116691.6" wire $1\dec31_dec_sub8_sgn_ext[0:0] - attribute \src "libresoc.v:116057.3-116099.6" + attribute \src "libresoc.v:116133.3-116175.6" wire width 3 $1\dec31_dec_sub8_sv_cr_in[2:0] - attribute \src "libresoc.v:116100.3-116142.6" + attribute \src "libresoc.v:116176.3-116218.6" wire width 3 $1\dec31_dec_sub8_sv_cr_out[2:0] - attribute \src "libresoc.v:115842.3-115884.6" + attribute \src "libresoc.v:115918.3-115960.6" wire width 3 $1\dec31_dec_sub8_sv_in1[2:0] - attribute \src "libresoc.v:115885.3-115927.6" + attribute \src "libresoc.v:115961.3-116003.6" wire width 3 $1\dec31_dec_sub8_sv_in2[2:0] - attribute \src "libresoc.v:115928.3-115970.6" + attribute \src "libresoc.v:116004.3-116046.6" wire width 3 $1\dec31_dec_sub8_sv_in3[2:0] - attribute \src "libresoc.v:116014.3-116056.6" + attribute \src "libresoc.v:116090.3-116132.6" wire width 3 $1\dec31_dec_sub8_sv_out2[2:0] - attribute \src "libresoc.v:115971.3-116013.6" + attribute \src "libresoc.v:116047.3-116089.6" wire width 3 $1\dec31_dec_sub8_sv_out[2:0] - attribute \src "libresoc.v:116229.3-116271.6" + attribute \src "libresoc.v:116305.3-116347.6" wire width 2 $1\dec31_dec_sub8_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -180118,28 +180181,28 @@ module \dec31_dec_sub8 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub8_upd - attribute \src "libresoc.v:115365.7-115365.15" + attribute \src "libresoc.v:115441.7-115441.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:115365.7-115365.20" - process $proc$libresoc.v:115365$4428 + attribute \src "libresoc.v:115441.7-115441.20" + process $proc$libresoc.v:115441$4428 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:115713.3-115755.6" - process $proc$libresoc.v:115713$4395 + attribute \src "libresoc.v:115789.3-115831.6" + process $proc$libresoc.v:115789$4395 assign { } { } assign { } { } assign $0\dec31_dec_sub8_function_unit[13:0] $1\dec31_dec_sub8_function_unit[13:0] - attribute \src "libresoc.v:115714.5-115714.29" + attribute \src "libresoc.v:115790.5-115790.29" switch \initial - attribute \src "libresoc.v:115714.9-115714.17" + attribute \src "libresoc.v:115790.9-115790.17" case 1'1 case end @@ -180199,14 +180262,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_function_unit $0\dec31_dec_sub8_function_unit[13:0] end - attribute \src "libresoc.v:115756.3-115798.6" - process $proc$libresoc.v:115756$4396 + attribute \src "libresoc.v:115832.3-115874.6" + process $proc$libresoc.v:115832$4396 assign { } { } assign { } { } assign $0\dec31_dec_sub8_cr_in[2:0] $1\dec31_dec_sub8_cr_in[2:0] - attribute \src "libresoc.v:115757.5-115757.29" + attribute \src "libresoc.v:115833.5-115833.29" switch \initial - attribute \src "libresoc.v:115757.9-115757.17" + attribute \src "libresoc.v:115833.9-115833.17" case 1'1 case end @@ -180266,14 +180329,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_cr_in $0\dec31_dec_sub8_cr_in[2:0] end - attribute \src "libresoc.v:115799.3-115841.6" - process $proc$libresoc.v:115799$4397 + attribute \src "libresoc.v:115875.3-115917.6" + process $proc$libresoc.v:115875$4397 assign { } { } assign { } { } assign $0\dec31_dec_sub8_cr_out[2:0] $1\dec31_dec_sub8_cr_out[2:0] - attribute \src "libresoc.v:115800.5-115800.29" + attribute \src "libresoc.v:115876.5-115876.29" switch \initial - attribute \src "libresoc.v:115800.9-115800.17" + attribute \src "libresoc.v:115876.9-115876.17" case 1'1 case end @@ -180333,14 +180396,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_cr_out $0\dec31_dec_sub8_cr_out[2:0] end - attribute \src "libresoc.v:115842.3-115884.6" - process $proc$libresoc.v:115842$4398 + attribute \src "libresoc.v:115918.3-115960.6" + process $proc$libresoc.v:115918$4398 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_in1[2:0] $1\dec31_dec_sub8_sv_in1[2:0] - attribute \src "libresoc.v:115843.5-115843.29" + attribute \src "libresoc.v:115919.5-115919.29" switch \initial - attribute \src "libresoc.v:115843.9-115843.17" + attribute \src "libresoc.v:115919.9-115919.17" case 1'1 case end @@ -180400,14 +180463,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_in1 $0\dec31_dec_sub8_sv_in1[2:0] end - attribute \src "libresoc.v:115885.3-115927.6" - process $proc$libresoc.v:115885$4399 + attribute \src "libresoc.v:115961.3-116003.6" + process $proc$libresoc.v:115961$4399 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_in2[2:0] $1\dec31_dec_sub8_sv_in2[2:0] - attribute \src "libresoc.v:115886.5-115886.29" + attribute \src "libresoc.v:115962.5-115962.29" switch \initial - attribute \src "libresoc.v:115886.9-115886.17" + attribute \src "libresoc.v:115962.9-115962.17" case 1'1 case end @@ -180467,14 +180530,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_in2 $0\dec31_dec_sub8_sv_in2[2:0] end - attribute \src "libresoc.v:115928.3-115970.6" - process $proc$libresoc.v:115928$4400 + attribute \src "libresoc.v:116004.3-116046.6" + process $proc$libresoc.v:116004$4400 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_in3[2:0] $1\dec31_dec_sub8_sv_in3[2:0] - attribute \src "libresoc.v:115929.5-115929.29" + attribute \src "libresoc.v:116005.5-116005.29" switch \initial - attribute \src "libresoc.v:115929.9-115929.17" + attribute \src "libresoc.v:116005.9-116005.17" case 1'1 case end @@ -180534,14 +180597,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_in3 $0\dec31_dec_sub8_sv_in3[2:0] end - attribute \src "libresoc.v:115971.3-116013.6" - process $proc$libresoc.v:115971$4401 + attribute \src "libresoc.v:116047.3-116089.6" + process $proc$libresoc.v:116047$4401 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_out[2:0] $1\dec31_dec_sub8_sv_out[2:0] - attribute \src "libresoc.v:115972.5-115972.29" + attribute \src "libresoc.v:116048.5-116048.29" switch \initial - attribute \src "libresoc.v:115972.9-115972.17" + attribute \src "libresoc.v:116048.9-116048.17" case 1'1 case end @@ -180601,14 +180664,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_out $0\dec31_dec_sub8_sv_out[2:0] end - attribute \src "libresoc.v:116014.3-116056.6" - process $proc$libresoc.v:116014$4402 + attribute \src "libresoc.v:116090.3-116132.6" + process $proc$libresoc.v:116090$4402 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_out2[2:0] $1\dec31_dec_sub8_sv_out2[2:0] - attribute \src "libresoc.v:116015.5-116015.29" + attribute \src "libresoc.v:116091.5-116091.29" switch \initial - attribute \src "libresoc.v:116015.9-116015.17" + attribute \src "libresoc.v:116091.9-116091.17" case 1'1 case end @@ -180668,14 +180731,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_out2 $0\dec31_dec_sub8_sv_out2[2:0] end - attribute \src "libresoc.v:116057.3-116099.6" - process $proc$libresoc.v:116057$4403 + attribute \src "libresoc.v:116133.3-116175.6" + process $proc$libresoc.v:116133$4403 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_cr_in[2:0] $1\dec31_dec_sub8_sv_cr_in[2:0] - attribute \src "libresoc.v:116058.5-116058.29" + attribute \src "libresoc.v:116134.5-116134.29" switch \initial - attribute \src "libresoc.v:116058.9-116058.17" + attribute \src "libresoc.v:116134.9-116134.17" case 1'1 case end @@ -180735,14 +180798,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_cr_in $0\dec31_dec_sub8_sv_cr_in[2:0] end - attribute \src "libresoc.v:116100.3-116142.6" - process $proc$libresoc.v:116100$4404 + attribute \src "libresoc.v:116176.3-116218.6" + process $proc$libresoc.v:116176$4404 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sv_cr_out[2:0] $1\dec31_dec_sub8_sv_cr_out[2:0] - attribute \src "libresoc.v:116101.5-116101.29" + attribute \src "libresoc.v:116177.5-116177.29" switch \initial - attribute \src "libresoc.v:116101.9-116101.17" + attribute \src "libresoc.v:116177.9-116177.17" case 1'1 case end @@ -180802,14 +180865,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sv_cr_out $0\dec31_dec_sub8_sv_cr_out[2:0] end - attribute \src "libresoc.v:116143.3-116185.6" - process $proc$libresoc.v:116143$4405 + attribute \src "libresoc.v:116219.3-116261.6" + process $proc$libresoc.v:116219$4405 assign { } { } assign { } { } assign $0\dec31_dec_sub8_ldst_len[3:0] $1\dec31_dec_sub8_ldst_len[3:0] - attribute \src "libresoc.v:116144.5-116144.29" + attribute \src "libresoc.v:116220.5-116220.29" switch \initial - attribute \src "libresoc.v:116144.9-116144.17" + attribute \src "libresoc.v:116220.9-116220.17" case 1'1 case end @@ -180869,14 +180932,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_ldst_len $0\dec31_dec_sub8_ldst_len[3:0] end - attribute \src "libresoc.v:116186.3-116228.6" - process $proc$libresoc.v:116186$4406 + attribute \src "libresoc.v:116262.3-116304.6" + process $proc$libresoc.v:116262$4406 assign { } { } assign { } { } assign $0\dec31_dec_sub8_internal_op[6:0] $1\dec31_dec_sub8_internal_op[6:0] - attribute \src "libresoc.v:116187.5-116187.29" + attribute \src "libresoc.v:116263.5-116263.29" switch \initial - attribute \src "libresoc.v:116187.9-116187.17" + attribute \src "libresoc.v:116263.9-116263.17" case 1'1 case end @@ -180936,14 +180999,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_internal_op $0\dec31_dec_sub8_internal_op[6:0] end - attribute \src "libresoc.v:116229.3-116271.6" - process $proc$libresoc.v:116229$4407 + attribute \src "libresoc.v:116305.3-116347.6" + process $proc$libresoc.v:116305$4407 assign { } { } assign { } { } assign $0\dec31_dec_sub8_upd[1:0] $1\dec31_dec_sub8_upd[1:0] - attribute \src "libresoc.v:116230.5-116230.29" + attribute \src "libresoc.v:116306.5-116306.29" switch \initial - attribute \src "libresoc.v:116230.9-116230.17" + attribute \src "libresoc.v:116306.9-116306.17" case 1'1 case end @@ -181003,14 +181066,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_upd $0\dec31_dec_sub8_upd[1:0] end - attribute \src "libresoc.v:116272.3-116314.6" - process $proc$libresoc.v:116272$4408 + attribute \src "libresoc.v:116348.3-116390.6" + process $proc$libresoc.v:116348$4408 assign { } { } assign { } { } assign $0\dec31_dec_sub8_rc_sel[1:0] $1\dec31_dec_sub8_rc_sel[1:0] - attribute \src "libresoc.v:116273.5-116273.29" + attribute \src "libresoc.v:116349.5-116349.29" switch \initial - attribute \src "libresoc.v:116273.9-116273.17" + attribute \src "libresoc.v:116349.9-116349.17" case 1'1 case end @@ -181070,14 +181133,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_rc_sel $0\dec31_dec_sub8_rc_sel[1:0] end - attribute \src "libresoc.v:116315.3-116357.6" - process $proc$libresoc.v:116315$4409 + attribute \src "libresoc.v:116391.3-116433.6" + process $proc$libresoc.v:116391$4409 assign { } { } assign { } { } assign $0\dec31_dec_sub8_cry_in[1:0] $1\dec31_dec_sub8_cry_in[1:0] - attribute \src "libresoc.v:116316.5-116316.29" + attribute \src "libresoc.v:116392.5-116392.29" switch \initial - attribute \src "libresoc.v:116316.9-116316.17" + attribute \src "libresoc.v:116392.9-116392.17" case 1'1 case end @@ -181137,14 +181200,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_cry_in $0\dec31_dec_sub8_cry_in[1:0] end - attribute \src "libresoc.v:116358.3-116400.6" - process $proc$libresoc.v:116358$4410 + attribute \src "libresoc.v:116434.3-116476.6" + process $proc$libresoc.v:116434$4410 assign { } { } assign { } { } assign $0\dec31_dec_sub8_asmcode[7:0] $1\dec31_dec_sub8_asmcode[7:0] - attribute \src "libresoc.v:116359.5-116359.29" + attribute \src "libresoc.v:116435.5-116435.29" switch \initial - attribute \src "libresoc.v:116359.9-116359.17" + attribute \src "libresoc.v:116435.9-116435.17" case 1'1 case end @@ -181204,14 +181267,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_asmcode $0\dec31_dec_sub8_asmcode[7:0] end - attribute \src "libresoc.v:116401.3-116443.6" - process $proc$libresoc.v:116401$4411 + attribute \src "libresoc.v:116477.3-116519.6" + process $proc$libresoc.v:116477$4411 assign { } { } assign { } { } assign $0\dec31_dec_sub8_inv_a[0:0] $1\dec31_dec_sub8_inv_a[0:0] - attribute \src "libresoc.v:116402.5-116402.29" + attribute \src "libresoc.v:116478.5-116478.29" switch \initial - attribute \src "libresoc.v:116402.9-116402.17" + attribute \src "libresoc.v:116478.9-116478.17" case 1'1 case end @@ -181271,14 +181334,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_inv_a $0\dec31_dec_sub8_inv_a[0:0] end - attribute \src "libresoc.v:116444.3-116486.6" - process $proc$libresoc.v:116444$4412 + attribute \src "libresoc.v:116520.3-116562.6" + process $proc$libresoc.v:116520$4412 assign { } { } assign { } { } assign $0\dec31_dec_sub8_inv_out[0:0] $1\dec31_dec_sub8_inv_out[0:0] - attribute \src "libresoc.v:116445.5-116445.29" + attribute \src "libresoc.v:116521.5-116521.29" switch \initial - attribute \src "libresoc.v:116445.9-116445.17" + attribute \src "libresoc.v:116521.9-116521.17" case 1'1 case end @@ -181338,14 +181401,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_inv_out $0\dec31_dec_sub8_inv_out[0:0] end - attribute \src "libresoc.v:116487.3-116529.6" - process $proc$libresoc.v:116487$4413 + attribute \src "libresoc.v:116563.3-116605.6" + process $proc$libresoc.v:116563$4413 assign { } { } assign { } { } assign $0\dec31_dec_sub8_cry_out[0:0] $1\dec31_dec_sub8_cry_out[0:0] - attribute \src "libresoc.v:116488.5-116488.29" + attribute \src "libresoc.v:116564.5-116564.29" switch \initial - attribute \src "libresoc.v:116488.9-116488.17" + attribute \src "libresoc.v:116564.9-116564.17" case 1'1 case end @@ -181405,14 +181468,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_cry_out $0\dec31_dec_sub8_cry_out[0:0] end - attribute \src "libresoc.v:116530.3-116572.6" - process $proc$libresoc.v:116530$4414 + attribute \src "libresoc.v:116606.3-116648.6" + process $proc$libresoc.v:116606$4414 assign { } { } assign { } { } assign $0\dec31_dec_sub8_br[0:0] $1\dec31_dec_sub8_br[0:0] - attribute \src "libresoc.v:116531.5-116531.29" + attribute \src "libresoc.v:116607.5-116607.29" switch \initial - attribute \src "libresoc.v:116531.9-116531.17" + attribute \src "libresoc.v:116607.9-116607.17" case 1'1 case end @@ -181472,14 +181535,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_br $0\dec31_dec_sub8_br[0:0] end - attribute \src "libresoc.v:116573.3-116615.6" - process $proc$libresoc.v:116573$4415 + attribute \src "libresoc.v:116649.3-116691.6" + process $proc$libresoc.v:116649$4415 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sgn_ext[0:0] $1\dec31_dec_sub8_sgn_ext[0:0] - attribute \src "libresoc.v:116574.5-116574.29" + attribute \src "libresoc.v:116650.5-116650.29" switch \initial - attribute \src "libresoc.v:116574.9-116574.17" + attribute \src "libresoc.v:116650.9-116650.17" case 1'1 case end @@ -181539,14 +181602,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sgn_ext $0\dec31_dec_sub8_sgn_ext[0:0] end - attribute \src "libresoc.v:116616.3-116658.6" - process $proc$libresoc.v:116616$4416 + attribute \src "libresoc.v:116692.3-116734.6" + process $proc$libresoc.v:116692$4416 assign { } { } assign { } { } assign $0\dec31_dec_sub8_rsrv[0:0] $1\dec31_dec_sub8_rsrv[0:0] - attribute \src "libresoc.v:116617.5-116617.29" + attribute \src "libresoc.v:116693.5-116693.29" switch \initial - attribute \src "libresoc.v:116617.9-116617.17" + attribute \src "libresoc.v:116693.9-116693.17" case 1'1 case end @@ -181606,14 +181669,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_rsrv $0\dec31_dec_sub8_rsrv[0:0] end - attribute \src "libresoc.v:116659.3-116701.6" - process $proc$libresoc.v:116659$4417 + attribute \src "libresoc.v:116735.3-116777.6" + process $proc$libresoc.v:116735$4417 assign { } { } assign { } { } assign $0\dec31_dec_sub8_form[4:0] $1\dec31_dec_sub8_form[4:0] - attribute \src "libresoc.v:116660.5-116660.29" + attribute \src "libresoc.v:116736.5-116736.29" switch \initial - attribute \src "libresoc.v:116660.9-116660.17" + attribute \src "libresoc.v:116736.9-116736.17" case 1'1 case end @@ -181673,14 +181736,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_form $0\dec31_dec_sub8_form[4:0] end - attribute \src "libresoc.v:116702.3-116744.6" - process $proc$libresoc.v:116702$4418 + attribute \src "libresoc.v:116778.3-116820.6" + process $proc$libresoc.v:116778$4418 assign { } { } assign { } { } assign $0\dec31_dec_sub8_is_32b[0:0] $1\dec31_dec_sub8_is_32b[0:0] - attribute \src "libresoc.v:116703.5-116703.29" + attribute \src "libresoc.v:116779.5-116779.29" switch \initial - attribute \src "libresoc.v:116703.9-116703.17" + attribute \src "libresoc.v:116779.9-116779.17" case 1'1 case end @@ -181740,14 +181803,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_is_32b $0\dec31_dec_sub8_is_32b[0:0] end - attribute \src "libresoc.v:116745.3-116787.6" - process $proc$libresoc.v:116745$4419 + attribute \src "libresoc.v:116821.3-116863.6" + process $proc$libresoc.v:116821$4419 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sgn[0:0] $1\dec31_dec_sub8_sgn[0:0] - attribute \src "libresoc.v:116746.5-116746.29" + attribute \src "libresoc.v:116822.5-116822.29" switch \initial - attribute \src "libresoc.v:116746.9-116746.17" + attribute \src "libresoc.v:116822.9-116822.17" case 1'1 case end @@ -181807,14 +181870,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sgn $0\dec31_dec_sub8_sgn[0:0] end - attribute \src "libresoc.v:116788.3-116830.6" - process $proc$libresoc.v:116788$4420 + attribute \src "libresoc.v:116864.3-116906.6" + process $proc$libresoc.v:116864$4420 assign { } { } assign { } { } assign $0\dec31_dec_sub8_lk[0:0] $1\dec31_dec_sub8_lk[0:0] - attribute \src "libresoc.v:116789.5-116789.29" + attribute \src "libresoc.v:116865.5-116865.29" switch \initial - attribute \src "libresoc.v:116789.9-116789.17" + attribute \src "libresoc.v:116865.9-116865.17" case 1'1 case end @@ -181874,14 +181937,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_lk $0\dec31_dec_sub8_lk[0:0] end - attribute \src "libresoc.v:116831.3-116873.6" - process $proc$libresoc.v:116831$4421 + attribute \src "libresoc.v:116907.3-116949.6" + process $proc$libresoc.v:116907$4421 assign { } { } assign { } { } assign $0\dec31_dec_sub8_sgl_pipe[0:0] $1\dec31_dec_sub8_sgl_pipe[0:0] - attribute \src "libresoc.v:116832.5-116832.29" + attribute \src "libresoc.v:116908.5-116908.29" switch \initial - attribute \src "libresoc.v:116832.9-116832.17" + attribute \src "libresoc.v:116908.9-116908.17" case 1'1 case end @@ -181941,14 +182004,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_sgl_pipe $0\dec31_dec_sub8_sgl_pipe[0:0] end - attribute \src "libresoc.v:116874.3-116916.6" - process $proc$libresoc.v:116874$4422 + attribute \src "libresoc.v:116950.3-116992.6" + process $proc$libresoc.v:116950$4422 assign { } { } assign { } { } assign $0\dec31_dec_sub8_SV_Etype[1:0] $1\dec31_dec_sub8_SV_Etype[1:0] - attribute \src "libresoc.v:116875.5-116875.29" + attribute \src "libresoc.v:116951.5-116951.29" switch \initial - attribute \src "libresoc.v:116875.9-116875.17" + attribute \src "libresoc.v:116951.9-116951.17" case 1'1 case end @@ -182008,14 +182071,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_SV_Etype $0\dec31_dec_sub8_SV_Etype[1:0] end - attribute \src "libresoc.v:116917.3-116959.6" - process $proc$libresoc.v:116917$4423 + attribute \src "libresoc.v:116993.3-117035.6" + process $proc$libresoc.v:116993$4423 assign { } { } assign { } { } assign $0\dec31_dec_sub8_SV_Ptype[1:0] $1\dec31_dec_sub8_SV_Ptype[1:0] - attribute \src "libresoc.v:116918.5-116918.29" + attribute \src "libresoc.v:116994.5-116994.29" switch \initial - attribute \src "libresoc.v:116918.9-116918.17" + attribute \src "libresoc.v:116994.9-116994.17" case 1'1 case end @@ -182075,14 +182138,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_SV_Ptype $0\dec31_dec_sub8_SV_Ptype[1:0] end - attribute \src "libresoc.v:116960.3-117002.6" - process $proc$libresoc.v:116960$4424 + attribute \src "libresoc.v:117036.3-117078.6" + process $proc$libresoc.v:117036$4424 assign { } { } assign { } { } assign $0\dec31_dec_sub8_in1_sel[2:0] $1\dec31_dec_sub8_in1_sel[2:0] - attribute \src "libresoc.v:116961.5-116961.29" + attribute \src "libresoc.v:117037.5-117037.29" switch \initial - attribute \src "libresoc.v:116961.9-116961.17" + attribute \src "libresoc.v:117037.9-117037.17" case 1'1 case end @@ -182142,14 +182205,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_in1_sel $0\dec31_dec_sub8_in1_sel[2:0] end - attribute \src "libresoc.v:117003.3-117045.6" - process $proc$libresoc.v:117003$4425 + attribute \src "libresoc.v:117079.3-117121.6" + process $proc$libresoc.v:117079$4425 assign { } { } assign { } { } assign $0\dec31_dec_sub8_in2_sel[3:0] $1\dec31_dec_sub8_in2_sel[3:0] - attribute \src "libresoc.v:117004.5-117004.29" + attribute \src "libresoc.v:117080.5-117080.29" switch \initial - attribute \src "libresoc.v:117004.9-117004.17" + attribute \src "libresoc.v:117080.9-117080.17" case 1'1 case end @@ -182209,14 +182272,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_in2_sel $0\dec31_dec_sub8_in2_sel[3:0] end - attribute \src "libresoc.v:117046.3-117088.6" - process $proc$libresoc.v:117046$4426 + attribute \src "libresoc.v:117122.3-117164.6" + process $proc$libresoc.v:117122$4426 assign { } { } assign { } { } assign $0\dec31_dec_sub8_in3_sel[1:0] $1\dec31_dec_sub8_in3_sel[1:0] - attribute \src "libresoc.v:117047.5-117047.29" + attribute \src "libresoc.v:117123.5-117123.29" switch \initial - attribute \src "libresoc.v:117047.9-117047.17" + attribute \src "libresoc.v:117123.9-117123.17" case 1'1 case end @@ -182276,14 +182339,14 @@ module \dec31_dec_sub8 sync always update \dec31_dec_sub8_in3_sel $0\dec31_dec_sub8_in3_sel[1:0] end - attribute \src "libresoc.v:117089.3-117131.6" - process $proc$libresoc.v:117089$4427 + attribute \src "libresoc.v:117165.3-117207.6" + process $proc$libresoc.v:117165$4427 assign { } { } assign { } { } assign $0\dec31_dec_sub8_out_sel[2:0] $1\dec31_dec_sub8_out_sel[2:0] - attribute \src "libresoc.v:117090.5-117090.29" + attribute \src "libresoc.v:117166.5-117166.29" switch \initial - attribute \src "libresoc.v:117090.9-117090.17" + attribute \src "libresoc.v:117166.9-117166.17" case 1'1 case end @@ -182345,144 +182408,144 @@ module \dec31_dec_sub8 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:117137.1-119302.10" +attribute \src "libresoc.v:117213.1-119378.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec31.dec31_dec_sub9" attribute \generator "nMigen" module \dec31_dec_sub9 - attribute \src "libresoc.v:118971.3-119025.6" + attribute \src "libresoc.v:119047.3-119101.6" wire width 2 $0\dec31_dec_sub9_SV_Etype[1:0] - attribute \src "libresoc.v:119026.3-119080.6" + attribute \src "libresoc.v:119102.3-119156.6" wire width 2 $0\dec31_dec_sub9_SV_Ptype[1:0] - attribute \src "libresoc.v:118311.3-118365.6" + attribute \src "libresoc.v:118387.3-118441.6" wire width 8 $0\dec31_dec_sub9_asmcode[7:0] - attribute \src "libresoc.v:118531.3-118585.6" + attribute \src "libresoc.v:118607.3-118661.6" wire $0\dec31_dec_sub9_br[0:0] - attribute \src "libresoc.v:117541.3-117595.6" + attribute \src "libresoc.v:117617.3-117671.6" wire width 3 $0\dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:117596.3-117650.6" + attribute \src "libresoc.v:117672.3-117726.6" wire width 3 $0\dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:118256.3-118310.6" + attribute \src "libresoc.v:118332.3-118386.6" wire width 2 $0\dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:118476.3-118530.6" + attribute \src "libresoc.v:118552.3-118606.6" wire $0\dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:118696.3-118750.6" + attribute \src "libresoc.v:118772.3-118826.6" wire width 5 $0\dec31_dec_sub9_form[4:0] - attribute \src "libresoc.v:117486.3-117540.6" + attribute \src "libresoc.v:117562.3-117616.6" wire width 14 $0\dec31_dec_sub9_function_unit[13:0] - attribute \src "libresoc.v:119081.3-119135.6" + attribute \src "libresoc.v:119157.3-119211.6" wire width 3 $0\dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:119136.3-119190.6" + attribute \src "libresoc.v:119212.3-119266.6" wire width 4 $0\dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:119191.3-119245.6" + attribute \src "libresoc.v:119267.3-119321.6" wire width 2 $0\dec31_dec_sub9_in3_sel[1:0] - attribute \src "libresoc.v:118091.3-118145.6" + attribute \src "libresoc.v:118167.3-118221.6" wire width 7 $0\dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:118366.3-118420.6" + attribute \src "libresoc.v:118442.3-118496.6" wire $0\dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:118421.3-118475.6" + attribute \src "libresoc.v:118497.3-118551.6" wire $0\dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:118751.3-118805.6" + attribute \src "libresoc.v:118827.3-118881.6" wire $0\dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:118036.3-118090.6" + attribute \src "libresoc.v:118112.3-118166.6" wire width 4 $0\dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:118861.3-118915.6" + attribute \src "libresoc.v:118937.3-118991.6" wire $0\dec31_dec_sub9_lk[0:0] - attribute \src "libresoc.v:119246.3-119300.6" + attribute \src "libresoc.v:119322.3-119376.6" wire width 3 $0\dec31_dec_sub9_out_sel[2:0] - attribute \src "libresoc.v:118201.3-118255.6" + attribute \src "libresoc.v:118277.3-118331.6" wire width 2 $0\dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:118641.3-118695.6" + attribute \src "libresoc.v:118717.3-118771.6" wire $0\dec31_dec_sub9_rsrv[0:0] - attribute \src "libresoc.v:118916.3-118970.6" + attribute \src "libresoc.v:118992.3-119046.6" wire $0\dec31_dec_sub9_sgl_pipe[0:0] - attribute \src "libresoc.v:118806.3-118860.6" + attribute \src "libresoc.v:118882.3-118936.6" wire $0\dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:118586.3-118640.6" + attribute \src "libresoc.v:118662.3-118716.6" wire $0\dec31_dec_sub9_sgn_ext[0:0] - attribute \src "libresoc.v:117926.3-117980.6" + attribute \src "libresoc.v:118002.3-118056.6" wire width 3 $0\dec31_dec_sub9_sv_cr_in[2:0] - attribute \src "libresoc.v:117981.3-118035.6" + attribute \src "libresoc.v:118057.3-118111.6" wire width 3 $0\dec31_dec_sub9_sv_cr_out[2:0] - attribute \src "libresoc.v:117651.3-117705.6" + attribute \src "libresoc.v:117727.3-117781.6" wire width 3 $0\dec31_dec_sub9_sv_in1[2:0] - attribute \src "libresoc.v:117706.3-117760.6" + attribute \src "libresoc.v:117782.3-117836.6" wire width 3 $0\dec31_dec_sub9_sv_in2[2:0] - attribute \src "libresoc.v:117761.3-117815.6" + attribute \src "libresoc.v:117837.3-117891.6" wire width 3 $0\dec31_dec_sub9_sv_in3[2:0] - attribute \src "libresoc.v:117871.3-117925.6" + attribute \src "libresoc.v:117947.3-118001.6" wire width 3 $0\dec31_dec_sub9_sv_out2[2:0] - attribute \src "libresoc.v:117816.3-117870.6" + attribute \src "libresoc.v:117892.3-117946.6" wire width 3 $0\dec31_dec_sub9_sv_out[2:0] - attribute \src "libresoc.v:118146.3-118200.6" + attribute \src "libresoc.v:118222.3-118276.6" wire width 2 $0\dec31_dec_sub9_upd[1:0] - attribute \src "libresoc.v:117138.7-117138.20" + attribute \src "libresoc.v:117214.7-117214.20" wire $0\initial[0:0] - attribute \src "libresoc.v:118971.3-119025.6" + attribute \src "libresoc.v:119047.3-119101.6" wire width 2 $1\dec31_dec_sub9_SV_Etype[1:0] - attribute \src "libresoc.v:119026.3-119080.6" + attribute \src "libresoc.v:119102.3-119156.6" wire width 2 $1\dec31_dec_sub9_SV_Ptype[1:0] - attribute \src "libresoc.v:118311.3-118365.6" + attribute \src "libresoc.v:118387.3-118441.6" wire width 8 $1\dec31_dec_sub9_asmcode[7:0] - attribute \src "libresoc.v:118531.3-118585.6" + attribute \src "libresoc.v:118607.3-118661.6" wire $1\dec31_dec_sub9_br[0:0] - attribute \src "libresoc.v:117541.3-117595.6" + attribute \src "libresoc.v:117617.3-117671.6" wire width 3 $1\dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:117596.3-117650.6" + attribute \src "libresoc.v:117672.3-117726.6" wire width 3 $1\dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:118256.3-118310.6" + attribute \src "libresoc.v:118332.3-118386.6" wire width 2 $1\dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:118476.3-118530.6" + attribute \src "libresoc.v:118552.3-118606.6" wire $1\dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:118696.3-118750.6" + attribute \src "libresoc.v:118772.3-118826.6" wire width 5 $1\dec31_dec_sub9_form[4:0] - attribute \src "libresoc.v:117486.3-117540.6" + attribute \src "libresoc.v:117562.3-117616.6" wire width 14 $1\dec31_dec_sub9_function_unit[13:0] - attribute \src "libresoc.v:119081.3-119135.6" + attribute \src "libresoc.v:119157.3-119211.6" wire width 3 $1\dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:119136.3-119190.6" + attribute \src "libresoc.v:119212.3-119266.6" wire width 4 $1\dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:119191.3-119245.6" + attribute \src "libresoc.v:119267.3-119321.6" wire width 2 $1\dec31_dec_sub9_in3_sel[1:0] - attribute \src "libresoc.v:118091.3-118145.6" + attribute \src "libresoc.v:118167.3-118221.6" wire width 7 $1\dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:118366.3-118420.6" + attribute \src "libresoc.v:118442.3-118496.6" wire $1\dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:118421.3-118475.6" + attribute \src "libresoc.v:118497.3-118551.6" wire $1\dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:118751.3-118805.6" + attribute \src "libresoc.v:118827.3-118881.6" wire $1\dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:118036.3-118090.6" + attribute \src "libresoc.v:118112.3-118166.6" wire width 4 $1\dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:118861.3-118915.6" + attribute \src "libresoc.v:118937.3-118991.6" wire $1\dec31_dec_sub9_lk[0:0] - attribute \src "libresoc.v:119246.3-119300.6" + attribute \src "libresoc.v:119322.3-119376.6" wire width 3 $1\dec31_dec_sub9_out_sel[2:0] - attribute \src "libresoc.v:118201.3-118255.6" + attribute \src "libresoc.v:118277.3-118331.6" wire width 2 $1\dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:118641.3-118695.6" + attribute \src "libresoc.v:118717.3-118771.6" wire $1\dec31_dec_sub9_rsrv[0:0] - attribute \src "libresoc.v:118916.3-118970.6" + attribute \src "libresoc.v:118992.3-119046.6" wire $1\dec31_dec_sub9_sgl_pipe[0:0] - attribute \src "libresoc.v:118806.3-118860.6" + attribute \src "libresoc.v:118882.3-118936.6" wire $1\dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:118586.3-118640.6" + attribute \src "libresoc.v:118662.3-118716.6" wire $1\dec31_dec_sub9_sgn_ext[0:0] - attribute \src "libresoc.v:117926.3-117980.6" + attribute \src "libresoc.v:118002.3-118056.6" wire width 3 $1\dec31_dec_sub9_sv_cr_in[2:0] - attribute \src "libresoc.v:117981.3-118035.6" + attribute \src "libresoc.v:118057.3-118111.6" wire width 3 $1\dec31_dec_sub9_sv_cr_out[2:0] - attribute \src "libresoc.v:117651.3-117705.6" + attribute \src "libresoc.v:117727.3-117781.6" wire width 3 $1\dec31_dec_sub9_sv_in1[2:0] - attribute \src "libresoc.v:117706.3-117760.6" + attribute \src "libresoc.v:117782.3-117836.6" wire width 3 $1\dec31_dec_sub9_sv_in2[2:0] - attribute \src "libresoc.v:117761.3-117815.6" + attribute \src "libresoc.v:117837.3-117891.6" wire width 3 $1\dec31_dec_sub9_sv_in3[2:0] - attribute \src "libresoc.v:117871.3-117925.6" + attribute \src "libresoc.v:117947.3-118001.6" wire width 3 $1\dec31_dec_sub9_sv_out2[2:0] - attribute \src "libresoc.v:117816.3-117870.6" + attribute \src "libresoc.v:117892.3-117946.6" wire width 3 $1\dec31_dec_sub9_sv_out[2:0] - attribute \src "libresoc.v:118146.3-118200.6" + attribute \src "libresoc.v:118222.3-118276.6" wire width 2 $1\dec31_dec_sub9_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -182794,28 +182857,28 @@ module \dec31_dec_sub9 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec31_dec_sub9_upd - attribute \src "libresoc.v:117138.7-117138.15" + attribute \src "libresoc.v:117214.7-117214.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 5 \opcode_switch - attribute \src "libresoc.v:117138.7-117138.20" - process $proc$libresoc.v:117138$4462 + attribute \src "libresoc.v:117214.7-117214.20" + process $proc$libresoc.v:117214$4462 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:117486.3-117540.6" - process $proc$libresoc.v:117486$4429 + attribute \src "libresoc.v:117562.3-117616.6" + process $proc$libresoc.v:117562$4429 assign { } { } assign { } { } assign $0\dec31_dec_sub9_function_unit[13:0] $1\dec31_dec_sub9_function_unit[13:0] - attribute \src "libresoc.v:117487.5-117487.29" + attribute \src "libresoc.v:117563.5-117563.29" switch \initial - attribute \src "libresoc.v:117487.9-117487.17" + attribute \src "libresoc.v:117563.9-117563.17" case 1'1 case end @@ -182891,14 +182954,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_function_unit $0\dec31_dec_sub9_function_unit[13:0] end - attribute \src "libresoc.v:117541.3-117595.6" - process $proc$libresoc.v:117541$4430 + attribute \src "libresoc.v:117617.3-117671.6" + process $proc$libresoc.v:117617$4430 assign { } { } assign { } { } assign $0\dec31_dec_sub9_cr_in[2:0] $1\dec31_dec_sub9_cr_in[2:0] - attribute \src "libresoc.v:117542.5-117542.29" + attribute \src "libresoc.v:117618.5-117618.29" switch \initial - attribute \src "libresoc.v:117542.9-117542.17" + attribute \src "libresoc.v:117618.9-117618.17" case 1'1 case end @@ -182974,14 +183037,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_cr_in $0\dec31_dec_sub9_cr_in[2:0] end - attribute \src "libresoc.v:117596.3-117650.6" - process $proc$libresoc.v:117596$4431 + attribute \src "libresoc.v:117672.3-117726.6" + process $proc$libresoc.v:117672$4431 assign { } { } assign { } { } assign $0\dec31_dec_sub9_cr_out[2:0] $1\dec31_dec_sub9_cr_out[2:0] - attribute \src "libresoc.v:117597.5-117597.29" + attribute \src "libresoc.v:117673.5-117673.29" switch \initial - attribute \src "libresoc.v:117597.9-117597.17" + attribute \src "libresoc.v:117673.9-117673.17" case 1'1 case end @@ -183057,14 +183120,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_cr_out $0\dec31_dec_sub9_cr_out[2:0] end - attribute \src "libresoc.v:117651.3-117705.6" - process $proc$libresoc.v:117651$4432 + attribute \src "libresoc.v:117727.3-117781.6" + process $proc$libresoc.v:117727$4432 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_in1[2:0] $1\dec31_dec_sub9_sv_in1[2:0] - attribute \src "libresoc.v:117652.5-117652.29" + attribute \src "libresoc.v:117728.5-117728.29" switch \initial - attribute \src "libresoc.v:117652.9-117652.17" + attribute \src "libresoc.v:117728.9-117728.17" case 1'1 case end @@ -183140,14 +183203,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_in1 $0\dec31_dec_sub9_sv_in1[2:0] end - attribute \src "libresoc.v:117706.3-117760.6" - process $proc$libresoc.v:117706$4433 + attribute \src "libresoc.v:117782.3-117836.6" + process $proc$libresoc.v:117782$4433 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_in2[2:0] $1\dec31_dec_sub9_sv_in2[2:0] - attribute \src "libresoc.v:117707.5-117707.29" + attribute \src "libresoc.v:117783.5-117783.29" switch \initial - attribute \src "libresoc.v:117707.9-117707.17" + attribute \src "libresoc.v:117783.9-117783.17" case 1'1 case end @@ -183223,14 +183286,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_in2 $0\dec31_dec_sub9_sv_in2[2:0] end - attribute \src "libresoc.v:117761.3-117815.6" - process $proc$libresoc.v:117761$4434 + attribute \src "libresoc.v:117837.3-117891.6" + process $proc$libresoc.v:117837$4434 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_in3[2:0] $1\dec31_dec_sub9_sv_in3[2:0] - attribute \src "libresoc.v:117762.5-117762.29" + attribute \src "libresoc.v:117838.5-117838.29" switch \initial - attribute \src "libresoc.v:117762.9-117762.17" + attribute \src "libresoc.v:117838.9-117838.17" case 1'1 case end @@ -183306,14 +183369,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_in3 $0\dec31_dec_sub9_sv_in3[2:0] end - attribute \src "libresoc.v:117816.3-117870.6" - process $proc$libresoc.v:117816$4435 + attribute \src "libresoc.v:117892.3-117946.6" + process $proc$libresoc.v:117892$4435 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_out[2:0] $1\dec31_dec_sub9_sv_out[2:0] - attribute \src "libresoc.v:117817.5-117817.29" + attribute \src "libresoc.v:117893.5-117893.29" switch \initial - attribute \src "libresoc.v:117817.9-117817.17" + attribute \src "libresoc.v:117893.9-117893.17" case 1'1 case end @@ -183389,14 +183452,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_out $0\dec31_dec_sub9_sv_out[2:0] end - attribute \src "libresoc.v:117871.3-117925.6" - process $proc$libresoc.v:117871$4436 + attribute \src "libresoc.v:117947.3-118001.6" + process $proc$libresoc.v:117947$4436 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_out2[2:0] $1\dec31_dec_sub9_sv_out2[2:0] - attribute \src "libresoc.v:117872.5-117872.29" + attribute \src "libresoc.v:117948.5-117948.29" switch \initial - attribute \src "libresoc.v:117872.9-117872.17" + attribute \src "libresoc.v:117948.9-117948.17" case 1'1 case end @@ -183472,14 +183535,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_out2 $0\dec31_dec_sub9_sv_out2[2:0] end - attribute \src "libresoc.v:117926.3-117980.6" - process $proc$libresoc.v:117926$4437 + attribute \src "libresoc.v:118002.3-118056.6" + process $proc$libresoc.v:118002$4437 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_cr_in[2:0] $1\dec31_dec_sub9_sv_cr_in[2:0] - attribute \src "libresoc.v:117927.5-117927.29" + attribute \src "libresoc.v:118003.5-118003.29" switch \initial - attribute \src "libresoc.v:117927.9-117927.17" + attribute \src "libresoc.v:118003.9-118003.17" case 1'1 case end @@ -183555,14 +183618,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_cr_in $0\dec31_dec_sub9_sv_cr_in[2:0] end - attribute \src "libresoc.v:117981.3-118035.6" - process $proc$libresoc.v:117981$4438 + attribute \src "libresoc.v:118057.3-118111.6" + process $proc$libresoc.v:118057$4438 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sv_cr_out[2:0] $1\dec31_dec_sub9_sv_cr_out[2:0] - attribute \src "libresoc.v:117982.5-117982.29" + attribute \src "libresoc.v:118058.5-118058.29" switch \initial - attribute \src "libresoc.v:117982.9-117982.17" + attribute \src "libresoc.v:118058.9-118058.17" case 1'1 case end @@ -183638,14 +183701,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sv_cr_out $0\dec31_dec_sub9_sv_cr_out[2:0] end - attribute \src "libresoc.v:118036.3-118090.6" - process $proc$libresoc.v:118036$4439 + attribute \src "libresoc.v:118112.3-118166.6" + process $proc$libresoc.v:118112$4439 assign { } { } assign { } { } assign $0\dec31_dec_sub9_ldst_len[3:0] $1\dec31_dec_sub9_ldst_len[3:0] - attribute \src "libresoc.v:118037.5-118037.29" + attribute \src "libresoc.v:118113.5-118113.29" switch \initial - attribute \src "libresoc.v:118037.9-118037.17" + attribute \src "libresoc.v:118113.9-118113.17" case 1'1 case end @@ -183721,14 +183784,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_ldst_len $0\dec31_dec_sub9_ldst_len[3:0] end - attribute \src "libresoc.v:118091.3-118145.6" - process $proc$libresoc.v:118091$4440 + attribute \src "libresoc.v:118167.3-118221.6" + process $proc$libresoc.v:118167$4440 assign { } { } assign { } { } assign $0\dec31_dec_sub9_internal_op[6:0] $1\dec31_dec_sub9_internal_op[6:0] - attribute \src "libresoc.v:118092.5-118092.29" + attribute \src "libresoc.v:118168.5-118168.29" switch \initial - attribute \src "libresoc.v:118092.9-118092.17" + attribute \src "libresoc.v:118168.9-118168.17" case 1'1 case end @@ -183804,14 +183867,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_internal_op $0\dec31_dec_sub9_internal_op[6:0] end - attribute \src "libresoc.v:118146.3-118200.6" - process $proc$libresoc.v:118146$4441 + attribute \src "libresoc.v:118222.3-118276.6" + process $proc$libresoc.v:118222$4441 assign { } { } assign { } { } assign $0\dec31_dec_sub9_upd[1:0] $1\dec31_dec_sub9_upd[1:0] - attribute \src "libresoc.v:118147.5-118147.29" + attribute \src "libresoc.v:118223.5-118223.29" switch \initial - attribute \src "libresoc.v:118147.9-118147.17" + attribute \src "libresoc.v:118223.9-118223.17" case 1'1 case end @@ -183887,14 +183950,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_upd $0\dec31_dec_sub9_upd[1:0] end - attribute \src "libresoc.v:118201.3-118255.6" - process $proc$libresoc.v:118201$4442 + attribute \src "libresoc.v:118277.3-118331.6" + process $proc$libresoc.v:118277$4442 assign { } { } assign { } { } assign $0\dec31_dec_sub9_rc_sel[1:0] $1\dec31_dec_sub9_rc_sel[1:0] - attribute \src "libresoc.v:118202.5-118202.29" + attribute \src "libresoc.v:118278.5-118278.29" switch \initial - attribute \src "libresoc.v:118202.9-118202.17" + attribute \src "libresoc.v:118278.9-118278.17" case 1'1 case end @@ -183970,14 +184033,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_rc_sel $0\dec31_dec_sub9_rc_sel[1:0] end - attribute \src "libresoc.v:118256.3-118310.6" - process $proc$libresoc.v:118256$4443 + attribute \src "libresoc.v:118332.3-118386.6" + process $proc$libresoc.v:118332$4443 assign { } { } assign { } { } assign $0\dec31_dec_sub9_cry_in[1:0] $1\dec31_dec_sub9_cry_in[1:0] - attribute \src "libresoc.v:118257.5-118257.29" + attribute \src "libresoc.v:118333.5-118333.29" switch \initial - attribute \src "libresoc.v:118257.9-118257.17" + attribute \src "libresoc.v:118333.9-118333.17" case 1'1 case end @@ -184053,14 +184116,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_cry_in $0\dec31_dec_sub9_cry_in[1:0] end - attribute \src "libresoc.v:118311.3-118365.6" - process $proc$libresoc.v:118311$4444 + attribute \src "libresoc.v:118387.3-118441.6" + process $proc$libresoc.v:118387$4444 assign { } { } assign { } { } assign $0\dec31_dec_sub9_asmcode[7:0] $1\dec31_dec_sub9_asmcode[7:0] - attribute \src "libresoc.v:118312.5-118312.29" + attribute \src "libresoc.v:118388.5-118388.29" switch \initial - attribute \src "libresoc.v:118312.9-118312.17" + attribute \src "libresoc.v:118388.9-118388.17" case 1'1 case end @@ -184136,14 +184199,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_asmcode $0\dec31_dec_sub9_asmcode[7:0] end - attribute \src "libresoc.v:118366.3-118420.6" - process $proc$libresoc.v:118366$4445 + attribute \src "libresoc.v:118442.3-118496.6" + process $proc$libresoc.v:118442$4445 assign { } { } assign { } { } assign $0\dec31_dec_sub9_inv_a[0:0] $1\dec31_dec_sub9_inv_a[0:0] - attribute \src "libresoc.v:118367.5-118367.29" + attribute \src "libresoc.v:118443.5-118443.29" switch \initial - attribute \src "libresoc.v:118367.9-118367.17" + attribute \src "libresoc.v:118443.9-118443.17" case 1'1 case end @@ -184219,14 +184282,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_inv_a $0\dec31_dec_sub9_inv_a[0:0] end - attribute \src "libresoc.v:118421.3-118475.6" - process $proc$libresoc.v:118421$4446 + attribute \src "libresoc.v:118497.3-118551.6" + process $proc$libresoc.v:118497$4446 assign { } { } assign { } { } assign $0\dec31_dec_sub9_inv_out[0:0] $1\dec31_dec_sub9_inv_out[0:0] - attribute \src "libresoc.v:118422.5-118422.29" + attribute \src "libresoc.v:118498.5-118498.29" switch \initial - attribute \src "libresoc.v:118422.9-118422.17" + attribute \src "libresoc.v:118498.9-118498.17" case 1'1 case end @@ -184302,14 +184365,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_inv_out $0\dec31_dec_sub9_inv_out[0:0] end - attribute \src "libresoc.v:118476.3-118530.6" - process $proc$libresoc.v:118476$4447 + attribute \src "libresoc.v:118552.3-118606.6" + process $proc$libresoc.v:118552$4447 assign { } { } assign { } { } assign $0\dec31_dec_sub9_cry_out[0:0] $1\dec31_dec_sub9_cry_out[0:0] - attribute \src "libresoc.v:118477.5-118477.29" + attribute \src "libresoc.v:118553.5-118553.29" switch \initial - attribute \src "libresoc.v:118477.9-118477.17" + attribute \src "libresoc.v:118553.9-118553.17" case 1'1 case end @@ -184385,14 +184448,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_cry_out $0\dec31_dec_sub9_cry_out[0:0] end - attribute \src "libresoc.v:118531.3-118585.6" - process $proc$libresoc.v:118531$4448 + attribute \src "libresoc.v:118607.3-118661.6" + process $proc$libresoc.v:118607$4448 assign { } { } assign { } { } assign $0\dec31_dec_sub9_br[0:0] $1\dec31_dec_sub9_br[0:0] - attribute \src "libresoc.v:118532.5-118532.29" + attribute \src "libresoc.v:118608.5-118608.29" switch \initial - attribute \src "libresoc.v:118532.9-118532.17" + attribute \src "libresoc.v:118608.9-118608.17" case 1'1 case end @@ -184468,14 +184531,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_br $0\dec31_dec_sub9_br[0:0] end - attribute \src "libresoc.v:118586.3-118640.6" - process $proc$libresoc.v:118586$4449 + attribute \src "libresoc.v:118662.3-118716.6" + process $proc$libresoc.v:118662$4449 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sgn_ext[0:0] $1\dec31_dec_sub9_sgn_ext[0:0] - attribute \src "libresoc.v:118587.5-118587.29" + attribute \src "libresoc.v:118663.5-118663.29" switch \initial - attribute \src "libresoc.v:118587.9-118587.17" + attribute \src "libresoc.v:118663.9-118663.17" case 1'1 case end @@ -184551,14 +184614,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sgn_ext $0\dec31_dec_sub9_sgn_ext[0:0] end - attribute \src "libresoc.v:118641.3-118695.6" - process $proc$libresoc.v:118641$4450 + attribute \src "libresoc.v:118717.3-118771.6" + process $proc$libresoc.v:118717$4450 assign { } { } assign { } { } assign $0\dec31_dec_sub9_rsrv[0:0] $1\dec31_dec_sub9_rsrv[0:0] - attribute \src "libresoc.v:118642.5-118642.29" + attribute \src "libresoc.v:118718.5-118718.29" switch \initial - attribute \src "libresoc.v:118642.9-118642.17" + attribute \src "libresoc.v:118718.9-118718.17" case 1'1 case end @@ -184634,14 +184697,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_rsrv $0\dec31_dec_sub9_rsrv[0:0] end - attribute \src "libresoc.v:118696.3-118750.6" - process $proc$libresoc.v:118696$4451 + attribute \src "libresoc.v:118772.3-118826.6" + process $proc$libresoc.v:118772$4451 assign { } { } assign { } { } assign $0\dec31_dec_sub9_form[4:0] $1\dec31_dec_sub9_form[4:0] - attribute \src "libresoc.v:118697.5-118697.29" + attribute \src "libresoc.v:118773.5-118773.29" switch \initial - attribute \src "libresoc.v:118697.9-118697.17" + attribute \src "libresoc.v:118773.9-118773.17" case 1'1 case end @@ -184717,14 +184780,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_form $0\dec31_dec_sub9_form[4:0] end - attribute \src "libresoc.v:118751.3-118805.6" - process $proc$libresoc.v:118751$4452 + attribute \src "libresoc.v:118827.3-118881.6" + process $proc$libresoc.v:118827$4452 assign { } { } assign { } { } assign $0\dec31_dec_sub9_is_32b[0:0] $1\dec31_dec_sub9_is_32b[0:0] - attribute \src "libresoc.v:118752.5-118752.29" + attribute \src "libresoc.v:118828.5-118828.29" switch \initial - attribute \src "libresoc.v:118752.9-118752.17" + attribute \src "libresoc.v:118828.9-118828.17" case 1'1 case end @@ -184800,14 +184863,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_is_32b $0\dec31_dec_sub9_is_32b[0:0] end - attribute \src "libresoc.v:118806.3-118860.6" - process $proc$libresoc.v:118806$4453 + attribute \src "libresoc.v:118882.3-118936.6" + process $proc$libresoc.v:118882$4453 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sgn[0:0] $1\dec31_dec_sub9_sgn[0:0] - attribute \src "libresoc.v:118807.5-118807.29" + attribute \src "libresoc.v:118883.5-118883.29" switch \initial - attribute \src "libresoc.v:118807.9-118807.17" + attribute \src "libresoc.v:118883.9-118883.17" case 1'1 case end @@ -184883,14 +184946,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sgn $0\dec31_dec_sub9_sgn[0:0] end - attribute \src "libresoc.v:118861.3-118915.6" - process $proc$libresoc.v:118861$4454 + attribute \src "libresoc.v:118937.3-118991.6" + process $proc$libresoc.v:118937$4454 assign { } { } assign { } { } assign $0\dec31_dec_sub9_lk[0:0] $1\dec31_dec_sub9_lk[0:0] - attribute \src "libresoc.v:118862.5-118862.29" + attribute \src "libresoc.v:118938.5-118938.29" switch \initial - attribute \src "libresoc.v:118862.9-118862.17" + attribute \src "libresoc.v:118938.9-118938.17" case 1'1 case end @@ -184966,14 +185029,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_lk $0\dec31_dec_sub9_lk[0:0] end - attribute \src "libresoc.v:118916.3-118970.6" - process $proc$libresoc.v:118916$4455 + attribute \src "libresoc.v:118992.3-119046.6" + process $proc$libresoc.v:118992$4455 assign { } { } assign { } { } assign $0\dec31_dec_sub9_sgl_pipe[0:0] $1\dec31_dec_sub9_sgl_pipe[0:0] - attribute \src "libresoc.v:118917.5-118917.29" + attribute \src "libresoc.v:118993.5-118993.29" switch \initial - attribute \src "libresoc.v:118917.9-118917.17" + attribute \src "libresoc.v:118993.9-118993.17" case 1'1 case end @@ -185049,14 +185112,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_sgl_pipe $0\dec31_dec_sub9_sgl_pipe[0:0] end - attribute \src "libresoc.v:118971.3-119025.6" - process $proc$libresoc.v:118971$4456 + attribute \src "libresoc.v:119047.3-119101.6" + process $proc$libresoc.v:119047$4456 assign { } { } assign { } { } assign $0\dec31_dec_sub9_SV_Etype[1:0] $1\dec31_dec_sub9_SV_Etype[1:0] - attribute \src "libresoc.v:118972.5-118972.29" + attribute \src "libresoc.v:119048.5-119048.29" switch \initial - attribute \src "libresoc.v:118972.9-118972.17" + attribute \src "libresoc.v:119048.9-119048.17" case 1'1 case end @@ -185132,14 +185195,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_SV_Etype $0\dec31_dec_sub9_SV_Etype[1:0] end - attribute \src "libresoc.v:119026.3-119080.6" - process $proc$libresoc.v:119026$4457 + attribute \src "libresoc.v:119102.3-119156.6" + process $proc$libresoc.v:119102$4457 assign { } { } assign { } { } assign $0\dec31_dec_sub9_SV_Ptype[1:0] $1\dec31_dec_sub9_SV_Ptype[1:0] - attribute \src "libresoc.v:119027.5-119027.29" + attribute \src "libresoc.v:119103.5-119103.29" switch \initial - attribute \src "libresoc.v:119027.9-119027.17" + attribute \src "libresoc.v:119103.9-119103.17" case 1'1 case end @@ -185215,14 +185278,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_SV_Ptype $0\dec31_dec_sub9_SV_Ptype[1:0] end - attribute \src "libresoc.v:119081.3-119135.6" - process $proc$libresoc.v:119081$4458 + attribute \src "libresoc.v:119157.3-119211.6" + process $proc$libresoc.v:119157$4458 assign { } { } assign { } { } assign $0\dec31_dec_sub9_in1_sel[2:0] $1\dec31_dec_sub9_in1_sel[2:0] - attribute \src "libresoc.v:119082.5-119082.29" + attribute \src "libresoc.v:119158.5-119158.29" switch \initial - attribute \src "libresoc.v:119082.9-119082.17" + attribute \src "libresoc.v:119158.9-119158.17" case 1'1 case end @@ -185298,14 +185361,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_in1_sel $0\dec31_dec_sub9_in1_sel[2:0] end - attribute \src "libresoc.v:119136.3-119190.6" - process $proc$libresoc.v:119136$4459 + attribute \src "libresoc.v:119212.3-119266.6" + process $proc$libresoc.v:119212$4459 assign { } { } assign { } { } assign $0\dec31_dec_sub9_in2_sel[3:0] $1\dec31_dec_sub9_in2_sel[3:0] - attribute \src "libresoc.v:119137.5-119137.29" + attribute \src "libresoc.v:119213.5-119213.29" switch \initial - attribute \src "libresoc.v:119137.9-119137.17" + attribute \src "libresoc.v:119213.9-119213.17" case 1'1 case end @@ -185381,14 +185444,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_in2_sel $0\dec31_dec_sub9_in2_sel[3:0] end - attribute \src "libresoc.v:119191.3-119245.6" - process $proc$libresoc.v:119191$4460 + attribute \src "libresoc.v:119267.3-119321.6" + process $proc$libresoc.v:119267$4460 assign { } { } assign { } { } assign $0\dec31_dec_sub9_in3_sel[1:0] $1\dec31_dec_sub9_in3_sel[1:0] - attribute \src "libresoc.v:119192.5-119192.29" + attribute \src "libresoc.v:119268.5-119268.29" switch \initial - attribute \src "libresoc.v:119192.9-119192.17" + attribute \src "libresoc.v:119268.9-119268.17" case 1'1 case end @@ -185464,14 +185527,14 @@ module \dec31_dec_sub9 sync always update \dec31_dec_sub9_in3_sel $0\dec31_dec_sub9_in3_sel[1:0] end - attribute \src "libresoc.v:119246.3-119300.6" - process $proc$libresoc.v:119246$4461 + attribute \src "libresoc.v:119322.3-119376.6" + process $proc$libresoc.v:119322$4461 assign { } { } assign { } { } assign $0\dec31_dec_sub9_out_sel[2:0] $1\dec31_dec_sub9_out_sel[2:0] - attribute \src "libresoc.v:119247.5-119247.29" + attribute \src "libresoc.v:119323.5-119323.29" switch \initial - attribute \src "libresoc.v:119247.9-119247.17" + attribute \src "libresoc.v:119323.9-119323.17" case 1'1 case end @@ -185549,144 +185612,144 @@ module \dec31_dec_sub9 end connect \opcode_switch \opcode_in [10:6] end -attribute \src "libresoc.v:119306.1-120184.10" +attribute \src "libresoc.v:119382.1-120260.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec58" attribute \generator "nMigen" module \dec58 - attribute \src "libresoc.v:120087.3-120102.6" + attribute \src "libresoc.v:120163.3-120178.6" wire width 2 $0\dec58_SV_Etype[1:0] - attribute \src "libresoc.v:120103.3-120118.6" + attribute \src "libresoc.v:120179.3-120194.6" wire width 2 $0\dec58_SV_Ptype[1:0] - attribute \src "libresoc.v:119895.3-119910.6" + attribute \src "libresoc.v:119971.3-119986.6" wire width 8 $0\dec58_asmcode[7:0] - attribute \src "libresoc.v:119959.3-119974.6" + attribute \src "libresoc.v:120035.3-120050.6" wire $0\dec58_br[0:0] - attribute \src "libresoc.v:119671.3-119686.6" + attribute \src "libresoc.v:119747.3-119762.6" wire width 3 $0\dec58_cr_in[2:0] - attribute \src "libresoc.v:119687.3-119702.6" + attribute \src "libresoc.v:119763.3-119778.6" wire width 3 $0\dec58_cr_out[2:0] - attribute \src "libresoc.v:119879.3-119894.6" + attribute \src "libresoc.v:119955.3-119970.6" wire width 2 $0\dec58_cry_in[1:0] - attribute \src "libresoc.v:119943.3-119958.6" + attribute \src "libresoc.v:120019.3-120034.6" wire $0\dec58_cry_out[0:0] - attribute \src "libresoc.v:120007.3-120022.6" + attribute \src "libresoc.v:120083.3-120098.6" wire width 5 $0\dec58_form[4:0] - attribute \src "libresoc.v:119655.3-119670.6" + attribute \src "libresoc.v:119731.3-119746.6" wire width 14 $0\dec58_function_unit[13:0] - attribute \src "libresoc.v:120119.3-120134.6" + attribute \src "libresoc.v:120195.3-120210.6" wire width 3 $0\dec58_in1_sel[2:0] - attribute \src "libresoc.v:120135.3-120150.6" + attribute \src "libresoc.v:120211.3-120226.6" wire width 4 $0\dec58_in2_sel[3:0] - attribute \src "libresoc.v:120151.3-120166.6" + attribute \src "libresoc.v:120227.3-120242.6" wire width 2 $0\dec58_in3_sel[1:0] - attribute \src "libresoc.v:119831.3-119846.6" + attribute \src "libresoc.v:119907.3-119922.6" wire width 7 $0\dec58_internal_op[6:0] - attribute \src "libresoc.v:119911.3-119926.6" + attribute \src "libresoc.v:119987.3-120002.6" wire $0\dec58_inv_a[0:0] - attribute \src "libresoc.v:119927.3-119942.6" + attribute \src "libresoc.v:120003.3-120018.6" wire $0\dec58_inv_out[0:0] - attribute \src "libresoc.v:120023.3-120038.6" + attribute \src "libresoc.v:120099.3-120114.6" wire $0\dec58_is_32b[0:0] - attribute \src "libresoc.v:119815.3-119830.6" + attribute \src "libresoc.v:119891.3-119906.6" wire width 4 $0\dec58_ldst_len[3:0] - attribute \src "libresoc.v:120055.3-120070.6" + attribute \src "libresoc.v:120131.3-120146.6" wire $0\dec58_lk[0:0] - attribute \src "libresoc.v:120167.3-120182.6" + attribute \src "libresoc.v:120243.3-120258.6" wire width 3 $0\dec58_out_sel[2:0] - attribute \src "libresoc.v:119863.3-119878.6" + attribute \src "libresoc.v:119939.3-119954.6" wire width 2 $0\dec58_rc_sel[1:0] - attribute \src "libresoc.v:119991.3-120006.6" + attribute \src "libresoc.v:120067.3-120082.6" wire $0\dec58_rsrv[0:0] - attribute \src "libresoc.v:120071.3-120086.6" + attribute \src "libresoc.v:120147.3-120162.6" wire $0\dec58_sgl_pipe[0:0] - attribute \src "libresoc.v:120039.3-120054.6" + attribute \src "libresoc.v:120115.3-120130.6" wire $0\dec58_sgn[0:0] - attribute \src "libresoc.v:119975.3-119990.6" + attribute \src "libresoc.v:120051.3-120066.6" wire $0\dec58_sgn_ext[0:0] - attribute \src "libresoc.v:119783.3-119798.6" + attribute \src "libresoc.v:119859.3-119874.6" wire width 3 $0\dec58_sv_cr_in[2:0] - attribute \src "libresoc.v:119799.3-119814.6" + attribute \src "libresoc.v:119875.3-119890.6" wire width 3 $0\dec58_sv_cr_out[2:0] - attribute \src "libresoc.v:119703.3-119718.6" + attribute \src "libresoc.v:119779.3-119794.6" wire width 3 $0\dec58_sv_in1[2:0] - attribute \src "libresoc.v:119719.3-119734.6" + attribute \src "libresoc.v:119795.3-119810.6" wire width 3 $0\dec58_sv_in2[2:0] - attribute \src "libresoc.v:119735.3-119750.6" + attribute \src "libresoc.v:119811.3-119826.6" wire width 3 $0\dec58_sv_in3[2:0] - attribute \src "libresoc.v:119767.3-119782.6" + attribute \src "libresoc.v:119843.3-119858.6" wire width 3 $0\dec58_sv_out2[2:0] - attribute \src "libresoc.v:119751.3-119766.6" + attribute \src "libresoc.v:119827.3-119842.6" wire width 3 $0\dec58_sv_out[2:0] - attribute \src "libresoc.v:119847.3-119862.6" + attribute \src "libresoc.v:119923.3-119938.6" wire width 2 $0\dec58_upd[1:0] - attribute \src "libresoc.v:119307.7-119307.20" + attribute \src "libresoc.v:119383.7-119383.20" wire $0\initial[0:0] - attribute \src "libresoc.v:120087.3-120102.6" + attribute \src "libresoc.v:120163.3-120178.6" wire width 2 $1\dec58_SV_Etype[1:0] - attribute \src "libresoc.v:120103.3-120118.6" + attribute \src "libresoc.v:120179.3-120194.6" wire width 2 $1\dec58_SV_Ptype[1:0] - attribute \src "libresoc.v:119895.3-119910.6" + attribute \src "libresoc.v:119971.3-119986.6" wire width 8 $1\dec58_asmcode[7:0] - attribute \src "libresoc.v:119959.3-119974.6" + attribute \src "libresoc.v:120035.3-120050.6" wire $1\dec58_br[0:0] - attribute \src "libresoc.v:119671.3-119686.6" + attribute \src "libresoc.v:119747.3-119762.6" wire width 3 $1\dec58_cr_in[2:0] - attribute \src "libresoc.v:119687.3-119702.6" + attribute \src "libresoc.v:119763.3-119778.6" wire width 3 $1\dec58_cr_out[2:0] - attribute \src "libresoc.v:119879.3-119894.6" + attribute \src "libresoc.v:119955.3-119970.6" wire width 2 $1\dec58_cry_in[1:0] - attribute \src "libresoc.v:119943.3-119958.6" + attribute \src "libresoc.v:120019.3-120034.6" wire $1\dec58_cry_out[0:0] - attribute \src "libresoc.v:120007.3-120022.6" + attribute \src "libresoc.v:120083.3-120098.6" wire width 5 $1\dec58_form[4:0] - attribute \src "libresoc.v:119655.3-119670.6" + attribute \src "libresoc.v:119731.3-119746.6" wire width 14 $1\dec58_function_unit[13:0] - attribute \src "libresoc.v:120119.3-120134.6" + attribute \src "libresoc.v:120195.3-120210.6" wire width 3 $1\dec58_in1_sel[2:0] - attribute \src "libresoc.v:120135.3-120150.6" + attribute \src "libresoc.v:120211.3-120226.6" wire width 4 $1\dec58_in2_sel[3:0] - attribute \src "libresoc.v:120151.3-120166.6" + attribute \src "libresoc.v:120227.3-120242.6" wire width 2 $1\dec58_in3_sel[1:0] - attribute \src "libresoc.v:119831.3-119846.6" + attribute \src "libresoc.v:119907.3-119922.6" wire width 7 $1\dec58_internal_op[6:0] - attribute \src "libresoc.v:119911.3-119926.6" + attribute \src "libresoc.v:119987.3-120002.6" wire $1\dec58_inv_a[0:0] - attribute \src "libresoc.v:119927.3-119942.6" + attribute \src "libresoc.v:120003.3-120018.6" wire $1\dec58_inv_out[0:0] - attribute \src "libresoc.v:120023.3-120038.6" + attribute \src "libresoc.v:120099.3-120114.6" wire $1\dec58_is_32b[0:0] - attribute \src "libresoc.v:119815.3-119830.6" + attribute \src "libresoc.v:119891.3-119906.6" wire width 4 $1\dec58_ldst_len[3:0] - attribute \src "libresoc.v:120055.3-120070.6" + attribute \src "libresoc.v:120131.3-120146.6" wire $1\dec58_lk[0:0] - attribute \src "libresoc.v:120167.3-120182.6" + attribute \src "libresoc.v:120243.3-120258.6" wire width 3 $1\dec58_out_sel[2:0] - attribute \src "libresoc.v:119863.3-119878.6" + attribute \src "libresoc.v:119939.3-119954.6" wire width 2 $1\dec58_rc_sel[1:0] - attribute \src "libresoc.v:119991.3-120006.6" + attribute \src "libresoc.v:120067.3-120082.6" wire $1\dec58_rsrv[0:0] - attribute \src "libresoc.v:120071.3-120086.6" + attribute \src "libresoc.v:120147.3-120162.6" wire $1\dec58_sgl_pipe[0:0] - attribute \src "libresoc.v:120039.3-120054.6" + attribute \src "libresoc.v:120115.3-120130.6" wire $1\dec58_sgn[0:0] - attribute \src "libresoc.v:119975.3-119990.6" + attribute \src "libresoc.v:120051.3-120066.6" wire $1\dec58_sgn_ext[0:0] - attribute \src "libresoc.v:119783.3-119798.6" + attribute \src "libresoc.v:119859.3-119874.6" wire width 3 $1\dec58_sv_cr_in[2:0] - attribute \src "libresoc.v:119799.3-119814.6" + attribute \src "libresoc.v:119875.3-119890.6" wire width 3 $1\dec58_sv_cr_out[2:0] - attribute \src "libresoc.v:119703.3-119718.6" + attribute \src "libresoc.v:119779.3-119794.6" wire width 3 $1\dec58_sv_in1[2:0] - attribute \src "libresoc.v:119719.3-119734.6" + attribute \src "libresoc.v:119795.3-119810.6" wire width 3 $1\dec58_sv_in2[2:0] - attribute \src "libresoc.v:119735.3-119750.6" + attribute \src "libresoc.v:119811.3-119826.6" wire width 3 $1\dec58_sv_in3[2:0] - attribute \src "libresoc.v:119767.3-119782.6" + attribute \src "libresoc.v:119843.3-119858.6" wire width 3 $1\dec58_sv_out2[2:0] - attribute \src "libresoc.v:119751.3-119766.6" + attribute \src "libresoc.v:119827.3-119842.6" wire width 3 $1\dec58_sv_out[2:0] - attribute \src "libresoc.v:119847.3-119862.6" + attribute \src "libresoc.v:119923.3-119938.6" wire width 2 $1\dec58_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -185998,28 +186061,28 @@ module \dec58 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec58_upd - attribute \src "libresoc.v:119307.7-119307.15" + attribute \src "libresoc.v:119383.7-119383.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 2 \opcode_switch - attribute \src "libresoc.v:119307.7-119307.20" - process $proc$libresoc.v:119307$4496 + attribute \src "libresoc.v:119383.7-119383.20" + process $proc$libresoc.v:119383$4496 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:119655.3-119670.6" - process $proc$libresoc.v:119655$4463 + attribute \src "libresoc.v:119731.3-119746.6" + process $proc$libresoc.v:119731$4463 assign { } { } assign { } { } assign $0\dec58_function_unit[13:0] $1\dec58_function_unit[13:0] - attribute \src "libresoc.v:119656.5-119656.29" + attribute \src "libresoc.v:119732.5-119732.29" switch \initial - attribute \src "libresoc.v:119656.9-119656.17" + attribute \src "libresoc.v:119732.9-119732.17" case 1'1 case end @@ -186043,14 +186106,14 @@ module \dec58 sync always update \dec58_function_unit $0\dec58_function_unit[13:0] end - attribute \src "libresoc.v:119671.3-119686.6" - process $proc$libresoc.v:119671$4464 + attribute \src "libresoc.v:119747.3-119762.6" + process $proc$libresoc.v:119747$4464 assign { } { } assign { } { } assign $0\dec58_cr_in[2:0] $1\dec58_cr_in[2:0] - attribute \src "libresoc.v:119672.5-119672.29" + attribute \src "libresoc.v:119748.5-119748.29" switch \initial - attribute \src "libresoc.v:119672.9-119672.17" + attribute \src "libresoc.v:119748.9-119748.17" case 1'1 case end @@ -186074,14 +186137,14 @@ module \dec58 sync always update \dec58_cr_in $0\dec58_cr_in[2:0] end - attribute \src "libresoc.v:119687.3-119702.6" - process $proc$libresoc.v:119687$4465 + attribute \src "libresoc.v:119763.3-119778.6" + process $proc$libresoc.v:119763$4465 assign { } { } assign { } { } assign $0\dec58_cr_out[2:0] $1\dec58_cr_out[2:0] - attribute \src "libresoc.v:119688.5-119688.29" + attribute \src "libresoc.v:119764.5-119764.29" switch \initial - attribute \src "libresoc.v:119688.9-119688.17" + attribute \src "libresoc.v:119764.9-119764.17" case 1'1 case end @@ -186105,14 +186168,14 @@ module \dec58 sync always update \dec58_cr_out $0\dec58_cr_out[2:0] end - attribute \src "libresoc.v:119703.3-119718.6" - process $proc$libresoc.v:119703$4466 + attribute \src "libresoc.v:119779.3-119794.6" + process $proc$libresoc.v:119779$4466 assign { } { } assign { } { } assign $0\dec58_sv_in1[2:0] $1\dec58_sv_in1[2:0] - attribute \src "libresoc.v:119704.5-119704.29" + attribute \src "libresoc.v:119780.5-119780.29" switch \initial - attribute \src "libresoc.v:119704.9-119704.17" + attribute \src "libresoc.v:119780.9-119780.17" case 1'1 case end @@ -186136,14 +186199,14 @@ module \dec58 sync always update \dec58_sv_in1 $0\dec58_sv_in1[2:0] end - attribute \src "libresoc.v:119719.3-119734.6" - process $proc$libresoc.v:119719$4467 + attribute \src "libresoc.v:119795.3-119810.6" + process $proc$libresoc.v:119795$4467 assign { } { } assign { } { } assign $0\dec58_sv_in2[2:0] $1\dec58_sv_in2[2:0] - attribute \src "libresoc.v:119720.5-119720.29" + attribute \src "libresoc.v:119796.5-119796.29" switch \initial - attribute \src "libresoc.v:119720.9-119720.17" + attribute \src "libresoc.v:119796.9-119796.17" case 1'1 case end @@ -186167,14 +186230,14 @@ module \dec58 sync always update \dec58_sv_in2 $0\dec58_sv_in2[2:0] end - attribute \src "libresoc.v:119735.3-119750.6" - process $proc$libresoc.v:119735$4468 + attribute \src "libresoc.v:119811.3-119826.6" + process $proc$libresoc.v:119811$4468 assign { } { } assign { } { } assign $0\dec58_sv_in3[2:0] $1\dec58_sv_in3[2:0] - attribute \src "libresoc.v:119736.5-119736.29" + attribute \src "libresoc.v:119812.5-119812.29" switch \initial - attribute \src "libresoc.v:119736.9-119736.17" + attribute \src "libresoc.v:119812.9-119812.17" case 1'1 case end @@ -186198,14 +186261,14 @@ module \dec58 sync always update \dec58_sv_in3 $0\dec58_sv_in3[2:0] end - attribute \src "libresoc.v:119751.3-119766.6" - process $proc$libresoc.v:119751$4469 + attribute \src "libresoc.v:119827.3-119842.6" + process $proc$libresoc.v:119827$4469 assign { } { } assign { } { } assign $0\dec58_sv_out[2:0] $1\dec58_sv_out[2:0] - attribute \src "libresoc.v:119752.5-119752.29" + attribute \src "libresoc.v:119828.5-119828.29" switch \initial - attribute \src "libresoc.v:119752.9-119752.17" + attribute \src "libresoc.v:119828.9-119828.17" case 1'1 case end @@ -186229,14 +186292,14 @@ module \dec58 sync always update \dec58_sv_out $0\dec58_sv_out[2:0] end - attribute \src "libresoc.v:119767.3-119782.6" - process $proc$libresoc.v:119767$4470 + attribute \src "libresoc.v:119843.3-119858.6" + process $proc$libresoc.v:119843$4470 assign { } { } assign { } { } assign $0\dec58_sv_out2[2:0] $1\dec58_sv_out2[2:0] - attribute \src "libresoc.v:119768.5-119768.29" + attribute \src "libresoc.v:119844.5-119844.29" switch \initial - attribute \src "libresoc.v:119768.9-119768.17" + attribute \src "libresoc.v:119844.9-119844.17" case 1'1 case end @@ -186260,14 +186323,14 @@ module \dec58 sync always update \dec58_sv_out2 $0\dec58_sv_out2[2:0] end - attribute \src "libresoc.v:119783.3-119798.6" - process $proc$libresoc.v:119783$4471 + attribute \src "libresoc.v:119859.3-119874.6" + process $proc$libresoc.v:119859$4471 assign { } { } assign { } { } assign $0\dec58_sv_cr_in[2:0] $1\dec58_sv_cr_in[2:0] - attribute \src "libresoc.v:119784.5-119784.29" + attribute \src "libresoc.v:119860.5-119860.29" switch \initial - attribute \src "libresoc.v:119784.9-119784.17" + attribute \src "libresoc.v:119860.9-119860.17" case 1'1 case end @@ -186291,14 +186354,14 @@ module \dec58 sync always update \dec58_sv_cr_in $0\dec58_sv_cr_in[2:0] end - attribute \src "libresoc.v:119799.3-119814.6" - process $proc$libresoc.v:119799$4472 + attribute \src "libresoc.v:119875.3-119890.6" + process $proc$libresoc.v:119875$4472 assign { } { } assign { } { } assign $0\dec58_sv_cr_out[2:0] $1\dec58_sv_cr_out[2:0] - attribute \src "libresoc.v:119800.5-119800.29" + attribute \src "libresoc.v:119876.5-119876.29" switch \initial - attribute \src "libresoc.v:119800.9-119800.17" + attribute \src "libresoc.v:119876.9-119876.17" case 1'1 case end @@ -186322,14 +186385,14 @@ module \dec58 sync always update \dec58_sv_cr_out $0\dec58_sv_cr_out[2:0] end - attribute \src "libresoc.v:119815.3-119830.6" - process $proc$libresoc.v:119815$4473 + attribute \src "libresoc.v:119891.3-119906.6" + process $proc$libresoc.v:119891$4473 assign { } { } assign { } { } assign $0\dec58_ldst_len[3:0] $1\dec58_ldst_len[3:0] - attribute \src "libresoc.v:119816.5-119816.29" + attribute \src "libresoc.v:119892.5-119892.29" switch \initial - attribute \src "libresoc.v:119816.9-119816.17" + attribute \src "libresoc.v:119892.9-119892.17" case 1'1 case end @@ -186353,14 +186416,14 @@ module \dec58 sync always update \dec58_ldst_len $0\dec58_ldst_len[3:0] end - attribute \src "libresoc.v:119831.3-119846.6" - process $proc$libresoc.v:119831$4474 + attribute \src "libresoc.v:119907.3-119922.6" + process $proc$libresoc.v:119907$4474 assign { } { } assign { } { } assign $0\dec58_internal_op[6:0] $1\dec58_internal_op[6:0] - attribute \src "libresoc.v:119832.5-119832.29" + attribute \src "libresoc.v:119908.5-119908.29" switch \initial - attribute \src "libresoc.v:119832.9-119832.17" + attribute \src "libresoc.v:119908.9-119908.17" case 1'1 case end @@ -186384,14 +186447,14 @@ module \dec58 sync always update \dec58_internal_op $0\dec58_internal_op[6:0] end - attribute \src "libresoc.v:119847.3-119862.6" - process $proc$libresoc.v:119847$4475 + attribute \src "libresoc.v:119923.3-119938.6" + process $proc$libresoc.v:119923$4475 assign { } { } assign { } { } assign $0\dec58_upd[1:0] $1\dec58_upd[1:0] - attribute \src "libresoc.v:119848.5-119848.29" + attribute \src "libresoc.v:119924.5-119924.29" switch \initial - attribute \src "libresoc.v:119848.9-119848.17" + attribute \src "libresoc.v:119924.9-119924.17" case 1'1 case end @@ -186415,14 +186478,14 @@ module \dec58 sync always update \dec58_upd $0\dec58_upd[1:0] end - attribute \src "libresoc.v:119863.3-119878.6" - process $proc$libresoc.v:119863$4476 + attribute \src "libresoc.v:119939.3-119954.6" + process $proc$libresoc.v:119939$4476 assign { } { } assign { } { } assign $0\dec58_rc_sel[1:0] $1\dec58_rc_sel[1:0] - attribute \src "libresoc.v:119864.5-119864.29" + attribute \src "libresoc.v:119940.5-119940.29" switch \initial - attribute \src "libresoc.v:119864.9-119864.17" + attribute \src "libresoc.v:119940.9-119940.17" case 1'1 case end @@ -186446,14 +186509,14 @@ module \dec58 sync always update \dec58_rc_sel $0\dec58_rc_sel[1:0] end - attribute \src "libresoc.v:119879.3-119894.6" - process $proc$libresoc.v:119879$4477 + attribute \src "libresoc.v:119955.3-119970.6" + process $proc$libresoc.v:119955$4477 assign { } { } assign { } { } assign $0\dec58_cry_in[1:0] $1\dec58_cry_in[1:0] - attribute \src "libresoc.v:119880.5-119880.29" + attribute \src "libresoc.v:119956.5-119956.29" switch \initial - attribute \src "libresoc.v:119880.9-119880.17" + attribute \src "libresoc.v:119956.9-119956.17" case 1'1 case end @@ -186477,14 +186540,14 @@ module \dec58 sync always update \dec58_cry_in $0\dec58_cry_in[1:0] end - attribute \src "libresoc.v:119895.3-119910.6" - process $proc$libresoc.v:119895$4478 + attribute \src "libresoc.v:119971.3-119986.6" + process $proc$libresoc.v:119971$4478 assign { } { } assign { } { } assign $0\dec58_asmcode[7:0] $1\dec58_asmcode[7:0] - attribute \src "libresoc.v:119896.5-119896.29" + attribute \src "libresoc.v:119972.5-119972.29" switch \initial - attribute \src "libresoc.v:119896.9-119896.17" + attribute \src "libresoc.v:119972.9-119972.17" case 1'1 case end @@ -186508,14 +186571,14 @@ module \dec58 sync always update \dec58_asmcode $0\dec58_asmcode[7:0] end - attribute \src "libresoc.v:119911.3-119926.6" - process $proc$libresoc.v:119911$4479 + attribute \src "libresoc.v:119987.3-120002.6" + process $proc$libresoc.v:119987$4479 assign { } { } assign { } { } assign $0\dec58_inv_a[0:0] $1\dec58_inv_a[0:0] - attribute \src "libresoc.v:119912.5-119912.29" + attribute \src "libresoc.v:119988.5-119988.29" switch \initial - attribute \src "libresoc.v:119912.9-119912.17" + attribute \src "libresoc.v:119988.9-119988.17" case 1'1 case end @@ -186539,14 +186602,14 @@ module \dec58 sync always update \dec58_inv_a $0\dec58_inv_a[0:0] end - attribute \src "libresoc.v:119927.3-119942.6" - process $proc$libresoc.v:119927$4480 + attribute \src "libresoc.v:120003.3-120018.6" + process $proc$libresoc.v:120003$4480 assign { } { } assign { } { } assign $0\dec58_inv_out[0:0] $1\dec58_inv_out[0:0] - attribute \src "libresoc.v:119928.5-119928.29" + attribute \src "libresoc.v:120004.5-120004.29" switch \initial - attribute \src "libresoc.v:119928.9-119928.17" + attribute \src "libresoc.v:120004.9-120004.17" case 1'1 case end @@ -186570,14 +186633,14 @@ module \dec58 sync always update \dec58_inv_out $0\dec58_inv_out[0:0] end - attribute \src "libresoc.v:119943.3-119958.6" - process $proc$libresoc.v:119943$4481 + attribute \src "libresoc.v:120019.3-120034.6" + process $proc$libresoc.v:120019$4481 assign { } { } assign { } { } assign $0\dec58_cry_out[0:0] $1\dec58_cry_out[0:0] - attribute \src "libresoc.v:119944.5-119944.29" + attribute \src "libresoc.v:120020.5-120020.29" switch \initial - attribute \src "libresoc.v:119944.9-119944.17" + attribute \src "libresoc.v:120020.9-120020.17" case 1'1 case end @@ -186601,14 +186664,14 @@ module \dec58 sync always update \dec58_cry_out $0\dec58_cry_out[0:0] end - attribute \src "libresoc.v:119959.3-119974.6" - process $proc$libresoc.v:119959$4482 + attribute \src "libresoc.v:120035.3-120050.6" + process $proc$libresoc.v:120035$4482 assign { } { } assign { } { } assign $0\dec58_br[0:0] $1\dec58_br[0:0] - attribute \src "libresoc.v:119960.5-119960.29" + attribute \src "libresoc.v:120036.5-120036.29" switch \initial - attribute \src "libresoc.v:119960.9-119960.17" + attribute \src "libresoc.v:120036.9-120036.17" case 1'1 case end @@ -186632,14 +186695,14 @@ module \dec58 sync always update \dec58_br $0\dec58_br[0:0] end - attribute \src "libresoc.v:119975.3-119990.6" - process $proc$libresoc.v:119975$4483 + attribute \src "libresoc.v:120051.3-120066.6" + process $proc$libresoc.v:120051$4483 assign { } { } assign { } { } assign $0\dec58_sgn_ext[0:0] $1\dec58_sgn_ext[0:0] - attribute \src "libresoc.v:119976.5-119976.29" + attribute \src "libresoc.v:120052.5-120052.29" switch \initial - attribute \src "libresoc.v:119976.9-119976.17" + attribute \src "libresoc.v:120052.9-120052.17" case 1'1 case end @@ -186663,14 +186726,14 @@ module \dec58 sync always update \dec58_sgn_ext $0\dec58_sgn_ext[0:0] end - attribute \src "libresoc.v:119991.3-120006.6" - process $proc$libresoc.v:119991$4484 + attribute \src "libresoc.v:120067.3-120082.6" + process $proc$libresoc.v:120067$4484 assign { } { } assign { } { } assign $0\dec58_rsrv[0:0] $1\dec58_rsrv[0:0] - attribute \src "libresoc.v:119992.5-119992.29" + attribute \src "libresoc.v:120068.5-120068.29" switch \initial - attribute \src "libresoc.v:119992.9-119992.17" + attribute \src "libresoc.v:120068.9-120068.17" case 1'1 case end @@ -186694,14 +186757,14 @@ module \dec58 sync always update \dec58_rsrv $0\dec58_rsrv[0:0] end - attribute \src "libresoc.v:120007.3-120022.6" - process $proc$libresoc.v:120007$4485 + attribute \src "libresoc.v:120083.3-120098.6" + process $proc$libresoc.v:120083$4485 assign { } { } assign { } { } assign $0\dec58_form[4:0] $1\dec58_form[4:0] - attribute \src "libresoc.v:120008.5-120008.29" + attribute \src "libresoc.v:120084.5-120084.29" switch \initial - attribute \src "libresoc.v:120008.9-120008.17" + attribute \src "libresoc.v:120084.9-120084.17" case 1'1 case end @@ -186725,14 +186788,14 @@ module \dec58 sync always update \dec58_form $0\dec58_form[4:0] end - attribute \src "libresoc.v:120023.3-120038.6" - process $proc$libresoc.v:120023$4486 + attribute \src "libresoc.v:120099.3-120114.6" + process $proc$libresoc.v:120099$4486 assign { } { } assign { } { } assign $0\dec58_is_32b[0:0] $1\dec58_is_32b[0:0] - attribute \src "libresoc.v:120024.5-120024.29" + attribute \src "libresoc.v:120100.5-120100.29" switch \initial - attribute \src "libresoc.v:120024.9-120024.17" + attribute \src "libresoc.v:120100.9-120100.17" case 1'1 case end @@ -186756,14 +186819,14 @@ module \dec58 sync always update \dec58_is_32b $0\dec58_is_32b[0:0] end - attribute \src "libresoc.v:120039.3-120054.6" - process $proc$libresoc.v:120039$4487 + attribute \src "libresoc.v:120115.3-120130.6" + process $proc$libresoc.v:120115$4487 assign { } { } assign { } { } assign $0\dec58_sgn[0:0] $1\dec58_sgn[0:0] - attribute \src "libresoc.v:120040.5-120040.29" + attribute \src "libresoc.v:120116.5-120116.29" switch \initial - attribute \src "libresoc.v:120040.9-120040.17" + attribute \src "libresoc.v:120116.9-120116.17" case 1'1 case end @@ -186787,14 +186850,14 @@ module \dec58 sync always update \dec58_sgn $0\dec58_sgn[0:0] end - attribute \src "libresoc.v:120055.3-120070.6" - process $proc$libresoc.v:120055$4488 + attribute \src "libresoc.v:120131.3-120146.6" + process $proc$libresoc.v:120131$4488 assign { } { } assign { } { } assign $0\dec58_lk[0:0] $1\dec58_lk[0:0] - attribute \src "libresoc.v:120056.5-120056.29" + attribute \src "libresoc.v:120132.5-120132.29" switch \initial - attribute \src "libresoc.v:120056.9-120056.17" + attribute \src "libresoc.v:120132.9-120132.17" case 1'1 case end @@ -186818,14 +186881,14 @@ module \dec58 sync always update \dec58_lk $0\dec58_lk[0:0] end - attribute \src "libresoc.v:120071.3-120086.6" - process $proc$libresoc.v:120071$4489 + attribute \src "libresoc.v:120147.3-120162.6" + process $proc$libresoc.v:120147$4489 assign { } { } assign { } { } assign $0\dec58_sgl_pipe[0:0] $1\dec58_sgl_pipe[0:0] - attribute \src "libresoc.v:120072.5-120072.29" + attribute \src "libresoc.v:120148.5-120148.29" switch \initial - attribute \src "libresoc.v:120072.9-120072.17" + attribute \src "libresoc.v:120148.9-120148.17" case 1'1 case end @@ -186849,14 +186912,14 @@ module \dec58 sync always update \dec58_sgl_pipe $0\dec58_sgl_pipe[0:0] end - attribute \src "libresoc.v:120087.3-120102.6" - process $proc$libresoc.v:120087$4490 + attribute \src "libresoc.v:120163.3-120178.6" + process $proc$libresoc.v:120163$4490 assign { } { } assign { } { } assign $0\dec58_SV_Etype[1:0] $1\dec58_SV_Etype[1:0] - attribute \src "libresoc.v:120088.5-120088.29" + attribute \src "libresoc.v:120164.5-120164.29" switch \initial - attribute \src "libresoc.v:120088.9-120088.17" + attribute \src "libresoc.v:120164.9-120164.17" case 1'1 case end @@ -186880,14 +186943,14 @@ module \dec58 sync always update \dec58_SV_Etype $0\dec58_SV_Etype[1:0] end - attribute \src "libresoc.v:120103.3-120118.6" - process $proc$libresoc.v:120103$4491 + attribute \src "libresoc.v:120179.3-120194.6" + process $proc$libresoc.v:120179$4491 assign { } { } assign { } { } assign $0\dec58_SV_Ptype[1:0] $1\dec58_SV_Ptype[1:0] - attribute \src "libresoc.v:120104.5-120104.29" + attribute \src "libresoc.v:120180.5-120180.29" switch \initial - attribute \src "libresoc.v:120104.9-120104.17" + attribute \src "libresoc.v:120180.9-120180.17" case 1'1 case end @@ -186911,14 +186974,14 @@ module \dec58 sync always update \dec58_SV_Ptype $0\dec58_SV_Ptype[1:0] end - attribute \src "libresoc.v:120119.3-120134.6" - process $proc$libresoc.v:120119$4492 + attribute \src "libresoc.v:120195.3-120210.6" + process $proc$libresoc.v:120195$4492 assign { } { } assign { } { } assign $0\dec58_in1_sel[2:0] $1\dec58_in1_sel[2:0] - attribute \src "libresoc.v:120120.5-120120.29" + attribute \src "libresoc.v:120196.5-120196.29" switch \initial - attribute \src "libresoc.v:120120.9-120120.17" + attribute \src "libresoc.v:120196.9-120196.17" case 1'1 case end @@ -186942,14 +187005,14 @@ module \dec58 sync always update \dec58_in1_sel $0\dec58_in1_sel[2:0] end - attribute \src "libresoc.v:120135.3-120150.6" - process $proc$libresoc.v:120135$4493 + attribute \src "libresoc.v:120211.3-120226.6" + process $proc$libresoc.v:120211$4493 assign { } { } assign { } { } assign $0\dec58_in2_sel[3:0] $1\dec58_in2_sel[3:0] - attribute \src "libresoc.v:120136.5-120136.29" + attribute \src "libresoc.v:120212.5-120212.29" switch \initial - attribute \src "libresoc.v:120136.9-120136.17" + attribute \src "libresoc.v:120212.9-120212.17" case 1'1 case end @@ -186973,14 +187036,14 @@ module \dec58 sync always update \dec58_in2_sel $0\dec58_in2_sel[3:0] end - attribute \src "libresoc.v:120151.3-120166.6" - process $proc$libresoc.v:120151$4494 + attribute \src "libresoc.v:120227.3-120242.6" + process $proc$libresoc.v:120227$4494 assign { } { } assign { } { } assign $0\dec58_in3_sel[1:0] $1\dec58_in3_sel[1:0] - attribute \src "libresoc.v:120152.5-120152.29" + attribute \src "libresoc.v:120228.5-120228.29" switch \initial - attribute \src "libresoc.v:120152.9-120152.17" + attribute \src "libresoc.v:120228.9-120228.17" case 1'1 case end @@ -187004,14 +187067,14 @@ module \dec58 sync always update \dec58_in3_sel $0\dec58_in3_sel[1:0] end - attribute \src "libresoc.v:120167.3-120182.6" - process $proc$libresoc.v:120167$4495 + attribute \src "libresoc.v:120243.3-120258.6" + process $proc$libresoc.v:120243$4495 assign { } { } assign { } { } assign $0\dec58_out_sel[2:0] $1\dec58_out_sel[2:0] - attribute \src "libresoc.v:120168.5-120168.29" + attribute \src "libresoc.v:120244.5-120244.29" switch \initial - attribute \src "libresoc.v:120168.9-120168.17" + attribute \src "libresoc.v:120244.9-120244.17" case 1'1 case end @@ -187037,144 +187100,144 @@ module \dec58 end connect \opcode_switch \opcode_in [1:0] end -attribute \src "libresoc.v:120188.1-120967.10" +attribute \src "libresoc.v:120264.1-121043.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec.dec62" attribute \generator "nMigen" module \dec62 - attribute \src "libresoc.v:120888.3-120900.6" + attribute \src "libresoc.v:120964.3-120976.6" wire width 2 $0\dec62_SV_Etype[1:0] - attribute \src "libresoc.v:120901.3-120913.6" + attribute \src "libresoc.v:120977.3-120989.6" wire width 2 $0\dec62_SV_Ptype[1:0] - attribute \src "libresoc.v:120732.3-120744.6" + attribute \src "libresoc.v:120808.3-120820.6" wire width 8 $0\dec62_asmcode[7:0] - attribute \src "libresoc.v:120784.3-120796.6" + attribute \src "libresoc.v:120860.3-120872.6" wire $0\dec62_br[0:0] - attribute \src "libresoc.v:120550.3-120562.6" + attribute \src "libresoc.v:120626.3-120638.6" wire width 3 $0\dec62_cr_in[2:0] - attribute \src "libresoc.v:120563.3-120575.6" + attribute \src "libresoc.v:120639.3-120651.6" wire width 3 $0\dec62_cr_out[2:0] - attribute \src "libresoc.v:120719.3-120731.6" + attribute \src "libresoc.v:120795.3-120807.6" wire width 2 $0\dec62_cry_in[1:0] - attribute \src "libresoc.v:120771.3-120783.6" + attribute \src "libresoc.v:120847.3-120859.6" wire $0\dec62_cry_out[0:0] - attribute \src "libresoc.v:120823.3-120835.6" + attribute \src "libresoc.v:120899.3-120911.6" wire width 5 $0\dec62_form[4:0] - attribute \src "libresoc.v:120537.3-120549.6" + attribute \src "libresoc.v:120613.3-120625.6" wire width 14 $0\dec62_function_unit[13:0] - attribute \src "libresoc.v:120914.3-120926.6" + attribute \src "libresoc.v:120990.3-121002.6" wire width 3 $0\dec62_in1_sel[2:0] - attribute \src "libresoc.v:120927.3-120939.6" + attribute \src "libresoc.v:121003.3-121015.6" wire width 4 $0\dec62_in2_sel[3:0] - attribute \src "libresoc.v:120940.3-120952.6" + attribute \src "libresoc.v:121016.3-121028.6" wire width 2 $0\dec62_in3_sel[1:0] - attribute \src "libresoc.v:120680.3-120692.6" + attribute \src "libresoc.v:120756.3-120768.6" wire width 7 $0\dec62_internal_op[6:0] - attribute \src "libresoc.v:120745.3-120757.6" + attribute \src "libresoc.v:120821.3-120833.6" wire $0\dec62_inv_a[0:0] - attribute \src "libresoc.v:120758.3-120770.6" + attribute \src "libresoc.v:120834.3-120846.6" wire $0\dec62_inv_out[0:0] - attribute \src "libresoc.v:120836.3-120848.6" + attribute \src "libresoc.v:120912.3-120924.6" wire $0\dec62_is_32b[0:0] - attribute \src "libresoc.v:120667.3-120679.6" + attribute \src "libresoc.v:120743.3-120755.6" wire width 4 $0\dec62_ldst_len[3:0] - attribute \src "libresoc.v:120862.3-120874.6" + attribute \src "libresoc.v:120938.3-120950.6" wire $0\dec62_lk[0:0] - attribute \src "libresoc.v:120953.3-120965.6" + attribute \src "libresoc.v:121029.3-121041.6" wire width 3 $0\dec62_out_sel[2:0] - attribute \src "libresoc.v:120706.3-120718.6" + attribute \src "libresoc.v:120782.3-120794.6" wire width 2 $0\dec62_rc_sel[1:0] - attribute \src "libresoc.v:120810.3-120822.6" + attribute \src "libresoc.v:120886.3-120898.6" wire $0\dec62_rsrv[0:0] - attribute \src "libresoc.v:120875.3-120887.6" + attribute \src "libresoc.v:120951.3-120963.6" wire $0\dec62_sgl_pipe[0:0] - attribute \src "libresoc.v:120849.3-120861.6" + attribute \src "libresoc.v:120925.3-120937.6" wire $0\dec62_sgn[0:0] - attribute \src "libresoc.v:120797.3-120809.6" + attribute \src "libresoc.v:120873.3-120885.6" wire $0\dec62_sgn_ext[0:0] - attribute \src "libresoc.v:120641.3-120653.6" + attribute \src "libresoc.v:120717.3-120729.6" wire width 3 $0\dec62_sv_cr_in[2:0] - attribute \src "libresoc.v:120654.3-120666.6" + attribute \src "libresoc.v:120730.3-120742.6" wire width 3 $0\dec62_sv_cr_out[2:0] - attribute \src "libresoc.v:120576.3-120588.6" + attribute \src "libresoc.v:120652.3-120664.6" wire width 3 $0\dec62_sv_in1[2:0] - attribute \src "libresoc.v:120589.3-120601.6" + attribute \src "libresoc.v:120665.3-120677.6" wire width 3 $0\dec62_sv_in2[2:0] - attribute \src "libresoc.v:120602.3-120614.6" + attribute \src "libresoc.v:120678.3-120690.6" wire width 3 $0\dec62_sv_in3[2:0] - attribute \src "libresoc.v:120628.3-120640.6" + attribute \src "libresoc.v:120704.3-120716.6" wire width 3 $0\dec62_sv_out2[2:0] - attribute \src "libresoc.v:120615.3-120627.6" + attribute \src "libresoc.v:120691.3-120703.6" wire width 3 $0\dec62_sv_out[2:0] - attribute \src "libresoc.v:120693.3-120705.6" + attribute \src "libresoc.v:120769.3-120781.6" wire width 2 $0\dec62_upd[1:0] - attribute \src "libresoc.v:120189.7-120189.20" + attribute \src "libresoc.v:120265.7-120265.20" wire $0\initial[0:0] - attribute \src "libresoc.v:120888.3-120900.6" + attribute \src "libresoc.v:120964.3-120976.6" wire width 2 $1\dec62_SV_Etype[1:0] - attribute \src "libresoc.v:120901.3-120913.6" + attribute \src "libresoc.v:120977.3-120989.6" wire width 2 $1\dec62_SV_Ptype[1:0] - attribute \src "libresoc.v:120732.3-120744.6" + attribute \src "libresoc.v:120808.3-120820.6" wire width 8 $1\dec62_asmcode[7:0] - attribute \src "libresoc.v:120784.3-120796.6" + attribute \src "libresoc.v:120860.3-120872.6" wire $1\dec62_br[0:0] - attribute \src "libresoc.v:120550.3-120562.6" + attribute \src "libresoc.v:120626.3-120638.6" wire width 3 $1\dec62_cr_in[2:0] - attribute \src "libresoc.v:120563.3-120575.6" + attribute \src "libresoc.v:120639.3-120651.6" wire width 3 $1\dec62_cr_out[2:0] - attribute \src "libresoc.v:120719.3-120731.6" + attribute \src "libresoc.v:120795.3-120807.6" wire width 2 $1\dec62_cry_in[1:0] - attribute \src "libresoc.v:120771.3-120783.6" + attribute \src "libresoc.v:120847.3-120859.6" wire $1\dec62_cry_out[0:0] - attribute \src "libresoc.v:120823.3-120835.6" + attribute \src "libresoc.v:120899.3-120911.6" wire width 5 $1\dec62_form[4:0] - attribute \src "libresoc.v:120537.3-120549.6" + attribute \src "libresoc.v:120613.3-120625.6" wire width 14 $1\dec62_function_unit[13:0] - attribute \src "libresoc.v:120914.3-120926.6" + attribute \src "libresoc.v:120990.3-121002.6" wire width 3 $1\dec62_in1_sel[2:0] - attribute \src "libresoc.v:120927.3-120939.6" + attribute \src "libresoc.v:121003.3-121015.6" wire width 4 $1\dec62_in2_sel[3:0] - attribute \src "libresoc.v:120940.3-120952.6" + attribute \src "libresoc.v:121016.3-121028.6" wire width 2 $1\dec62_in3_sel[1:0] - attribute \src "libresoc.v:120680.3-120692.6" + attribute \src "libresoc.v:120756.3-120768.6" wire width 7 $1\dec62_internal_op[6:0] - attribute \src "libresoc.v:120745.3-120757.6" + attribute \src "libresoc.v:120821.3-120833.6" wire $1\dec62_inv_a[0:0] - attribute \src "libresoc.v:120758.3-120770.6" + attribute \src "libresoc.v:120834.3-120846.6" wire $1\dec62_inv_out[0:0] - attribute \src "libresoc.v:120836.3-120848.6" + attribute \src "libresoc.v:120912.3-120924.6" wire $1\dec62_is_32b[0:0] - attribute \src "libresoc.v:120667.3-120679.6" + attribute \src "libresoc.v:120743.3-120755.6" wire width 4 $1\dec62_ldst_len[3:0] - attribute \src "libresoc.v:120862.3-120874.6" + attribute \src "libresoc.v:120938.3-120950.6" wire $1\dec62_lk[0:0] - attribute \src "libresoc.v:120953.3-120965.6" + attribute \src "libresoc.v:121029.3-121041.6" wire width 3 $1\dec62_out_sel[2:0] - attribute \src "libresoc.v:120706.3-120718.6" + attribute \src "libresoc.v:120782.3-120794.6" wire width 2 $1\dec62_rc_sel[1:0] - attribute \src "libresoc.v:120810.3-120822.6" + attribute \src "libresoc.v:120886.3-120898.6" wire $1\dec62_rsrv[0:0] - attribute \src "libresoc.v:120875.3-120887.6" + attribute \src "libresoc.v:120951.3-120963.6" wire $1\dec62_sgl_pipe[0:0] - attribute \src "libresoc.v:120849.3-120861.6" + attribute \src "libresoc.v:120925.3-120937.6" wire $1\dec62_sgn[0:0] - attribute \src "libresoc.v:120797.3-120809.6" + attribute \src "libresoc.v:120873.3-120885.6" wire $1\dec62_sgn_ext[0:0] - attribute \src "libresoc.v:120641.3-120653.6" + attribute \src "libresoc.v:120717.3-120729.6" wire width 3 $1\dec62_sv_cr_in[2:0] - attribute \src "libresoc.v:120654.3-120666.6" + attribute \src "libresoc.v:120730.3-120742.6" wire width 3 $1\dec62_sv_cr_out[2:0] - attribute \src "libresoc.v:120576.3-120588.6" + attribute \src "libresoc.v:120652.3-120664.6" wire width 3 $1\dec62_sv_in1[2:0] - attribute \src "libresoc.v:120589.3-120601.6" + attribute \src "libresoc.v:120665.3-120677.6" wire width 3 $1\dec62_sv_in2[2:0] - attribute \src "libresoc.v:120602.3-120614.6" + attribute \src "libresoc.v:120678.3-120690.6" wire width 3 $1\dec62_sv_in3[2:0] - attribute \src "libresoc.v:120628.3-120640.6" + attribute \src "libresoc.v:120704.3-120716.6" wire width 3 $1\dec62_sv_out2[2:0] - attribute \src "libresoc.v:120615.3-120627.6" + attribute \src "libresoc.v:120691.3-120703.6" wire width 3 $1\dec62_sv_out[2:0] - attribute \src "libresoc.v:120693.3-120705.6" + attribute \src "libresoc.v:120769.3-120781.6" wire width 2 $1\dec62_upd[1:0] attribute \enum_base_type "SVEtype" attribute \enum_value_00 "NONE" @@ -187486,28 +187549,28 @@ module \dec62 attribute \enum_value_11 "cx" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 output 21 \dec62_upd - attribute \src "libresoc.v:120189.7-120189.15" + attribute \src "libresoc.v:120265.7-120265.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:305" wire width 32 input 34 \opcode_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:342" wire width 2 \opcode_switch - attribute \src "libresoc.v:120189.7-120189.20" - process $proc$libresoc.v:120189$4530 + attribute \src "libresoc.v:120265.7-120265.20" + process $proc$libresoc.v:120265$4530 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:120537.3-120549.6" - process $proc$libresoc.v:120537$4497 + attribute \src "libresoc.v:120613.3-120625.6" + process $proc$libresoc.v:120613$4497 assign { } { } assign { } { } assign $0\dec62_function_unit[13:0] $1\dec62_function_unit[13:0] - attribute \src "libresoc.v:120538.5-120538.29" + attribute \src "libresoc.v:120614.5-120614.29" switch \initial - attribute \src "libresoc.v:120538.9-120538.17" + attribute \src "libresoc.v:120614.9-120614.17" case 1'1 case end @@ -187527,14 +187590,14 @@ module \dec62 sync always update \dec62_function_unit $0\dec62_function_unit[13:0] end - attribute \src "libresoc.v:120550.3-120562.6" - process $proc$libresoc.v:120550$4498 + attribute \src "libresoc.v:120626.3-120638.6" + process $proc$libresoc.v:120626$4498 assign { } { } assign { } { } assign $0\dec62_cr_in[2:0] $1\dec62_cr_in[2:0] - attribute \src "libresoc.v:120551.5-120551.29" + attribute \src "libresoc.v:120627.5-120627.29" switch \initial - attribute \src "libresoc.v:120551.9-120551.17" + attribute \src "libresoc.v:120627.9-120627.17" case 1'1 case end @@ -187554,14 +187617,14 @@ module \dec62 sync always update \dec62_cr_in $0\dec62_cr_in[2:0] end - attribute \src "libresoc.v:120563.3-120575.6" - process $proc$libresoc.v:120563$4499 + attribute \src "libresoc.v:120639.3-120651.6" + process $proc$libresoc.v:120639$4499 assign { } { } assign { } { } assign $0\dec62_cr_out[2:0] $1\dec62_cr_out[2:0] - attribute \src "libresoc.v:120564.5-120564.29" + attribute \src "libresoc.v:120640.5-120640.29" switch \initial - attribute \src "libresoc.v:120564.9-120564.17" + attribute \src "libresoc.v:120640.9-120640.17" case 1'1 case end @@ -187581,14 +187644,14 @@ module \dec62 sync always update \dec62_cr_out $0\dec62_cr_out[2:0] end - attribute \src "libresoc.v:120576.3-120588.6" - process $proc$libresoc.v:120576$4500 + attribute \src "libresoc.v:120652.3-120664.6" + process $proc$libresoc.v:120652$4500 assign { } { } assign { } { } assign $0\dec62_sv_in1[2:0] $1\dec62_sv_in1[2:0] - attribute \src "libresoc.v:120577.5-120577.29" + attribute \src "libresoc.v:120653.5-120653.29" switch \initial - attribute \src "libresoc.v:120577.9-120577.17" + attribute \src "libresoc.v:120653.9-120653.17" case 1'1 case end @@ -187608,14 +187671,14 @@ module \dec62 sync always update \dec62_sv_in1 $0\dec62_sv_in1[2:0] end - attribute \src "libresoc.v:120589.3-120601.6" - process $proc$libresoc.v:120589$4501 + attribute \src "libresoc.v:120665.3-120677.6" + process $proc$libresoc.v:120665$4501 assign { } { } assign { } { } assign $0\dec62_sv_in2[2:0] $1\dec62_sv_in2[2:0] - attribute \src "libresoc.v:120590.5-120590.29" + attribute \src "libresoc.v:120666.5-120666.29" switch \initial - attribute \src "libresoc.v:120590.9-120590.17" + attribute \src "libresoc.v:120666.9-120666.17" case 1'1 case end @@ -187635,14 +187698,14 @@ module \dec62 sync always update \dec62_sv_in2 $0\dec62_sv_in2[2:0] end - attribute \src "libresoc.v:120602.3-120614.6" - process $proc$libresoc.v:120602$4502 + attribute \src "libresoc.v:120678.3-120690.6" + process $proc$libresoc.v:120678$4502 assign { } { } assign { } { } assign $0\dec62_sv_in3[2:0] $1\dec62_sv_in3[2:0] - attribute \src "libresoc.v:120603.5-120603.29" + attribute \src "libresoc.v:120679.5-120679.29" switch \initial - attribute \src "libresoc.v:120603.9-120603.17" + attribute \src "libresoc.v:120679.9-120679.17" case 1'1 case end @@ -187662,14 +187725,14 @@ module \dec62 sync always update \dec62_sv_in3 $0\dec62_sv_in3[2:0] end - attribute \src "libresoc.v:120615.3-120627.6" - process $proc$libresoc.v:120615$4503 + attribute \src "libresoc.v:120691.3-120703.6" + process $proc$libresoc.v:120691$4503 assign { } { } assign { } { } assign $0\dec62_sv_out[2:0] $1\dec62_sv_out[2:0] - attribute \src "libresoc.v:120616.5-120616.29" + attribute \src "libresoc.v:120692.5-120692.29" switch \initial - attribute \src "libresoc.v:120616.9-120616.17" + attribute \src "libresoc.v:120692.9-120692.17" case 1'1 case end @@ -187689,14 +187752,14 @@ module \dec62 sync always update \dec62_sv_out $0\dec62_sv_out[2:0] end - attribute \src "libresoc.v:120628.3-120640.6" - process $proc$libresoc.v:120628$4504 + attribute \src "libresoc.v:120704.3-120716.6" + process $proc$libresoc.v:120704$4504 assign { } { } assign { } { } assign $0\dec62_sv_out2[2:0] $1\dec62_sv_out2[2:0] - attribute \src "libresoc.v:120629.5-120629.29" + attribute \src "libresoc.v:120705.5-120705.29" switch \initial - attribute \src "libresoc.v:120629.9-120629.17" + attribute \src "libresoc.v:120705.9-120705.17" case 1'1 case end @@ -187716,14 +187779,14 @@ module \dec62 sync always update \dec62_sv_out2 $0\dec62_sv_out2[2:0] end - attribute \src "libresoc.v:120641.3-120653.6" - process $proc$libresoc.v:120641$4505 + attribute \src "libresoc.v:120717.3-120729.6" + process $proc$libresoc.v:120717$4505 assign { } { } assign { } { } assign $0\dec62_sv_cr_in[2:0] $1\dec62_sv_cr_in[2:0] - attribute \src "libresoc.v:120642.5-120642.29" + attribute \src "libresoc.v:120718.5-120718.29" switch \initial - attribute \src "libresoc.v:120642.9-120642.17" + attribute \src "libresoc.v:120718.9-120718.17" case 1'1 case end @@ -187743,14 +187806,14 @@ module \dec62 sync always update \dec62_sv_cr_in $0\dec62_sv_cr_in[2:0] end - attribute \src "libresoc.v:120654.3-120666.6" - process $proc$libresoc.v:120654$4506 + attribute \src "libresoc.v:120730.3-120742.6" + process $proc$libresoc.v:120730$4506 assign { } { } assign { } { } assign $0\dec62_sv_cr_out[2:0] $1\dec62_sv_cr_out[2:0] - attribute \src "libresoc.v:120655.5-120655.29" + attribute \src "libresoc.v:120731.5-120731.29" switch \initial - attribute \src "libresoc.v:120655.9-120655.17" + attribute \src "libresoc.v:120731.9-120731.17" case 1'1 case end @@ -187770,14 +187833,14 @@ module \dec62 sync always update \dec62_sv_cr_out $0\dec62_sv_cr_out[2:0] end - attribute \src "libresoc.v:120667.3-120679.6" - process $proc$libresoc.v:120667$4507 + attribute \src "libresoc.v:120743.3-120755.6" + process $proc$libresoc.v:120743$4507 assign { } { } assign { } { } assign $0\dec62_ldst_len[3:0] $1\dec62_ldst_len[3:0] - attribute \src "libresoc.v:120668.5-120668.29" + attribute \src "libresoc.v:120744.5-120744.29" switch \initial - attribute \src "libresoc.v:120668.9-120668.17" + attribute \src "libresoc.v:120744.9-120744.17" case 1'1 case end @@ -187797,14 +187860,14 @@ module \dec62 sync always update \dec62_ldst_len $0\dec62_ldst_len[3:0] end - attribute \src "libresoc.v:120680.3-120692.6" - process $proc$libresoc.v:120680$4508 + attribute \src "libresoc.v:120756.3-120768.6" + process $proc$libresoc.v:120756$4508 assign { } { } assign { } { } assign $0\dec62_internal_op[6:0] $1\dec62_internal_op[6:0] - attribute \src "libresoc.v:120681.5-120681.29" + attribute \src "libresoc.v:120757.5-120757.29" switch \initial - attribute \src "libresoc.v:120681.9-120681.17" + attribute \src "libresoc.v:120757.9-120757.17" case 1'1 case end @@ -187824,14 +187887,14 @@ module \dec62 sync always update \dec62_internal_op $0\dec62_internal_op[6:0] end - attribute \src "libresoc.v:120693.3-120705.6" - process $proc$libresoc.v:120693$4509 + attribute \src "libresoc.v:120769.3-120781.6" + process $proc$libresoc.v:120769$4509 assign { } { } assign { } { } assign $0\dec62_upd[1:0] $1\dec62_upd[1:0] - attribute \src "libresoc.v:120694.5-120694.29" + attribute \src "libresoc.v:120770.5-120770.29" switch \initial - attribute \src "libresoc.v:120694.9-120694.17" + attribute \src "libresoc.v:120770.9-120770.17" case 1'1 case end @@ -187851,14 +187914,14 @@ module \dec62 sync always update \dec62_upd $0\dec62_upd[1:0] end - attribute \src "libresoc.v:120706.3-120718.6" - process $proc$libresoc.v:120706$4510 + attribute \src "libresoc.v:120782.3-120794.6" + process $proc$libresoc.v:120782$4510 assign { } { } assign { } { } assign $0\dec62_rc_sel[1:0] $1\dec62_rc_sel[1:0] - attribute \src "libresoc.v:120707.5-120707.29" + attribute \src "libresoc.v:120783.5-120783.29" switch \initial - attribute \src "libresoc.v:120707.9-120707.17" + attribute \src "libresoc.v:120783.9-120783.17" case 1'1 case end @@ -187878,14 +187941,14 @@ module \dec62 sync always update \dec62_rc_sel $0\dec62_rc_sel[1:0] end - attribute \src "libresoc.v:120719.3-120731.6" - process $proc$libresoc.v:120719$4511 + attribute \src "libresoc.v:120795.3-120807.6" + process $proc$libresoc.v:120795$4511 assign { } { } assign { } { } assign $0\dec62_cry_in[1:0] $1\dec62_cry_in[1:0] - attribute \src "libresoc.v:120720.5-120720.29" + attribute \src "libresoc.v:120796.5-120796.29" switch \initial - attribute \src "libresoc.v:120720.9-120720.17" + attribute \src "libresoc.v:120796.9-120796.17" case 1'1 case end @@ -187905,14 +187968,14 @@ module \dec62 sync always update \dec62_cry_in $0\dec62_cry_in[1:0] end - attribute \src "libresoc.v:120732.3-120744.6" - process $proc$libresoc.v:120732$4512 + attribute \src "libresoc.v:120808.3-120820.6" + process $proc$libresoc.v:120808$4512 assign { } { } assign { } { } assign $0\dec62_asmcode[7:0] $1\dec62_asmcode[7:0] - attribute \src "libresoc.v:120733.5-120733.29" + attribute \src "libresoc.v:120809.5-120809.29" switch \initial - attribute \src "libresoc.v:120733.9-120733.17" + attribute \src "libresoc.v:120809.9-120809.17" case 1'1 case end @@ -187932,14 +187995,14 @@ module \dec62 sync always update \dec62_asmcode $0\dec62_asmcode[7:0] end - attribute \src "libresoc.v:120745.3-120757.6" - process $proc$libresoc.v:120745$4513 + attribute \src "libresoc.v:120821.3-120833.6" + process $proc$libresoc.v:120821$4513 assign { } { } assign { } { } assign $0\dec62_inv_a[0:0] $1\dec62_inv_a[0:0] - attribute \src "libresoc.v:120746.5-120746.29" + attribute \src "libresoc.v:120822.5-120822.29" switch \initial - attribute \src "libresoc.v:120746.9-120746.17" + attribute \src "libresoc.v:120822.9-120822.17" case 1'1 case end @@ -187959,14 +188022,14 @@ module \dec62 sync always update \dec62_inv_a $0\dec62_inv_a[0:0] end - attribute \src "libresoc.v:120758.3-120770.6" - process $proc$libresoc.v:120758$4514 + attribute \src "libresoc.v:120834.3-120846.6" + process $proc$libresoc.v:120834$4514 assign { } { } assign { } { } assign $0\dec62_inv_out[0:0] $1\dec62_inv_out[0:0] - attribute \src "libresoc.v:120759.5-120759.29" + attribute \src "libresoc.v:120835.5-120835.29" switch \initial - attribute \src "libresoc.v:120759.9-120759.17" + attribute \src "libresoc.v:120835.9-120835.17" case 1'1 case end @@ -187986,14 +188049,14 @@ module \dec62 sync always update \dec62_inv_out $0\dec62_inv_out[0:0] end - attribute \src "libresoc.v:120771.3-120783.6" - process $proc$libresoc.v:120771$4515 + attribute \src "libresoc.v:120847.3-120859.6" + process $proc$libresoc.v:120847$4515 assign { } { } assign { } { } assign $0\dec62_cry_out[0:0] $1\dec62_cry_out[0:0] - attribute \src "libresoc.v:120772.5-120772.29" + attribute \src "libresoc.v:120848.5-120848.29" switch \initial - attribute \src "libresoc.v:120772.9-120772.17" + attribute \src "libresoc.v:120848.9-120848.17" case 1'1 case end @@ -188013,14 +188076,14 @@ module \dec62 sync always update \dec62_cry_out $0\dec62_cry_out[0:0] end - attribute \src "libresoc.v:120784.3-120796.6" - process $proc$libresoc.v:120784$4516 + attribute \src "libresoc.v:120860.3-120872.6" + process $proc$libresoc.v:120860$4516 assign { } { } assign { } { } assign $0\dec62_br[0:0] $1\dec62_br[0:0] - attribute \src "libresoc.v:120785.5-120785.29" + attribute \src "libresoc.v:120861.5-120861.29" switch \initial - attribute \src "libresoc.v:120785.9-120785.17" + attribute \src "libresoc.v:120861.9-120861.17" case 1'1 case end @@ -188040,14 +188103,14 @@ module \dec62 sync always update \dec62_br $0\dec62_br[0:0] end - attribute \src "libresoc.v:120797.3-120809.6" - process $proc$libresoc.v:120797$4517 + attribute \src "libresoc.v:120873.3-120885.6" + process $proc$libresoc.v:120873$4517 assign { } { } assign { } { } assign $0\dec62_sgn_ext[0:0] $1\dec62_sgn_ext[0:0] - attribute \src "libresoc.v:120798.5-120798.29" + attribute \src "libresoc.v:120874.5-120874.29" switch \initial - attribute \src "libresoc.v:120798.9-120798.17" + attribute \src "libresoc.v:120874.9-120874.17" case 1'1 case end @@ -188067,14 +188130,14 @@ module \dec62 sync always update \dec62_sgn_ext $0\dec62_sgn_ext[0:0] end - attribute \src "libresoc.v:120810.3-120822.6" - process $proc$libresoc.v:120810$4518 + attribute \src "libresoc.v:120886.3-120898.6" + process $proc$libresoc.v:120886$4518 assign { } { } assign { } { } assign $0\dec62_rsrv[0:0] $1\dec62_rsrv[0:0] - attribute \src "libresoc.v:120811.5-120811.29" + attribute \src "libresoc.v:120887.5-120887.29" switch \initial - attribute \src "libresoc.v:120811.9-120811.17" + attribute \src "libresoc.v:120887.9-120887.17" case 1'1 case end @@ -188094,14 +188157,14 @@ module \dec62 sync always update \dec62_rsrv $0\dec62_rsrv[0:0] end - attribute \src "libresoc.v:120823.3-120835.6" - process $proc$libresoc.v:120823$4519 + attribute \src "libresoc.v:120899.3-120911.6" + process $proc$libresoc.v:120899$4519 assign { } { } assign { } { } assign $0\dec62_form[4:0] $1\dec62_form[4:0] - attribute \src "libresoc.v:120824.5-120824.29" + attribute \src "libresoc.v:120900.5-120900.29" switch \initial - attribute \src "libresoc.v:120824.9-120824.17" + attribute \src "libresoc.v:120900.9-120900.17" case 1'1 case end @@ -188121,14 +188184,14 @@ module \dec62 sync always update \dec62_form $0\dec62_form[4:0] end - attribute \src "libresoc.v:120836.3-120848.6" - process $proc$libresoc.v:120836$4520 + attribute \src "libresoc.v:120912.3-120924.6" + process $proc$libresoc.v:120912$4520 assign { } { } assign { } { } assign $0\dec62_is_32b[0:0] $1\dec62_is_32b[0:0] - attribute \src "libresoc.v:120837.5-120837.29" + attribute \src "libresoc.v:120913.5-120913.29" switch \initial - attribute \src "libresoc.v:120837.9-120837.17" + attribute \src "libresoc.v:120913.9-120913.17" case 1'1 case end @@ -188148,14 +188211,14 @@ module \dec62 sync always update \dec62_is_32b $0\dec62_is_32b[0:0] end - attribute \src "libresoc.v:120849.3-120861.6" - process $proc$libresoc.v:120849$4521 + attribute \src "libresoc.v:120925.3-120937.6" + process $proc$libresoc.v:120925$4521 assign { } { } assign { } { } assign $0\dec62_sgn[0:0] $1\dec62_sgn[0:0] - attribute \src "libresoc.v:120850.5-120850.29" + attribute \src "libresoc.v:120926.5-120926.29" switch \initial - attribute \src "libresoc.v:120850.9-120850.17" + attribute \src "libresoc.v:120926.9-120926.17" case 1'1 case end @@ -188175,14 +188238,14 @@ module \dec62 sync always update \dec62_sgn $0\dec62_sgn[0:0] end - attribute \src "libresoc.v:120862.3-120874.6" - process $proc$libresoc.v:120862$4522 + attribute \src "libresoc.v:120938.3-120950.6" + process $proc$libresoc.v:120938$4522 assign { } { } assign { } { } assign $0\dec62_lk[0:0] $1\dec62_lk[0:0] - attribute \src "libresoc.v:120863.5-120863.29" + attribute \src "libresoc.v:120939.5-120939.29" switch \initial - attribute \src "libresoc.v:120863.9-120863.17" + attribute \src "libresoc.v:120939.9-120939.17" case 1'1 case end @@ -188202,14 +188265,14 @@ module \dec62 sync always update \dec62_lk $0\dec62_lk[0:0] end - attribute \src "libresoc.v:120875.3-120887.6" - process $proc$libresoc.v:120875$4523 + attribute \src "libresoc.v:120951.3-120963.6" + process $proc$libresoc.v:120951$4523 assign { } { } assign { } { } assign $0\dec62_sgl_pipe[0:0] $1\dec62_sgl_pipe[0:0] - attribute \src "libresoc.v:120876.5-120876.29" + attribute \src "libresoc.v:120952.5-120952.29" switch \initial - attribute \src "libresoc.v:120876.9-120876.17" + attribute \src "libresoc.v:120952.9-120952.17" case 1'1 case end @@ -188229,14 +188292,14 @@ module \dec62 sync always update \dec62_sgl_pipe $0\dec62_sgl_pipe[0:0] end - attribute \src "libresoc.v:120888.3-120900.6" - process $proc$libresoc.v:120888$4524 + attribute \src "libresoc.v:120964.3-120976.6" + process $proc$libresoc.v:120964$4524 assign { } { } assign { } { } assign $0\dec62_SV_Etype[1:0] $1\dec62_SV_Etype[1:0] - attribute \src "libresoc.v:120889.5-120889.29" + attribute \src "libresoc.v:120965.5-120965.29" switch \initial - attribute \src "libresoc.v:120889.9-120889.17" + attribute \src "libresoc.v:120965.9-120965.17" case 1'1 case end @@ -188256,14 +188319,14 @@ module \dec62 sync always update \dec62_SV_Etype $0\dec62_SV_Etype[1:0] end - attribute \src "libresoc.v:120901.3-120913.6" - process $proc$libresoc.v:120901$4525 + attribute \src "libresoc.v:120977.3-120989.6" + process $proc$libresoc.v:120977$4525 assign { } { } assign { } { } assign $0\dec62_SV_Ptype[1:0] $1\dec62_SV_Ptype[1:0] - attribute \src "libresoc.v:120902.5-120902.29" + attribute \src "libresoc.v:120978.5-120978.29" switch \initial - attribute \src "libresoc.v:120902.9-120902.17" + attribute \src "libresoc.v:120978.9-120978.17" case 1'1 case end @@ -188283,14 +188346,14 @@ module \dec62 sync always update \dec62_SV_Ptype $0\dec62_SV_Ptype[1:0] end - attribute \src "libresoc.v:120914.3-120926.6" - process $proc$libresoc.v:120914$4526 + attribute \src "libresoc.v:120990.3-121002.6" + process $proc$libresoc.v:120990$4526 assign { } { } assign { } { } assign $0\dec62_in1_sel[2:0] $1\dec62_in1_sel[2:0] - attribute \src "libresoc.v:120915.5-120915.29" + attribute \src "libresoc.v:120991.5-120991.29" switch \initial - attribute \src "libresoc.v:120915.9-120915.17" + attribute \src "libresoc.v:120991.9-120991.17" case 1'1 case end @@ -188310,14 +188373,14 @@ module \dec62 sync always update \dec62_in1_sel $0\dec62_in1_sel[2:0] end - attribute \src "libresoc.v:120927.3-120939.6" - process $proc$libresoc.v:120927$4527 + attribute \src "libresoc.v:121003.3-121015.6" + process $proc$libresoc.v:121003$4527 assign { } { } assign { } { } assign $0\dec62_in2_sel[3:0] $1\dec62_in2_sel[3:0] - attribute \src "libresoc.v:120928.5-120928.29" + attribute \src "libresoc.v:121004.5-121004.29" switch \initial - attribute \src "libresoc.v:120928.9-120928.17" + attribute \src "libresoc.v:121004.9-121004.17" case 1'1 case end @@ -188337,14 +188400,14 @@ module \dec62 sync always update \dec62_in2_sel $0\dec62_in2_sel[3:0] end - attribute \src "libresoc.v:120940.3-120952.6" - process $proc$libresoc.v:120940$4528 + attribute \src "libresoc.v:121016.3-121028.6" + process $proc$libresoc.v:121016$4528 assign { } { } assign { } { } assign $0\dec62_in3_sel[1:0] $1\dec62_in3_sel[1:0] - attribute \src "libresoc.v:120941.5-120941.29" + attribute \src "libresoc.v:121017.5-121017.29" switch \initial - attribute \src "libresoc.v:120941.9-120941.17" + attribute \src "libresoc.v:121017.9-121017.17" case 1'1 case end @@ -188364,14 +188427,14 @@ module \dec62 sync always update \dec62_in3_sel $0\dec62_in3_sel[1:0] end - attribute \src "libresoc.v:120953.3-120965.6" - process $proc$libresoc.v:120953$4529 + attribute \src "libresoc.v:121029.3-121041.6" + process $proc$libresoc.v:121029$4529 assign { } { } assign { } { } assign $0\dec62_out_sel[2:0] $1\dec62_out_sel[2:0] - attribute \src "libresoc.v:120954.5-120954.29" + attribute \src "libresoc.v:121030.5-121030.29" switch \initial - attribute \src "libresoc.v:120954.9-120954.17" + attribute \src "libresoc.v:121030.9-121030.17" case 1'1 case end @@ -188393,73 +188456,73 @@ module \dec62 end connect \opcode_switch \opcode_in [1:0] end -attribute \src "libresoc.v:120971.1-121554.10" +attribute \src "libresoc.v:121047.1-121630.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU" attribute \generator "nMigen" module \dec_ALU - attribute \src "libresoc.v:121517.3-121531.6" + attribute \src "libresoc.v:121593.3-121607.6" wire width 14 $0\ALU__fn_unit[13:0] - attribute \src "libresoc.v:121504.3-121516.6" + attribute \src "libresoc.v:121580.3-121592.6" wire width 7 $0\ALU__insn_type[6:0] - attribute \src "libresoc.v:121489.3-121503.6" + attribute \src "libresoc.v:121565.3-121579.6" wire $0\ALU__write_cr0[0:0] - attribute \src "libresoc.v:120972.7-120972.20" + attribute \src "libresoc.v:121048.7-121048.20" wire $0\initial[0:0] - attribute \src "libresoc.v:121517.3-121531.6" + attribute \src "libresoc.v:121593.3-121607.6" wire width 14 $1\ALU__fn_unit[13:0] - attribute \src "libresoc.v:121504.3-121516.6" + attribute \src "libresoc.v:121580.3-121592.6" wire width 7 $1\ALU__insn_type[6:0] - attribute \src "libresoc.v:121489.3-121503.6" + attribute \src "libresoc.v:121565.3-121579.6" wire $1\ALU__write_cr0[0:0] - attribute \src "libresoc.v:121405.18-121405.113" - wire $and$libresoc.v:121405$4531_Y - attribute \src "libresoc.v:121407.18-121407.110" - wire $and$libresoc.v:121407$4533_Y - attribute \src "libresoc.v:121420.18-121420.114" - wire $and$libresoc.v:121420$4546_Y - attribute \src "libresoc.v:121421.18-121421.116" - wire $and$libresoc.v:121421$4547_Y - attribute \src "libresoc.v:121423.18-121423.114" - wire $and$libresoc.v:121423$4549_Y - attribute \src "libresoc.v:121425.18-121425.110" - wire $and$libresoc.v:121425$4551_Y - attribute \src "libresoc.v:121426.17-121426.112" - wire $and$libresoc.v:121426$4552_Y - attribute \src "libresoc.v:121427.17-121427.114" - wire $and$libresoc.v:121427$4553_Y - attribute \src "libresoc.v:121408.18-121408.126" - wire $eq$libresoc.v:121408$4534_Y - attribute \src "libresoc.v:121409.18-121409.126" - wire $eq$libresoc.v:121409$4535_Y - attribute \src "libresoc.v:121411.18-121411.110" - wire $eq$libresoc.v:121411$4537_Y - attribute \src "libresoc.v:121412.18-121412.110" - wire $eq$libresoc.v:121412$4538_Y - attribute \src "libresoc.v:121414.18-121414.112" - wire $eq$libresoc.v:121414$4540_Y - attribute \src "libresoc.v:121415.17-121415.130" - wire $eq$libresoc.v:121415$4541_Y - attribute \src "libresoc.v:121417.18-121417.110" - wire $eq$libresoc.v:121417$4543_Y - attribute \src "libresoc.v:121419.18-121419.131" - wire $eq$libresoc.v:121419$4545_Y - attribute \src "libresoc.v:121422.18-121422.131" - wire $eq$libresoc.v:121422$4548_Y - attribute \src "libresoc.v:121428.17-121428.130" - wire $eq$libresoc.v:121428$4554_Y - attribute \src "libresoc.v:121406.18-121406.110" - wire $not$libresoc.v:121406$4532_Y - attribute \src "libresoc.v:121424.18-121424.110" - wire $not$libresoc.v:121424$4550_Y - attribute \src "libresoc.v:121410.18-121410.110" - wire $or$libresoc.v:121410$4536_Y - attribute \src "libresoc.v:121413.18-121413.110" - wire $or$libresoc.v:121413$4539_Y - attribute \src "libresoc.v:121416.18-121416.110" - wire $or$libresoc.v:121416$4542_Y - attribute \src "libresoc.v:121418.18-121418.110" - wire $or$libresoc.v:121418$4544_Y + attribute \src "libresoc.v:121481.18-121481.113" + wire $and$libresoc.v:121481$4531_Y + attribute \src "libresoc.v:121483.18-121483.110" + wire $and$libresoc.v:121483$4533_Y + attribute \src "libresoc.v:121496.18-121496.114" + wire $and$libresoc.v:121496$4546_Y + attribute \src "libresoc.v:121497.18-121497.116" + wire $and$libresoc.v:121497$4547_Y + attribute \src "libresoc.v:121499.18-121499.114" + wire $and$libresoc.v:121499$4549_Y + attribute \src "libresoc.v:121501.18-121501.110" + wire $and$libresoc.v:121501$4551_Y + attribute \src "libresoc.v:121502.17-121502.112" + wire $and$libresoc.v:121502$4552_Y + attribute \src "libresoc.v:121503.17-121503.114" + wire $and$libresoc.v:121503$4553_Y + attribute \src "libresoc.v:121484.18-121484.126" + wire $eq$libresoc.v:121484$4534_Y + attribute \src "libresoc.v:121485.18-121485.126" + wire $eq$libresoc.v:121485$4535_Y + attribute \src "libresoc.v:121487.18-121487.110" + wire $eq$libresoc.v:121487$4537_Y + attribute \src "libresoc.v:121488.18-121488.110" + wire $eq$libresoc.v:121488$4538_Y + attribute \src "libresoc.v:121490.18-121490.112" + wire $eq$libresoc.v:121490$4540_Y + attribute \src "libresoc.v:121491.17-121491.130" + wire $eq$libresoc.v:121491$4541_Y + attribute \src "libresoc.v:121493.18-121493.110" + wire $eq$libresoc.v:121493$4543_Y + attribute \src "libresoc.v:121495.18-121495.131" + wire $eq$libresoc.v:121495$4545_Y + attribute \src "libresoc.v:121498.18-121498.131" + wire $eq$libresoc.v:121498$4548_Y + attribute \src "libresoc.v:121504.17-121504.130" + wire $eq$libresoc.v:121504$4554_Y + attribute \src "libresoc.v:121482.18-121482.110" + wire $not$libresoc.v:121482$4532_Y + attribute \src "libresoc.v:121500.18-121500.110" + wire $not$libresoc.v:121500$4550_Y + attribute \src "libresoc.v:121486.18-121486.110" + wire $or$libresoc.v:121486$4536_Y + attribute \src "libresoc.v:121489.18-121489.110" + wire $or$libresoc.v:121489$4539_Y + attribute \src "libresoc.v:121492.18-121492.110" + wire $or$libresoc.v:121492$4542_Y + attribute \src "libresoc.v:121494.18-121494.110" + wire $or$libresoc.v:121494$4544_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" @@ -188875,7 +188938,7 @@ module \dec_ALU attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:120972.7-120972.15" + attribute \src "libresoc.v:121048.7-121048.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" wire width 32 \insn_in @@ -188892,7 +188955,7 @@ module \dec_ALU attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" wire input 2 \sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:121405$4531 + cell $and $and$libresoc.v:121481$4531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188900,10 +188963,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:121405$4531_Y + connect \Y $and$libresoc.v:121481$4531_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:121407$4533 + cell $and $and$libresoc.v:121483$4533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188911,10 +188974,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:121407$4533_Y + connect \Y $and$libresoc.v:121483$4533_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:121420$4546 + cell $and $and$libresoc.v:121496$4546 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188922,10 +188985,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:121420$4546_Y + connect \Y $and$libresoc.v:121496$4546_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:121421$4547 + cell $and $and$libresoc.v:121497$4547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188933,10 +188996,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:121421$4547_Y + connect \Y $and$libresoc.v:121497$4547_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:121423$4549 + cell $and $and$libresoc.v:121499$4549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188944,10 +189007,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:121423$4549_Y + connect \Y $and$libresoc.v:121499$4549_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:121425$4551 + cell $and $and$libresoc.v:121501$4551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188955,10 +189018,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:121425$4551_Y + connect \Y $and$libresoc.v:121501$4551_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:121426$4552 + cell $and $and$libresoc.v:121502$4552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188966,10 +189029,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:121426$4552_Y + connect \Y $and$libresoc.v:121502$4552_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:121427$4553 + cell $and $and$libresoc.v:121503$4553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -188977,10 +189040,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:121427$4553_Y + connect \Y $and$libresoc.v:121503$4553_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $eq $eq$libresoc.v:121408$4534 + cell $eq $eq$libresoc.v:121484$4534 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -188988,10 +189051,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \dec_ALU_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:121408$4534_Y + connect \Y $eq$libresoc.v:121484$4534_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $eq $eq$libresoc.v:121409$4535 + cell $eq $eq$libresoc.v:121485$4535 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -188999,10 +189062,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \dec_ALU_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:121409$4535_Y + connect \Y $eq$libresoc.v:121485$4535_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:121411$4537 + cell $eq $eq$libresoc.v:121487$4537 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -189010,10 +189073,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:121411$4537_Y + connect \Y $eq$libresoc.v:121487$4537_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:121412$4538 + cell $eq $eq$libresoc.v:121488$4538 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -189021,10 +189084,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:121412$4538_Y + connect \Y $eq$libresoc.v:121488$4538_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:121414$4540 + cell $eq $eq$libresoc.v:121490$4540 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -189032,10 +189095,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:121414$4540_Y + connect \Y $eq$libresoc.v:121490$4540_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $eq $eq$libresoc.v:121415$4541 + cell $eq $eq$libresoc.v:121491$4541 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -189043,10 +189106,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \dec_ALU_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:121415$4541_Y + connect \Y $eq$libresoc.v:121491$4541_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $eq $eq$libresoc.v:121417$4543 + cell $eq $eq$libresoc.v:121493$4543 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -189054,10 +189117,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:121417$4543_Y + connect \Y $eq$libresoc.v:121493$4543_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $eq $eq$libresoc.v:121419$4545 + cell $eq $eq$libresoc.v:121495$4545 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -189065,10 +189128,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \dec_ALU_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:121419$4545_Y + connect \Y $eq$libresoc.v:121495$4545_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $eq $eq$libresoc.v:121422$4548 + cell $eq $eq$libresoc.v:121498$4548 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -189076,10 +189139,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \dec_ALU_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:121422$4548_Y + connect \Y $eq$libresoc.v:121498$4548_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $eq $eq$libresoc.v:121428$4554 + cell $eq $eq$libresoc.v:121504$4554 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -189087,26 +189150,26 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \dec_ALU_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:121428$4554_Y + connect \Y $eq$libresoc.v:121504$4554_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $not $not$libresoc.v:121406$4532 + cell $not $not$libresoc.v:121482$4532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:121406$4532_Y + connect \Y $not$libresoc.v:121482$4532_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $not $not$libresoc.v:121424$4550 + cell $not $not$libresoc.v:121500$4550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:121424$4550_Y + connect \Y $not$libresoc.v:121500$4550_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $or $or$libresoc.v:121410$4536 + cell $or $or$libresoc.v:121486$4536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189114,10 +189177,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:121410$4536_Y + connect \Y $or$libresoc.v:121486$4536_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:121413$4539 + cell $or $or$libresoc.v:121489$4539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189125,10 +189188,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:121413$4539_Y + connect \Y $or$libresoc.v:121489$4539_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:121416$4542 + cell $or $or$libresoc.v:121492$4542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189136,10 +189199,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:121416$4542_Y + connect \Y $or$libresoc.v:121492$4542_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $or $or$libresoc.v:121418$4544 + cell $or $or$libresoc.v:121494$4544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189147,10 +189210,10 @@ module \dec_ALU parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:121418$4544_Y + connect \Y $or$libresoc.v:121494$4544_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:121429.7-121457.4" + attribute \src "libresoc.v:121505.7-121533.4" cell \dec \dec connect \ALU_BD \dec_ALU_BD connect \ALU_DS \dec_ALU_DS @@ -189181,7 +189244,7 @@ module \dec_ALU connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121458.10-121463.4" + attribute \src "libresoc.v:121534.10-121539.4" cell \dec_ai \dec_ai connect \ALU_RA \dec_ALU_RA connect \immz_out \dec_ai_immz_out @@ -189189,7 +189252,7 @@ module \dec_ALU connect \sv_nz \dec_ai_sv_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:121464.10-121475.4" + attribute \src "libresoc.v:121540.10-121551.4" cell \dec_bi \dec_bi connect \ALU_BD \dec_ALU_BD connect \ALU_DS \dec_ALU_DS @@ -189203,7 +189266,7 @@ module \dec_ALU connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121476.10-121482.4" + attribute \src "libresoc.v:121552.10-121558.4" cell \dec_oe \dec_oe connect \ALU_OE \dec_ALU_OE connect \ALU_internal_op \dec_ALU_internal_op @@ -189212,29 +189275,29 @@ module \dec_ALU connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121483.10-121488.4" + attribute \src "libresoc.v:121559.10-121564.4" cell \dec_rc \dec_rc connect \ALU_Rc \dec_ALU_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:120972.7-120972.20" - process $proc$libresoc.v:120972$4558 + attribute \src "libresoc.v:121048.7-121048.20" + process $proc$libresoc.v:121048$4558 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:121489.3-121503.6" - process $proc$libresoc.v:121489$4555 + attribute \src "libresoc.v:121565.3-121579.6" + process $proc$libresoc.v:121565$4555 assign { } { } assign { } { } assign $0\ALU__write_cr0[0:0] $1\ALU__write_cr0[0:0] - attribute \src "libresoc.v:121490.5-121490.29" + attribute \src "libresoc.v:121566.5-121566.29" switch \initial - attribute \src "libresoc.v:121490.9-121490.17" + attribute \src "libresoc.v:121566.9-121566.17" case 1'1 case end @@ -189254,14 +189317,14 @@ module \dec_ALU sync always update \ALU__write_cr0 $0\ALU__write_cr0[0:0] end - attribute \src "libresoc.v:121504.3-121516.6" - process $proc$libresoc.v:121504$4556 + attribute \src "libresoc.v:121580.3-121592.6" + process $proc$libresoc.v:121580$4556 assign { } { } assign { } { } assign $0\ALU__insn_type[6:0] $1\ALU__insn_type[6:0] - attribute \src "libresoc.v:121505.5-121505.29" + attribute \src "libresoc.v:121581.5-121581.29" switch \initial - attribute \src "libresoc.v:121505.9-121505.17" + attribute \src "libresoc.v:121581.9-121581.17" case 1'1 case end @@ -189281,13 +189344,13 @@ module \dec_ALU sync always update \ALU__insn_type $0\ALU__insn_type[6:0] end - attribute \src "libresoc.v:121517.3-121531.6" - process $proc$libresoc.v:121517$4557 + attribute \src "libresoc.v:121593.3-121607.6" + process $proc$libresoc.v:121593$4557 assign { } { } assign $0\ALU__fn_unit[13:0] $1\ALU__fn_unit[13:0] - attribute \src "libresoc.v:121518.5-121518.29" + attribute \src "libresoc.v:121594.5-121594.29" switch \initial - attribute \src "libresoc.v:121518.9-121518.17" + attribute \src "libresoc.v:121594.9-121594.17" case 1'1 case end @@ -189309,30 +189372,30 @@ module \dec_ALU sync always update \ALU__fn_unit $0\ALU__fn_unit[13:0] end - connect \$10 $and$libresoc.v:121405$4531_Y - connect \$12 $not$libresoc.v:121406$4532_Y - connect \$14 $and$libresoc.v:121407$4533_Y - connect \$16 $eq$libresoc.v:121408$4534_Y - connect \$18 $eq$libresoc.v:121409$4535_Y - connect \$20 $or$libresoc.v:121410$4536_Y - connect \$22 $eq$libresoc.v:121411$4537_Y - connect \$24 $eq$libresoc.v:121412$4538_Y - connect \$26 $or$libresoc.v:121413$4539_Y - connect \$28 $eq$libresoc.v:121414$4540_Y - connect \$2 $eq$libresoc.v:121415$4541_Y - connect \$30 $or$libresoc.v:121416$4542_Y - connect \$32 $eq$libresoc.v:121417$4543_Y - connect \$34 $or$libresoc.v:121418$4544_Y - connect \$36 $eq$libresoc.v:121419$4545_Y - connect \$38 $and$libresoc.v:121420$4546_Y - connect \$40 $and$libresoc.v:121421$4547_Y - connect \$42 $eq$libresoc.v:121422$4548_Y - connect \$44 $and$libresoc.v:121423$4549_Y - connect \$46 $not$libresoc.v:121424$4550_Y - connect \$48 $and$libresoc.v:121425$4551_Y - connect \$4 $and$libresoc.v:121426$4552_Y - connect \$6 $and$libresoc.v:121427$4553_Y - connect \$8 $eq$libresoc.v:121428$4554_Y + connect \$10 $and$libresoc.v:121481$4531_Y + connect \$12 $not$libresoc.v:121482$4532_Y + connect \$14 $and$libresoc.v:121483$4533_Y + connect \$16 $eq$libresoc.v:121484$4534_Y + connect \$18 $eq$libresoc.v:121485$4535_Y + connect \$20 $or$libresoc.v:121486$4536_Y + connect \$22 $eq$libresoc.v:121487$4537_Y + connect \$24 $eq$libresoc.v:121488$4538_Y + connect \$26 $or$libresoc.v:121489$4539_Y + connect \$28 $eq$libresoc.v:121490$4540_Y + connect \$2 $eq$libresoc.v:121491$4541_Y + connect \$30 $or$libresoc.v:121492$4542_Y + connect \$32 $eq$libresoc.v:121493$4543_Y + connect \$34 $or$libresoc.v:121494$4544_Y + connect \$36 $eq$libresoc.v:121495$4545_Y + connect \$38 $and$libresoc.v:121496$4546_Y + connect \$40 $and$libresoc.v:121497$4547_Y + connect \$42 $eq$libresoc.v:121498$4548_Y + connect \$44 $and$libresoc.v:121499$4549_Y + connect \$46 $not$libresoc.v:121500$4550_Y + connect \$48 $and$libresoc.v:121501$4551_Y + connect \$4 $and$libresoc.v:121502$4552_Y + connect \$6 $and$libresoc.v:121503$4553_Y + connect \$8 $eq$libresoc.v:121504$4554_Y connect \ALU__is_signed \dec_ALU_sgn connect \ALU__is_32bit \dec_ALU_is_32b connect \ALU__output_carry \dec_ALU_cry_out @@ -189356,73 +189419,73 @@ module \dec_ALU connect \insn_in \dec_opcode_in connect \ALU__insn \dec_opcode_in end -attribute \src "libresoc.v:121558.1-122038.10" +attribute \src "libresoc.v:121634.1-122114.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH" attribute \generator "nMigen" module \dec_BRANCH - attribute \src "libresoc.v:121988.3-122002.6" + attribute \src "libresoc.v:122064.3-122078.6" wire width 14 $0\BRANCH__fn_unit[13:0] - attribute \src "libresoc.v:122013.3-122025.6" + attribute \src "libresoc.v:122089.3-122101.6" wire width 7 $0\BRANCH__insn_type[6:0] - attribute \src "libresoc.v:122003.3-122012.6" + attribute \src "libresoc.v:122079.3-122088.6" wire $0\BRANCH__lk[0:0] - attribute \src "libresoc.v:121559.7-121559.20" + attribute \src "libresoc.v:121635.7-121635.20" wire $0\initial[0:0] - attribute \src "libresoc.v:121988.3-122002.6" + attribute \src "libresoc.v:122064.3-122078.6" wire width 14 $1\BRANCH__fn_unit[13:0] - attribute \src "libresoc.v:122013.3-122025.6" + attribute \src "libresoc.v:122089.3-122101.6" wire width 7 $1\BRANCH__insn_type[6:0] - attribute \src "libresoc.v:122003.3-122012.6" + attribute \src "libresoc.v:122079.3-122088.6" wire $1\BRANCH__lk[0:0] - attribute \src "libresoc.v:121920.18-121920.113" - wire $and$libresoc.v:121920$4559_Y - attribute \src "libresoc.v:121922.18-121922.110" - wire $and$libresoc.v:121922$4561_Y - attribute \src "libresoc.v:121935.18-121935.114" - wire $and$libresoc.v:121935$4574_Y - attribute \src "libresoc.v:121936.18-121936.116" - wire $and$libresoc.v:121936$4575_Y - attribute \src "libresoc.v:121938.18-121938.114" - wire $and$libresoc.v:121938$4577_Y - attribute \src "libresoc.v:121940.18-121940.110" - wire $and$libresoc.v:121940$4579_Y - attribute \src "libresoc.v:121941.17-121941.112" - wire $and$libresoc.v:121941$4580_Y - attribute \src "libresoc.v:121942.17-121942.114" - wire $and$libresoc.v:121942$4581_Y - attribute \src "libresoc.v:121923.18-121923.129" - wire $eq$libresoc.v:121923$4562_Y - attribute \src "libresoc.v:121924.18-121924.129" - wire $eq$libresoc.v:121924$4563_Y - attribute \src "libresoc.v:121926.18-121926.110" - wire $eq$libresoc.v:121926$4565_Y - attribute \src "libresoc.v:121927.18-121927.110" - wire $eq$libresoc.v:121927$4566_Y - attribute \src "libresoc.v:121929.18-121929.112" - wire $eq$libresoc.v:121929$4568_Y - attribute \src "libresoc.v:121930.17-121930.133" - wire $eq$libresoc.v:121930$4569_Y - attribute \src "libresoc.v:121932.18-121932.110" - wire $eq$libresoc.v:121932$4571_Y - attribute \src "libresoc.v:121934.18-121934.134" - wire $eq$libresoc.v:121934$4573_Y - attribute \src "libresoc.v:121937.18-121937.134" - wire $eq$libresoc.v:121937$4576_Y - attribute \src "libresoc.v:121943.17-121943.133" - wire $eq$libresoc.v:121943$4582_Y - attribute \src "libresoc.v:121921.18-121921.110" - wire $not$libresoc.v:121921$4560_Y - attribute \src "libresoc.v:121939.18-121939.110" - wire $not$libresoc.v:121939$4578_Y - attribute \src "libresoc.v:121925.18-121925.110" - wire $or$libresoc.v:121925$4564_Y - attribute \src "libresoc.v:121928.18-121928.110" - wire $or$libresoc.v:121928$4567_Y - attribute \src "libresoc.v:121931.18-121931.110" - wire $or$libresoc.v:121931$4570_Y - attribute \src "libresoc.v:121933.18-121933.110" - wire $or$libresoc.v:121933$4572_Y + attribute \src "libresoc.v:121996.18-121996.113" + wire $and$libresoc.v:121996$4559_Y + attribute \src "libresoc.v:121998.18-121998.110" + wire $and$libresoc.v:121998$4561_Y + attribute \src "libresoc.v:122011.18-122011.114" + wire $and$libresoc.v:122011$4574_Y + attribute \src "libresoc.v:122012.18-122012.116" + wire $and$libresoc.v:122012$4575_Y + attribute \src "libresoc.v:122014.18-122014.114" + wire $and$libresoc.v:122014$4577_Y + attribute \src "libresoc.v:122016.18-122016.110" + wire $and$libresoc.v:122016$4579_Y + attribute \src "libresoc.v:122017.17-122017.112" + wire $and$libresoc.v:122017$4580_Y + attribute \src "libresoc.v:122018.17-122018.114" + wire $and$libresoc.v:122018$4581_Y + attribute \src "libresoc.v:121999.18-121999.129" + wire $eq$libresoc.v:121999$4562_Y + attribute \src "libresoc.v:122000.18-122000.129" + wire $eq$libresoc.v:122000$4563_Y + attribute \src "libresoc.v:122002.18-122002.110" + wire $eq$libresoc.v:122002$4565_Y + attribute \src "libresoc.v:122003.18-122003.110" + wire $eq$libresoc.v:122003$4566_Y + attribute \src "libresoc.v:122005.18-122005.112" + wire $eq$libresoc.v:122005$4568_Y + attribute \src "libresoc.v:122006.17-122006.133" + wire $eq$libresoc.v:122006$4569_Y + attribute \src "libresoc.v:122008.18-122008.110" + wire $eq$libresoc.v:122008$4571_Y + attribute \src "libresoc.v:122010.18-122010.134" + wire $eq$libresoc.v:122010$4573_Y + attribute \src "libresoc.v:122013.18-122013.134" + wire $eq$libresoc.v:122013$4576_Y + attribute \src "libresoc.v:122019.17-122019.133" + wire $eq$libresoc.v:122019$4582_Y + attribute \src "libresoc.v:121997.18-121997.110" + wire $not$libresoc.v:121997$4560_Y + attribute \src "libresoc.v:122015.18-122015.110" + wire $not$libresoc.v:122015$4578_Y + attribute \src "libresoc.v:122001.18-122001.110" + wire $or$libresoc.v:122001$4564_Y + attribute \src "libresoc.v:122004.18-122004.110" + wire $or$libresoc.v:122004$4567_Y + attribute \src "libresoc.v:122007.18-122007.110" + wire $or$libresoc.v:122007$4570_Y + attribute \src "libresoc.v:122009.18-122009.110" + wire $or$libresoc.v:122009$4572_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" @@ -189768,7 +189831,7 @@ module \dec_BRANCH attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:121559.7-121559.15" + attribute \src "libresoc.v:121635.7-121635.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" wire width 32 \insn_in @@ -189783,7 +189846,7 @@ module \dec_BRANCH attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" wire width 10 \spr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:121920$4559 + cell $and $and$libresoc.v:121996$4559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189791,10 +189854,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:121920$4559_Y + connect \Y $and$libresoc.v:121996$4559_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:121922$4561 + cell $and $and$libresoc.v:121998$4561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189802,10 +189865,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:121922$4561_Y + connect \Y $and$libresoc.v:121998$4561_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:121935$4574 + cell $and $and$libresoc.v:122011$4574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189813,10 +189876,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:121935$4574_Y + connect \Y $and$libresoc.v:122011$4574_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:121936$4575 + cell $and $and$libresoc.v:122012$4575 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189824,10 +189887,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:121936$4575_Y + connect \Y $and$libresoc.v:122012$4575_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:121938$4577 + cell $and $and$libresoc.v:122014$4577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189835,10 +189898,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:121938$4577_Y + connect \Y $and$libresoc.v:122014$4577_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:121940$4579 + cell $and $and$libresoc.v:122016$4579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189846,10 +189909,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:121940$4579_Y + connect \Y $and$libresoc.v:122016$4579_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:121941$4580 + cell $and $and$libresoc.v:122017$4580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189857,10 +189920,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:121941$4580_Y + connect \Y $and$libresoc.v:122017$4580_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:121942$4581 + cell $and $and$libresoc.v:122018$4581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -189868,10 +189931,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:121942$4581_Y + connect \Y $and$libresoc.v:122018$4581_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $eq $eq$libresoc.v:121923$4562 + cell $eq $eq$libresoc.v:121999$4562 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -189879,10 +189942,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \dec_BRANCH_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:121923$4562_Y + connect \Y $eq$libresoc.v:121999$4562_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $eq $eq$libresoc.v:121924$4563 + cell $eq $eq$libresoc.v:122000$4563 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -189890,10 +189953,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \dec_BRANCH_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:121924$4563_Y + connect \Y $eq$libresoc.v:122000$4563_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:121926$4565 + cell $eq $eq$libresoc.v:122002$4565 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -189901,10 +189964,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:121926$4565_Y + connect \Y $eq$libresoc.v:122002$4565_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:121927$4566 + cell $eq $eq$libresoc.v:122003$4566 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -189912,10 +189975,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:121927$4566_Y + connect \Y $eq$libresoc.v:122003$4566_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:121929$4568 + cell $eq $eq$libresoc.v:122005$4568 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -189923,10 +189986,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:121929$4568_Y + connect \Y $eq$libresoc.v:122005$4568_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $eq $eq$libresoc.v:121930$4569 + cell $eq $eq$libresoc.v:122006$4569 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -189934,10 +189997,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \dec_BRANCH_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:121930$4569_Y + connect \Y $eq$libresoc.v:122006$4569_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $eq $eq$libresoc.v:121932$4571 + cell $eq $eq$libresoc.v:122008$4571 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -189945,10 +190008,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:121932$4571_Y + connect \Y $eq$libresoc.v:122008$4571_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $eq $eq$libresoc.v:121934$4573 + cell $eq $eq$libresoc.v:122010$4573 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -189956,10 +190019,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \dec_BRANCH_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:121934$4573_Y + connect \Y $eq$libresoc.v:122010$4573_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $eq $eq$libresoc.v:121937$4576 + cell $eq $eq$libresoc.v:122013$4576 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -189967,10 +190030,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \dec_BRANCH_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:121937$4576_Y + connect \Y $eq$libresoc.v:122013$4576_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $eq $eq$libresoc.v:121943$4582 + cell $eq $eq$libresoc.v:122019$4582 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -189978,26 +190041,26 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \dec_BRANCH_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:121943$4582_Y + connect \Y $eq$libresoc.v:122019$4582_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $not $not$libresoc.v:121921$4560 + cell $not $not$libresoc.v:121997$4560 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:121921$4560_Y + connect \Y $not$libresoc.v:121997$4560_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $not $not$libresoc.v:121939$4578 + cell $not $not$libresoc.v:122015$4578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:121939$4578_Y + connect \Y $not$libresoc.v:122015$4578_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $or $or$libresoc.v:121925$4564 + cell $or $or$libresoc.v:122001$4564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190005,10 +190068,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:121925$4564_Y + connect \Y $or$libresoc.v:122001$4564_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:121928$4567 + cell $or $or$libresoc.v:122004$4567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190016,10 +190079,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:121928$4567_Y + connect \Y $or$libresoc.v:122004$4567_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:121931$4570 + cell $or $or$libresoc.v:122007$4570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190027,10 +190090,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:121931$4570_Y + connect \Y $or$libresoc.v:122007$4570_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $or $or$libresoc.v:121933$4572 + cell $or $or$libresoc.v:122009$4572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190038,10 +190101,10 @@ module \dec_BRANCH parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:121933$4572_Y + connect \Y $or$libresoc.v:122009$4572_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:121944.13-121966.4" + attribute \src "libresoc.v:122020.13-122042.4" cell \dec$141 \dec connect \BRANCH_BD \dec_BRANCH_BD connect \BRANCH_DS \dec_BRANCH_DS @@ -190066,7 +190129,7 @@ module \dec_BRANCH connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121967.16-121978.4" + attribute \src "libresoc.v:122043.16-122054.4" cell \dec_bi$144 \dec_bi connect \BRANCH_BD \dec_BRANCH_BD connect \BRANCH_DS \dec_BRANCH_DS @@ -190080,33 +190143,33 @@ module \dec_BRANCH connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121979.16-121983.4" + attribute \src "libresoc.v:122055.16-122059.4" cell \dec_oe$143 \dec_oe connect \BRANCH_OE \dec_BRANCH_OE connect \BRANCH_internal_op \dec_BRANCH_internal_op connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:121984.16-121987.4" + attribute \src "libresoc.v:122060.16-122063.4" cell \dec_rc$142 \dec_rc connect \BRANCH_Rc \dec_BRANCH_Rc connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:121559.7-121559.20" - process $proc$libresoc.v:121559$4586 + attribute \src "libresoc.v:121635.7-121635.20" + process $proc$libresoc.v:121635$4586 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:121988.3-122002.6" - process $proc$libresoc.v:121988$4583 + attribute \src "libresoc.v:122064.3-122078.6" + process $proc$libresoc.v:122064$4583 assign { } { } assign $0\BRANCH__fn_unit[13:0] $1\BRANCH__fn_unit[13:0] - attribute \src "libresoc.v:121989.5-121989.29" + attribute \src "libresoc.v:122065.5-122065.29" switch \initial - attribute \src "libresoc.v:121989.9-121989.17" + attribute \src "libresoc.v:122065.9-122065.17" case 1'1 case end @@ -190128,14 +190191,14 @@ module \dec_BRANCH sync always update \BRANCH__fn_unit $0\BRANCH__fn_unit[13:0] end - attribute \src "libresoc.v:122003.3-122012.6" - process $proc$libresoc.v:122003$4584 + attribute \src "libresoc.v:122079.3-122088.6" + process $proc$libresoc.v:122079$4584 assign { } { } assign { } { } assign $0\BRANCH__lk[0:0] $1\BRANCH__lk[0:0] - attribute \src "libresoc.v:122004.5-122004.29" + attribute \src "libresoc.v:122080.5-122080.29" switch \initial - attribute \src "libresoc.v:122004.9-122004.17" + attribute \src "libresoc.v:122080.9-122080.17" case 1'1 case end @@ -190151,14 +190214,14 @@ module \dec_BRANCH sync always update \BRANCH__lk $0\BRANCH__lk[0:0] end - attribute \src "libresoc.v:122013.3-122025.6" - process $proc$libresoc.v:122013$4585 + attribute \src "libresoc.v:122089.3-122101.6" + process $proc$libresoc.v:122089$4585 assign { } { } assign { } { } assign $0\BRANCH__insn_type[6:0] $1\BRANCH__insn_type[6:0] - attribute \src "libresoc.v:122014.5-122014.29" + attribute \src "libresoc.v:122090.5-122090.29" switch \initial - attribute \src "libresoc.v:122014.9-122014.17" + attribute \src "libresoc.v:122090.9-122090.17" case 1'1 case end @@ -190178,30 +190241,30 @@ module \dec_BRANCH sync always update \BRANCH__insn_type $0\BRANCH__insn_type[6:0] end - connect \$10 $and$libresoc.v:121920$4559_Y - connect \$12 $not$libresoc.v:121921$4560_Y - connect \$14 $and$libresoc.v:121922$4561_Y - connect \$16 $eq$libresoc.v:121923$4562_Y - connect \$18 $eq$libresoc.v:121924$4563_Y - connect \$20 $or$libresoc.v:121925$4564_Y - connect \$22 $eq$libresoc.v:121926$4565_Y - connect \$24 $eq$libresoc.v:121927$4566_Y - connect \$26 $or$libresoc.v:121928$4567_Y - connect \$28 $eq$libresoc.v:121929$4568_Y - connect \$2 $eq$libresoc.v:121930$4569_Y - connect \$30 $or$libresoc.v:121931$4570_Y - connect \$32 $eq$libresoc.v:121932$4571_Y - connect \$34 $or$libresoc.v:121933$4572_Y - connect \$36 $eq$libresoc.v:121934$4573_Y - connect \$38 $and$libresoc.v:121935$4574_Y - connect \$40 $and$libresoc.v:121936$4575_Y - connect \$42 $eq$libresoc.v:121937$4576_Y - connect \$44 $and$libresoc.v:121938$4577_Y - connect \$46 $not$libresoc.v:121939$4578_Y - connect \$48 $and$libresoc.v:121940$4579_Y - connect \$4 $and$libresoc.v:121941$4580_Y - connect \$6 $and$libresoc.v:121942$4581_Y - connect \$8 $eq$libresoc.v:121943$4582_Y + connect \$10 $and$libresoc.v:121996$4559_Y + connect \$12 $not$libresoc.v:121997$4560_Y + connect \$14 $and$libresoc.v:121998$4561_Y + connect \$16 $eq$libresoc.v:121999$4562_Y + connect \$18 $eq$libresoc.v:122000$4563_Y + connect \$20 $or$libresoc.v:122001$4564_Y + connect \$22 $eq$libresoc.v:122002$4565_Y + connect \$24 $eq$libresoc.v:122003$4566_Y + connect \$26 $or$libresoc.v:122004$4567_Y + connect \$28 $eq$libresoc.v:122005$4568_Y + connect \$2 $eq$libresoc.v:122006$4569_Y + connect \$30 $or$libresoc.v:122007$4570_Y + connect \$32 $eq$libresoc.v:122008$4571_Y + connect \$34 $or$libresoc.v:122009$4572_Y + connect \$36 $eq$libresoc.v:122010$4573_Y + connect \$38 $and$libresoc.v:122011$4574_Y + connect \$40 $and$libresoc.v:122012$4575_Y + connect \$42 $eq$libresoc.v:122013$4576_Y + connect \$44 $and$libresoc.v:122014$4577_Y + connect \$46 $not$libresoc.v:122015$4578_Y + connect \$48 $and$libresoc.v:122016$4579_Y + connect \$4 $and$libresoc.v:122017$4580_Y + connect \$6 $and$libresoc.v:122018$4581_Y + connect \$8 $eq$libresoc.v:122019$4582_Y connect \BRANCH__is_32bit \dec_BRANCH_is_32b connect { \BRANCH__imm_data__ok \BRANCH__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } connect \dec_bi_sel_in \dec_BRANCH_in2_sel @@ -190215,69 +190278,69 @@ module \dec_BRANCH connect \insn_in \dec_opcode_in connect \BRANCH__insn \dec_opcode_in end -attribute \src "libresoc.v:122042.1-122414.10" +attribute \src "libresoc.v:122118.1-122490.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR" attribute \generator "nMigen" module \dec_CR - attribute \src "libresoc.v:122391.3-122405.6" + attribute \src "libresoc.v:122467.3-122481.6" wire width 14 $0\CR__fn_unit[13:0] - attribute \src "libresoc.v:122378.3-122390.6" + attribute \src "libresoc.v:122454.3-122466.6" wire width 7 $0\CR__insn_type[6:0] - attribute \src "libresoc.v:122043.7-122043.20" + attribute \src "libresoc.v:122119.7-122119.20" wire $0\initial[0:0] - attribute \src "libresoc.v:122391.3-122405.6" + attribute \src "libresoc.v:122467.3-122481.6" wire width 14 $1\CR__fn_unit[13:0] - attribute \src "libresoc.v:122378.3-122390.6" + attribute \src "libresoc.v:122454.3-122466.6" wire width 7 $1\CR__insn_type[6:0] - attribute \src "libresoc.v:122333.18-122333.113" - wire $and$libresoc.v:122333$4587_Y - attribute \src "libresoc.v:122335.18-122335.110" - wire $and$libresoc.v:122335$4589_Y - attribute \src "libresoc.v:122348.18-122348.114" - wire $and$libresoc.v:122348$4602_Y - attribute \src "libresoc.v:122349.18-122349.116" - wire $and$libresoc.v:122349$4603_Y - attribute \src "libresoc.v:122351.18-122351.114" - wire $and$libresoc.v:122351$4605_Y - attribute \src "libresoc.v:122353.18-122353.110" - wire $and$libresoc.v:122353$4607_Y - attribute \src "libresoc.v:122354.17-122354.112" - wire $and$libresoc.v:122354$4608_Y - attribute \src "libresoc.v:122355.17-122355.114" - wire $and$libresoc.v:122355$4609_Y - attribute \src "libresoc.v:122336.18-122336.125" - wire $eq$libresoc.v:122336$4590_Y - attribute \src "libresoc.v:122337.18-122337.125" - wire $eq$libresoc.v:122337$4591_Y - attribute \src "libresoc.v:122339.18-122339.110" - wire $eq$libresoc.v:122339$4593_Y - attribute \src "libresoc.v:122340.18-122340.110" - wire $eq$libresoc.v:122340$4594_Y - attribute \src "libresoc.v:122342.18-122342.112" - wire $eq$libresoc.v:122342$4596_Y - attribute \src "libresoc.v:122343.17-122343.129" - wire $eq$libresoc.v:122343$4597_Y - attribute \src "libresoc.v:122345.18-122345.110" - wire $eq$libresoc.v:122345$4599_Y - attribute \src "libresoc.v:122347.18-122347.130" - wire $eq$libresoc.v:122347$4601_Y - attribute \src "libresoc.v:122350.18-122350.130" - wire $eq$libresoc.v:122350$4604_Y - attribute \src "libresoc.v:122356.17-122356.129" - wire $eq$libresoc.v:122356$4610_Y - attribute \src "libresoc.v:122334.18-122334.110" - wire $not$libresoc.v:122334$4588_Y - attribute \src "libresoc.v:122352.18-122352.110" - wire $not$libresoc.v:122352$4606_Y - attribute \src "libresoc.v:122338.18-122338.110" - wire $or$libresoc.v:122338$4592_Y - attribute \src "libresoc.v:122341.18-122341.110" - wire $or$libresoc.v:122341$4595_Y - attribute \src "libresoc.v:122344.18-122344.110" - wire $or$libresoc.v:122344$4598_Y - attribute \src "libresoc.v:122346.18-122346.110" - wire $or$libresoc.v:122346$4600_Y + attribute \src "libresoc.v:122409.18-122409.113" + wire $and$libresoc.v:122409$4587_Y + attribute \src "libresoc.v:122411.18-122411.110" + wire $and$libresoc.v:122411$4589_Y + attribute \src "libresoc.v:122424.18-122424.114" + wire $and$libresoc.v:122424$4602_Y + attribute \src "libresoc.v:122425.18-122425.116" + wire $and$libresoc.v:122425$4603_Y + attribute \src "libresoc.v:122427.18-122427.114" + wire $and$libresoc.v:122427$4605_Y + attribute \src "libresoc.v:122429.18-122429.110" + wire $and$libresoc.v:122429$4607_Y + attribute \src "libresoc.v:122430.17-122430.112" + wire $and$libresoc.v:122430$4608_Y + attribute \src "libresoc.v:122431.17-122431.114" + wire $and$libresoc.v:122431$4609_Y + attribute \src "libresoc.v:122412.18-122412.125" + wire $eq$libresoc.v:122412$4590_Y + attribute \src "libresoc.v:122413.18-122413.125" + wire $eq$libresoc.v:122413$4591_Y + attribute \src "libresoc.v:122415.18-122415.110" + wire $eq$libresoc.v:122415$4593_Y + attribute \src "libresoc.v:122416.18-122416.110" + wire $eq$libresoc.v:122416$4594_Y + attribute \src "libresoc.v:122418.18-122418.112" + wire $eq$libresoc.v:122418$4596_Y + attribute \src "libresoc.v:122419.17-122419.129" + wire $eq$libresoc.v:122419$4597_Y + attribute \src "libresoc.v:122421.18-122421.110" + wire $eq$libresoc.v:122421$4599_Y + attribute \src "libresoc.v:122423.18-122423.130" + wire $eq$libresoc.v:122423$4601_Y + attribute \src "libresoc.v:122426.18-122426.130" + wire $eq$libresoc.v:122426$4604_Y + attribute \src "libresoc.v:122432.17-122432.129" + wire $eq$libresoc.v:122432$4610_Y + attribute \src "libresoc.v:122410.18-122410.110" + wire $not$libresoc.v:122410$4588_Y + attribute \src "libresoc.v:122428.18-122428.110" + wire $not$libresoc.v:122428$4606_Y + attribute \src "libresoc.v:122414.18-122414.110" + wire $or$libresoc.v:122414$4592_Y + attribute \src "libresoc.v:122417.18-122417.110" + wire $or$libresoc.v:122417$4595_Y + attribute \src "libresoc.v:122420.18-122420.110" + wire $or$libresoc.v:122420$4598_Y + attribute \src "libresoc.v:122422.18-122422.110" + wire $or$libresoc.v:122422$4600_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" @@ -190553,7 +190616,7 @@ module \dec_CR attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:122043.7-122043.15" + attribute \src "libresoc.v:122119.7-122119.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" wire width 32 \insn_in @@ -190568,7 +190631,7 @@ module \dec_CR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" wire width 10 \spr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:122333$4587 + cell $and $and$libresoc.v:122409$4587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190576,10 +190639,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:122333$4587_Y + connect \Y $and$libresoc.v:122409$4587_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:122335$4589 + cell $and $and$libresoc.v:122411$4589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190587,10 +190650,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:122335$4589_Y + connect \Y $and$libresoc.v:122411$4589_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:122348$4602 + cell $and $and$libresoc.v:122424$4602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190598,10 +190661,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:122348$4602_Y + connect \Y $and$libresoc.v:122424$4602_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:122349$4603 + cell $and $and$libresoc.v:122425$4603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190609,10 +190672,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:122349$4603_Y + connect \Y $and$libresoc.v:122425$4603_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:122351$4605 + cell $and $and$libresoc.v:122427$4605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190620,10 +190683,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:122351$4605_Y + connect \Y $and$libresoc.v:122427$4605_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:122353$4607 + cell $and $and$libresoc.v:122429$4607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190631,10 +190694,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:122353$4607_Y + connect \Y $and$libresoc.v:122429$4607_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:122354$4608 + cell $and $and$libresoc.v:122430$4608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190642,10 +190705,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:122354$4608_Y + connect \Y $and$libresoc.v:122430$4608_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:122355$4609 + cell $and $and$libresoc.v:122431$4609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190653,10 +190716,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:122355$4609_Y + connect \Y $and$libresoc.v:122431$4609_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $eq $eq$libresoc.v:122336$4590 + cell $eq $eq$libresoc.v:122412$4590 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -190664,10 +190727,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \dec_CR_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:122336$4590_Y + connect \Y $eq$libresoc.v:122412$4590_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $eq $eq$libresoc.v:122337$4591 + cell $eq $eq$libresoc.v:122413$4591 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -190675,10 +190738,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \dec_CR_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:122337$4591_Y + connect \Y $eq$libresoc.v:122413$4591_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:122339$4593 + cell $eq $eq$libresoc.v:122415$4593 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -190686,10 +190749,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:122339$4593_Y + connect \Y $eq$libresoc.v:122415$4593_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:122340$4594 + cell $eq $eq$libresoc.v:122416$4594 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -190697,10 +190760,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:122340$4594_Y + connect \Y $eq$libresoc.v:122416$4594_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:122342$4596 + cell $eq $eq$libresoc.v:122418$4596 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -190708,10 +190771,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:122342$4596_Y + connect \Y $eq$libresoc.v:122418$4596_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $eq $eq$libresoc.v:122343$4597 + cell $eq $eq$libresoc.v:122419$4597 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -190719,10 +190782,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \dec_CR_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:122343$4597_Y + connect \Y $eq$libresoc.v:122419$4597_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $eq $eq$libresoc.v:122345$4599 + cell $eq $eq$libresoc.v:122421$4599 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -190730,10 +190793,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:122345$4599_Y + connect \Y $eq$libresoc.v:122421$4599_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $eq $eq$libresoc.v:122347$4601 + cell $eq $eq$libresoc.v:122423$4601 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -190741,10 +190804,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \dec_CR_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:122347$4601_Y + connect \Y $eq$libresoc.v:122423$4601_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $eq $eq$libresoc.v:122350$4604 + cell $eq $eq$libresoc.v:122426$4604 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -190752,10 +190815,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \dec_CR_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:122350$4604_Y + connect \Y $eq$libresoc.v:122426$4604_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $eq $eq$libresoc.v:122356$4610 + cell $eq $eq$libresoc.v:122432$4610 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -190763,26 +190826,26 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \dec_CR_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:122356$4610_Y + connect \Y $eq$libresoc.v:122432$4610_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $not $not$libresoc.v:122334$4588 + cell $not $not$libresoc.v:122410$4588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:122334$4588_Y + connect \Y $not$libresoc.v:122410$4588_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $not $not$libresoc.v:122352$4606 + cell $not $not$libresoc.v:122428$4606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:122352$4606_Y + connect \Y $not$libresoc.v:122428$4606_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $or $or$libresoc.v:122338$4592 + cell $or $or$libresoc.v:122414$4592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190790,10 +190853,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:122338$4592_Y + connect \Y $or$libresoc.v:122414$4592_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:122341$4595 + cell $or $or$libresoc.v:122417$4595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190801,10 +190864,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:122341$4595_Y + connect \Y $or$libresoc.v:122417$4595_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:122344$4598 + cell $or $or$libresoc.v:122420$4598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190812,10 +190875,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:122344$4598_Y + connect \Y $or$libresoc.v:122420$4598_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $or $or$libresoc.v:122346$4600 + cell $or $or$libresoc.v:122422$4600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -190823,10 +190886,10 @@ module \dec_CR parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:122346$4600_Y + connect \Y $or$libresoc.v:122422$4600_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:122357.13-122368.4" + attribute \src "libresoc.v:122433.13-122444.4" cell \dec$138 \dec connect \CR_OE \dec_CR_OE connect \CR_Rc \dec_CR_Rc @@ -190840,34 +190903,34 @@ module \dec_CR connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:122369.16-122373.4" + attribute \src "libresoc.v:122445.16-122449.4" cell \dec_oe$140 \dec_oe connect \CR_OE \dec_CR_OE connect \CR_internal_op \dec_CR_internal_op connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:122374.16-122377.4" + attribute \src "libresoc.v:122450.16-122453.4" cell \dec_rc$139 \dec_rc connect \CR_Rc \dec_CR_Rc connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:122043.7-122043.20" - process $proc$libresoc.v:122043$4613 + attribute \src "libresoc.v:122119.7-122119.20" + process $proc$libresoc.v:122119$4613 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:122378.3-122390.6" - process $proc$libresoc.v:122378$4611 + attribute \src "libresoc.v:122454.3-122466.6" + process $proc$libresoc.v:122454$4611 assign { } { } assign { } { } assign $0\CR__insn_type[6:0] $1\CR__insn_type[6:0] - attribute \src "libresoc.v:122379.5-122379.29" + attribute \src "libresoc.v:122455.5-122455.29" switch \initial - attribute \src "libresoc.v:122379.9-122379.17" + attribute \src "libresoc.v:122455.9-122455.17" case 1'1 case end @@ -190887,13 +190950,13 @@ module \dec_CR sync always update \CR__insn_type $0\CR__insn_type[6:0] end - attribute \src "libresoc.v:122391.3-122405.6" - process $proc$libresoc.v:122391$4612 + attribute \src "libresoc.v:122467.3-122481.6" + process $proc$libresoc.v:122467$4612 assign { } { } assign $0\CR__fn_unit[13:0] $1\CR__fn_unit[13:0] - attribute \src "libresoc.v:122392.5-122392.29" + attribute \src "libresoc.v:122468.5-122468.29" switch \initial - attribute \src "libresoc.v:122392.9-122392.17" + attribute \src "libresoc.v:122468.9-122468.17" case 1'1 case end @@ -190915,30 +190978,30 @@ module \dec_CR sync always update \CR__fn_unit $0\CR__fn_unit[13:0] end - connect \$10 $and$libresoc.v:122333$4587_Y - connect \$12 $not$libresoc.v:122334$4588_Y - connect \$14 $and$libresoc.v:122335$4589_Y - connect \$16 $eq$libresoc.v:122336$4590_Y - connect \$18 $eq$libresoc.v:122337$4591_Y - connect \$20 $or$libresoc.v:122338$4592_Y - connect \$22 $eq$libresoc.v:122339$4593_Y - connect \$24 $eq$libresoc.v:122340$4594_Y - connect \$26 $or$libresoc.v:122341$4595_Y - connect \$28 $eq$libresoc.v:122342$4596_Y - connect \$2 $eq$libresoc.v:122343$4597_Y - connect \$30 $or$libresoc.v:122344$4598_Y - connect \$32 $eq$libresoc.v:122345$4599_Y - connect \$34 $or$libresoc.v:122346$4600_Y - connect \$36 $eq$libresoc.v:122347$4601_Y - connect \$38 $and$libresoc.v:122348$4602_Y - connect \$40 $and$libresoc.v:122349$4603_Y - connect \$42 $eq$libresoc.v:122350$4604_Y - connect \$44 $and$libresoc.v:122351$4605_Y - connect \$46 $not$libresoc.v:122352$4606_Y - connect \$48 $and$libresoc.v:122353$4607_Y - connect \$4 $and$libresoc.v:122354$4608_Y - connect \$6 $and$libresoc.v:122355$4609_Y - connect \$8 $eq$libresoc.v:122356$4610_Y + connect \$10 $and$libresoc.v:122409$4587_Y + connect \$12 $not$libresoc.v:122410$4588_Y + connect \$14 $and$libresoc.v:122411$4589_Y + connect \$16 $eq$libresoc.v:122412$4590_Y + connect \$18 $eq$libresoc.v:122413$4591_Y + connect \$20 $or$libresoc.v:122414$4592_Y + connect \$22 $eq$libresoc.v:122415$4593_Y + connect \$24 $eq$libresoc.v:122416$4594_Y + connect \$26 $or$libresoc.v:122417$4595_Y + connect \$28 $eq$libresoc.v:122418$4596_Y + connect \$2 $eq$libresoc.v:122419$4597_Y + connect \$30 $or$libresoc.v:122420$4598_Y + connect \$32 $eq$libresoc.v:122421$4599_Y + connect \$34 $or$libresoc.v:122422$4600_Y + connect \$36 $eq$libresoc.v:122423$4601_Y + connect \$38 $and$libresoc.v:122424$4602_Y + connect \$40 $and$libresoc.v:122425$4603_Y + connect \$42 $eq$libresoc.v:122426$4604_Y + connect \$44 $and$libresoc.v:122427$4605_Y + connect \$46 $not$libresoc.v:122428$4606_Y + connect \$48 $and$libresoc.v:122429$4607_Y + connect \$4 $and$libresoc.v:122430$4608_Y + connect \$6 $and$libresoc.v:122431$4609_Y + connect \$8 $eq$libresoc.v:122432$4610_Y connect \is_mmu_spr \$34 connect \is_spr_mv \$20 connect \spr { \dec_CR_SPR [4:0] \dec_CR_SPR [9:5] } @@ -190948,73 +191011,73 @@ module \dec_CR connect \insn_in \dec_opcode_in connect \CR__insn \dec_opcode_in end -attribute \src "libresoc.v:122418.1-123001.10" +attribute \src "libresoc.v:122494.1-123077.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV" attribute \generator "nMigen" module \dec_DIV - attribute \src "libresoc.v:122964.3-122978.6" + attribute \src "libresoc.v:123040.3-123054.6" wire width 14 $0\DIV__fn_unit[13:0] - attribute \src "libresoc.v:122951.3-122963.6" + attribute \src "libresoc.v:123027.3-123039.6" wire width 7 $0\DIV__insn_type[6:0] - attribute \src "libresoc.v:122936.3-122950.6" + attribute \src "libresoc.v:123012.3-123026.6" wire $0\DIV__write_cr0[0:0] - attribute \src "libresoc.v:122419.7-122419.20" + attribute \src "libresoc.v:122495.7-122495.20" wire $0\initial[0:0] - attribute \src "libresoc.v:122964.3-122978.6" + attribute \src "libresoc.v:123040.3-123054.6" wire width 14 $1\DIV__fn_unit[13:0] - attribute \src "libresoc.v:122951.3-122963.6" + attribute \src "libresoc.v:123027.3-123039.6" wire width 7 $1\DIV__insn_type[6:0] - attribute \src "libresoc.v:122936.3-122950.6" + attribute \src "libresoc.v:123012.3-123026.6" wire $1\DIV__write_cr0[0:0] - attribute \src "libresoc.v:122852.18-122852.113" - wire $and$libresoc.v:122852$4614_Y - attribute \src "libresoc.v:122854.18-122854.110" - wire $and$libresoc.v:122854$4616_Y - attribute \src "libresoc.v:122867.18-122867.114" - wire $and$libresoc.v:122867$4629_Y - attribute \src "libresoc.v:122868.18-122868.116" - wire $and$libresoc.v:122868$4630_Y - attribute \src "libresoc.v:122870.18-122870.114" - wire $and$libresoc.v:122870$4632_Y - attribute \src "libresoc.v:122872.18-122872.110" - wire $and$libresoc.v:122872$4634_Y - attribute \src "libresoc.v:122873.17-122873.112" - wire $and$libresoc.v:122873$4635_Y - attribute \src "libresoc.v:122874.17-122874.114" - wire $and$libresoc.v:122874$4636_Y - attribute \src "libresoc.v:122855.18-122855.126" - wire $eq$libresoc.v:122855$4617_Y - attribute \src "libresoc.v:122856.18-122856.126" - wire $eq$libresoc.v:122856$4618_Y - attribute \src "libresoc.v:122858.18-122858.110" - wire $eq$libresoc.v:122858$4620_Y - attribute \src "libresoc.v:122859.18-122859.110" - wire $eq$libresoc.v:122859$4621_Y - attribute \src "libresoc.v:122861.18-122861.112" - wire $eq$libresoc.v:122861$4623_Y - attribute \src "libresoc.v:122862.17-122862.130" - wire $eq$libresoc.v:122862$4624_Y - attribute \src "libresoc.v:122864.18-122864.110" - wire $eq$libresoc.v:122864$4626_Y - attribute \src "libresoc.v:122866.18-122866.131" - wire $eq$libresoc.v:122866$4628_Y - attribute \src "libresoc.v:122869.18-122869.131" - wire $eq$libresoc.v:122869$4631_Y - attribute \src "libresoc.v:122875.17-122875.130" - wire $eq$libresoc.v:122875$4637_Y - attribute \src "libresoc.v:122853.18-122853.110" - wire $not$libresoc.v:122853$4615_Y - attribute \src "libresoc.v:122871.18-122871.110" - wire $not$libresoc.v:122871$4633_Y - attribute \src "libresoc.v:122857.18-122857.110" - wire $or$libresoc.v:122857$4619_Y - attribute \src "libresoc.v:122860.18-122860.110" - wire $or$libresoc.v:122860$4622_Y - attribute \src "libresoc.v:122863.18-122863.110" - wire $or$libresoc.v:122863$4625_Y - attribute \src "libresoc.v:122865.18-122865.110" - wire $or$libresoc.v:122865$4627_Y + attribute \src "libresoc.v:122928.18-122928.113" + wire $and$libresoc.v:122928$4614_Y + attribute \src "libresoc.v:122930.18-122930.110" + wire $and$libresoc.v:122930$4616_Y + attribute \src "libresoc.v:122943.18-122943.114" + wire $and$libresoc.v:122943$4629_Y + attribute \src "libresoc.v:122944.18-122944.116" + wire $and$libresoc.v:122944$4630_Y + attribute \src "libresoc.v:122946.18-122946.114" + wire $and$libresoc.v:122946$4632_Y + attribute \src "libresoc.v:122948.18-122948.110" + wire $and$libresoc.v:122948$4634_Y + attribute \src "libresoc.v:122949.17-122949.112" + wire $and$libresoc.v:122949$4635_Y + attribute \src "libresoc.v:122950.17-122950.114" + wire $and$libresoc.v:122950$4636_Y + attribute \src "libresoc.v:122931.18-122931.126" + wire $eq$libresoc.v:122931$4617_Y + attribute \src "libresoc.v:122932.18-122932.126" + wire $eq$libresoc.v:122932$4618_Y + attribute \src "libresoc.v:122934.18-122934.110" + wire $eq$libresoc.v:122934$4620_Y + attribute \src "libresoc.v:122935.18-122935.110" + wire $eq$libresoc.v:122935$4621_Y + attribute \src "libresoc.v:122937.18-122937.112" + wire $eq$libresoc.v:122937$4623_Y + attribute \src "libresoc.v:122938.17-122938.130" + wire $eq$libresoc.v:122938$4624_Y + attribute \src "libresoc.v:122940.18-122940.110" + wire $eq$libresoc.v:122940$4626_Y + attribute \src "libresoc.v:122942.18-122942.131" + wire $eq$libresoc.v:122942$4628_Y + attribute \src "libresoc.v:122945.18-122945.131" + wire $eq$libresoc.v:122945$4631_Y + attribute \src "libresoc.v:122951.17-122951.130" + wire $eq$libresoc.v:122951$4637_Y + attribute \src "libresoc.v:122929.18-122929.110" + wire $not$libresoc.v:122929$4615_Y + attribute \src "libresoc.v:122947.18-122947.110" + wire $not$libresoc.v:122947$4633_Y + attribute \src "libresoc.v:122933.18-122933.110" + wire $or$libresoc.v:122933$4619_Y + attribute \src "libresoc.v:122936.18-122936.110" + wire $or$libresoc.v:122936$4622_Y + attribute \src "libresoc.v:122939.18-122939.110" + wire $or$libresoc.v:122939$4625_Y + attribute \src "libresoc.v:122941.18-122941.110" + wire $or$libresoc.v:122941$4627_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" @@ -191430,7 +191493,7 @@ module \dec_DIV attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:122419.7-122419.15" + attribute \src "libresoc.v:122495.7-122495.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" wire width 32 \insn_in @@ -191447,7 +191510,7 @@ module \dec_DIV attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" wire input 2 \sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:122852$4614 + cell $and $and$libresoc.v:122928$4614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191455,10 +191518,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:122852$4614_Y + connect \Y $and$libresoc.v:122928$4614_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:122854$4616 + cell $and $and$libresoc.v:122930$4616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191466,10 +191529,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:122854$4616_Y + connect \Y $and$libresoc.v:122930$4616_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:122867$4629 + cell $and $and$libresoc.v:122943$4629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191477,10 +191540,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:122867$4629_Y + connect \Y $and$libresoc.v:122943$4629_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:122868$4630 + cell $and $and$libresoc.v:122944$4630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191488,10 +191551,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:122868$4630_Y + connect \Y $and$libresoc.v:122944$4630_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:122870$4632 + cell $and $and$libresoc.v:122946$4632 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191499,10 +191562,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:122870$4632_Y + connect \Y $and$libresoc.v:122946$4632_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:122872$4634 + cell $and $and$libresoc.v:122948$4634 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191510,10 +191573,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:122872$4634_Y + connect \Y $and$libresoc.v:122948$4634_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:122873$4635 + cell $and $and$libresoc.v:122949$4635 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191521,10 +191584,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:122873$4635_Y + connect \Y $and$libresoc.v:122949$4635_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:122874$4636 + cell $and $and$libresoc.v:122950$4636 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191532,10 +191595,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:122874$4636_Y + connect \Y $and$libresoc.v:122950$4636_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $eq $eq$libresoc.v:122855$4617 + cell $eq $eq$libresoc.v:122931$4617 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -191543,10 +191606,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \dec_DIV_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:122855$4617_Y + connect \Y $eq$libresoc.v:122931$4617_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $eq $eq$libresoc.v:122856$4618 + cell $eq $eq$libresoc.v:122932$4618 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -191554,10 +191617,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \dec_DIV_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:122856$4618_Y + connect \Y $eq$libresoc.v:122932$4618_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:122858$4620 + cell $eq $eq$libresoc.v:122934$4620 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -191565,10 +191628,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:122858$4620_Y + connect \Y $eq$libresoc.v:122934$4620_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:122859$4621 + cell $eq $eq$libresoc.v:122935$4621 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -191576,10 +191639,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:122859$4621_Y + connect \Y $eq$libresoc.v:122935$4621_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:122861$4623 + cell $eq $eq$libresoc.v:122937$4623 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -191587,10 +191650,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:122861$4623_Y + connect \Y $eq$libresoc.v:122937$4623_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $eq $eq$libresoc.v:122862$4624 + cell $eq $eq$libresoc.v:122938$4624 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -191598,10 +191661,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \dec_DIV_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:122862$4624_Y + connect \Y $eq$libresoc.v:122938$4624_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $eq $eq$libresoc.v:122864$4626 + cell $eq $eq$libresoc.v:122940$4626 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -191609,10 +191672,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:122864$4626_Y + connect \Y $eq$libresoc.v:122940$4626_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $eq $eq$libresoc.v:122866$4628 + cell $eq $eq$libresoc.v:122942$4628 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -191620,10 +191683,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \dec_DIV_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:122866$4628_Y + connect \Y $eq$libresoc.v:122942$4628_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $eq $eq$libresoc.v:122869$4631 + cell $eq $eq$libresoc.v:122945$4631 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -191631,10 +191694,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \dec_DIV_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:122869$4631_Y + connect \Y $eq$libresoc.v:122945$4631_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $eq $eq$libresoc.v:122875$4637 + cell $eq $eq$libresoc.v:122951$4637 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -191642,26 +191705,26 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \dec_DIV_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:122875$4637_Y + connect \Y $eq$libresoc.v:122951$4637_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $not $not$libresoc.v:122853$4615 + cell $not $not$libresoc.v:122929$4615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:122853$4615_Y + connect \Y $not$libresoc.v:122929$4615_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $not $not$libresoc.v:122871$4633 + cell $not $not$libresoc.v:122947$4633 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:122871$4633_Y + connect \Y $not$libresoc.v:122947$4633_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $or $or$libresoc.v:122857$4619 + cell $or $or$libresoc.v:122933$4619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191669,10 +191732,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:122857$4619_Y + connect \Y $or$libresoc.v:122933$4619_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:122860$4622 + cell $or $or$libresoc.v:122936$4622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191680,10 +191743,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:122860$4622_Y + connect \Y $or$libresoc.v:122936$4622_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:122863$4625 + cell $or $or$libresoc.v:122939$4625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191691,10 +191754,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:122863$4625_Y + connect \Y $or$libresoc.v:122939$4625_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $or $or$libresoc.v:122865$4627 + cell $or $or$libresoc.v:122941$4627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -191702,10 +191765,10 @@ module \dec_DIV parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:122865$4627_Y + connect \Y $or$libresoc.v:122941$4627_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:122876.13-122904.4" + attribute \src "libresoc.v:122952.13-122980.4" cell \dec$153 \dec connect \DIV_BD \dec_DIV_BD connect \DIV_DS \dec_DIV_DS @@ -191736,7 +191799,7 @@ module \dec_DIV connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:122905.16-122910.4" + attribute \src "libresoc.v:122981.16-122986.4" cell \dec_ai$156 \dec_ai connect \DIV_RA \dec_DIV_RA connect \immz_out \dec_ai_immz_out @@ -191744,7 +191807,7 @@ module \dec_DIV connect \sv_nz \dec_ai_sv_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:122911.16-122922.4" + attribute \src "libresoc.v:122987.16-122998.4" cell \dec_bi$157 \dec_bi connect \DIV_BD \dec_DIV_BD connect \DIV_DS \dec_DIV_DS @@ -191758,7 +191821,7 @@ module \dec_DIV connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:122923.16-122929.4" + attribute \src "libresoc.v:122999.16-123005.4" cell \dec_oe$155 \dec_oe connect \DIV_OE \dec_DIV_OE connect \DIV_internal_op \dec_DIV_internal_op @@ -191767,29 +191830,29 @@ module \dec_DIV connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:122930.16-122935.4" + attribute \src "libresoc.v:123006.16-123011.4" cell \dec_rc$154 \dec_rc connect \DIV_Rc \dec_DIV_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:122419.7-122419.20" - process $proc$libresoc.v:122419$4641 + attribute \src "libresoc.v:122495.7-122495.20" + process $proc$libresoc.v:122495$4641 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:122936.3-122950.6" - process $proc$libresoc.v:122936$4638 + attribute \src "libresoc.v:123012.3-123026.6" + process $proc$libresoc.v:123012$4638 assign { } { } assign { } { } assign $0\DIV__write_cr0[0:0] $1\DIV__write_cr0[0:0] - attribute \src "libresoc.v:122937.5-122937.29" + attribute \src "libresoc.v:123013.5-123013.29" switch \initial - attribute \src "libresoc.v:122937.9-122937.17" + attribute \src "libresoc.v:123013.9-123013.17" case 1'1 case end @@ -191809,14 +191872,14 @@ module \dec_DIV sync always update \DIV__write_cr0 $0\DIV__write_cr0[0:0] end - attribute \src "libresoc.v:122951.3-122963.6" - process $proc$libresoc.v:122951$4639 + attribute \src "libresoc.v:123027.3-123039.6" + process $proc$libresoc.v:123027$4639 assign { } { } assign { } { } assign $0\DIV__insn_type[6:0] $1\DIV__insn_type[6:0] - attribute \src "libresoc.v:122952.5-122952.29" + attribute \src "libresoc.v:123028.5-123028.29" switch \initial - attribute \src "libresoc.v:122952.9-122952.17" + attribute \src "libresoc.v:123028.9-123028.17" case 1'1 case end @@ -191836,13 +191899,13 @@ module \dec_DIV sync always update \DIV__insn_type $0\DIV__insn_type[6:0] end - attribute \src "libresoc.v:122964.3-122978.6" - process $proc$libresoc.v:122964$4640 + attribute \src "libresoc.v:123040.3-123054.6" + process $proc$libresoc.v:123040$4640 assign { } { } assign $0\DIV__fn_unit[13:0] $1\DIV__fn_unit[13:0] - attribute \src "libresoc.v:122965.5-122965.29" + attribute \src "libresoc.v:123041.5-123041.29" switch \initial - attribute \src "libresoc.v:122965.9-122965.17" + attribute \src "libresoc.v:123041.9-123041.17" case 1'1 case end @@ -191864,30 +191927,30 @@ module \dec_DIV sync always update \DIV__fn_unit $0\DIV__fn_unit[13:0] end - connect \$10 $and$libresoc.v:122852$4614_Y - connect \$12 $not$libresoc.v:122853$4615_Y - connect \$14 $and$libresoc.v:122854$4616_Y - connect \$16 $eq$libresoc.v:122855$4617_Y - connect \$18 $eq$libresoc.v:122856$4618_Y - connect \$20 $or$libresoc.v:122857$4619_Y - connect \$22 $eq$libresoc.v:122858$4620_Y - connect \$24 $eq$libresoc.v:122859$4621_Y - connect \$26 $or$libresoc.v:122860$4622_Y - connect \$28 $eq$libresoc.v:122861$4623_Y - connect \$2 $eq$libresoc.v:122862$4624_Y - connect \$30 $or$libresoc.v:122863$4625_Y - connect \$32 $eq$libresoc.v:122864$4626_Y - connect \$34 $or$libresoc.v:122865$4627_Y - connect \$36 $eq$libresoc.v:122866$4628_Y - connect \$38 $and$libresoc.v:122867$4629_Y - connect \$40 $and$libresoc.v:122868$4630_Y - connect \$42 $eq$libresoc.v:122869$4631_Y - connect \$44 $and$libresoc.v:122870$4632_Y - connect \$46 $not$libresoc.v:122871$4633_Y - connect \$48 $and$libresoc.v:122872$4634_Y - connect \$4 $and$libresoc.v:122873$4635_Y - connect \$6 $and$libresoc.v:122874$4636_Y - connect \$8 $eq$libresoc.v:122875$4637_Y + connect \$10 $and$libresoc.v:122928$4614_Y + connect \$12 $not$libresoc.v:122929$4615_Y + connect \$14 $and$libresoc.v:122930$4616_Y + connect \$16 $eq$libresoc.v:122931$4617_Y + connect \$18 $eq$libresoc.v:122932$4618_Y + connect \$20 $or$libresoc.v:122933$4619_Y + connect \$22 $eq$libresoc.v:122934$4620_Y + connect \$24 $eq$libresoc.v:122935$4621_Y + connect \$26 $or$libresoc.v:122936$4622_Y + connect \$28 $eq$libresoc.v:122937$4623_Y + connect \$2 $eq$libresoc.v:122938$4624_Y + connect \$30 $or$libresoc.v:122939$4625_Y + connect \$32 $eq$libresoc.v:122940$4626_Y + connect \$34 $or$libresoc.v:122941$4627_Y + connect \$36 $eq$libresoc.v:122942$4628_Y + connect \$38 $and$libresoc.v:122943$4629_Y + connect \$40 $and$libresoc.v:122944$4630_Y + connect \$42 $eq$libresoc.v:122945$4631_Y + connect \$44 $and$libresoc.v:122946$4632_Y + connect \$46 $not$libresoc.v:122947$4633_Y + connect \$48 $and$libresoc.v:122948$4634_Y + connect \$4 $and$libresoc.v:122949$4635_Y + connect \$6 $and$libresoc.v:122950$4636_Y + connect \$8 $eq$libresoc.v:122951$4637_Y connect \DIV__is_signed \dec_DIV_sgn connect \DIV__is_32bit \dec_DIV_is_32b connect \DIV__output_carry \dec_DIV_cry_out @@ -191911,69 +191974,69 @@ module \dec_DIV connect \insn_in \dec_opcode_in connect \DIV__insn \dec_opcode_in end -attribute \src "libresoc.v:123005.1-123566.10" +attribute \src "libresoc.v:123081.1-123642.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST" attribute \generator "nMigen" module \dec_LDST - attribute \src "libresoc.v:123530.3-123544.6" + attribute \src "libresoc.v:123606.3-123620.6" wire width 14 $0\LDST__fn_unit[13:0] - attribute \src "libresoc.v:123517.3-123529.6" + attribute \src "libresoc.v:123593.3-123605.6" wire width 7 $0\LDST__insn_type[6:0] - attribute \src "libresoc.v:123006.7-123006.20" + attribute \src "libresoc.v:123082.7-123082.20" wire $0\initial[0:0] - attribute \src "libresoc.v:123530.3-123544.6" + attribute \src "libresoc.v:123606.3-123620.6" wire width 14 $1\LDST__fn_unit[13:0] - attribute \src "libresoc.v:123517.3-123529.6" + attribute \src "libresoc.v:123593.3-123605.6" wire width 7 $1\LDST__insn_type[6:0] - attribute \src "libresoc.v:123434.18-123434.113" - wire $and$libresoc.v:123434$4642_Y - attribute \src "libresoc.v:123436.18-123436.110" - wire $and$libresoc.v:123436$4644_Y - attribute \src "libresoc.v:123449.18-123449.114" - wire $and$libresoc.v:123449$4657_Y - attribute \src "libresoc.v:123450.18-123450.116" - wire $and$libresoc.v:123450$4658_Y - attribute \src "libresoc.v:123452.18-123452.114" - wire $and$libresoc.v:123452$4660_Y - attribute \src "libresoc.v:123454.18-123454.110" - wire $and$libresoc.v:123454$4662_Y - attribute \src "libresoc.v:123455.17-123455.112" - wire $and$libresoc.v:123455$4663_Y - attribute \src "libresoc.v:123456.17-123456.114" - wire $and$libresoc.v:123456$4664_Y - attribute \src "libresoc.v:123437.18-123437.127" - wire $eq$libresoc.v:123437$4645_Y - attribute \src "libresoc.v:123438.18-123438.127" - wire $eq$libresoc.v:123438$4646_Y - attribute \src "libresoc.v:123440.18-123440.110" - wire $eq$libresoc.v:123440$4648_Y - attribute \src "libresoc.v:123441.18-123441.110" - wire $eq$libresoc.v:123441$4649_Y - attribute \src "libresoc.v:123443.18-123443.112" - wire $eq$libresoc.v:123443$4651_Y - attribute \src "libresoc.v:123444.17-123444.131" - wire $eq$libresoc.v:123444$4652_Y - attribute \src "libresoc.v:123446.18-123446.110" - wire $eq$libresoc.v:123446$4654_Y - attribute \src "libresoc.v:123448.18-123448.132" - wire $eq$libresoc.v:123448$4656_Y - attribute \src "libresoc.v:123451.18-123451.132" - wire $eq$libresoc.v:123451$4659_Y - attribute \src "libresoc.v:123457.17-123457.131" - wire $eq$libresoc.v:123457$4665_Y - attribute \src "libresoc.v:123435.18-123435.110" - wire $not$libresoc.v:123435$4643_Y - attribute \src "libresoc.v:123453.18-123453.110" - wire $not$libresoc.v:123453$4661_Y - attribute \src "libresoc.v:123439.18-123439.110" - wire $or$libresoc.v:123439$4647_Y - attribute \src "libresoc.v:123442.18-123442.110" - wire $or$libresoc.v:123442$4650_Y - attribute \src "libresoc.v:123445.18-123445.110" - wire $or$libresoc.v:123445$4653_Y - attribute \src "libresoc.v:123447.18-123447.110" - wire $or$libresoc.v:123447$4655_Y + attribute \src "libresoc.v:123510.18-123510.113" + wire $and$libresoc.v:123510$4642_Y + attribute \src "libresoc.v:123512.18-123512.110" + wire $and$libresoc.v:123512$4644_Y + attribute \src "libresoc.v:123525.18-123525.114" + wire $and$libresoc.v:123525$4657_Y + attribute \src "libresoc.v:123526.18-123526.116" + wire $and$libresoc.v:123526$4658_Y + attribute \src "libresoc.v:123528.18-123528.114" + wire $and$libresoc.v:123528$4660_Y + attribute \src "libresoc.v:123530.18-123530.110" + wire $and$libresoc.v:123530$4662_Y + attribute \src "libresoc.v:123531.17-123531.112" + wire $and$libresoc.v:123531$4663_Y + attribute \src "libresoc.v:123532.17-123532.114" + wire $and$libresoc.v:123532$4664_Y + attribute \src "libresoc.v:123513.18-123513.127" + wire $eq$libresoc.v:123513$4645_Y + attribute \src "libresoc.v:123514.18-123514.127" + wire $eq$libresoc.v:123514$4646_Y + attribute \src "libresoc.v:123516.18-123516.110" + wire $eq$libresoc.v:123516$4648_Y + attribute \src "libresoc.v:123517.18-123517.110" + wire $eq$libresoc.v:123517$4649_Y + attribute \src "libresoc.v:123519.18-123519.112" + wire $eq$libresoc.v:123519$4651_Y + attribute \src "libresoc.v:123520.17-123520.131" + wire $eq$libresoc.v:123520$4652_Y + attribute \src "libresoc.v:123522.18-123522.110" + wire $eq$libresoc.v:123522$4654_Y + attribute \src "libresoc.v:123524.18-123524.132" + wire $eq$libresoc.v:123524$4656_Y + attribute \src "libresoc.v:123527.18-123527.132" + wire $eq$libresoc.v:123527$4659_Y + attribute \src "libresoc.v:123533.17-123533.131" + wire $eq$libresoc.v:123533$4665_Y + attribute \src "libresoc.v:123511.18-123511.110" + wire $not$libresoc.v:123511$4643_Y + attribute \src "libresoc.v:123529.18-123529.110" + wire $not$libresoc.v:123529$4661_Y + attribute \src "libresoc.v:123515.18-123515.110" + wire $or$libresoc.v:123515$4647_Y + attribute \src "libresoc.v:123518.18-123518.110" + wire $or$libresoc.v:123518$4650_Y + attribute \src "libresoc.v:123521.18-123521.110" + wire $or$libresoc.v:123521$4653_Y + attribute \src "libresoc.v:123523.18-123523.110" + wire $or$libresoc.v:123523$4655_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" @@ -192385,7 +192448,7 @@ module \dec_LDST attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:123006.7-123006.15" + attribute \src "libresoc.v:123082.7-123082.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" wire width 32 \insn_in @@ -192402,7 +192465,7 @@ module \dec_LDST attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" wire input 2 \sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:123434$4642 + cell $and $and$libresoc.v:123510$4642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192410,10 +192473,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:123434$4642_Y + connect \Y $and$libresoc.v:123510$4642_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:123436$4644 + cell $and $and$libresoc.v:123512$4644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192421,10 +192484,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:123436$4644_Y + connect \Y $and$libresoc.v:123512$4644_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:123449$4657 + cell $and $and$libresoc.v:123525$4657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192432,10 +192495,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:123449$4657_Y + connect \Y $and$libresoc.v:123525$4657_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:123450$4658 + cell $and $and$libresoc.v:123526$4658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192443,10 +192506,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:123450$4658_Y + connect \Y $and$libresoc.v:123526$4658_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:123452$4660 + cell $and $and$libresoc.v:123528$4660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192454,10 +192517,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:123452$4660_Y + connect \Y $and$libresoc.v:123528$4660_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:123454$4662 + cell $and $and$libresoc.v:123530$4662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192465,10 +192528,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:123454$4662_Y + connect \Y $and$libresoc.v:123530$4662_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:123455$4663 + cell $and $and$libresoc.v:123531$4663 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192476,10 +192539,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:123455$4663_Y + connect \Y $and$libresoc.v:123531$4663_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:123456$4664 + cell $and $and$libresoc.v:123532$4664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192487,10 +192550,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:123456$4664_Y + connect \Y $and$libresoc.v:123532$4664_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $eq $eq$libresoc.v:123437$4645 + cell $eq $eq$libresoc.v:123513$4645 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -192498,10 +192561,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \dec_LDST_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:123437$4645_Y + connect \Y $eq$libresoc.v:123513$4645_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $eq $eq$libresoc.v:123438$4646 + cell $eq $eq$libresoc.v:123514$4646 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -192509,10 +192572,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \dec_LDST_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:123438$4646_Y + connect \Y $eq$libresoc.v:123514$4646_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:123440$4648 + cell $eq $eq$libresoc.v:123516$4648 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -192520,10 +192583,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:123440$4648_Y + connect \Y $eq$libresoc.v:123516$4648_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:123441$4649 + cell $eq $eq$libresoc.v:123517$4649 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -192531,10 +192594,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:123441$4649_Y + connect \Y $eq$libresoc.v:123517$4649_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:123443$4651 + cell $eq $eq$libresoc.v:123519$4651 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -192542,10 +192605,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:123443$4651_Y + connect \Y $eq$libresoc.v:123519$4651_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $eq $eq$libresoc.v:123444$4652 + cell $eq $eq$libresoc.v:123520$4652 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -192553,10 +192616,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \dec_LDST_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:123444$4652_Y + connect \Y $eq$libresoc.v:123520$4652_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $eq $eq$libresoc.v:123446$4654 + cell $eq $eq$libresoc.v:123522$4654 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -192564,10 +192627,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:123446$4654_Y + connect \Y $eq$libresoc.v:123522$4654_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $eq $eq$libresoc.v:123448$4656 + cell $eq $eq$libresoc.v:123524$4656 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -192575,10 +192638,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \dec_LDST_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:123448$4656_Y + connect \Y $eq$libresoc.v:123524$4656_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $eq $eq$libresoc.v:123451$4659 + cell $eq $eq$libresoc.v:123527$4659 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -192586,10 +192649,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \dec_LDST_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:123451$4659_Y + connect \Y $eq$libresoc.v:123527$4659_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $eq $eq$libresoc.v:123457$4665 + cell $eq $eq$libresoc.v:123533$4665 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -192597,26 +192660,26 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \dec_LDST_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:123457$4665_Y + connect \Y $eq$libresoc.v:123533$4665_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $not $not$libresoc.v:123435$4643 + cell $not $not$libresoc.v:123511$4643 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:123435$4643_Y + connect \Y $not$libresoc.v:123511$4643_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $not $not$libresoc.v:123453$4661 + cell $not $not$libresoc.v:123529$4661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:123453$4661_Y + connect \Y $not$libresoc.v:123529$4661_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $or $or$libresoc.v:123439$4647 + cell $or $or$libresoc.v:123515$4647 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192624,10 +192687,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:123439$4647_Y + connect \Y $or$libresoc.v:123515$4647_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:123442$4650 + cell $or $or$libresoc.v:123518$4650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192635,10 +192698,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:123442$4650_Y + connect \Y $or$libresoc.v:123518$4650_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:123445$4653 + cell $or $or$libresoc.v:123521$4653 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192646,10 +192709,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:123445$4653_Y + connect \Y $or$libresoc.v:123521$4653_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $or $or$libresoc.v:123447$4655 + cell $or $or$libresoc.v:123523$4655 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -192657,10 +192720,10 @@ module \dec_LDST parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:123447$4655_Y + connect \Y $or$libresoc.v:123523$4655_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:123458.13-123485.4" + attribute \src "libresoc.v:123534.13-123561.4" cell \dec$166 \dec connect \LDST_BD \dec_LDST_BD connect \LDST_DS \dec_LDST_DS @@ -192690,7 +192753,7 @@ module \dec_LDST connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:123486.16-123491.4" + attribute \src "libresoc.v:123562.16-123567.4" cell \dec_ai$169 \dec_ai connect \LDST_RA \dec_LDST_RA connect \immz_out \dec_ai_immz_out @@ -192698,7 +192761,7 @@ module \dec_LDST connect \sv_nz \dec_ai_sv_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:123492.16-123503.4" + attribute \src "libresoc.v:123568.16-123579.4" cell \dec_bi$170 \dec_bi connect \LDST_BD \dec_LDST_BD connect \LDST_DS \dec_LDST_DS @@ -192712,7 +192775,7 @@ module \dec_LDST connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:123504.16-123510.4" + attribute \src "libresoc.v:123580.16-123586.4" cell \dec_oe$168 \dec_oe connect \LDST_OE \dec_LDST_OE connect \LDST_internal_op \dec_LDST_internal_op @@ -192721,29 +192784,29 @@ module \dec_LDST connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:123511.16-123516.4" + attribute \src "libresoc.v:123587.16-123592.4" cell \dec_rc$167 \dec_rc connect \LDST_Rc \dec_LDST_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:123006.7-123006.20" - process $proc$libresoc.v:123006$4668 + attribute \src "libresoc.v:123082.7-123082.20" + process $proc$libresoc.v:123082$4668 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:123517.3-123529.6" - process $proc$libresoc.v:123517$4666 + attribute \src "libresoc.v:123593.3-123605.6" + process $proc$libresoc.v:123593$4666 assign { } { } assign { } { } assign $0\LDST__insn_type[6:0] $1\LDST__insn_type[6:0] - attribute \src "libresoc.v:123518.5-123518.29" + attribute \src "libresoc.v:123594.5-123594.29" switch \initial - attribute \src "libresoc.v:123518.9-123518.17" + attribute \src "libresoc.v:123594.9-123594.17" case 1'1 case end @@ -192763,13 +192826,13 @@ module \dec_LDST sync always update \LDST__insn_type $0\LDST__insn_type[6:0] end - attribute \src "libresoc.v:123530.3-123544.6" - process $proc$libresoc.v:123530$4667 + attribute \src "libresoc.v:123606.3-123620.6" + process $proc$libresoc.v:123606$4667 assign { } { } assign $0\LDST__fn_unit[13:0] $1\LDST__fn_unit[13:0] - attribute \src "libresoc.v:123531.5-123531.29" + attribute \src "libresoc.v:123607.5-123607.29" switch \initial - attribute \src "libresoc.v:123531.9-123531.17" + attribute \src "libresoc.v:123607.9-123607.17" case 1'1 case end @@ -192791,30 +192854,30 @@ module \dec_LDST sync always update \LDST__fn_unit $0\LDST__fn_unit[13:0] end - connect \$10 $and$libresoc.v:123434$4642_Y - connect \$12 $not$libresoc.v:123435$4643_Y - connect \$14 $and$libresoc.v:123436$4644_Y - connect \$16 $eq$libresoc.v:123437$4645_Y - connect \$18 $eq$libresoc.v:123438$4646_Y - connect \$20 $or$libresoc.v:123439$4647_Y - connect \$22 $eq$libresoc.v:123440$4648_Y - connect \$24 $eq$libresoc.v:123441$4649_Y - connect \$26 $or$libresoc.v:123442$4650_Y - connect \$28 $eq$libresoc.v:123443$4651_Y - connect \$2 $eq$libresoc.v:123444$4652_Y - connect \$30 $or$libresoc.v:123445$4653_Y - connect \$32 $eq$libresoc.v:123446$4654_Y - connect \$34 $or$libresoc.v:123447$4655_Y - connect \$36 $eq$libresoc.v:123448$4656_Y - connect \$38 $and$libresoc.v:123449$4657_Y - connect \$40 $and$libresoc.v:123450$4658_Y - connect \$42 $eq$libresoc.v:123451$4659_Y - connect \$44 $and$libresoc.v:123452$4660_Y - connect \$46 $not$libresoc.v:123453$4661_Y - connect \$48 $and$libresoc.v:123454$4662_Y - connect \$4 $and$libresoc.v:123455$4663_Y - connect \$6 $and$libresoc.v:123456$4664_Y - connect \$8 $eq$libresoc.v:123457$4665_Y + connect \$10 $and$libresoc.v:123510$4642_Y + connect \$12 $not$libresoc.v:123511$4643_Y + connect \$14 $and$libresoc.v:123512$4644_Y + connect \$16 $eq$libresoc.v:123513$4645_Y + connect \$18 $eq$libresoc.v:123514$4646_Y + connect \$20 $or$libresoc.v:123515$4647_Y + connect \$22 $eq$libresoc.v:123516$4648_Y + connect \$24 $eq$libresoc.v:123517$4649_Y + connect \$26 $or$libresoc.v:123518$4650_Y + connect \$28 $eq$libresoc.v:123519$4651_Y + connect \$2 $eq$libresoc.v:123520$4652_Y + connect \$30 $or$libresoc.v:123521$4653_Y + connect \$32 $eq$libresoc.v:123522$4654_Y + connect \$34 $or$libresoc.v:123523$4655_Y + connect \$36 $eq$libresoc.v:123524$4656_Y + connect \$38 $and$libresoc.v:123525$4657_Y + connect \$40 $and$libresoc.v:123526$4658_Y + connect \$42 $eq$libresoc.v:123527$4659_Y + connect \$44 $and$libresoc.v:123528$4660_Y + connect \$46 $not$libresoc.v:123529$4661_Y + connect \$48 $and$libresoc.v:123530$4662_Y + connect \$4 $and$libresoc.v:123531$4663_Y + connect \$6 $and$libresoc.v:123532$4664_Y + connect \$8 $eq$libresoc.v:123533$4665_Y connect \LDST__ldst_mode \dec_LDST_upd connect \LDST__sign_extend \dec_LDST_sgn_ext connect \LDST__byte_reverse \dec_LDST_br @@ -192837,73 +192900,73 @@ module \dec_LDST connect \insn_in \dec_opcode_in connect \LDST__insn \dec_opcode_in end -attribute \src "libresoc.v:123570.1-124153.10" +attribute \src "libresoc.v:123646.1-124229.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL" attribute \generator "nMigen" module \dec_LOGICAL - attribute \src "libresoc.v:124116.3-124130.6" + attribute \src "libresoc.v:124192.3-124206.6" wire width 14 $0\LOGICAL__fn_unit[13:0] - attribute \src "libresoc.v:124103.3-124115.6" + attribute \src "libresoc.v:124179.3-124191.6" wire width 7 $0\LOGICAL__insn_type[6:0] - attribute \src "libresoc.v:124088.3-124102.6" + attribute \src "libresoc.v:124164.3-124178.6" wire $0\LOGICAL__write_cr0[0:0] - attribute \src "libresoc.v:123571.7-123571.20" + attribute \src "libresoc.v:123647.7-123647.20" wire $0\initial[0:0] - attribute \src "libresoc.v:124116.3-124130.6" + attribute \src "libresoc.v:124192.3-124206.6" wire width 14 $1\LOGICAL__fn_unit[13:0] - attribute \src "libresoc.v:124103.3-124115.6" + attribute \src "libresoc.v:124179.3-124191.6" wire width 7 $1\LOGICAL__insn_type[6:0] - attribute \src "libresoc.v:124088.3-124102.6" + attribute \src "libresoc.v:124164.3-124178.6" wire $1\LOGICAL__write_cr0[0:0] - attribute \src "libresoc.v:124004.18-124004.113" - wire $and$libresoc.v:124004$4669_Y - attribute \src "libresoc.v:124006.18-124006.110" - wire $and$libresoc.v:124006$4671_Y - attribute \src "libresoc.v:124019.18-124019.114" - wire $and$libresoc.v:124019$4684_Y - attribute \src "libresoc.v:124020.18-124020.116" - wire $and$libresoc.v:124020$4685_Y - attribute \src "libresoc.v:124022.18-124022.114" - wire $and$libresoc.v:124022$4687_Y - attribute \src "libresoc.v:124024.18-124024.110" - wire $and$libresoc.v:124024$4689_Y - attribute \src "libresoc.v:124025.17-124025.112" - wire $and$libresoc.v:124025$4690_Y - attribute \src "libresoc.v:124026.17-124026.114" - wire $and$libresoc.v:124026$4691_Y - attribute \src "libresoc.v:124007.18-124007.130" - wire $eq$libresoc.v:124007$4672_Y - attribute \src "libresoc.v:124008.18-124008.130" - wire $eq$libresoc.v:124008$4673_Y - attribute \src "libresoc.v:124010.18-124010.110" - wire $eq$libresoc.v:124010$4675_Y - attribute \src "libresoc.v:124011.18-124011.110" - wire $eq$libresoc.v:124011$4676_Y - attribute \src "libresoc.v:124013.18-124013.112" - wire $eq$libresoc.v:124013$4678_Y - attribute \src "libresoc.v:124014.17-124014.134" - wire $eq$libresoc.v:124014$4679_Y - attribute \src "libresoc.v:124016.18-124016.110" - wire $eq$libresoc.v:124016$4681_Y - attribute \src "libresoc.v:124018.18-124018.135" - wire $eq$libresoc.v:124018$4683_Y - attribute \src "libresoc.v:124021.18-124021.135" - wire $eq$libresoc.v:124021$4686_Y - attribute \src "libresoc.v:124027.17-124027.134" - wire $eq$libresoc.v:124027$4692_Y - attribute \src "libresoc.v:124005.18-124005.110" - wire $not$libresoc.v:124005$4670_Y - attribute \src "libresoc.v:124023.18-124023.110" - wire $not$libresoc.v:124023$4688_Y - attribute \src "libresoc.v:124009.18-124009.110" - wire $or$libresoc.v:124009$4674_Y - attribute \src "libresoc.v:124012.18-124012.110" - wire $or$libresoc.v:124012$4677_Y - attribute \src "libresoc.v:124015.18-124015.110" - wire $or$libresoc.v:124015$4680_Y - attribute \src "libresoc.v:124017.18-124017.110" - wire $or$libresoc.v:124017$4682_Y + attribute \src "libresoc.v:124080.18-124080.113" + wire $and$libresoc.v:124080$4669_Y + attribute \src "libresoc.v:124082.18-124082.110" + wire $and$libresoc.v:124082$4671_Y + attribute \src "libresoc.v:124095.18-124095.114" + wire $and$libresoc.v:124095$4684_Y + attribute \src "libresoc.v:124096.18-124096.116" + wire $and$libresoc.v:124096$4685_Y + attribute \src "libresoc.v:124098.18-124098.114" + wire $and$libresoc.v:124098$4687_Y + attribute \src "libresoc.v:124100.18-124100.110" + wire $and$libresoc.v:124100$4689_Y + attribute \src "libresoc.v:124101.17-124101.112" + wire $and$libresoc.v:124101$4690_Y + attribute \src "libresoc.v:124102.17-124102.114" + wire $and$libresoc.v:124102$4691_Y + attribute \src "libresoc.v:124083.18-124083.130" + wire $eq$libresoc.v:124083$4672_Y + attribute \src "libresoc.v:124084.18-124084.130" + wire $eq$libresoc.v:124084$4673_Y + attribute \src "libresoc.v:124086.18-124086.110" + wire $eq$libresoc.v:124086$4675_Y + attribute \src "libresoc.v:124087.18-124087.110" + wire $eq$libresoc.v:124087$4676_Y + attribute \src "libresoc.v:124089.18-124089.112" + wire $eq$libresoc.v:124089$4678_Y + attribute \src "libresoc.v:124090.17-124090.134" + wire $eq$libresoc.v:124090$4679_Y + attribute \src "libresoc.v:124092.18-124092.110" + wire $eq$libresoc.v:124092$4681_Y + attribute \src "libresoc.v:124094.18-124094.135" + wire $eq$libresoc.v:124094$4683_Y + attribute \src "libresoc.v:124097.18-124097.135" + wire $eq$libresoc.v:124097$4686_Y + attribute \src "libresoc.v:124103.17-124103.134" + wire $eq$libresoc.v:124103$4692_Y + attribute \src "libresoc.v:124081.18-124081.110" + wire $not$libresoc.v:124081$4670_Y + attribute \src "libresoc.v:124099.18-124099.110" + wire $not$libresoc.v:124099$4688_Y + attribute \src "libresoc.v:124085.18-124085.110" + wire $or$libresoc.v:124085$4674_Y + attribute \src "libresoc.v:124088.18-124088.110" + wire $or$libresoc.v:124088$4677_Y + attribute \src "libresoc.v:124091.18-124091.110" + wire $or$libresoc.v:124091$4680_Y + attribute \src "libresoc.v:124093.18-124093.110" + wire $or$libresoc.v:124093$4682_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" @@ -193319,7 +193382,7 @@ module \dec_LOGICAL attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:123571.7-123571.15" + attribute \src "libresoc.v:123647.7-123647.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" wire width 32 \insn_in @@ -193336,7 +193399,7 @@ module \dec_LOGICAL attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692" wire input 2 \sv_a_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:124004$4669 + cell $and $and$libresoc.v:124080$4669 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193344,10 +193407,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:124004$4669_Y + connect \Y $and$libresoc.v:124080$4669_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:124006$4671 + cell $and $and$libresoc.v:124082$4671 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193355,10 +193418,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:124006$4671_Y + connect \Y $and$libresoc.v:124082$4671_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:124019$4684 + cell $and $and$libresoc.v:124095$4684 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193366,10 +193429,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:124019$4684_Y + connect \Y $and$libresoc.v:124095$4684_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:124020$4685 + cell $and $and$libresoc.v:124096$4685 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193377,10 +193440,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:124020$4685_Y + connect \Y $and$libresoc.v:124096$4685_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:124022$4687 + cell $and $and$libresoc.v:124098$4687 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193388,10 +193451,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:124022$4687_Y + connect \Y $and$libresoc.v:124098$4687_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:124024$4689 + cell $and $and$libresoc.v:124100$4689 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193399,10 +193462,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:124024$4689_Y + connect \Y $and$libresoc.v:124100$4689_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:124025$4690 + cell $and $and$libresoc.v:124101$4690 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193410,10 +193473,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:124025$4690_Y + connect \Y $and$libresoc.v:124101$4690_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:124026$4691 + cell $and $and$libresoc.v:124102$4691 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193421,10 +193484,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:124026$4691_Y + connect \Y $and$libresoc.v:124102$4691_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $eq $eq$libresoc.v:124007$4672 + cell $eq $eq$libresoc.v:124083$4672 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -193432,10 +193495,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:124007$4672_Y + connect \Y $eq$libresoc.v:124083$4672_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $eq $eq$libresoc.v:124008$4673 + cell $eq $eq$libresoc.v:124084$4673 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -193443,10 +193506,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:124008$4673_Y + connect \Y $eq$libresoc.v:124084$4673_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:124010$4675 + cell $eq $eq$libresoc.v:124086$4675 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -193454,10 +193517,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:124010$4675_Y + connect \Y $eq$libresoc.v:124086$4675_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:124011$4676 + cell $eq $eq$libresoc.v:124087$4676 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -193465,10 +193528,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:124011$4676_Y + connect \Y $eq$libresoc.v:124087$4676_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:124013$4678 + cell $eq $eq$libresoc.v:124089$4678 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -193476,10 +193539,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:124013$4678_Y + connect \Y $eq$libresoc.v:124089$4678_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $eq $eq$libresoc.v:124014$4679 + cell $eq $eq$libresoc.v:124090$4679 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -193487,10 +193550,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:124014$4679_Y + connect \Y $eq$libresoc.v:124090$4679_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $eq $eq$libresoc.v:124016$4681 + cell $eq $eq$libresoc.v:124092$4681 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -193498,10 +193561,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:124016$4681_Y + connect \Y $eq$libresoc.v:124092$4681_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $eq $eq$libresoc.v:124018$4683 + cell $eq $eq$libresoc.v:124094$4683 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -193509,10 +193572,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:124018$4683_Y + connect \Y $eq$libresoc.v:124094$4683_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $eq $eq$libresoc.v:124021$4686 + cell $eq $eq$libresoc.v:124097$4686 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -193520,10 +193583,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:124021$4686_Y + connect \Y $eq$libresoc.v:124097$4686_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $eq $eq$libresoc.v:124027$4692 + cell $eq $eq$libresoc.v:124103$4692 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -193531,26 +193594,26 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \dec_LOGICAL_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:124027$4692_Y + connect \Y $eq$libresoc.v:124103$4692_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $not $not$libresoc.v:124005$4670 + cell $not $not$libresoc.v:124081$4670 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:124005$4670_Y + connect \Y $not$libresoc.v:124081$4670_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $not $not$libresoc.v:124023$4688 + cell $not $not$libresoc.v:124099$4688 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:124023$4688_Y + connect \Y $not$libresoc.v:124099$4688_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $or $or$libresoc.v:124009$4674 + cell $or $or$libresoc.v:124085$4674 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193558,10 +193621,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:124009$4674_Y + connect \Y $or$libresoc.v:124085$4674_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:124012$4677 + cell $or $or$libresoc.v:124088$4677 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193569,10 +193632,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:124012$4677_Y + connect \Y $or$libresoc.v:124088$4677_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:124015$4680 + cell $or $or$libresoc.v:124091$4680 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193580,10 +193643,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:124015$4680_Y + connect \Y $or$libresoc.v:124091$4680_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $or $or$libresoc.v:124017$4682 + cell $or $or$libresoc.v:124093$4682 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -193591,10 +193654,10 @@ module \dec_LOGICAL parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:124017$4682_Y + connect \Y $or$libresoc.v:124093$4682_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:124028.13-124056.4" + attribute \src "libresoc.v:124104.13-124132.4" cell \dec$145 \dec connect \LOGICAL_BD \dec_LOGICAL_BD connect \LOGICAL_DS \dec_LOGICAL_DS @@ -193625,7 +193688,7 @@ module \dec_LOGICAL connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:124057.16-124062.4" + attribute \src "libresoc.v:124133.16-124138.4" cell \dec_ai$148 \dec_ai connect \LOGICAL_RA \dec_LOGICAL_RA connect \immz_out \dec_ai_immz_out @@ -193633,7 +193696,7 @@ module \dec_LOGICAL connect \sv_nz \dec_ai_sv_nz end attribute \module_not_derived 1 - attribute \src "libresoc.v:124063.16-124074.4" + attribute \src "libresoc.v:124139.16-124150.4" cell \dec_bi$149 \dec_bi connect \LOGICAL_BD \dec_LOGICAL_BD connect \LOGICAL_DS \dec_LOGICAL_DS @@ -193647,7 +193710,7 @@ module \dec_LOGICAL connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:124075.16-124081.4" + attribute \src "libresoc.v:124151.16-124157.4" cell \dec_oe$147 \dec_oe connect \LOGICAL_OE \dec_LOGICAL_OE connect \LOGICAL_internal_op \dec_LOGICAL_internal_op @@ -193656,29 +193719,29 @@ module \dec_LOGICAL connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:124082.16-124087.4" + attribute \src "libresoc.v:124158.16-124163.4" cell \dec_rc$146 \dec_rc connect \LOGICAL_Rc \dec_LOGICAL_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:123571.7-123571.20" - process $proc$libresoc.v:123571$4696 + attribute \src "libresoc.v:123647.7-123647.20" + process $proc$libresoc.v:123647$4696 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:124088.3-124102.6" - process $proc$libresoc.v:124088$4693 + attribute \src "libresoc.v:124164.3-124178.6" + process $proc$libresoc.v:124164$4693 assign { } { } assign { } { } assign $0\LOGICAL__write_cr0[0:0] $1\LOGICAL__write_cr0[0:0] - attribute \src "libresoc.v:124089.5-124089.29" + attribute \src "libresoc.v:124165.5-124165.29" switch \initial - attribute \src "libresoc.v:124089.9-124089.17" + attribute \src "libresoc.v:124165.9-124165.17" case 1'1 case end @@ -193698,14 +193761,14 @@ module \dec_LOGICAL sync always update \LOGICAL__write_cr0 $0\LOGICAL__write_cr0[0:0] end - attribute \src "libresoc.v:124103.3-124115.6" - process $proc$libresoc.v:124103$4694 + attribute \src "libresoc.v:124179.3-124191.6" + process $proc$libresoc.v:124179$4694 assign { } { } assign { } { } assign $0\LOGICAL__insn_type[6:0] $1\LOGICAL__insn_type[6:0] - attribute \src "libresoc.v:124104.5-124104.29" + attribute \src "libresoc.v:124180.5-124180.29" switch \initial - attribute \src "libresoc.v:124104.9-124104.17" + attribute \src "libresoc.v:124180.9-124180.17" case 1'1 case end @@ -193725,13 +193788,13 @@ module \dec_LOGICAL sync always update \LOGICAL__insn_type $0\LOGICAL__insn_type[6:0] end - attribute \src "libresoc.v:124116.3-124130.6" - process $proc$libresoc.v:124116$4695 + attribute \src "libresoc.v:124192.3-124206.6" + process $proc$libresoc.v:124192$4695 assign { } { } assign $0\LOGICAL__fn_unit[13:0] $1\LOGICAL__fn_unit[13:0] - attribute \src "libresoc.v:124117.5-124117.29" + attribute \src "libresoc.v:124193.5-124193.29" switch \initial - attribute \src "libresoc.v:124117.9-124117.17" + attribute \src "libresoc.v:124193.9-124193.17" case 1'1 case end @@ -193753,30 +193816,30 @@ module \dec_LOGICAL sync always update \LOGICAL__fn_unit $0\LOGICAL__fn_unit[13:0] end - connect \$10 $and$libresoc.v:124004$4669_Y - connect \$12 $not$libresoc.v:124005$4670_Y - connect \$14 $and$libresoc.v:124006$4671_Y - connect \$16 $eq$libresoc.v:124007$4672_Y - connect \$18 $eq$libresoc.v:124008$4673_Y - connect \$20 $or$libresoc.v:124009$4674_Y - connect \$22 $eq$libresoc.v:124010$4675_Y - connect \$24 $eq$libresoc.v:124011$4676_Y - connect \$26 $or$libresoc.v:124012$4677_Y - connect \$28 $eq$libresoc.v:124013$4678_Y - connect \$2 $eq$libresoc.v:124014$4679_Y - connect \$30 $or$libresoc.v:124015$4680_Y - connect \$32 $eq$libresoc.v:124016$4681_Y - connect \$34 $or$libresoc.v:124017$4682_Y - connect \$36 $eq$libresoc.v:124018$4683_Y - connect \$38 $and$libresoc.v:124019$4684_Y - connect \$40 $and$libresoc.v:124020$4685_Y - connect \$42 $eq$libresoc.v:124021$4686_Y - connect \$44 $and$libresoc.v:124022$4687_Y - connect \$46 $not$libresoc.v:124023$4688_Y - connect \$48 $and$libresoc.v:124024$4689_Y - connect \$4 $and$libresoc.v:124025$4690_Y - connect \$6 $and$libresoc.v:124026$4691_Y - connect \$8 $eq$libresoc.v:124027$4692_Y + connect \$10 $and$libresoc.v:124080$4669_Y + connect \$12 $not$libresoc.v:124081$4670_Y + connect \$14 $and$libresoc.v:124082$4671_Y + connect \$16 $eq$libresoc.v:124083$4672_Y + connect \$18 $eq$libresoc.v:124084$4673_Y + connect \$20 $or$libresoc.v:124085$4674_Y + connect \$22 $eq$libresoc.v:124086$4675_Y + connect \$24 $eq$libresoc.v:124087$4676_Y + connect \$26 $or$libresoc.v:124088$4677_Y + connect \$28 $eq$libresoc.v:124089$4678_Y + connect \$2 $eq$libresoc.v:124090$4679_Y + connect \$30 $or$libresoc.v:124091$4680_Y + connect \$32 $eq$libresoc.v:124092$4681_Y + connect \$34 $or$libresoc.v:124093$4682_Y + connect \$36 $eq$libresoc.v:124094$4683_Y + connect \$38 $and$libresoc.v:124095$4684_Y + connect \$40 $and$libresoc.v:124096$4685_Y + connect \$42 $eq$libresoc.v:124097$4686_Y + connect \$44 $and$libresoc.v:124098$4687_Y + connect \$46 $not$libresoc.v:124099$4688_Y + connect \$48 $and$libresoc.v:124100$4689_Y + connect \$4 $and$libresoc.v:124101$4690_Y + connect \$6 $and$libresoc.v:124102$4691_Y + connect \$8 $eq$libresoc.v:124103$4692_Y connect \LOGICAL__is_signed \dec_LOGICAL_sgn connect \LOGICAL__is_32bit \dec_LOGICAL_is_32b connect \LOGICAL__output_carry \dec_LOGICAL_cry_out @@ -193800,73 +193863,73 @@ module \dec_LOGICAL connect \insn_in \dec_opcode_in connect \LOGICAL__insn \dec_opcode_in end -attribute \src "libresoc.v:124157.1-124659.10" +attribute \src "libresoc.v:124233.1-124735.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL" attribute \generator "nMigen" module \dec_MUL - attribute \src "libresoc.v:124630.3-124644.6" + attribute \src "libresoc.v:124706.3-124720.6" wire width 14 $0\MUL__fn_unit[13:0] - attribute \src "libresoc.v:124617.3-124629.6" + attribute \src "libresoc.v:124693.3-124705.6" wire width 7 $0\MUL__insn_type[6:0] - attribute \src "libresoc.v:124602.3-124616.6" + attribute \src "libresoc.v:124678.3-124692.6" wire $0\MUL__write_cr0[0:0] - attribute \src "libresoc.v:124158.7-124158.20" + attribute \src "libresoc.v:124234.7-124234.20" wire $0\initial[0:0] - attribute \src "libresoc.v:124630.3-124644.6" + attribute \src "libresoc.v:124706.3-124720.6" wire width 14 $1\MUL__fn_unit[13:0] - attribute \src "libresoc.v:124617.3-124629.6" + attribute \src "libresoc.v:124693.3-124705.6" wire width 7 $1\MUL__insn_type[6:0] - attribute \src "libresoc.v:124602.3-124616.6" + attribute \src "libresoc.v:124678.3-124692.6" wire $1\MUL__write_cr0[0:0] - attribute \src "libresoc.v:124531.18-124531.113" - wire $and$libresoc.v:124531$4697_Y - attribute \src "libresoc.v:124533.18-124533.110" - wire $and$libresoc.v:124533$4699_Y - attribute \src "libresoc.v:124546.18-124546.114" - wire $and$libresoc.v:124546$4712_Y - attribute \src "libresoc.v:124547.18-124547.116" - wire $and$libresoc.v:124547$4713_Y - attribute \src "libresoc.v:124549.18-124549.114" - wire $and$libresoc.v:124549$4715_Y - attribute \src "libresoc.v:124551.18-124551.110" - wire $and$libresoc.v:124551$4717_Y - attribute \src "libresoc.v:124552.17-124552.112" - wire $and$libresoc.v:124552$4718_Y - attribute \src "libresoc.v:124553.17-124553.114" - wire $and$libresoc.v:124553$4719_Y - attribute \src "libresoc.v:124534.18-124534.126" - wire $eq$libresoc.v:124534$4700_Y - attribute \src "libresoc.v:124535.18-124535.126" - wire $eq$libresoc.v:124535$4701_Y - attribute \src "libresoc.v:124537.18-124537.110" - wire $eq$libresoc.v:124537$4703_Y - attribute \src "libresoc.v:124538.18-124538.110" - wire $eq$libresoc.v:124538$4704_Y - attribute \src "libresoc.v:124540.18-124540.112" - wire $eq$libresoc.v:124540$4706_Y - attribute \src "libresoc.v:124541.17-124541.130" - wire $eq$libresoc.v:124541$4707_Y - attribute \src "libresoc.v:124543.18-124543.110" - wire $eq$libresoc.v:124543$4709_Y - attribute \src "libresoc.v:124545.18-124545.131" - wire $eq$libresoc.v:124545$4711_Y - attribute \src "libresoc.v:124548.18-124548.131" - wire $eq$libresoc.v:124548$4714_Y - attribute \src "libresoc.v:124554.17-124554.130" - wire $eq$libresoc.v:124554$4720_Y - attribute \src "libresoc.v:124532.18-124532.110" - wire $not$libresoc.v:124532$4698_Y - attribute \src "libresoc.v:124550.18-124550.110" - wire $not$libresoc.v:124550$4716_Y - attribute \src "libresoc.v:124536.18-124536.110" - wire $or$libresoc.v:124536$4702_Y - attribute \src "libresoc.v:124539.18-124539.110" - wire $or$libresoc.v:124539$4705_Y - attribute \src "libresoc.v:124542.18-124542.110" - wire $or$libresoc.v:124542$4708_Y - attribute \src "libresoc.v:124544.18-124544.110" - wire $or$libresoc.v:124544$4710_Y + attribute \src "libresoc.v:124607.18-124607.113" + wire $and$libresoc.v:124607$4697_Y + attribute \src "libresoc.v:124609.18-124609.110" + wire $and$libresoc.v:124609$4699_Y + attribute \src "libresoc.v:124622.18-124622.114" + wire $and$libresoc.v:124622$4712_Y + attribute \src "libresoc.v:124623.18-124623.116" + wire $and$libresoc.v:124623$4713_Y + attribute \src "libresoc.v:124625.18-124625.114" + wire $and$libresoc.v:124625$4715_Y + attribute \src "libresoc.v:124627.18-124627.110" + wire $and$libresoc.v:124627$4717_Y + attribute \src "libresoc.v:124628.17-124628.112" + wire $and$libresoc.v:124628$4718_Y + attribute \src "libresoc.v:124629.17-124629.114" + wire $and$libresoc.v:124629$4719_Y + attribute \src "libresoc.v:124610.18-124610.126" + wire $eq$libresoc.v:124610$4700_Y + attribute \src "libresoc.v:124611.18-124611.126" + wire $eq$libresoc.v:124611$4701_Y + attribute \src "libresoc.v:124613.18-124613.110" + wire $eq$libresoc.v:124613$4703_Y + attribute \src "libresoc.v:124614.18-124614.110" + wire $eq$libresoc.v:124614$4704_Y + attribute \src "libresoc.v:124616.18-124616.112" + wire $eq$libresoc.v:124616$4706_Y + attribute \src "libresoc.v:124617.17-124617.130" + wire $eq$libresoc.v:124617$4707_Y + attribute \src "libresoc.v:124619.18-124619.110" + wire $eq$libresoc.v:124619$4709_Y + attribute \src "libresoc.v:124621.18-124621.131" + wire $eq$libresoc.v:124621$4711_Y + attribute \src "libresoc.v:124624.18-124624.131" + wire $eq$libresoc.v:124624$4714_Y + attribute \src "libresoc.v:124630.17-124630.130" + wire $eq$libresoc.v:124630$4720_Y + attribute \src "libresoc.v:124608.18-124608.110" + wire $not$libresoc.v:124608$4698_Y + attribute \src "libresoc.v:124626.18-124626.110" + wire $not$libresoc.v:124626$4716_Y + attribute \src "libresoc.v:124612.18-124612.110" + wire $or$libresoc.v:124612$4702_Y + attribute \src "libresoc.v:124615.18-124615.110" + wire $or$libresoc.v:124615$4705_Y + attribute \src "libresoc.v:124618.18-124618.110" + wire $or$libresoc.v:124618$4708_Y + attribute \src "libresoc.v:124620.18-124620.110" + wire $or$libresoc.v:124620$4710_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" @@ -194224,7 +194287,7 @@ module \dec_MUL attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:124158.7-124158.15" + attribute \src "libresoc.v:124234.7-124234.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" wire width 32 \insn_in @@ -194239,7 +194302,7 @@ module \dec_MUL attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" wire width 10 \spr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:124531$4697 + cell $and $and$libresoc.v:124607$4697 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194247,10 +194310,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:124531$4697_Y + connect \Y $and$libresoc.v:124607$4697_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:124533$4699 + cell $and $and$libresoc.v:124609$4699 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194258,10 +194321,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:124533$4699_Y + connect \Y $and$libresoc.v:124609$4699_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:124546$4712 + cell $and $and$libresoc.v:124622$4712 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194269,10 +194332,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:124546$4712_Y + connect \Y $and$libresoc.v:124622$4712_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:124547$4713 + cell $and $and$libresoc.v:124623$4713 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194280,10 +194343,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:124547$4713_Y + connect \Y $and$libresoc.v:124623$4713_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:124549$4715 + cell $and $and$libresoc.v:124625$4715 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194291,10 +194354,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:124549$4715_Y + connect \Y $and$libresoc.v:124625$4715_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:124551$4717 + cell $and $and$libresoc.v:124627$4717 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194302,10 +194365,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:124551$4717_Y + connect \Y $and$libresoc.v:124627$4717_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:124552$4718 + cell $and $and$libresoc.v:124628$4718 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194313,10 +194376,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:124552$4718_Y + connect \Y $and$libresoc.v:124628$4718_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:124553$4719 + cell $and $and$libresoc.v:124629$4719 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194324,10 +194387,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:124553$4719_Y + connect \Y $and$libresoc.v:124629$4719_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $eq $eq$libresoc.v:124534$4700 + cell $eq $eq$libresoc.v:124610$4700 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -194335,10 +194398,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \dec_MUL_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:124534$4700_Y + connect \Y $eq$libresoc.v:124610$4700_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $eq $eq$libresoc.v:124535$4701 + cell $eq $eq$libresoc.v:124611$4701 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -194346,10 +194409,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \dec_MUL_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:124535$4701_Y + connect \Y $eq$libresoc.v:124611$4701_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:124537$4703 + cell $eq $eq$libresoc.v:124613$4703 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -194357,10 +194420,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:124537$4703_Y + connect \Y $eq$libresoc.v:124613$4703_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:124538$4704 + cell $eq $eq$libresoc.v:124614$4704 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -194368,10 +194431,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:124538$4704_Y + connect \Y $eq$libresoc.v:124614$4704_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:124540$4706 + cell $eq $eq$libresoc.v:124616$4706 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -194379,10 +194442,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:124540$4706_Y + connect \Y $eq$libresoc.v:124616$4706_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $eq $eq$libresoc.v:124541$4707 + cell $eq $eq$libresoc.v:124617$4707 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -194390,10 +194453,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \dec_MUL_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:124541$4707_Y + connect \Y $eq$libresoc.v:124617$4707_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $eq $eq$libresoc.v:124543$4709 + cell $eq $eq$libresoc.v:124619$4709 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -194401,10 +194464,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:124543$4709_Y + connect \Y $eq$libresoc.v:124619$4709_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $eq $eq$libresoc.v:124545$4711 + cell $eq $eq$libresoc.v:124621$4711 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -194412,10 +194475,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \dec_MUL_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:124545$4711_Y + connect \Y $eq$libresoc.v:124621$4711_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $eq $eq$libresoc.v:124548$4714 + cell $eq $eq$libresoc.v:124624$4714 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -194423,10 +194486,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \dec_MUL_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:124548$4714_Y + connect \Y $eq$libresoc.v:124624$4714_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $eq $eq$libresoc.v:124554$4720 + cell $eq $eq$libresoc.v:124630$4720 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -194434,26 +194497,26 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \dec_MUL_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:124554$4720_Y + connect \Y $eq$libresoc.v:124630$4720_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $not $not$libresoc.v:124532$4698 + cell $not $not$libresoc.v:124608$4698 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:124532$4698_Y + connect \Y $not$libresoc.v:124608$4698_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $not $not$libresoc.v:124550$4716 + cell $not $not$libresoc.v:124626$4716 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:124550$4716_Y + connect \Y $not$libresoc.v:124626$4716_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $or $or$libresoc.v:124536$4702 + cell $or $or$libresoc.v:124612$4702 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194461,10 +194524,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:124536$4702_Y + connect \Y $or$libresoc.v:124612$4702_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:124539$4705 + cell $or $or$libresoc.v:124615$4705 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194472,10 +194535,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:124539$4705_Y + connect \Y $or$libresoc.v:124615$4705_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:124542$4708 + cell $or $or$libresoc.v:124618$4708 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194483,10 +194546,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:124542$4708_Y + connect \Y $or$libresoc.v:124618$4708_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $or $or$libresoc.v:124544$4710 + cell $or $or$libresoc.v:124620$4710 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -194494,10 +194557,10 @@ module \dec_MUL parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:124544$4710_Y + connect \Y $or$libresoc.v:124620$4710_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:124555.13-124576.4" + attribute \src "libresoc.v:124631.13-124652.4" cell \dec$158 \dec connect \MUL_BD \dec_MUL_BD connect \MUL_DS \dec_MUL_DS @@ -194521,7 +194584,7 @@ module \dec_MUL connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:124577.16-124588.4" + attribute \src "libresoc.v:124653.16-124664.4" cell \dec_bi$161 \dec_bi connect \MUL_BD \dec_MUL_BD connect \MUL_DS \dec_MUL_DS @@ -194535,7 +194598,7 @@ module \dec_MUL connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:124589.16-124595.4" + attribute \src "libresoc.v:124665.16-124671.4" cell \dec_oe$160 \dec_oe connect \MUL_OE \dec_MUL_OE connect \MUL_internal_op \dec_MUL_internal_op @@ -194544,29 +194607,29 @@ module \dec_MUL connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:124596.16-124601.4" + attribute \src "libresoc.v:124672.16-124677.4" cell \dec_rc$159 \dec_rc connect \MUL_Rc \dec_MUL_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:124158.7-124158.20" - process $proc$libresoc.v:124158$4724 + attribute \src "libresoc.v:124234.7-124234.20" + process $proc$libresoc.v:124234$4724 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:124602.3-124616.6" - process $proc$libresoc.v:124602$4721 + attribute \src "libresoc.v:124678.3-124692.6" + process $proc$libresoc.v:124678$4721 assign { } { } assign { } { } assign $0\MUL__write_cr0[0:0] $1\MUL__write_cr0[0:0] - attribute \src "libresoc.v:124603.5-124603.29" + attribute \src "libresoc.v:124679.5-124679.29" switch \initial - attribute \src "libresoc.v:124603.9-124603.17" + attribute \src "libresoc.v:124679.9-124679.17" case 1'1 case end @@ -194586,14 +194649,14 @@ module \dec_MUL sync always update \MUL__write_cr0 $0\MUL__write_cr0[0:0] end - attribute \src "libresoc.v:124617.3-124629.6" - process $proc$libresoc.v:124617$4722 + attribute \src "libresoc.v:124693.3-124705.6" + process $proc$libresoc.v:124693$4722 assign { } { } assign { } { } assign $0\MUL__insn_type[6:0] $1\MUL__insn_type[6:0] - attribute \src "libresoc.v:124618.5-124618.29" + attribute \src "libresoc.v:124694.5-124694.29" switch \initial - attribute \src "libresoc.v:124618.9-124618.17" + attribute \src "libresoc.v:124694.9-124694.17" case 1'1 case end @@ -194613,13 +194676,13 @@ module \dec_MUL sync always update \MUL__insn_type $0\MUL__insn_type[6:0] end - attribute \src "libresoc.v:124630.3-124644.6" - process $proc$libresoc.v:124630$4723 + attribute \src "libresoc.v:124706.3-124720.6" + process $proc$libresoc.v:124706$4723 assign { } { } assign $0\MUL__fn_unit[13:0] $1\MUL__fn_unit[13:0] - attribute \src "libresoc.v:124631.5-124631.29" + attribute \src "libresoc.v:124707.5-124707.29" switch \initial - attribute \src "libresoc.v:124631.9-124631.17" + attribute \src "libresoc.v:124707.9-124707.17" case 1'1 case end @@ -194641,30 +194704,30 @@ module \dec_MUL sync always update \MUL__fn_unit $0\MUL__fn_unit[13:0] end - connect \$10 $and$libresoc.v:124531$4697_Y - connect \$12 $not$libresoc.v:124532$4698_Y - connect \$14 $and$libresoc.v:124533$4699_Y - connect \$16 $eq$libresoc.v:124534$4700_Y - connect \$18 $eq$libresoc.v:124535$4701_Y - connect \$20 $or$libresoc.v:124536$4702_Y - connect \$22 $eq$libresoc.v:124537$4703_Y - connect \$24 $eq$libresoc.v:124538$4704_Y - connect \$26 $or$libresoc.v:124539$4705_Y - connect \$28 $eq$libresoc.v:124540$4706_Y - connect \$2 $eq$libresoc.v:124541$4707_Y - connect \$30 $or$libresoc.v:124542$4708_Y - connect \$32 $eq$libresoc.v:124543$4709_Y - connect \$34 $or$libresoc.v:124544$4710_Y - connect \$36 $eq$libresoc.v:124545$4711_Y - connect \$38 $and$libresoc.v:124546$4712_Y - connect \$40 $and$libresoc.v:124547$4713_Y - connect \$42 $eq$libresoc.v:124548$4714_Y - connect \$44 $and$libresoc.v:124549$4715_Y - connect \$46 $not$libresoc.v:124550$4716_Y - connect \$48 $and$libresoc.v:124551$4717_Y - connect \$4 $and$libresoc.v:124552$4718_Y - connect \$6 $and$libresoc.v:124553$4719_Y - connect \$8 $eq$libresoc.v:124554$4720_Y + connect \$10 $and$libresoc.v:124607$4697_Y + connect \$12 $not$libresoc.v:124608$4698_Y + connect \$14 $and$libresoc.v:124609$4699_Y + connect \$16 $eq$libresoc.v:124610$4700_Y + connect \$18 $eq$libresoc.v:124611$4701_Y + connect \$20 $or$libresoc.v:124612$4702_Y + connect \$22 $eq$libresoc.v:124613$4703_Y + connect \$24 $eq$libresoc.v:124614$4704_Y + connect \$26 $or$libresoc.v:124615$4705_Y + connect \$28 $eq$libresoc.v:124616$4706_Y + connect \$2 $eq$libresoc.v:124617$4707_Y + connect \$30 $or$libresoc.v:124618$4708_Y + connect \$32 $eq$libresoc.v:124619$4709_Y + connect \$34 $or$libresoc.v:124620$4710_Y + connect \$36 $eq$libresoc.v:124621$4711_Y + connect \$38 $and$libresoc.v:124622$4712_Y + connect \$40 $and$libresoc.v:124623$4713_Y + connect \$42 $eq$libresoc.v:124624$4714_Y + connect \$44 $and$libresoc.v:124625$4715_Y + connect \$46 $not$libresoc.v:124626$4716_Y + connect \$48 $and$libresoc.v:124627$4717_Y + connect \$4 $and$libresoc.v:124628$4718_Y + connect \$6 $and$libresoc.v:124629$4719_Y + connect \$8 $eq$libresoc.v:124630$4720_Y connect \MUL__is_signed \dec_MUL_sgn connect \MUL__is_32bit \dec_MUL_is_32b connect { \MUL__oe__ok \MUL__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } @@ -194680,73 +194743,73 @@ module \dec_MUL connect \insn_in \dec_opcode_in connect \MUL__insn \dec_opcode_in end -attribute \src "libresoc.v:124663.1-125209.10" +attribute \src "libresoc.v:124739.1-125285.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT" attribute \generator "nMigen" module \dec_SHIFT_ROT - attribute \src "libresoc.v:125175.3-125189.6" + attribute \src "libresoc.v:125251.3-125265.6" wire width 14 $0\SHIFT_ROT__fn_unit[13:0] - attribute \src "libresoc.v:125162.3-125174.6" + attribute \src "libresoc.v:125238.3-125250.6" wire width 7 $0\SHIFT_ROT__insn_type[6:0] - attribute \src "libresoc.v:125147.3-125161.6" + attribute \src "libresoc.v:125223.3-125237.6" wire $0\SHIFT_ROT__write_cr0[0:0] - attribute \src "libresoc.v:124664.7-124664.20" + attribute \src "libresoc.v:124740.7-124740.20" wire $0\initial[0:0] - attribute \src "libresoc.v:125175.3-125189.6" + attribute \src "libresoc.v:125251.3-125265.6" wire width 14 $1\SHIFT_ROT__fn_unit[13:0] - attribute \src "libresoc.v:125162.3-125174.6" + attribute \src "libresoc.v:125238.3-125250.6" wire width 7 $1\SHIFT_ROT__insn_type[6:0] - attribute \src "libresoc.v:125147.3-125161.6" + attribute \src "libresoc.v:125223.3-125237.6" wire $1\SHIFT_ROT__write_cr0[0:0] - attribute \src "libresoc.v:125072.18-125072.113" - wire $and$libresoc.v:125072$4725_Y - attribute \src "libresoc.v:125074.18-125074.110" - wire $and$libresoc.v:125074$4727_Y - attribute \src "libresoc.v:125087.18-125087.114" - wire $and$libresoc.v:125087$4740_Y - attribute \src "libresoc.v:125088.18-125088.116" - wire $and$libresoc.v:125088$4741_Y - attribute \src "libresoc.v:125090.18-125090.114" - wire $and$libresoc.v:125090$4743_Y - attribute \src "libresoc.v:125092.18-125092.110" - wire $and$libresoc.v:125092$4745_Y - attribute \src "libresoc.v:125093.17-125093.112" - wire $and$libresoc.v:125093$4746_Y - attribute \src "libresoc.v:125094.17-125094.114" - wire $and$libresoc.v:125094$4747_Y - attribute \src "libresoc.v:125075.18-125075.132" - wire $eq$libresoc.v:125075$4728_Y - attribute \src "libresoc.v:125076.18-125076.132" - wire $eq$libresoc.v:125076$4729_Y - attribute \src "libresoc.v:125078.18-125078.110" - wire $eq$libresoc.v:125078$4731_Y - attribute \src "libresoc.v:125079.18-125079.110" - wire $eq$libresoc.v:125079$4732_Y - attribute \src "libresoc.v:125081.18-125081.112" - wire $eq$libresoc.v:125081$4734_Y - attribute \src "libresoc.v:125082.17-125082.136" - wire $eq$libresoc.v:125082$4735_Y - attribute \src "libresoc.v:125084.18-125084.110" - wire $eq$libresoc.v:125084$4737_Y - attribute \src "libresoc.v:125086.18-125086.137" - wire $eq$libresoc.v:125086$4739_Y - attribute \src "libresoc.v:125089.18-125089.137" - wire $eq$libresoc.v:125089$4742_Y - attribute \src "libresoc.v:125095.17-125095.136" - wire $eq$libresoc.v:125095$4748_Y - attribute \src "libresoc.v:125073.18-125073.110" - wire $not$libresoc.v:125073$4726_Y - attribute \src "libresoc.v:125091.18-125091.110" - wire $not$libresoc.v:125091$4744_Y - attribute \src "libresoc.v:125077.18-125077.110" - wire $or$libresoc.v:125077$4730_Y - attribute \src "libresoc.v:125080.18-125080.110" - wire $or$libresoc.v:125080$4733_Y - attribute \src "libresoc.v:125083.18-125083.110" - wire $or$libresoc.v:125083$4736_Y - attribute \src "libresoc.v:125085.18-125085.110" - wire $or$libresoc.v:125085$4738_Y + attribute \src "libresoc.v:125148.18-125148.113" + wire $and$libresoc.v:125148$4725_Y + attribute \src "libresoc.v:125150.18-125150.110" + wire $and$libresoc.v:125150$4727_Y + attribute \src "libresoc.v:125163.18-125163.114" + wire $and$libresoc.v:125163$4740_Y + attribute \src "libresoc.v:125164.18-125164.116" + wire $and$libresoc.v:125164$4741_Y + attribute \src "libresoc.v:125166.18-125166.114" + wire $and$libresoc.v:125166$4743_Y + attribute \src "libresoc.v:125168.18-125168.110" + wire $and$libresoc.v:125168$4745_Y + attribute \src "libresoc.v:125169.17-125169.112" + wire $and$libresoc.v:125169$4746_Y + attribute \src "libresoc.v:125170.17-125170.114" + wire $and$libresoc.v:125170$4747_Y + attribute \src "libresoc.v:125151.18-125151.132" + wire $eq$libresoc.v:125151$4728_Y + attribute \src "libresoc.v:125152.18-125152.132" + wire $eq$libresoc.v:125152$4729_Y + attribute \src "libresoc.v:125154.18-125154.110" + wire $eq$libresoc.v:125154$4731_Y + attribute \src "libresoc.v:125155.18-125155.110" + wire $eq$libresoc.v:125155$4732_Y + attribute \src "libresoc.v:125157.18-125157.112" + wire $eq$libresoc.v:125157$4734_Y + attribute \src "libresoc.v:125158.17-125158.136" + wire $eq$libresoc.v:125158$4735_Y + attribute \src "libresoc.v:125160.18-125160.110" + wire $eq$libresoc.v:125160$4737_Y + attribute \src "libresoc.v:125162.18-125162.137" + wire $eq$libresoc.v:125162$4739_Y + attribute \src "libresoc.v:125165.18-125165.137" + wire $eq$libresoc.v:125165$4742_Y + attribute \src "libresoc.v:125171.17-125171.136" + wire $eq$libresoc.v:125171$4748_Y + attribute \src "libresoc.v:125149.18-125149.110" + wire $not$libresoc.v:125149$4726_Y + attribute \src "libresoc.v:125167.18-125167.110" + wire $not$libresoc.v:125167$4744_Y + attribute \src "libresoc.v:125153.18-125153.110" + wire $or$libresoc.v:125153$4730_Y + attribute \src "libresoc.v:125156.18-125156.110" + wire $or$libresoc.v:125156$4733_Y + attribute \src "libresoc.v:125159.18-125159.110" + wire $or$libresoc.v:125159$4736_Y + attribute \src "libresoc.v:125161.18-125161.110" + wire $or$libresoc.v:125161$4738_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" @@ -195139,7 +195202,7 @@ module \dec_SHIFT_ROT attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:124664.7-124664.15" + attribute \src "libresoc.v:124740.7-124740.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" wire width 32 \insn_in @@ -195154,7 +195217,7 @@ module \dec_SHIFT_ROT attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" wire width 10 \spr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:125072$4725 + cell $and $and$libresoc.v:125148$4725 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195162,10 +195225,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:125072$4725_Y + connect \Y $and$libresoc.v:125148$4725_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:125074$4727 + cell $and $and$libresoc.v:125150$4727 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195173,10 +195236,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:125074$4727_Y + connect \Y $and$libresoc.v:125150$4727_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:125087$4740 + cell $and $and$libresoc.v:125163$4740 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195184,10 +195247,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:125087$4740_Y + connect \Y $and$libresoc.v:125163$4740_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:125088$4741 + cell $and $and$libresoc.v:125164$4741 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195195,10 +195258,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:125088$4741_Y + connect \Y $and$libresoc.v:125164$4741_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:125090$4743 + cell $and $and$libresoc.v:125166$4743 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195206,10 +195269,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:125090$4743_Y + connect \Y $and$libresoc.v:125166$4743_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:125092$4745 + cell $and $and$libresoc.v:125168$4745 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195217,10 +195280,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:125092$4745_Y + connect \Y $and$libresoc.v:125168$4745_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:125093$4746 + cell $and $and$libresoc.v:125169$4746 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195228,10 +195291,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:125093$4746_Y + connect \Y $and$libresoc.v:125169$4746_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:125094$4747 + cell $and $and$libresoc.v:125170$4747 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195239,10 +195302,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:125094$4747_Y + connect \Y $and$libresoc.v:125170$4747_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $eq $eq$libresoc.v:125075$4728 + cell $eq $eq$libresoc.v:125151$4728 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -195250,10 +195313,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:125075$4728_Y + connect \Y $eq$libresoc.v:125151$4728_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $eq $eq$libresoc.v:125076$4729 + cell $eq $eq$libresoc.v:125152$4729 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -195261,10 +195324,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:125076$4729_Y + connect \Y $eq$libresoc.v:125152$4729_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:125078$4731 + cell $eq $eq$libresoc.v:125154$4731 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -195272,10 +195335,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:125078$4731_Y + connect \Y $eq$libresoc.v:125154$4731_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:125079$4732 + cell $eq $eq$libresoc.v:125155$4732 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -195283,10 +195346,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:125079$4732_Y + connect \Y $eq$libresoc.v:125155$4732_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:125081$4734 + cell $eq $eq$libresoc.v:125157$4734 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -195294,10 +195357,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:125081$4734_Y + connect \Y $eq$libresoc.v:125157$4734_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $eq $eq$libresoc.v:125082$4735 + cell $eq $eq$libresoc.v:125158$4735 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -195305,10 +195368,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:125082$4735_Y + connect \Y $eq$libresoc.v:125158$4735_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $eq $eq$libresoc.v:125084$4737 + cell $eq $eq$libresoc.v:125160$4737 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -195316,10 +195379,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:125084$4737_Y + connect \Y $eq$libresoc.v:125160$4737_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $eq $eq$libresoc.v:125086$4739 + cell $eq $eq$libresoc.v:125162$4739 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -195327,10 +195390,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:125086$4739_Y + connect \Y $eq$libresoc.v:125162$4739_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $eq $eq$libresoc.v:125089$4742 + cell $eq $eq$libresoc.v:125165$4742 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -195338,10 +195401,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:125089$4742_Y + connect \Y $eq$libresoc.v:125165$4742_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $eq $eq$libresoc.v:125095$4748 + cell $eq $eq$libresoc.v:125171$4748 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -195349,26 +195412,26 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \dec_SHIFT_ROT_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:125095$4748_Y + connect \Y $eq$libresoc.v:125171$4748_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $not $not$libresoc.v:125073$4726 + cell $not $not$libresoc.v:125149$4726 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:125073$4726_Y + connect \Y $not$libresoc.v:125149$4726_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $not $not$libresoc.v:125091$4744 + cell $not $not$libresoc.v:125167$4744 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:125091$4744_Y + connect \Y $not$libresoc.v:125167$4744_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $or $or$libresoc.v:125077$4730 + cell $or $or$libresoc.v:125153$4730 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195376,10 +195439,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:125077$4730_Y + connect \Y $or$libresoc.v:125153$4730_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:125080$4733 + cell $or $or$libresoc.v:125156$4733 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195387,10 +195450,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:125080$4733_Y + connect \Y $or$libresoc.v:125156$4733_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:125083$4736 + cell $or $or$libresoc.v:125159$4736 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195398,10 +195461,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:125083$4736_Y + connect \Y $or$libresoc.v:125159$4736_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $or $or$libresoc.v:125085$4738 + cell $or $or$libresoc.v:125161$4738 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195409,10 +195472,10 @@ module \dec_SHIFT_ROT parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:125085$4738_Y + connect \Y $or$libresoc.v:125161$4738_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:125096.13-125121.4" + attribute \src "libresoc.v:125172.13-125197.4" cell \dec$162 \dec connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS @@ -195440,7 +195503,7 @@ module \dec_SHIFT_ROT connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:125122.16-125133.4" + attribute \src "libresoc.v:125198.16-125209.4" cell \dec_bi$165 \dec_bi connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS @@ -195454,7 +195517,7 @@ module \dec_SHIFT_ROT connect \sel_in \dec_bi_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:125134.16-125140.4" + attribute \src "libresoc.v:125210.16-125216.4" cell \dec_oe$164 \dec_oe connect \SHIFT_ROT_OE \dec_SHIFT_ROT_OE connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op @@ -195463,29 +195526,29 @@ module \dec_SHIFT_ROT connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:125141.16-125146.4" + attribute \src "libresoc.v:125217.16-125222.4" cell \dec_rc$163 \dec_rc connect \SHIFT_ROT_Rc \dec_SHIFT_ROT_Rc connect \rc \dec_rc_rc connect \rc_ok \dec_rc_rc_ok connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:124664.7-124664.20" - process $proc$libresoc.v:124664$4752 + attribute \src "libresoc.v:124740.7-124740.20" + process $proc$libresoc.v:124740$4752 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:125147.3-125161.6" - process $proc$libresoc.v:125147$4749 + attribute \src "libresoc.v:125223.3-125237.6" + process $proc$libresoc.v:125223$4749 assign { } { } assign { } { } assign $0\SHIFT_ROT__write_cr0[0:0] $1\SHIFT_ROT__write_cr0[0:0] - attribute \src "libresoc.v:125148.5-125148.29" + attribute \src "libresoc.v:125224.5-125224.29" switch \initial - attribute \src "libresoc.v:125148.9-125148.17" + attribute \src "libresoc.v:125224.9-125224.17" case 1'1 case end @@ -195505,14 +195568,14 @@ module \dec_SHIFT_ROT sync always update \SHIFT_ROT__write_cr0 $0\SHIFT_ROT__write_cr0[0:0] end - attribute \src "libresoc.v:125162.3-125174.6" - process $proc$libresoc.v:125162$4750 + attribute \src "libresoc.v:125238.3-125250.6" + process $proc$libresoc.v:125238$4750 assign { } { } assign { } { } assign $0\SHIFT_ROT__insn_type[6:0] $1\SHIFT_ROT__insn_type[6:0] - attribute \src "libresoc.v:125163.5-125163.29" + attribute \src "libresoc.v:125239.5-125239.29" switch \initial - attribute \src "libresoc.v:125163.9-125163.17" + attribute \src "libresoc.v:125239.9-125239.17" case 1'1 case end @@ -195532,13 +195595,13 @@ module \dec_SHIFT_ROT sync always update \SHIFT_ROT__insn_type $0\SHIFT_ROT__insn_type[6:0] end - attribute \src "libresoc.v:125175.3-125189.6" - process $proc$libresoc.v:125175$4751 + attribute \src "libresoc.v:125251.3-125265.6" + process $proc$libresoc.v:125251$4751 assign { } { } assign $0\SHIFT_ROT__fn_unit[13:0] $1\SHIFT_ROT__fn_unit[13:0] - attribute \src "libresoc.v:125176.5-125176.29" + attribute \src "libresoc.v:125252.5-125252.29" switch \initial - attribute \src "libresoc.v:125176.9-125176.17" + attribute \src "libresoc.v:125252.9-125252.17" case 1'1 case end @@ -195560,30 +195623,30 @@ module \dec_SHIFT_ROT sync always update \SHIFT_ROT__fn_unit $0\SHIFT_ROT__fn_unit[13:0] end - connect \$10 $and$libresoc.v:125072$4725_Y - connect \$12 $not$libresoc.v:125073$4726_Y - connect \$14 $and$libresoc.v:125074$4727_Y - connect \$16 $eq$libresoc.v:125075$4728_Y - connect \$18 $eq$libresoc.v:125076$4729_Y - connect \$20 $or$libresoc.v:125077$4730_Y - connect \$22 $eq$libresoc.v:125078$4731_Y - connect \$24 $eq$libresoc.v:125079$4732_Y - connect \$26 $or$libresoc.v:125080$4733_Y - connect \$28 $eq$libresoc.v:125081$4734_Y - connect \$2 $eq$libresoc.v:125082$4735_Y - connect \$30 $or$libresoc.v:125083$4736_Y - connect \$32 $eq$libresoc.v:125084$4737_Y - connect \$34 $or$libresoc.v:125085$4738_Y - connect \$36 $eq$libresoc.v:125086$4739_Y - connect \$38 $and$libresoc.v:125087$4740_Y - connect \$40 $and$libresoc.v:125088$4741_Y - connect \$42 $eq$libresoc.v:125089$4742_Y - connect \$44 $and$libresoc.v:125090$4743_Y - connect \$46 $not$libresoc.v:125091$4744_Y - connect \$48 $and$libresoc.v:125092$4745_Y - connect \$4 $and$libresoc.v:125093$4746_Y - connect \$6 $and$libresoc.v:125094$4747_Y - connect \$8 $eq$libresoc.v:125095$4748_Y + connect \$10 $and$libresoc.v:125148$4725_Y + connect \$12 $not$libresoc.v:125149$4726_Y + connect \$14 $and$libresoc.v:125150$4727_Y + connect \$16 $eq$libresoc.v:125151$4728_Y + connect \$18 $eq$libresoc.v:125152$4729_Y + connect \$20 $or$libresoc.v:125153$4730_Y + connect \$22 $eq$libresoc.v:125154$4731_Y + connect \$24 $eq$libresoc.v:125155$4732_Y + connect \$26 $or$libresoc.v:125156$4733_Y + connect \$28 $eq$libresoc.v:125157$4734_Y + connect \$2 $eq$libresoc.v:125158$4735_Y + connect \$30 $or$libresoc.v:125159$4736_Y + connect \$32 $eq$libresoc.v:125160$4737_Y + connect \$34 $or$libresoc.v:125161$4738_Y + connect \$36 $eq$libresoc.v:125162$4739_Y + connect \$38 $and$libresoc.v:125163$4740_Y + connect \$40 $and$libresoc.v:125164$4741_Y + connect \$42 $eq$libresoc.v:125165$4742_Y + connect \$44 $and$libresoc.v:125166$4743_Y + connect \$46 $not$libresoc.v:125167$4744_Y + connect \$48 $and$libresoc.v:125168$4745_Y + connect \$4 $and$libresoc.v:125169$4746_Y + connect \$6 $and$libresoc.v:125170$4747_Y + connect \$8 $eq$libresoc.v:125171$4748_Y connect \SHIFT_ROT__is_signed \dec_SHIFT_ROT_sgn connect \SHIFT_ROT__is_32bit \dec_SHIFT_ROT_is_32b connect \SHIFT_ROT__output_carry \dec_SHIFT_ROT_cry_out @@ -195604,69 +195667,69 @@ module \dec_SHIFT_ROT connect \insn_in \dec_opcode_in connect \SHIFT_ROT__insn \dec_opcode_in end -attribute \src "libresoc.v:125213.1-125591.10" +attribute \src "libresoc.v:125289.1-125667.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR" attribute \generator "nMigen" module \dec_SPR - attribute \src "libresoc.v:125567.3-125581.6" + attribute \src "libresoc.v:125643.3-125657.6" wire width 14 $0\SPR__fn_unit[13:0] - attribute \src "libresoc.v:125554.3-125566.6" + attribute \src "libresoc.v:125630.3-125642.6" wire width 7 $0\SPR__insn_type[6:0] - attribute \src "libresoc.v:125214.7-125214.20" + attribute \src "libresoc.v:125290.7-125290.20" wire $0\initial[0:0] - attribute \src "libresoc.v:125567.3-125581.6" + attribute \src "libresoc.v:125643.3-125657.6" wire width 14 $1\SPR__fn_unit[13:0] - attribute \src "libresoc.v:125554.3-125566.6" + attribute \src "libresoc.v:125630.3-125642.6" wire width 7 $1\SPR__insn_type[6:0] - attribute \src "libresoc.v:125508.18-125508.113" - wire $and$libresoc.v:125508$4753_Y - attribute \src "libresoc.v:125510.18-125510.110" - wire $and$libresoc.v:125510$4755_Y - attribute \src "libresoc.v:125523.18-125523.114" - wire $and$libresoc.v:125523$4768_Y - attribute \src "libresoc.v:125524.18-125524.116" - wire $and$libresoc.v:125524$4769_Y - attribute \src "libresoc.v:125526.18-125526.114" - wire $and$libresoc.v:125526$4771_Y - attribute \src "libresoc.v:125528.18-125528.110" - wire $and$libresoc.v:125528$4773_Y - attribute \src "libresoc.v:125529.17-125529.112" - wire $and$libresoc.v:125529$4774_Y - attribute \src "libresoc.v:125530.17-125530.114" - wire $and$libresoc.v:125530$4775_Y - attribute \src "libresoc.v:125511.18-125511.126" - wire $eq$libresoc.v:125511$4756_Y - attribute \src "libresoc.v:125512.18-125512.126" - wire $eq$libresoc.v:125512$4757_Y - attribute \src "libresoc.v:125514.18-125514.110" - wire $eq$libresoc.v:125514$4759_Y - attribute \src "libresoc.v:125515.18-125515.110" - wire $eq$libresoc.v:125515$4760_Y - attribute \src "libresoc.v:125517.18-125517.112" - wire $eq$libresoc.v:125517$4762_Y - attribute \src "libresoc.v:125518.17-125518.130" - wire $eq$libresoc.v:125518$4763_Y - attribute \src "libresoc.v:125520.18-125520.110" - wire $eq$libresoc.v:125520$4765_Y - attribute \src "libresoc.v:125522.18-125522.131" - wire $eq$libresoc.v:125522$4767_Y - attribute \src "libresoc.v:125525.18-125525.131" - wire $eq$libresoc.v:125525$4770_Y - attribute \src "libresoc.v:125531.17-125531.130" - wire $eq$libresoc.v:125531$4776_Y - attribute \src "libresoc.v:125509.18-125509.110" - wire $not$libresoc.v:125509$4754_Y - attribute \src "libresoc.v:125527.18-125527.110" - wire $not$libresoc.v:125527$4772_Y - attribute \src "libresoc.v:125513.18-125513.110" - wire $or$libresoc.v:125513$4758_Y - attribute \src "libresoc.v:125516.18-125516.110" - wire $or$libresoc.v:125516$4761_Y - attribute \src "libresoc.v:125519.18-125519.110" - wire $or$libresoc.v:125519$4764_Y - attribute \src "libresoc.v:125521.18-125521.110" - wire $or$libresoc.v:125521$4766_Y + attribute \src "libresoc.v:125584.18-125584.113" + wire $and$libresoc.v:125584$4753_Y + attribute \src "libresoc.v:125586.18-125586.110" + wire $and$libresoc.v:125586$4755_Y + attribute \src "libresoc.v:125599.18-125599.114" + wire $and$libresoc.v:125599$4768_Y + attribute \src "libresoc.v:125600.18-125600.116" + wire $and$libresoc.v:125600$4769_Y + attribute \src "libresoc.v:125602.18-125602.114" + wire $and$libresoc.v:125602$4771_Y + attribute \src "libresoc.v:125604.18-125604.110" + wire $and$libresoc.v:125604$4773_Y + attribute \src "libresoc.v:125605.17-125605.112" + wire $and$libresoc.v:125605$4774_Y + attribute \src "libresoc.v:125606.17-125606.114" + wire $and$libresoc.v:125606$4775_Y + attribute \src "libresoc.v:125587.18-125587.126" + wire $eq$libresoc.v:125587$4756_Y + attribute \src "libresoc.v:125588.18-125588.126" + wire $eq$libresoc.v:125588$4757_Y + attribute \src "libresoc.v:125590.18-125590.110" + wire $eq$libresoc.v:125590$4759_Y + attribute \src "libresoc.v:125591.18-125591.110" + wire $eq$libresoc.v:125591$4760_Y + attribute \src "libresoc.v:125593.18-125593.112" + wire $eq$libresoc.v:125593$4762_Y + attribute \src "libresoc.v:125594.17-125594.130" + wire $eq$libresoc.v:125594$4763_Y + attribute \src "libresoc.v:125596.18-125596.110" + wire $eq$libresoc.v:125596$4765_Y + attribute \src "libresoc.v:125598.18-125598.131" + wire $eq$libresoc.v:125598$4767_Y + attribute \src "libresoc.v:125601.18-125601.131" + wire $eq$libresoc.v:125601$4770_Y + attribute \src "libresoc.v:125607.17-125607.130" + wire $eq$libresoc.v:125607$4776_Y + attribute \src "libresoc.v:125585.18-125585.110" + wire $not$libresoc.v:125585$4754_Y + attribute \src "libresoc.v:125603.18-125603.110" + wire $not$libresoc.v:125603$4772_Y + attribute \src "libresoc.v:125589.18-125589.110" + wire $or$libresoc.v:125589$4758_Y + attribute \src "libresoc.v:125592.18-125592.110" + wire $or$libresoc.v:125592$4761_Y + attribute \src "libresoc.v:125595.18-125595.110" + wire $or$libresoc.v:125595$4764_Y + attribute \src "libresoc.v:125597.18-125597.110" + wire $or$libresoc.v:125597$4766_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" @@ -195946,7 +196009,7 @@ module \dec_SPR attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 \dec_rc_sel_in - attribute \src "libresoc.v:125214.7-125214.15" + attribute \src "libresoc.v:125290.7-125290.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" wire width 32 \insn_in @@ -195961,7 +196024,7 @@ module \dec_SPR attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:808" wire width 10 \spr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:125508$4753 + cell $and $and$libresoc.v:125584$4753 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195969,10 +196032,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$8 - connect \Y $and$libresoc.v:125508$4753_Y + connect \Y $and$libresoc.v:125584$4753_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:125510$4755 + cell $and $and$libresoc.v:125586$4755 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195980,10 +196043,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$10 connect \B \$12 - connect \Y $and$libresoc.v:125510$4755_Y + connect \Y $and$libresoc.v:125586$4755_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:125523$4768 + cell $and $and$libresoc.v:125599$4768 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -195991,10 +196054,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$36 - connect \Y $and$libresoc.v:125523$4768_Y + connect \Y $and$libresoc.v:125599$4768_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:125524$4769 + cell $and $and$libresoc.v:125600$4769 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196002,10 +196065,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$38 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:125524$4769_Y + connect \Y $and$libresoc.v:125600$4769_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:125526$4771 + cell $and $and$libresoc.v:125602$4771 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196013,10 +196076,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$42 - connect \Y $and$libresoc.v:125526$4771_Y + connect \Y $and$libresoc.v:125602$4771_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $and $and$libresoc.v:125528$4773 + cell $and $and$libresoc.v:125604$4773 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196024,10 +196087,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:125528$4773_Y + connect \Y $and$libresoc.v:125604$4773_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:125529$4774 + cell $and $and$libresoc.v:125605$4774 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196035,10 +196098,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \is_spr_mv connect \B \$2 - connect \Y $and$libresoc.v:125529$4774_Y + connect \Y $and$libresoc.v:125605$4774_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $and $and$libresoc.v:125530$4775 + cell $and $and$libresoc.v:125606$4775 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196046,10 +196109,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$4 connect \B \is_mmu_spr - connect \Y $and$libresoc.v:125530$4775_Y + connect \Y $and$libresoc.v:125606$4775_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:815" - cell $eq $eq$libresoc.v:125511$4756 + cell $eq $eq$libresoc.v:125587$4756 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -196057,10 +196120,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \dec_SPR_internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:125511$4756_Y + connect \Y $eq$libresoc.v:125587$4756_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $eq $eq$libresoc.v:125512$4757 + cell $eq $eq$libresoc.v:125588$4757 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -196068,10 +196131,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \dec_SPR_internal_op connect \B 7'0101110 - connect \Y $eq$libresoc.v:125512$4757_Y + connect \Y $eq$libresoc.v:125588$4757_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:125514$4759 + cell $eq $eq$libresoc.v:125590$4759 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -196079,10 +196142,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10010 - connect \Y $eq$libresoc.v:125514$4759_Y + connect \Y $eq$libresoc.v:125590$4759_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:125515$4760 + cell $eq $eq$libresoc.v:125591$4760 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -196090,10 +196153,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \spr connect \B 5'10011 - connect \Y $eq$libresoc.v:125515$4760_Y + connect \Y $eq$libresoc.v:125591$4760_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $eq $eq$libresoc.v:125517$4762 + cell $eq $eq$libresoc.v:125593$4762 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -196101,10 +196164,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \spr connect \B 10'1011010000 - connect \Y $eq$libresoc.v:125517$4762_Y + connect \Y $eq$libresoc.v:125593$4762_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $eq $eq$libresoc.v:125518$4763 + cell $eq $eq$libresoc.v:125594$4763 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -196112,10 +196175,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \dec_SPR_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:125518$4763_Y + connect \Y $eq$libresoc.v:125594$4763_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $eq $eq$libresoc.v:125520$4765 + cell $eq $eq$libresoc.v:125596$4765 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -196123,10 +196186,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \spr connect \B 6'110000 - connect \Y $eq$libresoc.v:125520$4765_Y + connect \Y $eq$libresoc.v:125596$4765_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:822" - cell $eq $eq$libresoc.v:125522$4767 + cell $eq $eq$libresoc.v:125598$4767 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -196134,10 +196197,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \dec_SPR_function_unit connect \B 14'00010000000000 - connect \Y $eq$libresoc.v:125522$4767_Y + connect \Y $eq$libresoc.v:125598$4767_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $eq $eq$libresoc.v:125525$4770 + cell $eq $eq$libresoc.v:125601$4770 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -196145,10 +196208,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \dec_SPR_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:125525$4770_Y + connect \Y $eq$libresoc.v:125601$4770_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $eq $eq$libresoc.v:125531$4776 + cell $eq $eq$libresoc.v:125607$4776 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -196156,26 +196219,26 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \dec_SPR_function_unit connect \B 14'00100000000000 - connect \Y $eq$libresoc.v:125531$4776_Y + connect \Y $eq$libresoc.v:125607$4776_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $not $not$libresoc.v:125509$4754 + cell $not $not$libresoc.v:125585$4754 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:125509$4754_Y + connect \Y $not$libresoc.v:125585$4754_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:826" - cell $not $not$libresoc.v:125527$4772 + cell $not $not$libresoc.v:125603$4772 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_mmu_spr - connect \Y $not$libresoc.v:125527$4772_Y + connect \Y $not$libresoc.v:125603$4772_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:816" - cell $or $or$libresoc.v:125513$4758 + cell $or $or$libresoc.v:125589$4758 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196183,10 +196246,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$16 connect \B \$18 - connect \Y $or$libresoc.v:125513$4758_Y + connect \Y $or$libresoc.v:125589$4758_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:125516$4761 + cell $or $or$libresoc.v:125592$4761 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196194,10 +196257,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$22 connect \B \$24 - connect \Y $or$libresoc.v:125516$4761_Y + connect \Y $or$libresoc.v:125592$4761_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:819" - cell $or $or$libresoc.v:125519$4764 + cell $or $or$libresoc.v:125595$4764 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196205,10 +196268,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$26 connect \B \$28 - connect \Y $or$libresoc.v:125519$4764_Y + connect \Y $or$libresoc.v:125595$4764_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:820" - cell $or $or$libresoc.v:125521$4766 + cell $or $or$libresoc.v:125597$4766 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196216,10 +196279,10 @@ module \dec_SPR parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:125521$4766_Y + connect \Y $or$libresoc.v:125597$4766_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:125532.13-125544.4" + attribute \src "libresoc.v:125608.13-125620.4" cell \dec$150 \dec connect \SPR_OE \dec_SPR_OE connect \SPR_Rc \dec_SPR_Rc @@ -196234,34 +196297,34 @@ module \dec_SPR connect \raw_opcode_in \raw_opcode_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:125545.16-125549.4" + attribute \src "libresoc.v:125621.16-125625.4" cell \dec_oe$152 \dec_oe connect \SPR_OE \dec_SPR_OE connect \SPR_internal_op \dec_SPR_internal_op connect \sel_in \dec_oe_sel_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:125550.16-125553.4" + attribute \src "libresoc.v:125626.16-125629.4" cell \dec_rc$151 \dec_rc connect \SPR_Rc \dec_SPR_Rc connect \sel_in \dec_rc_sel_in end - attribute \src "libresoc.v:125214.7-125214.20" - process $proc$libresoc.v:125214$4779 + attribute \src "libresoc.v:125290.7-125290.20" + process $proc$libresoc.v:125290$4779 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:125554.3-125566.6" - process $proc$libresoc.v:125554$4777 + attribute \src "libresoc.v:125630.3-125642.6" + process $proc$libresoc.v:125630$4777 assign { } { } assign { } { } assign $0\SPR__insn_type[6:0] $1\SPR__insn_type[6:0] - attribute \src "libresoc.v:125555.5-125555.29" + attribute \src "libresoc.v:125631.5-125631.29" switch \initial - attribute \src "libresoc.v:125555.9-125555.17" + attribute \src "libresoc.v:125631.9-125631.17" case 1'1 case end @@ -196281,13 +196344,13 @@ module \dec_SPR sync always update \SPR__insn_type $0\SPR__insn_type[6:0] end - attribute \src "libresoc.v:125567.3-125581.6" - process $proc$libresoc.v:125567$4778 + attribute \src "libresoc.v:125643.3-125657.6" + process $proc$libresoc.v:125643$4778 assign { } { } assign $0\SPR__fn_unit[13:0] $1\SPR__fn_unit[13:0] - attribute \src "libresoc.v:125568.5-125568.29" + attribute \src "libresoc.v:125644.5-125644.29" switch \initial - attribute \src "libresoc.v:125568.9-125568.17" + attribute \src "libresoc.v:125644.9-125644.17" case 1'1 case end @@ -196309,30 +196372,30 @@ module \dec_SPR sync always update \SPR__fn_unit $0\SPR__fn_unit[13:0] end - connect \$10 $and$libresoc.v:125508$4753_Y - connect \$12 $not$libresoc.v:125509$4754_Y - connect \$14 $and$libresoc.v:125510$4755_Y - connect \$16 $eq$libresoc.v:125511$4756_Y - connect \$18 $eq$libresoc.v:125512$4757_Y - connect \$20 $or$libresoc.v:125513$4758_Y - connect \$22 $eq$libresoc.v:125514$4759_Y - connect \$24 $eq$libresoc.v:125515$4760_Y - connect \$26 $or$libresoc.v:125516$4761_Y - connect \$28 $eq$libresoc.v:125517$4762_Y - connect \$2 $eq$libresoc.v:125518$4763_Y - connect \$30 $or$libresoc.v:125519$4764_Y - connect \$32 $eq$libresoc.v:125520$4765_Y - connect \$34 $or$libresoc.v:125521$4766_Y - connect \$36 $eq$libresoc.v:125522$4767_Y - connect \$38 $and$libresoc.v:125523$4768_Y - connect \$40 $and$libresoc.v:125524$4769_Y - connect \$42 $eq$libresoc.v:125525$4770_Y - connect \$44 $and$libresoc.v:125526$4771_Y - connect \$46 $not$libresoc.v:125527$4772_Y - connect \$48 $and$libresoc.v:125528$4773_Y - connect \$4 $and$libresoc.v:125529$4774_Y - connect \$6 $and$libresoc.v:125530$4775_Y - connect \$8 $eq$libresoc.v:125531$4776_Y + connect \$10 $and$libresoc.v:125584$4753_Y + connect \$12 $not$libresoc.v:125585$4754_Y + connect \$14 $and$libresoc.v:125586$4755_Y + connect \$16 $eq$libresoc.v:125587$4756_Y + connect \$18 $eq$libresoc.v:125588$4757_Y + connect \$20 $or$libresoc.v:125589$4758_Y + connect \$22 $eq$libresoc.v:125590$4759_Y + connect \$24 $eq$libresoc.v:125591$4760_Y + connect \$26 $or$libresoc.v:125592$4761_Y + connect \$28 $eq$libresoc.v:125593$4762_Y + connect \$2 $eq$libresoc.v:125594$4763_Y + connect \$30 $or$libresoc.v:125595$4764_Y + connect \$32 $eq$libresoc.v:125596$4765_Y + connect \$34 $or$libresoc.v:125597$4766_Y + connect \$36 $eq$libresoc.v:125598$4767_Y + connect \$38 $and$libresoc.v:125599$4768_Y + connect \$40 $and$libresoc.v:125600$4769_Y + connect \$42 $eq$libresoc.v:125601$4770_Y + connect \$44 $and$libresoc.v:125602$4771_Y + connect \$46 $not$libresoc.v:125603$4772_Y + connect \$48 $and$libresoc.v:125604$4773_Y + connect \$4 $and$libresoc.v:125605$4774_Y + connect \$6 $and$libresoc.v:125606$4775_Y + connect \$8 $eq$libresoc.v:125607$4776_Y connect \SPR__is_32bit \dec_SPR_is_32b connect \is_mmu_spr \$34 connect \is_spr_mv \$20 @@ -196343,95 +196406,95 @@ module \dec_SPR connect \insn_in \dec_opcode_in connect \SPR__insn \dec_opcode_in end -attribute \src "libresoc.v:125595.1-126124.10" +attribute \src "libresoc.v:125671.1-126224.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a" attribute \generator "nMigen" module \dec_a - attribute \src "libresoc.v:126052.3-126087.6" + attribute \src "libresoc.v:126128.3-126163.6" wire width 3 $0\fast_a[2:0] - attribute \src "libresoc.v:126052.3-126087.6" + attribute \src "libresoc.v:126128.3-126163.6" wire $0\fast_a_ok[0:0] - attribute \src "libresoc.v:125596.7-125596.20" + attribute \src "libresoc.v:125672.7-125672.20" wire $0\initial[0:0] - attribute \src "libresoc.v:126020.3-126035.6" + attribute \src "libresoc.v:126096.3-126111.6" wire width 5 $0\reg_a[4:0] - attribute \src "libresoc.v:126036.3-126051.6" + attribute \src "libresoc.v:126112.3-126127.6" wire $0\reg_a_ok[0:0] - attribute \src "libresoc.v:126088.3-126098.6" + attribute \src "libresoc.v:126164.3-126182.6" wire width 10 $0\spr[9:0] - attribute \src "libresoc.v:126110.3-126121.6" + attribute \src "libresoc.v:126202.3-126221.6" wire width 10 $0\spr_a[9:0] - attribute \src "libresoc.v:126110.3-126121.6" + attribute \src "libresoc.v:126202.3-126221.6" wire $0\spr_a_ok[0:0] - attribute \src "libresoc.v:126099.3-126109.6" + attribute \src "libresoc.v:126183.3-126201.6" wire width 10 $0\sprmap_spr_i[9:0] - attribute \src "libresoc.v:126052.3-126087.6" + attribute \src "libresoc.v:126128.3-126163.6" wire width 3 $1\fast_a[2:0] - attribute \src "libresoc.v:126052.3-126087.6" + attribute \src "libresoc.v:126128.3-126163.6" wire $1\fast_a_ok[0:0] - attribute \src "libresoc.v:126020.3-126035.6" + attribute \src "libresoc.v:126096.3-126111.6" wire width 5 $1\reg_a[4:0] - attribute \src "libresoc.v:126036.3-126051.6" + attribute \src "libresoc.v:126112.3-126127.6" wire $1\reg_a_ok[0:0] - attribute \src "libresoc.v:126088.3-126098.6" + attribute \src "libresoc.v:126164.3-126182.6" wire width 10 $1\spr[9:0] - attribute \src "libresoc.v:126110.3-126121.6" + attribute \src "libresoc.v:126202.3-126221.6" wire width 10 $1\spr_a[9:0] - attribute \src "libresoc.v:126110.3-126121.6" + attribute \src "libresoc.v:126202.3-126221.6" wire $1\spr_a_ok[0:0] - attribute \src "libresoc.v:126099.3-126109.6" + attribute \src "libresoc.v:126183.3-126201.6" wire width 10 $1\sprmap_spr_i[9:0] - attribute \src "libresoc.v:126052.3-126087.6" + attribute \src "libresoc.v:126128.3-126163.6" wire width 3 $2\fast_a[2:0] - attribute \src "libresoc.v:126052.3-126087.6" + attribute \src "libresoc.v:126128.3-126163.6" wire $2\fast_a_ok[0:0] - attribute \src "libresoc.v:126020.3-126035.6" + attribute \src "libresoc.v:126096.3-126111.6" wire width 5 $2\reg_a[4:0] - attribute \src "libresoc.v:126036.3-126051.6" + attribute \src "libresoc.v:126112.3-126127.6" wire $2\reg_a_ok[0:0] - attribute \src "libresoc.v:126052.3-126087.6" + attribute \src "libresoc.v:126128.3-126163.6" wire width 3 $3\fast_a[2:0] - attribute \src "libresoc.v:126052.3-126087.6" + attribute \src "libresoc.v:126128.3-126163.6" wire $3\fast_a_ok[0:0] - attribute \src "libresoc.v:125995.18-125995.108" - wire $and$libresoc.v:125995$4781_Y - attribute \src "libresoc.v:126004.18-126004.110" - wire $and$libresoc.v:126004$4790_Y - attribute \src "libresoc.v:126009.18-126009.113" - wire $and$libresoc.v:126009$4795_Y - attribute \src "libresoc.v:125997.18-125997.112" - wire $eq$libresoc.v:125997$4783_Y - attribute \src "libresoc.v:125998.18-125998.112" - wire $eq$libresoc.v:125998$4784_Y - attribute \src "libresoc.v:125999.17-125999.111" - wire $eq$libresoc.v:125999$4785_Y - attribute \src "libresoc.v:126000.18-126000.112" - wire $eq$libresoc.v:126000$4786_Y - attribute \src "libresoc.v:126006.18-126006.112" - wire $eq$libresoc.v:126006$4792_Y - attribute \src "libresoc.v:126010.17-126010.111" - wire $eq$libresoc.v:126010$4796_Y - attribute \src "libresoc.v:126001.18-126001.109" - wire $ne$libresoc.v:126001$4787_Y - attribute \src "libresoc.v:126002.18-126002.111" - wire $ne$libresoc.v:126002$4788_Y - attribute \src "libresoc.v:126011.17-126011.108" - wire $ne$libresoc.v:126011$4797_Y - attribute \src "libresoc.v:126012.17-126012.110" - wire $ne$libresoc.v:126012$4798_Y - attribute \src "libresoc.v:126007.18-126007.105" - wire $not$libresoc.v:126007$4793_Y - attribute \src "libresoc.v:126008.18-126008.108" - wire $not$libresoc.v:126008$4794_Y - attribute \src "libresoc.v:125994.17-125994.107" - wire $or$libresoc.v:125994$4780_Y - attribute \src "libresoc.v:125996.18-125996.109" - wire $or$libresoc.v:125996$4782_Y - attribute \src "libresoc.v:126003.18-126003.110" - wire $or$libresoc.v:126003$4789_Y - attribute \src "libresoc.v:126005.18-126005.110" - wire $or$libresoc.v:126005$4791_Y + attribute \src "libresoc.v:126071.18-126071.108" + wire $and$libresoc.v:126071$4781_Y + attribute \src "libresoc.v:126080.18-126080.110" + wire $and$libresoc.v:126080$4790_Y + attribute \src "libresoc.v:126085.18-126085.113" + wire $and$libresoc.v:126085$4795_Y + attribute \src "libresoc.v:126073.18-126073.112" + wire $eq$libresoc.v:126073$4783_Y + attribute \src "libresoc.v:126074.18-126074.112" + wire $eq$libresoc.v:126074$4784_Y + attribute \src "libresoc.v:126075.17-126075.111" + wire $eq$libresoc.v:126075$4785_Y + attribute \src "libresoc.v:126076.18-126076.112" + wire $eq$libresoc.v:126076$4786_Y + attribute \src "libresoc.v:126082.18-126082.112" + wire $eq$libresoc.v:126082$4792_Y + attribute \src "libresoc.v:126086.17-126086.111" + wire $eq$libresoc.v:126086$4796_Y + attribute \src "libresoc.v:126077.18-126077.109" + wire $ne$libresoc.v:126077$4787_Y + attribute \src "libresoc.v:126078.18-126078.111" + wire $ne$libresoc.v:126078$4788_Y + attribute \src "libresoc.v:126087.17-126087.108" + wire $ne$libresoc.v:126087$4797_Y + attribute \src "libresoc.v:126088.17-126088.110" + wire $ne$libresoc.v:126088$4798_Y + attribute \src "libresoc.v:126083.18-126083.105" + wire $not$libresoc.v:126083$4793_Y + attribute \src "libresoc.v:126084.18-126084.108" + wire $not$libresoc.v:126084$4794_Y + attribute \src "libresoc.v:126070.17-126070.107" + wire $or$libresoc.v:126070$4780_Y + attribute \src "libresoc.v:126072.18-126072.109" + wire $or$libresoc.v:126072$4782_Y + attribute \src "libresoc.v:126079.18-126079.110" + wire $or$libresoc.v:126079$4789_Y + attribute \src "libresoc.v:126081.18-126081.110" + wire $or$libresoc.v:126081$4791_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" @@ -196484,7 +196547,7 @@ module \dec_a wire width 3 output 8 \fast_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 9 \fast_a_ok - attribute \src "libresoc.v:125596.7-125596.15" + attribute \src "libresoc.v:125672.7-125672.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -196826,7 +196889,7 @@ module \dec_a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" wire input 2 \sv_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" - cell $and $and$libresoc.v:125995$4781 + cell $and $and$libresoc.v:126071$4781 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196834,10 +196897,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \$3 connect \B \$9 - connect \Y $and$libresoc.v:125995$4781_Y + connect \Y $and$libresoc.v:126071$4781_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" - cell $and $and$libresoc.v:126004$4790 + cell $and $and$libresoc.v:126080$4790 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196845,10 +196908,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \$19 connect \B \$25 - connect \Y $and$libresoc.v:126004$4790_Y + connect \Y $and$libresoc.v:126080$4790_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" - cell $and $and$libresoc.v:126009$4795 + cell $and $and$libresoc.v:126085$4795 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196856,10 +196919,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \XL_XO [9] connect \B \$35 - connect \Y $and$libresoc.v:126009$4795_Y + connect \Y $and$libresoc.v:126085$4795_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122" - cell $eq $eq$libresoc.v:125997$4783 + cell $eq $eq$libresoc.v:126073$4783 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -196867,10 +196930,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'100 - connect \Y $eq$libresoc.v:125997$4783_Y + connect \Y $eq$libresoc.v:126073$4783_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" - cell $eq $eq$libresoc.v:125998$4784 + cell $eq $eq$libresoc.v:126074$4784 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -196878,10 +196941,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'001 - connect \Y $eq$libresoc.v:125998$4784_Y + connect \Y $eq$libresoc.v:126074$4784_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" - cell $eq $eq$libresoc.v:125999$4785 + cell $eq $eq$libresoc.v:126075$4785 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -196889,10 +196952,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'001 - connect \Y $eq$libresoc.v:125999$4785_Y + connect \Y $eq$libresoc.v:126075$4785_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" - cell $eq $eq$libresoc.v:126000$4786 + cell $eq $eq$libresoc.v:126076$4786 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -196900,10 +196963,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:126000$4786_Y + connect \Y $eq$libresoc.v:126076$4786_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:122" - cell $eq $eq$libresoc.v:126006$4792 + cell $eq $eq$libresoc.v:126082$4792 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -196911,10 +196974,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'100 - connect \Y $eq$libresoc.v:126006$4792_Y + connect \Y $eq$libresoc.v:126082$4792_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113" - cell $eq $eq$libresoc.v:126010$4796 + cell $eq $eq$libresoc.v:126086$4796 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -196922,10 +196985,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:126010$4796_Y + connect \Y $eq$libresoc.v:126086$4796_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" - cell $ne $ne$libresoc.v:126001$4787 + cell $ne $ne$libresoc.v:126077$4787 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -196933,10 +196996,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $ne$libresoc.v:126001$4787_Y + connect \Y $ne$libresoc.v:126077$4787_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" - cell $ne $ne$libresoc.v:126002$4788 + cell $ne $ne$libresoc.v:126078$4788 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196944,10 +197007,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sv_nz connect \B 1'0 - connect \Y $ne$libresoc.v:126002$4788_Y + connect \Y $ne$libresoc.v:126078$4788_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" - cell $ne $ne$libresoc.v:126011$4797 + cell $ne $ne$libresoc.v:126087$4797 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -196955,10 +197018,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $ne$libresoc.v:126011$4797_Y + connect \Y $ne$libresoc.v:126087$4797_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" - cell $ne $ne$libresoc.v:126012$4798 + cell $ne $ne$libresoc.v:126088$4798 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196966,26 +197029,26 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \sv_nz connect \B 1'0 - connect \Y $ne$libresoc.v:126012$4798_Y + connect \Y $ne$libresoc.v:126088$4798_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:131" - cell $not $not$libresoc.v:126007$4793 + cell $not $not$libresoc.v:126083$4793 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \BO [2] - connect \Y $not$libresoc.v:126007$4793_Y + connect \Y $not$libresoc.v:126083$4793_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138" - cell $not $not$libresoc.v:126008$4794 + cell $not $not$libresoc.v:126084$4794 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \XL_XO [5] - connect \Y $not$libresoc.v:126008$4794_Y + connect \Y $not$libresoc.v:126084$4794_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" - cell $or $or$libresoc.v:125994$4780 + cell $or $or$libresoc.v:126070$4780 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -196993,10 +197056,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \$5 connect \B \$7 - connect \Y $or$libresoc.v:125994$4780_Y + connect \Y $or$libresoc.v:126070$4780_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" - cell $or $or$libresoc.v:125996$4782 + cell $or $or$libresoc.v:126072$4782 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197004,10 +197067,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \$1 connect \B \$11 - connect \Y $or$libresoc.v:125996$4782_Y + connect \Y $or$libresoc.v:126072$4782_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" - cell $or $or$libresoc.v:126003$4789 + cell $or $or$libresoc.v:126079$4789 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197015,10 +197078,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \$21 connect \B \$23 - connect \Y $or$libresoc.v:126003$4789_Y + connect \Y $or$libresoc.v:126079$4789_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114" - cell $or $or$libresoc.v:126005$4791 + cell $or $or$libresoc.v:126081$4791 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197026,10 +197089,10 @@ module \dec_a parameter \Y_WIDTH 1 connect \A \$17 connect \B \$27 - connect \Y $or$libresoc.v:126005$4791_Y + connect \Y $or$libresoc.v:126081$4791_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:126013.10-126019.4" + attribute \src "libresoc.v:126089.10-126095.4" cell \sprmap \sprmap connect \fast_o \sprmap_fast_o connect \fast_o_ok \sprmap_fast_o_ok @@ -197037,23 +197100,23 @@ module \dec_a connect \spr_o \sprmap_spr_o connect \spr_o_ok \sprmap_spr_o_ok end - attribute \src "libresoc.v:125596.7-125596.20" - process $proc$libresoc.v:125596$4805 + attribute \src "libresoc.v:125672.7-125672.20" + process $proc$libresoc.v:125672$4805 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126020.3-126035.6" - process $proc$libresoc.v:126020$4799 + attribute \src "libresoc.v:126096.3-126111.6" + process $proc$libresoc.v:126096$4799 assign { } { } assign { } { } assign { } { } assign $0\reg_a[4:0] $2\reg_a[4:0] - attribute \src "libresoc.v:126021.5-126021.29" + attribute \src "libresoc.v:126097.5-126097.29" switch \initial - attribute \src "libresoc.v:126021.9-126021.17" + attribute \src "libresoc.v:126097.9-126097.17" case 1'1 case end @@ -197078,15 +197141,15 @@ module \dec_a sync always update \reg_a $0\reg_a[4:0] end - attribute \src "libresoc.v:126036.3-126051.6" - process $proc$libresoc.v:126036$4800 + attribute \src "libresoc.v:126112.3-126127.6" + process $proc$libresoc.v:126112$4800 assign { } { } assign { } { } assign { } { } assign $0\reg_a_ok[0:0] $2\reg_a_ok[0:0] - attribute \src "libresoc.v:126037.5-126037.29" + attribute \src "libresoc.v:126113.5-126113.29" switch \initial - attribute \src "libresoc.v:126037.9-126037.17" + attribute \src "libresoc.v:126113.9-126113.17" case 1'1 case end @@ -197111,17 +197174,17 @@ module \dec_a sync always update \reg_a_ok $0\reg_a_ok[0:0] end - attribute \src "libresoc.v:126052.3-126087.6" - process $proc$libresoc.v:126052$4801 + attribute \src "libresoc.v:126128.3-126163.6" + process $proc$libresoc.v:126128$4801 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\fast_a[2:0] $1\fast_a[2:0] assign $0\fast_a_ok[0:0] $1\fast_a_ok[0:0] - attribute \src "libresoc.v:126053.5-126053.29" + attribute \src "libresoc.v:126129.5-126129.29" switch \initial - attribute \src "libresoc.v:126053.9-126053.17" + attribute \src "libresoc.v:126129.9-126129.17" case 1'1 case end @@ -197176,20 +197239,26 @@ module \dec_a update \fast_a $0\fast_a[2:0] update \fast_a_ok $0\fast_a_ok[0:0] end - attribute \src "libresoc.v:126088.3-126098.6" - process $proc$libresoc.v:126088$4802 + attribute \src "libresoc.v:126164.3-126182.6" + process $proc$libresoc.v:126164$4802 assign { } { } assign { } { } assign $0\spr[9:0] $1\spr[9:0] - attribute \src "libresoc.v:126089.5-126089.29" + attribute \src "libresoc.v:126165.5-126165.29" switch \initial - attribute \src "libresoc.v:126089.9-126089.17" + attribute \src "libresoc.v:126165.9-126165.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127" switch \internal_op attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 + assign $1\spr[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001000 + assign $1\spr[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" case 7'0101110 assign { } { } assign $1\spr[9:0] { \SPR [4:0] \SPR [9:5] } @@ -197199,20 +197268,26 @@ module \dec_a sync always update \spr $0\spr[9:0] end - attribute \src "libresoc.v:126099.3-126109.6" - process $proc$libresoc.v:126099$4803 + attribute \src "libresoc.v:126183.3-126201.6" + process $proc$libresoc.v:126183$4803 assign { } { } assign { } { } assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] - attribute \src "libresoc.v:126100.5-126100.29" + attribute \src "libresoc.v:126184.5-126184.29" switch \initial - attribute \src "libresoc.v:126100.9-126100.17" + attribute \src "libresoc.v:126184.9-126184.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127" switch \internal_op attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 + assign $1\sprmap_spr_i[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001000 + assign $1\sprmap_spr_i[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" case 7'0101110 assign { } { } assign $1\sprmap_spr_i[9:0] \spr @@ -197222,23 +197297,31 @@ module \dec_a sync always update \sprmap_spr_i $0\sprmap_spr_i[9:0] end - attribute \src "libresoc.v:126110.3-126121.6" - process $proc$libresoc.v:126110$4804 + attribute \src "libresoc.v:126202.3-126221.6" + process $proc$libresoc.v:126202$4804 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\spr_a[9:0] $1\spr_a[9:0] assign $0\spr_a_ok[0:0] $1\spr_a_ok[0:0] - attribute \src "libresoc.v:126111.5-126111.29" + attribute \src "libresoc.v:126203.5-126203.29" switch \initial - attribute \src "libresoc.v:126111.9-126111.17" + attribute \src "libresoc.v:126203.9-126203.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127" switch \internal_op attribute \src "libresoc.v:0.0-0.0" + case 7'0000111 + assign $1\spr_a[9:0] 10'0000000000 + assign $1\spr_a_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001000 + assign $1\spr_a[9:0] 10'0000000000 + assign $1\spr_a_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 7'0101110 assign { } { } assign { } { } @@ -197251,49 +197334,49 @@ module \dec_a update \spr_a $0\spr_a[9:0] update \spr_a_ok $0\spr_a_ok[0:0] end - connect \$9 $or$libresoc.v:125994$4780_Y - connect \$11 $and$libresoc.v:125995$4781_Y - connect \$13 $or$libresoc.v:125996$4782_Y - connect \$15 $eq$libresoc.v:125997$4783_Y - connect \$17 $eq$libresoc.v:125998$4784_Y - connect \$1 $eq$libresoc.v:125999$4785_Y - connect \$19 $eq$libresoc.v:126000$4786_Y - connect \$21 $ne$libresoc.v:126001$4787_Y - connect \$23 $ne$libresoc.v:126002$4788_Y - connect \$25 $or$libresoc.v:126003$4789_Y - connect \$27 $and$libresoc.v:126004$4790_Y - connect \$29 $or$libresoc.v:126005$4791_Y - connect \$31 $eq$libresoc.v:126006$4792_Y - connect \$33 $not$libresoc.v:126007$4793_Y - connect \$35 $not$libresoc.v:126008$4794_Y - connect \$37 $and$libresoc.v:126009$4795_Y - connect \$3 $eq$libresoc.v:126010$4796_Y - connect \$5 $ne$libresoc.v:126011$4797_Y - connect \$7 $ne$libresoc.v:126012$4798_Y + connect \$9 $or$libresoc.v:126070$4780_Y + connect \$11 $and$libresoc.v:126071$4781_Y + connect \$13 $or$libresoc.v:126072$4782_Y + connect \$15 $eq$libresoc.v:126073$4783_Y + connect \$17 $eq$libresoc.v:126074$4784_Y + connect \$1 $eq$libresoc.v:126075$4785_Y + connect \$19 $eq$libresoc.v:126076$4786_Y + connect \$21 $ne$libresoc.v:126077$4787_Y + connect \$23 $ne$libresoc.v:126078$4788_Y + connect \$25 $or$libresoc.v:126079$4789_Y + connect \$27 $and$libresoc.v:126080$4790_Y + connect \$29 $or$libresoc.v:126081$4791_Y + connect \$31 $eq$libresoc.v:126082$4792_Y + connect \$33 $not$libresoc.v:126083$4793_Y + connect \$35 $not$libresoc.v:126084$4794_Y + connect \$37 $and$libresoc.v:126085$4795_Y + connect \$3 $eq$libresoc.v:126086$4796_Y + connect \$5 $ne$libresoc.v:126087$4797_Y + connect \$7 $ne$libresoc.v:126088$4798_Y connect \rs \RS connect \ra \RA end -attribute \src "libresoc.v:126128.1-126173.10" +attribute \src "libresoc.v:126228.1-126273.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_ai" attribute \generator "nMigen" module \dec_ai - attribute \src "libresoc.v:126162.3-126171.6" + attribute \src "libresoc.v:126262.3-126271.6" wire $0\immz_out[0:0] - attribute \src "libresoc.v:126129.7-126129.20" + attribute \src "libresoc.v:126229.7-126229.20" wire $0\initial[0:0] - attribute \src "libresoc.v:126162.3-126171.6" + attribute \src "libresoc.v:126262.3-126271.6" wire $1\immz_out[0:0] - attribute \src "libresoc.v:126157.17-126157.107" - wire $and$libresoc.v:126157$4806_Y - attribute \src "libresoc.v:126160.17-126160.107" - wire $and$libresoc.v:126160$4809_Y - attribute \src "libresoc.v:126158.17-126158.111" - wire $eq$libresoc.v:126158$4807_Y - attribute \src "libresoc.v:126159.17-126159.108" - wire $eq$libresoc.v:126159$4808_Y - attribute \src "libresoc.v:126161.17-126161.110" - wire $eq$libresoc.v:126161$4810_Y + attribute \src "libresoc.v:126257.17-126257.107" + wire $and$libresoc.v:126257$4806_Y + attribute \src "libresoc.v:126260.17-126260.107" + wire $and$libresoc.v:126260$4809_Y + attribute \src "libresoc.v:126258.17-126258.111" + wire $eq$libresoc.v:126258$4807_Y + attribute \src "libresoc.v:126259.17-126259.108" + wire $eq$libresoc.v:126259$4808_Y + attribute \src "libresoc.v:126261.17-126261.110" + wire $eq$libresoc.v:126261$4810_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" @@ -197308,7 +197391,7 @@ module \dec_ai wire width 5 input 3 \ALU_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" wire output 2 \immz_out - attribute \src "libresoc.v:126129.7-126129.15" + attribute \src "libresoc.v:126229.7-126229.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:172" wire width 5 \ra @@ -197323,7 +197406,7 @@ module \dec_ai attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165" wire input 4 \sv_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" - cell $and $and$libresoc.v:126157$4806 + cell $and $and$libresoc.v:126257$4806 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197331,10 +197414,10 @@ module \dec_ai parameter \Y_WIDTH 1 connect \A \$5 connect \B \$7 - connect \Y $and$libresoc.v:126157$4806_Y + connect \Y $and$libresoc.v:126257$4806_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - cell $and $and$libresoc.v:126160$4809 + cell $and $and$libresoc.v:126260$4809 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197342,10 +197425,10 @@ module \dec_ai parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $and$libresoc.v:126160$4809_Y + connect \Y $and$libresoc.v:126260$4809_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - cell $eq $eq$libresoc.v:126158$4807 + cell $eq $eq$libresoc.v:126258$4807 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -197353,10 +197436,10 @@ module \dec_ai parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:126158$4807_Y + connect \Y $eq$libresoc.v:126258$4807_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - cell $eq $eq$libresoc.v:126159$4808 + cell $eq $eq$libresoc.v:126259$4808 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -197364,10 +197447,10 @@ module \dec_ai parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $eq$libresoc.v:126159$4808_Y + connect \Y $eq$libresoc.v:126259$4808_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" - cell $eq $eq$libresoc.v:126161$4810 + cell $eq $eq$libresoc.v:126261$4810 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197375,24 +197458,24 @@ module \dec_ai parameter \Y_WIDTH 1 connect \A \sv_nz connect \B 1'0 - connect \Y $eq$libresoc.v:126161$4810_Y + connect \Y $eq$libresoc.v:126261$4810_Y end - attribute \src "libresoc.v:126129.7-126129.20" - process $proc$libresoc.v:126129$4812 + attribute \src "libresoc.v:126229.7-126229.20" + process $proc$libresoc.v:126229$4812 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126162.3-126171.6" - process $proc$libresoc.v:126162$4811 + attribute \src "libresoc.v:126262.3-126271.6" + process $proc$libresoc.v:126262$4811 assign { } { } assign { } { } assign $0\immz_out[0:0] $1\immz_out[0:0] - attribute \src "libresoc.v:126163.5-126163.29" + attribute \src "libresoc.v:126263.5-126263.29" switch \initial - attribute \src "libresoc.v:126163.9-126163.17" + attribute \src "libresoc.v:126263.9-126263.17" case 1'1 case end @@ -197408,34 +197491,34 @@ module \dec_ai sync always update \immz_out $0\immz_out[0:0] end - connect \$9 $and$libresoc.v:126157$4806_Y - connect \$1 $eq$libresoc.v:126158$4807_Y - connect \$3 $eq$libresoc.v:126159$4808_Y - connect \$5 $and$libresoc.v:126160$4809_Y - connect \$7 $eq$libresoc.v:126161$4810_Y + connect \$9 $and$libresoc.v:126257$4806_Y + connect \$1 $eq$libresoc.v:126258$4807_Y + connect \$3 $eq$libresoc.v:126259$4808_Y + connect \$5 $and$libresoc.v:126260$4809_Y + connect \$7 $eq$libresoc.v:126261$4810_Y connect \ra \ALU_RA end -attribute \src "libresoc.v:126177.1-126222.10" +attribute \src "libresoc.v:126277.1-126322.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_ai" attribute \generator "nMigen" module \dec_ai$148 - attribute \src "libresoc.v:126211.3-126220.6" + attribute \src "libresoc.v:126311.3-126320.6" wire $0\immz_out[0:0] - attribute \src "libresoc.v:126178.7-126178.20" + attribute \src "libresoc.v:126278.7-126278.20" wire $0\initial[0:0] - attribute \src "libresoc.v:126211.3-126220.6" + attribute \src "libresoc.v:126311.3-126320.6" wire $1\immz_out[0:0] - attribute \src "libresoc.v:126206.17-126206.107" - wire $and$libresoc.v:126206$4813_Y - attribute \src "libresoc.v:126209.17-126209.107" - wire $and$libresoc.v:126209$4816_Y - attribute \src "libresoc.v:126207.17-126207.111" - wire $eq$libresoc.v:126207$4814_Y - attribute \src "libresoc.v:126208.17-126208.108" - wire $eq$libresoc.v:126208$4815_Y - attribute \src "libresoc.v:126210.17-126210.110" - wire $eq$libresoc.v:126210$4817_Y + attribute \src "libresoc.v:126306.17-126306.107" + wire $and$libresoc.v:126306$4813_Y + attribute \src "libresoc.v:126309.17-126309.107" + wire $and$libresoc.v:126309$4816_Y + attribute \src "libresoc.v:126307.17-126307.111" + wire $eq$libresoc.v:126307$4814_Y + attribute \src "libresoc.v:126308.17-126308.108" + wire $eq$libresoc.v:126308$4815_Y + attribute \src "libresoc.v:126310.17-126310.110" + wire $eq$libresoc.v:126310$4817_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" @@ -197450,7 +197533,7 @@ module \dec_ai$148 wire width 5 input 3 \LOGICAL_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" wire output 2 \immz_out - attribute \src "libresoc.v:126178.7-126178.15" + attribute \src "libresoc.v:126278.7-126278.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:172" wire width 5 \ra @@ -197465,7 +197548,7 @@ module \dec_ai$148 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165" wire input 4 \sv_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" - cell $and $and$libresoc.v:126206$4813 + cell $and $and$libresoc.v:126306$4813 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197473,10 +197556,10 @@ module \dec_ai$148 parameter \Y_WIDTH 1 connect \A \$5 connect \B \$7 - connect \Y $and$libresoc.v:126206$4813_Y + connect \Y $and$libresoc.v:126306$4813_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - cell $and $and$libresoc.v:126209$4816 + cell $and $and$libresoc.v:126309$4816 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197484,10 +197567,10 @@ module \dec_ai$148 parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $and$libresoc.v:126209$4816_Y + connect \Y $and$libresoc.v:126309$4816_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - cell $eq $eq$libresoc.v:126207$4814 + cell $eq $eq$libresoc.v:126307$4814 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -197495,10 +197578,10 @@ module \dec_ai$148 parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:126207$4814_Y + connect \Y $eq$libresoc.v:126307$4814_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - cell $eq $eq$libresoc.v:126208$4815 + cell $eq $eq$libresoc.v:126308$4815 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -197506,10 +197589,10 @@ module \dec_ai$148 parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $eq$libresoc.v:126208$4815_Y + connect \Y $eq$libresoc.v:126308$4815_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" - cell $eq $eq$libresoc.v:126210$4817 + cell $eq $eq$libresoc.v:126310$4817 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197517,24 +197600,24 @@ module \dec_ai$148 parameter \Y_WIDTH 1 connect \A \sv_nz connect \B 1'0 - connect \Y $eq$libresoc.v:126210$4817_Y + connect \Y $eq$libresoc.v:126310$4817_Y end - attribute \src "libresoc.v:126178.7-126178.20" - process $proc$libresoc.v:126178$4819 + attribute \src "libresoc.v:126278.7-126278.20" + process $proc$libresoc.v:126278$4819 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126211.3-126220.6" - process $proc$libresoc.v:126211$4818 + attribute \src "libresoc.v:126311.3-126320.6" + process $proc$libresoc.v:126311$4818 assign { } { } assign { } { } assign $0\immz_out[0:0] $1\immz_out[0:0] - attribute \src "libresoc.v:126212.5-126212.29" + attribute \src "libresoc.v:126312.5-126312.29" switch \initial - attribute \src "libresoc.v:126212.9-126212.17" + attribute \src "libresoc.v:126312.9-126312.17" case 1'1 case end @@ -197550,34 +197633,34 @@ module \dec_ai$148 sync always update \immz_out $0\immz_out[0:0] end - connect \$9 $and$libresoc.v:126206$4813_Y - connect \$1 $eq$libresoc.v:126207$4814_Y - connect \$3 $eq$libresoc.v:126208$4815_Y - connect \$5 $and$libresoc.v:126209$4816_Y - connect \$7 $eq$libresoc.v:126210$4817_Y + connect \$9 $and$libresoc.v:126306$4813_Y + connect \$1 $eq$libresoc.v:126307$4814_Y + connect \$3 $eq$libresoc.v:126308$4815_Y + connect \$5 $and$libresoc.v:126309$4816_Y + connect \$7 $eq$libresoc.v:126310$4817_Y connect \ra \LOGICAL_RA end -attribute \src "libresoc.v:126226.1-126271.10" +attribute \src "libresoc.v:126326.1-126371.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_ai" attribute \generator "nMigen" module \dec_ai$156 - attribute \src "libresoc.v:126260.3-126269.6" + attribute \src "libresoc.v:126360.3-126369.6" wire $0\immz_out[0:0] - attribute \src "libresoc.v:126227.7-126227.20" + attribute \src "libresoc.v:126327.7-126327.20" wire $0\initial[0:0] - attribute \src "libresoc.v:126260.3-126269.6" + attribute \src "libresoc.v:126360.3-126369.6" wire $1\immz_out[0:0] - attribute \src "libresoc.v:126255.17-126255.107" - wire $and$libresoc.v:126255$4820_Y - attribute \src "libresoc.v:126258.17-126258.107" - wire $and$libresoc.v:126258$4823_Y - attribute \src "libresoc.v:126256.17-126256.111" - wire $eq$libresoc.v:126256$4821_Y - attribute \src "libresoc.v:126257.17-126257.108" - wire $eq$libresoc.v:126257$4822_Y - attribute \src "libresoc.v:126259.17-126259.110" - wire $eq$libresoc.v:126259$4824_Y + attribute \src "libresoc.v:126355.17-126355.107" + wire $and$libresoc.v:126355$4820_Y + attribute \src "libresoc.v:126358.17-126358.107" + wire $and$libresoc.v:126358$4823_Y + attribute \src "libresoc.v:126356.17-126356.111" + wire $eq$libresoc.v:126356$4821_Y + attribute \src "libresoc.v:126357.17-126357.108" + wire $eq$libresoc.v:126357$4822_Y + attribute \src "libresoc.v:126359.17-126359.110" + wire $eq$libresoc.v:126359$4824_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" @@ -197592,7 +197675,7 @@ module \dec_ai$156 wire width 5 input 3 \DIV_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" wire output 2 \immz_out - attribute \src "libresoc.v:126227.7-126227.15" + attribute \src "libresoc.v:126327.7-126327.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:172" wire width 5 \ra @@ -197607,7 +197690,7 @@ module \dec_ai$156 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165" wire input 4 \sv_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" - cell $and $and$libresoc.v:126255$4820 + cell $and $and$libresoc.v:126355$4820 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197615,10 +197698,10 @@ module \dec_ai$156 parameter \Y_WIDTH 1 connect \A \$5 connect \B \$7 - connect \Y $and$libresoc.v:126255$4820_Y + connect \Y $and$libresoc.v:126355$4820_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - cell $and $and$libresoc.v:126258$4823 + cell $and $and$libresoc.v:126358$4823 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197626,10 +197709,10 @@ module \dec_ai$156 parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $and$libresoc.v:126258$4823_Y + connect \Y $and$libresoc.v:126358$4823_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - cell $eq $eq$libresoc.v:126256$4821 + cell $eq $eq$libresoc.v:126356$4821 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -197637,10 +197720,10 @@ module \dec_ai$156 parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:126256$4821_Y + connect \Y $eq$libresoc.v:126356$4821_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - cell $eq $eq$libresoc.v:126257$4822 + cell $eq $eq$libresoc.v:126357$4822 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -197648,10 +197731,10 @@ module \dec_ai$156 parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $eq$libresoc.v:126257$4822_Y + connect \Y $eq$libresoc.v:126357$4822_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" - cell $eq $eq$libresoc.v:126259$4824 + cell $eq $eq$libresoc.v:126359$4824 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197659,24 +197742,24 @@ module \dec_ai$156 parameter \Y_WIDTH 1 connect \A \sv_nz connect \B 1'0 - connect \Y $eq$libresoc.v:126259$4824_Y + connect \Y $eq$libresoc.v:126359$4824_Y end - attribute \src "libresoc.v:126227.7-126227.20" - process $proc$libresoc.v:126227$4826 + attribute \src "libresoc.v:126327.7-126327.20" + process $proc$libresoc.v:126327$4826 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126260.3-126269.6" - process $proc$libresoc.v:126260$4825 + attribute \src "libresoc.v:126360.3-126369.6" + process $proc$libresoc.v:126360$4825 assign { } { } assign { } { } assign $0\immz_out[0:0] $1\immz_out[0:0] - attribute \src "libresoc.v:126261.5-126261.29" + attribute \src "libresoc.v:126361.5-126361.29" switch \initial - attribute \src "libresoc.v:126261.9-126261.17" + attribute \src "libresoc.v:126361.9-126361.17" case 1'1 case end @@ -197692,34 +197775,34 @@ module \dec_ai$156 sync always update \immz_out $0\immz_out[0:0] end - connect \$9 $and$libresoc.v:126255$4820_Y - connect \$1 $eq$libresoc.v:126256$4821_Y - connect \$3 $eq$libresoc.v:126257$4822_Y - connect \$5 $and$libresoc.v:126258$4823_Y - connect \$7 $eq$libresoc.v:126259$4824_Y + connect \$9 $and$libresoc.v:126355$4820_Y + connect \$1 $eq$libresoc.v:126356$4821_Y + connect \$3 $eq$libresoc.v:126357$4822_Y + connect \$5 $and$libresoc.v:126358$4823_Y + connect \$7 $eq$libresoc.v:126359$4824_Y connect \ra \DIV_RA end -attribute \src "libresoc.v:126275.1-126320.10" +attribute \src "libresoc.v:126375.1-126420.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_ai" attribute \generator "nMigen" module \dec_ai$169 - attribute \src "libresoc.v:126309.3-126318.6" + attribute \src "libresoc.v:126409.3-126418.6" wire $0\immz_out[0:0] - attribute \src "libresoc.v:126276.7-126276.20" + attribute \src "libresoc.v:126376.7-126376.20" wire $0\initial[0:0] - attribute \src "libresoc.v:126309.3-126318.6" + attribute \src "libresoc.v:126409.3-126418.6" wire $1\immz_out[0:0] - attribute \src "libresoc.v:126304.17-126304.107" - wire $and$libresoc.v:126304$4827_Y - attribute \src "libresoc.v:126307.17-126307.107" - wire $and$libresoc.v:126307$4830_Y - attribute \src "libresoc.v:126305.17-126305.111" - wire $eq$libresoc.v:126305$4828_Y - attribute \src "libresoc.v:126306.17-126306.108" - wire $eq$libresoc.v:126306$4829_Y - attribute \src "libresoc.v:126308.17-126308.110" - wire $eq$libresoc.v:126308$4831_Y + attribute \src "libresoc.v:126404.17-126404.107" + wire $and$libresoc.v:126404$4827_Y + attribute \src "libresoc.v:126407.17-126407.107" + wire $and$libresoc.v:126407$4830_Y + attribute \src "libresoc.v:126405.17-126405.111" + wire $eq$libresoc.v:126405$4828_Y + attribute \src "libresoc.v:126406.17-126406.108" + wire $eq$libresoc.v:126406$4829_Y + attribute \src "libresoc.v:126408.17-126408.110" + wire $eq$libresoc.v:126408$4831_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" @@ -197734,7 +197817,7 @@ module \dec_ai$169 wire width 5 input 3 \LDST_RA attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:164" wire output 2 \immz_out - attribute \src "libresoc.v:126276.7-126276.15" + attribute \src "libresoc.v:126376.7-126376.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:172" wire width 5 \ra @@ -197749,7 +197832,7 @@ module \dec_ai$169 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:165" wire input 4 \sv_nz attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" - cell $and $and$libresoc.v:126304$4827 + cell $and $and$libresoc.v:126404$4827 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197757,10 +197840,10 @@ module \dec_ai$169 parameter \Y_WIDTH 1 connect \A \$5 connect \B \$7 - connect \Y $and$libresoc.v:126304$4827_Y + connect \Y $and$libresoc.v:126404$4827_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - cell $and $and$libresoc.v:126307$4830 + cell $and $and$libresoc.v:126407$4830 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197768,10 +197851,10 @@ module \dec_ai$169 parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $and$libresoc.v:126307$4830_Y + connect \Y $and$libresoc.v:126407$4830_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - cell $eq $eq$libresoc.v:126305$4828 + cell $eq $eq$libresoc.v:126405$4828 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -197779,10 +197862,10 @@ module \dec_ai$169 parameter \Y_WIDTH 1 connect \A \sel_in connect \B 3'010 - connect \Y $eq$libresoc.v:126305$4828_Y + connect \Y $eq$libresoc.v:126405$4828_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" - cell $eq $eq$libresoc.v:126306$4829 + cell $eq $eq$libresoc.v:126406$4829 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -197790,10 +197873,10 @@ module \dec_ai$169 parameter \Y_WIDTH 1 connect \A \ra connect \B 5'00000 - connect \Y $eq$libresoc.v:126306$4829_Y + connect \Y $eq$libresoc.v:126406$4829_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" - cell $eq $eq$libresoc.v:126308$4831 + cell $eq $eq$libresoc.v:126408$4831 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -197801,24 +197884,24 @@ module \dec_ai$169 parameter \Y_WIDTH 1 connect \A \sv_nz connect \B 1'0 - connect \Y $eq$libresoc.v:126308$4831_Y + connect \Y $eq$libresoc.v:126408$4831_Y end - attribute \src "libresoc.v:126276.7-126276.20" - process $proc$libresoc.v:126276$4833 + attribute \src "libresoc.v:126376.7-126376.20" + process $proc$libresoc.v:126376$4833 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126309.3-126318.6" - process $proc$libresoc.v:126309$4832 + attribute \src "libresoc.v:126409.3-126418.6" + process $proc$libresoc.v:126409$4832 assign { } { } assign { } { } assign $0\immz_out[0:0] $1\immz_out[0:0] - attribute \src "libresoc.v:126310.5-126310.29" + attribute \src "libresoc.v:126410.5-126410.29" switch \initial - attribute \src "libresoc.v:126310.9-126310.17" + attribute \src "libresoc.v:126410.9-126410.17" case 1'1 case end @@ -197834,56 +197917,56 @@ module \dec_ai$169 sync always update \immz_out $0\immz_out[0:0] end - connect \$9 $and$libresoc.v:126304$4827_Y - connect \$1 $eq$libresoc.v:126305$4828_Y - connect \$3 $eq$libresoc.v:126306$4829_Y - connect \$5 $and$libresoc.v:126307$4830_Y - connect \$7 $eq$libresoc.v:126308$4831_Y + connect \$9 $and$libresoc.v:126404$4827_Y + connect \$1 $eq$libresoc.v:126405$4828_Y + connect \$3 $eq$libresoc.v:126406$4829_Y + connect \$5 $and$libresoc.v:126407$4830_Y + connect \$7 $eq$libresoc.v:126408$4831_Y connect \ra \LDST_RA end -attribute \src "libresoc.v:126324.1-126522.10" +attribute \src "libresoc.v:126424.1-126622.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_b" attribute \generator "nMigen" module \dec_b - attribute \src "libresoc.v:126486.3-126503.6" + attribute \src "libresoc.v:126586.3-126603.6" wire width 3 $0\fast_b[2:0] - attribute \src "libresoc.v:126504.3-126521.6" + attribute \src "libresoc.v:126604.3-126621.6" wire $0\fast_b_ok[0:0] - attribute \src "libresoc.v:126325.7-126325.20" + attribute \src "libresoc.v:126425.7-126425.20" wire $0\initial[0:0] - attribute \src "libresoc.v:126456.3-126470.6" + attribute \src "libresoc.v:126556.3-126570.6" wire width 7 $0\reg_b[6:0] - attribute \src "libresoc.v:126471.3-126485.6" + attribute \src "libresoc.v:126571.3-126585.6" wire $0\reg_b_ok[0:0] - attribute \src "libresoc.v:126486.3-126503.6" + attribute \src "libresoc.v:126586.3-126603.6" wire width 3 $1\fast_b[2:0] - attribute \src "libresoc.v:126504.3-126521.6" + attribute \src "libresoc.v:126604.3-126621.6" wire $1\fast_b_ok[0:0] - attribute \src "libresoc.v:126456.3-126470.6" + attribute \src "libresoc.v:126556.3-126570.6" wire width 7 $1\reg_b[6:0] - attribute \src "libresoc.v:126471.3-126485.6" + attribute \src "libresoc.v:126571.3-126585.6" wire $1\reg_b_ok[0:0] - attribute \src "libresoc.v:126486.3-126503.6" + attribute \src "libresoc.v:126586.3-126603.6" wire width 3 $2\fast_b[2:0] - attribute \src "libresoc.v:126504.3-126521.6" + attribute \src "libresoc.v:126604.3-126621.6" wire $2\fast_b_ok[0:0] - attribute \src "libresoc.v:126450.17-126450.117" - wire $eq$libresoc.v:126450$4834_Y - attribute \src "libresoc.v:126454.17-126454.117" - wire $eq$libresoc.v:126454$4840_Y - attribute \src "libresoc.v:126452.17-126452.100" - wire width 7 $extend$libresoc.v:126452$4836_Y - attribute \src "libresoc.v:126453.17-126453.100" - wire width 7 $extend$libresoc.v:126453$4838_Y - attribute \src "libresoc.v:126451.18-126451.108" - wire $not$libresoc.v:126451$4835_Y - attribute \src "libresoc.v:126455.17-126455.107" - wire $not$libresoc.v:126455$4841_Y - attribute \src "libresoc.v:126452.17-126452.100" - wire width 7 $pos$libresoc.v:126452$4837_Y - attribute \src "libresoc.v:126453.17-126453.100" - wire width 7 $pos$libresoc.v:126453$4839_Y + attribute \src "libresoc.v:126550.17-126550.117" + wire $eq$libresoc.v:126550$4834_Y + attribute \src "libresoc.v:126554.17-126554.117" + wire $eq$libresoc.v:126554$4840_Y + attribute \src "libresoc.v:126552.17-126552.100" + wire width 7 $extend$libresoc.v:126552$4836_Y + attribute \src "libresoc.v:126553.17-126553.100" + wire width 7 $extend$libresoc.v:126553$4838_Y + attribute \src "libresoc.v:126551.18-126551.108" + wire $not$libresoc.v:126551$4835_Y + attribute \src "libresoc.v:126555.17-126555.107" + wire $not$libresoc.v:126555$4841_Y + attribute \src "libresoc.v:126552.17-126552.100" + wire width 7 $pos$libresoc.v:126552$4837_Y + attribute \src "libresoc.v:126553.17-126553.100" + wire width 7 $pos$libresoc.v:126553$4839_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 7 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:221" @@ -197906,7 +197989,7 @@ module \dec_b wire width 3 output 4 \fast_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 5 \fast_b_ok - attribute \src "libresoc.v:126325.7-126325.15" + attribute \src "libresoc.v:126425.7-126425.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -198007,7 +198090,7 @@ module \dec_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:193" wire width 4 input 1 \sel_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218" - cell $eq $eq$libresoc.v:126450$4834 + cell $eq $eq$libresoc.v:126550$4834 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -198015,10 +198098,10 @@ module \dec_b parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0001000 - connect \Y $eq$libresoc.v:126450$4834_Y + connect \Y $eq$libresoc.v:126550$4834_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218" - cell $eq $eq$libresoc.v:126454$4840 + cell $eq $eq$libresoc.v:126554$4840 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -198026,72 +198109,72 @@ module \dec_b parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0001000 - connect \Y $eq$libresoc.v:126454$4840_Y + connect \Y $eq$libresoc.v:126554$4840_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:126452$4836 + cell $pos $extend$libresoc.v:126552$4836 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \RB - connect \Y $extend$libresoc.v:126452$4836_Y + connect \Y $extend$libresoc.v:126552$4836_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:126453$4838 + cell $pos $extend$libresoc.v:126553$4838 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \RS - connect \Y $extend$libresoc.v:126453$4838_Y + connect \Y $extend$libresoc.v:126553$4838_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:221" - cell $not $not$libresoc.v:126451$4835 + cell $not $not$libresoc.v:126551$4835 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \XL_XO [9] - connect \Y $not$libresoc.v:126451$4835_Y + connect \Y $not$libresoc.v:126551$4835_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:221" - cell $not $not$libresoc.v:126455$4841 + cell $not $not$libresoc.v:126555$4841 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \XL_XO [9] - connect \Y $not$libresoc.v:126455$4841_Y + connect \Y $not$libresoc.v:126555$4841_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:126452$4837 + cell $pos $pos$libresoc.v:126552$4837 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:126452$4836_Y - connect \Y $pos$libresoc.v:126452$4837_Y + connect \A $extend$libresoc.v:126552$4836_Y + connect \Y $pos$libresoc.v:126552$4837_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:126453$4839 + cell $pos $pos$libresoc.v:126553$4839 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:126453$4838_Y - connect \Y $pos$libresoc.v:126453$4839_Y + connect \A $extend$libresoc.v:126553$4838_Y + connect \Y $pos$libresoc.v:126553$4839_Y end - attribute \src "libresoc.v:126325.7-126325.20" - process $proc$libresoc.v:126325$4846 + attribute \src "libresoc.v:126425.7-126425.20" + process $proc$libresoc.v:126425$4846 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126456.3-126470.6" - process $proc$libresoc.v:126456$4842 + attribute \src "libresoc.v:126556.3-126570.6" + process $proc$libresoc.v:126556$4842 assign { } { } assign { } { } assign $0\reg_b[6:0] $1\reg_b[6:0] - attribute \src "libresoc.v:126457.5-126457.29" + attribute \src "libresoc.v:126557.5-126557.29" switch \initial - attribute \src "libresoc.v:126457.9-126457.17" + attribute \src "libresoc.v:126557.9-126557.17" case 1'1 case end @@ -198111,14 +198194,14 @@ module \dec_b sync always update \reg_b $0\reg_b[6:0] end - attribute \src "libresoc.v:126471.3-126485.6" - process $proc$libresoc.v:126471$4843 + attribute \src "libresoc.v:126571.3-126585.6" + process $proc$libresoc.v:126571$4843 assign { } { } assign { } { } assign $0\reg_b_ok[0:0] $1\reg_b_ok[0:0] - attribute \src "libresoc.v:126472.5-126472.29" + attribute \src "libresoc.v:126572.5-126572.29" switch \initial - attribute \src "libresoc.v:126472.9-126472.17" + attribute \src "libresoc.v:126572.9-126572.17" case 1'1 case end @@ -198138,14 +198221,14 @@ module \dec_b sync always update \reg_b_ok $0\reg_b_ok[0:0] end - attribute \src "libresoc.v:126486.3-126503.6" - process $proc$libresoc.v:126486$4844 + attribute \src "libresoc.v:126586.3-126603.6" + process $proc$libresoc.v:126586$4844 assign { } { } assign { } { } assign $0\fast_b[2:0] $1\fast_b[2:0] - attribute \src "libresoc.v:126487.5-126487.29" + attribute \src "libresoc.v:126587.5-126587.29" switch \initial - attribute \src "libresoc.v:126487.9-126487.17" + attribute \src "libresoc.v:126587.9-126587.17" case 1'1 case end @@ -198174,14 +198257,14 @@ module \dec_b sync always update \fast_b $0\fast_b[2:0] end - attribute \src "libresoc.v:126504.3-126521.6" - process $proc$libresoc.v:126504$4845 + attribute \src "libresoc.v:126604.3-126621.6" + process $proc$libresoc.v:126604$4845 assign { } { } assign { } { } assign $0\fast_b_ok[0:0] $1\fast_b_ok[0:0] - attribute \src "libresoc.v:126505.5-126505.29" + attribute \src "libresoc.v:126605.5-126605.29" switch \initial - attribute \src "libresoc.v:126505.9-126505.17" + attribute \src "libresoc.v:126605.9-126605.17" case 1'1 case end @@ -198210,78 +198293,78 @@ module \dec_b sync always update \fast_b_ok $0\fast_b_ok[0:0] end - connect \$9 $eq$libresoc.v:126450$4834_Y - connect \$11 $not$libresoc.v:126451$4835_Y - connect \$1 $pos$libresoc.v:126452$4837_Y - connect \$3 $pos$libresoc.v:126453$4839_Y - connect \$5 $eq$libresoc.v:126454$4840_Y - connect \$7 $not$libresoc.v:126455$4841_Y + connect \$9 $eq$libresoc.v:126550$4834_Y + connect \$11 $not$libresoc.v:126551$4835_Y + connect \$1 $pos$libresoc.v:126552$4837_Y + connect \$3 $pos$libresoc.v:126553$4839_Y + connect \$5 $eq$libresoc.v:126554$4840_Y + connect \$7 $not$libresoc.v:126555$4841_Y end -attribute \src "libresoc.v:126526.1-126779.10" +attribute \src "libresoc.v:126626.1-126963.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_bi" attribute \generator "nMigen" module \dec_bi - attribute \src "libresoc.v:126753.3-126763.6" + attribute \src "libresoc.v:126893.3-126923.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:126764.3-126774.6" + attribute \src "libresoc.v:126924.3-126958.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:126615.3-126661.6" + attribute \src "libresoc.v:126715.3-126761.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:126662.3-126708.6" + attribute \src "libresoc.v:126762.3-126808.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:126527.7-126527.20" + attribute \src "libresoc.v:126627.7-126627.20" wire $0\initial[0:0] - attribute \src "libresoc.v:126742.3-126752.6" + attribute \src "libresoc.v:126866.3-126892.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:126709.3-126719.6" + attribute \src "libresoc.v:126809.3-126823.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:126720.3-126730.6" + attribute \src "libresoc.v:126824.3-126842.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:126731.3-126741.6" + attribute \src "libresoc.v:126843.3-126865.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:126753.3-126763.6" + attribute \src "libresoc.v:126893.3-126923.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:126764.3-126774.6" + attribute \src "libresoc.v:126924.3-126958.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:126615.3-126661.6" + attribute \src "libresoc.v:126715.3-126761.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:126662.3-126708.6" + attribute \src "libresoc.v:126762.3-126808.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:126742.3-126752.6" + attribute \src "libresoc.v:126866.3-126892.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:126709.3-126719.6" + attribute \src "libresoc.v:126809.3-126823.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:126720.3-126730.6" + attribute \src "libresoc.v:126824.3-126842.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:126731.3-126741.6" + attribute \src "libresoc.v:126843.3-126865.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:126605.17-126605.104" - wire width 64 $extend$libresoc.v:126605$4847_Y - attribute \src "libresoc.v:126606.18-126606.107" - wire width 64 $extend$libresoc.v:126606$4849_Y - attribute \src "libresoc.v:126609.17-126609.104" - wire width 64 $extend$libresoc.v:126609$4853_Y - attribute \src "libresoc.v:126613.17-126613.102" - wire width 64 $extend$libresoc.v:126613$4858_Y - attribute \src "libresoc.v:126605.17-126605.104" - wire width 64 $pos$libresoc.v:126605$4848_Y - attribute \src "libresoc.v:126606.18-126606.107" - wire width 64 $pos$libresoc.v:126606$4850_Y - attribute \src "libresoc.v:126609.17-126609.104" - wire width 64 $pos$libresoc.v:126609$4854_Y - attribute \src "libresoc.v:126613.17-126613.102" - wire width 64 $pos$libresoc.v:126613$4859_Y - attribute \src "libresoc.v:126607.18-126607.114" - wire width 47 $sshl$libresoc.v:126607$4851_Y - attribute \src "libresoc.v:126608.18-126608.113" - wire width 27 $sshl$libresoc.v:126608$4852_Y - attribute \src "libresoc.v:126610.18-126610.113" - wire width 17 $sshl$libresoc.v:126610$4855_Y - attribute \src "libresoc.v:126611.18-126611.113" - wire width 17 $sshl$libresoc.v:126611$4856_Y - attribute \src "libresoc.v:126612.17-126612.109" - wire width 47 $sshl$libresoc.v:126612$4857_Y + attribute \src "libresoc.v:126705.17-126705.104" + wire width 64 $extend$libresoc.v:126705$4847_Y + attribute \src "libresoc.v:126706.18-126706.107" + wire width 64 $extend$libresoc.v:126706$4849_Y + attribute \src "libresoc.v:126709.17-126709.104" + wire width 64 $extend$libresoc.v:126709$4853_Y + attribute \src "libresoc.v:126713.17-126713.102" + wire width 64 $extend$libresoc.v:126713$4858_Y + attribute \src "libresoc.v:126705.17-126705.104" + wire width 64 $pos$libresoc.v:126705$4848_Y + attribute \src "libresoc.v:126706.18-126706.107" + wire width 64 $pos$libresoc.v:126706$4850_Y + attribute \src "libresoc.v:126709.17-126709.104" + wire width 64 $pos$libresoc.v:126709$4854_Y + attribute \src "libresoc.v:126713.17-126713.102" + wire width 64 $pos$libresoc.v:126713$4859_Y + attribute \src "libresoc.v:126707.18-126707.114" + wire width 47 $sshl$libresoc.v:126707$4851_Y + attribute \src "libresoc.v:126708.18-126708.113" + wire width 27 $sshl$libresoc.v:126708$4852_Y + attribute \src "libresoc.v:126710.18-126710.113" + wire width 17 $sshl$libresoc.v:126710$4855_Y + attribute \src "libresoc.v:126711.18-126711.113" + wire width 17 $sshl$libresoc.v:126711$4856_Y + attribute \src "libresoc.v:126712.17-126712.109" + wire width 47 $sshl$libresoc.v:126712$4857_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" @@ -198332,7 +198415,7 @@ module \dec_bi wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \imm_b_ok - attribute \src "libresoc.v:126527.7-126527.15" + attribute \src "libresoc.v:126627.7-126627.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" wire width 26 \li @@ -198360,71 +198443,71 @@ module \dec_bi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" wire width 16 \ui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:126605$4847 + cell $pos $extend$libresoc.v:126705$4847 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \ALU_sh - connect \Y $extend$libresoc.v:126605$4847_Y + connect \Y $extend$libresoc.v:126705$4847_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:126606$4849 + cell $pos $extend$libresoc.v:126706$4849 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \ALU_SH32 - connect \Y $extend$libresoc.v:126606$4849_Y + connect \Y $extend$libresoc.v:126706$4849_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:126609$4853 + cell $pos $extend$libresoc.v:126709$4853 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \ALU_UI - connect \Y $extend$libresoc.v:126609$4853_Y + connect \Y $extend$libresoc.v:126709$4853_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - cell $pos $extend$libresoc.v:126613$4858 + cell $pos $extend$libresoc.v:126713$4858 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:126613$4858_Y + connect \Y $extend$libresoc.v:126713$4858_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:126605$4848 + cell $pos $pos$libresoc.v:126705$4848 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126605$4847_Y - connect \Y $pos$libresoc.v:126605$4848_Y + connect \A $extend$libresoc.v:126705$4847_Y + connect \Y $pos$libresoc.v:126705$4848_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:126606$4850 + cell $pos $pos$libresoc.v:126706$4850 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126606$4849_Y - connect \Y $pos$libresoc.v:126606$4850_Y + connect \A $extend$libresoc.v:126706$4849_Y + connect \Y $pos$libresoc.v:126706$4850_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:126609$4854 + cell $pos $pos$libresoc.v:126709$4854 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126609$4853_Y - connect \Y $pos$libresoc.v:126609$4854_Y + connect \A $extend$libresoc.v:126709$4853_Y + connect \Y $pos$libresoc.v:126709$4854_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - cell $pos $pos$libresoc.v:126613$4859 + cell $pos $pos$libresoc.v:126713$4859 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126613$4858_Y - connect \Y $pos$libresoc.v:126613$4859_Y + connect \A $extend$libresoc.v:126713$4858_Y + connect \Y $pos$libresoc.v:126713$4859_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - cell $sshl $sshl$libresoc.v:126607$4851 + cell $sshl $sshl$libresoc.v:126707$4851 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -198432,10 +198515,10 @@ module \dec_bi parameter \Y_WIDTH 47 connect \A \ALU_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:126607$4851_Y + connect \Y $sshl$libresoc.v:126707$4851_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" - cell $sshl $sshl$libresoc.v:126608$4852 + cell $sshl $sshl$libresoc.v:126708$4852 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -198443,10 +198526,10 @@ module \dec_bi parameter \Y_WIDTH 27 connect \A \ALU_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:126608$4852_Y + connect \Y $sshl$libresoc.v:126708$4852_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" - cell $sshl $sshl$libresoc.v:126610$4855 + cell $sshl $sshl$libresoc.v:126710$4855 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -198454,10 +198537,10 @@ module \dec_bi parameter \Y_WIDTH 17 connect \A \ALU_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:126610$4855_Y + connect \Y $sshl$libresoc.v:126710$4855_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" - cell $sshl $sshl$libresoc.v:126611$4856 + cell $sshl $sshl$libresoc.v:126711$4856 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -198465,10 +198548,10 @@ module \dec_bi parameter \Y_WIDTH 17 connect \A \ALU_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:126611$4856_Y + connect \Y $sshl$libresoc.v:126711$4856_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - cell $sshl $sshl$libresoc.v:126612$4857 + cell $sshl $sshl$libresoc.v:126712$4857 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -198476,24 +198559,24 @@ module \dec_bi parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:126612$4857_Y + connect \Y $sshl$libresoc.v:126712$4857_Y end - attribute \src "libresoc.v:126527.7-126527.20" - process $proc$libresoc.v:126527$4868 + attribute \src "libresoc.v:126627.7-126627.20" + process $proc$libresoc.v:126627$4868 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126615.3-126661.6" - process $proc$libresoc.v:126615$4860 + attribute \src "libresoc.v:126715.3-126761.6" + process $proc$libresoc.v:126715$4860 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:126616.5-126616.29" + attribute \src "libresoc.v:126716.5-126716.29" switch \initial - attribute \src "libresoc.v:126616.9-126616.17" + attribute \src "libresoc.v:126716.9-126716.17" case 1'1 case end @@ -198545,14 +198628,14 @@ module \dec_bi sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:126662.3-126708.6" - process $proc$libresoc.v:126662$4861 + attribute \src "libresoc.v:126762.3-126808.6" + process $proc$libresoc.v:126762$4861 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:126663.5-126663.29" + attribute \src "libresoc.v:126763.5-126763.29" switch \initial - attribute \src "libresoc.v:126663.9-126663.17" + attribute \src "libresoc.v:126763.9-126763.17" case 1'1 case end @@ -198604,20 +198687,23 @@ module \dec_bi sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:126709.3-126719.6" - process $proc$libresoc.v:126709$4862 + attribute \src "libresoc.v:126809.3-126823.6" + process $proc$libresoc.v:126809$4862 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:126710.5-126710.29" + attribute \src "libresoc.v:126810.5-126810.29" switch \initial - attribute \src "libresoc.v:126710.9-126710.17" + attribute \src "libresoc.v:126810.9-126810.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\si[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\si[15:0] \ALU_SI @@ -198627,20 +198713,26 @@ module \dec_bi sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:126720.3-126730.6" - process $proc$libresoc.v:126720$4863 + attribute \src "libresoc.v:126824.3-126842.6" + process $proc$libresoc.v:126824$4863 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:126721.5-126721.29" + attribute \src "libresoc.v:126825.5-126825.29" switch \initial - attribute \src "libresoc.v:126721.9-126721.17" + attribute \src "libresoc.v:126825.9-126825.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\si_hi[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\si_hi[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\si_hi[31:0] \$13 [31:0] @@ -198650,20 +198742,29 @@ module \dec_bi sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:126731.3-126741.6" - process $proc$libresoc.v:126731$4864 + attribute \src "libresoc.v:126843.3-126865.6" + process $proc$libresoc.v:126843$4864 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:126732.5-126732.29" + attribute \src "libresoc.v:126844.5-126844.29" switch \initial - attribute \src "libresoc.v:126732.9-126732.17" + attribute \src "libresoc.v:126844.9-126844.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\ui[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\ui[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\ui[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\ui[15:0] \ALU_UI @@ -198673,20 +198774,32 @@ module \dec_bi sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:126742.3-126752.6" - process $proc$libresoc.v:126742$4865 + attribute \src "libresoc.v:126866.3-126892.6" + process $proc$libresoc.v:126866$4865 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:126743.5-126743.29" + attribute \src "libresoc.v:126867.5-126867.29" switch \initial - attribute \src "libresoc.v:126743.9-126743.17" + attribute \src "libresoc.v:126867.9-126867.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\li[25:0] \$16 [25:0] @@ -198696,20 +198809,35 @@ module \dec_bi sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:126753.3-126763.6" - process $proc$libresoc.v:126753$4866 + attribute \src "libresoc.v:126893.3-126923.6" + process $proc$libresoc.v:126893$4866 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:126754.5-126754.29" + attribute \src "libresoc.v:126894.5-126894.29" switch \initial - attribute \src "libresoc.v:126754.9-126754.17" + attribute \src "libresoc.v:126894.9-126894.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\bd[15:0] \$19 [15:0] @@ -198719,20 +198847,38 @@ module \dec_bi sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:126764.3-126774.6" - process $proc$libresoc.v:126764$4867 + attribute \src "libresoc.v:126924.3-126958.6" + process $proc$libresoc.v:126924$4867 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:126765.5-126765.29" + attribute \src "libresoc.v:126925.5-126925.29" switch \initial - attribute \src "libresoc.v:126765.9-126765.17" + attribute \src "libresoc.v:126925.9-126925.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\ds[15:0] \$22 [15:0] @@ -198742,86 +198888,86 @@ module \dec_bi sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:126605$4848_Y - connect \$11 $pos$libresoc.v:126606$4850_Y - connect \$14 $sshl$libresoc.v:126607$4851_Y - connect \$17 $sshl$libresoc.v:126608$4852_Y - connect \$1 $pos$libresoc.v:126609$4854_Y - connect \$20 $sshl$libresoc.v:126610$4855_Y - connect \$23 $sshl$libresoc.v:126611$4856_Y - connect \$4 $sshl$libresoc.v:126612$4857_Y - connect \$3 $pos$libresoc.v:126613$4859_Y + connect \$9 $pos$libresoc.v:126705$4848_Y + connect \$11 $pos$libresoc.v:126706$4850_Y + connect \$14 $sshl$libresoc.v:126707$4851_Y + connect \$17 $sshl$libresoc.v:126708$4852_Y + connect \$1 $pos$libresoc.v:126709$4854_Y + connect \$20 $sshl$libresoc.v:126710$4855_Y + connect \$23 $sshl$libresoc.v:126711$4856_Y + connect \$4 $sshl$libresoc.v:126712$4857_Y + connect \$3 $pos$libresoc.v:126713$4859_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:126783.1-127036.10" +attribute \src "libresoc.v:126967.1-127304.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_bi" attribute \generator "nMigen" module \dec_bi$144 - attribute \src "libresoc.v:127010.3-127020.6" + attribute \src "libresoc.v:127234.3-127264.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:127021.3-127031.6" + attribute \src "libresoc.v:127265.3-127299.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:126872.3-126918.6" + attribute \src "libresoc.v:127056.3-127102.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:126919.3-126965.6" + attribute \src "libresoc.v:127103.3-127149.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:126784.7-126784.20" + attribute \src "libresoc.v:126968.7-126968.20" wire $0\initial[0:0] - attribute \src "libresoc.v:126999.3-127009.6" + attribute \src "libresoc.v:127207.3-127233.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:126966.3-126976.6" + attribute \src "libresoc.v:127150.3-127164.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:126977.3-126987.6" + attribute \src "libresoc.v:127165.3-127183.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:126988.3-126998.6" + attribute \src "libresoc.v:127184.3-127206.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:127010.3-127020.6" + attribute \src "libresoc.v:127234.3-127264.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:127021.3-127031.6" + attribute \src "libresoc.v:127265.3-127299.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:126872.3-126918.6" + attribute \src "libresoc.v:127056.3-127102.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:126919.3-126965.6" + attribute \src "libresoc.v:127103.3-127149.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:126999.3-127009.6" + attribute \src "libresoc.v:127207.3-127233.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:126966.3-126976.6" + attribute \src "libresoc.v:127150.3-127164.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:126977.3-126987.6" + attribute \src "libresoc.v:127165.3-127183.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:126988.3-126998.6" + attribute \src "libresoc.v:127184.3-127206.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:126862.17-126862.107" - wire width 64 $extend$libresoc.v:126862$4869_Y - attribute \src "libresoc.v:126863.18-126863.110" - wire width 64 $extend$libresoc.v:126863$4871_Y - attribute \src "libresoc.v:126866.17-126866.107" - wire width 64 $extend$libresoc.v:126866$4875_Y - attribute \src "libresoc.v:126870.17-126870.102" - wire width 64 $extend$libresoc.v:126870$4880_Y - attribute \src "libresoc.v:126862.17-126862.107" - wire width 64 $pos$libresoc.v:126862$4870_Y - attribute \src "libresoc.v:126863.18-126863.110" - wire width 64 $pos$libresoc.v:126863$4872_Y - attribute \src "libresoc.v:126866.17-126866.107" - wire width 64 $pos$libresoc.v:126866$4876_Y - attribute \src "libresoc.v:126870.17-126870.102" - wire width 64 $pos$libresoc.v:126870$4881_Y - attribute \src "libresoc.v:126864.18-126864.117" - wire width 47 $sshl$libresoc.v:126864$4873_Y - attribute \src "libresoc.v:126865.18-126865.116" - wire width 27 $sshl$libresoc.v:126865$4874_Y - attribute \src "libresoc.v:126867.18-126867.116" - wire width 17 $sshl$libresoc.v:126867$4877_Y - attribute \src "libresoc.v:126868.18-126868.116" - wire width 17 $sshl$libresoc.v:126868$4878_Y - attribute \src "libresoc.v:126869.17-126869.109" - wire width 47 $sshl$libresoc.v:126869$4879_Y + attribute \src "libresoc.v:127046.17-127046.107" + wire width 64 $extend$libresoc.v:127046$4869_Y + attribute \src "libresoc.v:127047.18-127047.110" + wire width 64 $extend$libresoc.v:127047$4871_Y + attribute \src "libresoc.v:127050.17-127050.107" + wire width 64 $extend$libresoc.v:127050$4875_Y + attribute \src "libresoc.v:127054.17-127054.102" + wire width 64 $extend$libresoc.v:127054$4880_Y + attribute \src "libresoc.v:127046.17-127046.107" + wire width 64 $pos$libresoc.v:127046$4870_Y + attribute \src "libresoc.v:127047.18-127047.110" + wire width 64 $pos$libresoc.v:127047$4872_Y + attribute \src "libresoc.v:127050.17-127050.107" + wire width 64 $pos$libresoc.v:127050$4876_Y + attribute \src "libresoc.v:127054.17-127054.102" + wire width 64 $pos$libresoc.v:127054$4881_Y + attribute \src "libresoc.v:127048.18-127048.117" + wire width 47 $sshl$libresoc.v:127048$4873_Y + attribute \src "libresoc.v:127049.18-127049.116" + wire width 27 $sshl$libresoc.v:127049$4874_Y + attribute \src "libresoc.v:127051.18-127051.116" + wire width 17 $sshl$libresoc.v:127051$4877_Y + attribute \src "libresoc.v:127052.18-127052.116" + wire width 17 $sshl$libresoc.v:127052$4878_Y + attribute \src "libresoc.v:127053.17-127053.109" + wire width 47 $sshl$libresoc.v:127053$4879_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" @@ -198872,7 +199018,7 @@ module \dec_bi$144 wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \imm_b_ok - attribute \src "libresoc.v:126784.7-126784.15" + attribute \src "libresoc.v:126968.7-126968.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" wire width 26 \li @@ -198900,71 +199046,71 @@ module \dec_bi$144 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" wire width 16 \ui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:126862$4869 + cell $pos $extend$libresoc.v:127046$4869 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \BRANCH_sh - connect \Y $extend$libresoc.v:126862$4869_Y + connect \Y $extend$libresoc.v:127046$4869_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:126863$4871 + cell $pos $extend$libresoc.v:127047$4871 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \BRANCH_SH32 - connect \Y $extend$libresoc.v:126863$4871_Y + connect \Y $extend$libresoc.v:127047$4871_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:126866$4875 + cell $pos $extend$libresoc.v:127050$4875 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \BRANCH_UI - connect \Y $extend$libresoc.v:126866$4875_Y + connect \Y $extend$libresoc.v:127050$4875_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - cell $pos $extend$libresoc.v:126870$4880 + cell $pos $extend$libresoc.v:127054$4880 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:126870$4880_Y + connect \Y $extend$libresoc.v:127054$4880_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:126862$4870 + cell $pos $pos$libresoc.v:127046$4870 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126862$4869_Y - connect \Y $pos$libresoc.v:126862$4870_Y + connect \A $extend$libresoc.v:127046$4869_Y + connect \Y $pos$libresoc.v:127046$4870_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:126863$4872 + cell $pos $pos$libresoc.v:127047$4872 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126863$4871_Y - connect \Y $pos$libresoc.v:126863$4872_Y + connect \A $extend$libresoc.v:127047$4871_Y + connect \Y $pos$libresoc.v:127047$4872_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:126866$4876 + cell $pos $pos$libresoc.v:127050$4876 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126866$4875_Y - connect \Y $pos$libresoc.v:126866$4876_Y + connect \A $extend$libresoc.v:127050$4875_Y + connect \Y $pos$libresoc.v:127050$4876_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - cell $pos $pos$libresoc.v:126870$4881 + cell $pos $pos$libresoc.v:127054$4881 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:126870$4880_Y - connect \Y $pos$libresoc.v:126870$4881_Y + connect \A $extend$libresoc.v:127054$4880_Y + connect \Y $pos$libresoc.v:127054$4881_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - cell $sshl $sshl$libresoc.v:126864$4873 + cell $sshl $sshl$libresoc.v:127048$4873 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -198972,10 +199118,10 @@ module \dec_bi$144 parameter \Y_WIDTH 47 connect \A \BRANCH_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:126864$4873_Y + connect \Y $sshl$libresoc.v:127048$4873_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" - cell $sshl $sshl$libresoc.v:126865$4874 + cell $sshl $sshl$libresoc.v:127049$4874 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -198983,10 +199129,10 @@ module \dec_bi$144 parameter \Y_WIDTH 27 connect \A \BRANCH_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:126865$4874_Y + connect \Y $sshl$libresoc.v:127049$4874_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" - cell $sshl $sshl$libresoc.v:126867$4877 + cell $sshl $sshl$libresoc.v:127051$4877 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -198994,10 +199140,10 @@ module \dec_bi$144 parameter \Y_WIDTH 17 connect \A \BRANCH_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:126867$4877_Y + connect \Y $sshl$libresoc.v:127051$4877_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" - cell $sshl $sshl$libresoc.v:126868$4878 + cell $sshl $sshl$libresoc.v:127052$4878 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -199005,10 +199151,10 @@ module \dec_bi$144 parameter \Y_WIDTH 17 connect \A \BRANCH_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:126868$4878_Y + connect \Y $sshl$libresoc.v:127052$4878_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - cell $sshl $sshl$libresoc.v:126869$4879 + cell $sshl $sshl$libresoc.v:127053$4879 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -199016,24 +199162,24 @@ module \dec_bi$144 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:126869$4879_Y + connect \Y $sshl$libresoc.v:127053$4879_Y end - attribute \src "libresoc.v:126784.7-126784.20" - process $proc$libresoc.v:126784$4890 + attribute \src "libresoc.v:126968.7-126968.20" + process $proc$libresoc.v:126968$4890 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:126872.3-126918.6" - process $proc$libresoc.v:126872$4882 + attribute \src "libresoc.v:127056.3-127102.6" + process $proc$libresoc.v:127056$4882 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:126873.5-126873.29" + attribute \src "libresoc.v:127057.5-127057.29" switch \initial - attribute \src "libresoc.v:126873.9-126873.17" + attribute \src "libresoc.v:127057.9-127057.17" case 1'1 case end @@ -199085,14 +199231,14 @@ module \dec_bi$144 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:126919.3-126965.6" - process $proc$libresoc.v:126919$4883 + attribute \src "libresoc.v:127103.3-127149.6" + process $proc$libresoc.v:127103$4883 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:126920.5-126920.29" + attribute \src "libresoc.v:127104.5-127104.29" switch \initial - attribute \src "libresoc.v:126920.9-126920.17" + attribute \src "libresoc.v:127104.9-127104.17" case 1'1 case end @@ -199144,20 +199290,23 @@ module \dec_bi$144 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:126966.3-126976.6" - process $proc$libresoc.v:126966$4884 + attribute \src "libresoc.v:127150.3-127164.6" + process $proc$libresoc.v:127150$4884 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:126967.5-126967.29" + attribute \src "libresoc.v:127151.5-127151.29" switch \initial - attribute \src "libresoc.v:126967.9-126967.17" + attribute \src "libresoc.v:127151.9-127151.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\si[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\si[15:0] \BRANCH_SI @@ -199167,20 +199316,26 @@ module \dec_bi$144 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:126977.3-126987.6" - process $proc$libresoc.v:126977$4885 + attribute \src "libresoc.v:127165.3-127183.6" + process $proc$libresoc.v:127165$4885 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:126978.5-126978.29" + attribute \src "libresoc.v:127166.5-127166.29" switch \initial - attribute \src "libresoc.v:126978.9-126978.17" + attribute \src "libresoc.v:127166.9-127166.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\si_hi[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\si_hi[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\si_hi[31:0] \$13 [31:0] @@ -199190,20 +199345,29 @@ module \dec_bi$144 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:126988.3-126998.6" - process $proc$libresoc.v:126988$4886 + attribute \src "libresoc.v:127184.3-127206.6" + process $proc$libresoc.v:127184$4886 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:126989.5-126989.29" + attribute \src "libresoc.v:127185.5-127185.29" switch \initial - attribute \src "libresoc.v:126989.9-126989.17" + attribute \src "libresoc.v:127185.9-127185.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\ui[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\ui[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\ui[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\ui[15:0] \BRANCH_UI @@ -199213,20 +199377,32 @@ module \dec_bi$144 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:126999.3-127009.6" - process $proc$libresoc.v:126999$4887 + attribute \src "libresoc.v:127207.3-127233.6" + process $proc$libresoc.v:127207$4887 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:127000.5-127000.29" + attribute \src "libresoc.v:127208.5-127208.29" switch \initial - attribute \src "libresoc.v:127000.9-127000.17" + attribute \src "libresoc.v:127208.9-127208.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\li[25:0] \$16 [25:0] @@ -199236,20 +199412,35 @@ module \dec_bi$144 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:127010.3-127020.6" - process $proc$libresoc.v:127010$4888 + attribute \src "libresoc.v:127234.3-127264.6" + process $proc$libresoc.v:127234$4888 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:127011.5-127011.29" + attribute \src "libresoc.v:127235.5-127235.29" switch \initial - attribute \src "libresoc.v:127011.9-127011.17" + attribute \src "libresoc.v:127235.9-127235.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\bd[15:0] \$19 [15:0] @@ -199259,20 +199450,38 @@ module \dec_bi$144 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:127021.3-127031.6" - process $proc$libresoc.v:127021$4889 + attribute \src "libresoc.v:127265.3-127299.6" + process $proc$libresoc.v:127265$4889 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:127022.5-127022.29" + attribute \src "libresoc.v:127266.5-127266.29" switch \initial - attribute \src "libresoc.v:127022.9-127022.17" + attribute \src "libresoc.v:127266.9-127266.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\ds[15:0] \$22 [15:0] @@ -199282,86 +199491,86 @@ module \dec_bi$144 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:126862$4870_Y - connect \$11 $pos$libresoc.v:126863$4872_Y - connect \$14 $sshl$libresoc.v:126864$4873_Y - connect \$17 $sshl$libresoc.v:126865$4874_Y - connect \$1 $pos$libresoc.v:126866$4876_Y - connect \$20 $sshl$libresoc.v:126867$4877_Y - connect \$23 $sshl$libresoc.v:126868$4878_Y - connect \$4 $sshl$libresoc.v:126869$4879_Y - connect \$3 $pos$libresoc.v:126870$4881_Y + connect \$9 $pos$libresoc.v:127046$4870_Y + connect \$11 $pos$libresoc.v:127047$4872_Y + connect \$14 $sshl$libresoc.v:127048$4873_Y + connect \$17 $sshl$libresoc.v:127049$4874_Y + connect \$1 $pos$libresoc.v:127050$4876_Y + connect \$20 $sshl$libresoc.v:127051$4877_Y + connect \$23 $sshl$libresoc.v:127052$4878_Y + connect \$4 $sshl$libresoc.v:127053$4879_Y + connect \$3 $pos$libresoc.v:127054$4881_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:127040.1-127293.10" +attribute \src "libresoc.v:127308.1-127645.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_bi" attribute \generator "nMigen" module \dec_bi$149 - attribute \src "libresoc.v:127267.3-127277.6" + attribute \src "libresoc.v:127575.3-127605.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:127278.3-127288.6" + attribute \src "libresoc.v:127606.3-127640.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:127129.3-127175.6" + attribute \src "libresoc.v:127397.3-127443.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:127176.3-127222.6" + attribute \src "libresoc.v:127444.3-127490.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:127041.7-127041.20" + attribute \src "libresoc.v:127309.7-127309.20" wire $0\initial[0:0] - attribute \src "libresoc.v:127256.3-127266.6" + attribute \src "libresoc.v:127548.3-127574.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:127223.3-127233.6" + attribute \src "libresoc.v:127491.3-127505.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:127234.3-127244.6" + attribute \src "libresoc.v:127506.3-127524.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:127245.3-127255.6" + attribute \src "libresoc.v:127525.3-127547.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:127267.3-127277.6" + attribute \src "libresoc.v:127575.3-127605.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:127278.3-127288.6" + attribute \src "libresoc.v:127606.3-127640.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:127129.3-127175.6" + attribute \src "libresoc.v:127397.3-127443.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:127176.3-127222.6" + attribute \src "libresoc.v:127444.3-127490.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:127256.3-127266.6" + attribute \src "libresoc.v:127548.3-127574.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:127223.3-127233.6" + attribute \src "libresoc.v:127491.3-127505.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:127234.3-127244.6" + attribute \src "libresoc.v:127506.3-127524.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:127245.3-127255.6" + attribute \src "libresoc.v:127525.3-127547.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:127119.17-127119.108" - wire width 64 $extend$libresoc.v:127119$4891_Y - attribute \src "libresoc.v:127120.18-127120.111" - wire width 64 $extend$libresoc.v:127120$4893_Y - attribute \src "libresoc.v:127123.17-127123.108" - wire width 64 $extend$libresoc.v:127123$4897_Y - attribute \src "libresoc.v:127127.17-127127.102" - wire width 64 $extend$libresoc.v:127127$4902_Y - attribute \src "libresoc.v:127119.17-127119.108" - wire width 64 $pos$libresoc.v:127119$4892_Y - attribute \src "libresoc.v:127120.18-127120.111" - wire width 64 $pos$libresoc.v:127120$4894_Y - attribute \src "libresoc.v:127123.17-127123.108" - wire width 64 $pos$libresoc.v:127123$4898_Y - attribute \src "libresoc.v:127127.17-127127.102" - wire width 64 $pos$libresoc.v:127127$4903_Y - attribute \src "libresoc.v:127121.18-127121.118" - wire width 47 $sshl$libresoc.v:127121$4895_Y - attribute \src "libresoc.v:127122.18-127122.117" - wire width 27 $sshl$libresoc.v:127122$4896_Y - attribute \src "libresoc.v:127124.18-127124.117" - wire width 17 $sshl$libresoc.v:127124$4899_Y - attribute \src "libresoc.v:127125.18-127125.117" - wire width 17 $sshl$libresoc.v:127125$4900_Y - attribute \src "libresoc.v:127126.17-127126.109" - wire width 47 $sshl$libresoc.v:127126$4901_Y + attribute \src "libresoc.v:127387.17-127387.108" + wire width 64 $extend$libresoc.v:127387$4891_Y + attribute \src "libresoc.v:127388.18-127388.111" + wire width 64 $extend$libresoc.v:127388$4893_Y + attribute \src "libresoc.v:127391.17-127391.108" + wire width 64 $extend$libresoc.v:127391$4897_Y + attribute \src "libresoc.v:127395.17-127395.102" + wire width 64 $extend$libresoc.v:127395$4902_Y + attribute \src "libresoc.v:127387.17-127387.108" + wire width 64 $pos$libresoc.v:127387$4892_Y + attribute \src "libresoc.v:127388.18-127388.111" + wire width 64 $pos$libresoc.v:127388$4894_Y + attribute \src "libresoc.v:127391.17-127391.108" + wire width 64 $pos$libresoc.v:127391$4898_Y + attribute \src "libresoc.v:127395.17-127395.102" + wire width 64 $pos$libresoc.v:127395$4903_Y + attribute \src "libresoc.v:127389.18-127389.118" + wire width 47 $sshl$libresoc.v:127389$4895_Y + attribute \src "libresoc.v:127390.18-127390.117" + wire width 27 $sshl$libresoc.v:127390$4896_Y + attribute \src "libresoc.v:127392.18-127392.117" + wire width 17 $sshl$libresoc.v:127392$4899_Y + attribute \src "libresoc.v:127393.18-127393.117" + wire width 17 $sshl$libresoc.v:127393$4900_Y + attribute \src "libresoc.v:127394.17-127394.109" + wire width 47 $sshl$libresoc.v:127394$4901_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" @@ -199412,7 +199621,7 @@ module \dec_bi$149 wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \imm_b_ok - attribute \src "libresoc.v:127041.7-127041.15" + attribute \src "libresoc.v:127309.7-127309.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" wire width 26 \li @@ -199440,71 +199649,71 @@ module \dec_bi$149 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" wire width 16 \ui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:127119$4891 + cell $pos $extend$libresoc.v:127387$4891 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \LOGICAL_sh - connect \Y $extend$libresoc.v:127119$4891_Y + connect \Y $extend$libresoc.v:127387$4891_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:127120$4893 + cell $pos $extend$libresoc.v:127388$4893 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \LOGICAL_SH32 - connect \Y $extend$libresoc.v:127120$4893_Y + connect \Y $extend$libresoc.v:127388$4893_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:127123$4897 + cell $pos $extend$libresoc.v:127391$4897 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \LOGICAL_UI - connect \Y $extend$libresoc.v:127123$4897_Y + connect \Y $extend$libresoc.v:127391$4897_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - cell $pos $extend$libresoc.v:127127$4902 + cell $pos $extend$libresoc.v:127395$4902 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:127127$4902_Y + connect \Y $extend$libresoc.v:127395$4902_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:127119$4892 + cell $pos $pos$libresoc.v:127387$4892 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127119$4891_Y - connect \Y $pos$libresoc.v:127119$4892_Y + connect \A $extend$libresoc.v:127387$4891_Y + connect \Y $pos$libresoc.v:127387$4892_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:127120$4894 + cell $pos $pos$libresoc.v:127388$4894 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127120$4893_Y - connect \Y $pos$libresoc.v:127120$4894_Y + connect \A $extend$libresoc.v:127388$4893_Y + connect \Y $pos$libresoc.v:127388$4894_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:127123$4898 + cell $pos $pos$libresoc.v:127391$4898 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127123$4897_Y - connect \Y $pos$libresoc.v:127123$4898_Y + connect \A $extend$libresoc.v:127391$4897_Y + connect \Y $pos$libresoc.v:127391$4898_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - cell $pos $pos$libresoc.v:127127$4903 + cell $pos $pos$libresoc.v:127395$4903 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127127$4902_Y - connect \Y $pos$libresoc.v:127127$4903_Y + connect \A $extend$libresoc.v:127395$4902_Y + connect \Y $pos$libresoc.v:127395$4903_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - cell $sshl $sshl$libresoc.v:127121$4895 + cell $sshl $sshl$libresoc.v:127389$4895 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -199512,10 +199721,10 @@ module \dec_bi$149 parameter \Y_WIDTH 47 connect \A \LOGICAL_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:127121$4895_Y + connect \Y $sshl$libresoc.v:127389$4895_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" - cell $sshl $sshl$libresoc.v:127122$4896 + cell $sshl $sshl$libresoc.v:127390$4896 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -199523,10 +199732,10 @@ module \dec_bi$149 parameter \Y_WIDTH 27 connect \A \LOGICAL_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:127122$4896_Y + connect \Y $sshl$libresoc.v:127390$4896_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" - cell $sshl $sshl$libresoc.v:127124$4899 + cell $sshl $sshl$libresoc.v:127392$4899 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -199534,10 +199743,10 @@ module \dec_bi$149 parameter \Y_WIDTH 17 connect \A \LOGICAL_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:127124$4899_Y + connect \Y $sshl$libresoc.v:127392$4899_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" - cell $sshl $sshl$libresoc.v:127125$4900 + cell $sshl $sshl$libresoc.v:127393$4900 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -199545,10 +199754,10 @@ module \dec_bi$149 parameter \Y_WIDTH 17 connect \A \LOGICAL_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:127125$4900_Y + connect \Y $sshl$libresoc.v:127393$4900_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - cell $sshl $sshl$libresoc.v:127126$4901 + cell $sshl $sshl$libresoc.v:127394$4901 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -199556,24 +199765,24 @@ module \dec_bi$149 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:127126$4901_Y + connect \Y $sshl$libresoc.v:127394$4901_Y end - attribute \src "libresoc.v:127041.7-127041.20" - process $proc$libresoc.v:127041$4912 + attribute \src "libresoc.v:127309.7-127309.20" + process $proc$libresoc.v:127309$4912 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:127129.3-127175.6" - process $proc$libresoc.v:127129$4904 + attribute \src "libresoc.v:127397.3-127443.6" + process $proc$libresoc.v:127397$4904 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:127130.5-127130.29" + attribute \src "libresoc.v:127398.5-127398.29" switch \initial - attribute \src "libresoc.v:127130.9-127130.17" + attribute \src "libresoc.v:127398.9-127398.17" case 1'1 case end @@ -199625,14 +199834,14 @@ module \dec_bi$149 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:127176.3-127222.6" - process $proc$libresoc.v:127176$4905 + attribute \src "libresoc.v:127444.3-127490.6" + process $proc$libresoc.v:127444$4905 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:127177.5-127177.29" + attribute \src "libresoc.v:127445.5-127445.29" switch \initial - attribute \src "libresoc.v:127177.9-127177.17" + attribute \src "libresoc.v:127445.9-127445.17" case 1'1 case end @@ -199684,20 +199893,23 @@ module \dec_bi$149 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:127223.3-127233.6" - process $proc$libresoc.v:127223$4906 + attribute \src "libresoc.v:127491.3-127505.6" + process $proc$libresoc.v:127491$4906 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:127224.5-127224.29" + attribute \src "libresoc.v:127492.5-127492.29" switch \initial - attribute \src "libresoc.v:127224.9-127224.17" + attribute \src "libresoc.v:127492.9-127492.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\si[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\si[15:0] \LOGICAL_SI @@ -199707,20 +199919,26 @@ module \dec_bi$149 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:127234.3-127244.6" - process $proc$libresoc.v:127234$4907 + attribute \src "libresoc.v:127506.3-127524.6" + process $proc$libresoc.v:127506$4907 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:127235.5-127235.29" + attribute \src "libresoc.v:127507.5-127507.29" switch \initial - attribute \src "libresoc.v:127235.9-127235.17" + attribute \src "libresoc.v:127507.9-127507.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\si_hi[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\si_hi[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\si_hi[31:0] \$13 [31:0] @@ -199730,20 +199948,29 @@ module \dec_bi$149 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:127245.3-127255.6" - process $proc$libresoc.v:127245$4908 + attribute \src "libresoc.v:127525.3-127547.6" + process $proc$libresoc.v:127525$4908 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:127246.5-127246.29" + attribute \src "libresoc.v:127526.5-127526.29" switch \initial - attribute \src "libresoc.v:127246.9-127246.17" + attribute \src "libresoc.v:127526.9-127526.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\ui[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\ui[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\ui[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\ui[15:0] \LOGICAL_UI @@ -199753,20 +199980,32 @@ module \dec_bi$149 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:127256.3-127266.6" - process $proc$libresoc.v:127256$4909 + attribute \src "libresoc.v:127548.3-127574.6" + process $proc$libresoc.v:127548$4909 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:127257.5-127257.29" + attribute \src "libresoc.v:127549.5-127549.29" switch \initial - attribute \src "libresoc.v:127257.9-127257.17" + attribute \src "libresoc.v:127549.9-127549.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\li[25:0] \$16 [25:0] @@ -199776,20 +200015,35 @@ module \dec_bi$149 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:127267.3-127277.6" - process $proc$libresoc.v:127267$4910 + attribute \src "libresoc.v:127575.3-127605.6" + process $proc$libresoc.v:127575$4910 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:127268.5-127268.29" + attribute \src "libresoc.v:127576.5-127576.29" switch \initial - attribute \src "libresoc.v:127268.9-127268.17" + attribute \src "libresoc.v:127576.9-127576.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\bd[15:0] \$19 [15:0] @@ -199799,20 +200053,38 @@ module \dec_bi$149 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:127278.3-127288.6" - process $proc$libresoc.v:127278$4911 + attribute \src "libresoc.v:127606.3-127640.6" + process $proc$libresoc.v:127606$4911 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:127279.5-127279.29" + attribute \src "libresoc.v:127607.5-127607.29" switch \initial - attribute \src "libresoc.v:127279.9-127279.17" + attribute \src "libresoc.v:127607.9-127607.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\ds[15:0] \$22 [15:0] @@ -199822,86 +200094,86 @@ module \dec_bi$149 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:127119$4892_Y - connect \$11 $pos$libresoc.v:127120$4894_Y - connect \$14 $sshl$libresoc.v:127121$4895_Y - connect \$17 $sshl$libresoc.v:127122$4896_Y - connect \$1 $pos$libresoc.v:127123$4898_Y - connect \$20 $sshl$libresoc.v:127124$4899_Y - connect \$23 $sshl$libresoc.v:127125$4900_Y - connect \$4 $sshl$libresoc.v:127126$4901_Y - connect \$3 $pos$libresoc.v:127127$4903_Y + connect \$9 $pos$libresoc.v:127387$4892_Y + connect \$11 $pos$libresoc.v:127388$4894_Y + connect \$14 $sshl$libresoc.v:127389$4895_Y + connect \$17 $sshl$libresoc.v:127390$4896_Y + connect \$1 $pos$libresoc.v:127391$4898_Y + connect \$20 $sshl$libresoc.v:127392$4899_Y + connect \$23 $sshl$libresoc.v:127393$4900_Y + connect \$4 $sshl$libresoc.v:127394$4901_Y + connect \$3 $pos$libresoc.v:127395$4903_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:127297.1-127550.10" +attribute \src "libresoc.v:127649.1-127986.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_bi" attribute \generator "nMigen" module \dec_bi$157 - attribute \src "libresoc.v:127524.3-127534.6" + attribute \src "libresoc.v:127916.3-127946.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:127535.3-127545.6" + attribute \src "libresoc.v:127947.3-127981.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:127386.3-127432.6" + attribute \src "libresoc.v:127738.3-127784.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:127433.3-127479.6" + attribute \src "libresoc.v:127785.3-127831.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:127298.7-127298.20" + attribute \src "libresoc.v:127650.7-127650.20" wire $0\initial[0:0] - attribute \src "libresoc.v:127513.3-127523.6" + attribute \src "libresoc.v:127889.3-127915.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:127480.3-127490.6" + attribute \src "libresoc.v:127832.3-127846.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:127491.3-127501.6" + attribute \src "libresoc.v:127847.3-127865.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:127502.3-127512.6" + attribute \src "libresoc.v:127866.3-127888.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:127524.3-127534.6" + attribute \src "libresoc.v:127916.3-127946.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:127535.3-127545.6" + attribute \src "libresoc.v:127947.3-127981.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:127386.3-127432.6" + attribute \src "libresoc.v:127738.3-127784.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:127433.3-127479.6" + attribute \src "libresoc.v:127785.3-127831.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:127513.3-127523.6" + attribute \src "libresoc.v:127889.3-127915.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:127480.3-127490.6" + attribute \src "libresoc.v:127832.3-127846.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:127491.3-127501.6" + attribute \src "libresoc.v:127847.3-127865.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:127502.3-127512.6" + attribute \src "libresoc.v:127866.3-127888.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:127376.17-127376.104" - wire width 64 $extend$libresoc.v:127376$4913_Y - attribute \src "libresoc.v:127377.18-127377.107" - wire width 64 $extend$libresoc.v:127377$4915_Y - attribute \src "libresoc.v:127380.17-127380.104" - wire width 64 $extend$libresoc.v:127380$4919_Y - attribute \src "libresoc.v:127384.17-127384.102" - wire width 64 $extend$libresoc.v:127384$4924_Y - attribute \src "libresoc.v:127376.17-127376.104" - wire width 64 $pos$libresoc.v:127376$4914_Y - attribute \src "libresoc.v:127377.18-127377.107" - wire width 64 $pos$libresoc.v:127377$4916_Y - attribute \src "libresoc.v:127380.17-127380.104" - wire width 64 $pos$libresoc.v:127380$4920_Y - attribute \src "libresoc.v:127384.17-127384.102" - wire width 64 $pos$libresoc.v:127384$4925_Y - attribute \src "libresoc.v:127378.18-127378.114" - wire width 47 $sshl$libresoc.v:127378$4917_Y - attribute \src "libresoc.v:127379.18-127379.113" - wire width 27 $sshl$libresoc.v:127379$4918_Y - attribute \src "libresoc.v:127381.18-127381.113" - wire width 17 $sshl$libresoc.v:127381$4921_Y - attribute \src "libresoc.v:127382.18-127382.113" - wire width 17 $sshl$libresoc.v:127382$4922_Y - attribute \src "libresoc.v:127383.17-127383.109" - wire width 47 $sshl$libresoc.v:127383$4923_Y + attribute \src "libresoc.v:127728.17-127728.104" + wire width 64 $extend$libresoc.v:127728$4913_Y + attribute \src "libresoc.v:127729.18-127729.107" + wire width 64 $extend$libresoc.v:127729$4915_Y + attribute \src "libresoc.v:127732.17-127732.104" + wire width 64 $extend$libresoc.v:127732$4919_Y + attribute \src "libresoc.v:127736.17-127736.102" + wire width 64 $extend$libresoc.v:127736$4924_Y + attribute \src "libresoc.v:127728.17-127728.104" + wire width 64 $pos$libresoc.v:127728$4914_Y + attribute \src "libresoc.v:127729.18-127729.107" + wire width 64 $pos$libresoc.v:127729$4916_Y + attribute \src "libresoc.v:127732.17-127732.104" + wire width 64 $pos$libresoc.v:127732$4920_Y + attribute \src "libresoc.v:127736.17-127736.102" + wire width 64 $pos$libresoc.v:127736$4925_Y + attribute \src "libresoc.v:127730.18-127730.114" + wire width 47 $sshl$libresoc.v:127730$4917_Y + attribute \src "libresoc.v:127731.18-127731.113" + wire width 27 $sshl$libresoc.v:127731$4918_Y + attribute \src "libresoc.v:127733.18-127733.113" + wire width 17 $sshl$libresoc.v:127733$4921_Y + attribute \src "libresoc.v:127734.18-127734.113" + wire width 17 $sshl$libresoc.v:127734$4922_Y + attribute \src "libresoc.v:127735.17-127735.109" + wire width 47 $sshl$libresoc.v:127735$4923_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" @@ -199952,7 +200224,7 @@ module \dec_bi$157 wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \imm_b_ok - attribute \src "libresoc.v:127298.7-127298.15" + attribute \src "libresoc.v:127650.7-127650.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" wire width 26 \li @@ -199980,71 +200252,71 @@ module \dec_bi$157 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" wire width 16 \ui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:127376$4913 + cell $pos $extend$libresoc.v:127728$4913 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \DIV_sh - connect \Y $extend$libresoc.v:127376$4913_Y + connect \Y $extend$libresoc.v:127728$4913_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:127377$4915 + cell $pos $extend$libresoc.v:127729$4915 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \DIV_SH32 - connect \Y $extend$libresoc.v:127377$4915_Y + connect \Y $extend$libresoc.v:127729$4915_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:127380$4919 + cell $pos $extend$libresoc.v:127732$4919 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \DIV_UI - connect \Y $extend$libresoc.v:127380$4919_Y + connect \Y $extend$libresoc.v:127732$4919_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - cell $pos $extend$libresoc.v:127384$4924 + cell $pos $extend$libresoc.v:127736$4924 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:127384$4924_Y + connect \Y $extend$libresoc.v:127736$4924_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:127376$4914 + cell $pos $pos$libresoc.v:127728$4914 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127376$4913_Y - connect \Y $pos$libresoc.v:127376$4914_Y + connect \A $extend$libresoc.v:127728$4913_Y + connect \Y $pos$libresoc.v:127728$4914_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:127377$4916 + cell $pos $pos$libresoc.v:127729$4916 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127377$4915_Y - connect \Y $pos$libresoc.v:127377$4916_Y + connect \A $extend$libresoc.v:127729$4915_Y + connect \Y $pos$libresoc.v:127729$4916_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:127380$4920 + cell $pos $pos$libresoc.v:127732$4920 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127380$4919_Y - connect \Y $pos$libresoc.v:127380$4920_Y + connect \A $extend$libresoc.v:127732$4919_Y + connect \Y $pos$libresoc.v:127732$4920_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - cell $pos $pos$libresoc.v:127384$4925 + cell $pos $pos$libresoc.v:127736$4925 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127384$4924_Y - connect \Y $pos$libresoc.v:127384$4925_Y + connect \A $extend$libresoc.v:127736$4924_Y + connect \Y $pos$libresoc.v:127736$4925_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - cell $sshl $sshl$libresoc.v:127378$4917 + cell $sshl $sshl$libresoc.v:127730$4917 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -200052,10 +200324,10 @@ module \dec_bi$157 parameter \Y_WIDTH 47 connect \A \DIV_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:127378$4917_Y + connect \Y $sshl$libresoc.v:127730$4917_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" - cell $sshl $sshl$libresoc.v:127379$4918 + cell $sshl $sshl$libresoc.v:127731$4918 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -200063,10 +200335,10 @@ module \dec_bi$157 parameter \Y_WIDTH 27 connect \A \DIV_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:127379$4918_Y + connect \Y $sshl$libresoc.v:127731$4918_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" - cell $sshl $sshl$libresoc.v:127381$4921 + cell $sshl $sshl$libresoc.v:127733$4921 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -200074,10 +200346,10 @@ module \dec_bi$157 parameter \Y_WIDTH 17 connect \A \DIV_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:127381$4921_Y + connect \Y $sshl$libresoc.v:127733$4921_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" - cell $sshl $sshl$libresoc.v:127382$4922 + cell $sshl $sshl$libresoc.v:127734$4922 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -200085,10 +200357,10 @@ module \dec_bi$157 parameter \Y_WIDTH 17 connect \A \DIV_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:127382$4922_Y + connect \Y $sshl$libresoc.v:127734$4922_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - cell $sshl $sshl$libresoc.v:127383$4923 + cell $sshl $sshl$libresoc.v:127735$4923 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -200096,24 +200368,24 @@ module \dec_bi$157 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:127383$4923_Y + connect \Y $sshl$libresoc.v:127735$4923_Y end - attribute \src "libresoc.v:127298.7-127298.20" - process $proc$libresoc.v:127298$4934 + attribute \src "libresoc.v:127650.7-127650.20" + process $proc$libresoc.v:127650$4934 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:127386.3-127432.6" - process $proc$libresoc.v:127386$4926 + attribute \src "libresoc.v:127738.3-127784.6" + process $proc$libresoc.v:127738$4926 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:127387.5-127387.29" + attribute \src "libresoc.v:127739.5-127739.29" switch \initial - attribute \src "libresoc.v:127387.9-127387.17" + attribute \src "libresoc.v:127739.9-127739.17" case 1'1 case end @@ -200165,14 +200437,14 @@ module \dec_bi$157 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:127433.3-127479.6" - process $proc$libresoc.v:127433$4927 + attribute \src "libresoc.v:127785.3-127831.6" + process $proc$libresoc.v:127785$4927 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:127434.5-127434.29" + attribute \src "libresoc.v:127786.5-127786.29" switch \initial - attribute \src "libresoc.v:127434.9-127434.17" + attribute \src "libresoc.v:127786.9-127786.17" case 1'1 case end @@ -200224,20 +200496,23 @@ module \dec_bi$157 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:127480.3-127490.6" - process $proc$libresoc.v:127480$4928 + attribute \src "libresoc.v:127832.3-127846.6" + process $proc$libresoc.v:127832$4928 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:127481.5-127481.29" + attribute \src "libresoc.v:127833.5-127833.29" switch \initial - attribute \src "libresoc.v:127481.9-127481.17" + attribute \src "libresoc.v:127833.9-127833.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\si[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\si[15:0] \DIV_SI @@ -200247,20 +200522,26 @@ module \dec_bi$157 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:127491.3-127501.6" - process $proc$libresoc.v:127491$4929 + attribute \src "libresoc.v:127847.3-127865.6" + process $proc$libresoc.v:127847$4929 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:127492.5-127492.29" + attribute \src "libresoc.v:127848.5-127848.29" switch \initial - attribute \src "libresoc.v:127492.9-127492.17" + attribute \src "libresoc.v:127848.9-127848.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\si_hi[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\si_hi[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\si_hi[31:0] \$13 [31:0] @@ -200270,20 +200551,29 @@ module \dec_bi$157 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:127502.3-127512.6" - process $proc$libresoc.v:127502$4930 + attribute \src "libresoc.v:127866.3-127888.6" + process $proc$libresoc.v:127866$4930 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:127503.5-127503.29" + attribute \src "libresoc.v:127867.5-127867.29" switch \initial - attribute \src "libresoc.v:127503.9-127503.17" + attribute \src "libresoc.v:127867.9-127867.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\ui[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\ui[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\ui[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\ui[15:0] \DIV_UI @@ -200293,20 +200583,32 @@ module \dec_bi$157 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:127513.3-127523.6" - process $proc$libresoc.v:127513$4931 + attribute \src "libresoc.v:127889.3-127915.6" + process $proc$libresoc.v:127889$4931 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:127514.5-127514.29" + attribute \src "libresoc.v:127890.5-127890.29" switch \initial - attribute \src "libresoc.v:127514.9-127514.17" + attribute \src "libresoc.v:127890.9-127890.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\li[25:0] \$16 [25:0] @@ -200316,20 +200618,35 @@ module \dec_bi$157 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:127524.3-127534.6" - process $proc$libresoc.v:127524$4932 + attribute \src "libresoc.v:127916.3-127946.6" + process $proc$libresoc.v:127916$4932 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:127525.5-127525.29" + attribute \src "libresoc.v:127917.5-127917.29" switch \initial - attribute \src "libresoc.v:127525.9-127525.17" + attribute \src "libresoc.v:127917.9-127917.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\bd[15:0] \$19 [15:0] @@ -200339,20 +200656,38 @@ module \dec_bi$157 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:127535.3-127545.6" - process $proc$libresoc.v:127535$4933 + attribute \src "libresoc.v:127947.3-127981.6" + process $proc$libresoc.v:127947$4933 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:127536.5-127536.29" + attribute \src "libresoc.v:127948.5-127948.29" switch \initial - attribute \src "libresoc.v:127536.9-127536.17" + attribute \src "libresoc.v:127948.9-127948.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\ds[15:0] \$22 [15:0] @@ -200362,86 +200697,86 @@ module \dec_bi$157 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:127376$4914_Y - connect \$11 $pos$libresoc.v:127377$4916_Y - connect \$14 $sshl$libresoc.v:127378$4917_Y - connect \$17 $sshl$libresoc.v:127379$4918_Y - connect \$1 $pos$libresoc.v:127380$4920_Y - connect \$20 $sshl$libresoc.v:127381$4921_Y - connect \$23 $sshl$libresoc.v:127382$4922_Y - connect \$4 $sshl$libresoc.v:127383$4923_Y - connect \$3 $pos$libresoc.v:127384$4925_Y + connect \$9 $pos$libresoc.v:127728$4914_Y + connect \$11 $pos$libresoc.v:127729$4916_Y + connect \$14 $sshl$libresoc.v:127730$4917_Y + connect \$17 $sshl$libresoc.v:127731$4918_Y + connect \$1 $pos$libresoc.v:127732$4920_Y + connect \$20 $sshl$libresoc.v:127733$4921_Y + connect \$23 $sshl$libresoc.v:127734$4922_Y + connect \$4 $sshl$libresoc.v:127735$4923_Y + connect \$3 $pos$libresoc.v:127736$4925_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:127554.1-127807.10" +attribute \src "libresoc.v:127990.1-128327.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_bi" attribute \generator "nMigen" module \dec_bi$161 - attribute \src "libresoc.v:127781.3-127791.6" + attribute \src "libresoc.v:128257.3-128287.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:127792.3-127802.6" + attribute \src "libresoc.v:128288.3-128322.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:127643.3-127689.6" + attribute \src "libresoc.v:128079.3-128125.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:127690.3-127736.6" + attribute \src "libresoc.v:128126.3-128172.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:127555.7-127555.20" + attribute \src "libresoc.v:127991.7-127991.20" wire $0\initial[0:0] - attribute \src "libresoc.v:127770.3-127780.6" + attribute \src "libresoc.v:128230.3-128256.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:127737.3-127747.6" + attribute \src "libresoc.v:128173.3-128187.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:127748.3-127758.6" + attribute \src "libresoc.v:128188.3-128206.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:127759.3-127769.6" + attribute \src "libresoc.v:128207.3-128229.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:127781.3-127791.6" + attribute \src "libresoc.v:128257.3-128287.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:127792.3-127802.6" + attribute \src "libresoc.v:128288.3-128322.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:127643.3-127689.6" + attribute \src "libresoc.v:128079.3-128125.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:127690.3-127736.6" + attribute \src "libresoc.v:128126.3-128172.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:127770.3-127780.6" + attribute \src "libresoc.v:128230.3-128256.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:127737.3-127747.6" + attribute \src "libresoc.v:128173.3-128187.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:127748.3-127758.6" + attribute \src "libresoc.v:128188.3-128206.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:127759.3-127769.6" + attribute \src "libresoc.v:128207.3-128229.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:127633.17-127633.104" - wire width 64 $extend$libresoc.v:127633$4935_Y - attribute \src "libresoc.v:127634.18-127634.107" - wire width 64 $extend$libresoc.v:127634$4937_Y - attribute \src "libresoc.v:127637.17-127637.104" - wire width 64 $extend$libresoc.v:127637$4941_Y - attribute \src "libresoc.v:127641.17-127641.102" - wire width 64 $extend$libresoc.v:127641$4946_Y - attribute \src "libresoc.v:127633.17-127633.104" - wire width 64 $pos$libresoc.v:127633$4936_Y - attribute \src "libresoc.v:127634.18-127634.107" - wire width 64 $pos$libresoc.v:127634$4938_Y - attribute \src "libresoc.v:127637.17-127637.104" - wire width 64 $pos$libresoc.v:127637$4942_Y - attribute \src "libresoc.v:127641.17-127641.102" - wire width 64 $pos$libresoc.v:127641$4947_Y - attribute \src "libresoc.v:127635.18-127635.114" - wire width 47 $sshl$libresoc.v:127635$4939_Y - attribute \src "libresoc.v:127636.18-127636.113" - wire width 27 $sshl$libresoc.v:127636$4940_Y - attribute \src "libresoc.v:127638.18-127638.113" - wire width 17 $sshl$libresoc.v:127638$4943_Y - attribute \src "libresoc.v:127639.18-127639.113" - wire width 17 $sshl$libresoc.v:127639$4944_Y - attribute \src "libresoc.v:127640.17-127640.109" - wire width 47 $sshl$libresoc.v:127640$4945_Y + attribute \src "libresoc.v:128069.17-128069.104" + wire width 64 $extend$libresoc.v:128069$4935_Y + attribute \src "libresoc.v:128070.18-128070.107" + wire width 64 $extend$libresoc.v:128070$4937_Y + attribute \src "libresoc.v:128073.17-128073.104" + wire width 64 $extend$libresoc.v:128073$4941_Y + attribute \src "libresoc.v:128077.17-128077.102" + wire width 64 $extend$libresoc.v:128077$4946_Y + attribute \src "libresoc.v:128069.17-128069.104" + wire width 64 $pos$libresoc.v:128069$4936_Y + attribute \src "libresoc.v:128070.18-128070.107" + wire width 64 $pos$libresoc.v:128070$4938_Y + attribute \src "libresoc.v:128073.17-128073.104" + wire width 64 $pos$libresoc.v:128073$4942_Y + attribute \src "libresoc.v:128077.17-128077.102" + wire width 64 $pos$libresoc.v:128077$4947_Y + attribute \src "libresoc.v:128071.18-128071.114" + wire width 47 $sshl$libresoc.v:128071$4939_Y + attribute \src "libresoc.v:128072.18-128072.113" + wire width 27 $sshl$libresoc.v:128072$4940_Y + attribute \src "libresoc.v:128074.18-128074.113" + wire width 17 $sshl$libresoc.v:128074$4943_Y + attribute \src "libresoc.v:128075.18-128075.113" + wire width 17 $sshl$libresoc.v:128075$4944_Y + attribute \src "libresoc.v:128076.17-128076.109" + wire width 47 $sshl$libresoc.v:128076$4945_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" @@ -200492,7 +200827,7 @@ module \dec_bi$161 wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \imm_b_ok - attribute \src "libresoc.v:127555.7-127555.15" + attribute \src "libresoc.v:127991.7-127991.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" wire width 26 \li @@ -200520,71 +200855,71 @@ module \dec_bi$161 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" wire width 16 \ui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:127633$4935 + cell $pos $extend$libresoc.v:128069$4935 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \MUL_sh - connect \Y $extend$libresoc.v:127633$4935_Y + connect \Y $extend$libresoc.v:128069$4935_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:127634$4937 + cell $pos $extend$libresoc.v:128070$4937 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \MUL_SH32 - connect \Y $extend$libresoc.v:127634$4937_Y + connect \Y $extend$libresoc.v:128070$4937_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:127637$4941 + cell $pos $extend$libresoc.v:128073$4941 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \MUL_UI - connect \Y $extend$libresoc.v:127637$4941_Y + connect \Y $extend$libresoc.v:128073$4941_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - cell $pos $extend$libresoc.v:127641$4946 + cell $pos $extend$libresoc.v:128077$4946 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:127641$4946_Y + connect \Y $extend$libresoc.v:128077$4946_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:127633$4936 + cell $pos $pos$libresoc.v:128069$4936 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127633$4935_Y - connect \Y $pos$libresoc.v:127633$4936_Y + connect \A $extend$libresoc.v:128069$4935_Y + connect \Y $pos$libresoc.v:128069$4936_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:127634$4938 + cell $pos $pos$libresoc.v:128070$4938 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127634$4937_Y - connect \Y $pos$libresoc.v:127634$4938_Y + connect \A $extend$libresoc.v:128070$4937_Y + connect \Y $pos$libresoc.v:128070$4938_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:127637$4942 + cell $pos $pos$libresoc.v:128073$4942 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127637$4941_Y - connect \Y $pos$libresoc.v:127637$4942_Y + connect \A $extend$libresoc.v:128073$4941_Y + connect \Y $pos$libresoc.v:128073$4942_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - cell $pos $pos$libresoc.v:127641$4947 + cell $pos $pos$libresoc.v:128077$4947 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127641$4946_Y - connect \Y $pos$libresoc.v:127641$4947_Y + connect \A $extend$libresoc.v:128077$4946_Y + connect \Y $pos$libresoc.v:128077$4947_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - cell $sshl $sshl$libresoc.v:127635$4939 + cell $sshl $sshl$libresoc.v:128071$4939 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -200592,10 +200927,10 @@ module \dec_bi$161 parameter \Y_WIDTH 47 connect \A \MUL_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:127635$4939_Y + connect \Y $sshl$libresoc.v:128071$4939_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" - cell $sshl $sshl$libresoc.v:127636$4940 + cell $sshl $sshl$libresoc.v:128072$4940 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -200603,10 +200938,10 @@ module \dec_bi$161 parameter \Y_WIDTH 27 connect \A \MUL_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:127636$4940_Y + connect \Y $sshl$libresoc.v:128072$4940_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" - cell $sshl $sshl$libresoc.v:127638$4943 + cell $sshl $sshl$libresoc.v:128074$4943 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -200614,10 +200949,10 @@ module \dec_bi$161 parameter \Y_WIDTH 17 connect \A \MUL_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:127638$4943_Y + connect \Y $sshl$libresoc.v:128074$4943_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" - cell $sshl $sshl$libresoc.v:127639$4944 + cell $sshl $sshl$libresoc.v:128075$4944 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -200625,10 +200960,10 @@ module \dec_bi$161 parameter \Y_WIDTH 17 connect \A \MUL_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:127639$4944_Y + connect \Y $sshl$libresoc.v:128075$4944_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - cell $sshl $sshl$libresoc.v:127640$4945 + cell $sshl $sshl$libresoc.v:128076$4945 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -200636,24 +200971,24 @@ module \dec_bi$161 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:127640$4945_Y + connect \Y $sshl$libresoc.v:128076$4945_Y end - attribute \src "libresoc.v:127555.7-127555.20" - process $proc$libresoc.v:127555$4956 + attribute \src "libresoc.v:127991.7-127991.20" + process $proc$libresoc.v:127991$4956 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:127643.3-127689.6" - process $proc$libresoc.v:127643$4948 + attribute \src "libresoc.v:128079.3-128125.6" + process $proc$libresoc.v:128079$4948 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:127644.5-127644.29" + attribute \src "libresoc.v:128080.5-128080.29" switch \initial - attribute \src "libresoc.v:127644.9-127644.17" + attribute \src "libresoc.v:128080.9-128080.17" case 1'1 case end @@ -200705,14 +201040,14 @@ module \dec_bi$161 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:127690.3-127736.6" - process $proc$libresoc.v:127690$4949 + attribute \src "libresoc.v:128126.3-128172.6" + process $proc$libresoc.v:128126$4949 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:127691.5-127691.29" + attribute \src "libresoc.v:128127.5-128127.29" switch \initial - attribute \src "libresoc.v:127691.9-127691.17" + attribute \src "libresoc.v:128127.9-128127.17" case 1'1 case end @@ -200764,20 +201099,23 @@ module \dec_bi$161 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:127737.3-127747.6" - process $proc$libresoc.v:127737$4950 + attribute \src "libresoc.v:128173.3-128187.6" + process $proc$libresoc.v:128173$4950 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:127738.5-127738.29" + attribute \src "libresoc.v:128174.5-128174.29" switch \initial - attribute \src "libresoc.v:127738.9-127738.17" + attribute \src "libresoc.v:128174.9-128174.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\si[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\si[15:0] \MUL_SI @@ -200787,20 +201125,26 @@ module \dec_bi$161 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:127748.3-127758.6" - process $proc$libresoc.v:127748$4951 + attribute \src "libresoc.v:128188.3-128206.6" + process $proc$libresoc.v:128188$4951 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:127749.5-127749.29" + attribute \src "libresoc.v:128189.5-128189.29" switch \initial - attribute \src "libresoc.v:127749.9-127749.17" + attribute \src "libresoc.v:128189.9-128189.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\si_hi[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\si_hi[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\si_hi[31:0] \$13 [31:0] @@ -200810,20 +201154,29 @@ module \dec_bi$161 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:127759.3-127769.6" - process $proc$libresoc.v:127759$4952 + attribute \src "libresoc.v:128207.3-128229.6" + process $proc$libresoc.v:128207$4952 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:127760.5-127760.29" + attribute \src "libresoc.v:128208.5-128208.29" switch \initial - attribute \src "libresoc.v:127760.9-127760.17" + attribute \src "libresoc.v:128208.9-128208.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\ui[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\ui[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\ui[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\ui[15:0] \MUL_UI @@ -200833,20 +201186,32 @@ module \dec_bi$161 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:127770.3-127780.6" - process $proc$libresoc.v:127770$4953 + attribute \src "libresoc.v:128230.3-128256.6" + process $proc$libresoc.v:128230$4953 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:127771.5-127771.29" + attribute \src "libresoc.v:128231.5-128231.29" switch \initial - attribute \src "libresoc.v:127771.9-127771.17" + attribute \src "libresoc.v:128231.9-128231.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\li[25:0] \$16 [25:0] @@ -200856,20 +201221,35 @@ module \dec_bi$161 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:127781.3-127791.6" - process $proc$libresoc.v:127781$4954 + attribute \src "libresoc.v:128257.3-128287.6" + process $proc$libresoc.v:128257$4954 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:127782.5-127782.29" + attribute \src "libresoc.v:128258.5-128258.29" switch \initial - attribute \src "libresoc.v:127782.9-127782.17" + attribute \src "libresoc.v:128258.9-128258.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\bd[15:0] \$19 [15:0] @@ -200879,20 +201259,38 @@ module \dec_bi$161 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:127792.3-127802.6" - process $proc$libresoc.v:127792$4955 + attribute \src "libresoc.v:128288.3-128322.6" + process $proc$libresoc.v:128288$4955 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:127793.5-127793.29" + attribute \src "libresoc.v:128289.5-128289.29" switch \initial - attribute \src "libresoc.v:127793.9-127793.17" + attribute \src "libresoc.v:128289.9-128289.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\ds[15:0] \$22 [15:0] @@ -200902,86 +201300,86 @@ module \dec_bi$161 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:127633$4936_Y - connect \$11 $pos$libresoc.v:127634$4938_Y - connect \$14 $sshl$libresoc.v:127635$4939_Y - connect \$17 $sshl$libresoc.v:127636$4940_Y - connect \$1 $pos$libresoc.v:127637$4942_Y - connect \$20 $sshl$libresoc.v:127638$4943_Y - connect \$23 $sshl$libresoc.v:127639$4944_Y - connect \$4 $sshl$libresoc.v:127640$4945_Y - connect \$3 $pos$libresoc.v:127641$4947_Y + connect \$9 $pos$libresoc.v:128069$4936_Y + connect \$11 $pos$libresoc.v:128070$4938_Y + connect \$14 $sshl$libresoc.v:128071$4939_Y + connect \$17 $sshl$libresoc.v:128072$4940_Y + connect \$1 $pos$libresoc.v:128073$4942_Y + connect \$20 $sshl$libresoc.v:128074$4943_Y + connect \$23 $sshl$libresoc.v:128075$4944_Y + connect \$4 $sshl$libresoc.v:128076$4945_Y + connect \$3 $pos$libresoc.v:128077$4947_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:127811.1-128064.10" +attribute \src "libresoc.v:128331.1-128668.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_bi" attribute \generator "nMigen" module \dec_bi$165 - attribute \src "libresoc.v:128038.3-128048.6" + attribute \src "libresoc.v:128598.3-128628.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:128049.3-128059.6" + attribute \src "libresoc.v:128629.3-128663.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:127900.3-127946.6" + attribute \src "libresoc.v:128420.3-128466.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:127947.3-127993.6" + attribute \src "libresoc.v:128467.3-128513.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:127812.7-127812.20" + attribute \src "libresoc.v:128332.7-128332.20" wire $0\initial[0:0] - attribute \src "libresoc.v:128027.3-128037.6" + attribute \src "libresoc.v:128571.3-128597.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:127994.3-128004.6" + attribute \src "libresoc.v:128514.3-128528.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:128005.3-128015.6" + attribute \src "libresoc.v:128529.3-128547.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:128016.3-128026.6" + attribute \src "libresoc.v:128548.3-128570.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:128038.3-128048.6" + attribute \src "libresoc.v:128598.3-128628.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:128049.3-128059.6" + attribute \src "libresoc.v:128629.3-128663.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:127900.3-127946.6" + attribute \src "libresoc.v:128420.3-128466.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:127947.3-127993.6" + attribute \src "libresoc.v:128467.3-128513.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:128027.3-128037.6" + attribute \src "libresoc.v:128571.3-128597.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:127994.3-128004.6" + attribute \src "libresoc.v:128514.3-128528.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:128005.3-128015.6" + attribute \src "libresoc.v:128529.3-128547.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:128016.3-128026.6" + attribute \src "libresoc.v:128548.3-128570.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:127890.17-127890.110" - wire width 64 $extend$libresoc.v:127890$4957_Y - attribute \src "libresoc.v:127891.18-127891.113" - wire width 64 $extend$libresoc.v:127891$4959_Y - attribute \src "libresoc.v:127894.17-127894.110" - wire width 64 $extend$libresoc.v:127894$4963_Y - attribute \src "libresoc.v:127898.17-127898.102" - wire width 64 $extend$libresoc.v:127898$4968_Y - attribute \src "libresoc.v:127890.17-127890.110" - wire width 64 $pos$libresoc.v:127890$4958_Y - attribute \src "libresoc.v:127891.18-127891.113" - wire width 64 $pos$libresoc.v:127891$4960_Y - attribute \src "libresoc.v:127894.17-127894.110" - wire width 64 $pos$libresoc.v:127894$4964_Y - attribute \src "libresoc.v:127898.17-127898.102" - wire width 64 $pos$libresoc.v:127898$4969_Y - attribute \src "libresoc.v:127892.18-127892.120" - wire width 47 $sshl$libresoc.v:127892$4961_Y - attribute \src "libresoc.v:127893.18-127893.119" - wire width 27 $sshl$libresoc.v:127893$4962_Y - attribute \src "libresoc.v:127895.18-127895.119" - wire width 17 $sshl$libresoc.v:127895$4965_Y - attribute \src "libresoc.v:127896.18-127896.119" - wire width 17 $sshl$libresoc.v:127896$4966_Y - attribute \src "libresoc.v:127897.17-127897.109" - wire width 47 $sshl$libresoc.v:127897$4967_Y + attribute \src "libresoc.v:128410.17-128410.110" + wire width 64 $extend$libresoc.v:128410$4957_Y + attribute \src "libresoc.v:128411.18-128411.113" + wire width 64 $extend$libresoc.v:128411$4959_Y + attribute \src "libresoc.v:128414.17-128414.110" + wire width 64 $extend$libresoc.v:128414$4963_Y + attribute \src "libresoc.v:128418.17-128418.102" + wire width 64 $extend$libresoc.v:128418$4968_Y + attribute \src "libresoc.v:128410.17-128410.110" + wire width 64 $pos$libresoc.v:128410$4958_Y + attribute \src "libresoc.v:128411.18-128411.113" + wire width 64 $pos$libresoc.v:128411$4960_Y + attribute \src "libresoc.v:128414.17-128414.110" + wire width 64 $pos$libresoc.v:128414$4964_Y + attribute \src "libresoc.v:128418.17-128418.102" + wire width 64 $pos$libresoc.v:128418$4969_Y + attribute \src "libresoc.v:128412.18-128412.120" + wire width 47 $sshl$libresoc.v:128412$4961_Y + attribute \src "libresoc.v:128413.18-128413.119" + wire width 27 $sshl$libresoc.v:128413$4962_Y + attribute \src "libresoc.v:128415.18-128415.119" + wire width 17 $sshl$libresoc.v:128415$4965_Y + attribute \src "libresoc.v:128416.18-128416.119" + wire width 17 $sshl$libresoc.v:128416$4966_Y + attribute \src "libresoc.v:128417.17-128417.109" + wire width 47 $sshl$libresoc.v:128417$4967_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" @@ -201032,7 +201430,7 @@ module \dec_bi$165 wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \imm_b_ok - attribute \src "libresoc.v:127812.7-127812.15" + attribute \src "libresoc.v:128332.7-128332.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" wire width 26 \li @@ -201060,71 +201458,71 @@ module \dec_bi$165 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" wire width 16 \ui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:127890$4957 + cell $pos $extend$libresoc.v:128410$4957 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \SHIFT_ROT_sh - connect \Y $extend$libresoc.v:127890$4957_Y + connect \Y $extend$libresoc.v:128410$4957_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:127891$4959 + cell $pos $extend$libresoc.v:128411$4959 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \SHIFT_ROT_SH32 - connect \Y $extend$libresoc.v:127891$4959_Y + connect \Y $extend$libresoc.v:128411$4959_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:127894$4963 + cell $pos $extend$libresoc.v:128414$4963 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \SHIFT_ROT_UI - connect \Y $extend$libresoc.v:127894$4963_Y + connect \Y $extend$libresoc.v:128414$4963_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - cell $pos $extend$libresoc.v:127898$4968 + cell $pos $extend$libresoc.v:128418$4968 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:127898$4968_Y + connect \Y $extend$libresoc.v:128418$4968_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:127890$4958 + cell $pos $pos$libresoc.v:128410$4958 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127890$4957_Y - connect \Y $pos$libresoc.v:127890$4958_Y + connect \A $extend$libresoc.v:128410$4957_Y + connect \Y $pos$libresoc.v:128410$4958_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:127891$4960 + cell $pos $pos$libresoc.v:128411$4960 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127891$4959_Y - connect \Y $pos$libresoc.v:127891$4960_Y + connect \A $extend$libresoc.v:128411$4959_Y + connect \Y $pos$libresoc.v:128411$4960_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:127894$4964 + cell $pos $pos$libresoc.v:128414$4964 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127894$4963_Y - connect \Y $pos$libresoc.v:127894$4964_Y + connect \A $extend$libresoc.v:128414$4963_Y + connect \Y $pos$libresoc.v:128414$4964_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - cell $pos $pos$libresoc.v:127898$4969 + cell $pos $pos$libresoc.v:128418$4969 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:127898$4968_Y - connect \Y $pos$libresoc.v:127898$4969_Y + connect \A $extend$libresoc.v:128418$4968_Y + connect \Y $pos$libresoc.v:128418$4969_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - cell $sshl $sshl$libresoc.v:127892$4961 + cell $sshl $sshl$libresoc.v:128412$4961 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -201132,10 +201530,10 @@ module \dec_bi$165 parameter \Y_WIDTH 47 connect \A \SHIFT_ROT_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:127892$4961_Y + connect \Y $sshl$libresoc.v:128412$4961_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" - cell $sshl $sshl$libresoc.v:127893$4962 + cell $sshl $sshl$libresoc.v:128413$4962 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -201143,10 +201541,10 @@ module \dec_bi$165 parameter \Y_WIDTH 27 connect \A \SHIFT_ROT_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:127893$4962_Y + connect \Y $sshl$libresoc.v:128413$4962_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" - cell $sshl $sshl$libresoc.v:127895$4965 + cell $sshl $sshl$libresoc.v:128415$4965 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -201154,10 +201552,10 @@ module \dec_bi$165 parameter \Y_WIDTH 17 connect \A \SHIFT_ROT_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:127895$4965_Y + connect \Y $sshl$libresoc.v:128415$4965_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" - cell $sshl $sshl$libresoc.v:127896$4966 + cell $sshl $sshl$libresoc.v:128416$4966 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -201165,10 +201563,10 @@ module \dec_bi$165 parameter \Y_WIDTH 17 connect \A \SHIFT_ROT_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:127896$4966_Y + connect \Y $sshl$libresoc.v:128416$4966_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - cell $sshl $sshl$libresoc.v:127897$4967 + cell $sshl $sshl$libresoc.v:128417$4967 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -201176,24 +201574,24 @@ module \dec_bi$165 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:127897$4967_Y + connect \Y $sshl$libresoc.v:128417$4967_Y end - attribute \src "libresoc.v:127812.7-127812.20" - process $proc$libresoc.v:127812$4978 + attribute \src "libresoc.v:128332.7-128332.20" + process $proc$libresoc.v:128332$4978 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:127900.3-127946.6" - process $proc$libresoc.v:127900$4970 + attribute \src "libresoc.v:128420.3-128466.6" + process $proc$libresoc.v:128420$4970 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:127901.5-127901.29" + attribute \src "libresoc.v:128421.5-128421.29" switch \initial - attribute \src "libresoc.v:127901.9-127901.17" + attribute \src "libresoc.v:128421.9-128421.17" case 1'1 case end @@ -201245,14 +201643,14 @@ module \dec_bi$165 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:127947.3-127993.6" - process $proc$libresoc.v:127947$4971 + attribute \src "libresoc.v:128467.3-128513.6" + process $proc$libresoc.v:128467$4971 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:127948.5-127948.29" + attribute \src "libresoc.v:128468.5-128468.29" switch \initial - attribute \src "libresoc.v:127948.9-127948.17" + attribute \src "libresoc.v:128468.9-128468.17" case 1'1 case end @@ -201304,20 +201702,23 @@ module \dec_bi$165 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:127994.3-128004.6" - process $proc$libresoc.v:127994$4972 + attribute \src "libresoc.v:128514.3-128528.6" + process $proc$libresoc.v:128514$4972 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:127995.5-127995.29" + attribute \src "libresoc.v:128515.5-128515.29" switch \initial - attribute \src "libresoc.v:127995.9-127995.17" + attribute \src "libresoc.v:128515.9-128515.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\si[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\si[15:0] \SHIFT_ROT_SI @@ -201327,20 +201728,26 @@ module \dec_bi$165 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:128005.3-128015.6" - process $proc$libresoc.v:128005$4973 + attribute \src "libresoc.v:128529.3-128547.6" + process $proc$libresoc.v:128529$4973 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:128006.5-128006.29" + attribute \src "libresoc.v:128530.5-128530.29" switch \initial - attribute \src "libresoc.v:128006.9-128006.17" + attribute \src "libresoc.v:128530.9-128530.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\si_hi[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\si_hi[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\si_hi[31:0] \$13 [31:0] @@ -201350,20 +201757,29 @@ module \dec_bi$165 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:128016.3-128026.6" - process $proc$libresoc.v:128016$4974 + attribute \src "libresoc.v:128548.3-128570.6" + process $proc$libresoc.v:128548$4974 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:128017.5-128017.29" + attribute \src "libresoc.v:128549.5-128549.29" switch \initial - attribute \src "libresoc.v:128017.9-128017.17" + attribute \src "libresoc.v:128549.9-128549.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\ui[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\ui[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\ui[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\ui[15:0] \SHIFT_ROT_UI @@ -201373,20 +201789,32 @@ module \dec_bi$165 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:128027.3-128037.6" - process $proc$libresoc.v:128027$4975 + attribute \src "libresoc.v:128571.3-128597.6" + process $proc$libresoc.v:128571$4975 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:128028.5-128028.29" + attribute \src "libresoc.v:128572.5-128572.29" switch \initial - attribute \src "libresoc.v:128028.9-128028.17" + attribute \src "libresoc.v:128572.9-128572.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\li[25:0] \$16 [25:0] @@ -201396,20 +201824,35 @@ module \dec_bi$165 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:128038.3-128048.6" - process $proc$libresoc.v:128038$4976 + attribute \src "libresoc.v:128598.3-128628.6" + process $proc$libresoc.v:128598$4976 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:128039.5-128039.29" + attribute \src "libresoc.v:128599.5-128599.29" switch \initial - attribute \src "libresoc.v:128039.9-128039.17" + attribute \src "libresoc.v:128599.9-128599.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\bd[15:0] \$19 [15:0] @@ -201419,20 +201862,38 @@ module \dec_bi$165 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:128049.3-128059.6" - process $proc$libresoc.v:128049$4977 + attribute \src "libresoc.v:128629.3-128663.6" + process $proc$libresoc.v:128629$4977 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:128050.5-128050.29" + attribute \src "libresoc.v:128630.5-128630.29" switch \initial - attribute \src "libresoc.v:128050.9-128050.17" + attribute \src "libresoc.v:128630.9-128630.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\ds[15:0] \$22 [15:0] @@ -201442,86 +201903,86 @@ module \dec_bi$165 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:127890$4958_Y - connect \$11 $pos$libresoc.v:127891$4960_Y - connect \$14 $sshl$libresoc.v:127892$4961_Y - connect \$17 $sshl$libresoc.v:127893$4962_Y - connect \$1 $pos$libresoc.v:127894$4964_Y - connect \$20 $sshl$libresoc.v:127895$4965_Y - connect \$23 $sshl$libresoc.v:127896$4966_Y - connect \$4 $sshl$libresoc.v:127897$4967_Y - connect \$3 $pos$libresoc.v:127898$4969_Y + connect \$9 $pos$libresoc.v:128410$4958_Y + connect \$11 $pos$libresoc.v:128411$4960_Y + connect \$14 $sshl$libresoc.v:128412$4961_Y + connect \$17 $sshl$libresoc.v:128413$4962_Y + connect \$1 $pos$libresoc.v:128414$4964_Y + connect \$20 $sshl$libresoc.v:128415$4965_Y + connect \$23 $sshl$libresoc.v:128416$4966_Y + connect \$4 $sshl$libresoc.v:128417$4967_Y + connect \$3 $pos$libresoc.v:128418$4969_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:128068.1-128321.10" +attribute \src "libresoc.v:128672.1-129009.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_bi" attribute \generator "nMigen" module \dec_bi$170 - attribute \src "libresoc.v:128295.3-128305.6" + attribute \src "libresoc.v:128939.3-128969.6" wire width 16 $0\bd[15:0] - attribute \src "libresoc.v:128306.3-128316.6" + attribute \src "libresoc.v:128970.3-129004.6" wire width 16 $0\ds[15:0] - attribute \src "libresoc.v:128157.3-128203.6" + attribute \src "libresoc.v:128761.3-128807.6" wire width 64 $0\imm_b[63:0] - attribute \src "libresoc.v:128204.3-128250.6" + attribute \src "libresoc.v:128808.3-128854.6" wire $0\imm_b_ok[0:0] - attribute \src "libresoc.v:128069.7-128069.20" + attribute \src "libresoc.v:128673.7-128673.20" wire $0\initial[0:0] - attribute \src "libresoc.v:128284.3-128294.6" + attribute \src "libresoc.v:128912.3-128938.6" wire width 26 $0\li[25:0] - attribute \src "libresoc.v:128251.3-128261.6" + attribute \src "libresoc.v:128855.3-128869.6" wire width 16 $0\si[15:0] - attribute \src "libresoc.v:128262.3-128272.6" + attribute \src "libresoc.v:128870.3-128888.6" wire width 32 $0\si_hi[31:0] - attribute \src "libresoc.v:128273.3-128283.6" + attribute \src "libresoc.v:128889.3-128911.6" wire width 16 $0\ui[15:0] - attribute \src "libresoc.v:128295.3-128305.6" + attribute \src "libresoc.v:128939.3-128969.6" wire width 16 $1\bd[15:0] - attribute \src "libresoc.v:128306.3-128316.6" + attribute \src "libresoc.v:128970.3-129004.6" wire width 16 $1\ds[15:0] - attribute \src "libresoc.v:128157.3-128203.6" + attribute \src "libresoc.v:128761.3-128807.6" wire width 64 $1\imm_b[63:0] - attribute \src "libresoc.v:128204.3-128250.6" + attribute \src "libresoc.v:128808.3-128854.6" wire $1\imm_b_ok[0:0] - attribute \src "libresoc.v:128284.3-128294.6" + attribute \src "libresoc.v:128912.3-128938.6" wire width 26 $1\li[25:0] - attribute \src "libresoc.v:128251.3-128261.6" + attribute \src "libresoc.v:128855.3-128869.6" wire width 16 $1\si[15:0] - attribute \src "libresoc.v:128262.3-128272.6" + attribute \src "libresoc.v:128870.3-128888.6" wire width 32 $1\si_hi[31:0] - attribute \src "libresoc.v:128273.3-128283.6" + attribute \src "libresoc.v:128889.3-128911.6" wire width 16 $1\ui[15:0] - attribute \src "libresoc.v:128147.17-128147.105" - wire width 64 $extend$libresoc.v:128147$4979_Y - attribute \src "libresoc.v:128148.18-128148.108" - wire width 64 $extend$libresoc.v:128148$4981_Y - attribute \src "libresoc.v:128151.17-128151.105" - wire width 64 $extend$libresoc.v:128151$4985_Y - attribute \src "libresoc.v:128155.17-128155.102" - wire width 64 $extend$libresoc.v:128155$4990_Y - attribute \src "libresoc.v:128147.17-128147.105" - wire width 64 $pos$libresoc.v:128147$4980_Y - attribute \src "libresoc.v:128148.18-128148.108" - wire width 64 $pos$libresoc.v:128148$4982_Y - attribute \src "libresoc.v:128151.17-128151.105" - wire width 64 $pos$libresoc.v:128151$4986_Y - attribute \src "libresoc.v:128155.17-128155.102" - wire width 64 $pos$libresoc.v:128155$4991_Y - attribute \src "libresoc.v:128149.18-128149.115" - wire width 47 $sshl$libresoc.v:128149$4983_Y - attribute \src "libresoc.v:128150.18-128150.114" - wire width 27 $sshl$libresoc.v:128150$4984_Y - attribute \src "libresoc.v:128152.18-128152.114" - wire width 17 $sshl$libresoc.v:128152$4987_Y - attribute \src "libresoc.v:128153.18-128153.114" - wire width 17 $sshl$libresoc.v:128153$4988_Y - attribute \src "libresoc.v:128154.17-128154.109" - wire width 47 $sshl$libresoc.v:128154$4989_Y + attribute \src "libresoc.v:128751.17-128751.105" + wire width 64 $extend$libresoc.v:128751$4979_Y + attribute \src "libresoc.v:128752.18-128752.108" + wire width 64 $extend$libresoc.v:128752$4981_Y + attribute \src "libresoc.v:128755.17-128755.105" + wire width 64 $extend$libresoc.v:128755$4985_Y + attribute \src "libresoc.v:128759.17-128759.102" + wire width 64 $extend$libresoc.v:128759$4990_Y + attribute \src "libresoc.v:128751.17-128751.105" + wire width 64 $pos$libresoc.v:128751$4980_Y + attribute \src "libresoc.v:128752.18-128752.108" + wire width 64 $pos$libresoc.v:128752$4982_Y + attribute \src "libresoc.v:128755.17-128755.105" + wire width 64 $pos$libresoc.v:128755$4986_Y + attribute \src "libresoc.v:128759.17-128759.102" + wire width 64 $pos$libresoc.v:128759$4991_Y + attribute \src "libresoc.v:128753.18-128753.115" + wire width 47 $sshl$libresoc.v:128753$4983_Y + attribute \src "libresoc.v:128754.18-128754.114" + wire width 27 $sshl$libresoc.v:128754$4984_Y + attribute \src "libresoc.v:128756.18-128756.114" + wire width 17 $sshl$libresoc.v:128756$4987_Y + attribute \src "libresoc.v:128757.18-128757.114" + wire width 17 $sshl$libresoc.v:128757$4988_Y + attribute \src "libresoc.v:128758.17-128758.109" + wire width 47 $sshl$libresoc.v:128758$4989_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" @@ -201572,7 +202033,7 @@ module \dec_bi$170 wire width 64 output 1 \imm_b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \imm_b_ok - attribute \src "libresoc.v:128069.7-128069.15" + attribute \src "libresoc.v:128673.7-128673.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" wire width 26 \li @@ -201600,71 +202061,71 @@ module \dec_bi$170 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" wire width 16 \ui attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:128147$4979 + cell $pos $extend$libresoc.v:128751$4979 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \LDST_sh - connect \Y $extend$libresoc.v:128147$4979_Y + connect \Y $extend$libresoc.v:128751$4979_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:128148$4981 + cell $pos $extend$libresoc.v:128752$4981 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 64 connect \A \LDST_SH32 - connect \Y $extend$libresoc.v:128148$4981_Y + connect \Y $extend$libresoc.v:128752$4981_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $extend$libresoc.v:128151$4985 + cell $pos $extend$libresoc.v:128755$4985 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \Y_WIDTH 64 connect \A \LDST_UI - connect \Y $extend$libresoc.v:128151$4985_Y + connect \Y $extend$libresoc.v:128755$4985_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - cell $pos $extend$libresoc.v:128155$4990 + cell $pos $extend$libresoc.v:128759$4990 parameter \A_SIGNED 0 parameter \A_WIDTH 47 parameter \Y_WIDTH 64 connect \A \$4 - connect \Y $extend$libresoc.v:128155$4990_Y + connect \Y $extend$libresoc.v:128759$4990_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:128147$4980 + cell $pos $pos$libresoc.v:128751$4980 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:128147$4979_Y - connect \Y $pos$libresoc.v:128147$4980_Y + connect \A $extend$libresoc.v:128751$4979_Y + connect \Y $pos$libresoc.v:128751$4980_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:128148$4982 + cell $pos $pos$libresoc.v:128752$4982 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:128148$4981_Y - connect \Y $pos$libresoc.v:128148$4982_Y + connect \A $extend$libresoc.v:128752$4981_Y + connect \Y $pos$libresoc.v:128752$4982_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" - cell $pos $pos$libresoc.v:128151$4986 + cell $pos $pos$libresoc.v:128755$4986 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:128151$4985_Y - connect \Y $pos$libresoc.v:128151$4986_Y + connect \A $extend$libresoc.v:128755$4985_Y + connect \Y $pos$libresoc.v:128755$4986_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - cell $pos $pos$libresoc.v:128155$4991 + cell $pos $pos$libresoc.v:128759$4991 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:128155$4990_Y - connect \Y $pos$libresoc.v:128155$4991_Y + connect \A $extend$libresoc.v:128759$4990_Y + connect \Y $pos$libresoc.v:128759$4991_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - cell $sshl $sshl$libresoc.v:128149$4983 + cell $sshl $sshl$libresoc.v:128753$4983 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -201672,10 +202133,10 @@ module \dec_bi$170 parameter \Y_WIDTH 47 connect \A \LDST_SI connect \B 5'10000 - connect \Y $sshl$libresoc.v:128149$4983_Y + connect \Y $sshl$libresoc.v:128753$4983_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:265" - cell $sshl $sshl$libresoc.v:128150$4984 + cell $sshl $sshl$libresoc.v:128754$4984 parameter \A_SIGNED 0 parameter \A_WIDTH 24 parameter \B_SIGNED 0 @@ -201683,10 +202144,10 @@ module \dec_bi$170 parameter \Y_WIDTH 27 connect \A \LDST_LI connect \B 2'10 - connect \Y $sshl$libresoc.v:128150$4984_Y + connect \Y $sshl$libresoc.v:128754$4984_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:270" - cell $sshl $sshl$libresoc.v:128152$4987 + cell $sshl $sshl$libresoc.v:128756$4987 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -201694,10 +202155,10 @@ module \dec_bi$170 parameter \Y_WIDTH 17 connect \A \LDST_BD connect \B 2'10 - connect \Y $sshl$libresoc.v:128152$4987_Y + connect \Y $sshl$libresoc.v:128756$4987_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275" - cell $sshl $sshl$libresoc.v:128153$4988 + cell $sshl $sshl$libresoc.v:128757$4988 parameter \A_SIGNED 0 parameter \A_WIDTH 14 parameter \B_SIGNED 0 @@ -201705,10 +202166,10 @@ module \dec_bi$170 parameter \Y_WIDTH 17 connect \A \LDST_DS connect \B 2'10 - connect \Y $sshl$libresoc.v:128153$4988_Y + connect \Y $sshl$libresoc.v:128757$4988_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - cell $sshl $sshl$libresoc.v:128154$4989 + cell $sshl $sshl$libresoc.v:128758$4989 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -201716,24 +202177,24 @@ module \dec_bi$170 parameter \Y_WIDTH 47 connect \A \ui connect \B 5'10000 - connect \Y $sshl$libresoc.v:128154$4989_Y + connect \Y $sshl$libresoc.v:128758$4989_Y end - attribute \src "libresoc.v:128069.7-128069.20" - process $proc$libresoc.v:128069$5000 + attribute \src "libresoc.v:128673.7-128673.20" + process $proc$libresoc.v:128673$5000 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:128157.3-128203.6" - process $proc$libresoc.v:128157$4992 + attribute \src "libresoc.v:128761.3-128807.6" + process $proc$libresoc.v:128761$4992 assign { } { } assign { } { } assign $0\imm_b[63:0] $1\imm_b[63:0] - attribute \src "libresoc.v:128158.5-128158.29" + attribute \src "libresoc.v:128762.5-128762.29" switch \initial - attribute \src "libresoc.v:128158.9-128158.17" + attribute \src "libresoc.v:128762.9-128762.17" case 1'1 case end @@ -201785,14 +202246,14 @@ module \dec_bi$170 sync always update \imm_b $0\imm_b[63:0] end - attribute \src "libresoc.v:128204.3-128250.6" - process $proc$libresoc.v:128204$4993 + attribute \src "libresoc.v:128808.3-128854.6" + process $proc$libresoc.v:128808$4993 assign { } { } assign { } { } assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] - attribute \src "libresoc.v:128205.5-128205.29" + attribute \src "libresoc.v:128809.5-128809.29" switch \initial - attribute \src "libresoc.v:128205.9-128205.17" + attribute \src "libresoc.v:128809.9-128809.17" case 1'1 case end @@ -201844,20 +202305,23 @@ module \dec_bi$170 sync always update \imm_b_ok $0\imm_b_ok[0:0] end - attribute \src "libresoc.v:128251.3-128261.6" - process $proc$libresoc.v:128251$4994 + attribute \src "libresoc.v:128855.3-128869.6" + process $proc$libresoc.v:128855$4994 assign { } { } assign { } { } assign $0\si[15:0] $1\si[15:0] - attribute \src "libresoc.v:128252.5-128252.29" + attribute \src "libresoc.v:128856.5-128856.29" switch \initial - attribute \src "libresoc.v:128252.9-128252.17" + attribute \src "libresoc.v:128856.9-128856.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\si[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0011 assign { } { } assign $1\si[15:0] \LDST_SI @@ -201867,20 +202331,26 @@ module \dec_bi$170 sync always update \si $0\si[15:0] end - attribute \src "libresoc.v:128262.3-128272.6" - process $proc$libresoc.v:128262$4995 + attribute \src "libresoc.v:128870.3-128888.6" + process $proc$libresoc.v:128870$4995 assign { } { } assign { } { } assign $0\si_hi[31:0] $1\si_hi[31:0] - attribute \src "libresoc.v:128263.5-128263.29" + attribute \src "libresoc.v:128871.5-128871.29" switch \initial - attribute \src "libresoc.v:128263.9-128263.17" + attribute \src "libresoc.v:128871.9-128871.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\si_hi[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\si_hi[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" case 4'0101 assign { } { } assign $1\si_hi[31:0] \$13 [31:0] @@ -201890,20 +202360,29 @@ module \dec_bi$170 sync always update \si_hi $0\si_hi[31:0] end - attribute \src "libresoc.v:128273.3-128283.6" - process $proc$libresoc.v:128273$4996 + attribute \src "libresoc.v:128889.3-128911.6" + process $proc$libresoc.v:128889$4996 assign { } { } assign { } { } assign $0\ui[15:0] $1\ui[15:0] - attribute \src "libresoc.v:128274.5-128274.29" + attribute \src "libresoc.v:128890.5-128890.29" switch \initial - attribute \src "libresoc.v:128274.9-128274.17" + attribute \src "libresoc.v:128890.9-128890.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\ui[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\ui[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\ui[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0100 assign { } { } assign $1\ui[15:0] \LDST_UI @@ -201913,20 +202392,32 @@ module \dec_bi$170 sync always update \ui $0\ui[15:0] end - attribute \src "libresoc.v:128284.3-128294.6" - process $proc$libresoc.v:128284$4997 + attribute \src "libresoc.v:128912.3-128938.6" + process $proc$libresoc.v:128912$4997 assign { } { } assign { } { } assign $0\li[25:0] $1\li[25:0] - attribute \src "libresoc.v:128285.5-128285.29" + attribute \src "libresoc.v:128913.5-128913.29" switch \initial - attribute \src "libresoc.v:128285.9-128285.17" + attribute \src "libresoc.v:128913.9-128913.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\li[25:0] 26'00000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0110 assign { } { } assign $1\li[25:0] \$16 [25:0] @@ -201936,20 +202427,35 @@ module \dec_bi$170 sync always update \li $0\li[25:0] end - attribute \src "libresoc.v:128295.3-128305.6" - process $proc$libresoc.v:128295$4998 + attribute \src "libresoc.v:128939.3-128969.6" + process $proc$libresoc.v:128939$4998 assign { } { } assign { } { } assign $0\bd[15:0] $1\bd[15:0] - attribute \src "libresoc.v:128296.5-128296.29" + attribute \src "libresoc.v:128940.5-128940.29" switch \initial - attribute \src "libresoc.v:128296.9-128296.17" + attribute \src "libresoc.v:128940.9-128940.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign $1\bd[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'0111 assign { } { } assign $1\bd[15:0] \$19 [15:0] @@ -201959,20 +202465,38 @@ module \dec_bi$170 sync always update \bd $0\bd[15:0] end - attribute \src "libresoc.v:128306.3-128316.6" - process $proc$libresoc.v:128306$4999 + attribute \src "libresoc.v:128970.3-129004.6" + process $proc$libresoc.v:128970$4999 assign { } { } assign { } { } assign $0\ds[15:0] $1\ds[15:0] - attribute \src "libresoc.v:128307.5-128307.29" + attribute \src "libresoc.v:128971.5-128971.29" switch \initial - attribute \src "libresoc.v:128307.9-128307.17" + attribute \src "libresoc.v:128971.9-128971.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 4'0010 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0011 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0101 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0100 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0110 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 4'0111 + assign $1\ds[15:0] 16'0000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 4'1000 assign { } { } assign $1\ds[15:0] \$22 [15:0] @@ -201982,41 +202506,41 @@ module \dec_bi$170 sync always update \ds $0\ds[15:0] end - connect \$9 $pos$libresoc.v:128147$4980_Y - connect \$11 $pos$libresoc.v:128148$4982_Y - connect \$14 $sshl$libresoc.v:128149$4983_Y - connect \$17 $sshl$libresoc.v:128150$4984_Y - connect \$1 $pos$libresoc.v:128151$4986_Y - connect \$20 $sshl$libresoc.v:128152$4987_Y - connect \$23 $sshl$libresoc.v:128153$4988_Y - connect \$4 $sshl$libresoc.v:128154$4989_Y - connect \$3 $pos$libresoc.v:128155$4991_Y + connect \$9 $pos$libresoc.v:128751$4980_Y + connect \$11 $pos$libresoc.v:128752$4982_Y + connect \$14 $sshl$libresoc.v:128753$4983_Y + connect \$17 $sshl$libresoc.v:128754$4984_Y + connect \$1 $pos$libresoc.v:128755$4986_Y + connect \$20 $sshl$libresoc.v:128756$4987_Y + connect \$23 $sshl$libresoc.v:128757$4988_Y + connect \$4 $sshl$libresoc.v:128758$4989_Y + connect \$3 $pos$libresoc.v:128759$4991_Y connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 connect \$13 \$14 connect \$16 \$17 connect \$19 \$20 connect \$22 \$23 end -attribute \src "libresoc.v:128325.1-128373.10" +attribute \src "libresoc.v:129013.1-129061.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_c" attribute \generator "nMigen" module \dec_c - attribute \src "libresoc.v:128326.7-128326.20" + attribute \src "libresoc.v:129014.7-129014.20" wire $0\initial[0:0] - attribute \src "libresoc.v:128343.3-128357.6" + attribute \src "libresoc.v:129031.3-129045.6" wire width 5 $0\reg_c[4:0] - attribute \src "libresoc.v:128358.3-128372.6" + attribute \src "libresoc.v:129046.3-129060.6" wire $0\reg_c_ok[0:0] - attribute \src "libresoc.v:128343.3-128357.6" + attribute \src "libresoc.v:129031.3-129045.6" wire width 5 $1\reg_c[4:0] - attribute \src "libresoc.v:128358.3-128372.6" + attribute \src "libresoc.v:129046.3-129060.6" wire $1\reg_c_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 4 \RB attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire width 5 input 3 \RS - attribute \src "libresoc.v:128326.7-128326.15" + attribute \src "libresoc.v:129014.7-129014.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 5 output 1 \reg_c @@ -202028,22 +202552,22 @@ module \dec_c attribute \enum_value_10 "RB" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:128326.7-128326.20" - process $proc$libresoc.v:128326$5003 + attribute \src "libresoc.v:129014.7-129014.20" + process $proc$libresoc.v:129014$5003 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:128343.3-128357.6" - process $proc$libresoc.v:128343$5001 + attribute \src "libresoc.v:129031.3-129045.6" + process $proc$libresoc.v:129031$5001 assign { } { } assign { } { } assign $0\reg_c[4:0] $1\reg_c[4:0] - attribute \src "libresoc.v:128344.5-128344.29" + attribute \src "libresoc.v:129032.5-129032.29" switch \initial - attribute \src "libresoc.v:128344.9-128344.17" + attribute \src "libresoc.v:129032.9-129032.17" case 1'1 case end @@ -202063,14 +202587,14 @@ module \dec_c sync always update \reg_c $0\reg_c[4:0] end - attribute \src "libresoc.v:128358.3-128372.6" - process $proc$libresoc.v:128358$5002 + attribute \src "libresoc.v:129046.3-129060.6" + process $proc$libresoc.v:129046$5002 assign { } { } assign { } { } assign $0\reg_c_ok[0:0] $1\reg_c_ok[0:0] - attribute \src "libresoc.v:128359.5-128359.29" + attribute \src "libresoc.v:129047.5-129047.29" switch \initial - attribute \src "libresoc.v:128359.9-128359.17" + attribute \src "libresoc.v:129047.9-129047.17" case 1'1 case end @@ -202091,69 +202615,69 @@ module \dec_c update \reg_c_ok $0\reg_c_ok[0:0] end end -attribute \src "libresoc.v:128377.1-128709.10" +attribute \src "libresoc.v:129065.1-129601.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in" attribute \generator "nMigen" module \dec_cr_in - attribute \src "libresoc.v:128629.3-128659.6" + attribute \src "libresoc.v:129421.3-129455.6" wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:128660.3-128670.6" + attribute \src "libresoc.v:129456.3-129486.6" wire width 3 $0\cr_bitfield_b[2:0] - attribute \src "libresoc.v:128562.3-128572.6" + attribute \src "libresoc.v:129254.3-129284.6" wire $0\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:128671.3-128681.6" + attribute \src "libresoc.v:129487.3-129517.6" wire width 3 $0\cr_bitfield_o[2:0] - attribute \src "libresoc.v:128592.3-128602.6" + attribute \src "libresoc.v:129332.3-129362.6" wire $0\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:128531.3-128561.6" + attribute \src "libresoc.v:129219.3-129253.6" wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:128573.3-128591.6" + attribute \src "libresoc.v:129285.3-129331.6" wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:128603.3-128613.6" + attribute \src "libresoc.v:129363.3-129401.6" wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:128378.7-128378.20" + attribute \src "libresoc.v:129066.7-129066.20" wire $0\initial[0:0] - attribute \src "libresoc.v:128682.3-128692.6" + attribute \src "libresoc.v:129518.3-129556.6" wire $0\move_one[0:0] - attribute \src "libresoc.v:128693.3-128708.6" + attribute \src "libresoc.v:129557.3-129600.6" wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:128614.3-128628.6" + attribute \src "libresoc.v:129402.3-129420.6" wire width 2 $0\sv_override[1:0] - attribute \src "libresoc.v:128629.3-128659.6" + attribute \src "libresoc.v:129421.3-129455.6" wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:128660.3-128670.6" + attribute \src "libresoc.v:129456.3-129486.6" wire width 3 $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:128562.3-128572.6" + attribute \src "libresoc.v:129254.3-129284.6" wire $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:128671.3-128681.6" + attribute \src "libresoc.v:129487.3-129517.6" wire width 3 $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:128592.3-128602.6" + attribute \src "libresoc.v:129332.3-129362.6" wire $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:128531.3-128561.6" + attribute \src "libresoc.v:129219.3-129253.6" wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:128573.3-128591.6" + attribute \src "libresoc.v:129285.3-129331.6" wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:128603.3-128613.6" + attribute \src "libresoc.v:129363.3-129401.6" wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:128682.3-128692.6" + attribute \src "libresoc.v:129518.3-129556.6" wire $1\move_one[0:0] - attribute \src "libresoc.v:128693.3-128708.6" + attribute \src "libresoc.v:129557.3-129600.6" wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:128614.3-128628.6" + attribute \src "libresoc.v:129402.3-129420.6" wire width 2 $1\sv_override[1:0] - attribute \src "libresoc.v:128573.3-128591.6" + attribute \src "libresoc.v:129285.3-129331.6" wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:128693.3-128708.6" + attribute \src "libresoc.v:129557.3-129600.6" wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:128524.17-128524.112" - wire $and$libresoc.v:128524$5005_Y - attribute \src "libresoc.v:128526.17-128526.112" - wire $and$libresoc.v:128526$5007_Y - attribute \src "libresoc.v:128523.17-128523.117" - wire $eq$libresoc.v:128523$5004_Y - attribute \src "libresoc.v:128525.17-128525.117" - wire $eq$libresoc.v:128525$5006_Y + attribute \src "libresoc.v:129212.17-129212.112" + wire $and$libresoc.v:129212$5005_Y + attribute \src "libresoc.v:129214.17-129214.112" + wire $and$libresoc.v:129214$5007_Y + attribute \src "libresoc.v:129211.17-129211.117" + wire $eq$libresoc.v:129211$5004_Y + attribute \src "libresoc.v:129213.17-129213.117" + wire $eq$libresoc.v:129213$5006_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" @@ -202192,7 +202716,7 @@ module \dec_cr_in wire width 8 output 3 \cr_fxm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 4 \cr_fxm_ok - attribute \src "libresoc.v:128378.7-128378.15" + attribute \src "libresoc.v:129066.7-129066.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:522" wire width 32 input 1 \insn_in @@ -202293,7 +202817,7 @@ module \dec_cr_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:527" wire width 2 \sv_override attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - cell $and $and$libresoc.v:128524$5005 + cell $and $and$libresoc.v:129212$5005 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -202301,10 +202825,10 @@ module \dec_cr_in parameter \Y_WIDTH 1 connect \A \$1 connect \B \move_one - connect \Y $and$libresoc.v:128524$5005_Y + connect \Y $and$libresoc.v:129212$5005_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - cell $and $and$libresoc.v:128526$5007 + cell $and $and$libresoc.v:129214$5007 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -202312,10 +202836,10 @@ module \dec_cr_in parameter \Y_WIDTH 1 connect \A \$5 connect \B \move_one - connect \Y $and$libresoc.v:128526$5007_Y + connect \Y $and$libresoc.v:129214$5007_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - cell $eq $eq$libresoc.v:128523$5004 + cell $eq $eq$libresoc.v:129211$5004 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -202323,10 +202847,10 @@ module \dec_cr_in parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0101101 - connect \Y $eq$libresoc.v:128523$5004_Y + connect \Y $eq$libresoc.v:129211$5004_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - cell $eq $eq$libresoc.v:128525$5006 + cell $eq $eq$libresoc.v:129213$5006 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -202334,36 +202858,39 @@ module \dec_cr_in parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0101101 - connect \Y $eq$libresoc.v:128525$5006_Y + connect \Y $eq$libresoc.v:129213$5006_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:128527.9-128530.4" + attribute \src "libresoc.v:129215.9-129218.4" cell \ppick \ppick connect \i \ppick_i connect \o \ppick_o end - attribute \src "libresoc.v:128378.7-128378.20" - process $proc$libresoc.v:128378$5019 + attribute \src "libresoc.v:129066.7-129066.20" + process $proc$libresoc.v:129066$5019 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:128531.3-128561.6" - process $proc$libresoc.v:128531$5008 + attribute \src "libresoc.v:129219.3-129253.6" + process $proc$libresoc.v:129219$5008 assign { } { } assign { } { } assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:128532.5-128532.29" + attribute \src "libresoc.v:129220.5-129220.29" switch \initial - attribute \src "libresoc.v:128532.9-128532.17" + attribute \src "libresoc.v:129220.9-129220.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\cr_bitfield_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } assign $1\cr_bitfield_ok[0:0] 1'1 @@ -202393,20 +202920,35 @@ module \dec_cr_in sync always update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:128562.3-128572.6" - process $proc$libresoc.v:128562$5009 + attribute \src "libresoc.v:129254.3-129284.6" + process $proc$libresoc.v:129254$5009 assign { } { } assign { } { } assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] - attribute \src "libresoc.v:128563.5-128563.29" + attribute \src "libresoc.v:129255.5-129255.29" switch \initial - attribute \src "libresoc.v:128563.9-128563.17" + attribute \src "libresoc.v:129255.9-129255.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\cr_bitfield_b_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\cr_bitfield_b_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'111 + assign $1\cr_bitfield_b_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\cr_bitfield_b_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\cr_bitfield_b_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\cr_bitfield_b_ok[0:0] 1'1 @@ -202416,20 +202958,41 @@ module \dec_cr_in sync always update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] end - attribute \src "libresoc.v:128573.3-128591.6" - process $proc$libresoc.v:128573$5010 + attribute \src "libresoc.v:129285.3-129331.6" + process $proc$libresoc.v:129285$5010 assign { } { } assign { } { } assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:128574.5-128574.29" + attribute \src "libresoc.v:129286.5-129286.29" switch \initial - attribute \src "libresoc.v:128574.9-128574.17" + attribute \src "libresoc.v:129286.9-129286.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\cr_fxm[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\cr_fxm[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'111 + assign $1\cr_fxm[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\cr_fxm[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\cr_fxm[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign $1\cr_fxm[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign $1\cr_fxm[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] @@ -202450,20 +203013,35 @@ module \dec_cr_in sync always update \cr_fxm $0\cr_fxm[7:0] end - attribute \src "libresoc.v:128592.3-128602.6" - process $proc$libresoc.v:128592$5011 + attribute \src "libresoc.v:129332.3-129362.6" + process $proc$libresoc.v:129332$5011 assign { } { } assign { } { } assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] - attribute \src "libresoc.v:128593.5-128593.29" + attribute \src "libresoc.v:129333.5-129333.29" switch \initial - attribute \src "libresoc.v:128593.9-128593.17" + attribute \src "libresoc.v:129333.9-129333.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\cr_bitfield_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\cr_bitfield_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'111 + assign $1\cr_bitfield_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\cr_bitfield_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\cr_bitfield_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\cr_bitfield_o_ok[0:0] 1'1 @@ -202473,20 +203051,41 @@ module \dec_cr_in sync always update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] end - attribute \src "libresoc.v:128603.3-128613.6" - process $proc$libresoc.v:128603$5012 + attribute \src "libresoc.v:129363.3-129401.6" + process $proc$libresoc.v:129363$5012 assign { } { } assign { } { } assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:128604.5-128604.29" + attribute \src "libresoc.v:129364.5-129364.29" switch \initial - attribute \src "libresoc.v:128604.9-128604.17" + attribute \src "libresoc.v:129364.9-129364.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\cr_fxm_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\cr_fxm_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'111 + assign $1\cr_fxm_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\cr_fxm_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\cr_fxm_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign $1\cr_fxm_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign $1\cr_fxm_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign $1\cr_fxm_ok[0:0] 1'1 @@ -202496,20 +203095,23 @@ module \dec_cr_in sync always update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:128614.3-128628.6" - process $proc$libresoc.v:128614$5013 + attribute \src "libresoc.v:129402.3-129420.6" + process $proc$libresoc.v:129402$5013 assign { } { } assign { } { } assign $0\sv_override[1:0] $1\sv_override[1:0] - attribute \src "libresoc.v:128615.5-128615.29" + attribute \src "libresoc.v:129403.5-129403.29" switch \initial - attribute \src "libresoc.v:128615.9-128615.17" + attribute \src "libresoc.v:129403.9-129403.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\sv_override[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } assign $1\sv_override[1:0] 2'01 @@ -202523,20 +203125,23 @@ module \dec_cr_in sync always update \sv_override $0\sv_override[1:0] end - attribute \src "libresoc.v:128629.3-128659.6" - process $proc$libresoc.v:128629$5014 + attribute \src "libresoc.v:129421.3-129455.6" + process $proc$libresoc.v:129421$5014 assign { } { } assign { } { } assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:128630.5-128630.29" + attribute \src "libresoc.v:129422.5-129422.29" switch \initial - attribute \src "libresoc.v:128630.9-128630.17" + attribute \src "libresoc.v:129422.9-129422.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } assign $1\cr_bitfield[2:0] 3'000 @@ -202566,20 +203171,35 @@ module \dec_cr_in sync always update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:128660.3-128670.6" - process $proc$libresoc.v:128660$5015 + attribute \src "libresoc.v:129456.3-129486.6" + process $proc$libresoc.v:129456$5015 assign { } { } assign { } { } assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] - attribute \src "libresoc.v:128661.5-128661.29" + attribute \src "libresoc.v:129457.5-129457.29" switch \initial - attribute \src "libresoc.v:128661.9-128661.17" + attribute \src "libresoc.v:129457.9-129457.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\cr_bitfield_b[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\cr_bitfield_b[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'111 + assign $1\cr_bitfield_b[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\cr_bitfield_b[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\cr_bitfield_b[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\cr_bitfield_b[2:0] \BB [4:2] @@ -202589,20 +203209,35 @@ module \dec_cr_in sync always update \cr_bitfield_b $0\cr_bitfield_b[2:0] end - attribute \src "libresoc.v:128671.3-128681.6" - process $proc$libresoc.v:128671$5016 + attribute \src "libresoc.v:129487.3-129517.6" + process $proc$libresoc.v:129487$5016 assign { } { } assign { } { } assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] - attribute \src "libresoc.v:128672.5-128672.29" + attribute \src "libresoc.v:129488.5-129488.29" switch \initial - attribute \src "libresoc.v:128672.9-128672.17" + attribute \src "libresoc.v:129488.9-129488.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\cr_bitfield_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\cr_bitfield_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'111 + assign $1\cr_bitfield_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\cr_bitfield_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\cr_bitfield_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\cr_bitfield_o[2:0] \BT [4:2] @@ -202612,20 +203247,41 @@ module \dec_cr_in sync always update \cr_bitfield_o $0\cr_bitfield_o[2:0] end - attribute \src "libresoc.v:128682.3-128692.6" - process $proc$libresoc.v:128682$5017 + attribute \src "libresoc.v:129518.3-129556.6" + process $proc$libresoc.v:129518$5017 assign { } { } assign { } { } assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:128683.5-128683.29" + attribute \src "libresoc.v:129519.5-129519.29" switch \initial - attribute \src "libresoc.v:128683.9-128683.17" + attribute \src "libresoc.v:129519.9-129519.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\move_one[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\move_one[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'111 + assign $1\move_one[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\move_one[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\move_one[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign $1\move_one[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign $1\move_one[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign $1\move_one[0:0] \insn_in [20] @@ -202635,20 +203291,41 @@ module \dec_cr_in sync always update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:128693.3-128708.6" - process $proc$libresoc.v:128693$5018 + attribute \src "libresoc.v:129557.3-129600.6" + process $proc$libresoc.v:129557$5018 assign { } { } assign { } { } assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:128694.5-128694.29" + attribute \src "libresoc.v:129558.5-129558.29" switch \initial - attribute \src "libresoc.v:128694.9-128694.17" + attribute \src "libresoc.v:129558.9-129558.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:544" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\ppick_i[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\ppick_i[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'111 + assign $1\ppick_i[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\ppick_i[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\ppick_i[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign $1\ppick_i[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign $1\ppick_i[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign $1\ppick_i[7:0] $2\ppick_i[7:0] @@ -202667,60 +203344,60 @@ module \dec_cr_in sync always update \ppick_i $0\ppick_i[7:0] end - connect \$1 $eq$libresoc.v:128523$5004_Y - connect \$3 $and$libresoc.v:128524$5005_Y - connect \$5 $eq$libresoc.v:128525$5006_Y - connect \$7 $and$libresoc.v:128526$5007_Y + connect \$1 $eq$libresoc.v:129211$5004_Y + connect \$3 $and$libresoc.v:129212$5005_Y + connect \$5 $eq$libresoc.v:129213$5006_Y + connect \$7 $and$libresoc.v:129214$5007_Y end -attribute \src "libresoc.v:128713.1-128983.10" +attribute \src "libresoc.v:129605.1-129967.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out" attribute \generator "nMigen" module \dec_cr_out - attribute \src "libresoc.v:128893.3-128915.6" + attribute \src "libresoc.v:129813.3-129839.6" wire width 3 $0\cr_bitfield[2:0] - attribute \src "libresoc.v:128844.3-128866.6" + attribute \src "libresoc.v:129736.3-129762.6" wire $0\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:128948.3-128982.6" + attribute \src "libresoc.v:129912.3-129966.6" wire width 8 $0\cr_fxm[7:0] - attribute \src "libresoc.v:128867.3-128877.6" + attribute \src "libresoc.v:129763.3-129793.6" wire $0\cr_fxm_ok[0:0] - attribute \src "libresoc.v:128714.7-128714.20" + attribute \src "libresoc.v:129606.7-129606.20" wire $0\initial[0:0] - attribute \src "libresoc.v:128916.3-128926.6" + attribute \src "libresoc.v:129840.3-129870.6" wire $0\move_one[0:0] - attribute \src "libresoc.v:128927.3-128947.6" + attribute \src "libresoc.v:129871.3-129911.6" wire width 8 $0\ppick_i[7:0] - attribute \src "libresoc.v:128878.3-128892.6" + attribute \src "libresoc.v:129794.3-129812.6" wire width 2 $0\sv_override[1:0] - attribute \src "libresoc.v:128893.3-128915.6" + attribute \src "libresoc.v:129813.3-129839.6" wire width 3 $1\cr_bitfield[2:0] - attribute \src "libresoc.v:128844.3-128866.6" + attribute \src "libresoc.v:129736.3-129762.6" wire $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:128948.3-128982.6" + attribute \src "libresoc.v:129912.3-129966.6" wire width 8 $1\cr_fxm[7:0] - attribute \src "libresoc.v:128867.3-128877.6" + attribute \src "libresoc.v:129763.3-129793.6" wire $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:128916.3-128926.6" + attribute \src "libresoc.v:129840.3-129870.6" wire $1\move_one[0:0] - attribute \src "libresoc.v:128927.3-128947.6" + attribute \src "libresoc.v:129871.3-129911.6" wire width 8 $1\ppick_i[7:0] - attribute \src "libresoc.v:128878.3-128892.6" + attribute \src "libresoc.v:129794.3-129812.6" wire width 2 $1\sv_override[1:0] - attribute \src "libresoc.v:128948.3-128982.6" + attribute \src "libresoc.v:129912.3-129966.6" wire width 8 $2\cr_fxm[7:0] - attribute \src "libresoc.v:128927.3-128947.6" + attribute \src "libresoc.v:129871.3-129911.6" wire width 8 $2\ppick_i[7:0] - attribute \src "libresoc.v:128948.3-128982.6" + attribute \src "libresoc.v:129912.3-129966.6" wire width 8 $3\cr_fxm[7:0] - attribute \src "libresoc.v:128927.3-128947.6" + attribute \src "libresoc.v:129871.3-129911.6" wire width 8 $3\ppick_i[7:0] - attribute \src "libresoc.v:128948.3-128982.6" + attribute \src "libresoc.v:129912.3-129966.6" wire width 8 $4\cr_fxm[7:0] - attribute \src "libresoc.v:128837.17-128837.117" - wire $eq$libresoc.v:128837$5020_Y - attribute \src "libresoc.v:128838.17-128838.117" - wire $eq$libresoc.v:128838$5021_Y + attribute \src "libresoc.v:129729.17-129729.117" + wire $eq$libresoc.v:129729$5020_Y + attribute \src "libresoc.v:129730.17-129730.117" + wire $eq$libresoc.v:129730$5021_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" @@ -202739,7 +203416,7 @@ module \dec_cr_out wire width 8 output 4 \cr_fxm attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 5 \cr_fxm_ok - attribute \src "libresoc.v:128714.7-128714.15" + attribute \src "libresoc.v:129606.7-129606.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:597" wire width 32 input 1 \insn_in @@ -202842,7 +203519,7 @@ module \dec_cr_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:600" wire width 2 \sv_override attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" - cell $eq $eq$libresoc.v:128837$5020 + cell $eq $eq$libresoc.v:129729$5020 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -202850,10 +203527,10 @@ module \dec_cr_out parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110000 - connect \Y $eq$libresoc.v:128837$5020_Y + connect \Y $eq$libresoc.v:129729$5020_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:640" - cell $eq $eq$libresoc.v:128838$5021 + cell $eq $eq$libresoc.v:129730$5021 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -202861,37 +203538,40 @@ module \dec_cr_out parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110000 - connect \Y $eq$libresoc.v:128838$5021_Y + connect \Y $eq$libresoc.v:129730$5021_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:128839.15-128843.4" + attribute \src "libresoc.v:129731.15-129735.4" cell \ppick$175 \ppick connect \en_o \ppick_en_o connect \i \ppick_i connect \o \ppick_o end - attribute \src "libresoc.v:128714.7-128714.20" - process $proc$libresoc.v:128714$5029 + attribute \src "libresoc.v:129606.7-129606.20" + process $proc$libresoc.v:129606$5029 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:128844.3-128866.6" - process $proc$libresoc.v:128844$5022 + attribute \src "libresoc.v:129736.3-129762.6" + process $proc$libresoc.v:129736$5022 assign { } { } assign { } { } assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] - attribute \src "libresoc.v:128845.5-128845.29" + attribute \src "libresoc.v:129737.5-129737.29" switch \initial - attribute \src "libresoc.v:128845.9-128845.17" + attribute \src "libresoc.v:129737.9-129737.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:619" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\cr_bitfield_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } assign $1\cr_bitfield_ok[0:0] \rc_in @@ -202913,20 +203593,35 @@ module \dec_cr_out sync always update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] end - attribute \src "libresoc.v:128867.3-128877.6" - process $proc$libresoc.v:128867$5023 + attribute \src "libresoc.v:129763.3-129793.6" + process $proc$libresoc.v:129763$5023 assign { } { } assign { } { } assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] - attribute \src "libresoc.v:128868.5-128868.29" + attribute \src "libresoc.v:129764.5-129764.29" switch \initial - attribute \src "libresoc.v:128868.9-128868.17" + attribute \src "libresoc.v:129764.9-129764.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:619" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\cr_fxm_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\cr_fxm_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign $1\cr_fxm_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\cr_fxm_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\cr_fxm_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\cr_fxm_ok[0:0] 1'1 @@ -202936,20 +203631,23 @@ module \dec_cr_out sync always update \cr_fxm_ok $0\cr_fxm_ok[0:0] end - attribute \src "libresoc.v:128878.3-128892.6" - process $proc$libresoc.v:128878$5024 + attribute \src "libresoc.v:129794.3-129812.6" + process $proc$libresoc.v:129794$5024 assign { } { } assign { } { } assign $0\sv_override[1:0] $1\sv_override[1:0] - attribute \src "libresoc.v:128879.5-128879.29" + attribute \src "libresoc.v:129795.5-129795.29" switch \initial - attribute \src "libresoc.v:128879.9-128879.17" + attribute \src "libresoc.v:129795.9-129795.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:619" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\sv_override[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } assign $1\sv_override[1:0] 2'01 @@ -202963,20 +203661,23 @@ module \dec_cr_out sync always update \sv_override $0\sv_override[1:0] end - attribute \src "libresoc.v:128893.3-128915.6" - process $proc$libresoc.v:128893$5025 + attribute \src "libresoc.v:129813.3-129839.6" + process $proc$libresoc.v:129813$5025 assign { } { } assign { } { } assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] - attribute \src "libresoc.v:128894.5-128894.29" + attribute \src "libresoc.v:129814.5-129814.29" switch \initial - attribute \src "libresoc.v:128894.9-128894.17" + attribute \src "libresoc.v:129814.9-129814.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:619" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } assign $1\cr_bitfield[2:0] 3'000 @@ -202998,20 +203699,35 @@ module \dec_cr_out sync always update \cr_bitfield $0\cr_bitfield[2:0] end - attribute \src "libresoc.v:128916.3-128926.6" - process $proc$libresoc.v:128916$5026 + attribute \src "libresoc.v:129840.3-129870.6" + process $proc$libresoc.v:129840$5026 assign { } { } assign { } { } assign $0\move_one[0:0] $1\move_one[0:0] - attribute \src "libresoc.v:128917.5-128917.29" + attribute \src "libresoc.v:129841.5-129841.29" switch \initial - attribute \src "libresoc.v:128917.9-128917.17" + attribute \src "libresoc.v:129841.9-129841.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:619" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\move_one[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\move_one[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign $1\move_one[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\move_one[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\move_one[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\move_one[0:0] \insn_in [20] @@ -203021,20 +203737,35 @@ module \dec_cr_out sync always update \move_one $0\move_one[0:0] end - attribute \src "libresoc.v:128927.3-128947.6" - process $proc$libresoc.v:128927$5027 + attribute \src "libresoc.v:129871.3-129911.6" + process $proc$libresoc.v:129871$5027 assign { } { } assign { } { } assign $0\ppick_i[7:0] $1\ppick_i[7:0] - attribute \src "libresoc.v:128928.5-128928.29" + attribute \src "libresoc.v:129872.5-129872.29" switch \initial - attribute \src "libresoc.v:128928.9-128928.17" + attribute \src "libresoc.v:129872.9-129872.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:619" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\ppick_i[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\ppick_i[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign $1\ppick_i[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\ppick_i[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\ppick_i[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\ppick_i[7:0] $2\ppick_i[7:0] @@ -203062,20 +203793,35 @@ module \dec_cr_out sync always update \ppick_i $0\ppick_i[7:0] end - attribute \src "libresoc.v:128948.3-128982.6" - process $proc$libresoc.v:128948$5028 + attribute \src "libresoc.v:129912.3-129966.6" + process $proc$libresoc.v:129912$5028 assign { } { } assign { } { } assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] - attribute \src "libresoc.v:128949.5-128949.29" + attribute \src "libresoc.v:129913.5-129913.29" switch \initial - attribute \src "libresoc.v:128949.9-128949.17" + attribute \src "libresoc.v:129913.9-129913.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:619" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\cr_fxm[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\cr_fxm[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign $1\cr_fxm[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\cr_fxm[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\cr_fxm[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] @@ -203118,74 +203864,74 @@ module \dec_cr_out sync always update \cr_fxm $0\cr_fxm[7:0] end - connect \$1 $eq$libresoc.v:128837$5020_Y - connect \$3 $eq$libresoc.v:128838$5021_Y + connect \$1 $eq$libresoc.v:129729$5020_Y + connect \$3 $eq$libresoc.v:129730$5021_Y end -attribute \src "libresoc.v:128987.1-129472.10" +attribute \src "libresoc.v:129971.1-130488.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o" attribute \generator "nMigen" module \dec_o - attribute \src "libresoc.v:129433.3-129471.6" + attribute \src "libresoc.v:130441.3-130487.6" wire width 3 $0\fast_o[2:0] - attribute \src "libresoc.v:129433.3-129471.6" + attribute \src "libresoc.v:130441.3-130487.6" wire $0\fast_o_ok[0:0] - attribute \src "libresoc.v:128988.7-128988.20" + attribute \src "libresoc.v:129972.7-129972.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129359.3-129373.6" + attribute \src "libresoc.v:130343.3-130357.6" wire width 5 $0\reg_o[4:0] - attribute \src "libresoc.v:129374.3-129388.6" + attribute \src "libresoc.v:130358.3-130372.6" wire $0\reg_o_ok[0:0] - attribute \src "libresoc.v:129389.3-129399.6" + attribute \src "libresoc.v:130373.3-130391.6" wire width 10 $0\spr[9:0] - attribute \src "libresoc.v:129416.3-129432.6" + attribute \src "libresoc.v:130416.3-130440.6" wire width 10 $0\spr_o[9:0] - attribute \src "libresoc.v:129416.3-129432.6" + attribute \src "libresoc.v:130416.3-130440.6" wire $0\spr_o_ok[0:0] - attribute \src "libresoc.v:129400.3-129415.6" + attribute \src "libresoc.v:130392.3-130415.6" wire width 10 $0\sprmap_spr_i[9:0] - attribute \src "libresoc.v:129433.3-129471.6" + attribute \src "libresoc.v:130441.3-130487.6" wire width 3 $1\fast_o[2:0] - attribute \src "libresoc.v:129433.3-129471.6" + attribute \src "libresoc.v:130441.3-130487.6" wire $1\fast_o_ok[0:0] - attribute \src "libresoc.v:129359.3-129373.6" + attribute \src "libresoc.v:130343.3-130357.6" wire width 5 $1\reg_o[4:0] - attribute \src "libresoc.v:129374.3-129388.6" + attribute \src "libresoc.v:130358.3-130372.6" wire $1\reg_o_ok[0:0] - attribute \src "libresoc.v:129389.3-129399.6" + attribute \src "libresoc.v:130373.3-130391.6" wire width 10 $1\spr[9:0] - attribute \src "libresoc.v:129416.3-129432.6" + attribute \src "libresoc.v:130416.3-130440.6" wire width 10 $1\spr_o[9:0] - attribute \src "libresoc.v:129416.3-129432.6" + attribute \src "libresoc.v:130416.3-130440.6" wire $1\spr_o_ok[0:0] - attribute \src "libresoc.v:129400.3-129415.6" + attribute \src "libresoc.v:130392.3-130415.6" wire width 10 $1\sprmap_spr_i[9:0] - attribute \src "libresoc.v:129433.3-129471.6" + attribute \src "libresoc.v:130441.3-130487.6" wire width 3 $2\fast_o[2:0] - attribute \src "libresoc.v:129433.3-129471.6" + attribute \src "libresoc.v:130441.3-130487.6" wire $2\fast_o_ok[0:0] - attribute \src "libresoc.v:129416.3-129432.6" + attribute \src "libresoc.v:130416.3-130440.6" wire width 10 $2\spr_o[9:0] - attribute \src "libresoc.v:129416.3-129432.6" + attribute \src "libresoc.v:130416.3-130440.6" wire $2\spr_o_ok[0:0] - attribute \src "libresoc.v:129400.3-129415.6" + attribute \src "libresoc.v:130392.3-130415.6" wire width 10 $2\sprmap_spr_i[9:0] - attribute \src "libresoc.v:129433.3-129471.6" + attribute \src "libresoc.v:130441.3-130487.6" wire width 3 $3\fast_o[2:0] - attribute \src "libresoc.v:129433.3-129471.6" + attribute \src "libresoc.v:130441.3-130487.6" wire $3\fast_o_ok[0:0] - attribute \src "libresoc.v:129433.3-129471.6" + attribute \src "libresoc.v:130441.3-130487.6" wire width 3 $4\fast_o[2:0] - attribute \src "libresoc.v:129433.3-129471.6" + attribute \src "libresoc.v:130441.3-130487.6" wire $4\fast_o_ok[0:0] - attribute \src "libresoc.v:129348.17-129348.117" - wire $eq$libresoc.v:129348$5030_Y - attribute \src "libresoc.v:129349.17-129349.117" - wire $eq$libresoc.v:129349$5031_Y - attribute \src "libresoc.v:129350.17-129350.117" - wire $eq$libresoc.v:129350$5032_Y - attribute \src "libresoc.v:129351.17-129351.104" - wire $not$libresoc.v:129351$5033_Y + attribute \src "libresoc.v:130332.17-130332.117" + wire $eq$libresoc.v:130332$5030_Y + attribute \src "libresoc.v:130333.17-130333.117" + wire $eq$libresoc.v:130333$5031_Y + attribute \src "libresoc.v:130334.17-130334.117" + wire $eq$libresoc.v:130334$5032_Y + attribute \src "libresoc.v:130335.17-130335.104" + wire $not$libresoc.v:130335$5033_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355" @@ -203206,7 +203952,7 @@ module \dec_o wire width 3 output 7 \fast_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 8 \fast_o_ok - attribute \src "libresoc.v:128988.7-128988.15" + attribute \src "libresoc.v:129972.7-129972.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -203542,7 +204288,7 @@ module \dec_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \sprmap_spr_o_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355" - cell $eq $eq$libresoc.v:129348$5030 + cell $eq $eq$libresoc.v:130332$5030 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -203550,10 +204296,10 @@ module \dec_o parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:129348$5030_Y + connect \Y $eq$libresoc.v:130332$5030_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355" - cell $eq $eq$libresoc.v:129349$5031 + cell $eq $eq$libresoc.v:130333$5031 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -203561,10 +204307,10 @@ module \dec_o parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:129349$5031_Y + connect \Y $eq$libresoc.v:130333$5031_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:355" - cell $eq $eq$libresoc.v:129350$5032 + cell $eq $eq$libresoc.v:130334$5032 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -203572,18 +204318,18 @@ module \dec_o parameter \Y_WIDTH 1 connect \A \internal_op connect \B 7'0110001 - connect \Y $eq$libresoc.v:129350$5032_Y + connect \Y $eq$libresoc.v:130334$5032_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:365" - cell $not $not$libresoc.v:129351$5033 + cell $not $not$libresoc.v:130335$5033 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \BO [2] - connect \Y $not$libresoc.v:129351$5033_Y + connect \Y $not$libresoc.v:130335$5033_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:129352.16-129358.4" + attribute \src "libresoc.v:130336.16-130342.4" cell \sprmap$174 \sprmap connect \fast_o \sprmap_fast_o connect \fast_o_ok \sprmap_fast_o_ok @@ -203591,22 +204337,22 @@ module \dec_o connect \spr_o \sprmap_spr_o connect \spr_o_ok \sprmap_spr_o_ok end - attribute \src "libresoc.v:128988.7-128988.20" - process $proc$libresoc.v:128988$5040 + attribute \src "libresoc.v:129972.7-129972.20" + process $proc$libresoc.v:129972$5040 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129359.3-129373.6" - process $proc$libresoc.v:129359$5034 + attribute \src "libresoc.v:130343.3-130357.6" + process $proc$libresoc.v:130343$5034 assign { } { } assign { } { } assign $0\reg_o[4:0] $1\reg_o[4:0] - attribute \src "libresoc.v:129360.5-129360.29" + attribute \src "libresoc.v:130344.5-130344.29" switch \initial - attribute \src "libresoc.v:129360.9-129360.17" + attribute \src "libresoc.v:130344.9-130344.17" case 1'1 case end @@ -203626,14 +204372,14 @@ module \dec_o sync always update \reg_o $0\reg_o[4:0] end - attribute \src "libresoc.v:129374.3-129388.6" - process $proc$libresoc.v:129374$5035 + attribute \src "libresoc.v:130358.3-130372.6" + process $proc$libresoc.v:130358$5035 assign { } { } assign { } { } assign $0\reg_o_ok[0:0] $1\reg_o_ok[0:0] - attribute \src "libresoc.v:129375.5-129375.29" + attribute \src "libresoc.v:130359.5-130359.29" switch \initial - attribute \src "libresoc.v:129375.9-129375.17" + attribute \src "libresoc.v:130359.9-130359.17" case 1'1 case end @@ -203653,20 +204399,26 @@ module \dec_o sync always update \reg_o_ok $0\reg_o_ok[0:0] end - attribute \src "libresoc.v:129389.3-129399.6" - process $proc$libresoc.v:129389$5036 + attribute \src "libresoc.v:130373.3-130391.6" + process $proc$libresoc.v:130373$5036 assign { } { } assign { } { } assign $0\spr[9:0] $1\spr[9:0] - attribute \src "libresoc.v:129390.5-129390.29" + attribute \src "libresoc.v:130374.5-130374.29" switch \initial - attribute \src "libresoc.v:129390.9-129390.17" + attribute \src "libresoc.v:130374.9-130374.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\spr[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\spr[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } assign $1\spr[9:0] { \SPR [4:0] \SPR [9:5] } @@ -203676,20 +204428,26 @@ module \dec_o sync always update \spr $0\spr[9:0] end - attribute \src "libresoc.v:129400.3-129415.6" - process $proc$libresoc.v:129400$5037 + attribute \src "libresoc.v:130392.3-130415.6" + process $proc$libresoc.v:130392$5037 assign { } { } assign { } { } assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] - attribute \src "libresoc.v:129401.5-129401.29" + attribute \src "libresoc.v:130393.5-130393.29" switch \initial - attribute \src "libresoc.v:129401.9-129401.17" + attribute \src "libresoc.v:130393.9-130393.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\sprmap_spr_i[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\sprmap_spr_i[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } assign $1\sprmap_spr_i[9:0] $2\sprmap_spr_i[9:0] @@ -203708,23 +204466,31 @@ module \dec_o sync always update \sprmap_spr_i $0\sprmap_spr_i[9:0] end - attribute \src "libresoc.v:129416.3-129432.6" - process $proc$libresoc.v:129416$5038 + attribute \src "libresoc.v:130416.3-130440.6" + process $proc$libresoc.v:130416$5038 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\spr_o[9:0] $1\spr_o[9:0] assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] - attribute \src "libresoc.v:129417.5-129417.29" + attribute \src "libresoc.v:130417.5-130417.29" switch \initial - attribute \src "libresoc.v:129417.9-129417.17" + attribute \src "libresoc.v:130417.9-130417.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\spr_o[9:0] 10'0000000000 + assign $1\spr_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\spr_o[9:0] 10'0000000000 + assign $1\spr_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } assign { } { } @@ -203749,8 +204515,8 @@ module \dec_o update \spr_o $0\spr_o[9:0] update \spr_o_ok $0\spr_o_ok[0:0] end - attribute \src "libresoc.v:129433.3-129471.6" - process $proc$libresoc.v:129433$5039 + attribute \src "libresoc.v:130441.3-130487.6" + process $proc$libresoc.v:130441$5039 assign { } { } assign { } { } assign { } { } @@ -203759,15 +204525,23 @@ module \dec_o assign { } { } assign $0\fast_o[2:0] $3\fast_o[2:0] assign $0\fast_o_ok[0:0] $3\fast_o_ok[0:0] - attribute \src "libresoc.v:129434.5-129434.29" + attribute \src "libresoc.v:130442.5-130442.29" switch \initial - attribute \src "libresoc.v:129434.9-129434.17" + attribute \src "libresoc.v:130442.9-130442.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:344" switch \sel_in attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\fast_o[2:0] 3'000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\fast_o[2:0] 3'000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } assign { } { } @@ -203822,42 +204596,42 @@ module \dec_o update \fast_o $0\fast_o[2:0] update \fast_o_ok $0\fast_o_ok[0:0] end - connect \$1 $eq$libresoc.v:129348$5030_Y - connect \$3 $eq$libresoc.v:129349$5031_Y - connect \$5 $eq$libresoc.v:129350$5032_Y - connect \$7 $not$libresoc.v:129351$5033_Y + connect \$1 $eq$libresoc.v:130332$5030_Y + connect \$3 $eq$libresoc.v:130333$5031_Y + connect \$5 $eq$libresoc.v:130334$5032_Y + connect \$7 $not$libresoc.v:130335$5033_Y end -attribute \src "libresoc.v:129476.1-129644.10" +attribute \src "libresoc.v:130492.1-130660.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o2" attribute \generator "nMigen" module \dec_o2 - attribute \src "libresoc.v:129604.3-129623.6" + attribute \src "libresoc.v:130620.3-130639.6" wire width 3 $0\fast_o2[2:0] - attribute \src "libresoc.v:129624.3-129643.6" + attribute \src "libresoc.v:130640.3-130659.6" wire $0\fast_o2_ok[0:0] - attribute \src "libresoc.v:129477.7-129477.20" + attribute \src "libresoc.v:130493.7-130493.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129584.3-129593.6" + attribute \src "libresoc.v:130600.3-130609.6" wire width 5 $0\reg_o2[4:0] - attribute \src "libresoc.v:129594.3-129603.6" + attribute \src "libresoc.v:130610.3-130619.6" wire $0\reg_o2_ok[0:0] - attribute \src "libresoc.v:129604.3-129623.6" + attribute \src "libresoc.v:130620.3-130639.6" wire width 3 $1\fast_o2[2:0] - attribute \src "libresoc.v:129624.3-129643.6" + attribute \src "libresoc.v:130640.3-130659.6" wire $1\fast_o2_ok[0:0] - attribute \src "libresoc.v:129584.3-129593.6" + attribute \src "libresoc.v:130600.3-130609.6" wire width 5 $1\reg_o2[4:0] - attribute \src "libresoc.v:129594.3-129603.6" + attribute \src "libresoc.v:130610.3-130619.6" wire $1\reg_o2_ok[0:0] - attribute \src "libresoc.v:129604.3-129623.6" + attribute \src "libresoc.v:130620.3-130639.6" wire width 3 $2\fast_o2[2:0] - attribute \src "libresoc.v:129624.3-129643.6" + attribute \src "libresoc.v:130640.3-130659.6" wire $2\fast_o2_ok[0:0] - attribute \src "libresoc.v:129582.17-129582.108" - wire $eq$libresoc.v:129582$5041_Y - attribute \src "libresoc.v:129583.17-129583.108" - wire $eq$libresoc.v:129583$5042_Y + attribute \src "libresoc.v:130598.17-130598.108" + wire $eq$libresoc.v:130598$5041_Y + attribute \src "libresoc.v:130599.17-130599.108" + wire $eq$libresoc.v:130599$5042_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:411" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:411" @@ -203868,7 +204642,7 @@ module \dec_o2 wire width 3 output 4 \fast_o2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 5 \fast_o2_ok - attribute \src "libresoc.v:129477.7-129477.15" + attribute \src "libresoc.v:130493.7-130493.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -203961,7 +204735,7 @@ module \dec_o2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 2 input 6 \upd attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:411" - cell $eq $eq$libresoc.v:129582$5041 + cell $eq $eq$libresoc.v:130598$5041 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -203969,10 +204743,10 @@ module \dec_o2 parameter \Y_WIDTH 1 connect \A \upd connect \B 2'01 - connect \Y $eq$libresoc.v:129582$5041_Y + connect \Y $eq$libresoc.v:130598$5041_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:411" - cell $eq $eq$libresoc.v:129583$5042 + cell $eq $eq$libresoc.v:130599$5042 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -203980,24 +204754,24 @@ module \dec_o2 parameter \Y_WIDTH 1 connect \A \upd connect \B 2'01 - connect \Y $eq$libresoc.v:129583$5042_Y + connect \Y $eq$libresoc.v:130599$5042_Y end - attribute \src "libresoc.v:129477.7-129477.20" - process $proc$libresoc.v:129477$5047 + attribute \src "libresoc.v:130493.7-130493.20" + process $proc$libresoc.v:130493$5047 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129584.3-129593.6" - process $proc$libresoc.v:129584$5043 + attribute \src "libresoc.v:130600.3-130609.6" + process $proc$libresoc.v:130600$5043 assign { } { } assign { } { } assign $0\reg_o2[4:0] $1\reg_o2[4:0] - attribute \src "libresoc.v:129585.5-129585.29" + attribute \src "libresoc.v:130601.5-130601.29" switch \initial - attribute \src "libresoc.v:129585.9-129585.17" + attribute \src "libresoc.v:130601.9-130601.17" case 1'1 case end @@ -204013,14 +204787,14 @@ module \dec_o2 sync always update \reg_o2 $0\reg_o2[4:0] end - attribute \src "libresoc.v:129594.3-129603.6" - process $proc$libresoc.v:129594$5044 + attribute \src "libresoc.v:130610.3-130619.6" + process $proc$libresoc.v:130610$5044 assign { } { } assign { } { } assign $0\reg_o2_ok[0:0] $1\reg_o2_ok[0:0] - attribute \src "libresoc.v:129595.5-129595.29" + attribute \src "libresoc.v:130611.5-130611.29" switch \initial - attribute \src "libresoc.v:129595.9-129595.17" + attribute \src "libresoc.v:130611.9-130611.17" case 1'1 case end @@ -204036,14 +204810,14 @@ module \dec_o2 sync always update \reg_o2_ok $0\reg_o2_ok[0:0] end - attribute \src "libresoc.v:129604.3-129623.6" - process $proc$libresoc.v:129604$5045 + attribute \src "libresoc.v:130620.3-130639.6" + process $proc$libresoc.v:130620$5045 assign { } { } assign { } { } assign $0\fast_o2[2:0] $1\fast_o2[2:0] - attribute \src "libresoc.v:129605.5-129605.29" + attribute \src "libresoc.v:130621.5-130621.29" switch \initial - attribute \src "libresoc.v:129605.9-129605.17" + attribute \src "libresoc.v:130621.9-130621.17" case 1'1 case end @@ -204072,14 +204846,14 @@ module \dec_o2 sync always update \fast_o2 $0\fast_o2[2:0] end - attribute \src "libresoc.v:129624.3-129643.6" - process $proc$libresoc.v:129624$5046 + attribute \src "libresoc.v:130640.3-130659.6" + process $proc$libresoc.v:130640$5046 assign { } { } assign { } { } assign $0\fast_o2_ok[0:0] $1\fast_o2_ok[0:0] - attribute \src "libresoc.v:129625.5-129625.29" + attribute \src "libresoc.v:130641.5-130641.29" switch \initial - attribute \src "libresoc.v:129625.9-129625.17" + attribute \src "libresoc.v:130641.9-130641.17" case 1'1 case end @@ -204108,27 +204882,27 @@ module \dec_o2 sync always update \fast_o2_ok $0\fast_o2_ok[0:0] end - connect \$1 $eq$libresoc.v:129582$5041_Y - connect \$3 $eq$libresoc.v:129583$5042_Y + connect \$1 $eq$libresoc.v:130598$5041_Y + connect \$3 $eq$libresoc.v:130599$5042_Y end -attribute \src "libresoc.v:129648.1-129783.10" +attribute \src "libresoc.v:130664.1-130799.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_oe" attribute \generator "nMigen" module \dec_oe - attribute \src "libresoc.v:129649.7-129649.20" + attribute \src "libresoc.v:130665.7-130665.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129741.3-129761.6" + attribute \src "libresoc.v:130757.3-130777.6" wire $0\oe[0:0] - attribute \src "libresoc.v:129762.3-129782.6" + attribute \src "libresoc.v:130778.3-130798.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:129741.3-129761.6" + attribute \src "libresoc.v:130757.3-130777.6" wire $1\oe[0:0] - attribute \src "libresoc.v:129762.3-129782.6" + attribute \src "libresoc.v:130778.3-130798.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:129741.3-129761.6" + attribute \src "libresoc.v:130757.3-130777.6" wire $2\oe[0:0] - attribute \src "libresoc.v:129762.3-129782.6" + attribute \src "libresoc.v:130778.3-130798.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 4 \ALU_OE @@ -204209,7 +204983,7 @@ module \dec_oe attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \ALU_internal_op - attribute \src "libresoc.v:129649.7-129649.15" + attribute \src "libresoc.v:130665.7-130665.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \oe @@ -204221,22 +204995,22 @@ module \dec_oe attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:129649.7-129649.20" - process $proc$libresoc.v:129649$5050 + attribute \src "libresoc.v:130665.7-130665.20" + process $proc$libresoc.v:130665$5050 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129741.3-129761.6" - process $proc$libresoc.v:129741$5048 + attribute \src "libresoc.v:130757.3-130777.6" + process $proc$libresoc.v:130757$5048 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:129742.5-129742.29" + attribute \src "libresoc.v:130758.5-130758.29" switch \initial - attribute \src "libresoc.v:129742.9-129742.17" + attribute \src "libresoc.v:130758.9-130758.17" case 1'1 case end @@ -204262,14 +205036,14 @@ module \dec_oe sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:129762.3-129782.6" - process $proc$libresoc.v:129762$5049 + attribute \src "libresoc.v:130778.3-130798.6" + process $proc$libresoc.v:130778$5049 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:129763.5-129763.29" + attribute \src "libresoc.v:130779.5-130779.29" switch \initial - attribute \src "libresoc.v:129763.9-129763.17" + attribute \src "libresoc.v:130779.9-130779.17" case 1'1 case end @@ -204296,24 +205070,24 @@ module \dec_oe update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:129787.1-129920.10" +attribute \src "libresoc.v:130803.1-130936.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_oe" attribute \generator "nMigen" module \dec_oe$140 - attribute \src "libresoc.v:129788.7-129788.20" + attribute \src "libresoc.v:130804.7-130804.20" wire $0\initial[0:0] - attribute \src "libresoc.v:129878.3-129898.6" + attribute \src "libresoc.v:130894.3-130914.6" wire $0\oe[0:0] - attribute \src "libresoc.v:129899.3-129919.6" + attribute \src "libresoc.v:130915.3-130935.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:129878.3-129898.6" + attribute \src "libresoc.v:130894.3-130914.6" wire $1\oe[0:0] - attribute \src "libresoc.v:129899.3-129919.6" + attribute \src "libresoc.v:130915.3-130935.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:129878.3-129898.6" + attribute \src "libresoc.v:130894.3-130914.6" wire $2\oe[0:0] - attribute \src "libresoc.v:129899.3-129919.6" + attribute \src "libresoc.v:130915.3-130935.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 2 \CR_OE @@ -204394,7 +205168,7 @@ module \dec_oe$140 attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \CR_internal_op - attribute \src "libresoc.v:129788.7-129788.15" + attribute \src "libresoc.v:130804.7-130804.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \oe @@ -204406,22 +205180,22 @@ module \dec_oe$140 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 input 3 \sel_in - attribute \src "libresoc.v:129788.7-129788.20" - process $proc$libresoc.v:129788$5053 + attribute \src "libresoc.v:130804.7-130804.20" + process $proc$libresoc.v:130804$5053 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:129878.3-129898.6" - process $proc$libresoc.v:129878$5051 + attribute \src "libresoc.v:130894.3-130914.6" + process $proc$libresoc.v:130894$5051 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:129879.5-129879.29" + attribute \src "libresoc.v:130895.5-130895.29" switch \initial - attribute \src "libresoc.v:129879.9-129879.17" + attribute \src "libresoc.v:130895.9-130895.17" case 1'1 case end @@ -204447,14 +205221,14 @@ module \dec_oe$140 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:129899.3-129919.6" - process $proc$libresoc.v:129899$5052 + attribute \src "libresoc.v:130915.3-130935.6" + process $proc$libresoc.v:130915$5052 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:129900.5-129900.29" + attribute \src "libresoc.v:130916.5-130916.29" switch \initial - attribute \src "libresoc.v:129900.9-129900.17" + attribute \src "libresoc.v:130916.9-130916.17" case 1'1 case end @@ -204481,24 +205255,24 @@ module \dec_oe$140 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:129924.1-130057.10" +attribute \src "libresoc.v:130940.1-131073.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_oe" attribute \generator "nMigen" module \dec_oe$143 - attribute \src "libresoc.v:129925.7-129925.20" + attribute \src "libresoc.v:130941.7-130941.20" wire $0\initial[0:0] - attribute \src "libresoc.v:130015.3-130035.6" + attribute \src "libresoc.v:131031.3-131051.6" wire $0\oe[0:0] - attribute \src "libresoc.v:130036.3-130056.6" + attribute \src "libresoc.v:131052.3-131072.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:130015.3-130035.6" + attribute \src "libresoc.v:131031.3-131051.6" wire $1\oe[0:0] - attribute \src "libresoc.v:130036.3-130056.6" + attribute \src "libresoc.v:131052.3-131072.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:130015.3-130035.6" + attribute \src "libresoc.v:131031.3-131051.6" wire $2\oe[0:0] - attribute \src "libresoc.v:130036.3-130056.6" + attribute \src "libresoc.v:131052.3-131072.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 2 \BRANCH_OE @@ -204579,7 +205353,7 @@ module \dec_oe$143 attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \BRANCH_internal_op - attribute \src "libresoc.v:129925.7-129925.15" + attribute \src "libresoc.v:130941.7-130941.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \oe @@ -204591,22 +205365,22 @@ module \dec_oe$143 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 input 3 \sel_in - attribute \src "libresoc.v:129925.7-129925.20" - process $proc$libresoc.v:129925$5056 + attribute \src "libresoc.v:130941.7-130941.20" + process $proc$libresoc.v:130941$5056 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:130015.3-130035.6" - process $proc$libresoc.v:130015$5054 + attribute \src "libresoc.v:131031.3-131051.6" + process $proc$libresoc.v:131031$5054 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:130016.5-130016.29" + attribute \src "libresoc.v:131032.5-131032.29" switch \initial - attribute \src "libresoc.v:130016.9-130016.17" + attribute \src "libresoc.v:131032.9-131032.17" case 1'1 case end @@ -204632,14 +205406,14 @@ module \dec_oe$143 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:130036.3-130056.6" - process $proc$libresoc.v:130036$5055 + attribute \src "libresoc.v:131052.3-131072.6" + process $proc$libresoc.v:131052$5055 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:130037.5-130037.29" + attribute \src "libresoc.v:131053.5-131053.29" switch \initial - attribute \src "libresoc.v:130037.9-130037.17" + attribute \src "libresoc.v:131053.9-131053.17" case 1'1 case end @@ -204666,24 +205440,24 @@ module \dec_oe$143 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:130061.1-130196.10" +attribute \src "libresoc.v:131077.1-131212.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_oe" attribute \generator "nMigen" module \dec_oe$147 - attribute \src "libresoc.v:130062.7-130062.20" + attribute \src "libresoc.v:131078.7-131078.20" wire $0\initial[0:0] - attribute \src "libresoc.v:130154.3-130174.6" + attribute \src "libresoc.v:131170.3-131190.6" wire $0\oe[0:0] - attribute \src "libresoc.v:130175.3-130195.6" + attribute \src "libresoc.v:131191.3-131211.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:130154.3-130174.6" + attribute \src "libresoc.v:131170.3-131190.6" wire $1\oe[0:0] - attribute \src "libresoc.v:130175.3-130195.6" + attribute \src "libresoc.v:131191.3-131211.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:130154.3-130174.6" + attribute \src "libresoc.v:131170.3-131190.6" wire $2\oe[0:0] - attribute \src "libresoc.v:130175.3-130195.6" + attribute \src "libresoc.v:131191.3-131211.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 4 \LOGICAL_OE @@ -204764,7 +205538,7 @@ module \dec_oe$147 attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \LOGICAL_internal_op - attribute \src "libresoc.v:130062.7-130062.15" + attribute \src "libresoc.v:131078.7-131078.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \oe @@ -204776,22 +205550,22 @@ module \dec_oe$147 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:130062.7-130062.20" - process $proc$libresoc.v:130062$5059 + attribute \src "libresoc.v:131078.7-131078.20" + process $proc$libresoc.v:131078$5059 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:130154.3-130174.6" - process $proc$libresoc.v:130154$5057 + attribute \src "libresoc.v:131170.3-131190.6" + process $proc$libresoc.v:131170$5057 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:130155.5-130155.29" + attribute \src "libresoc.v:131171.5-131171.29" switch \initial - attribute \src "libresoc.v:130155.9-130155.17" + attribute \src "libresoc.v:131171.9-131171.17" case 1'1 case end @@ -204817,14 +205591,14 @@ module \dec_oe$147 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:130175.3-130195.6" - process $proc$libresoc.v:130175$5058 + attribute \src "libresoc.v:131191.3-131211.6" + process $proc$libresoc.v:131191$5058 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:130176.5-130176.29" + attribute \src "libresoc.v:131192.5-131192.29" switch \initial - attribute \src "libresoc.v:130176.9-130176.17" + attribute \src "libresoc.v:131192.9-131192.17" case 1'1 case end @@ -204851,24 +205625,24 @@ module \dec_oe$147 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:130200.1-130333.10" +attribute \src "libresoc.v:131216.1-131349.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_oe" attribute \generator "nMigen" module \dec_oe$152 - attribute \src "libresoc.v:130201.7-130201.20" + attribute \src "libresoc.v:131217.7-131217.20" wire $0\initial[0:0] - attribute \src "libresoc.v:130291.3-130311.6" + attribute \src "libresoc.v:131307.3-131327.6" wire $0\oe[0:0] - attribute \src "libresoc.v:130312.3-130332.6" + attribute \src "libresoc.v:131328.3-131348.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:130291.3-130311.6" + attribute \src "libresoc.v:131307.3-131327.6" wire $1\oe[0:0] - attribute \src "libresoc.v:130312.3-130332.6" + attribute \src "libresoc.v:131328.3-131348.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:130291.3-130311.6" + attribute \src "libresoc.v:131307.3-131327.6" wire $2\oe[0:0] - attribute \src "libresoc.v:130312.3-130332.6" + attribute \src "libresoc.v:131328.3-131348.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 2 \SPR_OE @@ -204949,7 +205723,7 @@ module \dec_oe$152 attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \SPR_internal_op - attribute \src "libresoc.v:130201.7-130201.15" + attribute \src "libresoc.v:131217.7-131217.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \oe @@ -204961,22 +205735,22 @@ module \dec_oe$152 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 input 3 \sel_in - attribute \src "libresoc.v:130201.7-130201.20" - process $proc$libresoc.v:130201$5062 + attribute \src "libresoc.v:131217.7-131217.20" + process $proc$libresoc.v:131217$5062 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:130291.3-130311.6" - process $proc$libresoc.v:130291$5060 + attribute \src "libresoc.v:131307.3-131327.6" + process $proc$libresoc.v:131307$5060 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:130292.5-130292.29" + attribute \src "libresoc.v:131308.5-131308.29" switch \initial - attribute \src "libresoc.v:130292.9-130292.17" + attribute \src "libresoc.v:131308.9-131308.17" case 1'1 case end @@ -205002,14 +205776,14 @@ module \dec_oe$152 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:130312.3-130332.6" - process $proc$libresoc.v:130312$5061 + attribute \src "libresoc.v:131328.3-131348.6" + process $proc$libresoc.v:131328$5061 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:130313.5-130313.29" + attribute \src "libresoc.v:131329.5-131329.29" switch \initial - attribute \src "libresoc.v:130313.9-130313.17" + attribute \src "libresoc.v:131329.9-131329.17" case 1'1 case end @@ -205036,24 +205810,24 @@ module \dec_oe$152 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:130337.1-130472.10" +attribute \src "libresoc.v:131353.1-131488.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_oe" attribute \generator "nMigen" module \dec_oe$155 - attribute \src "libresoc.v:130338.7-130338.20" + attribute \src "libresoc.v:131354.7-131354.20" wire $0\initial[0:0] - attribute \src "libresoc.v:130430.3-130450.6" + attribute \src "libresoc.v:131446.3-131466.6" wire $0\oe[0:0] - attribute \src "libresoc.v:130451.3-130471.6" + attribute \src "libresoc.v:131467.3-131487.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:130430.3-130450.6" + attribute \src "libresoc.v:131446.3-131466.6" wire $1\oe[0:0] - attribute \src "libresoc.v:130451.3-130471.6" + attribute \src "libresoc.v:131467.3-131487.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:130430.3-130450.6" + attribute \src "libresoc.v:131446.3-131466.6" wire $2\oe[0:0] - attribute \src "libresoc.v:130451.3-130471.6" + attribute \src "libresoc.v:131467.3-131487.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 4 \DIV_OE @@ -205134,7 +205908,7 @@ module \dec_oe$155 attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \DIV_internal_op - attribute \src "libresoc.v:130338.7-130338.15" + attribute \src "libresoc.v:131354.7-131354.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \oe @@ -205146,22 +205920,22 @@ module \dec_oe$155 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:130338.7-130338.20" - process $proc$libresoc.v:130338$5065 + attribute \src "libresoc.v:131354.7-131354.20" + process $proc$libresoc.v:131354$5065 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:130430.3-130450.6" - process $proc$libresoc.v:130430$5063 + attribute \src "libresoc.v:131446.3-131466.6" + process $proc$libresoc.v:131446$5063 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:130431.5-130431.29" + attribute \src "libresoc.v:131447.5-131447.29" switch \initial - attribute \src "libresoc.v:130431.9-130431.17" + attribute \src "libresoc.v:131447.9-131447.17" case 1'1 case end @@ -205187,14 +205961,14 @@ module \dec_oe$155 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:130451.3-130471.6" - process $proc$libresoc.v:130451$5064 + attribute \src "libresoc.v:131467.3-131487.6" + process $proc$libresoc.v:131467$5064 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:130452.5-130452.29" + attribute \src "libresoc.v:131468.5-131468.29" switch \initial - attribute \src "libresoc.v:130452.9-130452.17" + attribute \src "libresoc.v:131468.9-131468.17" case 1'1 case end @@ -205221,24 +205995,24 @@ module \dec_oe$155 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:130476.1-130611.10" +attribute \src "libresoc.v:131492.1-131627.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_oe" attribute \generator "nMigen" module \dec_oe$160 - attribute \src "libresoc.v:130477.7-130477.20" + attribute \src "libresoc.v:131493.7-131493.20" wire $0\initial[0:0] - attribute \src "libresoc.v:130569.3-130589.6" + attribute \src "libresoc.v:131585.3-131605.6" wire $0\oe[0:0] - attribute \src "libresoc.v:130590.3-130610.6" + attribute \src "libresoc.v:131606.3-131626.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:130569.3-130589.6" + attribute \src "libresoc.v:131585.3-131605.6" wire $1\oe[0:0] - attribute \src "libresoc.v:130590.3-130610.6" + attribute \src "libresoc.v:131606.3-131626.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:130569.3-130589.6" + attribute \src "libresoc.v:131585.3-131605.6" wire $2\oe[0:0] - attribute \src "libresoc.v:130590.3-130610.6" + attribute \src "libresoc.v:131606.3-131626.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 4 \MUL_OE @@ -205319,7 +206093,7 @@ module \dec_oe$160 attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \MUL_internal_op - attribute \src "libresoc.v:130477.7-130477.15" + attribute \src "libresoc.v:131493.7-131493.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \oe @@ -205331,22 +206105,22 @@ module \dec_oe$160 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:130477.7-130477.20" - process $proc$libresoc.v:130477$5068 + attribute \src "libresoc.v:131493.7-131493.20" + process $proc$libresoc.v:131493$5068 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:130569.3-130589.6" - process $proc$libresoc.v:130569$5066 + attribute \src "libresoc.v:131585.3-131605.6" + process $proc$libresoc.v:131585$5066 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:130570.5-130570.29" + attribute \src "libresoc.v:131586.5-131586.29" switch \initial - attribute \src "libresoc.v:130570.9-130570.17" + attribute \src "libresoc.v:131586.9-131586.17" case 1'1 case end @@ -205372,14 +206146,14 @@ module \dec_oe$160 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:130590.3-130610.6" - process $proc$libresoc.v:130590$5067 + attribute \src "libresoc.v:131606.3-131626.6" + process $proc$libresoc.v:131606$5067 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:130591.5-130591.29" + attribute \src "libresoc.v:131607.5-131607.29" switch \initial - attribute \src "libresoc.v:130591.9-130591.17" + attribute \src "libresoc.v:131607.9-131607.17" case 1'1 case end @@ -205406,24 +206180,24 @@ module \dec_oe$160 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:130615.1-130750.10" +attribute \src "libresoc.v:131631.1-131766.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_oe" attribute \generator "nMigen" module \dec_oe$164 - attribute \src "libresoc.v:130616.7-130616.20" + attribute \src "libresoc.v:131632.7-131632.20" wire $0\initial[0:0] - attribute \src "libresoc.v:130708.3-130728.6" + attribute \src "libresoc.v:131724.3-131744.6" wire $0\oe[0:0] - attribute \src "libresoc.v:130729.3-130749.6" + attribute \src "libresoc.v:131745.3-131765.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:130708.3-130728.6" + attribute \src "libresoc.v:131724.3-131744.6" wire $1\oe[0:0] - attribute \src "libresoc.v:130729.3-130749.6" + attribute \src "libresoc.v:131745.3-131765.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:130708.3-130728.6" + attribute \src "libresoc.v:131724.3-131744.6" wire $2\oe[0:0] - attribute \src "libresoc.v:130729.3-130749.6" + attribute \src "libresoc.v:131745.3-131765.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 4 \SHIFT_ROT_OE @@ -205504,7 +206278,7 @@ module \dec_oe$164 attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \SHIFT_ROT_internal_op - attribute \src "libresoc.v:130616.7-130616.15" + attribute \src "libresoc.v:131632.7-131632.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \oe @@ -205516,22 +206290,22 @@ module \dec_oe$164 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:130616.7-130616.20" - process $proc$libresoc.v:130616$5071 + attribute \src "libresoc.v:131632.7-131632.20" + process $proc$libresoc.v:131632$5071 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:130708.3-130728.6" - process $proc$libresoc.v:130708$5069 + attribute \src "libresoc.v:131724.3-131744.6" + process $proc$libresoc.v:131724$5069 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:130709.5-130709.29" + attribute \src "libresoc.v:131725.5-131725.29" switch \initial - attribute \src "libresoc.v:130709.9-130709.17" + attribute \src "libresoc.v:131725.9-131725.17" case 1'1 case end @@ -205557,14 +206331,14 @@ module \dec_oe$164 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:130729.3-130749.6" - process $proc$libresoc.v:130729$5070 + attribute \src "libresoc.v:131745.3-131765.6" + process $proc$libresoc.v:131745$5070 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:130730.5-130730.29" + attribute \src "libresoc.v:131746.5-131746.29" switch \initial - attribute \src "libresoc.v:130730.9-130730.17" + attribute \src "libresoc.v:131746.9-131746.17" case 1'1 case end @@ -205591,24 +206365,24 @@ module \dec_oe$164 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:130754.1-130889.10" +attribute \src "libresoc.v:131770.1-131905.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_oe" attribute \generator "nMigen" module \dec_oe$168 - attribute \src "libresoc.v:130755.7-130755.20" + attribute \src "libresoc.v:131771.7-131771.20" wire $0\initial[0:0] - attribute \src "libresoc.v:130847.3-130867.6" + attribute \src "libresoc.v:131863.3-131883.6" wire $0\oe[0:0] - attribute \src "libresoc.v:130868.3-130888.6" + attribute \src "libresoc.v:131884.3-131904.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:130847.3-130867.6" + attribute \src "libresoc.v:131863.3-131883.6" wire $1\oe[0:0] - attribute \src "libresoc.v:130868.3-130888.6" + attribute \src "libresoc.v:131884.3-131904.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:130847.3-130867.6" + attribute \src "libresoc.v:131863.3-131883.6" wire $2\oe[0:0] - attribute \src "libresoc.v:130868.3-130888.6" + attribute \src "libresoc.v:131884.3-131904.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 4 \LDST_OE @@ -205689,7 +206463,7 @@ module \dec_oe$168 attribute \enum_value_1001100 "OP_SETVL" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:189" wire width 7 input 1 \LDST_internal_op - attribute \src "libresoc.v:130755.7-130755.15" + attribute \src "libresoc.v:131771.7-131771.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \oe @@ -205701,22 +206475,22 @@ module \dec_oe$168 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:130755.7-130755.20" - process $proc$libresoc.v:130755$5074 + attribute \src "libresoc.v:131771.7-131771.20" + process $proc$libresoc.v:131771$5074 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:130847.3-130867.6" - process $proc$libresoc.v:130847$5072 + attribute \src "libresoc.v:131863.3-131883.6" + process $proc$libresoc.v:131863$5072 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:130848.5-130848.29" + attribute \src "libresoc.v:131864.5-131864.29" switch \initial - attribute \src "libresoc.v:130848.9-130848.17" + attribute \src "libresoc.v:131864.9-131864.17" case 1'1 case end @@ -205742,14 +206516,14 @@ module \dec_oe$168 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:130868.3-130888.6" - process $proc$libresoc.v:130868$5073 + attribute \src "libresoc.v:131884.3-131904.6" + process $proc$libresoc.v:131884$5073 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:130869.5-130869.29" + attribute \src "libresoc.v:131885.5-131885.29" switch \initial - attribute \src "libresoc.v:130869.9-130869.17" + attribute \src "libresoc.v:131885.9-131885.17" case 1'1 case end @@ -205776,28 +206550,28 @@ module \dec_oe$168 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:130893.1-131028.10" +attribute \src "libresoc.v:131909.1-132044.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_oe" attribute \generator "nMigen" module \dec_oe$173 - attribute \src "libresoc.v:130894.7-130894.20" + attribute \src "libresoc.v:131910.7-131910.20" wire $0\initial[0:0] - attribute \src "libresoc.v:130986.3-131006.6" + attribute \src "libresoc.v:132002.3-132022.6" wire $0\oe[0:0] - attribute \src "libresoc.v:131007.3-131027.6" + attribute \src "libresoc.v:132023.3-132043.6" wire $0\oe_ok[0:0] - attribute \src "libresoc.v:130986.3-131006.6" + attribute \src "libresoc.v:132002.3-132022.6" wire $1\oe[0:0] - attribute \src "libresoc.v:131007.3-131027.6" + attribute \src "libresoc.v:132023.3-132043.6" wire $1\oe_ok[0:0] - attribute \src "libresoc.v:130986.3-131006.6" + attribute \src "libresoc.v:132002.3-132022.6" wire $2\oe[0:0] - attribute \src "libresoc.v:131007.3-131027.6" + attribute \src "libresoc.v:132023.3-132043.6" wire $2\oe_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 4 \OE - attribute \src "libresoc.v:130894.7-130894.15" + attribute \src "libresoc.v:131910.7-131910.15" wire \initial attribute \enum_base_type "MicrOp" attribute \enum_value_0000000 "OP_ILLEGAL" @@ -205886,22 +206660,22 @@ module \dec_oe$173 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:478" wire width 2 input 5 \sel_in - attribute \src "libresoc.v:130894.7-130894.20" - process $proc$libresoc.v:130894$5077 + attribute \src "libresoc.v:131910.7-131910.20" + process $proc$libresoc.v:131910$5077 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:130986.3-131006.6" - process $proc$libresoc.v:130986$5075 + attribute \src "libresoc.v:132002.3-132022.6" + process $proc$libresoc.v:132002$5075 assign { } { } assign { } { } assign $0\oe[0:0] $1\oe[0:0] - attribute \src "libresoc.v:130987.5-130987.29" + attribute \src "libresoc.v:132003.5-132003.29" switch \initial - attribute \src "libresoc.v:130987.9-130987.17" + attribute \src "libresoc.v:132003.9-132003.17" case 1'1 case end @@ -205927,14 +206701,14 @@ module \dec_oe$173 sync always update \oe $0\oe[0:0] end - attribute \src "libresoc.v:131007.3-131027.6" - process $proc$libresoc.v:131007$5076 + attribute \src "libresoc.v:132023.3-132043.6" + process $proc$libresoc.v:132023$5076 assign { } { } assign { } { } assign $0\oe_ok[0:0] $1\oe_ok[0:0] - attribute \src "libresoc.v:131008.5-131008.29" + attribute \src "libresoc.v:132024.5-132024.29" switch \initial - attribute \src "libresoc.v:131008.9-131008.17" + attribute \src "libresoc.v:132024.9-132024.17" case 1'1 case end @@ -205961,24 +206735,24 @@ module \dec_oe$173 update \oe_ok $0\oe_ok[0:0] end end -attribute \src "libresoc.v:131032.1-131086.10" +attribute \src "libresoc.v:132048.1-132102.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_ALU.dec_rc" attribute \generator "nMigen" module \dec_rc - attribute \src "libresoc.v:131033.7-131033.20" + attribute \src "libresoc.v:132049.7-132049.20" wire $0\initial[0:0] - attribute \src "libresoc.v:131048.3-131066.6" + attribute \src "libresoc.v:132064.3-132082.6" wire $0\rc[0:0] - attribute \src "libresoc.v:131067.3-131085.6" + attribute \src "libresoc.v:132083.3-132101.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:131048.3-131066.6" + attribute \src "libresoc.v:132064.3-132082.6" wire $1\rc[0:0] - attribute \src "libresoc.v:131067.3-131085.6" + attribute \src "libresoc.v:132083.3-132101.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 3 \ALU_Rc - attribute \src "libresoc.v:131033.7-131033.15" + attribute \src "libresoc.v:132049.7-132049.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc @@ -205990,22 +206764,22 @@ module \dec_rc attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:131033.7-131033.20" - process $proc$libresoc.v:131033$5080 + attribute \src "libresoc.v:132049.7-132049.20" + process $proc$libresoc.v:132049$5080 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:131048.3-131066.6" - process $proc$libresoc.v:131048$5078 + attribute \src "libresoc.v:132064.3-132082.6" + process $proc$libresoc.v:132064$5078 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:131049.5-131049.29" + attribute \src "libresoc.v:132065.5-132065.29" switch \initial - attribute \src "libresoc.v:131049.9-131049.17" + attribute \src "libresoc.v:132065.9-132065.17" case 1'1 case end @@ -206029,14 +206803,14 @@ module \dec_rc sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:131067.3-131085.6" - process $proc$libresoc.v:131067$5079 + attribute \src "libresoc.v:132083.3-132101.6" + process $proc$libresoc.v:132083$5079 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:131068.5-131068.29" + attribute \src "libresoc.v:132084.5-132084.29" switch \initial - attribute \src "libresoc.v:131068.9-131068.17" + attribute \src "libresoc.v:132084.9-132084.17" case 1'1 case end @@ -206061,24 +206835,24 @@ module \dec_rc update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:131090.1-131142.10" +attribute \src "libresoc.v:132106.1-132158.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_CR.dec_rc" attribute \generator "nMigen" module \dec_rc$139 - attribute \src "libresoc.v:131091.7-131091.20" + attribute \src "libresoc.v:132107.7-132107.20" wire $0\initial[0:0] - attribute \src "libresoc.v:131104.3-131122.6" + attribute \src "libresoc.v:132120.3-132138.6" wire $0\rc[0:0] - attribute \src "libresoc.v:131123.3-131141.6" + attribute \src "libresoc.v:132139.3-132157.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:131104.3-131122.6" + attribute \src "libresoc.v:132120.3-132138.6" wire $1\rc[0:0] - attribute \src "libresoc.v:131123.3-131141.6" + attribute \src "libresoc.v:132139.3-132157.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 1 \CR_Rc - attribute \src "libresoc.v:131091.7-131091.15" + attribute \src "libresoc.v:132107.7-132107.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \rc @@ -206090,22 +206864,22 @@ module \dec_rc$139 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 input 2 \sel_in - attribute \src "libresoc.v:131091.7-131091.20" - process $proc$libresoc.v:131091$5083 + attribute \src "libresoc.v:132107.7-132107.20" + process $proc$libresoc.v:132107$5083 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:131104.3-131122.6" - process $proc$libresoc.v:131104$5081 + attribute \src "libresoc.v:132120.3-132138.6" + process $proc$libresoc.v:132120$5081 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:131105.5-131105.29" + attribute \src "libresoc.v:132121.5-132121.29" switch \initial - attribute \src "libresoc.v:131105.9-131105.17" + attribute \src "libresoc.v:132121.9-132121.17" case 1'1 case end @@ -206129,14 +206903,14 @@ module \dec_rc$139 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:131123.3-131141.6" - process $proc$libresoc.v:131123$5082 + attribute \src "libresoc.v:132139.3-132157.6" + process $proc$libresoc.v:132139$5082 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:131124.5-131124.29" + attribute \src "libresoc.v:132140.5-132140.29" switch \initial - attribute \src "libresoc.v:131124.9-131124.17" + attribute \src "libresoc.v:132140.9-132140.17" case 1'1 case end @@ -206161,24 +206935,24 @@ module \dec_rc$139 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:131146.1-131198.10" +attribute \src "libresoc.v:132162.1-132214.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_BRANCH.dec_rc" attribute \generator "nMigen" module \dec_rc$142 - attribute \src "libresoc.v:131147.7-131147.20" + attribute \src "libresoc.v:132163.7-132163.20" wire $0\initial[0:0] - attribute \src "libresoc.v:131160.3-131178.6" + attribute \src "libresoc.v:132176.3-132194.6" wire $0\rc[0:0] - attribute \src "libresoc.v:131179.3-131197.6" + attribute \src "libresoc.v:132195.3-132213.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:131160.3-131178.6" + attribute \src "libresoc.v:132176.3-132194.6" wire $1\rc[0:0] - attribute \src "libresoc.v:131179.3-131197.6" + attribute \src "libresoc.v:132195.3-132213.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 1 \BRANCH_Rc - attribute \src "libresoc.v:131147.7-131147.15" + attribute \src "libresoc.v:132163.7-132163.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \rc @@ -206190,22 +206964,22 @@ module \dec_rc$142 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 input 2 \sel_in - attribute \src "libresoc.v:131147.7-131147.20" - process $proc$libresoc.v:131147$5086 + attribute \src "libresoc.v:132163.7-132163.20" + process $proc$libresoc.v:132163$5086 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:131160.3-131178.6" - process $proc$libresoc.v:131160$5084 + attribute \src "libresoc.v:132176.3-132194.6" + process $proc$libresoc.v:132176$5084 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:131161.5-131161.29" + attribute \src "libresoc.v:132177.5-132177.29" switch \initial - attribute \src "libresoc.v:131161.9-131161.17" + attribute \src "libresoc.v:132177.9-132177.17" case 1'1 case end @@ -206229,14 +207003,14 @@ module \dec_rc$142 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:131179.3-131197.6" - process $proc$libresoc.v:131179$5085 + attribute \src "libresoc.v:132195.3-132213.6" + process $proc$libresoc.v:132195$5085 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:131180.5-131180.29" + attribute \src "libresoc.v:132196.5-132196.29" switch \initial - attribute \src "libresoc.v:131180.9-131180.17" + attribute \src "libresoc.v:132196.9-132196.17" case 1'1 case end @@ -206261,24 +207035,24 @@ module \dec_rc$142 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:131202.1-131256.10" +attribute \src "libresoc.v:132218.1-132272.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LOGICAL.dec_rc" attribute \generator "nMigen" module \dec_rc$146 - attribute \src "libresoc.v:131203.7-131203.20" + attribute \src "libresoc.v:132219.7-132219.20" wire $0\initial[0:0] - attribute \src "libresoc.v:131218.3-131236.6" + attribute \src "libresoc.v:132234.3-132252.6" wire $0\rc[0:0] - attribute \src "libresoc.v:131237.3-131255.6" + attribute \src "libresoc.v:132253.3-132271.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:131218.3-131236.6" + attribute \src "libresoc.v:132234.3-132252.6" wire $1\rc[0:0] - attribute \src "libresoc.v:131237.3-131255.6" + attribute \src "libresoc.v:132253.3-132271.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 3 \LOGICAL_Rc - attribute \src "libresoc.v:131203.7-131203.15" + attribute \src "libresoc.v:132219.7-132219.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc @@ -206290,22 +207064,22 @@ module \dec_rc$146 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:131203.7-131203.20" - process $proc$libresoc.v:131203$5089 + attribute \src "libresoc.v:132219.7-132219.20" + process $proc$libresoc.v:132219$5089 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:131218.3-131236.6" - process $proc$libresoc.v:131218$5087 + attribute \src "libresoc.v:132234.3-132252.6" + process $proc$libresoc.v:132234$5087 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:131219.5-131219.29" + attribute \src "libresoc.v:132235.5-132235.29" switch \initial - attribute \src "libresoc.v:131219.9-131219.17" + attribute \src "libresoc.v:132235.9-132235.17" case 1'1 case end @@ -206329,14 +207103,14 @@ module \dec_rc$146 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:131237.3-131255.6" - process $proc$libresoc.v:131237$5088 + attribute \src "libresoc.v:132253.3-132271.6" + process $proc$libresoc.v:132253$5088 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:131238.5-131238.29" + attribute \src "libresoc.v:132254.5-132254.29" switch \initial - attribute \src "libresoc.v:131238.9-131238.17" + attribute \src "libresoc.v:132254.9-132254.17" case 1'1 case end @@ -206361,24 +207135,24 @@ module \dec_rc$146 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:131260.1-131312.10" +attribute \src "libresoc.v:132276.1-132328.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SPR.dec_rc" attribute \generator "nMigen" module \dec_rc$151 - attribute \src "libresoc.v:131261.7-131261.20" + attribute \src "libresoc.v:132277.7-132277.20" wire $0\initial[0:0] - attribute \src "libresoc.v:131274.3-131292.6" + attribute \src "libresoc.v:132290.3-132308.6" wire $0\rc[0:0] - attribute \src "libresoc.v:131293.3-131311.6" + attribute \src "libresoc.v:132309.3-132327.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:131274.3-131292.6" + attribute \src "libresoc.v:132290.3-132308.6" wire $1\rc[0:0] - attribute \src "libresoc.v:131293.3-131311.6" + attribute \src "libresoc.v:132309.3-132327.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 1 \SPR_Rc - attribute \src "libresoc.v:131261.7-131261.15" + attribute \src "libresoc.v:132277.7-132277.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \rc @@ -206390,22 +207164,22 @@ module \dec_rc$151 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 input 2 \sel_in - attribute \src "libresoc.v:131261.7-131261.20" - process $proc$libresoc.v:131261$5092 + attribute \src "libresoc.v:132277.7-132277.20" + process $proc$libresoc.v:132277$5092 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:131274.3-131292.6" - process $proc$libresoc.v:131274$5090 + attribute \src "libresoc.v:132290.3-132308.6" + process $proc$libresoc.v:132290$5090 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:131275.5-131275.29" + attribute \src "libresoc.v:132291.5-132291.29" switch \initial - attribute \src "libresoc.v:131275.9-131275.17" + attribute \src "libresoc.v:132291.9-132291.17" case 1'1 case end @@ -206429,14 +207203,14 @@ module \dec_rc$151 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:131293.3-131311.6" - process $proc$libresoc.v:131293$5091 + attribute \src "libresoc.v:132309.3-132327.6" + process $proc$libresoc.v:132309$5091 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:131294.5-131294.29" + attribute \src "libresoc.v:132310.5-132310.29" switch \initial - attribute \src "libresoc.v:131294.9-131294.17" + attribute \src "libresoc.v:132310.9-132310.17" case 1'1 case end @@ -206461,24 +207235,24 @@ module \dec_rc$151 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:131316.1-131370.10" +attribute \src "libresoc.v:132332.1-132386.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_DIV.dec_rc" attribute \generator "nMigen" module \dec_rc$154 - attribute \src "libresoc.v:131317.7-131317.20" + attribute \src "libresoc.v:132333.7-132333.20" wire $0\initial[0:0] - attribute \src "libresoc.v:131332.3-131350.6" + attribute \src "libresoc.v:132348.3-132366.6" wire $0\rc[0:0] - attribute \src "libresoc.v:131351.3-131369.6" + attribute \src "libresoc.v:132367.3-132385.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:131332.3-131350.6" + attribute \src "libresoc.v:132348.3-132366.6" wire $1\rc[0:0] - attribute \src "libresoc.v:131351.3-131369.6" + attribute \src "libresoc.v:132367.3-132385.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 3 \DIV_Rc - attribute \src "libresoc.v:131317.7-131317.15" + attribute \src "libresoc.v:132333.7-132333.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc @@ -206490,22 +207264,22 @@ module \dec_rc$154 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:131317.7-131317.20" - process $proc$libresoc.v:131317$5095 + attribute \src "libresoc.v:132333.7-132333.20" + process $proc$libresoc.v:132333$5095 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:131332.3-131350.6" - process $proc$libresoc.v:131332$5093 + attribute \src "libresoc.v:132348.3-132366.6" + process $proc$libresoc.v:132348$5093 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:131333.5-131333.29" + attribute \src "libresoc.v:132349.5-132349.29" switch \initial - attribute \src "libresoc.v:131333.9-131333.17" + attribute \src "libresoc.v:132349.9-132349.17" case 1'1 case end @@ -206529,14 +207303,14 @@ module \dec_rc$154 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:131351.3-131369.6" - process $proc$libresoc.v:131351$5094 + attribute \src "libresoc.v:132367.3-132385.6" + process $proc$libresoc.v:132367$5094 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:131352.5-131352.29" + attribute \src "libresoc.v:132368.5-132368.29" switch \initial - attribute \src "libresoc.v:131352.9-131352.17" + attribute \src "libresoc.v:132368.9-132368.17" case 1'1 case end @@ -206561,24 +207335,24 @@ module \dec_rc$154 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:131374.1-131428.10" +attribute \src "libresoc.v:132390.1-132444.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_MUL.dec_rc" attribute \generator "nMigen" module \dec_rc$159 - attribute \src "libresoc.v:131375.7-131375.20" + attribute \src "libresoc.v:132391.7-132391.20" wire $0\initial[0:0] - attribute \src "libresoc.v:131390.3-131408.6" + attribute \src "libresoc.v:132406.3-132424.6" wire $0\rc[0:0] - attribute \src "libresoc.v:131409.3-131427.6" + attribute \src "libresoc.v:132425.3-132443.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:131390.3-131408.6" + attribute \src "libresoc.v:132406.3-132424.6" wire $1\rc[0:0] - attribute \src "libresoc.v:131409.3-131427.6" + attribute \src "libresoc.v:132425.3-132443.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 3 \MUL_Rc - attribute \src "libresoc.v:131375.7-131375.15" + attribute \src "libresoc.v:132391.7-132391.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc @@ -206590,22 +207364,22 @@ module \dec_rc$159 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:131375.7-131375.20" - process $proc$libresoc.v:131375$5098 + attribute \src "libresoc.v:132391.7-132391.20" + process $proc$libresoc.v:132391$5098 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:131390.3-131408.6" - process $proc$libresoc.v:131390$5096 + attribute \src "libresoc.v:132406.3-132424.6" + process $proc$libresoc.v:132406$5096 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:131391.5-131391.29" + attribute \src "libresoc.v:132407.5-132407.29" switch \initial - attribute \src "libresoc.v:131391.9-131391.17" + attribute \src "libresoc.v:132407.9-132407.17" case 1'1 case end @@ -206629,14 +207403,14 @@ module \dec_rc$159 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:131409.3-131427.6" - process $proc$libresoc.v:131409$5097 + attribute \src "libresoc.v:132425.3-132443.6" + process $proc$libresoc.v:132425$5097 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:131410.5-131410.29" + attribute \src "libresoc.v:132426.5-132426.29" switch \initial - attribute \src "libresoc.v:131410.9-131410.17" + attribute \src "libresoc.v:132426.9-132426.17" case 1'1 case end @@ -206661,24 +207435,24 @@ module \dec_rc$159 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:131432.1-131486.10" +attribute \src "libresoc.v:132448.1-132502.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_SHIFT_ROT.dec_rc" attribute \generator "nMigen" module \dec_rc$163 - attribute \src "libresoc.v:131433.7-131433.20" + attribute \src "libresoc.v:132449.7-132449.20" wire $0\initial[0:0] - attribute \src "libresoc.v:131448.3-131466.6" + attribute \src "libresoc.v:132464.3-132482.6" wire $0\rc[0:0] - attribute \src "libresoc.v:131467.3-131485.6" + attribute \src "libresoc.v:132483.3-132501.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:131448.3-131466.6" + attribute \src "libresoc.v:132464.3-132482.6" wire $1\rc[0:0] - attribute \src "libresoc.v:131467.3-131485.6" + attribute \src "libresoc.v:132483.3-132501.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 3 \SHIFT_ROT_Rc - attribute \src "libresoc.v:131433.7-131433.15" + attribute \src "libresoc.v:132449.7-132449.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc @@ -206690,22 +207464,22 @@ module \dec_rc$163 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:131433.7-131433.20" - process $proc$libresoc.v:131433$5101 + attribute \src "libresoc.v:132449.7-132449.20" + process $proc$libresoc.v:132449$5101 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:131448.3-131466.6" - process $proc$libresoc.v:131448$5099 + attribute \src "libresoc.v:132464.3-132482.6" + process $proc$libresoc.v:132464$5099 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:131449.5-131449.29" + attribute \src "libresoc.v:132465.5-132465.29" switch \initial - attribute \src "libresoc.v:131449.9-131449.17" + attribute \src "libresoc.v:132465.9-132465.17" case 1'1 case end @@ -206729,14 +207503,14 @@ module \dec_rc$163 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:131467.3-131485.6" - process $proc$libresoc.v:131467$5100 + attribute \src "libresoc.v:132483.3-132501.6" + process $proc$libresoc.v:132483$5100 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:131468.5-131468.29" + attribute \src "libresoc.v:132484.5-132484.29" switch \initial - attribute \src "libresoc.v:131468.9-131468.17" + attribute \src "libresoc.v:132484.9-132484.17" case 1'1 case end @@ -206761,24 +207535,24 @@ module \dec_rc$163 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:131490.1-131544.10" +attribute \src "libresoc.v:132506.1-132560.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.dec_LDST.dec_rc" attribute \generator "nMigen" module \dec_rc$167 - attribute \src "libresoc.v:131491.7-131491.20" + attribute \src "libresoc.v:132507.7-132507.20" wire $0\initial[0:0] - attribute \src "libresoc.v:131506.3-131524.6" + attribute \src "libresoc.v:132522.3-132540.6" wire $0\rc[0:0] - attribute \src "libresoc.v:131525.3-131543.6" + attribute \src "libresoc.v:132541.3-132559.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:131506.3-131524.6" + attribute \src "libresoc.v:132522.3-132540.6" wire $1\rc[0:0] - attribute \src "libresoc.v:131525.3-131543.6" + attribute \src "libresoc.v:132541.3-132559.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 3 \LDST_Rc - attribute \src "libresoc.v:131491.7-131491.15" + attribute \src "libresoc.v:132507.7-132507.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc @@ -206790,22 +207564,22 @@ module \dec_rc$167 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:131491.7-131491.20" - process $proc$libresoc.v:131491$5104 + attribute \src "libresoc.v:132507.7-132507.20" + process $proc$libresoc.v:132507$5104 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:131506.3-131524.6" - process $proc$libresoc.v:131506$5102 + attribute \src "libresoc.v:132522.3-132540.6" + process $proc$libresoc.v:132522$5102 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:131507.5-131507.29" + attribute \src "libresoc.v:132523.5-132523.29" switch \initial - attribute \src "libresoc.v:131507.9-131507.17" + attribute \src "libresoc.v:132523.9-132523.17" case 1'1 case end @@ -206829,14 +207603,14 @@ module \dec_rc$167 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:131525.3-131543.6" - process $proc$libresoc.v:131525$5103 + attribute \src "libresoc.v:132541.3-132559.6" + process $proc$libresoc.v:132541$5103 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:131526.5-131526.29" + attribute \src "libresoc.v:132542.5-132542.29" switch \initial - attribute \src "libresoc.v:131526.9-131526.17" + attribute \src "libresoc.v:132542.9-132542.17" case 1'1 case end @@ -206861,24 +207635,24 @@ module \dec_rc$167 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:131548.1-131602.10" +attribute \src "libresoc.v:132564.1-132618.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_rc" attribute \generator "nMigen" module \dec_rc$172 - attribute \src "libresoc.v:131549.7-131549.20" + attribute \src "libresoc.v:132565.7-132565.20" wire $0\initial[0:0] - attribute \src "libresoc.v:131564.3-131582.6" + attribute \src "libresoc.v:132580.3-132598.6" wire $0\rc[0:0] - attribute \src "libresoc.v:131583.3-131601.6" + attribute \src "libresoc.v:132599.3-132617.6" wire $0\rc_ok[0:0] - attribute \src "libresoc.v:131564.3-131582.6" + attribute \src "libresoc.v:132580.3-132598.6" wire $1\rc[0:0] - attribute \src "libresoc.v:131583.3-131601.6" + attribute \src "libresoc.v:132599.3-132617.6" wire $1\rc_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:470" wire input 3 \Rc - attribute \src "libresoc.v:131549.7-131549.15" + attribute \src "libresoc.v:132565.7-132565.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 1 \rc @@ -206890,22 +207664,22 @@ module \dec_rc$172 attribute \enum_value_10 "RC" attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" wire width 2 input 4 \sel_in - attribute \src "libresoc.v:131549.7-131549.20" - process $proc$libresoc.v:131549$5107 + attribute \src "libresoc.v:132565.7-132565.20" + process $proc$libresoc.v:132565$5107 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:131564.3-131582.6" - process $proc$libresoc.v:131564$5105 + attribute \src "libresoc.v:132580.3-132598.6" + process $proc$libresoc.v:132580$5105 assign { } { } assign { } { } assign $0\rc[0:0] $1\rc[0:0] - attribute \src "libresoc.v:131565.5-131565.29" + attribute \src "libresoc.v:132581.5-132581.29" switch \initial - attribute \src "libresoc.v:131565.9-131565.17" + attribute \src "libresoc.v:132581.9-132581.17" case 1'1 case end @@ -206929,14 +207703,14 @@ module \dec_rc$172 sync always update \rc $0\rc[0:0] end - attribute \src "libresoc.v:131583.3-131601.6" - process $proc$libresoc.v:131583$5106 + attribute \src "libresoc.v:132599.3-132617.6" + process $proc$libresoc.v:132599$5106 assign { } { } assign { } { } assign $0\rc_ok[0:0] $1\rc_ok[0:0] - attribute \src "libresoc.v:131584.5-131584.29" + attribute \src "libresoc.v:132600.5-132600.29" switch \initial - attribute \src "libresoc.v:131584.9-131584.17" + attribute \src "libresoc.v:132600.9-132600.17" case 1'1 case end @@ -206961,539 +207735,539 @@ module \dec_rc$172 update \rc_ok $0\rc_ok[0:0] end end -attribute \src "libresoc.v:131606.1-132850.10" +attribute \src "libresoc.v:132622.1-133866.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0" attribute \generator "nMigen" module \div0 - attribute \src "libresoc.v:132407.3-132408.25" + attribute \src "libresoc.v:133423.3-133424.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:132594.3-132632.6" + attribute \src "libresoc.v:133610.3-133648.6" wire width 4 $0\alu_div0_logical_op__data_len$next[3:0]$5247 - attribute \src "libresoc.v:132379.3-132380.75" + attribute \src "libresoc.v:133395.3-133396.75" wire width 4 $0\alu_div0_logical_op__data_len[3:0] - attribute \src "libresoc.v:132594.3-132632.6" + attribute \src "libresoc.v:133610.3-133648.6" wire width 14 $0\alu_div0_logical_op__fn_unit$next[13:0]$5248 - attribute \src "libresoc.v:132349.3-132350.73" + attribute \src "libresoc.v:133365.3-133366.73" wire width 14 $0\alu_div0_logical_op__fn_unit[13:0] - attribute \src "libresoc.v:132594.3-132632.6" + attribute \src "libresoc.v:133610.3-133648.6" wire width 64 $0\alu_div0_logical_op__imm_data__data$next[63:0]$5249 - attribute \src "libresoc.v:132351.3-132352.87" + attribute \src "libresoc.v:133367.3-133368.87" wire width 64 $0\alu_div0_logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:132594.3-132632.6" + attribute \src "libresoc.v:133610.3-133648.6" wire $0\alu_div0_logical_op__imm_data__ok$next[0:0]$5250 - attribute \src "libresoc.v:132353.3-132354.83" + attribute \src "libresoc.v:133369.3-133370.83" wire $0\alu_div0_logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:132594.3-132632.6" + attribute \src "libresoc.v:133610.3-133648.6" wire width 2 $0\alu_div0_logical_op__input_carry$next[1:0]$5251 - attribute \src "libresoc.v:132367.3-132368.81" + attribute \src "libresoc.v:133383.3-133384.81" wire width 2 $0\alu_div0_logical_op__input_carry[1:0] - attribute \src "libresoc.v:132594.3-132632.6" + attribute \src "libresoc.v:133610.3-133648.6" wire width 32 $0\alu_div0_logical_op__insn$next[31:0]$5252 - attribute \src "libresoc.v:132381.3-132382.67" + attribute \src "libresoc.v:133397.3-133398.67" wire width 32 $0\alu_div0_logical_op__insn[31:0] - attribute \src "libresoc.v:132594.3-132632.6" + attribute \src "libresoc.v:133610.3-133648.6" wire width 7 $0\alu_div0_logical_op__insn_type$next[6:0]$5253 - attribute \src "libresoc.v:132347.3-132348.77" + attribute \src "libresoc.v:133363.3-133364.77" wire width 7 $0\alu_div0_logical_op__insn_type[6:0] - attribute \src "libresoc.v:132594.3-132632.6" + attribute \src "libresoc.v:133610.3-133648.6" wire $0\alu_div0_logical_op__invert_in$next[0:0]$5254 - attribute \src "libresoc.v:132363.3-132364.77" + attribute \src "libresoc.v:133379.3-133380.77" wire $0\alu_div0_logical_op__invert_in[0:0] - attribute \src "libresoc.v:132594.3-132632.6" + attribute \src "libresoc.v:133610.3-133648.6" wire $0\alu_div0_logical_op__invert_out$next[0:0]$5255 - attribute \src "libresoc.v:132369.3-132370.79" + attribute \src "libresoc.v:133385.3-133386.79" wire $0\alu_div0_logical_op__invert_out[0:0] - attribute \src "libresoc.v:132594.3-132632.6" + attribute \src "libresoc.v:133610.3-133648.6" wire $0\alu_div0_logical_op__is_32bit$next[0:0]$5256 - attribute \src "libresoc.v:132375.3-132376.75" + attribute \src "libresoc.v:133391.3-133392.75" wire $0\alu_div0_logical_op__is_32bit[0:0] - attribute \src "libresoc.v:132594.3-132632.6" + attribute \src "libresoc.v:133610.3-133648.6" wire $0\alu_div0_logical_op__is_signed$next[0:0]$5257 - attribute \src "libresoc.v:132377.3-132378.77" + attribute \src "libresoc.v:133393.3-133394.77" wire $0\alu_div0_logical_op__is_signed[0:0] - attribute \src "libresoc.v:132594.3-132632.6" + attribute \src "libresoc.v:133610.3-133648.6" wire $0\alu_div0_logical_op__oe__oe$next[0:0]$5258 - attribute \src "libresoc.v:132359.3-132360.71" + attribute \src "libresoc.v:133375.3-133376.71" wire $0\alu_div0_logical_op__oe__oe[0:0] - attribute \src "libresoc.v:132594.3-132632.6" + attribute \src "libresoc.v:133610.3-133648.6" wire $0\alu_div0_logical_op__oe__ok$next[0:0]$5259 - attribute \src "libresoc.v:132361.3-132362.71" + attribute \src "libresoc.v:133377.3-133378.71" wire $0\alu_div0_logical_op__oe__ok[0:0] - attribute \src "libresoc.v:132594.3-132632.6" + attribute \src "libresoc.v:133610.3-133648.6" wire $0\alu_div0_logical_op__output_carry$next[0:0]$5260 - attribute \src "libresoc.v:132373.3-132374.83" + attribute \src "libresoc.v:133389.3-133390.83" wire $0\alu_div0_logical_op__output_carry[0:0] - attribute \src "libresoc.v:132594.3-132632.6" + attribute \src "libresoc.v:133610.3-133648.6" wire $0\alu_div0_logical_op__rc__ok$next[0:0]$5261 - attribute \src "libresoc.v:132357.3-132358.71" + attribute \src "libresoc.v:133373.3-133374.71" wire $0\alu_div0_logical_op__rc__ok[0:0] - attribute \src "libresoc.v:132594.3-132632.6" + attribute \src "libresoc.v:133610.3-133648.6" wire $0\alu_div0_logical_op__rc__rc$next[0:0]$5262 - attribute \src "libresoc.v:132355.3-132356.71" + attribute \src "libresoc.v:133371.3-133372.71" wire $0\alu_div0_logical_op__rc__rc[0:0] - attribute \src "libresoc.v:132594.3-132632.6" + attribute \src "libresoc.v:133610.3-133648.6" wire $0\alu_div0_logical_op__write_cr0$next[0:0]$5263 - attribute \src "libresoc.v:132371.3-132372.77" + attribute \src "libresoc.v:133387.3-133388.77" wire $0\alu_div0_logical_op__write_cr0[0:0] - attribute \src "libresoc.v:132594.3-132632.6" + attribute \src "libresoc.v:133610.3-133648.6" wire $0\alu_div0_logical_op__zero_a$next[0:0]$5264 - attribute \src "libresoc.v:132365.3-132366.71" + attribute \src "libresoc.v:133381.3-133382.71" wire $0\alu_div0_logical_op__zero_a[0:0] - attribute \src "libresoc.v:132405.3-132406.40" + attribute \src "libresoc.v:133421.3-133422.40" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:132760.3-132768.6" + attribute \src "libresoc.v:133776.3-133784.6" wire $0\alu_l_r_alu$next[0:0]$5334 - attribute \src "libresoc.v:132321.3-132322.39" + attribute \src "libresoc.v:133337.3-133338.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:132751.3-132759.6" + attribute \src "libresoc.v:133767.3-133775.6" wire $0\alui_l_r_alui$next[0:0]$5331 - attribute \src "libresoc.v:132323.3-132324.43" + attribute \src "libresoc.v:133339.3-133340.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:132633.3-132654.6" + attribute \src "libresoc.v:133649.3-133670.6" wire width 64 $0\data_r0__o$next[63:0]$5290 - attribute \src "libresoc.v:132343.3-132344.37" + attribute \src "libresoc.v:133359.3-133360.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:132633.3-132654.6" + attribute \src "libresoc.v:133649.3-133670.6" wire $0\data_r0__o_ok$next[0:0]$5291 - attribute \src "libresoc.v:132345.3-132346.43" + attribute \src "libresoc.v:133361.3-133362.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:132655.3-132676.6" + attribute \src "libresoc.v:133671.3-133692.6" wire width 4 $0\data_r1__cr_a$next[3:0]$5298 - attribute \src "libresoc.v:132339.3-132340.43" + attribute \src "libresoc.v:133355.3-133356.43" wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:132655.3-132676.6" + attribute \src "libresoc.v:133671.3-133692.6" wire $0\data_r1__cr_a_ok$next[0:0]$5299 - attribute \src "libresoc.v:132341.3-132342.49" + attribute \src "libresoc.v:133357.3-133358.49" wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:132677.3-132698.6" + attribute \src "libresoc.v:133693.3-133714.6" wire width 2 $0\data_r2__xer_ov$next[1:0]$5306 - attribute \src "libresoc.v:132335.3-132336.47" + attribute \src "libresoc.v:133351.3-133352.47" wire width 2 $0\data_r2__xer_ov[1:0] - attribute \src "libresoc.v:132677.3-132698.6" + attribute \src "libresoc.v:133693.3-133714.6" wire $0\data_r2__xer_ov_ok$next[0:0]$5307 - attribute \src "libresoc.v:132337.3-132338.53" + attribute \src "libresoc.v:133353.3-133354.53" wire $0\data_r2__xer_ov_ok[0:0] - attribute \src "libresoc.v:132699.3-132720.6" + attribute \src "libresoc.v:133715.3-133736.6" wire $0\data_r3__xer_so$next[0:0]$5314 - attribute \src "libresoc.v:132331.3-132332.47" + attribute \src "libresoc.v:133347.3-133348.47" wire $0\data_r3__xer_so[0:0] - attribute \src "libresoc.v:132699.3-132720.6" + attribute \src "libresoc.v:133715.3-133736.6" wire $0\data_r3__xer_so_ok$next[0:0]$5315 - attribute \src "libresoc.v:132333.3-132334.53" + attribute \src "libresoc.v:133349.3-133350.53" wire $0\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:132769.3-132778.6" + attribute \src "libresoc.v:133785.3-133794.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:132779.3-132788.6" + attribute \src "libresoc.v:133795.3-133804.6" wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:132789.3-132798.6" + attribute \src "libresoc.v:133805.3-133814.6" wire width 2 $0\dest3_o[1:0] - attribute \src "libresoc.v:132799.3-132808.6" + attribute \src "libresoc.v:133815.3-133824.6" wire $0\dest4_o[0:0] - attribute \src "libresoc.v:131607.7-131607.20" + attribute \src "libresoc.v:132623.7-132623.20" wire $0\initial[0:0] - attribute \src "libresoc.v:132549.3-132557.6" + attribute \src "libresoc.v:133565.3-133573.6" wire $0\opc_l_r_opc$next[0:0]$5232 - attribute \src "libresoc.v:132391.3-132392.39" + attribute \src "libresoc.v:133407.3-133408.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:132540.3-132548.6" + attribute \src "libresoc.v:133556.3-133564.6" wire $0\opc_l_s_opc$next[0:0]$5229 - attribute \src "libresoc.v:132393.3-132394.39" + attribute \src "libresoc.v:133409.3-133410.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:132809.3-132817.6" + attribute \src "libresoc.v:133825.3-133833.6" wire width 4 $0\prev_wr_go$next[3:0]$5341 - attribute \src "libresoc.v:132403.3-132404.37" + attribute \src "libresoc.v:133419.3-133420.37" wire width 4 $0\prev_wr_go[3:0] - attribute \src "libresoc.v:132494.3-132503.6" + attribute \src "libresoc.v:133510.3-133519.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:132585.3-132593.6" + attribute \src "libresoc.v:133601.3-133609.6" wire width 4 $0\req_l_r_req$next[3:0]$5244 - attribute \src "libresoc.v:132383.3-132384.39" + attribute \src "libresoc.v:133399.3-133400.39" wire width 4 $0\req_l_r_req[3:0] - attribute \src "libresoc.v:132576.3-132584.6" + attribute \src "libresoc.v:133592.3-133600.6" wire width 4 $0\req_l_s_req$next[3:0]$5241 - attribute \src "libresoc.v:132385.3-132386.39" + attribute \src "libresoc.v:133401.3-133402.39" wire width 4 $0\req_l_s_req[3:0] - attribute \src "libresoc.v:132513.3-132521.6" + attribute \src "libresoc.v:133529.3-133537.6" wire $0\rok_l_r_rdok$next[0:0]$5220 - attribute \src "libresoc.v:132399.3-132400.41" + attribute \src "libresoc.v:133415.3-133416.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:132504.3-132512.6" + attribute \src "libresoc.v:133520.3-133528.6" wire $0\rok_l_s_rdok$next[0:0]$5217 - attribute \src "libresoc.v:132401.3-132402.41" + attribute \src "libresoc.v:133417.3-133418.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:132531.3-132539.6" + attribute \src "libresoc.v:133547.3-133555.6" wire $0\rst_l_r_rst$next[0:0]$5226 - attribute \src "libresoc.v:132395.3-132396.39" + attribute \src "libresoc.v:133411.3-133412.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:132522.3-132530.6" + attribute \src "libresoc.v:133538.3-133546.6" wire $0\rst_l_s_rst$next[0:0]$5223 - attribute \src "libresoc.v:132397.3-132398.39" + attribute \src "libresoc.v:133413.3-133414.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:132567.3-132575.6" + attribute \src "libresoc.v:133583.3-133591.6" wire width 3 $0\src_l_r_src$next[2:0]$5238 - attribute \src "libresoc.v:132387.3-132388.39" + attribute \src "libresoc.v:133403.3-133404.39" wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:132558.3-132566.6" + attribute \src "libresoc.v:133574.3-133582.6" wire width 3 $0\src_l_s_src$next[2:0]$5235 - attribute \src "libresoc.v:132389.3-132390.39" + attribute \src "libresoc.v:133405.3-133406.39" wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:132721.3-132730.6" + attribute \src "libresoc.v:133737.3-133746.6" wire width 64 $0\src_r0$next[63:0]$5322 - attribute \src "libresoc.v:132329.3-132330.29" + attribute \src "libresoc.v:133345.3-133346.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:132731.3-132740.6" + attribute \src "libresoc.v:133747.3-133756.6" wire width 64 $0\src_r1$next[63:0]$5325 - attribute \src "libresoc.v:132327.3-132328.29" + attribute \src "libresoc.v:133343.3-133344.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:132741.3-132750.6" + attribute \src "libresoc.v:133757.3-133766.6" wire $0\src_r2$next[0:0]$5328 - attribute \src "libresoc.v:132325.3-132326.29" + attribute \src "libresoc.v:133341.3-133342.29" wire $0\src_r2[0:0] - attribute \src "libresoc.v:131737.7-131737.24" + attribute \src "libresoc.v:132753.7-132753.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:132594.3-132632.6" + attribute \src "libresoc.v:133610.3-133648.6" wire width 4 $1\alu_div0_logical_op__data_len$next[3:0]$5265 - attribute \src "libresoc.v:131747.13-131747.49" + attribute \src "libresoc.v:132763.13-132763.49" wire width 4 $1\alu_div0_logical_op__data_len[3:0] - attribute \src "libresoc.v:132594.3-132632.6" + attribute \src "libresoc.v:133610.3-133648.6" wire width 14 $1\alu_div0_logical_op__fn_unit$next[13:0]$5266 - attribute \src "libresoc.v:131766.14-131766.53" + attribute \src "libresoc.v:132782.14-132782.53" wire width 14 $1\alu_div0_logical_op__fn_unit[13:0] - attribute \src "libresoc.v:132594.3-132632.6" + attribute \src "libresoc.v:133610.3-133648.6" wire width 64 $1\alu_div0_logical_op__imm_data__data$next[63:0]$5267 - attribute \src "libresoc.v:131770.14-131770.72" + attribute \src "libresoc.v:132786.14-132786.72" wire width 64 $1\alu_div0_logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:132594.3-132632.6" + attribute \src "libresoc.v:133610.3-133648.6" wire $1\alu_div0_logical_op__imm_data__ok$next[0:0]$5268 - attribute \src "libresoc.v:131774.7-131774.47" + attribute \src "libresoc.v:132790.7-132790.47" wire $1\alu_div0_logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:132594.3-132632.6" + attribute \src "libresoc.v:133610.3-133648.6" wire width 2 $1\alu_div0_logical_op__input_carry$next[1:0]$5269 - attribute \src "libresoc.v:131782.13-131782.52" + attribute \src "libresoc.v:132798.13-132798.52" wire width 2 $1\alu_div0_logical_op__input_carry[1:0] - attribute \src "libresoc.v:132594.3-132632.6" + attribute \src "libresoc.v:133610.3-133648.6" wire width 32 $1\alu_div0_logical_op__insn$next[31:0]$5270 - attribute \src "libresoc.v:131786.14-131786.47" + attribute \src "libresoc.v:132802.14-132802.47" wire width 32 $1\alu_div0_logical_op__insn[31:0] - attribute \src "libresoc.v:132594.3-132632.6" + attribute \src "libresoc.v:133610.3-133648.6" wire width 7 $1\alu_div0_logical_op__insn_type$next[6:0]$5271 - attribute \src "libresoc.v:131865.13-131865.51" + attribute \src "libresoc.v:132881.13-132881.51" wire width 7 $1\alu_div0_logical_op__insn_type[6:0] - attribute \src "libresoc.v:132594.3-132632.6" + attribute \src "libresoc.v:133610.3-133648.6" wire $1\alu_div0_logical_op__invert_in$next[0:0]$5272 - attribute \src "libresoc.v:131869.7-131869.44" + attribute \src "libresoc.v:132885.7-132885.44" wire $1\alu_div0_logical_op__invert_in[0:0] - attribute \src "libresoc.v:132594.3-132632.6" + attribute \src "libresoc.v:133610.3-133648.6" wire $1\alu_div0_logical_op__invert_out$next[0:0]$5273 - attribute \src "libresoc.v:131873.7-131873.45" + attribute \src "libresoc.v:132889.7-132889.45" wire $1\alu_div0_logical_op__invert_out[0:0] - attribute \src "libresoc.v:132594.3-132632.6" + attribute \src "libresoc.v:133610.3-133648.6" wire $1\alu_div0_logical_op__is_32bit$next[0:0]$5274 - attribute \src "libresoc.v:131877.7-131877.43" + attribute \src "libresoc.v:132893.7-132893.43" wire $1\alu_div0_logical_op__is_32bit[0:0] - attribute \src "libresoc.v:132594.3-132632.6" + attribute \src "libresoc.v:133610.3-133648.6" wire $1\alu_div0_logical_op__is_signed$next[0:0]$5275 - attribute \src "libresoc.v:131881.7-131881.44" + attribute \src "libresoc.v:132897.7-132897.44" wire $1\alu_div0_logical_op__is_signed[0:0] - attribute \src "libresoc.v:132594.3-132632.6" + attribute \src "libresoc.v:133610.3-133648.6" wire $1\alu_div0_logical_op__oe__oe$next[0:0]$5276 - attribute \src "libresoc.v:131885.7-131885.41" + attribute \src "libresoc.v:132901.7-132901.41" wire $1\alu_div0_logical_op__oe__oe[0:0] - attribute \src "libresoc.v:132594.3-132632.6" + attribute \src "libresoc.v:133610.3-133648.6" wire $1\alu_div0_logical_op__oe__ok$next[0:0]$5277 - attribute \src "libresoc.v:131889.7-131889.41" + attribute \src "libresoc.v:132905.7-132905.41" wire $1\alu_div0_logical_op__oe__ok[0:0] - attribute \src "libresoc.v:132594.3-132632.6" + attribute \src "libresoc.v:133610.3-133648.6" wire $1\alu_div0_logical_op__output_carry$next[0:0]$5278 - attribute \src "libresoc.v:131893.7-131893.47" + attribute \src "libresoc.v:132909.7-132909.47" wire $1\alu_div0_logical_op__output_carry[0:0] - attribute \src "libresoc.v:132594.3-132632.6" + attribute \src "libresoc.v:133610.3-133648.6" wire $1\alu_div0_logical_op__rc__ok$next[0:0]$5279 - attribute \src "libresoc.v:131897.7-131897.41" + attribute \src "libresoc.v:132913.7-132913.41" wire $1\alu_div0_logical_op__rc__ok[0:0] - attribute \src "libresoc.v:132594.3-132632.6" + attribute \src "libresoc.v:133610.3-133648.6" wire $1\alu_div0_logical_op__rc__rc$next[0:0]$5280 - attribute \src "libresoc.v:131901.7-131901.41" + attribute \src "libresoc.v:132917.7-132917.41" wire $1\alu_div0_logical_op__rc__rc[0:0] - attribute \src "libresoc.v:132594.3-132632.6" + attribute \src "libresoc.v:133610.3-133648.6" wire $1\alu_div0_logical_op__write_cr0$next[0:0]$5281 - attribute \src "libresoc.v:131905.7-131905.44" + attribute \src "libresoc.v:132921.7-132921.44" wire $1\alu_div0_logical_op__write_cr0[0:0] - attribute \src "libresoc.v:132594.3-132632.6" + attribute \src "libresoc.v:133610.3-133648.6" wire $1\alu_div0_logical_op__zero_a$next[0:0]$5282 - attribute \src "libresoc.v:131909.7-131909.41" + attribute \src "libresoc.v:132925.7-132925.41" wire $1\alu_div0_logical_op__zero_a[0:0] - attribute \src "libresoc.v:131935.7-131935.26" + attribute \src "libresoc.v:132951.7-132951.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:132760.3-132768.6" + attribute \src "libresoc.v:133776.3-133784.6" wire $1\alu_l_r_alu$next[0:0]$5335 - attribute \src "libresoc.v:131943.7-131943.25" + attribute \src "libresoc.v:132959.7-132959.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:132751.3-132759.6" + attribute \src "libresoc.v:133767.3-133775.6" wire $1\alui_l_r_alui$next[0:0]$5332 - attribute \src "libresoc.v:131955.7-131955.27" + attribute \src "libresoc.v:132971.7-132971.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:132633.3-132654.6" + attribute \src "libresoc.v:133649.3-133670.6" wire width 64 $1\data_r0__o$next[63:0]$5292 - attribute \src "libresoc.v:131989.14-131989.47" + attribute \src "libresoc.v:133005.14-133005.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:132633.3-132654.6" + attribute \src "libresoc.v:133649.3-133670.6" wire $1\data_r0__o_ok$next[0:0]$5293 - attribute \src "libresoc.v:131993.7-131993.27" + attribute \src "libresoc.v:133009.7-133009.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:132655.3-132676.6" + attribute \src "libresoc.v:133671.3-133692.6" wire width 4 $1\data_r1__cr_a$next[3:0]$5300 - attribute \src "libresoc.v:131997.13-131997.33" + attribute \src "libresoc.v:133013.13-133013.33" wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:132655.3-132676.6" + attribute \src "libresoc.v:133671.3-133692.6" wire $1\data_r1__cr_a_ok$next[0:0]$5301 - attribute \src "libresoc.v:132001.7-132001.30" + attribute \src "libresoc.v:133017.7-133017.30" wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:132677.3-132698.6" + attribute \src "libresoc.v:133693.3-133714.6" wire width 2 $1\data_r2__xer_ov$next[1:0]$5308 - attribute \src "libresoc.v:132005.13-132005.35" + attribute \src "libresoc.v:133021.13-133021.35" wire width 2 $1\data_r2__xer_ov[1:0] - attribute \src "libresoc.v:132677.3-132698.6" + attribute \src "libresoc.v:133693.3-133714.6" wire $1\data_r2__xer_ov_ok$next[0:0]$5309 - attribute \src "libresoc.v:132009.7-132009.32" + attribute \src "libresoc.v:133025.7-133025.32" wire $1\data_r2__xer_ov_ok[0:0] - attribute \src "libresoc.v:132699.3-132720.6" + attribute \src "libresoc.v:133715.3-133736.6" wire $1\data_r3__xer_so$next[0:0]$5316 - attribute \src "libresoc.v:132013.7-132013.29" + attribute \src "libresoc.v:133029.7-133029.29" wire $1\data_r3__xer_so[0:0] - attribute \src "libresoc.v:132699.3-132720.6" + attribute \src "libresoc.v:133715.3-133736.6" wire $1\data_r3__xer_so_ok$next[0:0]$5317 - attribute \src "libresoc.v:132017.7-132017.32" + attribute \src "libresoc.v:133033.7-133033.32" wire $1\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:132769.3-132778.6" + attribute \src "libresoc.v:133785.3-133794.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:132779.3-132788.6" + attribute \src "libresoc.v:133795.3-133804.6" wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:132789.3-132798.6" + attribute \src "libresoc.v:133805.3-133814.6" wire width 2 $1\dest3_o[1:0] - attribute \src "libresoc.v:132799.3-132808.6" + attribute \src "libresoc.v:133815.3-133824.6" wire $1\dest4_o[0:0] - attribute \src "libresoc.v:132549.3-132557.6" + attribute \src "libresoc.v:133565.3-133573.6" wire $1\opc_l_r_opc$next[0:0]$5233 - attribute \src "libresoc.v:132037.7-132037.25" + attribute \src "libresoc.v:133053.7-133053.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:132540.3-132548.6" + attribute \src "libresoc.v:133556.3-133564.6" wire $1\opc_l_s_opc$next[0:0]$5230 - attribute \src "libresoc.v:132041.7-132041.25" + attribute \src "libresoc.v:133057.7-133057.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:132809.3-132817.6" + attribute \src "libresoc.v:133825.3-133833.6" wire width 4 $1\prev_wr_go$next[3:0]$5342 - attribute \src "libresoc.v:132175.13-132175.30" + attribute \src "libresoc.v:133191.13-133191.30" wire width 4 $1\prev_wr_go[3:0] - attribute \src "libresoc.v:132494.3-132503.6" + attribute \src "libresoc.v:133510.3-133519.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:132585.3-132593.6" + attribute \src "libresoc.v:133601.3-133609.6" wire width 4 $1\req_l_r_req$next[3:0]$5245 - attribute \src "libresoc.v:132183.13-132183.31" + attribute \src "libresoc.v:133199.13-133199.31" wire width 4 $1\req_l_r_req[3:0] - attribute \src "libresoc.v:132576.3-132584.6" + attribute \src "libresoc.v:133592.3-133600.6" wire width 4 $1\req_l_s_req$next[3:0]$5242 - attribute \src "libresoc.v:132187.13-132187.31" + attribute \src "libresoc.v:133203.13-133203.31" wire width 4 $1\req_l_s_req[3:0] - attribute \src "libresoc.v:132513.3-132521.6" + attribute \src "libresoc.v:133529.3-133537.6" wire $1\rok_l_r_rdok$next[0:0]$5221 - attribute \src "libresoc.v:132199.7-132199.26" + attribute \src "libresoc.v:133215.7-133215.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:132504.3-132512.6" + attribute \src "libresoc.v:133520.3-133528.6" wire $1\rok_l_s_rdok$next[0:0]$5218 - attribute \src "libresoc.v:132203.7-132203.26" + attribute \src "libresoc.v:133219.7-133219.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:132531.3-132539.6" + attribute \src "libresoc.v:133547.3-133555.6" wire $1\rst_l_r_rst$next[0:0]$5227 - attribute \src "libresoc.v:132207.7-132207.25" + attribute \src "libresoc.v:133223.7-133223.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:132522.3-132530.6" + attribute \src "libresoc.v:133538.3-133546.6" wire $1\rst_l_s_rst$next[0:0]$5224 - attribute \src "libresoc.v:132211.7-132211.25" + attribute \src "libresoc.v:133227.7-133227.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:132567.3-132575.6" + attribute \src "libresoc.v:133583.3-133591.6" wire width 3 $1\src_l_r_src$next[2:0]$5239 - attribute \src "libresoc.v:132225.13-132225.31" + attribute \src "libresoc.v:133241.13-133241.31" wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:132558.3-132566.6" + attribute \src "libresoc.v:133574.3-133582.6" wire width 3 $1\src_l_s_src$next[2:0]$5236 - attribute \src "libresoc.v:132229.13-132229.31" + attribute \src "libresoc.v:133245.13-133245.31" wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:132721.3-132730.6" + attribute \src "libresoc.v:133737.3-133746.6" wire width 64 $1\src_r0$next[63:0]$5323 - attribute \src "libresoc.v:132237.14-132237.43" + attribute \src "libresoc.v:133253.14-133253.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:132731.3-132740.6" + attribute \src "libresoc.v:133747.3-133756.6" wire width 64 $1\src_r1$next[63:0]$5326 - attribute \src "libresoc.v:132241.14-132241.43" + attribute \src "libresoc.v:133257.14-133257.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:132741.3-132750.6" + attribute \src "libresoc.v:133757.3-133766.6" wire $1\src_r2$next[0:0]$5329 - attribute \src "libresoc.v:132245.7-132245.20" + attribute \src "libresoc.v:133261.7-133261.20" wire $1\src_r2[0:0] - attribute \src "libresoc.v:132594.3-132632.6" + attribute \src "libresoc.v:133610.3-133648.6" wire width 64 $2\alu_div0_logical_op__imm_data__data$next[63:0]$5283 - attribute \src "libresoc.v:132594.3-132632.6" + attribute \src "libresoc.v:133610.3-133648.6" wire $2\alu_div0_logical_op__imm_data__ok$next[0:0]$5284 - attribute \src "libresoc.v:132594.3-132632.6" + attribute \src "libresoc.v:133610.3-133648.6" wire $2\alu_div0_logical_op__oe__oe$next[0:0]$5285 - attribute \src "libresoc.v:132594.3-132632.6" + attribute \src "libresoc.v:133610.3-133648.6" wire $2\alu_div0_logical_op__oe__ok$next[0:0]$5286 - attribute \src "libresoc.v:132594.3-132632.6" + attribute \src "libresoc.v:133610.3-133648.6" wire $2\alu_div0_logical_op__rc__ok$next[0:0]$5287 - attribute \src "libresoc.v:132594.3-132632.6" + attribute \src "libresoc.v:133610.3-133648.6" wire $2\alu_div0_logical_op__rc__rc$next[0:0]$5288 - attribute \src "libresoc.v:132633.3-132654.6" + attribute \src "libresoc.v:133649.3-133670.6" wire width 64 $2\data_r0__o$next[63:0]$5294 - attribute \src "libresoc.v:132633.3-132654.6" + attribute \src "libresoc.v:133649.3-133670.6" wire $2\data_r0__o_ok$next[0:0]$5295 - attribute \src "libresoc.v:132655.3-132676.6" + attribute \src "libresoc.v:133671.3-133692.6" wire width 4 $2\data_r1__cr_a$next[3:0]$5302 - attribute \src "libresoc.v:132655.3-132676.6" + attribute \src "libresoc.v:133671.3-133692.6" wire $2\data_r1__cr_a_ok$next[0:0]$5303 - attribute \src "libresoc.v:132677.3-132698.6" + attribute \src "libresoc.v:133693.3-133714.6" wire width 2 $2\data_r2__xer_ov$next[1:0]$5310 - attribute \src "libresoc.v:132677.3-132698.6" + attribute \src "libresoc.v:133693.3-133714.6" wire $2\data_r2__xer_ov_ok$next[0:0]$5311 - attribute \src "libresoc.v:132699.3-132720.6" + attribute \src "libresoc.v:133715.3-133736.6" wire $2\data_r3__xer_so$next[0:0]$5318 - attribute \src "libresoc.v:132699.3-132720.6" + attribute \src "libresoc.v:133715.3-133736.6" wire $2\data_r3__xer_so_ok$next[0:0]$5319 - attribute \src "libresoc.v:132633.3-132654.6" + attribute \src "libresoc.v:133649.3-133670.6" wire $3\data_r0__o_ok$next[0:0]$5296 - attribute \src "libresoc.v:132655.3-132676.6" + attribute \src "libresoc.v:133671.3-133692.6" wire $3\data_r1__cr_a_ok$next[0:0]$5304 - attribute \src "libresoc.v:132677.3-132698.6" + attribute \src "libresoc.v:133693.3-133714.6" wire $3\data_r2__xer_ov_ok$next[0:0]$5312 - attribute \src "libresoc.v:132699.3-132720.6" + attribute \src "libresoc.v:133715.3-133736.6" wire $3\data_r3__xer_so_ok$next[0:0]$5320 - attribute \src "libresoc.v:132260.19-132260.133" - wire width 3 $and$libresoc.v:132260$5110_Y - attribute \src "libresoc.v:132262.19-132262.115" - wire width 3 $and$libresoc.v:132262$5112_Y - attribute \src "libresoc.v:132263.18-132263.110" - wire $and$libresoc.v:132263$5113_Y - attribute \src "libresoc.v:132264.19-132264.125" - wire $and$libresoc.v:132264$5114_Y - attribute \src "libresoc.v:132265.19-132265.125" - wire $and$libresoc.v:132265$5115_Y - attribute \src "libresoc.v:132266.19-132266.125" - wire $and$libresoc.v:132266$5116_Y - attribute \src "libresoc.v:132267.19-132267.125" - wire $and$libresoc.v:132267$5117_Y - attribute \src "libresoc.v:132268.19-132268.149" - wire width 4 $and$libresoc.v:132268$5118_Y - attribute \src "libresoc.v:132269.19-132269.121" - wire width 4 $and$libresoc.v:132269$5119_Y - attribute \src "libresoc.v:132270.19-132270.127" - wire $and$libresoc.v:132270$5120_Y - attribute \src "libresoc.v:132271.19-132271.127" - wire $and$libresoc.v:132271$5121_Y - attribute \src "libresoc.v:132272.19-132272.127" - wire $and$libresoc.v:132272$5122_Y - attribute \src "libresoc.v:132273.19-132273.127" - wire $and$libresoc.v:132273$5123_Y - attribute \src "libresoc.v:132275.18-132275.98" - wire $and$libresoc.v:132275$5125_Y - attribute \src "libresoc.v:132277.18-132277.100" - wire $and$libresoc.v:132277$5127_Y - attribute \src "libresoc.v:132278.18-132278.160" - wire width 4 $and$libresoc.v:132278$5128_Y - attribute \src "libresoc.v:132280.18-132280.119" - wire width 4 $and$libresoc.v:132280$5130_Y - attribute \src "libresoc.v:132283.17-132283.123" - wire $and$libresoc.v:132283$5133_Y - attribute \src "libresoc.v:132284.18-132284.116" - wire $and$libresoc.v:132284$5134_Y - attribute \src "libresoc.v:132289.18-132289.113" - wire $and$libresoc.v:132289$5139_Y - attribute \src "libresoc.v:132290.18-132290.125" - wire width 4 $and$libresoc.v:132290$5140_Y - attribute \src "libresoc.v:132292.18-132292.112" - wire $and$libresoc.v:132292$5142_Y - attribute \src "libresoc.v:132294.18-132294.126" - wire $and$libresoc.v:132294$5144_Y - attribute \src "libresoc.v:132295.18-132295.126" - wire $and$libresoc.v:132295$5145_Y - attribute \src "libresoc.v:132296.18-132296.117" - wire $and$libresoc.v:132296$5146_Y - attribute \src "libresoc.v:132302.18-132302.130" - wire $and$libresoc.v:132302$5152_Y - attribute \src "libresoc.v:132303.18-132303.124" - wire width 4 $and$libresoc.v:132303$5153_Y - attribute \src "libresoc.v:132305.18-132305.116" - wire $and$libresoc.v:132305$5155_Y - attribute \src "libresoc.v:132306.18-132306.119" - wire $and$libresoc.v:132306$5156_Y - attribute \src "libresoc.v:132307.18-132307.121" - wire $and$libresoc.v:132307$5157_Y - attribute \src "libresoc.v:132308.18-132308.121" - wire $and$libresoc.v:132308$5158_Y - attribute \src "libresoc.v:132318.18-132318.134" - wire $and$libresoc.v:132318$5168_Y - attribute \src "libresoc.v:132319.18-132319.132" - wire $and$libresoc.v:132319$5169_Y - attribute \src "libresoc.v:132320.18-132320.149" - wire width 3 $and$libresoc.v:132320$5170_Y - attribute \src "libresoc.v:132291.18-132291.113" - wire $eq$libresoc.v:132291$5141_Y - attribute \src "libresoc.v:132293.18-132293.119" - wire $eq$libresoc.v:132293$5143_Y - attribute \src "libresoc.v:132258.19-132258.130" - wire $not$libresoc.v:132258$5108_Y - attribute \src "libresoc.v:132259.19-132259.136" - wire $not$libresoc.v:132259$5109_Y - attribute \src "libresoc.v:132261.19-132261.115" - wire width 3 $not$libresoc.v:132261$5111_Y - attribute \src "libresoc.v:132274.18-132274.97" - wire $not$libresoc.v:132274$5124_Y - attribute \src "libresoc.v:132276.18-132276.99" - wire $not$libresoc.v:132276$5126_Y - attribute \src "libresoc.v:132279.18-132279.113" - wire width 4 $not$libresoc.v:132279$5129_Y - attribute \src "libresoc.v:132282.18-132282.106" - wire $not$libresoc.v:132282$5132_Y - attribute \src "libresoc.v:132288.18-132288.120" - wire $not$libresoc.v:132288$5138_Y - attribute \src "libresoc.v:132299.17-132299.113" - wire width 3 $not$libresoc.v:132299$5149_Y - attribute \src "libresoc.v:132287.18-132287.112" - wire $or$libresoc.v:132287$5137_Y - attribute \src "libresoc.v:132297.18-132297.122" - wire $or$libresoc.v:132297$5147_Y - attribute \src "libresoc.v:132298.18-132298.124" - wire $or$libresoc.v:132298$5148_Y - attribute \src "libresoc.v:132300.18-132300.168" - wire width 4 $or$libresoc.v:132300$5150_Y - attribute \src "libresoc.v:132301.18-132301.155" - wire width 3 $or$libresoc.v:132301$5151_Y - attribute \src "libresoc.v:132304.18-132304.120" - wire width 4 $or$libresoc.v:132304$5154_Y - attribute \src "libresoc.v:132310.17-132310.117" - wire width 3 $or$libresoc.v:132310$5160_Y - attribute \src "libresoc.v:132315.17-132315.104" - wire $reduce_and$libresoc.v:132315$5165_Y - attribute \src "libresoc.v:132281.18-132281.106" - wire $reduce_or$libresoc.v:132281$5131_Y - attribute \src "libresoc.v:132285.18-132285.113" - wire $reduce_or$libresoc.v:132285$5135_Y - attribute \src "libresoc.v:132286.18-132286.112" - wire $reduce_or$libresoc.v:132286$5136_Y - attribute \src "libresoc.v:132309.18-132309.158" - wire $ternary$libresoc.v:132309$5159_Y - attribute \src "libresoc.v:132311.18-132311.159" - wire width 64 $ternary$libresoc.v:132311$5161_Y - attribute \src "libresoc.v:132312.18-132312.164" - wire $ternary$libresoc.v:132312$5162_Y - attribute \src "libresoc.v:132313.18-132313.180" - wire width 64 $ternary$libresoc.v:132313$5163_Y - attribute \src "libresoc.v:132314.18-132314.115" - wire width 64 $ternary$libresoc.v:132314$5164_Y - attribute \src "libresoc.v:132316.18-132316.125" - wire width 64 $ternary$libresoc.v:132316$5166_Y - attribute \src "libresoc.v:132317.18-132317.118" - wire $ternary$libresoc.v:132317$5167_Y + attribute \src "libresoc.v:133276.19-133276.133" + wire width 3 $and$libresoc.v:133276$5110_Y + attribute \src "libresoc.v:133278.19-133278.115" + wire width 3 $and$libresoc.v:133278$5112_Y + attribute \src "libresoc.v:133279.18-133279.110" + wire $and$libresoc.v:133279$5113_Y + attribute \src "libresoc.v:133280.19-133280.125" + wire $and$libresoc.v:133280$5114_Y + attribute \src "libresoc.v:133281.19-133281.125" + wire $and$libresoc.v:133281$5115_Y + attribute \src "libresoc.v:133282.19-133282.125" + wire $and$libresoc.v:133282$5116_Y + attribute \src "libresoc.v:133283.19-133283.125" + wire $and$libresoc.v:133283$5117_Y + attribute \src "libresoc.v:133284.19-133284.149" + wire width 4 $and$libresoc.v:133284$5118_Y + attribute \src "libresoc.v:133285.19-133285.121" + wire width 4 $and$libresoc.v:133285$5119_Y + attribute \src "libresoc.v:133286.19-133286.127" + wire $and$libresoc.v:133286$5120_Y + attribute \src "libresoc.v:133287.19-133287.127" + wire $and$libresoc.v:133287$5121_Y + attribute \src "libresoc.v:133288.19-133288.127" + wire $and$libresoc.v:133288$5122_Y + attribute \src "libresoc.v:133289.19-133289.127" + wire $and$libresoc.v:133289$5123_Y + attribute \src "libresoc.v:133291.18-133291.98" + wire $and$libresoc.v:133291$5125_Y + attribute \src "libresoc.v:133293.18-133293.100" + wire $and$libresoc.v:133293$5127_Y + attribute \src "libresoc.v:133294.18-133294.160" + wire width 4 $and$libresoc.v:133294$5128_Y + attribute \src "libresoc.v:133296.18-133296.119" + wire width 4 $and$libresoc.v:133296$5130_Y + attribute \src "libresoc.v:133299.17-133299.123" + wire $and$libresoc.v:133299$5133_Y + attribute \src "libresoc.v:133300.18-133300.116" + wire $and$libresoc.v:133300$5134_Y + attribute \src "libresoc.v:133305.18-133305.113" + wire $and$libresoc.v:133305$5139_Y + attribute \src "libresoc.v:133306.18-133306.125" + wire width 4 $and$libresoc.v:133306$5140_Y + attribute \src "libresoc.v:133308.18-133308.112" + wire $and$libresoc.v:133308$5142_Y + attribute \src "libresoc.v:133310.18-133310.126" + wire $and$libresoc.v:133310$5144_Y + attribute \src "libresoc.v:133311.18-133311.126" + wire $and$libresoc.v:133311$5145_Y + attribute \src "libresoc.v:133312.18-133312.117" + wire $and$libresoc.v:133312$5146_Y + attribute \src "libresoc.v:133318.18-133318.130" + wire $and$libresoc.v:133318$5152_Y + attribute \src "libresoc.v:133319.18-133319.124" + wire width 4 $and$libresoc.v:133319$5153_Y + attribute \src "libresoc.v:133321.18-133321.116" + wire $and$libresoc.v:133321$5155_Y + attribute \src "libresoc.v:133322.18-133322.119" + wire $and$libresoc.v:133322$5156_Y + attribute \src "libresoc.v:133323.18-133323.121" + wire $and$libresoc.v:133323$5157_Y + attribute \src "libresoc.v:133324.18-133324.121" + wire $and$libresoc.v:133324$5158_Y + attribute \src "libresoc.v:133334.18-133334.134" + wire $and$libresoc.v:133334$5168_Y + attribute \src "libresoc.v:133335.18-133335.132" + wire $and$libresoc.v:133335$5169_Y + attribute \src "libresoc.v:133336.18-133336.149" + wire width 3 $and$libresoc.v:133336$5170_Y + attribute \src "libresoc.v:133307.18-133307.113" + wire $eq$libresoc.v:133307$5141_Y + attribute \src "libresoc.v:133309.18-133309.119" + wire $eq$libresoc.v:133309$5143_Y + attribute \src "libresoc.v:133274.19-133274.130" + wire $not$libresoc.v:133274$5108_Y + attribute \src "libresoc.v:133275.19-133275.136" + wire $not$libresoc.v:133275$5109_Y + attribute \src "libresoc.v:133277.19-133277.115" + wire width 3 $not$libresoc.v:133277$5111_Y + attribute \src "libresoc.v:133290.18-133290.97" + wire $not$libresoc.v:133290$5124_Y + attribute \src "libresoc.v:133292.18-133292.99" + wire $not$libresoc.v:133292$5126_Y + attribute \src "libresoc.v:133295.18-133295.113" + wire width 4 $not$libresoc.v:133295$5129_Y + attribute \src "libresoc.v:133298.18-133298.106" + wire $not$libresoc.v:133298$5132_Y + attribute \src "libresoc.v:133304.18-133304.120" + wire $not$libresoc.v:133304$5138_Y + attribute \src "libresoc.v:133315.17-133315.113" + wire width 3 $not$libresoc.v:133315$5149_Y + attribute \src "libresoc.v:133303.18-133303.112" + wire $or$libresoc.v:133303$5137_Y + attribute \src "libresoc.v:133313.18-133313.122" + wire $or$libresoc.v:133313$5147_Y + attribute \src "libresoc.v:133314.18-133314.124" + wire $or$libresoc.v:133314$5148_Y + attribute \src "libresoc.v:133316.18-133316.168" + wire width 4 $or$libresoc.v:133316$5150_Y + attribute \src "libresoc.v:133317.18-133317.155" + wire width 3 $or$libresoc.v:133317$5151_Y + attribute \src "libresoc.v:133320.18-133320.120" + wire width 4 $or$libresoc.v:133320$5154_Y + attribute \src "libresoc.v:133326.17-133326.117" + wire width 3 $or$libresoc.v:133326$5160_Y + attribute \src "libresoc.v:133331.17-133331.104" + wire $reduce_and$libresoc.v:133331$5165_Y + attribute \src "libresoc.v:133297.18-133297.106" + wire $reduce_or$libresoc.v:133297$5131_Y + attribute \src "libresoc.v:133301.18-133301.113" + wire $reduce_or$libresoc.v:133301$5135_Y + attribute \src "libresoc.v:133302.18-133302.112" + wire $reduce_or$libresoc.v:133302$5136_Y + attribute \src "libresoc.v:133325.18-133325.158" + wire $ternary$libresoc.v:133325$5159_Y + attribute \src "libresoc.v:133327.18-133327.159" + wire width 64 $ternary$libresoc.v:133327$5161_Y + attribute \src "libresoc.v:133328.18-133328.164" + wire $ternary$libresoc.v:133328$5162_Y + attribute \src "libresoc.v:133329.18-133329.180" + wire width 64 $ternary$libresoc.v:133329$5163_Y + attribute \src "libresoc.v:133330.18-133330.115" + wire width 64 $ternary$libresoc.v:133330$5164_Y + attribute \src "libresoc.v:133332.18-133332.125" + wire width 64 $ternary$libresoc.v:133332$5166_Y + attribute \src "libresoc.v:133333.18-133333.118" + wire $ternary$libresoc.v:133333$5167_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" @@ -207846,9 +208620,9 @@ module \div0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 38 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 32 \cr_a_ok @@ -207914,7 +208688,7 @@ module \div0 wire width 2 output 35 \dest3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire output 37 \dest4_o - attribute \src "libresoc.v:131607.7-131607.15" + attribute \src "libresoc.v:132623.7-132623.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 28 \o_ok @@ -208143,7 +208917,7 @@ module \div0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 36 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:132260$5110 + cell $and $and$libresoc.v:133276$5110 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -208151,10 +208925,10 @@ module \div0 parameter \Y_WIDTH 3 connect \A \$98 connect \B { 1'1 \$102 \$100 } - connect \Y $and$libresoc.v:132260$5110_Y + connect \Y $and$libresoc.v:133276$5110_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:132262$5112 + cell $and $and$libresoc.v:133278$5112 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -208162,10 +208936,10 @@ module \div0 parameter \Y_WIDTH 3 connect \A \$104 connect \B \$106 - connect \Y $and$libresoc.v:132262$5112_Y + connect \Y $and$libresoc.v:133278$5112_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:132263$5113 + cell $and $and$libresoc.v:133279$5113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208173,10 +208947,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$2 connect \B \$4 - connect \Y $and$libresoc.v:132263$5113_Y + connect \Y $and$libresoc.v:133279$5113_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:132264$5114 + cell $and $and$libresoc.v:133280$5114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208184,10 +208958,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:132264$5114_Y + connect \Y $and$libresoc.v:133280$5114_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:132265$5115 + cell $and $and$libresoc.v:133281$5115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208195,10 +208969,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:132265$5115_Y + connect \Y $and$libresoc.v:133281$5115_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:132266$5116 + cell $and $and$libresoc.v:133282$5116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208206,10 +208980,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:132266$5116_Y + connect \Y $and$libresoc.v:133282$5116_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:132267$5117 + cell $and $and$libresoc.v:133283$5117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208217,10 +208991,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:132267$5117_Y + connect \Y $and$libresoc.v:133283$5117_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:132268$5118 + cell $and $and$libresoc.v:133284$5118 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -208228,10 +209002,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \req_l_q_req connect \B { \$110 \$112 \$114 \$116 } - connect \Y $and$libresoc.v:132268$5118_Y + connect \Y $and$libresoc.v:133284$5118_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:132269$5119 + cell $and $and$libresoc.v:133285$5119 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -208239,10 +209013,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \$118 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:132269$5119_Y + connect \Y $and$libresoc.v:133285$5119_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:132270$5120 + cell $and $and$libresoc.v:133286$5120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208250,10 +209024,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:132270$5120_Y + connect \Y $and$libresoc.v:133286$5120_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:132271$5121 + cell $and $and$libresoc.v:133287$5121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208261,10 +209035,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:132271$5121_Y + connect \Y $and$libresoc.v:133287$5121_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:132272$5122 + cell $and $and$libresoc.v:133288$5122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208272,10 +209046,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:132272$5122_Y + connect \Y $and$libresoc.v:133288$5122_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:132273$5123 + cell $and $and$libresoc.v:133289$5123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208283,10 +209057,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o - connect \Y $and$libresoc.v:132273$5123_Y + connect \Y $and$libresoc.v:133289$5123_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:132275$5125 + cell $and $and$libresoc.v:133291$5125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208294,10 +209068,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$12 - connect \Y $and$libresoc.v:132275$5125_Y + connect \Y $and$libresoc.v:133291$5125_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:132277$5127 + cell $and $and$libresoc.v:133293$5127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208305,10 +209079,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$16 - connect \Y $and$libresoc.v:132277$5127_Y + connect \Y $and$libresoc.v:133293$5127_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:132278$5128 + cell $and $and$libresoc.v:133294$5128 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -208316,10 +209090,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:132278$5128_Y + connect \Y $and$libresoc.v:133294$5128_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:132280$5130 + cell $and $and$libresoc.v:133296$5130 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -208327,10 +209101,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \cu_wr__rel_o connect \B \$24 - connect \Y $and$libresoc.v:132280$5130_Y + connect \Y $and$libresoc.v:133296$5130_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:132283$5133 + cell $and $and$libresoc.v:133299$5133 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208338,10 +209112,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:132283$5133_Y + connect \Y $and$libresoc.v:133299$5133_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:132284$5134 + cell $and $and$libresoc.v:133300$5134 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208349,10 +209123,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$22 - connect \Y $and$libresoc.v:132284$5134_Y + connect \Y $and$libresoc.v:133300$5134_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:132289$5139 + cell $and $and$libresoc.v:133305$5139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208360,10 +209134,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$38 - connect \Y $and$libresoc.v:132289$5139_Y + connect \Y $and$libresoc.v:133305$5139_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:132290$5140 + cell $and $and$libresoc.v:133306$5140 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -208371,10 +209145,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:132290$5140_Y + connect \Y $and$libresoc.v:133306$5140_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:132292$5142 + cell $and $and$libresoc.v:133308$5142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208382,10 +209156,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$40 connect \B \$44 - connect \Y $and$libresoc.v:132292$5142_Y + connect \Y $and$libresoc.v:133308$5142_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:132294$5144 + cell $and $and$libresoc.v:133310$5144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208393,10 +209167,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$48 connect \B \alu_div0_n_ready_i - connect \Y $and$libresoc.v:132294$5144_Y + connect \Y $and$libresoc.v:133310$5144_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:132295$5145 + cell $and $and$libresoc.v:133311$5145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208404,10 +209178,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$50 connect \B \alu_div0_n_valid_o - connect \Y $and$libresoc.v:132295$5145_Y + connect \Y $and$libresoc.v:133311$5145_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:132296$5146 + cell $and $and$libresoc.v:133312$5146 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208415,10 +209189,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$52 connect \B \cu_busy_o - connect \Y $and$libresoc.v:132296$5146_Y + connect \Y $and$libresoc.v:133312$5146_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:132302$5152 + cell $and $and$libresoc.v:133318$5152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208426,10 +209200,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \alu_div0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:132302$5152_Y + connect \Y $and$libresoc.v:133318$5152_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:132303$5153 + cell $and $and$libresoc.v:133319$5153 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -208437,10 +209211,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:132303$5153_Y + connect \Y $and$libresoc.v:133319$5153_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:132305$5155 + cell $and $and$libresoc.v:133321$5155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208448,10 +209222,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:132305$5155_Y + connect \Y $and$libresoc.v:133321$5155_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:132306$5156 + cell $and $and$libresoc.v:133322$5156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208459,10 +209233,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:132306$5156_Y + connect \Y $and$libresoc.v:133322$5156_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:132307$5157 + cell $and $and$libresoc.v:133323$5157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208470,10 +209244,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \xer_ov_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:132307$5157_Y + connect \Y $and$libresoc.v:133323$5157_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:132308$5158 + cell $and $and$libresoc.v:133324$5158 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208481,10 +209255,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \xer_so_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:132308$5158_Y + connect \Y $and$libresoc.v:133324$5158_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:132318$5168 + cell $and $and$libresoc.v:133334$5168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208492,10 +209266,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \alu_div0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:132318$5168_Y + connect \Y $and$libresoc.v:133334$5168_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:132319$5169 + cell $and $and$libresoc.v:133335$5169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208503,10 +209277,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \alu_div0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:132319$5169_Y + connect \Y $and$libresoc.v:133335$5169_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:132320$5170 + cell $and $and$libresoc.v:133336$5170 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -208514,10 +209288,10 @@ module \div0 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:132320$5170_Y + connect \Y $and$libresoc.v:133336$5170_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:132291$5141 + cell $eq $eq$libresoc.v:133307$5141 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -208525,10 +209299,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$42 connect \B 1'0 - connect \Y $eq$libresoc.v:132291$5141_Y + connect \Y $eq$libresoc.v:133307$5141_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:132293$5143 + cell $eq $eq$libresoc.v:133309$5143 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -208536,82 +209310,82 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:132293$5143_Y + connect \Y $eq$libresoc.v:133309$5143_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:132258$5108 + cell $not $not$libresoc.v:133274$5108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_div0_logical_op__zero_a - connect \Y $not$libresoc.v:132258$5108_Y + connect \Y $not$libresoc.v:133274$5108_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:132259$5109 + cell $not $not$libresoc.v:133275$5109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_div0_logical_op__imm_data__ok - connect \Y $not$libresoc.v:132259$5109_Y + connect \Y $not$libresoc.v:133275$5109_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:132261$5111 + cell $not $not$libresoc.v:133277$5111 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:132261$5111_Y + connect \Y $not$libresoc.v:133277$5111_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:132274$5124 + cell $not $not$libresoc.v:133290$5124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:132274$5124_Y + connect \Y $not$libresoc.v:133290$5124_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:132276$5126 + cell $not $not$libresoc.v:133292$5126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:132276$5126_Y + connect \Y $not$libresoc.v:133292$5126_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:132279$5129 + cell $not $not$libresoc.v:133295$5129 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:132279$5129_Y + connect \Y $not$libresoc.v:133295$5129_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:132282$5132 + cell $not $not$libresoc.v:133298$5132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$23 - connect \Y $not$libresoc.v:132282$5132_Y + connect \Y $not$libresoc.v:133298$5132_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:132288$5138 + cell $not $not$libresoc.v:133304$5138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_div0_n_ready_i - connect \Y $not$libresoc.v:132288$5138_Y + connect \Y $not$libresoc.v:133304$5138_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:132299$5149 + cell $not $not$libresoc.v:133315$5149 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:132299$5149_Y + connect \Y $not$libresoc.v:133315$5149_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:132287$5137 + cell $or $or$libresoc.v:133303$5137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208619,10 +209393,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \$32 connect \B \$34 - connect \Y $or$libresoc.v:132287$5137_Y + connect \Y $or$libresoc.v:133303$5137_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:132297$5147 + cell $or $or$libresoc.v:133313$5147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208630,10 +209404,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:132297$5147_Y + connect \Y $or$libresoc.v:133313$5147_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:132298$5148 + cell $or $or$libresoc.v:133314$5148 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -208641,10 +209415,10 @@ module \div0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:132298$5148_Y + connect \Y $or$libresoc.v:133314$5148_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:132300$5150 + cell $or $or$libresoc.v:133316$5150 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -208652,10 +209426,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:132300$5150_Y + connect \Y $or$libresoc.v:133316$5150_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:132301$5151 + cell $or $or$libresoc.v:133317$5151 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -208663,10 +209437,10 @@ module \div0 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:132301$5151_Y + connect \Y $or$libresoc.v:133317$5151_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:132304$5154 + cell $or $or$libresoc.v:133320$5154 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -208674,10 +209448,10 @@ module \div0 parameter \Y_WIDTH 4 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:132304$5154_Y + connect \Y $or$libresoc.v:133320$5154_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:132310$5160 + cell $or $or$libresoc.v:133326$5160 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -208685,98 +209459,98 @@ module \div0 parameter \Y_WIDTH 3 connect \A \$5 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:132310$5160_Y + connect \Y $or$libresoc.v:133326$5160_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:132315$5165 + cell $reduce_and $reduce_and$libresoc.v:133331$5165 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$7 - connect \Y $reduce_and$libresoc.v:132315$5165_Y + connect \Y $reduce_and$libresoc.v:133331$5165_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:132281$5131 + cell $reduce_or $reduce_or$libresoc.v:133297$5131 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \$26 - connect \Y $reduce_or$libresoc.v:132281$5131_Y + connect \Y $reduce_or$libresoc.v:133297$5131_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:132285$5135 + cell $reduce_or $reduce_or$libresoc.v:133301$5135 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:132285$5135_Y + connect \Y $reduce_or$libresoc.v:133301$5135_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:132286$5136 + cell $reduce_or $reduce_or$libresoc.v:133302$5136 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:132286$5136_Y + connect \Y $reduce_or$libresoc.v:133302$5136_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:132309$5159 + cell $mux $ternary$libresoc.v:133325$5159 parameter \WIDTH 1 connect \A \src_l_q_src [0] connect \B \opc_l_q_opc connect \S \alu_div0_logical_op__zero_a - connect \Y $ternary$libresoc.v:132309$5159_Y + connect \Y $ternary$libresoc.v:133325$5159_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:132311$5161 + cell $mux $ternary$libresoc.v:133327$5161 parameter \WIDTH 64 connect \A \src1_i connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 connect \S \alu_div0_logical_op__zero_a - connect \Y $ternary$libresoc.v:132311$5161_Y + connect \Y $ternary$libresoc.v:133327$5161_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:132312$5162 + cell $mux $ternary$libresoc.v:133328$5162 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_div0_logical_op__imm_data__ok - connect \Y $ternary$libresoc.v:132312$5162_Y + connect \Y $ternary$libresoc.v:133328$5162_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:132313$5163 + cell $mux $ternary$libresoc.v:133329$5163 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_div0_logical_op__imm_data__data connect \S \alu_div0_logical_op__imm_data__ok - connect \Y $ternary$libresoc.v:132313$5163_Y + connect \Y $ternary$libresoc.v:133329$5163_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:132314$5164 + cell $mux $ternary$libresoc.v:133330$5164 parameter \WIDTH 64 connect \A \src_r0 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:132314$5164_Y + connect \Y $ternary$libresoc.v:133330$5164_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:132316$5166 + cell $mux $ternary$libresoc.v:133332$5166 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm$85 connect \S \src_sel$82 - connect \Y $ternary$libresoc.v:132316$5166_Y + connect \Y $ternary$libresoc.v:133332$5166_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:132317$5167 + cell $mux $ternary$libresoc.v:133333$5167 parameter \WIDTH 1 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:132317$5167_Y + connect \Y $ternary$libresoc.v:133333$5167_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:132409.12-132445.4" + attribute \src "libresoc.v:133425.12-133461.4" cell \alu_div0 \alu_div0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -208815,7 +209589,7 @@ module \div0 connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:132446.14-132452.4" + attribute \src "libresoc.v:133462.14-133468.4" cell \alu_l$90 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -208824,7 +209598,7 @@ module \div0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:132453.15-132459.4" + attribute \src "libresoc.v:133469.15-133475.4" cell \alui_l$89 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -208833,7 +209607,7 @@ module \div0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:132460.14-132466.4" + attribute \src "libresoc.v:133476.14-133482.4" cell \opc_l$85 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -208842,7 +209616,7 @@ module \div0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:132467.14-132473.4" + attribute \src "libresoc.v:133483.14-133489.4" cell \req_l$86 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -208851,7 +209625,7 @@ module \div0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:132474.14-132480.4" + attribute \src "libresoc.v:133490.14-133496.4" cell \rok_l$88 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -208860,7 +209634,7 @@ module \div0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:132481.14-132486.4" + attribute \src "libresoc.v:133497.14-133502.4" cell \rst_l$87 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -208868,7 +209642,7 @@ module \div0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:132487.14-132493.4" + attribute \src "libresoc.v:133503.14-133509.4" cell \src_l$84 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -208876,682 +209650,682 @@ module \div0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:131607.7-131607.20" - process $proc$libresoc.v:131607$5343 + attribute \src "libresoc.v:132623.7-132623.20" + process $proc$libresoc.v:132623$5343 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:131737.7-131737.24" - process $proc$libresoc.v:131737$5344 + attribute \src "libresoc.v:132753.7-132753.24" + process $proc$libresoc.v:132753$5344 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:131747.13-131747.49" - process $proc$libresoc.v:131747$5345 + attribute \src "libresoc.v:132763.13-132763.49" + process $proc$libresoc.v:132763$5345 assign { } { } assign $1\alu_div0_logical_op__data_len[3:0] 4'0000 sync always sync init update \alu_div0_logical_op__data_len $1\alu_div0_logical_op__data_len[3:0] end - attribute \src "libresoc.v:131766.14-131766.53" - process $proc$libresoc.v:131766$5346 + attribute \src "libresoc.v:132782.14-132782.53" + process $proc$libresoc.v:132782$5346 assign { } { } assign $1\alu_div0_logical_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_div0_logical_op__fn_unit $1\alu_div0_logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:131770.14-131770.72" - process $proc$libresoc.v:131770$5347 + attribute \src "libresoc.v:132786.14-132786.72" + process $proc$libresoc.v:132786$5347 assign { } { } assign $1\alu_div0_logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_div0_logical_op__imm_data__data $1\alu_div0_logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:131774.7-131774.47" - process $proc$libresoc.v:131774$5348 + attribute \src "libresoc.v:132790.7-132790.47" + process $proc$libresoc.v:132790$5348 assign { } { } assign $1\alu_div0_logical_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_div0_logical_op__imm_data__ok $1\alu_div0_logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:131782.13-131782.52" - process $proc$libresoc.v:131782$5349 + attribute \src "libresoc.v:132798.13-132798.52" + process $proc$libresoc.v:132798$5349 assign { } { } assign $1\alu_div0_logical_op__input_carry[1:0] 2'00 sync always sync init update \alu_div0_logical_op__input_carry $1\alu_div0_logical_op__input_carry[1:0] end - attribute \src "libresoc.v:131786.14-131786.47" - process $proc$libresoc.v:131786$5350 + attribute \src "libresoc.v:132802.14-132802.47" + process $proc$libresoc.v:132802$5350 assign { } { } assign $1\alu_div0_logical_op__insn[31:0] 0 sync always sync init update \alu_div0_logical_op__insn $1\alu_div0_logical_op__insn[31:0] end - attribute \src "libresoc.v:131865.13-131865.51" - process $proc$libresoc.v:131865$5351 + attribute \src "libresoc.v:132881.13-132881.51" + process $proc$libresoc.v:132881$5351 assign { } { } assign $1\alu_div0_logical_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_div0_logical_op__insn_type $1\alu_div0_logical_op__insn_type[6:0] end - attribute \src "libresoc.v:131869.7-131869.44" - process $proc$libresoc.v:131869$5352 + attribute \src "libresoc.v:132885.7-132885.44" + process $proc$libresoc.v:132885$5352 assign { } { } assign $1\alu_div0_logical_op__invert_in[0:0] 1'0 sync always sync init update \alu_div0_logical_op__invert_in $1\alu_div0_logical_op__invert_in[0:0] end - attribute \src "libresoc.v:131873.7-131873.45" - process $proc$libresoc.v:131873$5353 + attribute \src "libresoc.v:132889.7-132889.45" + process $proc$libresoc.v:132889$5353 assign { } { } assign $1\alu_div0_logical_op__invert_out[0:0] 1'0 sync always sync init update \alu_div0_logical_op__invert_out $1\alu_div0_logical_op__invert_out[0:0] end - attribute \src "libresoc.v:131877.7-131877.43" - process $proc$libresoc.v:131877$5354 + attribute \src "libresoc.v:132893.7-132893.43" + process $proc$libresoc.v:132893$5354 assign { } { } assign $1\alu_div0_logical_op__is_32bit[0:0] 1'0 sync always sync init update \alu_div0_logical_op__is_32bit $1\alu_div0_logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:131881.7-131881.44" - process $proc$libresoc.v:131881$5355 + attribute \src "libresoc.v:132897.7-132897.44" + process $proc$libresoc.v:132897$5355 assign { } { } assign $1\alu_div0_logical_op__is_signed[0:0] 1'0 sync always sync init update \alu_div0_logical_op__is_signed $1\alu_div0_logical_op__is_signed[0:0] end - attribute \src "libresoc.v:131885.7-131885.41" - process $proc$libresoc.v:131885$5356 + attribute \src "libresoc.v:132901.7-132901.41" + process $proc$libresoc.v:132901$5356 assign { } { } assign $1\alu_div0_logical_op__oe__oe[0:0] 1'0 sync always sync init update \alu_div0_logical_op__oe__oe $1\alu_div0_logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:131889.7-131889.41" - process $proc$libresoc.v:131889$5357 + attribute \src "libresoc.v:132905.7-132905.41" + process $proc$libresoc.v:132905$5357 assign { } { } assign $1\alu_div0_logical_op__oe__ok[0:0] 1'0 sync always sync init update \alu_div0_logical_op__oe__ok $1\alu_div0_logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:131893.7-131893.47" - process $proc$libresoc.v:131893$5358 + attribute \src "libresoc.v:132909.7-132909.47" + process $proc$libresoc.v:132909$5358 assign { } { } assign $1\alu_div0_logical_op__output_carry[0:0] 1'0 sync always sync init update \alu_div0_logical_op__output_carry $1\alu_div0_logical_op__output_carry[0:0] end - attribute \src "libresoc.v:131897.7-131897.41" - process $proc$libresoc.v:131897$5359 + attribute \src "libresoc.v:132913.7-132913.41" + process $proc$libresoc.v:132913$5359 assign { } { } assign $1\alu_div0_logical_op__rc__ok[0:0] 1'0 sync always sync init update \alu_div0_logical_op__rc__ok $1\alu_div0_logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:131901.7-131901.41" - process $proc$libresoc.v:131901$5360 + attribute \src "libresoc.v:132917.7-132917.41" + process $proc$libresoc.v:132917$5360 assign { } { } assign $1\alu_div0_logical_op__rc__rc[0:0] 1'0 sync always sync init update \alu_div0_logical_op__rc__rc $1\alu_div0_logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:131905.7-131905.44" - process $proc$libresoc.v:131905$5361 + attribute \src "libresoc.v:132921.7-132921.44" + process $proc$libresoc.v:132921$5361 assign { } { } assign $1\alu_div0_logical_op__write_cr0[0:0] 1'0 sync always sync init update \alu_div0_logical_op__write_cr0 $1\alu_div0_logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:131909.7-131909.41" - process $proc$libresoc.v:131909$5362 + attribute \src "libresoc.v:132925.7-132925.41" + process $proc$libresoc.v:132925$5362 assign { } { } assign $1\alu_div0_logical_op__zero_a[0:0] 1'0 sync always sync init update \alu_div0_logical_op__zero_a $1\alu_div0_logical_op__zero_a[0:0] end - attribute \src "libresoc.v:131935.7-131935.26" - process $proc$libresoc.v:131935$5363 + attribute \src "libresoc.v:132951.7-132951.26" + process $proc$libresoc.v:132951$5363 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:131943.7-131943.25" - process $proc$libresoc.v:131943$5364 + attribute \src "libresoc.v:132959.7-132959.25" + process $proc$libresoc.v:132959$5364 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:131955.7-131955.27" - process $proc$libresoc.v:131955$5365 + attribute \src "libresoc.v:132971.7-132971.27" + process $proc$libresoc.v:132971$5365 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:131989.14-131989.47" - process $proc$libresoc.v:131989$5366 + attribute \src "libresoc.v:133005.14-133005.47" + process $proc$libresoc.v:133005$5366 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:131993.7-131993.27" - process $proc$libresoc.v:131993$5367 + attribute \src "libresoc.v:133009.7-133009.27" + process $proc$libresoc.v:133009$5367 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:131997.13-131997.33" - process $proc$libresoc.v:131997$5368 + attribute \src "libresoc.v:133013.13-133013.33" + process $proc$libresoc.v:133013$5368 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:132001.7-132001.30" - process $proc$libresoc.v:132001$5369 + attribute \src "libresoc.v:133017.7-133017.30" + process $proc$libresoc.v:133017$5369 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:132005.13-132005.35" - process $proc$libresoc.v:132005$5370 + attribute \src "libresoc.v:133021.13-133021.35" + process $proc$libresoc.v:133021$5370 assign { } { } assign $1\data_r2__xer_ov[1:0] 2'00 sync always sync init update \data_r2__xer_ov $1\data_r2__xer_ov[1:0] end - attribute \src "libresoc.v:132009.7-132009.32" - process $proc$libresoc.v:132009$5371 + attribute \src "libresoc.v:133025.7-133025.32" + process $proc$libresoc.v:133025$5371 assign { } { } assign $1\data_r2__xer_ov_ok[0:0] 1'0 sync always sync init update \data_r2__xer_ov_ok $1\data_r2__xer_ov_ok[0:0] end - attribute \src "libresoc.v:132013.7-132013.29" - process $proc$libresoc.v:132013$5372 + attribute \src "libresoc.v:133029.7-133029.29" + process $proc$libresoc.v:133029$5372 assign { } { } assign $1\data_r3__xer_so[0:0] 1'0 sync always sync init update \data_r3__xer_so $1\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:132017.7-132017.32" - process $proc$libresoc.v:132017$5373 + attribute \src "libresoc.v:133033.7-133033.32" + process $proc$libresoc.v:133033$5373 assign { } { } assign $1\data_r3__xer_so_ok[0:0] 1'0 sync always sync init update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:132037.7-132037.25" - process $proc$libresoc.v:132037$5374 + attribute \src "libresoc.v:133053.7-133053.25" + process $proc$libresoc.v:133053$5374 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:132041.7-132041.25" - process $proc$libresoc.v:132041$5375 + attribute \src "libresoc.v:133057.7-133057.25" + process $proc$libresoc.v:133057$5375 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:132175.13-132175.30" - process $proc$libresoc.v:132175$5376 + attribute \src "libresoc.v:133191.13-133191.30" + process $proc$libresoc.v:133191$5376 assign { } { } assign $1\prev_wr_go[3:0] 4'0000 sync always sync init update \prev_wr_go $1\prev_wr_go[3:0] end - attribute \src "libresoc.v:132183.13-132183.31" - process $proc$libresoc.v:132183$5377 + attribute \src "libresoc.v:133199.13-133199.31" + process $proc$libresoc.v:133199$5377 assign { } { } assign $1\req_l_r_req[3:0] 4'1111 sync always sync init update \req_l_r_req $1\req_l_r_req[3:0] end - attribute \src "libresoc.v:132187.13-132187.31" - process $proc$libresoc.v:132187$5378 + attribute \src "libresoc.v:133203.13-133203.31" + process $proc$libresoc.v:133203$5378 assign { } { } assign $1\req_l_s_req[3:0] 4'0000 sync always sync init update \req_l_s_req $1\req_l_s_req[3:0] end - attribute \src "libresoc.v:132199.7-132199.26" - process $proc$libresoc.v:132199$5379 + attribute \src "libresoc.v:133215.7-133215.26" + process $proc$libresoc.v:133215$5379 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:132203.7-132203.26" - process $proc$libresoc.v:132203$5380 + attribute \src "libresoc.v:133219.7-133219.26" + process $proc$libresoc.v:133219$5380 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:132207.7-132207.25" - process $proc$libresoc.v:132207$5381 + attribute \src "libresoc.v:133223.7-133223.25" + process $proc$libresoc.v:133223$5381 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:132211.7-132211.25" - process $proc$libresoc.v:132211$5382 + attribute \src "libresoc.v:133227.7-133227.25" + process $proc$libresoc.v:133227$5382 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:132225.13-132225.31" - process $proc$libresoc.v:132225$5383 + attribute \src "libresoc.v:133241.13-133241.31" + process $proc$libresoc.v:133241$5383 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end - attribute \src "libresoc.v:132229.13-132229.31" - process $proc$libresoc.v:132229$5384 + attribute \src "libresoc.v:133245.13-133245.31" + process $proc$libresoc.v:133245$5384 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end - attribute \src "libresoc.v:132237.14-132237.43" - process $proc$libresoc.v:132237$5385 + attribute \src "libresoc.v:133253.14-133253.43" + process $proc$libresoc.v:133253$5385 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:132241.14-132241.43" - process $proc$libresoc.v:132241$5386 + attribute \src "libresoc.v:133257.14-133257.43" + process $proc$libresoc.v:133257$5386 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:132245.7-132245.20" - process $proc$libresoc.v:132245$5387 + attribute \src "libresoc.v:133261.7-133261.20" + process $proc$libresoc.v:133261$5387 assign { } { } assign $1\src_r2[0:0] 1'0 sync always sync init update \src_r2 $1\src_r2[0:0] end - attribute \src "libresoc.v:132321.3-132322.39" - process $proc$libresoc.v:132321$5171 + attribute \src "libresoc.v:133337.3-133338.39" + process $proc$libresoc.v:133337$5171 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:132323.3-132324.43" - process $proc$libresoc.v:132323$5172 + attribute \src "libresoc.v:133339.3-133340.43" + process $proc$libresoc.v:133339$5172 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:132325.3-132326.29" - process $proc$libresoc.v:132325$5173 + attribute \src "libresoc.v:133341.3-133342.29" + process $proc$libresoc.v:133341$5173 assign { } { } assign $0\src_r2[0:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[0:0] end - attribute \src "libresoc.v:132327.3-132328.29" - process $proc$libresoc.v:132327$5174 + attribute \src "libresoc.v:133343.3-133344.29" + process $proc$libresoc.v:133343$5174 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:132329.3-132330.29" - process $proc$libresoc.v:132329$5175 + attribute \src "libresoc.v:133345.3-133346.29" + process $proc$libresoc.v:133345$5175 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:132331.3-132332.47" - process $proc$libresoc.v:132331$5176 + attribute \src "libresoc.v:133347.3-133348.47" + process $proc$libresoc.v:133347$5176 assign { } { } assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next sync posedge \coresync_clk update \data_r3__xer_so $0\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:132333.3-132334.53" - process $proc$libresoc.v:132333$5177 + attribute \src "libresoc.v:133349.3-133350.53" + process $proc$libresoc.v:133349$5177 assign { } { } assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next sync posedge \coresync_clk update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:132335.3-132336.47" - process $proc$libresoc.v:132335$5178 + attribute \src "libresoc.v:133351.3-133352.47" + process $proc$libresoc.v:133351$5178 assign { } { } assign $0\data_r2__xer_ov[1:0] \data_r2__xer_ov$next sync posedge \coresync_clk update \data_r2__xer_ov $0\data_r2__xer_ov[1:0] end - attribute \src "libresoc.v:132337.3-132338.53" - process $proc$libresoc.v:132337$5179 + attribute \src "libresoc.v:133353.3-133354.53" + process $proc$libresoc.v:133353$5179 assign { } { } assign $0\data_r2__xer_ov_ok[0:0] \data_r2__xer_ov_ok$next sync posedge \coresync_clk update \data_r2__xer_ov_ok $0\data_r2__xer_ov_ok[0:0] end - attribute \src "libresoc.v:132339.3-132340.43" - process $proc$libresoc.v:132339$5180 + attribute \src "libresoc.v:133355.3-133356.43" + process $proc$libresoc.v:133355$5180 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:132341.3-132342.49" - process $proc$libresoc.v:132341$5181 + attribute \src "libresoc.v:133357.3-133358.49" + process $proc$libresoc.v:133357$5181 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:132343.3-132344.37" - process $proc$libresoc.v:132343$5182 + attribute \src "libresoc.v:133359.3-133360.37" + process $proc$libresoc.v:133359$5182 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:132345.3-132346.43" - process $proc$libresoc.v:132345$5183 + attribute \src "libresoc.v:133361.3-133362.43" + process $proc$libresoc.v:133361$5183 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:132347.3-132348.77" - process $proc$libresoc.v:132347$5184 + attribute \src "libresoc.v:133363.3-133364.77" + process $proc$libresoc.v:133363$5184 assign { } { } assign $0\alu_div0_logical_op__insn_type[6:0] \alu_div0_logical_op__insn_type$next sync posedge \coresync_clk update \alu_div0_logical_op__insn_type $0\alu_div0_logical_op__insn_type[6:0] end - attribute \src "libresoc.v:132349.3-132350.73" - process $proc$libresoc.v:132349$5185 + attribute \src "libresoc.v:133365.3-133366.73" + process $proc$libresoc.v:133365$5185 assign { } { } assign $0\alu_div0_logical_op__fn_unit[13:0] \alu_div0_logical_op__fn_unit$next sync posedge \coresync_clk update \alu_div0_logical_op__fn_unit $0\alu_div0_logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:132351.3-132352.87" - process $proc$libresoc.v:132351$5186 + attribute \src "libresoc.v:133367.3-133368.87" + process $proc$libresoc.v:133367$5186 assign { } { } assign $0\alu_div0_logical_op__imm_data__data[63:0] \alu_div0_logical_op__imm_data__data$next sync posedge \coresync_clk update \alu_div0_logical_op__imm_data__data $0\alu_div0_logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:132353.3-132354.83" - process $proc$libresoc.v:132353$5187 + attribute \src "libresoc.v:133369.3-133370.83" + process $proc$libresoc.v:133369$5187 assign { } { } assign $0\alu_div0_logical_op__imm_data__ok[0:0] \alu_div0_logical_op__imm_data__ok$next sync posedge \coresync_clk update \alu_div0_logical_op__imm_data__ok $0\alu_div0_logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:132355.3-132356.71" - process $proc$libresoc.v:132355$5188 + attribute \src "libresoc.v:133371.3-133372.71" + process $proc$libresoc.v:133371$5188 assign { } { } assign $0\alu_div0_logical_op__rc__rc[0:0] \alu_div0_logical_op__rc__rc$next sync posedge \coresync_clk update \alu_div0_logical_op__rc__rc $0\alu_div0_logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:132357.3-132358.71" - process $proc$libresoc.v:132357$5189 + attribute \src "libresoc.v:133373.3-133374.71" + process $proc$libresoc.v:133373$5189 assign { } { } assign $0\alu_div0_logical_op__rc__ok[0:0] \alu_div0_logical_op__rc__ok$next sync posedge \coresync_clk update \alu_div0_logical_op__rc__ok $0\alu_div0_logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:132359.3-132360.71" - process $proc$libresoc.v:132359$5190 + attribute \src "libresoc.v:133375.3-133376.71" + process $proc$libresoc.v:133375$5190 assign { } { } assign $0\alu_div0_logical_op__oe__oe[0:0] \alu_div0_logical_op__oe__oe$next sync posedge \coresync_clk update \alu_div0_logical_op__oe__oe $0\alu_div0_logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:132361.3-132362.71" - process $proc$libresoc.v:132361$5191 + attribute \src "libresoc.v:133377.3-133378.71" + process $proc$libresoc.v:133377$5191 assign { } { } assign $0\alu_div0_logical_op__oe__ok[0:0] \alu_div0_logical_op__oe__ok$next sync posedge \coresync_clk update \alu_div0_logical_op__oe__ok $0\alu_div0_logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:132363.3-132364.77" - process $proc$libresoc.v:132363$5192 + attribute \src "libresoc.v:133379.3-133380.77" + process $proc$libresoc.v:133379$5192 assign { } { } assign $0\alu_div0_logical_op__invert_in[0:0] \alu_div0_logical_op__invert_in$next sync posedge \coresync_clk update \alu_div0_logical_op__invert_in $0\alu_div0_logical_op__invert_in[0:0] end - attribute \src "libresoc.v:132365.3-132366.71" - process $proc$libresoc.v:132365$5193 + attribute \src "libresoc.v:133381.3-133382.71" + process $proc$libresoc.v:133381$5193 assign { } { } assign $0\alu_div0_logical_op__zero_a[0:0] \alu_div0_logical_op__zero_a$next sync posedge \coresync_clk update \alu_div0_logical_op__zero_a $0\alu_div0_logical_op__zero_a[0:0] end - attribute \src "libresoc.v:132367.3-132368.81" - process $proc$libresoc.v:132367$5194 + attribute \src "libresoc.v:133383.3-133384.81" + process $proc$libresoc.v:133383$5194 assign { } { } assign $0\alu_div0_logical_op__input_carry[1:0] \alu_div0_logical_op__input_carry$next sync posedge \coresync_clk update \alu_div0_logical_op__input_carry $0\alu_div0_logical_op__input_carry[1:0] end - attribute \src "libresoc.v:132369.3-132370.79" - process $proc$libresoc.v:132369$5195 + attribute \src "libresoc.v:133385.3-133386.79" + process $proc$libresoc.v:133385$5195 assign { } { } assign $0\alu_div0_logical_op__invert_out[0:0] \alu_div0_logical_op__invert_out$next sync posedge \coresync_clk update \alu_div0_logical_op__invert_out $0\alu_div0_logical_op__invert_out[0:0] end - attribute \src "libresoc.v:132371.3-132372.77" - process $proc$libresoc.v:132371$5196 + attribute \src "libresoc.v:133387.3-133388.77" + process $proc$libresoc.v:133387$5196 assign { } { } assign $0\alu_div0_logical_op__write_cr0[0:0] \alu_div0_logical_op__write_cr0$next sync posedge \coresync_clk update \alu_div0_logical_op__write_cr0 $0\alu_div0_logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:132373.3-132374.83" - process $proc$libresoc.v:132373$5197 + attribute \src "libresoc.v:133389.3-133390.83" + process $proc$libresoc.v:133389$5197 assign { } { } assign $0\alu_div0_logical_op__output_carry[0:0] \alu_div0_logical_op__output_carry$next sync posedge \coresync_clk update \alu_div0_logical_op__output_carry $0\alu_div0_logical_op__output_carry[0:0] end - attribute \src "libresoc.v:132375.3-132376.75" - process $proc$libresoc.v:132375$5198 + attribute \src "libresoc.v:133391.3-133392.75" + process $proc$libresoc.v:133391$5198 assign { } { } assign $0\alu_div0_logical_op__is_32bit[0:0] \alu_div0_logical_op__is_32bit$next sync posedge \coresync_clk update \alu_div0_logical_op__is_32bit $0\alu_div0_logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:132377.3-132378.77" - process $proc$libresoc.v:132377$5199 + attribute \src "libresoc.v:133393.3-133394.77" + process $proc$libresoc.v:133393$5199 assign { } { } assign $0\alu_div0_logical_op__is_signed[0:0] \alu_div0_logical_op__is_signed$next sync posedge \coresync_clk update \alu_div0_logical_op__is_signed $0\alu_div0_logical_op__is_signed[0:0] end - attribute \src "libresoc.v:132379.3-132380.75" - process $proc$libresoc.v:132379$5200 + attribute \src "libresoc.v:133395.3-133396.75" + process $proc$libresoc.v:133395$5200 assign { } { } assign $0\alu_div0_logical_op__data_len[3:0] \alu_div0_logical_op__data_len$next sync posedge \coresync_clk update \alu_div0_logical_op__data_len $0\alu_div0_logical_op__data_len[3:0] end - attribute \src "libresoc.v:132381.3-132382.67" - process $proc$libresoc.v:132381$5201 + attribute \src "libresoc.v:133397.3-133398.67" + process $proc$libresoc.v:133397$5201 assign { } { } assign $0\alu_div0_logical_op__insn[31:0] \alu_div0_logical_op__insn$next sync posedge \coresync_clk update \alu_div0_logical_op__insn $0\alu_div0_logical_op__insn[31:0] end - attribute \src "libresoc.v:132383.3-132384.39" - process $proc$libresoc.v:132383$5202 + attribute \src "libresoc.v:133399.3-133400.39" + process $proc$libresoc.v:133399$5202 assign { } { } assign $0\req_l_r_req[3:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[3:0] end - attribute \src "libresoc.v:132385.3-132386.39" - process $proc$libresoc.v:132385$5203 + attribute \src "libresoc.v:133401.3-133402.39" + process $proc$libresoc.v:133401$5203 assign { } { } assign $0\req_l_s_req[3:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[3:0] end - attribute \src "libresoc.v:132387.3-132388.39" - process $proc$libresoc.v:132387$5204 + attribute \src "libresoc.v:133403.3-133404.39" + process $proc$libresoc.v:133403$5204 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "libresoc.v:132389.3-132390.39" - process $proc$libresoc.v:132389$5205 + attribute \src "libresoc.v:133405.3-133406.39" + process $proc$libresoc.v:133405$5205 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:132391.3-132392.39" - process $proc$libresoc.v:132391$5206 + attribute \src "libresoc.v:133407.3-133408.39" + process $proc$libresoc.v:133407$5206 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:132393.3-132394.39" - process $proc$libresoc.v:132393$5207 + attribute \src "libresoc.v:133409.3-133410.39" + process $proc$libresoc.v:133409$5207 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:132395.3-132396.39" - process $proc$libresoc.v:132395$5208 + attribute \src "libresoc.v:133411.3-133412.39" + process $proc$libresoc.v:133411$5208 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:132397.3-132398.39" - process $proc$libresoc.v:132397$5209 + attribute \src "libresoc.v:133413.3-133414.39" + process $proc$libresoc.v:133413$5209 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:132399.3-132400.41" - process $proc$libresoc.v:132399$5210 + attribute \src "libresoc.v:133415.3-133416.41" + process $proc$libresoc.v:133415$5210 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:132401.3-132402.41" - process $proc$libresoc.v:132401$5211 + attribute \src "libresoc.v:133417.3-133418.41" + process $proc$libresoc.v:133417$5211 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:132403.3-132404.37" - process $proc$libresoc.v:132403$5212 + attribute \src "libresoc.v:133419.3-133420.37" + process $proc$libresoc.v:133419$5212 assign { } { } assign $0\prev_wr_go[3:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[3:0] end - attribute \src "libresoc.v:132405.3-132406.40" - process $proc$libresoc.v:132405$5213 + attribute \src "libresoc.v:133421.3-133422.40" + process $proc$libresoc.v:133421$5213 assign { } { } assign $0\alu_done_dly[0:0] \alu_div0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:132407.3-132408.25" - process $proc$libresoc.v:132407$5214 + attribute \src "libresoc.v:133423.3-133424.25" + process $proc$libresoc.v:133423$5214 assign { } { } assign $0\all_rd_dly[0:0] \$10 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:132494.3-132503.6" - process $proc$libresoc.v:132494$5215 + attribute \src "libresoc.v:133510.3-133519.6" + process $proc$libresoc.v:133510$5215 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:132495.5-132495.29" + attribute \src "libresoc.v:133511.5-133511.29" switch \initial - attribute \src "libresoc.v:132495.9-132495.17" + attribute \src "libresoc.v:133511.9-133511.17" case 1'1 case end @@ -209567,14 +210341,14 @@ module \div0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:132504.3-132512.6" - process $proc$libresoc.v:132504$5216 + attribute \src "libresoc.v:133520.3-133528.6" + process $proc$libresoc.v:133520$5216 assign { } { } assign { } { } assign $0\rok_l_s_rdok$next[0:0]$5217 $1\rok_l_s_rdok$next[0:0]$5218 - attribute \src "libresoc.v:132505.5-132505.29" + attribute \src "libresoc.v:133521.5-133521.29" switch \initial - attribute \src "libresoc.v:132505.9-132505.17" + attribute \src "libresoc.v:133521.9-133521.17" case 1'1 case end @@ -209590,14 +210364,14 @@ module \div0 sync always update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$5217 end - attribute \src "libresoc.v:132513.3-132521.6" - process $proc$libresoc.v:132513$5219 + attribute \src "libresoc.v:133529.3-133537.6" + process $proc$libresoc.v:133529$5219 assign { } { } assign { } { } assign $0\rok_l_r_rdok$next[0:0]$5220 $1\rok_l_r_rdok$next[0:0]$5221 - attribute \src "libresoc.v:132514.5-132514.29" + attribute \src "libresoc.v:133530.5-133530.29" switch \initial - attribute \src "libresoc.v:132514.9-132514.17" + attribute \src "libresoc.v:133530.9-133530.17" case 1'1 case end @@ -209613,14 +210387,14 @@ module \div0 sync always update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$5220 end - attribute \src "libresoc.v:132522.3-132530.6" - process $proc$libresoc.v:132522$5222 + attribute \src "libresoc.v:133538.3-133546.6" + process $proc$libresoc.v:133538$5222 assign { } { } assign { } { } assign $0\rst_l_s_rst$next[0:0]$5223 $1\rst_l_s_rst$next[0:0]$5224 - attribute \src "libresoc.v:132523.5-132523.29" + attribute \src "libresoc.v:133539.5-133539.29" switch \initial - attribute \src "libresoc.v:132523.9-132523.17" + attribute \src "libresoc.v:133539.9-133539.17" case 1'1 case end @@ -209636,14 +210410,14 @@ module \div0 sync always update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$5223 end - attribute \src "libresoc.v:132531.3-132539.6" - process $proc$libresoc.v:132531$5225 + attribute \src "libresoc.v:133547.3-133555.6" + process $proc$libresoc.v:133547$5225 assign { } { } assign { } { } assign $0\rst_l_r_rst$next[0:0]$5226 $1\rst_l_r_rst$next[0:0]$5227 - attribute \src "libresoc.v:132532.5-132532.29" + attribute \src "libresoc.v:133548.5-133548.29" switch \initial - attribute \src "libresoc.v:132532.9-132532.17" + attribute \src "libresoc.v:133548.9-133548.17" case 1'1 case end @@ -209659,14 +210433,14 @@ module \div0 sync always update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$5226 end - attribute \src "libresoc.v:132540.3-132548.6" - process $proc$libresoc.v:132540$5228 + attribute \src "libresoc.v:133556.3-133564.6" + process $proc$libresoc.v:133556$5228 assign { } { } assign { } { } assign $0\opc_l_s_opc$next[0:0]$5229 $1\opc_l_s_opc$next[0:0]$5230 - attribute \src "libresoc.v:132541.5-132541.29" + attribute \src "libresoc.v:133557.5-133557.29" switch \initial - attribute \src "libresoc.v:132541.9-132541.17" + attribute \src "libresoc.v:133557.9-133557.17" case 1'1 case end @@ -209682,14 +210456,14 @@ module \div0 sync always update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$5229 end - attribute \src "libresoc.v:132549.3-132557.6" - process $proc$libresoc.v:132549$5231 + attribute \src "libresoc.v:133565.3-133573.6" + process $proc$libresoc.v:133565$5231 assign { } { } assign { } { } assign $0\opc_l_r_opc$next[0:0]$5232 $1\opc_l_r_opc$next[0:0]$5233 - attribute \src "libresoc.v:132550.5-132550.29" + attribute \src "libresoc.v:133566.5-133566.29" switch \initial - attribute \src "libresoc.v:132550.9-132550.17" + attribute \src "libresoc.v:133566.9-133566.17" case 1'1 case end @@ -209705,14 +210479,14 @@ module \div0 sync always update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$5232 end - attribute \src "libresoc.v:132558.3-132566.6" - process $proc$libresoc.v:132558$5234 + attribute \src "libresoc.v:133574.3-133582.6" + process $proc$libresoc.v:133574$5234 assign { } { } assign { } { } assign $0\src_l_s_src$next[2:0]$5235 $1\src_l_s_src$next[2:0]$5236 - attribute \src "libresoc.v:132559.5-132559.29" + attribute \src "libresoc.v:133575.5-133575.29" switch \initial - attribute \src "libresoc.v:132559.9-132559.17" + attribute \src "libresoc.v:133575.9-133575.17" case 1'1 case end @@ -209728,14 +210502,14 @@ module \div0 sync always update \src_l_s_src$next $0\src_l_s_src$next[2:0]$5235 end - attribute \src "libresoc.v:132567.3-132575.6" - process $proc$libresoc.v:132567$5237 + attribute \src "libresoc.v:133583.3-133591.6" + process $proc$libresoc.v:133583$5237 assign { } { } assign { } { } assign $0\src_l_r_src$next[2:0]$5238 $1\src_l_r_src$next[2:0]$5239 - attribute \src "libresoc.v:132568.5-132568.29" + attribute \src "libresoc.v:133584.5-133584.29" switch \initial - attribute \src "libresoc.v:132568.9-132568.17" + attribute \src "libresoc.v:133584.9-133584.17" case 1'1 case end @@ -209751,14 +210525,14 @@ module \div0 sync always update \src_l_r_src$next $0\src_l_r_src$next[2:0]$5238 end - attribute \src "libresoc.v:132576.3-132584.6" - process $proc$libresoc.v:132576$5240 + attribute \src "libresoc.v:133592.3-133600.6" + process $proc$libresoc.v:133592$5240 assign { } { } assign { } { } assign $0\req_l_s_req$next[3:0]$5241 $1\req_l_s_req$next[3:0]$5242 - attribute \src "libresoc.v:132577.5-132577.29" + attribute \src "libresoc.v:133593.5-133593.29" switch \initial - attribute \src "libresoc.v:132577.9-132577.17" + attribute \src "libresoc.v:133593.9-133593.17" case 1'1 case end @@ -209774,14 +210548,14 @@ module \div0 sync always update \req_l_s_req$next $0\req_l_s_req$next[3:0]$5241 end - attribute \src "libresoc.v:132585.3-132593.6" - process $proc$libresoc.v:132585$5243 + attribute \src "libresoc.v:133601.3-133609.6" + process $proc$libresoc.v:133601$5243 assign { } { } assign { } { } assign $0\req_l_r_req$next[3:0]$5244 $1\req_l_r_req$next[3:0]$5245 - attribute \src "libresoc.v:132586.5-132586.29" + attribute \src "libresoc.v:133602.5-133602.29" switch \initial - attribute \src "libresoc.v:132586.9-132586.17" + attribute \src "libresoc.v:133602.9-133602.17" case 1'1 case end @@ -209797,8 +210571,8 @@ module \div0 sync always update \req_l_r_req$next $0\req_l_r_req$next[3:0]$5244 end - attribute \src "libresoc.v:132594.3-132632.6" - process $proc$libresoc.v:132594$5246 + attribute \src "libresoc.v:133610.3-133648.6" + process $proc$libresoc.v:133610$5246 assign { } { } assign { } { } assign { } { } @@ -209859,9 +210633,9 @@ module \div0 assign $0\alu_div0_logical_op__oe__ok$next[0:0]$5259 $2\alu_div0_logical_op__oe__ok$next[0:0]$5286 assign $0\alu_div0_logical_op__rc__ok$next[0:0]$5261 $2\alu_div0_logical_op__rc__ok$next[0:0]$5287 assign $0\alu_div0_logical_op__rc__rc$next[0:0]$5262 $2\alu_div0_logical_op__rc__rc$next[0:0]$5288 - attribute \src "libresoc.v:132595.5-132595.29" + attribute \src "libresoc.v:133611.5-133611.29" switch \initial - attribute \src "libresoc.v:132595.9-132595.17" + attribute \src "libresoc.v:133611.9-133611.17" case 1'1 case end @@ -209952,8 +210726,8 @@ module \div0 update \alu_div0_logical_op__write_cr0$next $0\alu_div0_logical_op__write_cr0$next[0:0]$5263 update \alu_div0_logical_op__zero_a$next $0\alu_div0_logical_op__zero_a$next[0:0]$5264 end - attribute \src "libresoc.v:132633.3-132654.6" - process $proc$libresoc.v:132633$5289 + attribute \src "libresoc.v:133649.3-133670.6" + process $proc$libresoc.v:133649$5289 assign { } { } assign { } { } assign { } { } @@ -209963,9 +210737,9 @@ module \div0 assign $0\data_r0__o$next[63:0]$5290 $2\data_r0__o$next[63:0]$5294 assign { } { } assign $0\data_r0__o_ok$next[0:0]$5291 $3\data_r0__o_ok$next[0:0]$5296 - attribute \src "libresoc.v:132634.5-132634.29" + attribute \src "libresoc.v:133650.5-133650.29" switch \initial - attribute \src "libresoc.v:132634.9-132634.17" + attribute \src "libresoc.v:133650.9-133650.17" case 1'1 case end @@ -210004,8 +210778,8 @@ module \div0 update \data_r0__o$next $0\data_r0__o$next[63:0]$5290 update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$5291 end - attribute \src "libresoc.v:132655.3-132676.6" - process $proc$libresoc.v:132655$5297 + attribute \src "libresoc.v:133671.3-133692.6" + process $proc$libresoc.v:133671$5297 assign { } { } assign { } { } assign { } { } @@ -210015,9 +210789,9 @@ module \div0 assign $0\data_r1__cr_a$next[3:0]$5298 $2\data_r1__cr_a$next[3:0]$5302 assign { } { } assign $0\data_r1__cr_a_ok$next[0:0]$5299 $3\data_r1__cr_a_ok$next[0:0]$5304 - attribute \src "libresoc.v:132656.5-132656.29" + attribute \src "libresoc.v:133672.5-133672.29" switch \initial - attribute \src "libresoc.v:132656.9-132656.17" + attribute \src "libresoc.v:133672.9-133672.17" case 1'1 case end @@ -210056,8 +210830,8 @@ module \div0 update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$5298 update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$5299 end - attribute \src "libresoc.v:132677.3-132698.6" - process $proc$libresoc.v:132677$5305 + attribute \src "libresoc.v:133693.3-133714.6" + process $proc$libresoc.v:133693$5305 assign { } { } assign { } { } assign { } { } @@ -210067,9 +210841,9 @@ module \div0 assign $0\data_r2__xer_ov$next[1:0]$5306 $2\data_r2__xer_ov$next[1:0]$5310 assign { } { } assign $0\data_r2__xer_ov_ok$next[0:0]$5307 $3\data_r2__xer_ov_ok$next[0:0]$5312 - attribute \src "libresoc.v:132678.5-132678.29" + attribute \src "libresoc.v:133694.5-133694.29" switch \initial - attribute \src "libresoc.v:132678.9-132678.17" + attribute \src "libresoc.v:133694.9-133694.17" case 1'1 case end @@ -210108,8 +210882,8 @@ module \div0 update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$5306 update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$5307 end - attribute \src "libresoc.v:132699.3-132720.6" - process $proc$libresoc.v:132699$5313 + attribute \src "libresoc.v:133715.3-133736.6" + process $proc$libresoc.v:133715$5313 assign { } { } assign { } { } assign { } { } @@ -210119,9 +210893,9 @@ module \div0 assign $0\data_r3__xer_so$next[0:0]$5314 $2\data_r3__xer_so$next[0:0]$5318 assign { } { } assign $0\data_r3__xer_so_ok$next[0:0]$5315 $3\data_r3__xer_so_ok$next[0:0]$5320 - attribute \src "libresoc.v:132700.5-132700.29" + attribute \src "libresoc.v:133716.5-133716.29" switch \initial - attribute \src "libresoc.v:132700.9-132700.17" + attribute \src "libresoc.v:133716.9-133716.17" case 1'1 case end @@ -210160,14 +210934,14 @@ module \div0 update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$5314 update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$5315 end - attribute \src "libresoc.v:132721.3-132730.6" - process $proc$libresoc.v:132721$5321 + attribute \src "libresoc.v:133737.3-133746.6" + process $proc$libresoc.v:133737$5321 assign { } { } assign { } { } assign $0\src_r0$next[63:0]$5322 $1\src_r0$next[63:0]$5323 - attribute \src "libresoc.v:132722.5-132722.29" + attribute \src "libresoc.v:133738.5-133738.29" switch \initial - attribute \src "libresoc.v:132722.9-132722.17" + attribute \src "libresoc.v:133738.9-133738.17" case 1'1 case end @@ -210183,14 +210957,14 @@ module \div0 sync always update \src_r0$next $0\src_r0$next[63:0]$5322 end - attribute \src "libresoc.v:132731.3-132740.6" - process $proc$libresoc.v:132731$5324 + attribute \src "libresoc.v:133747.3-133756.6" + process $proc$libresoc.v:133747$5324 assign { } { } assign { } { } assign $0\src_r1$next[63:0]$5325 $1\src_r1$next[63:0]$5326 - attribute \src "libresoc.v:132732.5-132732.29" + attribute \src "libresoc.v:133748.5-133748.29" switch \initial - attribute \src "libresoc.v:132732.9-132732.17" + attribute \src "libresoc.v:133748.9-133748.17" case 1'1 case end @@ -210206,14 +210980,14 @@ module \div0 sync always update \src_r1$next $0\src_r1$next[63:0]$5325 end - attribute \src "libresoc.v:132741.3-132750.6" - process $proc$libresoc.v:132741$5327 + attribute \src "libresoc.v:133757.3-133766.6" + process $proc$libresoc.v:133757$5327 assign { } { } assign { } { } assign $0\src_r2$next[0:0]$5328 $1\src_r2$next[0:0]$5329 - attribute \src "libresoc.v:132742.5-132742.29" + attribute \src "libresoc.v:133758.5-133758.29" switch \initial - attribute \src "libresoc.v:132742.9-132742.17" + attribute \src "libresoc.v:133758.9-133758.17" case 1'1 case end @@ -210229,14 +211003,14 @@ module \div0 sync always update \src_r2$next $0\src_r2$next[0:0]$5328 end - attribute \src "libresoc.v:132751.3-132759.6" - process $proc$libresoc.v:132751$5330 + attribute \src "libresoc.v:133767.3-133775.6" + process $proc$libresoc.v:133767$5330 assign { } { } assign { } { } assign $0\alui_l_r_alui$next[0:0]$5331 $1\alui_l_r_alui$next[0:0]$5332 - attribute \src "libresoc.v:132752.5-132752.29" + attribute \src "libresoc.v:133768.5-133768.29" switch \initial - attribute \src "libresoc.v:132752.9-132752.17" + attribute \src "libresoc.v:133768.9-133768.17" case 1'1 case end @@ -210252,14 +211026,14 @@ module \div0 sync always update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$5331 end - attribute \src "libresoc.v:132760.3-132768.6" - process $proc$libresoc.v:132760$5333 + attribute \src "libresoc.v:133776.3-133784.6" + process $proc$libresoc.v:133776$5333 assign { } { } assign { } { } assign $0\alu_l_r_alu$next[0:0]$5334 $1\alu_l_r_alu$next[0:0]$5335 - attribute \src "libresoc.v:132761.5-132761.29" + attribute \src "libresoc.v:133777.5-133777.29" switch \initial - attribute \src "libresoc.v:132761.9-132761.17" + attribute \src "libresoc.v:133777.9-133777.17" case 1'1 case end @@ -210275,14 +211049,14 @@ module \div0 sync always update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$5334 end - attribute \src "libresoc.v:132769.3-132778.6" - process $proc$libresoc.v:132769$5336 + attribute \src "libresoc.v:133785.3-133794.6" + process $proc$libresoc.v:133785$5336 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:132770.5-132770.29" + attribute \src "libresoc.v:133786.5-133786.29" switch \initial - attribute \src "libresoc.v:132770.9-132770.17" + attribute \src "libresoc.v:133786.9-133786.17" case 1'1 case end @@ -210298,14 +211072,14 @@ module \div0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:132779.3-132788.6" - process $proc$libresoc.v:132779$5337 + attribute \src "libresoc.v:133795.3-133804.6" + process $proc$libresoc.v:133795$5337 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:132780.5-132780.29" + attribute \src "libresoc.v:133796.5-133796.29" switch \initial - attribute \src "libresoc.v:132780.9-132780.17" + attribute \src "libresoc.v:133796.9-133796.17" case 1'1 case end @@ -210321,14 +211095,14 @@ module \div0 sync always update \dest2_o $0\dest2_o[3:0] end - attribute \src "libresoc.v:132789.3-132798.6" - process $proc$libresoc.v:132789$5338 + attribute \src "libresoc.v:133805.3-133814.6" + process $proc$libresoc.v:133805$5338 assign { } { } assign { } { } assign $0\dest3_o[1:0] $1\dest3_o[1:0] - attribute \src "libresoc.v:132790.5-132790.29" + attribute \src "libresoc.v:133806.5-133806.29" switch \initial - attribute \src "libresoc.v:132790.9-132790.17" + attribute \src "libresoc.v:133806.9-133806.17" case 1'1 case end @@ -210344,14 +211118,14 @@ module \div0 sync always update \dest3_o $0\dest3_o[1:0] end - attribute \src "libresoc.v:132799.3-132808.6" - process $proc$libresoc.v:132799$5339 + attribute \src "libresoc.v:133815.3-133824.6" + process $proc$libresoc.v:133815$5339 assign { } { } assign { } { } assign $0\dest4_o[0:0] $1\dest4_o[0:0] - attribute \src "libresoc.v:132800.5-132800.29" + attribute \src "libresoc.v:133816.5-133816.29" switch \initial - attribute \src "libresoc.v:132800.9-132800.17" + attribute \src "libresoc.v:133816.9-133816.17" case 1'1 case end @@ -210367,14 +211141,14 @@ module \div0 sync always update \dest4_o $0\dest4_o[0:0] end - attribute \src "libresoc.v:132809.3-132817.6" - process $proc$libresoc.v:132809$5340 + attribute \src "libresoc.v:133825.3-133833.6" + process $proc$libresoc.v:133825$5340 assign { } { } assign { } { } assign $0\prev_wr_go$next[3:0]$5341 $1\prev_wr_go$next[3:0]$5342 - attribute \src "libresoc.v:132810.5-132810.29" + attribute \src "libresoc.v:133826.5-133826.29" switch \initial - attribute \src "libresoc.v:132810.9-132810.17" + attribute \src "libresoc.v:133826.9-133826.17" case 1'1 case end @@ -210390,69 +211164,69 @@ module \div0 sync always update \prev_wr_go$next $0\prev_wr_go$next[3:0]$5341 end - connect \$100 $not$libresoc.v:132258$5108_Y - connect \$102 $not$libresoc.v:132259$5109_Y - connect \$104 $and$libresoc.v:132260$5110_Y - connect \$106 $not$libresoc.v:132261$5111_Y - connect \$108 $and$libresoc.v:132262$5112_Y - connect \$10 $and$libresoc.v:132263$5113_Y - connect \$110 $and$libresoc.v:132264$5114_Y - connect \$112 $and$libresoc.v:132265$5115_Y - connect \$114 $and$libresoc.v:132266$5116_Y - connect \$116 $and$libresoc.v:132267$5117_Y - connect \$118 $and$libresoc.v:132268$5118_Y - connect \$120 $and$libresoc.v:132269$5119_Y - connect \$122 $and$libresoc.v:132270$5120_Y - connect \$124 $and$libresoc.v:132271$5121_Y - connect \$126 $and$libresoc.v:132272$5122_Y - connect \$128 $and$libresoc.v:132273$5123_Y - connect \$12 $not$libresoc.v:132274$5124_Y - connect \$14 $and$libresoc.v:132275$5125_Y - connect \$16 $not$libresoc.v:132276$5126_Y - connect \$18 $and$libresoc.v:132277$5127_Y - connect \$20 $and$libresoc.v:132278$5128_Y - connect \$24 $not$libresoc.v:132279$5129_Y - connect \$26 $and$libresoc.v:132280$5130_Y - connect \$23 $reduce_or$libresoc.v:132281$5131_Y - connect \$22 $not$libresoc.v:132282$5132_Y - connect \$2 $and$libresoc.v:132283$5133_Y - connect \$30 $and$libresoc.v:132284$5134_Y - connect \$32 $reduce_or$libresoc.v:132285$5135_Y - connect \$34 $reduce_or$libresoc.v:132286$5136_Y - connect \$36 $or$libresoc.v:132287$5137_Y - connect \$38 $not$libresoc.v:132288$5138_Y - connect \$40 $and$libresoc.v:132289$5139_Y - connect \$42 $and$libresoc.v:132290$5140_Y - connect \$44 $eq$libresoc.v:132291$5141_Y - connect \$46 $and$libresoc.v:132292$5142_Y - connect \$48 $eq$libresoc.v:132293$5143_Y - connect \$50 $and$libresoc.v:132294$5144_Y - connect \$52 $and$libresoc.v:132295$5145_Y - connect \$54 $and$libresoc.v:132296$5146_Y - connect \$56 $or$libresoc.v:132297$5147_Y - connect \$58 $or$libresoc.v:132298$5148_Y - connect \$5 $not$libresoc.v:132299$5149_Y - connect \$60 $or$libresoc.v:132300$5150_Y - connect \$62 $or$libresoc.v:132301$5151_Y - connect \$64 $and$libresoc.v:132302$5152_Y - connect \$66 $and$libresoc.v:132303$5153_Y - connect \$68 $or$libresoc.v:132304$5154_Y - connect \$70 $and$libresoc.v:132305$5155_Y - connect \$72 $and$libresoc.v:132306$5156_Y - connect \$74 $and$libresoc.v:132307$5157_Y - connect \$76 $and$libresoc.v:132308$5158_Y - connect \$78 $ternary$libresoc.v:132309$5159_Y - connect \$7 $or$libresoc.v:132310$5160_Y - connect \$80 $ternary$libresoc.v:132311$5161_Y - connect \$83 $ternary$libresoc.v:132312$5162_Y - connect \$86 $ternary$libresoc.v:132313$5163_Y - connect \$88 $ternary$libresoc.v:132314$5164_Y - connect \$4 $reduce_and$libresoc.v:132315$5165_Y - connect \$90 $ternary$libresoc.v:132316$5166_Y - connect \$92 $ternary$libresoc.v:132317$5167_Y - connect \$94 $and$libresoc.v:132318$5168_Y - connect \$96 $and$libresoc.v:132319$5169_Y - connect \$98 $and$libresoc.v:132320$5170_Y + connect \$100 $not$libresoc.v:133274$5108_Y + connect \$102 $not$libresoc.v:133275$5109_Y + connect \$104 $and$libresoc.v:133276$5110_Y + connect \$106 $not$libresoc.v:133277$5111_Y + connect \$108 $and$libresoc.v:133278$5112_Y + connect \$10 $and$libresoc.v:133279$5113_Y + connect \$110 $and$libresoc.v:133280$5114_Y + connect \$112 $and$libresoc.v:133281$5115_Y + connect \$114 $and$libresoc.v:133282$5116_Y + connect \$116 $and$libresoc.v:133283$5117_Y + connect \$118 $and$libresoc.v:133284$5118_Y + connect \$120 $and$libresoc.v:133285$5119_Y + connect \$122 $and$libresoc.v:133286$5120_Y + connect \$124 $and$libresoc.v:133287$5121_Y + connect \$126 $and$libresoc.v:133288$5122_Y + connect \$128 $and$libresoc.v:133289$5123_Y + connect \$12 $not$libresoc.v:133290$5124_Y + connect \$14 $and$libresoc.v:133291$5125_Y + connect \$16 $not$libresoc.v:133292$5126_Y + connect \$18 $and$libresoc.v:133293$5127_Y + connect \$20 $and$libresoc.v:133294$5128_Y + connect \$24 $not$libresoc.v:133295$5129_Y + connect \$26 $and$libresoc.v:133296$5130_Y + connect \$23 $reduce_or$libresoc.v:133297$5131_Y + connect \$22 $not$libresoc.v:133298$5132_Y + connect \$2 $and$libresoc.v:133299$5133_Y + connect \$30 $and$libresoc.v:133300$5134_Y + connect \$32 $reduce_or$libresoc.v:133301$5135_Y + connect \$34 $reduce_or$libresoc.v:133302$5136_Y + connect \$36 $or$libresoc.v:133303$5137_Y + connect \$38 $not$libresoc.v:133304$5138_Y + connect \$40 $and$libresoc.v:133305$5139_Y + connect \$42 $and$libresoc.v:133306$5140_Y + connect \$44 $eq$libresoc.v:133307$5141_Y + connect \$46 $and$libresoc.v:133308$5142_Y + connect \$48 $eq$libresoc.v:133309$5143_Y + connect \$50 $and$libresoc.v:133310$5144_Y + connect \$52 $and$libresoc.v:133311$5145_Y + connect \$54 $and$libresoc.v:133312$5146_Y + connect \$56 $or$libresoc.v:133313$5147_Y + connect \$58 $or$libresoc.v:133314$5148_Y + connect \$5 $not$libresoc.v:133315$5149_Y + connect \$60 $or$libresoc.v:133316$5150_Y + connect \$62 $or$libresoc.v:133317$5151_Y + connect \$64 $and$libresoc.v:133318$5152_Y + connect \$66 $and$libresoc.v:133319$5153_Y + connect \$68 $or$libresoc.v:133320$5154_Y + connect \$70 $and$libresoc.v:133321$5155_Y + connect \$72 $and$libresoc.v:133322$5156_Y + connect \$74 $and$libresoc.v:133323$5157_Y + connect \$76 $and$libresoc.v:133324$5158_Y + connect \$78 $ternary$libresoc.v:133325$5159_Y + connect \$7 $or$libresoc.v:133326$5160_Y + connect \$80 $ternary$libresoc.v:133327$5161_Y + connect \$83 $ternary$libresoc.v:133328$5162_Y + connect \$86 $ternary$libresoc.v:133329$5163_Y + connect \$88 $ternary$libresoc.v:133330$5164_Y + connect \$4 $reduce_and$libresoc.v:133331$5165_Y + connect \$90 $ternary$libresoc.v:133332$5166_Y + connect \$92 $ternary$libresoc.v:133333$5167_Y + connect \$94 $and$libresoc.v:133334$5168_Y + connect \$96 $and$libresoc.v:133335$5169_Y + connect \$98 $and$libresoc.v:133336$5170_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$120 @@ -210486,7 +211260,7 @@ module \div0 connect \all_rd_dly$next \all_rd connect \all_rd \$10 end -attribute \src "libresoc.v:132854.1-132863.10" +attribute \src "libresoc.v:133870.1-133879.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.div_state_init" attribute \generator "nMigen" @@ -210500,37 +211274,37 @@ module \div_state_init connect \o_dividend_quotient \dividend connect \o_q_bits_known 7'0000000 end -attribute \src "libresoc.v:132867.1-132949.10" +attribute \src "libresoc.v:133883.1-133965.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.div_state_next" attribute \generator "nMigen" module \div_state_next - attribute \src "libresoc.v:132868.7-132868.20" + attribute \src "libresoc.v:133884.7-133884.20" wire $0\initial[0:0] - attribute \src "libresoc.v:132933.3-132944.6" + attribute \src "libresoc.v:133949.3-133960.6" wire width 128 $0\o_dividend_quotient[127:0] - attribute \src "libresoc.v:132921.3-132932.6" + attribute \src "libresoc.v:133937.3-133948.6" wire width 7 $0\o_q_bits_known[6:0] - attribute \src "libresoc.v:132909.3-132920.6" + attribute \src "libresoc.v:133925.3-133936.6" wire width 128 $0\value[127:0] - attribute \src "libresoc.v:132933.3-132944.6" + attribute \src "libresoc.v:133949.3-133960.6" wire width 128 $1\o_dividend_quotient[127:0] - attribute \src "libresoc.v:132921.3-132932.6" + attribute \src "libresoc.v:133937.3-133948.6" wire width 7 $1\o_q_bits_known[6:0] - attribute \src "libresoc.v:132909.3-132920.6" + attribute \src "libresoc.v:133925.3-133936.6" wire width 128 $1\value[127:0] - attribute \src "libresoc.v:132903.18-132903.106" - wire width 8 $add$libresoc.v:132903$5388_Y - attribute \src "libresoc.v:132904.18-132904.109" - wire $ge$libresoc.v:132904$5389_Y - attribute \src "libresoc.v:132908.17-132908.108" - wire $ge$libresoc.v:132908$5393_Y - attribute \src "libresoc.v:132907.17-132907.101" - wire $not$libresoc.v:132907$5392_Y - attribute \src "libresoc.v:132905.17-132905.101" - wire width 127 $sshl$libresoc.v:132905$5390_Y - attribute \src "libresoc.v:132906.17-132906.109" - wire width 129 $sub$libresoc.v:132906$5391_Y + attribute \src "libresoc.v:133919.18-133919.106" + wire width 8 $add$libresoc.v:133919$5388_Y + attribute \src "libresoc.v:133920.18-133920.109" + wire $ge$libresoc.v:133920$5389_Y + attribute \src "libresoc.v:133924.17-133924.108" + wire $ge$libresoc.v:133924$5393_Y + attribute \src "libresoc.v:133923.17-133923.101" + wire $not$libresoc.v:133923$5392_Y + attribute \src "libresoc.v:133921.17-133921.101" + wire width 127 $sshl$libresoc.v:133921$5390_Y + attribute \src "libresoc.v:133922.17-133922.109" + wire width 129 $sub$libresoc.v:133922$5391_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" wire width 129 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81" @@ -210555,7 +211329,7 @@ module \div_state_next wire width 128 input 3 \i_dividend_quotient attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" wire width 7 input 2 \i_q_bits_known - attribute \src "libresoc.v:132868.7-132868.15" + attribute \src "libresoc.v:133884.7-133884.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:68" wire \next_quotient_bit @@ -210566,7 +211340,7 @@ module \div_state_next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:71" wire width 128 \value attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81" - cell $add $add$libresoc.v:132903$5388 + cell $add $add$libresoc.v:133919$5388 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -210574,10 +211348,10 @@ module \div_state_next parameter \Y_WIDTH 8 connect \A \i_q_bits_known connect \B 1'1 - connect \Y $add$libresoc.v:132903$5388_Y + connect \Y $add$libresoc.v:133919$5388_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" - cell $ge $ge$libresoc.v:132904$5389 + cell $ge $ge$libresoc.v:133920$5389 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -210585,10 +211359,10 @@ module \div_state_next parameter \Y_WIDTH 1 connect \A \i_q_bits_known connect \B 7'1000000 - connect \Y $ge$libresoc.v:132904$5389_Y + connect \Y $ge$libresoc.v:133920$5389_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" - cell $ge $ge$libresoc.v:132908$5393 + cell $ge $ge$libresoc.v:133924$5393 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -210596,18 +211370,18 @@ module \div_state_next parameter \Y_WIDTH 1 connect \A \i_q_bits_known connect \B 7'1000000 - connect \Y $ge$libresoc.v:132908$5393_Y + connect \Y $ge$libresoc.v:133924$5393_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:70" - cell $not $not$libresoc.v:132907$5392 + cell $not $not$libresoc.v:133923$5392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \difference [127] - connect \Y $not$libresoc.v:132907$5392_Y + connect \Y $not$libresoc.v:133923$5392_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" - cell $sshl $sshl$libresoc.v:132905$5390 + cell $sshl $sshl$libresoc.v:133921$5390 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -210615,10 +211389,10 @@ module \div_state_next parameter \Y_WIDTH 127 connect \A \divisor connect \B 6'111111 - connect \Y $sshl$libresoc.v:132905$5390_Y + connect \Y $sshl$libresoc.v:133921$5390_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" - cell $sub $sub$libresoc.v:132906$5391 + cell $sub $sub$libresoc.v:133922$5391 parameter \A_SIGNED 0 parameter \A_WIDTH 128 parameter \B_SIGNED 0 @@ -210626,23 +211400,23 @@ module \div_state_next parameter \Y_WIDTH 129 connect \A \i_dividend_quotient connect \B \$2 - connect \Y $sub$libresoc.v:132906$5391_Y + connect \Y $sub$libresoc.v:133922$5391_Y end - attribute \src "libresoc.v:132868.7-132868.20" - process $proc$libresoc.v:132868$5397 + attribute \src "libresoc.v:133884.7-133884.20" + process $proc$libresoc.v:133884$5397 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:132909.3-132920.6" - process $proc$libresoc.v:132909$5394 + attribute \src "libresoc.v:133925.3-133936.6" + process $proc$libresoc.v:133925$5394 assign { } { } assign $0\value[127:0] $1\value[127:0] - attribute \src "libresoc.v:132910.5-132910.29" + attribute \src "libresoc.v:133926.5-133926.29" switch \initial - attribute \src "libresoc.v:132910.9-132910.17" + attribute \src "libresoc.v:133926.9-133926.17" case 1'1 case end @@ -210660,13 +211434,13 @@ module \div_state_next sync always update \value $0\value[127:0] end - attribute \src "libresoc.v:132921.3-132932.6" - process $proc$libresoc.v:132921$5395 + attribute \src "libresoc.v:133937.3-133948.6" + process $proc$libresoc.v:133937$5395 assign { } { } assign $0\o_q_bits_known[6:0] $1\o_q_bits_known[6:0] - attribute \src "libresoc.v:132922.5-132922.29" + attribute \src "libresoc.v:133938.5-133938.29" switch \initial - attribute \src "libresoc.v:132922.9-132922.17" + attribute \src "libresoc.v:133938.9-133938.17" case 1'1 case end @@ -210684,13 +211458,13 @@ module \div_state_next sync always update \o_q_bits_known $0\o_q_bits_known[6:0] end - attribute \src "libresoc.v:132933.3-132944.6" - process $proc$libresoc.v:132933$5396 + attribute \src "libresoc.v:133949.3-133960.6" + process $proc$libresoc.v:133949$5396 assign { } { } assign $0\o_dividend_quotient[127:0] $1\o_dividend_quotient[127:0] - attribute \src "libresoc.v:132934.5-132934.29" + attribute \src "libresoc.v:133950.5-133950.29" switch \initial - attribute \src "libresoc.v:132934.9-132934.17" + attribute \src "libresoc.v:133950.9-133950.17" case 1'1 case end @@ -210708,18 +211482,18 @@ module \div_state_next sync always update \o_dividend_quotient $0\o_dividend_quotient[127:0] end - connect \$11 $add$libresoc.v:132903$5388_Y - connect \$13 $ge$libresoc.v:132904$5389_Y - connect \$2 $sshl$libresoc.v:132905$5390_Y - connect \$4 $sub$libresoc.v:132906$5391_Y - connect \$6 $not$libresoc.v:132907$5392_Y - connect \$8 $ge$libresoc.v:132908$5393_Y + connect \$11 $add$libresoc.v:133919$5388_Y + connect \$13 $ge$libresoc.v:133920$5389_Y + connect \$2 $sshl$libresoc.v:133921$5390_Y + connect \$4 $sub$libresoc.v:133922$5391_Y + connect \$6 $not$libresoc.v:133923$5392_Y + connect \$8 $ge$libresoc.v:133924$5393_Y connect \$1 \$4 connect \$10 \$11 connect \next_quotient_bit \$6 connect \difference \$4 [127:0] end -attribute \src "libresoc.v:132953.1-133196.10" +attribute \src "libresoc.v:133969.1-134212.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.dummy" attribute \generator "nMigen" @@ -210967,94 +211741,106 @@ module \dummy connect { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } connect \muxid$1 \muxid end -attribute \src "libresoc.v:133200.1-133371.10" +attribute \src "libresoc.v:134216.1-134387.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fast" attribute \generator "nMigen" module \fast - attribute \src "libresoc.v:133295.3-133301.6" - wire width 3 $0$memwr$\memory$libresoc.v:133299$5406_ADDR[2:0]$5414 - attribute \src "libresoc.v:133295.3-133301.6" - wire width 64 $0$memwr$\memory$libresoc.v:133299$5406_DATA[63:0]$5415 - attribute \src "libresoc.v:133295.3-133301.6" - wire width 64 $0$memwr$\memory$libresoc.v:133299$5406_EN[63:0]$5416 - attribute \src "libresoc.v:133295.3-133301.6" - wire width 3 $0$memwr$\memory$libresoc.v:133300$5407_ADDR[2:0]$5417 - attribute \src "libresoc.v:133295.3-133301.6" - wire width 64 $0$memwr$\memory$libresoc.v:133300$5407_DATA[63:0]$5418 - attribute \src "libresoc.v:133295.3-133301.6" - wire width 64 $0$memwr$\memory$libresoc.v:133300$5407_EN[63:0]$5419 - attribute \src "libresoc.v:133295.3-133301.6" + attribute \src "libresoc.v:134305.3-134311.6" + wire width 3 $0$memwr$\memory$libresoc.v:134309$5406_ADDR[2:0]$5409 + attribute \src "libresoc.v:134305.3-134311.6" + wire width 64 $0$memwr$\memory$libresoc.v:134309$5406_DATA[63:0]$5410 + attribute \src "libresoc.v:134305.3-134311.6" + wire width 64 $0$memwr$\memory$libresoc.v:134309$5406_EN[63:0]$5411 + attribute \src "libresoc.v:134305.3-134311.6" + wire width 3 $0$memwr$\memory$libresoc.v:134310$5407_ADDR[2:0]$5412 + attribute \src "libresoc.v:134305.3-134311.6" + wire width 64 $0$memwr$\memory$libresoc.v:134310$5407_DATA[63:0]$5413 + attribute \src "libresoc.v:134305.3-134311.6" + wire width 64 $0$memwr$\memory$libresoc.v:134310$5407_EN[63:0]$5414 + attribute \src "libresoc.v:134305.3-134311.6" wire width 3 $0\_0_[2:0] - attribute \src "libresoc.v:133295.3-133301.6" + attribute \src "libresoc.v:134305.3-134311.6" wire width 3 $0\_1_[2:0] - attribute \src "libresoc.v:133295.3-133301.6" + attribute \src "libresoc.v:134305.3-134311.6" wire width 3 $0\_2_[2:0] - attribute \src "libresoc.v:133201.7-133201.20" + attribute \src "libresoc.v:134217.7-134217.20" wire $0\initial[0:0] - attribute \src "libresoc.v:133352.3-133361.6" + attribute \src "libresoc.v:134368.3-134377.6" wire width 64 $0\issue__data_o[63:0] - attribute \src "libresoc.v:133324.3-133332.6" - wire $0\ren_delay$10$next[0:0]$5428 - attribute \src "libresoc.v:133277.3-133278.43" - wire $0\ren_delay$10[0:0]$5411 - attribute \src "libresoc.v:133252.7-133252.28" - wire $0\ren_delay$10[0:0]$5448 - attribute \src "libresoc.v:133343.3-133351.6" - wire $0\ren_delay$11$next[0:0]$5432 - attribute \src "libresoc.v:133275.3-133276.43" - wire $0\ren_delay$11[0:0]$5409 - attribute \src "libresoc.v:133256.7-133256.28" - wire $0\ren_delay$11[0:0]$5450 - attribute \src "libresoc.v:133305.3-133313.6" - wire $0\ren_delay$next[0:0]$5424 - attribute \src "libresoc.v:133279.3-133280.35" + attribute \src "libresoc.v:134340.3-134348.6" + wire $0\ren_delay$10$next[0:0]$5434 + attribute \src "libresoc.v:134317.3-134318.43" + wire $0\ren_delay$10[0:0]$5427 + attribute \src "libresoc.v:134268.7-134268.28" + wire $0\ren_delay$10[0:0]$5452 + attribute \src "libresoc.v:134359.3-134367.6" + wire $0\ren_delay$11$next[0:0]$5438 + attribute \src "libresoc.v:134315.3-134316.43" + wire $0\ren_delay$11[0:0]$5425 + attribute \src "libresoc.v:134272.7-134272.28" + wire $0\ren_delay$11[0:0]$5454 + attribute \src "libresoc.v:134321.3-134329.6" + wire $0\ren_delay$next[0:0]$5430 + attribute \src "libresoc.v:134319.3-134320.35" wire $0\ren_delay[0:0] - attribute \src "libresoc.v:133314.3-133323.6" + attribute \src "libresoc.v:134330.3-134339.6" wire width 64 $0\src1__data_o[63:0] - attribute \src "libresoc.v:133333.3-133342.6" + attribute \src "libresoc.v:134349.3-134358.6" wire width 64 $0\src2__data_o[63:0] - attribute \src "libresoc.v:133352.3-133361.6" + attribute \src "libresoc.v:134305.3-134311.6" + wire width 3 $1$memwr$\memory$libresoc.v:134309$5406_ADDR[2:0]$5415 + attribute \src "libresoc.v:134305.3-134311.6" + wire width 64 $1$memwr$\memory$libresoc.v:134309$5406_DATA[63:0]$5416 + attribute \src "libresoc.v:134305.3-134311.6" + wire width 64 $1$memwr$\memory$libresoc.v:134309$5406_EN[63:0]$5417 + attribute \src "libresoc.v:134305.3-134311.6" + wire width 3 $1$memwr$\memory$libresoc.v:134310$5407_ADDR[2:0]$5418 + attribute \src "libresoc.v:134305.3-134311.6" + wire width 64 $1$memwr$\memory$libresoc.v:134310$5407_DATA[63:0]$5419 + attribute \src "libresoc.v:134305.3-134311.6" + wire width 64 $1$memwr$\memory$libresoc.v:134310$5407_EN[63:0]$5420 + attribute \src "libresoc.v:134368.3-134377.6" wire width 64 $1\issue__data_o[63:0] - attribute \src "libresoc.v:133324.3-133332.6" - wire $1\ren_delay$10$next[0:0]$5429 - attribute \src "libresoc.v:133343.3-133351.6" - wire $1\ren_delay$11$next[0:0]$5433 - attribute \src "libresoc.v:133305.3-133313.6" - wire $1\ren_delay$next[0:0]$5425 - attribute \src "libresoc.v:133250.7-133250.23" + attribute \src "libresoc.v:134340.3-134348.6" + wire $1\ren_delay$10$next[0:0]$5435 + attribute \src "libresoc.v:134359.3-134367.6" + wire $1\ren_delay$11$next[0:0]$5439 + attribute \src "libresoc.v:134321.3-134329.6" + wire $1\ren_delay$next[0:0]$5431 + attribute \src "libresoc.v:134266.7-134266.23" wire $1\ren_delay[0:0] - attribute \src "libresoc.v:133314.3-133323.6" + attribute \src "libresoc.v:134330.3-134339.6" wire width 64 $1\src1__data_o[63:0] - attribute \src "libresoc.v:133333.3-133342.6" + attribute \src "libresoc.v:134349.3-134358.6" wire width 64 $1\src2__data_o[63:0] - attribute \src "libresoc.v:133302.26-133302.32" - wire width 64 $memrd$\memory$libresoc.v:133302$5420_DATA - attribute \src "libresoc.v:133303.30-133303.36" - wire width 64 $memrd$\memory$libresoc.v:133303$5421_DATA - attribute \src "libresoc.v:133304.30-133304.36" - wire width 64 $memrd$\memory$libresoc.v:133304$5422_DATA + attribute \src "libresoc.v:134312.26-134312.32" + wire width 64 $memrd$\memory$libresoc.v:134312$5421_DATA + attribute \src "libresoc.v:134313.30-134313.36" + wire width 64 $memrd$\memory$libresoc.v:134313$5422_DATA + attribute \src "libresoc.v:134314.30-134314.36" + wire width 64 $memrd$\memory$libresoc.v:134314$5423_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 3 $memwr$\memory$libresoc.v:133299$5406_ADDR + wire width 3 $memwr$\memory$libresoc.v:134309$5406_ADDR attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:133299$5406_DATA + wire width 64 $memwr$\memory$libresoc.v:134309$5406_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:133299$5406_EN + wire width 64 $memwr$\memory$libresoc.v:134309$5406_EN attribute \src "libresoc.v:0.0-0.0" - wire width 3 $memwr$\memory$libresoc.v:133300$5407_ADDR + wire width 3 $memwr$\memory$libresoc.v:134310$5407_ADDR attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:133300$5407_DATA + wire width 64 $memwr$\memory$libresoc.v:134310$5407_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:133300$5407_EN - attribute \src "libresoc.v:133292.13-133292.16" + wire width 64 $memwr$\memory$libresoc.v:134310$5407_EN + attribute \src "libresoc.v:134302.13-134302.16" wire width 3 \_0_ - attribute \src "libresoc.v:133293.13-133293.16" + attribute \src "libresoc.v:134303.13-134303.16" wire width 3 \_1_ - attribute \src "libresoc.v:133294.13-133294.16" + attribute \src "libresoc.v:134304.13-134304.16" wire width 3 \_2_ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 17 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 15 \dest1__addr @@ -211062,7 +211848,7 @@ module \fast wire width 64 input 14 \dest1__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 16 \dest1__wen - attribute \src "libresoc.v:133201.7-133201.15" + attribute \src "libresoc.v:134217.7-134217.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 2 \issue__addr @@ -211124,90 +211910,90 @@ module \fast wire width 64 output 11 \src2__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 13 \src2__ren - attribute \src "libresoc.v:133281.14-133281.20" + attribute \src "libresoc.v:134291.14-134291.20" memory width 64 size 8 \memory - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5435 + attribute \src "libresoc.v:134293.5-134293.37" + cell $meminit $meminit$\memory$libresoc.v:134293$5441 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5435 + parameter \PRIORITY 5441 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 0 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5436 + attribute \src "libresoc.v:134294.5-134294.37" + cell $meminit $meminit$\memory$libresoc.v:134294$5442 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5436 + parameter \PRIORITY 5442 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 1 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5437 + attribute \src "libresoc.v:134295.5-134295.37" + cell $meminit $meminit$\memory$libresoc.v:134295$5443 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5437 + parameter \PRIORITY 5443 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 2 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5438 + attribute \src "libresoc.v:134296.5-134296.37" + cell $meminit $meminit$\memory$libresoc.v:134296$5444 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5438 + parameter \PRIORITY 5444 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 3 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5439 + attribute \src "libresoc.v:134297.5-134297.37" + cell $meminit $meminit$\memory$libresoc.v:134297$5445 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5439 + parameter \PRIORITY 5445 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 4 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5440 + attribute \src "libresoc.v:134298.5-134298.37" + cell $meminit $meminit$\memory$libresoc.v:134298$5446 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5440 + parameter \PRIORITY 5446 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 5 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5441 + attribute \src "libresoc.v:134299.5-134299.37" + cell $meminit $meminit$\memory$libresoc.v:134299$5447 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5441 + parameter \PRIORITY 5447 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 6 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5442 + attribute \src "libresoc.v:134300.5-134300.37" + cell $meminit $meminit$\memory$libresoc.v:134300$5448 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5442 + parameter \PRIORITY 5448 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 7 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:133302.26-133302.32" - cell $memrd $memrd$\memory$libresoc.v:133302$5420 + attribute \src "libresoc.v:134312.26-134312.32" + cell $memrd $memrd$\memory$libresoc.v:134312$5421 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -211216,11 +212002,11 @@ module \fast parameter \WIDTH 64 connect \ADDR \_0_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:133302$5420_DATA + connect \DATA $memrd$\memory$libresoc.v:134312$5421_DATA connect \EN 1'x end - attribute \src "libresoc.v:133303.30-133303.36" - cell $memrd $memrd$\memory$libresoc.v:133303$5421 + attribute \src "libresoc.v:134313.30-134313.36" + cell $memrd $memrd$\memory$libresoc.v:134313$5422 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -211229,11 +212015,11 @@ module \fast parameter \WIDTH 64 connect \ADDR \_1_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:133303$5421_DATA + connect \DATA $memrd$\memory$libresoc.v:134313$5422_DATA connect \EN 1'x end - attribute \src "libresoc.v:133304.30-133304.36" - cell $memrd $memrd$\memory$libresoc.v:133304$5422 + attribute \src "libresoc.v:134314.30-134314.36" + cell $memrd $memrd$\memory$libresoc.v:134314$5423 parameter \ABITS 3 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -211242,95 +212028,53 @@ module \fast parameter \WIDTH 64 connect \ADDR \_2_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:133304$5422_DATA + connect \DATA $memrd$\memory$libresoc.v:134314$5423_DATA connect \EN 1'x end attribute \src "libresoc.v:0.0-0.0" - cell $memwr $memwr$\memory$libresoc.v:0$5443 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \PRIORITY 5443 - parameter \WIDTH 64 - connect \ADDR $memwr$\memory$libresoc.v:133299$5406_ADDR - connect \CLK 1'x - connect \DATA $memwr$\memory$libresoc.v:133299$5406_DATA - connect \EN $memwr$\memory$libresoc.v:133299$5406_EN - end - attribute \src "libresoc.v:0.0-0.0" - cell $memwr $memwr$\memory$libresoc.v:0$5444 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \PRIORITY 5444 - parameter \WIDTH 64 - connect \ADDR $memwr$\memory$libresoc.v:133300$5407_ADDR - connect \CLK 1'x - connect \DATA $memwr$\memory$libresoc.v:133300$5407_DATA - connect \EN $memwr$\memory$libresoc.v:133300$5407_EN - end - attribute \src "libresoc.v:0.0-0.0" - process $proc$libresoc.v:0$5451 + process $proc$libresoc.v:0$5455 sync always sync init end - attribute \src "libresoc.v:133201.7-133201.20" - process $proc$libresoc.v:133201$5445 + attribute \src "libresoc.v:134217.7-134217.20" + process $proc$libresoc.v:134217$5449 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:133250.7-133250.23" - process $proc$libresoc.v:133250$5446 + attribute \src "libresoc.v:134266.7-134266.23" + process $proc$libresoc.v:134266$5450 assign { } { } assign $1\ren_delay[0:0] 1'0 sync always sync init update \ren_delay $1\ren_delay[0:0] end - attribute \src "libresoc.v:133252.7-133252.28" - process $proc$libresoc.v:133252$5447 + attribute \src "libresoc.v:134268.7-134268.28" + process $proc$libresoc.v:134268$5451 assign { } { } - assign $0\ren_delay$10[0:0]$5448 1'0 + assign $0\ren_delay$10[0:0]$5452 1'0 sync always sync init - update \ren_delay$10 $0\ren_delay$10[0:0]$5448 + update \ren_delay$10 $0\ren_delay$10[0:0]$5452 end - attribute \src "libresoc.v:133256.7-133256.28" - process $proc$libresoc.v:133256$5449 + attribute \src "libresoc.v:134272.7-134272.28" + process $proc$libresoc.v:134272$5453 assign { } { } - assign $0\ren_delay$11[0:0]$5450 1'0 + assign $0\ren_delay$11[0:0]$5454 1'0 sync always sync init - update \ren_delay$11 $0\ren_delay$11[0:0]$5450 + update \ren_delay$11 $0\ren_delay$11[0:0]$5454 end - attribute \src "libresoc.v:133275.3-133276.43" - process $proc$libresoc.v:133275$5408 + attribute \src "libresoc.v:134305.3-134311.6" + process $proc$libresoc.v:134305$5408 + assign { } { } + assign { } { } assign { } { } - assign $0\ren_delay$11[0:0]$5409 \ren_delay$11$next - sync posedge \coresync_clk - update \ren_delay$11 $0\ren_delay$11[0:0]$5409 - end - attribute \src "libresoc.v:133277.3-133278.43" - process $proc$libresoc.v:133277$5410 assign { } { } - assign $0\ren_delay$10[0:0]$5411 \ren_delay$10$next - sync posedge \coresync_clk - update \ren_delay$10 $0\ren_delay$10[0:0]$5411 - end - attribute \src "libresoc.v:133279.3-133280.35" - process $proc$libresoc.v:133279$5412 assign { } { } - assign $0\ren_delay[0:0] \ren_delay$next - sync posedge \coresync_clk - update \ren_delay $0\ren_delay[0:0] - end - attribute \src "libresoc.v:133295.3-133301.6" - process $proc$libresoc.v:133295$5413 assign { } { } assign { } { } assign { } { } @@ -211340,52 +212084,90 @@ module \fast assign { } { } assign { } { } assign { } { } - assign $0$memwr$\memory$libresoc.v:133300$5407_ADDR[2:0]$5417 3'xxx - assign $0$memwr$\memory$libresoc.v:133300$5407_DATA[63:0]$5418 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\memory$libresoc.v:133300$5407_EN[63:0]$5419 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\memory$libresoc.v:133299$5406_ADDR[2:0]$5414 3'xxx - assign $0$memwr$\memory$libresoc.v:133299$5406_DATA[63:0]$5415 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\memory$libresoc.v:133299$5406_EN[63:0]$5416 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\_0_[2:0] \src1__addr - assign $0\_1_[2:0] \src2__addr - assign $0\_2_[2:0] \issue__addr - attribute \src "libresoc.v:133299.5-133299.62" - switch \issue__wen - attribute \src "libresoc.v:133299.9-133299.19" + assign { } { } + assign $0\_0_[2:0] \memory_r_addr + assign $0\_1_[2:0] \memory_r_addr$3 + assign $0\_2_[2:0] \memory_r_addr$5 + assign $0$memwr$\memory$libresoc.v:134309$5406_ADDR[2:0]$5409 $1$memwr$\memory$libresoc.v:134309$5406_ADDR[2:0]$5415 + assign $0$memwr$\memory$libresoc.v:134309$5406_DATA[63:0]$5410 $1$memwr$\memory$libresoc.v:134309$5406_DATA[63:0]$5416 + assign $0$memwr$\memory$libresoc.v:134309$5406_EN[63:0]$5411 $1$memwr$\memory$libresoc.v:134309$5406_EN[63:0]$5417 + assign $0$memwr$\memory$libresoc.v:134310$5407_ADDR[2:0]$5412 $1$memwr$\memory$libresoc.v:134310$5407_ADDR[2:0]$5418 + assign $0$memwr$\memory$libresoc.v:134310$5407_DATA[63:0]$5413 $1$memwr$\memory$libresoc.v:134310$5407_DATA[63:0]$5419 + assign $0$memwr$\memory$libresoc.v:134310$5407_EN[63:0]$5414 $1$memwr$\memory$libresoc.v:134310$5407_EN[63:0]$5420 + attribute \src "libresoc.v:134309.5-134309.61" + switch \memory_w_en + attribute \src "libresoc.v:134309.9-134309.20" case 1'1 - assign $0$memwr$\memory$libresoc.v:133299$5406_ADDR[2:0]$5414 \issue__addr$1 - assign $0$memwr$\memory$libresoc.v:133299$5406_DATA[63:0]$5415 \issue__data_i - assign $0$memwr$\memory$libresoc.v:133299$5406_EN[63:0]$5416 64'1111111111111111111111111111111111111111111111111111111111111111 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\memory$libresoc.v:134309$5406_ADDR[2:0]$5415 \memory_w_addr + assign $1$memwr$\memory$libresoc.v:134309$5406_DATA[63:0]$5416 \memory_w_data + assign $1$memwr$\memory$libresoc.v:134309$5406_EN[63:0]$5417 64'1111111111111111111111111111111111111111111111111111111111111111 case + assign $1$memwr$\memory$libresoc.v:134309$5406_ADDR[2:0]$5415 3'xxx + assign $1$memwr$\memory$libresoc.v:134309$5406_DATA[63:0]$5416 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\memory$libresoc.v:134309$5406_EN[63:0]$5417 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:133300.5-133300.58" - switch \dest1__wen - attribute \src "libresoc.v:133300.9-133300.19" + attribute \src "libresoc.v:134310.5-134310.73" + switch \memory_w_en$7 + attribute \src "libresoc.v:134310.9-134310.23" case 1'1 - assign $0$memwr$\memory$libresoc.v:133300$5407_ADDR[2:0]$5417 \dest1__addr - assign $0$memwr$\memory$libresoc.v:133300$5407_DATA[63:0]$5418 \dest1__data_i - assign $0$memwr$\memory$libresoc.v:133300$5407_EN[63:0]$5419 64'1111111111111111111111111111111111111111111111111111111111111111 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\memory$libresoc.v:134310$5407_ADDR[2:0]$5418 \memory_w_addr$8 + assign $1$memwr$\memory$libresoc.v:134310$5407_DATA[63:0]$5419 \memory_w_data$9 + assign $1$memwr$\memory$libresoc.v:134310$5407_EN[63:0]$5420 64'1111111111111111111111111111111111111111111111111111111111111111 case + assign $1$memwr$\memory$libresoc.v:134310$5407_ADDR[2:0]$5418 3'xxx + assign $1$memwr$\memory$libresoc.v:134310$5407_DATA[63:0]$5419 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\memory$libresoc.v:134310$5407_EN[63:0]$5420 64'0000000000000000000000000000000000000000000000000000000000000000 end sync posedge \coresync_clk update \_0_ $0\_0_[2:0] update \_1_ $0\_1_[2:0] update \_2_ $0\_2_[2:0] - update $memwr$\memory$libresoc.v:133299$5406_ADDR $0$memwr$\memory$libresoc.v:133299$5406_ADDR[2:0]$5414 - update $memwr$\memory$libresoc.v:133299$5406_DATA $0$memwr$\memory$libresoc.v:133299$5406_DATA[63:0]$5415 - update $memwr$\memory$libresoc.v:133299$5406_EN $0$memwr$\memory$libresoc.v:133299$5406_EN[63:0]$5416 - update $memwr$\memory$libresoc.v:133300$5407_ADDR $0$memwr$\memory$libresoc.v:133300$5407_ADDR[2:0]$5417 - update $memwr$\memory$libresoc.v:133300$5407_DATA $0$memwr$\memory$libresoc.v:133300$5407_DATA[63:0]$5418 - update $memwr$\memory$libresoc.v:133300$5407_EN $0$memwr$\memory$libresoc.v:133300$5407_EN[63:0]$5419 + update $memwr$\memory$libresoc.v:134309$5406_ADDR $0$memwr$\memory$libresoc.v:134309$5406_ADDR[2:0]$5409 + update $memwr$\memory$libresoc.v:134309$5406_DATA $0$memwr$\memory$libresoc.v:134309$5406_DATA[63:0]$5410 + update $memwr$\memory$libresoc.v:134309$5406_EN $0$memwr$\memory$libresoc.v:134309$5406_EN[63:0]$5411 + update $memwr$\memory$libresoc.v:134310$5407_ADDR $0$memwr$\memory$libresoc.v:134310$5407_ADDR[2:0]$5412 + update $memwr$\memory$libresoc.v:134310$5407_DATA $0$memwr$\memory$libresoc.v:134310$5407_DATA[63:0]$5413 + update $memwr$\memory$libresoc.v:134310$5407_EN $0$memwr$\memory$libresoc.v:134310$5407_EN[63:0]$5414 + attribute \src "libresoc.v:134309.22-134309.60" + memwr \memory $1$memwr$\memory$libresoc.v:134309$5406_ADDR[2:0]$5415 $1$memwr$\memory$libresoc.v:134309$5406_DATA[63:0]$5416 $1$memwr$\memory$libresoc.v:134309$5406_EN[63:0]$5417 0' + attribute \src "libresoc.v:134310.26-134310.71" + memwr \memory $1$memwr$\memory$libresoc.v:134310$5407_ADDR[2:0]$5418 $1$memwr$\memory$libresoc.v:134310$5407_DATA[63:0]$5419 $1$memwr$\memory$libresoc.v:134310$5407_EN[63:0]$5420 1'1 + end + attribute \src "libresoc.v:134315.3-134316.43" + process $proc$libresoc.v:134315$5424 + assign { } { } + assign $0\ren_delay$11[0:0]$5425 \ren_delay$11$next + sync posedge \coresync_clk + update \ren_delay$11 $0\ren_delay$11[0:0]$5425 + end + attribute \src "libresoc.v:134317.3-134318.43" + process $proc$libresoc.v:134317$5426 + assign { } { } + assign $0\ren_delay$10[0:0]$5427 \ren_delay$10$next + sync posedge \coresync_clk + update \ren_delay$10 $0\ren_delay$10[0:0]$5427 + end + attribute \src "libresoc.v:134319.3-134320.35" + process $proc$libresoc.v:134319$5428 + assign { } { } + assign $0\ren_delay[0:0] \ren_delay$next + sync posedge \coresync_clk + update \ren_delay $0\ren_delay[0:0] end - attribute \src "libresoc.v:133305.3-133313.6" - process $proc$libresoc.v:133305$5423 + attribute \src "libresoc.v:134321.3-134329.6" + process $proc$libresoc.v:134321$5429 assign { } { } assign { } { } - assign $0\ren_delay$next[0:0]$5424 $1\ren_delay$next[0:0]$5425 - attribute \src "libresoc.v:133306.5-133306.29" + assign $0\ren_delay$next[0:0]$5430 $1\ren_delay$next[0:0]$5431 + attribute \src "libresoc.v:134322.5-134322.29" switch \initial - attribute \src "libresoc.v:133306.9-133306.17" + attribute \src "libresoc.v:134322.9-134322.17" case 1'1 case end @@ -211394,21 +212176,21 @@ module \fast attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[0:0]$5425 1'0 + assign $1\ren_delay$next[0:0]$5431 1'0 case - assign $1\ren_delay$next[0:0]$5425 \src1__ren + assign $1\ren_delay$next[0:0]$5431 \src1__ren end sync always - update \ren_delay$next $0\ren_delay$next[0:0]$5424 + update \ren_delay$next $0\ren_delay$next[0:0]$5430 end - attribute \src "libresoc.v:133314.3-133323.6" - process $proc$libresoc.v:133314$5426 + attribute \src "libresoc.v:134330.3-134339.6" + process $proc$libresoc.v:134330$5432 assign { } { } assign { } { } assign $0\src1__data_o[63:0] $1\src1__data_o[63:0] - attribute \src "libresoc.v:133315.5-133315.29" + attribute \src "libresoc.v:134331.5-134331.29" switch \initial - attribute \src "libresoc.v:133315.9-133315.17" + attribute \src "libresoc.v:134331.9-134331.17" case 1'1 case end @@ -211424,14 +212206,14 @@ module \fast sync always update \src1__data_o $0\src1__data_o[63:0] end - attribute \src "libresoc.v:133324.3-133332.6" - process $proc$libresoc.v:133324$5427 + attribute \src "libresoc.v:134340.3-134348.6" + process $proc$libresoc.v:134340$5433 assign { } { } assign { } { } - assign $0\ren_delay$10$next[0:0]$5428 $1\ren_delay$10$next[0:0]$5429 - attribute \src "libresoc.v:133325.5-133325.29" + assign $0\ren_delay$10$next[0:0]$5434 $1\ren_delay$10$next[0:0]$5435 + attribute \src "libresoc.v:134341.5-134341.29" switch \initial - attribute \src "libresoc.v:133325.9-133325.17" + attribute \src "libresoc.v:134341.9-134341.17" case 1'1 case end @@ -211440,21 +212222,21 @@ module \fast attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$10$next[0:0]$5429 1'0 + assign $1\ren_delay$10$next[0:0]$5435 1'0 case - assign $1\ren_delay$10$next[0:0]$5429 \src2__ren + assign $1\ren_delay$10$next[0:0]$5435 \src2__ren end sync always - update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5428 + update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5434 end - attribute \src "libresoc.v:133333.3-133342.6" - process $proc$libresoc.v:133333$5430 + attribute \src "libresoc.v:134349.3-134358.6" + process $proc$libresoc.v:134349$5436 assign { } { } assign { } { } assign $0\src2__data_o[63:0] $1\src2__data_o[63:0] - attribute \src "libresoc.v:133334.5-133334.29" + attribute \src "libresoc.v:134350.5-134350.29" switch \initial - attribute \src "libresoc.v:133334.9-133334.17" + attribute \src "libresoc.v:134350.9-134350.17" case 1'1 case end @@ -211470,14 +212252,14 @@ module \fast sync always update \src2__data_o $0\src2__data_o[63:0] end - attribute \src "libresoc.v:133343.3-133351.6" - process $proc$libresoc.v:133343$5431 + attribute \src "libresoc.v:134359.3-134367.6" + process $proc$libresoc.v:134359$5437 assign { } { } assign { } { } - assign $0\ren_delay$11$next[0:0]$5432 $1\ren_delay$11$next[0:0]$5433 - attribute \src "libresoc.v:133344.5-133344.29" + assign $0\ren_delay$11$next[0:0]$5438 $1\ren_delay$11$next[0:0]$5439 + attribute \src "libresoc.v:134360.5-134360.29" switch \initial - attribute \src "libresoc.v:133344.9-133344.17" + attribute \src "libresoc.v:134360.9-134360.17" case 1'1 case end @@ -211486,21 +212268,21 @@ module \fast attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$11$next[0:0]$5433 1'0 + assign $1\ren_delay$11$next[0:0]$5439 1'0 case - assign $1\ren_delay$11$next[0:0]$5433 \issue__ren + assign $1\ren_delay$11$next[0:0]$5439 \issue__ren end sync always - update \ren_delay$11$next $0\ren_delay$11$next[0:0]$5432 + update \ren_delay$11$next $0\ren_delay$11$next[0:0]$5438 end - attribute \src "libresoc.v:133352.3-133361.6" - process $proc$libresoc.v:133352$5434 + attribute \src "libresoc.v:134368.3-134377.6" + process $proc$libresoc.v:134368$5440 assign { } { } assign { } { } assign $0\issue__data_o[63:0] $1\issue__data_o[63:0] - attribute \src "libresoc.v:133353.5-133353.29" + attribute \src "libresoc.v:134369.5-134369.29" switch \initial - attribute \src "libresoc.v:133353.9-133353.17" + attribute \src "libresoc.v:134369.9-134369.17" case 1'1 case end @@ -211516,9 +212298,9 @@ module \fast sync always update \issue__data_o $0\issue__data_o[63:0] end - connect \memory_r_data $memrd$\memory$libresoc.v:133302$5420_DATA - connect \memory_r_data$4 $memrd$\memory$libresoc.v:133303$5421_DATA - connect \memory_r_data$6 $memrd$\memory$libresoc.v:133304$5422_DATA + connect \memory_r_data $memrd$\memory$libresoc.v:134312$5421_DATA + connect \memory_r_data$4 $memrd$\memory$libresoc.v:134313$5422_DATA + connect \memory_r_data$6 $memrd$\memory$libresoc.v:134314$5423_DATA connect \memory_w_data$9 \issue__data_i connect \memory_w_en$7 \issue__wen connect \memory_w_addr$8 \issue__addr$1 @@ -211529,14 +212311,14 @@ module \fast connect \memory_r_addr$3 \src2__addr connect \memory_r_addr \src1__addr end -attribute \src "libresoc.v:133375.1-135325.10" +attribute \src "libresoc.v:134391.1-136341.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus" attribute \generator "nMigen" module \fus - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 330 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 257 \cr_a_ok @@ -213116,7 +213898,7 @@ module \fus attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 286 \xer_so_ok$131 attribute \module_not_derived 1 - attribute \src "libresoc.v:134957.8-134999.4" + attribute \src "libresoc.v:135973.8-136015.4" cell \alu0 \alu0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -213161,7 +213943,7 @@ module \fus connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:135000.11-135027.4" + attribute \src "libresoc.v:136016.11-136043.4" cell \branch0 \branch0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -213191,7 +213973,7 @@ module \fus connect \src3_i \src3_i$71 end attribute \module_not_derived 1 - attribute \src "libresoc.v:135028.7-135053.4" + attribute \src "libresoc.v:136044.7-136069.4" cell \cr0 \cr0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -213219,7 +214001,7 @@ module \fus connect \src6_i \src6_i$73 end attribute \module_not_derived 1 - attribute \src "libresoc.v:135054.8-135093.4" + attribute \src "libresoc.v:136070.8-136109.4" cell \div0 \div0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -213261,7 +214043,7 @@ module \fus connect \xer_so_ok \xer_so_ok$130 end attribute \module_not_derived 1 - attribute \src "libresoc.v:135094.9-135148.4" + attribute \src "libresoc.v:136110.9-136164.4" cell \ldst0 \ldst0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -213318,7 +214100,7 @@ module \fus connect \src3_i \src3_i$59 end attribute \module_not_derived 1 - attribute \src "libresoc.v:135149.12-135184.4" + attribute \src "libresoc.v:136165.12-136200.4" cell \logical0 \logical0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -213356,7 +214138,7 @@ module \fus connect \src3_i \src3_i$61 end attribute \module_not_derived 1 - attribute \src "libresoc.v:135185.8-135218.4" + attribute \src "libresoc.v:136201.8-136234.4" cell \mul0 \mul0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -213392,7 +214174,7 @@ module \fus connect \xer_so_ok \xer_so_ok$131 end attribute \module_not_derived 1 - attribute \src "libresoc.v:135219.13-135257.4" + attribute \src "libresoc.v:136235.13-136273.4" cell \shiftrot0 \shiftrot0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -213433,7 +214215,7 @@ module \fus connect \xer_ca_ok \xer_ca_ok$121 end attribute \module_not_derived 1 - attribute \src "libresoc.v:135258.8-135290.4" + attribute \src "libresoc.v:136274.8-136306.4" cell \spr0 \spr0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -213468,7 +214250,7 @@ module \fus connect \xer_so_ok \xer_so_ok$129 end attribute \module_not_derived 1 - attribute \src "libresoc.v:135291.9-135324.4" + attribute \src "libresoc.v:136307.9-136340.4" cell \trap0 \trap0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -213504,37 +214286,37 @@ module \fus connect \src4_i \src4_i$78 end end -attribute \src "libresoc.v:135329.1-135387.10" +attribute \src "libresoc.v:136345.1-136403.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.idx_l" attribute \generator "nMigen" module \idx_l - attribute \src "libresoc.v:135330.7-135330.20" + attribute \src "libresoc.v:136346.7-136346.20" wire $0\initial[0:0] - attribute \src "libresoc.v:135375.3-135383.6" - wire $0\q_int$next[0:0]$5462 - attribute \src "libresoc.v:135373.3-135374.27" + attribute \src "libresoc.v:136391.3-136399.6" + wire $0\q_int$next[0:0]$5466 + attribute \src "libresoc.v:136389.3-136390.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:135375.3-135383.6" - wire $1\q_int$next[0:0]$5463 - attribute \src "libresoc.v:135354.7-135354.19" + attribute \src "libresoc.v:136391.3-136399.6" + wire $1\q_int$next[0:0]$5467 + attribute \src "libresoc.v:136370.7-136370.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:135365.17-135365.96" - wire $and$libresoc.v:135365$5452_Y - attribute \src "libresoc.v:135370.17-135370.96" - wire $and$libresoc.v:135370$5457_Y - attribute \src "libresoc.v:135367.18-135367.95" - wire $not$libresoc.v:135367$5454_Y - attribute \src "libresoc.v:135369.17-135369.94" - wire $not$libresoc.v:135369$5456_Y - attribute \src "libresoc.v:135372.17-135372.94" - wire $not$libresoc.v:135372$5459_Y - attribute \src "libresoc.v:135366.18-135366.100" - wire $or$libresoc.v:135366$5453_Y - attribute \src "libresoc.v:135368.18-135368.101" - wire $or$libresoc.v:135368$5455_Y - attribute \src "libresoc.v:135371.17-135371.99" - wire $or$libresoc.v:135371$5458_Y + attribute \src "libresoc.v:136381.17-136381.96" + wire $and$libresoc.v:136381$5456_Y + attribute \src "libresoc.v:136386.17-136386.96" + wire $and$libresoc.v:136386$5461_Y + attribute \src "libresoc.v:136383.18-136383.95" + wire $not$libresoc.v:136383$5458_Y + attribute \src "libresoc.v:136385.17-136385.94" + wire $not$libresoc.v:136385$5460_Y + attribute \src "libresoc.v:136388.17-136388.94" + wire $not$libresoc.v:136388$5463_Y + attribute \src "libresoc.v:136382.18-136382.100" + wire $or$libresoc.v:136382$5457_Y + attribute \src "libresoc.v:136384.18-136384.101" + wire $or$libresoc.v:136384$5459_Y + attribute \src "libresoc.v:136387.17-136387.99" + wire $or$libresoc.v:136387$5462_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -213551,11 +214333,11 @@ module \idx_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:135330.7-135330.15" + attribute \src "libresoc.v:136346.7-136346.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire output 2 \q_idx_l @@ -213572,7 +214354,7 @@ module \idx_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_idx_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:135365$5452 + cell $and $and$libresoc.v:136381$5456 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -213580,10 +214362,10 @@ module \idx_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:135365$5452_Y + connect \Y $and$libresoc.v:136381$5456_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:135370$5457 + cell $and $and$libresoc.v:136386$5461 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -213591,34 +214373,34 @@ module \idx_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:135370$5457_Y + connect \Y $and$libresoc.v:136386$5461_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:135367$5454 + cell $not $not$libresoc.v:136383$5458 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_idx_l - connect \Y $not$libresoc.v:135367$5454_Y + connect \Y $not$libresoc.v:136383$5458_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:135369$5456 + cell $not $not$libresoc.v:136385$5460 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_idx_l - connect \Y $not$libresoc.v:135369$5456_Y + connect \Y $not$libresoc.v:136385$5460_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:135372$5459 + cell $not $not$libresoc.v:136388$5463 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_idx_l - connect \Y $not$libresoc.v:135372$5459_Y + connect \Y $not$libresoc.v:136388$5463_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:135366$5453 + cell $or $or$libresoc.v:136382$5457 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -213626,10 +214408,10 @@ module \idx_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_idx_l - connect \Y $or$libresoc.v:135366$5453_Y + connect \Y $or$libresoc.v:136382$5457_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:135368$5455 + cell $or $or$libresoc.v:136384$5459 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -213637,10 +214419,10 @@ module \idx_l parameter \Y_WIDTH 1 connect \A \q_idx_l connect \B \q_int - connect \Y $or$libresoc.v:135368$5455_Y + connect \Y $or$libresoc.v:136384$5459_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:135371$5458 + cell $or $or$libresoc.v:136387$5462 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -213648,39 +214430,39 @@ module \idx_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_idx_l - connect \Y $or$libresoc.v:135371$5458_Y + connect \Y $or$libresoc.v:136387$5462_Y end - attribute \src "libresoc.v:135330.7-135330.20" - process $proc$libresoc.v:135330$5464 + attribute \src "libresoc.v:136346.7-136346.20" + process $proc$libresoc.v:136346$5468 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:135354.7-135354.19" - process $proc$libresoc.v:135354$5465 + attribute \src "libresoc.v:136370.7-136370.19" + process $proc$libresoc.v:136370$5469 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:135373.3-135374.27" - process $proc$libresoc.v:135373$5460 + attribute \src "libresoc.v:136389.3-136390.27" + process $proc$libresoc.v:136389$5464 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:135375.3-135383.6" - process $proc$libresoc.v:135375$5461 + attribute \src "libresoc.v:136391.3-136399.6" + process $proc$libresoc.v:136391$5465 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$5462 $1\q_int$next[0:0]$5463 - attribute \src "libresoc.v:135376.5-135376.29" + assign $0\q_int$next[0:0]$5466 $1\q_int$next[0:0]$5467 + attribute \src "libresoc.v:136392.5-136392.29" switch \initial - attribute \src "libresoc.v:135376.9-135376.17" + attribute \src "libresoc.v:136392.9-136392.17" case 1'1 case end @@ -213689,192 +214471,192 @@ module \idx_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$5463 1'0 + assign $1\q_int$next[0:0]$5467 1'0 case - assign $1\q_int$next[0:0]$5463 \$5 + assign $1\q_int$next[0:0]$5467 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$5462 + update \q_int$next $0\q_int$next[0:0]$5466 end - connect \$9 $and$libresoc.v:135365$5452_Y - connect \$11 $or$libresoc.v:135366$5453_Y - connect \$13 $not$libresoc.v:135367$5454_Y - connect \$15 $or$libresoc.v:135368$5455_Y - connect \$1 $not$libresoc.v:135369$5456_Y - connect \$3 $and$libresoc.v:135370$5457_Y - connect \$5 $or$libresoc.v:135371$5458_Y - connect \$7 $not$libresoc.v:135372$5459_Y + connect \$9 $and$libresoc.v:136381$5456_Y + connect \$11 $or$libresoc.v:136382$5457_Y + connect \$13 $not$libresoc.v:136383$5458_Y + connect \$15 $or$libresoc.v:136384$5459_Y + connect \$1 $not$libresoc.v:136385$5460_Y + connect \$3 $and$libresoc.v:136386$5461_Y + connect \$5 $or$libresoc.v:136387$5462_Y + connect \$7 $not$libresoc.v:136388$5463_Y connect \qlq_idx_l \$15 connect \qn_idx_l \$13 connect \q_idx_l \$11 end -attribute \src "libresoc.v:135391.1-135770.10" +attribute \src "libresoc.v:136407.1-136786.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.imem" attribute \generator "nMigen" module \imem - attribute \src "libresoc.v:135722.3-135731.6" + attribute \src "libresoc.v:136738.3-136747.6" wire $0\a_busy_o[0:0] - attribute \src "libresoc.v:135702.3-135721.6" - wire width 45 $0\f_badaddr_o$next[44:0]$5534 - attribute \src "libresoc.v:135533.3-135534.39" + attribute \src "libresoc.v:136718.3-136737.6" + wire width 45 $0\f_badaddr_o$next[44:0]$5538 + attribute \src "libresoc.v:136549.3-136550.39" wire width 45 $0\f_badaddr_o[44:0] - attribute \src "libresoc.v:135732.3-135749.6" + attribute \src "libresoc.v:136748.3-136765.6" wire $0\f_busy_o[0:0] - attribute \src "libresoc.v:135679.3-135701.6" - wire $0\f_fetch_err_o$next[0:0]$5529 - attribute \src "libresoc.v:135535.3-135536.43" + attribute \src "libresoc.v:136695.3-136717.6" + wire $0\f_fetch_err_o$next[0:0]$5533 + attribute \src "libresoc.v:136551.3-136552.43" wire $0\f_fetch_err_o[0:0] - attribute \src "libresoc.v:135750.3-135767.6" + attribute \src "libresoc.v:136766.3-136783.6" wire width 64 $0\f_instr_o[63:0] - attribute \src "libresoc.v:135656.3-135678.6" - wire width 45 $0\ibus__adr$next[44:0]$5524 - attribute \src "libresoc.v:135537.3-135538.35" + attribute \src "libresoc.v:136672.3-136694.6" + wire width 45 $0\ibus__adr$next[44:0]$5528 + attribute \src "libresoc.v:136553.3-136554.35" wire width 45 $0\ibus__adr[44:0] - attribute \src "libresoc.v:135547.3-135574.6" - wire $0\ibus__cyc$next[0:0]$5500 - attribute \src "libresoc.v:135545.3-135546.35" + attribute \src "libresoc.v:136563.3-136590.6" + wire $0\ibus__cyc$next[0:0]$5504 + attribute \src "libresoc.v:136561.3-136562.35" wire $0\ibus__cyc[0:0] - attribute \src "libresoc.v:135603.3-135630.6" - wire width 8 $0\ibus__sel$next[7:0]$5512 - attribute \src "libresoc.v:135541.3-135542.35" + attribute \src "libresoc.v:136619.3-136646.6" + wire width 8 $0\ibus__sel$next[7:0]$5516 + attribute \src "libresoc.v:136557.3-136558.35" wire width 8 $0\ibus__sel[7:0] - attribute \src "libresoc.v:135575.3-135602.6" - wire $0\ibus__stb$next[0:0]$5506 - attribute \src "libresoc.v:135543.3-135544.35" + attribute \src "libresoc.v:136591.3-136618.6" + wire $0\ibus__stb$next[0:0]$5510 + attribute \src "libresoc.v:136559.3-136560.35" wire $0\ibus__stb[0:0] - attribute \src "libresoc.v:135631.3-135655.6" - wire width 64 $0\ibus_rdata$next[63:0]$5518 - attribute \src "libresoc.v:135539.3-135540.37" + attribute \src "libresoc.v:136647.3-136671.6" + wire width 64 $0\ibus_rdata$next[63:0]$5522 + attribute \src "libresoc.v:136555.3-136556.37" wire width 64 $0\ibus_rdata[63:0] - attribute \src "libresoc.v:135392.7-135392.20" + attribute \src "libresoc.v:136408.7-136408.20" wire $0\initial[0:0] - attribute \src "libresoc.v:135722.3-135731.6" + attribute \src "libresoc.v:136738.3-136747.6" wire $1\a_busy_o[0:0] - attribute \src "libresoc.v:135702.3-135721.6" - wire width 45 $1\f_badaddr_o$next[44:0]$5535 - attribute \src "libresoc.v:135456.14-135456.44" + attribute \src "libresoc.v:136718.3-136737.6" + wire width 45 $1\f_badaddr_o$next[44:0]$5539 + attribute \src "libresoc.v:136472.14-136472.44" wire width 45 $1\f_badaddr_o[44:0] - attribute \src "libresoc.v:135732.3-135749.6" + attribute \src "libresoc.v:136748.3-136765.6" wire $1\f_busy_o[0:0] - attribute \src "libresoc.v:135679.3-135701.6" - wire $1\f_fetch_err_o$next[0:0]$5530 - attribute \src "libresoc.v:135463.7-135463.27" + attribute \src "libresoc.v:136695.3-136717.6" + wire $1\f_fetch_err_o$next[0:0]$5534 + attribute \src "libresoc.v:136479.7-136479.27" wire $1\f_fetch_err_o[0:0] - attribute \src "libresoc.v:135750.3-135767.6" + attribute \src "libresoc.v:136766.3-136783.6" wire width 64 $1\f_instr_o[63:0] - attribute \src "libresoc.v:135656.3-135678.6" - wire width 45 $1\ibus__adr$next[44:0]$5525 - attribute \src "libresoc.v:135477.14-135477.42" + attribute \src "libresoc.v:136672.3-136694.6" + wire width 45 $1\ibus__adr$next[44:0]$5529 + attribute \src "libresoc.v:136493.14-136493.42" wire width 45 $1\ibus__adr[44:0] - attribute \src "libresoc.v:135547.3-135574.6" - wire $1\ibus__cyc$next[0:0]$5501 - attribute \src "libresoc.v:135482.7-135482.23" + attribute \src "libresoc.v:136563.3-136590.6" + wire $1\ibus__cyc$next[0:0]$5505 + attribute \src "libresoc.v:136498.7-136498.23" wire $1\ibus__cyc[0:0] - attribute \src "libresoc.v:135603.3-135630.6" - wire width 8 $1\ibus__sel$next[7:0]$5513 - attribute \src "libresoc.v:135491.13-135491.30" + attribute \src "libresoc.v:136619.3-136646.6" + wire width 8 $1\ibus__sel$next[7:0]$5517 + attribute \src "libresoc.v:136507.13-136507.30" wire width 8 $1\ibus__sel[7:0] - attribute \src "libresoc.v:135575.3-135602.6" - wire $1\ibus__stb$next[0:0]$5507 - attribute \src "libresoc.v:135496.7-135496.23" + attribute \src "libresoc.v:136591.3-136618.6" + wire $1\ibus__stb$next[0:0]$5511 + attribute \src "libresoc.v:136512.7-136512.23" wire $1\ibus__stb[0:0] - attribute \src "libresoc.v:135631.3-135655.6" - wire width 64 $1\ibus_rdata$next[63:0]$5519 - attribute \src "libresoc.v:135500.14-135500.47" + attribute \src "libresoc.v:136647.3-136671.6" + wire width 64 $1\ibus_rdata$next[63:0]$5523 + attribute \src "libresoc.v:136516.14-136516.47" wire width 64 $1\ibus_rdata[63:0] - attribute \src "libresoc.v:135702.3-135721.6" - wire width 45 $2\f_badaddr_o$next[44:0]$5536 - attribute \src "libresoc.v:135732.3-135749.6" + attribute \src "libresoc.v:136718.3-136737.6" + wire width 45 $2\f_badaddr_o$next[44:0]$5540 + attribute \src "libresoc.v:136748.3-136765.6" wire $2\f_busy_o[0:0] - attribute \src "libresoc.v:135679.3-135701.6" - wire $2\f_fetch_err_o$next[0:0]$5531 - attribute \src "libresoc.v:135750.3-135767.6" + attribute \src "libresoc.v:136695.3-136717.6" + wire $2\f_fetch_err_o$next[0:0]$5535 + attribute \src "libresoc.v:136766.3-136783.6" wire width 64 $2\f_instr_o[63:0] - attribute \src "libresoc.v:135656.3-135678.6" - wire width 45 $2\ibus__adr$next[44:0]$5526 - attribute \src "libresoc.v:135547.3-135574.6" - wire $2\ibus__cyc$next[0:0]$5502 - attribute \src "libresoc.v:135603.3-135630.6" - wire width 8 $2\ibus__sel$next[7:0]$5514 - attribute \src "libresoc.v:135575.3-135602.6" - wire $2\ibus__stb$next[0:0]$5508 - attribute \src "libresoc.v:135631.3-135655.6" - wire width 64 $2\ibus_rdata$next[63:0]$5520 - attribute \src "libresoc.v:135702.3-135721.6" - wire width 45 $3\f_badaddr_o$next[44:0]$5537 - attribute \src "libresoc.v:135679.3-135701.6" - wire $3\f_fetch_err_o$next[0:0]$5532 - attribute \src "libresoc.v:135656.3-135678.6" - wire width 45 $3\ibus__adr$next[44:0]$5527 - attribute \src "libresoc.v:135547.3-135574.6" - wire $3\ibus__cyc$next[0:0]$5503 - attribute \src "libresoc.v:135603.3-135630.6" - wire width 8 $3\ibus__sel$next[7:0]$5515 - attribute \src "libresoc.v:135575.3-135602.6" - wire $3\ibus__stb$next[0:0]$5509 - attribute \src "libresoc.v:135631.3-135655.6" - wire width 64 $3\ibus_rdata$next[63:0]$5521 - attribute \src "libresoc.v:135547.3-135574.6" - wire $4\ibus__cyc$next[0:0]$5504 - attribute \src "libresoc.v:135603.3-135630.6" - wire width 8 $4\ibus__sel$next[7:0]$5516 - attribute \src "libresoc.v:135575.3-135602.6" - wire $4\ibus__stb$next[0:0]$5510 - attribute \src "libresoc.v:135631.3-135655.6" - wire width 64 $4\ibus_rdata$next[63:0]$5522 - attribute \src "libresoc.v:135509.18-135509.110" - wire $and$libresoc.v:135509$5468_Y - attribute \src "libresoc.v:135515.18-135515.110" - wire $and$libresoc.v:135515$5474_Y - attribute \src "libresoc.v:135520.18-135520.110" - wire $and$libresoc.v:135520$5479_Y - attribute \src "libresoc.v:135523.17-135523.108" - wire $and$libresoc.v:135523$5482_Y - attribute \src "libresoc.v:135526.18-135526.110" - wire $and$libresoc.v:135526$5485_Y - attribute \src "libresoc.v:135527.18-135527.115" - wire $and$libresoc.v:135527$5486_Y - attribute \src "libresoc.v:135529.18-135529.115" - wire $and$libresoc.v:135529$5488_Y - attribute \src "libresoc.v:135508.18-135508.105" - wire $not$libresoc.v:135508$5467_Y - attribute \src "libresoc.v:135511.18-135511.105" - wire $not$libresoc.v:135511$5470_Y - attribute \src "libresoc.v:135512.17-135512.104" - wire $not$libresoc.v:135512$5471_Y - attribute \src "libresoc.v:135514.18-135514.105" - wire $not$libresoc.v:135514$5473_Y - attribute \src "libresoc.v:135517.18-135517.105" - wire $not$libresoc.v:135517$5476_Y - attribute \src "libresoc.v:135519.18-135519.105" - wire $not$libresoc.v:135519$5478_Y - attribute \src "libresoc.v:135522.18-135522.105" - wire $not$libresoc.v:135522$5481_Y - attribute \src "libresoc.v:135525.18-135525.105" - wire $not$libresoc.v:135525$5484_Y - attribute \src "libresoc.v:135528.18-135528.105" - wire $not$libresoc.v:135528$5487_Y - attribute \src "libresoc.v:135530.18-135530.105" - wire $not$libresoc.v:135530$5489_Y - attribute \src "libresoc.v:135532.17-135532.104" - wire $not$libresoc.v:135532$5491_Y - attribute \src "libresoc.v:135507.17-135507.103" - wire $or$libresoc.v:135507$5466_Y - attribute \src "libresoc.v:135510.18-135510.115" - wire $or$libresoc.v:135510$5469_Y - attribute \src "libresoc.v:135513.18-135513.106" - wire $or$libresoc.v:135513$5472_Y - attribute \src "libresoc.v:135516.18-135516.115" - wire $or$libresoc.v:135516$5475_Y - attribute \src "libresoc.v:135518.18-135518.106" - wire $or$libresoc.v:135518$5477_Y - attribute \src "libresoc.v:135521.18-135521.115" - wire $or$libresoc.v:135521$5480_Y - attribute \src "libresoc.v:135524.18-135524.106" - wire $or$libresoc.v:135524$5483_Y - attribute \src "libresoc.v:135531.17-135531.114" - wire $or$libresoc.v:135531$5490_Y + attribute \src "libresoc.v:136672.3-136694.6" + wire width 45 $2\ibus__adr$next[44:0]$5530 + attribute \src "libresoc.v:136563.3-136590.6" + wire $2\ibus__cyc$next[0:0]$5506 + attribute \src "libresoc.v:136619.3-136646.6" + wire width 8 $2\ibus__sel$next[7:0]$5518 + attribute \src "libresoc.v:136591.3-136618.6" + wire $2\ibus__stb$next[0:0]$5512 + attribute \src "libresoc.v:136647.3-136671.6" + wire width 64 $2\ibus_rdata$next[63:0]$5524 + attribute \src "libresoc.v:136718.3-136737.6" + wire width 45 $3\f_badaddr_o$next[44:0]$5541 + attribute \src "libresoc.v:136695.3-136717.6" + wire $3\f_fetch_err_o$next[0:0]$5536 + attribute \src "libresoc.v:136672.3-136694.6" + wire width 45 $3\ibus__adr$next[44:0]$5531 + attribute \src "libresoc.v:136563.3-136590.6" + wire $3\ibus__cyc$next[0:0]$5507 + attribute \src "libresoc.v:136619.3-136646.6" + wire width 8 $3\ibus__sel$next[7:0]$5519 + attribute \src "libresoc.v:136591.3-136618.6" + wire $3\ibus__stb$next[0:0]$5513 + attribute \src "libresoc.v:136647.3-136671.6" + wire width 64 $3\ibus_rdata$next[63:0]$5525 + attribute \src "libresoc.v:136563.3-136590.6" + wire $4\ibus__cyc$next[0:0]$5508 + attribute \src "libresoc.v:136619.3-136646.6" + wire width 8 $4\ibus__sel$next[7:0]$5520 + attribute \src "libresoc.v:136591.3-136618.6" + wire $4\ibus__stb$next[0:0]$5514 + attribute \src "libresoc.v:136647.3-136671.6" + wire width 64 $4\ibus_rdata$next[63:0]$5526 + attribute \src "libresoc.v:136525.18-136525.110" + wire $and$libresoc.v:136525$5472_Y + attribute \src "libresoc.v:136531.18-136531.110" + wire $and$libresoc.v:136531$5478_Y + attribute \src "libresoc.v:136536.18-136536.110" + wire $and$libresoc.v:136536$5483_Y + attribute \src "libresoc.v:136539.17-136539.108" + wire $and$libresoc.v:136539$5486_Y + attribute \src "libresoc.v:136542.18-136542.110" + wire $and$libresoc.v:136542$5489_Y + attribute \src "libresoc.v:136543.18-136543.115" + wire $and$libresoc.v:136543$5490_Y + attribute \src "libresoc.v:136545.18-136545.115" + wire $and$libresoc.v:136545$5492_Y + attribute \src "libresoc.v:136524.18-136524.105" + wire $not$libresoc.v:136524$5471_Y + attribute \src "libresoc.v:136527.18-136527.105" + wire $not$libresoc.v:136527$5474_Y + attribute \src "libresoc.v:136528.17-136528.104" + wire $not$libresoc.v:136528$5475_Y + attribute \src "libresoc.v:136530.18-136530.105" + wire $not$libresoc.v:136530$5477_Y + attribute \src "libresoc.v:136533.18-136533.105" + wire $not$libresoc.v:136533$5480_Y + attribute \src "libresoc.v:136535.18-136535.105" + wire $not$libresoc.v:136535$5482_Y + attribute \src "libresoc.v:136538.18-136538.105" + wire $not$libresoc.v:136538$5485_Y + attribute \src "libresoc.v:136541.18-136541.105" + wire $not$libresoc.v:136541$5488_Y + attribute \src "libresoc.v:136544.18-136544.105" + wire $not$libresoc.v:136544$5491_Y + attribute \src "libresoc.v:136546.18-136546.105" + wire $not$libresoc.v:136546$5493_Y + attribute \src "libresoc.v:136548.17-136548.104" + wire $not$libresoc.v:136548$5495_Y + attribute \src "libresoc.v:136523.17-136523.103" + wire $or$libresoc.v:136523$5470_Y + attribute \src "libresoc.v:136526.18-136526.115" + wire $or$libresoc.v:136526$5473_Y + attribute \src "libresoc.v:136529.18-136529.106" + wire $or$libresoc.v:136529$5476_Y + attribute \src "libresoc.v:136532.18-136532.115" + wire $or$libresoc.v:136532$5479_Y + attribute \src "libresoc.v:136534.18-136534.106" + wire $or$libresoc.v:136534$5481_Y + attribute \src "libresoc.v:136537.18-136537.115" + wire $or$libresoc.v:136537$5484_Y + attribute \src "libresoc.v:136540.18-136540.106" + wire $or$libresoc.v:136540$5487_Y + attribute \src "libresoc.v:136547.17-136547.114" + wire $or$libresoc.v:136547$5494_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" @@ -213935,7 +214717,7 @@ module \imem wire \a_stall_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" wire input 3 \a_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 15 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" wire width 45 \f_badaddr_o @@ -213979,14 +214761,14 @@ module \imem wire width 64 \ibus_rdata attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:69" wire width 64 \ibus_rdata$next - attribute \src "libresoc.v:135392.7-135392.15" + attribute \src "libresoc.v:136408.7-136408.15" wire \initial - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" wire input 7 \wb_icache_en attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:135509$5468 + cell $and $and$libresoc.v:136525$5472 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -213994,10 +214776,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$11 - connect \Y $and$libresoc.v:135509$5468_Y + connect \Y $and$libresoc.v:136525$5472_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:135515$5474 + cell $and $and$libresoc.v:136531$5478 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214005,10 +214787,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$21 - connect \Y $and$libresoc.v:135515$5474_Y + connect \Y $and$libresoc.v:136531$5478_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:135520$5479 + cell $and $and$libresoc.v:136536$5483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214016,10 +214798,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$31 - connect \Y $and$libresoc.v:135520$5479_Y + connect \Y $and$libresoc.v:136536$5483_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:135523$5482 + cell $and $and$libresoc.v:136539$5486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214027,10 +214809,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$1 - connect \Y $and$libresoc.v:135523$5482_Y + connect \Y $and$libresoc.v:136539$5486_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $and $and$libresoc.v:135526$5485 + cell $and $and$libresoc.v:136542$5489 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214038,10 +214820,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \a_valid_i connect \B \$41 - connect \Y $and$libresoc.v:135526$5485_Y + connect \Y $and$libresoc.v:136542$5489_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" - cell $and $and$libresoc.v:135527$5486 + cell $and $and$libresoc.v:136543$5490 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214049,10 +214831,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__cyc connect \B \ibus__err - connect \Y $and$libresoc.v:135527$5486_Y + connect \Y $and$libresoc.v:136543$5490_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" - cell $and $and$libresoc.v:135529$5488 + cell $and $and$libresoc.v:136545$5492 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214060,98 +214842,98 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__cyc connect \B \ibus__err - connect \Y $and$libresoc.v:135529$5488_Y + connect \Y $and$libresoc.v:136545$5492_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:135508$5467 + cell $not $not$libresoc.v:136524$5471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i - connect \Y $not$libresoc.v:135508$5467_Y + connect \Y $not$libresoc.v:136524$5471_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $not $not$libresoc.v:135511$5470 + cell $not $not$libresoc.v:136527$5474 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_valid_i - connect \Y $not$libresoc.v:135511$5470_Y + connect \Y $not$libresoc.v:136527$5474_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:135512$5471 + cell $not $not$libresoc.v:136528$5475 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i - connect \Y $not$libresoc.v:135512$5471_Y + connect \Y $not$libresoc.v:136528$5475_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:135514$5473 + cell $not $not$libresoc.v:136530$5477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i - connect \Y $not$libresoc.v:135514$5473_Y + connect \Y $not$libresoc.v:136530$5477_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $not $not$libresoc.v:135517$5476 + cell $not $not$libresoc.v:136533$5480 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_valid_i - connect \Y $not$libresoc.v:135517$5476_Y + connect \Y $not$libresoc.v:136533$5480_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:135519$5478 + cell $not $not$libresoc.v:136535$5482 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i - connect \Y $not$libresoc.v:135519$5478_Y + connect \Y $not$libresoc.v:136535$5482_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $not $not$libresoc.v:135522$5481 + cell $not $not$libresoc.v:136538$5485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_valid_i - connect \Y $not$libresoc.v:135522$5481_Y + connect \Y $not$libresoc.v:136538$5485_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:78" - cell $not $not$libresoc.v:135525$5484 + cell $not $not$libresoc.v:136541$5488 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_stall_i - connect \Y $not$libresoc.v:135525$5484_Y + connect \Y $not$libresoc.v:136541$5488_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" - cell $not $not$libresoc.v:135528$5487 + cell $not $not$libresoc.v:136544$5491 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_stall_i - connect \Y $not$libresoc.v:135528$5487_Y + connect \Y $not$libresoc.v:136544$5491_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:91" - cell $not $not$libresoc.v:135530$5489 + cell $not $not$libresoc.v:136546$5493 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_stall_i - connect \Y $not$libresoc.v:135530$5489_Y + connect \Y $not$libresoc.v:136546$5493_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $not $not$libresoc.v:135532$5491 + cell $not $not$libresoc.v:136548$5495 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \f_valid_i - connect \Y $not$libresoc.v:135532$5491_Y + connect \Y $not$libresoc.v:136548$5495_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:135507$5466 + cell $or $or$libresoc.v:136523$5470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214159,10 +214941,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \$5 connect \B \$7 - connect \Y $or$libresoc.v:135507$5466_Y + connect \Y $or$libresoc.v:136523$5470_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:135510$5469 + cell $or $or$libresoc.v:136526$5473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214170,10 +214952,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__ack connect \B \ibus__err - connect \Y $or$libresoc.v:135510$5469_Y + connect \Y $or$libresoc.v:136526$5473_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:135513$5472 + cell $or $or$libresoc.v:136529$5476 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214181,10 +214963,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \$15 connect \B \$17 - connect \Y $or$libresoc.v:135513$5472_Y + connect \Y $or$libresoc.v:136529$5476_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:135516$5475 + cell $or $or$libresoc.v:136532$5479 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214192,10 +214974,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__ack connect \B \ibus__err - connect \Y $or$libresoc.v:135516$5475_Y + connect \Y $or$libresoc.v:136532$5479_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:135518$5477 + cell $or $or$libresoc.v:136534$5481 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214203,10 +214985,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \$25 connect \B \$27 - connect \Y $or$libresoc.v:135518$5477_Y + connect \Y $or$libresoc.v:136534$5481_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:135521$5480 + cell $or $or$libresoc.v:136537$5484 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214214,10 +214996,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__ack connect \B \ibus__err - connect \Y $or$libresoc.v:135521$5480_Y + connect \Y $or$libresoc.v:136537$5484_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:135524$5483 + cell $or $or$libresoc.v:136540$5487 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214225,10 +215007,10 @@ module \imem parameter \Y_WIDTH 1 connect \A \$35 connect \B \$37 - connect \Y $or$libresoc.v:135524$5483_Y + connect \Y $or$libresoc.v:136540$5487_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" - cell $or $or$libresoc.v:135531$5490 + cell $or $or$libresoc.v:136547$5494 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -214236,130 +215018,130 @@ module \imem parameter \Y_WIDTH 1 connect \A \ibus__ack connect \B \ibus__err - connect \Y $or$libresoc.v:135531$5490_Y + connect \Y $or$libresoc.v:136547$5494_Y end - attribute \src "libresoc.v:135392.7-135392.20" - process $proc$libresoc.v:135392$5541 + attribute \src "libresoc.v:136408.7-136408.20" + process $proc$libresoc.v:136408$5545 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:135456.14-135456.44" - process $proc$libresoc.v:135456$5542 + attribute \src "libresoc.v:136472.14-136472.44" + process $proc$libresoc.v:136472$5546 assign { } { } assign $1\f_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 sync always sync init update \f_badaddr_o $1\f_badaddr_o[44:0] end - attribute \src "libresoc.v:135463.7-135463.27" - process $proc$libresoc.v:135463$5543 + attribute \src "libresoc.v:136479.7-136479.27" + process $proc$libresoc.v:136479$5547 assign { } { } assign $1\f_fetch_err_o[0:0] 1'0 sync always sync init update \f_fetch_err_o $1\f_fetch_err_o[0:0] end - attribute \src "libresoc.v:135477.14-135477.42" - process $proc$libresoc.v:135477$5544 + attribute \src "libresoc.v:136493.14-136493.42" + process $proc$libresoc.v:136493$5548 assign { } { } assign $1\ibus__adr[44:0] 45'000000000000000000000000000000000000000000000 sync always sync init update \ibus__adr $1\ibus__adr[44:0] end - attribute \src "libresoc.v:135482.7-135482.23" - process $proc$libresoc.v:135482$5545 + attribute \src "libresoc.v:136498.7-136498.23" + process $proc$libresoc.v:136498$5549 assign { } { } assign $1\ibus__cyc[0:0] 1'0 sync always sync init update \ibus__cyc $1\ibus__cyc[0:0] end - attribute \src "libresoc.v:135491.13-135491.30" - process $proc$libresoc.v:135491$5546 + attribute \src "libresoc.v:136507.13-136507.30" + process $proc$libresoc.v:136507$5550 assign { } { } assign $1\ibus__sel[7:0] 8'00000000 sync always sync init update \ibus__sel $1\ibus__sel[7:0] end - attribute \src "libresoc.v:135496.7-135496.23" - process $proc$libresoc.v:135496$5547 + attribute \src "libresoc.v:136512.7-136512.23" + process $proc$libresoc.v:136512$5551 assign { } { } assign $1\ibus__stb[0:0] 1'0 sync always sync init update \ibus__stb $1\ibus__stb[0:0] end - attribute \src "libresoc.v:135500.14-135500.47" - process $proc$libresoc.v:135500$5548 + attribute \src "libresoc.v:136516.14-136516.47" + process $proc$libresoc.v:136516$5552 assign { } { } assign $1\ibus_rdata[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ibus_rdata $1\ibus_rdata[63:0] end - attribute \src "libresoc.v:135533.3-135534.39" - process $proc$libresoc.v:135533$5492 + attribute \src "libresoc.v:136549.3-136550.39" + process $proc$libresoc.v:136549$5496 assign { } { } assign $0\f_badaddr_o[44:0] \f_badaddr_o$next sync posedge \clk update \f_badaddr_o $0\f_badaddr_o[44:0] end - attribute \src "libresoc.v:135535.3-135536.43" - process $proc$libresoc.v:135535$5493 + attribute \src "libresoc.v:136551.3-136552.43" + process $proc$libresoc.v:136551$5497 assign { } { } assign $0\f_fetch_err_o[0:0] \f_fetch_err_o$next sync posedge \clk update \f_fetch_err_o $0\f_fetch_err_o[0:0] end - attribute \src "libresoc.v:135537.3-135538.35" - process $proc$libresoc.v:135537$5494 + attribute \src "libresoc.v:136553.3-136554.35" + process $proc$libresoc.v:136553$5498 assign { } { } assign $0\ibus__adr[44:0] \ibus__adr$next sync posedge \clk update \ibus__adr $0\ibus__adr[44:0] end - attribute \src "libresoc.v:135539.3-135540.37" - process $proc$libresoc.v:135539$5495 + attribute \src "libresoc.v:136555.3-136556.37" + process $proc$libresoc.v:136555$5499 assign { } { } assign $0\ibus_rdata[63:0] \ibus_rdata$next sync posedge \clk update \ibus_rdata $0\ibus_rdata[63:0] end - attribute \src "libresoc.v:135541.3-135542.35" - process $proc$libresoc.v:135541$5496 + attribute \src "libresoc.v:136557.3-136558.35" + process $proc$libresoc.v:136557$5500 assign { } { } assign $0\ibus__sel[7:0] \ibus__sel$next sync posedge \clk update \ibus__sel $0\ibus__sel[7:0] end - attribute \src "libresoc.v:135543.3-135544.35" - process $proc$libresoc.v:135543$5497 + attribute \src "libresoc.v:136559.3-136560.35" + process $proc$libresoc.v:136559$5501 assign { } { } assign $0\ibus__stb[0:0] \ibus__stb$next sync posedge \clk update \ibus__stb $0\ibus__stb[0:0] end - attribute \src "libresoc.v:135545.3-135546.35" - process $proc$libresoc.v:135545$5498 + attribute \src "libresoc.v:136561.3-136562.35" + process $proc$libresoc.v:136561$5502 assign { } { } assign $0\ibus__cyc[0:0] \ibus__cyc$next sync posedge \clk update \ibus__cyc $0\ibus__cyc[0:0] end - attribute \src "libresoc.v:135547.3-135574.6" - process $proc$libresoc.v:135547$5499 + attribute \src "libresoc.v:136563.3-136590.6" + process $proc$libresoc.v:136563$5503 assign { } { } assign { } { } assign { } { } - assign $0\ibus__cyc$next[0:0]$5500 $4\ibus__cyc$next[0:0]$5504 - attribute \src "libresoc.v:135548.5-135548.29" + assign $0\ibus__cyc$next[0:0]$5504 $4\ibus__cyc$next[0:0]$5508 + attribute \src "libresoc.v:136564.5-136564.29" switch \initial - attribute \src "libresoc.v:135548.9-135548.17" + attribute \src "libresoc.v:136564.9-136564.17" case 1'1 case end @@ -214368,53 +215150,53 @@ module \imem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ibus__cyc$next[0:0]$5501 $2\ibus__cyc$next[0:0]$5502 + assign $1\ibus__cyc$next[0:0]$5505 $2\ibus__cyc$next[0:0]$5506 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" switch { \$3 \ibus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\ibus__cyc$next[0:0]$5502 $3\ibus__cyc$next[0:0]$5503 + assign $2\ibus__cyc$next[0:0]$5506 $3\ibus__cyc$next[0:0]$5507 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\ibus__cyc$next[0:0]$5503 1'0 + assign $3\ibus__cyc$next[0:0]$5507 1'0 case - assign $3\ibus__cyc$next[0:0]$5503 \ibus__cyc + assign $3\ibus__cyc$next[0:0]$5507 \ibus__cyc end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\ibus__cyc$next[0:0]$5502 1'1 + assign $2\ibus__cyc$next[0:0]$5506 1'1 case - assign $2\ibus__cyc$next[0:0]$5502 \ibus__cyc + assign $2\ibus__cyc$next[0:0]$5506 \ibus__cyc end case - assign $1\ibus__cyc$next[0:0]$5501 \ibus__cyc + assign $1\ibus__cyc$next[0:0]$5505 \ibus__cyc end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\ibus__cyc$next[0:0]$5504 1'0 + assign $4\ibus__cyc$next[0:0]$5508 1'0 case - assign $4\ibus__cyc$next[0:0]$5504 $1\ibus__cyc$next[0:0]$5501 + assign $4\ibus__cyc$next[0:0]$5508 $1\ibus__cyc$next[0:0]$5505 end sync always - update \ibus__cyc$next $0\ibus__cyc$next[0:0]$5500 + update \ibus__cyc$next $0\ibus__cyc$next[0:0]$5504 end - attribute \src "libresoc.v:135575.3-135602.6" - process $proc$libresoc.v:135575$5505 + attribute \src "libresoc.v:136591.3-136618.6" + process $proc$libresoc.v:136591$5509 assign { } { } assign { } { } assign { } { } - assign $0\ibus__stb$next[0:0]$5506 $4\ibus__stb$next[0:0]$5510 - attribute \src "libresoc.v:135576.5-135576.29" + assign $0\ibus__stb$next[0:0]$5510 $4\ibus__stb$next[0:0]$5514 + attribute \src "libresoc.v:136592.5-136592.29" switch \initial - attribute \src "libresoc.v:135576.9-135576.17" + attribute \src "libresoc.v:136592.9-136592.17" case 1'1 case end @@ -214423,53 +215205,53 @@ module \imem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ibus__stb$next[0:0]$5507 $2\ibus__stb$next[0:0]$5508 + assign $1\ibus__stb$next[0:0]$5511 $2\ibus__stb$next[0:0]$5512 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" switch { \$13 \ibus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\ibus__stb$next[0:0]$5508 $3\ibus__stb$next[0:0]$5509 + assign $2\ibus__stb$next[0:0]$5512 $3\ibus__stb$next[0:0]$5513 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" switch \$19 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\ibus__stb$next[0:0]$5509 1'0 + assign $3\ibus__stb$next[0:0]$5513 1'0 case - assign $3\ibus__stb$next[0:0]$5509 \ibus__stb + assign $3\ibus__stb$next[0:0]$5513 \ibus__stb end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\ibus__stb$next[0:0]$5508 1'1 + assign $2\ibus__stb$next[0:0]$5512 1'1 case - assign $2\ibus__stb$next[0:0]$5508 \ibus__stb + assign $2\ibus__stb$next[0:0]$5512 \ibus__stb end case - assign $1\ibus__stb$next[0:0]$5507 \ibus__stb + assign $1\ibus__stb$next[0:0]$5511 \ibus__stb end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\ibus__stb$next[0:0]$5510 1'0 + assign $4\ibus__stb$next[0:0]$5514 1'0 case - assign $4\ibus__stb$next[0:0]$5510 $1\ibus__stb$next[0:0]$5507 + assign $4\ibus__stb$next[0:0]$5514 $1\ibus__stb$next[0:0]$5511 end sync always - update \ibus__stb$next $0\ibus__stb$next[0:0]$5506 + update \ibus__stb$next $0\ibus__stb$next[0:0]$5510 end - attribute \src "libresoc.v:135603.3-135630.6" - process $proc$libresoc.v:135603$5511 + attribute \src "libresoc.v:136619.3-136646.6" + process $proc$libresoc.v:136619$5515 assign { } { } assign { } { } assign { } { } - assign $0\ibus__sel$next[7:0]$5512 $4\ibus__sel$next[7:0]$5516 - attribute \src "libresoc.v:135604.5-135604.29" + assign $0\ibus__sel$next[7:0]$5516 $4\ibus__sel$next[7:0]$5520 + attribute \src "libresoc.v:136620.5-136620.29" switch \initial - attribute \src "libresoc.v:135604.9-135604.17" + attribute \src "libresoc.v:136620.9-136620.17" case 1'1 case end @@ -214478,53 +215260,53 @@ module \imem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ibus__sel$next[7:0]$5513 $2\ibus__sel$next[7:0]$5514 + assign $1\ibus__sel$next[7:0]$5517 $2\ibus__sel$next[7:0]$5518 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" switch { \$23 \ibus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\ibus__sel$next[7:0]$5514 $3\ibus__sel$next[7:0]$5515 + assign $2\ibus__sel$next[7:0]$5518 $3\ibus__sel$next[7:0]$5519 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" switch \$29 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\ibus__sel$next[7:0]$5515 8'00000000 + assign $3\ibus__sel$next[7:0]$5519 8'00000000 case - assign $3\ibus__sel$next[7:0]$5515 \ibus__sel + assign $3\ibus__sel$next[7:0]$5519 \ibus__sel end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\ibus__sel$next[7:0]$5514 8'11111111 + assign $2\ibus__sel$next[7:0]$5518 8'11111111 case - assign $2\ibus__sel$next[7:0]$5514 \ibus__sel + assign $2\ibus__sel$next[7:0]$5518 \ibus__sel end case - assign $1\ibus__sel$next[7:0]$5513 \ibus__sel + assign $1\ibus__sel$next[7:0]$5517 \ibus__sel end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\ibus__sel$next[7:0]$5516 8'00000000 + assign $4\ibus__sel$next[7:0]$5520 8'00000000 case - assign $4\ibus__sel$next[7:0]$5516 $1\ibus__sel$next[7:0]$5513 + assign $4\ibus__sel$next[7:0]$5520 $1\ibus__sel$next[7:0]$5517 end sync always - update \ibus__sel$next $0\ibus__sel$next[7:0]$5512 + update \ibus__sel$next $0\ibus__sel$next[7:0]$5516 end - attribute \src "libresoc.v:135631.3-135655.6" - process $proc$libresoc.v:135631$5517 + attribute \src "libresoc.v:136647.3-136671.6" + process $proc$libresoc.v:136647$5521 assign { } { } assign { } { } assign { } { } - assign $0\ibus_rdata$next[63:0]$5518 $4\ibus_rdata$next[63:0]$5522 - attribute \src "libresoc.v:135632.5-135632.29" + assign $0\ibus_rdata$next[63:0]$5522 $4\ibus_rdata$next[63:0]$5526 + attribute \src "libresoc.v:136648.5-136648.29" switch \initial - attribute \src "libresoc.v:135632.9-135632.17" + attribute \src "libresoc.v:136648.9-136648.17" case 1'1 case end @@ -214533,49 +215315,49 @@ module \imem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ibus_rdata$next[63:0]$5519 $2\ibus_rdata$next[63:0]$5520 + assign $1\ibus_rdata$next[63:0]$5523 $2\ibus_rdata$next[63:0]$5524 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" switch { \$33 \ibus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\ibus_rdata$next[63:0]$5520 $3\ibus_rdata$next[63:0]$5521 + assign $2\ibus_rdata$next[63:0]$5524 $3\ibus_rdata$next[63:0]$5525 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:71" switch \$39 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\ibus_rdata$next[63:0]$5521 \ibus__dat_r + assign $3\ibus_rdata$next[63:0]$5525 \ibus__dat_r case - assign $3\ibus_rdata$next[63:0]$5521 \ibus_rdata + assign $3\ibus_rdata$next[63:0]$5525 \ibus_rdata end case - assign $2\ibus_rdata$next[63:0]$5520 \ibus_rdata + assign $2\ibus_rdata$next[63:0]$5524 \ibus_rdata end case - assign $1\ibus_rdata$next[63:0]$5519 \ibus_rdata + assign $1\ibus_rdata$next[63:0]$5523 \ibus_rdata end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\ibus_rdata$next[63:0]$5522 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $4\ibus_rdata$next[63:0]$5526 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $4\ibus_rdata$next[63:0]$5522 $1\ibus_rdata$next[63:0]$5519 + assign $4\ibus_rdata$next[63:0]$5526 $1\ibus_rdata$next[63:0]$5523 end sync always - update \ibus_rdata$next $0\ibus_rdata$next[63:0]$5518 + update \ibus_rdata$next $0\ibus_rdata$next[63:0]$5522 end - attribute \src "libresoc.v:135656.3-135678.6" - process $proc$libresoc.v:135656$5523 + attribute \src "libresoc.v:136672.3-136694.6" + process $proc$libresoc.v:136672$5527 assign { } { } assign { } { } assign { } { } - assign $0\ibus__adr$next[44:0]$5524 $3\ibus__adr$next[44:0]$5527 - attribute \src "libresoc.v:135657.5-135657.29" + assign $0\ibus__adr$next[44:0]$5528 $3\ibus__adr$next[44:0]$5531 + attribute \src "libresoc.v:136673.5-136673.29" switch \initial - attribute \src "libresoc.v:135657.9-135657.17" + attribute \src "libresoc.v:136673.9-136673.17" case 1'1 case end @@ -214584,43 +215366,43 @@ module \imem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ibus__adr$next[44:0]$5525 $2\ibus__adr$next[44:0]$5526 + assign $1\ibus__adr$next[44:0]$5529 $2\ibus__adr$next[44:0]$5530 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:70" switch { \$43 \ibus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 - assign $2\ibus__adr$next[44:0]$5526 \ibus__adr + assign $2\ibus__adr$next[44:0]$5530 \ibus__adr attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\ibus__adr$next[44:0]$5526 \a_pc_i [47:3] + assign $2\ibus__adr$next[44:0]$5530 \a_pc_i [47:3] case - assign $2\ibus__adr$next[44:0]$5526 \ibus__adr + assign $2\ibus__adr$next[44:0]$5530 \ibus__adr end case - assign $1\ibus__adr$next[44:0]$5525 \ibus__adr + assign $1\ibus__adr$next[44:0]$5529 \ibus__adr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\ibus__adr$next[44:0]$5527 45'000000000000000000000000000000000000000000000 + assign $3\ibus__adr$next[44:0]$5531 45'000000000000000000000000000000000000000000000 case - assign $3\ibus__adr$next[44:0]$5527 $1\ibus__adr$next[44:0]$5525 + assign $3\ibus__adr$next[44:0]$5531 $1\ibus__adr$next[44:0]$5529 end sync always - update \ibus__adr$next $0\ibus__adr$next[44:0]$5524 + update \ibus__adr$next $0\ibus__adr$next[44:0]$5528 end - attribute \src "libresoc.v:135679.3-135701.6" - process $proc$libresoc.v:135679$5528 + attribute \src "libresoc.v:136695.3-136717.6" + process $proc$libresoc.v:136695$5532 assign { } { } assign { } { } assign { } { } - assign $0\f_fetch_err_o$next[0:0]$5529 $3\f_fetch_err_o$next[0:0]$5532 - attribute \src "libresoc.v:135680.5-135680.29" + assign $0\f_fetch_err_o$next[0:0]$5533 $3\f_fetch_err_o$next[0:0]$5536 + attribute \src "libresoc.v:136696.5-136696.29" switch \initial - attribute \src "libresoc.v:135680.9-135680.17" + attribute \src "libresoc.v:136696.9-136696.17" case 1'1 case end @@ -214629,44 +215411,44 @@ module \imem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\f_fetch_err_o$next[0:0]$5530 $2\f_fetch_err_o$next[0:0]$5531 + assign $1\f_fetch_err_o$next[0:0]$5534 $2\f_fetch_err_o$next[0:0]$5535 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" switch { \$47 \$45 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\f_fetch_err_o$next[0:0]$5531 1'1 + assign $2\f_fetch_err_o$next[0:0]$5535 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\f_fetch_err_o$next[0:0]$5531 1'0 + assign $2\f_fetch_err_o$next[0:0]$5535 1'0 case - assign $2\f_fetch_err_o$next[0:0]$5531 \f_fetch_err_o + assign $2\f_fetch_err_o$next[0:0]$5535 \f_fetch_err_o end case - assign $1\f_fetch_err_o$next[0:0]$5530 \f_fetch_err_o + assign $1\f_fetch_err_o$next[0:0]$5534 \f_fetch_err_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\f_fetch_err_o$next[0:0]$5532 1'0 + assign $3\f_fetch_err_o$next[0:0]$5536 1'0 case - assign $3\f_fetch_err_o$next[0:0]$5532 $1\f_fetch_err_o$next[0:0]$5530 + assign $3\f_fetch_err_o$next[0:0]$5536 $1\f_fetch_err_o$next[0:0]$5534 end sync always - update \f_fetch_err_o$next $0\f_fetch_err_o$next[0:0]$5529 + update \f_fetch_err_o$next $0\f_fetch_err_o$next[0:0]$5533 end - attribute \src "libresoc.v:135702.3-135721.6" - process $proc$libresoc.v:135702$5533 + attribute \src "libresoc.v:136718.3-136737.6" + process $proc$libresoc.v:136718$5537 assign { } { } assign { } { } assign { } { } - assign $0\f_badaddr_o$next[44:0]$5534 $3\f_badaddr_o$next[44:0]$5537 - attribute \src "libresoc.v:135703.5-135703.29" + assign $0\f_badaddr_o$next[44:0]$5538 $3\f_badaddr_o$next[44:0]$5541 + attribute \src "libresoc.v:136719.5-136719.29" switch \initial - attribute \src "libresoc.v:135703.9-135703.17" + attribute \src "libresoc.v:136719.9-136719.17" case 1'1 case end @@ -214675,39 +215457,39 @@ module \imem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\f_badaddr_o$next[44:0]$5535 $2\f_badaddr_o$next[44:0]$5536 + assign $1\f_badaddr_o$next[44:0]$5539 $2\f_badaddr_o$next[44:0]$5540 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" switch { \$51 \$49 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\f_badaddr_o$next[44:0]$5536 \ibus__adr + assign $2\f_badaddr_o$next[44:0]$5540 \ibus__adr case - assign $2\f_badaddr_o$next[44:0]$5536 \f_badaddr_o + assign $2\f_badaddr_o$next[44:0]$5540 \f_badaddr_o end case - assign $1\f_badaddr_o$next[44:0]$5535 \f_badaddr_o + assign $1\f_badaddr_o$next[44:0]$5539 \f_badaddr_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\f_badaddr_o$next[44:0]$5537 45'000000000000000000000000000000000000000000000 + assign $3\f_badaddr_o$next[44:0]$5541 45'000000000000000000000000000000000000000000000 case - assign $3\f_badaddr_o$next[44:0]$5537 $1\f_badaddr_o$next[44:0]$5535 + assign $3\f_badaddr_o$next[44:0]$5541 $1\f_badaddr_o$next[44:0]$5539 end sync always - update \f_badaddr_o$next $0\f_badaddr_o$next[44:0]$5534 + update \f_badaddr_o$next $0\f_badaddr_o$next[44:0]$5538 end - attribute \src "libresoc.v:135722.3-135731.6" - process $proc$libresoc.v:135722$5538 + attribute \src "libresoc.v:136738.3-136747.6" + process $proc$libresoc.v:136738$5542 assign { } { } assign { } { } assign $0\a_busy_o[0:0] $1\a_busy_o[0:0] - attribute \src "libresoc.v:135723.5-135723.29" + attribute \src "libresoc.v:136739.5-136739.29" switch \initial - attribute \src "libresoc.v:135723.9-135723.17" + attribute \src "libresoc.v:136739.9-136739.17" case 1'1 case end @@ -214723,14 +215505,14 @@ module \imem sync always update \a_busy_o $0\a_busy_o[0:0] end - attribute \src "libresoc.v:135732.3-135749.6" - process $proc$libresoc.v:135732$5539 + attribute \src "libresoc.v:136748.3-136765.6" + process $proc$libresoc.v:136748$5543 assign { } { } assign { } { } assign $0\f_busy_o[0:0] $1\f_busy_o[0:0] - attribute \src "libresoc.v:135733.5-135733.29" + attribute \src "libresoc.v:136749.5-136749.29" switch \initial - attribute \src "libresoc.v:135733.9-135733.17" + attribute \src "libresoc.v:136749.9-136749.17" case 1'1 case end @@ -214757,14 +215539,14 @@ module \imem sync always update \f_busy_o $0\f_busy_o[0:0] end - attribute \src "libresoc.v:135750.3-135767.6" - process $proc$libresoc.v:135750$5540 + attribute \src "libresoc.v:136766.3-136783.6" + process $proc$libresoc.v:136766$5544 assign { } { } assign { } { } assign $0\f_instr_o[63:0] $1\f_instr_o[63:0] - attribute \src "libresoc.v:135751.5-135751.29" + attribute \src "libresoc.v:136767.5-136767.29" switch \initial - attribute \src "libresoc.v:135751.9-135751.17" + attribute \src "libresoc.v:136767.9-136767.17" case 1'1 case end @@ -214790,52 +215572,52 @@ module \imem sync always update \f_instr_o $0\f_instr_o[63:0] end - connect \$9 $or$libresoc.v:135507$5466_Y - connect \$11 $not$libresoc.v:135508$5467_Y - connect \$13 $and$libresoc.v:135509$5468_Y - connect \$15 $or$libresoc.v:135510$5469_Y - connect \$17 $not$libresoc.v:135511$5470_Y - connect \$1 $not$libresoc.v:135512$5471_Y - connect \$19 $or$libresoc.v:135513$5472_Y - connect \$21 $not$libresoc.v:135514$5473_Y - connect \$23 $and$libresoc.v:135515$5474_Y - connect \$25 $or$libresoc.v:135516$5475_Y - connect \$27 $not$libresoc.v:135517$5476_Y - connect \$29 $or$libresoc.v:135518$5477_Y - connect \$31 $not$libresoc.v:135519$5478_Y - connect \$33 $and$libresoc.v:135520$5479_Y - connect \$35 $or$libresoc.v:135521$5480_Y - connect \$37 $not$libresoc.v:135522$5481_Y - connect \$3 $and$libresoc.v:135523$5482_Y - connect \$39 $or$libresoc.v:135524$5483_Y - connect \$41 $not$libresoc.v:135525$5484_Y - connect \$43 $and$libresoc.v:135526$5485_Y - connect \$45 $and$libresoc.v:135527$5486_Y - connect \$47 $not$libresoc.v:135528$5487_Y - connect \$49 $and$libresoc.v:135529$5488_Y - connect \$51 $not$libresoc.v:135530$5489_Y - connect \$5 $or$libresoc.v:135531$5490_Y - connect \$7 $not$libresoc.v:135532$5491_Y + connect \$9 $or$libresoc.v:136523$5470_Y + connect \$11 $not$libresoc.v:136524$5471_Y + connect \$13 $and$libresoc.v:136525$5472_Y + connect \$15 $or$libresoc.v:136526$5473_Y + connect \$17 $not$libresoc.v:136527$5474_Y + connect \$1 $not$libresoc.v:136528$5475_Y + connect \$19 $or$libresoc.v:136529$5476_Y + connect \$21 $not$libresoc.v:136530$5477_Y + connect \$23 $and$libresoc.v:136531$5478_Y + connect \$25 $or$libresoc.v:136532$5479_Y + connect \$27 $not$libresoc.v:136533$5480_Y + connect \$29 $or$libresoc.v:136534$5481_Y + connect \$31 $not$libresoc.v:136535$5482_Y + connect \$33 $and$libresoc.v:136536$5483_Y + connect \$35 $or$libresoc.v:136537$5484_Y + connect \$37 $not$libresoc.v:136538$5485_Y + connect \$3 $and$libresoc.v:136539$5486_Y + connect \$39 $or$libresoc.v:136540$5487_Y + connect \$41 $not$libresoc.v:136541$5488_Y + connect \$43 $and$libresoc.v:136542$5489_Y + connect \$45 $and$libresoc.v:136543$5490_Y + connect \$47 $not$libresoc.v:136544$5491_Y + connect \$49 $and$libresoc.v:136545$5492_Y + connect \$51 $not$libresoc.v:136546$5493_Y + connect \$5 $or$libresoc.v:136547$5494_Y + connect \$7 $not$libresoc.v:136548$5495_Y connect \a_stall_i 1'0 connect \f_stall_i 1'0 end -attribute \src "libresoc.v:135774.1-136101.10" +attribute \src "libresoc.v:136790.1-137117.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.input" attribute \generator "nMigen" module \input - attribute \src "libresoc.v:136064.3-136075.6" + attribute \src "libresoc.v:137080.3-137091.6" wire width 64 $0\a[63:0] - attribute \src "libresoc.v:135775.7-135775.20" + attribute \src "libresoc.v:136791.7-136791.20" wire $0\initial[0:0] - attribute \src "libresoc.v:136076.3-136094.6" - wire width 2 $0\xer_ca$23[1:0]$5552 - attribute \src "libresoc.v:136064.3-136075.6" + attribute \src "libresoc.v:137092.3-137110.6" + wire width 2 $0\xer_ca$23[1:0]$5556 + attribute \src "libresoc.v:137080.3-137091.6" wire width 64 $1\a[63:0] - attribute \src "libresoc.v:136076.3-136094.6" - wire width 2 $1\xer_ca$23[1:0]$5553 - attribute \src "libresoc.v:136063.18-136063.100" - wire width 64 $not$libresoc.v:136063$5549_Y + attribute \src "libresoc.v:137092.3-137110.6" + wire width 2 $1\xer_ca$23[1:0]$5557 + attribute \src "libresoc.v:137079.18-137079.100" + wire width 64 $not$libresoc.v:137079$5553_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" wire width 64 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" @@ -215102,7 +215884,7 @@ module \input wire output 33 \alu_op__zero_a$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" wire width 64 \b - attribute \src "libresoc.v:135775.7-135775.15" + attribute \src "libresoc.v:136791.7-136791.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 46 \muxid @@ -215125,28 +215907,28 @@ module \input attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 44 \xer_so$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" - cell $not $not$libresoc.v:136063$5549 + cell $not $not$libresoc.v:137079$5553 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ra - connect \Y $not$libresoc.v:136063$5549_Y + connect \Y $not$libresoc.v:137079$5553_Y end - attribute \src "libresoc.v:135775.7-135775.20" - process $proc$libresoc.v:135775$5554 + attribute \src "libresoc.v:136791.7-136791.20" + process $proc$libresoc.v:136791$5558 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:136064.3-136075.6" - process $proc$libresoc.v:136064$5550 + attribute \src "libresoc.v:137080.3-137091.6" + process $proc$libresoc.v:137080$5554 assign { } { } assign $0\a[63:0] $1\a[63:0] - attribute \src "libresoc.v:136065.5-136065.29" + attribute \src "libresoc.v:137081.5-137081.29" switch \initial - attribute \src "libresoc.v:136065.9-136065.17" + attribute \src "libresoc.v:137081.9-137081.17" case 1'1 case end @@ -215164,14 +215946,14 @@ module \input sync always update \a $0\a[63:0] end - attribute \src "libresoc.v:136076.3-136094.6" - process $proc$libresoc.v:136076$5551 + attribute \src "libresoc.v:137092.3-137110.6" + process $proc$libresoc.v:137092$5555 assign { } { } assign { } { } - assign $0\xer_ca$23[1:0]$5552 $1\xer_ca$23[1:0]$5553 - attribute \src "libresoc.v:136077.5-136077.29" + assign $0\xer_ca$23[1:0]$5556 $1\xer_ca$23[1:0]$5557 + attribute \src "libresoc.v:137093.5-137093.29" switch \initial - attribute \src "libresoc.v:136077.9-136077.17" + attribute \src "libresoc.v:137093.9-137093.17" case 1'1 case end @@ -215180,22 +215962,22 @@ module \input attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\xer_ca$23[1:0]$5553 2'00 + assign $1\xer_ca$23[1:0]$5557 2'00 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\xer_ca$23[1:0]$5553 2'11 + assign $1\xer_ca$23[1:0]$5557 2'11 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\xer_ca$23[1:0]$5553 \xer_ca + assign $1\xer_ca$23[1:0]$5557 \xer_ca case - assign $1\xer_ca$23[1:0]$5553 2'00 + assign $1\xer_ca$23[1:0]$5557 2'00 end sync always - update \xer_ca$23 $0\xer_ca$23[1:0]$5552 + update \xer_ca$23 $0\xer_ca$23[1:0]$5556 end - connect \$24 $not$libresoc.v:136063$5549_Y + connect \$24 $not$libresoc.v:137079$5553_Y connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } connect \muxid$1 \muxid connect \xer_so$22 \xer_so @@ -215203,30 +215985,30 @@ module \input connect \b \rb connect \ra$20 \a end -attribute \src "libresoc.v:136105.1-136433.10" +attribute \src "libresoc.v:137121.1-137449.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.input" attribute \generator "nMigen" module \input$113 - attribute \src "libresoc.v:136395.3-136406.6" + attribute \src "libresoc.v:137411.3-137422.6" wire width 64 $0\a[63:0] - attribute \src "libresoc.v:136106.7-136106.20" + attribute \src "libresoc.v:137122.7-137122.20" wire $0\initial[0:0] - attribute \src "libresoc.v:136407.3-136425.6" - wire width 2 $0\xer_ca$23[1:0]$5558 - attribute \src "libresoc.v:136395.3-136406.6" + attribute \src "libresoc.v:137423.3-137441.6" + wire width 2 $0\xer_ca$23[1:0]$5562 + attribute \src "libresoc.v:137411.3-137422.6" wire width 64 $1\a[63:0] - attribute \src "libresoc.v:136407.3-136425.6" - wire width 2 $1\xer_ca$23[1:0]$5559 - attribute \src "libresoc.v:136394.18-136394.100" - wire width 64 $not$libresoc.v:136394$5555_Y + attribute \src "libresoc.v:137423.3-137441.6" + wire width 2 $1\xer_ca$23[1:0]$5563 + attribute \src "libresoc.v:137410.18-137410.100" + wire width 64 $not$libresoc.v:137410$5559_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" wire width 64 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" wire width 64 \a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" wire width 64 \b - attribute \src "libresoc.v:136106.7-136106.15" + attribute \src "libresoc.v:137122.7-137122.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 46 \muxid @@ -215509,28 +216291,28 @@ module \input$113 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 44 \xer_so$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" - cell $not $not$libresoc.v:136394$5555 + cell $not $not$libresoc.v:137410$5559 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ra - connect \Y $not$libresoc.v:136394$5555_Y + connect \Y $not$libresoc.v:137410$5559_Y end - attribute \src "libresoc.v:136106.7-136106.20" - process $proc$libresoc.v:136106$5560 + attribute \src "libresoc.v:137122.7-137122.20" + process $proc$libresoc.v:137122$5564 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:136395.3-136406.6" - process $proc$libresoc.v:136395$5556 + attribute \src "libresoc.v:137411.3-137422.6" + process $proc$libresoc.v:137411$5560 assign { } { } assign $0\a[63:0] $1\a[63:0] - attribute \src "libresoc.v:136396.5-136396.29" + attribute \src "libresoc.v:137412.5-137412.29" switch \initial - attribute \src "libresoc.v:136396.9-136396.17" + attribute \src "libresoc.v:137412.9-137412.17" case 1'1 case end @@ -215548,14 +216330,14 @@ module \input$113 sync always update \a $0\a[63:0] end - attribute \src "libresoc.v:136407.3-136425.6" - process $proc$libresoc.v:136407$5557 + attribute \src "libresoc.v:137423.3-137441.6" + process $proc$libresoc.v:137423$5561 assign { } { } assign { } { } - assign $0\xer_ca$23[1:0]$5558 $1\xer_ca$23[1:0]$5559 - attribute \src "libresoc.v:136408.5-136408.29" + assign $0\xer_ca$23[1:0]$5562 $1\xer_ca$23[1:0]$5563 + attribute \src "libresoc.v:137424.5-137424.29" switch \initial - attribute \src "libresoc.v:136408.9-136408.17" + attribute \src "libresoc.v:137424.9-137424.17" case 1'1 case end @@ -215564,22 +216346,22 @@ module \input$113 attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\xer_ca$23[1:0]$5559 2'00 + assign $1\xer_ca$23[1:0]$5563 2'00 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\xer_ca$23[1:0]$5559 2'11 + assign $1\xer_ca$23[1:0]$5563 2'11 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\xer_ca$23[1:0]$5559 \xer_ca + assign $1\xer_ca$23[1:0]$5563 \xer_ca case - assign $1\xer_ca$23[1:0]$5559 2'00 + assign $1\xer_ca$23[1:0]$5563 2'00 end sync always - update \xer_ca$23 $0\xer_ca$23[1:0]$5558 + update \xer_ca$23 $0\xer_ca$23[1:0]$5562 end - connect \$24 $not$libresoc.v:136394$5555_Y + connect \$24 $not$libresoc.v:137410$5559_Y connect \rc$21 \rc connect { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } connect \muxid$1 \muxid @@ -215588,26 +216370,26 @@ module \input$113 connect \b \rb connect \ra$19 \a end -attribute \src "libresoc.v:136437.1-136740.10" +attribute \src "libresoc.v:137453.1-137756.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.input" attribute \generator "nMigen" module \input$50 - attribute \src "libresoc.v:136722.3-136733.6" + attribute \src "libresoc.v:137738.3-137749.6" wire width 64 $0\b[63:0] - attribute \src "libresoc.v:136438.7-136438.20" + attribute \src "libresoc.v:137454.7-137454.20" wire $0\initial[0:0] - attribute \src "libresoc.v:136722.3-136733.6" + attribute \src "libresoc.v:137738.3-137749.6" wire width 64 $1\b[63:0] - attribute \src "libresoc.v:136721.18-136721.100" - wire width 64 $not$libresoc.v:136721$5561_Y + attribute \src "libresoc.v:137737.18-137737.100" + wire width 64 $not$libresoc.v:137737$5565_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" wire width 64 \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" wire width 64 \a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" wire width 64 \b - attribute \src "libresoc.v:136438.7-136438.15" + attribute \src "libresoc.v:137454.7-137454.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len @@ -215886,28 +216668,28 @@ module \input$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 43 \xer_so$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" - cell $not $not$libresoc.v:136721$5561 + cell $not $not$libresoc.v:137737$5565 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \rb - connect \Y $not$libresoc.v:136721$5561_Y + connect \Y $not$libresoc.v:137737$5565_Y end - attribute \src "libresoc.v:136438.7-136438.20" - process $proc$libresoc.v:136438$5563 + attribute \src "libresoc.v:137454.7-137454.20" + process $proc$libresoc.v:137454$5567 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:136722.3-136733.6" - process $proc$libresoc.v:136722$5562 + attribute \src "libresoc.v:137738.3-137749.6" + process $proc$libresoc.v:137738$5566 assign { } { } assign $0\b[63:0] $1\b[63:0] - attribute \src "libresoc.v:136723.5-136723.29" + attribute \src "libresoc.v:137739.5-137739.29" switch \initial - attribute \src "libresoc.v:136723.9-136723.17" + attribute \src "libresoc.v:137739.9-137739.17" case 1'1 case end @@ -215925,7 +216707,7 @@ module \input$50 sync always update \b $0\b[63:0] end - connect \$23 $not$libresoc.v:136721$5561_Y + connect \$23 $not$libresoc.v:137737$5565_Y connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid connect \xer_so$22 \xer_so @@ -215933,26 +216715,26 @@ module \input$50 connect \ra$20 \a connect \a \ra end -attribute \src "libresoc.v:136744.1-137047.10" +attribute \src "libresoc.v:137760.1-138063.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.input" attribute \generator "nMigen" module \input$78 - attribute \src "libresoc.v:137029.3-137040.6" + attribute \src "libresoc.v:138045.3-138056.6" wire width 64 $0\a[63:0] - attribute \src "libresoc.v:136745.7-136745.20" + attribute \src "libresoc.v:137761.7-137761.20" wire $0\initial[0:0] - attribute \src "libresoc.v:137029.3-137040.6" + attribute \src "libresoc.v:138045.3-138056.6" wire width 64 $1\a[63:0] - attribute \src "libresoc.v:137028.18-137028.100" - wire width 64 $not$libresoc.v:137028$5564_Y + attribute \src "libresoc.v:138044.18-138044.100" + wire width 64 $not$libresoc.v:138044$5568_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" wire width 64 \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" wire width 64 \a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" wire width 64 \b - attribute \src "libresoc.v:136745.7-136745.15" + attribute \src "libresoc.v:137761.7-137761.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len @@ -216231,28 +217013,28 @@ module \input$78 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 43 \xer_so$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" - cell $not $not$libresoc.v:137028$5564 + cell $not $not$libresoc.v:138044$5568 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ra - connect \Y $not$libresoc.v:137028$5564_Y + connect \Y $not$libresoc.v:138044$5568_Y end - attribute \src "libresoc.v:136745.7-136745.20" - process $proc$libresoc.v:136745$5566 + attribute \src "libresoc.v:137761.7-137761.20" + process $proc$libresoc.v:137761$5570 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:137029.3-137040.6" - process $proc$libresoc.v:137029$5565 + attribute \src "libresoc.v:138045.3-138056.6" + process $proc$libresoc.v:138045$5569 assign { } { } assign $0\a[63:0] $1\a[63:0] - attribute \src "libresoc.v:137030.5-137030.29" + attribute \src "libresoc.v:138046.5-138046.29" switch \initial - attribute \src "libresoc.v:137030.9-137030.17" + attribute \src "libresoc.v:138046.9-138046.17" case 1'1 case end @@ -216270,7 +217052,7 @@ module \input$78 sync always update \a $0\a[63:0] end - connect \$23 $not$libresoc.v:137028$5564_Y + connect \$23 $not$libresoc.v:138044$5568_Y connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid connect \xer_so$22 \xer_so @@ -216278,7 +217060,7 @@ module \input$78 connect \b \rb connect \ra$20 \a end -attribute \src "libresoc.v:137051.1-137307.10" +attribute \src "libresoc.v:138067.1-138323.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.input" attribute \generator "nMigen" @@ -216539,118 +217321,124 @@ module \input$95 connect \ra$14 \a connect \a \ra end -attribute \src "libresoc.v:137311.1-137571.10" +attribute \src "libresoc.v:138327.1-138587.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.int" attribute \generator "nMigen" module \int - attribute \src "libresoc.v:137453.3-137460.6" - wire width 5 $0$memwr$\memory$libresoc.v:137459$5599_ADDR[4:0]$5610 - attribute \src "libresoc.v:137453.3-137460.6" - wire width 64 $0$memwr$\memory$libresoc.v:137459$5599_DATA[63:0]$5611 - attribute \src "libresoc.v:137453.3-137460.6" - wire width 64 $0$memwr$\memory$libresoc.v:137459$5599_EN[63:0]$5612 - attribute \src "libresoc.v:137453.3-137460.6" + attribute \src "libresoc.v:138459.3-138466.6" + wire width 5 $0$memwr$\memory$libresoc.v:138465$5603_ADDR[4:0]$5605 + attribute \src "libresoc.v:138459.3-138466.6" + wire width 64 $0$memwr$\memory$libresoc.v:138465$5603_DATA[63:0]$5606 + attribute \src "libresoc.v:138459.3-138466.6" + wire width 64 $0$memwr$\memory$libresoc.v:138465$5603_EN[63:0]$5607 + attribute \src "libresoc.v:138459.3-138466.6" wire width 5 $0\_0_[4:0] - attribute \src "libresoc.v:137453.3-137460.6" + attribute \src "libresoc.v:138459.3-138466.6" wire width 5 $0\_1_[4:0] - attribute \src "libresoc.v:137453.3-137460.6" + attribute \src "libresoc.v:138459.3-138466.6" wire width 5 $0\_2_[4:0] - attribute \src "libresoc.v:137453.3-137460.6" + attribute \src "libresoc.v:138459.3-138466.6" wire width 5 $0\_3_[4:0] - attribute \src "libresoc.v:137453.3-137460.6" + attribute \src "libresoc.v:138459.3-138466.6" wire width 5 $0\_4_[4:0] - attribute \src "libresoc.v:137503.3-137512.6" + attribute \src "libresoc.v:138519.3-138528.6" wire width 64 $0\dmi__data_o[63:0] - attribute \src "libresoc.v:137312.7-137312.20" + attribute \src "libresoc.v:138328.7-138328.20" wire $0\initial[0:0] - attribute \src "libresoc.v:137484.3-137493.6" + attribute \src "libresoc.v:138500.3-138509.6" wire width 64 $0\pred__data_o[63:0] - attribute \src "libresoc.v:137523.3-137531.6" - wire $0\ren_delay$10$next[0:0]$5631 - attribute \src "libresoc.v:137409.3-137410.43" - wire $0\ren_delay$10[0:0]$5607 - attribute \src "libresoc.v:137365.7-137365.28" - wire $0\ren_delay$10[0:0]$5674 - attribute \src "libresoc.v:137542.3-137550.6" - wire $0\ren_delay$11$next[0:0]$5635 - attribute \src "libresoc.v:137407.3-137408.43" - wire $0\ren_delay$11[0:0]$5605 - attribute \src "libresoc.v:137369.7-137369.28" - wire $0\ren_delay$11[0:0]$5676 - attribute \src "libresoc.v:137475.3-137483.6" - wire $0\ren_delay$12$next[0:0]$5622 - attribute \src "libresoc.v:137405.3-137406.43" - wire $0\ren_delay$12[0:0]$5603 - attribute \src "libresoc.v:137373.7-137373.28" - wire $0\ren_delay$12[0:0]$5678 - attribute \src "libresoc.v:137494.3-137502.6" - wire $0\ren_delay$13$next[0:0]$5626 - attribute \src "libresoc.v:137403.3-137404.43" - wire $0\ren_delay$13[0:0]$5601 - attribute \src "libresoc.v:137377.7-137377.28" - wire $0\ren_delay$13[0:0]$5680 - attribute \src "libresoc.v:137466.3-137474.6" - wire $0\ren_delay$next[0:0]$5619 - attribute \src "libresoc.v:137411.3-137412.35" + attribute \src "libresoc.v:138539.3-138547.6" + wire $0\ren_delay$10$next[0:0]$5638 + attribute \src "libresoc.v:138478.3-138479.43" + wire $0\ren_delay$10[0:0]$5623 + attribute \src "libresoc.v:138381.7-138381.28" + wire $0\ren_delay$10[0:0]$5680 + attribute \src "libresoc.v:138558.3-138566.6" + wire $0\ren_delay$11$next[0:0]$5642 + attribute \src "libresoc.v:138476.3-138477.43" + wire $0\ren_delay$11[0:0]$5621 + attribute \src "libresoc.v:138385.7-138385.28" + wire $0\ren_delay$11[0:0]$5682 + attribute \src "libresoc.v:138491.3-138499.6" + wire $0\ren_delay$12$next[0:0]$5629 + attribute \src "libresoc.v:138474.3-138475.43" + wire $0\ren_delay$12[0:0]$5619 + attribute \src "libresoc.v:138389.7-138389.28" + wire $0\ren_delay$12[0:0]$5684 + attribute \src "libresoc.v:138510.3-138518.6" + wire $0\ren_delay$13$next[0:0]$5633 + attribute \src "libresoc.v:138472.3-138473.43" + wire $0\ren_delay$13[0:0]$5617 + attribute \src "libresoc.v:138393.7-138393.28" + wire $0\ren_delay$13[0:0]$5686 + attribute \src "libresoc.v:138482.3-138490.6" + wire $0\ren_delay$next[0:0]$5626 + attribute \src "libresoc.v:138480.3-138481.35" wire $0\ren_delay[0:0] - attribute \src "libresoc.v:137513.3-137522.6" + attribute \src "libresoc.v:138529.3-138538.6" wire width 64 $0\src1__data_o[63:0] - attribute \src "libresoc.v:137532.3-137541.6" + attribute \src "libresoc.v:138548.3-138557.6" wire width 64 $0\src2__data_o[63:0] - attribute \src "libresoc.v:137551.3-137560.6" + attribute \src "libresoc.v:138567.3-138576.6" wire width 64 $0\src3__data_o[63:0] - attribute \src "libresoc.v:137503.3-137512.6" + attribute \src "libresoc.v:138459.3-138466.6" + wire width 5 $1$memwr$\memory$libresoc.v:138465$5603_ADDR[4:0]$5608 + attribute \src "libresoc.v:138459.3-138466.6" + wire width 64 $1$memwr$\memory$libresoc.v:138465$5603_DATA[63:0]$5609 + attribute \src "libresoc.v:138459.3-138466.6" + wire width 64 $1$memwr$\memory$libresoc.v:138465$5603_EN[63:0]$5610 + attribute \src "libresoc.v:138519.3-138528.6" wire width 64 $1\dmi__data_o[63:0] - attribute \src "libresoc.v:137484.3-137493.6" + attribute \src "libresoc.v:138500.3-138509.6" wire width 64 $1\pred__data_o[63:0] - attribute \src "libresoc.v:137523.3-137531.6" - wire $1\ren_delay$10$next[0:0]$5632 - attribute \src "libresoc.v:137542.3-137550.6" - wire $1\ren_delay$11$next[0:0]$5636 - attribute \src "libresoc.v:137475.3-137483.6" - wire $1\ren_delay$12$next[0:0]$5623 - attribute \src "libresoc.v:137494.3-137502.6" - wire $1\ren_delay$13$next[0:0]$5627 - attribute \src "libresoc.v:137466.3-137474.6" - wire $1\ren_delay$next[0:0]$5620 - attribute \src "libresoc.v:137363.7-137363.23" + attribute \src "libresoc.v:138539.3-138547.6" + wire $1\ren_delay$10$next[0:0]$5639 + attribute \src "libresoc.v:138558.3-138566.6" + wire $1\ren_delay$11$next[0:0]$5643 + attribute \src "libresoc.v:138491.3-138499.6" + wire $1\ren_delay$12$next[0:0]$5630 + attribute \src "libresoc.v:138510.3-138518.6" + wire $1\ren_delay$13$next[0:0]$5634 + attribute \src "libresoc.v:138482.3-138490.6" + wire $1\ren_delay$next[0:0]$5627 + attribute \src "libresoc.v:138379.7-138379.23" wire $1\ren_delay[0:0] - attribute \src "libresoc.v:137513.3-137522.6" + attribute \src "libresoc.v:138529.3-138538.6" wire width 64 $1\src1__data_o[63:0] - attribute \src "libresoc.v:137532.3-137541.6" + attribute \src "libresoc.v:138548.3-138557.6" wire width 64 $1\src2__data_o[63:0] - attribute \src "libresoc.v:137551.3-137560.6" + attribute \src "libresoc.v:138567.3-138576.6" wire width 64 $1\src3__data_o[63:0] - attribute \src "libresoc.v:137461.26-137461.32" - wire width 64 $memrd$\memory$libresoc.v:137461$5613_DATA - attribute \src "libresoc.v:137462.30-137462.36" - wire width 64 $memrd$\memory$libresoc.v:137462$5614_DATA - attribute \src "libresoc.v:137463.30-137463.36" - wire width 64 $memrd$\memory$libresoc.v:137463$5615_DATA - attribute \src "libresoc.v:137464.30-137464.36" - wire width 64 $memrd$\memory$libresoc.v:137464$5616_DATA - attribute \src "libresoc.v:137465.30-137465.36" - wire width 64 $memrd$\memory$libresoc.v:137465$5617_DATA + attribute \src "libresoc.v:138467.26-138467.32" + wire width 64 $memrd$\memory$libresoc.v:138467$5611_DATA + attribute \src "libresoc.v:138468.30-138468.36" + wire width 64 $memrd$\memory$libresoc.v:138468$5612_DATA + attribute \src "libresoc.v:138469.30-138469.36" + wire width 64 $memrd$\memory$libresoc.v:138469$5613_DATA + attribute \src "libresoc.v:138470.30-138470.36" + wire width 64 $memrd$\memory$libresoc.v:138470$5614_DATA + attribute \src "libresoc.v:138471.30-138471.36" + wire width 64 $memrd$\memory$libresoc.v:138471$5615_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 5 $memwr$\memory$libresoc.v:137459$5599_ADDR + wire width 5 $memwr$\memory$libresoc.v:138465$5603_ADDR attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:137459$5599_DATA + wire width 64 $memwr$\memory$libresoc.v:138465$5603_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:137459$5599_EN - attribute \src "libresoc.v:137448.13-137448.16" + wire width 64 $memwr$\memory$libresoc.v:138465$5603_EN + attribute \src "libresoc.v:138454.13-138454.16" wire width 5 \_0_ - attribute \src "libresoc.v:137449.13-137449.16" + attribute \src "libresoc.v:138455.13-138455.16" wire width 5 \_1_ - attribute \src "libresoc.v:137450.13-137450.16" + attribute \src "libresoc.v:138456.13-138456.16" wire width 5 \_2_ - attribute \src "libresoc.v:137451.13-137451.16" + attribute \src "libresoc.v:138457.13-138457.16" wire width 5 \_3_ - attribute \src "libresoc.v:137452.13-137452.16" + attribute \src "libresoc.v:138458.13-138458.16" wire width 5 \_4_ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 17 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 5 input 15 \dest1__addr @@ -216664,7 +217452,7 @@ module \int wire width 64 output 4 \dmi__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 3 \dmi__ren - attribute \src "libresoc.v:137312.7-137312.15" + attribute \src "libresoc.v:138328.7-138328.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 5 \memory_r_addr @@ -216736,330 +217524,330 @@ module \int wire width 64 output 11 \src3__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 13 \src3__ren - attribute \src "libresoc.v:137413.14-137413.20" + attribute \src "libresoc.v:138419.14-138419.20" memory width 64 size 32 \memory - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5638 + attribute \src "libresoc.v:138421.5-138421.37" + cell $meminit $meminit$\memory$libresoc.v:138421$5645 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5638 + parameter \PRIORITY 5645 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 0 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5639 + attribute \src "libresoc.v:138422.5-138422.37" + cell $meminit $meminit$\memory$libresoc.v:138422$5646 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5639 + parameter \PRIORITY 5646 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 1 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5640 + attribute \src "libresoc.v:138423.5-138423.37" + cell $meminit $meminit$\memory$libresoc.v:138423$5647 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5640 + parameter \PRIORITY 5647 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 2 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5641 + attribute \src "libresoc.v:138424.5-138424.37" + cell $meminit $meminit$\memory$libresoc.v:138424$5648 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5641 + parameter \PRIORITY 5648 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 3 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5642 + attribute \src "libresoc.v:138425.5-138425.37" + cell $meminit $meminit$\memory$libresoc.v:138425$5649 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5642 + parameter \PRIORITY 5649 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 4 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5643 + attribute \src "libresoc.v:138426.5-138426.37" + cell $meminit $meminit$\memory$libresoc.v:138426$5650 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5643 + parameter \PRIORITY 5650 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 5 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5644 + attribute \src "libresoc.v:138427.5-138427.37" + cell $meminit $meminit$\memory$libresoc.v:138427$5651 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5644 + parameter \PRIORITY 5651 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 6 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5645 + attribute \src "libresoc.v:138428.5-138428.37" + cell $meminit $meminit$\memory$libresoc.v:138428$5652 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5645 + parameter \PRIORITY 5652 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 7 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5646 + attribute \src "libresoc.v:138429.5-138429.37" + cell $meminit $meminit$\memory$libresoc.v:138429$5653 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5646 + parameter \PRIORITY 5653 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 8 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5647 + attribute \src "libresoc.v:138430.5-138430.37" + cell $meminit $meminit$\memory$libresoc.v:138430$5654 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5647 + parameter \PRIORITY 5654 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 9 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5648 + attribute \src "libresoc.v:138431.5-138431.38" + cell $meminit $meminit$\memory$libresoc.v:138431$5655 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5648 + parameter \PRIORITY 5655 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 10 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5649 + attribute \src "libresoc.v:138432.5-138432.38" + cell $meminit $meminit$\memory$libresoc.v:138432$5656 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5649 + parameter \PRIORITY 5656 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 11 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5650 + attribute \src "libresoc.v:138433.5-138433.38" + cell $meminit $meminit$\memory$libresoc.v:138433$5657 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5650 + parameter \PRIORITY 5657 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 12 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5651 + attribute \src "libresoc.v:138434.5-138434.38" + cell $meminit $meminit$\memory$libresoc.v:138434$5658 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5651 + parameter \PRIORITY 5658 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 13 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5652 + attribute \src "libresoc.v:138435.5-138435.38" + cell $meminit $meminit$\memory$libresoc.v:138435$5659 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5652 + parameter \PRIORITY 5659 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 14 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5653 + attribute \src "libresoc.v:138436.5-138436.38" + cell $meminit $meminit$\memory$libresoc.v:138436$5660 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5653 + parameter \PRIORITY 5660 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 15 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5654 + attribute \src "libresoc.v:138437.5-138437.38" + cell $meminit $meminit$\memory$libresoc.v:138437$5661 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5654 + parameter \PRIORITY 5661 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 16 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5655 + attribute \src "libresoc.v:138438.5-138438.38" + cell $meminit $meminit$\memory$libresoc.v:138438$5662 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5655 + parameter \PRIORITY 5662 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 17 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5656 + attribute \src "libresoc.v:138439.5-138439.38" + cell $meminit $meminit$\memory$libresoc.v:138439$5663 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5656 + parameter \PRIORITY 5663 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 18 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5657 + attribute \src "libresoc.v:138440.5-138440.38" + cell $meminit $meminit$\memory$libresoc.v:138440$5664 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5657 + parameter \PRIORITY 5664 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 19 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5658 + attribute \src "libresoc.v:138441.5-138441.38" + cell $meminit $meminit$\memory$libresoc.v:138441$5665 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5658 + parameter \PRIORITY 5665 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 20 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5659 + attribute \src "libresoc.v:138442.5-138442.38" + cell $meminit $meminit$\memory$libresoc.v:138442$5666 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5659 + parameter \PRIORITY 5666 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 21 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5660 + attribute \src "libresoc.v:138443.5-138443.38" + cell $meminit $meminit$\memory$libresoc.v:138443$5667 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5660 + parameter \PRIORITY 5667 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 22 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5661 + attribute \src "libresoc.v:138444.5-138444.38" + cell $meminit $meminit$\memory$libresoc.v:138444$5668 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5661 + parameter \PRIORITY 5668 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 23 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5662 + attribute \src "libresoc.v:138445.5-138445.38" + cell $meminit $meminit$\memory$libresoc.v:138445$5669 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5662 + parameter \PRIORITY 5669 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 24 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5663 + attribute \src "libresoc.v:138446.5-138446.38" + cell $meminit $meminit$\memory$libresoc.v:138446$5670 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5663 + parameter \PRIORITY 5670 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 25 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5664 + attribute \src "libresoc.v:138447.5-138447.38" + cell $meminit $meminit$\memory$libresoc.v:138447$5671 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5664 + parameter \PRIORITY 5671 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 26 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5665 + attribute \src "libresoc.v:138448.5-138448.38" + cell $meminit $meminit$\memory$libresoc.v:138448$5672 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5665 + parameter \PRIORITY 5672 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 27 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5666 + attribute \src "libresoc.v:138449.5-138449.38" + cell $meminit $meminit$\memory$libresoc.v:138449$5673 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5666 + parameter \PRIORITY 5673 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 28 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5667 + attribute \src "libresoc.v:138450.5-138450.38" + cell $meminit $meminit$\memory$libresoc.v:138450$5674 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5667 + parameter \PRIORITY 5674 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 29 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5668 + attribute \src "libresoc.v:138451.5-138451.38" + cell $meminit $meminit$\memory$libresoc.v:138451$5675 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5668 + parameter \PRIORITY 5675 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 30 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$5669 + attribute \src "libresoc.v:138452.5-138452.38" + cell $meminit $meminit$\memory$libresoc.v:138452$5676 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 5669 + parameter \PRIORITY 5676 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 31 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:137461.26-137461.32" - cell $memrd $memrd$\memory$libresoc.v:137461$5613 + attribute \src "libresoc.v:138467.26-138467.32" + cell $memrd $memrd$\memory$libresoc.v:138467$5611 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -217068,11 +217856,11 @@ module \int parameter \WIDTH 64 connect \ADDR \_0_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:137461$5613_DATA + connect \DATA $memrd$\memory$libresoc.v:138467$5611_DATA connect \EN 1'x end - attribute \src "libresoc.v:137462.30-137462.36" - cell $memrd $memrd$\memory$libresoc.v:137462$5614 + attribute \src "libresoc.v:138468.30-138468.36" + cell $memrd $memrd$\memory$libresoc.v:138468$5612 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -217081,11 +217869,11 @@ module \int parameter \WIDTH 64 connect \ADDR \_1_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:137462$5614_DATA + connect \DATA $memrd$\memory$libresoc.v:138468$5612_DATA connect \EN 1'x end - attribute \src "libresoc.v:137463.30-137463.36" - cell $memrd $memrd$\memory$libresoc.v:137463$5615 + attribute \src "libresoc.v:138469.30-138469.36" + cell $memrd $memrd$\memory$libresoc.v:138469$5613 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -217094,11 +217882,11 @@ module \int parameter \WIDTH 64 connect \ADDR \_2_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:137463$5615_DATA + connect \DATA $memrd$\memory$libresoc.v:138469$5613_DATA connect \EN 1'x end - attribute \src "libresoc.v:137464.30-137464.36" - cell $memrd $memrd$\memory$libresoc.v:137464$5616 + attribute \src "libresoc.v:138470.30-138470.36" + cell $memrd $memrd$\memory$libresoc.v:138470$5614 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -217107,11 +217895,11 @@ module \int parameter \WIDTH 64 connect \ADDR \_3_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:137464$5616_DATA + connect \DATA $memrd$\memory$libresoc.v:138470$5614_DATA connect \EN 1'x end - attribute \src "libresoc.v:137465.30-137465.36" - cell $memrd $memrd$\memory$libresoc.v:137465$5617 + attribute \src "libresoc.v:138471.30-138471.36" + cell $memrd $memrd$\memory$libresoc.v:138471$5615 parameter \ABITS 5 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -217120,112 +217908,67 @@ module \int parameter \WIDTH 64 connect \ADDR \_4_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:137465$5617_DATA + connect \DATA $memrd$\memory$libresoc.v:138471$5615_DATA connect \EN 1'x end attribute \src "libresoc.v:0.0-0.0" - cell $memwr $memwr$\memory$libresoc.v:0$5670 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \PRIORITY 5670 - parameter \WIDTH 64 - connect \ADDR $memwr$\memory$libresoc.v:137459$5599_ADDR - connect \CLK 1'x - connect \DATA $memwr$\memory$libresoc.v:137459$5599_DATA - connect \EN $memwr$\memory$libresoc.v:137459$5599_EN - end - attribute \src "libresoc.v:0.0-0.0" - process $proc$libresoc.v:0$5681 + process $proc$libresoc.v:0$5687 sync always sync init end - attribute \src "libresoc.v:137312.7-137312.20" - process $proc$libresoc.v:137312$5671 + attribute \src "libresoc.v:138328.7-138328.20" + process $proc$libresoc.v:138328$5677 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:137363.7-137363.23" - process $proc$libresoc.v:137363$5672 + attribute \src "libresoc.v:138379.7-138379.23" + process $proc$libresoc.v:138379$5678 assign { } { } assign $1\ren_delay[0:0] 1'0 sync always sync init update \ren_delay $1\ren_delay[0:0] end - attribute \src "libresoc.v:137365.7-137365.28" - process $proc$libresoc.v:137365$5673 + attribute \src "libresoc.v:138381.7-138381.28" + process $proc$libresoc.v:138381$5679 assign { } { } - assign $0\ren_delay$10[0:0]$5674 1'0 + assign $0\ren_delay$10[0:0]$5680 1'0 sync always sync init - update \ren_delay$10 $0\ren_delay$10[0:0]$5674 + update \ren_delay$10 $0\ren_delay$10[0:0]$5680 end - attribute \src "libresoc.v:137369.7-137369.28" - process $proc$libresoc.v:137369$5675 + attribute \src "libresoc.v:138385.7-138385.28" + process $proc$libresoc.v:138385$5681 assign { } { } - assign $0\ren_delay$11[0:0]$5676 1'0 + assign $0\ren_delay$11[0:0]$5682 1'0 sync always sync init - update \ren_delay$11 $0\ren_delay$11[0:0]$5676 + update \ren_delay$11 $0\ren_delay$11[0:0]$5682 end - attribute \src "libresoc.v:137373.7-137373.28" - process $proc$libresoc.v:137373$5677 + attribute \src "libresoc.v:138389.7-138389.28" + process $proc$libresoc.v:138389$5683 assign { } { } - assign $0\ren_delay$12[0:0]$5678 1'0 + assign $0\ren_delay$12[0:0]$5684 1'0 sync always sync init - update \ren_delay$12 $0\ren_delay$12[0:0]$5678 + update \ren_delay$12 $0\ren_delay$12[0:0]$5684 end - attribute \src "libresoc.v:137377.7-137377.28" - process $proc$libresoc.v:137377$5679 + attribute \src "libresoc.v:138393.7-138393.28" + process $proc$libresoc.v:138393$5685 assign { } { } - assign $0\ren_delay$13[0:0]$5680 1'0 + assign $0\ren_delay$13[0:0]$5686 1'0 sync always sync init - update \ren_delay$13 $0\ren_delay$13[0:0]$5680 + update \ren_delay$13 $0\ren_delay$13[0:0]$5686 end - attribute \src "libresoc.v:137403.3-137404.43" - process $proc$libresoc.v:137403$5600 + attribute \src "libresoc.v:138459.3-138466.6" + process $proc$libresoc.v:138459$5604 assign { } { } - assign $0\ren_delay$13[0:0]$5601 \ren_delay$13$next - sync posedge \coresync_clk - update \ren_delay$13 $0\ren_delay$13[0:0]$5601 - end - attribute \src "libresoc.v:137405.3-137406.43" - process $proc$libresoc.v:137405$5602 assign { } { } - assign $0\ren_delay$12[0:0]$5603 \ren_delay$12$next - sync posedge \coresync_clk - update \ren_delay$12 $0\ren_delay$12[0:0]$5603 - end - attribute \src "libresoc.v:137407.3-137408.43" - process $proc$libresoc.v:137407$5604 assign { } { } - assign $0\ren_delay$11[0:0]$5605 \ren_delay$11$next - sync posedge \coresync_clk - update \ren_delay$11 $0\ren_delay$11[0:0]$5605 - end - attribute \src "libresoc.v:137409.3-137410.43" - process $proc$libresoc.v:137409$5606 - assign { } { } - assign $0\ren_delay$10[0:0]$5607 \ren_delay$10$next - sync posedge \coresync_clk - update \ren_delay$10 $0\ren_delay$10[0:0]$5607 - end - attribute \src "libresoc.v:137411.3-137412.35" - process $proc$libresoc.v:137411$5608 - assign { } { } - assign $0\ren_delay[0:0] \ren_delay$next - sync posedge \coresync_clk - update \ren_delay $0\ren_delay[0:0] - end - attribute \src "libresoc.v:137453.3-137460.6" - process $proc$libresoc.v:137453$5609 assign { } { } assign { } { } assign { } { } @@ -217234,22 +217977,28 @@ module \int assign { } { } assign { } { } assign { } { } - assign $0$memwr$\memory$libresoc.v:137459$5599_ADDR[4:0]$5610 5'xxxxx - assign $0$memwr$\memory$libresoc.v:137459$5599_DATA[63:0]$5611 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\memory$libresoc.v:137459$5599_EN[63:0]$5612 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\_0_[4:0] \src1__addr - assign $0\_1_[4:0] \src2__addr - assign $0\_2_[4:0] \src3__addr - assign $0\_3_[4:0] 5'00000 - assign $0\_4_[4:0] \dmi__addr - attribute \src "libresoc.v:137459.5-137459.58" - switch \dest1__wen - attribute \src "libresoc.v:137459.9-137459.19" + assign $0\_0_[4:0] \memory_r_addr + assign $0\_1_[4:0] \memory_r_addr$2 + assign $0\_2_[4:0] \memory_r_addr$4 + assign $0\_3_[4:0] \memory_r_addr$6 + assign $0\_4_[4:0] \memory_r_addr$8 + assign $0$memwr$\memory$libresoc.v:138465$5603_ADDR[4:0]$5605 $1$memwr$\memory$libresoc.v:138465$5603_ADDR[4:0]$5608 + assign $0$memwr$\memory$libresoc.v:138465$5603_DATA[63:0]$5606 $1$memwr$\memory$libresoc.v:138465$5603_DATA[63:0]$5609 + assign $0$memwr$\memory$libresoc.v:138465$5603_EN[63:0]$5607 $1$memwr$\memory$libresoc.v:138465$5603_EN[63:0]$5610 + attribute \src "libresoc.v:138465.5-138465.61" + switch \memory_w_en + attribute \src "libresoc.v:138465.9-138465.20" case 1'1 - assign $0$memwr$\memory$libresoc.v:137459$5599_ADDR[4:0]$5610 \dest1__addr - assign $0$memwr$\memory$libresoc.v:137459$5599_DATA[63:0]$5611 \dest1__data_i - assign $0$memwr$\memory$libresoc.v:137459$5599_EN[63:0]$5612 64'1111111111111111111111111111111111111111111111111111111111111111 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\memory$libresoc.v:138465$5603_ADDR[4:0]$5608 \memory_w_addr + assign $1$memwr$\memory$libresoc.v:138465$5603_DATA[63:0]$5609 \memory_w_data + assign $1$memwr$\memory$libresoc.v:138465$5603_EN[63:0]$5610 64'1111111111111111111111111111111111111111111111111111111111111111 case + assign $1$memwr$\memory$libresoc.v:138465$5603_ADDR[4:0]$5608 5'xxxxx + assign $1$memwr$\memory$libresoc.v:138465$5603_DATA[63:0]$5609 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\memory$libresoc.v:138465$5603_EN[63:0]$5610 64'0000000000000000000000000000000000000000000000000000000000000000 end sync posedge \coresync_clk update \_0_ $0\_0_[4:0] @@ -217257,18 +218006,55 @@ module \int update \_2_ $0\_2_[4:0] update \_3_ $0\_3_[4:0] update \_4_ $0\_4_[4:0] - update $memwr$\memory$libresoc.v:137459$5599_ADDR $0$memwr$\memory$libresoc.v:137459$5599_ADDR[4:0]$5610 - update $memwr$\memory$libresoc.v:137459$5599_DATA $0$memwr$\memory$libresoc.v:137459$5599_DATA[63:0]$5611 - update $memwr$\memory$libresoc.v:137459$5599_EN $0$memwr$\memory$libresoc.v:137459$5599_EN[63:0]$5612 + update $memwr$\memory$libresoc.v:138465$5603_ADDR $0$memwr$\memory$libresoc.v:138465$5603_ADDR[4:0]$5605 + update $memwr$\memory$libresoc.v:138465$5603_DATA $0$memwr$\memory$libresoc.v:138465$5603_DATA[63:0]$5606 + update $memwr$\memory$libresoc.v:138465$5603_EN $0$memwr$\memory$libresoc.v:138465$5603_EN[63:0]$5607 + attribute \src "libresoc.v:138465.22-138465.60" + memwr \memory $1$memwr$\memory$libresoc.v:138465$5603_ADDR[4:0]$5608 $1$memwr$\memory$libresoc.v:138465$5603_DATA[63:0]$5609 $1$memwr$\memory$libresoc.v:138465$5603_EN[63:0]$5610 0' + end + attribute \src "libresoc.v:138472.3-138473.43" + process $proc$libresoc.v:138472$5616 + assign { } { } + assign $0\ren_delay$13[0:0]$5617 \ren_delay$13$next + sync posedge \coresync_clk + update \ren_delay$13 $0\ren_delay$13[0:0]$5617 end - attribute \src "libresoc.v:137466.3-137474.6" - process $proc$libresoc.v:137466$5618 + attribute \src "libresoc.v:138474.3-138475.43" + process $proc$libresoc.v:138474$5618 assign { } { } + assign $0\ren_delay$12[0:0]$5619 \ren_delay$12$next + sync posedge \coresync_clk + update \ren_delay$12 $0\ren_delay$12[0:0]$5619 + end + attribute \src "libresoc.v:138476.3-138477.43" + process $proc$libresoc.v:138476$5620 + assign { } { } + assign $0\ren_delay$11[0:0]$5621 \ren_delay$11$next + sync posedge \coresync_clk + update \ren_delay$11 $0\ren_delay$11[0:0]$5621 + end + attribute \src "libresoc.v:138478.3-138479.43" + process $proc$libresoc.v:138478$5622 + assign { } { } + assign $0\ren_delay$10[0:0]$5623 \ren_delay$10$next + sync posedge \coresync_clk + update \ren_delay$10 $0\ren_delay$10[0:0]$5623 + end + attribute \src "libresoc.v:138480.3-138481.35" + process $proc$libresoc.v:138480$5624 assign { } { } - assign $0\ren_delay$next[0:0]$5619 $1\ren_delay$next[0:0]$5620 - attribute \src "libresoc.v:137467.5-137467.29" + assign $0\ren_delay[0:0] \ren_delay$next + sync posedge \coresync_clk + update \ren_delay $0\ren_delay[0:0] + end + attribute \src "libresoc.v:138482.3-138490.6" + process $proc$libresoc.v:138482$5625 + assign { } { } + assign { } { } + assign $0\ren_delay$next[0:0]$5626 $1\ren_delay$next[0:0]$5627 + attribute \src "libresoc.v:138483.5-138483.29" switch \initial - attribute \src "libresoc.v:137467.9-137467.17" + attribute \src "libresoc.v:138483.9-138483.17" case 1'1 case end @@ -217277,21 +218063,21 @@ module \int attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[0:0]$5620 1'0 + assign $1\ren_delay$next[0:0]$5627 1'0 case - assign $1\ren_delay$next[0:0]$5620 \src1__ren + assign $1\ren_delay$next[0:0]$5627 \src1__ren end sync always - update \ren_delay$next $0\ren_delay$next[0:0]$5619 + update \ren_delay$next $0\ren_delay$next[0:0]$5626 end - attribute \src "libresoc.v:137475.3-137483.6" - process $proc$libresoc.v:137475$5621 + attribute \src "libresoc.v:138491.3-138499.6" + process $proc$libresoc.v:138491$5628 assign { } { } assign { } { } - assign $0\ren_delay$12$next[0:0]$5622 $1\ren_delay$12$next[0:0]$5623 - attribute \src "libresoc.v:137476.5-137476.29" + assign $0\ren_delay$12$next[0:0]$5629 $1\ren_delay$12$next[0:0]$5630 + attribute \src "libresoc.v:138492.5-138492.29" switch \initial - attribute \src "libresoc.v:137476.9-137476.17" + attribute \src "libresoc.v:138492.9-138492.17" case 1'1 case end @@ -217300,21 +218086,21 @@ module \int attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$12$next[0:0]$5623 1'0 + assign $1\ren_delay$12$next[0:0]$5630 1'0 case - assign $1\ren_delay$12$next[0:0]$5623 \pred__ren + assign $1\ren_delay$12$next[0:0]$5630 \pred__ren end sync always - update \ren_delay$12$next $0\ren_delay$12$next[0:0]$5622 + update \ren_delay$12$next $0\ren_delay$12$next[0:0]$5629 end - attribute \src "libresoc.v:137484.3-137493.6" - process $proc$libresoc.v:137484$5624 + attribute \src "libresoc.v:138500.3-138509.6" + process $proc$libresoc.v:138500$5631 assign { } { } assign { } { } assign $0\pred__data_o[63:0] $1\pred__data_o[63:0] - attribute \src "libresoc.v:137485.5-137485.29" + attribute \src "libresoc.v:138501.5-138501.29" switch \initial - attribute \src "libresoc.v:137485.9-137485.17" + attribute \src "libresoc.v:138501.9-138501.17" case 1'1 case end @@ -217330,14 +218116,14 @@ module \int sync always update \pred__data_o $0\pred__data_o[63:0] end - attribute \src "libresoc.v:137494.3-137502.6" - process $proc$libresoc.v:137494$5625 + attribute \src "libresoc.v:138510.3-138518.6" + process $proc$libresoc.v:138510$5632 assign { } { } assign { } { } - assign $0\ren_delay$13$next[0:0]$5626 $1\ren_delay$13$next[0:0]$5627 - attribute \src "libresoc.v:137495.5-137495.29" + assign $0\ren_delay$13$next[0:0]$5633 $1\ren_delay$13$next[0:0]$5634 + attribute \src "libresoc.v:138511.5-138511.29" switch \initial - attribute \src "libresoc.v:137495.9-137495.17" + attribute \src "libresoc.v:138511.9-138511.17" case 1'1 case end @@ -217346,21 +218132,21 @@ module \int attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$13$next[0:0]$5627 1'0 + assign $1\ren_delay$13$next[0:0]$5634 1'0 case - assign $1\ren_delay$13$next[0:0]$5627 \dmi__ren + assign $1\ren_delay$13$next[0:0]$5634 \dmi__ren end sync always - update \ren_delay$13$next $0\ren_delay$13$next[0:0]$5626 + update \ren_delay$13$next $0\ren_delay$13$next[0:0]$5633 end - attribute \src "libresoc.v:137503.3-137512.6" - process $proc$libresoc.v:137503$5628 + attribute \src "libresoc.v:138519.3-138528.6" + process $proc$libresoc.v:138519$5635 assign { } { } assign { } { } assign $0\dmi__data_o[63:0] $1\dmi__data_o[63:0] - attribute \src "libresoc.v:137504.5-137504.29" + attribute \src "libresoc.v:138520.5-138520.29" switch \initial - attribute \src "libresoc.v:137504.9-137504.17" + attribute \src "libresoc.v:138520.9-138520.17" case 1'1 case end @@ -217376,14 +218162,14 @@ module \int sync always update \dmi__data_o $0\dmi__data_o[63:0] end - attribute \src "libresoc.v:137513.3-137522.6" - process $proc$libresoc.v:137513$5629 + attribute \src "libresoc.v:138529.3-138538.6" + process $proc$libresoc.v:138529$5636 assign { } { } assign { } { } assign $0\src1__data_o[63:0] $1\src1__data_o[63:0] - attribute \src "libresoc.v:137514.5-137514.29" + attribute \src "libresoc.v:138530.5-138530.29" switch \initial - attribute \src "libresoc.v:137514.9-137514.17" + attribute \src "libresoc.v:138530.9-138530.17" case 1'1 case end @@ -217399,14 +218185,14 @@ module \int sync always update \src1__data_o $0\src1__data_o[63:0] end - attribute \src "libresoc.v:137523.3-137531.6" - process $proc$libresoc.v:137523$5630 + attribute \src "libresoc.v:138539.3-138547.6" + process $proc$libresoc.v:138539$5637 assign { } { } assign { } { } - assign $0\ren_delay$10$next[0:0]$5631 $1\ren_delay$10$next[0:0]$5632 - attribute \src "libresoc.v:137524.5-137524.29" + assign $0\ren_delay$10$next[0:0]$5638 $1\ren_delay$10$next[0:0]$5639 + attribute \src "libresoc.v:138540.5-138540.29" switch \initial - attribute \src "libresoc.v:137524.9-137524.17" + attribute \src "libresoc.v:138540.9-138540.17" case 1'1 case end @@ -217415,21 +218201,21 @@ module \int attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$10$next[0:0]$5632 1'0 + assign $1\ren_delay$10$next[0:0]$5639 1'0 case - assign $1\ren_delay$10$next[0:0]$5632 \src2__ren + assign $1\ren_delay$10$next[0:0]$5639 \src2__ren end sync always - update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5631 + update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5638 end - attribute \src "libresoc.v:137532.3-137541.6" - process $proc$libresoc.v:137532$5633 + attribute \src "libresoc.v:138548.3-138557.6" + process $proc$libresoc.v:138548$5640 assign { } { } assign { } { } assign $0\src2__data_o[63:0] $1\src2__data_o[63:0] - attribute \src "libresoc.v:137533.5-137533.29" + attribute \src "libresoc.v:138549.5-138549.29" switch \initial - attribute \src "libresoc.v:137533.9-137533.17" + attribute \src "libresoc.v:138549.9-138549.17" case 1'1 case end @@ -217445,14 +218231,14 @@ module \int sync always update \src2__data_o $0\src2__data_o[63:0] end - attribute \src "libresoc.v:137542.3-137550.6" - process $proc$libresoc.v:137542$5634 + attribute \src "libresoc.v:138558.3-138566.6" + process $proc$libresoc.v:138558$5641 assign { } { } assign { } { } - assign $0\ren_delay$11$next[0:0]$5635 $1\ren_delay$11$next[0:0]$5636 - attribute \src "libresoc.v:137543.5-137543.29" + assign $0\ren_delay$11$next[0:0]$5642 $1\ren_delay$11$next[0:0]$5643 + attribute \src "libresoc.v:138559.5-138559.29" switch \initial - attribute \src "libresoc.v:137543.9-137543.17" + attribute \src "libresoc.v:138559.9-138559.17" case 1'1 case end @@ -217461,21 +218247,21 @@ module \int attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$11$next[0:0]$5636 1'0 + assign $1\ren_delay$11$next[0:0]$5643 1'0 case - assign $1\ren_delay$11$next[0:0]$5636 \src3__ren + assign $1\ren_delay$11$next[0:0]$5643 \src3__ren end sync always - update \ren_delay$11$next $0\ren_delay$11$next[0:0]$5635 + update \ren_delay$11$next $0\ren_delay$11$next[0:0]$5642 end - attribute \src "libresoc.v:137551.3-137560.6" - process $proc$libresoc.v:137551$5637 + attribute \src "libresoc.v:138567.3-138576.6" + process $proc$libresoc.v:138567$5644 assign { } { } assign { } { } assign $0\src3__data_o[63:0] $1\src3__data_o[63:0] - attribute \src "libresoc.v:137552.5-137552.29" + attribute \src "libresoc.v:138568.5-138568.29" switch \initial - attribute \src "libresoc.v:137552.9-137552.17" + attribute \src "libresoc.v:138568.9-138568.17" case 1'1 case end @@ -217491,11 +218277,11 @@ module \int sync always update \src3__data_o $0\src3__data_o[63:0] end - connect \memory_r_data $memrd$\memory$libresoc.v:137461$5613_DATA - connect \memory_r_data$3 $memrd$\memory$libresoc.v:137462$5614_DATA - connect \memory_r_data$5 $memrd$\memory$libresoc.v:137463$5615_DATA - connect \memory_r_data$7 $memrd$\memory$libresoc.v:137464$5616_DATA - connect \memory_r_data$9 $memrd$\memory$libresoc.v:137465$5617_DATA + connect \memory_r_data $memrd$\memory$libresoc.v:138467$5611_DATA + connect \memory_r_data$3 $memrd$\memory$libresoc.v:138468$5612_DATA + connect \memory_r_data$5 $memrd$\memory$libresoc.v:138469$5613_DATA + connect \memory_r_data$7 $memrd$\memory$libresoc.v:138470$5614_DATA + connect \memory_r_data$9 $memrd$\memory$libresoc.v:138471$5615_DATA connect \pred__addr 5'00000 connect \pred__ren 1'0 connect \memory_w_data \dest1__data_i @@ -217507,921 +218293,877 @@ module \int connect \memory_r_addr$2 \src2__addr connect \memory_r_addr \src1__addr end -attribute \src "libresoc.v:137575.1-140281.10" +attribute \src "libresoc.v:138591.1-141161.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.jtag" attribute \generator "nMigen" module \jtag - attribute \src "libresoc.v:139713.3-139739.6" + attribute \src "libresoc.v:140575.3-140601.6" wire $0\TAP_bus__tdo[0:0] - attribute \src "libresoc.v:139361.3-139376.6" + attribute \src "libresoc.v:140223.3-140238.6" wire $0\TAP_tdo[0:0] - attribute \src "libresoc.v:139874.3-139906.6" - wire width 4 $0\dmi0__addr_i$next[3:0]$6091 - attribute \src "libresoc.v:139264.3-139265.41" + attribute \src "libresoc.v:140756.3-140800.6" + wire width 4 $0\dmi0__addr_i$next[3:0]$6075 + attribute \src "libresoc.v:140126.3-140127.41" wire width 4 $0\dmi0__addr_i[3:0] - attribute \src "libresoc.v:139960.3-139986.6" - wire width 64 $0\dmi0__din$next[63:0]$6104 - attribute \src "libresoc.v:139260.3-139261.35" + attribute \src "libresoc.v:140854.3-140880.6" + wire width 64 $0\dmi0__din$next[63:0]$6088 + attribute \src "libresoc.v:140122.3-140123.35" wire width 64 $0\dmi0__din[63:0] - attribute \src "libresoc.v:139563.3-139579.6" - wire $0\dmi0_addrsr__oe$next[0:0]$6028 - attribute \src "libresoc.v:139292.3-139293.47" + attribute \src "libresoc.v:140425.3-140441.6" + wire $0\dmi0_addrsr__oe$next[0:0]$6012 + attribute \src "libresoc.v:140154.3-140155.47" wire $0\dmi0_addrsr__oe[0:0] - attribute \src "libresoc.v:139580.3-139600.6" - wire width 8 $0\dmi0_addrsr_reg$next[7:0]$6032 - attribute \src "libresoc.v:139290.3-139291.47" + attribute \src "libresoc.v:140442.3-140462.6" + wire width 8 $0\dmi0_addrsr_reg$next[7:0]$6016 + attribute \src "libresoc.v:140152.3-140153.47" wire width 8 $0\dmi0_addrsr_reg[7:0] - attribute \src "libresoc.v:139545.3-139553.6" - wire $0\dmi0_addrsr_update_core$next[0:0]$6022 - attribute \src "libresoc.v:139296.3-139297.63" + attribute \src "libresoc.v:140407.3-140415.6" + wire $0\dmi0_addrsr_update_core$next[0:0]$6006 + attribute \src "libresoc.v:140158.3-140159.63" wire $0\dmi0_addrsr_update_core[0:0] - attribute \src "libresoc.v:139554.3-139562.6" - wire $0\dmi0_addrsr_update_core_prev$next[0:0]$6025 - attribute \src "libresoc.v:139294.3-139295.73" + attribute \src "libresoc.v:140416.3-140424.6" + wire $0\dmi0_addrsr_update_core_prev$next[0:0]$6009 + attribute \src "libresoc.v:140156.3-140157.73" wire $0\dmi0_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:139987.3-140007.6" - wire width 64 $0\dmi0_datasr__i$next[63:0]$6109 - attribute \src "libresoc.v:139258.3-139259.45" + attribute \src "libresoc.v:140881.3-140909.6" + wire width 64 $0\dmi0_datasr__i$next[63:0]$6093 + attribute \src "libresoc.v:140120.3-140121.45" wire width 64 $0\dmi0_datasr__i[63:0] - attribute \src "libresoc.v:139619.3-139635.6" - wire width 2 $0\dmi0_datasr__oe$next[1:0]$6043 - attribute \src "libresoc.v:139284.3-139285.47" + attribute \src "libresoc.v:140481.3-140497.6" + wire width 2 $0\dmi0_datasr__oe$next[1:0]$6027 + attribute \src "libresoc.v:140146.3-140147.47" wire width 2 $0\dmi0_datasr__oe[1:0] - attribute \src "libresoc.v:139636.3-139656.6" - wire width 64 $0\dmi0_datasr_reg$next[63:0]$6047 - attribute \src "libresoc.v:139282.3-139283.47" + attribute \src "libresoc.v:140498.3-140518.6" + wire width 64 $0\dmi0_datasr_reg$next[63:0]$6031 + attribute \src "libresoc.v:140144.3-140145.47" wire width 64 $0\dmi0_datasr_reg[63:0] - attribute \src "libresoc.v:139601.3-139609.6" - wire $0\dmi0_datasr_update_core$next[0:0]$6037 - attribute \src "libresoc.v:139288.3-139289.63" + attribute \src "libresoc.v:140463.3-140471.6" + wire $0\dmi0_datasr_update_core$next[0:0]$6021 + attribute \src "libresoc.v:140150.3-140151.63" wire $0\dmi0_datasr_update_core[0:0] - attribute \src "libresoc.v:139610.3-139618.6" - wire $0\dmi0_datasr_update_core_prev$next[0:0]$6040 - attribute \src "libresoc.v:139286.3-139287.73" + attribute \src "libresoc.v:140472.3-140480.6" + wire $0\dmi0_datasr_update_core_prev$next[0:0]$6024 + attribute \src "libresoc.v:140148.3-140149.73" wire $0\dmi0_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:139907.3-139959.6" - wire width 3 $0\fsm_state$499$next[2:0]$6097 - attribute \src "libresoc.v:139262.3-139263.45" - wire width 3 $0\fsm_state$499[2:0]$5943 - attribute \src "libresoc.v:138217.13-138217.35" - wire width 3 $0\fsm_state$499[2:0]$6146 - attribute \src "libresoc.v:139773.3-139825.6" - wire width 3 $0\fsm_state$next[2:0]$6074 - attribute \src "libresoc.v:139270.3-139271.35" + attribute \src "libresoc.v:140801.3-140853.6" + wire width 3 $0\fsm_state$455$next[2:0]$6081 + attribute \src "libresoc.v:140124.3-140125.45" + wire width 3 $0\fsm_state$455[2:0]$5927 + attribute \src "libresoc.v:139189.13-139189.35" + wire width 3 $0\fsm_state$455[2:0]$6130 + attribute \src "libresoc.v:140647.3-140699.6" + wire width 3 $0\fsm_state$next[2:0]$6058 + attribute \src "libresoc.v:140132.3-140133.35" wire width 3 $0\fsm_state[2:0] - attribute \src "libresoc.v:137576.7-137576.20" + attribute \src "libresoc.v:138592.7-138592.20" wire $0\initial[0:0] - attribute \src "libresoc.v:140057.3-140077.6" - wire width 152 $0\io_bd$next[151:0]$6129 - attribute \src "libresoc.v:139322.3-139323.27" - wire width 152 $0\io_bd[151:0] - attribute \src "libresoc.v:140039.3-140056.6" - wire width 152 $0\io_sr$next[151:0]$6125 - attribute \src "libresoc.v:139324.3-139325.27" - wire width 152 $0\io_sr[151:0] - attribute \src "libresoc.v:139740.3-139772.6" - wire width 29 $0\jtag_wb__adr$next[28:0]$6068 - attribute \src "libresoc.v:139272.3-139273.41" + attribute \src "libresoc.v:140959.3-140979.6" + wire width 130 $0\io_bd$next[129:0]$6113 + attribute \src "libresoc.v:140184.3-140185.27" + wire width 130 $0\io_bd[129:0] + attribute \src "libresoc.v:140941.3-140958.6" + wire width 130 $0\io_sr$next[129:0]$6109 + attribute \src "libresoc.v:140186.3-140187.27" + wire width 130 $0\io_sr[129:0] + attribute \src "libresoc.v:140602.3-140646.6" + wire width 29 $0\jtag_wb__adr$next[28:0]$6052 + attribute \src "libresoc.v:140134.3-140135.41" wire width 29 $0\jtag_wb__adr[28:0] - attribute \src "libresoc.v:139826.3-139852.6" - wire width 64 $0\jtag_wb__dat_w$next[63:0]$6081 - attribute \src "libresoc.v:139268.3-139269.45" + attribute \src "libresoc.v:140700.3-140726.6" + wire width 64 $0\jtag_wb__dat_w$next[63:0]$6065 + attribute \src "libresoc.v:140130.3-140131.45" wire width 64 $0\jtag_wb__dat_w[63:0] - attribute \src "libresoc.v:139451.3-139467.6" - wire $0\jtag_wb_addrsr__oe$next[0:0]$5998 - attribute \src "libresoc.v:139308.3-139309.53" + attribute \src "libresoc.v:140313.3-140329.6" + wire $0\jtag_wb_addrsr__oe$next[0:0]$5982 + attribute \src "libresoc.v:140170.3-140171.53" wire $0\jtag_wb_addrsr__oe[0:0] - attribute \src "libresoc.v:139468.3-139488.6" - wire width 29 $0\jtag_wb_addrsr_reg$next[28:0]$6002 - attribute \src "libresoc.v:139306.3-139307.53" + attribute \src "libresoc.v:140330.3-140350.6" + wire width 29 $0\jtag_wb_addrsr_reg$next[28:0]$5986 + attribute \src "libresoc.v:140168.3-140169.53" wire width 29 $0\jtag_wb_addrsr_reg[28:0] - attribute \src "libresoc.v:139433.3-139441.6" - wire $0\jtag_wb_addrsr_update_core$next[0:0]$5992 - attribute \src "libresoc.v:139312.3-139313.69" + attribute \src "libresoc.v:140295.3-140303.6" + wire $0\jtag_wb_addrsr_update_core$next[0:0]$5976 + attribute \src "libresoc.v:140174.3-140175.69" wire $0\jtag_wb_addrsr_update_core[0:0] - attribute \src "libresoc.v:139442.3-139450.6" - wire $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5995 - attribute \src "libresoc.v:139310.3-139311.79" + attribute \src "libresoc.v:140304.3-140312.6" + wire $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5979 + attribute \src "libresoc.v:140172.3-140173.79" wire $0\jtag_wb_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:139853.3-139873.6" - wire width 64 $0\jtag_wb_datasr__i$next[63:0]$6086 - attribute \src "libresoc.v:139266.3-139267.51" + attribute \src "libresoc.v:140727.3-140755.6" + wire width 64 $0\jtag_wb_datasr__i$next[63:0]$6070 + attribute \src "libresoc.v:140128.3-140129.51" wire width 64 $0\jtag_wb_datasr__i[63:0] - attribute \src "libresoc.v:139507.3-139523.6" - wire width 2 $0\jtag_wb_datasr__oe$next[1:0]$6013 - attribute \src "libresoc.v:139300.3-139301.53" + attribute \src "libresoc.v:140369.3-140385.6" + wire width 2 $0\jtag_wb_datasr__oe$next[1:0]$5997 + attribute \src "libresoc.v:140162.3-140163.53" wire width 2 $0\jtag_wb_datasr__oe[1:0] - attribute \src "libresoc.v:139524.3-139544.6" - wire width 64 $0\jtag_wb_datasr_reg$next[63:0]$6017 - attribute \src "libresoc.v:139298.3-139299.53" + attribute \src "libresoc.v:140386.3-140406.6" + wire width 64 $0\jtag_wb_datasr_reg$next[63:0]$6001 + attribute \src "libresoc.v:140160.3-140161.53" wire width 64 $0\jtag_wb_datasr_reg[63:0] - attribute \src "libresoc.v:139489.3-139497.6" - wire $0\jtag_wb_datasr_update_core$next[0:0]$6007 - attribute \src "libresoc.v:139304.3-139305.69" + attribute \src "libresoc.v:140351.3-140359.6" + wire $0\jtag_wb_datasr_update_core$next[0:0]$5991 + attribute \src "libresoc.v:140166.3-140167.69" wire $0\jtag_wb_datasr_update_core[0:0] - attribute \src "libresoc.v:139498.3-139506.6" - wire $0\jtag_wb_datasr_update_core_prev$next[0:0]$6010 - attribute \src "libresoc.v:139302.3-139303.79" + attribute \src "libresoc.v:140360.3-140368.6" + wire $0\jtag_wb_datasr_update_core_prev$next[0:0]$5994 + attribute \src "libresoc.v:140164.3-140165.79" wire $0\jtag_wb_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:139395.3-139411.6" - wire $0\sr0__oe$next[0:0]$5983 - attribute \src "libresoc.v:139316.3-139317.31" + attribute \src "libresoc.v:140257.3-140273.6" + wire $0\sr0__oe$next[0:0]$5967 + attribute \src "libresoc.v:140178.3-140179.31" wire $0\sr0__oe[0:0] - attribute \src "libresoc.v:139412.3-139432.6" - wire width 3 $0\sr0_reg$next[2:0]$5987 - attribute \src "libresoc.v:139314.3-139315.31" + attribute \src "libresoc.v:140274.3-140294.6" + wire width 3 $0\sr0_reg$next[2:0]$5971 + attribute \src "libresoc.v:140176.3-140177.31" wire width 3 $0\sr0_reg[2:0] - attribute \src "libresoc.v:139377.3-139385.6" - wire $0\sr0_update_core$next[0:0]$5977 - attribute \src "libresoc.v:139320.3-139321.47" + attribute \src "libresoc.v:140239.3-140247.6" + wire $0\sr0_update_core$next[0:0]$5961 + attribute \src "libresoc.v:140182.3-140183.47" wire $0\sr0_update_core[0:0] - attribute \src "libresoc.v:139386.3-139394.6" - wire $0\sr0_update_core_prev$next[0:0]$5980 - attribute \src "libresoc.v:139318.3-139319.57" + attribute \src "libresoc.v:140248.3-140256.6" + wire $0\sr0_update_core_prev$next[0:0]$5964 + attribute \src "libresoc.v:140180.3-140181.57" wire $0\sr0_update_core_prev[0:0] - attribute \src "libresoc.v:140029.3-140038.6" + attribute \src "libresoc.v:140931.3-140940.6" wire width 3 $0\sr5__i[2:0] - attribute \src "libresoc.v:139675.3-139691.6" - wire $0\sr5__oe$next[0:0]$6058 - attribute \src "libresoc.v:139276.3-139277.31" + attribute \src "libresoc.v:140537.3-140553.6" + wire $0\sr5__oe$next[0:0]$6042 + attribute \src "libresoc.v:140138.3-140139.31" wire $0\sr5__oe[0:0] - attribute \src "libresoc.v:139692.3-139712.6" - wire width 3 $0\sr5_reg$next[2:0]$6062 - attribute \src "libresoc.v:139274.3-139275.31" + attribute \src "libresoc.v:140554.3-140574.6" + wire width 3 $0\sr5_reg$next[2:0]$6046 + attribute \src "libresoc.v:140136.3-140137.31" wire width 3 $0\sr5_reg[2:0] - attribute \src "libresoc.v:139657.3-139665.6" - wire $0\sr5_update_core$next[0:0]$6052 - attribute \src "libresoc.v:139280.3-139281.47" + attribute \src "libresoc.v:140519.3-140527.6" + wire $0\sr5_update_core$next[0:0]$6036 + attribute \src "libresoc.v:140142.3-140143.47" wire $0\sr5_update_core[0:0] - attribute \src "libresoc.v:139666.3-139674.6" - wire $0\sr5_update_core_prev$next[0:0]$6055 - attribute \src "libresoc.v:139278.3-139279.57" + attribute \src "libresoc.v:140528.3-140536.6" + wire $0\sr5_update_core_prev$next[0:0]$6039 + attribute \src "libresoc.v:140140.3-140141.57" wire $0\sr5_update_core_prev[0:0] - attribute \src "libresoc.v:140008.3-140028.6" - wire $0\wb_dcache_en$next[0:0]$6114 - attribute \src "libresoc.v:139254.3-139255.41" + attribute \src "libresoc.v:140910.3-140930.6" + wire $0\wb_dcache_en$next[0:0]$6098 + attribute \src "libresoc.v:140116.3-140117.41" wire $0\wb_dcache_en[0:0] - attribute \src "libresoc.v:140008.3-140028.6" - wire $0\wb_icache_en$next[0:0]$6115 - attribute \src "libresoc.v:139252.3-139253.41" + attribute \src "libresoc.v:140910.3-140930.6" + wire $0\wb_icache_en$next[0:0]$6099 + attribute \src "libresoc.v:140114.3-140115.41" wire $0\wb_icache_en[0:0] - attribute \src "libresoc.v:140008.3-140028.6" - wire $0\wb_sram_en$next[0:0]$6116 - attribute \src "libresoc.v:139256.3-139257.37" + attribute \src "libresoc.v:140910.3-140930.6" + wire $0\wb_sram_en$next[0:0]$6100 + attribute \src "libresoc.v:140118.3-140119.37" wire $0\wb_sram_en[0:0] - attribute \src "libresoc.v:139713.3-139739.6" + attribute \src "libresoc.v:140575.3-140601.6" wire $1\TAP_bus__tdo[0:0] - attribute \src "libresoc.v:139361.3-139376.6" + attribute \src "libresoc.v:140223.3-140238.6" wire $1\TAP_tdo[0:0] - attribute \src "libresoc.v:139874.3-139906.6" - wire width 4 $1\dmi0__addr_i$next[3:0]$6092 - attribute \src "libresoc.v:138130.13-138130.32" + attribute \src "libresoc.v:140756.3-140800.6" + wire width 4 $1\dmi0__addr_i$next[3:0]$6076 + attribute \src "libresoc.v:139102.13-139102.32" wire width 4 $1\dmi0__addr_i[3:0] - attribute \src "libresoc.v:139960.3-139986.6" - wire width 64 $1\dmi0__din$next[63:0]$6105 - attribute \src "libresoc.v:138135.14-138135.46" + attribute \src "libresoc.v:140854.3-140880.6" + wire width 64 $1\dmi0__din$next[63:0]$6089 + attribute \src "libresoc.v:139107.14-139107.46" wire width 64 $1\dmi0__din[63:0] - attribute \src "libresoc.v:139563.3-139579.6" - wire $1\dmi0_addrsr__oe$next[0:0]$6029 - attribute \src "libresoc.v:138149.7-138149.29" + attribute \src "libresoc.v:140425.3-140441.6" + wire $1\dmi0_addrsr__oe$next[0:0]$6013 + attribute \src "libresoc.v:139121.7-139121.29" wire $1\dmi0_addrsr__oe[0:0] - attribute \src "libresoc.v:139580.3-139600.6" - wire width 8 $1\dmi0_addrsr_reg$next[7:0]$6033 - attribute \src "libresoc.v:138157.13-138157.36" + attribute \src "libresoc.v:140442.3-140462.6" + wire width 8 $1\dmi0_addrsr_reg$next[7:0]$6017 + attribute \src "libresoc.v:139129.13-139129.36" wire width 8 $1\dmi0_addrsr_reg[7:0] - attribute \src "libresoc.v:139545.3-139553.6" - wire $1\dmi0_addrsr_update_core$next[0:0]$6023 - attribute \src "libresoc.v:138165.7-138165.37" + attribute \src "libresoc.v:140407.3-140415.6" + wire $1\dmi0_addrsr_update_core$next[0:0]$6007 + attribute \src "libresoc.v:139137.7-139137.37" wire $1\dmi0_addrsr_update_core[0:0] - attribute \src "libresoc.v:139554.3-139562.6" - wire $1\dmi0_addrsr_update_core_prev$next[0:0]$6026 - attribute \src "libresoc.v:138169.7-138169.42" + attribute \src "libresoc.v:140416.3-140424.6" + wire $1\dmi0_addrsr_update_core_prev$next[0:0]$6010 + attribute \src "libresoc.v:139141.7-139141.42" wire $1\dmi0_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:139987.3-140007.6" - wire width 64 $1\dmi0_datasr__i$next[63:0]$6110 - attribute \src "libresoc.v:138173.14-138173.51" + attribute \src "libresoc.v:140881.3-140909.6" + wire width 64 $1\dmi0_datasr__i$next[63:0]$6094 + attribute \src "libresoc.v:139145.14-139145.51" wire width 64 $1\dmi0_datasr__i[63:0] - attribute \src "libresoc.v:139619.3-139635.6" - wire width 2 $1\dmi0_datasr__oe$next[1:0]$6044 - attribute \src "libresoc.v:138179.13-138179.35" + attribute \src "libresoc.v:140481.3-140497.6" + wire width 2 $1\dmi0_datasr__oe$next[1:0]$6028 + attribute \src "libresoc.v:139151.13-139151.35" wire width 2 $1\dmi0_datasr__oe[1:0] - attribute \src "libresoc.v:139636.3-139656.6" - wire width 64 $1\dmi0_datasr_reg$next[63:0]$6048 - attribute \src "libresoc.v:138187.14-138187.52" + attribute \src "libresoc.v:140498.3-140518.6" + wire width 64 $1\dmi0_datasr_reg$next[63:0]$6032 + attribute \src "libresoc.v:139159.14-139159.52" wire width 64 $1\dmi0_datasr_reg[63:0] - attribute \src "libresoc.v:139601.3-139609.6" - wire $1\dmi0_datasr_update_core$next[0:0]$6038 - attribute \src "libresoc.v:138195.7-138195.37" + attribute \src "libresoc.v:140463.3-140471.6" + wire $1\dmi0_datasr_update_core$next[0:0]$6022 + attribute \src "libresoc.v:139167.7-139167.37" wire $1\dmi0_datasr_update_core[0:0] - attribute \src "libresoc.v:139610.3-139618.6" - wire $1\dmi0_datasr_update_core_prev$next[0:0]$6041 - attribute \src "libresoc.v:138199.7-138199.42" + attribute \src "libresoc.v:140472.3-140480.6" + wire $1\dmi0_datasr_update_core_prev$next[0:0]$6025 + attribute \src "libresoc.v:139171.7-139171.42" wire $1\dmi0_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:139907.3-139959.6" - wire width 3 $1\fsm_state$499$next[2:0]$6098 - attribute \src "libresoc.v:139773.3-139825.6" - wire width 3 $1\fsm_state$next[2:0]$6075 - attribute \src "libresoc.v:138215.13-138215.29" + attribute \src "libresoc.v:140801.3-140853.6" + wire width 3 $1\fsm_state$455$next[2:0]$6082 + attribute \src "libresoc.v:140647.3-140699.6" + wire width 3 $1\fsm_state$next[2:0]$6059 + attribute \src "libresoc.v:139187.13-139187.29" wire width 3 $1\fsm_state[2:0] - attribute \src "libresoc.v:140057.3-140077.6" - wire width 152 $1\io_bd$next[151:0]$6130 - attribute \src "libresoc.v:138415.15-138415.66" - wire width 152 $1\io_bd[151:0] - attribute \src "libresoc.v:140039.3-140056.6" - wire width 152 $1\io_sr$next[151:0]$6126 - attribute \src "libresoc.v:138427.15-138427.66" - wire width 152 $1\io_sr[151:0] - attribute \src "libresoc.v:139740.3-139772.6" - wire width 29 $1\jtag_wb__adr$next[28:0]$6069 - attribute \src "libresoc.v:138436.14-138436.41" + attribute \src "libresoc.v:140959.3-140979.6" + wire width 130 $1\io_bd$next[129:0]$6114 + attribute \src "libresoc.v:139387.15-139387.61" + wire width 130 $1\io_bd[129:0] + attribute \src "libresoc.v:140941.3-140958.6" + wire width 130 $1\io_sr$next[129:0]$6110 + attribute \src "libresoc.v:139399.15-139399.61" + wire width 130 $1\io_sr[129:0] + attribute \src "libresoc.v:140602.3-140646.6" + wire width 29 $1\jtag_wb__adr$next[28:0]$6053 + attribute \src "libresoc.v:139408.14-139408.41" wire width 29 $1\jtag_wb__adr[28:0] - attribute \src "libresoc.v:139826.3-139852.6" - wire width 64 $1\jtag_wb__dat_w$next[63:0]$6082 - attribute \src "libresoc.v:138445.14-138445.51" + attribute \src "libresoc.v:140700.3-140726.6" + wire width 64 $1\jtag_wb__dat_w$next[63:0]$6066 + attribute \src "libresoc.v:139417.14-139417.51" wire width 64 $1\jtag_wb__dat_w[63:0] - attribute \src "libresoc.v:139451.3-139467.6" - wire $1\jtag_wb_addrsr__oe$next[0:0]$5999 - attribute \src "libresoc.v:138459.7-138459.32" + attribute \src "libresoc.v:140313.3-140329.6" + wire $1\jtag_wb_addrsr__oe$next[0:0]$5983 + attribute \src "libresoc.v:139431.7-139431.32" wire $1\jtag_wb_addrsr__oe[0:0] - attribute \src "libresoc.v:139468.3-139488.6" - wire width 29 $1\jtag_wb_addrsr_reg$next[28:0]$6003 - attribute \src "libresoc.v:138467.14-138467.47" + attribute \src "libresoc.v:140330.3-140350.6" + wire width 29 $1\jtag_wb_addrsr_reg$next[28:0]$5987 + attribute \src "libresoc.v:139439.14-139439.47" wire width 29 $1\jtag_wb_addrsr_reg[28:0] - attribute \src "libresoc.v:139433.3-139441.6" - wire $1\jtag_wb_addrsr_update_core$next[0:0]$5993 - attribute \src "libresoc.v:138475.7-138475.40" + attribute \src "libresoc.v:140295.3-140303.6" + wire $1\jtag_wb_addrsr_update_core$next[0:0]$5977 + attribute \src "libresoc.v:139447.7-139447.40" wire $1\jtag_wb_addrsr_update_core[0:0] - attribute \src "libresoc.v:139442.3-139450.6" - wire $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5996 - attribute \src "libresoc.v:138479.7-138479.45" + attribute \src "libresoc.v:140304.3-140312.6" + wire $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5980 + attribute \src "libresoc.v:139451.7-139451.45" wire $1\jtag_wb_addrsr_update_core_prev[0:0] - attribute \src "libresoc.v:139853.3-139873.6" - wire width 64 $1\jtag_wb_datasr__i$next[63:0]$6087 - attribute \src "libresoc.v:138483.14-138483.54" + attribute \src "libresoc.v:140727.3-140755.6" + wire width 64 $1\jtag_wb_datasr__i$next[63:0]$6071 + attribute \src "libresoc.v:139455.14-139455.54" wire width 64 $1\jtag_wb_datasr__i[63:0] - attribute \src "libresoc.v:139507.3-139523.6" - wire width 2 $1\jtag_wb_datasr__oe$next[1:0]$6014 - attribute \src "libresoc.v:138489.13-138489.38" + attribute \src "libresoc.v:140369.3-140385.6" + wire width 2 $1\jtag_wb_datasr__oe$next[1:0]$5998 + attribute \src "libresoc.v:139461.13-139461.38" wire width 2 $1\jtag_wb_datasr__oe[1:0] - attribute \src "libresoc.v:139524.3-139544.6" - wire width 64 $1\jtag_wb_datasr_reg$next[63:0]$6018 - attribute \src "libresoc.v:138497.14-138497.55" + attribute \src "libresoc.v:140386.3-140406.6" + wire width 64 $1\jtag_wb_datasr_reg$next[63:0]$6002 + attribute \src "libresoc.v:139469.14-139469.55" wire width 64 $1\jtag_wb_datasr_reg[63:0] - attribute \src "libresoc.v:139489.3-139497.6" - wire $1\jtag_wb_datasr_update_core$next[0:0]$6008 - attribute \src "libresoc.v:138505.7-138505.40" + attribute \src "libresoc.v:140351.3-140359.6" + wire $1\jtag_wb_datasr_update_core$next[0:0]$5992 + attribute \src "libresoc.v:139477.7-139477.40" wire $1\jtag_wb_datasr_update_core[0:0] - attribute \src "libresoc.v:139498.3-139506.6" - wire $1\jtag_wb_datasr_update_core_prev$next[0:0]$6011 - attribute \src "libresoc.v:138509.7-138509.45" + attribute \src "libresoc.v:140360.3-140368.6" + wire $1\jtag_wb_datasr_update_core_prev$next[0:0]$5995 + attribute \src "libresoc.v:139481.7-139481.45" wire $1\jtag_wb_datasr_update_core_prev[0:0] - attribute \src "libresoc.v:139395.3-139411.6" - wire $1\sr0__oe$next[0:0]$5984 - attribute \src "libresoc.v:138931.7-138931.21" + attribute \src "libresoc.v:140257.3-140273.6" + wire $1\sr0__oe$next[0:0]$5968 + attribute \src "libresoc.v:139815.7-139815.21" wire $1\sr0__oe[0:0] - attribute \src "libresoc.v:139412.3-139432.6" - wire width 3 $1\sr0_reg$next[2:0]$5988 - attribute \src "libresoc.v:138939.13-138939.27" + attribute \src "libresoc.v:140274.3-140294.6" + wire width 3 $1\sr0_reg$next[2:0]$5972 + attribute \src "libresoc.v:139823.13-139823.27" wire width 3 $1\sr0_reg[2:0] - attribute \src "libresoc.v:139377.3-139385.6" - wire $1\sr0_update_core$next[0:0]$5978 - attribute \src "libresoc.v:138947.7-138947.29" + attribute \src "libresoc.v:140239.3-140247.6" + wire $1\sr0_update_core$next[0:0]$5962 + attribute \src "libresoc.v:139831.7-139831.29" wire $1\sr0_update_core[0:0] - attribute \src "libresoc.v:139386.3-139394.6" - wire $1\sr0_update_core_prev$next[0:0]$5981 - attribute \src "libresoc.v:138951.7-138951.34" + attribute \src "libresoc.v:140248.3-140256.6" + wire $1\sr0_update_core_prev$next[0:0]$5965 + attribute \src "libresoc.v:139835.7-139835.34" wire $1\sr0_update_core_prev[0:0] - attribute \src "libresoc.v:140029.3-140038.6" + attribute \src "libresoc.v:140931.3-140940.6" wire width 3 $1\sr5__i[2:0] - attribute \src "libresoc.v:139675.3-139691.6" - wire $1\sr5__oe$next[0:0]$6059 - attribute \src "libresoc.v:138961.7-138961.21" + attribute \src "libresoc.v:140537.3-140553.6" + wire $1\sr5__oe$next[0:0]$6043 + attribute \src "libresoc.v:139845.7-139845.21" wire $1\sr5__oe[0:0] - attribute \src "libresoc.v:139692.3-139712.6" - wire width 3 $1\sr5_reg$next[2:0]$6063 - attribute \src "libresoc.v:138969.13-138969.27" + attribute \src "libresoc.v:140554.3-140574.6" + wire width 3 $1\sr5_reg$next[2:0]$6047 + attribute \src "libresoc.v:139853.13-139853.27" wire width 3 $1\sr5_reg[2:0] - attribute \src "libresoc.v:139657.3-139665.6" - wire $1\sr5_update_core$next[0:0]$6053 - attribute \src "libresoc.v:138977.7-138977.29" + attribute \src "libresoc.v:140519.3-140527.6" + wire $1\sr5_update_core$next[0:0]$6037 + attribute \src "libresoc.v:139861.7-139861.29" wire $1\sr5_update_core[0:0] - attribute \src "libresoc.v:139666.3-139674.6" - wire $1\sr5_update_core_prev$next[0:0]$6056 - attribute \src "libresoc.v:138981.7-138981.34" + attribute \src "libresoc.v:140528.3-140536.6" + wire $1\sr5_update_core_prev$next[0:0]$6040 + attribute \src "libresoc.v:139865.7-139865.34" wire $1\sr5_update_core_prev[0:0] - attribute \src "libresoc.v:140008.3-140028.6" - wire $1\wb_dcache_en$next[0:0]$6117 - attribute \src "libresoc.v:138986.7-138986.26" + attribute \src "libresoc.v:140910.3-140930.6" + wire $1\wb_dcache_en$next[0:0]$6101 + attribute \src "libresoc.v:139870.7-139870.26" wire $1\wb_dcache_en[0:0] - attribute \src "libresoc.v:140008.3-140028.6" - wire $1\wb_icache_en$next[0:0]$6118 - attribute \src "libresoc.v:138991.7-138991.26" + attribute \src "libresoc.v:140910.3-140930.6" + wire $1\wb_icache_en$next[0:0]$6102 + attribute \src "libresoc.v:139875.7-139875.26" wire $1\wb_icache_en[0:0] - attribute \src "libresoc.v:140008.3-140028.6" - wire $1\wb_sram_en$next[0:0]$6119 - attribute \src "libresoc.v:138995.7-138995.24" + attribute \src "libresoc.v:140910.3-140930.6" + wire $1\wb_sram_en$next[0:0]$6103 + attribute \src "libresoc.v:139879.7-139879.24" wire $1\wb_sram_en[0:0] - attribute \src "libresoc.v:139874.3-139906.6" - wire width 4 $2\dmi0__addr_i$next[3:0]$6093 - attribute \src "libresoc.v:139960.3-139986.6" - wire width 64 $2\dmi0__din$next[63:0]$6106 - attribute \src "libresoc.v:139563.3-139579.6" - wire $2\dmi0_addrsr__oe$next[0:0]$6030 - attribute \src "libresoc.v:139580.3-139600.6" - wire width 8 $2\dmi0_addrsr_reg$next[7:0]$6034 - attribute \src "libresoc.v:139987.3-140007.6" - wire width 64 $2\dmi0_datasr__i$next[63:0]$6111 - attribute \src "libresoc.v:139619.3-139635.6" - wire width 2 $2\dmi0_datasr__oe$next[1:0]$6045 - attribute \src "libresoc.v:139636.3-139656.6" - wire width 64 $2\dmi0_datasr_reg$next[63:0]$6049 - attribute \src "libresoc.v:139907.3-139959.6" - wire width 3 $2\fsm_state$499$next[2:0]$6099 - attribute \src "libresoc.v:139773.3-139825.6" - wire width 3 $2\fsm_state$next[2:0]$6076 - attribute \src "libresoc.v:140057.3-140077.6" - wire width 152 $2\io_bd$next[151:0]$6131 - attribute \src "libresoc.v:140039.3-140056.6" - wire width 152 $2\io_sr$next[151:0]$6127 - attribute \src "libresoc.v:139740.3-139772.6" - wire width 29 $2\jtag_wb__adr$next[28:0]$6070 - attribute \src "libresoc.v:139826.3-139852.6" - wire width 64 $2\jtag_wb__dat_w$next[63:0]$6083 - attribute \src "libresoc.v:139451.3-139467.6" - wire $2\jtag_wb_addrsr__oe$next[0:0]$6000 - attribute \src "libresoc.v:139468.3-139488.6" - wire width 29 $2\jtag_wb_addrsr_reg$next[28:0]$6004 - attribute \src "libresoc.v:139853.3-139873.6" - wire width 64 $2\jtag_wb_datasr__i$next[63:0]$6088 - attribute \src "libresoc.v:139507.3-139523.6" - wire width 2 $2\jtag_wb_datasr__oe$next[1:0]$6015 - attribute \src "libresoc.v:139524.3-139544.6" - wire width 64 $2\jtag_wb_datasr_reg$next[63:0]$6019 - attribute \src "libresoc.v:139395.3-139411.6" - wire $2\sr0__oe$next[0:0]$5985 - attribute \src "libresoc.v:139412.3-139432.6" - wire width 3 $2\sr0_reg$next[2:0]$5989 - attribute \src "libresoc.v:139675.3-139691.6" - wire $2\sr5__oe$next[0:0]$6060 - attribute \src "libresoc.v:139692.3-139712.6" - wire width 3 $2\sr5_reg$next[2:0]$6064 - attribute \src "libresoc.v:140008.3-140028.6" - wire $2\wb_dcache_en$next[0:0]$6120 - attribute \src "libresoc.v:140008.3-140028.6" - wire $2\wb_icache_en$next[0:0]$6121 - attribute \src "libresoc.v:140008.3-140028.6" - wire $2\wb_sram_en$next[0:0]$6122 - attribute \src "libresoc.v:139874.3-139906.6" - wire width 4 $3\dmi0__addr_i$next[3:0]$6094 - attribute \src "libresoc.v:139960.3-139986.6" - wire width 64 $3\dmi0__din$next[63:0]$6107 - attribute \src "libresoc.v:139580.3-139600.6" - wire width 8 $3\dmi0_addrsr_reg$next[7:0]$6035 - attribute \src "libresoc.v:139987.3-140007.6" - wire width 64 $3\dmi0_datasr__i$next[63:0]$6112 - attribute \src "libresoc.v:139636.3-139656.6" - wire width 64 $3\dmi0_datasr_reg$next[63:0]$6050 - attribute \src "libresoc.v:139907.3-139959.6" - wire width 3 $3\fsm_state$499$next[2:0]$6100 - attribute \src "libresoc.v:139773.3-139825.6" - wire width 3 $3\fsm_state$next[2:0]$6077 - attribute \src "libresoc.v:139740.3-139772.6" - wire width 29 $3\jtag_wb__adr$next[28:0]$6071 - attribute \src "libresoc.v:139826.3-139852.6" - wire width 64 $3\jtag_wb__dat_w$next[63:0]$6084 - attribute \src "libresoc.v:139468.3-139488.6" - wire width 29 $3\jtag_wb_addrsr_reg$next[28:0]$6005 - attribute \src "libresoc.v:139853.3-139873.6" - wire width 64 $3\jtag_wb_datasr__i$next[63:0]$6089 - attribute \src "libresoc.v:139524.3-139544.6" - wire width 64 $3\jtag_wb_datasr_reg$next[63:0]$6020 - attribute \src "libresoc.v:139412.3-139432.6" - wire width 3 $3\sr0_reg$next[2:0]$5990 - attribute \src "libresoc.v:139692.3-139712.6" - wire width 3 $3\sr5_reg$next[2:0]$6065 - attribute \src "libresoc.v:139874.3-139906.6" - wire width 4 $4\dmi0__addr_i$next[3:0]$6095 - attribute \src "libresoc.v:139907.3-139959.6" - wire width 3 $4\fsm_state$499$next[2:0]$6101 - attribute \src "libresoc.v:139773.3-139825.6" - wire width 3 $4\fsm_state$next[2:0]$6078 - attribute \src "libresoc.v:139740.3-139772.6" - wire width 29 $4\jtag_wb__adr$next[28:0]$6072 - attribute \src "libresoc.v:139907.3-139959.6" - wire width 3 $5\fsm_state$499$next[2:0]$6102 - attribute \src "libresoc.v:139773.3-139825.6" - wire width 3 $5\fsm_state$next[2:0]$6079 - attribute \src "libresoc.v:139216.19-139216.112" - wire width 30 $add$libresoc.v:139216$5900_Y - attribute \src "libresoc.v:139217.19-139217.112" - wire width 30 $add$libresoc.v:139217$5901_Y - attribute \src "libresoc.v:139224.19-139224.112" - wire width 5 $add$libresoc.v:139224$5909_Y - attribute \src "libresoc.v:139225.19-139225.112" - wire width 5 $add$libresoc.v:139225$5910_Y - attribute \src "libresoc.v:139042.18-139042.112" - wire $and$libresoc.v:139042$5726_Y - attribute \src "libresoc.v:139109.18-139109.108" - wire $and$libresoc.v:139109$5793_Y - attribute \src "libresoc.v:139120.18-139120.110" - wire $and$libresoc.v:139120$5804_Y - attribute \src "libresoc.v:139146.19-139146.110" - wire $and$libresoc.v:139146$5830_Y - attribute \src "libresoc.v:139149.19-139149.114" - wire $and$libresoc.v:139149$5833_Y - attribute \src "libresoc.v:139151.19-139151.112" - wire $and$libresoc.v:139151$5835_Y - attribute \src "libresoc.v:139154.19-139154.113" - wire $and$libresoc.v:139154$5838_Y - attribute \src "libresoc.v:139156.19-139156.121" - wire $and$libresoc.v:139156$5840_Y - attribute \src "libresoc.v:139159.19-139159.114" - wire $and$libresoc.v:139159$5843_Y - attribute \src "libresoc.v:139161.19-139161.112" - wire $and$libresoc.v:139161$5845_Y - attribute \src "libresoc.v:139163.19-139163.113" - wire $and$libresoc.v:139163$5847_Y - attribute \src "libresoc.v:139167.19-139167.132" - wire $and$libresoc.v:139167$5851_Y - attribute \src "libresoc.v:139171.19-139171.114" - wire $and$libresoc.v:139171$5855_Y - attribute \src "libresoc.v:139173.19-139173.112" - wire $and$libresoc.v:139173$5857_Y - attribute \src "libresoc.v:139175.19-139175.113" - wire $and$libresoc.v:139175$5859_Y - attribute \src "libresoc.v:139178.19-139178.132" - wire $and$libresoc.v:139178$5862_Y - attribute \src "libresoc.v:139181.19-139181.114" - wire $and$libresoc.v:139181$5865_Y - attribute \src "libresoc.v:139183.19-139183.112" - wire $and$libresoc.v:139183$5867_Y - attribute \src "libresoc.v:139185.19-139185.113" - wire $and$libresoc.v:139185$5869_Y - attribute \src "libresoc.v:139187.18-139187.108" - wire $and$libresoc.v:139187$5871_Y - attribute \src "libresoc.v:139188.19-139188.129" - wire $and$libresoc.v:139188$5872_Y - attribute \src "libresoc.v:139192.19-139192.114" - wire $and$libresoc.v:139192$5876_Y - attribute \src "libresoc.v:139194.19-139194.112" - wire $and$libresoc.v:139194$5878_Y - attribute \src "libresoc.v:139196.19-139196.113" - wire $and$libresoc.v:139196$5880_Y - attribute \src "libresoc.v:139198.18-139198.111" - wire $and$libresoc.v:139198$5882_Y - attribute \src "libresoc.v:139199.19-139199.129" - wire $and$libresoc.v:139199$5883_Y - attribute \src "libresoc.v:139202.19-139202.114" - wire $and$libresoc.v:139202$5886_Y - attribute \src "libresoc.v:139204.19-139204.112" - wire $and$libresoc.v:139204$5888_Y - attribute \src "libresoc.v:139206.19-139206.113" - wire $and$libresoc.v:139206$5890_Y - attribute \src "libresoc.v:139208.19-139208.121" - wire $and$libresoc.v:139208$5892_Y - attribute \src "libresoc.v:139241.17-139241.106" - wire $and$libresoc.v:139241$5926_Y - attribute \src "libresoc.v:138998.17-138998.110" - wire $eq$libresoc.v:138998$5682_Y - attribute \src "libresoc.v:139009.18-139009.111" - wire $eq$libresoc.v:139009$5693_Y - attribute \src "libresoc.v:139020.18-139020.111" - wire $eq$libresoc.v:139020$5704_Y - attribute \src "libresoc.v:139053.17-139053.110" - wire $eq$libresoc.v:139053$5737_Y - attribute \src "libresoc.v:139054.18-139054.111" - wire $eq$libresoc.v:139054$5738_Y - attribute \src "libresoc.v:139065.18-139065.111" - wire $eq$libresoc.v:139065$5749_Y - attribute \src "libresoc.v:139087.18-139087.111" - wire $eq$libresoc.v:139087$5771_Y - attribute \src "libresoc.v:139131.18-139131.111" - wire $eq$libresoc.v:139131$5815_Y - attribute \src "libresoc.v:139140.19-139140.112" - wire $eq$libresoc.v:139140$5824_Y - attribute \src "libresoc.v:139141.19-139141.112" - wire $eq$libresoc.v:139141$5825_Y - attribute \src "libresoc.v:139142.18-139142.111" - wire $eq$libresoc.v:139142$5826_Y - attribute \src "libresoc.v:139144.19-139144.112" - wire $eq$libresoc.v:139144$5828_Y - attribute \src "libresoc.v:139147.19-139147.112" - wire $eq$libresoc.v:139147$5831_Y - attribute \src "libresoc.v:139157.19-139157.112" - wire $eq$libresoc.v:139157$5841_Y - attribute \src "libresoc.v:139164.17-139164.110" - wire $eq$libresoc.v:139164$5848_Y - attribute \src "libresoc.v:139165.18-139165.111" - wire $eq$libresoc.v:139165$5849_Y - attribute \src "libresoc.v:139168.19-139168.112" - wire $eq$libresoc.v:139168$5852_Y - attribute \src "libresoc.v:139169.19-139169.112" - wire $eq$libresoc.v:139169$5853_Y - attribute \src "libresoc.v:139179.19-139179.112" - wire $eq$libresoc.v:139179$5863_Y - attribute \src "libresoc.v:139189.19-139189.112" - wire $eq$libresoc.v:139189$5873_Y - attribute \src "libresoc.v:139190.19-139190.112" - wire $eq$libresoc.v:139190$5874_Y - attribute \src "libresoc.v:139200.19-139200.112" - wire $eq$libresoc.v:139200$5884_Y - attribute \src "libresoc.v:139209.18-139209.111" - wire $eq$libresoc.v:139209$5893_Y - attribute \src "libresoc.v:139210.19-139210.110" - wire $eq$libresoc.v:139210$5894_Y - attribute \src "libresoc.v:139212.19-139212.110" - wire $eq$libresoc.v:139212$5896_Y - attribute \src "libresoc.v:139213.19-139213.110" - wire $eq$libresoc.v:139213$5897_Y - attribute \src "libresoc.v:139215.19-139215.110" - wire $eq$libresoc.v:139215$5899_Y - attribute \src "libresoc.v:139219.18-139219.111" - wire $eq$libresoc.v:139219$5904_Y - attribute \src "libresoc.v:139220.19-139220.116" - wire $eq$libresoc.v:139220$5905_Y - attribute \src "libresoc.v:139221.19-139221.116" - wire $eq$libresoc.v:139221$5906_Y - attribute \src "libresoc.v:139223.19-139223.116" - wire $eq$libresoc.v:139223$5908_Y - attribute \src "libresoc.v:139218.19-139218.106" - wire width 8 $extend$libresoc.v:139218$5902_Y - attribute \src "libresoc.v:139148.19-139148.109" - wire $ne$libresoc.v:139148$5832_Y - attribute \src "libresoc.v:139150.19-139150.109" - wire $ne$libresoc.v:139150$5834_Y - attribute \src "libresoc.v:139152.19-139152.109" - wire $ne$libresoc.v:139152$5836_Y - attribute \src "libresoc.v:139158.19-139158.120" - wire $ne$libresoc.v:139158$5842_Y - attribute \src "libresoc.v:139160.19-139160.120" - wire $ne$libresoc.v:139160$5844_Y - attribute \src "libresoc.v:139162.19-139162.120" - wire $ne$libresoc.v:139162$5846_Y - attribute \src "libresoc.v:139170.19-139170.120" - wire $ne$libresoc.v:139170$5854_Y - attribute \src "libresoc.v:139172.19-139172.120" - wire $ne$libresoc.v:139172$5856_Y - attribute \src "libresoc.v:139174.19-139174.120" - wire $ne$libresoc.v:139174$5858_Y - attribute \src "libresoc.v:139180.19-139180.117" - wire $ne$libresoc.v:139180$5864_Y - attribute \src "libresoc.v:139182.19-139182.117" - wire $ne$libresoc.v:139182$5866_Y - attribute \src "libresoc.v:139184.19-139184.117" - wire $ne$libresoc.v:139184$5868_Y - attribute \src "libresoc.v:139191.19-139191.117" - wire $ne$libresoc.v:139191$5875_Y - attribute \src "libresoc.v:139193.19-139193.117" - wire $ne$libresoc.v:139193$5877_Y - attribute \src "libresoc.v:139195.19-139195.117" - wire $ne$libresoc.v:139195$5879_Y - attribute \src "libresoc.v:139201.19-139201.109" - wire $ne$libresoc.v:139201$5885_Y - attribute \src "libresoc.v:139203.19-139203.109" - wire $ne$libresoc.v:139203$5887_Y - attribute \src "libresoc.v:139205.19-139205.109" - wire $ne$libresoc.v:139205$5889_Y - attribute \src "libresoc.v:139155.19-139155.110" - wire $not$libresoc.v:139155$5839_Y - attribute \src "libresoc.v:139166.19-139166.121" - wire $not$libresoc.v:139166$5850_Y - attribute \src "libresoc.v:139177.19-139177.121" - wire $not$libresoc.v:139177$5861_Y - attribute \src "libresoc.v:139186.19-139186.118" - wire $not$libresoc.v:139186$5870_Y - attribute \src "libresoc.v:139197.19-139197.118" - wire $not$libresoc.v:139197$5881_Y - attribute \src "libresoc.v:139207.19-139207.110" - wire $not$libresoc.v:139207$5891_Y - attribute \src "libresoc.v:139211.19-139211.100" - wire $not$libresoc.v:139211$5895_Y - attribute \src "libresoc.v:139031.18-139031.104" - wire $or$libresoc.v:139031$5715_Y - attribute \src "libresoc.v:139076.18-139076.104" - wire $or$libresoc.v:139076$5760_Y - attribute \src "libresoc.v:139098.18-139098.104" - wire $or$libresoc.v:139098$5782_Y - attribute \src "libresoc.v:139143.19-139143.107" - wire $or$libresoc.v:139143$5827_Y - attribute \src "libresoc.v:139145.19-139145.107" - wire $or$libresoc.v:139145$5829_Y - attribute \src "libresoc.v:139153.18-139153.104" - wire $or$libresoc.v:139153$5837_Y - attribute \src "libresoc.v:139176.18-139176.104" - wire $or$libresoc.v:139176$5860_Y - attribute \src "libresoc.v:139214.19-139214.107" - wire $or$libresoc.v:139214$5898_Y - attribute \src "libresoc.v:139222.19-139222.107" - wire $or$libresoc.v:139222$5907_Y - attribute \src "libresoc.v:139230.17-139230.101" - wire $or$libresoc.v:139230$5915_Y - attribute \src "libresoc.v:139218.19-139218.106" - wire width 8 $pos$libresoc.v:139218$5903_Y - attribute \src "libresoc.v:138999.18-138999.133" - wire $ternary$libresoc.v:138999$5683_Y - attribute \src "libresoc.v:139000.19-139000.133" - wire $ternary$libresoc.v:139000$5684_Y - attribute \src "libresoc.v:139001.19-139001.134" - wire $ternary$libresoc.v:139001$5685_Y - attribute \src "libresoc.v:139002.19-139002.133" - wire $ternary$libresoc.v:139002$5686_Y - attribute \src "libresoc.v:139003.19-139003.132" - wire $ternary$libresoc.v:139003$5687_Y - attribute \src "libresoc.v:139004.19-139004.133" - wire $ternary$libresoc.v:139004$5688_Y - attribute \src "libresoc.v:139005.19-139005.133" - wire $ternary$libresoc.v:139005$5689_Y - attribute \src "libresoc.v:139006.19-139006.132" - wire $ternary$libresoc.v:139006$5690_Y - attribute \src "libresoc.v:139007.19-139007.133" - wire $ternary$libresoc.v:139007$5691_Y - attribute \src "libresoc.v:139008.19-139008.133" - wire $ternary$libresoc.v:139008$5692_Y - attribute \src "libresoc.v:139010.19-139010.132" - wire $ternary$libresoc.v:139010$5694_Y - attribute \src "libresoc.v:139011.19-139011.133" - wire $ternary$libresoc.v:139011$5695_Y - attribute \src "libresoc.v:139012.19-139012.133" - wire $ternary$libresoc.v:139012$5696_Y - attribute \src "libresoc.v:139013.19-139013.132" - wire $ternary$libresoc.v:139013$5697_Y - attribute \src "libresoc.v:139014.19-139014.133" - wire $ternary$libresoc.v:139014$5698_Y - attribute \src "libresoc.v:139015.19-139015.133" - wire $ternary$libresoc.v:139015$5699_Y - attribute \src "libresoc.v:139016.19-139016.132" - wire $ternary$libresoc.v:139016$5700_Y - attribute \src "libresoc.v:139017.19-139017.133" - wire $ternary$libresoc.v:139017$5701_Y - attribute \src "libresoc.v:139018.19-139018.133" - wire $ternary$libresoc.v:139018$5702_Y - attribute \src "libresoc.v:139019.19-139019.132" - wire $ternary$libresoc.v:139019$5703_Y - attribute \src "libresoc.v:139021.19-139021.133" - wire $ternary$libresoc.v:139021$5705_Y - attribute \src "libresoc.v:139022.19-139022.133" - wire $ternary$libresoc.v:139022$5706_Y - attribute \src "libresoc.v:139023.19-139023.132" - wire $ternary$libresoc.v:139023$5707_Y - attribute \src "libresoc.v:139024.19-139024.133" - wire $ternary$libresoc.v:139024$5708_Y - attribute \src "libresoc.v:139025.19-139025.133" - wire $ternary$libresoc.v:139025$5709_Y - attribute \src "libresoc.v:139026.19-139026.132" - wire $ternary$libresoc.v:139026$5710_Y - attribute \src "libresoc.v:139027.19-139027.133" - wire $ternary$libresoc.v:139027$5711_Y - attribute \src "libresoc.v:139028.19-139028.134" - wire $ternary$libresoc.v:139028$5712_Y - attribute \src "libresoc.v:139029.19-139029.135" - wire $ternary$libresoc.v:139029$5713_Y - attribute \src "libresoc.v:139030.19-139030.135" - wire $ternary$libresoc.v:139030$5714_Y - attribute \src "libresoc.v:139032.19-139032.136" - wire $ternary$libresoc.v:139032$5716_Y - attribute \src "libresoc.v:139033.19-139033.134" - wire $ternary$libresoc.v:139033$5717_Y - attribute \src "libresoc.v:139034.19-139034.135" - wire $ternary$libresoc.v:139034$5718_Y - attribute \src "libresoc.v:139035.19-139035.135" - wire $ternary$libresoc.v:139035$5719_Y - attribute \src "libresoc.v:139036.19-139036.136" - wire $ternary$libresoc.v:139036$5720_Y - attribute \src "libresoc.v:139037.19-139037.134" - wire $ternary$libresoc.v:139037$5721_Y - attribute \src "libresoc.v:139038.19-139038.133" - wire $ternary$libresoc.v:139038$5722_Y - attribute \src "libresoc.v:139039.19-139039.134" - wire $ternary$libresoc.v:139039$5723_Y - attribute \src "libresoc.v:139040.19-139040.133" - wire $ternary$libresoc.v:139040$5724_Y - attribute \src "libresoc.v:139041.19-139041.130" - wire $ternary$libresoc.v:139041$5725_Y - attribute \src "libresoc.v:139043.19-139043.130" - wire $ternary$libresoc.v:139043$5727_Y - attribute \src "libresoc.v:139044.19-139044.133" - wire $ternary$libresoc.v:139044$5728_Y - attribute \src "libresoc.v:139045.19-139045.132" - wire $ternary$libresoc.v:139045$5729_Y - attribute \src "libresoc.v:139046.19-139046.133" - wire $ternary$libresoc.v:139046$5730_Y - attribute \src "libresoc.v:139047.19-139047.132" - wire $ternary$libresoc.v:139047$5731_Y - attribute \src "libresoc.v:139048.19-139048.135" - wire $ternary$libresoc.v:139048$5732_Y - attribute \src "libresoc.v:139049.19-139049.134" - wire $ternary$libresoc.v:139049$5733_Y - attribute \src "libresoc.v:139050.19-139050.135" - wire $ternary$libresoc.v:139050$5734_Y - attribute \src "libresoc.v:139051.19-139051.135" - wire $ternary$libresoc.v:139051$5735_Y - attribute \src "libresoc.v:139052.19-139052.134" - wire $ternary$libresoc.v:139052$5736_Y - attribute \src "libresoc.v:139055.19-139055.135" - wire $ternary$libresoc.v:139055$5739_Y - attribute \src "libresoc.v:139056.19-139056.135" - wire $ternary$libresoc.v:139056$5740_Y - attribute \src "libresoc.v:139057.19-139057.134" - wire $ternary$libresoc.v:139057$5741_Y - attribute \src "libresoc.v:139058.19-139058.135" - wire $ternary$libresoc.v:139058$5742_Y - attribute \src "libresoc.v:139059.19-139059.135" - wire $ternary$libresoc.v:139059$5743_Y - attribute \src "libresoc.v:139060.19-139060.134" - wire $ternary$libresoc.v:139060$5744_Y - attribute \src "libresoc.v:139061.19-139061.135" - wire $ternary$libresoc.v:139061$5745_Y - attribute \src "libresoc.v:139062.19-139062.133" - wire $ternary$libresoc.v:139062$5746_Y - attribute \src "libresoc.v:139063.19-139063.134" - wire $ternary$libresoc.v:139063$5747_Y - attribute \src "libresoc.v:139064.19-139064.133" - wire $ternary$libresoc.v:139064$5748_Y - attribute \src "libresoc.v:139066.19-139066.134" - wire $ternary$libresoc.v:139066$5750_Y - attribute \src "libresoc.v:139067.19-139067.134" - wire $ternary$libresoc.v:139067$5751_Y - attribute \src "libresoc.v:139068.19-139068.133" - wire $ternary$libresoc.v:139068$5752_Y - attribute \src "libresoc.v:139069.19-139069.134" - wire $ternary$libresoc.v:139069$5753_Y - attribute \src "libresoc.v:139070.19-139070.134" - wire $ternary$libresoc.v:139070$5754_Y - attribute \src "libresoc.v:139071.19-139071.133" - wire $ternary$libresoc.v:139071$5755_Y - attribute \src "libresoc.v:139072.19-139072.134" - wire $ternary$libresoc.v:139072$5756_Y - attribute \src "libresoc.v:139073.19-139073.134" - wire $ternary$libresoc.v:139073$5757_Y - attribute \src "libresoc.v:139074.19-139074.133" - wire $ternary$libresoc.v:139074$5758_Y - attribute \src "libresoc.v:139075.19-139075.134" - wire $ternary$libresoc.v:139075$5759_Y - attribute \src "libresoc.v:139077.19-139077.134" - wire $ternary$libresoc.v:139077$5761_Y - attribute \src "libresoc.v:139078.19-139078.133" - wire $ternary$libresoc.v:139078$5762_Y - attribute \src "libresoc.v:139079.19-139079.134" - wire $ternary$libresoc.v:139079$5763_Y - attribute \src "libresoc.v:139080.19-139080.134" - wire $ternary$libresoc.v:139080$5764_Y - attribute \src "libresoc.v:139081.19-139081.133" - wire $ternary$libresoc.v:139081$5765_Y - attribute \src "libresoc.v:139082.19-139082.134" - wire $ternary$libresoc.v:139082$5766_Y - attribute \src "libresoc.v:139083.19-139083.135" - wire $ternary$libresoc.v:139083$5767_Y - attribute \src "libresoc.v:139084.19-139084.134" - wire $ternary$libresoc.v:139084$5768_Y - attribute \src "libresoc.v:139085.19-139085.135" - wire $ternary$libresoc.v:139085$5769_Y - attribute \src "libresoc.v:139086.19-139086.135" - wire $ternary$libresoc.v:139086$5770_Y - attribute \src "libresoc.v:139088.19-139088.134" - wire $ternary$libresoc.v:139088$5772_Y - attribute \src "libresoc.v:139089.19-139089.135" - wire $ternary$libresoc.v:139089$5773_Y - attribute \src "libresoc.v:139090.19-139090.133" - wire $ternary$libresoc.v:139090$5774_Y - attribute \src "libresoc.v:139091.19-139091.133" - wire $ternary$libresoc.v:139091$5775_Y - attribute \src "libresoc.v:139092.19-139092.133" - wire $ternary$libresoc.v:139092$5776_Y - attribute \src "libresoc.v:139093.19-139093.133" - wire $ternary$libresoc.v:139093$5777_Y - attribute \src "libresoc.v:139094.19-139094.133" - wire $ternary$libresoc.v:139094$5778_Y - attribute \src "libresoc.v:139095.19-139095.133" - wire $ternary$libresoc.v:139095$5779_Y - attribute \src "libresoc.v:139096.19-139096.133" - wire $ternary$libresoc.v:139096$5780_Y - attribute \src "libresoc.v:139097.19-139097.133" - wire $ternary$libresoc.v:139097$5781_Y - attribute \src "libresoc.v:139099.19-139099.133" - wire $ternary$libresoc.v:139099$5783_Y - attribute \src "libresoc.v:139100.19-139100.133" - wire $ternary$libresoc.v:139100$5784_Y - attribute \src "libresoc.v:139101.19-139101.134" - wire $ternary$libresoc.v:139101$5785_Y - attribute \src "libresoc.v:139102.19-139102.134" - wire $ternary$libresoc.v:139102$5786_Y - attribute \src "libresoc.v:139103.19-139103.135" - wire $ternary$libresoc.v:139103$5787_Y - attribute \src "libresoc.v:139104.19-139104.133" - wire $ternary$libresoc.v:139104$5788_Y - attribute \src "libresoc.v:139105.19-139105.135" - wire $ternary$libresoc.v:139105$5789_Y - attribute \src "libresoc.v:139106.19-139106.135" - wire $ternary$libresoc.v:139106$5790_Y - attribute \src "libresoc.v:139107.19-139107.134" - wire $ternary$libresoc.v:139107$5791_Y - attribute \src "libresoc.v:139108.19-139108.134" - wire $ternary$libresoc.v:139108$5792_Y - attribute \src "libresoc.v:139110.19-139110.134" - wire $ternary$libresoc.v:139110$5794_Y - attribute \src "libresoc.v:139111.19-139111.134" - wire $ternary$libresoc.v:139111$5795_Y - attribute \src "libresoc.v:139112.19-139112.134" - wire $ternary$libresoc.v:139112$5796_Y - attribute \src "libresoc.v:139113.19-139113.134" - wire $ternary$libresoc.v:139113$5797_Y - attribute \src "libresoc.v:139114.19-139114.135" - wire $ternary$libresoc.v:139114$5798_Y - attribute \src "libresoc.v:139115.19-139115.134" - wire $ternary$libresoc.v:139115$5799_Y - attribute \src "libresoc.v:139116.19-139116.135" - wire $ternary$libresoc.v:139116$5800_Y - attribute \src "libresoc.v:139117.19-139117.135" - wire $ternary$libresoc.v:139117$5801_Y - attribute \src "libresoc.v:139118.19-139118.134" - wire $ternary$libresoc.v:139118$5802_Y - attribute \src "libresoc.v:139119.19-139119.135" - wire $ternary$libresoc.v:139119$5803_Y - attribute \src "libresoc.v:139121.19-139121.136" - wire $ternary$libresoc.v:139121$5805_Y - attribute \src "libresoc.v:139122.19-139122.135" - wire $ternary$libresoc.v:139122$5806_Y - attribute \src "libresoc.v:139123.19-139123.136" - wire $ternary$libresoc.v:139123$5807_Y - attribute \src "libresoc.v:139124.19-139124.136" - wire $ternary$libresoc.v:139124$5808_Y - attribute \src "libresoc.v:139125.19-139125.135" - wire $ternary$libresoc.v:139125$5809_Y - attribute \src "libresoc.v:139126.19-139126.136" - wire $ternary$libresoc.v:139126$5810_Y - attribute \src "libresoc.v:139127.19-139127.136" - wire $ternary$libresoc.v:139127$5811_Y - attribute \src "libresoc.v:139128.19-139128.135" - wire $ternary$libresoc.v:139128$5812_Y - attribute \src "libresoc.v:139129.19-139129.136" - wire $ternary$libresoc.v:139129$5813_Y - attribute \src "libresoc.v:139130.19-139130.136" - wire $ternary$libresoc.v:139130$5814_Y - attribute \src "libresoc.v:139132.19-139132.135" - wire $ternary$libresoc.v:139132$5816_Y - attribute \src "libresoc.v:139133.19-139133.136" - wire $ternary$libresoc.v:139133$5817_Y - attribute \src "libresoc.v:139134.19-139134.136" - wire $ternary$libresoc.v:139134$5818_Y - attribute \src "libresoc.v:139135.19-139135.135" - wire $ternary$libresoc.v:139135$5819_Y - attribute \src "libresoc.v:139136.19-139136.136" - wire $ternary$libresoc.v:139136$5820_Y - attribute \src "libresoc.v:139137.19-139137.136" - wire $ternary$libresoc.v:139137$5821_Y - attribute \src "libresoc.v:139138.19-139138.135" - wire $ternary$libresoc.v:139138$5822_Y - attribute \src "libresoc.v:139139.19-139139.136" - wire $ternary$libresoc.v:139139$5823_Y - attribute \src "libresoc.v:139226.18-139226.130" - wire $ternary$libresoc.v:139226$5911_Y - attribute \src "libresoc.v:139227.18-139227.130" - wire $ternary$libresoc.v:139227$5912_Y - attribute \src "libresoc.v:139228.18-139228.130" - wire $ternary$libresoc.v:139228$5913_Y - attribute \src "libresoc.v:139229.18-139229.131" - wire $ternary$libresoc.v:139229$5914_Y - attribute \src "libresoc.v:139231.18-139231.130" - wire $ternary$libresoc.v:139231$5916_Y - attribute \src "libresoc.v:139232.18-139232.131" - wire $ternary$libresoc.v:139232$5917_Y - attribute \src "libresoc.v:139233.18-139233.131" - wire $ternary$libresoc.v:139233$5918_Y - attribute \src "libresoc.v:139234.18-139234.130" - wire $ternary$libresoc.v:139234$5919_Y - attribute \src "libresoc.v:139235.18-139235.131" - wire $ternary$libresoc.v:139235$5920_Y - attribute \src "libresoc.v:139236.18-139236.132" - wire $ternary$libresoc.v:139236$5921_Y - attribute \src "libresoc.v:139237.18-139237.132" - wire $ternary$libresoc.v:139237$5922_Y - attribute \src "libresoc.v:139238.18-139238.133" - wire $ternary$libresoc.v:139238$5923_Y - attribute \src "libresoc.v:139239.18-139239.133" - wire $ternary$libresoc.v:139239$5924_Y - attribute \src "libresoc.v:139240.18-139240.132" - wire $ternary$libresoc.v:139240$5925_Y - attribute \src "libresoc.v:139242.18-139242.133" - wire $ternary$libresoc.v:139242$5927_Y - attribute \src "libresoc.v:139243.18-139243.133" - wire $ternary$libresoc.v:139243$5928_Y - attribute \src "libresoc.v:139244.18-139244.132" - wire $ternary$libresoc.v:139244$5929_Y - attribute \src "libresoc.v:139245.18-139245.133" - wire $ternary$libresoc.v:139245$5930_Y - attribute \src "libresoc.v:139246.18-139246.133" - wire $ternary$libresoc.v:139246$5931_Y - attribute \src "libresoc.v:139247.18-139247.132" - wire $ternary$libresoc.v:139247$5932_Y - attribute \src "libresoc.v:139248.18-139248.133" - wire $ternary$libresoc.v:139248$5933_Y - attribute \src "libresoc.v:139249.18-139249.133" - wire $ternary$libresoc.v:139249$5934_Y - attribute \src "libresoc.v:139250.18-139250.132" - wire $ternary$libresoc.v:139250$5935_Y - attribute \src "libresoc.v:139251.18-139251.133" - wire $ternary$libresoc.v:139251$5936_Y + attribute \src "libresoc.v:140756.3-140800.6" + wire width 4 $2\dmi0__addr_i$next[3:0]$6077 + attribute \src "libresoc.v:140854.3-140880.6" + wire width 64 $2\dmi0__din$next[63:0]$6090 + attribute \src "libresoc.v:140425.3-140441.6" + wire $2\dmi0_addrsr__oe$next[0:0]$6014 + attribute \src "libresoc.v:140442.3-140462.6" + wire width 8 $2\dmi0_addrsr_reg$next[7:0]$6018 + attribute \src "libresoc.v:140881.3-140909.6" + wire width 64 $2\dmi0_datasr__i$next[63:0]$6095 + attribute \src "libresoc.v:140481.3-140497.6" + wire width 2 $2\dmi0_datasr__oe$next[1:0]$6029 + attribute \src "libresoc.v:140498.3-140518.6" + wire width 64 $2\dmi0_datasr_reg$next[63:0]$6033 + attribute \src "libresoc.v:140801.3-140853.6" + wire width 3 $2\fsm_state$455$next[2:0]$6083 + attribute \src "libresoc.v:140647.3-140699.6" + wire width 3 $2\fsm_state$next[2:0]$6060 + attribute \src "libresoc.v:140959.3-140979.6" + wire width 130 $2\io_bd$next[129:0]$6115 + attribute \src "libresoc.v:140941.3-140958.6" + wire width 130 $2\io_sr$next[129:0]$6111 + attribute \src "libresoc.v:140602.3-140646.6" + wire width 29 $2\jtag_wb__adr$next[28:0]$6054 + attribute \src "libresoc.v:140700.3-140726.6" + wire width 64 $2\jtag_wb__dat_w$next[63:0]$6067 + attribute \src "libresoc.v:140313.3-140329.6" + wire $2\jtag_wb_addrsr__oe$next[0:0]$5984 + attribute \src "libresoc.v:140330.3-140350.6" + wire width 29 $2\jtag_wb_addrsr_reg$next[28:0]$5988 + attribute \src "libresoc.v:140727.3-140755.6" + wire width 64 $2\jtag_wb_datasr__i$next[63:0]$6072 + attribute \src "libresoc.v:140369.3-140385.6" + wire width 2 $2\jtag_wb_datasr__oe$next[1:0]$5999 + attribute \src "libresoc.v:140386.3-140406.6" + wire width 64 $2\jtag_wb_datasr_reg$next[63:0]$6003 + attribute \src "libresoc.v:140257.3-140273.6" + wire $2\sr0__oe$next[0:0]$5969 + attribute \src "libresoc.v:140274.3-140294.6" + wire width 3 $2\sr0_reg$next[2:0]$5973 + attribute \src "libresoc.v:140537.3-140553.6" + wire $2\sr5__oe$next[0:0]$6044 + attribute \src "libresoc.v:140554.3-140574.6" + wire width 3 $2\sr5_reg$next[2:0]$6048 + attribute \src "libresoc.v:140910.3-140930.6" + wire $2\wb_dcache_en$next[0:0]$6104 + attribute \src "libresoc.v:140910.3-140930.6" + wire $2\wb_icache_en$next[0:0]$6105 + attribute \src "libresoc.v:140910.3-140930.6" + wire $2\wb_sram_en$next[0:0]$6106 + attribute \src "libresoc.v:140756.3-140800.6" + wire width 4 $3\dmi0__addr_i$next[3:0]$6078 + attribute \src "libresoc.v:140854.3-140880.6" + wire width 64 $3\dmi0__din$next[63:0]$6091 + attribute \src "libresoc.v:140442.3-140462.6" + wire width 8 $3\dmi0_addrsr_reg$next[7:0]$6019 + attribute \src "libresoc.v:140881.3-140909.6" + wire width 64 $3\dmi0_datasr__i$next[63:0]$6096 + attribute \src "libresoc.v:140498.3-140518.6" + wire width 64 $3\dmi0_datasr_reg$next[63:0]$6034 + attribute \src "libresoc.v:140801.3-140853.6" + wire width 3 $3\fsm_state$455$next[2:0]$6084 + attribute \src "libresoc.v:140647.3-140699.6" + wire width 3 $3\fsm_state$next[2:0]$6061 + attribute \src "libresoc.v:140602.3-140646.6" + wire width 29 $3\jtag_wb__adr$next[28:0]$6055 + attribute \src "libresoc.v:140700.3-140726.6" + wire width 64 $3\jtag_wb__dat_w$next[63:0]$6068 + attribute \src "libresoc.v:140330.3-140350.6" + wire width 29 $3\jtag_wb_addrsr_reg$next[28:0]$5989 + attribute \src "libresoc.v:140727.3-140755.6" + wire width 64 $3\jtag_wb_datasr__i$next[63:0]$6073 + attribute \src "libresoc.v:140386.3-140406.6" + wire width 64 $3\jtag_wb_datasr_reg$next[63:0]$6004 + attribute \src "libresoc.v:140274.3-140294.6" + wire width 3 $3\sr0_reg$next[2:0]$5974 + attribute \src "libresoc.v:140554.3-140574.6" + wire width 3 $3\sr5_reg$next[2:0]$6049 + attribute \src "libresoc.v:140756.3-140800.6" + wire width 4 $4\dmi0__addr_i$next[3:0]$6079 + attribute \src "libresoc.v:140801.3-140853.6" + wire width 3 $4\fsm_state$455$next[2:0]$6085 + attribute \src "libresoc.v:140647.3-140699.6" + wire width 3 $4\fsm_state$next[2:0]$6062 + attribute \src "libresoc.v:140602.3-140646.6" + wire width 29 $4\jtag_wb__adr$next[28:0]$6056 + attribute \src "libresoc.v:140801.3-140853.6" + wire width 3 $5\fsm_state$455$next[2:0]$6086 + attribute \src "libresoc.v:140647.3-140699.6" + wire width 3 $5\fsm_state$next[2:0]$6063 + attribute \src "libresoc.v:140076.19-140076.112" + wire width 30 $add$libresoc.v:140076$5882_Y + attribute \src "libresoc.v:140077.19-140077.112" + wire width 30 $add$libresoc.v:140077$5883_Y + attribute \src "libresoc.v:140084.19-140084.112" + wire width 5 $add$libresoc.v:140084$5891_Y + attribute \src "libresoc.v:140085.19-140085.112" + wire width 5 $add$libresoc.v:140085$5892_Y + attribute \src "libresoc.v:139926.18-139926.112" + wire $and$libresoc.v:139926$5732_Y + attribute \src "libresoc.v:139993.18-139993.108" + wire $and$libresoc.v:139993$5799_Y + attribute \src "libresoc.v:140004.18-140004.110" + wire $and$libresoc.v:140004$5810_Y + attribute \src "libresoc.v:140006.19-140006.110" + wire $and$libresoc.v:140006$5812_Y + attribute \src "libresoc.v:140009.19-140009.114" + wire $and$libresoc.v:140009$5815_Y + attribute \src "libresoc.v:140011.19-140011.112" + wire $and$libresoc.v:140011$5817_Y + attribute \src "libresoc.v:140013.19-140013.113" + wire $and$libresoc.v:140013$5819_Y + attribute \src "libresoc.v:140016.19-140016.121" + wire $and$libresoc.v:140016$5822_Y + attribute \src "libresoc.v:140019.19-140019.114" + wire $and$libresoc.v:140019$5825_Y + attribute \src "libresoc.v:140021.19-140021.112" + wire $and$libresoc.v:140021$5827_Y + attribute \src "libresoc.v:140023.19-140023.113" + wire $and$libresoc.v:140023$5829_Y + attribute \src "libresoc.v:140025.19-140025.132" + wire $and$libresoc.v:140025$5831_Y + attribute \src "libresoc.v:140030.19-140030.114" + wire $and$libresoc.v:140030$5836_Y + attribute \src "libresoc.v:140032.19-140032.112" + wire $and$libresoc.v:140032$5838_Y + attribute \src "libresoc.v:140034.19-140034.113" + wire $and$libresoc.v:140034$5840_Y + attribute \src "libresoc.v:140036.19-140036.132" + wire $and$libresoc.v:140036$5842_Y + attribute \src "libresoc.v:140040.19-140040.114" + wire $and$libresoc.v:140040$5846_Y + attribute \src "libresoc.v:140042.19-140042.112" + wire $and$libresoc.v:140042$5848_Y + attribute \src "libresoc.v:140044.19-140044.113" + wire $and$libresoc.v:140044$5850_Y + attribute \src "libresoc.v:140046.19-140046.129" + wire $and$libresoc.v:140046$5852_Y + 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"libresoc.v:139882.17-139882.110" + wire $eq$libresoc.v:139882$5688_Y + attribute \src "libresoc.v:139893.18-139893.111" + wire $eq$libresoc.v:139893$5699_Y + attribute \src "libresoc.v:139904.18-139904.111" + wire $eq$libresoc.v:139904$5710_Y + attribute \src "libresoc.v:139937.17-139937.110" + wire $eq$libresoc.v:139937$5743_Y + attribute \src "libresoc.v:139938.18-139938.111" + wire $eq$libresoc.v:139938$5744_Y + attribute \src "libresoc.v:139949.18-139949.111" + wire $eq$libresoc.v:139949$5755_Y + attribute \src "libresoc.v:139971.18-139971.111" + wire $eq$libresoc.v:139971$5777_Y + attribute \src "libresoc.v:140000.19-140000.112" + wire $eq$libresoc.v:140000$5806_Y + attribute \src "libresoc.v:140001.19-140001.112" + wire $eq$libresoc.v:140001$5807_Y + attribute \src "libresoc.v:140003.19-140003.112" + wire $eq$libresoc.v:140003$5809_Y + attribute \src "libresoc.v:140007.19-140007.112" + wire $eq$libresoc.v:140007$5813_Y + attribute \src "libresoc.v:140015.18-140015.111" + wire $eq$libresoc.v:140015$5821_Y + attribute \src "libresoc.v:140017.19-140017.112" + wire $eq$libresoc.v:140017$5823_Y + attribute \src "libresoc.v:140026.18-140026.111" + wire $eq$libresoc.v:140026$5832_Y + attribute \src "libresoc.v:140027.19-140027.112" + wire $eq$libresoc.v:140027$5833_Y + attribute \src "libresoc.v:140028.19-140028.112" + wire $eq$libresoc.v:140028$5834_Y + attribute \src "libresoc.v:140038.19-140038.112" + wire $eq$libresoc.v:140038$5844_Y + attribute \src "libresoc.v:140047.19-140047.112" + wire $eq$libresoc.v:140047$5853_Y + attribute \src "libresoc.v:140048.17-140048.110" + wire $eq$libresoc.v:140048$5854_Y + attribute \src "libresoc.v:140049.18-140049.111" + wire $eq$libresoc.v:140049$5855_Y + attribute \src "libresoc.v:140050.19-140050.112" + wire $eq$libresoc.v:140050$5856_Y + attribute \src "libresoc.v:140059.19-140059.112" + wire $eq$libresoc.v:140059$5865_Y + attribute \src "libresoc.v:140069.19-140069.110" + wire $eq$libresoc.v:140069$5875_Y + attribute \src "libresoc.v:140072.19-140072.110" + wire $eq$libresoc.v:140072$5878_Y + attribute \src "libresoc.v:140073.19-140073.110" + wire $eq$libresoc.v:140073$5879_Y + attribute \src "libresoc.v:140075.19-140075.110" + wire $eq$libresoc.v:140075$5881_Y + attribute \src "libresoc.v:140079.19-140079.116" + wire $eq$libresoc.v:140079$5886_Y + attribute \src "libresoc.v:140080.19-140080.116" + wire $eq$libresoc.v:140080$5887_Y + attribute \src "libresoc.v:140083.19-140083.116" + wire $eq$libresoc.v:140083$5890_Y + attribute \src "libresoc.v:140086.18-140086.111" + wire $eq$libresoc.v:140086$5893_Y + attribute \src "libresoc.v:140087.18-140087.111" + wire $eq$libresoc.v:140087$5894_Y + attribute \src "libresoc.v:140078.19-140078.106" + wire width 8 $extend$libresoc.v:140078$5884_Y + attribute \src "libresoc.v:140008.19-140008.109" + wire $ne$libresoc.v:140008$5814_Y + attribute \src "libresoc.v:140010.19-140010.109" + wire $ne$libresoc.v:140010$5816_Y + attribute \src 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attribute \src "libresoc.v:139930.19-139930.133" + wire $ternary$libresoc.v:139930$5736_Y + attribute \src "libresoc.v:139931.19-139931.134" + wire $ternary$libresoc.v:139931$5737_Y + attribute \src "libresoc.v:139932.19-139932.134" + wire $ternary$libresoc.v:139932$5738_Y + attribute \src "libresoc.v:139933.19-139933.133" + wire $ternary$libresoc.v:139933$5739_Y + attribute \src "libresoc.v:139934.19-139934.134" + wire $ternary$libresoc.v:139934$5740_Y + attribute \src "libresoc.v:139935.19-139935.134" + wire $ternary$libresoc.v:139935$5741_Y + attribute \src "libresoc.v:139936.19-139936.133" + wire $ternary$libresoc.v:139936$5742_Y + attribute \src "libresoc.v:139939.19-139939.134" + wire $ternary$libresoc.v:139939$5745_Y + attribute \src "libresoc.v:139940.19-139940.134" + wire $ternary$libresoc.v:139940$5746_Y + attribute \src "libresoc.v:139941.19-139941.133" + wire $ternary$libresoc.v:139941$5747_Y + attribute \src "libresoc.v:139942.19-139942.134" + wire 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attribute \src "libresoc.v:139966.19-139966.134" + wire $ternary$libresoc.v:139966$5772_Y + attribute \src "libresoc.v:139967.19-139967.134" + wire $ternary$libresoc.v:139967$5773_Y + attribute \src "libresoc.v:139968.19-139968.134" + wire $ternary$libresoc.v:139968$5774_Y + attribute \src "libresoc.v:139969.19-139969.134" + wire $ternary$libresoc.v:139969$5775_Y + attribute \src "libresoc.v:139970.19-139970.134" + wire $ternary$libresoc.v:139970$5776_Y + attribute \src "libresoc.v:139972.19-139972.134" + wire $ternary$libresoc.v:139972$5778_Y + attribute \src "libresoc.v:139973.19-139973.134" + wire $ternary$libresoc.v:139973$5779_Y + attribute \src "libresoc.v:139974.19-139974.135" + wire $ternary$libresoc.v:139974$5780_Y + attribute \src "libresoc.v:139975.19-139975.134" + wire $ternary$libresoc.v:139975$5781_Y + attribute \src "libresoc.v:139976.19-139976.135" + wire $ternary$libresoc.v:139976$5782_Y + attribute \src "libresoc.v:139977.19-139977.135" + wire $ternary$libresoc.v:139977$5783_Y + attribute \src "libresoc.v:139978.19-139978.134" + wire $ternary$libresoc.v:139978$5784_Y + attribute \src "libresoc.v:139979.19-139979.135" + wire $ternary$libresoc.v:139979$5785_Y + attribute \src "libresoc.v:139980.19-139980.136" + wire $ternary$libresoc.v:139980$5786_Y + attribute \src "libresoc.v:139981.19-139981.135" + wire $ternary$libresoc.v:139981$5787_Y + attribute \src "libresoc.v:139983.19-139983.136" + wire $ternary$libresoc.v:139983$5789_Y + attribute \src "libresoc.v:139984.19-139984.136" + wire $ternary$libresoc.v:139984$5790_Y + attribute \src "libresoc.v:139985.19-139985.135" + wire $ternary$libresoc.v:139985$5791_Y + attribute \src "libresoc.v:139986.19-139986.136" + wire $ternary$libresoc.v:139986$5792_Y + attribute \src "libresoc.v:139987.19-139987.136" + wire $ternary$libresoc.v:139987$5793_Y + attribute \src "libresoc.v:139988.19-139988.135" + wire $ternary$libresoc.v:139988$5794_Y + attribute \src "libresoc.v:139989.19-139989.136" + wire $ternary$libresoc.v:139989$5795_Y + attribute \src "libresoc.v:139990.19-139990.136" + wire $ternary$libresoc.v:139990$5796_Y + attribute \src "libresoc.v:139991.19-139991.135" + wire $ternary$libresoc.v:139991$5797_Y + attribute \src "libresoc.v:139992.19-139992.136" + wire $ternary$libresoc.v:139992$5798_Y + attribute \src "libresoc.v:139994.19-139994.136" + wire $ternary$libresoc.v:139994$5800_Y + attribute \src "libresoc.v:139995.19-139995.135" + wire $ternary$libresoc.v:139995$5801_Y + attribute \src "libresoc.v:139996.19-139996.136" + wire $ternary$libresoc.v:139996$5802_Y + attribute \src "libresoc.v:139997.19-139997.136" + wire $ternary$libresoc.v:139997$5803_Y + attribute \src "libresoc.v:139998.19-139998.135" + wire $ternary$libresoc.v:139998$5804_Y + attribute \src "libresoc.v:139999.19-139999.136" + wire $ternary$libresoc.v:139999$5805_Y + attribute \src "libresoc.v:140088.18-140088.130" + wire $ternary$libresoc.v:140088$5895_Y + attribute \src "libresoc.v:140089.18-140089.130" + wire $ternary$libresoc.v:140089$5896_Y + attribute \src "libresoc.v:140090.18-140090.130" + wire $ternary$libresoc.v:140090$5897_Y + attribute \src "libresoc.v:140091.18-140091.131" + wire $ternary$libresoc.v:140091$5898_Y + attribute \src "libresoc.v:140093.18-140093.130" + wire $ternary$libresoc.v:140093$5900_Y + attribute \src "libresoc.v:140094.18-140094.131" + wire $ternary$libresoc.v:140094$5901_Y + attribute \src "libresoc.v:140095.18-140095.131" + wire $ternary$libresoc.v:140095$5902_Y + attribute \src "libresoc.v:140096.18-140096.130" + wire $ternary$libresoc.v:140096$5903_Y + attribute \src "libresoc.v:140097.18-140097.131" + wire $ternary$libresoc.v:140097$5904_Y + attribute \src "libresoc.v:140098.18-140098.132" + wire $ternary$libresoc.v:140098$5905_Y + attribute \src "libresoc.v:140099.18-140099.132" + wire $ternary$libresoc.v:140099$5906_Y + attribute \src "libresoc.v:140100.18-140100.133" + wire $ternary$libresoc.v:140100$5907_Y + attribute \src "libresoc.v:140101.18-140101.133" + wire $ternary$libresoc.v:140101$5908_Y + attribute \src "libresoc.v:140102.18-140102.132" + wire $ternary$libresoc.v:140102$5909_Y + attribute \src "libresoc.v:140104.18-140104.133" + wire $ternary$libresoc.v:140104$5911_Y + attribute \src "libresoc.v:140105.18-140105.133" + wire $ternary$libresoc.v:140105$5912_Y + attribute \src "libresoc.v:140106.18-140106.132" + wire $ternary$libresoc.v:140106$5913_Y + attribute \src "libresoc.v:140107.18-140107.133" + wire $ternary$libresoc.v:140107$5914_Y + attribute \src "libresoc.v:140108.18-140108.133" + wire $ternary$libresoc.v:140108$5915_Y + attribute \src "libresoc.v:140109.18-140109.132" + wire $ternary$libresoc.v:140109$5916_Y + attribute \src "libresoc.v:140110.18-140110.133" + wire $ternary$libresoc.v:140110$5917_Y + attribute \src "libresoc.v:140111.18-140111.133" + wire $ternary$libresoc.v:140111$5918_Y + attribute \src "libresoc.v:140112.18-140112.132" + wire $ternary$libresoc.v:140112$5919_Y + attribute \src "libresoc.v:140113.18-140113.133" + wire $ternary$libresoc.v:140113$5920_Y attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" wire \$1 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" @@ -218490,35 +219232,35 @@ module \jtag wire \$157 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" wire \$159 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$161 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$163 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$165 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$167 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$169 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:400" wire \$17 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$171 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$173 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$175 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$177 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$179 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$181 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$183 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$185 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$187 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$189 @@ -218548,344 +219290,300 @@ module \jtag wire \$21 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$211 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$213 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$215 + wire \$213 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - wire \$217 + wire \$215 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + wire \$217 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$219 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$221 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$223 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$225 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$227 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$229 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$23 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$231 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$233 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$235 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$237 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$239 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$241 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$243 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$245 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$247 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$249 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" wire \$25 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$251 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$253 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$255 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$257 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" wire \$259 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - wire \$261 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + wire \$261 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$263 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$265 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$267 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$269 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" wire \$27 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$271 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$273 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$275 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$277 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$279 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$281 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$283 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$285 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$287 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$289 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" wire \$29 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$291 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$293 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$295 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$297 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$299 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" wire \$3 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" wire \$301 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$303 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - wire \$305 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - wire \$307 + wire \$305 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + wire \$307 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" wire \$309 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" wire \$31 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$311 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$313 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$315 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" wire \$317 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" wire \$319 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" wire \$321 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" wire \$323 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$325 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$327 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$329 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$33 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$331 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$333 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$335 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$337 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$339 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" wire \$341 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$343 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$345 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$347 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$349 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$35 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$351 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$353 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$355 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$357 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" wire \$359 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" wire \$361 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$363 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$365 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$367 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$369 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" wire \$37 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$371 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$373 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$375 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$377 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" wire \$379 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$381 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$383 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$385 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$387 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$389 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" wire \$39 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$391 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$393 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$395 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" wire \$397 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" wire \$399 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$401 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$403 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$405 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$407 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$409 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" wire \$41 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$411 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$413 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" wire \$415 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" wire \$417 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$419 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" wire \$421 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$423 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" wire \$425 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$427 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" wire \$429 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" wire \$43 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$431 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$433 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$435 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$437 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$439 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - wire \$441 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - wire \$443 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$445 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$447 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$449 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" - wire \$45 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$451 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$453 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$455 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$457 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$459 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - wire \$461 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$463 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - wire \$465 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$467 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - wire \$469 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" - wire \$47 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$471 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - wire \$473 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$475 + wire \$431 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - wire \$477 + wire \$433 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" - wire \$479 + wire \$435 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" - wire \$480 + wire \$436 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - wire \$483 + wire \$439 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - wire \$485 + wire \$441 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - wire \$487 + wire \$443 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:792" - wire \$489 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405" - wire \$49 + wire \$445 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" - wire width 30 \$491 + wire width 30 \$447 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" - wire width 30 \$492 + wire width 30 \$448 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" + wire \$45 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" - wire width 30 \$494 + wire width 30 \$450 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" - wire width 30 \$495 + wire width 30 \$451 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - wire width 8 \$497 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - wire \$5 + wire width 8 \$453 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - wire \$500 + wire \$456 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - wire \$502 + wire \$458 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - wire \$504 + wire \$460 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" - wire \$506 + wire \$462 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" - wire width 5 \$508 + wire width 5 \$464 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" - wire width 5 \$509 - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - wire \$51 + wire width 5 \$465 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" - wire width 5 \$511 + wire width 5 \$467 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" - wire width 5 \$512 + wire width 5 \$468 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" + wire \$47 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" + wire \$51 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" wire \$53 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" @@ -218939,13 +219637,13 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" wire \$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 324 \TAP_bus__tck + wire input 280 \TAP_bus__tck attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 162 \TAP_bus__tdi + wire input 140 \TAP_bus__tdi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire output 315 \TAP_bus__tdo + wire output 271 \TAP_bus__tdo attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 325 \TAP_bus__tms + wire input 281 \TAP_bus__tms attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:414" wire \TAP_tdo attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:24" @@ -218968,8 +219666,8 @@ module \jtag wire width 4 \_irblock_ir attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:128" wire \_irblock_tdo - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" - wire input 326 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 282 \clk attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" wire input 6 \dmi0__ack_o attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" @@ -219045,27 +219743,27 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:661" wire \dmi0_datasr_update_core_prev$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 163 \eint_0__core__i + wire output 141 \eint_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 10 \eint_0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 164 \eint_1__core__i + wire output 142 \eint_1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 11 \eint_1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 165 \eint_2__core__i + wire output 143 \eint_2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 12 \eint_2__pad__i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" wire width 3 \fsm_state attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - wire width 3 \fsm_state$499 + wire width 3 \fsm_state$455 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - wire width 3 \fsm_state$499$next + wire width 3 \fsm_state$455$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" wire width 3 \fsm_state$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 172 \gpio_e10__core__i + wire output 150 \gpio_e10__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 20 \gpio_e10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -219073,11 +219771,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 19 \gpio_e10__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 173 \gpio_e10__pad__o + wire output 151 \gpio_e10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 174 \gpio_e10__pad__oe + wire output 152 \gpio_e10__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 175 \gpio_e11__core__i + wire output 153 \gpio_e11__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 23 \gpio_e11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -219085,11 +219783,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 22 \gpio_e11__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 176 \gpio_e11__pad__o + wire output 154 \gpio_e11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 177 \gpio_e11__pad__oe + wire output 155 \gpio_e11__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 178 \gpio_e12__core__i + wire output 156 \gpio_e12__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 26 \gpio_e12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -219097,11 +219795,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 25 \gpio_e12__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 179 \gpio_e12__pad__o + wire output 157 \gpio_e12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 180 \gpio_e12__pad__oe + wire output 158 \gpio_e12__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 181 \gpio_e13__core__i + wire output 159 \gpio_e13__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 29 \gpio_e13__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -219109,11 +219807,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 28 \gpio_e13__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 182 \gpio_e13__pad__o + wire output 160 \gpio_e13__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 183 \gpio_e13__pad__oe + wire output 161 \gpio_e13__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 184 \gpio_e14__core__i + wire output 162 \gpio_e14__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 32 \gpio_e14__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -219121,11 +219819,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 31 \gpio_e14__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 185 \gpio_e14__pad__o + wire output 163 \gpio_e14__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 186 \gpio_e14__pad__oe + wire output 164 \gpio_e14__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 187 \gpio_e15__core__i + wire output 165 \gpio_e15__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 35 \gpio_e15__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -219133,11 +219831,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 34 \gpio_e15__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 188 \gpio_e15__pad__o + wire output 166 \gpio_e15__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 189 \gpio_e15__pad__oe + wire output 167 \gpio_e15__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 166 \gpio_e8__core__i + wire output 144 \gpio_e8__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 14 \gpio_e8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -219145,11 +219843,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 13 \gpio_e8__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 167 \gpio_e8__pad__o + wire output 145 \gpio_e8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 168 \gpio_e8__pad__oe + wire output 146 \gpio_e8__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 169 \gpio_e9__core__i + wire output 147 \gpio_e9__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 17 \gpio_e9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -219157,11 +219855,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 16 \gpio_e9__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 170 \gpio_e9__pad__o + wire output 148 \gpio_e9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 171 \gpio_e9__pad__oe + wire output 149 \gpio_e9__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 190 \gpio_s0__core__i + wire output 168 \gpio_s0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 38 \gpio_s0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -219169,11 +219867,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 37 \gpio_s0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 191 \gpio_s0__pad__o + wire output 169 \gpio_s0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 192 \gpio_s0__pad__oe + wire output 170 \gpio_s0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 193 \gpio_s1__core__i + wire output 171 \gpio_s1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 41 \gpio_s1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -219181,11 +219879,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 40 \gpio_s1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 194 \gpio_s1__pad__o + wire output 172 \gpio_s1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 195 \gpio_s1__pad__oe + wire output 173 \gpio_s1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 196 \gpio_s2__core__i + wire output 174 \gpio_s2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 44 \gpio_s2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -219193,11 +219891,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 43 \gpio_s2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 197 \gpio_s2__pad__o + wire output 175 \gpio_s2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 198 \gpio_s2__pad__oe + wire output 176 \gpio_s2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 199 \gpio_s3__core__i + wire output 177 \gpio_s3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 47 \gpio_s3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -219205,11 +219903,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 46 \gpio_s3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 200 \gpio_s3__pad__o + wire output 178 \gpio_s3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 201 \gpio_s3__pad__oe + wire output 179 \gpio_s3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 202 \gpio_s4__core__i + wire output 180 \gpio_s4__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 50 \gpio_s4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -219217,11 +219915,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 49 \gpio_s4__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 203 \gpio_s4__pad__o + wire output 181 \gpio_s4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 204 \gpio_s4__pad__oe + wire output 182 \gpio_s4__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 205 \gpio_s5__core__i + wire output 183 \gpio_s5__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 53 \gpio_s5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -219229,11 +219927,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 52 \gpio_s5__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 206 \gpio_s5__pad__o + wire output 184 \gpio_s5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 207 \gpio_s5__pad__oe + wire output 185 \gpio_s5__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 208 \gpio_s6__core__i + wire output 186 \gpio_s6__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 56 \gpio_s6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -219241,11 +219939,11 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 55 \gpio_s6__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 209 \gpio_s6__pad__o + wire output 187 \gpio_s6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 210 \gpio_s6__pad__oe + wire output 188 \gpio_s6__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 211 \gpio_s7__core__i + wire output 189 \gpio_s7__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 59 \gpio_s7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -219253,15 +219951,15 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 58 \gpio_s7__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 212 \gpio_s7__pad__o + wire output 190 \gpio_s7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 213 \gpio_s7__pad__oe - attribute \src "libresoc.v:137576.7-137576.15" + wire output 191 \gpio_s7__pad__oe + attribute \src "libresoc.v:138592.7-138592.15" wire \initial attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549" - wire width 152 \io_bd + wire width 130 \io_bd attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:549" - wire width 152 \io_bd$next + wire width 130 \io_bd$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:395" wire \io_bd2core attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:394" @@ -219271,31 +219969,31 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:392" wire \io_shift attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" - wire width 152 \io_sr + wire width 130 \io_sr attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:548" - wire width 152 \io_sr$next + wire width 130 \io_sr$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:393" wire \io_update attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire input 322 \jtag_wb__ack + wire input 278 \jtag_wb__ack attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 29 output 316 \jtag_wb__adr + wire width 29 output 272 \jtag_wb__adr attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire width 29 \jtag_wb__adr$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 318 \jtag_wb__cyc + wire output 274 \jtag_wb__cyc attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 64 input 323 \jtag_wb__dat_r + wire width 64 input 279 \jtag_wb__dat_r attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 64 output 321 \jtag_wb__dat_w + wire width 64 output 277 \jtag_wb__dat_w attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire width 64 \jtag_wb__dat_w$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 317 \jtag_wb__sel + wire output 273 \jtag_wb__sel attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 319 \jtag_wb__stb + wire output 275 \jtag_wb__stb attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 320 \jtag_wb__we + wire output 276 \jtag_wb__we attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" wire width 29 \jtag_wb_addrsr__i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:731" @@ -219357,51 +220055,35 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 61 \mspi0_clk__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 214 \mspi0_clk__pad__o + wire output 192 \mspi0_clk__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 62 \mspi0_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 215 \mspi0_cs_n__pad__o + wire output 193 \mspi0_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 217 \mspi0_miso__core__i + wire output 195 \mspi0_miso__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 64 \mspi0_miso__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 63 \mspi0_mosi__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 216 \mspi0_mosi__pad__o + wire output 194 \mspi0_mosi__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 65 \mspi1_clk__core__o + wire input 68 \mtwi_scl__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 218 \mspi1_clk__pad__o + wire output 199 \mtwi_scl__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 66 \mspi1_cs_n__core__o + wire output 196 \mtwi_sda__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 219 \mspi1_cs_n__pad__o + wire input 66 \mtwi_sda__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 221 \mspi1_miso__core__i + wire input 67 \mtwi_sda__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 68 \mspi1_miso__pad__i + wire input 65 \mtwi_sda__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 67 \mspi1_mosi__core__o + wire output 197 \mtwi_sda__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 220 \mspi1_mosi__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 72 \mtwi_scl__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 225 \mtwi_scl__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 222 \mtwi_sda__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 70 \mtwi_sda__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 71 \mtwi_sda__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 69 \mtwi_sda__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 223 \mtwi_sda__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 224 \mtwi_sda__pad__oe + wire output 198 \mtwi_sda__pad__oe attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" wire \negjtag_clk attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:29" @@ -219410,364 +220092,292 @@ module \jtag wire \posjtag_clk attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:28" wire \posjtag_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 73 \pwm_0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 226 \pwm_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 74 \pwm_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 227 \pwm_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 78 \sd0_clk__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 231 \sd0_clk__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 228 \sd0_cmd__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 76 \sd0_cmd__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 77 \sd0_cmd__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 75 \sd0_cmd__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 229 \sd0_cmd__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 230 \sd0_cmd__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 232 \sd0_data0__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 80 \sd0_data0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 81 \sd0_data0__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 79 \sd0_data0__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 233 \sd0_data0__pad__o + wire input 94 \sdr_a_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 234 \sd0_data0__pad__oe + wire output 225 \sdr_a_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 235 \sd0_data1__core__i + wire input 112 \sdr_a_10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 83 \sd0_data1__core__o + wire output 243 \sdr_a_10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 84 \sd0_data1__core__oe + wire input 113 \sdr_a_11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 82 \sd0_data1__pad__i + wire output 244 \sdr_a_11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 236 \sd0_data1__pad__o + wire input 114 \sdr_a_12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 237 \sd0_data1__pad__oe + wire output 245 \sdr_a_12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 238 \sd0_data2__core__i + wire input 95 \sdr_a_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 86 \sd0_data2__core__o + wire output 226 \sdr_a_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 87 \sd0_data2__core__oe + wire input 96 \sdr_a_2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 85 \sd0_data2__pad__i + wire output 227 \sdr_a_2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 239 \sd0_data2__pad__o + wire input 97 \sdr_a_3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 240 \sd0_data2__pad__oe + wire output 228 \sdr_a_3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 241 \sd0_data3__core__i + wire input 98 \sdr_a_4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 89 \sd0_data3__core__o + wire output 229 \sdr_a_4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 90 \sd0_data3__core__oe + wire input 99 \sdr_a_5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 88 \sd0_data3__pad__i + wire output 230 \sdr_a_5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 242 \sd0_data3__pad__o + wire input 100 \sdr_a_6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 243 \sd0_data3__pad__oe + wire output 231 \sdr_a_6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 116 \sdr_a_0__core__o + wire input 101 \sdr_a_7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 269 \sdr_a_0__pad__o + wire output 232 \sdr_a_7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 134 \sdr_a_10__core__o + wire input 102 \sdr_a_8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 287 \sdr_a_10__pad__o + wire output 233 \sdr_a_8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 135 \sdr_a_11__core__o + wire input 103 \sdr_a_9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 288 \sdr_a_11__pad__o + wire output 234 \sdr_a_9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 136 \sdr_a_12__core__o + wire input 104 \sdr_ba_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 289 \sdr_a_12__pad__o + wire output 235 \sdr_ba_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 117 \sdr_a_1__core__o + wire input 105 \sdr_ba_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 270 \sdr_a_1__pad__o + wire output 236 \sdr_ba_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 118 \sdr_a_2__core__o + wire input 109 \sdr_cas_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 271 \sdr_a_2__pad__o + wire output 240 \sdr_cas_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 119 \sdr_a_3__core__o + wire input 107 \sdr_cke__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 272 \sdr_a_3__pad__o + wire output 238 \sdr_cke__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 120 \sdr_a_4__core__o + wire input 106 \sdr_clock__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 273 \sdr_a_4__pad__o + wire output 237 \sdr_clock__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 121 \sdr_a_5__core__o + wire input 111 \sdr_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 274 \sdr_a_5__pad__o + wire output 242 \sdr_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 122 \sdr_a_6__core__o + wire input 69 \sdr_dm_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 275 \sdr_a_6__pad__o + wire output 200 \sdr_dm_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 123 \sdr_a_7__core__o + wire input 115 \sdr_dm_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 276 \sdr_a_7__pad__o + wire output 246 \sdr_dm_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 124 \sdr_a_8__core__o + wire output 201 \sdr_dq_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 277 \sdr_a_8__pad__o + wire input 71 \sdr_dq_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 125 \sdr_a_9__core__o + wire input 72 \sdr_dq_0__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 278 \sdr_a_9__pad__o + wire input 70 \sdr_dq_0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 126 \sdr_ba_0__core__o + wire output 202 \sdr_dq_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 279 \sdr_ba_0__pad__o + wire output 203 \sdr_dq_0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 127 \sdr_ba_1__core__o + wire output 253 \sdr_dq_10__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 280 \sdr_ba_1__pad__o + wire input 123 \sdr_dq_10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 131 \sdr_cas_n__core__o + wire input 124 \sdr_dq_10__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 284 \sdr_cas_n__pad__o + wire input 122 \sdr_dq_10__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 129 \sdr_cke__core__o + wire output 254 \sdr_dq_10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 282 \sdr_cke__pad__o + wire output 255 \sdr_dq_10__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 128 \sdr_clock__core__o + wire output 256 \sdr_dq_11__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 281 \sdr_clock__pad__o + wire input 126 \sdr_dq_11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 133 \sdr_cs_n__core__o + wire input 127 \sdr_dq_11__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 286 \sdr_cs_n__pad__o + wire input 125 \sdr_dq_11__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 91 \sdr_dm_0__core__o + wire output 257 \sdr_dq_11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 244 \sdr_dm_0__pad__o + wire output 258 \sdr_dq_11__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 137 \sdr_dm_1__core__o + wire output 259 \sdr_dq_12__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 290 \sdr_dm_1__pad__o + wire input 129 \sdr_dq_12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 245 \sdr_dq_0__core__i + wire input 130 \sdr_dq_12__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 93 \sdr_dq_0__core__o + wire input 128 \sdr_dq_12__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 94 \sdr_dq_0__core__oe + wire output 260 \sdr_dq_12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 92 \sdr_dq_0__pad__i + wire output 261 \sdr_dq_12__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 246 \sdr_dq_0__pad__o + wire output 262 \sdr_dq_13__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 247 \sdr_dq_0__pad__oe + wire input 132 \sdr_dq_13__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 297 \sdr_dq_10__core__i + wire input 133 \sdr_dq_13__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 145 \sdr_dq_10__core__o + wire input 131 \sdr_dq_13__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 146 \sdr_dq_10__core__oe + wire output 263 \sdr_dq_13__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 144 \sdr_dq_10__pad__i + wire output 264 \sdr_dq_13__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 298 \sdr_dq_10__pad__o + wire output 265 \sdr_dq_14__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 299 \sdr_dq_10__pad__oe + wire input 135 \sdr_dq_14__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 300 \sdr_dq_11__core__i + wire input 136 \sdr_dq_14__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 148 \sdr_dq_11__core__o + wire input 134 \sdr_dq_14__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 149 \sdr_dq_11__core__oe + wire output 266 \sdr_dq_14__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 147 \sdr_dq_11__pad__i + wire output 267 \sdr_dq_14__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 301 \sdr_dq_11__pad__o + wire output 268 \sdr_dq_15__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 302 \sdr_dq_11__pad__oe + wire input 138 \sdr_dq_15__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 303 \sdr_dq_12__core__i + wire input 139 \sdr_dq_15__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 151 \sdr_dq_12__core__o + wire input 137 \sdr_dq_15__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 152 \sdr_dq_12__core__oe + wire output 269 \sdr_dq_15__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 150 \sdr_dq_12__pad__i + wire output 270 \sdr_dq_15__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 304 \sdr_dq_12__pad__o + wire output 204 \sdr_dq_1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 305 \sdr_dq_12__pad__oe + wire input 74 \sdr_dq_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 306 \sdr_dq_13__core__i + wire input 75 \sdr_dq_1__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 154 \sdr_dq_13__core__o + wire input 73 \sdr_dq_1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 155 \sdr_dq_13__core__oe + wire output 205 \sdr_dq_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 153 \sdr_dq_13__pad__i + wire output 206 \sdr_dq_1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 307 \sdr_dq_13__pad__o + wire output 207 \sdr_dq_2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 308 \sdr_dq_13__pad__oe + wire input 77 \sdr_dq_2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 309 \sdr_dq_14__core__i + wire input 78 \sdr_dq_2__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 157 \sdr_dq_14__core__o + wire input 76 \sdr_dq_2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 158 \sdr_dq_14__core__oe + wire output 208 \sdr_dq_2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 156 \sdr_dq_14__pad__i + wire output 209 \sdr_dq_2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 310 \sdr_dq_14__pad__o + wire output 210 \sdr_dq_3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 311 \sdr_dq_14__pad__oe + wire input 80 \sdr_dq_3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 312 \sdr_dq_15__core__i + wire input 81 \sdr_dq_3__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 160 \sdr_dq_15__core__o + wire input 79 \sdr_dq_3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 161 \sdr_dq_15__core__oe + wire output 211 \sdr_dq_3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 159 \sdr_dq_15__pad__i + wire output 212 \sdr_dq_3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 313 \sdr_dq_15__pad__o + wire output 213 \sdr_dq_4__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 314 \sdr_dq_15__pad__oe + wire input 83 \sdr_dq_4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 248 \sdr_dq_1__core__i + wire input 84 \sdr_dq_4__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 96 \sdr_dq_1__core__o + wire input 82 \sdr_dq_4__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 97 \sdr_dq_1__core__oe + wire output 214 \sdr_dq_4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 95 \sdr_dq_1__pad__i + wire output 215 \sdr_dq_4__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 249 \sdr_dq_1__pad__o + wire output 216 \sdr_dq_5__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 250 \sdr_dq_1__pad__oe + wire input 86 \sdr_dq_5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 251 \sdr_dq_2__core__i + wire input 87 \sdr_dq_5__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 99 \sdr_dq_2__core__o + wire input 85 \sdr_dq_5__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 100 \sdr_dq_2__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 98 \sdr_dq_2__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 252 \sdr_dq_2__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 253 \sdr_dq_2__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 254 \sdr_dq_3__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 102 \sdr_dq_3__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 103 \sdr_dq_3__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 101 \sdr_dq_3__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 255 \sdr_dq_3__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 256 \sdr_dq_3__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 257 \sdr_dq_4__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 105 \sdr_dq_4__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 106 \sdr_dq_4__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 104 \sdr_dq_4__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 258 \sdr_dq_4__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 259 \sdr_dq_4__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 260 \sdr_dq_5__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 108 \sdr_dq_5__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 109 \sdr_dq_5__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 107 \sdr_dq_5__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 261 \sdr_dq_5__pad__o + wire output 217 \sdr_dq_5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 262 \sdr_dq_5__pad__oe + wire output 218 \sdr_dq_5__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 263 \sdr_dq_6__core__i + wire output 219 \sdr_dq_6__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 111 \sdr_dq_6__core__o + wire input 89 \sdr_dq_6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 112 \sdr_dq_6__core__oe + wire input 90 \sdr_dq_6__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 110 \sdr_dq_6__pad__i + wire input 88 \sdr_dq_6__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 264 \sdr_dq_6__pad__o + wire output 220 \sdr_dq_6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 265 \sdr_dq_6__pad__oe + wire output 221 \sdr_dq_6__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 266 \sdr_dq_7__core__i + wire output 222 \sdr_dq_7__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 114 \sdr_dq_7__core__o + wire input 92 \sdr_dq_7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 115 \sdr_dq_7__core__oe + wire input 93 \sdr_dq_7__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 113 \sdr_dq_7__pad__i + wire input 91 \sdr_dq_7__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 267 \sdr_dq_7__pad__o + wire output 223 \sdr_dq_7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 268 \sdr_dq_7__pad__oe + wire output 224 \sdr_dq_7__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 291 \sdr_dq_8__core__i + wire output 247 \sdr_dq_8__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 139 \sdr_dq_8__core__o + wire input 117 \sdr_dq_8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 140 \sdr_dq_8__core__oe + wire input 118 \sdr_dq_8__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 138 \sdr_dq_8__pad__i + wire input 116 \sdr_dq_8__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 292 \sdr_dq_8__pad__o + wire output 248 \sdr_dq_8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 293 \sdr_dq_8__pad__oe + wire output 249 \sdr_dq_8__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 294 \sdr_dq_9__core__i + wire output 250 \sdr_dq_9__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 142 \sdr_dq_9__core__o + wire input 120 \sdr_dq_9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 143 \sdr_dq_9__core__oe + wire input 121 \sdr_dq_9__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 141 \sdr_dq_9__pad__i + wire input 119 \sdr_dq_9__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 295 \sdr_dq_9__pad__o + wire output 251 \sdr_dq_9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 296 \sdr_dq_9__pad__oe + wire output 252 \sdr_dq_9__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 130 \sdr_ras_n__core__o + wire input 108 \sdr_ras_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 283 \sdr_ras_n__pad__o + wire output 239 \sdr_ras_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 132 \sdr_we_n__core__o + wire input 110 \sdr_we_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 285 \sdr_we_n__pad__o + wire output 241 \sdr_we_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" wire width 3 \sr0__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:80" @@ -219839,7 +220449,7 @@ module \jtag attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:95" wire \wb_sram_en$next attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:761" - cell $add $add$libresoc.v:139216$5900 + cell $add $add$libresoc.v:140076$5882 parameter \A_SIGNED 0 parameter \A_WIDTH 29 parameter \B_SIGNED 0 @@ -219847,10 +220457,10 @@ module \jtag parameter \Y_WIDTH 30 connect \A \jtag_wb__adr connect \B 1'1 - connect \Y $add$libresoc.v:139216$5900_Y + connect \Y $add$libresoc.v:140076$5882_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:786" - cell $add $add$libresoc.v:139217$5901 + cell $add $add$libresoc.v:140077$5883 parameter \A_SIGNED 0 parameter \A_WIDTH 29 parameter \B_SIGNED 0 @@ -219858,10 +220468,10 @@ module \jtag parameter \Y_WIDTH 30 connect \A \jtag_wb__adr connect \B 1'1 - connect \Y $add$libresoc.v:139217$5901_Y + connect \Y $add$libresoc.v:140077$5883_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:494" - cell $add $add$libresoc.v:139224$5909 + cell $add $add$libresoc.v:140084$5891 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -219869,10 +220479,10 @@ module \jtag parameter \Y_WIDTH 5 connect \A \dmi0__addr_i connect \B 1'1 - connect \Y $add$libresoc.v:139224$5909_Y + connect \Y $add$libresoc.v:140084$5891_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:518" - cell $add $add$libresoc.v:139225$5910 + cell $add $add$libresoc.v:140085$5892 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -219880,10 +220490,10 @@ module \jtag parameter \Y_WIDTH 5 connect \A \dmi0__addr_i connect \B 1'1 - connect \Y $add$libresoc.v:139225$5910_Y + connect \Y $add$libresoc.v:140085$5892_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:400" - cell $and $and$libresoc.v:139042$5726 + cell $and $and$libresoc.v:139926$5732 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -219891,10 +220501,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$15 connect \B \_fsm_capture - connect \Y $and$libresoc.v:139042$5726_Y + connect \Y $and$libresoc.v:139926$5732_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $and $and$libresoc.v:139109$5793 + cell $and $and$libresoc.v:139993$5799 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -219902,10 +220512,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_fsm_isdr connect \B \$27 - connect \Y $and$libresoc.v:139109$5793_Y + connect \Y $and$libresoc.v:139993$5799_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:402" - cell $and $and$libresoc.v:139120$5804 + cell $and $and$libresoc.v:140004$5810 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -219913,307 +220523,307 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$29 connect \B \_fsm_shift - connect \Y $and$libresoc.v:139120$5804_Y + connect \Y $and$libresoc.v:140004$5810_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $and $and$libresoc.v:139146$5830 + cell $and $and$libresoc.v:140006$5812 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \_fsm_isdr - connect \B \$363 - connect \Y $and$libresoc.v:139146$5830_Y + connect \B \$319 + connect \Y $and$libresoc.v:140006$5812_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:139149$5833 + cell $and $and$libresoc.v:140009$5815 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$369 + connect \A \$325 connect \B \_fsm_capture - connect \Y $and$libresoc.v:139149$5833_Y + connect \Y $and$libresoc.v:140009$5815_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:139151$5835 + cell $and $and$libresoc.v:140011$5817 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$373 + connect \A \$329 connect \B \_fsm_shift - connect \Y $and$libresoc.v:139151$5835_Y + connect \Y $and$libresoc.v:140011$5817_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:139154$5838 + cell $and $and$libresoc.v:140013$5819 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$377 + connect \A \$333 connect \B \_fsm_update - connect \Y $and$libresoc.v:139154$5838_Y + connect \Y $and$libresoc.v:140013$5819_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:139156$5840 + cell $and $and$libresoc.v:140016$5822 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sr0_update_core_prev - connect \B \$381 - connect \Y $and$libresoc.v:139156$5840_Y + connect \B \$337 + connect \Y $and$libresoc.v:140016$5822_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:139159$5843 + cell $and $and$libresoc.v:140019$5825 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$387 + connect \A \$343 connect \B \_fsm_capture - connect \Y $and$libresoc.v:139159$5843_Y + connect \Y $and$libresoc.v:140019$5825_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:139161$5845 + cell $and $and$libresoc.v:140021$5827 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$391 + connect \A \$347 connect \B \_fsm_shift - connect \Y $and$libresoc.v:139161$5845_Y + connect \Y $and$libresoc.v:140021$5827_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:139163$5847 + cell $and $and$libresoc.v:140023$5829 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$395 + connect \A \$351 connect \B \_fsm_update - connect \Y $and$libresoc.v:139163$5847_Y + connect \Y $and$libresoc.v:140023$5829_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:139167$5851 + cell $and $and$libresoc.v:140025$5831 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_update_core_prev - connect \B \$399 - connect \Y $and$libresoc.v:139167$5851_Y + connect \B \$355 + connect \Y $and$libresoc.v:140025$5831_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:139171$5855 + cell $and $and$libresoc.v:140030$5836 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$407 + connect \A \$363 connect \B \_fsm_capture - connect \Y $and$libresoc.v:139171$5855_Y + connect \Y $and$libresoc.v:140030$5836_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:139173$5857 + cell $and $and$libresoc.v:140032$5838 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$411 + connect \A \$367 connect \B \_fsm_shift - connect \Y $and$libresoc.v:139173$5857_Y + connect \Y $and$libresoc.v:140032$5838_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:139175$5859 + cell $and $and$libresoc.v:140034$5840 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$415 + connect \A \$371 connect \B \_fsm_update - connect \Y $and$libresoc.v:139175$5859_Y + connect \Y $and$libresoc.v:140034$5840_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:139178$5862 + cell $and $and$libresoc.v:140036$5842 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_update_core_prev - connect \B \$419 - connect \Y $and$libresoc.v:139178$5862_Y + connect \B \$375 + connect \Y $and$libresoc.v:140036$5842_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:139181$5865 + cell $and $and$libresoc.v:140040$5846 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$425 + connect \A \$381 connect \B \_fsm_capture - connect \Y $and$libresoc.v:139181$5865_Y + connect \Y $and$libresoc.v:140040$5846_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:139183$5867 + cell $and $and$libresoc.v:140042$5848 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$429 + connect \A \$385 connect \B \_fsm_shift - connect \Y $and$libresoc.v:139183$5867_Y + connect \Y $and$libresoc.v:140042$5848_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:139185$5869 + cell $and $and$libresoc.v:140044$5850 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$433 + connect \A \$389 connect \B \_fsm_update - connect \Y $and$libresoc.v:139185$5869_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $and $and$libresoc.v:139187$5871 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \_fsm_isdr - connect \B \$41 - connect \Y $and$libresoc.v:139187$5871_Y + connect \Y $and$libresoc.v:140044$5850_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:139188$5872 + cell $and $and$libresoc.v:140046$5852 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_update_core_prev - connect \B \$437 - connect \Y $and$libresoc.v:139188$5872_Y + connect \B \$393 + connect \Y $and$libresoc.v:140046$5852_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:139192$5876 + cell $and $and$libresoc.v:140052$5858 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$445 + connect \A \$401 connect \B \_fsm_capture - connect \Y $and$libresoc.v:139192$5876_Y + connect \Y $and$libresoc.v:140052$5858_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:139194$5878 + cell $and $and$libresoc.v:140054$5860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$449 + connect \A \$405 connect \B \_fsm_shift - connect \Y $and$libresoc.v:139194$5878_Y + connect \Y $and$libresoc.v:140054$5860_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:139196$5880 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \$453 - connect \B \_fsm_update - connect \Y $and$libresoc.v:139196$5880_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" - cell $and $and$libresoc.v:139198$5882 + cell $and $and$libresoc.v:140056$5862 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$43 + connect \A \$409 connect \B \_fsm_update - connect \Y $and$libresoc.v:139198$5882_Y + connect \Y $and$libresoc.v:140056$5862_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:139199$5883 + cell $and $and$libresoc.v:140058$5864 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi0_datasr_update_core_prev - connect \B \$457 - connect \Y $and$libresoc.v:139199$5883_Y + connect \B \$413 + connect \Y $and$libresoc.v:140058$5864_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $and $and$libresoc.v:139202$5886 + cell $and $and$libresoc.v:140062$5868 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$463 + connect \A \$419 connect \B \_fsm_capture - connect \Y $and$libresoc.v:139202$5886_Y + connect \Y $and$libresoc.v:140062$5868_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $and $and$libresoc.v:139204$5888 + cell $and $and$libresoc.v:140064$5870 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$467 + connect \A \$423 connect \B \_fsm_shift - connect \Y $and$libresoc.v:139204$5888_Y + connect \Y $and$libresoc.v:140064$5870_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $and $and$libresoc.v:139206$5890 + cell $and $and$libresoc.v:140066$5872 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$471 + connect \A \$427 connect \B \_fsm_update - connect \Y $and$libresoc.v:139206$5890_Y + connect \Y $and$libresoc.v:140066$5872_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $and $and$libresoc.v:139208$5892 + cell $and $and$libresoc.v:140068$5874 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sr5_update_core_prev - connect \B \$475 - connect \Y $and$libresoc.v:139208$5892_Y + connect \B \$431 + connect \Y $and$libresoc.v:140068$5874_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" + cell $and $and$libresoc.v:140071$5877 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_fsm_isdr + connect \B \$41 + connect \Y $and$libresoc.v:140071$5877_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:403" + cell $and $and$libresoc.v:140081$5888 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$43 + connect \B \_fsm_update + connect \Y $and$libresoc.v:140081$5888_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $and $and$libresoc.v:139241$5926 + cell $and $and$libresoc.v:140103$5910 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220221,10 +220831,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_fsm_isdr connect \B \$5 - connect \Y $and$libresoc.v:139241$5926_Y + connect \Y $and$libresoc.v:140103$5910_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:378" - cell $eq $eq$libresoc.v:138998$5682 + cell $eq $eq$libresoc.v:139882$5688 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220232,10 +220842,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1111 - connect \Y $eq$libresoc.v:138998$5682_Y + connect \Y $eq$libresoc.v:139882$5688_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:139009$5693 + cell $eq $eq$libresoc.v:139893$5699 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220243,10 +220853,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:139009$5693_Y + connect \Y $eq$libresoc.v:139893$5699_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:139020$5704 + cell $eq $eq$libresoc.v:139904$5710 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220254,10 +220864,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:139020$5704_Y + connect \Y $eq$libresoc.v:139904$5710_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $eq $eq$libresoc.v:139053$5737 + cell $eq $eq$libresoc.v:139937$5743 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220265,10 +220875,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'1 - connect \Y $eq$libresoc.v:139053$5737_Y + connect \Y $eq$libresoc.v:139937$5743_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:139054$5738 + cell $eq $eq$libresoc.v:139938$5744 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220276,10 +220886,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:139054$5738_Y + connect \Y $eq$libresoc.v:139938$5744_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:139065$5749 + cell $eq $eq$libresoc.v:139949$5755 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220287,10 +220897,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:139065$5749_Y + connect \Y $eq$libresoc.v:139949$5755_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" - cell $eq $eq$libresoc.v:139087$5771 + cell $eq $eq$libresoc.v:139971$5777 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220298,10 +220908,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:139087$5771_Y + connect \Y $eq$libresoc.v:139971$5777_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:139131$5815 + cell $eq $eq$libresoc.v:140000$5806 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220309,21 +220919,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 1'0 - connect \Y $eq$libresoc.v:139131$5815_Y + connect \Y $eq$libresoc.v:140000$5806_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:139140$5824 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 1'0 - connect \Y $eq$libresoc.v:139140$5824_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:139141$5825 + cell $eq $eq$libresoc.v:140001$5807 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220331,21 +220930,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:139141$5825_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $eq $eq$libresoc.v:139142$5826 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 2'10 - connect \Y $eq$libresoc.v:139142$5826_Y + connect \Y $eq$libresoc.v:140001$5807_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" - cell $eq $eq$libresoc.v:139144$5828 + cell $eq $eq$libresoc.v:140003$5809 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220353,10 +220941,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:139144$5828_Y + connect \Y $eq$libresoc.v:140003$5809_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:139147$5831 + cell $eq $eq$libresoc.v:140007$5813 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220364,32 +220952,32 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 3'100 - connect \Y $eq$libresoc.v:139147$5831_Y + connect \Y $eq$libresoc.v:140007$5813_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:139157$5841 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $eq $eq$libresoc.v:140015$5821 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 connect \A \_irblock_ir - connect \B 3'101 - connect \Y $eq$libresoc.v:139157$5841_Y + connect \B 1'0 + connect \Y $eq$libresoc.v:140015$5821_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $eq $eq$libresoc.v:139164$5848 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + cell $eq $eq$libresoc.v:140017$5823 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 connect \A \_irblock_ir - connect \B 4'1111 - connect \Y $eq$libresoc.v:139164$5848_Y + connect \B 3'101 + connect \Y $eq$libresoc.v:140017$5823_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" - cell $eq $eq$libresoc.v:139165$5849 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" + cell $eq $eq$libresoc.v:140026$5832 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220397,10 +220985,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 2'10 - connect \Y $eq$libresoc.v:139165$5849_Y + connect \Y $eq$libresoc.v:140026$5832_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:139168$5852 + cell $eq $eq$libresoc.v:140027$5833 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220408,10 +220996,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 3'110 - connect \Y $eq$libresoc.v:139168$5852_Y + connect \Y $eq$libresoc.v:140027$5833_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:139169$5853 + cell $eq $eq$libresoc.v:140028$5834 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220419,10 +221007,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 3'111 - connect \Y $eq$libresoc.v:139169$5853_Y + connect \Y $eq$libresoc.v:140028$5834_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:139179$5863 + cell $eq $eq$libresoc.v:140038$5844 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220430,10 +221018,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1000 - connect \Y $eq$libresoc.v:139179$5863_Y + connect \Y $eq$libresoc.v:140038$5844_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:139189$5873 + cell $eq $eq$libresoc.v:140047$5853 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -220441,43 +221029,54 @@ module \jtag parameter \Y_WIDTH 1 connect \A \_irblock_ir connect \B 4'1001 - connect \Y $eq$libresoc.v:139189$5873_Y + connect \Y $eq$libresoc.v:140047$5853_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:139190$5874 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" + cell $eq $eq$libresoc.v:140048$5854 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \_irblock_ir - connect \B 4'1010 - connect \Y $eq$libresoc.v:139190$5874_Y + connect \B 4'1111 + connect \Y $eq$libresoc.v:140048$5854_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:397" + cell $eq $eq$libresoc.v:140049$5855 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 2'10 + connect \Y $eq$libresoc.v:140049$5855_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" - cell $eq $eq$libresoc.v:139200$5884 + cell $eq $eq$libresoc.v:140050$5856 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \_irblock_ir - connect \B 4'1011 - connect \Y $eq$libresoc.v:139200$5884_Y + connect \B 4'1010 + connect \Y $eq$libresoc.v:140050$5856_Y end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" - cell $eq $eq$libresoc.v:139209$5893 + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:650" + cell $eq $eq$libresoc.v:140059$5865 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 connect \A \_irblock_ir - connect \B 1'0 - connect \Y $eq$libresoc.v:139209$5893_Y + connect \B 4'1011 + connect \Y $eq$libresoc.v:140059$5865_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" - cell $eq $eq$libresoc.v:139210$5894 + cell $eq $eq$libresoc.v:140069$5875 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -220485,10 +221084,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 1'0 - connect \Y $eq$libresoc.v:139210$5894_Y + connect \Y $eq$libresoc.v:140069$5875_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - cell $eq $eq$libresoc.v:139212$5896 + cell $eq $eq$libresoc.v:140072$5878 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -220496,10 +221095,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 1'1 - connect \Y $eq$libresoc.v:139212$5896_Y + connect \Y $eq$libresoc.v:140072$5878_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - cell $eq $eq$libresoc.v:139213$5897 + cell $eq $eq$libresoc.v:140073$5879 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -220507,10 +221106,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 2'10 - connect \Y $eq$libresoc.v:139213$5897_Y + connect \Y $eq$libresoc.v:140073$5879_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:792" - cell $eq $eq$libresoc.v:139215$5899 + cell $eq $eq$libresoc.v:140075$5881 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -220518,62 +221117,73 @@ module \jtag parameter \Y_WIDTH 1 connect \A \fsm_state connect \B 2'10 - connect \Y $eq$libresoc.v:139215$5899_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405" - cell $eq $eq$libresoc.v:139219$5904 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \_irblock_ir - connect \B 1'0 - connect \Y $eq$libresoc.v:139219$5904_Y + connect \Y $eq$libresoc.v:140075$5881_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - cell $eq $eq$libresoc.v:139220$5905 + cell $eq $eq$libresoc.v:140079$5886 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \fsm_state$499 + connect \A \fsm_state$455 connect \B 1'1 - connect \Y $eq$libresoc.v:139220$5905_Y + connect \Y $eq$libresoc.v:140079$5886_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - cell $eq $eq$libresoc.v:139221$5906 + cell $eq $eq$libresoc.v:140080$5887 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \fsm_state$499 + connect \A \fsm_state$455 connect \B 2'10 - connect \Y $eq$libresoc.v:139221$5906_Y + connect \Y $eq$libresoc.v:140080$5887_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:524" - cell $eq $eq$libresoc.v:139223$5908 + cell $eq $eq$libresoc.v:140083$5890 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \fsm_state$499 + connect \A \fsm_state$455 connect \B 2'10 - connect \Y $eq$libresoc.v:139223$5908_Y + connect \Y $eq$libresoc.v:140083$5890_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:404" + cell $eq $eq$libresoc.v:140086$5893 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 1'0 + connect \Y $eq$libresoc.v:140086$5893_Y + end + attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:405" + cell $eq $eq$libresoc.v:140087$5894 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \_irblock_ir + connect \B 1'0 + connect \Y $eq$libresoc.v:140087$5894_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - cell $pos $extend$libresoc.v:139218$5902 + cell $pos $extend$libresoc.v:140078$5884 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \dmi0__addr_i - connect \Y $extend$libresoc.v:139218$5902_Y + connect \Y $extend$libresoc.v:140078$5884_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:139148$5832 + cell $ne $ne$libresoc.v:140008$5814 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220581,10 +221191,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr0_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139148$5832_Y + connect \Y $ne$libresoc.v:140008$5814_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:139150$5834 + cell $ne $ne$libresoc.v:140010$5816 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220592,10 +221202,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr0_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139150$5834_Y + connect \Y $ne$libresoc.v:140010$5816_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:139152$5836 + cell $ne $ne$libresoc.v:140012$5818 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220603,10 +221213,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr0_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139152$5836_Y + connect \Y $ne$libresoc.v:140012$5818_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:139158$5842 + cell $ne $ne$libresoc.v:140018$5824 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220614,10 +221224,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139158$5842_Y + connect \Y $ne$libresoc.v:140018$5824_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:139160$5844 + cell $ne $ne$libresoc.v:140020$5826 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220625,10 +221235,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139160$5844_Y + connect \Y $ne$libresoc.v:140020$5826_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:139162$5846 + cell $ne $ne$libresoc.v:140022$5828 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220636,10 +221246,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139162$5846_Y + connect \Y $ne$libresoc.v:140022$5828_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:139170$5854 + cell $ne $ne$libresoc.v:140029$5835 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -220647,10 +221257,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139170$5854_Y + connect \Y $ne$libresoc.v:140029$5835_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:139172$5856 + cell $ne $ne$libresoc.v:140031$5837 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -220658,10 +221268,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139172$5856_Y + connect \Y $ne$libresoc.v:140031$5837_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:139174$5858 + cell $ne $ne$libresoc.v:140033$5839 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -220669,10 +221279,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139174$5858_Y + connect \Y $ne$libresoc.v:140033$5839_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:139180$5864 + cell $ne $ne$libresoc.v:140039$5845 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220680,10 +221290,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139180$5864_Y + connect \Y $ne$libresoc.v:140039$5845_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:139182$5866 + cell $ne $ne$libresoc.v:140041$5847 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220691,10 +221301,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139182$5866_Y + connect \Y $ne$libresoc.v:140041$5847_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:139184$5868 + cell $ne $ne$libresoc.v:140043$5849 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220702,10 +221312,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139184$5868_Y + connect \Y $ne$libresoc.v:140043$5849_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:139191$5875 + cell $ne $ne$libresoc.v:140051$5857 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -220713,10 +221323,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139191$5875_Y + connect \Y $ne$libresoc.v:140051$5857_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:139193$5877 + cell $ne $ne$libresoc.v:140053$5859 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -220724,10 +221334,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139193$5877_Y + connect \Y $ne$libresoc.v:140053$5859_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:139195$5879 + cell $ne $ne$libresoc.v:140055$5861 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -220735,10 +221345,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \dmi0_datasr_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139195$5879_Y + connect \Y $ne$libresoc.v:140055$5861_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:651" - cell $ne $ne$libresoc.v:139201$5885 + cell $ne $ne$libresoc.v:140061$5867 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220746,10 +221356,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr5_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139201$5885_Y + connect \Y $ne$libresoc.v:140061$5867_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:652" - cell $ne $ne$libresoc.v:139203$5887 + cell $ne $ne$libresoc.v:140063$5869 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220757,10 +221367,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr5_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139203$5887_Y + connect \Y $ne$libresoc.v:140063$5869_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:653" - cell $ne $ne$libresoc.v:139205$5889 + cell $ne $ne$libresoc.v:140065$5871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220768,66 +221378,66 @@ module \jtag parameter \Y_WIDTH 1 connect \A \sr5_isir connect \B 1'0 - connect \Y $ne$libresoc.v:139205$5889_Y + connect \Y $ne$libresoc.v:140065$5871_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:139155$5839 + cell $not $not$libresoc.v:140014$5820 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sr0_update_core - connect \Y $not$libresoc.v:139155$5839_Y + connect \Y $not$libresoc.v:140014$5820_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:139166$5850 + cell $not $not$libresoc.v:140024$5830 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \jtag_wb_addrsr_update_core - connect \Y $not$libresoc.v:139166$5850_Y + connect \Y $not$libresoc.v:140024$5830_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:139177$5861 + cell $not $not$libresoc.v:140035$5841 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \jtag_wb_datasr_update_core - connect \Y $not$libresoc.v:139177$5861_Y + connect \Y $not$libresoc.v:140035$5841_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:139186$5870 + cell $not $not$libresoc.v:140045$5851 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi0_addrsr_update_core - connect \Y $not$libresoc.v:139186$5870_Y + connect \Y $not$libresoc.v:140045$5851_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:139197$5881 + cell $not $not$libresoc.v:140057$5863 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dmi0_datasr_update_core - connect \Y $not$libresoc.v:139197$5881_Y + connect \Y $not$libresoc.v:140057$5863_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - cell $not $not$libresoc.v:139207$5891 + cell $not $not$libresoc.v:140067$5873 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sr5_update_core - connect \Y $not$libresoc.v:139207$5891_Y + connect \Y $not$libresoc.v:140067$5873_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:790" - cell $not $not$libresoc.v:139211$5895 + cell $not $not$libresoc.v:140070$5876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$480 - connect \Y $not$libresoc.v:139211$5895_Y + connect \A \$436 + connect \Y $not$libresoc.v:140070$5876_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:139031$5715 + cell $or $or$libresoc.v:139915$5721 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220835,10 +221445,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$11 connect \B \$13 - connect \Y $or$libresoc.v:139031$5715_Y + connect \Y $or$libresoc.v:139915$5721_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:139076$5760 + cell $or $or$libresoc.v:139960$5766 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220846,10 +221456,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$19 connect \B \$21 - connect \Y $or$libresoc.v:139076$5760_Y + connect \Y $or$libresoc.v:139960$5766_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $or $or$libresoc.v:139098$5782 + cell $or $or$libresoc.v:139982$5788 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220857,32 +221467,32 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$23 connect \B \$25 - connect \Y $or$libresoc.v:139098$5782_Y + connect \Y $or$libresoc.v:139982$5788_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:139143$5827 + cell $or $or$libresoc.v:140002$5808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$355 - connect \B \$357 - connect \Y $or$libresoc.v:139143$5827_Y + connect \A \$311 + connect \B \$313 + connect \Y $or$libresoc.v:140002$5808_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $or $or$libresoc.v:139145$5829 + cell $or $or$libresoc.v:140005$5811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$359 - connect \B \$361 - connect \Y $or$libresoc.v:139145$5829_Y + connect \A \$315 + connect \B \$317 + connect \Y $or$libresoc.v:140005$5811_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:396" - cell $or $or$libresoc.v:139153$5837 + cell $or $or$libresoc.v:140037$5843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220890,10 +221500,10 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$33 connect \B \$35 - connect \Y $or$libresoc.v:139153$5837_Y + connect \Y $or$libresoc.v:140037$5843_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:398" - cell $or $or$libresoc.v:139176$5860 + cell $or $or$libresoc.v:140060$5866 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220901,32 +221511,32 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$37 connect \B \$39 - connect \Y $or$libresoc.v:139176$5860_Y + connect \Y $or$libresoc.v:140060$5866_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:791" - cell $or $or$libresoc.v:139214$5898 + cell $or $or$libresoc.v:140074$5880 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$483 - connect \B \$485 - connect \Y $or$libresoc.v:139214$5898_Y + connect \A \$439 + connect \B \$441 + connect \Y $or$libresoc.v:140074$5880_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:523" - cell $or $or$libresoc.v:139222$5907 + cell $or $or$libresoc.v:140082$5889 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \$500 - connect \B \$502 - connect \Y $or$libresoc.v:139222$5907_Y + connect \A \$456 + connect \B \$458 + connect \Y $or$libresoc.v:140082$5889_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:377" - cell $or $or$libresoc.v:139230$5915 + cell $or $or$libresoc.v:140092$5899 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -220934,1234 +221544,1058 @@ module \jtag parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $or$libresoc.v:139230$5915_Y + connect \Y $or$libresoc.v:140092$5899_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" - cell $pos $pos$libresoc.v:139218$5903 + cell $pos $pos$libresoc.v:140078$5885 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:139218$5902_Y - connect \Y $pos$libresoc.v:139218$5903_Y + connect \A $extend$libresoc.v:140078$5884_Y + connect \Y $pos$libresoc.v:140078$5885_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:138999$5683 + cell $mux $ternary$libresoc.v:139883$5689 parameter \WIDTH 1 connect \A \gpio_e15__pad__i connect \B \io_bd [24] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:138999$5683_Y + connect \Y $ternary$libresoc.v:139883$5689_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139000$5684 + cell $mux $ternary$libresoc.v:139884$5690 parameter \WIDTH 1 connect \A \gpio_e15__core__o connect \B \io_bd [25] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139000$5684_Y + connect \Y $ternary$libresoc.v:139884$5690_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139001$5685 + cell $mux $ternary$libresoc.v:139885$5691 parameter \WIDTH 1 connect \A \gpio_e15__core__oe connect \B \io_bd [26] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139001$5685_Y + connect \Y $ternary$libresoc.v:139885$5691_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139002$5686 + cell $mux $ternary$libresoc.v:139886$5692 parameter \WIDTH 1 connect \A \gpio_s0__pad__i connect \B \io_bd [27] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139002$5686_Y + connect \Y $ternary$libresoc.v:139886$5692_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139003$5687 + cell $mux $ternary$libresoc.v:139887$5693 parameter \WIDTH 1 connect \A \gpio_s0__core__o connect \B \io_bd [28] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139003$5687_Y + connect \Y $ternary$libresoc.v:139887$5693_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139004$5688 + cell $mux $ternary$libresoc.v:139888$5694 parameter \WIDTH 1 connect \A \gpio_s0__core__oe connect \B \io_bd [29] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139004$5688_Y + connect \Y $ternary$libresoc.v:139888$5694_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139005$5689 + cell $mux $ternary$libresoc.v:139889$5695 parameter \WIDTH 1 connect \A \gpio_s1__pad__i connect \B \io_bd [30] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139005$5689_Y + connect \Y $ternary$libresoc.v:139889$5695_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139006$5690 + cell $mux $ternary$libresoc.v:139890$5696 parameter \WIDTH 1 connect \A \gpio_s1__core__o connect \B \io_bd [31] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139006$5690_Y + connect \Y $ternary$libresoc.v:139890$5696_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139007$5691 + cell $mux $ternary$libresoc.v:139891$5697 parameter \WIDTH 1 connect \A \gpio_s1__core__oe connect \B \io_bd [32] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139007$5691_Y + connect \Y $ternary$libresoc.v:139891$5697_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139008$5692 + cell $mux $ternary$libresoc.v:139892$5698 parameter \WIDTH 1 connect \A \gpio_s2__pad__i connect \B \io_bd [33] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139008$5692_Y + connect \Y $ternary$libresoc.v:139892$5698_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139010$5694 + cell $mux $ternary$libresoc.v:139894$5700 parameter \WIDTH 1 connect \A \gpio_s2__core__o connect \B \io_bd [34] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139010$5694_Y + connect \Y $ternary$libresoc.v:139894$5700_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139011$5695 + cell $mux $ternary$libresoc.v:139895$5701 parameter \WIDTH 1 connect \A \gpio_s2__core__oe connect \B \io_bd [35] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139011$5695_Y + connect \Y $ternary$libresoc.v:139895$5701_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139012$5696 + cell $mux $ternary$libresoc.v:139896$5702 parameter \WIDTH 1 connect \A \gpio_s3__pad__i connect \B \io_bd [36] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139012$5696_Y + connect \Y $ternary$libresoc.v:139896$5702_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139013$5697 + cell $mux $ternary$libresoc.v:139897$5703 parameter \WIDTH 1 connect \A \gpio_s3__core__o connect \B \io_bd [37] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139013$5697_Y + connect \Y $ternary$libresoc.v:139897$5703_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139014$5698 + cell $mux $ternary$libresoc.v:139898$5704 parameter \WIDTH 1 connect \A \gpio_s3__core__oe connect \B \io_bd [38] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139014$5698_Y + connect \Y $ternary$libresoc.v:139898$5704_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139015$5699 + cell $mux $ternary$libresoc.v:139899$5705 parameter \WIDTH 1 connect \A \gpio_s4__pad__i connect \B \io_bd [39] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139015$5699_Y + connect \Y $ternary$libresoc.v:139899$5705_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139016$5700 + cell $mux $ternary$libresoc.v:139900$5706 parameter \WIDTH 1 connect \A \gpio_s4__core__o connect \B \io_bd [40] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139016$5700_Y + connect \Y $ternary$libresoc.v:139900$5706_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139017$5701 + cell $mux $ternary$libresoc.v:139901$5707 parameter \WIDTH 1 connect \A \gpio_s4__core__oe connect \B \io_bd [41] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139017$5701_Y + connect \Y $ternary$libresoc.v:139901$5707_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139018$5702 + cell $mux $ternary$libresoc.v:139902$5708 parameter \WIDTH 1 connect \A \gpio_s5__pad__i connect \B \io_bd [42] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139018$5702_Y + connect \Y $ternary$libresoc.v:139902$5708_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139019$5703 + cell $mux $ternary$libresoc.v:139903$5709 parameter \WIDTH 1 connect \A \gpio_s5__core__o connect \B \io_bd [43] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139019$5703_Y + connect \Y $ternary$libresoc.v:139903$5709_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139021$5705 + cell $mux $ternary$libresoc.v:139905$5711 parameter \WIDTH 1 connect \A \gpio_s5__core__oe connect \B \io_bd [44] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139021$5705_Y + connect \Y $ternary$libresoc.v:139905$5711_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139022$5706 + cell $mux $ternary$libresoc.v:139906$5712 parameter \WIDTH 1 connect \A \gpio_s6__pad__i connect \B \io_bd [45] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139022$5706_Y + connect \Y $ternary$libresoc.v:139906$5712_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139023$5707 + cell $mux $ternary$libresoc.v:139907$5713 parameter \WIDTH 1 connect \A \gpio_s6__core__o connect \B \io_bd [46] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139023$5707_Y + connect \Y $ternary$libresoc.v:139907$5713_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139024$5708 + cell $mux $ternary$libresoc.v:139908$5714 parameter \WIDTH 1 connect \A \gpio_s6__core__oe connect \B \io_bd [47] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139024$5708_Y + connect \Y $ternary$libresoc.v:139908$5714_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139025$5709 + cell $mux $ternary$libresoc.v:139909$5715 parameter \WIDTH 1 connect \A \gpio_s7__pad__i connect \B \io_bd [48] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139025$5709_Y + connect \Y $ternary$libresoc.v:139909$5715_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139026$5710 + cell $mux $ternary$libresoc.v:139910$5716 parameter \WIDTH 1 connect \A \gpio_s7__core__o connect \B \io_bd [49] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139026$5710_Y + connect \Y $ternary$libresoc.v:139910$5716_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139027$5711 + cell $mux $ternary$libresoc.v:139911$5717 parameter \WIDTH 1 connect \A \gpio_s7__core__oe connect \B \io_bd [50] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139027$5711_Y + connect \Y $ternary$libresoc.v:139911$5717_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139028$5712 + cell $mux $ternary$libresoc.v:139912$5718 parameter \WIDTH 1 connect \A \mspi0_clk__core__o connect \B \io_bd [51] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139028$5712_Y + connect \Y $ternary$libresoc.v:139912$5718_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139029$5713 + cell $mux $ternary$libresoc.v:139913$5719 parameter \WIDTH 1 connect \A \mspi0_cs_n__core__o connect \B \io_bd [52] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139029$5713_Y + connect \Y $ternary$libresoc.v:139913$5719_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139030$5714 + cell $mux $ternary$libresoc.v:139914$5720 parameter \WIDTH 1 connect \A \mspi0_mosi__core__o connect \B \io_bd [53] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139030$5714_Y + connect \Y $ternary$libresoc.v:139914$5720_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:139032$5716 + cell $mux $ternary$libresoc.v:139916$5722 parameter \WIDTH 1 connect \A \mspi0_miso__pad__i connect \B \io_bd [54] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139032$5716_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139033$5717 - parameter \WIDTH 1 - connect \A \mspi1_clk__core__o - connect \B \io_bd [55] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139033$5717_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139034$5718 - parameter \WIDTH 1 - connect \A \mspi1_cs_n__core__o - connect \B \io_bd [56] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139034$5718_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139035$5719 - parameter \WIDTH 1 - connect \A \mspi1_mosi__core__o - connect \B \io_bd [57] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139035$5719_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:139036$5720 - parameter \WIDTH 1 - connect \A \mspi1_miso__pad__i - connect \B \io_bd [58] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139036$5720_Y + connect \Y $ternary$libresoc.v:139916$5722_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139037$5721 + cell $mux $ternary$libresoc.v:139917$5723 parameter \WIDTH 1 connect \A \mtwi_sda__pad__i - connect \B \io_bd [59] + connect \B \io_bd [55] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139037$5721_Y + connect \Y $ternary$libresoc.v:139917$5723_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139038$5722 + cell $mux $ternary$libresoc.v:139918$5724 parameter \WIDTH 1 connect \A \mtwi_sda__core__o - connect \B \io_bd [60] + connect \B \io_bd [56] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139038$5722_Y + connect \Y $ternary$libresoc.v:139918$5724_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139039$5723 + cell $mux $ternary$libresoc.v:139919$5725 parameter \WIDTH 1 connect \A \mtwi_sda__core__oe - connect \B \io_bd [61] + connect \B \io_bd [57] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139039$5723_Y + connect \Y $ternary$libresoc.v:139919$5725_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139040$5724 + cell $mux $ternary$libresoc.v:139920$5726 parameter \WIDTH 1 connect \A \mtwi_scl__core__o - connect \B \io_bd [62] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139040$5724_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139041$5725 - parameter \WIDTH 1 - connect \A \pwm_0__core__o - connect \B \io_bd [63] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139041$5725_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139043$5727 - parameter \WIDTH 1 - connect \A \pwm_1__core__o - connect \B \io_bd [64] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139043$5727_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139044$5728 - parameter \WIDTH 1 - connect \A \sd0_cmd__pad__i - connect \B \io_bd [65] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139044$5728_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139045$5729 - parameter \WIDTH 1 - connect \A \sd0_cmd__core__o - connect \B \io_bd [66] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139045$5729_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139046$5730 - parameter \WIDTH 1 - connect \A \sd0_cmd__core__oe - connect \B \io_bd [67] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139046$5730_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139047$5731 - parameter \WIDTH 1 - connect \A \sd0_clk__core__o - connect \B \io_bd [68] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139047$5731_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139048$5732 - parameter \WIDTH 1 - connect \A \sd0_data0__pad__i - connect \B \io_bd [69] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139048$5732_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139049$5733 - parameter \WIDTH 1 - connect \A \sd0_data0__core__o - connect \B \io_bd [70] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139049$5733_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139050$5734 - parameter \WIDTH 1 - connect \A \sd0_data0__core__oe - connect \B \io_bd [71] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139050$5734_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139051$5735 - parameter \WIDTH 1 - connect \A \sd0_data1__pad__i - connect \B \io_bd [72] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139051$5735_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139052$5736 - parameter \WIDTH 1 - connect \A \sd0_data1__core__o - connect \B \io_bd [73] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139052$5736_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139055$5739 - parameter \WIDTH 1 - connect \A \sd0_data1__core__oe - connect \B \io_bd [74] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139055$5739_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139056$5740 - parameter \WIDTH 1 - connect \A \sd0_data2__pad__i - connect \B \io_bd [75] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139056$5740_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139057$5741 - parameter \WIDTH 1 - connect \A \sd0_data2__core__o - connect \B \io_bd [76] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139057$5741_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139058$5742 - parameter \WIDTH 1 - connect \A \sd0_data2__core__oe - connect \B \io_bd [77] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139058$5742_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139059$5743 - parameter \WIDTH 1 - connect \A \sd0_data3__pad__i - connect \B \io_bd [78] - connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139059$5743_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139060$5744 - parameter \WIDTH 1 - connect \A \sd0_data3__core__o - connect \B \io_bd [79] - connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139060$5744_Y - end - attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139061$5745 - parameter \WIDTH 1 - connect \A \sd0_data3__core__oe - connect \B \io_bd [80] + connect \B \io_bd [58] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139061$5745_Y + connect \Y $ternary$libresoc.v:139920$5726_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139062$5746 + cell $mux $ternary$libresoc.v:139921$5727 parameter \WIDTH 1 connect \A \sdr_dm_0__core__o - connect \B \io_bd [81] + connect \B \io_bd [59] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139062$5746_Y + connect \Y $ternary$libresoc.v:139921$5727_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139063$5747 + cell $mux $ternary$libresoc.v:139922$5728 parameter \WIDTH 1 connect \A \sdr_dq_0__pad__i - connect \B \io_bd [82] + connect \B \io_bd [60] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139063$5747_Y + connect \Y $ternary$libresoc.v:139922$5728_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139064$5748 + cell $mux $ternary$libresoc.v:139923$5729 parameter \WIDTH 1 connect \A \sdr_dq_0__core__o - connect \B \io_bd [83] + connect \B \io_bd [61] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139064$5748_Y + connect \Y $ternary$libresoc.v:139923$5729_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139066$5750 + cell $mux $ternary$libresoc.v:139924$5730 parameter \WIDTH 1 connect \A \sdr_dq_0__core__oe - connect \B \io_bd [84] + connect \B \io_bd [62] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139066$5750_Y + connect \Y $ternary$libresoc.v:139924$5730_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139067$5751 + cell $mux $ternary$libresoc.v:139925$5731 parameter \WIDTH 1 connect \A \sdr_dq_1__pad__i - connect \B \io_bd [85] + connect \B \io_bd [63] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139067$5751_Y + connect \Y $ternary$libresoc.v:139925$5731_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139068$5752 + cell $mux $ternary$libresoc.v:139927$5733 parameter \WIDTH 1 connect \A \sdr_dq_1__core__o - connect \B \io_bd [86] + connect \B \io_bd [64] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139068$5752_Y + connect \Y $ternary$libresoc.v:139927$5733_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139069$5753 + cell $mux $ternary$libresoc.v:139928$5734 parameter \WIDTH 1 connect \A \sdr_dq_1__core__oe - connect \B \io_bd [87] + connect \B \io_bd [65] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139069$5753_Y + connect \Y $ternary$libresoc.v:139928$5734_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139070$5754 + cell $mux $ternary$libresoc.v:139929$5735 parameter \WIDTH 1 connect \A \sdr_dq_2__pad__i - connect \B \io_bd [88] + connect \B \io_bd [66] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139070$5754_Y + connect \Y $ternary$libresoc.v:139929$5735_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139071$5755 + cell $mux $ternary$libresoc.v:139930$5736 parameter \WIDTH 1 connect \A \sdr_dq_2__core__o - connect \B \io_bd [89] + connect \B \io_bd [67] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139071$5755_Y + connect \Y $ternary$libresoc.v:139930$5736_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139072$5756 + cell $mux $ternary$libresoc.v:139931$5737 parameter \WIDTH 1 connect \A \sdr_dq_2__core__oe - connect \B \io_bd [90] + connect \B \io_bd [68] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139072$5756_Y + connect \Y $ternary$libresoc.v:139931$5737_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139073$5757 + cell $mux $ternary$libresoc.v:139932$5738 parameter \WIDTH 1 connect \A \sdr_dq_3__pad__i - connect \B \io_bd [91] + connect \B \io_bd [69] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139073$5757_Y + connect \Y $ternary$libresoc.v:139932$5738_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139074$5758 + cell $mux $ternary$libresoc.v:139933$5739 parameter \WIDTH 1 connect \A \sdr_dq_3__core__o - connect \B \io_bd [92] + connect \B \io_bd [70] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139074$5758_Y + connect \Y $ternary$libresoc.v:139933$5739_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139075$5759 + cell $mux $ternary$libresoc.v:139934$5740 parameter \WIDTH 1 connect \A \sdr_dq_3__core__oe - connect \B \io_bd [93] + connect \B \io_bd [71] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139075$5759_Y + connect \Y $ternary$libresoc.v:139934$5740_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139077$5761 + cell $mux $ternary$libresoc.v:139935$5741 parameter \WIDTH 1 connect \A \sdr_dq_4__pad__i - connect \B \io_bd [94] + connect \B \io_bd [72] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139077$5761_Y + connect \Y $ternary$libresoc.v:139935$5741_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139078$5762 + cell $mux $ternary$libresoc.v:139936$5742 parameter \WIDTH 1 connect \A \sdr_dq_4__core__o - connect \B \io_bd [95] + connect \B \io_bd [73] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139078$5762_Y + connect \Y $ternary$libresoc.v:139936$5742_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139079$5763 + cell $mux $ternary$libresoc.v:139939$5745 parameter \WIDTH 1 connect \A \sdr_dq_4__core__oe - connect \B \io_bd [96] + connect \B \io_bd [74] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139079$5763_Y + connect \Y $ternary$libresoc.v:139939$5745_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139080$5764 + cell $mux $ternary$libresoc.v:139940$5746 parameter \WIDTH 1 connect \A \sdr_dq_5__pad__i - connect \B \io_bd [97] + connect \B \io_bd [75] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139080$5764_Y + connect \Y $ternary$libresoc.v:139940$5746_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139081$5765 + cell $mux $ternary$libresoc.v:139941$5747 parameter \WIDTH 1 connect \A \sdr_dq_5__core__o - connect \B \io_bd [98] + connect \B \io_bd [76] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139081$5765_Y + connect \Y $ternary$libresoc.v:139941$5747_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139082$5766 + cell $mux $ternary$libresoc.v:139942$5748 parameter \WIDTH 1 connect \A \sdr_dq_5__core__oe - connect \B \io_bd [99] + connect \B \io_bd [77] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139082$5766_Y + connect \Y $ternary$libresoc.v:139942$5748_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139083$5767 + cell $mux $ternary$libresoc.v:139943$5749 parameter \WIDTH 1 connect \A \sdr_dq_6__pad__i - connect \B \io_bd [100] + connect \B \io_bd [78] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139083$5767_Y + connect \Y $ternary$libresoc.v:139943$5749_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139084$5768 + cell $mux $ternary$libresoc.v:139944$5750 parameter \WIDTH 1 connect \A \sdr_dq_6__core__o - connect \B \io_bd [101] + connect \B \io_bd [79] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139084$5768_Y + connect \Y $ternary$libresoc.v:139944$5750_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139085$5769 + cell $mux $ternary$libresoc.v:139945$5751 parameter \WIDTH 1 connect \A \sdr_dq_6__core__oe - connect \B \io_bd [102] + connect \B \io_bd [80] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139085$5769_Y + connect \Y $ternary$libresoc.v:139945$5751_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139086$5770 + cell $mux $ternary$libresoc.v:139946$5752 parameter \WIDTH 1 connect \A \sdr_dq_7__pad__i - connect \B \io_bd [103] + connect \B \io_bd [81] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139086$5770_Y + connect \Y $ternary$libresoc.v:139946$5752_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139088$5772 + cell $mux $ternary$libresoc.v:139947$5753 parameter \WIDTH 1 connect \A \sdr_dq_7__core__o - connect \B \io_bd [104] + connect \B \io_bd [82] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139088$5772_Y + connect \Y $ternary$libresoc.v:139947$5753_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139089$5773 + cell $mux $ternary$libresoc.v:139948$5754 parameter \WIDTH 1 connect \A \sdr_dq_7__core__oe - connect \B \io_bd [105] + connect \B \io_bd [83] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139089$5773_Y + connect \Y $ternary$libresoc.v:139948$5754_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139090$5774 + cell $mux $ternary$libresoc.v:139950$5756 parameter \WIDTH 1 connect \A \sdr_a_0__core__o - connect \B \io_bd [106] + connect \B \io_bd [84] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139090$5774_Y + connect \Y $ternary$libresoc.v:139950$5756_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139091$5775 + cell $mux $ternary$libresoc.v:139951$5757 parameter \WIDTH 1 connect \A \sdr_a_1__core__o - connect \B \io_bd [107] + connect \B \io_bd [85] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139091$5775_Y + connect \Y $ternary$libresoc.v:139951$5757_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139092$5776 + cell $mux $ternary$libresoc.v:139952$5758 parameter \WIDTH 1 connect \A \sdr_a_2__core__o - connect \B \io_bd [108] + connect \B \io_bd [86] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139092$5776_Y + connect \Y $ternary$libresoc.v:139952$5758_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139093$5777 + cell $mux $ternary$libresoc.v:139953$5759 parameter \WIDTH 1 connect \A \sdr_a_3__core__o - connect \B \io_bd [109] + connect \B \io_bd [87] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139093$5777_Y + connect \Y $ternary$libresoc.v:139953$5759_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139094$5778 + cell $mux $ternary$libresoc.v:139954$5760 parameter \WIDTH 1 connect \A \sdr_a_4__core__o - connect \B \io_bd [110] + connect \B \io_bd [88] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139094$5778_Y + connect \Y $ternary$libresoc.v:139954$5760_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139095$5779 + cell $mux $ternary$libresoc.v:139955$5761 parameter \WIDTH 1 connect \A \sdr_a_5__core__o - connect \B \io_bd [111] + connect \B \io_bd [89] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139095$5779_Y + connect \Y $ternary$libresoc.v:139955$5761_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139096$5780 + cell $mux $ternary$libresoc.v:139956$5762 parameter \WIDTH 1 connect \A \sdr_a_6__core__o - connect \B \io_bd [112] + connect \B \io_bd [90] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139096$5780_Y + connect \Y $ternary$libresoc.v:139956$5762_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139097$5781 + cell $mux $ternary$libresoc.v:139957$5763 parameter \WIDTH 1 connect \A \sdr_a_7__core__o - connect \B \io_bd [113] + connect \B \io_bd [91] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139097$5781_Y + connect \Y $ternary$libresoc.v:139957$5763_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139099$5783 + cell $mux $ternary$libresoc.v:139958$5764 parameter \WIDTH 1 connect \A \sdr_a_8__core__o - connect \B \io_bd [114] + connect \B \io_bd [92] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139099$5783_Y + connect \Y $ternary$libresoc.v:139958$5764_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139100$5784 + cell $mux $ternary$libresoc.v:139959$5765 parameter \WIDTH 1 connect \A \sdr_a_9__core__o - connect \B \io_bd [115] + connect \B \io_bd [93] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139100$5784_Y + connect \Y $ternary$libresoc.v:139959$5765_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139101$5785 + cell $mux $ternary$libresoc.v:139961$5767 parameter \WIDTH 1 connect \A \sdr_ba_0__core__o - connect \B \io_bd [116] + connect \B \io_bd [94] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139101$5785_Y + connect \Y $ternary$libresoc.v:139961$5767_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139102$5786 + cell $mux $ternary$libresoc.v:139962$5768 parameter \WIDTH 1 connect \A \sdr_ba_1__core__o - connect \B \io_bd [117] + connect \B \io_bd [95] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139102$5786_Y + connect \Y $ternary$libresoc.v:139962$5768_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139103$5787 + cell $mux $ternary$libresoc.v:139963$5769 parameter \WIDTH 1 connect \A \sdr_clock__core__o - connect \B \io_bd [118] + connect \B \io_bd [96] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139103$5787_Y + connect \Y $ternary$libresoc.v:139963$5769_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139104$5788 + cell $mux $ternary$libresoc.v:139964$5770 parameter \WIDTH 1 connect \A \sdr_cke__core__o - connect \B \io_bd [119] + connect \B \io_bd [97] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139104$5788_Y + connect \Y $ternary$libresoc.v:139964$5770_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139105$5789 + cell $mux $ternary$libresoc.v:139965$5771 parameter \WIDTH 1 connect \A \sdr_ras_n__core__o - connect \B \io_bd [120] + connect \B \io_bd [98] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139105$5789_Y + connect \Y $ternary$libresoc.v:139965$5771_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139106$5790 + cell $mux $ternary$libresoc.v:139966$5772 parameter \WIDTH 1 connect \A \sdr_cas_n__core__o - connect \B \io_bd [121] + connect \B \io_bd [99] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139106$5790_Y + connect \Y $ternary$libresoc.v:139966$5772_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139107$5791 + cell $mux $ternary$libresoc.v:139967$5773 parameter \WIDTH 1 connect \A \sdr_we_n__core__o - connect \B \io_bd [122] + connect \B \io_bd [100] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139107$5791_Y + connect \Y $ternary$libresoc.v:139967$5773_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139108$5792 + cell $mux $ternary$libresoc.v:139968$5774 parameter \WIDTH 1 connect \A \sdr_cs_n__core__o - connect \B \io_bd [123] + connect \B \io_bd [101] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139108$5792_Y + connect \Y $ternary$libresoc.v:139968$5774_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139110$5794 + cell $mux $ternary$libresoc.v:139969$5775 parameter \WIDTH 1 connect \A \sdr_a_10__core__o - connect \B \io_bd [124] + connect \B \io_bd [102] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139110$5794_Y + connect \Y $ternary$libresoc.v:139969$5775_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139111$5795 + cell $mux $ternary$libresoc.v:139970$5776 parameter \WIDTH 1 connect \A \sdr_a_11__core__o - connect \B \io_bd [125] + connect \B \io_bd [103] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139111$5795_Y + connect \Y $ternary$libresoc.v:139970$5776_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139112$5796 + cell $mux $ternary$libresoc.v:139972$5778 parameter \WIDTH 1 connect \A \sdr_a_12__core__o - connect \B \io_bd [126] + connect \B \io_bd [104] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139112$5796_Y + connect \Y $ternary$libresoc.v:139972$5778_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:585" - cell $mux $ternary$libresoc.v:139113$5797 + cell $mux $ternary$libresoc.v:139973$5779 parameter \WIDTH 1 connect \A \sdr_dm_1__core__o - connect \B \io_bd [127] + connect \B \io_bd [105] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139113$5797_Y + connect \Y $ternary$libresoc.v:139973$5779_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139114$5798 + cell $mux $ternary$libresoc.v:139974$5780 parameter \WIDTH 1 connect \A \sdr_dq_8__pad__i - connect \B \io_bd [128] + connect \B \io_bd [106] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139114$5798_Y + connect \Y $ternary$libresoc.v:139974$5780_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139115$5799 + cell $mux $ternary$libresoc.v:139975$5781 parameter \WIDTH 1 connect \A \sdr_dq_8__core__o - connect \B \io_bd [129] + connect \B \io_bd [107] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139115$5799_Y + connect \Y $ternary$libresoc.v:139975$5781_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139116$5800 + cell $mux $ternary$libresoc.v:139976$5782 parameter \WIDTH 1 connect \A \sdr_dq_8__core__oe - connect \B \io_bd [130] + connect \B \io_bd [108] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139116$5800_Y + connect \Y $ternary$libresoc.v:139976$5782_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139117$5801 + cell $mux $ternary$libresoc.v:139977$5783 parameter \WIDTH 1 connect \A \sdr_dq_9__pad__i - connect \B \io_bd [131] + connect \B \io_bd [109] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139117$5801_Y + connect \Y $ternary$libresoc.v:139977$5783_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139118$5802 + cell $mux $ternary$libresoc.v:139978$5784 parameter \WIDTH 1 connect \A \sdr_dq_9__core__o - connect \B \io_bd [132] + connect \B \io_bd [110] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139118$5802_Y + connect \Y $ternary$libresoc.v:139978$5784_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139119$5803 + cell $mux $ternary$libresoc.v:139979$5785 parameter \WIDTH 1 connect \A \sdr_dq_9__core__oe - connect \B \io_bd [133] + connect \B \io_bd [111] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139119$5803_Y + connect \Y $ternary$libresoc.v:139979$5785_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139121$5805 + cell $mux $ternary$libresoc.v:139980$5786 parameter \WIDTH 1 connect \A \sdr_dq_10__pad__i - connect \B \io_bd [134] + connect \B \io_bd [112] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139121$5805_Y + connect \Y $ternary$libresoc.v:139980$5786_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139122$5806 + cell $mux $ternary$libresoc.v:139981$5787 parameter \WIDTH 1 connect \A \sdr_dq_10__core__o - connect \B \io_bd [135] + connect \B \io_bd [113] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139122$5806_Y + connect \Y $ternary$libresoc.v:139981$5787_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139123$5807 + cell $mux $ternary$libresoc.v:139983$5789 parameter \WIDTH 1 connect \A \sdr_dq_10__core__oe - connect \B \io_bd [136] + connect \B \io_bd [114] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139123$5807_Y + connect \Y $ternary$libresoc.v:139983$5789_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139124$5808 + cell $mux $ternary$libresoc.v:139984$5790 parameter \WIDTH 1 connect \A \sdr_dq_11__pad__i - connect \B \io_bd [137] + connect \B \io_bd [115] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139124$5808_Y + connect \Y $ternary$libresoc.v:139984$5790_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139125$5809 + cell $mux $ternary$libresoc.v:139985$5791 parameter \WIDTH 1 connect \A \sdr_dq_11__core__o - connect \B \io_bd [138] + connect \B \io_bd [116] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139125$5809_Y + connect \Y $ternary$libresoc.v:139985$5791_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139126$5810 + cell $mux $ternary$libresoc.v:139986$5792 parameter \WIDTH 1 connect \A \sdr_dq_11__core__oe - connect \B \io_bd [139] + connect \B \io_bd [117] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139126$5810_Y + connect \Y $ternary$libresoc.v:139986$5792_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139127$5811 + cell $mux $ternary$libresoc.v:139987$5793 parameter \WIDTH 1 connect \A \sdr_dq_12__pad__i - connect \B \io_bd [140] + connect \B \io_bd [118] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139127$5811_Y + connect \Y $ternary$libresoc.v:139987$5793_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139128$5812 + cell $mux $ternary$libresoc.v:139988$5794 parameter \WIDTH 1 connect \A \sdr_dq_12__core__o - connect \B \io_bd [141] + connect \B \io_bd [119] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139128$5812_Y + connect \Y $ternary$libresoc.v:139988$5794_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139129$5813 + cell $mux $ternary$libresoc.v:139989$5795 parameter \WIDTH 1 connect \A \sdr_dq_12__core__oe - connect \B \io_bd [142] + connect \B \io_bd [120] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139129$5813_Y + connect \Y $ternary$libresoc.v:139989$5795_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139130$5814 + cell $mux $ternary$libresoc.v:139990$5796 parameter \WIDTH 1 connect \A \sdr_dq_13__pad__i - connect \B \io_bd [143] + connect \B \io_bd [121] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139130$5814_Y + connect \Y $ternary$libresoc.v:139990$5796_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139132$5816 + cell $mux $ternary$libresoc.v:139991$5797 parameter \WIDTH 1 connect \A \sdr_dq_13__core__o - connect \B \io_bd [144] + connect \B \io_bd [122] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139132$5816_Y + connect \Y $ternary$libresoc.v:139991$5797_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139133$5817 + cell $mux $ternary$libresoc.v:139992$5798 parameter \WIDTH 1 connect \A \sdr_dq_13__core__oe - connect \B \io_bd [145] + connect \B \io_bd [123] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139133$5817_Y + connect \Y $ternary$libresoc.v:139992$5798_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139134$5818 + cell $mux $ternary$libresoc.v:139994$5800 parameter \WIDTH 1 connect \A \sdr_dq_14__pad__i - connect \B \io_bd [146] + connect \B \io_bd [124] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139134$5818_Y + connect \Y $ternary$libresoc.v:139994$5800_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139135$5819 + cell $mux $ternary$libresoc.v:139995$5801 parameter \WIDTH 1 connect \A \sdr_dq_14__core__o - connect \B \io_bd [147] + connect \B \io_bd [125] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139135$5819_Y + connect \Y $ternary$libresoc.v:139995$5801_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139136$5820 + cell $mux $ternary$libresoc.v:139996$5802 parameter \WIDTH 1 connect \A \sdr_dq_14__core__oe - connect \B \io_bd [148] + connect \B \io_bd [126] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139136$5820_Y + connect \Y $ternary$libresoc.v:139996$5802_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139137$5821 + cell $mux $ternary$libresoc.v:139997$5803 parameter \WIDTH 1 connect \A \sdr_dq_15__pad__i - connect \B \io_bd [149] + connect \B \io_bd [127] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139137$5821_Y + connect \Y $ternary$libresoc.v:139997$5803_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139138$5822 + cell $mux $ternary$libresoc.v:139998$5804 parameter \WIDTH 1 connect \A \sdr_dq_15__core__o - connect \B \io_bd [150] + connect \B \io_bd [128] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139138$5822_Y + connect \Y $ternary$libresoc.v:139998$5804_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139139$5823 + cell $mux $ternary$libresoc.v:139999$5805 parameter \WIDTH 1 connect \A \sdr_dq_15__core__oe - connect \B \io_bd [151] + connect \B \io_bd [129] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139139$5823_Y + connect \Y $ternary$libresoc.v:139999$5805_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:139226$5911 + cell $mux $ternary$libresoc.v:140088$5895 parameter \WIDTH 1 connect \A \eint_0__pad__i connect \B \io_bd [0] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139226$5911_Y + connect \Y $ternary$libresoc.v:140088$5895_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:139227$5912 + cell $mux $ternary$libresoc.v:140089$5896 parameter \WIDTH 1 connect \A \eint_1__pad__i connect \B \io_bd [1] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139227$5912_Y + connect \Y $ternary$libresoc.v:140089$5896_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:582" - cell $mux $ternary$libresoc.v:139228$5913 + cell $mux $ternary$libresoc.v:140090$5897 parameter \WIDTH 1 connect \A \eint_2__pad__i connect \B \io_bd [2] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139228$5913_Y + connect \Y $ternary$libresoc.v:140090$5897_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139229$5914 + cell $mux $ternary$libresoc.v:140091$5898 parameter \WIDTH 1 connect \A \gpio_e8__pad__i connect \B \io_bd [3] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139229$5914_Y + connect \Y $ternary$libresoc.v:140091$5898_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139231$5916 + cell $mux $ternary$libresoc.v:140093$5900 parameter \WIDTH 1 connect \A \gpio_e8__core__o connect \B \io_bd [4] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139231$5916_Y + connect \Y $ternary$libresoc.v:140093$5900_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139232$5917 + cell $mux $ternary$libresoc.v:140094$5901 parameter \WIDTH 1 connect \A \gpio_e8__core__oe connect \B \io_bd [5] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139232$5917_Y + connect \Y $ternary$libresoc.v:140094$5901_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139233$5918 + cell $mux $ternary$libresoc.v:140095$5902 parameter \WIDTH 1 connect \A \gpio_e9__pad__i connect \B \io_bd [6] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139233$5918_Y + connect \Y $ternary$libresoc.v:140095$5902_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139234$5919 + cell $mux $ternary$libresoc.v:140096$5903 parameter \WIDTH 1 connect \A \gpio_e9__core__o connect \B \io_bd [7] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139234$5919_Y + connect \Y $ternary$libresoc.v:140096$5903_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139235$5920 + cell $mux $ternary$libresoc.v:140097$5904 parameter \WIDTH 1 connect \A \gpio_e9__core__oe connect \B \io_bd [8] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139235$5920_Y + connect \Y $ternary$libresoc.v:140097$5904_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139236$5921 + cell $mux $ternary$libresoc.v:140098$5905 parameter \WIDTH 1 connect \A \gpio_e10__pad__i connect \B \io_bd [9] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139236$5921_Y + connect \Y $ternary$libresoc.v:140098$5905_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139237$5922 + cell $mux $ternary$libresoc.v:140099$5906 parameter \WIDTH 1 connect \A \gpio_e10__core__o connect \B \io_bd [10] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139237$5922_Y + connect \Y $ternary$libresoc.v:140099$5906_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139238$5923 + cell $mux $ternary$libresoc.v:140100$5907 parameter \WIDTH 1 connect \A \gpio_e10__core__oe connect \B \io_bd [11] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139238$5923_Y + connect \Y $ternary$libresoc.v:140100$5907_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139239$5924 + cell $mux $ternary$libresoc.v:140101$5908 parameter \WIDTH 1 connect \A \gpio_e11__pad__i connect \B \io_bd [12] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139239$5924_Y + connect \Y $ternary$libresoc.v:140101$5908_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139240$5925 + cell $mux $ternary$libresoc.v:140102$5909 parameter \WIDTH 1 connect \A \gpio_e11__core__o connect \B \io_bd [13] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139240$5925_Y + connect \Y $ternary$libresoc.v:140102$5909_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139242$5927 + cell $mux $ternary$libresoc.v:140104$5911 parameter \WIDTH 1 connect \A \gpio_e11__core__oe connect \B \io_bd [14] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139242$5927_Y + connect \Y $ternary$libresoc.v:140104$5911_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139243$5928 + cell $mux $ternary$libresoc.v:140105$5912 parameter \WIDTH 1 connect \A \gpio_e12__pad__i connect \B \io_bd [15] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139243$5928_Y + connect \Y $ternary$libresoc.v:140105$5912_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139244$5929 + cell $mux $ternary$libresoc.v:140106$5913 parameter \WIDTH 1 connect \A \gpio_e12__core__o connect \B \io_bd [16] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139244$5929_Y + connect \Y $ternary$libresoc.v:140106$5913_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139245$5930 + cell $mux $ternary$libresoc.v:140107$5914 parameter \WIDTH 1 connect \A \gpio_e12__core__oe connect \B \io_bd [17] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139245$5930_Y + connect \Y $ternary$libresoc.v:140107$5914_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139246$5931 + cell $mux $ternary$libresoc.v:140108$5915 parameter \WIDTH 1 connect \A \gpio_e13__pad__i connect \B \io_bd [18] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139246$5931_Y + connect \Y $ternary$libresoc.v:140108$5915_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139247$5932 + cell $mux $ternary$libresoc.v:140109$5916 parameter \WIDTH 1 connect \A \gpio_e13__core__o connect \B \io_bd [19] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139247$5932_Y + connect \Y $ternary$libresoc.v:140109$5916_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139248$5933 + cell $mux $ternary$libresoc.v:140110$5917 parameter \WIDTH 1 connect \A \gpio_e13__core__oe connect \B \io_bd [20] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139248$5933_Y + connect \Y $ternary$libresoc.v:140110$5917_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:595" - cell $mux $ternary$libresoc.v:139249$5934 + cell $mux $ternary$libresoc.v:140111$5918 parameter \WIDTH 1 connect \A \gpio_e14__pad__i connect \B \io_bd [21] connect \S \io_bd2core - connect \Y $ternary$libresoc.v:139249$5934_Y + connect \Y $ternary$libresoc.v:140111$5918_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:596" - cell $mux $ternary$libresoc.v:139250$5935 + cell $mux $ternary$libresoc.v:140112$5919 parameter \WIDTH 1 connect \A \gpio_e14__core__o connect \B \io_bd [22] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139250$5935_Y + connect \Y $ternary$libresoc.v:140112$5919_Y end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:597" - cell $mux $ternary$libresoc.v:139251$5936 + cell $mux $ternary$libresoc.v:140113$5920 parameter \WIDTH 1 connect \A \gpio_e14__core__oe connect \B \io_bd [23] connect \S \io_bd2io - connect \Y $ternary$libresoc.v:139251$5936_Y + connect \Y $ternary$libresoc.v:140113$5920_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:139326.8-139338.4" + attribute \src "libresoc.v:140188.8-140200.4" cell \_fsm \_fsm connect \TAP_bus__tck \TAP_bus__tck connect \TAP_bus__tms \TAP_bus__tms @@ -222176,7 +222610,7 @@ module \jtag connect \update \_fsm_update end attribute \module_not_derived 1 - attribute \src "libresoc.v:139339.12-139349.4" + attribute \src "libresoc.v:140201.12-140211.4" cell \_idblock \_idblock connect \TAP_bus__tdi \TAP_bus__tdi connect \TAP_id_tdo \_idblock_TAP_id_tdo @@ -222189,7 +222623,7 @@ module \jtag connect \update \_fsm_update end attribute \module_not_derived 1 - attribute \src "libresoc.v:139350.12-139360.4" + attribute \src "libresoc.v:140212.12-140222.4" cell \_irblock \_irblock connect \TAP_bus__tdi \TAP_bus__tdi connect \capture \_fsm_capture @@ -222201,582 +222635,582 @@ module \jtag connect \tdo \_irblock_tdo connect \update \_fsm_update end - attribute \src "libresoc.v:137576.7-137576.20" - process $proc$libresoc.v:137576$6132 + attribute \src "libresoc.v:138592.7-138592.20" + process $proc$libresoc.v:138592$6116 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:138130.13-138130.32" - process $proc$libresoc.v:138130$6133 + attribute \src "libresoc.v:139102.13-139102.32" + process $proc$libresoc.v:139102$6117 assign { } { } assign $1\dmi0__addr_i[3:0] 4'0000 sync always sync init update \dmi0__addr_i $1\dmi0__addr_i[3:0] end - attribute \src "libresoc.v:138135.14-138135.46" - process $proc$libresoc.v:138135$6134 + attribute \src "libresoc.v:139107.14-139107.46" + process $proc$libresoc.v:139107$6118 assign { } { } assign $1\dmi0__din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dmi0__din $1\dmi0__din[63:0] end - attribute \src "libresoc.v:138149.7-138149.29" - process $proc$libresoc.v:138149$6135 + attribute \src "libresoc.v:139121.7-139121.29" + process $proc$libresoc.v:139121$6119 assign { } { } assign $1\dmi0_addrsr__oe[0:0] 1'0 sync always sync init update \dmi0_addrsr__oe $1\dmi0_addrsr__oe[0:0] end - attribute \src "libresoc.v:138157.13-138157.36" - process $proc$libresoc.v:138157$6136 + attribute \src "libresoc.v:139129.13-139129.36" + process $proc$libresoc.v:139129$6120 assign { } { } assign $1\dmi0_addrsr_reg[7:0] 8'00000000 sync always sync init update \dmi0_addrsr_reg $1\dmi0_addrsr_reg[7:0] end - attribute \src "libresoc.v:138165.7-138165.37" - process $proc$libresoc.v:138165$6137 + attribute \src "libresoc.v:139137.7-139137.37" + process $proc$libresoc.v:139137$6121 assign { } { } assign $1\dmi0_addrsr_update_core[0:0] 1'0 sync always sync init update \dmi0_addrsr_update_core $1\dmi0_addrsr_update_core[0:0] end - attribute \src "libresoc.v:138169.7-138169.42" - process $proc$libresoc.v:138169$6138 + attribute \src "libresoc.v:139141.7-139141.42" + process $proc$libresoc.v:139141$6122 assign { } { } assign $1\dmi0_addrsr_update_core_prev[0:0] 1'0 sync always sync init update \dmi0_addrsr_update_core_prev $1\dmi0_addrsr_update_core_prev[0:0] end - attribute \src "libresoc.v:138173.14-138173.51" - process $proc$libresoc.v:138173$6139 + attribute \src "libresoc.v:139145.14-139145.51" + process $proc$libresoc.v:139145$6123 assign { } { } assign $1\dmi0_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dmi0_datasr__i $1\dmi0_datasr__i[63:0] end - attribute \src "libresoc.v:138179.13-138179.35" - process $proc$libresoc.v:138179$6140 + attribute \src "libresoc.v:139151.13-139151.35" + process $proc$libresoc.v:139151$6124 assign { } { } assign $1\dmi0_datasr__oe[1:0] 2'00 sync always sync init update \dmi0_datasr__oe $1\dmi0_datasr__oe[1:0] end - attribute \src "libresoc.v:138187.14-138187.52" - process $proc$libresoc.v:138187$6141 + attribute \src "libresoc.v:139159.14-139159.52" + process $proc$libresoc.v:139159$6125 assign { } { } assign $1\dmi0_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dmi0_datasr_reg $1\dmi0_datasr_reg[63:0] end - attribute \src "libresoc.v:138195.7-138195.37" - process $proc$libresoc.v:138195$6142 + attribute \src "libresoc.v:139167.7-139167.37" + process $proc$libresoc.v:139167$6126 assign { } { } assign $1\dmi0_datasr_update_core[0:0] 1'0 sync always sync init update \dmi0_datasr_update_core $1\dmi0_datasr_update_core[0:0] end - attribute \src "libresoc.v:138199.7-138199.42" - process $proc$libresoc.v:138199$6143 + attribute \src "libresoc.v:139171.7-139171.42" + process $proc$libresoc.v:139171$6127 assign { } { } assign $1\dmi0_datasr_update_core_prev[0:0] 1'0 sync always sync init update \dmi0_datasr_update_core_prev $1\dmi0_datasr_update_core_prev[0:0] end - attribute \src "libresoc.v:138215.13-138215.29" - process $proc$libresoc.v:138215$6144 + attribute \src "libresoc.v:139187.13-139187.29" + process $proc$libresoc.v:139187$6128 assign { } { } assign $1\fsm_state[2:0] 3'000 sync always sync init update \fsm_state $1\fsm_state[2:0] end - attribute \src "libresoc.v:138217.13-138217.35" - process $proc$libresoc.v:138217$6145 + attribute \src "libresoc.v:139189.13-139189.35" + process $proc$libresoc.v:139189$6129 assign { } { } - assign $0\fsm_state$499[2:0]$6146 3'000 + assign $0\fsm_state$455[2:0]$6130 3'000 sync always sync init - update \fsm_state$499 $0\fsm_state$499[2:0]$6146 + update \fsm_state$455 $0\fsm_state$455[2:0]$6130 end - attribute \src "libresoc.v:138415.15-138415.66" - process $proc$libresoc.v:138415$6147 + attribute \src "libresoc.v:139387.15-139387.61" + process $proc$libresoc.v:139387$6131 assign { } { } - assign $1\io_bd[151:0] 152'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\io_bd[129:0] 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \io_bd $1\io_bd[151:0] + update \io_bd $1\io_bd[129:0] end - attribute \src "libresoc.v:138427.15-138427.66" - process $proc$libresoc.v:138427$6148 + attribute \src "libresoc.v:139399.15-139399.61" + process $proc$libresoc.v:139399$6132 assign { } { } - assign $1\io_sr[151:0] 152'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\io_sr[129:0] 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \io_sr $1\io_sr[151:0] + update \io_sr $1\io_sr[129:0] end - attribute \src "libresoc.v:138436.14-138436.41" - process $proc$libresoc.v:138436$6149 + attribute \src "libresoc.v:139408.14-139408.41" + process $proc$libresoc.v:139408$6133 assign { } { } assign $1\jtag_wb__adr[28:0] 29'00000000000000000000000000000 sync always sync init update \jtag_wb__adr $1\jtag_wb__adr[28:0] end - attribute \src "libresoc.v:138445.14-138445.51" - process $proc$libresoc.v:138445$6150 + attribute \src "libresoc.v:139417.14-139417.51" + process $proc$libresoc.v:139417$6134 assign { } { } assign $1\jtag_wb__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \jtag_wb__dat_w $1\jtag_wb__dat_w[63:0] end - attribute \src "libresoc.v:138459.7-138459.32" - process $proc$libresoc.v:138459$6151 + attribute \src "libresoc.v:139431.7-139431.32" + process $proc$libresoc.v:139431$6135 assign { } { } assign $1\jtag_wb_addrsr__oe[0:0] 1'0 sync always sync init update \jtag_wb_addrsr__oe $1\jtag_wb_addrsr__oe[0:0] end - attribute \src "libresoc.v:138467.14-138467.47" - process $proc$libresoc.v:138467$6152 + attribute \src "libresoc.v:139439.14-139439.47" + process $proc$libresoc.v:139439$6136 assign { } { } assign $1\jtag_wb_addrsr_reg[28:0] 29'00000000000000000000000000000 sync always sync init update \jtag_wb_addrsr_reg $1\jtag_wb_addrsr_reg[28:0] end - attribute \src "libresoc.v:138475.7-138475.40" - process $proc$libresoc.v:138475$6153 + attribute \src "libresoc.v:139447.7-139447.40" + process $proc$libresoc.v:139447$6137 assign { } { } assign $1\jtag_wb_addrsr_update_core[0:0] 1'0 sync always sync init update \jtag_wb_addrsr_update_core $1\jtag_wb_addrsr_update_core[0:0] end - attribute \src "libresoc.v:138479.7-138479.45" - process $proc$libresoc.v:138479$6154 + attribute \src "libresoc.v:139451.7-139451.45" + process $proc$libresoc.v:139451$6138 assign { } { } assign $1\jtag_wb_addrsr_update_core_prev[0:0] 1'0 sync always sync init update \jtag_wb_addrsr_update_core_prev $1\jtag_wb_addrsr_update_core_prev[0:0] end - attribute \src "libresoc.v:138483.14-138483.54" - process $proc$libresoc.v:138483$6155 + attribute \src "libresoc.v:139455.14-139455.54" + process $proc$libresoc.v:139455$6139 assign { } { } assign $1\jtag_wb_datasr__i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \jtag_wb_datasr__i $1\jtag_wb_datasr__i[63:0] end - attribute \src "libresoc.v:138489.13-138489.38" - process $proc$libresoc.v:138489$6156 + attribute \src "libresoc.v:139461.13-139461.38" + process $proc$libresoc.v:139461$6140 assign { } { } assign $1\jtag_wb_datasr__oe[1:0] 2'00 sync always sync init update \jtag_wb_datasr__oe $1\jtag_wb_datasr__oe[1:0] end - attribute \src "libresoc.v:138497.14-138497.55" - process $proc$libresoc.v:138497$6157 + attribute \src "libresoc.v:139469.14-139469.55" + process $proc$libresoc.v:139469$6141 assign { } { } assign $1\jtag_wb_datasr_reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \jtag_wb_datasr_reg $1\jtag_wb_datasr_reg[63:0] end - attribute \src "libresoc.v:138505.7-138505.40" - process $proc$libresoc.v:138505$6158 + attribute \src "libresoc.v:139477.7-139477.40" + process $proc$libresoc.v:139477$6142 assign { } { } assign $1\jtag_wb_datasr_update_core[0:0] 1'0 sync always sync init update \jtag_wb_datasr_update_core $1\jtag_wb_datasr_update_core[0:0] end - attribute \src "libresoc.v:138509.7-138509.45" - process $proc$libresoc.v:138509$6159 + attribute \src "libresoc.v:139481.7-139481.45" + process $proc$libresoc.v:139481$6143 assign { } { } assign $1\jtag_wb_datasr_update_core_prev[0:0] 1'0 sync always sync init update \jtag_wb_datasr_update_core_prev $1\jtag_wb_datasr_update_core_prev[0:0] end - attribute \src "libresoc.v:138931.7-138931.21" - process $proc$libresoc.v:138931$6160 + attribute \src "libresoc.v:139815.7-139815.21" + process $proc$libresoc.v:139815$6144 assign { } { } assign $1\sr0__oe[0:0] 1'0 sync always sync init update \sr0__oe $1\sr0__oe[0:0] end - attribute \src "libresoc.v:138939.13-138939.27" - process $proc$libresoc.v:138939$6161 + attribute \src "libresoc.v:139823.13-139823.27" + process $proc$libresoc.v:139823$6145 assign { } { } assign $1\sr0_reg[2:0] 3'000 sync always sync init update \sr0_reg $1\sr0_reg[2:0] end - attribute \src "libresoc.v:138947.7-138947.29" - process $proc$libresoc.v:138947$6162 + attribute \src "libresoc.v:139831.7-139831.29" + process $proc$libresoc.v:139831$6146 assign { } { } assign $1\sr0_update_core[0:0] 1'0 sync always sync init update \sr0_update_core $1\sr0_update_core[0:0] end - attribute \src "libresoc.v:138951.7-138951.34" - process $proc$libresoc.v:138951$6163 + attribute \src "libresoc.v:139835.7-139835.34" + process $proc$libresoc.v:139835$6147 assign { } { } assign $1\sr0_update_core_prev[0:0] 1'0 sync always sync init update \sr0_update_core_prev $1\sr0_update_core_prev[0:0] end - attribute \src "libresoc.v:138961.7-138961.21" - process $proc$libresoc.v:138961$6164 + attribute \src "libresoc.v:139845.7-139845.21" + process $proc$libresoc.v:139845$6148 assign { } { } assign $1\sr5__oe[0:0] 1'0 sync always sync init update \sr5__oe $1\sr5__oe[0:0] end - attribute \src "libresoc.v:138969.13-138969.27" - process $proc$libresoc.v:138969$6165 + attribute \src "libresoc.v:139853.13-139853.27" + process $proc$libresoc.v:139853$6149 assign { } { } assign $1\sr5_reg[2:0] 3'000 sync always sync init update \sr5_reg $1\sr5_reg[2:0] end - attribute \src "libresoc.v:138977.7-138977.29" - process $proc$libresoc.v:138977$6166 + attribute \src "libresoc.v:139861.7-139861.29" + process $proc$libresoc.v:139861$6150 assign { } { } assign $1\sr5_update_core[0:0] 1'0 sync always sync init update \sr5_update_core $1\sr5_update_core[0:0] end - attribute \src "libresoc.v:138981.7-138981.34" - process $proc$libresoc.v:138981$6167 + attribute \src "libresoc.v:139865.7-139865.34" + process $proc$libresoc.v:139865$6151 assign { } { } assign $1\sr5_update_core_prev[0:0] 1'0 sync always sync init update \sr5_update_core_prev $1\sr5_update_core_prev[0:0] end - attribute \src "libresoc.v:138986.7-138986.26" - process $proc$libresoc.v:138986$6168 + attribute \src "libresoc.v:139870.7-139870.26" + process $proc$libresoc.v:139870$6152 assign { } { } assign $1\wb_dcache_en[0:0] 1'1 sync always sync init update \wb_dcache_en $1\wb_dcache_en[0:0] end - attribute \src "libresoc.v:138991.7-138991.26" - process $proc$libresoc.v:138991$6169 + attribute \src "libresoc.v:139875.7-139875.26" + process $proc$libresoc.v:139875$6153 assign { } { } assign $1\wb_icache_en[0:0] 1'1 sync always sync init update \wb_icache_en $1\wb_icache_en[0:0] end - attribute \src "libresoc.v:138995.7-138995.24" - process $proc$libresoc.v:138995$6170 + attribute \src "libresoc.v:139879.7-139879.24" + process $proc$libresoc.v:139879$6154 assign { } { } assign $1\wb_sram_en[0:0] 1'1 sync always sync init update \wb_sram_en $1\wb_sram_en[0:0] end - attribute \src "libresoc.v:139252.3-139253.41" - process $proc$libresoc.v:139252$5937 + attribute \src "libresoc.v:140114.3-140115.41" + process $proc$libresoc.v:140114$5921 assign { } { } assign $0\wb_icache_en[0:0] \wb_icache_en$next sync posedge \clk update \wb_icache_en $0\wb_icache_en[0:0] end - attribute \src "libresoc.v:139254.3-139255.41" - process $proc$libresoc.v:139254$5938 + attribute \src "libresoc.v:140116.3-140117.41" + process $proc$libresoc.v:140116$5922 assign { } { } assign $0\wb_dcache_en[0:0] \wb_dcache_en$next sync posedge \clk update \wb_dcache_en $0\wb_dcache_en[0:0] end - attribute \src "libresoc.v:139256.3-139257.37" - process $proc$libresoc.v:139256$5939 + attribute \src "libresoc.v:140118.3-140119.37" + process $proc$libresoc.v:140118$5923 assign { } { } assign $0\wb_sram_en[0:0] \wb_sram_en$next sync posedge \clk update \wb_sram_en $0\wb_sram_en[0:0] end - attribute \src "libresoc.v:139258.3-139259.45" - process $proc$libresoc.v:139258$5940 + attribute \src "libresoc.v:140120.3-140121.45" + process $proc$libresoc.v:140120$5924 assign { } { } assign $0\dmi0_datasr__i[63:0] \dmi0_datasr__i$next sync posedge \clk update \dmi0_datasr__i $0\dmi0_datasr__i[63:0] end - attribute \src "libresoc.v:139260.3-139261.35" - process $proc$libresoc.v:139260$5941 + attribute \src "libresoc.v:140122.3-140123.35" + process $proc$libresoc.v:140122$5925 assign { } { } assign $0\dmi0__din[63:0] \dmi0__din$next sync posedge \clk update \dmi0__din $0\dmi0__din[63:0] end - attribute \src "libresoc.v:139262.3-139263.45" - process $proc$libresoc.v:139262$5942 + attribute \src "libresoc.v:140124.3-140125.45" + process $proc$libresoc.v:140124$5926 assign { } { } - assign $0\fsm_state$499[2:0]$5943 \fsm_state$499$next + assign $0\fsm_state$455[2:0]$5927 \fsm_state$455$next sync posedge \clk - update \fsm_state$499 $0\fsm_state$499[2:0]$5943 + update \fsm_state$455 $0\fsm_state$455[2:0]$5927 end - attribute \src "libresoc.v:139264.3-139265.41" - process $proc$libresoc.v:139264$5944 + attribute \src "libresoc.v:140126.3-140127.41" + process $proc$libresoc.v:140126$5928 assign { } { } assign $0\dmi0__addr_i[3:0] \dmi0__addr_i$next sync posedge \clk update \dmi0__addr_i $0\dmi0__addr_i[3:0] end - attribute \src "libresoc.v:139266.3-139267.51" - process $proc$libresoc.v:139266$5945 + attribute \src "libresoc.v:140128.3-140129.51" + process $proc$libresoc.v:140128$5929 assign { } { } assign $0\jtag_wb_datasr__i[63:0] \jtag_wb_datasr__i$next sync posedge \clk update \jtag_wb_datasr__i $0\jtag_wb_datasr__i[63:0] end - attribute \src "libresoc.v:139268.3-139269.45" - process $proc$libresoc.v:139268$5946 + attribute \src "libresoc.v:140130.3-140131.45" + process $proc$libresoc.v:140130$5930 assign { } { } assign $0\jtag_wb__dat_w[63:0] \jtag_wb__dat_w$next sync posedge \clk update \jtag_wb__dat_w $0\jtag_wb__dat_w[63:0] end - attribute \src "libresoc.v:139270.3-139271.35" - process $proc$libresoc.v:139270$5947 + attribute \src "libresoc.v:140132.3-140133.35" + process $proc$libresoc.v:140132$5931 assign { } { } assign $0\fsm_state[2:0] \fsm_state$next sync posedge \clk update \fsm_state $0\fsm_state[2:0] end - attribute \src "libresoc.v:139272.3-139273.41" - process $proc$libresoc.v:139272$5948 + attribute \src "libresoc.v:140134.3-140135.41" + process $proc$libresoc.v:140134$5932 assign { } { } assign $0\jtag_wb__adr[28:0] \jtag_wb__adr$next sync posedge \clk update \jtag_wb__adr $0\jtag_wb__adr[28:0] end - attribute \src "libresoc.v:139274.3-139275.31" - process $proc$libresoc.v:139274$5949 + attribute \src "libresoc.v:140136.3-140137.31" + process $proc$libresoc.v:140136$5933 assign { } { } assign $0\sr5_reg[2:0] \sr5_reg$next sync posedge \posjtag_clk update \sr5_reg $0\sr5_reg[2:0] end - attribute \src "libresoc.v:139276.3-139277.31" - process $proc$libresoc.v:139276$5950 + attribute \src "libresoc.v:140138.3-140139.31" + process $proc$libresoc.v:140138$5934 assign { } { } assign $0\sr5__oe[0:0] \sr5__oe$next sync posedge \clk update \sr5__oe $0\sr5__oe[0:0] end - attribute \src "libresoc.v:139278.3-139279.57" - process $proc$libresoc.v:139278$5951 + attribute \src "libresoc.v:140140.3-140141.57" + process $proc$libresoc.v:140140$5935 assign { } { } assign $0\sr5_update_core_prev[0:0] \sr5_update_core_prev$next sync posedge \clk update \sr5_update_core_prev $0\sr5_update_core_prev[0:0] end - attribute \src "libresoc.v:139280.3-139281.47" - process $proc$libresoc.v:139280$5952 + attribute \src "libresoc.v:140142.3-140143.47" + process $proc$libresoc.v:140142$5936 assign { } { } assign $0\sr5_update_core[0:0] \sr5_update_core$next sync posedge \clk update \sr5_update_core $0\sr5_update_core[0:0] end - attribute \src "libresoc.v:139282.3-139283.47" - process $proc$libresoc.v:139282$5953 + attribute \src "libresoc.v:140144.3-140145.47" + process $proc$libresoc.v:140144$5937 assign { } { } assign $0\dmi0_datasr_reg[63:0] \dmi0_datasr_reg$next sync posedge \posjtag_clk update \dmi0_datasr_reg $0\dmi0_datasr_reg[63:0] end - attribute \src "libresoc.v:139284.3-139285.47" - process $proc$libresoc.v:139284$5954 + attribute \src "libresoc.v:140146.3-140147.47" + process $proc$libresoc.v:140146$5938 assign { } { } assign $0\dmi0_datasr__oe[1:0] \dmi0_datasr__oe$next sync posedge \clk update \dmi0_datasr__oe $0\dmi0_datasr__oe[1:0] end - attribute \src "libresoc.v:139286.3-139287.73" - process $proc$libresoc.v:139286$5955 + attribute \src "libresoc.v:140148.3-140149.73" + process $proc$libresoc.v:140148$5939 assign { } { } assign $0\dmi0_datasr_update_core_prev[0:0] \dmi0_datasr_update_core_prev$next sync posedge \clk update \dmi0_datasr_update_core_prev $0\dmi0_datasr_update_core_prev[0:0] end - attribute \src "libresoc.v:139288.3-139289.63" - process $proc$libresoc.v:139288$5956 + attribute \src "libresoc.v:140150.3-140151.63" + process $proc$libresoc.v:140150$5940 assign { } { } assign $0\dmi0_datasr_update_core[0:0] \dmi0_datasr_update_core$next sync posedge \clk update \dmi0_datasr_update_core $0\dmi0_datasr_update_core[0:0] end - attribute \src "libresoc.v:139290.3-139291.47" - process $proc$libresoc.v:139290$5957 + attribute \src "libresoc.v:140152.3-140153.47" + process $proc$libresoc.v:140152$5941 assign { } { } assign $0\dmi0_addrsr_reg[7:0] \dmi0_addrsr_reg$next sync posedge \posjtag_clk update \dmi0_addrsr_reg $0\dmi0_addrsr_reg[7:0] end - attribute \src "libresoc.v:139292.3-139293.47" - process $proc$libresoc.v:139292$5958 + attribute \src "libresoc.v:140154.3-140155.47" + process $proc$libresoc.v:140154$5942 assign { } { } assign $0\dmi0_addrsr__oe[0:0] \dmi0_addrsr__oe$next sync posedge \clk update \dmi0_addrsr__oe $0\dmi0_addrsr__oe[0:0] end - attribute \src "libresoc.v:139294.3-139295.73" - process $proc$libresoc.v:139294$5959 + attribute \src "libresoc.v:140156.3-140157.73" + process $proc$libresoc.v:140156$5943 assign { } { } assign $0\dmi0_addrsr_update_core_prev[0:0] \dmi0_addrsr_update_core_prev$next sync posedge \clk update \dmi0_addrsr_update_core_prev $0\dmi0_addrsr_update_core_prev[0:0] end - attribute \src "libresoc.v:139296.3-139297.63" - process $proc$libresoc.v:139296$5960 + attribute \src "libresoc.v:140158.3-140159.63" + process $proc$libresoc.v:140158$5944 assign { } { } assign $0\dmi0_addrsr_update_core[0:0] \dmi0_addrsr_update_core$next sync posedge \clk update \dmi0_addrsr_update_core $0\dmi0_addrsr_update_core[0:0] end - attribute \src "libresoc.v:139298.3-139299.53" - process $proc$libresoc.v:139298$5961 + attribute \src "libresoc.v:140160.3-140161.53" + process $proc$libresoc.v:140160$5945 assign { } { } assign $0\jtag_wb_datasr_reg[63:0] \jtag_wb_datasr_reg$next sync posedge \posjtag_clk update \jtag_wb_datasr_reg $0\jtag_wb_datasr_reg[63:0] end - attribute \src "libresoc.v:139300.3-139301.53" - process $proc$libresoc.v:139300$5962 + attribute \src "libresoc.v:140162.3-140163.53" + process $proc$libresoc.v:140162$5946 assign { } { } assign $0\jtag_wb_datasr__oe[1:0] \jtag_wb_datasr__oe$next sync posedge \clk update \jtag_wb_datasr__oe $0\jtag_wb_datasr__oe[1:0] end - attribute \src "libresoc.v:139302.3-139303.79" - process $proc$libresoc.v:139302$5963 + attribute \src "libresoc.v:140164.3-140165.79" + process $proc$libresoc.v:140164$5947 assign { } { } assign $0\jtag_wb_datasr_update_core_prev[0:0] \jtag_wb_datasr_update_core_prev$next sync posedge \clk update \jtag_wb_datasr_update_core_prev $0\jtag_wb_datasr_update_core_prev[0:0] end - attribute \src "libresoc.v:139304.3-139305.69" - process $proc$libresoc.v:139304$5964 + attribute \src "libresoc.v:140166.3-140167.69" + process $proc$libresoc.v:140166$5948 assign { } { } assign $0\jtag_wb_datasr_update_core[0:0] \jtag_wb_datasr_update_core$next sync posedge \clk update \jtag_wb_datasr_update_core $0\jtag_wb_datasr_update_core[0:0] end - attribute \src "libresoc.v:139306.3-139307.53" - process $proc$libresoc.v:139306$5965 + attribute \src "libresoc.v:140168.3-140169.53" + process $proc$libresoc.v:140168$5949 assign { } { } assign $0\jtag_wb_addrsr_reg[28:0] \jtag_wb_addrsr_reg$next sync posedge \posjtag_clk update \jtag_wb_addrsr_reg $0\jtag_wb_addrsr_reg[28:0] end - attribute \src "libresoc.v:139308.3-139309.53" - process $proc$libresoc.v:139308$5966 + attribute \src "libresoc.v:140170.3-140171.53" + process $proc$libresoc.v:140170$5950 assign { } { } assign $0\jtag_wb_addrsr__oe[0:0] \jtag_wb_addrsr__oe$next sync posedge \clk update \jtag_wb_addrsr__oe $0\jtag_wb_addrsr__oe[0:0] end - attribute \src "libresoc.v:139310.3-139311.79" - process $proc$libresoc.v:139310$5967 + attribute \src "libresoc.v:140172.3-140173.79" + process $proc$libresoc.v:140172$5951 assign { } { } assign $0\jtag_wb_addrsr_update_core_prev[0:0] \jtag_wb_addrsr_update_core_prev$next sync posedge \clk update \jtag_wb_addrsr_update_core_prev $0\jtag_wb_addrsr_update_core_prev[0:0] end - attribute \src "libresoc.v:139312.3-139313.69" - process $proc$libresoc.v:139312$5968 + attribute \src "libresoc.v:140174.3-140175.69" + process $proc$libresoc.v:140174$5952 assign { } { } assign $0\jtag_wb_addrsr_update_core[0:0] \jtag_wb_addrsr_update_core$next sync posedge \clk update \jtag_wb_addrsr_update_core $0\jtag_wb_addrsr_update_core[0:0] end - attribute \src "libresoc.v:139314.3-139315.31" - process $proc$libresoc.v:139314$5969 + attribute \src "libresoc.v:140176.3-140177.31" + process $proc$libresoc.v:140176$5953 assign { } { } assign $0\sr0_reg[2:0] \sr0_reg$next sync posedge \posjtag_clk update \sr0_reg $0\sr0_reg[2:0] end - attribute \src "libresoc.v:139316.3-139317.31" - process $proc$libresoc.v:139316$5970 + attribute \src "libresoc.v:140178.3-140179.31" + process $proc$libresoc.v:140178$5954 assign { } { } assign $0\sr0__oe[0:0] \sr0__oe$next sync posedge \clk update \sr0__oe $0\sr0__oe[0:0] end - attribute \src "libresoc.v:139318.3-139319.57" - process $proc$libresoc.v:139318$5971 + attribute \src "libresoc.v:140180.3-140181.57" + process $proc$libresoc.v:140180$5955 assign { } { } assign $0\sr0_update_core_prev[0:0] \sr0_update_core_prev$next sync posedge \clk update \sr0_update_core_prev $0\sr0_update_core_prev[0:0] end - attribute \src "libresoc.v:139320.3-139321.47" - process $proc$libresoc.v:139320$5972 + attribute \src "libresoc.v:140182.3-140183.47" + process $proc$libresoc.v:140182$5956 assign { } { } assign $0\sr0_update_core[0:0] \sr0_update_core$next sync posedge \clk update \sr0_update_core $0\sr0_update_core[0:0] end - attribute \src "libresoc.v:139322.3-139323.27" - process $proc$libresoc.v:139322$5973 + attribute \src "libresoc.v:140184.3-140185.27" + process $proc$libresoc.v:140184$5957 assign { } { } - assign $0\io_bd[151:0] \io_bd$next + assign $0\io_bd[129:0] \io_bd$next sync negedge \negjtag_clk - update \io_bd $0\io_bd[151:0] + update \io_bd $0\io_bd[129:0] end - attribute \src "libresoc.v:139324.3-139325.27" - process $proc$libresoc.v:139324$5974 + attribute \src "libresoc.v:140186.3-140187.27" + process $proc$libresoc.v:140186$5958 assign { } { } - assign $0\io_sr[151:0] \io_sr$next + assign $0\io_sr[129:0] \io_sr$next sync posedge \posjtag_clk - update \io_sr $0\io_sr[151:0] + update \io_sr $0\io_sr[129:0] end - attribute \src "libresoc.v:139361.3-139376.6" - process $proc$libresoc.v:139361$5975 + attribute \src "libresoc.v:140223.3-140238.6" + process $proc$libresoc.v:140223$5959 assign { } { } assign { } { } assign $0\TAP_tdo[0:0] $1\TAP_tdo[0:0] - attribute \src "libresoc.v:139362.5-139362.29" + attribute \src "libresoc.v:140224.5-140224.29" switch \initial - attribute \src "libresoc.v:139362.9-139362.17" + attribute \src "libresoc.v:140224.9-140224.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:415" - switch { \$365 \_idblock_select_id \_fsm_isir } + switch { \$321 \_idblock_select_id \_fsm_isir } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } @@ -222788,21 +223222,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $1\TAP_tdo[0:0] \io_sr [151] + assign $1\TAP_tdo[0:0] \io_sr [129] case assign $1\TAP_tdo[0:0] 1'0 end sync always update \TAP_tdo $0\TAP_tdo[0:0] end - attribute \src "libresoc.v:139377.3-139385.6" - process $proc$libresoc.v:139377$5976 + attribute \src "libresoc.v:140239.3-140247.6" + process $proc$libresoc.v:140239$5960 assign { } { } assign { } { } - assign $0\sr0_update_core$next[0:0]$5977 $1\sr0_update_core$next[0:0]$5978 - attribute \src "libresoc.v:139378.5-139378.29" + assign $0\sr0_update_core$next[0:0]$5961 $1\sr0_update_core$next[0:0]$5962 + attribute \src "libresoc.v:140240.5-140240.29" switch \initial - attribute \src "libresoc.v:139378.9-139378.17" + attribute \src "libresoc.v:140240.9-140240.17" case 1'1 case end @@ -222811,21 +223245,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr0_update_core$next[0:0]$5978 1'0 + assign $1\sr0_update_core$next[0:0]$5962 1'0 case - assign $1\sr0_update_core$next[0:0]$5978 \sr0_update + assign $1\sr0_update_core$next[0:0]$5962 \sr0_update end sync always - update \sr0_update_core$next $0\sr0_update_core$next[0:0]$5977 + update \sr0_update_core$next $0\sr0_update_core$next[0:0]$5961 end - attribute \src "libresoc.v:139386.3-139394.6" - process $proc$libresoc.v:139386$5979 + attribute \src "libresoc.v:140248.3-140256.6" + process $proc$libresoc.v:140248$5963 assign { } { } assign { } { } - assign $0\sr0_update_core_prev$next[0:0]$5980 $1\sr0_update_core_prev$next[0:0]$5981 - attribute \src "libresoc.v:139387.5-139387.29" + assign $0\sr0_update_core_prev$next[0:0]$5964 $1\sr0_update_core_prev$next[0:0]$5965 + attribute \src "libresoc.v:140249.5-140249.29" switch \initial - attribute \src "libresoc.v:139387.9-139387.17" + attribute \src "libresoc.v:140249.9-140249.17" case 1'1 case end @@ -222834,57 +223268,57 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr0_update_core_prev$next[0:0]$5981 1'0 + assign $1\sr0_update_core_prev$next[0:0]$5965 1'0 case - assign $1\sr0_update_core_prev$next[0:0]$5981 \sr0_update_core + assign $1\sr0_update_core_prev$next[0:0]$5965 \sr0_update_core end sync always - update \sr0_update_core_prev$next $0\sr0_update_core_prev$next[0:0]$5980 + update \sr0_update_core_prev$next $0\sr0_update_core_prev$next[0:0]$5964 end - attribute \src "libresoc.v:139395.3-139411.6" - process $proc$libresoc.v:139395$5982 + attribute \src "libresoc.v:140257.3-140273.6" + process $proc$libresoc.v:140257$5966 assign { } { } assign { } { } - assign $0\sr0__oe$next[0:0]$5983 $2\sr0__oe$next[0:0]$5985 - attribute \src "libresoc.v:139396.5-139396.29" + assign $0\sr0__oe$next[0:0]$5967 $2\sr0__oe$next[0:0]$5969 + attribute \src "libresoc.v:140258.5-140258.29" switch \initial - attribute \src "libresoc.v:139396.9-139396.17" + attribute \src "libresoc.v:140258.9-140258.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - switch \$383 + switch \$339 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr0__oe$next[0:0]$5984 \sr0_isir + assign $1\sr0__oe$next[0:0]$5968 \sr0_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\sr0__oe$next[0:0]$5984 1'0 + assign $1\sr0__oe$next[0:0]$5968 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sr0__oe$next[0:0]$5985 1'0 + assign $2\sr0__oe$next[0:0]$5969 1'0 case - assign $2\sr0__oe$next[0:0]$5985 $1\sr0__oe$next[0:0]$5984 + assign $2\sr0__oe$next[0:0]$5969 $1\sr0__oe$next[0:0]$5968 end sync always - update \sr0__oe$next $0\sr0__oe$next[0:0]$5983 + update \sr0__oe$next $0\sr0__oe$next[0:0]$5967 end - attribute \src "libresoc.v:139412.3-139432.6" - process $proc$libresoc.v:139412$5986 + attribute \src "libresoc.v:140274.3-140294.6" + process $proc$libresoc.v:140274$5970 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\sr0_reg$next[2:0]$5987 $3\sr0_reg$next[2:0]$5990 - attribute \src "libresoc.v:139413.5-139413.29" + assign $0\sr0_reg$next[2:0]$5971 $3\sr0_reg$next[2:0]$5974 + attribute \src "libresoc.v:140275.5-140275.29" switch \initial - attribute \src "libresoc.v:139413.9-139413.17" + attribute \src "libresoc.v:140275.9-140275.17" case 1'1 case end @@ -222893,39 +223327,39 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr0_reg$next[2:0]$5988 { \TAP_bus__tdi \sr0_reg [2:1] } + assign $1\sr0_reg$next[2:0]$5972 { \TAP_bus__tdi \sr0_reg [2:1] } case - assign $1\sr0_reg$next[2:0]$5988 \sr0_reg + assign $1\sr0_reg$next[2:0]$5972 \sr0_reg end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch \sr0_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sr0_reg$next[2:0]$5989 \sr0__i + assign $2\sr0_reg$next[2:0]$5973 \sr0__i case - assign $2\sr0_reg$next[2:0]$5989 $1\sr0_reg$next[2:0]$5988 + assign $2\sr0_reg$next[2:0]$5973 $1\sr0_reg$next[2:0]$5972 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sr0_reg$next[2:0]$5990 3'000 + assign $3\sr0_reg$next[2:0]$5974 3'000 case - assign $3\sr0_reg$next[2:0]$5990 $2\sr0_reg$next[2:0]$5989 + assign $3\sr0_reg$next[2:0]$5974 $2\sr0_reg$next[2:0]$5973 end sync always - update \sr0_reg$next $0\sr0_reg$next[2:0]$5987 + update \sr0_reg$next $0\sr0_reg$next[2:0]$5971 end - attribute \src "libresoc.v:139433.3-139441.6" - process $proc$libresoc.v:139433$5991 + attribute \src "libresoc.v:140295.3-140303.6" + process $proc$libresoc.v:140295$5975 assign { } { } assign { } { } - assign $0\jtag_wb_addrsr_update_core$next[0:0]$5992 $1\jtag_wb_addrsr_update_core$next[0:0]$5993 - attribute \src "libresoc.v:139434.5-139434.29" + assign $0\jtag_wb_addrsr_update_core$next[0:0]$5976 $1\jtag_wb_addrsr_update_core$next[0:0]$5977 + attribute \src "libresoc.v:140296.5-140296.29" switch \initial - attribute \src "libresoc.v:139434.9-139434.17" + attribute \src "libresoc.v:140296.9-140296.17" case 1'1 case end @@ -222934,21 +223368,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_addrsr_update_core$next[0:0]$5993 1'0 + assign $1\jtag_wb_addrsr_update_core$next[0:0]$5977 1'0 case - assign $1\jtag_wb_addrsr_update_core$next[0:0]$5993 \jtag_wb_addrsr_update + assign $1\jtag_wb_addrsr_update_core$next[0:0]$5977 \jtag_wb_addrsr_update end sync always - update \jtag_wb_addrsr_update_core$next $0\jtag_wb_addrsr_update_core$next[0:0]$5992 + update \jtag_wb_addrsr_update_core$next $0\jtag_wb_addrsr_update_core$next[0:0]$5976 end - attribute \src "libresoc.v:139442.3-139450.6" - process $proc$libresoc.v:139442$5994 + attribute \src "libresoc.v:140304.3-140312.6" + process $proc$libresoc.v:140304$5978 assign { } { } assign { } { } - assign $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5995 $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5996 - attribute \src "libresoc.v:139443.5-139443.29" + assign $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5979 $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5980 + attribute \src "libresoc.v:140305.5-140305.29" switch \initial - attribute \src "libresoc.v:139443.9-139443.17" + attribute \src "libresoc.v:140305.9-140305.17" case 1'1 case end @@ -222957,57 +223391,57 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5996 1'0 + assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5980 1'0 case - assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5996 \jtag_wb_addrsr_update_core + assign $1\jtag_wb_addrsr_update_core_prev$next[0:0]$5980 \jtag_wb_addrsr_update_core end sync always - update \jtag_wb_addrsr_update_core_prev$next $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5995 + update \jtag_wb_addrsr_update_core_prev$next $0\jtag_wb_addrsr_update_core_prev$next[0:0]$5979 end - attribute \src "libresoc.v:139451.3-139467.6" - process $proc$libresoc.v:139451$5997 + attribute \src "libresoc.v:140313.3-140329.6" + process $proc$libresoc.v:140313$5981 assign { } { } assign { } { } - assign $0\jtag_wb_addrsr__oe$next[0:0]$5998 $2\jtag_wb_addrsr__oe$next[0:0]$6000 - attribute \src "libresoc.v:139452.5-139452.29" + assign $0\jtag_wb_addrsr__oe$next[0:0]$5982 $2\jtag_wb_addrsr__oe$next[0:0]$5984 + attribute \src "libresoc.v:140314.5-140314.29" switch \initial - attribute \src "libresoc.v:139452.9-139452.17" + attribute \src "libresoc.v:140314.9-140314.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - switch \$401 + switch \$357 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_addrsr__oe$next[0:0]$5999 \jtag_wb_addrsr_isir + assign $1\jtag_wb_addrsr__oe$next[0:0]$5983 \jtag_wb_addrsr_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\jtag_wb_addrsr__oe$next[0:0]$5999 1'0 + assign $1\jtag_wb_addrsr__oe$next[0:0]$5983 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\jtag_wb_addrsr__oe$next[0:0]$6000 1'0 + assign $2\jtag_wb_addrsr__oe$next[0:0]$5984 1'0 case - assign $2\jtag_wb_addrsr__oe$next[0:0]$6000 $1\jtag_wb_addrsr__oe$next[0:0]$5999 + assign $2\jtag_wb_addrsr__oe$next[0:0]$5984 $1\jtag_wb_addrsr__oe$next[0:0]$5983 end sync always - update \jtag_wb_addrsr__oe$next $0\jtag_wb_addrsr__oe$next[0:0]$5998 + update \jtag_wb_addrsr__oe$next $0\jtag_wb_addrsr__oe$next[0:0]$5982 end - attribute \src "libresoc.v:139468.3-139488.6" - process $proc$libresoc.v:139468$6001 + attribute \src "libresoc.v:140330.3-140350.6" + process $proc$libresoc.v:140330$5985 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\jtag_wb_addrsr_reg$next[28:0]$6002 $3\jtag_wb_addrsr_reg$next[28:0]$6005 - attribute \src "libresoc.v:139469.5-139469.29" + assign $0\jtag_wb_addrsr_reg$next[28:0]$5986 $3\jtag_wb_addrsr_reg$next[28:0]$5989 + attribute \src "libresoc.v:140331.5-140331.29" switch \initial - attribute \src "libresoc.v:139469.9-139469.17" + attribute \src "libresoc.v:140331.9-140331.17" case 1'1 case end @@ -223016,39 +223450,39 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_addrsr_reg$next[28:0]$6003 { \TAP_bus__tdi \jtag_wb_addrsr_reg [28:1] } + assign $1\jtag_wb_addrsr_reg$next[28:0]$5987 { \TAP_bus__tdi \jtag_wb_addrsr_reg [28:1] } case - assign $1\jtag_wb_addrsr_reg$next[28:0]$6003 \jtag_wb_addrsr_reg + assign $1\jtag_wb_addrsr_reg$next[28:0]$5987 \jtag_wb_addrsr_reg end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch \jtag_wb_addrsr_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\jtag_wb_addrsr_reg$next[28:0]$6004 \jtag_wb_addrsr__i + assign $2\jtag_wb_addrsr_reg$next[28:0]$5988 \jtag_wb_addrsr__i case - assign $2\jtag_wb_addrsr_reg$next[28:0]$6004 $1\jtag_wb_addrsr_reg$next[28:0]$6003 + assign $2\jtag_wb_addrsr_reg$next[28:0]$5988 $1\jtag_wb_addrsr_reg$next[28:0]$5987 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\jtag_wb_addrsr_reg$next[28:0]$6005 29'00000000000000000000000000000 + assign $3\jtag_wb_addrsr_reg$next[28:0]$5989 29'00000000000000000000000000000 case - assign $3\jtag_wb_addrsr_reg$next[28:0]$6005 $2\jtag_wb_addrsr_reg$next[28:0]$6004 + assign $3\jtag_wb_addrsr_reg$next[28:0]$5989 $2\jtag_wb_addrsr_reg$next[28:0]$5988 end sync always - update \jtag_wb_addrsr_reg$next $0\jtag_wb_addrsr_reg$next[28:0]$6002 + update \jtag_wb_addrsr_reg$next $0\jtag_wb_addrsr_reg$next[28:0]$5986 end - attribute \src "libresoc.v:139489.3-139497.6" - process $proc$libresoc.v:139489$6006 + attribute \src "libresoc.v:140351.3-140359.6" + process $proc$libresoc.v:140351$5990 assign { } { } assign { } { } - assign $0\jtag_wb_datasr_update_core$next[0:0]$6007 $1\jtag_wb_datasr_update_core$next[0:0]$6008 - attribute \src "libresoc.v:139490.5-139490.29" + assign $0\jtag_wb_datasr_update_core$next[0:0]$5991 $1\jtag_wb_datasr_update_core$next[0:0]$5992 + attribute \src "libresoc.v:140352.5-140352.29" switch \initial - attribute \src "libresoc.v:139490.9-139490.17" + attribute \src "libresoc.v:140352.9-140352.17" case 1'1 case end @@ -223057,21 +223491,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_datasr_update_core$next[0:0]$6008 1'0 + assign $1\jtag_wb_datasr_update_core$next[0:0]$5992 1'0 case - assign $1\jtag_wb_datasr_update_core$next[0:0]$6008 \jtag_wb_datasr_update + assign $1\jtag_wb_datasr_update_core$next[0:0]$5992 \jtag_wb_datasr_update end sync always - update \jtag_wb_datasr_update_core$next $0\jtag_wb_datasr_update_core$next[0:0]$6007 + update \jtag_wb_datasr_update_core$next $0\jtag_wb_datasr_update_core$next[0:0]$5991 end - attribute \src "libresoc.v:139498.3-139506.6" - process $proc$libresoc.v:139498$6009 + attribute \src "libresoc.v:140360.3-140368.6" + process $proc$libresoc.v:140360$5993 assign { } { } assign { } { } - assign $0\jtag_wb_datasr_update_core_prev$next[0:0]$6010 $1\jtag_wb_datasr_update_core_prev$next[0:0]$6011 - attribute \src "libresoc.v:139499.5-139499.29" + assign $0\jtag_wb_datasr_update_core_prev$next[0:0]$5994 $1\jtag_wb_datasr_update_core_prev$next[0:0]$5995 + attribute \src "libresoc.v:140361.5-140361.29" switch \initial - attribute \src "libresoc.v:139499.9-139499.17" + attribute \src "libresoc.v:140361.9-140361.17" case 1'1 case end @@ -223080,57 +223514,57 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$6011 1'0 + assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$5995 1'0 case - assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$6011 \jtag_wb_datasr_update_core + assign $1\jtag_wb_datasr_update_core_prev$next[0:0]$5995 \jtag_wb_datasr_update_core end sync always - update \jtag_wb_datasr_update_core_prev$next $0\jtag_wb_datasr_update_core_prev$next[0:0]$6010 + update \jtag_wb_datasr_update_core_prev$next $0\jtag_wb_datasr_update_core_prev$next[0:0]$5994 end - attribute \src "libresoc.v:139507.3-139523.6" - process $proc$libresoc.v:139507$6012 + attribute \src "libresoc.v:140369.3-140385.6" + process $proc$libresoc.v:140369$5996 assign { } { } assign { } { } - assign $0\jtag_wb_datasr__oe$next[1:0]$6013 $2\jtag_wb_datasr__oe$next[1:0]$6015 - attribute \src "libresoc.v:139508.5-139508.29" + assign $0\jtag_wb_datasr__oe$next[1:0]$5997 $2\jtag_wb_datasr__oe$next[1:0]$5999 + attribute \src "libresoc.v:140370.5-140370.29" switch \initial - attribute \src "libresoc.v:139508.9-139508.17" + attribute \src "libresoc.v:140370.9-140370.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - switch \$421 + switch \$377 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_datasr__oe$next[1:0]$6014 \jtag_wb_datasr_isir + assign $1\jtag_wb_datasr__oe$next[1:0]$5998 \jtag_wb_datasr_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\jtag_wb_datasr__oe$next[1:0]$6014 2'00 + assign $1\jtag_wb_datasr__oe$next[1:0]$5998 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\jtag_wb_datasr__oe$next[1:0]$6015 2'00 + assign $2\jtag_wb_datasr__oe$next[1:0]$5999 2'00 case - assign $2\jtag_wb_datasr__oe$next[1:0]$6015 $1\jtag_wb_datasr__oe$next[1:0]$6014 + assign $2\jtag_wb_datasr__oe$next[1:0]$5999 $1\jtag_wb_datasr__oe$next[1:0]$5998 end sync always - update \jtag_wb_datasr__oe$next $0\jtag_wb_datasr__oe$next[1:0]$6013 + update \jtag_wb_datasr__oe$next $0\jtag_wb_datasr__oe$next[1:0]$5997 end - attribute \src "libresoc.v:139524.3-139544.6" - process $proc$libresoc.v:139524$6016 + attribute \src "libresoc.v:140386.3-140406.6" + process $proc$libresoc.v:140386$6000 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\jtag_wb_datasr_reg$next[63:0]$6017 $3\jtag_wb_datasr_reg$next[63:0]$6020 - attribute \src "libresoc.v:139525.5-139525.29" + assign $0\jtag_wb_datasr_reg$next[63:0]$6001 $3\jtag_wb_datasr_reg$next[63:0]$6004 + attribute \src "libresoc.v:140387.5-140387.29" switch \initial - attribute \src "libresoc.v:139525.9-139525.17" + attribute \src "libresoc.v:140387.9-140387.17" case 1'1 case end @@ -223139,39 +223573,39 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_wb_datasr_reg$next[63:0]$6018 { \TAP_bus__tdi \jtag_wb_datasr_reg [63:1] } + assign $1\jtag_wb_datasr_reg$next[63:0]$6002 { \TAP_bus__tdi \jtag_wb_datasr_reg [63:1] } case - assign $1\jtag_wb_datasr_reg$next[63:0]$6018 \jtag_wb_datasr_reg + assign $1\jtag_wb_datasr_reg$next[63:0]$6002 \jtag_wb_datasr_reg end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch \jtag_wb_datasr_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\jtag_wb_datasr_reg$next[63:0]$6019 \jtag_wb_datasr__i + assign $2\jtag_wb_datasr_reg$next[63:0]$6003 \jtag_wb_datasr__i case - assign $2\jtag_wb_datasr_reg$next[63:0]$6019 $1\jtag_wb_datasr_reg$next[63:0]$6018 + assign $2\jtag_wb_datasr_reg$next[63:0]$6003 $1\jtag_wb_datasr_reg$next[63:0]$6002 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\jtag_wb_datasr_reg$next[63:0]$6020 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\jtag_wb_datasr_reg$next[63:0]$6004 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\jtag_wb_datasr_reg$next[63:0]$6020 $2\jtag_wb_datasr_reg$next[63:0]$6019 + assign $3\jtag_wb_datasr_reg$next[63:0]$6004 $2\jtag_wb_datasr_reg$next[63:0]$6003 end sync always - update \jtag_wb_datasr_reg$next $0\jtag_wb_datasr_reg$next[63:0]$6017 + update \jtag_wb_datasr_reg$next $0\jtag_wb_datasr_reg$next[63:0]$6001 end - attribute \src "libresoc.v:139545.3-139553.6" - process $proc$libresoc.v:139545$6021 + attribute \src "libresoc.v:140407.3-140415.6" + process $proc$libresoc.v:140407$6005 assign { } { } assign { } { } - assign $0\dmi0_addrsr_update_core$next[0:0]$6022 $1\dmi0_addrsr_update_core$next[0:0]$6023 - attribute \src "libresoc.v:139546.5-139546.29" + assign $0\dmi0_addrsr_update_core$next[0:0]$6006 $1\dmi0_addrsr_update_core$next[0:0]$6007 + attribute \src "libresoc.v:140408.5-140408.29" switch \initial - attribute \src "libresoc.v:139546.9-139546.17" + attribute \src "libresoc.v:140408.9-140408.17" case 1'1 case end @@ -223180,21 +223614,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_addrsr_update_core$next[0:0]$6023 1'0 + assign $1\dmi0_addrsr_update_core$next[0:0]$6007 1'0 case - assign $1\dmi0_addrsr_update_core$next[0:0]$6023 \dmi0_addrsr_update + assign $1\dmi0_addrsr_update_core$next[0:0]$6007 \dmi0_addrsr_update end sync always - update \dmi0_addrsr_update_core$next $0\dmi0_addrsr_update_core$next[0:0]$6022 + update \dmi0_addrsr_update_core$next $0\dmi0_addrsr_update_core$next[0:0]$6006 end - attribute \src "libresoc.v:139554.3-139562.6" - process $proc$libresoc.v:139554$6024 + attribute \src "libresoc.v:140416.3-140424.6" + process $proc$libresoc.v:140416$6008 assign { } { } assign { } { } - assign $0\dmi0_addrsr_update_core_prev$next[0:0]$6025 $1\dmi0_addrsr_update_core_prev$next[0:0]$6026 - attribute \src "libresoc.v:139555.5-139555.29" + assign $0\dmi0_addrsr_update_core_prev$next[0:0]$6009 $1\dmi0_addrsr_update_core_prev$next[0:0]$6010 + attribute \src "libresoc.v:140417.5-140417.29" switch \initial - attribute \src "libresoc.v:139555.9-139555.17" + attribute \src "libresoc.v:140417.9-140417.17" case 1'1 case end @@ -223203,57 +223637,57 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_addrsr_update_core_prev$next[0:0]$6026 1'0 + assign $1\dmi0_addrsr_update_core_prev$next[0:0]$6010 1'0 case - assign $1\dmi0_addrsr_update_core_prev$next[0:0]$6026 \dmi0_addrsr_update_core + assign $1\dmi0_addrsr_update_core_prev$next[0:0]$6010 \dmi0_addrsr_update_core end sync always - update \dmi0_addrsr_update_core_prev$next $0\dmi0_addrsr_update_core_prev$next[0:0]$6025 + update \dmi0_addrsr_update_core_prev$next $0\dmi0_addrsr_update_core_prev$next[0:0]$6009 end - attribute \src "libresoc.v:139563.3-139579.6" - process $proc$libresoc.v:139563$6027 + attribute \src "libresoc.v:140425.3-140441.6" + process $proc$libresoc.v:140425$6011 assign { } { } assign { } { } - assign $0\dmi0_addrsr__oe$next[0:0]$6028 $2\dmi0_addrsr__oe$next[0:0]$6030 - attribute \src "libresoc.v:139564.5-139564.29" + assign $0\dmi0_addrsr__oe$next[0:0]$6012 $2\dmi0_addrsr__oe$next[0:0]$6014 + attribute \src "libresoc.v:140426.5-140426.29" switch \initial - attribute \src "libresoc.v:139564.9-139564.17" + attribute \src "libresoc.v:140426.9-140426.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - switch \$439 + switch \$395 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_addrsr__oe$next[0:0]$6029 \dmi0_addrsr_isir + assign $1\dmi0_addrsr__oe$next[0:0]$6013 \dmi0_addrsr_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\dmi0_addrsr__oe$next[0:0]$6029 1'0 + assign $1\dmi0_addrsr__oe$next[0:0]$6013 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dmi0_addrsr__oe$next[0:0]$6030 1'0 + assign $2\dmi0_addrsr__oe$next[0:0]$6014 1'0 case - assign $2\dmi0_addrsr__oe$next[0:0]$6030 $1\dmi0_addrsr__oe$next[0:0]$6029 + assign $2\dmi0_addrsr__oe$next[0:0]$6014 $1\dmi0_addrsr__oe$next[0:0]$6013 end sync always - update \dmi0_addrsr__oe$next $0\dmi0_addrsr__oe$next[0:0]$6028 + update \dmi0_addrsr__oe$next $0\dmi0_addrsr__oe$next[0:0]$6012 end - attribute \src "libresoc.v:139580.3-139600.6" - process $proc$libresoc.v:139580$6031 + attribute \src "libresoc.v:140442.3-140462.6" + process $proc$libresoc.v:140442$6015 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\dmi0_addrsr_reg$next[7:0]$6032 $3\dmi0_addrsr_reg$next[7:0]$6035 - attribute \src "libresoc.v:139581.5-139581.29" + assign $0\dmi0_addrsr_reg$next[7:0]$6016 $3\dmi0_addrsr_reg$next[7:0]$6019 + attribute \src "libresoc.v:140443.5-140443.29" switch \initial - attribute \src "libresoc.v:139581.9-139581.17" + attribute \src "libresoc.v:140443.9-140443.17" case 1'1 case end @@ -223262,39 +223696,39 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_addrsr_reg$next[7:0]$6033 { \TAP_bus__tdi \dmi0_addrsr_reg [7:1] } + assign $1\dmi0_addrsr_reg$next[7:0]$6017 { \TAP_bus__tdi \dmi0_addrsr_reg [7:1] } case - assign $1\dmi0_addrsr_reg$next[7:0]$6033 \dmi0_addrsr_reg + assign $1\dmi0_addrsr_reg$next[7:0]$6017 \dmi0_addrsr_reg end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch \dmi0_addrsr_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dmi0_addrsr_reg$next[7:0]$6034 \dmi0_addrsr__i + assign $2\dmi0_addrsr_reg$next[7:0]$6018 \dmi0_addrsr__i case - assign $2\dmi0_addrsr_reg$next[7:0]$6034 $1\dmi0_addrsr_reg$next[7:0]$6033 + assign $2\dmi0_addrsr_reg$next[7:0]$6018 $1\dmi0_addrsr_reg$next[7:0]$6017 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dmi0_addrsr_reg$next[7:0]$6035 8'00000000 + assign $3\dmi0_addrsr_reg$next[7:0]$6019 8'00000000 case - assign $3\dmi0_addrsr_reg$next[7:0]$6035 $2\dmi0_addrsr_reg$next[7:0]$6034 + assign $3\dmi0_addrsr_reg$next[7:0]$6019 $2\dmi0_addrsr_reg$next[7:0]$6018 end sync always - update \dmi0_addrsr_reg$next $0\dmi0_addrsr_reg$next[7:0]$6032 + update \dmi0_addrsr_reg$next $0\dmi0_addrsr_reg$next[7:0]$6016 end - attribute \src "libresoc.v:139601.3-139609.6" - process $proc$libresoc.v:139601$6036 + attribute \src "libresoc.v:140463.3-140471.6" + process $proc$libresoc.v:140463$6020 assign { } { } assign { } { } - assign $0\dmi0_datasr_update_core$next[0:0]$6037 $1\dmi0_datasr_update_core$next[0:0]$6038 - attribute \src "libresoc.v:139602.5-139602.29" + assign $0\dmi0_datasr_update_core$next[0:0]$6021 $1\dmi0_datasr_update_core$next[0:0]$6022 + attribute \src "libresoc.v:140464.5-140464.29" switch \initial - attribute \src "libresoc.v:139602.9-139602.17" + attribute \src "libresoc.v:140464.9-140464.17" case 1'1 case end @@ -223303,21 +223737,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_datasr_update_core$next[0:0]$6038 1'0 + assign $1\dmi0_datasr_update_core$next[0:0]$6022 1'0 case - assign $1\dmi0_datasr_update_core$next[0:0]$6038 \dmi0_datasr_update + assign $1\dmi0_datasr_update_core$next[0:0]$6022 \dmi0_datasr_update end sync always - update \dmi0_datasr_update_core$next $0\dmi0_datasr_update_core$next[0:0]$6037 + update \dmi0_datasr_update_core$next $0\dmi0_datasr_update_core$next[0:0]$6021 end - attribute \src "libresoc.v:139610.3-139618.6" - process $proc$libresoc.v:139610$6039 + attribute \src "libresoc.v:140472.3-140480.6" + process $proc$libresoc.v:140472$6023 assign { } { } assign { } { } - assign $0\dmi0_datasr_update_core_prev$next[0:0]$6040 $1\dmi0_datasr_update_core_prev$next[0:0]$6041 - attribute \src "libresoc.v:139611.5-139611.29" + assign $0\dmi0_datasr_update_core_prev$next[0:0]$6024 $1\dmi0_datasr_update_core_prev$next[0:0]$6025 + attribute \src "libresoc.v:140473.5-140473.29" switch \initial - attribute \src "libresoc.v:139611.9-139611.17" + attribute \src "libresoc.v:140473.9-140473.17" case 1'1 case end @@ -223326,57 +223760,57 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_datasr_update_core_prev$next[0:0]$6041 1'0 + assign $1\dmi0_datasr_update_core_prev$next[0:0]$6025 1'0 case - assign $1\dmi0_datasr_update_core_prev$next[0:0]$6041 \dmi0_datasr_update_core + assign $1\dmi0_datasr_update_core_prev$next[0:0]$6025 \dmi0_datasr_update_core end sync always - update \dmi0_datasr_update_core_prev$next $0\dmi0_datasr_update_core_prev$next[0:0]$6040 + update \dmi0_datasr_update_core_prev$next $0\dmi0_datasr_update_core_prev$next[0:0]$6024 end - attribute \src "libresoc.v:139619.3-139635.6" - process $proc$libresoc.v:139619$6042 + attribute \src "libresoc.v:140481.3-140497.6" + process $proc$libresoc.v:140481$6026 assign { } { } assign { } { } - assign $0\dmi0_datasr__oe$next[1:0]$6043 $2\dmi0_datasr__oe$next[1:0]$6045 - attribute \src "libresoc.v:139620.5-139620.29" + assign $0\dmi0_datasr__oe$next[1:0]$6027 $2\dmi0_datasr__oe$next[1:0]$6029 + attribute \src "libresoc.v:140482.5-140482.29" switch \initial - attribute \src "libresoc.v:139620.9-139620.17" + attribute \src "libresoc.v:140482.9-140482.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - switch \$459 + switch \$415 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_datasr__oe$next[1:0]$6044 \dmi0_datasr_isir + assign $1\dmi0_datasr__oe$next[1:0]$6028 \dmi0_datasr_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\dmi0_datasr__oe$next[1:0]$6044 2'00 + assign $1\dmi0_datasr__oe$next[1:0]$6028 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dmi0_datasr__oe$next[1:0]$6045 2'00 + assign $2\dmi0_datasr__oe$next[1:0]$6029 2'00 case - assign $2\dmi0_datasr__oe$next[1:0]$6045 $1\dmi0_datasr__oe$next[1:0]$6044 + assign $2\dmi0_datasr__oe$next[1:0]$6029 $1\dmi0_datasr__oe$next[1:0]$6028 end sync always - update \dmi0_datasr__oe$next $0\dmi0_datasr__oe$next[1:0]$6043 + update \dmi0_datasr__oe$next $0\dmi0_datasr__oe$next[1:0]$6027 end - attribute \src "libresoc.v:139636.3-139656.6" - process $proc$libresoc.v:139636$6046 + attribute \src "libresoc.v:140498.3-140518.6" + process $proc$libresoc.v:140498$6030 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\dmi0_datasr_reg$next[63:0]$6047 $3\dmi0_datasr_reg$next[63:0]$6050 - attribute \src "libresoc.v:139637.5-139637.29" + assign $0\dmi0_datasr_reg$next[63:0]$6031 $3\dmi0_datasr_reg$next[63:0]$6034 + attribute \src "libresoc.v:140499.5-140499.29" switch \initial - attribute \src "libresoc.v:139637.9-139637.17" + attribute \src "libresoc.v:140499.9-140499.17" case 1'1 case end @@ -223385,39 +223819,39 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dmi0_datasr_reg$next[63:0]$6048 { \TAP_bus__tdi \dmi0_datasr_reg [63:1] } + assign $1\dmi0_datasr_reg$next[63:0]$6032 { \TAP_bus__tdi \dmi0_datasr_reg [63:1] } case - assign $1\dmi0_datasr_reg$next[63:0]$6048 \dmi0_datasr_reg + assign $1\dmi0_datasr_reg$next[63:0]$6032 \dmi0_datasr_reg end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch \dmi0_datasr_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dmi0_datasr_reg$next[63:0]$6049 \dmi0_datasr__i + assign $2\dmi0_datasr_reg$next[63:0]$6033 \dmi0_datasr__i case - assign $2\dmi0_datasr_reg$next[63:0]$6049 $1\dmi0_datasr_reg$next[63:0]$6048 + assign $2\dmi0_datasr_reg$next[63:0]$6033 $1\dmi0_datasr_reg$next[63:0]$6032 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dmi0_datasr_reg$next[63:0]$6050 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dmi0_datasr_reg$next[63:0]$6034 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\dmi0_datasr_reg$next[63:0]$6050 $2\dmi0_datasr_reg$next[63:0]$6049 + assign $3\dmi0_datasr_reg$next[63:0]$6034 $2\dmi0_datasr_reg$next[63:0]$6033 end sync always - update \dmi0_datasr_reg$next $0\dmi0_datasr_reg$next[63:0]$6047 + update \dmi0_datasr_reg$next $0\dmi0_datasr_reg$next[63:0]$6031 end - attribute \src "libresoc.v:139657.3-139665.6" - process $proc$libresoc.v:139657$6051 + attribute \src "libresoc.v:140519.3-140527.6" + process $proc$libresoc.v:140519$6035 assign { } { } assign { } { } - assign $0\sr5_update_core$next[0:0]$6052 $1\sr5_update_core$next[0:0]$6053 - attribute \src "libresoc.v:139658.5-139658.29" + assign $0\sr5_update_core$next[0:0]$6036 $1\sr5_update_core$next[0:0]$6037 + attribute \src "libresoc.v:140520.5-140520.29" switch \initial - attribute \src "libresoc.v:139658.9-139658.17" + attribute \src "libresoc.v:140520.9-140520.17" case 1'1 case end @@ -223426,21 +223860,21 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr5_update_core$next[0:0]$6053 1'0 + assign $1\sr5_update_core$next[0:0]$6037 1'0 case - assign $1\sr5_update_core$next[0:0]$6053 \sr5_update + assign $1\sr5_update_core$next[0:0]$6037 \sr5_update end sync always - update \sr5_update_core$next $0\sr5_update_core$next[0:0]$6052 + update \sr5_update_core$next $0\sr5_update_core$next[0:0]$6036 end - attribute \src "libresoc.v:139666.3-139674.6" - process $proc$libresoc.v:139666$6054 + attribute \src "libresoc.v:140528.3-140536.6" + process $proc$libresoc.v:140528$6038 assign { } { } assign { } { } - assign $0\sr5_update_core_prev$next[0:0]$6055 $1\sr5_update_core_prev$next[0:0]$6056 - attribute \src "libresoc.v:139667.5-139667.29" + assign $0\sr5_update_core_prev$next[0:0]$6039 $1\sr5_update_core_prev$next[0:0]$6040 + attribute \src "libresoc.v:140529.5-140529.29" switch \initial - attribute \src "libresoc.v:139667.9-139667.17" + attribute \src "libresoc.v:140529.9-140529.17" case 1'1 case end @@ -223449,57 +223883,57 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr5_update_core_prev$next[0:0]$6056 1'0 + assign $1\sr5_update_core_prev$next[0:0]$6040 1'0 case - assign $1\sr5_update_core_prev$next[0:0]$6056 \sr5_update_core + assign $1\sr5_update_core_prev$next[0:0]$6040 \sr5_update_core end sync always - update \sr5_update_core_prev$next $0\sr5_update_core_prev$next[0:0]$6055 + update \sr5_update_core_prev$next $0\sr5_update_core_prev$next[0:0]$6039 end - attribute \src "libresoc.v:139675.3-139691.6" - process $proc$libresoc.v:139675$6057 + attribute \src "libresoc.v:140537.3-140553.6" + process $proc$libresoc.v:140537$6041 assign { } { } assign { } { } - assign $0\sr5__oe$next[0:0]$6058 $2\sr5__oe$next[0:0]$6060 - attribute \src "libresoc.v:139676.5-139676.29" + assign $0\sr5__oe$next[0:0]$6042 $2\sr5__oe$next[0:0]$6044 + attribute \src "libresoc.v:140538.5-140538.29" switch \initial - attribute \src "libresoc.v:139676.9-139676.17" + attribute \src "libresoc.v:140538.9-140538.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:667" - switch \$477 + switch \$433 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr5__oe$next[0:0]$6059 \sr5_isir + assign $1\sr5__oe$next[0:0]$6043 \sr5_isir attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\sr5__oe$next[0:0]$6059 1'0 + assign $1\sr5__oe$next[0:0]$6043 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sr5__oe$next[0:0]$6060 1'0 + assign $2\sr5__oe$next[0:0]$6044 1'0 case - assign $2\sr5__oe$next[0:0]$6060 $1\sr5__oe$next[0:0]$6059 + assign $2\sr5__oe$next[0:0]$6044 $1\sr5__oe$next[0:0]$6043 end sync always - update \sr5__oe$next $0\sr5__oe$next[0:0]$6058 + update \sr5__oe$next $0\sr5__oe$next[0:0]$6042 end - attribute \src "libresoc.v:139692.3-139712.6" - process $proc$libresoc.v:139692$6061 + attribute \src "libresoc.v:140554.3-140574.6" + process $proc$libresoc.v:140554$6045 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\sr5_reg$next[2:0]$6062 $3\sr5_reg$next[2:0]$6065 - attribute \src "libresoc.v:139693.5-139693.29" + assign $0\sr5_reg$next[2:0]$6046 $3\sr5_reg$next[2:0]$6049 + attribute \src "libresoc.v:140555.5-140555.29" switch \initial - attribute \src "libresoc.v:139693.9-139693.17" + attribute \src "libresoc.v:140555.9-140555.17" case 1'1 case end @@ -223508,38 +223942,38 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sr5_reg$next[2:0]$6063 { \TAP_bus__tdi \sr5_reg [2:1] } + assign $1\sr5_reg$next[2:0]$6047 { \TAP_bus__tdi \sr5_reg [2:1] } case - assign $1\sr5_reg$next[2:0]$6063 \sr5_reg + assign $1\sr5_reg$next[2:0]$6047 \sr5_reg end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:675" switch \sr5_capture attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sr5_reg$next[2:0]$6064 \sr5__i + assign $2\sr5_reg$next[2:0]$6048 \sr5__i case - assign $2\sr5_reg$next[2:0]$6064 $1\sr5_reg$next[2:0]$6063 + assign $2\sr5_reg$next[2:0]$6048 $1\sr5_reg$next[2:0]$6047 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sr5_reg$next[2:0]$6065 3'000 + assign $3\sr5_reg$next[2:0]$6049 3'000 case - assign $3\sr5_reg$next[2:0]$6065 $2\sr5_reg$next[2:0]$6064 + assign $3\sr5_reg$next[2:0]$6049 $2\sr5_reg$next[2:0]$6048 end sync always - update \sr5_reg$next $0\sr5_reg$next[2:0]$6062 + update \sr5_reg$next $0\sr5_reg$next[2:0]$6046 end - attribute \src "libresoc.v:139713.3-139739.6" - process $proc$libresoc.v:139713$6066 + attribute \src "libresoc.v:140575.3-140601.6" + process $proc$libresoc.v:140575$6050 assign { } { } assign $0\TAP_bus__tdo[0:0] $1\TAP_bus__tdo[0:0] - attribute \src "libresoc.v:139714.5-139714.29" + attribute \src "libresoc.v:140576.5-140576.29" switch \initial - attribute \src "libresoc.v:139714.9-139714.17" + attribute \src "libresoc.v:140576.9-140576.17" case 1'1 case end @@ -223577,15 +224011,15 @@ module \jtag sync always update \TAP_bus__tdo $0\TAP_bus__tdo[0:0] end - attribute \src "libresoc.v:139740.3-139772.6" - process $proc$libresoc.v:139740$6067 + attribute \src "libresoc.v:140602.3-140646.6" + process $proc$libresoc.v:140602$6051 assign { } { } assign { } { } assign { } { } - assign $0\jtag_wb__adr$next[28:0]$6068 $4\jtag_wb__adr$next[28:0]$6072 - attribute \src "libresoc.v:139741.5-139741.29" + assign $0\jtag_wb__adr$next[28:0]$6052 $4\jtag_wb__adr$next[28:0]$6056 + attribute \src "libresoc.v:140603.5-140603.29" switch \initial - attribute \src "libresoc.v:139741.9-139741.17" + attribute \src "libresoc.v:140603.9-140603.17" case 1'1 case end @@ -223594,57 +224028,66 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\jtag_wb__adr$next[28:0]$6069 $2\jtag_wb__adr$next[28:0]$6070 + assign $1\jtag_wb__adr$next[28:0]$6053 $2\jtag_wb__adr$next[28:0]$6054 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $2\jtag_wb__adr$next[28:0]$6070 \jtag_wb_addrsr__o + assign $2\jtag_wb__adr$next[28:0]$6054 \jtag_wb_addrsr__o attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } - assign $2\jtag_wb__adr$next[28:0]$6070 \$491 [28:0] + assign $2\jtag_wb__adr$next[28:0]$6054 \$447 [28:0] case - assign $2\jtag_wb__adr$next[28:0]$6070 \jtag_wb__adr + assign $2\jtag_wb__adr$next[28:0]$6054 \jtag_wb__adr end attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\jtag_wb__adr$next[28:0]$6053 \jtag_wb__adr + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\jtag_wb__adr$next[28:0]$6053 \jtag_wb__adr + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\jtag_wb__adr$next[28:0]$6053 \jtag_wb__adr + attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } - assign $1\jtag_wb__adr$next[28:0]$6069 $3\jtag_wb__adr$next[28:0]$6071 + assign $1\jtag_wb__adr$next[28:0]$6053 $3\jtag_wb__adr$next[28:0]$6055 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785" switch \jtag_wb__ack attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\jtag_wb__adr$next[28:0]$6071 \$494 [28:0] + assign $3\jtag_wb__adr$next[28:0]$6055 \$450 [28:0] case - assign $3\jtag_wb__adr$next[28:0]$6071 \jtag_wb__adr + assign $3\jtag_wb__adr$next[28:0]$6055 \jtag_wb__adr end case - assign $1\jtag_wb__adr$next[28:0]$6069 \jtag_wb__adr + assign $1\jtag_wb__adr$next[28:0]$6053 \jtag_wb__adr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\jtag_wb__adr$next[28:0]$6072 29'00000000000000000000000000000 + assign $4\jtag_wb__adr$next[28:0]$6056 29'00000000000000000000000000000 case - assign $4\jtag_wb__adr$next[28:0]$6072 $1\jtag_wb__adr$next[28:0]$6069 + assign $4\jtag_wb__adr$next[28:0]$6056 $1\jtag_wb__adr$next[28:0]$6053 end sync always - update \jtag_wb__adr$next $0\jtag_wb__adr$next[28:0]$6068 + update \jtag_wb__adr$next $0\jtag_wb__adr$next[28:0]$6052 end - attribute \src "libresoc.v:139773.3-139825.6" - process $proc$libresoc.v:139773$6073 + attribute \src "libresoc.v:140647.3-140699.6" + process $proc$libresoc.v:140647$6057 assign { } { } assign { } { } assign { } { } - assign $0\fsm_state$next[2:0]$6074 $5\fsm_state$next[2:0]$6079 - attribute \src "libresoc.v:139774.5-139774.29" + assign $0\fsm_state$next[2:0]$6058 $5\fsm_state$next[2:0]$6063 + attribute \src "libresoc.v:140648.5-140648.29" switch \initial - attribute \src "libresoc.v:139774.9-139774.17" + attribute \src "libresoc.v:140648.9-140648.17" case 1'1 case end @@ -223653,82 +224096,82 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\fsm_state$next[2:0]$6075 $2\fsm_state$next[2:0]$6076 + assign $1\fsm_state$next[2:0]$6059 $2\fsm_state$next[2:0]$6060 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $2\fsm_state$next[2:0]$6076 3'001 + assign $2\fsm_state$next[2:0]$6060 3'001 attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } - assign $2\fsm_state$next[2:0]$6076 3'001 + assign $2\fsm_state$next[2:0]$6060 3'001 attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $2\fsm_state$next[2:0]$6076 3'010 + assign $2\fsm_state$next[2:0]$6060 3'010 case - assign $2\fsm_state$next[2:0]$6076 \fsm_state + assign $2\fsm_state$next[2:0]$6060 \fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } - assign $1\fsm_state$next[2:0]$6075 3'011 + assign $1\fsm_state$next[2:0]$6059 3'011 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } - assign $1\fsm_state$next[2:0]$6075 $3\fsm_state$next[2:0]$6077 + assign $1\fsm_state$next[2:0]$6059 $3\fsm_state$next[2:0]$6061 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773" switch \jtag_wb__ack attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fsm_state$next[2:0]$6077 3'000 + assign $3\fsm_state$next[2:0]$6061 3'000 case - assign $3\fsm_state$next[2:0]$6077 \fsm_state + assign $3\fsm_state$next[2:0]$6061 \fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } - assign $1\fsm_state$next[2:0]$6075 3'100 + assign $1\fsm_state$next[2:0]$6059 3'100 attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } - assign $1\fsm_state$next[2:0]$6075 $4\fsm_state$next[2:0]$6078 + assign $1\fsm_state$next[2:0]$6059 $4\fsm_state$next[2:0]$6062 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:785" switch \jtag_wb__ack attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\fsm_state$next[2:0]$6078 3'001 + assign $4\fsm_state$next[2:0]$6062 3'001 case - assign $4\fsm_state$next[2:0]$6078 \fsm_state + assign $4\fsm_state$next[2:0]$6062 \fsm_state end case - assign $1\fsm_state$next[2:0]$6075 \fsm_state + assign $1\fsm_state$next[2:0]$6059 \fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fsm_state$next[2:0]$6079 3'000 + assign $5\fsm_state$next[2:0]$6063 3'000 case - assign $5\fsm_state$next[2:0]$6079 $1\fsm_state$next[2:0]$6075 + assign $5\fsm_state$next[2:0]$6063 $1\fsm_state$next[2:0]$6059 end sync always - update \fsm_state$next $0\fsm_state$next[2:0]$6074 + update \fsm_state$next $0\fsm_state$next[2:0]$6058 end - attribute \src "libresoc.v:139826.3-139852.6" - process $proc$libresoc.v:139826$6080 + attribute \src "libresoc.v:140700.3-140726.6" + process $proc$libresoc.v:140700$6064 assign { } { } assign { } { } assign { } { } - assign $0\jtag_wb__dat_w$next[63:0]$6081 $3\jtag_wb__dat_w$next[63:0]$6084 - attribute \src "libresoc.v:139827.5-139827.29" + assign $0\jtag_wb__dat_w$next[63:0]$6065 $3\jtag_wb__dat_w$next[63:0]$6068 + attribute \src "libresoc.v:140701.5-140701.29" switch \initial - attribute \src "libresoc.v:139827.9-139827.17" + attribute \src "libresoc.v:140701.9-140701.17" case 1'1 case end @@ -223737,314 +224180,335 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\jtag_wb__dat_w$next[63:0]$6082 $2\jtag_wb__dat_w$next[63:0]$6083 + assign $1\jtag_wb__dat_w$next[63:0]$6066 $2\jtag_wb__dat_w$next[63:0]$6067 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:756" switch { \jtag_wb_datasr__oe \jtag_wb_addrsr__oe } attribute \src "libresoc.v:0.0-0.0" case 3'--1 - assign $2\jtag_wb__dat_w$next[63:0]$6083 \jtag_wb__dat_w + assign $2\jtag_wb__dat_w$next[63:0]$6067 \jtag_wb__dat_w attribute \src "libresoc.v:0.0-0.0" case 3'-1- - assign $2\jtag_wb__dat_w$next[63:0]$6083 \jtag_wb__dat_w + assign $2\jtag_wb__dat_w$next[63:0]$6067 \jtag_wb__dat_w attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $2\jtag_wb__dat_w$next[63:0]$6083 \jtag_wb_datasr__o + assign $2\jtag_wb__dat_w$next[63:0]$6067 \jtag_wb_datasr__o case - assign $2\jtag_wb__dat_w$next[63:0]$6083 \jtag_wb__dat_w + assign $2\jtag_wb__dat_w$next[63:0]$6067 \jtag_wb__dat_w end case - assign $1\jtag_wb__dat_w$next[63:0]$6082 \jtag_wb__dat_w + assign $1\jtag_wb__dat_w$next[63:0]$6066 \jtag_wb__dat_w end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\jtag_wb__dat_w$next[63:0]$6084 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\jtag_wb__dat_w$next[63:0]$6068 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\jtag_wb__dat_w$next[63:0]$6084 $1\jtag_wb__dat_w$next[63:0]$6082 + assign $3\jtag_wb__dat_w$next[63:0]$6068 $1\jtag_wb__dat_w$next[63:0]$6066 end sync always - update \jtag_wb__dat_w$next $0\jtag_wb__dat_w$next[63:0]$6081 + update \jtag_wb__dat_w$next $0\jtag_wb__dat_w$next[63:0]$6065 end - attribute \src "libresoc.v:139853.3-139873.6" - process $proc$libresoc.v:139853$6085 + attribute \src "libresoc.v:140727.3-140755.6" + process $proc$libresoc.v:140727$6069 assign { } { } assign { } { } assign { } { } - assign $0\jtag_wb_datasr__i$next[63:0]$6086 $3\jtag_wb_datasr__i$next[63:0]$6089 - attribute \src "libresoc.v:139854.5-139854.29" + assign $0\jtag_wb_datasr__i$next[63:0]$6070 $3\jtag_wb_datasr__i$next[63:0]$6073 + attribute \src "libresoc.v:140728.5-140728.29" switch \initial - attribute \src "libresoc.v:139854.9-139854.17" + attribute \src "libresoc.v:140728.9-140728.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:754" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\jtag_wb_datasr__i$next[63:0]$6071 \jtag_wb_datasr__i + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\jtag_wb_datasr__i$next[63:0]$6071 \jtag_wb_datasr__i + attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } - assign $1\jtag_wb_datasr__i$next[63:0]$6087 $2\jtag_wb_datasr__i$next[63:0]$6088 + assign $1\jtag_wb_datasr__i$next[63:0]$6071 $2\jtag_wb_datasr__i$next[63:0]$6072 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:773" switch \jtag_wb__ack attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\jtag_wb_datasr__i$next[63:0]$6088 \jtag_wb__dat_r + assign $2\jtag_wb_datasr__i$next[63:0]$6072 \jtag_wb__dat_r case - assign $2\jtag_wb_datasr__i$next[63:0]$6088 \jtag_wb_datasr__i + assign $2\jtag_wb_datasr__i$next[63:0]$6072 \jtag_wb_datasr__i end case - assign $1\jtag_wb_datasr__i$next[63:0]$6087 \jtag_wb_datasr__i + assign $1\jtag_wb_datasr__i$next[63:0]$6071 \jtag_wb_datasr__i end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\jtag_wb_datasr__i$next[63:0]$6089 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\jtag_wb_datasr__i$next[63:0]$6073 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\jtag_wb_datasr__i$next[63:0]$6089 $1\jtag_wb_datasr__i$next[63:0]$6087 + assign $3\jtag_wb_datasr__i$next[63:0]$6073 $1\jtag_wb_datasr__i$next[63:0]$6071 end sync always - update \jtag_wb_datasr__i$next $0\jtag_wb_datasr__i$next[63:0]$6086 + update \jtag_wb_datasr__i$next $0\jtag_wb_datasr__i$next[63:0]$6070 end - attribute \src "libresoc.v:139874.3-139906.6" - process $proc$libresoc.v:139874$6090 + attribute \src "libresoc.v:140756.3-140800.6" + process $proc$libresoc.v:140756$6074 assign { } { } assign { } { } assign { } { } - assign $0\dmi0__addr_i$next[3:0]$6091 $4\dmi0__addr_i$next[3:0]$6095 - attribute \src "libresoc.v:139875.5-139875.29" + assign $0\dmi0__addr_i$next[3:0]$6075 $4\dmi0__addr_i$next[3:0]$6079 + attribute \src "libresoc.v:140757.5-140757.29" switch \initial - attribute \src "libresoc.v:139875.9-139875.17" + attribute \src "libresoc.v:140757.9-140757.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - switch \fsm_state$499 + switch \fsm_state$455 attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\dmi0__addr_i$next[3:0]$6092 $2\dmi0__addr_i$next[3:0]$6093 + assign $1\dmi0__addr_i$next[3:0]$6076 $2\dmi0__addr_i$next[3:0]$6077 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" switch { \dmi0_datasr__oe \dmi0_addrsr__oe } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $2\dmi0__addr_i$next[3:0]$6093 \dmi0_addrsr__o [3:0] + assign $2\dmi0__addr_i$next[3:0]$6077 \dmi0_addrsr__o [3:0] attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } - assign $2\dmi0__addr_i$next[3:0]$6093 \$508 [3:0] + assign $2\dmi0__addr_i$next[3:0]$6077 \$464 [3:0] case - assign $2\dmi0__addr_i$next[3:0]$6093 \dmi0__addr_i + assign $2\dmi0__addr_i$next[3:0]$6077 \dmi0__addr_i end attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\dmi0__addr_i$next[3:0]$6076 \dmi0__addr_i + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\dmi0__addr_i$next[3:0]$6076 \dmi0__addr_i + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\dmi0__addr_i$next[3:0]$6076 \dmi0__addr_i + attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } - assign $1\dmi0__addr_i$next[3:0]$6092 $3\dmi0__addr_i$next[3:0]$6094 + assign $1\dmi0__addr_i$next[3:0]$6076 $3\dmi0__addr_i$next[3:0]$6078 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517" switch \dmi0__ack_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dmi0__addr_i$next[3:0]$6094 \$511 [3:0] + assign $3\dmi0__addr_i$next[3:0]$6078 \$467 [3:0] case - assign $3\dmi0__addr_i$next[3:0]$6094 \dmi0__addr_i + assign $3\dmi0__addr_i$next[3:0]$6078 \dmi0__addr_i end case - assign $1\dmi0__addr_i$next[3:0]$6092 \dmi0__addr_i + assign $1\dmi0__addr_i$next[3:0]$6076 \dmi0__addr_i end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\dmi0__addr_i$next[3:0]$6095 4'0000 + assign $4\dmi0__addr_i$next[3:0]$6079 4'0000 case - assign $4\dmi0__addr_i$next[3:0]$6095 $1\dmi0__addr_i$next[3:0]$6092 + assign $4\dmi0__addr_i$next[3:0]$6079 $1\dmi0__addr_i$next[3:0]$6076 end sync always - update \dmi0__addr_i$next $0\dmi0__addr_i$next[3:0]$6091 + update \dmi0__addr_i$next $0\dmi0__addr_i$next[3:0]$6075 end - attribute \src "libresoc.v:139907.3-139959.6" - process $proc$libresoc.v:139907$6096 + attribute \src "libresoc.v:140801.3-140853.6" + process $proc$libresoc.v:140801$6080 assign { } { } assign { } { } assign { } { } - assign $0\fsm_state$499$next[2:0]$6097 $5\fsm_state$499$next[2:0]$6102 - attribute \src "libresoc.v:139908.5-139908.29" + assign $0\fsm_state$455$next[2:0]$6081 $5\fsm_state$455$next[2:0]$6086 + attribute \src "libresoc.v:140802.5-140802.29" switch \initial - attribute \src "libresoc.v:139908.9-139908.17" + attribute \src "libresoc.v:140802.9-140802.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - switch \fsm_state$499 + switch \fsm_state$455 attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\fsm_state$499$next[2:0]$6098 $2\fsm_state$499$next[2:0]$6099 + assign $1\fsm_state$455$next[2:0]$6082 $2\fsm_state$455$next[2:0]$6083 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" switch { \dmi0_datasr__oe \dmi0_addrsr__oe } attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $2\fsm_state$499$next[2:0]$6099 3'001 + assign $2\fsm_state$455$next[2:0]$6083 3'001 attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } - assign $2\fsm_state$499$next[2:0]$6099 3'001 + assign $2\fsm_state$455$next[2:0]$6083 3'001 attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $2\fsm_state$499$next[2:0]$6099 3'010 + assign $2\fsm_state$455$next[2:0]$6083 3'010 case - assign $2\fsm_state$499$next[2:0]$6099 \fsm_state$499 + assign $2\fsm_state$455$next[2:0]$6083 \fsm_state$455 end attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } - assign $1\fsm_state$499$next[2:0]$6098 3'011 + assign $1\fsm_state$455$next[2:0]$6082 3'011 attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } - assign $1\fsm_state$499$next[2:0]$6098 $3\fsm_state$499$next[2:0]$6100 + assign $1\fsm_state$455$next[2:0]$6082 $3\fsm_state$455$next[2:0]$6084 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506" switch \dmi0__ack_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fsm_state$499$next[2:0]$6100 3'000 + assign $3\fsm_state$455$next[2:0]$6084 3'000 case - assign $3\fsm_state$499$next[2:0]$6100 \fsm_state$499 + assign $3\fsm_state$455$next[2:0]$6084 \fsm_state$455 end attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } - assign $1\fsm_state$499$next[2:0]$6098 3'100 + assign $1\fsm_state$455$next[2:0]$6082 3'100 attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } - assign $1\fsm_state$499$next[2:0]$6098 $4\fsm_state$499$next[2:0]$6101 + assign $1\fsm_state$455$next[2:0]$6082 $4\fsm_state$455$next[2:0]$6085 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:517" switch \dmi0__ack_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\fsm_state$499$next[2:0]$6101 3'001 + assign $4\fsm_state$455$next[2:0]$6085 3'001 case - assign $4\fsm_state$499$next[2:0]$6101 \fsm_state$499 + assign $4\fsm_state$455$next[2:0]$6085 \fsm_state$455 end case - assign $1\fsm_state$499$next[2:0]$6098 \fsm_state$499 + assign $1\fsm_state$455$next[2:0]$6082 \fsm_state$455 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fsm_state$499$next[2:0]$6102 3'000 + assign $5\fsm_state$455$next[2:0]$6086 3'000 case - assign $5\fsm_state$499$next[2:0]$6102 $1\fsm_state$499$next[2:0]$6098 + assign $5\fsm_state$455$next[2:0]$6086 $1\fsm_state$455$next[2:0]$6082 end sync always - update \fsm_state$499$next $0\fsm_state$499$next[2:0]$6097 + update \fsm_state$455$next $0\fsm_state$455$next[2:0]$6081 end - attribute \src "libresoc.v:139960.3-139986.6" - process $proc$libresoc.v:139960$6103 + attribute \src "libresoc.v:140854.3-140880.6" + process $proc$libresoc.v:140854$6087 assign { } { } assign { } { } assign { } { } - assign $0\dmi0__din$next[63:0]$6104 $3\dmi0__din$next[63:0]$6107 - attribute \src "libresoc.v:139961.5-139961.29" + assign $0\dmi0__din$next[63:0]$6088 $3\dmi0__din$next[63:0]$6091 + attribute \src "libresoc.v:140855.5-140855.29" switch \initial - attribute \src "libresoc.v:139961.9-139961.17" + attribute \src "libresoc.v:140855.9-140855.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - switch \fsm_state$499 + switch \fsm_state$455 attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\dmi0__din$next[63:0]$6105 $2\dmi0__din$next[63:0]$6106 + assign $1\dmi0__din$next[63:0]$6089 $2\dmi0__din$next[63:0]$6090 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:489" switch { \dmi0_datasr__oe \dmi0_addrsr__oe } attribute \src "libresoc.v:0.0-0.0" case 3'--1 - assign $2\dmi0__din$next[63:0]$6106 \dmi0__din + assign $2\dmi0__din$next[63:0]$6090 \dmi0__din attribute \src "libresoc.v:0.0-0.0" case 3'-1- - assign $2\dmi0__din$next[63:0]$6106 \dmi0__din + assign $2\dmi0__din$next[63:0]$6090 \dmi0__din attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $2\dmi0__din$next[63:0]$6106 \dmi0_datasr__o + assign $2\dmi0__din$next[63:0]$6090 \dmi0_datasr__o case - assign $2\dmi0__din$next[63:0]$6106 \dmi0__din + assign $2\dmi0__din$next[63:0]$6090 \dmi0__din end case - assign $1\dmi0__din$next[63:0]$6105 \dmi0__din + assign $1\dmi0__din$next[63:0]$6089 \dmi0__din end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dmi0__din$next[63:0]$6107 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dmi0__din$next[63:0]$6091 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\dmi0__din$next[63:0]$6107 $1\dmi0__din$next[63:0]$6105 + assign $3\dmi0__din$next[63:0]$6091 $1\dmi0__din$next[63:0]$6089 end sync always - update \dmi0__din$next $0\dmi0__din$next[63:0]$6104 + update \dmi0__din$next $0\dmi0__din$next[63:0]$6088 end - attribute \src "libresoc.v:139987.3-140007.6" - process $proc$libresoc.v:139987$6108 + attribute \src "libresoc.v:140881.3-140909.6" + process $proc$libresoc.v:140881$6092 assign { } { } assign { } { } assign { } { } - assign $0\dmi0_datasr__i$next[63:0]$6109 $3\dmi0_datasr__i$next[63:0]$6112 - attribute \src "libresoc.v:139988.5-139988.29" + assign $0\dmi0_datasr__i$next[63:0]$6093 $3\dmi0_datasr__i$next[63:0]$6096 + attribute \src "libresoc.v:140882.5-140882.29" switch \initial - attribute \src "libresoc.v:139988.9-139988.17" + attribute \src "libresoc.v:140882.9-140882.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:485" - switch \fsm_state$499 + switch \fsm_state$455 + attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\dmi0_datasr__i$next[63:0]$6094 \dmi0_datasr__i + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\dmi0_datasr__i$next[63:0]$6094 \dmi0_datasr__i attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } - assign $1\dmi0_datasr__i$next[63:0]$6110 $2\dmi0_datasr__i$next[63:0]$6111 + assign $1\dmi0_datasr__i$next[63:0]$6094 $2\dmi0_datasr__i$next[63:0]$6095 attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:506" switch \dmi0__ack_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dmi0_datasr__i$next[63:0]$6111 \dmi0__dout + assign $2\dmi0_datasr__i$next[63:0]$6095 \dmi0__dout case - assign $2\dmi0_datasr__i$next[63:0]$6111 \dmi0_datasr__i + assign $2\dmi0_datasr__i$next[63:0]$6095 \dmi0_datasr__i end case - assign $1\dmi0_datasr__i$next[63:0]$6110 \dmi0_datasr__i + assign $1\dmi0_datasr__i$next[63:0]$6094 \dmi0_datasr__i end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dmi0_datasr__i$next[63:0]$6112 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dmi0_datasr__i$next[63:0]$6096 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\dmi0_datasr__i$next[63:0]$6112 $1\dmi0_datasr__i$next[63:0]$6110 + assign $3\dmi0_datasr__i$next[63:0]$6096 $1\dmi0_datasr__i$next[63:0]$6094 end sync always - update \dmi0_datasr__i$next $0\dmi0_datasr__i$next[63:0]$6109 + update \dmi0_datasr__i$next $0\dmi0_datasr__i$next[63:0]$6093 end - attribute \src "libresoc.v:140008.3-140028.6" - process $proc$libresoc.v:140008$6113 + attribute \src "libresoc.v:140910.3-140930.6" + process $proc$libresoc.v:140910$6097 assign { } { } assign { } { } assign { } { } @@ -224054,12 +224518,12 @@ module \jtag assign { } { } assign { } { } assign { } { } - assign $0\wb_dcache_en$next[0:0]$6114 $2\wb_dcache_en$next[0:0]$6120 - assign $0\wb_icache_en$next[0:0]$6115 $2\wb_icache_en$next[0:0]$6121 - assign $0\wb_sram_en$next[0:0]$6116 $2\wb_sram_en$next[0:0]$6122 - attribute \src "libresoc.v:140009.5-140009.29" + assign $0\wb_dcache_en$next[0:0]$6098 $2\wb_dcache_en$next[0:0]$6104 + assign $0\wb_icache_en$next[0:0]$6099 $2\wb_icache_en$next[0:0]$6105 + assign $0\wb_sram_en$next[0:0]$6100 $2\wb_sram_en$next[0:0]$6106 + attribute \src "libresoc.v:140911.5-140911.29" switch \initial - attribute \src "libresoc.v:140009.9-140009.17" + attribute \src "libresoc.v:140911.9-140911.17" case 1'1 case end @@ -224070,11 +224534,11 @@ module \jtag assign { } { } assign { } { } assign { } { } - assign { $1\wb_sram_en$next[0:0]$6119 $1\wb_dcache_en$next[0:0]$6117 $1\wb_icache_en$next[0:0]$6118 } \sr5__o + assign { $1\wb_sram_en$next[0:0]$6103 $1\wb_dcache_en$next[0:0]$6101 $1\wb_icache_en$next[0:0]$6102 } \sr5__o case - assign $1\wb_dcache_en$next[0:0]$6117 \wb_dcache_en - assign $1\wb_icache_en$next[0:0]$6118 \wb_icache_en - assign $1\wb_sram_en$next[0:0]$6119 \wb_sram_en + assign $1\wb_dcache_en$next[0:0]$6101 \wb_dcache_en + assign $1\wb_icache_en$next[0:0]$6102 \wb_icache_en + assign $1\wb_sram_en$next[0:0]$6103 \wb_sram_en end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -224083,27 +224547,27 @@ module \jtag assign { } { } assign { } { } assign { } { } - assign $2\wb_icache_en$next[0:0]$6121 1'1 - assign $2\wb_dcache_en$next[0:0]$6120 1'1 - assign $2\wb_sram_en$next[0:0]$6122 1'1 + assign $2\wb_icache_en$next[0:0]$6105 1'1 + assign $2\wb_dcache_en$next[0:0]$6104 1'1 + assign $2\wb_sram_en$next[0:0]$6106 1'1 case - assign $2\wb_dcache_en$next[0:0]$6120 $1\wb_dcache_en$next[0:0]$6117 - assign $2\wb_icache_en$next[0:0]$6121 $1\wb_icache_en$next[0:0]$6118 - assign $2\wb_sram_en$next[0:0]$6122 $1\wb_sram_en$next[0:0]$6119 + assign $2\wb_dcache_en$next[0:0]$6104 $1\wb_dcache_en$next[0:0]$6101 + assign $2\wb_icache_en$next[0:0]$6105 $1\wb_icache_en$next[0:0]$6102 + assign $2\wb_sram_en$next[0:0]$6106 $1\wb_sram_en$next[0:0]$6103 end sync always - update \wb_dcache_en$next $0\wb_dcache_en$next[0:0]$6114 - update \wb_icache_en$next $0\wb_icache_en$next[0:0]$6115 - update \wb_sram_en$next $0\wb_sram_en$next[0:0]$6116 + update \wb_dcache_en$next $0\wb_dcache_en$next[0:0]$6098 + update \wb_icache_en$next $0\wb_icache_en$next[0:0]$6099 + update \wb_sram_en$next $0\wb_sram_en$next[0:0]$6100 end - attribute \src "libresoc.v:140029.3-140038.6" - process $proc$libresoc.v:140029$6123 + attribute \src "libresoc.v:140931.3-140940.6" + process $proc$libresoc.v:140931$6107 assign { } { } assign { } { } assign $0\sr5__i[2:0] $1\sr5__i[2:0] - attribute \src "libresoc.v:140030.5-140030.29" + attribute \src "libresoc.v:140932.5-140932.29" switch \initial - attribute \src "libresoc.v:140030.9-140030.17" + attribute \src "libresoc.v:140932.9-140932.17" case 1'1 case end @@ -224119,15 +224583,15 @@ module \jtag sync always update \sr5__i $0\sr5__i[2:0] end - attribute \src "libresoc.v:140039.3-140056.6" - process $proc$libresoc.v:140039$6124 + attribute \src "libresoc.v:140941.3-140958.6" + process $proc$libresoc.v:140941$6108 assign { } { } assign { } { } assign { } { } - assign $0\io_sr$next[151:0]$6125 $2\io_sr$next[151:0]$6127 - attribute \src "libresoc.v:140040.5-140040.29" + assign $0\io_sr$next[129:0]$6109 $2\io_sr$next[129:0]$6111 + attribute \src "libresoc.v:140942.5-140942.29" switch \initial - attribute \src "libresoc.v:140040.9-140040.17" + attribute \src "libresoc.v:140942.9-140942.17" case 1'1 case end @@ -224136,35 +224600,35 @@ module \jtag attribute \src "libresoc.v:0.0-0.0" case 3'--1 assign { } { } - assign $1\io_sr$next[151:0]$6126 { \sdr_dq_15__core__oe \sdr_dq_15__core__o \sdr_dq_15__pad__i \sdr_dq_14__core__oe \sdr_dq_14__core__o \sdr_dq_14__pad__i \sdr_dq_13__core__oe \sdr_dq_13__core__o \sdr_dq_13__pad__i \sdr_dq_12__core__oe \sdr_dq_12__core__o \sdr_dq_12__pad__i \sdr_dq_11__core__oe \sdr_dq_11__core__o \sdr_dq_11__pad__i \sdr_dq_10__core__oe \sdr_dq_10__core__o \sdr_dq_10__pad__i \sdr_dq_9__core__oe \sdr_dq_9__core__o \sdr_dq_9__pad__i \sdr_dq_8__core__oe \sdr_dq_8__core__o \sdr_dq_8__pad__i \sdr_dm_1__core__o \sdr_a_12__core__o \sdr_a_11__core__o \sdr_a_10__core__o \sdr_cs_n__core__o \sdr_we_n__core__o \sdr_cas_n__core__o \sdr_ras_n__core__o \sdr_cke__core__o \sdr_clock__core__o \sdr_ba_1__core__o \sdr_ba_0__core__o \sdr_a_9__core__o \sdr_a_8__core__o \sdr_a_7__core__o \sdr_a_6__core__o \sdr_a_5__core__o \sdr_a_4__core__o \sdr_a_3__core__o \sdr_a_2__core__o \sdr_a_1__core__o \sdr_a_0__core__o \sdr_dq_7__core__oe \sdr_dq_7__core__o \sdr_dq_7__pad__i \sdr_dq_6__core__oe \sdr_dq_6__core__o \sdr_dq_6__pad__i \sdr_dq_5__core__oe \sdr_dq_5__core__o \sdr_dq_5__pad__i \sdr_dq_4__core__oe \sdr_dq_4__core__o \sdr_dq_4__pad__i \sdr_dq_3__core__oe \sdr_dq_3__core__o \sdr_dq_3__pad__i \sdr_dq_2__core__oe \sdr_dq_2__core__o \sdr_dq_2__pad__i \sdr_dq_1__core__oe \sdr_dq_1__core__o \sdr_dq_1__pad__i \sdr_dq_0__core__oe \sdr_dq_0__core__o \sdr_dq_0__pad__i \sdr_dm_0__core__o \sd0_data3__core__oe \sd0_data3__core__o \sd0_data3__pad__i \sd0_data2__core__oe \sd0_data2__core__o \sd0_data2__pad__i \sd0_data1__core__oe \sd0_data1__core__o \sd0_data1__pad__i \sd0_data0__core__oe \sd0_data0__core__o \sd0_data0__pad__i \sd0_clk__core__o \sd0_cmd__core__oe \sd0_cmd__core__o \sd0_cmd__pad__i \pwm_1__core__o \pwm_0__core__o \mtwi_scl__core__o \mtwi_sda__core__oe \mtwi_sda__core__o \mtwi_sda__pad__i \mspi1_miso__pad__i \mspi1_mosi__core__o \mspi1_cs_n__core__o \mspi1_clk__core__o \mspi0_miso__pad__i \mspi0_mosi__core__o \mspi0_cs_n__core__o \mspi0_clk__core__o \gpio_s7__core__oe \gpio_s7__core__o \gpio_s7__pad__i \gpio_s6__core__oe \gpio_s6__core__o \gpio_s6__pad__i \gpio_s5__core__oe \gpio_s5__core__o \gpio_s5__pad__i \gpio_s4__core__oe \gpio_s4__core__o \gpio_s4__pad__i \gpio_s3__core__oe \gpio_s3__core__o \gpio_s3__pad__i \gpio_s2__core__oe \gpio_s2__core__o \gpio_s2__pad__i \gpio_s1__core__oe \gpio_s1__core__o \gpio_s1__pad__i \gpio_s0__core__oe \gpio_s0__core__o \gpio_s0__pad__i \gpio_e15__core__oe \gpio_e15__core__o \gpio_e15__pad__i \gpio_e14__core__oe \gpio_e14__core__o \gpio_e14__pad__i \gpio_e13__core__oe \gpio_e13__core__o \gpio_e13__pad__i \gpio_e12__core__oe \gpio_e12__core__o \gpio_e12__pad__i \gpio_e11__core__oe \gpio_e11__core__o \gpio_e11__pad__i \gpio_e10__core__oe \gpio_e10__core__o \gpio_e10__pad__i \gpio_e9__core__oe \gpio_e9__core__o \gpio_e9__pad__i \gpio_e8__core__oe \gpio_e8__core__o \gpio_e8__pad__i \eint_2__pad__i \eint_1__pad__i \eint_0__pad__i } + assign $1\io_sr$next[129:0]$6110 { \sdr_dq_15__core__oe \sdr_dq_15__core__o \sdr_dq_15__pad__i \sdr_dq_14__core__oe \sdr_dq_14__core__o \sdr_dq_14__pad__i \sdr_dq_13__core__oe \sdr_dq_13__core__o \sdr_dq_13__pad__i \sdr_dq_12__core__oe \sdr_dq_12__core__o \sdr_dq_12__pad__i \sdr_dq_11__core__oe \sdr_dq_11__core__o \sdr_dq_11__pad__i \sdr_dq_10__core__oe \sdr_dq_10__core__o \sdr_dq_10__pad__i \sdr_dq_9__core__oe \sdr_dq_9__core__o \sdr_dq_9__pad__i \sdr_dq_8__core__oe \sdr_dq_8__core__o \sdr_dq_8__pad__i \sdr_dm_1__core__o \sdr_a_12__core__o \sdr_a_11__core__o \sdr_a_10__core__o \sdr_cs_n__core__o \sdr_we_n__core__o \sdr_cas_n__core__o \sdr_ras_n__core__o \sdr_cke__core__o \sdr_clock__core__o \sdr_ba_1__core__o \sdr_ba_0__core__o \sdr_a_9__core__o \sdr_a_8__core__o \sdr_a_7__core__o \sdr_a_6__core__o \sdr_a_5__core__o \sdr_a_4__core__o \sdr_a_3__core__o \sdr_a_2__core__o \sdr_a_1__core__o \sdr_a_0__core__o \sdr_dq_7__core__oe \sdr_dq_7__core__o \sdr_dq_7__pad__i \sdr_dq_6__core__oe \sdr_dq_6__core__o \sdr_dq_6__pad__i \sdr_dq_5__core__oe \sdr_dq_5__core__o \sdr_dq_5__pad__i \sdr_dq_4__core__oe \sdr_dq_4__core__o \sdr_dq_4__pad__i \sdr_dq_3__core__oe \sdr_dq_3__core__o \sdr_dq_3__pad__i \sdr_dq_2__core__oe \sdr_dq_2__core__o \sdr_dq_2__pad__i \sdr_dq_1__core__oe \sdr_dq_1__core__o \sdr_dq_1__pad__i \sdr_dq_0__core__oe \sdr_dq_0__core__o \sdr_dq_0__pad__i \sdr_dm_0__core__o \mtwi_scl__core__o \mtwi_sda__core__oe \mtwi_sda__core__o \mtwi_sda__pad__i \mspi0_miso__pad__i \mspi0_mosi__core__o \mspi0_cs_n__core__o \mspi0_clk__core__o \gpio_s7__core__oe \gpio_s7__core__o \gpio_s7__pad__i \gpio_s6__core__oe \gpio_s6__core__o \gpio_s6__pad__i \gpio_s5__core__oe \gpio_s5__core__o \gpio_s5__pad__i \gpio_s4__core__oe \gpio_s4__core__o \gpio_s4__pad__i \gpio_s3__core__oe \gpio_s3__core__o \gpio_s3__pad__i \gpio_s2__core__oe \gpio_s2__core__o \gpio_s2__pad__i \gpio_s1__core__oe \gpio_s1__core__o \gpio_s1__pad__i \gpio_s0__core__oe \gpio_s0__core__o \gpio_s0__pad__i \gpio_e15__core__oe \gpio_e15__core__o \gpio_e15__pad__i \gpio_e14__core__oe \gpio_e14__core__o \gpio_e14__pad__i \gpio_e13__core__oe \gpio_e13__core__o \gpio_e13__pad__i \gpio_e12__core__oe \gpio_e12__core__o \gpio_e12__pad__i \gpio_e11__core__oe \gpio_e11__core__o \gpio_e11__pad__i \gpio_e10__core__oe \gpio_e10__core__o \gpio_e10__pad__i \gpio_e9__core__oe \gpio_e9__core__o \gpio_e9__pad__i \gpio_e8__core__oe \gpio_e8__core__o \gpio_e8__pad__i \eint_2__pad__i \eint_1__pad__i \eint_0__pad__i } attribute \src "libresoc.v:0.0-0.0" case 3'-1- assign { } { } - assign $1\io_sr$next[151:0]$6126 { \io_sr [150:0] \TAP_bus__tdi } + assign $1\io_sr$next[129:0]$6110 { \io_sr [128:0] \TAP_bus__tdi } case - assign $1\io_sr$next[151:0]$6126 \io_sr + assign $1\io_sr$next[129:0]$6110 \io_sr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \posjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\io_sr$next[151:0]$6127 152'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $2\io_sr$next[129:0]$6111 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 case - assign $2\io_sr$next[151:0]$6127 $1\io_sr$next[151:0]$6126 + assign $2\io_sr$next[129:0]$6111 $1\io_sr$next[129:0]$6110 end sync always - update \io_sr$next $0\io_sr$next[151:0]$6125 + update \io_sr$next $0\io_sr$next[129:0]$6109 end - attribute \src "libresoc.v:140057.3-140077.6" - process $proc$libresoc.v:140057$6128 + attribute \src "libresoc.v:140959.3-140979.6" + process $proc$libresoc.v:140959$6112 assign { } { } assign { } { } assign { } { } - assign $0\io_bd$next[151:0]$6129 $2\io_bd$next[151:0]$6131 - attribute \src "libresoc.v:140058.5-140058.29" + assign $0\io_bd$next[129:0]$6113 $2\io_bd$next[129:0]$6115 + attribute \src "libresoc.v:140960.5-140960.29" switch \initial - attribute \src "libresoc.v:140058.9-140058.17" + attribute \src "libresoc.v:140960.9-140960.17" case 1'1 case end @@ -224172,424 +224636,380 @@ module \jtag switch { \io_update \io_shift \io_capture } attribute \src "libresoc.v:0.0-0.0" case 3'--1 - assign $1\io_bd$next[151:0]$6130 \io_bd + assign $1\io_bd$next[129:0]$6114 \io_bd attribute \src "libresoc.v:0.0-0.0" case 3'-1- - assign $1\io_bd$next[151:0]$6130 \io_bd + assign $1\io_bd$next[129:0]$6114 \io_bd attribute \src "libresoc.v:0.0-0.0" case 3'1-- assign { } { } - assign $1\io_bd$next[151:0]$6130 \io_sr + assign $1\io_bd$next[129:0]$6114 \io_sr case - assign $1\io_bd$next[151:0]$6130 \io_bd + assign $1\io_bd$next[129:0]$6114 \io_bd end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \negjtag_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\io_bd$next[151:0]$6131 152'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - case - assign $2\io_bd$next[151:0]$6131 $1\io_bd$next[151:0]$6130 - end - sync always - update \io_bd$next $0\io_bd$next[151:0]$6129 - end - connect \$9 $eq$libresoc.v:138998$5682_Y - connect \$99 $ternary$libresoc.v:138999$5683_Y - connect \$101 $ternary$libresoc.v:139000$5684_Y - connect \$103 $ternary$libresoc.v:139001$5685_Y - connect \$105 $ternary$libresoc.v:139002$5686_Y - connect \$107 $ternary$libresoc.v:139003$5687_Y - connect \$109 $ternary$libresoc.v:139004$5688_Y - connect \$111 $ternary$libresoc.v:139005$5689_Y - connect \$113 $ternary$libresoc.v:139006$5690_Y - connect \$115 $ternary$libresoc.v:139007$5691_Y - connect \$117 $ternary$libresoc.v:139008$5692_Y - connect \$11 $eq$libresoc.v:139009$5693_Y - connect \$119 $ternary$libresoc.v:139010$5694_Y - connect \$121 $ternary$libresoc.v:139011$5695_Y - connect \$123 $ternary$libresoc.v:139012$5696_Y - connect \$125 $ternary$libresoc.v:139013$5697_Y - connect \$127 $ternary$libresoc.v:139014$5698_Y - connect \$129 $ternary$libresoc.v:139015$5699_Y - connect \$131 $ternary$libresoc.v:139016$5700_Y - connect \$133 $ternary$libresoc.v:139017$5701_Y - connect \$135 $ternary$libresoc.v:139018$5702_Y - connect \$137 $ternary$libresoc.v:139019$5703_Y - connect \$13 $eq$libresoc.v:139020$5704_Y - connect \$139 $ternary$libresoc.v:139021$5705_Y - connect \$141 $ternary$libresoc.v:139022$5706_Y - connect \$143 $ternary$libresoc.v:139023$5707_Y - connect \$145 $ternary$libresoc.v:139024$5708_Y - connect \$147 $ternary$libresoc.v:139025$5709_Y - connect \$149 $ternary$libresoc.v:139026$5710_Y - connect \$151 $ternary$libresoc.v:139027$5711_Y - connect \$153 $ternary$libresoc.v:139028$5712_Y - connect \$155 $ternary$libresoc.v:139029$5713_Y - connect \$157 $ternary$libresoc.v:139030$5714_Y - connect \$15 $or$libresoc.v:139031$5715_Y - connect \$159 $ternary$libresoc.v:139032$5716_Y - connect \$161 $ternary$libresoc.v:139033$5717_Y - connect \$163 $ternary$libresoc.v:139034$5718_Y - connect \$165 $ternary$libresoc.v:139035$5719_Y - connect \$167 $ternary$libresoc.v:139036$5720_Y - connect \$169 $ternary$libresoc.v:139037$5721_Y - connect \$171 $ternary$libresoc.v:139038$5722_Y - connect \$173 $ternary$libresoc.v:139039$5723_Y - connect \$175 $ternary$libresoc.v:139040$5724_Y - connect \$177 $ternary$libresoc.v:139041$5725_Y - connect \$17 $and$libresoc.v:139042$5726_Y - connect \$179 $ternary$libresoc.v:139043$5727_Y - connect \$181 $ternary$libresoc.v:139044$5728_Y - connect \$183 $ternary$libresoc.v:139045$5729_Y - connect \$185 $ternary$libresoc.v:139046$5730_Y - connect \$187 $ternary$libresoc.v:139047$5731_Y - connect \$189 $ternary$libresoc.v:139048$5732_Y - connect \$191 $ternary$libresoc.v:139049$5733_Y - connect \$193 $ternary$libresoc.v:139050$5734_Y - connect \$195 $ternary$libresoc.v:139051$5735_Y - connect \$197 $ternary$libresoc.v:139052$5736_Y - connect \$1 $eq$libresoc.v:139053$5737_Y - connect \$19 $eq$libresoc.v:139054$5738_Y - connect \$199 $ternary$libresoc.v:139055$5739_Y - connect \$201 $ternary$libresoc.v:139056$5740_Y - connect \$203 $ternary$libresoc.v:139057$5741_Y - connect \$205 $ternary$libresoc.v:139058$5742_Y - connect \$207 $ternary$libresoc.v:139059$5743_Y - connect \$209 $ternary$libresoc.v:139060$5744_Y - connect \$211 $ternary$libresoc.v:139061$5745_Y - connect \$213 $ternary$libresoc.v:139062$5746_Y - connect \$215 $ternary$libresoc.v:139063$5747_Y - connect \$217 $ternary$libresoc.v:139064$5748_Y - connect \$21 $eq$libresoc.v:139065$5749_Y - connect \$219 $ternary$libresoc.v:139066$5750_Y - connect \$221 $ternary$libresoc.v:139067$5751_Y - connect \$223 $ternary$libresoc.v:139068$5752_Y - connect \$225 $ternary$libresoc.v:139069$5753_Y - connect \$227 $ternary$libresoc.v:139070$5754_Y - connect \$229 $ternary$libresoc.v:139071$5755_Y - connect \$231 $ternary$libresoc.v:139072$5756_Y - connect \$233 $ternary$libresoc.v:139073$5757_Y - connect \$235 $ternary$libresoc.v:139074$5758_Y - connect \$237 $ternary$libresoc.v:139075$5759_Y - connect \$23 $or$libresoc.v:139076$5760_Y - connect \$239 $ternary$libresoc.v:139077$5761_Y - connect \$241 $ternary$libresoc.v:139078$5762_Y - connect \$243 $ternary$libresoc.v:139079$5763_Y - connect \$245 $ternary$libresoc.v:139080$5764_Y - connect \$247 $ternary$libresoc.v:139081$5765_Y - connect \$249 $ternary$libresoc.v:139082$5766_Y - connect \$251 $ternary$libresoc.v:139083$5767_Y - connect \$253 $ternary$libresoc.v:139084$5768_Y - connect \$255 $ternary$libresoc.v:139085$5769_Y - connect \$257 $ternary$libresoc.v:139086$5770_Y - connect \$25 $eq$libresoc.v:139087$5771_Y - connect \$259 $ternary$libresoc.v:139088$5772_Y - connect \$261 $ternary$libresoc.v:139089$5773_Y - connect \$263 $ternary$libresoc.v:139090$5774_Y - connect \$265 $ternary$libresoc.v:139091$5775_Y - connect \$267 $ternary$libresoc.v:139092$5776_Y - connect \$269 $ternary$libresoc.v:139093$5777_Y - connect \$271 $ternary$libresoc.v:139094$5778_Y - connect \$273 $ternary$libresoc.v:139095$5779_Y - connect \$275 $ternary$libresoc.v:139096$5780_Y - connect \$277 $ternary$libresoc.v:139097$5781_Y - connect \$27 $or$libresoc.v:139098$5782_Y - connect \$279 $ternary$libresoc.v:139099$5783_Y - connect \$281 $ternary$libresoc.v:139100$5784_Y - connect \$283 $ternary$libresoc.v:139101$5785_Y - connect \$285 $ternary$libresoc.v:139102$5786_Y - connect \$287 $ternary$libresoc.v:139103$5787_Y - connect \$289 $ternary$libresoc.v:139104$5788_Y - connect \$291 $ternary$libresoc.v:139105$5789_Y - connect \$293 $ternary$libresoc.v:139106$5790_Y - connect \$295 $ternary$libresoc.v:139107$5791_Y - connect \$297 $ternary$libresoc.v:139108$5792_Y - connect \$29 $and$libresoc.v:139109$5793_Y - connect \$299 $ternary$libresoc.v:139110$5794_Y - connect \$301 $ternary$libresoc.v:139111$5795_Y - connect \$303 $ternary$libresoc.v:139112$5796_Y - connect \$305 $ternary$libresoc.v:139113$5797_Y - connect \$307 $ternary$libresoc.v:139114$5798_Y - connect \$309 $ternary$libresoc.v:139115$5799_Y - connect \$311 $ternary$libresoc.v:139116$5800_Y - connect \$313 $ternary$libresoc.v:139117$5801_Y - connect \$315 $ternary$libresoc.v:139118$5802_Y - connect \$317 $ternary$libresoc.v:139119$5803_Y - connect \$31 $and$libresoc.v:139120$5804_Y - connect \$319 $ternary$libresoc.v:139121$5805_Y - connect \$321 $ternary$libresoc.v:139122$5806_Y - connect \$323 $ternary$libresoc.v:139123$5807_Y - connect \$325 $ternary$libresoc.v:139124$5808_Y - connect \$327 $ternary$libresoc.v:139125$5809_Y - connect \$329 $ternary$libresoc.v:139126$5810_Y - connect \$331 $ternary$libresoc.v:139127$5811_Y - connect \$333 $ternary$libresoc.v:139128$5812_Y - connect \$335 $ternary$libresoc.v:139129$5813_Y - connect \$337 $ternary$libresoc.v:139130$5814_Y - connect \$33 $eq$libresoc.v:139131$5815_Y - connect \$339 $ternary$libresoc.v:139132$5816_Y - connect \$341 $ternary$libresoc.v:139133$5817_Y - connect \$343 $ternary$libresoc.v:139134$5818_Y - connect \$345 $ternary$libresoc.v:139135$5819_Y - connect \$347 $ternary$libresoc.v:139136$5820_Y - connect \$349 $ternary$libresoc.v:139137$5821_Y - connect \$351 $ternary$libresoc.v:139138$5822_Y - connect \$353 $ternary$libresoc.v:139139$5823_Y - connect \$355 $eq$libresoc.v:139140$5824_Y - connect \$357 $eq$libresoc.v:139141$5825_Y - connect \$35 $eq$libresoc.v:139142$5826_Y - connect \$359 $or$libresoc.v:139143$5827_Y - connect \$361 $eq$libresoc.v:139144$5828_Y - connect \$363 $or$libresoc.v:139145$5829_Y - connect \$365 $and$libresoc.v:139146$5830_Y - connect \$367 $eq$libresoc.v:139147$5831_Y - connect \$369 $ne$libresoc.v:139148$5832_Y - connect \$371 $and$libresoc.v:139149$5833_Y - connect \$373 $ne$libresoc.v:139150$5834_Y - connect \$375 $and$libresoc.v:139151$5835_Y - connect \$377 $ne$libresoc.v:139152$5836_Y - connect \$37 $or$libresoc.v:139153$5837_Y - connect \$379 $and$libresoc.v:139154$5838_Y - connect \$381 $not$libresoc.v:139155$5839_Y - connect \$383 $and$libresoc.v:139156$5840_Y - connect \$385 $eq$libresoc.v:139157$5841_Y - connect \$387 $ne$libresoc.v:139158$5842_Y - connect \$389 $and$libresoc.v:139159$5843_Y - connect \$391 $ne$libresoc.v:139160$5844_Y - connect \$393 $and$libresoc.v:139161$5845_Y - connect \$395 $ne$libresoc.v:139162$5846_Y - connect \$397 $and$libresoc.v:139163$5847_Y - connect \$3 $eq$libresoc.v:139164$5848_Y - connect \$39 $eq$libresoc.v:139165$5849_Y - connect \$399 $not$libresoc.v:139166$5850_Y - connect \$401 $and$libresoc.v:139167$5851_Y - connect \$403 $eq$libresoc.v:139168$5852_Y - connect \$405 $eq$libresoc.v:139169$5853_Y - connect \$407 $ne$libresoc.v:139170$5854_Y - connect \$409 $and$libresoc.v:139171$5855_Y - connect \$411 $ne$libresoc.v:139172$5856_Y - connect \$413 $and$libresoc.v:139173$5857_Y - connect \$415 $ne$libresoc.v:139174$5858_Y - connect \$417 $and$libresoc.v:139175$5859_Y - connect \$41 $or$libresoc.v:139176$5860_Y - connect \$419 $not$libresoc.v:139177$5861_Y - connect \$421 $and$libresoc.v:139178$5862_Y - connect \$423 $eq$libresoc.v:139179$5863_Y - connect \$425 $ne$libresoc.v:139180$5864_Y - connect \$427 $and$libresoc.v:139181$5865_Y - connect \$429 $ne$libresoc.v:139182$5866_Y - connect \$431 $and$libresoc.v:139183$5867_Y - connect \$433 $ne$libresoc.v:139184$5868_Y - connect \$435 $and$libresoc.v:139185$5869_Y - connect \$437 $not$libresoc.v:139186$5870_Y - connect \$43 $and$libresoc.v:139187$5871_Y - connect \$439 $and$libresoc.v:139188$5872_Y - connect \$441 $eq$libresoc.v:139189$5873_Y - connect \$443 $eq$libresoc.v:139190$5874_Y - connect \$445 $ne$libresoc.v:139191$5875_Y - connect \$447 $and$libresoc.v:139192$5876_Y - connect \$449 $ne$libresoc.v:139193$5877_Y - connect \$451 $and$libresoc.v:139194$5878_Y - connect \$453 $ne$libresoc.v:139195$5879_Y - connect \$455 $and$libresoc.v:139196$5880_Y - connect \$457 $not$libresoc.v:139197$5881_Y - connect \$45 $and$libresoc.v:139198$5882_Y - connect \$459 $and$libresoc.v:139199$5883_Y - connect \$461 $eq$libresoc.v:139200$5884_Y - connect \$463 $ne$libresoc.v:139201$5885_Y - connect \$465 $and$libresoc.v:139202$5886_Y - connect \$467 $ne$libresoc.v:139203$5887_Y - connect \$469 $and$libresoc.v:139204$5888_Y - connect \$471 $ne$libresoc.v:139205$5889_Y - connect \$473 $and$libresoc.v:139206$5890_Y - connect \$475 $not$libresoc.v:139207$5891_Y - connect \$477 $and$libresoc.v:139208$5892_Y - connect \$47 $eq$libresoc.v:139209$5893_Y - connect \$480 $eq$libresoc.v:139210$5894_Y - connect \$479 $not$libresoc.v:139211$5895_Y - connect \$483 $eq$libresoc.v:139212$5896_Y - connect \$485 $eq$libresoc.v:139213$5897_Y - connect \$487 $or$libresoc.v:139214$5898_Y - connect \$489 $eq$libresoc.v:139215$5899_Y - connect \$492 $add$libresoc.v:139216$5900_Y - connect \$495 $add$libresoc.v:139217$5901_Y - connect \$497 $pos$libresoc.v:139218$5903_Y - connect \$49 $eq$libresoc.v:139219$5904_Y - connect \$500 $eq$libresoc.v:139220$5905_Y - connect \$502 $eq$libresoc.v:139221$5906_Y - connect \$504 $or$libresoc.v:139222$5907_Y - connect \$506 $eq$libresoc.v:139223$5908_Y - connect \$509 $add$libresoc.v:139224$5909_Y - connect \$512 $add$libresoc.v:139225$5910_Y - connect \$51 $ternary$libresoc.v:139226$5911_Y - connect \$53 $ternary$libresoc.v:139227$5912_Y - connect \$55 $ternary$libresoc.v:139228$5913_Y - connect \$57 $ternary$libresoc.v:139229$5914_Y - connect \$5 $or$libresoc.v:139230$5915_Y - connect \$59 $ternary$libresoc.v:139231$5916_Y - connect \$61 $ternary$libresoc.v:139232$5917_Y - connect \$63 $ternary$libresoc.v:139233$5918_Y - connect \$65 $ternary$libresoc.v:139234$5919_Y - connect \$67 $ternary$libresoc.v:139235$5920_Y - connect \$69 $ternary$libresoc.v:139236$5921_Y - connect \$71 $ternary$libresoc.v:139237$5922_Y - connect \$73 $ternary$libresoc.v:139238$5923_Y - connect \$75 $ternary$libresoc.v:139239$5924_Y - connect \$77 $ternary$libresoc.v:139240$5925_Y - connect \$7 $and$libresoc.v:139241$5926_Y - connect \$79 $ternary$libresoc.v:139242$5927_Y - connect \$81 $ternary$libresoc.v:139243$5928_Y - connect \$83 $ternary$libresoc.v:139244$5929_Y - connect \$85 $ternary$libresoc.v:139245$5930_Y - connect \$87 $ternary$libresoc.v:139246$5931_Y - connect \$89 $ternary$libresoc.v:139247$5932_Y - connect \$91 $ternary$libresoc.v:139248$5933_Y - connect \$93 $ternary$libresoc.v:139249$5934_Y - connect \$95 $ternary$libresoc.v:139250$5935_Y - connect \$97 $ternary$libresoc.v:139251$5936_Y - connect \$491 \$492 - connect \$494 \$495 - connect \$508 \$509 - connect \$511 \$512 + assign $2\io_bd$next[129:0]$6115 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\io_bd$next[129:0]$6115 $1\io_bd$next[129:0]$6114 + end + sync always + update \io_bd$next $0\io_bd$next[129:0]$6113 + end + connect \$9 $eq$libresoc.v:139882$5688_Y + connect \$99 $ternary$libresoc.v:139883$5689_Y + connect \$101 $ternary$libresoc.v:139884$5690_Y + connect \$103 $ternary$libresoc.v:139885$5691_Y + connect \$105 $ternary$libresoc.v:139886$5692_Y + connect \$107 $ternary$libresoc.v:139887$5693_Y + connect \$109 $ternary$libresoc.v:139888$5694_Y + connect \$111 $ternary$libresoc.v:139889$5695_Y + connect \$113 $ternary$libresoc.v:139890$5696_Y + connect \$115 $ternary$libresoc.v:139891$5697_Y + connect \$117 $ternary$libresoc.v:139892$5698_Y + connect \$11 $eq$libresoc.v:139893$5699_Y + connect \$119 $ternary$libresoc.v:139894$5700_Y + connect \$121 $ternary$libresoc.v:139895$5701_Y + connect \$123 $ternary$libresoc.v:139896$5702_Y + connect \$125 $ternary$libresoc.v:139897$5703_Y + connect \$127 $ternary$libresoc.v:139898$5704_Y + connect \$129 $ternary$libresoc.v:139899$5705_Y + connect \$131 $ternary$libresoc.v:139900$5706_Y + connect \$133 $ternary$libresoc.v:139901$5707_Y + connect \$135 $ternary$libresoc.v:139902$5708_Y + connect \$137 $ternary$libresoc.v:139903$5709_Y + connect \$13 $eq$libresoc.v:139904$5710_Y + connect \$139 $ternary$libresoc.v:139905$5711_Y + connect \$141 $ternary$libresoc.v:139906$5712_Y + connect \$143 $ternary$libresoc.v:139907$5713_Y + connect \$145 $ternary$libresoc.v:139908$5714_Y + connect \$147 $ternary$libresoc.v:139909$5715_Y + connect \$149 $ternary$libresoc.v:139910$5716_Y + connect \$151 $ternary$libresoc.v:139911$5717_Y + connect \$153 $ternary$libresoc.v:139912$5718_Y + connect \$155 $ternary$libresoc.v:139913$5719_Y + connect \$157 $ternary$libresoc.v:139914$5720_Y + connect \$15 $or$libresoc.v:139915$5721_Y + connect \$159 $ternary$libresoc.v:139916$5722_Y + connect \$161 $ternary$libresoc.v:139917$5723_Y + connect \$163 $ternary$libresoc.v:139918$5724_Y + connect \$165 $ternary$libresoc.v:139919$5725_Y + connect \$167 $ternary$libresoc.v:139920$5726_Y + connect \$169 $ternary$libresoc.v:139921$5727_Y + connect \$171 $ternary$libresoc.v:139922$5728_Y + connect \$173 $ternary$libresoc.v:139923$5729_Y + connect \$175 $ternary$libresoc.v:139924$5730_Y + connect \$177 $ternary$libresoc.v:139925$5731_Y + connect \$17 $and$libresoc.v:139926$5732_Y + connect \$179 $ternary$libresoc.v:139927$5733_Y + connect \$181 $ternary$libresoc.v:139928$5734_Y + connect \$183 $ternary$libresoc.v:139929$5735_Y + connect \$185 $ternary$libresoc.v:139930$5736_Y + connect \$187 $ternary$libresoc.v:139931$5737_Y + connect \$189 $ternary$libresoc.v:139932$5738_Y + connect \$191 $ternary$libresoc.v:139933$5739_Y + connect \$193 $ternary$libresoc.v:139934$5740_Y + connect \$195 $ternary$libresoc.v:139935$5741_Y + connect \$197 $ternary$libresoc.v:139936$5742_Y + connect \$1 $eq$libresoc.v:139937$5743_Y + connect \$19 $eq$libresoc.v:139938$5744_Y + connect \$199 $ternary$libresoc.v:139939$5745_Y + connect \$201 $ternary$libresoc.v:139940$5746_Y + connect \$203 $ternary$libresoc.v:139941$5747_Y + connect \$205 $ternary$libresoc.v:139942$5748_Y + connect \$207 $ternary$libresoc.v:139943$5749_Y + connect \$209 $ternary$libresoc.v:139944$5750_Y + connect \$211 $ternary$libresoc.v:139945$5751_Y + connect \$213 $ternary$libresoc.v:139946$5752_Y + connect \$215 $ternary$libresoc.v:139947$5753_Y + connect \$217 $ternary$libresoc.v:139948$5754_Y + connect \$21 $eq$libresoc.v:139949$5755_Y + connect \$219 $ternary$libresoc.v:139950$5756_Y + connect \$221 $ternary$libresoc.v:139951$5757_Y + connect \$223 $ternary$libresoc.v:139952$5758_Y + connect \$225 $ternary$libresoc.v:139953$5759_Y + connect \$227 $ternary$libresoc.v:139954$5760_Y + connect \$229 $ternary$libresoc.v:139955$5761_Y + connect \$231 $ternary$libresoc.v:139956$5762_Y + connect \$233 $ternary$libresoc.v:139957$5763_Y + connect \$235 $ternary$libresoc.v:139958$5764_Y + connect \$237 $ternary$libresoc.v:139959$5765_Y + connect \$23 $or$libresoc.v:139960$5766_Y + connect \$239 $ternary$libresoc.v:139961$5767_Y + connect \$241 $ternary$libresoc.v:139962$5768_Y + connect \$243 $ternary$libresoc.v:139963$5769_Y + connect \$245 $ternary$libresoc.v:139964$5770_Y + connect \$247 $ternary$libresoc.v:139965$5771_Y + connect \$249 $ternary$libresoc.v:139966$5772_Y + connect \$251 $ternary$libresoc.v:139967$5773_Y + connect \$253 $ternary$libresoc.v:139968$5774_Y + connect \$255 $ternary$libresoc.v:139969$5775_Y + connect \$257 $ternary$libresoc.v:139970$5776_Y + connect \$25 $eq$libresoc.v:139971$5777_Y + connect \$259 $ternary$libresoc.v:139972$5778_Y + connect \$261 $ternary$libresoc.v:139973$5779_Y + connect \$263 $ternary$libresoc.v:139974$5780_Y + connect \$265 $ternary$libresoc.v:139975$5781_Y + connect \$267 $ternary$libresoc.v:139976$5782_Y + connect \$269 $ternary$libresoc.v:139977$5783_Y + connect \$271 $ternary$libresoc.v:139978$5784_Y + connect \$273 $ternary$libresoc.v:139979$5785_Y + connect \$275 $ternary$libresoc.v:139980$5786_Y + connect \$277 $ternary$libresoc.v:139981$5787_Y + connect \$27 $or$libresoc.v:139982$5788_Y + connect \$279 $ternary$libresoc.v:139983$5789_Y + connect \$281 $ternary$libresoc.v:139984$5790_Y + connect \$283 $ternary$libresoc.v:139985$5791_Y + connect \$285 $ternary$libresoc.v:139986$5792_Y + connect \$287 $ternary$libresoc.v:139987$5793_Y + connect \$289 $ternary$libresoc.v:139988$5794_Y + connect \$291 $ternary$libresoc.v:139989$5795_Y + connect \$293 $ternary$libresoc.v:139990$5796_Y + connect \$295 $ternary$libresoc.v:139991$5797_Y + connect \$297 $ternary$libresoc.v:139992$5798_Y + connect \$29 $and$libresoc.v:139993$5799_Y + connect \$299 $ternary$libresoc.v:139994$5800_Y + connect \$301 $ternary$libresoc.v:139995$5801_Y + connect \$303 $ternary$libresoc.v:139996$5802_Y + connect \$305 $ternary$libresoc.v:139997$5803_Y + connect \$307 $ternary$libresoc.v:139998$5804_Y + connect \$309 $ternary$libresoc.v:139999$5805_Y + connect \$311 $eq$libresoc.v:140000$5806_Y + connect \$313 $eq$libresoc.v:140001$5807_Y + connect \$315 $or$libresoc.v:140002$5808_Y + connect \$317 $eq$libresoc.v:140003$5809_Y + connect \$31 $and$libresoc.v:140004$5810_Y + connect \$319 $or$libresoc.v:140005$5811_Y + connect \$321 $and$libresoc.v:140006$5812_Y + connect \$323 $eq$libresoc.v:140007$5813_Y + connect \$325 $ne$libresoc.v:140008$5814_Y + connect \$327 $and$libresoc.v:140009$5815_Y + connect \$329 $ne$libresoc.v:140010$5816_Y + connect \$331 $and$libresoc.v:140011$5817_Y + connect \$333 $ne$libresoc.v:140012$5818_Y + connect \$335 $and$libresoc.v:140013$5819_Y + connect \$337 $not$libresoc.v:140014$5820_Y + connect \$33 $eq$libresoc.v:140015$5821_Y + connect \$339 $and$libresoc.v:140016$5822_Y + connect \$341 $eq$libresoc.v:140017$5823_Y + connect \$343 $ne$libresoc.v:140018$5824_Y + connect \$345 $and$libresoc.v:140019$5825_Y + connect \$347 $ne$libresoc.v:140020$5826_Y + connect \$349 $and$libresoc.v:140021$5827_Y + connect \$351 $ne$libresoc.v:140022$5828_Y + connect \$353 $and$libresoc.v:140023$5829_Y + connect \$355 $not$libresoc.v:140024$5830_Y + connect \$357 $and$libresoc.v:140025$5831_Y + connect \$35 $eq$libresoc.v:140026$5832_Y + connect \$359 $eq$libresoc.v:140027$5833_Y + connect \$361 $eq$libresoc.v:140028$5834_Y + connect \$363 $ne$libresoc.v:140029$5835_Y + connect \$365 $and$libresoc.v:140030$5836_Y + connect \$367 $ne$libresoc.v:140031$5837_Y + connect \$369 $and$libresoc.v:140032$5838_Y + connect \$371 $ne$libresoc.v:140033$5839_Y + connect \$373 $and$libresoc.v:140034$5840_Y + connect \$375 $not$libresoc.v:140035$5841_Y + connect \$377 $and$libresoc.v:140036$5842_Y + connect \$37 $or$libresoc.v:140037$5843_Y + connect \$379 $eq$libresoc.v:140038$5844_Y + connect \$381 $ne$libresoc.v:140039$5845_Y + connect \$383 $and$libresoc.v:140040$5846_Y + connect \$385 $ne$libresoc.v:140041$5847_Y + connect \$387 $and$libresoc.v:140042$5848_Y + connect \$389 $ne$libresoc.v:140043$5849_Y + connect \$391 $and$libresoc.v:140044$5850_Y + connect \$393 $not$libresoc.v:140045$5851_Y + connect \$395 $and$libresoc.v:140046$5852_Y + connect \$397 $eq$libresoc.v:140047$5853_Y + connect \$3 $eq$libresoc.v:140048$5854_Y + connect \$39 $eq$libresoc.v:140049$5855_Y + connect \$399 $eq$libresoc.v:140050$5856_Y + connect \$401 $ne$libresoc.v:140051$5857_Y + connect \$403 $and$libresoc.v:140052$5858_Y + connect \$405 $ne$libresoc.v:140053$5859_Y + connect \$407 $and$libresoc.v:140054$5860_Y + connect \$409 $ne$libresoc.v:140055$5861_Y + connect \$411 $and$libresoc.v:140056$5862_Y + connect \$413 $not$libresoc.v:140057$5863_Y + connect \$415 $and$libresoc.v:140058$5864_Y + connect \$417 $eq$libresoc.v:140059$5865_Y + connect \$41 $or$libresoc.v:140060$5866_Y + connect \$419 $ne$libresoc.v:140061$5867_Y + connect \$421 $and$libresoc.v:140062$5868_Y + connect \$423 $ne$libresoc.v:140063$5869_Y + connect \$425 $and$libresoc.v:140064$5870_Y + connect \$427 $ne$libresoc.v:140065$5871_Y + connect \$429 $and$libresoc.v:140066$5872_Y + connect \$431 $not$libresoc.v:140067$5873_Y + connect \$433 $and$libresoc.v:140068$5874_Y + connect \$436 $eq$libresoc.v:140069$5875_Y + connect \$435 $not$libresoc.v:140070$5876_Y + connect \$43 $and$libresoc.v:140071$5877_Y + connect \$439 $eq$libresoc.v:140072$5878_Y + connect \$441 $eq$libresoc.v:140073$5879_Y + connect \$443 $or$libresoc.v:140074$5880_Y + connect \$445 $eq$libresoc.v:140075$5881_Y + connect \$448 $add$libresoc.v:140076$5882_Y + connect \$451 $add$libresoc.v:140077$5883_Y + connect \$453 $pos$libresoc.v:140078$5885_Y + connect \$456 $eq$libresoc.v:140079$5886_Y + connect \$458 $eq$libresoc.v:140080$5887_Y + connect \$45 $and$libresoc.v:140081$5888_Y + connect \$460 $or$libresoc.v:140082$5889_Y + connect \$462 $eq$libresoc.v:140083$5890_Y + connect \$465 $add$libresoc.v:140084$5891_Y + connect \$468 $add$libresoc.v:140085$5892_Y + connect \$47 $eq$libresoc.v:140086$5893_Y + connect \$49 $eq$libresoc.v:140087$5894_Y + connect \$51 $ternary$libresoc.v:140088$5895_Y + connect \$53 $ternary$libresoc.v:140089$5896_Y + connect \$55 $ternary$libresoc.v:140090$5897_Y + connect \$57 $ternary$libresoc.v:140091$5898_Y + connect \$5 $or$libresoc.v:140092$5899_Y + connect \$59 $ternary$libresoc.v:140093$5900_Y + connect \$61 $ternary$libresoc.v:140094$5901_Y + connect \$63 $ternary$libresoc.v:140095$5902_Y + connect \$65 $ternary$libresoc.v:140096$5903_Y + connect \$67 $ternary$libresoc.v:140097$5904_Y + connect \$69 $ternary$libresoc.v:140098$5905_Y + connect \$71 $ternary$libresoc.v:140099$5906_Y + connect \$73 $ternary$libresoc.v:140100$5907_Y + connect \$75 $ternary$libresoc.v:140101$5908_Y + connect \$77 $ternary$libresoc.v:140102$5909_Y + connect \$7 $and$libresoc.v:140103$5910_Y + connect \$79 $ternary$libresoc.v:140104$5911_Y + connect \$81 $ternary$libresoc.v:140105$5912_Y + connect \$83 $ternary$libresoc.v:140106$5913_Y + connect \$85 $ternary$libresoc.v:140107$5914_Y + connect \$87 $ternary$libresoc.v:140108$5915_Y + connect \$89 $ternary$libresoc.v:140109$5916_Y + connect \$91 $ternary$libresoc.v:140110$5917_Y + connect \$93 $ternary$libresoc.v:140111$5918_Y + connect \$95 $ternary$libresoc.v:140112$5919_Y + connect \$97 $ternary$libresoc.v:140113$5920_Y + connect \$447 \$448 + connect \$450 \$451 + connect \$464 \$465 + connect \$467 \$468 connect \sr5__ie 1'0 connect \sr0__i \sr0__o - connect \dmi0__we_i \$506 - connect \dmi0__req_i \$504 - connect \dmi0_addrsr__i \$497 - connect \jtag_wb__we \$489 - connect \jtag_wb__stb \$487 - connect \jtag_wb__cyc \$479 + connect \dmi0__we_i \$462 + connect \dmi0__req_i \$460 + connect \dmi0_addrsr__i \$453 + connect \jtag_wb__we \$445 + connect \jtag_wb__stb \$443 + connect \jtag_wb__cyc \$435 connect \jtag_wb__sel 1'1 connect \jtag_wb_addrsr__i \jtag_wb__adr - connect \sr5_update \$473 - connect \sr5_shift \$469 - connect \sr5_capture \$465 - connect \sr5_isir \$461 + connect \sr5_update \$429 + connect \sr5_shift \$425 + connect \sr5_capture \$421 + connect \sr5_isir \$417 connect \sr5__o \sr5_reg - connect \dmi0_datasr_update \$455 - connect \dmi0_datasr_shift \$451 - connect \dmi0_datasr_capture \$447 - connect \dmi0_datasr_isir { \$443 \$441 } + connect \dmi0_datasr_update \$411 + connect \dmi0_datasr_shift \$407 + connect \dmi0_datasr_capture \$403 + connect \dmi0_datasr_isir { \$399 \$397 } connect \dmi0_datasr__o \dmi0_datasr_reg - connect \dmi0_addrsr_update \$435 - connect \dmi0_addrsr_shift \$431 - connect \dmi0_addrsr_capture \$427 - connect \dmi0_addrsr_isir \$423 + connect \dmi0_addrsr_update \$391 + connect \dmi0_addrsr_shift \$387 + connect \dmi0_addrsr_capture \$383 + connect \dmi0_addrsr_isir \$379 connect \dmi0_addrsr__o \dmi0_addrsr_reg - connect \jtag_wb_datasr_update \$417 - connect \jtag_wb_datasr_shift \$413 - connect \jtag_wb_datasr_capture \$409 - connect \jtag_wb_datasr_isir { \$405 \$403 } + connect \jtag_wb_datasr_update \$373 + connect \jtag_wb_datasr_shift \$369 + connect \jtag_wb_datasr_capture \$365 + connect \jtag_wb_datasr_isir { \$361 \$359 } connect \jtag_wb_datasr__o \jtag_wb_datasr_reg - connect \jtag_wb_addrsr_update \$397 - connect \jtag_wb_addrsr_shift \$393 - connect \jtag_wb_addrsr_capture \$389 - connect \jtag_wb_addrsr_isir \$385 + connect \jtag_wb_addrsr_update \$353 + connect \jtag_wb_addrsr_shift \$349 + connect \jtag_wb_addrsr_capture \$345 + connect \jtag_wb_addrsr_isir \$341 connect \jtag_wb_addrsr__o \jtag_wb_addrsr_reg - connect \sr0_update \$379 - connect \sr0_shift \$375 - connect \sr0_capture \$371 - connect \sr0_isir \$367 + connect \sr0_update \$335 + connect \sr0_shift \$331 + connect \sr0_capture \$327 + connect \sr0_isir \$323 connect \sr0__o \sr0_reg - connect \sdr_dq_15__pad__oe \$353 - connect \sdr_dq_15__pad__o \$351 - connect \sdr_dq_15__core__i \$349 - connect \sdr_dq_14__pad__oe \$347 - connect \sdr_dq_14__pad__o \$345 - connect \sdr_dq_14__core__i \$343 - connect \sdr_dq_13__pad__oe \$341 - connect \sdr_dq_13__pad__o \$339 - connect \sdr_dq_13__core__i \$337 - connect \sdr_dq_12__pad__oe \$335 - connect \sdr_dq_12__pad__o \$333 - connect \sdr_dq_12__core__i \$331 - connect \sdr_dq_11__pad__oe \$329 - connect \sdr_dq_11__pad__o \$327 - connect \sdr_dq_11__core__i \$325 - connect \sdr_dq_10__pad__oe \$323 - connect \sdr_dq_10__pad__o \$321 - connect \sdr_dq_10__core__i \$319 - connect \sdr_dq_9__pad__oe \$317 - connect \sdr_dq_9__pad__o \$315 - connect \sdr_dq_9__core__i \$313 - connect \sdr_dq_8__pad__oe \$311 - connect \sdr_dq_8__pad__o \$309 - connect \sdr_dq_8__core__i \$307 - connect \sdr_dm_1__pad__o \$305 - connect \sdr_a_12__pad__o \$303 - connect \sdr_a_11__pad__o \$301 - connect \sdr_a_10__pad__o \$299 - connect \sdr_cs_n__pad__o \$297 - connect \sdr_we_n__pad__o \$295 - connect \sdr_cas_n__pad__o \$293 - connect \sdr_ras_n__pad__o \$291 - connect \sdr_cke__pad__o \$289 - connect \sdr_clock__pad__o \$287 - connect \sdr_ba_1__pad__o \$285 - connect \sdr_ba_0__pad__o \$283 - connect \sdr_a_9__pad__o \$281 - connect \sdr_a_8__pad__o \$279 - connect \sdr_a_7__pad__o \$277 - connect \sdr_a_6__pad__o \$275 - connect \sdr_a_5__pad__o \$273 - connect \sdr_a_4__pad__o \$271 - connect \sdr_a_3__pad__o \$269 - connect \sdr_a_2__pad__o \$267 - connect \sdr_a_1__pad__o \$265 - connect \sdr_a_0__pad__o \$263 - connect \sdr_dq_7__pad__oe \$261 - connect \sdr_dq_7__pad__o \$259 - connect \sdr_dq_7__core__i \$257 - connect \sdr_dq_6__pad__oe \$255 - connect \sdr_dq_6__pad__o \$253 - connect \sdr_dq_6__core__i \$251 - connect \sdr_dq_5__pad__oe \$249 - connect \sdr_dq_5__pad__o \$247 - connect \sdr_dq_5__core__i \$245 - connect \sdr_dq_4__pad__oe \$243 - connect \sdr_dq_4__pad__o \$241 - connect \sdr_dq_4__core__i \$239 - connect \sdr_dq_3__pad__oe \$237 - connect \sdr_dq_3__pad__o \$235 - connect \sdr_dq_3__core__i \$233 - connect \sdr_dq_2__pad__oe \$231 - connect \sdr_dq_2__pad__o \$229 - connect \sdr_dq_2__core__i \$227 - connect \sdr_dq_1__pad__oe \$225 - connect \sdr_dq_1__pad__o \$223 - connect \sdr_dq_1__core__i \$221 - connect \sdr_dq_0__pad__oe \$219 - connect \sdr_dq_0__pad__o \$217 - connect \sdr_dq_0__core__i \$215 - connect \sdr_dm_0__pad__o \$213 - connect \sd0_data3__pad__oe \$211 - connect \sd0_data3__pad__o \$209 - connect \sd0_data3__core__i \$207 - connect \sd0_data2__pad__oe \$205 - connect \sd0_data2__pad__o \$203 - connect \sd0_data2__core__i \$201 - connect \sd0_data1__pad__oe \$199 - connect \sd0_data1__pad__o \$197 - connect \sd0_data1__core__i \$195 - connect \sd0_data0__pad__oe \$193 - connect \sd0_data0__pad__o \$191 - connect \sd0_data0__core__i \$189 - connect \sd0_clk__pad__o \$187 - connect \sd0_cmd__pad__oe \$185 - connect \sd0_cmd__pad__o \$183 - connect \sd0_cmd__core__i \$181 - connect \pwm_1__pad__o \$179 - connect \pwm_0__pad__o \$177 - connect \mtwi_scl__pad__o \$175 - connect \mtwi_sda__pad__oe \$173 - connect \mtwi_sda__pad__o \$171 - connect \mtwi_sda__core__i \$169 - connect \mspi1_miso__core__i \$167 - connect \mspi1_mosi__pad__o \$165 - connect \mspi1_cs_n__pad__o \$163 - connect \mspi1_clk__pad__o \$161 + connect \sdr_dq_15__pad__oe \$309 + connect \sdr_dq_15__pad__o \$307 + connect \sdr_dq_15__core__i \$305 + connect \sdr_dq_14__pad__oe \$303 + connect \sdr_dq_14__pad__o \$301 + connect \sdr_dq_14__core__i \$299 + connect \sdr_dq_13__pad__oe \$297 + connect \sdr_dq_13__pad__o \$295 + connect \sdr_dq_13__core__i \$293 + connect \sdr_dq_12__pad__oe \$291 + connect \sdr_dq_12__pad__o \$289 + connect \sdr_dq_12__core__i \$287 + connect \sdr_dq_11__pad__oe \$285 + connect \sdr_dq_11__pad__o \$283 + connect \sdr_dq_11__core__i \$281 + connect \sdr_dq_10__pad__oe \$279 + connect \sdr_dq_10__pad__o \$277 + connect \sdr_dq_10__core__i \$275 + connect \sdr_dq_9__pad__oe \$273 + connect \sdr_dq_9__pad__o \$271 + connect \sdr_dq_9__core__i \$269 + connect \sdr_dq_8__pad__oe \$267 + connect \sdr_dq_8__pad__o \$265 + connect \sdr_dq_8__core__i \$263 + connect \sdr_dm_1__pad__o \$261 + connect \sdr_a_12__pad__o \$259 + connect \sdr_a_11__pad__o \$257 + connect \sdr_a_10__pad__o \$255 + connect \sdr_cs_n__pad__o \$253 + connect \sdr_we_n__pad__o \$251 + connect \sdr_cas_n__pad__o \$249 + connect \sdr_ras_n__pad__o \$247 + connect \sdr_cke__pad__o \$245 + connect \sdr_clock__pad__o \$243 + connect \sdr_ba_1__pad__o \$241 + connect \sdr_ba_0__pad__o \$239 + connect \sdr_a_9__pad__o \$237 + connect \sdr_a_8__pad__o \$235 + connect \sdr_a_7__pad__o \$233 + connect \sdr_a_6__pad__o \$231 + connect \sdr_a_5__pad__o \$229 + connect \sdr_a_4__pad__o \$227 + connect \sdr_a_3__pad__o \$225 + connect \sdr_a_2__pad__o \$223 + connect \sdr_a_1__pad__o \$221 + connect \sdr_a_0__pad__o \$219 + connect \sdr_dq_7__pad__oe \$217 + connect \sdr_dq_7__pad__o \$215 + connect \sdr_dq_7__core__i \$213 + connect \sdr_dq_6__pad__oe \$211 + connect \sdr_dq_6__pad__o \$209 + connect \sdr_dq_6__core__i \$207 + connect \sdr_dq_5__pad__oe \$205 + connect \sdr_dq_5__pad__o \$203 + connect \sdr_dq_5__core__i \$201 + connect \sdr_dq_4__pad__oe \$199 + connect \sdr_dq_4__pad__o \$197 + connect \sdr_dq_4__core__i \$195 + connect \sdr_dq_3__pad__oe \$193 + connect \sdr_dq_3__pad__o \$191 + connect \sdr_dq_3__core__i \$189 + connect \sdr_dq_2__pad__oe \$187 + connect \sdr_dq_2__pad__o \$185 + connect \sdr_dq_2__core__i \$183 + connect \sdr_dq_1__pad__oe \$181 + connect \sdr_dq_1__pad__o \$179 + connect \sdr_dq_1__core__i \$177 + connect \sdr_dq_0__pad__oe \$175 + connect \sdr_dq_0__pad__o \$173 + connect \sdr_dq_0__core__i \$171 + connect \sdr_dm_0__pad__o \$169 + connect \mtwi_scl__pad__o \$167 + connect \mtwi_sda__pad__oe \$165 + connect \mtwi_sda__pad__o \$163 + connect \mtwi_sda__core__i \$161 connect \mspi0_miso__core__i \$159 connect \mspi0_mosi__pad__o \$157 connect \mspi0_cs_n__pad__o \$155 @@ -224653,14 +225073,14 @@ module \jtag connect \_idblock_id_bypass \$9 connect \_idblock_select_id \$7 end -attribute \src "libresoc.v:140285.1-140474.10" +attribute \src "libresoc.v:141165.1-141354.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0" attribute \generator "nMigen" module \l0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 31 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire input 23 \dbus__ack @@ -224763,7 +225183,7 @@ module \l0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:94" wire input 21 \wb_dcache_en attribute \module_not_derived 1 - attribute \src "libresoc.v:140390.12-140424.4" + attribute \src "libresoc.v:141270.12-141304.4" cell \l0$130 \l0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -224800,7 +225220,7 @@ module \l0 connect \ldst_port0_st_data_i_ok$17 \pimem_ldst_port0_st_data_i_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:140425.9-140447.4" + attribute \src "libresoc.v:141305.9-141327.4" cell \lsmem \lsmem connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -224825,7 +225245,7 @@ module \l0 connect \x_valid_i \pimem_x_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:140448.9-140472.4" + attribute \src "libresoc.v:141328.9-141352.4" cell \pimem \pimem connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -224853,145 +225273,145 @@ module \l0 end connect \pimem_ldst_port0_exc_$signal 1'0 end -attribute \src "libresoc.v:140478.1-140886.10" +attribute \src "libresoc.v:141358.1-141766.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0" attribute \generator "nMigen" module \l0$130 - attribute \src "libresoc.v:140741.3-140755.6" - wire $0\idx_l$23$next[0:0]$6210 - attribute \src "libresoc.v:140641.3-140642.35" - wire $0\idx_l$23[0:0]$6177 - attribute \src "libresoc.v:140499.7-140499.24" - wire $0\idx_l$23[0:0]$6232 - attribute \src "libresoc.v:140796.3-140805.6" + attribute \src "libresoc.v:141621.3-141635.6" + wire $0\idx_l$23$next[0:0]$6194 + attribute \src "libresoc.v:141521.3-141522.35" + wire $0\idx_l$23[0:0]$6161 + attribute \src "libresoc.v:141379.7-141379.24" + wire $0\idx_l$23[0:0]$6216 + attribute \src "libresoc.v:141676.3-141685.6" wire $0\idx_l_r_idx_l[0:0] - attribute \src "libresoc.v:140786.3-140795.6" + attribute \src "libresoc.v:141666.3-141675.6" wire $0\idx_l_s_idx_l[0:0] - attribute \src "libresoc.v:140479.7-140479.20" + attribute \src "libresoc.v:141359.7-141359.20" wire $0\initial[0:0] - attribute \src "libresoc.v:140662.3-140671.6" - wire width 48 $0\ldst_port0_addr_i$12[47:0]$6179 - attribute \src "libresoc.v:140672.3-140681.6" - wire $0\ldst_port0_addr_i_ok$13[0:0]$6182 - attribute \src "libresoc.v:140714.3-140723.6" + attribute \src "libresoc.v:141542.3-141551.6" + wire width 48 $0\ldst_port0_addr_i$12[47:0]$6163 + attribute \src "libresoc.v:141552.3-141561.6" + wire $0\ldst_port0_addr_i_ok$13[0:0]$6166 + attribute \src "libresoc.v:141594.3-141603.6" wire $0\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:140704.3-140713.6" + attribute \src "libresoc.v:141584.3-141593.6" wire $0\ldst_port0_busy_o[0:0] - attribute \src "libresoc.v:140776.3-140785.6" + attribute \src "libresoc.v:141656.3-141665.6" wire $0\ldst_port0_cache_paradox[0:0] - attribute \src "libresoc.v:140851.3-140860.6" - wire width 4 $0\ldst_port0_data_len$11[3:0]$6227 - attribute \src "libresoc.v:140724.3-140740.6" - wire $0\ldst_port0_exc_$signal$1[0:0]$6194 - attribute \src "libresoc.v:140724.3-140740.6" - wire $0\ldst_port0_exc_$signal$2[0:0]$6195 - attribute \src "libresoc.v:140724.3-140740.6" - wire $0\ldst_port0_exc_$signal$3[0:0]$6196 - attribute \src "libresoc.v:140724.3-140740.6" - wire $0\ldst_port0_exc_$signal$4[0:0]$6197 - attribute \src "libresoc.v:140724.3-140740.6" - wire $0\ldst_port0_exc_$signal$5[0:0]$6198 - attribute \src "libresoc.v:140724.3-140740.6" - wire $0\ldst_port0_exc_$signal$6[0:0]$6199 - attribute \src "libresoc.v:140724.3-140740.6" - wire $0\ldst_port0_exc_$signal$7[0:0]$6200 - attribute \src "libresoc.v:140724.3-140740.6" - wire $0\ldst_port0_exc_$signal[0:0]$6193 - attribute \src "libresoc.v:140861.3-140870.6" + attribute \src "libresoc.v:141731.3-141740.6" + wire width 4 $0\ldst_port0_data_len$11[3:0]$6211 + attribute \src "libresoc.v:141604.3-141620.6" + wire $0\ldst_port0_exc_$signal$1[0:0]$6178 + attribute \src "libresoc.v:141604.3-141620.6" + wire $0\ldst_port0_exc_$signal$2[0:0]$6179 + attribute \src "libresoc.v:141604.3-141620.6" + wire $0\ldst_port0_exc_$signal$3[0:0]$6180 + attribute \src "libresoc.v:141604.3-141620.6" + wire $0\ldst_port0_exc_$signal$4[0:0]$6181 + attribute \src "libresoc.v:141604.3-141620.6" + wire $0\ldst_port0_exc_$signal$5[0:0]$6182 + attribute \src "libresoc.v:141604.3-141620.6" + wire $0\ldst_port0_exc_$signal$6[0:0]$6183 + attribute \src "libresoc.v:141604.3-141620.6" + wire $0\ldst_port0_exc_$signal$7[0:0]$6184 + attribute \src "libresoc.v:141604.3-141620.6" + wire $0\ldst_port0_exc_$signal[0:0]$6177 + attribute \src "libresoc.v:141741.3-141750.6" wire $0\ldst_port0_go_die_i[0:0] - attribute \src "libresoc.v:140831.3-140840.6" - wire $0\ldst_port0_is_ld_i$8[0:0]$6221 - attribute \src "libresoc.v:140841.3-140850.6" - wire $0\ldst_port0_is_st_i$9[0:0]$6224 - attribute \src "libresoc.v:140693.3-140703.6" + attribute \src "libresoc.v:141711.3-141720.6" + wire $0\ldst_port0_is_ld_i$8[0:0]$6205 + attribute \src "libresoc.v:141721.3-141730.6" + wire $0\ldst_port0_is_st_i$9[0:0]$6208 + attribute \src "libresoc.v:141573.3-141583.6" wire width 64 $0\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:140693.3-140703.6" + attribute \src "libresoc.v:141573.3-141583.6" wire $0\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:140766.3-140775.6" + attribute \src "libresoc.v:141646.3-141655.6" wire $0\ldst_port0_ldst_error[0:0] - attribute \src "libresoc.v:140756.3-140765.6" + attribute \src "libresoc.v:141636.3-141645.6" wire $0\ldst_port0_mmu_done[0:0] - attribute \src "libresoc.v:140682.3-140692.6" - wire width 64 $0\ldst_port0_st_data_i$18[63:0]$6185 - attribute \src "libresoc.v:140682.3-140692.6" - wire $0\ldst_port0_st_data_i_ok$17[0:0]$6186 - attribute \src "libresoc.v:140639.3-140640.36" + attribute \src "libresoc.v:141562.3-141572.6" + wire width 64 $0\ldst_port0_st_data_i$18[63:0]$6169 + attribute \src "libresoc.v:141562.3-141572.6" + wire $0\ldst_port0_st_data_i_ok$17[0:0]$6170 + attribute \src "libresoc.v:141519.3-141520.36" wire $0\reset_delay[0:0] - attribute \src "libresoc.v:140821.3-140830.6" + attribute \src "libresoc.v:141701.3-141710.6" wire $0\reset_l_r_reset[0:0] - attribute \src "libresoc.v:140806.3-140820.6" + attribute \src "libresoc.v:141686.3-141700.6" wire $0\reset_l_s_reset[0:0] - attribute \src "libresoc.v:140741.3-140755.6" - wire $1\idx_l$23$next[0:0]$6211 - attribute \src "libresoc.v:140796.3-140805.6" + attribute \src "libresoc.v:141621.3-141635.6" + wire $1\idx_l$23$next[0:0]$6195 + attribute \src "libresoc.v:141676.3-141685.6" wire $1\idx_l_r_idx_l[0:0] - attribute \src "libresoc.v:140786.3-140795.6" + attribute \src "libresoc.v:141666.3-141675.6" wire $1\idx_l_s_idx_l[0:0] - attribute \src "libresoc.v:140662.3-140671.6" - wire width 48 $1\ldst_port0_addr_i$12[47:0]$6180 - attribute \src "libresoc.v:140672.3-140681.6" - wire $1\ldst_port0_addr_i_ok$13[0:0]$6183 - attribute \src "libresoc.v:140714.3-140723.6" + attribute \src "libresoc.v:141542.3-141551.6" + wire width 48 $1\ldst_port0_addr_i$12[47:0]$6164 + attribute \src "libresoc.v:141552.3-141561.6" + wire $1\ldst_port0_addr_i_ok$13[0:0]$6167 + attribute \src "libresoc.v:141594.3-141603.6" wire $1\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:140704.3-140713.6" + attribute \src "libresoc.v:141584.3-141593.6" wire $1\ldst_port0_busy_o[0:0] - attribute \src "libresoc.v:140776.3-140785.6" + attribute \src "libresoc.v:141656.3-141665.6" wire $1\ldst_port0_cache_paradox[0:0] - attribute \src "libresoc.v:140851.3-140860.6" - wire width 4 $1\ldst_port0_data_len$11[3:0]$6228 - attribute \src "libresoc.v:140724.3-140740.6" - wire $1\ldst_port0_exc_$signal$1[0:0]$6202 - attribute \src "libresoc.v:140724.3-140740.6" - wire $1\ldst_port0_exc_$signal$2[0:0]$6203 - attribute \src "libresoc.v:140724.3-140740.6" - wire $1\ldst_port0_exc_$signal$3[0:0]$6204 - attribute \src "libresoc.v:140724.3-140740.6" - wire $1\ldst_port0_exc_$signal$4[0:0]$6205 - attribute \src "libresoc.v:140724.3-140740.6" - wire $1\ldst_port0_exc_$signal$5[0:0]$6206 - attribute \src "libresoc.v:140724.3-140740.6" - wire $1\ldst_port0_exc_$signal$6[0:0]$6207 - attribute \src "libresoc.v:140724.3-140740.6" - wire $1\ldst_port0_exc_$signal$7[0:0]$6208 - attribute \src "libresoc.v:140724.3-140740.6" - wire $1\ldst_port0_exc_$signal[0:0]$6201 - attribute \src "libresoc.v:140861.3-140870.6" + attribute \src "libresoc.v:141731.3-141740.6" + wire width 4 $1\ldst_port0_data_len$11[3:0]$6212 + attribute \src "libresoc.v:141604.3-141620.6" + wire $1\ldst_port0_exc_$signal$1[0:0]$6186 + attribute \src "libresoc.v:141604.3-141620.6" + wire $1\ldst_port0_exc_$signal$2[0:0]$6187 + attribute \src "libresoc.v:141604.3-141620.6" + wire $1\ldst_port0_exc_$signal$3[0:0]$6188 + attribute \src "libresoc.v:141604.3-141620.6" + wire $1\ldst_port0_exc_$signal$4[0:0]$6189 + attribute \src "libresoc.v:141604.3-141620.6" + wire $1\ldst_port0_exc_$signal$5[0:0]$6190 + attribute \src "libresoc.v:141604.3-141620.6" + wire $1\ldst_port0_exc_$signal$6[0:0]$6191 + attribute \src "libresoc.v:141604.3-141620.6" + wire $1\ldst_port0_exc_$signal$7[0:0]$6192 + attribute \src "libresoc.v:141604.3-141620.6" + wire $1\ldst_port0_exc_$signal[0:0]$6185 + attribute \src "libresoc.v:141741.3-141750.6" wire $1\ldst_port0_go_die_i[0:0] - attribute \src "libresoc.v:140831.3-140840.6" - wire $1\ldst_port0_is_ld_i$8[0:0]$6222 - attribute \src "libresoc.v:140841.3-140850.6" - wire $1\ldst_port0_is_st_i$9[0:0]$6225 - attribute \src "libresoc.v:140693.3-140703.6" + attribute \src "libresoc.v:141711.3-141720.6" + wire $1\ldst_port0_is_ld_i$8[0:0]$6206 + attribute \src "libresoc.v:141721.3-141730.6" + wire $1\ldst_port0_is_st_i$9[0:0]$6209 + attribute \src "libresoc.v:141573.3-141583.6" wire width 64 $1\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:140693.3-140703.6" + attribute \src "libresoc.v:141573.3-141583.6" wire $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:140766.3-140775.6" + attribute \src "libresoc.v:141646.3-141655.6" wire $1\ldst_port0_ldst_error[0:0] - attribute \src "libresoc.v:140756.3-140765.6" + attribute \src "libresoc.v:141636.3-141645.6" wire $1\ldst_port0_mmu_done[0:0] - attribute \src "libresoc.v:140682.3-140692.6" - wire width 64 $1\ldst_port0_st_data_i$18[63:0]$6187 - attribute \src "libresoc.v:140682.3-140692.6" - wire $1\ldst_port0_st_data_i_ok$17[0:0]$6188 - attribute \src "libresoc.v:140626.7-140626.25" + attribute \src "libresoc.v:141562.3-141572.6" + wire width 64 $1\ldst_port0_st_data_i$18[63:0]$6171 + attribute \src "libresoc.v:141562.3-141572.6" + wire $1\ldst_port0_st_data_i_ok$17[0:0]$6172 + attribute \src "libresoc.v:141506.7-141506.25" wire $1\reset_delay[0:0] - attribute \src "libresoc.v:140821.3-140830.6" + attribute \src "libresoc.v:141701.3-141710.6" wire $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:140806.3-140820.6" + attribute \src "libresoc.v:141686.3-141700.6" wire $1\reset_l_s_reset[0:0] - attribute \src "libresoc.v:140741.3-140755.6" - wire $2\idx_l$23$next[0:0]$6212 - attribute \src "libresoc.v:140806.3-140820.6" + attribute \src "libresoc.v:141621.3-141635.6" + wire $2\idx_l$23$next[0:0]$6196 + attribute \src "libresoc.v:141686.3-141700.6" wire $2\reset_l_s_reset[0:0] - attribute \src "libresoc.v:140637.18-140637.103" - wire $not$libresoc.v:140637$6173_Y - attribute \src "libresoc.v:140638.18-140638.118" - wire $not$libresoc.v:140638$6174_Y - attribute \src "libresoc.v:140635.18-140635.134" - wire $or$libresoc.v:140635$6171_Y - attribute \src "libresoc.v:140636.18-140636.120" - wire $ternary$libresoc.v:140636$6172_Y + attribute \src "libresoc.v:141517.18-141517.103" + wire $not$libresoc.v:141517$6157_Y + attribute \src "libresoc.v:141518.18-141518.118" + wire $not$libresoc.v:141518$6158_Y + attribute \src "libresoc.v:141515.18-141515.134" + wire $or$libresoc.v:141515$6155_Y + attribute \src "libresoc.v:141516.18-141516.120" + wire $ternary$libresoc.v:141516$6156_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" wire \$20 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" @@ -225006,9 +225426,9 @@ module \l0$130 wire width 96 \$31 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:136" wire width 96 \$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 33 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:46" wire \idx_l$23 @@ -225020,7 +225440,7 @@ module \l0$130 wire \idx_l_r_idx_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \idx_l_s_idx_l - attribute \src "libresoc.v:140479.7-140479.15" + attribute \src "libresoc.v:141359.7-141359.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 96 input 6 \ldst_port0_addr_i @@ -225131,23 +225551,23 @@ module \l0$130 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \reset_l_s_reset attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" - cell $not $not$libresoc.v:140637$6173 + cell $not $not$libresoc.v:141517$6157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \pick_n - connect \Y $not$libresoc.v:140637$6173_Y + connect \Y $not$libresoc.v:141517$6157_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" - cell $not $not$libresoc.v:140638$6174 + cell $not $not$libresoc.v:141518$6158 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o$10 - connect \Y $not$libresoc.v:140638$6174_Y + connect \Y $not$libresoc.v:141518$6158_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" - cell $or $or$libresoc.v:140635$6171 + cell $or $or$libresoc.v:141515$6155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225155,18 +225575,18 @@ module \l0$130 parameter \Y_WIDTH 1 connect \A \ldst_port0_is_ld_i connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:140635$6171_Y + connect \Y $or$libresoc.v:141515$6155_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:140636$6172 + cell $mux $ternary$libresoc.v:141516$6156 parameter \WIDTH 1 connect \A \idx_l$23 connect \B \pick_o connect \S \idx_l_q_idx_l - connect \Y $ternary$libresoc.v:140636$6172_Y + connect \Y $ternary$libresoc.v:141516$6156_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:140643.9-140649.4" + attribute \src "libresoc.v:141523.9-141529.4" cell \idx_l \idx_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -225175,14 +225595,14 @@ module \l0$130 connect \s_idx_l \idx_l_s_idx_l end attribute \module_not_derived 1 - attribute \src "libresoc.v:140650.8-140654.4" + attribute \src "libresoc.v:141530.8-141534.4" cell \pick \pick connect \i \pick_i connect \n \pick_n connect \o \pick_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:140655.17-140661.4" + attribute \src "libresoc.v:141535.17-141541.4" cell \reset_l$131 \reset_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -225190,52 +225610,52 @@ module \l0$130 connect \r_reset \reset_l_r_reset connect \s_reset \reset_l_s_reset end - attribute \src "libresoc.v:140479.7-140479.20" - process $proc$libresoc.v:140479$6230 + attribute \src "libresoc.v:141359.7-141359.20" + process $proc$libresoc.v:141359$6214 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:140499.7-140499.24" - process $proc$libresoc.v:140499$6231 + attribute \src "libresoc.v:141379.7-141379.24" + process $proc$libresoc.v:141379$6215 assign { } { } - assign $0\idx_l$23[0:0]$6232 1'0 + assign $0\idx_l$23[0:0]$6216 1'0 sync always sync init - update \idx_l$23 $0\idx_l$23[0:0]$6232 + update \idx_l$23 $0\idx_l$23[0:0]$6216 end - attribute \src "libresoc.v:140626.7-140626.25" - process $proc$libresoc.v:140626$6233 + attribute \src "libresoc.v:141506.7-141506.25" + process $proc$libresoc.v:141506$6217 assign { } { } assign $1\reset_delay[0:0] 1'0 sync always sync init update \reset_delay $1\reset_delay[0:0] end - attribute \src "libresoc.v:140639.3-140640.36" - process $proc$libresoc.v:140639$6175 + attribute \src "libresoc.v:141519.3-141520.36" + process $proc$libresoc.v:141519$6159 assign { } { } assign $0\reset_delay[0:0] \reset_l_q_reset sync posedge \coresync_clk update \reset_delay $0\reset_delay[0:0] end - attribute \src "libresoc.v:140641.3-140642.35" - process $proc$libresoc.v:140641$6176 + attribute \src "libresoc.v:141521.3-141522.35" + process $proc$libresoc.v:141521$6160 assign { } { } - assign $0\idx_l$23[0:0]$6177 \idx_l$23$next + assign $0\idx_l$23[0:0]$6161 \idx_l$23$next sync posedge \coresync_clk - update \idx_l$23 $0\idx_l$23[0:0]$6177 + update \idx_l$23 $0\idx_l$23[0:0]$6161 end - attribute \src "libresoc.v:140662.3-140671.6" - process $proc$libresoc.v:140662$6178 + attribute \src "libresoc.v:141542.3-141551.6" + process $proc$libresoc.v:141542$6162 assign { } { } assign { } { } - assign $0\ldst_port0_addr_i$12[47:0]$6179 $1\ldst_port0_addr_i$12[47:0]$6180 - attribute \src "libresoc.v:140663.5-140663.29" + assign $0\ldst_port0_addr_i$12[47:0]$6163 $1\ldst_port0_addr_i$12[47:0]$6164 + attribute \src "libresoc.v:141543.5-141543.29" switch \initial - attribute \src "libresoc.v:140663.9-140663.17" + attribute \src "libresoc.v:141543.9-141543.17" case 1'1 case end @@ -225244,21 +225664,21 @@ module \l0$130 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_addr_i$12[47:0]$6180 \$32 [47:0] + assign $1\ldst_port0_addr_i$12[47:0]$6164 \$32 [47:0] case - assign $1\ldst_port0_addr_i$12[47:0]$6180 48'000000000000000000000000000000000000000000000000 + assign $1\ldst_port0_addr_i$12[47:0]$6164 48'000000000000000000000000000000000000000000000000 end sync always - update \ldst_port0_addr_i$12 $0\ldst_port0_addr_i$12[47:0]$6179 + update \ldst_port0_addr_i$12 $0\ldst_port0_addr_i$12[47:0]$6163 end - attribute \src "libresoc.v:140672.3-140681.6" - process $proc$libresoc.v:140672$6181 + attribute \src "libresoc.v:141552.3-141561.6" + process $proc$libresoc.v:141552$6165 assign { } { } assign { } { } - assign $0\ldst_port0_addr_i_ok$13[0:0]$6182 $1\ldst_port0_addr_i_ok$13[0:0]$6183 - attribute \src "libresoc.v:140673.5-140673.29" + assign $0\ldst_port0_addr_i_ok$13[0:0]$6166 $1\ldst_port0_addr_i_ok$13[0:0]$6167 + attribute \src "libresoc.v:141553.5-141553.29" switch \initial - attribute \src "libresoc.v:140673.9-140673.17" + attribute \src "libresoc.v:141553.9-141553.17" case 1'1 case end @@ -225267,24 +225687,24 @@ module \l0$130 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_addr_i_ok$13[0:0]$6183 \ldst_port0_addr_i_ok + assign $1\ldst_port0_addr_i_ok$13[0:0]$6167 \ldst_port0_addr_i_ok case - assign $1\ldst_port0_addr_i_ok$13[0:0]$6183 1'0 + assign $1\ldst_port0_addr_i_ok$13[0:0]$6167 1'0 end sync always - update \ldst_port0_addr_i_ok$13 $0\ldst_port0_addr_i_ok$13[0:0]$6182 + update \ldst_port0_addr_i_ok$13 $0\ldst_port0_addr_i_ok$13[0:0]$6166 end - attribute \src "libresoc.v:140682.3-140692.6" - process $proc$libresoc.v:140682$6184 + attribute \src "libresoc.v:141562.3-141572.6" + process $proc$libresoc.v:141562$6168 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\ldst_port0_st_data_i$18[63:0]$6185 $1\ldst_port0_st_data_i$18[63:0]$6187 - assign $0\ldst_port0_st_data_i_ok$17[0:0]$6186 $1\ldst_port0_st_data_i_ok$17[0:0]$6188 - attribute \src "libresoc.v:140683.5-140683.29" + assign $0\ldst_port0_st_data_i$18[63:0]$6169 $1\ldst_port0_st_data_i$18[63:0]$6171 + assign $0\ldst_port0_st_data_i_ok$17[0:0]$6170 $1\ldst_port0_st_data_i_ok$17[0:0]$6172 + attribute \src "libresoc.v:141563.5-141563.29" switch \initial - attribute \src "libresoc.v:140683.9-140683.17" + attribute \src "libresoc.v:141563.9-141563.17" case 1'1 case end @@ -225294,26 +225714,26 @@ module \l0$130 case 1'1 assign { } { } assign { } { } - assign { $1\ldst_port0_st_data_i_ok$17[0:0]$6188 $1\ldst_port0_st_data_i$18[63:0]$6187 } { \ldst_port0_st_data_i_ok \ldst_port0_st_data_i } + assign { $1\ldst_port0_st_data_i_ok$17[0:0]$6172 $1\ldst_port0_st_data_i$18[63:0]$6171 } { \ldst_port0_st_data_i_ok \ldst_port0_st_data_i } case - assign $1\ldst_port0_st_data_i$18[63:0]$6187 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $1\ldst_port0_st_data_i_ok$17[0:0]$6188 1'0 + assign $1\ldst_port0_st_data_i$18[63:0]$6171 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\ldst_port0_st_data_i_ok$17[0:0]$6172 1'0 end sync always - update \ldst_port0_st_data_i$18 $0\ldst_port0_st_data_i$18[63:0]$6185 - update \ldst_port0_st_data_i_ok$17 $0\ldst_port0_st_data_i_ok$17[0:0]$6186 + update \ldst_port0_st_data_i$18 $0\ldst_port0_st_data_i$18[63:0]$6169 + update \ldst_port0_st_data_i_ok$17 $0\ldst_port0_st_data_i_ok$17[0:0]$6170 end - attribute \src "libresoc.v:140693.3-140703.6" - process $proc$libresoc.v:140693$6189 + attribute \src "libresoc.v:141573.3-141583.6" + process $proc$libresoc.v:141573$6173 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0] assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:140694.5-140694.29" + attribute \src "libresoc.v:141574.5-141574.29" switch \initial - attribute \src "libresoc.v:140694.9-140694.17" + attribute \src "libresoc.v:141574.9-141574.17" case 1'1 case end @@ -225332,14 +225752,14 @@ module \l0$130 update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0] update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0] end - attribute \src "libresoc.v:140704.3-140713.6" - process $proc$libresoc.v:140704$6190 + attribute \src "libresoc.v:141584.3-141593.6" + process $proc$libresoc.v:141584$6174 assign { } { } assign { } { } assign $0\ldst_port0_busy_o[0:0] $1\ldst_port0_busy_o[0:0] - attribute \src "libresoc.v:140705.5-140705.29" + attribute \src "libresoc.v:141585.5-141585.29" switch \initial - attribute \src "libresoc.v:140705.9-140705.17" + attribute \src "libresoc.v:141585.9-141585.17" case 1'1 case end @@ -225355,14 +225775,14 @@ module \l0$130 sync always update \ldst_port0_busy_o $0\ldst_port0_busy_o[0:0] end - attribute \src "libresoc.v:140714.3-140723.6" - process $proc$libresoc.v:140714$6191 + attribute \src "libresoc.v:141594.3-141603.6" + process $proc$libresoc.v:141594$6175 assign { } { } assign { } { } assign $0\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:140715.5-140715.29" + attribute \src "libresoc.v:141595.5-141595.29" switch \initial - attribute \src "libresoc.v:140715.9-140715.17" + attribute \src "libresoc.v:141595.9-141595.17" case 1'1 case end @@ -225378,8 +225798,8 @@ module \l0$130 sync always update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0] end - attribute \src "libresoc.v:140724.3-140740.6" - process $proc$libresoc.v:140724$6192 + attribute \src "libresoc.v:141604.3-141620.6" + process $proc$libresoc.v:141604$6176 assign { } { } assign { } { } assign { } { } @@ -225396,17 +225816,17 @@ module \l0$130 assign { } { } assign { } { } assign { } { } - assign $0\ldst_port0_exc_$signal[0:0]$6193 $1\ldst_port0_exc_$signal[0:0]$6201 - assign $0\ldst_port0_exc_$signal$1[0:0]$6194 $1\ldst_port0_exc_$signal$1[0:0]$6202 - assign $0\ldst_port0_exc_$signal$2[0:0]$6195 $1\ldst_port0_exc_$signal$2[0:0]$6203 - assign $0\ldst_port0_exc_$signal$3[0:0]$6196 $1\ldst_port0_exc_$signal$3[0:0]$6204 - assign $0\ldst_port0_exc_$signal$4[0:0]$6197 $1\ldst_port0_exc_$signal$4[0:0]$6205 - assign $0\ldst_port0_exc_$signal$5[0:0]$6198 $1\ldst_port0_exc_$signal$5[0:0]$6206 - assign $0\ldst_port0_exc_$signal$6[0:0]$6199 $1\ldst_port0_exc_$signal$6[0:0]$6207 - assign $0\ldst_port0_exc_$signal$7[0:0]$6200 $1\ldst_port0_exc_$signal$7[0:0]$6208 - attribute \src "libresoc.v:140725.5-140725.29" + assign $0\ldst_port0_exc_$signal[0:0]$6177 $1\ldst_port0_exc_$signal[0:0]$6185 + assign $0\ldst_port0_exc_$signal$1[0:0]$6178 $1\ldst_port0_exc_$signal$1[0:0]$6186 + assign $0\ldst_port0_exc_$signal$2[0:0]$6179 $1\ldst_port0_exc_$signal$2[0:0]$6187 + assign $0\ldst_port0_exc_$signal$3[0:0]$6180 $1\ldst_port0_exc_$signal$3[0:0]$6188 + assign $0\ldst_port0_exc_$signal$4[0:0]$6181 $1\ldst_port0_exc_$signal$4[0:0]$6189 + assign $0\ldst_port0_exc_$signal$5[0:0]$6182 $1\ldst_port0_exc_$signal$5[0:0]$6190 + assign $0\ldst_port0_exc_$signal$6[0:0]$6183 $1\ldst_port0_exc_$signal$6[0:0]$6191 + assign $0\ldst_port0_exc_$signal$7[0:0]$6184 $1\ldst_port0_exc_$signal$7[0:0]$6192 + attribute \src "libresoc.v:141605.5-141605.29" switch \initial - attribute \src "libresoc.v:140725.9-140725.17" + attribute \src "libresoc.v:141605.9-141605.17" case 1'1 case end @@ -225422,36 +225842,36 @@ module \l0$130 assign { } { } assign { } { } assign { } { } - assign { $1\ldst_port0_exc_$signal$7[0:0]$6208 $1\ldst_port0_exc_$signal$6[0:0]$6207 $1\ldst_port0_exc_$signal$5[0:0]$6206 $1\ldst_port0_exc_$signal$4[0:0]$6205 $1\ldst_port0_exc_$signal$3[0:0]$6204 $1\ldst_port0_exc_$signal$2[0:0]$6203 $1\ldst_port0_exc_$signal$1[0:0]$6202 $1\ldst_port0_exc_$signal[0:0]$6201 } { \ldst_port0_exc_$signal$39 \ldst_port0_exc_$signal$38 \ldst_port0_exc_$signal$37 \ldst_port0_exc_$signal$36 \ldst_port0_exc_$signal$35 \ldst_port0_exc_$signal$34 \ldst_port0_exc_$signal$33 \ldst_port0_exc_$signal$19 } + assign { $1\ldst_port0_exc_$signal$7[0:0]$6192 $1\ldst_port0_exc_$signal$6[0:0]$6191 $1\ldst_port0_exc_$signal$5[0:0]$6190 $1\ldst_port0_exc_$signal$4[0:0]$6189 $1\ldst_port0_exc_$signal$3[0:0]$6188 $1\ldst_port0_exc_$signal$2[0:0]$6187 $1\ldst_port0_exc_$signal$1[0:0]$6186 $1\ldst_port0_exc_$signal[0:0]$6185 } { \ldst_port0_exc_$signal$39 \ldst_port0_exc_$signal$38 \ldst_port0_exc_$signal$37 \ldst_port0_exc_$signal$36 \ldst_port0_exc_$signal$35 \ldst_port0_exc_$signal$34 \ldst_port0_exc_$signal$33 \ldst_port0_exc_$signal$19 } case - assign $1\ldst_port0_exc_$signal[0:0]$6201 1'0 - assign $1\ldst_port0_exc_$signal$1[0:0]$6202 1'0 - assign $1\ldst_port0_exc_$signal$2[0:0]$6203 1'0 - assign $1\ldst_port0_exc_$signal$3[0:0]$6204 1'0 - assign $1\ldst_port0_exc_$signal$4[0:0]$6205 1'0 - assign $1\ldst_port0_exc_$signal$5[0:0]$6206 1'0 - assign $1\ldst_port0_exc_$signal$6[0:0]$6207 1'0 - assign $1\ldst_port0_exc_$signal$7[0:0]$6208 1'0 + assign $1\ldst_port0_exc_$signal[0:0]$6185 1'0 + assign $1\ldst_port0_exc_$signal$1[0:0]$6186 1'0 + assign $1\ldst_port0_exc_$signal$2[0:0]$6187 1'0 + assign $1\ldst_port0_exc_$signal$3[0:0]$6188 1'0 + assign $1\ldst_port0_exc_$signal$4[0:0]$6189 1'0 + assign $1\ldst_port0_exc_$signal$5[0:0]$6190 1'0 + assign $1\ldst_port0_exc_$signal$6[0:0]$6191 1'0 + assign $1\ldst_port0_exc_$signal$7[0:0]$6192 1'0 end sync always - update \ldst_port0_exc_$signal $0\ldst_port0_exc_$signal[0:0]$6193 - update \ldst_port0_exc_$signal$1 $0\ldst_port0_exc_$signal$1[0:0]$6194 - update \ldst_port0_exc_$signal$2 $0\ldst_port0_exc_$signal$2[0:0]$6195 - update \ldst_port0_exc_$signal$3 $0\ldst_port0_exc_$signal$3[0:0]$6196 - update \ldst_port0_exc_$signal$4 $0\ldst_port0_exc_$signal$4[0:0]$6197 - update \ldst_port0_exc_$signal$5 $0\ldst_port0_exc_$signal$5[0:0]$6198 - update \ldst_port0_exc_$signal$6 $0\ldst_port0_exc_$signal$6[0:0]$6199 - update \ldst_port0_exc_$signal$7 $0\ldst_port0_exc_$signal$7[0:0]$6200 + update \ldst_port0_exc_$signal $0\ldst_port0_exc_$signal[0:0]$6177 + update \ldst_port0_exc_$signal$1 $0\ldst_port0_exc_$signal$1[0:0]$6178 + update \ldst_port0_exc_$signal$2 $0\ldst_port0_exc_$signal$2[0:0]$6179 + update \ldst_port0_exc_$signal$3 $0\ldst_port0_exc_$signal$3[0:0]$6180 + update \ldst_port0_exc_$signal$4 $0\ldst_port0_exc_$signal$4[0:0]$6181 + update \ldst_port0_exc_$signal$5 $0\ldst_port0_exc_$signal$5[0:0]$6182 + update \ldst_port0_exc_$signal$6 $0\ldst_port0_exc_$signal$6[0:0]$6183 + update \ldst_port0_exc_$signal$7 $0\ldst_port0_exc_$signal$7[0:0]$6184 end - attribute \src "libresoc.v:140741.3-140755.6" - process $proc$libresoc.v:140741$6209 + attribute \src "libresoc.v:141621.3-141635.6" + process $proc$libresoc.v:141621$6193 assign { } { } assign { } { } assign { } { } - assign $0\idx_l$23$next[0:0]$6210 $2\idx_l$23$next[0:0]$6212 - attribute \src "libresoc.v:140742.5-140742.29" + assign $0\idx_l$23$next[0:0]$6194 $2\idx_l$23$next[0:0]$6196 + attribute \src "libresoc.v:141622.5-141622.29" switch \initial - attribute \src "libresoc.v:140742.9-140742.17" + attribute \src "libresoc.v:141622.9-141622.17" case 1'1 case end @@ -225460,30 +225880,30 @@ module \l0$130 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\idx_l$23$next[0:0]$6211 \pick_o + assign $1\idx_l$23$next[0:0]$6195 \pick_o case - assign $1\idx_l$23$next[0:0]$6211 \idx_l$23 + assign $1\idx_l$23$next[0:0]$6195 \idx_l$23 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\idx_l$23$next[0:0]$6212 1'0 + assign $2\idx_l$23$next[0:0]$6196 1'0 case - assign $2\idx_l$23$next[0:0]$6212 $1\idx_l$23$next[0:0]$6211 + assign $2\idx_l$23$next[0:0]$6196 $1\idx_l$23$next[0:0]$6195 end sync always - update \idx_l$23$next $0\idx_l$23$next[0:0]$6210 + update \idx_l$23$next $0\idx_l$23$next[0:0]$6194 end - attribute \src "libresoc.v:140756.3-140765.6" - process $proc$libresoc.v:140756$6213 + attribute \src "libresoc.v:141636.3-141645.6" + process $proc$libresoc.v:141636$6197 assign { } { } assign { } { } assign $0\ldst_port0_mmu_done[0:0] $1\ldst_port0_mmu_done[0:0] - attribute \src "libresoc.v:140757.5-140757.29" + attribute \src "libresoc.v:141637.5-141637.29" switch \initial - attribute \src "libresoc.v:140757.9-140757.17" + attribute \src "libresoc.v:141637.9-141637.17" case 1'1 case end @@ -225499,14 +225919,14 @@ module \l0$130 sync always update \ldst_port0_mmu_done $0\ldst_port0_mmu_done[0:0] end - attribute \src "libresoc.v:140766.3-140775.6" - process $proc$libresoc.v:140766$6214 + attribute \src "libresoc.v:141646.3-141655.6" + process $proc$libresoc.v:141646$6198 assign { } { } assign { } { } assign $0\ldst_port0_ldst_error[0:0] $1\ldst_port0_ldst_error[0:0] - attribute \src "libresoc.v:140767.5-140767.29" + attribute \src "libresoc.v:141647.5-141647.29" switch \initial - attribute \src "libresoc.v:140767.9-140767.17" + attribute \src "libresoc.v:141647.9-141647.17" case 1'1 case end @@ -225522,14 +225942,14 @@ module \l0$130 sync always update \ldst_port0_ldst_error $0\ldst_port0_ldst_error[0:0] end - attribute \src "libresoc.v:140776.3-140785.6" - process $proc$libresoc.v:140776$6215 + attribute \src "libresoc.v:141656.3-141665.6" + process $proc$libresoc.v:141656$6199 assign { } { } assign { } { } assign $0\ldst_port0_cache_paradox[0:0] $1\ldst_port0_cache_paradox[0:0] - attribute \src "libresoc.v:140777.5-140777.29" + attribute \src "libresoc.v:141657.5-141657.29" switch \initial - attribute \src "libresoc.v:140777.9-140777.17" + attribute \src "libresoc.v:141657.9-141657.17" case 1'1 case end @@ -225545,14 +225965,14 @@ module \l0$130 sync always update \ldst_port0_cache_paradox $0\ldst_port0_cache_paradox[0:0] end - attribute \src "libresoc.v:140786.3-140795.6" - process $proc$libresoc.v:140786$6216 + attribute \src "libresoc.v:141666.3-141675.6" + process $proc$libresoc.v:141666$6200 assign { } { } assign { } { } assign $0\idx_l_s_idx_l[0:0] $1\idx_l_s_idx_l[0:0] - attribute \src "libresoc.v:140787.5-140787.29" + attribute \src "libresoc.v:141667.5-141667.29" switch \initial - attribute \src "libresoc.v:140787.9-140787.17" + attribute \src "libresoc.v:141667.9-141667.17" case 1'1 case end @@ -225568,14 +225988,14 @@ module \l0$130 sync always update \idx_l_s_idx_l $0\idx_l_s_idx_l[0:0] end - attribute \src "libresoc.v:140796.3-140805.6" - process $proc$libresoc.v:140796$6217 + attribute \src "libresoc.v:141676.3-141685.6" + process $proc$libresoc.v:141676$6201 assign { } { } assign { } { } assign $0\idx_l_r_idx_l[0:0] $1\idx_l_r_idx_l[0:0] - attribute \src "libresoc.v:140797.5-140797.29" + attribute \src "libresoc.v:141677.5-141677.29" switch \initial - attribute \src "libresoc.v:140797.9-140797.17" + attribute \src "libresoc.v:141677.9-141677.17" case 1'1 case end @@ -225591,14 +226011,14 @@ module \l0$130 sync always update \idx_l_r_idx_l $0\idx_l_r_idx_l[0:0] end - attribute \src "libresoc.v:140806.3-140820.6" - process $proc$libresoc.v:140806$6218 + attribute \src "libresoc.v:141686.3-141700.6" + process $proc$libresoc.v:141686$6202 assign { } { } assign { } { } assign $0\reset_l_s_reset[0:0] $1\reset_l_s_reset[0:0] - attribute \src "libresoc.v:140807.5-140807.29" + attribute \src "libresoc.v:141687.5-141687.29" switch \initial - attribute \src "libresoc.v:140807.9-140807.17" + attribute \src "libresoc.v:141687.9-141687.17" case 1'1 case end @@ -225623,14 +226043,14 @@ module \l0$130 sync always update \reset_l_s_reset $0\reset_l_s_reset[0:0] end - attribute \src "libresoc.v:140821.3-140830.6" - process $proc$libresoc.v:140821$6219 + attribute \src "libresoc.v:141701.3-141710.6" + process $proc$libresoc.v:141701$6203 assign { } { } assign { } { } assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:140822.5-140822.29" + attribute \src "libresoc.v:141702.5-141702.29" switch \initial - attribute \src "libresoc.v:140822.9-140822.17" + attribute \src "libresoc.v:141702.9-141702.17" case 1'1 case end @@ -225646,14 +226066,14 @@ module \l0$130 sync always update \reset_l_r_reset $0\reset_l_r_reset[0:0] end - attribute \src "libresoc.v:140831.3-140840.6" - process $proc$libresoc.v:140831$6220 + attribute \src "libresoc.v:141711.3-141720.6" + process $proc$libresoc.v:141711$6204 assign { } { } assign { } { } - assign $0\ldst_port0_is_ld_i$8[0:0]$6221 $1\ldst_port0_is_ld_i$8[0:0]$6222 - attribute \src "libresoc.v:140832.5-140832.29" + assign $0\ldst_port0_is_ld_i$8[0:0]$6205 $1\ldst_port0_is_ld_i$8[0:0]$6206 + attribute \src "libresoc.v:141712.5-141712.29" switch \initial - attribute \src "libresoc.v:140832.9-140832.17" + attribute \src "libresoc.v:141712.9-141712.17" case 1'1 case end @@ -225662,21 +226082,21 @@ module \l0$130 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_is_ld_i$8[0:0]$6222 \ldst_port0_is_ld_i + assign $1\ldst_port0_is_ld_i$8[0:0]$6206 \ldst_port0_is_ld_i case - assign $1\ldst_port0_is_ld_i$8[0:0]$6222 1'0 + assign $1\ldst_port0_is_ld_i$8[0:0]$6206 1'0 end sync always - update \ldst_port0_is_ld_i$8 $0\ldst_port0_is_ld_i$8[0:0]$6221 + update \ldst_port0_is_ld_i$8 $0\ldst_port0_is_ld_i$8[0:0]$6205 end - attribute \src "libresoc.v:140841.3-140850.6" - process $proc$libresoc.v:140841$6223 + attribute \src "libresoc.v:141721.3-141730.6" + process $proc$libresoc.v:141721$6207 assign { } { } assign { } { } - assign $0\ldst_port0_is_st_i$9[0:0]$6224 $1\ldst_port0_is_st_i$9[0:0]$6225 - attribute \src "libresoc.v:140842.5-140842.29" + assign $0\ldst_port0_is_st_i$9[0:0]$6208 $1\ldst_port0_is_st_i$9[0:0]$6209 + attribute \src "libresoc.v:141722.5-141722.29" switch \initial - attribute \src "libresoc.v:140842.9-140842.17" + attribute \src "libresoc.v:141722.9-141722.17" case 1'1 case end @@ -225685,21 +226105,21 @@ module \l0$130 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_is_st_i$9[0:0]$6225 \ldst_port0_is_st_i + assign $1\ldst_port0_is_st_i$9[0:0]$6209 \ldst_port0_is_st_i case - assign $1\ldst_port0_is_st_i$9[0:0]$6225 1'0 + assign $1\ldst_port0_is_st_i$9[0:0]$6209 1'0 end sync always - update \ldst_port0_is_st_i$9 $0\ldst_port0_is_st_i$9[0:0]$6224 + update \ldst_port0_is_st_i$9 $0\ldst_port0_is_st_i$9[0:0]$6208 end - attribute \src "libresoc.v:140851.3-140860.6" - process $proc$libresoc.v:140851$6226 + attribute \src "libresoc.v:141731.3-141740.6" + process $proc$libresoc.v:141731$6210 assign { } { } assign { } { } - assign $0\ldst_port0_data_len$11[3:0]$6227 $1\ldst_port0_data_len$11[3:0]$6228 - attribute \src "libresoc.v:140852.5-140852.29" + assign $0\ldst_port0_data_len$11[3:0]$6211 $1\ldst_port0_data_len$11[3:0]$6212 + attribute \src "libresoc.v:141732.5-141732.29" switch \initial - attribute \src "libresoc.v:140852.9-140852.17" + attribute \src "libresoc.v:141732.9-141732.17" case 1'1 case end @@ -225708,21 +226128,21 @@ module \l0$130 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_data_len$11[3:0]$6228 \ldst_port0_data_len + assign $1\ldst_port0_data_len$11[3:0]$6212 \ldst_port0_data_len case - assign $1\ldst_port0_data_len$11[3:0]$6228 4'0000 + assign $1\ldst_port0_data_len$11[3:0]$6212 4'0000 end sync always - update \ldst_port0_data_len$11 $0\ldst_port0_data_len$11[3:0]$6227 + update \ldst_port0_data_len$11 $0\ldst_port0_data_len$11[3:0]$6211 end - attribute \src "libresoc.v:140861.3-140870.6" - process $proc$libresoc.v:140861$6229 + attribute \src "libresoc.v:141741.3-141750.6" + process $proc$libresoc.v:141741$6213 assign { } { } assign { } { } assign $0\ldst_port0_go_die_i[0:0] $1\ldst_port0_go_die_i[0:0] - attribute \src "libresoc.v:140862.5-140862.29" + attribute \src "libresoc.v:141742.5-141742.29" switch \initial - attribute \src "libresoc.v:140862.9-140862.17" + attribute \src "libresoc.v:141742.9-141742.17" case 1'1 case end @@ -225738,10 +226158,10 @@ module \l0$130 sync always update \ldst_port0_go_die_i $0\ldst_port0_go_die_i[0:0] end - connect \$20 $or$libresoc.v:140635$6171_Y - connect \$24 $ternary$libresoc.v:140636$6172_Y - connect \$26 $not$libresoc.v:140637$6173_Y - connect \$28 $not$libresoc.v:140638$6174_Y + connect \$20 $or$libresoc.v:141515$6155_Y + connect \$24 $ternary$libresoc.v:141516$6156_Y + connect \$26 $not$libresoc.v:141517$6157_Y + connect \$28 $not$libresoc.v:141518$6158_Y connect \$22 \$24 connect \$32 \ldst_port0_addr_i connect \ldst_port0_go_die_i$30 1'0 @@ -225758,37 +226178,37 @@ module \l0$130 connect \reset_delay$next \reset_l_q_reset connect \pick_i \$20 end -attribute \src "libresoc.v:140890.1-140948.10" +attribute \src "libresoc.v:141770.1-141828.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.ld_active" attribute \generator "nMigen" module \ld_active - attribute \src "libresoc.v:140891.7-140891.20" + attribute \src "libresoc.v:141771.7-141771.20" wire $0\initial[0:0] - attribute \src "libresoc.v:140936.3-140944.6" - wire $0\q_int$next[0:0]$6244 - attribute \src "libresoc.v:140934.3-140935.27" + attribute \src "libresoc.v:141816.3-141824.6" + wire $0\q_int$next[0:0]$6228 + attribute \src "libresoc.v:141814.3-141815.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:140936.3-140944.6" - wire $1\q_int$next[0:0]$6245 - attribute \src "libresoc.v:140913.7-140913.19" + attribute \src "libresoc.v:141816.3-141824.6" + wire $1\q_int$next[0:0]$6229 + attribute \src "libresoc.v:141793.7-141793.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:140926.17-140926.96" - wire $and$libresoc.v:140926$6234_Y - attribute \src "libresoc.v:140931.17-140931.96" - wire $and$libresoc.v:140931$6239_Y - attribute \src "libresoc.v:140928.18-140928.99" - wire $not$libresoc.v:140928$6236_Y - attribute \src "libresoc.v:140930.17-140930.98" - wire $not$libresoc.v:140930$6238_Y - attribute \src "libresoc.v:140933.17-140933.98" - wire $not$libresoc.v:140933$6241_Y - attribute \src "libresoc.v:140927.18-140927.104" - wire $or$libresoc.v:140927$6235_Y - attribute \src "libresoc.v:140929.18-140929.105" - wire $or$libresoc.v:140929$6237_Y - attribute \src "libresoc.v:140932.17-140932.103" - wire $or$libresoc.v:140932$6240_Y + attribute \src "libresoc.v:141806.17-141806.96" + wire $and$libresoc.v:141806$6218_Y + attribute \src "libresoc.v:141811.17-141811.96" + wire $and$libresoc.v:141811$6223_Y + attribute \src "libresoc.v:141808.18-141808.99" + wire $not$libresoc.v:141808$6220_Y + attribute \src "libresoc.v:141810.17-141810.98" + wire $not$libresoc.v:141810$6222_Y + attribute \src "libresoc.v:141813.17-141813.98" + wire $not$libresoc.v:141813$6225_Y + attribute \src "libresoc.v:141807.18-141807.104" + wire $or$libresoc.v:141807$6219_Y + attribute \src "libresoc.v:141809.18-141809.105" + wire $or$libresoc.v:141809$6221_Y + attribute \src "libresoc.v:141812.17-141812.103" + wire $or$libresoc.v:141812$6224_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -225805,11 +226225,11 @@ module \ld_active wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:140891.7-140891.15" + attribute \src "libresoc.v:141771.7-141771.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -225826,7 +226246,7 @@ module \ld_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_ld_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:140926$6234 + cell $and $and$libresoc.v:141806$6218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225834,10 +226254,10 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:140926$6234_Y + connect \Y $and$libresoc.v:141806$6218_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:140931$6239 + cell $and $and$libresoc.v:141811$6223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225845,34 +226265,34 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:140931$6239_Y + connect \Y $and$libresoc.v:141811$6223_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:140928$6236 + cell $not $not$libresoc.v:141808$6220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_ld_active - connect \Y $not$libresoc.v:140928$6236_Y + connect \Y $not$libresoc.v:141808$6220_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:140930$6238 + cell $not $not$libresoc.v:141810$6222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_ld_active - connect \Y $not$libresoc.v:140930$6238_Y + connect \Y $not$libresoc.v:141810$6222_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:140933$6241 + cell $not $not$libresoc.v:141813$6225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_ld_active - connect \Y $not$libresoc.v:140933$6241_Y + connect \Y $not$libresoc.v:141813$6225_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:140927$6235 + cell $or $or$libresoc.v:141807$6219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225880,10 +226300,10 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_ld_active - connect \Y $or$libresoc.v:140927$6235_Y + connect \Y $or$libresoc.v:141807$6219_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:140929$6237 + cell $or $or$libresoc.v:141809$6221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225891,10 +226311,10 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \q_ld_active connect \B \q_int - connect \Y $or$libresoc.v:140929$6237_Y + connect \Y $or$libresoc.v:141809$6221_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:140932$6240 + cell $or $or$libresoc.v:141812$6224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -225902,39 +226322,39 @@ module \ld_active parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_ld_active - connect \Y $or$libresoc.v:140932$6240_Y + connect \Y $or$libresoc.v:141812$6224_Y end - attribute \src "libresoc.v:140891.7-140891.20" - process $proc$libresoc.v:140891$6246 + attribute \src "libresoc.v:141771.7-141771.20" + process $proc$libresoc.v:141771$6230 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:140913.7-140913.19" - process $proc$libresoc.v:140913$6247 + attribute \src "libresoc.v:141793.7-141793.19" + process $proc$libresoc.v:141793$6231 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:140934.3-140935.27" - process $proc$libresoc.v:140934$6242 + attribute \src "libresoc.v:141814.3-141815.27" + process $proc$libresoc.v:141814$6226 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:140936.3-140944.6" - process $proc$libresoc.v:140936$6243 + attribute \src "libresoc.v:141816.3-141824.6" + process $proc$libresoc.v:141816$6227 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$6244 $1\q_int$next[0:0]$6245 - attribute \src "libresoc.v:140937.5-140937.29" + assign $0\q_int$next[0:0]$6228 $1\q_int$next[0:0]$6229 + attribute \src "libresoc.v:141817.5-141817.29" switch \initial - attribute \src "libresoc.v:140937.9-140937.17" + attribute \src "libresoc.v:141817.9-141817.17" case 1'1 case end @@ -225943,572 +226363,572 @@ module \ld_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$6245 1'0 + assign $1\q_int$next[0:0]$6229 1'0 case - assign $1\q_int$next[0:0]$6245 \$5 + assign $1\q_int$next[0:0]$6229 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$6244 + update \q_int$next $0\q_int$next[0:0]$6228 end - connect \$9 $and$libresoc.v:140926$6234_Y - connect \$11 $or$libresoc.v:140927$6235_Y - connect \$13 $not$libresoc.v:140928$6236_Y - connect \$15 $or$libresoc.v:140929$6237_Y - connect \$1 $not$libresoc.v:140930$6238_Y - connect \$3 $and$libresoc.v:140931$6239_Y - connect \$5 $or$libresoc.v:140932$6240_Y - connect \$7 $not$libresoc.v:140933$6241_Y + connect \$9 $and$libresoc.v:141806$6218_Y + connect \$11 $or$libresoc.v:141807$6219_Y + connect \$13 $not$libresoc.v:141808$6220_Y + connect \$15 $or$libresoc.v:141809$6221_Y + connect \$1 $not$libresoc.v:141810$6222_Y + connect \$3 $and$libresoc.v:141811$6223_Y + connect \$5 $or$libresoc.v:141812$6224_Y + connect \$7 $not$libresoc.v:141813$6225_Y connect \qlq_ld_active \$15 connect \qn_ld_active \$13 connect \q_ld_active \$11 end -attribute \src "libresoc.v:140952.1-142315.10" +attribute \src "libresoc.v:141832.1-143195.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0" attribute \generator "nMigen" module \ldst0 - attribute \src "libresoc.v:141970.3-141978.6" - wire $0\adr_l_r_adr$next[0:0]$6390 - attribute \src "libresoc.v:141852.3-141853.39" + attribute \src "libresoc.v:142850.3-142858.6" + wire $0\adr_l_r_adr$next[0:0]$6374 + attribute \src "libresoc.v:142732.3-142733.39" wire $0\adr_l_r_adr[0:0] - attribute \src "libresoc.v:141798.3-141799.21" + attribute \src "libresoc.v:142678.3-142679.21" wire $0\alu_ok[0:0] - attribute \src "libresoc.v:142135.3-142144.6" + attribute \src "libresoc.v:143015.3-143024.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:142145.3-142154.6" + attribute \src "libresoc.v:143025.3-143034.6" wire width 64 $0\dest2_o[63:0] - attribute \src "libresoc.v:142125.3-142134.6" - wire width 64 $0\ea_r$next[63:0]$6478 - attribute \src "libresoc.v:141800.3-141801.25" + attribute \src "libresoc.v:143005.3-143014.6" + wire width 64 $0\ea_r$next[63:0]$6462 + attribute \src "libresoc.v:142680.3-142681.25" wire width 64 $0\ea_r[63:0] - attribute \src "libresoc.v:140953.7-140953.20" + attribute \src "libresoc.v:141833.7-141833.20" wire $0\initial[0:0] - attribute \src "libresoc.v:142200.3-142219.6" + attribute \src "libresoc.v:143080.3-143099.6" wire width 64 $0\ldd_o[63:0] - attribute \src "libresoc.v:142164.3-142187.6" + attribute \src "libresoc.v:143044.3-143067.6" wire width 64 $0\lddata_r[63:0] - attribute \src "libresoc.v:142067.3-142076.6" - wire width 64 $0\ldo_r$next[63:0]$6463 - attribute \src "libresoc.v:141808.3-141809.27" + attribute \src "libresoc.v:142947.3-142956.6" + wire width 64 $0\ldo_r$next[63:0]$6447 + attribute \src "libresoc.v:142688.3-142689.27" wire width 64 $0\ldo_r[63:0] - attribute \src "libresoc.v:141796.3-141797.33" + attribute \src "libresoc.v:142676.3-142677.33" wire width 96 $0\ldst_port0_addr_i[95:0] - attribute \src "libresoc.v:142155.3-142163.6" - wire $0\ldst_port0_addr_i_ok$next[0:0]$6483 - attribute \src "libresoc.v:141794.3-141795.57" + attribute \src "libresoc.v:143035.3-143043.6" + wire $0\ldst_port0_addr_i_ok$next[0:0]$6467 + attribute \src "libresoc.v:142674.3-142675.57" wire $0\ldst_port0_addr_i_ok[0:0] - attribute \src "libresoc.v:142244.3-142255.6" + attribute \src "libresoc.v:143124.3-143135.6" wire width 64 $0\ldst_port0_st_data_i[63:0] - attribute \src "libresoc.v:142015.3-142023.6" - wire $0\lsd_l_r_lsd$next[0:0]$6405 - attribute \src "libresoc.v:141842.3-141843.39" + attribute \src "libresoc.v:142895.3-142903.6" + wire $0\lsd_l_r_lsd$next[0:0]$6389 + attribute \src "libresoc.v:142722.3-142723.39" wire $0\lsd_l_r_lsd[0:0] - attribute \src "libresoc.v:141943.3-141951.6" - wire $0\opc_l_r_opc$next[0:0]$6381 - attribute \src "libresoc.v:141858.3-141859.39" + attribute \src "libresoc.v:142823.3-142831.6" + wire $0\opc_l_r_opc$next[0:0]$6365 + attribute \src "libresoc.v:142738.3-142739.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:141934.3-141942.6" - wire $0\opc_l_s_opc$next[0:0]$6378 - attribute \src "libresoc.v:141860.3-141861.39" + attribute \src "libresoc.v:142814.3-142822.6" + wire $0\opc_l_s_opc$next[0:0]$6362 + attribute \src "libresoc.v:142740.3-142741.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:142024.3-142066.6" - wire $0\oper_r__byte_reverse$next[0:0]$6408 - attribute \src "libresoc.v:141834.3-141835.57" + attribute \src "libresoc.v:142904.3-142946.6" + wire $0\oper_r__byte_reverse$next[0:0]$6392 + attribute \src "libresoc.v:142714.3-142715.57" wire $0\oper_r__byte_reverse[0:0] - attribute \src "libresoc.v:142024.3-142066.6" - wire width 4 $0\oper_r__data_len$next[3:0]$6409 - attribute \src "libresoc.v:141832.3-141833.49" + attribute \src "libresoc.v:142904.3-142946.6" + wire width 4 $0\oper_r__data_len$next[3:0]$6393 + attribute \src "libresoc.v:142712.3-142713.49" wire width 4 $0\oper_r__data_len[3:0] - attribute \src "libresoc.v:142024.3-142066.6" - wire width 14 $0\oper_r__fn_unit$next[13:0]$6410 - attribute \src "libresoc.v:141812.3-141813.47" + attribute \src "libresoc.v:142904.3-142946.6" + wire width 14 $0\oper_r__fn_unit$next[13:0]$6394 + attribute \src "libresoc.v:142692.3-142693.47" wire width 14 $0\oper_r__fn_unit[13:0] - attribute \src "libresoc.v:142024.3-142066.6" - wire width 64 $0\oper_r__imm_data__data$next[63:0]$6411 - attribute \src "libresoc.v:141814.3-141815.61" + attribute \src "libresoc.v:142904.3-142946.6" + wire width 64 $0\oper_r__imm_data__data$next[63:0]$6395 + attribute \src "libresoc.v:142694.3-142695.61" wire width 64 $0\oper_r__imm_data__data[63:0] - attribute \src "libresoc.v:142024.3-142066.6" - wire $0\oper_r__imm_data__ok$next[0:0]$6412 - attribute \src "libresoc.v:141816.3-141817.57" + attribute \src "libresoc.v:142904.3-142946.6" + wire $0\oper_r__imm_data__ok$next[0:0]$6396 + attribute \src "libresoc.v:142696.3-142697.57" wire $0\oper_r__imm_data__ok[0:0] - attribute \src "libresoc.v:142024.3-142066.6" - wire width 32 $0\oper_r__insn$next[31:0]$6413 - attribute \src "libresoc.v:141840.3-141841.41" + attribute \src "libresoc.v:142904.3-142946.6" + wire width 32 $0\oper_r__insn$next[31:0]$6397 + attribute \src "libresoc.v:142720.3-142721.41" wire width 32 $0\oper_r__insn[31:0] - attribute \src "libresoc.v:142024.3-142066.6" - wire width 7 $0\oper_r__insn_type$next[6:0]$6414 - attribute \src "libresoc.v:141810.3-141811.51" + attribute \src "libresoc.v:142904.3-142946.6" + wire width 7 $0\oper_r__insn_type$next[6:0]$6398 + attribute \src "libresoc.v:142690.3-142691.51" wire width 7 $0\oper_r__insn_type[6:0] - attribute \src "libresoc.v:142024.3-142066.6" - wire $0\oper_r__is_32bit$next[0:0]$6415 - attribute \src "libresoc.v:141828.3-141829.49" + attribute \src "libresoc.v:142904.3-142946.6" + wire $0\oper_r__is_32bit$next[0:0]$6399 + attribute \src "libresoc.v:142708.3-142709.49" wire $0\oper_r__is_32bit[0:0] - attribute \src "libresoc.v:142024.3-142066.6" - wire $0\oper_r__is_signed$next[0:0]$6416 - attribute \src "libresoc.v:141830.3-141831.51" + attribute \src "libresoc.v:142904.3-142946.6" + wire $0\oper_r__is_signed$next[0:0]$6400 + attribute \src "libresoc.v:142710.3-142711.51" wire $0\oper_r__is_signed[0:0] - attribute \src "libresoc.v:142024.3-142066.6" - wire width 2 $0\oper_r__ldst_mode$next[1:0]$6417 - attribute \src "libresoc.v:141838.3-141839.51" + attribute \src "libresoc.v:142904.3-142946.6" + wire width 2 $0\oper_r__ldst_mode$next[1:0]$6401 + attribute \src "libresoc.v:142718.3-142719.51" wire width 2 $0\oper_r__ldst_mode[1:0] - attribute \src "libresoc.v:142024.3-142066.6" - wire $0\oper_r__oe__oe$next[0:0]$6418 - attribute \src "libresoc.v:141824.3-141825.45" + attribute \src "libresoc.v:142904.3-142946.6" + wire $0\oper_r__oe__oe$next[0:0]$6402 + attribute \src "libresoc.v:142704.3-142705.45" wire $0\oper_r__oe__oe[0:0] - attribute \src "libresoc.v:142024.3-142066.6" - wire $0\oper_r__oe__ok$next[0:0]$6419 - attribute \src "libresoc.v:141826.3-141827.45" + attribute \src "libresoc.v:142904.3-142946.6" + wire $0\oper_r__oe__ok$next[0:0]$6403 + attribute \src "libresoc.v:142706.3-142707.45" wire $0\oper_r__oe__ok[0:0] - attribute \src "libresoc.v:142024.3-142066.6" - wire $0\oper_r__rc__ok$next[0:0]$6420 - attribute \src "libresoc.v:141822.3-141823.45" + attribute \src "libresoc.v:142904.3-142946.6" + wire $0\oper_r__rc__ok$next[0:0]$6404 + attribute \src "libresoc.v:142702.3-142703.45" wire $0\oper_r__rc__ok[0:0] - attribute \src "libresoc.v:142024.3-142066.6" - wire $0\oper_r__rc__rc$next[0:0]$6421 - attribute \src "libresoc.v:141820.3-141821.45" + attribute \src "libresoc.v:142904.3-142946.6" + wire $0\oper_r__rc__rc$next[0:0]$6405 + attribute \src "libresoc.v:142700.3-142701.45" wire $0\oper_r__rc__rc[0:0] - attribute \src "libresoc.v:142024.3-142066.6" - wire $0\oper_r__sign_extend$next[0:0]$6422 - attribute \src "libresoc.v:141836.3-141837.55" + attribute \src "libresoc.v:142904.3-142946.6" + wire $0\oper_r__sign_extend$next[0:0]$6406 + attribute \src "libresoc.v:142716.3-142717.55" wire $0\oper_r__sign_extend[0:0] - attribute \src "libresoc.v:142024.3-142066.6" - wire $0\oper_r__zero_a$next[0:0]$6423 - attribute \src "libresoc.v:141818.3-141819.45" + attribute \src "libresoc.v:142904.3-142946.6" + wire $0\oper_r__zero_a$next[0:0]$6407 + attribute \src "libresoc.v:142698.3-142699.45" wire $0\oper_r__zero_a[0:0] - attribute \src "libresoc.v:141862.3-141863.28" + attribute \src "libresoc.v:142742.3-142743.28" wire $0\p_st_go[0:0] - attribute \src "libresoc.v:142188.3-142199.6" + attribute \src "libresoc.v:143068.3-143079.6" wire width 64 $0\revnorev[63:0] - attribute \src "libresoc.v:141961.3-141969.6" - wire width 3 $0\src_l_r_src$next[2:0]$6387 - attribute \src "libresoc.v:141854.3-141855.39" + attribute \src "libresoc.v:142841.3-142849.6" + wire width 3 $0\src_l_r_src$next[2:0]$6371 + attribute \src "libresoc.v:142734.3-142735.39" wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:141952.3-141960.6" - wire width 3 $0\src_l_s_src$next[2:0]$6384 - attribute \src "libresoc.v:141856.3-141857.39" + attribute \src "libresoc.v:142832.3-142840.6" + wire width 3 $0\src_l_s_src$next[2:0]$6368 + attribute \src "libresoc.v:142736.3-142737.39" wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:142077.3-142092.6" - wire width 64 $0\src_r0$next[63:0]$6466 - attribute \src "libresoc.v:141806.3-141807.29" + attribute \src "libresoc.v:142957.3-142972.6" + wire width 64 $0\src_r0$next[63:0]$6450 + attribute \src "libresoc.v:142686.3-142687.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:142093.3-142108.6" - wire width 64 $0\src_r1$next[63:0]$6470 - attribute \src "libresoc.v:141804.3-141805.29" + attribute \src "libresoc.v:142973.3-142988.6" + wire width 64 $0\src_r1$next[63:0]$6454 + attribute \src "libresoc.v:142684.3-142685.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:142109.3-142124.6" - wire width 64 $0\src_r2$next[63:0]$6474 - attribute \src "libresoc.v:141802.3-141803.29" + attribute \src "libresoc.v:142989.3-143004.6" + wire width 64 $0\src_r2$next[63:0]$6458 + attribute \src "libresoc.v:142682.3-142683.29" wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:142220.3-142243.6" + attribute \src "libresoc.v:143100.3-143123.6" wire width 64 $0\stdata_r[63:0] - attribute \src "libresoc.v:142006.3-142014.6" - wire $0\sto_l_r_sto$next[0:0]$6402 - attribute \src "libresoc.v:141844.3-141845.39" + attribute \src "libresoc.v:142886.3-142894.6" + wire $0\sto_l_r_sto$next[0:0]$6386 + attribute \src "libresoc.v:142724.3-142725.39" wire $0\sto_l_r_sto[0:0] - attribute \src "libresoc.v:141997.3-142005.6" - wire $0\upd_l_r_upd$next[0:0]$6399 - attribute \src "libresoc.v:141846.3-141847.39" + attribute \src "libresoc.v:142877.3-142885.6" + wire $0\upd_l_r_upd$next[0:0]$6383 + attribute \src "libresoc.v:142726.3-142727.39" wire $0\upd_l_r_upd[0:0] - attribute \src "libresoc.v:141988.3-141996.6" - wire $0\upd_l_s_upd$next[0:0]$6396 - attribute \src "libresoc.v:141848.3-141849.39" + attribute \src "libresoc.v:142868.3-142876.6" + wire $0\upd_l_s_upd$next[0:0]$6380 + attribute \src "libresoc.v:142728.3-142729.39" wire $0\upd_l_s_upd[0:0] - attribute \src "libresoc.v:141979.3-141987.6" - wire $0\wri_l_r_wri$next[0:0]$6393 - attribute \src "libresoc.v:141850.3-141851.39" + attribute \src "libresoc.v:142859.3-142867.6" + wire $0\wri_l_r_wri$next[0:0]$6377 + attribute \src "libresoc.v:142730.3-142731.39" wire $0\wri_l_r_wri[0:0] - attribute \src "libresoc.v:141970.3-141978.6" - wire $1\adr_l_r_adr$next[0:0]$6391 - attribute \src "libresoc.v:141149.7-141149.25" + attribute \src "libresoc.v:142850.3-142858.6" + wire $1\adr_l_r_adr$next[0:0]$6375 + attribute \src "libresoc.v:142029.7-142029.25" wire $1\adr_l_r_adr[0:0] - attribute \src "libresoc.v:141163.7-141163.20" + attribute \src "libresoc.v:142043.7-142043.20" wire $1\alu_ok[0:0] - attribute \src "libresoc.v:142135.3-142144.6" + attribute \src "libresoc.v:143015.3-143024.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:142145.3-142154.6" + attribute \src "libresoc.v:143025.3-143034.6" wire width 64 $1\dest2_o[63:0] - attribute \src "libresoc.v:142125.3-142134.6" - wire width 64 $1\ea_r$next[63:0]$6479 - attribute \src "libresoc.v:141209.14-141209.41" + attribute \src "libresoc.v:143005.3-143014.6" + wire width 64 $1\ea_r$next[63:0]$6463 + attribute \src "libresoc.v:142089.14-142089.41" wire width 64 $1\ea_r[63:0] - attribute \src "libresoc.v:142200.3-142219.6" + attribute \src "libresoc.v:143080.3-143099.6" wire width 64 $1\ldd_o[63:0] - attribute \src "libresoc.v:142164.3-142187.6" + attribute \src "libresoc.v:143044.3-143067.6" wire width 64 $1\lddata_r[63:0] - attribute \src "libresoc.v:142067.3-142076.6" - wire width 64 $1\ldo_r$next[63:0]$6464 - attribute \src "libresoc.v:141239.14-141239.42" + attribute \src "libresoc.v:142947.3-142956.6" + wire width 64 $1\ldo_r$next[63:0]$6448 + attribute \src "libresoc.v:142119.14-142119.42" wire width 64 $1\ldo_r[63:0] - attribute \src "libresoc.v:141244.14-141244.62" + attribute \src "libresoc.v:142124.14-142124.62" wire width 96 $1\ldst_port0_addr_i[95:0] - attribute \src "libresoc.v:142155.3-142163.6" - wire $1\ldst_port0_addr_i_ok$next[0:0]$6484 - attribute \src "libresoc.v:141249.7-141249.34" + attribute \src "libresoc.v:143035.3-143043.6" + wire $1\ldst_port0_addr_i_ok$next[0:0]$6468 + attribute \src "libresoc.v:142129.7-142129.34" wire $1\ldst_port0_addr_i_ok[0:0] - attribute \src "libresoc.v:142244.3-142255.6" + attribute \src "libresoc.v:143124.3-143135.6" wire width 64 $1\ldst_port0_st_data_i[63:0] - attribute \src "libresoc.v:142015.3-142023.6" - wire $1\lsd_l_r_lsd$next[0:0]$6406 - attribute \src "libresoc.v:141298.7-141298.25" + attribute \src "libresoc.v:142895.3-142903.6" + wire $1\lsd_l_r_lsd$next[0:0]$6390 + attribute \src "libresoc.v:142178.7-142178.25" wire $1\lsd_l_r_lsd[0:0] - attribute \src "libresoc.v:141943.3-141951.6" - wire $1\opc_l_r_opc$next[0:0]$6382 - attribute \src "libresoc.v:141312.7-141312.25" + attribute \src "libresoc.v:142823.3-142831.6" + wire $1\opc_l_r_opc$next[0:0]$6366 + attribute \src "libresoc.v:142192.7-142192.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:141934.3-141942.6" - wire $1\opc_l_s_opc$next[0:0]$6379 - attribute \src "libresoc.v:141316.7-141316.25" + attribute \src "libresoc.v:142814.3-142822.6" + wire $1\opc_l_s_opc$next[0:0]$6363 + attribute \src "libresoc.v:142196.7-142196.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:142024.3-142066.6" - wire $1\oper_r__byte_reverse$next[0:0]$6424 - attribute \src "libresoc.v:141447.7-141447.34" + attribute \src "libresoc.v:142904.3-142946.6" + wire $1\oper_r__byte_reverse$next[0:0]$6408 + attribute \src "libresoc.v:142327.7-142327.34" wire $1\oper_r__byte_reverse[0:0] - attribute \src "libresoc.v:142024.3-142066.6" - wire width 4 $1\oper_r__data_len$next[3:0]$6425 - attribute \src "libresoc.v:141451.13-141451.36" + attribute \src "libresoc.v:142904.3-142946.6" + wire width 4 $1\oper_r__data_len$next[3:0]$6409 + attribute \src "libresoc.v:142331.13-142331.36" wire width 4 $1\oper_r__data_len[3:0] - attribute \src "libresoc.v:142024.3-142066.6" - wire width 14 $1\oper_r__fn_unit$next[13:0]$6426 - attribute \src "libresoc.v:141470.14-141470.40" + attribute \src "libresoc.v:142904.3-142946.6" + wire width 14 $1\oper_r__fn_unit$next[13:0]$6410 + attribute \src "libresoc.v:142350.14-142350.40" wire width 14 $1\oper_r__fn_unit[13:0] - attribute \src "libresoc.v:142024.3-142066.6" - wire width 64 $1\oper_r__imm_data__data$next[63:0]$6427 - attribute \src "libresoc.v:141474.14-141474.59" + attribute \src "libresoc.v:142904.3-142946.6" + wire width 64 $1\oper_r__imm_data__data$next[63:0]$6411 + attribute \src "libresoc.v:142354.14-142354.59" wire width 64 $1\oper_r__imm_data__data[63:0] - attribute \src "libresoc.v:142024.3-142066.6" - wire $1\oper_r__imm_data__ok$next[0:0]$6428 - attribute \src "libresoc.v:141478.7-141478.34" + attribute \src "libresoc.v:142904.3-142946.6" + wire $1\oper_r__imm_data__ok$next[0:0]$6412 + attribute \src "libresoc.v:142358.7-142358.34" wire $1\oper_r__imm_data__ok[0:0] - attribute \src "libresoc.v:142024.3-142066.6" - wire width 32 $1\oper_r__insn$next[31:0]$6429 - attribute \src "libresoc.v:141482.14-141482.34" + attribute \src "libresoc.v:142904.3-142946.6" + wire width 32 $1\oper_r__insn$next[31:0]$6413 + attribute \src "libresoc.v:142362.14-142362.34" wire width 32 $1\oper_r__insn[31:0] - attribute \src "libresoc.v:142024.3-142066.6" - wire width 7 $1\oper_r__insn_type$next[6:0]$6430 - attribute \src "libresoc.v:141561.13-141561.38" + attribute \src "libresoc.v:142904.3-142946.6" + wire width 7 $1\oper_r__insn_type$next[6:0]$6414 + attribute \src "libresoc.v:142441.13-142441.38" wire width 7 $1\oper_r__insn_type[6:0] - attribute \src "libresoc.v:142024.3-142066.6" - wire $1\oper_r__is_32bit$next[0:0]$6431 - attribute \src "libresoc.v:141565.7-141565.30" + attribute \src "libresoc.v:142904.3-142946.6" + wire $1\oper_r__is_32bit$next[0:0]$6415 + attribute \src "libresoc.v:142445.7-142445.30" wire $1\oper_r__is_32bit[0:0] - attribute \src "libresoc.v:142024.3-142066.6" - wire $1\oper_r__is_signed$next[0:0]$6432 - attribute \src "libresoc.v:141569.7-141569.31" + attribute \src "libresoc.v:142904.3-142946.6" + wire $1\oper_r__is_signed$next[0:0]$6416 + attribute \src "libresoc.v:142449.7-142449.31" wire $1\oper_r__is_signed[0:0] - attribute \src "libresoc.v:142024.3-142066.6" - wire width 2 $1\oper_r__ldst_mode$next[1:0]$6433 - attribute \src "libresoc.v:141578.13-141578.37" + attribute \src "libresoc.v:142904.3-142946.6" + wire width 2 $1\oper_r__ldst_mode$next[1:0]$6417 + attribute \src "libresoc.v:142458.13-142458.37" wire width 2 $1\oper_r__ldst_mode[1:0] - attribute \src "libresoc.v:142024.3-142066.6" - wire $1\oper_r__oe__oe$next[0:0]$6434 - attribute \src "libresoc.v:141582.7-141582.28" + attribute \src "libresoc.v:142904.3-142946.6" + wire $1\oper_r__oe__oe$next[0:0]$6418 + attribute \src "libresoc.v:142462.7-142462.28" wire $1\oper_r__oe__oe[0:0] - attribute \src "libresoc.v:142024.3-142066.6" - wire $1\oper_r__oe__ok$next[0:0]$6435 - attribute \src "libresoc.v:141586.7-141586.28" + attribute \src "libresoc.v:142904.3-142946.6" + wire $1\oper_r__oe__ok$next[0:0]$6419 + attribute \src "libresoc.v:142466.7-142466.28" wire $1\oper_r__oe__ok[0:0] - attribute \src "libresoc.v:142024.3-142066.6" - wire $1\oper_r__rc__ok$next[0:0]$6436 - attribute \src "libresoc.v:141590.7-141590.28" + attribute \src "libresoc.v:142904.3-142946.6" + wire $1\oper_r__rc__ok$next[0:0]$6420 + attribute \src "libresoc.v:142470.7-142470.28" wire $1\oper_r__rc__ok[0:0] - attribute \src "libresoc.v:142024.3-142066.6" - wire $1\oper_r__rc__rc$next[0:0]$6437 - attribute \src "libresoc.v:141594.7-141594.28" + attribute \src "libresoc.v:142904.3-142946.6" + wire $1\oper_r__rc__rc$next[0:0]$6421 + attribute \src "libresoc.v:142474.7-142474.28" wire $1\oper_r__rc__rc[0:0] - attribute \src "libresoc.v:142024.3-142066.6" - wire $1\oper_r__sign_extend$next[0:0]$6438 - attribute \src "libresoc.v:141598.7-141598.33" + attribute \src "libresoc.v:142904.3-142946.6" + wire $1\oper_r__sign_extend$next[0:0]$6422 + attribute \src "libresoc.v:142478.7-142478.33" wire $1\oper_r__sign_extend[0:0] - attribute \src "libresoc.v:142024.3-142066.6" - wire $1\oper_r__zero_a$next[0:0]$6439 - attribute \src "libresoc.v:141602.7-141602.28" + attribute \src "libresoc.v:142904.3-142946.6" + wire $1\oper_r__zero_a$next[0:0]$6423 + attribute \src "libresoc.v:142482.7-142482.28" wire $1\oper_r__zero_a[0:0] - attribute \src "libresoc.v:141606.7-141606.21" + attribute \src "libresoc.v:142486.7-142486.21" wire $1\p_st_go[0:0] - attribute \src "libresoc.v:142188.3-142199.6" + attribute \src "libresoc.v:143068.3-143079.6" wire width 64 $1\revnorev[63:0] - attribute \src "libresoc.v:141961.3-141969.6" - wire width 3 $1\src_l_r_src$next[2:0]$6388 - attribute \src "libresoc.v:141648.13-141648.31" + attribute \src "libresoc.v:142841.3-142849.6" + wire width 3 $1\src_l_r_src$next[2:0]$6372 + attribute \src "libresoc.v:142528.13-142528.31" wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:141952.3-141960.6" - wire width 3 $1\src_l_s_src$next[2:0]$6385 - attribute \src "libresoc.v:141652.13-141652.31" + attribute \src "libresoc.v:142832.3-142840.6" + wire width 3 $1\src_l_s_src$next[2:0]$6369 + attribute \src "libresoc.v:142532.13-142532.31" wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:142077.3-142092.6" - wire width 64 $1\src_r0$next[63:0]$6467 - attribute \src "libresoc.v:141656.14-141656.43" + attribute \src "libresoc.v:142957.3-142972.6" + wire width 64 $1\src_r0$next[63:0]$6451 + attribute \src "libresoc.v:142536.14-142536.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:142093.3-142108.6" - wire width 64 $1\src_r1$next[63:0]$6471 - attribute \src "libresoc.v:141660.14-141660.43" + attribute \src "libresoc.v:142973.3-142988.6" + wire width 64 $1\src_r1$next[63:0]$6455 + attribute \src "libresoc.v:142540.14-142540.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:142109.3-142124.6" - wire width 64 $1\src_r2$next[63:0]$6475 - attribute \src "libresoc.v:141664.14-141664.43" + attribute \src "libresoc.v:142989.3-143004.6" + wire width 64 $1\src_r2$next[63:0]$6459 + attribute \src "libresoc.v:142544.14-142544.43" wire width 64 $1\src_r2[63:0] - attribute \src "libresoc.v:142220.3-142243.6" + attribute \src "libresoc.v:143100.3-143123.6" wire width 64 $1\stdata_r[63:0] - attribute \src "libresoc.v:142006.3-142014.6" - wire $1\sto_l_r_sto$next[0:0]$6403 - attribute \src "libresoc.v:141674.7-141674.25" + attribute \src "libresoc.v:142886.3-142894.6" + wire $1\sto_l_r_sto$next[0:0]$6387 + attribute \src "libresoc.v:142554.7-142554.25" wire $1\sto_l_r_sto[0:0] - attribute \src "libresoc.v:141997.3-142005.6" - wire $1\upd_l_r_upd$next[0:0]$6400 - attribute \src "libresoc.v:141684.7-141684.25" + attribute \src "libresoc.v:142877.3-142885.6" + wire $1\upd_l_r_upd$next[0:0]$6384 + attribute \src "libresoc.v:142564.7-142564.25" wire $1\upd_l_r_upd[0:0] - attribute \src "libresoc.v:141988.3-141996.6" - wire $1\upd_l_s_upd$next[0:0]$6397 - attribute \src "libresoc.v:141688.7-141688.25" + attribute \src "libresoc.v:142868.3-142876.6" + wire $1\upd_l_s_upd$next[0:0]$6381 + attribute \src "libresoc.v:142568.7-142568.25" wire $1\upd_l_s_upd[0:0] - attribute \src "libresoc.v:141979.3-141987.6" - wire $1\wri_l_r_wri$next[0:0]$6394 - attribute \src "libresoc.v:141698.7-141698.25" + attribute \src "libresoc.v:142859.3-142867.6" + wire $1\wri_l_r_wri$next[0:0]$6378 + attribute \src "libresoc.v:142578.7-142578.25" wire $1\wri_l_r_wri[0:0] - attribute \src "libresoc.v:142200.3-142219.6" + attribute \src "libresoc.v:143080.3-143099.6" wire width 64 $2\ldd_o[63:0] - attribute \src "libresoc.v:142164.3-142187.6" + attribute \src "libresoc.v:143044.3-143067.6" wire width 64 $2\lddata_r[63:0] - attribute \src "libresoc.v:142024.3-142066.6" - wire $2\oper_r__byte_reverse$next[0:0]$6440 - attribute \src "libresoc.v:142024.3-142066.6" - wire width 4 $2\oper_r__data_len$next[3:0]$6441 - attribute \src "libresoc.v:142024.3-142066.6" - wire width 14 $2\oper_r__fn_unit$next[13:0]$6442 - attribute \src "libresoc.v:142024.3-142066.6" - wire width 64 $2\oper_r__imm_data__data$next[63:0]$6443 - attribute \src "libresoc.v:142024.3-142066.6" - wire $2\oper_r__imm_data__ok$next[0:0]$6444 - attribute \src "libresoc.v:142024.3-142066.6" - wire width 32 $2\oper_r__insn$next[31:0]$6445 - attribute \src "libresoc.v:142024.3-142066.6" - wire width 7 $2\oper_r__insn_type$next[6:0]$6446 - attribute \src "libresoc.v:142024.3-142066.6" - wire $2\oper_r__is_32bit$next[0:0]$6447 - attribute \src "libresoc.v:142024.3-142066.6" - wire $2\oper_r__is_signed$next[0:0]$6448 - attribute \src "libresoc.v:142024.3-142066.6" - wire width 2 $2\oper_r__ldst_mode$next[1:0]$6449 - attribute \src "libresoc.v:142024.3-142066.6" - wire $2\oper_r__oe__oe$next[0:0]$6450 - attribute \src "libresoc.v:142024.3-142066.6" - wire $2\oper_r__oe__ok$next[0:0]$6451 - attribute \src "libresoc.v:142024.3-142066.6" - wire $2\oper_r__rc__ok$next[0:0]$6452 - attribute \src "libresoc.v:142024.3-142066.6" - wire $2\oper_r__rc__rc$next[0:0]$6453 - attribute \src "libresoc.v:142024.3-142066.6" - wire $2\oper_r__sign_extend$next[0:0]$6454 - attribute \src "libresoc.v:142024.3-142066.6" - wire $2\oper_r__zero_a$next[0:0]$6455 - attribute \src "libresoc.v:142077.3-142092.6" - wire width 64 $2\src_r0$next[63:0]$6468 - attribute \src "libresoc.v:142093.3-142108.6" - wire width 64 $2\src_r1$next[63:0]$6472 - attribute \src "libresoc.v:142109.3-142124.6" - wire width 64 $2\src_r2$next[63:0]$6476 - attribute \src "libresoc.v:142220.3-142243.6" + attribute \src "libresoc.v:142904.3-142946.6" + wire $2\oper_r__byte_reverse$next[0:0]$6424 + attribute \src "libresoc.v:142904.3-142946.6" + wire width 4 $2\oper_r__data_len$next[3:0]$6425 + attribute \src "libresoc.v:142904.3-142946.6" + wire width 14 $2\oper_r__fn_unit$next[13:0]$6426 + attribute \src "libresoc.v:142904.3-142946.6" + wire width 64 $2\oper_r__imm_data__data$next[63:0]$6427 + attribute \src "libresoc.v:142904.3-142946.6" + wire $2\oper_r__imm_data__ok$next[0:0]$6428 + attribute \src "libresoc.v:142904.3-142946.6" + wire width 32 $2\oper_r__insn$next[31:0]$6429 + attribute \src "libresoc.v:142904.3-142946.6" + wire width 7 $2\oper_r__insn_type$next[6:0]$6430 + attribute \src "libresoc.v:142904.3-142946.6" + wire $2\oper_r__is_32bit$next[0:0]$6431 + attribute \src "libresoc.v:142904.3-142946.6" + wire $2\oper_r__is_signed$next[0:0]$6432 + attribute \src "libresoc.v:142904.3-142946.6" + wire width 2 $2\oper_r__ldst_mode$next[1:0]$6433 + attribute \src "libresoc.v:142904.3-142946.6" + wire $2\oper_r__oe__oe$next[0:0]$6434 + attribute \src "libresoc.v:142904.3-142946.6" + wire $2\oper_r__oe__ok$next[0:0]$6435 + attribute \src "libresoc.v:142904.3-142946.6" + wire $2\oper_r__rc__ok$next[0:0]$6436 + attribute \src "libresoc.v:142904.3-142946.6" + wire $2\oper_r__rc__rc$next[0:0]$6437 + attribute \src "libresoc.v:142904.3-142946.6" + wire $2\oper_r__sign_extend$next[0:0]$6438 + attribute \src "libresoc.v:142904.3-142946.6" + wire $2\oper_r__zero_a$next[0:0]$6439 + attribute \src "libresoc.v:142957.3-142972.6" + wire width 64 $2\src_r0$next[63:0]$6452 + attribute \src "libresoc.v:142973.3-142988.6" + wire width 64 $2\src_r1$next[63:0]$6456 + attribute \src "libresoc.v:142989.3-143004.6" + wire width 64 $2\src_r2$next[63:0]$6460 + attribute \src "libresoc.v:143100.3-143123.6" wire width 64 $2\stdata_r[63:0] - attribute \src "libresoc.v:142024.3-142066.6" - wire width 64 $3\oper_r__imm_data__data$next[63:0]$6456 - attribute \src "libresoc.v:142024.3-142066.6" - wire $3\oper_r__imm_data__ok$next[0:0]$6457 - attribute \src "libresoc.v:142024.3-142066.6" - wire $3\oper_r__oe__oe$next[0:0]$6458 - attribute \src "libresoc.v:142024.3-142066.6" - wire $3\oper_r__oe__ok$next[0:0]$6459 - attribute \src "libresoc.v:142024.3-142066.6" - wire $3\oper_r__rc__ok$next[0:0]$6460 - attribute \src "libresoc.v:142024.3-142066.6" - wire $3\oper_r__rc__rc$next[0:0]$6461 - attribute \src "libresoc.v:141780.18-141780.124" - wire width 65 $add$libresoc.v:141780$6328_Y - attribute \src "libresoc.v:141703.19-141703.118" - wire $and$libresoc.v:141703$6248_Y - attribute \src "libresoc.v:141704.19-141704.125" - wire $and$libresoc.v:141704$6249_Y - attribute \src "libresoc.v:141705.19-141705.120" - wire $and$libresoc.v:141705$6250_Y - attribute \src "libresoc.v:141706.19-141706.125" - wire $and$libresoc.v:141706$6251_Y - attribute \src "libresoc.v:141707.19-141707.118" - wire $and$libresoc.v:141707$6252_Y - attribute \src "libresoc.v:141709.19-141709.119" - wire $and$libresoc.v:141709$6254_Y - attribute \src "libresoc.v:141710.19-141710.123" - wire $and$libresoc.v:141710$6255_Y - attribute \src "libresoc.v:141711.19-141711.123" - wire $and$libresoc.v:141711$6256_Y - attribute \src "libresoc.v:141712.19-141712.120" - wire $and$libresoc.v:141712$6257_Y - attribute \src "libresoc.v:141713.19-141713.123" - wire $and$libresoc.v:141713$6258_Y - attribute \src "libresoc.v:141714.19-141714.119" - wire $and$libresoc.v:141714$6259_Y - attribute \src "libresoc.v:141715.19-141715.123" - wire $and$libresoc.v:141715$6260_Y - attribute \src "libresoc.v:141716.19-141716.125" - wire $and$libresoc.v:141716$6261_Y - attribute \src "libresoc.v:141718.19-141718.116" - wire $and$libresoc.v:141718$6263_Y - attribute \src "libresoc.v:141720.19-141720.120" - wire $and$libresoc.v:141720$6265_Y - attribute \src "libresoc.v:141721.19-141721.123" - wire $and$libresoc.v:141721$6266_Y - attribute \src "libresoc.v:141725.19-141725.125" - wire $and$libresoc.v:141725$6270_Y - attribute \src "libresoc.v:141726.19-141726.123" - wire $and$libresoc.v:141726$6271_Y - attribute \src "libresoc.v:141731.19-141731.116" - wire $and$libresoc.v:141731$6276_Y - attribute \src "libresoc.v:141733.19-141733.116" - wire $and$libresoc.v:141733$6278_Y - attribute \src "libresoc.v:141736.19-141736.118" - wire $and$libresoc.v:141736$6281_Y - attribute \src "libresoc.v:141738.19-141738.125" - wire $and$libresoc.v:141738$6283_Y - attribute \src "libresoc.v:141741.19-141741.160" - wire width 3 $and$libresoc.v:141741$6286_Y - attribute \src "libresoc.v:141742.19-141742.122" - wire $and$libresoc.v:141742$6287_Y - attribute \src "libresoc.v:141743.19-141743.122" - wire $and$libresoc.v:141743$6288_Y - attribute \src "libresoc.v:141745.19-141745.122" - wire $and$libresoc.v:141745$6291_Y - attribute \src "libresoc.v:141757.18-141757.123" - wire $and$libresoc.v:141757$6305_Y - attribute \src "libresoc.v:141758.18-141758.123" - wire $and$libresoc.v:141758$6306_Y - attribute \src "libresoc.v:141760.18-141760.114" - wire $and$libresoc.v:141760$6308_Y - attribute \src "libresoc.v:141762.18-141762.113" - wire $and$libresoc.v:141762$6310_Y - attribute \src "libresoc.v:141765.18-141765.113" - wire $and$libresoc.v:141765$6313_Y - attribute \src "libresoc.v:141769.18-141769.113" - wire $and$libresoc.v:141769$6317_Y - attribute \src "libresoc.v:141772.18-141772.119" - wire $and$libresoc.v:141772$6320_Y - attribute \src "libresoc.v:141781.18-141781.150" - wire width 3 $and$libresoc.v:141781$6329_Y - attribute \src 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"libresoc.v:142653.18-142653.118" + wire $or$libresoc.v:142653$6305_Y + attribute \src "libresoc.v:142654.18-142654.118" + wire $or$libresoc.v:142654$6306_Y + attribute \src "libresoc.v:142655.18-142655.114" + wire $or$libresoc.v:142655$6307_Y + attribute \src "libresoc.v:142668.17-142668.124" + wire $or$libresoc.v:142668$6320_Y + attribute \src "libresoc.v:142669.18-142669.132" + wire $or$libresoc.v:142669$6321_Y + attribute \src "libresoc.v:142670.18-142670.134" + wire $or$libresoc.v:142670$6322_Y + attribute \src "libresoc.v:142624.19-142624.110" + wire width 96 $pos$libresoc.v:142624$6274_Y + attribute \src "libresoc.v:142626.19-142626.116" + wire width 64 $pos$libresoc.v:142626$6277_Y + attribute \src "libresoc.v:142627.19-142627.148" + wire width 64 $pos$libresoc.v:142627$6278_Y + attribute \src "libresoc.v:142629.19-142629.206" + wire width 64 $pos$libresoc.v:142629$6280_Y + attribute \src "libresoc.v:142631.19-142631.102" + wire width 64 $pos$libresoc.v:142631$6283_Y + attribute \src "libresoc.v:142632.19-142632.120" + wire width 64 $pos$libresoc.v:142632$6284_Y + attribute \src "libresoc.v:142633.19-142633.150" + wire width 64 $pos$libresoc.v:142633$6285_Y + attribute \src "libresoc.v:142656.18-142656.107" + wire width 64 $ternary$libresoc.v:142656$6308_Y + attribute \src "libresoc.v:142657.18-142657.112" + wire width 64 $ternary$libresoc.v:142657$6309_Y + attribute \src "libresoc.v:142658.18-142658.147" + wire width 64 $ternary$libresoc.v:142658$6310_Y + attribute \src "libresoc.v:142659.18-142659.155" + wire width 64 $ternary$libresoc.v:142659$6311_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" @@ -226723,9 +227143,9 @@ module \ldst0 wire \alu_ok$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:270" wire \alu_valid - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 53 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" wire input 3 \cu_ad__go_i @@ -226783,7 +227203,7 @@ module \ldst0 wire \exc_$signal$184 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \exc_$signal$185 - attribute \src "libresoc.v:140953.7-140953.15" + attribute \src "libresoc.v:141833.7-141833.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:110" wire \ld_o @@ -227258,7 +227678,7 @@ module \ldst0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \wri_l_s_wri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:414" - cell $add $add$libresoc.v:141780$6328 + cell $add $add$libresoc.v:142660$6312 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -227266,10 +227686,10 @@ module \ldst0 parameter \Y_WIDTH 65 connect \A \src1_or_z connect \B \src2_or_imm - connect \Y $add$libresoc.v:141780$6328_Y + connect \Y $add$libresoc.v:142660$6312_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" - cell $and $and$libresoc.v:141703$6248 + cell $and $and$libresoc.v:142583$6232 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227277,10 +227697,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \alu_valid connect \B \$98 - connect \Y $and$libresoc.v:141703$6248_Y + connect \Y $and$libresoc.v:142583$6232_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" - cell $and $and$libresoc.v:141704$6249 + cell $and $and$libresoc.v:142584$6233 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227288,10 +227708,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \alu_valid connect \B \adr_l_q_adr - connect \Y $and$libresoc.v:141704$6249_Y + connect \Y $and$libresoc.v:142584$6233_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443" - cell $and $and$libresoc.v:141705$6250 + cell $and $and$libresoc.v:142585$6234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227299,10 +227719,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$102 connect \B \cu_busy_o - connect \Y $and$libresoc.v:141705$6250_Y + connect \Y $and$libresoc.v:142585$6234_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" - cell $and $and$libresoc.v:141706$6251 + cell $and $and$libresoc.v:142586$6235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227310,10 +227730,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \sto_l_q_sto connect \B \cu_busy_o - connect \Y $and$libresoc.v:141706$6251_Y + connect \Y $and$libresoc.v:142586$6235_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" - cell $and $and$libresoc.v:141707$6252 + cell $and $and$libresoc.v:142587$6236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227321,10 +227741,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$106 connect \B \rd_done - connect \Y $and$libresoc.v:141707$6252_Y + connect \Y $and$libresoc.v:142587$6236_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" - cell $and $and$libresoc.v:141709$6254 + cell $and $and$libresoc.v:142589$6238 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227332,10 +227752,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$108 connect \B \op_is_st - connect \Y $and$libresoc.v:141709$6254_Y + connect \Y $and$libresoc.v:142589$6238_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:447" - cell $and $and$libresoc.v:141710$6255 + cell $and $and$libresoc.v:142590$6239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227343,10 +227763,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$110 connect \B \cu_shadown_i - connect \Y $and$libresoc.v:141710$6255_Y + connect \Y $and$libresoc.v:142590$6239_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:141711$6256 + cell $and $and$libresoc.v:142591$6240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227354,10 +227774,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \rd_done connect \B \wri_l_q_wri - connect \Y $and$libresoc.v:141711$6256_Y + connect \Y $and$libresoc.v:142591$6240_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:141712$6257 + cell $and $and$libresoc.v:142592$6241 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227365,10 +227785,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$114 connect \B \cu_busy_o - connect \Y $and$libresoc.v:141712$6257_Y + connect \Y $and$libresoc.v:142592$6241_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:141713$6258 + cell $and $and$libresoc.v:142593$6242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227376,10 +227796,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$116 connect \B \lod_l_qn_lod - connect \Y $and$libresoc.v:141713$6258_Y + connect \Y $and$libresoc.v:142593$6242_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:141714$6259 + cell $and $and$libresoc.v:142594$6243 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227387,10 +227807,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$118 connect \B \op_is_ld - connect \Y $and$libresoc.v:141714$6259_Y + connect \Y $and$libresoc.v:142594$6243_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451" - cell $and $and$libresoc.v:141715$6260 + cell $and $and$libresoc.v:142595$6244 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227398,10 +227818,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$120 connect \B \cu_shadown_i - connect \Y $and$libresoc.v:141715$6260_Y + connect \Y $and$libresoc.v:142595$6244_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" - cell $and $and$libresoc.v:141716$6261 + cell $and $and$libresoc.v:142596$6245 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227409,10 +227829,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \upd_l_q_upd connect \B \cu_busy_o - connect \Y $and$libresoc.v:141716$6261_Y + connect \Y $and$libresoc.v:142596$6245_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" - cell $and $and$libresoc.v:141718$6263 + cell $and $and$libresoc.v:142598$6247 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227420,10 +227840,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$124 connect \B \$126 - connect \Y $and$libresoc.v:141718$6263_Y + connect \Y $and$libresoc.v:142598$6247_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" - cell $and $and$libresoc.v:141720$6265 + cell $and $and$libresoc.v:142600$6249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227431,10 +227851,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$128 connect \B \alu_valid - connect \Y $and$libresoc.v:141720$6265_Y + connect \Y $and$libresoc.v:142600$6249_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:455" - cell $and $and$libresoc.v:141721$6266 + cell $and $and$libresoc.v:142601$6250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227442,10 +227862,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$130 connect \B \cu_shadown_i - connect \Y $and$libresoc.v:141721$6266_Y + connect \Y $and$libresoc.v:142601$6250_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $and $and$libresoc.v:141725$6270 + cell $and $and$libresoc.v:142605$6254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227453,10 +227873,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \rst_l_q_rst connect \B \cu_busy_o - connect \Y $and$libresoc.v:141725$6270_Y + connect \Y $and$libresoc.v:142605$6254_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $and $and$libresoc.v:141726$6271 + cell $and $and$libresoc.v:142606$6255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227464,10 +227884,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$140 connect \B \cu_shadown_i - connect \Y $and$libresoc.v:141726$6271_Y + connect \Y $and$libresoc.v:142606$6255_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $and $and$libresoc.v:141731$6276 + cell $and $and$libresoc.v:142611$6260 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227475,10 +227895,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$142 connect \B \$144 - connect \Y $and$libresoc.v:141731$6276_Y + connect \Y $and$libresoc.v:142611$6260_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463" - cell $and $and$libresoc.v:141733$6278 + cell $and $and$libresoc.v:142613$6262 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227486,10 +227906,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$150 connect \B \$152 - connect \Y $and$libresoc.v:141733$6278_Y + connect \Y $and$libresoc.v:142613$6262_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" - cell $and $and$libresoc.v:141736$6281 + cell $and $and$libresoc.v:142616$6265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227497,10 +227917,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \wr_reset connect \B \$158 - connect \Y $and$libresoc.v:141736$6281_Y + connect \Y $and$libresoc.v:142616$6265_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:477" - cell $and $and$libresoc.v:141738$6283 + cell $and $and$libresoc.v:142618$6267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227508,10 +227928,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$162 connect \B \cu_wr__go_i [1] - connect \Y $and$libresoc.v:141738$6283_Y + connect \Y $and$libresoc.v:142618$6267_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:482" - cell $and $and$libresoc.v:141741$6286 + cell $and $and$libresoc.v:142621$6270 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -227519,10 +227939,10 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A { \cu_busy_o \cu_busy_o \cu_busy_o } connect \B { 1'0 \$167 \op_is_ld } - connect \Y $and$libresoc.v:141741$6286_Y + connect \Y $and$libresoc.v:142621$6270_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:489" - cell $and $and$libresoc.v:141742$6287 + cell $and $and$libresoc.v:142622$6271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227530,10 +227950,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \op_is_ld connect \B \cu_busy_o - connect \Y $and$libresoc.v:141742$6287_Y + connect \Y $and$libresoc.v:142622$6271_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:490" - cell $and $and$libresoc.v:141743$6288 + cell $and $and$libresoc.v:142623$6272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227541,10 +227961,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \op_is_st connect \B \cu_busy_o - connect \Y $and$libresoc.v:141743$6288_Y + connect \Y $and$libresoc.v:142623$6272_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:494" - cell $and $and$libresoc.v:141745$6291 + cell $and $and$libresoc.v:142625$6275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227552,10 +227972,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \alu_ok connect \B \lsd_l_q_lsd - connect \Y $and$libresoc.v:141745$6291_Y + connect \Y $and$libresoc.v:142625$6275_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:312" - cell $and $and$libresoc.v:141757$6305 + cell $and $and$libresoc.v:142637$6289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227563,10 +227983,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \op_is_ld connect \B \cu_ad__go_i - connect \Y $and$libresoc.v:141757$6305_Y + connect \Y $and$libresoc.v:142637$6289_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:313" - cell $and $and$libresoc.v:141758$6306 + cell $and $and$libresoc.v:142638$6290 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227574,10 +227994,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \op_is_st connect \B \cu_st__go_i - connect \Y $and$libresoc.v:141758$6306_Y + connect \Y $and$libresoc.v:142638$6290_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" - cell $and $and$libresoc.v:141760$6308 + cell $and $and$libresoc.v:142640$6292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227585,10 +228005,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \alu_ok connect \B \$30 - connect \Y $and$libresoc.v:141760$6308_Y + connect \Y $and$libresoc.v:142640$6292_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" - cell $and $and$libresoc.v:141762$6310 + cell $and $and$libresoc.v:142642$6294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227596,10 +228016,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$32 connect \B \$34 - connect \Y $and$libresoc.v:141762$6310_Y + connect \Y $and$libresoc.v:142642$6294_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $and $and$libresoc.v:141765$6313 + cell $and $and$libresoc.v:142645$6297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227607,10 +228027,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$39 connect \B \$41 - connect \Y $and$libresoc.v:141765$6313_Y + connect \Y $and$libresoc.v:142645$6297_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $and $and$libresoc.v:141769$6317 + cell $and $and$libresoc.v:142649$6301 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227618,10 +228038,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$47 connect \B \$49 - connect \Y $and$libresoc.v:141769$6317_Y + connect \Y $and$libresoc.v:142649$6301_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:367" - cell $and $and$libresoc.v:141772$6320 + cell $and $and$libresoc.v:142652$6304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227629,10 +228049,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \addr_ok connect \B \op_is_st - connect \Y $and$libresoc.v:141772$6320_Y + connect \Y $and$libresoc.v:142652$6304_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $and $and$libresoc.v:141781$6329 + cell $and $and$libresoc.v:142661$6313 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -227640,10 +228060,10 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:141781$6329_Y + connect \Y $and$libresoc.v:142661$6313_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $and $and$libresoc.v:141783$6331 + cell $and $and$libresoc.v:142663$6315 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -227651,10 +228071,10 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A \$76 connect \B \$78 - connect \Y $and$libresoc.v:141783$6331_Y + connect \Y $and$libresoc.v:142663$6315_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $and $and$libresoc.v:141785$6333 + cell $and $and$libresoc.v:142665$6317 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -227662,10 +228082,10 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A \$80 connect \B \$82 - connect \Y $and$libresoc.v:141785$6333_Y + connect \Y $and$libresoc.v:142665$6317_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" - cell $and $and$libresoc.v:141786$6334 + cell $and $and$libresoc.v:142666$6318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227673,10 +228093,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \src_l_q_src [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:141786$6334_Y + connect \Y $and$libresoc.v:142666$6318_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437" - cell $and $and$libresoc.v:141787$6335 + cell $and $and$libresoc.v:142667$6319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227684,10 +228104,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$86 connect \B \op_is_st - connect \Y $and$libresoc.v:141787$6335_Y + connect \Y $and$libresoc.v:142667$6319_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" - cell $and $and$libresoc.v:141792$6340 + cell $and $and$libresoc.v:142672$6324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227695,10 +228115,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$92 - connect \Y $and$libresoc.v:141792$6340_Y + connect \Y $and$libresoc.v:142672$6324_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:141717$6262 + cell $eq $eq$libresoc.v:142597$6246 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -227706,10 +228126,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:141717$6262_Y + connect \Y $eq$libresoc.v:142597$6246_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:141737$6282 + cell $eq $eq$libresoc.v:142617$6266 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -227717,10 +228137,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:141737$6282_Y + connect \Y $eq$libresoc.v:142617$6266_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:141739$6284 + cell $eq $eq$libresoc.v:142619$6268 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -227728,10 +228148,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:141739$6284_Y + connect \Y $eq$libresoc.v:142619$6268_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:511" - cell $eq $eq$libresoc.v:141750$6297 + cell $eq $eq$libresoc.v:142630$6281 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -227739,10 +228159,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__data_len connect \B 2'10 - connect \Y $eq$libresoc.v:141750$6297_Y + connect \Y $eq$libresoc.v:142630$6281_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:308" - cell $eq $eq$libresoc.v:141755$6303 + cell $eq $eq$libresoc.v:142635$6287 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227750,10 +228170,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__insn_type connect \B 7'0100110 - connect \Y $eq$libresoc.v:141755$6303_Y + connect \Y $eq$libresoc.v:142635$6287_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" - cell $eq $eq$libresoc.v:141756$6304 + cell $eq $eq$libresoc.v:142636$6288 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -227761,10 +228181,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__insn_type connect \B 7'0100101 - connect \Y $eq$libresoc.v:141756$6304_Y + connect \Y $eq$libresoc.v:142636$6288_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:141764$6312 + cell $eq $eq$libresoc.v:142644$6296 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -227772,10 +228192,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:141764$6312_Y + connect \Y $eq$libresoc.v:142644$6296_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:310" - cell $eq $eq$libresoc.v:141768$6316 + cell $eq $eq$libresoc.v:142648$6300 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -227783,114 +228203,114 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \oper_r__ldst_mode connect \B 2'01 - connect \Y $eq$libresoc.v:141768$6316_Y + connect \Y $eq$libresoc.v:142648$6300_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" - cell $pos $extend$libresoc.v:141744$6289 + cell $pos $extend$libresoc.v:142624$6273 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 96 connect \A \addr_r - connect \Y $extend$libresoc.v:141744$6289_Y + connect \Y $extend$libresoc.v:142624$6273_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $extend$libresoc.v:141746$6292 + cell $pos $extend$libresoc.v:142626$6276 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 64 connect \A \ldst_port0_ld_data_o [7:0] - connect \Y $extend$libresoc.v:141746$6292_Y + connect \Y $extend$libresoc.v:142626$6276_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $extend$libresoc.v:141751$6298 + cell $pos $extend$libresoc.v:142631$6282 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 64 connect \A \src_r2 [7:0] - connect \Y $extend$libresoc.v:141751$6298_Y + connect \Y $extend$libresoc.v:142631$6282_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $not $not$libresoc.v:141729$6274 + cell $not $not$libresoc.v:142609$6258 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$147 - connect \Y $not$libresoc.v:141729$6274_Y + connect \Y $not$libresoc.v:142609$6258_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" - cell $not $not$libresoc.v:141734$6279 + cell $not $not$libresoc.v:142614$6263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o - connect \Y $not$libresoc.v:141734$6279_Y + connect \Y $not$libresoc.v:142614$6263_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" - cell $not $not$libresoc.v:141759$6307 + cell $not $not$libresoc.v:142639$6291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_valid - connect \Y $not$libresoc.v:141759$6307_Y + connect \Y $not$libresoc.v:142639$6291_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:344" - cell $not $not$libresoc.v:141761$6309 + cell $not $not$libresoc.v:142641$6293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \rda_any - connect \Y $not$libresoc.v:141761$6309_Y + connect \Y $not$libresoc.v:142641$6293_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $not $not$libresoc.v:141763$6311 + cell $not $not$libresoc.v:142643$6295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o - connect \Y $not$libresoc.v:141763$6311_Y + connect \Y $not$libresoc.v:142643$6295_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $not $not$libresoc.v:141767$6315 + cell $not $not$libresoc.v:142647$6299 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o - connect \Y $not$libresoc.v:141767$6315_Y + connect \Y $not$libresoc.v:142647$6299_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $not $not$libresoc.v:141782$6330 + cell $not $not$libresoc.v:142662$6314 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A { \oper_r__imm_data__ok \oper_r__zero_a } - connect \Y $not$libresoc.v:141782$6330_Y + connect \Y $not$libresoc.v:142662$6314_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428" - cell $not $not$libresoc.v:141784$6332 + cell $not $not$libresoc.v:142664$6316 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:141784$6332_Y + connect \Y $not$libresoc.v:142664$6316_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" - cell $not $not$libresoc.v:141791$6339 + cell $not $not$libresoc.v:142671$6323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$93 - connect \Y $not$libresoc.v:141791$6339_Y + connect \Y $not$libresoc.v:142671$6323_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440" - cell $not $not$libresoc.v:141793$6341 + cell $not $not$libresoc.v:142673$6325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_rd__rel_o [2] - connect \Y $not$libresoc.v:141793$6341_Y + connect \Y $not$libresoc.v:142673$6325_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296" - cell $or $or$libresoc.v:141708$6253 + cell $or $or$libresoc.v:142588$6237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227898,10 +228318,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_done_o connect \B \cu_go_die_i - connect \Y $or$libresoc.v:141708$6253_Y + connect \Y $or$libresoc.v:142588$6237_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297" - cell $or $or$libresoc.v:141719$6264 + cell $or $or$libresoc.v:142599$6248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227909,10 +228329,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_go_die_i - connect \Y $or$libresoc.v:141719$6264_Y + connect \Y $or$libresoc.v:142599$6248_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" - cell $or $or$libresoc.v:141722$6267 + cell $or $or$libresoc.v:142602$6251 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227920,10 +228340,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_st__go_i connect \B \p_st_go - connect \Y $or$libresoc.v:141722$6267_Y + connect \Y $or$libresoc.v:142602$6251_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" - cell $or $or$libresoc.v:141723$6268 + cell $or $or$libresoc.v:142603$6252 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227931,10 +228351,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$134 connect \B \cu_wr__go_i [0] - connect \Y $or$libresoc.v:141723$6268_Y + connect \Y $or$libresoc.v:142603$6252_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459" - cell $or $or$libresoc.v:141724$6269 + cell $or $or$libresoc.v:142604$6253 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227942,10 +228362,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$136 connect \B \cu_wr__go_i [1] - connect \Y $or$libresoc.v:141724$6269_Y + connect \Y $or$libresoc.v:142604$6253_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $or $or$libresoc.v:141727$6272 + cell $or $or$libresoc.v:142607$6256 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227953,10 +228373,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_st__rel_o connect \B \cu_wr__rel_o [0] - connect \Y $or$libresoc.v:141727$6272_Y + connect \Y $or$libresoc.v:142607$6256_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $or $or$libresoc.v:141728$6273 + cell $or $or$libresoc.v:142608$6257 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227964,10 +228384,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$145 connect \B \cu_wr__rel_o [1] - connect \Y $or$libresoc.v:141728$6273_Y + connect \Y $or$libresoc.v:142608$6257_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298" - cell $or $or$libresoc.v:141730$6275 + cell $or $or$libresoc.v:142610$6259 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227975,10 +228395,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_go_die_i - connect \Y $or$libresoc.v:141730$6275_Y + connect \Y $or$libresoc.v:142610$6259_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:463" - cell $or $or$libresoc.v:141732$6277 + cell $or $or$libresoc.v:142612$6261 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227986,10 +228406,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \lod_l_qn_lod connect \B \op_is_st - connect \Y $or$libresoc.v:141732$6277_Y + connect \Y $or$libresoc.v:142612$6261_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:465" - cell $or $or$libresoc.v:141735$6280 + cell $or $or$libresoc.v:142615$6264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -227997,10 +228417,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$156 connect \B \op_is_ld - connect \Y $or$libresoc.v:141735$6280_Y + connect \Y $or$libresoc.v:142615$6264_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:299" - cell $or $or$libresoc.v:141740$6285 + cell $or $or$libresoc.v:142620$6269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228008,10 +228428,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_st__go_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:141740$6285_Y + connect \Y $or$libresoc.v:142620$6269_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:300" - cell $or $or$libresoc.v:141748$6295 + cell $or $or$libresoc.v:142628$6279 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -228019,10 +228439,10 @@ module \ldst0 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:141748$6295_Y + connect \Y $or$libresoc.v:142628$6279_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:301" - cell $or $or$libresoc.v:141754$6302 + cell $or $or$libresoc.v:142634$6286 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228030,10 +228450,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_ad__go_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:141754$6302_Y + connect \Y $or$libresoc.v:142634$6286_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $or $or$libresoc.v:141766$6314 + cell $or $or$libresoc.v:142646$6298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228041,10 +228461,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \wr_reset connect \B \$43 - connect \Y $or$libresoc.v:141766$6314_Y + connect \Y $or$libresoc.v:142646$6298_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:357" - cell $or $or$libresoc.v:141770$6318 + cell $or $or$libresoc.v:142650$6302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228052,10 +228472,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \wr_reset connect \B \$51 - connect \Y $or$libresoc.v:141770$6318_Y + connect \Y $or$libresoc.v:142650$6302_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:360" - cell $or $or$libresoc.v:141771$6319 + cell $or $or$libresoc.v:142651$6303 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228063,10 +228483,10 @@ module \ldst0 parameter \Y_WIDTH 2 connect \A \reset_w connect \B { \$45 \$53 } - connect \Y $or$libresoc.v:141771$6319_Y + connect \Y $or$libresoc.v:142651$6303_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:368" - cell $or $or$libresoc.v:141773$6321 + cell $or $or$libresoc.v:142653$6305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228074,10 +228494,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \reset_s connect \B \p_st_go - connect \Y $or$libresoc.v:141773$6321_Y + connect \Y $or$libresoc.v:142653$6305_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" - cell $or $or$libresoc.v:141774$6322 + cell $or $or$libresoc.v:142654$6306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228085,10 +228505,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \reset_s connect \B \p_st_go - connect \Y $or$libresoc.v:141774$6322_Y + connect \Y $or$libresoc.v:142654$6306_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:372" - cell $or $or$libresoc.v:141775$6323 + cell $or $or$libresoc.v:142655$6307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228096,10 +228516,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \$61 connect \B \ld_ok - connect \Y $or$libresoc.v:141775$6323_Y + connect \Y $or$libresoc.v:142655$6307_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295" - cell $or $or$libresoc.v:141788$6336 + cell $or $or$libresoc.v:142668$6320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228107,10 +228527,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:141788$6336_Y + connect \Y $or$libresoc.v:142668$6320_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:431" - cell $or $or$libresoc.v:141789$6337 + cell $or $or$libresoc.v:142669$6321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228118,10 +228538,10 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_rd__go_i [0] connect \B \cu_rd__go_i [1] - connect \Y $or$libresoc.v:141789$6337_Y + connect \Y $or$libresoc.v:142669$6321_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434" - cell $or $or$libresoc.v:141790$6338 + cell $or $or$libresoc.v:142670$6322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -228129,98 +228549,98 @@ module \ldst0 parameter \Y_WIDTH 1 connect \A \cu_rd__rel_o [0] connect \B \cu_rd__rel_o [1] - connect \Y $or$libresoc.v:141790$6338_Y + connect \Y $or$libresoc.v:142670$6322_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400" - cell $pos $pos$libresoc.v:141744$6290 + cell $pos $pos$libresoc.v:142624$6274 parameter \A_SIGNED 0 parameter \A_WIDTH 96 parameter \Y_WIDTH 96 - connect \A $extend$libresoc.v:141744$6289_Y - connect \Y $pos$libresoc.v:141744$6290_Y + connect \A $extend$libresoc.v:142624$6273_Y + connect \Y $pos$libresoc.v:142624$6274_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $pos$libresoc.v:141746$6293 + cell $pos $pos$libresoc.v:142626$6277 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:141746$6292_Y - connect \Y $pos$libresoc.v:141746$6293_Y + connect \A $extend$libresoc.v:142626$6276_Y + connect \Y $pos$libresoc.v:142626$6277_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $pos$libresoc.v:141747$6294 + cell $pos $pos$libresoc.v:142627$6278 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 48'000000000000000000000000000000000000000000000000 \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] } - connect \Y $pos$libresoc.v:141747$6294_Y + connect \Y $pos$libresoc.v:142627$6278_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $pos$libresoc.v:141749$6296 + cell $pos $pos$libresoc.v:142629$6280 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] \ldst_port0_ld_data_o [23:16] \ldst_port0_ld_data_o [31:24] } - connect \Y $pos$libresoc.v:141749$6296_Y + connect \Y $pos$libresoc.v:142629$6280_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $pos$libresoc.v:141751$6299 + cell $pos $pos$libresoc.v:142631$6283 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:141751$6298_Y - connect \Y $pos$libresoc.v:141751$6299_Y + connect \A $extend$libresoc.v:142631$6282_Y + connect \Y $pos$libresoc.v:142631$6283_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $pos$libresoc.v:141752$6300 + cell $pos $pos$libresoc.v:142632$6284 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 48'000000000000000000000000000000000000000000000000 \src_r2 [7:0] \src_r2 [15:8] } - connect \Y $pos$libresoc.v:141752$6300_Y + connect \Y $pos$libresoc.v:142632$6284_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:36" - cell $pos $pos$libresoc.v:141753$6301 + cell $pos $pos$libresoc.v:142633$6285 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \src_r2 [7:0] \src_r2 [15:8] \src_r2 [23:16] \src_r2 [31:24] } - connect \Y $pos$libresoc.v:141753$6301_Y + connect \Y $pos$libresoc.v:142633$6285_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:141776$6324 + cell $mux $ternary$libresoc.v:142656$6308 parameter \WIDTH 64 connect \A \ldo_r connect \B \ldd_o connect \S \ld_ok - connect \Y $ternary$libresoc.v:141776$6324_Y + connect \Y $ternary$libresoc.v:142656$6308_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:141777$6325 + cell $mux $ternary$libresoc.v:142657$6309 parameter \WIDTH 64 connect \A \ea_r connect \B \alu_o connect \S \alu_l_q_alu - connect \Y $ternary$libresoc.v:141777$6325_Y + connect \Y $ternary$libresoc.v:142657$6309_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:406" - cell $mux $ternary$libresoc.v:141778$6326 + cell $mux $ternary$libresoc.v:142658$6310 parameter \WIDTH 64 connect \A \src_r0 connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 connect \S \oper_r__zero_a - connect \Y $ternary$libresoc.v:141778$6326_Y + connect \Y $ternary$libresoc.v:142658$6310_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411" - cell $mux $ternary$libresoc.v:141779$6327 + cell $mux $ternary$libresoc.v:142659$6311 parameter \WIDTH 64 connect \A \src_r1 connect \B \oper_r__imm_data__data connect \S \oper_r__imm_data__ok - connect \Y $ternary$libresoc.v:141779$6327_Y + connect \Y $ternary$libresoc.v:142659$6311_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:141864.9-141870.4" + attribute \src "libresoc.v:142744.9-142750.4" cell \adr_l \adr_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -228229,7 +228649,7 @@ module \ldst0 connect \s_adr \adr_l_s_adr end attribute \module_not_derived 1 - attribute \src "libresoc.v:141871.15-141877.4" + attribute \src "libresoc.v:142751.15-142757.4" cell \alu_l$128 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -228238,7 +228658,7 @@ module \ldst0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:141878.9-141884.4" + attribute \src "libresoc.v:142758.9-142764.4" cell \lod_l \lod_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -228247,7 +228667,7 @@ module \ldst0 connect \s_lod \lod_l_s_lod end attribute \module_not_derived 1 - attribute \src "libresoc.v:141885.9-141891.4" + attribute \src "libresoc.v:142765.9-142771.4" cell \lsd_l \lsd_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -228256,7 +228676,7 @@ module \ldst0 connect \s_lsd \lsd_l_s_lsd end attribute \module_not_derived 1 - attribute \src "libresoc.v:141892.15-141898.4" + attribute \src "libresoc.v:142772.15-142778.4" cell \opc_l$126 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -228265,7 +228685,7 @@ module \ldst0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:141899.15-141905.4" + attribute \src "libresoc.v:142779.15-142785.4" cell \rst_l$129 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -228274,7 +228694,7 @@ module \ldst0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:141906.15-141912.4" + attribute \src "libresoc.v:142786.15-142792.4" cell \src_l$127 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -228283,7 +228703,7 @@ module \ldst0 connect \s_src \src_l_s_src end attribute \module_not_derived 1 - attribute \src "libresoc.v:141913.9-141919.4" + attribute \src "libresoc.v:142793.9-142799.4" cell \sto_l \sto_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -228292,7 +228712,7 @@ module \ldst0 connect \s_sto \sto_l_s_sto end attribute \module_not_derived 1 - attribute \src "libresoc.v:141920.9-141926.4" + attribute \src "libresoc.v:142800.9-142806.4" cell \upd_l \upd_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -228301,7 +228721,7 @@ module \ldst0 connect \s_upd \upd_l_s_upd end attribute \module_not_derived 1 - attribute \src "libresoc.v:141927.9-141933.4" + attribute \src "libresoc.v:142807.9-142813.4" cell \wri_l \wri_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -228309,547 +228729,547 @@ module \ldst0 connect \r_wri \wri_l_r_wri connect \s_wri \wri_l_s_wri end - attribute \src "libresoc.v:140953.7-140953.20" - process $proc$libresoc.v:140953$6490 + attribute \src "libresoc.v:141833.7-141833.20" + process $proc$libresoc.v:141833$6474 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:141149.7-141149.25" - process $proc$libresoc.v:141149$6491 + attribute \src "libresoc.v:142029.7-142029.25" + process $proc$libresoc.v:142029$6475 assign { } { } assign $1\adr_l_r_adr[0:0] 1'1 sync always sync init update \adr_l_r_adr $1\adr_l_r_adr[0:0] end - attribute \src "libresoc.v:141163.7-141163.20" - process $proc$libresoc.v:141163$6492 + attribute \src "libresoc.v:142043.7-142043.20" + process $proc$libresoc.v:142043$6476 assign { } { } assign $1\alu_ok[0:0] 1'0 sync always sync init update \alu_ok $1\alu_ok[0:0] end - attribute \src "libresoc.v:141209.14-141209.41" - process $proc$libresoc.v:141209$6493 + attribute \src "libresoc.v:142089.14-142089.41" + process $proc$libresoc.v:142089$6477 assign { } { } assign $1\ea_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ea_r $1\ea_r[63:0] end - attribute \src "libresoc.v:141239.14-141239.42" - process $proc$libresoc.v:141239$6494 + attribute \src "libresoc.v:142119.14-142119.42" + process $proc$libresoc.v:142119$6478 assign { } { } assign $1\ldo_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ldo_r $1\ldo_r[63:0] end - attribute \src "libresoc.v:141244.14-141244.62" - process $proc$libresoc.v:141244$6495 + attribute \src "libresoc.v:142124.14-142124.62" + process $proc$libresoc.v:142124$6479 assign { } { } assign $1\ldst_port0_addr_i[95:0] 96'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ldst_port0_addr_i $1\ldst_port0_addr_i[95:0] end - attribute \src "libresoc.v:141249.7-141249.34" - process $proc$libresoc.v:141249$6496 + attribute \src "libresoc.v:142129.7-142129.34" + process $proc$libresoc.v:142129$6480 assign { } { } assign $1\ldst_port0_addr_i_ok[0:0] 1'0 sync always sync init update \ldst_port0_addr_i_ok $1\ldst_port0_addr_i_ok[0:0] end - attribute \src "libresoc.v:141298.7-141298.25" - process $proc$libresoc.v:141298$6497 + attribute \src "libresoc.v:142178.7-142178.25" + process $proc$libresoc.v:142178$6481 assign { } { } assign $1\lsd_l_r_lsd[0:0] 1'1 sync always sync init update \lsd_l_r_lsd $1\lsd_l_r_lsd[0:0] end - attribute \src "libresoc.v:141312.7-141312.25" - process $proc$libresoc.v:141312$6498 + attribute \src "libresoc.v:142192.7-142192.25" + process $proc$libresoc.v:142192$6482 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:141316.7-141316.25" - process $proc$libresoc.v:141316$6499 + attribute \src "libresoc.v:142196.7-142196.25" + process $proc$libresoc.v:142196$6483 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:141447.7-141447.34" - process $proc$libresoc.v:141447$6500 + attribute \src "libresoc.v:142327.7-142327.34" + process $proc$libresoc.v:142327$6484 assign { } { } assign $1\oper_r__byte_reverse[0:0] 1'0 sync always sync init update \oper_r__byte_reverse $1\oper_r__byte_reverse[0:0] end - attribute \src "libresoc.v:141451.13-141451.36" - process $proc$libresoc.v:141451$6501 + attribute \src "libresoc.v:142331.13-142331.36" + process $proc$libresoc.v:142331$6485 assign { } { } assign $1\oper_r__data_len[3:0] 4'0000 sync always sync init update \oper_r__data_len $1\oper_r__data_len[3:0] end - attribute \src "libresoc.v:141470.14-141470.40" - process $proc$libresoc.v:141470$6502 + attribute \src "libresoc.v:142350.14-142350.40" + process $proc$libresoc.v:142350$6486 assign { } { } assign $1\oper_r__fn_unit[13:0] 14'00000000000000 sync always sync init update \oper_r__fn_unit $1\oper_r__fn_unit[13:0] end - attribute \src "libresoc.v:141474.14-141474.59" - process $proc$libresoc.v:141474$6503 + attribute \src "libresoc.v:142354.14-142354.59" + process $proc$libresoc.v:142354$6487 assign { } { } assign $1\oper_r__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \oper_r__imm_data__data $1\oper_r__imm_data__data[63:0] end - attribute \src "libresoc.v:141478.7-141478.34" - process $proc$libresoc.v:141478$6504 + attribute \src "libresoc.v:142358.7-142358.34" + process $proc$libresoc.v:142358$6488 assign { } { } assign $1\oper_r__imm_data__ok[0:0] 1'0 sync always sync init update \oper_r__imm_data__ok $1\oper_r__imm_data__ok[0:0] end - attribute \src "libresoc.v:141482.14-141482.34" - process $proc$libresoc.v:141482$6505 + attribute \src "libresoc.v:142362.14-142362.34" + process $proc$libresoc.v:142362$6489 assign { } { } assign $1\oper_r__insn[31:0] 0 sync always sync init update \oper_r__insn $1\oper_r__insn[31:0] end - attribute \src "libresoc.v:141561.13-141561.38" - process $proc$libresoc.v:141561$6506 + attribute \src "libresoc.v:142441.13-142441.38" + process $proc$libresoc.v:142441$6490 assign { } { } assign $1\oper_r__insn_type[6:0] 7'0000000 sync always sync init update \oper_r__insn_type $1\oper_r__insn_type[6:0] end - attribute \src "libresoc.v:141565.7-141565.30" - process $proc$libresoc.v:141565$6507 + attribute \src "libresoc.v:142445.7-142445.30" + process $proc$libresoc.v:142445$6491 assign { } { } assign $1\oper_r__is_32bit[0:0] 1'0 sync always sync init update \oper_r__is_32bit $1\oper_r__is_32bit[0:0] end - attribute \src "libresoc.v:141569.7-141569.31" - process $proc$libresoc.v:141569$6508 + attribute \src "libresoc.v:142449.7-142449.31" + process $proc$libresoc.v:142449$6492 assign { } { } assign $1\oper_r__is_signed[0:0] 1'0 sync always sync init update \oper_r__is_signed $1\oper_r__is_signed[0:0] end - attribute \src "libresoc.v:141578.13-141578.37" - process $proc$libresoc.v:141578$6509 + attribute \src "libresoc.v:142458.13-142458.37" + process $proc$libresoc.v:142458$6493 assign { } { } assign $1\oper_r__ldst_mode[1:0] 2'00 sync always sync init update \oper_r__ldst_mode $1\oper_r__ldst_mode[1:0] end - attribute \src "libresoc.v:141582.7-141582.28" - process $proc$libresoc.v:141582$6510 + attribute \src "libresoc.v:142462.7-142462.28" + process $proc$libresoc.v:142462$6494 assign { } { } assign $1\oper_r__oe__oe[0:0] 1'0 sync always sync init update \oper_r__oe__oe $1\oper_r__oe__oe[0:0] end - attribute \src "libresoc.v:141586.7-141586.28" - process $proc$libresoc.v:141586$6511 + attribute \src "libresoc.v:142466.7-142466.28" + process $proc$libresoc.v:142466$6495 assign { } { } assign $1\oper_r__oe__ok[0:0] 1'0 sync always sync init update \oper_r__oe__ok $1\oper_r__oe__ok[0:0] end - attribute \src "libresoc.v:141590.7-141590.28" - process $proc$libresoc.v:141590$6512 + attribute \src "libresoc.v:142470.7-142470.28" + process $proc$libresoc.v:142470$6496 assign { } { } assign $1\oper_r__rc__ok[0:0] 1'0 sync always sync init update \oper_r__rc__ok $1\oper_r__rc__ok[0:0] end - attribute \src "libresoc.v:141594.7-141594.28" - process $proc$libresoc.v:141594$6513 + attribute \src "libresoc.v:142474.7-142474.28" + process $proc$libresoc.v:142474$6497 assign { } { } assign $1\oper_r__rc__rc[0:0] 1'0 sync always sync init update \oper_r__rc__rc $1\oper_r__rc__rc[0:0] end - attribute \src "libresoc.v:141598.7-141598.33" - process $proc$libresoc.v:141598$6514 + attribute \src "libresoc.v:142478.7-142478.33" + process $proc$libresoc.v:142478$6498 assign { } { } assign $1\oper_r__sign_extend[0:0] 1'0 sync always sync init update \oper_r__sign_extend $1\oper_r__sign_extend[0:0] end - attribute \src "libresoc.v:141602.7-141602.28" - process $proc$libresoc.v:141602$6515 + attribute \src "libresoc.v:142482.7-142482.28" + process $proc$libresoc.v:142482$6499 assign { } { } assign $1\oper_r__zero_a[0:0] 1'0 sync always sync init update \oper_r__zero_a $1\oper_r__zero_a[0:0] end - attribute \src "libresoc.v:141606.7-141606.21" - process $proc$libresoc.v:141606$6516 + attribute \src "libresoc.v:142486.7-142486.21" + process $proc$libresoc.v:142486$6500 assign { } { } assign $1\p_st_go[0:0] 1'0 sync always sync init update \p_st_go $1\p_st_go[0:0] end - attribute \src "libresoc.v:141648.13-141648.31" - process $proc$libresoc.v:141648$6517 + attribute \src "libresoc.v:142528.13-142528.31" + process $proc$libresoc.v:142528$6501 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end - attribute \src "libresoc.v:141652.13-141652.31" - process $proc$libresoc.v:141652$6518 + attribute \src "libresoc.v:142532.13-142532.31" + process $proc$libresoc.v:142532$6502 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end - attribute \src "libresoc.v:141656.14-141656.43" - process $proc$libresoc.v:141656$6519 + attribute \src "libresoc.v:142536.14-142536.43" + process $proc$libresoc.v:142536$6503 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:141660.14-141660.43" - process $proc$libresoc.v:141660$6520 + attribute \src "libresoc.v:142540.14-142540.43" + process $proc$libresoc.v:142540$6504 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:141664.14-141664.43" - process $proc$libresoc.v:141664$6521 + attribute \src "libresoc.v:142544.14-142544.43" + process $proc$libresoc.v:142544$6505 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end - attribute \src "libresoc.v:141674.7-141674.25" - process $proc$libresoc.v:141674$6522 + attribute \src "libresoc.v:142554.7-142554.25" + process $proc$libresoc.v:142554$6506 assign { } { } assign $1\sto_l_r_sto[0:0] 1'1 sync always sync init update \sto_l_r_sto $1\sto_l_r_sto[0:0] end - attribute \src "libresoc.v:141684.7-141684.25" - process $proc$libresoc.v:141684$6523 + attribute \src "libresoc.v:142564.7-142564.25" + process $proc$libresoc.v:142564$6507 assign { } { } assign $1\upd_l_r_upd[0:0] 1'1 sync always sync init update \upd_l_r_upd $1\upd_l_r_upd[0:0] end - attribute \src "libresoc.v:141688.7-141688.25" - process $proc$libresoc.v:141688$6524 + attribute \src "libresoc.v:142568.7-142568.25" + process $proc$libresoc.v:142568$6508 assign { } { } assign $1\upd_l_s_upd[0:0] 1'0 sync always sync init update \upd_l_s_upd $1\upd_l_s_upd[0:0] end - attribute \src "libresoc.v:141698.7-141698.25" - process $proc$libresoc.v:141698$6525 + attribute \src "libresoc.v:142578.7-142578.25" + process $proc$libresoc.v:142578$6509 assign { } { } assign $1\wri_l_r_wri[0:0] 1'1 sync always sync init update \wri_l_r_wri $1\wri_l_r_wri[0:0] end - attribute \src "libresoc.v:141794.3-141795.57" - process $proc$libresoc.v:141794$6342 + attribute \src "libresoc.v:142674.3-142675.57" + process $proc$libresoc.v:142674$6326 assign { } { } assign $0\ldst_port0_addr_i_ok[0:0] \ldst_port0_addr_i_ok$next sync posedge \coresync_clk update \ldst_port0_addr_i_ok $0\ldst_port0_addr_i_ok[0:0] end - attribute \src "libresoc.v:141796.3-141797.33" - process $proc$libresoc.v:141796$6343 + attribute \src "libresoc.v:142676.3-142677.33" + process $proc$libresoc.v:142676$6327 assign { } { } assign $0\ldst_port0_addr_i[95:0] \$175 sync posedge \coresync_clk update \ldst_port0_addr_i $0\ldst_port0_addr_i[95:0] end - attribute \src "libresoc.v:141798.3-141799.21" - process $proc$libresoc.v:141798$6344 + attribute \src "libresoc.v:142678.3-142679.21" + process $proc$libresoc.v:142678$6328 assign { } { } assign $0\alu_ok[0:0] \$96 sync posedge \coresync_clk update \alu_ok $0\alu_ok[0:0] end - attribute \src "libresoc.v:141800.3-141801.25" - process $proc$libresoc.v:141800$6345 + attribute \src "libresoc.v:142680.3-142681.25" + process $proc$libresoc.v:142680$6329 assign { } { } assign $0\ea_r[63:0] \ea_r$next sync posedge \coresync_clk update \ea_r $0\ea_r[63:0] end - attribute \src "libresoc.v:141802.3-141803.29" - process $proc$libresoc.v:141802$6346 + attribute \src "libresoc.v:142682.3-142683.29" + process $proc$libresoc.v:142682$6330 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end - attribute \src "libresoc.v:141804.3-141805.29" - process $proc$libresoc.v:141804$6347 + attribute \src "libresoc.v:142684.3-142685.29" + process $proc$libresoc.v:142684$6331 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:141806.3-141807.29" - process $proc$libresoc.v:141806$6348 + attribute \src "libresoc.v:142686.3-142687.29" + process $proc$libresoc.v:142686$6332 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:141808.3-141809.27" - process $proc$libresoc.v:141808$6349 + attribute \src "libresoc.v:142688.3-142689.27" + process $proc$libresoc.v:142688$6333 assign { } { } assign $0\ldo_r[63:0] \ldo_r$next sync posedge \coresync_clk update \ldo_r $0\ldo_r[63:0] end - attribute \src "libresoc.v:141810.3-141811.51" - process $proc$libresoc.v:141810$6350 + attribute \src "libresoc.v:142690.3-142691.51" + process $proc$libresoc.v:142690$6334 assign { } { } assign $0\oper_r__insn_type[6:0] \oper_r__insn_type$next sync posedge \coresync_clk update \oper_r__insn_type $0\oper_r__insn_type[6:0] end - attribute \src "libresoc.v:141812.3-141813.47" - process $proc$libresoc.v:141812$6351 + attribute \src "libresoc.v:142692.3-142693.47" + process $proc$libresoc.v:142692$6335 assign { } { } assign $0\oper_r__fn_unit[13:0] \oper_r__fn_unit$next sync posedge \coresync_clk update \oper_r__fn_unit $0\oper_r__fn_unit[13:0] end - attribute \src "libresoc.v:141814.3-141815.61" - process $proc$libresoc.v:141814$6352 + attribute \src "libresoc.v:142694.3-142695.61" + process $proc$libresoc.v:142694$6336 assign { } { } assign $0\oper_r__imm_data__data[63:0] \oper_r__imm_data__data$next sync posedge \coresync_clk update \oper_r__imm_data__data $0\oper_r__imm_data__data[63:0] end - attribute \src "libresoc.v:141816.3-141817.57" - process $proc$libresoc.v:141816$6353 + attribute \src "libresoc.v:142696.3-142697.57" + process $proc$libresoc.v:142696$6337 assign { } { } assign $0\oper_r__imm_data__ok[0:0] \oper_r__imm_data__ok$next sync posedge \coresync_clk update \oper_r__imm_data__ok $0\oper_r__imm_data__ok[0:0] end - attribute \src "libresoc.v:141818.3-141819.45" - process $proc$libresoc.v:141818$6354 + attribute \src "libresoc.v:142698.3-142699.45" + process $proc$libresoc.v:142698$6338 assign { } { } assign $0\oper_r__zero_a[0:0] \oper_r__zero_a$next sync posedge \coresync_clk update \oper_r__zero_a $0\oper_r__zero_a[0:0] end - attribute \src "libresoc.v:141820.3-141821.45" - process $proc$libresoc.v:141820$6355 + attribute \src "libresoc.v:142700.3-142701.45" + process $proc$libresoc.v:142700$6339 assign { } { } assign $0\oper_r__rc__rc[0:0] \oper_r__rc__rc$next sync posedge \coresync_clk update \oper_r__rc__rc $0\oper_r__rc__rc[0:0] end - attribute \src "libresoc.v:141822.3-141823.45" - process $proc$libresoc.v:141822$6356 + attribute \src "libresoc.v:142702.3-142703.45" + process $proc$libresoc.v:142702$6340 assign { } { } assign $0\oper_r__rc__ok[0:0] \oper_r__rc__ok$next sync posedge \coresync_clk update \oper_r__rc__ok $0\oper_r__rc__ok[0:0] end - attribute \src "libresoc.v:141824.3-141825.45" - process $proc$libresoc.v:141824$6357 + attribute \src "libresoc.v:142704.3-142705.45" + process $proc$libresoc.v:142704$6341 assign { } { } assign $0\oper_r__oe__oe[0:0] \oper_r__oe__oe$next sync posedge \coresync_clk update \oper_r__oe__oe $0\oper_r__oe__oe[0:0] end - attribute \src "libresoc.v:141826.3-141827.45" - process $proc$libresoc.v:141826$6358 + attribute \src "libresoc.v:142706.3-142707.45" + process $proc$libresoc.v:142706$6342 assign { } { } assign $0\oper_r__oe__ok[0:0] \oper_r__oe__ok$next sync posedge \coresync_clk update \oper_r__oe__ok $0\oper_r__oe__ok[0:0] end - attribute \src "libresoc.v:141828.3-141829.49" - process $proc$libresoc.v:141828$6359 + attribute \src "libresoc.v:142708.3-142709.49" + process $proc$libresoc.v:142708$6343 assign { } { } assign $0\oper_r__is_32bit[0:0] \oper_r__is_32bit$next sync posedge \coresync_clk update \oper_r__is_32bit $0\oper_r__is_32bit[0:0] end - attribute \src "libresoc.v:141830.3-141831.51" - process $proc$libresoc.v:141830$6360 + attribute \src "libresoc.v:142710.3-142711.51" + process $proc$libresoc.v:142710$6344 assign { } { } assign $0\oper_r__is_signed[0:0] \oper_r__is_signed$next sync posedge \coresync_clk update \oper_r__is_signed $0\oper_r__is_signed[0:0] end - attribute \src "libresoc.v:141832.3-141833.49" - process $proc$libresoc.v:141832$6361 + attribute \src "libresoc.v:142712.3-142713.49" + process $proc$libresoc.v:142712$6345 assign { } { } assign $0\oper_r__data_len[3:0] \oper_r__data_len$next sync posedge \coresync_clk update \oper_r__data_len $0\oper_r__data_len[3:0] end - attribute \src "libresoc.v:141834.3-141835.57" - process $proc$libresoc.v:141834$6362 + attribute \src "libresoc.v:142714.3-142715.57" + process $proc$libresoc.v:142714$6346 assign { } { } assign $0\oper_r__byte_reverse[0:0] \oper_r__byte_reverse$next sync posedge \coresync_clk update \oper_r__byte_reverse $0\oper_r__byte_reverse[0:0] end - attribute \src "libresoc.v:141836.3-141837.55" - process $proc$libresoc.v:141836$6363 + attribute \src "libresoc.v:142716.3-142717.55" + process $proc$libresoc.v:142716$6347 assign { } { } assign $0\oper_r__sign_extend[0:0] \oper_r__sign_extend$next sync posedge \coresync_clk update \oper_r__sign_extend $0\oper_r__sign_extend[0:0] end - attribute \src "libresoc.v:141838.3-141839.51" - process $proc$libresoc.v:141838$6364 + attribute \src "libresoc.v:142718.3-142719.51" + process $proc$libresoc.v:142718$6348 assign { } { } assign $0\oper_r__ldst_mode[1:0] \oper_r__ldst_mode$next sync posedge \coresync_clk update \oper_r__ldst_mode $0\oper_r__ldst_mode[1:0] end - attribute \src "libresoc.v:141840.3-141841.41" - process $proc$libresoc.v:141840$6365 + attribute \src "libresoc.v:142720.3-142721.41" + process $proc$libresoc.v:142720$6349 assign { } { } assign $0\oper_r__insn[31:0] \oper_r__insn$next sync posedge \coresync_clk update \oper_r__insn $0\oper_r__insn[31:0] end - attribute \src "libresoc.v:141842.3-141843.39" - process $proc$libresoc.v:141842$6366 + attribute \src "libresoc.v:142722.3-142723.39" + process $proc$libresoc.v:142722$6350 assign { } { } assign $0\lsd_l_r_lsd[0:0] \lsd_l_r_lsd$next sync posedge \coresync_clk update \lsd_l_r_lsd $0\lsd_l_r_lsd[0:0] end - attribute \src "libresoc.v:141844.3-141845.39" - process $proc$libresoc.v:141844$6367 + attribute \src "libresoc.v:142724.3-142725.39" + process $proc$libresoc.v:142724$6351 assign { } { } assign $0\sto_l_r_sto[0:0] \sto_l_r_sto$next sync posedge \coresync_clk update \sto_l_r_sto $0\sto_l_r_sto[0:0] end - attribute \src "libresoc.v:141846.3-141847.39" - process $proc$libresoc.v:141846$6368 + attribute \src "libresoc.v:142726.3-142727.39" + process $proc$libresoc.v:142726$6352 assign { } { } assign $0\upd_l_r_upd[0:0] \upd_l_r_upd$next sync posedge \coresync_clk update \upd_l_r_upd $0\upd_l_r_upd[0:0] end - attribute \src "libresoc.v:141848.3-141849.39" - process $proc$libresoc.v:141848$6369 + attribute \src "libresoc.v:142728.3-142729.39" + process $proc$libresoc.v:142728$6353 assign { } { } assign $0\upd_l_s_upd[0:0] \upd_l_s_upd$next sync posedge \coresync_clk update \upd_l_s_upd $0\upd_l_s_upd[0:0] end - attribute \src "libresoc.v:141850.3-141851.39" - process $proc$libresoc.v:141850$6370 + attribute \src "libresoc.v:142730.3-142731.39" + process $proc$libresoc.v:142730$6354 assign { } { } assign $0\wri_l_r_wri[0:0] \wri_l_r_wri$next sync posedge \coresync_clk update \wri_l_r_wri $0\wri_l_r_wri[0:0] end - attribute \src "libresoc.v:141852.3-141853.39" - process $proc$libresoc.v:141852$6371 + attribute \src "libresoc.v:142732.3-142733.39" + process $proc$libresoc.v:142732$6355 assign { } { } assign $0\adr_l_r_adr[0:0] \adr_l_r_adr$next sync posedge \coresync_clk update \adr_l_r_adr $0\adr_l_r_adr[0:0] end - attribute \src "libresoc.v:141854.3-141855.39" - process $proc$libresoc.v:141854$6372 + attribute \src "libresoc.v:142734.3-142735.39" + process $proc$libresoc.v:142734$6356 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "libresoc.v:141856.3-141857.39" - process $proc$libresoc.v:141856$6373 + attribute \src "libresoc.v:142736.3-142737.39" + process $proc$libresoc.v:142736$6357 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:141858.3-141859.39" - process $proc$libresoc.v:141858$6374 + attribute \src "libresoc.v:142738.3-142739.39" + process $proc$libresoc.v:142738$6358 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:141860.3-141861.39" - process $proc$libresoc.v:141860$6375 + attribute \src "libresoc.v:142740.3-142741.39" + process $proc$libresoc.v:142740$6359 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:141862.3-141863.28" - process $proc$libresoc.v:141862$6376 + attribute \src "libresoc.v:142742.3-142743.28" + process $proc$libresoc.v:142742$6360 assign { } { } assign $0\p_st_go[0:0] \cu_st__go_i sync posedge \coresync_clk update \p_st_go $0\p_st_go[0:0] end - attribute \src "libresoc.v:141934.3-141942.6" - process $proc$libresoc.v:141934$6377 + attribute \src "libresoc.v:142814.3-142822.6" + process $proc$libresoc.v:142814$6361 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$6378 $1\opc_l_s_opc$next[0:0]$6379 - attribute \src "libresoc.v:141935.5-141935.29" + assign $0\opc_l_s_opc$next[0:0]$6362 $1\opc_l_s_opc$next[0:0]$6363 + attribute \src "libresoc.v:142815.5-142815.29" switch \initial - attribute \src "libresoc.v:141935.9-141935.17" + attribute \src "libresoc.v:142815.9-142815.17" case 1'1 case end @@ -228858,21 +229278,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$6379 1'0 + assign $1\opc_l_s_opc$next[0:0]$6363 1'0 case - assign $1\opc_l_s_opc$next[0:0]$6379 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$6363 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6378 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6362 end - attribute \src "libresoc.v:141943.3-141951.6" - process $proc$libresoc.v:141943$6380 + attribute \src "libresoc.v:142823.3-142831.6" + process $proc$libresoc.v:142823$6364 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$6381 $1\opc_l_r_opc$next[0:0]$6382 - attribute \src "libresoc.v:141944.5-141944.29" + assign $0\opc_l_r_opc$next[0:0]$6365 $1\opc_l_r_opc$next[0:0]$6366 + attribute \src "libresoc.v:142824.5-142824.29" switch \initial - attribute \src "libresoc.v:141944.9-141944.17" + attribute \src "libresoc.v:142824.9-142824.17" case 1'1 case end @@ -228881,21 +229301,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$6382 1'1 + assign $1\opc_l_r_opc$next[0:0]$6366 1'1 case - assign $1\opc_l_r_opc$next[0:0]$6382 \reset_o + assign $1\opc_l_r_opc$next[0:0]$6366 \reset_o end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6381 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6365 end - attribute \src "libresoc.v:141952.3-141960.6" - process $proc$libresoc.v:141952$6383 + attribute \src "libresoc.v:142832.3-142840.6" + process $proc$libresoc.v:142832$6367 assign { } { } assign { } { } - assign $0\src_l_s_src$next[2:0]$6384 $1\src_l_s_src$next[2:0]$6385 - attribute \src "libresoc.v:141953.5-141953.29" + assign $0\src_l_s_src$next[2:0]$6368 $1\src_l_s_src$next[2:0]$6369 + attribute \src "libresoc.v:142833.5-142833.29" switch \initial - attribute \src "libresoc.v:141953.9-141953.17" + attribute \src "libresoc.v:142833.9-142833.17" case 1'1 case end @@ -228904,21 +229324,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[2:0]$6385 3'000 + assign $1\src_l_s_src$next[2:0]$6369 3'000 case - assign $1\src_l_s_src$next[2:0]$6385 { \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[2:0]$6369 { \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6384 + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6368 end - attribute \src "libresoc.v:141961.3-141969.6" - process $proc$libresoc.v:141961$6386 + attribute \src "libresoc.v:142841.3-142849.6" + process $proc$libresoc.v:142841$6370 assign { } { } assign { } { } - assign $0\src_l_r_src$next[2:0]$6387 $1\src_l_r_src$next[2:0]$6388 - attribute \src "libresoc.v:141962.5-141962.29" + assign $0\src_l_r_src$next[2:0]$6371 $1\src_l_r_src$next[2:0]$6372 + attribute \src "libresoc.v:142842.5-142842.29" switch \initial - attribute \src "libresoc.v:141962.9-141962.17" + attribute \src "libresoc.v:142842.9-142842.17" case 1'1 case end @@ -228927,21 +229347,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[2:0]$6388 3'111 + assign $1\src_l_r_src$next[2:0]$6372 3'111 case - assign $1\src_l_r_src$next[2:0]$6388 \reset_r + assign $1\src_l_r_src$next[2:0]$6372 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6387 + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6371 end - attribute \src "libresoc.v:141970.3-141978.6" - process $proc$libresoc.v:141970$6389 + attribute \src "libresoc.v:142850.3-142858.6" + process $proc$libresoc.v:142850$6373 assign { } { } assign { } { } - assign $0\adr_l_r_adr$next[0:0]$6390 $1\adr_l_r_adr$next[0:0]$6391 - attribute \src "libresoc.v:141971.5-141971.29" + assign $0\adr_l_r_adr$next[0:0]$6374 $1\adr_l_r_adr$next[0:0]$6375 + attribute \src "libresoc.v:142851.5-142851.29" switch \initial - attribute \src "libresoc.v:141971.9-141971.17" + attribute \src "libresoc.v:142851.9-142851.17" case 1'1 case end @@ -228950,21 +229370,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\adr_l_r_adr$next[0:0]$6391 1'1 + assign $1\adr_l_r_adr$next[0:0]$6375 1'1 case - assign $1\adr_l_r_adr$next[0:0]$6391 \reset_a + assign $1\adr_l_r_adr$next[0:0]$6375 \reset_a end sync always - update \adr_l_r_adr$next $0\adr_l_r_adr$next[0:0]$6390 + update \adr_l_r_adr$next $0\adr_l_r_adr$next[0:0]$6374 end - attribute \src "libresoc.v:141979.3-141987.6" - process $proc$libresoc.v:141979$6392 + attribute \src "libresoc.v:142859.3-142867.6" + process $proc$libresoc.v:142859$6376 assign { } { } assign { } { } - assign $0\wri_l_r_wri$next[0:0]$6393 $1\wri_l_r_wri$next[0:0]$6394 - attribute \src "libresoc.v:141980.5-141980.29" + assign $0\wri_l_r_wri$next[0:0]$6377 $1\wri_l_r_wri$next[0:0]$6378 + attribute \src "libresoc.v:142860.5-142860.29" switch \initial - attribute \src "libresoc.v:141980.9-141980.17" + attribute \src "libresoc.v:142860.9-142860.17" case 1'1 case end @@ -228973,21 +229393,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\wri_l_r_wri$next[0:0]$6394 1'1 + assign $1\wri_l_r_wri$next[0:0]$6378 1'1 case - assign $1\wri_l_r_wri$next[0:0]$6394 \$38 [0] + assign $1\wri_l_r_wri$next[0:0]$6378 \$38 [0] end sync always - update \wri_l_r_wri$next $0\wri_l_r_wri$next[0:0]$6393 + update \wri_l_r_wri$next $0\wri_l_r_wri$next[0:0]$6377 end - attribute \src "libresoc.v:141988.3-141996.6" - process $proc$libresoc.v:141988$6395 + attribute \src "libresoc.v:142868.3-142876.6" + process $proc$libresoc.v:142868$6379 assign { } { } assign { } { } - assign $0\upd_l_s_upd$next[0:0]$6396 $1\upd_l_s_upd$next[0:0]$6397 - attribute \src "libresoc.v:141989.5-141989.29" + assign $0\upd_l_s_upd$next[0:0]$6380 $1\upd_l_s_upd$next[0:0]$6381 + attribute \src "libresoc.v:142869.5-142869.29" switch \initial - attribute \src "libresoc.v:141989.9-141989.17" + attribute \src "libresoc.v:142869.9-142869.17" case 1'1 case end @@ -228996,21 +229416,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\upd_l_s_upd$next[0:0]$6397 1'0 + assign $1\upd_l_s_upd$next[0:0]$6381 1'0 case - assign $1\upd_l_s_upd$next[0:0]$6397 \reset_i + assign $1\upd_l_s_upd$next[0:0]$6381 \reset_i end sync always - update \upd_l_s_upd$next $0\upd_l_s_upd$next[0:0]$6396 + update \upd_l_s_upd$next $0\upd_l_s_upd$next[0:0]$6380 end - attribute \src "libresoc.v:141997.3-142005.6" - process $proc$libresoc.v:141997$6398 + attribute \src "libresoc.v:142877.3-142885.6" + process $proc$libresoc.v:142877$6382 assign { } { } assign { } { } - assign $0\upd_l_r_upd$next[0:0]$6399 $1\upd_l_r_upd$next[0:0]$6400 - attribute \src "libresoc.v:141998.5-141998.29" + assign $0\upd_l_r_upd$next[0:0]$6383 $1\upd_l_r_upd$next[0:0]$6384 + attribute \src "libresoc.v:142878.5-142878.29" switch \initial - attribute \src "libresoc.v:141998.9-141998.17" + attribute \src "libresoc.v:142878.9-142878.17" case 1'1 case end @@ -229019,21 +229439,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\upd_l_r_upd$next[0:0]$6400 1'1 + assign $1\upd_l_r_upd$next[0:0]$6384 1'1 case - assign $1\upd_l_r_upd$next[0:0]$6400 \reset_u + assign $1\upd_l_r_upd$next[0:0]$6384 \reset_u end sync always - update \upd_l_r_upd$next $0\upd_l_r_upd$next[0:0]$6399 + update \upd_l_r_upd$next $0\upd_l_r_upd$next[0:0]$6383 end - attribute \src "libresoc.v:142006.3-142014.6" - process $proc$libresoc.v:142006$6401 + attribute \src "libresoc.v:142886.3-142894.6" + process $proc$libresoc.v:142886$6385 assign { } { } assign { } { } - assign $0\sto_l_r_sto$next[0:0]$6402 $1\sto_l_r_sto$next[0:0]$6403 - attribute \src "libresoc.v:142007.5-142007.29" + assign $0\sto_l_r_sto$next[0:0]$6386 $1\sto_l_r_sto$next[0:0]$6387 + attribute \src "libresoc.v:142887.5-142887.29" switch \initial - attribute \src "libresoc.v:142007.9-142007.17" + attribute \src "libresoc.v:142887.9-142887.17" case 1'1 case end @@ -229042,21 +229462,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\sto_l_r_sto$next[0:0]$6403 1'1 + assign $1\sto_l_r_sto$next[0:0]$6387 1'1 case - assign $1\sto_l_r_sto$next[0:0]$6403 \$59 + assign $1\sto_l_r_sto$next[0:0]$6387 \$59 end sync always - update \sto_l_r_sto$next $0\sto_l_r_sto$next[0:0]$6402 + update \sto_l_r_sto$next $0\sto_l_r_sto$next[0:0]$6386 end - attribute \src "libresoc.v:142015.3-142023.6" - process $proc$libresoc.v:142015$6404 + attribute \src "libresoc.v:142895.3-142903.6" + process $proc$libresoc.v:142895$6388 assign { } { } assign { } { } - assign $0\lsd_l_r_lsd$next[0:0]$6405 $1\lsd_l_r_lsd$next[0:0]$6406 - attribute \src "libresoc.v:142016.5-142016.29" + assign $0\lsd_l_r_lsd$next[0:0]$6389 $1\lsd_l_r_lsd$next[0:0]$6390 + attribute \src "libresoc.v:142896.5-142896.29" switch \initial - attribute \src "libresoc.v:142016.9-142016.17" + attribute \src "libresoc.v:142896.9-142896.17" case 1'1 case end @@ -229065,15 +229485,15 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\lsd_l_r_lsd$next[0:0]$6406 1'1 + assign $1\lsd_l_r_lsd$next[0:0]$6390 1'1 case - assign $1\lsd_l_r_lsd$next[0:0]$6406 \$63 + assign $1\lsd_l_r_lsd$next[0:0]$6390 \$63 end sync always - update \lsd_l_r_lsd$next $0\lsd_l_r_lsd$next[0:0]$6405 + update \lsd_l_r_lsd$next $0\lsd_l_r_lsd$next[0:0]$6389 end - attribute \src "libresoc.v:142024.3-142066.6" - process $proc$libresoc.v:142024$6407 + attribute \src "libresoc.v:142904.3-142946.6" + process $proc$libresoc.v:142904$6391 assign { } { } assign { } { } assign { } { } @@ -229122,31 +229542,31 @@ module \ldst0 assign { } { } assign { } { } assign { } { } - assign $0\oper_r__byte_reverse$next[0:0]$6408 $2\oper_r__byte_reverse$next[0:0]$6440 - assign $0\oper_r__data_len$next[3:0]$6409 $2\oper_r__data_len$next[3:0]$6441 - assign $0\oper_r__fn_unit$next[13:0]$6410 $2\oper_r__fn_unit$next[13:0]$6442 + assign $0\oper_r__byte_reverse$next[0:0]$6392 $2\oper_r__byte_reverse$next[0:0]$6424 + assign $0\oper_r__data_len$next[3:0]$6393 $2\oper_r__data_len$next[3:0]$6425 + assign $0\oper_r__fn_unit$next[13:0]$6394 $2\oper_r__fn_unit$next[13:0]$6426 assign { } { } assign { } { } - assign $0\oper_r__insn$next[31:0]$6413 $2\oper_r__insn$next[31:0]$6445 - assign $0\oper_r__insn_type$next[6:0]$6414 $2\oper_r__insn_type$next[6:0]$6446 - assign $0\oper_r__is_32bit$next[0:0]$6415 $2\oper_r__is_32bit$next[0:0]$6447 - assign $0\oper_r__is_signed$next[0:0]$6416 $2\oper_r__is_signed$next[0:0]$6448 - assign $0\oper_r__ldst_mode$next[1:0]$6417 $2\oper_r__ldst_mode$next[1:0]$6449 + assign $0\oper_r__insn$next[31:0]$6397 $2\oper_r__insn$next[31:0]$6429 + assign $0\oper_r__insn_type$next[6:0]$6398 $2\oper_r__insn_type$next[6:0]$6430 + assign $0\oper_r__is_32bit$next[0:0]$6399 $2\oper_r__is_32bit$next[0:0]$6431 + assign $0\oper_r__is_signed$next[0:0]$6400 $2\oper_r__is_signed$next[0:0]$6432 + assign $0\oper_r__ldst_mode$next[1:0]$6401 $2\oper_r__ldst_mode$next[1:0]$6433 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\oper_r__sign_extend$next[0:0]$6422 $2\oper_r__sign_extend$next[0:0]$6454 - assign $0\oper_r__zero_a$next[0:0]$6423 $2\oper_r__zero_a$next[0:0]$6455 - assign $0\oper_r__imm_data__data$next[63:0]$6411 $3\oper_r__imm_data__data$next[63:0]$6456 - assign $0\oper_r__imm_data__ok$next[0:0]$6412 $3\oper_r__imm_data__ok$next[0:0]$6457 - assign $0\oper_r__oe__oe$next[0:0]$6418 $3\oper_r__oe__oe$next[0:0]$6458 - assign $0\oper_r__oe__ok$next[0:0]$6419 $3\oper_r__oe__ok$next[0:0]$6459 - assign $0\oper_r__rc__ok$next[0:0]$6420 $3\oper_r__rc__ok$next[0:0]$6460 - assign $0\oper_r__rc__rc$next[0:0]$6421 $3\oper_r__rc__rc$next[0:0]$6461 - attribute \src "libresoc.v:142025.5-142025.29" + assign $0\oper_r__sign_extend$next[0:0]$6406 $2\oper_r__sign_extend$next[0:0]$6438 + assign $0\oper_r__zero_a$next[0:0]$6407 $2\oper_r__zero_a$next[0:0]$6439 + assign $0\oper_r__imm_data__data$next[63:0]$6395 $3\oper_r__imm_data__data$next[63:0]$6440 + assign $0\oper_r__imm_data__ok$next[0:0]$6396 $3\oper_r__imm_data__ok$next[0:0]$6441 + assign $0\oper_r__oe__oe$next[0:0]$6402 $3\oper_r__oe__oe$next[0:0]$6442 + assign $0\oper_r__oe__ok$next[0:0]$6403 $3\oper_r__oe__ok$next[0:0]$6443 + assign $0\oper_r__rc__ok$next[0:0]$6404 $3\oper_r__rc__ok$next[0:0]$6444 + assign $0\oper_r__rc__rc$next[0:0]$6405 $3\oper_r__rc__rc$next[0:0]$6445 + attribute \src "libresoc.v:142905.5-142905.29" switch \initial - attribute \src "libresoc.v:142025.9-142025.17" + attribute \src "libresoc.v:142905.9-142905.17" case 1'1 case end @@ -229170,24 +229590,24 @@ module \ldst0 assign { } { } assign { } { } assign { } { } - assign { $1\oper_r__insn$next[31:0]$6429 $1\oper_r__ldst_mode$next[1:0]$6433 $1\oper_r__sign_extend$next[0:0]$6438 $1\oper_r__byte_reverse$next[0:0]$6424 $1\oper_r__data_len$next[3:0]$6425 $1\oper_r__is_signed$next[0:0]$6432 $1\oper_r__is_32bit$next[0:0]$6431 $1\oper_r__oe__ok$next[0:0]$6435 $1\oper_r__oe__oe$next[0:0]$6434 $1\oper_r__rc__ok$next[0:0]$6436 $1\oper_r__rc__rc$next[0:0]$6437 $1\oper_r__zero_a$next[0:0]$6439 $1\oper_r__imm_data__ok$next[0:0]$6428 $1\oper_r__imm_data__data$next[63:0]$6427 $1\oper_r__fn_unit$next[13:0]$6426 $1\oper_r__insn_type$next[6:0]$6430 } { \oper_i_ldst_ldst0__insn \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__oe__ok \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__rc__ok \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__imm_data__ok \oper_i_ldst_ldst0__imm_data__data \oper_i_ldst_ldst0__fn_unit \oper_i_ldst_ldst0__insn_type } + assign { $1\oper_r__insn$next[31:0]$6413 $1\oper_r__ldst_mode$next[1:0]$6417 $1\oper_r__sign_extend$next[0:0]$6422 $1\oper_r__byte_reverse$next[0:0]$6408 $1\oper_r__data_len$next[3:0]$6409 $1\oper_r__is_signed$next[0:0]$6416 $1\oper_r__is_32bit$next[0:0]$6415 $1\oper_r__oe__ok$next[0:0]$6419 $1\oper_r__oe__oe$next[0:0]$6418 $1\oper_r__rc__ok$next[0:0]$6420 $1\oper_r__rc__rc$next[0:0]$6421 $1\oper_r__zero_a$next[0:0]$6423 $1\oper_r__imm_data__ok$next[0:0]$6412 $1\oper_r__imm_data__data$next[63:0]$6411 $1\oper_r__fn_unit$next[13:0]$6410 $1\oper_r__insn_type$next[6:0]$6414 } { \oper_i_ldst_ldst0__insn \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__oe__ok \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__rc__ok \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__imm_data__ok \oper_i_ldst_ldst0__imm_data__data \oper_i_ldst_ldst0__fn_unit \oper_i_ldst_ldst0__insn_type } case - assign $1\oper_r__byte_reverse$next[0:0]$6424 \oper_r__byte_reverse - assign $1\oper_r__data_len$next[3:0]$6425 \oper_r__data_len - assign $1\oper_r__fn_unit$next[13:0]$6426 \oper_r__fn_unit - assign $1\oper_r__imm_data__data$next[63:0]$6427 \oper_r__imm_data__data - assign $1\oper_r__imm_data__ok$next[0:0]$6428 \oper_r__imm_data__ok - assign $1\oper_r__insn$next[31:0]$6429 \oper_r__insn - assign $1\oper_r__insn_type$next[6:0]$6430 \oper_r__insn_type - assign $1\oper_r__is_32bit$next[0:0]$6431 \oper_r__is_32bit - assign $1\oper_r__is_signed$next[0:0]$6432 \oper_r__is_signed - assign $1\oper_r__ldst_mode$next[1:0]$6433 \oper_r__ldst_mode - assign $1\oper_r__oe__oe$next[0:0]$6434 \oper_r__oe__oe - assign $1\oper_r__oe__ok$next[0:0]$6435 \oper_r__oe__ok - assign $1\oper_r__rc__ok$next[0:0]$6436 \oper_r__rc__ok - assign $1\oper_r__rc__rc$next[0:0]$6437 \oper_r__rc__rc - assign $1\oper_r__sign_extend$next[0:0]$6438 \oper_r__sign_extend - assign $1\oper_r__zero_a$next[0:0]$6439 \oper_r__zero_a + assign $1\oper_r__byte_reverse$next[0:0]$6408 \oper_r__byte_reverse + assign $1\oper_r__data_len$next[3:0]$6409 \oper_r__data_len + assign $1\oper_r__fn_unit$next[13:0]$6410 \oper_r__fn_unit + assign $1\oper_r__imm_data__data$next[63:0]$6411 \oper_r__imm_data__data + assign $1\oper_r__imm_data__ok$next[0:0]$6412 \oper_r__imm_data__ok + assign $1\oper_r__insn$next[31:0]$6413 \oper_r__insn + assign $1\oper_r__insn_type$next[6:0]$6414 \oper_r__insn_type + assign $1\oper_r__is_32bit$next[0:0]$6415 \oper_r__is_32bit + assign $1\oper_r__is_signed$next[0:0]$6416 \oper_r__is_signed + assign $1\oper_r__ldst_mode$next[1:0]$6417 \oper_r__ldst_mode + assign $1\oper_r__oe__oe$next[0:0]$6418 \oper_r__oe__oe + assign $1\oper_r__oe__ok$next[0:0]$6419 \oper_r__oe__ok + assign $1\oper_r__rc__ok$next[0:0]$6420 \oper_r__rc__ok + assign $1\oper_r__rc__rc$next[0:0]$6421 \oper_r__rc__rc + assign $1\oper_r__sign_extend$next[0:0]$6422 \oper_r__sign_extend + assign $1\oper_r__zero_a$next[0:0]$6423 \oper_r__zero_a end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:381" switch \cu_done_o @@ -229209,24 +229629,24 @@ module \ldst0 assign { } { } assign { } { } assign { } { } - assign { $2\oper_r__insn$next[31:0]$6445 $2\oper_r__ldst_mode$next[1:0]$6449 $2\oper_r__sign_extend$next[0:0]$6454 $2\oper_r__byte_reverse$next[0:0]$6440 $2\oper_r__data_len$next[3:0]$6441 $2\oper_r__is_signed$next[0:0]$6448 $2\oper_r__is_32bit$next[0:0]$6447 $2\oper_r__oe__ok$next[0:0]$6451 $2\oper_r__oe__oe$next[0:0]$6450 $2\oper_r__rc__ok$next[0:0]$6452 $2\oper_r__rc__rc$next[0:0]$6453 $2\oper_r__zero_a$next[0:0]$6455 $2\oper_r__imm_data__ok$next[0:0]$6444 $2\oper_r__imm_data__data$next[63:0]$6443 $2\oper_r__fn_unit$next[13:0]$6442 $2\oper_r__insn_type$next[6:0]$6446 } 133'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign { $2\oper_r__insn$next[31:0]$6429 $2\oper_r__ldst_mode$next[1:0]$6433 $2\oper_r__sign_extend$next[0:0]$6438 $2\oper_r__byte_reverse$next[0:0]$6424 $2\oper_r__data_len$next[3:0]$6425 $2\oper_r__is_signed$next[0:0]$6432 $2\oper_r__is_32bit$next[0:0]$6431 $2\oper_r__oe__ok$next[0:0]$6435 $2\oper_r__oe__oe$next[0:0]$6434 $2\oper_r__rc__ok$next[0:0]$6436 $2\oper_r__rc__rc$next[0:0]$6437 $2\oper_r__zero_a$next[0:0]$6439 $2\oper_r__imm_data__ok$next[0:0]$6428 $2\oper_r__imm_data__data$next[63:0]$6427 $2\oper_r__fn_unit$next[13:0]$6426 $2\oper_r__insn_type$next[6:0]$6430 } 133'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 case - assign $2\oper_r__byte_reverse$next[0:0]$6440 $1\oper_r__byte_reverse$next[0:0]$6424 - assign $2\oper_r__data_len$next[3:0]$6441 $1\oper_r__data_len$next[3:0]$6425 - assign $2\oper_r__fn_unit$next[13:0]$6442 $1\oper_r__fn_unit$next[13:0]$6426 - assign $2\oper_r__imm_data__data$next[63:0]$6443 $1\oper_r__imm_data__data$next[63:0]$6427 - assign $2\oper_r__imm_data__ok$next[0:0]$6444 $1\oper_r__imm_data__ok$next[0:0]$6428 - assign $2\oper_r__insn$next[31:0]$6445 $1\oper_r__insn$next[31:0]$6429 - assign $2\oper_r__insn_type$next[6:0]$6446 $1\oper_r__insn_type$next[6:0]$6430 - assign $2\oper_r__is_32bit$next[0:0]$6447 $1\oper_r__is_32bit$next[0:0]$6431 - assign $2\oper_r__is_signed$next[0:0]$6448 $1\oper_r__is_signed$next[0:0]$6432 - assign $2\oper_r__ldst_mode$next[1:0]$6449 $1\oper_r__ldst_mode$next[1:0]$6433 - assign $2\oper_r__oe__oe$next[0:0]$6450 $1\oper_r__oe__oe$next[0:0]$6434 - assign $2\oper_r__oe__ok$next[0:0]$6451 $1\oper_r__oe__ok$next[0:0]$6435 - assign $2\oper_r__rc__ok$next[0:0]$6452 $1\oper_r__rc__ok$next[0:0]$6436 - assign $2\oper_r__rc__rc$next[0:0]$6453 $1\oper_r__rc__rc$next[0:0]$6437 - assign $2\oper_r__sign_extend$next[0:0]$6454 $1\oper_r__sign_extend$next[0:0]$6438 - assign $2\oper_r__zero_a$next[0:0]$6455 $1\oper_r__zero_a$next[0:0]$6439 + assign $2\oper_r__byte_reverse$next[0:0]$6424 $1\oper_r__byte_reverse$next[0:0]$6408 + assign $2\oper_r__data_len$next[3:0]$6425 $1\oper_r__data_len$next[3:0]$6409 + assign $2\oper_r__fn_unit$next[13:0]$6426 $1\oper_r__fn_unit$next[13:0]$6410 + assign $2\oper_r__imm_data__data$next[63:0]$6427 $1\oper_r__imm_data__data$next[63:0]$6411 + assign $2\oper_r__imm_data__ok$next[0:0]$6428 $1\oper_r__imm_data__ok$next[0:0]$6412 + assign $2\oper_r__insn$next[31:0]$6429 $1\oper_r__insn$next[31:0]$6413 + assign $2\oper_r__insn_type$next[6:0]$6430 $1\oper_r__insn_type$next[6:0]$6414 + assign $2\oper_r__is_32bit$next[0:0]$6431 $1\oper_r__is_32bit$next[0:0]$6415 + assign $2\oper_r__is_signed$next[0:0]$6432 $1\oper_r__is_signed$next[0:0]$6416 + assign $2\oper_r__ldst_mode$next[1:0]$6433 $1\oper_r__ldst_mode$next[1:0]$6417 + assign $2\oper_r__oe__oe$next[0:0]$6434 $1\oper_r__oe__oe$next[0:0]$6418 + assign $2\oper_r__oe__ok$next[0:0]$6435 $1\oper_r__oe__ok$next[0:0]$6419 + assign $2\oper_r__rc__ok$next[0:0]$6436 $1\oper_r__rc__ok$next[0:0]$6420 + assign $2\oper_r__rc__rc$next[0:0]$6437 $1\oper_r__rc__rc$next[0:0]$6421 + assign $2\oper_r__sign_extend$next[0:0]$6438 $1\oper_r__sign_extend$next[0:0]$6422 + assign $2\oper_r__zero_a$next[0:0]$6439 $1\oper_r__zero_a$next[0:0]$6423 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -229238,46 +229658,46 @@ module \ldst0 assign { } { } assign { } { } assign { } { } - assign $3\oper_r__imm_data__data$next[63:0]$6456 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\oper_r__imm_data__ok$next[0:0]$6457 1'0 - assign $3\oper_r__rc__rc$next[0:0]$6461 1'0 - assign $3\oper_r__rc__ok$next[0:0]$6460 1'0 - assign $3\oper_r__oe__oe$next[0:0]$6458 1'0 - assign $3\oper_r__oe__ok$next[0:0]$6459 1'0 + assign $3\oper_r__imm_data__data$next[63:0]$6440 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\oper_r__imm_data__ok$next[0:0]$6441 1'0 + assign $3\oper_r__rc__rc$next[0:0]$6445 1'0 + assign $3\oper_r__rc__ok$next[0:0]$6444 1'0 + assign $3\oper_r__oe__oe$next[0:0]$6442 1'0 + assign $3\oper_r__oe__ok$next[0:0]$6443 1'0 case - assign $3\oper_r__imm_data__data$next[63:0]$6456 $2\oper_r__imm_data__data$next[63:0]$6443 - assign $3\oper_r__imm_data__ok$next[0:0]$6457 $2\oper_r__imm_data__ok$next[0:0]$6444 - assign $3\oper_r__oe__oe$next[0:0]$6458 $2\oper_r__oe__oe$next[0:0]$6450 - assign $3\oper_r__oe__ok$next[0:0]$6459 $2\oper_r__oe__ok$next[0:0]$6451 - assign $3\oper_r__rc__ok$next[0:0]$6460 $2\oper_r__rc__ok$next[0:0]$6452 - assign $3\oper_r__rc__rc$next[0:0]$6461 $2\oper_r__rc__rc$next[0:0]$6453 + assign $3\oper_r__imm_data__data$next[63:0]$6440 $2\oper_r__imm_data__data$next[63:0]$6427 + assign $3\oper_r__imm_data__ok$next[0:0]$6441 $2\oper_r__imm_data__ok$next[0:0]$6428 + assign $3\oper_r__oe__oe$next[0:0]$6442 $2\oper_r__oe__oe$next[0:0]$6434 + assign $3\oper_r__oe__ok$next[0:0]$6443 $2\oper_r__oe__ok$next[0:0]$6435 + assign $3\oper_r__rc__ok$next[0:0]$6444 $2\oper_r__rc__ok$next[0:0]$6436 + assign $3\oper_r__rc__rc$next[0:0]$6445 $2\oper_r__rc__rc$next[0:0]$6437 end sync always - update \oper_r__byte_reverse$next $0\oper_r__byte_reverse$next[0:0]$6408 - update \oper_r__data_len$next $0\oper_r__data_len$next[3:0]$6409 - update \oper_r__fn_unit$next $0\oper_r__fn_unit$next[13:0]$6410 - update \oper_r__imm_data__data$next $0\oper_r__imm_data__data$next[63:0]$6411 - update \oper_r__imm_data__ok$next $0\oper_r__imm_data__ok$next[0:0]$6412 - update \oper_r__insn$next $0\oper_r__insn$next[31:0]$6413 - update \oper_r__insn_type$next $0\oper_r__insn_type$next[6:0]$6414 - update \oper_r__is_32bit$next $0\oper_r__is_32bit$next[0:0]$6415 - update \oper_r__is_signed$next $0\oper_r__is_signed$next[0:0]$6416 - update \oper_r__ldst_mode$next $0\oper_r__ldst_mode$next[1:0]$6417 - update \oper_r__oe__oe$next $0\oper_r__oe__oe$next[0:0]$6418 - update \oper_r__oe__ok$next $0\oper_r__oe__ok$next[0:0]$6419 - update \oper_r__rc__ok$next $0\oper_r__rc__ok$next[0:0]$6420 - update \oper_r__rc__rc$next $0\oper_r__rc__rc$next[0:0]$6421 - update \oper_r__sign_extend$next $0\oper_r__sign_extend$next[0:0]$6422 - update \oper_r__zero_a$next $0\oper_r__zero_a$next[0:0]$6423 + update \oper_r__byte_reverse$next $0\oper_r__byte_reverse$next[0:0]$6392 + update \oper_r__data_len$next $0\oper_r__data_len$next[3:0]$6393 + update \oper_r__fn_unit$next $0\oper_r__fn_unit$next[13:0]$6394 + update \oper_r__imm_data__data$next $0\oper_r__imm_data__data$next[63:0]$6395 + update \oper_r__imm_data__ok$next $0\oper_r__imm_data__ok$next[0:0]$6396 + update \oper_r__insn$next $0\oper_r__insn$next[31:0]$6397 + update \oper_r__insn_type$next $0\oper_r__insn_type$next[6:0]$6398 + update \oper_r__is_32bit$next $0\oper_r__is_32bit$next[0:0]$6399 + update \oper_r__is_signed$next $0\oper_r__is_signed$next[0:0]$6400 + update \oper_r__ldst_mode$next $0\oper_r__ldst_mode$next[1:0]$6401 + update \oper_r__oe__oe$next $0\oper_r__oe__oe$next[0:0]$6402 + update \oper_r__oe__ok$next $0\oper_r__oe__ok$next[0:0]$6403 + update \oper_r__rc__ok$next $0\oper_r__rc__ok$next[0:0]$6404 + update \oper_r__rc__rc$next $0\oper_r__rc__rc$next[0:0]$6405 + update \oper_r__sign_extend$next $0\oper_r__sign_extend$next[0:0]$6406 + update \oper_r__zero_a$next $0\oper_r__zero_a$next[0:0]$6407 end - attribute \src "libresoc.v:142067.3-142076.6" - process $proc$libresoc.v:142067$6462 + attribute \src "libresoc.v:142947.3-142956.6" + process $proc$libresoc.v:142947$6446 assign { } { } assign { } { } - assign $0\ldo_r$next[63:0]$6463 $1\ldo_r$next[63:0]$6464 - attribute \src "libresoc.v:142068.5-142068.29" + assign $0\ldo_r$next[63:0]$6447 $1\ldo_r$next[63:0]$6448 + attribute \src "libresoc.v:142948.5-142948.29" switch \initial - attribute \src "libresoc.v:142068.9-142068.17" + attribute \src "libresoc.v:142948.9-142948.17" case 1'1 case end @@ -229286,22 +229706,22 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldo_r$next[63:0]$6464 \ldd_o + assign $1\ldo_r$next[63:0]$6448 \ldd_o case - assign $1\ldo_r$next[63:0]$6464 \ldo_r + assign $1\ldo_r$next[63:0]$6448 \ldo_r end sync always - update \ldo_r$next $0\ldo_r$next[63:0]$6463 + update \ldo_r$next $0\ldo_r$next[63:0]$6447 end - attribute \src "libresoc.v:142077.3-142092.6" - process $proc$libresoc.v:142077$6465 + attribute \src "libresoc.v:142957.3-142972.6" + process $proc$libresoc.v:142957$6449 assign { } { } assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$6466 $2\src_r0$next[63:0]$6468 - attribute \src "libresoc.v:142078.5-142078.29" + assign $0\src_r0$next[63:0]$6450 $2\src_r0$next[63:0]$6452 + attribute \src "libresoc.v:142958.5-142958.29" switch \initial - attribute \src "libresoc.v:142078.9-142078.17" + attribute \src "libresoc.v:142958.9-142958.17" case 1'1 case end @@ -229310,31 +229730,31 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$6467 \src1_i + assign $1\src_r0$next[63:0]$6451 \src1_i case - assign $1\src_r0$next[63:0]$6467 \src_r0 + assign $1\src_r0$next[63:0]$6451 \src_r0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src_r0$next[63:0]$6468 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\src_r0$next[63:0]$6452 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $2\src_r0$next[63:0]$6468 $1\src_r0$next[63:0]$6467 + assign $2\src_r0$next[63:0]$6452 $1\src_r0$next[63:0]$6451 end sync always - update \src_r0$next $0\src_r0$next[63:0]$6466 + update \src_r0$next $0\src_r0$next[63:0]$6450 end - attribute \src "libresoc.v:142093.3-142108.6" - process $proc$libresoc.v:142093$6469 + attribute \src "libresoc.v:142973.3-142988.6" + process $proc$libresoc.v:142973$6453 assign { } { } assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$6470 $2\src_r1$next[63:0]$6472 - attribute \src "libresoc.v:142094.5-142094.29" + assign $0\src_r1$next[63:0]$6454 $2\src_r1$next[63:0]$6456 + attribute \src "libresoc.v:142974.5-142974.29" switch \initial - attribute \src "libresoc.v:142094.9-142094.17" + attribute \src "libresoc.v:142974.9-142974.17" case 1'1 case end @@ -229343,31 +229763,31 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$6471 \src2_i + assign $1\src_r1$next[63:0]$6455 \src2_i case - assign $1\src_r1$next[63:0]$6471 \src_r1 + assign $1\src_r1$next[63:0]$6455 \src_r1 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src_r1$next[63:0]$6472 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\src_r1$next[63:0]$6456 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $2\src_r1$next[63:0]$6472 $1\src_r1$next[63:0]$6471 + assign $2\src_r1$next[63:0]$6456 $1\src_r1$next[63:0]$6455 end sync always - update \src_r1$next $0\src_r1$next[63:0]$6470 + update \src_r1$next $0\src_r1$next[63:0]$6454 end - attribute \src "libresoc.v:142109.3-142124.6" - process $proc$libresoc.v:142109$6473 + attribute \src "libresoc.v:142989.3-143004.6" + process $proc$libresoc.v:142989$6457 assign { } { } assign { } { } assign { } { } - assign $0\src_r2$next[63:0]$6474 $2\src_r2$next[63:0]$6476 - attribute \src "libresoc.v:142110.5-142110.29" + assign $0\src_r2$next[63:0]$6458 $2\src_r2$next[63:0]$6460 + attribute \src "libresoc.v:142990.5-142990.29" switch \initial - attribute \src "libresoc.v:142110.9-142110.17" + attribute \src "libresoc.v:142990.9-142990.17" case 1'1 case end @@ -229376,30 +229796,30 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[63:0]$6475 \src3_i + assign $1\src_r2$next[63:0]$6459 \src3_i case - assign $1\src_r2$next[63:0]$6475 \src_r2 + assign $1\src_r2$next[63:0]$6459 \src_r2 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395" switch \cu_issue_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src_r2$next[63:0]$6476 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\src_r2$next[63:0]$6460 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $2\src_r2$next[63:0]$6476 $1\src_r2$next[63:0]$6475 + assign $2\src_r2$next[63:0]$6460 $1\src_r2$next[63:0]$6459 end sync always - update \src_r2$next $0\src_r2$next[63:0]$6474 + update \src_r2$next $0\src_r2$next[63:0]$6458 end - attribute \src "libresoc.v:142125.3-142134.6" - process $proc$libresoc.v:142125$6477 + attribute \src "libresoc.v:143005.3-143014.6" + process $proc$libresoc.v:143005$6461 assign { } { } assign { } { } - assign $0\ea_r$next[63:0]$6478 $1\ea_r$next[63:0]$6479 - attribute \src "libresoc.v:142126.5-142126.29" + assign $0\ea_r$next[63:0]$6462 $1\ea_r$next[63:0]$6463 + attribute \src "libresoc.v:143006.5-143006.29" switch \initial - attribute \src "libresoc.v:142126.9-142126.17" + attribute \src "libresoc.v:143006.9-143006.17" case 1'1 case end @@ -229408,21 +229828,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ea_r$next[63:0]$6479 \alu_o + assign $1\ea_r$next[63:0]$6463 \alu_o case - assign $1\ea_r$next[63:0]$6479 \ea_r + assign $1\ea_r$next[63:0]$6463 \ea_r end sync always - update \ea_r$next $0\ea_r$next[63:0]$6478 + update \ea_r$next $0\ea_r$next[63:0]$6462 end - attribute \src "libresoc.v:142135.3-142144.6" - process $proc$libresoc.v:142135$6480 + attribute \src "libresoc.v:143015.3-143024.6" + process $proc$libresoc.v:143015$6464 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:142136.5-142136.29" + attribute \src "libresoc.v:143016.5-143016.29" switch \initial - attribute \src "libresoc.v:142136.9-142136.17" + attribute \src "libresoc.v:143016.9-143016.17" case 1'1 case end @@ -229438,14 +229858,14 @@ module \ldst0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:142145.3-142154.6" - process $proc$libresoc.v:142145$6481 + attribute \src "libresoc.v:143025.3-143034.6" + process $proc$libresoc.v:143025$6465 assign { } { } assign { } { } assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "libresoc.v:142146.5-142146.29" + attribute \src "libresoc.v:143026.5-143026.29" switch \initial - attribute \src "libresoc.v:142146.9-142146.17" + attribute \src "libresoc.v:143026.9-143026.17" case 1'1 case end @@ -229461,14 +229881,14 @@ module \ldst0 sync always update \dest2_o $0\dest2_o[63:0] end - attribute \src "libresoc.v:142155.3-142163.6" - process $proc$libresoc.v:142155$6482 + attribute \src "libresoc.v:143035.3-143043.6" + process $proc$libresoc.v:143035$6466 assign { } { } assign { } { } - assign $0\ldst_port0_addr_i_ok$next[0:0]$6483 $1\ldst_port0_addr_i_ok$next[0:0]$6484 - attribute \src "libresoc.v:142156.5-142156.29" + assign $0\ldst_port0_addr_i_ok$next[0:0]$6467 $1\ldst_port0_addr_i_ok$next[0:0]$6468 + attribute \src "libresoc.v:143036.5-143036.29" switch \initial - attribute \src "libresoc.v:142156.9-142156.17" + attribute \src "libresoc.v:143036.9-143036.17" case 1'1 case end @@ -229477,21 +229897,21 @@ module \ldst0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ldst_port0_addr_i_ok$next[0:0]$6484 1'0 + assign $1\ldst_port0_addr_i_ok$next[0:0]$6468 1'0 case - assign $1\ldst_port0_addr_i_ok$next[0:0]$6484 \$177 + assign $1\ldst_port0_addr_i_ok$next[0:0]$6468 \$177 end sync always - update \ldst_port0_addr_i_ok$next $0\ldst_port0_addr_i_ok$next[0:0]$6483 + update \ldst_port0_addr_i_ok$next $0\ldst_port0_addr_i_ok$next[0:0]$6467 end - attribute \src "libresoc.v:142164.3-142187.6" - process $proc$libresoc.v:142164$6485 + attribute \src "libresoc.v:143044.3-143067.6" + process $proc$libresoc.v:143044$6469 assign { } { } assign { } { } assign $0\lddata_r[63:0] $1\lddata_r[63:0] - attribute \src "libresoc.v:142165.5-142165.29" + attribute \src "libresoc.v:143045.5-143045.29" switch \initial - attribute \src "libresoc.v:142165.9-142165.17" + attribute \src "libresoc.v:143045.9-143045.17" case 1'1 case end @@ -229528,13 +229948,13 @@ module \ldst0 sync always update \lddata_r $0\lddata_r[63:0] end - attribute \src "libresoc.v:142188.3-142199.6" - process $proc$libresoc.v:142188$6486 + attribute \src "libresoc.v:143068.3-143079.6" + process $proc$libresoc.v:143068$6470 assign { } { } assign $0\revnorev[63:0] $1\revnorev[63:0] - attribute \src "libresoc.v:142189.5-142189.29" + attribute \src "libresoc.v:143069.5-143069.29" switch \initial - attribute \src "libresoc.v:142189.9-142189.17" + attribute \src "libresoc.v:143069.9-143069.17" case 1'1 case end @@ -229552,13 +229972,13 @@ module \ldst0 sync always update \revnorev $0\revnorev[63:0] end - attribute \src "libresoc.v:142200.3-142219.6" - process $proc$libresoc.v:142200$6487 + attribute \src "libresoc.v:143080.3-143099.6" + process $proc$libresoc.v:143080$6471 assign { } { } assign $0\ldd_o[63:0] $1\ldd_o[63:0] - attribute \src "libresoc.v:142201.5-142201.29" + attribute \src "libresoc.v:143081.5-143081.29" switch \initial - attribute \src "libresoc.v:142201.9-142201.17" + attribute \src "libresoc.v:143081.9-143081.17" case 1'1 case end @@ -229587,14 +230007,14 @@ module \ldst0 sync always update \ldd_o $0\ldd_o[63:0] end - attribute \src "libresoc.v:142220.3-142243.6" - process $proc$libresoc.v:142220$6488 + attribute \src "libresoc.v:143100.3-143123.6" + process $proc$libresoc.v:143100$6472 assign { } { } assign { } { } assign $0\stdata_r[63:0] $1\stdata_r[63:0] - attribute \src "libresoc.v:142221.5-142221.29" + attribute \src "libresoc.v:143101.5-143101.29" switch \initial - attribute \src "libresoc.v:142221.9-142221.17" + attribute \src "libresoc.v:143101.9-143101.17" case 1'1 case end @@ -229631,13 +230051,13 @@ module \ldst0 sync always update \stdata_r $0\stdata_r[63:0] end - attribute \src "libresoc.v:142244.3-142255.6" - process $proc$libresoc.v:142244$6489 + attribute \src "libresoc.v:143124.3-143135.6" + process $proc$libresoc.v:143124$6473 assign { } { } assign $0\ldst_port0_st_data_i[63:0] $1\ldst_port0_st_data_i[63:0] - attribute \src "libresoc.v:142245.5-142245.29" + attribute \src "libresoc.v:143125.5-143125.29" switch \initial - attribute \src "libresoc.v:142245.9-142245.17" + attribute \src "libresoc.v:143125.9-143125.17" case 1'1 case end @@ -229655,97 +230075,97 @@ module \ldst0 sync always update \ldst_port0_st_data_i $0\ldst_port0_st_data_i[63:0] end - connect \$100 $and$libresoc.v:141703$6248_Y - connect \$102 $and$libresoc.v:141704$6249_Y - connect \$104 $and$libresoc.v:141705$6250_Y - connect \$106 $and$libresoc.v:141706$6251_Y - connect \$108 $and$libresoc.v:141707$6252_Y - connect \$10 $or$libresoc.v:141708$6253_Y - connect \$110 $and$libresoc.v:141709$6254_Y - connect \$112 $and$libresoc.v:141710$6255_Y - connect \$114 $and$libresoc.v:141711$6256_Y - connect \$116 $and$libresoc.v:141712$6257_Y - connect \$118 $and$libresoc.v:141713$6258_Y - connect \$120 $and$libresoc.v:141714$6259_Y - connect \$122 $and$libresoc.v:141715$6260_Y - connect \$124 $and$libresoc.v:141716$6261_Y - connect \$126 $eq$libresoc.v:141717$6262_Y - connect \$128 $and$libresoc.v:141718$6263_Y - connect \$12 $or$libresoc.v:141719$6264_Y - connect \$130 $and$libresoc.v:141720$6265_Y - connect \$132 $and$libresoc.v:141721$6266_Y - connect \$134 $or$libresoc.v:141722$6267_Y - connect \$136 $or$libresoc.v:141723$6268_Y - connect \$138 $or$libresoc.v:141724$6269_Y - connect \$140 $and$libresoc.v:141725$6270_Y - connect \$142 $and$libresoc.v:141726$6271_Y - connect \$145 $or$libresoc.v:141727$6272_Y - connect \$147 $or$libresoc.v:141728$6273_Y - connect \$144 $not$libresoc.v:141729$6274_Y - connect \$14 $or$libresoc.v:141730$6275_Y - connect \$150 $and$libresoc.v:141731$6276_Y - connect \$152 $or$libresoc.v:141732$6277_Y - connect \$154 $and$libresoc.v:141733$6278_Y - connect \$156 $not$libresoc.v:141734$6279_Y - connect \$158 $or$libresoc.v:141735$6280_Y - connect \$160 $and$libresoc.v:141736$6281_Y - connect \$162 $eq$libresoc.v:141737$6282_Y - connect \$164 $and$libresoc.v:141738$6283_Y - connect \$167 $eq$libresoc.v:141739$6284_Y - connect \$16 $or$libresoc.v:141740$6285_Y - connect \$169 $and$libresoc.v:141741$6286_Y - connect \$171 $and$libresoc.v:141742$6287_Y - connect \$173 $and$libresoc.v:141743$6288_Y - connect \$175 $pos$libresoc.v:141744$6290_Y - connect \$177 $and$libresoc.v:141745$6291_Y - connect \$186 $pos$libresoc.v:141746$6293_Y - connect \$188 $pos$libresoc.v:141747$6294_Y - connect \$18 $or$libresoc.v:141748$6295_Y - connect \$190 $pos$libresoc.v:141749$6296_Y - connect \$192 $eq$libresoc.v:141750$6297_Y - connect \$194 $pos$libresoc.v:141751$6299_Y - connect \$196 $pos$libresoc.v:141752$6300_Y - connect \$198 $pos$libresoc.v:141753$6301_Y - connect \$20 $or$libresoc.v:141754$6302_Y - connect \$22 $eq$libresoc.v:141755$6303_Y - connect \$24 $eq$libresoc.v:141756$6304_Y - connect \$26 $and$libresoc.v:141757$6305_Y - connect \$28 $and$libresoc.v:141758$6306_Y - connect \$30 $not$libresoc.v:141759$6307_Y - connect \$32 $and$libresoc.v:141760$6308_Y - connect \$34 $not$libresoc.v:141761$6309_Y - connect \$36 $and$libresoc.v:141762$6310_Y - connect \$39 $not$libresoc.v:141763$6311_Y - connect \$41 $eq$libresoc.v:141764$6312_Y - connect \$43 $and$libresoc.v:141765$6313_Y - connect \$45 $or$libresoc.v:141766$6314_Y - connect \$47 $not$libresoc.v:141767$6315_Y - connect \$49 $eq$libresoc.v:141768$6316_Y - connect \$51 $and$libresoc.v:141769$6317_Y - connect \$53 $or$libresoc.v:141770$6318_Y - connect \$55 $or$libresoc.v:141771$6319_Y - connect \$57 $and$libresoc.v:141772$6320_Y - connect \$59 $or$libresoc.v:141773$6321_Y - connect \$61 $or$libresoc.v:141774$6322_Y - connect \$63 $or$libresoc.v:141775$6323_Y - connect \$65 $ternary$libresoc.v:141776$6324_Y - connect \$67 $ternary$libresoc.v:141777$6325_Y - connect \$69 $ternary$libresoc.v:141778$6326_Y - connect \$71 $ternary$libresoc.v:141779$6327_Y - connect \$74 $add$libresoc.v:141780$6328_Y - connect \$76 $and$libresoc.v:141781$6329_Y - connect \$78 $not$libresoc.v:141782$6330_Y - connect \$80 $and$libresoc.v:141783$6331_Y - connect \$82 $not$libresoc.v:141784$6332_Y - connect \$84 $and$libresoc.v:141785$6333_Y - connect \$86 $and$libresoc.v:141786$6334_Y - connect \$88 $and$libresoc.v:141787$6335_Y - connect \$8 $or$libresoc.v:141788$6336_Y - connect \$90 $or$libresoc.v:141789$6337_Y - connect \$93 $or$libresoc.v:141790$6338_Y - connect \$92 $not$libresoc.v:141791$6339_Y - connect \$96 $and$libresoc.v:141792$6340_Y - connect \$98 $not$libresoc.v:141793$6341_Y + connect \$100 $and$libresoc.v:142583$6232_Y + connect \$102 $and$libresoc.v:142584$6233_Y + connect \$104 $and$libresoc.v:142585$6234_Y + connect \$106 $and$libresoc.v:142586$6235_Y + connect \$108 $and$libresoc.v:142587$6236_Y + connect \$10 $or$libresoc.v:142588$6237_Y + connect \$110 $and$libresoc.v:142589$6238_Y + connect \$112 $and$libresoc.v:142590$6239_Y + connect \$114 $and$libresoc.v:142591$6240_Y + connect \$116 $and$libresoc.v:142592$6241_Y + connect \$118 $and$libresoc.v:142593$6242_Y + connect \$120 $and$libresoc.v:142594$6243_Y + connect \$122 $and$libresoc.v:142595$6244_Y + connect \$124 $and$libresoc.v:142596$6245_Y + connect \$126 $eq$libresoc.v:142597$6246_Y + connect \$128 $and$libresoc.v:142598$6247_Y + connect \$12 $or$libresoc.v:142599$6248_Y + connect \$130 $and$libresoc.v:142600$6249_Y + connect \$132 $and$libresoc.v:142601$6250_Y + connect \$134 $or$libresoc.v:142602$6251_Y + connect \$136 $or$libresoc.v:142603$6252_Y + connect \$138 $or$libresoc.v:142604$6253_Y + connect \$140 $and$libresoc.v:142605$6254_Y + connect \$142 $and$libresoc.v:142606$6255_Y + connect \$145 $or$libresoc.v:142607$6256_Y + connect \$147 $or$libresoc.v:142608$6257_Y + connect \$144 $not$libresoc.v:142609$6258_Y + connect \$14 $or$libresoc.v:142610$6259_Y + connect \$150 $and$libresoc.v:142611$6260_Y + connect \$152 $or$libresoc.v:142612$6261_Y + connect \$154 $and$libresoc.v:142613$6262_Y + connect \$156 $not$libresoc.v:142614$6263_Y + connect \$158 $or$libresoc.v:142615$6264_Y + connect \$160 $and$libresoc.v:142616$6265_Y + connect \$162 $eq$libresoc.v:142617$6266_Y + connect \$164 $and$libresoc.v:142618$6267_Y + connect \$167 $eq$libresoc.v:142619$6268_Y + connect \$16 $or$libresoc.v:142620$6269_Y + connect \$169 $and$libresoc.v:142621$6270_Y + connect \$171 $and$libresoc.v:142622$6271_Y + connect \$173 $and$libresoc.v:142623$6272_Y + connect \$175 $pos$libresoc.v:142624$6274_Y + connect \$177 $and$libresoc.v:142625$6275_Y + connect \$186 $pos$libresoc.v:142626$6277_Y + connect \$188 $pos$libresoc.v:142627$6278_Y + connect \$18 $or$libresoc.v:142628$6279_Y + connect \$190 $pos$libresoc.v:142629$6280_Y + connect \$192 $eq$libresoc.v:142630$6281_Y + connect \$194 $pos$libresoc.v:142631$6283_Y + connect \$196 $pos$libresoc.v:142632$6284_Y + connect \$198 $pos$libresoc.v:142633$6285_Y + connect \$20 $or$libresoc.v:142634$6286_Y + connect \$22 $eq$libresoc.v:142635$6287_Y + connect \$24 $eq$libresoc.v:142636$6288_Y + connect \$26 $and$libresoc.v:142637$6289_Y + connect \$28 $and$libresoc.v:142638$6290_Y + connect \$30 $not$libresoc.v:142639$6291_Y + connect \$32 $and$libresoc.v:142640$6292_Y + connect \$34 $not$libresoc.v:142641$6293_Y + connect \$36 $and$libresoc.v:142642$6294_Y + connect \$39 $not$libresoc.v:142643$6295_Y + connect \$41 $eq$libresoc.v:142644$6296_Y + connect \$43 $and$libresoc.v:142645$6297_Y + connect \$45 $or$libresoc.v:142646$6298_Y + connect \$47 $not$libresoc.v:142647$6299_Y + connect \$49 $eq$libresoc.v:142648$6300_Y + connect \$51 $and$libresoc.v:142649$6301_Y + connect \$53 $or$libresoc.v:142650$6302_Y + connect \$55 $or$libresoc.v:142651$6303_Y + connect \$57 $and$libresoc.v:142652$6304_Y + connect \$59 $or$libresoc.v:142653$6305_Y + connect \$61 $or$libresoc.v:142654$6306_Y + connect \$63 $or$libresoc.v:142655$6307_Y + connect \$65 $ternary$libresoc.v:142656$6308_Y + connect \$67 $ternary$libresoc.v:142657$6309_Y + connect \$69 $ternary$libresoc.v:142658$6310_Y + connect \$71 $ternary$libresoc.v:142659$6311_Y + connect \$74 $add$libresoc.v:142660$6312_Y + connect \$76 $and$libresoc.v:142661$6313_Y + connect \$78 $not$libresoc.v:142662$6314_Y + connect \$80 $and$libresoc.v:142663$6315_Y + connect \$82 $not$libresoc.v:142664$6316_Y + connect \$84 $and$libresoc.v:142665$6317_Y + connect \$86 $and$libresoc.v:142666$6318_Y + connect \$88 $and$libresoc.v:142667$6319_Y + connect \$8 $or$libresoc.v:142668$6320_Y + connect \$90 $or$libresoc.v:142669$6321_Y + connect \$93 $or$libresoc.v:142670$6322_Y + connect \$92 $not$libresoc.v:142671$6323_Y + connect \$96 $and$libresoc.v:142672$6324_Y + connect \$98 $not$libresoc.v:142673$6325_Y connect \$38 \$55 connect \$73 \$74 connect \$166 \$169 @@ -229806,271 +230226,271 @@ module \ldst0 connect \reset_o \$10 connect \reset_i \$8 end -attribute \src "libresoc.v:142319.1-142906.10" +attribute \src "libresoc.v:143199.1-143786.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.left_mask" attribute \generator "nMigen" module \left_mask - attribute \src "libresoc.v:142320.7-142320.20" + attribute \src "libresoc.v:143200.7-143200.20" wire $0\initial[0:0] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire width 64 $0\mask[63:0] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $10\mask[9:9] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $11\mask[10:10] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $12\mask[11:11] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $13\mask[12:12] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $14\mask[13:13] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $15\mask[14:14] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $16\mask[15:15] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $17\mask[16:16] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $18\mask[17:17] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $19\mask[18:18] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $1\mask[0:0] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $20\mask[19:19] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $21\mask[20:20] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $22\mask[21:21] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $23\mask[22:22] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $24\mask[23:23] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $25\mask[24:24] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $26\mask[25:25] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $27\mask[26:26] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $28\mask[27:27] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $29\mask[28:28] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $2\mask[1:1] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $30\mask[29:29] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $31\mask[30:30] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $32\mask[31:31] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $33\mask[32:32] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $34\mask[33:33] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $35\mask[34:34] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $36\mask[35:35] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $37\mask[36:36] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $38\mask[37:37] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $39\mask[38:38] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $3\mask[2:2] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $40\mask[39:39] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $41\mask[40:40] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $42\mask[41:41] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $43\mask[42:42] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $44\mask[43:43] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $45\mask[44:44] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $46\mask[45:45] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $47\mask[46:46] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $48\mask[47:47] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $49\mask[48:48] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $4\mask[3:3] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $50\mask[49:49] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $51\mask[50:50] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $52\mask[51:51] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $53\mask[52:52] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $54\mask[53:53] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $55\mask[54:54] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $56\mask[55:55] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $57\mask[56:56] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $58\mask[57:57] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $59\mask[58:58] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $5\mask[4:4] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $60\mask[59:59] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $61\mask[60:60] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $62\mask[61:61] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $63\mask[62:62] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $64\mask[63:63] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $6\mask[5:5] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $7\mask[6:6] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $8\mask[7:7] - attribute \src "libresoc.v:142518.3-142905.6" + attribute \src "libresoc.v:143398.3-143785.6" wire $9\mask[8:8] - attribute \src "libresoc.v:142454.17-142454.96" - wire $gt$libresoc.v:142454$6526_Y - attribute \src "libresoc.v:142455.18-142455.98" - wire $gt$libresoc.v:142455$6527_Y - attribute \src "libresoc.v:142456.19-142456.99" - wire $gt$libresoc.v:142456$6528_Y - attribute \src "libresoc.v:142457.19-142457.99" - wire $gt$libresoc.v:142457$6529_Y - attribute \src "libresoc.v:142458.19-142458.99" - wire $gt$libresoc.v:142458$6530_Y - attribute \src "libresoc.v:142459.19-142459.99" - wire $gt$libresoc.v:142459$6531_Y - attribute \src "libresoc.v:142460.19-142460.99" - wire $gt$libresoc.v:142460$6532_Y - attribute \src "libresoc.v:142461.19-142461.99" - wire $gt$libresoc.v:142461$6533_Y - attribute \src "libresoc.v:142462.19-142462.99" - wire $gt$libresoc.v:142462$6534_Y - attribute \src "libresoc.v:142463.19-142463.99" - wire $gt$libresoc.v:142463$6535_Y - attribute \src "libresoc.v:142464.19-142464.99" - wire $gt$libresoc.v:142464$6536_Y - attribute \src "libresoc.v:142465.18-142465.97" - wire $gt$libresoc.v:142465$6537_Y - attribute \src "libresoc.v:142466.19-142466.99" - wire $gt$libresoc.v:142466$6538_Y - attribute \src "libresoc.v:142467.19-142467.99" - wire $gt$libresoc.v:142467$6539_Y - attribute \src "libresoc.v:142468.19-142468.99" - wire $gt$libresoc.v:142468$6540_Y - attribute \src "libresoc.v:142469.19-142469.99" - wire $gt$libresoc.v:142469$6541_Y - attribute \src "libresoc.v:142470.19-142470.99" - wire $gt$libresoc.v:142470$6542_Y - attribute \src "libresoc.v:142471.18-142471.97" - wire $gt$libresoc.v:142471$6543_Y - attribute \src "libresoc.v:142472.18-142472.97" - wire $gt$libresoc.v:142472$6544_Y - attribute \src "libresoc.v:142473.18-142473.97" - wire $gt$libresoc.v:142473$6545_Y - attribute \src "libresoc.v:142474.17-142474.96" - wire $gt$libresoc.v:142474$6546_Y - attribute \src "libresoc.v:142475.18-142475.97" - wire $gt$libresoc.v:142475$6547_Y - attribute \src "libresoc.v:142476.18-142476.97" - wire $gt$libresoc.v:142476$6548_Y - attribute \src "libresoc.v:142477.18-142477.97" - wire $gt$libresoc.v:142477$6549_Y - attribute \src "libresoc.v:142478.18-142478.97" - wire $gt$libresoc.v:142478$6550_Y - attribute \src "libresoc.v:142479.18-142479.97" - wire $gt$libresoc.v:142479$6551_Y - attribute \src "libresoc.v:142480.18-142480.97" - wire $gt$libresoc.v:142480$6552_Y - attribute \src "libresoc.v:142481.18-142481.97" - wire $gt$libresoc.v:142481$6553_Y - attribute \src "libresoc.v:142482.18-142482.98" - wire $gt$libresoc.v:142482$6554_Y - attribute \src "libresoc.v:142483.18-142483.98" - wire $gt$libresoc.v:142483$6555_Y - attribute \src "libresoc.v:142484.18-142484.98" - wire $gt$libresoc.v:142484$6556_Y - attribute \src "libresoc.v:142485.17-142485.96" - wire $gt$libresoc.v:142485$6557_Y - attribute \src "libresoc.v:142486.18-142486.98" - wire $gt$libresoc.v:142486$6558_Y - attribute \src "libresoc.v:142487.18-142487.98" - wire $gt$libresoc.v:142487$6559_Y - attribute \src "libresoc.v:142488.18-142488.98" - wire $gt$libresoc.v:142488$6560_Y - attribute \src "libresoc.v:142489.18-142489.98" - wire $gt$libresoc.v:142489$6561_Y - attribute \src "libresoc.v:142490.18-142490.98" - wire $gt$libresoc.v:142490$6562_Y - attribute \src "libresoc.v:142491.18-142491.98" - wire $gt$libresoc.v:142491$6563_Y - attribute \src "libresoc.v:142492.18-142492.98" - wire $gt$libresoc.v:142492$6564_Y - attribute \src "libresoc.v:142493.18-142493.98" - wire $gt$libresoc.v:142493$6565_Y - attribute \src "libresoc.v:142494.18-142494.98" - wire $gt$libresoc.v:142494$6566_Y - attribute \src "libresoc.v:142495.18-142495.98" - wire $gt$libresoc.v:142495$6567_Y - attribute \src "libresoc.v:142496.17-142496.96" - wire $gt$libresoc.v:142496$6568_Y - attribute \src "libresoc.v:142497.18-142497.98" - wire $gt$libresoc.v:142497$6569_Y - attribute \src "libresoc.v:142498.18-142498.98" - wire $gt$libresoc.v:142498$6570_Y - attribute \src "libresoc.v:142499.18-142499.98" - wire $gt$libresoc.v:142499$6571_Y - attribute \src "libresoc.v:142500.18-142500.98" - wire $gt$libresoc.v:142500$6572_Y - attribute \src "libresoc.v:142501.18-142501.98" - wire $gt$libresoc.v:142501$6573_Y - attribute \src "libresoc.v:142502.18-142502.98" - wire $gt$libresoc.v:142502$6574_Y - attribute \src "libresoc.v:142503.18-142503.98" - wire $gt$libresoc.v:142503$6575_Y - attribute \src "libresoc.v:142504.18-142504.98" - wire $gt$libresoc.v:142504$6576_Y - attribute \src "libresoc.v:142505.18-142505.98" - wire $gt$libresoc.v:142505$6577_Y - attribute \src "libresoc.v:142506.18-142506.98" - wire $gt$libresoc.v:142506$6578_Y - attribute \src "libresoc.v:142507.17-142507.96" - wire $gt$libresoc.v:142507$6579_Y - attribute \src "libresoc.v:142508.18-142508.98" - wire $gt$libresoc.v:142508$6580_Y - attribute \src "libresoc.v:142509.18-142509.98" - wire $gt$libresoc.v:142509$6581_Y - attribute \src "libresoc.v:142510.18-142510.98" - wire $gt$libresoc.v:142510$6582_Y - attribute \src "libresoc.v:142511.18-142511.98" - wire $gt$libresoc.v:142511$6583_Y - attribute \src "libresoc.v:142512.18-142512.98" - wire $gt$libresoc.v:142512$6584_Y - attribute \src "libresoc.v:142513.18-142513.98" - wire $gt$libresoc.v:142513$6585_Y - attribute \src "libresoc.v:142514.18-142514.98" - wire $gt$libresoc.v:142514$6586_Y - attribute \src "libresoc.v:142515.18-142515.98" - wire $gt$libresoc.v:142515$6587_Y - attribute \src "libresoc.v:142516.18-142516.98" - wire $gt$libresoc.v:142516$6588_Y - attribute \src "libresoc.v:142517.18-142517.98" - wire $gt$libresoc.v:142517$6589_Y + attribute \src "libresoc.v:143334.17-143334.96" + wire $gt$libresoc.v:143334$6510_Y + attribute \src "libresoc.v:143335.18-143335.98" + wire $gt$libresoc.v:143335$6511_Y + attribute \src "libresoc.v:143336.19-143336.99" + wire $gt$libresoc.v:143336$6512_Y + attribute \src "libresoc.v:143337.19-143337.99" + wire $gt$libresoc.v:143337$6513_Y + attribute \src "libresoc.v:143338.19-143338.99" + wire $gt$libresoc.v:143338$6514_Y + attribute \src "libresoc.v:143339.19-143339.99" + wire $gt$libresoc.v:143339$6515_Y + attribute \src "libresoc.v:143340.19-143340.99" + wire $gt$libresoc.v:143340$6516_Y + attribute \src "libresoc.v:143341.19-143341.99" + wire $gt$libresoc.v:143341$6517_Y + attribute \src "libresoc.v:143342.19-143342.99" + wire $gt$libresoc.v:143342$6518_Y + attribute \src "libresoc.v:143343.19-143343.99" + wire $gt$libresoc.v:143343$6519_Y + attribute \src "libresoc.v:143344.19-143344.99" + wire $gt$libresoc.v:143344$6520_Y + attribute \src "libresoc.v:143345.18-143345.97" + wire $gt$libresoc.v:143345$6521_Y + attribute \src "libresoc.v:143346.19-143346.99" + wire $gt$libresoc.v:143346$6522_Y + attribute \src "libresoc.v:143347.19-143347.99" + wire $gt$libresoc.v:143347$6523_Y + attribute \src "libresoc.v:143348.19-143348.99" + wire $gt$libresoc.v:143348$6524_Y + attribute \src "libresoc.v:143349.19-143349.99" + wire $gt$libresoc.v:143349$6525_Y + attribute \src "libresoc.v:143350.19-143350.99" + wire $gt$libresoc.v:143350$6526_Y + attribute \src "libresoc.v:143351.18-143351.97" + wire $gt$libresoc.v:143351$6527_Y + attribute \src "libresoc.v:143352.18-143352.97" + wire $gt$libresoc.v:143352$6528_Y + attribute \src "libresoc.v:143353.18-143353.97" + wire $gt$libresoc.v:143353$6529_Y + attribute \src "libresoc.v:143354.17-143354.96" + wire $gt$libresoc.v:143354$6530_Y + attribute \src "libresoc.v:143355.18-143355.97" + wire $gt$libresoc.v:143355$6531_Y + attribute \src "libresoc.v:143356.18-143356.97" + wire $gt$libresoc.v:143356$6532_Y + attribute \src "libresoc.v:143357.18-143357.97" + wire $gt$libresoc.v:143357$6533_Y + attribute \src "libresoc.v:143358.18-143358.97" + wire $gt$libresoc.v:143358$6534_Y + attribute \src "libresoc.v:143359.18-143359.97" + wire $gt$libresoc.v:143359$6535_Y + attribute \src "libresoc.v:143360.18-143360.97" + wire $gt$libresoc.v:143360$6536_Y + attribute \src "libresoc.v:143361.18-143361.97" + wire $gt$libresoc.v:143361$6537_Y + attribute \src "libresoc.v:143362.18-143362.98" + wire $gt$libresoc.v:143362$6538_Y + attribute \src "libresoc.v:143363.18-143363.98" + wire $gt$libresoc.v:143363$6539_Y + attribute \src "libresoc.v:143364.18-143364.98" + wire $gt$libresoc.v:143364$6540_Y + attribute \src "libresoc.v:143365.17-143365.96" + wire $gt$libresoc.v:143365$6541_Y + attribute \src "libresoc.v:143366.18-143366.98" + wire $gt$libresoc.v:143366$6542_Y + attribute \src "libresoc.v:143367.18-143367.98" + wire $gt$libresoc.v:143367$6543_Y + attribute \src "libresoc.v:143368.18-143368.98" + wire $gt$libresoc.v:143368$6544_Y + attribute \src "libresoc.v:143369.18-143369.98" + wire $gt$libresoc.v:143369$6545_Y + attribute \src "libresoc.v:143370.18-143370.98" + wire $gt$libresoc.v:143370$6546_Y + attribute \src "libresoc.v:143371.18-143371.98" + wire $gt$libresoc.v:143371$6547_Y + attribute \src "libresoc.v:143372.18-143372.98" + wire $gt$libresoc.v:143372$6548_Y + attribute \src "libresoc.v:143373.18-143373.98" + wire $gt$libresoc.v:143373$6549_Y + attribute \src "libresoc.v:143374.18-143374.98" + wire $gt$libresoc.v:143374$6550_Y + attribute \src "libresoc.v:143375.18-143375.98" + wire $gt$libresoc.v:143375$6551_Y + attribute \src "libresoc.v:143376.17-143376.96" + wire $gt$libresoc.v:143376$6552_Y + attribute \src "libresoc.v:143377.18-143377.98" + wire $gt$libresoc.v:143377$6553_Y + attribute \src "libresoc.v:143378.18-143378.98" + wire $gt$libresoc.v:143378$6554_Y + attribute \src "libresoc.v:143379.18-143379.98" + wire $gt$libresoc.v:143379$6555_Y + attribute \src "libresoc.v:143380.18-143380.98" + wire $gt$libresoc.v:143380$6556_Y + attribute \src "libresoc.v:143381.18-143381.98" + wire $gt$libresoc.v:143381$6557_Y + attribute \src "libresoc.v:143382.18-143382.98" + wire $gt$libresoc.v:143382$6558_Y + attribute \src "libresoc.v:143383.18-143383.98" + wire $gt$libresoc.v:143383$6559_Y + attribute \src "libresoc.v:143384.18-143384.98" + wire $gt$libresoc.v:143384$6560_Y + attribute \src "libresoc.v:143385.18-143385.98" + wire $gt$libresoc.v:143385$6561_Y + attribute \src "libresoc.v:143386.18-143386.98" + wire $gt$libresoc.v:143386$6562_Y + attribute \src "libresoc.v:143387.17-143387.96" + wire $gt$libresoc.v:143387$6563_Y + attribute \src "libresoc.v:143388.18-143388.98" + wire $gt$libresoc.v:143388$6564_Y + attribute \src "libresoc.v:143389.18-143389.98" + wire $gt$libresoc.v:143389$6565_Y + attribute \src "libresoc.v:143390.18-143390.98" + wire $gt$libresoc.v:143390$6566_Y + attribute \src "libresoc.v:143391.18-143391.98" + wire $gt$libresoc.v:143391$6567_Y + attribute \src "libresoc.v:143392.18-143392.98" + wire $gt$libresoc.v:143392$6568_Y + attribute \src "libresoc.v:143393.18-143393.98" + wire $gt$libresoc.v:143393$6569_Y + attribute \src "libresoc.v:143394.18-143394.98" + wire $gt$libresoc.v:143394$6570_Y + attribute \src "libresoc.v:143395.18-143395.98" + wire $gt$libresoc.v:143395$6571_Y + attribute \src "libresoc.v:143396.18-143396.98" + wire $gt$libresoc.v:143396$6572_Y + attribute \src "libresoc.v:143397.18-143397.98" + wire $gt$libresoc.v:143397$6573_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" @@ -230199,14 +230619,14 @@ module \left_mask wire \$97 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$99 - attribute \src "libresoc.v:142320.7-142320.15" + attribute \src "libresoc.v:143200.7-143200.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:20" wire width 64 output 1 \mask attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:19" wire width 7 input 2 \shift attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142454$6526 + cell $gt $gt$libresoc.v:143334$6510 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230214,10 +230634,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'100 - connect \Y $gt$libresoc.v:142454$6526_Y + connect \Y $gt$libresoc.v:143334$6510_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142455$6527 + cell $gt $gt$libresoc.v:143335$6511 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230225,10 +230645,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110001 - connect \Y $gt$libresoc.v:142455$6527_Y + connect \Y $gt$libresoc.v:143335$6511_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142456$6528 + cell $gt $gt$libresoc.v:143336$6512 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230236,10 +230656,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110010 - connect \Y $gt$libresoc.v:142456$6528_Y + connect \Y $gt$libresoc.v:143336$6512_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142457$6529 + cell $gt $gt$libresoc.v:143337$6513 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230247,10 +230667,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110011 - connect \Y $gt$libresoc.v:142457$6529_Y + connect \Y $gt$libresoc.v:143337$6513_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142458$6530 + cell $gt $gt$libresoc.v:143338$6514 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230258,10 +230678,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110100 - connect \Y $gt$libresoc.v:142458$6530_Y + connect \Y $gt$libresoc.v:143338$6514_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142459$6531 + cell $gt $gt$libresoc.v:143339$6515 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230269,10 +230689,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110101 - connect \Y $gt$libresoc.v:142459$6531_Y + connect \Y $gt$libresoc.v:143339$6515_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142460$6532 + cell $gt $gt$libresoc.v:143340$6516 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230280,10 +230700,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110110 - connect \Y $gt$libresoc.v:142460$6532_Y + connect \Y $gt$libresoc.v:143340$6516_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142461$6533 + cell $gt $gt$libresoc.v:143341$6517 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230291,10 +230711,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110111 - connect \Y $gt$libresoc.v:142461$6533_Y + connect \Y $gt$libresoc.v:143341$6517_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142462$6534 + cell $gt $gt$libresoc.v:143342$6518 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230302,10 +230722,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111000 - connect \Y $gt$libresoc.v:142462$6534_Y + connect \Y $gt$libresoc.v:143342$6518_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142463$6535 + cell $gt $gt$libresoc.v:143343$6519 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230313,10 +230733,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111001 - connect \Y $gt$libresoc.v:142463$6535_Y + connect \Y $gt$libresoc.v:143343$6519_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142464$6536 + cell $gt $gt$libresoc.v:143344$6520 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230324,10 +230744,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111010 - connect \Y $gt$libresoc.v:142464$6536_Y + connect \Y $gt$libresoc.v:143344$6520_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142465$6537 + cell $gt $gt$libresoc.v:143345$6521 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230335,10 +230755,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'101 - connect \Y $gt$libresoc.v:142465$6537_Y + connect \Y $gt$libresoc.v:143345$6521_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142466$6538 + cell $gt $gt$libresoc.v:143346$6522 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230346,10 +230766,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111011 - connect \Y $gt$libresoc.v:142466$6538_Y + connect \Y $gt$libresoc.v:143346$6522_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142467$6539 + cell $gt $gt$libresoc.v:143347$6523 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230357,10 +230777,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111100 - connect \Y $gt$libresoc.v:142467$6539_Y + connect \Y $gt$libresoc.v:143347$6523_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142468$6540 + cell $gt $gt$libresoc.v:143348$6524 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230368,10 +230788,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111101 - connect \Y $gt$libresoc.v:142468$6540_Y + connect \Y $gt$libresoc.v:143348$6524_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142469$6541 + cell $gt $gt$libresoc.v:143349$6525 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230379,10 +230799,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111110 - connect \Y $gt$libresoc.v:142469$6541_Y + connect \Y $gt$libresoc.v:143349$6525_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142470$6542 + cell $gt $gt$libresoc.v:143350$6526 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230390,10 +230810,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111111 - connect \Y $gt$libresoc.v:142470$6542_Y + connect \Y $gt$libresoc.v:143350$6526_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142471$6543 + cell $gt $gt$libresoc.v:143351$6527 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230401,10 +230821,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'110 - connect \Y $gt$libresoc.v:142471$6543_Y + connect \Y $gt$libresoc.v:143351$6527_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142472$6544 + cell $gt $gt$libresoc.v:143352$6528 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230412,10 +230832,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'111 - connect \Y $gt$libresoc.v:142472$6544_Y + connect \Y $gt$libresoc.v:143352$6528_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142473$6545 + cell $gt $gt$libresoc.v:143353$6529 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230423,10 +230843,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1000 - connect \Y $gt$libresoc.v:142473$6545_Y + connect \Y $gt$libresoc.v:143353$6529_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142474$6546 + cell $gt $gt$libresoc.v:143354$6530 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230434,10 +230854,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 1'0 - connect \Y $gt$libresoc.v:142474$6546_Y + connect \Y $gt$libresoc.v:143354$6530_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142475$6547 + cell $gt $gt$libresoc.v:143355$6531 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230445,10 +230865,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1001 - connect \Y $gt$libresoc.v:142475$6547_Y + connect \Y $gt$libresoc.v:143355$6531_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142476$6548 + cell $gt $gt$libresoc.v:143356$6532 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230456,10 +230876,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1010 - connect \Y $gt$libresoc.v:142476$6548_Y + connect \Y $gt$libresoc.v:143356$6532_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142477$6549 + cell $gt $gt$libresoc.v:143357$6533 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230467,10 +230887,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1011 - connect \Y $gt$libresoc.v:142477$6549_Y + connect \Y $gt$libresoc.v:143357$6533_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142478$6550 + cell $gt $gt$libresoc.v:143358$6534 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230478,10 +230898,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1100 - connect \Y $gt$libresoc.v:142478$6550_Y + connect \Y $gt$libresoc.v:143358$6534_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142479$6551 + cell $gt $gt$libresoc.v:143359$6535 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230489,10 +230909,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1101 - connect \Y $gt$libresoc.v:142479$6551_Y + connect \Y $gt$libresoc.v:143359$6535_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142480$6552 + cell $gt $gt$libresoc.v:143360$6536 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230500,10 +230920,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1110 - connect \Y $gt$libresoc.v:142480$6552_Y + connect \Y $gt$libresoc.v:143360$6536_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142481$6553 + cell $gt $gt$libresoc.v:143361$6537 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230511,10 +230931,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1111 - connect \Y $gt$libresoc.v:142481$6553_Y + connect \Y $gt$libresoc.v:143361$6537_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142482$6554 + cell $gt $gt$libresoc.v:143362$6538 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230522,10 +230942,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10000 - connect \Y $gt$libresoc.v:142482$6554_Y + connect \Y $gt$libresoc.v:143362$6538_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142483$6555 + cell $gt $gt$libresoc.v:143363$6539 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230533,10 +230953,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10001 - connect \Y $gt$libresoc.v:142483$6555_Y + connect \Y $gt$libresoc.v:143363$6539_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142484$6556 + cell $gt $gt$libresoc.v:143364$6540 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230544,10 +230964,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10010 - connect \Y $gt$libresoc.v:142484$6556_Y + connect \Y $gt$libresoc.v:143364$6540_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142485$6557 + cell $gt $gt$libresoc.v:143365$6541 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230555,10 +230975,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 1'1 - connect \Y $gt$libresoc.v:142485$6557_Y + connect \Y $gt$libresoc.v:143365$6541_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142486$6558 + cell $gt $gt$libresoc.v:143366$6542 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230566,10 +230986,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10011 - connect \Y $gt$libresoc.v:142486$6558_Y + connect \Y $gt$libresoc.v:143366$6542_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142487$6559 + cell $gt $gt$libresoc.v:143367$6543 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230577,10 +230997,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10100 - connect \Y $gt$libresoc.v:142487$6559_Y + connect \Y $gt$libresoc.v:143367$6543_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142488$6560 + cell $gt $gt$libresoc.v:143368$6544 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230588,10 +231008,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10101 - connect \Y $gt$libresoc.v:142488$6560_Y + connect \Y $gt$libresoc.v:143368$6544_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142489$6561 + cell $gt $gt$libresoc.v:143369$6545 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230599,10 +231019,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10110 - connect \Y $gt$libresoc.v:142489$6561_Y + connect \Y $gt$libresoc.v:143369$6545_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142490$6562 + cell $gt $gt$libresoc.v:143370$6546 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230610,10 +231030,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10111 - connect \Y $gt$libresoc.v:142490$6562_Y + connect \Y $gt$libresoc.v:143370$6546_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142491$6563 + cell $gt $gt$libresoc.v:143371$6547 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230621,10 +231041,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11000 - connect \Y $gt$libresoc.v:142491$6563_Y + connect \Y $gt$libresoc.v:143371$6547_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142492$6564 + cell $gt $gt$libresoc.v:143372$6548 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230632,10 +231052,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11001 - connect \Y $gt$libresoc.v:142492$6564_Y + connect \Y $gt$libresoc.v:143372$6548_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142493$6565 + cell $gt $gt$libresoc.v:143373$6549 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230643,10 +231063,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11010 - connect \Y $gt$libresoc.v:142493$6565_Y + connect \Y $gt$libresoc.v:143373$6549_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142494$6566 + cell $gt $gt$libresoc.v:143374$6550 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230654,10 +231074,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11011 - connect \Y $gt$libresoc.v:142494$6566_Y + connect \Y $gt$libresoc.v:143374$6550_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142495$6567 + cell $gt $gt$libresoc.v:143375$6551 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230665,10 +231085,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11100 - connect \Y $gt$libresoc.v:142495$6567_Y + connect \Y $gt$libresoc.v:143375$6551_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142496$6568 + cell $gt $gt$libresoc.v:143376$6552 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230676,10 +231096,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 2'10 - connect \Y $gt$libresoc.v:142496$6568_Y + connect \Y $gt$libresoc.v:143376$6552_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142497$6569 + cell $gt $gt$libresoc.v:143377$6553 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230687,10 +231107,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11101 - connect \Y $gt$libresoc.v:142497$6569_Y + connect \Y $gt$libresoc.v:143377$6553_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142498$6570 + cell $gt $gt$libresoc.v:143378$6554 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230698,10 +231118,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11110 - connect \Y $gt$libresoc.v:142498$6570_Y + connect \Y $gt$libresoc.v:143378$6554_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142499$6571 + cell $gt $gt$libresoc.v:143379$6555 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230709,10 +231129,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11111 - connect \Y $gt$libresoc.v:142499$6571_Y + connect \Y $gt$libresoc.v:143379$6555_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142500$6572 + cell $gt $gt$libresoc.v:143380$6556 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230720,10 +231140,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100000 - connect \Y $gt$libresoc.v:142500$6572_Y + connect \Y $gt$libresoc.v:143380$6556_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142501$6573 + cell $gt $gt$libresoc.v:143381$6557 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230731,10 +231151,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100001 - connect \Y $gt$libresoc.v:142501$6573_Y + connect \Y $gt$libresoc.v:143381$6557_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142502$6574 + cell $gt $gt$libresoc.v:143382$6558 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230742,10 +231162,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100010 - connect \Y $gt$libresoc.v:142502$6574_Y + connect \Y $gt$libresoc.v:143382$6558_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142503$6575 + cell $gt $gt$libresoc.v:143383$6559 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230753,10 +231173,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100011 - connect \Y $gt$libresoc.v:142503$6575_Y + connect \Y $gt$libresoc.v:143383$6559_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142504$6576 + cell $gt $gt$libresoc.v:143384$6560 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230764,10 +231184,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100100 - connect \Y $gt$libresoc.v:142504$6576_Y + connect \Y $gt$libresoc.v:143384$6560_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142505$6577 + cell $gt $gt$libresoc.v:143385$6561 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230775,10 +231195,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100101 - connect \Y $gt$libresoc.v:142505$6577_Y + connect \Y $gt$libresoc.v:143385$6561_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142506$6578 + cell $gt $gt$libresoc.v:143386$6562 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230786,10 +231206,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100110 - connect \Y $gt$libresoc.v:142506$6578_Y + connect \Y $gt$libresoc.v:143386$6562_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142507$6579 + cell $gt $gt$libresoc.v:143387$6563 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230797,10 +231217,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 2'11 - connect \Y $gt$libresoc.v:142507$6579_Y + connect \Y $gt$libresoc.v:143387$6563_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142508$6580 + cell $gt $gt$libresoc.v:143388$6564 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230808,10 +231228,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100111 - connect \Y $gt$libresoc.v:142508$6580_Y + connect \Y $gt$libresoc.v:143388$6564_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142509$6581 + cell $gt $gt$libresoc.v:143389$6565 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230819,10 +231239,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101000 - connect \Y $gt$libresoc.v:142509$6581_Y + connect \Y $gt$libresoc.v:143389$6565_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142510$6582 + cell $gt $gt$libresoc.v:143390$6566 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230830,10 +231250,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101001 - connect \Y $gt$libresoc.v:142510$6582_Y + connect \Y $gt$libresoc.v:143390$6566_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142511$6583 + cell $gt $gt$libresoc.v:143391$6567 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230841,10 +231261,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101010 - connect \Y $gt$libresoc.v:142511$6583_Y + connect \Y $gt$libresoc.v:143391$6567_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142512$6584 + cell $gt $gt$libresoc.v:143392$6568 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230852,10 +231272,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101011 - connect \Y $gt$libresoc.v:142512$6584_Y + connect \Y $gt$libresoc.v:143392$6568_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142513$6585 + cell $gt $gt$libresoc.v:143393$6569 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230863,10 +231283,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101100 - connect \Y $gt$libresoc.v:142513$6585_Y + connect \Y $gt$libresoc.v:143393$6569_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142514$6586 + cell $gt $gt$libresoc.v:143394$6570 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230874,10 +231294,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101101 - connect \Y $gt$libresoc.v:142514$6586_Y + connect \Y $gt$libresoc.v:143394$6570_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142515$6587 + cell $gt $gt$libresoc.v:143395$6571 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230885,10 +231305,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101110 - connect \Y $gt$libresoc.v:142515$6587_Y + connect \Y $gt$libresoc.v:143395$6571_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142516$6588 + cell $gt $gt$libresoc.v:143396$6572 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230896,10 +231316,10 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101111 - connect \Y $gt$libresoc.v:142516$6588_Y + connect \Y $gt$libresoc.v:143396$6572_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:142517$6589 + cell $gt $gt$libresoc.v:143397$6573 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -230907,18 +231327,18 @@ module \left_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110000 - connect \Y $gt$libresoc.v:142517$6589_Y + connect \Y $gt$libresoc.v:143397$6573_Y end - attribute \src "libresoc.v:142320.7-142320.20" - process $proc$libresoc.v:142320$6591 + attribute \src "libresoc.v:143200.7-143200.20" + process $proc$libresoc.v:143200$6575 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:142518.3-142905.6" - process $proc$libresoc.v:142518$6590 + attribute \src "libresoc.v:143398.3-143785.6" + process $proc$libresoc.v:143398$6574 assign { } { } assign { } { } assign $0\mask[63:0] [0] $1\mask[0:0] @@ -230985,9 +231405,9 @@ module \left_mask assign $0\mask[63:0] [61] $62\mask[61:61] assign $0\mask[63:0] [62] $63\mask[62:62] assign $0\mask[63:0] [63] $64\mask[63:63] - attribute \src "libresoc.v:142519.5-142519.29" + attribute \src "libresoc.v:143399.5-143399.29" switch \initial - attribute \src "libresoc.v:142519.9-142519.17" + attribute \src "libresoc.v:143399.9-143399.17" case 1'1 case end @@ -231570,86 +231990,86 @@ module \left_mask sync always update \mask $0\mask[63:0] end - connect \$9 $gt$libresoc.v:142454$6526_Y - connect \$99 $gt$libresoc.v:142455$6527_Y - connect \$101 $gt$libresoc.v:142456$6528_Y - connect \$103 $gt$libresoc.v:142457$6529_Y - connect \$105 $gt$libresoc.v:142458$6530_Y - connect \$107 $gt$libresoc.v:142459$6531_Y - connect \$109 $gt$libresoc.v:142460$6532_Y - connect \$111 $gt$libresoc.v:142461$6533_Y - connect \$113 $gt$libresoc.v:142462$6534_Y - connect \$115 $gt$libresoc.v:142463$6535_Y - connect \$117 $gt$libresoc.v:142464$6536_Y - connect \$11 $gt$libresoc.v:142465$6537_Y - connect \$119 $gt$libresoc.v:142466$6538_Y - connect \$121 $gt$libresoc.v:142467$6539_Y - connect \$123 $gt$libresoc.v:142468$6540_Y - connect \$125 $gt$libresoc.v:142469$6541_Y - connect \$127 $gt$libresoc.v:142470$6542_Y - connect \$13 $gt$libresoc.v:142471$6543_Y - connect \$15 $gt$libresoc.v:142472$6544_Y - connect \$17 $gt$libresoc.v:142473$6545_Y - connect \$1 $gt$libresoc.v:142474$6546_Y - connect \$19 $gt$libresoc.v:142475$6547_Y - connect \$21 $gt$libresoc.v:142476$6548_Y - connect \$23 $gt$libresoc.v:142477$6549_Y - connect \$25 $gt$libresoc.v:142478$6550_Y - connect \$27 $gt$libresoc.v:142479$6551_Y - connect \$29 $gt$libresoc.v:142480$6552_Y - connect \$31 $gt$libresoc.v:142481$6553_Y - connect \$33 $gt$libresoc.v:142482$6554_Y - connect \$35 $gt$libresoc.v:142483$6555_Y - connect \$37 $gt$libresoc.v:142484$6556_Y - connect \$3 $gt$libresoc.v:142485$6557_Y - connect \$39 $gt$libresoc.v:142486$6558_Y - connect \$41 $gt$libresoc.v:142487$6559_Y - connect \$43 $gt$libresoc.v:142488$6560_Y - connect \$45 $gt$libresoc.v:142489$6561_Y - connect \$47 $gt$libresoc.v:142490$6562_Y - connect \$49 $gt$libresoc.v:142491$6563_Y - connect \$51 $gt$libresoc.v:142492$6564_Y - connect \$53 $gt$libresoc.v:142493$6565_Y - connect \$55 $gt$libresoc.v:142494$6566_Y - connect \$57 $gt$libresoc.v:142495$6567_Y - connect \$5 $gt$libresoc.v:142496$6568_Y - connect \$59 $gt$libresoc.v:142497$6569_Y - connect \$61 $gt$libresoc.v:142498$6570_Y - connect \$63 $gt$libresoc.v:142499$6571_Y - connect \$65 $gt$libresoc.v:142500$6572_Y - connect \$67 $gt$libresoc.v:142501$6573_Y - connect \$69 $gt$libresoc.v:142502$6574_Y - connect \$71 $gt$libresoc.v:142503$6575_Y - connect \$73 $gt$libresoc.v:142504$6576_Y - connect \$75 $gt$libresoc.v:142505$6577_Y - connect \$77 $gt$libresoc.v:142506$6578_Y - connect \$7 $gt$libresoc.v:142507$6579_Y - connect \$79 $gt$libresoc.v:142508$6580_Y - connect \$81 $gt$libresoc.v:142509$6581_Y - connect \$83 $gt$libresoc.v:142510$6582_Y - connect \$85 $gt$libresoc.v:142511$6583_Y - connect \$87 $gt$libresoc.v:142512$6584_Y - connect \$89 $gt$libresoc.v:142513$6585_Y - connect \$91 $gt$libresoc.v:142514$6586_Y - connect \$93 $gt$libresoc.v:142515$6587_Y - connect \$95 $gt$libresoc.v:142516$6588_Y - connect \$97 $gt$libresoc.v:142517$6589_Y + connect \$9 $gt$libresoc.v:143334$6510_Y + connect \$99 $gt$libresoc.v:143335$6511_Y + connect \$101 $gt$libresoc.v:143336$6512_Y + connect \$103 $gt$libresoc.v:143337$6513_Y + connect \$105 $gt$libresoc.v:143338$6514_Y + connect \$107 $gt$libresoc.v:143339$6515_Y + connect \$109 $gt$libresoc.v:143340$6516_Y + connect \$111 $gt$libresoc.v:143341$6517_Y + connect \$113 $gt$libresoc.v:143342$6518_Y + connect \$115 $gt$libresoc.v:143343$6519_Y + connect \$117 $gt$libresoc.v:143344$6520_Y + connect \$11 $gt$libresoc.v:143345$6521_Y + connect \$119 $gt$libresoc.v:143346$6522_Y + connect \$121 $gt$libresoc.v:143347$6523_Y + connect \$123 $gt$libresoc.v:143348$6524_Y + connect \$125 $gt$libresoc.v:143349$6525_Y + connect \$127 $gt$libresoc.v:143350$6526_Y + connect \$13 $gt$libresoc.v:143351$6527_Y + connect \$15 $gt$libresoc.v:143352$6528_Y + connect \$17 $gt$libresoc.v:143353$6529_Y + connect \$1 $gt$libresoc.v:143354$6530_Y + connect \$19 $gt$libresoc.v:143355$6531_Y + connect \$21 $gt$libresoc.v:143356$6532_Y + connect \$23 $gt$libresoc.v:143357$6533_Y + connect \$25 $gt$libresoc.v:143358$6534_Y + connect \$27 $gt$libresoc.v:143359$6535_Y + connect \$29 $gt$libresoc.v:143360$6536_Y + connect \$31 $gt$libresoc.v:143361$6537_Y + connect \$33 $gt$libresoc.v:143362$6538_Y + connect \$35 $gt$libresoc.v:143363$6539_Y + connect \$37 $gt$libresoc.v:143364$6540_Y + connect \$3 $gt$libresoc.v:143365$6541_Y + connect \$39 $gt$libresoc.v:143366$6542_Y + connect \$41 $gt$libresoc.v:143367$6543_Y + connect \$43 $gt$libresoc.v:143368$6544_Y + connect \$45 $gt$libresoc.v:143369$6545_Y + connect \$47 $gt$libresoc.v:143370$6546_Y + connect \$49 $gt$libresoc.v:143371$6547_Y + connect \$51 $gt$libresoc.v:143372$6548_Y + connect \$53 $gt$libresoc.v:143373$6549_Y + connect \$55 $gt$libresoc.v:143374$6550_Y + connect \$57 $gt$libresoc.v:143375$6551_Y + connect \$5 $gt$libresoc.v:143376$6552_Y + connect \$59 $gt$libresoc.v:143377$6553_Y + connect \$61 $gt$libresoc.v:143378$6554_Y + connect \$63 $gt$libresoc.v:143379$6555_Y + connect \$65 $gt$libresoc.v:143380$6556_Y + connect \$67 $gt$libresoc.v:143381$6557_Y + connect \$69 $gt$libresoc.v:143382$6558_Y + connect \$71 $gt$libresoc.v:143383$6559_Y + connect \$73 $gt$libresoc.v:143384$6560_Y + connect \$75 $gt$libresoc.v:143385$6561_Y + connect \$77 $gt$libresoc.v:143386$6562_Y + connect \$7 $gt$libresoc.v:143387$6563_Y + connect \$79 $gt$libresoc.v:143388$6564_Y + connect \$81 $gt$libresoc.v:143389$6565_Y + connect \$83 $gt$libresoc.v:143390$6566_Y + connect \$85 $gt$libresoc.v:143391$6567_Y + connect \$87 $gt$libresoc.v:143392$6568_Y + connect \$89 $gt$libresoc.v:143393$6569_Y + connect \$91 $gt$libresoc.v:143394$6570_Y + connect \$93 $gt$libresoc.v:143395$6571_Y + connect \$95 $gt$libresoc.v:143396$6572_Y + connect \$97 $gt$libresoc.v:143397$6573_Y end -attribute \src "libresoc.v:142910.1-142939.10" +attribute \src "libresoc.v:143790.1-143819.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.lenexp" attribute \generator "nMigen" module \lenexp - attribute \src "libresoc.v:142934.17-142934.101" - wire width 64 $extend$libresoc.v:142934$6595_Y - attribute \src "libresoc.v:142934.17-142934.101" - wire width 64 $pos$libresoc.v:142934$6596_Y - attribute \src "libresoc.v:142931.17-142931.111" - wire width 20 $sshl$libresoc.v:142931$6592_Y - attribute \src "libresoc.v:142933.17-142933.113" - wire width 32 $sshl$libresoc.v:142933$6594_Y - attribute \src "libresoc.v:142932.17-142932.107" - wire width 21 $sub$libresoc.v:142932$6593_Y + attribute \src "libresoc.v:143814.17-143814.101" + wire width 64 $extend$libresoc.v:143814$6579_Y + attribute \src "libresoc.v:143814.17-143814.101" + wire width 64 $pos$libresoc.v:143814$6580_Y + attribute \src "libresoc.v:143811.17-143811.111" + wire width 20 $sshl$libresoc.v:143811$6576_Y + attribute \src "libresoc.v:143813.17-143813.113" + wire width 32 $sshl$libresoc.v:143813$6578_Y + attribute \src "libresoc.v:143812.17-143812.107" + wire width 21 $sub$libresoc.v:143812$6577_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" wire width 21 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" @@ -231671,23 +232091,23 @@ module \lenexp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:134" wire width 176 output 3 \rexp_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - cell $pos $extend$libresoc.v:142934$6595 + cell $pos $extend$libresoc.v:143814$6579 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \$7 - connect \Y $extend$libresoc.v:142934$6595_Y + connect \Y $extend$libresoc.v:143814$6579_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - cell $pos $pos$libresoc.v:142934$6596 + cell $pos $pos$libresoc.v:143814$6580 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:142934$6595_Y - connect \Y $pos$libresoc.v:142934$6596_Y + connect \A $extend$libresoc.v:143814$6579_Y + connect \Y $pos$libresoc.v:143814$6580_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - cell $sshl $sshl$libresoc.v:142931$6592 + cell $sshl $sshl$libresoc.v:143811$6576 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -231695,10 +232115,10 @@ module \lenexp parameter \Y_WIDTH 20 connect \A 5'00001 connect \B \len_i - connect \Y $sshl$libresoc.v:142931$6592_Y + connect \Y $sshl$libresoc.v:143811$6576_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - cell $sshl $sshl$libresoc.v:142933$6594 + cell $sshl $sshl$libresoc.v:143813$6578 parameter \A_SIGNED 0 parameter \A_WIDTH 17 parameter \B_SIGNED 0 @@ -231706,10 +232126,10 @@ module \lenexp parameter \Y_WIDTH 32 connect \A \binlen connect \B \addr_i - connect \Y $sshl$libresoc.v:142933$6594_Y + connect \Y $sshl$libresoc.v:143813$6578_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - cell $sub $sub$libresoc.v:142932$6593 + cell $sub $sub$libresoc.v:143812$6577 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \B_SIGNED 0 @@ -231717,48 +232137,48 @@ module \lenexp parameter \Y_WIDTH 21 connect \A \$2 connect \B 1'1 - connect \Y $sub$libresoc.v:142932$6593_Y + connect \Y $sub$libresoc.v:143812$6577_Y end - connect \$2 $sshl$libresoc.v:142931$6592_Y - connect \$4 $sub$libresoc.v:142932$6593_Y - connect \$7 $sshl$libresoc.v:142933$6594_Y - connect \$6 $pos$libresoc.v:142934$6596_Y + connect \$2 $sshl$libresoc.v:143811$6576_Y + connect \$4 $sub$libresoc.v:143812$6577_Y + connect \$7 $sshl$libresoc.v:143813$6578_Y + connect \$6 $pos$libresoc.v:143814$6580_Y connect \$1 \$4 connect \rexp_o { \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21:20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20:19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19:18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18:17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17:16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16:15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15:14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14:13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13:12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12:11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11:10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10:9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9:8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8:7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7:6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6:5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5:4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4:3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3:2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2:1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1:0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] } connect \lexp_o \$6 connect \binlen \$4 [16:0] end -attribute \src "libresoc.v:142943.1-143001.10" +attribute \src "libresoc.v:143823.1-143881.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.lod_l" attribute \generator "nMigen" module \lod_l - attribute \src "libresoc.v:142944.7-142944.20" + attribute \src "libresoc.v:143824.7-143824.20" wire $0\initial[0:0] - attribute \src "libresoc.v:142989.3-142997.6" - wire $0\q_int$next[0:0]$6607 - attribute \src "libresoc.v:142987.3-142988.27" + attribute \src "libresoc.v:143869.3-143877.6" + wire $0\q_int$next[0:0]$6591 + attribute \src "libresoc.v:143867.3-143868.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:142989.3-142997.6" - wire $1\q_int$next[0:0]$6608 - attribute \src "libresoc.v:142966.7-142966.19" + attribute \src "libresoc.v:143869.3-143877.6" + wire $1\q_int$next[0:0]$6592 + attribute \src "libresoc.v:143846.7-143846.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:142979.17-142979.96" - wire $and$libresoc.v:142979$6597_Y - attribute \src "libresoc.v:142984.17-142984.96" - wire $and$libresoc.v:142984$6602_Y - attribute \src "libresoc.v:142981.18-142981.93" - wire $not$libresoc.v:142981$6599_Y - attribute \src "libresoc.v:142983.17-142983.92" - wire $not$libresoc.v:142983$6601_Y - attribute \src "libresoc.v:142986.17-142986.92" - wire $not$libresoc.v:142986$6604_Y - attribute \src "libresoc.v:142980.18-142980.98" - wire $or$libresoc.v:142980$6598_Y - attribute \src "libresoc.v:142982.18-142982.99" - wire $or$libresoc.v:142982$6600_Y - attribute \src "libresoc.v:142985.17-142985.97" - wire $or$libresoc.v:142985$6603_Y + attribute \src "libresoc.v:143859.17-143859.96" + wire $and$libresoc.v:143859$6581_Y + attribute \src "libresoc.v:143864.17-143864.96" + wire $and$libresoc.v:143864$6586_Y + attribute \src "libresoc.v:143861.18-143861.93" + wire $not$libresoc.v:143861$6583_Y + attribute \src "libresoc.v:143863.17-143863.92" + wire $not$libresoc.v:143863$6585_Y + attribute \src "libresoc.v:143866.17-143866.92" + wire $not$libresoc.v:143866$6588_Y + attribute \src "libresoc.v:143860.18-143860.98" + wire $or$libresoc.v:143860$6582_Y + attribute \src "libresoc.v:143862.18-143862.99" + wire $or$libresoc.v:143862$6584_Y + attribute \src "libresoc.v:143865.17-143865.97" + wire $or$libresoc.v:143865$6587_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -231775,11 +232195,11 @@ module \lod_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:142944.7-142944.15" + attribute \src "libresoc.v:143824.7-143824.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -231796,7 +232216,7 @@ module \lod_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_lod attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:142979$6597 + cell $and $and$libresoc.v:143859$6581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231804,10 +232224,10 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:142979$6597_Y + connect \Y $and$libresoc.v:143859$6581_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:142984$6602 + cell $and $and$libresoc.v:143864$6586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231815,34 +232235,34 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:142984$6602_Y + connect \Y $and$libresoc.v:143864$6586_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:142981$6599 + cell $not $not$libresoc.v:143861$6583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_lod - connect \Y $not$libresoc.v:142981$6599_Y + connect \Y $not$libresoc.v:143861$6583_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:142983$6601 + cell $not $not$libresoc.v:143863$6585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_lod - connect \Y $not$libresoc.v:142983$6601_Y + connect \Y $not$libresoc.v:143863$6585_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:142986$6604 + cell $not $not$libresoc.v:143866$6588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_lod - connect \Y $not$libresoc.v:142986$6604_Y + connect \Y $not$libresoc.v:143866$6588_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:142980$6598 + cell $or $or$libresoc.v:143860$6582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231850,10 +232270,10 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_lod - connect \Y $or$libresoc.v:142980$6598_Y + connect \Y $or$libresoc.v:143860$6582_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:142982$6600 + cell $or $or$libresoc.v:143862$6584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231861,10 +232281,10 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \q_lod connect \B \q_int - connect \Y $or$libresoc.v:142982$6600_Y + connect \Y $or$libresoc.v:143862$6584_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:142985$6603 + cell $or $or$libresoc.v:143865$6587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -231872,39 +232292,39 @@ module \lod_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_lod - connect \Y $or$libresoc.v:142985$6603_Y + connect \Y $or$libresoc.v:143865$6587_Y end - attribute \src "libresoc.v:142944.7-142944.20" - process $proc$libresoc.v:142944$6609 + attribute \src "libresoc.v:143824.7-143824.20" + process $proc$libresoc.v:143824$6593 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:142966.7-142966.19" - process $proc$libresoc.v:142966$6610 + attribute \src "libresoc.v:143846.7-143846.19" + process $proc$libresoc.v:143846$6594 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:142987.3-142988.27" - process $proc$libresoc.v:142987$6605 + attribute \src "libresoc.v:143867.3-143868.27" + process $proc$libresoc.v:143867$6589 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:142989.3-142997.6" - process $proc$libresoc.v:142989$6606 + attribute \src "libresoc.v:143869.3-143877.6" + process $proc$libresoc.v:143869$6590 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$6607 $1\q_int$next[0:0]$6608 - attribute \src "libresoc.v:142990.5-142990.29" + assign $0\q_int$next[0:0]$6591 $1\q_int$next[0:0]$6592 + attribute \src "libresoc.v:143870.5-143870.29" switch \initial - attribute \src "libresoc.v:142990.9-142990.17" + attribute \src "libresoc.v:143870.9-143870.17" case 1'1 case end @@ -231913,494 +232333,494 @@ module \lod_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$6608 1'0 + assign $1\q_int$next[0:0]$6592 1'0 case - assign $1\q_int$next[0:0]$6608 \$5 + assign $1\q_int$next[0:0]$6592 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$6607 + update \q_int$next $0\q_int$next[0:0]$6591 end - connect \$9 $and$libresoc.v:142979$6597_Y - connect \$11 $or$libresoc.v:142980$6598_Y - connect \$13 $not$libresoc.v:142981$6599_Y - connect \$15 $or$libresoc.v:142982$6600_Y - connect \$1 $not$libresoc.v:142983$6601_Y - connect \$3 $and$libresoc.v:142984$6602_Y - connect \$5 $or$libresoc.v:142985$6603_Y - connect \$7 $not$libresoc.v:142986$6604_Y + connect \$9 $and$libresoc.v:143859$6581_Y + connect \$11 $or$libresoc.v:143860$6582_Y + connect \$13 $not$libresoc.v:143861$6583_Y + connect \$15 $or$libresoc.v:143862$6584_Y + connect \$1 $not$libresoc.v:143863$6585_Y + connect \$3 $and$libresoc.v:143864$6586_Y + connect \$5 $or$libresoc.v:143865$6587_Y + connect \$7 $not$libresoc.v:143866$6588_Y connect \qlq_lod \$15 connect \qn_lod \$13 connect \q_lod \$11 end -attribute \src "libresoc.v:143005.1-144125.10" +attribute \src "libresoc.v:143885.1-145005.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0" attribute \generator "nMigen" module \logical0 - attribute \src "libresoc.v:143750.3-143751.24" + attribute \src "libresoc.v:144630.3-144631.24" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:143748.3-143749.44" + attribute \src "libresoc.v:144628.3-144629.44" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:144055.3-144063.6" - wire $0\alu_l_r_alu$next[0:0]$6811 - attribute \src "libresoc.v:143672.3-143673.39" + attribute \src "libresoc.v:144935.3-144943.6" + wire $0\alu_l_r_alu$next[0:0]$6795 + attribute \src "libresoc.v:144552.3-144553.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:143933.3-143971.6" - wire width 4 $0\alu_logical0_logical_op__data_len$next[3:0]$6740 - attribute \src "libresoc.v:143722.3-143723.83" + attribute \src "libresoc.v:144813.3-144851.6" + wire width 4 $0\alu_logical0_logical_op__data_len$next[3:0]$6724 + attribute \src "libresoc.v:144602.3-144603.83" wire width 4 $0\alu_logical0_logical_op__data_len[3:0] - attribute \src "libresoc.v:143933.3-143971.6" - wire width 14 $0\alu_logical0_logical_op__fn_unit$next[13:0]$6741 - attribute \src "libresoc.v:143692.3-143693.81" + attribute \src "libresoc.v:144813.3-144851.6" + wire width 14 $0\alu_logical0_logical_op__fn_unit$next[13:0]$6725 + attribute \src "libresoc.v:144572.3-144573.81" wire width 14 $0\alu_logical0_logical_op__fn_unit[13:0] - attribute \src "libresoc.v:143933.3-143971.6" - wire width 64 $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6742 - attribute \src "libresoc.v:143694.3-143695.95" + attribute \src "libresoc.v:144813.3-144851.6" + wire width 64 $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6726 + attribute \src "libresoc.v:144574.3-144575.95" wire width 64 $0\alu_logical0_logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:143933.3-143971.6" - wire $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6743 - attribute \src "libresoc.v:143696.3-143697.91" + attribute \src "libresoc.v:144813.3-144851.6" + wire $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6727 + attribute \src "libresoc.v:144576.3-144577.91" wire $0\alu_logical0_logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:143933.3-143971.6" - wire width 2 $0\alu_logical0_logical_op__input_carry$next[1:0]$6744 - attribute \src "libresoc.v:143710.3-143711.89" + attribute \src "libresoc.v:144813.3-144851.6" + wire width 2 $0\alu_logical0_logical_op__input_carry$next[1:0]$6728 + attribute \src "libresoc.v:144590.3-144591.89" wire width 2 $0\alu_logical0_logical_op__input_carry[1:0] - attribute \src "libresoc.v:143933.3-143971.6" - wire width 32 $0\alu_logical0_logical_op__insn$next[31:0]$6745 - attribute \src "libresoc.v:143724.3-143725.75" + attribute \src "libresoc.v:144813.3-144851.6" + wire width 32 $0\alu_logical0_logical_op__insn$next[31:0]$6729 + attribute \src "libresoc.v:144604.3-144605.75" wire width 32 $0\alu_logical0_logical_op__insn[31:0] - attribute \src "libresoc.v:143933.3-143971.6" - wire width 7 $0\alu_logical0_logical_op__insn_type$next[6:0]$6746 - attribute \src "libresoc.v:143690.3-143691.85" + attribute \src "libresoc.v:144813.3-144851.6" + wire width 7 $0\alu_logical0_logical_op__insn_type$next[6:0]$6730 + attribute \src "libresoc.v:144570.3-144571.85" wire width 7 $0\alu_logical0_logical_op__insn_type[6:0] - attribute \src "libresoc.v:143933.3-143971.6" - wire $0\alu_logical0_logical_op__invert_in$next[0:0]$6747 - attribute \src "libresoc.v:143706.3-143707.85" + attribute \src "libresoc.v:144813.3-144851.6" + wire $0\alu_logical0_logical_op__invert_in$next[0:0]$6731 + attribute \src "libresoc.v:144586.3-144587.85" wire $0\alu_logical0_logical_op__invert_in[0:0] - attribute \src "libresoc.v:143933.3-143971.6" - wire $0\alu_logical0_logical_op__invert_out$next[0:0]$6748 - attribute \src "libresoc.v:143712.3-143713.87" + attribute \src "libresoc.v:144813.3-144851.6" + wire $0\alu_logical0_logical_op__invert_out$next[0:0]$6732 + attribute \src "libresoc.v:144592.3-144593.87" wire $0\alu_logical0_logical_op__invert_out[0:0] - attribute \src "libresoc.v:143933.3-143971.6" - wire $0\alu_logical0_logical_op__is_32bit$next[0:0]$6749 - attribute \src "libresoc.v:143718.3-143719.83" + attribute \src "libresoc.v:144813.3-144851.6" + wire $0\alu_logical0_logical_op__is_32bit$next[0:0]$6733 + attribute \src "libresoc.v:144598.3-144599.83" wire $0\alu_logical0_logical_op__is_32bit[0:0] - attribute \src "libresoc.v:143933.3-143971.6" - wire $0\alu_logical0_logical_op__is_signed$next[0:0]$6750 - attribute \src "libresoc.v:143720.3-143721.85" + attribute \src "libresoc.v:144813.3-144851.6" + wire $0\alu_logical0_logical_op__is_signed$next[0:0]$6734 + attribute \src "libresoc.v:144600.3-144601.85" wire $0\alu_logical0_logical_op__is_signed[0:0] - attribute \src "libresoc.v:143933.3-143971.6" - wire $0\alu_logical0_logical_op__oe__oe$next[0:0]$6751 - attribute \src "libresoc.v:143702.3-143703.79" + attribute \src "libresoc.v:144813.3-144851.6" + wire $0\alu_logical0_logical_op__oe__oe$next[0:0]$6735 + attribute \src "libresoc.v:144582.3-144583.79" wire $0\alu_logical0_logical_op__oe__oe[0:0] - attribute \src "libresoc.v:143933.3-143971.6" - wire $0\alu_logical0_logical_op__oe__ok$next[0:0]$6752 - attribute \src "libresoc.v:143704.3-143705.79" + attribute \src "libresoc.v:144813.3-144851.6" + wire $0\alu_logical0_logical_op__oe__ok$next[0:0]$6736 + attribute \src "libresoc.v:144584.3-144585.79" wire $0\alu_logical0_logical_op__oe__ok[0:0] - attribute \src "libresoc.v:143933.3-143971.6" - wire $0\alu_logical0_logical_op__output_carry$next[0:0]$6753 - attribute \src "libresoc.v:143716.3-143717.91" + attribute \src "libresoc.v:144813.3-144851.6" + wire $0\alu_logical0_logical_op__output_carry$next[0:0]$6737 + attribute \src "libresoc.v:144596.3-144597.91" wire $0\alu_logical0_logical_op__output_carry[0:0] - attribute \src "libresoc.v:143933.3-143971.6" - wire $0\alu_logical0_logical_op__rc__ok$next[0:0]$6754 - attribute \src "libresoc.v:143700.3-143701.79" + attribute \src "libresoc.v:144813.3-144851.6" + wire $0\alu_logical0_logical_op__rc__ok$next[0:0]$6738 + attribute \src "libresoc.v:144580.3-144581.79" wire $0\alu_logical0_logical_op__rc__ok[0:0] - attribute \src "libresoc.v:143933.3-143971.6" - wire $0\alu_logical0_logical_op__rc__rc$next[0:0]$6755 - attribute \src "libresoc.v:143698.3-143699.79" + attribute \src "libresoc.v:144813.3-144851.6" + wire $0\alu_logical0_logical_op__rc__rc$next[0:0]$6739 + attribute \src "libresoc.v:144578.3-144579.79" wire $0\alu_logical0_logical_op__rc__rc[0:0] - attribute \src "libresoc.v:143933.3-143971.6" - wire $0\alu_logical0_logical_op__write_cr0$next[0:0]$6756 - attribute \src "libresoc.v:143714.3-143715.85" + attribute \src "libresoc.v:144813.3-144851.6" + wire $0\alu_logical0_logical_op__write_cr0$next[0:0]$6740 + attribute \src "libresoc.v:144594.3-144595.85" wire $0\alu_logical0_logical_op__write_cr0[0:0] - attribute \src "libresoc.v:143933.3-143971.6" - wire $0\alu_logical0_logical_op__zero_a$next[0:0]$6757 - attribute \src "libresoc.v:143708.3-143709.79" + attribute \src "libresoc.v:144813.3-144851.6" + wire $0\alu_logical0_logical_op__zero_a$next[0:0]$6741 + attribute \src "libresoc.v:144588.3-144589.79" wire $0\alu_logical0_logical_op__zero_a[0:0] - attribute \src "libresoc.v:144046.3-144054.6" - wire $0\alui_l_r_alui$next[0:0]$6808 - attribute \src "libresoc.v:143674.3-143675.43" + attribute \src "libresoc.v:144926.3-144934.6" + wire $0\alui_l_r_alui$next[0:0]$6792 + attribute \src "libresoc.v:144554.3-144555.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:143972.3-143993.6" - wire width 64 $0\data_r0__o$next[63:0]$6783 - attribute \src "libresoc.v:143686.3-143687.37" + attribute \src "libresoc.v:144852.3-144873.6" + wire width 64 $0\data_r0__o$next[63:0]$6767 + attribute \src "libresoc.v:144566.3-144567.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:143972.3-143993.6" - wire $0\data_r0__o_ok$next[0:0]$6784 - attribute \src "libresoc.v:143688.3-143689.43" + attribute \src "libresoc.v:144852.3-144873.6" + wire $0\data_r0__o_ok$next[0:0]$6768 + attribute \src "libresoc.v:144568.3-144569.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:143994.3-144015.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$6791 - attribute \src "libresoc.v:143682.3-143683.43" + attribute \src "libresoc.v:144874.3-144895.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$6775 + attribute \src "libresoc.v:144562.3-144563.43" wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:143994.3-144015.6" - wire $0\data_r1__cr_a_ok$next[0:0]$6792 - attribute \src "libresoc.v:143684.3-143685.49" + attribute \src "libresoc.v:144874.3-144895.6" + wire $0\data_r1__cr_a_ok$next[0:0]$6776 + attribute \src "libresoc.v:144564.3-144565.49" wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:144064.3-144073.6" + attribute \src "libresoc.v:144944.3-144953.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:144074.3-144083.6" + attribute \src "libresoc.v:144954.3-144963.6" wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:143006.7-143006.20" + attribute \src "libresoc.v:143886.7-143886.20" wire $0\initial[0:0] - attribute \src "libresoc.v:143888.3-143896.6" - wire $0\opc_l_r_opc$next[0:0]$6725 - attribute \src "libresoc.v:143734.3-143735.39" + attribute \src "libresoc.v:144768.3-144776.6" + wire $0\opc_l_r_opc$next[0:0]$6709 + attribute \src "libresoc.v:144614.3-144615.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:143879.3-143887.6" - wire $0\opc_l_s_opc$next[0:0]$6722 - attribute \src "libresoc.v:143736.3-143737.39" + attribute \src "libresoc.v:144759.3-144767.6" + wire $0\opc_l_s_opc$next[0:0]$6706 + attribute \src "libresoc.v:144616.3-144617.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:144084.3-144092.6" - wire width 2 $0\prev_wr_go$next[1:0]$6816 - attribute \src "libresoc.v:143746.3-143747.37" + attribute \src "libresoc.v:144964.3-144972.6" + wire width 2 $0\prev_wr_go$next[1:0]$6800 + attribute \src "libresoc.v:144626.3-144627.37" wire width 2 $0\prev_wr_go[1:0] - attribute \src "libresoc.v:143833.3-143842.6" + attribute \src "libresoc.v:144713.3-144722.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:143924.3-143932.6" - wire width 2 $0\req_l_r_req$next[1:0]$6737 - attribute \src "libresoc.v:143726.3-143727.39" + attribute \src "libresoc.v:144804.3-144812.6" + wire width 2 $0\req_l_r_req$next[1:0]$6721 + attribute \src "libresoc.v:144606.3-144607.39" wire width 2 $0\req_l_r_req[1:0] - attribute \src "libresoc.v:143915.3-143923.6" - wire width 2 $0\req_l_s_req$next[1:0]$6734 - attribute \src "libresoc.v:143728.3-143729.39" + attribute \src "libresoc.v:144795.3-144803.6" + wire width 2 $0\req_l_s_req$next[1:0]$6718 + attribute \src "libresoc.v:144608.3-144609.39" wire width 2 $0\req_l_s_req[1:0] - attribute \src "libresoc.v:143852.3-143860.6" - wire $0\rok_l_r_rdok$next[0:0]$6713 - attribute \src "libresoc.v:143742.3-143743.41" + attribute \src "libresoc.v:144732.3-144740.6" + wire $0\rok_l_r_rdok$next[0:0]$6697 + attribute \src "libresoc.v:144622.3-144623.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:143843.3-143851.6" - wire $0\rok_l_s_rdok$next[0:0]$6710 - attribute \src "libresoc.v:143744.3-143745.41" + attribute \src "libresoc.v:144723.3-144731.6" + wire $0\rok_l_s_rdok$next[0:0]$6694 + attribute \src "libresoc.v:144624.3-144625.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:143870.3-143878.6" - wire $0\rst_l_r_rst$next[0:0]$6719 - attribute \src "libresoc.v:143738.3-143739.39" + attribute \src "libresoc.v:144750.3-144758.6" + wire $0\rst_l_r_rst$next[0:0]$6703 + attribute \src "libresoc.v:144618.3-144619.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:143861.3-143869.6" - wire $0\rst_l_s_rst$next[0:0]$6716 - attribute \src "libresoc.v:143740.3-143741.39" + attribute \src "libresoc.v:144741.3-144749.6" + wire $0\rst_l_s_rst$next[0:0]$6700 + attribute \src "libresoc.v:144620.3-144621.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:143906.3-143914.6" - wire width 3 $0\src_l_r_src$next[2:0]$6731 - attribute \src "libresoc.v:143730.3-143731.39" + attribute \src "libresoc.v:144786.3-144794.6" + wire width 3 $0\src_l_r_src$next[2:0]$6715 + attribute \src "libresoc.v:144610.3-144611.39" wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:143897.3-143905.6" - wire width 3 $0\src_l_s_src$next[2:0]$6728 - attribute \src "libresoc.v:143732.3-143733.39" + attribute \src "libresoc.v:144777.3-144785.6" + wire width 3 $0\src_l_s_src$next[2:0]$6712 + attribute \src "libresoc.v:144612.3-144613.39" wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:144016.3-144025.6" - wire width 64 $0\src_r0$next[63:0]$6799 - attribute \src "libresoc.v:143680.3-143681.29" + attribute \src "libresoc.v:144896.3-144905.6" + wire width 64 $0\src_r0$next[63:0]$6783 + attribute \src "libresoc.v:144560.3-144561.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:144026.3-144035.6" - wire width 64 $0\src_r1$next[63:0]$6802 - attribute \src "libresoc.v:143678.3-143679.29" + attribute \src "libresoc.v:144906.3-144915.6" + wire width 64 $0\src_r1$next[63:0]$6786 + attribute \src "libresoc.v:144558.3-144559.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:144036.3-144045.6" - wire $0\src_r2$next[0:0]$6805 - attribute \src "libresoc.v:143676.3-143677.29" + attribute \src "libresoc.v:144916.3-144925.6" + wire $0\src_r2$next[0:0]$6789 + attribute \src "libresoc.v:144556.3-144557.29" wire $0\src_r2[0:0] - attribute \src "libresoc.v:143124.7-143124.24" + attribute \src "libresoc.v:144004.7-144004.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:143134.7-143134.26" + attribute \src "libresoc.v:144014.7-144014.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:144055.3-144063.6" - wire $1\alu_l_r_alu$next[0:0]$6812 - attribute \src "libresoc.v:143142.7-143142.25" + attribute \src "libresoc.v:144935.3-144943.6" + wire $1\alu_l_r_alu$next[0:0]$6796 + attribute \src "libresoc.v:144022.7-144022.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:143933.3-143971.6" - wire width 4 $1\alu_logical0_logical_op__data_len$next[3:0]$6758 - attribute \src "libresoc.v:143150.13-143150.53" + attribute \src "libresoc.v:144813.3-144851.6" + wire width 4 $1\alu_logical0_logical_op__data_len$next[3:0]$6742 + attribute \src "libresoc.v:144030.13-144030.53" wire width 4 $1\alu_logical0_logical_op__data_len[3:0] - attribute \src "libresoc.v:143933.3-143971.6" - wire width 14 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6759 - attribute \src "libresoc.v:143169.14-143169.57" + attribute \src "libresoc.v:144813.3-144851.6" + wire width 14 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6743 + attribute \src "libresoc.v:144049.14-144049.57" wire width 14 $1\alu_logical0_logical_op__fn_unit[13:0] - attribute \src "libresoc.v:143933.3-143971.6" - wire width 64 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6760 - attribute \src "libresoc.v:143173.14-143173.76" + attribute \src "libresoc.v:144813.3-144851.6" + wire width 64 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6744 + attribute \src "libresoc.v:144053.14-144053.76" wire width 64 $1\alu_logical0_logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:143933.3-143971.6" - wire $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6761 - attribute \src "libresoc.v:143177.7-143177.51" + attribute \src "libresoc.v:144813.3-144851.6" + wire $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6745 + attribute \src "libresoc.v:144057.7-144057.51" wire $1\alu_logical0_logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:143933.3-143971.6" - wire width 2 $1\alu_logical0_logical_op__input_carry$next[1:0]$6762 - attribute \src "libresoc.v:143185.13-143185.56" + attribute \src "libresoc.v:144813.3-144851.6" + wire width 2 $1\alu_logical0_logical_op__input_carry$next[1:0]$6746 + attribute \src "libresoc.v:144065.13-144065.56" wire width 2 $1\alu_logical0_logical_op__input_carry[1:0] - attribute \src "libresoc.v:143933.3-143971.6" - wire width 32 $1\alu_logical0_logical_op__insn$next[31:0]$6763 - attribute \src "libresoc.v:143189.14-143189.51" + attribute \src "libresoc.v:144813.3-144851.6" + wire width 32 $1\alu_logical0_logical_op__insn$next[31:0]$6747 + attribute \src "libresoc.v:144069.14-144069.51" wire width 32 $1\alu_logical0_logical_op__insn[31:0] - attribute \src "libresoc.v:143933.3-143971.6" - wire width 7 $1\alu_logical0_logical_op__insn_type$next[6:0]$6764 - attribute \src "libresoc.v:143268.13-143268.55" + attribute \src "libresoc.v:144813.3-144851.6" + wire width 7 $1\alu_logical0_logical_op__insn_type$next[6:0]$6748 + attribute \src "libresoc.v:144148.13-144148.55" wire width 7 $1\alu_logical0_logical_op__insn_type[6:0] - attribute \src "libresoc.v:143933.3-143971.6" - wire $1\alu_logical0_logical_op__invert_in$next[0:0]$6765 - attribute \src "libresoc.v:143272.7-143272.48" + attribute \src "libresoc.v:144813.3-144851.6" + wire $1\alu_logical0_logical_op__invert_in$next[0:0]$6749 + attribute \src "libresoc.v:144152.7-144152.48" wire $1\alu_logical0_logical_op__invert_in[0:0] - attribute \src "libresoc.v:143933.3-143971.6" - wire $1\alu_logical0_logical_op__invert_out$next[0:0]$6766 - attribute \src "libresoc.v:143276.7-143276.49" + attribute \src "libresoc.v:144813.3-144851.6" + wire $1\alu_logical0_logical_op__invert_out$next[0:0]$6750 + attribute \src "libresoc.v:144156.7-144156.49" wire $1\alu_logical0_logical_op__invert_out[0:0] - attribute \src "libresoc.v:143933.3-143971.6" - wire $1\alu_logical0_logical_op__is_32bit$next[0:0]$6767 - attribute \src "libresoc.v:143280.7-143280.47" + attribute \src "libresoc.v:144813.3-144851.6" + wire $1\alu_logical0_logical_op__is_32bit$next[0:0]$6751 + attribute \src "libresoc.v:144160.7-144160.47" wire $1\alu_logical0_logical_op__is_32bit[0:0] - attribute \src "libresoc.v:143933.3-143971.6" - wire $1\alu_logical0_logical_op__is_signed$next[0:0]$6768 - attribute \src "libresoc.v:143284.7-143284.48" + attribute \src "libresoc.v:144813.3-144851.6" + wire $1\alu_logical0_logical_op__is_signed$next[0:0]$6752 + attribute \src "libresoc.v:144164.7-144164.48" wire $1\alu_logical0_logical_op__is_signed[0:0] - attribute \src "libresoc.v:143933.3-143971.6" - wire $1\alu_logical0_logical_op__oe__oe$next[0:0]$6769 - attribute \src "libresoc.v:143288.7-143288.45" + attribute \src "libresoc.v:144813.3-144851.6" + wire $1\alu_logical0_logical_op__oe__oe$next[0:0]$6753 + attribute \src "libresoc.v:144168.7-144168.45" wire $1\alu_logical0_logical_op__oe__oe[0:0] - attribute \src "libresoc.v:143933.3-143971.6" - wire $1\alu_logical0_logical_op__oe__ok$next[0:0]$6770 - attribute \src "libresoc.v:143292.7-143292.45" + attribute \src "libresoc.v:144813.3-144851.6" + wire $1\alu_logical0_logical_op__oe__ok$next[0:0]$6754 + attribute \src "libresoc.v:144172.7-144172.45" wire $1\alu_logical0_logical_op__oe__ok[0:0] - attribute \src "libresoc.v:143933.3-143971.6" - wire $1\alu_logical0_logical_op__output_carry$next[0:0]$6771 - attribute \src "libresoc.v:143296.7-143296.51" + attribute \src "libresoc.v:144813.3-144851.6" + wire $1\alu_logical0_logical_op__output_carry$next[0:0]$6755 + attribute \src "libresoc.v:144176.7-144176.51" wire $1\alu_logical0_logical_op__output_carry[0:0] - attribute \src "libresoc.v:143933.3-143971.6" - wire $1\alu_logical0_logical_op__rc__ok$next[0:0]$6772 - attribute \src "libresoc.v:143300.7-143300.45" + attribute \src "libresoc.v:144813.3-144851.6" + wire $1\alu_logical0_logical_op__rc__ok$next[0:0]$6756 + attribute \src "libresoc.v:144180.7-144180.45" wire $1\alu_logical0_logical_op__rc__ok[0:0] - attribute \src "libresoc.v:143933.3-143971.6" - wire $1\alu_logical0_logical_op__rc__rc$next[0:0]$6773 - attribute \src "libresoc.v:143304.7-143304.45" + attribute \src "libresoc.v:144813.3-144851.6" + wire $1\alu_logical0_logical_op__rc__rc$next[0:0]$6757 + attribute \src "libresoc.v:144184.7-144184.45" wire $1\alu_logical0_logical_op__rc__rc[0:0] - attribute \src "libresoc.v:143933.3-143971.6" - wire $1\alu_logical0_logical_op__write_cr0$next[0:0]$6774 - attribute \src "libresoc.v:143308.7-143308.48" + attribute \src "libresoc.v:144813.3-144851.6" + wire $1\alu_logical0_logical_op__write_cr0$next[0:0]$6758 + attribute \src "libresoc.v:144188.7-144188.48" wire $1\alu_logical0_logical_op__write_cr0[0:0] - attribute \src "libresoc.v:143933.3-143971.6" - wire $1\alu_logical0_logical_op__zero_a$next[0:0]$6775 - attribute \src "libresoc.v:143312.7-143312.45" + attribute \src "libresoc.v:144813.3-144851.6" + wire $1\alu_logical0_logical_op__zero_a$next[0:0]$6759 + attribute \src "libresoc.v:144192.7-144192.45" wire $1\alu_logical0_logical_op__zero_a[0:0] - attribute \src "libresoc.v:144046.3-144054.6" - wire $1\alui_l_r_alui$next[0:0]$6809 - attribute \src "libresoc.v:143338.7-143338.27" + attribute \src "libresoc.v:144926.3-144934.6" + wire $1\alui_l_r_alui$next[0:0]$6793 + attribute \src "libresoc.v:144218.7-144218.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:143972.3-143993.6" - wire width 64 $1\data_r0__o$next[63:0]$6785 - attribute \src "libresoc.v:143372.14-143372.47" + attribute \src "libresoc.v:144852.3-144873.6" + wire width 64 $1\data_r0__o$next[63:0]$6769 + attribute \src "libresoc.v:144252.14-144252.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:143972.3-143993.6" - wire $1\data_r0__o_ok$next[0:0]$6786 - attribute \src "libresoc.v:143376.7-143376.27" + attribute \src "libresoc.v:144852.3-144873.6" + wire $1\data_r0__o_ok$next[0:0]$6770 + attribute \src "libresoc.v:144256.7-144256.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:143994.3-144015.6" - wire width 4 $1\data_r1__cr_a$next[3:0]$6793 - attribute \src "libresoc.v:143380.13-143380.33" + attribute \src "libresoc.v:144874.3-144895.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$6777 + attribute \src "libresoc.v:144260.13-144260.33" wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:143994.3-144015.6" - wire $1\data_r1__cr_a_ok$next[0:0]$6794 - attribute \src "libresoc.v:143384.7-143384.30" + attribute \src "libresoc.v:144874.3-144895.6" + wire $1\data_r1__cr_a_ok$next[0:0]$6778 + attribute \src "libresoc.v:144264.7-144264.30" wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:144064.3-144073.6" + attribute \src "libresoc.v:144944.3-144953.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:144074.3-144083.6" + attribute \src "libresoc.v:144954.3-144963.6" wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:143888.3-143896.6" - wire $1\opc_l_r_opc$next[0:0]$6726 - attribute \src "libresoc.v:143398.7-143398.25" + attribute \src "libresoc.v:144768.3-144776.6" + wire $1\opc_l_r_opc$next[0:0]$6710 + attribute \src "libresoc.v:144278.7-144278.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:143879.3-143887.6" - wire $1\opc_l_s_opc$next[0:0]$6723 - attribute \src "libresoc.v:143402.7-143402.25" + attribute \src "libresoc.v:144759.3-144767.6" + wire $1\opc_l_s_opc$next[0:0]$6707 + attribute \src "libresoc.v:144282.7-144282.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:144084.3-144092.6" - wire width 2 $1\prev_wr_go$next[1:0]$6817 - attribute \src "libresoc.v:143536.13-143536.30" + attribute \src "libresoc.v:144964.3-144972.6" + wire width 2 $1\prev_wr_go$next[1:0]$6801 + attribute \src "libresoc.v:144416.13-144416.30" wire width 2 $1\prev_wr_go[1:0] - attribute \src "libresoc.v:143833.3-143842.6" + attribute \src "libresoc.v:144713.3-144722.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:143924.3-143932.6" - wire width 2 $1\req_l_r_req$next[1:0]$6738 - attribute \src "libresoc.v:143544.13-143544.31" + attribute \src "libresoc.v:144804.3-144812.6" + wire width 2 $1\req_l_r_req$next[1:0]$6722 + attribute \src "libresoc.v:144424.13-144424.31" wire width 2 $1\req_l_r_req[1:0] - attribute \src "libresoc.v:143915.3-143923.6" - wire width 2 $1\req_l_s_req$next[1:0]$6735 - attribute \src "libresoc.v:143548.13-143548.31" + attribute \src "libresoc.v:144795.3-144803.6" + wire width 2 $1\req_l_s_req$next[1:0]$6719 + attribute \src "libresoc.v:144428.13-144428.31" wire width 2 $1\req_l_s_req[1:0] - attribute \src "libresoc.v:143852.3-143860.6" - wire $1\rok_l_r_rdok$next[0:0]$6714 - attribute \src "libresoc.v:143560.7-143560.26" + attribute \src "libresoc.v:144732.3-144740.6" + wire $1\rok_l_r_rdok$next[0:0]$6698 + attribute \src "libresoc.v:144440.7-144440.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:143843.3-143851.6" - wire $1\rok_l_s_rdok$next[0:0]$6711 - attribute \src "libresoc.v:143564.7-143564.26" + attribute \src "libresoc.v:144723.3-144731.6" + wire $1\rok_l_s_rdok$next[0:0]$6695 + attribute \src "libresoc.v:144444.7-144444.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:143870.3-143878.6" - wire $1\rst_l_r_rst$next[0:0]$6720 - attribute \src "libresoc.v:143568.7-143568.25" + attribute \src "libresoc.v:144750.3-144758.6" + wire $1\rst_l_r_rst$next[0:0]$6704 + attribute \src "libresoc.v:144448.7-144448.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:143861.3-143869.6" - wire $1\rst_l_s_rst$next[0:0]$6717 - attribute \src "libresoc.v:143572.7-143572.25" + attribute \src "libresoc.v:144741.3-144749.6" + wire $1\rst_l_s_rst$next[0:0]$6701 + attribute \src "libresoc.v:144452.7-144452.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:143906.3-143914.6" - wire width 3 $1\src_l_r_src$next[2:0]$6732 - attribute \src "libresoc.v:143586.13-143586.31" + attribute \src "libresoc.v:144786.3-144794.6" + wire width 3 $1\src_l_r_src$next[2:0]$6716 + attribute \src "libresoc.v:144466.13-144466.31" wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:143897.3-143905.6" - wire width 3 $1\src_l_s_src$next[2:0]$6729 - attribute \src "libresoc.v:143590.13-143590.31" + attribute \src "libresoc.v:144777.3-144785.6" + wire width 3 $1\src_l_s_src$next[2:0]$6713 + attribute \src "libresoc.v:144470.13-144470.31" wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:144016.3-144025.6" - wire width 64 $1\src_r0$next[63:0]$6800 - attribute \src "libresoc.v:143598.14-143598.43" + attribute \src "libresoc.v:144896.3-144905.6" + wire width 64 $1\src_r0$next[63:0]$6784 + attribute \src "libresoc.v:144478.14-144478.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:144026.3-144035.6" - wire width 64 $1\src_r1$next[63:0]$6803 - attribute \src "libresoc.v:143602.14-143602.43" + attribute \src "libresoc.v:144906.3-144915.6" + wire width 64 $1\src_r1$next[63:0]$6787 + attribute \src "libresoc.v:144482.14-144482.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:144036.3-144045.6" - wire $1\src_r2$next[0:0]$6806 - attribute \src "libresoc.v:143606.7-143606.20" + attribute \src "libresoc.v:144916.3-144925.6" + wire $1\src_r2$next[0:0]$6790 + attribute \src "libresoc.v:144486.7-144486.20" wire $1\src_r2[0:0] - attribute \src "libresoc.v:143933.3-143971.6" - wire width 64 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6776 - attribute \src "libresoc.v:143933.3-143971.6" - wire $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6777 - attribute \src "libresoc.v:143933.3-143971.6" - wire $2\alu_logical0_logical_op__oe__oe$next[0:0]$6778 - attribute \src "libresoc.v:143933.3-143971.6" - wire $2\alu_logical0_logical_op__oe__ok$next[0:0]$6779 - attribute \src "libresoc.v:143933.3-143971.6" - wire $2\alu_logical0_logical_op__rc__ok$next[0:0]$6780 - attribute \src "libresoc.v:143933.3-143971.6" - wire $2\alu_logical0_logical_op__rc__rc$next[0:0]$6781 - attribute \src "libresoc.v:143972.3-143993.6" - wire width 64 $2\data_r0__o$next[63:0]$6787 - attribute \src "libresoc.v:143972.3-143993.6" - wire $2\data_r0__o_ok$next[0:0]$6788 - attribute \src "libresoc.v:143994.3-144015.6" - wire width 4 $2\data_r1__cr_a$next[3:0]$6795 - attribute \src "libresoc.v:143994.3-144015.6" - wire $2\data_r1__cr_a_ok$next[0:0]$6796 - attribute \src "libresoc.v:143972.3-143993.6" - wire $3\data_r0__o_ok$next[0:0]$6789 - attribute \src "libresoc.v:143994.3-144015.6" - wire $3\data_r1__cr_a_ok$next[0:0]$6797 - attribute \src "libresoc.v:143615.17-143615.109" - wire $and$libresoc.v:143615$6611_Y - attribute \src "libresoc.v:143616.18-143616.130" - wire width 3 $and$libresoc.v:143616$6612_Y - attribute \src "libresoc.v:143618.19-143618.114" - wire width 3 $and$libresoc.v:143618$6614_Y - attribute \src "libresoc.v:143619.19-143619.125" - wire $and$libresoc.v:143619$6615_Y - attribute \src "libresoc.v:143620.19-143620.125" - wire $and$libresoc.v:143620$6616_Y - attribute \src "libresoc.v:143621.19-143621.133" - wire width 2 $and$libresoc.v:143621$6617_Y - attribute \src "libresoc.v:143622.19-143622.121" - wire width 2 $and$libresoc.v:143622$6618_Y - attribute \src "libresoc.v:143623.19-143623.127" - wire $and$libresoc.v:143623$6619_Y - attribute \src "libresoc.v:143624.19-143624.127" - wire $and$libresoc.v:143624$6620_Y - attribute \src "libresoc.v:143626.18-143626.98" - wire $and$libresoc.v:143626$6622_Y - attribute \src "libresoc.v:143628.18-143628.100" - wire $and$libresoc.v:143628$6624_Y - attribute \src "libresoc.v:143629.17-143629.123" - wire $and$libresoc.v:143629$6625_Y - attribute \src "libresoc.v:143630.18-143630.138" - wire width 2 $and$libresoc.v:143630$6626_Y - attribute \src "libresoc.v:143632.18-143632.119" - wire width 2 $and$libresoc.v:143632$6628_Y - attribute \src "libresoc.v:143635.18-143635.116" - wire $and$libresoc.v:143635$6631_Y - attribute \src "libresoc.v:143640.18-143640.113" - wire $and$libresoc.v:143640$6636_Y - attribute \src "libresoc.v:143641.18-143641.125" - wire width 2 $and$libresoc.v:143641$6637_Y - attribute \src "libresoc.v:143643.18-143643.112" - wire $and$libresoc.v:143643$6639_Y - attribute \src "libresoc.v:143646.18-143646.130" - wire $and$libresoc.v:143646$6642_Y - attribute \src "libresoc.v:143647.18-143647.130" - wire $and$libresoc.v:143647$6643_Y - attribute \src "libresoc.v:143648.18-143648.117" - wire $and$libresoc.v:143648$6644_Y - attribute \src "libresoc.v:143653.18-143653.134" - wire $and$libresoc.v:143653$6649_Y - attribute \src "libresoc.v:143654.18-143654.124" - wire width 2 $and$libresoc.v:143654$6650_Y - attribute \src "libresoc.v:143657.18-143657.116" - wire $and$libresoc.v:143657$6653_Y - attribute \src "libresoc.v:143658.18-143658.119" - wire $and$libresoc.v:143658$6654_Y - attribute \src "libresoc.v:143667.18-143667.138" - wire $and$libresoc.v:143667$6663_Y - attribute \src "libresoc.v:143668.18-143668.136" - wire $and$libresoc.v:143668$6664_Y - attribute \src "libresoc.v:143669.18-143669.149" - wire width 3 $and$libresoc.v:143669$6665_Y - attribute \src "libresoc.v:143642.18-143642.113" - wire $eq$libresoc.v:143642$6638_Y - attribute \src "libresoc.v:143644.18-143644.119" - wire $eq$libresoc.v:143644$6640_Y - attribute \src "libresoc.v:143617.19-143617.115" - wire width 3 $not$libresoc.v:143617$6613_Y - attribute \src "libresoc.v:143625.18-143625.97" - wire $not$libresoc.v:143625$6621_Y - attribute \src "libresoc.v:143627.18-143627.99" - wire $not$libresoc.v:143627$6623_Y - attribute \src "libresoc.v:143631.18-143631.113" - wire width 2 $not$libresoc.v:143631$6627_Y - attribute \src "libresoc.v:143634.18-143634.106" - wire $not$libresoc.v:143634$6630_Y - attribute \src "libresoc.v:143639.18-143639.124" - wire $not$libresoc.v:143639$6635_Y - attribute \src "libresoc.v:143645.17-143645.113" - wire width 3 $not$libresoc.v:143645$6641_Y - attribute \src "libresoc.v:143670.18-143670.133" - wire $not$libresoc.v:143670$6666_Y - attribute \src "libresoc.v:143671.18-143671.139" - wire $not$libresoc.v:143671$6667_Y - attribute \src "libresoc.v:143638.18-143638.112" - wire $or$libresoc.v:143638$6634_Y - attribute \src "libresoc.v:143649.18-143649.122" - wire $or$libresoc.v:143649$6645_Y - attribute \src "libresoc.v:143650.18-143650.124" - wire $or$libresoc.v:143650$6646_Y - attribute \src "libresoc.v:143651.18-143651.142" - wire width 2 $or$libresoc.v:143651$6647_Y - attribute \src "libresoc.v:143652.18-143652.155" - wire width 3 $or$libresoc.v:143652$6648_Y - attribute \src "libresoc.v:143655.18-143655.120" - wire width 2 $or$libresoc.v:143655$6651_Y - attribute \src "libresoc.v:143656.17-143656.117" - wire width 3 $or$libresoc.v:143656$6652_Y - attribute \src "libresoc.v:143662.17-143662.104" - wire $reduce_and$libresoc.v:143662$6658_Y - attribute \src "libresoc.v:143633.18-143633.106" - wire $reduce_or$libresoc.v:143633$6629_Y - attribute \src "libresoc.v:143636.18-143636.113" - wire $reduce_or$libresoc.v:143636$6632_Y - attribute \src "libresoc.v:143637.18-143637.112" - wire $reduce_or$libresoc.v:143637$6633_Y - attribute \src "libresoc.v:143659.18-143659.162" - wire $ternary$libresoc.v:143659$6655_Y - attribute \src "libresoc.v:143660.18-143660.163" - wire width 64 $ternary$libresoc.v:143660$6656_Y - attribute \src "libresoc.v:143661.18-143661.168" - wire $ternary$libresoc.v:143661$6657_Y - attribute \src "libresoc.v:143663.18-143663.188" - wire width 64 $ternary$libresoc.v:143663$6659_Y - attribute \src "libresoc.v:143664.18-143664.115" - wire width 64 $ternary$libresoc.v:143664$6660_Y - attribute \src "libresoc.v:143665.18-143665.125" - wire width 64 $ternary$libresoc.v:143665$6661_Y - attribute \src "libresoc.v:143666.18-143666.118" - wire $ternary$libresoc.v:143666$6662_Y + attribute \src "libresoc.v:144813.3-144851.6" + wire width 64 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6760 + attribute \src "libresoc.v:144813.3-144851.6" + wire $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6761 + attribute \src "libresoc.v:144813.3-144851.6" + wire $2\alu_logical0_logical_op__oe__oe$next[0:0]$6762 + attribute \src "libresoc.v:144813.3-144851.6" + wire $2\alu_logical0_logical_op__oe__ok$next[0:0]$6763 + attribute \src "libresoc.v:144813.3-144851.6" + wire $2\alu_logical0_logical_op__rc__ok$next[0:0]$6764 + attribute \src "libresoc.v:144813.3-144851.6" + wire $2\alu_logical0_logical_op__rc__rc$next[0:0]$6765 + attribute \src "libresoc.v:144852.3-144873.6" + wire width 64 $2\data_r0__o$next[63:0]$6771 + attribute \src "libresoc.v:144852.3-144873.6" + wire $2\data_r0__o_ok$next[0:0]$6772 + attribute \src "libresoc.v:144874.3-144895.6" + wire width 4 $2\data_r1__cr_a$next[3:0]$6779 + attribute \src "libresoc.v:144874.3-144895.6" + wire $2\data_r1__cr_a_ok$next[0:0]$6780 + attribute \src "libresoc.v:144852.3-144873.6" + wire $3\data_r0__o_ok$next[0:0]$6773 + attribute \src "libresoc.v:144874.3-144895.6" + wire $3\data_r1__cr_a_ok$next[0:0]$6781 + attribute \src "libresoc.v:144495.17-144495.109" + wire $and$libresoc.v:144495$6595_Y + attribute \src "libresoc.v:144496.18-144496.130" + wire width 3 $and$libresoc.v:144496$6596_Y + attribute \src "libresoc.v:144498.19-144498.114" + wire width 3 $and$libresoc.v:144498$6598_Y + attribute \src "libresoc.v:144499.19-144499.125" + wire $and$libresoc.v:144499$6599_Y + attribute \src "libresoc.v:144500.19-144500.125" + wire $and$libresoc.v:144500$6600_Y + attribute \src "libresoc.v:144501.19-144501.133" + wire width 2 $and$libresoc.v:144501$6601_Y + attribute \src "libresoc.v:144502.19-144502.121" + wire width 2 $and$libresoc.v:144502$6602_Y + attribute \src "libresoc.v:144503.19-144503.127" + wire $and$libresoc.v:144503$6603_Y + attribute \src "libresoc.v:144504.19-144504.127" + wire $and$libresoc.v:144504$6604_Y + attribute \src "libresoc.v:144506.18-144506.98" + wire $and$libresoc.v:144506$6606_Y + attribute \src "libresoc.v:144508.18-144508.100" + wire $and$libresoc.v:144508$6608_Y + attribute \src "libresoc.v:144509.17-144509.123" + wire $and$libresoc.v:144509$6609_Y + attribute \src "libresoc.v:144510.18-144510.138" + wire width 2 $and$libresoc.v:144510$6610_Y + attribute \src "libresoc.v:144512.18-144512.119" + wire width 2 $and$libresoc.v:144512$6612_Y + attribute \src "libresoc.v:144515.18-144515.116" + wire $and$libresoc.v:144515$6615_Y + attribute \src "libresoc.v:144520.18-144520.113" + wire $and$libresoc.v:144520$6620_Y + attribute \src "libresoc.v:144521.18-144521.125" + wire width 2 $and$libresoc.v:144521$6621_Y + attribute \src "libresoc.v:144523.18-144523.112" + wire $and$libresoc.v:144523$6623_Y + attribute \src "libresoc.v:144526.18-144526.130" + wire $and$libresoc.v:144526$6626_Y + attribute \src "libresoc.v:144527.18-144527.130" + wire $and$libresoc.v:144527$6627_Y + attribute \src "libresoc.v:144528.18-144528.117" + wire $and$libresoc.v:144528$6628_Y + attribute \src "libresoc.v:144533.18-144533.134" + wire $and$libresoc.v:144533$6633_Y + attribute \src "libresoc.v:144534.18-144534.124" + wire width 2 $and$libresoc.v:144534$6634_Y + attribute \src "libresoc.v:144537.18-144537.116" + wire $and$libresoc.v:144537$6637_Y + attribute \src "libresoc.v:144538.18-144538.119" + wire $and$libresoc.v:144538$6638_Y + attribute \src "libresoc.v:144547.18-144547.138" + wire $and$libresoc.v:144547$6647_Y + attribute \src "libresoc.v:144548.18-144548.136" + wire $and$libresoc.v:144548$6648_Y + attribute \src "libresoc.v:144549.18-144549.149" + wire width 3 $and$libresoc.v:144549$6649_Y + attribute \src "libresoc.v:144522.18-144522.113" + wire $eq$libresoc.v:144522$6622_Y + attribute \src "libresoc.v:144524.18-144524.119" + wire $eq$libresoc.v:144524$6624_Y + attribute \src "libresoc.v:144497.19-144497.115" + wire width 3 $not$libresoc.v:144497$6597_Y + attribute \src "libresoc.v:144505.18-144505.97" + wire $not$libresoc.v:144505$6605_Y + attribute \src "libresoc.v:144507.18-144507.99" + wire $not$libresoc.v:144507$6607_Y + attribute \src "libresoc.v:144511.18-144511.113" + wire width 2 $not$libresoc.v:144511$6611_Y + attribute \src "libresoc.v:144514.18-144514.106" + wire $not$libresoc.v:144514$6614_Y + attribute \src "libresoc.v:144519.18-144519.124" + wire $not$libresoc.v:144519$6619_Y + attribute \src "libresoc.v:144525.17-144525.113" + wire width 3 $not$libresoc.v:144525$6625_Y + attribute \src "libresoc.v:144550.18-144550.133" + wire $not$libresoc.v:144550$6650_Y + attribute \src "libresoc.v:144551.18-144551.139" + wire $not$libresoc.v:144551$6651_Y + attribute \src "libresoc.v:144518.18-144518.112" + wire $or$libresoc.v:144518$6618_Y + attribute \src "libresoc.v:144529.18-144529.122" + wire $or$libresoc.v:144529$6629_Y + attribute \src "libresoc.v:144530.18-144530.124" + wire $or$libresoc.v:144530$6630_Y + attribute \src "libresoc.v:144531.18-144531.142" + wire width 2 $or$libresoc.v:144531$6631_Y + attribute \src "libresoc.v:144532.18-144532.155" + wire width 3 $or$libresoc.v:144532$6632_Y + attribute \src "libresoc.v:144535.18-144535.120" + wire width 2 $or$libresoc.v:144535$6635_Y + attribute \src "libresoc.v:144536.17-144536.117" + wire width 3 $or$libresoc.v:144536$6636_Y + attribute \src "libresoc.v:144542.17-144542.104" + wire $reduce_and$libresoc.v:144542$6642_Y + attribute \src "libresoc.v:144513.18-144513.106" + wire $reduce_or$libresoc.v:144513$6613_Y + attribute \src "libresoc.v:144516.18-144516.113" + wire $reduce_or$libresoc.v:144516$6616_Y + attribute \src "libresoc.v:144517.18-144517.112" + wire $reduce_or$libresoc.v:144517$6617_Y + attribute \src "libresoc.v:144539.18-144539.162" + wire $ternary$libresoc.v:144539$6639_Y + attribute \src "libresoc.v:144540.18-144540.163" + wire width 64 $ternary$libresoc.v:144540$6640_Y + attribute \src "libresoc.v:144541.18-144541.168" + wire $ternary$libresoc.v:144541$6641_Y + attribute \src "libresoc.v:144543.18-144543.188" + wire width 64 $ternary$libresoc.v:144543$6643_Y + attribute \src "libresoc.v:144544.18-144544.115" + wire width 64 $ternary$libresoc.v:144544$6644_Y + attribute \src "libresoc.v:144545.18-144545.125" + wire width 64 $ternary$libresoc.v:144545$6645_Y + attribute \src "libresoc.v:144546.18-144546.118" + wire $ternary$libresoc.v:144546$6646_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -232737,9 +233157,9 @@ module \logical0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 34 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 32 \cr_a_ok @@ -232785,7 +233205,7 @@ module \logical0 wire width 64 output 31 \dest1_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 4 output 33 \dest2_o - attribute \src "libresoc.v:143006.7-143006.15" + attribute \src "libresoc.v:143886.7-143886.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 28 \o_ok @@ -233010,7 +233430,7 @@ module \logical0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:143615$6611 + cell $and $and$libresoc.v:144495$6595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233018,10 +233438,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$1 connect \B \$3 - connect \Y $and$libresoc.v:143615$6611_Y + connect \Y $and$libresoc.v:144495$6595_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:143616$6612 + cell $and $and$libresoc.v:144496$6596 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -233029,10 +233449,10 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \$93 connect \B { 1'1 \$97 \$95 } - connect \Y $and$libresoc.v:143616$6612_Y + connect \Y $and$libresoc.v:144496$6596_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:143618$6614 + cell $and $and$libresoc.v:144498$6598 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -233040,10 +233460,10 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \$99 connect \B \$101 - connect \Y $and$libresoc.v:143618$6614_Y + connect \Y $and$libresoc.v:144498$6598_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:143619$6615 + cell $and $and$libresoc.v:144499$6599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233051,10 +233471,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:143619$6615_Y + connect \Y $and$libresoc.v:144499$6599_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:143620$6616 + cell $and $and$libresoc.v:144500$6600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233062,10 +233482,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:143620$6616_Y + connect \Y $and$libresoc.v:144500$6600_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:143621$6617 + cell $and $and$libresoc.v:144501$6601 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -233073,10 +233493,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \req_l_q_req connect \B { \$105 \$107 } - connect \Y $and$libresoc.v:143621$6617_Y + connect \Y $and$libresoc.v:144501$6601_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:143622$6618 + cell $and $and$libresoc.v:144502$6602 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -233084,10 +233504,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \$109 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:143622$6618_Y + connect \Y $and$libresoc.v:144502$6602_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:143623$6619 + cell $and $and$libresoc.v:144503$6603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233095,10 +233515,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:143623$6619_Y + connect \Y $and$libresoc.v:144503$6603_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:143624$6620 + cell $and $and$libresoc.v:144504$6604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233106,10 +233526,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:143624$6620_Y + connect \Y $and$libresoc.v:144504$6604_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:143626$6622 + cell $and $and$libresoc.v:144506$6606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233117,10 +233537,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$11 - connect \Y $and$libresoc.v:143626$6622_Y + connect \Y $and$libresoc.v:144506$6606_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:143628$6624 + cell $and $and$libresoc.v:144508$6608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233128,10 +233548,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$15 - connect \Y $and$libresoc.v:143628$6624_Y + connect \Y $and$libresoc.v:144508$6608_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:143629$6625 + cell $and $and$libresoc.v:144509$6609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233139,10 +233559,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:143629$6625_Y + connect \Y $and$libresoc.v:144509$6609_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:143630$6626 + cell $and $and$libresoc.v:144510$6610 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -233150,10 +233570,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:143630$6626_Y + connect \Y $and$libresoc.v:144510$6610_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:143632$6628 + cell $and $and$libresoc.v:144512$6612 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -233161,10 +233581,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \cu_wr__rel_o connect \B \$23 - connect \Y $and$libresoc.v:143632$6628_Y + connect \Y $and$libresoc.v:144512$6612_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:143635$6631 + cell $and $and$libresoc.v:144515$6615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233172,10 +233592,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$21 - connect \Y $and$libresoc.v:143635$6631_Y + connect \Y $and$libresoc.v:144515$6615_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:143640$6636 + cell $and $and$libresoc.v:144520$6620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233183,10 +233603,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$37 - connect \Y $and$libresoc.v:143640$6636_Y + connect \Y $and$libresoc.v:144520$6620_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:143641$6637 + cell $and $and$libresoc.v:144521$6621 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -233194,10 +233614,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:143641$6637_Y + connect \Y $and$libresoc.v:144521$6621_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:143643$6639 + cell $and $and$libresoc.v:144523$6623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233205,10 +233625,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$39 connect \B \$43 - connect \Y $and$libresoc.v:143643$6639_Y + connect \Y $and$libresoc.v:144523$6623_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:143646$6642 + cell $and $and$libresoc.v:144526$6626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233216,10 +233636,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$47 connect \B \alu_logical0_n_ready_i - connect \Y $and$libresoc.v:143646$6642_Y + connect \Y $and$libresoc.v:144526$6626_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:143647$6643 + cell $and $and$libresoc.v:144527$6627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233227,10 +233647,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_logical0_n_valid_o - connect \Y $and$libresoc.v:143647$6643_Y + connect \Y $and$libresoc.v:144527$6627_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:143648$6644 + cell $and $and$libresoc.v:144528$6628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233238,10 +233658,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$51 connect \B \cu_busy_o - connect \Y $and$libresoc.v:143648$6644_Y + connect \Y $and$libresoc.v:144528$6628_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:143653$6649 + cell $and $and$libresoc.v:144533$6633 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233249,10 +233669,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \alu_logical0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:143653$6649_Y + connect \Y $and$libresoc.v:144533$6633_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:143654$6650 + cell $and $and$libresoc.v:144534$6634 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -233260,10 +233680,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:143654$6650_Y + connect \Y $and$libresoc.v:144534$6634_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:143657$6653 + cell $and $and$libresoc.v:144537$6637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233271,10 +233691,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:143657$6653_Y + connect \Y $and$libresoc.v:144537$6637_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:143658$6654 + cell $and $and$libresoc.v:144538$6638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233282,10 +233702,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:143658$6654_Y + connect \Y $and$libresoc.v:144538$6638_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:143667$6663 + cell $and $and$libresoc.v:144547$6647 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233293,10 +233713,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \alu_logical0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:143667$6663_Y + connect \Y $and$libresoc.v:144547$6647_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:143668$6664 + cell $and $and$libresoc.v:144548$6648 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233304,10 +233724,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \alu_logical0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:143668$6664_Y + connect \Y $and$libresoc.v:144548$6648_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:143669$6665 + cell $and $and$libresoc.v:144549$6649 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -233315,10 +233735,10 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:143669$6665_Y + connect \Y $and$libresoc.v:144549$6649_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:143642$6638 + cell $eq $eq$libresoc.v:144522$6622 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -233326,10 +233746,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$41 connect \B 1'0 - connect \Y $eq$libresoc.v:143642$6638_Y + connect \Y $eq$libresoc.v:144522$6622_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:143644$6640 + cell $eq $eq$libresoc.v:144524$6624 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -233337,82 +233757,82 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:143644$6640_Y + connect \Y $eq$libresoc.v:144524$6624_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:143617$6613 + cell $not $not$libresoc.v:144497$6597 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:143617$6613_Y + connect \Y $not$libresoc.v:144497$6597_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:143625$6621 + cell $not $not$libresoc.v:144505$6605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:143625$6621_Y + connect \Y $not$libresoc.v:144505$6605_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:143627$6623 + cell $not $not$libresoc.v:144507$6607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:143627$6623_Y + connect \Y $not$libresoc.v:144507$6607_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:143631$6627 + cell $not $not$libresoc.v:144511$6611 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:143631$6627_Y + connect \Y $not$libresoc.v:144511$6611_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:143634$6630 + cell $not $not$libresoc.v:144514$6614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$22 - connect \Y $not$libresoc.v:143634$6630_Y + connect \Y $not$libresoc.v:144514$6614_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:143639$6635 + cell $not $not$libresoc.v:144519$6619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_logical0_n_ready_i - connect \Y $not$libresoc.v:143639$6635_Y + connect \Y $not$libresoc.v:144519$6619_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:143645$6641 + cell $not $not$libresoc.v:144525$6625 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:143645$6641_Y + connect \Y $not$libresoc.v:144525$6625_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:143670$6666 + cell $not $not$libresoc.v:144550$6650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_logical0_logical_op__zero_a - connect \Y $not$libresoc.v:143670$6666_Y + connect \Y $not$libresoc.v:144550$6650_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:143671$6667 + cell $not $not$libresoc.v:144551$6651 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_logical0_logical_op__imm_data__ok - connect \Y $not$libresoc.v:143671$6667_Y + connect \Y $not$libresoc.v:144551$6651_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:143638$6634 + cell $or $or$libresoc.v:144518$6618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233420,10 +233840,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \$31 connect \B \$33 - connect \Y $or$libresoc.v:143638$6634_Y + connect \Y $or$libresoc.v:144518$6618_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:143649$6645 + cell $or $or$libresoc.v:144529$6629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233431,10 +233851,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:143649$6645_Y + connect \Y $or$libresoc.v:144529$6629_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:143650$6646 + cell $or $or$libresoc.v:144530$6630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -233442,10 +233862,10 @@ module \logical0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:143650$6646_Y + connect \Y $or$libresoc.v:144530$6630_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:143651$6647 + cell $or $or$libresoc.v:144531$6631 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -233453,10 +233873,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:143651$6647_Y + connect \Y $or$libresoc.v:144531$6631_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:143652$6648 + cell $or $or$libresoc.v:144532$6632 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -233464,10 +233884,10 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:143652$6648_Y + connect \Y $or$libresoc.v:144532$6632_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:143655$6651 + cell $or $or$libresoc.v:144535$6635 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -233475,10 +233895,10 @@ module \logical0 parameter \Y_WIDTH 2 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:143655$6651_Y + connect \Y $or$libresoc.v:144535$6635_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:143656$6652 + cell $or $or$libresoc.v:144536$6636 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -233486,98 +233906,98 @@ module \logical0 parameter \Y_WIDTH 3 connect \A \$4 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:143656$6652_Y + connect \Y $or$libresoc.v:144536$6636_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:143662$6658 + cell $reduce_and $reduce_and$libresoc.v:144542$6642 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$6 - connect \Y $reduce_and$libresoc.v:143662$6658_Y + connect \Y $reduce_and$libresoc.v:144542$6642_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:143633$6629 + cell $reduce_or $reduce_or$libresoc.v:144513$6613 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \$25 - connect \Y $reduce_or$libresoc.v:143633$6629_Y + connect \Y $reduce_or$libresoc.v:144513$6613_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:143636$6632 + cell $reduce_or $reduce_or$libresoc.v:144516$6616 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:143636$6632_Y + connect \Y $reduce_or$libresoc.v:144516$6616_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:143637$6633 + cell $reduce_or $reduce_or$libresoc.v:144517$6617 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:143637$6633_Y + connect \Y $reduce_or$libresoc.v:144517$6617_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:143659$6655 + cell $mux $ternary$libresoc.v:144539$6639 parameter \WIDTH 1 connect \A \src_l_q_src [0] connect \B \opc_l_q_opc connect \S \alu_logical0_logical_op__zero_a - connect \Y $ternary$libresoc.v:143659$6655_Y + connect \Y $ternary$libresoc.v:144539$6639_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:143660$6656 + cell $mux $ternary$libresoc.v:144540$6640 parameter \WIDTH 64 connect \A \src1_i connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 connect \S \alu_logical0_logical_op__zero_a - connect \Y $ternary$libresoc.v:143660$6656_Y + connect \Y $ternary$libresoc.v:144540$6640_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:143661$6657 + cell $mux $ternary$libresoc.v:144541$6641 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_logical0_logical_op__imm_data__ok - connect \Y $ternary$libresoc.v:143661$6657_Y + connect \Y $ternary$libresoc.v:144541$6641_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:143663$6659 + cell $mux $ternary$libresoc.v:144543$6643 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_logical0_logical_op__imm_data__data connect \S \alu_logical0_logical_op__imm_data__ok - connect \Y $ternary$libresoc.v:143663$6659_Y + connect \Y $ternary$libresoc.v:144543$6643_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:143664$6660 + cell $mux $ternary$libresoc.v:144544$6644 parameter \WIDTH 64 connect \A \src_r0 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:143664$6660_Y + connect \Y $ternary$libresoc.v:144544$6644_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:143665$6661 + cell $mux $ternary$libresoc.v:144545$6645 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm$80 connect \S \src_sel$77 - connect \Y $ternary$libresoc.v:143665$6661_Y + connect \Y $ternary$libresoc.v:144545$6645_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:143666$6662 + cell $mux $ternary$libresoc.v:144546$6646 parameter \WIDTH 1 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:143666$6662_Y + connect \Y $ternary$libresoc.v:144546$6646_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:143752.14-143758.4" + attribute \src "libresoc.v:144632.14-144638.4" cell \alu_l$61 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -233586,7 +234006,7 @@ module \logical0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:143759.16-143791.4" + attribute \src "libresoc.v:144639.16-144671.4" cell \alu_logical0 \alu_logical0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -233621,7 +234041,7 @@ module \logical0 connect \xer_so \alu_logical0_xer_so end attribute \module_not_derived 1 - attribute \src "libresoc.v:143792.15-143798.4" + attribute \src "libresoc.v:144672.15-144678.4" cell \alui_l$60 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -233630,7 +234050,7 @@ module \logical0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:143799.14-143805.4" + attribute \src "libresoc.v:144679.14-144685.4" cell \opc_l$56 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -233639,7 +234059,7 @@ module \logical0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:143806.14-143812.4" + attribute \src "libresoc.v:144686.14-144692.4" cell \req_l$57 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -233648,7 +234068,7 @@ module \logical0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:143813.14-143819.4" + attribute \src "libresoc.v:144693.14-144699.4" cell \rok_l$59 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -233657,7 +234077,7 @@ module \logical0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:143820.14-143825.4" + attribute \src "libresoc.v:144700.14-144705.4" cell \rst_l$58 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -233665,7 +234085,7 @@ module \logical0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:143826.14-143832.4" + attribute \src "libresoc.v:144706.14-144712.4" cell \src_l$55 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -233673,622 +234093,622 @@ module \logical0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:143006.7-143006.20" - process $proc$libresoc.v:143006$6818 + attribute \src "libresoc.v:143886.7-143886.20" + process $proc$libresoc.v:143886$6802 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:143124.7-143124.24" - process $proc$libresoc.v:143124$6819 + attribute \src "libresoc.v:144004.7-144004.24" + process $proc$libresoc.v:144004$6803 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:143134.7-143134.26" - process $proc$libresoc.v:143134$6820 + attribute \src "libresoc.v:144014.7-144014.26" + process $proc$libresoc.v:144014$6804 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:143142.7-143142.25" - process $proc$libresoc.v:143142$6821 + attribute \src "libresoc.v:144022.7-144022.25" + process $proc$libresoc.v:144022$6805 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:143150.13-143150.53" - process $proc$libresoc.v:143150$6822 + attribute \src "libresoc.v:144030.13-144030.53" + process $proc$libresoc.v:144030$6806 assign { } { } assign $1\alu_logical0_logical_op__data_len[3:0] 4'0000 sync always sync init update \alu_logical0_logical_op__data_len $1\alu_logical0_logical_op__data_len[3:0] end - attribute \src "libresoc.v:143169.14-143169.57" - process $proc$libresoc.v:143169$6823 + attribute \src "libresoc.v:144049.14-144049.57" + process $proc$libresoc.v:144049$6807 assign { } { } assign $1\alu_logical0_logical_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_logical0_logical_op__fn_unit $1\alu_logical0_logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:143173.14-143173.76" - process $proc$libresoc.v:143173$6824 + attribute \src "libresoc.v:144053.14-144053.76" + process $proc$libresoc.v:144053$6808 assign { } { } assign $1\alu_logical0_logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_logical0_logical_op__imm_data__data $1\alu_logical0_logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:143177.7-143177.51" - process $proc$libresoc.v:143177$6825 + attribute \src "libresoc.v:144057.7-144057.51" + process $proc$libresoc.v:144057$6809 assign { } { } assign $1\alu_logical0_logical_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__imm_data__ok $1\alu_logical0_logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:143185.13-143185.56" - process $proc$libresoc.v:143185$6826 + attribute \src "libresoc.v:144065.13-144065.56" + process $proc$libresoc.v:144065$6810 assign { } { } assign $1\alu_logical0_logical_op__input_carry[1:0] 2'00 sync always sync init update \alu_logical0_logical_op__input_carry $1\alu_logical0_logical_op__input_carry[1:0] end - attribute \src "libresoc.v:143189.14-143189.51" - process $proc$libresoc.v:143189$6827 + attribute \src "libresoc.v:144069.14-144069.51" + process $proc$libresoc.v:144069$6811 assign { } { } assign $1\alu_logical0_logical_op__insn[31:0] 0 sync always sync init update \alu_logical0_logical_op__insn $1\alu_logical0_logical_op__insn[31:0] end - attribute \src "libresoc.v:143268.13-143268.55" - process $proc$libresoc.v:143268$6828 + attribute \src "libresoc.v:144148.13-144148.55" + process $proc$libresoc.v:144148$6812 assign { } { } assign $1\alu_logical0_logical_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_logical0_logical_op__insn_type $1\alu_logical0_logical_op__insn_type[6:0] end - attribute \src "libresoc.v:143272.7-143272.48" - process $proc$libresoc.v:143272$6829 + attribute \src "libresoc.v:144152.7-144152.48" + process $proc$libresoc.v:144152$6813 assign { } { } assign $1\alu_logical0_logical_op__invert_in[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__invert_in $1\alu_logical0_logical_op__invert_in[0:0] end - attribute \src "libresoc.v:143276.7-143276.49" - process $proc$libresoc.v:143276$6830 + attribute \src "libresoc.v:144156.7-144156.49" + process $proc$libresoc.v:144156$6814 assign { } { } assign $1\alu_logical0_logical_op__invert_out[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__invert_out $1\alu_logical0_logical_op__invert_out[0:0] end - attribute \src "libresoc.v:143280.7-143280.47" - process $proc$libresoc.v:143280$6831 + attribute \src "libresoc.v:144160.7-144160.47" + process $proc$libresoc.v:144160$6815 assign { } { } assign $1\alu_logical0_logical_op__is_32bit[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__is_32bit $1\alu_logical0_logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:143284.7-143284.48" - process $proc$libresoc.v:143284$6832 + attribute \src "libresoc.v:144164.7-144164.48" + process $proc$libresoc.v:144164$6816 assign { } { } assign $1\alu_logical0_logical_op__is_signed[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__is_signed $1\alu_logical0_logical_op__is_signed[0:0] end - attribute \src "libresoc.v:143288.7-143288.45" - process $proc$libresoc.v:143288$6833 + attribute \src "libresoc.v:144168.7-144168.45" + process $proc$libresoc.v:144168$6817 assign { } { } assign $1\alu_logical0_logical_op__oe__oe[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__oe__oe $1\alu_logical0_logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:143292.7-143292.45" - process $proc$libresoc.v:143292$6834 + attribute \src "libresoc.v:144172.7-144172.45" + process $proc$libresoc.v:144172$6818 assign { } { } assign $1\alu_logical0_logical_op__oe__ok[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__oe__ok $1\alu_logical0_logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:143296.7-143296.51" - process $proc$libresoc.v:143296$6835 + attribute \src "libresoc.v:144176.7-144176.51" + process $proc$libresoc.v:144176$6819 assign { } { } assign $1\alu_logical0_logical_op__output_carry[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__output_carry $1\alu_logical0_logical_op__output_carry[0:0] end - attribute \src "libresoc.v:143300.7-143300.45" - process $proc$libresoc.v:143300$6836 + attribute \src "libresoc.v:144180.7-144180.45" + process $proc$libresoc.v:144180$6820 assign { } { } assign $1\alu_logical0_logical_op__rc__ok[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__rc__ok $1\alu_logical0_logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:143304.7-143304.45" - process $proc$libresoc.v:143304$6837 + attribute \src "libresoc.v:144184.7-144184.45" + process $proc$libresoc.v:144184$6821 assign { } { } assign $1\alu_logical0_logical_op__rc__rc[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__rc__rc $1\alu_logical0_logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:143308.7-143308.48" - process $proc$libresoc.v:143308$6838 + attribute \src "libresoc.v:144188.7-144188.48" + process $proc$libresoc.v:144188$6822 assign { } { } assign $1\alu_logical0_logical_op__write_cr0[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__write_cr0 $1\alu_logical0_logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:143312.7-143312.45" - process $proc$libresoc.v:143312$6839 + attribute \src "libresoc.v:144192.7-144192.45" + process $proc$libresoc.v:144192$6823 assign { } { } assign $1\alu_logical0_logical_op__zero_a[0:0] 1'0 sync always sync init update \alu_logical0_logical_op__zero_a $1\alu_logical0_logical_op__zero_a[0:0] end - attribute \src "libresoc.v:143338.7-143338.27" - process $proc$libresoc.v:143338$6840 + attribute \src "libresoc.v:144218.7-144218.27" + process $proc$libresoc.v:144218$6824 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:143372.14-143372.47" - process $proc$libresoc.v:143372$6841 + attribute \src "libresoc.v:144252.14-144252.47" + process $proc$libresoc.v:144252$6825 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:143376.7-143376.27" - process $proc$libresoc.v:143376$6842 + attribute \src "libresoc.v:144256.7-144256.27" + process $proc$libresoc.v:144256$6826 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:143380.13-143380.33" - process $proc$libresoc.v:143380$6843 + attribute \src "libresoc.v:144260.13-144260.33" + process $proc$libresoc.v:144260$6827 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:143384.7-143384.30" - process $proc$libresoc.v:143384$6844 + attribute \src "libresoc.v:144264.7-144264.30" + process $proc$libresoc.v:144264$6828 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:143398.7-143398.25" - process $proc$libresoc.v:143398$6845 + attribute \src "libresoc.v:144278.7-144278.25" + process $proc$libresoc.v:144278$6829 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:143402.7-143402.25" - process $proc$libresoc.v:143402$6846 + attribute \src "libresoc.v:144282.7-144282.25" + process $proc$libresoc.v:144282$6830 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:143536.13-143536.30" - process $proc$libresoc.v:143536$6847 + attribute \src "libresoc.v:144416.13-144416.30" + process $proc$libresoc.v:144416$6831 assign { } { } assign $1\prev_wr_go[1:0] 2'00 sync always sync init update \prev_wr_go $1\prev_wr_go[1:0] end - attribute \src "libresoc.v:143544.13-143544.31" - process $proc$libresoc.v:143544$6848 + attribute \src "libresoc.v:144424.13-144424.31" + process $proc$libresoc.v:144424$6832 assign { } { } assign $1\req_l_r_req[1:0] 2'11 sync always sync init update \req_l_r_req $1\req_l_r_req[1:0] end - attribute \src "libresoc.v:143548.13-143548.31" - process $proc$libresoc.v:143548$6849 + attribute \src "libresoc.v:144428.13-144428.31" + process $proc$libresoc.v:144428$6833 assign { } { } assign $1\req_l_s_req[1:0] 2'00 sync always sync init update \req_l_s_req $1\req_l_s_req[1:0] end - attribute \src "libresoc.v:143560.7-143560.26" - process $proc$libresoc.v:143560$6850 + attribute \src "libresoc.v:144440.7-144440.26" + process $proc$libresoc.v:144440$6834 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:143564.7-143564.26" - process $proc$libresoc.v:143564$6851 + attribute \src "libresoc.v:144444.7-144444.26" + process $proc$libresoc.v:144444$6835 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:143568.7-143568.25" - process $proc$libresoc.v:143568$6852 + attribute \src "libresoc.v:144448.7-144448.25" + process $proc$libresoc.v:144448$6836 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:143572.7-143572.25" - process $proc$libresoc.v:143572$6853 + attribute \src "libresoc.v:144452.7-144452.25" + process $proc$libresoc.v:144452$6837 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:143586.13-143586.31" - process $proc$libresoc.v:143586$6854 + attribute \src "libresoc.v:144466.13-144466.31" + process $proc$libresoc.v:144466$6838 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end - attribute \src "libresoc.v:143590.13-143590.31" - process $proc$libresoc.v:143590$6855 + attribute \src "libresoc.v:144470.13-144470.31" + process $proc$libresoc.v:144470$6839 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end - attribute \src "libresoc.v:143598.14-143598.43" - process $proc$libresoc.v:143598$6856 + attribute \src "libresoc.v:144478.14-144478.43" + process $proc$libresoc.v:144478$6840 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:143602.14-143602.43" - process $proc$libresoc.v:143602$6857 + attribute \src "libresoc.v:144482.14-144482.43" + process $proc$libresoc.v:144482$6841 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:143606.7-143606.20" - process $proc$libresoc.v:143606$6858 + attribute \src "libresoc.v:144486.7-144486.20" + process $proc$libresoc.v:144486$6842 assign { } { } assign $1\src_r2[0:0] 1'0 sync always sync init update \src_r2 $1\src_r2[0:0] end - attribute \src "libresoc.v:143672.3-143673.39" - process $proc$libresoc.v:143672$6668 + attribute \src "libresoc.v:144552.3-144553.39" + process $proc$libresoc.v:144552$6652 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:143674.3-143675.43" - process $proc$libresoc.v:143674$6669 + attribute \src "libresoc.v:144554.3-144555.43" + process $proc$libresoc.v:144554$6653 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:143676.3-143677.29" - process $proc$libresoc.v:143676$6670 + attribute \src "libresoc.v:144556.3-144557.29" + process $proc$libresoc.v:144556$6654 assign { } { } assign $0\src_r2[0:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[0:0] end - attribute \src "libresoc.v:143678.3-143679.29" - process $proc$libresoc.v:143678$6671 + attribute \src "libresoc.v:144558.3-144559.29" + process $proc$libresoc.v:144558$6655 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:143680.3-143681.29" - process $proc$libresoc.v:143680$6672 + attribute \src "libresoc.v:144560.3-144561.29" + process $proc$libresoc.v:144560$6656 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:143682.3-143683.43" - process $proc$libresoc.v:143682$6673 + attribute \src "libresoc.v:144562.3-144563.43" + process $proc$libresoc.v:144562$6657 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:143684.3-143685.49" - process $proc$libresoc.v:143684$6674 + attribute \src "libresoc.v:144564.3-144565.49" + process $proc$libresoc.v:144564$6658 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:143686.3-143687.37" - process $proc$libresoc.v:143686$6675 + attribute \src "libresoc.v:144566.3-144567.37" + process $proc$libresoc.v:144566$6659 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:143688.3-143689.43" - process $proc$libresoc.v:143688$6676 + attribute \src "libresoc.v:144568.3-144569.43" + process $proc$libresoc.v:144568$6660 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:143690.3-143691.85" - process $proc$libresoc.v:143690$6677 + attribute \src "libresoc.v:144570.3-144571.85" + process $proc$libresoc.v:144570$6661 assign { } { } assign $0\alu_logical0_logical_op__insn_type[6:0] \alu_logical0_logical_op__insn_type$next sync posedge \coresync_clk update \alu_logical0_logical_op__insn_type $0\alu_logical0_logical_op__insn_type[6:0] end - attribute \src "libresoc.v:143692.3-143693.81" - process $proc$libresoc.v:143692$6678 + attribute \src "libresoc.v:144572.3-144573.81" + process $proc$libresoc.v:144572$6662 assign { } { } assign $0\alu_logical0_logical_op__fn_unit[13:0] \alu_logical0_logical_op__fn_unit$next sync posedge \coresync_clk update \alu_logical0_logical_op__fn_unit $0\alu_logical0_logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:143694.3-143695.95" - process $proc$libresoc.v:143694$6679 + attribute \src "libresoc.v:144574.3-144575.95" + process $proc$libresoc.v:144574$6663 assign { } { } assign $0\alu_logical0_logical_op__imm_data__data[63:0] \alu_logical0_logical_op__imm_data__data$next sync posedge \coresync_clk update \alu_logical0_logical_op__imm_data__data $0\alu_logical0_logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:143696.3-143697.91" - process $proc$libresoc.v:143696$6680 + attribute \src "libresoc.v:144576.3-144577.91" + process $proc$libresoc.v:144576$6664 assign { } { } assign $0\alu_logical0_logical_op__imm_data__ok[0:0] \alu_logical0_logical_op__imm_data__ok$next sync posedge \coresync_clk update \alu_logical0_logical_op__imm_data__ok $0\alu_logical0_logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:143698.3-143699.79" - process $proc$libresoc.v:143698$6681 + attribute \src "libresoc.v:144578.3-144579.79" + process $proc$libresoc.v:144578$6665 assign { } { } assign $0\alu_logical0_logical_op__rc__rc[0:0] \alu_logical0_logical_op__rc__rc$next sync posedge \coresync_clk update \alu_logical0_logical_op__rc__rc $0\alu_logical0_logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:143700.3-143701.79" - process $proc$libresoc.v:143700$6682 + attribute \src "libresoc.v:144580.3-144581.79" + process $proc$libresoc.v:144580$6666 assign { } { } assign $0\alu_logical0_logical_op__rc__ok[0:0] \alu_logical0_logical_op__rc__ok$next sync posedge \coresync_clk update \alu_logical0_logical_op__rc__ok $0\alu_logical0_logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:143702.3-143703.79" - process $proc$libresoc.v:143702$6683 + attribute \src "libresoc.v:144582.3-144583.79" + process $proc$libresoc.v:144582$6667 assign { } { } assign $0\alu_logical0_logical_op__oe__oe[0:0] \alu_logical0_logical_op__oe__oe$next sync posedge \coresync_clk update \alu_logical0_logical_op__oe__oe $0\alu_logical0_logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:143704.3-143705.79" - process $proc$libresoc.v:143704$6684 + attribute \src "libresoc.v:144584.3-144585.79" + process $proc$libresoc.v:144584$6668 assign { } { } assign $0\alu_logical0_logical_op__oe__ok[0:0] \alu_logical0_logical_op__oe__ok$next sync posedge \coresync_clk update \alu_logical0_logical_op__oe__ok $0\alu_logical0_logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:143706.3-143707.85" - process $proc$libresoc.v:143706$6685 + attribute \src "libresoc.v:144586.3-144587.85" + process $proc$libresoc.v:144586$6669 assign { } { } assign $0\alu_logical0_logical_op__invert_in[0:0] \alu_logical0_logical_op__invert_in$next sync posedge \coresync_clk update \alu_logical0_logical_op__invert_in $0\alu_logical0_logical_op__invert_in[0:0] end - attribute \src "libresoc.v:143708.3-143709.79" - process $proc$libresoc.v:143708$6686 + attribute \src "libresoc.v:144588.3-144589.79" + process $proc$libresoc.v:144588$6670 assign { } { } assign $0\alu_logical0_logical_op__zero_a[0:0] \alu_logical0_logical_op__zero_a$next sync posedge \coresync_clk update \alu_logical0_logical_op__zero_a $0\alu_logical0_logical_op__zero_a[0:0] end - attribute \src "libresoc.v:143710.3-143711.89" - process $proc$libresoc.v:143710$6687 + attribute \src "libresoc.v:144590.3-144591.89" + process $proc$libresoc.v:144590$6671 assign { } { } assign $0\alu_logical0_logical_op__input_carry[1:0] \alu_logical0_logical_op__input_carry$next sync posedge \coresync_clk update \alu_logical0_logical_op__input_carry $0\alu_logical0_logical_op__input_carry[1:0] end - attribute \src "libresoc.v:143712.3-143713.87" - process $proc$libresoc.v:143712$6688 + attribute \src "libresoc.v:144592.3-144593.87" + process $proc$libresoc.v:144592$6672 assign { } { } assign $0\alu_logical0_logical_op__invert_out[0:0] \alu_logical0_logical_op__invert_out$next sync posedge \coresync_clk update \alu_logical0_logical_op__invert_out $0\alu_logical0_logical_op__invert_out[0:0] end - attribute \src "libresoc.v:143714.3-143715.85" - process $proc$libresoc.v:143714$6689 + attribute \src "libresoc.v:144594.3-144595.85" + process $proc$libresoc.v:144594$6673 assign { } { } assign $0\alu_logical0_logical_op__write_cr0[0:0] \alu_logical0_logical_op__write_cr0$next sync posedge \coresync_clk update \alu_logical0_logical_op__write_cr0 $0\alu_logical0_logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:143716.3-143717.91" - process $proc$libresoc.v:143716$6690 + attribute \src "libresoc.v:144596.3-144597.91" + process $proc$libresoc.v:144596$6674 assign { } { } assign $0\alu_logical0_logical_op__output_carry[0:0] \alu_logical0_logical_op__output_carry$next sync posedge \coresync_clk update \alu_logical0_logical_op__output_carry $0\alu_logical0_logical_op__output_carry[0:0] end - attribute \src "libresoc.v:143718.3-143719.83" - process $proc$libresoc.v:143718$6691 + attribute \src "libresoc.v:144598.3-144599.83" + process $proc$libresoc.v:144598$6675 assign { } { } assign $0\alu_logical0_logical_op__is_32bit[0:0] \alu_logical0_logical_op__is_32bit$next sync posedge \coresync_clk update \alu_logical0_logical_op__is_32bit $0\alu_logical0_logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:143720.3-143721.85" - process $proc$libresoc.v:143720$6692 + attribute \src "libresoc.v:144600.3-144601.85" + process $proc$libresoc.v:144600$6676 assign { } { } assign $0\alu_logical0_logical_op__is_signed[0:0] \alu_logical0_logical_op__is_signed$next sync posedge \coresync_clk update \alu_logical0_logical_op__is_signed $0\alu_logical0_logical_op__is_signed[0:0] end - attribute \src "libresoc.v:143722.3-143723.83" - process $proc$libresoc.v:143722$6693 + attribute \src "libresoc.v:144602.3-144603.83" + process $proc$libresoc.v:144602$6677 assign { } { } assign $0\alu_logical0_logical_op__data_len[3:0] \alu_logical0_logical_op__data_len$next sync posedge \coresync_clk update \alu_logical0_logical_op__data_len $0\alu_logical0_logical_op__data_len[3:0] end - attribute \src "libresoc.v:143724.3-143725.75" - process $proc$libresoc.v:143724$6694 + attribute \src "libresoc.v:144604.3-144605.75" + process $proc$libresoc.v:144604$6678 assign { } { } assign $0\alu_logical0_logical_op__insn[31:0] \alu_logical0_logical_op__insn$next sync posedge \coresync_clk update \alu_logical0_logical_op__insn $0\alu_logical0_logical_op__insn[31:0] end - attribute \src "libresoc.v:143726.3-143727.39" - process $proc$libresoc.v:143726$6695 + attribute \src "libresoc.v:144606.3-144607.39" + process $proc$libresoc.v:144606$6679 assign { } { } assign $0\req_l_r_req[1:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[1:0] end - attribute \src "libresoc.v:143728.3-143729.39" - process $proc$libresoc.v:143728$6696 + attribute \src "libresoc.v:144608.3-144609.39" + process $proc$libresoc.v:144608$6680 assign { } { } assign $0\req_l_s_req[1:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[1:0] end - attribute \src "libresoc.v:143730.3-143731.39" - process $proc$libresoc.v:143730$6697 + attribute \src "libresoc.v:144610.3-144611.39" + process $proc$libresoc.v:144610$6681 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "libresoc.v:143732.3-143733.39" - process $proc$libresoc.v:143732$6698 + attribute \src "libresoc.v:144612.3-144613.39" + process $proc$libresoc.v:144612$6682 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:143734.3-143735.39" - process $proc$libresoc.v:143734$6699 + attribute \src "libresoc.v:144614.3-144615.39" + process $proc$libresoc.v:144614$6683 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:143736.3-143737.39" - process $proc$libresoc.v:143736$6700 + attribute \src "libresoc.v:144616.3-144617.39" + process $proc$libresoc.v:144616$6684 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:143738.3-143739.39" - process $proc$libresoc.v:143738$6701 + attribute \src "libresoc.v:144618.3-144619.39" + process $proc$libresoc.v:144618$6685 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:143740.3-143741.39" - process $proc$libresoc.v:143740$6702 + attribute \src "libresoc.v:144620.3-144621.39" + process $proc$libresoc.v:144620$6686 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:143742.3-143743.41" - process $proc$libresoc.v:143742$6703 + attribute \src "libresoc.v:144622.3-144623.41" + process $proc$libresoc.v:144622$6687 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:143744.3-143745.41" - process $proc$libresoc.v:143744$6704 + attribute \src "libresoc.v:144624.3-144625.41" + process $proc$libresoc.v:144624$6688 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:143746.3-143747.37" - process $proc$libresoc.v:143746$6705 + attribute \src "libresoc.v:144626.3-144627.37" + process $proc$libresoc.v:144626$6689 assign { } { } assign $0\prev_wr_go[1:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[1:0] end - attribute \src "libresoc.v:143748.3-143749.44" - process $proc$libresoc.v:143748$6706 + attribute \src "libresoc.v:144628.3-144629.44" + process $proc$libresoc.v:144628$6690 assign { } { } assign $0\alu_done_dly[0:0] \alu_logical0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:143750.3-143751.24" - process $proc$libresoc.v:143750$6707 + attribute \src "libresoc.v:144630.3-144631.24" + process $proc$libresoc.v:144630$6691 assign { } { } assign $0\all_rd_dly[0:0] \$9 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:143833.3-143842.6" - process $proc$libresoc.v:143833$6708 + attribute \src "libresoc.v:144713.3-144722.6" + process $proc$libresoc.v:144713$6692 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:143834.5-143834.29" + attribute \src "libresoc.v:144714.5-144714.29" switch \initial - attribute \src "libresoc.v:143834.9-143834.17" + attribute \src "libresoc.v:144714.9-144714.17" case 1'1 case end @@ -234304,14 +234724,14 @@ module \logical0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:143843.3-143851.6" - process $proc$libresoc.v:143843$6709 + attribute \src "libresoc.v:144723.3-144731.6" + process $proc$libresoc.v:144723$6693 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$6710 $1\rok_l_s_rdok$next[0:0]$6711 - attribute \src "libresoc.v:143844.5-143844.29" + assign $0\rok_l_s_rdok$next[0:0]$6694 $1\rok_l_s_rdok$next[0:0]$6695 + attribute \src "libresoc.v:144724.5-144724.29" switch \initial - attribute \src "libresoc.v:143844.9-143844.17" + attribute \src "libresoc.v:144724.9-144724.17" case 1'1 case end @@ -234320,21 +234740,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$6711 1'0 + assign $1\rok_l_s_rdok$next[0:0]$6695 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$6711 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$6695 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$6710 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$6694 end - attribute \src "libresoc.v:143852.3-143860.6" - process $proc$libresoc.v:143852$6712 + attribute \src "libresoc.v:144732.3-144740.6" + process $proc$libresoc.v:144732$6696 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$6713 $1\rok_l_r_rdok$next[0:0]$6714 - attribute \src "libresoc.v:143853.5-143853.29" + assign $0\rok_l_r_rdok$next[0:0]$6697 $1\rok_l_r_rdok$next[0:0]$6698 + attribute \src "libresoc.v:144733.5-144733.29" switch \initial - attribute \src "libresoc.v:143853.9-143853.17" + attribute \src "libresoc.v:144733.9-144733.17" case 1'1 case end @@ -234343,21 +234763,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$6714 1'1 + assign $1\rok_l_r_rdok$next[0:0]$6698 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$6714 \$63 + assign $1\rok_l_r_rdok$next[0:0]$6698 \$63 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$6713 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$6697 end - attribute \src "libresoc.v:143861.3-143869.6" - process $proc$libresoc.v:143861$6715 + attribute \src "libresoc.v:144741.3-144749.6" + process $proc$libresoc.v:144741$6699 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$6716 $1\rst_l_s_rst$next[0:0]$6717 - attribute \src "libresoc.v:143862.5-143862.29" + assign $0\rst_l_s_rst$next[0:0]$6700 $1\rst_l_s_rst$next[0:0]$6701 + attribute \src "libresoc.v:144742.5-144742.29" switch \initial - attribute \src "libresoc.v:143862.9-143862.17" + attribute \src "libresoc.v:144742.9-144742.17" case 1'1 case end @@ -234366,21 +234786,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$6717 1'0 + assign $1\rst_l_s_rst$next[0:0]$6701 1'0 case - assign $1\rst_l_s_rst$next[0:0]$6717 \all_rd + assign $1\rst_l_s_rst$next[0:0]$6701 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$6716 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$6700 end - attribute \src "libresoc.v:143870.3-143878.6" - process $proc$libresoc.v:143870$6718 + attribute \src "libresoc.v:144750.3-144758.6" + process $proc$libresoc.v:144750$6702 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$6719 $1\rst_l_r_rst$next[0:0]$6720 - attribute \src "libresoc.v:143871.5-143871.29" + assign $0\rst_l_r_rst$next[0:0]$6703 $1\rst_l_r_rst$next[0:0]$6704 + attribute \src "libresoc.v:144751.5-144751.29" switch \initial - attribute \src "libresoc.v:143871.9-143871.17" + attribute \src "libresoc.v:144751.9-144751.17" case 1'1 case end @@ -234389,21 +234809,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$6720 1'1 + assign $1\rst_l_r_rst$next[0:0]$6704 1'1 case - assign $1\rst_l_r_rst$next[0:0]$6720 \rst_r + assign $1\rst_l_r_rst$next[0:0]$6704 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$6719 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$6703 end - attribute \src "libresoc.v:143879.3-143887.6" - process $proc$libresoc.v:143879$6721 + attribute \src "libresoc.v:144759.3-144767.6" + process $proc$libresoc.v:144759$6705 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$6722 $1\opc_l_s_opc$next[0:0]$6723 - attribute \src "libresoc.v:143880.5-143880.29" + assign $0\opc_l_s_opc$next[0:0]$6706 $1\opc_l_s_opc$next[0:0]$6707 + attribute \src "libresoc.v:144760.5-144760.29" switch \initial - attribute \src "libresoc.v:143880.9-143880.17" + attribute \src "libresoc.v:144760.9-144760.17" case 1'1 case end @@ -234412,21 +234832,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$6723 1'0 + assign $1\opc_l_s_opc$next[0:0]$6707 1'0 case - assign $1\opc_l_s_opc$next[0:0]$6723 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$6707 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6722 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6706 end - attribute \src "libresoc.v:143888.3-143896.6" - process $proc$libresoc.v:143888$6724 + attribute \src "libresoc.v:144768.3-144776.6" + process $proc$libresoc.v:144768$6708 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$6725 $1\opc_l_r_opc$next[0:0]$6726 - attribute \src "libresoc.v:143889.5-143889.29" + assign $0\opc_l_r_opc$next[0:0]$6709 $1\opc_l_r_opc$next[0:0]$6710 + attribute \src "libresoc.v:144769.5-144769.29" switch \initial - attribute \src "libresoc.v:143889.9-143889.17" + attribute \src "libresoc.v:144769.9-144769.17" case 1'1 case end @@ -234435,21 +234855,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$6726 1'1 + assign $1\opc_l_r_opc$next[0:0]$6710 1'1 case - assign $1\opc_l_r_opc$next[0:0]$6726 \req_done + assign $1\opc_l_r_opc$next[0:0]$6710 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6725 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6709 end - attribute \src "libresoc.v:143897.3-143905.6" - process $proc$libresoc.v:143897$6727 + attribute \src "libresoc.v:144777.3-144785.6" + process $proc$libresoc.v:144777$6711 assign { } { } assign { } { } - assign $0\src_l_s_src$next[2:0]$6728 $1\src_l_s_src$next[2:0]$6729 - attribute \src "libresoc.v:143898.5-143898.29" + assign $0\src_l_s_src$next[2:0]$6712 $1\src_l_s_src$next[2:0]$6713 + attribute \src "libresoc.v:144778.5-144778.29" switch \initial - attribute \src "libresoc.v:143898.9-143898.17" + attribute \src "libresoc.v:144778.9-144778.17" case 1'1 case end @@ -234458,21 +234878,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[2:0]$6729 3'000 + assign $1\src_l_s_src$next[2:0]$6713 3'000 case - assign $1\src_l_s_src$next[2:0]$6729 { \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[2:0]$6713 { \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6728 + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6712 end - attribute \src "libresoc.v:143906.3-143914.6" - process $proc$libresoc.v:143906$6730 + attribute \src "libresoc.v:144786.3-144794.6" + process $proc$libresoc.v:144786$6714 assign { } { } assign { } { } - assign $0\src_l_r_src$next[2:0]$6731 $1\src_l_r_src$next[2:0]$6732 - attribute \src "libresoc.v:143907.5-143907.29" + assign $0\src_l_r_src$next[2:0]$6715 $1\src_l_r_src$next[2:0]$6716 + attribute \src "libresoc.v:144787.5-144787.29" switch \initial - attribute \src "libresoc.v:143907.9-143907.17" + attribute \src "libresoc.v:144787.9-144787.17" case 1'1 case end @@ -234481,21 +234901,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[2:0]$6732 3'111 + assign $1\src_l_r_src$next[2:0]$6716 3'111 case - assign $1\src_l_r_src$next[2:0]$6732 \reset_r + assign $1\src_l_r_src$next[2:0]$6716 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6731 + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6715 end - attribute \src "libresoc.v:143915.3-143923.6" - process $proc$libresoc.v:143915$6733 + attribute \src "libresoc.v:144795.3-144803.6" + process $proc$libresoc.v:144795$6717 assign { } { } assign { } { } - assign $0\req_l_s_req$next[1:0]$6734 $1\req_l_s_req$next[1:0]$6735 - attribute \src "libresoc.v:143916.5-143916.29" + assign $0\req_l_s_req$next[1:0]$6718 $1\req_l_s_req$next[1:0]$6719 + attribute \src "libresoc.v:144796.5-144796.29" switch \initial - attribute \src "libresoc.v:143916.9-143916.17" + attribute \src "libresoc.v:144796.9-144796.17" case 1'1 case end @@ -234504,21 +234924,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[1:0]$6735 2'00 + assign $1\req_l_s_req$next[1:0]$6719 2'00 case - assign $1\req_l_s_req$next[1:0]$6735 \$65 + assign $1\req_l_s_req$next[1:0]$6719 \$65 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[1:0]$6734 + update \req_l_s_req$next $0\req_l_s_req$next[1:0]$6718 end - attribute \src "libresoc.v:143924.3-143932.6" - process $proc$libresoc.v:143924$6736 + attribute \src "libresoc.v:144804.3-144812.6" + process $proc$libresoc.v:144804$6720 assign { } { } assign { } { } - assign $0\req_l_r_req$next[1:0]$6737 $1\req_l_r_req$next[1:0]$6738 - attribute \src "libresoc.v:143925.5-143925.29" + assign $0\req_l_r_req$next[1:0]$6721 $1\req_l_r_req$next[1:0]$6722 + attribute \src "libresoc.v:144805.5-144805.29" switch \initial - attribute \src "libresoc.v:143925.9-143925.17" + attribute \src "libresoc.v:144805.9-144805.17" case 1'1 case end @@ -234527,15 +234947,15 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[1:0]$6738 2'11 + assign $1\req_l_r_req$next[1:0]$6722 2'11 case - assign $1\req_l_r_req$next[1:0]$6738 \$67 + assign $1\req_l_r_req$next[1:0]$6722 \$67 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[1:0]$6737 + update \req_l_r_req$next $0\req_l_r_req$next[1:0]$6721 end - attribute \src "libresoc.v:143933.3-143971.6" - process $proc$libresoc.v:143933$6739 + attribute \src "libresoc.v:144813.3-144851.6" + process $proc$libresoc.v:144813$6723 assign { } { } assign { } { } assign { } { } @@ -234572,33 +234992,33 @@ module \logical0 assign { } { } assign { } { } assign { } { } - assign $0\alu_logical0_logical_op__data_len$next[3:0]$6740 $1\alu_logical0_logical_op__data_len$next[3:0]$6758 - assign $0\alu_logical0_logical_op__fn_unit$next[13:0]$6741 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6759 + assign $0\alu_logical0_logical_op__data_len$next[3:0]$6724 $1\alu_logical0_logical_op__data_len$next[3:0]$6742 + assign $0\alu_logical0_logical_op__fn_unit$next[13:0]$6725 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6743 assign { } { } assign { } { } - assign $0\alu_logical0_logical_op__input_carry$next[1:0]$6744 $1\alu_logical0_logical_op__input_carry$next[1:0]$6762 - assign $0\alu_logical0_logical_op__insn$next[31:0]$6745 $1\alu_logical0_logical_op__insn$next[31:0]$6763 - assign $0\alu_logical0_logical_op__insn_type$next[6:0]$6746 $1\alu_logical0_logical_op__insn_type$next[6:0]$6764 - assign $0\alu_logical0_logical_op__invert_in$next[0:0]$6747 $1\alu_logical0_logical_op__invert_in$next[0:0]$6765 - assign $0\alu_logical0_logical_op__invert_out$next[0:0]$6748 $1\alu_logical0_logical_op__invert_out$next[0:0]$6766 - assign $0\alu_logical0_logical_op__is_32bit$next[0:0]$6749 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6767 - assign $0\alu_logical0_logical_op__is_signed$next[0:0]$6750 $1\alu_logical0_logical_op__is_signed$next[0:0]$6768 + assign $0\alu_logical0_logical_op__input_carry$next[1:0]$6728 $1\alu_logical0_logical_op__input_carry$next[1:0]$6746 + assign $0\alu_logical0_logical_op__insn$next[31:0]$6729 $1\alu_logical0_logical_op__insn$next[31:0]$6747 + assign $0\alu_logical0_logical_op__insn_type$next[6:0]$6730 $1\alu_logical0_logical_op__insn_type$next[6:0]$6748 + assign $0\alu_logical0_logical_op__invert_in$next[0:0]$6731 $1\alu_logical0_logical_op__invert_in$next[0:0]$6749 + assign $0\alu_logical0_logical_op__invert_out$next[0:0]$6732 $1\alu_logical0_logical_op__invert_out$next[0:0]$6750 + assign $0\alu_logical0_logical_op__is_32bit$next[0:0]$6733 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6751 + assign $0\alu_logical0_logical_op__is_signed$next[0:0]$6734 $1\alu_logical0_logical_op__is_signed$next[0:0]$6752 assign { } { } assign { } { } - assign $0\alu_logical0_logical_op__output_carry$next[0:0]$6753 $1\alu_logical0_logical_op__output_carry$next[0:0]$6771 + assign $0\alu_logical0_logical_op__output_carry$next[0:0]$6737 $1\alu_logical0_logical_op__output_carry$next[0:0]$6755 assign { } { } assign { } { } - assign $0\alu_logical0_logical_op__write_cr0$next[0:0]$6756 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6774 - assign $0\alu_logical0_logical_op__zero_a$next[0:0]$6757 $1\alu_logical0_logical_op__zero_a$next[0:0]$6775 - assign $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6742 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6776 - assign $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6743 $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6777 - assign $0\alu_logical0_logical_op__oe__oe$next[0:0]$6751 $2\alu_logical0_logical_op__oe__oe$next[0:0]$6778 - assign $0\alu_logical0_logical_op__oe__ok$next[0:0]$6752 $2\alu_logical0_logical_op__oe__ok$next[0:0]$6779 - assign $0\alu_logical0_logical_op__rc__ok$next[0:0]$6754 $2\alu_logical0_logical_op__rc__ok$next[0:0]$6780 - assign $0\alu_logical0_logical_op__rc__rc$next[0:0]$6755 $2\alu_logical0_logical_op__rc__rc$next[0:0]$6781 - attribute \src "libresoc.v:143934.5-143934.29" + assign $0\alu_logical0_logical_op__write_cr0$next[0:0]$6740 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6758 + assign $0\alu_logical0_logical_op__zero_a$next[0:0]$6741 $1\alu_logical0_logical_op__zero_a$next[0:0]$6759 + assign $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6726 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6760 + assign $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6727 $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6761 + assign $0\alu_logical0_logical_op__oe__oe$next[0:0]$6735 $2\alu_logical0_logical_op__oe__oe$next[0:0]$6762 + assign $0\alu_logical0_logical_op__oe__ok$next[0:0]$6736 $2\alu_logical0_logical_op__oe__ok$next[0:0]$6763 + assign $0\alu_logical0_logical_op__rc__ok$next[0:0]$6738 $2\alu_logical0_logical_op__rc__ok$next[0:0]$6764 + assign $0\alu_logical0_logical_op__rc__rc$next[0:0]$6739 $2\alu_logical0_logical_op__rc__rc$next[0:0]$6765 + attribute \src "libresoc.v:144814.5-144814.29" switch \initial - attribute \src "libresoc.v:143934.9-143934.17" + attribute \src "libresoc.v:144814.9-144814.17" case 1'1 case end @@ -234624,26 +235044,26 @@ module \logical0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_logical0_logical_op__insn$next[31:0]$6763 $1\alu_logical0_logical_op__data_len$next[3:0]$6758 $1\alu_logical0_logical_op__is_signed$next[0:0]$6768 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6767 $1\alu_logical0_logical_op__output_carry$next[0:0]$6771 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6774 $1\alu_logical0_logical_op__invert_out$next[0:0]$6766 $1\alu_logical0_logical_op__input_carry$next[1:0]$6762 $1\alu_logical0_logical_op__zero_a$next[0:0]$6775 $1\alu_logical0_logical_op__invert_in$next[0:0]$6765 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6770 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6769 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6772 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6773 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6761 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6760 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6759 $1\alu_logical0_logical_op__insn_type$next[6:0]$6764 } { \oper_i_alu_logical0__insn \oper_i_alu_logical0__data_len \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__invert_in \oper_i_alu_logical0__oe__ok \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__rc__ok \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__imm_data__ok \oper_i_alu_logical0__imm_data__data \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__insn_type } + assign { $1\alu_logical0_logical_op__insn$next[31:0]$6747 $1\alu_logical0_logical_op__data_len$next[3:0]$6742 $1\alu_logical0_logical_op__is_signed$next[0:0]$6752 $1\alu_logical0_logical_op__is_32bit$next[0:0]$6751 $1\alu_logical0_logical_op__output_carry$next[0:0]$6755 $1\alu_logical0_logical_op__write_cr0$next[0:0]$6758 $1\alu_logical0_logical_op__invert_out$next[0:0]$6750 $1\alu_logical0_logical_op__input_carry$next[1:0]$6746 $1\alu_logical0_logical_op__zero_a$next[0:0]$6759 $1\alu_logical0_logical_op__invert_in$next[0:0]$6749 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6754 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6753 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6756 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6757 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6745 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6744 $1\alu_logical0_logical_op__fn_unit$next[13:0]$6743 $1\alu_logical0_logical_op__insn_type$next[6:0]$6748 } { \oper_i_alu_logical0__insn \oper_i_alu_logical0__data_len \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__invert_in \oper_i_alu_logical0__oe__ok \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__rc__ok \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__imm_data__ok \oper_i_alu_logical0__imm_data__data \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__insn_type } case - assign $1\alu_logical0_logical_op__data_len$next[3:0]$6758 \alu_logical0_logical_op__data_len - assign $1\alu_logical0_logical_op__fn_unit$next[13:0]$6759 \alu_logical0_logical_op__fn_unit - assign $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6760 \alu_logical0_logical_op__imm_data__data - assign $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6761 \alu_logical0_logical_op__imm_data__ok - assign $1\alu_logical0_logical_op__input_carry$next[1:0]$6762 \alu_logical0_logical_op__input_carry - assign $1\alu_logical0_logical_op__insn$next[31:0]$6763 \alu_logical0_logical_op__insn - assign $1\alu_logical0_logical_op__insn_type$next[6:0]$6764 \alu_logical0_logical_op__insn_type - assign $1\alu_logical0_logical_op__invert_in$next[0:0]$6765 \alu_logical0_logical_op__invert_in - assign $1\alu_logical0_logical_op__invert_out$next[0:0]$6766 \alu_logical0_logical_op__invert_out - assign $1\alu_logical0_logical_op__is_32bit$next[0:0]$6767 \alu_logical0_logical_op__is_32bit - assign $1\alu_logical0_logical_op__is_signed$next[0:0]$6768 \alu_logical0_logical_op__is_signed - assign $1\alu_logical0_logical_op__oe__oe$next[0:0]$6769 \alu_logical0_logical_op__oe__oe - assign $1\alu_logical0_logical_op__oe__ok$next[0:0]$6770 \alu_logical0_logical_op__oe__ok - assign $1\alu_logical0_logical_op__output_carry$next[0:0]$6771 \alu_logical0_logical_op__output_carry - assign $1\alu_logical0_logical_op__rc__ok$next[0:0]$6772 \alu_logical0_logical_op__rc__ok - assign $1\alu_logical0_logical_op__rc__rc$next[0:0]$6773 \alu_logical0_logical_op__rc__rc - assign $1\alu_logical0_logical_op__write_cr0$next[0:0]$6774 \alu_logical0_logical_op__write_cr0 - assign $1\alu_logical0_logical_op__zero_a$next[0:0]$6775 \alu_logical0_logical_op__zero_a + assign $1\alu_logical0_logical_op__data_len$next[3:0]$6742 \alu_logical0_logical_op__data_len + assign $1\alu_logical0_logical_op__fn_unit$next[13:0]$6743 \alu_logical0_logical_op__fn_unit + assign $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6744 \alu_logical0_logical_op__imm_data__data + assign $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6745 \alu_logical0_logical_op__imm_data__ok + assign $1\alu_logical0_logical_op__input_carry$next[1:0]$6746 \alu_logical0_logical_op__input_carry + assign $1\alu_logical0_logical_op__insn$next[31:0]$6747 \alu_logical0_logical_op__insn + assign $1\alu_logical0_logical_op__insn_type$next[6:0]$6748 \alu_logical0_logical_op__insn_type + assign $1\alu_logical0_logical_op__invert_in$next[0:0]$6749 \alu_logical0_logical_op__invert_in + assign $1\alu_logical0_logical_op__invert_out$next[0:0]$6750 \alu_logical0_logical_op__invert_out + assign $1\alu_logical0_logical_op__is_32bit$next[0:0]$6751 \alu_logical0_logical_op__is_32bit + assign $1\alu_logical0_logical_op__is_signed$next[0:0]$6752 \alu_logical0_logical_op__is_signed + assign $1\alu_logical0_logical_op__oe__oe$next[0:0]$6753 \alu_logical0_logical_op__oe__oe + assign $1\alu_logical0_logical_op__oe__ok$next[0:0]$6754 \alu_logical0_logical_op__oe__ok + assign $1\alu_logical0_logical_op__output_carry$next[0:0]$6755 \alu_logical0_logical_op__output_carry + assign $1\alu_logical0_logical_op__rc__ok$next[0:0]$6756 \alu_logical0_logical_op__rc__ok + assign $1\alu_logical0_logical_op__rc__rc$next[0:0]$6757 \alu_logical0_logical_op__rc__rc + assign $1\alu_logical0_logical_op__write_cr0$next[0:0]$6758 \alu_logical0_logical_op__write_cr0 + assign $1\alu_logical0_logical_op__zero_a$next[0:0]$6759 \alu_logical0_logical_op__zero_a end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -234655,54 +235075,54 @@ module \logical0 assign { } { } assign { } { } assign { } { } - assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6776 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6777 1'0 - assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6781 1'0 - assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6780 1'0 - assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6778 1'0 - assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6779 1'0 + assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6760 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6761 1'0 + assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6765 1'0 + assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6764 1'0 + assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6762 1'0 + assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6763 1'0 case - assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6776 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6760 - assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6777 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6761 - assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6778 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6769 - assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6779 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6770 - assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6780 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6772 - assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6781 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6773 + assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$6760 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$6744 + assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$6761 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$6745 + assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$6762 $1\alu_logical0_logical_op__oe__oe$next[0:0]$6753 + assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$6763 $1\alu_logical0_logical_op__oe__ok$next[0:0]$6754 + assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$6764 $1\alu_logical0_logical_op__rc__ok$next[0:0]$6756 + assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$6765 $1\alu_logical0_logical_op__rc__rc$next[0:0]$6757 end sync always - update \alu_logical0_logical_op__data_len$next $0\alu_logical0_logical_op__data_len$next[3:0]$6740 - update \alu_logical0_logical_op__fn_unit$next $0\alu_logical0_logical_op__fn_unit$next[13:0]$6741 - update \alu_logical0_logical_op__imm_data__data$next $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6742 - update \alu_logical0_logical_op__imm_data__ok$next $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6743 - update \alu_logical0_logical_op__input_carry$next $0\alu_logical0_logical_op__input_carry$next[1:0]$6744 - update \alu_logical0_logical_op__insn$next $0\alu_logical0_logical_op__insn$next[31:0]$6745 - update \alu_logical0_logical_op__insn_type$next $0\alu_logical0_logical_op__insn_type$next[6:0]$6746 - update \alu_logical0_logical_op__invert_in$next $0\alu_logical0_logical_op__invert_in$next[0:0]$6747 - update \alu_logical0_logical_op__invert_out$next $0\alu_logical0_logical_op__invert_out$next[0:0]$6748 - update \alu_logical0_logical_op__is_32bit$next $0\alu_logical0_logical_op__is_32bit$next[0:0]$6749 - update \alu_logical0_logical_op__is_signed$next $0\alu_logical0_logical_op__is_signed$next[0:0]$6750 - update \alu_logical0_logical_op__oe__oe$next $0\alu_logical0_logical_op__oe__oe$next[0:0]$6751 - update \alu_logical0_logical_op__oe__ok$next $0\alu_logical0_logical_op__oe__ok$next[0:0]$6752 - update \alu_logical0_logical_op__output_carry$next $0\alu_logical0_logical_op__output_carry$next[0:0]$6753 - update \alu_logical0_logical_op__rc__ok$next $0\alu_logical0_logical_op__rc__ok$next[0:0]$6754 - update \alu_logical0_logical_op__rc__rc$next $0\alu_logical0_logical_op__rc__rc$next[0:0]$6755 - update \alu_logical0_logical_op__write_cr0$next $0\alu_logical0_logical_op__write_cr0$next[0:0]$6756 - update \alu_logical0_logical_op__zero_a$next $0\alu_logical0_logical_op__zero_a$next[0:0]$6757 + update \alu_logical0_logical_op__data_len$next $0\alu_logical0_logical_op__data_len$next[3:0]$6724 + update \alu_logical0_logical_op__fn_unit$next $0\alu_logical0_logical_op__fn_unit$next[13:0]$6725 + update \alu_logical0_logical_op__imm_data__data$next $0\alu_logical0_logical_op__imm_data__data$next[63:0]$6726 + update \alu_logical0_logical_op__imm_data__ok$next $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$6727 + update \alu_logical0_logical_op__input_carry$next $0\alu_logical0_logical_op__input_carry$next[1:0]$6728 + update \alu_logical0_logical_op__insn$next $0\alu_logical0_logical_op__insn$next[31:0]$6729 + update \alu_logical0_logical_op__insn_type$next $0\alu_logical0_logical_op__insn_type$next[6:0]$6730 + update \alu_logical0_logical_op__invert_in$next $0\alu_logical0_logical_op__invert_in$next[0:0]$6731 + update \alu_logical0_logical_op__invert_out$next $0\alu_logical0_logical_op__invert_out$next[0:0]$6732 + update \alu_logical0_logical_op__is_32bit$next $0\alu_logical0_logical_op__is_32bit$next[0:0]$6733 + update \alu_logical0_logical_op__is_signed$next $0\alu_logical0_logical_op__is_signed$next[0:0]$6734 + update \alu_logical0_logical_op__oe__oe$next $0\alu_logical0_logical_op__oe__oe$next[0:0]$6735 + update \alu_logical0_logical_op__oe__ok$next $0\alu_logical0_logical_op__oe__ok$next[0:0]$6736 + update \alu_logical0_logical_op__output_carry$next $0\alu_logical0_logical_op__output_carry$next[0:0]$6737 + update \alu_logical0_logical_op__rc__ok$next $0\alu_logical0_logical_op__rc__ok$next[0:0]$6738 + update \alu_logical0_logical_op__rc__rc$next $0\alu_logical0_logical_op__rc__rc$next[0:0]$6739 + update \alu_logical0_logical_op__write_cr0$next $0\alu_logical0_logical_op__write_cr0$next[0:0]$6740 + update \alu_logical0_logical_op__zero_a$next $0\alu_logical0_logical_op__zero_a$next[0:0]$6741 end - attribute \src "libresoc.v:143972.3-143993.6" - process $proc$libresoc.v:143972$6782 + attribute \src "libresoc.v:144852.3-144873.6" + process $proc$libresoc.v:144852$6766 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$6783 $2\data_r0__o$next[63:0]$6787 + assign $0\data_r0__o$next[63:0]$6767 $2\data_r0__o$next[63:0]$6771 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$6784 $3\data_r0__o_ok$next[0:0]$6789 - attribute \src "libresoc.v:143973.5-143973.29" + assign $0\data_r0__o_ok$next[0:0]$6768 $3\data_r0__o_ok$next[0:0]$6773 + attribute \src "libresoc.v:144853.5-144853.29" switch \initial - attribute \src "libresoc.v:143973.9-143973.17" + attribute \src "libresoc.v:144853.9-144853.17" case 1'1 case end @@ -234712,10 +235132,10 @@ module \logical0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$6786 $1\data_r0__o$next[63:0]$6785 } { \o_ok \alu_logical0_o } + assign { $1\data_r0__o_ok$next[0:0]$6770 $1\data_r0__o$next[63:0]$6769 } { \o_ok \alu_logical0_o } case - assign $1\data_r0__o$next[63:0]$6785 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$6786 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$6769 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$6770 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -234723,38 +235143,38 @@ module \logical0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$6788 $2\data_r0__o$next[63:0]$6787 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$6772 $2\data_r0__o$next[63:0]$6771 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$6787 $1\data_r0__o$next[63:0]$6785 - assign $2\data_r0__o_ok$next[0:0]$6788 $1\data_r0__o_ok$next[0:0]$6786 + assign $2\data_r0__o$next[63:0]$6771 $1\data_r0__o$next[63:0]$6769 + assign $2\data_r0__o_ok$next[0:0]$6772 $1\data_r0__o_ok$next[0:0]$6770 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$6789 1'0 + assign $3\data_r0__o_ok$next[0:0]$6773 1'0 case - assign $3\data_r0__o_ok$next[0:0]$6789 $2\data_r0__o_ok$next[0:0]$6788 + assign $3\data_r0__o_ok$next[0:0]$6773 $2\data_r0__o_ok$next[0:0]$6772 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$6783 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$6784 + update \data_r0__o$next $0\data_r0__o$next[63:0]$6767 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$6768 end - attribute \src "libresoc.v:143994.3-144015.6" - process $proc$libresoc.v:143994$6790 + attribute \src "libresoc.v:144874.3-144895.6" + process $proc$libresoc.v:144874$6774 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__cr_a$next[3:0]$6791 $2\data_r1__cr_a$next[3:0]$6795 + assign $0\data_r1__cr_a$next[3:0]$6775 $2\data_r1__cr_a$next[3:0]$6779 assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$6792 $3\data_r1__cr_a_ok$next[0:0]$6797 - attribute \src "libresoc.v:143995.5-143995.29" + assign $0\data_r1__cr_a_ok$next[0:0]$6776 $3\data_r1__cr_a_ok$next[0:0]$6781 + attribute \src "libresoc.v:144875.5-144875.29" switch \initial - attribute \src "libresoc.v:143995.9-143995.17" + attribute \src "libresoc.v:144875.9-144875.17" case 1'1 case end @@ -234764,10 +235184,10 @@ module \logical0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$6794 $1\data_r1__cr_a$next[3:0]$6793 } { \cr_a_ok \alu_logical0_cr_a } + assign { $1\data_r1__cr_a_ok$next[0:0]$6778 $1\data_r1__cr_a$next[3:0]$6777 } { \cr_a_ok \alu_logical0_cr_a } case - assign $1\data_r1__cr_a$next[3:0]$6793 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$6794 \data_r1__cr_a_ok + assign $1\data_r1__cr_a$next[3:0]$6777 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$6778 \data_r1__cr_a_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -234775,32 +235195,32 @@ module \logical0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$6796 $2\data_r1__cr_a$next[3:0]$6795 } 5'00000 + assign { $2\data_r1__cr_a_ok$next[0:0]$6780 $2\data_r1__cr_a$next[3:0]$6779 } 5'00000 case - assign $2\data_r1__cr_a$next[3:0]$6795 $1\data_r1__cr_a$next[3:0]$6793 - assign $2\data_r1__cr_a_ok$next[0:0]$6796 $1\data_r1__cr_a_ok$next[0:0]$6794 + assign $2\data_r1__cr_a$next[3:0]$6779 $1\data_r1__cr_a$next[3:0]$6777 + assign $2\data_r1__cr_a_ok$next[0:0]$6780 $1\data_r1__cr_a_ok$next[0:0]$6778 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$6797 1'0 + assign $3\data_r1__cr_a_ok$next[0:0]$6781 1'0 case - assign $3\data_r1__cr_a_ok$next[0:0]$6797 $2\data_r1__cr_a_ok$next[0:0]$6796 + assign $3\data_r1__cr_a_ok$next[0:0]$6781 $2\data_r1__cr_a_ok$next[0:0]$6780 end sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$6791 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$6792 + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$6775 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$6776 end - attribute \src "libresoc.v:144016.3-144025.6" - process $proc$libresoc.v:144016$6798 + attribute \src "libresoc.v:144896.3-144905.6" + process $proc$libresoc.v:144896$6782 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$6799 $1\src_r0$next[63:0]$6800 - attribute \src "libresoc.v:144017.5-144017.29" + assign $0\src_r0$next[63:0]$6783 $1\src_r0$next[63:0]$6784 + attribute \src "libresoc.v:144897.5-144897.29" switch \initial - attribute \src "libresoc.v:144017.9-144017.17" + attribute \src "libresoc.v:144897.9-144897.17" case 1'1 case end @@ -234809,21 +235229,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$6800 \src_or_imm + assign $1\src_r0$next[63:0]$6784 \src_or_imm case - assign $1\src_r0$next[63:0]$6800 \src_r0 + assign $1\src_r0$next[63:0]$6784 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$6799 + update \src_r0$next $0\src_r0$next[63:0]$6783 end - attribute \src "libresoc.v:144026.3-144035.6" - process $proc$libresoc.v:144026$6801 + attribute \src "libresoc.v:144906.3-144915.6" + process $proc$libresoc.v:144906$6785 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$6802 $1\src_r1$next[63:0]$6803 - attribute \src "libresoc.v:144027.5-144027.29" + assign $0\src_r1$next[63:0]$6786 $1\src_r1$next[63:0]$6787 + attribute \src "libresoc.v:144907.5-144907.29" switch \initial - attribute \src "libresoc.v:144027.9-144027.17" + attribute \src "libresoc.v:144907.9-144907.17" case 1'1 case end @@ -234832,21 +235252,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$6803 \src_or_imm$80 + assign $1\src_r1$next[63:0]$6787 \src_or_imm$80 case - assign $1\src_r1$next[63:0]$6803 \src_r1 + assign $1\src_r1$next[63:0]$6787 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$6802 + update \src_r1$next $0\src_r1$next[63:0]$6786 end - attribute \src "libresoc.v:144036.3-144045.6" - process $proc$libresoc.v:144036$6804 + attribute \src "libresoc.v:144916.3-144925.6" + process $proc$libresoc.v:144916$6788 assign { } { } assign { } { } - assign $0\src_r2$next[0:0]$6805 $1\src_r2$next[0:0]$6806 - attribute \src "libresoc.v:144037.5-144037.29" + assign $0\src_r2$next[0:0]$6789 $1\src_r2$next[0:0]$6790 + attribute \src "libresoc.v:144917.5-144917.29" switch \initial - attribute \src "libresoc.v:144037.9-144037.17" + attribute \src "libresoc.v:144917.9-144917.17" case 1'1 case end @@ -234855,21 +235275,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[0:0]$6806 \src3_i + assign $1\src_r2$next[0:0]$6790 \src3_i case - assign $1\src_r2$next[0:0]$6806 \src_r2 + assign $1\src_r2$next[0:0]$6790 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[0:0]$6805 + update \src_r2$next $0\src_r2$next[0:0]$6789 end - attribute \src "libresoc.v:144046.3-144054.6" - process $proc$libresoc.v:144046$6807 + attribute \src "libresoc.v:144926.3-144934.6" + process $proc$libresoc.v:144926$6791 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$6808 $1\alui_l_r_alui$next[0:0]$6809 - attribute \src "libresoc.v:144047.5-144047.29" + assign $0\alui_l_r_alui$next[0:0]$6792 $1\alui_l_r_alui$next[0:0]$6793 + attribute \src "libresoc.v:144927.5-144927.29" switch \initial - attribute \src "libresoc.v:144047.9-144047.17" + attribute \src "libresoc.v:144927.9-144927.17" case 1'1 case end @@ -234878,21 +235298,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$6809 1'1 + assign $1\alui_l_r_alui$next[0:0]$6793 1'1 case - assign $1\alui_l_r_alui$next[0:0]$6809 \$89 + assign $1\alui_l_r_alui$next[0:0]$6793 \$89 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$6808 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$6792 end - attribute \src "libresoc.v:144055.3-144063.6" - process $proc$libresoc.v:144055$6810 + attribute \src "libresoc.v:144935.3-144943.6" + process $proc$libresoc.v:144935$6794 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$6811 $1\alu_l_r_alu$next[0:0]$6812 - attribute \src "libresoc.v:144056.5-144056.29" + assign $0\alu_l_r_alu$next[0:0]$6795 $1\alu_l_r_alu$next[0:0]$6796 + attribute \src "libresoc.v:144936.5-144936.29" switch \initial - attribute \src "libresoc.v:144056.9-144056.17" + attribute \src "libresoc.v:144936.9-144936.17" case 1'1 case end @@ -234901,21 +235321,21 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$6812 1'1 + assign $1\alu_l_r_alu$next[0:0]$6796 1'1 case - assign $1\alu_l_r_alu$next[0:0]$6812 \$91 + assign $1\alu_l_r_alu$next[0:0]$6796 \$91 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$6811 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$6795 end - attribute \src "libresoc.v:144064.3-144073.6" - process $proc$libresoc.v:144064$6813 + attribute \src "libresoc.v:144944.3-144953.6" + process $proc$libresoc.v:144944$6797 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:144065.5-144065.29" + attribute \src "libresoc.v:144945.5-144945.29" switch \initial - attribute \src "libresoc.v:144065.9-144065.17" + attribute \src "libresoc.v:144945.9-144945.17" case 1'1 case end @@ -234931,14 +235351,14 @@ module \logical0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:144074.3-144083.6" - process $proc$libresoc.v:144074$6814 + attribute \src "libresoc.v:144954.3-144963.6" + process $proc$libresoc.v:144954$6798 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:144075.5-144075.29" + attribute \src "libresoc.v:144955.5-144955.29" switch \initial - attribute \src "libresoc.v:144075.9-144075.17" + attribute \src "libresoc.v:144955.9-144955.17" case 1'1 case end @@ -234954,14 +235374,14 @@ module \logical0 sync always update \dest2_o $0\dest2_o[3:0] end - attribute \src "libresoc.v:144084.3-144092.6" - process $proc$libresoc.v:144084$6815 + attribute \src "libresoc.v:144964.3-144972.6" + process $proc$libresoc.v:144964$6799 assign { } { } assign { } { } - assign $0\prev_wr_go$next[1:0]$6816 $1\prev_wr_go$next[1:0]$6817 - attribute \src "libresoc.v:144085.5-144085.29" + assign $0\prev_wr_go$next[1:0]$6800 $1\prev_wr_go$next[1:0]$6801 + attribute \src "libresoc.v:144965.5-144965.29" switch \initial - attribute \src "libresoc.v:144085.9-144085.17" + attribute \src "libresoc.v:144965.9-144965.17" case 1'1 case end @@ -234970,70 +235390,70 @@ module \logical0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[1:0]$6817 2'00 - case - assign $1\prev_wr_go$next[1:0]$6817 \$19 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[1:0]$6816 - end - connect \$9 $and$libresoc.v:143615$6611_Y - connect \$99 $and$libresoc.v:143616$6612_Y - connect \$101 $not$libresoc.v:143617$6613_Y - connect \$103 $and$libresoc.v:143618$6614_Y - connect \$105 $and$libresoc.v:143619$6615_Y - connect \$107 $and$libresoc.v:143620$6616_Y - connect \$109 $and$libresoc.v:143621$6617_Y - connect \$111 $and$libresoc.v:143622$6618_Y - connect \$113 $and$libresoc.v:143623$6619_Y - connect \$115 $and$libresoc.v:143624$6620_Y - connect \$11 $not$libresoc.v:143625$6621_Y - connect \$13 $and$libresoc.v:143626$6622_Y - connect \$15 $not$libresoc.v:143627$6623_Y - connect \$17 $and$libresoc.v:143628$6624_Y - connect \$1 $and$libresoc.v:143629$6625_Y - connect \$19 $and$libresoc.v:143630$6626_Y - connect \$23 $not$libresoc.v:143631$6627_Y - connect \$25 $and$libresoc.v:143632$6628_Y - connect \$22 $reduce_or$libresoc.v:143633$6629_Y - connect \$21 $not$libresoc.v:143634$6630_Y - connect \$29 $and$libresoc.v:143635$6631_Y - connect \$31 $reduce_or$libresoc.v:143636$6632_Y - connect \$33 $reduce_or$libresoc.v:143637$6633_Y - connect \$35 $or$libresoc.v:143638$6634_Y - connect \$37 $not$libresoc.v:143639$6635_Y - connect \$39 $and$libresoc.v:143640$6636_Y - connect \$41 $and$libresoc.v:143641$6637_Y - connect \$43 $eq$libresoc.v:143642$6638_Y - connect \$45 $and$libresoc.v:143643$6639_Y - connect \$47 $eq$libresoc.v:143644$6640_Y - connect \$4 $not$libresoc.v:143645$6641_Y - connect \$49 $and$libresoc.v:143646$6642_Y - connect \$51 $and$libresoc.v:143647$6643_Y - connect \$53 $and$libresoc.v:143648$6644_Y - connect \$55 $or$libresoc.v:143649$6645_Y - connect \$57 $or$libresoc.v:143650$6646_Y - connect \$59 $or$libresoc.v:143651$6647_Y - connect \$61 $or$libresoc.v:143652$6648_Y - connect \$63 $and$libresoc.v:143653$6649_Y - connect \$65 $and$libresoc.v:143654$6650_Y - connect \$67 $or$libresoc.v:143655$6651_Y - connect \$6 $or$libresoc.v:143656$6652_Y - connect \$69 $and$libresoc.v:143657$6653_Y - connect \$71 $and$libresoc.v:143658$6654_Y - connect \$73 $ternary$libresoc.v:143659$6655_Y - connect \$75 $ternary$libresoc.v:143660$6656_Y - connect \$78 $ternary$libresoc.v:143661$6657_Y - connect \$3 $reduce_and$libresoc.v:143662$6658_Y - connect \$81 $ternary$libresoc.v:143663$6659_Y - connect \$83 $ternary$libresoc.v:143664$6660_Y - connect \$85 $ternary$libresoc.v:143665$6661_Y - connect \$87 $ternary$libresoc.v:143666$6662_Y - connect \$89 $and$libresoc.v:143667$6663_Y - connect \$91 $and$libresoc.v:143668$6664_Y - connect \$93 $and$libresoc.v:143669$6665_Y - connect \$95 $not$libresoc.v:143670$6666_Y - connect \$97 $not$libresoc.v:143671$6667_Y + assign $1\prev_wr_go$next[1:0]$6801 2'00 + case + assign $1\prev_wr_go$next[1:0]$6801 \$19 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[1:0]$6800 + end + connect \$9 $and$libresoc.v:144495$6595_Y + connect \$99 $and$libresoc.v:144496$6596_Y + connect \$101 $not$libresoc.v:144497$6597_Y + connect \$103 $and$libresoc.v:144498$6598_Y + connect \$105 $and$libresoc.v:144499$6599_Y + connect \$107 $and$libresoc.v:144500$6600_Y + connect \$109 $and$libresoc.v:144501$6601_Y + connect \$111 $and$libresoc.v:144502$6602_Y + connect \$113 $and$libresoc.v:144503$6603_Y + connect \$115 $and$libresoc.v:144504$6604_Y + connect \$11 $not$libresoc.v:144505$6605_Y + connect \$13 $and$libresoc.v:144506$6606_Y + connect \$15 $not$libresoc.v:144507$6607_Y + connect \$17 $and$libresoc.v:144508$6608_Y + connect \$1 $and$libresoc.v:144509$6609_Y + connect \$19 $and$libresoc.v:144510$6610_Y + connect \$23 $not$libresoc.v:144511$6611_Y + connect \$25 $and$libresoc.v:144512$6612_Y + connect \$22 $reduce_or$libresoc.v:144513$6613_Y + connect \$21 $not$libresoc.v:144514$6614_Y + connect \$29 $and$libresoc.v:144515$6615_Y + connect \$31 $reduce_or$libresoc.v:144516$6616_Y + connect \$33 $reduce_or$libresoc.v:144517$6617_Y + connect \$35 $or$libresoc.v:144518$6618_Y + connect \$37 $not$libresoc.v:144519$6619_Y + connect \$39 $and$libresoc.v:144520$6620_Y + connect \$41 $and$libresoc.v:144521$6621_Y + connect \$43 $eq$libresoc.v:144522$6622_Y + connect \$45 $and$libresoc.v:144523$6623_Y + connect \$47 $eq$libresoc.v:144524$6624_Y + connect \$4 $not$libresoc.v:144525$6625_Y + connect \$49 $and$libresoc.v:144526$6626_Y + connect \$51 $and$libresoc.v:144527$6627_Y + connect \$53 $and$libresoc.v:144528$6628_Y + connect \$55 $or$libresoc.v:144529$6629_Y + connect \$57 $or$libresoc.v:144530$6630_Y + connect \$59 $or$libresoc.v:144531$6631_Y + connect \$61 $or$libresoc.v:144532$6632_Y + connect \$63 $and$libresoc.v:144533$6633_Y + connect \$65 $and$libresoc.v:144534$6634_Y + connect \$67 $or$libresoc.v:144535$6635_Y + connect \$6 $or$libresoc.v:144536$6636_Y + connect \$69 $and$libresoc.v:144537$6637_Y + connect \$71 $and$libresoc.v:144538$6638_Y + connect \$73 $ternary$libresoc.v:144539$6639_Y + connect \$75 $ternary$libresoc.v:144540$6640_Y + connect \$78 $ternary$libresoc.v:144541$6641_Y + connect \$3 $reduce_and$libresoc.v:144542$6642_Y + connect \$81 $ternary$libresoc.v:144543$6643_Y + connect \$83 $ternary$libresoc.v:144544$6644_Y + connect \$85 $ternary$libresoc.v:144545$6645_Y + connect \$87 $ternary$libresoc.v:144546$6646_Y + connect \$89 $and$libresoc.v:144547$6647_Y + connect \$91 $and$libresoc.v:144548$6648_Y + connect \$93 $and$libresoc.v:144549$6649_Y + connect \$95 $not$libresoc.v:144550$6650_Y + connect \$97 $not$libresoc.v:144551$6651_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$111 @@ -235067,248 +235487,248 @@ module \logical0 connect \all_rd_dly$next \all_rd connect \all_rd \$9 end -attribute \src "libresoc.v:144129.1-145520.10" +attribute \src "libresoc.v:145009.1-146400.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1" attribute \generator "nMigen" module \logical_pipe1 - attribute \src "libresoc.v:145459.3-145477.6" - wire width 4 $0\cr_a$next[3:0]$6943 - attribute \src "libresoc.v:145219.3-145220.25" + attribute \src "libresoc.v:146339.3-146357.6" + wire width 4 $0\cr_a$next[3:0]$6927 + attribute \src "libresoc.v:146099.3-146100.25" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:145459.3-145477.6" - wire $0\cr_a_ok$next[0:0]$6944 - attribute \src "libresoc.v:145221.3-145222.31" + attribute \src "libresoc.v:146339.3-146357.6" + wire $0\cr_a_ok$next[0:0]$6928 + attribute \src "libresoc.v:146101.3-146102.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:144130.7-144130.20" + attribute \src "libresoc.v:145010.7-145010.20" wire $0\initial[0:0] - attribute \src "libresoc.v:145398.3-145439.6" - wire width 4 $0\logical_op__data_len$next[3:0]$6894 - attribute \src "libresoc.v:145259.3-145260.57" + attribute \src "libresoc.v:146278.3-146319.6" + wire width 4 $0\logical_op__data_len$next[3:0]$6878 + attribute \src "libresoc.v:146139.3-146140.57" wire width 4 $0\logical_op__data_len[3:0] - attribute \src "libresoc.v:145398.3-145439.6" - wire width 14 $0\logical_op__fn_unit$next[13:0]$6895 - attribute \src "libresoc.v:145229.3-145230.55" + attribute \src "libresoc.v:146278.3-146319.6" + wire width 14 $0\logical_op__fn_unit$next[13:0]$6879 + attribute \src "libresoc.v:146109.3-146110.55" wire width 14 $0\logical_op__fn_unit[13:0] - attribute \src "libresoc.v:145398.3-145439.6" - wire width 64 $0\logical_op__imm_data__data$next[63:0]$6896 - attribute \src "libresoc.v:145231.3-145232.69" + attribute \src "libresoc.v:146278.3-146319.6" + wire width 64 $0\logical_op__imm_data__data$next[63:0]$6880 + attribute \src "libresoc.v:146111.3-146112.69" wire width 64 $0\logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:145398.3-145439.6" - wire $0\logical_op__imm_data__ok$next[0:0]$6897 - attribute \src "libresoc.v:145233.3-145234.65" + attribute \src "libresoc.v:146278.3-146319.6" + wire $0\logical_op__imm_data__ok$next[0:0]$6881 + attribute \src "libresoc.v:146113.3-146114.65" wire $0\logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:145398.3-145439.6" - wire width 2 $0\logical_op__input_carry$next[1:0]$6898 - attribute \src "libresoc.v:145247.3-145248.63" + attribute \src "libresoc.v:146278.3-146319.6" + wire width 2 $0\logical_op__input_carry$next[1:0]$6882 + attribute \src "libresoc.v:146127.3-146128.63" wire width 2 $0\logical_op__input_carry[1:0] - attribute \src "libresoc.v:145398.3-145439.6" - wire width 32 $0\logical_op__insn$next[31:0]$6899 - attribute \src "libresoc.v:145261.3-145262.49" + attribute \src "libresoc.v:146278.3-146319.6" + wire width 32 $0\logical_op__insn$next[31:0]$6883 + attribute \src "libresoc.v:146141.3-146142.49" wire width 32 $0\logical_op__insn[31:0] - attribute \src "libresoc.v:145398.3-145439.6" - wire width 7 $0\logical_op__insn_type$next[6:0]$6900 - attribute \src "libresoc.v:145227.3-145228.59" + attribute \src "libresoc.v:146278.3-146319.6" + wire width 7 $0\logical_op__insn_type$next[6:0]$6884 + attribute \src "libresoc.v:146107.3-146108.59" wire width 7 $0\logical_op__insn_type[6:0] - attribute \src "libresoc.v:145398.3-145439.6" - wire $0\logical_op__invert_in$next[0:0]$6901 - attribute \src "libresoc.v:145243.3-145244.59" + attribute \src "libresoc.v:146278.3-146319.6" + wire $0\logical_op__invert_in$next[0:0]$6885 + attribute \src "libresoc.v:146123.3-146124.59" wire $0\logical_op__invert_in[0:0] - attribute \src "libresoc.v:145398.3-145439.6" - wire $0\logical_op__invert_out$next[0:0]$6902 - attribute \src "libresoc.v:145249.3-145250.61" + attribute \src "libresoc.v:146278.3-146319.6" + wire $0\logical_op__invert_out$next[0:0]$6886 + attribute \src "libresoc.v:146129.3-146130.61" wire $0\logical_op__invert_out[0:0] - attribute \src "libresoc.v:145398.3-145439.6" - wire $0\logical_op__is_32bit$next[0:0]$6903 - attribute \src "libresoc.v:145255.3-145256.57" + attribute \src "libresoc.v:146278.3-146319.6" + wire $0\logical_op__is_32bit$next[0:0]$6887 + attribute \src "libresoc.v:146135.3-146136.57" wire $0\logical_op__is_32bit[0:0] - attribute \src "libresoc.v:145398.3-145439.6" - wire $0\logical_op__is_signed$next[0:0]$6904 - attribute \src "libresoc.v:145257.3-145258.59" + attribute \src "libresoc.v:146278.3-146319.6" + wire $0\logical_op__is_signed$next[0:0]$6888 + attribute \src "libresoc.v:146137.3-146138.59" wire $0\logical_op__is_signed[0:0] - attribute \src "libresoc.v:145398.3-145439.6" - wire $0\logical_op__oe__oe$next[0:0]$6905 - attribute \src "libresoc.v:145239.3-145240.53" + attribute \src "libresoc.v:146278.3-146319.6" + wire $0\logical_op__oe__oe$next[0:0]$6889 + attribute \src "libresoc.v:146119.3-146120.53" wire $0\logical_op__oe__oe[0:0] - attribute \src "libresoc.v:145398.3-145439.6" - wire $0\logical_op__oe__ok$next[0:0]$6906 - attribute \src "libresoc.v:145241.3-145242.53" + attribute \src "libresoc.v:146278.3-146319.6" + wire $0\logical_op__oe__ok$next[0:0]$6890 + attribute \src "libresoc.v:146121.3-146122.53" wire $0\logical_op__oe__ok[0:0] - attribute \src "libresoc.v:145398.3-145439.6" - wire $0\logical_op__output_carry$next[0:0]$6907 - attribute \src "libresoc.v:145253.3-145254.65" + attribute \src "libresoc.v:146278.3-146319.6" + wire $0\logical_op__output_carry$next[0:0]$6891 + attribute \src "libresoc.v:146133.3-146134.65" wire $0\logical_op__output_carry[0:0] - attribute \src "libresoc.v:145398.3-145439.6" - wire $0\logical_op__rc__ok$next[0:0]$6908 - attribute \src "libresoc.v:145237.3-145238.53" + attribute \src "libresoc.v:146278.3-146319.6" + wire $0\logical_op__rc__ok$next[0:0]$6892 + attribute \src "libresoc.v:146117.3-146118.53" wire $0\logical_op__rc__ok[0:0] - attribute \src "libresoc.v:145398.3-145439.6" - wire $0\logical_op__rc__rc$next[0:0]$6909 - attribute \src "libresoc.v:145235.3-145236.53" + attribute \src "libresoc.v:146278.3-146319.6" + wire $0\logical_op__rc__rc$next[0:0]$6893 + attribute \src "libresoc.v:146115.3-146116.53" wire $0\logical_op__rc__rc[0:0] - attribute \src "libresoc.v:145398.3-145439.6" - wire $0\logical_op__write_cr0$next[0:0]$6910 - attribute \src "libresoc.v:145251.3-145252.59" + attribute \src "libresoc.v:146278.3-146319.6" + wire $0\logical_op__write_cr0$next[0:0]$6894 + attribute \src "libresoc.v:146131.3-146132.59" wire $0\logical_op__write_cr0[0:0] - attribute \src "libresoc.v:145398.3-145439.6" - wire $0\logical_op__zero_a$next[0:0]$6911 - attribute \src "libresoc.v:145245.3-145246.53" + attribute \src "libresoc.v:146278.3-146319.6" + wire $0\logical_op__zero_a$next[0:0]$6895 + attribute \src "libresoc.v:146125.3-146126.53" wire $0\logical_op__zero_a[0:0] - attribute \src "libresoc.v:145385.3-145397.6" - wire width 2 $0\muxid$next[1:0]$6891 - attribute \src "libresoc.v:145263.3-145264.27" + attribute \src "libresoc.v:146265.3-146277.6" + wire width 2 $0\muxid$next[1:0]$6875 + attribute \src "libresoc.v:146143.3-146144.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:145440.3-145458.6" - wire width 64 $0\o$next[63:0]$6937 - attribute \src "libresoc.v:145223.3-145224.19" + attribute \src "libresoc.v:146320.3-146338.6" + wire width 64 $0\o$next[63:0]$6921 + attribute \src "libresoc.v:146103.3-146104.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:145440.3-145458.6" - wire $0\o_ok$next[0:0]$6938 - attribute \src "libresoc.v:145225.3-145226.25" + attribute \src "libresoc.v:146320.3-146338.6" + wire $0\o_ok$next[0:0]$6922 + attribute \src "libresoc.v:146105.3-146106.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:145367.3-145384.6" - wire $0\r_busy$next[0:0]$6887 - attribute \src "libresoc.v:145265.3-145266.29" + attribute \src "libresoc.v:146247.3-146264.6" + wire $0\r_busy$next[0:0]$6871 + attribute \src "libresoc.v:146145.3-146146.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:145478.3-145496.6" - wire $0\xer_so$next[0:0]$6949 - attribute \src "libresoc.v:145215.3-145216.29" + attribute \src "libresoc.v:146358.3-146376.6" + wire $0\xer_so$next[0:0]$6933 + attribute \src "libresoc.v:146095.3-146096.29" wire $0\xer_so[0:0] - attribute \src "libresoc.v:145478.3-145496.6" - wire $0\xer_so_ok$next[0:0]$6950 - attribute \src "libresoc.v:145217.3-145218.35" + attribute \src "libresoc.v:146358.3-146376.6" + wire $0\xer_so_ok$next[0:0]$6934 + attribute \src "libresoc.v:146097.3-146098.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:145459.3-145477.6" - wire width 4 $1\cr_a$next[3:0]$6945 - attribute \src "libresoc.v:144139.13-144139.24" + attribute \src "libresoc.v:146339.3-146357.6" + wire width 4 $1\cr_a$next[3:0]$6929 + attribute \src "libresoc.v:145019.13-145019.24" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:145459.3-145477.6" - wire $1\cr_a_ok$next[0:0]$6946 - attribute \src "libresoc.v:144148.7-144148.21" + attribute \src "libresoc.v:146339.3-146357.6" + wire $1\cr_a_ok$next[0:0]$6930 + attribute \src "libresoc.v:145028.7-145028.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:145398.3-145439.6" - wire width 4 $1\logical_op__data_len$next[3:0]$6912 - attribute \src "libresoc.v:144433.13-144433.40" + attribute \src "libresoc.v:146278.3-146319.6" + wire width 4 $1\logical_op__data_len$next[3:0]$6896 + attribute \src "libresoc.v:145313.13-145313.40" wire width 4 $1\logical_op__data_len[3:0] - attribute \src "libresoc.v:145398.3-145439.6" - wire width 14 $1\logical_op__fn_unit$next[13:0]$6913 - attribute \src "libresoc.v:144457.14-144457.44" + attribute \src "libresoc.v:146278.3-146319.6" + wire width 14 $1\logical_op__fn_unit$next[13:0]$6897 + attribute \src "libresoc.v:145337.14-145337.44" wire width 14 $1\logical_op__fn_unit[13:0] - attribute \src "libresoc.v:145398.3-145439.6" - wire width 64 $1\logical_op__imm_data__data$next[63:0]$6914 - attribute \src "libresoc.v:144496.14-144496.63" + attribute \src "libresoc.v:146278.3-146319.6" + wire width 64 $1\logical_op__imm_data__data$next[63:0]$6898 + attribute \src "libresoc.v:145376.14-145376.63" wire width 64 $1\logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:145398.3-145439.6" - wire $1\logical_op__imm_data__ok$next[0:0]$6915 - attribute \src "libresoc.v:144505.7-144505.38" + attribute \src "libresoc.v:146278.3-146319.6" + wire $1\logical_op__imm_data__ok$next[0:0]$6899 + attribute \src "libresoc.v:145385.7-145385.38" wire $1\logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:145398.3-145439.6" - wire width 2 $1\logical_op__input_carry$next[1:0]$6916 - attribute \src "libresoc.v:144518.13-144518.43" + attribute \src "libresoc.v:146278.3-146319.6" + wire width 2 $1\logical_op__input_carry$next[1:0]$6900 + attribute \src "libresoc.v:145398.13-145398.43" wire width 2 $1\logical_op__input_carry[1:0] - attribute \src "libresoc.v:145398.3-145439.6" - wire width 32 $1\logical_op__insn$next[31:0]$6917 - attribute \src "libresoc.v:144535.14-144535.38" + attribute \src "libresoc.v:146278.3-146319.6" + wire width 32 $1\logical_op__insn$next[31:0]$6901 + attribute \src "libresoc.v:145415.14-145415.38" wire width 32 $1\logical_op__insn[31:0] - attribute \src "libresoc.v:145398.3-145439.6" - wire width 7 $1\logical_op__insn_type$next[6:0]$6918 - attribute \src "libresoc.v:144619.13-144619.42" + attribute \src "libresoc.v:146278.3-146319.6" + wire width 7 $1\logical_op__insn_type$next[6:0]$6902 + attribute \src "libresoc.v:145499.13-145499.42" wire width 7 $1\logical_op__insn_type[6:0] - attribute \src "libresoc.v:145398.3-145439.6" - wire $1\logical_op__invert_in$next[0:0]$6919 - attribute \src "libresoc.v:144778.7-144778.35" + attribute \src "libresoc.v:146278.3-146319.6" + wire $1\logical_op__invert_in$next[0:0]$6903 + attribute \src "libresoc.v:145658.7-145658.35" wire $1\logical_op__invert_in[0:0] - attribute \src "libresoc.v:145398.3-145439.6" - wire $1\logical_op__invert_out$next[0:0]$6920 - attribute \src "libresoc.v:144787.7-144787.36" + attribute \src "libresoc.v:146278.3-146319.6" + wire $1\logical_op__invert_out$next[0:0]$6904 + attribute \src "libresoc.v:145667.7-145667.36" wire $1\logical_op__invert_out[0:0] - attribute \src "libresoc.v:145398.3-145439.6" - wire $1\logical_op__is_32bit$next[0:0]$6921 - attribute \src "libresoc.v:144796.7-144796.34" + attribute \src "libresoc.v:146278.3-146319.6" + wire $1\logical_op__is_32bit$next[0:0]$6905 + attribute \src "libresoc.v:145676.7-145676.34" wire $1\logical_op__is_32bit[0:0] - attribute \src "libresoc.v:145398.3-145439.6" - wire $1\logical_op__is_signed$next[0:0]$6922 - attribute \src "libresoc.v:144805.7-144805.35" + attribute \src "libresoc.v:146278.3-146319.6" + wire $1\logical_op__is_signed$next[0:0]$6906 + attribute \src "libresoc.v:145685.7-145685.35" wire $1\logical_op__is_signed[0:0] - attribute \src "libresoc.v:145398.3-145439.6" - wire $1\logical_op__oe__oe$next[0:0]$6923 - attribute \src "libresoc.v:144814.7-144814.32" + attribute \src "libresoc.v:146278.3-146319.6" + wire $1\logical_op__oe__oe$next[0:0]$6907 + attribute \src "libresoc.v:145694.7-145694.32" wire $1\logical_op__oe__oe[0:0] - attribute \src "libresoc.v:145398.3-145439.6" - wire $1\logical_op__oe__ok$next[0:0]$6924 - attribute \src "libresoc.v:144823.7-144823.32" + attribute \src "libresoc.v:146278.3-146319.6" + wire $1\logical_op__oe__ok$next[0:0]$6908 + attribute \src "libresoc.v:145703.7-145703.32" wire $1\logical_op__oe__ok[0:0] - attribute \src "libresoc.v:145398.3-145439.6" - wire $1\logical_op__output_carry$next[0:0]$6925 - attribute \src "libresoc.v:144832.7-144832.38" + attribute \src "libresoc.v:146278.3-146319.6" + wire $1\logical_op__output_carry$next[0:0]$6909 + attribute \src "libresoc.v:145712.7-145712.38" wire $1\logical_op__output_carry[0:0] - attribute \src "libresoc.v:145398.3-145439.6" - wire $1\logical_op__rc__ok$next[0:0]$6926 - attribute \src "libresoc.v:144841.7-144841.32" + attribute \src "libresoc.v:146278.3-146319.6" + wire $1\logical_op__rc__ok$next[0:0]$6910 + attribute \src "libresoc.v:145721.7-145721.32" wire $1\logical_op__rc__ok[0:0] - attribute \src "libresoc.v:145398.3-145439.6" - wire $1\logical_op__rc__rc$next[0:0]$6927 - attribute \src "libresoc.v:144850.7-144850.32" + attribute \src "libresoc.v:146278.3-146319.6" + wire $1\logical_op__rc__rc$next[0:0]$6911 + attribute \src "libresoc.v:145730.7-145730.32" wire $1\logical_op__rc__rc[0:0] - attribute \src "libresoc.v:145398.3-145439.6" - wire $1\logical_op__write_cr0$next[0:0]$6928 - attribute \src "libresoc.v:144859.7-144859.35" + attribute \src "libresoc.v:146278.3-146319.6" + wire $1\logical_op__write_cr0$next[0:0]$6912 + attribute \src "libresoc.v:145739.7-145739.35" wire $1\logical_op__write_cr0[0:0] - attribute \src "libresoc.v:145398.3-145439.6" - wire $1\logical_op__zero_a$next[0:0]$6929 - attribute \src "libresoc.v:144868.7-144868.32" + attribute \src "libresoc.v:146278.3-146319.6" + wire $1\logical_op__zero_a$next[0:0]$6913 + attribute \src "libresoc.v:145748.7-145748.32" wire $1\logical_op__zero_a[0:0] - attribute \src "libresoc.v:145385.3-145397.6" - wire width 2 $1\muxid$next[1:0]$6892 - attribute \src "libresoc.v:145153.13-145153.25" + attribute \src "libresoc.v:146265.3-146277.6" + wire width 2 $1\muxid$next[1:0]$6876 + attribute \src "libresoc.v:146033.13-146033.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:145440.3-145458.6" - wire width 64 $1\o$next[63:0]$6939 - attribute \src "libresoc.v:145168.14-145168.38" + attribute \src "libresoc.v:146320.3-146338.6" + wire width 64 $1\o$next[63:0]$6923 + attribute \src "libresoc.v:146048.14-146048.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:145440.3-145458.6" - wire $1\o_ok$next[0:0]$6940 - attribute \src "libresoc.v:145175.7-145175.18" + attribute \src "libresoc.v:146320.3-146338.6" + wire $1\o_ok$next[0:0]$6924 + attribute \src "libresoc.v:146055.7-146055.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:145367.3-145384.6" - wire $1\r_busy$next[0:0]$6888 - attribute \src "libresoc.v:145189.7-145189.20" + attribute \src "libresoc.v:146247.3-146264.6" + wire $1\r_busy$next[0:0]$6872 + attribute \src "libresoc.v:146069.7-146069.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:145478.3-145496.6" - wire $1\xer_so$next[0:0]$6951 - attribute \src "libresoc.v:145198.7-145198.20" + attribute \src "libresoc.v:146358.3-146376.6" + wire $1\xer_so$next[0:0]$6935 + attribute \src "libresoc.v:146078.7-146078.20" wire $1\xer_so[0:0] - attribute \src "libresoc.v:145478.3-145496.6" - wire $1\xer_so_ok$next[0:0]$6952 - attribute \src "libresoc.v:145207.7-145207.23" + attribute \src "libresoc.v:146358.3-146376.6" + wire $1\xer_so_ok$next[0:0]$6936 + attribute \src "libresoc.v:146087.7-146087.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:145459.3-145477.6" - wire $2\cr_a_ok$next[0:0]$6947 - attribute \src "libresoc.v:145398.3-145439.6" - wire width 64 $2\logical_op__imm_data__data$next[63:0]$6930 - attribute \src "libresoc.v:145398.3-145439.6" - wire $2\logical_op__imm_data__ok$next[0:0]$6931 - attribute \src "libresoc.v:145398.3-145439.6" - wire $2\logical_op__oe__oe$next[0:0]$6932 - attribute \src "libresoc.v:145398.3-145439.6" - wire $2\logical_op__oe__ok$next[0:0]$6933 - attribute \src "libresoc.v:145398.3-145439.6" - wire $2\logical_op__rc__ok$next[0:0]$6934 - attribute \src "libresoc.v:145398.3-145439.6" - wire $2\logical_op__rc__rc$next[0:0]$6935 - attribute \src "libresoc.v:145440.3-145458.6" - wire $2\o_ok$next[0:0]$6941 - attribute \src "libresoc.v:145367.3-145384.6" - wire $2\r_busy$next[0:0]$6889 - attribute \src "libresoc.v:145478.3-145496.6" - wire $2\xer_so_ok$next[0:0]$6953 - attribute \src "libresoc.v:145214.18-145214.118" - wire $and$libresoc.v:145214$6859_Y + attribute \src "libresoc.v:146339.3-146357.6" + wire $2\cr_a_ok$next[0:0]$6931 + attribute \src "libresoc.v:146278.3-146319.6" + wire width 64 $2\logical_op__imm_data__data$next[63:0]$6914 + attribute \src "libresoc.v:146278.3-146319.6" + wire $2\logical_op__imm_data__ok$next[0:0]$6915 + attribute \src "libresoc.v:146278.3-146319.6" + wire $2\logical_op__oe__oe$next[0:0]$6916 + attribute \src "libresoc.v:146278.3-146319.6" + wire $2\logical_op__oe__ok$next[0:0]$6917 + attribute \src "libresoc.v:146278.3-146319.6" + wire $2\logical_op__rc__ok$next[0:0]$6918 + attribute \src "libresoc.v:146278.3-146319.6" + wire $2\logical_op__rc__rc$next[0:0]$6919 + attribute \src "libresoc.v:146320.3-146338.6" + wire $2\o_ok$next[0:0]$6925 + attribute \src "libresoc.v:146247.3-146264.6" + wire $2\r_busy$next[0:0]$6873 + attribute \src "libresoc.v:146358.3-146376.6" + wire $2\xer_so_ok$next[0:0]$6937 + attribute \src "libresoc.v:146094.18-146094.118" + wire $and$libresoc.v:146094$6843_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 53 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 25 \cr_a @@ -235326,7 +235746,7 @@ module \logical_pipe1 wire \cr_a_ok$90 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$next - attribute \src "libresoc.v:144130.7-144130.15" + attribute \src "libresoc.v:145010.7-145010.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \input_logical_op__data_len @@ -236365,7 +236785,7 @@ module \logical_pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:145214$6859 + cell $and $and$libresoc.v:146094$6843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -236373,10 +236793,10 @@ module \logical_pipe1 parameter \Y_WIDTH 1 connect \A \p_valid_i$63 connect \B \p_ready_o - connect \Y $and$libresoc.v:145214$6859_Y + connect \Y $and$libresoc.v:146094$6843_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:145267.14-145312.4" + attribute \src "libresoc.v:146147.14-146192.4" cell \input$50 \input connect \logical_op__data_len \input_logical_op__data_len connect \logical_op__data_len$18 \input_logical_op__data_len$38 @@ -236424,7 +236844,7 @@ module \logical_pipe1 connect \xer_so$22 \input_xer_so$42 end attribute \module_not_derived 1 - attribute \src "libresoc.v:145313.13-145358.4" + attribute \src "libresoc.v:146193.13-146238.4" cell \main$51 \main connect \logical_op__data_len \main_logical_op__data_len connect \logical_op__data_len$18 \main_logical_op__data_len$60 @@ -236472,424 +236892,424 @@ module \logical_pipe1 connect \xer_so$20 \main_xer_so$62 end attribute \module_not_derived 1 - attribute \src "libresoc.v:145359.10-145362.4" + attribute \src "libresoc.v:146239.10-146242.4" cell \n$49 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:145363.10-145366.4" + attribute \src "libresoc.v:146243.10-146246.4" cell \p$48 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:144130.7-144130.20" - process $proc$libresoc.v:144130$6954 + attribute \src "libresoc.v:145010.7-145010.20" + process $proc$libresoc.v:145010$6938 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:144139.13-144139.24" - process $proc$libresoc.v:144139$6955 + attribute \src "libresoc.v:145019.13-145019.24" + process $proc$libresoc.v:145019$6939 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:144148.7-144148.21" - process $proc$libresoc.v:144148$6956 + attribute \src "libresoc.v:145028.7-145028.21" + process $proc$libresoc.v:145028$6940 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:144433.13-144433.40" - process $proc$libresoc.v:144433$6957 + attribute \src "libresoc.v:145313.13-145313.40" + process $proc$libresoc.v:145313$6941 assign { } { } assign $1\logical_op__data_len[3:0] 4'0000 sync always sync init update \logical_op__data_len $1\logical_op__data_len[3:0] end - attribute \src "libresoc.v:144457.14-144457.44" - process $proc$libresoc.v:144457$6958 + attribute \src "libresoc.v:145337.14-145337.44" + process $proc$libresoc.v:145337$6942 assign { } { } assign $1\logical_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \logical_op__fn_unit $1\logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:144496.14-144496.63" - process $proc$libresoc.v:144496$6959 + attribute \src "libresoc.v:145376.14-145376.63" + process $proc$libresoc.v:145376$6943 assign { } { } assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:144505.7-144505.38" - process $proc$libresoc.v:144505$6960 + attribute \src "libresoc.v:145385.7-145385.38" + process $proc$libresoc.v:145385$6944 assign { } { } assign $1\logical_op__imm_data__ok[0:0] 1'0 sync always sync init update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:144518.13-144518.43" - process $proc$libresoc.v:144518$6961 + attribute \src "libresoc.v:145398.13-145398.43" + process $proc$libresoc.v:145398$6945 assign { } { } assign $1\logical_op__input_carry[1:0] 2'00 sync always sync init update \logical_op__input_carry $1\logical_op__input_carry[1:0] end - attribute \src "libresoc.v:144535.14-144535.38" - process $proc$libresoc.v:144535$6962 + attribute \src "libresoc.v:145415.14-145415.38" + process $proc$libresoc.v:145415$6946 assign { } { } assign $1\logical_op__insn[31:0] 0 sync always sync init update \logical_op__insn $1\logical_op__insn[31:0] end - attribute \src "libresoc.v:144619.13-144619.42" - process $proc$libresoc.v:144619$6963 + attribute \src "libresoc.v:145499.13-145499.42" + process $proc$libresoc.v:145499$6947 assign { } { } assign $1\logical_op__insn_type[6:0] 7'0000000 sync always sync init update \logical_op__insn_type $1\logical_op__insn_type[6:0] end - attribute \src "libresoc.v:144778.7-144778.35" - process $proc$libresoc.v:144778$6964 + attribute \src "libresoc.v:145658.7-145658.35" + process $proc$libresoc.v:145658$6948 assign { } { } assign $1\logical_op__invert_in[0:0] 1'0 sync always sync init update \logical_op__invert_in $1\logical_op__invert_in[0:0] end - attribute \src "libresoc.v:144787.7-144787.36" - process $proc$libresoc.v:144787$6965 + attribute \src "libresoc.v:145667.7-145667.36" + process $proc$libresoc.v:145667$6949 assign { } { } assign $1\logical_op__invert_out[0:0] 1'0 sync always sync init update \logical_op__invert_out $1\logical_op__invert_out[0:0] end - attribute \src "libresoc.v:144796.7-144796.34" - process $proc$libresoc.v:144796$6966 + attribute \src "libresoc.v:145676.7-145676.34" + process $proc$libresoc.v:145676$6950 assign { } { } assign $1\logical_op__is_32bit[0:0] 1'0 sync always sync init update \logical_op__is_32bit $1\logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:144805.7-144805.35" - process $proc$libresoc.v:144805$6967 + attribute \src "libresoc.v:145685.7-145685.35" + process $proc$libresoc.v:145685$6951 assign { } { } assign $1\logical_op__is_signed[0:0] 1'0 sync always sync init update \logical_op__is_signed $1\logical_op__is_signed[0:0] end - attribute \src "libresoc.v:144814.7-144814.32" - process $proc$libresoc.v:144814$6968 + attribute \src "libresoc.v:145694.7-145694.32" + process $proc$libresoc.v:145694$6952 assign { } { } assign $1\logical_op__oe__oe[0:0] 1'0 sync always sync init update \logical_op__oe__oe $1\logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:144823.7-144823.32" - process $proc$libresoc.v:144823$6969 + attribute \src "libresoc.v:145703.7-145703.32" + process $proc$libresoc.v:145703$6953 assign { } { } assign $1\logical_op__oe__ok[0:0] 1'0 sync always sync init update \logical_op__oe__ok $1\logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:144832.7-144832.38" - process $proc$libresoc.v:144832$6970 + attribute \src "libresoc.v:145712.7-145712.38" + process $proc$libresoc.v:145712$6954 assign { } { } assign $1\logical_op__output_carry[0:0] 1'0 sync always sync init update \logical_op__output_carry $1\logical_op__output_carry[0:0] end - attribute \src "libresoc.v:144841.7-144841.32" - process $proc$libresoc.v:144841$6971 + attribute \src "libresoc.v:145721.7-145721.32" + process $proc$libresoc.v:145721$6955 assign { } { } assign $1\logical_op__rc__ok[0:0] 1'0 sync always sync init update \logical_op__rc__ok $1\logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:144850.7-144850.32" - process $proc$libresoc.v:144850$6972 + attribute \src "libresoc.v:145730.7-145730.32" + process $proc$libresoc.v:145730$6956 assign { } { } assign $1\logical_op__rc__rc[0:0] 1'0 sync always sync init update \logical_op__rc__rc $1\logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:144859.7-144859.35" - process $proc$libresoc.v:144859$6973 + attribute \src "libresoc.v:145739.7-145739.35" + process $proc$libresoc.v:145739$6957 assign { } { } assign $1\logical_op__write_cr0[0:0] 1'0 sync always sync init update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:144868.7-144868.32" - process $proc$libresoc.v:144868$6974 + attribute \src "libresoc.v:145748.7-145748.32" + process $proc$libresoc.v:145748$6958 assign { } { } assign $1\logical_op__zero_a[0:0] 1'0 sync always sync init update \logical_op__zero_a $1\logical_op__zero_a[0:0] end - attribute \src "libresoc.v:145153.13-145153.25" - process $proc$libresoc.v:145153$6975 + attribute \src "libresoc.v:146033.13-146033.25" + process $proc$libresoc.v:146033$6959 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:145168.14-145168.38" - process $proc$libresoc.v:145168$6976 + attribute \src "libresoc.v:146048.14-146048.38" + process $proc$libresoc.v:146048$6960 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:145175.7-145175.18" - process $proc$libresoc.v:145175$6977 + attribute \src "libresoc.v:146055.7-146055.18" + process $proc$libresoc.v:146055$6961 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:145189.7-145189.20" - process $proc$libresoc.v:145189$6978 + attribute \src "libresoc.v:146069.7-146069.20" + process $proc$libresoc.v:146069$6962 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:145198.7-145198.20" - process $proc$libresoc.v:145198$6979 + attribute \src "libresoc.v:146078.7-146078.20" + process $proc$libresoc.v:146078$6963 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:145207.7-145207.23" - process $proc$libresoc.v:145207$6980 + attribute \src "libresoc.v:146087.7-146087.23" + process $proc$libresoc.v:146087$6964 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:145215.3-145216.29" - process $proc$libresoc.v:145215$6860 + attribute \src "libresoc.v:146095.3-146096.29" + process $proc$libresoc.v:146095$6844 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:145217.3-145218.35" - process $proc$libresoc.v:145217$6861 + attribute \src "libresoc.v:146097.3-146098.35" + process $proc$libresoc.v:146097$6845 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:145219.3-145220.25" - process $proc$libresoc.v:145219$6862 + attribute \src "libresoc.v:146099.3-146100.25" + process $proc$libresoc.v:146099$6846 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:145221.3-145222.31" - process $proc$libresoc.v:145221$6863 + attribute \src "libresoc.v:146101.3-146102.31" + process $proc$libresoc.v:146101$6847 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:145223.3-145224.19" - process $proc$libresoc.v:145223$6864 + attribute \src "libresoc.v:146103.3-146104.19" + process $proc$libresoc.v:146103$6848 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:145225.3-145226.25" - process $proc$libresoc.v:145225$6865 + attribute \src "libresoc.v:146105.3-146106.25" + process $proc$libresoc.v:146105$6849 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:145227.3-145228.59" - process $proc$libresoc.v:145227$6866 + attribute \src "libresoc.v:146107.3-146108.59" + process $proc$libresoc.v:146107$6850 assign { } { } assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next sync posedge \coresync_clk update \logical_op__insn_type $0\logical_op__insn_type[6:0] end - attribute \src "libresoc.v:145229.3-145230.55" - process $proc$libresoc.v:145229$6867 + attribute \src "libresoc.v:146109.3-146110.55" + process $proc$libresoc.v:146109$6851 assign { } { } assign $0\logical_op__fn_unit[13:0] \logical_op__fn_unit$next sync posedge \coresync_clk update \logical_op__fn_unit $0\logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:145231.3-145232.69" - process $proc$libresoc.v:145231$6868 + attribute \src "libresoc.v:146111.3-146112.69" + process $proc$libresoc.v:146111$6852 assign { } { } assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next sync posedge \coresync_clk update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:145233.3-145234.65" - process $proc$libresoc.v:145233$6869 + attribute \src "libresoc.v:146113.3-146114.65" + process $proc$libresoc.v:146113$6853 assign { } { } assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next sync posedge \coresync_clk update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:145235.3-145236.53" - process $proc$libresoc.v:145235$6870 + attribute \src "libresoc.v:146115.3-146116.53" + process $proc$libresoc.v:146115$6854 assign { } { } assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next sync posedge \coresync_clk update \logical_op__rc__rc $0\logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:145237.3-145238.53" - process $proc$libresoc.v:145237$6871 + attribute \src "libresoc.v:146117.3-146118.53" + process $proc$libresoc.v:146117$6855 assign { } { } assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next sync posedge \coresync_clk update \logical_op__rc__ok $0\logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:145239.3-145240.53" - process $proc$libresoc.v:145239$6872 + attribute \src "libresoc.v:146119.3-146120.53" + process $proc$libresoc.v:146119$6856 assign { } { } assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next sync posedge \coresync_clk update \logical_op__oe__oe $0\logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:145241.3-145242.53" - process $proc$libresoc.v:145241$6873 + attribute \src "libresoc.v:146121.3-146122.53" + process $proc$libresoc.v:146121$6857 assign { } { } assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next sync posedge \coresync_clk update \logical_op__oe__ok $0\logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:145243.3-145244.59" - process $proc$libresoc.v:145243$6874 + attribute \src "libresoc.v:146123.3-146124.59" + process $proc$libresoc.v:146123$6858 assign { } { } assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next sync posedge \coresync_clk update \logical_op__invert_in $0\logical_op__invert_in[0:0] end - attribute \src "libresoc.v:145245.3-145246.53" - process $proc$libresoc.v:145245$6875 + attribute \src "libresoc.v:146125.3-146126.53" + process $proc$libresoc.v:146125$6859 assign { } { } assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next sync posedge \coresync_clk update \logical_op__zero_a $0\logical_op__zero_a[0:0] end - attribute \src "libresoc.v:145247.3-145248.63" - process $proc$libresoc.v:145247$6876 + attribute \src "libresoc.v:146127.3-146128.63" + process $proc$libresoc.v:146127$6860 assign { } { } assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next sync posedge \coresync_clk update \logical_op__input_carry $0\logical_op__input_carry[1:0] end - attribute \src "libresoc.v:145249.3-145250.61" - process $proc$libresoc.v:145249$6877 + attribute \src "libresoc.v:146129.3-146130.61" + process $proc$libresoc.v:146129$6861 assign { } { } assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next sync posedge \coresync_clk update \logical_op__invert_out $0\logical_op__invert_out[0:0] end - attribute \src "libresoc.v:145251.3-145252.59" - process $proc$libresoc.v:145251$6878 + attribute \src "libresoc.v:146131.3-146132.59" + process $proc$libresoc.v:146131$6862 assign { } { } assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next sync posedge \coresync_clk update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:145253.3-145254.65" - process $proc$libresoc.v:145253$6879 + attribute \src "libresoc.v:146133.3-146134.65" + process $proc$libresoc.v:146133$6863 assign { } { } assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next sync posedge \coresync_clk update \logical_op__output_carry $0\logical_op__output_carry[0:0] end - attribute \src "libresoc.v:145255.3-145256.57" - process $proc$libresoc.v:145255$6880 + attribute \src "libresoc.v:146135.3-146136.57" + process $proc$libresoc.v:146135$6864 assign { } { } assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next sync posedge \coresync_clk update \logical_op__is_32bit $0\logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:145257.3-145258.59" - process $proc$libresoc.v:145257$6881 + attribute \src "libresoc.v:146137.3-146138.59" + process $proc$libresoc.v:146137$6865 assign { } { } assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next sync posedge \coresync_clk update \logical_op__is_signed $0\logical_op__is_signed[0:0] end - attribute \src "libresoc.v:145259.3-145260.57" - process $proc$libresoc.v:145259$6882 + attribute \src "libresoc.v:146139.3-146140.57" + process $proc$libresoc.v:146139$6866 assign { } { } assign $0\logical_op__data_len[3:0] \logical_op__data_len$next sync posedge \coresync_clk update \logical_op__data_len $0\logical_op__data_len[3:0] end - attribute \src "libresoc.v:145261.3-145262.49" - process $proc$libresoc.v:145261$6883 + attribute \src "libresoc.v:146141.3-146142.49" + process $proc$libresoc.v:146141$6867 assign { } { } assign $0\logical_op__insn[31:0] \logical_op__insn$next sync posedge \coresync_clk update \logical_op__insn $0\logical_op__insn[31:0] end - attribute \src "libresoc.v:145263.3-145264.27" - process $proc$libresoc.v:145263$6884 + attribute \src "libresoc.v:146143.3-146144.27" + process $proc$libresoc.v:146143$6868 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:145265.3-145266.29" - process $proc$libresoc.v:145265$6885 + attribute \src "libresoc.v:146145.3-146146.29" + process $proc$libresoc.v:146145$6869 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:145367.3-145384.6" - process $proc$libresoc.v:145367$6886 + attribute \src "libresoc.v:146247.3-146264.6" + process $proc$libresoc.v:146247$6870 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$6887 $2\r_busy$next[0:0]$6889 - attribute \src "libresoc.v:145368.5-145368.29" + assign $0\r_busy$next[0:0]$6871 $2\r_busy$next[0:0]$6873 + attribute \src "libresoc.v:146248.5-146248.29" switch \initial - attribute \src "libresoc.v:145368.9-145368.17" + attribute \src "libresoc.v:146248.9-146248.17" case 1'1 case end @@ -236898,34 +237318,34 @@ module \logical_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$6888 1'1 + assign $1\r_busy$next[0:0]$6872 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$6888 1'0 + assign $1\r_busy$next[0:0]$6872 1'0 case - assign $1\r_busy$next[0:0]$6888 \r_busy + assign $1\r_busy$next[0:0]$6872 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$6889 1'0 + assign $2\r_busy$next[0:0]$6873 1'0 case - assign $2\r_busy$next[0:0]$6889 $1\r_busy$next[0:0]$6888 + assign $2\r_busy$next[0:0]$6873 $1\r_busy$next[0:0]$6872 end sync always - update \r_busy$next $0\r_busy$next[0:0]$6887 + update \r_busy$next $0\r_busy$next[0:0]$6871 end - attribute \src "libresoc.v:145385.3-145397.6" - process $proc$libresoc.v:145385$6890 + attribute \src "libresoc.v:146265.3-146277.6" + process $proc$libresoc.v:146265$6874 assign { } { } assign { } { } - assign $0\muxid$next[1:0]$6891 $1\muxid$next[1:0]$6892 - attribute \src "libresoc.v:145386.5-145386.29" + assign $0\muxid$next[1:0]$6875 $1\muxid$next[1:0]$6876 + attribute \src "libresoc.v:146266.5-146266.29" switch \initial - attribute \src "libresoc.v:145386.9-145386.17" + attribute \src "libresoc.v:146266.9-146266.17" case 1'1 case end @@ -236934,19 +237354,19 @@ module \logical_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$next[1:0]$6892 \muxid$66 + assign $1\muxid$next[1:0]$6876 \muxid$66 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$next[1:0]$6892 \muxid$66 + assign $1\muxid$next[1:0]$6876 \muxid$66 case - assign $1\muxid$next[1:0]$6892 \muxid + assign $1\muxid$next[1:0]$6876 \muxid end sync always - update \muxid$next $0\muxid$next[1:0]$6891 + update \muxid$next $0\muxid$next[1:0]$6875 end - attribute \src "libresoc.v:145398.3-145439.6" - process $proc$libresoc.v:145398$6893 + attribute \src "libresoc.v:146278.3-146319.6" + process $proc$libresoc.v:146278$6877 assign { } { } assign { } { } assign { } { } @@ -236983,33 +237403,33 @@ module \logical_pipe1 assign { } { } assign { } { } assign { } { } - assign $0\logical_op__data_len$next[3:0]$6894 $1\logical_op__data_len$next[3:0]$6912 - assign $0\logical_op__fn_unit$next[13:0]$6895 $1\logical_op__fn_unit$next[13:0]$6913 + assign $0\logical_op__data_len$next[3:0]$6878 $1\logical_op__data_len$next[3:0]$6896 + assign $0\logical_op__fn_unit$next[13:0]$6879 $1\logical_op__fn_unit$next[13:0]$6897 assign { } { } assign { } { } - assign $0\logical_op__input_carry$next[1:0]$6898 $1\logical_op__input_carry$next[1:0]$6916 - assign $0\logical_op__insn$next[31:0]$6899 $1\logical_op__insn$next[31:0]$6917 - assign $0\logical_op__insn_type$next[6:0]$6900 $1\logical_op__insn_type$next[6:0]$6918 - assign $0\logical_op__invert_in$next[0:0]$6901 $1\logical_op__invert_in$next[0:0]$6919 - assign $0\logical_op__invert_out$next[0:0]$6902 $1\logical_op__invert_out$next[0:0]$6920 - assign $0\logical_op__is_32bit$next[0:0]$6903 $1\logical_op__is_32bit$next[0:0]$6921 - assign $0\logical_op__is_signed$next[0:0]$6904 $1\logical_op__is_signed$next[0:0]$6922 + assign $0\logical_op__input_carry$next[1:0]$6882 $1\logical_op__input_carry$next[1:0]$6900 + assign $0\logical_op__insn$next[31:0]$6883 $1\logical_op__insn$next[31:0]$6901 + assign $0\logical_op__insn_type$next[6:0]$6884 $1\logical_op__insn_type$next[6:0]$6902 + assign $0\logical_op__invert_in$next[0:0]$6885 $1\logical_op__invert_in$next[0:0]$6903 + assign $0\logical_op__invert_out$next[0:0]$6886 $1\logical_op__invert_out$next[0:0]$6904 + assign $0\logical_op__is_32bit$next[0:0]$6887 $1\logical_op__is_32bit$next[0:0]$6905 + assign $0\logical_op__is_signed$next[0:0]$6888 $1\logical_op__is_signed$next[0:0]$6906 assign { } { } assign { } { } - assign $0\logical_op__output_carry$next[0:0]$6907 $1\logical_op__output_carry$next[0:0]$6925 + assign $0\logical_op__output_carry$next[0:0]$6891 $1\logical_op__output_carry$next[0:0]$6909 assign { } { } assign { } { } - assign $0\logical_op__write_cr0$next[0:0]$6910 $1\logical_op__write_cr0$next[0:0]$6928 - assign $0\logical_op__zero_a$next[0:0]$6911 $1\logical_op__zero_a$next[0:0]$6929 - assign $0\logical_op__imm_data__data$next[63:0]$6896 $2\logical_op__imm_data__data$next[63:0]$6930 - assign $0\logical_op__imm_data__ok$next[0:0]$6897 $2\logical_op__imm_data__ok$next[0:0]$6931 - assign $0\logical_op__oe__oe$next[0:0]$6905 $2\logical_op__oe__oe$next[0:0]$6932 - assign $0\logical_op__oe__ok$next[0:0]$6906 $2\logical_op__oe__ok$next[0:0]$6933 - assign $0\logical_op__rc__ok$next[0:0]$6908 $2\logical_op__rc__ok$next[0:0]$6934 - assign $0\logical_op__rc__rc$next[0:0]$6909 $2\logical_op__rc__rc$next[0:0]$6935 - attribute \src "libresoc.v:145399.5-145399.29" + assign $0\logical_op__write_cr0$next[0:0]$6894 $1\logical_op__write_cr0$next[0:0]$6912 + assign $0\logical_op__zero_a$next[0:0]$6895 $1\logical_op__zero_a$next[0:0]$6913 + assign $0\logical_op__imm_data__data$next[63:0]$6880 $2\logical_op__imm_data__data$next[63:0]$6914 + assign $0\logical_op__imm_data__ok$next[0:0]$6881 $2\logical_op__imm_data__ok$next[0:0]$6915 + assign $0\logical_op__oe__oe$next[0:0]$6889 $2\logical_op__oe__oe$next[0:0]$6916 + assign $0\logical_op__oe__ok$next[0:0]$6890 $2\logical_op__oe__ok$next[0:0]$6917 + assign $0\logical_op__rc__ok$next[0:0]$6892 $2\logical_op__rc__ok$next[0:0]$6918 + assign $0\logical_op__rc__rc$next[0:0]$6893 $2\logical_op__rc__rc$next[0:0]$6919 + attribute \src "libresoc.v:146279.5-146279.29" switch \initial - attribute \src "libresoc.v:145399.9-145399.17" + attribute \src "libresoc.v:146279.9-146279.17" case 1'1 case end @@ -237035,7 +237455,7 @@ module \logical_pipe1 assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$next[31:0]$6917 $1\logical_op__data_len$next[3:0]$6912 $1\logical_op__is_signed$next[0:0]$6922 $1\logical_op__is_32bit$next[0:0]$6921 $1\logical_op__output_carry$next[0:0]$6925 $1\logical_op__write_cr0$next[0:0]$6928 $1\logical_op__invert_out$next[0:0]$6920 $1\logical_op__input_carry$next[1:0]$6916 $1\logical_op__zero_a$next[0:0]$6929 $1\logical_op__invert_in$next[0:0]$6919 $1\logical_op__oe__ok$next[0:0]$6924 $1\logical_op__oe__oe$next[0:0]$6923 $1\logical_op__rc__ok$next[0:0]$6926 $1\logical_op__rc__rc$next[0:0]$6927 $1\logical_op__imm_data__ok$next[0:0]$6915 $1\logical_op__imm_data__data$next[63:0]$6914 $1\logical_op__fn_unit$next[13:0]$6913 $1\logical_op__insn_type$next[6:0]$6918 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } + assign { $1\logical_op__insn$next[31:0]$6901 $1\logical_op__data_len$next[3:0]$6896 $1\logical_op__is_signed$next[0:0]$6906 $1\logical_op__is_32bit$next[0:0]$6905 $1\logical_op__output_carry$next[0:0]$6909 $1\logical_op__write_cr0$next[0:0]$6912 $1\logical_op__invert_out$next[0:0]$6904 $1\logical_op__input_carry$next[1:0]$6900 $1\logical_op__zero_a$next[0:0]$6913 $1\logical_op__invert_in$next[0:0]$6903 $1\logical_op__oe__ok$next[0:0]$6908 $1\logical_op__oe__oe$next[0:0]$6907 $1\logical_op__rc__ok$next[0:0]$6910 $1\logical_op__rc__rc$next[0:0]$6911 $1\logical_op__imm_data__ok$next[0:0]$6899 $1\logical_op__imm_data__data$next[63:0]$6898 $1\logical_op__fn_unit$next[13:0]$6897 $1\logical_op__insn_type$next[6:0]$6902 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -237056,26 +237476,26 @@ module \logical_pipe1 assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$next[31:0]$6917 $1\logical_op__data_len$next[3:0]$6912 $1\logical_op__is_signed$next[0:0]$6922 $1\logical_op__is_32bit$next[0:0]$6921 $1\logical_op__output_carry$next[0:0]$6925 $1\logical_op__write_cr0$next[0:0]$6928 $1\logical_op__invert_out$next[0:0]$6920 $1\logical_op__input_carry$next[1:0]$6916 $1\logical_op__zero_a$next[0:0]$6929 $1\logical_op__invert_in$next[0:0]$6919 $1\logical_op__oe__ok$next[0:0]$6924 $1\logical_op__oe__oe$next[0:0]$6923 $1\logical_op__rc__ok$next[0:0]$6926 $1\logical_op__rc__rc$next[0:0]$6927 $1\logical_op__imm_data__ok$next[0:0]$6915 $1\logical_op__imm_data__data$next[63:0]$6914 $1\logical_op__fn_unit$next[13:0]$6913 $1\logical_op__insn_type$next[6:0]$6918 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } + assign { $1\logical_op__insn$next[31:0]$6901 $1\logical_op__data_len$next[3:0]$6896 $1\logical_op__is_signed$next[0:0]$6906 $1\logical_op__is_32bit$next[0:0]$6905 $1\logical_op__output_carry$next[0:0]$6909 $1\logical_op__write_cr0$next[0:0]$6912 $1\logical_op__invert_out$next[0:0]$6904 $1\logical_op__input_carry$next[1:0]$6900 $1\logical_op__zero_a$next[0:0]$6913 $1\logical_op__invert_in$next[0:0]$6903 $1\logical_op__oe__ok$next[0:0]$6908 $1\logical_op__oe__oe$next[0:0]$6907 $1\logical_op__rc__ok$next[0:0]$6910 $1\logical_op__rc__rc$next[0:0]$6911 $1\logical_op__imm_data__ok$next[0:0]$6899 $1\logical_op__imm_data__data$next[63:0]$6898 $1\logical_op__fn_unit$next[13:0]$6897 $1\logical_op__insn_type$next[6:0]$6902 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } case - assign $1\logical_op__data_len$next[3:0]$6912 \logical_op__data_len - assign $1\logical_op__fn_unit$next[13:0]$6913 \logical_op__fn_unit - assign $1\logical_op__imm_data__data$next[63:0]$6914 \logical_op__imm_data__data - assign $1\logical_op__imm_data__ok$next[0:0]$6915 \logical_op__imm_data__ok - assign $1\logical_op__input_carry$next[1:0]$6916 \logical_op__input_carry - assign $1\logical_op__insn$next[31:0]$6917 \logical_op__insn - assign $1\logical_op__insn_type$next[6:0]$6918 \logical_op__insn_type - assign $1\logical_op__invert_in$next[0:0]$6919 \logical_op__invert_in - assign $1\logical_op__invert_out$next[0:0]$6920 \logical_op__invert_out - assign $1\logical_op__is_32bit$next[0:0]$6921 \logical_op__is_32bit - assign $1\logical_op__is_signed$next[0:0]$6922 \logical_op__is_signed - assign $1\logical_op__oe__oe$next[0:0]$6923 \logical_op__oe__oe - assign $1\logical_op__oe__ok$next[0:0]$6924 \logical_op__oe__ok - assign $1\logical_op__output_carry$next[0:0]$6925 \logical_op__output_carry - assign $1\logical_op__rc__ok$next[0:0]$6926 \logical_op__rc__ok - assign $1\logical_op__rc__rc$next[0:0]$6927 \logical_op__rc__rc - assign $1\logical_op__write_cr0$next[0:0]$6928 \logical_op__write_cr0 - assign $1\logical_op__zero_a$next[0:0]$6929 \logical_op__zero_a + assign $1\logical_op__data_len$next[3:0]$6896 \logical_op__data_len + assign $1\logical_op__fn_unit$next[13:0]$6897 \logical_op__fn_unit + assign $1\logical_op__imm_data__data$next[63:0]$6898 \logical_op__imm_data__data + assign $1\logical_op__imm_data__ok$next[0:0]$6899 \logical_op__imm_data__ok + assign $1\logical_op__input_carry$next[1:0]$6900 \logical_op__input_carry + assign $1\logical_op__insn$next[31:0]$6901 \logical_op__insn + assign $1\logical_op__insn_type$next[6:0]$6902 \logical_op__insn_type + assign $1\logical_op__invert_in$next[0:0]$6903 \logical_op__invert_in + assign $1\logical_op__invert_out$next[0:0]$6904 \logical_op__invert_out + assign $1\logical_op__is_32bit$next[0:0]$6905 \logical_op__is_32bit + assign $1\logical_op__is_signed$next[0:0]$6906 \logical_op__is_signed + assign $1\logical_op__oe__oe$next[0:0]$6907 \logical_op__oe__oe + assign $1\logical_op__oe__ok$next[0:0]$6908 \logical_op__oe__ok + assign $1\logical_op__output_carry$next[0:0]$6909 \logical_op__output_carry + assign $1\logical_op__rc__ok$next[0:0]$6910 \logical_op__rc__ok + assign $1\logical_op__rc__rc$next[0:0]$6911 \logical_op__rc__rc + assign $1\logical_op__write_cr0$next[0:0]$6912 \logical_op__write_cr0 + assign $1\logical_op__zero_a$next[0:0]$6913 \logical_op__zero_a end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -237087,52 +237507,52 @@ module \logical_pipe1 assign { } { } assign { } { } assign { } { } - assign $2\logical_op__imm_data__data$next[63:0]$6930 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\logical_op__imm_data__ok$next[0:0]$6931 1'0 - assign $2\logical_op__rc__rc$next[0:0]$6935 1'0 - assign $2\logical_op__rc__ok$next[0:0]$6934 1'0 - assign $2\logical_op__oe__oe$next[0:0]$6932 1'0 - assign $2\logical_op__oe__ok$next[0:0]$6933 1'0 + assign $2\logical_op__imm_data__data$next[63:0]$6914 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$next[0:0]$6915 1'0 + assign $2\logical_op__rc__rc$next[0:0]$6919 1'0 + assign $2\logical_op__rc__ok$next[0:0]$6918 1'0 + assign $2\logical_op__oe__oe$next[0:0]$6916 1'0 + assign $2\logical_op__oe__ok$next[0:0]$6917 1'0 case - assign $2\logical_op__imm_data__data$next[63:0]$6930 $1\logical_op__imm_data__data$next[63:0]$6914 - assign $2\logical_op__imm_data__ok$next[0:0]$6931 $1\logical_op__imm_data__ok$next[0:0]$6915 - assign $2\logical_op__oe__oe$next[0:0]$6932 $1\logical_op__oe__oe$next[0:0]$6923 - assign $2\logical_op__oe__ok$next[0:0]$6933 $1\logical_op__oe__ok$next[0:0]$6924 - assign $2\logical_op__rc__ok$next[0:0]$6934 $1\logical_op__rc__ok$next[0:0]$6926 - assign $2\logical_op__rc__rc$next[0:0]$6935 $1\logical_op__rc__rc$next[0:0]$6927 + assign $2\logical_op__imm_data__data$next[63:0]$6914 $1\logical_op__imm_data__data$next[63:0]$6898 + assign $2\logical_op__imm_data__ok$next[0:0]$6915 $1\logical_op__imm_data__ok$next[0:0]$6899 + assign $2\logical_op__oe__oe$next[0:0]$6916 $1\logical_op__oe__oe$next[0:0]$6907 + assign $2\logical_op__oe__ok$next[0:0]$6917 $1\logical_op__oe__ok$next[0:0]$6908 + assign $2\logical_op__rc__ok$next[0:0]$6918 $1\logical_op__rc__ok$next[0:0]$6910 + assign $2\logical_op__rc__rc$next[0:0]$6919 $1\logical_op__rc__rc$next[0:0]$6911 end sync always - update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$6894 - update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[13:0]$6895 - update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$6896 - update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$6897 - update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$6898 - update \logical_op__insn$next $0\logical_op__insn$next[31:0]$6899 - update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$6900 - update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$6901 - update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$6902 - update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$6903 - update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$6904 - update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$6905 - update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$6906 - update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$6907 - update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$6908 - update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$6909 - update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$6910 - update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$6911 + update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$6878 + update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[13:0]$6879 + update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$6880 + update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$6881 + update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$6882 + update \logical_op__insn$next $0\logical_op__insn$next[31:0]$6883 + update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$6884 + update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$6885 + update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$6886 + update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$6887 + update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$6888 + update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$6889 + update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$6890 + update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$6891 + update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$6892 + update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$6893 + update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$6894 + update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$6895 end - attribute \src "libresoc.v:145440.3-145458.6" - process $proc$libresoc.v:145440$6936 + attribute \src "libresoc.v:146320.3-146338.6" + process $proc$libresoc.v:146320$6920 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$6937 $1\o$next[63:0]$6939 + assign $0\o$next[63:0]$6921 $1\o$next[63:0]$6923 assign { } { } - assign $0\o_ok$next[0:0]$6938 $2\o_ok$next[0:0]$6941 - attribute \src "libresoc.v:145441.5-145441.29" + assign $0\o_ok$next[0:0]$6922 $2\o_ok$next[0:0]$6925 + attribute \src "libresoc.v:146321.5-146321.29" switch \initial - attribute \src "libresoc.v:145441.9-145441.17" + attribute \src "libresoc.v:146321.9-146321.17" case 1'1 case end @@ -237142,41 +237562,41 @@ module \logical_pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$6940 $1\o$next[63:0]$6939 } { \o_ok$86 \o$85 } + assign { $1\o_ok$next[0:0]$6924 $1\o$next[63:0]$6923 } { \o_ok$86 \o$85 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$6940 $1\o$next[63:0]$6939 } { \o_ok$86 \o$85 } + assign { $1\o_ok$next[0:0]$6924 $1\o$next[63:0]$6923 } { \o_ok$86 \o$85 } case - assign $1\o$next[63:0]$6939 \o - assign $1\o_ok$next[0:0]$6940 \o_ok + assign $1\o$next[63:0]$6923 \o + assign $1\o_ok$next[0:0]$6924 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$6941 1'0 + assign $2\o_ok$next[0:0]$6925 1'0 case - assign $2\o_ok$next[0:0]$6941 $1\o_ok$next[0:0]$6940 + assign $2\o_ok$next[0:0]$6925 $1\o_ok$next[0:0]$6924 end sync always - update \o$next $0\o$next[63:0]$6937 - update \o_ok$next $0\o_ok$next[0:0]$6938 + update \o$next $0\o$next[63:0]$6921 + update \o_ok$next $0\o_ok$next[0:0]$6922 end - attribute \src "libresoc.v:145459.3-145477.6" - process $proc$libresoc.v:145459$6942 + attribute \src "libresoc.v:146339.3-146357.6" + process $proc$libresoc.v:146339$6926 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$next[3:0]$6943 $1\cr_a$next[3:0]$6945 + assign $0\cr_a$next[3:0]$6927 $1\cr_a$next[3:0]$6929 assign { } { } - assign $0\cr_a_ok$next[0:0]$6944 $2\cr_a_ok$next[0:0]$6947 - attribute \src "libresoc.v:145460.5-145460.29" + assign $0\cr_a_ok$next[0:0]$6928 $2\cr_a_ok$next[0:0]$6931 + attribute \src "libresoc.v:146340.5-146340.29" switch \initial - attribute \src "libresoc.v:145460.9-145460.17" + attribute \src "libresoc.v:146340.9-146340.17" case 1'1 case end @@ -237186,41 +237606,41 @@ module \logical_pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$6946 $1\cr_a$next[3:0]$6945 } { \cr_a_ok$88 \cr_a$87 } + assign { $1\cr_a_ok$next[0:0]$6930 $1\cr_a$next[3:0]$6929 } { \cr_a_ok$88 \cr_a$87 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$6946 $1\cr_a$next[3:0]$6945 } { \cr_a_ok$88 \cr_a$87 } + assign { $1\cr_a_ok$next[0:0]$6930 $1\cr_a$next[3:0]$6929 } { \cr_a_ok$88 \cr_a$87 } case - assign $1\cr_a$next[3:0]$6945 \cr_a - assign $1\cr_a_ok$next[0:0]$6946 \cr_a_ok + assign $1\cr_a$next[3:0]$6929 \cr_a + assign $1\cr_a_ok$next[0:0]$6930 \cr_a_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$6947 1'0 + assign $2\cr_a_ok$next[0:0]$6931 1'0 case - assign $2\cr_a_ok$next[0:0]$6947 $1\cr_a_ok$next[0:0]$6946 + assign $2\cr_a_ok$next[0:0]$6931 $1\cr_a_ok$next[0:0]$6930 end sync always - update \cr_a$next $0\cr_a$next[3:0]$6943 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$6944 + update \cr_a$next $0\cr_a$next[3:0]$6927 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$6928 end - attribute \src "libresoc.v:145478.3-145496.6" - process $proc$libresoc.v:145478$6948 + attribute \src "libresoc.v:146358.3-146376.6" + process $proc$libresoc.v:146358$6932 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$next[0:0]$6949 $1\xer_so$next[0:0]$6951 + assign $0\xer_so$next[0:0]$6933 $1\xer_so$next[0:0]$6935 assign { } { } - assign $0\xer_so_ok$next[0:0]$6950 $2\xer_so_ok$next[0:0]$6953 - attribute \src "libresoc.v:145479.5-145479.29" + assign $0\xer_so_ok$next[0:0]$6934 $2\xer_so_ok$next[0:0]$6937 + attribute \src "libresoc.v:146359.5-146359.29" switch \initial - attribute \src "libresoc.v:145479.9-145479.17" + attribute \src "libresoc.v:146359.9-146359.17" case 1'1 case end @@ -237230,30 +237650,30 @@ module \logical_pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$6952 $1\xer_so$next[0:0]$6951 } { \xer_so_ok$92 \xer_so$91 } + assign { $1\xer_so_ok$next[0:0]$6936 $1\xer_so$next[0:0]$6935 } { \xer_so_ok$92 \xer_so$91 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$6952 $1\xer_so$next[0:0]$6951 } { \xer_so_ok$92 \xer_so$91 } + assign { $1\xer_so_ok$next[0:0]$6936 $1\xer_so$next[0:0]$6935 } { \xer_so_ok$92 \xer_so$91 } case - assign $1\xer_so$next[0:0]$6951 \xer_so - assign $1\xer_so_ok$next[0:0]$6952 \xer_so_ok + assign $1\xer_so$next[0:0]$6935 \xer_so + assign $1\xer_so_ok$next[0:0]$6936 \xer_so_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$6953 1'0 + assign $2\xer_so_ok$next[0:0]$6937 1'0 case - assign $2\xer_so_ok$next[0:0]$6953 $1\xer_so_ok$next[0:0]$6952 + assign $2\xer_so_ok$next[0:0]$6937 $1\xer_so_ok$next[0:0]$6936 end sync always - update \xer_so$next $0\xer_so$next[0:0]$6949 - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$6950 + update \xer_so$next $0\xer_so$next[0:0]$6933 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$6934 end - connect \$64 $and$libresoc.v:145214$6859_Y + connect \$64 $and$libresoc.v:146094$6843_Y connect \cr_a$89 4'0000 connect \cr_a_ok$90 1'0 connect \xer_so_ok$93 1'0 @@ -237278,230 +237698,230 @@ module \logical_pipe1 connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:145524.1-146557.10" +attribute \src "libresoc.v:146404.1-147437.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2" attribute \generator "nMigen" module \logical_pipe2 - attribute \src "libresoc.v:146524.3-146542.6" - wire width 4 $0\cr_a$22$next[3:0]$7086 - attribute \src "libresoc.v:146328.3-146329.33" - wire width 4 $0\cr_a$22[3:0]$6983 - attribute \src "libresoc.v:145536.13-145536.29" - wire width 4 $0\cr_a$22[3:0]$7093 - attribute \src "libresoc.v:146524.3-146542.6" - wire $0\cr_a_ok$23$next[0:0]$7087 - attribute \src "libresoc.v:146330.3-146331.39" - wire $0\cr_a_ok$23[0:0]$6985 - attribute \src "libresoc.v:145545.7-145545.26" - wire $0\cr_a_ok$23[0:0]$7095 - attribute \src "libresoc.v:145525.7-145525.20" + attribute \src "libresoc.v:147404.3-147422.6" + wire width 4 $0\cr_a$22$next[3:0]$7070 + attribute \src "libresoc.v:147208.3-147209.33" + wire width 4 $0\cr_a$22[3:0]$6967 + attribute \src "libresoc.v:146416.13-146416.29" + wire width 4 $0\cr_a$22[3:0]$7077 + attribute \src "libresoc.v:147404.3-147422.6" + wire $0\cr_a_ok$23$next[0:0]$7071 + attribute \src "libresoc.v:147210.3-147211.39" + wire $0\cr_a_ok$23[0:0]$6969 + attribute \src "libresoc.v:146425.7-146425.26" + wire $0\cr_a_ok$23[0:0]$7079 + attribute \src "libresoc.v:146405.7-146405.20" wire $0\initial[0:0] - attribute \src "libresoc.v:146463.3-146504.6" - wire width 4 $0\logical_op__data_len$18$next[3:0]$7037 - attribute \src "libresoc.v:146368.3-146369.65" - wire width 4 $0\logical_op__data_len$18[3:0]$7023 - attribute \src "libresoc.v:145556.13-145556.45" - wire width 4 $0\logical_op__data_len$18[3:0]$7097 - attribute \src "libresoc.v:146463.3-146504.6" - wire width 14 $0\logical_op__fn_unit$3$next[13:0]$7038 - attribute \src "libresoc.v:146338.3-146339.61" - wire width 14 $0\logical_op__fn_unit$3[13:0]$6993 - attribute \src "libresoc.v:145595.14-145595.48" - wire width 14 $0\logical_op__fn_unit$3[13:0]$7099 - attribute \src "libresoc.v:146463.3-146504.6" - wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$7039 - attribute \src "libresoc.v:146340.3-146341.75" - wire width 64 $0\logical_op__imm_data__data$4[63:0]$6995 - attribute \src "libresoc.v:145619.14-145619.67" - wire width 64 $0\logical_op__imm_data__data$4[63:0]$7101 - attribute \src "libresoc.v:146463.3-146504.6" - wire $0\logical_op__imm_data__ok$5$next[0:0]$7040 - attribute \src "libresoc.v:146342.3-146343.71" - wire $0\logical_op__imm_data__ok$5[0:0]$6997 - attribute \src "libresoc.v:145628.7-145628.42" - wire $0\logical_op__imm_data__ok$5[0:0]$7103 - attribute \src "libresoc.v:146463.3-146504.6" - wire width 2 $0\logical_op__input_carry$12$next[1:0]$7041 - attribute \src "libresoc.v:146356.3-146357.71" - wire width 2 $0\logical_op__input_carry$12[1:0]$7011 - attribute \src "libresoc.v:145645.13-145645.48" - wire width 2 $0\logical_op__input_carry$12[1:0]$7105 - attribute \src "libresoc.v:146463.3-146504.6" - wire width 32 $0\logical_op__insn$19$next[31:0]$7042 - attribute \src "libresoc.v:146370.3-146371.57" - wire width 32 $0\logical_op__insn$19[31:0]$7025 - attribute \src "libresoc.v:145658.14-145658.43" - wire width 32 $0\logical_op__insn$19[31:0]$7107 - attribute \src "libresoc.v:146463.3-146504.6" - wire width 7 $0\logical_op__insn_type$2$next[6:0]$7043 - attribute \src "libresoc.v:146336.3-146337.65" - wire width 7 $0\logical_op__insn_type$2[6:0]$6991 - attribute \src "libresoc.v:145817.13-145817.46" - wire width 7 $0\logical_op__insn_type$2[6:0]$7109 - attribute \src "libresoc.v:146463.3-146504.6" - wire $0\logical_op__invert_in$10$next[0:0]$7044 - attribute \src "libresoc.v:146352.3-146353.67" - wire $0\logical_op__invert_in$10[0:0]$7007 - attribute \src "libresoc.v:145901.7-145901.40" - wire $0\logical_op__invert_in$10[0:0]$7111 - attribute \src "libresoc.v:146463.3-146504.6" - wire $0\logical_op__invert_out$13$next[0:0]$7045 - attribute \src "libresoc.v:146358.3-146359.69" - wire $0\logical_op__invert_out$13[0:0]$7013 - attribute \src "libresoc.v:145910.7-145910.41" - wire $0\logical_op__invert_out$13[0:0]$7113 - attribute \src "libresoc.v:146463.3-146504.6" - wire $0\logical_op__is_32bit$16$next[0:0]$7046 - attribute \src "libresoc.v:146364.3-146365.65" - wire $0\logical_op__is_32bit$16[0:0]$7019 - attribute \src "libresoc.v:145919.7-145919.39" - wire $0\logical_op__is_32bit$16[0:0]$7115 - attribute \src "libresoc.v:146463.3-146504.6" - wire $0\logical_op__is_signed$17$next[0:0]$7047 - attribute \src "libresoc.v:146366.3-146367.67" - wire $0\logical_op__is_signed$17[0:0]$7021 - attribute \src "libresoc.v:145928.7-145928.40" - wire $0\logical_op__is_signed$17[0:0]$7117 - attribute \src "libresoc.v:146463.3-146504.6" - wire $0\logical_op__oe__oe$8$next[0:0]$7048 - attribute \src "libresoc.v:146348.3-146349.59" - wire $0\logical_op__oe__oe$8[0:0]$7003 - attribute \src "libresoc.v:145939.7-145939.36" - wire $0\logical_op__oe__oe$8[0:0]$7119 - attribute \src "libresoc.v:146463.3-146504.6" - wire $0\logical_op__oe__ok$9$next[0:0]$7049 - attribute \src "libresoc.v:146350.3-146351.59" - wire $0\logical_op__oe__ok$9[0:0]$7005 - attribute \src "libresoc.v:145948.7-145948.36" - wire $0\logical_op__oe__ok$9[0:0]$7121 - attribute \src "libresoc.v:146463.3-146504.6" - wire $0\logical_op__output_carry$15$next[0:0]$7050 - attribute \src "libresoc.v:146362.3-146363.73" - wire $0\logical_op__output_carry$15[0:0]$7017 - attribute \src "libresoc.v:145955.7-145955.43" - wire $0\logical_op__output_carry$15[0:0]$7123 - attribute \src "libresoc.v:146463.3-146504.6" - wire $0\logical_op__rc__ok$7$next[0:0]$7051 - attribute \src "libresoc.v:146346.3-146347.59" - wire $0\logical_op__rc__ok$7[0:0]$7001 - attribute \src "libresoc.v:145966.7-145966.36" - wire $0\logical_op__rc__ok$7[0:0]$7125 - attribute \src "libresoc.v:146463.3-146504.6" - wire $0\logical_op__rc__rc$6$next[0:0]$7052 - attribute \src "libresoc.v:146344.3-146345.59" - wire $0\logical_op__rc__rc$6[0:0]$6999 - attribute \src "libresoc.v:145975.7-145975.36" - wire $0\logical_op__rc__rc$6[0:0]$7127 - attribute \src "libresoc.v:146463.3-146504.6" - wire $0\logical_op__write_cr0$14$next[0:0]$7053 - attribute \src "libresoc.v:146360.3-146361.67" - wire $0\logical_op__write_cr0$14[0:0]$7015 - attribute \src "libresoc.v:145982.7-145982.40" - wire $0\logical_op__write_cr0$14[0:0]$7129 - attribute \src "libresoc.v:146463.3-146504.6" - wire $0\logical_op__zero_a$11$next[0:0]$7054 - attribute \src "libresoc.v:146354.3-146355.61" - wire $0\logical_op__zero_a$11[0:0]$7009 - attribute \src "libresoc.v:145991.7-145991.37" - wire $0\logical_op__zero_a$11[0:0]$7131 - attribute \src "libresoc.v:146450.3-146462.6" - wire width 2 $0\muxid$1$next[1:0]$7034 - attribute \src "libresoc.v:146372.3-146373.33" - wire width 2 $0\muxid$1[1:0]$7027 - attribute \src "libresoc.v:146000.13-146000.29" - wire width 2 $0\muxid$1[1:0]$7133 - attribute \src "libresoc.v:146505.3-146523.6" - wire width 64 $0\o$20$next[63:0]$7080 - attribute \src "libresoc.v:146332.3-146333.27" - wire width 64 $0\o$20[63:0]$6987 - attribute \src "libresoc.v:146015.14-146015.43" - wire width 64 $0\o$20[63:0]$7135 - attribute \src "libresoc.v:146505.3-146523.6" - wire $0\o_ok$21$next[0:0]$7081 - attribute \src "libresoc.v:146334.3-146335.33" - wire $0\o_ok$21[0:0]$6989 - attribute \src "libresoc.v:146024.7-146024.23" - wire $0\o_ok$21[0:0]$7137 - attribute \src "libresoc.v:146432.3-146449.6" - wire $0\r_busy$next[0:0]$7030 - attribute \src "libresoc.v:146374.3-146375.29" + attribute \src "libresoc.v:147343.3-147384.6" + wire width 4 $0\logical_op__data_len$18$next[3:0]$7021 + attribute \src "libresoc.v:147248.3-147249.65" + wire width 4 $0\logical_op__data_len$18[3:0]$7007 + attribute \src "libresoc.v:146436.13-146436.45" + wire width 4 $0\logical_op__data_len$18[3:0]$7081 + attribute \src "libresoc.v:147343.3-147384.6" + wire width 14 $0\logical_op__fn_unit$3$next[13:0]$7022 + attribute \src "libresoc.v:147218.3-147219.61" + wire width 14 $0\logical_op__fn_unit$3[13:0]$6977 + attribute \src "libresoc.v:146475.14-146475.48" + wire width 14 $0\logical_op__fn_unit$3[13:0]$7083 + attribute \src "libresoc.v:147343.3-147384.6" + wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$7023 + attribute \src "libresoc.v:147220.3-147221.75" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$6979 + attribute \src "libresoc.v:146499.14-146499.67" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$7085 + attribute \src "libresoc.v:147343.3-147384.6" + wire $0\logical_op__imm_data__ok$5$next[0:0]$7024 + attribute \src "libresoc.v:147222.3-147223.71" + wire $0\logical_op__imm_data__ok$5[0:0]$6981 + attribute \src "libresoc.v:146508.7-146508.42" + wire $0\logical_op__imm_data__ok$5[0:0]$7087 + attribute \src "libresoc.v:147343.3-147384.6" + wire width 2 $0\logical_op__input_carry$12$next[1:0]$7025 + attribute \src "libresoc.v:147236.3-147237.71" + wire width 2 $0\logical_op__input_carry$12[1:0]$6995 + attribute \src "libresoc.v:146525.13-146525.48" + wire width 2 $0\logical_op__input_carry$12[1:0]$7089 + attribute \src "libresoc.v:147343.3-147384.6" + wire width 32 $0\logical_op__insn$19$next[31:0]$7026 + attribute \src "libresoc.v:147250.3-147251.57" + wire width 32 $0\logical_op__insn$19[31:0]$7009 + attribute \src "libresoc.v:146538.14-146538.43" + wire width 32 $0\logical_op__insn$19[31:0]$7091 + attribute \src "libresoc.v:147343.3-147384.6" + wire width 7 $0\logical_op__insn_type$2$next[6:0]$7027 + attribute \src "libresoc.v:147216.3-147217.65" + wire width 7 $0\logical_op__insn_type$2[6:0]$6975 + attribute \src "libresoc.v:146697.13-146697.46" + wire width 7 $0\logical_op__insn_type$2[6:0]$7093 + attribute \src "libresoc.v:147343.3-147384.6" + wire $0\logical_op__invert_in$10$next[0:0]$7028 + attribute \src "libresoc.v:147232.3-147233.67" + wire $0\logical_op__invert_in$10[0:0]$6991 + attribute \src "libresoc.v:146781.7-146781.40" + wire $0\logical_op__invert_in$10[0:0]$7095 + attribute \src "libresoc.v:147343.3-147384.6" + wire $0\logical_op__invert_out$13$next[0:0]$7029 + attribute \src "libresoc.v:147238.3-147239.69" + wire $0\logical_op__invert_out$13[0:0]$6997 + attribute \src "libresoc.v:146790.7-146790.41" + wire $0\logical_op__invert_out$13[0:0]$7097 + attribute \src "libresoc.v:147343.3-147384.6" + wire $0\logical_op__is_32bit$16$next[0:0]$7030 + attribute \src "libresoc.v:147244.3-147245.65" + wire $0\logical_op__is_32bit$16[0:0]$7003 + attribute \src "libresoc.v:146799.7-146799.39" + wire $0\logical_op__is_32bit$16[0:0]$7099 + attribute \src "libresoc.v:147343.3-147384.6" + wire $0\logical_op__is_signed$17$next[0:0]$7031 + attribute \src "libresoc.v:147246.3-147247.67" + wire $0\logical_op__is_signed$17[0:0]$7005 + attribute \src "libresoc.v:146808.7-146808.40" + wire $0\logical_op__is_signed$17[0:0]$7101 + attribute \src "libresoc.v:147343.3-147384.6" + wire $0\logical_op__oe__oe$8$next[0:0]$7032 + attribute \src "libresoc.v:147228.3-147229.59" + wire $0\logical_op__oe__oe$8[0:0]$6987 + attribute \src "libresoc.v:146819.7-146819.36" + wire $0\logical_op__oe__oe$8[0:0]$7103 + attribute \src "libresoc.v:147343.3-147384.6" + wire $0\logical_op__oe__ok$9$next[0:0]$7033 + attribute \src "libresoc.v:147230.3-147231.59" + wire $0\logical_op__oe__ok$9[0:0]$6989 + attribute \src "libresoc.v:146828.7-146828.36" + wire $0\logical_op__oe__ok$9[0:0]$7105 + attribute \src "libresoc.v:147343.3-147384.6" + wire $0\logical_op__output_carry$15$next[0:0]$7034 + attribute \src "libresoc.v:147242.3-147243.73" + wire $0\logical_op__output_carry$15[0:0]$7001 + attribute \src "libresoc.v:146835.7-146835.43" + wire $0\logical_op__output_carry$15[0:0]$7107 + attribute \src "libresoc.v:147343.3-147384.6" + wire $0\logical_op__rc__ok$7$next[0:0]$7035 + attribute \src "libresoc.v:147226.3-147227.59" + wire $0\logical_op__rc__ok$7[0:0]$6985 + attribute \src "libresoc.v:146846.7-146846.36" + wire $0\logical_op__rc__ok$7[0:0]$7109 + attribute \src "libresoc.v:147343.3-147384.6" + wire $0\logical_op__rc__rc$6$next[0:0]$7036 + attribute \src "libresoc.v:147224.3-147225.59" + wire $0\logical_op__rc__rc$6[0:0]$6983 + attribute \src "libresoc.v:146855.7-146855.36" + wire $0\logical_op__rc__rc$6[0:0]$7111 + attribute \src "libresoc.v:147343.3-147384.6" + wire $0\logical_op__write_cr0$14$next[0:0]$7037 + attribute \src "libresoc.v:147240.3-147241.67" + wire $0\logical_op__write_cr0$14[0:0]$6999 + attribute \src "libresoc.v:146862.7-146862.40" + wire $0\logical_op__write_cr0$14[0:0]$7113 + attribute \src "libresoc.v:147343.3-147384.6" + wire $0\logical_op__zero_a$11$next[0:0]$7038 + attribute \src "libresoc.v:147234.3-147235.61" + wire $0\logical_op__zero_a$11[0:0]$6993 + attribute \src "libresoc.v:146871.7-146871.37" + wire $0\logical_op__zero_a$11[0:0]$7115 + attribute \src "libresoc.v:147330.3-147342.6" + wire width 2 $0\muxid$1$next[1:0]$7018 + attribute \src "libresoc.v:147252.3-147253.33" + wire width 2 $0\muxid$1[1:0]$7011 + attribute \src "libresoc.v:146880.13-146880.29" + wire width 2 $0\muxid$1[1:0]$7117 + attribute \src "libresoc.v:147385.3-147403.6" + wire width 64 $0\o$20$next[63:0]$7064 + attribute \src "libresoc.v:147212.3-147213.27" + wire width 64 $0\o$20[63:0]$6971 + attribute \src "libresoc.v:146895.14-146895.43" + wire width 64 $0\o$20[63:0]$7119 + attribute \src "libresoc.v:147385.3-147403.6" + wire $0\o_ok$21$next[0:0]$7065 + attribute \src "libresoc.v:147214.3-147215.33" + wire $0\o_ok$21[0:0]$6973 + attribute \src "libresoc.v:146904.7-146904.23" + wire $0\o_ok$21[0:0]$7121 + attribute \src "libresoc.v:147312.3-147329.6" + wire $0\r_busy$next[0:0]$7014 + attribute \src "libresoc.v:147254.3-147255.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:146524.3-146542.6" - wire width 4 $1\cr_a$22$next[3:0]$7088 - attribute \src "libresoc.v:146524.3-146542.6" - wire $1\cr_a_ok$23$next[0:0]$7089 - attribute \src "libresoc.v:146463.3-146504.6" - wire width 4 $1\logical_op__data_len$18$next[3:0]$7055 - attribute \src "libresoc.v:146463.3-146504.6" - wire width 14 $1\logical_op__fn_unit$3$next[13:0]$7056 - attribute \src "libresoc.v:146463.3-146504.6" - wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$7057 - attribute \src "libresoc.v:146463.3-146504.6" - wire $1\logical_op__imm_data__ok$5$next[0:0]$7058 - attribute \src "libresoc.v:146463.3-146504.6" - wire width 2 $1\logical_op__input_carry$12$next[1:0]$7059 - attribute \src "libresoc.v:146463.3-146504.6" - wire width 32 $1\logical_op__insn$19$next[31:0]$7060 - attribute \src "libresoc.v:146463.3-146504.6" - wire width 7 $1\logical_op__insn_type$2$next[6:0]$7061 - attribute \src "libresoc.v:146463.3-146504.6" - wire $1\logical_op__invert_in$10$next[0:0]$7062 - attribute \src "libresoc.v:146463.3-146504.6" - wire $1\logical_op__invert_out$13$next[0:0]$7063 - attribute \src "libresoc.v:146463.3-146504.6" - wire $1\logical_op__is_32bit$16$next[0:0]$7064 - attribute \src "libresoc.v:146463.3-146504.6" - wire $1\logical_op__is_signed$17$next[0:0]$7065 - attribute \src "libresoc.v:146463.3-146504.6" - wire $1\logical_op__oe__oe$8$next[0:0]$7066 - attribute \src "libresoc.v:146463.3-146504.6" - wire $1\logical_op__oe__ok$9$next[0:0]$7067 - attribute \src "libresoc.v:146463.3-146504.6" - wire $1\logical_op__output_carry$15$next[0:0]$7068 - attribute \src "libresoc.v:146463.3-146504.6" - wire $1\logical_op__rc__ok$7$next[0:0]$7069 - attribute \src "libresoc.v:146463.3-146504.6" - wire $1\logical_op__rc__rc$6$next[0:0]$7070 - attribute \src "libresoc.v:146463.3-146504.6" - wire $1\logical_op__write_cr0$14$next[0:0]$7071 - attribute \src "libresoc.v:146463.3-146504.6" - wire $1\logical_op__zero_a$11$next[0:0]$7072 - attribute \src "libresoc.v:146450.3-146462.6" - wire width 2 $1\muxid$1$next[1:0]$7035 - attribute \src "libresoc.v:146505.3-146523.6" - wire width 64 $1\o$20$next[63:0]$7082 - attribute \src "libresoc.v:146505.3-146523.6" - wire $1\o_ok$21$next[0:0]$7083 - attribute \src "libresoc.v:146432.3-146449.6" - wire $1\r_busy$next[0:0]$7031 - attribute \src "libresoc.v:146318.7-146318.20" + attribute \src "libresoc.v:147404.3-147422.6" + wire width 4 $1\cr_a$22$next[3:0]$7072 + attribute \src "libresoc.v:147404.3-147422.6" + wire $1\cr_a_ok$23$next[0:0]$7073 + attribute \src "libresoc.v:147343.3-147384.6" + wire width 4 $1\logical_op__data_len$18$next[3:0]$7039 + attribute \src "libresoc.v:147343.3-147384.6" + wire width 14 $1\logical_op__fn_unit$3$next[13:0]$7040 + attribute \src "libresoc.v:147343.3-147384.6" + wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$7041 + attribute \src "libresoc.v:147343.3-147384.6" + wire $1\logical_op__imm_data__ok$5$next[0:0]$7042 + attribute \src "libresoc.v:147343.3-147384.6" + wire width 2 $1\logical_op__input_carry$12$next[1:0]$7043 + attribute \src "libresoc.v:147343.3-147384.6" + wire width 32 $1\logical_op__insn$19$next[31:0]$7044 + attribute \src "libresoc.v:147343.3-147384.6" + wire width 7 $1\logical_op__insn_type$2$next[6:0]$7045 + attribute \src "libresoc.v:147343.3-147384.6" + wire $1\logical_op__invert_in$10$next[0:0]$7046 + attribute \src "libresoc.v:147343.3-147384.6" + wire $1\logical_op__invert_out$13$next[0:0]$7047 + attribute \src "libresoc.v:147343.3-147384.6" + wire $1\logical_op__is_32bit$16$next[0:0]$7048 + attribute \src "libresoc.v:147343.3-147384.6" + wire $1\logical_op__is_signed$17$next[0:0]$7049 + attribute \src "libresoc.v:147343.3-147384.6" + wire $1\logical_op__oe__oe$8$next[0:0]$7050 + attribute \src "libresoc.v:147343.3-147384.6" + wire $1\logical_op__oe__ok$9$next[0:0]$7051 + attribute \src "libresoc.v:147343.3-147384.6" + wire $1\logical_op__output_carry$15$next[0:0]$7052 + attribute \src "libresoc.v:147343.3-147384.6" + wire $1\logical_op__rc__ok$7$next[0:0]$7053 + attribute \src "libresoc.v:147343.3-147384.6" + wire $1\logical_op__rc__rc$6$next[0:0]$7054 + attribute \src "libresoc.v:147343.3-147384.6" + wire $1\logical_op__write_cr0$14$next[0:0]$7055 + attribute \src "libresoc.v:147343.3-147384.6" + wire $1\logical_op__zero_a$11$next[0:0]$7056 + attribute \src "libresoc.v:147330.3-147342.6" + wire width 2 $1\muxid$1$next[1:0]$7019 + attribute \src "libresoc.v:147385.3-147403.6" + wire width 64 $1\o$20$next[63:0]$7066 + attribute \src "libresoc.v:147385.3-147403.6" + wire $1\o_ok$21$next[0:0]$7067 + attribute \src "libresoc.v:147312.3-147329.6" + wire $1\r_busy$next[0:0]$7015 + attribute \src "libresoc.v:147198.7-147198.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:146524.3-146542.6" - wire $2\cr_a_ok$23$next[0:0]$7090 - attribute \src "libresoc.v:146463.3-146504.6" - wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$7073 - attribute \src "libresoc.v:146463.3-146504.6" - wire $2\logical_op__imm_data__ok$5$next[0:0]$7074 - attribute \src "libresoc.v:146463.3-146504.6" - wire $2\logical_op__oe__oe$8$next[0:0]$7075 - attribute \src "libresoc.v:146463.3-146504.6" - wire $2\logical_op__oe__ok$9$next[0:0]$7076 - attribute \src "libresoc.v:146463.3-146504.6" - wire $2\logical_op__rc__ok$7$next[0:0]$7077 - attribute \src "libresoc.v:146463.3-146504.6" - wire $2\logical_op__rc__rc$6$next[0:0]$7078 - attribute \src "libresoc.v:146505.3-146523.6" - wire $2\o_ok$21$next[0:0]$7084 - attribute \src "libresoc.v:146432.3-146449.6" - wire $2\r_busy$next[0:0]$7032 - attribute \src "libresoc.v:146327.18-146327.118" - wire $and$libresoc.v:146327$6981_Y + attribute \src "libresoc.v:147404.3-147422.6" + wire $2\cr_a_ok$23$next[0:0]$7074 + attribute \src "libresoc.v:147343.3-147384.6" + wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$7057 + attribute \src "libresoc.v:147343.3-147384.6" + wire $2\logical_op__imm_data__ok$5$next[0:0]$7058 + attribute \src "libresoc.v:147343.3-147384.6" + wire $2\logical_op__oe__oe$8$next[0:0]$7059 + attribute \src "libresoc.v:147343.3-147384.6" + wire $2\logical_op__oe__ok$9$next[0:0]$7060 + attribute \src "libresoc.v:147343.3-147384.6" + wire $2\logical_op__rc__ok$7$next[0:0]$7061 + attribute \src "libresoc.v:147343.3-147384.6" + wire $2\logical_op__rc__rc$6$next[0:0]$7062 + attribute \src "libresoc.v:147385.3-147403.6" + wire $2\o_ok$21$next[0:0]$7068 + attribute \src "libresoc.v:147312.3-147329.6" + wire $2\r_busy$next[0:0]$7016 + attribute \src "libresoc.v:147207.18-147207.118" + wire $and$libresoc.v:147207$6965_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 54 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 input 25 \cr_a @@ -237521,7 +237941,7 @@ module \logical_pipe2 wire \cr_a_ok$46 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$73 - attribute \src "libresoc.v:145525.7-145525.15" + attribute \src "libresoc.v:146405.7-146405.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 21 \logical_op__data_len @@ -238278,7 +238698,7 @@ module \logical_pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$47 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:146327$6981 + cell $and $and$libresoc.v:147207$6965 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -238286,16 +238706,16 @@ module \logical_pipe2 parameter \Y_WIDTH 1 connect \A \p_valid_i$48 connect \B \p_ready_o - connect \Y $and$libresoc.v:146327$6981_Y + connect \Y $and$libresoc.v:147207$6965_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:146376.10-146379.4" + attribute \src "libresoc.v:147256.10-147259.4" cell \n$53 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:146380.15-146427.4" + attribute \src "libresoc.v:147260.15-147307.4" cell \output$54 \output connect \cr_a \output_cr_a connect \cr_a$22 \output_cr_a$45 @@ -238345,388 +238765,388 @@ module \logical_pipe2 connect \xer_so \output_xer_so end attribute \module_not_derived 1 - attribute \src "libresoc.v:146428.10-146431.4" + attribute \src "libresoc.v:147308.10-147311.4" cell \p$52 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:145525.7-145525.20" - process $proc$libresoc.v:145525$7091 + attribute \src "libresoc.v:146405.7-146405.20" + process $proc$libresoc.v:146405$7075 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:145536.13-145536.29" - process $proc$libresoc.v:145536$7092 + attribute \src "libresoc.v:146416.13-146416.29" + process $proc$libresoc.v:146416$7076 assign { } { } - assign $0\cr_a$22[3:0]$7093 4'0000 + assign $0\cr_a$22[3:0]$7077 4'0000 sync always sync init - update \cr_a$22 $0\cr_a$22[3:0]$7093 + update \cr_a$22 $0\cr_a$22[3:0]$7077 end - attribute \src "libresoc.v:145545.7-145545.26" - process $proc$libresoc.v:145545$7094 + attribute \src "libresoc.v:146425.7-146425.26" + process $proc$libresoc.v:146425$7078 assign { } { } - assign $0\cr_a_ok$23[0:0]$7095 1'0 + assign $0\cr_a_ok$23[0:0]$7079 1'0 sync always sync init - update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$7095 + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$7079 end - attribute \src "libresoc.v:145556.13-145556.45" - process $proc$libresoc.v:145556$7096 + attribute \src "libresoc.v:146436.13-146436.45" + process $proc$libresoc.v:146436$7080 assign { } { } - assign $0\logical_op__data_len$18[3:0]$7097 4'0000 + assign $0\logical_op__data_len$18[3:0]$7081 4'0000 sync always sync init - update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$7097 + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$7081 end - attribute \src "libresoc.v:145595.14-145595.48" - process $proc$libresoc.v:145595$7098 + attribute \src "libresoc.v:146475.14-146475.48" + process $proc$libresoc.v:146475$7082 assign { } { } - assign $0\logical_op__fn_unit$3[13:0]$7099 14'00000000000000 + assign $0\logical_op__fn_unit$3[13:0]$7083 14'00000000000000 sync always sync init - update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$7099 + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$7083 end - attribute \src "libresoc.v:145619.14-145619.67" - process $proc$libresoc.v:145619$7100 + attribute \src "libresoc.v:146499.14-146499.67" + process $proc$libresoc.v:146499$7084 assign { } { } - assign $0\logical_op__imm_data__data$4[63:0]$7101 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\logical_op__imm_data__data$4[63:0]$7085 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$7101 + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$7085 end - attribute \src "libresoc.v:145628.7-145628.42" - process $proc$libresoc.v:145628$7102 + attribute \src "libresoc.v:146508.7-146508.42" + process $proc$libresoc.v:146508$7086 assign { } { } - assign $0\logical_op__imm_data__ok$5[0:0]$7103 1'0 + assign $0\logical_op__imm_data__ok$5[0:0]$7087 1'0 sync always sync init - update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$7103 + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$7087 end - attribute \src "libresoc.v:145645.13-145645.48" - process $proc$libresoc.v:145645$7104 + attribute \src "libresoc.v:146525.13-146525.48" + process $proc$libresoc.v:146525$7088 assign { } { } - assign $0\logical_op__input_carry$12[1:0]$7105 2'00 + assign $0\logical_op__input_carry$12[1:0]$7089 2'00 sync always sync init - update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$7105 + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$7089 end - attribute \src "libresoc.v:145658.14-145658.43" - process $proc$libresoc.v:145658$7106 + attribute \src "libresoc.v:146538.14-146538.43" + process $proc$libresoc.v:146538$7090 assign { } { } - assign $0\logical_op__insn$19[31:0]$7107 0 + assign $0\logical_op__insn$19[31:0]$7091 0 sync always sync init - update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$7107 + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$7091 end - attribute \src "libresoc.v:145817.13-145817.46" - process $proc$libresoc.v:145817$7108 + attribute \src "libresoc.v:146697.13-146697.46" + process $proc$libresoc.v:146697$7092 assign { } { } - assign $0\logical_op__insn_type$2[6:0]$7109 7'0000000 + assign $0\logical_op__insn_type$2[6:0]$7093 7'0000000 sync always sync init - update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$7109 + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$7093 end - attribute \src "libresoc.v:145901.7-145901.40" - process $proc$libresoc.v:145901$7110 + attribute \src "libresoc.v:146781.7-146781.40" + process $proc$libresoc.v:146781$7094 assign { } { } - assign $0\logical_op__invert_in$10[0:0]$7111 1'0 + assign $0\logical_op__invert_in$10[0:0]$7095 1'0 sync always sync init - update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$7111 + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$7095 end - attribute \src "libresoc.v:145910.7-145910.41" - process $proc$libresoc.v:145910$7112 + attribute \src "libresoc.v:146790.7-146790.41" + process $proc$libresoc.v:146790$7096 assign { } { } - assign $0\logical_op__invert_out$13[0:0]$7113 1'0 + assign $0\logical_op__invert_out$13[0:0]$7097 1'0 sync always sync init - update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$7113 + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$7097 end - attribute \src "libresoc.v:145919.7-145919.39" - process $proc$libresoc.v:145919$7114 + attribute \src "libresoc.v:146799.7-146799.39" + process $proc$libresoc.v:146799$7098 assign { } { } - assign $0\logical_op__is_32bit$16[0:0]$7115 1'0 + assign $0\logical_op__is_32bit$16[0:0]$7099 1'0 sync always sync init - update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$7115 + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$7099 end - attribute \src "libresoc.v:145928.7-145928.40" - process $proc$libresoc.v:145928$7116 + attribute \src "libresoc.v:146808.7-146808.40" + process $proc$libresoc.v:146808$7100 assign { } { } - assign $0\logical_op__is_signed$17[0:0]$7117 1'0 + assign $0\logical_op__is_signed$17[0:0]$7101 1'0 sync always sync init - update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$7117 + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$7101 end - attribute \src "libresoc.v:145939.7-145939.36" - process $proc$libresoc.v:145939$7118 + attribute \src "libresoc.v:146819.7-146819.36" + process $proc$libresoc.v:146819$7102 assign { } { } - assign $0\logical_op__oe__oe$8[0:0]$7119 1'0 + assign $0\logical_op__oe__oe$8[0:0]$7103 1'0 sync always sync init - update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$7119 + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$7103 end - attribute \src "libresoc.v:145948.7-145948.36" - process $proc$libresoc.v:145948$7120 + attribute \src "libresoc.v:146828.7-146828.36" + process $proc$libresoc.v:146828$7104 assign { } { } - assign $0\logical_op__oe__ok$9[0:0]$7121 1'0 + assign $0\logical_op__oe__ok$9[0:0]$7105 1'0 sync always sync init - update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$7121 + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$7105 end - attribute \src "libresoc.v:145955.7-145955.43" - process $proc$libresoc.v:145955$7122 + attribute \src "libresoc.v:146835.7-146835.43" + process $proc$libresoc.v:146835$7106 assign { } { } - assign $0\logical_op__output_carry$15[0:0]$7123 1'0 + assign $0\logical_op__output_carry$15[0:0]$7107 1'0 sync always sync init - update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$7123 + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$7107 end - attribute \src "libresoc.v:145966.7-145966.36" - process $proc$libresoc.v:145966$7124 + attribute \src "libresoc.v:146846.7-146846.36" + process $proc$libresoc.v:146846$7108 assign { } { } - assign $0\logical_op__rc__ok$7[0:0]$7125 1'0 + assign $0\logical_op__rc__ok$7[0:0]$7109 1'0 sync always sync init - update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$7125 + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$7109 end - attribute \src "libresoc.v:145975.7-145975.36" - process $proc$libresoc.v:145975$7126 + attribute \src "libresoc.v:146855.7-146855.36" + process $proc$libresoc.v:146855$7110 assign { } { } - assign $0\logical_op__rc__rc$6[0:0]$7127 1'0 + assign $0\logical_op__rc__rc$6[0:0]$7111 1'0 sync always sync init - update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$7127 + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$7111 end - attribute \src "libresoc.v:145982.7-145982.40" - process $proc$libresoc.v:145982$7128 + attribute \src "libresoc.v:146862.7-146862.40" + process $proc$libresoc.v:146862$7112 assign { } { } - assign $0\logical_op__write_cr0$14[0:0]$7129 1'0 + assign $0\logical_op__write_cr0$14[0:0]$7113 1'0 sync always sync init - update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$7129 + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$7113 end - attribute \src "libresoc.v:145991.7-145991.37" - process $proc$libresoc.v:145991$7130 + attribute \src "libresoc.v:146871.7-146871.37" + process $proc$libresoc.v:146871$7114 assign { } { } - assign $0\logical_op__zero_a$11[0:0]$7131 1'0 + assign $0\logical_op__zero_a$11[0:0]$7115 1'0 sync always sync init - update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$7131 + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$7115 end - attribute \src "libresoc.v:146000.13-146000.29" - process $proc$libresoc.v:146000$7132 + attribute \src "libresoc.v:146880.13-146880.29" + process $proc$libresoc.v:146880$7116 assign { } { } - assign $0\muxid$1[1:0]$7133 2'00 + assign $0\muxid$1[1:0]$7117 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$7133 + update \muxid$1 $0\muxid$1[1:0]$7117 end - attribute \src "libresoc.v:146015.14-146015.43" - process $proc$libresoc.v:146015$7134 + attribute \src "libresoc.v:146895.14-146895.43" + process $proc$libresoc.v:146895$7118 assign { } { } - assign $0\o$20[63:0]$7135 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\o$20[63:0]$7119 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \o$20 $0\o$20[63:0]$7135 + update \o$20 $0\o$20[63:0]$7119 end - attribute \src "libresoc.v:146024.7-146024.23" - process $proc$libresoc.v:146024$7136 + attribute \src "libresoc.v:146904.7-146904.23" + process $proc$libresoc.v:146904$7120 assign { } { } - assign $0\o_ok$21[0:0]$7137 1'0 + assign $0\o_ok$21[0:0]$7121 1'0 sync always sync init - update \o_ok$21 $0\o_ok$21[0:0]$7137 + update \o_ok$21 $0\o_ok$21[0:0]$7121 end - attribute \src "libresoc.v:146318.7-146318.20" - process $proc$libresoc.v:146318$7138 + attribute \src "libresoc.v:147198.7-147198.20" + process $proc$libresoc.v:147198$7122 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:146328.3-146329.33" - process $proc$libresoc.v:146328$6982 + attribute \src "libresoc.v:147208.3-147209.33" + process $proc$libresoc.v:147208$6966 assign { } { } - assign $0\cr_a$22[3:0]$6983 \cr_a$22$next + assign $0\cr_a$22[3:0]$6967 \cr_a$22$next sync posedge \coresync_clk - update \cr_a$22 $0\cr_a$22[3:0]$6983 + update \cr_a$22 $0\cr_a$22[3:0]$6967 end - attribute \src "libresoc.v:146330.3-146331.39" - process $proc$libresoc.v:146330$6984 + attribute \src "libresoc.v:147210.3-147211.39" + process $proc$libresoc.v:147210$6968 assign { } { } - assign $0\cr_a_ok$23[0:0]$6985 \cr_a_ok$23$next + assign $0\cr_a_ok$23[0:0]$6969 \cr_a_ok$23$next sync posedge \coresync_clk - update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$6985 + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$6969 end - attribute \src "libresoc.v:146332.3-146333.27" - process $proc$libresoc.v:146332$6986 + attribute \src "libresoc.v:147212.3-147213.27" + process $proc$libresoc.v:147212$6970 assign { } { } - assign $0\o$20[63:0]$6987 \o$20$next + assign $0\o$20[63:0]$6971 \o$20$next sync posedge \coresync_clk - update \o$20 $0\o$20[63:0]$6987 + update \o$20 $0\o$20[63:0]$6971 end - attribute \src "libresoc.v:146334.3-146335.33" - process $proc$libresoc.v:146334$6988 + attribute \src "libresoc.v:147214.3-147215.33" + process $proc$libresoc.v:147214$6972 assign { } { } - assign $0\o_ok$21[0:0]$6989 \o_ok$21$next + assign $0\o_ok$21[0:0]$6973 \o_ok$21$next sync posedge \coresync_clk - update \o_ok$21 $0\o_ok$21[0:0]$6989 + update \o_ok$21 $0\o_ok$21[0:0]$6973 end - attribute \src "libresoc.v:146336.3-146337.65" - process $proc$libresoc.v:146336$6990 + attribute \src "libresoc.v:147216.3-147217.65" + process $proc$libresoc.v:147216$6974 assign { } { } - assign $0\logical_op__insn_type$2[6:0]$6991 \logical_op__insn_type$2$next + assign $0\logical_op__insn_type$2[6:0]$6975 \logical_op__insn_type$2$next sync posedge \coresync_clk - update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$6991 + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$6975 end - attribute \src "libresoc.v:146338.3-146339.61" - process $proc$libresoc.v:146338$6992 + attribute \src "libresoc.v:147218.3-147219.61" + process $proc$libresoc.v:147218$6976 assign { } { } - assign $0\logical_op__fn_unit$3[13:0]$6993 \logical_op__fn_unit$3$next + assign $0\logical_op__fn_unit$3[13:0]$6977 \logical_op__fn_unit$3$next sync posedge \coresync_clk - update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$6993 + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$6977 end - attribute \src "libresoc.v:146340.3-146341.75" - process $proc$libresoc.v:146340$6994 + attribute \src "libresoc.v:147220.3-147221.75" + process $proc$libresoc.v:147220$6978 assign { } { } - assign $0\logical_op__imm_data__data$4[63:0]$6995 \logical_op__imm_data__data$4$next + assign $0\logical_op__imm_data__data$4[63:0]$6979 \logical_op__imm_data__data$4$next sync posedge \coresync_clk - update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$6995 + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$6979 end - attribute \src "libresoc.v:146342.3-146343.71" - process $proc$libresoc.v:146342$6996 + attribute \src "libresoc.v:147222.3-147223.71" + process $proc$libresoc.v:147222$6980 assign { } { } - assign $0\logical_op__imm_data__ok$5[0:0]$6997 \logical_op__imm_data__ok$5$next + assign $0\logical_op__imm_data__ok$5[0:0]$6981 \logical_op__imm_data__ok$5$next sync posedge \coresync_clk - update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$6997 + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$6981 end - attribute \src "libresoc.v:146344.3-146345.59" - process $proc$libresoc.v:146344$6998 + attribute \src "libresoc.v:147224.3-147225.59" + process $proc$libresoc.v:147224$6982 assign { } { } - assign $0\logical_op__rc__rc$6[0:0]$6999 \logical_op__rc__rc$6$next + assign $0\logical_op__rc__rc$6[0:0]$6983 \logical_op__rc__rc$6$next sync posedge \coresync_clk - update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$6999 + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$6983 end - attribute \src "libresoc.v:146346.3-146347.59" - process $proc$libresoc.v:146346$7000 + attribute \src "libresoc.v:147226.3-147227.59" + process $proc$libresoc.v:147226$6984 assign { } { } - assign $0\logical_op__rc__ok$7[0:0]$7001 \logical_op__rc__ok$7$next + assign $0\logical_op__rc__ok$7[0:0]$6985 \logical_op__rc__ok$7$next sync posedge \coresync_clk - update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$7001 + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$6985 end - attribute \src "libresoc.v:146348.3-146349.59" - process $proc$libresoc.v:146348$7002 + attribute \src "libresoc.v:147228.3-147229.59" + process $proc$libresoc.v:147228$6986 assign { } { } - assign $0\logical_op__oe__oe$8[0:0]$7003 \logical_op__oe__oe$8$next + assign $0\logical_op__oe__oe$8[0:0]$6987 \logical_op__oe__oe$8$next sync posedge \coresync_clk - update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$7003 + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$6987 end - attribute \src "libresoc.v:146350.3-146351.59" - process $proc$libresoc.v:146350$7004 + attribute \src "libresoc.v:147230.3-147231.59" + process $proc$libresoc.v:147230$6988 assign { } { } - assign $0\logical_op__oe__ok$9[0:0]$7005 \logical_op__oe__ok$9$next + assign $0\logical_op__oe__ok$9[0:0]$6989 \logical_op__oe__ok$9$next sync posedge \coresync_clk - update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$7005 + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$6989 end - attribute \src "libresoc.v:146352.3-146353.67" - process $proc$libresoc.v:146352$7006 + attribute \src "libresoc.v:147232.3-147233.67" + process $proc$libresoc.v:147232$6990 assign { } { } - assign $0\logical_op__invert_in$10[0:0]$7007 \logical_op__invert_in$10$next + assign $0\logical_op__invert_in$10[0:0]$6991 \logical_op__invert_in$10$next sync posedge \coresync_clk - update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$7007 + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$6991 end - attribute \src "libresoc.v:146354.3-146355.61" - process $proc$libresoc.v:146354$7008 + attribute \src "libresoc.v:147234.3-147235.61" + process $proc$libresoc.v:147234$6992 assign { } { } - assign $0\logical_op__zero_a$11[0:0]$7009 \logical_op__zero_a$11$next + assign $0\logical_op__zero_a$11[0:0]$6993 \logical_op__zero_a$11$next sync posedge \coresync_clk - update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$7009 + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$6993 end - attribute \src "libresoc.v:146356.3-146357.71" - process $proc$libresoc.v:146356$7010 + attribute \src "libresoc.v:147236.3-147237.71" + process $proc$libresoc.v:147236$6994 assign { } { } - assign $0\logical_op__input_carry$12[1:0]$7011 \logical_op__input_carry$12$next + assign $0\logical_op__input_carry$12[1:0]$6995 \logical_op__input_carry$12$next sync posedge \coresync_clk - update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$7011 + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$6995 end - attribute \src "libresoc.v:146358.3-146359.69" - process $proc$libresoc.v:146358$7012 + attribute \src "libresoc.v:147238.3-147239.69" + process $proc$libresoc.v:147238$6996 assign { } { } - assign $0\logical_op__invert_out$13[0:0]$7013 \logical_op__invert_out$13$next + assign $0\logical_op__invert_out$13[0:0]$6997 \logical_op__invert_out$13$next sync posedge \coresync_clk - update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$7013 + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$6997 end - attribute \src "libresoc.v:146360.3-146361.67" - process $proc$libresoc.v:146360$7014 + attribute \src "libresoc.v:147240.3-147241.67" + process $proc$libresoc.v:147240$6998 assign { } { } - assign $0\logical_op__write_cr0$14[0:0]$7015 \logical_op__write_cr0$14$next + assign $0\logical_op__write_cr0$14[0:0]$6999 \logical_op__write_cr0$14$next sync posedge \coresync_clk - update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$7015 + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$6999 end - attribute \src "libresoc.v:146362.3-146363.73" - process $proc$libresoc.v:146362$7016 + attribute \src "libresoc.v:147242.3-147243.73" + process $proc$libresoc.v:147242$7000 assign { } { } - assign $0\logical_op__output_carry$15[0:0]$7017 \logical_op__output_carry$15$next + assign $0\logical_op__output_carry$15[0:0]$7001 \logical_op__output_carry$15$next sync posedge \coresync_clk - update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$7017 + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$7001 end - attribute \src "libresoc.v:146364.3-146365.65" - process $proc$libresoc.v:146364$7018 + attribute \src "libresoc.v:147244.3-147245.65" + process $proc$libresoc.v:147244$7002 assign { } { } - assign $0\logical_op__is_32bit$16[0:0]$7019 \logical_op__is_32bit$16$next + assign $0\logical_op__is_32bit$16[0:0]$7003 \logical_op__is_32bit$16$next sync posedge \coresync_clk - update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$7019 + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$7003 end - attribute \src "libresoc.v:146366.3-146367.67" - process $proc$libresoc.v:146366$7020 + attribute \src "libresoc.v:147246.3-147247.67" + process $proc$libresoc.v:147246$7004 assign { } { } - assign $0\logical_op__is_signed$17[0:0]$7021 \logical_op__is_signed$17$next + assign $0\logical_op__is_signed$17[0:0]$7005 \logical_op__is_signed$17$next sync posedge \coresync_clk - update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$7021 + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$7005 end - attribute \src "libresoc.v:146368.3-146369.65" - process $proc$libresoc.v:146368$7022 + attribute \src "libresoc.v:147248.3-147249.65" + process $proc$libresoc.v:147248$7006 assign { } { } - assign $0\logical_op__data_len$18[3:0]$7023 \logical_op__data_len$18$next + assign $0\logical_op__data_len$18[3:0]$7007 \logical_op__data_len$18$next sync posedge \coresync_clk - update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$7023 + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$7007 end - attribute \src "libresoc.v:146370.3-146371.57" - process $proc$libresoc.v:146370$7024 + attribute \src "libresoc.v:147250.3-147251.57" + process $proc$libresoc.v:147250$7008 assign { } { } - assign $0\logical_op__insn$19[31:0]$7025 \logical_op__insn$19$next + assign $0\logical_op__insn$19[31:0]$7009 \logical_op__insn$19$next sync posedge \coresync_clk - update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$7025 + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$7009 end - attribute \src "libresoc.v:146372.3-146373.33" - process $proc$libresoc.v:146372$7026 + attribute \src "libresoc.v:147252.3-147253.33" + process $proc$libresoc.v:147252$7010 assign { } { } - assign $0\muxid$1[1:0]$7027 \muxid$1$next + assign $0\muxid$1[1:0]$7011 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$7027 + update \muxid$1 $0\muxid$1[1:0]$7011 end - attribute \src "libresoc.v:146374.3-146375.29" - process $proc$libresoc.v:146374$7028 + attribute \src "libresoc.v:147254.3-147255.29" + process $proc$libresoc.v:147254$7012 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:146432.3-146449.6" - process $proc$libresoc.v:146432$7029 + attribute \src "libresoc.v:147312.3-147329.6" + process $proc$libresoc.v:147312$7013 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$7030 $2\r_busy$next[0:0]$7032 - attribute \src "libresoc.v:146433.5-146433.29" + assign $0\r_busy$next[0:0]$7014 $2\r_busy$next[0:0]$7016 + attribute \src "libresoc.v:147313.5-147313.29" switch \initial - attribute \src "libresoc.v:146433.9-146433.17" + attribute \src "libresoc.v:147313.9-147313.17" case 1'1 case end @@ -238735,34 +239155,34 @@ module \logical_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$7031 1'1 + assign $1\r_busy$next[0:0]$7015 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$7031 1'0 + assign $1\r_busy$next[0:0]$7015 1'0 case - assign $1\r_busy$next[0:0]$7031 \r_busy + assign $1\r_busy$next[0:0]$7015 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$7032 1'0 + assign $2\r_busy$next[0:0]$7016 1'0 case - assign $2\r_busy$next[0:0]$7032 $1\r_busy$next[0:0]$7031 + assign $2\r_busy$next[0:0]$7016 $1\r_busy$next[0:0]$7015 end sync always - update \r_busy$next $0\r_busy$next[0:0]$7030 + update \r_busy$next $0\r_busy$next[0:0]$7014 end - attribute \src "libresoc.v:146450.3-146462.6" - process $proc$libresoc.v:146450$7033 + attribute \src "libresoc.v:147330.3-147342.6" + process $proc$libresoc.v:147330$7017 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$7034 $1\muxid$1$next[1:0]$7035 - attribute \src "libresoc.v:146451.5-146451.29" + assign $0\muxid$1$next[1:0]$7018 $1\muxid$1$next[1:0]$7019 + attribute \src "libresoc.v:147331.5-147331.29" switch \initial - attribute \src "libresoc.v:146451.9-146451.17" + attribute \src "libresoc.v:147331.9-147331.17" case 1'1 case end @@ -238771,19 +239191,19 @@ module \logical_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$7035 \muxid$51 + assign $1\muxid$1$next[1:0]$7019 \muxid$51 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$7035 \muxid$51 + assign $1\muxid$1$next[1:0]$7019 \muxid$51 case - assign $1\muxid$1$next[1:0]$7035 \muxid$1 + assign $1\muxid$1$next[1:0]$7019 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$7034 + update \muxid$1$next $0\muxid$1$next[1:0]$7018 end - attribute \src "libresoc.v:146463.3-146504.6" - process $proc$libresoc.v:146463$7036 + attribute \src "libresoc.v:147343.3-147384.6" + process $proc$libresoc.v:147343$7020 assign { } { } assign { } { } assign { } { } @@ -238820,33 +239240,33 @@ module \logical_pipe2 assign { } { } assign { } { } assign { } { } - assign $0\logical_op__data_len$18$next[3:0]$7037 $1\logical_op__data_len$18$next[3:0]$7055 - assign $0\logical_op__fn_unit$3$next[13:0]$7038 $1\logical_op__fn_unit$3$next[13:0]$7056 + assign $0\logical_op__data_len$18$next[3:0]$7021 $1\logical_op__data_len$18$next[3:0]$7039 + assign $0\logical_op__fn_unit$3$next[13:0]$7022 $1\logical_op__fn_unit$3$next[13:0]$7040 assign { } { } assign { } { } - assign $0\logical_op__input_carry$12$next[1:0]$7041 $1\logical_op__input_carry$12$next[1:0]$7059 - assign $0\logical_op__insn$19$next[31:0]$7042 $1\logical_op__insn$19$next[31:0]$7060 - assign $0\logical_op__insn_type$2$next[6:0]$7043 $1\logical_op__insn_type$2$next[6:0]$7061 - assign $0\logical_op__invert_in$10$next[0:0]$7044 $1\logical_op__invert_in$10$next[0:0]$7062 - assign $0\logical_op__invert_out$13$next[0:0]$7045 $1\logical_op__invert_out$13$next[0:0]$7063 - assign $0\logical_op__is_32bit$16$next[0:0]$7046 $1\logical_op__is_32bit$16$next[0:0]$7064 - assign $0\logical_op__is_signed$17$next[0:0]$7047 $1\logical_op__is_signed$17$next[0:0]$7065 + assign $0\logical_op__input_carry$12$next[1:0]$7025 $1\logical_op__input_carry$12$next[1:0]$7043 + assign $0\logical_op__insn$19$next[31:0]$7026 $1\logical_op__insn$19$next[31:0]$7044 + assign $0\logical_op__insn_type$2$next[6:0]$7027 $1\logical_op__insn_type$2$next[6:0]$7045 + assign $0\logical_op__invert_in$10$next[0:0]$7028 $1\logical_op__invert_in$10$next[0:0]$7046 + assign $0\logical_op__invert_out$13$next[0:0]$7029 $1\logical_op__invert_out$13$next[0:0]$7047 + assign $0\logical_op__is_32bit$16$next[0:0]$7030 $1\logical_op__is_32bit$16$next[0:0]$7048 + assign $0\logical_op__is_signed$17$next[0:0]$7031 $1\logical_op__is_signed$17$next[0:0]$7049 assign { } { } assign { } { } - assign $0\logical_op__output_carry$15$next[0:0]$7050 $1\logical_op__output_carry$15$next[0:0]$7068 + assign $0\logical_op__output_carry$15$next[0:0]$7034 $1\logical_op__output_carry$15$next[0:0]$7052 assign { } { } assign { } { } - assign $0\logical_op__write_cr0$14$next[0:0]$7053 $1\logical_op__write_cr0$14$next[0:0]$7071 - assign $0\logical_op__zero_a$11$next[0:0]$7054 $1\logical_op__zero_a$11$next[0:0]$7072 - assign $0\logical_op__imm_data__data$4$next[63:0]$7039 $2\logical_op__imm_data__data$4$next[63:0]$7073 - assign $0\logical_op__imm_data__ok$5$next[0:0]$7040 $2\logical_op__imm_data__ok$5$next[0:0]$7074 - assign $0\logical_op__oe__oe$8$next[0:0]$7048 $2\logical_op__oe__oe$8$next[0:0]$7075 - assign $0\logical_op__oe__ok$9$next[0:0]$7049 $2\logical_op__oe__ok$9$next[0:0]$7076 - assign $0\logical_op__rc__ok$7$next[0:0]$7051 $2\logical_op__rc__ok$7$next[0:0]$7077 - assign $0\logical_op__rc__rc$6$next[0:0]$7052 $2\logical_op__rc__rc$6$next[0:0]$7078 - attribute \src "libresoc.v:146464.5-146464.29" + assign $0\logical_op__write_cr0$14$next[0:0]$7037 $1\logical_op__write_cr0$14$next[0:0]$7055 + assign $0\logical_op__zero_a$11$next[0:0]$7038 $1\logical_op__zero_a$11$next[0:0]$7056 + assign $0\logical_op__imm_data__data$4$next[63:0]$7023 $2\logical_op__imm_data__data$4$next[63:0]$7057 + assign $0\logical_op__imm_data__ok$5$next[0:0]$7024 $2\logical_op__imm_data__ok$5$next[0:0]$7058 + assign $0\logical_op__oe__oe$8$next[0:0]$7032 $2\logical_op__oe__oe$8$next[0:0]$7059 + assign $0\logical_op__oe__ok$9$next[0:0]$7033 $2\logical_op__oe__ok$9$next[0:0]$7060 + assign $0\logical_op__rc__ok$7$next[0:0]$7035 $2\logical_op__rc__ok$7$next[0:0]$7061 + assign $0\logical_op__rc__rc$6$next[0:0]$7036 $2\logical_op__rc__rc$6$next[0:0]$7062 + attribute \src "libresoc.v:147344.5-147344.29" switch \initial - attribute \src "libresoc.v:146464.9-146464.17" + attribute \src "libresoc.v:147344.9-147344.17" case 1'1 case end @@ -238872,7 +239292,7 @@ module \logical_pipe2 assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$19$next[31:0]$7060 $1\logical_op__data_len$18$next[3:0]$7055 $1\logical_op__is_signed$17$next[0:0]$7065 $1\logical_op__is_32bit$16$next[0:0]$7064 $1\logical_op__output_carry$15$next[0:0]$7068 $1\logical_op__write_cr0$14$next[0:0]$7071 $1\logical_op__invert_out$13$next[0:0]$7063 $1\logical_op__input_carry$12$next[1:0]$7059 $1\logical_op__zero_a$11$next[0:0]$7072 $1\logical_op__invert_in$10$next[0:0]$7062 $1\logical_op__oe__ok$9$next[0:0]$7067 $1\logical_op__oe__oe$8$next[0:0]$7066 $1\logical_op__rc__ok$7$next[0:0]$7069 $1\logical_op__rc__rc$6$next[0:0]$7070 $1\logical_op__imm_data__ok$5$next[0:0]$7058 $1\logical_op__imm_data__data$4$next[63:0]$7057 $1\logical_op__fn_unit$3$next[13:0]$7056 $1\logical_op__insn_type$2$next[6:0]$7061 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } + assign { $1\logical_op__insn$19$next[31:0]$7044 $1\logical_op__data_len$18$next[3:0]$7039 $1\logical_op__is_signed$17$next[0:0]$7049 $1\logical_op__is_32bit$16$next[0:0]$7048 $1\logical_op__output_carry$15$next[0:0]$7052 $1\logical_op__write_cr0$14$next[0:0]$7055 $1\logical_op__invert_out$13$next[0:0]$7047 $1\logical_op__input_carry$12$next[1:0]$7043 $1\logical_op__zero_a$11$next[0:0]$7056 $1\logical_op__invert_in$10$next[0:0]$7046 $1\logical_op__oe__ok$9$next[0:0]$7051 $1\logical_op__oe__oe$8$next[0:0]$7050 $1\logical_op__rc__ok$7$next[0:0]$7053 $1\logical_op__rc__rc$6$next[0:0]$7054 $1\logical_op__imm_data__ok$5$next[0:0]$7042 $1\logical_op__imm_data__data$4$next[63:0]$7041 $1\logical_op__fn_unit$3$next[13:0]$7040 $1\logical_op__insn_type$2$next[6:0]$7045 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -238893,26 +239313,26 @@ module \logical_pipe2 assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$19$next[31:0]$7060 $1\logical_op__data_len$18$next[3:0]$7055 $1\logical_op__is_signed$17$next[0:0]$7065 $1\logical_op__is_32bit$16$next[0:0]$7064 $1\logical_op__output_carry$15$next[0:0]$7068 $1\logical_op__write_cr0$14$next[0:0]$7071 $1\logical_op__invert_out$13$next[0:0]$7063 $1\logical_op__input_carry$12$next[1:0]$7059 $1\logical_op__zero_a$11$next[0:0]$7072 $1\logical_op__invert_in$10$next[0:0]$7062 $1\logical_op__oe__ok$9$next[0:0]$7067 $1\logical_op__oe__oe$8$next[0:0]$7066 $1\logical_op__rc__ok$7$next[0:0]$7069 $1\logical_op__rc__rc$6$next[0:0]$7070 $1\logical_op__imm_data__ok$5$next[0:0]$7058 $1\logical_op__imm_data__data$4$next[63:0]$7057 $1\logical_op__fn_unit$3$next[13:0]$7056 $1\logical_op__insn_type$2$next[6:0]$7061 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } + assign { $1\logical_op__insn$19$next[31:0]$7044 $1\logical_op__data_len$18$next[3:0]$7039 $1\logical_op__is_signed$17$next[0:0]$7049 $1\logical_op__is_32bit$16$next[0:0]$7048 $1\logical_op__output_carry$15$next[0:0]$7052 $1\logical_op__write_cr0$14$next[0:0]$7055 $1\logical_op__invert_out$13$next[0:0]$7047 $1\logical_op__input_carry$12$next[1:0]$7043 $1\logical_op__zero_a$11$next[0:0]$7056 $1\logical_op__invert_in$10$next[0:0]$7046 $1\logical_op__oe__ok$9$next[0:0]$7051 $1\logical_op__oe__oe$8$next[0:0]$7050 $1\logical_op__rc__ok$7$next[0:0]$7053 $1\logical_op__rc__rc$6$next[0:0]$7054 $1\logical_op__imm_data__ok$5$next[0:0]$7042 $1\logical_op__imm_data__data$4$next[63:0]$7041 $1\logical_op__fn_unit$3$next[13:0]$7040 $1\logical_op__insn_type$2$next[6:0]$7045 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } case - assign $1\logical_op__data_len$18$next[3:0]$7055 \logical_op__data_len$18 - assign $1\logical_op__fn_unit$3$next[13:0]$7056 \logical_op__fn_unit$3 - assign $1\logical_op__imm_data__data$4$next[63:0]$7057 \logical_op__imm_data__data$4 - assign $1\logical_op__imm_data__ok$5$next[0:0]$7058 \logical_op__imm_data__ok$5 - assign $1\logical_op__input_carry$12$next[1:0]$7059 \logical_op__input_carry$12 - assign $1\logical_op__insn$19$next[31:0]$7060 \logical_op__insn$19 - assign $1\logical_op__insn_type$2$next[6:0]$7061 \logical_op__insn_type$2 - assign $1\logical_op__invert_in$10$next[0:0]$7062 \logical_op__invert_in$10 - assign $1\logical_op__invert_out$13$next[0:0]$7063 \logical_op__invert_out$13 - assign $1\logical_op__is_32bit$16$next[0:0]$7064 \logical_op__is_32bit$16 - assign $1\logical_op__is_signed$17$next[0:0]$7065 \logical_op__is_signed$17 - assign $1\logical_op__oe__oe$8$next[0:0]$7066 \logical_op__oe__oe$8 - assign $1\logical_op__oe__ok$9$next[0:0]$7067 \logical_op__oe__ok$9 - assign $1\logical_op__output_carry$15$next[0:0]$7068 \logical_op__output_carry$15 - assign $1\logical_op__rc__ok$7$next[0:0]$7069 \logical_op__rc__ok$7 - assign $1\logical_op__rc__rc$6$next[0:0]$7070 \logical_op__rc__rc$6 - assign $1\logical_op__write_cr0$14$next[0:0]$7071 \logical_op__write_cr0$14 - assign $1\logical_op__zero_a$11$next[0:0]$7072 \logical_op__zero_a$11 + assign $1\logical_op__data_len$18$next[3:0]$7039 \logical_op__data_len$18 + assign $1\logical_op__fn_unit$3$next[13:0]$7040 \logical_op__fn_unit$3 + assign $1\logical_op__imm_data__data$4$next[63:0]$7041 \logical_op__imm_data__data$4 + assign $1\logical_op__imm_data__ok$5$next[0:0]$7042 \logical_op__imm_data__ok$5 + assign $1\logical_op__input_carry$12$next[1:0]$7043 \logical_op__input_carry$12 + assign $1\logical_op__insn$19$next[31:0]$7044 \logical_op__insn$19 + assign $1\logical_op__insn_type$2$next[6:0]$7045 \logical_op__insn_type$2 + assign $1\logical_op__invert_in$10$next[0:0]$7046 \logical_op__invert_in$10 + assign $1\logical_op__invert_out$13$next[0:0]$7047 \logical_op__invert_out$13 + assign $1\logical_op__is_32bit$16$next[0:0]$7048 \logical_op__is_32bit$16 + assign $1\logical_op__is_signed$17$next[0:0]$7049 \logical_op__is_signed$17 + assign $1\logical_op__oe__oe$8$next[0:0]$7050 \logical_op__oe__oe$8 + assign $1\logical_op__oe__ok$9$next[0:0]$7051 \logical_op__oe__ok$9 + assign $1\logical_op__output_carry$15$next[0:0]$7052 \logical_op__output_carry$15 + assign $1\logical_op__rc__ok$7$next[0:0]$7053 \logical_op__rc__ok$7 + assign $1\logical_op__rc__rc$6$next[0:0]$7054 \logical_op__rc__rc$6 + assign $1\logical_op__write_cr0$14$next[0:0]$7055 \logical_op__write_cr0$14 + assign $1\logical_op__zero_a$11$next[0:0]$7056 \logical_op__zero_a$11 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -238924,52 +239344,52 @@ module \logical_pipe2 assign { } { } assign { } { } assign { } { } - assign $2\logical_op__imm_data__data$4$next[63:0]$7073 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\logical_op__imm_data__ok$5$next[0:0]$7074 1'0 - assign $2\logical_op__rc__rc$6$next[0:0]$7078 1'0 - assign $2\logical_op__rc__ok$7$next[0:0]$7077 1'0 - assign $2\logical_op__oe__oe$8$next[0:0]$7075 1'0 - assign $2\logical_op__oe__ok$9$next[0:0]$7076 1'0 + assign $2\logical_op__imm_data__data$4$next[63:0]$7057 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$5$next[0:0]$7058 1'0 + assign $2\logical_op__rc__rc$6$next[0:0]$7062 1'0 + assign $2\logical_op__rc__ok$7$next[0:0]$7061 1'0 + assign $2\logical_op__oe__oe$8$next[0:0]$7059 1'0 + assign $2\logical_op__oe__ok$9$next[0:0]$7060 1'0 case - assign $2\logical_op__imm_data__data$4$next[63:0]$7073 $1\logical_op__imm_data__data$4$next[63:0]$7057 - assign $2\logical_op__imm_data__ok$5$next[0:0]$7074 $1\logical_op__imm_data__ok$5$next[0:0]$7058 - assign $2\logical_op__oe__oe$8$next[0:0]$7075 $1\logical_op__oe__oe$8$next[0:0]$7066 - assign $2\logical_op__oe__ok$9$next[0:0]$7076 $1\logical_op__oe__ok$9$next[0:0]$7067 - assign $2\logical_op__rc__ok$7$next[0:0]$7077 $1\logical_op__rc__ok$7$next[0:0]$7069 - assign $2\logical_op__rc__rc$6$next[0:0]$7078 $1\logical_op__rc__rc$6$next[0:0]$7070 + assign $2\logical_op__imm_data__data$4$next[63:0]$7057 $1\logical_op__imm_data__data$4$next[63:0]$7041 + assign $2\logical_op__imm_data__ok$5$next[0:0]$7058 $1\logical_op__imm_data__ok$5$next[0:0]$7042 + assign $2\logical_op__oe__oe$8$next[0:0]$7059 $1\logical_op__oe__oe$8$next[0:0]$7050 + assign $2\logical_op__oe__ok$9$next[0:0]$7060 $1\logical_op__oe__ok$9$next[0:0]$7051 + assign $2\logical_op__rc__ok$7$next[0:0]$7061 $1\logical_op__rc__ok$7$next[0:0]$7053 + assign $2\logical_op__rc__rc$6$next[0:0]$7062 $1\logical_op__rc__rc$6$next[0:0]$7054 end sync always - update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$7037 - update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[13:0]$7038 - update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$7039 - update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$7040 - update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$7041 - update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$7042 - update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$7043 - update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$7044 - update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$7045 - update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$7046 - update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$7047 - update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$7048 - update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$7049 - update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$7050 - update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$7051 - update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$7052 - update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$7053 - update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$7054 + update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$7021 + update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[13:0]$7022 + update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$7023 + update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$7024 + update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$7025 + update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$7026 + update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$7027 + update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$7028 + update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$7029 + update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$7030 + update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$7031 + update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$7032 + update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$7033 + update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$7034 + update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$7035 + update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$7036 + update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$7037 + update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$7038 end - attribute \src "libresoc.v:146505.3-146523.6" - process $proc$libresoc.v:146505$7079 + attribute \src "libresoc.v:147385.3-147403.6" + process $proc$libresoc.v:147385$7063 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$20$next[63:0]$7080 $1\o$20$next[63:0]$7082 + assign $0\o$20$next[63:0]$7064 $1\o$20$next[63:0]$7066 assign { } { } - assign $0\o_ok$21$next[0:0]$7081 $2\o_ok$21$next[0:0]$7084 - attribute \src "libresoc.v:146506.5-146506.29" + assign $0\o_ok$21$next[0:0]$7065 $2\o_ok$21$next[0:0]$7068 + attribute \src "libresoc.v:147386.5-147386.29" switch \initial - attribute \src "libresoc.v:146506.9-146506.17" + attribute \src "libresoc.v:147386.9-147386.17" case 1'1 case end @@ -238979,41 +239399,41 @@ module \logical_pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$21$next[0:0]$7083 $1\o$20$next[63:0]$7082 } { \o_ok$71 \o$70 } + assign { $1\o_ok$21$next[0:0]$7067 $1\o$20$next[63:0]$7066 } { \o_ok$71 \o$70 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$21$next[0:0]$7083 $1\o$20$next[63:0]$7082 } { \o_ok$71 \o$70 } + assign { $1\o_ok$21$next[0:0]$7067 $1\o$20$next[63:0]$7066 } { \o_ok$71 \o$70 } case - assign $1\o$20$next[63:0]$7082 \o$20 - assign $1\o_ok$21$next[0:0]$7083 \o_ok$21 + assign $1\o$20$next[63:0]$7066 \o$20 + assign $1\o_ok$21$next[0:0]$7067 \o_ok$21 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$21$next[0:0]$7084 1'0 + assign $2\o_ok$21$next[0:0]$7068 1'0 case - assign $2\o_ok$21$next[0:0]$7084 $1\o_ok$21$next[0:0]$7083 + assign $2\o_ok$21$next[0:0]$7068 $1\o_ok$21$next[0:0]$7067 end sync always - update \o$20$next $0\o$20$next[63:0]$7080 - update \o_ok$21$next $0\o_ok$21$next[0:0]$7081 + update \o$20$next $0\o$20$next[63:0]$7064 + update \o_ok$21$next $0\o_ok$21$next[0:0]$7065 end - attribute \src "libresoc.v:146524.3-146542.6" - process $proc$libresoc.v:146524$7085 + attribute \src "libresoc.v:147404.3-147422.6" + process $proc$libresoc.v:147404$7069 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$22$next[3:0]$7086 $1\cr_a$22$next[3:0]$7088 + assign $0\cr_a$22$next[3:0]$7070 $1\cr_a$22$next[3:0]$7072 assign { } { } - assign $0\cr_a_ok$23$next[0:0]$7087 $2\cr_a_ok$23$next[0:0]$7090 - attribute \src "libresoc.v:146525.5-146525.29" + assign $0\cr_a_ok$23$next[0:0]$7071 $2\cr_a_ok$23$next[0:0]$7074 + attribute \src "libresoc.v:147405.5-147405.29" switch \initial - attribute \src "libresoc.v:146525.9-146525.17" + attribute \src "libresoc.v:147405.9-147405.17" case 1'1 case end @@ -239023,30 +239443,30 @@ module \logical_pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$23$next[0:0]$7089 $1\cr_a$22$next[3:0]$7088 } { \cr_a_ok$73 \cr_a$72 } + assign { $1\cr_a_ok$23$next[0:0]$7073 $1\cr_a$22$next[3:0]$7072 } { \cr_a_ok$73 \cr_a$72 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$23$next[0:0]$7089 $1\cr_a$22$next[3:0]$7088 } { \cr_a_ok$73 \cr_a$72 } + assign { $1\cr_a_ok$23$next[0:0]$7073 $1\cr_a$22$next[3:0]$7072 } { \cr_a_ok$73 \cr_a$72 } case - assign $1\cr_a$22$next[3:0]$7088 \cr_a$22 - assign $1\cr_a_ok$23$next[0:0]$7089 \cr_a_ok$23 + assign $1\cr_a$22$next[3:0]$7072 \cr_a$22 + assign $1\cr_a_ok$23$next[0:0]$7073 \cr_a_ok$23 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$23$next[0:0]$7090 1'0 + assign $2\cr_a_ok$23$next[0:0]$7074 1'0 case - assign $2\cr_a_ok$23$next[0:0]$7090 $1\cr_a_ok$23$next[0:0]$7089 + assign $2\cr_a_ok$23$next[0:0]$7074 $1\cr_a_ok$23$next[0:0]$7073 end sync always - update \cr_a$22$next $0\cr_a$22$next[3:0]$7086 - update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$7087 + update \cr_a$22$next $0\cr_a$22$next[3:0]$7070 + update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$7071 end - connect \$49 $and$libresoc.v:146327$6981_Y + connect \$49 $and$libresoc.v:147207$6965_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \cr_a_ok$73 \cr_a$72 } { \output_cr_a_ok \output_cr_a$45 } @@ -239062,48943 +239482,23792 @@ module \logical_pipe2 connect { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in \output_logical_op__oe__ok \output_logical_op__oe__oe \output_logical_op__rc__ok \output_logical_op__rc__rc \output_logical_op__imm_data__ok \output_logical_op__imm_data__data \output_logical_op__fn_unit \output_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \output_muxid \muxid end -attribute \src "ls180.v:4.1-10688.10" +attribute \src "ls180.v:4.1-5963.10" attribute \cells_not_processed 1 module \ls180 - attribute \src "ls180.v:10144.1-10162.4" - wire width 6 $0$memwr$\mem$ls180.v:10146$1_ADDR[5:0]$2744 - attribute \src "ls180.v:10144.1-10162.4" - wire width 64 $0$memwr$\mem$ls180.v:10146$1_DATA[63:0]$2745 - attribute \src "ls180.v:10144.1-10162.4" - wire width 64 $0$memwr$\mem$ls180.v:10146$1_EN[63:0]$2746 - attribute \src "ls180.v:10144.1-10162.4" - wire width 6 $0$memwr$\mem$ls180.v:10148$2_ADDR[5:0]$2747 - attribute \src "ls180.v:10144.1-10162.4" - wire width 64 $0$memwr$\mem$ls180.v:10148$2_DATA[63:0]$2748 - attribute \src "ls180.v:10144.1-10162.4" - wire width 64 $0$memwr$\mem$ls180.v:10148$2_EN[63:0]$2749 - attribute \src "ls180.v:10144.1-10162.4" - wire width 6 $0$memwr$\mem$ls180.v:10150$3_ADDR[5:0]$2750 - attribute \src "ls180.v:10144.1-10162.4" - wire width 64 $0$memwr$\mem$ls180.v:10150$3_DATA[63:0]$2751 - attribute \src "ls180.v:10144.1-10162.4" - wire width 64 $0$memwr$\mem$ls180.v:10150$3_EN[63:0]$2752 - attribute \src "ls180.v:10144.1-10162.4" - wire width 6 $0$memwr$\mem$ls180.v:10152$4_ADDR[5:0]$2753 - attribute \src "ls180.v:10144.1-10162.4" - wire width 64 $0$memwr$\mem$ls180.v:10152$4_DATA[63:0]$2754 - attribute \src "ls180.v:10144.1-10162.4" - wire width 64 $0$memwr$\mem$ls180.v:10152$4_EN[63:0]$2755 - attribute \src "ls180.v:10144.1-10162.4" - wire width 6 $0$memwr$\mem$ls180.v:10154$5_ADDR[5:0]$2756 - attribute \src "ls180.v:10144.1-10162.4" - wire width 64 $0$memwr$\mem$ls180.v:10154$5_DATA[63:0]$2757 - attribute \src "ls180.v:10144.1-10162.4" - wire width 64 $0$memwr$\mem$ls180.v:10154$5_EN[63:0]$2758 - attribute \src "ls180.v:10144.1-10162.4" - wire width 6 $0$memwr$\mem$ls180.v:10156$6_ADDR[5:0]$2759 - attribute \src "ls180.v:10144.1-10162.4" - wire width 64 $0$memwr$\mem$ls180.v:10156$6_DATA[63:0]$2760 - attribute \src "ls180.v:10144.1-10162.4" - wire width 64 $0$memwr$\mem$ls180.v:10156$6_EN[63:0]$2761 - attribute \src "ls180.v:10144.1-10162.4" - wire width 6 $0$memwr$\mem$ls180.v:10158$7_ADDR[5:0]$2762 - attribute \src "ls180.v:10144.1-10162.4" - wire width 64 $0$memwr$\mem$ls180.v:10158$7_DATA[63:0]$2763 - attribute \src "ls180.v:10144.1-10162.4" - wire width 64 $0$memwr$\mem$ls180.v:10158$7_EN[63:0]$2764 - attribute \src "ls180.v:10144.1-10162.4" - wire width 6 $0$memwr$\mem$ls180.v:10160$8_ADDR[5:0]$2765 - attribute \src "ls180.v:10144.1-10162.4" - wire width 64 $0$memwr$\mem$ls180.v:10160$8_DATA[63:0]$2766 - attribute \src "ls180.v:10144.1-10162.4" - wire width 64 $0$memwr$\mem$ls180.v:10160$8_EN[63:0]$2767 - attribute \src "ls180.v:10172.1-10190.4" - wire width 4 $0$memwr$\mem_1$ls180.v:10174$9_ADDR[3:0]$2770 - attribute \src "ls180.v:10172.1-10190.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10174$9_DATA[63:0]$2771 - attribute \src "ls180.v:10172.1-10190.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10174$9_EN[63:0]$2772 - attribute \src "ls180.v:10172.1-10190.4" - wire width 4 $0$memwr$\mem_1$ls180.v:10176$10_ADDR[3:0]$2773 - attribute \src "ls180.v:10172.1-10190.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10176$10_DATA[63:0]$2774 - attribute \src "ls180.v:10172.1-10190.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10176$10_EN[63:0]$2775 - attribute \src "ls180.v:10172.1-10190.4" - wire width 4 $0$memwr$\mem_1$ls180.v:10178$11_ADDR[3:0]$2776 - attribute \src "ls180.v:10172.1-10190.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10178$11_DATA[63:0]$2777 - attribute \src "ls180.v:10172.1-10190.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10178$11_EN[63:0]$2778 - attribute \src "ls180.v:10172.1-10190.4" - wire width 4 $0$memwr$\mem_1$ls180.v:10180$12_ADDR[3:0]$2779 - attribute \src "ls180.v:10172.1-10190.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10180$12_DATA[63:0]$2780 - attribute \src "ls180.v:10172.1-10190.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10180$12_EN[63:0]$2781 - attribute \src "ls180.v:10172.1-10190.4" - wire width 4 $0$memwr$\mem_1$ls180.v:10182$13_ADDR[3:0]$2782 - attribute \src "ls180.v:10172.1-10190.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10182$13_DATA[63:0]$2783 - attribute \src "ls180.v:10172.1-10190.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10182$13_EN[63:0]$2784 - attribute \src "ls180.v:10172.1-10190.4" - wire width 4 $0$memwr$\mem_1$ls180.v:10184$14_ADDR[3:0]$2785 - attribute \src "ls180.v:10172.1-10190.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10184$14_DATA[63:0]$2786 - attribute \src "ls180.v:10172.1-10190.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10184$14_EN[63:0]$2787 - attribute \src "ls180.v:10172.1-10190.4" - wire width 4 $0$memwr$\mem_1$ls180.v:10186$15_ADDR[3:0]$2788 - attribute \src "ls180.v:10172.1-10190.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10186$15_DATA[63:0]$2789 - attribute \src "ls180.v:10172.1-10190.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10186$15_EN[63:0]$2790 - attribute \src "ls180.v:10172.1-10190.4" - wire width 4 $0$memwr$\mem_1$ls180.v:10188$16_ADDR[3:0]$2791 - attribute \src "ls180.v:10172.1-10190.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10188$16_DATA[63:0]$2792 - attribute \src "ls180.v:10172.1-10190.4" - wire width 64 $0$memwr$\mem_1$ls180.v:10188$16_EN[63:0]$2793 - attribute \src "ls180.v:10200.1-10204.4" - wire width 3 $0$memwr$\storage$ls180.v:10202$17_ADDR[2:0]$2796 - attribute \src "ls180.v:10200.1-10204.4" - wire width 25 $0$memwr$\storage$ls180.v:10202$17_DATA[24:0]$2797 - attribute \src "ls180.v:10200.1-10204.4" - wire width 25 $0$memwr$\storage$ls180.v:10202$17_EN[24:0]$2798 - attribute \src "ls180.v:10214.1-10218.4" - wire width 3 $0$memwr$\storage_1$ls180.v:10216$18_ADDR[2:0]$2803 - attribute \src "ls180.v:10214.1-10218.4" - wire width 25 $0$memwr$\storage_1$ls180.v:10216$18_DATA[24:0]$2804 - attribute \src "ls180.v:10214.1-10218.4" - wire width 25 $0$memwr$\storage_1$ls180.v:10216$18_EN[24:0]$2805 - attribute \src "ls180.v:10228.1-10232.4" - wire width 3 $0$memwr$\storage_2$ls180.v:10230$19_ADDR[2:0]$2810 - attribute \src "ls180.v:10228.1-10232.4" - wire width 25 $0$memwr$\storage_2$ls180.v:10230$19_DATA[24:0]$2811 - attribute \src "ls180.v:10228.1-10232.4" - wire width 25 $0$memwr$\storage_2$ls180.v:10230$19_EN[24:0]$2812 - attribute \src "ls180.v:10242.1-10246.4" - wire width 3 $0$memwr$\storage_3$ls180.v:10244$20_ADDR[2:0]$2817 - attribute \src "ls180.v:10242.1-10246.4" - wire width 25 $0$memwr$\storage_3$ls180.v:10244$20_DATA[24:0]$2818 - attribute \src "ls180.v:10242.1-10246.4" - wire width 25 $0$memwr$\storage_3$ls180.v:10244$20_EN[24:0]$2819 - attribute \src "ls180.v:10257.1-10261.4" - wire width 4 $0$memwr$\storage_4$ls180.v:10259$21_ADDR[3:0]$2824 - attribute \src "ls180.v:10257.1-10261.4" - wire width 10 $0$memwr$\storage_4$ls180.v:10259$21_DATA[9:0]$2825 - attribute \src "ls180.v:10257.1-10261.4" - wire width 10 $0$memwr$\storage_4$ls180.v:10259$21_EN[9:0]$2826 - attribute \src "ls180.v:10274.1-10278.4" - wire width 4 $0$memwr$\storage_5$ls180.v:10276$22_ADDR[3:0]$2831 - attribute \src "ls180.v:10274.1-10278.4" - wire width 10 $0$memwr$\storage_5$ls180.v:10276$22_DATA[9:0]$2832 - attribute \src "ls180.v:10274.1-10278.4" - wire width 10 $0$memwr$\storage_5$ls180.v:10276$22_EN[9:0]$2833 - attribute \src "ls180.v:10290.1-10294.4" - wire width 5 $0$memwr$\storage_6$ls180.v:10292$23_ADDR[4:0]$2838 - attribute \src "ls180.v:10290.1-10294.4" - wire width 10 $0$memwr$\storage_6$ls180.v:10292$23_DATA[9:0]$2839 - attribute \src "ls180.v:10290.1-10294.4" - wire width 10 $0$memwr$\storage_6$ls180.v:10292$23_EN[9:0]$2840 - attribute \src "ls180.v:10304.1-10308.4" - wire width 5 $0$memwr$\storage_7$ls180.v:10306$24_ADDR[4:0]$2845 - attribute \src "ls180.v:10304.1-10308.4" - wire width 10 $0$memwr$\storage_7$ls180.v:10306$24_DATA[9:0]$2846 - attribute \src "ls180.v:10304.1-10308.4" - wire width 10 $0$memwr$\storage_7$ls180.v:10306$24_EN[9:0]$2847 - attribute \src "ls180.v:3271.1-3364.4" - wire width 3 $0\builder_bankmachine0_next_state[2:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 3 $0\builder_bankmachine0_state[2:0] - attribute \src "ls180.v:3428.1-3521.4" - wire width 3 $0\builder_bankmachine1_next_state[2:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 3 $0\builder_bankmachine1_state[2:0] - attribute \src "ls180.v:3585.1-3678.4" - wire width 3 $0\builder_bankmachine2_next_state[2:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 3 $0\builder_bankmachine2_state[2:0] - attribute \src "ls180.v:3742.1-3835.4" - wire width 3 $0\builder_bankmachine3_next_state[2:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 3 $0\builder_bankmachine3_state[2:0] - attribute \src "ls180.v:6597.1-6613.4" - wire $0\builder_comb_rhs_array_muxed0[0:0] - attribute \src "ls180.v:6818.1-6834.4" - wire $0\builder_comb_rhs_array_muxed10[0:0] - attribute \src "ls180.v:6835.1-6851.4" - wire $0\builder_comb_rhs_array_muxed11[0:0] - attribute \src "ls180.v:6903.1-6910.4" - wire width 22 $0\builder_comb_rhs_array_muxed12[21:0] - attribute \src "ls180.v:6911.1-6918.4" - wire $0\builder_comb_rhs_array_muxed13[0:0] - attribute \src "ls180.v:6919.1-6926.4" - wire $0\builder_comb_rhs_array_muxed14[0:0] - attribute \src "ls180.v:6927.1-6934.4" - wire width 22 $0\builder_comb_rhs_array_muxed15[21:0] - attribute \src "ls180.v:6935.1-6942.4" - wire $0\builder_comb_rhs_array_muxed16[0:0] - attribute \src "ls180.v:6943.1-6950.4" - wire $0\builder_comb_rhs_array_muxed17[0:0] - attribute \src "ls180.v:6951.1-6958.4" - wire width 22 $0\builder_comb_rhs_array_muxed18[21:0] - attribute \src "ls180.v:6959.1-6966.4" - wire $0\builder_comb_rhs_array_muxed19[0:0] - attribute \src "ls180.v:6614.1-6630.4" - wire width 13 $0\builder_comb_rhs_array_muxed1[12:0] - attribute \src "ls180.v:6967.1-6974.4" - wire $0\builder_comb_rhs_array_muxed20[0:0] - attribute \src "ls180.v:6975.1-6982.4" - wire width 22 $0\builder_comb_rhs_array_muxed21[21:0] - attribute \src "ls180.v:6983.1-6990.4" - wire $0\builder_comb_rhs_array_muxed22[0:0] - attribute \src "ls180.v:6991.1-6998.4" - wire $0\builder_comb_rhs_array_muxed23[0:0] - attribute \src "ls180.v:6999.1-7018.4" - wire width 32 $0\builder_comb_rhs_array_muxed24[31:0] - attribute \src "ls180.v:7019.1-7038.4" - wire width 64 $0\builder_comb_rhs_array_muxed25[63:0] - attribute \src "ls180.v:7039.1-7058.4" - wire width 8 $0\builder_comb_rhs_array_muxed26[7:0] - attribute \src "ls180.v:7059.1-7078.4" - wire $0\builder_comb_rhs_array_muxed27[0:0] - attribute \src "ls180.v:7079.1-7098.4" - wire $0\builder_comb_rhs_array_muxed28[0:0] - attribute \src "ls180.v:7099.1-7118.4" - wire $0\builder_comb_rhs_array_muxed29[0:0] - attribute \src "ls180.v:6631.1-6647.4" - wire width 2 $0\builder_comb_rhs_array_muxed2[1:0] - attribute \src "ls180.v:7119.1-7138.4" - wire width 3 $0\builder_comb_rhs_array_muxed30[2:0] - attribute \src "ls180.v:7139.1-7158.4" - wire width 2 $0\builder_comb_rhs_array_muxed31[1:0] - attribute \src "ls180.v:6648.1-6664.4" - wire $0\builder_comb_rhs_array_muxed3[0:0] - attribute \src "ls180.v:6665.1-6681.4" - wire $0\builder_comb_rhs_array_muxed4[0:0] - attribute \src "ls180.v:6682.1-6698.4" - wire $0\builder_comb_rhs_array_muxed5[0:0] - attribute \src "ls180.v:6750.1-6766.4" - wire $0\builder_comb_rhs_array_muxed6[0:0] - attribute \src "ls180.v:6767.1-6783.4" - wire width 13 $0\builder_comb_rhs_array_muxed7[12:0] - attribute \src "ls180.v:6784.1-6800.4" - wire width 2 $0\builder_comb_rhs_array_muxed8[1:0] - attribute \src "ls180.v:6801.1-6817.4" - wire $0\builder_comb_rhs_array_muxed9[0:0] - attribute \src "ls180.v:6699.1-6715.4" - wire $0\builder_comb_t_array_muxed0[0:0] - attribute \src "ls180.v:6716.1-6732.4" - wire $0\builder_comb_t_array_muxed1[0:0] - attribute \src "ls180.v:6733.1-6749.4" - wire $0\builder_comb_t_array_muxed2[0:0] - attribute \src "ls180.v:6852.1-6868.4" - wire $0\builder_comb_t_array_muxed3[0:0] - attribute \src "ls180.v:6869.1-6885.4" - wire $0\builder_comb_t_array_muxed4[0:0] - attribute \src "ls180.v:6886.1-6902.4" - wire $0\builder_comb_t_array_muxed5[0:0] - attribute \src "ls180.v:2817.1-2863.4" - wire $0\builder_converter0_next_state[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_converter0_state[0:0] - attribute \src "ls180.v:2877.1-2923.4" - wire $0\builder_converter1_next_state[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_converter1_state[0:0] - attribute \src "ls180.v:2937.1-2983.4" - wire $0\builder_converter2_next_state[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_converter2_state[0:0] - attribute \src "ls180.v:4088.1-4134.4" - wire $0\builder_converter_next_state[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_converter_state[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 20 $0\builder_count[19:0] - attribute \src "ls180.v:5837.1-5848.4" - wire $0\builder_error[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 3 $0\builder_grant[2:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 8 $0\builder_interface0_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 8 $0\builder_interface10_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 8 $0\builder_interface11_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 8 $0\builder_interface12_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 8 $0\builder_interface13_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 8 $0\builder_interface14_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 8 $0\builder_interface1_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 8 $0\builder_interface2_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 8 $0\builder_interface3_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 8 $0\builder_interface4_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 8 $0\builder_interface5_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 8 $0\builder_interface6_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 8 $0\builder_interface7_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 8 $0\builder_interface8_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 8 $0\builder_interface9_bank_bus_dat_r[7:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 14 $0\builder_libresocsim_adr[13:0] - attribute \src "ls180.v:5717.1-5753.4" - wire width 14 $0\builder_libresocsim_adr_next_value1[13:0] - attribute \src "ls180.v:5717.1-5753.4" - wire $0\builder_libresocsim_adr_next_value_ce1[0:0] - attribute \src "ls180.v:1904.5-1904.55" - wire $0\builder_libresocsim_converted_interface_ack[0:0] - attribute \src "ls180.v:1900.12-1900.65" - wire width 64 $0\builder_libresocsim_converted_interface_dat_r[63:0] - attribute \src "ls180.v:1908.5-1908.55" - wire $0\builder_libresocsim_converted_interface_err[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 8 $0\builder_libresocsim_dat_w[7:0] - attribute \src "ls180.v:5717.1-5753.4" - wire width 8 $0\builder_libresocsim_dat_w_next_value0[7:0] - attribute \src "ls180.v:5717.1-5753.4" - wire $0\builder_libresocsim_dat_w_next_value_ce0[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_libresocsim_we[0:0] - attribute \src "ls180.v:5717.1-5753.4" - wire $0\builder_libresocsim_we_next_value2[0:0] - attribute \src "ls180.v:5717.1-5753.4" - wire $0\builder_libresocsim_we_next_value_ce2[0:0] - attribute \src "ls180.v:5717.1-5753.4" - wire $0\builder_libresocsim_wishbone_ack[0:0] - attribute \src "ls180.v:1890.12-1890.52" - wire width 30 $0\builder_libresocsim_wishbone_adr[29:0] - attribute \src "ls180.v:1894.5-1894.44" - wire $0\builder_libresocsim_wishbone_cyc[0:0] - attribute \src "ls180.v:5717.1-5753.4" - wire width 32 $0\builder_libresocsim_wishbone_dat_r[31:0] - attribute \src "ls180.v:1891.12-1891.54" - wire width 32 $0\builder_libresocsim_wishbone_dat_w[31:0] - attribute \src "ls180.v:1893.11-1893.50" - wire width 4 $0\builder_libresocsim_wishbone_sel[3:0] - attribute \src "ls180.v:1895.5-1895.44" - wire $0\builder_libresocsim_wishbone_stb[0:0] - attribute \src "ls180.v:1897.5-1897.43" - wire $0\builder_libresocsim_wishbone_we[0:0] - attribute \src "ls180.v:1789.5-1789.27" - wire $0\builder_locked0[0:0] - attribute \src "ls180.v:1790.5-1790.27" - wire $0\builder_locked1[0:0] - attribute \src "ls180.v:1791.5-1791.27" - wire $0\builder_locked2[0:0] - attribute \src "ls180.v:1792.5-1792.27" - wire $0\builder_locked3[0:0] - attribute \src "ls180.v:3960.1-4032.4" - wire width 3 $0\builder_multiplexer_next_state[2:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 3 $0\builder_multiplexer_state[2:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_multiregimpl0_regs0[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_multiregimpl0_regs1[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_multiregimpl10_regs0[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_multiregimpl10_regs1[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_multiregimpl11_regs0[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_multiregimpl11_regs1[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_multiregimpl12_regs0[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_multiregimpl12_regs1[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_multiregimpl13_regs0[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_multiregimpl13_regs1[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_multiregimpl14_regs0[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_multiregimpl14_regs1[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_multiregimpl15_regs0[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_multiregimpl15_regs1[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_multiregimpl16_regs0[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_multiregimpl16_regs1[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_multiregimpl1_regs0[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_multiregimpl1_regs1[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_multiregimpl2_regs0[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_multiregimpl2_regs1[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_multiregimpl3_regs0[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_multiregimpl3_regs1[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_multiregimpl4_regs0[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_multiregimpl4_regs1[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_multiregimpl5_regs0[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_multiregimpl5_regs1[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_multiregimpl6_regs0[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_multiregimpl6_regs1[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_multiregimpl7_regs0[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_multiregimpl7_regs1[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_multiregimpl8_regs0[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_multiregimpl8_regs1[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_multiregimpl9_regs0[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_multiregimpl9_regs1[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_new_master_rdata_valid0[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_new_master_rdata_valid1[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_new_master_rdata_valid2[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_new_master_rdata_valid3[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_new_master_wdata_ready[0:0] - attribute \src "ls180.v:5717.1-5753.4" - wire width 2 $0\builder_next_state[1:0] - attribute \src "ls180.v:3177.1-3207.4" - wire width 2 $0\builder_refresher_next_state[1:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 2 $0\builder_refresher_state[1:0] - attribute \src "ls180.v:5515.1-5554.4" - wire width 2 $0\builder_sdblock2memdma_next_state[1:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 2 $0\builder_sdblock2memdma_state[1:0] - attribute \src "ls180.v:5082.1-5161.4" - wire $0\builder_sdcore_crcupstreaminserter_next_state[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_sdcore_crcupstreaminserter_state[0:0] - attribute \src "ls180.v:5264.1-5454.4" - wire width 3 $0\builder_sdcore_fsm_next_state[2:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 3 $0\builder_sdcore_fsm_state[2:0] - attribute \src "ls180.v:5574.1-5611.4" - wire $0\builder_sdmem2blockdma_fsm_next_state[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_sdmem2blockdma_fsm_state[0:0] - attribute \src "ls180.v:5612.1-5648.4" - wire width 2 $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 2 $0\builder_sdmem2blockdma_resetinserter_state[1:0] - attribute \src "ls180.v:4757.1-4829.4" - wire width 3 $0\builder_sdphy_fsm_next_state[2:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 3 $0\builder_sdphy_fsm_state[2:0] - attribute \src "ls180.v:4602.1-4695.4" - wire width 3 $0\builder_sdphy_sdphycmdr_next_state[2:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 3 $0\builder_sdphy_sdphycmdr_state[2:0] - attribute \src "ls180.v:4492.1-4568.4" - wire width 2 $0\builder_sdphy_sdphycmdw_next_state[1:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 2 $0\builder_sdphy_sdphycmdw_state[1:0] - attribute \src "ls180.v:4729.1-4756.4" - wire $0\builder_sdphy_sdphycrcr_next_state[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_sdphy_sdphycrcr_state[0:0] - attribute \src "ls180.v:4863.1-4964.4" - wire width 3 $0\builder_sdphy_sdphydatar_next_state[2:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 3 $0\builder_sdphy_sdphydatar_state[2:0] - attribute \src "ls180.v:4458.1-4491.4" - wire $0\builder_sdphy_sdphyinit_next_state[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\builder_sdphy_sdphyinit_state[0:0] - attribute \src "ls180.v:5837.1-5848.4" - wire $0\builder_shared_ack[0:0] - attribute \src "ls180.v:5837.1-5848.4" - wire width 32 $0\builder_shared_dat_r[31:0] - attribute \src "ls180.v:5778.1-5786.4" - wire width 6 $0\builder_slave_sel[5:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 6 $0\builder_slave_sel_r[5:0] - attribute \src "ls180.v:4289.1-4337.4" - wire width 2 $0\builder_spimaster0_next_state[1:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 2 $0\builder_spimaster0_state[1:0] - attribute \src "ls180.v:4348.1-4396.4" - wire width 2 $0\builder_spimaster1_next_state[1:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 2 $0\builder_spimaster1_state[1:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 2 $0\builder_state[1:0] - attribute \src "ls180.v:7278.1-7306.4" - wire $0\builder_sync_f_array_muxed0[0:0] - attribute \src "ls180.v:7307.1-7335.4" - wire $0\builder_sync_f_array_muxed1[0:0] - attribute \src "ls180.v:7159.1-7175.4" - wire width 2 $0\builder_sync_rhs_array_muxed0[1:0] - attribute \src "ls180.v:7176.1-7192.4" - wire width 13 $0\builder_sync_rhs_array_muxed1[12:0] - attribute \src "ls180.v:7193.1-7209.4" - wire $0\builder_sync_rhs_array_muxed2[0:0] - attribute \src "ls180.v:7210.1-7226.4" - wire $0\builder_sync_rhs_array_muxed3[0:0] - attribute \src "ls180.v:7227.1-7243.4" - wire $0\builder_sync_rhs_array_muxed4[0:0] - attribute \src "ls180.v:7244.1-7260.4" - wire $0\builder_sync_rhs_array_muxed5[0:0] - attribute \src "ls180.v:7261.1-7277.4" - wire $0\builder_sync_rhs_array_muxed6[0:0] - attribute \src "ls180.v:4268.1-4272.4" - wire width 16 $0\gpio_o[15:0] - attribute \src "ls180.v:4273.1-4277.4" - wire width 16 $0\gpio_oe[15:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_cmd_consumed[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_converter0_counter[0:0] - attribute \src "ls180.v:2817.1-2863.4" - wire $0\main_converter0_counter_converter0_next_value[0:0] - attribute \src "ls180.v:2817.1-2863.4" - wire $0\main_converter0_counter_converter0_next_value_ce[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 64 $0\main_converter0_dat_r[63:0] - attribute \src "ls180.v:2817.1-2863.4" - wire $0\main_converter0_skip[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_converter1_counter[0:0] - attribute \src "ls180.v:2877.1-2923.4" - wire $0\main_converter1_counter_converter1_next_value[0:0] - attribute \src "ls180.v:2877.1-2923.4" - wire $0\main_converter1_counter_converter1_next_value_ce[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 64 $0\main_converter1_dat_r[63:0] - attribute \src "ls180.v:2877.1-2923.4" - wire $0\main_converter1_skip[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_converter_counter[0:0] - attribute \src "ls180.v:4088.1-4134.4" - wire $0\main_converter_counter_converter_next_value[0:0] - attribute \src "ls180.v:4088.1-4134.4" - wire $0\main_converter_counter_converter_next_value_ce[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 32 $0\main_converter_dat_r[31:0] - attribute \src "ls180.v:4088.1-4134.4" - wire $0\main_converter_skip[0:0] - attribute \src "ls180.v:7439.1-7509.4" - wire width 16 $0\main_dfi_p0_rddata[15:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_dfi_p0_rddata_valid[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 24 $0\main_dummy[23:0] - attribute \src "ls180.v:996.12-996.53" - wire width 16 $0\main_gpiotristateasic0_oe_storage[15:0] - attribute \src "ls180.v:998.12-998.54" - wire width 16 $0\main_gpiotristateasic0_out_storage[15:0] - attribute \src "ls180.v:7393.1-7403.4" - wire width 16 $0\main_gpiotristateasic0_status[15:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_gpiotristateasic1_oe_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 16 $0\main_gpiotristateasic1_oe_storage[15:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_gpiotristateasic1_out_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 16 $0\main_gpiotristateasic1_out_storage[15:0] - attribute \src "ls180.v:7404.1-7414.4" - wire width 16 $0\main_gpiotristateasic1_status[15:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_i2c_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 3 $0\main_i2c_storage[2:0] - attribute \src "ls180.v:7435.1-7437.4" - wire $0\main_int_rst[0:0] - attribute \src "ls180.v:1577.11-1577.41" - wire width 2 $0\main_interface0_bus_bte[1:0] - attribute \src "ls180.v:1576.11-1576.41" - wire width 3 $0\main_interface0_bus_cti[2:0] - attribute \src "ls180.v:2817.1-2863.4" - wire $0\main_interface0_converted_interface_ack[0:0] - attribute \src "ls180.v:230.5-230.51" - wire $0\main_interface0_converted_interface_err[0:0] - attribute \src "ls180.v:5574.1-5611.4" - wire width 32 $0\main_interface1_bus_adr[31:0] - attribute \src "ls180.v:1668.11-1668.41" - wire width 2 $0\main_interface1_bus_bte[1:0] - attribute \src "ls180.v:1667.11-1667.41" - wire width 3 $0\main_interface1_bus_cti[2:0] - attribute \src "ls180.v:5574.1-5611.4" - wire $0\main_interface1_bus_cyc[0:0] - attribute \src "ls180.v:1660.12-1660.45" - wire width 64 $0\main_interface1_bus_dat_w[63:0] - attribute \src "ls180.v:5574.1-5611.4" - wire width 8 $0\main_interface1_bus_sel[7:0] - attribute \src "ls180.v:5574.1-5611.4" - wire $0\main_interface1_bus_stb[0:0] - attribute \src "ls180.v:5574.1-5611.4" - wire $0\main_interface1_bus_we[0:0] - attribute \src "ls180.v:2877.1-2923.4" - wire $0\main_interface1_converted_interface_ack[0:0] - attribute \src "ls180.v:245.5-245.51" - wire $0\main_interface1_converted_interface_err[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 32 $0\main_libresocsim_bus_errors[31:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_libresocsim_en_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_libresocsim_en_storage[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_libresocsim_eventmanager_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_libresocsim_eventmanager_storage[0:0] - attribute \src "ls180.v:140.12-140.74" - wire width 16 $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] - attribute \src "ls180.v:133.5-133.69" - wire $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] - attribute \src "ls180.v:145.5-145.72" - wire $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] - attribute \src "ls180.v:148.11-148.79" - wire width 4 $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] - attribute \src "ls180.v:152.12-152.78" - wire width 16 $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] - attribute \src "ls180.v:75.11-75.52" - wire width 2 $0\main_libresocsim_libresoc_dbus_bte[1:0] - attribute \src "ls180.v:74.11-74.52" - wire width 3 $0\main_libresocsim_libresoc_dbus_cti[2:0] - attribute \src "ls180.v:86.11-86.52" - wire width 2 $0\main_libresocsim_libresoc_ibus_bte[1:0] - attribute \src "ls180.v:85.11-85.52" - wire width 3 $0\main_libresocsim_libresoc_ibus_cti[2:0] - attribute \src "ls180.v:2798.1-2803.4" - wire width 16 $0\main_libresocsim_libresoc_interrupt[15:0] - attribute \src "ls180.v:115.11-115.55" - wire width 2 $0\main_libresocsim_libresoc_jtag_wb_bte[1:0] - attribute \src "ls180.v:114.11-114.55" - wire width 3 $0\main_libresocsim_libresoc_jtag_wb_cti[2:0] - attribute \src "ls180.v:2817.1-2863.4" - wire width 30 $0\main_libresocsim_libresoc_xics_icp_adr[29:0] - attribute \src "ls180.v:2817.1-2863.4" - wire $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] - attribute \src "ls180.v:2805.1-2815.4" - wire width 32 $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] - attribute \src "ls180.v:2817.1-2863.4" - wire width 4 $0\main_libresocsim_libresoc_xics_icp_sel[3:0] - attribute \src "ls180.v:2817.1-2863.4" - wire $0\main_libresocsim_libresoc_xics_icp_stb[0:0] - attribute \src "ls180.v:2817.1-2863.4" - wire $0\main_libresocsim_libresoc_xics_icp_we[0:0] - attribute \src "ls180.v:2877.1-2923.4" - wire width 30 $0\main_libresocsim_libresoc_xics_ics_adr[29:0] - attribute \src "ls180.v:2877.1-2923.4" - wire $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] - attribute \src "ls180.v:2865.1-2875.4" - wire width 32 $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] - attribute \src "ls180.v:2877.1-2923.4" - wire width 4 $0\main_libresocsim_libresoc_xics_ics_sel[3:0] - attribute \src "ls180.v:2877.1-2923.4" - wire $0\main_libresocsim_libresoc_xics_ics_stb[0:0] - attribute \src "ls180.v:2877.1-2923.4" - wire $0\main_libresocsim_libresoc_xics_ics_we[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_libresocsim_load_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 32 $0\main_libresocsim_load_storage[31:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_libresocsim_ram_bus_ack[0:0] - attribute \src "ls180.v:173.5-173.40" - wire $0\main_libresocsim_ram_bus_err[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_libresocsim_reload_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 32 $0\main_libresocsim_reload_storage[31:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_libresocsim_reset_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_libresocsim_reset_storage[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_libresocsim_scratch_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 32 $0\main_libresocsim_scratch_storage[31:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_libresocsim_update_value_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_libresocsim_update_value_storage[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 32 $0\main_libresocsim_value[31:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 32 $0\main_libresocsim_value_status[31:0] - attribute \src "ls180.v:2986.1-2996.4" - wire width 8 $0\main_libresocsim_we[7:0] - attribute \src "ls180.v:3002.1-3007.4" - wire $0\main_libresocsim_zero_clear[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_libresocsim_zero_old_trigger[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_libresocsim_zero_pending[0:0] - attribute \src "ls180.v:4088.1-4134.4" - wire width 30 $0\main_litedram_wb_adr[29:0] - attribute \src "ls180.v:4088.1-4134.4" - wire $0\main_litedram_wb_cyc[0:0] - attribute \src "ls180.v:4076.1-4086.4" - wire width 16 $0\main_litedram_wb_dat_w[15:0] - attribute \src "ls180.v:4088.1-4134.4" - wire width 2 $0\main_litedram_wb_sel[1:0] - attribute \src "ls180.v:4088.1-4134.4" - wire $0\main_litedram_wb_stb[0:0] - attribute \src "ls180.v:4088.1-4134.4" - wire $0\main_litedram_wb_we[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 32 $0\main_pwm0_counter[31:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_pwm0_enable_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_pwm0_enable_storage[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_pwm0_period_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 32 $0\main_pwm0_period_storage[31:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_pwm0_width_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 32 $0\main_pwm0_width_storage[31:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 32 $0\main_pwm1_counter[31:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_pwm1_enable_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_pwm1_enable_storage[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_pwm1_period_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 32 $0\main_pwm1_period_storage[31:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_pwm1_width_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 32 $0\main_pwm1_width_storage[31:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_ram_bus_ram_bus_ack[0:0] - attribute \src "ls180.v:215.5-215.36" - wire $0\main_ram_bus_ram_bus_err[0:0] - attribute \src "ls180.v:3011.1-3021.4" - wire width 8 $0\main_ram_we[7:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 3 $0\main_rddata_en[2:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 3 $0\main_sdblock2mem_converter_demux[2:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdblock2mem_converter_source_first[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdblock2mem_converter_source_last[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 64 $0\main_sdblock2mem_converter_source_payload_data[63:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 4 $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdblock2mem_converter_strobe_all[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 5 $0\main_sdblock2mem_fifo_consume[4:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 6 $0\main_sdblock2mem_fifo_level[5:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 5 $0\main_sdblock2mem_fifo_produce[4:0] - attribute \src "ls180.v:1601.5-1601.41" - wire $0\main_sdblock2mem_fifo_replace[0:0] - attribute \src "ls180.v:5482.1-5489.4" - wire width 5 $0\main_sdblock2mem_fifo_wrport_adr[4:0] - attribute \src "ls180.v:5515.1-5554.4" - wire width 32 $0\main_sdblock2mem_sink_sink_payload_address[31:0] - attribute \src "ls180.v:5515.1-5554.4" - wire width 64 $0\main_sdblock2mem_sink_sink_payload_data1[63:0] - attribute \src "ls180.v:5515.1-5554.4" - wire $0\main_sdblock2mem_sink_sink_valid1[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 64 $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 32 $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] - attribute \src "ls180.v:5515.1-5554.4" - wire width 32 $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] - attribute \src "ls180.v:5515.1-5554.4" - wire $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] - attribute \src "ls180.v:5515.1-5554.4" - wire $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] - attribute \src "ls180.v:5515.1-5554.4" - wire $0\main_sdblock2mem_wishbonedmawriter_status[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdcore_block_count_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 32 $0\main_sdcore_block_count_storage[31:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdcore_block_length_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 10 $0\main_sdcore_block_length_storage[9:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdcore_cmd_argument_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 32 $0\main_sdcore_cmd_argument_storage[31:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdcore_cmd_command_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 32 $0\main_sdcore_cmd_command_storage[31:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 3 $0\main_sdcore_cmd_count[2:0] - attribute \src "ls180.v:5264.1-5454.4" - wire width 3 $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] - attribute \src "ls180.v:5264.1-5454.4" - wire $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdcore_cmd_done[0:0] - attribute \src "ls180.v:5264.1-5454.4" - wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] - attribute \src "ls180.v:5264.1-5454.4" - wire $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdcore_cmd_error[0:0] - attribute \src "ls180.v:5264.1-5454.4" - wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] - attribute \src "ls180.v:5264.1-5454.4" - wire $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 128 $0\main_sdcore_cmd_response_status[127:0] - attribute \src "ls180.v:5264.1-5454.4" - wire width 128 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] - attribute \src "ls180.v:5264.1-5454.4" - wire $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] - attribute \src "ls180.v:1410.5-1410.34" - wire $0\main_sdcore_cmd_send_w[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdcore_cmd_timeout[0:0] - attribute \src "ls180.v:5264.1-5454.4" - wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] - attribute \src "ls180.v:5264.1-5454.4" - wire $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 4 $0\main_sdcore_crc16_checker_cnt[3:0] - attribute \src "ls180.v:5170.1-5177.4" - wire $0\main_sdcore_crc16_checker_crc0_clr[0:0] - attribute \src "ls180.v:5226.1-5233.4" - wire width 16 $0\main_sdcore_crc16_checker_crc0_crc[15:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 16 $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] - attribute \src "ls180.v:5180.1-5187.4" - wire $0\main_sdcore_crc16_checker_crc1_clr[0:0] - attribute \src "ls180.v:5236.1-5243.4" - wire width 16 $0\main_sdcore_crc16_checker_crc1_crc[15:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 16 $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] - attribute \src "ls180.v:5190.1-5197.4" - wire $0\main_sdcore_crc16_checker_crc2_clr[0:0] - attribute \src "ls180.v:5246.1-5253.4" - wire width 16 $0\main_sdcore_crc16_checker_crc2_crc[15:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 16 $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] - attribute \src "ls180.v:5200.1-5207.4" - wire $0\main_sdcore_crc16_checker_crc3_clr[0:0] - attribute \src "ls180.v:5256.1-5263.4" - wire width 16 $0\main_sdcore_crc16_checker_crc3_crc[15:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 16 $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 16 $0\main_sdcore_crc16_checker_crctmp0[15:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 16 $0\main_sdcore_crc16_checker_crctmp1[15:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 16 $0\main_sdcore_crc16_checker_crctmp2[15:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 16 $0\main_sdcore_crc16_checker_crctmp3[15:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 16 $0\main_sdcore_crc16_checker_fifo0[15:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 16 $0\main_sdcore_crc16_checker_fifo1[15:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 16 $0\main_sdcore_crc16_checker_fifo2[15:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 16 $0\main_sdcore_crc16_checker_fifo3[15:0] - attribute \src "ls180.v:5264.1-5454.4" - wire $0\main_sdcore_crc16_checker_sink_first[0:0] - attribute \src "ls180.v:5264.1-5454.4" - wire $0\main_sdcore_crc16_checker_sink_last[0:0] - attribute \src "ls180.v:5264.1-5454.4" - wire width 8 $0\main_sdcore_crc16_checker_sink_payload_data[7:0] - attribute \src "ls180.v:5215.1-5222.4" - wire $0\main_sdcore_crc16_checker_sink_ready[0:0] - attribute \src "ls180.v:5264.1-5454.4" - wire $0\main_sdcore_crc16_checker_sink_valid[0:0] - attribute \src "ls180.v:1516.5-1516.50" - wire $0\main_sdcore_crc16_checker_source_first[0:0] - attribute \src "ls180.v:5209.1-5214.4" - wire $0\main_sdcore_crc16_checker_source_valid[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 8 $0\main_sdcore_crc16_checker_val[7:0] - attribute \src "ls180.v:5162.1-5167.4" - wire $0\main_sdcore_crc16_checker_valid[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 3 $0\main_sdcore_crc16_inserter_cnt[2:0] - attribute \src "ls180.v:5082.1-5161.4" - wire width 3 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] - attribute \src "ls180.v:5082.1-5161.4" - wire $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] - attribute \src "ls180.v:5044.1-5051.4" - wire width 16 $0\main_sdcore_crc16_inserter_crc0_crc[15:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 16 $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] - attribute \src "ls180.v:5054.1-5061.4" - wire width 16 $0\main_sdcore_crc16_inserter_crc1_crc[15:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 16 $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] - attribute \src "ls180.v:5064.1-5071.4" - wire width 16 $0\main_sdcore_crc16_inserter_crc2_crc[15:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 16 $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] - attribute \src "ls180.v:5074.1-5081.4" - wire width 16 $0\main_sdcore_crc16_inserter_crc3_crc[15:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 16 $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 16 $0\main_sdcore_crc16_inserter_crctmp0[15:0] - attribute \src "ls180.v:5082.1-5161.4" - wire width 16 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] - attribute \src "ls180.v:5082.1-5161.4" - wire $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 16 $0\main_sdcore_crc16_inserter_crctmp1[15:0] - attribute \src "ls180.v:5082.1-5161.4" - wire width 16 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] - attribute \src "ls180.v:5082.1-5161.4" - wire $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 16 $0\main_sdcore_crc16_inserter_crctmp2[15:0] - attribute \src "ls180.v:5082.1-5161.4" - wire width 16 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] - attribute \src "ls180.v:5082.1-5161.4" - wire $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 16 $0\main_sdcore_crc16_inserter_crctmp3[15:0] - attribute \src "ls180.v:5082.1-5161.4" - wire width 16 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] - attribute \src "ls180.v:5082.1-5161.4" - wire $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] - attribute \src "ls180.v:5082.1-5161.4" - wire $0\main_sdcore_crc16_inserter_sink_ready[0:0] - attribute \src "ls180.v:1473.5-1473.51" - wire $0\main_sdcore_crc16_inserter_source_first[0:0] - attribute \src "ls180.v:5082.1-5161.4" - wire $0\main_sdcore_crc16_inserter_source_last[0:0] - attribute \src "ls180.v:5082.1-5161.4" - wire width 8 $0\main_sdcore_crc16_inserter_source_payload_data[7:0] - attribute \src "ls180.v:5264.1-5454.4" - wire $0\main_sdcore_crc16_inserter_source_ready[0:0] - attribute \src "ls180.v:5082.1-5161.4" - wire $0\main_sdcore_crc16_inserter_source_valid[0:0] - attribute \src "ls180.v:5022.1-5029.4" - wire width 7 $0\main_sdcore_crc7_inserter_crc[6:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 7 $0\main_sdcore_crc7_inserter_crcreg0[6:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 32 $0\main_sdcore_data_count[31:0] - attribute \src "ls180.v:5264.1-5454.4" - wire width 32 $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] - attribute \src "ls180.v:5264.1-5454.4" - wire $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdcore_data_done[0:0] - attribute \src "ls180.v:5264.1-5454.4" - wire $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] - attribute \src "ls180.v:5264.1-5454.4" - wire $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdcore_data_error[0:0] - attribute \src "ls180.v:5264.1-5454.4" - wire $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] - attribute \src "ls180.v:5264.1-5454.4" - wire $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdcore_data_timeout[0:0] - attribute \src "ls180.v:5264.1-5454.4" - wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] - attribute \src "ls180.v:5264.1-5454.4" - wire $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 3 $0\main_sdmem2block_converter_mux[2:0] - attribute \src "ls180.v:5660.1-5688.4" - wire width 8 $0\main_sdmem2block_converter_source_payload_data[7:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdmem2block_dma_base_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 64 $0\main_sdmem2block_dma_base_storage[63:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 64 $0\main_sdmem2block_dma_data[63:0] - attribute \src "ls180.v:5574.1-5611.4" - wire width 64 $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] - attribute \src "ls180.v:5574.1-5611.4" - wire $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] - attribute \src "ls180.v:5612.1-5648.4" - wire $0\main_sdmem2block_dma_done_status[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdmem2block_dma_enable_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdmem2block_dma_enable_storage[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdmem2block_dma_length_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 32 $0\main_sdmem2block_dma_length_storage[31:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdmem2block_dma_loop_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdmem2block_dma_loop_storage[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 32 $0\main_sdmem2block_dma_offset[31:0] - attribute \src "ls180.v:5612.1-5648.4" - wire width 32 $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] - attribute \src "ls180.v:5612.1-5648.4" - wire $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] - attribute \src "ls180.v:5612.1-5648.4" - wire $0\main_sdmem2block_dma_sink_last[0:0] - attribute \src "ls180.v:5612.1-5648.4" - wire width 32 $0\main_sdmem2block_dma_sink_payload_address[31:0] - attribute \src "ls180.v:5574.1-5611.4" - wire $0\main_sdmem2block_dma_sink_ready[0:0] - attribute \src "ls180.v:5612.1-5648.4" - wire $0\main_sdmem2block_dma_sink_valid[0:0] - attribute \src "ls180.v:1681.5-1681.45" - wire $0\main_sdmem2block_dma_source_first[0:0] - attribute \src "ls180.v:5574.1-5611.4" - wire $0\main_sdmem2block_dma_source_last[0:0] - attribute \src "ls180.v:5574.1-5611.4" - wire width 64 $0\main_sdmem2block_dma_source_payload_data[63:0] - attribute \src "ls180.v:5574.1-5611.4" - wire $0\main_sdmem2block_dma_source_valid[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 5 $0\main_sdmem2block_fifo_consume[4:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 6 $0\main_sdmem2block_fifo_level[5:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 5 $0\main_sdmem2block_fifo_produce[4:0] - attribute \src "ls180.v:1737.5-1737.41" - wire $0\main_sdmem2block_fifo_replace[0:0] - attribute \src "ls180.v:5702.1-5709.4" - wire width 5 $0\main_sdmem2block_fifo_wrport_adr[4:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdphy_clocker_clk0[0:0] - attribute \src "ls180.v:4428.1-4456.4" - wire $0\main_sdphy_clocker_clk1[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdphy_clocker_clk_d[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 9 $0\main_sdphy_clocker_clks[8:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdphy_clocker_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 9 $0\main_sdphy_clocker_storage[8:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 8 $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 3 $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] - attribute \src "ls180.v:1202.5-1202.53" - wire $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] - attribute \src "ls180.v:1203.5-1203.52" - wire $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 8 $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 4 $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] - attribute \src "ls180.v:1183.5-1183.46" - wire $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdphy_cmdr_cmdr_reset[0:0] - attribute \src "ls180.v:4602.1-4695.4" - wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] - attribute \src "ls180.v:4602.1-4695.4" - wire $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdphy_cmdr_cmdr_run[0:0] - attribute \src "ls180.v:4602.1-4695.4" - wire $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 8 $0\main_sdphy_cmdr_count[7:0] - attribute \src "ls180.v:4602.1-4695.4" - wire width 8 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] - attribute \src "ls180.v:4602.1-4695.4" - wire $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] - attribute \src "ls180.v:1156.5-1156.49" - wire $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] - attribute \src "ls180.v:1157.5-1157.48" - wire $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] - attribute \src "ls180.v:1158.5-1158.55" - wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] - attribute \src "ls180.v:1160.5-1160.57" - wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] - attribute \src "ls180.v:1161.5-1161.58" - wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] - attribute \src "ls180.v:1163.11-1163.64" - wire width 4 $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] - attribute \src "ls180.v:1164.5-1164.59" - wire $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] - attribute \src "ls180.v:4602.1-4695.4" - wire $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] - attribute \src "ls180.v:4602.1-4695.4" - wire $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:4602.1-4695.4" - wire $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1169.11-1169.57" - wire width 4 $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1170.5-1170.52" - wire $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5264.1-5454.4" - wire $0\main_sdphy_cmdr_sink_last[0:0] - attribute \src "ls180.v:5264.1-5454.4" - wire width 8 $0\main_sdphy_cmdr_sink_payload_length[7:0] - attribute \src "ls180.v:4602.1-4695.4" - wire $0\main_sdphy_cmdr_sink_ready[0:0] - attribute \src "ls180.v:5264.1-5454.4" - wire $0\main_sdphy_cmdr_sink_valid[0:0] - attribute \src "ls180.v:4602.1-4695.4" - wire $0\main_sdphy_cmdr_source_last[0:0] - attribute \src "ls180.v:4602.1-4695.4" - wire width 8 $0\main_sdphy_cmdr_source_payload_data[7:0] - attribute \src "ls180.v:4602.1-4695.4" - wire width 3 $0\main_sdphy_cmdr_source_payload_status[2:0] - attribute \src "ls180.v:5264.1-5454.4" - wire $0\main_sdphy_cmdr_source_ready[0:0] - attribute \src "ls180.v:4602.1-4695.4" - wire $0\main_sdphy_cmdr_source_valid[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 32 $0\main_sdphy_cmdr_timeout[31:0] - attribute \src "ls180.v:4602.1-4695.4" - wire width 32 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] - attribute \src "ls180.v:4602.1-4695.4" - wire $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 8 $0\main_sdphy_cmdw_count[7:0] - attribute \src "ls180.v:4492.1-4568.4" - wire width 8 $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] - attribute \src "ls180.v:4492.1-4568.4" - wire $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] - attribute \src "ls180.v:4492.1-4568.4" - wire $0\main_sdphy_cmdw_done[0:0] - attribute \src "ls180.v:4492.1-4568.4" - wire $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:4492.1-4568.4" - wire $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:4492.1-4568.4" - wire $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1146.11-1146.57" - wire width 4 $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1147.5-1147.52" - wire $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5264.1-5454.4" - wire $0\main_sdphy_cmdw_sink_last[0:0] - attribute \src "ls180.v:5264.1-5454.4" - wire width 8 $0\main_sdphy_cmdw_sink_payload_data[7:0] - attribute \src "ls180.v:4492.1-4568.4" - wire $0\main_sdphy_cmdw_sink_ready[0:0] - attribute \src "ls180.v:5264.1-5454.4" - wire $0\main_sdphy_cmdw_sink_valid[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 10 $0\main_sdphy_datar_count[9:0] - attribute \src "ls180.v:4863.1-4964.4" - wire width 10 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] - attribute \src "ls180.v:4863.1-4964.4" - wire $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdphy_datar_datar_buf_source_first[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdphy_datar_datar_buf_source_last[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 8 $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdphy_datar_datar_buf_source_valid[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdphy_datar_datar_converter_demux[0:0] - attribute \src "ls180.v:1358.5-1358.55" - wire $0\main_sdphy_datar_datar_converter_sink_first[0:0] - attribute \src "ls180.v:1359.5-1359.54" - wire $0\main_sdphy_datar_datar_converter_sink_last[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdphy_datar_datar_converter_source_first[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdphy_datar_datar_converter_source_last[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 8 $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 2 $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdphy_datar_datar_converter_strobe_all[0:0] - attribute \src "ls180.v:1339.5-1339.48" - wire $0\main_sdphy_datar_datar_pads_in_ready[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdphy_datar_datar_reset[0:0] - attribute \src "ls180.v:4863.1-4964.4" - wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] - attribute \src "ls180.v:4863.1-4964.4" - wire $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdphy_datar_datar_run[0:0] - attribute \src "ls180.v:4863.1-4964.4" - wire $0\main_sdphy_datar_datar_source_source_ready0[0:0] - attribute \src "ls180.v:1310.5-1310.50" - wire $0\main_sdphy_datar_pads_in_pads_in_first[0:0] - attribute \src "ls180.v:1311.5-1311.49" - wire $0\main_sdphy_datar_pads_in_pads_in_last[0:0] - attribute \src "ls180.v:1312.5-1312.56" - wire $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] - attribute \src "ls180.v:1314.5-1314.58" - wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] - attribute \src "ls180.v:1315.5-1315.59" - wire $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] - attribute \src "ls180.v:1317.11-1317.65" - wire width 4 $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] - attribute \src "ls180.v:1318.5-1318.60" - wire $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] - attribute \src "ls180.v:4863.1-4964.4" - wire $0\main_sdphy_datar_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1321.5-1321.51" - wire $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1322.5-1322.52" - wire $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1323.11-1323.58" - wire width 4 $0\main_sdphy_datar_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1324.5-1324.53" - wire $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5264.1-5454.4" - wire $0\main_sdphy_datar_sink_last[0:0] - attribute \src "ls180.v:5264.1-5454.4" - wire width 10 $0\main_sdphy_datar_sink_payload_block_length[9:0] - attribute \src "ls180.v:4863.1-4964.4" - wire $0\main_sdphy_datar_sink_ready[0:0] - attribute \src "ls180.v:5264.1-5454.4" - wire $0\main_sdphy_datar_sink_valid[0:0] - attribute \src "ls180.v:1331.5-1331.41" - wire $0\main_sdphy_datar_source_first[0:0] - attribute \src "ls180.v:4863.1-4964.4" - wire $0\main_sdphy_datar_source_last[0:0] - attribute \src "ls180.v:4863.1-4964.4" - wire width 8 $0\main_sdphy_datar_source_payload_data[7:0] - attribute \src "ls180.v:4863.1-4964.4" - wire width 3 $0\main_sdphy_datar_source_payload_status[2:0] - attribute \src "ls180.v:5264.1-5454.4" - wire $0\main_sdphy_datar_source_ready[0:0] - attribute \src "ls180.v:4863.1-4964.4" - wire $0\main_sdphy_datar_source_valid[0:0] - attribute \src "ls180.v:4863.1-4964.4" - wire $0\main_sdphy_datar_stop[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 32 $0\main_sdphy_datar_timeout[31:0] - attribute \src "ls180.v:4863.1-4964.4" - wire width 32 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] - attribute \src "ls180.v:4863.1-4964.4" - wire $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 8 $0\main_sdphy_dataw_count[7:0] - attribute \src "ls180.v:4757.1-4829.4" - wire width 8 $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] - attribute \src "ls180.v:4757.1-4829.4" - wire $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdphy_dataw_crcr_buf_source_first[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdphy_dataw_crcr_buf_source_last[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 8 $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 3 $0\main_sdphy_dataw_crcr_converter_demux[2:0] - attribute \src "ls180.v:1280.5-1280.54" - wire $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] - attribute \src "ls180.v:1281.5-1281.53" - wire $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdphy_dataw_crcr_converter_source_first[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdphy_dataw_crcr_converter_source_last[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 8 $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 4 $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] - attribute \src "ls180.v:1261.5-1261.47" - wire $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdphy_dataw_crcr_reset[0:0] - attribute \src "ls180.v:4729.1-4756.4" - wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] - attribute \src "ls180.v:4729.1-4756.4" - wire $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdphy_dataw_crcr_run[0:0] - attribute \src "ls180.v:4729.1-4756.4" - wire $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] - attribute \src "ls180.v:4729.1-4756.4" - wire $0\main_sdphy_dataw_error[0:0] - attribute \src "ls180.v:1248.5-1248.50" - wire $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] - attribute \src "ls180.v:1249.5-1249.49" - wire $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] - attribute \src "ls180.v:1250.5-1250.56" - wire $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] - attribute \src "ls180.v:1251.5-1251.58" - wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] - attribute \src "ls180.v:1252.5-1252.58" - wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] - attribute \src "ls180.v:1253.5-1253.59" - wire $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] - attribute \src "ls180.v:1254.11-1254.65" - wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] - attribute \src "ls180.v:1255.11-1255.65" - wire width 4 $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] - attribute \src "ls180.v:1256.5-1256.60" - wire $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] - attribute \src "ls180.v:1246.5-1246.50" - wire $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] - attribute \src "ls180.v:4757.1-4829.4" - wire $0\main_sdphy_dataw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1235.5-1235.51" - wire $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1236.5-1236.52" - wire $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:4757.1-4829.4" - wire width 4 $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:4757.1-4829.4" - wire $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:5264.1-5454.4" - wire $0\main_sdphy_dataw_sink_first[0:0] - attribute \src "ls180.v:5264.1-5454.4" - wire $0\main_sdphy_dataw_sink_last[0:0] - attribute \src "ls180.v:5264.1-5454.4" - wire width 8 $0\main_sdphy_dataw_sink_payload_data[7:0] - attribute \src "ls180.v:4757.1-4829.4" - wire $0\main_sdphy_dataw_sink_ready[0:0] - attribute \src "ls180.v:5264.1-5454.4" - wire $0\main_sdphy_dataw_sink_valid[0:0] - attribute \src "ls180.v:4757.1-4829.4" - wire $0\main_sdphy_dataw_start[0:0] - attribute \src "ls180.v:4757.1-4829.4" - wire $0\main_sdphy_dataw_stop[0:0] - attribute \src "ls180.v:4729.1-4756.4" - wire $0\main_sdphy_dataw_valid[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 8 $0\main_sdphy_init_count[7:0] - attribute \src "ls180.v:4458.1-4491.4" - wire width 8 $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] - attribute \src "ls180.v:4458.1-4491.4" - wire $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] - attribute \src "ls180.v:1128.5-1128.40" - wire $0\main_sdphy_init_initialize_w[0:0] - attribute \src "ls180.v:4458.1-4491.4" - wire $0\main_sdphy_init_pads_out_payload_clk[0:0] - attribute \src "ls180.v:4458.1-4491.4" - wire $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:4458.1-4491.4" - wire $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:4458.1-4491.4" - wire width 4 $0\main_sdphy_init_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:4458.1-4491.4" - wire $0\main_sdphy_init_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:7439.1-7509.4" - wire $0\main_sdphy_sdpads_cmd_i[0:0] - attribute \src "ls180.v:7439.1-7509.4" - wire width 4 $0\main_sdphy_sdpads_data_i[3:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_address_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 13 $0\main_sdram_address_storage[12:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_baddress_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 2 $0\main_sdram_baddress_storage[1:0] - attribute \src "ls180.v:3233.1-3240.4" - wire $0\main_sdram_bankmachine0_auto_precharge[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 4 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:450.5-450.64" - wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:433.5-433.67" - wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:434.5-434.66" - wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3255.1-3262.4" - wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 22 $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3222.1-3229.4" - wire width 13 $0\main_sdram_bankmachine0_cmd_payload_a[12:0] - attribute \src "ls180.v:3271.1-3364.4" - wire $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] - attribute \src "ls180.v:3271.1-3364.4" - wire $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3271.1-3364.4" - wire $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3271.1-3364.4" - wire $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3271.1-3364.4" - wire $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] - attribute \src "ls180.v:3271.1-3364.4" - wire $0\main_sdram_bankmachine0_cmd_payload_we[0:0] - attribute \src "ls180.v:3920.1-3928.4" - wire $0\main_sdram_bankmachine0_cmd_ready[0:0] - attribute \src "ls180.v:3271.1-3364.4" - wire $0\main_sdram_bankmachine0_cmd_valid[0:0] - attribute \src "ls180.v:3271.1-3364.4" - wire $0\main_sdram_bankmachine0_refresh_gnt[0:0] - attribute \src "ls180.v:3271.1-3364.4" - wire $0\main_sdram_bankmachine0_req_rdata_valid[0:0] - attribute \src "ls180.v:3271.1-3364.4" - wire $0\main_sdram_bankmachine0_req_wdata_ready[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 13 $0\main_sdram_bankmachine0_row[12:0] - attribute \src "ls180.v:3271.1-3364.4" - wire $0\main_sdram_bankmachine0_row_close[0:0] - attribute \src "ls180.v:3271.1-3364.4" - wire $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3271.1-3364.4" - wire $0\main_sdram_bankmachine0_row_open[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_bankmachine0_row_opened[0:0] - attribute \src "ls180.v:492.32-492.76" - wire $0\main_sdram_bankmachine0_trascon_ready[0:0] - attribute \src "ls180.v:490.32-490.75" - wire $0\main_sdram_bankmachine0_trccon_ready[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 3 $0\main_sdram_bankmachine0_twtpcon_count[2:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_bankmachine0_twtpcon_ready[0:0] - attribute \src "ls180.v:3390.1-3397.4" - wire $0\main_sdram_bankmachine1_auto_precharge[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 4 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:532.5-532.64" - wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:515.5-515.67" - wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:516.5-516.66" - wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3412.1-3419.4" - wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 22 $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3379.1-3386.4" - wire width 13 $0\main_sdram_bankmachine1_cmd_payload_a[12:0] - attribute \src "ls180.v:3428.1-3521.4" - wire $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] - attribute \src "ls180.v:3428.1-3521.4" - wire $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3428.1-3521.4" - wire $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3428.1-3521.4" - wire $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3428.1-3521.4" - wire $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] - attribute \src "ls180.v:3428.1-3521.4" - wire $0\main_sdram_bankmachine1_cmd_payload_we[0:0] - attribute \src "ls180.v:3929.1-3937.4" - wire $0\main_sdram_bankmachine1_cmd_ready[0:0] - attribute \src "ls180.v:3428.1-3521.4" - wire $0\main_sdram_bankmachine1_cmd_valid[0:0] - attribute \src "ls180.v:3428.1-3521.4" - wire $0\main_sdram_bankmachine1_refresh_gnt[0:0] - attribute \src "ls180.v:3428.1-3521.4" - wire $0\main_sdram_bankmachine1_req_rdata_valid[0:0] - attribute \src "ls180.v:3428.1-3521.4" - wire $0\main_sdram_bankmachine1_req_wdata_ready[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 13 $0\main_sdram_bankmachine1_row[12:0] - attribute \src "ls180.v:3428.1-3521.4" - wire $0\main_sdram_bankmachine1_row_close[0:0] - attribute \src "ls180.v:3428.1-3521.4" - wire $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3428.1-3521.4" - wire $0\main_sdram_bankmachine1_row_open[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_bankmachine1_row_opened[0:0] - attribute \src "ls180.v:574.32-574.76" - wire $0\main_sdram_bankmachine1_trascon_ready[0:0] - attribute \src "ls180.v:572.32-572.75" - wire $0\main_sdram_bankmachine1_trccon_ready[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 3 $0\main_sdram_bankmachine1_twtpcon_count[2:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_bankmachine1_twtpcon_ready[0:0] - attribute \src "ls180.v:3547.1-3554.4" - wire $0\main_sdram_bankmachine2_auto_precharge[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 4 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:614.5-614.64" - wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:597.5-597.67" - wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:598.5-598.66" - wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3569.1-3576.4" - wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 22 $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3536.1-3543.4" - wire width 13 $0\main_sdram_bankmachine2_cmd_payload_a[12:0] - attribute \src "ls180.v:3585.1-3678.4" - wire $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] - attribute \src "ls180.v:3585.1-3678.4" - wire $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3585.1-3678.4" - wire $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3585.1-3678.4" - wire $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3585.1-3678.4" - wire $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] - attribute \src "ls180.v:3585.1-3678.4" - wire $0\main_sdram_bankmachine2_cmd_payload_we[0:0] - attribute \src "ls180.v:3938.1-3946.4" - wire $0\main_sdram_bankmachine2_cmd_ready[0:0] - attribute \src "ls180.v:3585.1-3678.4" - wire $0\main_sdram_bankmachine2_cmd_valid[0:0] - attribute \src "ls180.v:3585.1-3678.4" - wire $0\main_sdram_bankmachine2_refresh_gnt[0:0] - attribute \src "ls180.v:3585.1-3678.4" - wire $0\main_sdram_bankmachine2_req_rdata_valid[0:0] - attribute \src "ls180.v:3585.1-3678.4" - wire $0\main_sdram_bankmachine2_req_wdata_ready[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 13 $0\main_sdram_bankmachine2_row[12:0] - attribute \src "ls180.v:3585.1-3678.4" - wire $0\main_sdram_bankmachine2_row_close[0:0] - attribute \src "ls180.v:3585.1-3678.4" - wire $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3585.1-3678.4" - wire $0\main_sdram_bankmachine2_row_open[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_bankmachine2_row_opened[0:0] - attribute \src "ls180.v:656.32-656.76" - wire $0\main_sdram_bankmachine2_trascon_ready[0:0] - attribute \src "ls180.v:654.32-654.75" - wire $0\main_sdram_bankmachine2_trccon_ready[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 3 $0\main_sdram_bankmachine2_twtpcon_count[2:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_bankmachine2_twtpcon_ready[0:0] - attribute \src "ls180.v:3704.1-3711.4" - wire $0\main_sdram_bankmachine3_auto_precharge[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 4 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:696.5-696.64" - wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] - attribute \src "ls180.v:679.5-679.67" - wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] - attribute \src "ls180.v:680.5-680.66" - wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] - attribute \src "ls180.v:3726.1-3733.4" - wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 22 $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:3693.1-3700.4" - wire width 13 $0\main_sdram_bankmachine3_cmd_payload_a[12:0] - attribute \src "ls180.v:3742.1-3835.4" - wire $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] - attribute \src "ls180.v:3742.1-3835.4" - wire $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:3742.1-3835.4" - wire $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] - attribute \src "ls180.v:3742.1-3835.4" - wire $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] - attribute \src "ls180.v:3742.1-3835.4" - wire $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] - attribute \src "ls180.v:3742.1-3835.4" - wire $0\main_sdram_bankmachine3_cmd_payload_we[0:0] - attribute \src "ls180.v:3947.1-3955.4" - wire $0\main_sdram_bankmachine3_cmd_ready[0:0] - attribute \src "ls180.v:3742.1-3835.4" - wire $0\main_sdram_bankmachine3_cmd_valid[0:0] - attribute \src "ls180.v:3742.1-3835.4" - wire $0\main_sdram_bankmachine3_refresh_gnt[0:0] - attribute \src "ls180.v:3742.1-3835.4" - wire $0\main_sdram_bankmachine3_req_rdata_valid[0:0] - attribute \src "ls180.v:3742.1-3835.4" - wire $0\main_sdram_bankmachine3_req_wdata_ready[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 13 $0\main_sdram_bankmachine3_row[12:0] - attribute \src "ls180.v:3742.1-3835.4" - wire $0\main_sdram_bankmachine3_row_close[0:0] - attribute \src "ls180.v:3742.1-3835.4" - wire $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:3742.1-3835.4" - wire $0\main_sdram_bankmachine3_row_open[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_bankmachine3_row_opened[0:0] - attribute \src "ls180.v:738.32-738.76" - wire $0\main_sdram_bankmachine3_trascon_ready[0:0] - attribute \src "ls180.v:736.32-736.75" - wire $0\main_sdram_bankmachine3_trccon_ready[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 3 $0\main_sdram_bankmachine3_twtpcon_count[2:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_bankmachine3_twtpcon_ready[0:0] - attribute \src "ls180.v:3869.1-3874.4" - wire $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] - attribute \src "ls180.v:3875.1-3880.4" - wire $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] - attribute \src "ls180.v:3881.1-3886.4" - wire $0\main_sdram_choose_cmd_cmd_payload_we[0:0] - attribute \src "ls180.v:746.5-746.43" - wire $0\main_sdram_choose_cmd_cmd_ready[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 2 $0\main_sdram_choose_cmd_grant[1:0] - attribute \src "ls180.v:3855.1-3861.4" - wire width 4 $0\main_sdram_choose_cmd_valids[3:0] - attribute \src "ls180.v:744.5-744.48" - wire $0\main_sdram_choose_cmd_want_activates[0:0] - attribute \src "ls180.v:743.5-743.43" - wire $0\main_sdram_choose_cmd_want_cmds[0:0] - attribute \src "ls180.v:741.5-741.44" - wire $0\main_sdram_choose_cmd_want_reads[0:0] - attribute \src "ls180.v:742.5-742.45" - wire $0\main_sdram_choose_cmd_want_writes[0:0] - attribute \src "ls180.v:3902.1-3907.4" - wire $0\main_sdram_choose_req_cmd_payload_cas[0:0] - attribute \src "ls180.v:3908.1-3913.4" - wire $0\main_sdram_choose_req_cmd_payload_ras[0:0] - attribute \src "ls180.v:3914.1-3919.4" - wire $0\main_sdram_choose_req_cmd_payload_we[0:0] - attribute \src "ls180.v:3960.1-4032.4" - wire $0\main_sdram_choose_req_cmd_ready[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 2 $0\main_sdram_choose_req_grant[1:0] - attribute \src "ls180.v:3888.1-3894.4" - wire width 4 $0\main_sdram_choose_req_valids[3:0] - attribute \src "ls180.v:3960.1-4032.4" - wire $0\main_sdram_choose_req_want_activates[0:0] - attribute \src "ls180.v:3960.1-4032.4" - wire $0\main_sdram_choose_req_want_reads[0:0] - attribute \src "ls180.v:3960.1-4032.4" - wire $0\main_sdram_choose_req_want_writes[0:0] - attribute \src "ls180.v:3177.1-3207.4" - wire $0\main_sdram_cmd_last[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 13 $0\main_sdram_cmd_payload_a[12:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 2 $0\main_sdram_cmd_payload_ba[1:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_cmd_payload_cas[0:0] - attribute \src "ls180.v:394.5-394.42" - wire $0\main_sdram_cmd_payload_is_read[0:0] - attribute \src "ls180.v:395.5-395.43" - wire $0\main_sdram_cmd_payload_is_write[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_cmd_payload_ras[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_cmd_payload_we[0:0] - attribute \src "ls180.v:3960.1-4032.4" - wire $0\main_sdram_cmd_ready[0:0] - attribute \src "ls180.v:3177.1-3207.4" - wire $0\main_sdram_cmd_valid[0:0] - attribute \src "ls180.v:330.5-330.38" - wire $0\main_sdram_command_issue_w[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_command_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 6 $0\main_sdram_command_storage[5:0] - attribute \src "ls180.v:379.5-379.35" - wire $0\main_sdram_dfi_p0_act_n[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 13 $0\main_sdram_dfi_p0_address[12:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 2 $0\main_sdram_dfi_p0_bank[1:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_dfi_p0_cas_n[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_dfi_p0_cs_n[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_dfi_p0_ras_n[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_dfi_p0_rddata_en[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_dfi_p0_we_n[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_dfi_p0_wrdata_en[0:0] - attribute \src "ls180.v:3960.1-4032.4" - wire $0\main_sdram_en0[0:0] - attribute \src "ls180.v:3960.1-4032.4" - wire $0\main_sdram_en1[0:0] - attribute \src "ls180.v:4056.1-4069.4" - wire width 16 $0\main_sdram_interface_wdata[15:0] - attribute \src "ls180.v:4056.1-4069.4" - wire width 2 $0\main_sdram_interface_wdata_we[1:0] - attribute \src "ls180.v:280.5-280.36" - wire $0\main_sdram_inti_p0_act_n[0:0] - attribute \src "ls180.v:3118.1-3134.4" - wire $0\main_sdram_inti_p0_cas_n[0:0] - attribute \src "ls180.v:3118.1-3134.4" - wire $0\main_sdram_inti_p0_cs_n[0:0] - attribute \src "ls180.v:3118.1-3134.4" - wire $0\main_sdram_inti_p0_ras_n[0:0] - attribute \src "ls180.v:3060.1-3114.4" - wire width 16 $0\main_sdram_inti_p0_rddata[15:0] - attribute \src "ls180.v:3060.1-3114.4" - wire $0\main_sdram_inti_p0_rddata_valid[0:0] - attribute \src "ls180.v:3118.1-3134.4" - wire $0\main_sdram_inti_p0_we_n[0:0] - attribute \src "ls180.v:3060.1-3114.4" - wire $0\main_sdram_master_p0_act_n[0:0] - attribute \src "ls180.v:3060.1-3114.4" - wire width 13 $0\main_sdram_master_p0_address[12:0] - attribute \src "ls180.v:3060.1-3114.4" - wire width 2 $0\main_sdram_master_p0_bank[1:0] - attribute \src "ls180.v:3060.1-3114.4" - wire $0\main_sdram_master_p0_cas_n[0:0] - attribute \src "ls180.v:3060.1-3114.4" - wire $0\main_sdram_master_p0_cke[0:0] - attribute \src "ls180.v:3060.1-3114.4" - wire $0\main_sdram_master_p0_cs_n[0:0] - attribute \src "ls180.v:3060.1-3114.4" - wire $0\main_sdram_master_p0_odt[0:0] - attribute \src "ls180.v:3060.1-3114.4" - wire $0\main_sdram_master_p0_ras_n[0:0] - attribute \src "ls180.v:3060.1-3114.4" - wire $0\main_sdram_master_p0_rddata_en[0:0] - attribute \src "ls180.v:3060.1-3114.4" - wire $0\main_sdram_master_p0_reset_n[0:0] - attribute \src "ls180.v:3060.1-3114.4" - wire $0\main_sdram_master_p0_we_n[0:0] - attribute \src "ls180.v:3060.1-3114.4" - wire width 16 $0\main_sdram_master_p0_wrdata[15:0] - attribute \src "ls180.v:3060.1-3114.4" - wire $0\main_sdram_master_p0_wrdata_en[0:0] - attribute \src "ls180.v:3060.1-3114.4" - wire width 2 $0\main_sdram_master_p0_wrdata_mask[1:0] - attribute \src "ls180.v:777.12-777.36" - wire width 13 $0\main_sdram_nop_a[12:0] - attribute \src "ls180.v:778.11-778.35" - wire width 2 $0\main_sdram_nop_ba[1:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_postponer_count[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_postponer_req_o[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_sequencer_count[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 4 $0\main_sdram_sequencer_counter[3:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_sequencer_done1[0:0] - attribute \src "ls180.v:3177.1-3207.4" - wire $0\main_sdram_sequencer_start0[0:0] - attribute \src "ls180.v:3060.1-3114.4" - wire width 16 $0\main_sdram_slave_p0_rddata[15:0] - attribute \src "ls180.v:3060.1-3114.4" - wire $0\main_sdram_slave_p0_rddata_valid[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 16 $0\main_sdram_status[15:0] - attribute \src "ls180.v:780.5-780.31" - wire $0\main_sdram_steerer0[0:0] - attribute \src "ls180.v:781.5-781.31" - wire $0\main_sdram_steerer1[0:0] - attribute \src "ls180.v:3960.1-4032.4" - wire width 2 $0\main_sdram_steerer_sel[1:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 4 $0\main_sdram_storage[3:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_tccdcon_count[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_tccdcon_ready[0:0] - attribute \src "ls180.v:785.32-785.63" - wire $0\main_sdram_tfawcon_ready[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 5 $0\main_sdram_time0[4:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 4 $0\main_sdram_time1[3:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 10 $0\main_sdram_timer_count1[9:0] - attribute \src "ls180.v:783.32-783.63" - wire $0\main_sdram_trrdcon_ready[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 3 $0\main_sdram_twtrcon_count[2:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_twtrcon_ready[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_sdram_wrdata_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 16 $0\main_sdram_wrdata_storage[15:0] - attribute \src "ls180.v:2937.1-2983.4" - wire $0\main_socbushandler_converted_interface_ack[0:0] - attribute \src "ls180.v:832.5-832.54" - wire $0\main_socbushandler_converted_interface_err[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_socbushandler_counter[0:0] - attribute \src "ls180.v:2937.1-2983.4" - wire $0\main_socbushandler_counter_converter2_next_value[0:0] - attribute \src "ls180.v:2937.1-2983.4" - wire $0\main_socbushandler_counter_converter2_next_value_ce[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 64 $0\main_socbushandler_dat_r[63:0] - attribute \src "ls180.v:2937.1-2983.4" - wire $0\main_socbushandler_skip[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 16 $0\main_spimaster11_storage[15:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_spimaster12_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 8 $0\main_spimaster16_storage[7:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_spimaster17_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_spimaster1_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 16 $0\main_spimaster1_storage[15:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_spimaster21_storage[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_spimaster22_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_spimaster23_storage[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_spimaster24_re[0:0] - attribute \src "ls180.v:4289.1-4337.4" - wire $0\main_spimaster25_clk_enable[0:0] - attribute \src "ls180.v:4289.1-4337.4" - wire $0\main_spimaster26_cs_enable[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 3 $0\main_spimaster27_count[2:0] - attribute \src "ls180.v:4289.1-4337.4" - wire width 3 $0\main_spimaster27_count_spimaster0_next_value[2:0] - attribute \src "ls180.v:4289.1-4337.4" - wire $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] - attribute \src "ls180.v:4289.1-4337.4" - wire $0\main_spimaster28_mosi_latch[0:0] - attribute \src "ls180.v:4289.1-4337.4" - wire $0\main_spimaster29_miso_latch[0:0] - attribute \src "ls180.v:4289.1-4337.4" - wire $0\main_spimaster2_done[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 16 $0\main_spimaster30_clk_divider[15:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 8 $0\main_spimaster33_mosi_data[7:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 3 $0\main_spimaster34_mosi_sel[2:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 8 $0\main_spimaster35_miso_data[7:0] - attribute \src "ls180.v:4289.1-4337.4" - wire $0\main_spimaster3_irq[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 8 $0\main_spimaster5_miso[7:0] - attribute \src "ls180.v:1019.12-1019.47" - wire width 16 $0\main_spimaster8_clk_divider[15:0] - attribute \src "ls180.v:6362.1-6367.4" - wire $0\main_spimaster9_start[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 16 $0\main_spisdcard_clk_divider1[15:0] - attribute \src "ls180.v:4348.1-4396.4" - wire $0\main_spisdcard_clk_enable[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_spisdcard_control_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 16 $0\main_spisdcard_control_storage[15:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 3 $0\main_spisdcard_count[2:0] - attribute \src "ls180.v:4348.1-4396.4" - wire width 3 $0\main_spisdcard_count_spimaster1_next_value[2:0] - attribute \src "ls180.v:4348.1-4396.4" - wire $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] - attribute \src "ls180.v:4348.1-4396.4" - wire $0\main_spisdcard_cs_enable[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_spisdcard_cs_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_spisdcard_cs_storage[0:0] - attribute \src "ls180.v:4348.1-4396.4" - wire $0\main_spisdcard_done0[0:0] - attribute \src "ls180.v:4348.1-4396.4" - wire $0\main_spisdcard_irq[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_spisdcard_loopback_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_spisdcard_loopback_storage[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 8 $0\main_spisdcard_miso[7:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 8 $0\main_spisdcard_miso_data[7:0] - attribute \src "ls180.v:4348.1-4396.4" - wire $0\main_spisdcard_miso_latch[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 8 $0\main_spisdcard_mosi_data[7:0] - attribute \src "ls180.v:4348.1-4396.4" - wire $0\main_spisdcard_mosi_latch[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_spisdcard_mosi_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 3 $0\main_spisdcard_mosi_sel[2:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 8 $0\main_spisdcard_mosi_storage[7:0] - attribute \src "ls180.v:6408.1-6413.4" - wire $0\main_spisdcard_start1[0:0] - attribute \src "ls180.v:4196.1-4200.4" - wire width 2 $0\main_uart_eventmanager_pending_w[1:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_uart_eventmanager_re[0:0] - attribute \src "ls180.v:4185.1-4189.4" - wire width 2 $0\main_uart_eventmanager_status_w[1:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 2 $0\main_uart_eventmanager_storage[1:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 32 $0\main_uart_phy_phase_accumulator_rx[31:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 32 $0\main_uart_phy_phase_accumulator_tx[31:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_uart_phy_re[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 4 $0\main_uart_phy_rx_bitcount[3:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_uart_phy_rx_busy[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_uart_phy_rx_r[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 8 $0\main_uart_phy_rx_reg[7:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_uart_phy_sink_ready[0:0] - attribute \src "ls180.v:868.5-868.38" - wire $0\main_uart_phy_source_first[0:0] - attribute \src "ls180.v:869.5-869.37" - wire $0\main_uart_phy_source_last[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 8 $0\main_uart_phy_source_payload_data[7:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_uart_phy_source_valid[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 32 $0\main_uart_phy_storage[31:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 4 $0\main_uart_phy_tx_bitcount[3:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_uart_phy_tx_busy[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 8 $0\main_uart_phy_tx_reg[7:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_uart_phy_uart_clk_rxen[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_uart_phy_uart_clk_txen[0:0] - attribute \src "ls180.v:995.5-995.27" - wire $0\main_uart_reset[0:0] - attribute \src "ls180.v:4190.1-4195.4" - wire $0\main_uart_rx_clear[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 4 $0\main_uart_rx_fifo_consume[3:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 5 $0\main_uart_rx_fifo_level0[4:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 4 $0\main_uart_rx_fifo_produce[3:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_uart_rx_fifo_readable[0:0] - attribute \src "ls180.v:977.5-977.37" - wire $0\main_uart_rx_fifo_replace[0:0] - attribute \src "ls180.v:4248.1-4255.4" - wire width 4 $0\main_uart_rx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_uart_rx_old_trigger[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_uart_rx_pending[0:0] - attribute \src "ls180.v:4179.1-4184.4" - wire $0\main_uart_tx_clear[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 4 $0\main_uart_tx_fifo_consume[3:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 5 $0\main_uart_tx_fifo_level0[4:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 4 $0\main_uart_tx_fifo_produce[3:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_uart_tx_fifo_readable[0:0] - attribute \src "ls180.v:940.5-940.37" - wire $0\main_uart_tx_fifo_replace[0:0] - attribute \src "ls180.v:923.5-923.40" - wire $0\main_uart_tx_fifo_sink_first[0:0] - attribute \src "ls180.v:924.5-924.39" - wire $0\main_uart_tx_fifo_sink_last[0:0] - attribute \src "ls180.v:4218.1-4225.4" - wire width 4 $0\main_uart_tx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_uart_tx_old_trigger[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_uart_tx_pending[0:0] - attribute \src "ls180.v:4088.1-4134.4" - wire $0\main_wb_sdram_ack[0:0] - attribute \src "ls180.v:2937.1-2983.4" - wire width 30 $0\main_wb_sdram_adr[29:0] - attribute \src "ls180.v:2937.1-2983.4" - wire $0\main_wb_sdram_cyc[0:0] - attribute \src "ls180.v:2925.1-2935.4" - wire width 32 $0\main_wb_sdram_dat_w[31:0] - attribute \src "ls180.v:2937.1-2983.4" - wire width 4 $0\main_wb_sdram_sel[3:0] - attribute \src "ls180.v:2937.1-2983.4" - wire $0\main_wb_sdram_stb[0:0] - attribute \src "ls180.v:2937.1-2983.4" - wire $0\main_wb_sdram_we[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\main_wdata_consumed[0:0] - attribute \src "ls180.v:10144.1-10162.4" + attribute \src "ls180.v:5491.1-5509.4" + wire width 6 $0$memwr$\mem$ls180.v:5493$1_ADDR[5:0]$1460 + attribute \src "ls180.v:5491.1-5509.4" + wire width 64 $0$memwr$\mem$ls180.v:5493$1_DATA[63:0]$1461 + attribute \src "ls180.v:5491.1-5509.4" + wire width 64 $0$memwr$\mem$ls180.v:5493$1_EN[63:0]$1462 + attribute \src "ls180.v:5491.1-5509.4" + wire width 6 $0$memwr$\mem$ls180.v:5495$2_ADDR[5:0]$1463 + attribute \src "ls180.v:5491.1-5509.4" + wire width 64 $0$memwr$\mem$ls180.v:5495$2_DATA[63:0]$1464 + attribute \src "ls180.v:5491.1-5509.4" + wire width 64 $0$memwr$\mem$ls180.v:5495$2_EN[63:0]$1465 + attribute \src "ls180.v:5491.1-5509.4" + wire width 6 $0$memwr$\mem$ls180.v:5497$3_ADDR[5:0]$1466 + attribute \src "ls180.v:5491.1-5509.4" + wire width 64 $0$memwr$\mem$ls180.v:5497$3_DATA[63:0]$1467 + attribute \src "ls180.v:5491.1-5509.4" + wire width 64 $0$memwr$\mem$ls180.v:5497$3_EN[63:0]$1468 + attribute \src "ls180.v:5491.1-5509.4" + wire width 6 $0$memwr$\mem$ls180.v:5499$4_ADDR[5:0]$1469 + attribute \src "ls180.v:5491.1-5509.4" + wire width 64 $0$memwr$\mem$ls180.v:5499$4_DATA[63:0]$1470 + attribute \src "ls180.v:5491.1-5509.4" + wire width 64 $0$memwr$\mem$ls180.v:5499$4_EN[63:0]$1471 + attribute \src "ls180.v:5491.1-5509.4" + wire width 6 $0$memwr$\mem$ls180.v:5501$5_ADDR[5:0]$1472 + attribute \src "ls180.v:5491.1-5509.4" + wire width 64 $0$memwr$\mem$ls180.v:5501$5_DATA[63:0]$1473 + attribute \src "ls180.v:5491.1-5509.4" + wire width 64 $0$memwr$\mem$ls180.v:5501$5_EN[63:0]$1474 + attribute \src "ls180.v:5491.1-5509.4" + wire width 6 $0$memwr$\mem$ls180.v:5503$6_ADDR[5:0]$1475 + attribute \src "ls180.v:5491.1-5509.4" + wire width 64 $0$memwr$\mem$ls180.v:5503$6_DATA[63:0]$1476 + attribute \src "ls180.v:5491.1-5509.4" + wire width 64 $0$memwr$\mem$ls180.v:5503$6_EN[63:0]$1477 + attribute \src "ls180.v:5491.1-5509.4" + wire width 6 $0$memwr$\mem$ls180.v:5505$7_ADDR[5:0]$1478 + attribute \src "ls180.v:5491.1-5509.4" + wire width 64 $0$memwr$\mem$ls180.v:5505$7_DATA[63:0]$1479 + attribute \src "ls180.v:5491.1-5509.4" + wire width 64 $0$memwr$\mem$ls180.v:5505$7_EN[63:0]$1480 + attribute \src "ls180.v:5491.1-5509.4" + wire width 6 $0$memwr$\mem$ls180.v:5507$8_ADDR[5:0]$1481 + attribute \src "ls180.v:5491.1-5509.4" + wire width 64 $0$memwr$\mem$ls180.v:5507$8_DATA[63:0]$1482 + attribute \src "ls180.v:5491.1-5509.4" + wire width 64 $0$memwr$\mem$ls180.v:5507$8_EN[63:0]$1483 + attribute \src "ls180.v:5519.1-5537.4" + wire width 4 $0$memwr$\mem_1$ls180.v:5521$9_ADDR[3:0]$1510 + attribute \src "ls180.v:5519.1-5537.4" + wire width 64 $0$memwr$\mem_1$ls180.v:5521$9_DATA[63:0]$1511 + attribute \src "ls180.v:5519.1-5537.4" + wire width 64 $0$memwr$\mem_1$ls180.v:5521$9_EN[63:0]$1512 + attribute \src "ls180.v:5519.1-5537.4" + wire width 4 $0$memwr$\mem_1$ls180.v:5523$10_ADDR[3:0]$1513 + attribute \src "ls180.v:5519.1-5537.4" + wire width 64 $0$memwr$\mem_1$ls180.v:5523$10_DATA[63:0]$1514 + attribute \src "ls180.v:5519.1-5537.4" + wire width 64 $0$memwr$\mem_1$ls180.v:5523$10_EN[63:0]$1515 + attribute \src "ls180.v:5519.1-5537.4" + wire width 4 $0$memwr$\mem_1$ls180.v:5525$11_ADDR[3:0]$1516 + attribute \src "ls180.v:5519.1-5537.4" + wire width 64 $0$memwr$\mem_1$ls180.v:5525$11_DATA[63:0]$1517 + attribute \src "ls180.v:5519.1-5537.4" + wire width 64 $0$memwr$\mem_1$ls180.v:5525$11_EN[63:0]$1518 + attribute \src "ls180.v:5519.1-5537.4" + wire width 4 $0$memwr$\mem_1$ls180.v:5527$12_ADDR[3:0]$1519 + attribute \src "ls180.v:5519.1-5537.4" + wire width 64 $0$memwr$\mem_1$ls180.v:5527$12_DATA[63:0]$1520 + attribute \src "ls180.v:5519.1-5537.4" + wire width 64 $0$memwr$\mem_1$ls180.v:5527$12_EN[63:0]$1521 + attribute \src "ls180.v:5519.1-5537.4" + wire width 4 $0$memwr$\mem_1$ls180.v:5529$13_ADDR[3:0]$1522 + attribute \src "ls180.v:5519.1-5537.4" + wire width 64 $0$memwr$\mem_1$ls180.v:5529$13_DATA[63:0]$1523 + attribute \src "ls180.v:5519.1-5537.4" + wire width 64 $0$memwr$\mem_1$ls180.v:5529$13_EN[63:0]$1524 + attribute \src "ls180.v:5519.1-5537.4" + wire width 4 $0$memwr$\mem_1$ls180.v:5531$14_ADDR[3:0]$1525 + attribute \src "ls180.v:5519.1-5537.4" + wire width 64 $0$memwr$\mem_1$ls180.v:5531$14_DATA[63:0]$1526 + attribute \src "ls180.v:5519.1-5537.4" + wire width 64 $0$memwr$\mem_1$ls180.v:5531$14_EN[63:0]$1527 + attribute \src "ls180.v:5519.1-5537.4" + wire width 4 $0$memwr$\mem_1$ls180.v:5533$15_ADDR[3:0]$1528 + attribute \src "ls180.v:5519.1-5537.4" + wire width 64 $0$memwr$\mem_1$ls180.v:5533$15_DATA[63:0]$1529 + attribute \src "ls180.v:5519.1-5537.4" + wire width 64 $0$memwr$\mem_1$ls180.v:5533$15_EN[63:0]$1530 + attribute \src "ls180.v:5519.1-5537.4" + wire width 4 $0$memwr$\mem_1$ls180.v:5535$16_ADDR[3:0]$1531 + attribute \src "ls180.v:5519.1-5537.4" + wire width 64 $0$memwr$\mem_1$ls180.v:5535$16_DATA[63:0]$1532 + attribute \src "ls180.v:5519.1-5537.4" + wire width 64 $0$memwr$\mem_1$ls180.v:5535$16_EN[63:0]$1533 + attribute \src "ls180.v:5547.1-5551.4" + wire width 3 $0$memwr$\storage$ls180.v:5549$17_ADDR[2:0]$1560 + attribute \src "ls180.v:5547.1-5551.4" + wire width 25 $0$memwr$\storage$ls180.v:5549$17_DATA[24:0]$1561 + attribute \src "ls180.v:5547.1-5551.4" + wire width 25 $0$memwr$\storage$ls180.v:5549$17_EN[24:0]$1562 + attribute \src "ls180.v:5561.1-5565.4" + wire width 3 $0$memwr$\storage_1$ls180.v:5563$18_ADDR[2:0]$1570 + attribute \src "ls180.v:5561.1-5565.4" + wire width 25 $0$memwr$\storage_1$ls180.v:5563$18_DATA[24:0]$1571 + attribute \src "ls180.v:5561.1-5565.4" + wire width 25 $0$memwr$\storage_1$ls180.v:5563$18_EN[24:0]$1572 + attribute \src "ls180.v:5575.1-5579.4" + wire width 3 $0$memwr$\storage_2$ls180.v:5577$19_ADDR[2:0]$1580 + attribute \src "ls180.v:5575.1-5579.4" + wire width 25 $0$memwr$\storage_2$ls180.v:5577$19_DATA[24:0]$1581 + attribute \src "ls180.v:5575.1-5579.4" + wire width 25 $0$memwr$\storage_2$ls180.v:5577$19_EN[24:0]$1582 + attribute \src "ls180.v:5589.1-5593.4" + wire width 3 $0$memwr$\storage_3$ls180.v:5591$20_ADDR[2:0]$1590 + attribute \src "ls180.v:5589.1-5593.4" + wire width 25 $0$memwr$\storage_3$ls180.v:5591$20_DATA[24:0]$1591 + attribute \src "ls180.v:5589.1-5593.4" + wire width 25 $0$memwr$\storage_3$ls180.v:5591$20_EN[24:0]$1592 + attribute \src "ls180.v:5604.1-5608.4" + wire width 4 $0$memwr$\storage_4$ls180.v:5606$21_ADDR[3:0]$1600 + attribute \src "ls180.v:5604.1-5608.4" + wire width 10 $0$memwr$\storage_4$ls180.v:5606$21_DATA[9:0]$1601 + attribute \src "ls180.v:5604.1-5608.4" + wire width 10 $0$memwr$\storage_4$ls180.v:5606$21_EN[9:0]$1602 + attribute \src "ls180.v:5621.1-5625.4" + wire width 4 $0$memwr$\storage_5$ls180.v:5623$22_ADDR[3:0]$1610 + attribute \src "ls180.v:5621.1-5625.4" + wire width 10 $0$memwr$\storage_5$ls180.v:5623$22_DATA[9:0]$1611 + attribute \src "ls180.v:5621.1-5625.4" + wire width 10 $0$memwr$\storage_5$ls180.v:5623$22_EN[9:0]$1612 + attribute \src "ls180.v:3951.1-3967.4" + wire width 2 $0\array_muxed0[1:0] + attribute \src "ls180.v:3968.1-3984.4" + wire width 13 $0\array_muxed1[12:0] + attribute \src "ls180.v:3985.1-4001.4" + wire $0\array_muxed2[0:0] + attribute \src "ls180.v:4002.1-4018.4" + wire $0\array_muxed3[0:0] + attribute \src "ls180.v:4019.1-4035.4" + wire $0\array_muxed4[0:0] + attribute \src "ls180.v:4036.1-4052.4" + wire $0\array_muxed5[0:0] + attribute \src "ls180.v:4053.1-4069.4" + wire $0\array_muxed6[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\cmd_consumed[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\converter0_counter[0:0] + attribute \src "ls180.v:1526.1-1572.4" + wire $0\converter0_counter_subfragments_converter0_next_value[0:0] + attribute \src "ls180.v:1526.1-1572.4" + wire $0\converter0_counter_subfragments_converter0_next_value_ce[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 64 $0\converter0_dat_r[63:0] + attribute \src "ls180.v:1526.1-1572.4" + wire $0\converter0_skip[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\converter1_counter[0:0] + attribute \src "ls180.v:1586.1-1632.4" + wire $0\converter1_counter_subfragments_converter1_next_value[0:0] + attribute \src "ls180.v:1586.1-1632.4" + wire $0\converter1_counter_subfragments_converter1_next_value_ce[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 64 $0\converter1_dat_r[63:0] + attribute \src "ls180.v:1586.1-1632.4" + wire $0\converter1_skip[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\converter_counter[0:0] + attribute \src "ls180.v:2797.1-2843.4" + wire $0\converter_counter_subfragments_next_value[0:0] + attribute \src "ls180.v:2797.1-2843.4" + wire $0\converter_counter_subfragments_next_value_ce[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 32 $0\converter_dat_r[31:0] + attribute \src "ls180.v:2797.1-2843.4" + wire $0\converter_skip[0:0] + attribute \src "ls180.v:4180.1-4285.4" + wire width 16 $0\dfi_p0_rddata[15:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\dfi_p0_rddata_valid[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 30 $0\dummy[29:0] + attribute \src "ls180.v:2905.1-2909.4" + wire width 2 $0\eventmanager_pending_w[1:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\eventmanager_re[0:0] + attribute \src "ls180.v:2894.1-2898.4" + wire width 2 $0\eventmanager_status_w[1:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 2 $0\eventmanager_storage[1:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\gpio0_oe_re[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 8 $0\gpio0_oe_storage[7:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\gpio0_out_re[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 8 $0\gpio0_out_storage[7:0] + attribute \src "ls180.v:2973.1-2983.4" + wire width 8 $0\gpio0_pads_gpio0i[7:0] + attribute \src "ls180.v:4180.1-4285.4" + wire width 8 $0\gpio0_pads_gpio0o[7:0] + attribute \src "ls180.v:4180.1-4285.4" + wire width 8 $0\gpio0_pads_gpio0oe[7:0] + attribute \src "ls180.v:4180.1-4285.4" + wire width 8 $0\gpio0_status[7:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\gpio1_oe_re[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 8 $0\gpio1_oe_storage[7:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\gpio1_out_re[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 8 $0\gpio1_out_storage[7:0] + attribute \src "ls180.v:2984.1-2994.4" + wire width 8 $0\gpio1_pads_gpio1i[7:0] + attribute \src "ls180.v:4180.1-4285.4" + wire width 8 $0\gpio1_pads_gpio1o[7:0] + attribute \src "ls180.v:4180.1-4285.4" + wire width 8 $0\gpio1_pads_gpio1oe[7:0] + attribute \src "ls180.v:4180.1-4285.4" + wire width 8 $0\gpio1_status[7:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\i2c_re[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 3 $0\i2c_storage[2:0] + attribute \src "ls180.v:4176.1-4178.4" + wire $0\int_rst[0:0] + attribute \src "ls180.v:1526.1-1572.4" + wire $0\interface0_converted_interface_ack[0:0] + attribute \src "ls180.v:208.5-208.46" + wire $0\interface0_converted_interface_err[0:0] + attribute \src "ls180.v:1586.1-1632.4" + wire $0\interface1_converted_interface_ack[0:0] + attribute \src "ls180.v:223.5-223.46" + wire $0\interface1_converted_interface_err[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 32 $0\libresocsim_bus_errors[31:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 20 $0\libresocsim_count[19:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\libresocsim_en_re[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\libresocsim_en_storage[0:0] + attribute \src "ls180.v:3151.1-3162.4" + wire $0\libresocsim_error[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\libresocsim_eventmanager_re[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\libresocsim_eventmanager_storage[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 2 $0\libresocsim_grant[1:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 8 $0\libresocsim_interface0_bank_bus_dat_r[7:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 8 $0\libresocsim_interface1_bank_bus_dat_r[7:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 8 $0\libresocsim_interface2_bank_bus_dat_r[7:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 8 $0\libresocsim_interface3_bank_bus_dat_r[7:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 8 $0\libresocsim_interface4_bank_bus_dat_r[7:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 8 $0\libresocsim_interface5_bank_bus_dat_r[7:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 8 $0\libresocsim_interface6_bank_bus_dat_r[7:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 8 $0\libresocsim_interface7_bank_bus_dat_r[7:0] + attribute \src "ls180.v:2995.1-3013.4" + wire width 16 $0\libresocsim_libresoc_constraintmanager_obj_gpio_o[15:0] + attribute \src "ls180.v:3014.1-3032.4" + wire width 16 $0\libresocsim_libresoc_constraintmanager_obj_gpio_oe[15:0] + attribute \src "ls180.v:4180.1-4285.4" + wire width 13 $0\libresocsim_libresoc_constraintmanager_obj_sdram_a[12:0] + attribute \src "ls180.v:4180.1-4285.4" + wire width 2 $0\libresocsim_libresoc_constraintmanager_obj_sdram_ba[1:0] + attribute \src "ls180.v:4180.1-4285.4" + wire $0\libresocsim_libresoc_constraintmanager_obj_sdram_cas_n[0:0] + attribute \src "ls180.v:4180.1-4285.4" + wire $0\libresocsim_libresoc_constraintmanager_obj_sdram_cke[0:0] + attribute \src "ls180.v:4180.1-4285.4" + wire $0\libresocsim_libresoc_constraintmanager_obj_sdram_cs_n[0:0] + attribute \src "ls180.v:4180.1-4285.4" + wire width 2 $0\libresocsim_libresoc_constraintmanager_obj_sdram_dm[1:0] + attribute \src "ls180.v:4180.1-4285.4" + wire width 16 $0\libresocsim_libresoc_constraintmanager_obj_sdram_dq_o[15:0] + attribute \src "ls180.v:4180.1-4285.4" + wire $0\libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe[0:0] + attribute \src "ls180.v:4180.1-4285.4" + wire $0\libresocsim_libresoc_constraintmanager_obj_sdram_ras_n[0:0] + attribute \src "ls180.v:4180.1-4285.4" + wire $0\libresocsim_libresoc_constraintmanager_obj_sdram_we_n[0:0] + attribute \src "ls180.v:118.5-118.68" + wire $0\libresocsim_libresoc_constraintmanager_obj_spimaster_clk[0:0] + attribute \src "ls180.v:120.5-120.69" + wire $0\libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n[0:0] + attribute \src "ls180.v:119.5-119.69" + wire $0\libresocsim_libresoc_constraintmanager_obj_spimaster_mosi[0:0] + attribute \src "ls180.v:123.5-123.62" + wire $0\libresocsim_libresoc_constraintmanager_obj_uart_rx[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\libresocsim_libresoc_constraintmanager_obj_uart_tx[0:0] + attribute \src "ls180.v:63.11-63.47" + wire width 2 $0\libresocsim_libresoc_dbus_bte[1:0] + attribute \src "ls180.v:62.11-62.47" + wire width 3 $0\libresocsim_libresoc_dbus_cti[2:0] + attribute \src "ls180.v:74.11-74.47" + wire width 2 $0\libresocsim_libresoc_ibus_bte[1:0] + attribute \src "ls180.v:73.11-73.47" + wire width 3 $0\libresocsim_libresoc_ibus_cti[2:0] + attribute \src "ls180.v:1507.1-1512.4" + wire width 16 $0\libresocsim_libresoc_interrupt[15:0] + attribute \src "ls180.v:103.11-103.50" + wire width 2 $0\libresocsim_libresoc_jtag_wb_bte[1:0] + attribute \src "ls180.v:102.11-102.50" + wire width 3 $0\libresocsim_libresoc_jtag_wb_cti[2:0] + attribute \src "ls180.v:1526.1-1572.4" + wire width 30 $0\libresocsim_libresoc_xics_icp_adr[29:0] + attribute \src "ls180.v:1526.1-1572.4" + wire $0\libresocsim_libresoc_xics_icp_cyc[0:0] + attribute \src "ls180.v:1514.1-1524.4" + wire width 32 $0\libresocsim_libresoc_xics_icp_dat_w[31:0] + attribute \src "ls180.v:1526.1-1572.4" + wire width 4 $0\libresocsim_libresoc_xics_icp_sel[3:0] + attribute \src "ls180.v:1526.1-1572.4" + wire $0\libresocsim_libresoc_xics_icp_stb[0:0] + attribute \src "ls180.v:1526.1-1572.4" + wire $0\libresocsim_libresoc_xics_icp_we[0:0] + attribute \src "ls180.v:1586.1-1632.4" + wire width 30 $0\libresocsim_libresoc_xics_ics_adr[29:0] + attribute \src "ls180.v:1586.1-1632.4" + wire $0\libresocsim_libresoc_xics_ics_cyc[0:0] + attribute \src "ls180.v:1574.1-1584.4" + wire width 32 $0\libresocsim_libresoc_xics_ics_dat_w[31:0] + attribute \src "ls180.v:1586.1-1632.4" + wire width 4 $0\libresocsim_libresoc_xics_ics_sel[3:0] + attribute \src "ls180.v:1586.1-1632.4" + wire $0\libresocsim_libresoc_xics_ics_stb[0:0] + attribute \src "ls180.v:1586.1-1632.4" + wire $0\libresocsim_libresoc_xics_ics_we[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 14 $0\libresocsim_libresocsim_adr[13:0] + attribute \src "ls180.v:3037.1-3073.4" + wire width 14 $0\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0] + attribute \src "ls180.v:3037.1-3073.4" + wire $0\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0] + attribute \src "ls180.v:1069.5-1069.59" + wire $0\libresocsim_libresocsim_converted_interface_ack[0:0] + attribute \src "ls180.v:1065.12-1065.69" + wire width 64 $0\libresocsim_libresocsim_converted_interface_dat_r[63:0] + attribute \src "ls180.v:1073.5-1073.59" + wire $0\libresocsim_libresocsim_converted_interface_err[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 8 $0\libresocsim_libresocsim_dat_w[7:0] + attribute \src "ls180.v:3037.1-3073.4" + wire width 8 $0\libresocsim_libresocsim_dat_w_libresocsim_next_value0[7:0] + attribute \src "ls180.v:3037.1-3073.4" + wire $0\libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\libresocsim_libresocsim_we[0:0] + attribute \src "ls180.v:3037.1-3073.4" + wire $0\libresocsim_libresocsim_we_libresocsim_next_value2[0:0] + attribute \src "ls180.v:3037.1-3073.4" + wire $0\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0] + attribute \src "ls180.v:3037.1-3073.4" + wire $0\libresocsim_libresocsim_wishbone_ack[0:0] + attribute \src "ls180.v:1055.12-1055.56" + wire width 30 $0\libresocsim_libresocsim_wishbone_adr[29:0] + attribute \src "ls180.v:1059.5-1059.48" + wire $0\libresocsim_libresocsim_wishbone_cyc[0:0] + attribute \src "ls180.v:3037.1-3073.4" + wire width 32 $0\libresocsim_libresocsim_wishbone_dat_r[31:0] + attribute \src "ls180.v:1056.12-1056.58" + wire width 32 $0\libresocsim_libresocsim_wishbone_dat_w[31:0] + attribute \src "ls180.v:1058.11-1058.54" + wire width 4 $0\libresocsim_libresocsim_wishbone_sel[3:0] + attribute \src "ls180.v:1060.5-1060.48" + wire $0\libresocsim_libresocsim_wishbone_stb[0:0] + attribute \src "ls180.v:1062.5-1062.47" + wire $0\libresocsim_libresocsim_wishbone_we[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\libresocsim_load_re[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 32 $0\libresocsim_load_storage[31:0] + attribute \src "ls180.v:3037.1-3073.4" + wire width 2 $0\libresocsim_next_state[1:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\libresocsim_ram_bus_ack[0:0] + attribute \src "ls180.v:151.5-151.35" + wire $0\libresocsim_ram_bus_err[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\libresocsim_reload_re[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 32 $0\libresocsim_reload_storage[31:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\libresocsim_reset_re[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\libresocsim_reset_storage[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\libresocsim_scratch_re[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 32 $0\libresocsim_scratch_storage[31:0] + attribute \src "ls180.v:3151.1-3162.4" + wire $0\libresocsim_shared_ack[0:0] + attribute \src "ls180.v:3151.1-3162.4" + wire width 32 $0\libresocsim_shared_dat_r[31:0] + attribute \src "ls180.v:3092.1-3100.4" + wire width 6 $0\libresocsim_slave_sel[5:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 6 $0\libresocsim_slave_sel_r[5:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 2 $0\libresocsim_state[1:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\libresocsim_update_value_re[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\libresocsim_update_value_storage[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 32 $0\libresocsim_value[31:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 32 $0\libresocsim_value_status[31:0] + attribute \src "ls180.v:1695.1-1705.4" + wire width 8 $0\libresocsim_we[7:0] + attribute \src "ls180.v:1711.1-1716.4" + wire $0\libresocsim_zero_clear[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\libresocsim_zero_old_trigger[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\libresocsim_zero_pending[0:0] + attribute \src "ls180.v:2797.1-2843.4" + wire width 30 $0\litedram_wb_adr[29:0] + attribute \src "ls180.v:2797.1-2843.4" + wire $0\litedram_wb_cyc[0:0] + attribute \src "ls180.v:2785.1-2795.4" + wire width 16 $0\litedram_wb_dat_w[15:0] + attribute \src "ls180.v:2797.1-2843.4" + wire width 2 $0\litedram_wb_sel[1:0] + attribute \src "ls180.v:2797.1-2843.4" + wire $0\litedram_wb_stb[0:0] + attribute \src "ls180.v:2797.1-2843.4" + wire $0\litedram_wb_we[0:0] + attribute \src "ls180.v:5491.1-5509.4" wire width 6 $0\memadr[5:0] - attribute \src "ls180.v:10172.1-10190.4" + attribute \src "ls180.v:5519.1-5537.4" wire width 4 $0\memadr_1[3:0] - attribute \src "ls180.v:10200.1-10204.4" + attribute \src "ls180.v:5547.1-5551.4" wire width 25 $0\memdat[24:0] - attribute \src "ls180.v:10214.1-10218.4" + attribute \src "ls180.v:5561.1-5565.4" wire width 25 $0\memdat_1[24:0] - attribute \src "ls180.v:10228.1-10232.4" + attribute \src "ls180.v:5575.1-5579.4" wire width 25 $0\memdat_2[24:0] - attribute \src "ls180.v:10242.1-10246.4" + attribute \src "ls180.v:5589.1-5593.4" wire width 25 $0\memdat_3[24:0] - attribute \src "ls180.v:10257.1-10261.4" + attribute \src "ls180.v:5604.1-5608.4" wire width 10 $0\memdat_4[9:0] - attribute \src "ls180.v:10263.1-10266.4" + attribute \src "ls180.v:5610.1-5613.4" wire width 10 $0\memdat_5[9:0] - attribute \src "ls180.v:10274.1-10278.4" + attribute \src "ls180.v:5621.1-5625.4" wire width 10 $0\memdat_6[9:0] - attribute \src "ls180.v:10280.1-10283.4" + attribute \src "ls180.v:5627.1-5630.4" wire width 10 $0\memdat_7[9:0] - attribute \src "ls180.v:10290.1-10294.4" - wire width 10 $0\memdat_8[9:0] - attribute \src "ls180.v:10304.1-10308.4" - wire width 10 $0\memdat_9[9:0] - attribute \src "ls180.v:7511.1-10140.4" - wire width 2 $0\pwm[1:0] - attribute \src "ls180.v:7439.1-7509.4" - wire $0\sdcard_clk[0:0] - attribute \src "ls180.v:7439.1-7509.4" - wire $0\sdcard_cmd_o[0:0] - attribute \src "ls180.v:7439.1-7509.4" - wire $0\sdcard_cmd_oe[0:0] - attribute \src "ls180.v:7439.1-7509.4" - wire width 4 $0\sdcard_data_o[3:0] - attribute \src "ls180.v:7439.1-7509.4" - wire $0\sdcard_data_oe[0:0] - attribute \src "ls180.v:7439.1-7509.4" - wire width 13 $0\sdram_a[12:0] - attribute \src "ls180.v:7439.1-7509.4" - wire width 2 $0\sdram_ba[1:0] - attribute \src "ls180.v:7439.1-7509.4" - wire $0\sdram_cas_n[0:0] - attribute \src "ls180.v:7439.1-7509.4" - wire $0\sdram_cke[0:0] - attribute \src "ls180.v:7439.1-7509.4" + attribute \src "ls180.v:4287.1-5487.4" + wire $0\ram_bus_ram_bus_ack[0:0] + attribute \src "ls180.v:193.5-193.31" + wire $0\ram_bus_ram_bus_err[0:0] + attribute \src "ls180.v:1720.1-1730.4" + wire width 8 $0\ram_we[7:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 3 $0\rddata_en[2:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\regs0[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\regs1[0:0] + attribute \src "ls180.v:973.5-973.17" + wire $0\reset[0:0] + attribute \src "ls180.v:3437.1-3453.4" + wire $0\rhs_array_muxed0[0:0] + attribute \src "ls180.v:3658.1-3674.4" + wire $0\rhs_array_muxed10[0:0] + attribute \src "ls180.v:3675.1-3691.4" + wire $0\rhs_array_muxed11[0:0] + attribute \src "ls180.v:3743.1-3750.4" + wire width 22 $0\rhs_array_muxed12[21:0] + attribute \src "ls180.v:3751.1-3758.4" + wire $0\rhs_array_muxed13[0:0] + attribute \src "ls180.v:3759.1-3766.4" + wire $0\rhs_array_muxed14[0:0] + attribute \src "ls180.v:3767.1-3774.4" + wire width 22 $0\rhs_array_muxed15[21:0] + attribute \src "ls180.v:3775.1-3782.4" + wire $0\rhs_array_muxed16[0:0] + attribute \src "ls180.v:3783.1-3790.4" + wire $0\rhs_array_muxed17[0:0] + attribute \src "ls180.v:3791.1-3798.4" + wire width 22 $0\rhs_array_muxed18[21:0] + attribute \src "ls180.v:3799.1-3806.4" + wire $0\rhs_array_muxed19[0:0] + attribute \src "ls180.v:3454.1-3470.4" + wire width 13 $0\rhs_array_muxed1[12:0] + attribute \src "ls180.v:3807.1-3814.4" + wire $0\rhs_array_muxed20[0:0] + attribute \src "ls180.v:3815.1-3822.4" + wire width 22 $0\rhs_array_muxed21[21:0] + attribute \src "ls180.v:3823.1-3830.4" + wire $0\rhs_array_muxed22[0:0] + attribute \src "ls180.v:3831.1-3838.4" + wire $0\rhs_array_muxed23[0:0] + attribute \src "ls180.v:3839.1-3852.4" + wire width 29 $0\rhs_array_muxed24[28:0] + attribute \src "ls180.v:3853.1-3866.4" + wire width 64 $0\rhs_array_muxed25[63:0] + attribute \src "ls180.v:3867.1-3880.4" + wire width 8 $0\rhs_array_muxed26[7:0] + attribute \src "ls180.v:3881.1-3894.4" + wire $0\rhs_array_muxed27[0:0] + attribute \src "ls180.v:3895.1-3908.4" + wire $0\rhs_array_muxed28[0:0] + attribute \src "ls180.v:3909.1-3922.4" + wire $0\rhs_array_muxed29[0:0] + attribute \src "ls180.v:3471.1-3487.4" + wire width 2 $0\rhs_array_muxed2[1:0] + attribute \src "ls180.v:3923.1-3936.4" + wire width 3 $0\rhs_array_muxed30[2:0] + attribute \src "ls180.v:3937.1-3950.4" + wire width 2 $0\rhs_array_muxed31[1:0] + attribute \src "ls180.v:3488.1-3504.4" + wire $0\rhs_array_muxed3[0:0] + attribute \src "ls180.v:3505.1-3521.4" + wire $0\rhs_array_muxed4[0:0] + attribute \src "ls180.v:3522.1-3538.4" + wire $0\rhs_array_muxed5[0:0] + attribute \src "ls180.v:3590.1-3606.4" + wire $0\rhs_array_muxed6[0:0] + attribute \src "ls180.v:3607.1-3623.4" + wire width 13 $0\rhs_array_muxed7[12:0] + attribute \src "ls180.v:3624.1-3640.4" + wire width 2 $0\rhs_array_muxed8[1:0] + attribute \src "ls180.v:3641.1-3657.4" + wire $0\rhs_array_muxed9[0:0] + attribute \src "ls180.v:2899.1-2904.4" + wire $0\rx_clear[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 4 $0\rx_fifo_consume[3:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 5 $0\rx_fifo_level0[4:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 4 $0\rx_fifo_produce[3:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\rx_fifo_readable[0:0] + attribute \src "ls180.v:955.5-955.27" + wire $0\rx_fifo_replace[0:0] + attribute \src "ls180.v:2957.1-2964.4" + wire width 4 $0\rx_fifo_wrport_adr[3:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\rx_old_trigger[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\rx_pending[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_address_re[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 13 $0\sdram_address_storage[12:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_baddress_re[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 2 $0\sdram_baddress_storage[1:0] + attribute \src "ls180.v:1942.1-1949.4" + wire $0\sdram_bankmachine0_auto_precharge[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 3 $0\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 4 $0\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 3 $0\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:428.5-428.59" + wire $0\sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] + attribute \src "ls180.v:411.5-411.62" + wire $0\sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "ls180.v:412.5-412.61" + wire $0\sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "ls180.v:1964.1-1971.4" + wire width 3 $0\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_bankmachine0_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_bankmachine0_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 22 $0\sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_bankmachine0_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:1931.1-1938.4" + wire width 13 $0\sdram_bankmachine0_cmd_payload_a[12:0] + attribute \src "ls180.v:1980.1-2073.4" + wire $0\sdram_bankmachine0_cmd_payload_cas[0:0] + attribute \src "ls180.v:1980.1-2073.4" + wire $0\sdram_bankmachine0_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:1980.1-2073.4" + wire $0\sdram_bankmachine0_cmd_payload_is_read[0:0] + attribute \src "ls180.v:1980.1-2073.4" + wire $0\sdram_bankmachine0_cmd_payload_is_write[0:0] + attribute \src "ls180.v:1980.1-2073.4" + wire $0\sdram_bankmachine0_cmd_payload_ras[0:0] + attribute \src "ls180.v:1980.1-2073.4" + wire $0\sdram_bankmachine0_cmd_payload_we[0:0] + attribute \src "ls180.v:2629.1-2637.4" + wire $0\sdram_bankmachine0_cmd_ready[0:0] + attribute \src "ls180.v:1980.1-2073.4" + wire $0\sdram_bankmachine0_cmd_valid[0:0] + attribute \src "ls180.v:1980.1-2073.4" + wire $0\sdram_bankmachine0_refresh_gnt[0:0] + attribute \src "ls180.v:1980.1-2073.4" + wire $0\sdram_bankmachine0_req_rdata_valid[0:0] + attribute \src "ls180.v:1980.1-2073.4" + wire $0\sdram_bankmachine0_req_wdata_ready[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 13 $0\sdram_bankmachine0_row[12:0] + attribute \src "ls180.v:1980.1-2073.4" + wire $0\sdram_bankmachine0_row_close[0:0] + attribute \src "ls180.v:1980.1-2073.4" + wire $0\sdram_bankmachine0_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:1980.1-2073.4" + wire $0\sdram_bankmachine0_row_open[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_bankmachine0_row_opened[0:0] + attribute \src "ls180.v:470.32-470.71" + wire $0\sdram_bankmachine0_trascon_ready[0:0] + attribute \src "ls180.v:468.32-468.70" + wire $0\sdram_bankmachine0_trccon_ready[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 3 $0\sdram_bankmachine0_twtpcon_count[2:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_bankmachine0_twtpcon_ready[0:0] + attribute \src "ls180.v:2099.1-2106.4" + wire $0\sdram_bankmachine1_auto_precharge[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 3 $0\sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 4 $0\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 3 $0\sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:510.5-510.59" + wire $0\sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] + attribute \src "ls180.v:493.5-493.62" + wire $0\sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "ls180.v:494.5-494.61" + wire $0\sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "ls180.v:2121.1-2128.4" + wire width 3 $0\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_bankmachine1_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_bankmachine1_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 22 $0\sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_bankmachine1_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:2088.1-2095.4" + wire width 13 $0\sdram_bankmachine1_cmd_payload_a[12:0] + attribute \src "ls180.v:2137.1-2230.4" + wire $0\sdram_bankmachine1_cmd_payload_cas[0:0] + attribute \src "ls180.v:2137.1-2230.4" + wire $0\sdram_bankmachine1_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:2137.1-2230.4" + wire $0\sdram_bankmachine1_cmd_payload_is_read[0:0] + attribute \src "ls180.v:2137.1-2230.4" + wire $0\sdram_bankmachine1_cmd_payload_is_write[0:0] + attribute \src "ls180.v:2137.1-2230.4" + wire $0\sdram_bankmachine1_cmd_payload_ras[0:0] + attribute \src "ls180.v:2137.1-2230.4" + wire $0\sdram_bankmachine1_cmd_payload_we[0:0] + attribute \src "ls180.v:2638.1-2646.4" + wire $0\sdram_bankmachine1_cmd_ready[0:0] + attribute \src "ls180.v:2137.1-2230.4" + wire $0\sdram_bankmachine1_cmd_valid[0:0] + attribute \src "ls180.v:2137.1-2230.4" + wire $0\sdram_bankmachine1_refresh_gnt[0:0] + attribute \src "ls180.v:2137.1-2230.4" + wire $0\sdram_bankmachine1_req_rdata_valid[0:0] + attribute \src "ls180.v:2137.1-2230.4" + wire $0\sdram_bankmachine1_req_wdata_ready[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 13 $0\sdram_bankmachine1_row[12:0] + attribute \src "ls180.v:2137.1-2230.4" + wire $0\sdram_bankmachine1_row_close[0:0] + attribute \src "ls180.v:2137.1-2230.4" + wire $0\sdram_bankmachine1_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:2137.1-2230.4" + wire $0\sdram_bankmachine1_row_open[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_bankmachine1_row_opened[0:0] + attribute \src "ls180.v:552.32-552.71" + wire $0\sdram_bankmachine1_trascon_ready[0:0] + attribute \src "ls180.v:550.32-550.70" + wire $0\sdram_bankmachine1_trccon_ready[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 3 $0\sdram_bankmachine1_twtpcon_count[2:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_bankmachine1_twtpcon_ready[0:0] + attribute \src "ls180.v:2256.1-2263.4" + wire $0\sdram_bankmachine2_auto_precharge[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 3 $0\sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 4 $0\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 3 $0\sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:592.5-592.59" + wire $0\sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] + attribute \src "ls180.v:575.5-575.62" + wire $0\sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "ls180.v:576.5-576.61" + wire $0\sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "ls180.v:2278.1-2285.4" + wire width 3 $0\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_bankmachine2_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_bankmachine2_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 22 $0\sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_bankmachine2_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:2245.1-2252.4" + wire width 13 $0\sdram_bankmachine2_cmd_payload_a[12:0] + attribute \src "ls180.v:2294.1-2387.4" + wire $0\sdram_bankmachine2_cmd_payload_cas[0:0] + attribute \src "ls180.v:2294.1-2387.4" + wire $0\sdram_bankmachine2_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:2294.1-2387.4" + wire $0\sdram_bankmachine2_cmd_payload_is_read[0:0] + attribute \src "ls180.v:2294.1-2387.4" + wire $0\sdram_bankmachine2_cmd_payload_is_write[0:0] + attribute \src "ls180.v:2294.1-2387.4" + wire $0\sdram_bankmachine2_cmd_payload_ras[0:0] + attribute \src "ls180.v:2294.1-2387.4" + wire $0\sdram_bankmachine2_cmd_payload_we[0:0] + attribute \src "ls180.v:2647.1-2655.4" + wire $0\sdram_bankmachine2_cmd_ready[0:0] + attribute \src "ls180.v:2294.1-2387.4" + wire $0\sdram_bankmachine2_cmd_valid[0:0] + attribute \src "ls180.v:2294.1-2387.4" + wire $0\sdram_bankmachine2_refresh_gnt[0:0] + attribute \src "ls180.v:2294.1-2387.4" + wire $0\sdram_bankmachine2_req_rdata_valid[0:0] + attribute \src "ls180.v:2294.1-2387.4" + wire $0\sdram_bankmachine2_req_wdata_ready[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 13 $0\sdram_bankmachine2_row[12:0] + attribute \src "ls180.v:2294.1-2387.4" + wire $0\sdram_bankmachine2_row_close[0:0] + attribute \src "ls180.v:2294.1-2387.4" + wire $0\sdram_bankmachine2_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:2294.1-2387.4" + wire $0\sdram_bankmachine2_row_open[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_bankmachine2_row_opened[0:0] + attribute \src "ls180.v:634.32-634.71" + wire $0\sdram_bankmachine2_trascon_ready[0:0] + attribute \src "ls180.v:632.32-632.70" + wire $0\sdram_bankmachine2_trccon_ready[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 3 $0\sdram_bankmachine2_twtpcon_count[2:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_bankmachine2_twtpcon_ready[0:0] + attribute \src "ls180.v:2413.1-2420.4" + wire $0\sdram_bankmachine3_auto_precharge[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 3 $0\sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 4 $0\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 3 $0\sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:674.5-674.59" + wire $0\sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] + attribute \src "ls180.v:657.5-657.62" + wire $0\sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "ls180.v:658.5-658.61" + wire $0\sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "ls180.v:2435.1-2442.4" + wire width 3 $0\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_bankmachine3_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_bankmachine3_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 22 $0\sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_bankmachine3_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:2402.1-2409.4" + wire width 13 $0\sdram_bankmachine3_cmd_payload_a[12:0] + attribute \src "ls180.v:2451.1-2544.4" + wire $0\sdram_bankmachine3_cmd_payload_cas[0:0] + attribute \src "ls180.v:2451.1-2544.4" + wire $0\sdram_bankmachine3_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:2451.1-2544.4" + wire $0\sdram_bankmachine3_cmd_payload_is_read[0:0] + attribute \src "ls180.v:2451.1-2544.4" + wire $0\sdram_bankmachine3_cmd_payload_is_write[0:0] + attribute \src "ls180.v:2451.1-2544.4" + wire $0\sdram_bankmachine3_cmd_payload_ras[0:0] + attribute \src "ls180.v:2451.1-2544.4" + wire $0\sdram_bankmachine3_cmd_payload_we[0:0] + attribute \src "ls180.v:2656.1-2664.4" + wire $0\sdram_bankmachine3_cmd_ready[0:0] + attribute \src "ls180.v:2451.1-2544.4" + wire $0\sdram_bankmachine3_cmd_valid[0:0] + attribute \src "ls180.v:2451.1-2544.4" + wire $0\sdram_bankmachine3_refresh_gnt[0:0] + attribute \src "ls180.v:2451.1-2544.4" + wire $0\sdram_bankmachine3_req_rdata_valid[0:0] + attribute \src "ls180.v:2451.1-2544.4" + wire $0\sdram_bankmachine3_req_wdata_ready[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 13 $0\sdram_bankmachine3_row[12:0] + attribute \src "ls180.v:2451.1-2544.4" + wire $0\sdram_bankmachine3_row_close[0:0] + attribute \src "ls180.v:2451.1-2544.4" + wire $0\sdram_bankmachine3_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:2451.1-2544.4" + wire $0\sdram_bankmachine3_row_open[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_bankmachine3_row_opened[0:0] + attribute \src "ls180.v:716.32-716.71" + wire $0\sdram_bankmachine3_trascon_ready[0:0] + attribute \src "ls180.v:714.32-714.70" + wire $0\sdram_bankmachine3_trccon_ready[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 3 $0\sdram_bankmachine3_twtpcon_count[2:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_bankmachine3_twtpcon_ready[0:0] + attribute \src "ls180.v:2578.1-2583.4" + wire $0\sdram_choose_cmd_cmd_payload_cas[0:0] + attribute \src "ls180.v:2584.1-2589.4" + wire $0\sdram_choose_cmd_cmd_payload_ras[0:0] + attribute \src "ls180.v:2590.1-2595.4" + wire $0\sdram_choose_cmd_cmd_payload_we[0:0] + attribute \src "ls180.v:724.5-724.38" + wire $0\sdram_choose_cmd_cmd_ready[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 2 $0\sdram_choose_cmd_grant[1:0] + attribute \src "ls180.v:2564.1-2570.4" + wire width 4 $0\sdram_choose_cmd_valids[3:0] + attribute \src "ls180.v:722.5-722.43" + wire $0\sdram_choose_cmd_want_activates[0:0] + attribute \src "ls180.v:721.5-721.38" + wire $0\sdram_choose_cmd_want_cmds[0:0] + attribute \src "ls180.v:719.5-719.39" + wire $0\sdram_choose_cmd_want_reads[0:0] + attribute \src "ls180.v:720.5-720.40" + wire $0\sdram_choose_cmd_want_writes[0:0] + attribute \src "ls180.v:2611.1-2616.4" + wire $0\sdram_choose_req_cmd_payload_cas[0:0] + attribute \src "ls180.v:2617.1-2622.4" + wire $0\sdram_choose_req_cmd_payload_ras[0:0] + attribute \src "ls180.v:2623.1-2628.4" + wire $0\sdram_choose_req_cmd_payload_we[0:0] + attribute \src "ls180.v:2669.1-2741.4" + wire $0\sdram_choose_req_cmd_ready[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 2 $0\sdram_choose_req_grant[1:0] + attribute \src "ls180.v:2597.1-2603.4" + wire width 4 $0\sdram_choose_req_valids[3:0] + attribute \src "ls180.v:2669.1-2741.4" + wire $0\sdram_choose_req_want_activates[0:0] + attribute \src "ls180.v:2669.1-2741.4" + wire $0\sdram_choose_req_want_reads[0:0] + attribute \src "ls180.v:2669.1-2741.4" + wire $0\sdram_choose_req_want_writes[0:0] + attribute \src "ls180.v:4180.1-4285.4" wire $0\sdram_clock[0:0] - attribute \src "ls180.v:7439.1-7509.4" - wire $0\sdram_cs_n[0:0] - attribute \src "ls180.v:7439.1-7509.4" - wire width 2 $0\sdram_dm[1:0] - attribute \src "ls180.v:7439.1-7509.4" - wire width 16 $0\sdram_dq_o[15:0] - attribute \src "ls180.v:7439.1-7509.4" - wire $0\sdram_dq_oe[0:0] - attribute \src "ls180.v:7439.1-7509.4" - wire $0\sdram_ras_n[0:0] - attribute \src "ls180.v:7439.1-7509.4" - wire $0\sdram_we_n[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\spimaster_clk[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\spimaster_cs_n[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\spimaster_mosi[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\spisdcard_clk[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\spisdcard_cs_n[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\spisdcard_mosi[0:0] - attribute \src "ls180.v:7511.1-10140.4" - wire $0\uart_tx[0:0] - attribute \src "ls180.v:1768.11-1768.49" - wire width 3 $1\builder_bankmachine0_next_state[2:0] - attribute \src "ls180.v:1767.11-1767.44" - wire width 3 $1\builder_bankmachine0_state[2:0] - attribute \src "ls180.v:1770.11-1770.49" - wire width 3 $1\builder_bankmachine1_next_state[2:0] - attribute \src "ls180.v:1769.11-1769.44" - wire width 3 $1\builder_bankmachine1_state[2:0] - attribute \src "ls180.v:1772.11-1772.49" - wire width 3 $1\builder_bankmachine2_next_state[2:0] - attribute \src "ls180.v:1771.11-1771.44" - wire width 3 $1\builder_bankmachine2_state[2:0] - attribute \src "ls180.v:1774.11-1774.49" - wire width 3 $1\builder_bankmachine3_next_state[2:0] - attribute \src "ls180.v:1773.11-1773.44" - wire width 3 $1\builder_bankmachine3_state[2:0] - attribute \src "ls180.v:2627.5-2627.41" - wire $1\builder_comb_rhs_array_muxed0[0:0] - attribute \src "ls180.v:2640.5-2640.42" - wire $1\builder_comb_rhs_array_muxed10[0:0] - attribute \src "ls180.v:2641.5-2641.42" - wire $1\builder_comb_rhs_array_muxed11[0:0] - attribute \src "ls180.v:2645.12-2645.50" - wire width 22 $1\builder_comb_rhs_array_muxed12[21:0] - attribute \src "ls180.v:2646.5-2646.42" - wire $1\builder_comb_rhs_array_muxed13[0:0] - attribute \src "ls180.v:2647.5-2647.42" - wire $1\builder_comb_rhs_array_muxed14[0:0] - attribute \src "ls180.v:2648.12-2648.50" - wire width 22 $1\builder_comb_rhs_array_muxed15[21:0] - attribute \src "ls180.v:2649.5-2649.42" - wire $1\builder_comb_rhs_array_muxed16[0:0] - attribute \src "ls180.v:2650.5-2650.42" - wire $1\builder_comb_rhs_array_muxed17[0:0] - attribute \src "ls180.v:2651.12-2651.50" - wire width 22 $1\builder_comb_rhs_array_muxed18[21:0] - attribute \src "ls180.v:2652.5-2652.42" - wire $1\builder_comb_rhs_array_muxed19[0:0] - attribute \src "ls180.v:2628.12-2628.49" - wire width 13 $1\builder_comb_rhs_array_muxed1[12:0] - attribute \src "ls180.v:2653.5-2653.42" - wire $1\builder_comb_rhs_array_muxed20[0:0] - attribute \src "ls180.v:2654.12-2654.50" - wire width 22 $1\builder_comb_rhs_array_muxed21[21:0] - attribute \src "ls180.v:2655.5-2655.42" - wire $1\builder_comb_rhs_array_muxed22[0:0] - attribute \src "ls180.v:2656.5-2656.42" - wire $1\builder_comb_rhs_array_muxed23[0:0] - attribute \src "ls180.v:2657.12-2657.50" - wire width 32 $1\builder_comb_rhs_array_muxed24[31:0] - attribute \src "ls180.v:2658.12-2658.50" - wire width 64 $1\builder_comb_rhs_array_muxed25[63:0] - attribute \src "ls180.v:2659.11-2659.48" - wire width 8 $1\builder_comb_rhs_array_muxed26[7:0] - attribute \src "ls180.v:2660.5-2660.42" - wire $1\builder_comb_rhs_array_muxed27[0:0] - attribute \src "ls180.v:2661.5-2661.42" - wire $1\builder_comb_rhs_array_muxed28[0:0] - attribute \src "ls180.v:2662.5-2662.42" - wire $1\builder_comb_rhs_array_muxed29[0:0] - attribute \src "ls180.v:2629.11-2629.47" - wire width 2 $1\builder_comb_rhs_array_muxed2[1:0] - attribute \src "ls180.v:2663.11-2663.48" - wire width 3 $1\builder_comb_rhs_array_muxed30[2:0] - attribute \src "ls180.v:2664.11-2664.48" - wire width 2 $1\builder_comb_rhs_array_muxed31[1:0] - attribute \src "ls180.v:2630.5-2630.41" - wire $1\builder_comb_rhs_array_muxed3[0:0] - attribute \src "ls180.v:2631.5-2631.41" - wire $1\builder_comb_rhs_array_muxed4[0:0] - attribute \src "ls180.v:2632.5-2632.41" - wire $1\builder_comb_rhs_array_muxed5[0:0] - attribute \src "ls180.v:2636.5-2636.41" - wire $1\builder_comb_rhs_array_muxed6[0:0] - attribute \src "ls180.v:2637.12-2637.49" - wire width 13 $1\builder_comb_rhs_array_muxed7[12:0] - attribute \src "ls180.v:2638.11-2638.47" - wire width 2 $1\builder_comb_rhs_array_muxed8[1:0] - attribute \src "ls180.v:2639.5-2639.41" - wire $1\builder_comb_rhs_array_muxed9[0:0] - attribute \src "ls180.v:2633.5-2633.39" - wire $1\builder_comb_t_array_muxed0[0:0] - attribute \src "ls180.v:2634.5-2634.39" - wire $1\builder_comb_t_array_muxed1[0:0] - attribute \src "ls180.v:2635.5-2635.39" - wire $1\builder_comb_t_array_muxed2[0:0] - attribute \src "ls180.v:2642.5-2642.39" - wire $1\builder_comb_t_array_muxed3[0:0] - attribute \src "ls180.v:2643.5-2643.39" - wire $1\builder_comb_t_array_muxed4[0:0] - attribute \src "ls180.v:2644.5-2644.39" - wire $1\builder_comb_t_array_muxed5[0:0] - attribute \src "ls180.v:1754.5-1754.41" - wire $1\builder_converter0_next_state[0:0] - attribute \src "ls180.v:1753.5-1753.36" - wire $1\builder_converter0_state[0:0] - attribute \src "ls180.v:1758.5-1758.41" - wire $1\builder_converter1_next_state[0:0] - attribute \src "ls180.v:1757.5-1757.36" - wire $1\builder_converter1_state[0:0] - attribute \src "ls180.v:1762.5-1762.41" - wire $1\builder_converter2_next_state[0:0] - attribute \src "ls180.v:1761.5-1761.36" - wire $1\builder_converter2_state[0:0] - attribute \src "ls180.v:1799.5-1799.40" - wire $1\builder_converter_next_state[0:0] - attribute \src "ls180.v:1798.5-1798.35" - wire $1\builder_converter_state[0:0] - attribute \src "ls180.v:1927.12-1927.39" - wire width 20 $1\builder_count[19:0] - attribute \src "ls180.v:1924.5-1924.25" - wire $1\builder_error[0:0] - attribute \src "ls180.v:1921.11-1921.31" - wire width 3 $1\builder_grant[2:0] - attribute \src "ls180.v:1931.11-1931.51" - wire width 8 $1\builder_interface0_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2433.11-2433.52" - wire width 8 $1\builder_interface10_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2466.11-2466.52" - wire width 8 $1\builder_interface11_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2507.11-2507.52" - wire width 8 $1\builder_interface12_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2572.11-2572.52" - wire width 8 $1\builder_interface13_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2597.11-2597.52" - wire width 8 $1\builder_interface14_bank_bus_dat_r[7:0] - attribute \src "ls180.v:1972.11-1972.51" - wire width 8 $1\builder_interface1_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2001.11-2001.51" - wire width 8 $1\builder_interface2_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2014.11-2014.51" - wire width 8 $1\builder_interface3_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2055.11-2055.51" - wire width 8 $1\builder_interface4_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2096.11-2096.51" - wire width 8 $1\builder_interface5_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2161.11-2161.51" - wire width 8 $1\builder_interface6_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2294.11-2294.51" - wire width 8 $1\builder_interface7_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2375.11-2375.51" - wire width 8 $1\builder_interface8_bank_bus_dat_r[7:0] - attribute \src "ls180.v:2392.11-2392.51" - wire width 8 $1\builder_interface9_bank_bus_dat_r[7:0] - attribute \src "ls180.v:1886.12-1886.43" - wire width 14 $1\builder_libresocsim_adr[13:0] - attribute \src "ls180.v:2623.12-2623.55" - wire width 14 $1\builder_libresocsim_adr_next_value1[13:0] - attribute \src "ls180.v:2624.5-2624.50" - wire $1\builder_libresocsim_adr_next_value_ce1[0:0] - attribute \src "ls180.v:1888.11-1888.43" - wire width 8 $1\builder_libresocsim_dat_w[7:0] - attribute \src "ls180.v:2621.11-2621.55" - wire width 8 $1\builder_libresocsim_dat_w_next_value0[7:0] - attribute \src "ls180.v:2622.5-2622.52" - wire $1\builder_libresocsim_dat_w_next_value_ce0[0:0] - attribute \src "ls180.v:1887.5-1887.34" - wire $1\builder_libresocsim_we[0:0] - attribute \src "ls180.v:2625.5-2625.46" - wire $1\builder_libresocsim_we_next_value2[0:0] - attribute \src "ls180.v:2626.5-2626.49" - wire $1\builder_libresocsim_we_next_value_ce2[0:0] - attribute \src "ls180.v:1896.5-1896.44" - wire $1\builder_libresocsim_wishbone_ack[0:0] - attribute \src "ls180.v:1892.12-1892.54" - wire width 32 $1\builder_libresocsim_wishbone_dat_r[31:0] - attribute \src "ls180.v:1776.11-1776.48" - wire width 3 $1\builder_multiplexer_next_state[2:0] - attribute \src "ls180.v:1775.11-1775.43" - wire width 3 $1\builder_multiplexer_state[2:0] - attribute \src "ls180.v:2730.32-2730.66" - wire $1\builder_multiregimpl0_regs0[0:0] - attribute \src "ls180.v:2731.32-2731.66" - wire $1\builder_multiregimpl0_regs1[0:0] - attribute \src "ls180.v:2750.32-2750.67" - wire $1\builder_multiregimpl10_regs0[0:0] - attribute \src "ls180.v:2751.32-2751.67" - wire $1\builder_multiregimpl10_regs1[0:0] - attribute \src "ls180.v:2752.32-2752.67" - wire $1\builder_multiregimpl11_regs0[0:0] - attribute \src "ls180.v:2753.32-2753.67" - wire $1\builder_multiregimpl11_regs1[0:0] - attribute \src "ls180.v:2754.32-2754.67" - wire $1\builder_multiregimpl12_regs0[0:0] - attribute \src "ls180.v:2755.32-2755.67" - wire $1\builder_multiregimpl12_regs1[0:0] - attribute \src "ls180.v:2756.32-2756.67" - wire $1\builder_multiregimpl13_regs0[0:0] - attribute \src "ls180.v:2757.32-2757.67" - wire $1\builder_multiregimpl13_regs1[0:0] - attribute \src "ls180.v:2758.32-2758.67" - wire $1\builder_multiregimpl14_regs0[0:0] - attribute \src "ls180.v:2759.32-2759.67" - wire $1\builder_multiregimpl14_regs1[0:0] - attribute \src "ls180.v:2760.32-2760.67" - wire $1\builder_multiregimpl15_regs0[0:0] - attribute \src "ls180.v:2761.32-2761.67" - wire $1\builder_multiregimpl15_regs1[0:0] - attribute \src "ls180.v:2762.32-2762.67" - wire $1\builder_multiregimpl16_regs0[0:0] - attribute \src "ls180.v:2763.32-2763.67" - wire $1\builder_multiregimpl16_regs1[0:0] - attribute \src "ls180.v:2732.32-2732.66" - wire $1\builder_multiregimpl1_regs0[0:0] - attribute \src "ls180.v:2733.32-2733.66" - wire $1\builder_multiregimpl1_regs1[0:0] - attribute \src "ls180.v:2734.32-2734.66" - wire $1\builder_multiregimpl2_regs0[0:0] - attribute \src "ls180.v:2735.32-2735.66" - wire $1\builder_multiregimpl2_regs1[0:0] - attribute \src "ls180.v:2736.32-2736.66" - wire $1\builder_multiregimpl3_regs0[0:0] - attribute \src "ls180.v:2737.32-2737.66" - wire $1\builder_multiregimpl3_regs1[0:0] - attribute \src "ls180.v:2738.32-2738.66" - wire $1\builder_multiregimpl4_regs0[0:0] - attribute \src "ls180.v:2739.32-2739.66" - wire $1\builder_multiregimpl4_regs1[0:0] - attribute \src "ls180.v:2740.32-2740.66" - wire $1\builder_multiregimpl5_regs0[0:0] - attribute \src "ls180.v:2741.32-2741.66" - wire $1\builder_multiregimpl5_regs1[0:0] - attribute \src "ls180.v:2742.32-2742.66" - wire $1\builder_multiregimpl6_regs0[0:0] - attribute \src "ls180.v:2743.32-2743.66" - wire $1\builder_multiregimpl6_regs1[0:0] - attribute \src "ls180.v:2744.32-2744.66" - wire $1\builder_multiregimpl7_regs0[0:0] - attribute \src "ls180.v:2745.32-2745.66" - wire $1\builder_multiregimpl7_regs1[0:0] - attribute \src "ls180.v:2746.32-2746.66" - wire $1\builder_multiregimpl8_regs0[0:0] - attribute \src "ls180.v:2747.32-2747.66" - wire $1\builder_multiregimpl8_regs1[0:0] - attribute \src "ls180.v:2748.32-2748.66" - wire $1\builder_multiregimpl9_regs0[0:0] - attribute \src "ls180.v:2749.32-2749.66" - wire $1\builder_multiregimpl9_regs1[0:0] - attribute \src "ls180.v:1794.5-1794.43" - wire $1\builder_new_master_rdata_valid0[0:0] - attribute \src "ls180.v:1795.5-1795.43" - wire $1\builder_new_master_rdata_valid1[0:0] - attribute \src "ls180.v:1796.5-1796.43" - wire $1\builder_new_master_rdata_valid2[0:0] - attribute \src "ls180.v:1797.5-1797.43" - wire $1\builder_new_master_rdata_valid3[0:0] - attribute \src "ls180.v:1793.5-1793.42" - wire $1\builder_new_master_wdata_ready[0:0] - attribute \src "ls180.v:2620.11-2620.36" - wire width 2 $1\builder_next_state[1:0] - attribute \src "ls180.v:1766.11-1766.46" - wire width 2 $1\builder_refresher_next_state[1:0] - attribute \src "ls180.v:1765.11-1765.41" - wire width 2 $1\builder_refresher_state[1:0] - attribute \src "ls180.v:1875.11-1875.51" - wire width 2 $1\builder_sdblock2memdma_next_state[1:0] - attribute \src "ls180.v:1874.11-1874.46" - wire width 2 $1\builder_sdblock2memdma_state[1:0] - attribute \src "ls180.v:1843.5-1843.57" - wire $1\builder_sdcore_crcupstreaminserter_next_state[0:0] - attribute \src "ls180.v:1842.5-1842.52" - wire $1\builder_sdcore_crcupstreaminserter_state[0:0] - attribute \src "ls180.v:1855.11-1855.47" - wire width 3 $1\builder_sdcore_fsm_next_state[2:0] - attribute \src "ls180.v:1854.11-1854.42" - wire width 3 $1\builder_sdcore_fsm_state[2:0] - attribute \src "ls180.v:1879.5-1879.49" - wire $1\builder_sdmem2blockdma_fsm_next_state[0:0] - attribute \src "ls180.v:1878.5-1878.44" - wire $1\builder_sdmem2blockdma_fsm_state[0:0] - attribute \src "ls180.v:1883.11-1883.65" - wire width 2 $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] - attribute \src "ls180.v:1882.11-1882.60" - wire width 2 $1\builder_sdmem2blockdma_resetinserter_state[1:0] - attribute \src "ls180.v:1831.11-1831.46" - wire width 3 $1\builder_sdphy_fsm_next_state[2:0] - attribute \src "ls180.v:1830.11-1830.41" - wire width 3 $1\builder_sdphy_fsm_state[2:0] - attribute \src "ls180.v:1819.11-1819.52" - wire width 3 $1\builder_sdphy_sdphycmdr_next_state[2:0] - attribute \src "ls180.v:1818.11-1818.47" - wire width 3 $1\builder_sdphy_sdphycmdr_state[2:0] - attribute \src "ls180.v:1815.11-1815.52" - wire width 2 $1\builder_sdphy_sdphycmdw_next_state[1:0] - attribute \src "ls180.v:1814.11-1814.47" - wire width 2 $1\builder_sdphy_sdphycmdw_state[1:0] - attribute \src "ls180.v:1827.5-1827.46" - wire $1\builder_sdphy_sdphycrcr_next_state[0:0] - attribute \src "ls180.v:1826.5-1826.41" - wire $1\builder_sdphy_sdphycrcr_state[0:0] - attribute \src "ls180.v:1835.11-1835.53" - wire width 3 $1\builder_sdphy_sdphydatar_next_state[2:0] - attribute \src "ls180.v:1834.11-1834.48" - wire width 3 $1\builder_sdphy_sdphydatar_state[2:0] - attribute \src "ls180.v:1811.5-1811.46" - wire $1\builder_sdphy_sdphyinit_next_state[0:0] - attribute \src "ls180.v:1810.5-1810.41" - wire $1\builder_sdphy_sdphyinit_state[0:0] - attribute \src "ls180.v:1915.5-1915.30" - wire $1\builder_shared_ack[0:0] - attribute \src "ls180.v:1911.12-1911.40" - wire width 32 $1\builder_shared_dat_r[31:0] - attribute \src "ls180.v:1922.11-1922.35" - wire width 6 $1\builder_slave_sel[5:0] - attribute \src "ls180.v:1923.11-1923.37" - wire width 6 $1\builder_slave_sel_r[5:0] - attribute \src "ls180.v:1803.11-1803.47" - wire width 2 $1\builder_spimaster0_next_state[1:0] - attribute \src "ls180.v:1802.11-1802.42" - wire width 2 $1\builder_spimaster0_state[1:0] - attribute \src "ls180.v:1807.11-1807.47" - wire width 2 $1\builder_spimaster1_next_state[1:0] - attribute \src "ls180.v:1806.11-1806.42" - wire width 2 $1\builder_spimaster1_state[1:0] - attribute \src "ls180.v:2619.11-2619.31" - wire width 2 $1\builder_state[1:0] - attribute \src "ls180.v:2672.5-2672.39" - wire $1\builder_sync_f_array_muxed0[0:0] - attribute \src "ls180.v:2673.5-2673.39" - wire $1\builder_sync_f_array_muxed1[0:0] - attribute \src "ls180.v:2665.11-2665.47" - wire width 2 $1\builder_sync_rhs_array_muxed0[1:0] - attribute \src "ls180.v:2666.12-2666.49" - wire width 13 $1\builder_sync_rhs_array_muxed1[12:0] - attribute \src "ls180.v:2667.5-2667.41" - wire $1\builder_sync_rhs_array_muxed2[0:0] - attribute \src "ls180.v:2668.5-2668.41" - wire $1\builder_sync_rhs_array_muxed3[0:0] - attribute \src "ls180.v:2669.5-2669.41" - wire $1\builder_sync_rhs_array_muxed4[0:0] - attribute \src "ls180.v:2670.5-2670.41" - wire $1\builder_sync_rhs_array_muxed5[0:0] - attribute \src "ls180.v:2671.5-2671.41" - wire $1\builder_sync_rhs_array_muxed6[0:0] - attribute \src "ls180.v:849.5-849.29" - wire $1\main_cmd_consumed[0:0] - attribute \src "ls180.v:232.5-232.35" - wire $1\main_converter0_counter[0:0] - attribute \src "ls180.v:1755.5-1755.57" - wire $1\main_converter0_counter_converter0_next_value[0:0] - attribute \src "ls180.v:1756.5-1756.60" - wire $1\main_converter0_counter_converter0_next_value_ce[0:0] - attribute \src "ls180.v:234.12-234.41" - wire width 64 $1\main_converter0_dat_r[63:0] - attribute \src "ls180.v:231.5-231.32" - wire $1\main_converter0_skip[0:0] - attribute \src "ls180.v:247.5-247.35" - wire $1\main_converter1_counter[0:0] - attribute \src "ls180.v:1759.5-1759.57" - wire $1\main_converter1_counter_converter1_next_value[0:0] - attribute \src "ls180.v:1760.5-1760.60" - wire $1\main_converter1_counter_converter1_next_value_ce[0:0] - attribute \src "ls180.v:249.12-249.41" - wire width 64 $1\main_converter1_dat_r[63:0] - attribute \src "ls180.v:246.5-246.32" - wire $1\main_converter1_skip[0:0] - attribute \src "ls180.v:846.5-846.34" - wire $1\main_converter_counter[0:0] - attribute \src "ls180.v:1800.5-1800.55" - wire $1\main_converter_counter_converter_next_value[0:0] - attribute \src "ls180.v:1801.5-1801.58" - wire $1\main_converter_counter_converter_next_value_ce[0:0] - attribute \src "ls180.v:848.12-848.40" - wire width 32 $1\main_converter_dat_r[31:0] - attribute \src "ls180.v:845.5-845.31" - wire $1\main_converter_skip[0:0] - attribute \src "ls180.v:268.12-268.38" - wire width 16 $1\main_dfi_p0_rddata[15:0] - attribute \src "ls180.v:269.5-269.36" - wire $1\main_dfi_p0_rddata_valid[0:0] - attribute \src "ls180.v:1086.12-1086.30" - wire width 24 $1\main_dummy[23:0] - attribute \src "ls180.v:997.12-997.49" - wire width 16 $1\main_gpiotristateasic0_status[15:0] - attribute \src "ls180.v:1003.5-1003.40" - wire $1\main_gpiotristateasic1_oe_re[0:0] - attribute \src "ls180.v:1002.12-1002.53" - wire width 16 $1\main_gpiotristateasic1_oe_storage[15:0] - attribute \src "ls180.v:1007.5-1007.41" - wire $1\main_gpiotristateasic1_out_re[0:0] - attribute \src "ls180.v:1006.12-1006.54" - wire width 16 $1\main_gpiotristateasic1_out_storage[15:0] - attribute \src "ls180.v:1004.12-1004.49" - wire width 16 $1\main_gpiotristateasic1_status[15:0] - attribute \src "ls180.v:1111.5-1111.23" - wire $1\main_i2c_re[0:0] - attribute \src "ls180.v:1110.11-1110.34" - wire width 3 $1\main_i2c_storage[2:0] - attribute \src "ls180.v:253.5-253.24" - wire $1\main_int_rst[0:0] - attribute \src "ls180.v:226.5-226.51" - wire $1\main_interface0_converted_interface_ack[0:0] - attribute \src "ls180.v:1659.12-1659.43" - wire width 32 $1\main_interface1_bus_adr[31:0] - attribute \src "ls180.v:1663.5-1663.35" - wire $1\main_interface1_bus_cyc[0:0] - attribute \src "ls180.v:1662.11-1662.41" - wire width 8 $1\main_interface1_bus_sel[7:0] - attribute \src "ls180.v:1664.5-1664.35" - wire $1\main_interface1_bus_stb[0:0] - attribute \src "ls180.v:1666.5-1666.34" - wire $1\main_interface1_bus_we[0:0] - attribute \src "ls180.v:241.5-241.51" - wire $1\main_interface1_converted_interface_ack[0:0] - attribute \src "ls180.v:63.12-63.47" - wire width 32 $1\main_libresocsim_bus_errors[31:0] - attribute \src "ls180.v:183.5-183.34" - wire $1\main_libresocsim_en_re[0:0] - attribute \src "ls180.v:182.5-182.39" - wire $1\main_libresocsim_en_storage[0:0] - attribute \src "ls180.v:203.5-203.44" - wire $1\main_libresocsim_eventmanager_re[0:0] - attribute \src "ls180.v:202.5-202.49" - wire $1\main_libresocsim_eventmanager_storage[0:0] - attribute \src "ls180.v:65.12-65.55" - wire width 16 $1\main_libresocsim_libresoc_interrupt[15:0] - attribute \src "ls180.v:88.12-88.58" - wire width 30 $1\main_libresocsim_libresoc_xics_icp_adr[29:0] - attribute \src "ls180.v:92.5-92.50" - wire $1\main_libresocsim_libresoc_xics_icp_cyc[0:0] - attribute \src "ls180.v:89.12-89.60" - wire width 32 $1\main_libresocsim_libresoc_xics_icp_dat_w[31:0] - attribute \src "ls180.v:91.11-91.56" - wire width 4 $1\main_libresocsim_libresoc_xics_icp_sel[3:0] - attribute \src "ls180.v:93.5-93.50" - wire $1\main_libresocsim_libresoc_xics_icp_stb[0:0] - attribute \src "ls180.v:95.5-95.49" - wire $1\main_libresocsim_libresoc_xics_icp_we[0:0] - attribute \src "ls180.v:97.12-97.58" - wire width 30 $1\main_libresocsim_libresoc_xics_ics_adr[29:0] - attribute \src "ls180.v:101.5-101.50" - wire $1\main_libresocsim_libresoc_xics_ics_cyc[0:0] - attribute \src "ls180.v:98.12-98.60" - wire width 32 $1\main_libresocsim_libresoc_xics_ics_dat_w[31:0] - attribute \src "ls180.v:100.11-100.56" - wire width 4 $1\main_libresocsim_libresoc_xics_ics_sel[3:0] - attribute \src "ls180.v:102.5-102.50" - wire $1\main_libresocsim_libresoc_xics_ics_stb[0:0] - attribute \src "ls180.v:104.5-104.49" - wire $1\main_libresocsim_libresoc_xics_ics_we[0:0] - attribute \src "ls180.v:179.5-179.36" - wire $1\main_libresocsim_load_re[0:0] - attribute \src "ls180.v:178.12-178.49" - wire width 32 $1\main_libresocsim_load_storage[31:0] - attribute \src "ls180.v:169.5-169.40" - wire $1\main_libresocsim_ram_bus_ack[0:0] - attribute \src "ls180.v:181.5-181.38" - wire $1\main_libresocsim_reload_re[0:0] - attribute \src "ls180.v:180.12-180.51" - wire width 32 $1\main_libresocsim_reload_storage[31:0] - attribute \src "ls180.v:56.5-56.37" - wire $1\main_libresocsim_reset_re[0:0] - attribute \src "ls180.v:55.5-55.42" - wire $1\main_libresocsim_reset_storage[0:0] - attribute \src "ls180.v:58.5-58.39" - wire $1\main_libresocsim_scratch_re[0:0] - attribute \src "ls180.v:57.12-57.60" - wire width 32 $1\main_libresocsim_scratch_storage[31:0] - attribute \src "ls180.v:185.5-185.44" - wire $1\main_libresocsim_update_value_re[0:0] - attribute \src "ls180.v:184.5-184.49" - wire $1\main_libresocsim_update_value_storage[0:0] - attribute \src "ls180.v:204.12-204.42" - wire width 32 $1\main_libresocsim_value[31:0] - attribute \src "ls180.v:186.12-186.49" - wire width 32 $1\main_libresocsim_value_status[31:0] - attribute \src "ls180.v:176.11-176.37" - wire width 8 $1\main_libresocsim_we[7:0] - attribute \src "ls180.v:192.5-192.39" - wire $1\main_libresocsim_zero_clear[0:0] - attribute \src "ls180.v:193.5-193.45" - wire $1\main_libresocsim_zero_old_trigger[0:0] - attribute \src "ls180.v:190.5-190.41" - wire $1\main_libresocsim_zero_pending[0:0] - attribute \src "ls180.v:837.12-837.40" - wire width 30 $1\main_litedram_wb_adr[29:0] - attribute \src "ls180.v:841.5-841.32" - wire $1\main_litedram_wb_cyc[0:0] - attribute \src "ls180.v:838.12-838.42" - wire width 16 $1\main_litedram_wb_dat_w[15:0] - attribute \src "ls180.v:840.11-840.38" - wire width 2 $1\main_litedram_wb_sel[1:0] - attribute \src "ls180.v:842.5-842.32" - wire $1\main_litedram_wb_stb[0:0] - attribute \src "ls180.v:844.5-844.31" - wire $1\main_litedram_wb_we[0:0] - attribute \src "ls180.v:1090.12-1090.37" - wire width 32 $1\main_pwm0_counter[31:0] - attribute \src "ls180.v:1092.5-1092.31" - wire $1\main_pwm0_enable_re[0:0] - attribute \src "ls180.v:1091.5-1091.36" - wire $1\main_pwm0_enable_storage[0:0] - attribute \src "ls180.v:1096.5-1096.31" - wire $1\main_pwm0_period_re[0:0] - attribute \src "ls180.v:1095.12-1095.44" - wire width 32 $1\main_pwm0_period_storage[31:0] - attribute \src "ls180.v:1094.5-1094.30" - wire $1\main_pwm0_width_re[0:0] - attribute \src "ls180.v:1093.12-1093.43" - wire width 32 $1\main_pwm0_width_storage[31:0] - attribute \src "ls180.v:1100.12-1100.37" - wire width 32 $1\main_pwm1_counter[31:0] - attribute \src "ls180.v:1102.5-1102.31" - wire $1\main_pwm1_enable_re[0:0] - attribute \src "ls180.v:1101.5-1101.36" - wire $1\main_pwm1_enable_storage[0:0] - attribute \src "ls180.v:1106.5-1106.31" - wire $1\main_pwm1_period_re[0:0] - attribute \src "ls180.v:1105.12-1105.44" - wire width 32 $1\main_pwm1_period_storage[31:0] - attribute \src "ls180.v:1104.5-1104.30" - wire $1\main_pwm1_width_re[0:0] - attribute \src "ls180.v:1103.12-1103.43" - wire width 32 $1\main_pwm1_width_storage[31:0] - attribute \src "ls180.v:211.5-211.36" - wire $1\main_ram_bus_ram_bus_ack[0:0] - attribute \src "ls180.v:218.11-218.29" - wire width 8 $1\main_ram_we[7:0] - attribute \src "ls180.v:270.11-270.32" - wire width 3 $1\main_rddata_en[2:0] - attribute \src "ls180.v:1628.11-1628.50" - wire width 3 $1\main_sdblock2mem_converter_demux[2:0] - attribute \src "ls180.v:1624.5-1624.51" - wire $1\main_sdblock2mem_converter_source_first[0:0] - attribute \src "ls180.v:1625.5-1625.50" - wire $1\main_sdblock2mem_converter_source_last[0:0] - attribute \src "ls180.v:1626.12-1626.66" - wire width 64 $1\main_sdblock2mem_converter_source_payload_data[63:0] - attribute \src "ls180.v:1627.11-1627.77" - wire width 4 $1\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:1630.5-1630.49" - wire $1\main_sdblock2mem_converter_strobe_all[0:0] - attribute \src "ls180.v:1603.11-1603.47" - wire width 5 $1\main_sdblock2mem_fifo_consume[4:0] - attribute \src "ls180.v:1600.11-1600.45" - wire width 6 $1\main_sdblock2mem_fifo_level[5:0] - attribute \src "ls180.v:1602.11-1602.47" - wire width 5 $1\main_sdblock2mem_fifo_produce[4:0] - attribute \src "ls180.v:1604.11-1604.50" - wire width 5 $1\main_sdblock2mem_fifo_wrport_adr[4:0] - attribute \src "ls180.v:1638.12-1638.62" - wire width 32 $1\main_sdblock2mem_sink_sink_payload_address[31:0] - attribute \src "ls180.v:1639.12-1639.60" - wire width 64 $1\main_sdblock2mem_sink_sink_payload_data1[63:0] - attribute \src "ls180.v:1636.5-1636.45" - wire $1\main_sdblock2mem_sink_sink_valid1[0:0] - attribute \src "ls180.v:1646.5-1646.54" - wire $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] - attribute \src "ls180.v:1645.12-1645.67" - wire width 64 $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] - attribute \src "ls180.v:1650.5-1650.56" - wire $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] - attribute \src "ls180.v:1649.5-1649.61" - wire $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] - attribute \src "ls180.v:1648.5-1648.56" - wire $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] - attribute \src "ls180.v:1647.12-1647.69" - wire width 32 $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] - attribute \src "ls180.v:1654.5-1654.54" - wire $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] - attribute \src "ls180.v:1653.5-1653.59" - wire $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] - attribute \src "ls180.v:1656.12-1656.61" - wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] - attribute \src "ls180.v:1876.12-1876.87" - wire width 32 $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] - attribute \src "ls180.v:1877.5-1877.82" - wire $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] - attribute \src "ls180.v:1641.5-1641.57" - wire $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] - attribute \src "ls180.v:1651.5-1651.53" - wire $1\main_sdblock2mem_wishbonedmawriter_status[0:0] - attribute \src "ls180.v:1420.5-1420.38" - wire $1\main_sdcore_block_count_re[0:0] - attribute \src "ls180.v:1419.12-1419.51" - wire width 32 $1\main_sdcore_block_count_storage[31:0] - attribute \src "ls180.v:1418.5-1418.39" - wire $1\main_sdcore_block_length_re[0:0] - attribute \src "ls180.v:1417.11-1417.51" - wire width 10 $1\main_sdcore_block_length_storage[9:0] - attribute \src "ls180.v:1404.5-1404.39" - wire $1\main_sdcore_cmd_argument_re[0:0] - attribute \src "ls180.v:1403.12-1403.52" - wire width 32 $1\main_sdcore_cmd_argument_storage[31:0] - attribute \src "ls180.v:1406.5-1406.38" - wire $1\main_sdcore_cmd_command_re[0:0] - attribute \src "ls180.v:1405.12-1405.51" - wire width 32 $1\main_sdcore_cmd_command_storage[31:0] - attribute \src "ls180.v:1559.11-1559.39" - wire width 3 $1\main_sdcore_cmd_count[2:0] - attribute \src "ls180.v:1860.11-1860.62" - wire width 3 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] - attribute \src "ls180.v:1861.5-1861.59" - wire $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] - attribute \src "ls180.v:1560.5-1560.32" - wire $1\main_sdcore_cmd_done[0:0] - attribute \src "ls180.v:1856.5-1856.55" - wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] - attribute \src "ls180.v:1857.5-1857.58" - wire $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] - attribute \src "ls180.v:1561.5-1561.33" - wire $1\main_sdcore_cmd_error[0:0] - attribute \src "ls180.v:1864.5-1864.56" - wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] - attribute \src "ls180.v:1865.5-1865.59" - wire $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] - attribute \src "ls180.v:1411.13-1411.53" - wire width 128 $1\main_sdcore_cmd_response_status[127:0] - attribute \src "ls180.v:1872.13-1872.76" - wire width 128 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] - attribute \src "ls180.v:1873.5-1873.69" - wire $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] - attribute \src "ls180.v:1562.5-1562.35" - wire $1\main_sdcore_cmd_timeout[0:0] - attribute \src "ls180.v:1866.5-1866.58" - wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] - attribute \src "ls180.v:1867.5-1867.61" - wire $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] - attribute \src "ls180.v:1520.11-1520.47" - wire width 4 $1\main_sdcore_crc16_checker_cnt[3:0] - attribute \src "ls180.v:1526.5-1526.46" - wire $1\main_sdcore_crc16_checker_crc0_clr[0:0] - attribute \src "ls180.v:1525.12-1525.54" - wire width 16 $1\main_sdcore_crc16_checker_crc0_crc[15:0] - attribute \src "ls180.v:1521.12-1521.58" - wire width 16 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] - attribute \src "ls180.v:1533.5-1533.46" - wire $1\main_sdcore_crc16_checker_crc1_clr[0:0] - attribute \src "ls180.v:1532.12-1532.54" - wire width 16 $1\main_sdcore_crc16_checker_crc1_crc[15:0] - attribute \src "ls180.v:1528.12-1528.58" - wire width 16 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] - attribute \src "ls180.v:1540.5-1540.46" - wire $1\main_sdcore_crc16_checker_crc2_clr[0:0] - attribute \src "ls180.v:1539.12-1539.54" - wire width 16 $1\main_sdcore_crc16_checker_crc2_crc[15:0] - attribute \src "ls180.v:1535.12-1535.58" - wire width 16 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] - attribute \src "ls180.v:1547.5-1547.46" - wire $1\main_sdcore_crc16_checker_crc3_clr[0:0] - attribute \src "ls180.v:1546.12-1546.54" - wire width 16 $1\main_sdcore_crc16_checker_crc3_crc[15:0] - attribute \src "ls180.v:1542.12-1542.58" - wire width 16 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] - attribute \src "ls180.v:1549.12-1549.53" - wire width 16 $1\main_sdcore_crc16_checker_crctmp0[15:0] - attribute \src "ls180.v:1550.12-1550.53" - wire width 16 $1\main_sdcore_crc16_checker_crctmp1[15:0] - attribute \src "ls180.v:1551.12-1551.53" - wire width 16 $1\main_sdcore_crc16_checker_crctmp2[15:0] - attribute \src "ls180.v:1552.12-1552.53" - wire width 16 $1\main_sdcore_crc16_checker_crctmp3[15:0] - attribute \src "ls180.v:1554.12-1554.51" - wire width 16 $1\main_sdcore_crc16_checker_fifo0[15:0] - attribute \src "ls180.v:1555.12-1555.51" - wire width 16 $1\main_sdcore_crc16_checker_fifo1[15:0] - attribute \src "ls180.v:1556.12-1556.51" - wire width 16 $1\main_sdcore_crc16_checker_fifo2[15:0] - attribute \src "ls180.v:1557.12-1557.51" - wire width 16 $1\main_sdcore_crc16_checker_fifo3[15:0] - attribute \src "ls180.v:1511.5-1511.48" - wire $1\main_sdcore_crc16_checker_sink_first[0:0] - attribute \src "ls180.v:1512.5-1512.47" - wire $1\main_sdcore_crc16_checker_sink_last[0:0] - attribute \src "ls180.v:1513.11-1513.61" - wire width 8 $1\main_sdcore_crc16_checker_sink_payload_data[7:0] - attribute \src "ls180.v:1510.5-1510.48" - wire $1\main_sdcore_crc16_checker_sink_ready[0:0] - attribute \src "ls180.v:1509.5-1509.48" - wire $1\main_sdcore_crc16_checker_sink_valid[0:0] - attribute \src "ls180.v:1514.5-1514.50" - wire $1\main_sdcore_crc16_checker_source_valid[0:0] - attribute \src "ls180.v:1519.11-1519.47" - wire width 8 $1\main_sdcore_crc16_checker_val[7:0] - attribute \src "ls180.v:1553.5-1553.43" - wire $1\main_sdcore_crc16_checker_valid[0:0] - attribute \src "ls180.v:1476.11-1476.48" - wire width 3 $1\main_sdcore_crc16_inserter_cnt[2:0] - attribute \src "ls180.v:1852.11-1852.87" - wire width 3 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] - attribute \src "ls180.v:1853.5-1853.84" - wire $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] - attribute \src "ls180.v:1481.12-1481.55" - wire width 16 $1\main_sdcore_crc16_inserter_crc0_crc[15:0] - attribute \src "ls180.v:1477.12-1477.59" - wire width 16 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] - attribute \src "ls180.v:1488.12-1488.55" - wire width 16 $1\main_sdcore_crc16_inserter_crc1_crc[15:0] - attribute \src "ls180.v:1484.12-1484.59" - wire width 16 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] - attribute \src "ls180.v:1495.12-1495.55" - wire width 16 $1\main_sdcore_crc16_inserter_crc2_crc[15:0] - attribute \src "ls180.v:1491.12-1491.59" - wire width 16 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] - attribute \src "ls180.v:1502.12-1502.55" - wire width 16 $1\main_sdcore_crc16_inserter_crc3_crc[15:0] - attribute \src "ls180.v:1498.12-1498.59" - wire width 16 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] - attribute \src "ls180.v:1505.12-1505.54" - wire width 16 $1\main_sdcore_crc16_inserter_crctmp0[15:0] - attribute \src "ls180.v:1844.12-1844.93" - wire width 16 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] - attribute \src "ls180.v:1845.5-1845.88" - wire $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] - attribute \src "ls180.v:1506.12-1506.54" - wire width 16 $1\main_sdcore_crc16_inserter_crctmp1[15:0] - attribute \src "ls180.v:1846.12-1846.93" - wire width 16 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] - attribute \src "ls180.v:1847.5-1847.88" - wire $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] - attribute \src "ls180.v:1507.12-1507.54" - wire width 16 $1\main_sdcore_crc16_inserter_crctmp2[15:0] - attribute \src "ls180.v:1848.12-1848.93" - wire width 16 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] - attribute \src "ls180.v:1849.5-1849.88" - wire $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] - attribute \src "ls180.v:1508.12-1508.54" - wire width 16 $1\main_sdcore_crc16_inserter_crctmp3[15:0] - attribute \src "ls180.v:1850.12-1850.93" - wire width 16 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] - attribute \src "ls180.v:1851.5-1851.88" - wire $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] - attribute \src "ls180.v:1467.5-1467.49" - wire $1\main_sdcore_crc16_inserter_sink_ready[0:0] - attribute \src "ls180.v:1474.5-1474.50" - wire $1\main_sdcore_crc16_inserter_source_last[0:0] - attribute \src "ls180.v:1475.11-1475.64" - wire width 8 $1\main_sdcore_crc16_inserter_source_payload_data[7:0] - attribute \src "ls180.v:1472.5-1472.51" - wire $1\main_sdcore_crc16_inserter_source_ready[0:0] - attribute \src "ls180.v:1471.5-1471.51" - wire $1\main_sdcore_crc16_inserter_source_valid[0:0] - attribute \src "ls180.v:1463.11-1463.47" - wire width 7 $1\main_sdcore_crc7_inserter_crc[6:0] - attribute \src "ls180.v:1421.11-1421.51" - wire width 7 $1\main_sdcore_crc7_inserter_crcreg0[6:0] - attribute \src "ls180.v:1564.12-1564.42" - wire width 32 $1\main_sdcore_data_count[31:0] - attribute \src "ls180.v:1862.12-1862.65" - wire width 32 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] - attribute \src "ls180.v:1863.5-1863.60" - wire $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] - attribute \src "ls180.v:1565.5-1565.33" - wire $1\main_sdcore_data_done[0:0] - attribute \src "ls180.v:1858.5-1858.56" - wire $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] - attribute \src "ls180.v:1859.5-1859.59" - wire $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] - attribute \src "ls180.v:1566.5-1566.34" - wire $1\main_sdcore_data_error[0:0] - attribute \src "ls180.v:1868.5-1868.57" - wire $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] - attribute \src "ls180.v:1869.5-1869.60" - wire $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] - attribute \src "ls180.v:1567.5-1567.36" - wire $1\main_sdcore_data_timeout[0:0] - attribute \src "ls180.v:1870.5-1870.59" - wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] - attribute \src "ls180.v:1871.5-1871.62" - wire $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] - attribute \src "ls180.v:1712.11-1712.48" - wire width 3 $1\main_sdmem2block_converter_mux[2:0] - attribute \src "ls180.v:1710.11-1710.64" - wire width 8 $1\main_sdmem2block_converter_source_payload_data[7:0] - attribute \src "ls180.v:1686.5-1686.40" - wire $1\main_sdmem2block_dma_base_re[0:0] - attribute \src "ls180.v:1685.12-1685.53" - wire width 64 $1\main_sdmem2block_dma_base_storage[63:0] - attribute \src "ls180.v:1684.12-1684.45" - wire width 64 $1\main_sdmem2block_dma_data[63:0] - attribute \src "ls180.v:1880.12-1880.75" - wire width 64 $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] - attribute \src "ls180.v:1881.5-1881.70" - wire $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] - attribute \src "ls180.v:1691.5-1691.44" - wire $1\main_sdmem2block_dma_done_status[0:0] - attribute \src "ls180.v:1690.5-1690.42" - wire $1\main_sdmem2block_dma_enable_re[0:0] - attribute \src "ls180.v:1689.5-1689.47" - wire $1\main_sdmem2block_dma_enable_storage[0:0] - attribute \src "ls180.v:1688.5-1688.42" - wire $1\main_sdmem2block_dma_length_re[0:0] - attribute \src "ls180.v:1687.12-1687.55" - wire width 32 $1\main_sdmem2block_dma_length_storage[31:0] - attribute \src "ls180.v:1694.5-1694.40" - wire $1\main_sdmem2block_dma_loop_re[0:0] - attribute \src "ls180.v:1693.5-1693.45" - wire $1\main_sdmem2block_dma_loop_storage[0:0] - attribute \src "ls180.v:1698.12-1698.47" - wire width 32 $1\main_sdmem2block_dma_offset[31:0] - attribute \src "ls180.v:1884.12-1884.87" - wire width 32 $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] - attribute \src "ls180.v:1885.5-1885.82" - wire $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] - attribute \src "ls180.v:1677.5-1677.42" - wire $1\main_sdmem2block_dma_sink_last[0:0] - attribute \src "ls180.v:1678.12-1678.61" - wire width 32 $1\main_sdmem2block_dma_sink_payload_address[31:0] - attribute \src "ls180.v:1676.5-1676.43" - wire $1\main_sdmem2block_dma_sink_ready[0:0] - attribute \src "ls180.v:1675.5-1675.43" - wire $1\main_sdmem2block_dma_sink_valid[0:0] - attribute \src "ls180.v:1682.5-1682.44" - wire $1\main_sdmem2block_dma_source_last[0:0] - attribute \src "ls180.v:1683.12-1683.60" - wire width 64 $1\main_sdmem2block_dma_source_payload_data[63:0] - attribute \src "ls180.v:1679.5-1679.45" - wire $1\main_sdmem2block_dma_source_valid[0:0] - attribute \src "ls180.v:1739.11-1739.47" - wire width 5 $1\main_sdmem2block_fifo_consume[4:0] - attribute \src "ls180.v:1736.11-1736.45" - wire width 6 $1\main_sdmem2block_fifo_level[5:0] - attribute \src "ls180.v:1738.11-1738.47" - wire width 5 $1\main_sdmem2block_fifo_produce[4:0] - attribute \src "ls180.v:1740.11-1740.50" - wire width 5 $1\main_sdmem2block_fifo_wrport_adr[4:0] - attribute \src "ls180.v:1120.5-1120.35" - wire $1\main_sdphy_clocker_clk0[0:0] - attribute \src "ls180.v:1123.5-1123.35" - wire $1\main_sdphy_clocker_clk1[0:0] - attribute \src "ls180.v:1124.5-1124.36" - wire $1\main_sdphy_clocker_clk_d[0:0] - attribute \src "ls180.v:1122.11-1122.41" - wire width 9 $1\main_sdphy_clocker_clks[8:0] - attribute \src "ls180.v:1118.5-1118.33" - wire $1\main_sdphy_clocker_re[0:0] - attribute \src "ls180.v:1117.11-1117.46" - wire width 9 $1\main_sdphy_clocker_storage[8:0] - attribute \src "ls180.v:1226.5-1226.49" - wire $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] - attribute \src "ls180.v:1227.5-1227.48" - wire $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] - attribute \src "ls180.v:1228.11-1228.62" - wire width 8 $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] - attribute \src "ls180.v:1224.5-1224.49" - wire $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] - attribute \src "ls180.v:1211.11-1211.54" - wire width 3 $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] - attribute \src "ls180.v:1207.5-1207.55" - wire $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] - attribute \src "ls180.v:1208.5-1208.54" - wire $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] - attribute \src "ls180.v:1209.11-1209.68" - wire width 8 $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] - attribute \src "ls180.v:1210.11-1210.81" - wire width 4 $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:1213.5-1213.53" - wire $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] - attribute \src "ls180.v:1229.5-1229.38" - wire $1\main_sdphy_cmdr_cmdr_reset[0:0] - attribute \src "ls180.v:1824.5-1824.66" - wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] - attribute \src "ls180.v:1825.5-1825.69" - wire $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] - attribute \src "ls180.v:1199.5-1199.36" - wire $1\main_sdphy_cmdr_cmdr_run[0:0] - attribute \src "ls180.v:1194.5-1194.53" - wire $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] - attribute \src "ls180.v:1181.11-1181.39" - wire width 8 $1\main_sdphy_cmdr_count[7:0] - attribute \src "ls180.v:1820.11-1820.67" - wire width 8 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] - attribute \src "ls180.v:1821.5-1821.64" - wire $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] - attribute \src "ls180.v:1166.5-1166.48" - wire $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1167.5-1167.50" - wire $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1168.5-1168.51" - wire $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1173.5-1173.37" - wire $1\main_sdphy_cmdr_sink_last[0:0] - attribute \src "ls180.v:1174.11-1174.53" - wire width 8 $1\main_sdphy_cmdr_sink_payload_length[7:0] - attribute \src "ls180.v:1172.5-1172.38" - wire $1\main_sdphy_cmdr_sink_ready[0:0] - attribute \src "ls180.v:1171.5-1171.38" - wire $1\main_sdphy_cmdr_sink_valid[0:0] - attribute \src "ls180.v:1177.5-1177.39" - wire $1\main_sdphy_cmdr_source_last[0:0] - attribute \src "ls180.v:1178.11-1178.53" - wire width 8 $1\main_sdphy_cmdr_source_payload_data[7:0] - attribute \src "ls180.v:1179.11-1179.55" - wire width 3 $1\main_sdphy_cmdr_source_payload_status[2:0] - attribute \src "ls180.v:1176.5-1176.40" - wire $1\main_sdphy_cmdr_source_ready[0:0] - attribute \src "ls180.v:1175.5-1175.40" - wire $1\main_sdphy_cmdr_source_valid[0:0] - attribute \src "ls180.v:1180.12-1180.48" - wire width 32 $1\main_sdphy_cmdr_timeout[31:0] - attribute \src "ls180.v:1822.12-1822.71" - wire width 32 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] - attribute \src "ls180.v:1823.5-1823.66" - wire $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] - attribute \src "ls180.v:1153.11-1153.39" - wire width 8 $1\main_sdphy_cmdw_count[7:0] - attribute \src "ls180.v:1816.11-1816.66" - wire width 8 $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] - attribute \src "ls180.v:1817.5-1817.63" - wire $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] - attribute \src "ls180.v:1152.5-1152.32" - wire $1\main_sdphy_cmdw_done[0:0] - attribute \src "ls180.v:1143.5-1143.48" - wire $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1144.5-1144.50" - wire $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1145.5-1145.51" - wire $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1150.5-1150.37" - wire $1\main_sdphy_cmdw_sink_last[0:0] - attribute \src "ls180.v:1151.11-1151.51" - wire width 8 $1\main_sdphy_cmdw_sink_payload_data[7:0] - attribute \src "ls180.v:1149.5-1149.38" - wire $1\main_sdphy_cmdw_sink_ready[0:0] - attribute \src "ls180.v:1148.5-1148.38" - wire $1\main_sdphy_cmdw_sink_valid[0:0] - attribute \src "ls180.v:1337.11-1337.41" - wire width 10 $1\main_sdphy_datar_count[9:0] - attribute \src "ls180.v:1836.11-1836.70" - wire width 10 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] - attribute \src "ls180.v:1837.5-1837.66" - wire $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] - attribute \src "ls180.v:1382.5-1382.51" - wire $1\main_sdphy_datar_datar_buf_source_first[0:0] - attribute \src "ls180.v:1383.5-1383.50" - wire $1\main_sdphy_datar_datar_buf_source_last[0:0] - attribute \src "ls180.v:1384.11-1384.64" - wire width 8 $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] - attribute \src "ls180.v:1380.5-1380.51" - wire $1\main_sdphy_datar_datar_buf_source_valid[0:0] - attribute \src "ls180.v:1367.5-1367.50" - wire $1\main_sdphy_datar_datar_converter_demux[0:0] - attribute \src "ls180.v:1363.5-1363.57" - wire $1\main_sdphy_datar_datar_converter_source_first[0:0] - attribute \src "ls180.v:1364.5-1364.56" - wire $1\main_sdphy_datar_datar_converter_source_last[0:0] - attribute \src "ls180.v:1365.11-1365.70" - wire width 8 $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] - attribute \src "ls180.v:1366.11-1366.83" - wire width 2 $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] - attribute \src "ls180.v:1369.5-1369.55" - wire $1\main_sdphy_datar_datar_converter_strobe_all[0:0] - attribute \src "ls180.v:1385.5-1385.40" - wire $1\main_sdphy_datar_datar_reset[0:0] - attribute \src "ls180.v:1840.5-1840.69" - wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] - attribute \src "ls180.v:1841.5-1841.72" - wire $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] - attribute \src "ls180.v:1355.5-1355.38" - wire $1\main_sdphy_datar_datar_run[0:0] - attribute \src "ls180.v:1350.5-1350.55" - wire $1\main_sdphy_datar_datar_source_source_ready0[0:0] - attribute \src "ls180.v:1320.5-1320.49" - wire $1\main_sdphy_datar_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1327.5-1327.38" - wire $1\main_sdphy_datar_sink_last[0:0] - attribute \src "ls180.v:1328.11-1328.61" - wire width 10 $1\main_sdphy_datar_sink_payload_block_length[9:0] - attribute \src "ls180.v:1326.5-1326.39" - wire $1\main_sdphy_datar_sink_ready[0:0] - attribute \src "ls180.v:1325.5-1325.39" - wire $1\main_sdphy_datar_sink_valid[0:0] - attribute \src "ls180.v:1332.5-1332.40" - wire $1\main_sdphy_datar_source_last[0:0] - attribute \src "ls180.v:1333.11-1333.54" - wire width 8 $1\main_sdphy_datar_source_payload_data[7:0] - attribute \src "ls180.v:1334.11-1334.56" - wire width 3 $1\main_sdphy_datar_source_payload_status[2:0] - attribute \src "ls180.v:1330.5-1330.41" - wire $1\main_sdphy_datar_source_ready[0:0] - attribute \src "ls180.v:1329.5-1329.41" - wire $1\main_sdphy_datar_source_valid[0:0] - attribute \src "ls180.v:1335.5-1335.33" - wire $1\main_sdphy_datar_stop[0:0] - attribute \src "ls180.v:1336.12-1336.49" - wire width 32 $1\main_sdphy_datar_timeout[31:0] - attribute \src "ls180.v:1838.12-1838.73" - wire width 32 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] - attribute \src "ls180.v:1839.5-1839.68" - wire $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] - attribute \src "ls180.v:1245.11-1245.40" - wire width 8 $1\main_sdphy_dataw_count[7:0] - attribute \src "ls180.v:1832.11-1832.61" - wire width 8 $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] - attribute \src "ls180.v:1833.5-1833.58" - wire $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] - attribute \src "ls180.v:1304.5-1304.50" - wire $1\main_sdphy_dataw_crcr_buf_source_first[0:0] - attribute \src "ls180.v:1305.5-1305.49" - wire $1\main_sdphy_dataw_crcr_buf_source_last[0:0] - attribute \src "ls180.v:1306.11-1306.63" - wire width 8 $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] - attribute \src "ls180.v:1302.5-1302.50" - wire $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] - attribute \src "ls180.v:1289.11-1289.55" - wire width 3 $1\main_sdphy_dataw_crcr_converter_demux[2:0] - attribute \src "ls180.v:1285.5-1285.56" - wire $1\main_sdphy_dataw_crcr_converter_source_first[0:0] - attribute \src "ls180.v:1286.5-1286.55" - wire $1\main_sdphy_dataw_crcr_converter_source_last[0:0] - attribute \src "ls180.v:1287.11-1287.69" - wire width 8 $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] - attribute \src "ls180.v:1288.11-1288.82" - wire width 4 $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] - attribute \src "ls180.v:1291.5-1291.54" - wire $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] - attribute \src "ls180.v:1307.5-1307.39" - wire $1\main_sdphy_dataw_crcr_reset[0:0] - attribute \src "ls180.v:1828.5-1828.66" - wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] - attribute \src "ls180.v:1829.5-1829.69" - wire $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] - attribute \src "ls180.v:1277.5-1277.37" - wire $1\main_sdphy_dataw_crcr_run[0:0] - attribute \src "ls180.v:1272.5-1272.54" - wire $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] - attribute \src "ls180.v:1259.5-1259.34" - wire $1\main_sdphy_dataw_error[0:0] - attribute \src "ls180.v:1234.5-1234.49" - wire $1\main_sdphy_dataw_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1237.11-1237.58" - wire width 4 $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1238.5-1238.53" - wire $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:1241.5-1241.39" - wire $1\main_sdphy_dataw_sink_first[0:0] - attribute \src "ls180.v:1242.5-1242.38" - wire $1\main_sdphy_dataw_sink_last[0:0] - attribute \src "ls180.v:1243.11-1243.52" - wire width 8 $1\main_sdphy_dataw_sink_payload_data[7:0] - attribute \src "ls180.v:1240.5-1240.39" - wire $1\main_sdphy_dataw_sink_ready[0:0] - attribute \src "ls180.v:1239.5-1239.39" - wire $1\main_sdphy_dataw_sink_valid[0:0] - attribute \src "ls180.v:1257.5-1257.34" - wire $1\main_sdphy_dataw_start[0:0] - attribute \src "ls180.v:1244.5-1244.33" - wire $1\main_sdphy_dataw_stop[0:0] - attribute \src "ls180.v:1258.5-1258.34" - wire $1\main_sdphy_dataw_valid[0:0] - attribute \src "ls180.v:1138.11-1138.39" - wire width 8 $1\main_sdphy_init_count[7:0] - attribute \src "ls180.v:1812.11-1812.66" - wire width 8 $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] - attribute \src "ls180.v:1813.5-1813.63" - wire $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] - attribute \src "ls180.v:1133.5-1133.48" - wire $1\main_sdphy_init_pads_out_payload_clk[0:0] - attribute \src "ls180.v:1134.5-1134.50" - wire $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] - attribute \src "ls180.v:1135.5-1135.51" - wire $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] - attribute \src "ls180.v:1136.11-1136.57" - wire width 4 $1\main_sdphy_init_pads_out_payload_data_o[3:0] - attribute \src "ls180.v:1137.5-1137.52" - wire $1\main_sdphy_init_pads_out_payload_data_oe[0:0] - attribute \src "ls180.v:1387.5-1387.35" - wire $1\main_sdphy_sdpads_cmd_i[0:0] - attribute \src "ls180.v:1390.11-1390.42" - wire width 4 $1\main_sdphy_sdpads_data_i[3:0] - attribute \src "ls180.v:332.5-332.33" - wire $1\main_sdram_address_re[0:0] - attribute \src "ls180.v:331.12-331.46" - wire width 13 $1\main_sdram_address_storage[12:0] - attribute \src "ls180.v:334.5-334.34" - wire $1\main_sdram_baddress_re[0:0] - attribute \src "ls180.v:333.11-333.45" - wire width 2 $1\main_sdram_baddress_storage[1:0] - attribute \src "ls180.v:430.5-430.50" - wire $1\main_sdram_bankmachine0_auto_precharge[0:0] - attribute \src "ls180.v:452.11-452.70" - wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:449.11-449.68" - wire width 4 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:451.11-451.70" - wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:453.11-453.73" - wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:476.5-476.59" - wire $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:477.5-477.58" - wire $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:479.12-479.74" - wire width 22 $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:478.5-478.64" - wire $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:474.5-474.59" - wire $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:422.12-422.57" - wire width 13 $1\main_sdram_bankmachine0_cmd_payload_a[12:0] - attribute \src "ls180.v:424.5-424.51" - wire $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] - attribute \src "ls180.v:427.5-427.54" - wire $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:428.5-428.55" - wire $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] - attribute \src "ls180.v:429.5-429.56" - wire $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] - attribute \src "ls180.v:425.5-425.51" - wire $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] - attribute \src "ls180.v:426.5-426.50" - wire $1\main_sdram_bankmachine0_cmd_payload_we[0:0] - attribute \src "ls180.v:421.5-421.45" - wire $1\main_sdram_bankmachine0_cmd_ready[0:0] - attribute \src "ls180.v:420.5-420.45" - wire $1\main_sdram_bankmachine0_cmd_valid[0:0] - attribute \src "ls180.v:419.5-419.47" - wire $1\main_sdram_bankmachine0_refresh_gnt[0:0] - attribute \src "ls180.v:417.5-417.51" - wire $1\main_sdram_bankmachine0_req_rdata_valid[0:0] - attribute \src "ls180.v:416.5-416.51" - wire $1\main_sdram_bankmachine0_req_wdata_ready[0:0] - attribute \src "ls180.v:480.12-480.47" - wire width 13 $1\main_sdram_bankmachine0_row[12:0] - attribute \src "ls180.v:484.5-484.45" - wire $1\main_sdram_bankmachine0_row_close[0:0] - attribute \src "ls180.v:485.5-485.54" - wire $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:483.5-483.44" - wire $1\main_sdram_bankmachine0_row_open[0:0] - attribute \src "ls180.v:481.5-481.46" - wire $1\main_sdram_bankmachine0_row_opened[0:0] - attribute \src "ls180.v:488.11-488.55" - wire width 3 $1\main_sdram_bankmachine0_twtpcon_count[2:0] - attribute \src "ls180.v:487.32-487.76" - wire $1\main_sdram_bankmachine0_twtpcon_ready[0:0] - attribute \src "ls180.v:512.5-512.50" - wire $1\main_sdram_bankmachine1_auto_precharge[0:0] - attribute \src "ls180.v:534.11-534.70" - wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:531.11-531.68" - wire width 4 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:533.11-533.70" - wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:535.11-535.73" - wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:558.5-558.59" - wire $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:559.5-559.58" - wire $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:561.12-561.74" - wire width 22 $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:560.5-560.64" - wire $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:556.5-556.59" - wire $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:504.12-504.57" - wire width 13 $1\main_sdram_bankmachine1_cmd_payload_a[12:0] - attribute \src "ls180.v:506.5-506.51" - wire $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] - attribute \src "ls180.v:509.5-509.54" - wire $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:510.5-510.55" - wire $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] - attribute \src "ls180.v:511.5-511.56" - wire $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] - attribute \src "ls180.v:507.5-507.51" - wire $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] - attribute \src "ls180.v:508.5-508.50" - wire $1\main_sdram_bankmachine1_cmd_payload_we[0:0] - attribute \src "ls180.v:503.5-503.45" - wire $1\main_sdram_bankmachine1_cmd_ready[0:0] - attribute \src "ls180.v:502.5-502.45" - wire $1\main_sdram_bankmachine1_cmd_valid[0:0] - attribute \src "ls180.v:501.5-501.47" - wire $1\main_sdram_bankmachine1_refresh_gnt[0:0] - attribute \src "ls180.v:499.5-499.51" - wire $1\main_sdram_bankmachine1_req_rdata_valid[0:0] - attribute \src "ls180.v:498.5-498.51" - wire $1\main_sdram_bankmachine1_req_wdata_ready[0:0] - attribute \src "ls180.v:562.12-562.47" - wire width 13 $1\main_sdram_bankmachine1_row[12:0] - attribute \src "ls180.v:566.5-566.45" - wire $1\main_sdram_bankmachine1_row_close[0:0] - attribute \src "ls180.v:567.5-567.54" - wire $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:565.5-565.44" - wire $1\main_sdram_bankmachine1_row_open[0:0] - attribute \src "ls180.v:563.5-563.46" - wire $1\main_sdram_bankmachine1_row_opened[0:0] - attribute \src "ls180.v:570.11-570.55" - wire width 3 $1\main_sdram_bankmachine1_twtpcon_count[2:0] - attribute \src "ls180.v:569.32-569.76" - wire $1\main_sdram_bankmachine1_twtpcon_ready[0:0] - attribute \src "ls180.v:594.5-594.50" - wire $1\main_sdram_bankmachine2_auto_precharge[0:0] - attribute \src "ls180.v:616.11-616.70" - wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:613.11-613.68" - wire width 4 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:615.11-615.70" - wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:617.11-617.73" - wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:640.5-640.59" - wire $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:641.5-641.58" - wire $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:643.12-643.74" - wire width 22 $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:642.5-642.64" - wire $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:638.5-638.59" - wire $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:586.12-586.57" - wire width 13 $1\main_sdram_bankmachine2_cmd_payload_a[12:0] - attribute \src "ls180.v:588.5-588.51" - wire $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] - attribute \src "ls180.v:591.5-591.54" - wire $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:592.5-592.55" - wire $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] - attribute \src "ls180.v:593.5-593.56" - wire $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] - attribute \src "ls180.v:589.5-589.51" - wire $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] - attribute \src "ls180.v:590.5-590.50" - wire $1\main_sdram_bankmachine2_cmd_payload_we[0:0] - attribute \src "ls180.v:585.5-585.45" - wire $1\main_sdram_bankmachine2_cmd_ready[0:0] - attribute \src "ls180.v:584.5-584.45" - wire $1\main_sdram_bankmachine2_cmd_valid[0:0] - attribute \src "ls180.v:583.5-583.47" - wire $1\main_sdram_bankmachine2_refresh_gnt[0:0] - attribute \src "ls180.v:581.5-581.51" - wire $1\main_sdram_bankmachine2_req_rdata_valid[0:0] - attribute \src "ls180.v:580.5-580.51" - wire $1\main_sdram_bankmachine2_req_wdata_ready[0:0] - attribute \src "ls180.v:644.12-644.47" - wire width 13 $1\main_sdram_bankmachine2_row[12:0] - attribute \src "ls180.v:648.5-648.45" - wire $1\main_sdram_bankmachine2_row_close[0:0] - attribute \src "ls180.v:649.5-649.54" - wire $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:647.5-647.44" - wire $1\main_sdram_bankmachine2_row_open[0:0] - attribute \src "ls180.v:645.5-645.46" - wire $1\main_sdram_bankmachine2_row_opened[0:0] - attribute \src "ls180.v:652.11-652.55" - wire width 3 $1\main_sdram_bankmachine2_twtpcon_count[2:0] - attribute \src "ls180.v:651.32-651.76" - wire $1\main_sdram_bankmachine2_twtpcon_ready[0:0] - attribute \src "ls180.v:676.5-676.50" - wire $1\main_sdram_bankmachine3_auto_precharge[0:0] - attribute \src "ls180.v:698.11-698.70" - wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] - attribute \src "ls180.v:695.11-695.68" - wire width 4 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] - attribute \src "ls180.v:697.11-697.70" - wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] - attribute \src "ls180.v:699.11-699.73" - wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] - attribute \src "ls180.v:722.5-722.59" - wire $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] - attribute \src "ls180.v:723.5-723.58" - wire $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] - attribute \src "ls180.v:725.12-725.74" - wire width 22 $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] - attribute \src "ls180.v:724.5-724.64" - wire $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] - attribute \src "ls180.v:720.5-720.59" - wire $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] - attribute \src "ls180.v:668.12-668.57" - wire width 13 $1\main_sdram_bankmachine3_cmd_payload_a[12:0] - attribute \src "ls180.v:670.5-670.51" - wire $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] - attribute \src "ls180.v:673.5-673.54" - wire $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] - attribute \src "ls180.v:674.5-674.55" - wire $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] - attribute \src "ls180.v:675.5-675.56" - wire $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] - attribute \src "ls180.v:671.5-671.51" - wire $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] - attribute \src "ls180.v:672.5-672.50" - wire $1\main_sdram_bankmachine3_cmd_payload_we[0:0] - attribute \src "ls180.v:667.5-667.45" - wire $1\main_sdram_bankmachine3_cmd_ready[0:0] - attribute \src "ls180.v:666.5-666.45" - wire $1\main_sdram_bankmachine3_cmd_valid[0:0] - attribute \src "ls180.v:665.5-665.47" - wire $1\main_sdram_bankmachine3_refresh_gnt[0:0] - attribute \src "ls180.v:663.5-663.51" - wire $1\main_sdram_bankmachine3_req_rdata_valid[0:0] - attribute \src "ls180.v:662.5-662.51" - wire $1\main_sdram_bankmachine3_req_wdata_ready[0:0] - attribute \src "ls180.v:726.12-726.47" - wire width 13 $1\main_sdram_bankmachine3_row[12:0] - attribute \src "ls180.v:730.5-730.45" - wire $1\main_sdram_bankmachine3_row_close[0:0] - attribute \src "ls180.v:731.5-731.54" - wire $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] - attribute \src "ls180.v:729.5-729.44" - wire $1\main_sdram_bankmachine3_row_open[0:0] - attribute \src "ls180.v:727.5-727.46" - wire $1\main_sdram_bankmachine3_row_opened[0:0] - attribute \src "ls180.v:734.11-734.55" - wire width 3 $1\main_sdram_bankmachine3_twtpcon_count[2:0] - attribute \src "ls180.v:733.32-733.76" - wire $1\main_sdram_bankmachine3_twtpcon_ready[0:0] - attribute \src "ls180.v:749.5-749.49" - wire $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] - attribute \src "ls180.v:750.5-750.49" - wire $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] - attribute \src "ls180.v:751.5-751.48" - wire $1\main_sdram_choose_cmd_cmd_payload_we[0:0] - attribute \src "ls180.v:757.11-757.45" - wire width 2 $1\main_sdram_choose_cmd_grant[1:0] - attribute \src "ls180.v:755.11-755.46" - wire width 4 $1\main_sdram_choose_cmd_valids[3:0] - attribute \src "ls180.v:767.5-767.49" - wire $1\main_sdram_choose_req_cmd_payload_cas[0:0] - attribute \src "ls180.v:768.5-768.49" - wire $1\main_sdram_choose_req_cmd_payload_ras[0:0] - attribute \src "ls180.v:769.5-769.48" - wire $1\main_sdram_choose_req_cmd_payload_we[0:0] - attribute \src "ls180.v:764.5-764.43" - wire $1\main_sdram_choose_req_cmd_ready[0:0] - attribute \src "ls180.v:775.11-775.45" - wire width 2 $1\main_sdram_choose_req_grant[1:0] - attribute \src "ls180.v:773.11-773.46" - wire width 4 $1\main_sdram_choose_req_valids[3:0] - attribute \src "ls180.v:762.5-762.48" - wire $1\main_sdram_choose_req_want_activates[0:0] - attribute \src "ls180.v:759.5-759.44" - wire $1\main_sdram_choose_req_want_reads[0:0] - attribute \src "ls180.v:760.5-760.45" - wire $1\main_sdram_choose_req_want_writes[0:0] - attribute \src "ls180.v:388.5-388.31" - wire $1\main_sdram_cmd_last[0:0] - attribute \src "ls180.v:389.12-389.44" - wire width 13 $1\main_sdram_cmd_payload_a[12:0] - attribute \src "ls180.v:390.11-390.43" - wire width 2 $1\main_sdram_cmd_payload_ba[1:0] - attribute \src "ls180.v:391.5-391.38" - wire $1\main_sdram_cmd_payload_cas[0:0] - attribute \src "ls180.v:392.5-392.38" - wire $1\main_sdram_cmd_payload_ras[0:0] - attribute \src "ls180.v:393.5-393.37" - wire $1\main_sdram_cmd_payload_we[0:0] - attribute \src "ls180.v:387.5-387.32" - wire $1\main_sdram_cmd_ready[0:0] - attribute \src "ls180.v:386.5-386.32" - wire $1\main_sdram_cmd_valid[0:0] - attribute \src "ls180.v:326.5-326.33" - wire $1\main_sdram_command_re[0:0] - attribute \src "ls180.v:325.11-325.44" - wire width 6 $1\main_sdram_command_storage[5:0] - attribute \src "ls180.v:370.12-370.45" - wire width 13 $1\main_sdram_dfi_p0_address[12:0] - attribute \src "ls180.v:371.11-371.40" - wire width 2 $1\main_sdram_dfi_p0_bank[1:0] - attribute \src "ls180.v:372.5-372.35" - wire $1\main_sdram_dfi_p0_cas_n[0:0] - attribute \src "ls180.v:373.5-373.34" - wire $1\main_sdram_dfi_p0_cs_n[0:0] - attribute \src "ls180.v:374.5-374.35" - wire $1\main_sdram_dfi_p0_ras_n[0:0] - attribute \src "ls180.v:383.5-383.39" - wire $1\main_sdram_dfi_p0_rddata_en[0:0] - attribute \src "ls180.v:375.5-375.34" - wire $1\main_sdram_dfi_p0_we_n[0:0] - attribute \src "ls180.v:381.5-381.39" - wire $1\main_sdram_dfi_p0_wrdata_en[0:0] - attribute \src "ls180.v:794.5-794.26" - wire $1\main_sdram_en0[0:0] - attribute \src "ls180.v:797.5-797.26" - wire $1\main_sdram_en1[0:0] - attribute \src "ls180.v:367.12-367.46" - wire width 16 $1\main_sdram_interface_wdata[15:0] - attribute \src "ls180.v:368.11-368.47" - wire width 2 $1\main_sdram_interface_wdata_we[1:0] - attribute \src "ls180.v:273.5-273.36" - wire $1\main_sdram_inti_p0_cas_n[0:0] - attribute \src "ls180.v:274.5-274.35" - wire $1\main_sdram_inti_p0_cs_n[0:0] - attribute \src "ls180.v:275.5-275.36" - wire $1\main_sdram_inti_p0_ras_n[0:0] - attribute \src "ls180.v:285.12-285.45" - wire width 16 $1\main_sdram_inti_p0_rddata[15:0] - attribute \src "ls180.v:286.5-286.43" - wire $1\main_sdram_inti_p0_rddata_valid[0:0] - attribute \src "ls180.v:276.5-276.35" - wire $1\main_sdram_inti_p0_we_n[0:0] - attribute \src "ls180.v:312.5-312.38" - wire $1\main_sdram_master_p0_act_n[0:0] - attribute \src "ls180.v:303.12-303.48" - wire width 13 $1\main_sdram_master_p0_address[12:0] - attribute \src "ls180.v:304.11-304.43" - wire width 2 $1\main_sdram_master_p0_bank[1:0] - attribute \src "ls180.v:305.5-305.38" - wire $1\main_sdram_master_p0_cas_n[0:0] - attribute \src "ls180.v:309.5-309.36" - wire $1\main_sdram_master_p0_cke[0:0] - attribute \src "ls180.v:306.5-306.37" - wire $1\main_sdram_master_p0_cs_n[0:0] - attribute \src "ls180.v:310.5-310.36" - wire $1\main_sdram_master_p0_odt[0:0] - attribute \src "ls180.v:307.5-307.38" - wire $1\main_sdram_master_p0_ras_n[0:0] - attribute \src "ls180.v:316.5-316.42" - wire $1\main_sdram_master_p0_rddata_en[0:0] - attribute \src "ls180.v:311.5-311.40" - wire $1\main_sdram_master_p0_reset_n[0:0] - attribute \src "ls180.v:308.5-308.37" - wire $1\main_sdram_master_p0_we_n[0:0] - attribute \src "ls180.v:313.12-313.47" - wire width 16 $1\main_sdram_master_p0_wrdata[15:0] - attribute \src "ls180.v:314.5-314.42" - wire $1\main_sdram_master_p0_wrdata_en[0:0] - attribute \src "ls180.v:315.11-315.50" - wire width 2 $1\main_sdram_master_p0_wrdata_mask[1:0] - attribute \src "ls180.v:404.5-404.38" - wire $1\main_sdram_postponer_count[0:0] - attribute \src "ls180.v:403.5-403.38" - wire $1\main_sdram_postponer_req_o[0:0] - attribute \src "ls180.v:324.5-324.25" - wire $1\main_sdram_re[0:0] - attribute \src "ls180.v:410.5-410.38" - wire $1\main_sdram_sequencer_count[0:0] - attribute \src "ls180.v:409.11-409.46" - wire width 4 $1\main_sdram_sequencer_counter[3:0] - attribute \src "ls180.v:408.5-408.38" - wire $1\main_sdram_sequencer_done1[0:0] - attribute \src "ls180.v:405.5-405.39" - wire $1\main_sdram_sequencer_start0[0:0] - attribute \src "ls180.v:301.12-301.46" - wire width 16 $1\main_sdram_slave_p0_rddata[15:0] - attribute \src "ls180.v:302.5-302.44" - wire $1\main_sdram_slave_p0_rddata_valid[0:0] - attribute \src "ls180.v:337.12-337.37" - wire width 16 $1\main_sdram_status[15:0] - attribute \src "ls180.v:779.11-779.40" - wire width 2 $1\main_sdram_steerer_sel[1:0] - attribute \src "ls180.v:323.11-323.36" - wire width 4 $1\main_sdram_storage[3:0] - attribute \src "ls180.v:788.5-788.36" - wire $1\main_sdram_tccdcon_count[0:0] - attribute \src "ls180.v:787.32-787.63" - wire $1\main_sdram_tccdcon_ready[0:0] - attribute \src "ls180.v:796.11-796.34" - wire width 5 $1\main_sdram_time0[4:0] - attribute \src "ls180.v:799.11-799.34" - wire width 4 $1\main_sdram_time1[3:0] - attribute \src "ls180.v:401.11-401.44" - wire width 10 $1\main_sdram_timer_count1[9:0] - attribute \src "ls180.v:791.11-791.42" - wire width 3 $1\main_sdram_twtrcon_count[2:0] - attribute \src "ls180.v:790.32-790.63" - wire $1\main_sdram_twtrcon_ready[0:0] - attribute \src "ls180.v:336.5-336.32" - wire $1\main_sdram_wrdata_re[0:0] - attribute \src "ls180.v:335.12-335.45" - wire width 16 $1\main_sdram_wrdata_storage[15:0] - attribute \src "ls180.v:828.5-828.54" - wire $1\main_socbushandler_converted_interface_ack[0:0] - attribute \src "ls180.v:834.5-834.38" - wire $1\main_socbushandler_counter[0:0] - attribute \src "ls180.v:1763.5-1763.60" - wire $1\main_socbushandler_counter_converter2_next_value[0:0] - attribute \src "ls180.v:1764.5-1764.63" - wire $1\main_socbushandler_counter_converter2_next_value_ce[0:0] - attribute \src "ls180.v:836.12-836.44" - wire width 64 $1\main_socbushandler_dat_r[63:0] - attribute \src "ls180.v:833.5-833.35" - wire $1\main_socbushandler_skip[0:0] - attribute \src "ls180.v:1022.12-1022.44" - wire width 16 $1\main_spimaster11_storage[15:0] - attribute \src "ls180.v:1023.5-1023.31" - wire $1\main_spimaster12_re[0:0] - attribute \src "ls180.v:1027.11-1027.42" - wire width 8 $1\main_spimaster16_storage[7:0] - attribute \src "ls180.v:1028.5-1028.31" - wire $1\main_spimaster17_re[0:0] - attribute \src "ls180.v:1084.5-1084.30" - wire $1\main_spimaster1_re[0:0] - attribute \src "ls180.v:1083.12-1083.45" - wire width 16 $1\main_spimaster1_storage[15:0] - attribute \src "ls180.v:1032.5-1032.36" - wire $1\main_spimaster21_storage[0:0] - attribute \src "ls180.v:1033.5-1033.31" - wire $1\main_spimaster22_re[0:0] - attribute \src "ls180.v:1034.5-1034.36" - wire $1\main_spimaster23_storage[0:0] - attribute \src "ls180.v:1035.5-1035.31" - wire $1\main_spimaster24_re[0:0] - attribute \src "ls180.v:1036.5-1036.39" - wire $1\main_spimaster25_clk_enable[0:0] - attribute \src "ls180.v:1037.5-1037.38" - wire $1\main_spimaster26_cs_enable[0:0] - attribute \src "ls180.v:1038.11-1038.40" - wire width 3 $1\main_spimaster27_count[2:0] - attribute \src "ls180.v:1804.11-1804.62" - wire width 3 $1\main_spimaster27_count_spimaster0_next_value[2:0] - attribute \src "ls180.v:1805.5-1805.59" - wire $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] - attribute \src "ls180.v:1039.5-1039.39" - wire $1\main_spimaster28_mosi_latch[0:0] - attribute \src "ls180.v:1040.5-1040.39" - wire $1\main_spimaster29_miso_latch[0:0] - attribute \src "ls180.v:1013.5-1013.32" - wire $1\main_spimaster2_done[0:0] - attribute \src "ls180.v:1041.12-1041.48" - wire width 16 $1\main_spimaster30_clk_divider[15:0] - attribute \src "ls180.v:1044.11-1044.44" - wire width 8 $1\main_spimaster33_mosi_data[7:0] - attribute \src "ls180.v:1045.11-1045.43" - wire width 3 $1\main_spimaster34_mosi_sel[2:0] - attribute \src "ls180.v:1046.11-1046.44" - wire width 8 $1\main_spimaster35_miso_data[7:0] - attribute \src "ls180.v:1014.5-1014.31" - wire $1\main_spimaster3_irq[0:0] - attribute \src "ls180.v:1016.11-1016.38" - wire width 8 $1\main_spimaster5_miso[7:0] - attribute \src "ls180.v:1020.5-1020.33" - wire $1\main_spimaster9_start[0:0] - attribute \src "ls180.v:1077.12-1077.47" - wire width 16 $1\main_spisdcard_clk_divider1[15:0] - attribute \src "ls180.v:1072.5-1072.37" - wire $1\main_spisdcard_clk_enable[0:0] - attribute \src "ls180.v:1059.5-1059.37" - wire $1\main_spisdcard_control_re[0:0] - attribute \src "ls180.v:1058.12-1058.50" - wire width 16 $1\main_spisdcard_control_storage[15:0] - attribute \src "ls180.v:1074.11-1074.38" - wire width 3 $1\main_spisdcard_count[2:0] - attribute \src "ls180.v:1808.11-1808.60" - wire width 3 $1\main_spisdcard_count_spimaster1_next_value[2:0] - attribute \src "ls180.v:1809.5-1809.57" - wire $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] - attribute \src "ls180.v:1073.5-1073.36" - wire $1\main_spisdcard_cs_enable[0:0] - attribute \src "ls180.v:1069.5-1069.32" - wire $1\main_spisdcard_cs_re[0:0] - attribute \src "ls180.v:1068.5-1068.37" - wire $1\main_spisdcard_cs_storage[0:0] - attribute \src "ls180.v:1049.5-1049.32" - wire $1\main_spisdcard_done0[0:0] - attribute \src "ls180.v:1050.5-1050.30" - wire $1\main_spisdcard_irq[0:0] - attribute \src "ls180.v:1071.5-1071.38" - wire $1\main_spisdcard_loopback_re[0:0] - attribute \src "ls180.v:1070.5-1070.43" - wire $1\main_spisdcard_loopback_storage[0:0] - attribute \src "ls180.v:1052.11-1052.37" - wire width 8 $1\main_spisdcard_miso[7:0] - attribute \src "ls180.v:1082.11-1082.42" - wire width 8 $1\main_spisdcard_miso_data[7:0] - attribute \src "ls180.v:1076.5-1076.37" - wire $1\main_spisdcard_miso_latch[0:0] - attribute \src "ls180.v:1080.11-1080.42" - wire width 8 $1\main_spisdcard_mosi_data[7:0] - attribute \src "ls180.v:1075.5-1075.37" - wire $1\main_spisdcard_mosi_latch[0:0] - attribute \src "ls180.v:1064.5-1064.34" - wire $1\main_spisdcard_mosi_re[0:0] - attribute \src "ls180.v:1081.11-1081.41" - wire width 3 $1\main_spisdcard_mosi_sel[2:0] - attribute \src "ls180.v:1063.11-1063.45" - wire width 8 $1\main_spisdcard_mosi_storage[7:0] - attribute \src "ls180.v:1056.5-1056.33" - wire $1\main_spisdcard_start1[0:0] - attribute \src "ls180.v:904.11-904.50" - wire width 2 $1\main_uart_eventmanager_pending_w[1:0] - attribute \src "ls180.v:906.5-906.37" - wire $1\main_uart_eventmanager_re[0:0] - attribute \src "ls180.v:900.11-900.49" - wire width 2 $1\main_uart_eventmanager_status_w[1:0] - attribute \src "ls180.v:905.11-905.48" - wire width 2 $1\main_uart_eventmanager_storage[1:0] - attribute \src "ls180.v:872.12-872.54" - wire width 32 $1\main_uart_phy_phase_accumulator_rx[31:0] - attribute \src "ls180.v:862.12-862.54" - wire width 32 $1\main_uart_phy_phase_accumulator_tx[31:0] + attribute \src "ls180.v:1886.1-1916.4" + wire $0\sdram_cmd_last[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 13 $0\sdram_cmd_payload_a[12:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 2 $0\sdram_cmd_payload_ba[1:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_cmd_payload_cas[0:0] + attribute \src "ls180.v:372.5-372.37" + wire $0\sdram_cmd_payload_is_read[0:0] + attribute \src "ls180.v:373.5-373.38" + wire $0\sdram_cmd_payload_is_write[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_cmd_payload_ras[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_cmd_payload_we[0:0] + attribute \src "ls180.v:2669.1-2741.4" + wire $0\sdram_cmd_ready[0:0] + attribute \src "ls180.v:1886.1-1916.4" + wire $0\sdram_cmd_valid[0:0] + attribute \src "ls180.v:308.5-308.33" + wire $0\sdram_command_issue_w[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_command_re[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 6 $0\sdram_command_storage[5:0] + attribute \src "ls180.v:357.5-357.30" + wire $0\sdram_dfi_p0_act_n[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 13 $0\sdram_dfi_p0_address[12:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 2 $0\sdram_dfi_p0_bank[1:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_dfi_p0_cas_n[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_dfi_p0_cs_n[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_dfi_p0_ras_n[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_dfi_p0_rddata_en[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_dfi_p0_we_n[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_dfi_p0_wrdata_en[0:0] + attribute \src "ls180.v:2669.1-2741.4" + wire $0\sdram_en0[0:0] + attribute \src "ls180.v:2669.1-2741.4" + wire $0\sdram_en1[0:0] + attribute \src "ls180.v:2765.1-2778.4" + wire width 16 $0\sdram_interface_wdata[15:0] + attribute \src "ls180.v:2765.1-2778.4" + wire width 2 $0\sdram_interface_wdata_we[1:0] + attribute \src "ls180.v:258.5-258.31" + wire $0\sdram_inti_p0_act_n[0:0] + attribute \src "ls180.v:1827.1-1843.4" + wire $0\sdram_inti_p0_cas_n[0:0] + attribute \src "ls180.v:1827.1-1843.4" + wire $0\sdram_inti_p0_cs_n[0:0] + attribute \src "ls180.v:1827.1-1843.4" + wire $0\sdram_inti_p0_ras_n[0:0] + attribute \src "ls180.v:1769.1-1823.4" + wire width 16 $0\sdram_inti_p0_rddata[15:0] + attribute \src "ls180.v:1769.1-1823.4" + wire $0\sdram_inti_p0_rddata_valid[0:0] + attribute \src "ls180.v:1827.1-1843.4" + wire $0\sdram_inti_p0_we_n[0:0] + attribute \src "ls180.v:1769.1-1823.4" + wire $0\sdram_master_p0_act_n[0:0] + attribute \src "ls180.v:1769.1-1823.4" + wire width 13 $0\sdram_master_p0_address[12:0] + attribute \src "ls180.v:1769.1-1823.4" + wire width 2 $0\sdram_master_p0_bank[1:0] + attribute \src "ls180.v:1769.1-1823.4" + wire $0\sdram_master_p0_cas_n[0:0] + attribute \src "ls180.v:1769.1-1823.4" + wire $0\sdram_master_p0_cke[0:0] + attribute \src "ls180.v:1769.1-1823.4" + wire $0\sdram_master_p0_cs_n[0:0] + attribute \src "ls180.v:1769.1-1823.4" + wire $0\sdram_master_p0_odt[0:0] + attribute \src "ls180.v:1769.1-1823.4" + wire $0\sdram_master_p0_ras_n[0:0] + attribute \src "ls180.v:1769.1-1823.4" + wire $0\sdram_master_p0_rddata_en[0:0] + attribute \src "ls180.v:1769.1-1823.4" + wire $0\sdram_master_p0_reset_n[0:0] + attribute \src "ls180.v:1769.1-1823.4" + wire $0\sdram_master_p0_we_n[0:0] + attribute \src "ls180.v:1769.1-1823.4" + wire width 16 $0\sdram_master_p0_wrdata[15:0] + attribute \src "ls180.v:1769.1-1823.4" + wire $0\sdram_master_p0_wrdata_en[0:0] + attribute \src "ls180.v:1769.1-1823.4" + wire width 2 $0\sdram_master_p0_wrdata_mask[1:0] + attribute \src "ls180.v:755.12-755.31" + wire width 13 $0\sdram_nop_a[12:0] + attribute \src "ls180.v:756.11-756.30" + wire width 2 $0\sdram_nop_ba[1:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_postponer_count[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_postponer_req_o[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_re[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_sequencer_count[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 4 $0\sdram_sequencer_counter[3:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_sequencer_done1[0:0] + attribute \src "ls180.v:1886.1-1916.4" + wire $0\sdram_sequencer_start0[0:0] + attribute \src "ls180.v:1769.1-1823.4" + wire width 16 $0\sdram_slave_p0_rddata[15:0] + attribute \src "ls180.v:1769.1-1823.4" + wire $0\sdram_slave_p0_rddata_valid[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 16 $0\sdram_status[15:0] + attribute \src "ls180.v:758.5-758.26" + wire $0\sdram_steerer0[0:0] + attribute \src "ls180.v:759.5-759.26" + wire $0\sdram_steerer1[0:0] + attribute \src "ls180.v:2669.1-2741.4" + wire width 2 $0\sdram_steerer_sel[1:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 4 $0\sdram_storage[3:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_tccdcon_count[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_tccdcon_ready[0:0] + attribute \src "ls180.v:763.32-763.58" + wire $0\sdram_tfawcon_ready[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 5 $0\sdram_time0[4:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 4 $0\sdram_time1[3:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 10 $0\sdram_timer_count1[9:0] + attribute \src "ls180.v:761.32-761.58" + wire $0\sdram_trrdcon_ready[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 3 $0\sdram_twtrcon_count[2:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_twtrcon_ready[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\sdram_wrdata_re[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 16 $0\sdram_wrdata_storage[15:0] + attribute \src "ls180.v:1646.1-1692.4" + wire $0\socbushandler_converted_interface_ack[0:0] + attribute \src "ls180.v:810.5-810.49" + wire $0\socbushandler_converted_interface_err[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\socbushandler_counter[0:0] + attribute \src "ls180.v:1646.1-1692.4" + wire $0\socbushandler_counter_subfragments_converter2_next_value[0:0] + attribute \src "ls180.v:1646.1-1692.4" + wire $0\socbushandler_counter_subfragments_converter2_next_value_ce[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 64 $0\socbushandler_dat_r[63:0] + attribute \src "ls180.v:1646.1-1692.4" + wire $0\socbushandler_skip[0:0] + attribute \src "ls180.v:1980.1-2073.4" + wire width 3 $0\subfragments_bankmachine0_next_state[2:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 3 $0\subfragments_bankmachine0_state[2:0] + attribute \src "ls180.v:2137.1-2230.4" + wire width 3 $0\subfragments_bankmachine1_next_state[2:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 3 $0\subfragments_bankmachine1_state[2:0] + attribute \src "ls180.v:2294.1-2387.4" + wire width 3 $0\subfragments_bankmachine2_next_state[2:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 3 $0\subfragments_bankmachine2_state[2:0] + attribute \src "ls180.v:2451.1-2544.4" + wire width 3 $0\subfragments_bankmachine3_next_state[2:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 3 $0\subfragments_bankmachine3_state[2:0] + attribute \src "ls180.v:1526.1-1572.4" + wire $0\subfragments_converter0_next_state[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\subfragments_converter0_state[0:0] + attribute \src "ls180.v:1586.1-1632.4" + wire $0\subfragments_converter1_next_state[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\subfragments_converter1_state[0:0] + attribute \src "ls180.v:1646.1-1692.4" + wire $0\subfragments_converter2_next_state[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\subfragments_converter2_state[0:0] + attribute \src "ls180.v:1038.5-1038.32" + wire $0\subfragments_locked0[0:0] + attribute \src "ls180.v:1039.5-1039.32" + wire $0\subfragments_locked1[0:0] + attribute \src "ls180.v:1040.5-1040.32" + wire $0\subfragments_locked2[0:0] + attribute \src "ls180.v:1041.5-1041.32" + wire $0\subfragments_locked3[0:0] + attribute \src "ls180.v:2669.1-2741.4" + wire width 3 $0\subfragments_multiplexer_next_state[2:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 3 $0\subfragments_multiplexer_state[2:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\subfragments_new_master_rdata_valid0[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\subfragments_new_master_rdata_valid1[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\subfragments_new_master_rdata_valid2[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\subfragments_new_master_rdata_valid3[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\subfragments_new_master_wdata_ready[0:0] + attribute \src "ls180.v:2797.1-2843.4" + wire $0\subfragments_next_state[0:0] + attribute \src "ls180.v:1886.1-1916.4" + wire width 2 $0\subfragments_refresher_next_state[1:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 2 $0\subfragments_refresher_state[1:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\subfragments_state[0:0] + attribute \src "ls180.v:3539.1-3555.4" + wire $0\t_array_muxed0[0:0] + attribute \src "ls180.v:3556.1-3572.4" + wire $0\t_array_muxed1[0:0] + attribute \src "ls180.v:3573.1-3589.4" + wire $0\t_array_muxed2[0:0] + attribute \src "ls180.v:3692.1-3708.4" + wire $0\t_array_muxed3[0:0] + attribute \src "ls180.v:3709.1-3725.4" + wire $0\t_array_muxed4[0:0] + attribute \src "ls180.v:3726.1-3742.4" + wire $0\t_array_muxed5[0:0] + attribute \src "ls180.v:2888.1-2893.4" + wire $0\tx_clear[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 4 $0\tx_fifo_consume[3:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 5 $0\tx_fifo_level0[4:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 4 $0\tx_fifo_produce[3:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\tx_fifo_readable[0:0] + attribute \src "ls180.v:918.5-918.27" + wire $0\tx_fifo_replace[0:0] + attribute \src "ls180.v:901.5-901.30" + wire $0\tx_fifo_sink_first[0:0] + attribute \src "ls180.v:902.5-902.29" + wire $0\tx_fifo_sink_last[0:0] + attribute \src "ls180.v:2927.1-2934.4" + wire width 4 $0\tx_fifo_wrport_adr[3:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\tx_old_trigger[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\tx_pending[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 32 $0\uart_phy_phase_accumulator_rx[31:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 32 $0\uart_phy_phase_accumulator_tx[31:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\uart_phy_re[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 4 $0\uart_phy_rx_bitcount[3:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\uart_phy_rx_busy[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\uart_phy_rx_r[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 8 $0\uart_phy_rx_reg[7:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\uart_phy_sink_ready[0:0] + attribute \src "ls180.v:846.5-846.33" + wire $0\uart_phy_source_first[0:0] + attribute \src "ls180.v:847.5-847.32" + wire $0\uart_phy_source_last[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 8 $0\uart_phy_source_payload_data[7:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\uart_phy_source_valid[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 32 $0\uart_phy_storage[31:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 4 $0\uart_phy_tx_bitcount[3:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\uart_phy_tx_busy[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire width 8 $0\uart_phy_tx_reg[7:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\uart_phy_uart_clk_rxen[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\uart_phy_uart_clk_txen[0:0] + attribute \src "ls180.v:2797.1-2843.4" + wire $0\wb_sdram_ack[0:0] + attribute \src "ls180.v:1646.1-1692.4" + wire width 30 $0\wb_sdram_adr[29:0] + attribute \src "ls180.v:1646.1-1692.4" + wire $0\wb_sdram_cyc[0:0] + attribute \src "ls180.v:1634.1-1644.4" + wire width 32 $0\wb_sdram_dat_w[31:0] + attribute \src "ls180.v:1646.1-1692.4" + wire width 4 $0\wb_sdram_sel[3:0] + attribute \src "ls180.v:1646.1-1692.4" + wire $0\wb_sdram_stb[0:0] + attribute \src "ls180.v:1646.1-1692.4" + wire $0\wb_sdram_we[0:0] + attribute \src "ls180.v:4287.1-5487.4" + wire $0\wdata_consumed[0:0] + attribute \src "ls180.v:5491.1-5509.4" + wire width 6 $1$memwr$\mem$ls180.v:5493$1_ADDR[5:0]$1484 + attribute \src "ls180.v:5491.1-5509.4" + wire width 64 $1$memwr$\mem$ls180.v:5493$1_DATA[63:0]$1485 + attribute \src "ls180.v:5491.1-5509.4" + wire width 64 $1$memwr$\mem$ls180.v:5493$1_EN[63:0]$1486 + attribute \src "ls180.v:5491.1-5509.4" + wire width 6 $1$memwr$\mem$ls180.v:5495$2_ADDR[5:0]$1487 + attribute \src "ls180.v:5491.1-5509.4" + wire width 64 $1$memwr$\mem$ls180.v:5495$2_DATA[63:0]$1488 + attribute \src "ls180.v:5491.1-5509.4" + wire width 64 $1$memwr$\mem$ls180.v:5495$2_EN[63:0]$1489 + attribute \src "ls180.v:5491.1-5509.4" + wire width 6 $1$memwr$\mem$ls180.v:5497$3_ADDR[5:0]$1490 + attribute \src "ls180.v:5491.1-5509.4" + wire width 64 $1$memwr$\mem$ls180.v:5497$3_DATA[63:0]$1491 + attribute \src "ls180.v:5491.1-5509.4" + wire width 64 $1$memwr$\mem$ls180.v:5497$3_EN[63:0]$1492 + attribute \src "ls180.v:5491.1-5509.4" + wire width 6 $1$memwr$\mem$ls180.v:5499$4_ADDR[5:0]$1493 + attribute \src "ls180.v:5491.1-5509.4" + wire width 64 $1$memwr$\mem$ls180.v:5499$4_DATA[63:0]$1494 + attribute \src "ls180.v:5491.1-5509.4" + wire width 64 $1$memwr$\mem$ls180.v:5499$4_EN[63:0]$1495 + attribute \src "ls180.v:5491.1-5509.4" + wire width 6 $1$memwr$\mem$ls180.v:5501$5_ADDR[5:0]$1496 + attribute \src "ls180.v:5491.1-5509.4" + wire width 64 $1$memwr$\mem$ls180.v:5501$5_DATA[63:0]$1497 + attribute \src "ls180.v:5491.1-5509.4" + wire width 64 $1$memwr$\mem$ls180.v:5501$5_EN[63:0]$1498 + attribute \src "ls180.v:5491.1-5509.4" + wire width 6 $1$memwr$\mem$ls180.v:5503$6_ADDR[5:0]$1499 + attribute \src "ls180.v:5491.1-5509.4" + wire width 64 $1$memwr$\mem$ls180.v:5503$6_DATA[63:0]$1500 + attribute \src "ls180.v:5491.1-5509.4" + wire width 64 $1$memwr$\mem$ls180.v:5503$6_EN[63:0]$1501 + attribute \src "ls180.v:5491.1-5509.4" + wire width 6 $1$memwr$\mem$ls180.v:5505$7_ADDR[5:0]$1502 + attribute \src "ls180.v:5491.1-5509.4" + wire width 64 $1$memwr$\mem$ls180.v:5505$7_DATA[63:0]$1503 + attribute \src "ls180.v:5491.1-5509.4" + wire width 64 $1$memwr$\mem$ls180.v:5505$7_EN[63:0]$1504 + attribute \src "ls180.v:5491.1-5509.4" + wire width 6 $1$memwr$\mem$ls180.v:5507$8_ADDR[5:0]$1505 + attribute \src "ls180.v:5491.1-5509.4" + wire width 64 $1$memwr$\mem$ls180.v:5507$8_DATA[63:0]$1506 + attribute \src "ls180.v:5491.1-5509.4" + wire width 64 $1$memwr$\mem$ls180.v:5507$8_EN[63:0]$1507 + attribute \src "ls180.v:5519.1-5537.4" + wire width 4 $1$memwr$\mem_1$ls180.v:5521$9_ADDR[3:0]$1534 + attribute \src "ls180.v:5519.1-5537.4" + wire width 64 $1$memwr$\mem_1$ls180.v:5521$9_DATA[63:0]$1535 + attribute \src "ls180.v:5519.1-5537.4" + wire width 64 $1$memwr$\mem_1$ls180.v:5521$9_EN[63:0]$1536 + attribute \src "ls180.v:5519.1-5537.4" + wire width 4 $1$memwr$\mem_1$ls180.v:5523$10_ADDR[3:0]$1537 + attribute \src "ls180.v:5519.1-5537.4" + wire width 64 $1$memwr$\mem_1$ls180.v:5523$10_DATA[63:0]$1538 + attribute \src "ls180.v:5519.1-5537.4" + wire width 64 $1$memwr$\mem_1$ls180.v:5523$10_EN[63:0]$1539 + attribute \src "ls180.v:5519.1-5537.4" + wire width 4 $1$memwr$\mem_1$ls180.v:5525$11_ADDR[3:0]$1540 + attribute \src "ls180.v:5519.1-5537.4" + wire width 64 $1$memwr$\mem_1$ls180.v:5525$11_DATA[63:0]$1541 + attribute \src "ls180.v:5519.1-5537.4" + wire width 64 $1$memwr$\mem_1$ls180.v:5525$11_EN[63:0]$1542 + attribute \src "ls180.v:5519.1-5537.4" + wire width 4 $1$memwr$\mem_1$ls180.v:5527$12_ADDR[3:0]$1543 + attribute \src "ls180.v:5519.1-5537.4" + wire width 64 $1$memwr$\mem_1$ls180.v:5527$12_DATA[63:0]$1544 + attribute \src "ls180.v:5519.1-5537.4" + wire width 64 $1$memwr$\mem_1$ls180.v:5527$12_EN[63:0]$1545 + attribute \src "ls180.v:5519.1-5537.4" + wire width 4 $1$memwr$\mem_1$ls180.v:5529$13_ADDR[3:0]$1546 + attribute \src "ls180.v:5519.1-5537.4" + wire width 64 $1$memwr$\mem_1$ls180.v:5529$13_DATA[63:0]$1547 + attribute \src "ls180.v:5519.1-5537.4" + wire width 64 $1$memwr$\mem_1$ls180.v:5529$13_EN[63:0]$1548 + attribute \src "ls180.v:5519.1-5537.4" + wire width 4 $1$memwr$\mem_1$ls180.v:5531$14_ADDR[3:0]$1549 + attribute \src "ls180.v:5519.1-5537.4" + wire width 64 $1$memwr$\mem_1$ls180.v:5531$14_DATA[63:0]$1550 + attribute \src "ls180.v:5519.1-5537.4" + wire width 64 $1$memwr$\mem_1$ls180.v:5531$14_EN[63:0]$1551 + attribute \src "ls180.v:5519.1-5537.4" + wire width 4 $1$memwr$\mem_1$ls180.v:5533$15_ADDR[3:0]$1552 + attribute \src "ls180.v:5519.1-5537.4" + wire width 64 $1$memwr$\mem_1$ls180.v:5533$15_DATA[63:0]$1553 + attribute \src "ls180.v:5519.1-5537.4" + wire width 64 $1$memwr$\mem_1$ls180.v:5533$15_EN[63:0]$1554 + attribute \src "ls180.v:5519.1-5537.4" + wire width 4 $1$memwr$\mem_1$ls180.v:5535$16_ADDR[3:0]$1555 + attribute \src "ls180.v:5519.1-5537.4" + wire width 64 $1$memwr$\mem_1$ls180.v:5535$16_DATA[63:0]$1556 + attribute \src "ls180.v:5519.1-5537.4" + wire width 64 $1$memwr$\mem_1$ls180.v:5535$16_EN[63:0]$1557 + attribute \src "ls180.v:5547.1-5551.4" + wire width 3 $1$memwr$\storage$ls180.v:5549$17_ADDR[2:0]$1563 + attribute \src "ls180.v:5547.1-5551.4" + wire width 25 $1$memwr$\storage$ls180.v:5549$17_DATA[24:0]$1564 + attribute \src "ls180.v:5547.1-5551.4" + wire width 25 $1$memwr$\storage$ls180.v:5549$17_EN[24:0]$1565 + attribute \src "ls180.v:5561.1-5565.4" + wire width 3 $1$memwr$\storage_1$ls180.v:5563$18_ADDR[2:0]$1573 + attribute \src "ls180.v:5561.1-5565.4" + wire width 25 $1$memwr$\storage_1$ls180.v:5563$18_DATA[24:0]$1574 + attribute \src "ls180.v:5561.1-5565.4" + wire width 25 $1$memwr$\storage_1$ls180.v:5563$18_EN[24:0]$1575 + attribute \src "ls180.v:5575.1-5579.4" + wire width 3 $1$memwr$\storage_2$ls180.v:5577$19_ADDR[2:0]$1583 + attribute \src "ls180.v:5575.1-5579.4" + wire width 25 $1$memwr$\storage_2$ls180.v:5577$19_DATA[24:0]$1584 + attribute \src "ls180.v:5575.1-5579.4" + wire width 25 $1$memwr$\storage_2$ls180.v:5577$19_EN[24:0]$1585 + attribute \src "ls180.v:5589.1-5593.4" + wire width 3 $1$memwr$\storage_3$ls180.v:5591$20_ADDR[2:0]$1593 + attribute \src "ls180.v:5589.1-5593.4" + wire width 25 $1$memwr$\storage_3$ls180.v:5591$20_DATA[24:0]$1594 + attribute \src "ls180.v:5589.1-5593.4" + wire width 25 $1$memwr$\storage_3$ls180.v:5591$20_EN[24:0]$1595 + attribute \src "ls180.v:5604.1-5608.4" + wire width 4 $1$memwr$\storage_4$ls180.v:5606$21_ADDR[3:0]$1603 + attribute \src "ls180.v:5604.1-5608.4" + wire width 10 $1$memwr$\storage_4$ls180.v:5606$21_DATA[9:0]$1604 + attribute \src "ls180.v:5604.1-5608.4" + wire width 10 $1$memwr$\storage_4$ls180.v:5606$21_EN[9:0]$1605 + attribute \src "ls180.v:5621.1-5625.4" + wire width 4 $1$memwr$\storage_5$ls180.v:5623$22_ADDR[3:0]$1613 + attribute \src "ls180.v:5621.1-5625.4" + wire width 10 $1$memwr$\storage_5$ls180.v:5623$22_DATA[9:0]$1614 + attribute \src "ls180.v:5621.1-5625.4" + wire width 10 $1$memwr$\storage_5$ls180.v:5623$22_EN[9:0]$1615 + attribute \src "ls180.v:1383.11-1383.30" + wire width 2 $1\array_muxed0[1:0] + attribute \src "ls180.v:1384.12-1384.32" + wire width 13 $1\array_muxed1[12:0] + attribute \src "ls180.v:1385.5-1385.24" + wire $1\array_muxed2[0:0] + attribute \src "ls180.v:1386.5-1386.24" + wire $1\array_muxed3[0:0] + attribute \src "ls180.v:1387.5-1387.24" + wire $1\array_muxed4[0:0] + attribute \src "ls180.v:1388.5-1388.24" + wire $1\array_muxed5[0:0] + attribute \src "ls180.v:1389.5-1389.24" + wire $1\array_muxed6[0:0] + attribute \src "ls180.v:827.5-827.24" + wire $1\cmd_consumed[0:0] + attribute \src "ls180.v:210.5-210.30" + wire $1\converter0_counter[0:0] + attribute \src "ls180.v:1004.5-1004.65" + wire $1\converter0_counter_subfragments_converter0_next_value[0:0] + attribute \src "ls180.v:1005.5-1005.68" + wire $1\converter0_counter_subfragments_converter0_next_value_ce[0:0] + attribute \src "ls180.v:212.12-212.36" + wire width 64 $1\converter0_dat_r[63:0] + attribute \src "ls180.v:209.5-209.27" + wire $1\converter0_skip[0:0] + attribute \src "ls180.v:225.5-225.30" + wire $1\converter1_counter[0:0] + attribute \src "ls180.v:1008.5-1008.65" + wire $1\converter1_counter_subfragments_converter1_next_value[0:0] + attribute \src "ls180.v:1009.5-1009.68" + wire $1\converter1_counter_subfragments_converter1_next_value_ce[0:0] + attribute \src "ls180.v:227.12-227.36" + wire width 64 $1\converter1_dat_r[63:0] + attribute \src "ls180.v:224.5-224.27" + wire $1\converter1_skip[0:0] + attribute \src "ls180.v:824.5-824.29" + wire $1\converter_counter[0:0] + attribute \src "ls180.v:1049.5-1049.53" + wire $1\converter_counter_subfragments_next_value[0:0] + attribute \src "ls180.v:1050.5-1050.56" + wire $1\converter_counter_subfragments_next_value_ce[0:0] + attribute \src "ls180.v:826.12-826.35" + wire width 32 $1\converter_dat_r[31:0] + attribute \src "ls180.v:823.5-823.26" + wire $1\converter_skip[0:0] + attribute \src "ls180.v:246.12-246.33" + wire width 16 $1\dfi_p0_rddata[15:0] + attribute \src "ls180.v:247.5-247.31" + wire $1\dfi_p0_rddata_valid[0:0] + attribute \src "ls180.v:993.12-993.25" + wire width 30 $1\dummy[29:0] + attribute \src "ls180.v:882.11-882.40" + wire width 2 $1\eventmanager_pending_w[1:0] + attribute \src "ls180.v:884.5-884.27" + wire $1\eventmanager_re[0:0] + attribute \src "ls180.v:878.11-878.39" + wire width 2 $1\eventmanager_status_w[1:0] + attribute \src "ls180.v:883.11-883.38" + wire width 2 $1\eventmanager_storage[1:0] + attribute \src "ls180.v:975.5-975.23" + wire $1\gpio0_oe_re[0:0] + attribute \src "ls180.v:974.11-974.34" + wire width 8 $1\gpio0_oe_storage[7:0] + attribute \src "ls180.v:979.5-979.24" + wire $1\gpio0_out_re[0:0] + attribute \src "ls180.v:978.11-978.35" + wire width 8 $1\gpio0_out_storage[7:0] + attribute \src "ls180.v:980.11-980.35" + wire width 8 $1\gpio0_pads_gpio0i[7:0] + attribute \src "ls180.v:981.11-981.35" + wire width 8 $1\gpio0_pads_gpio0o[7:0] + attribute \src "ls180.v:982.11-982.36" + wire width 8 $1\gpio0_pads_gpio0oe[7:0] + attribute \src "ls180.v:976.11-976.30" + wire width 8 $1\gpio0_status[7:0] + attribute \src "ls180.v:984.5-984.23" + wire $1\gpio1_oe_re[0:0] + attribute \src "ls180.v:983.11-983.34" + wire width 8 $1\gpio1_oe_storage[7:0] + attribute \src "ls180.v:988.5-988.24" + wire $1\gpio1_out_re[0:0] + attribute \src "ls180.v:987.11-987.35" + wire width 8 $1\gpio1_out_storage[7:0] + attribute \src "ls180.v:989.11-989.35" + wire width 8 $1\gpio1_pads_gpio1i[7:0] + attribute \src "ls180.v:990.11-990.35" + wire width 8 $1\gpio1_pads_gpio1o[7:0] + attribute \src "ls180.v:991.11-991.36" + wire width 8 $1\gpio1_pads_gpio1oe[7:0] + attribute \src "ls180.v:985.11-985.30" + wire width 8 $1\gpio1_status[7:0] + attribute \src "ls180.v:998.5-998.18" + wire $1\i2c_re[0:0] + attribute \src "ls180.v:997.11-997.29" + wire width 3 $1\i2c_storage[2:0] + attribute \src "ls180.v:231.5-231.19" + wire $1\int_rst[0:0] + attribute \src "ls180.v:204.5-204.46" + wire $1\interface0_converted_interface_ack[0:0] + attribute \src "ls180.v:219.5-219.46" + wire $1\interface1_converted_interface_ack[0:0] + attribute \src "ls180.v:51.12-51.42" + wire width 32 $1\libresocsim_bus_errors[31:0] + attribute \src "ls180.v:1092.12-1092.43" + wire width 20 $1\libresocsim_count[19:0] + attribute \src "ls180.v:161.5-161.29" + wire $1\libresocsim_en_re[0:0] + attribute \src "ls180.v:160.5-160.34" + wire $1\libresocsim_en_storage[0:0] + attribute \src "ls180.v:1089.5-1089.29" + wire $1\libresocsim_error[0:0] + attribute \src "ls180.v:181.5-181.39" + wire $1\libresocsim_eventmanager_re[0:0] + attribute \src "ls180.v:180.5-180.44" + wire $1\libresocsim_eventmanager_storage[0:0] + attribute \src "ls180.v:1086.11-1086.35" + wire width 2 $1\libresocsim_grant[1:0] + attribute \src "ls180.v:1096.11-1096.55" + wire width 8 $1\libresocsim_interface0_bank_bus_dat_r[7:0] + attribute \src "ls180.v:1137.11-1137.55" + wire width 8 $1\libresocsim_interface1_bank_bus_dat_r[7:0] + attribute \src "ls180.v:1154.11-1154.55" + wire width 8 $1\libresocsim_interface2_bank_bus_dat_r[7:0] + attribute \src "ls180.v:1171.11-1171.55" + wire width 8 $1\libresocsim_interface3_bank_bus_dat_r[7:0] + attribute \src "ls180.v:1184.11-1184.55" + wire width 8 $1\libresocsim_interface4_bank_bus_dat_r[7:0] + attribute \src "ls180.v:1225.11-1225.55" + wire width 8 $1\libresocsim_interface5_bank_bus_dat_r[7:0] + attribute \src "ls180.v:1290.11-1290.55" + wire width 8 $1\libresocsim_interface6_bank_bus_dat_r[7:0] + attribute \src "ls180.v:1315.11-1315.55" + wire width 8 $1\libresocsim_interface7_bank_bus_dat_r[7:0] + attribute \src "ls180.v:116.12-116.69" + wire width 16 $1\libresocsim_libresoc_constraintmanager_obj_gpio_o[15:0] + attribute \src "ls180.v:117.12-117.70" + wire width 16 $1\libresocsim_libresoc_constraintmanager_obj_gpio_oe[15:0] + attribute \src "ls180.v:125.12-125.70" + wire width 13 $1\libresocsim_libresoc_constraintmanager_obj_sdram_a[12:0] + attribute \src "ls180.v:134.11-134.69" + wire width 2 $1\libresocsim_libresoc_constraintmanager_obj_sdram_ba[1:0] + attribute \src "ls180.v:131.5-131.66" + wire $1\libresocsim_libresoc_constraintmanager_obj_sdram_cas_n[0:0] + attribute \src "ls180.v:133.5-133.64" + wire $1\libresocsim_libresoc_constraintmanager_obj_sdram_cke[0:0] + attribute \src "ls180.v:132.5-132.65" + wire $1\libresocsim_libresoc_constraintmanager_obj_sdram_cs_n[0:0] + attribute \src "ls180.v:135.11-135.69" + wire width 2 $1\libresocsim_libresoc_constraintmanager_obj_sdram_dm[1:0] + attribute \src "ls180.v:127.12-127.73" + wire width 16 $1\libresocsim_libresoc_constraintmanager_obj_sdram_dq_o[15:0] + attribute \src "ls180.v:128.5-128.66" + wire $1\libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe[0:0] + attribute \src "ls180.v:130.5-130.66" + wire $1\libresocsim_libresoc_constraintmanager_obj_sdram_ras_n[0:0] + attribute \src "ls180.v:129.5-129.65" + wire $1\libresocsim_libresoc_constraintmanager_obj_sdram_we_n[0:0] + attribute \src "ls180.v:122.5-122.62" + wire $1\libresocsim_libresoc_constraintmanager_obj_uart_tx[0:0] + attribute \src "ls180.v:53.12-53.50" + wire width 16 $1\libresocsim_libresoc_interrupt[15:0] + attribute \src "ls180.v:76.12-76.53" + wire width 30 $1\libresocsim_libresoc_xics_icp_adr[29:0] + attribute \src "ls180.v:80.5-80.45" + wire $1\libresocsim_libresoc_xics_icp_cyc[0:0] + attribute \src "ls180.v:77.12-77.55" + wire width 32 $1\libresocsim_libresoc_xics_icp_dat_w[31:0] + attribute \src "ls180.v:79.11-79.51" + wire width 4 $1\libresocsim_libresoc_xics_icp_sel[3:0] + attribute \src "ls180.v:81.5-81.45" + wire $1\libresocsim_libresoc_xics_icp_stb[0:0] + attribute \src "ls180.v:83.5-83.44" + wire $1\libresocsim_libresoc_xics_icp_we[0:0] + attribute \src "ls180.v:85.12-85.53" + wire width 30 $1\libresocsim_libresoc_xics_ics_adr[29:0] + attribute \src "ls180.v:89.5-89.45" + wire $1\libresocsim_libresoc_xics_ics_cyc[0:0] + attribute \src "ls180.v:86.12-86.55" + wire width 32 $1\libresocsim_libresoc_xics_ics_dat_w[31:0] + attribute \src "ls180.v:88.11-88.51" + wire width 4 $1\libresocsim_libresoc_xics_ics_sel[3:0] + attribute \src "ls180.v:90.5-90.45" + wire $1\libresocsim_libresoc_xics_ics_stb[0:0] + attribute \src "ls180.v:92.5-92.44" + wire $1\libresocsim_libresoc_xics_ics_we[0:0] + attribute \src "ls180.v:1051.12-1051.47" + wire width 14 $1\libresocsim_libresocsim_adr[13:0] + attribute \src "ls180.v:1341.12-1341.71" + wire width 14 $1\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0] + attribute \src "ls180.v:1342.5-1342.66" + wire $1\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0] + attribute \src "ls180.v:1053.11-1053.47" + wire width 8 $1\libresocsim_libresocsim_dat_w[7:0] + attribute \src "ls180.v:1339.11-1339.71" + wire width 8 $1\libresocsim_libresocsim_dat_w_libresocsim_next_value0[7:0] + attribute \src "ls180.v:1340.5-1340.68" + wire $1\libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0[0:0] + attribute \src "ls180.v:1052.5-1052.38" + wire $1\libresocsim_libresocsim_we[0:0] + attribute \src "ls180.v:1343.5-1343.62" + wire $1\libresocsim_libresocsim_we_libresocsim_next_value2[0:0] + attribute \src "ls180.v:1344.5-1344.65" + wire $1\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0] + attribute \src "ls180.v:1061.5-1061.48" + wire $1\libresocsim_libresocsim_wishbone_ack[0:0] + attribute \src "ls180.v:1057.12-1057.58" + wire width 32 $1\libresocsim_libresocsim_wishbone_dat_r[31:0] + attribute \src "ls180.v:157.5-157.31" + wire $1\libresocsim_load_re[0:0] + attribute \src "ls180.v:156.12-156.44" + wire width 32 $1\libresocsim_load_storage[31:0] + attribute \src "ls180.v:1338.11-1338.40" + wire width 2 $1\libresocsim_next_state[1:0] + attribute \src "ls180.v:147.5-147.35" + wire $1\libresocsim_ram_bus_ack[0:0] + attribute \src "ls180.v:159.5-159.33" + wire $1\libresocsim_reload_re[0:0] + attribute \src "ls180.v:158.12-158.46" + wire width 32 $1\libresocsim_reload_storage[31:0] + attribute \src "ls180.v:44.5-44.32" + wire $1\libresocsim_reset_re[0:0] + attribute \src "ls180.v:43.5-43.37" + wire $1\libresocsim_reset_storage[0:0] + attribute \src "ls180.v:46.5-46.34" + wire $1\libresocsim_scratch_re[0:0] + attribute \src "ls180.v:45.12-45.55" + wire width 32 $1\libresocsim_scratch_storage[31:0] + attribute \src "ls180.v:1080.5-1080.34" + wire $1\libresocsim_shared_ack[0:0] + attribute \src "ls180.v:1076.12-1076.44" + wire width 32 $1\libresocsim_shared_dat_r[31:0] + attribute \src "ls180.v:1087.11-1087.39" + wire width 6 $1\libresocsim_slave_sel[5:0] + attribute \src "ls180.v:1088.11-1088.41" + wire width 6 $1\libresocsim_slave_sel_r[5:0] + attribute \src "ls180.v:1337.11-1337.35" + wire width 2 $1\libresocsim_state[1:0] + attribute \src "ls180.v:163.5-163.39" + wire $1\libresocsim_update_value_re[0:0] + attribute \src "ls180.v:162.5-162.44" + wire $1\libresocsim_update_value_storage[0:0] + attribute \src "ls180.v:182.12-182.37" + wire width 32 $1\libresocsim_value[31:0] + attribute \src "ls180.v:164.12-164.44" + wire width 32 $1\libresocsim_value_status[31:0] + attribute \src "ls180.v:154.11-154.32" + wire width 8 $1\libresocsim_we[7:0] + attribute \src "ls180.v:170.5-170.34" + wire $1\libresocsim_zero_clear[0:0] + attribute \src "ls180.v:171.5-171.40" + wire $1\libresocsim_zero_old_trigger[0:0] + attribute \src "ls180.v:168.5-168.36" + wire $1\libresocsim_zero_pending[0:0] + attribute \src "ls180.v:815.12-815.35" + wire width 30 $1\litedram_wb_adr[29:0] + attribute \src "ls180.v:819.5-819.27" + wire $1\litedram_wb_cyc[0:0] + attribute \src "ls180.v:816.12-816.37" + wire width 16 $1\litedram_wb_dat_w[15:0] + attribute \src "ls180.v:818.11-818.33" + wire width 2 $1\litedram_wb_sel[1:0] + attribute \src "ls180.v:820.5-820.27" + wire $1\litedram_wb_stb[0:0] + attribute \src "ls180.v:822.5-822.26" + wire $1\litedram_wb_we[0:0] + attribute \src "ls180.v:189.5-189.31" + wire $1\ram_bus_ram_bus_ack[0:0] + attribute \src "ls180.v:196.11-196.24" + wire width 8 $1\ram_we[7:0] + attribute \src "ls180.v:248.11-248.27" + wire width 3 $1\rddata_en[2:0] + attribute \src "ls180.v:1446.32-1446.44" + wire $1\regs0[0:0] + attribute \src "ls180.v:1447.32-1447.44" + wire $1\regs1[0:0] + attribute \src "ls180.v:1345.5-1345.28" + wire $1\rhs_array_muxed0[0:0] + attribute \src "ls180.v:1358.5-1358.29" + wire $1\rhs_array_muxed10[0:0] + attribute \src "ls180.v:1359.5-1359.29" + wire $1\rhs_array_muxed11[0:0] + attribute \src "ls180.v:1363.12-1363.37" + wire width 22 $1\rhs_array_muxed12[21:0] + attribute \src "ls180.v:1364.5-1364.29" + wire $1\rhs_array_muxed13[0:0] + attribute \src "ls180.v:1365.5-1365.29" + wire $1\rhs_array_muxed14[0:0] + attribute \src "ls180.v:1366.12-1366.37" + wire width 22 $1\rhs_array_muxed15[21:0] + attribute \src "ls180.v:1367.5-1367.29" + wire $1\rhs_array_muxed16[0:0] + attribute \src "ls180.v:1368.5-1368.29" + wire $1\rhs_array_muxed17[0:0] + attribute \src "ls180.v:1369.12-1369.37" + wire width 22 $1\rhs_array_muxed18[21:0] + attribute \src "ls180.v:1370.5-1370.29" + wire $1\rhs_array_muxed19[0:0] + attribute \src "ls180.v:1346.12-1346.36" + wire width 13 $1\rhs_array_muxed1[12:0] + attribute \src "ls180.v:1371.5-1371.29" + wire $1\rhs_array_muxed20[0:0] + attribute \src "ls180.v:1372.12-1372.37" + wire width 22 $1\rhs_array_muxed21[21:0] + attribute \src "ls180.v:1373.5-1373.29" + wire $1\rhs_array_muxed22[0:0] + attribute \src "ls180.v:1374.5-1374.29" + wire $1\rhs_array_muxed23[0:0] + attribute \src "ls180.v:1375.12-1375.37" + wire width 29 $1\rhs_array_muxed24[28:0] + attribute \src "ls180.v:1376.12-1376.37" + wire width 64 $1\rhs_array_muxed25[63:0] + attribute \src "ls180.v:1377.11-1377.35" + wire width 8 $1\rhs_array_muxed26[7:0] + attribute \src "ls180.v:1378.5-1378.29" + wire $1\rhs_array_muxed27[0:0] + attribute \src "ls180.v:1379.5-1379.29" + wire $1\rhs_array_muxed28[0:0] + attribute \src "ls180.v:1380.5-1380.29" + wire $1\rhs_array_muxed29[0:0] + attribute \src "ls180.v:1347.11-1347.34" + wire width 2 $1\rhs_array_muxed2[1:0] + attribute \src "ls180.v:1381.11-1381.35" + wire width 3 $1\rhs_array_muxed30[2:0] + attribute \src "ls180.v:1382.11-1382.35" + wire width 2 $1\rhs_array_muxed31[1:0] + attribute \src "ls180.v:1348.5-1348.28" + wire $1\rhs_array_muxed3[0:0] + attribute \src "ls180.v:1349.5-1349.28" + wire $1\rhs_array_muxed4[0:0] + attribute \src "ls180.v:1350.5-1350.28" + wire $1\rhs_array_muxed5[0:0] + attribute \src "ls180.v:1354.5-1354.28" + wire $1\rhs_array_muxed6[0:0] + attribute \src "ls180.v:1355.12-1355.36" + wire width 13 $1\rhs_array_muxed7[12:0] + attribute \src "ls180.v:1356.11-1356.34" + wire width 2 $1\rhs_array_muxed8[1:0] + attribute \src "ls180.v:1357.5-1357.28" + wire $1\rhs_array_muxed9[0:0] + attribute \src "ls180.v:873.5-873.20" + wire $1\rx_clear[0:0] + attribute \src "ls180.v:957.11-957.33" + wire width 4 $1\rx_fifo_consume[3:0] + attribute \src "ls180.v:954.11-954.32" + wire width 5 $1\rx_fifo_level0[4:0] + attribute \src "ls180.v:956.11-956.33" + wire width 4 $1\rx_fifo_produce[3:0] + attribute \src "ls180.v:947.5-947.28" + wire $1\rx_fifo_readable[0:0] + attribute \src "ls180.v:958.11-958.36" + wire width 4 $1\rx_fifo_wrport_adr[3:0] + attribute \src "ls180.v:874.5-874.26" + wire $1\rx_old_trigger[0:0] + attribute \src "ls180.v:871.5-871.22" + wire $1\rx_pending[0:0] + attribute \src "ls180.v:310.5-310.28" + wire $1\sdram_address_re[0:0] + attribute \src "ls180.v:309.12-309.41" + wire width 13 $1\sdram_address_storage[12:0] + attribute \src "ls180.v:312.5-312.29" + wire $1\sdram_baddress_re[0:0] + attribute \src "ls180.v:311.11-311.40" + wire width 2 $1\sdram_baddress_storage[1:0] + attribute \src "ls180.v:408.5-408.45" + wire $1\sdram_bankmachine0_auto_precharge[0:0] + attribute \src "ls180.v:430.11-430.65" + wire width 3 $1\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:427.11-427.63" + wire width 4 $1\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:429.11-429.65" + wire width 3 $1\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:431.11-431.68" + wire width 3 $1\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:454.5-454.54" + wire $1\sdram_bankmachine0_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:455.5-455.53" + wire $1\sdram_bankmachine0_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:457.12-457.69" + wire width 22 $1\sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:456.5-456.59" + wire $1\sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:452.5-452.54" + wire $1\sdram_bankmachine0_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:400.12-400.52" + wire width 13 $1\sdram_bankmachine0_cmd_payload_a[12:0] + attribute \src "ls180.v:402.5-402.46" + wire $1\sdram_bankmachine0_cmd_payload_cas[0:0] + attribute \src "ls180.v:405.5-405.49" + wire $1\sdram_bankmachine0_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:406.5-406.50" + wire $1\sdram_bankmachine0_cmd_payload_is_read[0:0] + attribute \src "ls180.v:407.5-407.51" + wire $1\sdram_bankmachine0_cmd_payload_is_write[0:0] + attribute \src "ls180.v:403.5-403.46" + wire $1\sdram_bankmachine0_cmd_payload_ras[0:0] + attribute \src "ls180.v:404.5-404.45" + wire $1\sdram_bankmachine0_cmd_payload_we[0:0] + attribute \src "ls180.v:399.5-399.40" + wire $1\sdram_bankmachine0_cmd_ready[0:0] + attribute \src "ls180.v:398.5-398.40" + wire $1\sdram_bankmachine0_cmd_valid[0:0] + attribute \src "ls180.v:397.5-397.42" + wire $1\sdram_bankmachine0_refresh_gnt[0:0] + attribute \src "ls180.v:395.5-395.46" + wire $1\sdram_bankmachine0_req_rdata_valid[0:0] + attribute \src "ls180.v:394.5-394.46" + wire $1\sdram_bankmachine0_req_wdata_ready[0:0] + attribute \src "ls180.v:458.12-458.42" + wire width 13 $1\sdram_bankmachine0_row[12:0] + attribute \src "ls180.v:462.5-462.40" + wire $1\sdram_bankmachine0_row_close[0:0] + attribute \src "ls180.v:463.5-463.49" + wire $1\sdram_bankmachine0_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:461.5-461.39" + wire $1\sdram_bankmachine0_row_open[0:0] + attribute \src "ls180.v:459.5-459.41" + wire $1\sdram_bankmachine0_row_opened[0:0] + attribute \src "ls180.v:466.11-466.50" + wire width 3 $1\sdram_bankmachine0_twtpcon_count[2:0] + attribute \src "ls180.v:465.32-465.71" + wire $1\sdram_bankmachine0_twtpcon_ready[0:0] + attribute \src "ls180.v:490.5-490.45" + wire $1\sdram_bankmachine1_auto_precharge[0:0] + attribute \src "ls180.v:512.11-512.65" + wire width 3 $1\sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:509.11-509.63" + wire width 4 $1\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:511.11-511.65" + wire width 3 $1\sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:513.11-513.68" + wire width 3 $1\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:536.5-536.54" + wire $1\sdram_bankmachine1_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:537.5-537.53" + wire $1\sdram_bankmachine1_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:539.12-539.69" + wire width 22 $1\sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:538.5-538.59" + wire $1\sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:534.5-534.54" + wire $1\sdram_bankmachine1_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:482.12-482.52" + wire width 13 $1\sdram_bankmachine1_cmd_payload_a[12:0] + attribute \src "ls180.v:484.5-484.46" + wire $1\sdram_bankmachine1_cmd_payload_cas[0:0] + attribute \src "ls180.v:487.5-487.49" + wire $1\sdram_bankmachine1_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:488.5-488.50" + wire $1\sdram_bankmachine1_cmd_payload_is_read[0:0] + attribute \src "ls180.v:489.5-489.51" + wire $1\sdram_bankmachine1_cmd_payload_is_write[0:0] + attribute \src "ls180.v:485.5-485.46" + wire $1\sdram_bankmachine1_cmd_payload_ras[0:0] + attribute \src "ls180.v:486.5-486.45" + wire $1\sdram_bankmachine1_cmd_payload_we[0:0] + attribute \src "ls180.v:481.5-481.40" + wire $1\sdram_bankmachine1_cmd_ready[0:0] + attribute \src "ls180.v:480.5-480.40" + wire $1\sdram_bankmachine1_cmd_valid[0:0] + attribute \src "ls180.v:479.5-479.42" + wire $1\sdram_bankmachine1_refresh_gnt[0:0] + attribute \src "ls180.v:477.5-477.46" + wire $1\sdram_bankmachine1_req_rdata_valid[0:0] + attribute \src "ls180.v:476.5-476.46" + wire $1\sdram_bankmachine1_req_wdata_ready[0:0] + attribute \src "ls180.v:540.12-540.42" + wire width 13 $1\sdram_bankmachine1_row[12:0] + attribute \src "ls180.v:544.5-544.40" + wire $1\sdram_bankmachine1_row_close[0:0] + attribute \src "ls180.v:545.5-545.49" + wire $1\sdram_bankmachine1_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:543.5-543.39" + wire $1\sdram_bankmachine1_row_open[0:0] + attribute \src "ls180.v:541.5-541.41" + wire $1\sdram_bankmachine1_row_opened[0:0] + attribute \src "ls180.v:548.11-548.50" + wire width 3 $1\sdram_bankmachine1_twtpcon_count[2:0] + attribute \src "ls180.v:547.32-547.71" + wire $1\sdram_bankmachine1_twtpcon_ready[0:0] + attribute \src "ls180.v:572.5-572.45" + wire $1\sdram_bankmachine2_auto_precharge[0:0] + attribute \src "ls180.v:594.11-594.65" + wire width 3 $1\sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:591.11-591.63" + wire width 4 $1\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:593.11-593.65" + wire width 3 $1\sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:595.11-595.68" + wire width 3 $1\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:618.5-618.54" + wire $1\sdram_bankmachine2_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:619.5-619.53" + wire $1\sdram_bankmachine2_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:621.12-621.69" + wire width 22 $1\sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:620.5-620.59" + wire $1\sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:616.5-616.54" + wire $1\sdram_bankmachine2_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:564.12-564.52" + wire width 13 $1\sdram_bankmachine2_cmd_payload_a[12:0] + attribute \src "ls180.v:566.5-566.46" + wire $1\sdram_bankmachine2_cmd_payload_cas[0:0] + attribute \src "ls180.v:569.5-569.49" + wire $1\sdram_bankmachine2_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:570.5-570.50" + wire $1\sdram_bankmachine2_cmd_payload_is_read[0:0] + attribute \src "ls180.v:571.5-571.51" + wire $1\sdram_bankmachine2_cmd_payload_is_write[0:0] + attribute \src "ls180.v:567.5-567.46" + wire $1\sdram_bankmachine2_cmd_payload_ras[0:0] + attribute \src "ls180.v:568.5-568.45" + wire $1\sdram_bankmachine2_cmd_payload_we[0:0] + attribute \src "ls180.v:563.5-563.40" + wire $1\sdram_bankmachine2_cmd_ready[0:0] + attribute \src "ls180.v:562.5-562.40" + wire $1\sdram_bankmachine2_cmd_valid[0:0] + attribute \src "ls180.v:561.5-561.42" + wire $1\sdram_bankmachine2_refresh_gnt[0:0] + attribute \src "ls180.v:559.5-559.46" + wire $1\sdram_bankmachine2_req_rdata_valid[0:0] + attribute \src "ls180.v:558.5-558.46" + wire $1\sdram_bankmachine2_req_wdata_ready[0:0] + attribute \src "ls180.v:622.12-622.42" + wire width 13 $1\sdram_bankmachine2_row[12:0] + attribute \src "ls180.v:626.5-626.40" + wire $1\sdram_bankmachine2_row_close[0:0] + attribute \src "ls180.v:627.5-627.49" + wire $1\sdram_bankmachine2_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:625.5-625.39" + wire $1\sdram_bankmachine2_row_open[0:0] + attribute \src "ls180.v:623.5-623.41" + wire $1\sdram_bankmachine2_row_opened[0:0] + attribute \src "ls180.v:630.11-630.50" + wire width 3 $1\sdram_bankmachine2_twtpcon_count[2:0] + attribute \src "ls180.v:629.32-629.71" + wire $1\sdram_bankmachine2_twtpcon_ready[0:0] + attribute \src "ls180.v:654.5-654.45" + wire $1\sdram_bankmachine3_auto_precharge[0:0] + attribute \src "ls180.v:676.11-676.65" + wire width 3 $1\sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + attribute \src "ls180.v:673.11-673.63" + wire width 4 $1\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + attribute \src "ls180.v:675.11-675.65" + wire width 3 $1\sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + attribute \src "ls180.v:677.11-677.68" + wire width 3 $1\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "ls180.v:700.5-700.54" + wire $1\sdram_bankmachine3_cmd_buffer_source_first[0:0] + attribute \src "ls180.v:701.5-701.53" + wire $1\sdram_bankmachine3_cmd_buffer_source_last[0:0] + attribute \src "ls180.v:703.12-703.69" + wire width 22 $1\sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + attribute \src "ls180.v:702.5-702.59" + wire $1\sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + attribute \src "ls180.v:698.5-698.54" + wire $1\sdram_bankmachine3_cmd_buffer_source_valid[0:0] + attribute \src "ls180.v:646.12-646.52" + wire width 13 $1\sdram_bankmachine3_cmd_payload_a[12:0] + attribute \src "ls180.v:648.5-648.46" + wire $1\sdram_bankmachine3_cmd_payload_cas[0:0] + attribute \src "ls180.v:651.5-651.49" + wire $1\sdram_bankmachine3_cmd_payload_is_cmd[0:0] + attribute \src "ls180.v:652.5-652.50" + wire $1\sdram_bankmachine3_cmd_payload_is_read[0:0] + attribute \src "ls180.v:653.5-653.51" + wire $1\sdram_bankmachine3_cmd_payload_is_write[0:0] + attribute \src "ls180.v:649.5-649.46" + wire $1\sdram_bankmachine3_cmd_payload_ras[0:0] + attribute \src "ls180.v:650.5-650.45" + wire $1\sdram_bankmachine3_cmd_payload_we[0:0] + attribute \src "ls180.v:645.5-645.40" + wire $1\sdram_bankmachine3_cmd_ready[0:0] + attribute \src "ls180.v:644.5-644.40" + wire $1\sdram_bankmachine3_cmd_valid[0:0] + attribute \src "ls180.v:643.5-643.42" + wire $1\sdram_bankmachine3_refresh_gnt[0:0] + attribute \src "ls180.v:641.5-641.46" + wire $1\sdram_bankmachine3_req_rdata_valid[0:0] + attribute \src "ls180.v:640.5-640.46" + wire $1\sdram_bankmachine3_req_wdata_ready[0:0] + attribute \src "ls180.v:704.12-704.42" + wire width 13 $1\sdram_bankmachine3_row[12:0] + attribute \src "ls180.v:708.5-708.40" + wire $1\sdram_bankmachine3_row_close[0:0] + attribute \src "ls180.v:709.5-709.49" + wire $1\sdram_bankmachine3_row_col_n_addr_sel[0:0] + attribute \src "ls180.v:707.5-707.39" + wire $1\sdram_bankmachine3_row_open[0:0] + attribute \src "ls180.v:705.5-705.41" + wire $1\sdram_bankmachine3_row_opened[0:0] + attribute \src "ls180.v:712.11-712.50" + wire width 3 $1\sdram_bankmachine3_twtpcon_count[2:0] + attribute \src "ls180.v:711.32-711.71" + wire $1\sdram_bankmachine3_twtpcon_ready[0:0] + attribute \src "ls180.v:727.5-727.44" + wire $1\sdram_choose_cmd_cmd_payload_cas[0:0] + attribute \src "ls180.v:728.5-728.44" + wire $1\sdram_choose_cmd_cmd_payload_ras[0:0] + attribute \src "ls180.v:729.5-729.43" + wire $1\sdram_choose_cmd_cmd_payload_we[0:0] + attribute \src "ls180.v:735.11-735.40" + wire width 2 $1\sdram_choose_cmd_grant[1:0] + attribute \src "ls180.v:733.11-733.41" + wire width 4 $1\sdram_choose_cmd_valids[3:0] + attribute \src "ls180.v:745.5-745.44" + wire $1\sdram_choose_req_cmd_payload_cas[0:0] + attribute \src "ls180.v:746.5-746.44" + wire $1\sdram_choose_req_cmd_payload_ras[0:0] + attribute \src "ls180.v:747.5-747.43" + wire $1\sdram_choose_req_cmd_payload_we[0:0] + attribute \src "ls180.v:742.5-742.38" + wire $1\sdram_choose_req_cmd_ready[0:0] + attribute \src "ls180.v:753.11-753.40" + wire width 2 $1\sdram_choose_req_grant[1:0] + attribute \src "ls180.v:751.11-751.41" + wire width 4 $1\sdram_choose_req_valids[3:0] + attribute \src "ls180.v:740.5-740.43" + wire $1\sdram_choose_req_want_activates[0:0] + attribute \src "ls180.v:737.5-737.39" + wire $1\sdram_choose_req_want_reads[0:0] + attribute \src "ls180.v:738.5-738.40" + wire $1\sdram_choose_req_want_writes[0:0] + attribute \src "ls180.v:136.5-136.23" + wire $1\sdram_clock[0:0] + attribute \src "ls180.v:366.5-366.26" + wire $1\sdram_cmd_last[0:0] + attribute \src "ls180.v:367.12-367.39" + wire width 13 $1\sdram_cmd_payload_a[12:0] + attribute \src "ls180.v:368.11-368.38" + wire width 2 $1\sdram_cmd_payload_ba[1:0] + attribute \src "ls180.v:369.5-369.33" + wire $1\sdram_cmd_payload_cas[0:0] + attribute \src "ls180.v:370.5-370.33" + wire $1\sdram_cmd_payload_ras[0:0] + attribute \src "ls180.v:371.5-371.32" + wire $1\sdram_cmd_payload_we[0:0] + attribute \src "ls180.v:365.5-365.27" + wire $1\sdram_cmd_ready[0:0] + attribute \src "ls180.v:364.5-364.27" + wire $1\sdram_cmd_valid[0:0] + attribute \src "ls180.v:304.5-304.28" + wire $1\sdram_command_re[0:0] + attribute \src "ls180.v:303.11-303.39" + wire width 6 $1\sdram_command_storage[5:0] + attribute \src "ls180.v:348.12-348.40" + wire width 13 $1\sdram_dfi_p0_address[12:0] + attribute \src "ls180.v:349.11-349.35" + wire width 2 $1\sdram_dfi_p0_bank[1:0] + attribute \src "ls180.v:350.5-350.30" + wire $1\sdram_dfi_p0_cas_n[0:0] + attribute \src "ls180.v:351.5-351.29" + wire $1\sdram_dfi_p0_cs_n[0:0] + attribute \src "ls180.v:352.5-352.30" + wire $1\sdram_dfi_p0_ras_n[0:0] + attribute \src "ls180.v:361.5-361.34" + wire $1\sdram_dfi_p0_rddata_en[0:0] + attribute \src "ls180.v:353.5-353.29" + wire $1\sdram_dfi_p0_we_n[0:0] + attribute \src "ls180.v:359.5-359.34" + wire $1\sdram_dfi_p0_wrdata_en[0:0] + attribute \src "ls180.v:772.5-772.21" + wire $1\sdram_en0[0:0] + attribute \src "ls180.v:775.5-775.21" + wire $1\sdram_en1[0:0] + attribute \src "ls180.v:345.12-345.41" + wire width 16 $1\sdram_interface_wdata[15:0] + attribute \src "ls180.v:346.11-346.42" + wire width 2 $1\sdram_interface_wdata_we[1:0] + attribute \src "ls180.v:251.5-251.31" + wire $1\sdram_inti_p0_cas_n[0:0] + attribute \src "ls180.v:252.5-252.30" + wire $1\sdram_inti_p0_cs_n[0:0] + attribute \src "ls180.v:253.5-253.31" + wire $1\sdram_inti_p0_ras_n[0:0] + attribute \src "ls180.v:263.12-263.40" + wire width 16 $1\sdram_inti_p0_rddata[15:0] + attribute \src "ls180.v:264.5-264.38" + wire $1\sdram_inti_p0_rddata_valid[0:0] + attribute \src "ls180.v:254.5-254.30" + wire $1\sdram_inti_p0_we_n[0:0] + attribute \src "ls180.v:290.5-290.33" + wire $1\sdram_master_p0_act_n[0:0] + attribute \src "ls180.v:281.12-281.43" + wire width 13 $1\sdram_master_p0_address[12:0] + attribute \src "ls180.v:282.11-282.38" + wire width 2 $1\sdram_master_p0_bank[1:0] + attribute \src "ls180.v:283.5-283.33" + wire $1\sdram_master_p0_cas_n[0:0] + attribute \src "ls180.v:287.5-287.31" + wire $1\sdram_master_p0_cke[0:0] + attribute \src "ls180.v:284.5-284.32" + wire $1\sdram_master_p0_cs_n[0:0] + attribute \src "ls180.v:288.5-288.31" + wire $1\sdram_master_p0_odt[0:0] + attribute \src "ls180.v:285.5-285.33" + wire $1\sdram_master_p0_ras_n[0:0] + attribute \src "ls180.v:294.5-294.37" + wire $1\sdram_master_p0_rddata_en[0:0] + attribute \src "ls180.v:289.5-289.35" + wire $1\sdram_master_p0_reset_n[0:0] + attribute \src "ls180.v:286.5-286.32" + wire $1\sdram_master_p0_we_n[0:0] + attribute \src "ls180.v:291.12-291.42" + wire width 16 $1\sdram_master_p0_wrdata[15:0] + attribute \src "ls180.v:292.5-292.37" + wire $1\sdram_master_p0_wrdata_en[0:0] + attribute \src "ls180.v:293.11-293.45" + wire width 2 $1\sdram_master_p0_wrdata_mask[1:0] + attribute \src "ls180.v:382.5-382.33" + wire $1\sdram_postponer_count[0:0] + attribute \src "ls180.v:381.5-381.33" + wire $1\sdram_postponer_req_o[0:0] + attribute \src "ls180.v:302.5-302.20" + wire $1\sdram_re[0:0] + attribute \src "ls180.v:388.5-388.33" + wire $1\sdram_sequencer_count[0:0] + attribute \src "ls180.v:387.11-387.41" + wire width 4 $1\sdram_sequencer_counter[3:0] + attribute \src "ls180.v:386.5-386.33" + wire $1\sdram_sequencer_done1[0:0] + attribute \src "ls180.v:383.5-383.34" + wire $1\sdram_sequencer_start0[0:0] + attribute \src "ls180.v:279.12-279.41" + wire width 16 $1\sdram_slave_p0_rddata[15:0] + attribute \src "ls180.v:280.5-280.39" + wire $1\sdram_slave_p0_rddata_valid[0:0] + attribute \src "ls180.v:315.12-315.32" + wire width 16 $1\sdram_status[15:0] + attribute \src "ls180.v:757.11-757.35" + wire width 2 $1\sdram_steerer_sel[1:0] + attribute \src "ls180.v:301.11-301.31" + wire width 4 $1\sdram_storage[3:0] + attribute \src "ls180.v:766.5-766.31" + wire $1\sdram_tccdcon_count[0:0] + attribute \src "ls180.v:765.32-765.58" + wire $1\sdram_tccdcon_ready[0:0] + attribute \src "ls180.v:774.11-774.29" + wire width 5 $1\sdram_time0[4:0] + attribute \src "ls180.v:777.11-777.29" + wire width 4 $1\sdram_time1[3:0] + attribute \src "ls180.v:379.11-379.39" + wire width 10 $1\sdram_timer_count1[9:0] + attribute \src "ls180.v:769.11-769.37" + wire width 3 $1\sdram_twtrcon_count[2:0] + attribute \src "ls180.v:768.32-768.58" + wire $1\sdram_twtrcon_ready[0:0] + attribute \src "ls180.v:314.5-314.27" + wire $1\sdram_wrdata_re[0:0] + attribute \src "ls180.v:313.12-313.40" + wire width 16 $1\sdram_wrdata_storage[15:0] + attribute \src "ls180.v:806.5-806.49" + wire $1\socbushandler_converted_interface_ack[0:0] + attribute \src "ls180.v:812.5-812.33" + wire $1\socbushandler_counter[0:0] + attribute \src "ls180.v:1012.5-1012.68" + wire $1\socbushandler_counter_subfragments_converter2_next_value[0:0] + attribute \src "ls180.v:1013.5-1013.71" + wire $1\socbushandler_counter_subfragments_converter2_next_value_ce[0:0] + attribute \src "ls180.v:814.12-814.39" + wire width 64 $1\socbushandler_dat_r[63:0] + attribute \src "ls180.v:811.5-811.30" + wire $1\socbushandler_skip[0:0] + attribute \src "ls180.v:1017.11-1017.54" + wire width 3 $1\subfragments_bankmachine0_next_state[2:0] + attribute \src "ls180.v:1016.11-1016.49" + wire width 3 $1\subfragments_bankmachine0_state[2:0] + attribute \src "ls180.v:1019.11-1019.54" + wire width 3 $1\subfragments_bankmachine1_next_state[2:0] + attribute \src "ls180.v:1018.11-1018.49" + wire width 3 $1\subfragments_bankmachine1_state[2:0] + attribute \src "ls180.v:1021.11-1021.54" + wire width 3 $1\subfragments_bankmachine2_next_state[2:0] + attribute \src "ls180.v:1020.11-1020.49" + wire width 3 $1\subfragments_bankmachine2_state[2:0] + attribute \src "ls180.v:1023.11-1023.54" + wire width 3 $1\subfragments_bankmachine3_next_state[2:0] + attribute \src "ls180.v:1022.11-1022.49" + wire width 3 $1\subfragments_bankmachine3_state[2:0] + attribute \src "ls180.v:1003.5-1003.46" + wire $1\subfragments_converter0_next_state[0:0] + attribute \src "ls180.v:1002.5-1002.41" + wire $1\subfragments_converter0_state[0:0] + attribute \src "ls180.v:1007.5-1007.46" + wire $1\subfragments_converter1_next_state[0:0] + attribute \src "ls180.v:1006.5-1006.41" + wire $1\subfragments_converter1_state[0:0] + attribute \src "ls180.v:1011.5-1011.46" + wire $1\subfragments_converter2_next_state[0:0] + attribute \src "ls180.v:1010.5-1010.41" + wire $1\subfragments_converter2_state[0:0] + attribute \src "ls180.v:1025.11-1025.53" + wire width 3 $1\subfragments_multiplexer_next_state[2:0] + attribute \src "ls180.v:1024.11-1024.48" + wire width 3 $1\subfragments_multiplexer_state[2:0] + attribute \src "ls180.v:1043.5-1043.48" + wire $1\subfragments_new_master_rdata_valid0[0:0] + attribute \src "ls180.v:1044.5-1044.48" + wire $1\subfragments_new_master_rdata_valid1[0:0] + attribute \src "ls180.v:1045.5-1045.48" + wire $1\subfragments_new_master_rdata_valid2[0:0] + attribute \src "ls180.v:1046.5-1046.48" + wire $1\subfragments_new_master_rdata_valid3[0:0] + attribute \src "ls180.v:1042.5-1042.47" + wire $1\subfragments_new_master_wdata_ready[0:0] + attribute \src "ls180.v:1048.5-1048.35" + wire $1\subfragments_next_state[0:0] + attribute \src "ls180.v:1015.11-1015.51" + wire width 2 $1\subfragments_refresher_next_state[1:0] + attribute \src "ls180.v:1014.11-1014.46" + wire width 2 $1\subfragments_refresher_state[1:0] + attribute \src "ls180.v:1047.5-1047.30" + wire $1\subfragments_state[0:0] + attribute \src "ls180.v:1351.5-1351.26" + wire $1\t_array_muxed0[0:0] + attribute \src "ls180.v:1352.5-1352.26" + wire $1\t_array_muxed1[0:0] + attribute \src "ls180.v:1353.5-1353.26" + wire $1\t_array_muxed2[0:0] + attribute \src "ls180.v:1360.5-1360.26" + wire $1\t_array_muxed3[0:0] + attribute \src "ls180.v:1361.5-1361.26" + wire $1\t_array_muxed4[0:0] + attribute \src "ls180.v:1362.5-1362.26" + wire $1\t_array_muxed5[0:0] + attribute \src "ls180.v:868.5-868.20" + wire $1\tx_clear[0:0] + attribute \src "ls180.v:920.11-920.33" + wire width 4 $1\tx_fifo_consume[3:0] + attribute \src "ls180.v:917.11-917.32" + wire width 5 $1\tx_fifo_level0[4:0] + attribute \src "ls180.v:919.11-919.33" + wire width 4 $1\tx_fifo_produce[3:0] + attribute \src "ls180.v:910.5-910.28" + wire $1\tx_fifo_readable[0:0] + attribute \src "ls180.v:921.11-921.36" + wire width 4 $1\tx_fifo_wrport_adr[3:0] + attribute \src "ls180.v:869.5-869.26" + wire $1\tx_old_trigger[0:0] + attribute \src "ls180.v:866.5-866.22" + wire $1\tx_pending[0:0] + attribute \src "ls180.v:850.12-850.49" + wire width 32 $1\uart_phy_phase_accumulator_rx[31:0] + attribute \src "ls180.v:840.12-840.49" + wire width 32 $1\uart_phy_phase_accumulator_tx[31:0] + attribute \src "ls180.v:833.5-833.23" + wire $1\uart_phy_re[0:0] + attribute \src "ls180.v:854.11-854.38" + wire width 4 $1\uart_phy_rx_bitcount[3:0] attribute \src "ls180.v:855.5-855.28" - wire $1\main_uart_phy_re[0:0] - attribute \src "ls180.v:876.11-876.43" - wire width 4 $1\main_uart_phy_rx_bitcount[3:0] - attribute \src "ls180.v:877.5-877.33" - wire $1\main_uart_phy_rx_busy[0:0] - attribute \src "ls180.v:874.5-874.30" - wire $1\main_uart_phy_rx_r[0:0] - attribute \src "ls180.v:875.11-875.38" - wire width 8 $1\main_uart_phy_rx_reg[7:0] - attribute \src "ls180.v:857.5-857.36" - wire $1\main_uart_phy_sink_ready[0:0] - attribute \src "ls180.v:870.11-870.51" - wire width 8 $1\main_uart_phy_source_payload_data[7:0] - attribute \src "ls180.v:866.5-866.38" - wire $1\main_uart_phy_source_valid[0:0] - attribute \src "ls180.v:854.12-854.47" - wire width 32 $1\main_uart_phy_storage[31:0] - attribute \src "ls180.v:864.11-864.43" - wire width 4 $1\main_uart_phy_tx_bitcount[3:0] - attribute \src "ls180.v:865.5-865.33" - wire $1\main_uart_phy_tx_busy[0:0] - attribute \src "ls180.v:863.11-863.38" - wire width 8 $1\main_uart_phy_tx_reg[7:0] - attribute \src "ls180.v:871.5-871.39" - wire $1\main_uart_phy_uart_clk_rxen[0:0] - attribute \src "ls180.v:861.5-861.39" - wire $1\main_uart_phy_uart_clk_txen[0:0] - attribute \src "ls180.v:895.5-895.30" - wire $1\main_uart_rx_clear[0:0] - attribute \src "ls180.v:979.11-979.43" - wire width 4 $1\main_uart_rx_fifo_consume[3:0] - attribute \src "ls180.v:976.11-976.42" - wire width 5 $1\main_uart_rx_fifo_level0[4:0] - attribute \src "ls180.v:978.11-978.43" - wire width 4 $1\main_uart_rx_fifo_produce[3:0] - attribute \src "ls180.v:969.5-969.38" - wire $1\main_uart_rx_fifo_readable[0:0] - attribute \src "ls180.v:980.11-980.46" - wire width 4 $1\main_uart_rx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:896.5-896.36" - wire $1\main_uart_rx_old_trigger[0:0] - attribute \src "ls180.v:893.5-893.32" - wire $1\main_uart_rx_pending[0:0] - attribute \src "ls180.v:890.5-890.30" - wire $1\main_uart_tx_clear[0:0] - attribute \src "ls180.v:942.11-942.43" - wire width 4 $1\main_uart_tx_fifo_consume[3:0] - attribute \src "ls180.v:939.11-939.42" - wire width 5 $1\main_uart_tx_fifo_level0[4:0] - attribute \src "ls180.v:941.11-941.43" - wire width 4 $1\main_uart_tx_fifo_produce[3:0] - attribute \src "ls180.v:932.5-932.38" - wire $1\main_uart_tx_fifo_readable[0:0] - attribute \src "ls180.v:943.11-943.46" - wire width 4 $1\main_uart_tx_fifo_wrport_adr[3:0] - attribute \src "ls180.v:891.5-891.36" - wire $1\main_uart_tx_old_trigger[0:0] - attribute \src "ls180.v:888.5-888.32" - wire $1\main_uart_tx_pending[0:0] - attribute \src "ls180.v:820.5-820.29" - wire $1\main_wb_sdram_ack[0:0] - attribute \src "ls180.v:814.12-814.37" - wire width 30 $1\main_wb_sdram_adr[29:0] - attribute \src "ls180.v:818.5-818.29" - wire $1\main_wb_sdram_cyc[0:0] - attribute \src "ls180.v:815.12-815.39" - wire width 32 $1\main_wb_sdram_dat_w[31:0] - attribute \src "ls180.v:817.11-817.35" - wire width 4 $1\main_wb_sdram_sel[3:0] - attribute \src "ls180.v:819.5-819.29" - wire $1\main_wb_sdram_stb[0:0] - attribute \src "ls180.v:821.5-821.28" - wire $1\main_wb_sdram_we[0:0] - attribute \src "ls180.v:850.5-850.31" - wire $1\main_wdata_consumed[0:0] - attribute \src "ls180.v:2846.56-2846.86" - wire $add$ls180.v:2846$34_Y - attribute \src "ls180.v:2906.56-2906.86" - wire $add$ls180.v:2906$45_Y - attribute \src "ls180.v:2966.59-2966.92" - wire $add$ls180.v:2966$56_Y - attribute \src "ls180.v:4117.54-4117.83" - wire $add$ls180.v:4117$586_Y - attribute \src "ls180.v:4217.36-4217.89" - wire width 5 $add$ls180.v:4217$632_Y - attribute \src "ls180.v:4247.36-4247.89" - wire width 5 $add$ls180.v:4247$643_Y - attribute \src "ls180.v:4313.54-4313.83" - wire width 3 $add$ls180.v:4313$658_Y - attribute \src "ls180.v:4372.52-4372.79" - wire width 3 $add$ls180.v:4372$666_Y - attribute \src "ls180.v:4476.58-4476.86" - wire width 8 $add$ls180.v:4476$694_Y - attribute \src "ls180.v:4533.58-4533.86" - wire width 8 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"ls180.v:8764.36-8764.70" - wire width 6 $add$ls180.v:8764$2734_Y - attribute \src "ls180.v:2840.9-2840.90" - wire $and$ls180.v:2840$29_Y - attribute \src "ls180.v:2858.9-2858.90" - wire $and$ls180.v:2858$36_Y - attribute \src "ls180.v:2900.9-2900.90" - wire $and$ls180.v:2900$40_Y - attribute \src "ls180.v:2918.9-2918.90" - wire $and$ls180.v:2918$47_Y - attribute \src "ls180.v:2960.9-2960.96" - wire $and$ls180.v:2960$51_Y - attribute \src "ls180.v:2978.9-2978.96" - wire $and$ls180.v:2978$58_Y - attribute \src "ls180.v:2988.31-2988.90" - wire $and$ls180.v:2988$60_Y - attribute \src "ls180.v:2988.30-2988.121" - wire $and$ls180.v:2988$61_Y - attribute \src "ls180.v:2988.29-2988.156" - wire $and$ls180.v:2988$62_Y - attribute \src "ls180.v:2989.31-2989.90" - wire $and$ls180.v:2989$63_Y - attribute \src "ls180.v:2989.30-2989.121" - wire $and$ls180.v:2989$64_Y - attribute \src "ls180.v:2989.29-2989.156" - wire $and$ls180.v:2989$65_Y - attribute \src "ls180.v:2990.31-2990.90" - wire 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$eq$ls180.v:1929$128_Y + attribute \src "ls180.v:1946.42-1946.78" + wire $eq$ls180.v:1946$141_Y + attribute \src "ls180.v:2086.38-2086.119" + wire $eq$ls180.v:2086$158_Y + attribute \src "ls180.v:2103.42-2103.78" + wire $eq$ls180.v:2103$171_Y + attribute \src "ls180.v:2243.38-2243.119" + wire $eq$ls180.v:2243$188_Y + attribute \src "ls180.v:2260.42-2260.78" + wire $eq$ls180.v:2260$201_Y + attribute \src "ls180.v:2400.38-2400.119" + wire $eq$ls180.v:2400$218_Y + attribute \src "ls180.v:2417.42-2417.78" + wire $eq$ls180.v:2417$231_Y + attribute \src "ls180.v:2554.27-2554.46" + wire $eq$ls180.v:2554$278_Y + attribute \src "ls180.v:2555.27-2555.46" + wire $eq$ls180.v:2555$279_Y + attribute \src "ls180.v:2566.299-2566.368" + wire $eq$ls180.v:2566$293_Y + attribute \src "ls180.v:2566.373-2566.444" + wire $eq$ls180.v:2566$294_Y + attribute \src "ls180.v:2567.299-2567.368" + wire $eq$ls180.v:2567$306_Y + attribute \src "ls180.v:2567.373-2567.444" + wire $eq$ls180.v:2567$307_Y + attribute \src "ls180.v:2568.299-2568.368" + wire $eq$ls180.v:2568$319_Y + attribute \src "ls180.v:2568.373-2568.444" + wire $eq$ls180.v:2568$320_Y + attribute \src "ls180.v:2569.299-2569.368" + wire $eq$ls180.v:2569$332_Y + attribute \src "ls180.v:2569.373-2569.444" + wire $eq$ls180.v:2569$333_Y + attribute \src "ls180.v:2599.299-2599.368" + wire $eq$ls180.v:2599$351_Y + attribute \src "ls180.v:2599.373-2599.444" + wire $eq$ls180.v:2599$352_Y + attribute \src "ls180.v:2600.299-2600.368" + wire $eq$ls180.v:2600$364_Y + attribute \src "ls180.v:2600.373-2600.444" + wire $eq$ls180.v:2600$365_Y + attribute \src "ls180.v:2601.299-2601.368" + wire $eq$ls180.v:2601$377_Y + attribute \src "ls180.v:2601.373-2601.444" + wire $eq$ls180.v:2601$378_Y + attribute \src "ls180.v:2602.299-2602.368" + wire $eq$ls180.v:2602$390_Y + attribute \src "ls180.v:2602.373-2602.444" + wire $eq$ls180.v:2602$391_Y + attribute \src "ls180.v:2631.68-2631.98" + wire $eq$ls180.v:2631$400_Y + attribute \src "ls180.v:2634.68-2634.98" + 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\src "ls180.v:2747.295-2747.333" + wire $eq$ls180.v:2747$470_Y + attribute \src "ls180.v:2752.47-2752.82" + wire $eq$ls180.v:2752$479_Y + attribute \src "ls180.v:2752.145-2752.183" + wire $eq$ls180.v:2752$480_Y + attribute \src "ls180.v:2752.220-2752.258" + wire $eq$ls180.v:2752$483_Y + attribute \src "ls180.v:2752.295-2752.333" + wire $eq$ls180.v:2752$486_Y + attribute \src "ls180.v:2757.47-2757.82" + wire $eq$ls180.v:2757$495_Y + attribute \src "ls180.v:2757.145-2757.183" + wire $eq$ls180.v:2757$496_Y + attribute \src "ls180.v:2757.220-2757.258" + wire $eq$ls180.v:2757$499_Y + attribute \src "ls180.v:2757.295-2757.333" + wire $eq$ls180.v:2757$502_Y + attribute \src "ls180.v:2762.39-2762.77" + wire $eq$ls180.v:2762$511_Y + attribute \src "ls180.v:2762.83-2762.118" + wire $eq$ls180.v:2762$512_Y + attribute \src "ls180.v:2762.181-2762.219" + wire $eq$ls180.v:2762$513_Y + attribute \src "ls180.v:2762.256-2762.294" + wire $eq$ls180.v:2762$516_Y + attribute \src "ls180.v:2762.331-2762.369" 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"ls180.v:3097.31-3097.73" + wire $eq$ls180.v:3097$673_Y + attribute \src "ls180.v:3098.31-3098.69" + wire $eq$ls180.v:3098$674_Y + attribute \src "ls180.v:3099.31-3099.73" + wire $eq$ls180.v:3099$675_Y + attribute \src "ls180.v:3163.28-3163.53" + wire $eq$ls180.v:3163$707_Y + attribute \src "ls180.v:3164.36-3164.85" + wire $eq$ls180.v:3164$708_Y + attribute \src "ls180.v:3166.109-3166.157" + wire $eq$ls180.v:3166$710_Y + attribute \src "ls180.v:3167.112-3167.160" + wire $eq$ls180.v:3167$714_Y + attribute \src "ls180.v:3169.111-3169.159" + wire $eq$ls180.v:3169$717_Y + attribute \src "ls180.v:3170.114-3170.162" + wire $eq$ls180.v:3170$721_Y + attribute \src "ls180.v:3172.111-3172.159" + wire $eq$ls180.v:3172$724_Y + attribute \src "ls180.v:3173.114-3173.162" + wire $eq$ls180.v:3173$728_Y + attribute \src "ls180.v:3175.111-3175.159" + wire $eq$ls180.v:3175$731_Y + attribute \src "ls180.v:3176.114-3176.162" + wire $eq$ls180.v:3176$735_Y + attribute \src "ls180.v:3178.111-3178.159" + wire $eq$ls180.v:3178$738_Y + attribute \src "ls180.v:3179.114-3179.162" + wire $eq$ls180.v:3179$742_Y + attribute \src "ls180.v:3181.114-3181.162" + wire $eq$ls180.v:3181$745_Y + attribute \src "ls180.v:3182.117-3182.165" + wire $eq$ls180.v:3182$749_Y + attribute \src "ls180.v:3184.114-3184.162" + wire $eq$ls180.v:3184$752_Y + attribute \src "ls180.v:3185.117-3185.165" + wire $eq$ls180.v:3185$756_Y + attribute \src "ls180.v:3187.114-3187.162" + wire $eq$ls180.v:3187$759_Y + attribute \src "ls180.v:3188.117-3188.165" + wire $eq$ls180.v:3188$763_Y + attribute \src "ls180.v:3190.114-3190.162" + wire $eq$ls180.v:3190$766_Y + attribute \src "ls180.v:3191.117-3191.165" + wire $eq$ls180.v:3191$770_Y + attribute \src "ls180.v:3202.36-3202.85" + wire $eq$ls180.v:3202$772_Y + attribute \src "ls180.v:3204.106-3204.154" + wire $eq$ls180.v:3204$774_Y + attribute \src "ls180.v:3205.109-3205.157" + wire $eq$ls180.v:3205$778_Y + attribute \src "ls180.v:3207.105-3207.153" + wire $eq$ls180.v:3207$781_Y + attribute \src "ls180.v:3208.108-3208.156" + wire $eq$ls180.v:3208$785_Y + attribute \src "ls180.v:3210.107-3210.155" + wire $eq$ls180.v:3210$788_Y + attribute \src "ls180.v:3211.110-3211.158" + wire $eq$ls180.v:3211$792_Y + attribute \src "ls180.v:3216.36-3216.85" + wire $eq$ls180.v:3216$794_Y + attribute \src "ls180.v:3218.106-3218.154" + wire $eq$ls180.v:3218$796_Y + attribute \src "ls180.v:3219.109-3219.157" + wire $eq$ls180.v:3219$800_Y + attribute \src "ls180.v:3221.105-3221.153" + wire $eq$ls180.v:3221$803_Y + attribute \src "ls180.v:3222.108-3222.156" + wire $eq$ls180.v:3222$807_Y + attribute \src "ls180.v:3224.107-3224.155" + wire $eq$ls180.v:3224$810_Y + attribute \src "ls180.v:3225.110-3225.158" + wire $eq$ls180.v:3225$814_Y + attribute \src "ls180.v:3230.36-3230.85" + wire $eq$ls180.v:3230$816_Y + attribute \src "ls180.v:3232.105-3232.151" + wire $eq$ls180.v:3232$818_Y + attribute \src "ls180.v:3233.108-3233.154" + wire $eq$ls180.v:3233$822_Y + attribute \src "ls180.v:3235.104-3235.150" + wire $eq$ls180.v:3235$825_Y + attribute \src "ls180.v:3236.107-3236.153" + wire $eq$ls180.v:3236$829_Y + attribute \src "ls180.v:3244.36-3244.85" + wire $eq$ls180.v:3244$831_Y + attribute \src "ls180.v:3246.116-3246.164" + wire $eq$ls180.v:3246$833_Y + attribute \src "ls180.v:3247.119-3247.167" + wire $eq$ls180.v:3247$837_Y + attribute \src "ls180.v:3249.120-3249.168" + wire $eq$ls180.v:3249$840_Y + attribute \src "ls180.v:3250.123-3250.171" + wire $eq$ls180.v:3250$844_Y + attribute \src "ls180.v:3252.101-3252.149" + wire $eq$ls180.v:3252$847_Y + attribute \src "ls180.v:3253.104-3253.152" + wire $eq$ls180.v:3253$851_Y + attribute \src "ls180.v:3255.120-3255.168" + wire $eq$ls180.v:3255$854_Y + attribute \src "ls180.v:3256.123-3256.171" + wire $eq$ls180.v:3256$858_Y + attribute \src "ls180.v:3258.120-3258.168" + wire $eq$ls180.v:3258$861_Y + attribute \src "ls180.v:3259.123-3259.171" + wire $eq$ls180.v:3259$865_Y + attribute \src "ls180.v:3261.121-3261.169" + wire $eq$ls180.v:3261$868_Y + attribute \src "ls180.v:3262.124-3262.172" + wire $eq$ls180.v:3262$872_Y + attribute \src "ls180.v:3264.119-3264.167" + wire $eq$ls180.v:3264$875_Y + attribute \src "ls180.v:3265.122-3265.170" + wire $eq$ls180.v:3265$879_Y + attribute \src "ls180.v:3267.119-3267.167" + wire $eq$ls180.v:3267$882_Y + attribute \src "ls180.v:3268.122-3268.170" + wire $eq$ls180.v:3268$886_Y + attribute \src "ls180.v:3270.119-3270.167" + wire $eq$ls180.v:3270$889_Y + attribute \src "ls180.v:3271.122-3271.170" + wire $eq$ls180.v:3271$893_Y + attribute \src "ls180.v:3273.119-3273.167" + wire $eq$ls180.v:3273$896_Y + attribute \src "ls180.v:3274.122-3274.170" + wire $eq$ls180.v:3274$900_Y + attribute \src "ls180.v:3289.36-3289.85" + wire $eq$ls180.v:3289$902_Y + attribute \src "ls180.v:3291.108-3291.156" + wire $eq$ls180.v:3291$904_Y + attribute \src "ls180.v:3292.111-3292.159" + wire $eq$ls180.v:3292$908_Y + attribute \src "ls180.v:3294.108-3294.156" + wire $eq$ls180.v:3294$911_Y + attribute \src "ls180.v:3295.111-3295.159" + wire $eq$ls180.v:3295$915_Y + attribute \src "ls180.v:3297.108-3297.156" + wire $eq$ls180.v:3297$918_Y + attribute \src "ls180.v:3298.111-3298.159" + wire $eq$ls180.v:3298$922_Y + attribute \src "ls180.v:3300.108-3300.156" + wire $eq$ls180.v:3300$925_Y + attribute \src "ls180.v:3301.111-3301.159" + wire $eq$ls180.v:3301$929_Y + attribute \src "ls180.v:3303.110-3303.158" + wire $eq$ls180.v:3303$932_Y + attribute \src "ls180.v:3304.113-3304.161" + wire $eq$ls180.v:3304$936_Y + attribute \src "ls180.v:3306.110-3306.158" + wire $eq$ls180.v:3306$939_Y + attribute \src "ls180.v:3307.113-3307.161" + wire $eq$ls180.v:3307$943_Y + attribute \src "ls180.v:3309.110-3309.158" + wire $eq$ls180.v:3309$946_Y + attribute \src "ls180.v:3310.113-3310.161" + wire $eq$ls180.v:3310$950_Y + attribute \src "ls180.v:3312.110-3312.158" + wire $eq$ls180.v:3312$953_Y + attribute \src "ls180.v:3313.113-3313.161" + wire $eq$ls180.v:3313$957_Y + attribute \src "ls180.v:3315.106-3315.154" + wire $eq$ls180.v:3315$960_Y + attribute \src "ls180.v:3316.109-3316.157" + wire $eq$ls180.v:3316$964_Y + attribute \src "ls180.v:3318.116-3318.164" + wire $eq$ls180.v:3318$967_Y + attribute \src "ls180.v:3319.119-3319.167" + wire $eq$ls180.v:3319$971_Y + attribute \src "ls180.v:3321.109-3321.158" + wire $eq$ls180.v:3321$974_Y + attribute \src "ls180.v:3322.112-3322.161" + wire $eq$ls180.v:3322$978_Y + attribute \src "ls180.v:3324.109-3324.158" + wire $eq$ls180.v:3324$981_Y + attribute \src "ls180.v:3325.112-3325.161" + wire $eq$ls180.v:3325$985_Y + attribute \src "ls180.v:3327.109-3327.158" + wire $eq$ls180.v:3327$988_Y + attribute \src "ls180.v:3328.112-3328.161" + wire $eq$ls180.v:3328$992_Y + attribute \src "ls180.v:3330.109-3330.158" + wire $eq$ls180.v:3330$995_Y + attribute \src "ls180.v:3331.112-3331.161" + wire $eq$ls180.v:3331$999_Y + attribute \src "ls180.v:3333.113-3333.162" + wire $eq$ls180.v:3333$1002_Y + attribute \src "ls180.v:3334.116-3334.165" + wire $eq$ls180.v:3334$1006_Y + attribute \src "ls180.v:3336.114-3336.163" + wire $eq$ls180.v:3336$1009_Y + attribute \src "ls180.v:3337.117-3337.166" + wire $eq$ls180.v:3337$1013_Y + attribute \src "ls180.v:3339.113-3339.162" + wire $eq$ls180.v:3339$1016_Y + attribute \src "ls180.v:3340.116-3340.165" + wire $eq$ls180.v:3340$1020_Y + attribute \src "ls180.v:3357.36-3357.85" + wire $eq$ls180.v:3357$1022_Y + attribute \src "ls180.v:3359.86-3359.134" + wire $eq$ls180.v:3359$1024_Y + attribute \src "ls180.v:3360.89-3360.137" + wire $eq$ls180.v:3360$1028_Y + attribute \src "ls180.v:3362.109-3362.157" + wire $eq$ls180.v:3362$1031_Y + attribute \src "ls180.v:3363.112-3363.160" + wire $eq$ls180.v:3363$1035_Y + attribute \src "ls180.v:3365.110-3365.158" + wire $eq$ls180.v:3365$1038_Y + attribute \src "ls180.v:3366.113-3366.161" + wire $eq$ls180.v:3366$1042_Y + attribute \src "ls180.v:3368.101-3368.149" + wire $eq$ls180.v:3368$1045_Y + attribute \src "ls180.v:3369.104-3369.152" + wire $eq$ls180.v:3369$1049_Y + attribute \src "ls180.v:3371.102-3371.150" + wire $eq$ls180.v:3371$1052_Y + attribute \src "ls180.v:3372.105-3372.153" + wire $eq$ls180.v:3372$1056_Y + attribute \src "ls180.v:3374.113-3374.161" + wire $eq$ls180.v:3374$1059_Y + attribute \src "ls180.v:3375.116-3375.164" + wire $eq$ls180.v:3375$1063_Y + attribute \src "ls180.v:3377.110-3377.158" + wire $eq$ls180.v:3377$1066_Y + attribute \src "ls180.v:3378.113-3378.161" + wire $eq$ls180.v:3378$1070_Y + attribute \src "ls180.v:3380.109-3380.157" + wire $eq$ls180.v:3380$1073_Y + attribute \src "ls180.v:3381.112-3381.160" + wire $eq$ls180.v:3381$1077_Y + attribute \src "ls180.v:3391.36-3391.85" + wire $eq$ls180.v:3391$1079_Y + attribute \src "ls180.v:3393.115-3393.163" + wire $eq$ls180.v:3393$1081_Y + attribute \src "ls180.v:3394.118-3394.166" + wire $eq$ls180.v:3394$1085_Y + attribute \src "ls180.v:3396.115-3396.163" + wire $eq$ls180.v:3396$1088_Y + attribute \src "ls180.v:3397.118-3397.166" + wire $eq$ls180.v:3397$1092_Y + attribute \src "ls180.v:3399.115-3399.163" + wire $eq$ls180.v:3399$1095_Y + attribute \src "ls180.v:3400.118-3400.166" + wire $eq$ls180.v:3400$1099_Y + attribute \src "ls180.v:3402.115-3402.163" + wire $eq$ls180.v:3402$1102_Y + attribute \src "ls180.v:3403.118-3403.166" + wire $eq$ls180.v:3403$1106_Y + attribute \src "ls180.v:3763.28-3763.63" + wire $eq$ls180.v:3763$1136_Y + attribute \src "ls180.v:3763.126-3763.164" + wire $eq$ls180.v:3763$1137_Y + attribute \src "ls180.v:3763.201-3763.239" + wire $eq$ls180.v:3763$1140_Y + attribute \src "ls180.v:3763.276-3763.314" + wire $eq$ls180.v:3763$1143_Y + attribute \src "ls180.v:3787.28-3787.63" + wire $eq$ls180.v:3787$1152_Y + attribute \src "ls180.v:3787.126-3787.164" + wire $eq$ls180.v:3787$1153_Y + attribute \src "ls180.v:3787.201-3787.239" + wire $eq$ls180.v:3787$1156_Y + attribute \src "ls180.v:3787.276-3787.314" + wire $eq$ls180.v:3787$1159_Y + attribute \src "ls180.v:3811.28-3811.63" + wire $eq$ls180.v:3811$1168_Y + attribute \src "ls180.v:3811.126-3811.164" + wire $eq$ls180.v:3811$1169_Y + attribute \src "ls180.v:3811.201-3811.239" + wire $eq$ls180.v:3811$1172_Y + attribute \src "ls180.v:3811.276-3811.314" + wire $eq$ls180.v:3811$1175_Y + attribute \src "ls180.v:3835.28-3835.63" + wire $eq$ls180.v:3835$1184_Y + attribute \src "ls180.v:3835.126-3835.164" + wire $eq$ls180.v:3835$1185_Y + attribute \src "ls180.v:3835.201-3835.239" + wire $eq$ls180.v:3835$1188_Y + attribute \src "ls180.v:3835.276-3835.314" + wire $eq$ls180.v:3835$1191_Y + attribute \src "ls180.v:4361.8-4361.33" + wire $eq$ls180.v:4361$1285_Y + attribute \src "ls180.v:4396.8-4396.37" + wire $eq$ls180.v:4396$1296_Y + attribute \src "ls180.v:4416.33-4416.64" + wire $eq$ls180.v:4416$1299_Y + attribute \src "ls180.v:4423.7-4423.38" + wire $eq$ls180.v:4423$1301_Y + attribute \src "ls180.v:4430.7-4430.38" + wire $eq$ls180.v:4430$1302_Y + attribute \src "ls180.v:4438.7-4438.38" + wire $eq$ls180.v:4438$1303_Y + attribute \src "ls180.v:4490.9-4490.49" + wire $eq$ls180.v:4490$1321_Y + attribute \src "ls180.v:4536.9-4536.49" + wire $eq$ls180.v:4536$1337_Y + attribute \src "ls180.v:4582.9-4582.49" + wire $eq$ls180.v:4582$1353_Y + attribute \src "ls180.v:4628.9-4628.49" + wire $eq$ls180.v:4628$1369_Y + attribute \src "ls180.v:4778.9-4778.36" + wire $eq$ls180.v:4778$1381_Y + attribute \src "ls180.v:4793.9-4793.36" + wire $eq$ls180.v:4793$1384_Y + attribute \src "ls180.v:4799.54-4799.92" + wire $eq$ls180.v:4799$1385_Y + attribute \src "ls180.v:4799.136-4799.174" + wire $eq$ls180.v:4799$1388_Y + attribute \src "ls180.v:4799.218-4799.256" + wire $eq$ls180.v:4799$1391_Y + attribute \src "ls180.v:4799.300-4799.338" + wire $eq$ls180.v:4799$1394_Y + attribute \src "ls180.v:4800.55-4800.93" + wire $eq$ls180.v:4800$1397_Y + attribute \src "ls180.v:4800.137-4800.175" + wire $eq$ls180.v:4800$1400_Y + attribute \src "ls180.v:4800.219-4800.257" + wire $eq$ls180.v:4800$1403_Y + attribute \src "ls180.v:4800.301-4800.339" + wire $eq$ls180.v:4800$1406_Y + attribute \src "ls180.v:4835.9-4835.37" + wire $eq$ls180.v:4835$1418_Y + attribute \src "ls180.v:4838.10-4838.38" + wire $eq$ls180.v:4838$1419_Y + attribute \src "ls180.v:4864.9-4864.37" + wire $eq$ls180.v:4864$1425_Y + attribute \src "ls180.v:4869.10-4869.38" + wire $eq$ls180.v:4869$1426_Y + attribute \src "ls180.v:5511.28-5511.31" + wire width 64 $memrd$\mem$ls180.v:5511$1508_DATA + attribute \src "ls180.v:5539.20-5539.25" + wire width 64 $memrd$\mem_1$ls180.v:5539$1558_DATA + attribute \src "ls180.v:5550.12-5550.19" + wire width 25 $memrd$\storage$ls180.v:5550$1566_DATA + attribute \src "ls180.v:5557.63-5557.70" + wire width 25 $memrd$\storage$ls180.v:5557$1568_DATA + attribute \src "ls180.v:5564.14-5564.23" + wire width 25 $memrd$\storage_1$ls180.v:5564$1576_DATA + attribute \src "ls180.v:5571.63-5571.72" + wire width 25 $memrd$\storage_1$ls180.v:5571$1578_DATA + attribute \src "ls180.v:5578.14-5578.23" + wire width 25 $memrd$\storage_2$ls180.v:5578$1586_DATA + attribute \src "ls180.v:5585.63-5585.72" + wire width 25 $memrd$\storage_2$ls180.v:5585$1588_DATA + attribute \src "ls180.v:5592.14-5592.23" + wire width 25 $memrd$\storage_3$ls180.v:5592$1596_DATA + attribute \src "ls180.v:5599.63-5599.72" + wire width 25 $memrd$\storage_3$ls180.v:5599$1598_DATA + attribute \src "ls180.v:5607.14-5607.23" + wire width 10 $memrd$\storage_4$ls180.v:5607$1606_DATA + attribute \src "ls180.v:5612.15-5612.24" + wire width 10 $memrd$\storage_4$ls180.v:5612$1608_DATA + attribute \src "ls180.v:5624.14-5624.23" + wire width 10 $memrd$\storage_5$ls180.v:5624$1616_DATA + attribute \src "ls180.v:5629.15-5629.24" + wire width 10 $memrd$\storage_5$ls180.v:5629$1618_DATA attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem$ls180.v:10146$1_DATA + wire width 6 $memwr$\mem$ls180.v:5493$1_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem$ls180.v:10146$1_EN + wire width 64 $memwr$\mem$ls180.v:5493$1_DATA attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem$ls180.v:10148$2_ADDR + wire width 64 $memwr$\mem$ls180.v:5493$1_EN attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem$ls180.v:10148$2_DATA + wire width 6 $memwr$\mem$ls180.v:5495$2_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem$ls180.v:10148$2_EN + wire width 64 $memwr$\mem$ls180.v:5495$2_DATA attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem$ls180.v:10150$3_ADDR + wire width 64 $memwr$\mem$ls180.v:5495$2_EN attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem$ls180.v:10150$3_DATA + wire width 6 $memwr$\mem$ls180.v:5497$3_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem$ls180.v:10150$3_EN + wire width 64 $memwr$\mem$ls180.v:5497$3_DATA attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem$ls180.v:10152$4_ADDR + wire width 64 $memwr$\mem$ls180.v:5497$3_EN attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem$ls180.v:10152$4_DATA + wire width 6 $memwr$\mem$ls180.v:5499$4_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem$ls180.v:10152$4_EN + wire width 64 $memwr$\mem$ls180.v:5499$4_DATA attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem$ls180.v:10154$5_ADDR + wire width 64 $memwr$\mem$ls180.v:5499$4_EN attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem$ls180.v:10154$5_DATA + wire width 6 $memwr$\mem$ls180.v:5501$5_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem$ls180.v:10154$5_EN + wire width 64 $memwr$\mem$ls180.v:5501$5_DATA attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem$ls180.v:10156$6_ADDR + wire width 64 $memwr$\mem$ls180.v:5501$5_EN attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem$ls180.v:10156$6_DATA + wire width 6 $memwr$\mem$ls180.v:5503$6_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem$ls180.v:10156$6_EN + wire width 64 $memwr$\mem$ls180.v:5503$6_DATA attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem$ls180.v:10158$7_ADDR + wire width 64 $memwr$\mem$ls180.v:5503$6_EN attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem$ls180.v:10158$7_DATA + wire width 6 $memwr$\mem$ls180.v:5505$7_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem$ls180.v:10158$7_EN + wire width 64 $memwr$\mem$ls180.v:5505$7_DATA attribute \src "ls180.v:0.0-0.0" - wire width 6 $memwr$\mem$ls180.v:10160$8_ADDR + wire width 64 $memwr$\mem$ls180.v:5505$7_EN attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem$ls180.v:10160$8_DATA + wire width 6 $memwr$\mem$ls180.v:5507$8_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem$ls180.v:10160$8_EN + wire width 64 $memwr$\mem$ls180.v:5507$8_DATA attribute \src "ls180.v:0.0-0.0" - wire width 4 $memwr$\mem_1$ls180.v:10174$9_ADDR + wire width 64 $memwr$\mem$ls180.v:5507$8_EN attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_1$ls180.v:10174$9_DATA + wire width 4 $memwr$\mem_1$ls180.v:5521$9_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_1$ls180.v:10174$9_EN + wire width 64 $memwr$\mem_1$ls180.v:5521$9_DATA attribute \src "ls180.v:0.0-0.0" - wire width 4 $memwr$\mem_1$ls180.v:10176$10_ADDR + wire width 64 $memwr$\mem_1$ls180.v:5521$9_EN attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_1$ls180.v:10176$10_DATA + wire width 4 $memwr$\mem_1$ls180.v:5523$10_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_1$ls180.v:10176$10_EN + wire width 64 $memwr$\mem_1$ls180.v:5523$10_DATA attribute \src "ls180.v:0.0-0.0" - wire width 4 $memwr$\mem_1$ls180.v:10178$11_ADDR + wire width 64 $memwr$\mem_1$ls180.v:5523$10_EN attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_1$ls180.v:10178$11_DATA + wire width 4 $memwr$\mem_1$ls180.v:5525$11_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_1$ls180.v:10178$11_EN + wire width 64 $memwr$\mem_1$ls180.v:5525$11_DATA attribute \src "ls180.v:0.0-0.0" - wire width 4 $memwr$\mem_1$ls180.v:10180$12_ADDR + wire width 64 $memwr$\mem_1$ls180.v:5525$11_EN attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_1$ls180.v:10180$12_DATA + wire width 4 $memwr$\mem_1$ls180.v:5527$12_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_1$ls180.v:10180$12_EN + wire width 64 $memwr$\mem_1$ls180.v:5527$12_DATA attribute \src "ls180.v:0.0-0.0" - wire width 4 $memwr$\mem_1$ls180.v:10182$13_ADDR + wire width 64 $memwr$\mem_1$ls180.v:5527$12_EN attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_1$ls180.v:10182$13_DATA + wire width 4 $memwr$\mem_1$ls180.v:5529$13_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_1$ls180.v:10182$13_EN + wire width 64 $memwr$\mem_1$ls180.v:5529$13_DATA attribute \src "ls180.v:0.0-0.0" - wire width 4 $memwr$\mem_1$ls180.v:10184$14_ADDR + wire width 64 $memwr$\mem_1$ls180.v:5529$13_EN attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_1$ls180.v:10184$14_DATA + wire width 4 $memwr$\mem_1$ls180.v:5531$14_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_1$ls180.v:10184$14_EN + wire width 64 $memwr$\mem_1$ls180.v:5531$14_DATA attribute \src "ls180.v:0.0-0.0" - wire width 4 $memwr$\mem_1$ls180.v:10186$15_ADDR + wire width 64 $memwr$\mem_1$ls180.v:5531$14_EN attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_1$ls180.v:10186$15_DATA + wire width 4 $memwr$\mem_1$ls180.v:5533$15_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_1$ls180.v:10186$15_EN + wire width 64 $memwr$\mem_1$ls180.v:5533$15_DATA attribute \src "ls180.v:0.0-0.0" - wire width 4 $memwr$\mem_1$ls180.v:10188$16_ADDR + wire width 64 $memwr$\mem_1$ls180.v:5533$15_EN attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_1$ls180.v:10188$16_DATA + wire width 4 $memwr$\mem_1$ls180.v:5535$16_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 64 $memwr$\mem_1$ls180.v:10188$16_EN + wire width 64 $memwr$\mem_1$ls180.v:5535$16_DATA attribute \src "ls180.v:0.0-0.0" - wire width 3 $memwr$\storage$ls180.v:10202$17_ADDR + wire width 64 $memwr$\mem_1$ls180.v:5535$16_EN attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage$ls180.v:10202$17_DATA + wire width 3 $memwr$\storage$ls180.v:5549$17_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage$ls180.v:10202$17_EN + wire width 25 $memwr$\storage$ls180.v:5549$17_DATA attribute \src "ls180.v:0.0-0.0" - wire width 3 $memwr$\storage_1$ls180.v:10216$18_ADDR + wire width 25 $memwr$\storage$ls180.v:5549$17_EN attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage_1$ls180.v:10216$18_DATA + wire width 3 $memwr$\storage_1$ls180.v:5563$18_ADDR attribute \src "ls180.v:0.0-0.0" - wire width 25 $memwr$\storage_1$ls180.v:10216$18_EN + wire width 25 $memwr$\storage_1$ls180.v:5563$18_DATA attribute \src "ls180.v:0.0-0.0" - wire width 3 $memwr$\storage_2$ls180.v:10230$19_ADDR + wire width 25 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"ls180.v:5009.361-5009.434" - wire $xor$ls180.v:5009$842_Y - attribute \src "ls180.v:5009.205-5009.278" - wire $xor$ls180.v:5009$843_Y - attribute \src "ls180.v:5009.164-5009.279" - wire $xor$ls180.v:5009$844_Y - attribute \src "ls180.v:5010.361-5010.434" - wire $xor$ls180.v:5010$845_Y - attribute \src "ls180.v:5010.205-5010.278" - wire $xor$ls180.v:5010$846_Y - attribute \src "ls180.v:5010.164-5010.279" - wire $xor$ls180.v:5010$847_Y - attribute \src "ls180.v:5011.361-5011.434" - wire $xor$ls180.v:5011$848_Y - attribute \src "ls180.v:5011.205-5011.278" - wire $xor$ls180.v:5011$849_Y - attribute \src "ls180.v:5011.164-5011.279" - wire $xor$ls180.v:5011$850_Y - attribute \src "ls180.v:5012.360-5012.432" - wire $xor$ls180.v:5012$851_Y - attribute \src "ls180.v:5012.205-5012.277" - wire $xor$ls180.v:5012$852_Y - attribute \src "ls180.v:5012.164-5012.278" - wire $xor$ls180.v:5012$853_Y - attribute \src "ls180.v:5013.360-5013.432" - wire $xor$ls180.v:5013$854_Y - attribute \src "ls180.v:5013.205-5013.277" - wire $xor$ls180.v:5013$855_Y - attribute \src "ls180.v:5013.164-5013.278" - wire $xor$ls180.v:5013$856_Y - attribute \src "ls180.v:5014.360-5014.432" - wire $xor$ls180.v:5014$857_Y - attribute \src "ls180.v:5014.205-5014.277" - wire $xor$ls180.v:5014$858_Y - attribute \src "ls180.v:5014.164-5014.278" - wire $xor$ls180.v:5014$859_Y - attribute \src "ls180.v:5015.360-5015.432" - wire $xor$ls180.v:5015$860_Y - attribute \src "ls180.v:5015.205-5015.277" - wire $xor$ls180.v:5015$861_Y - attribute \src "ls180.v:5015.164-5015.278" - wire $xor$ls180.v:5015$862_Y - attribute \src "ls180.v:5016.360-5016.432" - wire $xor$ls180.v:5016$863_Y - attribute \src "ls180.v:5016.205-5016.277" - wire $xor$ls180.v:5016$864_Y - attribute \src "ls180.v:5016.164-5016.278" - wire $xor$ls180.v:5016$865_Y - attribute \src "ls180.v:5017.360-5017.432" - wire $xor$ls180.v:5017$866_Y - attribute \src "ls180.v:5017.205-5017.277" - wire $xor$ls180.v:5017$867_Y - attribute \src "ls180.v:5017.164-5017.278" - wire $xor$ls180.v:5017$868_Y - attribute \src "ls180.v:5018.360-5018.432" - wire $xor$ls180.v:5018$869_Y - attribute \src "ls180.v:5018.205-5018.277" - wire $xor$ls180.v:5018$870_Y - attribute \src "ls180.v:5018.164-5018.278" - wire $xor$ls180.v:5018$871_Y - attribute \src "ls180.v:5019.360-5019.432" - wire $xor$ls180.v:5019$872_Y - attribute \src "ls180.v:5019.205-5019.277" - wire $xor$ls180.v:5019$873_Y - attribute \src "ls180.v:5019.164-5019.278" - wire $xor$ls180.v:5019$874_Y - attribute \src "ls180.v:5020.360-5020.432" - wire $xor$ls180.v:5020$875_Y - attribute \src "ls180.v:5020.205-5020.277" - wire $xor$ls180.v:5020$876_Y - attribute \src "ls180.v:5020.164-5020.278" - wire $xor$ls180.v:5020$877_Y - attribute \src "ls180.v:5021.360-5021.432" - wire $xor$ls180.v:5021$878_Y - attribute \src "ls180.v:5021.205-5021.277" - wire $xor$ls180.v:5021$879_Y - attribute \src "ls180.v:5021.164-5021.278" - wire $xor$ls180.v:5021$880_Y - attribute \src "ls180.v:5042.899-5042.983" - wire $xor$ls180.v:5042$894_Y - attribute \src "ls180.v:5042.634-5042.718" - wire $xor$ls180.v:5042$895_Y - attribute \src "ls180.v:5042.588-5042.719" - wire $xor$ls180.v:5042$896_Y - attribute \src "ls180.v:5042.234-5042.318" - wire $xor$ls180.v:5042$897_Y - attribute \src "ls180.v:5042.187-5042.319" - wire $xor$ls180.v:5042$898_Y - attribute \src "ls180.v:5043.899-5043.983" - wire $xor$ls180.v:5043$899_Y - attribute \src "ls180.v:5043.634-5043.718" - wire $xor$ls180.v:5043$900_Y - attribute \src "ls180.v:5043.588-5043.719" - wire $xor$ls180.v:5043$901_Y - attribute \src "ls180.v:5043.234-5043.318" - wire $xor$ls180.v:5043$902_Y - attribute \src "ls180.v:5043.187-5043.319" - wire $xor$ls180.v:5043$903_Y - attribute \src "ls180.v:5052.899-5052.983" - wire $xor$ls180.v:5052$905_Y - attribute \src "ls180.v:5052.634-5052.718" - wire $xor$ls180.v:5052$906_Y - attribute \src "ls180.v:5052.588-5052.719" - wire $xor$ls180.v:5052$907_Y - attribute \src "ls180.v:5052.234-5052.318" - wire $xor$ls180.v:5052$908_Y - attribute \src "ls180.v:5052.187-5052.319" - wire $xor$ls180.v:5052$909_Y - attribute \src "ls180.v:5053.899-5053.983" - wire $xor$ls180.v:5053$910_Y - attribute \src "ls180.v:5053.634-5053.718" - wire $xor$ls180.v:5053$911_Y - attribute \src "ls180.v:5053.588-5053.719" - wire $xor$ls180.v:5053$912_Y - attribute \src "ls180.v:5053.234-5053.318" - wire $xor$ls180.v:5053$913_Y - attribute \src "ls180.v:5053.187-5053.319" - wire $xor$ls180.v:5053$914_Y - attribute \src "ls180.v:5062.899-5062.983" - wire $xor$ls180.v:5062$916_Y - attribute \src "ls180.v:5062.634-5062.718" - wire $xor$ls180.v:5062$917_Y - attribute \src "ls180.v:5062.588-5062.719" - wire $xor$ls180.v:5062$918_Y - attribute \src "ls180.v:5062.234-5062.318" - wire $xor$ls180.v:5062$919_Y - attribute \src "ls180.v:5062.187-5062.319" - wire $xor$ls180.v:5062$920_Y - attribute \src "ls180.v:5063.899-5063.983" - wire $xor$ls180.v:5063$921_Y - attribute \src "ls180.v:5063.634-5063.718" - wire $xor$ls180.v:5063$922_Y - attribute \src "ls180.v:5063.588-5063.719" - wire $xor$ls180.v:5063$923_Y - attribute \src "ls180.v:5063.234-5063.318" - wire $xor$ls180.v:5063$924_Y - attribute \src "ls180.v:5063.187-5063.319" - wire $xor$ls180.v:5063$925_Y - attribute \src "ls180.v:5072.899-5072.983" - wire $xor$ls180.v:5072$927_Y - attribute \src "ls180.v:5072.634-5072.718" - wire $xor$ls180.v:5072$928_Y - attribute \src "ls180.v:5072.588-5072.719" - wire $xor$ls180.v:5072$929_Y - attribute \src "ls180.v:5072.234-5072.318" - wire $xor$ls180.v:5072$930_Y - attribute \src "ls180.v:5072.187-5072.319" - wire $xor$ls180.v:5072$931_Y - attribute \src "ls180.v:5073.899-5073.983" - wire $xor$ls180.v:5073$932_Y - attribute \src "ls180.v:5073.634-5073.718" - wire $xor$ls180.v:5073$933_Y - attribute \src "ls180.v:5073.588-5073.719" - wire $xor$ls180.v:5073$934_Y - attribute \src "ls180.v:5073.234-5073.318" - wire $xor$ls180.v:5073$935_Y - attribute \src "ls180.v:5073.187-5073.319" - wire $xor$ls180.v:5073$936_Y - attribute \src "ls180.v:5224.879-5224.961" - wire $xor$ls180.v:5224$969_Y - attribute \src "ls180.v:5224.620-5224.702" - wire $xor$ls180.v:5224$970_Y - attribute \src "ls180.v:5224.575-5224.703" - wire $xor$ls180.v:5224$971_Y - attribute \src "ls180.v:5224.229-5224.311" - wire $xor$ls180.v:5224$972_Y - attribute \src "ls180.v:5224.183-5224.312" - wire $xor$ls180.v:5224$973_Y - attribute \src "ls180.v:5225.879-5225.961" - wire $xor$ls180.v:5225$974_Y - attribute \src "ls180.v:5225.620-5225.702" - wire $xor$ls180.v:5225$975_Y - attribute \src "ls180.v:5225.575-5225.703" - wire $xor$ls180.v:5225$976_Y - attribute \src "ls180.v:5225.229-5225.311" - wire $xor$ls180.v:5225$977_Y - attribute \src "ls180.v:5225.183-5225.312" - wire $xor$ls180.v:5225$978_Y - attribute \src "ls180.v:5234.879-5234.961" - wire $xor$ls180.v:5234$980_Y - attribute \src "ls180.v:5234.620-5234.702" - wire $xor$ls180.v:5234$981_Y - attribute \src "ls180.v:5234.575-5234.703" - wire $xor$ls180.v:5234$982_Y - attribute \src "ls180.v:5234.229-5234.311" - wire $xor$ls180.v:5234$983_Y - attribute \src "ls180.v:5234.183-5234.312" - wire $xor$ls180.v:5234$984_Y - attribute \src "ls180.v:5235.879-5235.961" - wire $xor$ls180.v:5235$985_Y - attribute \src "ls180.v:5235.620-5235.702" - wire $xor$ls180.v:5235$986_Y - attribute \src "ls180.v:5235.575-5235.703" - wire $xor$ls180.v:5235$987_Y - attribute \src "ls180.v:5235.229-5235.311" - wire $xor$ls180.v:5235$988_Y - attribute \src "ls180.v:5235.183-5235.312" - wire $xor$ls180.v:5235$989_Y - attribute \src "ls180.v:5244.879-5244.961" - wire $xor$ls180.v:5244$991_Y - attribute \src "ls180.v:5244.620-5244.702" - wire $xor$ls180.v:5244$992_Y - attribute \src "ls180.v:5244.575-5244.703" - wire $xor$ls180.v:5244$993_Y - attribute \src "ls180.v:5244.229-5244.311" - wire $xor$ls180.v:5244$994_Y - attribute \src "ls180.v:5244.183-5244.312" - wire $xor$ls180.v:5244$995_Y - attribute \src "ls180.v:5245.183-5245.312" - wire $xor$ls180.v:5245$1000_Y - attribute \src "ls180.v:5245.879-5245.961" - wire $xor$ls180.v:5245$996_Y - attribute \src "ls180.v:5245.620-5245.702" - wire $xor$ls180.v:5245$997_Y - attribute \src "ls180.v:5245.575-5245.703" - wire $xor$ls180.v:5245$998_Y - attribute \src "ls180.v:5245.229-5245.311" - wire $xor$ls180.v:5245$999_Y - attribute \src "ls180.v:5254.879-5254.961" - wire $xor$ls180.v:5254$1002_Y - attribute \src "ls180.v:5254.620-5254.702" - wire $xor$ls180.v:5254$1003_Y - attribute \src "ls180.v:5254.575-5254.703" - wire $xor$ls180.v:5254$1004_Y - attribute \src "ls180.v:5254.229-5254.311" - wire $xor$ls180.v:5254$1005_Y - attribute \src "ls180.v:5254.183-5254.312" - wire $xor$ls180.v:5254$1006_Y - attribute \src "ls180.v:5255.879-5255.961" - wire $xor$ls180.v:5255$1007_Y - attribute \src "ls180.v:5255.620-5255.702" - wire $xor$ls180.v:5255$1008_Y - attribute \src "ls180.v:5255.575-5255.703" - wire $xor$ls180.v:5255$1009_Y - attribute \src "ls180.v:5255.229-5255.311" - wire $xor$ls180.v:5255$1010_Y - attribute \src "ls180.v:5255.183-5255.312" - wire $xor$ls180.v:5255$1011_Y - attribute \src "ls180.v:1768.11-1768.42" - wire width 3 \builder_bankmachine0_next_state - attribute \src "ls180.v:1767.11-1767.37" - wire width 3 \builder_bankmachine0_state - attribute \src "ls180.v:1770.11-1770.42" - wire width 3 \builder_bankmachine1_next_state - attribute \src "ls180.v:1769.11-1769.37" - wire width 3 \builder_bankmachine1_state - attribute \src "ls180.v:1772.11-1772.42" - wire width 3 \builder_bankmachine2_next_state - attribute \src "ls180.v:1771.11-1771.37" - wire width 3 \builder_bankmachine2_state - attribute \src "ls180.v:1774.11-1774.42" - wire width 3 \builder_bankmachine3_next_state - attribute \src "ls180.v:1773.11-1773.37" - wire width 3 \builder_bankmachine3_state - attribute \src "ls180.v:2627.5-2627.34" - wire \builder_comb_rhs_array_muxed0 - attribute \src "ls180.v:2628.12-2628.41" - wire width 13 \builder_comb_rhs_array_muxed1 - attribute \src "ls180.v:2640.5-2640.35" - wire \builder_comb_rhs_array_muxed10 - attribute \src "ls180.v:2641.5-2641.35" - wire \builder_comb_rhs_array_muxed11 - attribute \src "ls180.v:2645.12-2645.42" - wire width 22 \builder_comb_rhs_array_muxed12 - attribute \src "ls180.v:2646.5-2646.35" - wire \builder_comb_rhs_array_muxed13 - attribute \src "ls180.v:2647.5-2647.35" - wire \builder_comb_rhs_array_muxed14 - attribute \src "ls180.v:2648.12-2648.42" - wire width 22 \builder_comb_rhs_array_muxed15 - attribute \src "ls180.v:2649.5-2649.35" - wire \builder_comb_rhs_array_muxed16 - attribute \src "ls180.v:2650.5-2650.35" - wire \builder_comb_rhs_array_muxed17 - attribute \src "ls180.v:2651.12-2651.42" - wire width 22 \builder_comb_rhs_array_muxed18 - attribute \src "ls180.v:2652.5-2652.35" - wire \builder_comb_rhs_array_muxed19 - attribute \src "ls180.v:2629.11-2629.40" - wire width 2 \builder_comb_rhs_array_muxed2 - attribute \src "ls180.v:2653.5-2653.35" - wire \builder_comb_rhs_array_muxed20 - attribute \src "ls180.v:2654.12-2654.42" - wire width 22 \builder_comb_rhs_array_muxed21 - attribute \src "ls180.v:2655.5-2655.35" - wire \builder_comb_rhs_array_muxed22 - attribute \src "ls180.v:2656.5-2656.35" - wire \builder_comb_rhs_array_muxed23 - attribute \src "ls180.v:2657.12-2657.42" - wire width 32 \builder_comb_rhs_array_muxed24 - attribute \src "ls180.v:2658.12-2658.42" - wire width 64 \builder_comb_rhs_array_muxed25 - attribute \src "ls180.v:2659.11-2659.41" - wire width 8 \builder_comb_rhs_array_muxed26 - attribute \src "ls180.v:2660.5-2660.35" - wire \builder_comb_rhs_array_muxed27 - attribute \src "ls180.v:2661.5-2661.35" - wire \builder_comb_rhs_array_muxed28 - attribute \src "ls180.v:2662.5-2662.35" - wire \builder_comb_rhs_array_muxed29 - attribute \src "ls180.v:2630.5-2630.34" - wire \builder_comb_rhs_array_muxed3 - attribute \src "ls180.v:2663.11-2663.41" - wire width 3 \builder_comb_rhs_array_muxed30 - attribute \src "ls180.v:2664.11-2664.41" - wire width 2 \builder_comb_rhs_array_muxed31 - attribute \src "ls180.v:2631.5-2631.34" - wire \builder_comb_rhs_array_muxed4 - attribute \src "ls180.v:2632.5-2632.34" - wire \builder_comb_rhs_array_muxed5 - attribute \src "ls180.v:2636.5-2636.34" - wire \builder_comb_rhs_array_muxed6 - attribute \src "ls180.v:2637.12-2637.41" - wire width 13 \builder_comb_rhs_array_muxed7 - attribute \src "ls180.v:2638.11-2638.40" - wire width 2 \builder_comb_rhs_array_muxed8 - attribute \src "ls180.v:2639.5-2639.34" - wire \builder_comb_rhs_array_muxed9 - attribute \src "ls180.v:2633.5-2633.32" - wire \builder_comb_t_array_muxed0 - attribute \src "ls180.v:2634.5-2634.32" - wire \builder_comb_t_array_muxed1 - attribute \src "ls180.v:2635.5-2635.32" - wire \builder_comb_t_array_muxed2 - attribute \src "ls180.v:2642.5-2642.32" - wire \builder_comb_t_array_muxed3 - attribute \src "ls180.v:2643.5-2643.32" - wire \builder_comb_t_array_muxed4 - attribute \src "ls180.v:2644.5-2644.32" - wire \builder_comb_t_array_muxed5 - attribute \src "ls180.v:1754.5-1754.34" - wire \builder_converter0_next_state - attribute \src "ls180.v:1753.5-1753.29" - wire \builder_converter0_state - attribute \src "ls180.v:1758.5-1758.34" - wire \builder_converter1_next_state - attribute \src "ls180.v:1757.5-1757.29" - wire \builder_converter1_state - attribute \src "ls180.v:1762.5-1762.34" - wire \builder_converter2_next_state - attribute \src "ls180.v:1761.5-1761.29" - wire \builder_converter2_state - attribute \src "ls180.v:1799.5-1799.33" - wire \builder_converter_next_state - attribute \src "ls180.v:1798.5-1798.28" - wire \builder_converter_state - attribute \src "ls180.v:1927.12-1927.25" - wire width 20 \builder_count - attribute \src "ls180.v:2615.13-2615.41" - wire width 14 \builder_csr_interconnect_adr - attribute \src "ls180.v:2618.12-2618.42" - wire width 8 \builder_csr_interconnect_dat_r - attribute \src "ls180.v:2617.12-2617.42" - wire width 8 \builder_csr_interconnect_dat_w - attribute \src "ls180.v:2616.6-2616.33" - wire \builder_csr_interconnect_we - attribute \src "ls180.v:1965.12-1965.42" - wire width 8 \builder_csrbank0_bus_errors0_r - attribute \src "ls180.v:1964.6-1964.37" - wire \builder_csrbank0_bus_errors0_re - attribute \src "ls180.v:1967.12-1967.42" - wire width 8 \builder_csrbank0_bus_errors0_w - attribute \src "ls180.v:1966.6-1966.37" - wire \builder_csrbank0_bus_errors0_we - attribute \src "ls180.v:1961.12-1961.42" - wire width 8 \builder_csrbank0_bus_errors1_r - attribute \src "ls180.v:1960.6-1960.37" - wire \builder_csrbank0_bus_errors1_re - attribute \src "ls180.v:1963.12-1963.42" - wire width 8 \builder_csrbank0_bus_errors1_w - attribute \src "ls180.v:1962.6-1962.37" - wire \builder_csrbank0_bus_errors1_we - attribute \src "ls180.v:1957.12-1957.42" - wire width 8 \builder_csrbank0_bus_errors2_r - attribute \src "ls180.v:1956.6-1956.37" - wire \builder_csrbank0_bus_errors2_re - attribute \src "ls180.v:1959.12-1959.42" - wire width 8 \builder_csrbank0_bus_errors2_w - attribute \src "ls180.v:1958.6-1958.37" - wire \builder_csrbank0_bus_errors2_we - attribute \src "ls180.v:1953.12-1953.42" - wire width 8 \builder_csrbank0_bus_errors3_r - attribute \src "ls180.v:1952.6-1952.37" - wire \builder_csrbank0_bus_errors3_re - attribute \src "ls180.v:1955.12-1955.42" - wire width 8 \builder_csrbank0_bus_errors3_w - attribute \src "ls180.v:1954.6-1954.37" - wire \builder_csrbank0_bus_errors3_we - attribute \src "ls180.v:1933.6-1933.31" - wire \builder_csrbank0_reset0_r - attribute \src "ls180.v:1932.6-1932.32" - wire \builder_csrbank0_reset0_re - attribute \src "ls180.v:1935.6-1935.31" - wire \builder_csrbank0_reset0_w - attribute \src "ls180.v:1934.6-1934.32" - wire \builder_csrbank0_reset0_we - attribute \src "ls180.v:1949.12-1949.39" - wire width 8 \builder_csrbank0_scratch0_r - attribute \src "ls180.v:1948.6-1948.34" - wire \builder_csrbank0_scratch0_re - attribute \src "ls180.v:1951.12-1951.39" - wire width 8 \builder_csrbank0_scratch0_w - attribute \src "ls180.v:1950.6-1950.34" - wire \builder_csrbank0_scratch0_we - attribute \src "ls180.v:1945.12-1945.39" - wire width 8 \builder_csrbank0_scratch1_r - attribute \src "ls180.v:1944.6-1944.34" - wire \builder_csrbank0_scratch1_re - attribute \src "ls180.v:1947.12-1947.39" - wire width 8 \builder_csrbank0_scratch1_w - attribute \src "ls180.v:1946.6-1946.34" - wire \builder_csrbank0_scratch1_we - attribute \src "ls180.v:1941.12-1941.39" - wire width 8 \builder_csrbank0_scratch2_r - attribute \src "ls180.v:1940.6-1940.34" - wire \builder_csrbank0_scratch2_re - attribute \src "ls180.v:1943.12-1943.39" - wire width 8 \builder_csrbank0_scratch2_w - attribute \src "ls180.v:1942.6-1942.34" - wire \builder_csrbank0_scratch2_we - attribute \src "ls180.v:1937.12-1937.39" - wire width 8 \builder_csrbank0_scratch3_r - attribute \src "ls180.v:1936.6-1936.34" - wire \builder_csrbank0_scratch3_re - attribute \src "ls180.v:1939.12-1939.39" - wire width 8 \builder_csrbank0_scratch3_w - attribute \src "ls180.v:1938.6-1938.34" - wire \builder_csrbank0_scratch3_we - attribute \src "ls180.v:1968.6-1968.26" - wire \builder_csrbank0_sel - attribute \src "ls180.v:2439.12-2439.40" - wire width 8 \builder_csrbank10_control0_r - attribute \src "ls180.v:2438.6-2438.35" - wire \builder_csrbank10_control0_re - attribute \src "ls180.v:2441.12-2441.40" - wire width 8 \builder_csrbank10_control0_w - attribute \src "ls180.v:2440.6-2440.35" - wire \builder_csrbank10_control0_we - attribute \src "ls180.v:2435.12-2435.40" - wire width 8 \builder_csrbank10_control1_r - attribute \src "ls180.v:2434.6-2434.35" - wire \builder_csrbank10_control1_re - attribute \src "ls180.v:2437.12-2437.40" - wire width 8 \builder_csrbank10_control1_w - attribute \src "ls180.v:2436.6-2436.35" - wire \builder_csrbank10_control1_we - attribute \src "ls180.v:2455.6-2455.29" - wire \builder_csrbank10_cs0_r - attribute \src "ls180.v:2454.6-2454.30" - wire \builder_csrbank10_cs0_re - attribute \src "ls180.v:2457.6-2457.29" - wire \builder_csrbank10_cs0_w - attribute \src "ls180.v:2456.6-2456.30" - wire \builder_csrbank10_cs0_we - attribute \src "ls180.v:2459.6-2459.35" - wire \builder_csrbank10_loopback0_r - attribute \src "ls180.v:2458.6-2458.36" - wire \builder_csrbank10_loopback0_re - attribute \src "ls180.v:2461.6-2461.35" - wire \builder_csrbank10_loopback0_w - attribute \src "ls180.v:2460.6-2460.36" - wire \builder_csrbank10_loopback0_we - attribute \src "ls180.v:2451.12-2451.36" - wire width 8 \builder_csrbank10_miso_r - attribute \src "ls180.v:2450.6-2450.31" - wire \builder_csrbank10_miso_re - attribute \src "ls180.v:2453.12-2453.36" - wire width 8 \builder_csrbank10_miso_w - attribute \src "ls180.v:2452.6-2452.31" - wire \builder_csrbank10_miso_we - attribute \src "ls180.v:2447.12-2447.37" - wire width 8 \builder_csrbank10_mosi0_r - attribute \src "ls180.v:2446.6-2446.32" - wire \builder_csrbank10_mosi0_re - attribute \src "ls180.v:2449.12-2449.37" - wire width 8 \builder_csrbank10_mosi0_w - attribute \src "ls180.v:2448.6-2448.32" - wire \builder_csrbank10_mosi0_we - attribute \src "ls180.v:2462.6-2462.27" - wire \builder_csrbank10_sel - attribute \src "ls180.v:2443.6-2443.32" - wire \builder_csrbank10_status_r - attribute \src "ls180.v:2442.6-2442.33" - wire \builder_csrbank10_status_re - attribute \src "ls180.v:2445.6-2445.32" - wire \builder_csrbank10_status_w - attribute \src "ls180.v:2444.6-2444.33" - wire \builder_csrbank10_status_we - attribute \src "ls180.v:2500.12-2500.44" - wire width 8 \builder_csrbank11_clk_divider0_r - attribute \src "ls180.v:2499.6-2499.39" - wire \builder_csrbank11_clk_divider0_re - attribute \src "ls180.v:2502.12-2502.44" - wire width 8 \builder_csrbank11_clk_divider0_w - attribute \src "ls180.v:2501.6-2501.39" - wire \builder_csrbank11_clk_divider0_we - attribute \src "ls180.v:2496.12-2496.44" - wire width 8 \builder_csrbank11_clk_divider1_r - attribute \src "ls180.v:2495.6-2495.39" - wire \builder_csrbank11_clk_divider1_re - attribute \src "ls180.v:2498.12-2498.44" - wire width 8 \builder_csrbank11_clk_divider1_w - attribute \src "ls180.v:2497.6-2497.39" - wire \builder_csrbank11_clk_divider1_we - attribute \src "ls180.v:2472.12-2472.40" - wire width 8 \builder_csrbank11_control0_r - attribute \src "ls180.v:2471.6-2471.35" - wire \builder_csrbank11_control0_re - attribute \src "ls180.v:2474.12-2474.40" - wire width 8 \builder_csrbank11_control0_w - attribute \src "ls180.v:2473.6-2473.35" - wire \builder_csrbank11_control0_we - attribute \src "ls180.v:2468.12-2468.40" - wire width 8 \builder_csrbank11_control1_r - attribute \src "ls180.v:2467.6-2467.35" - wire \builder_csrbank11_control1_re - attribute \src "ls180.v:2470.12-2470.40" - wire width 8 \builder_csrbank11_control1_w - attribute \src "ls180.v:2469.6-2469.35" - wire \builder_csrbank11_control1_we - attribute \src "ls180.v:2488.6-2488.29" - wire \builder_csrbank11_cs0_r - attribute \src "ls180.v:2487.6-2487.30" - wire \builder_csrbank11_cs0_re - attribute \src "ls180.v:2490.6-2490.29" - wire \builder_csrbank11_cs0_w - attribute \src "ls180.v:2489.6-2489.30" - wire \builder_csrbank11_cs0_we - attribute \src "ls180.v:2492.6-2492.35" - wire \builder_csrbank11_loopback0_r - attribute \src "ls180.v:2491.6-2491.36" - wire \builder_csrbank11_loopback0_re - attribute \src "ls180.v:2494.6-2494.35" - wire \builder_csrbank11_loopback0_w - attribute \src "ls180.v:2493.6-2493.36" - wire \builder_csrbank11_loopback0_we - attribute \src "ls180.v:2484.12-2484.36" - wire width 8 \builder_csrbank11_miso_r - attribute \src "ls180.v:2483.6-2483.31" - wire \builder_csrbank11_miso_re - attribute \src "ls180.v:2486.12-2486.36" - wire width 8 \builder_csrbank11_miso_w - attribute \src "ls180.v:2485.6-2485.31" - wire \builder_csrbank11_miso_we - attribute \src "ls180.v:2480.12-2480.37" - wire width 8 \builder_csrbank11_mosi0_r - attribute \src "ls180.v:2479.6-2479.32" - wire \builder_csrbank11_mosi0_re - attribute \src "ls180.v:2482.12-2482.37" - wire width 8 \builder_csrbank11_mosi0_w - attribute \src "ls180.v:2481.6-2481.32" - wire \builder_csrbank11_mosi0_we - attribute \src "ls180.v:2503.6-2503.27" - wire \builder_csrbank11_sel - attribute \src "ls180.v:2476.6-2476.32" - wire \builder_csrbank11_status_r - attribute \src "ls180.v:2475.6-2475.33" - wire \builder_csrbank11_status_re - attribute \src "ls180.v:2478.6-2478.32" - wire \builder_csrbank11_status_w - attribute \src "ls180.v:2477.6-2477.33" - wire \builder_csrbank11_status_we - attribute \src "ls180.v:2541.6-2541.29" - wire \builder_csrbank12_en0_r - attribute \src "ls180.v:2540.6-2540.30" - wire \builder_csrbank12_en0_re - attribute \src "ls180.v:2543.6-2543.29" - wire \builder_csrbank12_en0_w - attribute \src "ls180.v:2542.6-2542.30" - wire \builder_csrbank12_en0_we - attribute \src "ls180.v:2565.6-2565.36" - wire \builder_csrbank12_ev_enable0_r - attribute \src "ls180.v:2564.6-2564.37" - wire \builder_csrbank12_ev_enable0_re - attribute \src "ls180.v:2567.6-2567.36" - wire \builder_csrbank12_ev_enable0_w - attribute \src "ls180.v:2566.6-2566.37" - wire \builder_csrbank12_ev_enable0_we - attribute \src "ls180.v:2521.12-2521.37" - wire width 8 \builder_csrbank12_load0_r - attribute \src "ls180.v:2520.6-2520.32" - wire \builder_csrbank12_load0_re - attribute \src "ls180.v:2523.12-2523.37" - wire width 8 \builder_csrbank12_load0_w - attribute \src "ls180.v:2522.6-2522.32" - wire \builder_csrbank12_load0_we - attribute \src "ls180.v:2517.12-2517.37" - wire width 8 \builder_csrbank12_load1_r - attribute \src "ls180.v:2516.6-2516.32" - wire \builder_csrbank12_load1_re - attribute \src "ls180.v:2519.12-2519.37" - wire width 8 \builder_csrbank12_load1_w - attribute \src "ls180.v:2518.6-2518.32" - wire \builder_csrbank12_load1_we - attribute \src "ls180.v:2513.12-2513.37" - wire width 8 \builder_csrbank12_load2_r - attribute \src "ls180.v:2512.6-2512.32" - wire \builder_csrbank12_load2_re - attribute \src "ls180.v:2515.12-2515.37" - wire width 8 \builder_csrbank12_load2_w - attribute \src "ls180.v:2514.6-2514.32" - wire \builder_csrbank12_load2_we - attribute \src "ls180.v:2509.12-2509.37" - wire width 8 \builder_csrbank12_load3_r - attribute \src "ls180.v:2508.6-2508.32" - wire \builder_csrbank12_load3_re - attribute \src "ls180.v:2511.12-2511.37" - wire width 8 \builder_csrbank12_load3_w - attribute \src "ls180.v:2510.6-2510.32" - wire \builder_csrbank12_load3_we - attribute \src "ls180.v:2537.12-2537.39" - wire width 8 \builder_csrbank12_reload0_r - attribute \src "ls180.v:2536.6-2536.34" - wire \builder_csrbank12_reload0_re - attribute \src "ls180.v:2539.12-2539.39" - wire width 8 \builder_csrbank12_reload0_w - attribute \src "ls180.v:2538.6-2538.34" - wire \builder_csrbank12_reload0_we - attribute \src "ls180.v:2533.12-2533.39" - wire width 8 \builder_csrbank12_reload1_r - attribute \src "ls180.v:2532.6-2532.34" - wire \builder_csrbank12_reload1_re - attribute \src "ls180.v:2535.12-2535.39" - wire width 8 \builder_csrbank12_reload1_w - attribute \src "ls180.v:2534.6-2534.34" - wire \builder_csrbank12_reload1_we - attribute \src "ls180.v:2529.12-2529.39" - wire width 8 \builder_csrbank12_reload2_r - attribute \src "ls180.v:2528.6-2528.34" - wire \builder_csrbank12_reload2_re - attribute \src "ls180.v:2531.12-2531.39" - wire width 8 \builder_csrbank12_reload2_w - attribute \src "ls180.v:2530.6-2530.34" - wire \builder_csrbank12_reload2_we - attribute \src "ls180.v:2525.12-2525.39" - wire width 8 \builder_csrbank12_reload3_r - attribute \src "ls180.v:2524.6-2524.34" - wire \builder_csrbank12_reload3_re - attribute \src "ls180.v:2527.12-2527.39" - wire width 8 \builder_csrbank12_reload3_w - attribute \src "ls180.v:2526.6-2526.34" - wire \builder_csrbank12_reload3_we - attribute \src "ls180.v:2568.6-2568.27" - wire \builder_csrbank12_sel - attribute \src "ls180.v:2545.6-2545.39" - wire \builder_csrbank12_update_value0_r - attribute \src "ls180.v:2544.6-2544.40" - wire \builder_csrbank12_update_value0_re - attribute \src "ls180.v:2547.6-2547.39" - wire \builder_csrbank12_update_value0_w - attribute \src "ls180.v:2546.6-2546.40" - wire \builder_csrbank12_update_value0_we - attribute \src "ls180.v:2561.12-2561.38" - wire width 8 \builder_csrbank12_value0_r - attribute \src "ls180.v:2560.6-2560.33" - wire \builder_csrbank12_value0_re - attribute \src "ls180.v:2563.12-2563.38" - wire width 8 \builder_csrbank12_value0_w - attribute \src "ls180.v:2562.6-2562.33" - wire \builder_csrbank12_value0_we - attribute \src "ls180.v:2557.12-2557.38" - wire width 8 \builder_csrbank12_value1_r - attribute \src "ls180.v:2556.6-2556.33" - wire \builder_csrbank12_value1_re - attribute \src "ls180.v:2559.12-2559.38" - wire width 8 \builder_csrbank12_value1_w - attribute \src "ls180.v:2558.6-2558.33" - wire \builder_csrbank12_value1_we - attribute \src "ls180.v:2553.12-2553.38" - wire width 8 \builder_csrbank12_value2_r - attribute \src "ls180.v:2552.6-2552.33" - wire \builder_csrbank12_value2_re - attribute \src "ls180.v:2555.12-2555.38" - wire width 8 \builder_csrbank12_value2_w - attribute \src "ls180.v:2554.6-2554.33" - wire \builder_csrbank12_value2_we - attribute \src "ls180.v:2549.12-2549.38" - wire width 8 \builder_csrbank12_value3_r - attribute \src "ls180.v:2548.6-2548.33" - wire \builder_csrbank12_value3_re - attribute \src "ls180.v:2551.12-2551.38" - wire width 8 \builder_csrbank12_value3_w - attribute \src "ls180.v:2550.6-2550.33" - wire \builder_csrbank12_value3_we - attribute \src "ls180.v:2582.12-2582.42" - wire width 2 \builder_csrbank13_ev_enable0_r - attribute \src "ls180.v:2581.6-2581.37" - wire \builder_csrbank13_ev_enable0_re - attribute \src "ls180.v:2584.12-2584.42" - wire width 2 \builder_csrbank13_ev_enable0_w - attribute \src "ls180.v:2583.6-2583.37" - wire \builder_csrbank13_ev_enable0_we - attribute \src "ls180.v:2578.6-2578.33" - wire \builder_csrbank13_rxempty_r - attribute \src "ls180.v:2577.6-2577.34" - wire \builder_csrbank13_rxempty_re - attribute \src "ls180.v:2580.6-2580.33" - wire \builder_csrbank13_rxempty_w - attribute \src "ls180.v:2579.6-2579.34" - wire \builder_csrbank13_rxempty_we - attribute \src "ls180.v:2590.6-2590.32" - wire \builder_csrbank13_rxfull_r - attribute \src "ls180.v:2589.6-2589.33" - wire \builder_csrbank13_rxfull_re - attribute \src "ls180.v:2592.6-2592.32" - wire \builder_csrbank13_rxfull_w - attribute \src "ls180.v:2591.6-2591.33" - wire \builder_csrbank13_rxfull_we - attribute \src "ls180.v:2593.6-2593.27" - wire \builder_csrbank13_sel - attribute \src "ls180.v:2586.6-2586.33" - wire \builder_csrbank13_txempty_r - attribute \src "ls180.v:2585.6-2585.34" - wire \builder_csrbank13_txempty_re - attribute \src "ls180.v:2588.6-2588.33" - wire \builder_csrbank13_txempty_w - attribute \src "ls180.v:2587.6-2587.34" - wire \builder_csrbank13_txempty_we - attribute \src "ls180.v:2574.6-2574.32" - wire \builder_csrbank13_txfull_r - attribute \src "ls180.v:2573.6-2573.33" - wire \builder_csrbank13_txfull_re - attribute \src "ls180.v:2576.6-2576.32" - wire \builder_csrbank13_txfull_w - attribute \src "ls180.v:2575.6-2575.33" - wire \builder_csrbank13_txfull_we - attribute \src "ls180.v:2614.6-2614.27" - wire \builder_csrbank14_sel - attribute \src "ls180.v:2611.12-2611.44" - wire width 8 \builder_csrbank14_tuning_word0_r - attribute \src "ls180.v:2610.6-2610.39" - wire \builder_csrbank14_tuning_word0_re - attribute \src "ls180.v:2613.12-2613.44" - wire width 8 \builder_csrbank14_tuning_word0_w - attribute \src "ls180.v:2612.6-2612.39" - wire \builder_csrbank14_tuning_word0_we - attribute \src "ls180.v:2607.12-2607.44" - wire width 8 \builder_csrbank14_tuning_word1_r - attribute \src "ls180.v:2606.6-2606.39" - wire \builder_csrbank14_tuning_word1_re - attribute \src "ls180.v:2609.12-2609.44" - wire width 8 \builder_csrbank14_tuning_word1_w - attribute \src "ls180.v:2608.6-2608.39" - wire \builder_csrbank14_tuning_word1_we - attribute \src "ls180.v:2603.12-2603.44" - wire width 8 \builder_csrbank14_tuning_word2_r - attribute \src "ls180.v:2602.6-2602.39" - wire \builder_csrbank14_tuning_word2_re - attribute \src "ls180.v:2605.12-2605.44" - wire width 8 \builder_csrbank14_tuning_word2_w - attribute \src "ls180.v:2604.6-2604.39" - wire \builder_csrbank14_tuning_word2_we - attribute \src "ls180.v:2599.12-2599.44" - wire width 8 \builder_csrbank14_tuning_word3_r - attribute \src "ls180.v:2598.6-2598.39" - wire \builder_csrbank14_tuning_word3_re - attribute \src "ls180.v:2601.12-2601.44" - wire width 8 \builder_csrbank14_tuning_word3_w - attribute \src "ls180.v:2600.6-2600.39" - wire \builder_csrbank14_tuning_word3_we - attribute \src "ls180.v:1986.12-1986.34" - wire width 8 \builder_csrbank1_in0_r - attribute \src "ls180.v:1985.6-1985.29" - wire \builder_csrbank1_in0_re - attribute \src "ls180.v:1988.12-1988.34" - wire width 8 \builder_csrbank1_in0_w - attribute \src "ls180.v:1987.6-1987.29" - wire \builder_csrbank1_in0_we - attribute \src "ls180.v:1982.12-1982.34" - wire width 8 \builder_csrbank1_in1_r - attribute \src "ls180.v:1981.6-1981.29" - wire \builder_csrbank1_in1_re - attribute \src "ls180.v:1984.12-1984.34" - wire width 8 \builder_csrbank1_in1_w - attribute \src "ls180.v:1983.6-1983.29" - wire \builder_csrbank1_in1_we - attribute \src "ls180.v:1978.12-1978.34" - wire width 8 \builder_csrbank1_oe0_r - attribute \src "ls180.v:1977.6-1977.29" - wire \builder_csrbank1_oe0_re - attribute \src "ls180.v:1980.12-1980.34" - wire width 8 \builder_csrbank1_oe0_w - attribute \src "ls180.v:1979.6-1979.29" - wire \builder_csrbank1_oe0_we - attribute \src "ls180.v:1974.12-1974.34" - wire width 8 \builder_csrbank1_oe1_r - attribute \src "ls180.v:1973.6-1973.29" - wire \builder_csrbank1_oe1_re - attribute \src "ls180.v:1976.12-1976.34" - wire width 8 \builder_csrbank1_oe1_w - attribute \src "ls180.v:1975.6-1975.29" - wire \builder_csrbank1_oe1_we - attribute \src "ls180.v:1994.12-1994.35" - wire width 8 \builder_csrbank1_out0_r - attribute \src "ls180.v:1993.6-1993.30" - wire \builder_csrbank1_out0_re - attribute \src "ls180.v:1996.12-1996.35" - wire width 8 \builder_csrbank1_out0_w - attribute \src "ls180.v:1995.6-1995.30" - wire \builder_csrbank1_out0_we - attribute \src "ls180.v:1990.12-1990.35" - wire width 8 \builder_csrbank1_out1_r - attribute \src "ls180.v:1989.6-1989.30" - wire \builder_csrbank1_out1_re - attribute \src "ls180.v:1992.12-1992.35" - wire width 8 \builder_csrbank1_out1_w - attribute \src "ls180.v:1991.6-1991.30" - wire \builder_csrbank1_out1_we - attribute \src "ls180.v:1997.6-1997.26" - wire \builder_csrbank1_sel - attribute \src "ls180.v:2007.6-2007.26" - wire \builder_csrbank2_r_r - attribute \src "ls180.v:2006.6-2006.27" - wire \builder_csrbank2_r_re - attribute \src "ls180.v:2009.6-2009.26" - wire \builder_csrbank2_r_w - attribute \src "ls180.v:2008.6-2008.27" - wire \builder_csrbank2_r_we - attribute \src "ls180.v:2010.6-2010.26" - wire \builder_csrbank2_sel - attribute \src "ls180.v:2003.12-2003.33" - wire width 3 \builder_csrbank2_w0_r - attribute \src "ls180.v:2002.6-2002.28" - wire \builder_csrbank2_w0_re - attribute \src "ls180.v:2005.12-2005.33" - wire width 3 \builder_csrbank2_w0_w - attribute \src "ls180.v:2004.6-2004.28" - wire \builder_csrbank2_w0_we - attribute \src "ls180.v:2016.6-2016.32" - wire \builder_csrbank3_enable0_r - attribute \src "ls180.v:2015.6-2015.33" - wire \builder_csrbank3_enable0_re - attribute \src "ls180.v:2018.6-2018.32" - wire \builder_csrbank3_enable0_w - attribute \src "ls180.v:2017.6-2017.33" - wire \builder_csrbank3_enable0_we - attribute \src "ls180.v:2048.12-2048.38" - wire width 8 \builder_csrbank3_period0_r - attribute \src "ls180.v:2047.6-2047.33" - wire \builder_csrbank3_period0_re - attribute \src "ls180.v:2050.12-2050.38" - wire width 8 \builder_csrbank3_period0_w - attribute \src "ls180.v:2049.6-2049.33" - wire \builder_csrbank3_period0_we - attribute \src "ls180.v:2044.12-2044.38" - wire width 8 \builder_csrbank3_period1_r - attribute \src "ls180.v:2043.6-2043.33" - wire \builder_csrbank3_period1_re - attribute \src "ls180.v:2046.12-2046.38" - wire width 8 \builder_csrbank3_period1_w - attribute \src "ls180.v:2045.6-2045.33" - wire \builder_csrbank3_period1_we - attribute \src "ls180.v:2040.12-2040.38" - wire width 8 \builder_csrbank3_period2_r - attribute \src "ls180.v:2039.6-2039.33" - wire \builder_csrbank3_period2_re - attribute \src "ls180.v:2042.12-2042.38" - wire width 8 \builder_csrbank3_period2_w - attribute \src "ls180.v:2041.6-2041.33" - wire \builder_csrbank3_period2_we - attribute \src "ls180.v:2036.12-2036.38" - wire width 8 \builder_csrbank3_period3_r - attribute \src "ls180.v:2035.6-2035.33" - wire \builder_csrbank3_period3_re - attribute \src "ls180.v:2038.12-2038.38" - wire width 8 \builder_csrbank3_period3_w - attribute \src "ls180.v:2037.6-2037.33" - wire \builder_csrbank3_period3_we - attribute \src "ls180.v:2051.6-2051.26" - wire \builder_csrbank3_sel - attribute \src "ls180.v:2032.12-2032.37" - wire width 8 \builder_csrbank3_width0_r - attribute \src "ls180.v:2031.6-2031.32" - wire \builder_csrbank3_width0_re - attribute \src "ls180.v:2034.12-2034.37" - wire width 8 \builder_csrbank3_width0_w - attribute \src "ls180.v:2033.6-2033.32" - wire \builder_csrbank3_width0_we - attribute \src "ls180.v:2028.12-2028.37" - wire width 8 \builder_csrbank3_width1_r - attribute \src "ls180.v:2027.6-2027.32" - wire \builder_csrbank3_width1_re - attribute \src "ls180.v:2030.12-2030.37" - wire width 8 \builder_csrbank3_width1_w - attribute \src "ls180.v:2029.6-2029.32" - wire \builder_csrbank3_width1_we - attribute \src "ls180.v:2024.12-2024.37" - wire width 8 \builder_csrbank3_width2_r - attribute \src "ls180.v:2023.6-2023.32" - wire \builder_csrbank3_width2_re - attribute \src "ls180.v:2026.12-2026.37" - wire width 8 \builder_csrbank3_width2_w - attribute \src "ls180.v:2025.6-2025.32" - wire \builder_csrbank3_width2_we - attribute \src "ls180.v:2020.12-2020.37" - wire width 8 \builder_csrbank3_width3_r - attribute \src "ls180.v:2019.6-2019.32" - wire \builder_csrbank3_width3_re - attribute \src "ls180.v:2022.12-2022.37" - wire width 8 \builder_csrbank3_width3_w - attribute \src "ls180.v:2021.6-2021.32" - wire \builder_csrbank3_width3_we - attribute \src "ls180.v:2057.6-2057.32" - wire \builder_csrbank4_enable0_r - attribute \src "ls180.v:2056.6-2056.33" - wire \builder_csrbank4_enable0_re - attribute \src "ls180.v:2059.6-2059.32" - wire \builder_csrbank4_enable0_w - attribute \src "ls180.v:2058.6-2058.33" - wire \builder_csrbank4_enable0_we - attribute \src "ls180.v:2089.12-2089.38" - wire width 8 \builder_csrbank4_period0_r - attribute \src "ls180.v:2088.6-2088.33" - wire \builder_csrbank4_period0_re - attribute \src "ls180.v:2091.12-2091.38" - wire width 8 \builder_csrbank4_period0_w - attribute \src "ls180.v:2090.6-2090.33" - wire \builder_csrbank4_period0_we - attribute \src "ls180.v:2085.12-2085.38" - wire width 8 \builder_csrbank4_period1_r - attribute \src "ls180.v:2084.6-2084.33" - wire \builder_csrbank4_period1_re - attribute \src "ls180.v:2087.12-2087.38" - wire width 8 \builder_csrbank4_period1_w - attribute \src "ls180.v:2086.6-2086.33" - wire \builder_csrbank4_period1_we - attribute \src "ls180.v:2081.12-2081.38" - wire width 8 \builder_csrbank4_period2_r - attribute \src "ls180.v:2080.6-2080.33" - wire \builder_csrbank4_period2_re - attribute \src "ls180.v:2083.12-2083.38" - wire width 8 \builder_csrbank4_period2_w - attribute \src "ls180.v:2082.6-2082.33" - wire \builder_csrbank4_period2_we - attribute \src "ls180.v:2077.12-2077.38" - wire width 8 \builder_csrbank4_period3_r - attribute \src "ls180.v:2076.6-2076.33" - wire \builder_csrbank4_period3_re - attribute \src "ls180.v:2079.12-2079.38" - wire width 8 \builder_csrbank4_period3_w - attribute \src "ls180.v:2078.6-2078.33" - wire \builder_csrbank4_period3_we - attribute \src "ls180.v:2092.6-2092.26" - wire \builder_csrbank4_sel - attribute \src "ls180.v:2073.12-2073.37" - wire width 8 \builder_csrbank4_width0_r - attribute \src "ls180.v:2072.6-2072.32" - wire \builder_csrbank4_width0_re - attribute \src "ls180.v:2075.12-2075.37" - wire width 8 \builder_csrbank4_width0_w - attribute \src "ls180.v:2074.6-2074.32" - wire \builder_csrbank4_width0_we - attribute \src "ls180.v:2069.12-2069.37" - wire width 8 \builder_csrbank4_width1_r - attribute \src "ls180.v:2068.6-2068.32" - wire \builder_csrbank4_width1_re - attribute \src "ls180.v:2071.12-2071.37" - wire width 8 \builder_csrbank4_width1_w - attribute \src "ls180.v:2070.6-2070.32" - wire \builder_csrbank4_width1_we - attribute \src "ls180.v:2065.12-2065.37" - wire width 8 \builder_csrbank4_width2_r - attribute \src "ls180.v:2064.6-2064.32" - wire \builder_csrbank4_width2_re - attribute \src "ls180.v:2067.12-2067.37" - wire width 8 \builder_csrbank4_width2_w - attribute \src "ls180.v:2066.6-2066.32" - wire \builder_csrbank4_width2_we - attribute \src "ls180.v:2061.12-2061.37" - wire width 8 \builder_csrbank4_width3_r - attribute \src "ls180.v:2060.6-2060.32" - wire \builder_csrbank4_width3_re - attribute \src "ls180.v:2063.12-2063.37" - wire width 8 \builder_csrbank4_width3_w - attribute \src "ls180.v:2062.6-2062.32" - wire \builder_csrbank4_width3_we - attribute \src "ls180.v:2126.12-2126.40" - wire width 8 \builder_csrbank5_dma_base0_r - attribute \src "ls180.v:2125.6-2125.35" - wire \builder_csrbank5_dma_base0_re - attribute \src "ls180.v:2128.12-2128.40" - wire width 8 \builder_csrbank5_dma_base0_w - attribute \src "ls180.v:2127.6-2127.35" - wire \builder_csrbank5_dma_base0_we - attribute \src "ls180.v:2122.12-2122.40" - wire width 8 \builder_csrbank5_dma_base1_r - attribute \src "ls180.v:2121.6-2121.35" - wire \builder_csrbank5_dma_base1_re - attribute \src "ls180.v:2124.12-2124.40" - wire width 8 \builder_csrbank5_dma_base1_w - attribute \src "ls180.v:2123.6-2123.35" - wire \builder_csrbank5_dma_base1_we - attribute \src "ls180.v:2118.12-2118.40" - wire width 8 \builder_csrbank5_dma_base2_r - attribute \src "ls180.v:2117.6-2117.35" - wire \builder_csrbank5_dma_base2_re - attribute \src "ls180.v:2120.12-2120.40" - wire width 8 \builder_csrbank5_dma_base2_w - attribute \src "ls180.v:2119.6-2119.35" - wire \builder_csrbank5_dma_base2_we - attribute \src "ls180.v:2114.12-2114.40" - wire width 8 \builder_csrbank5_dma_base3_r - attribute \src "ls180.v:2113.6-2113.35" - wire \builder_csrbank5_dma_base3_re - attribute \src "ls180.v:2116.12-2116.40" - wire width 8 \builder_csrbank5_dma_base3_w - attribute \src "ls180.v:2115.6-2115.35" - wire \builder_csrbank5_dma_base3_we - attribute \src "ls180.v:2110.12-2110.40" - wire width 8 \builder_csrbank5_dma_base4_r - attribute \src "ls180.v:2109.6-2109.35" - wire \builder_csrbank5_dma_base4_re - attribute \src "ls180.v:2112.12-2112.40" - wire width 8 \builder_csrbank5_dma_base4_w - attribute \src "ls180.v:2111.6-2111.35" - wire \builder_csrbank5_dma_base4_we - attribute \src "ls180.v:2106.12-2106.40" - wire width 8 \builder_csrbank5_dma_base5_r - attribute \src "ls180.v:2105.6-2105.35" - wire \builder_csrbank5_dma_base5_re - attribute \src "ls180.v:2108.12-2108.40" - wire width 8 \builder_csrbank5_dma_base5_w - attribute \src "ls180.v:2107.6-2107.35" - wire \builder_csrbank5_dma_base5_we - attribute \src "ls180.v:2102.12-2102.40" - wire width 8 \builder_csrbank5_dma_base6_r - attribute \src "ls180.v:2101.6-2101.35" - wire \builder_csrbank5_dma_base6_re - attribute \src "ls180.v:2104.12-2104.40" - wire width 8 \builder_csrbank5_dma_base6_w - attribute \src "ls180.v:2103.6-2103.35" - wire \builder_csrbank5_dma_base6_we - attribute \src "ls180.v:2098.12-2098.40" - wire width 8 \builder_csrbank5_dma_base7_r - attribute \src "ls180.v:2097.6-2097.35" - wire \builder_csrbank5_dma_base7_re - attribute \src "ls180.v:2100.12-2100.40" - wire width 8 \builder_csrbank5_dma_base7_w - attribute \src "ls180.v:2099.6-2099.35" - wire \builder_csrbank5_dma_base7_we - attribute \src "ls180.v:2150.6-2150.33" - wire \builder_csrbank5_dma_done_r - attribute \src "ls180.v:2149.6-2149.34" - wire \builder_csrbank5_dma_done_re - attribute \src "ls180.v:2152.6-2152.33" - wire \builder_csrbank5_dma_done_w - attribute \src "ls180.v:2151.6-2151.34" - wire \builder_csrbank5_dma_done_we - attribute \src "ls180.v:2146.6-2146.36" - wire \builder_csrbank5_dma_enable0_r - attribute \src "ls180.v:2145.6-2145.37" - wire \builder_csrbank5_dma_enable0_re - attribute \src "ls180.v:2148.6-2148.36" - wire \builder_csrbank5_dma_enable0_w - attribute \src "ls180.v:2147.6-2147.37" - wire \builder_csrbank5_dma_enable0_we - attribute \src "ls180.v:2142.12-2142.42" - wire width 8 \builder_csrbank5_dma_length0_r - attribute \src "ls180.v:2141.6-2141.37" - wire \builder_csrbank5_dma_length0_re - attribute \src "ls180.v:2144.12-2144.42" - wire width 8 \builder_csrbank5_dma_length0_w - attribute \src "ls180.v:2143.6-2143.37" - wire \builder_csrbank5_dma_length0_we - attribute \src "ls180.v:2138.12-2138.42" - wire width 8 \builder_csrbank5_dma_length1_r - attribute \src "ls180.v:2137.6-2137.37" - wire \builder_csrbank5_dma_length1_re - attribute \src "ls180.v:2140.12-2140.42" - wire width 8 \builder_csrbank5_dma_length1_w - attribute \src "ls180.v:2139.6-2139.37" - wire \builder_csrbank5_dma_length1_we - attribute \src "ls180.v:2134.12-2134.42" - wire width 8 \builder_csrbank5_dma_length2_r - attribute \src "ls180.v:2133.6-2133.37" - wire \builder_csrbank5_dma_length2_re - attribute \src "ls180.v:2136.12-2136.42" - wire width 8 \builder_csrbank5_dma_length2_w - attribute \src "ls180.v:2135.6-2135.37" - wire \builder_csrbank5_dma_length2_we - attribute \src "ls180.v:2130.12-2130.42" - wire width 8 \builder_csrbank5_dma_length3_r - attribute \src "ls180.v:2129.6-2129.37" - wire \builder_csrbank5_dma_length3_re - attribute \src "ls180.v:2132.12-2132.42" - wire width 8 \builder_csrbank5_dma_length3_w - attribute \src "ls180.v:2131.6-2131.37" - wire \builder_csrbank5_dma_length3_we - attribute \src "ls180.v:2154.6-2154.34" - wire \builder_csrbank5_dma_loop0_r - attribute \src "ls180.v:2153.6-2153.35" - wire \builder_csrbank5_dma_loop0_re - attribute \src "ls180.v:2156.6-2156.34" - wire \builder_csrbank5_dma_loop0_w - attribute \src "ls180.v:2155.6-2155.35" - wire \builder_csrbank5_dma_loop0_we - attribute \src "ls180.v:2157.6-2157.26" - wire \builder_csrbank5_sel - attribute \src "ls180.v:2287.12-2287.43" - wire width 8 \builder_csrbank6_block_count0_r - attribute \src "ls180.v:2286.6-2286.38" - wire \builder_csrbank6_block_count0_re - attribute \src "ls180.v:2289.12-2289.43" - wire width 8 \builder_csrbank6_block_count0_w - attribute \src "ls180.v:2288.6-2288.38" - wire \builder_csrbank6_block_count0_we - attribute \src "ls180.v:2283.12-2283.43" - wire width 8 \builder_csrbank6_block_count1_r - attribute \src "ls180.v:2282.6-2282.38" - wire \builder_csrbank6_block_count1_re - attribute \src "ls180.v:2285.12-2285.43" - wire width 8 \builder_csrbank6_block_count1_w - attribute \src "ls180.v:2284.6-2284.38" - wire \builder_csrbank6_block_count1_we - attribute \src "ls180.v:2279.12-2279.43" - wire width 8 \builder_csrbank6_block_count2_r - attribute \src "ls180.v:2278.6-2278.38" - wire \builder_csrbank6_block_count2_re - attribute \src "ls180.v:2281.12-2281.43" - wire width 8 \builder_csrbank6_block_count2_w - attribute \src "ls180.v:2280.6-2280.38" - wire \builder_csrbank6_block_count2_we - attribute \src "ls180.v:2275.12-2275.43" - wire width 8 \builder_csrbank6_block_count3_r - attribute \src "ls180.v:2274.6-2274.38" - wire \builder_csrbank6_block_count3_re - attribute \src "ls180.v:2277.12-2277.43" - wire width 8 \builder_csrbank6_block_count3_w - attribute \src "ls180.v:2276.6-2276.38" - wire \builder_csrbank6_block_count3_we - attribute \src "ls180.v:2271.12-2271.44" - wire width 8 \builder_csrbank6_block_length0_r - attribute \src "ls180.v:2270.6-2270.39" - wire \builder_csrbank6_block_length0_re - attribute \src "ls180.v:2273.12-2273.44" - wire width 8 \builder_csrbank6_block_length0_w - attribute \src "ls180.v:2272.6-2272.39" - wire \builder_csrbank6_block_length0_we - attribute \src "ls180.v:2267.12-2267.44" - wire width 2 \builder_csrbank6_block_length1_r - attribute \src "ls180.v:2266.6-2266.39" - wire \builder_csrbank6_block_length1_re - attribute \src "ls180.v:2269.12-2269.44" - wire width 2 \builder_csrbank6_block_length1_w - attribute \src "ls180.v:2268.6-2268.39" - wire \builder_csrbank6_block_length1_we - attribute \src "ls180.v:2175.12-2175.44" - wire width 8 \builder_csrbank6_cmd_argument0_r - attribute \src "ls180.v:2174.6-2174.39" - wire \builder_csrbank6_cmd_argument0_re - attribute \src "ls180.v:2177.12-2177.44" - wire width 8 \builder_csrbank6_cmd_argument0_w - attribute \src "ls180.v:2176.6-2176.39" - wire \builder_csrbank6_cmd_argument0_we - attribute \src "ls180.v:2171.12-2171.44" - wire width 8 \builder_csrbank6_cmd_argument1_r - attribute \src "ls180.v:2170.6-2170.39" - wire \builder_csrbank6_cmd_argument1_re - attribute \src "ls180.v:2173.12-2173.44" - wire width 8 \builder_csrbank6_cmd_argument1_w - attribute \src "ls180.v:2172.6-2172.39" - wire \builder_csrbank6_cmd_argument1_we - attribute \src "ls180.v:2167.12-2167.44" - wire width 8 \builder_csrbank6_cmd_argument2_r - attribute \src "ls180.v:2166.6-2166.39" - wire \builder_csrbank6_cmd_argument2_re - attribute \src "ls180.v:2169.12-2169.44" - wire width 8 \builder_csrbank6_cmd_argument2_w - attribute \src "ls180.v:2168.6-2168.39" - wire \builder_csrbank6_cmd_argument2_we - attribute \src "ls180.v:2163.12-2163.44" - wire width 8 \builder_csrbank6_cmd_argument3_r - attribute \src "ls180.v:2162.6-2162.39" - wire \builder_csrbank6_cmd_argument3_re - attribute \src "ls180.v:2165.12-2165.44" - wire width 8 \builder_csrbank6_cmd_argument3_w - attribute \src "ls180.v:2164.6-2164.39" - wire \builder_csrbank6_cmd_argument3_we - attribute \src "ls180.v:2191.12-2191.43" - wire width 8 \builder_csrbank6_cmd_command0_r - attribute \src "ls180.v:2190.6-2190.38" - wire \builder_csrbank6_cmd_command0_re - attribute \src "ls180.v:2193.12-2193.43" - wire width 8 \builder_csrbank6_cmd_command0_w - attribute \src "ls180.v:2192.6-2192.38" - wire \builder_csrbank6_cmd_command0_we - attribute \src "ls180.v:2187.12-2187.43" - wire width 8 \builder_csrbank6_cmd_command1_r - attribute \src "ls180.v:2186.6-2186.38" - wire \builder_csrbank6_cmd_command1_re - attribute \src "ls180.v:2189.12-2189.43" - wire width 8 \builder_csrbank6_cmd_command1_w - attribute \src "ls180.v:2188.6-2188.38" - wire \builder_csrbank6_cmd_command1_we - attribute \src "ls180.v:2183.12-2183.43" - wire width 8 \builder_csrbank6_cmd_command2_r - attribute \src "ls180.v:2182.6-2182.38" - wire \builder_csrbank6_cmd_command2_re - attribute \src "ls180.v:2185.12-2185.43" - wire width 8 \builder_csrbank6_cmd_command2_w - attribute \src "ls180.v:2184.6-2184.38" - wire \builder_csrbank6_cmd_command2_we - attribute \src "ls180.v:2179.12-2179.43" - wire width 8 \builder_csrbank6_cmd_command3_r - attribute \src "ls180.v:2178.6-2178.38" - wire \builder_csrbank6_cmd_command3_re - attribute \src "ls180.v:2181.12-2181.43" - wire width 8 \builder_csrbank6_cmd_command3_w - attribute \src "ls180.v:2180.6-2180.38" - wire \builder_csrbank6_cmd_command3_we - attribute \src "ls180.v:2259.12-2259.40" - wire width 4 \builder_csrbank6_cmd_event_r - attribute \src "ls180.v:2258.6-2258.35" - wire \builder_csrbank6_cmd_event_re - attribute \src "ls180.v:2261.12-2261.40" - wire width 4 \builder_csrbank6_cmd_event_w - attribute \src "ls180.v:2260.6-2260.35" - wire \builder_csrbank6_cmd_event_we - attribute \src "ls180.v:2255.12-2255.44" - wire width 8 \builder_csrbank6_cmd_response0_r - attribute \src "ls180.v:2254.6-2254.39" - wire \builder_csrbank6_cmd_response0_re - attribute \src "ls180.v:2257.12-2257.44" - wire width 8 \builder_csrbank6_cmd_response0_w - attribute \src "ls180.v:2256.6-2256.39" - wire \builder_csrbank6_cmd_response0_we - attribute \src "ls180.v:2215.12-2215.45" - wire width 8 \builder_csrbank6_cmd_response10_r - attribute \src "ls180.v:2214.6-2214.40" - wire \builder_csrbank6_cmd_response10_re - attribute \src "ls180.v:2217.12-2217.45" - wire width 8 \builder_csrbank6_cmd_response10_w - attribute \src "ls180.v:2216.6-2216.40" - wire \builder_csrbank6_cmd_response10_we - attribute \src "ls180.v:2211.12-2211.45" - wire width 8 \builder_csrbank6_cmd_response11_r - attribute \src "ls180.v:2210.6-2210.40" - wire \builder_csrbank6_cmd_response11_re - attribute \src "ls180.v:2213.12-2213.45" - wire width 8 \builder_csrbank6_cmd_response11_w - attribute \src "ls180.v:2212.6-2212.40" - wire \builder_csrbank6_cmd_response11_we - attribute \src "ls180.v:2207.12-2207.45" - wire width 8 \builder_csrbank6_cmd_response12_r - attribute \src "ls180.v:2206.6-2206.40" - wire \builder_csrbank6_cmd_response12_re - attribute \src "ls180.v:2209.12-2209.45" - wire width 8 \builder_csrbank6_cmd_response12_w - attribute \src "ls180.v:2208.6-2208.40" - wire \builder_csrbank6_cmd_response12_we - attribute \src "ls180.v:2203.12-2203.45" - wire width 8 \builder_csrbank6_cmd_response13_r - attribute \src "ls180.v:2202.6-2202.40" - wire \builder_csrbank6_cmd_response13_re - attribute \src "ls180.v:2205.12-2205.45" - wire width 8 \builder_csrbank6_cmd_response13_w - attribute \src "ls180.v:2204.6-2204.40" - wire \builder_csrbank6_cmd_response13_we - attribute \src "ls180.v:2199.12-2199.45" - wire width 8 \builder_csrbank6_cmd_response14_r - attribute \src "ls180.v:2198.6-2198.40" - wire \builder_csrbank6_cmd_response14_re - attribute \src "ls180.v:2201.12-2201.45" - wire width 8 \builder_csrbank6_cmd_response14_w - attribute \src "ls180.v:2200.6-2200.40" - wire \builder_csrbank6_cmd_response14_we - attribute \src "ls180.v:2195.12-2195.45" - wire width 8 \builder_csrbank6_cmd_response15_r - attribute \src "ls180.v:2194.6-2194.40" - wire \builder_csrbank6_cmd_response15_re - attribute \src "ls180.v:2197.12-2197.45" - wire width 8 \builder_csrbank6_cmd_response15_w - attribute \src "ls180.v:2196.6-2196.40" - wire \builder_csrbank6_cmd_response15_we - attribute \src "ls180.v:2251.12-2251.44" - wire width 8 \builder_csrbank6_cmd_response1_r - attribute \src "ls180.v:2250.6-2250.39" - wire \builder_csrbank6_cmd_response1_re - attribute \src "ls180.v:2253.12-2253.44" - wire width 8 \builder_csrbank6_cmd_response1_w - attribute \src "ls180.v:2252.6-2252.39" - wire \builder_csrbank6_cmd_response1_we - attribute \src "ls180.v:2247.12-2247.44" - wire width 8 \builder_csrbank6_cmd_response2_r - attribute \src "ls180.v:2246.6-2246.39" - wire \builder_csrbank6_cmd_response2_re - attribute \src "ls180.v:2249.12-2249.44" - wire width 8 \builder_csrbank6_cmd_response2_w - attribute \src "ls180.v:2248.6-2248.39" - wire \builder_csrbank6_cmd_response2_we - attribute \src "ls180.v:2243.12-2243.44" - wire width 8 \builder_csrbank6_cmd_response3_r - attribute \src "ls180.v:2242.6-2242.39" - wire \builder_csrbank6_cmd_response3_re - attribute \src "ls180.v:2245.12-2245.44" - wire width 8 \builder_csrbank6_cmd_response3_w - attribute \src "ls180.v:2244.6-2244.39" - wire \builder_csrbank6_cmd_response3_we - attribute \src "ls180.v:2239.12-2239.44" - wire width 8 \builder_csrbank6_cmd_response4_r - attribute \src "ls180.v:2238.6-2238.39" - wire \builder_csrbank6_cmd_response4_re - attribute \src "ls180.v:2241.12-2241.44" - wire width 8 \builder_csrbank6_cmd_response4_w - attribute \src "ls180.v:2240.6-2240.39" - wire \builder_csrbank6_cmd_response4_we - attribute \src "ls180.v:2235.12-2235.44" - wire width 8 \builder_csrbank6_cmd_response5_r - attribute \src "ls180.v:2234.6-2234.39" - wire \builder_csrbank6_cmd_response5_re - attribute \src "ls180.v:2237.12-2237.44" - wire width 8 \builder_csrbank6_cmd_response5_w - attribute \src "ls180.v:2236.6-2236.39" - wire \builder_csrbank6_cmd_response5_we - attribute \src "ls180.v:2231.12-2231.44" - wire width 8 \builder_csrbank6_cmd_response6_r - attribute \src "ls180.v:2230.6-2230.39" - wire \builder_csrbank6_cmd_response6_re - attribute \src "ls180.v:2233.12-2233.44" - wire width 8 \builder_csrbank6_cmd_response6_w - attribute \src "ls180.v:2232.6-2232.39" - wire \builder_csrbank6_cmd_response6_we - attribute \src "ls180.v:2227.12-2227.44" - wire width 8 \builder_csrbank6_cmd_response7_r - attribute \src "ls180.v:2226.6-2226.39" - wire \builder_csrbank6_cmd_response7_re - attribute \src "ls180.v:2229.12-2229.44" - wire width 8 \builder_csrbank6_cmd_response7_w - attribute \src "ls180.v:2228.6-2228.39" - wire \builder_csrbank6_cmd_response7_we - attribute \src "ls180.v:2223.12-2223.44" - wire width 8 \builder_csrbank6_cmd_response8_r - attribute \src "ls180.v:2222.6-2222.39" - wire \builder_csrbank6_cmd_response8_re - attribute \src "ls180.v:2225.12-2225.44" - wire width 8 \builder_csrbank6_cmd_response8_w - attribute \src "ls180.v:2224.6-2224.39" - wire \builder_csrbank6_cmd_response8_we - attribute \src "ls180.v:2219.12-2219.44" - wire width 8 \builder_csrbank6_cmd_response9_r - attribute \src "ls180.v:2218.6-2218.39" - wire \builder_csrbank6_cmd_response9_re - attribute \src "ls180.v:2221.12-2221.44" - wire width 8 \builder_csrbank6_cmd_response9_w - attribute \src "ls180.v:2220.6-2220.39" - wire \builder_csrbank6_cmd_response9_we - attribute \src "ls180.v:2263.12-2263.41" - wire width 4 \builder_csrbank6_data_event_r - attribute \src "ls180.v:2262.6-2262.36" - wire \builder_csrbank6_data_event_re - attribute \src "ls180.v:2265.12-2265.41" - wire width 4 \builder_csrbank6_data_event_w - attribute \src "ls180.v:2264.6-2264.36" - wire \builder_csrbank6_data_event_we - attribute \src "ls180.v:2290.6-2290.26" - wire \builder_csrbank6_sel - attribute \src "ls180.v:2324.12-2324.40" - wire width 8 \builder_csrbank7_dma_base0_r - attribute \src "ls180.v:2323.6-2323.35" - wire \builder_csrbank7_dma_base0_re - attribute \src "ls180.v:2326.12-2326.40" - wire width 8 \builder_csrbank7_dma_base0_w - attribute \src "ls180.v:2325.6-2325.35" - wire \builder_csrbank7_dma_base0_we - attribute \src "ls180.v:2320.12-2320.40" - wire width 8 \builder_csrbank7_dma_base1_r - attribute \src "ls180.v:2319.6-2319.35" - wire \builder_csrbank7_dma_base1_re - attribute \src "ls180.v:2322.12-2322.40" - wire width 8 \builder_csrbank7_dma_base1_w - attribute \src "ls180.v:2321.6-2321.35" - wire \builder_csrbank7_dma_base1_we - attribute \src "ls180.v:2316.12-2316.40" - wire width 8 \builder_csrbank7_dma_base2_r - attribute \src "ls180.v:2315.6-2315.35" - wire \builder_csrbank7_dma_base2_re - attribute \src "ls180.v:2318.12-2318.40" - wire width 8 \builder_csrbank7_dma_base2_w - attribute \src "ls180.v:2317.6-2317.35" - wire \builder_csrbank7_dma_base2_we - attribute \src "ls180.v:2312.12-2312.40" - wire width 8 \builder_csrbank7_dma_base3_r - attribute \src "ls180.v:2311.6-2311.35" - wire \builder_csrbank7_dma_base3_re - attribute \src "ls180.v:2314.12-2314.40" - wire width 8 \builder_csrbank7_dma_base3_w - attribute \src "ls180.v:2313.6-2313.35" - wire \builder_csrbank7_dma_base3_we - attribute \src "ls180.v:2308.12-2308.40" - wire width 8 \builder_csrbank7_dma_base4_r - attribute \src "ls180.v:2307.6-2307.35" - wire \builder_csrbank7_dma_base4_re - attribute \src "ls180.v:2310.12-2310.40" - wire width 8 \builder_csrbank7_dma_base4_w - attribute \src "ls180.v:2309.6-2309.35" - wire \builder_csrbank7_dma_base4_we - attribute \src "ls180.v:2304.12-2304.40" - wire width 8 \builder_csrbank7_dma_base5_r - attribute \src "ls180.v:2303.6-2303.35" - wire \builder_csrbank7_dma_base5_re - attribute \src "ls180.v:2306.12-2306.40" - wire width 8 \builder_csrbank7_dma_base5_w - attribute \src "ls180.v:2305.6-2305.35" - wire \builder_csrbank7_dma_base5_we - attribute \src "ls180.v:2300.12-2300.40" - wire width 8 \builder_csrbank7_dma_base6_r - attribute \src "ls180.v:2299.6-2299.35" - wire \builder_csrbank7_dma_base6_re - attribute \src "ls180.v:2302.12-2302.40" - wire width 8 \builder_csrbank7_dma_base6_w - attribute \src "ls180.v:2301.6-2301.35" - wire \builder_csrbank7_dma_base6_we - attribute \src "ls180.v:2296.12-2296.40" - wire width 8 \builder_csrbank7_dma_base7_r - attribute \src "ls180.v:2295.6-2295.35" - wire \builder_csrbank7_dma_base7_re - attribute \src "ls180.v:2298.12-2298.40" - wire width 8 \builder_csrbank7_dma_base7_w - attribute \src "ls180.v:2297.6-2297.35" - wire \builder_csrbank7_dma_base7_we - attribute \src "ls180.v:2348.6-2348.33" - wire \builder_csrbank7_dma_done_r - attribute \src "ls180.v:2347.6-2347.34" - wire \builder_csrbank7_dma_done_re - attribute \src "ls180.v:2350.6-2350.33" - wire \builder_csrbank7_dma_done_w - attribute \src "ls180.v:2349.6-2349.34" - wire \builder_csrbank7_dma_done_we - attribute \src "ls180.v:2344.6-2344.36" - wire \builder_csrbank7_dma_enable0_r - attribute \src "ls180.v:2343.6-2343.37" - wire \builder_csrbank7_dma_enable0_re - attribute \src "ls180.v:2346.6-2346.36" - wire \builder_csrbank7_dma_enable0_w - attribute \src "ls180.v:2345.6-2345.37" - wire \builder_csrbank7_dma_enable0_we - attribute \src "ls180.v:2340.12-2340.42" - wire width 8 \builder_csrbank7_dma_length0_r - attribute \src "ls180.v:2339.6-2339.37" - wire \builder_csrbank7_dma_length0_re - attribute \src "ls180.v:2342.12-2342.42" - wire width 8 \builder_csrbank7_dma_length0_w - attribute \src "ls180.v:2341.6-2341.37" - wire \builder_csrbank7_dma_length0_we - attribute \src "ls180.v:2336.12-2336.42" - wire width 8 \builder_csrbank7_dma_length1_r - attribute \src "ls180.v:2335.6-2335.37" - wire \builder_csrbank7_dma_length1_re - attribute \src "ls180.v:2338.12-2338.42" - wire width 8 \builder_csrbank7_dma_length1_w - attribute \src "ls180.v:2337.6-2337.37" - wire \builder_csrbank7_dma_length1_we - attribute \src "ls180.v:2332.12-2332.42" - wire width 8 \builder_csrbank7_dma_length2_r - attribute \src "ls180.v:2331.6-2331.37" - wire \builder_csrbank7_dma_length2_re - attribute \src "ls180.v:2334.12-2334.42" - wire width 8 \builder_csrbank7_dma_length2_w - attribute \src "ls180.v:2333.6-2333.37" - wire \builder_csrbank7_dma_length2_we - attribute \src "ls180.v:2328.12-2328.42" - wire width 8 \builder_csrbank7_dma_length3_r - attribute \src "ls180.v:2327.6-2327.37" - wire \builder_csrbank7_dma_length3_re - attribute \src "ls180.v:2330.12-2330.42" - wire width 8 \builder_csrbank7_dma_length3_w - attribute \src "ls180.v:2329.6-2329.37" - wire \builder_csrbank7_dma_length3_we - attribute \src "ls180.v:2352.6-2352.34" - wire \builder_csrbank7_dma_loop0_r - attribute \src "ls180.v:2351.6-2351.35" - wire \builder_csrbank7_dma_loop0_re - attribute \src "ls180.v:2354.6-2354.34" - wire \builder_csrbank7_dma_loop0_w - attribute \src "ls180.v:2353.6-2353.35" - wire \builder_csrbank7_dma_loop0_we - attribute \src "ls180.v:2368.12-2368.42" - wire width 8 \builder_csrbank7_dma_offset0_r - attribute \src "ls180.v:2367.6-2367.37" - wire \builder_csrbank7_dma_offset0_re - attribute \src "ls180.v:2370.12-2370.42" - wire width 8 \builder_csrbank7_dma_offset0_w - attribute \src "ls180.v:2369.6-2369.37" - wire \builder_csrbank7_dma_offset0_we - attribute \src "ls180.v:2364.12-2364.42" - wire width 8 \builder_csrbank7_dma_offset1_r - attribute \src "ls180.v:2363.6-2363.37" - wire \builder_csrbank7_dma_offset1_re - attribute \src "ls180.v:2366.12-2366.42" - wire width 8 \builder_csrbank7_dma_offset1_w - attribute \src "ls180.v:2365.6-2365.37" - wire \builder_csrbank7_dma_offset1_we - attribute \src "ls180.v:2360.12-2360.42" - wire width 8 \builder_csrbank7_dma_offset2_r - attribute \src "ls180.v:2359.6-2359.37" - wire \builder_csrbank7_dma_offset2_re - attribute \src "ls180.v:2362.12-2362.42" - wire width 8 \builder_csrbank7_dma_offset2_w - attribute \src "ls180.v:2361.6-2361.37" - wire \builder_csrbank7_dma_offset2_we - attribute \src "ls180.v:2356.12-2356.42" - wire width 8 \builder_csrbank7_dma_offset3_r - attribute \src "ls180.v:2355.6-2355.37" - wire \builder_csrbank7_dma_offset3_re - attribute \src "ls180.v:2358.12-2358.42" - wire width 8 \builder_csrbank7_dma_offset3_w - attribute \src "ls180.v:2357.6-2357.37" - wire \builder_csrbank7_dma_offset3_we - attribute \src "ls180.v:2371.6-2371.26" - wire \builder_csrbank7_sel - attribute \src "ls180.v:2377.6-2377.36" - wire \builder_csrbank8_card_detect_r - attribute \src "ls180.v:2376.6-2376.37" - wire \builder_csrbank8_card_detect_re - attribute \src "ls180.v:2379.6-2379.36" - wire \builder_csrbank8_card_detect_w - attribute \src "ls180.v:2378.6-2378.37" - wire \builder_csrbank8_card_detect_we - attribute \src "ls180.v:2385.12-2385.47" - wire width 8 \builder_csrbank8_clocker_divider0_r - attribute \src "ls180.v:2384.6-2384.42" - wire \builder_csrbank8_clocker_divider0_re - attribute \src "ls180.v:2387.12-2387.47" - wire width 8 \builder_csrbank8_clocker_divider0_w - attribute \src "ls180.v:2386.6-2386.42" - wire \builder_csrbank8_clocker_divider0_we - attribute \src "ls180.v:2381.6-2381.41" - wire \builder_csrbank8_clocker_divider1_r - attribute \src "ls180.v:2380.6-2380.42" - wire \builder_csrbank8_clocker_divider1_re - attribute \src "ls180.v:2383.6-2383.41" - wire \builder_csrbank8_clocker_divider1_w - attribute \src "ls180.v:2382.6-2382.42" - wire \builder_csrbank8_clocker_divider1_we - attribute \src "ls180.v:2388.6-2388.26" - wire \builder_csrbank8_sel - attribute \src "ls180.v:2394.12-2394.44" - wire width 4 \builder_csrbank9_dfii_control0_r - attribute \src "ls180.v:2393.6-2393.39" - wire \builder_csrbank9_dfii_control0_re - attribute \src "ls180.v:2396.12-2396.44" - wire width 4 \builder_csrbank9_dfii_control0_w - attribute \src "ls180.v:2395.6-2395.39" - wire \builder_csrbank9_dfii_control0_we - attribute \src "ls180.v:2406.12-2406.48" - wire width 8 \builder_csrbank9_dfii_pi0_address0_r - attribute \src "ls180.v:2405.6-2405.43" - wire \builder_csrbank9_dfii_pi0_address0_re - attribute \src "ls180.v:2408.12-2408.48" - wire width 8 \builder_csrbank9_dfii_pi0_address0_w - attribute \src "ls180.v:2407.6-2407.43" - wire \builder_csrbank9_dfii_pi0_address0_we - attribute \src "ls180.v:2402.12-2402.48" - wire width 5 \builder_csrbank9_dfii_pi0_address1_r - attribute \src "ls180.v:2401.6-2401.43" - wire \builder_csrbank9_dfii_pi0_address1_re - attribute \src "ls180.v:2404.12-2404.48" - wire width 5 \builder_csrbank9_dfii_pi0_address1_w - attribute \src "ls180.v:2403.6-2403.43" - wire \builder_csrbank9_dfii_pi0_address1_we - attribute \src "ls180.v:2410.12-2410.49" - wire width 2 \builder_csrbank9_dfii_pi0_baddress0_r - attribute \src "ls180.v:2409.6-2409.44" - wire \builder_csrbank9_dfii_pi0_baddress0_re - attribute \src "ls180.v:2412.12-2412.49" - wire width 2 \builder_csrbank9_dfii_pi0_baddress0_w - attribute \src "ls180.v:2411.6-2411.44" - wire \builder_csrbank9_dfii_pi0_baddress0_we - attribute \src "ls180.v:2398.12-2398.48" - wire width 6 \builder_csrbank9_dfii_pi0_command0_r - attribute \src "ls180.v:2397.6-2397.43" - wire \builder_csrbank9_dfii_pi0_command0_re - attribute \src "ls180.v:2400.12-2400.48" - wire width 6 \builder_csrbank9_dfii_pi0_command0_w - attribute \src "ls180.v:2399.6-2399.43" - wire \builder_csrbank9_dfii_pi0_command0_we - attribute \src "ls180.v:2426.12-2426.47" - wire width 8 \builder_csrbank9_dfii_pi0_rddata0_r - attribute \src "ls180.v:2425.6-2425.42" - wire \builder_csrbank9_dfii_pi0_rddata0_re - attribute \src "ls180.v:2428.12-2428.47" - wire width 8 \builder_csrbank9_dfii_pi0_rddata0_w - attribute \src "ls180.v:2427.6-2427.42" - wire \builder_csrbank9_dfii_pi0_rddata0_we - attribute \src "ls180.v:2422.12-2422.47" - wire width 8 \builder_csrbank9_dfii_pi0_rddata1_r - attribute \src "ls180.v:2421.6-2421.42" - wire \builder_csrbank9_dfii_pi0_rddata1_re - attribute \src "ls180.v:2424.12-2424.47" - wire width 8 \builder_csrbank9_dfii_pi0_rddata1_w - attribute \src "ls180.v:2423.6-2423.42" - wire \builder_csrbank9_dfii_pi0_rddata1_we - attribute \src "ls180.v:2418.12-2418.47" - wire width 8 \builder_csrbank9_dfii_pi0_wrdata0_r - attribute \src "ls180.v:2417.6-2417.42" - wire \builder_csrbank9_dfii_pi0_wrdata0_re - attribute \src "ls180.v:2420.12-2420.47" - wire width 8 \builder_csrbank9_dfii_pi0_wrdata0_w - attribute \src "ls180.v:2419.6-2419.42" - wire \builder_csrbank9_dfii_pi0_wrdata0_we - attribute \src "ls180.v:2414.12-2414.47" - wire width 8 \builder_csrbank9_dfii_pi0_wrdata1_r - attribute \src "ls180.v:2413.6-2413.42" - wire \builder_csrbank9_dfii_pi0_wrdata1_re - attribute \src "ls180.v:2416.12-2416.47" - wire width 8 \builder_csrbank9_dfii_pi0_wrdata1_w - attribute \src "ls180.v:2415.6-2415.42" - wire \builder_csrbank9_dfii_pi0_wrdata1_we - attribute \src "ls180.v:2429.6-2429.26" - wire \builder_csrbank9_sel - attribute \src "ls180.v:1926.6-1926.18" - wire \builder_done - attribute \src "ls180.v:1924.5-1924.18" - wire \builder_error - attribute \src "ls180.v:1921.11-1921.24" - wire width 3 \builder_grant - attribute \src "ls180.v:1928.13-1928.44" - wire width 14 \builder_interface0_bank_bus_adr - attribute \src "ls180.v:1931.11-1931.44" - wire width 8 \builder_interface0_bank_bus_dat_r - attribute \src "ls180.v:1930.12-1930.45" - wire width 8 \builder_interface0_bank_bus_dat_w - attribute \src "ls180.v:1929.6-1929.36" - wire \builder_interface0_bank_bus_we - attribute \src "ls180.v:2430.13-2430.45" - wire width 14 \builder_interface10_bank_bus_adr - attribute \src "ls180.v:2433.11-2433.45" - wire width 8 \builder_interface10_bank_bus_dat_r - attribute \src "ls180.v:2432.12-2432.46" - wire width 8 \builder_interface10_bank_bus_dat_w - attribute \src "ls180.v:2431.6-2431.37" - wire \builder_interface10_bank_bus_we - attribute \src "ls180.v:2463.13-2463.45" - wire width 14 \builder_interface11_bank_bus_adr - attribute \src "ls180.v:2466.11-2466.45" - wire width 8 \builder_interface11_bank_bus_dat_r - attribute \src "ls180.v:2465.12-2465.46" - wire width 8 \builder_interface11_bank_bus_dat_w - attribute \src "ls180.v:2464.6-2464.37" - wire \builder_interface11_bank_bus_we - attribute \src "ls180.v:2504.13-2504.45" - wire width 14 \builder_interface12_bank_bus_adr - attribute \src "ls180.v:2507.11-2507.45" - wire width 8 \builder_interface12_bank_bus_dat_r - attribute \src "ls180.v:2506.12-2506.46" - wire width 8 \builder_interface12_bank_bus_dat_w - attribute \src "ls180.v:2505.6-2505.37" - wire \builder_interface12_bank_bus_we - attribute \src "ls180.v:2569.13-2569.45" - wire width 14 \builder_interface13_bank_bus_adr - attribute \src "ls180.v:2572.11-2572.45" - wire width 8 \builder_interface13_bank_bus_dat_r - attribute \src "ls180.v:2571.12-2571.46" - wire width 8 \builder_interface13_bank_bus_dat_w - attribute \src "ls180.v:2570.6-2570.37" - wire \builder_interface13_bank_bus_we - attribute \src "ls180.v:2594.13-2594.45" - wire width 14 \builder_interface14_bank_bus_adr - attribute \src "ls180.v:2597.11-2597.45" - wire width 8 \builder_interface14_bank_bus_dat_r - attribute \src "ls180.v:2596.12-2596.46" - wire width 8 \builder_interface14_bank_bus_dat_w - attribute \src "ls180.v:2595.6-2595.37" - wire \builder_interface14_bank_bus_we - attribute \src "ls180.v:1969.13-1969.44" - wire width 14 \builder_interface1_bank_bus_adr - attribute \src "ls180.v:1972.11-1972.44" - wire width 8 \builder_interface1_bank_bus_dat_r - attribute \src "ls180.v:1971.12-1971.45" - wire width 8 \builder_interface1_bank_bus_dat_w - attribute \src "ls180.v:1970.6-1970.36" - wire \builder_interface1_bank_bus_we - attribute \src "ls180.v:1998.13-1998.44" - wire width 14 \builder_interface2_bank_bus_adr - attribute \src "ls180.v:2001.11-2001.44" - wire width 8 \builder_interface2_bank_bus_dat_r - attribute \src "ls180.v:2000.12-2000.45" - wire width 8 \builder_interface2_bank_bus_dat_w - attribute \src "ls180.v:1999.6-1999.36" - wire \builder_interface2_bank_bus_we - attribute \src "ls180.v:2011.13-2011.44" - wire width 14 \builder_interface3_bank_bus_adr - attribute \src "ls180.v:2014.11-2014.44" - wire width 8 \builder_interface3_bank_bus_dat_r - attribute \src "ls180.v:2013.12-2013.45" - wire width 8 \builder_interface3_bank_bus_dat_w - attribute \src "ls180.v:2012.6-2012.36" - wire \builder_interface3_bank_bus_we - attribute \src "ls180.v:2052.13-2052.44" - wire width 14 \builder_interface4_bank_bus_adr - attribute \src "ls180.v:2055.11-2055.44" - wire width 8 \builder_interface4_bank_bus_dat_r - attribute \src "ls180.v:2054.12-2054.45" - wire width 8 \builder_interface4_bank_bus_dat_w - attribute \src "ls180.v:2053.6-2053.36" - wire \builder_interface4_bank_bus_we - attribute \src "ls180.v:2093.13-2093.44" - wire width 14 \builder_interface5_bank_bus_adr - attribute \src "ls180.v:2096.11-2096.44" - wire width 8 \builder_interface5_bank_bus_dat_r - attribute \src "ls180.v:2095.12-2095.45" - wire width 8 \builder_interface5_bank_bus_dat_w - attribute \src "ls180.v:2094.6-2094.36" - wire \builder_interface5_bank_bus_we - attribute \src "ls180.v:2158.13-2158.44" - wire width 14 \builder_interface6_bank_bus_adr - attribute \src "ls180.v:2161.11-2161.44" - wire width 8 \builder_interface6_bank_bus_dat_r - attribute \src "ls180.v:2160.12-2160.45" - wire width 8 \builder_interface6_bank_bus_dat_w - attribute \src "ls180.v:2159.6-2159.36" - wire \builder_interface6_bank_bus_we - attribute \src "ls180.v:2291.13-2291.44" - wire width 14 \builder_interface7_bank_bus_adr - attribute \src "ls180.v:2294.11-2294.44" - wire width 8 \builder_interface7_bank_bus_dat_r - attribute \src "ls180.v:2293.12-2293.45" - wire width 8 \builder_interface7_bank_bus_dat_w - attribute \src "ls180.v:2292.6-2292.36" - wire \builder_interface7_bank_bus_we - attribute \src "ls180.v:2372.13-2372.44" - wire width 14 \builder_interface8_bank_bus_adr - attribute \src "ls180.v:2375.11-2375.44" - wire width 8 \builder_interface8_bank_bus_dat_r - attribute \src "ls180.v:2374.12-2374.45" - wire width 8 \builder_interface8_bank_bus_dat_w - attribute \src "ls180.v:2373.6-2373.36" - wire \builder_interface8_bank_bus_we - attribute \src "ls180.v:2389.13-2389.44" - wire width 14 \builder_interface9_bank_bus_adr - attribute \src "ls180.v:2392.11-2392.44" - wire width 8 \builder_interface9_bank_bus_dat_r - attribute \src "ls180.v:2391.12-2391.45" - wire width 8 \builder_interface9_bank_bus_dat_w - attribute \src "ls180.v:2390.6-2390.36" - wire \builder_interface9_bank_bus_we - attribute \src "ls180.v:1886.12-1886.35" - wire width 14 \builder_libresocsim_adr - attribute \src "ls180.v:2623.12-2623.47" - wire width 14 \builder_libresocsim_adr_next_value1 - attribute \src "ls180.v:2624.5-2624.43" - wire \builder_libresocsim_adr_next_value_ce1 - attribute \src "ls180.v:1904.5-1904.48" - wire \builder_libresocsim_converted_interface_ack - attribute \src "ls180.v:1898.13-1898.56" - wire width 30 \builder_libresocsim_converted_interface_adr - attribute \src "ls180.v:1907.12-1907.55" - wire width 2 \builder_libresocsim_converted_interface_bte - attribute \src "ls180.v:1906.12-1906.55" - wire width 3 \builder_libresocsim_converted_interface_cti - attribute \src "ls180.v:1902.6-1902.49" - wire \builder_libresocsim_converted_interface_cyc - attribute \src "ls180.v:1900.12-1900.57" - wire width 64 \builder_libresocsim_converted_interface_dat_r - attribute \src "ls180.v:1899.13-1899.58" - wire width 64 \builder_libresocsim_converted_interface_dat_w - attribute \src "ls180.v:1908.5-1908.48" - wire \builder_libresocsim_converted_interface_err - attribute \src "ls180.v:1901.12-1901.55" - wire width 8 \builder_libresocsim_converted_interface_sel - attribute \src "ls180.v:1903.6-1903.49" - wire \builder_libresocsim_converted_interface_stb - attribute \src "ls180.v:1905.6-1905.48" - wire \builder_libresocsim_converted_interface_we - attribute \src "ls180.v:1889.12-1889.37" - wire width 8 \builder_libresocsim_dat_r - attribute \src "ls180.v:1888.11-1888.36" - wire width 8 \builder_libresocsim_dat_w - attribute \src "ls180.v:2621.11-2621.48" - wire width 8 \builder_libresocsim_dat_w_next_value0 - attribute \src "ls180.v:2622.5-2622.45" - wire \builder_libresocsim_dat_w_next_value_ce0 - attribute \src "ls180.v:1887.5-1887.27" - wire \builder_libresocsim_we - attribute \src "ls180.v:2625.5-2625.39" - wire \builder_libresocsim_we_next_value2 - attribute \src "ls180.v:2626.5-2626.42" - wire \builder_libresocsim_we_next_value_ce2 - attribute \src "ls180.v:1896.5-1896.37" - wire \builder_libresocsim_wishbone_ack - attribute \src "ls180.v:1890.12-1890.44" - wire width 30 \builder_libresocsim_wishbone_adr - attribute \src "ls180.v:1894.5-1894.37" - wire \builder_libresocsim_wishbone_cyc - attribute \src "ls180.v:1892.12-1892.46" - wire width 32 \builder_libresocsim_wishbone_dat_r - attribute \src "ls180.v:1891.12-1891.46" - wire width 32 \builder_libresocsim_wishbone_dat_w - attribute \src "ls180.v:1893.11-1893.43" - wire width 4 \builder_libresocsim_wishbone_sel - attribute \src "ls180.v:1895.5-1895.37" - wire \builder_libresocsim_wishbone_stb - attribute \src "ls180.v:1897.5-1897.36" - wire \builder_libresocsim_wishbone_we - attribute \src "ls180.v:1789.5-1789.20" - wire \builder_locked0 - attribute \src "ls180.v:1790.5-1790.20" - wire \builder_locked1 - attribute \src "ls180.v:1791.5-1791.20" - wire \builder_locked2 - attribute \src "ls180.v:1792.5-1792.20" - wire \builder_locked3 - attribute \src "ls180.v:1776.11-1776.41" - wire width 3 \builder_multiplexer_next_state - attribute \src "ls180.v:1775.11-1775.36" - wire width 3 \builder_multiplexer_state - attribute \no_retiming "true" - attribute \src "ls180.v:2730.32-2730.59" - wire \builder_multiregimpl0_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2731.32-2731.59" - wire \builder_multiregimpl0_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2750.32-2750.60" - wire \builder_multiregimpl10_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2751.32-2751.60" - wire \builder_multiregimpl10_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2752.32-2752.60" - wire \builder_multiregimpl11_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2753.32-2753.60" - wire \builder_multiregimpl11_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2754.32-2754.60" - wire \builder_multiregimpl12_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2755.32-2755.60" - wire \builder_multiregimpl12_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2756.32-2756.60" - wire \builder_multiregimpl13_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2757.32-2757.60" - wire \builder_multiregimpl13_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2758.32-2758.60" - wire \builder_multiregimpl14_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2759.32-2759.60" - wire \builder_multiregimpl14_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2760.32-2760.60" - wire \builder_multiregimpl15_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2761.32-2761.60" - wire \builder_multiregimpl15_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2762.32-2762.60" - wire \builder_multiregimpl16_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2763.32-2763.60" - wire \builder_multiregimpl16_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2732.32-2732.59" - wire \builder_multiregimpl1_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2733.32-2733.59" - wire \builder_multiregimpl1_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2734.32-2734.59" - wire \builder_multiregimpl2_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2735.32-2735.59" - wire \builder_multiregimpl2_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2736.32-2736.59" - wire \builder_multiregimpl3_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2737.32-2737.59" - wire \builder_multiregimpl3_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2738.32-2738.59" - wire \builder_multiregimpl4_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2739.32-2739.59" - wire \builder_multiregimpl4_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2740.32-2740.59" - wire \builder_multiregimpl5_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2741.32-2741.59" - wire \builder_multiregimpl5_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2742.32-2742.59" - wire \builder_multiregimpl6_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2743.32-2743.59" - wire \builder_multiregimpl6_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2744.32-2744.59" - wire \builder_multiregimpl7_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2745.32-2745.59" - wire \builder_multiregimpl7_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2746.32-2746.59" - wire \builder_multiregimpl8_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2747.32-2747.59" - wire \builder_multiregimpl8_regs1 - attribute \no_retiming "true" - attribute \src "ls180.v:2748.32-2748.59" - wire \builder_multiregimpl9_regs0 - attribute \no_retiming "true" - attribute \src "ls180.v:2749.32-2749.59" - wire \builder_multiregimpl9_regs1 - attribute \src "ls180.v:1794.5-1794.36" - wire \builder_new_master_rdata_valid0 - attribute \src "ls180.v:1795.5-1795.36" - wire \builder_new_master_rdata_valid1 - attribute \src "ls180.v:1796.5-1796.36" - wire \builder_new_master_rdata_valid2 - attribute \src "ls180.v:1797.5-1797.36" - wire \builder_new_master_rdata_valid3 - attribute \src "ls180.v:1793.5-1793.35" - wire \builder_new_master_wdata_ready - attribute \src "ls180.v:2620.11-2620.29" - wire width 2 \builder_next_state - attribute \src "ls180.v:1766.11-1766.39" - wire width 2 \builder_refresher_next_state - attribute \src "ls180.v:1765.11-1765.34" - wire width 2 \builder_refresher_state - attribute \src "ls180.v:1920.12-1920.27" - wire width 5 \builder_request - attribute \src "ls180.v:1779.6-1779.28" - wire \builder_roundrobin0_ce - attribute \src "ls180.v:1778.6-1778.31" - wire \builder_roundrobin0_grant - attribute \src "ls180.v:1777.6-1777.33" - wire \builder_roundrobin0_request - attribute \src "ls180.v:1782.6-1782.28" - wire \builder_roundrobin1_ce - attribute \src "ls180.v:1781.6-1781.31" - wire \builder_roundrobin1_grant - attribute \src "ls180.v:1780.6-1780.33" - wire \builder_roundrobin1_request - attribute \src "ls180.v:1785.6-1785.28" - wire \builder_roundrobin2_ce - attribute \src "ls180.v:1784.6-1784.31" - wire \builder_roundrobin2_grant - attribute \src "ls180.v:1783.6-1783.33" - wire \builder_roundrobin2_request - attribute \src "ls180.v:1788.6-1788.28" - wire \builder_roundrobin3_ce - attribute \src "ls180.v:1787.6-1787.31" - wire \builder_roundrobin3_grant - attribute \src "ls180.v:1786.6-1786.33" - wire \builder_roundrobin3_request - attribute \src "ls180.v:1875.11-1875.44" - wire width 2 \builder_sdblock2memdma_next_state - attribute \src "ls180.v:1874.11-1874.39" - wire width 2 \builder_sdblock2memdma_state - attribute \src "ls180.v:1843.5-1843.50" - wire \builder_sdcore_crcupstreaminserter_next_state - attribute \src "ls180.v:1842.5-1842.45" - wire \builder_sdcore_crcupstreaminserter_state - attribute \src "ls180.v:1855.11-1855.40" - wire width 3 \builder_sdcore_fsm_next_state - attribute \src "ls180.v:1854.11-1854.35" - wire width 3 \builder_sdcore_fsm_state - attribute \src "ls180.v:1879.5-1879.42" - wire \builder_sdmem2blockdma_fsm_next_state - attribute \src "ls180.v:1878.5-1878.37" - wire \builder_sdmem2blockdma_fsm_state - attribute \src "ls180.v:1883.11-1883.58" - wire width 2 \builder_sdmem2blockdma_resetinserter_next_state - attribute \src "ls180.v:1882.11-1882.53" - wire width 2 \builder_sdmem2blockdma_resetinserter_state - attribute \src "ls180.v:1831.11-1831.39" - wire width 3 \builder_sdphy_fsm_next_state - attribute \src "ls180.v:1830.11-1830.34" - wire width 3 \builder_sdphy_fsm_state - attribute \src "ls180.v:1819.11-1819.45" - wire width 3 \builder_sdphy_sdphycmdr_next_state - attribute \src "ls180.v:1818.11-1818.40" - wire width 3 \builder_sdphy_sdphycmdr_state - attribute \src "ls180.v:1815.11-1815.45" - wire width 2 \builder_sdphy_sdphycmdw_next_state - attribute \src "ls180.v:1814.11-1814.40" - wire width 2 \builder_sdphy_sdphycmdw_state - attribute \src "ls180.v:1827.5-1827.39" - wire \builder_sdphy_sdphycrcr_next_state - attribute \src "ls180.v:1826.5-1826.34" - wire \builder_sdphy_sdphycrcr_state - attribute \src "ls180.v:1835.11-1835.46" - wire width 3 \builder_sdphy_sdphydatar_next_state - attribute \src "ls180.v:1834.11-1834.41" - wire width 3 \builder_sdphy_sdphydatar_state - attribute \src "ls180.v:1811.5-1811.39" - wire \builder_sdphy_sdphyinit_next_state - attribute \src "ls180.v:1810.5-1810.34" - wire \builder_sdphy_sdphyinit_state - attribute \src "ls180.v:1915.5-1915.23" - wire \builder_shared_ack - attribute \src "ls180.v:1909.13-1909.31" - wire width 30 \builder_shared_adr - attribute \src "ls180.v:1918.12-1918.30" - wire width 2 \builder_shared_bte - attribute \src "ls180.v:1917.12-1917.30" - wire width 3 \builder_shared_cti - attribute \src "ls180.v:1913.6-1913.24" - wire \builder_shared_cyc - attribute \src "ls180.v:1911.12-1911.32" - wire width 32 \builder_shared_dat_r - attribute \src "ls180.v:1910.13-1910.33" - wire width 32 \builder_shared_dat_w - attribute \src "ls180.v:1919.6-1919.24" - wire \builder_shared_err - attribute \src "ls180.v:1912.12-1912.30" - wire width 4 \builder_shared_sel - attribute \src "ls180.v:1914.6-1914.24" - wire \builder_shared_stb - attribute \src "ls180.v:1916.6-1916.23" - wire \builder_shared_we - attribute \src "ls180.v:1922.11-1922.28" - wire width 6 \builder_slave_sel - attribute \src "ls180.v:1923.11-1923.30" - wire width 6 \builder_slave_sel_r - attribute \src "ls180.v:1803.11-1803.40" - wire width 2 \builder_spimaster0_next_state - attribute \src "ls180.v:1802.11-1802.35" - wire width 2 \builder_spimaster0_state - attribute \src "ls180.v:1807.11-1807.40" - wire width 2 \builder_spimaster1_next_state - attribute \src "ls180.v:1806.11-1806.35" - wire width 2 \builder_spimaster1_state - attribute \src "ls180.v:2619.11-2619.24" - wire width 2 \builder_state - attribute \src "ls180.v:2672.5-2672.32" - wire \builder_sync_f_array_muxed0 - attribute \src "ls180.v:2673.5-2673.32" - wire \builder_sync_f_array_muxed1 - attribute \src "ls180.v:2665.11-2665.40" - wire width 2 \builder_sync_rhs_array_muxed0 - attribute \src "ls180.v:2666.12-2666.41" - wire width 13 \builder_sync_rhs_array_muxed1 - attribute \src "ls180.v:2667.5-2667.34" - wire \builder_sync_rhs_array_muxed2 - attribute \src "ls180.v:2668.5-2668.34" - wire \builder_sync_rhs_array_muxed3 - attribute \src "ls180.v:2669.5-2669.34" - wire \builder_sync_rhs_array_muxed4 - attribute \src "ls180.v:2670.5-2670.34" - wire \builder_sync_rhs_array_muxed5 - attribute \src "ls180.v:2671.5-2671.34" - wire \builder_sync_rhs_array_muxed6 - attribute \src "ls180.v:1925.6-1925.18" - wire \builder_wait - attribute \src "ls180.v:5.19-5.23" - wire width 3 input 1 \eint - attribute \src "ls180.v:127.12-127.18" - wire width 3 \eint_1 - attribute \src "ls180.v:18.21-18.27" - wire width 16 output 14 \gpio_i - attribute \src "ls180.v:19.20-19.26" - wire width 16 output 15 \gpio_o - attribute \src "ls180.v:20.20-20.27" - wire width 16 output 16 \gpio_oe - attribute \src "ls180.v:10.14-10.21" - wire output 6 \i2c_scl - attribute \src "ls180.v:11.14-11.23" - wire output 7 \i2c_sda_i - attribute \src "ls180.v:12.14-12.23" - wire output 8 \i2c_sda_o - attribute \src "ls180.v:13.14-13.24" - wire output 9 \i2c_sda_oe - attribute \src "ls180.v:49.13-49.21" - wire input 45 \jtag_tck - attribute \src "ls180.v:50.13-50.21" - wire input 46 \jtag_tdi - attribute \src "ls180.v:51.14-51.22" - wire output 47 \jtag_tdo - attribute \src "ls180.v:48.13-48.21" - wire input 44 \jtag_tms - attribute \src "ls180.v:851.6-851.18" - wire \main_ack_cmd - attribute \src "ls180.v:853.6-853.20" - wire \main_ack_rdata - attribute \src "ls180.v:852.6-852.20" - wire \main_ack_wdata - attribute \src "ls180.v:849.5-849.22" - wire \main_cmd_consumed - attribute \src "ls180.v:232.5-232.28" - wire \main_converter0_counter - attribute \src "ls180.v:1755.5-1755.50" - wire \main_converter0_counter_converter0_next_value - attribute \src "ls180.v:1756.5-1756.53" - wire \main_converter0_counter_converter0_next_value_ce - attribute \src "ls180.v:234.12-234.33" - wire width 64 \main_converter0_dat_r - attribute \src "ls180.v:233.6-233.27" - wire \main_converter0_reset - attribute \src "ls180.v:231.5-231.25" - wire \main_converter0_skip - attribute \src "ls180.v:247.5-247.28" - wire \main_converter1_counter - attribute \src "ls180.v:1759.5-1759.50" - wire \main_converter1_counter_converter1_next_value - attribute \src "ls180.v:1760.5-1760.53" - wire \main_converter1_counter_converter1_next_value_ce - attribute \src "ls180.v:249.12-249.33" - wire width 64 \main_converter1_dat_r - attribute \src "ls180.v:248.6-248.27" - wire \main_converter1_reset - attribute \src "ls180.v:246.5-246.25" - wire \main_converter1_skip - attribute \src "ls180.v:846.5-846.27" - wire \main_converter_counter - attribute \src "ls180.v:1800.5-1800.48" - wire \main_converter_counter_converter_next_value - attribute \src "ls180.v:1801.5-1801.51" - wire \main_converter_counter_converter_next_value_ce - attribute \src "ls180.v:848.12-848.32" - wire width 32 \main_converter_dat_r - attribute \src "ls180.v:847.6-847.26" - wire \main_converter_reset - attribute \src "ls180.v:845.5-845.24" - wire \main_converter_skip - attribute \src "ls180.v:263.6-263.23" - wire \main_dfi_p0_act_n - attribute \src "ls180.v:254.13-254.32" - wire width 13 \main_dfi_p0_address - attribute \src "ls180.v:255.12-255.28" - wire width 2 \main_dfi_p0_bank - attribute \src "ls180.v:256.6-256.23" - wire \main_dfi_p0_cas_n - attribute \src "ls180.v:260.6-260.21" - wire \main_dfi_p0_cke - attribute \src "ls180.v:257.6-257.22" - wire \main_dfi_p0_cs_n - attribute \src "ls180.v:261.6-261.21" - wire \main_dfi_p0_odt - attribute \src "ls180.v:258.6-258.23" - wire \main_dfi_p0_ras_n - attribute \src "ls180.v:268.12-268.30" - wire width 16 \main_dfi_p0_rddata - attribute \src "ls180.v:267.6-267.27" - wire \main_dfi_p0_rddata_en - attribute \src "ls180.v:269.5-269.29" - wire \main_dfi_p0_rddata_valid - attribute \src "ls180.v:262.6-262.25" - wire \main_dfi_p0_reset_n - attribute \src "ls180.v:259.6-259.22" - wire \main_dfi_p0_we_n - attribute \src "ls180.v:264.13-264.31" - wire width 16 \main_dfi_p0_wrdata - attribute \src "ls180.v:265.6-265.27" - wire \main_dfi_p0_wrdata_en - attribute \src "ls180.v:266.12-266.35" - wire width 2 \main_dfi_p0_wrdata_mask - attribute \src "ls180.v:1086.12-1086.22" - wire width 24 \main_dummy - attribute \src "ls180.v:996.12-996.45" - wire width 16 \main_gpiotristateasic0_oe_storage - attribute \src "ls180.v:998.12-998.46" - wire width 16 \main_gpiotristateasic0_out_storage - attribute \src "ls180.v:999.13-999.42" - wire width 16 \main_gpiotristateasic0_pads_i - attribute \src "ls180.v:1000.13-1000.42" - wire width 16 \main_gpiotristateasic0_pads_o - attribute \src "ls180.v:1001.13-1001.43" - wire width 16 \main_gpiotristateasic0_pads_oe - attribute \src "ls180.v:997.12-997.41" - wire width 16 \main_gpiotristateasic0_status - attribute \src "ls180.v:1003.5-1003.33" - wire \main_gpiotristateasic1_oe_re - attribute \src "ls180.v:1002.12-1002.45" - wire width 16 \main_gpiotristateasic1_oe_storage - attribute \src "ls180.v:1007.5-1007.34" - wire \main_gpiotristateasic1_out_re - attribute \src "ls180.v:1006.12-1006.46" - wire width 16 \main_gpiotristateasic1_out_storage - attribute \src "ls180.v:1008.13-1008.42" - wire width 16 \main_gpiotristateasic1_pads_i - attribute \src "ls180.v:1009.13-1009.42" - wire width 16 \main_gpiotristateasic1_pads_o - attribute \src "ls180.v:1010.13-1010.43" - wire width 16 \main_gpiotristateasic1_pads_oe - attribute \src "ls180.v:1004.12-1004.41" - wire width 16 \main_gpiotristateasic1_status - attribute \src "ls180.v:1005.6-1005.31" - wire \main_gpiotristateasic1_we - attribute \src "ls180.v:1108.6-1108.17" - wire \main_i2c_oe - attribute \src "ls180.v:1111.5-1111.16" - wire \main_i2c_re - attribute \src "ls180.v:1107.6-1107.18" - wire \main_i2c_scl - attribute \src "ls180.v:1109.6-1109.19" - wire \main_i2c_sda0 - attribute \src "ls180.v:1112.6-1112.19" - wire \main_i2c_sda1 - attribute \src "ls180.v:1113.6-1113.21" - wire \main_i2c_status - attribute \src "ls180.v:1110.11-1110.27" - wire width 3 \main_i2c_storage - attribute \src "ls180.v:1114.6-1114.17" - wire \main_i2c_we - attribute \src "ls180.v:253.5-253.17" - wire \main_int_rst - attribute \src "ls180.v:1574.6-1574.29" - wire \main_interface0_bus_ack - attribute \src "ls180.v:1568.13-1568.36" - wire width 32 \main_interface0_bus_adr - attribute \src "ls180.v:1577.11-1577.34" - wire width 2 \main_interface0_bus_bte - attribute \src "ls180.v:1576.11-1576.34" - wire width 3 \main_interface0_bus_cti - attribute \src "ls180.v:1572.6-1572.29" - wire \main_interface0_bus_cyc - attribute \src "ls180.v:1570.13-1570.38" - wire width 64 \main_interface0_bus_dat_r - attribute \src "ls180.v:1569.13-1569.38" - wire width 64 \main_interface0_bus_dat_w - attribute \src "ls180.v:1578.6-1578.29" - wire \main_interface0_bus_err - attribute \src "ls180.v:1571.12-1571.35" - wire width 8 \main_interface0_bus_sel - attribute \src "ls180.v:1573.6-1573.29" - wire \main_interface0_bus_stb - attribute \src "ls180.v:1575.6-1575.28" - wire \main_interface0_bus_we - attribute \src "ls180.v:226.5-226.44" - wire \main_interface0_converted_interface_ack - attribute \src "ls180.v:220.13-220.52" - wire width 30 \main_interface0_converted_interface_adr - attribute \src "ls180.v:229.12-229.51" - wire width 2 \main_interface0_converted_interface_bte - attribute \src "ls180.v:228.12-228.51" - wire width 3 \main_interface0_converted_interface_cti - attribute \src "ls180.v:224.6-224.45" - wire \main_interface0_converted_interface_cyc - attribute \src "ls180.v:222.13-222.54" - wire width 64 \main_interface0_converted_interface_dat_r - attribute \src "ls180.v:221.13-221.54" - wire width 64 \main_interface0_converted_interface_dat_w - attribute \src "ls180.v:230.5-230.44" - wire \main_interface0_converted_interface_err - attribute \src "ls180.v:223.12-223.51" - wire width 8 \main_interface0_converted_interface_sel - attribute \src "ls180.v:225.6-225.45" - wire \main_interface0_converted_interface_stb - attribute \src "ls180.v:227.6-227.44" - wire \main_interface0_converted_interface_we - attribute \src "ls180.v:1665.6-1665.29" - wire \main_interface1_bus_ack - attribute \src "ls180.v:1659.12-1659.35" - wire width 32 \main_interface1_bus_adr - attribute \src "ls180.v:1668.11-1668.34" - wire width 2 \main_interface1_bus_bte - attribute \src "ls180.v:1667.11-1667.34" - wire width 3 \main_interface1_bus_cti - attribute \src "ls180.v:1663.5-1663.28" - wire \main_interface1_bus_cyc - attribute \src "ls180.v:1661.13-1661.38" - wire width 64 \main_interface1_bus_dat_r - attribute \src "ls180.v:1660.12-1660.37" - wire width 64 \main_interface1_bus_dat_w - attribute \src "ls180.v:1669.6-1669.29" - wire \main_interface1_bus_err - attribute \src "ls180.v:1662.11-1662.34" - wire width 8 \main_interface1_bus_sel - attribute \src "ls180.v:1664.5-1664.28" - wire \main_interface1_bus_stb - attribute \src "ls180.v:1666.5-1666.27" - wire \main_interface1_bus_we - attribute \src "ls180.v:241.5-241.44" - wire \main_interface1_converted_interface_ack - attribute \src "ls180.v:235.13-235.52" - wire width 30 \main_interface1_converted_interface_adr - attribute \src "ls180.v:244.12-244.51" - wire width 2 \main_interface1_converted_interface_bte - attribute \src "ls180.v:243.12-243.51" - wire width 3 \main_interface1_converted_interface_cti - attribute \src "ls180.v:239.6-239.45" - wire \main_interface1_converted_interface_cyc - attribute \src "ls180.v:237.13-237.54" - wire width 64 \main_interface1_converted_interface_dat_r - attribute \src "ls180.v:236.13-236.54" - wire width 64 \main_interface1_converted_interface_dat_w - attribute \src "ls180.v:245.5-245.44" - wire \main_interface1_converted_interface_err - attribute \src "ls180.v:238.12-238.51" - wire width 8 \main_interface1_converted_interface_sel - attribute \src "ls180.v:240.6-240.45" - wire \main_interface1_converted_interface_stb - attribute \src "ls180.v:242.6-242.44" - wire \main_interface1_converted_interface_we - attribute \src "ls180.v:174.12-174.32" - wire width 6 \main_libresocsim_adr - attribute \src "ls180.v:62.6-62.32" - wire \main_libresocsim_bus_error - attribute \src "ls180.v:63.12-63.39" - wire width 32 \main_libresocsim_bus_errors - attribute \src "ls180.v:59.13-59.47" - wire width 32 \main_libresocsim_bus_errors_status - attribute \src "ls180.v:60.6-60.36" - wire \main_libresocsim_bus_errors_we - attribute \src "ls180.v:175.13-175.35" - wire width 64 \main_libresocsim_dat_r - attribute \src "ls180.v:177.13-177.35" - wire width 64 \main_libresocsim_dat_w - attribute \src "ls180.v:183.5-183.27" - wire \main_libresocsim_en_re - attribute \src "ls180.v:182.5-182.32" - wire \main_libresocsim_en_storage - attribute \src "ls180.v:199.6-199.45" - wire \main_libresocsim_eventmanager_pending_r - attribute \src "ls180.v:198.6-198.46" - wire \main_libresocsim_eventmanager_pending_re - attribute \src "ls180.v:201.6-201.45" - wire \main_libresocsim_eventmanager_pending_w - attribute \src "ls180.v:200.6-200.46" - wire \main_libresocsim_eventmanager_pending_we - attribute \src "ls180.v:203.5-203.37" - wire \main_libresocsim_eventmanager_re - attribute \src "ls180.v:195.6-195.44" - wire \main_libresocsim_eventmanager_status_r - attribute \src "ls180.v:194.6-194.45" - wire \main_libresocsim_eventmanager_status_re - attribute \src "ls180.v:197.6-197.44" - wire \main_libresocsim_eventmanager_status_w - attribute \src "ls180.v:196.6-196.45" - wire \main_libresocsim_eventmanager_status_we - attribute \src "ls180.v:202.5-202.42" - wire \main_libresocsim_eventmanager_storage - attribute \src "ls180.v:188.6-188.26" - wire \main_libresocsim_irq - attribute \src "ls180.v:121.6-121.32" - wire \main_libresocsim_libresoc0 - attribute \src "ls180.v:122.6-122.32" - wire \main_libresocsim_libresoc1 - attribute \src "ls180.v:123.13-123.39" - wire width 64 \main_libresocsim_libresoc2 - attribute \src "ls180.v:125.12-125.45" - wire width 2 \main_libresocsim_libresoc_clk_sel - attribute \src "ls180.v:140.12-140.66" - wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_i - attribute \src "ls180.v:141.13-141.67" - wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_o - attribute \src "ls180.v:142.13-142.68" - wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe - attribute \src "ls180.v:132.6-132.61" - wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl - attribute \src "ls180.v:133.5-133.62" - wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i - attribute \src "ls180.v:134.6-134.63" - wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o - attribute \src "ls180.v:135.6-135.64" - wire \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe - attribute \src "ls180.v:144.6-144.64" - wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk - attribute \src "ls180.v:145.5-145.65" - wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i - attribute \src "ls180.v:146.6-146.66" - wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o - attribute \src "ls180.v:147.6-147.67" - wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe - attribute \src "ls180.v:148.11-148.72" - wire width 4 \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i - attribute \src "ls180.v:149.12-149.73" - wire width 4 \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_o - attribute \src "ls180.v:150.6-150.68" - wire \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_oe - attribute \src "ls180.v:151.13-151.68" - wire width 13 \main_libresocsim_libresoc_constraintmanager_obj_sdram_a - attribute \src "ls180.v:160.12-160.68" - wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba - attribute \src "ls180.v:157.6-157.65" - wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n - attribute \src "ls180.v:159.6-159.63" - wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke - attribute \src "ls180.v:158.6-158.64" - wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n - attribute \src "ls180.v:161.12-161.68" - wire width 2 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm - attribute \src "ls180.v:152.12-152.70" - wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i - attribute \src "ls180.v:153.13-153.71" - wire width 16 \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o - attribute \src "ls180.v:154.6-154.65" - wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - attribute \src "ls180.v:156.6-156.65" - wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n - attribute \src "ls180.v:155.6-155.64" - wire \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n - attribute \src "ls180.v:128.6-128.67" - wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk - attribute \src "ls180.v:130.6-130.68" - wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n - attribute \src "ls180.v:131.6-131.68" - wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso - attribute \src "ls180.v:129.6-129.68" - wire \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi - attribute \src "ls180.v:136.6-136.67" - wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk - attribute \src "ls180.v:138.6-138.68" - wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n - attribute \src "ls180.v:139.6-139.68" - wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso - attribute \src "ls180.v:137.6-137.68" - wire \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi - attribute \src "ls180.v:72.6-72.40" - wire \main_libresocsim_libresoc_dbus_ack - attribute \src "ls180.v:66.13-66.47" - wire width 29 \main_libresocsim_libresoc_dbus_adr - attribute \src "ls180.v:75.11-75.45" - wire width 2 \main_libresocsim_libresoc_dbus_bte - attribute \src "ls180.v:74.11-74.45" - wire width 3 \main_libresocsim_libresoc_dbus_cti - attribute \src "ls180.v:70.6-70.40" - wire \main_libresocsim_libresoc_dbus_cyc - attribute \src "ls180.v:68.13-68.49" - wire width 64 \main_libresocsim_libresoc_dbus_dat_r - attribute \src "ls180.v:67.13-67.49" - wire width 64 \main_libresocsim_libresoc_dbus_dat_w - attribute \src "ls180.v:76.6-76.40" - wire \main_libresocsim_libresoc_dbus_err - attribute \src "ls180.v:69.12-69.46" - wire width 8 \main_libresocsim_libresoc_dbus_sel - attribute \src "ls180.v:71.6-71.40" - wire \main_libresocsim_libresoc_dbus_stb - attribute \src "ls180.v:73.6-73.39" - wire \main_libresocsim_libresoc_dbus_we - attribute \src "ls180.v:83.6-83.40" - wire \main_libresocsim_libresoc_ibus_ack - attribute \src "ls180.v:77.13-77.47" - wire width 29 \main_libresocsim_libresoc_ibus_adr - attribute \src "ls180.v:86.11-86.45" - wire width 2 \main_libresocsim_libresoc_ibus_bte - attribute \src "ls180.v:85.11-85.45" - wire width 3 \main_libresocsim_libresoc_ibus_cti - attribute \src "ls180.v:81.6-81.40" - wire \main_libresocsim_libresoc_ibus_cyc - attribute \src "ls180.v:79.13-79.49" - wire width 64 \main_libresocsim_libresoc_ibus_dat_r - attribute \src "ls180.v:78.13-78.49" - wire width 64 \main_libresocsim_libresoc_ibus_dat_w - attribute \src "ls180.v:87.6-87.40" - wire \main_libresocsim_libresoc_ibus_err - attribute \src "ls180.v:80.12-80.46" - wire width 8 \main_libresocsim_libresoc_ibus_sel - attribute \src "ls180.v:82.6-82.40" - wire \main_libresocsim_libresoc_ibus_stb - attribute \src "ls180.v:84.6-84.39" - wire \main_libresocsim_libresoc_ibus_we - attribute \src "ls180.v:65.12-65.47" - wire width 16 \main_libresocsim_libresoc_interrupt - attribute \src "ls180.v:117.6-117.40" - wire \main_libresocsim_libresoc_jtag_tck - attribute \src "ls180.v:119.6-119.40" - wire \main_libresocsim_libresoc_jtag_tdi - attribute \src "ls180.v:120.6-120.40" - wire \main_libresocsim_libresoc_jtag_tdo - attribute \src "ls180.v:118.6-118.40" - wire \main_libresocsim_libresoc_jtag_tms - attribute \src "ls180.v:112.6-112.43" - wire \main_libresocsim_libresoc_jtag_wb_ack - attribute \src "ls180.v:106.13-106.50" - wire width 29 \main_libresocsim_libresoc_jtag_wb_adr - attribute \src "ls180.v:115.11-115.48" - wire width 2 \main_libresocsim_libresoc_jtag_wb_bte - attribute \src "ls180.v:114.11-114.48" - wire width 3 \main_libresocsim_libresoc_jtag_wb_cti - attribute \src "ls180.v:110.6-110.43" - wire \main_libresocsim_libresoc_jtag_wb_cyc - attribute \src "ls180.v:108.13-108.52" - wire width 64 \main_libresocsim_libresoc_jtag_wb_dat_r - attribute \src "ls180.v:107.13-107.52" - wire width 64 \main_libresocsim_libresoc_jtag_wb_dat_w - attribute \src "ls180.v:116.6-116.43" - wire \main_libresocsim_libresoc_jtag_wb_err - attribute \src "ls180.v:109.12-109.49" - wire width 8 \main_libresocsim_libresoc_jtag_wb_sel - attribute \src "ls180.v:111.6-111.43" - wire \main_libresocsim_libresoc_jtag_wb_stb - attribute \src "ls180.v:113.6-113.42" - wire \main_libresocsim_libresoc_jtag_wb_we - attribute \src "ls180.v:124.6-124.40" - wire \main_libresocsim_libresoc_pll_18_o - attribute \src "ls180.v:126.6-126.41" - wire \main_libresocsim_libresoc_pll_lck_o - attribute \src "ls180.v:64.6-64.37" - wire \main_libresocsim_libresoc_reset - attribute \src "ls180.v:94.6-94.44" - wire \main_libresocsim_libresoc_xics_icp_ack - attribute \src "ls180.v:88.12-88.50" - wire width 30 \main_libresocsim_libresoc_xics_icp_adr - attribute \src "ls180.v:92.5-92.43" - wire \main_libresocsim_libresoc_xics_icp_cyc - attribute \src "ls180.v:90.13-90.53" - wire width 32 \main_libresocsim_libresoc_xics_icp_dat_r - attribute \src "ls180.v:89.12-89.52" - wire width 32 \main_libresocsim_libresoc_xics_icp_dat_w - attribute \src "ls180.v:96.6-96.44" - wire \main_libresocsim_libresoc_xics_icp_err - attribute \src "ls180.v:91.11-91.49" - wire width 4 \main_libresocsim_libresoc_xics_icp_sel - attribute \src "ls180.v:93.5-93.43" - wire \main_libresocsim_libresoc_xics_icp_stb - attribute \src "ls180.v:95.5-95.42" - wire \main_libresocsim_libresoc_xics_icp_we - attribute \src "ls180.v:103.6-103.44" - wire \main_libresocsim_libresoc_xics_ics_ack - attribute \src "ls180.v:97.12-97.50" - wire width 30 \main_libresocsim_libresoc_xics_ics_adr - attribute \src "ls180.v:101.5-101.43" - wire \main_libresocsim_libresoc_xics_ics_cyc - attribute \src "ls180.v:99.13-99.53" - wire width 32 \main_libresocsim_libresoc_xics_ics_dat_r - attribute \src "ls180.v:98.12-98.52" - wire width 32 \main_libresocsim_libresoc_xics_ics_dat_w - attribute \src "ls180.v:105.6-105.44" - wire \main_libresocsim_libresoc_xics_ics_err - attribute \src "ls180.v:100.11-100.49" - wire width 4 \main_libresocsim_libresoc_xics_ics_sel - attribute \src "ls180.v:102.5-102.43" - wire \main_libresocsim_libresoc_xics_ics_stb - attribute \src "ls180.v:104.5-104.42" - wire \main_libresocsim_libresoc_xics_ics_we - attribute \src "ls180.v:179.5-179.29" - wire \main_libresocsim_load_re - attribute \src "ls180.v:178.12-178.41" - wire width 32 \main_libresocsim_load_storage - attribute \src "ls180.v:169.5-169.33" - wire \main_libresocsim_ram_bus_ack - attribute \src "ls180.v:163.13-163.41" - wire width 30 \main_libresocsim_ram_bus_adr - attribute \src "ls180.v:172.12-172.40" - wire width 2 \main_libresocsim_ram_bus_bte - attribute \src "ls180.v:171.12-171.40" - wire width 3 \main_libresocsim_ram_bus_cti - attribute \src "ls180.v:167.6-167.34" - wire \main_libresocsim_ram_bus_cyc - attribute \src "ls180.v:165.13-165.43" - wire width 64 \main_libresocsim_ram_bus_dat_r - attribute \src "ls180.v:164.13-164.43" - wire width 64 \main_libresocsim_ram_bus_dat_w - attribute \src "ls180.v:173.5-173.33" - wire \main_libresocsim_ram_bus_err - attribute \src "ls180.v:166.12-166.40" - wire width 8 \main_libresocsim_ram_bus_sel - attribute \src "ls180.v:168.6-168.34" - wire \main_libresocsim_ram_bus_stb - attribute \src "ls180.v:170.6-170.33" - wire \main_libresocsim_ram_bus_we - attribute \src "ls180.v:181.5-181.31" - wire \main_libresocsim_reload_re - attribute \src "ls180.v:180.12-180.43" - wire width 32 \main_libresocsim_reload_storage - attribute \src "ls180.v:61.6-61.28" - wire \main_libresocsim_reset - attribute \src "ls180.v:56.5-56.30" - wire \main_libresocsim_reset_re - attribute \src "ls180.v:55.5-55.35" - wire \main_libresocsim_reset_storage - attribute \src "ls180.v:58.5-58.32" - wire \main_libresocsim_scratch_re - attribute \src "ls180.v:57.12-57.44" - wire width 32 \main_libresocsim_scratch_storage - attribute \src "ls180.v:185.5-185.37" - wire \main_libresocsim_update_value_re - attribute \src "ls180.v:184.5-184.42" - wire \main_libresocsim_update_value_storage - attribute \src "ls180.v:204.12-204.34" - wire width 32 \main_libresocsim_value - attribute \src "ls180.v:186.12-186.41" - wire width 32 \main_libresocsim_value_status - attribute \src "ls180.v:187.6-187.31" - wire \main_libresocsim_value_we - attribute \src "ls180.v:176.11-176.30" - wire width 8 \main_libresocsim_we - attribute \src "ls180.v:192.5-192.32" - wire \main_libresocsim_zero_clear - attribute \src "ls180.v:193.5-193.38" - wire \main_libresocsim_zero_old_trigger - attribute \src "ls180.v:190.5-190.34" - wire \main_libresocsim_zero_pending - attribute \src "ls180.v:189.6-189.34" - wire \main_libresocsim_zero_status - attribute \src "ls180.v:191.6-191.35" - wire \main_libresocsim_zero_trigger - attribute \src "ls180.v:843.6-843.26" - wire \main_litedram_wb_ack - attribute \src "ls180.v:837.12-837.32" - wire width 30 \main_litedram_wb_adr - attribute \src "ls180.v:841.5-841.25" - wire \main_litedram_wb_cyc - attribute \src "ls180.v:839.13-839.35" - wire width 16 \main_litedram_wb_dat_r - attribute \src "ls180.v:838.12-838.34" - wire width 16 \main_litedram_wb_dat_w - attribute \src "ls180.v:840.11-840.31" - wire width 2 \main_litedram_wb_sel - attribute \src "ls180.v:842.5-842.25" - wire \main_litedram_wb_stb - attribute \src "ls180.v:844.5-844.24" - wire \main_litedram_wb_we - attribute \src "ls180.v:1085.13-1085.20" - wire width 24 \main_nc - attribute \src "ls180.v:804.6-804.24" - wire \main_port_cmd_last - attribute \src "ls180.v:806.13-806.39" - wire width 24 \main_port_cmd_payload_addr - attribute \src "ls180.v:805.6-805.30" - wire \main_port_cmd_payload_we - attribute \src "ls180.v:803.6-803.25" - wire \main_port_cmd_ready - attribute \src "ls180.v:802.6-802.25" - wire \main_port_cmd_valid - attribute \src "ls180.v:801.6-801.21" - wire \main_port_flush - attribute \src "ls180.v:813.13-813.41" - wire width 16 \main_port_rdata_payload_data - attribute \src "ls180.v:812.6-812.27" - wire \main_port_rdata_ready - attribute \src "ls180.v:811.6-811.27" - wire \main_port_rdata_valid - attribute \src "ls180.v:809.13-809.41" - wire width 16 \main_port_wdata_payload_data - attribute \src "ls180.v:810.12-810.38" - wire width 2 \main_port_wdata_payload_we - attribute \src "ls180.v:808.6-808.27" - wire \main_port_wdata_ready - attribute \src "ls180.v:807.6-807.27" - wire \main_port_wdata_valid - attribute \src "ls180.v:1090.12-1090.29" - wire width 32 \main_pwm0_counter - attribute \src "ls180.v:1087.6-1087.22" - wire \main_pwm0_enable - attribute \src "ls180.v:1092.5-1092.24" - wire \main_pwm0_enable_re - attribute \src "ls180.v:1091.5-1091.29" - wire \main_pwm0_enable_storage - attribute \src "ls180.v:1089.13-1089.29" - wire width 32 \main_pwm0_period - attribute \src "ls180.v:1096.5-1096.24" - wire \main_pwm0_period_re - attribute \src "ls180.v:1095.12-1095.36" - wire width 32 \main_pwm0_period_storage - attribute \src "ls180.v:1088.13-1088.28" - wire width 32 \main_pwm0_width - attribute \src "ls180.v:1094.5-1094.23" - wire \main_pwm0_width_re - attribute \src "ls180.v:1093.12-1093.35" - wire width 32 \main_pwm0_width_storage - attribute \src "ls180.v:1100.12-1100.29" - wire width 32 \main_pwm1_counter - attribute \src "ls180.v:1097.6-1097.22" - wire \main_pwm1_enable - attribute \src "ls180.v:1102.5-1102.24" - wire \main_pwm1_enable_re - attribute \src "ls180.v:1101.5-1101.29" - wire \main_pwm1_enable_storage - attribute \src "ls180.v:1099.13-1099.29" - wire width 32 \main_pwm1_period - attribute \src "ls180.v:1106.5-1106.24" - wire \main_pwm1_period_re - attribute \src "ls180.v:1105.12-1105.36" - wire width 32 \main_pwm1_period_storage - attribute \src "ls180.v:1098.13-1098.28" - wire width 32 \main_pwm1_width - attribute \src "ls180.v:1104.5-1104.23" - wire \main_pwm1_width_re - attribute \src "ls180.v:1103.12-1103.35" - wire width 32 \main_pwm1_width_storage - attribute \src "ls180.v:216.12-216.24" - wire width 4 \main_ram_adr - attribute \src "ls180.v:211.5-211.29" - wire \main_ram_bus_ram_bus_ack - attribute \src "ls180.v:205.13-205.37" - wire width 30 \main_ram_bus_ram_bus_adr - attribute \src "ls180.v:214.12-214.36" - wire width 2 \main_ram_bus_ram_bus_bte - attribute \src "ls180.v:213.12-213.36" - wire width 3 \main_ram_bus_ram_bus_cti - attribute \src "ls180.v:209.6-209.30" - wire \main_ram_bus_ram_bus_cyc - attribute \src "ls180.v:207.13-207.39" - wire width 64 \main_ram_bus_ram_bus_dat_r - attribute \src "ls180.v:206.13-206.39" - wire width 64 \main_ram_bus_ram_bus_dat_w - attribute \src "ls180.v:215.5-215.29" - wire \main_ram_bus_ram_bus_err - attribute \src "ls180.v:208.12-208.36" - wire width 8 \main_ram_bus_ram_bus_sel - attribute \src "ls180.v:210.6-210.30" - wire \main_ram_bus_ram_bus_stb - attribute \src "ls180.v:212.6-212.29" - wire \main_ram_bus_ram_bus_we - attribute \src "ls180.v:217.13-217.27" - wire width 64 \main_ram_dat_r - attribute \src "ls180.v:219.13-219.27" - wire width 64 \main_ram_dat_w - attribute \src "ls180.v:218.11-218.22" - wire width 8 \main_ram_we - attribute \src "ls180.v:270.11-270.25" - wire width 3 \main_rddata_en - attribute \src "ls180.v:1628.11-1628.43" - wire width 3 \main_sdblock2mem_converter_demux - attribute \src "ls180.v:1629.6-1629.42" - wire \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:1619.6-1619.43" - wire \main_sdblock2mem_converter_sink_first - attribute \src "ls180.v:1620.6-1620.42" - wire \main_sdblock2mem_converter_sink_last - attribute \src "ls180.v:1621.12-1621.56" - wire width 8 \main_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:1618.6-1618.43" - wire \main_sdblock2mem_converter_sink_ready - attribute \src "ls180.v:1617.6-1617.43" - wire \main_sdblock2mem_converter_sink_valid - attribute \src "ls180.v:1624.5-1624.44" - wire \main_sdblock2mem_converter_source_first - attribute \src "ls180.v:1625.5-1625.43" - wire \main_sdblock2mem_converter_source_last - attribute \src "ls180.v:1626.12-1626.58" - wire width 64 \main_sdblock2mem_converter_source_payload_data - attribute \src "ls180.v:1627.11-1627.70" - wire width 4 \main_sdblock2mem_converter_source_payload_valid_token_count - attribute \src "ls180.v:1623.6-1623.45" - wire \main_sdblock2mem_converter_source_ready - attribute \src "ls180.v:1622.6-1622.45" - wire \main_sdblock2mem_converter_source_valid - attribute \src "ls180.v:1630.5-1630.42" - wire \main_sdblock2mem_converter_strobe_all - attribute \src "ls180.v:1603.11-1603.40" - wire width 5 \main_sdblock2mem_fifo_consume - attribute \src "ls180.v:1608.6-1608.35" - wire \main_sdblock2mem_fifo_do_read - attribute \src "ls180.v:1612.6-1612.41" - wire \main_sdblock2mem_fifo_fifo_in_first - attribute \src "ls180.v:1613.6-1613.40" - wire \main_sdblock2mem_fifo_fifo_in_last - attribute \src "ls180.v:1611.12-1611.54" - wire width 8 \main_sdblock2mem_fifo_fifo_in_payload_data - attribute \src "ls180.v:1615.6-1615.42" - wire \main_sdblock2mem_fifo_fifo_out_first - attribute \src "ls180.v:1616.6-1616.41" - wire \main_sdblock2mem_fifo_fifo_out_last - attribute \src "ls180.v:1614.12-1614.55" - wire width 8 \main_sdblock2mem_fifo_fifo_out_payload_data - attribute \src "ls180.v:1600.11-1600.38" - wire width 6 \main_sdblock2mem_fifo_level - attribute \src "ls180.v:1602.11-1602.40" - wire width 5 \main_sdblock2mem_fifo_produce - attribute \src "ls180.v:1609.12-1609.44" - wire width 5 \main_sdblock2mem_fifo_rdport_adr - attribute \src "ls180.v:1610.12-1610.46" - wire width 10 \main_sdblock2mem_fifo_rdport_dat_r - attribute \src "ls180.v:1601.5-1601.34" - wire \main_sdblock2mem_fifo_replace - attribute \src "ls180.v:1586.6-1586.38" - wire \main_sdblock2mem_fifo_sink_first - attribute \src "ls180.v:1587.6-1587.37" - wire \main_sdblock2mem_fifo_sink_last - attribute \src "ls180.v:1588.12-1588.51" - wire width 8 \main_sdblock2mem_fifo_sink_payload_data - attribute \src "ls180.v:1585.6-1585.38" - wire \main_sdblock2mem_fifo_sink_ready - attribute \src "ls180.v:1584.6-1584.38" - wire \main_sdblock2mem_fifo_sink_valid - attribute \src "ls180.v:1591.6-1591.40" - wire \main_sdblock2mem_fifo_source_first - attribute \src "ls180.v:1592.6-1592.39" - wire \main_sdblock2mem_fifo_source_last - attribute \src "ls180.v:1593.12-1593.53" - wire width 8 \main_sdblock2mem_fifo_source_payload_data - attribute \src "ls180.v:1590.6-1590.40" - wire \main_sdblock2mem_fifo_source_ready - attribute \src "ls180.v:1589.6-1589.40" - wire \main_sdblock2mem_fifo_source_valid - attribute \src "ls180.v:1598.12-1598.46" - wire width 10 \main_sdblock2mem_fifo_syncfifo_din - attribute \src "ls180.v:1599.12-1599.47" - wire width 10 \main_sdblock2mem_fifo_syncfifo_dout - attribute \src "ls180.v:1596.6-1596.39" - wire \main_sdblock2mem_fifo_syncfifo_re - attribute \src "ls180.v:1597.6-1597.45" - wire \main_sdblock2mem_fifo_syncfifo_readable - attribute \src "ls180.v:1594.6-1594.39" - wire \main_sdblock2mem_fifo_syncfifo_we - attribute \src "ls180.v:1595.6-1595.45" - wire \main_sdblock2mem_fifo_syncfifo_writable - attribute \src "ls180.v:1604.11-1604.43" - wire width 5 \main_sdblock2mem_fifo_wrport_adr - attribute \src "ls180.v:1605.12-1605.46" - wire width 10 \main_sdblock2mem_fifo_wrport_dat_r - attribute \src "ls180.v:1607.12-1607.46" - wire width 10 \main_sdblock2mem_fifo_wrport_dat_w - attribute \src "ls180.v:1606.6-1606.37" - wire \main_sdblock2mem_fifo_wrport_we - attribute \src "ls180.v:1581.6-1581.38" - wire \main_sdblock2mem_sink_sink_first - attribute \src "ls180.v:1582.6-1582.37" - wire \main_sdblock2mem_sink_sink_last - attribute \src "ls180.v:1638.12-1638.54" - wire width 32 \main_sdblock2mem_sink_sink_payload_address - attribute \src "ls180.v:1583.12-1583.52" - wire width 8 \main_sdblock2mem_sink_sink_payload_data0 - attribute \src "ls180.v:1639.12-1639.52" - wire width 64 \main_sdblock2mem_sink_sink_payload_data1 - attribute \src "ls180.v:1580.6-1580.39" - wire \main_sdblock2mem_sink_sink_ready0 - attribute \src "ls180.v:1637.6-1637.39" - wire \main_sdblock2mem_sink_sink_ready1 - attribute \src "ls180.v:1579.6-1579.39" - wire \main_sdblock2mem_sink_sink_valid0 - attribute \src "ls180.v:1636.5-1636.38" - wire \main_sdblock2mem_sink_sink_valid1 - attribute \src "ls180.v:1633.6-1633.42" - wire \main_sdblock2mem_source_source_first - attribute \src "ls180.v:1634.6-1634.41" - wire \main_sdblock2mem_source_source_last - attribute \src "ls180.v:1635.13-1635.56" - wire width 64 \main_sdblock2mem_source_source_payload_data - attribute \src "ls180.v:1632.6-1632.42" - wire \main_sdblock2mem_source_source_ready - attribute \src "ls180.v:1631.6-1631.42" - wire \main_sdblock2mem_source_source_valid - attribute \src "ls180.v:1655.13-1655.52" - wire width 32 \main_sdblock2mem_wishbonedmawriter_base - attribute \src "ls180.v:1646.5-1646.47" - wire \main_sdblock2mem_wishbonedmawriter_base_re - attribute \src "ls180.v:1645.12-1645.59" - wire width 64 \main_sdblock2mem_wishbonedmawriter_base_storage - attribute \src "ls180.v:1650.5-1650.49" - wire \main_sdblock2mem_wishbonedmawriter_enable_re - attribute \src "ls180.v:1649.5-1649.54" - wire \main_sdblock2mem_wishbonedmawriter_enable_storage - attribute \src "ls180.v:1657.13-1657.54" - wire width 32 \main_sdblock2mem_wishbonedmawriter_length - attribute \src "ls180.v:1648.5-1648.49" - wire \main_sdblock2mem_wishbonedmawriter_length_re - attribute \src "ls180.v:1647.12-1647.61" - wire width 32 \main_sdblock2mem_wishbonedmawriter_length_storage - attribute \src "ls180.v:1654.5-1654.47" - wire \main_sdblock2mem_wishbonedmawriter_loop_re - attribute \src "ls180.v:1653.5-1653.52" - wire \main_sdblock2mem_wishbonedmawriter_loop_storage - attribute \src "ls180.v:1656.12-1656.53" - wire width 32 \main_sdblock2mem_wishbonedmawriter_offset - attribute \src "ls180.v:1876.12-1876.79" - wire width 32 \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value - attribute \src "ls180.v:1877.5-1877.75" - wire \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce - attribute \src "ls180.v:1658.6-1658.46" - wire \main_sdblock2mem_wishbonedmawriter_reset - attribute \src "ls180.v:1642.6-1642.51" - wire \main_sdblock2mem_wishbonedmawriter_sink_first - attribute \src "ls180.v:1643.6-1643.50" - wire \main_sdblock2mem_wishbonedmawriter_sink_last - attribute \src "ls180.v:1644.13-1644.65" - wire width 64 \main_sdblock2mem_wishbonedmawriter_sink_payload_data - attribute \src "ls180.v:1641.5-1641.50" - wire \main_sdblock2mem_wishbonedmawriter_sink_ready - attribute \src "ls180.v:1640.6-1640.51" - wire \main_sdblock2mem_wishbonedmawriter_sink_valid - attribute \src "ls180.v:1651.5-1651.46" - wire \main_sdblock2mem_wishbonedmawriter_status - attribute \src "ls180.v:1652.6-1652.43" - wire \main_sdblock2mem_wishbonedmawriter_we - attribute \src "ls180.v:1420.5-1420.31" - wire \main_sdcore_block_count_re - attribute \src "ls180.v:1419.12-1419.43" - wire width 32 \main_sdcore_block_count_storage - attribute \src "ls180.v:1418.5-1418.32" - wire \main_sdcore_block_length_re - attribute \src "ls180.v:1417.11-1417.43" - wire width 10 \main_sdcore_block_length_storage - attribute \src "ls180.v:1404.5-1404.32" - wire \main_sdcore_cmd_argument_re - attribute \src "ls180.v:1403.12-1403.44" - wire width 32 \main_sdcore_cmd_argument_storage - attribute \src "ls180.v:1406.5-1406.31" - wire \main_sdcore_cmd_command_re - attribute \src "ls180.v:1405.12-1405.43" - wire width 32 \main_sdcore_cmd_command_storage - attribute \src "ls180.v:1559.11-1559.32" - wire width 3 \main_sdcore_cmd_count - attribute \src "ls180.v:1860.11-1860.55" - wire width 3 \main_sdcore_cmd_count_sdcore_fsm_next_value2 - attribute \src "ls180.v:1861.5-1861.52" - wire \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 - attribute \src "ls180.v:1560.5-1560.25" - wire \main_sdcore_cmd_done - attribute \src "ls180.v:1856.5-1856.48" - wire \main_sdcore_cmd_done_sdcore_fsm_next_value0 - attribute \src "ls180.v:1857.5-1857.51" - wire \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 - attribute \src "ls180.v:1561.5-1561.26" - wire \main_sdcore_cmd_error - attribute \src "ls180.v:1864.5-1864.49" - wire \main_sdcore_cmd_error_sdcore_fsm_next_value4 - attribute \src "ls180.v:1865.5-1865.52" - wire \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 - attribute \src "ls180.v:1413.12-1413.40" - wire width 4 \main_sdcore_cmd_event_status - attribute \src "ls180.v:1414.6-1414.30" - wire \main_sdcore_cmd_event_we - attribute \src "ls180.v:1411.13-1411.44" - wire width 128 \main_sdcore_cmd_response_status - attribute \src "ls180.v:1872.13-1872.67" - wire width 128 \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 - attribute \src "ls180.v:1873.5-1873.62" - wire \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 - attribute \src "ls180.v:1412.6-1412.33" - wire \main_sdcore_cmd_response_we - attribute \src "ls180.v:1408.6-1408.28" - wire \main_sdcore_cmd_send_r - attribute \src "ls180.v:1407.6-1407.29" - wire \main_sdcore_cmd_send_re - attribute \src "ls180.v:1410.5-1410.27" - wire \main_sdcore_cmd_send_w - attribute \src "ls180.v:1409.6-1409.29" - wire \main_sdcore_cmd_send_we - attribute \src "ls180.v:1562.5-1562.28" - wire \main_sdcore_cmd_timeout - attribute \src "ls180.v:1866.5-1866.51" - wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 - attribute \src "ls180.v:1867.5-1867.54" - wire \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 - attribute \src "ls180.v:1558.12-1558.32" - wire width 2 \main_sdcore_cmd_type - attribute \src "ls180.v:1520.11-1520.40" - wire width 4 \main_sdcore_crc16_checker_cnt - attribute \src "ls180.v:1526.5-1526.39" - wire \main_sdcore_crc16_checker_crc0_clr - attribute \src "ls180.v:1525.12-1525.46" - wire width 16 \main_sdcore_crc16_checker_crc0_crc - attribute \src "ls180.v:1521.12-1521.50" - wire width 16 \main_sdcore_crc16_checker_crc0_crcreg0 - attribute \src "ls180.v:1522.13-1522.51" - wire width 16 \main_sdcore_crc16_checker_crc0_crcreg1 - attribute \src "ls180.v:1523.13-1523.51" - wire width 16 \main_sdcore_crc16_checker_crc0_crcreg2 - attribute \src "ls180.v:1527.6-1527.43" - wire \main_sdcore_crc16_checker_crc0_enable - attribute \src "ls180.v:1524.12-1524.46" - wire width 2 \main_sdcore_crc16_checker_crc0_val - attribute \src "ls180.v:1533.5-1533.39" - wire \main_sdcore_crc16_checker_crc1_clr - attribute \src "ls180.v:1532.12-1532.46" - wire width 16 \main_sdcore_crc16_checker_crc1_crc - attribute \src "ls180.v:1528.12-1528.50" - wire width 16 \main_sdcore_crc16_checker_crc1_crcreg0 - attribute \src "ls180.v:1529.13-1529.51" - wire width 16 \main_sdcore_crc16_checker_crc1_crcreg1 - attribute \src "ls180.v:1530.13-1530.51" - wire width 16 \main_sdcore_crc16_checker_crc1_crcreg2 - attribute \src "ls180.v:1534.6-1534.43" - wire \main_sdcore_crc16_checker_crc1_enable - attribute \src "ls180.v:1531.12-1531.46" - wire width 2 \main_sdcore_crc16_checker_crc1_val - attribute \src "ls180.v:1540.5-1540.39" - wire \main_sdcore_crc16_checker_crc2_clr - attribute \src "ls180.v:1539.12-1539.46" - wire width 16 \main_sdcore_crc16_checker_crc2_crc - attribute \src "ls180.v:1535.12-1535.50" - wire width 16 \main_sdcore_crc16_checker_crc2_crcreg0 - attribute \src "ls180.v:1536.13-1536.51" - wire width 16 \main_sdcore_crc16_checker_crc2_crcreg1 - attribute \src "ls180.v:1537.13-1537.51" - wire width 16 \main_sdcore_crc16_checker_crc2_crcreg2 - attribute \src "ls180.v:1541.6-1541.43" - wire \main_sdcore_crc16_checker_crc2_enable - attribute \src "ls180.v:1538.12-1538.46" - wire width 2 \main_sdcore_crc16_checker_crc2_val - attribute \src "ls180.v:1547.5-1547.39" - wire \main_sdcore_crc16_checker_crc3_clr - attribute \src "ls180.v:1546.12-1546.46" - wire width 16 \main_sdcore_crc16_checker_crc3_crc - attribute \src "ls180.v:1542.12-1542.50" - wire width 16 \main_sdcore_crc16_checker_crc3_crcreg0 - attribute \src "ls180.v:1543.13-1543.51" - wire width 16 \main_sdcore_crc16_checker_crc3_crcreg1 - attribute \src "ls180.v:1544.13-1544.51" - wire width 16 \main_sdcore_crc16_checker_crc3_crcreg2 - attribute \src "ls180.v:1548.6-1548.43" - wire \main_sdcore_crc16_checker_crc3_enable - attribute \src "ls180.v:1545.12-1545.46" - wire width 2 \main_sdcore_crc16_checker_crc3_val - attribute \src "ls180.v:1549.12-1549.45" - wire width 16 \main_sdcore_crc16_checker_crctmp0 - attribute \src "ls180.v:1550.12-1550.45" - wire width 16 \main_sdcore_crc16_checker_crctmp1 - attribute \src "ls180.v:1551.12-1551.45" - wire width 16 \main_sdcore_crc16_checker_crctmp2 - attribute \src "ls180.v:1552.12-1552.45" - wire width 16 \main_sdcore_crc16_checker_crctmp3 - attribute \src "ls180.v:1554.12-1554.43" - wire width 16 \main_sdcore_crc16_checker_fifo0 - attribute \src "ls180.v:1555.12-1555.43" - wire width 16 \main_sdcore_crc16_checker_fifo1 - attribute \src "ls180.v:1556.12-1556.43" - wire width 16 \main_sdcore_crc16_checker_fifo2 - attribute \src "ls180.v:1557.12-1557.43" - wire width 16 \main_sdcore_crc16_checker_fifo3 - attribute \src "ls180.v:1511.5-1511.41" - wire \main_sdcore_crc16_checker_sink_first - attribute \src "ls180.v:1512.5-1512.40" - wire \main_sdcore_crc16_checker_sink_last - attribute \src "ls180.v:1513.11-1513.54" - wire width 8 \main_sdcore_crc16_checker_sink_payload_data - attribute \src "ls180.v:1510.5-1510.41" - wire \main_sdcore_crc16_checker_sink_ready - attribute \src "ls180.v:1509.5-1509.41" - wire \main_sdcore_crc16_checker_sink_valid - attribute \src "ls180.v:1516.5-1516.43" - wire \main_sdcore_crc16_checker_source_first - attribute \src "ls180.v:1517.6-1517.43" - wire \main_sdcore_crc16_checker_source_last - attribute \src "ls180.v:1518.12-1518.57" - wire width 8 \main_sdcore_crc16_checker_source_payload_data - attribute \src "ls180.v:1515.6-1515.44" - wire \main_sdcore_crc16_checker_source_ready - attribute \src "ls180.v:1514.5-1514.43" - wire \main_sdcore_crc16_checker_source_valid - attribute \src "ls180.v:1519.11-1519.40" - wire width 8 \main_sdcore_crc16_checker_val - attribute \src "ls180.v:1553.5-1553.36" - wire \main_sdcore_crc16_checker_valid - attribute \src "ls180.v:1476.11-1476.41" - wire width 3 \main_sdcore_crc16_inserter_cnt - attribute \src "ls180.v:1852.11-1852.80" - wire width 3 \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 - attribute \src "ls180.v:1853.5-1853.77" - wire \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 - attribute \src "ls180.v:1482.6-1482.41" - wire \main_sdcore_crc16_inserter_crc0_clr - attribute \src "ls180.v:1481.12-1481.47" - wire width 16 \main_sdcore_crc16_inserter_crc0_crc - attribute \src "ls180.v:1477.12-1477.51" - wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg0 - attribute \src "ls180.v:1478.13-1478.52" - wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg1 - attribute \src "ls180.v:1479.13-1479.52" - wire width 16 \main_sdcore_crc16_inserter_crc0_crcreg2 - attribute \src "ls180.v:1483.6-1483.44" - wire \main_sdcore_crc16_inserter_crc0_enable - attribute \src "ls180.v:1480.12-1480.47" - wire width 2 \main_sdcore_crc16_inserter_crc0_val - attribute \src "ls180.v:1489.6-1489.41" - wire \main_sdcore_crc16_inserter_crc1_clr - attribute \src "ls180.v:1488.12-1488.47" - wire width 16 \main_sdcore_crc16_inserter_crc1_crc - attribute \src "ls180.v:1484.12-1484.51" - wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg0 - attribute \src "ls180.v:1485.13-1485.52" - wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg1 - attribute \src "ls180.v:1486.13-1486.52" - wire width 16 \main_sdcore_crc16_inserter_crc1_crcreg2 - attribute \src "ls180.v:1490.6-1490.44" - wire \main_sdcore_crc16_inserter_crc1_enable - attribute \src "ls180.v:1487.12-1487.47" - wire width 2 \main_sdcore_crc16_inserter_crc1_val - attribute \src "ls180.v:1496.6-1496.41" - wire \main_sdcore_crc16_inserter_crc2_clr - attribute \src "ls180.v:1495.12-1495.47" - wire width 16 \main_sdcore_crc16_inserter_crc2_crc - attribute \src "ls180.v:1491.12-1491.51" - wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg0 - attribute \src "ls180.v:1492.13-1492.52" - wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg1 - attribute \src "ls180.v:1493.13-1493.52" - wire width 16 \main_sdcore_crc16_inserter_crc2_crcreg2 - attribute \src "ls180.v:1497.6-1497.44" - wire \main_sdcore_crc16_inserter_crc2_enable - attribute \src "ls180.v:1494.12-1494.47" - wire width 2 \main_sdcore_crc16_inserter_crc2_val - attribute \src "ls180.v:1503.6-1503.41" - wire \main_sdcore_crc16_inserter_crc3_clr - attribute \src "ls180.v:1502.12-1502.47" - wire width 16 \main_sdcore_crc16_inserter_crc3_crc - attribute \src "ls180.v:1498.12-1498.51" - wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg0 - attribute \src "ls180.v:1499.13-1499.52" - wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg1 - attribute \src "ls180.v:1500.13-1500.52" - wire width 16 \main_sdcore_crc16_inserter_crc3_crcreg2 - attribute \src "ls180.v:1504.6-1504.44" - wire \main_sdcore_crc16_inserter_crc3_enable - attribute \src "ls180.v:1501.12-1501.47" - wire width 2 \main_sdcore_crc16_inserter_crc3_val - attribute \src "ls180.v:1505.12-1505.46" - wire width 16 \main_sdcore_crc16_inserter_crctmp0 - attribute \src "ls180.v:1844.12-1844.85" - wire width 16 \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 - attribute \src "ls180.v:1845.5-1845.81" - wire \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 - attribute \src "ls180.v:1506.12-1506.46" - wire width 16 \main_sdcore_crc16_inserter_crctmp1 - attribute \src "ls180.v:1846.12-1846.85" - wire width 16 \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 - attribute \src "ls180.v:1847.5-1847.81" - wire \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 - attribute \src "ls180.v:1507.12-1507.46" - wire width 16 \main_sdcore_crc16_inserter_crctmp2 - attribute \src "ls180.v:1848.12-1848.85" - wire width 16 \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 - attribute \src "ls180.v:1849.5-1849.81" - wire \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 - attribute \src "ls180.v:1508.12-1508.46" - wire width 16 \main_sdcore_crc16_inserter_crctmp3 - attribute \src "ls180.v:1850.12-1850.85" - wire width 16 \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 - attribute \src "ls180.v:1851.5-1851.81" - wire \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 - attribute \src "ls180.v:1468.6-1468.43" - wire \main_sdcore_crc16_inserter_sink_first - attribute \src "ls180.v:1469.6-1469.42" - wire \main_sdcore_crc16_inserter_sink_last - attribute \src "ls180.v:1470.12-1470.56" - wire width 8 \main_sdcore_crc16_inserter_sink_payload_data - attribute \src "ls180.v:1467.5-1467.42" - wire \main_sdcore_crc16_inserter_sink_ready - attribute \src "ls180.v:1466.6-1466.43" - wire \main_sdcore_crc16_inserter_sink_valid - attribute \src "ls180.v:1473.5-1473.44" - wire \main_sdcore_crc16_inserter_source_first - attribute \src "ls180.v:1474.5-1474.43" - wire \main_sdcore_crc16_inserter_source_last - attribute \src "ls180.v:1475.11-1475.57" - wire width 8 \main_sdcore_crc16_inserter_source_payload_data - attribute \src "ls180.v:1472.5-1472.44" - wire \main_sdcore_crc16_inserter_source_ready - attribute \src "ls180.v:1471.5-1471.44" - wire \main_sdcore_crc16_inserter_source_valid - attribute \src "ls180.v:1464.6-1464.35" - wire \main_sdcore_crc7_inserter_clr - attribute \src "ls180.v:1463.11-1463.40" - wire width 7 \main_sdcore_crc7_inserter_crc - attribute \src "ls180.v:1421.11-1421.44" - wire width 7 \main_sdcore_crc7_inserter_crcreg0 - attribute \src "ls180.v:1422.12-1422.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg1 - attribute \src "ls180.v:1431.12-1431.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg10 - attribute \src "ls180.v:1432.12-1432.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg11 - attribute \src "ls180.v:1433.12-1433.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg12 - attribute \src "ls180.v:1434.12-1434.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg13 - attribute \src "ls180.v:1435.12-1435.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg14 - attribute \src "ls180.v:1436.12-1436.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg15 - attribute \src "ls180.v:1437.12-1437.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg16 - attribute \src "ls180.v:1438.12-1438.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg17 - attribute \src "ls180.v:1439.12-1439.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg18 - attribute \src "ls180.v:1440.12-1440.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg19 - attribute \src "ls180.v:1423.12-1423.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg2 - attribute \src "ls180.v:1441.12-1441.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg20 - attribute \src "ls180.v:1442.12-1442.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg21 - attribute \src "ls180.v:1443.12-1443.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg22 - attribute \src "ls180.v:1444.12-1444.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg23 - attribute \src "ls180.v:1445.12-1445.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg24 - attribute \src "ls180.v:1446.12-1446.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg25 - attribute \src "ls180.v:1447.12-1447.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg26 - attribute \src "ls180.v:1448.12-1448.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg27 - attribute \src "ls180.v:1449.12-1449.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg28 - attribute \src "ls180.v:1450.12-1450.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg29 - attribute \src "ls180.v:1424.12-1424.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg3 - attribute \src "ls180.v:1451.12-1451.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg30 - attribute \src "ls180.v:1452.12-1452.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg31 - attribute \src "ls180.v:1453.12-1453.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg32 - attribute \src "ls180.v:1454.12-1454.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg33 - attribute \src "ls180.v:1455.12-1455.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg34 - attribute \src "ls180.v:1456.12-1456.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg35 - attribute \src "ls180.v:1457.12-1457.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg36 - attribute \src "ls180.v:1458.12-1458.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg37 - attribute \src "ls180.v:1459.12-1459.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg38 - attribute \src "ls180.v:1460.12-1460.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg39 - attribute \src "ls180.v:1425.12-1425.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg4 - attribute \src "ls180.v:1461.12-1461.46" - wire width 7 \main_sdcore_crc7_inserter_crcreg40 - attribute \src "ls180.v:1426.12-1426.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg5 - attribute \src "ls180.v:1427.12-1427.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg6 - attribute \src "ls180.v:1428.12-1428.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg7 - attribute \src "ls180.v:1429.12-1429.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg8 - attribute \src "ls180.v:1430.12-1430.45" - wire width 7 \main_sdcore_crc7_inserter_crcreg9 - attribute \src "ls180.v:1465.6-1465.38" - wire \main_sdcore_crc7_inserter_enable - attribute \src "ls180.v:1462.13-1462.42" - wire width 40 \main_sdcore_crc7_inserter_val - attribute \src "ls180.v:1564.12-1564.34" - wire width 32 \main_sdcore_data_count - attribute \src "ls180.v:1862.12-1862.57" - wire width 32 \main_sdcore_data_count_sdcore_fsm_next_value3 - attribute \src "ls180.v:1863.5-1863.53" - wire \main_sdcore_data_count_sdcore_fsm_next_value_ce3 - attribute \src "ls180.v:1565.5-1565.26" - wire \main_sdcore_data_done - attribute \src "ls180.v:1858.5-1858.49" - wire \main_sdcore_data_done_sdcore_fsm_next_value1 - attribute \src "ls180.v:1859.5-1859.52" - wire \main_sdcore_data_done_sdcore_fsm_next_value_ce1 - attribute \src "ls180.v:1566.5-1566.27" - wire \main_sdcore_data_error - attribute \src "ls180.v:1868.5-1868.50" - wire \main_sdcore_data_error_sdcore_fsm_next_value6 - attribute \src "ls180.v:1869.5-1869.53" - wire \main_sdcore_data_error_sdcore_fsm_next_value_ce6 - attribute \src "ls180.v:1415.12-1415.41" - wire width 4 \main_sdcore_data_event_status - attribute \src "ls180.v:1416.6-1416.31" - wire \main_sdcore_data_event_we - attribute \src "ls180.v:1567.5-1567.29" - wire \main_sdcore_data_timeout - attribute \src "ls180.v:1870.5-1870.52" - wire \main_sdcore_data_timeout_sdcore_fsm_next_value7 - attribute \src "ls180.v:1871.5-1871.55" - wire \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 - attribute \src "ls180.v:1563.12-1563.33" - wire width 2 \main_sdcore_data_type - attribute \src "ls180.v:1395.6-1395.33" - wire \main_sdcore_sink_sink_first - attribute \src "ls180.v:1396.6-1396.32" - wire \main_sdcore_sink_sink_last - attribute \src "ls180.v:1397.12-1397.46" - wire width 8 \main_sdcore_sink_sink_payload_data - attribute \src "ls180.v:1394.6-1394.33" - wire \main_sdcore_sink_sink_ready - attribute \src "ls180.v:1393.6-1393.33" - wire \main_sdcore_sink_sink_valid - attribute \src "ls180.v:1400.6-1400.37" - wire \main_sdcore_source_source_first - attribute \src "ls180.v:1401.6-1401.36" - wire \main_sdcore_source_source_last - attribute \src "ls180.v:1402.12-1402.50" - wire width 8 \main_sdcore_source_source_payload_data - attribute \src "ls180.v:1399.6-1399.37" - wire \main_sdcore_source_source_ready - attribute \src "ls180.v:1398.6-1398.37" - wire \main_sdcore_source_source_valid - attribute \src "ls180.v:1713.6-1713.38" - wire \main_sdmem2block_converter_first - attribute \src "ls180.v:1714.6-1714.37" - wire \main_sdmem2block_converter_last - attribute \src "ls180.v:1712.11-1712.41" - wire width 3 \main_sdmem2block_converter_mux - attribute \src "ls180.v:1703.6-1703.43" - wire \main_sdmem2block_converter_sink_first - attribute \src "ls180.v:1704.6-1704.42" - wire \main_sdmem2block_converter_sink_last - attribute \src "ls180.v:1705.13-1705.57" - wire width 64 \main_sdmem2block_converter_sink_payload_data - attribute \src "ls180.v:1702.6-1702.43" - wire \main_sdmem2block_converter_sink_ready - attribute \src "ls180.v:1701.6-1701.43" - wire \main_sdmem2block_converter_sink_valid - attribute \src "ls180.v:1708.6-1708.45" - wire \main_sdmem2block_converter_source_first - attribute \src "ls180.v:1709.6-1709.44" - wire \main_sdmem2block_converter_source_last - attribute \src "ls180.v:1710.11-1710.57" - wire width 8 \main_sdmem2block_converter_source_payload_data - attribute \src "ls180.v:1711.6-1711.65" - wire \main_sdmem2block_converter_source_payload_valid_token_count - attribute \src "ls180.v:1707.6-1707.45" - wire \main_sdmem2block_converter_source_ready - attribute \src "ls180.v:1706.6-1706.45" - wire \main_sdmem2block_converter_source_valid - attribute \src "ls180.v:1697.13-1697.38" - wire width 32 \main_sdmem2block_dma_base - attribute \src "ls180.v:1686.5-1686.33" - wire \main_sdmem2block_dma_base_re - attribute \src "ls180.v:1685.12-1685.45" - wire width 64 \main_sdmem2block_dma_base_storage - attribute \src "ls180.v:1684.12-1684.37" - wire width 64 \main_sdmem2block_dma_data - attribute \src "ls180.v:1880.12-1880.67" - wire width 64 \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value - attribute \src "ls180.v:1881.5-1881.63" - wire \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce - attribute \src "ls180.v:1691.5-1691.37" - wire \main_sdmem2block_dma_done_status - attribute \src "ls180.v:1692.6-1692.34" - wire \main_sdmem2block_dma_done_we - attribute \src "ls180.v:1690.5-1690.35" - wire \main_sdmem2block_dma_enable_re - attribute \src "ls180.v:1689.5-1689.40" - wire \main_sdmem2block_dma_enable_storage - attribute \src "ls180.v:1699.13-1699.40" - wire width 32 \main_sdmem2block_dma_length - attribute \src "ls180.v:1688.5-1688.35" - wire \main_sdmem2block_dma_length_re - attribute \src "ls180.v:1687.12-1687.47" - wire width 32 \main_sdmem2block_dma_length_storage - attribute \src "ls180.v:1694.5-1694.33" - wire \main_sdmem2block_dma_loop_re - attribute \src "ls180.v:1693.5-1693.38" - wire \main_sdmem2block_dma_loop_storage - attribute \src "ls180.v:1698.12-1698.39" - wire width 32 \main_sdmem2block_dma_offset - attribute \src "ls180.v:1884.12-1884.79" - wire width 32 \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value - attribute \src "ls180.v:1885.5-1885.75" - wire \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce - attribute \src "ls180.v:1695.13-1695.47" - wire width 32 \main_sdmem2block_dma_offset_status - attribute \src "ls180.v:1696.6-1696.36" - wire \main_sdmem2block_dma_offset_we - attribute \src "ls180.v:1700.6-1700.32" - wire \main_sdmem2block_dma_reset - attribute \src "ls180.v:1677.5-1677.35" - wire \main_sdmem2block_dma_sink_last - attribute \src "ls180.v:1678.12-1678.53" - wire width 32 \main_sdmem2block_dma_sink_payload_address - attribute \src "ls180.v:1676.5-1676.36" - wire \main_sdmem2block_dma_sink_ready - attribute \src "ls180.v:1675.5-1675.36" - wire \main_sdmem2block_dma_sink_valid - attribute \src "ls180.v:1681.5-1681.38" - wire \main_sdmem2block_dma_source_first - attribute \src "ls180.v:1682.5-1682.37" - wire \main_sdmem2block_dma_source_last - attribute \src "ls180.v:1683.12-1683.52" - wire width 64 \main_sdmem2block_dma_source_payload_data - attribute \src "ls180.v:1680.6-1680.39" - wire \main_sdmem2block_dma_source_ready - attribute \src "ls180.v:1679.5-1679.38" - wire \main_sdmem2block_dma_source_valid - attribute \src "ls180.v:1739.11-1739.40" - wire width 5 \main_sdmem2block_fifo_consume - attribute \src "ls180.v:1744.6-1744.35" - wire \main_sdmem2block_fifo_do_read - attribute \src "ls180.v:1748.6-1748.41" - wire \main_sdmem2block_fifo_fifo_in_first - attribute \src "ls180.v:1749.6-1749.40" - wire \main_sdmem2block_fifo_fifo_in_last - attribute \src "ls180.v:1747.12-1747.54" - wire width 8 \main_sdmem2block_fifo_fifo_in_payload_data - attribute \src "ls180.v:1751.6-1751.42" - wire \main_sdmem2block_fifo_fifo_out_first - attribute \src "ls180.v:1752.6-1752.41" - wire \main_sdmem2block_fifo_fifo_out_last - attribute \src "ls180.v:1750.12-1750.55" - wire width 8 \main_sdmem2block_fifo_fifo_out_payload_data - attribute \src "ls180.v:1736.11-1736.38" - wire width 6 \main_sdmem2block_fifo_level - attribute \src "ls180.v:1738.11-1738.40" - wire width 5 \main_sdmem2block_fifo_produce - attribute \src "ls180.v:1745.12-1745.44" - wire width 5 \main_sdmem2block_fifo_rdport_adr - attribute \src "ls180.v:1746.12-1746.46" - wire width 10 \main_sdmem2block_fifo_rdport_dat_r - attribute \src "ls180.v:1737.5-1737.34" - wire \main_sdmem2block_fifo_replace - attribute \src "ls180.v:1722.6-1722.38" - wire \main_sdmem2block_fifo_sink_first - attribute \src "ls180.v:1723.6-1723.37" - wire \main_sdmem2block_fifo_sink_last - attribute \src "ls180.v:1724.12-1724.51" - wire width 8 \main_sdmem2block_fifo_sink_payload_data - attribute \src "ls180.v:1721.6-1721.38" - wire \main_sdmem2block_fifo_sink_ready - attribute \src "ls180.v:1720.6-1720.38" - wire \main_sdmem2block_fifo_sink_valid - attribute \src "ls180.v:1727.6-1727.40" - wire \main_sdmem2block_fifo_source_first - attribute \src "ls180.v:1728.6-1728.39" - wire \main_sdmem2block_fifo_source_last - attribute \src "ls180.v:1729.12-1729.53" - wire width 8 \main_sdmem2block_fifo_source_payload_data - attribute \src "ls180.v:1726.6-1726.40" - wire \main_sdmem2block_fifo_source_ready - attribute \src "ls180.v:1725.6-1725.40" - wire \main_sdmem2block_fifo_source_valid - attribute \src "ls180.v:1734.12-1734.46" - wire width 10 \main_sdmem2block_fifo_syncfifo_din - attribute \src "ls180.v:1735.12-1735.47" - wire width 10 \main_sdmem2block_fifo_syncfifo_dout - attribute \src "ls180.v:1732.6-1732.39" - wire \main_sdmem2block_fifo_syncfifo_re - attribute \src "ls180.v:1733.6-1733.45" - wire \main_sdmem2block_fifo_syncfifo_readable - attribute \src "ls180.v:1730.6-1730.39" - wire \main_sdmem2block_fifo_syncfifo_we - attribute \src "ls180.v:1731.6-1731.45" - wire \main_sdmem2block_fifo_syncfifo_writable - attribute \src "ls180.v:1740.11-1740.43" - wire width 5 \main_sdmem2block_fifo_wrport_adr - attribute \src "ls180.v:1741.12-1741.46" - wire width 10 \main_sdmem2block_fifo_wrport_dat_r - attribute \src "ls180.v:1743.12-1743.46" - wire width 10 \main_sdmem2block_fifo_wrport_dat_w - attribute \src "ls180.v:1742.6-1742.37" - wire \main_sdmem2block_fifo_wrport_we - attribute \src "ls180.v:1672.6-1672.43" - wire \main_sdmem2block_source_source_first0 - attribute \src "ls180.v:1717.6-1717.43" - wire \main_sdmem2block_source_source_first1 - attribute \src "ls180.v:1673.6-1673.42" - wire \main_sdmem2block_source_source_last0 - attribute \src "ls180.v:1718.6-1718.42" - wire \main_sdmem2block_source_source_last1 - attribute \src "ls180.v:1674.12-1674.56" - wire width 8 \main_sdmem2block_source_source_payload_data0 - attribute \src "ls180.v:1719.12-1719.56" - wire width 8 \main_sdmem2block_source_source_payload_data1 - attribute \src "ls180.v:1671.6-1671.43" - wire \main_sdmem2block_source_source_ready0 - attribute \src "ls180.v:1716.6-1716.43" - wire \main_sdmem2block_source_source_ready1 - attribute \src "ls180.v:1670.6-1670.43" - wire \main_sdmem2block_source_source_valid0 - attribute \src "ls180.v:1715.6-1715.43" - wire \main_sdmem2block_source_source_valid1 - attribute \src "ls180.v:1121.6-1121.27" - wire \main_sdphy_clocker_ce - attribute \src "ls180.v:1120.5-1120.28" - wire \main_sdphy_clocker_clk0 - attribute \src "ls180.v:1123.5-1123.28" - wire \main_sdphy_clocker_clk1 - attribute \src "ls180.v:1124.5-1124.29" - wire \main_sdphy_clocker_clk_d - attribute \src "ls180.v:1122.11-1122.34" - wire width 9 \main_sdphy_clocker_clks - attribute \src "ls180.v:1118.5-1118.26" - wire \main_sdphy_clocker_re - attribute \src "ls180.v:1119.6-1119.29" - wire \main_sdphy_clocker_stop - attribute \src "ls180.v:1117.11-1117.37" - wire width 9 \main_sdphy_clocker_storage - attribute \src "ls180.v:1221.6-1221.41" - wire \main_sdphy_cmdr_cmdr_buf_sink_first - attribute \src "ls180.v:1222.6-1222.40" - wire \main_sdphy_cmdr_cmdr_buf_sink_last - attribute \src "ls180.v:1223.12-1223.54" - wire width 8 \main_sdphy_cmdr_cmdr_buf_sink_payload_data - attribute \src "ls180.v:1220.6-1220.41" - wire \main_sdphy_cmdr_cmdr_buf_sink_ready - attribute \src "ls180.v:1219.6-1219.41" - wire \main_sdphy_cmdr_cmdr_buf_sink_valid - attribute \src "ls180.v:1226.5-1226.42" - wire \main_sdphy_cmdr_cmdr_buf_source_first - attribute \src "ls180.v:1227.5-1227.41" - wire \main_sdphy_cmdr_cmdr_buf_source_last - attribute \src "ls180.v:1228.11-1228.55" - wire width 8 \main_sdphy_cmdr_cmdr_buf_source_payload_data - attribute \src "ls180.v:1225.6-1225.43" - wire \main_sdphy_cmdr_cmdr_buf_source_ready - attribute \src "ls180.v:1224.5-1224.42" - wire \main_sdphy_cmdr_cmdr_buf_source_valid - attribute \src "ls180.v:1211.11-1211.47" - wire width 3 \main_sdphy_cmdr_cmdr_converter_demux - attribute \src "ls180.v:1212.6-1212.46" - wire \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:1202.5-1202.46" - wire \main_sdphy_cmdr_cmdr_converter_sink_first - attribute \src "ls180.v:1203.5-1203.45" - wire \main_sdphy_cmdr_cmdr_converter_sink_last - attribute \src "ls180.v:1204.6-1204.54" - wire \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:1201.6-1201.47" - wire \main_sdphy_cmdr_cmdr_converter_sink_ready - attribute \src "ls180.v:1200.6-1200.47" - wire \main_sdphy_cmdr_cmdr_converter_sink_valid - attribute \src "ls180.v:1207.5-1207.48" - wire \main_sdphy_cmdr_cmdr_converter_source_first - attribute \src "ls180.v:1208.5-1208.47" - wire \main_sdphy_cmdr_cmdr_converter_source_last - attribute \src "ls180.v:1209.11-1209.61" - wire width 8 \main_sdphy_cmdr_cmdr_converter_source_payload_data - attribute \src "ls180.v:1210.11-1210.74" - wire width 4 \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count - attribute \src "ls180.v:1206.6-1206.49" - wire \main_sdphy_cmdr_cmdr_converter_source_ready - attribute \src "ls180.v:1205.6-1205.49" - wire \main_sdphy_cmdr_cmdr_converter_source_valid - attribute \src "ls180.v:1213.5-1213.46" - wire \main_sdphy_cmdr_cmdr_converter_strobe_all - attribute \src "ls180.v:1184.6-1184.40" - wire \main_sdphy_cmdr_cmdr_pads_in_first - attribute \src "ls180.v:1185.6-1185.39" - wire \main_sdphy_cmdr_cmdr_pads_in_last - attribute \src "ls180.v:1186.6-1186.46" - wire \main_sdphy_cmdr_cmdr_pads_in_payload_clk - attribute \src "ls180.v:1187.6-1187.48" - wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i - attribute \src "ls180.v:1188.6-1188.48" - wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_o - attribute \src "ls180.v:1189.6-1189.49" - wire \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_oe - attribute \src "ls180.v:1190.12-1190.55" - wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_i - attribute \src "ls180.v:1191.12-1191.55" - wire width 4 \main_sdphy_cmdr_cmdr_pads_in_payload_data_o - attribute \src "ls180.v:1192.6-1192.50" - wire \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe - attribute \src "ls180.v:1183.5-1183.39" - wire \main_sdphy_cmdr_cmdr_pads_in_ready - attribute \src "ls180.v:1182.6-1182.40" - wire \main_sdphy_cmdr_cmdr_pads_in_valid - attribute \src "ls180.v:1229.5-1229.31" - wire \main_sdphy_cmdr_cmdr_reset - attribute \src "ls180.v:1824.5-1824.59" - wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 - attribute \src "ls180.v:1825.5-1825.62" - wire \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 - attribute \src "ls180.v:1199.5-1199.29" - wire \main_sdphy_cmdr_cmdr_run + wire width 10 $memwr$\storage_5$ls180.v:5623$22_EN + attribute \src "ls180.v:1709.36-1709.61" + wire $ne$ls180.v:1709$82_Y + attribute \src "ls180.v:1884.60-1884.89" + wire $ne$ls180.v:1884$121_Y + attribute \src "ls180.v:1945.8-1945.132" + wire $ne$ls180.v:1945$140_Y + attribute \src "ls180.v:1977.70-1977.123" + wire $ne$ls180.v:1977$147_Y + attribute \src "ls180.v:1978.70-1978.123" + wire $ne$ls180.v:1978$148_Y + attribute \src "ls180.v:2102.8-2102.132" + wire $ne$ls180.v:2102$170_Y + attribute \src "ls180.v:2134.70-2134.123" + wire $ne$ls180.v:2134$177_Y + attribute \src "ls180.v:2135.70-2135.123" + wire $ne$ls180.v:2135$178_Y + attribute \src "ls180.v:2259.8-2259.132" + wire $ne$ls180.v:2259$200_Y + attribute \src "ls180.v:2291.70-2291.123" + wire $ne$ls180.v:2291$207_Y + attribute \src "ls180.v:2292.70-2292.123" + wire $ne$ls180.v:2292$208_Y + attribute \src "ls180.v:2416.8-2416.132" + wire $ne$ls180.v:2416$230_Y + attribute \src "ls180.v:2448.70-2448.123" + wire $ne$ls180.v:2448$237_Y + attribute \src "ls180.v:2449.70-2449.123" + wire $ne$ls180.v:2449$238_Y + attribute \src "ls180.v:2941.37-2941.60" + wire $ne$ls180.v:2941$636_Y + attribute \src "ls180.v:2942.37-2942.59" + wire $ne$ls180.v:2942$637_Y + attribute \src "ls180.v:2971.37-2971.60" + wire $ne$ls180.v:2971$647_Y + attribute \src "ls180.v:2972.37-2972.59" + wire $ne$ls180.v:2972$648_Y + attribute \src "ls180.v:3067.99-3067.143" + wire $ne$ls180.v:3067$655_Y + attribute \src "ls180.v:4351.7-4351.47" + wire $ne$ls180.v:4351$1280_Y + attribute \src "ls180.v:4405.9-4405.38" + wire $ne$ls180.v:4405$1297_Y + attribute \src "ls180.v:4441.8-4441.39" + wire $ne$ls180.v:4441$1304_Y + attribute \src "ls180.v:1513.28-1513.63" + wire $not$ls180.v:1513$24_Y + attribute \src "ls180.v:1552.43-1552.59" + wire $not$ls180.v:1552$29_Y + attribute \src "ls180.v:1553.43-1553.59" + wire $not$ls180.v:1553$30_Y + attribute \src "ls180.v:1573.28-1573.63" + wire $not$ls180.v:1573$35_Y + attribute \src "ls180.v:1612.43-1612.59" + wire $not$ls180.v:1612$40_Y + attribute \src "ls180.v:1613.43-1613.59" + wire $not$ls180.v:1613$41_Y + attribute \src "ls180.v:1633.31-1633.69" + wire $not$ls180.v:1633$46_Y + attribute \src "ls180.v:1672.22-1672.41" + wire $not$ls180.v:1672$51_Y + attribute \src "ls180.v:1673.22-1673.41" + wire $not$ls180.v:1673$52_Y + attribute \src "ls180.v:1833.29-1833.54" + wire $not$ls180.v:1833$113_Y + attribute \src "ls180.v:1834.26-1834.51" + wire $not$ls180.v:1834$114_Y + attribute \src "ls180.v:1835.27-1835.52" + wire $not$ls180.v:1835$115_Y + attribute \src "ls180.v:1836.27-1836.52" + wire $not$ls180.v:1836$116_Y + attribute \src "ls180.v:1878.28-1878.46" + wire $not$ls180.v:1878$119_Y + attribute \src "ls180.v:1979.53-1979.96" + wire $not$ls180.v:1979$149_Y + attribute \src "ls180.v:2033.9-2033.40" + wire $not$ls180.v:2033$154_Y + attribute \src "ls180.v:2136.53-2136.96" + wire $not$ls180.v:2136$179_Y + attribute \src "ls180.v:2190.9-2190.40" + wire $not$ls180.v:2190$184_Y + attribute \src "ls180.v:2293.53-2293.96" + wire $not$ls180.v:2293$209_Y + attribute \src "ls180.v:2347.9-2347.40" + wire $not$ls180.v:2347$214_Y + attribute \src "ls180.v:2450.53-2450.96" + wire $not$ls180.v:2450$239_Y + attribute \src "ls180.v:2504.9-2504.40" + wire $not$ls180.v:2504$244_Y + attribute \src "ls180.v:2546.129-2546.162" + wire $not$ls180.v:2546$247_Y + attribute \src "ls180.v:2546.168-2546.200" + wire $not$ls180.v:2546$249_Y + attribute \src "ls180.v:2547.129-2547.162" + wire $not$ls180.v:2547$253_Y + attribute \src "ls180.v:2547.168-2547.200" + wire $not$ls180.v:2547$255_Y + attribute \src "ls180.v:2563.38-2563.63" + wire width 2 $not$ls180.v:2563$283_Y + attribute \src "ls180.v:2566.180-2566.215" + wire $not$ls180.v:2566$286_Y + attribute \src "ls180.v:2566.221-2566.255" + wire $not$ls180.v:2566$288_Y + attribute \src "ls180.v:2566.139-2566.257" + wire $not$ls180.v:2566$290_Y + attribute \src "ls180.v:2567.180-2567.215" + wire $not$ls180.v:2567$299_Y + attribute \src "ls180.v:2567.221-2567.255" + wire $not$ls180.v:2567$301_Y + attribute \src "ls180.v:2567.139-2567.257" + wire $not$ls180.v:2567$303_Y + attribute \src "ls180.v:2568.180-2568.215" + wire $not$ls180.v:2568$312_Y + attribute \src "ls180.v:2568.221-2568.255" + wire $not$ls180.v:2568$314_Y + attribute \src "ls180.v:2568.139-2568.257" + wire $not$ls180.v:2568$316_Y + attribute \src "ls180.v:2569.180-2569.215" + wire $not$ls180.v:2569$325_Y + attribute \src "ls180.v:2569.221-2569.255" + wire $not$ls180.v:2569$327_Y + attribute \src "ls180.v:2569.139-2569.257" + wire $not$ls180.v:2569$329_Y + attribute \src "ls180.v:2596.61-2596.88" + wire $not$ls180.v:2596$340_Y + attribute \src "ls180.v:2599.180-2599.215" + wire $not$ls180.v:2599$344_Y + attribute \src "ls180.v:2599.221-2599.255" + wire $not$ls180.v:2599$346_Y + attribute \src "ls180.v:2599.139-2599.257" + wire $not$ls180.v:2599$348_Y + attribute \src "ls180.v:2600.180-2600.215" + wire $not$ls180.v:2600$357_Y + attribute \src "ls180.v:2600.221-2600.255" + wire $not$ls180.v:2600$359_Y + attribute \src "ls180.v:2600.139-2600.257" + wire $not$ls180.v:2600$361_Y + attribute \src "ls180.v:2601.180-2601.215" + wire $not$ls180.v:2601$370_Y + attribute \src "ls180.v:2601.221-2601.255" + wire $not$ls180.v:2601$372_Y + attribute \src "ls180.v:2601.139-2601.257" + wire $not$ls180.v:2601$374_Y + attribute \src "ls180.v:2602.180-2602.215" + wire $not$ls180.v:2602$383_Y + attribute \src "ls180.v:2602.221-2602.255" + wire $not$ls180.v:2602$385_Y + attribute \src "ls180.v:2602.139-2602.257" + wire $not$ls180.v:2602$387_Y + attribute \src "ls180.v:2665.61-2665.88" + wire $not$ls180.v:2665$426_Y + attribute \src "ls180.v:2686.97-2686.130" + wire $not$ls180.v:2686$429_Y + attribute \src "ls180.v:2686.136-2686.168" + wire $not$ls180.v:2686$431_Y + attribute \src "ls180.v:2686.58-2686.170" + wire $not$ls180.v:2686$433_Y + attribute \src "ls180.v:2694.11-2694.33" + wire $not$ls180.v:2694$436_Y + attribute \src "ls180.v:2724.97-2724.130" + wire $not$ls180.v:2724$438_Y + attribute \src "ls180.v:2724.136-2724.168" + wire $not$ls180.v:2724$440_Y + attribute \src "ls180.v:2724.58-2724.170" + wire $not$ls180.v:2724$442_Y + attribute \src "ls180.v:2732.11-2732.32" + wire $not$ls180.v:2732$445_Y + attribute \src "ls180.v:2742.87-2742.336" + wire $not$ls180.v:2742$457_Y + attribute \src "ls180.v:2743.40-2743.68" + wire $not$ls180.v:2743$460_Y + attribute \src "ls180.v:2743.73-2743.100" + wire $not$ls180.v:2743$461_Y + attribute \src "ls180.v:2747.87-2747.336" + wire $not$ls180.v:2747$473_Y + attribute \src "ls180.v:2748.40-2748.68" + wire $not$ls180.v:2748$476_Y + attribute \src "ls180.v:2748.73-2748.100" + wire $not$ls180.v:2748$477_Y + attribute \src "ls180.v:2752.87-2752.336" + wire $not$ls180.v:2752$489_Y + attribute \src "ls180.v:2753.40-2753.68" + wire $not$ls180.v:2753$492_Y + attribute \src "ls180.v:2753.73-2753.100" + wire $not$ls180.v:2753$493_Y + attribute \src "ls180.v:2757.87-2757.336" + wire $not$ls180.v:2757$505_Y + attribute \src "ls180.v:2758.40-2758.68" + wire $not$ls180.v:2758$508_Y + attribute \src "ls180.v:2758.73-2758.100" + wire $not$ls180.v:2758$509_Y + attribute \src "ls180.v:2762.123-2762.372" + wire $not$ls180.v:2762$522_Y + attribute \src "ls180.v:2762.497-2762.746" + wire $not$ls180.v:2762$538_Y + attribute \src "ls180.v:2762.871-2762.1120" + wire $not$ls180.v:2762$554_Y + attribute \src "ls180.v:2762.1245-2762.1494" + wire $not$ls180.v:2762$570_Y + attribute \src "ls180.v:2784.27-2784.40" + wire $not$ls180.v:2784$576_Y + attribute \src "ls180.v:2823.25-2823.40" + wire $not$ls180.v:2823$581_Y + attribute \src "ls180.v:2824.25-2824.40" + wire $not$ls180.v:2824$582_Y + attribute \src "ls180.v:2849.22-2849.38" + wire $not$ls180.v:2849$588_Y + attribute \src "ls180.v:2850.25-2850.40" + wire $not$ls180.v:2850$589_Y + attribute \src "ls180.v:2851.65-2851.78" + wire $not$ls180.v:2851$591_Y + attribute \src "ls180.v:2852.87-2852.102" + wire $not$ls180.v:2852$595_Y + attribute \src "ls180.v:2853.63-2853.83" + wire $not$ls180.v:2853$598_Y + attribute \src "ls180.v:2854.71-2854.86" + wire $not$ls180.v:2854$601_Y + attribute \src "ls180.v:2870.25-2870.44" + wire $not$ls180.v:2870$610_Y + attribute \src "ls180.v:2871.26-2871.47" + wire $not$ls180.v:2871$611_Y + attribute \src "ls180.v:2877.22-2877.41" + wire $not$ls180.v:2877$612_Y + attribute \src "ls180.v:2883.26-2883.47" + wire $not$ls180.v:2883$613_Y + attribute \src "ls180.v:2884.25-2884.44" + wire $not$ls180.v:2884$614_Y + attribute \src "ls180.v:2887.22-2887.43" + wire $not$ls180.v:2887$617_Y + attribute \src "ls180.v:2925.61-2925.78" + wire $not$ls180.v:2925$627_Y + attribute \src "ls180.v:2955.61-2955.78" + wire $not$ls180.v:2955$638_Y + attribute \src "ls180.v:3150.81-3150.104" + wire $not$ls180.v:3150$688_Y + attribute \src "ls180.v:3167.71-3167.106" + wire $not$ls180.v:3167$712_Y + attribute \src "ls180.v:3170.73-3170.108" + wire $not$ls180.v:3170$719_Y + attribute \src "ls180.v:3173.73-3173.108" + wire $not$ls180.v:3173$726_Y + attribute \src "ls180.v:3176.73-3176.108" + wire $not$ls180.v:3176$733_Y + attribute \src "ls180.v:3179.73-3179.108" + wire $not$ls180.v:3179$740_Y + attribute \src "ls180.v:3182.76-3182.111" + wire $not$ls180.v:3182$747_Y + attribute \src "ls180.v:3185.76-3185.111" + wire $not$ls180.v:3185$754_Y + attribute \src "ls180.v:3188.76-3188.111" + wire $not$ls180.v:3188$761_Y + attribute \src "ls180.v:3191.76-3191.111" + wire $not$ls180.v:3191$768_Y + attribute \src "ls180.v:3205.68-3205.103" + wire $not$ls180.v:3205$776_Y + attribute \src "ls180.v:3208.67-3208.102" + wire $not$ls180.v:3208$783_Y + attribute \src "ls180.v:3211.69-3211.104" + wire $not$ls180.v:3211$790_Y + attribute \src "ls180.v:3219.68-3219.103" + wire $not$ls180.v:3219$798_Y + attribute \src "ls180.v:3222.67-3222.102" + wire $not$ls180.v:3222$805_Y + attribute \src "ls180.v:3225.69-3225.104" + wire $not$ls180.v:3225$812_Y + attribute \src "ls180.v:3233.67-3233.102" + wire $not$ls180.v:3233$820_Y + attribute \src "ls180.v:3236.66-3236.101" + wire $not$ls180.v:3236$827_Y + attribute \src "ls180.v:3247.78-3247.113" + wire $not$ls180.v:3247$835_Y + attribute \src "ls180.v:3250.82-3250.117" + wire $not$ls180.v:3250$842_Y + attribute \src "ls180.v:3253.63-3253.98" + wire $not$ls180.v:3253$849_Y + attribute \src "ls180.v:3256.82-3256.117" + wire $not$ls180.v:3256$856_Y + attribute \src "ls180.v:3259.82-3259.117" + wire $not$ls180.v:3259$863_Y + attribute \src "ls180.v:3262.83-3262.118" + wire $not$ls180.v:3262$870_Y + attribute \src "ls180.v:3265.81-3265.116" + wire $not$ls180.v:3265$877_Y + attribute \src "ls180.v:3268.81-3268.116" + wire $not$ls180.v:3268$884_Y + attribute \src "ls180.v:3271.81-3271.116" + wire $not$ls180.v:3271$891_Y + attribute \src "ls180.v:3274.81-3274.116" + wire $not$ls180.v:3274$898_Y + attribute \src "ls180.v:3292.70-3292.105" + wire $not$ls180.v:3292$906_Y + attribute \src "ls180.v:3295.70-3295.105" + wire $not$ls180.v:3295$913_Y + attribute \src "ls180.v:3298.70-3298.105" + wire $not$ls180.v:3298$920_Y + attribute \src "ls180.v:3301.70-3301.105" + wire $not$ls180.v:3301$927_Y + attribute \src "ls180.v:3304.72-3304.107" + wire $not$ls180.v:3304$934_Y + attribute \src "ls180.v:3307.72-3307.107" + wire $not$ls180.v:3307$941_Y + attribute \src "ls180.v:3310.72-3310.107" + wire $not$ls180.v:3310$948_Y + attribute \src "ls180.v:3313.72-3313.107" + wire $not$ls180.v:3313$955_Y + attribute \src "ls180.v:3316.68-3316.103" + wire $not$ls180.v:3316$962_Y + attribute \src "ls180.v:3319.78-3319.113" + wire $not$ls180.v:3319$969_Y + attribute \src "ls180.v:3322.71-3322.106" + wire $not$ls180.v:3322$976_Y + attribute \src "ls180.v:3325.71-3325.106" + wire $not$ls180.v:3325$983_Y + attribute \src "ls180.v:3328.71-3328.106" + wire $not$ls180.v:3328$990_Y + attribute \src "ls180.v:3331.71-3331.106" + wire $not$ls180.v:3331$997_Y + attribute \src "ls180.v:3334.75-3334.110" + wire $not$ls180.v:3334$1004_Y + attribute \src "ls180.v:3337.76-3337.111" + wire $not$ls180.v:3337$1011_Y + attribute \src "ls180.v:3340.75-3340.110" + wire $not$ls180.v:3340$1018_Y + attribute \src "ls180.v:3360.48-3360.83" + wire $not$ls180.v:3360$1026_Y + attribute \src "ls180.v:3363.71-3363.106" + wire $not$ls180.v:3363$1033_Y + attribute \src "ls180.v:3366.72-3366.107" + wire $not$ls180.v:3366$1040_Y + attribute \src "ls180.v:3369.63-3369.98" + wire $not$ls180.v:3369$1047_Y + attribute \src "ls180.v:3372.64-3372.99" + wire $not$ls180.v:3372$1054_Y + attribute \src "ls180.v:3375.75-3375.110" + wire $not$ls180.v:3375$1061_Y + attribute \src "ls180.v:3378.72-3378.107" + wire $not$ls180.v:3378$1068_Y + attribute \src "ls180.v:3381.71-3381.106" + wire $not$ls180.v:3381$1075_Y + attribute \src "ls180.v:3394.77-3394.112" + wire $not$ls180.v:3394$1083_Y + attribute \src "ls180.v:3397.77-3397.112" + wire $not$ls180.v:3397$1090_Y + attribute \src "ls180.v:3400.77-3400.112" + wire $not$ls180.v:3400$1097_Y + attribute \src "ls180.v:3403.77-3403.112" + wire $not$ls180.v:3403$1104_Y + attribute \src "ls180.v:3763.68-3763.317" + wire $not$ls180.v:3763$1146_Y + attribute \src "ls180.v:3787.68-3787.317" + wire $not$ls180.v:3787$1162_Y + attribute \src "ls180.v:3811.68-3811.317" + wire $not$ls180.v:3811$1178_Y + attribute \src "ls180.v:3835.68-3835.317" + wire $not$ls180.v:3835$1194_Y + attribute \src "ls180.v:4357.62-4357.86" + wire $not$ls180.v:4357$1283_Y + attribute \src "ls180.v:4376.8-4376.33" + wire $not$ls180.v:4376$1287_Y + attribute \src "ls180.v:4380.54-4380.74" + wire $not$ls180.v:4380$1290_Y + attribute \src "ls180.v:4388.27-4388.45" + wire $not$ls180.v:4388$1292_Y + attribute \src "ls180.v:4458.126-4458.174" + wire $not$ls180.v:4458$1307_Y + attribute \src "ls180.v:4464.126-4464.174" + wire $not$ls180.v:4464$1312_Y + attribute \src "ls180.v:4465.8-4465.56" + wire $not$ls180.v:4465$1314_Y + attribute \src "ls180.v:4473.8-4473.51" + wire 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\src "ls180.v:233.12-233.23" + wire width 2 \dfi_p0_bank + attribute \src "ls180.v:234.6-234.18" + wire \dfi_p0_cas_n + attribute \src "ls180.v:238.6-238.16" + wire \dfi_p0_cke + attribute \src "ls180.v:235.6-235.17" + wire \dfi_p0_cs_n + attribute \src "ls180.v:239.6-239.16" + wire \dfi_p0_odt + attribute \src "ls180.v:236.6-236.18" + wire \dfi_p0_ras_n + attribute \src "ls180.v:246.12-246.25" + wire width 16 \dfi_p0_rddata + attribute \src "ls180.v:245.6-245.22" + wire \dfi_p0_rddata_en + attribute \src "ls180.v:247.5-247.24" + wire \dfi_p0_rddata_valid + attribute \src "ls180.v:240.6-240.20" + wire \dfi_p0_reset_n + attribute \src "ls180.v:237.6-237.17" + wire \dfi_p0_we_n + attribute \src "ls180.v:242.13-242.26" + wire width 16 \dfi_p0_wrdata + attribute \src "ls180.v:243.6-243.22" + wire \dfi_p0_wrdata_en + attribute \src "ls180.v:244.12-244.30" + wire width 2 \dfi_p0_wrdata_mask + attribute \src "ls180.v:993.12-993.17" + wire width 30 \dummy + attribute \src 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attribute \src "ls180.v:979.5-979.17" + wire \gpio0_out_re + attribute \src "ls180.v:978.11-978.28" + wire width 8 \gpio0_out_storage + attribute \src "ls180.v:980.11-980.28" + wire width 8 \gpio0_pads_gpio0i + attribute \src "ls180.v:981.11-981.28" + wire width 8 \gpio0_pads_gpio0o + attribute \src "ls180.v:982.11-982.29" + wire width 8 \gpio0_pads_gpio0oe + attribute \src "ls180.v:976.11-976.23" + wire width 8 \gpio0_status + attribute \src "ls180.v:977.6-977.14" + wire \gpio0_we + attribute \src "ls180.v:984.5-984.16" + wire \gpio1_oe_re + attribute \src "ls180.v:983.11-983.27" + wire width 8 \gpio1_oe_storage + attribute \src "ls180.v:988.5-988.17" + wire \gpio1_out_re + attribute \src "ls180.v:987.11-987.28" + wire width 8 \gpio1_out_storage + attribute \src "ls180.v:989.11-989.28" + wire width 8 \gpio1_pads_gpio1i + attribute \src "ls180.v:990.11-990.28" + wire width 8 \gpio1_pads_gpio1o + attribute \src "ls180.v:991.11-991.29" + wire width 8 \gpio1_pads_gpio1oe + attribute \src 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attribute \src "ls180.v:1001.6-1001.12" + wire \i2c_we + attribute \src "ls180.v:231.5-231.12" + wire \int_rst + attribute \src "ls180.v:204.5-204.39" + wire \interface0_converted_interface_ack + attribute \src "ls180.v:198.13-198.47" + wire width 30 \interface0_converted_interface_adr + attribute \src "ls180.v:207.12-207.46" + wire width 2 \interface0_converted_interface_bte + attribute \src "ls180.v:206.12-206.46" + wire width 3 \interface0_converted_interface_cti + attribute \src "ls180.v:202.6-202.40" + wire \interface0_converted_interface_cyc + attribute \src "ls180.v:200.13-200.49" + wire width 64 \interface0_converted_interface_dat_r + attribute \src "ls180.v:199.13-199.49" + wire width 64 \interface0_converted_interface_dat_w + attribute \src "ls180.v:208.5-208.39" + wire \interface0_converted_interface_err + attribute \src "ls180.v:201.12-201.46" + wire width 8 \interface0_converted_interface_sel + attribute \src "ls180.v:203.6-203.40" + wire \interface0_converted_interface_stb + attribute \src "ls180.v:205.6-205.39" + wire \interface0_converted_interface_we + attribute \src "ls180.v:219.5-219.39" + wire \interface1_converted_interface_ack + attribute \src "ls180.v:213.13-213.47" + wire width 30 \interface1_converted_interface_adr + attribute \src "ls180.v:222.12-222.46" + wire width 2 \interface1_converted_interface_bte + attribute \src "ls180.v:221.12-221.46" + wire width 3 \interface1_converted_interface_cti + attribute \src "ls180.v:217.6-217.40" + wire \interface1_converted_interface_cyc + attribute \src "ls180.v:215.13-215.49" + wire width 64 \interface1_converted_interface_dat_r + attribute \src "ls180.v:214.13-214.49" + wire width 64 \interface1_converted_interface_dat_w + attribute \src "ls180.v:223.5-223.39" + wire \interface1_converted_interface_err + attribute \src "ls180.v:216.12-216.46" + wire width 8 \interface1_converted_interface_sel + attribute \src "ls180.v:218.6-218.40" + wire \interface1_converted_interface_stb + attribute \src "ls180.v:220.6-220.39" + wire \interface1_converted_interface_we + attribute \src "ls180.v:864.6-864.9" + wire \irq + attribute \src "ls180.v:37.13-37.21" + wire input 33 \jtag_tck + attribute \src "ls180.v:38.13-38.21" + wire input 34 \jtag_tdi + attribute \src "ls180.v:39.14-39.22" + wire output 35 \jtag_tdo + attribute \src "ls180.v:36.13-36.21" + wire input 32 \jtag_tms + attribute \src "ls180.v:152.12-152.27" + wire width 6 \libresocsim_adr + attribute \src "ls180.v:50.6-50.27" + wire \libresocsim_bus_error + attribute \src "ls180.v:51.12-51.34" + wire width 32 \libresocsim_bus_errors + attribute \src "ls180.v:47.13-47.42" + wire width 32 \libresocsim_bus_errors_status + attribute \src "ls180.v:48.6-48.31" + wire \libresocsim_bus_errors_we + attribute \src "ls180.v:1092.12-1092.29" + wire width 20 \libresocsim_count + attribute \src "ls180.v:1333.13-1333.45" + wire width 14 \libresocsim_csr_interconnect_adr + attribute \src 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\libresocsim_csrbank0_reset0_we + attribute \src "ls180.v:1114.12-1114.43" + wire width 8 \libresocsim_csrbank0_scratch0_r + attribute \src "ls180.v:1113.6-1113.38" + wire \libresocsim_csrbank0_scratch0_re + attribute \src "ls180.v:1116.12-1116.43" + wire width 8 \libresocsim_csrbank0_scratch0_w + attribute \src "ls180.v:1115.6-1115.38" + wire \libresocsim_csrbank0_scratch0_we + attribute \src "ls180.v:1110.12-1110.43" + wire width 8 \libresocsim_csrbank0_scratch1_r + attribute \src "ls180.v:1109.6-1109.38" + wire \libresocsim_csrbank0_scratch1_re + attribute \src "ls180.v:1112.12-1112.43" + wire width 8 \libresocsim_csrbank0_scratch1_w + attribute \src "ls180.v:1111.6-1111.38" + wire \libresocsim_csrbank0_scratch1_we + attribute \src "ls180.v:1106.12-1106.43" + wire width 8 \libresocsim_csrbank0_scratch2_r + attribute \src "ls180.v:1105.6-1105.38" + wire \libresocsim_csrbank0_scratch2_re + attribute \src "ls180.v:1108.12-1108.43" + wire width 8 \libresocsim_csrbank0_scratch2_w + attribute \src "ls180.v:1107.6-1107.38" + wire \libresocsim_csrbank0_scratch2_we + attribute \src "ls180.v:1102.12-1102.43" + wire width 8 \libresocsim_csrbank0_scratch3_r + attribute \src "ls180.v:1101.6-1101.38" + wire \libresocsim_csrbank0_scratch3_re + attribute \src "ls180.v:1104.12-1104.43" + wire width 8 \libresocsim_csrbank0_scratch3_w + attribute \src "ls180.v:1103.6-1103.38" + wire \libresocsim_csrbank0_scratch3_we + attribute \src "ls180.v:1133.6-1133.30" + wire \libresocsim_csrbank0_sel + attribute \src "ls180.v:1143.12-1143.37" + wire width 8 \libresocsim_csrbank1_in_r + attribute \src "ls180.v:1142.6-1142.32" + wire \libresocsim_csrbank1_in_re + attribute \src "ls180.v:1145.12-1145.37" + wire width 8 \libresocsim_csrbank1_in_w + attribute \src "ls180.v:1144.6-1144.32" + wire \libresocsim_csrbank1_in_we + attribute \src "ls180.v:1139.12-1139.38" + wire width 8 \libresocsim_csrbank1_oe0_r + attribute \src "ls180.v:1138.6-1138.33" + wire \libresocsim_csrbank1_oe0_re + attribute \src "ls180.v:1141.12-1141.38" + wire width 8 \libresocsim_csrbank1_oe0_w + attribute \src "ls180.v:1140.6-1140.33" + wire \libresocsim_csrbank1_oe0_we + attribute \src "ls180.v:1147.12-1147.39" + wire width 8 \libresocsim_csrbank1_out0_r + attribute \src "ls180.v:1146.6-1146.34" + wire \libresocsim_csrbank1_out0_re + attribute \src "ls180.v:1149.12-1149.39" + wire width 8 \libresocsim_csrbank1_out0_w + attribute \src "ls180.v:1148.6-1148.34" + wire \libresocsim_csrbank1_out0_we + attribute \src "ls180.v:1150.6-1150.30" + wire \libresocsim_csrbank1_sel + attribute \src "ls180.v:1160.12-1160.37" + wire width 8 \libresocsim_csrbank2_in_r + attribute \src "ls180.v:1159.6-1159.32" + wire \libresocsim_csrbank2_in_re + attribute \src "ls180.v:1162.12-1162.37" + wire width 8 \libresocsim_csrbank2_in_w + attribute \src "ls180.v:1161.6-1161.32" + wire \libresocsim_csrbank2_in_we + attribute \src "ls180.v:1156.12-1156.38" + wire width 8 \libresocsim_csrbank2_oe0_r + attribute \src "ls180.v:1155.6-1155.33" + wire \libresocsim_csrbank2_oe0_re + attribute \src "ls180.v:1158.12-1158.38" + wire width 8 \libresocsim_csrbank2_oe0_w + attribute \src "ls180.v:1157.6-1157.33" + wire \libresocsim_csrbank2_oe0_we + attribute \src "ls180.v:1164.12-1164.39" + wire width 8 \libresocsim_csrbank2_out0_r + attribute \src "ls180.v:1163.6-1163.34" + wire \libresocsim_csrbank2_out0_re + attribute \src "ls180.v:1166.12-1166.39" + wire width 8 \libresocsim_csrbank2_out0_w + attribute \src "ls180.v:1165.6-1165.34" + wire \libresocsim_csrbank2_out0_we + attribute \src "ls180.v:1167.6-1167.30" + wire \libresocsim_csrbank2_sel + attribute \src "ls180.v:1177.6-1177.30" + wire \libresocsim_csrbank3_r_r + attribute \src "ls180.v:1176.6-1176.31" + wire \libresocsim_csrbank3_r_re + attribute \src "ls180.v:1179.6-1179.30" + wire \libresocsim_csrbank3_r_w + attribute \src "ls180.v:1178.6-1178.31" + wire \libresocsim_csrbank3_r_we + attribute \src "ls180.v:1180.6-1180.30" + wire \libresocsim_csrbank3_sel + attribute \src "ls180.v:1173.12-1173.37" + wire width 3 \libresocsim_csrbank3_w0_r + attribute \src "ls180.v:1172.6-1172.32" + wire \libresocsim_csrbank3_w0_re + attribute \src "ls180.v:1175.12-1175.37" + wire width 3 \libresocsim_csrbank3_w0_w + attribute \src "ls180.v:1174.6-1174.32" + wire \libresocsim_csrbank3_w0_we + attribute \src "ls180.v:1186.12-1186.48" + wire width 4 \libresocsim_csrbank4_dfii_control0_r + attribute \src "ls180.v:1185.6-1185.43" + wire \libresocsim_csrbank4_dfii_control0_re + attribute \src "ls180.v:1188.12-1188.48" + wire width 4 \libresocsim_csrbank4_dfii_control0_w + attribute \src "ls180.v:1187.6-1187.43" + wire \libresocsim_csrbank4_dfii_control0_we + attribute \src "ls180.v:1198.12-1198.52" + wire width 8 \libresocsim_csrbank4_dfii_pi0_address0_r + attribute \src "ls180.v:1197.6-1197.47" + wire \libresocsim_csrbank4_dfii_pi0_address0_re + attribute \src "ls180.v:1200.12-1200.52" + wire width 8 \libresocsim_csrbank4_dfii_pi0_address0_w + attribute \src "ls180.v:1199.6-1199.47" + wire \libresocsim_csrbank4_dfii_pi0_address0_we + attribute \src "ls180.v:1194.12-1194.52" + wire width 5 \libresocsim_csrbank4_dfii_pi0_address1_r + attribute \src "ls180.v:1193.6-1193.47" + wire \libresocsim_csrbank4_dfii_pi0_address1_re + attribute \src "ls180.v:1196.12-1196.52" + wire width 5 \libresocsim_csrbank4_dfii_pi0_address1_w attribute \src "ls180.v:1195.6-1195.47" - wire \main_sdphy_cmdr_cmdr_source_source_first0 - attribute \src "ls180.v:1216.6-1216.47" - wire \main_sdphy_cmdr_cmdr_source_source_first1 - attribute \src "ls180.v:1196.6-1196.46" - wire \main_sdphy_cmdr_cmdr_source_source_last0 + wire \libresocsim_csrbank4_dfii_pi0_address1_we + attribute \src "ls180.v:1202.12-1202.53" + wire width 2 \libresocsim_csrbank4_dfii_pi0_baddress0_r + attribute \src "ls180.v:1201.6-1201.48" + wire \libresocsim_csrbank4_dfii_pi0_baddress0_re + attribute \src "ls180.v:1204.12-1204.53" + wire width 2 \libresocsim_csrbank4_dfii_pi0_baddress0_w + attribute \src "ls180.v:1203.6-1203.48" + wire \libresocsim_csrbank4_dfii_pi0_baddress0_we + attribute \src "ls180.v:1190.12-1190.52" + wire width 6 \libresocsim_csrbank4_dfii_pi0_command0_r + attribute \src "ls180.v:1189.6-1189.47" + wire \libresocsim_csrbank4_dfii_pi0_command0_re + attribute \src "ls180.v:1192.12-1192.52" + wire width 6 \libresocsim_csrbank4_dfii_pi0_command0_w + attribute \src "ls180.v:1191.6-1191.47" + wire \libresocsim_csrbank4_dfii_pi0_command0_we + attribute \src "ls180.v:1218.12-1218.51" + wire width 8 \libresocsim_csrbank4_dfii_pi0_rddata0_r attribute \src "ls180.v:1217.6-1217.46" - wire \main_sdphy_cmdr_cmdr_source_source_last1 - attribute \src "ls180.v:1197.12-1197.60" - wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data0 - attribute \src "ls180.v:1218.12-1218.60" - wire width 8 \main_sdphy_cmdr_cmdr_source_source_payload_data1 - attribute \src "ls180.v:1194.5-1194.46" - wire \main_sdphy_cmdr_cmdr_source_source_ready0 - attribute \src "ls180.v:1215.6-1215.47" - wire \main_sdphy_cmdr_cmdr_source_source_ready1 - attribute \src "ls180.v:1193.6-1193.47" - wire \main_sdphy_cmdr_cmdr_source_source_valid0 - attribute \src "ls180.v:1214.6-1214.47" - wire \main_sdphy_cmdr_cmdr_source_source_valid1 - attribute \src "ls180.v:1198.6-1198.32" - wire \main_sdphy_cmdr_cmdr_start - attribute \src "ls180.v:1181.11-1181.32" - wire width 8 \main_sdphy_cmdr_count - attribute \src "ls180.v:1820.11-1820.60" - wire width 8 \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 - attribute \src "ls180.v:1821.5-1821.57" - wire \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 - attribute \src "ls180.v:1156.5-1156.42" - wire \main_sdphy_cmdr_pads_in_pads_in_first - attribute \src "ls180.v:1157.5-1157.41" - wire \main_sdphy_cmdr_pads_in_pads_in_last - attribute \src "ls180.v:1158.5-1158.48" - wire \main_sdphy_cmdr_pads_in_pads_in_payload_clk - attribute \src "ls180.v:1159.6-1159.51" - wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i - attribute \src "ls180.v:1160.5-1160.50" - wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o - attribute \src "ls180.v:1161.5-1161.51" - wire \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe - attribute \src "ls180.v:1162.12-1162.58" - wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_i - attribute \src "ls180.v:1163.11-1163.57" - wire width 4 \main_sdphy_cmdr_pads_in_pads_in_payload_data_o - attribute \src "ls180.v:1164.5-1164.52" - wire \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe - attribute \src "ls180.v:1155.6-1155.43" - wire \main_sdphy_cmdr_pads_in_pads_in_ready - attribute \src "ls180.v:1154.6-1154.43" - wire \main_sdphy_cmdr_pads_in_pads_in_valid - attribute \src "ls180.v:1166.5-1166.41" - wire \main_sdphy_cmdr_pads_out_payload_clk - attribute \src "ls180.v:1167.5-1167.43" - wire \main_sdphy_cmdr_pads_out_payload_cmd_o - attribute \src "ls180.v:1168.5-1168.44" - wire \main_sdphy_cmdr_pads_out_payload_cmd_oe - attribute \src "ls180.v:1169.11-1169.50" - wire width 4 \main_sdphy_cmdr_pads_out_payload_data_o - attribute \src "ls180.v:1170.5-1170.45" - wire \main_sdphy_cmdr_pads_out_payload_data_oe - attribute \src "ls180.v:1165.6-1165.36" - wire \main_sdphy_cmdr_pads_out_ready - attribute \src "ls180.v:1173.5-1173.30" - wire \main_sdphy_cmdr_sink_last - attribute \src "ls180.v:1174.11-1174.46" - wire width 8 \main_sdphy_cmdr_sink_payload_length - attribute \src "ls180.v:1172.5-1172.31" - wire \main_sdphy_cmdr_sink_ready - attribute \src "ls180.v:1171.5-1171.31" - wire \main_sdphy_cmdr_sink_valid - attribute \src "ls180.v:1177.5-1177.32" - wire \main_sdphy_cmdr_source_last - attribute \src "ls180.v:1178.11-1178.46" - wire width 8 \main_sdphy_cmdr_source_payload_data - attribute \src "ls180.v:1179.11-1179.48" - wire width 3 \main_sdphy_cmdr_source_payload_status - attribute \src "ls180.v:1176.5-1176.33" - wire \main_sdphy_cmdr_source_ready - attribute \src "ls180.v:1175.5-1175.33" - wire \main_sdphy_cmdr_source_valid - attribute \src "ls180.v:1180.12-1180.35" - wire width 32 \main_sdphy_cmdr_timeout - attribute \src "ls180.v:1822.12-1822.63" - wire width 32 \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 - attribute \src "ls180.v:1823.5-1823.59" - wire \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 - attribute \src "ls180.v:1153.11-1153.32" - wire width 8 \main_sdphy_cmdw_count - attribute \src "ls180.v:1816.11-1816.59" - wire width 8 \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value - attribute \src "ls180.v:1817.5-1817.56" - wire \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce - attribute \src "ls180.v:1152.5-1152.25" - wire \main_sdphy_cmdw_done - attribute \src "ls180.v:1140.6-1140.43" - wire \main_sdphy_cmdw_pads_in_payload_cmd_i - attribute \src "ls180.v:1141.12-1141.50" - wire width 4 \main_sdphy_cmdw_pads_in_payload_data_i - attribute \src "ls180.v:1139.6-1139.35" - wire \main_sdphy_cmdw_pads_in_valid - attribute \src "ls180.v:1143.5-1143.41" - wire \main_sdphy_cmdw_pads_out_payload_clk - attribute \src "ls180.v:1144.5-1144.43" - wire \main_sdphy_cmdw_pads_out_payload_cmd_o - attribute \src "ls180.v:1145.5-1145.44" - wire \main_sdphy_cmdw_pads_out_payload_cmd_oe - attribute \src "ls180.v:1146.11-1146.50" - wire width 4 \main_sdphy_cmdw_pads_out_payload_data_o - attribute \src "ls180.v:1147.5-1147.45" - wire \main_sdphy_cmdw_pads_out_payload_data_oe - attribute \src "ls180.v:1142.6-1142.36" - wire \main_sdphy_cmdw_pads_out_ready - attribute \src "ls180.v:1150.5-1150.30" - wire \main_sdphy_cmdw_sink_last - attribute \src "ls180.v:1151.11-1151.44" - wire width 8 \main_sdphy_cmdw_sink_payload_data - attribute \src "ls180.v:1149.5-1149.31" - wire \main_sdphy_cmdw_sink_ready - attribute \src "ls180.v:1148.5-1148.31" - wire \main_sdphy_cmdw_sink_valid - attribute \src "ls180.v:1337.11-1337.33" - wire width 10 \main_sdphy_datar_count - attribute \src "ls180.v:1836.11-1836.62" - wire width 10 \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 - attribute \src "ls180.v:1837.5-1837.59" - wire \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 - attribute \src "ls180.v:1377.6-1377.43" - wire \main_sdphy_datar_datar_buf_sink_first - attribute \src "ls180.v:1378.6-1378.42" - wire \main_sdphy_datar_datar_buf_sink_last - attribute \src "ls180.v:1379.12-1379.56" - wire width 8 \main_sdphy_datar_datar_buf_sink_payload_data - attribute \src "ls180.v:1376.6-1376.43" - wire \main_sdphy_datar_datar_buf_sink_ready - attribute \src "ls180.v:1375.6-1375.43" - wire \main_sdphy_datar_datar_buf_sink_valid - attribute \src "ls180.v:1382.5-1382.44" - wire \main_sdphy_datar_datar_buf_source_first - attribute \src "ls180.v:1383.5-1383.43" - wire \main_sdphy_datar_datar_buf_source_last - attribute \src "ls180.v:1384.11-1384.57" - wire width 8 \main_sdphy_datar_datar_buf_source_payload_data - attribute \src "ls180.v:1381.6-1381.45" - wire \main_sdphy_datar_datar_buf_source_ready - attribute \src "ls180.v:1380.5-1380.44" - wire \main_sdphy_datar_datar_buf_source_valid - attribute \src "ls180.v:1367.5-1367.43" - wire \main_sdphy_datar_datar_converter_demux - attribute \src "ls180.v:1368.6-1368.48" - wire \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:1358.5-1358.48" - wire \main_sdphy_datar_datar_converter_sink_first - attribute \src "ls180.v:1359.5-1359.47" - wire \main_sdphy_datar_datar_converter_sink_last - attribute \src "ls180.v:1360.12-1360.62" - wire width 4 \main_sdphy_datar_datar_converter_sink_payload_data - attribute \src "ls180.v:1357.6-1357.49" - wire \main_sdphy_datar_datar_converter_sink_ready - attribute \src "ls180.v:1356.6-1356.49" - wire \main_sdphy_datar_datar_converter_sink_valid - attribute \src "ls180.v:1363.5-1363.50" - wire \main_sdphy_datar_datar_converter_source_first - attribute \src "ls180.v:1364.5-1364.49" - wire \main_sdphy_datar_datar_converter_source_last - attribute \src "ls180.v:1365.11-1365.63" - wire width 8 \main_sdphy_datar_datar_converter_source_payload_data - attribute \src "ls180.v:1366.11-1366.76" - wire width 2 \main_sdphy_datar_datar_converter_source_payload_valid_token_count - attribute \src "ls180.v:1362.6-1362.51" - wire \main_sdphy_datar_datar_converter_source_ready - attribute \src "ls180.v:1361.6-1361.51" - wire \main_sdphy_datar_datar_converter_source_valid - attribute \src "ls180.v:1369.5-1369.48" - wire \main_sdphy_datar_datar_converter_strobe_all - attribute \src "ls180.v:1340.6-1340.42" - wire \main_sdphy_datar_datar_pads_in_first - attribute \src "ls180.v:1341.6-1341.41" - wire \main_sdphy_datar_datar_pads_in_last - attribute \src "ls180.v:1342.6-1342.48" - wire \main_sdphy_datar_datar_pads_in_payload_clk - attribute \src "ls180.v:1343.6-1343.50" - wire \main_sdphy_datar_datar_pads_in_payload_cmd_i - attribute \src "ls180.v:1344.6-1344.50" - wire \main_sdphy_datar_datar_pads_in_payload_cmd_o - attribute \src "ls180.v:1345.6-1345.51" - wire \main_sdphy_datar_datar_pads_in_payload_cmd_oe - attribute \src "ls180.v:1346.12-1346.57" - wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_i - attribute \src "ls180.v:1347.12-1347.57" - wire width 4 \main_sdphy_datar_datar_pads_in_payload_data_o - attribute \src "ls180.v:1348.6-1348.52" - wire \main_sdphy_datar_datar_pads_in_payload_data_oe - attribute \src "ls180.v:1339.5-1339.41" - wire \main_sdphy_datar_datar_pads_in_ready - attribute \src "ls180.v:1338.6-1338.42" - wire \main_sdphy_datar_datar_pads_in_valid - attribute \src "ls180.v:1385.5-1385.33" - wire \main_sdphy_datar_datar_reset - attribute \src "ls180.v:1840.5-1840.62" - wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 - attribute \src "ls180.v:1841.5-1841.65" - wire \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 - attribute \src "ls180.v:1355.5-1355.31" - wire \main_sdphy_datar_datar_run - attribute \src "ls180.v:1351.6-1351.49" - wire \main_sdphy_datar_datar_source_source_first0 - attribute \src "ls180.v:1372.6-1372.49" - wire \main_sdphy_datar_datar_source_source_first1 - attribute \src "ls180.v:1352.6-1352.48" - wire \main_sdphy_datar_datar_source_source_last0 - attribute \src "ls180.v:1373.6-1373.48" - wire \main_sdphy_datar_datar_source_source_last1 - attribute \src "ls180.v:1353.12-1353.62" - wire width 8 \main_sdphy_datar_datar_source_source_payload_data0 - attribute \src "ls180.v:1374.12-1374.62" - wire width 8 \main_sdphy_datar_datar_source_source_payload_data1 - attribute \src "ls180.v:1350.5-1350.48" - wire \main_sdphy_datar_datar_source_source_ready0 - attribute \src "ls180.v:1371.6-1371.49" - wire \main_sdphy_datar_datar_source_source_ready1 - attribute \src "ls180.v:1349.6-1349.49" - wire \main_sdphy_datar_datar_source_source_valid0 - attribute \src "ls180.v:1370.6-1370.49" - wire \main_sdphy_datar_datar_source_source_valid1 - attribute \src "ls180.v:1354.6-1354.34" - wire \main_sdphy_datar_datar_start - attribute \src "ls180.v:1310.5-1310.43" - wire \main_sdphy_datar_pads_in_pads_in_first - attribute \src "ls180.v:1311.5-1311.42" - wire \main_sdphy_datar_pads_in_pads_in_last - attribute \src "ls180.v:1312.5-1312.49" - wire \main_sdphy_datar_pads_in_pads_in_payload_clk - attribute \src "ls180.v:1313.6-1313.52" - wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_i - attribute \src "ls180.v:1314.5-1314.51" - wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_o - attribute \src "ls180.v:1315.5-1315.52" - wire \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe - attribute \src "ls180.v:1316.12-1316.59" - wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_i - attribute \src "ls180.v:1317.11-1317.58" - wire width 4 \main_sdphy_datar_pads_in_pads_in_payload_data_o - attribute \src "ls180.v:1318.5-1318.53" - wire \main_sdphy_datar_pads_in_pads_in_payload_data_oe - attribute \src "ls180.v:1309.6-1309.44" - wire \main_sdphy_datar_pads_in_pads_in_ready - attribute \src "ls180.v:1308.6-1308.44" - wire \main_sdphy_datar_pads_in_pads_in_valid - attribute \src "ls180.v:1320.5-1320.42" - wire \main_sdphy_datar_pads_out_payload_clk - attribute \src "ls180.v:1321.5-1321.44" - wire \main_sdphy_datar_pads_out_payload_cmd_o - attribute \src "ls180.v:1322.5-1322.45" - wire \main_sdphy_datar_pads_out_payload_cmd_oe - attribute \src "ls180.v:1323.11-1323.51" - wire width 4 \main_sdphy_datar_pads_out_payload_data_o - attribute \src "ls180.v:1324.5-1324.46" - wire \main_sdphy_datar_pads_out_payload_data_oe - attribute \src "ls180.v:1319.6-1319.37" - wire \main_sdphy_datar_pads_out_ready - attribute \src "ls180.v:1327.5-1327.31" - wire \main_sdphy_datar_sink_last - attribute \src "ls180.v:1328.11-1328.53" - wire width 10 \main_sdphy_datar_sink_payload_block_length - attribute \src "ls180.v:1326.5-1326.32" - wire \main_sdphy_datar_sink_ready - attribute \src "ls180.v:1325.5-1325.32" - wire \main_sdphy_datar_sink_valid - attribute \src "ls180.v:1331.5-1331.34" - wire \main_sdphy_datar_source_first - attribute \src "ls180.v:1332.5-1332.33" - wire \main_sdphy_datar_source_last - attribute \src "ls180.v:1333.11-1333.47" - wire width 8 \main_sdphy_datar_source_payload_data - attribute \src "ls180.v:1334.11-1334.49" - wire width 3 \main_sdphy_datar_source_payload_status - attribute \src "ls180.v:1330.5-1330.34" - wire \main_sdphy_datar_source_ready - attribute \src "ls180.v:1329.5-1329.34" - wire \main_sdphy_datar_source_valid - attribute \src "ls180.v:1335.5-1335.26" - wire \main_sdphy_datar_stop - attribute \src "ls180.v:1336.12-1336.36" - wire width 32 \main_sdphy_datar_timeout - attribute \src "ls180.v:1838.12-1838.65" - wire width 32 \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 - attribute \src "ls180.v:1839.5-1839.61" - wire \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 - attribute \src "ls180.v:1245.11-1245.33" - wire width 8 \main_sdphy_dataw_count - attribute \src "ls180.v:1832.11-1832.54" - wire width 8 \main_sdphy_dataw_count_sdphy_fsm_next_value - attribute \src "ls180.v:1833.5-1833.51" - wire \main_sdphy_dataw_count_sdphy_fsm_next_value_ce - attribute \src "ls180.v:1299.6-1299.42" - wire \main_sdphy_dataw_crcr_buf_sink_first - attribute \src "ls180.v:1300.6-1300.41" - wire \main_sdphy_dataw_crcr_buf_sink_last - attribute \src "ls180.v:1301.12-1301.55" - wire width 8 \main_sdphy_dataw_crcr_buf_sink_payload_data - attribute \src "ls180.v:1298.6-1298.42" - wire \main_sdphy_dataw_crcr_buf_sink_ready - attribute \src "ls180.v:1297.6-1297.42" - wire \main_sdphy_dataw_crcr_buf_sink_valid - attribute \src "ls180.v:1304.5-1304.43" - wire \main_sdphy_dataw_crcr_buf_source_first - attribute \src "ls180.v:1305.5-1305.42" - wire \main_sdphy_dataw_crcr_buf_source_last - attribute \src "ls180.v:1306.11-1306.56" - wire width 8 \main_sdphy_dataw_crcr_buf_source_payload_data - attribute \src "ls180.v:1303.6-1303.44" - wire \main_sdphy_dataw_crcr_buf_source_ready - attribute \src "ls180.v:1302.5-1302.43" - wire \main_sdphy_dataw_crcr_buf_source_valid - attribute \src "ls180.v:1289.11-1289.48" - wire width 3 \main_sdphy_dataw_crcr_converter_demux - attribute \src "ls180.v:1290.6-1290.47" - wire \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:1280.5-1280.47" - wire \main_sdphy_dataw_crcr_converter_sink_first - attribute \src "ls180.v:1281.5-1281.46" - wire \main_sdphy_dataw_crcr_converter_sink_last - attribute \src "ls180.v:1282.6-1282.55" - wire \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:1279.6-1279.48" - wire \main_sdphy_dataw_crcr_converter_sink_ready - attribute \src "ls180.v:1278.6-1278.48" - wire \main_sdphy_dataw_crcr_converter_sink_valid - attribute \src "ls180.v:1285.5-1285.49" - wire \main_sdphy_dataw_crcr_converter_source_first - attribute \src "ls180.v:1286.5-1286.48" - wire \main_sdphy_dataw_crcr_converter_source_last - attribute \src "ls180.v:1287.11-1287.62" - wire width 8 \main_sdphy_dataw_crcr_converter_source_payload_data - attribute \src "ls180.v:1288.11-1288.75" - wire width 4 \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count - attribute \src "ls180.v:1284.6-1284.50" - wire \main_sdphy_dataw_crcr_converter_source_ready - attribute \src "ls180.v:1283.6-1283.50" - wire \main_sdphy_dataw_crcr_converter_source_valid - attribute \src "ls180.v:1291.5-1291.47" - wire \main_sdphy_dataw_crcr_converter_strobe_all - attribute \src "ls180.v:1262.6-1262.41" - wire \main_sdphy_dataw_crcr_pads_in_first - attribute \src "ls180.v:1263.6-1263.40" - wire \main_sdphy_dataw_crcr_pads_in_last - attribute \src "ls180.v:1264.6-1264.47" - wire \main_sdphy_dataw_crcr_pads_in_payload_clk - attribute \src "ls180.v:1265.6-1265.49" - wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_i - attribute \src "ls180.v:1266.6-1266.49" - wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_o - attribute \src "ls180.v:1267.6-1267.50" - wire \main_sdphy_dataw_crcr_pads_in_payload_cmd_oe - attribute \src "ls180.v:1268.12-1268.56" - wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_i - attribute \src "ls180.v:1269.12-1269.56" - wire width 4 \main_sdphy_dataw_crcr_pads_in_payload_data_o - attribute \src "ls180.v:1270.6-1270.51" - wire \main_sdphy_dataw_crcr_pads_in_payload_data_oe - attribute \src "ls180.v:1261.5-1261.40" - wire \main_sdphy_dataw_crcr_pads_in_ready - attribute \src "ls180.v:1260.6-1260.41" - wire \main_sdphy_dataw_crcr_pads_in_valid - attribute \src "ls180.v:1307.5-1307.32" - wire \main_sdphy_dataw_crcr_reset - attribute \src "ls180.v:1828.5-1828.59" - wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value - attribute \src "ls180.v:1829.5-1829.62" - wire \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce - attribute \src "ls180.v:1277.5-1277.30" - wire \main_sdphy_dataw_crcr_run - attribute \src "ls180.v:1273.6-1273.48" - wire \main_sdphy_dataw_crcr_source_source_first0 - attribute \src "ls180.v:1294.6-1294.48" - wire \main_sdphy_dataw_crcr_source_source_first1 - attribute \src "ls180.v:1274.6-1274.47" - wire \main_sdphy_dataw_crcr_source_source_last0 - attribute \src "ls180.v:1295.6-1295.47" - wire \main_sdphy_dataw_crcr_source_source_last1 - attribute \src "ls180.v:1275.12-1275.61" - wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data0 - attribute \src "ls180.v:1296.12-1296.61" - wire width 8 \main_sdphy_dataw_crcr_source_source_payload_data1 - attribute \src "ls180.v:1272.5-1272.47" - wire \main_sdphy_dataw_crcr_source_source_ready0 - attribute \src "ls180.v:1293.6-1293.48" - wire \main_sdphy_dataw_crcr_source_source_ready1 - attribute \src "ls180.v:1271.6-1271.48" - wire \main_sdphy_dataw_crcr_source_source_valid0 - attribute \src "ls180.v:1292.6-1292.48" - wire \main_sdphy_dataw_crcr_source_source_valid1 - attribute \src "ls180.v:1276.6-1276.33" - wire \main_sdphy_dataw_crcr_start - attribute \src "ls180.v:1259.5-1259.27" - wire \main_sdphy_dataw_error - attribute \src "ls180.v:1248.5-1248.43" - wire \main_sdphy_dataw_pads_in_pads_in_first - attribute \src "ls180.v:1249.5-1249.42" - wire \main_sdphy_dataw_pads_in_pads_in_last - attribute \src "ls180.v:1250.5-1250.49" - wire \main_sdphy_dataw_pads_in_pads_in_payload_clk - attribute \src "ls180.v:1251.5-1251.51" - wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i - attribute \src "ls180.v:1252.5-1252.51" - wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o - attribute \src "ls180.v:1253.5-1253.52" - wire \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe - attribute \src "ls180.v:1254.11-1254.58" - wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_i - attribute \src "ls180.v:1255.11-1255.58" - wire width 4 \main_sdphy_dataw_pads_in_pads_in_payload_data_o - attribute \src "ls180.v:1256.5-1256.53" - wire \main_sdphy_dataw_pads_in_pads_in_payload_data_oe - attribute \src "ls180.v:1247.6-1247.44" - wire \main_sdphy_dataw_pads_in_pads_in_ready - attribute \src "ls180.v:1246.5-1246.43" - wire \main_sdphy_dataw_pads_in_pads_in_valid - attribute \src "ls180.v:1231.6-1231.44" - wire \main_sdphy_dataw_pads_in_payload_cmd_i - attribute \src "ls180.v:1232.12-1232.51" - wire width 4 \main_sdphy_dataw_pads_in_payload_data_i - attribute \src "ls180.v:1230.6-1230.36" - wire \main_sdphy_dataw_pads_in_valid - attribute \src "ls180.v:1234.5-1234.42" - wire \main_sdphy_dataw_pads_out_payload_clk - attribute \src "ls180.v:1235.5-1235.44" - wire \main_sdphy_dataw_pads_out_payload_cmd_o - attribute \src "ls180.v:1236.5-1236.45" - wire \main_sdphy_dataw_pads_out_payload_cmd_oe - attribute \src "ls180.v:1237.11-1237.51" - wire width 4 \main_sdphy_dataw_pads_out_payload_data_o - attribute \src "ls180.v:1238.5-1238.46" - wire \main_sdphy_dataw_pads_out_payload_data_oe - attribute \src "ls180.v:1233.6-1233.37" - wire \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:1241.5-1241.32" - wire \main_sdphy_dataw_sink_first - attribute \src "ls180.v:1242.5-1242.31" - wire \main_sdphy_dataw_sink_last - attribute \src "ls180.v:1243.11-1243.45" - wire width 8 \main_sdphy_dataw_sink_payload_data - attribute \src "ls180.v:1240.5-1240.32" - wire \main_sdphy_dataw_sink_ready - attribute \src "ls180.v:1239.5-1239.32" - wire \main_sdphy_dataw_sink_valid - attribute \src "ls180.v:1257.5-1257.27" - wire \main_sdphy_dataw_start - attribute \src "ls180.v:1244.5-1244.26" - wire \main_sdphy_dataw_stop - attribute \src "ls180.v:1258.5-1258.27" - wire \main_sdphy_dataw_valid - attribute \src "ls180.v:1138.11-1138.32" - wire width 8 \main_sdphy_init_count - attribute \src "ls180.v:1812.11-1812.59" - wire width 8 \main_sdphy_init_count_sdphy_sdphyinit_next_value - attribute \src "ls180.v:1813.5-1813.56" - wire \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce - attribute \src "ls180.v:1126.6-1126.34" - wire \main_sdphy_init_initialize_r - attribute \src "ls180.v:1125.6-1125.35" - wire \main_sdphy_init_initialize_re - attribute \src "ls180.v:1128.5-1128.33" - wire \main_sdphy_init_initialize_w - attribute \src "ls180.v:1127.6-1127.35" - wire \main_sdphy_init_initialize_we - attribute \src "ls180.v:1130.6-1130.43" - wire \main_sdphy_init_pads_in_payload_cmd_i - attribute \src "ls180.v:1131.12-1131.50" - wire width 4 \main_sdphy_init_pads_in_payload_data_i - attribute \src "ls180.v:1129.6-1129.35" - wire \main_sdphy_init_pads_in_valid - attribute \src "ls180.v:1133.5-1133.41" - wire \main_sdphy_init_pads_out_payload_clk - attribute \src "ls180.v:1134.5-1134.43" - wire \main_sdphy_init_pads_out_payload_cmd_o - attribute \src "ls180.v:1135.5-1135.44" - wire \main_sdphy_init_pads_out_payload_cmd_oe - attribute \src "ls180.v:1136.11-1136.50" - wire width 4 \main_sdphy_init_pads_out_payload_data_o - attribute \src "ls180.v:1137.5-1137.45" - wire \main_sdphy_init_pads_out_payload_data_oe - attribute \src "ls180.v:1132.6-1132.36" - wire \main_sdphy_init_pads_out_ready - attribute \src "ls180.v:1386.6-1386.27" - wire \main_sdphy_sdpads_clk - attribute \src "ls180.v:1387.5-1387.28" - wire \main_sdphy_sdpads_cmd_i - attribute \src "ls180.v:1388.6-1388.29" - wire \main_sdphy_sdpads_cmd_o - attribute \src "ls180.v:1389.6-1389.30" - wire \main_sdphy_sdpads_cmd_oe - attribute \src "ls180.v:1390.11-1390.35" - wire width 4 \main_sdphy_sdpads_data_i - attribute \src "ls180.v:1391.12-1391.36" - wire width 4 \main_sdphy_sdpads_data_o - attribute \src "ls180.v:1392.6-1392.31" - wire \main_sdphy_sdpads_data_oe - attribute \src "ls180.v:1115.6-1115.23" - wire \main_sdphy_status - attribute \src "ls180.v:1116.6-1116.19" - wire \main_sdphy_we - attribute \src "ls180.v:332.5-332.26" - wire \main_sdram_address_re - attribute \src "ls180.v:331.12-331.38" - wire width 13 \main_sdram_address_storage - attribute \src "ls180.v:334.5-334.27" - wire \main_sdram_baddress_re - attribute \src "ls180.v:333.11-333.38" - wire width 2 \main_sdram_baddress_storage - attribute \src "ls180.v:430.5-430.43" - wire \main_sdram_bankmachine0_auto_precharge - attribute \src "ls180.v:452.11-452.63" - wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_consume - attribute \src "ls180.v:457.6-457.58" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:462.6-462.64" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:463.6-463.63" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:461.13-461.78" - wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:460.6-460.69" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:466.6-466.65" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:467.6-467.64" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:465.13-465.79" - wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:464.6-464.70" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:449.11-449.61" - wire width 4 \main_sdram_bankmachine0_cmd_buffer_lookahead_level - attribute \src "ls180.v:451.11-451.63" - wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_produce - attribute \src "ls180.v:458.12-458.67" - wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:459.13-459.70" - wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:450.5-450.57" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - attribute \src "ls180.v:433.5-433.60" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:434.5-434.59" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:436.13-436.75" - wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:435.6-435.66" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:432.6-432.61" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:431.6-431.61" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:439.6-439.63" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:440.6-440.62" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:442.13-442.77" - wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:441.6-441.68" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:438.6-438.63" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:437.6-437.63" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:447.13-447.71" - wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din - attribute \src "ls180.v:448.13-448.72" - wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout - attribute \src "ls180.v:445.6-445.63" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re - attribute \src "ls180.v:446.6-446.69" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable - attribute \src "ls180.v:443.6-443.63" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we - attribute \src "ls180.v:444.6-444.69" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - attribute \src "ls180.v:453.11-453.66" - wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:454.13-454.70" - wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:456.13-456.70" - wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:455.6-455.60" - wire \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:470.6-470.51" - wire \main_sdram_bankmachine0_cmd_buffer_sink_first - attribute \src "ls180.v:471.6-471.50" - wire \main_sdram_bankmachine0_cmd_buffer_sink_last - attribute \src "ls180.v:473.13-473.65" - wire width 22 \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:472.6-472.56" - wire \main_sdram_bankmachine0_cmd_buffer_sink_payload_we - attribute \src "ls180.v:469.6-469.51" - wire \main_sdram_bankmachine0_cmd_buffer_sink_ready - attribute \src "ls180.v:468.6-468.51" - wire \main_sdram_bankmachine0_cmd_buffer_sink_valid - attribute \src "ls180.v:476.5-476.52" - wire \main_sdram_bankmachine0_cmd_buffer_source_first - attribute \src "ls180.v:477.5-477.51" - wire \main_sdram_bankmachine0_cmd_buffer_source_last - attribute \src "ls180.v:479.12-479.66" - wire width 22 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr - attribute \src "ls180.v:478.5-478.57" - wire \main_sdram_bankmachine0_cmd_buffer_source_payload_we - attribute \src "ls180.v:475.6-475.53" - wire \main_sdram_bankmachine0_cmd_buffer_source_ready - attribute \src "ls180.v:474.5-474.52" - wire \main_sdram_bankmachine0_cmd_buffer_source_valid - attribute \src "ls180.v:422.12-422.49" - wire width 13 \main_sdram_bankmachine0_cmd_payload_a - attribute \src "ls180.v:423.12-423.50" - wire width 2 \main_sdram_bankmachine0_cmd_payload_ba - attribute \src "ls180.v:424.5-424.44" - wire \main_sdram_bankmachine0_cmd_payload_cas - attribute \src "ls180.v:427.5-427.47" - wire \main_sdram_bankmachine0_cmd_payload_is_cmd - attribute \src "ls180.v:428.5-428.48" - wire \main_sdram_bankmachine0_cmd_payload_is_read - attribute \src "ls180.v:429.5-429.49" - wire \main_sdram_bankmachine0_cmd_payload_is_write - attribute \src "ls180.v:425.5-425.44" - wire \main_sdram_bankmachine0_cmd_payload_ras - attribute \src "ls180.v:426.5-426.43" - wire \main_sdram_bankmachine0_cmd_payload_we - attribute \src "ls180.v:421.5-421.38" - wire \main_sdram_bankmachine0_cmd_ready - attribute \src "ls180.v:420.5-420.38" - wire \main_sdram_bankmachine0_cmd_valid - attribute \src "ls180.v:419.5-419.40" - wire \main_sdram_bankmachine0_refresh_gnt - attribute \src "ls180.v:418.6-418.41" - wire \main_sdram_bankmachine0_refresh_req - attribute \src "ls180.v:414.13-414.45" - wire width 22 \main_sdram_bankmachine0_req_addr - attribute \src "ls180.v:415.6-415.38" - wire \main_sdram_bankmachine0_req_lock - attribute \src "ls180.v:417.5-417.44" - wire \main_sdram_bankmachine0_req_rdata_valid - attribute \src "ls180.v:412.6-412.39" - wire \main_sdram_bankmachine0_req_ready - attribute \src "ls180.v:411.6-411.39" - wire \main_sdram_bankmachine0_req_valid - attribute \src "ls180.v:416.5-416.44" - wire \main_sdram_bankmachine0_req_wdata_ready - attribute \src "ls180.v:413.6-413.36" - wire \main_sdram_bankmachine0_req_we - attribute \src "ls180.v:480.12-480.39" - wire width 13 \main_sdram_bankmachine0_row - attribute \src "ls180.v:484.5-484.38" - wire \main_sdram_bankmachine0_row_close - attribute \src "ls180.v:485.5-485.47" - wire \main_sdram_bankmachine0_row_col_n_addr_sel - attribute \src "ls180.v:482.6-482.37" - wire \main_sdram_bankmachine0_row_hit - attribute \src "ls180.v:483.5-483.37" - wire \main_sdram_bankmachine0_row_open - attribute \src "ls180.v:481.5-481.39" - wire \main_sdram_bankmachine0_row_opened + wire \libresocsim_csrbank4_dfii_pi0_rddata0_re + attribute \src "ls180.v:1220.12-1220.51" + wire width 8 \libresocsim_csrbank4_dfii_pi0_rddata0_w + attribute \src "ls180.v:1219.6-1219.46" + wire \libresocsim_csrbank4_dfii_pi0_rddata0_we + attribute \src "ls180.v:1214.12-1214.51" + wire width 8 \libresocsim_csrbank4_dfii_pi0_rddata1_r + attribute \src "ls180.v:1213.6-1213.46" + wire \libresocsim_csrbank4_dfii_pi0_rddata1_re + attribute \src "ls180.v:1216.12-1216.51" + wire width 8 \libresocsim_csrbank4_dfii_pi0_rddata1_w + attribute \src "ls180.v:1215.6-1215.46" + wire \libresocsim_csrbank4_dfii_pi0_rddata1_we + attribute \src "ls180.v:1210.12-1210.51" + wire width 8 \libresocsim_csrbank4_dfii_pi0_wrdata0_r + attribute \src "ls180.v:1209.6-1209.46" + wire \libresocsim_csrbank4_dfii_pi0_wrdata0_re + attribute \src "ls180.v:1212.12-1212.51" + wire width 8 \libresocsim_csrbank4_dfii_pi0_wrdata0_w + attribute \src "ls180.v:1211.6-1211.46" + wire \libresocsim_csrbank4_dfii_pi0_wrdata0_we + attribute \src "ls180.v:1206.12-1206.51" + wire width 8 \libresocsim_csrbank4_dfii_pi0_wrdata1_r + attribute \src "ls180.v:1205.6-1205.46" + wire \libresocsim_csrbank4_dfii_pi0_wrdata1_re + attribute \src "ls180.v:1208.12-1208.51" + wire width 8 \libresocsim_csrbank4_dfii_pi0_wrdata1_w + attribute \src "ls180.v:1207.6-1207.46" + wire \libresocsim_csrbank4_dfii_pi0_wrdata1_we + attribute \src "ls180.v:1221.6-1221.30" + wire \libresocsim_csrbank4_sel + attribute \src "ls180.v:1259.6-1259.32" + wire \libresocsim_csrbank5_en0_r + attribute \src "ls180.v:1258.6-1258.33" + wire \libresocsim_csrbank5_en0_re + attribute \src "ls180.v:1261.6-1261.32" + wire \libresocsim_csrbank5_en0_w + attribute \src "ls180.v:1260.6-1260.33" + wire \libresocsim_csrbank5_en0_we + attribute \src "ls180.v:1283.6-1283.39" + wire \libresocsim_csrbank5_ev_enable0_r + attribute \src "ls180.v:1282.6-1282.40" + wire \libresocsim_csrbank5_ev_enable0_re + attribute \src "ls180.v:1285.6-1285.39" + wire \libresocsim_csrbank5_ev_enable0_w + attribute \src "ls180.v:1284.6-1284.40" + wire \libresocsim_csrbank5_ev_enable0_we + attribute \src "ls180.v:1239.12-1239.40" + wire width 8 \libresocsim_csrbank5_load0_r + attribute \src "ls180.v:1238.6-1238.35" + wire \libresocsim_csrbank5_load0_re + attribute \src "ls180.v:1241.12-1241.40" + wire width 8 \libresocsim_csrbank5_load0_w + attribute \src "ls180.v:1240.6-1240.35" + wire \libresocsim_csrbank5_load0_we + attribute \src "ls180.v:1235.12-1235.40" + wire width 8 \libresocsim_csrbank5_load1_r + attribute \src "ls180.v:1234.6-1234.35" + wire \libresocsim_csrbank5_load1_re + attribute \src "ls180.v:1237.12-1237.40" + wire width 8 \libresocsim_csrbank5_load1_w + attribute \src "ls180.v:1236.6-1236.35" + wire \libresocsim_csrbank5_load1_we + attribute \src "ls180.v:1231.12-1231.40" + wire width 8 \libresocsim_csrbank5_load2_r + attribute \src "ls180.v:1230.6-1230.35" + wire \libresocsim_csrbank5_load2_re + attribute \src "ls180.v:1233.12-1233.40" + wire width 8 \libresocsim_csrbank5_load2_w + attribute \src "ls180.v:1232.6-1232.35" + wire \libresocsim_csrbank5_load2_we + attribute \src "ls180.v:1227.12-1227.40" + wire width 8 \libresocsim_csrbank5_load3_r + attribute \src "ls180.v:1226.6-1226.35" + wire \libresocsim_csrbank5_load3_re + attribute \src "ls180.v:1229.12-1229.40" + wire width 8 \libresocsim_csrbank5_load3_w + attribute \src "ls180.v:1228.6-1228.35" + wire \libresocsim_csrbank5_load3_we + attribute \src "ls180.v:1255.12-1255.42" + wire width 8 \libresocsim_csrbank5_reload0_r + attribute \src "ls180.v:1254.6-1254.37" + wire \libresocsim_csrbank5_reload0_re + attribute \src "ls180.v:1257.12-1257.42" + wire width 8 \libresocsim_csrbank5_reload0_w + attribute \src "ls180.v:1256.6-1256.37" + wire \libresocsim_csrbank5_reload0_we + attribute \src "ls180.v:1251.12-1251.42" + wire width 8 \libresocsim_csrbank5_reload1_r + attribute \src "ls180.v:1250.6-1250.37" + wire \libresocsim_csrbank5_reload1_re + attribute \src "ls180.v:1253.12-1253.42" + wire width 8 \libresocsim_csrbank5_reload1_w + attribute \src "ls180.v:1252.6-1252.37" + wire \libresocsim_csrbank5_reload1_we + attribute \src "ls180.v:1247.12-1247.42" + wire width 8 \libresocsim_csrbank5_reload2_r + attribute \src "ls180.v:1246.6-1246.37" + wire \libresocsim_csrbank5_reload2_re + attribute \src "ls180.v:1249.12-1249.42" + wire width 8 \libresocsim_csrbank5_reload2_w + attribute \src "ls180.v:1248.6-1248.37" + wire \libresocsim_csrbank5_reload2_we + attribute \src "ls180.v:1243.12-1243.42" + wire width 8 \libresocsim_csrbank5_reload3_r + attribute \src "ls180.v:1242.6-1242.37" + wire \libresocsim_csrbank5_reload3_re + attribute \src "ls180.v:1245.12-1245.42" + wire width 8 \libresocsim_csrbank5_reload3_w + attribute \src "ls180.v:1244.6-1244.37" + wire \libresocsim_csrbank5_reload3_we + attribute \src "ls180.v:1286.6-1286.30" + wire \libresocsim_csrbank5_sel + attribute \src "ls180.v:1263.6-1263.42" + wire \libresocsim_csrbank5_update_value0_r + attribute \src "ls180.v:1262.6-1262.43" + wire \libresocsim_csrbank5_update_value0_re + attribute \src "ls180.v:1265.6-1265.42" + wire \libresocsim_csrbank5_update_value0_w + attribute \src "ls180.v:1264.6-1264.43" + wire \libresocsim_csrbank5_update_value0_we + attribute \src "ls180.v:1279.12-1279.41" + wire width 8 \libresocsim_csrbank5_value0_r + attribute \src "ls180.v:1278.6-1278.36" + wire \libresocsim_csrbank5_value0_re + attribute \src "ls180.v:1281.12-1281.41" + wire width 8 \libresocsim_csrbank5_value0_w + attribute \src "ls180.v:1280.6-1280.36" + wire \libresocsim_csrbank5_value0_we + attribute \src "ls180.v:1275.12-1275.41" + wire width 8 \libresocsim_csrbank5_value1_r + attribute \src "ls180.v:1274.6-1274.36" + wire \libresocsim_csrbank5_value1_re + attribute \src "ls180.v:1277.12-1277.41" + wire width 8 \libresocsim_csrbank5_value1_w + attribute \src "ls180.v:1276.6-1276.36" + wire \libresocsim_csrbank5_value1_we + attribute \src "ls180.v:1271.12-1271.41" + wire width 8 \libresocsim_csrbank5_value2_r + attribute \src "ls180.v:1270.6-1270.36" + wire \libresocsim_csrbank5_value2_re + attribute \src "ls180.v:1273.12-1273.41" + wire width 8 \libresocsim_csrbank5_value2_w + attribute \src "ls180.v:1272.6-1272.36" + wire \libresocsim_csrbank5_value2_we + attribute \src "ls180.v:1267.12-1267.41" + wire width 8 \libresocsim_csrbank5_value3_r + attribute \src "ls180.v:1266.6-1266.36" + wire \libresocsim_csrbank5_value3_re + attribute \src "ls180.v:1269.12-1269.41" + wire width 8 \libresocsim_csrbank5_value3_w + attribute \src "ls180.v:1268.6-1268.36" + wire \libresocsim_csrbank5_value3_we + attribute \src "ls180.v:1300.12-1300.45" + wire width 2 \libresocsim_csrbank6_ev_enable0_r + attribute \src "ls180.v:1299.6-1299.40" + wire \libresocsim_csrbank6_ev_enable0_re + attribute \src "ls180.v:1302.12-1302.45" + wire width 2 \libresocsim_csrbank6_ev_enable0_w + attribute \src "ls180.v:1301.6-1301.40" + wire \libresocsim_csrbank6_ev_enable0_we + attribute \src "ls180.v:1296.6-1296.36" + wire \libresocsim_csrbank6_rxempty_r + attribute \src "ls180.v:1295.6-1295.37" + wire \libresocsim_csrbank6_rxempty_re + attribute \src "ls180.v:1298.6-1298.36" + wire \libresocsim_csrbank6_rxempty_w + attribute \src "ls180.v:1297.6-1297.37" + wire \libresocsim_csrbank6_rxempty_we + attribute \src "ls180.v:1308.6-1308.35" + wire \libresocsim_csrbank6_rxfull_r + attribute \src "ls180.v:1307.6-1307.36" + wire \libresocsim_csrbank6_rxfull_re + attribute \src "ls180.v:1310.6-1310.35" + wire \libresocsim_csrbank6_rxfull_w + attribute \src "ls180.v:1309.6-1309.36" + wire \libresocsim_csrbank6_rxfull_we + attribute \src "ls180.v:1311.6-1311.30" + wire \libresocsim_csrbank6_sel + attribute \src "ls180.v:1304.6-1304.36" + wire \libresocsim_csrbank6_txempty_r + attribute \src "ls180.v:1303.6-1303.37" + wire \libresocsim_csrbank6_txempty_re + attribute \src "ls180.v:1306.6-1306.36" + wire \libresocsim_csrbank6_txempty_w + attribute \src "ls180.v:1305.6-1305.37" + wire \libresocsim_csrbank6_txempty_we + attribute \src "ls180.v:1292.6-1292.35" + wire \libresocsim_csrbank6_txfull_r + attribute \src "ls180.v:1291.6-1291.36" + wire \libresocsim_csrbank6_txfull_re + attribute \src "ls180.v:1294.6-1294.35" + wire \libresocsim_csrbank6_txfull_w + attribute \src "ls180.v:1293.6-1293.36" + wire \libresocsim_csrbank6_txfull_we + attribute \src "ls180.v:1332.6-1332.30" + wire \libresocsim_csrbank7_sel + attribute \src "ls180.v:1329.12-1329.47" + wire width 8 \libresocsim_csrbank7_tuning_word0_r + attribute \src "ls180.v:1328.6-1328.42" + wire \libresocsim_csrbank7_tuning_word0_re + attribute \src "ls180.v:1331.12-1331.47" + wire width 8 \libresocsim_csrbank7_tuning_word0_w + attribute \src "ls180.v:1330.6-1330.42" + wire \libresocsim_csrbank7_tuning_word0_we + attribute \src "ls180.v:1325.12-1325.47" + wire width 8 \libresocsim_csrbank7_tuning_word1_r + attribute \src "ls180.v:1324.6-1324.42" + wire \libresocsim_csrbank7_tuning_word1_re + attribute \src "ls180.v:1327.12-1327.47" + wire width 8 \libresocsim_csrbank7_tuning_word1_w + attribute \src "ls180.v:1326.6-1326.42" + wire \libresocsim_csrbank7_tuning_word1_we + attribute \src "ls180.v:1321.12-1321.47" + wire width 8 \libresocsim_csrbank7_tuning_word2_r + attribute \src "ls180.v:1320.6-1320.42" + wire \libresocsim_csrbank7_tuning_word2_re + attribute \src "ls180.v:1323.12-1323.47" + wire width 8 \libresocsim_csrbank7_tuning_word2_w + attribute \src "ls180.v:1322.6-1322.42" + wire \libresocsim_csrbank7_tuning_word2_we + attribute \src "ls180.v:1317.12-1317.47" + wire width 8 \libresocsim_csrbank7_tuning_word3_r + attribute \src "ls180.v:1316.6-1316.42" + wire \libresocsim_csrbank7_tuning_word3_re + attribute \src "ls180.v:1319.12-1319.47" + wire width 8 \libresocsim_csrbank7_tuning_word3_w + attribute \src "ls180.v:1318.6-1318.42" + wire \libresocsim_csrbank7_tuning_word3_we + attribute \src "ls180.v:153.13-153.30" + wire width 64 \libresocsim_dat_r + attribute \src "ls180.v:155.13-155.30" + wire width 64 \libresocsim_dat_w + attribute \src "ls180.v:1091.6-1091.22" + wire \libresocsim_done + attribute \src "ls180.v:161.5-161.22" + wire \libresocsim_en_re + attribute \src "ls180.v:160.5-160.27" + wire \libresocsim_en_storage + attribute \src "ls180.v:1089.5-1089.22" + wire \libresocsim_error + attribute \src "ls180.v:177.6-177.40" + wire \libresocsim_eventmanager_pending_r + attribute \src "ls180.v:176.6-176.41" + wire \libresocsim_eventmanager_pending_re + attribute \src "ls180.v:179.6-179.40" + wire \libresocsim_eventmanager_pending_w + attribute \src "ls180.v:178.6-178.41" + wire \libresocsim_eventmanager_pending_we + attribute \src "ls180.v:181.5-181.32" + wire \libresocsim_eventmanager_re + attribute \src "ls180.v:173.6-173.39" + wire \libresocsim_eventmanager_status_r + attribute \src "ls180.v:172.6-172.40" + wire \libresocsim_eventmanager_status_re + attribute \src "ls180.v:175.6-175.39" + wire \libresocsim_eventmanager_status_w + attribute \src "ls180.v:174.6-174.40" + wire \libresocsim_eventmanager_status_we + attribute \src "ls180.v:180.5-180.37" + wire \libresocsim_eventmanager_storage + attribute \src "ls180.v:1086.11-1086.28" + wire width 2 \libresocsim_grant + attribute \src "ls180.v:1093.13-1093.48" + wire width 14 \libresocsim_interface0_bank_bus_adr + attribute \src "ls180.v:1096.11-1096.48" + wire width 8 \libresocsim_interface0_bank_bus_dat_r + attribute \src "ls180.v:1095.12-1095.49" + wire width 8 \libresocsim_interface0_bank_bus_dat_w + attribute \src "ls180.v:1094.6-1094.40" + wire \libresocsim_interface0_bank_bus_we + attribute \src "ls180.v:1134.13-1134.48" + wire width 14 \libresocsim_interface1_bank_bus_adr + attribute \src "ls180.v:1137.11-1137.48" + wire width 8 \libresocsim_interface1_bank_bus_dat_r + attribute \src "ls180.v:1136.12-1136.49" + wire width 8 \libresocsim_interface1_bank_bus_dat_w + attribute \src "ls180.v:1135.6-1135.40" + wire \libresocsim_interface1_bank_bus_we + attribute \src "ls180.v:1151.13-1151.48" + wire width 14 \libresocsim_interface2_bank_bus_adr + attribute \src "ls180.v:1154.11-1154.48" + wire width 8 \libresocsim_interface2_bank_bus_dat_r + attribute \src "ls180.v:1153.12-1153.49" + wire width 8 \libresocsim_interface2_bank_bus_dat_w + attribute \src "ls180.v:1152.6-1152.40" + wire \libresocsim_interface2_bank_bus_we + attribute \src "ls180.v:1168.13-1168.48" + wire width 14 \libresocsim_interface3_bank_bus_adr + attribute \src "ls180.v:1171.11-1171.48" + wire width 8 \libresocsim_interface3_bank_bus_dat_r + attribute \src "ls180.v:1170.12-1170.49" + wire width 8 \libresocsim_interface3_bank_bus_dat_w + attribute \src "ls180.v:1169.6-1169.40" + wire \libresocsim_interface3_bank_bus_we + attribute \src "ls180.v:1181.13-1181.48" + wire width 14 \libresocsim_interface4_bank_bus_adr + attribute \src "ls180.v:1184.11-1184.48" + wire width 8 \libresocsim_interface4_bank_bus_dat_r + attribute \src "ls180.v:1183.12-1183.49" + wire width 8 \libresocsim_interface4_bank_bus_dat_w + attribute \src "ls180.v:1182.6-1182.40" + wire \libresocsim_interface4_bank_bus_we + attribute \src "ls180.v:1222.13-1222.48" + wire width 14 \libresocsim_interface5_bank_bus_adr + attribute \src "ls180.v:1225.11-1225.48" + wire width 8 \libresocsim_interface5_bank_bus_dat_r + attribute \src "ls180.v:1224.12-1224.49" + wire width 8 \libresocsim_interface5_bank_bus_dat_w + attribute \src "ls180.v:1223.6-1223.40" + wire \libresocsim_interface5_bank_bus_we + attribute \src "ls180.v:1287.13-1287.48" + wire width 14 \libresocsim_interface6_bank_bus_adr + attribute \src "ls180.v:1290.11-1290.48" + wire width 8 \libresocsim_interface6_bank_bus_dat_r + attribute \src "ls180.v:1289.12-1289.49" + wire width 8 \libresocsim_interface6_bank_bus_dat_w + attribute \src "ls180.v:1288.6-1288.40" + wire \libresocsim_interface6_bank_bus_we + attribute \src "ls180.v:1312.13-1312.48" + wire width 14 \libresocsim_interface7_bank_bus_adr + attribute \src "ls180.v:1315.11-1315.48" + wire width 8 \libresocsim_interface7_bank_bus_dat_r + attribute \src "ls180.v:1314.12-1314.49" + wire width 8 \libresocsim_interface7_bank_bus_dat_w + attribute \src "ls180.v:1313.6-1313.40" + wire \libresocsim_interface7_bank_bus_we + attribute \src "ls180.v:166.6-166.21" + wire \libresocsim_irq + attribute \src "ls180.v:109.6-109.27" + wire \libresocsim_libresoc0 + attribute \src "ls180.v:110.6-110.27" + wire \libresocsim_libresoc1 + attribute \src "ls180.v:111.13-111.34" + wire width 64 \libresocsim_libresoc2 + attribute \src "ls180.v:113.12-113.40" + wire width 2 \libresocsim_libresoc_clk_sel + attribute \src "ls180.v:115.13-115.62" + wire width 16 \libresocsim_libresoc_constraintmanager_obj_gpio_i + attribute \src "ls180.v:116.12-116.61" + wire width 16 \libresocsim_libresoc_constraintmanager_obj_gpio_o + attribute \src "ls180.v:117.12-117.62" + wire width 16 \libresocsim_libresoc_constraintmanager_obj_gpio_oe + attribute \src "ls180.v:137.6-137.56" + wire \libresocsim_libresoc_constraintmanager_obj_i2c_scl + attribute \src "ls180.v:138.6-138.58" + wire \libresocsim_libresoc_constraintmanager_obj_i2c_sda_i + attribute \src "ls180.v:139.6-139.58" + wire \libresocsim_libresoc_constraintmanager_obj_i2c_sda_o + attribute \src "ls180.v:140.6-140.59" + wire \libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe + attribute \src "ls180.v:125.12-125.62" + wire width 13 \libresocsim_libresoc_constraintmanager_obj_sdram_a + attribute \src "ls180.v:134.11-134.62" + wire width 2 \libresocsim_libresoc_constraintmanager_obj_sdram_ba + attribute \src "ls180.v:131.5-131.59" + wire \libresocsim_libresoc_constraintmanager_obj_sdram_cas_n + attribute \src "ls180.v:133.5-133.57" + wire \libresocsim_libresoc_constraintmanager_obj_sdram_cke + attribute \src "ls180.v:132.5-132.58" + wire \libresocsim_libresoc_constraintmanager_obj_sdram_cs_n + attribute \src "ls180.v:135.11-135.62" + wire width 2 \libresocsim_libresoc_constraintmanager_obj_sdram_dm + attribute \src "ls180.v:126.13-126.66" + wire width 16 \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i + attribute \src "ls180.v:127.12-127.65" + wire width 16 \libresocsim_libresoc_constraintmanager_obj_sdram_dq_o + attribute \src "ls180.v:128.5-128.59" + wire \libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + attribute \src "ls180.v:130.5-130.59" + wire \libresocsim_libresoc_constraintmanager_obj_sdram_ras_n + attribute \src "ls180.v:129.5-129.58" + wire \libresocsim_libresoc_constraintmanager_obj_sdram_we_n + attribute \src "ls180.v:118.5-118.61" + wire \libresocsim_libresoc_constraintmanager_obj_spimaster_clk + attribute \src "ls180.v:120.5-120.62" + wire \libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n + attribute \src "ls180.v:121.6-121.63" + wire \libresocsim_libresoc_constraintmanager_obj_spimaster_miso + attribute \src "ls180.v:119.5-119.62" + wire \libresocsim_libresoc_constraintmanager_obj_spimaster_mosi + attribute \src "ls180.v:123.5-123.55" + wire \libresocsim_libresoc_constraintmanager_obj_uart_rx + attribute \src "ls180.v:122.5-122.55" + wire \libresocsim_libresoc_constraintmanager_obj_uart_tx + attribute \src "ls180.v:60.6-60.35" + wire \libresocsim_libresoc_dbus_ack + attribute \src "ls180.v:54.13-54.42" + wire width 29 \libresocsim_libresoc_dbus_adr + attribute \src "ls180.v:63.11-63.40" + wire width 2 \libresocsim_libresoc_dbus_bte + attribute \src "ls180.v:62.11-62.40" + wire width 3 \libresocsim_libresoc_dbus_cti + attribute \src "ls180.v:58.6-58.35" + wire \libresocsim_libresoc_dbus_cyc + attribute \src "ls180.v:56.13-56.44" + wire width 64 \libresocsim_libresoc_dbus_dat_r + attribute \src "ls180.v:55.13-55.44" + wire width 64 \libresocsim_libresoc_dbus_dat_w + attribute \src "ls180.v:64.6-64.35" + wire \libresocsim_libresoc_dbus_err + attribute \src "ls180.v:57.12-57.41" + wire width 8 \libresocsim_libresoc_dbus_sel + attribute \src "ls180.v:59.6-59.35" + wire \libresocsim_libresoc_dbus_stb + attribute \src "ls180.v:61.6-61.34" + wire \libresocsim_libresoc_dbus_we + attribute \src "ls180.v:71.6-71.35" + wire \libresocsim_libresoc_ibus_ack + attribute \src "ls180.v:65.13-65.42" + wire width 29 \libresocsim_libresoc_ibus_adr + attribute \src "ls180.v:74.11-74.40" + wire width 2 \libresocsim_libresoc_ibus_bte + attribute \src "ls180.v:73.11-73.40" + wire width 3 \libresocsim_libresoc_ibus_cti + attribute \src "ls180.v:69.6-69.35" + wire \libresocsim_libresoc_ibus_cyc + attribute \src "ls180.v:67.13-67.44" + wire width 64 \libresocsim_libresoc_ibus_dat_r + attribute \src "ls180.v:66.13-66.44" + wire width 64 \libresocsim_libresoc_ibus_dat_w + attribute \src "ls180.v:75.6-75.35" + wire \libresocsim_libresoc_ibus_err + attribute \src "ls180.v:68.12-68.41" + wire width 8 \libresocsim_libresoc_ibus_sel + attribute \src "ls180.v:70.6-70.35" + wire \libresocsim_libresoc_ibus_stb + attribute \src "ls180.v:72.6-72.34" + wire \libresocsim_libresoc_ibus_we + attribute \src "ls180.v:53.12-53.42" + wire width 16 \libresocsim_libresoc_interrupt + attribute \src "ls180.v:105.6-105.35" + wire \libresocsim_libresoc_jtag_tck + attribute \src "ls180.v:107.6-107.35" + wire \libresocsim_libresoc_jtag_tdi + attribute \src "ls180.v:108.6-108.35" + wire \libresocsim_libresoc_jtag_tdo + attribute \src "ls180.v:106.6-106.35" + wire \libresocsim_libresoc_jtag_tms + attribute \src "ls180.v:100.6-100.38" + wire \libresocsim_libresoc_jtag_wb_ack + attribute \src "ls180.v:94.13-94.45" + wire width 29 \libresocsim_libresoc_jtag_wb_adr + attribute \src "ls180.v:103.11-103.43" + wire width 2 \libresocsim_libresoc_jtag_wb_bte + attribute \src "ls180.v:102.11-102.43" + wire width 3 \libresocsim_libresoc_jtag_wb_cti + attribute \src "ls180.v:98.6-98.38" + wire \libresocsim_libresoc_jtag_wb_cyc + attribute \src "ls180.v:96.13-96.47" + wire width 64 \libresocsim_libresoc_jtag_wb_dat_r + attribute \src "ls180.v:95.13-95.47" + wire width 64 \libresocsim_libresoc_jtag_wb_dat_w + attribute \src "ls180.v:104.6-104.38" + wire \libresocsim_libresoc_jtag_wb_err + attribute \src "ls180.v:97.12-97.44" + wire width 8 \libresocsim_libresoc_jtag_wb_sel + attribute \src "ls180.v:99.6-99.38" + wire \libresocsim_libresoc_jtag_wb_stb + attribute \src "ls180.v:101.6-101.37" + wire \libresocsim_libresoc_jtag_wb_we + attribute \src "ls180.v:112.6-112.35" + wire \libresocsim_libresoc_pll_18_o + attribute \src "ls180.v:114.6-114.36" + wire \libresocsim_libresoc_pll_lck_o + attribute \src "ls180.v:52.6-52.32" + wire \libresocsim_libresoc_reset + attribute \src "ls180.v:82.6-82.39" + wire \libresocsim_libresoc_xics_icp_ack + attribute \src "ls180.v:76.12-76.45" + wire width 30 \libresocsim_libresoc_xics_icp_adr + attribute \src "ls180.v:80.5-80.38" + wire \libresocsim_libresoc_xics_icp_cyc + attribute \src "ls180.v:78.13-78.48" + wire width 32 \libresocsim_libresoc_xics_icp_dat_r + attribute \src "ls180.v:77.12-77.47" + wire width 32 \libresocsim_libresoc_xics_icp_dat_w + attribute \src "ls180.v:84.6-84.39" + wire \libresocsim_libresoc_xics_icp_err + attribute \src "ls180.v:79.11-79.44" + wire width 4 \libresocsim_libresoc_xics_icp_sel + attribute \src "ls180.v:81.5-81.38" + wire \libresocsim_libresoc_xics_icp_stb + attribute \src "ls180.v:83.5-83.37" + wire \libresocsim_libresoc_xics_icp_we + attribute \src "ls180.v:91.6-91.39" + wire \libresocsim_libresoc_xics_ics_ack + attribute \src "ls180.v:85.12-85.45" + wire width 30 \libresocsim_libresoc_xics_ics_adr + attribute \src "ls180.v:89.5-89.38" + wire \libresocsim_libresoc_xics_ics_cyc + attribute \src "ls180.v:87.13-87.48" + wire width 32 \libresocsim_libresoc_xics_ics_dat_r + attribute \src "ls180.v:86.12-86.47" + wire width 32 \libresocsim_libresoc_xics_ics_dat_w + attribute \src "ls180.v:93.6-93.39" + wire \libresocsim_libresoc_xics_ics_err + attribute \src "ls180.v:88.11-88.44" + wire width 4 \libresocsim_libresoc_xics_ics_sel + attribute \src "ls180.v:90.5-90.38" + wire \libresocsim_libresoc_xics_ics_stb + attribute \src "ls180.v:92.5-92.37" + wire \libresocsim_libresoc_xics_ics_we + attribute \src "ls180.v:1051.12-1051.39" + wire width 14 \libresocsim_libresocsim_adr + attribute \src "ls180.v:1341.12-1341.63" + wire width 14 \libresocsim_libresocsim_adr_libresocsim_next_value1 + attribute \src "ls180.v:1342.5-1342.59" + wire \libresocsim_libresocsim_adr_libresocsim_next_value_ce1 + attribute \src "ls180.v:1069.5-1069.52" + wire \libresocsim_libresocsim_converted_interface_ack + attribute \src "ls180.v:1063.13-1063.60" + wire width 30 \libresocsim_libresocsim_converted_interface_adr + attribute \src "ls180.v:1072.12-1072.59" + wire width 2 \libresocsim_libresocsim_converted_interface_bte + attribute \src "ls180.v:1071.12-1071.59" + wire width 3 \libresocsim_libresocsim_converted_interface_cti + attribute \src "ls180.v:1067.6-1067.53" + wire \libresocsim_libresocsim_converted_interface_cyc + attribute \src "ls180.v:1065.12-1065.61" + wire width 64 \libresocsim_libresocsim_converted_interface_dat_r + attribute \src "ls180.v:1064.13-1064.62" + wire width 64 \libresocsim_libresocsim_converted_interface_dat_w + attribute \src "ls180.v:1073.5-1073.52" + wire \libresocsim_libresocsim_converted_interface_err + attribute \src "ls180.v:1066.12-1066.59" + wire width 8 \libresocsim_libresocsim_converted_interface_sel + attribute \src "ls180.v:1068.6-1068.53" + wire \libresocsim_libresocsim_converted_interface_stb + attribute \src "ls180.v:1070.6-1070.52" + wire \libresocsim_libresocsim_converted_interface_we + attribute \src "ls180.v:1054.12-1054.41" + wire width 8 \libresocsim_libresocsim_dat_r + attribute \src "ls180.v:1053.11-1053.40" + wire width 8 \libresocsim_libresocsim_dat_w + attribute \src "ls180.v:1339.11-1339.64" + wire width 8 \libresocsim_libresocsim_dat_w_libresocsim_next_value0 + attribute \src "ls180.v:1340.5-1340.61" + wire \libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0 + attribute \src "ls180.v:1052.5-1052.31" + wire \libresocsim_libresocsim_we + attribute \src "ls180.v:1343.5-1343.55" + wire \libresocsim_libresocsim_we_libresocsim_next_value2 + attribute \src "ls180.v:1344.5-1344.58" + wire \libresocsim_libresocsim_we_libresocsim_next_value_ce2 + attribute \src "ls180.v:1061.5-1061.41" + wire \libresocsim_libresocsim_wishbone_ack + attribute \src "ls180.v:1055.12-1055.48" + wire width 30 \libresocsim_libresocsim_wishbone_adr + attribute \src "ls180.v:1059.5-1059.41" + wire \libresocsim_libresocsim_wishbone_cyc + attribute \src "ls180.v:1057.12-1057.50" + wire width 32 \libresocsim_libresocsim_wishbone_dat_r + attribute \src "ls180.v:1056.12-1056.50" + wire width 32 \libresocsim_libresocsim_wishbone_dat_w + attribute \src "ls180.v:1058.11-1058.47" + wire width 4 \libresocsim_libresocsim_wishbone_sel + attribute \src "ls180.v:1060.5-1060.41" + wire \libresocsim_libresocsim_wishbone_stb + attribute \src "ls180.v:1062.5-1062.40" + wire \libresocsim_libresocsim_wishbone_we + attribute \src "ls180.v:157.5-157.24" + wire \libresocsim_load_re + attribute \src "ls180.v:156.12-156.36" + wire width 32 \libresocsim_load_storage + attribute \src "ls180.v:1338.11-1338.33" + wire width 2 \libresocsim_next_state + attribute \src "ls180.v:147.5-147.28" + wire \libresocsim_ram_bus_ack + attribute \src "ls180.v:141.13-141.36" + wire width 30 \libresocsim_ram_bus_adr + attribute \src "ls180.v:150.12-150.35" + wire width 2 \libresocsim_ram_bus_bte + attribute \src "ls180.v:149.12-149.35" + wire width 3 \libresocsim_ram_bus_cti + attribute \src "ls180.v:145.6-145.29" + wire \libresocsim_ram_bus_cyc + attribute \src "ls180.v:143.13-143.38" + wire width 64 \libresocsim_ram_bus_dat_r + attribute \src "ls180.v:142.13-142.38" + wire width 64 \libresocsim_ram_bus_dat_w + attribute \src "ls180.v:151.5-151.28" + wire \libresocsim_ram_bus_err + attribute \src "ls180.v:144.12-144.35" + wire width 8 \libresocsim_ram_bus_sel + attribute \src "ls180.v:146.6-146.29" + wire \libresocsim_ram_bus_stb + attribute \src "ls180.v:148.6-148.28" + wire \libresocsim_ram_bus_we + attribute \src "ls180.v:159.5-159.26" + wire \libresocsim_reload_re + attribute \src "ls180.v:158.12-158.38" + wire width 32 \libresocsim_reload_storage + attribute \src "ls180.v:1085.12-1085.31" + wire width 3 \libresocsim_request + attribute \src "ls180.v:49.6-49.23" + wire \libresocsim_reset + attribute \src "ls180.v:44.5-44.25" + wire \libresocsim_reset_re + attribute \src "ls180.v:43.5-43.30" + wire \libresocsim_reset_storage + attribute \src "ls180.v:46.5-46.27" + wire \libresocsim_scratch_re + attribute \src "ls180.v:45.12-45.39" + wire width 32 \libresocsim_scratch_storage + attribute \src "ls180.v:1080.5-1080.27" + wire \libresocsim_shared_ack + attribute \src "ls180.v:1074.13-1074.35" + wire width 30 \libresocsim_shared_adr + attribute \src "ls180.v:1083.12-1083.34" + wire width 2 \libresocsim_shared_bte + attribute \src "ls180.v:1082.12-1082.34" + wire width 3 \libresocsim_shared_cti + attribute \src "ls180.v:1078.6-1078.28" + wire \libresocsim_shared_cyc + attribute \src "ls180.v:1076.12-1076.36" + wire width 32 \libresocsim_shared_dat_r + attribute \src "ls180.v:1075.13-1075.37" + wire width 32 \libresocsim_shared_dat_w + attribute \src "ls180.v:1084.6-1084.28" + wire \libresocsim_shared_err + attribute \src "ls180.v:1077.12-1077.34" + wire width 4 \libresocsim_shared_sel + attribute \src "ls180.v:1079.6-1079.28" + wire \libresocsim_shared_stb + attribute \src "ls180.v:1081.6-1081.27" + wire \libresocsim_shared_we + attribute \src "ls180.v:1087.11-1087.32" + wire width 6 \libresocsim_slave_sel + attribute \src "ls180.v:1088.11-1088.34" + wire width 6 \libresocsim_slave_sel_r + attribute \src "ls180.v:1337.11-1337.28" + wire width 2 \libresocsim_state + attribute \src "ls180.v:163.5-163.32" + wire \libresocsim_update_value_re + attribute \src "ls180.v:162.5-162.37" + wire \libresocsim_update_value_storage + attribute \src "ls180.v:182.12-182.29" + wire width 32 \libresocsim_value + attribute \src "ls180.v:164.12-164.36" + wire width 32 \libresocsim_value_status + attribute \src "ls180.v:165.6-165.26" + wire \libresocsim_value_we + attribute \src "ls180.v:1090.6-1090.22" + wire \libresocsim_wait + attribute \src "ls180.v:154.11-154.25" + wire width 8 \libresocsim_we + attribute \src "ls180.v:170.5-170.27" + wire \libresocsim_zero_clear + attribute \src "ls180.v:171.5-171.33" + wire \libresocsim_zero_old_trigger + attribute \src "ls180.v:168.5-168.29" + wire \libresocsim_zero_pending + attribute \src "ls180.v:167.6-167.29" + wire \libresocsim_zero_status + attribute \src "ls180.v:169.6-169.30" + wire \libresocsim_zero_trigger + attribute \src "ls180.v:821.6-821.21" + wire \litedram_wb_ack + attribute \src "ls180.v:815.12-815.27" + wire width 30 \litedram_wb_adr + attribute \src "ls180.v:819.5-819.20" + wire \litedram_wb_cyc + attribute \src "ls180.v:817.13-817.30" + wire width 16 \litedram_wb_dat_r + attribute \src "ls180.v:816.12-816.29" + wire width 16 \litedram_wb_dat_w + attribute \src "ls180.v:818.11-818.26" + wire width 2 \litedram_wb_sel + attribute \src "ls180.v:820.5-820.20" + wire \litedram_wb_stb + attribute \src "ls180.v:822.5-822.19" + wire \litedram_wb_we + attribute \src "ls180.v:5490.11-5490.17" + wire width 6 \memadr + attribute \src "ls180.v:5518.11-5518.19" + wire width 4 \memadr_1 + attribute \src "ls180.v:5546.12-5546.18" + wire width 25 \memdat + attribute \src "ls180.v:5560.12-5560.20" + wire width 25 \memdat_1 + attribute \src "ls180.v:5574.12-5574.20" + wire width 25 \memdat_2 + attribute \src "ls180.v:5588.12-5588.20" + wire width 25 \memdat_3 + attribute \src "ls180.v:5602.11-5602.19" + wire width 10 \memdat_4 + attribute \src "ls180.v:5603.11-5603.19" + wire width 10 \memdat_5 + attribute \src "ls180.v:5619.11-5619.19" + wire width 10 \memdat_6 + attribute \src "ls180.v:5620.11-5620.19" + wire width 10 \memdat_7 + attribute \src "ls180.v:40.20-40.22" + wire width 30 input 36 \nc + attribute \src "ls180.v:992.13-992.17" + wire width 30 \nc_1 + attribute \src "ls180.v:230.6-230.13" + wire \por_clk + attribute \src "ls180.v:782.6-782.19" + wire \port_cmd_last + attribute \src "ls180.v:784.13-784.34" + wire width 24 \port_cmd_payload_addr + attribute \src "ls180.v:783.6-783.25" + wire \port_cmd_payload_we + attribute \src "ls180.v:781.6-781.20" + wire \port_cmd_ready + attribute \src "ls180.v:780.6-780.20" + wire \port_cmd_valid + attribute \src "ls180.v:779.6-779.16" + wire \port_flush + attribute \src "ls180.v:791.13-791.36" + wire width 16 \port_rdata_payload_data + attribute \src "ls180.v:790.6-790.22" + wire \port_rdata_ready + attribute \src "ls180.v:789.6-789.22" + wire \port_rdata_valid + attribute \src "ls180.v:787.13-787.36" + wire width 16 \port_wdata_payload_data + attribute \src "ls180.v:788.12-788.33" + wire width 2 \port_wdata_payload_we + attribute \src "ls180.v:786.6-786.22" + wire \port_wdata_ready + attribute \src "ls180.v:785.6-785.22" + wire \port_wdata_valid + attribute \src "ls180.v:194.12-194.19" + wire width 4 \ram_adr + attribute \src "ls180.v:189.5-189.24" + wire \ram_bus_ram_bus_ack + attribute \src "ls180.v:183.13-183.32" + wire width 30 \ram_bus_ram_bus_adr + attribute \src "ls180.v:192.12-192.31" + wire width 2 \ram_bus_ram_bus_bte + attribute \src "ls180.v:191.12-191.31" + wire width 3 \ram_bus_ram_bus_cti + attribute \src "ls180.v:187.6-187.25" + wire \ram_bus_ram_bus_cyc + attribute \src "ls180.v:185.13-185.34" + wire width 64 \ram_bus_ram_bus_dat_r + attribute \src "ls180.v:184.13-184.34" + wire width 64 \ram_bus_ram_bus_dat_w + attribute \src "ls180.v:193.5-193.24" + wire \ram_bus_ram_bus_err + attribute \src "ls180.v:186.12-186.31" + wire width 8 \ram_bus_ram_bus_sel + attribute \src "ls180.v:188.6-188.25" + wire \ram_bus_ram_bus_stb + attribute \src "ls180.v:190.6-190.24" + wire \ram_bus_ram_bus_we + attribute \src "ls180.v:195.13-195.22" + wire width 64 \ram_dat_r + attribute \src "ls180.v:197.13-197.22" + wire width 64 \ram_dat_w + attribute \src "ls180.v:196.11-196.17" + wire width 8 \ram_we + attribute \src "ls180.v:248.11-248.20" + wire width 3 \rddata_en attribute \no_retiming "true" - attribute \src "ls180.v:492.32-492.69" - wire \main_sdram_bankmachine0_trascon_ready - attribute \src "ls180.v:491.6-491.43" - wire \main_sdram_bankmachine0_trascon_valid + attribute \src "ls180.v:1446.32-1446.37" + wire \regs0 attribute \no_retiming "true" - attribute \src "ls180.v:490.32-490.68" - wire \main_sdram_bankmachine0_trccon_ready - attribute \src "ls180.v:489.6-489.42" - wire \main_sdram_bankmachine0_trccon_valid - attribute \src "ls180.v:488.11-488.48" - wire width 3 \main_sdram_bankmachine0_twtpcon_count + attribute \src "ls180.v:1447.32-1447.37" + wire \regs1 + attribute \src "ls180.v:973.5-973.10" + wire \reset + attribute \src "ls180.v:1345.5-1345.21" + wire \rhs_array_muxed0 + attribute \src "ls180.v:1346.12-1346.28" + wire width 13 \rhs_array_muxed1 + attribute \src "ls180.v:1358.5-1358.22" + wire \rhs_array_muxed10 + attribute \src "ls180.v:1359.5-1359.22" + wire \rhs_array_muxed11 + attribute \src "ls180.v:1363.12-1363.29" + wire width 22 \rhs_array_muxed12 + attribute \src "ls180.v:1364.5-1364.22" + wire \rhs_array_muxed13 + attribute \src "ls180.v:1365.5-1365.22" + wire \rhs_array_muxed14 + attribute \src "ls180.v:1366.12-1366.29" + wire width 22 \rhs_array_muxed15 + attribute \src "ls180.v:1367.5-1367.22" + wire \rhs_array_muxed16 + attribute \src "ls180.v:1368.5-1368.22" + wire \rhs_array_muxed17 + attribute \src "ls180.v:1369.12-1369.29" + wire width 22 \rhs_array_muxed18 + attribute \src "ls180.v:1370.5-1370.22" + wire \rhs_array_muxed19 + attribute \src "ls180.v:1347.11-1347.27" + wire width 2 \rhs_array_muxed2 + attribute \src "ls180.v:1371.5-1371.22" + wire \rhs_array_muxed20 + attribute \src "ls180.v:1372.12-1372.29" + wire width 22 \rhs_array_muxed21 + attribute \src "ls180.v:1373.5-1373.22" + wire \rhs_array_muxed22 + attribute \src "ls180.v:1374.5-1374.22" + wire \rhs_array_muxed23 + attribute \src "ls180.v:1375.12-1375.29" + wire width 29 \rhs_array_muxed24 + attribute \src "ls180.v:1376.12-1376.29" + wire width 64 \rhs_array_muxed25 + attribute \src "ls180.v:1377.11-1377.28" + wire width 8 \rhs_array_muxed26 + attribute \src "ls180.v:1378.5-1378.22" + wire \rhs_array_muxed27 + attribute \src "ls180.v:1379.5-1379.22" + wire \rhs_array_muxed28 + attribute \src "ls180.v:1380.5-1380.22" + wire \rhs_array_muxed29 + attribute \src "ls180.v:1348.5-1348.21" + wire \rhs_array_muxed3 + attribute \src "ls180.v:1381.11-1381.28" + wire width 3 \rhs_array_muxed30 + attribute \src "ls180.v:1382.11-1382.28" + wire width 2 \rhs_array_muxed31 + attribute \src "ls180.v:1349.5-1349.21" + wire \rhs_array_muxed4 + attribute \src "ls180.v:1350.5-1350.21" + wire \rhs_array_muxed5 + attribute \src "ls180.v:1354.5-1354.21" + wire \rhs_array_muxed6 + attribute \src "ls180.v:1355.12-1355.28" + wire width 13 \rhs_array_muxed7 + attribute \src "ls180.v:1356.11-1356.27" + wire width 2 \rhs_array_muxed8 + attribute \src "ls180.v:1357.5-1357.21" + wire \rhs_array_muxed9 + attribute \src "ls180.v:873.5-873.13" + wire \rx_clear + attribute \src "ls180.v:957.11-957.26" + wire width 4 \rx_fifo_consume + attribute \src "ls180.v:962.6-962.21" + wire \rx_fifo_do_read + attribute \src "ls180.v:968.6-968.27" + wire \rx_fifo_fifo_in_first + attribute \src "ls180.v:969.6-969.26" + wire \rx_fifo_fifo_in_last + attribute \src "ls180.v:967.12-967.40" + wire width 8 \rx_fifo_fifo_in_payload_data + attribute \src "ls180.v:971.6-971.28" + wire \rx_fifo_fifo_out_first + attribute \src "ls180.v:972.6-972.27" + wire \rx_fifo_fifo_out_last + attribute \src "ls180.v:970.12-970.41" + wire width 8 \rx_fifo_fifo_out_payload_data + attribute \src "ls180.v:954.11-954.25" + wire width 5 \rx_fifo_level0 + attribute \src "ls180.v:966.12-966.26" + wire width 5 \rx_fifo_level1 + attribute \src "ls180.v:956.11-956.26" + wire width 4 \rx_fifo_produce + attribute \src "ls180.v:963.12-963.30" + wire width 4 \rx_fifo_rdport_adr + attribute \src "ls180.v:964.12-964.32" + wire width 10 \rx_fifo_rdport_dat_r + attribute \src "ls180.v:965.6-965.23" + wire \rx_fifo_rdport_re + attribute \src "ls180.v:946.6-946.16" + wire \rx_fifo_re + attribute \src "ls180.v:947.5-947.21" + wire \rx_fifo_readable + attribute \src "ls180.v:955.5-955.20" + wire \rx_fifo_replace + attribute \src "ls180.v:938.6-938.24" + wire \rx_fifo_sink_first + attribute \src "ls180.v:939.6-939.23" + wire \rx_fifo_sink_last + attribute \src "ls180.v:940.12-940.37" + wire width 8 \rx_fifo_sink_payload_data + attribute \src "ls180.v:937.6-937.24" + wire \rx_fifo_sink_ready + attribute \src "ls180.v:936.6-936.24" + wire \rx_fifo_sink_valid + attribute \src "ls180.v:943.6-943.26" + wire \rx_fifo_source_first + attribute \src "ls180.v:944.6-944.25" + wire \rx_fifo_source_last + attribute \src "ls180.v:945.12-945.39" + wire width 8 \rx_fifo_source_payload_data + attribute \src "ls180.v:942.6-942.26" + wire \rx_fifo_source_ready + attribute \src "ls180.v:941.6-941.26" + wire \rx_fifo_source_valid + attribute \src "ls180.v:952.12-952.32" + wire width 10 \rx_fifo_syncfifo_din + attribute \src "ls180.v:953.12-953.33" + wire width 10 \rx_fifo_syncfifo_dout + attribute \src "ls180.v:950.6-950.25" + wire \rx_fifo_syncfifo_re + attribute \src "ls180.v:951.6-951.31" + wire \rx_fifo_syncfifo_readable + attribute \src "ls180.v:948.6-948.25" + wire \rx_fifo_syncfifo_we + attribute \src "ls180.v:949.6-949.31" + wire \rx_fifo_syncfifo_writable + attribute \src "ls180.v:958.11-958.29" + wire width 4 \rx_fifo_wrport_adr + attribute \src "ls180.v:959.12-959.32" + wire width 10 \rx_fifo_wrport_dat_r + attribute \src "ls180.v:961.12-961.32" + wire width 10 \rx_fifo_wrport_dat_w + attribute \src "ls180.v:960.6-960.23" + wire \rx_fifo_wrport_we + attribute \src "ls180.v:874.5-874.19" + wire \rx_old_trigger + attribute \src "ls180.v:871.5-871.15" + wire \rx_pending + attribute \src "ls180.v:870.6-870.15" + wire \rx_status + attribute \src "ls180.v:872.6-872.16" + wire \rx_trigger + attribute \src "ls180.v:862.6-862.20" + wire \rxempty_status + attribute \src "ls180.v:863.6-863.16" + wire \rxempty_we + attribute \src "ls180.v:887.6-887.19" + wire \rxfull_status + attribute \src "ls180.v:888.6-888.15" + wire \rxfull_we + attribute \src "ls180.v:857.12-857.18" + wire width 8 \rxtx_r + attribute \src "ls180.v:856.6-856.13" + wire \rxtx_re + attribute \src "ls180.v:859.12-859.18" + wire width 8 \rxtx_w + attribute \src "ls180.v:858.6-858.13" + wire \rxtx_we + attribute \src "ls180.v:15.21-15.28" + wire width 13 output 11 \sdram_a + attribute \src "ls180.v:310.5-310.21" + wire \sdram_address_re + attribute \src "ls180.v:309.12-309.33" + wire width 13 \sdram_address_storage + attribute \src "ls180.v:24.20-24.28" + wire width 2 output 20 \sdram_ba + attribute \src "ls180.v:312.5-312.22" + wire \sdram_baddress_re + attribute \src "ls180.v:311.11-311.33" + wire width 2 \sdram_baddress_storage + attribute \src "ls180.v:408.5-408.38" + wire \sdram_bankmachine0_auto_precharge + attribute \src "ls180.v:430.11-430.58" + wire width 3 \sdram_bankmachine0_cmd_buffer_lookahead_consume + attribute \src "ls180.v:435.6-435.53" + wire \sdram_bankmachine0_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:440.6-440.59" + wire \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first + attribute \src "ls180.v:441.6-441.58" + wire \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last + attribute \src "ls180.v:439.13-439.73" + wire width 22 \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "ls180.v:438.6-438.64" + wire \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "ls180.v:444.6-444.60" + wire \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first + attribute \src "ls180.v:445.6-445.59" + wire \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last + attribute \src "ls180.v:443.13-443.74" + wire width 22 \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "ls180.v:442.6-442.65" + wire \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "ls180.v:427.11-427.56" + wire width 4 \sdram_bankmachine0_cmd_buffer_lookahead_level + attribute \src "ls180.v:429.11-429.58" + wire width 3 \sdram_bankmachine0_cmd_buffer_lookahead_produce + attribute \src "ls180.v:436.12-436.62" + wire width 3 \sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr + attribute \src "ls180.v:437.13-437.65" + wire width 25 \sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r + attribute \src "ls180.v:428.5-428.52" + wire \sdram_bankmachine0_cmd_buffer_lookahead_replace + attribute \src "ls180.v:411.5-411.55" + wire \sdram_bankmachine0_cmd_buffer_lookahead_sink_first + attribute \src "ls180.v:412.5-412.54" + wire \sdram_bankmachine0_cmd_buffer_lookahead_sink_last + attribute \src "ls180.v:414.13-414.70" + wire width 22 \sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr + attribute \src "ls180.v:413.6-413.61" + wire \sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we + attribute \src "ls180.v:410.6-410.56" + wire \sdram_bankmachine0_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:409.6-409.56" + wire \sdram_bankmachine0_cmd_buffer_lookahead_sink_valid + attribute \src "ls180.v:417.6-417.58" + wire \sdram_bankmachine0_cmd_buffer_lookahead_source_first + attribute \src "ls180.v:418.6-418.57" + wire \sdram_bankmachine0_cmd_buffer_lookahead_source_last + attribute \src "ls180.v:420.13-420.72" + wire width 22 \sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr + attribute \src "ls180.v:419.6-419.63" + wire \sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we + attribute \src "ls180.v:416.6-416.58" + wire \sdram_bankmachine0_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:415.6-415.58" + wire \sdram_bankmachine0_cmd_buffer_lookahead_source_valid + attribute \src "ls180.v:425.13-425.66" + wire width 25 \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din + attribute \src "ls180.v:426.13-426.67" + wire width 25 \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout + attribute \src "ls180.v:423.6-423.58" + wire \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re + attribute \src "ls180.v:424.6-424.64" + wire \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable + attribute \src "ls180.v:421.6-421.58" + wire \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + attribute \src "ls180.v:422.6-422.64" + wire \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + attribute \src "ls180.v:431.11-431.61" + wire width 3 \sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + attribute \src "ls180.v:432.13-432.65" + wire width 25 \sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r + attribute \src "ls180.v:434.13-434.65" + wire width 25 \sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w + attribute \src "ls180.v:433.6-433.55" + wire \sdram_bankmachine0_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:448.6-448.46" + wire \sdram_bankmachine0_cmd_buffer_sink_first + attribute \src "ls180.v:449.6-449.45" + wire \sdram_bankmachine0_cmd_buffer_sink_last + attribute \src "ls180.v:451.13-451.60" + wire width 22 \sdram_bankmachine0_cmd_buffer_sink_payload_addr + attribute \src "ls180.v:450.6-450.51" + wire \sdram_bankmachine0_cmd_buffer_sink_payload_we + attribute \src "ls180.v:447.6-447.46" + wire \sdram_bankmachine0_cmd_buffer_sink_ready + attribute \src "ls180.v:446.6-446.46" + wire \sdram_bankmachine0_cmd_buffer_sink_valid + attribute \src "ls180.v:454.5-454.47" + wire \sdram_bankmachine0_cmd_buffer_source_first + attribute \src "ls180.v:455.5-455.46" + wire \sdram_bankmachine0_cmd_buffer_source_last + attribute \src "ls180.v:457.12-457.61" + wire width 22 \sdram_bankmachine0_cmd_buffer_source_payload_addr + attribute \src "ls180.v:456.5-456.52" + wire \sdram_bankmachine0_cmd_buffer_source_payload_we + attribute \src "ls180.v:453.6-453.48" + wire \sdram_bankmachine0_cmd_buffer_source_ready + attribute \src "ls180.v:452.5-452.47" + wire \sdram_bankmachine0_cmd_buffer_source_valid + attribute \src "ls180.v:400.12-400.44" + wire width 13 \sdram_bankmachine0_cmd_payload_a + attribute \src "ls180.v:401.12-401.45" + wire width 2 \sdram_bankmachine0_cmd_payload_ba + attribute \src "ls180.v:402.5-402.39" + wire \sdram_bankmachine0_cmd_payload_cas + attribute \src "ls180.v:405.5-405.42" + wire \sdram_bankmachine0_cmd_payload_is_cmd + attribute \src "ls180.v:406.5-406.43" + wire \sdram_bankmachine0_cmd_payload_is_read + attribute \src "ls180.v:407.5-407.44" + wire \sdram_bankmachine0_cmd_payload_is_write + attribute \src "ls180.v:403.5-403.39" + wire \sdram_bankmachine0_cmd_payload_ras + attribute \src "ls180.v:404.5-404.38" + wire \sdram_bankmachine0_cmd_payload_we + attribute \src "ls180.v:399.5-399.33" + wire \sdram_bankmachine0_cmd_ready + attribute \src "ls180.v:398.5-398.33" + wire \sdram_bankmachine0_cmd_valid + attribute \src "ls180.v:397.5-397.35" + wire \sdram_bankmachine0_refresh_gnt + attribute \src "ls180.v:396.6-396.36" + wire \sdram_bankmachine0_refresh_req + attribute \src "ls180.v:392.13-392.40" + wire width 22 \sdram_bankmachine0_req_addr + attribute \src "ls180.v:393.6-393.33" + wire \sdram_bankmachine0_req_lock + attribute \src "ls180.v:395.5-395.39" + wire \sdram_bankmachine0_req_rdata_valid + attribute \src "ls180.v:390.6-390.34" + wire \sdram_bankmachine0_req_ready + attribute \src "ls180.v:389.6-389.34" + wire \sdram_bankmachine0_req_valid + attribute \src "ls180.v:394.5-394.39" + wire \sdram_bankmachine0_req_wdata_ready + attribute \src "ls180.v:391.6-391.31" + wire \sdram_bankmachine0_req_we + attribute \src "ls180.v:458.12-458.34" + wire width 13 \sdram_bankmachine0_row + attribute \src "ls180.v:462.5-462.33" + wire \sdram_bankmachine0_row_close + attribute \src "ls180.v:463.5-463.42" + wire \sdram_bankmachine0_row_col_n_addr_sel + attribute \src "ls180.v:460.6-460.32" + wire \sdram_bankmachine0_row_hit + attribute \src "ls180.v:461.5-461.32" + wire \sdram_bankmachine0_row_open + attribute \src "ls180.v:459.5-459.34" + wire \sdram_bankmachine0_row_opened + attribute \no_retiming "true" + attribute \src "ls180.v:470.32-470.64" + wire \sdram_bankmachine0_trascon_ready + attribute \src "ls180.v:469.6-469.38" + wire \sdram_bankmachine0_trascon_valid attribute \no_retiming "true" - attribute \src "ls180.v:487.32-487.69" - wire \main_sdram_bankmachine0_twtpcon_ready - attribute \src "ls180.v:486.6-486.43" - wire \main_sdram_bankmachine0_twtpcon_valid - attribute \src "ls180.v:512.5-512.43" - wire \main_sdram_bankmachine1_auto_precharge - attribute \src "ls180.v:534.11-534.63" - wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_consume - attribute \src "ls180.v:539.6-539.58" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:544.6-544.64" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:545.6-545.63" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:543.13-543.78" - wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:542.6-542.69" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:548.6-548.65" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:549.6-549.64" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:547.13-547.79" - wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:546.6-546.70" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:531.11-531.61" - wire width 4 \main_sdram_bankmachine1_cmd_buffer_lookahead_level - attribute \src "ls180.v:533.11-533.63" - wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_produce - attribute \src "ls180.v:540.12-540.67" - wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:541.13-541.70" - wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:532.5-532.57" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - attribute \src "ls180.v:515.5-515.60" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:516.5-516.59" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:518.13-518.75" - wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:517.6-517.66" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:514.6-514.61" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:513.6-513.61" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:521.6-521.63" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:522.6-522.62" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:524.13-524.77" - wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:523.6-523.68" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:520.6-520.63" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:519.6-519.63" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:529.13-529.71" - wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din - attribute \src "ls180.v:530.13-530.72" - wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout - attribute \src "ls180.v:527.6-527.63" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re - attribute \src "ls180.v:528.6-528.69" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable - attribute \src "ls180.v:525.6-525.63" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we - attribute \src "ls180.v:526.6-526.69" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - attribute \src "ls180.v:535.11-535.66" - wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:536.13-536.70" - wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:538.13-538.70" - wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:537.6-537.60" - wire \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:552.6-552.51" - wire \main_sdram_bankmachine1_cmd_buffer_sink_first - attribute \src "ls180.v:553.6-553.50" - wire \main_sdram_bankmachine1_cmd_buffer_sink_last - attribute \src "ls180.v:555.13-555.65" - wire width 22 \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:554.6-554.56" - wire \main_sdram_bankmachine1_cmd_buffer_sink_payload_we - attribute \src "ls180.v:551.6-551.51" - wire \main_sdram_bankmachine1_cmd_buffer_sink_ready - attribute \src "ls180.v:550.6-550.51" - wire \main_sdram_bankmachine1_cmd_buffer_sink_valid - attribute \src "ls180.v:558.5-558.52" - wire \main_sdram_bankmachine1_cmd_buffer_source_first - attribute \src "ls180.v:559.5-559.51" - wire \main_sdram_bankmachine1_cmd_buffer_source_last - attribute \src "ls180.v:561.12-561.66" - wire width 22 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr - attribute \src "ls180.v:560.5-560.57" - wire \main_sdram_bankmachine1_cmd_buffer_source_payload_we - attribute \src "ls180.v:557.6-557.53" - wire \main_sdram_bankmachine1_cmd_buffer_source_ready - attribute \src "ls180.v:556.5-556.52" - wire \main_sdram_bankmachine1_cmd_buffer_source_valid - attribute \src "ls180.v:504.12-504.49" - wire width 13 \main_sdram_bankmachine1_cmd_payload_a - attribute \src "ls180.v:505.12-505.50" - wire width 2 \main_sdram_bankmachine1_cmd_payload_ba - attribute \src "ls180.v:506.5-506.44" - wire \main_sdram_bankmachine1_cmd_payload_cas - attribute \src "ls180.v:509.5-509.47" - wire \main_sdram_bankmachine1_cmd_payload_is_cmd - attribute \src "ls180.v:510.5-510.48" - wire \main_sdram_bankmachine1_cmd_payload_is_read - attribute \src "ls180.v:511.5-511.49" - wire \main_sdram_bankmachine1_cmd_payload_is_write - attribute \src "ls180.v:507.5-507.44" - wire \main_sdram_bankmachine1_cmd_payload_ras - attribute \src "ls180.v:508.5-508.43" - wire \main_sdram_bankmachine1_cmd_payload_we - attribute \src "ls180.v:503.5-503.38" - wire \main_sdram_bankmachine1_cmd_ready - attribute \src "ls180.v:502.5-502.38" - wire \main_sdram_bankmachine1_cmd_valid - attribute \src "ls180.v:501.5-501.40" - wire \main_sdram_bankmachine1_refresh_gnt - attribute \src "ls180.v:500.6-500.41" - wire \main_sdram_bankmachine1_refresh_req - attribute \src "ls180.v:496.13-496.45" - wire width 22 \main_sdram_bankmachine1_req_addr - attribute \src "ls180.v:497.6-497.38" - wire \main_sdram_bankmachine1_req_lock - attribute \src "ls180.v:499.5-499.44" - wire \main_sdram_bankmachine1_req_rdata_valid - attribute \src "ls180.v:494.6-494.39" - wire \main_sdram_bankmachine1_req_ready - attribute \src "ls180.v:493.6-493.39" - wire \main_sdram_bankmachine1_req_valid - attribute \src "ls180.v:498.5-498.44" - wire \main_sdram_bankmachine1_req_wdata_ready - attribute \src "ls180.v:495.6-495.36" - wire \main_sdram_bankmachine1_req_we - attribute \src "ls180.v:562.12-562.39" - wire width 13 \main_sdram_bankmachine1_row - attribute \src "ls180.v:566.5-566.38" - wire \main_sdram_bankmachine1_row_close - attribute \src "ls180.v:567.5-567.47" - wire \main_sdram_bankmachine1_row_col_n_addr_sel - attribute \src "ls180.v:564.6-564.37" - wire \main_sdram_bankmachine1_row_hit - attribute \src "ls180.v:565.5-565.37" - wire \main_sdram_bankmachine1_row_open - attribute \src "ls180.v:563.5-563.39" - wire \main_sdram_bankmachine1_row_opened + attribute \src "ls180.v:468.32-468.63" + wire \sdram_bankmachine0_trccon_ready + attribute \src "ls180.v:467.6-467.37" + wire \sdram_bankmachine0_trccon_valid + attribute \src "ls180.v:466.11-466.43" + wire width 3 \sdram_bankmachine0_twtpcon_count attribute \no_retiming "true" - attribute \src "ls180.v:574.32-574.69" - wire \main_sdram_bankmachine1_trascon_ready - attribute \src "ls180.v:573.6-573.43" - wire \main_sdram_bankmachine1_trascon_valid + attribute \src "ls180.v:465.32-465.64" + wire \sdram_bankmachine0_twtpcon_ready + attribute \src "ls180.v:464.6-464.38" + wire \sdram_bankmachine0_twtpcon_valid + attribute \src "ls180.v:490.5-490.38" + wire \sdram_bankmachine1_auto_precharge + attribute \src "ls180.v:512.11-512.58" + wire width 3 \sdram_bankmachine1_cmd_buffer_lookahead_consume + attribute \src "ls180.v:517.6-517.53" + wire \sdram_bankmachine1_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:522.6-522.59" + wire \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first + attribute \src "ls180.v:523.6-523.58" + wire \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last + attribute \src "ls180.v:521.13-521.73" + wire width 22 \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "ls180.v:520.6-520.64" + wire \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "ls180.v:526.6-526.60" + wire \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first + attribute \src "ls180.v:527.6-527.59" + wire \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last + attribute \src "ls180.v:525.13-525.74" + wire width 22 \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "ls180.v:524.6-524.65" + wire \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "ls180.v:509.11-509.56" + wire width 4 \sdram_bankmachine1_cmd_buffer_lookahead_level + attribute \src "ls180.v:511.11-511.58" + wire width 3 \sdram_bankmachine1_cmd_buffer_lookahead_produce + attribute \src "ls180.v:518.12-518.62" + wire width 3 \sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr + attribute \src "ls180.v:519.13-519.65" + wire width 25 \sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r + attribute \src "ls180.v:510.5-510.52" + wire \sdram_bankmachine1_cmd_buffer_lookahead_replace + attribute \src "ls180.v:493.5-493.55" + wire \sdram_bankmachine1_cmd_buffer_lookahead_sink_first + attribute \src "ls180.v:494.5-494.54" + wire \sdram_bankmachine1_cmd_buffer_lookahead_sink_last + attribute \src "ls180.v:496.13-496.70" + wire width 22 \sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr + attribute \src "ls180.v:495.6-495.61" + wire \sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we + attribute \src "ls180.v:492.6-492.56" + wire \sdram_bankmachine1_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:491.6-491.56" + wire \sdram_bankmachine1_cmd_buffer_lookahead_sink_valid + attribute \src "ls180.v:499.6-499.58" + wire \sdram_bankmachine1_cmd_buffer_lookahead_source_first + attribute \src "ls180.v:500.6-500.57" + wire \sdram_bankmachine1_cmd_buffer_lookahead_source_last + attribute \src "ls180.v:502.13-502.72" + wire width 22 \sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr + attribute \src "ls180.v:501.6-501.63" + wire \sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we + attribute \src "ls180.v:498.6-498.58" + wire \sdram_bankmachine1_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:497.6-497.58" + wire \sdram_bankmachine1_cmd_buffer_lookahead_source_valid + attribute \src "ls180.v:507.13-507.66" + wire width 25 \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din + attribute \src "ls180.v:508.13-508.67" + wire width 25 \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout + attribute \src "ls180.v:505.6-505.58" + wire \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re + attribute \src "ls180.v:506.6-506.64" + wire \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable + attribute \src "ls180.v:503.6-503.58" + wire \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + attribute \src "ls180.v:504.6-504.64" + wire \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + attribute \src "ls180.v:513.11-513.61" + wire width 3 \sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + attribute \src "ls180.v:514.13-514.65" + wire width 25 \sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r + attribute \src "ls180.v:516.13-516.65" + wire width 25 \sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w + attribute \src "ls180.v:515.6-515.55" + wire \sdram_bankmachine1_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:530.6-530.46" + wire \sdram_bankmachine1_cmd_buffer_sink_first + attribute \src "ls180.v:531.6-531.45" + wire \sdram_bankmachine1_cmd_buffer_sink_last + attribute \src "ls180.v:533.13-533.60" + wire width 22 \sdram_bankmachine1_cmd_buffer_sink_payload_addr + attribute \src "ls180.v:532.6-532.51" + wire \sdram_bankmachine1_cmd_buffer_sink_payload_we + attribute \src "ls180.v:529.6-529.46" + wire \sdram_bankmachine1_cmd_buffer_sink_ready + attribute \src "ls180.v:528.6-528.46" + wire \sdram_bankmachine1_cmd_buffer_sink_valid + attribute \src "ls180.v:536.5-536.47" + wire \sdram_bankmachine1_cmd_buffer_source_first + attribute \src "ls180.v:537.5-537.46" + wire \sdram_bankmachine1_cmd_buffer_source_last + attribute \src "ls180.v:539.12-539.61" + wire width 22 \sdram_bankmachine1_cmd_buffer_source_payload_addr + attribute \src "ls180.v:538.5-538.52" + wire \sdram_bankmachine1_cmd_buffer_source_payload_we + attribute \src "ls180.v:535.6-535.48" + wire \sdram_bankmachine1_cmd_buffer_source_ready + attribute \src "ls180.v:534.5-534.47" + wire \sdram_bankmachine1_cmd_buffer_source_valid + attribute \src "ls180.v:482.12-482.44" + wire width 13 \sdram_bankmachine1_cmd_payload_a + attribute \src "ls180.v:483.12-483.45" + wire width 2 \sdram_bankmachine1_cmd_payload_ba + attribute \src "ls180.v:484.5-484.39" + wire \sdram_bankmachine1_cmd_payload_cas + attribute \src "ls180.v:487.5-487.42" + wire \sdram_bankmachine1_cmd_payload_is_cmd + attribute \src "ls180.v:488.5-488.43" + wire \sdram_bankmachine1_cmd_payload_is_read + attribute \src "ls180.v:489.5-489.44" + wire \sdram_bankmachine1_cmd_payload_is_write + attribute \src "ls180.v:485.5-485.39" + wire \sdram_bankmachine1_cmd_payload_ras + attribute \src "ls180.v:486.5-486.38" + wire \sdram_bankmachine1_cmd_payload_we + attribute \src "ls180.v:481.5-481.33" + wire \sdram_bankmachine1_cmd_ready + attribute \src "ls180.v:480.5-480.33" + wire \sdram_bankmachine1_cmd_valid + attribute \src "ls180.v:479.5-479.35" + wire \sdram_bankmachine1_refresh_gnt + attribute \src "ls180.v:478.6-478.36" + wire \sdram_bankmachine1_refresh_req + attribute \src "ls180.v:474.13-474.40" + wire width 22 \sdram_bankmachine1_req_addr + attribute \src "ls180.v:475.6-475.33" + wire \sdram_bankmachine1_req_lock + attribute \src "ls180.v:477.5-477.39" + wire \sdram_bankmachine1_req_rdata_valid + attribute \src "ls180.v:472.6-472.34" + wire \sdram_bankmachine1_req_ready + attribute \src "ls180.v:471.6-471.34" + wire \sdram_bankmachine1_req_valid + attribute \src "ls180.v:476.5-476.39" + wire \sdram_bankmachine1_req_wdata_ready + attribute \src "ls180.v:473.6-473.31" + wire \sdram_bankmachine1_req_we + attribute \src "ls180.v:540.12-540.34" + wire width 13 \sdram_bankmachine1_row + attribute \src "ls180.v:544.5-544.33" + wire \sdram_bankmachine1_row_close + attribute \src "ls180.v:545.5-545.42" + wire \sdram_bankmachine1_row_col_n_addr_sel + attribute \src "ls180.v:542.6-542.32" + wire \sdram_bankmachine1_row_hit + attribute \src "ls180.v:543.5-543.32" + wire \sdram_bankmachine1_row_open + attribute \src "ls180.v:541.5-541.34" + wire \sdram_bankmachine1_row_opened attribute \no_retiming "true" - attribute \src "ls180.v:572.32-572.68" - wire \main_sdram_bankmachine1_trccon_ready - attribute \src "ls180.v:571.6-571.42" - wire \main_sdram_bankmachine1_trccon_valid - attribute \src "ls180.v:570.11-570.48" - wire width 3 \main_sdram_bankmachine1_twtpcon_count + attribute \src "ls180.v:552.32-552.64" + wire \sdram_bankmachine1_trascon_ready + attribute \src "ls180.v:551.6-551.38" + wire \sdram_bankmachine1_trascon_valid attribute \no_retiming "true" - attribute \src "ls180.v:569.32-569.69" - wire \main_sdram_bankmachine1_twtpcon_ready - attribute \src "ls180.v:568.6-568.43" - wire \main_sdram_bankmachine1_twtpcon_valid - attribute \src "ls180.v:594.5-594.43" - wire \main_sdram_bankmachine2_auto_precharge - attribute \src "ls180.v:616.11-616.63" - wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_consume - attribute \src "ls180.v:621.6-621.58" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:626.6-626.64" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:627.6-627.63" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:625.13-625.78" - wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:624.6-624.69" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:630.6-630.65" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:631.6-631.64" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:629.13-629.79" - wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:628.6-628.70" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:613.11-613.61" - wire width 4 \main_sdram_bankmachine2_cmd_buffer_lookahead_level - attribute \src "ls180.v:615.11-615.63" - wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_produce - attribute \src "ls180.v:622.12-622.67" - wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:623.13-623.70" - wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:614.5-614.57" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - attribute \src "ls180.v:597.5-597.60" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:598.5-598.59" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:600.13-600.75" - wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:599.6-599.66" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:596.6-596.61" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:595.6-595.61" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:603.6-603.63" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:604.6-604.62" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:606.13-606.77" - wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:605.6-605.68" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:602.6-602.63" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:601.6-601.63" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:611.13-611.71" - wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din - attribute \src "ls180.v:612.13-612.72" - wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout - attribute \src "ls180.v:609.6-609.63" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re - attribute \src "ls180.v:610.6-610.69" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable - attribute \src "ls180.v:607.6-607.63" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we - attribute \src "ls180.v:608.6-608.69" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - attribute \src "ls180.v:617.11-617.66" - wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:618.13-618.70" - wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:620.13-620.70" - wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:619.6-619.60" - wire \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:634.6-634.51" - wire \main_sdram_bankmachine2_cmd_buffer_sink_first - attribute \src "ls180.v:635.6-635.50" - wire \main_sdram_bankmachine2_cmd_buffer_sink_last - attribute \src "ls180.v:637.13-637.65" - wire width 22 \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:636.6-636.56" - wire \main_sdram_bankmachine2_cmd_buffer_sink_payload_we - attribute \src "ls180.v:633.6-633.51" - wire \main_sdram_bankmachine2_cmd_buffer_sink_ready - attribute \src "ls180.v:632.6-632.51" - wire \main_sdram_bankmachine2_cmd_buffer_sink_valid - attribute \src "ls180.v:640.5-640.52" - wire \main_sdram_bankmachine2_cmd_buffer_source_first - attribute \src "ls180.v:641.5-641.51" - wire \main_sdram_bankmachine2_cmd_buffer_source_last - attribute \src "ls180.v:643.12-643.66" - wire width 22 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr - attribute \src "ls180.v:642.5-642.57" - wire \main_sdram_bankmachine2_cmd_buffer_source_payload_we - attribute \src "ls180.v:639.6-639.53" - wire \main_sdram_bankmachine2_cmd_buffer_source_ready - attribute \src "ls180.v:638.5-638.52" - wire \main_sdram_bankmachine2_cmd_buffer_source_valid - attribute \src "ls180.v:586.12-586.49" - wire width 13 \main_sdram_bankmachine2_cmd_payload_a - attribute \src "ls180.v:587.12-587.50" - wire width 2 \main_sdram_bankmachine2_cmd_payload_ba - attribute \src "ls180.v:588.5-588.44" - wire \main_sdram_bankmachine2_cmd_payload_cas - attribute \src "ls180.v:591.5-591.47" - wire \main_sdram_bankmachine2_cmd_payload_is_cmd - attribute \src "ls180.v:592.5-592.48" - wire \main_sdram_bankmachine2_cmd_payload_is_read - attribute \src "ls180.v:593.5-593.49" - wire \main_sdram_bankmachine2_cmd_payload_is_write - attribute \src "ls180.v:589.5-589.44" - wire \main_sdram_bankmachine2_cmd_payload_ras - attribute \src "ls180.v:590.5-590.43" - wire \main_sdram_bankmachine2_cmd_payload_we - attribute \src "ls180.v:585.5-585.38" - wire \main_sdram_bankmachine2_cmd_ready - attribute \src "ls180.v:584.5-584.38" - wire \main_sdram_bankmachine2_cmd_valid - attribute \src "ls180.v:583.5-583.40" - wire \main_sdram_bankmachine2_refresh_gnt - attribute \src "ls180.v:582.6-582.41" - wire \main_sdram_bankmachine2_refresh_req - attribute \src "ls180.v:578.13-578.45" - wire width 22 \main_sdram_bankmachine2_req_addr - attribute \src "ls180.v:579.6-579.38" - wire \main_sdram_bankmachine2_req_lock - attribute \src "ls180.v:581.5-581.44" - wire \main_sdram_bankmachine2_req_rdata_valid - attribute \src "ls180.v:576.6-576.39" - wire \main_sdram_bankmachine2_req_ready - attribute \src "ls180.v:575.6-575.39" - wire \main_sdram_bankmachine2_req_valid - attribute \src "ls180.v:580.5-580.44" - wire \main_sdram_bankmachine2_req_wdata_ready - attribute \src "ls180.v:577.6-577.36" - wire \main_sdram_bankmachine2_req_we - attribute \src "ls180.v:644.12-644.39" - wire width 13 \main_sdram_bankmachine2_row - attribute \src "ls180.v:648.5-648.38" - wire \main_sdram_bankmachine2_row_close - attribute \src "ls180.v:649.5-649.47" - wire \main_sdram_bankmachine2_row_col_n_addr_sel - attribute \src "ls180.v:646.6-646.37" - wire \main_sdram_bankmachine2_row_hit - attribute \src "ls180.v:647.5-647.37" - wire \main_sdram_bankmachine2_row_open - attribute \src "ls180.v:645.5-645.39" - wire \main_sdram_bankmachine2_row_opened + attribute \src "ls180.v:550.32-550.63" + wire \sdram_bankmachine1_trccon_ready + attribute \src "ls180.v:549.6-549.37" + wire \sdram_bankmachine1_trccon_valid + attribute \src "ls180.v:548.11-548.43" + wire width 3 \sdram_bankmachine1_twtpcon_count attribute \no_retiming "true" - attribute \src "ls180.v:656.32-656.69" - wire \main_sdram_bankmachine2_trascon_ready - attribute \src "ls180.v:655.6-655.43" - wire \main_sdram_bankmachine2_trascon_valid + attribute \src "ls180.v:547.32-547.64" + wire \sdram_bankmachine1_twtpcon_ready + attribute \src "ls180.v:546.6-546.38" + wire \sdram_bankmachine1_twtpcon_valid + attribute \src "ls180.v:572.5-572.38" + wire \sdram_bankmachine2_auto_precharge + attribute \src "ls180.v:594.11-594.58" + wire width 3 \sdram_bankmachine2_cmd_buffer_lookahead_consume + attribute \src "ls180.v:599.6-599.53" + wire \sdram_bankmachine2_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:604.6-604.59" + wire \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first + attribute \src "ls180.v:605.6-605.58" + wire \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last + attribute \src "ls180.v:603.13-603.73" + wire width 22 \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "ls180.v:602.6-602.64" + wire \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "ls180.v:608.6-608.60" + wire \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first + attribute \src "ls180.v:609.6-609.59" + wire \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last + attribute \src "ls180.v:607.13-607.74" + wire width 22 \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "ls180.v:606.6-606.65" + wire \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "ls180.v:591.11-591.56" + wire width 4 \sdram_bankmachine2_cmd_buffer_lookahead_level + attribute \src "ls180.v:593.11-593.58" + wire width 3 \sdram_bankmachine2_cmd_buffer_lookahead_produce + attribute \src "ls180.v:600.12-600.62" + wire width 3 \sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr + attribute \src "ls180.v:601.13-601.65" + wire width 25 \sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r + attribute \src "ls180.v:592.5-592.52" + wire \sdram_bankmachine2_cmd_buffer_lookahead_replace + attribute \src "ls180.v:575.5-575.55" + wire \sdram_bankmachine2_cmd_buffer_lookahead_sink_first + attribute \src "ls180.v:576.5-576.54" + wire \sdram_bankmachine2_cmd_buffer_lookahead_sink_last + attribute \src "ls180.v:578.13-578.70" + wire width 22 \sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr + attribute \src "ls180.v:577.6-577.61" + wire \sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we + attribute \src "ls180.v:574.6-574.56" + wire \sdram_bankmachine2_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:573.6-573.56" + wire \sdram_bankmachine2_cmd_buffer_lookahead_sink_valid + attribute \src "ls180.v:581.6-581.58" + wire \sdram_bankmachine2_cmd_buffer_lookahead_source_first + attribute \src "ls180.v:582.6-582.57" + wire \sdram_bankmachine2_cmd_buffer_lookahead_source_last + attribute \src "ls180.v:584.13-584.72" + wire width 22 \sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr + attribute \src "ls180.v:583.6-583.63" + wire \sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we + attribute \src "ls180.v:580.6-580.58" + wire \sdram_bankmachine2_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:579.6-579.58" + wire \sdram_bankmachine2_cmd_buffer_lookahead_source_valid + attribute \src "ls180.v:589.13-589.66" + wire width 25 \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din + attribute \src "ls180.v:590.13-590.67" + wire width 25 \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout + attribute \src "ls180.v:587.6-587.58" + wire \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re + attribute \src "ls180.v:588.6-588.64" + wire \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable + attribute \src "ls180.v:585.6-585.58" + wire \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + attribute \src "ls180.v:586.6-586.64" + wire \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + attribute \src "ls180.v:595.11-595.61" + wire width 3 \sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + attribute \src "ls180.v:596.13-596.65" + wire width 25 \sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r + attribute \src "ls180.v:598.13-598.65" + wire width 25 \sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w + attribute \src "ls180.v:597.6-597.55" + wire \sdram_bankmachine2_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:612.6-612.46" + wire \sdram_bankmachine2_cmd_buffer_sink_first + attribute \src "ls180.v:613.6-613.45" + wire \sdram_bankmachine2_cmd_buffer_sink_last + attribute \src "ls180.v:615.13-615.60" + wire width 22 \sdram_bankmachine2_cmd_buffer_sink_payload_addr + attribute \src "ls180.v:614.6-614.51" + wire \sdram_bankmachine2_cmd_buffer_sink_payload_we + attribute \src "ls180.v:611.6-611.46" + wire \sdram_bankmachine2_cmd_buffer_sink_ready + attribute \src "ls180.v:610.6-610.46" + wire \sdram_bankmachine2_cmd_buffer_sink_valid + attribute \src "ls180.v:618.5-618.47" + wire \sdram_bankmachine2_cmd_buffer_source_first + attribute \src "ls180.v:619.5-619.46" + wire \sdram_bankmachine2_cmd_buffer_source_last + attribute \src "ls180.v:621.12-621.61" + wire width 22 \sdram_bankmachine2_cmd_buffer_source_payload_addr + attribute \src "ls180.v:620.5-620.52" + wire \sdram_bankmachine2_cmd_buffer_source_payload_we + attribute \src "ls180.v:617.6-617.48" + wire \sdram_bankmachine2_cmd_buffer_source_ready + attribute \src "ls180.v:616.5-616.47" + wire \sdram_bankmachine2_cmd_buffer_source_valid + attribute \src "ls180.v:564.12-564.44" + wire width 13 \sdram_bankmachine2_cmd_payload_a + attribute \src "ls180.v:565.12-565.45" + wire width 2 \sdram_bankmachine2_cmd_payload_ba + attribute \src "ls180.v:566.5-566.39" + wire \sdram_bankmachine2_cmd_payload_cas + attribute \src "ls180.v:569.5-569.42" + wire \sdram_bankmachine2_cmd_payload_is_cmd + attribute \src "ls180.v:570.5-570.43" + wire \sdram_bankmachine2_cmd_payload_is_read + attribute \src "ls180.v:571.5-571.44" + wire \sdram_bankmachine2_cmd_payload_is_write + attribute \src "ls180.v:567.5-567.39" + wire \sdram_bankmachine2_cmd_payload_ras + attribute \src "ls180.v:568.5-568.38" + wire \sdram_bankmachine2_cmd_payload_we + attribute \src "ls180.v:563.5-563.33" + wire \sdram_bankmachine2_cmd_ready + attribute \src "ls180.v:562.5-562.33" + wire \sdram_bankmachine2_cmd_valid + attribute \src "ls180.v:561.5-561.35" + wire \sdram_bankmachine2_refresh_gnt + attribute \src "ls180.v:560.6-560.36" + wire \sdram_bankmachine2_refresh_req + attribute \src "ls180.v:556.13-556.40" + wire width 22 \sdram_bankmachine2_req_addr + attribute \src "ls180.v:557.6-557.33" + wire \sdram_bankmachine2_req_lock + attribute \src "ls180.v:559.5-559.39" + wire \sdram_bankmachine2_req_rdata_valid + attribute \src "ls180.v:554.6-554.34" + wire \sdram_bankmachine2_req_ready + attribute \src "ls180.v:553.6-553.34" + wire \sdram_bankmachine2_req_valid + attribute \src "ls180.v:558.5-558.39" + wire \sdram_bankmachine2_req_wdata_ready + attribute \src "ls180.v:555.6-555.31" + wire \sdram_bankmachine2_req_we + attribute \src "ls180.v:622.12-622.34" + wire width 13 \sdram_bankmachine2_row + attribute \src "ls180.v:626.5-626.33" + wire \sdram_bankmachine2_row_close + attribute \src "ls180.v:627.5-627.42" + wire \sdram_bankmachine2_row_col_n_addr_sel + attribute \src "ls180.v:624.6-624.32" + wire \sdram_bankmachine2_row_hit + attribute \src "ls180.v:625.5-625.32" + wire \sdram_bankmachine2_row_open + attribute \src "ls180.v:623.5-623.34" + wire \sdram_bankmachine2_row_opened attribute \no_retiming "true" - attribute \src "ls180.v:654.32-654.68" - wire \main_sdram_bankmachine2_trccon_ready - attribute \src "ls180.v:653.6-653.42" - wire \main_sdram_bankmachine2_trccon_valid - attribute \src "ls180.v:652.11-652.48" - wire width 3 \main_sdram_bankmachine2_twtpcon_count + attribute \src "ls180.v:634.32-634.64" + wire \sdram_bankmachine2_trascon_ready + attribute \src "ls180.v:633.6-633.38" + wire \sdram_bankmachine2_trascon_valid attribute \no_retiming "true" - attribute \src "ls180.v:651.32-651.69" - wire \main_sdram_bankmachine2_twtpcon_ready - attribute \src "ls180.v:650.6-650.43" - wire \main_sdram_bankmachine2_twtpcon_valid - attribute \src "ls180.v:676.5-676.43" - wire \main_sdram_bankmachine3_auto_precharge - attribute \src "ls180.v:698.11-698.63" - wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_consume - attribute \src "ls180.v:703.6-703.58" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:708.6-708.64" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first - attribute \src "ls180.v:709.6-709.63" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last - attribute \src "ls180.v:707.13-707.78" - wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr - attribute \src "ls180.v:706.6-706.69" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we - attribute \src "ls180.v:712.6-712.65" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first - attribute \src "ls180.v:713.6-713.64" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last - attribute \src "ls180.v:711.13-711.79" - wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr - attribute \src "ls180.v:710.6-710.70" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we - attribute \src "ls180.v:695.11-695.61" - wire width 4 \main_sdram_bankmachine3_cmd_buffer_lookahead_level - attribute \src "ls180.v:697.11-697.63" - wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_produce - attribute \src "ls180.v:704.12-704.67" - wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr - attribute \src "ls180.v:705.13-705.70" - wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r - attribute \src "ls180.v:696.5-696.57" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - attribute \src "ls180.v:679.5-679.60" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first - attribute \src "ls180.v:680.5-680.59" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last - attribute \src "ls180.v:682.13-682.75" - wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr - attribute \src "ls180.v:681.6-681.66" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we - attribute \src "ls180.v:678.6-678.61" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready - attribute \src "ls180.v:677.6-677.61" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid - attribute \src "ls180.v:685.6-685.63" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first - attribute \src "ls180.v:686.6-686.62" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last - attribute \src "ls180.v:688.13-688.77" - wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr - attribute \src "ls180.v:687.6-687.68" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we - attribute \src "ls180.v:684.6-684.63" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready - attribute \src "ls180.v:683.6-683.63" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid - attribute \src "ls180.v:693.13-693.71" - wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din - attribute \src "ls180.v:694.13-694.72" - wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout - attribute \src "ls180.v:691.6-691.63" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re - attribute \src "ls180.v:692.6-692.69" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable - attribute \src "ls180.v:689.6-689.63" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we - attribute \src "ls180.v:690.6-690.69" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - attribute \src "ls180.v:699.11-699.66" - wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr - attribute \src "ls180.v:700.13-700.70" - wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r - attribute \src "ls180.v:702.13-702.70" - wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w - attribute \src "ls180.v:701.6-701.60" - wire \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:716.6-716.51" - wire \main_sdram_bankmachine3_cmd_buffer_sink_first - attribute \src "ls180.v:717.6-717.50" - wire \main_sdram_bankmachine3_cmd_buffer_sink_last - attribute \src "ls180.v:719.13-719.65" - wire width 22 \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr - attribute \src "ls180.v:718.6-718.56" - wire \main_sdram_bankmachine3_cmd_buffer_sink_payload_we - attribute \src "ls180.v:715.6-715.51" - wire \main_sdram_bankmachine3_cmd_buffer_sink_ready - attribute \src "ls180.v:714.6-714.51" - wire \main_sdram_bankmachine3_cmd_buffer_sink_valid - attribute \src "ls180.v:722.5-722.52" - wire \main_sdram_bankmachine3_cmd_buffer_source_first - attribute \src "ls180.v:723.5-723.51" - wire \main_sdram_bankmachine3_cmd_buffer_source_last - attribute \src "ls180.v:725.12-725.66" - wire width 22 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr - attribute \src "ls180.v:724.5-724.57" - wire \main_sdram_bankmachine3_cmd_buffer_source_payload_we - attribute \src "ls180.v:721.6-721.53" - wire \main_sdram_bankmachine3_cmd_buffer_source_ready - attribute \src "ls180.v:720.5-720.52" - wire \main_sdram_bankmachine3_cmd_buffer_source_valid - attribute \src "ls180.v:668.12-668.49" - wire width 13 \main_sdram_bankmachine3_cmd_payload_a - attribute \src "ls180.v:669.12-669.50" - wire width 2 \main_sdram_bankmachine3_cmd_payload_ba - attribute \src "ls180.v:670.5-670.44" - wire \main_sdram_bankmachine3_cmd_payload_cas - attribute \src "ls180.v:673.5-673.47" - wire \main_sdram_bankmachine3_cmd_payload_is_cmd - attribute \src "ls180.v:674.5-674.48" - wire \main_sdram_bankmachine3_cmd_payload_is_read - attribute \src "ls180.v:675.5-675.49" - wire \main_sdram_bankmachine3_cmd_payload_is_write - attribute \src "ls180.v:671.5-671.44" - wire \main_sdram_bankmachine3_cmd_payload_ras - attribute \src "ls180.v:672.5-672.43" - wire \main_sdram_bankmachine3_cmd_payload_we - attribute \src "ls180.v:667.5-667.38" - wire \main_sdram_bankmachine3_cmd_ready - attribute \src "ls180.v:666.5-666.38" - wire \main_sdram_bankmachine3_cmd_valid - attribute \src "ls180.v:665.5-665.40" - wire \main_sdram_bankmachine3_refresh_gnt - attribute \src "ls180.v:664.6-664.41" - wire \main_sdram_bankmachine3_refresh_req - attribute \src "ls180.v:660.13-660.45" - wire width 22 \main_sdram_bankmachine3_req_addr - attribute \src "ls180.v:661.6-661.38" - wire \main_sdram_bankmachine3_req_lock - attribute \src "ls180.v:663.5-663.44" - wire \main_sdram_bankmachine3_req_rdata_valid - attribute \src "ls180.v:658.6-658.39" - wire \main_sdram_bankmachine3_req_ready - attribute \src "ls180.v:657.6-657.39" - wire \main_sdram_bankmachine3_req_valid - attribute \src "ls180.v:662.5-662.44" - wire \main_sdram_bankmachine3_req_wdata_ready - attribute \src "ls180.v:659.6-659.36" - wire \main_sdram_bankmachine3_req_we - attribute \src "ls180.v:726.12-726.39" - wire width 13 \main_sdram_bankmachine3_row - attribute \src "ls180.v:730.5-730.38" - wire \main_sdram_bankmachine3_row_close - attribute \src "ls180.v:731.5-731.47" - wire \main_sdram_bankmachine3_row_col_n_addr_sel - attribute \src "ls180.v:728.6-728.37" - wire \main_sdram_bankmachine3_row_hit - attribute \src "ls180.v:729.5-729.37" - wire \main_sdram_bankmachine3_row_open - attribute \src "ls180.v:727.5-727.39" - wire \main_sdram_bankmachine3_row_opened + attribute \src "ls180.v:632.32-632.63" + wire \sdram_bankmachine2_trccon_ready + attribute \src "ls180.v:631.6-631.37" + wire \sdram_bankmachine2_trccon_valid + attribute \src "ls180.v:630.11-630.43" + wire width 3 \sdram_bankmachine2_twtpcon_count attribute \no_retiming "true" - attribute \src "ls180.v:738.32-738.69" - wire \main_sdram_bankmachine3_trascon_ready - attribute \src "ls180.v:737.6-737.43" - wire \main_sdram_bankmachine3_trascon_valid + attribute \src "ls180.v:629.32-629.64" + wire \sdram_bankmachine2_twtpcon_ready + attribute \src "ls180.v:628.6-628.38" + wire \sdram_bankmachine2_twtpcon_valid + attribute \src "ls180.v:654.5-654.38" + wire \sdram_bankmachine3_auto_precharge + attribute \src "ls180.v:676.11-676.58" + wire width 3 \sdram_bankmachine3_cmd_buffer_lookahead_consume + attribute \src "ls180.v:681.6-681.53" + wire \sdram_bankmachine3_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:686.6-686.59" + wire \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first + attribute \src "ls180.v:687.6-687.58" + wire \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last + attribute \src "ls180.v:685.13-685.73" + wire width 22 \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "ls180.v:684.6-684.64" + wire \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "ls180.v:690.6-690.60" + wire \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first + attribute \src "ls180.v:691.6-691.59" + wire \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last + attribute \src "ls180.v:689.13-689.74" + wire width 22 \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "ls180.v:688.6-688.65" + wire \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "ls180.v:673.11-673.56" + wire width 4 \sdram_bankmachine3_cmd_buffer_lookahead_level + attribute \src "ls180.v:675.11-675.58" + wire width 3 \sdram_bankmachine3_cmd_buffer_lookahead_produce + attribute \src "ls180.v:682.12-682.62" + wire width 3 \sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr + attribute \src "ls180.v:683.13-683.65" + wire width 25 \sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r + attribute \src "ls180.v:674.5-674.52" + wire \sdram_bankmachine3_cmd_buffer_lookahead_replace + attribute \src "ls180.v:657.5-657.55" + wire \sdram_bankmachine3_cmd_buffer_lookahead_sink_first + attribute \src "ls180.v:658.5-658.54" + wire \sdram_bankmachine3_cmd_buffer_lookahead_sink_last + attribute \src "ls180.v:660.13-660.70" + wire width 22 \sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr + attribute \src "ls180.v:659.6-659.61" + wire \sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we + attribute \src "ls180.v:656.6-656.56" + wire \sdram_bankmachine3_cmd_buffer_lookahead_sink_ready + attribute \src "ls180.v:655.6-655.56" + wire \sdram_bankmachine3_cmd_buffer_lookahead_sink_valid + attribute \src "ls180.v:663.6-663.58" + wire \sdram_bankmachine3_cmd_buffer_lookahead_source_first + attribute \src "ls180.v:664.6-664.57" + wire \sdram_bankmachine3_cmd_buffer_lookahead_source_last + attribute \src "ls180.v:666.13-666.72" + wire width 22 \sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr + attribute \src "ls180.v:665.6-665.63" + wire \sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we + attribute \src "ls180.v:662.6-662.58" + wire \sdram_bankmachine3_cmd_buffer_lookahead_source_ready + attribute \src "ls180.v:661.6-661.58" + wire \sdram_bankmachine3_cmd_buffer_lookahead_source_valid + attribute \src "ls180.v:671.13-671.66" + wire width 25 \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din + attribute \src "ls180.v:672.13-672.67" + wire width 25 \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout + attribute \src "ls180.v:669.6-669.58" + wire \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re + attribute \src "ls180.v:670.6-670.64" + wire \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable + attribute \src "ls180.v:667.6-667.58" + wire \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + attribute \src "ls180.v:668.6-668.64" + wire \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + attribute \src "ls180.v:677.11-677.61" + wire width 3 \sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + attribute \src "ls180.v:678.13-678.65" + wire width 25 \sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r + attribute \src "ls180.v:680.13-680.65" + wire width 25 \sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w + attribute \src "ls180.v:679.6-679.55" + wire \sdram_bankmachine3_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:694.6-694.46" + wire \sdram_bankmachine3_cmd_buffer_sink_first + attribute \src "ls180.v:695.6-695.45" + wire \sdram_bankmachine3_cmd_buffer_sink_last + attribute \src "ls180.v:697.13-697.60" + wire width 22 \sdram_bankmachine3_cmd_buffer_sink_payload_addr + attribute \src "ls180.v:696.6-696.51" + wire \sdram_bankmachine3_cmd_buffer_sink_payload_we + attribute \src "ls180.v:693.6-693.46" + wire \sdram_bankmachine3_cmd_buffer_sink_ready + attribute \src "ls180.v:692.6-692.46" + wire \sdram_bankmachine3_cmd_buffer_sink_valid + attribute \src "ls180.v:700.5-700.47" + wire \sdram_bankmachine3_cmd_buffer_source_first + attribute \src "ls180.v:701.5-701.46" + wire \sdram_bankmachine3_cmd_buffer_source_last + attribute \src "ls180.v:703.12-703.61" + wire width 22 \sdram_bankmachine3_cmd_buffer_source_payload_addr + attribute \src "ls180.v:702.5-702.52" + wire \sdram_bankmachine3_cmd_buffer_source_payload_we + attribute \src "ls180.v:699.6-699.48" + wire \sdram_bankmachine3_cmd_buffer_source_ready + attribute \src "ls180.v:698.5-698.47" + wire \sdram_bankmachine3_cmd_buffer_source_valid + attribute \src "ls180.v:646.12-646.44" + wire width 13 \sdram_bankmachine3_cmd_payload_a + attribute \src "ls180.v:647.12-647.45" + wire width 2 \sdram_bankmachine3_cmd_payload_ba + attribute \src "ls180.v:648.5-648.39" + wire \sdram_bankmachine3_cmd_payload_cas + attribute \src "ls180.v:651.5-651.42" + wire \sdram_bankmachine3_cmd_payload_is_cmd + attribute \src "ls180.v:652.5-652.43" + wire \sdram_bankmachine3_cmd_payload_is_read + attribute \src "ls180.v:653.5-653.44" + wire \sdram_bankmachine3_cmd_payload_is_write + attribute \src "ls180.v:649.5-649.39" + wire \sdram_bankmachine3_cmd_payload_ras + attribute \src "ls180.v:650.5-650.38" + wire \sdram_bankmachine3_cmd_payload_we + attribute \src "ls180.v:645.5-645.33" + wire \sdram_bankmachine3_cmd_ready + attribute \src "ls180.v:644.5-644.33" + wire \sdram_bankmachine3_cmd_valid + attribute \src "ls180.v:643.5-643.35" + wire \sdram_bankmachine3_refresh_gnt + attribute \src "ls180.v:642.6-642.36" + wire \sdram_bankmachine3_refresh_req + attribute \src "ls180.v:638.13-638.40" + wire width 22 \sdram_bankmachine3_req_addr + attribute \src "ls180.v:639.6-639.33" + wire \sdram_bankmachine3_req_lock + attribute \src "ls180.v:641.5-641.39" + wire \sdram_bankmachine3_req_rdata_valid + attribute \src "ls180.v:636.6-636.34" + wire \sdram_bankmachine3_req_ready + attribute \src "ls180.v:635.6-635.34" + wire \sdram_bankmachine3_req_valid + attribute \src "ls180.v:640.5-640.39" + wire \sdram_bankmachine3_req_wdata_ready + attribute \src "ls180.v:637.6-637.31" + wire \sdram_bankmachine3_req_we + attribute \src "ls180.v:704.12-704.34" + wire width 13 \sdram_bankmachine3_row + attribute \src "ls180.v:708.5-708.33" + wire \sdram_bankmachine3_row_close + attribute \src "ls180.v:709.5-709.42" + wire \sdram_bankmachine3_row_col_n_addr_sel + attribute \src "ls180.v:706.6-706.32" + wire \sdram_bankmachine3_row_hit + attribute \src "ls180.v:707.5-707.32" + wire \sdram_bankmachine3_row_open + attribute \src "ls180.v:705.5-705.34" + wire \sdram_bankmachine3_row_opened attribute \no_retiming "true" - attribute \src "ls180.v:736.32-736.68" - wire \main_sdram_bankmachine3_trccon_ready - attribute \src "ls180.v:735.6-735.42" - wire \main_sdram_bankmachine3_trccon_valid - attribute \src "ls180.v:734.11-734.48" - wire width 3 \main_sdram_bankmachine3_twtpcon_count + attribute \src "ls180.v:716.32-716.64" + wire \sdram_bankmachine3_trascon_ready + attribute \src "ls180.v:715.6-715.38" + wire \sdram_bankmachine3_trascon_valid attribute \no_retiming "true" - attribute \src "ls180.v:733.32-733.69" - wire \main_sdram_bankmachine3_twtpcon_ready + attribute \src "ls180.v:714.32-714.63" + wire \sdram_bankmachine3_trccon_ready + attribute \src "ls180.v:713.6-713.37" + wire \sdram_bankmachine3_trccon_valid + attribute \src "ls180.v:712.11-712.43" + wire width 3 \sdram_bankmachine3_twtpcon_count + attribute \no_retiming "true" + attribute \src "ls180.v:711.32-711.64" + wire \sdram_bankmachine3_twtpcon_ready + attribute \src "ls180.v:710.6-710.38" + wire \sdram_bankmachine3_twtpcon_valid + attribute \src "ls180.v:718.6-718.23" + wire \sdram_cas_allowed + attribute \src "ls180.v:21.14-21.25" + wire output 17 \sdram_cas_n + attribute \src "ls180.v:736.6-736.25" + wire \sdram_choose_cmd_ce + attribute \src "ls180.v:725.13-725.43" + wire width 13 \sdram_choose_cmd_cmd_payload_a + attribute \src "ls180.v:726.12-726.43" + wire width 2 \sdram_choose_cmd_cmd_payload_ba + attribute \src "ls180.v:727.5-727.37" + wire \sdram_choose_cmd_cmd_payload_cas + attribute \src "ls180.v:730.6-730.41" + wire \sdram_choose_cmd_cmd_payload_is_cmd + attribute \src "ls180.v:731.6-731.42" + wire \sdram_choose_cmd_cmd_payload_is_read attribute \src "ls180.v:732.6-732.43" - wire \main_sdram_bankmachine3_twtpcon_valid - attribute \src "ls180.v:740.6-740.28" - wire \main_sdram_cas_allowed - attribute \src "ls180.v:758.6-758.30" - wire \main_sdram_choose_cmd_ce - attribute \src "ls180.v:747.13-747.48" - wire width 13 \main_sdram_choose_cmd_cmd_payload_a - attribute \src "ls180.v:748.12-748.48" - wire width 2 \main_sdram_choose_cmd_cmd_payload_ba - attribute \src "ls180.v:749.5-749.42" - wire \main_sdram_choose_cmd_cmd_payload_cas - attribute \src "ls180.v:752.6-752.46" - wire \main_sdram_choose_cmd_cmd_payload_is_cmd - attribute \src "ls180.v:753.6-753.47" - wire \main_sdram_choose_cmd_cmd_payload_is_read - attribute \src "ls180.v:754.6-754.48" - wire \main_sdram_choose_cmd_cmd_payload_is_write - attribute \src "ls180.v:750.5-750.42" - wire \main_sdram_choose_cmd_cmd_payload_ras - attribute \src "ls180.v:751.5-751.41" - wire \main_sdram_choose_cmd_cmd_payload_we - attribute \src "ls180.v:746.5-746.36" - wire \main_sdram_choose_cmd_cmd_ready - attribute \src "ls180.v:745.6-745.37" - wire \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:757.11-757.38" - wire width 2 \main_sdram_choose_cmd_grant - attribute \src "ls180.v:756.12-756.41" - wire width 4 \main_sdram_choose_cmd_request - attribute \src "ls180.v:755.11-755.39" - wire width 4 \main_sdram_choose_cmd_valids - attribute \src "ls180.v:744.5-744.41" - wire \main_sdram_choose_cmd_want_activates - attribute \src "ls180.v:743.5-743.36" - wire \main_sdram_choose_cmd_want_cmds - attribute \src "ls180.v:741.5-741.37" - wire \main_sdram_choose_cmd_want_reads - attribute \src "ls180.v:742.5-742.38" - wire \main_sdram_choose_cmd_want_writes - attribute \src "ls180.v:776.6-776.30" - wire \main_sdram_choose_req_ce - attribute \src "ls180.v:765.13-765.48" - wire width 13 \main_sdram_choose_req_cmd_payload_a - attribute \src "ls180.v:766.12-766.48" - wire width 2 \main_sdram_choose_req_cmd_payload_ba - attribute \src "ls180.v:767.5-767.42" - wire \main_sdram_choose_req_cmd_payload_cas - attribute \src "ls180.v:770.6-770.46" - wire \main_sdram_choose_req_cmd_payload_is_cmd - attribute \src "ls180.v:771.6-771.47" - wire \main_sdram_choose_req_cmd_payload_is_read - attribute \src "ls180.v:772.6-772.48" - wire \main_sdram_choose_req_cmd_payload_is_write - attribute \src "ls180.v:768.5-768.42" - wire \main_sdram_choose_req_cmd_payload_ras - attribute \src "ls180.v:769.5-769.41" - wire \main_sdram_choose_req_cmd_payload_we - attribute \src "ls180.v:764.5-764.36" - wire \main_sdram_choose_req_cmd_ready - attribute \src "ls180.v:763.6-763.37" - wire \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:775.11-775.38" - wire width 2 \main_sdram_choose_req_grant - attribute \src "ls180.v:774.12-774.41" - wire width 4 \main_sdram_choose_req_request - attribute \src "ls180.v:773.11-773.39" - wire width 4 \main_sdram_choose_req_valids - attribute \src "ls180.v:762.5-762.41" - wire \main_sdram_choose_req_want_activates - attribute \src "ls180.v:761.6-761.37" - wire \main_sdram_choose_req_want_cmds - attribute \src "ls180.v:759.5-759.37" - wire \main_sdram_choose_req_want_reads - attribute \src "ls180.v:760.5-760.38" - wire \main_sdram_choose_req_want_writes - attribute \src "ls180.v:320.6-320.20" - wire \main_sdram_cke - attribute \src "ls180.v:388.5-388.24" - wire \main_sdram_cmd_last - attribute \src "ls180.v:389.12-389.36" - wire width 13 \main_sdram_cmd_payload_a - attribute \src "ls180.v:390.11-390.36" - wire width 2 \main_sdram_cmd_payload_ba - attribute \src "ls180.v:391.5-391.31" - wire \main_sdram_cmd_payload_cas - attribute \src "ls180.v:394.5-394.35" - wire \main_sdram_cmd_payload_is_read - attribute \src "ls180.v:395.5-395.36" - wire \main_sdram_cmd_payload_is_write - attribute \src "ls180.v:392.5-392.31" - wire \main_sdram_cmd_payload_ras - attribute \src "ls180.v:393.5-393.30" - wire \main_sdram_cmd_payload_we - attribute \src "ls180.v:387.5-387.25" - wire \main_sdram_cmd_ready - attribute \src "ls180.v:386.5-386.25" - wire \main_sdram_cmd_valid + wire \sdram_choose_cmd_cmd_payload_is_write + attribute \src "ls180.v:728.5-728.37" + wire \sdram_choose_cmd_cmd_payload_ras + attribute \src "ls180.v:729.5-729.36" + wire \sdram_choose_cmd_cmd_payload_we + attribute \src "ls180.v:724.5-724.31" + wire \sdram_choose_cmd_cmd_ready + attribute \src "ls180.v:723.6-723.32" + wire \sdram_choose_cmd_cmd_valid + attribute \src "ls180.v:735.11-735.33" + wire width 2 \sdram_choose_cmd_grant + attribute \src "ls180.v:734.12-734.36" + wire width 4 \sdram_choose_cmd_request + attribute \src "ls180.v:733.11-733.34" + wire width 4 \sdram_choose_cmd_valids + attribute \src "ls180.v:722.5-722.36" + wire \sdram_choose_cmd_want_activates + attribute \src "ls180.v:721.5-721.31" + wire \sdram_choose_cmd_want_cmds + attribute \src "ls180.v:719.5-719.32" + wire \sdram_choose_cmd_want_reads + attribute \src "ls180.v:720.5-720.33" + wire \sdram_choose_cmd_want_writes + attribute \src "ls180.v:754.6-754.25" + wire \sdram_choose_req_ce + attribute \src "ls180.v:743.13-743.43" + wire width 13 \sdram_choose_req_cmd_payload_a + attribute \src "ls180.v:744.12-744.43" + wire width 2 \sdram_choose_req_cmd_payload_ba + attribute \src "ls180.v:745.5-745.37" + wire \sdram_choose_req_cmd_payload_cas + attribute \src "ls180.v:748.6-748.41" + wire \sdram_choose_req_cmd_payload_is_cmd + attribute \src "ls180.v:749.6-749.42" + wire \sdram_choose_req_cmd_payload_is_read + attribute \src "ls180.v:750.6-750.43" + wire \sdram_choose_req_cmd_payload_is_write + attribute \src "ls180.v:746.5-746.37" + wire \sdram_choose_req_cmd_payload_ras + attribute \src "ls180.v:747.5-747.36" + wire \sdram_choose_req_cmd_payload_we + attribute \src "ls180.v:742.5-742.31" + wire \sdram_choose_req_cmd_ready + attribute \src "ls180.v:741.6-741.32" + wire \sdram_choose_req_cmd_valid + attribute \src "ls180.v:753.11-753.33" + wire width 2 \sdram_choose_req_grant + attribute \src "ls180.v:752.12-752.36" + wire width 4 \sdram_choose_req_request + attribute \src "ls180.v:751.11-751.34" + wire width 4 \sdram_choose_req_valids + attribute \src "ls180.v:740.5-740.36" + wire \sdram_choose_req_want_activates + attribute \src "ls180.v:739.6-739.32" + wire \sdram_choose_req_want_cmds + attribute \src "ls180.v:737.5-737.32" + wire \sdram_choose_req_want_reads + attribute \src "ls180.v:738.5-738.33" + wire \sdram_choose_req_want_writes + attribute \src "ls180.v:23.14-23.23" + wire output 19 \sdram_cke + attribute \src "ls180.v:298.6-298.17" + wire \sdram_cke_1 + attribute \src "ls180.v:136.5-136.16" + wire \sdram_clock + attribute \src "ls180.v:26.14-26.27" + wire output 22 \sdram_clock_1 + attribute \src "ls180.v:366.5-366.19" + wire \sdram_cmd_last + attribute \src "ls180.v:367.12-367.31" + wire width 13 \sdram_cmd_payload_a + attribute \src "ls180.v:368.11-368.31" + wire width 2 \sdram_cmd_payload_ba + attribute \src "ls180.v:369.5-369.26" + wire \sdram_cmd_payload_cas + attribute \src "ls180.v:372.5-372.30" + wire \sdram_cmd_payload_is_read + attribute \src "ls180.v:373.5-373.31" + wire \sdram_cmd_payload_is_write + attribute \src "ls180.v:370.5-370.26" + wire \sdram_cmd_payload_ras + attribute \src "ls180.v:371.5-371.25" + wire \sdram_cmd_payload_we + attribute \src "ls180.v:365.5-365.20" + wire \sdram_cmd_ready + attribute \src "ls180.v:364.5-364.20" + wire \sdram_cmd_valid + attribute \src "ls180.v:306.6-306.27" + wire \sdram_command_issue_r + attribute \src "ls180.v:305.6-305.28" + wire \sdram_command_issue_re + attribute \src "ls180.v:308.5-308.26" + wire \sdram_command_issue_w + attribute \src "ls180.v:307.6-307.28" + wire \sdram_command_issue_we + attribute \src "ls180.v:304.5-304.21" + wire \sdram_command_re + attribute \src "ls180.v:303.11-303.32" + wire width 6 \sdram_command_storage + attribute \src "ls180.v:22.14-22.24" + wire output 18 \sdram_cs_n + attribute \src "ls180.v:357.5-357.23" + wire \sdram_dfi_p0_act_n + attribute \src "ls180.v:348.12-348.32" + wire width 13 \sdram_dfi_p0_address + attribute \src "ls180.v:349.11-349.28" + wire width 2 \sdram_dfi_p0_bank + attribute \src "ls180.v:350.5-350.23" + wire \sdram_dfi_p0_cas_n + attribute \src "ls180.v:354.6-354.22" + wire \sdram_dfi_p0_cke + attribute \src "ls180.v:351.5-351.22" + wire \sdram_dfi_p0_cs_n + attribute \src "ls180.v:355.6-355.22" + wire \sdram_dfi_p0_odt + attribute \src "ls180.v:352.5-352.23" + wire \sdram_dfi_p0_ras_n + attribute \src "ls180.v:362.13-362.32" + wire width 16 \sdram_dfi_p0_rddata + attribute \src "ls180.v:361.5-361.27" + wire \sdram_dfi_p0_rddata_en + attribute \src "ls180.v:363.6-363.31" + wire \sdram_dfi_p0_rddata_valid + attribute \src "ls180.v:356.6-356.26" + wire \sdram_dfi_p0_reset_n + attribute \src "ls180.v:353.5-353.22" + wire \sdram_dfi_p0_we_n + attribute \src "ls180.v:358.13-358.32" + wire width 16 \sdram_dfi_p0_wrdata + attribute \src "ls180.v:359.5-359.27" + wire \sdram_dfi_p0_wrdata_en + attribute \src "ls180.v:360.12-360.36" + wire width 2 \sdram_dfi_p0_wrdata_mask + attribute \src "ls180.v:25.20-25.28" + wire width 2 output 21 \sdram_dm + attribute \src "ls180.v:16.20-16.30" + wire width 16 input 12 \sdram_dq_i + attribute \src "ls180.v:17.21-17.31" + wire width 16 output 13 \sdram_dq_o + attribute \src "ls180.v:18.14-18.25" + wire output 14 \sdram_dq_oe + attribute \src "ls180.v:772.5-772.14" + wire \sdram_en0 + attribute \src "ls180.v:775.5-775.14" + wire \sdram_en1 + attribute \src "ls180.v:778.6-778.25" + wire \sdram_go_to_refresh + attribute \src "ls180.v:320.13-320.39" + wire width 22 \sdram_interface_bank0_addr + attribute \src "ls180.v:321.6-321.32" + wire \sdram_interface_bank0_lock + attribute \src "ls180.v:323.6-323.39" + wire \sdram_interface_bank0_rdata_valid + attribute \src "ls180.v:318.6-318.33" + wire \sdram_interface_bank0_ready + attribute \src "ls180.v:317.6-317.33" + wire \sdram_interface_bank0_valid + attribute \src "ls180.v:322.6-322.39" + wire \sdram_interface_bank0_wdata_ready + attribute \src "ls180.v:319.6-319.30" + wire \sdram_interface_bank0_we + attribute \src "ls180.v:327.13-327.39" + wire width 22 \sdram_interface_bank1_addr attribute \src "ls180.v:328.6-328.32" - wire \main_sdram_command_issue_r - attribute \src "ls180.v:327.6-327.33" - wire \main_sdram_command_issue_re - attribute \src "ls180.v:330.5-330.31" - wire \main_sdram_command_issue_w - attribute \src "ls180.v:329.6-329.33" - wire \main_sdram_command_issue_we - attribute \src "ls180.v:326.5-326.26" - wire \main_sdram_command_re - attribute \src "ls180.v:325.11-325.37" - wire width 6 \main_sdram_command_storage - attribute \src "ls180.v:379.5-379.28" - wire \main_sdram_dfi_p0_act_n - attribute \src "ls180.v:370.12-370.37" - wire width 13 \main_sdram_dfi_p0_address - attribute \src "ls180.v:371.11-371.33" - wire width 2 \main_sdram_dfi_p0_bank - attribute \src "ls180.v:372.5-372.28" - wire \main_sdram_dfi_p0_cas_n - attribute \src "ls180.v:376.6-376.27" - wire \main_sdram_dfi_p0_cke - attribute \src "ls180.v:373.5-373.27" - wire \main_sdram_dfi_p0_cs_n - attribute \src "ls180.v:377.6-377.27" - wire \main_sdram_dfi_p0_odt - attribute \src "ls180.v:374.5-374.28" - wire \main_sdram_dfi_p0_ras_n - attribute \src "ls180.v:384.13-384.37" - wire width 16 \main_sdram_dfi_p0_rddata - attribute \src "ls180.v:383.5-383.32" - wire \main_sdram_dfi_p0_rddata_en - attribute \src "ls180.v:385.6-385.36" - wire \main_sdram_dfi_p0_rddata_valid - attribute \src "ls180.v:378.6-378.31" - wire \main_sdram_dfi_p0_reset_n - attribute \src "ls180.v:375.5-375.27" - wire \main_sdram_dfi_p0_we_n - attribute \src "ls180.v:380.13-380.37" - wire width 16 \main_sdram_dfi_p0_wrdata - attribute \src "ls180.v:381.5-381.32" - wire \main_sdram_dfi_p0_wrdata_en - attribute \src "ls180.v:382.12-382.41" - wire width 2 \main_sdram_dfi_p0_wrdata_mask - attribute \src "ls180.v:794.5-794.19" - wire \main_sdram_en0 - attribute \src "ls180.v:797.5-797.19" - wire \main_sdram_en1 - attribute \src "ls180.v:800.6-800.30" - wire \main_sdram_go_to_refresh - attribute \src "ls180.v:342.13-342.44" - wire width 22 \main_sdram_interface_bank0_addr - attribute \src "ls180.v:343.6-343.37" - wire \main_sdram_interface_bank0_lock - attribute \src "ls180.v:345.6-345.44" - wire \main_sdram_interface_bank0_rdata_valid - attribute \src "ls180.v:340.6-340.38" - wire \main_sdram_interface_bank0_ready - attribute \src "ls180.v:339.6-339.38" - wire \main_sdram_interface_bank0_valid - attribute \src "ls180.v:344.6-344.44" - wire \main_sdram_interface_bank0_wdata_ready - attribute \src "ls180.v:341.6-341.35" - wire \main_sdram_interface_bank0_we - attribute \src "ls180.v:349.13-349.44" - wire width 22 \main_sdram_interface_bank1_addr - attribute \src "ls180.v:350.6-350.37" - wire \main_sdram_interface_bank1_lock - attribute \src "ls180.v:352.6-352.44" - wire \main_sdram_interface_bank1_rdata_valid - attribute \src "ls180.v:347.6-347.38" - wire \main_sdram_interface_bank1_ready - attribute \src "ls180.v:346.6-346.38" - wire \main_sdram_interface_bank1_valid - attribute \src "ls180.v:351.6-351.44" - wire \main_sdram_interface_bank1_wdata_ready - attribute \src "ls180.v:348.6-348.35" - wire \main_sdram_interface_bank1_we - attribute \src "ls180.v:356.13-356.44" - wire width 22 \main_sdram_interface_bank2_addr - attribute \src "ls180.v:357.6-357.37" - wire \main_sdram_interface_bank2_lock - attribute \src "ls180.v:359.6-359.44" - wire \main_sdram_interface_bank2_rdata_valid - attribute \src "ls180.v:354.6-354.38" - wire \main_sdram_interface_bank2_ready - attribute \src "ls180.v:353.6-353.38" - wire \main_sdram_interface_bank2_valid - attribute \src "ls180.v:358.6-358.44" - wire \main_sdram_interface_bank2_wdata_ready - attribute \src "ls180.v:355.6-355.35" - wire \main_sdram_interface_bank2_we - attribute \src "ls180.v:363.13-363.44" - wire width 22 \main_sdram_interface_bank3_addr - attribute \src "ls180.v:364.6-364.37" - wire \main_sdram_interface_bank3_lock - attribute \src "ls180.v:366.6-366.44" - wire \main_sdram_interface_bank3_rdata_valid - attribute \src "ls180.v:361.6-361.38" - wire \main_sdram_interface_bank3_ready - attribute \src "ls180.v:360.6-360.38" - wire \main_sdram_interface_bank3_valid - attribute \src "ls180.v:365.6-365.44" - wire \main_sdram_interface_bank3_wdata_ready - attribute \src "ls180.v:362.6-362.35" - wire \main_sdram_interface_bank3_we - attribute \src "ls180.v:369.13-369.39" - wire width 16 \main_sdram_interface_rdata - attribute \src "ls180.v:367.12-367.38" - wire width 16 \main_sdram_interface_wdata - attribute \src "ls180.v:368.11-368.40" - wire width 2 \main_sdram_interface_wdata_we - attribute \src "ls180.v:280.5-280.29" - wire \main_sdram_inti_p0_act_n - attribute \src "ls180.v:271.13-271.39" - wire width 13 \main_sdram_inti_p0_address - attribute \src "ls180.v:272.12-272.35" - wire width 2 \main_sdram_inti_p0_bank - attribute \src "ls180.v:273.5-273.29" - wire \main_sdram_inti_p0_cas_n - attribute \src "ls180.v:277.6-277.28" - wire \main_sdram_inti_p0_cke - attribute \src "ls180.v:274.5-274.28" - wire \main_sdram_inti_p0_cs_n - attribute \src "ls180.v:278.6-278.28" - wire \main_sdram_inti_p0_odt - attribute \src "ls180.v:275.5-275.29" - wire \main_sdram_inti_p0_ras_n - attribute \src "ls180.v:285.12-285.37" - wire width 16 \main_sdram_inti_p0_rddata - attribute \src "ls180.v:284.6-284.34" - wire \main_sdram_inti_p0_rddata_en - attribute \src "ls180.v:286.5-286.36" - wire \main_sdram_inti_p0_rddata_valid - attribute \src "ls180.v:279.6-279.32" - wire \main_sdram_inti_p0_reset_n - attribute \src "ls180.v:276.5-276.28" - wire \main_sdram_inti_p0_we_n - attribute \src "ls180.v:281.13-281.38" - wire width 16 \main_sdram_inti_p0_wrdata - attribute \src "ls180.v:282.6-282.34" - wire \main_sdram_inti_p0_wrdata_en - attribute \src "ls180.v:283.12-283.42" - wire width 2 \main_sdram_inti_p0_wrdata_mask - attribute \src "ls180.v:312.5-312.31" - wire \main_sdram_master_p0_act_n - attribute \src "ls180.v:303.12-303.40" - wire width 13 \main_sdram_master_p0_address - attribute \src "ls180.v:304.11-304.36" - wire width 2 \main_sdram_master_p0_bank - attribute \src "ls180.v:305.5-305.31" - wire \main_sdram_master_p0_cas_n - attribute \src "ls180.v:309.5-309.29" - wire \main_sdram_master_p0_cke - attribute \src "ls180.v:306.5-306.30" - wire \main_sdram_master_p0_cs_n - attribute \src "ls180.v:310.5-310.29" - wire \main_sdram_master_p0_odt - attribute \src "ls180.v:307.5-307.31" - wire \main_sdram_master_p0_ras_n - attribute \src "ls180.v:317.13-317.40" - wire width 16 \main_sdram_master_p0_rddata - attribute \src "ls180.v:316.5-316.35" - wire \main_sdram_master_p0_rddata_en - attribute \src "ls180.v:318.6-318.39" - wire \main_sdram_master_p0_rddata_valid - attribute \src "ls180.v:311.5-311.33" - wire \main_sdram_master_p0_reset_n - attribute \src "ls180.v:308.5-308.30" - wire \main_sdram_master_p0_we_n - attribute \src "ls180.v:313.12-313.39" - wire width 16 \main_sdram_master_p0_wrdata - attribute \src "ls180.v:314.5-314.35" - wire \main_sdram_master_p0_wrdata_en - attribute \src "ls180.v:315.11-315.43" - wire width 2 \main_sdram_master_p0_wrdata_mask - attribute \src "ls180.v:795.6-795.26" - wire \main_sdram_max_time0 - attribute \src "ls180.v:798.6-798.26" - wire \main_sdram_max_time1 - attribute \src "ls180.v:777.12-777.28" - wire width 13 \main_sdram_nop_a - attribute \src "ls180.v:778.11-778.28" - wire width 2 \main_sdram_nop_ba - attribute \src "ls180.v:321.6-321.20" - wire \main_sdram_odt - attribute \src "ls180.v:404.5-404.31" - wire \main_sdram_postponer_count - attribute \src "ls180.v:402.6-402.32" - wire \main_sdram_postponer_req_i - attribute \src "ls180.v:403.5-403.31" - wire \main_sdram_postponer_req_o - attribute \src "ls180.v:739.6-739.28" - wire \main_sdram_ras_allowed - attribute \src "ls180.v:324.5-324.18" - wire \main_sdram_re - attribute \src "ls180.v:792.6-792.31" - wire \main_sdram_read_available - attribute \src "ls180.v:322.6-322.24" - wire \main_sdram_reset_n - attribute \src "ls180.v:319.6-319.20" - wire \main_sdram_sel - attribute \src "ls180.v:410.5-410.31" - wire \main_sdram_sequencer_count - attribute \src "ls180.v:409.11-409.39" - wire width 4 \main_sdram_sequencer_counter - attribute \src "ls180.v:406.6-406.32" - wire \main_sdram_sequencer_done0 - attribute \src "ls180.v:408.5-408.31" - wire \main_sdram_sequencer_done1 - attribute \src "ls180.v:405.5-405.32" - wire \main_sdram_sequencer_start0 - attribute \src "ls180.v:407.6-407.33" - wire \main_sdram_sequencer_start1 - attribute \src "ls180.v:296.6-296.31" - wire \main_sdram_slave_p0_act_n - attribute \src "ls180.v:287.13-287.40" - wire width 13 \main_sdram_slave_p0_address - attribute \src "ls180.v:288.12-288.36" - wire width 2 \main_sdram_slave_p0_bank - attribute \src "ls180.v:289.6-289.31" - wire \main_sdram_slave_p0_cas_n - attribute \src "ls180.v:293.6-293.29" - wire \main_sdram_slave_p0_cke - attribute \src "ls180.v:290.6-290.30" - wire \main_sdram_slave_p0_cs_n - attribute \src "ls180.v:294.6-294.29" - wire \main_sdram_slave_p0_odt - attribute \src "ls180.v:291.6-291.31" - wire \main_sdram_slave_p0_ras_n - attribute \src "ls180.v:301.12-301.38" - wire width 16 \main_sdram_slave_p0_rddata - attribute \src "ls180.v:300.6-300.35" - wire \main_sdram_slave_p0_rddata_en - attribute \src "ls180.v:302.5-302.37" - wire \main_sdram_slave_p0_rddata_valid - attribute \src "ls180.v:295.6-295.33" - wire \main_sdram_slave_p0_reset_n - attribute \src "ls180.v:292.6-292.30" - wire \main_sdram_slave_p0_we_n - attribute \src "ls180.v:297.13-297.39" - wire width 16 \main_sdram_slave_p0_wrdata - attribute \src "ls180.v:298.6-298.35" - wire \main_sdram_slave_p0_wrdata_en - attribute \src "ls180.v:299.12-299.43" - wire width 2 \main_sdram_slave_p0_wrdata_mask - attribute \src "ls180.v:337.12-337.29" - wire width 16 \main_sdram_status - attribute \src "ls180.v:780.5-780.24" - wire \main_sdram_steerer0 - attribute \src "ls180.v:781.5-781.24" - wire \main_sdram_steerer1 - attribute \src "ls180.v:779.11-779.33" - wire width 2 \main_sdram_steerer_sel - attribute \src "ls180.v:323.11-323.29" - wire width 4 \main_sdram_storage - attribute \src "ls180.v:788.5-788.29" - wire \main_sdram_tccdcon_count + wire \sdram_interface_bank1_lock + attribute \src "ls180.v:330.6-330.39" + wire \sdram_interface_bank1_rdata_valid + attribute \src "ls180.v:325.6-325.33" + wire \sdram_interface_bank1_ready + attribute \src "ls180.v:324.6-324.33" + wire \sdram_interface_bank1_valid + attribute \src "ls180.v:329.6-329.39" + wire \sdram_interface_bank1_wdata_ready + attribute \src "ls180.v:326.6-326.30" + wire \sdram_interface_bank1_we + attribute \src "ls180.v:334.13-334.39" + wire width 22 \sdram_interface_bank2_addr + attribute \src "ls180.v:335.6-335.32" + wire \sdram_interface_bank2_lock + attribute \src "ls180.v:337.6-337.39" + wire \sdram_interface_bank2_rdata_valid + attribute \src "ls180.v:332.6-332.33" + wire \sdram_interface_bank2_ready + attribute \src "ls180.v:331.6-331.33" + wire \sdram_interface_bank2_valid + attribute \src "ls180.v:336.6-336.39" + wire \sdram_interface_bank2_wdata_ready + attribute \src "ls180.v:333.6-333.30" + wire \sdram_interface_bank2_we + attribute \src "ls180.v:341.13-341.39" + wire width 22 \sdram_interface_bank3_addr + attribute \src "ls180.v:342.6-342.32" + wire \sdram_interface_bank3_lock + attribute \src "ls180.v:344.6-344.39" + wire \sdram_interface_bank3_rdata_valid + attribute \src "ls180.v:339.6-339.33" + wire \sdram_interface_bank3_ready + attribute \src "ls180.v:338.6-338.33" + wire \sdram_interface_bank3_valid + attribute \src "ls180.v:343.6-343.39" + wire \sdram_interface_bank3_wdata_ready + attribute \src "ls180.v:340.6-340.30" + wire \sdram_interface_bank3_we + attribute \src "ls180.v:347.13-347.34" + wire width 16 \sdram_interface_rdata + attribute \src "ls180.v:345.12-345.33" + wire width 16 \sdram_interface_wdata + attribute \src "ls180.v:346.11-346.35" + wire width 2 \sdram_interface_wdata_we + attribute \src "ls180.v:258.5-258.24" + wire \sdram_inti_p0_act_n + attribute \src "ls180.v:249.13-249.34" + wire width 13 \sdram_inti_p0_address + attribute \src "ls180.v:250.12-250.30" + wire width 2 \sdram_inti_p0_bank + attribute \src "ls180.v:251.5-251.24" + wire \sdram_inti_p0_cas_n + attribute \src "ls180.v:255.6-255.23" + wire \sdram_inti_p0_cke + attribute \src "ls180.v:252.5-252.23" + wire \sdram_inti_p0_cs_n + attribute \src "ls180.v:256.6-256.23" + wire \sdram_inti_p0_odt + attribute \src "ls180.v:253.5-253.24" + wire \sdram_inti_p0_ras_n + attribute \src "ls180.v:263.12-263.32" + wire width 16 \sdram_inti_p0_rddata + attribute \src "ls180.v:262.6-262.29" + wire \sdram_inti_p0_rddata_en + attribute \src "ls180.v:264.5-264.31" + wire \sdram_inti_p0_rddata_valid + attribute \src "ls180.v:257.6-257.27" + wire \sdram_inti_p0_reset_n + attribute \src "ls180.v:254.5-254.23" + wire \sdram_inti_p0_we_n + attribute \src "ls180.v:259.13-259.33" + wire width 16 \sdram_inti_p0_wrdata + attribute \src "ls180.v:260.6-260.29" + wire \sdram_inti_p0_wrdata_en + attribute \src "ls180.v:261.12-261.37" + wire width 2 \sdram_inti_p0_wrdata_mask + attribute \src "ls180.v:290.5-290.26" + wire \sdram_master_p0_act_n + attribute \src "ls180.v:281.12-281.35" + wire width 13 \sdram_master_p0_address + attribute \src "ls180.v:282.11-282.31" + wire width 2 \sdram_master_p0_bank + attribute \src "ls180.v:283.5-283.26" + wire \sdram_master_p0_cas_n + attribute \src "ls180.v:287.5-287.24" + wire \sdram_master_p0_cke + attribute \src "ls180.v:284.5-284.25" + wire \sdram_master_p0_cs_n + attribute \src "ls180.v:288.5-288.24" + wire \sdram_master_p0_odt + attribute \src "ls180.v:285.5-285.26" + wire \sdram_master_p0_ras_n + attribute \src "ls180.v:295.13-295.35" + wire width 16 \sdram_master_p0_rddata + attribute \src "ls180.v:294.5-294.30" + wire \sdram_master_p0_rddata_en + attribute \src "ls180.v:296.6-296.34" + wire \sdram_master_p0_rddata_valid + attribute \src "ls180.v:289.5-289.28" + wire \sdram_master_p0_reset_n + attribute \src "ls180.v:286.5-286.25" + wire \sdram_master_p0_we_n + attribute \src "ls180.v:291.12-291.34" + wire width 16 \sdram_master_p0_wrdata + attribute \src "ls180.v:292.5-292.30" + wire \sdram_master_p0_wrdata_en + attribute \src "ls180.v:293.11-293.38" + wire width 2 \sdram_master_p0_wrdata_mask + attribute \src "ls180.v:773.6-773.21" + wire \sdram_max_time0 + attribute \src "ls180.v:776.6-776.21" + wire \sdram_max_time1 + attribute \src "ls180.v:755.12-755.23" + wire width 13 \sdram_nop_a + attribute \src "ls180.v:756.11-756.23" + wire width 2 \sdram_nop_ba + attribute \src "ls180.v:299.6-299.15" + wire \sdram_odt + attribute \src "ls180.v:382.5-382.26" + wire \sdram_postponer_count + attribute \src "ls180.v:380.6-380.27" + wire \sdram_postponer_req_i + attribute \src "ls180.v:381.5-381.26" + wire \sdram_postponer_req_o + attribute \src "ls180.v:717.6-717.23" + wire \sdram_ras_allowed + attribute \src "ls180.v:20.14-20.25" + wire output 16 \sdram_ras_n + attribute \src "ls180.v:302.5-302.13" + wire \sdram_re + attribute \src "ls180.v:770.6-770.26" + wire \sdram_read_available + attribute \src "ls180.v:300.6-300.19" + wire \sdram_reset_n + attribute \src "ls180.v:297.6-297.15" + wire \sdram_sel + attribute \src "ls180.v:388.5-388.26" + wire \sdram_sequencer_count + attribute \src "ls180.v:387.11-387.34" + wire width 4 \sdram_sequencer_counter + attribute \src "ls180.v:384.6-384.27" + wire \sdram_sequencer_done0 + attribute \src "ls180.v:386.5-386.26" + wire \sdram_sequencer_done1 + attribute \src "ls180.v:383.5-383.27" + wire \sdram_sequencer_start0 + attribute \src "ls180.v:385.6-385.28" + wire \sdram_sequencer_start1 + attribute \src "ls180.v:274.6-274.26" + wire \sdram_slave_p0_act_n + attribute \src "ls180.v:265.13-265.35" + wire width 13 \sdram_slave_p0_address + attribute \src "ls180.v:266.12-266.31" + wire width 2 \sdram_slave_p0_bank + attribute \src "ls180.v:267.6-267.26" + wire \sdram_slave_p0_cas_n + attribute \src "ls180.v:271.6-271.24" + wire \sdram_slave_p0_cke + attribute \src "ls180.v:268.6-268.25" + wire \sdram_slave_p0_cs_n + attribute \src "ls180.v:272.6-272.24" + wire \sdram_slave_p0_odt + attribute \src "ls180.v:269.6-269.26" + wire \sdram_slave_p0_ras_n + attribute \src "ls180.v:279.12-279.33" + wire width 16 \sdram_slave_p0_rddata + attribute \src "ls180.v:278.6-278.30" + wire \sdram_slave_p0_rddata_en + attribute \src "ls180.v:280.5-280.32" + wire \sdram_slave_p0_rddata_valid + attribute \src "ls180.v:273.6-273.28" + wire \sdram_slave_p0_reset_n + attribute \src "ls180.v:270.6-270.25" + wire \sdram_slave_p0_we_n + attribute \src "ls180.v:275.13-275.34" + wire width 16 \sdram_slave_p0_wrdata + attribute \src "ls180.v:276.6-276.30" + wire \sdram_slave_p0_wrdata_en + attribute \src "ls180.v:277.12-277.38" + wire width 2 \sdram_slave_p0_wrdata_mask + attribute \src "ls180.v:315.12-315.24" + wire width 16 \sdram_status + attribute \src "ls180.v:758.5-758.19" + wire \sdram_steerer0 + attribute \src "ls180.v:759.5-759.19" + wire \sdram_steerer1 + attribute \src "ls180.v:757.11-757.28" + wire width 2 \sdram_steerer_sel + attribute \src "ls180.v:301.11-301.24" + wire width 4 \sdram_storage + attribute \src "ls180.v:766.5-766.24" + wire \sdram_tccdcon_count attribute \no_retiming "true" - attribute \src "ls180.v:787.32-787.56" - wire \main_sdram_tccdcon_ready - attribute \src "ls180.v:786.6-786.30" - wire \main_sdram_tccdcon_valid + attribute \src "ls180.v:765.32-765.51" + wire \sdram_tccdcon_ready + attribute \src "ls180.v:764.6-764.25" + wire \sdram_tccdcon_valid attribute \no_retiming "true" - attribute \src "ls180.v:785.32-785.56" - wire \main_sdram_tfawcon_ready - attribute \src "ls180.v:784.6-784.30" - wire \main_sdram_tfawcon_valid - attribute \src "ls180.v:796.11-796.27" - wire width 5 \main_sdram_time0 - attribute \src "ls180.v:799.11-799.27" - wire width 4 \main_sdram_time1 - attribute \src "ls180.v:399.12-399.35" - wire width 10 \main_sdram_timer_count0 - attribute \src "ls180.v:401.11-401.34" - wire width 10 \main_sdram_timer_count1 - attribute \src "ls180.v:398.6-398.28" - wire \main_sdram_timer_done0 - attribute \src "ls180.v:400.6-400.28" - wire \main_sdram_timer_done1 - attribute \src "ls180.v:397.6-397.27" - wire \main_sdram_timer_wait + attribute \src "ls180.v:763.32-763.51" + wire \sdram_tfawcon_ready + attribute \src "ls180.v:762.6-762.25" + wire \sdram_tfawcon_valid + attribute \src "ls180.v:774.11-774.22" + wire width 5 \sdram_time0 + attribute \src "ls180.v:777.11-777.22" + wire width 4 \sdram_time1 + attribute \src "ls180.v:377.12-377.30" + wire width 10 \sdram_timer_count0 + attribute \src "ls180.v:379.11-379.29" + wire width 10 \sdram_timer_count1 + attribute \src "ls180.v:376.6-376.23" + wire \sdram_timer_done0 + attribute \src "ls180.v:378.6-378.23" + wire \sdram_timer_done1 + attribute \src "ls180.v:375.6-375.22" + wire \sdram_timer_wait attribute \no_retiming "true" - attribute \src "ls180.v:783.32-783.56" - wire \main_sdram_trrdcon_ready - attribute \src "ls180.v:782.6-782.30" - wire \main_sdram_trrdcon_valid - attribute \src "ls180.v:791.11-791.35" - wire width 3 \main_sdram_twtrcon_count + attribute \src "ls180.v:761.32-761.51" + wire \sdram_trrdcon_ready + attribute \src "ls180.v:760.6-760.25" + wire \sdram_trrdcon_valid + attribute \src "ls180.v:769.11-769.30" + wire width 3 \sdram_twtrcon_count attribute \no_retiming "true" - attribute \src "ls180.v:790.32-790.56" - wire \main_sdram_twtrcon_ready - attribute \src "ls180.v:789.6-789.30" - wire \main_sdram_twtrcon_valid - attribute \src "ls180.v:396.6-396.30" - wire \main_sdram_wants_refresh - attribute \src "ls180.v:338.6-338.19" - wire \main_sdram_we - attribute \src "ls180.v:336.5-336.25" - wire \main_sdram_wrdata_re - attribute \src "ls180.v:335.12-335.37" - wire width 16 \main_sdram_wrdata_storage - attribute \src "ls180.v:793.6-793.32" - wire \main_sdram_write_available - attribute \src "ls180.v:828.5-828.47" - wire \main_socbushandler_converted_interface_ack - attribute \src "ls180.v:822.13-822.55" - wire width 30 \main_socbushandler_converted_interface_adr - attribute \src "ls180.v:831.12-831.54" - wire width 2 \main_socbushandler_converted_interface_bte - attribute \src "ls180.v:830.12-830.54" - wire width 3 \main_socbushandler_converted_interface_cti - attribute \src "ls180.v:826.6-826.48" - wire \main_socbushandler_converted_interface_cyc - attribute \src "ls180.v:824.13-824.57" - wire width 64 \main_socbushandler_converted_interface_dat_r - attribute \src "ls180.v:823.13-823.57" - wire width 64 \main_socbushandler_converted_interface_dat_w - attribute \src "ls180.v:832.5-832.47" - wire \main_socbushandler_converted_interface_err - attribute \src "ls180.v:825.12-825.54" - wire width 8 \main_socbushandler_converted_interface_sel - attribute \src "ls180.v:827.6-827.48" - wire \main_socbushandler_converted_interface_stb - attribute \src "ls180.v:829.6-829.47" - wire \main_socbushandler_converted_interface_we - attribute \src "ls180.v:834.5-834.31" - wire \main_socbushandler_counter - attribute \src "ls180.v:1763.5-1763.53" - wire \main_socbushandler_counter_converter2_next_value - attribute \src "ls180.v:1764.5-1764.56" - wire \main_socbushandler_counter_converter2_next_value_ce - attribute \src "ls180.v:836.12-836.36" - wire width 64 \main_socbushandler_dat_r - attribute \src "ls180.v:835.6-835.30" - wire \main_socbushandler_reset - attribute \src "ls180.v:833.5-833.28" - wire \main_socbushandler_skip - attribute \src "ls180.v:1011.6-1011.27" - wire \main_spimaster0_start - attribute \src "ls180.v:1021.12-1021.35" - wire width 8 \main_spimaster10_length - attribute \src "ls180.v:1022.12-1022.36" - wire width 16 \main_spimaster11_storage - attribute \src "ls180.v:1023.5-1023.24" - wire \main_spimaster12_re - attribute \src "ls180.v:1024.6-1024.27" - wire \main_spimaster13_done - attribute \src "ls180.v:1025.6-1025.29" - wire \main_spimaster14_status - attribute \src "ls180.v:1026.6-1026.25" - wire \main_spimaster15_we - attribute \src "ls180.v:1027.11-1027.35" - wire width 8 \main_spimaster16_storage - attribute \src "ls180.v:1028.5-1028.24" - wire \main_spimaster17_re - attribute \src "ls180.v:1029.12-1029.35" - wire width 8 \main_spimaster18_status - attribute \src "ls180.v:1030.6-1030.25" - wire \main_spimaster19_we - attribute \src "ls180.v:1012.12-1012.34" - wire width 8 \main_spimaster1_length - attribute \src "ls180.v:1084.5-1084.23" - wire \main_spimaster1_re - attribute \src "ls180.v:1083.12-1083.35" - wire width 16 \main_spimaster1_storage - attribute \src "ls180.v:1031.6-1031.26" - wire \main_spimaster20_sel - attribute \src "ls180.v:1032.5-1032.29" - wire \main_spimaster21_storage - attribute \src "ls180.v:1033.5-1033.24" - wire \main_spimaster22_re - attribute \src "ls180.v:1034.5-1034.29" - wire \main_spimaster23_storage - attribute \src "ls180.v:1035.5-1035.24" - wire \main_spimaster24_re - attribute \src "ls180.v:1036.5-1036.32" - wire \main_spimaster25_clk_enable - attribute \src "ls180.v:1037.5-1037.31" - wire \main_spimaster26_cs_enable - attribute \src "ls180.v:1038.11-1038.33" - wire width 3 \main_spimaster27_count - attribute \src "ls180.v:1804.11-1804.55" - wire width 3 \main_spimaster27_count_spimaster0_next_value - attribute \src "ls180.v:1805.5-1805.52" - wire \main_spimaster27_count_spimaster0_next_value_ce - attribute \src "ls180.v:1039.5-1039.32" - wire \main_spimaster28_mosi_latch - attribute \src "ls180.v:1040.5-1040.32" - wire \main_spimaster29_miso_latch - attribute \src "ls180.v:1013.5-1013.25" - wire \main_spimaster2_done - attribute \src "ls180.v:1041.12-1041.40" - wire width 16 \main_spimaster30_clk_divider - attribute \src "ls180.v:1042.6-1042.31" - wire \main_spimaster31_clk_rise - attribute \src "ls180.v:1043.6-1043.31" - wire \main_spimaster32_clk_fall - attribute \src "ls180.v:1044.11-1044.37" - wire width 8 \main_spimaster33_mosi_data - attribute \src "ls180.v:1045.11-1045.36" - wire width 3 \main_spimaster34_mosi_sel - attribute \src "ls180.v:1046.11-1046.37" - wire width 8 \main_spimaster35_miso_data - attribute \src "ls180.v:1014.5-1014.24" - wire \main_spimaster3_irq - attribute \src "ls180.v:1015.12-1015.32" - wire width 8 \main_spimaster4_mosi - attribute \src "ls180.v:1016.11-1016.31" - wire width 8 \main_spimaster5_miso - attribute \src "ls180.v:1017.6-1017.24" - wire \main_spimaster6_cs - attribute \src "ls180.v:1018.6-1018.30" - wire \main_spimaster7_loopback - attribute \src "ls180.v:1019.12-1019.39" - wire width 16 \main_spimaster8_clk_divider - attribute \src "ls180.v:1020.5-1020.26" - wire \main_spimaster9_start - attribute \src "ls180.v:1055.13-1055.40" - wire width 16 \main_spisdcard_clk_divider0 - attribute \src "ls180.v:1077.12-1077.39" - wire width 16 \main_spisdcard_clk_divider1 - attribute \src "ls180.v:1072.5-1072.30" - wire \main_spisdcard_clk_enable - attribute \src "ls180.v:1079.6-1079.29" - wire \main_spisdcard_clk_fall - attribute \src "ls180.v:1078.6-1078.29" - wire \main_spisdcard_clk_rise - attribute \src "ls180.v:1059.5-1059.30" - wire \main_spisdcard_control_re - attribute \src "ls180.v:1058.12-1058.42" - wire width 16 \main_spisdcard_control_storage - attribute \src "ls180.v:1074.11-1074.31" - wire width 3 \main_spisdcard_count - attribute \src "ls180.v:1808.11-1808.53" - wire width 3 \main_spisdcard_count_spimaster1_next_value - attribute \src "ls180.v:1809.5-1809.50" - wire \main_spisdcard_count_spimaster1_next_value_ce - attribute \src "ls180.v:1053.6-1053.23" - wire \main_spisdcard_cs - attribute \src "ls180.v:1073.5-1073.29" - wire \main_spisdcard_cs_enable - attribute \src "ls180.v:1069.5-1069.25" - wire \main_spisdcard_cs_re - attribute \src "ls180.v:1068.5-1068.30" - wire \main_spisdcard_cs_storage - attribute \src "ls180.v:1049.5-1049.25" - wire \main_spisdcard_done0 - attribute \src "ls180.v:1060.6-1060.26" - wire \main_spisdcard_done1 - attribute \src "ls180.v:1050.5-1050.23" - wire \main_spisdcard_irq - attribute \src "ls180.v:1048.12-1048.34" - wire width 8 \main_spisdcard_length0 - attribute \src "ls180.v:1057.12-1057.34" - wire width 8 \main_spisdcard_length1 - attribute \src "ls180.v:1054.6-1054.29" - wire \main_spisdcard_loopback - attribute \src "ls180.v:1071.5-1071.31" - wire \main_spisdcard_loopback_re - attribute \src "ls180.v:1070.5-1070.36" - wire \main_spisdcard_loopback_storage - attribute \src "ls180.v:1052.11-1052.30" - wire width 8 \main_spisdcard_miso - attribute \src "ls180.v:1082.11-1082.35" - wire width 8 \main_spisdcard_miso_data - attribute \src "ls180.v:1076.5-1076.30" - wire \main_spisdcard_miso_latch - attribute \src "ls180.v:1065.12-1065.38" - wire width 8 \main_spisdcard_miso_status - attribute \src "ls180.v:1066.6-1066.28" - wire \main_spisdcard_miso_we - attribute \src "ls180.v:1051.12-1051.31" - wire width 8 \main_spisdcard_mosi - attribute \src "ls180.v:1080.11-1080.35" - wire width 8 \main_spisdcard_mosi_data - attribute \src "ls180.v:1075.5-1075.30" - wire \main_spisdcard_mosi_latch - attribute \src "ls180.v:1064.5-1064.27" - wire \main_spisdcard_mosi_re - attribute \src "ls180.v:1081.11-1081.34" - wire width 3 \main_spisdcard_mosi_sel - attribute \src "ls180.v:1063.11-1063.38" - wire width 8 \main_spisdcard_mosi_storage - attribute \src "ls180.v:1067.6-1067.24" - wire \main_spisdcard_sel - attribute \src "ls180.v:1047.6-1047.27" - wire \main_spisdcard_start0 - attribute \src "ls180.v:1056.5-1056.26" - wire \main_spisdcard_start1 - attribute \src "ls180.v:1061.6-1061.34" - wire \main_spisdcard_status_status - attribute \src "ls180.v:1062.6-1062.30" - wire \main_spisdcard_status_we - attribute \src "ls180.v:902.12-902.44" - wire width 2 \main_uart_eventmanager_pending_r - attribute \src "ls180.v:901.6-901.39" - wire \main_uart_eventmanager_pending_re - attribute \src "ls180.v:904.11-904.43" - wire width 2 \main_uart_eventmanager_pending_w - attribute \src "ls180.v:903.6-903.39" - wire \main_uart_eventmanager_pending_we - attribute \src "ls180.v:906.5-906.30" - wire \main_uart_eventmanager_re - attribute \src "ls180.v:898.12-898.43" - wire width 2 \main_uart_eventmanager_status_r - attribute \src "ls180.v:897.6-897.38" - wire \main_uart_eventmanager_status_re - attribute \src "ls180.v:900.11-900.42" - wire width 2 \main_uart_eventmanager_status_w - attribute \src "ls180.v:899.6-899.38" - wire \main_uart_eventmanager_status_we - attribute \src "ls180.v:905.11-905.41" - wire width 2 \main_uart_eventmanager_storage - attribute \src "ls180.v:886.6-886.19" - wire \main_uart_irq - attribute \src "ls180.v:872.12-872.46" - wire width 32 \main_uart_phy_phase_accumulator_rx - attribute \src "ls180.v:862.12-862.46" - wire width 32 \main_uart_phy_phase_accumulator_tx - attribute \src "ls180.v:855.5-855.21" - wire \main_uart_phy_re - attribute \src "ls180.v:873.6-873.22" - wire \main_uart_phy_rx - attribute \src "ls180.v:876.11-876.36" - wire width 4 \main_uart_phy_rx_bitcount - attribute \src "ls180.v:877.5-877.26" - wire \main_uart_phy_rx_busy - attribute \src "ls180.v:874.5-874.23" - wire \main_uart_phy_rx_r - attribute \src "ls180.v:875.11-875.31" - wire width 8 \main_uart_phy_rx_reg - attribute \src "ls180.v:858.6-858.30" - wire \main_uart_phy_sink_first - attribute \src "ls180.v:859.6-859.29" - wire \main_uart_phy_sink_last - attribute \src "ls180.v:860.12-860.43" - wire width 8 \main_uart_phy_sink_payload_data - attribute \src "ls180.v:857.5-857.29" - wire \main_uart_phy_sink_ready - attribute \src "ls180.v:856.6-856.30" - wire \main_uart_phy_sink_valid - attribute \src "ls180.v:868.5-868.31" - wire \main_uart_phy_source_first - attribute \src "ls180.v:869.5-869.30" - wire \main_uart_phy_source_last - attribute \src "ls180.v:870.11-870.44" - wire width 8 \main_uart_phy_source_payload_data - attribute \src "ls180.v:867.6-867.32" - wire \main_uart_phy_source_ready - attribute \src "ls180.v:866.5-866.31" - wire \main_uart_phy_source_valid - attribute \src "ls180.v:854.12-854.33" - wire width 32 \main_uart_phy_storage - attribute \src "ls180.v:864.11-864.36" - wire width 4 \main_uart_phy_tx_bitcount - attribute \src "ls180.v:865.5-865.26" - wire \main_uart_phy_tx_busy - attribute \src "ls180.v:863.11-863.31" - wire width 8 \main_uart_phy_tx_reg - attribute \src "ls180.v:871.5-871.32" - wire \main_uart_phy_uart_clk_rxen - attribute \src "ls180.v:861.5-861.32" - wire \main_uart_phy_uart_clk_txen - attribute \src "ls180.v:995.5-995.20" - wire \main_uart_reset - attribute \src "ls180.v:895.5-895.23" - wire \main_uart_rx_clear - attribute \src "ls180.v:979.11-979.36" - wire width 4 \main_uart_rx_fifo_consume - attribute \src "ls180.v:984.6-984.31" - wire \main_uart_rx_fifo_do_read - attribute \src "ls180.v:990.6-990.37" - wire \main_uart_rx_fifo_fifo_in_first - attribute \src "ls180.v:991.6-991.36" - wire \main_uart_rx_fifo_fifo_in_last - attribute \src "ls180.v:989.12-989.50" - wire width 8 \main_uart_rx_fifo_fifo_in_payload_data - attribute \src "ls180.v:993.6-993.38" - wire \main_uart_rx_fifo_fifo_out_first - attribute \src "ls180.v:994.6-994.37" - wire \main_uart_rx_fifo_fifo_out_last - attribute \src "ls180.v:992.12-992.51" - wire width 8 \main_uart_rx_fifo_fifo_out_payload_data - attribute \src "ls180.v:976.11-976.35" - wire width 5 \main_uart_rx_fifo_level0 - attribute \src "ls180.v:988.12-988.36" - wire width 5 \main_uart_rx_fifo_level1 - attribute \src "ls180.v:978.11-978.36" - wire width 4 \main_uart_rx_fifo_produce - attribute \src "ls180.v:985.12-985.40" - wire width 4 \main_uart_rx_fifo_rdport_adr - attribute \src "ls180.v:986.12-986.42" - wire width 10 \main_uart_rx_fifo_rdport_dat_r - attribute \src "ls180.v:987.6-987.33" - wire \main_uart_rx_fifo_rdport_re - attribute \src "ls180.v:968.6-968.26" - wire \main_uart_rx_fifo_re - attribute \src "ls180.v:969.5-969.31" - wire \main_uart_rx_fifo_readable - attribute \src "ls180.v:977.5-977.30" - wire \main_uart_rx_fifo_replace - attribute \src "ls180.v:960.6-960.34" - wire \main_uart_rx_fifo_sink_first - attribute \src "ls180.v:961.6-961.33" - wire \main_uart_rx_fifo_sink_last - attribute \src "ls180.v:962.12-962.47" - wire width 8 \main_uart_rx_fifo_sink_payload_data - attribute \src "ls180.v:959.6-959.34" - wire \main_uart_rx_fifo_sink_ready - attribute \src "ls180.v:958.6-958.34" - wire \main_uart_rx_fifo_sink_valid - attribute \src "ls180.v:965.6-965.36" - wire \main_uart_rx_fifo_source_first - attribute \src "ls180.v:966.6-966.35" - wire \main_uart_rx_fifo_source_last - attribute \src "ls180.v:967.12-967.49" - wire width 8 \main_uart_rx_fifo_source_payload_data - attribute \src "ls180.v:964.6-964.36" - wire \main_uart_rx_fifo_source_ready - attribute \src "ls180.v:963.6-963.36" - wire \main_uart_rx_fifo_source_valid - attribute \src "ls180.v:974.12-974.42" - wire width 10 \main_uart_rx_fifo_syncfifo_din - attribute \src "ls180.v:975.12-975.43" - wire width 10 \main_uart_rx_fifo_syncfifo_dout - attribute \src "ls180.v:972.6-972.35" - wire \main_uart_rx_fifo_syncfifo_re - attribute \src "ls180.v:973.6-973.41" - wire \main_uart_rx_fifo_syncfifo_readable - attribute \src "ls180.v:970.6-970.35" - wire \main_uart_rx_fifo_syncfifo_we - attribute \src "ls180.v:971.6-971.41" - wire \main_uart_rx_fifo_syncfifo_writable - attribute \src "ls180.v:980.11-980.39" - wire width 4 \main_uart_rx_fifo_wrport_adr - attribute \src "ls180.v:981.12-981.42" - wire width 10 \main_uart_rx_fifo_wrport_dat_r - attribute \src "ls180.v:983.12-983.42" - wire width 10 \main_uart_rx_fifo_wrport_dat_w - attribute \src "ls180.v:982.6-982.33" - wire \main_uart_rx_fifo_wrport_we - attribute \src "ls180.v:896.5-896.29" - wire \main_uart_rx_old_trigger - attribute \src "ls180.v:893.5-893.25" - wire \main_uart_rx_pending - attribute \src "ls180.v:892.6-892.25" - wire \main_uart_rx_status - attribute \src "ls180.v:894.6-894.26" - wire \main_uart_rx_trigger - attribute \src "ls180.v:884.6-884.30" - wire \main_uart_rxempty_status - attribute \src "ls180.v:885.6-885.26" - wire \main_uart_rxempty_we - attribute \src "ls180.v:909.6-909.29" - wire \main_uart_rxfull_status - attribute \src "ls180.v:910.6-910.25" - wire \main_uart_rxfull_we - attribute \src "ls180.v:879.12-879.28" - wire width 8 \main_uart_rxtx_r - attribute \src "ls180.v:878.6-878.23" - wire \main_uart_rxtx_re - attribute \src "ls180.v:881.12-881.28" - wire width 8 \main_uart_rxtx_w - attribute \src "ls180.v:880.6-880.23" - wire \main_uart_rxtx_we - attribute \src "ls180.v:890.5-890.23" - wire \main_uart_tx_clear - attribute \src "ls180.v:942.11-942.36" - wire width 4 \main_uart_tx_fifo_consume - attribute \src "ls180.v:947.6-947.31" - wire \main_uart_tx_fifo_do_read - attribute \src "ls180.v:953.6-953.37" - wire \main_uart_tx_fifo_fifo_in_first - attribute \src "ls180.v:954.6-954.36" - wire \main_uart_tx_fifo_fifo_in_last - attribute \src "ls180.v:952.12-952.50" - wire width 8 \main_uart_tx_fifo_fifo_in_payload_data - attribute \src "ls180.v:956.6-956.38" - wire \main_uart_tx_fifo_fifo_out_first - attribute \src "ls180.v:957.6-957.37" - wire \main_uart_tx_fifo_fifo_out_last - attribute \src "ls180.v:955.12-955.51" - wire width 8 \main_uart_tx_fifo_fifo_out_payload_data - attribute \src "ls180.v:939.11-939.35" - wire width 5 \main_uart_tx_fifo_level0 - attribute \src "ls180.v:951.12-951.36" - wire width 5 \main_uart_tx_fifo_level1 - attribute \src "ls180.v:941.11-941.36" - wire width 4 \main_uart_tx_fifo_produce - attribute \src "ls180.v:948.12-948.40" - wire width 4 \main_uart_tx_fifo_rdport_adr - attribute \src "ls180.v:949.12-949.42" - wire width 10 \main_uart_tx_fifo_rdport_dat_r - attribute \src "ls180.v:950.6-950.33" - wire \main_uart_tx_fifo_rdport_re - attribute \src "ls180.v:931.6-931.26" - wire \main_uart_tx_fifo_re - attribute \src "ls180.v:932.5-932.31" - wire \main_uart_tx_fifo_readable - attribute \src "ls180.v:940.5-940.30" - wire \main_uart_tx_fifo_replace - attribute \src "ls180.v:923.5-923.33" - wire \main_uart_tx_fifo_sink_first - attribute \src "ls180.v:924.5-924.32" - wire \main_uart_tx_fifo_sink_last - attribute \src "ls180.v:925.12-925.47" - wire width 8 \main_uart_tx_fifo_sink_payload_data - attribute \src "ls180.v:922.6-922.34" - wire \main_uart_tx_fifo_sink_ready - attribute \src "ls180.v:921.6-921.34" - wire \main_uart_tx_fifo_sink_valid - attribute \src "ls180.v:928.6-928.36" - wire \main_uart_tx_fifo_source_first - attribute \src "ls180.v:929.6-929.35" - wire \main_uart_tx_fifo_source_last - attribute \src "ls180.v:930.12-930.49" - wire width 8 \main_uart_tx_fifo_source_payload_data - attribute \src "ls180.v:927.6-927.36" - wire \main_uart_tx_fifo_source_ready - attribute \src "ls180.v:926.6-926.36" - wire \main_uart_tx_fifo_source_valid - attribute \src "ls180.v:937.12-937.42" - wire width 10 \main_uart_tx_fifo_syncfifo_din - attribute \src "ls180.v:938.12-938.43" - wire width 10 \main_uart_tx_fifo_syncfifo_dout - attribute \src "ls180.v:935.6-935.35" - wire \main_uart_tx_fifo_syncfifo_re - attribute \src "ls180.v:936.6-936.41" - wire \main_uart_tx_fifo_syncfifo_readable - attribute \src "ls180.v:933.6-933.35" - wire \main_uart_tx_fifo_syncfifo_we - attribute \src "ls180.v:934.6-934.41" - wire \main_uart_tx_fifo_syncfifo_writable - attribute \src "ls180.v:943.11-943.39" - wire width 4 \main_uart_tx_fifo_wrport_adr - attribute \src "ls180.v:944.12-944.42" - wire width 10 \main_uart_tx_fifo_wrport_dat_r - attribute \src "ls180.v:946.12-946.42" - wire width 10 \main_uart_tx_fifo_wrport_dat_w - attribute \src "ls180.v:945.6-945.33" - wire \main_uart_tx_fifo_wrport_we - attribute \src "ls180.v:891.5-891.29" - wire \main_uart_tx_old_trigger - attribute \src "ls180.v:888.5-888.25" - wire \main_uart_tx_pending - attribute \src "ls180.v:887.6-887.25" - wire \main_uart_tx_status - attribute \src "ls180.v:889.6-889.26" - wire \main_uart_tx_trigger - attribute \src "ls180.v:907.6-907.30" - wire \main_uart_txempty_status - attribute \src "ls180.v:908.6-908.26" - wire \main_uart_txempty_we - attribute \src "ls180.v:882.6-882.29" - wire \main_uart_txfull_status - attribute \src "ls180.v:883.6-883.25" - wire \main_uart_txfull_we - attribute \src "ls180.v:913.6-913.31" - wire \main_uart_uart_sink_first - attribute \src "ls180.v:914.6-914.30" - wire \main_uart_uart_sink_last - attribute \src "ls180.v:915.12-915.44" - wire width 8 \main_uart_uart_sink_payload_data - attribute \src "ls180.v:912.6-912.31" - wire \main_uart_uart_sink_ready - attribute \src "ls180.v:911.6-911.31" - wire \main_uart_uart_sink_valid - attribute \src "ls180.v:918.6-918.33" - wire \main_uart_uart_source_first - attribute \src "ls180.v:919.6-919.32" - wire \main_uart_uart_source_last - attribute \src "ls180.v:920.12-920.46" - wire width 8 \main_uart_uart_source_payload_data - attribute \src "ls180.v:917.6-917.33" - wire \main_uart_uart_source_ready - attribute \src "ls180.v:916.6-916.33" - wire \main_uart_uart_source_valid - attribute \src "ls180.v:820.5-820.22" - wire \main_wb_sdram_ack - attribute \src "ls180.v:814.12-814.29" - wire width 30 \main_wb_sdram_adr - attribute \src "ls180.v:818.5-818.22" - wire \main_wb_sdram_cyc - attribute \src "ls180.v:816.13-816.32" - wire width 32 \main_wb_sdram_dat_r - attribute \src "ls180.v:815.12-815.31" - wire width 32 \main_wb_sdram_dat_w - attribute \src "ls180.v:817.11-817.28" - wire width 4 \main_wb_sdram_sel - attribute \src "ls180.v:819.5-819.22" - wire \main_wb_sdram_stb - attribute \src "ls180.v:821.5-821.21" - wire \main_wb_sdram_we - attribute \src "ls180.v:850.5-850.24" - wire \main_wdata_consumed - attribute \src "ls180.v:10143.11-10143.17" - wire width 6 \memadr - attribute \src "ls180.v:10171.11-10171.19" - wire width 4 \memadr_1 - attribute \src "ls180.v:10199.12-10199.18" - wire width 25 \memdat - attribute \src "ls180.v:10213.12-10213.20" - wire width 25 \memdat_1 - attribute \src "ls180.v:10227.12-10227.20" - wire width 25 \memdat_2 - attribute \src "ls180.v:10241.12-10241.20" - wire width 25 \memdat_3 - attribute \src "ls180.v:10255.11-10255.19" - wire width 10 \memdat_4 - attribute \src "ls180.v:10256.11-10256.19" - wire width 10 \memdat_5 - attribute \src "ls180.v:10272.11-10272.19" - wire width 10 \memdat_6 - attribute \src "ls180.v:10273.11-10273.19" - wire width 10 \memdat_7 - attribute \src "ls180.v:10289.11-10289.19" - wire width 10 \memdat_8 - attribute \src "ls180.v:10303.11-10303.19" - wire width 10 \memdat_9 - attribute \src "ls180.v:52.20-52.22" - wire width 24 input 48 \nc - attribute \src "ls180.v:252.6-252.13" - wire \por_clk - attribute \src "ls180.v:23.19-23.22" - wire width 2 output 19 \pwm - attribute \src "ls180.v:143.12-143.17" - wire width 2 \pwm_1 - attribute \src "ls180.v:24.13-24.23" - wire output 20 \sdcard_clk - attribute \src "ls180.v:25.14-25.26" - wire output 21 \sdcard_cmd_i - attribute \src "ls180.v:26.13-26.25" - wire output 22 \sdcard_cmd_o - attribute \src "ls180.v:27.13-27.26" - wire output 23 \sdcard_cmd_oe - attribute \src "ls180.v:28.20-28.33" - wire width 4 output 24 \sdcard_data_i - attribute \src "ls180.v:29.19-29.32" - wire width 4 output 25 \sdcard_data_o - attribute \src "ls180.v:30.13-30.27" - wire output 26 \sdcard_data_oe - attribute \src "ls180.v:31.20-31.27" - wire width 13 output 27 \sdram_a - attribute \src "ls180.v:40.19-40.27" - wire width 2 output 36 \sdram_ba - attribute \src "ls180.v:37.13-37.24" - wire output 33 \sdram_cas_n - attribute \src "ls180.v:39.13-39.22" - wire output 35 \sdram_cke - attribute \src "ls180.v:42.13-42.24" - wire output 38 \sdram_clock - attribute \src "ls180.v:162.6-162.19" - wire \sdram_clock_1 - attribute \src "ls180.v:38.13-38.23" - wire output 34 \sdram_cs_n - attribute \src "ls180.v:41.19-41.27" - wire width 2 output 37 \sdram_dm - attribute \src "ls180.v:32.21-32.31" - wire width 16 output 28 \sdram_dq_i - attribute \src "ls180.v:33.20-33.30" - wire width 16 output 29 \sdram_dq_o - attribute \src "ls180.v:34.13-34.24" - wire output 30 \sdram_dq_oe - attribute \src "ls180.v:36.13-36.24" - wire output 32 \sdram_ras_n - attribute \src "ls180.v:35.13-35.23" - wire output 31 \sdram_we_n - attribute \src "ls180.v:2674.6-2674.15" + attribute \src "ls180.v:768.32-768.51" + wire \sdram_twtrcon_ready + attribute \src "ls180.v:767.6-767.25" + wire \sdram_twtrcon_valid + attribute \src "ls180.v:374.6-374.25" + wire \sdram_wants_refresh + attribute \src "ls180.v:316.6-316.14" + wire \sdram_we + attribute \src "ls180.v:19.14-19.24" + wire output 15 \sdram_we_n + attribute \src "ls180.v:314.5-314.20" + wire \sdram_wrdata_re + attribute \src "ls180.v:313.12-313.32" + wire width 16 \sdram_wrdata_storage + attribute \src "ls180.v:771.6-771.27" + wire \sdram_write_available + attribute \src "ls180.v:1390.6-1390.15" wire \sdrio_clk - attribute \src "ls180.v:2675.6-2675.17" + attribute \src "ls180.v:1391.6-1391.17" wire \sdrio_clk_1 - attribute \src "ls180.v:2684.6-2684.18" + attribute \src "ls180.v:1400.6-1400.18" wire \sdrio_clk_10 - attribute \src "ls180.v:2685.6-2685.18" + attribute \src "ls180.v:1492.6-1492.19" + wire \sdrio_clk_100 + attribute \src "ls180.v:1493.6-1493.19" + wire \sdrio_clk_101 + attribute \src "ls180.v:1494.6-1494.19" + wire \sdrio_clk_102 + attribute \src "ls180.v:1495.6-1495.19" + wire \sdrio_clk_103 + attribute \src "ls180.v:1401.6-1401.18" wire \sdrio_clk_11 - attribute \src "ls180.v:2686.6-2686.18" + attribute \src "ls180.v:1402.6-1402.18" wire \sdrio_clk_12 - attribute \src "ls180.v:2687.6-2687.18" + attribute \src "ls180.v:1403.6-1403.18" wire \sdrio_clk_13 - attribute \src "ls180.v:2688.6-2688.18" + attribute \src "ls180.v:1404.6-1404.18" wire \sdrio_clk_14 - attribute \src "ls180.v:2689.6-2689.18" + attribute \src "ls180.v:1405.6-1405.18" wire \sdrio_clk_15 - attribute \src "ls180.v:2690.6-2690.18" + attribute \src "ls180.v:1406.6-1406.18" wire \sdrio_clk_16 - attribute \src "ls180.v:2691.6-2691.18" + attribute \src "ls180.v:1407.6-1407.18" wire \sdrio_clk_17 - attribute \src "ls180.v:2692.6-2692.18" + attribute \src "ls180.v:1408.6-1408.18" wire \sdrio_clk_18 - attribute \src "ls180.v:2693.6-2693.18" + attribute \src "ls180.v:1409.6-1409.18" wire \sdrio_clk_19 - attribute \src "ls180.v:2676.6-2676.17" + attribute \src "ls180.v:1392.6-1392.17" wire \sdrio_clk_2 - attribute \src "ls180.v:2694.6-2694.18" + attribute \src "ls180.v:1410.6-1410.18" wire \sdrio_clk_20 - attribute \src "ls180.v:2695.6-2695.18" + attribute \src "ls180.v:1411.6-1411.18" wire \sdrio_clk_21 - attribute \src "ls180.v:2696.6-2696.18" + attribute \src "ls180.v:1412.6-1412.18" wire \sdrio_clk_22 - attribute \src "ls180.v:2697.6-2697.18" + attribute \src "ls180.v:1413.6-1413.18" wire \sdrio_clk_23 - attribute \src "ls180.v:2698.6-2698.18" + attribute \src "ls180.v:1414.6-1414.18" wire \sdrio_clk_24 - attribute \src "ls180.v:2699.6-2699.18" + attribute \src "ls180.v:1415.6-1415.18" wire \sdrio_clk_25 - attribute \src "ls180.v:2700.6-2700.18" + attribute \src "ls180.v:1416.6-1416.18" wire \sdrio_clk_26 - attribute \src "ls180.v:2701.6-2701.18" + attribute \src "ls180.v:1417.6-1417.18" wire \sdrio_clk_27 - attribute \src "ls180.v:2702.6-2702.18" + attribute \src "ls180.v:1418.6-1418.18" wire \sdrio_clk_28 - attribute \src "ls180.v:2703.6-2703.18" + attribute \src "ls180.v:1419.6-1419.18" wire \sdrio_clk_29 - attribute \src "ls180.v:2677.6-2677.17" + attribute \src "ls180.v:1393.6-1393.17" wire \sdrio_clk_3 - attribute \src "ls180.v:2704.6-2704.18" + attribute \src "ls180.v:1420.6-1420.18" wire \sdrio_clk_30 - attribute \src "ls180.v:2705.6-2705.18" + attribute \src "ls180.v:1421.6-1421.18" wire \sdrio_clk_31 - attribute \src "ls180.v:2706.6-2706.18" + attribute \src "ls180.v:1422.6-1422.18" wire \sdrio_clk_32 - attribute \src "ls180.v:2707.6-2707.18" + attribute \src "ls180.v:1423.6-1423.18" wire \sdrio_clk_33 - attribute \src "ls180.v:2708.6-2708.18" + attribute \src "ls180.v:1424.6-1424.18" wire \sdrio_clk_34 - attribute \src "ls180.v:2709.6-2709.18" + attribute \src "ls180.v:1425.6-1425.18" wire \sdrio_clk_35 - attribute \src "ls180.v:2710.6-2710.18" + attribute \src "ls180.v:1426.6-1426.18" wire \sdrio_clk_36 - attribute \src "ls180.v:2711.6-2711.18" + attribute \src "ls180.v:1427.6-1427.18" wire \sdrio_clk_37 - attribute \src "ls180.v:2712.6-2712.18" + attribute \src "ls180.v:1428.6-1428.18" wire \sdrio_clk_38 - attribute \src "ls180.v:2713.6-2713.18" + attribute \src "ls180.v:1429.6-1429.18" wire \sdrio_clk_39 - attribute \src "ls180.v:2678.6-2678.17" + attribute \src "ls180.v:1394.6-1394.17" wire \sdrio_clk_4 - attribute \src "ls180.v:2714.6-2714.18" + attribute \src "ls180.v:1430.6-1430.18" wire \sdrio_clk_40 - attribute \src "ls180.v:2715.6-2715.18" + attribute \src "ls180.v:1431.6-1431.18" wire \sdrio_clk_41 - attribute \src "ls180.v:2716.6-2716.18" + attribute \src "ls180.v:1432.6-1432.18" wire \sdrio_clk_42 - attribute \src "ls180.v:2717.6-2717.18" + attribute \src "ls180.v:1433.6-1433.18" wire \sdrio_clk_43 - attribute \src "ls180.v:2718.6-2718.18" + attribute \src "ls180.v:1434.6-1434.18" wire \sdrio_clk_44 - attribute \src "ls180.v:2719.6-2719.18" + attribute \src "ls180.v:1435.6-1435.18" wire \sdrio_clk_45 - attribute \src "ls180.v:2720.6-2720.18" + attribute \src "ls180.v:1436.6-1436.18" wire \sdrio_clk_46 - attribute \src "ls180.v:2721.6-2721.18" + attribute \src "ls180.v:1437.6-1437.18" wire \sdrio_clk_47 - attribute \src "ls180.v:2722.6-2722.18" + attribute \src "ls180.v:1438.6-1438.18" wire \sdrio_clk_48 - attribute \src "ls180.v:2723.6-2723.18" + attribute \src "ls180.v:1439.6-1439.18" wire \sdrio_clk_49 - attribute \src "ls180.v:2679.6-2679.17" + attribute \src "ls180.v:1395.6-1395.17" wire \sdrio_clk_5 - attribute \src "ls180.v:2724.6-2724.18" + attribute \src "ls180.v:1440.6-1440.18" wire \sdrio_clk_50 - attribute \src "ls180.v:2725.6-2725.18" + attribute \src "ls180.v:1441.6-1441.18" wire \sdrio_clk_51 - attribute \src "ls180.v:2726.6-2726.18" + attribute \src "ls180.v:1442.6-1442.18" wire \sdrio_clk_52 - attribute \src "ls180.v:2727.6-2727.18" + attribute \src "ls180.v:1443.6-1443.18" wire \sdrio_clk_53 - attribute \src "ls180.v:2728.6-2728.18" + attribute \src "ls180.v:1444.6-1444.18" wire \sdrio_clk_54 - attribute \src "ls180.v:2729.6-2729.18" + attribute \src "ls180.v:1445.6-1445.18" wire \sdrio_clk_55 - attribute \src "ls180.v:2764.6-2764.18" + attribute \src "ls180.v:1448.6-1448.18" wire \sdrio_clk_56 - attribute \src "ls180.v:2765.6-2765.18" + attribute \src "ls180.v:1449.6-1449.18" wire \sdrio_clk_57 - attribute \src "ls180.v:2766.6-2766.18" + attribute \src "ls180.v:1450.6-1450.18" wire \sdrio_clk_58 - attribute \src "ls180.v:2767.6-2767.18" + attribute \src "ls180.v:1451.6-1451.18" wire \sdrio_clk_59 - attribute \src "ls180.v:2680.6-2680.17" + attribute \src "ls180.v:1396.6-1396.17" wire \sdrio_clk_6 - attribute \src "ls180.v:2768.6-2768.18" + attribute \src "ls180.v:1452.6-1452.18" wire \sdrio_clk_60 - attribute \src "ls180.v:2769.6-2769.18" + attribute \src "ls180.v:1453.6-1453.18" wire \sdrio_clk_61 - attribute \src "ls180.v:2770.6-2770.18" + attribute \src "ls180.v:1454.6-1454.18" wire \sdrio_clk_62 - attribute \src "ls180.v:2771.6-2771.18" + attribute \src "ls180.v:1455.6-1455.18" wire \sdrio_clk_63 - attribute \src "ls180.v:2772.6-2772.18" + attribute \src "ls180.v:1456.6-1456.18" wire \sdrio_clk_64 - attribute \src "ls180.v:2773.6-2773.18" + attribute \src "ls180.v:1457.6-1457.18" wire \sdrio_clk_65 - attribute \src "ls180.v:2774.6-2774.18" + attribute \src "ls180.v:1458.6-1458.18" wire \sdrio_clk_66 - attribute \src "ls180.v:2775.6-2775.18" + attribute \src "ls180.v:1459.6-1459.18" wire \sdrio_clk_67 - attribute \src "ls180.v:2776.6-2776.18" + attribute \src "ls180.v:1460.6-1460.18" wire \sdrio_clk_68 - attribute \src "ls180.v:2681.6-2681.17" + attribute \src "ls180.v:1461.6-1461.18" + wire \sdrio_clk_69 + attribute \src "ls180.v:1397.6-1397.17" wire \sdrio_clk_7 - attribute \src "ls180.v:2682.6-2682.17" + attribute \src "ls180.v:1462.6-1462.18" + wire \sdrio_clk_70 + attribute \src "ls180.v:1463.6-1463.18" + wire \sdrio_clk_71 + attribute \src "ls180.v:1464.6-1464.18" + wire \sdrio_clk_72 + attribute \src "ls180.v:1465.6-1465.18" + wire \sdrio_clk_73 + attribute \src "ls180.v:1466.6-1466.18" + wire \sdrio_clk_74 + attribute \src "ls180.v:1467.6-1467.18" + wire \sdrio_clk_75 + attribute \src "ls180.v:1468.6-1468.18" + wire \sdrio_clk_76 + attribute \src "ls180.v:1469.6-1469.18" + wire \sdrio_clk_77 + attribute \src "ls180.v:1470.6-1470.18" + wire \sdrio_clk_78 + attribute \src "ls180.v:1471.6-1471.18" + wire \sdrio_clk_79 + attribute \src "ls180.v:1398.6-1398.17" wire \sdrio_clk_8 - attribute \src "ls180.v:2683.6-2683.17" + attribute \src "ls180.v:1472.6-1472.18" + wire \sdrio_clk_80 + attribute \src "ls180.v:1473.6-1473.18" + wire \sdrio_clk_81 + attribute \src "ls180.v:1474.6-1474.18" + wire \sdrio_clk_82 + attribute \src "ls180.v:1475.6-1475.18" + wire \sdrio_clk_83 + attribute \src "ls180.v:1476.6-1476.18" + wire \sdrio_clk_84 + attribute \src "ls180.v:1477.6-1477.18" + wire \sdrio_clk_85 + attribute \src "ls180.v:1478.6-1478.18" + wire \sdrio_clk_86 + attribute \src "ls180.v:1479.6-1479.18" + wire \sdrio_clk_87 + attribute \src "ls180.v:1480.6-1480.18" + wire \sdrio_clk_88 + attribute \src "ls180.v:1481.6-1481.18" + wire \sdrio_clk_89 + attribute \src "ls180.v:1399.6-1399.17" wire \sdrio_clk_9 - attribute \src "ls180.v:6.13-6.26" - wire output 2 \spimaster_clk - attribute \src "ls180.v:8.13-8.27" - wire output 4 \spimaster_cs_n - attribute \src "ls180.v:9.13-9.27" - wire input 5 \spimaster_miso - attribute \src "ls180.v:7.13-7.27" - wire output 3 \spimaster_mosi - attribute \src "ls180.v:14.13-14.26" - wire output 10 \spisdcard_clk - attribute \src "ls180.v:16.13-16.27" - wire output 12 \spisdcard_cs_n - attribute \src "ls180.v:17.13-17.27" - wire input 13 \spisdcard_miso - attribute \src "ls180.v:15.13-15.27" - wire output 11 \spisdcard_mosi - attribute \src "ls180.v:43.13-43.20" - wire input 39 \sys_clk - attribute \src "ls180.v:250.6-250.15" + attribute \src "ls180.v:1482.6-1482.18" + wire \sdrio_clk_90 + attribute \src "ls180.v:1483.6-1483.18" + wire \sdrio_clk_91 + attribute \src "ls180.v:1484.6-1484.18" + wire \sdrio_clk_92 + attribute \src "ls180.v:1485.6-1485.18" + wire \sdrio_clk_93 + attribute \src "ls180.v:1486.6-1486.18" + wire \sdrio_clk_94 + attribute \src "ls180.v:1487.6-1487.18" + wire \sdrio_clk_95 + attribute \src "ls180.v:1488.6-1488.18" + wire \sdrio_clk_96 + attribute \src "ls180.v:1489.6-1489.18" + wire \sdrio_clk_97 + attribute \src "ls180.v:1490.6-1490.18" + wire \sdrio_clk_98 + attribute \src "ls180.v:1491.6-1491.18" + wire \sdrio_clk_99 + attribute \src "ls180.v:806.5-806.42" + wire \socbushandler_converted_interface_ack + attribute \src "ls180.v:800.13-800.50" + wire width 30 \socbushandler_converted_interface_adr + attribute \src "ls180.v:809.12-809.49" + wire width 2 \socbushandler_converted_interface_bte + attribute \src "ls180.v:808.12-808.49" + wire width 3 \socbushandler_converted_interface_cti + attribute \src "ls180.v:804.6-804.43" + wire \socbushandler_converted_interface_cyc + attribute \src "ls180.v:802.13-802.52" + wire width 64 \socbushandler_converted_interface_dat_r + attribute \src "ls180.v:801.13-801.52" + wire width 64 \socbushandler_converted_interface_dat_w + attribute \src "ls180.v:810.5-810.42" + wire \socbushandler_converted_interface_err + attribute \src "ls180.v:803.12-803.49" + wire width 8 \socbushandler_converted_interface_sel + attribute \src "ls180.v:805.6-805.43" + wire \socbushandler_converted_interface_stb + attribute \src "ls180.v:807.6-807.42" + wire \socbushandler_converted_interface_we + attribute \src "ls180.v:812.5-812.26" + wire \socbushandler_counter + attribute \src "ls180.v:1012.5-1012.61" + wire \socbushandler_counter_subfragments_converter2_next_value + attribute \src "ls180.v:1013.5-1013.64" + wire \socbushandler_counter_subfragments_converter2_next_value_ce + attribute \src "ls180.v:814.12-814.31" + wire width 64 \socbushandler_dat_r + attribute \src "ls180.v:813.6-813.25" + wire \socbushandler_reset + attribute \src "ls180.v:811.5-811.23" + wire \socbushandler_skip + attribute \src "ls180.v:8.14-8.27" + wire output 4 \spimaster_clk + attribute \src "ls180.v:10.14-10.28" + wire output 6 \spimaster_cs_n + attribute \src "ls180.v:11.13-11.27" + wire input 7 \spimaster_miso + attribute \src "ls180.v:9.14-9.28" + wire output 5 \spimaster_mosi + attribute \src "ls180.v:1017.11-1017.47" + wire width 3 \subfragments_bankmachine0_next_state + attribute \src "ls180.v:1016.11-1016.42" + wire width 3 \subfragments_bankmachine0_state + attribute \src "ls180.v:1019.11-1019.47" + wire width 3 \subfragments_bankmachine1_next_state + attribute \src "ls180.v:1018.11-1018.42" + wire width 3 \subfragments_bankmachine1_state + attribute \src "ls180.v:1021.11-1021.47" + wire width 3 \subfragments_bankmachine2_next_state + attribute \src "ls180.v:1020.11-1020.42" + wire width 3 \subfragments_bankmachine2_state + attribute \src "ls180.v:1023.11-1023.47" + wire width 3 \subfragments_bankmachine3_next_state + attribute \src "ls180.v:1022.11-1022.42" + wire width 3 \subfragments_bankmachine3_state + attribute \src "ls180.v:1003.5-1003.39" + wire \subfragments_converter0_next_state + attribute \src "ls180.v:1002.5-1002.34" + wire \subfragments_converter0_state + attribute \src "ls180.v:1007.5-1007.39" + wire \subfragments_converter1_next_state + attribute \src "ls180.v:1006.5-1006.34" + wire \subfragments_converter1_state + attribute \src "ls180.v:1011.5-1011.39" + wire \subfragments_converter2_next_state + attribute \src "ls180.v:1010.5-1010.34" + wire \subfragments_converter2_state + attribute \src "ls180.v:1038.5-1038.25" + wire \subfragments_locked0 + attribute \src "ls180.v:1039.5-1039.25" + wire \subfragments_locked1 + attribute \src "ls180.v:1040.5-1040.25" + wire \subfragments_locked2 + attribute \src "ls180.v:1041.5-1041.25" + wire \subfragments_locked3 + attribute \src "ls180.v:1025.11-1025.46" + wire width 3 \subfragments_multiplexer_next_state + attribute \src "ls180.v:1024.11-1024.41" + wire width 3 \subfragments_multiplexer_state + attribute \src "ls180.v:1043.5-1043.41" + wire \subfragments_new_master_rdata_valid0 + attribute \src "ls180.v:1044.5-1044.41" + wire \subfragments_new_master_rdata_valid1 + attribute \src "ls180.v:1045.5-1045.41" + wire \subfragments_new_master_rdata_valid2 + attribute \src "ls180.v:1046.5-1046.41" + wire \subfragments_new_master_rdata_valid3 + attribute \src "ls180.v:1042.5-1042.40" + wire \subfragments_new_master_wdata_ready + attribute \src "ls180.v:1048.5-1048.28" + wire \subfragments_next_state + attribute \src "ls180.v:1015.11-1015.44" + wire width 2 \subfragments_refresher_next_state + attribute \src "ls180.v:1014.11-1014.39" + wire width 2 \subfragments_refresher_state + attribute \src "ls180.v:1028.6-1028.33" + wire \subfragments_roundrobin0_ce + attribute \src "ls180.v:1027.6-1027.36" + wire \subfragments_roundrobin0_grant + attribute \src "ls180.v:1026.6-1026.38" + wire \subfragments_roundrobin0_request + attribute \src "ls180.v:1031.6-1031.33" + wire \subfragments_roundrobin1_ce + attribute \src "ls180.v:1030.6-1030.36" + wire \subfragments_roundrobin1_grant + attribute \src "ls180.v:1029.6-1029.38" + wire \subfragments_roundrobin1_request + attribute \src "ls180.v:1034.6-1034.33" + wire \subfragments_roundrobin2_ce + attribute \src "ls180.v:1033.6-1033.36" + wire \subfragments_roundrobin2_grant + attribute \src "ls180.v:1032.6-1032.38" + wire \subfragments_roundrobin2_request + attribute \src "ls180.v:1037.6-1037.33" + wire \subfragments_roundrobin3_ce + attribute \src "ls180.v:1036.6-1036.36" + wire \subfragments_roundrobin3_grant + attribute \src "ls180.v:1035.6-1035.38" + wire \subfragments_roundrobin3_request + attribute \src "ls180.v:1047.5-1047.23" + wire \subfragments_state + attribute \src "ls180.v:31.13-31.20" + wire input 27 \sys_clk + attribute \src "ls180.v:228.6-228.15" wire \sys_clk_1 - attribute \src "ls180.v:45.19-45.31" - wire width 2 input 41 \sys_clksel_i - attribute \src "ls180.v:46.14-46.26" - wire output 42 \sys_pll_18_o - attribute \src "ls180.v:47.14-47.27" - wire output 43 \sys_pll_lck_o - attribute \src "ls180.v:44.13-44.20" - wire input 40 \sys_rst - attribute \src "ls180.v:251.6-251.15" + attribute \src "ls180.v:33.19-33.31" + wire width 2 input 29 \sys_clksel_i + attribute \src "ls180.v:34.14-34.26" + wire output 30 \sys_pll_18_o + attribute \src "ls180.v:35.14-35.27" + wire output 31 \sys_pll_lck_o + attribute \src "ls180.v:32.13-32.20" + wire input 28 \sys_rst + attribute \src "ls180.v:229.6-229.15" wire \sys_rst_1 - attribute \src "ls180.v:22.13-22.20" - wire input 18 \uart_rx - attribute \src "ls180.v:21.13-21.20" - wire output 17 \uart_tx - attribute \src "ls180.v:10142.12-10142.15" + attribute \src "ls180.v:1351.5-1351.19" + wire \t_array_muxed0 + attribute \src "ls180.v:1352.5-1352.19" + wire \t_array_muxed1 + attribute \src "ls180.v:1353.5-1353.19" + wire \t_array_muxed2 + attribute \src "ls180.v:1360.5-1360.19" + wire \t_array_muxed3 + attribute \src "ls180.v:1361.5-1361.19" + wire \t_array_muxed4 + attribute \src "ls180.v:1362.5-1362.19" + wire \t_array_muxed5 + attribute \src "ls180.v:868.5-868.13" + wire \tx_clear + attribute \src "ls180.v:920.11-920.26" + wire width 4 \tx_fifo_consume + attribute \src "ls180.v:925.6-925.21" + wire \tx_fifo_do_read + attribute \src "ls180.v:931.6-931.27" + wire \tx_fifo_fifo_in_first + attribute \src "ls180.v:932.6-932.26" + wire \tx_fifo_fifo_in_last + attribute \src "ls180.v:930.12-930.40" + wire width 8 \tx_fifo_fifo_in_payload_data + attribute \src "ls180.v:934.6-934.28" + wire \tx_fifo_fifo_out_first + attribute \src "ls180.v:935.6-935.27" + wire \tx_fifo_fifo_out_last + attribute \src "ls180.v:933.12-933.41" + wire width 8 \tx_fifo_fifo_out_payload_data + attribute \src "ls180.v:917.11-917.25" + wire width 5 \tx_fifo_level0 + attribute \src "ls180.v:929.12-929.26" + wire width 5 \tx_fifo_level1 + attribute \src "ls180.v:919.11-919.26" + wire width 4 \tx_fifo_produce + attribute \src "ls180.v:926.12-926.30" + wire width 4 \tx_fifo_rdport_adr + attribute \src "ls180.v:927.12-927.32" + wire width 10 \tx_fifo_rdport_dat_r + attribute \src "ls180.v:928.6-928.23" + wire \tx_fifo_rdport_re + attribute \src "ls180.v:909.6-909.16" + wire \tx_fifo_re + attribute \src "ls180.v:910.5-910.21" + wire \tx_fifo_readable + attribute \src "ls180.v:918.5-918.20" + wire \tx_fifo_replace + attribute \src "ls180.v:901.5-901.23" + wire \tx_fifo_sink_first + attribute \src "ls180.v:902.5-902.22" + wire \tx_fifo_sink_last + attribute \src "ls180.v:903.12-903.37" + wire width 8 \tx_fifo_sink_payload_data + attribute \src "ls180.v:900.6-900.24" + wire \tx_fifo_sink_ready + attribute \src "ls180.v:899.6-899.24" + wire \tx_fifo_sink_valid + attribute \src "ls180.v:906.6-906.26" + wire \tx_fifo_source_first + attribute \src "ls180.v:907.6-907.25" + wire \tx_fifo_source_last + attribute \src "ls180.v:908.12-908.39" + wire width 8 \tx_fifo_source_payload_data + attribute \src "ls180.v:905.6-905.26" + wire \tx_fifo_source_ready + attribute \src "ls180.v:904.6-904.26" + wire \tx_fifo_source_valid + attribute \src "ls180.v:915.12-915.32" + wire width 10 \tx_fifo_syncfifo_din + attribute \src "ls180.v:916.12-916.33" + wire width 10 \tx_fifo_syncfifo_dout + attribute \src "ls180.v:913.6-913.25" + wire \tx_fifo_syncfifo_re + attribute \src "ls180.v:914.6-914.31" + wire \tx_fifo_syncfifo_readable + attribute \src "ls180.v:911.6-911.25" + wire \tx_fifo_syncfifo_we + attribute \src "ls180.v:912.6-912.31" + wire \tx_fifo_syncfifo_writable + attribute \src "ls180.v:921.11-921.29" + wire width 4 \tx_fifo_wrport_adr + attribute \src "ls180.v:922.12-922.32" + wire width 10 \tx_fifo_wrport_dat_r + attribute \src "ls180.v:924.12-924.32" + wire width 10 \tx_fifo_wrport_dat_w + attribute \src "ls180.v:923.6-923.23" + wire \tx_fifo_wrport_we + attribute \src "ls180.v:869.5-869.19" + wire \tx_old_trigger + attribute \src "ls180.v:866.5-866.15" + wire \tx_pending + attribute \src "ls180.v:865.6-865.15" + wire \tx_status + attribute \src "ls180.v:867.6-867.16" + wire \tx_trigger + attribute \src "ls180.v:885.6-885.20" + wire \txempty_status + attribute \src "ls180.v:886.6-886.16" + wire \txempty_we + attribute \src "ls180.v:860.6-860.19" + wire \txfull_status + attribute \src "ls180.v:861.6-861.15" + wire \txfull_we + attribute \src "ls180.v:850.12-850.41" + wire width 32 \uart_phy_phase_accumulator_rx + attribute \src "ls180.v:840.12-840.41" + wire width 32 \uart_phy_phase_accumulator_tx + attribute \src "ls180.v:833.5-833.16" + wire \uart_phy_re + attribute \src "ls180.v:851.6-851.17" + wire \uart_phy_rx + attribute \src "ls180.v:854.11-854.31" + wire width 4 \uart_phy_rx_bitcount + attribute \src "ls180.v:855.5-855.21" + wire \uart_phy_rx_busy + attribute \src "ls180.v:852.5-852.18" + wire \uart_phy_rx_r + attribute \src "ls180.v:853.11-853.26" + wire width 8 \uart_phy_rx_reg + attribute \src "ls180.v:836.6-836.25" + wire \uart_phy_sink_first + attribute \src "ls180.v:837.6-837.24" + wire \uart_phy_sink_last + attribute \src "ls180.v:838.12-838.38" + wire width 8 \uart_phy_sink_payload_data + attribute \src "ls180.v:835.5-835.24" + wire \uart_phy_sink_ready + attribute \src "ls180.v:834.6-834.25" + wire \uart_phy_sink_valid + attribute \src "ls180.v:846.5-846.26" + wire \uart_phy_source_first + attribute \src "ls180.v:847.5-847.25" + wire \uart_phy_source_last + attribute \src "ls180.v:848.11-848.39" + wire width 8 \uart_phy_source_payload_data + attribute \src "ls180.v:845.6-845.27" + wire \uart_phy_source_ready + attribute \src "ls180.v:844.5-844.26" + wire \uart_phy_source_valid + attribute \src "ls180.v:832.12-832.28" + wire width 32 \uart_phy_storage + attribute \src "ls180.v:842.11-842.31" + wire width 4 \uart_phy_tx_bitcount + attribute \src "ls180.v:843.5-843.21" + wire \uart_phy_tx_busy + attribute \src "ls180.v:841.11-841.26" + wire width 8 \uart_phy_tx_reg + attribute \src "ls180.v:849.5-849.27" + wire \uart_phy_uart_clk_rxen + attribute \src "ls180.v:839.5-839.27" + wire \uart_phy_uart_clk_txen + attribute \src "ls180.v:13.13-13.20" + wire input 9 \uart_rx + attribute \src "ls180.v:891.6-891.21" + wire \uart_sink_first + attribute \src "ls180.v:892.6-892.20" + wire \uart_sink_last + attribute \src "ls180.v:893.12-893.34" + wire width 8 \uart_sink_payload_data + attribute \src "ls180.v:890.6-890.21" + wire \uart_sink_ready + attribute \src "ls180.v:889.6-889.21" + wire \uart_sink_valid + attribute \src "ls180.v:896.6-896.23" + wire \uart_source_first + attribute \src "ls180.v:897.6-897.22" + wire \uart_source_last + attribute \src "ls180.v:898.12-898.36" + wire width 8 \uart_source_payload_data + attribute \src "ls180.v:895.6-895.23" + wire \uart_source_ready + attribute \src "ls180.v:894.6-894.23" + wire \uart_source_valid + attribute \src "ls180.v:12.13-12.20" + wire input 8 \uart_tx + attribute \src "ls180.v:798.5-798.17" + wire \wb_sdram_ack + attribute \src "ls180.v:792.12-792.24" + wire width 30 \wb_sdram_adr + attribute \src "ls180.v:796.5-796.17" + wire \wb_sdram_cyc + attribute \src "ls180.v:794.13-794.27" + wire width 32 \wb_sdram_dat_r + attribute \src "ls180.v:793.12-793.26" + wire width 32 \wb_sdram_dat_w + attribute \src "ls180.v:795.11-795.23" + wire width 4 \wb_sdram_sel + attribute \src "ls180.v:797.5-797.17" + wire \wb_sdram_stb + attribute \src "ls180.v:799.5-799.16" + wire \wb_sdram_we + attribute \src "ls180.v:828.5-828.19" + wire \wdata_consumed + attribute \src "ls180.v:5489.12-5489.15" memory width 64 size 64 \mem - attribute \src "ls180.v:10170.12-10170.17" + attribute \src "ls180.v:5517.12-5517.17" memory width 64 size 16 \mem_1 - attribute \src "ls180.v:10198.12-10198.19" + attribute \src "ls180.v:5545.12-5545.19" memory width 25 size 8 \storage - attribute \src "ls180.v:10212.12-10212.21" + attribute \src "ls180.v:5559.12-5559.21" memory width 25 size 8 \storage_1 - attribute \src "ls180.v:10226.12-10226.21" + attribute \src "ls180.v:5573.12-5573.21" memory width 25 size 8 \storage_2 - attribute \src "ls180.v:10240.12-10240.21" + attribute \src "ls180.v:5587.12-5587.21" memory width 25 size 8 \storage_3 - attribute \src "ls180.v:10254.11-10254.20" + attribute \src "ls180.v:5601.11-5601.20" memory width 10 size 16 \storage_4 - attribute \src "ls180.v:10271.11-10271.20" + attribute \src "ls180.v:5618.11-5618.20" memory width 10 size 16 \storage_5 - attribute \src "ls180.v:10288.11-10288.20" - memory width 10 size 32 \storage_6 - attribute \src "ls180.v:10302.11-10302.20" - memory width 10 size 32 \storage_7 - attribute \src "ls180.v:2846.56-2846.86" - cell $add $add$ls180.v:2846$34 + attribute \src "ls180.v:1555.64-1555.89" + cell $add $add$ls180.v:1555$32 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_converter0_counter + connect \A \converter0_counter connect \B 1'1 - connect \Y $add$ls180.v:2846$34_Y + connect \Y $add$ls180.v:1555$32_Y end - attribute \src "ls180.v:2906.56-2906.86" - cell $add $add$ls180.v:2906$45 + attribute \src "ls180.v:1615.64-1615.89" + cell $add $add$ls180.v:1615$43 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_converter1_counter + connect \A \converter1_counter connect \B 1'1 - connect \Y $add$ls180.v:2906$45_Y + connect \Y $add$ls180.v:1615$43_Y end - attribute \src "ls180.v:2966.59-2966.92" - cell $add $add$ls180.v:2966$56 + attribute \src "ls180.v:1675.67-1675.95" + cell $add $add$ls180.v:1675$54 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_socbushandler_counter + connect \A \socbushandler_counter connect \B 1'1 - connect \Y $add$ls180.v:2966$56_Y + connect \Y $add$ls180.v:1675$54_Y end - attribute \src "ls180.v:4117.54-4117.83" - cell $add $add$ls180.v:4117$586 + attribute \src "ls180.v:2826.52-2826.76" + cell $add $add$ls180.v:2826$584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_converter_counter + connect \A \converter_counter connect \B 1'1 - connect \Y $add$ls180.v:4117$586_Y + connect \Y $add$ls180.v:2826$584_Y end - attribute \src "ls180.v:4217.36-4217.89" - cell $add $add$ls180.v:4217$632 + attribute \src "ls180.v:2926.26-2926.59" + cell $add $add$ls180.v:2926$630 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 5 - connect \A \main_uart_tx_fifo_level0 - connect \B \main_uart_tx_fifo_readable - connect \Y $add$ls180.v:4217$632_Y + connect \A \tx_fifo_level0 + connect \B \tx_fifo_readable + connect \Y $add$ls180.v:2926$630_Y end - attribute \src "ls180.v:4247.36-4247.89" - cell $add $add$ls180.v:4247$643 + attribute \src "ls180.v:2956.26-2956.59" + cell $add $add$ls180.v:2956$641 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 5 - connect \A \main_uart_rx_fifo_level0 - connect \B \main_uart_rx_fifo_readable - connect \Y $add$ls180.v:4247$643_Y - end - attribute \src "ls180.v:4313.54-4313.83" - cell $add $add$ls180.v:4313$658 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_spimaster27_count - connect \B 1'1 - connect \Y $add$ls180.v:4313$658_Y - end - attribute \src "ls180.v:4372.52-4372.79" - cell $add $add$ls180.v:4372$666 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_spisdcard_count - connect \B 1'1 - connect \Y $add$ls180.v:4372$666_Y - end - attribute \src "ls180.v:4476.58-4476.86" - cell $add $add$ls180.v:4476$694 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_sdphy_init_count - connect \B 1'1 - connect \Y $add$ls180.v:4476$694_Y - end - attribute \src "ls180.v:4533.58-4533.86" - cell $add $add$ls180.v:4533$697 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_sdphy_cmdw_count - connect \B 1'1 - connect \Y $add$ls180.v:4533$697_Y - end - attribute \src "ls180.v:4550.58-4550.86" - cell $add $add$ls180.v:4550$699 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_sdphy_cmdw_count - connect \B 1'1 - connect \Y $add$ls180.v:4550$699_Y - end - attribute \src "ls180.v:4643.59-4643.87" - cell $add $add$ls180.v:4643$716 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_sdphy_cmdr_count - connect \B 1'1 - connect \Y $add$ls180.v:4643$716_Y - end - attribute \src "ls180.v:4668.59-4668.87" - cell $add $add$ls180.v:4668$719 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_sdphy_cmdr_count - connect \B 1'1 - connect \Y $add$ls180.v:4668$719_Y - end - attribute \src "ls180.v:4790.53-4790.82" - cell $add $add$ls180.v:4790$736 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_sdphy_dataw_count - connect \B 1'1 - connect \Y $add$ls180.v:4790$736_Y - end - attribute \src "ls180.v:4901.65-4901.114" - cell $add $add$ls180.v:4901$750 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 10 - connect \A \main_sdphy_datar_sink_payload_block_length - connect \B 4'1000 - connect \Y $add$ls180.v:4901$750_Y - end - attribute \src "ls180.v:4906.62-4906.91" - cell $add $add$ls180.v:4906$753 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 10 - connect \A \main_sdphy_datar_count - connect \B 1'1 - connect \Y $add$ls180.v:4906$753_Y - end - attribute \src "ls180.v:4932.61-4932.90" - cell $add $add$ls180.v:4932$756 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 10 - connect \A \main_sdphy_datar_count - connect \B 1'1 - connect \Y $add$ls180.v:4932$756_Y - end - attribute \src "ls180.v:5136.80-5136.117" - cell $add $add$ls180.v:5136$941 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdcore_crc16_inserter_cnt - connect \B 1'1 - connect \Y $add$ls180.v:5136$941_Y - end - attribute \src "ls180.v:5330.54-5330.82" - cell $add $add$ls180.v:5330$1016 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdcore_cmd_count - connect \B 1'1 - connect \Y $add$ls180.v:5330$1016_Y - end - attribute \src "ls180.v:5382.55-5382.84" - cell $add $add$ls180.v:5382$1026 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdcore_data_count - connect \B 1'1 - connect \Y $add$ls180.v:5382$1026_Y - end - attribute \src "ls180.v:5408.57-5408.86" - cell $add $add$ls180.v:5408$1034 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdcore_data_count - connect \B 1'1 - connect \Y $add$ls180.v:5408$1034_Y - end - attribute \src "ls180.v:5529.51-5529.134" - cell $add $add$ls180.v:5529$1050 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A \main_sdblock2mem_wishbonedmawriter_base - connect \B \main_sdblock2mem_wishbonedmawriter_offset - connect \Y $add$ls180.v:5529$1050_Y - end - attribute \src "ls180.v:5532.77-5532.125" - cell $add $add$ls180.v:5532$1052 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdblock2mem_wishbonedmawriter_offset - connect \B 1'1 - connect \Y $add$ls180.v:5532$1052_Y - end - attribute \src "ls180.v:5625.50-5625.105" - cell $add $add$ls180.v:5625$1061 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A \main_sdmem2block_dma_base - connect \B \main_sdmem2block_dma_offset - connect \Y $add$ls180.v:5625$1061_Y - end - attribute \src "ls180.v:5627.77-5627.111" - cell $add $add$ls180.v:5627$1062 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdmem2block_dma_offset - connect \B 1'1 - connect \Y $add$ls180.v:5627$1062_Y + connect \A \rx_fifo_level0 + connect \B \rx_fifo_readable + connect \Y $add$ls180.v:2956$641_Y end - attribute \src "ls180.v:7571.36-7571.70" - cell $add $add$ls180.v:7571$2463 + attribute \src "ls180.v:4353.31-4353.60" + cell $add $add$ls180.v:4353$1281 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 32 - connect \A \main_libresocsim_bus_errors + connect \A \libresocsim_bus_errors connect \B 1'1 - connect \Y $add$ls180.v:7571$2463_Y + connect \Y $add$ls180.v:4353$1281_Y end - attribute \src "ls180.v:7660.37-7660.72" - cell $add $add$ls180.v:7660$2487 + attribute \src "ls180.v:4442.32-4442.62" + cell $add $add$ls180.v:4442$1305 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 4 - connect \A \main_sdram_sequencer_counter + connect \A \sdram_sequencer_counter connect \B 1'1 - connect \Y $add$ls180.v:7660$2487_Y + connect \Y $add$ls180.v:4442$1305_Y end - attribute \src "ls180.v:7677.60-7677.119" - cell $add $add$ls180.v:7677$2491 + attribute \src "ls180.v:4459.55-4459.109" + cell $add $add$ls180.v:4459$1309 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + connect \A \sdram_bankmachine0_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:7677$2491_Y + connect \Y $add$ls180.v:4459$1309_Y end - attribute \src "ls180.v:7680.60-7680.119" - cell $add $add$ls180.v:7680$2492 + attribute \src "ls180.v:4462.55-4462.109" + cell $add $add$ls180.v:4462$1310 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_consume + connect \A \sdram_bankmachine0_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:7680$2492_Y + connect \Y $add$ls180.v:4462$1310_Y end - attribute \src "ls180.v:7684.59-7684.116" - cell $add $add$ls180.v:7684$2497 + attribute \src "ls180.v:4466.54-4466.106" + cell $add $add$ls180.v:4466$1315 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level + connect \A \sdram_bankmachine0_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:7684$2497_Y + connect \Y $add$ls180.v:4466$1315_Y end - attribute \src "ls180.v:7723.60-7723.119" - cell $add $add$ls180.v:7723$2507 + attribute \src "ls180.v:4505.55-4505.109" + cell $add $add$ls180.v:4505$1325 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + connect \A \sdram_bankmachine1_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:7723$2507_Y + connect \Y $add$ls180.v:4505$1325_Y end - attribute \src "ls180.v:7726.60-7726.119" - cell $add $add$ls180.v:7726$2508 + attribute \src "ls180.v:4508.55-4508.109" + cell $add $add$ls180.v:4508$1326 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_consume + connect \A \sdram_bankmachine1_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:7726$2508_Y + connect \Y $add$ls180.v:4508$1326_Y end - attribute \src "ls180.v:7730.59-7730.116" - cell $add $add$ls180.v:7730$2513 + attribute \src "ls180.v:4512.54-4512.106" + cell $add $add$ls180.v:4512$1331 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level + connect \A \sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:7730$2513_Y + connect \Y $add$ls180.v:4512$1331_Y end - attribute \src "ls180.v:7769.60-7769.119" - cell $add $add$ls180.v:7769$2523 + attribute \src "ls180.v:4551.55-4551.109" + cell $add $add$ls180.v:4551$1341 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + connect \A \sdram_bankmachine2_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:7769$2523_Y + connect \Y $add$ls180.v:4551$1341_Y end - attribute \src "ls180.v:7772.60-7772.119" - cell $add $add$ls180.v:7772$2524 + attribute \src "ls180.v:4554.55-4554.109" + cell $add $add$ls180.v:4554$1342 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_consume + connect \A \sdram_bankmachine2_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:7772$2524_Y + connect \Y $add$ls180.v:4554$1342_Y end - attribute \src "ls180.v:7776.59-7776.116" - cell $add $add$ls180.v:7776$2529 + attribute \src "ls180.v:4558.54-4558.106" + cell $add $add$ls180.v:4558$1347 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level + connect \A \sdram_bankmachine2_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:7776$2529_Y + connect \Y $add$ls180.v:4558$1347_Y end - attribute \src "ls180.v:7815.60-7815.119" - cell $add $add$ls180.v:7815$2539 + attribute \src "ls180.v:4597.55-4597.109" + cell $add $add$ls180.v:4597$1357 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + connect \A \sdram_bankmachine3_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $add$ls180.v:7815$2539_Y + connect \Y $add$ls180.v:4597$1357_Y end - attribute \src "ls180.v:7818.60-7818.119" - cell $add $add$ls180.v:7818$2540 + attribute \src "ls180.v:4600.55-4600.109" + cell $add $add$ls180.v:4600$1358 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_consume + connect \A \sdram_bankmachine3_cmd_buffer_lookahead_consume connect \B 1'1 - connect \Y $add$ls180.v:7818$2540_Y + connect \Y $add$ls180.v:4600$1358_Y end - attribute \src "ls180.v:7822.59-7822.116" - cell $add $add$ls180.v:7822$2545 + attribute \src "ls180.v:4604.54-4604.106" + cell $add $add$ls180.v:4604$1363 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level + connect \A \sdram_bankmachine3_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $add$ls180.v:7822$2545_Y + connect \Y $add$ls180.v:4604$1363_Y end - attribute \src "ls180.v:8052.34-8052.66" - cell $add $add$ls180.v:8052$2599 + attribute \src "ls180.v:4834.29-4834.56" + cell $add $add$ls180.v:4834$1417 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 4 - connect \A \main_uart_phy_tx_bitcount + connect \A \uart_phy_tx_bitcount connect \B 1'1 - connect \Y $add$ls180.v:8052$2599_Y + connect \Y $add$ls180.v:4834$1417_Y end - attribute \src "ls180.v:8068.73-8068.131" - cell $add $add$ls180.v:8068$2602 + attribute \src "ls180.v:4850.63-4850.111" + cell $add $add$ls180.v:4850$1420 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 33 - connect \A \main_uart_phy_phase_accumulator_tx - connect \B \main_uart_phy_storage - connect \Y $add$ls180.v:8068$2602_Y + connect \A \uart_phy_phase_accumulator_tx + connect \B \uart_phy_storage + connect \Y $add$ls180.v:4850$1420_Y end - attribute \src "ls180.v:8081.34-8081.66" - cell $add $add$ls180.v:8081$2606 + attribute \src "ls180.v:4863.29-4863.56" + cell $add $add$ls180.v:4863$1424 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 4 - connect \A \main_uart_phy_rx_bitcount + connect \A \uart_phy_rx_bitcount connect \B 1'1 - connect \Y $add$ls180.v:8081$2606_Y + connect \Y $add$ls180.v:4863$1424_Y end - attribute \src "ls180.v:8100.73-8100.131" - cell $add $add$ls180.v:8100$2609 + attribute \src "ls180.v:4882.63-4882.111" + cell $add $add$ls180.v:4882$1427 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 32 parameter \Y_WIDTH 33 - connect \A \main_uart_phy_phase_accumulator_rx - connect \B \main_uart_phy_storage - connect \Y $add$ls180.v:8100$2609_Y + connect \A \uart_phy_phase_accumulator_rx + connect \B \uart_phy_storage + connect \Y $add$ls180.v:4882$1427_Y end - attribute \src "ls180.v:8126.33-8126.65" - cell $add $add$ls180.v:8126$2617 + attribute \src "ls180.v:4908.23-4908.45" + cell $add $add$ls180.v:4908$1435 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 4 - connect \A \main_uart_tx_fifo_produce + connect \A \tx_fifo_produce connect \B 1'1 - connect \Y $add$ls180.v:8126$2617_Y + connect \Y $add$ls180.v:4908$1435_Y end - attribute \src "ls180.v:8129.33-8129.65" - cell $add $add$ls180.v:8129$2618 + attribute \src "ls180.v:4911.23-4911.45" + cell $add $add$ls180.v:4911$1436 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 4 - connect \A \main_uart_tx_fifo_consume + connect \A \tx_fifo_consume connect \B 1'1 - connect \Y $add$ls180.v:8129$2618_Y + connect \Y $add$ls180.v:4911$1436_Y end - attribute \src "ls180.v:8133.33-8133.64" - cell $add $add$ls180.v:8133$2623 + attribute \src "ls180.v:4915.23-4915.44" + cell $add $add$ls180.v:4915$1441 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 5 - connect \A \main_uart_tx_fifo_level0 + connect \A \tx_fifo_level0 connect \B 1'1 - connect \Y $add$ls180.v:8133$2623_Y + connect \Y $add$ls180.v:4915$1441_Y end - attribute \src "ls180.v:8148.33-8148.65" - cell $add $add$ls180.v:8148$2628 + attribute \src "ls180.v:4930.23-4930.45" + cell $add $add$ls180.v:4930$1446 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 4 - connect \A \main_uart_rx_fifo_produce + connect \A \rx_fifo_produce connect \B 1'1 - connect \Y $add$ls180.v:8148$2628_Y + connect \Y $add$ls180.v:4930$1446_Y end - attribute \src "ls180.v:8151.33-8151.65" - cell $add $add$ls180.v:8151$2629 + attribute \src "ls180.v:4933.23-4933.45" + cell $add $add$ls180.v:4933$1447 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 4 - connect \A \main_uart_rx_fifo_consume + connect \A \rx_fifo_consume connect \B 1'1 - connect \Y $add$ls180.v:8151$2629_Y + connect \Y $add$ls180.v:4933$1447_Y end - attribute \src "ls180.v:8155.33-8155.64" - cell $add $add$ls180.v:8155$2634 + attribute \src "ls180.v:4937.23-4937.44" + cell $add $add$ls180.v:4937$1452 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 5 - connect \A \main_uart_rx_fifo_level0 + connect \A \rx_fifo_level0 connect \B 1'1 - connect \Y $add$ls180.v:8155$2634_Y + connect \Y $add$ls180.v:4937$1452_Y end - attribute \src "ls180.v:8176.35-8176.70" - cell $add $add$ls180.v:8176$2636 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 16 - connect \A \main_spimaster30_clk_divider - connect \B 1'1 - connect \Y $add$ls180.v:8176$2636_Y - end - attribute \src "ls180.v:8211.34-8211.68" - cell $add $add$ls180.v:8211$2641 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 16 - connect \A \main_spisdcard_clk_divider1 - connect \B 1'1 - connect \Y $add$ls180.v:8211$2641_Y - end - attribute \src "ls180.v:8247.25-8247.49" - cell $add $add$ls180.v:8247$2646 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_pwm0_counter - connect \B 1'1 - connect \Y $add$ls180.v:8247$2646_Y - end - attribute \src "ls180.v:8261.25-8261.49" - cell $add $add$ls180.v:8261$2650 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_pwm1_counter - connect \B 1'1 - connect \Y $add$ls180.v:8261$2650_Y - end - attribute \src "ls180.v:8275.31-8275.61" - cell $add $add$ls180.v:8275$2655 - parameter \A_SIGNED 0 - parameter \A_WIDTH 9 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 9 - connect \A \main_sdphy_clocker_clks - connect \B 1'1 - connect \Y $add$ls180.v:8275$2655_Y - end - attribute \src "ls180.v:8298.45-8298.88" - cell $add $add$ls180.v:8298$2659 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdphy_cmdr_cmdr_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:8298$2659_Y - end - attribute \src "ls180.v:8344.71-8344.114" - cell $add $add$ls180.v:8344$2665 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdphy_cmdr_cmdr_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:8344$2665_Y - end - attribute \src "ls180.v:8379.46-8379.90" - cell $add $add$ls180.v:8379$2671 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdphy_dataw_crcr_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:8379$2671_Y - end - attribute \src "ls180.v:8425.72-8425.116" - cell $add $add$ls180.v:8425$2677 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdphy_dataw_crcr_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:8425$2677_Y - end - attribute \src "ls180.v:8458.47-8458.92" - cell $add $add$ls180.v:8458$2683 + attribute \src "ls180.v:1549.9-1549.80" + cell $and $and$ls180.v:1549$27 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:8458$2683_Y + connect \A \interface0_converted_interface_stb + connect \B \interface0_converted_interface_cyc + connect \Y $and$ls180.v:1549$27_Y end - attribute \src "ls180.v:8486.73-8486.118" - cell $add $add$ls180.v:8486$2689 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \main_sdphy_datar_datar_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:8486$2689_Y - end - attribute \src "ls180.v:8598.39-8598.75" - cell $add $add$ls180.v:8598$2702 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdcore_crc16_checker_cnt - connect \B 1'1 - connect \Y $add$ls180.v:8598$2702_Y - end - attribute \src "ls180.v:8659.37-8659.73" - cell $add $add$ls180.v:8659$2706 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_sdblock2mem_fifo_produce - connect \B 1'1 - connect \Y $add$ls180.v:8659$2706_Y - end - attribute \src "ls180.v:8662.37-8662.73" - cell $add $add$ls180.v:8662$2707 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_sdblock2mem_fifo_consume - connect \B 1'1 - connect \Y $add$ls180.v:8662$2707_Y - end - attribute \src "ls180.v:8666.36-8666.70" - cell $add $add$ls180.v:8666$2712 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 6 - connect \A \main_sdblock2mem_fifo_level - connect \B 1'1 - connect \Y $add$ls180.v:8666$2712_Y - end - attribute \src "ls180.v:8681.41-8681.80" - cell $add $add$ls180.v:8681$2716 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdblock2mem_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:8681$2716_Y - end - attribute \src "ls180.v:8727.67-8727.106" - cell $add $add$ls180.v:8727$2722 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdblock2mem_converter_demux - connect \B 1'1 - connect \Y $add$ls180.v:8727$2722_Y - end - attribute \src "ls180.v:8753.39-8753.76" - cell $add $add$ls180.v:8753$2724 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdmem2block_converter_mux - connect \B 1'1 - connect \Y $add$ls180.v:8753$2724_Y - end - attribute \src "ls180.v:8757.37-8757.73" - cell $add $add$ls180.v:8757$2728 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_sdmem2block_fifo_produce - connect \B 1'1 - connect \Y $add$ls180.v:8757$2728_Y - end - attribute \src "ls180.v:8760.37-8760.73" - cell $add $add$ls180.v:8760$2729 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_sdmem2block_fifo_consume - connect \B 1'1 - connect \Y $add$ls180.v:8760$2729_Y - end - attribute \src "ls180.v:8764.36-8764.70" - cell $add $add$ls180.v:8764$2734 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 6 - connect \A \main_sdmem2block_fifo_level - connect \B 1'1 - connect \Y $add$ls180.v:8764$2734_Y - end - attribute \src "ls180.v:2840.9-2840.90" - cell $and $and$ls180.v:2840$29 + attribute \src "ls180.v:1567.9-1567.80" + cell $and $and$ls180.v:1567$34 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface0_converted_interface_stb - connect \B \main_interface0_converted_interface_cyc - connect \Y $and$ls180.v:2840$29_Y + connect \A \interface0_converted_interface_stb + connect \B \interface0_converted_interface_cyc + connect \Y $and$ls180.v:1567$34_Y end - attribute \src "ls180.v:2858.9-2858.90" - cell $and $and$ls180.v:2858$36 + attribute \src "ls180.v:1609.9-1609.80" + cell $and $and$ls180.v:1609$38 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface0_converted_interface_stb - connect \B \main_interface0_converted_interface_cyc - connect \Y $and$ls180.v:2858$36_Y + connect \A \interface1_converted_interface_stb + connect \B \interface1_converted_interface_cyc + connect \Y $and$ls180.v:1609$38_Y end - attribute \src "ls180.v:2900.9-2900.90" - cell $and $and$ls180.v:2900$40 + attribute \src "ls180.v:1627.9-1627.80" + cell $and $and$ls180.v:1627$45 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface1_converted_interface_stb - connect \B \main_interface1_converted_interface_cyc - connect \Y $and$ls180.v:2900$40_Y + connect \A \interface1_converted_interface_stb + connect \B \interface1_converted_interface_cyc + connect \Y $and$ls180.v:1627$45_Y end - attribute \src "ls180.v:2918.9-2918.90" - cell $and $and$ls180.v:2918$47 + attribute \src "ls180.v:1669.9-1669.86" + cell $and $and$ls180.v:1669$49 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface1_converted_interface_stb - connect \B \main_interface1_converted_interface_cyc - connect \Y $and$ls180.v:2918$47_Y + connect \A \socbushandler_converted_interface_stb + connect \B \socbushandler_converted_interface_cyc + connect \Y $and$ls180.v:1669$49_Y end - attribute \src "ls180.v:2960.9-2960.96" - cell $and $and$ls180.v:2960$51 + attribute \src "ls180.v:1687.9-1687.86" + cell $and $and$ls180.v:1687$56 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_socbushandler_converted_interface_stb - connect \B \main_socbushandler_converted_interface_cyc - connect \Y $and$ls180.v:2960$51_Y + connect \A \socbushandler_converted_interface_stb + connect \B \socbushandler_converted_interface_cyc + connect \Y $and$ls180.v:1687$56_Y end - attribute \src "ls180.v:2978.9-2978.96" - cell $and $and$ls180.v:2978$58 + attribute \src "ls180.v:1697.26-1697.75" + cell $and $and$ls180.v:1697$58 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_socbushandler_converted_interface_stb - connect \B \main_socbushandler_converted_interface_cyc - connect \Y $and$ls180.v:2978$58_Y + connect \A \libresocsim_ram_bus_cyc + connect \B \libresocsim_ram_bus_stb + connect \Y $and$ls180.v:1697$58_Y end - attribute \src "ls180.v:2988.31-2988.90" - cell $and $and$ls180.v:2988$60 + attribute \src "ls180.v:1697.25-1697.101" + cell $and $and$ls180.v:1697$59 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:2988$60_Y + connect \A $and$ls180.v:1697$58_Y + connect \B \libresocsim_ram_bus_we + connect \Y $and$ls180.v:1697$59_Y end - attribute \src "ls180.v:2988.30-2988.121" - cell $and $and$ls180.v:2988$61 + attribute \src "ls180.v:1697.24-1697.131" + cell $and $and$ls180.v:1697$60 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2988$60_Y - connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:2988$61_Y + connect \A $and$ls180.v:1697$59_Y + connect \B \libresocsim_ram_bus_sel [0] + connect \Y $and$ls180.v:1697$60_Y end - attribute \src "ls180.v:2988.29-2988.156" - cell $and $and$ls180.v:2988$62 + attribute \src "ls180.v:1698.26-1698.75" + cell $and $and$ls180.v:1698$61 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2988$61_Y - connect \B \main_libresocsim_ram_bus_sel [0] - connect \Y $and$ls180.v:2988$62_Y + connect \A \libresocsim_ram_bus_cyc + connect \B \libresocsim_ram_bus_stb + connect \Y $and$ls180.v:1698$61_Y end - attribute \src "ls180.v:2989.31-2989.90" - cell $and $and$ls180.v:2989$63 + attribute \src "ls180.v:1698.25-1698.101" + cell $and $and$ls180.v:1698$62 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:2989$63_Y + connect \A $and$ls180.v:1698$61_Y + connect \B \libresocsim_ram_bus_we + connect \Y $and$ls180.v:1698$62_Y end - attribute \src "ls180.v:2989.30-2989.121" - cell $and $and$ls180.v:2989$64 + attribute \src "ls180.v:1698.24-1698.131" + cell $and $and$ls180.v:1698$63 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2989$63_Y - connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:2989$64_Y + connect \A $and$ls180.v:1698$62_Y + connect \B \libresocsim_ram_bus_sel [1] + connect \Y $and$ls180.v:1698$63_Y end - attribute \src "ls180.v:2989.29-2989.156" - cell $and $and$ls180.v:2989$65 + attribute \src "ls180.v:1699.26-1699.75" + cell $and $and$ls180.v:1699$64 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2989$64_Y - connect \B \main_libresocsim_ram_bus_sel [1] - connect \Y $and$ls180.v:2989$65_Y + connect \A \libresocsim_ram_bus_cyc + connect \B \libresocsim_ram_bus_stb + connect \Y $and$ls180.v:1699$64_Y end - attribute \src "ls180.v:2990.31-2990.90" - cell $and $and$ls180.v:2990$66 + attribute \src "ls180.v:1699.25-1699.101" + cell $and $and$ls180.v:1699$65 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:2990$66_Y + connect \A $and$ls180.v:1699$64_Y + connect \B \libresocsim_ram_bus_we + connect \Y $and$ls180.v:1699$65_Y end - attribute \src "ls180.v:2990.30-2990.121" - cell $and $and$ls180.v:2990$67 + attribute \src "ls180.v:1699.24-1699.131" + cell $and $and$ls180.v:1699$66 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2990$66_Y - connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:2990$67_Y + connect \A $and$ls180.v:1699$65_Y + connect \B \libresocsim_ram_bus_sel [2] + connect \Y $and$ls180.v:1699$66_Y end - attribute \src "ls180.v:2990.29-2990.156" - cell $and $and$ls180.v:2990$68 + attribute \src "ls180.v:1700.26-1700.75" + cell $and $and$ls180.v:1700$67 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2990$67_Y - connect \B \main_libresocsim_ram_bus_sel [2] - connect \Y $and$ls180.v:2990$68_Y + connect \A \libresocsim_ram_bus_cyc + connect \B \libresocsim_ram_bus_stb + connect \Y $and$ls180.v:1700$67_Y end - attribute \src "ls180.v:2991.31-2991.90" - cell $and $and$ls180.v:2991$69 + attribute \src "ls180.v:1700.25-1700.101" + cell $and $and$ls180.v:1700$68 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:2991$69_Y + connect \A $and$ls180.v:1700$67_Y + connect \B \libresocsim_ram_bus_we + connect \Y $and$ls180.v:1700$68_Y end - attribute \src "ls180.v:2991.30-2991.121" - cell $and $and$ls180.v:2991$70 + attribute \src "ls180.v:1700.24-1700.131" + cell $and $and$ls180.v:1700$69 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2991$69_Y - connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:2991$70_Y + connect \A $and$ls180.v:1700$68_Y + connect \B \libresocsim_ram_bus_sel [3] + connect \Y $and$ls180.v:1700$69_Y end - attribute \src "ls180.v:2991.29-2991.156" - cell $and $and$ls180.v:2991$71 + attribute \src "ls180.v:1701.26-1701.75" + cell $and $and$ls180.v:1701$70 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2991$70_Y - connect \B \main_libresocsim_ram_bus_sel [3] - connect \Y $and$ls180.v:2991$71_Y + connect \A \libresocsim_ram_bus_cyc + connect \B \libresocsim_ram_bus_stb + connect \Y $and$ls180.v:1701$70_Y end - attribute \src "ls180.v:2992.31-2992.90" - cell $and $and$ls180.v:2992$72 + attribute \src "ls180.v:1701.25-1701.101" + cell $and $and$ls180.v:1701$71 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:2992$72_Y + connect \A $and$ls180.v:1701$70_Y + connect \B \libresocsim_ram_bus_we + connect \Y $and$ls180.v:1701$71_Y end - attribute \src "ls180.v:2992.30-2992.121" - cell $and $and$ls180.v:2992$73 + attribute \src "ls180.v:1701.24-1701.131" + cell $and $and$ls180.v:1701$72 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2992$72_Y - connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:2992$73_Y + connect \A $and$ls180.v:1701$71_Y + connect \B \libresocsim_ram_bus_sel [4] + connect \Y $and$ls180.v:1701$72_Y end - attribute \src "ls180.v:2992.29-2992.156" - cell $and $and$ls180.v:2992$74 + attribute \src "ls180.v:1702.26-1702.75" + cell $and $and$ls180.v:1702$73 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2992$73_Y - connect \B \main_libresocsim_ram_bus_sel [4] - connect \Y $and$ls180.v:2992$74_Y + connect \A \libresocsim_ram_bus_cyc + connect \B \libresocsim_ram_bus_stb + connect \Y $and$ls180.v:1702$73_Y end - attribute \src "ls180.v:2993.31-2993.90" - cell $and $and$ls180.v:2993$75 + attribute \src "ls180.v:1702.25-1702.101" + cell $and $and$ls180.v:1702$74 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:2993$75_Y + connect \A $and$ls180.v:1702$73_Y + connect \B \libresocsim_ram_bus_we + connect \Y $and$ls180.v:1702$74_Y end - attribute \src "ls180.v:2993.30-2993.121" - cell $and $and$ls180.v:2993$76 + attribute \src "ls180.v:1702.24-1702.131" + cell $and $and$ls180.v:1702$75 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2993$75_Y - connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:2993$76_Y + connect \A $and$ls180.v:1702$74_Y + connect \B \libresocsim_ram_bus_sel [5] + connect \Y $and$ls180.v:1702$75_Y end - attribute \src "ls180.v:2993.29-2993.156" - cell $and $and$ls180.v:2993$77 + attribute \src "ls180.v:1703.26-1703.75" + cell $and $and$ls180.v:1703$76 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2993$76_Y - connect \B \main_libresocsim_ram_bus_sel [5] - connect \Y $and$ls180.v:2993$77_Y + connect \A \libresocsim_ram_bus_cyc + connect \B \libresocsim_ram_bus_stb + connect \Y $and$ls180.v:1703$76_Y end - attribute \src "ls180.v:2994.31-2994.90" - cell $and $and$ls180.v:2994$78 + attribute \src "ls180.v:1703.25-1703.101" + cell $and $and$ls180.v:1703$77 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:2994$78_Y + connect \A $and$ls180.v:1703$76_Y + connect \B \libresocsim_ram_bus_we + connect \Y $and$ls180.v:1703$77_Y end - attribute \src "ls180.v:2994.30-2994.121" - cell $and $and$ls180.v:2994$79 + attribute \src "ls180.v:1703.24-1703.131" + cell $and $and$ls180.v:1703$78 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2994$78_Y - connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:2994$79_Y + connect \A $and$ls180.v:1703$77_Y + connect \B \libresocsim_ram_bus_sel [6] + connect \Y $and$ls180.v:1703$78_Y end - attribute \src "ls180.v:2994.29-2994.156" - cell $and $and$ls180.v:2994$80 + attribute \src "ls180.v:1704.26-1704.75" + cell $and $and$ls180.v:1704$79 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2994$79_Y - connect \B \main_libresocsim_ram_bus_sel [6] - connect \Y $and$ls180.v:2994$80_Y + connect \A \libresocsim_ram_bus_cyc + connect \B \libresocsim_ram_bus_stb + connect \Y $and$ls180.v:1704$79_Y end - attribute \src "ls180.v:2995.31-2995.90" - cell $and $and$ls180.v:2995$81 + attribute \src "ls180.v:1704.25-1704.101" + cell $and $and$ls180.v:1704$80 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:2995$81_Y + connect \A $and$ls180.v:1704$79_Y + connect \B \libresocsim_ram_bus_we + connect \Y $and$ls180.v:1704$80_Y end - attribute \src "ls180.v:2995.30-2995.121" - cell $and $and$ls180.v:2995$82 + attribute \src "ls180.v:1704.24-1704.131" + cell $and $and$ls180.v:1704$81 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2995$81_Y - connect \B \main_libresocsim_ram_bus_we - connect \Y $and$ls180.v:2995$82_Y + connect \A $and$ls180.v:1704$80_Y + connect \B \libresocsim_ram_bus_sel [7] + connect \Y $and$ls180.v:1704$81_Y end - attribute \src "ls180.v:2995.29-2995.156" - cell $and $and$ls180.v:2995$83 + attribute \src "ls180.v:1713.7-1713.79" + cell $and $and$ls180.v:1713$84 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:2995$82_Y - connect \B \main_libresocsim_ram_bus_sel [7] - connect \Y $and$ls180.v:2995$83_Y + connect \A \libresocsim_eventmanager_pending_re + connect \B \libresocsim_eventmanager_pending_r + connect \Y $and$ls180.v:1713$84_Y end - attribute \src "ls180.v:3004.7-3004.89" - cell $and $and$ls180.v:3004$86 + attribute \src "ls180.v:1718.27-1718.96" + cell $and $and$ls180.v:1718$85 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_eventmanager_pending_re - connect \B \main_libresocsim_eventmanager_pending_r - connect \Y $and$ls180.v:3004$86_Y + connect \A \libresocsim_eventmanager_pending_w + connect \B \libresocsim_eventmanager_storage + connect \Y $and$ls180.v:1718$85_Y end - attribute \src "ls180.v:3009.32-3009.111" - cell $and $and$ls180.v:3009$87 + attribute \src "ls180.v:1722.18-1722.59" + cell $and $and$ls180.v:1722$87 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_eventmanager_pending_w - connect \B \main_libresocsim_eventmanager_storage - connect \Y $and$ls180.v:3009$87_Y + connect \A \ram_bus_ram_bus_cyc + connect \B \ram_bus_ram_bus_stb + connect \Y $and$ls180.v:1722$87_Y end - attribute \src "ls180.v:3013.23-3013.74" - cell $and $and$ls180.v:3013$89 + attribute \src "ls180.v:1722.17-1722.81" + cell $and $and$ls180.v:1722$88 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_ram_bus_ram_bus_cyc - connect \B \main_ram_bus_ram_bus_stb - connect \Y $and$ls180.v:3013$89_Y + connect \A $and$ls180.v:1722$87_Y + connect \B \ram_bus_ram_bus_we + connect \Y $and$ls180.v:1722$88_Y end - attribute \src "ls180.v:3013.22-3013.101" - cell $and $and$ls180.v:3013$90 + attribute \src "ls180.v:1722.16-1722.107" + cell $and $and$ls180.v:1722$89 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3013$89_Y - connect \B \main_ram_bus_ram_bus_we - connect \Y $and$ls180.v:3013$90_Y + connect \A $and$ls180.v:1722$88_Y + connect \B \ram_bus_ram_bus_sel [0] + connect \Y $and$ls180.v:1722$89_Y end - attribute \src "ls180.v:3013.21-3013.132" - cell $and $and$ls180.v:3013$91 + attribute \src "ls180.v:1723.18-1723.59" + cell $and $and$ls180.v:1723$90 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3013$90_Y - connect \B \main_ram_bus_ram_bus_sel [0] - connect \Y $and$ls180.v:3013$91_Y + connect \A \ram_bus_ram_bus_cyc + connect \B \ram_bus_ram_bus_stb + connect \Y $and$ls180.v:1723$90_Y end - attribute \src "ls180.v:3014.23-3014.74" - cell $and $and$ls180.v:3014$92 + attribute \src "ls180.v:1723.17-1723.81" + cell $and $and$ls180.v:1723$91 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_ram_bus_ram_bus_cyc - connect \B \main_ram_bus_ram_bus_stb - connect \Y $and$ls180.v:3014$92_Y + connect \A $and$ls180.v:1723$90_Y + connect \B \ram_bus_ram_bus_we + connect \Y $and$ls180.v:1723$91_Y end - attribute \src "ls180.v:3014.22-3014.101" - cell $and $and$ls180.v:3014$93 + attribute \src "ls180.v:1723.16-1723.107" + cell $and $and$ls180.v:1723$92 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3014$92_Y - connect \B \main_ram_bus_ram_bus_we - connect \Y $and$ls180.v:3014$93_Y + connect \A $and$ls180.v:1723$91_Y + connect \B \ram_bus_ram_bus_sel [1] + connect \Y $and$ls180.v:1723$92_Y end - attribute \src "ls180.v:3014.21-3014.132" - cell $and $and$ls180.v:3014$94 + attribute \src "ls180.v:1724.18-1724.59" + cell $and $and$ls180.v:1724$93 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3014$93_Y - connect \B \main_ram_bus_ram_bus_sel [1] - connect \Y $and$ls180.v:3014$94_Y + connect \A \ram_bus_ram_bus_cyc + connect \B \ram_bus_ram_bus_stb + connect \Y $and$ls180.v:1724$93_Y end - attribute \src "ls180.v:3015.23-3015.74" - cell $and $and$ls180.v:3015$95 + attribute \src "ls180.v:1724.17-1724.81" + cell $and $and$ls180.v:1724$94 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_ram_bus_ram_bus_cyc - connect \B \main_ram_bus_ram_bus_stb - connect \Y $and$ls180.v:3015$95_Y + connect \A $and$ls180.v:1724$93_Y + connect \B \ram_bus_ram_bus_we + connect \Y $and$ls180.v:1724$94_Y end - attribute \src "ls180.v:3015.22-3015.101" - cell $and $and$ls180.v:3015$96 + attribute \src "ls180.v:1724.16-1724.107" + cell $and $and$ls180.v:1724$95 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3015$95_Y - connect \B \main_ram_bus_ram_bus_we - connect \Y $and$ls180.v:3015$96_Y + connect \A $and$ls180.v:1724$94_Y + connect \B \ram_bus_ram_bus_sel [2] + connect \Y $and$ls180.v:1724$95_Y end - attribute \src "ls180.v:3015.21-3015.132" - cell $and $and$ls180.v:3015$97 + attribute \src "ls180.v:1725.18-1725.59" + cell $and $and$ls180.v:1725$96 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3015$96_Y - connect \B \main_ram_bus_ram_bus_sel [2] - connect \Y $and$ls180.v:3015$97_Y + connect \A \ram_bus_ram_bus_cyc + connect \B \ram_bus_ram_bus_stb + connect \Y $and$ls180.v:1725$96_Y end - attribute \src "ls180.v:3016.21-3016.132" - cell $and $and$ls180.v:3016$100 + attribute \src "ls180.v:1725.17-1725.81" + cell $and $and$ls180.v:1725$97 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3016$99_Y - connect \B \main_ram_bus_ram_bus_sel [3] - connect \Y $and$ls180.v:3016$100_Y + connect \A $and$ls180.v:1725$96_Y + connect \B \ram_bus_ram_bus_we + connect \Y $and$ls180.v:1725$97_Y end - attribute \src "ls180.v:3016.23-3016.74" - cell $and $and$ls180.v:3016$98 + attribute \src "ls180.v:1725.16-1725.107" + cell $and $and$ls180.v:1725$98 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_ram_bus_ram_bus_cyc - connect \B \main_ram_bus_ram_bus_stb - connect \Y $and$ls180.v:3016$98_Y + connect \A $and$ls180.v:1725$97_Y + connect \B \ram_bus_ram_bus_sel [3] + connect \Y $and$ls180.v:1725$98_Y end - attribute \src "ls180.v:3016.22-3016.101" - cell $and $and$ls180.v:3016$99 + attribute \src "ls180.v:1726.17-1726.81" + cell $and $and$ls180.v:1726$100 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3016$98_Y - connect \B \main_ram_bus_ram_bus_we - connect \Y $and$ls180.v:3016$99_Y + connect \A $and$ls180.v:1726$99_Y + connect \B \ram_bus_ram_bus_we + connect \Y $and$ls180.v:1726$100_Y end - attribute \src "ls180.v:3017.23-3017.74" - cell $and $and$ls180.v:3017$101 + attribute \src "ls180.v:1726.16-1726.107" + cell $and $and$ls180.v:1726$101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_ram_bus_ram_bus_cyc - connect \B \main_ram_bus_ram_bus_stb - connect \Y $and$ls180.v:3017$101_Y + connect \A $and$ls180.v:1726$100_Y + connect \B \ram_bus_ram_bus_sel [4] + connect \Y $and$ls180.v:1726$101_Y end - attribute \src "ls180.v:3017.22-3017.101" - cell $and $and$ls180.v:3017$102 + attribute \src "ls180.v:1726.18-1726.59" + cell $and $and$ls180.v:1726$99 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3017$101_Y - connect \B \main_ram_bus_ram_bus_we - connect \Y $and$ls180.v:3017$102_Y + connect \A \ram_bus_ram_bus_cyc + connect \B \ram_bus_ram_bus_stb + connect \Y $and$ls180.v:1726$99_Y end - attribute \src "ls180.v:3017.21-3017.132" - cell $and $and$ls180.v:3017$103 + attribute \src "ls180.v:1727.18-1727.59" + cell $and $and$ls180.v:1727$102 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3017$102_Y - connect \B \main_ram_bus_ram_bus_sel [4] - connect \Y $and$ls180.v:3017$103_Y + connect \A \ram_bus_ram_bus_cyc + connect \B \ram_bus_ram_bus_stb + connect \Y $and$ls180.v:1727$102_Y end - attribute \src "ls180.v:3018.23-3018.74" - cell $and $and$ls180.v:3018$104 + attribute \src "ls180.v:1727.17-1727.81" + cell $and $and$ls180.v:1727$103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_ram_bus_ram_bus_cyc - connect \B \main_ram_bus_ram_bus_stb - connect \Y $and$ls180.v:3018$104_Y + connect \A $and$ls180.v:1727$102_Y + connect \B \ram_bus_ram_bus_we + connect \Y $and$ls180.v:1727$103_Y end - attribute \src "ls180.v:3018.22-3018.101" - cell $and $and$ls180.v:3018$105 + attribute \src "ls180.v:1727.16-1727.107" + cell $and $and$ls180.v:1727$104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3018$104_Y - connect \B \main_ram_bus_ram_bus_we - connect \Y $and$ls180.v:3018$105_Y + connect \A $and$ls180.v:1727$103_Y + connect \B \ram_bus_ram_bus_sel [5] + connect \Y $and$ls180.v:1727$104_Y end - attribute \src "ls180.v:3018.21-3018.132" - cell $and $and$ls180.v:3018$106 + attribute \src "ls180.v:1728.18-1728.59" + cell $and $and$ls180.v:1728$105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3018$105_Y - connect \B \main_ram_bus_ram_bus_sel [5] - connect \Y $and$ls180.v:3018$106_Y + connect \A \ram_bus_ram_bus_cyc + connect \B \ram_bus_ram_bus_stb + connect \Y $and$ls180.v:1728$105_Y end - attribute \src "ls180.v:3019.23-3019.74" - cell $and $and$ls180.v:3019$107 + attribute \src "ls180.v:1728.17-1728.81" + cell $and $and$ls180.v:1728$106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_ram_bus_ram_bus_cyc - connect \B \main_ram_bus_ram_bus_stb - connect \Y $and$ls180.v:3019$107_Y + connect \A $and$ls180.v:1728$105_Y + connect \B \ram_bus_ram_bus_we + connect \Y $and$ls180.v:1728$106_Y end - attribute \src "ls180.v:3019.22-3019.101" - cell $and $and$ls180.v:3019$108 + attribute \src "ls180.v:1728.16-1728.107" + cell $and $and$ls180.v:1728$107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3019$107_Y - connect \B \main_ram_bus_ram_bus_we - connect \Y $and$ls180.v:3019$108_Y + connect \A $and$ls180.v:1728$106_Y + connect \B \ram_bus_ram_bus_sel [6] + connect \Y $and$ls180.v:1728$107_Y end - attribute \src "ls180.v:3019.21-3019.132" - cell $and $and$ls180.v:3019$109 + attribute \src "ls180.v:1729.18-1729.59" + cell $and $and$ls180.v:1729$108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3019$108_Y - connect \B \main_ram_bus_ram_bus_sel [6] - connect \Y $and$ls180.v:3019$109_Y + connect \A \ram_bus_ram_bus_cyc + connect \B \ram_bus_ram_bus_stb + connect \Y $and$ls180.v:1729$108_Y end - attribute \src "ls180.v:3020.23-3020.74" - cell $and $and$ls180.v:3020$110 + attribute \src "ls180.v:1729.17-1729.81" + cell $and $and$ls180.v:1729$109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_ram_bus_ram_bus_cyc - connect \B \main_ram_bus_ram_bus_stb - connect \Y $and$ls180.v:3020$110_Y + connect \A $and$ls180.v:1729$108_Y + connect \B \ram_bus_ram_bus_we + connect \Y $and$ls180.v:1729$109_Y end - attribute \src "ls180.v:3020.22-3020.101" - cell $and $and$ls180.v:3020$111 + attribute \src "ls180.v:1729.16-1729.107" + cell $and $and$ls180.v:1729$110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3020$110_Y - connect \B \main_ram_bus_ram_bus_we - connect \Y $and$ls180.v:3020$111_Y + connect \A $and$ls180.v:1729$109_Y + connect \B \ram_bus_ram_bus_sel [7] + connect \Y $and$ls180.v:1729$110_Y end - attribute \src "ls180.v:3020.21-3020.132" - cell $and $and$ls180.v:3020$112 + attribute \src "ls180.v:1846.35-1846.84" + cell $and $and$ls180.v:1846$117 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3020$111_Y - connect \B \main_ram_bus_ram_bus_sel [7] - connect \Y $and$ls180.v:3020$112_Y + connect \A \sdram_command_issue_re + connect \B \sdram_command_storage [4] + connect \Y $and$ls180.v:1846$117_Y end - attribute \src "ls180.v:3137.40-3137.99" - cell $and $and$ls180.v:3137$119 + attribute \src "ls180.v:1847.35-1847.84" + cell $and $and$ls180.v:1847$118 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_command_issue_re - connect \B \main_sdram_command_storage [4] - connect \Y $and$ls180.v:3137$119_Y + connect \A \sdram_command_issue_re + connect \B \sdram_command_storage [5] + connect \Y $and$ls180.v:1847$118_Y end - attribute \src "ls180.v:3138.40-3138.99" - cell $and $and$ls180.v:3138$120 + attribute \src "ls180.v:1885.33-1885.88" + cell $and $and$ls180.v:1885$124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_command_issue_re - connect \B \main_sdram_command_storage [5] - connect \Y $and$ls180.v:3138$120_Y + connect \A \sdram_sequencer_done1 + connect \B $eq$ls180.v:1885$123_Y + connect \Y $and$ls180.v:1885$124_Y end - attribute \src "ls180.v:3176.38-3176.103" - cell $and $and$ls180.v:3176$126 + attribute \src "ls180.v:1939.45-1939.104" + cell $and $and$ls180.v:1939$132 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_done1 - connect \B $eq$ls180.v:3176$125_Y - connect \Y $and$ls180.v:3176$126_Y + connect \A \sdram_bankmachine0_cmd_valid + connect \B \sdram_bankmachine0_cmd_ready + connect \Y $and$ls180.v:1939$132_Y end - attribute \src "ls180.v:3230.50-3230.119" - cell $and $and$ls180.v:3230$134 + attribute \src "ls180.v:1939.44-1939.147" + cell $and $and$ls180.v:1939$133 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B \main_sdram_bankmachine0_cmd_ready - connect \Y $and$ls180.v:3230$134_Y + connect \A $and$ls180.v:1939$132_Y + connect \B \sdram_bankmachine0_cmd_payload_is_write + connect \Y $and$ls180.v:1939$133_Y end - attribute \src "ls180.v:3230.49-3230.167" - cell $and $and$ls180.v:3230$135 + attribute \src "ls180.v:1940.44-1940.103" + cell $and $and$ls180.v:1940$134 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3230$134_Y - connect \B \main_sdram_bankmachine0_cmd_payload_is_write - connect \Y $and$ls180.v:3230$135_Y + connect \A \sdram_bankmachine0_cmd_valid + connect \B \sdram_bankmachine0_cmd_ready + connect \Y $and$ls180.v:1940$134_Y end - attribute \src "ls180.v:3231.49-3231.118" - cell $and $and$ls180.v:3231$136 + attribute \src "ls180.v:1940.43-1940.134" + cell $and $and$ls180.v:1940$135 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B \main_sdram_bankmachine0_cmd_ready - connect \Y $and$ls180.v:3231$136_Y + connect \A $and$ls180.v:1940$134_Y + connect \B \sdram_bankmachine0_row_open + connect \Y $and$ls180.v:1940$135_Y end - attribute \src "ls180.v:3231.48-3231.154" - cell $and $and$ls180.v:3231$137 + attribute \src "ls180.v:1941.45-1941.104" + cell $and $and$ls180.v:1941$136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3231$136_Y - connect \B \main_sdram_bankmachine0_row_open - connect \Y $and$ls180.v:3231$137_Y + connect \A \sdram_bankmachine0_cmd_valid + connect \B \sdram_bankmachine0_cmd_ready + connect \Y $and$ls180.v:1941$136_Y end - attribute \src "ls180.v:3232.50-3232.119" - cell $and $and$ls180.v:3232$138 + attribute \src "ls180.v:1941.44-1941.135" + cell $and $and$ls180.v:1941$137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B \main_sdram_bankmachine0_cmd_ready - connect \Y $and$ls180.v:3232$138_Y + connect \A $and$ls180.v:1941$136_Y + connect \B \sdram_bankmachine0_row_open + connect \Y $and$ls180.v:1941$137_Y end - attribute \src "ls180.v:3232.49-3232.155" - cell $and $and$ls180.v:3232$139 + attribute \src "ls180.v:1944.7-1944.104" + cell $and $and$ls180.v:1944$139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3232$138_Y - connect \B \main_sdram_bankmachine0_row_open - connect \Y $and$ls180.v:3232$139_Y + connect \A \sdram_bankmachine0_cmd_buffer_lookahead_source_valid + connect \B \sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $and$ls180.v:1944$139_Y end - attribute \src "ls180.v:3235.7-3235.114" - cell $and $and$ls180.v:3235$141 + attribute \src "ls180.v:1973.61-1973.226" + cell $and $and$ls180.v:1973$145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $and$ls180.v:3235$141_Y + connect \A \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + connect \B $or$ls180.v:1973$144_Y + connect \Y $and$ls180.v:1973$145_Y end - attribute \src "ls180.v:3264.66-3264.246" - cell $and $and$ls180.v:3264$147 + attribute \src "ls180.v:1974.59-1974.172" + cell $and $and$ls180.v:1974$146 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we - connect \B $or$ls180.v:3264$146_Y - connect \Y $and$ls180.v:3264$147_Y + connect \A \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable + connect \B \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re + connect \Y $and$ls180.v:1974$146_Y end - attribute \src "ls180.v:3265.64-3265.187" - cell $and $and$ls180.v:3265$148 + attribute \src "ls180.v:1998.9-1998.76" + cell $and $and$ls180.v:1998$152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable - connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re - connect \Y $and$ls180.v:3265$148_Y + connect \A \sdram_bankmachine0_twtpcon_ready + connect \B \sdram_bankmachine0_trascon_ready + connect \Y $and$ls180.v:1998$152_Y end - attribute \src "ls180.v:3289.9-3289.86" - cell $and $and$ls180.v:3289$154 + attribute \src "ls180.v:2010.9-2010.76" + cell $and $and$ls180.v:2010$153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_twtpcon_ready - connect \B \main_sdram_bankmachine0_trascon_ready - connect \Y $and$ls180.v:3289$154_Y + connect \A \sdram_bankmachine0_twtpcon_ready + connect \B \sdram_bankmachine0_trascon_ready + connect \Y $and$ls180.v:2010$153_Y end - attribute \src "ls180.v:3301.9-3301.86" - cell $and $and$ls180.v:3301$155 + attribute \src "ls180.v:2060.13-2060.77" + cell $and $and$ls180.v:2060$155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_twtpcon_ready - connect \B \main_sdram_bankmachine0_trascon_ready - connect \Y $and$ls180.v:3301$155_Y + connect \A \sdram_bankmachine0_cmd_ready + connect \B \sdram_bankmachine0_auto_precharge + connect \Y $and$ls180.v:2060$155_Y end - attribute \src "ls180.v:3351.13-3351.87" - cell $and $and$ls180.v:3351$157 + attribute \src "ls180.v:2096.45-2096.104" + cell $and $and$ls180.v:2096$162 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_ready - connect \B \main_sdram_bankmachine0_auto_precharge - connect \Y $and$ls180.v:3351$157_Y + connect \A \sdram_bankmachine1_cmd_valid + connect \B \sdram_bankmachine1_cmd_ready + connect \Y $and$ls180.v:2096$162_Y end - attribute \src "ls180.v:3387.50-3387.119" - cell $and $and$ls180.v:3387$164 + attribute \src "ls180.v:2096.44-2096.147" + cell $and $and$ls180.v:2096$163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B \main_sdram_bankmachine1_cmd_ready - connect \Y $and$ls180.v:3387$164_Y + connect \A $and$ls180.v:2096$162_Y + connect \B \sdram_bankmachine1_cmd_payload_is_write + connect \Y $and$ls180.v:2096$163_Y end - attribute \src "ls180.v:3387.49-3387.167" - cell $and $and$ls180.v:3387$165 + attribute \src "ls180.v:2097.44-2097.103" + cell $and $and$ls180.v:2097$164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3387$164_Y - connect \B \main_sdram_bankmachine1_cmd_payload_is_write - connect \Y $and$ls180.v:3387$165_Y + connect \A \sdram_bankmachine1_cmd_valid + connect \B \sdram_bankmachine1_cmd_ready + connect \Y $and$ls180.v:2097$164_Y end - attribute \src "ls180.v:3388.49-3388.118" - cell $and $and$ls180.v:3388$166 + attribute \src "ls180.v:2097.43-2097.134" + cell $and $and$ls180.v:2097$165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B \main_sdram_bankmachine1_cmd_ready - connect \Y $and$ls180.v:3388$166_Y + connect \A $and$ls180.v:2097$164_Y + connect \B \sdram_bankmachine1_row_open + connect \Y $and$ls180.v:2097$165_Y end - attribute \src "ls180.v:3388.48-3388.154" - cell $and $and$ls180.v:3388$167 + attribute \src "ls180.v:2098.45-2098.104" + cell $and $and$ls180.v:2098$166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3388$166_Y - connect \B \main_sdram_bankmachine1_row_open - connect \Y $and$ls180.v:3388$167_Y + connect \A \sdram_bankmachine1_cmd_valid + connect \B \sdram_bankmachine1_cmd_ready + connect \Y $and$ls180.v:2098$166_Y end - attribute \src "ls180.v:3389.50-3389.119" - cell $and $and$ls180.v:3389$168 + attribute \src "ls180.v:2098.44-2098.135" + cell $and $and$ls180.v:2098$167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B \main_sdram_bankmachine1_cmd_ready - connect \Y $and$ls180.v:3389$168_Y + connect \A $and$ls180.v:2098$166_Y + connect \B \sdram_bankmachine1_row_open + connect \Y $and$ls180.v:2098$167_Y end - attribute \src "ls180.v:3389.49-3389.155" - cell $and $and$ls180.v:3389$169 + attribute \src "ls180.v:2101.7-2101.104" + cell $and $and$ls180.v:2101$169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3389$168_Y - connect \B \main_sdram_bankmachine1_row_open - connect \Y $and$ls180.v:3389$169_Y + connect \A \sdram_bankmachine1_cmd_buffer_lookahead_source_valid + connect \B \sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $and$ls180.v:2101$169_Y end - attribute \src "ls180.v:3392.7-3392.114" - cell $and $and$ls180.v:3392$171 + attribute \src "ls180.v:2130.61-2130.226" + cell $and $and$ls180.v:2130$175 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $and$ls180.v:3392$171_Y + connect \A \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + connect \B $or$ls180.v:2130$174_Y + connect \Y $and$ls180.v:2130$175_Y end - attribute \src "ls180.v:3421.66-3421.246" - cell $and $and$ls180.v:3421$177 + attribute \src "ls180.v:2131.59-2131.172" + cell $and $and$ls180.v:2131$176 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we - connect \B $or$ls180.v:3421$176_Y - connect \Y $and$ls180.v:3421$177_Y + connect \A \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable + connect \B \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re + connect \Y $and$ls180.v:2131$176_Y end - attribute \src "ls180.v:3422.64-3422.187" - cell $and $and$ls180.v:3422$178 + attribute \src "ls180.v:2155.9-2155.76" + cell $and $and$ls180.v:2155$182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable - connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re - connect \Y $and$ls180.v:3422$178_Y + connect \A \sdram_bankmachine1_twtpcon_ready + connect \B \sdram_bankmachine1_trascon_ready + connect \Y $and$ls180.v:2155$182_Y end - attribute \src "ls180.v:3446.9-3446.86" - cell $and $and$ls180.v:3446$184 + attribute \src "ls180.v:2167.9-2167.76" + cell $and $and$ls180.v:2167$183 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_twtpcon_ready - connect \B \main_sdram_bankmachine1_trascon_ready - connect \Y $and$ls180.v:3446$184_Y + connect \A \sdram_bankmachine1_twtpcon_ready + connect \B \sdram_bankmachine1_trascon_ready + connect \Y $and$ls180.v:2167$183_Y end - attribute \src "ls180.v:3458.9-3458.86" - cell $and $and$ls180.v:3458$185 + attribute \src "ls180.v:2217.13-2217.77" + cell $and $and$ls180.v:2217$185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_twtpcon_ready - connect \B \main_sdram_bankmachine1_trascon_ready - connect \Y $and$ls180.v:3458$185_Y + connect \A \sdram_bankmachine1_cmd_ready + connect \B \sdram_bankmachine1_auto_precharge + connect \Y $and$ls180.v:2217$185_Y end - attribute \src "ls180.v:3508.13-3508.87" - cell $and $and$ls180.v:3508$187 + attribute \src "ls180.v:2253.45-2253.104" + cell $and $and$ls180.v:2253$192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_ready - connect \B \main_sdram_bankmachine1_auto_precharge - connect \Y $and$ls180.v:3508$187_Y + connect \A \sdram_bankmachine2_cmd_valid + connect \B \sdram_bankmachine2_cmd_ready + connect \Y $and$ls180.v:2253$192_Y end - attribute \src "ls180.v:3544.50-3544.119" - cell $and $and$ls180.v:3544$194 + attribute \src "ls180.v:2253.44-2253.147" + cell $and $and$ls180.v:2253$193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B \main_sdram_bankmachine2_cmd_ready - connect \Y $and$ls180.v:3544$194_Y + connect \A $and$ls180.v:2253$192_Y + connect \B \sdram_bankmachine2_cmd_payload_is_write + connect \Y $and$ls180.v:2253$193_Y end - attribute \src "ls180.v:3544.49-3544.167" - cell $and $and$ls180.v:3544$195 + attribute \src "ls180.v:2254.44-2254.103" + cell $and $and$ls180.v:2254$194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3544$194_Y - connect \B \main_sdram_bankmachine2_cmd_payload_is_write - connect \Y $and$ls180.v:3544$195_Y + connect \A \sdram_bankmachine2_cmd_valid + connect \B \sdram_bankmachine2_cmd_ready + connect \Y $and$ls180.v:2254$194_Y end - attribute \src "ls180.v:3545.49-3545.118" - cell $and $and$ls180.v:3545$196 + attribute \src "ls180.v:2254.43-2254.134" + cell $and $and$ls180.v:2254$195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B \main_sdram_bankmachine2_cmd_ready - connect \Y $and$ls180.v:3545$196_Y + connect \A $and$ls180.v:2254$194_Y + connect \B \sdram_bankmachine2_row_open + connect \Y $and$ls180.v:2254$195_Y end - attribute \src "ls180.v:3545.48-3545.154" - cell $and $and$ls180.v:3545$197 + attribute \src "ls180.v:2255.45-2255.104" + cell $and $and$ls180.v:2255$196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3545$196_Y - connect \B \main_sdram_bankmachine2_row_open - connect \Y $and$ls180.v:3545$197_Y + connect \A \sdram_bankmachine2_cmd_valid + connect \B \sdram_bankmachine2_cmd_ready + connect \Y $and$ls180.v:2255$196_Y end - attribute \src "ls180.v:3546.50-3546.119" - cell $and $and$ls180.v:3546$198 + attribute \src "ls180.v:2255.44-2255.135" + cell $and $and$ls180.v:2255$197 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B \main_sdram_bankmachine2_cmd_ready - connect \Y $and$ls180.v:3546$198_Y + connect \A $and$ls180.v:2255$196_Y + connect \B \sdram_bankmachine2_row_open + connect \Y $and$ls180.v:2255$197_Y end - attribute \src "ls180.v:3546.49-3546.155" - cell $and $and$ls180.v:3546$199 + attribute \src "ls180.v:2258.7-2258.104" + cell $and $and$ls180.v:2258$199 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3546$198_Y - connect \B \main_sdram_bankmachine2_row_open - connect \Y $and$ls180.v:3546$199_Y + connect \A \sdram_bankmachine2_cmd_buffer_lookahead_source_valid + connect \B \sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $and$ls180.v:2258$199_Y end - attribute \src "ls180.v:3549.7-3549.114" - cell $and $and$ls180.v:3549$201 + attribute \src "ls180.v:2287.61-2287.226" + cell $and $and$ls180.v:2287$205 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $and$ls180.v:3549$201_Y + connect \A \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + connect \B $or$ls180.v:2287$204_Y + connect \Y $and$ls180.v:2287$205_Y end - attribute \src "ls180.v:3578.66-3578.246" - cell $and $and$ls180.v:3578$207 + attribute \src "ls180.v:2288.59-2288.172" + cell $and $and$ls180.v:2288$206 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we - connect \B $or$ls180.v:3578$206_Y - connect \Y $and$ls180.v:3578$207_Y + connect \A \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable + connect \B \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re + connect \Y $and$ls180.v:2288$206_Y end - attribute \src "ls180.v:3579.64-3579.187" - cell $and $and$ls180.v:3579$208 + attribute \src "ls180.v:2312.9-2312.76" + cell $and $and$ls180.v:2312$212 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable - connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re - connect \Y $and$ls180.v:3579$208_Y + connect \A \sdram_bankmachine2_twtpcon_ready + connect \B \sdram_bankmachine2_trascon_ready + connect \Y $and$ls180.v:2312$212_Y end - attribute \src "ls180.v:3603.9-3603.86" - cell $and $and$ls180.v:3603$214 + attribute \src "ls180.v:2324.9-2324.76" + cell $and $and$ls180.v:2324$213 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_twtpcon_ready - connect \B \main_sdram_bankmachine2_trascon_ready - connect \Y $and$ls180.v:3603$214_Y + connect \A \sdram_bankmachine2_twtpcon_ready + connect \B \sdram_bankmachine2_trascon_ready + connect \Y $and$ls180.v:2324$213_Y end - attribute \src "ls180.v:3615.9-3615.86" - cell $and $and$ls180.v:3615$215 + attribute \src "ls180.v:2374.13-2374.77" + cell $and $and$ls180.v:2374$215 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_twtpcon_ready - connect \B \main_sdram_bankmachine2_trascon_ready - connect \Y $and$ls180.v:3615$215_Y + connect \A \sdram_bankmachine2_cmd_ready + connect \B \sdram_bankmachine2_auto_precharge + connect \Y $and$ls180.v:2374$215_Y end - attribute \src "ls180.v:3665.13-3665.87" - cell $and $and$ls180.v:3665$217 + attribute \src "ls180.v:2410.45-2410.104" + cell $and $and$ls180.v:2410$222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_ready - connect \B \main_sdram_bankmachine2_auto_precharge - connect \Y $and$ls180.v:3665$217_Y + connect \A \sdram_bankmachine3_cmd_valid + connect \B \sdram_bankmachine3_cmd_ready + connect \Y $and$ls180.v:2410$222_Y end - attribute \src "ls180.v:3701.50-3701.119" - cell $and $and$ls180.v:3701$224 + attribute \src "ls180.v:2410.44-2410.147" + cell $and $and$ls180.v:2410$223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B \main_sdram_bankmachine3_cmd_ready - connect \Y $and$ls180.v:3701$224_Y + connect \A $and$ls180.v:2410$222_Y + connect \B \sdram_bankmachine3_cmd_payload_is_write + connect \Y $and$ls180.v:2410$223_Y end - attribute \src "ls180.v:3701.49-3701.167" - cell $and $and$ls180.v:3701$225 + attribute \src "ls180.v:2411.44-2411.103" + cell $and $and$ls180.v:2411$224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3701$224_Y - connect \B \main_sdram_bankmachine3_cmd_payload_is_write - connect \Y $and$ls180.v:3701$225_Y + connect \A \sdram_bankmachine3_cmd_valid + connect \B \sdram_bankmachine3_cmd_ready + connect \Y $and$ls180.v:2411$224_Y end - attribute \src "ls180.v:3702.49-3702.118" - cell $and $and$ls180.v:3702$226 + attribute \src "ls180.v:2411.43-2411.134" + cell $and $and$ls180.v:2411$225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B \main_sdram_bankmachine3_cmd_ready - connect \Y $and$ls180.v:3702$226_Y + connect \A $and$ls180.v:2411$224_Y + connect \B \sdram_bankmachine3_row_open + connect \Y $and$ls180.v:2411$225_Y end - attribute \src "ls180.v:3702.48-3702.154" - cell $and $and$ls180.v:3702$227 + attribute \src "ls180.v:2412.45-2412.104" + cell $and $and$ls180.v:2412$226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3702$226_Y - connect \B \main_sdram_bankmachine3_row_open - connect \Y $and$ls180.v:3702$227_Y + connect \A \sdram_bankmachine3_cmd_valid + connect \B \sdram_bankmachine3_cmd_ready + connect \Y $and$ls180.v:2412$226_Y end - attribute \src "ls180.v:3703.50-3703.119" - cell $and $and$ls180.v:3703$228 + attribute \src "ls180.v:2412.44-2412.135" + cell $and $and$ls180.v:2412$227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B \main_sdram_bankmachine3_cmd_ready - connect \Y $and$ls180.v:3703$228_Y + connect \A $and$ls180.v:2412$226_Y + connect \B \sdram_bankmachine3_row_open + connect \Y $and$ls180.v:2412$227_Y end - attribute \src "ls180.v:3703.49-3703.155" - cell $and $and$ls180.v:3703$229 + attribute \src "ls180.v:2415.7-2415.104" + cell $and $and$ls180.v:2415$229 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3703$228_Y - connect \B \main_sdram_bankmachine3_row_open - connect \Y $and$ls180.v:3703$229_Y + connect \A \sdram_bankmachine3_cmd_buffer_lookahead_source_valid + connect \B \sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $and$ls180.v:2415$229_Y end - attribute \src "ls180.v:3706.7-3706.114" - cell $and $and$ls180.v:3706$231 + attribute \src "ls180.v:2444.61-2444.226" + cell $and $and$ls180.v:2444$235 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $and$ls180.v:3706$231_Y + connect \A \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + connect \B $or$ls180.v:2444$234_Y + connect \Y $and$ls180.v:2444$235_Y end - attribute \src "ls180.v:3735.66-3735.246" - cell $and $and$ls180.v:3735$237 + attribute \src "ls180.v:2445.59-2445.172" + cell $and $and$ls180.v:2445$236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we - connect \B $or$ls180.v:3735$236_Y - connect \Y $and$ls180.v:3735$237_Y + connect \A \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable + connect \B \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re + connect \Y $and$ls180.v:2445$236_Y end - attribute \src "ls180.v:3736.64-3736.187" - cell $and $and$ls180.v:3736$238 + attribute \src "ls180.v:2469.9-2469.76" + cell $and $and$ls180.v:2469$242 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable - connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re - connect \Y $and$ls180.v:3736$238_Y + connect \A \sdram_bankmachine3_twtpcon_ready + connect \B \sdram_bankmachine3_trascon_ready + connect \Y $and$ls180.v:2469$242_Y end - attribute \src "ls180.v:3760.9-3760.86" - cell $and $and$ls180.v:3760$244 + attribute \src "ls180.v:2481.9-2481.76" + cell $and $and$ls180.v:2481$243 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_twtpcon_ready - connect \B \main_sdram_bankmachine3_trascon_ready - connect \Y $and$ls180.v:3760$244_Y + connect \A \sdram_bankmachine3_twtpcon_ready + connect \B \sdram_bankmachine3_trascon_ready + connect \Y $and$ls180.v:2481$243_Y end - attribute \src "ls180.v:3772.9-3772.86" - cell $and $and$ls180.v:3772$245 + attribute \src "ls180.v:2531.13-2531.77" + cell $and $and$ls180.v:2531$245 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_twtpcon_ready - connect \B \main_sdram_bankmachine3_trascon_ready - connect \Y $and$ls180.v:3772$245_Y + connect \A \sdram_bankmachine3_cmd_ready + connect \B \sdram_bankmachine3_auto_precharge + connect \Y $and$ls180.v:2531$245_Y end - attribute \src "ls180.v:3822.13-3822.87" - cell $and $and$ls180.v:3822$247 + attribute \src "ls180.v:2546.32-2546.87" + cell $and $and$ls180.v:2546$246 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_ready - connect \B \main_sdram_bankmachine3_auto_precharge - connect \Y $and$ls180.v:3822$247_Y + connect \A \sdram_choose_req_cmd_valid + connect \B \sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:2546$246_Y end - attribute \src "ls180.v:3837.37-3837.102" - cell $and $and$ls180.v:3837$248 + attribute \src "ls180.v:2546.93-2546.163" + cell $and $and$ls180.v:2546$248 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3837$248_Y + connect \A \sdram_choose_req_cmd_payload_ras + connect \B $not$ls180.v:2546$247_Y + connect \Y $and$ls180.v:2546$248_Y end - attribute \src "ls180.v:3837.108-3837.188" - cell $and $and$ls180.v:3837$250 + attribute \src "ls180.v:2546.92-2546.201" + cell $and $and$ls180.v:2546$250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:3837$249_Y - connect \Y $and$ls180.v:3837$250_Y + connect \A $and$ls180.v:2546$248_Y + connect \B $not$ls180.v:2546$249_Y + connect \Y $and$ls180.v:2546$250_Y end - attribute \src "ls180.v:3837.107-3837.231" - cell $and $and$ls180.v:3837$252 + attribute \src "ls180.v:2546.31-2546.202" + cell $and $and$ls180.v:2546$251 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3837$250_Y - connect \B $not$ls180.v:3837$251_Y - connect \Y $and$ls180.v:3837$252_Y + connect \A $and$ls180.v:2546$246_Y + connect \B $and$ls180.v:2546$250_Y + connect \Y $and$ls180.v:2546$251_Y end - attribute \src "ls180.v:3837.36-3837.232" - cell $and $and$ls180.v:3837$253 + attribute \src "ls180.v:2547.32-2547.87" + cell $and $and$ls180.v:2547$252 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3837$248_Y - connect \B $and$ls180.v:3837$252_Y - connect \Y $and$ls180.v:3837$253_Y + connect \A \sdram_choose_req_cmd_valid + connect \B \sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:2547$252_Y end - attribute \src "ls180.v:3838.37-3838.102" - cell $and $and$ls180.v:3838$254 + attribute \src "ls180.v:2547.93-2547.163" + cell $and $and$ls180.v:2547$254 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3838$254_Y + connect \A \sdram_choose_req_cmd_payload_ras + connect \B $not$ls180.v:2547$253_Y + connect \Y $and$ls180.v:2547$254_Y end - attribute \src "ls180.v:3838.108-3838.188" - cell $and $and$ls180.v:3838$256 + attribute \src "ls180.v:2547.92-2547.201" + cell $and $and$ls180.v:2547$256 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:3838$255_Y - connect \Y $and$ls180.v:3838$256_Y + connect \A $and$ls180.v:2547$254_Y + connect \B $not$ls180.v:2547$255_Y + connect \Y $and$ls180.v:2547$256_Y end - attribute \src "ls180.v:3838.107-3838.231" - cell $and $and$ls180.v:3838$258 + attribute \src "ls180.v:2547.31-2547.202" + cell $and $and$ls180.v:2547$257 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3838$256_Y - connect \B $not$ls180.v:3838$257_Y - connect \Y $and$ls180.v:3838$258_Y + connect \A $and$ls180.v:2547$252_Y + connect \B $and$ls180.v:2547$256_Y + connect \Y $and$ls180.v:2547$257_Y end - attribute \src "ls180.v:3838.36-3838.232" - cell $and $and$ls180.v:3838$259 + attribute \src "ls180.v:2548.29-2548.70" + cell $and $and$ls180.v:2548$258 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3838$254_Y - connect \B $and$ls180.v:3838$258_Y - connect \Y $and$ls180.v:3838$259_Y + connect \A \sdram_trrdcon_ready + connect \B \sdram_tfawcon_ready + connect \Y $and$ls180.v:2548$258_Y end - attribute \src "ls180.v:3839.34-3839.85" - cell $and $and$ls180.v:3839$260 + attribute \src "ls180.v:2549.32-2549.87" + cell $and $and$ls180.v:2549$259 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_trrdcon_ready - connect \B \main_sdram_tfawcon_ready - connect \Y $and$ls180.v:3839$260_Y + connect \A \sdram_choose_req_cmd_valid + connect \B \sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:2549$259_Y end - attribute \src "ls180.v:3840.37-3840.102" - cell $and $and$ls180.v:3840$261 + attribute \src "ls180.v:2549.31-2549.169" + cell $and $and$ls180.v:2549$261 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3840$261_Y + connect \A $and$ls180.v:2549$259_Y + connect \B $or$ls180.v:2549$260_Y + connect \Y $and$ls180.v:2549$261_Y end - attribute \src "ls180.v:3840.36-3840.194" - cell $and $and$ls180.v:3840$263 + attribute \src "ls180.v:2551.32-2551.87" + cell $and $and$ls180.v:2551$262 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3840$261_Y - connect \B $or$ls180.v:3840$262_Y - connect \Y $and$ls180.v:3840$263_Y + connect \A \sdram_choose_req_cmd_valid + connect \B \sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:2551$262_Y end - attribute \src "ls180.v:3842.37-3842.102" - cell $and $and$ls180.v:3842$264 + attribute \src "ls180.v:2551.31-2551.128" + cell $and $and$ls180.v:2551$263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3842$264_Y + connect \A $and$ls180.v:2551$262_Y + connect \B \sdram_choose_req_cmd_payload_is_write + connect \Y $and$ls180.v:2551$263_Y end - attribute \src "ls180.v:3842.36-3842.148" - cell $and $and$ls180.v:3842$265 + attribute \src "ls180.v:2552.35-2552.104" + cell $and $and$ls180.v:2552$264 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3842$264_Y - connect \B \main_sdram_choose_req_cmd_payload_is_write - connect \Y $and$ls180.v:3842$265_Y + connect \A \sdram_bankmachine0_cmd_valid + connect \B \sdram_bankmachine0_cmd_payload_is_read + connect \Y $and$ls180.v:2552$264_Y end - attribute \src "ls180.v:3843.40-3843.119" - cell $and $and$ls180.v:3843$266 + attribute \src "ls180.v:2552.109-2552.178" + cell $and $and$ls180.v:2552$265 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B \main_sdram_bankmachine0_cmd_payload_is_read - connect \Y $and$ls180.v:3843$266_Y + connect \A \sdram_bankmachine1_cmd_valid + connect \B \sdram_bankmachine1_cmd_payload_is_read + connect \Y $and$ls180.v:2552$265_Y end - attribute \src "ls180.v:3843.124-3843.203" - cell $and $and$ls180.v:3843$267 + attribute \src "ls180.v:2552.184-2552.253" + cell $and $and$ls180.v:2552$267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B \main_sdram_bankmachine1_cmd_payload_is_read - connect \Y $and$ls180.v:3843$267_Y + connect \A \sdram_bankmachine2_cmd_valid + connect \B \sdram_bankmachine2_cmd_payload_is_read + connect \Y $and$ls180.v:2552$267_Y end - attribute \src "ls180.v:3843.209-3843.288" - cell $and $and$ls180.v:3843$269 + attribute \src "ls180.v:2552.259-2552.328" + cell $and $and$ls180.v:2552$269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B \main_sdram_bankmachine2_cmd_payload_is_read - connect \Y $and$ls180.v:3843$269_Y + connect \A \sdram_bankmachine3_cmd_valid + connect \B \sdram_bankmachine3_cmd_payload_is_read + connect \Y $and$ls180.v:2552$269_Y end - attribute \src "ls180.v:3843.294-3843.373" - cell $and $and$ls180.v:3843$271 + attribute \src "ls180.v:2553.36-2553.106" + cell $and $and$ls180.v:2553$271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B \main_sdram_bankmachine3_cmd_payload_is_read - connect \Y $and$ls180.v:3843$271_Y + connect \A \sdram_bankmachine0_cmd_valid + connect \B \sdram_bankmachine0_cmd_payload_is_write + connect \Y $and$ls180.v:2553$271_Y end - attribute \src "ls180.v:3844.41-3844.121" - cell $and $and$ls180.v:3844$273 + attribute \src "ls180.v:2553.111-2553.181" + cell $and $and$ls180.v:2553$272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B \main_sdram_bankmachine0_cmd_payload_is_write - connect \Y $and$ls180.v:3844$273_Y + connect \A \sdram_bankmachine1_cmd_valid + connect \B \sdram_bankmachine1_cmd_payload_is_write + connect \Y $and$ls180.v:2553$272_Y end - attribute \src "ls180.v:3844.126-3844.206" - cell $and $and$ls180.v:3844$274 + attribute \src "ls180.v:2553.187-2553.257" + cell $and $and$ls180.v:2553$274 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B \main_sdram_bankmachine1_cmd_payload_is_write - connect \Y $and$ls180.v:3844$274_Y + connect \A \sdram_bankmachine2_cmd_valid + connect \B \sdram_bankmachine2_cmd_payload_is_write + connect \Y $and$ls180.v:2553$274_Y end - attribute \src "ls180.v:3844.212-3844.292" - cell $and $and$ls180.v:3844$276 + attribute \src "ls180.v:2553.263-2553.333" + cell $and $and$ls180.v:2553$276 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B \main_sdram_bankmachine2_cmd_payload_is_write - connect \Y $and$ls180.v:3844$276_Y + connect \A \sdram_bankmachine3_cmd_valid + connect \B \sdram_bankmachine3_cmd_payload_is_write + connect \Y $and$ls180.v:2553$276_Y end - attribute \src "ls180.v:3844.298-3844.378" - cell $and $and$ls180.v:3844$278 + attribute \src "ls180.v:2560.33-2560.96" + cell $and $and$ls180.v:2560$280 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B \main_sdram_bankmachine3_cmd_payload_is_write - connect \Y $and$ls180.v:3844$278_Y + connect \A \sdram_bankmachine0_refresh_gnt + connect \B \sdram_bankmachine1_refresh_gnt + connect \Y $and$ls180.v:2560$280_Y end - attribute \src "ls180.v:3851.38-3851.111" - cell $and $and$ls180.v:3851$282 + attribute \src "ls180.v:2560.32-2560.130" + cell $and $and$ls180.v:2560$281 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_refresh_gnt - connect \B \main_sdram_bankmachine1_refresh_gnt - connect \Y $and$ls180.v:3851$282_Y + connect \A $and$ls180.v:2560$280_Y + connect \B \sdram_bankmachine2_refresh_gnt + connect \Y $and$ls180.v:2560$281_Y end - attribute \src "ls180.v:3851.37-3851.150" - cell $and $and$ls180.v:3851$283 + attribute \src "ls180.v:2560.31-2560.164" + cell $and $and$ls180.v:2560$282 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3851$282_Y - connect \B \main_sdram_bankmachine2_refresh_gnt - connect \Y $and$ls180.v:3851$283_Y + connect \A $and$ls180.v:2560$281_Y + connect \B \sdram_bankmachine3_refresh_gnt + connect \Y $and$ls180.v:2560$282_Y end - attribute \src "ls180.v:3851.36-3851.189" - cell $and $and$ls180.v:3851$284 + attribute \src "ls180.v:2566.67-2566.133" + cell $and $and$ls180.v:2566$285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3851$283_Y - connect \B \main_sdram_bankmachine3_refresh_gnt - connect \Y $and$ls180.v:3851$284_Y + connect \A \sdram_bankmachine0_cmd_payload_is_cmd + connect \B \sdram_choose_cmd_want_cmds + connect \Y $and$ls180.v:2566$285_Y end - attribute \src "ls180.v:3857.77-3857.153" - cell $and $and$ls180.v:3857$287 + attribute \src "ls180.v:2566.142-2566.216" + cell $and $and$ls180.v:2566$287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd - connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3857$287_Y + connect \A \sdram_bankmachine0_cmd_payload_ras + connect \B $not$ls180.v:2566$286_Y + connect \Y $and$ls180.v:2566$287_Y end - attribute \src "ls180.v:3857.162-3857.246" - cell $and $and$ls180.v:3857$289 + attribute \src "ls180.v:2566.141-2566.256" + cell $and $and$ls180.v:2566$289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_ras - connect \B $not$ls180.v:3857$288_Y - connect \Y $and$ls180.v:3857$289_Y + connect \A $and$ls180.v:2566$287_Y + connect \B $not$ls180.v:2566$288_Y + connect \Y $and$ls180.v:2566$289_Y end - attribute \src "ls180.v:3857.161-3857.291" - cell $and $and$ls180.v:3857$291 + attribute \src "ls180.v:2566.66-2566.293" + cell $and $and$ls180.v:2566$292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3857$289_Y - connect \B $not$ls180.v:3857$290_Y - connect \Y $and$ls180.v:3857$291_Y + connect \A $and$ls180.v:2566$285_Y + connect \B $or$ls180.v:2566$291_Y + connect \Y $and$ls180.v:2566$292_Y end - attribute \src "ls180.v:3857.76-3857.333" - cell $and $and$ls180.v:3857$294 + attribute \src "ls180.v:2566.298-2566.445" + cell $and $and$ls180.v:2566$295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3857$287_Y - connect \B $or$ls180.v:3857$293_Y - connect \Y $and$ls180.v:3857$294_Y + connect \A $eq$ls180.v:2566$293_Y + connect \B $eq$ls180.v:2566$294_Y + connect \Y $and$ls180.v:2566$295_Y end - attribute \src "ls180.v:3857.338-3857.505" - cell $and $and$ls180.v:3857$297 + attribute \src "ls180.v:2566.33-2566.447" + cell $and $and$ls180.v:2566$297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3857$295_Y - connect \B $eq$ls180.v:3857$296_Y - connect \Y $and$ls180.v:3857$297_Y + connect \A \sdram_bankmachine0_cmd_valid + connect \B $or$ls180.v:2566$296_Y + connect \Y $and$ls180.v:2566$297_Y end - attribute \src "ls180.v:3857.38-3857.507" - cell $and $and$ls180.v:3857$299 + attribute \src "ls180.v:2567.67-2567.133" + cell $and $and$ls180.v:2567$298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B $or$ls180.v:3857$298_Y - connect \Y $and$ls180.v:3857$299_Y + connect \A \sdram_bankmachine1_cmd_payload_is_cmd + connect \B \sdram_choose_cmd_want_cmds + connect \Y $and$ls180.v:2567$298_Y end - attribute \src "ls180.v:3858.77-3858.153" - cell $and $and$ls180.v:3858$300 + attribute \src "ls180.v:2567.142-2567.216" + cell $and $and$ls180.v:2567$300 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd - connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3858$300_Y + connect \A \sdram_bankmachine1_cmd_payload_ras + connect \B $not$ls180.v:2567$299_Y + connect \Y $and$ls180.v:2567$300_Y end - attribute \src "ls180.v:3858.162-3858.246" - cell $and $and$ls180.v:3858$302 + attribute \src "ls180.v:2567.141-2567.256" + cell $and $and$ls180.v:2567$302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_ras - connect \B $not$ls180.v:3858$301_Y - connect \Y $and$ls180.v:3858$302_Y + connect \A $and$ls180.v:2567$300_Y + connect \B $not$ls180.v:2567$301_Y + connect \Y $and$ls180.v:2567$302_Y end - attribute \src "ls180.v:3858.161-3858.291" - cell $and $and$ls180.v:3858$304 + attribute \src "ls180.v:2567.66-2567.293" + cell $and $and$ls180.v:2567$305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3858$302_Y - connect \B $not$ls180.v:3858$303_Y - connect \Y $and$ls180.v:3858$304_Y + connect \A $and$ls180.v:2567$298_Y + connect \B $or$ls180.v:2567$304_Y + connect \Y $and$ls180.v:2567$305_Y end - attribute \src "ls180.v:3858.76-3858.333" - cell $and $and$ls180.v:3858$307 + attribute \src "ls180.v:2567.298-2567.445" + cell $and $and$ls180.v:2567$308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3858$300_Y - connect \B $or$ls180.v:3858$306_Y - connect \Y $and$ls180.v:3858$307_Y + connect \A $eq$ls180.v:2567$306_Y + connect \B $eq$ls180.v:2567$307_Y + connect \Y $and$ls180.v:2567$308_Y end - attribute \src "ls180.v:3858.338-3858.505" - cell $and $and$ls180.v:3858$310 + attribute \src "ls180.v:2567.33-2567.447" + cell $and $and$ls180.v:2567$310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3858$308_Y - connect \B $eq$ls180.v:3858$309_Y - connect \Y $and$ls180.v:3858$310_Y + connect \A \sdram_bankmachine1_cmd_valid + connect \B $or$ls180.v:2567$309_Y + connect \Y $and$ls180.v:2567$310_Y end - attribute \src "ls180.v:3858.38-3858.507" - cell $and $and$ls180.v:3858$312 + attribute \src "ls180.v:2568.67-2568.133" + cell $and $and$ls180.v:2568$311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B $or$ls180.v:3858$311_Y - connect \Y $and$ls180.v:3858$312_Y + connect \A \sdram_bankmachine2_cmd_payload_is_cmd + connect \B \sdram_choose_cmd_want_cmds + connect \Y $and$ls180.v:2568$311_Y end - attribute \src "ls180.v:3859.77-3859.153" - cell $and $and$ls180.v:3859$313 + attribute \src "ls180.v:2568.142-2568.216" + cell $and $and$ls180.v:2568$313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd - connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3859$313_Y + connect \A \sdram_bankmachine2_cmd_payload_ras + connect \B $not$ls180.v:2568$312_Y + connect \Y $and$ls180.v:2568$313_Y end - attribute \src "ls180.v:3859.162-3859.246" - cell $and $and$ls180.v:3859$315 + attribute \src "ls180.v:2568.141-2568.256" + cell $and $and$ls180.v:2568$315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_ras - connect \B $not$ls180.v:3859$314_Y - connect \Y $and$ls180.v:3859$315_Y + connect \A $and$ls180.v:2568$313_Y + connect \B $not$ls180.v:2568$314_Y + connect \Y $and$ls180.v:2568$315_Y end - attribute \src "ls180.v:3859.161-3859.291" - cell $and $and$ls180.v:3859$317 + attribute \src "ls180.v:2568.66-2568.293" + cell $and $and$ls180.v:2568$318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3859$315_Y - connect \B $not$ls180.v:3859$316_Y - connect \Y $and$ls180.v:3859$317_Y + connect \A $and$ls180.v:2568$311_Y + connect \B $or$ls180.v:2568$317_Y + connect \Y $and$ls180.v:2568$318_Y end - attribute \src "ls180.v:3859.76-3859.333" - cell $and $and$ls180.v:3859$320 + attribute \src "ls180.v:2568.298-2568.445" + cell $and $and$ls180.v:2568$321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3859$313_Y - connect \B $or$ls180.v:3859$319_Y - connect \Y $and$ls180.v:3859$320_Y + connect \A $eq$ls180.v:2568$319_Y + connect \B $eq$ls180.v:2568$320_Y + connect \Y $and$ls180.v:2568$321_Y end - attribute \src "ls180.v:3859.338-3859.505" - cell $and $and$ls180.v:3859$323 + attribute \src "ls180.v:2568.33-2568.447" + cell $and $and$ls180.v:2568$323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3859$321_Y - connect \B $eq$ls180.v:3859$322_Y - connect \Y $and$ls180.v:3859$323_Y + connect \A \sdram_bankmachine2_cmd_valid + connect \B $or$ls180.v:2568$322_Y + connect \Y $and$ls180.v:2568$323_Y end - attribute \src "ls180.v:3859.38-3859.507" - cell $and $and$ls180.v:3859$325 + attribute \src "ls180.v:2569.67-2569.133" + cell $and $and$ls180.v:2569$324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B $or$ls180.v:3859$324_Y - connect \Y $and$ls180.v:3859$325_Y + connect \A \sdram_bankmachine3_cmd_payload_is_cmd + connect \B \sdram_choose_cmd_want_cmds + connect \Y $and$ls180.v:2569$324_Y end - attribute \src "ls180.v:3860.77-3860.153" - cell $and $and$ls180.v:3860$326 + attribute \src "ls180.v:2569.142-2569.216" + cell $and $and$ls180.v:2569$326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd - connect \B \main_sdram_choose_cmd_want_cmds - connect \Y $and$ls180.v:3860$326_Y + connect \A \sdram_bankmachine3_cmd_payload_ras + connect \B $not$ls180.v:2569$325_Y + connect \Y $and$ls180.v:2569$326_Y end - attribute \src "ls180.v:3860.162-3860.246" - cell $and $and$ls180.v:3860$328 + attribute \src "ls180.v:2569.141-2569.256" + cell $and $and$ls180.v:2569$328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_ras - connect \B $not$ls180.v:3860$327_Y - connect \Y $and$ls180.v:3860$328_Y + connect \A $and$ls180.v:2569$326_Y + connect \B $not$ls180.v:2569$327_Y + connect \Y $and$ls180.v:2569$328_Y end - attribute \src "ls180.v:3860.161-3860.291" - cell $and $and$ls180.v:3860$330 + attribute \src "ls180.v:2569.66-2569.293" + cell $and $and$ls180.v:2569$331 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3860$328_Y - connect \B $not$ls180.v:3860$329_Y - connect \Y $and$ls180.v:3860$330_Y + connect \A $and$ls180.v:2569$324_Y + connect \B $or$ls180.v:2569$330_Y + connect \Y $and$ls180.v:2569$331_Y end - attribute \src "ls180.v:3860.76-3860.333" - cell $and $and$ls180.v:3860$333 + attribute \src "ls180.v:2569.298-2569.445" + cell $and $and$ls180.v:2569$334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3860$326_Y - connect \B $or$ls180.v:3860$332_Y - connect \Y $and$ls180.v:3860$333_Y + connect \A $eq$ls180.v:2569$332_Y + connect \B $eq$ls180.v:2569$333_Y + connect \Y $and$ls180.v:2569$334_Y end - attribute \src "ls180.v:3860.338-3860.505" - cell $and $and$ls180.v:3860$336 + attribute \src "ls180.v:2569.33-2569.447" + cell $and $and$ls180.v:2569$336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3860$334_Y - connect \B $eq$ls180.v:3860$335_Y - connect \Y $and$ls180.v:3860$336_Y + connect \A \sdram_bankmachine3_cmd_valid + connect \B $or$ls180.v:2569$335_Y + connect \Y $and$ls180.v:2569$336_Y end - attribute \src "ls180.v:3860.38-3860.507" - cell $and $and$ls180.v:3860$338 + attribute \src "ls180.v:2599.67-2599.133" + cell $and $and$ls180.v:2599$343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B $or$ls180.v:3860$337_Y - connect \Y $and$ls180.v:3860$338_Y + connect \A \sdram_bankmachine0_cmd_payload_is_cmd + connect \B \sdram_choose_req_want_cmds + connect \Y $and$ls180.v:2599$343_Y end - attribute \src "ls180.v:3890.77-3890.153" - cell $and $and$ls180.v:3890$345 + attribute \src "ls180.v:2599.142-2599.216" + cell $and $and$ls180.v:2599$345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd - connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:3890$345_Y + connect \A \sdram_bankmachine0_cmd_payload_ras + connect \B $not$ls180.v:2599$344_Y + connect \Y $and$ls180.v:2599$345_Y end - attribute \src "ls180.v:3890.162-3890.246" - cell $and $and$ls180.v:3890$347 + attribute \src "ls180.v:2599.141-2599.256" + cell $and $and$ls180.v:2599$347 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_ras - connect \B $not$ls180.v:3890$346_Y - connect \Y $and$ls180.v:3890$347_Y + connect \A $and$ls180.v:2599$345_Y + connect \B $not$ls180.v:2599$346_Y + connect \Y $and$ls180.v:2599$347_Y end - attribute \src "ls180.v:3890.161-3890.291" - cell $and $and$ls180.v:3890$349 + attribute \src "ls180.v:2599.66-2599.293" + cell $and $and$ls180.v:2599$350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3890$347_Y - connect \B $not$ls180.v:3890$348_Y - connect \Y $and$ls180.v:3890$349_Y + connect \A $and$ls180.v:2599$343_Y + connect \B $or$ls180.v:2599$349_Y + connect \Y $and$ls180.v:2599$350_Y end - attribute \src "ls180.v:3890.76-3890.333" - cell $and $and$ls180.v:3890$352 + attribute \src "ls180.v:2599.298-2599.445" + cell $and $and$ls180.v:2599$353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3890$345_Y - connect \B $or$ls180.v:3890$351_Y - connect \Y $and$ls180.v:3890$352_Y + connect \A $eq$ls180.v:2599$351_Y + connect \B $eq$ls180.v:2599$352_Y + connect \Y $and$ls180.v:2599$353_Y end - attribute \src "ls180.v:3890.338-3890.505" - cell $and $and$ls180.v:3890$355 + attribute \src "ls180.v:2599.33-2599.447" + cell $and $and$ls180.v:2599$355 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3890$353_Y - connect \B $eq$ls180.v:3890$354_Y - connect \Y $and$ls180.v:3890$355_Y + connect \A \sdram_bankmachine0_cmd_valid + connect \B $or$ls180.v:2599$354_Y + connect \Y $and$ls180.v:2599$355_Y end - attribute \src "ls180.v:3890.38-3890.507" - cell $and $and$ls180.v:3890$357 + attribute \src "ls180.v:2600.67-2600.133" + cell $and $and$ls180.v:2600$356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_valid - connect \B $or$ls180.v:3890$356_Y - connect \Y $and$ls180.v:3890$357_Y + connect \A \sdram_bankmachine1_cmd_payload_is_cmd + connect \B \sdram_choose_req_want_cmds + connect \Y $and$ls180.v:2600$356_Y end - attribute \src "ls180.v:3891.77-3891.153" - cell $and $and$ls180.v:3891$358 + attribute \src "ls180.v:2600.142-2600.216" + cell $and $and$ls180.v:2600$358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd - connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:3891$358_Y + connect \A \sdram_bankmachine1_cmd_payload_ras + connect \B $not$ls180.v:2600$357_Y + connect \Y $and$ls180.v:2600$358_Y end - attribute \src "ls180.v:3891.162-3891.246" - cell $and $and$ls180.v:3891$360 + attribute \src "ls180.v:2600.141-2600.256" + cell $and $and$ls180.v:2600$360 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_ras - connect \B $not$ls180.v:3891$359_Y - connect \Y $and$ls180.v:3891$360_Y + connect \A $and$ls180.v:2600$358_Y + connect \B $not$ls180.v:2600$359_Y + connect \Y $and$ls180.v:2600$360_Y end - attribute \src "ls180.v:3891.161-3891.291" - cell $and $and$ls180.v:3891$362 + attribute \src "ls180.v:2600.66-2600.293" + cell $and $and$ls180.v:2600$363 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3891$360_Y - connect \B $not$ls180.v:3891$361_Y - connect \Y $and$ls180.v:3891$362_Y + connect \A $and$ls180.v:2600$356_Y + connect \B $or$ls180.v:2600$362_Y + connect \Y $and$ls180.v:2600$363_Y end - attribute \src "ls180.v:3891.76-3891.333" - cell $and $and$ls180.v:3891$365 + attribute \src "ls180.v:2600.298-2600.445" + cell $and $and$ls180.v:2600$366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3891$358_Y - connect \B $or$ls180.v:3891$364_Y - connect \Y $and$ls180.v:3891$365_Y + connect \A $eq$ls180.v:2600$364_Y + connect \B $eq$ls180.v:2600$365_Y + connect \Y $and$ls180.v:2600$366_Y end - attribute \src "ls180.v:3891.338-3891.505" - cell $and $and$ls180.v:3891$368 + attribute \src "ls180.v:2600.33-2600.447" + cell $and $and$ls180.v:2600$368 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3891$366_Y - connect \B $eq$ls180.v:3891$367_Y - connect \Y $and$ls180.v:3891$368_Y + connect \A \sdram_bankmachine1_cmd_valid + connect \B $or$ls180.v:2600$367_Y + connect \Y $and$ls180.v:2600$368_Y end - attribute \src "ls180.v:3891.38-3891.507" - cell $and $and$ls180.v:3891$370 + attribute \src "ls180.v:2601.67-2601.133" + cell $and $and$ls180.v:2601$369 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_valid - connect \B $or$ls180.v:3891$369_Y - connect \Y $and$ls180.v:3891$370_Y + connect \A \sdram_bankmachine2_cmd_payload_is_cmd + connect \B \sdram_choose_req_want_cmds + connect \Y $and$ls180.v:2601$369_Y end - attribute \src "ls180.v:3892.77-3892.153" - cell $and $and$ls180.v:3892$371 + attribute \src "ls180.v:2601.142-2601.216" + cell $and $and$ls180.v:2601$371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd - connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:3892$371_Y + connect \A \sdram_bankmachine2_cmd_payload_ras + connect \B $not$ls180.v:2601$370_Y + connect \Y $and$ls180.v:2601$371_Y end - attribute \src "ls180.v:3892.162-3892.246" - cell $and $and$ls180.v:3892$373 + attribute \src "ls180.v:2601.141-2601.256" + cell $and $and$ls180.v:2601$373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_ras - connect \B $not$ls180.v:3892$372_Y - connect \Y $and$ls180.v:3892$373_Y + connect \A $and$ls180.v:2601$371_Y + connect \B $not$ls180.v:2601$372_Y + connect \Y $and$ls180.v:2601$373_Y end - attribute \src "ls180.v:3892.161-3892.291" - cell $and $and$ls180.v:3892$375 + attribute \src "ls180.v:2601.66-2601.293" + cell $and $and$ls180.v:2601$376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3892$373_Y - connect \B $not$ls180.v:3892$374_Y - connect \Y $and$ls180.v:3892$375_Y + connect \A $and$ls180.v:2601$369_Y + connect \B $or$ls180.v:2601$375_Y + connect \Y $and$ls180.v:2601$376_Y end - attribute \src "ls180.v:3892.76-3892.333" - cell $and $and$ls180.v:3892$378 + attribute \src "ls180.v:2601.298-2601.445" + cell $and $and$ls180.v:2601$379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3892$371_Y - connect \B $or$ls180.v:3892$377_Y - connect \Y $and$ls180.v:3892$378_Y + connect \A $eq$ls180.v:2601$377_Y + connect \B $eq$ls180.v:2601$378_Y + connect \Y $and$ls180.v:2601$379_Y end - attribute \src "ls180.v:3892.338-3892.505" - cell $and $and$ls180.v:3892$381 + attribute \src "ls180.v:2601.33-2601.447" + cell $and $and$ls180.v:2601$381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3892$379_Y - connect \B $eq$ls180.v:3892$380_Y - connect \Y $and$ls180.v:3892$381_Y + connect \A \sdram_bankmachine2_cmd_valid + connect \B $or$ls180.v:2601$380_Y + connect \Y $and$ls180.v:2601$381_Y end - attribute \src "ls180.v:3892.38-3892.507" - cell $and $and$ls180.v:3892$383 + attribute \src "ls180.v:2602.67-2602.133" + cell $and $and$ls180.v:2602$382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_valid - connect \B $or$ls180.v:3892$382_Y - connect \Y $and$ls180.v:3892$383_Y + connect \A \sdram_bankmachine3_cmd_payload_is_cmd + connect \B \sdram_choose_req_want_cmds + connect \Y $and$ls180.v:2602$382_Y end - attribute \src "ls180.v:3893.77-3893.153" - cell $and $and$ls180.v:3893$384 + attribute \src "ls180.v:2602.142-2602.216" + cell $and $and$ls180.v:2602$384 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd - connect \B \main_sdram_choose_req_want_cmds - connect \Y $and$ls180.v:3893$384_Y + connect \A \sdram_bankmachine3_cmd_payload_ras + connect \B $not$ls180.v:2602$383_Y + connect \Y $and$ls180.v:2602$384_Y end - attribute \src "ls180.v:3893.162-3893.246" - cell $and $and$ls180.v:3893$386 + attribute \src "ls180.v:2602.141-2602.256" + cell $and $and$ls180.v:2602$386 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_ras - connect \B $not$ls180.v:3893$385_Y - connect \Y $and$ls180.v:3893$386_Y + connect \A $and$ls180.v:2602$384_Y + connect \B $not$ls180.v:2602$385_Y + connect \Y $and$ls180.v:2602$386_Y end - attribute \src "ls180.v:3893.161-3893.291" - cell $and $and$ls180.v:3893$388 + attribute \src "ls180.v:2602.66-2602.293" + cell $and $and$ls180.v:2602$389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3893$386_Y - connect \B $not$ls180.v:3893$387_Y - connect \Y $and$ls180.v:3893$388_Y + connect \A $and$ls180.v:2602$382_Y + connect \B $or$ls180.v:2602$388_Y + connect \Y $and$ls180.v:2602$389_Y end - attribute \src "ls180.v:3893.76-3893.333" - cell $and $and$ls180.v:3893$391 + attribute \src "ls180.v:2602.298-2602.445" + cell $and $and$ls180.v:2602$392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3893$384_Y - connect \B $or$ls180.v:3893$390_Y - connect \Y $and$ls180.v:3893$391_Y + connect \A $eq$ls180.v:2602$390_Y + connect \B $eq$ls180.v:2602$391_Y + connect \Y $and$ls180.v:2602$392_Y end - attribute \src "ls180.v:3893.338-3893.505" - cell $and $and$ls180.v:3893$394 + attribute \src "ls180.v:2602.33-2602.447" + cell $and $and$ls180.v:2602$394 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:3893$392_Y - connect \B $eq$ls180.v:3893$393_Y - connect \Y $and$ls180.v:3893$394_Y + connect \A \sdram_bankmachine3_cmd_valid + connect \B $or$ls180.v:2602$393_Y + connect \Y $and$ls180.v:2602$394_Y end - attribute \src "ls180.v:3893.38-3893.507" - cell $and $and$ls180.v:3893$396 + attribute \src "ls180.v:2631.8-2631.63" + cell $and $and$ls180.v:2631$399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_valid - connect \B $or$ls180.v:3893$395_Y - connect \Y $and$ls180.v:3893$396_Y + connect \A \sdram_choose_cmd_cmd_valid + connect \B \sdram_choose_cmd_cmd_ready + connect \Y $and$ls180.v:2631$399_Y end - attribute \src "ls180.v:3922.8-3922.73" - cell $and $and$ls180.v:3922$401 + attribute \src "ls180.v:2631.7-2631.99" + cell $and $and$ls180.v:2631$401 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_cmd_valid - connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:3922$401_Y + connect \A $and$ls180.v:2631$399_Y + connect \B $eq$ls180.v:2631$400_Y + connect \Y $and$ls180.v:2631$401_Y end - attribute \src "ls180.v:3922.7-3922.114" - cell $and $and$ls180.v:3922$403 + attribute \src "ls180.v:2634.8-2634.63" + cell $and $and$ls180.v:2634$402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3922$401_Y - connect \B $eq$ls180.v:3922$402_Y - connect \Y $and$ls180.v:3922$403_Y + connect \A \sdram_choose_req_cmd_valid + connect \B \sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:2634$402_Y end - attribute \src "ls180.v:3925.8-3925.73" - cell $and $and$ls180.v:3925$404 + attribute \src "ls180.v:2634.7-2634.99" + cell $and $and$ls180.v:2634$404 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3925$404_Y + connect \A $and$ls180.v:2634$402_Y + connect \B $eq$ls180.v:2634$403_Y + connect \Y $and$ls180.v:2634$404_Y end - attribute \src "ls180.v:3925.7-3925.114" - cell $and $and$ls180.v:3925$406 + attribute \src "ls180.v:2640.8-2640.63" + cell $and $and$ls180.v:2640$406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3925$404_Y - connect \B $eq$ls180.v:3925$405_Y - connect \Y $and$ls180.v:3925$406_Y + connect \A \sdram_choose_cmd_cmd_valid + connect \B \sdram_choose_cmd_cmd_ready + connect \Y $and$ls180.v:2640$406_Y end - attribute \src "ls180.v:3931.8-3931.73" - cell $and $and$ls180.v:3931$408 + attribute \src "ls180.v:2640.7-2640.99" + cell $and $and$ls180.v:2640$408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_cmd_valid - connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:3931$408_Y + connect \A $and$ls180.v:2640$406_Y + connect \B $eq$ls180.v:2640$407_Y + connect \Y $and$ls180.v:2640$408_Y end - attribute \src "ls180.v:3931.7-3931.114" - cell $and $and$ls180.v:3931$410 + attribute \src "ls180.v:2643.8-2643.63" + cell $and $and$ls180.v:2643$409 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3931$408_Y - connect \B $eq$ls180.v:3931$409_Y - connect \Y $and$ls180.v:3931$410_Y + connect \A \sdram_choose_req_cmd_valid + connect \B \sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:2643$409_Y end - attribute \src "ls180.v:3934.8-3934.73" - cell $and $and$ls180.v:3934$411 + attribute \src "ls180.v:2643.7-2643.99" + cell $and $and$ls180.v:2643$411 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3934$411_Y + connect \A $and$ls180.v:2643$409_Y + connect \B $eq$ls180.v:2643$410_Y + connect \Y $and$ls180.v:2643$411_Y end - attribute \src "ls180.v:3934.7-3934.114" - cell $and $and$ls180.v:3934$413 + attribute \src "ls180.v:2649.8-2649.63" + cell $and $and$ls180.v:2649$413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3934$411_Y - connect \B $eq$ls180.v:3934$412_Y - connect \Y $and$ls180.v:3934$413_Y + connect \A \sdram_choose_cmd_cmd_valid + connect \B \sdram_choose_cmd_cmd_ready + connect \Y $and$ls180.v:2649$413_Y end - attribute \src "ls180.v:3940.8-3940.73" - cell $and $and$ls180.v:3940$415 + attribute \src "ls180.v:2649.7-2649.99" + cell $and $and$ls180.v:2649$415 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_cmd_valid - connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:3940$415_Y + connect \A $and$ls180.v:2649$413_Y + connect \B $eq$ls180.v:2649$414_Y + connect \Y $and$ls180.v:2649$415_Y end - attribute \src "ls180.v:3940.7-3940.114" - cell $and $and$ls180.v:3940$417 + attribute \src "ls180.v:2652.8-2652.63" + cell $and $and$ls180.v:2652$416 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3940$415_Y - connect \B $eq$ls180.v:3940$416_Y - connect \Y $and$ls180.v:3940$417_Y + connect \A \sdram_choose_req_cmd_valid + connect \B \sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:2652$416_Y end - attribute \src "ls180.v:3943.8-3943.73" - cell $and $and$ls180.v:3943$418 + attribute \src "ls180.v:2652.7-2652.99" + cell $and $and$ls180.v:2652$418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3943$418_Y + connect \A $and$ls180.v:2652$416_Y + connect \B $eq$ls180.v:2652$417_Y + connect \Y $and$ls180.v:2652$418_Y end - attribute \src "ls180.v:3943.7-3943.114" - cell $and $and$ls180.v:3943$420 + attribute \src "ls180.v:2658.8-2658.63" + cell $and $and$ls180.v:2658$420 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3943$418_Y - connect \B $eq$ls180.v:3943$419_Y - connect \Y $and$ls180.v:3943$420_Y + connect \A \sdram_choose_cmd_cmd_valid + connect \B \sdram_choose_cmd_cmd_ready + connect \Y $and$ls180.v:2658$420_Y end - attribute \src "ls180.v:3949.8-3949.73" - cell $and $and$ls180.v:3949$422 + attribute \src "ls180.v:2658.7-2658.99" + cell $and $and$ls180.v:2658$422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_cmd_valid - connect \B \main_sdram_choose_cmd_cmd_ready - connect \Y $and$ls180.v:3949$422_Y + connect \A $and$ls180.v:2658$420_Y + connect \B $eq$ls180.v:2658$421_Y + connect \Y $and$ls180.v:2658$422_Y end - attribute \src "ls180.v:3949.7-3949.114" - cell $and $and$ls180.v:3949$424 + attribute \src "ls180.v:2661.8-2661.63" + cell $and $and$ls180.v:2661$423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3949$422_Y - connect \B $eq$ls180.v:3949$423_Y - connect \Y $and$ls180.v:3949$424_Y + connect \A \sdram_choose_req_cmd_valid + connect \B \sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:2661$423_Y end - attribute \src "ls180.v:3952.8-3952.73" - cell $and $and$ls180.v:3952$425 + attribute \src "ls180.v:2661.7-2661.99" + cell $and $and$ls180.v:2661$425 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:3952$425_Y + connect \A $and$ls180.v:2661$423_Y + connect \B $eq$ls180.v:2661$424_Y + connect \Y $and$ls180.v:2661$425_Y end - attribute \src "ls180.v:3952.7-3952.114" - cell $and $and$ls180.v:3952$427 + attribute \src "ls180.v:2686.61-2686.131" + cell $and $and$ls180.v:2686$430 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3952$425_Y - connect \B $eq$ls180.v:3952$426_Y - connect \Y $and$ls180.v:3952$427_Y + connect \A \sdram_choose_req_cmd_payload_ras + connect \B $not$ls180.v:2686$429_Y + connect \Y $and$ls180.v:2686$430_Y end - attribute \src "ls180.v:3977.71-3977.151" - cell $and $and$ls180.v:3977$432 + attribute \src "ls180.v:2686.60-2686.169" + cell $and $and$ls180.v:2686$432 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:3977$431_Y - connect \Y $and$ls180.v:3977$432_Y + connect \A $and$ls180.v:2686$430_Y + connect \B $not$ls180.v:2686$431_Y + connect \Y $and$ls180.v:2686$432_Y end - attribute \src "ls180.v:3977.70-3977.194" - cell $and $and$ls180.v:3977$434 + attribute \src "ls180.v:2686.36-2686.192" + cell $and $and$ls180.v:2686$435 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3977$432_Y - connect \B $not$ls180.v:3977$433_Y - connect \Y $and$ls180.v:3977$434_Y + connect \A \sdram_cas_allowed + connect \B $or$ls180.v:2686$434_Y + connect \Y $and$ls180.v:2686$435_Y end - attribute \src "ls180.v:3977.41-3977.222" - cell $and $and$ls180.v:3977$437 + attribute \src "ls180.v:2724.61-2724.131" + cell $and $and$ls180.v:2724$439 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_cas_allowed - connect \B $or$ls180.v:3977$436_Y - connect \Y $and$ls180.v:3977$437_Y + connect \A \sdram_choose_req_cmd_payload_ras + connect \B $not$ls180.v:2724$438_Y + connect \Y $and$ls180.v:2724$439_Y end - attribute \src "ls180.v:4015.71-4015.151" - cell $and $and$ls180.v:4015$441 + attribute \src "ls180.v:2724.60-2724.169" + cell $and $and$ls180.v:2724$441 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_ras - connect \B $not$ls180.v:4015$440_Y - connect \Y $and$ls180.v:4015$441_Y + connect \A $and$ls180.v:2724$439_Y + connect \B $not$ls180.v:2724$440_Y + connect \Y $and$ls180.v:2724$441_Y end - attribute \src "ls180.v:4015.70-4015.194" - cell $and $and$ls180.v:4015$443 + attribute \src "ls180.v:2724.36-2724.192" + cell $and $and$ls180.v:2724$444 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4015$441_Y - connect \B $not$ls180.v:4015$442_Y - connect \Y $and$ls180.v:4015$443_Y + connect \A \sdram_cas_allowed + connect \B $or$ls180.v:2724$443_Y + connect \Y $and$ls180.v:2724$444_Y end - attribute \src "ls180.v:4015.41-4015.222" - cell $and $and$ls180.v:4015$446 + attribute \src "ls180.v:2742.115-2742.184" + cell $and $and$ls180.v:2742$449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_cas_allowed - connect \B $or$ls180.v:4015$445_Y - connect \Y $and$ls180.v:4015$446_Y + connect \A \sdram_interface_bank1_lock + connect \B $eq$ls180.v:2742$448_Y + connect \Y $and$ls180.v:2742$449_Y end - attribute \src "ls180.v:4033.110-4033.179" - cell $and $and$ls180.v:4033$451 + attribute \src "ls180.v:2742.190-2742.259" + cell $and $and$ls180.v:2742$452 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4033$450_Y - connect \Y $and$ls180.v:4033$451_Y + connect \A \sdram_interface_bank2_lock + connect \B $eq$ls180.v:2742$451_Y + connect \Y $and$ls180.v:2742$452_Y end - attribute \src "ls180.v:4033.185-4033.254" - cell $and $and$ls180.v:4033$454 + attribute \src "ls180.v:2742.265-2742.334" + cell $and $and$ls180.v:2742$455 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4033$453_Y - connect \Y $and$ls180.v:4033$454_Y + connect \A \sdram_interface_bank3_lock + connect \B $eq$ls180.v:2742$454_Y + connect \Y $and$ls180.v:2742$455_Y end - attribute \src "ls180.v:4033.260-4033.329" - cell $and $and$ls180.v:4033$457 + attribute \src "ls180.v:2742.46-2742.337" + cell $and $and$ls180.v:2742$458 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4033$456_Y - connect \Y $and$ls180.v:4033$457_Y + connect \A $eq$ls180.v:2742$447_Y + connect \B $not$ls180.v:2742$457_Y + connect \Y $and$ls180.v:2742$458_Y end - attribute \src "ls180.v:4033.41-4033.332" - cell $and $and$ls180.v:4033$460 + attribute \src "ls180.v:2742.45-2742.355" + cell $and $and$ls180.v:2742$459 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4033$449_Y - connect \B $not$ls180.v:4033$459_Y - connect \Y $and$ls180.v:4033$460_Y + connect \A $and$ls180.v:2742$458_Y + connect \B \port_cmd_valid + connect \Y $and$ls180.v:2742$459_Y end - attribute \src "ls180.v:4033.40-4033.355" - cell $and $and$ls180.v:4033$461 + attribute \src "ls180.v:2743.39-2743.101" + cell $and $and$ls180.v:2743$462 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4033$460_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:4033$461_Y + connect \A $not$ls180.v:2743$460_Y + connect \B $not$ls180.v:2743$461_Y + connect \Y $and$ls180.v:2743$462_Y end - attribute \src "ls180.v:4034.34-4034.106" - cell $and $and$ls180.v:4034$464 + attribute \src "ls180.v:2747.115-2747.184" + cell $and $and$ls180.v:2747$465 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4034$462_Y - connect \B $not$ls180.v:4034$463_Y - connect \Y $and$ls180.v:4034$464_Y + connect \A \sdram_interface_bank0_lock + connect \B $eq$ls180.v:2747$464_Y + connect \Y $and$ls180.v:2747$465_Y end - attribute \src "ls180.v:4038.110-4038.179" - cell $and $and$ls180.v:4038$467 + attribute \src "ls180.v:2747.190-2747.259" + cell $and $and$ls180.v:2747$468 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4038$466_Y - connect \Y $and$ls180.v:4038$467_Y + connect \A \sdram_interface_bank2_lock + connect \B $eq$ls180.v:2747$467_Y + connect \Y $and$ls180.v:2747$468_Y end - attribute \src "ls180.v:4038.185-4038.254" - cell $and $and$ls180.v:4038$470 + attribute \src "ls180.v:2747.265-2747.334" + cell $and $and$ls180.v:2747$471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4038$469_Y - connect \Y $and$ls180.v:4038$470_Y + connect \A \sdram_interface_bank3_lock + connect \B $eq$ls180.v:2747$470_Y + connect \Y $and$ls180.v:2747$471_Y end - attribute \src "ls180.v:4038.260-4038.329" - cell $and $and$ls180.v:4038$473 + attribute \src "ls180.v:2747.46-2747.337" + cell $and $and$ls180.v:2747$474 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4038$472_Y - connect \Y $and$ls180.v:4038$473_Y + connect \A $eq$ls180.v:2747$463_Y + connect \B $not$ls180.v:2747$473_Y + connect \Y $and$ls180.v:2747$474_Y end - attribute \src "ls180.v:4038.41-4038.332" - cell $and $and$ls180.v:4038$476 + attribute \src "ls180.v:2747.45-2747.355" + cell $and $and$ls180.v:2747$475 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4038$465_Y - connect \B $not$ls180.v:4038$475_Y - connect \Y $and$ls180.v:4038$476_Y + connect \A $and$ls180.v:2747$474_Y + connect \B \port_cmd_valid + connect \Y $and$ls180.v:2747$475_Y end - attribute \src "ls180.v:4038.40-4038.355" - cell $and $and$ls180.v:4038$477 + attribute \src "ls180.v:2748.39-2748.101" + cell $and $and$ls180.v:2748$478 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4038$476_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:4038$477_Y + connect \A $not$ls180.v:2748$476_Y + connect \B $not$ls180.v:2748$477_Y + connect \Y $and$ls180.v:2748$478_Y end - attribute \src "ls180.v:4039.34-4039.106" - cell $and $and$ls180.v:4039$480 + attribute \src "ls180.v:2752.115-2752.184" + cell $and $and$ls180.v:2752$481 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4039$478_Y - connect \B $not$ls180.v:4039$479_Y - connect \Y $and$ls180.v:4039$480_Y + connect \A \sdram_interface_bank0_lock + connect \B $eq$ls180.v:2752$480_Y + connect \Y $and$ls180.v:2752$481_Y end - attribute \src "ls180.v:4043.110-4043.179" - cell $and $and$ls180.v:4043$483 + attribute \src "ls180.v:2752.190-2752.259" + cell $and $and$ls180.v:2752$484 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4043$482_Y - connect \Y $and$ls180.v:4043$483_Y + connect \A \sdram_interface_bank1_lock + connect \B $eq$ls180.v:2752$483_Y + connect \Y $and$ls180.v:2752$484_Y end - attribute \src "ls180.v:4043.185-4043.254" - cell $and $and$ls180.v:4043$486 + attribute \src "ls180.v:2752.265-2752.334" + cell $and $and$ls180.v:2752$487 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4043$485_Y - connect \Y $and$ls180.v:4043$486_Y + connect \A \sdram_interface_bank3_lock + connect \B $eq$ls180.v:2752$486_Y + connect \Y $and$ls180.v:2752$487_Y end - attribute \src "ls180.v:4043.260-4043.329" - cell $and $and$ls180.v:4043$489 + attribute \src "ls180.v:2752.46-2752.337" + cell $and $and$ls180.v:2752$490 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4043$488_Y - connect \Y $and$ls180.v:4043$489_Y + connect \A $eq$ls180.v:2752$479_Y + connect \B $not$ls180.v:2752$489_Y + connect \Y $and$ls180.v:2752$490_Y end - attribute \src "ls180.v:4043.41-4043.332" - cell $and $and$ls180.v:4043$492 + attribute \src "ls180.v:2752.45-2752.355" + cell $and $and$ls180.v:2752$491 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4043$481_Y - connect \B $not$ls180.v:4043$491_Y - connect \Y $and$ls180.v:4043$492_Y + connect \A $and$ls180.v:2752$490_Y + connect \B \port_cmd_valid + connect \Y $and$ls180.v:2752$491_Y end - attribute \src "ls180.v:4043.40-4043.355" - cell $and $and$ls180.v:4043$493 + attribute \src "ls180.v:2753.39-2753.101" + cell $and $and$ls180.v:2753$494 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4043$492_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:4043$493_Y + connect \A $not$ls180.v:2753$492_Y + connect \B $not$ls180.v:2753$493_Y + connect \Y $and$ls180.v:2753$494_Y end - attribute \src "ls180.v:4044.34-4044.106" - cell $and $and$ls180.v:4044$496 + attribute \src "ls180.v:2757.115-2757.184" + cell $and $and$ls180.v:2757$497 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4044$494_Y - connect \B $not$ls180.v:4044$495_Y - connect \Y $and$ls180.v:4044$496_Y + connect \A \sdram_interface_bank0_lock + connect \B $eq$ls180.v:2757$496_Y + connect \Y $and$ls180.v:2757$497_Y end - attribute \src "ls180.v:4048.110-4048.179" - cell $and $and$ls180.v:4048$499 + attribute \src "ls180.v:2757.190-2757.259" + cell $and $and$ls180.v:2757$500 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4048$498_Y - connect \Y $and$ls180.v:4048$499_Y + connect \A \sdram_interface_bank1_lock + connect \B $eq$ls180.v:2757$499_Y + connect \Y $and$ls180.v:2757$500_Y end - attribute \src "ls180.v:4048.185-4048.254" - cell $and $and$ls180.v:4048$502 + attribute \src "ls180.v:2757.265-2757.334" + cell $and $and$ls180.v:2757$503 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4048$501_Y - connect \Y $and$ls180.v:4048$502_Y + connect \A \sdram_interface_bank2_lock + connect \B $eq$ls180.v:2757$502_Y + connect \Y $and$ls180.v:2757$503_Y end - attribute \src "ls180.v:4048.260-4048.329" - cell $and $and$ls180.v:4048$505 + attribute \src "ls180.v:2757.46-2757.337" + cell $and $and$ls180.v:2757$506 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4048$504_Y - connect \Y $and$ls180.v:4048$505_Y + connect \A $eq$ls180.v:2757$495_Y + connect \B $not$ls180.v:2757$505_Y + connect \Y $and$ls180.v:2757$506_Y end - attribute \src "ls180.v:4048.41-4048.332" - cell $and $and$ls180.v:4048$508 + attribute \src "ls180.v:2757.45-2757.355" + cell $and $and$ls180.v:2757$507 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4048$497_Y - connect \B $not$ls180.v:4048$507_Y - connect \Y $and$ls180.v:4048$508_Y + connect \A $and$ls180.v:2757$506_Y + connect \B \port_cmd_valid + connect \Y $and$ls180.v:2757$507_Y end - attribute \src "ls180.v:4048.40-4048.355" - cell $and $and$ls180.v:4048$509 + attribute \src "ls180.v:2758.39-2758.101" + cell $and $and$ls180.v:2758$510 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4048$508_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:4048$509_Y + connect \A $not$ls180.v:2758$508_Y + connect \B $not$ls180.v:2758$509_Y + connect \Y $and$ls180.v:2758$510_Y end - attribute \src "ls180.v:4049.34-4049.106" - cell $and $and$ls180.v:4049$512 + attribute \src "ls180.v:2762.151-2762.220" + cell $and $and$ls180.v:2762$514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4049$510_Y - connect \B $not$ls180.v:4049$511_Y - connect \Y $and$ls180.v:4049$512_Y + connect \A \sdram_interface_bank1_lock + connect \B $eq$ls180.v:2762$513_Y + connect \Y $and$ls180.v:2762$514_Y end - attribute \src "ls180.v:4053.151-4053.220" - cell $and $and$ls180.v:4053$516 + attribute \src "ls180.v:2762.226-2762.295" + cell $and $and$ls180.v:2762$517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4053$515_Y - connect \Y $and$ls180.v:4053$516_Y + connect \A \sdram_interface_bank2_lock + connect \B $eq$ls180.v:2762$516_Y + connect \Y $and$ls180.v:2762$517_Y end - attribute \src "ls180.v:4053.226-4053.295" - cell $and $and$ls180.v:4053$519 + attribute \src "ls180.v:2762.301-2762.370" + cell $and $and$ls180.v:2762$520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4053$518_Y - connect \Y $and$ls180.v:4053$519_Y + connect \A \sdram_interface_bank3_lock + connect \B $eq$ls180.v:2762$519_Y + connect \Y $and$ls180.v:2762$520_Y end - attribute \src "ls180.v:4053.301-4053.370" - cell $and $and$ls180.v:4053$522 + attribute \src "ls180.v:2762.82-2762.373" + cell $and $and$ls180.v:2762$523 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4053$521_Y - connect \Y $and$ls180.v:4053$522_Y + connect \A $eq$ls180.v:2762$512_Y + connect \B $not$ls180.v:2762$522_Y + connect \Y $and$ls180.v:2762$523_Y end - attribute \src "ls180.v:4053.82-4053.373" - cell $and $and$ls180.v:4053$525 + attribute \src "ls180.v:2762.38-2762.374" + cell $and $and$ls180.v:2762$524 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4053$514_Y - connect \B $not$ls180.v:4053$524_Y - connect \Y $and$ls180.v:4053$525_Y + connect \A $eq$ls180.v:2762$511_Y + connect \B $and$ls180.v:2762$523_Y + connect \Y $and$ls180.v:2762$524_Y end - attribute \src "ls180.v:4053.43-4053.374" - cell $and $and$ls180.v:4053$526 + attribute \src "ls180.v:2762.37-2762.405" + cell $and $and$ls180.v:2762$525 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4053$513_Y - connect \B $and$ls180.v:4053$525_Y - connect \Y $and$ls180.v:4053$526_Y + connect \A $and$ls180.v:2762$524_Y + connect \B \sdram_interface_bank0_ready + connect \Y $and$ls180.v:2762$525_Y end - attribute \src "ls180.v:4053.42-4053.410" - cell $and $and$ls180.v:4053$527 + attribute \src "ls180.v:2762.525-2762.594" + cell $and $and$ls180.v:2762$530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4053$526_Y - connect \B \main_sdram_interface_bank0_ready - connect \Y $and$ls180.v:4053$527_Y + connect \A \sdram_interface_bank0_lock + connect \B $eq$ls180.v:2762$529_Y + connect \Y $and$ls180.v:2762$530_Y end - attribute \src "ls180.v:4053.525-4053.594" - cell $and $and$ls180.v:4053$532 + attribute \src "ls180.v:2762.600-2762.669" + cell $and $and$ls180.v:2762$533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4053$531_Y - connect \Y $and$ls180.v:4053$532_Y + connect \A \sdram_interface_bank2_lock + connect \B $eq$ls180.v:2762$532_Y + connect \Y $and$ls180.v:2762$533_Y end - attribute \src "ls180.v:4053.600-4053.669" - cell $and $and$ls180.v:4053$535 + attribute \src "ls180.v:2762.675-2762.744" + cell $and $and$ls180.v:2762$536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4053$534_Y - connect \Y $and$ls180.v:4053$535_Y + connect \A \sdram_interface_bank3_lock + connect \B $eq$ls180.v:2762$535_Y + connect \Y $and$ls180.v:2762$536_Y end - attribute \src "ls180.v:4053.675-4053.744" - cell $and $and$ls180.v:4053$538 + attribute \src "ls180.v:2762.456-2762.747" + cell $and $and$ls180.v:2762$539 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4053$537_Y - connect \Y $and$ls180.v:4053$538_Y + connect \A $eq$ls180.v:2762$528_Y + connect \B $not$ls180.v:2762$538_Y + connect \Y $and$ls180.v:2762$539_Y end - attribute \src "ls180.v:4053.456-4053.747" - cell $and $and$ls180.v:4053$541 + attribute \src "ls180.v:2762.412-2762.748" + cell $and $and$ls180.v:2762$540 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4053$530_Y - connect \B $not$ls180.v:4053$540_Y - connect \Y $and$ls180.v:4053$541_Y + connect \A $eq$ls180.v:2762$527_Y + connect \B $and$ls180.v:2762$539_Y + connect \Y $and$ls180.v:2762$540_Y end - attribute \src "ls180.v:4053.417-4053.748" - cell $and $and$ls180.v:4053$542 + attribute \src "ls180.v:2762.411-2762.779" + cell $and $and$ls180.v:2762$541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4053$529_Y - connect \B $and$ls180.v:4053$541_Y - connect \Y $and$ls180.v:4053$542_Y + connect \A $and$ls180.v:2762$540_Y + connect \B \sdram_interface_bank1_ready + connect \Y $and$ls180.v:2762$541_Y end - attribute \src "ls180.v:4053.416-4053.784" - cell $and $and$ls180.v:4053$543 + attribute \src "ls180.v:2762.899-2762.968" + cell $and $and$ls180.v:2762$546 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4053$542_Y - connect \B \main_sdram_interface_bank1_ready - connect \Y $and$ls180.v:4053$543_Y + connect \A \sdram_interface_bank0_lock + connect \B $eq$ls180.v:2762$545_Y + connect \Y $and$ls180.v:2762$546_Y end - attribute \src "ls180.v:4053.899-4053.968" - cell $and $and$ls180.v:4053$548 + attribute \src "ls180.v:2762.974-2762.1043" + cell $and $and$ls180.v:2762$549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4053$547_Y - connect \Y $and$ls180.v:4053$548_Y + connect \A \sdram_interface_bank1_lock + connect \B $eq$ls180.v:2762$548_Y + connect \Y $and$ls180.v:2762$549_Y end - attribute \src "ls180.v:4053.974-4053.1043" - cell $and $and$ls180.v:4053$551 + attribute \src "ls180.v:2762.1049-2762.1118" + cell $and $and$ls180.v:2762$552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4053$550_Y - connect \Y $and$ls180.v:4053$551_Y + connect \A \sdram_interface_bank3_lock + connect \B $eq$ls180.v:2762$551_Y + connect \Y $and$ls180.v:2762$552_Y end - attribute \src "ls180.v:4053.1049-4053.1118" - cell $and $and$ls180.v:4053$554 + attribute \src "ls180.v:2762.830-2762.1121" + cell $and $and$ls180.v:2762$555 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:4053$553_Y - connect \Y $and$ls180.v:4053$554_Y + connect \A $eq$ls180.v:2762$544_Y + connect \B $not$ls180.v:2762$554_Y + connect \Y $and$ls180.v:2762$555_Y end - attribute \src "ls180.v:4053.830-4053.1121" - cell $and $and$ls180.v:4053$557 + attribute \src "ls180.v:2762.786-2762.1122" + cell $and $and$ls180.v:2762$556 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4053$546_Y - connect \B $not$ls180.v:4053$556_Y - connect \Y $and$ls180.v:4053$557_Y + connect \A $eq$ls180.v:2762$543_Y + connect \B $and$ls180.v:2762$555_Y + connect \Y $and$ls180.v:2762$556_Y end - attribute \src "ls180.v:4053.791-4053.1122" - cell $and $and$ls180.v:4053$558 + attribute \src "ls180.v:2762.785-2762.1153" + cell $and $and$ls180.v:2762$557 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4053$545_Y - connect \B $and$ls180.v:4053$557_Y - connect \Y $and$ls180.v:4053$558_Y + connect \A $and$ls180.v:2762$556_Y + connect \B \sdram_interface_bank2_ready + connect \Y $and$ls180.v:2762$557_Y end - attribute \src "ls180.v:4053.790-4053.1158" - cell $and $and$ls180.v:4053$559 + attribute \src "ls180.v:2762.1273-2762.1342" + cell $and $and$ls180.v:2762$562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4053$558_Y - connect \B \main_sdram_interface_bank2_ready - connect \Y $and$ls180.v:4053$559_Y + connect \A \sdram_interface_bank0_lock + connect \B $eq$ls180.v:2762$561_Y + connect \Y $and$ls180.v:2762$562_Y end - attribute \src "ls180.v:4053.1273-4053.1342" - cell $and $and$ls180.v:4053$564 + attribute \src "ls180.v:2762.1348-2762.1417" + cell $and $and$ls180.v:2762$565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:4053$563_Y - connect \Y $and$ls180.v:4053$564_Y + connect \A \sdram_interface_bank1_lock + connect \B $eq$ls180.v:2762$564_Y + connect \Y $and$ls180.v:2762$565_Y end - attribute \src "ls180.v:4053.1348-4053.1417" - cell $and $and$ls180.v:4053$567 + attribute \src "ls180.v:2762.1423-2762.1492" + cell $and $and$ls180.v:2762$568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:4053$566_Y - connect \Y $and$ls180.v:4053$567_Y + connect \A \sdram_interface_bank2_lock + connect \B $eq$ls180.v:2762$567_Y + connect \Y $and$ls180.v:2762$568_Y end - attribute \src "ls180.v:4053.1423-4053.1492" - cell $and $and$ls180.v:4053$570 + attribute \src "ls180.v:2762.1204-2762.1495" + cell $and $and$ls180.v:2762$571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:4053$569_Y - connect \Y $and$ls180.v:4053$570_Y + connect \A $eq$ls180.v:2762$560_Y + connect \B $not$ls180.v:2762$570_Y + connect \Y $and$ls180.v:2762$571_Y end - attribute \src "ls180.v:4053.1204-4053.1495" - cell $and $and$ls180.v:4053$573 + attribute \src "ls180.v:2762.1160-2762.1496" + cell $and $and$ls180.v:2762$572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4053$562_Y - connect \B $not$ls180.v:4053$572_Y - connect \Y $and$ls180.v:4053$573_Y + connect \A $eq$ls180.v:2762$559_Y + connect \B $and$ls180.v:2762$571_Y + connect \Y $and$ls180.v:2762$572_Y end - attribute \src "ls180.v:4053.1165-4053.1496" - cell $and $and$ls180.v:4053$574 + attribute \src "ls180.v:2762.1159-2762.1527" + cell $and $and$ls180.v:2762$573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:4053$561_Y - connect \B $and$ls180.v:4053$573_Y - connect \Y $and$ls180.v:4053$574_Y + connect \A $and$ls180.v:2762$572_Y + connect \B \sdram_interface_bank3_ready + connect \Y $and$ls180.v:2762$573_Y end - attribute \src "ls180.v:4053.1164-4053.1532" - cell $and $and$ls180.v:4053$575 + attribute \src "ls180.v:2820.9-2820.36" + cell $and $and$ls180.v:2820$579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4053$574_Y - connect \B \main_sdram_interface_bank3_ready - connect \Y $and$ls180.v:4053$575_Y + connect \A \wb_sdram_stb + connect \B \wb_sdram_cyc + connect \Y $and$ls180.v:2820$579_Y end - attribute \src "ls180.v:4111.9-4111.46" - cell $and $and$ls180.v:4111$581 + attribute \src "ls180.v:2838.9-2838.36" + cell $and $and$ls180.v:2838$586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_wb_sdram_stb - connect \B \main_wb_sdram_cyc - connect \Y $and$ls180.v:4111$581_Y + connect \A \wb_sdram_stb + connect \B \wb_sdram_cyc + connect \Y $and$ls180.v:2838$586_Y end - attribute \src "ls180.v:4129.9-4129.46" - cell $and $and$ls180.v:4129$588 + attribute \src "ls180.v:2851.27-2851.60" + cell $and $and$ls180.v:2851$590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_wb_sdram_stb - connect \B \main_wb_sdram_cyc - connect \Y $and$ls180.v:4129$588_Y + connect \A \litedram_wb_cyc + connect \B \litedram_wb_stb + connect \Y $and$ls180.v:2851$590_Y end - attribute \src "ls180.v:4142.32-4142.75" - cell $and $and$ls180.v:4142$592 + attribute \src "ls180.v:2851.26-2851.79" + cell $and $and$ls180.v:2851$592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_cyc - connect \B \main_litedram_wb_stb - connect \Y $and$ls180.v:4142$592_Y + connect \A $and$ls180.v:2851$590_Y + connect \B $not$ls180.v:2851$591_Y + connect \Y $and$ls180.v:2851$592_Y end - attribute \src "ls180.v:4142.31-4142.99" - cell $and $and$ls180.v:4142$594 + attribute \src "ls180.v:2852.29-2852.82" + cell $and $and$ls180.v:2852$594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4142$592_Y - connect \B $not$ls180.v:4142$593_Y - connect \Y $and$ls180.v:4142$594_Y + connect \A $or$ls180.v:2852$593_Y + connect \B \port_cmd_payload_we + connect \Y $and$ls180.v:2852$594_Y end - attribute \src "ls180.v:4143.34-4143.102" - cell $and $and$ls180.v:4143$596 + attribute \src "ls180.v:2852.28-2852.103" + cell $and $and$ls180.v:2852$596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4143$595_Y - connect \B \main_port_cmd_payload_we - connect \Y $and$ls180.v:4143$596_Y + connect \A $and$ls180.v:2852$594_Y + connect \B $not$ls180.v:2852$595_Y + connect \Y $and$ls180.v:2852$596_Y end - attribute \src "ls180.v:4143.33-4143.128" - cell $and $and$ls180.v:4143$598 + attribute \src "ls180.v:2853.28-2853.84" + cell $and $and$ls180.v:2853$599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4143$596_Y - connect \B $not$ls180.v:4143$597_Y - connect \Y $and$ls180.v:4143$598_Y + connect \A $or$ls180.v:2853$597_Y + connect \B $not$ls180.v:2853$598_Y + connect \Y $and$ls180.v:2853$599_Y end - attribute \src "ls180.v:4144.33-4144.104" - cell $and $and$ls180.v:4144$601 + attribute \src "ls180.v:2854.39-2854.65" + cell $and $and$ls180.v:2854$600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4144$599_Y - connect \B $not$ls180.v:4144$600_Y - connect \Y $and$ls180.v:4144$601_Y + connect \A \litedram_wb_we + connect \B \ack_wdata + connect \Y $and$ls180.v:2854$600_Y end - attribute \src "ls180.v:4145.49-4145.85" - cell $and $and$ls180.v:4145$602 + attribute \src "ls180.v:2854.70-2854.99" + cell $and $and$ls180.v:2854$602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_we - connect \B \main_ack_wdata - connect \Y $and$ls180.v:4145$602_Y + connect \A $not$ls180.v:2854$601_Y + connect \B \ack_rdata + connect \Y $and$ls180.v:2854$602_Y end - attribute \src "ls180.v:4145.90-4145.129" - cell $and $and$ls180.v:4145$604 + attribute \src "ls180.v:2854.27-2854.101" + cell $and $and$ls180.v:2854$604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4145$603_Y - connect \B \main_ack_rdata - connect \Y $and$ls180.v:4145$604_Y + connect \A \ack_cmd + connect \B $or$ls180.v:2854$603_Y + connect \Y $and$ls180.v:2854$604_Y end - attribute \src "ls180.v:4145.32-4145.131" - cell $and $and$ls180.v:4145$606 + attribute \src "ls180.v:2855.20-2855.51" + cell $and $and$ls180.v:2855$605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_ack_cmd - connect \B $or$ls180.v:4145$605_Y - connect \Y $and$ls180.v:4145$606_Y + connect \A \port_cmd_valid + connect \B \port_cmd_ready + connect \Y $and$ls180.v:2855$605_Y end - attribute \src "ls180.v:4146.25-4146.66" - cell $and $and$ls180.v:4146$607 + attribute \src "ls180.v:2856.22-2856.57" + cell $and $and$ls180.v:2856$607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_port_cmd_valid - connect \B \main_port_cmd_ready - connect \Y $and$ls180.v:4146$607_Y + connect \A \port_wdata_valid + connect \B \port_wdata_ready + connect \Y $and$ls180.v:2856$607_Y end - attribute \src "ls180.v:4147.27-4147.72" - cell $and $and$ls180.v:4147$609 + attribute \src "ls180.v:2857.21-2857.56" + cell $and $and$ls180.v:2857$609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_port_wdata_valid - connect \B \main_port_wdata_ready - connect \Y $and$ls180.v:4147$609_Y + connect \A \port_rdata_valid + connect \B \port_rdata_ready + connect \Y $and$ls180.v:2857$609_Y end - attribute \src "ls180.v:4148.26-4148.71" - cell $and $and$ls180.v:4148$611 + attribute \src "ls180.v:2886.44-2886.58" + cell $and $and$ls180.v:2886$615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_port_rdata_valid - connect \B \main_port_rdata_ready - connect \Y $and$ls180.v:4148$611_Y + connect \A 1'0 + connect \B \rxtx_we + connect \Y $and$ls180.v:2886$615_Y end - attribute \src "ls180.v:4177.64-4177.88" - cell $and $and$ls180.v:4177$617 + attribute \src "ls180.v:2890.7-2890.58" + cell $and $and$ls180.v:2890$619 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A 1'0 - connect \B \main_uart_rxtx_we - connect \Y $and$ls180.v:4177$617_Y + connect \A \eventmanager_pending_re + connect \B \eventmanager_pending_r [0] + connect \Y $and$ls180.v:2890$619_Y end - attribute \src "ls180.v:4181.7-4181.78" - cell $and $and$ls180.v:4181$621 + attribute \src "ls180.v:2901.7-2901.58" + cell $and $and$ls180.v:2901$622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_uart_eventmanager_pending_re - connect \B \main_uart_eventmanager_pending_r [0] - connect \Y $and$ls180.v:4181$621_Y + connect \A \eventmanager_pending_re + connect \B \eventmanager_pending_r [1] + connect \Y $and$ls180.v:2901$622_Y end - attribute \src "ls180.v:4192.7-4192.78" - cell $and $and$ls180.v:4192$624 + attribute \src "ls180.v:2910.16-2910.67" + cell $and $and$ls180.v:2910$624 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_uart_eventmanager_pending_re - connect \B \main_uart_eventmanager_pending_r [1] - connect \Y $and$ls180.v:4192$624_Y + connect \A \eventmanager_pending_w [0] + connect \B \eventmanager_storage [0] + connect \Y $and$ls180.v:2910$624_Y end - attribute \src "ls180.v:4201.26-4201.97" - cell $and $and$ls180.v:4201$626 + attribute \src "ls180.v:2910.72-2910.123" + cell $and $and$ls180.v:2910$625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_uart_eventmanager_pending_w [0] - connect \B \main_uart_eventmanager_storage [0] - connect \Y $and$ls180.v:4201$626_Y + connect \A \eventmanager_pending_w [1] + connect \B \eventmanager_storage [1] + connect \Y $and$ls180.v:2910$625_Y end - attribute \src "ls180.v:4201.102-4201.173" - cell $and $and$ls180.v:4201$627 + attribute \src "ls180.v:2925.31-2925.93" + cell $and $and$ls180.v:2925$629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_uart_eventmanager_pending_w [1] - connect \B \main_uart_eventmanager_storage [1] - connect \Y $and$ls180.v:4201$627_Y + connect \A \tx_fifo_syncfifo_readable + connect \B $or$ls180.v:2925$628_Y + connect \Y $and$ls180.v:2925$629_Y end - attribute \src "ls180.v:4216.41-4216.133" - cell $and $and$ls180.v:4216$631 + attribute \src "ls180.v:2936.29-2936.96" + cell $and $and$ls180.v:2936$634 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_syncfifo_readable - connect \B $or$ls180.v:4216$630_Y - connect \Y $and$ls180.v:4216$631_Y + connect \A \tx_fifo_syncfifo_we + connect \B $or$ls180.v:2936$633_Y + connect \Y $and$ls180.v:2936$634_Y end - attribute \src "ls180.v:4227.39-4227.136" - cell $and $and$ls180.v:4227$636 + attribute \src "ls180.v:2937.27-2937.74" + cell $and $and$ls180.v:2937$635 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_syncfifo_we - connect \B $or$ls180.v:4227$635_Y - connect \Y $and$ls180.v:4227$636_Y + connect \A \tx_fifo_syncfifo_readable + connect \B \tx_fifo_syncfifo_re + connect \Y $and$ls180.v:2937$635_Y end - attribute \src "ls180.v:4228.37-4228.104" - cell $and $and$ls180.v:4228$637 + attribute \src "ls180.v:2955.31-2955.93" + cell $and $and$ls180.v:2955$640 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_syncfifo_readable - connect \B \main_uart_tx_fifo_syncfifo_re - connect \Y $and$ls180.v:4228$637_Y + connect \A \rx_fifo_syncfifo_readable + connect \B $or$ls180.v:2955$639_Y + connect \Y $and$ls180.v:2955$640_Y end - attribute \src "ls180.v:4246.41-4246.133" - cell $and $and$ls180.v:4246$642 + attribute \src "ls180.v:2966.29-2966.96" + cell $and $and$ls180.v:2966$645 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_syncfifo_readable - connect \B $or$ls180.v:4246$641_Y - connect \Y $and$ls180.v:4246$642_Y + connect \A \rx_fifo_syncfifo_we + connect \B $or$ls180.v:2966$644_Y + connect \Y $and$ls180.v:2966$645_Y end - attribute \src "ls180.v:4257.39-4257.136" - cell $and $and$ls180.v:4257$647 + attribute \src "ls180.v:2967.27-2967.74" + cell $and $and$ls180.v:2967$646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_syncfifo_we - connect \B $or$ls180.v:4257$646_Y - connect \Y $and$ls180.v:4257$647_Y + connect \A \rx_fifo_syncfifo_readable + connect \B \rx_fifo_syncfifo_re + connect \Y $and$ls180.v:2967$646_Y end - attribute \src "ls180.v:4258.37-4258.104" - cell $and $and$ls180.v:4258$648 + attribute \src "ls180.v:3064.9-3064.84" + cell $and $and$ls180.v:3064$654 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_syncfifo_readable - connect \B \main_uart_rx_fifo_syncfifo_re - connect \Y $and$ls180.v:4258$648_Y + connect \A \libresocsim_libresocsim_wishbone_cyc + connect \B \libresocsim_libresocsim_wishbone_stb + connect \Y $and$ls180.v:3064$654_Y end - attribute \src "ls180.v:4457.33-4457.86" - cell $and $and$ls180.v:4457$692 + attribute \src "ls180.v:3067.60-3067.144" + cell $and $and$ls180.v:3067$656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_clocker_clk1 - connect \B $not$ls180.v:4457$691_Y - connect \Y $and$ls180.v:4457$692_Y + connect \A \libresocsim_libresocsim_wishbone_we + connect \B $ne$ls180.v:3067$655_Y + connect \Y $and$ls180.v:3067$656_Y end - attribute \src "ls180.v:4561.9-4561.68" - cell $and $and$ls180.v:4561$701 + attribute \src "ls180.v:3085.41-3085.93" + cell $and $and$ls180.v:3085$658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdw_sink_valid - connect \B \main_sdphy_cmdw_pads_out_ready - connect \Y $and$ls180.v:4561$701_Y + connect \A \libresocsim_shared_ack + connect \B $eq$ls180.v:3085$657_Y + connect \Y $and$ls180.v:3085$658_Y end - attribute \src "ls180.v:4581.53-4581.145" - cell $and $and$ls180.v:4581$704 + attribute \src "ls180.v:3086.41-3086.93" + cell $and $and$ls180.v:3086$660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_pads_in_valid - connect \B $or$ls180.v:4581$703_Y - connect \Y $and$ls180.v:4581$704_Y + connect \A \libresocsim_shared_ack + connect \B $eq$ls180.v:3086$659_Y + connect \Y $and$ls180.v:3086$660_Y end - attribute \src "ls180.v:4600.52-4600.137" - cell $and $and$ls180.v:4600$707 + attribute \src "ls180.v:3087.44-3087.96" + cell $and $and$ls180.v:3087$662 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid - connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:4600$707_Y + connect \A \libresocsim_shared_ack + connect \B $eq$ls180.v:3087$661_Y + connect \Y $and$ls180.v:3087$662_Y end - attribute \src "ls180.v:4641.9-4641.68" - cell $and $and$ls180.v:4641$715 + attribute \src "ls180.v:3088.41-3088.93" + cell $and $and$ls180.v:3088$664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_source_valid - connect \B \main_sdphy_cmdr_source_ready - connect \Y $and$ls180.v:4641$715_Y + connect \A \libresocsim_shared_err + connect \B $eq$ls180.v:3088$663_Y + connect \Y $and$ls180.v:3088$664_Y end - attribute \src "ls180.v:4679.9-4679.68" - cell $and $and$ls180.v:4679$721 + attribute \src "ls180.v:3089.41-3089.93" + cell $and $and$ls180.v:3089$666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_source_valid - connect \B \main_sdphy_cmdr_source_ready - connect \Y $and$ls180.v:4679$721_Y + connect \A \libresocsim_shared_err + connect \B $eq$ls180.v:3089$665_Y + connect \Y $and$ls180.v:3089$666_Y end - attribute \src "ls180.v:4688.10-4688.69" - cell $and $and$ls180.v:4688$722 + attribute \src "ls180.v:3090.44-3090.96" + cell $and $and$ls180.v:3090$668 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_sink_valid - connect \B \main_sdphy_cmdr_pads_out_ready - connect \Y $and$ls180.v:4688$722_Y + connect \A \libresocsim_shared_err + connect \B $eq$ls180.v:3090$667_Y + connect \Y $and$ls180.v:3090$668_Y end - attribute \src "ls180.v:4688.9-4688.93" - cell $and $and$ls180.v:4688$723 + attribute \src "ls180.v:3143.35-3143.84" + cell $and $and$ls180.v:3143$676 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4688$722_Y - connect \B \main_sdphy_cmdw_done - connect \Y $and$ls180.v:4688$723_Y + connect \A \libresocsim_shared_cyc + connect \B \libresocsim_slave_sel [0] + connect \Y $and$ls180.v:3143$676_Y end - attribute \src "ls180.v:4708.54-4708.117" - cell $and $and$ls180.v:4708$725 + attribute \src "ls180.v:3144.31-3144.80" + cell $and $and$ls180.v:3144$677 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_pads_in_valid - connect \B \main_sdphy_dataw_crcr_run - connect \Y $and$ls180.v:4708$725_Y + connect \A \libresocsim_shared_cyc + connect \B \libresocsim_slave_sel [1] + connect \Y $and$ls180.v:3144$677_Y end - attribute \src "ls180.v:4727.53-4727.140" - cell $and $and$ls180.v:4727$728 + attribute \src "ls180.v:3145.46-3145.95" + cell $and $and$ls180.v:3145$678 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_converter_sink_valid - connect \B \main_sdphy_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:4727$728_Y + connect \A \libresocsim_shared_cyc + connect \B \libresocsim_slave_sel [2] + connect \Y $and$ls180.v:3145$678_Y end - attribute \src "ls180.v:4824.9-4824.70" - cell $and $and$ls180.v:4824$738 + attribute \src "ls180.v:3146.46-3146.95" + cell $and $and$ls180.v:3146$679 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_sink_valid - connect \B \main_sdphy_dataw_pads_out_ready - connect \Y $and$ls180.v:4824$738_Y + connect \A \libresocsim_shared_cyc + connect \B \libresocsim_slave_sel [3] + connect \Y $and$ls180.v:3146$679_Y end - attribute \src "ls180.v:4842.55-4842.120" - cell $and $and$ls180.v:4842$740 + attribute \src "ls180.v:3147.49-3147.98" + cell $and $and$ls180.v:3147$680 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_pads_in_valid - connect \B \main_sdphy_datar_datar_run - connect \Y $and$ls180.v:4842$740_Y + connect \A \libresocsim_shared_cyc + connect \B \libresocsim_slave_sel [4] + connect \Y $and$ls180.v:3147$680_Y end - attribute \src "ls180.v:4861.54-4861.143" - cell $and $and$ls180.v:4861$743 + attribute \src "ls180.v:3148.59-3148.108" + cell $and $and$ls180.v:3148$681 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_sink_valid - connect \B \main_sdphy_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:4861$743_Y + connect \A \libresocsim_shared_cyc + connect \B \libresocsim_slave_sel [5] + connect \Y $and$ls180.v:3148$681_Y end - attribute \src "ls180.v:4943.9-4943.70" - cell $and $and$ls180.v:4943$758 + attribute \src "ls180.v:3150.29-3150.76" + cell $and $and$ls180.v:3150$687 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_source_valid - connect \B \main_sdphy_datar_source_ready - connect \Y $and$ls180.v:4943$758_Y + connect \A \libresocsim_shared_stb + connect \B \libresocsim_shared_cyc + connect \Y $and$ls180.v:3150$687_Y end - attribute \src "ls180.v:4950.9-4950.70" - cell $and $and$ls180.v:4950$759 + attribute \src "ls180.v:3150.28-3150.105" + cell $and $and$ls180.v:3150$689 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_sink_valid - connect \B \main_sdphy_datar_pads_out_ready - connect \Y $and$ls180.v:4950$759_Y + connect \A $and$ls180.v:3150$687_Y + connect \B $not$ls180.v:3150$688_Y + connect \Y $and$ls180.v:3150$689_Y end - attribute \src "ls180.v:5031.48-5031.124" - cell $and $and$ls180.v:5031$882 + attribute \src "ls180.v:3156.36-3156.96" + cell $and $and$ls180.v:3156$696 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_last - connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:5031$882_Y + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] \libresocsim_slave_sel_r [0] } + connect \B \libresocsim_ram_bus_dat_r + connect \Y $and$ls180.v:3156$696_Y end - attribute \src "ls180.v:5031.47-5031.165" - cell $and $and$ls180.v:5031$883 + attribute \src "ls180.v:3156.101-3156.157" + cell $and $and$ls180.v:3156$697 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5031$882_Y - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5031$883_Y + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] \libresocsim_slave_sel_r [1] } + connect \B \ram_bus_ram_bus_dat_r + connect \Y $and$ls180.v:3156$697_Y end - attribute \src "ls180.v:5032.50-5032.127" - cell $and $and$ls180.v:5032$884 + attribute \src "ls180.v:3156.163-3156.234" + cell $and $and$ls180.v:3156$699 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_valid - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5032$884_Y + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] \libresocsim_slave_sel_r [2] } + connect \B \interface0_converted_interface_dat_r + connect \Y $and$ls180.v:3156$699_Y end - attribute \src "ls180.v:5034.48-5034.124" - cell $and $and$ls180.v:5034$885 + attribute \src "ls180.v:3156.240-3156.311" + cell $and $and$ls180.v:3156$701 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_last - connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:5034$885_Y + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] \libresocsim_slave_sel_r [3] } + connect \B \interface1_converted_interface_dat_r + connect \Y $and$ls180.v:3156$701_Y end - attribute \src "ls180.v:5034.47-5034.165" - cell $and $and$ls180.v:5034$886 + attribute \src "ls180.v:3156.317-3156.391" + cell $and $and$ls180.v:3156$703 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5034$885_Y - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5034$886_Y + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] \libresocsim_slave_sel_r [4] } + connect \B \socbushandler_converted_interface_dat_r + connect \Y $and$ls180.v:3156$703_Y end - attribute \src "ls180.v:5035.50-5035.127" - cell $and $and$ls180.v:5035$887 + attribute \src "ls180.v:3156.397-3156.481" + cell $and $and$ls180.v:3156$705 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_valid - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5035$887_Y + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] \libresocsim_slave_sel_r [5] } + connect \B \libresocsim_libresocsim_converted_interface_dat_r + connect \Y $and$ls180.v:3156$705_Y end - attribute \src "ls180.v:5037.48-5037.124" - cell $and $and$ls180.v:5037$888 + attribute \src "ls180.v:3166.43-3166.104" + cell $and $and$ls180.v:3166$709 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_last - connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:5037$888_Y + connect \A \libresocsim_csrbank0_sel + connect \B \libresocsim_interface0_bank_bus_we + connect \Y $and$ls180.v:3166$709_Y end - attribute \src "ls180.v:5037.47-5037.165" - cell $and $and$ls180.v:5037$889 + attribute \src "ls180.v:3166.42-3166.158" + cell $and $and$ls180.v:3166$711 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5037$888_Y - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5037$889_Y + connect \A $and$ls180.v:3166$709_Y + connect \B $eq$ls180.v:3166$710_Y + connect \Y $and$ls180.v:3166$711_Y end - attribute \src "ls180.v:5038.50-5038.127" - cell $and $and$ls180.v:5038$890 + attribute \src "ls180.v:3167.43-3167.107" + cell $and $and$ls180.v:3167$713 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_valid - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5038$890_Y + connect \A \libresocsim_csrbank0_sel + connect \B $not$ls180.v:3167$712_Y + connect \Y $and$ls180.v:3167$713_Y end - attribute \src "ls180.v:5040.48-5040.124" - cell $and $and$ls180.v:5040$891 + attribute \src "ls180.v:3167.42-3167.161" + cell $and $and$ls180.v:3167$715 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_last - connect \B \main_sdcore_crc16_inserter_sink_valid - connect \Y $and$ls180.v:5040$891_Y + connect \A $and$ls180.v:3167$713_Y + connect \B $eq$ls180.v:3167$714_Y + connect \Y $and$ls180.v:3167$715_Y end - attribute \src "ls180.v:5040.47-5040.165" - cell $and $and$ls180.v:5040$892 + attribute \src "ls180.v:3169.45-3169.106" + cell $and $and$ls180.v:3169$716 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5040$891_Y - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5040$892_Y + connect \A \libresocsim_csrbank0_sel + connect \B \libresocsim_interface0_bank_bus_we + connect \Y $and$ls180.v:3169$716_Y end - attribute \src "ls180.v:5041.50-5041.127" - cell $and $and$ls180.v:5041$893 + attribute \src "ls180.v:3169.44-3169.160" + cell $and $and$ls180.v:3169$718 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_valid - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5041$893_Y + connect \A $and$ls180.v:3169$716_Y + connect \B $eq$ls180.v:3169$717_Y + connect \Y $and$ls180.v:3169$718_Y end - attribute \src "ls180.v:5154.10-5154.86" - cell $and $and$ls180.v:5154$942 + attribute \src "ls180.v:3170.45-3170.109" + cell $and $and$ls180.v:3170$720 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_sink_valid - connect \B \main_sdcore_crc16_inserter_sink_last - connect \Y $and$ls180.v:5154$942_Y + connect \A \libresocsim_csrbank0_sel + connect \B $not$ls180.v:3170$719_Y + connect \Y $and$ls180.v:3170$720_Y end - attribute \src "ls180.v:5154.9-5154.127" - cell $and $and$ls180.v:5154$943 + attribute \src "ls180.v:3170.44-3170.163" + cell $and $and$ls180.v:3170$722 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5154$942_Y - connect \B \main_sdcore_crc16_inserter_sink_ready - connect \Y $and$ls180.v:5154$943_Y + connect \A $and$ls180.v:3170$720_Y + connect \B $eq$ls180.v:3170$721_Y + connect \Y $and$ls180.v:3170$722_Y end - attribute \src "ls180.v:5164.9-5164.152" - cell $and $and$ls180.v:5164$947 + attribute \src "ls180.v:3172.45-3172.106" + cell $and $and$ls180.v:3172$723 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:5164$945_Y - connect \B $eq$ls180.v:5164$946_Y - connect \Y $and$ls180.v:5164$947_Y + connect \A \libresocsim_csrbank0_sel + connect \B \libresocsim_interface0_bank_bus_we + connect \Y $and$ls180.v:3172$723_Y end - attribute \src "ls180.v:5164.8-5164.226" - cell $and $and$ls180.v:5164$949 + attribute \src "ls180.v:3172.44-3172.160" + cell $and $and$ls180.v:3172$725 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5164$947_Y - connect \B $eq$ls180.v:5164$948_Y - connect \Y $and$ls180.v:5164$949_Y + connect \A $and$ls180.v:3172$723_Y + connect \B $eq$ls180.v:3172$724_Y + connect \Y $and$ls180.v:3172$725_Y end - attribute \src "ls180.v:5164.7-5164.300" - cell $and $and$ls180.v:5164$951 + attribute \src "ls180.v:3173.45-3173.109" + cell $and $and$ls180.v:3173$727 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5164$949_Y - connect \B $eq$ls180.v:5164$950_Y - connect \Y $and$ls180.v:5164$951_Y + connect \A \libresocsim_csrbank0_sel + connect \B $not$ls180.v:3173$726_Y + connect \Y $and$ls180.v:3173$727_Y end - attribute \src "ls180.v:5169.49-5169.124" - cell $and $and$ls180.v:5169$952 + attribute \src "ls180.v:3173.44-3173.163" + cell $and $and$ls180.v:3173$729 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5169$952_Y + connect \A $and$ls180.v:3173$727_Y + connect \B $eq$ls180.v:3173$728_Y + connect \Y $and$ls180.v:3173$729_Y end - attribute \src "ls180.v:5179.49-5179.124" - cell $and $and$ls180.v:5179$955 + attribute \src "ls180.v:3175.45-3175.106" + cell $and $and$ls180.v:3175$730 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5179$955_Y + connect \A \libresocsim_csrbank0_sel + connect \B \libresocsim_interface0_bank_bus_we + connect \Y $and$ls180.v:3175$730_Y end - attribute \src "ls180.v:5189.49-5189.124" - cell $and $and$ls180.v:5189$958 + attribute \src "ls180.v:3175.44-3175.160" + cell $and $and$ls180.v:3175$732 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5189$958_Y + connect \A $and$ls180.v:3175$730_Y + connect \B $eq$ls180.v:3175$731_Y + connect \Y $and$ls180.v:3175$732_Y end - attribute \src "ls180.v:5199.49-5199.124" - cell $and $and$ls180.v:5199$961 + attribute \src "ls180.v:3176.45-3176.109" + cell $and $and$ls180.v:3176$734 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:5199$961_Y + connect \A \libresocsim_csrbank0_sel + connect \B $not$ls180.v:3176$733_Y + connect \Y $and$ls180.v:3176$734_Y end - attribute \src "ls180.v:5211.7-5211.84" - cell $and $and$ls180.v:5211$966 + attribute \src "ls180.v:3176.44-3176.163" + cell $and $and$ls180.v:3176$736 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B $gt$ls180.v:5211$965_Y - connect \Y $and$ls180.v:5211$966_Y + connect \A $and$ls180.v:3176$734_Y + connect \B $eq$ls180.v:3176$735_Y + connect \Y $and$ls180.v:3176$736_Y end - attribute \src "ls180.v:5329.9-5329.64" - cell $and $and$ls180.v:5329$1015 + attribute \src "ls180.v:3178.45-3178.106" + cell $and $and$ls180.v:3178$737 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdw_sink_valid - connect \B \main_sdphy_cmdw_sink_ready - connect \Y $and$ls180.v:5329$1015_Y + connect \A \libresocsim_csrbank0_sel + connect \B \libresocsim_interface0_bank_bus_we + connect \Y $and$ls180.v:3178$737_Y end - attribute \src "ls180.v:5381.10-5381.66" - cell $and $and$ls180.v:5381$1024 + attribute \src "ls180.v:3178.44-3178.160" + cell $and $and$ls180.v:3178$739 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_sink_valid - connect \B \main_sdphy_dataw_sink_last - connect \Y $and$ls180.v:5381$1024_Y + connect \A $and$ls180.v:3178$737_Y + connect \B $eq$ls180.v:3178$738_Y + connect \Y $and$ls180.v:3178$739_Y end - attribute \src "ls180.v:5381.9-5381.97" - cell $and $and$ls180.v:5381$1025 + attribute \src "ls180.v:3179.45-3179.109" + cell $and $and$ls180.v:3179$741 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5381$1024_Y - connect \B \main_sdphy_dataw_sink_ready - connect \Y $and$ls180.v:5381$1025_Y + connect \A \libresocsim_csrbank0_sel + connect \B $not$ls180.v:3179$740_Y + connect \Y $and$ls180.v:3179$741_Y end - attribute \src "ls180.v:5407.11-5407.71" - cell $and $and$ls180.v:5407$1033 + attribute \src "ls180.v:3179.44-3179.163" + cell $and $and$ls180.v:3179$743 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_source_last - connect \B \main_sdphy_datar_source_ready - connect \Y $and$ls180.v:5407$1033_Y + connect \A $and$ls180.v:3179$741_Y + connect \B $eq$ls180.v:3179$742_Y + connect \Y $and$ls180.v:3179$743_Y end - attribute \src "ls180.v:5491.43-5491.152" - cell $and $and$ls180.v:5491$1041 + attribute \src "ls180.v:3181.48-3181.109" + cell $and $and$ls180.v:3181$744 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_syncfifo_we - connect \B $or$ls180.v:5491$1040_Y - connect \Y $and$ls180.v:5491$1041_Y + connect \A \libresocsim_csrbank0_sel + connect \B \libresocsim_interface0_bank_bus_we + connect \Y $and$ls180.v:3181$744_Y end - attribute \src "ls180.v:5492.41-5492.116" - cell $and $and$ls180.v:5492$1042 + attribute \src "ls180.v:3181.47-3181.163" + cell $and $and$ls180.v:3181$746 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_syncfifo_readable - connect \B \main_sdblock2mem_fifo_syncfifo_re - connect \Y $and$ls180.v:5492$1042_Y + connect \A $and$ls180.v:3181$744_Y + connect \B $eq$ls180.v:3181$745_Y + connect \Y $and$ls180.v:3181$746_Y end - attribute \src "ls180.v:5504.48-5504.125" - cell $and $and$ls180.v:5504$1047 + attribute \src "ls180.v:3182.48-3182.112" + cell $and $and$ls180.v:3182$748 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_converter_sink_valid - connect \B \main_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:5504$1047_Y + connect \A \libresocsim_csrbank0_sel + connect \B $not$ls180.v:3182$747_Y + connect \Y $and$ls180.v:3182$748_Y end - attribute \src "ls180.v:5531.9-5531.102" - cell $and $and$ls180.v:5531$1051 + attribute \src "ls180.v:3182.47-3182.166" + cell $and $and$ls180.v:3182$750 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_wishbonedmawriter_sink_valid - connect \B \main_sdblock2mem_wishbonedmawriter_sink_ready - connect \Y $and$ls180.v:5531$1051_Y + connect \A $and$ls180.v:3182$748_Y + connect \B $eq$ls180.v:3182$749_Y + connect \Y $and$ls180.v:3182$750_Y end - attribute \src "ls180.v:5604.9-5604.58" - cell $and $and$ls180.v:5604$1057 + attribute \src "ls180.v:3184.48-3184.109" + cell $and $and$ls180.v:3184$751 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_interface1_bus_stb - connect \B \main_interface1_bus_ack - connect \Y $and$ls180.v:5604$1057_Y + connect \A \libresocsim_csrbank0_sel + connect \B \libresocsim_interface0_bank_bus_we + connect \Y $and$ls180.v:3184$751_Y end - attribute \src "ls180.v:5657.51-5657.123" - cell $and $and$ls180.v:5657$1065 + attribute \src "ls180.v:3184.47-3184.163" + cell $and $and$ls180.v:3184$753 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_converter_sink_first - connect \B \main_sdmem2block_converter_first - connect \Y $and$ls180.v:5657$1065_Y + connect \A $and$ls180.v:3184$751_Y + connect \B $eq$ls180.v:3184$752_Y + connect \Y $and$ls180.v:3184$753_Y end - attribute \src "ls180.v:5658.50-5658.120" - cell $and $and$ls180.v:5658$1066 + attribute \src "ls180.v:3185.48-3185.112" + cell $and $and$ls180.v:3185$755 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_converter_sink_last - connect \B \main_sdmem2block_converter_last - connect \Y $and$ls180.v:5658$1066_Y + connect \A \libresocsim_csrbank0_sel + connect \B $not$ls180.v:3185$754_Y + connect \Y $and$ls180.v:3185$755_Y end - attribute \src "ls180.v:5659.49-5659.122" - cell $and $and$ls180.v:5659$1067 + attribute \src "ls180.v:3185.47-3185.166" + cell $and $and$ls180.v:3185$757 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_converter_last - connect \B \main_sdmem2block_converter_source_ready - connect \Y $and$ls180.v:5659$1067_Y + connect \A $and$ls180.v:3185$755_Y + connect \B $eq$ls180.v:3185$756_Y + connect \Y $and$ls180.v:3185$757_Y end - attribute \src "ls180.v:5711.43-5711.152" - cell $and $and$ls180.v:5711$1072 + attribute \src "ls180.v:3187.48-3187.109" + cell $and $and$ls180.v:3187$758 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_syncfifo_we - connect \B $or$ls180.v:5711$1071_Y - connect \Y $and$ls180.v:5711$1072_Y + connect \A \libresocsim_csrbank0_sel + connect \B \libresocsim_interface0_bank_bus_we + connect \Y $and$ls180.v:3187$758_Y end - attribute \src "ls180.v:5712.41-5712.116" - cell $and $and$ls180.v:5712$1073 + attribute \src "ls180.v:3187.47-3187.163" + cell $and $and$ls180.v:3187$760 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_syncfifo_readable - connect \B \main_sdmem2block_fifo_syncfifo_re - connect \Y $and$ls180.v:5712$1073_Y + connect \A $and$ls180.v:3187$758_Y + connect \B $eq$ls180.v:3187$759_Y + connect \Y $and$ls180.v:3187$760_Y end - attribute \src "ls180.v:5744.9-5744.76" - cell $and $and$ls180.v:5744$1077 + attribute \src "ls180.v:3188.48-3188.112" + cell $and $and$ls180.v:3188$762 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_libresocsim_wishbone_cyc - connect \B \builder_libresocsim_wishbone_stb - connect \Y $and$ls180.v:5744$1077_Y + connect \A \libresocsim_csrbank0_sel + connect \B $not$ls180.v:3188$761_Y + connect \Y $and$ls180.v:3188$762_Y end - attribute \src "ls180.v:5747.44-5747.120" - cell $and $and$ls180.v:5747$1079 + attribute \src "ls180.v:3188.47-3188.166" + cell $and $and$ls180.v:3188$764 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_libresocsim_wishbone_we - connect \B $ne$ls180.v:5747$1078_Y - connect \Y $and$ls180.v:5747$1079_Y + connect \A $and$ls180.v:3188$762_Y + connect \B $eq$ls180.v:3188$763_Y + connect \Y $and$ls180.v:3188$764_Y end - attribute \src "ls180.v:5767.46-5767.90" - cell $and $and$ls180.v:5767$1081 + attribute \src "ls180.v:3190.48-3190.109" + cell $and $and$ls180.v:3190$765 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_ack - connect \B $eq$ls180.v:5767$1080_Y - connect \Y $and$ls180.v:5767$1081_Y + connect \A \libresocsim_csrbank0_sel + connect \B \libresocsim_interface0_bank_bus_we + connect \Y $and$ls180.v:3190$765_Y end - attribute \src "ls180.v:5768.46-5768.90" - cell $and $and$ls180.v:5768$1083 + attribute \src "ls180.v:3190.47-3190.163" + cell $and $and$ls180.v:3190$767 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_ack - connect \B $eq$ls180.v:5768$1082_Y - connect \Y $and$ls180.v:5768$1083_Y + connect \A $and$ls180.v:3190$765_Y + connect \B $eq$ls180.v:3190$766_Y + connect \Y $and$ls180.v:3190$767_Y end - attribute \src "ls180.v:5769.49-5769.93" - cell $and $and$ls180.v:5769$1085 + attribute \src "ls180.v:3191.48-3191.112" + cell $and $and$ls180.v:3191$769 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_ack - connect \B $eq$ls180.v:5769$1084_Y - connect \Y $and$ls180.v:5769$1085_Y + connect \A \libresocsim_csrbank0_sel + connect \B $not$ls180.v:3191$768_Y + connect \Y $and$ls180.v:3191$769_Y end - attribute \src "ls180.v:5770.35-5770.79" - cell $and $and$ls180.v:5770$1087 + attribute \src "ls180.v:3191.47-3191.166" + cell $and $and$ls180.v:3191$771 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_ack - connect \B $eq$ls180.v:5770$1086_Y - connect \Y $and$ls180.v:5770$1087_Y + connect \A $and$ls180.v:3191$769_Y + connect \B $eq$ls180.v:3191$770_Y + connect \Y $and$ls180.v:3191$771_Y end - attribute \src "ls180.v:5771.35-5771.79" - cell $and $and$ls180.v:5771$1089 + attribute \src "ls180.v:3204.40-3204.101" + cell $and $and$ls180.v:3204$773 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_ack - connect \B $eq$ls180.v:5771$1088_Y - connect \Y $and$ls180.v:5771$1089_Y + connect \A \libresocsim_csrbank1_sel + connect \B \libresocsim_interface1_bank_bus_we + connect \Y $and$ls180.v:3204$773_Y end - attribute \src "ls180.v:5772.46-5772.90" - cell $and $and$ls180.v:5772$1091 + attribute \src "ls180.v:3204.39-3204.155" + cell $and $and$ls180.v:3204$775 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_err - connect \B $eq$ls180.v:5772$1090_Y - connect \Y $and$ls180.v:5772$1091_Y + connect \A $and$ls180.v:3204$773_Y + connect \B $eq$ls180.v:3204$774_Y + connect \Y $and$ls180.v:3204$775_Y end - attribute \src "ls180.v:5773.46-5773.90" - cell $and $and$ls180.v:5773$1093 + attribute \src "ls180.v:3205.40-3205.104" + cell $and $and$ls180.v:3205$777 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_err - connect \B $eq$ls180.v:5773$1092_Y - connect \Y $and$ls180.v:5773$1093_Y + connect \A \libresocsim_csrbank1_sel + connect \B $not$ls180.v:3205$776_Y + connect \Y $and$ls180.v:3205$777_Y end - attribute \src "ls180.v:5774.49-5774.93" - cell $and $and$ls180.v:5774$1095 + attribute \src "ls180.v:3205.39-3205.158" + cell $and $and$ls180.v:3205$779 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_err - connect \B $eq$ls180.v:5774$1094_Y - connect \Y $and$ls180.v:5774$1095_Y + connect \A $and$ls180.v:3205$777_Y + connect \B $eq$ls180.v:3205$778_Y + connect \Y $and$ls180.v:3205$779_Y end - attribute \src "ls180.v:5775.35-5775.79" - cell $and $and$ls180.v:5775$1097 + attribute \src "ls180.v:3207.39-3207.100" + cell $and $and$ls180.v:3207$780 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_err - connect \B $eq$ls180.v:5775$1096_Y - connect \Y $and$ls180.v:5775$1097_Y + connect \A \libresocsim_csrbank1_sel + connect \B \libresocsim_interface1_bank_bus_we + connect \Y $and$ls180.v:3207$780_Y end - attribute \src "ls180.v:5776.35-5776.79" - cell $and $and$ls180.v:5776$1099 + attribute \src "ls180.v:3207.38-3207.154" + cell $and $and$ls180.v:3207$782 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_err - connect \B $eq$ls180.v:5776$1098_Y - connect \Y $and$ls180.v:5776$1099_Y + connect \A $and$ls180.v:3207$780_Y + connect \B $eq$ls180.v:3207$781_Y + connect \Y $and$ls180.v:3207$782_Y end - attribute \src "ls180.v:5829.40-5829.81" - cell $and $and$ls180.v:5829$1107 + attribute \src "ls180.v:3208.39-3208.103" + cell $and $and$ls180.v:3208$784 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [0] - connect \Y $and$ls180.v:5829$1107_Y + connect \A \libresocsim_csrbank1_sel + connect \B $not$ls180.v:3208$783_Y + connect \Y $and$ls180.v:3208$784_Y end - attribute \src "ls180.v:5830.36-5830.77" - cell $and $and$ls180.v:5830$1108 + attribute \src "ls180.v:3208.38-3208.157" + cell $and $and$ls180.v:3208$786 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [1] - connect \Y $and$ls180.v:5830$1108_Y + connect \A $and$ls180.v:3208$784_Y + connect \B $eq$ls180.v:3208$785_Y + connect \Y $and$ls180.v:3208$786_Y end - attribute \src "ls180.v:5831.51-5831.92" - cell $and $and$ls180.v:5831$1109 + attribute \src "ls180.v:3210.41-3210.102" + cell $and $and$ls180.v:3210$787 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [2] - connect \Y $and$ls180.v:5831$1109_Y + connect \A \libresocsim_csrbank1_sel + connect \B \libresocsim_interface1_bank_bus_we + connect \Y $and$ls180.v:3210$787_Y end - attribute \src "ls180.v:5832.51-5832.92" - cell $and $and$ls180.v:5832$1110 + attribute \src "ls180.v:3210.40-3210.156" + cell $and $and$ls180.v:3210$789 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [3] - connect \Y $and$ls180.v:5832$1110_Y + connect \A $and$ls180.v:3210$787_Y + connect \B $eq$ls180.v:3210$788_Y + connect \Y $and$ls180.v:3210$789_Y end - attribute \src "ls180.v:5833.54-5833.95" - cell $and $and$ls180.v:5833$1111 + attribute \src "ls180.v:3211.41-3211.105" + cell $and $and$ls180.v:3211$791 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [4] - connect \Y $and$ls180.v:5833$1111_Y + connect \A \libresocsim_csrbank1_sel + connect \B $not$ls180.v:3211$790_Y + connect \Y $and$ls180.v:3211$791_Y end - attribute \src "ls180.v:5834.55-5834.96" - cell $and $and$ls180.v:5834$1112 + attribute \src "ls180.v:3211.40-3211.159" + cell $and $and$ls180.v:3211$793 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_cyc - connect \B \builder_slave_sel [5] - connect \Y $and$ls180.v:5834$1112_Y + connect \A $and$ls180.v:3211$791_Y + connect \B $eq$ls180.v:3211$792_Y + connect \Y $and$ls180.v:3211$793_Y end - attribute \src "ls180.v:5836.25-5836.64" - cell $and $and$ls180.v:5836$1118 + attribute \src "ls180.v:3218.40-3218.101" + cell $and $and$ls180.v:3218$795 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_stb - connect \B \builder_shared_cyc - connect \Y $and$ls180.v:5836$1118_Y + connect \A \libresocsim_csrbank2_sel + connect \B \libresocsim_interface2_bank_bus_we + connect \Y $and$ls180.v:3218$795_Y end - attribute \src "ls180.v:5836.24-5836.89" - cell $and $and$ls180.v:5836$1120 + attribute \src "ls180.v:3218.39-3218.155" + cell $and $and$ls180.v:3218$797 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5836$1118_Y - connect \B $not$ls180.v:5836$1119_Y - connect \Y $and$ls180.v:5836$1120_Y - end - attribute \src "ls180.v:5842.32-5842.93" - cell $and $and$ls180.v:5842$1127 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] } - connect \B \main_libresocsim_ram_bus_dat_r - connect \Y $and$ls180.v:5842$1127_Y - end - attribute \src "ls180.v:5842.98-5842.155" - cell $and $and$ls180.v:5842$1128 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] } - connect \B \main_ram_bus_ram_bus_dat_r - connect \Y $and$ls180.v:5842$1128_Y - end - attribute \src "ls180.v:5842.161-5842.233" - cell $and $and$ls180.v:5842$1130 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] } - connect \B \main_interface0_converted_interface_dat_r - connect \Y $and$ls180.v:5842$1130_Y - end - attribute \src "ls180.v:5842.239-5842.311" - cell $and $and$ls180.v:5842$1132 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] } - connect \B \main_interface1_converted_interface_dat_r - connect \Y $and$ls180.v:5842$1132_Y - end - attribute \src "ls180.v:5842.317-5842.392" - cell $and $and$ls180.v:5842$1134 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] } - connect \B \main_socbushandler_converted_interface_dat_r - connect \Y $and$ls180.v:5842$1134_Y + connect \A $and$ls180.v:3218$795_Y + connect \B $eq$ls180.v:3218$796_Y + connect \Y $and$ls180.v:3218$797_Y end - attribute \src "ls180.v:5842.398-5842.474" - cell $and $and$ls180.v:5842$1136 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A { 32'00000000000000000000000000000000 \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] \builder_slave_sel_r [5] } - connect \B \builder_libresocsim_converted_interface_dat_r - connect \Y $and$ls180.v:5842$1136_Y - end - attribute \src "ls180.v:5852.39-5852.92" - cell $and $and$ls180.v:5852$1140 + attribute \src "ls180.v:3219.40-3219.104" + cell $and $and$ls180.v:3219$799 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5852$1140_Y + connect \A \libresocsim_csrbank2_sel + connect \B $not$ls180.v:3219$798_Y + connect \Y $and$ls180.v:3219$799_Y end - attribute \src "ls180.v:5852.38-5852.142" - cell $and $and$ls180.v:5852$1142 + attribute \src "ls180.v:3219.39-3219.158" + cell $and $and$ls180.v:3219$801 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5852$1140_Y - connect \B $eq$ls180.v:5852$1141_Y - connect \Y $and$ls180.v:5852$1142_Y + connect \A $and$ls180.v:3219$799_Y + connect \B $eq$ls180.v:3219$800_Y + connect \Y $and$ls180.v:3219$801_Y end - attribute \src "ls180.v:5853.39-5853.95" - cell $and $and$ls180.v:5853$1144 + attribute \src "ls180.v:3221.39-3221.100" + cell $and $and$ls180.v:3221$802 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5853$1143_Y - connect \Y $and$ls180.v:5853$1144_Y + connect \A \libresocsim_csrbank2_sel + connect \B \libresocsim_interface2_bank_bus_we + connect \Y $and$ls180.v:3221$802_Y end - attribute \src "ls180.v:5853.38-5853.145" - cell $and $and$ls180.v:5853$1146 + attribute \src "ls180.v:3221.38-3221.154" + cell $and $and$ls180.v:3221$804 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5853$1144_Y - connect \B $eq$ls180.v:5853$1145_Y - connect \Y $and$ls180.v:5853$1146_Y + connect \A $and$ls180.v:3221$802_Y + connect \B $eq$ls180.v:3221$803_Y + connect \Y $and$ls180.v:3221$804_Y end - attribute \src "ls180.v:5855.41-5855.94" - cell $and $and$ls180.v:5855$1147 + attribute \src "ls180.v:3222.39-3222.103" + cell $and $and$ls180.v:3222$806 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5855$1147_Y + connect \A \libresocsim_csrbank2_sel + connect \B $not$ls180.v:3222$805_Y + connect \Y $and$ls180.v:3222$806_Y end - attribute \src "ls180.v:5855.40-5855.144" - cell $and $and$ls180.v:5855$1149 + attribute \src "ls180.v:3222.38-3222.157" + cell $and $and$ls180.v:3222$808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5855$1147_Y - connect \B $eq$ls180.v:5855$1148_Y - connect \Y $and$ls180.v:5855$1149_Y + connect \A $and$ls180.v:3222$806_Y + connect \B $eq$ls180.v:3222$807_Y + connect \Y $and$ls180.v:3222$808_Y end - attribute \src "ls180.v:5856.41-5856.97" - cell $and $and$ls180.v:5856$1151 + attribute \src "ls180.v:3224.41-3224.102" + cell $and $and$ls180.v:3224$809 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5856$1150_Y - connect \Y $and$ls180.v:5856$1151_Y + connect \A \libresocsim_csrbank2_sel + connect \B \libresocsim_interface2_bank_bus_we + connect \Y $and$ls180.v:3224$809_Y end - attribute \src "ls180.v:5856.40-5856.147" - cell $and $and$ls180.v:5856$1153 + attribute \src "ls180.v:3224.40-3224.156" + cell $and $and$ls180.v:3224$811 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5856$1151_Y - connect \B $eq$ls180.v:5856$1152_Y - connect \Y $and$ls180.v:5856$1153_Y + connect \A $and$ls180.v:3224$809_Y + connect \B $eq$ls180.v:3224$810_Y + connect \Y $and$ls180.v:3224$811_Y end - attribute \src "ls180.v:5858.41-5858.94" - cell $and $and$ls180.v:5858$1154 + attribute \src "ls180.v:3225.41-3225.105" + cell $and $and$ls180.v:3225$813 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5858$1154_Y + connect \A \libresocsim_csrbank2_sel + connect \B $not$ls180.v:3225$812_Y + connect \Y $and$ls180.v:3225$813_Y end - attribute \src "ls180.v:5858.40-5858.144" - cell $and $and$ls180.v:5858$1156 + attribute \src "ls180.v:3225.40-3225.159" + cell $and $and$ls180.v:3225$815 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5858$1154_Y - connect \B $eq$ls180.v:5858$1155_Y - connect \Y $and$ls180.v:5858$1156_Y + connect \A $and$ls180.v:3225$813_Y + connect \B $eq$ls180.v:3225$814_Y + connect \Y $and$ls180.v:3225$815_Y end - attribute \src "ls180.v:5859.41-5859.97" - cell $and $and$ls180.v:5859$1158 + attribute \src "ls180.v:3232.39-3232.100" + cell $and $and$ls180.v:3232$817 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5859$1157_Y - connect \Y $and$ls180.v:5859$1158_Y + connect \A \libresocsim_csrbank3_sel + connect \B \libresocsim_interface3_bank_bus_we + connect \Y $and$ls180.v:3232$817_Y end - attribute \src "ls180.v:5859.40-5859.147" - cell $and $and$ls180.v:5859$1160 + attribute \src "ls180.v:3232.38-3232.152" + cell $and $and$ls180.v:3232$819 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5859$1158_Y - connect \B $eq$ls180.v:5859$1159_Y - connect \Y $and$ls180.v:5859$1160_Y + connect \A $and$ls180.v:3232$817_Y + connect \B $eq$ls180.v:3232$818_Y + connect \Y $and$ls180.v:3232$819_Y end - attribute \src "ls180.v:5861.41-5861.94" - cell $and $and$ls180.v:5861$1161 + attribute \src "ls180.v:3233.39-3233.103" + cell $and $and$ls180.v:3233$821 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5861$1161_Y + connect \A \libresocsim_csrbank3_sel + connect \B $not$ls180.v:3233$820_Y + connect \Y $and$ls180.v:3233$821_Y end - attribute \src "ls180.v:5861.40-5861.144" - cell $and $and$ls180.v:5861$1163 + attribute \src "ls180.v:3233.38-3233.155" + cell $and $and$ls180.v:3233$823 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5861$1161_Y - connect \B $eq$ls180.v:5861$1162_Y - connect \Y $and$ls180.v:5861$1163_Y + connect \A $and$ls180.v:3233$821_Y + connect \B $eq$ls180.v:3233$822_Y + connect \Y $and$ls180.v:3233$823_Y end - attribute \src "ls180.v:5862.41-5862.97" - cell $and $and$ls180.v:5862$1165 + attribute \src "ls180.v:3235.38-3235.99" + cell $and $and$ls180.v:3235$824 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5862$1164_Y - connect \Y $and$ls180.v:5862$1165_Y + connect \A \libresocsim_csrbank3_sel + connect \B \libresocsim_interface3_bank_bus_we + connect \Y $and$ls180.v:3235$824_Y end - attribute \src "ls180.v:5862.40-5862.147" - cell $and $and$ls180.v:5862$1167 + attribute \src "ls180.v:3235.37-3235.151" + cell $and $and$ls180.v:3235$826 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5862$1165_Y - connect \B $eq$ls180.v:5862$1166_Y - connect \Y $and$ls180.v:5862$1167_Y + connect \A $and$ls180.v:3235$824_Y + connect \B $eq$ls180.v:3235$825_Y + connect \Y $and$ls180.v:3235$826_Y end - attribute \src "ls180.v:5864.41-5864.94" - cell $and $and$ls180.v:5864$1168 + attribute \src "ls180.v:3236.38-3236.102" + cell $and $and$ls180.v:3236$828 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5864$1168_Y + connect \A \libresocsim_csrbank3_sel + connect \B $not$ls180.v:3236$827_Y + connect \Y $and$ls180.v:3236$828_Y end - attribute \src "ls180.v:5864.40-5864.144" - cell $and $and$ls180.v:5864$1170 + attribute \src "ls180.v:3236.37-3236.154" + cell $and $and$ls180.v:3236$830 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5864$1168_Y - connect \B $eq$ls180.v:5864$1169_Y - connect \Y $and$ls180.v:5864$1170_Y + connect \A $and$ls180.v:3236$828_Y + connect \B $eq$ls180.v:3236$829_Y + connect \Y $and$ls180.v:3236$830_Y end - attribute \src "ls180.v:5865.41-5865.97" - cell $and $and$ls180.v:5865$1172 + attribute \src "ls180.v:3246.50-3246.111" + cell $and $and$ls180.v:3246$832 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5865$1171_Y - connect \Y $and$ls180.v:5865$1172_Y + connect \A \libresocsim_csrbank4_sel + connect \B \libresocsim_interface4_bank_bus_we + connect \Y $and$ls180.v:3246$832_Y end - attribute \src "ls180.v:5865.40-5865.147" - cell $and $and$ls180.v:5865$1174 + attribute \src "ls180.v:3246.49-3246.165" + cell $and $and$ls180.v:3246$834 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5865$1172_Y - connect \B $eq$ls180.v:5865$1173_Y - connect \Y $and$ls180.v:5865$1174_Y + connect \A $and$ls180.v:3246$832_Y + connect \B $eq$ls180.v:3246$833_Y + connect \Y $and$ls180.v:3246$834_Y end - attribute \src "ls180.v:5867.44-5867.97" - cell $and $and$ls180.v:5867$1175 + attribute \src "ls180.v:3247.50-3247.114" + cell $and $and$ls180.v:3247$836 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5867$1175_Y + connect \A \libresocsim_csrbank4_sel + connect \B $not$ls180.v:3247$835_Y + connect \Y $and$ls180.v:3247$836_Y end - attribute \src "ls180.v:5867.43-5867.147" - cell $and $and$ls180.v:5867$1177 + attribute \src "ls180.v:3247.49-3247.168" + cell $and $and$ls180.v:3247$838 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5867$1175_Y - connect \B $eq$ls180.v:5867$1176_Y - connect \Y $and$ls180.v:5867$1177_Y + connect \A $and$ls180.v:3247$836_Y + connect \B $eq$ls180.v:3247$837_Y + connect \Y $and$ls180.v:3247$838_Y end - attribute \src "ls180.v:5868.44-5868.100" - cell $and $and$ls180.v:5868$1179 + attribute \src "ls180.v:3249.54-3249.115" + cell $and $and$ls180.v:3249$839 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5868$1178_Y - connect \Y $and$ls180.v:5868$1179_Y + connect \A \libresocsim_csrbank4_sel + connect \B \libresocsim_interface4_bank_bus_we + connect \Y $and$ls180.v:3249$839_Y end - attribute \src "ls180.v:5868.43-5868.150" - cell $and $and$ls180.v:5868$1181 + attribute \src "ls180.v:3249.53-3249.169" + cell $and $and$ls180.v:3249$841 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5868$1179_Y - connect \B $eq$ls180.v:5868$1180_Y - connect \Y $and$ls180.v:5868$1181_Y + connect \A $and$ls180.v:3249$839_Y + connect \B $eq$ls180.v:3249$840_Y + connect \Y $and$ls180.v:3249$841_Y end - attribute \src "ls180.v:5870.44-5870.97" - cell $and $and$ls180.v:5870$1182 + attribute \src "ls180.v:3250.54-3250.118" + cell $and $and$ls180.v:3250$843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5870$1182_Y + connect \A \libresocsim_csrbank4_sel + connect \B $not$ls180.v:3250$842_Y + connect \Y $and$ls180.v:3250$843_Y end - attribute \src "ls180.v:5870.43-5870.147" - cell $and $and$ls180.v:5870$1184 + attribute \src "ls180.v:3250.53-3250.172" + cell $and $and$ls180.v:3250$845 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5870$1182_Y - connect \B $eq$ls180.v:5870$1183_Y - connect \Y $and$ls180.v:5870$1184_Y + connect \A $and$ls180.v:3250$843_Y + connect \B $eq$ls180.v:3250$844_Y + connect \Y $and$ls180.v:3250$845_Y end - attribute \src "ls180.v:5871.44-5871.100" - cell $and $and$ls180.v:5871$1186 + attribute \src "ls180.v:3252.35-3252.96" + cell $and $and$ls180.v:3252$846 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5871$1185_Y - connect \Y $and$ls180.v:5871$1186_Y + connect \A \libresocsim_csrbank4_sel + connect \B \libresocsim_interface4_bank_bus_we + connect \Y $and$ls180.v:3252$846_Y end - attribute \src "ls180.v:5871.43-5871.150" - cell $and $and$ls180.v:5871$1188 + attribute \src "ls180.v:3252.34-3252.150" + cell $and $and$ls180.v:3252$848 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5871$1186_Y - connect \B $eq$ls180.v:5871$1187_Y - connect \Y $and$ls180.v:5871$1188_Y + connect \A $and$ls180.v:3252$846_Y + connect \B $eq$ls180.v:3252$847_Y + connect \Y $and$ls180.v:3252$848_Y end - attribute \src "ls180.v:5873.44-5873.97" - cell $and $and$ls180.v:5873$1189 + attribute \src "ls180.v:3253.35-3253.99" + cell $and $and$ls180.v:3253$850 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5873$1189_Y + connect \A \libresocsim_csrbank4_sel + connect \B $not$ls180.v:3253$849_Y + connect \Y $and$ls180.v:3253$850_Y end - attribute \src "ls180.v:5873.43-5873.147" - cell $and $and$ls180.v:5873$1191 + attribute \src "ls180.v:3253.34-3253.153" + cell $and $and$ls180.v:3253$852 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5873$1189_Y - connect \B $eq$ls180.v:5873$1190_Y - connect \Y $and$ls180.v:5873$1191_Y + connect \A $and$ls180.v:3253$850_Y + connect \B $eq$ls180.v:3253$851_Y + connect \Y $and$ls180.v:3253$852_Y end - attribute \src "ls180.v:5874.44-5874.100" - cell $and $and$ls180.v:5874$1193 + attribute \src "ls180.v:3255.54-3255.115" + cell $and $and$ls180.v:3255$853 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5874$1192_Y - connect \Y $and$ls180.v:5874$1193_Y + connect \A \libresocsim_csrbank4_sel + connect \B \libresocsim_interface4_bank_bus_we + connect \Y $and$ls180.v:3255$853_Y end - attribute \src "ls180.v:5874.43-5874.150" - cell $and $and$ls180.v:5874$1195 + attribute \src "ls180.v:3255.53-3255.169" + cell $and $and$ls180.v:3255$855 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5874$1193_Y - connect \B $eq$ls180.v:5874$1194_Y - connect \Y $and$ls180.v:5874$1195_Y + connect \A $and$ls180.v:3255$853_Y + connect \B $eq$ls180.v:3255$854_Y + connect \Y $and$ls180.v:3255$855_Y end - attribute \src "ls180.v:5876.44-5876.97" - cell $and $and$ls180.v:5876$1196 + attribute \src "ls180.v:3256.54-3256.118" + cell $and $and$ls180.v:3256$857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B \builder_interface0_bank_bus_we - connect \Y $and$ls180.v:5876$1196_Y + connect \A \libresocsim_csrbank4_sel + connect \B $not$ls180.v:3256$856_Y + connect \Y $and$ls180.v:3256$857_Y end - attribute \src "ls180.v:5876.43-5876.147" - cell $and $and$ls180.v:5876$1198 + attribute \src "ls180.v:3256.53-3256.172" + cell $and $and$ls180.v:3256$859 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5876$1196_Y - connect \B $eq$ls180.v:5876$1197_Y - connect \Y $and$ls180.v:5876$1198_Y + connect \A $and$ls180.v:3256$857_Y + connect \B $eq$ls180.v:3256$858_Y + connect \Y $and$ls180.v:3256$859_Y end - attribute \src "ls180.v:5877.44-5877.100" - cell $and $and$ls180.v:5877$1200 + attribute \src "ls180.v:3258.54-3258.115" + cell $and $and$ls180.v:3258$860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank0_sel - connect \B $not$ls180.v:5877$1199_Y - connect \Y $and$ls180.v:5877$1200_Y + connect \A \libresocsim_csrbank4_sel + connect \B \libresocsim_interface4_bank_bus_we + connect \Y $and$ls180.v:3258$860_Y end - attribute \src "ls180.v:5877.43-5877.150" - cell $and $and$ls180.v:5877$1202 + attribute \src "ls180.v:3258.53-3258.169" + cell $and $and$ls180.v:3258$862 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5877$1200_Y - connect \B $eq$ls180.v:5877$1201_Y - connect \Y $and$ls180.v:5877$1202_Y + connect \A $and$ls180.v:3258$860_Y + connect \B $eq$ls180.v:3258$861_Y + connect \Y $and$ls180.v:3258$862_Y end - attribute \src "ls180.v:5890.36-5890.89" - cell $and $and$ls180.v:5890$1204 + attribute \src "ls180.v:3259.54-3259.118" + cell $and $and$ls180.v:3259$864 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5890$1204_Y + connect \A \libresocsim_csrbank4_sel + connect \B $not$ls180.v:3259$863_Y + connect \Y $and$ls180.v:3259$864_Y end - attribute \src "ls180.v:5890.35-5890.139" - cell $and $and$ls180.v:5890$1206 + attribute \src "ls180.v:3259.53-3259.172" + cell $and $and$ls180.v:3259$866 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5890$1204_Y - connect \B $eq$ls180.v:5890$1205_Y - connect \Y $and$ls180.v:5890$1206_Y + connect \A $and$ls180.v:3259$864_Y + connect \B $eq$ls180.v:3259$865_Y + connect \Y $and$ls180.v:3259$866_Y end - attribute \src "ls180.v:5891.36-5891.92" - cell $and $and$ls180.v:5891$1208 + attribute \src "ls180.v:3261.55-3261.116" + cell $and $and$ls180.v:3261$867 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5891$1207_Y - connect \Y $and$ls180.v:5891$1208_Y + connect \A \libresocsim_csrbank4_sel + connect \B \libresocsim_interface4_bank_bus_we + connect \Y $and$ls180.v:3261$867_Y end - attribute \src "ls180.v:5891.35-5891.142" - cell $and $and$ls180.v:5891$1210 + attribute \src "ls180.v:3261.54-3261.170" + cell $and $and$ls180.v:3261$869 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5891$1208_Y - connect \B $eq$ls180.v:5891$1209_Y - connect \Y $and$ls180.v:5891$1210_Y + connect \A $and$ls180.v:3261$867_Y + connect \B $eq$ls180.v:3261$868_Y + connect \Y $and$ls180.v:3261$869_Y end - attribute \src "ls180.v:5893.36-5893.89" - cell $and $and$ls180.v:5893$1211 + attribute \src "ls180.v:3262.55-3262.119" + cell $and $and$ls180.v:3262$871 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5893$1211_Y + connect \A \libresocsim_csrbank4_sel + connect \B $not$ls180.v:3262$870_Y + connect \Y $and$ls180.v:3262$871_Y end - attribute \src "ls180.v:5893.35-5893.139" - cell $and $and$ls180.v:5893$1213 + attribute \src "ls180.v:3262.54-3262.173" + cell $and $and$ls180.v:3262$873 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5893$1211_Y - connect \B $eq$ls180.v:5893$1212_Y - connect \Y $and$ls180.v:5893$1213_Y + connect \A $and$ls180.v:3262$871_Y + connect \B $eq$ls180.v:3262$872_Y + connect \Y $and$ls180.v:3262$873_Y end - attribute \src "ls180.v:5894.36-5894.92" - cell $and $and$ls180.v:5894$1215 + attribute \src "ls180.v:3264.53-3264.114" + cell $and $and$ls180.v:3264$874 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5894$1214_Y - connect \Y $and$ls180.v:5894$1215_Y + connect \A \libresocsim_csrbank4_sel + connect \B \libresocsim_interface4_bank_bus_we + connect \Y $and$ls180.v:3264$874_Y end - attribute \src "ls180.v:5894.35-5894.142" - cell $and $and$ls180.v:5894$1217 + attribute \src "ls180.v:3264.52-3264.168" + cell $and $and$ls180.v:3264$876 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5894$1215_Y - connect \B $eq$ls180.v:5894$1216_Y - connect \Y $and$ls180.v:5894$1217_Y + connect \A $and$ls180.v:3264$874_Y + connect \B $eq$ls180.v:3264$875_Y + connect \Y $and$ls180.v:3264$876_Y end - attribute \src "ls180.v:5896.36-5896.89" - cell $and $and$ls180.v:5896$1218 + attribute \src "ls180.v:3265.53-3265.117" + cell $and $and$ls180.v:3265$878 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5896$1218_Y + connect \A \libresocsim_csrbank4_sel + connect \B $not$ls180.v:3265$877_Y + connect \Y $and$ls180.v:3265$878_Y end - attribute \src "ls180.v:5896.35-5896.139" - cell $and $and$ls180.v:5896$1220 + attribute \src "ls180.v:3265.52-3265.171" + cell $and $and$ls180.v:3265$880 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5896$1218_Y - connect \B $eq$ls180.v:5896$1219_Y - connect \Y $and$ls180.v:5896$1220_Y + connect \A $and$ls180.v:3265$878_Y + connect \B $eq$ls180.v:3265$879_Y + connect \Y $and$ls180.v:3265$880_Y end - attribute \src "ls180.v:5897.36-5897.92" - cell $and $and$ls180.v:5897$1222 + attribute \src "ls180.v:3267.53-3267.114" + cell $and $and$ls180.v:3267$881 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5897$1221_Y - connect \Y $and$ls180.v:5897$1222_Y + connect \A \libresocsim_csrbank4_sel + connect \B \libresocsim_interface4_bank_bus_we + connect \Y $and$ls180.v:3267$881_Y end - attribute \src "ls180.v:5897.35-5897.142" - cell $and $and$ls180.v:5897$1224 + attribute \src "ls180.v:3267.52-3267.168" + cell $and $and$ls180.v:3267$883 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5897$1222_Y - connect \B $eq$ls180.v:5897$1223_Y - connect \Y $and$ls180.v:5897$1224_Y + connect \A $and$ls180.v:3267$881_Y + connect \B $eq$ls180.v:3267$882_Y + connect \Y $and$ls180.v:3267$883_Y end - attribute \src "ls180.v:5899.36-5899.89" - cell $and $and$ls180.v:5899$1225 + attribute \src "ls180.v:3268.53-3268.117" + cell $and $and$ls180.v:3268$885 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5899$1225_Y + connect \A \libresocsim_csrbank4_sel + connect \B $not$ls180.v:3268$884_Y + connect \Y $and$ls180.v:3268$885_Y end - attribute \src "ls180.v:5899.35-5899.139" - cell $and $and$ls180.v:5899$1227 + attribute \src "ls180.v:3268.52-3268.171" + cell $and $and$ls180.v:3268$887 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5899$1225_Y - connect \B $eq$ls180.v:5899$1226_Y - connect \Y $and$ls180.v:5899$1227_Y + connect \A $and$ls180.v:3268$885_Y + connect \B $eq$ls180.v:3268$886_Y + connect \Y $and$ls180.v:3268$887_Y end - attribute \src "ls180.v:5900.36-5900.92" - cell $and $and$ls180.v:5900$1229 + attribute \src "ls180.v:3270.53-3270.114" + cell $and $and$ls180.v:3270$888 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5900$1228_Y - connect \Y $and$ls180.v:5900$1229_Y + connect \A \libresocsim_csrbank4_sel + connect \B \libresocsim_interface4_bank_bus_we + connect \Y $and$ls180.v:3270$888_Y end - attribute \src "ls180.v:5900.35-5900.142" - cell $and $and$ls180.v:5900$1231 + attribute \src "ls180.v:3270.52-3270.168" + cell $and $and$ls180.v:3270$890 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5900$1229_Y - connect \B $eq$ls180.v:5900$1230_Y - connect \Y $and$ls180.v:5900$1231_Y + connect \A $and$ls180.v:3270$888_Y + connect \B $eq$ls180.v:3270$889_Y + connect \Y $and$ls180.v:3270$890_Y end - attribute \src "ls180.v:5902.37-5902.90" - cell $and $and$ls180.v:5902$1232 + attribute \src "ls180.v:3271.53-3271.117" + cell $and $and$ls180.v:3271$892 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5902$1232_Y + connect \A \libresocsim_csrbank4_sel + connect \B $not$ls180.v:3271$891_Y + connect \Y $and$ls180.v:3271$892_Y end - attribute \src "ls180.v:5902.36-5902.140" - cell $and $and$ls180.v:5902$1234 + attribute \src "ls180.v:3271.52-3271.171" + cell $and $and$ls180.v:3271$894 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5902$1232_Y - connect \B $eq$ls180.v:5902$1233_Y - connect \Y $and$ls180.v:5902$1234_Y + connect \A $and$ls180.v:3271$892_Y + connect \B $eq$ls180.v:3271$893_Y + connect \Y $and$ls180.v:3271$894_Y end - attribute \src "ls180.v:5903.37-5903.93" - cell $and $and$ls180.v:5903$1236 + attribute \src "ls180.v:3273.53-3273.114" + cell $and $and$ls180.v:3273$895 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5903$1235_Y - connect \Y $and$ls180.v:5903$1236_Y + connect \A \libresocsim_csrbank4_sel + connect \B \libresocsim_interface4_bank_bus_we + connect \Y $and$ls180.v:3273$895_Y end - attribute \src "ls180.v:5903.36-5903.143" - cell $and $and$ls180.v:5903$1238 + attribute \src "ls180.v:3273.52-3273.168" + cell $and $and$ls180.v:3273$897 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5903$1236_Y - connect \B $eq$ls180.v:5903$1237_Y - connect \Y $and$ls180.v:5903$1238_Y + connect \A $and$ls180.v:3273$895_Y + connect \B $eq$ls180.v:3273$896_Y + connect \Y $and$ls180.v:3273$897_Y end - attribute \src "ls180.v:5905.37-5905.90" - cell $and $and$ls180.v:5905$1239 + attribute \src "ls180.v:3274.53-3274.117" + cell $and $and$ls180.v:3274$899 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B \builder_interface1_bank_bus_we - connect \Y $and$ls180.v:5905$1239_Y + connect \A \libresocsim_csrbank4_sel + connect \B $not$ls180.v:3274$898_Y + connect \Y $and$ls180.v:3274$899_Y end - attribute \src "ls180.v:5905.36-5905.140" - cell $and $and$ls180.v:5905$1241 + attribute \src "ls180.v:3274.52-3274.171" + cell $and $and$ls180.v:3274$901 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5905$1239_Y - connect \B $eq$ls180.v:5905$1240_Y - connect \Y $and$ls180.v:5905$1241_Y + connect \A $and$ls180.v:3274$899_Y + connect \B $eq$ls180.v:3274$900_Y + connect \Y $and$ls180.v:3274$901_Y end - attribute \src "ls180.v:5906.37-5906.93" - cell $and $and$ls180.v:5906$1243 + attribute \src "ls180.v:3291.42-3291.103" + cell $and $and$ls180.v:3291$903 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank1_sel - connect \B $not$ls180.v:5906$1242_Y - connect \Y $and$ls180.v:5906$1243_Y + connect \A \libresocsim_csrbank5_sel + connect \B \libresocsim_interface5_bank_bus_we + connect \Y $and$ls180.v:3291$903_Y end - attribute \src "ls180.v:5906.36-5906.143" - cell $and $and$ls180.v:5906$1245 + attribute \src "ls180.v:3291.41-3291.157" + cell $and $and$ls180.v:3291$905 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5906$1243_Y - connect \B $eq$ls180.v:5906$1244_Y - connect \Y $and$ls180.v:5906$1245_Y + connect \A $and$ls180.v:3291$903_Y + connect \B $eq$ls180.v:3291$904_Y + connect \Y $and$ls180.v:3291$905_Y end - attribute \src "ls180.v:5916.35-5916.88" - cell $and $and$ls180.v:5916$1247 + attribute \src "ls180.v:3292.42-3292.106" + cell $and $and$ls180.v:3292$907 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank2_sel - connect \B \builder_interface2_bank_bus_we - connect \Y $and$ls180.v:5916$1247_Y + connect \A \libresocsim_csrbank5_sel + connect \B $not$ls180.v:3292$906_Y + connect \Y $and$ls180.v:3292$907_Y end - attribute \src "ls180.v:5916.34-5916.136" - cell $and $and$ls180.v:5916$1249 + attribute \src "ls180.v:3292.41-3292.160" + cell $and $and$ls180.v:3292$909 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5916$1247_Y - connect \B $eq$ls180.v:5916$1248_Y - connect \Y $and$ls180.v:5916$1249_Y + connect \A $and$ls180.v:3292$907_Y + connect \B $eq$ls180.v:3292$908_Y + connect \Y $and$ls180.v:3292$909_Y end - attribute \src "ls180.v:5917.35-5917.91" - cell $and $and$ls180.v:5917$1251 + attribute \src "ls180.v:3294.42-3294.103" + cell $and $and$ls180.v:3294$910 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank2_sel - connect \B $not$ls180.v:5917$1250_Y - connect \Y $and$ls180.v:5917$1251_Y + connect \A \libresocsim_csrbank5_sel + connect \B \libresocsim_interface5_bank_bus_we + connect \Y $and$ls180.v:3294$910_Y end - attribute \src "ls180.v:5917.34-5917.139" - cell $and $and$ls180.v:5917$1253 + attribute \src "ls180.v:3294.41-3294.157" + cell $and $and$ls180.v:3294$912 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5917$1251_Y - connect \B $eq$ls180.v:5917$1252_Y - connect \Y $and$ls180.v:5917$1253_Y + connect \A $and$ls180.v:3294$910_Y + connect \B $eq$ls180.v:3294$911_Y + connect \Y $and$ls180.v:3294$912_Y end - attribute \src "ls180.v:5919.34-5919.87" - cell $and $and$ls180.v:5919$1254 + attribute \src "ls180.v:3295.42-3295.106" + cell $and $and$ls180.v:3295$914 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank2_sel - connect \B \builder_interface2_bank_bus_we - connect \Y $and$ls180.v:5919$1254_Y + connect \A \libresocsim_csrbank5_sel + connect \B $not$ls180.v:3295$913_Y + connect \Y $and$ls180.v:3295$914_Y end - attribute \src "ls180.v:5919.33-5919.135" - cell $and $and$ls180.v:5919$1256 + attribute \src "ls180.v:3295.41-3295.160" + cell $and $and$ls180.v:3295$916 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5919$1254_Y - connect \B $eq$ls180.v:5919$1255_Y - connect \Y $and$ls180.v:5919$1256_Y + connect \A $and$ls180.v:3295$914_Y + connect \B $eq$ls180.v:3295$915_Y + connect \Y $and$ls180.v:3295$916_Y end - attribute \src "ls180.v:5920.34-5920.90" - cell $and $and$ls180.v:5920$1258 + attribute \src "ls180.v:3297.42-3297.103" + cell $and $and$ls180.v:3297$917 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank2_sel - connect \B $not$ls180.v:5920$1257_Y - connect \Y $and$ls180.v:5920$1258_Y + connect \A \libresocsim_csrbank5_sel + connect \B \libresocsim_interface5_bank_bus_we + connect \Y $and$ls180.v:3297$917_Y end - attribute \src "ls180.v:5920.33-5920.138" - cell $and $and$ls180.v:5920$1260 + attribute \src "ls180.v:3297.41-3297.157" + cell $and $and$ls180.v:3297$919 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5920$1258_Y - connect \B $eq$ls180.v:5920$1259_Y - connect \Y $and$ls180.v:5920$1260_Y + connect \A $and$ls180.v:3297$917_Y + connect \B $eq$ls180.v:3297$918_Y + connect \Y $and$ls180.v:3297$919_Y end - attribute \src "ls180.v:5930.40-5930.93" - cell $and $and$ls180.v:5930$1262 + attribute \src "ls180.v:3298.42-3298.106" + cell $and $and$ls180.v:3298$921 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5930$1262_Y + connect \A \libresocsim_csrbank5_sel + connect \B $not$ls180.v:3298$920_Y + connect \Y $and$ls180.v:3298$921_Y end - attribute \src "ls180.v:5930.39-5930.143" - cell $and $and$ls180.v:5930$1264 + attribute \src "ls180.v:3298.41-3298.160" + cell $and $and$ls180.v:3298$923 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5930$1262_Y - connect \B $eq$ls180.v:5930$1263_Y - connect \Y $and$ls180.v:5930$1264_Y + connect \A $and$ls180.v:3298$921_Y + connect \B $eq$ls180.v:3298$922_Y + connect \Y $and$ls180.v:3298$923_Y end - attribute \src "ls180.v:5931.40-5931.96" - cell $and $and$ls180.v:5931$1266 + attribute \src "ls180.v:3300.42-3300.103" + cell $and $and$ls180.v:3300$924 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5931$1265_Y - connect \Y $and$ls180.v:5931$1266_Y + connect \A \libresocsim_csrbank5_sel + connect \B \libresocsim_interface5_bank_bus_we + connect \Y $and$ls180.v:3300$924_Y end - attribute \src "ls180.v:5931.39-5931.146" - cell $and $and$ls180.v:5931$1268 + attribute \src "ls180.v:3300.41-3300.157" + cell $and $and$ls180.v:3300$926 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5931$1266_Y - connect \B $eq$ls180.v:5931$1267_Y - connect \Y $and$ls180.v:5931$1268_Y + connect \A $and$ls180.v:3300$924_Y + connect \B $eq$ls180.v:3300$925_Y + connect \Y $and$ls180.v:3300$926_Y end - attribute \src "ls180.v:5933.39-5933.92" - cell $and $and$ls180.v:5933$1269 + attribute \src "ls180.v:3301.42-3301.106" + cell $and $and$ls180.v:3301$928 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5933$1269_Y + connect \A \libresocsim_csrbank5_sel + connect \B $not$ls180.v:3301$927_Y + connect \Y $and$ls180.v:3301$928_Y end - attribute \src "ls180.v:5933.38-5933.142" - cell $and $and$ls180.v:5933$1271 + attribute \src "ls180.v:3301.41-3301.160" + cell $and $and$ls180.v:3301$930 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5933$1269_Y - connect \B $eq$ls180.v:5933$1270_Y - connect \Y $and$ls180.v:5933$1271_Y + connect \A $and$ls180.v:3301$928_Y + connect \B $eq$ls180.v:3301$929_Y + connect \Y $and$ls180.v:3301$930_Y end - attribute \src "ls180.v:5934.39-5934.95" - cell $and $and$ls180.v:5934$1273 + attribute \src "ls180.v:3303.44-3303.105" + cell $and $and$ls180.v:3303$931 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5934$1272_Y - connect \Y $and$ls180.v:5934$1273_Y + connect \A \libresocsim_csrbank5_sel + connect \B \libresocsim_interface5_bank_bus_we + connect \Y $and$ls180.v:3303$931_Y end - attribute \src "ls180.v:5934.38-5934.145" - cell $and $and$ls180.v:5934$1275 + attribute \src "ls180.v:3303.43-3303.159" + cell $and $and$ls180.v:3303$933 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5934$1273_Y - connect \B $eq$ls180.v:5934$1274_Y - connect \Y $and$ls180.v:5934$1275_Y + connect \A $and$ls180.v:3303$931_Y + connect \B $eq$ls180.v:3303$932_Y + connect \Y $and$ls180.v:3303$933_Y end - attribute \src "ls180.v:5936.39-5936.92" - cell $and $and$ls180.v:5936$1276 + attribute \src "ls180.v:3304.44-3304.108" + cell $and $and$ls180.v:3304$935 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5936$1276_Y + connect \A \libresocsim_csrbank5_sel + connect \B $not$ls180.v:3304$934_Y + connect \Y $and$ls180.v:3304$935_Y end - attribute \src "ls180.v:5936.38-5936.142" - cell $and $and$ls180.v:5936$1278 + attribute \src "ls180.v:3304.43-3304.162" + cell $and $and$ls180.v:3304$937 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5936$1276_Y - connect \B $eq$ls180.v:5936$1277_Y - connect \Y $and$ls180.v:5936$1278_Y + connect \A $and$ls180.v:3304$935_Y + connect \B $eq$ls180.v:3304$936_Y + connect \Y $and$ls180.v:3304$937_Y end - attribute \src "ls180.v:5937.39-5937.95" - cell $and $and$ls180.v:5937$1280 + attribute \src "ls180.v:3306.44-3306.105" + cell $and $and$ls180.v:3306$938 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5937$1279_Y - connect \Y $and$ls180.v:5937$1280_Y + connect \A \libresocsim_csrbank5_sel + connect \B \libresocsim_interface5_bank_bus_we + connect \Y $and$ls180.v:3306$938_Y end - attribute \src "ls180.v:5937.38-5937.145" - cell $and $and$ls180.v:5937$1282 + attribute \src "ls180.v:3306.43-3306.159" + cell $and $and$ls180.v:3306$940 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5937$1280_Y - connect \B $eq$ls180.v:5937$1281_Y - connect \Y $and$ls180.v:5937$1282_Y + connect \A $and$ls180.v:3306$938_Y + connect \B $eq$ls180.v:3306$939_Y + connect \Y $and$ls180.v:3306$940_Y end - attribute \src "ls180.v:5939.39-5939.92" - cell $and $and$ls180.v:5939$1283 + attribute \src "ls180.v:3307.44-3307.108" + cell $and $and$ls180.v:3307$942 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5939$1283_Y + connect \A \libresocsim_csrbank5_sel + connect \B $not$ls180.v:3307$941_Y + connect \Y $and$ls180.v:3307$942_Y end - attribute \src "ls180.v:5939.38-5939.142" - cell $and $and$ls180.v:5939$1285 + attribute \src "ls180.v:3307.43-3307.162" + cell $and $and$ls180.v:3307$944 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5939$1283_Y - connect \B $eq$ls180.v:5939$1284_Y - connect \Y $and$ls180.v:5939$1285_Y + connect \A $and$ls180.v:3307$942_Y + connect \B $eq$ls180.v:3307$943_Y + connect \Y $and$ls180.v:3307$944_Y end - attribute \src "ls180.v:5940.39-5940.95" - cell $and $and$ls180.v:5940$1287 + attribute \src "ls180.v:3309.44-3309.105" + cell $and $and$ls180.v:3309$945 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5940$1286_Y - connect \Y $and$ls180.v:5940$1287_Y + connect \A \libresocsim_csrbank5_sel + connect \B \libresocsim_interface5_bank_bus_we + connect \Y $and$ls180.v:3309$945_Y end - attribute \src "ls180.v:5940.38-5940.145" - cell $and $and$ls180.v:5940$1289 + attribute \src "ls180.v:3309.43-3309.159" + cell $and $and$ls180.v:3309$947 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5940$1287_Y - connect \B $eq$ls180.v:5940$1288_Y - connect \Y $and$ls180.v:5940$1289_Y + connect \A $and$ls180.v:3309$945_Y + connect \B $eq$ls180.v:3309$946_Y + connect \Y $and$ls180.v:3309$947_Y end - attribute \src "ls180.v:5942.39-5942.92" - cell $and $and$ls180.v:5942$1290 + attribute \src "ls180.v:3310.44-3310.108" + cell $and $and$ls180.v:3310$949 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5942$1290_Y + connect \A \libresocsim_csrbank5_sel + connect \B $not$ls180.v:3310$948_Y + connect \Y $and$ls180.v:3310$949_Y end - attribute \src "ls180.v:5942.38-5942.142" - cell $and $and$ls180.v:5942$1292 + attribute \src "ls180.v:3310.43-3310.162" + cell $and $and$ls180.v:3310$951 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5942$1290_Y - connect \B $eq$ls180.v:5942$1291_Y - connect \Y $and$ls180.v:5942$1292_Y + connect \A $and$ls180.v:3310$949_Y + connect \B $eq$ls180.v:3310$950_Y + connect \Y $and$ls180.v:3310$951_Y end - attribute \src "ls180.v:5943.39-5943.95" - cell $and $and$ls180.v:5943$1294 + attribute \src "ls180.v:3312.44-3312.105" + cell $and $and$ls180.v:3312$952 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5943$1293_Y - connect \Y $and$ls180.v:5943$1294_Y + connect \A \libresocsim_csrbank5_sel + connect \B \libresocsim_interface5_bank_bus_we + connect \Y $and$ls180.v:3312$952_Y end - attribute \src "ls180.v:5943.38-5943.145" - cell $and $and$ls180.v:5943$1296 + attribute \src "ls180.v:3312.43-3312.159" + cell $and $and$ls180.v:3312$954 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5943$1294_Y - connect \B $eq$ls180.v:5943$1295_Y - connect \Y $and$ls180.v:5943$1296_Y + connect \A $and$ls180.v:3312$952_Y + connect \B $eq$ls180.v:3312$953_Y + connect \Y $and$ls180.v:3312$954_Y end - attribute \src "ls180.v:5945.40-5945.93" - cell $and $and$ls180.v:5945$1297 + attribute \src "ls180.v:3313.44-3313.108" + cell $and $and$ls180.v:3313$956 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5945$1297_Y + connect \A \libresocsim_csrbank5_sel + connect \B $not$ls180.v:3313$955_Y + connect \Y $and$ls180.v:3313$956_Y end - attribute \src "ls180.v:5945.39-5945.143" - cell $and $and$ls180.v:5945$1299 + attribute \src "ls180.v:3313.43-3313.162" + cell $and $and$ls180.v:3313$958 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5945$1297_Y - connect \B $eq$ls180.v:5945$1298_Y - connect \Y $and$ls180.v:5945$1299_Y + connect \A $and$ls180.v:3313$956_Y + connect \B $eq$ls180.v:3313$957_Y + connect \Y $and$ls180.v:3313$958_Y end - attribute \src "ls180.v:5946.40-5946.96" - cell $and $and$ls180.v:5946$1301 + attribute \src "ls180.v:3315.40-3315.101" + cell $and $and$ls180.v:3315$959 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5946$1300_Y - connect \Y $and$ls180.v:5946$1301_Y + connect \A \libresocsim_csrbank5_sel + connect \B \libresocsim_interface5_bank_bus_we + connect \Y $and$ls180.v:3315$959_Y end - attribute \src "ls180.v:5946.39-5946.146" - cell $and $and$ls180.v:5946$1303 + attribute \src "ls180.v:3315.39-3315.155" + cell $and $and$ls180.v:3315$961 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5946$1301_Y - connect \B $eq$ls180.v:5946$1302_Y - connect \Y $and$ls180.v:5946$1303_Y + connect \A $and$ls180.v:3315$959_Y + connect \B $eq$ls180.v:3315$960_Y + connect \Y $and$ls180.v:3315$961_Y end - attribute \src "ls180.v:5948.40-5948.93" - cell $and $and$ls180.v:5948$1304 + attribute \src "ls180.v:3316.40-3316.104" + cell $and $and$ls180.v:3316$963 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5948$1304_Y + connect \A \libresocsim_csrbank5_sel + connect \B $not$ls180.v:3316$962_Y + connect \Y $and$ls180.v:3316$963_Y end - attribute \src "ls180.v:5948.39-5948.143" - cell $and $and$ls180.v:5948$1306 + attribute \src "ls180.v:3316.39-3316.158" + cell $and $and$ls180.v:3316$965 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5948$1304_Y - connect \B $eq$ls180.v:5948$1305_Y - connect \Y $and$ls180.v:5948$1306_Y + connect \A $and$ls180.v:3316$963_Y + connect \B $eq$ls180.v:3316$964_Y + connect \Y $and$ls180.v:3316$965_Y end - attribute \src "ls180.v:5949.40-5949.96" - cell $and $and$ls180.v:5949$1308 + attribute \src "ls180.v:3318.50-3318.111" + cell $and $and$ls180.v:3318$966 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5949$1307_Y - connect \Y $and$ls180.v:5949$1308_Y + connect \A \libresocsim_csrbank5_sel + connect \B \libresocsim_interface5_bank_bus_we + connect \Y $and$ls180.v:3318$966_Y end - attribute \src "ls180.v:5949.39-5949.146" - cell $and $and$ls180.v:5949$1310 + attribute \src "ls180.v:3318.49-3318.165" + cell $and $and$ls180.v:3318$968 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5949$1308_Y - connect \B $eq$ls180.v:5949$1309_Y - connect \Y $and$ls180.v:5949$1310_Y + connect \A $and$ls180.v:3318$966_Y + connect \B $eq$ls180.v:3318$967_Y + connect \Y $and$ls180.v:3318$968_Y end - attribute \src "ls180.v:5951.40-5951.93" - cell $and $and$ls180.v:5951$1311 + attribute \src "ls180.v:3319.50-3319.114" + cell $and $and$ls180.v:3319$970 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5951$1311_Y + connect \A \libresocsim_csrbank5_sel + connect \B $not$ls180.v:3319$969_Y + connect \Y $and$ls180.v:3319$970_Y end - attribute \src "ls180.v:5951.39-5951.143" - cell $and $and$ls180.v:5951$1313 + attribute \src "ls180.v:3319.49-3319.168" + cell $and $and$ls180.v:3319$972 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5951$1311_Y - connect \B $eq$ls180.v:5951$1312_Y - connect \Y $and$ls180.v:5951$1313_Y + connect \A $and$ls180.v:3319$970_Y + connect \B $eq$ls180.v:3319$971_Y + connect \Y $and$ls180.v:3319$972_Y end - attribute \src "ls180.v:5952.40-5952.96" - cell $and $and$ls180.v:5952$1315 + attribute \src "ls180.v:3321.43-3321.104" + cell $and $and$ls180.v:3321$973 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5952$1314_Y - connect \Y $and$ls180.v:5952$1315_Y + connect \A \libresocsim_csrbank5_sel + connect \B \libresocsim_interface5_bank_bus_we + connect \Y $and$ls180.v:3321$973_Y end - attribute \src "ls180.v:5952.39-5952.146" - cell $and $and$ls180.v:5952$1317 + attribute \src "ls180.v:3321.42-3321.159" + cell $and $and$ls180.v:3321$975 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5952$1315_Y - connect \B $eq$ls180.v:5952$1316_Y - connect \Y $and$ls180.v:5952$1317_Y + connect \A $and$ls180.v:3321$973_Y + connect \B $eq$ls180.v:3321$974_Y + connect \Y $and$ls180.v:3321$975_Y end - attribute \src "ls180.v:5954.40-5954.93" - cell $and $and$ls180.v:5954$1318 + attribute \src "ls180.v:3322.43-3322.107" + cell $and $and$ls180.v:3322$977 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B \builder_interface3_bank_bus_we - connect \Y $and$ls180.v:5954$1318_Y + connect \A \libresocsim_csrbank5_sel + connect \B $not$ls180.v:3322$976_Y + connect \Y $and$ls180.v:3322$977_Y end - attribute \src "ls180.v:5954.39-5954.143" - cell $and $and$ls180.v:5954$1320 + attribute \src "ls180.v:3322.42-3322.162" + cell $and $and$ls180.v:3322$979 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5954$1318_Y - connect \B $eq$ls180.v:5954$1319_Y - connect \Y $and$ls180.v:5954$1320_Y + connect \A $and$ls180.v:3322$977_Y + connect \B $eq$ls180.v:3322$978_Y + connect \Y $and$ls180.v:3322$979_Y end - attribute \src "ls180.v:5955.40-5955.96" - cell $and $and$ls180.v:5955$1322 + attribute \src "ls180.v:3324.43-3324.104" + cell $and $and$ls180.v:3324$980 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank3_sel - connect \B $not$ls180.v:5955$1321_Y - connect \Y $and$ls180.v:5955$1322_Y + connect \A \libresocsim_csrbank5_sel + connect \B \libresocsim_interface5_bank_bus_we + connect \Y $and$ls180.v:3324$980_Y end - attribute \src "ls180.v:5955.39-5955.146" - cell $and $and$ls180.v:5955$1324 + attribute \src "ls180.v:3324.42-3324.159" + cell $and $and$ls180.v:3324$982 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5955$1322_Y - connect \B $eq$ls180.v:5955$1323_Y - connect \Y $and$ls180.v:5955$1324_Y + connect \A $and$ls180.v:3324$980_Y + connect \B $eq$ls180.v:3324$981_Y + connect \Y $and$ls180.v:3324$982_Y end - attribute \src "ls180.v:5967.40-5967.93" - cell $and $and$ls180.v:5967$1326 + attribute \src "ls180.v:3325.43-3325.107" + cell $and $and$ls180.v:3325$984 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5967$1326_Y + connect \A \libresocsim_csrbank5_sel + connect \B $not$ls180.v:3325$983_Y + connect \Y $and$ls180.v:3325$984_Y end - attribute \src "ls180.v:5967.39-5967.143" - cell $and $and$ls180.v:5967$1328 + attribute \src "ls180.v:3325.42-3325.162" + cell $and $and$ls180.v:3325$986 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5967$1326_Y - connect \B $eq$ls180.v:5967$1327_Y - connect \Y $and$ls180.v:5967$1328_Y + connect \A $and$ls180.v:3325$984_Y + connect \B $eq$ls180.v:3325$985_Y + connect \Y $and$ls180.v:3325$986_Y end - attribute \src "ls180.v:5968.40-5968.96" - cell $and $and$ls180.v:5968$1330 + attribute \src "ls180.v:3327.43-3327.104" + cell $and $and$ls180.v:3327$987 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5968$1329_Y - connect \Y $and$ls180.v:5968$1330_Y + connect \A \libresocsim_csrbank5_sel + connect \B \libresocsim_interface5_bank_bus_we + connect \Y $and$ls180.v:3327$987_Y end - attribute \src "ls180.v:5968.39-5968.146" - cell $and $and$ls180.v:5968$1332 + attribute \src "ls180.v:3327.42-3327.159" + cell $and $and$ls180.v:3327$989 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5968$1330_Y - connect \B $eq$ls180.v:5968$1331_Y - connect \Y $and$ls180.v:5968$1332_Y + connect \A $and$ls180.v:3327$987_Y + connect \B $eq$ls180.v:3327$988_Y + connect \Y $and$ls180.v:3327$989_Y end - attribute \src "ls180.v:5970.39-5970.92" - cell $and $and$ls180.v:5970$1333 + attribute \src "ls180.v:3328.43-3328.107" + cell $and $and$ls180.v:3328$991 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5970$1333_Y + connect \A \libresocsim_csrbank5_sel + connect \B $not$ls180.v:3328$990_Y + connect \Y $and$ls180.v:3328$991_Y end - attribute \src "ls180.v:5970.38-5970.142" - cell $and $and$ls180.v:5970$1335 + attribute \src "ls180.v:3328.42-3328.162" + cell $and $and$ls180.v:3328$993 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5970$1333_Y - connect \B $eq$ls180.v:5970$1334_Y - connect \Y $and$ls180.v:5970$1335_Y + connect \A $and$ls180.v:3328$991_Y + connect \B $eq$ls180.v:3328$992_Y + connect \Y $and$ls180.v:3328$993_Y end - attribute \src "ls180.v:5971.39-5971.95" - cell $and $and$ls180.v:5971$1337 + attribute \src "ls180.v:3330.43-3330.104" + cell $and $and$ls180.v:3330$994 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5971$1336_Y - connect \Y $and$ls180.v:5971$1337_Y + connect \A \libresocsim_csrbank5_sel + connect \B \libresocsim_interface5_bank_bus_we + connect \Y $and$ls180.v:3330$994_Y end - attribute \src "ls180.v:5971.38-5971.145" - cell $and $and$ls180.v:5971$1339 + attribute \src "ls180.v:3330.42-3330.159" + cell $and $and$ls180.v:3330$996 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5971$1337_Y - connect \B $eq$ls180.v:5971$1338_Y - connect \Y $and$ls180.v:5971$1339_Y + connect \A $and$ls180.v:3330$994_Y + connect \B $eq$ls180.v:3330$995_Y + connect \Y $and$ls180.v:3330$996_Y end - attribute \src "ls180.v:5973.39-5973.92" - cell $and $and$ls180.v:5973$1340 + attribute \src "ls180.v:3331.42-3331.162" + cell $and $and$ls180.v:3331$1000 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5973$1340_Y + connect \A $and$ls180.v:3331$998_Y + connect \B $eq$ls180.v:3331$999_Y + connect \Y $and$ls180.v:3331$1000_Y end - attribute \src "ls180.v:5973.38-5973.142" - cell $and $and$ls180.v:5973$1342 + attribute \src "ls180.v:3331.43-3331.107" + cell $and $and$ls180.v:3331$998 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5973$1340_Y - connect \B $eq$ls180.v:5973$1341_Y - connect \Y $and$ls180.v:5973$1342_Y + connect \A \libresocsim_csrbank5_sel + connect \B $not$ls180.v:3331$997_Y + connect \Y $and$ls180.v:3331$998_Y end - attribute \src "ls180.v:5974.39-5974.95" - cell $and $and$ls180.v:5974$1344 + attribute \src "ls180.v:3333.47-3333.108" + cell $and $and$ls180.v:3333$1001 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5974$1343_Y - connect \Y $and$ls180.v:5974$1344_Y + connect \A \libresocsim_csrbank5_sel + connect \B \libresocsim_interface5_bank_bus_we + connect \Y $and$ls180.v:3333$1001_Y end - attribute \src "ls180.v:5974.38-5974.145" - cell $and $and$ls180.v:5974$1346 + attribute \src "ls180.v:3333.46-3333.163" + cell $and $and$ls180.v:3333$1003 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5974$1344_Y - connect \B $eq$ls180.v:5974$1345_Y - connect \Y $and$ls180.v:5974$1346_Y + connect \A $and$ls180.v:3333$1001_Y + connect \B $eq$ls180.v:3333$1002_Y + connect \Y $and$ls180.v:3333$1003_Y end - attribute \src "ls180.v:5976.39-5976.92" - cell $and $and$ls180.v:5976$1347 + attribute \src "ls180.v:3334.47-3334.111" + cell $and $and$ls180.v:3334$1005 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5976$1347_Y + connect \A \libresocsim_csrbank5_sel + connect \B $not$ls180.v:3334$1004_Y + connect \Y $and$ls180.v:3334$1005_Y end - attribute \src "ls180.v:5976.38-5976.142" - cell $and $and$ls180.v:5976$1349 + attribute \src "ls180.v:3334.46-3334.166" + cell $and $and$ls180.v:3334$1007 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5976$1347_Y - connect \B $eq$ls180.v:5976$1348_Y - connect \Y $and$ls180.v:5976$1349_Y + connect \A $and$ls180.v:3334$1005_Y + connect \B $eq$ls180.v:3334$1006_Y + connect \Y $and$ls180.v:3334$1007_Y end - attribute \src "ls180.v:5977.39-5977.95" - cell $and $and$ls180.v:5977$1351 + attribute \src "ls180.v:3336.48-3336.109" + cell $and $and$ls180.v:3336$1008 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5977$1350_Y - connect \Y $and$ls180.v:5977$1351_Y + connect \A \libresocsim_csrbank5_sel + connect \B \libresocsim_interface5_bank_bus_we + connect \Y $and$ls180.v:3336$1008_Y end - attribute \src "ls180.v:5977.38-5977.145" - cell $and $and$ls180.v:5977$1353 + attribute \src "ls180.v:3336.47-3336.164" + cell $and $and$ls180.v:3336$1010 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5977$1351_Y - connect \B $eq$ls180.v:5977$1352_Y - connect \Y $and$ls180.v:5977$1353_Y + connect \A $and$ls180.v:3336$1008_Y + connect \B $eq$ls180.v:3336$1009_Y + connect \Y $and$ls180.v:3336$1010_Y end - attribute \src "ls180.v:5979.39-5979.92" - cell $and $and$ls180.v:5979$1354 + attribute \src "ls180.v:3337.48-3337.112" + cell $and $and$ls180.v:3337$1012 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5979$1354_Y + connect \A \libresocsim_csrbank5_sel + connect \B $not$ls180.v:3337$1011_Y + connect \Y $and$ls180.v:3337$1012_Y end - attribute \src "ls180.v:5979.38-5979.142" - cell $and $and$ls180.v:5979$1356 + attribute \src "ls180.v:3337.47-3337.167" + cell $and $and$ls180.v:3337$1014 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5979$1354_Y - connect \B $eq$ls180.v:5979$1355_Y - connect \Y $and$ls180.v:5979$1356_Y + connect \A $and$ls180.v:3337$1012_Y + connect \B $eq$ls180.v:3337$1013_Y + connect \Y $and$ls180.v:3337$1014_Y end - attribute \src "ls180.v:5980.39-5980.95" - cell $and $and$ls180.v:5980$1358 + attribute \src "ls180.v:3339.47-3339.108" + cell $and $and$ls180.v:3339$1015 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5980$1357_Y - connect \Y $and$ls180.v:5980$1358_Y + connect \A \libresocsim_csrbank5_sel + connect \B \libresocsim_interface5_bank_bus_we + connect \Y $and$ls180.v:3339$1015_Y end - attribute \src "ls180.v:5980.38-5980.145" - cell $and $and$ls180.v:5980$1360 + attribute \src "ls180.v:3339.46-3339.163" + cell $and $and$ls180.v:3339$1017 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5980$1358_Y - connect \B $eq$ls180.v:5980$1359_Y - connect \Y $and$ls180.v:5980$1360_Y + connect \A $and$ls180.v:3339$1015_Y + connect \B $eq$ls180.v:3339$1016_Y + connect \Y $and$ls180.v:3339$1017_Y end - attribute \src "ls180.v:5982.40-5982.93" - cell $and $and$ls180.v:5982$1361 + attribute \src "ls180.v:3340.47-3340.111" + cell $and $and$ls180.v:3340$1019 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5982$1361_Y + connect \A \libresocsim_csrbank5_sel + connect \B $not$ls180.v:3340$1018_Y + connect \Y $and$ls180.v:3340$1019_Y end - attribute \src "ls180.v:5982.39-5982.143" - cell $and $and$ls180.v:5982$1363 + attribute \src "ls180.v:3340.46-3340.166" + cell $and $and$ls180.v:3340$1021 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5982$1361_Y - connect \B $eq$ls180.v:5982$1362_Y - connect \Y $and$ls180.v:5982$1363_Y + connect \A $and$ls180.v:3340$1019_Y + connect \B $eq$ls180.v:3340$1020_Y + connect \Y $and$ls180.v:3340$1021_Y end - attribute \src "ls180.v:5983.40-5983.96" - cell $and $and$ls180.v:5983$1365 + attribute \src "ls180.v:3359.20-3359.81" + cell $and $and$ls180.v:3359$1023 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5983$1364_Y - connect \Y $and$ls180.v:5983$1365_Y + connect \A \libresocsim_csrbank6_sel + connect \B \libresocsim_interface6_bank_bus_we + connect \Y $and$ls180.v:3359$1023_Y end - attribute \src "ls180.v:5983.39-5983.146" - cell $and $and$ls180.v:5983$1367 + attribute \src "ls180.v:3359.19-3359.135" + cell $and $and$ls180.v:3359$1025 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5983$1365_Y - connect \B $eq$ls180.v:5983$1366_Y - connect \Y $and$ls180.v:5983$1367_Y + connect \A $and$ls180.v:3359$1023_Y + connect \B $eq$ls180.v:3359$1024_Y + connect \Y $and$ls180.v:3359$1025_Y end - attribute \src "ls180.v:5985.40-5985.93" - cell $and $and$ls180.v:5985$1368 + attribute \src "ls180.v:3360.20-3360.84" + cell $and $and$ls180.v:3360$1027 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5985$1368_Y + connect \A \libresocsim_csrbank6_sel + connect \B $not$ls180.v:3360$1026_Y + connect \Y $and$ls180.v:3360$1027_Y end - attribute \src "ls180.v:5985.39-5985.143" - cell $and $and$ls180.v:5985$1370 + attribute \src "ls180.v:3360.19-3360.138" + cell $and $and$ls180.v:3360$1029 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5985$1368_Y - connect \B $eq$ls180.v:5985$1369_Y - connect \Y $and$ls180.v:5985$1370_Y + connect \A $and$ls180.v:3360$1027_Y + connect \B $eq$ls180.v:3360$1028_Y + connect \Y $and$ls180.v:3360$1029_Y end - attribute \src "ls180.v:5986.40-5986.96" - cell $and $and$ls180.v:5986$1372 + attribute \src "ls180.v:3362.43-3362.104" + cell $and $and$ls180.v:3362$1030 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5986$1371_Y - connect \Y $and$ls180.v:5986$1372_Y + connect \A \libresocsim_csrbank6_sel + connect \B \libresocsim_interface6_bank_bus_we + connect \Y $and$ls180.v:3362$1030_Y end - attribute \src "ls180.v:5986.39-5986.146" - cell $and $and$ls180.v:5986$1374 + attribute \src "ls180.v:3362.42-3362.158" + cell $and $and$ls180.v:3362$1032 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5986$1372_Y - connect \B $eq$ls180.v:5986$1373_Y - connect \Y $and$ls180.v:5986$1374_Y + connect \A $and$ls180.v:3362$1030_Y + connect \B $eq$ls180.v:3362$1031_Y + connect \Y $and$ls180.v:3362$1032_Y end - attribute \src "ls180.v:5988.40-5988.93" - cell $and $and$ls180.v:5988$1375 + attribute \src "ls180.v:3363.43-3363.107" + cell $and $and$ls180.v:3363$1034 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5988$1375_Y + connect \A \libresocsim_csrbank6_sel + connect \B $not$ls180.v:3363$1033_Y + connect \Y $and$ls180.v:3363$1034_Y end - attribute \src "ls180.v:5988.39-5988.143" - cell $and $and$ls180.v:5988$1377 + attribute \src "ls180.v:3363.42-3363.161" + cell $and $and$ls180.v:3363$1036 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5988$1375_Y - connect \B $eq$ls180.v:5988$1376_Y - connect \Y $and$ls180.v:5988$1377_Y + connect \A $and$ls180.v:3363$1034_Y + connect \B $eq$ls180.v:3363$1035_Y + connect \Y $and$ls180.v:3363$1036_Y end - attribute \src "ls180.v:5989.40-5989.96" - cell $and $and$ls180.v:5989$1379 + attribute \src "ls180.v:3365.44-3365.105" + cell $and $and$ls180.v:3365$1037 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5989$1378_Y - connect \Y $and$ls180.v:5989$1379_Y + connect \A \libresocsim_csrbank6_sel + connect \B \libresocsim_interface6_bank_bus_we + connect \Y $and$ls180.v:3365$1037_Y end - attribute \src "ls180.v:5989.39-5989.146" - cell $and $and$ls180.v:5989$1381 + attribute \src "ls180.v:3365.43-3365.159" + cell $and $and$ls180.v:3365$1039 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5989$1379_Y - connect \B $eq$ls180.v:5989$1380_Y - connect \Y $and$ls180.v:5989$1381_Y + connect \A $and$ls180.v:3365$1037_Y + connect \B $eq$ls180.v:3365$1038_Y + connect \Y $and$ls180.v:3365$1039_Y end - attribute \src "ls180.v:5991.40-5991.93" - cell $and $and$ls180.v:5991$1382 + attribute \src "ls180.v:3366.44-3366.108" + cell $and $and$ls180.v:3366$1041 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B \builder_interface4_bank_bus_we - connect \Y $and$ls180.v:5991$1382_Y + connect \A \libresocsim_csrbank6_sel + connect \B $not$ls180.v:3366$1040_Y + connect \Y $and$ls180.v:3366$1041_Y end - attribute \src "ls180.v:5991.39-5991.143" - cell $and $and$ls180.v:5991$1384 + attribute \src "ls180.v:3366.43-3366.162" + cell $and $and$ls180.v:3366$1043 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5991$1382_Y - connect \B $eq$ls180.v:5991$1383_Y - connect \Y $and$ls180.v:5991$1384_Y + connect \A $and$ls180.v:3366$1041_Y + connect \B $eq$ls180.v:3366$1042_Y + connect \Y $and$ls180.v:3366$1043_Y end - attribute \src "ls180.v:5992.40-5992.96" - cell $and $and$ls180.v:5992$1386 + attribute \src "ls180.v:3368.35-3368.96" + cell $and $and$ls180.v:3368$1044 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank4_sel - connect \B $not$ls180.v:5992$1385_Y - connect \Y $and$ls180.v:5992$1386_Y + connect \A \libresocsim_csrbank6_sel + connect \B \libresocsim_interface6_bank_bus_we + connect \Y $and$ls180.v:3368$1044_Y end - attribute \src "ls180.v:5992.39-5992.146" - cell $and $and$ls180.v:5992$1388 + attribute \src "ls180.v:3368.34-3368.150" + cell $and $and$ls180.v:3368$1046 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:5992$1386_Y - connect \B $eq$ls180.v:5992$1387_Y - connect \Y $and$ls180.v:5992$1388_Y + connect \A $and$ls180.v:3368$1044_Y + connect \B $eq$ls180.v:3368$1045_Y + connect \Y $and$ls180.v:3368$1046_Y end - attribute \src "ls180.v:6004.42-6004.95" - cell $and $and$ls180.v:6004$1390 + attribute \src "ls180.v:3369.35-3369.99" + cell $and $and$ls180.v:3369$1048 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6004$1390_Y + connect \A \libresocsim_csrbank6_sel + connect \B $not$ls180.v:3369$1047_Y + connect \Y $and$ls180.v:3369$1048_Y end - attribute \src "ls180.v:6004.41-6004.145" - cell $and $and$ls180.v:6004$1392 + attribute \src "ls180.v:3369.34-3369.153" + cell $and $and$ls180.v:3369$1050 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6004$1390_Y - connect \B $eq$ls180.v:6004$1391_Y - connect \Y $and$ls180.v:6004$1392_Y + connect \A $and$ls180.v:3369$1048_Y + connect \B $eq$ls180.v:3369$1049_Y + connect \Y $and$ls180.v:3369$1050_Y end - attribute \src "ls180.v:6005.42-6005.98" - cell $and $and$ls180.v:6005$1394 + attribute \src "ls180.v:3371.36-3371.97" + cell $and $and$ls180.v:3371$1051 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6005$1393_Y - connect \Y $and$ls180.v:6005$1394_Y + connect \A \libresocsim_csrbank6_sel + connect \B \libresocsim_interface6_bank_bus_we + connect \Y $and$ls180.v:3371$1051_Y end - attribute \src "ls180.v:6005.41-6005.148" - cell $and $and$ls180.v:6005$1396 + attribute \src "ls180.v:3371.35-3371.151" + cell $and $and$ls180.v:3371$1053 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6005$1394_Y - connect \B $eq$ls180.v:6005$1395_Y - connect \Y $and$ls180.v:6005$1396_Y + connect \A $and$ls180.v:3371$1051_Y + connect \B $eq$ls180.v:3371$1052_Y + connect \Y $and$ls180.v:3371$1053_Y end - attribute \src "ls180.v:6007.42-6007.95" - cell $and $and$ls180.v:6007$1397 + attribute \src "ls180.v:3372.36-3372.100" + cell $and $and$ls180.v:3372$1055 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6007$1397_Y + connect \A \libresocsim_csrbank6_sel + connect \B $not$ls180.v:3372$1054_Y + connect \Y $and$ls180.v:3372$1055_Y end - attribute \src "ls180.v:6007.41-6007.145" - cell $and $and$ls180.v:6007$1399 + attribute \src "ls180.v:3372.35-3372.154" + cell $and $and$ls180.v:3372$1057 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6007$1397_Y - connect \B $eq$ls180.v:6007$1398_Y - connect \Y $and$ls180.v:6007$1399_Y + connect \A $and$ls180.v:3372$1055_Y + connect \B $eq$ls180.v:3372$1056_Y + connect \Y $and$ls180.v:3372$1057_Y end - attribute \src "ls180.v:6008.42-6008.98" - cell $and $and$ls180.v:6008$1401 + attribute \src "ls180.v:3374.47-3374.108" + cell $and $and$ls180.v:3374$1058 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6008$1400_Y - connect \Y $and$ls180.v:6008$1401_Y + connect \A \libresocsim_csrbank6_sel + connect \B \libresocsim_interface6_bank_bus_we + connect \Y $and$ls180.v:3374$1058_Y end - attribute \src "ls180.v:6008.41-6008.148" - cell $and $and$ls180.v:6008$1403 + attribute \src "ls180.v:3374.46-3374.162" + cell $and $and$ls180.v:3374$1060 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6008$1401_Y - connect \B $eq$ls180.v:6008$1402_Y - connect \Y $and$ls180.v:6008$1403_Y + connect \A $and$ls180.v:3374$1058_Y + connect \B $eq$ls180.v:3374$1059_Y + connect \Y $and$ls180.v:3374$1060_Y end - attribute \src "ls180.v:6010.42-6010.95" - cell $and $and$ls180.v:6010$1404 + attribute \src "ls180.v:3375.47-3375.111" + cell $and $and$ls180.v:3375$1062 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6010$1404_Y + connect \A \libresocsim_csrbank6_sel + connect \B $not$ls180.v:3375$1061_Y + connect \Y $and$ls180.v:3375$1062_Y end - attribute \src "ls180.v:6010.41-6010.145" - cell $and $and$ls180.v:6010$1406 + attribute \src "ls180.v:3375.46-3375.165" + cell $and $and$ls180.v:3375$1064 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6010$1404_Y - connect \B $eq$ls180.v:6010$1405_Y - connect \Y $and$ls180.v:6010$1406_Y + connect \A $and$ls180.v:3375$1062_Y + connect \B $eq$ls180.v:3375$1063_Y + connect \Y $and$ls180.v:3375$1064_Y end - attribute \src "ls180.v:6011.42-6011.98" - cell $and $and$ls180.v:6011$1408 + attribute \src "ls180.v:3377.44-3377.105" + cell $and $and$ls180.v:3377$1065 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6011$1407_Y - connect \Y $and$ls180.v:6011$1408_Y + connect \A \libresocsim_csrbank6_sel + connect \B \libresocsim_interface6_bank_bus_we + connect \Y $and$ls180.v:3377$1065_Y end - attribute \src "ls180.v:6011.41-6011.148" - cell $and $and$ls180.v:6011$1410 + attribute \src "ls180.v:3377.43-3377.159" + cell $and $and$ls180.v:3377$1067 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6011$1408_Y - connect \B $eq$ls180.v:6011$1409_Y - connect \Y $and$ls180.v:6011$1410_Y + connect \A $and$ls180.v:3377$1065_Y + connect \B $eq$ls180.v:3377$1066_Y + connect \Y $and$ls180.v:3377$1067_Y end - attribute \src "ls180.v:6013.42-6013.95" - cell $and $and$ls180.v:6013$1411 + attribute \src "ls180.v:3378.44-3378.108" + cell $and $and$ls180.v:3378$1069 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6013$1411_Y + connect \A \libresocsim_csrbank6_sel + connect \B $not$ls180.v:3378$1068_Y + connect \Y $and$ls180.v:3378$1069_Y end - attribute \src "ls180.v:6013.41-6013.145" - cell $and $and$ls180.v:6013$1413 + attribute \src "ls180.v:3378.43-3378.162" + cell $and $and$ls180.v:3378$1071 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6013$1411_Y - connect \B $eq$ls180.v:6013$1412_Y - connect \Y $and$ls180.v:6013$1413_Y + connect \A $and$ls180.v:3378$1069_Y + connect \B $eq$ls180.v:3378$1070_Y + connect \Y $and$ls180.v:3378$1071_Y end - attribute \src "ls180.v:6014.42-6014.98" - cell $and $and$ls180.v:6014$1415 + attribute \src "ls180.v:3380.43-3380.104" + cell $and $and$ls180.v:3380$1072 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6014$1414_Y - connect \Y $and$ls180.v:6014$1415_Y + connect \A \libresocsim_csrbank6_sel + connect \B \libresocsim_interface6_bank_bus_we + connect \Y $and$ls180.v:3380$1072_Y end - attribute \src "ls180.v:6014.41-6014.148" - cell $and $and$ls180.v:6014$1417 + attribute \src "ls180.v:3380.42-3380.158" + cell $and $and$ls180.v:3380$1074 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6014$1415_Y - connect \B $eq$ls180.v:6014$1416_Y - connect \Y $and$ls180.v:6014$1417_Y + connect \A $and$ls180.v:3380$1072_Y + connect \B $eq$ls180.v:3380$1073_Y + connect \Y $and$ls180.v:3380$1074_Y end - attribute \src "ls180.v:6016.42-6016.95" - cell $and $and$ls180.v:6016$1418 + attribute \src "ls180.v:3381.43-3381.107" + cell $and $and$ls180.v:3381$1076 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6016$1418_Y + connect \A \libresocsim_csrbank6_sel + connect \B $not$ls180.v:3381$1075_Y + connect \Y $and$ls180.v:3381$1076_Y end - attribute \src "ls180.v:6016.41-6016.145" - cell $and $and$ls180.v:6016$1420 + attribute \src "ls180.v:3381.42-3381.161" + cell $and $and$ls180.v:3381$1078 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6016$1418_Y - connect \B $eq$ls180.v:6016$1419_Y - connect \Y $and$ls180.v:6016$1420_Y + connect \A $and$ls180.v:3381$1076_Y + connect \B $eq$ls180.v:3381$1077_Y + connect \Y $and$ls180.v:3381$1078_Y end - attribute \src "ls180.v:6017.42-6017.98" - cell $and $and$ls180.v:6017$1422 + attribute \src "ls180.v:3393.49-3393.110" + cell $and $and$ls180.v:3393$1080 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6017$1421_Y - connect \Y $and$ls180.v:6017$1422_Y + connect \A \libresocsim_csrbank7_sel + connect \B \libresocsim_interface7_bank_bus_we + connect \Y $and$ls180.v:3393$1080_Y end - attribute \src "ls180.v:6017.41-6017.148" - cell $and $and$ls180.v:6017$1424 + attribute \src "ls180.v:3393.48-3393.164" + cell $and $and$ls180.v:3393$1082 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6017$1422_Y - connect \B $eq$ls180.v:6017$1423_Y - connect \Y $and$ls180.v:6017$1424_Y + connect \A $and$ls180.v:3393$1080_Y + connect \B $eq$ls180.v:3393$1081_Y + connect \Y $and$ls180.v:3393$1082_Y end - attribute \src "ls180.v:6019.42-6019.95" - cell $and $and$ls180.v:6019$1425 + attribute \src "ls180.v:3394.49-3394.113" + cell $and $and$ls180.v:3394$1084 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6019$1425_Y + connect \A \libresocsim_csrbank7_sel + connect \B $not$ls180.v:3394$1083_Y + connect \Y $and$ls180.v:3394$1084_Y end - attribute \src "ls180.v:6019.41-6019.145" - cell $and $and$ls180.v:6019$1427 + attribute \src "ls180.v:3394.48-3394.167" + cell $and $and$ls180.v:3394$1086 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6019$1425_Y - connect \B $eq$ls180.v:6019$1426_Y - connect \Y $and$ls180.v:6019$1427_Y + connect \A $and$ls180.v:3394$1084_Y + connect \B $eq$ls180.v:3394$1085_Y + connect \Y $and$ls180.v:3394$1086_Y end - attribute \src "ls180.v:6020.42-6020.98" - cell $and $and$ls180.v:6020$1429 + attribute \src "ls180.v:3396.49-3396.110" + cell $and $and$ls180.v:3396$1087 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6020$1428_Y - connect \Y $and$ls180.v:6020$1429_Y + connect \A \libresocsim_csrbank7_sel + connect \B \libresocsim_interface7_bank_bus_we + connect \Y $and$ls180.v:3396$1087_Y end - attribute \src "ls180.v:6020.41-6020.148" - cell $and $and$ls180.v:6020$1431 + attribute \src "ls180.v:3396.48-3396.164" + cell $and $and$ls180.v:3396$1089 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6020$1429_Y - connect \B $eq$ls180.v:6020$1430_Y - connect \Y $and$ls180.v:6020$1431_Y + connect \A $and$ls180.v:3396$1087_Y + connect \B $eq$ls180.v:3396$1088_Y + connect \Y $and$ls180.v:3396$1089_Y end - attribute \src "ls180.v:6022.42-6022.95" - cell $and $and$ls180.v:6022$1432 + attribute \src "ls180.v:3397.49-3397.113" + cell $and $and$ls180.v:3397$1091 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6022$1432_Y + connect \A \libresocsim_csrbank7_sel + connect \B $not$ls180.v:3397$1090_Y + connect \Y $and$ls180.v:3397$1091_Y end - attribute \src "ls180.v:6022.41-6022.145" - cell $and $and$ls180.v:6022$1434 + attribute \src "ls180.v:3397.48-3397.167" + cell $and $and$ls180.v:3397$1093 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6022$1432_Y - connect \B $eq$ls180.v:6022$1433_Y - connect \Y $and$ls180.v:6022$1434_Y + connect \A $and$ls180.v:3397$1091_Y + connect \B $eq$ls180.v:3397$1092_Y + connect \Y $and$ls180.v:3397$1093_Y end - attribute \src "ls180.v:6023.42-6023.98" - cell $and $and$ls180.v:6023$1436 + attribute \src "ls180.v:3399.49-3399.110" + cell $and $and$ls180.v:3399$1094 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6023$1435_Y - connect \Y $and$ls180.v:6023$1436_Y + connect \A \libresocsim_csrbank7_sel + connect \B \libresocsim_interface7_bank_bus_we + connect \Y $and$ls180.v:3399$1094_Y end - attribute \src "ls180.v:6023.41-6023.148" - cell $and $and$ls180.v:6023$1438 + attribute \src "ls180.v:3399.48-3399.164" + cell $and $and$ls180.v:3399$1096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6023$1436_Y - connect \B $eq$ls180.v:6023$1437_Y - connect \Y $and$ls180.v:6023$1438_Y + connect \A $and$ls180.v:3399$1094_Y + connect \B $eq$ls180.v:3399$1095_Y + connect \Y $and$ls180.v:3399$1096_Y end - attribute \src "ls180.v:6025.42-6025.95" - cell $and $and$ls180.v:6025$1439 + attribute \src "ls180.v:3400.49-3400.113" + cell $and $and$ls180.v:3400$1098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6025$1439_Y + connect \A \libresocsim_csrbank7_sel + connect \B $not$ls180.v:3400$1097_Y + connect \Y $and$ls180.v:3400$1098_Y end - attribute \src "ls180.v:6025.41-6025.145" - cell $and $and$ls180.v:6025$1441 + attribute \src "ls180.v:3400.48-3400.167" + cell $and $and$ls180.v:3400$1100 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6025$1439_Y - connect \B $eq$ls180.v:6025$1440_Y - connect \Y $and$ls180.v:6025$1441_Y + connect \A $and$ls180.v:3400$1098_Y + connect \B $eq$ls180.v:3400$1099_Y + connect \Y $and$ls180.v:3400$1100_Y end - attribute \src "ls180.v:6026.42-6026.98" - cell $and $and$ls180.v:6026$1443 + attribute \src "ls180.v:3402.49-3402.110" + cell $and $and$ls180.v:3402$1101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6026$1442_Y - connect \Y $and$ls180.v:6026$1443_Y + connect \A \libresocsim_csrbank7_sel + connect \B \libresocsim_interface7_bank_bus_we + connect \Y $and$ls180.v:3402$1101_Y end - attribute \src "ls180.v:6026.41-6026.148" - cell $and $and$ls180.v:6026$1445 + attribute \src "ls180.v:3402.48-3402.164" + cell $and $and$ls180.v:3402$1103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6026$1443_Y - connect \B $eq$ls180.v:6026$1444_Y - connect \Y $and$ls180.v:6026$1445_Y + connect \A $and$ls180.v:3402$1101_Y + connect \B $eq$ls180.v:3402$1102_Y + connect \Y $and$ls180.v:3402$1103_Y end - attribute \src "ls180.v:6028.44-6028.97" - cell $and $and$ls180.v:6028$1446 + attribute \src "ls180.v:3403.49-3403.113" + cell $and $and$ls180.v:3403$1105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6028$1446_Y + connect \A \libresocsim_csrbank7_sel + connect \B $not$ls180.v:3403$1104_Y + connect \Y $and$ls180.v:3403$1105_Y end - attribute \src "ls180.v:6028.43-6028.147" - cell $and $and$ls180.v:6028$1448 + attribute \src "ls180.v:3403.48-3403.167" + cell $and $and$ls180.v:3403$1107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6028$1446_Y - connect \B $eq$ls180.v:6028$1447_Y - connect \Y $and$ls180.v:6028$1448_Y + connect \A $and$ls180.v:3403$1105_Y + connect \B $eq$ls180.v:3403$1106_Y + connect \Y $and$ls180.v:3403$1107_Y end - attribute \src "ls180.v:6029.44-6029.100" - cell $and $and$ls180.v:6029$1450 + attribute \src "ls180.v:3763.96-3763.165" + cell $and $and$ls180.v:3763$1138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6029$1449_Y - connect \Y $and$ls180.v:6029$1450_Y + connect \A \sdram_interface_bank1_lock + connect \B $eq$ls180.v:3763$1137_Y + connect \Y $and$ls180.v:3763$1138_Y end - attribute \src "ls180.v:6029.43-6029.150" - cell $and $and$ls180.v:6029$1452 + attribute \src "ls180.v:3763.171-3763.240" + cell $and $and$ls180.v:3763$1141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6029$1450_Y - connect \B $eq$ls180.v:6029$1451_Y - connect \Y $and$ls180.v:6029$1452_Y + connect \A \sdram_interface_bank2_lock + connect \B $eq$ls180.v:3763$1140_Y + connect \Y $and$ls180.v:3763$1141_Y end - attribute \src "ls180.v:6031.44-6031.97" - cell $and $and$ls180.v:6031$1453 + attribute \src "ls180.v:3763.246-3763.315" + cell $and $and$ls180.v:3763$1144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6031$1453_Y + connect \A \sdram_interface_bank3_lock + connect \B $eq$ls180.v:3763$1143_Y + connect \Y $and$ls180.v:3763$1144_Y end - attribute \src "ls180.v:6031.43-6031.147" - cell $and $and$ls180.v:6031$1455 + attribute \src "ls180.v:3763.27-3763.318" + cell $and $and$ls180.v:3763$1147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6031$1453_Y - connect \B $eq$ls180.v:6031$1454_Y - connect \Y $and$ls180.v:6031$1455_Y + connect \A $eq$ls180.v:3763$1136_Y + connect \B $not$ls180.v:3763$1146_Y + connect \Y $and$ls180.v:3763$1147_Y end - attribute \src "ls180.v:6032.44-6032.100" - cell $and $and$ls180.v:6032$1457 + attribute \src "ls180.v:3763.26-3763.336" + cell $and $and$ls180.v:3763$1148 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6032$1456_Y - connect \Y $and$ls180.v:6032$1457_Y + connect \A $and$ls180.v:3763$1147_Y + connect \B \port_cmd_valid + connect \Y $and$ls180.v:3763$1148_Y end - attribute \src "ls180.v:6032.43-6032.150" - cell $and $and$ls180.v:6032$1459 + attribute \src "ls180.v:3787.96-3787.165" + cell $and $and$ls180.v:3787$1154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6032$1457_Y - connect \B $eq$ls180.v:6032$1458_Y - connect \Y $and$ls180.v:6032$1459_Y + connect \A \sdram_interface_bank0_lock + connect \B $eq$ls180.v:3787$1153_Y + connect \Y $and$ls180.v:3787$1154_Y end - attribute \src "ls180.v:6034.44-6034.97" - cell $and $and$ls180.v:6034$1460 + attribute \src "ls180.v:3787.171-3787.240" + cell $and $and$ls180.v:3787$1157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6034$1460_Y + connect \A \sdram_interface_bank2_lock + connect \B $eq$ls180.v:3787$1156_Y + connect \Y $and$ls180.v:3787$1157_Y end - attribute \src "ls180.v:6034.43-6034.148" - cell $and $and$ls180.v:6034$1462 + attribute \src "ls180.v:3787.246-3787.315" + cell $and $and$ls180.v:3787$1160 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6034$1460_Y - connect \B $eq$ls180.v:6034$1461_Y - connect \Y $and$ls180.v:6034$1462_Y + connect \A \sdram_interface_bank3_lock + connect \B $eq$ls180.v:3787$1159_Y + connect \Y $and$ls180.v:3787$1160_Y end - attribute \src "ls180.v:6035.44-6035.100" - cell $and $and$ls180.v:6035$1464 + attribute \src "ls180.v:3787.27-3787.318" + cell $and $and$ls180.v:3787$1163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6035$1463_Y - connect \Y $and$ls180.v:6035$1464_Y + connect \A $eq$ls180.v:3787$1152_Y + connect \B $not$ls180.v:3787$1162_Y + connect \Y $and$ls180.v:3787$1163_Y end - attribute \src "ls180.v:6035.43-6035.151" - cell $and $and$ls180.v:6035$1466 + attribute \src "ls180.v:3787.26-3787.336" + cell $and $and$ls180.v:3787$1164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6035$1464_Y - connect \B $eq$ls180.v:6035$1465_Y - connect \Y $and$ls180.v:6035$1466_Y + connect \A $and$ls180.v:3787$1163_Y + connect \B \port_cmd_valid + connect \Y $and$ls180.v:3787$1164_Y end - attribute \src "ls180.v:6037.44-6037.97" - cell $and $and$ls180.v:6037$1467 + attribute \src "ls180.v:3811.96-3811.165" + cell $and $and$ls180.v:3811$1170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6037$1467_Y + connect \A \sdram_interface_bank0_lock + connect \B $eq$ls180.v:3811$1169_Y + connect \Y $and$ls180.v:3811$1170_Y end - attribute \src "ls180.v:6037.43-6037.148" - cell $and $and$ls180.v:6037$1469 + attribute \src "ls180.v:3811.171-3811.240" + cell $and $and$ls180.v:3811$1173 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6037$1467_Y - connect \B $eq$ls180.v:6037$1468_Y - connect \Y $and$ls180.v:6037$1469_Y + connect \A \sdram_interface_bank1_lock + connect \B $eq$ls180.v:3811$1172_Y + connect \Y $and$ls180.v:3811$1173_Y end - attribute \src "ls180.v:6038.44-6038.100" - cell $and $and$ls180.v:6038$1471 + attribute \src "ls180.v:3811.246-3811.315" + cell $and $and$ls180.v:3811$1176 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6038$1470_Y - connect \Y $and$ls180.v:6038$1471_Y + connect \A \sdram_interface_bank3_lock + connect \B $eq$ls180.v:3811$1175_Y + connect \Y $and$ls180.v:3811$1176_Y end - attribute \src "ls180.v:6038.43-6038.151" - cell $and $and$ls180.v:6038$1473 + attribute \src "ls180.v:3811.27-3811.318" + cell $and $and$ls180.v:3811$1179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6038$1471_Y - connect \B $eq$ls180.v:6038$1472_Y - connect \Y $and$ls180.v:6038$1473_Y + connect \A $eq$ls180.v:3811$1168_Y + connect \B $not$ls180.v:3811$1178_Y + connect \Y $and$ls180.v:3811$1179_Y end - attribute \src "ls180.v:6040.44-6040.97" - cell $and $and$ls180.v:6040$1474 + attribute \src "ls180.v:3811.26-3811.336" + cell $and $and$ls180.v:3811$1180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6040$1474_Y + connect \A $and$ls180.v:3811$1179_Y + connect \B \port_cmd_valid + connect \Y $and$ls180.v:3811$1180_Y end - attribute \src "ls180.v:6040.43-6040.148" - cell $and $and$ls180.v:6040$1476 + attribute \src "ls180.v:3835.96-3835.165" + cell $and $and$ls180.v:3835$1186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6040$1474_Y - connect \B $eq$ls180.v:6040$1475_Y - connect \Y $and$ls180.v:6040$1476_Y + connect \A \sdram_interface_bank0_lock + connect \B $eq$ls180.v:3835$1185_Y + connect \Y $and$ls180.v:3835$1186_Y end - attribute \src "ls180.v:6041.44-6041.100" - cell $and $and$ls180.v:6041$1478 + attribute \src "ls180.v:3835.171-3835.240" + cell $and $and$ls180.v:3835$1189 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6041$1477_Y - connect \Y $and$ls180.v:6041$1478_Y + connect \A \sdram_interface_bank1_lock + connect \B $eq$ls180.v:3835$1188_Y + connect \Y $and$ls180.v:3835$1189_Y end - attribute \src "ls180.v:6041.43-6041.151" - cell $and $and$ls180.v:6041$1480 + attribute \src "ls180.v:3835.246-3835.315" + cell $and $and$ls180.v:3835$1192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6041$1478_Y - connect \B $eq$ls180.v:6041$1479_Y - connect \Y $and$ls180.v:6041$1480_Y + connect \A \sdram_interface_bank2_lock + connect \B $eq$ls180.v:3835$1191_Y + connect \Y $and$ls180.v:3835$1192_Y end - attribute \src "ls180.v:6043.41-6043.94" - cell $and $and$ls180.v:6043$1481 + attribute \src "ls180.v:3835.27-3835.318" + cell $and $and$ls180.v:3835$1195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6043$1481_Y + connect \A $eq$ls180.v:3835$1184_Y + connect \B $not$ls180.v:3835$1194_Y + connect \Y $and$ls180.v:3835$1195_Y end - attribute \src "ls180.v:6043.40-6043.145" - cell $and $and$ls180.v:6043$1483 + attribute \src "ls180.v:3835.26-3835.336" + cell $and $and$ls180.v:3835$1196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6043$1481_Y - connect \B $eq$ls180.v:6043$1482_Y - connect \Y $and$ls180.v:6043$1483_Y + connect \A $and$ls180.v:3835$1195_Y + connect \B \port_cmd_valid + connect \Y $and$ls180.v:3835$1196_Y end - attribute \src "ls180.v:6044.41-6044.97" - cell $and $and$ls180.v:6044$1485 + attribute \src "ls180.v:3992.22-3992.77" + cell $and $and$ls180.v:3992$1208 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6044$1484_Y - connect \Y $and$ls180.v:6044$1485_Y + connect \A \sdram_choose_req_cmd_valid + connect \B \sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3992$1208_Y end - attribute \src "ls180.v:6044.40-6044.148" - cell $and $and$ls180.v:6044$1487 + attribute \src "ls180.v:3992.21-3992.113" + cell $and $and$ls180.v:3992$1209 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6044$1485_Y - connect \B $eq$ls180.v:6044$1486_Y - connect \Y $and$ls180.v:6044$1487_Y + connect \A $and$ls180.v:3992$1208_Y + connect \B \sdram_choose_req_cmd_payload_cas + connect \Y $and$ls180.v:3992$1209_Y end - attribute \src "ls180.v:6046.42-6046.95" - cell $and $and$ls180.v:6046$1488 + attribute \src "ls180.v:3995.22-3995.77" + cell $and $and$ls180.v:3995$1210 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B \builder_interface5_bank_bus_we - connect \Y $and$ls180.v:6046$1488_Y + connect \A \sdram_choose_req_cmd_valid + connect \B \sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:3995$1210_Y end - attribute \src "ls180.v:6046.41-6046.146" - cell $and $and$ls180.v:6046$1490 + attribute \src "ls180.v:3995.21-3995.113" + cell $and $and$ls180.v:3995$1211 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6046$1488_Y - connect \B $eq$ls180.v:6046$1489_Y - connect \Y $and$ls180.v:6046$1490_Y + connect \A $and$ls180.v:3995$1210_Y + connect \B \sdram_choose_req_cmd_payload_cas + connect \Y $and$ls180.v:3995$1211_Y end - attribute \src "ls180.v:6047.42-6047.98" - cell $and $and$ls180.v:6047$1492 + attribute \src "ls180.v:3998.22-3998.55" + cell $and $and$ls180.v:3998$1212 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank5_sel - connect \B $not$ls180.v:6047$1491_Y - connect \Y $and$ls180.v:6047$1492_Y + connect \A \sdram_cmd_valid + connect \B \sdram_cmd_ready + connect \Y $and$ls180.v:3998$1212_Y end - attribute \src "ls180.v:6047.41-6047.149" - cell $and $and$ls180.v:6047$1494 + attribute \src "ls180.v:3998.21-3998.80" + cell $and $and$ls180.v:3998$1213 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6047$1492_Y - connect \B $eq$ls180.v:6047$1493_Y - connect \Y $and$ls180.v:6047$1494_Y + connect \A $and$ls180.v:3998$1212_Y + connect \B \sdram_cmd_payload_cas + connect \Y $and$ls180.v:3998$1213_Y end - attribute \src "ls180.v:6066.46-6066.99" - cell $and $and$ls180.v:6066$1496 + attribute \src "ls180.v:4009.22-4009.77" + cell $and $and$ls180.v:4009$1215 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6066$1496_Y + connect \A \sdram_choose_req_cmd_valid + connect \B \sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:4009$1215_Y end - attribute \src "ls180.v:6066.45-6066.149" - cell $and $and$ls180.v:6066$1498 + attribute \src "ls180.v:4009.21-4009.113" + cell $and $and$ls180.v:4009$1216 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6066$1496_Y - connect \B $eq$ls180.v:6066$1497_Y - connect \Y $and$ls180.v:6066$1498_Y + connect \A $and$ls180.v:4009$1215_Y + connect \B \sdram_choose_req_cmd_payload_ras + connect \Y $and$ls180.v:4009$1216_Y end - attribute \src "ls180.v:6067.46-6067.102" - cell $and $and$ls180.v:6067$1500 + attribute \src "ls180.v:4012.22-4012.77" + cell $and $and$ls180.v:4012$1217 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6067$1499_Y - connect \Y $and$ls180.v:6067$1500_Y + connect \A \sdram_choose_req_cmd_valid + connect \B \sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:4012$1217_Y end - attribute \src "ls180.v:6067.45-6067.152" - cell $and $and$ls180.v:6067$1502 + attribute \src "ls180.v:4012.21-4012.113" + cell $and $and$ls180.v:4012$1218 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6067$1500_Y - connect \B $eq$ls180.v:6067$1501_Y - connect \Y $and$ls180.v:6067$1502_Y + connect \A $and$ls180.v:4012$1217_Y + connect \B \sdram_choose_req_cmd_payload_ras + connect \Y $and$ls180.v:4012$1218_Y end - attribute \src "ls180.v:6069.46-6069.99" - cell $and $and$ls180.v:6069$1503 + attribute \src "ls180.v:4015.22-4015.55" + cell $and $and$ls180.v:4015$1219 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6069$1503_Y + connect \A \sdram_cmd_valid + connect \B \sdram_cmd_ready + connect \Y $and$ls180.v:4015$1219_Y end - attribute \src "ls180.v:6069.45-6069.149" - cell $and $and$ls180.v:6069$1505 + attribute \src "ls180.v:4015.21-4015.80" + cell $and $and$ls180.v:4015$1220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6069$1503_Y - connect \B $eq$ls180.v:6069$1504_Y - connect \Y $and$ls180.v:6069$1505_Y + connect \A $and$ls180.v:4015$1219_Y + connect \B \sdram_cmd_payload_ras + connect \Y $and$ls180.v:4015$1220_Y end - attribute \src "ls180.v:6070.46-6070.102" - cell $and $and$ls180.v:6070$1507 + attribute \src "ls180.v:4026.22-4026.77" + cell $and $and$ls180.v:4026$1222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6070$1506_Y - connect \Y $and$ls180.v:6070$1507_Y + connect \A \sdram_choose_req_cmd_valid + connect \B \sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:4026$1222_Y end - attribute \src "ls180.v:6070.45-6070.152" - cell $and $and$ls180.v:6070$1509 + attribute \src "ls180.v:4026.21-4026.112" + cell $and $and$ls180.v:4026$1223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6070$1507_Y - connect \B $eq$ls180.v:6070$1508_Y - connect \Y $and$ls180.v:6070$1509_Y + connect \A $and$ls180.v:4026$1222_Y + connect \B \sdram_choose_req_cmd_payload_we + connect \Y $and$ls180.v:4026$1223_Y end - attribute \src "ls180.v:6072.46-6072.99" - cell $and $and$ls180.v:6072$1510 + attribute \src "ls180.v:4029.22-4029.77" + cell $and $and$ls180.v:4029$1224 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6072$1510_Y + connect \A \sdram_choose_req_cmd_valid + connect \B \sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:4029$1224_Y end - attribute \src "ls180.v:6072.45-6072.149" - cell $and $and$ls180.v:6072$1512 + attribute \src "ls180.v:4029.21-4029.112" + cell $and $and$ls180.v:4029$1225 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6072$1510_Y - connect \B $eq$ls180.v:6072$1511_Y - connect \Y $and$ls180.v:6072$1512_Y + connect \A $and$ls180.v:4029$1224_Y + connect \B \sdram_choose_req_cmd_payload_we + connect \Y $and$ls180.v:4029$1225_Y end - attribute \src "ls180.v:6073.46-6073.102" - cell $and $and$ls180.v:6073$1514 + attribute \src "ls180.v:4032.22-4032.55" + cell $and $and$ls180.v:4032$1226 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6073$1513_Y - connect \Y $and$ls180.v:6073$1514_Y + connect \A \sdram_cmd_valid + connect \B \sdram_cmd_ready + connect \Y $and$ls180.v:4032$1226_Y end - attribute \src "ls180.v:6073.45-6073.152" - cell $and $and$ls180.v:6073$1516 + attribute \src "ls180.v:4032.21-4032.79" + cell $and $and$ls180.v:4032$1227 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6073$1514_Y - connect \B $eq$ls180.v:6073$1515_Y - connect \Y $and$ls180.v:6073$1516_Y + connect \A $and$ls180.v:4032$1226_Y + connect \B \sdram_cmd_payload_we + connect \Y $and$ls180.v:4032$1227_Y end - attribute \src "ls180.v:6075.46-6075.99" - cell $and $and$ls180.v:6075$1517 + attribute \src "ls180.v:4043.22-4043.77" + cell $and $and$ls180.v:4043$1229 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6075$1517_Y + connect \A \sdram_choose_req_cmd_valid + connect \B \sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:4043$1229_Y end - attribute \src "ls180.v:6075.45-6075.149" - cell $and $and$ls180.v:6075$1519 + attribute \src "ls180.v:4043.21-4043.117" + cell $and $and$ls180.v:4043$1230 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6075$1517_Y - connect \B $eq$ls180.v:6075$1518_Y - connect \Y $and$ls180.v:6075$1519_Y + connect \A $and$ls180.v:4043$1229_Y + connect \B \sdram_choose_req_cmd_payload_is_read + connect \Y $and$ls180.v:4043$1230_Y end - attribute \src "ls180.v:6076.46-6076.102" - cell $and $and$ls180.v:6076$1521 + attribute \src "ls180.v:4046.22-4046.77" + cell $and $and$ls180.v:4046$1231 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6076$1520_Y - connect \Y $and$ls180.v:6076$1521_Y + connect \A \sdram_choose_req_cmd_valid + connect \B \sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:4046$1231_Y end - attribute \src "ls180.v:6076.45-6076.152" - cell $and $and$ls180.v:6076$1523 + attribute \src "ls180.v:4046.21-4046.117" + cell $and $and$ls180.v:4046$1232 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6076$1521_Y - connect \B $eq$ls180.v:6076$1522_Y - connect \Y $and$ls180.v:6076$1523_Y + connect \A $and$ls180.v:4046$1231_Y + connect \B \sdram_choose_req_cmd_payload_is_read + connect \Y $and$ls180.v:4046$1232_Y end - attribute \src "ls180.v:6078.45-6078.98" - cell $and $and$ls180.v:6078$1524 + attribute \src "ls180.v:4049.22-4049.55" + cell $and $and$ls180.v:4049$1233 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6078$1524_Y + connect \A \sdram_cmd_valid + connect \B \sdram_cmd_ready + connect \Y $and$ls180.v:4049$1233_Y end - attribute \src "ls180.v:6078.44-6078.148" - cell $and $and$ls180.v:6078$1526 + attribute \src "ls180.v:4049.21-4049.84" + cell $and $and$ls180.v:4049$1234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6078$1524_Y - connect \B $eq$ls180.v:6078$1525_Y - connect \Y $and$ls180.v:6078$1526_Y + connect \A $and$ls180.v:4049$1233_Y + connect \B \sdram_cmd_payload_is_read + connect \Y $and$ls180.v:4049$1234_Y end - attribute \src "ls180.v:6079.45-6079.101" - cell $and $and$ls180.v:6079$1528 + attribute \src "ls180.v:4060.22-4060.77" + cell $and $and$ls180.v:4060$1236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6079$1527_Y - connect \Y $and$ls180.v:6079$1528_Y + connect \A \sdram_choose_req_cmd_valid + connect \B \sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:4060$1236_Y end - attribute \src "ls180.v:6079.44-6079.151" - cell $and $and$ls180.v:6079$1530 + attribute \src "ls180.v:4060.21-4060.118" + cell $and $and$ls180.v:4060$1237 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6079$1528_Y - connect \B $eq$ls180.v:6079$1529_Y - connect \Y $and$ls180.v:6079$1530_Y + connect \A $and$ls180.v:4060$1236_Y + connect \B \sdram_choose_req_cmd_payload_is_write + connect \Y $and$ls180.v:4060$1237_Y end - attribute \src "ls180.v:6081.45-6081.98" - cell $and $and$ls180.v:6081$1531 + attribute \src "ls180.v:4063.22-4063.77" + cell $and $and$ls180.v:4063$1238 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6081$1531_Y + connect \A \sdram_choose_req_cmd_valid + connect \B \sdram_choose_req_cmd_ready + connect \Y $and$ls180.v:4063$1238_Y end - attribute \src "ls180.v:6081.44-6081.148" - cell $and $and$ls180.v:6081$1533 + attribute \src "ls180.v:4063.21-4063.118" + cell $and $and$ls180.v:4063$1239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6081$1531_Y - connect \B $eq$ls180.v:6081$1532_Y - connect \Y $and$ls180.v:6081$1533_Y + connect \A $and$ls180.v:4063$1238_Y + connect \B \sdram_choose_req_cmd_payload_is_write + connect \Y $and$ls180.v:4063$1239_Y end - attribute \src "ls180.v:6082.45-6082.101" - cell $and $and$ls180.v:6082$1535 + attribute \src "ls180.v:4066.22-4066.55" + cell $and $and$ls180.v:4066$1240 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6082$1534_Y - connect \Y $and$ls180.v:6082$1535_Y + connect \A \sdram_cmd_valid + connect \B \sdram_cmd_ready + connect \Y $and$ls180.v:4066$1240_Y end - attribute \src "ls180.v:6082.44-6082.151" - cell $and $and$ls180.v:6082$1537 + attribute \src "ls180.v:4066.21-4066.85" + cell $and $and$ls180.v:4066$1241 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6082$1535_Y - connect \B $eq$ls180.v:6082$1536_Y - connect \Y $and$ls180.v:6082$1537_Y + connect \A $and$ls180.v:4066$1240_Y + connect \B \sdram_cmd_payload_is_write + connect \Y $and$ls180.v:4066$1241_Y end - attribute \src "ls180.v:6084.45-6084.98" - cell $and $and$ls180.v:6084$1538 + attribute \src "ls180.v:4234.61-4234.101" + cell $and $and$ls180.v:4234$1244 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6084$1538_Y + connect \A \dfi_p0_wrdata_en + connect \B \dfi_p0_wrdata_mask [0] + connect \Y $and$ls180.v:4234$1244_Y end - attribute \src "ls180.v:6084.44-6084.148" - cell $and $and$ls180.v:6084$1540 + attribute \src "ls180.v:4235.61-4235.101" + cell $and $and$ls180.v:4235$1245 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6084$1538_Y - connect \B $eq$ls180.v:6084$1539_Y - connect \Y $and$ls180.v:6084$1540_Y + connect \A \dfi_p0_wrdata_en + connect \B \dfi_p0_wrdata_mask [1] + connect \Y $and$ls180.v:4235$1245_Y end - attribute \src "ls180.v:6085.45-6085.101" - cell $and $and$ls180.v:6085$1542 + attribute \src "ls180.v:4357.8-4357.57" + cell $and $and$ls180.v:4357$1282 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6085$1541_Y - connect \Y $and$ls180.v:6085$1542_Y + connect \A \libresocsim_ram_bus_cyc + connect \B \libresocsim_ram_bus_stb + connect \Y $and$ls180.v:4357$1282_Y end - attribute \src "ls180.v:6085.44-6085.151" - cell $and $and$ls180.v:6085$1544 + attribute \src "ls180.v:4357.7-4357.87" + cell $and $and$ls180.v:4357$1284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6085$1542_Y - connect \B $eq$ls180.v:6085$1543_Y - connect \Y $and$ls180.v:6085$1544_Y + connect \A $and$ls180.v:4357$1282_Y + connect \B $not$ls180.v:4357$1283_Y + connect \Y $and$ls180.v:4357$1284_Y end - attribute \src "ls180.v:6087.45-6087.98" - cell $and $and$ls180.v:6087$1545 + attribute \src "ls180.v:4376.7-4376.65" + cell $and $and$ls180.v:4376$1288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6087$1545_Y + connect \A $not$ls180.v:4376$1287_Y + connect \B \libresocsim_zero_old_trigger + connect \Y $and$ls180.v:4376$1288_Y end - attribute \src "ls180.v:6087.44-6087.148" - cell $and $and$ls180.v:6087$1547 + attribute \src "ls180.v:4380.8-4380.49" + cell $and $and$ls180.v:4380$1289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6087$1545_Y - connect \B $eq$ls180.v:6087$1546_Y - connect \Y $and$ls180.v:6087$1547_Y + connect \A \ram_bus_ram_bus_cyc + connect \B \ram_bus_ram_bus_stb + connect \Y $and$ls180.v:4380$1289_Y end - attribute \src "ls180.v:6088.45-6088.101" - cell $and $and$ls180.v:6088$1549 + attribute \src "ls180.v:4380.7-4380.75" + cell $and $and$ls180.v:4380$1291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6088$1548_Y - connect \Y $and$ls180.v:6088$1549_Y + connect \A $and$ls180.v:4380$1289_Y + connect \B $not$ls180.v:4380$1290_Y + connect \Y $and$ls180.v:4380$1291_Y end - attribute \src "ls180.v:6088.44-6088.151" - cell $and $and$ls180.v:6088$1551 + attribute \src "ls180.v:4388.7-4388.46" + cell $and $and$ls180.v:4388$1293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6088$1549_Y - connect \B $eq$ls180.v:6088$1550_Y - connect \Y $and$ls180.v:6088$1551_Y + connect \A \sdram_timer_wait + connect \B $not$ls180.v:4388$1292_Y + connect \Y $and$ls180.v:4388$1293_Y end - attribute \src "ls180.v:6090.36-6090.89" - cell $and $and$ls180.v:6090$1552 + attribute \src "ls180.v:4416.7-4416.65" + cell $and $and$ls180.v:4416$1300 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6090$1552_Y + connect \A \sdram_sequencer_start1 + connect \B $eq$ls180.v:4416$1299_Y + connect \Y $and$ls180.v:4416$1300_Y end - attribute \src "ls180.v:6090.35-6090.139" - cell $and $and$ls180.v:6090$1554 + attribute \src "ls180.v:4458.8-4458.121" + cell $and $and$ls180.v:4458$1306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6090$1552_Y - connect \B $eq$ls180.v:6090$1553_Y - connect \Y $and$ls180.v:6090$1554_Y + connect \A \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + connect \B \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \Y $and$ls180.v:4458$1306_Y end - attribute \src "ls180.v:6091.36-6091.92" - cell $and $and$ls180.v:6091$1556 + attribute \src "ls180.v:4458.7-4458.175" + cell $and $and$ls180.v:4458$1308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6091$1555_Y - connect \Y $and$ls180.v:6091$1556_Y + connect \A $and$ls180.v:4458$1306_Y + connect \B $not$ls180.v:4458$1307_Y + connect \Y $and$ls180.v:4458$1308_Y end - attribute \src "ls180.v:6091.35-6091.142" - cell $and $and$ls180.v:6091$1558 + attribute \src "ls180.v:4464.8-4464.121" + cell $and $and$ls180.v:4464$1311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6091$1556_Y - connect \B $eq$ls180.v:6091$1557_Y - connect \Y $and$ls180.v:6091$1558_Y + connect \A \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + connect \B \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \Y $and$ls180.v:4464$1311_Y end - attribute \src "ls180.v:6093.47-6093.100" - cell $and $and$ls180.v:6093$1559 + attribute \src "ls180.v:4464.7-4464.175" + cell $and $and$ls180.v:4464$1313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6093$1559_Y + connect \A $and$ls180.v:4464$1311_Y + connect \B $not$ls180.v:4464$1312_Y + connect \Y $and$ls180.v:4464$1313_Y end - attribute \src "ls180.v:6093.46-6093.150" - cell $and $and$ls180.v:6093$1561 + attribute \src "ls180.v:4504.8-4504.121" + cell $and $and$ls180.v:4504$1322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6093$1559_Y - connect \B $eq$ls180.v:6093$1560_Y - connect \Y $and$ls180.v:6093$1561_Y + connect \A \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + connect \B \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \Y $and$ls180.v:4504$1322_Y end - attribute \src "ls180.v:6094.47-6094.103" - cell $and $and$ls180.v:6094$1563 + attribute \src "ls180.v:4504.7-4504.175" + cell $and $and$ls180.v:4504$1324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6094$1562_Y - connect \Y $and$ls180.v:6094$1563_Y + connect \A $and$ls180.v:4504$1322_Y + connect \B $not$ls180.v:4504$1323_Y + connect \Y $and$ls180.v:4504$1324_Y end - attribute \src "ls180.v:6094.46-6094.153" - cell $and $and$ls180.v:6094$1565 + attribute \src "ls180.v:4510.8-4510.121" + cell $and $and$ls180.v:4510$1327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6094$1563_Y - connect \B $eq$ls180.v:6094$1564_Y - connect \Y $and$ls180.v:6094$1565_Y + connect \A \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + connect \B \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \Y $and$ls180.v:4510$1327_Y end - attribute \src "ls180.v:6096.47-6096.100" - cell $and $and$ls180.v:6096$1566 + attribute \src "ls180.v:4510.7-4510.175" + cell $and $and$ls180.v:4510$1329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6096$1566_Y + connect \A $and$ls180.v:4510$1327_Y + connect \B $not$ls180.v:4510$1328_Y + connect \Y $and$ls180.v:4510$1329_Y end - attribute \src "ls180.v:6096.46-6096.151" - cell $and $and$ls180.v:6096$1568 + attribute \src "ls180.v:4550.8-4550.121" + cell $and $and$ls180.v:4550$1338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6096$1566_Y - connect \B $eq$ls180.v:6096$1567_Y - connect \Y $and$ls180.v:6096$1568_Y + connect \A \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + connect \B \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \Y $and$ls180.v:4550$1338_Y end - attribute \src "ls180.v:6097.47-6097.103" - cell $and $and$ls180.v:6097$1570 + attribute \src "ls180.v:4550.7-4550.175" + cell $and $and$ls180.v:4550$1340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6097$1569_Y - connect \Y $and$ls180.v:6097$1570_Y + connect \A $and$ls180.v:4550$1338_Y + connect \B $not$ls180.v:4550$1339_Y + connect \Y $and$ls180.v:4550$1340_Y end - attribute \src "ls180.v:6097.46-6097.154" - cell $and $and$ls180.v:6097$1572 + attribute \src "ls180.v:4556.8-4556.121" + cell $and $and$ls180.v:4556$1343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6097$1570_Y - connect \B $eq$ls180.v:6097$1571_Y - connect \Y $and$ls180.v:6097$1572_Y + connect \A \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + connect \B \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \Y $and$ls180.v:4556$1343_Y end - attribute \src "ls180.v:6099.47-6099.100" - cell $and $and$ls180.v:6099$1573 + attribute \src "ls180.v:4556.7-4556.175" + cell $and $and$ls180.v:4556$1345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6099$1573_Y + connect \A $and$ls180.v:4556$1343_Y + connect \B $not$ls180.v:4556$1344_Y + connect \Y $and$ls180.v:4556$1345_Y end - attribute \src "ls180.v:6099.46-6099.151" - cell $and $and$ls180.v:6099$1575 + attribute \src "ls180.v:4596.8-4596.121" + cell $and $and$ls180.v:4596$1354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6099$1573_Y - connect \B $eq$ls180.v:6099$1574_Y - connect \Y $and$ls180.v:6099$1575_Y + connect \A \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + connect \B \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \Y $and$ls180.v:4596$1354_Y end - attribute \src "ls180.v:6100.47-6100.103" - cell $and $and$ls180.v:6100$1577 + attribute \src "ls180.v:4596.7-4596.175" + cell $and $and$ls180.v:4596$1356 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6100$1576_Y - connect \Y $and$ls180.v:6100$1577_Y + connect \A $and$ls180.v:4596$1354_Y + connect \B $not$ls180.v:4596$1355_Y + connect \Y $and$ls180.v:4596$1356_Y end - attribute \src "ls180.v:6100.46-6100.154" - cell $and $and$ls180.v:6100$1579 + attribute \src "ls180.v:4602.8-4602.121" + cell $and $and$ls180.v:4602$1359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6100$1577_Y - connect \B $eq$ls180.v:6100$1578_Y - connect \Y $and$ls180.v:6100$1579_Y + connect \A \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + connect \B \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \Y $and$ls180.v:4602$1359_Y end - attribute \src "ls180.v:6102.47-6102.100" - cell $and $and$ls180.v:6102$1580 + attribute \src "ls180.v:4602.7-4602.175" + cell $and $and$ls180.v:4602$1361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6102$1580_Y + connect \A $and$ls180.v:4602$1359_Y + connect \B $not$ls180.v:4602$1360_Y + connect \Y $and$ls180.v:4602$1361_Y end - attribute \src "ls180.v:6102.46-6102.151" - cell $and $and$ls180.v:6102$1582 + attribute \src "ls180.v:4799.53-4799.129" + cell $and $and$ls180.v:4799$1386 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6102$1580_Y - connect \B $eq$ls180.v:6102$1581_Y - connect \Y $and$ls180.v:6102$1582_Y + connect \A $eq$ls180.v:4799$1385_Y + connect \B \sdram_interface_bank0_wdata_ready + connect \Y $and$ls180.v:4799$1386_Y end - attribute \src "ls180.v:6103.47-6103.103" - cell $and $and$ls180.v:6103$1584 + attribute \src "ls180.v:4799.135-4799.211" + cell $and $and$ls180.v:4799$1389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6103$1583_Y - connect \Y $and$ls180.v:6103$1584_Y + connect \A $eq$ls180.v:4799$1388_Y + connect \B \sdram_interface_bank1_wdata_ready + connect \Y $and$ls180.v:4799$1389_Y end - attribute \src "ls180.v:6103.46-6103.154" - cell $and $and$ls180.v:6103$1586 + attribute \src "ls180.v:4799.217-4799.293" + cell $and $and$ls180.v:4799$1392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6103$1584_Y - connect \B $eq$ls180.v:6103$1585_Y - connect \Y $and$ls180.v:6103$1586_Y + connect \A $eq$ls180.v:4799$1391_Y + connect \B \sdram_interface_bank2_wdata_ready + connect \Y $and$ls180.v:4799$1392_Y end - attribute \src "ls180.v:6105.47-6105.100" - cell $and $and$ls180.v:6105$1587 + attribute \src "ls180.v:4799.299-4799.375" + cell $and $and$ls180.v:4799$1395 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6105$1587_Y + connect \A $eq$ls180.v:4799$1394_Y + connect \B \sdram_interface_bank3_wdata_ready + connect \Y $and$ls180.v:4799$1395_Y end - attribute \src "ls180.v:6105.46-6105.151" - cell $and $and$ls180.v:6105$1589 + attribute \src "ls180.v:4800.54-4800.130" + cell $and $and$ls180.v:4800$1398 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6105$1587_Y - connect \B $eq$ls180.v:6105$1588_Y - connect \Y $and$ls180.v:6105$1589_Y + connect \A $eq$ls180.v:4800$1397_Y + connect \B \sdram_interface_bank0_rdata_valid + connect \Y $and$ls180.v:4800$1398_Y end - attribute \src "ls180.v:6106.47-6106.103" - cell $and $and$ls180.v:6106$1591 + attribute \src "ls180.v:4800.136-4800.212" + cell $and $and$ls180.v:4800$1401 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6106$1590_Y - connect \Y $and$ls180.v:6106$1591_Y + connect \A $eq$ls180.v:4800$1400_Y + connect \B \sdram_interface_bank1_rdata_valid + connect \Y $and$ls180.v:4800$1401_Y end - attribute \src "ls180.v:6106.46-6106.154" - cell $and $and$ls180.v:6106$1593 + attribute \src "ls180.v:4800.218-4800.294" + cell $and $and$ls180.v:4800$1404 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6106$1591_Y - connect \B $eq$ls180.v:6106$1592_Y - connect \Y $and$ls180.v:6106$1593_Y + connect \A $eq$ls180.v:4800$1403_Y + connect \B \sdram_interface_bank2_rdata_valid + connect \Y $and$ls180.v:4800$1404_Y end - attribute \src "ls180.v:6108.47-6108.100" - cell $and $and$ls180.v:6108$1594 + attribute \src "ls180.v:4800.300-4800.376" + cell $and $and$ls180.v:4800$1407 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6108$1594_Y + connect \A $eq$ls180.v:4800$1406_Y + connect \B \sdram_interface_bank3_rdata_valid + connect \Y $and$ls180.v:4800$1407_Y end - attribute \src "ls180.v:6108.46-6108.151" - cell $and $and$ls180.v:6108$1596 + attribute \src "ls180.v:4819.8-4819.39" + cell $and $and$ls180.v:4819$1410 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6108$1594_Y - connect \B $eq$ls180.v:6108$1595_Y - connect \Y $and$ls180.v:6108$1596_Y + connect \A \port_cmd_valid + connect \B \port_cmd_ready + connect \Y $and$ls180.v:4819$1410_Y end - attribute \src "ls180.v:6109.47-6109.103" - cell $and $and$ls180.v:6109$1598 + attribute \src "ls180.v:4822.8-4822.43" + cell $and $and$ls180.v:4822$1411 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6109$1597_Y - connect \Y $and$ls180.v:6109$1598_Y + connect \A \port_wdata_valid + connect \B \port_wdata_ready + connect \Y $and$ls180.v:4822$1411_Y end - attribute \src "ls180.v:6109.46-6109.154" - cell $and $and$ls180.v:6109$1600 + attribute \src "ls180.v:4827.8-4827.49" + cell $and $and$ls180.v:4827$1413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6109$1598_Y - connect \B $eq$ls180.v:6109$1599_Y - connect \Y $and$ls180.v:6109$1600_Y + connect \A \uart_phy_sink_valid + connect \B $not$ls180.v:4827$1412_Y + connect \Y $and$ls180.v:4827$1413_Y end - attribute \src "ls180.v:6111.46-6111.99" - cell $and $and$ls180.v:6111$1601 + attribute \src "ls180.v:4827.7-4827.75" + cell $and $and$ls180.v:4827$1415 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6111$1601_Y + connect \A $and$ls180.v:4827$1413_Y + connect \B $not$ls180.v:4827$1414_Y + connect \Y $and$ls180.v:4827$1415_Y end - attribute \src "ls180.v:6111.45-6111.150" - cell $and $and$ls180.v:6111$1603 + attribute \src "ls180.v:4833.8-4833.49" + cell $and $and$ls180.v:4833$1416 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6111$1601_Y - connect \B $eq$ls180.v:6111$1602_Y - connect \Y $and$ls180.v:6111$1603_Y + connect \A \uart_phy_uart_clk_txen + connect \B \uart_phy_tx_busy + connect \Y $and$ls180.v:4833$1416_Y end - attribute \src "ls180.v:6112.46-6112.102" - cell $and $and$ls180.v:6112$1605 + attribute \src "ls180.v:4857.8-4857.38" + cell $and $and$ls180.v:4857$1423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6112$1604_Y - connect \Y $and$ls180.v:6112$1605_Y + connect \A $not$ls180.v:4857$1422_Y + connect \B \uart_phy_rx_r + connect \Y $and$ls180.v:4857$1423_Y end - attribute \src "ls180.v:6112.45-6112.153" - cell $and $and$ls180.v:6112$1607 + attribute \src "ls180.v:4890.7-4890.37" + cell $and $and$ls180.v:4890$1429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6112$1605_Y - connect \B $eq$ls180.v:6112$1606_Y - connect \Y $and$ls180.v:6112$1607_Y + connect \A $not$ls180.v:4890$1428_Y + connect \B \tx_old_trigger + connect \Y $and$ls180.v:4890$1429_Y end - attribute \src "ls180.v:6114.46-6114.99" - cell $and $and$ls180.v:6114$1608 + attribute \src "ls180.v:4897.7-4897.37" + cell $and $and$ls180.v:4897$1431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6114$1608_Y + connect \A $not$ls180.v:4897$1430_Y + connect \B \rx_old_trigger + connect \Y $and$ls180.v:4897$1431_Y end - attribute \src "ls180.v:6114.45-6114.150" - cell $and $and$ls180.v:6114$1610 + attribute \src "ls180.v:4907.8-4907.55" + cell $and $and$ls180.v:4907$1432 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6114$1608_Y - connect \B $eq$ls180.v:6114$1609_Y - connect \Y $and$ls180.v:6114$1610_Y + connect \A \tx_fifo_syncfifo_we + connect \B \tx_fifo_syncfifo_writable + connect \Y $and$ls180.v:4907$1432_Y end - attribute \src "ls180.v:6115.46-6115.102" - cell $and $and$ls180.v:6115$1612 + attribute \src "ls180.v:4907.7-4907.77" + cell $and $and$ls180.v:4907$1434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6115$1611_Y - connect \Y $and$ls180.v:6115$1612_Y + connect \A $and$ls180.v:4907$1432_Y + connect \B $not$ls180.v:4907$1433_Y + connect \Y $and$ls180.v:4907$1434_Y end - attribute \src "ls180.v:6115.45-6115.153" - cell $and $and$ls180.v:6115$1614 + attribute \src "ls180.v:4913.8-4913.55" + cell $and $and$ls180.v:4913$1437 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6115$1612_Y - connect \B $eq$ls180.v:6115$1613_Y - connect \Y $and$ls180.v:6115$1614_Y + connect \A \tx_fifo_syncfifo_we + connect \B \tx_fifo_syncfifo_writable + connect \Y $and$ls180.v:4913$1437_Y end - attribute \src "ls180.v:6117.46-6117.99" - cell $and $and$ls180.v:6117$1615 + attribute \src "ls180.v:4913.7-4913.77" + cell $and $and$ls180.v:4913$1439 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6117$1615_Y + connect \A $and$ls180.v:4913$1437_Y + connect \B $not$ls180.v:4913$1438_Y + connect \Y $and$ls180.v:4913$1439_Y end - attribute \src "ls180.v:6117.45-6117.150" - cell $and $and$ls180.v:6117$1617 + attribute \src "ls180.v:4929.8-4929.55" + cell $and $and$ls180.v:4929$1443 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6117$1615_Y - connect \B $eq$ls180.v:6117$1616_Y - connect \Y $and$ls180.v:6117$1617_Y + connect \A \rx_fifo_syncfifo_we + connect \B \rx_fifo_syncfifo_writable + connect \Y $and$ls180.v:4929$1443_Y end - attribute \src "ls180.v:6118.46-6118.102" - cell $and $and$ls180.v:6118$1619 + attribute \src "ls180.v:4929.7-4929.77" + cell $and $and$ls180.v:4929$1445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6118$1618_Y - connect \Y $and$ls180.v:6118$1619_Y + connect \A $and$ls180.v:4929$1443_Y + connect \B $not$ls180.v:4929$1444_Y + connect \Y $and$ls180.v:4929$1445_Y end - attribute \src "ls180.v:6118.45-6118.153" - cell $and $and$ls180.v:6118$1621 + attribute \src "ls180.v:4935.8-4935.55" + cell $and $and$ls180.v:4935$1448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6118$1619_Y - connect \B $eq$ls180.v:6118$1620_Y - connect \Y $and$ls180.v:6118$1621_Y + connect \A \rx_fifo_syncfifo_we + connect \B \rx_fifo_syncfifo_writable + connect \Y $and$ls180.v:4935$1448_Y end - attribute \src "ls180.v:6120.46-6120.99" - cell $and $and$ls180.v:6120$1622 + attribute \src "ls180.v:4935.7-4935.77" + cell $and $and$ls180.v:4935$1450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6120$1622_Y + connect \A $and$ls180.v:4935$1448_Y + connect \B $not$ls180.v:4935$1449_Y + connect \Y $and$ls180.v:4935$1450_Y end - attribute \src "ls180.v:6120.45-6120.150" - cell $and $and$ls180.v:6120$1624 + attribute \src "ls180.v:1550.25-1550.66" + cell $eq $eq$ls180.v:1550$28 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6120$1622_Y - connect \B $eq$ls180.v:6120$1623_Y - connect \Y $and$ls180.v:6120$1624_Y + connect \A \libresocsim_libresoc_xics_icp_sel + connect \B 1'0 + connect \Y $eq$ls180.v:1550$28_Y end - attribute \src "ls180.v:6121.46-6121.102" - cell $and $and$ls180.v:6121$1626 + attribute \src "ls180.v:1557.11-1557.37" + cell $eq $eq$ls180.v:1557$33 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6121$1625_Y - connect \Y $and$ls180.v:6121$1626_Y + connect \A \converter0_counter + connect \B 1'1 + connect \Y $eq$ls180.v:1557$33_Y end - attribute \src "ls180.v:6121.45-6121.153" - cell $and $and$ls180.v:6121$1628 + attribute \src "ls180.v:1610.25-1610.66" + cell $eq $eq$ls180.v:1610$39 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6121$1626_Y - connect \B $eq$ls180.v:6121$1627_Y - connect \Y $and$ls180.v:6121$1628_Y + connect \A \libresocsim_libresoc_xics_ics_sel + connect \B 1'0 + connect \Y $eq$ls180.v:1610$39_Y end - attribute \src "ls180.v:6123.46-6123.99" - cell $and $and$ls180.v:6123$1629 + attribute \src "ls180.v:1617.11-1617.37" + cell $eq $eq$ls180.v:1617$44 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6123$1629_Y + connect \A \converter1_counter + connect \B 1'1 + connect \Y $eq$ls180.v:1617$44_Y end - attribute \src "ls180.v:6123.45-6123.150" - cell $and $and$ls180.v:6123$1631 + attribute \src "ls180.v:1670.28-1670.48" + cell $eq $eq$ls180.v:1670$50 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6123$1629_Y - connect \B $eq$ls180.v:6123$1630_Y - connect \Y $and$ls180.v:6123$1631_Y + connect \A \wb_sdram_sel + connect \B 1'0 + connect \Y $eq$ls180.v:1670$50_Y end - attribute \src "ls180.v:6124.46-6124.102" - cell $and $and$ls180.v:6124$1633 + attribute \src "ls180.v:1677.11-1677.40" + cell $eq $eq$ls180.v:1677$55 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6124$1632_Y - connect \Y $and$ls180.v:6124$1633_Y + connect \A \socbushandler_counter + connect \B 1'1 + connect \Y $eq$ls180.v:1677$55_Y end - attribute \src "ls180.v:6124.45-6124.153" - cell $and $and$ls180.v:6124$1635 + attribute \src "ls180.v:1881.29-1881.55" + cell $eq $eq$ls180.v:1881$120 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6124$1633_Y - connect \B $eq$ls180.v:6124$1634_Y - connect \Y $and$ls180.v:6124$1635_Y + connect \A \sdram_timer_count1 + connect \B 1'0 + connect \Y $eq$ls180.v:1881$120_Y end - attribute \src "ls180.v:6126.46-6126.99" - cell $and $and$ls180.v:6126$1636 + attribute \src "ls180.v:1885.58-1885.87" + cell $eq $eq$ls180.v:1885$123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6126$1636_Y + connect \A \sdram_sequencer_count + connect \B 1'0 + connect \Y $eq$ls180.v:1885$123_Y end - attribute \src "ls180.v:6126.45-6126.150" - cell $and $and$ls180.v:6126$1638 + attribute \src "ls180.v:1929.38-1929.119" + cell $eq $eq$ls180.v:1929$128 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 13 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 13 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6126$1636_Y - connect \B $eq$ls180.v:6126$1637_Y - connect \Y $and$ls180.v:6126$1638_Y + connect \A \sdram_bankmachine0_row + connect \B \sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$ls180.v:1929$128_Y end - attribute \src "ls180.v:6127.46-6127.102" - cell $and $and$ls180.v:6127$1640 + attribute \src "ls180.v:1946.42-1946.78" + cell $eq $eq$ls180.v:1946$141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6127$1639_Y - connect \Y $and$ls180.v:6127$1640_Y + connect \A \sdram_bankmachine0_row_close + connect \B 1'0 + connect \Y $eq$ls180.v:1946$141_Y end - attribute \src "ls180.v:6127.45-6127.153" - cell $and $and$ls180.v:6127$1642 + attribute \src "ls180.v:2086.38-2086.119" + cell $eq $eq$ls180.v:2086$158 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 13 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 13 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6127$1640_Y - connect \B $eq$ls180.v:6127$1641_Y - connect \Y $and$ls180.v:6127$1642_Y + connect \A \sdram_bankmachine1_row + connect \B \sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$ls180.v:2086$158_Y end - attribute \src "ls180.v:6129.46-6129.99" - cell $and $and$ls180.v:6129$1643 + attribute \src "ls180.v:2103.42-2103.78" + cell $eq $eq$ls180.v:2103$171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6129$1643_Y + connect \A \sdram_bankmachine1_row_close + connect \B 1'0 + connect \Y $eq$ls180.v:2103$171_Y end - attribute \src "ls180.v:6129.45-6129.150" - cell $and $and$ls180.v:6129$1645 + attribute \src "ls180.v:2243.38-2243.119" + cell $eq $eq$ls180.v:2243$188 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 13 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 13 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6129$1643_Y - connect \B $eq$ls180.v:6129$1644_Y - connect \Y $and$ls180.v:6129$1645_Y + connect \A \sdram_bankmachine2_row + connect \B \sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$ls180.v:2243$188_Y end - attribute \src "ls180.v:6130.46-6130.102" - cell $and $and$ls180.v:6130$1647 + attribute \src "ls180.v:2260.42-2260.78" + cell $eq $eq$ls180.v:2260$201 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6130$1646_Y - connect \Y $and$ls180.v:6130$1647_Y + connect \A \sdram_bankmachine2_row_close + connect \B 1'0 + connect \Y $eq$ls180.v:2260$201_Y end - attribute \src "ls180.v:6130.45-6130.153" - cell $and $and$ls180.v:6130$1649 + attribute \src "ls180.v:2400.38-2400.119" + cell $eq $eq$ls180.v:2400$218 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 13 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 13 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6130$1647_Y - connect \B $eq$ls180.v:6130$1648_Y - connect \Y $and$ls180.v:6130$1649_Y + connect \A \sdram_bankmachine3_row + connect \B \sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$ls180.v:2400$218_Y end - attribute \src "ls180.v:6132.46-6132.99" - cell $and $and$ls180.v:6132$1650 + attribute \src "ls180.v:2417.42-2417.78" + cell $eq $eq$ls180.v:2417$231 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6132$1650_Y + connect \A \sdram_bankmachine3_row_close + connect \B 1'0 + connect \Y $eq$ls180.v:2417$231_Y end - attribute \src "ls180.v:6132.45-6132.150" - cell $and $and$ls180.v:6132$1652 + attribute \src "ls180.v:2554.27-2554.46" + cell $eq $eq$ls180.v:2554$278 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6132$1650_Y - connect \B $eq$ls180.v:6132$1651_Y - connect \Y $and$ls180.v:6132$1652_Y + connect \A \sdram_time0 + connect \B 1'0 + connect \Y $eq$ls180.v:2554$278_Y end - attribute \src "ls180.v:6133.46-6133.102" - cell $and $and$ls180.v:6133$1654 + attribute \src "ls180.v:2555.27-2555.46" + cell $eq $eq$ls180.v:2555$279 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6133$1653_Y - connect \Y $and$ls180.v:6133$1654_Y + connect \A \sdram_time1 + connect \B 1'0 + connect \Y $eq$ls180.v:2555$279_Y end - attribute \src "ls180.v:6133.45-6133.153" - cell $and $and$ls180.v:6133$1656 + attribute \src "ls180.v:2566.299-2566.368" + cell $eq $eq$ls180.v:2566$293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6133$1654_Y - connect \B $eq$ls180.v:6133$1655_Y - connect \Y $and$ls180.v:6133$1656_Y + connect \A \sdram_bankmachine0_cmd_payload_is_read + connect \B \sdram_choose_cmd_want_reads + connect \Y $eq$ls180.v:2566$293_Y end - attribute \src "ls180.v:6135.46-6135.99" - cell $and $and$ls180.v:6135$1657 + attribute \src "ls180.v:2566.373-2566.444" + cell $eq $eq$ls180.v:2566$294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6135$1657_Y + connect \A \sdram_bankmachine0_cmd_payload_is_write + connect \B \sdram_choose_cmd_want_writes + connect \Y $eq$ls180.v:2566$294_Y end - attribute \src "ls180.v:6135.45-6135.150" - cell $and $and$ls180.v:6135$1659 + attribute \src "ls180.v:2567.299-2567.368" + cell $eq $eq$ls180.v:2567$306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6135$1657_Y - connect \B $eq$ls180.v:6135$1658_Y - connect \Y $and$ls180.v:6135$1659_Y + connect \A \sdram_bankmachine1_cmd_payload_is_read + connect \B \sdram_choose_cmd_want_reads + connect \Y $eq$ls180.v:2567$306_Y end - attribute \src "ls180.v:6136.46-6136.102" - cell $and $and$ls180.v:6136$1661 + attribute \src "ls180.v:2567.373-2567.444" + cell $eq $eq$ls180.v:2567$307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6136$1660_Y - connect \Y $and$ls180.v:6136$1661_Y + connect \A \sdram_bankmachine1_cmd_payload_is_write + connect \B \sdram_choose_cmd_want_writes + connect \Y $eq$ls180.v:2567$307_Y end - attribute \src "ls180.v:6136.45-6136.153" - cell $and $and$ls180.v:6136$1663 + attribute \src "ls180.v:2568.299-2568.368" + cell $eq $eq$ls180.v:2568$319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6136$1661_Y - connect \B $eq$ls180.v:6136$1662_Y - connect \Y $and$ls180.v:6136$1663_Y + connect \A \sdram_bankmachine2_cmd_payload_is_read + connect \B \sdram_choose_cmd_want_reads + connect \Y $eq$ls180.v:2568$319_Y end - attribute \src "ls180.v:6138.46-6138.99" - cell $and $and$ls180.v:6138$1664 + attribute \src "ls180.v:2568.373-2568.444" + cell $eq $eq$ls180.v:2568$320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6138$1664_Y + connect \A \sdram_bankmachine2_cmd_payload_is_write + connect \B \sdram_choose_cmd_want_writes + connect \Y $eq$ls180.v:2568$320_Y end - attribute \src "ls180.v:6138.45-6138.150" - cell $and $and$ls180.v:6138$1666 + attribute \src "ls180.v:2569.299-2569.368" + cell $eq $eq$ls180.v:2569$332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6138$1664_Y - connect \B $eq$ls180.v:6138$1665_Y - connect \Y $and$ls180.v:6138$1666_Y + connect \A \sdram_bankmachine3_cmd_payload_is_read + connect \B \sdram_choose_cmd_want_reads + connect \Y $eq$ls180.v:2569$332_Y end - attribute \src "ls180.v:6139.46-6139.102" - cell $and $and$ls180.v:6139$1668 + attribute \src "ls180.v:2569.373-2569.444" + cell $eq $eq$ls180.v:2569$333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6139$1667_Y - connect \Y $and$ls180.v:6139$1668_Y + connect \A \sdram_bankmachine3_cmd_payload_is_write + connect \B \sdram_choose_cmd_want_writes + connect \Y $eq$ls180.v:2569$333_Y end - attribute \src "ls180.v:6139.45-6139.153" - cell $and $and$ls180.v:6139$1670 + attribute \src "ls180.v:2599.299-2599.368" + cell $eq $eq$ls180.v:2599$351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6139$1668_Y - connect \B $eq$ls180.v:6139$1669_Y - connect \Y $and$ls180.v:6139$1670_Y + connect \A \sdram_bankmachine0_cmd_payload_is_read + connect \B \sdram_choose_req_want_reads + connect \Y $eq$ls180.v:2599$351_Y end - attribute \src "ls180.v:6141.42-6141.95" - cell $and $and$ls180.v:6141$1671 + attribute \src "ls180.v:2599.373-2599.444" + cell $eq $eq$ls180.v:2599$352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6141$1671_Y + connect \A \sdram_bankmachine0_cmd_payload_is_write + connect \B \sdram_choose_req_want_writes + connect \Y $eq$ls180.v:2599$352_Y end - attribute \src "ls180.v:6141.41-6141.146" - cell $and $and$ls180.v:6141$1673 + attribute \src "ls180.v:2600.299-2600.368" + cell $eq $eq$ls180.v:2600$364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6141$1671_Y - connect \B $eq$ls180.v:6141$1672_Y - connect \Y $and$ls180.v:6141$1673_Y + connect \A \sdram_bankmachine1_cmd_payload_is_read + connect \B \sdram_choose_req_want_reads + connect \Y $eq$ls180.v:2600$364_Y end - attribute \src "ls180.v:6142.42-6142.98" - cell $and $and$ls180.v:6142$1675 + attribute \src "ls180.v:2600.373-2600.444" + cell $eq $eq$ls180.v:2600$365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6142$1674_Y - connect \Y $and$ls180.v:6142$1675_Y + connect \A \sdram_bankmachine1_cmd_payload_is_write + connect \B \sdram_choose_req_want_writes + connect \Y $eq$ls180.v:2600$365_Y end - attribute \src "ls180.v:6142.41-6142.149" - cell $and $and$ls180.v:6142$1677 + attribute \src "ls180.v:2601.299-2601.368" + cell $eq $eq$ls180.v:2601$377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6142$1675_Y - connect \B $eq$ls180.v:6142$1676_Y - connect \Y $and$ls180.v:6142$1677_Y + connect \A \sdram_bankmachine2_cmd_payload_is_read + connect \B \sdram_choose_req_want_reads + connect \Y $eq$ls180.v:2601$377_Y end - attribute \src "ls180.v:6144.43-6144.96" - cell $and $and$ls180.v:6144$1678 + attribute \src "ls180.v:2601.373-2601.444" + cell $eq $eq$ls180.v:2601$378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6144$1678_Y + connect \A \sdram_bankmachine2_cmd_payload_is_write + connect \B \sdram_choose_req_want_writes + connect \Y $eq$ls180.v:2601$378_Y end - attribute \src "ls180.v:6144.42-6144.147" - cell $and $and$ls180.v:6144$1680 + attribute \src "ls180.v:2602.299-2602.368" + cell $eq $eq$ls180.v:2602$390 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6144$1678_Y - connect \B $eq$ls180.v:6144$1679_Y - connect \Y $and$ls180.v:6144$1680_Y + connect \A \sdram_bankmachine3_cmd_payload_is_read + connect \B \sdram_choose_req_want_reads + connect \Y $eq$ls180.v:2602$390_Y end - attribute \src "ls180.v:6145.43-6145.99" - cell $and $and$ls180.v:6145$1682 + attribute \src "ls180.v:2602.373-2602.444" + cell $eq $eq$ls180.v:2602$391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6145$1681_Y - connect \Y $and$ls180.v:6145$1682_Y + connect \A \sdram_bankmachine3_cmd_payload_is_write + connect \B \sdram_choose_req_want_writes + connect \Y $eq$ls180.v:2602$391_Y end - attribute \src "ls180.v:6145.42-6145.150" - cell $and $and$ls180.v:6145$1684 + attribute \src "ls180.v:2631.68-2631.98" + cell $eq $eq$ls180.v:2631$400 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6145$1682_Y - connect \B $eq$ls180.v:6145$1683_Y - connect \Y $and$ls180.v:6145$1684_Y + connect \A \sdram_choose_cmd_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2631$400_Y end - attribute \src "ls180.v:6147.46-6147.99" - cell $and $and$ls180.v:6147$1685 + attribute \src "ls180.v:2634.68-2634.98" + cell $eq $eq$ls180.v:2634$403 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6147$1685_Y + connect \A \sdram_choose_req_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2634$403_Y end - attribute \src "ls180.v:6147.45-6147.150" - cell $and $and$ls180.v:6147$1687 + attribute \src "ls180.v:2640.68-2640.98" + cell $eq $eq$ls180.v:2640$407 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6147$1685_Y - connect \B $eq$ls180.v:6147$1686_Y - connect \Y $and$ls180.v:6147$1687_Y + connect \A \sdram_choose_cmd_grant + connect \B 1'1 + connect \Y $eq$ls180.v:2640$407_Y end - attribute \src "ls180.v:6148.46-6148.102" - cell $and $and$ls180.v:6148$1689 + attribute \src "ls180.v:2643.68-2643.98" + cell $eq $eq$ls180.v:2643$410 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6148$1688_Y - connect \Y $and$ls180.v:6148$1689_Y + connect \A \sdram_choose_req_grant + connect \B 1'1 + connect \Y $eq$ls180.v:2643$410_Y end - attribute \src "ls180.v:6148.45-6148.153" - cell $and $and$ls180.v:6148$1691 + attribute \src "ls180.v:2649.68-2649.98" + cell $eq $eq$ls180.v:2649$414 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6148$1689_Y - connect \B $eq$ls180.v:6148$1690_Y - connect \Y $and$ls180.v:6148$1691_Y + connect \A \sdram_choose_cmd_grant + connect \B 2'10 + connect \Y $eq$ls180.v:2649$414_Y end - attribute \src "ls180.v:6150.46-6150.99" - cell $and $and$ls180.v:6150$1692 + attribute \src "ls180.v:2652.68-2652.98" + cell $eq $eq$ls180.v:2652$417 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6150$1692_Y + connect \A \sdram_choose_req_grant + connect \B 2'10 + connect \Y $eq$ls180.v:2652$417_Y end - attribute \src "ls180.v:6150.45-6150.150" - cell $and $and$ls180.v:6150$1694 + attribute \src "ls180.v:2658.68-2658.98" + cell $eq $eq$ls180.v:2658$421 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6150$1692_Y - connect \B $eq$ls180.v:6150$1693_Y - connect \Y $and$ls180.v:6150$1694_Y + connect \A \sdram_choose_cmd_grant + connect \B 2'11 + connect \Y $eq$ls180.v:2658$421_Y end - attribute \src "ls180.v:6151.46-6151.102" - cell $and $and$ls180.v:6151$1696 + attribute \src "ls180.v:2661.68-2661.98" + cell $eq $eq$ls180.v:2661$424 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6151$1695_Y - connect \Y $and$ls180.v:6151$1696_Y + connect \A \sdram_choose_req_grant + connect \B 2'11 + connect \Y $eq$ls180.v:2661$424_Y end - attribute \src "ls180.v:6151.45-6151.153" - cell $and $and$ls180.v:6151$1698 + attribute \src "ls180.v:2742.47-2742.82" + cell $eq $eq$ls180.v:2742$447 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6151$1696_Y - connect \B $eq$ls180.v:6151$1697_Y - connect \Y $and$ls180.v:6151$1698_Y + connect \A \port_cmd_payload_addr [10:9] + connect \B 1'0 + connect \Y $eq$ls180.v:2742$447_Y end - attribute \src "ls180.v:6153.45-6153.98" - cell $and $and$ls180.v:6153$1699 + attribute \src "ls180.v:2742.145-2742.183" + cell $eq $eq$ls180.v:2742$448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6153$1699_Y + connect \A \subfragments_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2742$448_Y end - attribute \src "ls180.v:6153.44-6153.149" - cell $and $and$ls180.v:6153$1701 + attribute \src "ls180.v:2742.220-2742.258" + cell $eq $eq$ls180.v:2742$451 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6153$1699_Y - connect \B $eq$ls180.v:6153$1700_Y - connect \Y $and$ls180.v:6153$1701_Y + connect \A \subfragments_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2742$451_Y end - attribute \src "ls180.v:6154.45-6154.101" - cell $and $and$ls180.v:6154$1703 + attribute \src "ls180.v:2742.295-2742.333" + cell $eq $eq$ls180.v:2742$454 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6154$1702_Y - connect \Y $and$ls180.v:6154$1703_Y + connect \A \subfragments_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2742$454_Y end - attribute \src "ls180.v:6154.44-6154.152" - cell $and $and$ls180.v:6154$1705 + attribute \src "ls180.v:2747.47-2747.82" + cell $eq $eq$ls180.v:2747$463 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6154$1703_Y - connect \B $eq$ls180.v:6154$1704_Y - connect \Y $and$ls180.v:6154$1705_Y + connect \A \port_cmd_payload_addr [10:9] + connect \B 1'1 + connect \Y $eq$ls180.v:2747$463_Y end - attribute \src "ls180.v:6156.45-6156.98" - cell $and $and$ls180.v:6156$1706 + attribute \src "ls180.v:2747.145-2747.183" + cell $eq $eq$ls180.v:2747$464 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6156$1706_Y + connect \A \subfragments_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2747$464_Y end - attribute \src "ls180.v:6156.44-6156.149" - cell $and $and$ls180.v:6156$1708 + attribute \src "ls180.v:2747.220-2747.258" + cell $eq $eq$ls180.v:2747$467 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6156$1706_Y - connect \B $eq$ls180.v:6156$1707_Y - connect \Y $and$ls180.v:6156$1708_Y + connect \A \subfragments_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2747$467_Y end - attribute \src "ls180.v:6157.45-6157.101" - cell $and $and$ls180.v:6157$1710 + attribute \src "ls180.v:2747.295-2747.333" + cell $eq $eq$ls180.v:2747$470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6157$1709_Y - connect \Y $and$ls180.v:6157$1710_Y + connect \A \subfragments_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2747$470_Y end - attribute \src "ls180.v:6157.44-6157.152" - cell $and $and$ls180.v:6157$1712 + attribute \src "ls180.v:2752.47-2752.82" + cell $eq $eq$ls180.v:2752$479 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6157$1710_Y - connect \B $eq$ls180.v:6157$1711_Y - connect \Y $and$ls180.v:6157$1712_Y + connect \A \port_cmd_payload_addr [10:9] + connect \B 2'10 + connect \Y $eq$ls180.v:2752$479_Y end - attribute \src "ls180.v:6159.45-6159.98" - cell $and $and$ls180.v:6159$1713 + attribute \src "ls180.v:2752.145-2752.183" + cell $eq $eq$ls180.v:2752$480 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6159$1713_Y + connect \A \subfragments_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2752$480_Y end - attribute \src "ls180.v:6159.44-6159.149" - cell $and $and$ls180.v:6159$1715 + attribute \src "ls180.v:2752.220-2752.258" + cell $eq $eq$ls180.v:2752$483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6159$1713_Y - connect \B $eq$ls180.v:6159$1714_Y - connect \Y $and$ls180.v:6159$1715_Y + connect \A \subfragments_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2752$483_Y end - attribute \src "ls180.v:6160.45-6160.101" - cell $and $and$ls180.v:6160$1717 + attribute \src "ls180.v:2752.295-2752.333" + cell $eq $eq$ls180.v:2752$486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6160$1716_Y - connect \Y $and$ls180.v:6160$1717_Y + connect \A \subfragments_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2752$486_Y end - attribute \src "ls180.v:6160.44-6160.152" - cell $and $and$ls180.v:6160$1719 + attribute \src "ls180.v:2757.47-2757.82" + cell $eq $eq$ls180.v:2757$495 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6160$1717_Y - connect \B $eq$ls180.v:6160$1718_Y - connect \Y $and$ls180.v:6160$1719_Y + connect \A \port_cmd_payload_addr [10:9] + connect \B 2'11 + connect \Y $eq$ls180.v:2757$495_Y end - attribute \src "ls180.v:6162.45-6162.98" - cell $and $and$ls180.v:6162$1720 + attribute \src "ls180.v:2757.145-2757.183" + cell $eq $eq$ls180.v:2757$496 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B \builder_interface6_bank_bus_we - connect \Y $and$ls180.v:6162$1720_Y + connect \A \subfragments_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2757$496_Y end - attribute \src "ls180.v:6162.44-6162.149" - cell $and $and$ls180.v:6162$1722 + attribute \src "ls180.v:2757.220-2757.258" + cell $eq $eq$ls180.v:2757$499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6162$1720_Y - connect \B $eq$ls180.v:6162$1721_Y - connect \Y $and$ls180.v:6162$1722_Y + connect \A \subfragments_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2757$499_Y end - attribute \src "ls180.v:6163.45-6163.101" - cell $and $and$ls180.v:6163$1724 + attribute \src "ls180.v:2757.295-2757.333" + cell $eq $eq$ls180.v:2757$502 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank6_sel - connect \B $not$ls180.v:6163$1723_Y - connect \Y $and$ls180.v:6163$1724_Y + connect \A \subfragments_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2757$502_Y end - attribute \src "ls180.v:6163.44-6163.152" - cell $and $and$ls180.v:6163$1726 + attribute \src "ls180.v:2762.39-2762.77" + cell $eq $eq$ls180.v:2762$511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6163$1724_Y - connect \B $eq$ls180.v:6163$1725_Y - connect \Y $and$ls180.v:6163$1726_Y + connect \A \subfragments_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2762$511_Y end - attribute \src "ls180.v:6201.42-6201.95" - cell $and $and$ls180.v:6201$1728 + attribute \src "ls180.v:2762.83-2762.118" + cell $eq $eq$ls180.v:2762$512 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6201$1728_Y + connect \A \port_cmd_payload_addr [10:9] + connect \B 1'0 + connect \Y $eq$ls180.v:2762$512_Y end - attribute \src "ls180.v:6201.41-6201.145" - cell $and $and$ls180.v:6201$1730 + attribute \src "ls180.v:2762.181-2762.219" + cell $eq $eq$ls180.v:2762$513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6201$1728_Y - connect \B $eq$ls180.v:6201$1729_Y - connect \Y $and$ls180.v:6201$1730_Y + connect \A \subfragments_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2762$513_Y end - attribute \src "ls180.v:6202.42-6202.98" - cell $and $and$ls180.v:6202$1732 + attribute \src "ls180.v:2762.256-2762.294" + cell $eq $eq$ls180.v:2762$516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6202$1731_Y - connect \Y $and$ls180.v:6202$1732_Y + connect \A \subfragments_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2762$516_Y end - attribute \src "ls180.v:6202.41-6202.148" - cell $and $and$ls180.v:6202$1734 + attribute \src "ls180.v:2762.331-2762.369" + cell $eq $eq$ls180.v:2762$519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6202$1732_Y - connect \B $eq$ls180.v:6202$1733_Y - connect \Y $and$ls180.v:6202$1734_Y + connect \A \subfragments_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2762$519_Y end - attribute \src "ls180.v:6204.42-6204.95" - cell $and $and$ls180.v:6204$1735 + attribute \src "ls180.v:2762.413-2762.451" + cell $eq $eq$ls180.v:2762$527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6204$1735_Y + connect \A \subfragments_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2762$527_Y end - attribute \src "ls180.v:6204.41-6204.145" - cell $and $and$ls180.v:6204$1737 + attribute \src "ls180.v:2762.457-2762.492" + cell $eq $eq$ls180.v:2762$528 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6204$1735_Y - connect \B $eq$ls180.v:6204$1736_Y - connect \Y $and$ls180.v:6204$1737_Y + connect \A \port_cmd_payload_addr [10:9] + connect \B 1'1 + connect \Y $eq$ls180.v:2762$528_Y end - attribute \src "ls180.v:6205.42-6205.98" - cell $and $and$ls180.v:6205$1739 + attribute \src "ls180.v:2762.555-2762.593" + cell $eq $eq$ls180.v:2762$529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6205$1738_Y - connect \Y $and$ls180.v:6205$1739_Y + connect \A \subfragments_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2762$529_Y end - attribute \src "ls180.v:6205.41-6205.148" - cell $and $and$ls180.v:6205$1741 + attribute \src "ls180.v:2762.630-2762.668" + cell $eq $eq$ls180.v:2762$532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6205$1739_Y - connect \B $eq$ls180.v:6205$1740_Y - connect \Y $and$ls180.v:6205$1741_Y + connect \A \subfragments_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2762$532_Y end - attribute \src "ls180.v:6207.42-6207.95" - cell $and $and$ls180.v:6207$1742 + attribute \src "ls180.v:2762.705-2762.743" + cell $eq $eq$ls180.v:2762$535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6207$1742_Y + connect \A \subfragments_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2762$535_Y end - attribute \src "ls180.v:6207.41-6207.145" - cell $and $and$ls180.v:6207$1744 + attribute \src "ls180.v:2762.787-2762.825" + cell $eq $eq$ls180.v:2762$543 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6207$1742_Y - connect \B $eq$ls180.v:6207$1743_Y - connect \Y $and$ls180.v:6207$1744_Y + connect \A \subfragments_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2762$543_Y end - attribute \src "ls180.v:6208.42-6208.98" - cell $and $and$ls180.v:6208$1746 + attribute \src "ls180.v:2762.831-2762.866" + cell $eq $eq$ls180.v:2762$544 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6208$1745_Y - connect \Y $and$ls180.v:6208$1746_Y + connect \A \port_cmd_payload_addr [10:9] + connect \B 2'10 + connect \Y $eq$ls180.v:2762$544_Y end - attribute \src "ls180.v:6208.41-6208.148" - cell $and $and$ls180.v:6208$1748 + attribute \src "ls180.v:2762.929-2762.967" + cell $eq $eq$ls180.v:2762$545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6208$1746_Y - connect \B $eq$ls180.v:6208$1747_Y - connect \Y $and$ls180.v:6208$1748_Y + connect \A \subfragments_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2762$545_Y end - attribute \src "ls180.v:6210.42-6210.95" - cell $and $and$ls180.v:6210$1749 + attribute \src "ls180.v:2762.1004-2762.1042" + cell $eq $eq$ls180.v:2762$548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6210$1749_Y + connect \A \subfragments_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2762$548_Y end - attribute \src "ls180.v:6210.41-6210.145" - cell $and $and$ls180.v:6210$1751 + attribute \src "ls180.v:2762.1079-2762.1117" + cell $eq $eq$ls180.v:2762$551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6210$1749_Y - connect \B $eq$ls180.v:6210$1750_Y - connect \Y $and$ls180.v:6210$1751_Y + connect \A \subfragments_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2762$551_Y end - attribute \src "ls180.v:6211.42-6211.98" - cell $and $and$ls180.v:6211$1753 + attribute \src "ls180.v:2762.1161-2762.1199" + cell $eq $eq$ls180.v:2762$559 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6211$1752_Y - connect \Y $and$ls180.v:6211$1753_Y + connect \A \subfragments_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2762$559_Y end - attribute \src "ls180.v:6211.41-6211.148" - cell $and $and$ls180.v:6211$1755 + attribute \src "ls180.v:2762.1205-2762.1240" + cell $eq $eq$ls180.v:2762$560 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6211$1753_Y - connect \B $eq$ls180.v:6211$1754_Y - connect \Y $and$ls180.v:6211$1755_Y + connect \A \port_cmd_payload_addr [10:9] + connect \B 2'11 + connect \Y $eq$ls180.v:2762$560_Y end - attribute \src "ls180.v:6213.42-6213.95" - cell $and $and$ls180.v:6213$1756 + attribute \src "ls180.v:2762.1303-2762.1341" + cell $eq $eq$ls180.v:2762$561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6213$1756_Y + connect \A \subfragments_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2762$561_Y end - attribute \src "ls180.v:6213.41-6213.145" - cell $and $and$ls180.v:6213$1758 + attribute \src "ls180.v:2762.1378-2762.1416" + cell $eq $eq$ls180.v:2762$564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6213$1756_Y - connect \B $eq$ls180.v:6213$1757_Y - connect \Y $and$ls180.v:6213$1758_Y + connect \A \subfragments_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2762$564_Y end - attribute \src "ls180.v:6214.42-6214.98" - cell $and $and$ls180.v:6214$1760 + attribute \src "ls180.v:2762.1453-2762.1491" + cell $eq $eq$ls180.v:2762$567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6214$1759_Y - connect \Y $and$ls180.v:6214$1760_Y + connect \A \subfragments_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:2762$567_Y end - attribute \src "ls180.v:6214.41-6214.148" - cell $and $and$ls180.v:6214$1762 + attribute \src "ls180.v:2821.24-2821.47" + cell $eq $eq$ls180.v:2821$580 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6214$1760_Y - connect \B $eq$ls180.v:6214$1761_Y - connect \Y $and$ls180.v:6214$1762_Y + connect \A \litedram_wb_sel + connect \B 1'0 + connect \Y $eq$ls180.v:2821$580_Y end - attribute \src "ls180.v:6216.42-6216.95" - cell $and $and$ls180.v:6216$1763 + attribute \src "ls180.v:2828.11-2828.36" + cell $eq $eq$ls180.v:2828$585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6216$1763_Y + connect \A \converter_counter + connect \B 1'1 + connect \Y $eq$ls180.v:2828$585_Y end - attribute \src "ls180.v:6216.41-6216.145" - cell $and $and$ls180.v:6216$1765 + attribute \src "ls180.v:3085.67-3085.92" + cell $eq $eq$ls180.v:3085$657 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6216$1763_Y - connect \B $eq$ls180.v:6216$1764_Y - connect \Y $and$ls180.v:6216$1765_Y + connect \A \libresocsim_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3085$657_Y end - attribute \src "ls180.v:6217.42-6217.98" - cell $and $and$ls180.v:6217$1767 + attribute \src "ls180.v:3086.67-3086.92" + cell $eq $eq$ls180.v:3086$659 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6217$1766_Y - connect \Y $and$ls180.v:6217$1767_Y + connect \A \libresocsim_grant + connect \B 1'1 + connect \Y $eq$ls180.v:3086$659_Y end - attribute \src "ls180.v:6217.41-6217.148" - cell $and $and$ls180.v:6217$1769 + attribute \src "ls180.v:3087.70-3087.95" + cell $eq $eq$ls180.v:3087$661 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6217$1767_Y - connect \B $eq$ls180.v:6217$1768_Y - connect \Y $and$ls180.v:6217$1769_Y + connect \A \libresocsim_grant + connect \B 2'10 + connect \Y $eq$ls180.v:3087$661_Y end - attribute \src "ls180.v:6219.42-6219.95" - cell $and $and$ls180.v:6219$1770 + attribute \src "ls180.v:3088.67-3088.92" + cell $eq $eq$ls180.v:3088$663 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6219$1770_Y + connect \A \libresocsim_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3088$663_Y end - attribute \src "ls180.v:6219.41-6219.145" - cell $and $and$ls180.v:6219$1772 + attribute \src "ls180.v:3089.67-3089.92" + cell $eq $eq$ls180.v:3089$665 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6219$1770_Y - connect \B $eq$ls180.v:6219$1771_Y - connect \Y $and$ls180.v:6219$1772_Y + connect \A \libresocsim_grant + connect \B 1'1 + connect \Y $eq$ls180.v:3089$665_Y end - attribute \src "ls180.v:6220.42-6220.98" - cell $and $and$ls180.v:6220$1774 + attribute \src "ls180.v:3090.70-3090.95" + cell $eq $eq$ls180.v:3090$667 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6220$1773_Y - connect \Y $and$ls180.v:6220$1774_Y + connect \A \libresocsim_grant + connect \B 2'10 + connect \Y $eq$ls180.v:3090$667_Y end - attribute \src "ls180.v:6220.41-6220.148" - cell $and $and$ls180.v:6220$1776 + attribute \src "ls180.v:3094.31-3094.67" + cell $eq $eq$ls180.v:3094$670 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 24 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6220$1774_Y - connect \B $eq$ls180.v:6220$1775_Y - connect \Y $and$ls180.v:6220$1776_Y + connect \A \libresocsim_shared_adr [29:6] + connect \B 1'0 + connect \Y $eq$ls180.v:3094$670_Y end - attribute \src "ls180.v:6222.42-6222.95" - cell $and $and$ls180.v:6222$1777 + attribute \src "ls180.v:3095.31-3095.68" + cell $eq $eq$ls180.v:3095$671 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 26 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6222$1777_Y + connect \A \libresocsim_shared_adr [29:4] + connect \B 4'1110 + connect \Y $eq$ls180.v:3095$671_Y end - attribute \src "ls180.v:6222.41-6222.145" - cell $and $and$ls180.v:6222$1779 + attribute \src "ls180.v:3096.31-3096.76" + cell $eq $eq$ls180.v:3096$672 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 28 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 27 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6222$1777_Y - connect \B $eq$ls180.v:6222$1778_Y - connect \Y $and$ls180.v:6222$1779_Y + connect \A \libresocsim_shared_adr [29:2] + connect \B 27'110000000000000100000000000 + connect \Y $eq$ls180.v:3096$672_Y end - attribute \src "ls180.v:6223.42-6223.98" - cell $and $and$ls180.v:6223$1781 + attribute \src "ls180.v:3097.31-3097.73" + cell $eq $eq$ls180.v:3097$673 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 21 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 20 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6223$1780_Y - connect \Y $and$ls180.v:6223$1781_Y + connect \A \libresocsim_shared_adr [29:9] + connect \B 20'11000000000000010001 + connect \Y $eq$ls180.v:3097$673_Y end - attribute \src "ls180.v:6223.41-6223.148" - cell $and $and$ls180.v:6223$1783 + attribute \src "ls180.v:3098.31-3098.69" + cell $eq $eq$ls180.v:3098$674 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 8 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 7 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6223$1781_Y - connect \B $eq$ls180.v:6223$1782_Y - connect \Y $and$ls180.v:6223$1783_Y + connect \A \libresocsim_shared_adr [29:22] + connect \B 7'1001000 + connect \Y $eq$ls180.v:3098$674_Y end - attribute \src "ls180.v:6225.44-6225.97" - cell $and $and$ls180.v:6225$1784 + attribute \src "ls180.v:3099.31-3099.73" + cell $eq $eq$ls180.v:3099$675 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 17 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 16 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6225$1784_Y + connect \A \libresocsim_shared_adr [29:13] + connect \B 16'1100000000000000 + connect \Y $eq$ls180.v:3099$675_Y end - attribute \src "ls180.v:6225.43-6225.147" - cell $and $and$ls180.v:6225$1786 + attribute \src "ls180.v:3163.28-3163.53" + cell $eq $eq$ls180.v:3163$707 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 20 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6225$1784_Y - connect \B $eq$ls180.v:6225$1785_Y - connect \Y $and$ls180.v:6225$1786_Y + connect \A \libresocsim_count + connect \B 1'0 + connect \Y $eq$ls180.v:3163$707_Y end - attribute \src "ls180.v:6226.44-6226.100" - cell $and $and$ls180.v:6226$1788 + attribute \src "ls180.v:3164.36-3164.85" + cell $eq $eq$ls180.v:3164$708 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6226$1787_Y - connect \Y $and$ls180.v:6226$1788_Y + connect \A \libresocsim_interface0_bank_bus_adr [13:8] + connect \B 1'0 + connect \Y $eq$ls180.v:3164$708_Y end - attribute \src "ls180.v:6226.43-6226.150" - cell $and $and$ls180.v:6226$1790 + attribute \src "ls180.v:3166.109-3166.157" + cell $eq $eq$ls180.v:3166$710 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6226$1788_Y - connect \B $eq$ls180.v:6226$1789_Y - connect \Y $and$ls180.v:6226$1790_Y + connect \A \libresocsim_interface0_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:3166$710_Y end - attribute \src "ls180.v:6228.44-6228.97" - cell $and $and$ls180.v:6228$1791 + attribute \src "ls180.v:3167.112-3167.160" + cell $eq $eq$ls180.v:3167$714 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6228$1791_Y + connect \A \libresocsim_interface0_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:3167$714_Y end - attribute \src "ls180.v:6228.43-6228.147" - cell $and $and$ls180.v:6228$1793 + attribute \src "ls180.v:3169.111-3169.159" + cell $eq $eq$ls180.v:3169$717 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6228$1791_Y - connect \B $eq$ls180.v:6228$1792_Y - connect \Y $and$ls180.v:6228$1793_Y + connect \A \libresocsim_interface0_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:3169$717_Y end - attribute \src "ls180.v:6229.44-6229.100" - cell $and $and$ls180.v:6229$1795 + attribute \src "ls180.v:3170.114-3170.162" + cell $eq $eq$ls180.v:3170$721 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6229$1794_Y - connect \Y $and$ls180.v:6229$1795_Y + connect \A \libresocsim_interface0_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:3170$721_Y end - attribute \src "ls180.v:6229.43-6229.150" - cell $and $and$ls180.v:6229$1797 + attribute \src "ls180.v:3172.111-3172.159" + cell $eq $eq$ls180.v:3172$724 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6229$1795_Y - connect \B $eq$ls180.v:6229$1796_Y - connect \Y $and$ls180.v:6229$1797_Y + connect \A \libresocsim_interface0_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:3172$724_Y end - attribute \src "ls180.v:6231.44-6231.97" - cell $and $and$ls180.v:6231$1798 + attribute \src "ls180.v:3173.114-3173.162" + cell $eq $eq$ls180.v:3173$728 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6231$1798_Y + connect \A \libresocsim_interface0_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:3173$728_Y end - attribute \src "ls180.v:6231.43-6231.148" - cell $and $and$ls180.v:6231$1800 + attribute \src "ls180.v:3175.111-3175.159" + cell $eq $eq$ls180.v:3175$731 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6231$1798_Y - connect \B $eq$ls180.v:6231$1799_Y - connect \Y $and$ls180.v:6231$1800_Y + connect \A \libresocsim_interface0_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:3175$731_Y end - attribute \src "ls180.v:6232.44-6232.100" - cell $and $and$ls180.v:6232$1802 + attribute \src "ls180.v:3176.114-3176.162" + cell $eq $eq$ls180.v:3176$735 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6232$1801_Y - connect \Y $and$ls180.v:6232$1802_Y + connect \A \libresocsim_interface0_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:3176$735_Y end - attribute \src "ls180.v:6232.43-6232.151" - cell $and $and$ls180.v:6232$1804 + attribute \src "ls180.v:3178.111-3178.159" + cell $eq $eq$ls180.v:3178$738 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6232$1802_Y - connect \B $eq$ls180.v:6232$1803_Y - connect \Y $and$ls180.v:6232$1804_Y + connect \A \libresocsim_interface0_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:3178$738_Y end - attribute \src "ls180.v:6234.44-6234.97" - cell $and $and$ls180.v:6234$1805 + attribute \src "ls180.v:3179.114-3179.162" + cell $eq $eq$ls180.v:3179$742 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6234$1805_Y + connect \A \libresocsim_interface0_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:3179$742_Y end - attribute \src "ls180.v:6234.43-6234.148" - cell $and $and$ls180.v:6234$1807 + attribute \src "ls180.v:3181.114-3181.162" + cell $eq $eq$ls180.v:3181$745 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6234$1805_Y - connect \B $eq$ls180.v:6234$1806_Y - connect \Y $and$ls180.v:6234$1807_Y + connect \A \libresocsim_interface0_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:3181$745_Y end - attribute \src "ls180.v:6235.44-6235.100" - cell $and $and$ls180.v:6235$1809 + attribute \src "ls180.v:3182.117-3182.165" + cell $eq $eq$ls180.v:3182$749 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6235$1808_Y - connect \Y $and$ls180.v:6235$1809_Y + connect \A \libresocsim_interface0_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:3182$749_Y end - attribute \src "ls180.v:6235.43-6235.151" - cell $and $and$ls180.v:6235$1811 + attribute \src "ls180.v:3184.114-3184.162" + cell $eq $eq$ls180.v:3184$752 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6235$1809_Y - connect \B $eq$ls180.v:6235$1810_Y - connect \Y $and$ls180.v:6235$1811_Y + connect \A \libresocsim_interface0_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:3184$752_Y end - attribute \src "ls180.v:6237.44-6237.97" - cell $and $and$ls180.v:6237$1812 + attribute \src "ls180.v:3185.117-3185.165" + cell $eq $eq$ls180.v:3185$756 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6237$1812_Y + connect \A \libresocsim_interface0_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:3185$756_Y end - attribute \src "ls180.v:6237.43-6237.148" - cell $and $and$ls180.v:6237$1814 + attribute \src "ls180.v:3187.114-3187.162" + cell $eq $eq$ls180.v:3187$759 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6237$1812_Y - connect \B $eq$ls180.v:6237$1813_Y - connect \Y $and$ls180.v:6237$1814_Y + connect \A \libresocsim_interface0_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:3187$759_Y end - attribute \src "ls180.v:6238.44-6238.100" - cell $and $and$ls180.v:6238$1816 + attribute \src "ls180.v:3188.117-3188.165" + cell $eq $eq$ls180.v:3188$763 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6238$1815_Y - connect \Y $and$ls180.v:6238$1816_Y + connect \A \libresocsim_interface0_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:3188$763_Y end - attribute \src "ls180.v:6238.43-6238.151" - cell $and $and$ls180.v:6238$1818 + attribute \src "ls180.v:3190.114-3190.162" + cell $eq $eq$ls180.v:3190$766 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6238$1816_Y - connect \B $eq$ls180.v:6238$1817_Y - connect \Y $and$ls180.v:6238$1818_Y + connect \A \libresocsim_interface0_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:3190$766_Y end - attribute \src "ls180.v:6240.41-6240.94" - cell $and $and$ls180.v:6240$1819 + attribute \src "ls180.v:3191.117-3191.165" + cell $eq $eq$ls180.v:3191$770 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6240$1819_Y + connect \A \libresocsim_interface0_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:3191$770_Y end - attribute \src "ls180.v:6240.40-6240.145" - cell $and $and$ls180.v:6240$1821 + attribute \src "ls180.v:3202.36-3202.85" + cell $eq $eq$ls180.v:3202$772 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6240$1819_Y - connect \B $eq$ls180.v:6240$1820_Y - connect \Y $and$ls180.v:6240$1821_Y + connect \A \libresocsim_interface1_bank_bus_adr [13:8] + connect \B 3'110 + connect \Y $eq$ls180.v:3202$772_Y end - attribute \src "ls180.v:6241.41-6241.97" - cell $and $and$ls180.v:6241$1823 + attribute \src "ls180.v:3204.106-3204.154" + cell $eq $eq$ls180.v:3204$774 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6241$1822_Y - connect \Y $and$ls180.v:6241$1823_Y + connect \A \libresocsim_interface1_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:3204$774_Y end - attribute \src "ls180.v:6241.40-6241.148" - cell $and $and$ls180.v:6241$1825 + attribute \src "ls180.v:3205.109-3205.157" + cell $eq $eq$ls180.v:3205$778 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6241$1823_Y - connect \B $eq$ls180.v:6241$1824_Y - connect \Y $and$ls180.v:6241$1825_Y + connect \A \libresocsim_interface1_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:3205$778_Y end - attribute \src "ls180.v:6243.42-6243.95" - cell $and $and$ls180.v:6243$1826 + attribute \src "ls180.v:3207.105-3207.153" + cell $eq $eq$ls180.v:3207$781 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6243$1826_Y + connect \A \libresocsim_interface1_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:3207$781_Y end - attribute \src "ls180.v:6243.41-6243.146" - cell $and $and$ls180.v:6243$1828 + attribute \src "ls180.v:3208.108-3208.156" + cell $eq $eq$ls180.v:3208$785 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6243$1826_Y - connect \B $eq$ls180.v:6243$1827_Y - connect \Y $and$ls180.v:6243$1828_Y + connect \A \libresocsim_interface1_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:3208$785_Y end - attribute \src "ls180.v:6244.42-6244.98" - cell $and $and$ls180.v:6244$1830 + attribute \src "ls180.v:3210.107-3210.155" + cell $eq $eq$ls180.v:3210$788 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6244$1829_Y - connect \Y $and$ls180.v:6244$1830_Y + connect \A \libresocsim_interface1_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:3210$788_Y end - attribute \src "ls180.v:6244.41-6244.149" - cell $and $and$ls180.v:6244$1832 + attribute \src "ls180.v:3211.110-3211.158" + cell $eq $eq$ls180.v:3211$792 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6244$1830_Y - connect \B $eq$ls180.v:6244$1831_Y - connect \Y $and$ls180.v:6244$1832_Y + connect \A \libresocsim_interface1_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:3211$792_Y end - attribute \src "ls180.v:6246.44-6246.97" - cell $and $and$ls180.v:6246$1833 + attribute \src "ls180.v:3216.36-3216.85" + cell $eq $eq$ls180.v:3216$794 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6246$1833_Y + connect \A \libresocsim_interface2_bank_bus_adr [13:8] + connect \B 3'111 + connect \Y $eq$ls180.v:3216$794_Y end - attribute \src "ls180.v:6246.43-6246.148" - cell $and $and$ls180.v:6246$1835 + attribute \src "ls180.v:3218.106-3218.154" + cell $eq $eq$ls180.v:3218$796 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6246$1833_Y - connect \B $eq$ls180.v:6246$1834_Y - connect \Y $and$ls180.v:6246$1835_Y + connect \A \libresocsim_interface2_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:3218$796_Y end - attribute \src "ls180.v:6247.44-6247.100" - cell $and $and$ls180.v:6247$1837 + attribute \src "ls180.v:3219.109-3219.157" + cell $eq $eq$ls180.v:3219$800 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6247$1836_Y - connect \Y $and$ls180.v:6247$1837_Y + connect \A \libresocsim_interface2_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:3219$800_Y end - attribute \src "ls180.v:6247.43-6247.151" - cell $and $and$ls180.v:6247$1839 + attribute \src "ls180.v:3221.105-3221.153" + cell $eq $eq$ls180.v:3221$803 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6247$1837_Y - connect \B $eq$ls180.v:6247$1838_Y - connect \Y $and$ls180.v:6247$1839_Y + connect \A \libresocsim_interface2_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:3221$803_Y end - attribute \src "ls180.v:6249.44-6249.97" - cell $and $and$ls180.v:6249$1840 + attribute \src "ls180.v:3222.108-3222.156" + cell $eq $eq$ls180.v:3222$807 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6249$1840_Y + connect \A \libresocsim_interface2_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:3222$807_Y end - attribute \src "ls180.v:6249.43-6249.148" - cell $and $and$ls180.v:6249$1842 + attribute \src "ls180.v:3224.107-3224.155" + cell $eq $eq$ls180.v:3224$810 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6249$1840_Y - connect \B $eq$ls180.v:6249$1841_Y - connect \Y $and$ls180.v:6249$1842_Y + connect \A \libresocsim_interface2_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:3224$810_Y end - attribute \src "ls180.v:6250.44-6250.100" - cell $and $and$ls180.v:6250$1844 + attribute \src "ls180.v:3225.110-3225.158" + cell $eq $eq$ls180.v:3225$814 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6250$1843_Y - connect \Y $and$ls180.v:6250$1844_Y + connect \A \libresocsim_interface2_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:3225$814_Y end - attribute \src "ls180.v:6250.43-6250.151" - cell $and $and$ls180.v:6250$1846 + attribute \src "ls180.v:3230.36-3230.85" + cell $eq $eq$ls180.v:3230$816 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6250$1844_Y - connect \B $eq$ls180.v:6250$1845_Y - connect \Y $and$ls180.v:6250$1846_Y + connect \A \libresocsim_interface3_bank_bus_adr [13:8] + connect \B 4'1000 + connect \Y $eq$ls180.v:3230$816_Y end - attribute \src "ls180.v:6252.44-6252.97" - cell $and $and$ls180.v:6252$1847 + attribute \src "ls180.v:3232.105-3232.151" + cell $eq $eq$ls180.v:3232$818 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6252$1847_Y + connect \A \libresocsim_interface3_bank_bus_adr [0] + connect \B 1'0 + connect \Y $eq$ls180.v:3232$818_Y end - attribute \src "ls180.v:6252.43-6252.148" - cell $and $and$ls180.v:6252$1849 + attribute \src "ls180.v:3233.108-3233.154" + cell $eq $eq$ls180.v:3233$822 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6252$1847_Y - connect \B $eq$ls180.v:6252$1848_Y - connect \Y $and$ls180.v:6252$1849_Y + connect \A \libresocsim_interface3_bank_bus_adr [0] + connect \B 1'0 + connect \Y $eq$ls180.v:3233$822_Y end - attribute \src "ls180.v:6253.44-6253.100" - cell $and $and$ls180.v:6253$1851 + attribute \src "ls180.v:3235.104-3235.150" + cell $eq $eq$ls180.v:3235$825 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6253$1850_Y - connect \Y $and$ls180.v:6253$1851_Y + connect \A \libresocsim_interface3_bank_bus_adr [0] + connect \B 1'1 + connect \Y $eq$ls180.v:3235$825_Y end - attribute \src "ls180.v:6253.43-6253.151" - cell $and $and$ls180.v:6253$1853 + attribute \src "ls180.v:3236.107-3236.153" + cell $eq $eq$ls180.v:3236$829 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6253$1851_Y - connect \B $eq$ls180.v:6253$1852_Y - connect \Y $and$ls180.v:6253$1853_Y + connect \A \libresocsim_interface3_bank_bus_adr [0] + connect \B 1'1 + connect \Y $eq$ls180.v:3236$829_Y end - attribute \src "ls180.v:6255.44-6255.97" - cell $and $and$ls180.v:6255$1854 + attribute \src "ls180.v:3244.36-3244.85" + cell $eq $eq$ls180.v:3244$831 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B \builder_interface7_bank_bus_we - connect \Y $and$ls180.v:6255$1854_Y + connect \A \libresocsim_interface4_bank_bus_adr [13:8] + connect \B 2'11 + connect \Y $eq$ls180.v:3244$831_Y end - attribute \src "ls180.v:6255.43-6255.148" - cell $and $and$ls180.v:6255$1856 + attribute \src "ls180.v:3246.116-3246.164" + cell $eq $eq$ls180.v:3246$833 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6255$1854_Y - connect \B $eq$ls180.v:6255$1855_Y - connect \Y $and$ls180.v:6255$1856_Y + connect \A \libresocsim_interface4_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:3246$833_Y end - attribute \src "ls180.v:6256.44-6256.100" - cell $and $and$ls180.v:6256$1858 + attribute \src "ls180.v:3247.119-3247.167" + cell $eq $eq$ls180.v:3247$837 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank7_sel - connect \B $not$ls180.v:6256$1857_Y - connect \Y $and$ls180.v:6256$1858_Y + connect \A \libresocsim_interface4_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$ls180.v:3247$837_Y end - attribute \src "ls180.v:6256.43-6256.151" - cell $and $and$ls180.v:6256$1860 + attribute \src "ls180.v:3249.120-3249.168" + cell $eq $eq$ls180.v:3249$840 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6256$1858_Y - connect \B $eq$ls180.v:6256$1859_Y - connect \Y $and$ls180.v:6256$1860_Y + connect \A \libresocsim_interface4_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:3249$840_Y end - attribute \src "ls180.v:6280.44-6280.97" - cell $and $and$ls180.v:6280$1862 + attribute \src "ls180.v:3250.123-3250.171" + cell $eq $eq$ls180.v:3250$844 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6280$1862_Y + connect \A \libresocsim_interface4_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$ls180.v:3250$844_Y end - attribute \src "ls180.v:6280.43-6280.147" - cell $and $and$ls180.v:6280$1864 + attribute \src "ls180.v:3252.101-3252.149" + cell $eq $eq$ls180.v:3252$847 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6280$1862_Y - connect \B $eq$ls180.v:6280$1863_Y - connect \Y $and$ls180.v:6280$1864_Y + connect \A \libresocsim_interface4_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:3252$847_Y end - attribute \src "ls180.v:6281.44-6281.100" - cell $and $and$ls180.v:6281$1866 + attribute \src "ls180.v:3253.104-3253.152" + cell $eq $eq$ls180.v:3253$851 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6281$1865_Y - connect \Y $and$ls180.v:6281$1866_Y + connect \A \libresocsim_interface4_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$ls180.v:3253$851_Y end - attribute \src "ls180.v:6281.43-6281.150" - cell $and $and$ls180.v:6281$1868 + attribute \src "ls180.v:3255.120-3255.168" + cell $eq $eq$ls180.v:3255$854 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6281$1866_Y - connect \B $eq$ls180.v:6281$1867_Y - connect \Y $and$ls180.v:6281$1868_Y + connect \A \libresocsim_interface4_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:3255$854_Y end - attribute \src "ls180.v:6283.49-6283.102" - cell $and $and$ls180.v:6283$1869 + attribute \src "ls180.v:3256.123-3256.171" + cell $eq $eq$ls180.v:3256$858 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6283$1869_Y + connect \A \libresocsim_interface4_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$ls180.v:3256$858_Y end - attribute \src "ls180.v:6283.48-6283.152" - cell $and $and$ls180.v:6283$1871 + attribute \src "ls180.v:3258.120-3258.168" + cell $eq $eq$ls180.v:3258$861 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6283$1869_Y - connect \B $eq$ls180.v:6283$1870_Y - connect \Y $and$ls180.v:6283$1871_Y + connect \A \libresocsim_interface4_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:3258$861_Y end - attribute \src "ls180.v:6284.49-6284.105" - cell $and $and$ls180.v:6284$1873 + attribute \src "ls180.v:3259.123-3259.171" + cell $eq $eq$ls180.v:3259$865 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6284$1872_Y - connect \Y $and$ls180.v:6284$1873_Y + connect \A \libresocsim_interface4_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$ls180.v:3259$865_Y end - attribute \src "ls180.v:6284.48-6284.155" - cell $and $and$ls180.v:6284$1875 + attribute \src "ls180.v:3261.121-3261.169" + cell $eq $eq$ls180.v:3261$868 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6284$1873_Y - connect \B $eq$ls180.v:6284$1874_Y - connect \Y $and$ls180.v:6284$1875_Y + connect \A \libresocsim_interface4_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:3261$868_Y end - attribute \src "ls180.v:6286.49-6286.102" - cell $and $and$ls180.v:6286$1876 + attribute \src "ls180.v:3262.124-3262.172" + cell $eq $eq$ls180.v:3262$872 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6286$1876_Y + connect \A \libresocsim_interface4_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$ls180.v:3262$872_Y end - attribute \src "ls180.v:6286.48-6286.152" - cell $and $and$ls180.v:6286$1878 + attribute \src "ls180.v:3264.119-3264.167" + cell $eq $eq$ls180.v:3264$875 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6286$1876_Y - connect \B $eq$ls180.v:6286$1877_Y - connect \Y $and$ls180.v:6286$1878_Y + connect \A \libresocsim_interface4_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:3264$875_Y end - attribute \src "ls180.v:6287.49-6287.105" - cell $and $and$ls180.v:6287$1880 + attribute \src "ls180.v:3265.122-3265.170" + cell $eq $eq$ls180.v:3265$879 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6287$1879_Y - connect \Y $and$ls180.v:6287$1880_Y + connect \A \libresocsim_interface4_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$ls180.v:3265$879_Y end - attribute \src "ls180.v:6287.48-6287.155" - cell $and $and$ls180.v:6287$1882 + attribute \src "ls180.v:3267.119-3267.167" + cell $eq $eq$ls180.v:3267$882 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6287$1880_Y - connect \B $eq$ls180.v:6287$1881_Y - connect \Y $and$ls180.v:6287$1882_Y + connect \A \libresocsim_interface4_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:3267$882_Y end - attribute \src "ls180.v:6289.42-6289.95" - cell $and $and$ls180.v:6289$1883 + attribute \src "ls180.v:3268.122-3268.170" + cell $eq $eq$ls180.v:3268$886 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B \builder_interface8_bank_bus_we - connect \Y $and$ls180.v:6289$1883_Y + connect \A \libresocsim_interface4_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$ls180.v:3268$886_Y end - attribute \src "ls180.v:6289.41-6289.145" - cell $and $and$ls180.v:6289$1885 + attribute \src "ls180.v:3270.119-3270.167" + cell $eq $eq$ls180.v:3270$889 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6289$1883_Y - connect \B $eq$ls180.v:6289$1884_Y - connect \Y $and$ls180.v:6289$1885_Y + connect \A \libresocsim_interface4_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:3270$889_Y end - attribute \src "ls180.v:6290.42-6290.98" - cell $and $and$ls180.v:6290$1887 + attribute \src "ls180.v:3271.122-3271.170" + cell $eq $eq$ls180.v:3271$893 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_csrbank8_sel - connect \B $not$ls180.v:6290$1886_Y - connect \Y $and$ls180.v:6290$1887_Y + connect \A \libresocsim_interface4_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:3271$893_Y end - attribute \src "ls180.v:6290.41-6290.148" - cell $and $and$ls180.v:6290$1889 + attribute \src "ls180.v:3273.119-3273.167" + cell $eq $eq$ls180.v:3273$896 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6290$1887_Y - connect \B $eq$ls180.v:6290$1888_Y - connect \Y $and$ls180.v:6290$1889_Y + connect \A \libresocsim_interface4_bank_bus_adr [3:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:3273$896_Y end - attribute \src "ls180.v:6297.46-6297.99" - cell $and $and$ls180.v:6297$1891 + attribute \src "ls180.v:3274.122-3274.170" + cell $eq $eq$ls180.v:3274$900 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6297$1891_Y + connect \A \libresocsim_interface4_bank_bus_adr [3:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:3274$900_Y end - attribute \src "ls180.v:6297.45-6297.149" - cell $and $and$ls180.v:6297$1893 + attribute \src "ls180.v:3289.36-3289.85" + cell $eq $eq$ls180.v:3289$902 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6297$1891_Y - connect \B $eq$ls180.v:6297$1892_Y - connect \Y $and$ls180.v:6297$1893_Y + connect \A \libresocsim_interface5_bank_bus_adr [13:8] + connect \B 2'10 + connect \Y $eq$ls180.v:3289$902_Y end - attribute \src "ls180.v:6298.46-6298.102" - cell $and $and$ls180.v:6298$1895 + attribute \src "ls180.v:3291.108-3291.156" + cell $eq $eq$ls180.v:3291$904 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6298$1894_Y - connect \Y $and$ls180.v:6298$1895_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 1'0 + connect \Y $eq$ls180.v:3291$904_Y end - attribute \src "ls180.v:6298.45-6298.152" - cell $and $and$ls180.v:6298$1897 + attribute \src "ls180.v:3292.111-3292.159" + cell $eq $eq$ls180.v:3292$908 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6298$1895_Y - connect \B $eq$ls180.v:6298$1896_Y - connect \Y $and$ls180.v:6298$1897_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 1'0 + connect \Y $eq$ls180.v:3292$908_Y end - attribute \src "ls180.v:6300.50-6300.103" - cell $and $and$ls180.v:6300$1898 + attribute \src "ls180.v:3294.108-3294.156" + cell $eq $eq$ls180.v:3294$911 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6300$1898_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 1'1 + connect \Y $eq$ls180.v:3294$911_Y end - attribute \src "ls180.v:6300.49-6300.153" - cell $and $and$ls180.v:6300$1900 + attribute \src "ls180.v:3295.111-3295.159" + cell $eq $eq$ls180.v:3295$915 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6300$1898_Y - connect \B $eq$ls180.v:6300$1899_Y - connect \Y $and$ls180.v:6300$1900_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 1'1 + connect \Y $eq$ls180.v:3295$915_Y end - attribute \src "ls180.v:6301.50-6301.106" - cell $and $and$ls180.v:6301$1902 + attribute \src "ls180.v:3297.108-3297.156" + cell $eq $eq$ls180.v:3297$918 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6301$1901_Y - connect \Y $and$ls180.v:6301$1902_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 2'10 + connect \Y $eq$ls180.v:3297$918_Y end - attribute \src "ls180.v:6301.49-6301.156" - cell $and $and$ls180.v:6301$1904 + attribute \src "ls180.v:3298.111-3298.159" + cell $eq $eq$ls180.v:3298$922 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6301$1902_Y - connect \B $eq$ls180.v:6301$1903_Y - connect \Y $and$ls180.v:6301$1904_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 2'10 + connect \Y $eq$ls180.v:3298$922_Y end - attribute \src "ls180.v:6303.40-6303.93" - cell $and $and$ls180.v:6303$1905 + attribute \src "ls180.v:3300.108-3300.156" + cell $eq $eq$ls180.v:3300$925 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6303$1905_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 2'11 + connect \Y $eq$ls180.v:3300$925_Y end - attribute \src "ls180.v:6303.39-6303.143" - cell $and $and$ls180.v:6303$1907 + attribute \src "ls180.v:3301.111-3301.159" + cell $eq $eq$ls180.v:3301$929 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6303$1905_Y - connect \B $eq$ls180.v:6303$1906_Y - connect \Y $and$ls180.v:6303$1907_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 2'11 + connect \Y $eq$ls180.v:3301$929_Y end - attribute \src "ls180.v:6304.40-6304.96" - cell $and $and$ls180.v:6304$1909 + attribute \src "ls180.v:3303.110-3303.158" + cell $eq $eq$ls180.v:3303$932 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6304$1908_Y - connect \Y $and$ls180.v:6304$1909_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 3'100 + connect \Y $eq$ls180.v:3303$932_Y end - attribute \src "ls180.v:6304.39-6304.146" - cell $and $and$ls180.v:6304$1911 + attribute \src "ls180.v:3304.113-3304.161" + cell $eq $eq$ls180.v:3304$936 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6304$1909_Y - connect \B $eq$ls180.v:6304$1910_Y - connect \Y $and$ls180.v:6304$1911_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 3'100 + connect \Y $eq$ls180.v:3304$936_Y end - attribute \src "ls180.v:6306.50-6306.103" - cell $and $and$ls180.v:6306$1912 + attribute \src "ls180.v:3306.110-3306.158" + cell $eq $eq$ls180.v:3306$939 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6306$1912_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 3'101 + connect \Y $eq$ls180.v:3306$939_Y end - attribute \src "ls180.v:6306.49-6306.153" - cell $and $and$ls180.v:6306$1914 + attribute \src "ls180.v:3307.113-3307.161" + cell $eq $eq$ls180.v:3307$943 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6306$1912_Y - connect \B $eq$ls180.v:6306$1913_Y - connect \Y $and$ls180.v:6306$1914_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 3'101 + connect \Y $eq$ls180.v:3307$943_Y end - attribute \src "ls180.v:6307.50-6307.106" - cell $and $and$ls180.v:6307$1916 + attribute \src "ls180.v:3309.110-3309.158" + cell $eq $eq$ls180.v:3309$946 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6307$1915_Y - connect \Y $and$ls180.v:6307$1916_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 3'110 + connect \Y $eq$ls180.v:3309$946_Y end - attribute \src "ls180.v:6307.49-6307.156" - cell $and $and$ls180.v:6307$1918 + attribute \src "ls180.v:3310.113-3310.161" + cell $eq $eq$ls180.v:3310$950 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6307$1916_Y - connect \B $eq$ls180.v:6307$1917_Y - connect \Y $and$ls180.v:6307$1918_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 3'110 + connect \Y $eq$ls180.v:3310$950_Y end - attribute \src "ls180.v:6309.50-6309.103" - cell $and $and$ls180.v:6309$1919 + attribute \src "ls180.v:3312.110-3312.158" + cell $eq $eq$ls180.v:3312$953 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6309$1919_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 3'111 + connect \Y $eq$ls180.v:3312$953_Y end - attribute \src "ls180.v:6309.49-6309.153" - cell $and $and$ls180.v:6309$1921 + attribute \src "ls180.v:3313.113-3313.161" + cell $eq $eq$ls180.v:3313$957 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6309$1919_Y - connect \B $eq$ls180.v:6309$1920_Y - connect \Y $and$ls180.v:6309$1921_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 3'111 + connect \Y $eq$ls180.v:3313$957_Y end - attribute \src "ls180.v:6310.50-6310.106" - cell $and $and$ls180.v:6310$1923 + attribute \src "ls180.v:3315.106-3315.154" + cell $eq $eq$ls180.v:3315$960 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6310$1922_Y - connect \Y $and$ls180.v:6310$1923_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:3315$960_Y end - attribute \src "ls180.v:6310.49-6310.156" - cell $and $and$ls180.v:6310$1925 + attribute \src "ls180.v:3316.109-3316.157" + cell $eq $eq$ls180.v:3316$964 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6310$1923_Y - connect \B $eq$ls180.v:6310$1924_Y - connect \Y $and$ls180.v:6310$1925_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 4'1000 + connect \Y $eq$ls180.v:3316$964_Y end - attribute \src "ls180.v:6312.51-6312.104" - cell $and $and$ls180.v:6312$1926 + attribute \src "ls180.v:3318.116-3318.164" + cell $eq $eq$ls180.v:3318$967 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6312$1926_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:3318$967_Y end - attribute \src "ls180.v:6312.50-6312.154" - cell $and $and$ls180.v:6312$1928 + attribute \src "ls180.v:3319.119-3319.167" + cell $eq $eq$ls180.v:3319$971 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6312$1926_Y - connect \B $eq$ls180.v:6312$1927_Y - connect \Y $and$ls180.v:6312$1928_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 4'1001 + connect \Y $eq$ls180.v:3319$971_Y end - attribute \src "ls180.v:6313.51-6313.107" - cell $and $and$ls180.v:6313$1930 + attribute \src "ls180.v:3321.109-3321.158" + cell $eq $eq$ls180.v:3321$974 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6313$1929_Y - connect \Y $and$ls180.v:6313$1930_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:3321$974_Y end - attribute \src "ls180.v:6313.50-6313.157" - cell $and $and$ls180.v:6313$1932 + attribute \src "ls180.v:3322.112-3322.161" + cell $eq $eq$ls180.v:3322$978 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6313$1930_Y - connect \B $eq$ls180.v:6313$1931_Y - connect \Y $and$ls180.v:6313$1932_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 4'1010 + connect \Y $eq$ls180.v:3322$978_Y end - attribute \src "ls180.v:6315.49-6315.102" - cell $and $and$ls180.v:6315$1933 + attribute \src "ls180.v:3324.109-3324.158" + cell $eq $eq$ls180.v:3324$981 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6315$1933_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:3324$981_Y end - attribute \src "ls180.v:6315.48-6315.152" - cell $and $and$ls180.v:6315$1935 + attribute \src "ls180.v:3325.112-3325.161" + cell $eq $eq$ls180.v:3325$985 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6315$1933_Y - connect \B $eq$ls180.v:6315$1934_Y - connect \Y $and$ls180.v:6315$1935_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 4'1011 + connect \Y $eq$ls180.v:3325$985_Y end - attribute \src "ls180.v:6316.49-6316.105" - cell $and $and$ls180.v:6316$1937 + attribute \src "ls180.v:3327.109-3327.158" + cell $eq $eq$ls180.v:3327$988 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6316$1936_Y - connect \Y $and$ls180.v:6316$1937_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:3327$988_Y end - attribute \src "ls180.v:6316.48-6316.155" - cell $and $and$ls180.v:6316$1939 + attribute \src "ls180.v:3328.112-3328.161" + cell $eq $eq$ls180.v:3328$992 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6316$1937_Y - connect \B $eq$ls180.v:6316$1938_Y - connect \Y $and$ls180.v:6316$1939_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 4'1100 + connect \Y $eq$ls180.v:3328$992_Y end - attribute \src "ls180.v:6318.49-6318.102" - cell $and $and$ls180.v:6318$1940 + attribute \src "ls180.v:3330.109-3330.158" + cell $eq $eq$ls180.v:3330$995 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6318$1940_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:3330$995_Y end - attribute \src "ls180.v:6318.48-6318.152" - cell $and $and$ls180.v:6318$1942 + attribute \src "ls180.v:3331.112-3331.161" + cell $eq $eq$ls180.v:3331$999 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6318$1940_Y - connect \B $eq$ls180.v:6318$1941_Y - connect \Y $and$ls180.v:6318$1942_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 4'1101 + connect \Y $eq$ls180.v:3331$999_Y end - attribute \src "ls180.v:6319.49-6319.105" - cell $and $and$ls180.v:6319$1944 + attribute \src "ls180.v:3333.113-3333.162" + cell $eq $eq$ls180.v:3333$1002 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6319$1943_Y - connect \Y $and$ls180.v:6319$1944_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:3333$1002_Y end - attribute \src "ls180.v:6319.48-6319.155" - cell $and $and$ls180.v:6319$1946 + attribute \src "ls180.v:3334.116-3334.165" + cell $eq $eq$ls180.v:3334$1006 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6319$1944_Y - connect \B $eq$ls180.v:6319$1945_Y - connect \Y $and$ls180.v:6319$1946_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 4'1110 + connect \Y $eq$ls180.v:3334$1006_Y end - attribute \src "ls180.v:6321.49-6321.102" - cell $and $and$ls180.v:6321$1947 + attribute \src "ls180.v:3336.114-3336.163" + cell $eq $eq$ls180.v:3336$1009 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6321$1947_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:3336$1009_Y end - attribute \src "ls180.v:6321.48-6321.152" - cell $and $and$ls180.v:6321$1949 + attribute \src "ls180.v:3337.117-3337.166" + cell $eq $eq$ls180.v:3337$1013 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6321$1947_Y - connect \B $eq$ls180.v:6321$1948_Y - connect \Y $and$ls180.v:6321$1949_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 4'1111 + connect \Y $eq$ls180.v:3337$1013_Y end - attribute \src "ls180.v:6322.49-6322.105" - cell $and $and$ls180.v:6322$1951 + attribute \src "ls180.v:3339.113-3339.162" + cell $eq $eq$ls180.v:3339$1016 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6322$1950_Y - connect \Y $and$ls180.v:6322$1951_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:3339$1016_Y end - attribute \src "ls180.v:6322.48-6322.155" - cell $and $and$ls180.v:6322$1953 + attribute \src "ls180.v:3340.116-3340.165" + cell $eq $eq$ls180.v:3340$1020 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6322$1951_Y - connect \B $eq$ls180.v:6322$1952_Y - connect \Y $and$ls180.v:6322$1953_Y + connect \A \libresocsim_interface5_bank_bus_adr [4:0] + connect \B 5'10000 + connect \Y $eq$ls180.v:3340$1020_Y end - attribute \src "ls180.v:6324.49-6324.102" - cell $and $and$ls180.v:6324$1954 + attribute \src "ls180.v:3357.36-3357.85" + cell $eq $eq$ls180.v:3357$1022 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B \builder_interface9_bank_bus_we - connect \Y $and$ls180.v:6324$1954_Y + connect \A \libresocsim_interface6_bank_bus_adr [13:8] + connect \B 3'101 + connect \Y $eq$ls180.v:3357$1022_Y end - attribute \src "ls180.v:6324.48-6324.152" - cell $and $and$ls180.v:6324$1956 + attribute \src "ls180.v:3359.86-3359.134" + cell $eq $eq$ls180.v:3359$1024 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6324$1954_Y - connect \B $eq$ls180.v:6324$1955_Y - connect \Y $and$ls180.v:6324$1956_Y + connect \A \libresocsim_interface6_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:3359$1024_Y end - attribute \src "ls180.v:6325.49-6325.105" - cell $and $and$ls180.v:6325$1958 + attribute \src "ls180.v:3360.89-3360.137" + cell $eq $eq$ls180.v:3360$1028 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank9_sel - connect \B $not$ls180.v:6325$1957_Y - connect \Y $and$ls180.v:6325$1958_Y + connect \A \libresocsim_interface6_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$ls180.v:3360$1028_Y end - attribute \src "ls180.v:6325.48-6325.155" - cell $and $and$ls180.v:6325$1960 + attribute \src "ls180.v:3362.109-3362.157" + cell $eq $eq$ls180.v:3362$1031 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6325$1958_Y - connect \B $eq$ls180.v:6325$1959_Y - connect \Y $and$ls180.v:6325$1960_Y + connect \A \libresocsim_interface6_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:3362$1031_Y end - attribute \src "ls180.v:6342.42-6342.97" - cell $and $and$ls180.v:6342$1962 + attribute \src "ls180.v:3363.112-3363.160" + cell $eq $eq$ls180.v:3363$1035 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6342$1962_Y + connect \A \libresocsim_interface6_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$ls180.v:3363$1035_Y end - attribute \src "ls180.v:6342.41-6342.148" - cell $and $and$ls180.v:6342$1964 + attribute \src "ls180.v:3365.110-3365.158" + cell $eq $eq$ls180.v:3365$1038 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6342$1962_Y - connect \B $eq$ls180.v:6342$1963_Y - connect \Y $and$ls180.v:6342$1964_Y + connect \A \libresocsim_interface6_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:3365$1038_Y end - attribute \src "ls180.v:6343.42-6343.100" - cell $and $and$ls180.v:6343$1966 + attribute \src "ls180.v:3366.113-3366.161" + cell $eq $eq$ls180.v:3366$1042 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6343$1965_Y - connect \Y $and$ls180.v:6343$1966_Y + connect \A \libresocsim_interface6_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$ls180.v:3366$1042_Y end - attribute \src "ls180.v:6343.41-6343.151" - cell $and $and$ls180.v:6343$1968 + attribute \src "ls180.v:3368.101-3368.149" + cell $eq $eq$ls180.v:3368$1045 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6343$1966_Y - connect \B $eq$ls180.v:6343$1967_Y - connect \Y $and$ls180.v:6343$1968_Y + connect \A \libresocsim_interface6_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:3368$1045_Y end - attribute \src "ls180.v:6345.42-6345.97" - cell $and $and$ls180.v:6345$1969 + attribute \src "ls180.v:3369.104-3369.152" + cell $eq $eq$ls180.v:3369$1049 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6345$1969_Y + connect \A \libresocsim_interface6_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$ls180.v:3369$1049_Y end - attribute \src "ls180.v:6345.41-6345.148" - cell $and $and$ls180.v:6345$1971 + attribute \src "ls180.v:3371.102-3371.150" + cell $eq $eq$ls180.v:3371$1052 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6345$1969_Y - connect \B $eq$ls180.v:6345$1970_Y - connect \Y $and$ls180.v:6345$1971_Y + connect \A \libresocsim_interface6_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:3371$1052_Y end - attribute \src "ls180.v:6346.42-6346.100" - cell $and $and$ls180.v:6346$1973 + attribute \src "ls180.v:3372.105-3372.153" + cell $eq $eq$ls180.v:3372$1056 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6346$1972_Y - connect \Y $and$ls180.v:6346$1973_Y + connect \A \libresocsim_interface6_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$ls180.v:3372$1056_Y end - attribute \src "ls180.v:6346.41-6346.151" - cell $and $and$ls180.v:6346$1975 + attribute \src "ls180.v:3374.113-3374.161" + cell $eq $eq$ls180.v:3374$1059 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6346$1973_Y - connect \B $eq$ls180.v:6346$1974_Y - connect \Y $and$ls180.v:6346$1975_Y + connect \A \libresocsim_interface6_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:3374$1059_Y end - attribute \src "ls180.v:6348.40-6348.95" - cell $and $and$ls180.v:6348$1976 + attribute \src "ls180.v:3375.116-3375.164" + cell $eq $eq$ls180.v:3375$1063 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6348$1976_Y + connect \A \libresocsim_interface6_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$ls180.v:3375$1063_Y end - attribute \src "ls180.v:6348.39-6348.146" - cell $and $and$ls180.v:6348$1978 + attribute \src "ls180.v:3377.110-3377.158" + cell $eq $eq$ls180.v:3377$1066 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6348$1976_Y - connect \B $eq$ls180.v:6348$1977_Y - connect \Y $and$ls180.v:6348$1978_Y + connect \A \libresocsim_interface6_bank_bus_adr [2:0] + connect \B 3'110 + connect \Y $eq$ls180.v:3377$1066_Y end - attribute \src "ls180.v:6349.40-6349.98" - cell $and $and$ls180.v:6349$1980 + attribute \src "ls180.v:3378.113-3378.161" + cell $eq $eq$ls180.v:3378$1070 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6349$1979_Y - connect \Y $and$ls180.v:6349$1980_Y + connect \A \libresocsim_interface6_bank_bus_adr [2:0] + connect \B 3'110 + connect \Y $eq$ls180.v:3378$1070_Y end - attribute \src "ls180.v:6349.39-6349.149" - cell $and $and$ls180.v:6349$1982 + attribute \src "ls180.v:3380.109-3380.157" + cell $eq $eq$ls180.v:3380$1073 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6349$1980_Y - connect \B $eq$ls180.v:6349$1981_Y - connect \Y $and$ls180.v:6349$1982_Y + connect \A \libresocsim_interface6_bank_bus_adr [2:0] + connect \B 3'111 + connect \Y $eq$ls180.v:3380$1073_Y end - attribute \src "ls180.v:6351.39-6351.94" - cell $and $and$ls180.v:6351$1983 + attribute \src "ls180.v:3381.112-3381.160" + cell $eq $eq$ls180.v:3381$1077 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6351$1983_Y + connect \A \libresocsim_interface6_bank_bus_adr [2:0] + connect \B 3'111 + connect \Y $eq$ls180.v:3381$1077_Y end - attribute \src "ls180.v:6351.38-6351.145" - cell $and $and$ls180.v:6351$1985 + attribute \src "ls180.v:3391.36-3391.85" + cell $eq $eq$ls180.v:3391$1079 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 6 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 3 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6351$1983_Y - connect \B $eq$ls180.v:6351$1984_Y - connect \Y $and$ls180.v:6351$1985_Y + connect \A \libresocsim_interface7_bank_bus_adr [13:8] + connect \B 3'100 + connect \Y $eq$ls180.v:3391$1079_Y end - attribute \src "ls180.v:6352.39-6352.97" - cell $and $and$ls180.v:6352$1987 + attribute \src "ls180.v:3393.115-3393.163" + cell $eq $eq$ls180.v:3393$1081 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6352$1986_Y - connect \Y $and$ls180.v:6352$1987_Y + connect \A \libresocsim_interface7_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:3393$1081_Y end - attribute \src "ls180.v:6352.38-6352.148" - cell $and $and$ls180.v:6352$1989 + attribute \src "ls180.v:3394.118-3394.166" + cell $eq $eq$ls180.v:3394$1085 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6352$1987_Y - connect \B $eq$ls180.v:6352$1988_Y - connect \Y $and$ls180.v:6352$1989_Y + connect \A \libresocsim_interface7_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$ls180.v:3394$1085_Y end - attribute \src "ls180.v:6354.38-6354.93" - cell $and $and$ls180.v:6354$1990 + attribute \src "ls180.v:3396.115-3396.163" + cell $eq $eq$ls180.v:3396$1088 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6354$1990_Y + connect \A \libresocsim_interface7_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:3396$1088_Y end - attribute \src "ls180.v:6354.37-6354.144" - cell $and $and$ls180.v:6354$1992 + attribute \src "ls180.v:3397.118-3397.166" + cell $eq $eq$ls180.v:3397$1092 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6354$1990_Y - connect \B $eq$ls180.v:6354$1991_Y - connect \Y $and$ls180.v:6354$1992_Y + connect \A \libresocsim_interface7_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$ls180.v:3397$1092_Y end - attribute \src "ls180.v:6355.38-6355.96" - cell $and $and$ls180.v:6355$1994 + attribute \src "ls180.v:3399.115-3399.163" + cell $eq $eq$ls180.v:3399$1095 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6355$1993_Y - connect \Y $and$ls180.v:6355$1994_Y + connect \A \libresocsim_interface7_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:3399$1095_Y end - attribute \src "ls180.v:6355.37-6355.147" - cell $and $and$ls180.v:6355$1996 + attribute \src "ls180.v:3400.118-3400.166" + cell $eq $eq$ls180.v:3400$1099 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6355$1994_Y - connect \B $eq$ls180.v:6355$1995_Y - connect \Y $and$ls180.v:6355$1996_Y + connect \A \libresocsim_interface7_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$ls180.v:3400$1099_Y end - attribute \src "ls180.v:6357.37-6357.92" - cell $and $and$ls180.v:6357$1997 + attribute \src "ls180.v:3402.115-3402.163" + cell $eq $eq$ls180.v:3402$1102 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6357$1997_Y + connect \A \libresocsim_interface7_bank_bus_adr [1:0] + connect \B 2'11 + connect \Y $eq$ls180.v:3402$1102_Y end - attribute \src "ls180.v:6357.36-6357.143" - cell $and $and$ls180.v:6357$1999 + attribute \src "ls180.v:3403.118-3403.166" + cell $eq $eq$ls180.v:3403$1106 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6357$1997_Y - connect \B $eq$ls180.v:6357$1998_Y - connect \Y $and$ls180.v:6357$1999_Y + connect \A \libresocsim_interface7_bank_bus_adr [1:0] + connect \B 2'11 + connect \Y $eq$ls180.v:3403$1106_Y end - attribute \src "ls180.v:6358.37-6358.95" - cell $and $and$ls180.v:6358$2001 + attribute \src "ls180.v:3763.28-3763.63" + cell $eq $eq$ls180.v:3763$1136 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6358$2000_Y - connect \Y $and$ls180.v:6358$2001_Y + connect \A \port_cmd_payload_addr [10:9] + connect \B 1'0 + connect \Y $eq$ls180.v:3763$1136_Y end - attribute \src "ls180.v:6358.36-6358.146" - cell $and $and$ls180.v:6358$2003 + attribute \src "ls180.v:3763.126-3763.164" + cell $eq $eq$ls180.v:3763$1137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6358$2001_Y - connect \B $eq$ls180.v:6358$2002_Y - connect \Y $and$ls180.v:6358$2003_Y + connect \A \subfragments_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3763$1137_Y end - attribute \src "ls180.v:6360.43-6360.98" - cell $and $and$ls180.v:6360$2004 + attribute \src "ls180.v:3763.201-3763.239" + cell $eq $eq$ls180.v:3763$1140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B \builder_interface10_bank_bus_we - connect \Y $and$ls180.v:6360$2004_Y + connect \A \subfragments_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3763$1140_Y end - attribute \src "ls180.v:6360.42-6360.149" - cell $and $and$ls180.v:6360$2006 + attribute \src "ls180.v:3763.276-3763.314" + cell $eq $eq$ls180.v:3763$1143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6360$2004_Y - connect \B $eq$ls180.v:6360$2005_Y - connect \Y $and$ls180.v:6360$2006_Y + connect \A \subfragments_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3763$1143_Y end - attribute \src "ls180.v:6361.43-6361.101" - cell $and $and$ls180.v:6361$2008 + attribute \src "ls180.v:3787.28-3787.63" + cell $eq $eq$ls180.v:3787$1152 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank10_sel - connect \B $not$ls180.v:6361$2007_Y - connect \Y $and$ls180.v:6361$2008_Y + connect \A \port_cmd_payload_addr [10:9] + connect \B 1'1 + connect \Y $eq$ls180.v:3787$1152_Y end - attribute \src "ls180.v:6361.42-6361.152" - cell $and $and$ls180.v:6361$2010 + attribute \src "ls180.v:3787.126-3787.164" + cell $eq $eq$ls180.v:3787$1153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6361$2008_Y - connect \B $eq$ls180.v:6361$2009_Y - connect \Y $and$ls180.v:6361$2010_Y + connect \A \subfragments_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3787$1153_Y end - attribute \src "ls180.v:6382.42-6382.97" - cell $and $and$ls180.v:6382$2013 + attribute \src "ls180.v:3787.201-3787.239" + cell $eq $eq$ls180.v:3787$1156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6382$2013_Y + connect \A \subfragments_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3787$1156_Y end - attribute \src "ls180.v:6382.41-6382.148" - cell $and $and$ls180.v:6382$2015 + attribute \src "ls180.v:3787.276-3787.314" + cell $eq $eq$ls180.v:3787$1159 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6382$2013_Y - connect \B $eq$ls180.v:6382$2014_Y - connect \Y $and$ls180.v:6382$2015_Y + connect \A \subfragments_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3787$1159_Y end - attribute \src "ls180.v:6383.42-6383.100" - cell $and $and$ls180.v:6383$2017 + attribute \src "ls180.v:3811.28-3811.63" + cell $eq $eq$ls180.v:3811$1168 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6383$2016_Y - connect \Y $and$ls180.v:6383$2017_Y + connect \A \port_cmd_payload_addr [10:9] + connect \B 2'10 + connect \Y $eq$ls180.v:3811$1168_Y end - attribute \src "ls180.v:6383.41-6383.151" - cell $and $and$ls180.v:6383$2019 + attribute \src "ls180.v:3811.126-3811.164" + cell $eq $eq$ls180.v:3811$1169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6383$2017_Y - connect \B $eq$ls180.v:6383$2018_Y - connect \Y $and$ls180.v:6383$2019_Y + connect \A \subfragments_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3811$1169_Y end - attribute \src "ls180.v:6385.42-6385.97" - cell $and $and$ls180.v:6385$2020 + attribute \src "ls180.v:3811.201-3811.239" + cell $eq $eq$ls180.v:3811$1172 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6385$2020_Y + connect \A \subfragments_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3811$1172_Y end - attribute \src "ls180.v:6385.41-6385.148" - cell $and $and$ls180.v:6385$2022 + attribute \src "ls180.v:3811.276-3811.314" + cell $eq $eq$ls180.v:3811$1175 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6385$2020_Y - connect \B $eq$ls180.v:6385$2021_Y - connect \Y $and$ls180.v:6385$2022_Y + connect \A \subfragments_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3811$1175_Y end - attribute \src "ls180.v:6386.42-6386.100" - cell $and $and$ls180.v:6386$2024 + attribute \src "ls180.v:3835.28-3835.63" + cell $eq $eq$ls180.v:3835$1184 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 2 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6386$2023_Y - connect \Y $and$ls180.v:6386$2024_Y + connect \A \port_cmd_payload_addr [10:9] + connect \B 2'11 + connect \Y $eq$ls180.v:3835$1184_Y end - attribute \src "ls180.v:6386.41-6386.151" - cell $and $and$ls180.v:6386$2026 + attribute \src "ls180.v:3835.126-3835.164" + cell $eq $eq$ls180.v:3835$1185 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6386$2024_Y - connect \B $eq$ls180.v:6386$2025_Y - connect \Y $and$ls180.v:6386$2026_Y + connect \A \subfragments_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3835$1185_Y end - attribute \src "ls180.v:6388.40-6388.95" - cell $and $and$ls180.v:6388$2027 + attribute \src "ls180.v:3835.201-3835.239" + cell $eq $eq$ls180.v:3835$1188 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6388$2027_Y + connect \A \subfragments_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3835$1188_Y end - attribute \src "ls180.v:6388.39-6388.146" - cell $and $and$ls180.v:6388$2029 + attribute \src "ls180.v:3835.276-3835.314" + cell $eq $eq$ls180.v:3835$1191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6388$2027_Y - connect \B $eq$ls180.v:6388$2028_Y - connect \Y $and$ls180.v:6388$2029_Y + connect \A \subfragments_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:3835$1191_Y end - attribute \src "ls180.v:6389.40-6389.98" - cell $and $and$ls180.v:6389$2031 + attribute \src "ls180.v:4361.8-4361.33" + cell $eq $eq$ls180.v:4361$1285 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6389$2030_Y - connect \Y $and$ls180.v:6389$2031_Y + connect \A \libresocsim_value + connect \B 1'0 + connect \Y $eq$ls180.v:4361$1285_Y end - attribute \src "ls180.v:6389.39-6389.149" - cell $and $and$ls180.v:6389$2033 + attribute \src "ls180.v:4396.8-4396.37" + cell $eq $eq$ls180.v:4396$1296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6389$2031_Y - connect \B $eq$ls180.v:6389$2032_Y - connect \Y $and$ls180.v:6389$2033_Y + connect \A \sdram_postponer_count + connect \B 1'0 + connect \Y $eq$ls180.v:4396$1296_Y end - attribute \src "ls180.v:6391.39-6391.94" - cell $and $and$ls180.v:6391$2034 + attribute \src "ls180.v:4416.33-4416.64" + cell $eq $eq$ls180.v:4416$1299 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6391$2034_Y + connect \A \sdram_sequencer_counter + connect \B 1'0 + connect \Y $eq$ls180.v:4416$1299_Y end - attribute \src "ls180.v:6391.38-6391.145" - cell $and $and$ls180.v:6391$2036 + attribute \src "ls180.v:4423.7-4423.38" + cell $eq $eq$ls180.v:4423$1301 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 2 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6391$2034_Y - connect \B $eq$ls180.v:6391$2035_Y - connect \Y $and$ls180.v:6391$2036_Y + connect \A \sdram_sequencer_counter + connect \B 2'10 + connect \Y $eq$ls180.v:4423$1301_Y end - attribute \src "ls180.v:6392.39-6392.97" - cell $and $and$ls180.v:6392$2038 + attribute \src "ls180.v:4430.7-4430.38" + cell $eq $eq$ls180.v:4430$1302 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6392$2037_Y - connect \Y $and$ls180.v:6392$2038_Y + connect \A \sdram_sequencer_counter + connect \B 4'1000 + connect \Y $eq$ls180.v:4430$1302_Y end - attribute \src "ls180.v:6392.38-6392.148" - cell $and $and$ls180.v:6392$2040 + attribute \src "ls180.v:4438.7-4438.38" + cell $eq $eq$ls180.v:4438$1303 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6392$2038_Y - connect \B $eq$ls180.v:6392$2039_Y - connect \Y $and$ls180.v:6392$2040_Y + connect \A \sdram_sequencer_counter + connect \B 4'1000 + connect \Y $eq$ls180.v:4438$1303_Y end - attribute \src "ls180.v:6394.38-6394.93" - cell $and $and$ls180.v:6394$2041 + attribute \src "ls180.v:4490.9-4490.49" + cell $eq $eq$ls180.v:4490$1321 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6394$2041_Y + connect \A \sdram_bankmachine0_twtpcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:4490$1321_Y end - attribute \src "ls180.v:6394.37-6394.144" - cell $and $and$ls180.v:6394$2043 + attribute \src "ls180.v:4536.9-4536.49" + cell $eq $eq$ls180.v:4536$1337 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6394$2041_Y - connect \B $eq$ls180.v:6394$2042_Y - connect \Y $and$ls180.v:6394$2043_Y + connect \A \sdram_bankmachine1_twtpcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:4536$1337_Y end - attribute \src "ls180.v:6395.38-6395.96" - cell $and $and$ls180.v:6395$2045 + attribute \src "ls180.v:4582.9-4582.49" + cell $eq $eq$ls180.v:4582$1353 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6395$2044_Y - connect \Y $and$ls180.v:6395$2045_Y + connect \A \sdram_bankmachine2_twtpcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:4582$1353_Y end - attribute \src "ls180.v:6395.37-6395.147" - cell $and $and$ls180.v:6395$2047 + attribute \src "ls180.v:4628.9-4628.49" + cell $eq $eq$ls180.v:4628$1369 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6395$2045_Y - connect \B $eq$ls180.v:6395$2046_Y - connect \Y $and$ls180.v:6395$2047_Y + connect \A \sdram_bankmachine3_twtpcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:4628$1369_Y end - attribute \src "ls180.v:6397.37-6397.92" - cell $and $and$ls180.v:6397$2048 + attribute \src "ls180.v:4778.9-4778.36" + cell $eq $eq$ls180.v:4778$1381 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6397$2048_Y + connect \A \sdram_tccdcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:4778$1381_Y end - attribute \src "ls180.v:6397.36-6397.143" - cell $and $and$ls180.v:6397$2050 + attribute \src "ls180.v:4793.9-4793.36" + cell $eq $eq$ls180.v:4793$1384 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6397$2048_Y - connect \B $eq$ls180.v:6397$2049_Y - connect \Y $and$ls180.v:6397$2050_Y + connect \A \sdram_twtrcon_count + connect \B 1'1 + connect \Y $eq$ls180.v:4793$1384_Y end - attribute \src "ls180.v:6398.37-6398.95" - cell $and $and$ls180.v:6398$2052 + attribute \src "ls180.v:4799.54-4799.92" + cell $eq $eq$ls180.v:4799$1385 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6398$2051_Y - connect \Y $and$ls180.v:6398$2052_Y + connect \A \subfragments_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4799$1385_Y end - attribute \src "ls180.v:6398.36-6398.146" - cell $and $and$ls180.v:6398$2054 + attribute \src "ls180.v:4799.136-4799.174" + cell $eq $eq$ls180.v:4799$1388 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6398$2052_Y - connect \B $eq$ls180.v:6398$2053_Y - connect \Y $and$ls180.v:6398$2054_Y + connect \A \subfragments_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4799$1388_Y end - attribute \src "ls180.v:6400.43-6400.98" - cell $and $and$ls180.v:6400$2055 + attribute \src "ls180.v:4799.218-4799.256" + cell $eq $eq$ls180.v:4799$1391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6400$2055_Y + connect \A \subfragments_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4799$1391_Y end - attribute \src "ls180.v:6400.42-6400.149" - cell $and $and$ls180.v:6400$2057 + attribute \src "ls180.v:4799.300-4799.338" + cell $eq $eq$ls180.v:4799$1394 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6400$2055_Y - connect \B $eq$ls180.v:6400$2056_Y - connect \Y $and$ls180.v:6400$2057_Y + connect \A \subfragments_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4799$1394_Y end - attribute \src "ls180.v:6401.43-6401.101" - cell $and $and$ls180.v:6401$2059 + attribute \src "ls180.v:4800.55-4800.93" + cell $eq $eq$ls180.v:4800$1397 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6401$2058_Y - connect \Y $and$ls180.v:6401$2059_Y + connect \A \subfragments_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4800$1397_Y end - attribute \src "ls180.v:6401.42-6401.152" - cell $and $and$ls180.v:6401$2061 + attribute \src "ls180.v:4800.137-4800.175" + cell $eq $eq$ls180.v:4800$1400 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6401$2059_Y - connect \B $eq$ls180.v:6401$2060_Y - connect \Y $and$ls180.v:6401$2061_Y + connect \A \subfragments_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4800$1400_Y end - attribute \src "ls180.v:6403.46-6403.101" - cell $and $and$ls180.v:6403$2062 + attribute \src "ls180.v:4800.219-4800.257" + cell $eq $eq$ls180.v:4800$1403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6403$2062_Y + connect \A \subfragments_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4800$1403_Y end - attribute \src "ls180.v:6403.45-6403.152" - cell $and $and$ls180.v:6403$2064 + attribute \src "ls180.v:4800.301-4800.339" + cell $eq $eq$ls180.v:4800$1406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6403$2062_Y - connect \B $eq$ls180.v:6403$2063_Y - connect \Y $and$ls180.v:6403$2064_Y + connect \A \subfragments_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$ls180.v:4800$1406_Y end - attribute \src "ls180.v:6404.46-6404.104" - cell $and $and$ls180.v:6404$2066 + attribute \src "ls180.v:4835.9-4835.37" + cell $eq $eq$ls180.v:4835$1418 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6404$2065_Y - connect \Y $and$ls180.v:6404$2066_Y + connect \A \uart_phy_tx_bitcount + connect \B 4'1000 + connect \Y $eq$ls180.v:4835$1418_Y end - attribute \src "ls180.v:6404.45-6404.155" - cell $and $and$ls180.v:6404$2068 + attribute \src "ls180.v:4838.10-4838.38" + cell $eq $eq$ls180.v:4838$1419 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6404$2066_Y - connect \B $eq$ls180.v:6404$2067_Y - connect \Y $and$ls180.v:6404$2068_Y + connect \A \uart_phy_tx_bitcount + connect \B 4'1001 + connect \Y $eq$ls180.v:4838$1419_Y end - attribute \src "ls180.v:6406.46-6406.101" - cell $and $and$ls180.v:6406$2069 + attribute \src "ls180.v:4864.9-4864.37" + cell $eq $eq$ls180.v:4864$1425 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B \builder_interface11_bank_bus_we - connect \Y $and$ls180.v:6406$2069_Y + connect \A \uart_phy_rx_bitcount + connect \B 1'0 + connect \Y $eq$ls180.v:4864$1425_Y end - attribute \src "ls180.v:6406.45-6406.152" - cell $and $and$ls180.v:6406$2071 + attribute \src "ls180.v:4869.10-4869.38" + cell $eq $eq$ls180.v:4869$1426 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6406$2069_Y - connect \B $eq$ls180.v:6406$2070_Y - connect \Y $and$ls180.v:6406$2071_Y + connect \A \uart_phy_rx_bitcount + connect \B 4'1001 + connect \Y $eq$ls180.v:4869$1426_Y + end + attribute \src "ls180.v:5511.28-5511.31" + cell $memrd $memrd$\mem$ls180.v:5511$1508 + parameter \ABITS 6 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \memadr + connect \CLK 1'x + connect \DATA $memrd$\mem$ls180.v:5511$1508_DATA + connect \EN 1'x + end + attribute \src "ls180.v:5539.20-5539.25" + cell $memrd $memrd$\mem_1$ls180.v:5539$1558 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem_1" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \memadr_1 + connect \CLK 1'x + connect \DATA $memrd$\mem_1$ls180.v:5539$1558_DATA + connect \EN 1'x + end + attribute \src "ls180.v:5550.12-5550.19" + cell $memrd $memrd$\storage$ls180.v:5550$1566 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage$ls180.v:5550$1566_DATA + connect \EN 1'x + end + attribute \src "ls180.v:5557.63-5557.70" + cell $memrd $memrd$\storage$ls180.v:5557$1568 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage$ls180.v:5557$1568_DATA + connect \EN 1'x + end + attribute \src "ls180.v:5564.14-5564.23" + cell $memrd $memrd$\storage_1$ls180.v:5564$1576 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_1" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_1$ls180.v:5564$1576_DATA + connect \EN 1'x + end + attribute \src "ls180.v:5571.63-5571.72" + cell $memrd $memrd$\storage_1$ls180.v:5571$1578 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_1" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_1$ls180.v:5571$1578_DATA + connect \EN 1'x + end + attribute \src "ls180.v:5578.14-5578.23" + cell $memrd $memrd$\storage_2$ls180.v:5578$1586 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_2" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_2$ls180.v:5578$1586_DATA + connect \EN 1'x end - attribute \src "ls180.v:6407.46-6407.104" - cell $and $and$ls180.v:6407$2073 + attribute \src "ls180.v:5585.63-5585.72" + cell $memrd $memrd$\storage_2$ls180.v:5585$1588 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_2" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_2$ls180.v:5585$1588_DATA + connect \EN 1'x + end + attribute \src "ls180.v:5592.14-5592.23" + cell $memrd $memrd$\storage_3$ls180.v:5592$1596 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_3" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_3$ls180.v:5592$1596_DATA + connect \EN 1'x + end + attribute \src "ls180.v:5599.63-5599.72" + cell $memrd $memrd$\storage_3$ls180.v:5599$1598 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_3" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_3$ls180.v:5599$1598_DATA + connect \EN 1'x + end + attribute \src "ls180.v:5607.14-5607.23" + cell $memrd $memrd$\storage_4$ls180.v:5607$1606 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_4" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \tx_fifo_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_4$ls180.v:5607$1606_DATA + connect \EN 1'x + end + attribute \src "ls180.v:5612.15-5612.24" + cell $memrd $memrd$\storage_4$ls180.v:5612$1608 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_4" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \tx_fifo_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_4$ls180.v:5612$1608_DATA + connect \EN 1'x + end + attribute \src "ls180.v:5624.14-5624.23" + cell $memrd $memrd$\storage_5$ls180.v:5624$1616 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_5" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \rx_fifo_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_5$ls180.v:5624$1616_DATA + connect \EN 1'x + end + attribute \src "ls180.v:5629.15-5629.24" + cell $memrd $memrd$\storage_5$ls180.v:5629$1618 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_5" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \rx_fifo_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_5$ls180.v:5629$1618_DATA + connect \EN 1'x + end + attribute \src "ls180.v:1709.36-1709.61" + cell $ne $ne$ls180.v:1709$82 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank11_sel - connect \B $not$ls180.v:6407$2072_Y - connect \Y $and$ls180.v:6407$2073_Y + connect \A \libresocsim_value + connect \B 1'0 + connect \Y $ne$ls180.v:1709$82_Y end - attribute \src "ls180.v:6407.45-6407.155" - cell $and $and$ls180.v:6407$2075 + attribute \src "ls180.v:1884.60-1884.89" + cell $ne $ne$ls180.v:1884$121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6407$2073_Y - connect \B $eq$ls180.v:6407$2074_Y - connect \Y $and$ls180.v:6407$2075_Y + connect \A \sdram_sequencer_count + connect \B 1'0 + connect \Y $ne$ls180.v:1884$121_Y end - attribute \src "ls180.v:6430.39-6430.94" - cell $and $and$ls180.v:6430$2078 + attribute \src "ls180.v:1945.8-1945.132" + cell $ne $ne$ls180.v:1945$140 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 13 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 13 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6430$2078_Y + connect \A \sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$ls180.v:1945$140_Y end - attribute \src "ls180.v:6430.38-6430.145" - cell $and $and$ls180.v:6430$2080 + attribute \src "ls180.v:1977.70-1977.123" + cell $ne $ne$ls180.v:1977$147 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6430$2078_Y - connect \B $eq$ls180.v:6430$2079_Y - connect \Y $and$ls180.v:6430$2080_Y + connect \A \sdram_bankmachine0_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$ls180.v:1977$147_Y end - attribute \src "ls180.v:6431.39-6431.97" - cell $and $and$ls180.v:6431$2082 + attribute \src "ls180.v:1978.70-1978.123" + cell $ne $ne$ls180.v:1978$148 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6431$2081_Y - connect \Y $and$ls180.v:6431$2082_Y + connect \A \sdram_bankmachine0_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$ls180.v:1978$148_Y end - attribute \src "ls180.v:6431.38-6431.148" - cell $and $and$ls180.v:6431$2084 + attribute \src "ls180.v:2102.8-2102.132" + cell $ne $ne$ls180.v:2102$170 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 13 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 13 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6431$2082_Y - connect \B $eq$ls180.v:6431$2083_Y - connect \Y $and$ls180.v:6431$2084_Y + connect \A \sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$ls180.v:2102$170_Y end - attribute \src "ls180.v:6433.39-6433.94" - cell $and $and$ls180.v:6433$2085 + attribute \src "ls180.v:2134.70-2134.123" + cell $ne $ne$ls180.v:2134$177 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6433$2085_Y + connect \A \sdram_bankmachine1_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$ls180.v:2134$177_Y end - attribute \src "ls180.v:6433.38-6433.145" - cell $and $and$ls180.v:6433$2087 + attribute \src "ls180.v:2135.70-2135.123" + cell $ne $ne$ls180.v:2135$178 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6433$2085_Y - connect \B $eq$ls180.v:6433$2086_Y - connect \Y $and$ls180.v:6433$2087_Y + connect \A \sdram_bankmachine1_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$ls180.v:2135$178_Y end - attribute \src "ls180.v:6434.39-6434.97" - cell $and $and$ls180.v:6434$2089 + attribute \src "ls180.v:2259.8-2259.132" + cell $ne $ne$ls180.v:2259$200 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 13 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 13 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6434$2088_Y - connect \Y $and$ls180.v:6434$2089_Y + connect \A \sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$ls180.v:2259$200_Y end - attribute \src "ls180.v:6434.38-6434.148" - cell $and $and$ls180.v:6434$2091 + attribute \src "ls180.v:2291.70-2291.123" + cell $ne $ne$ls180.v:2291$207 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6434$2089_Y - connect \B $eq$ls180.v:6434$2090_Y - connect \Y $and$ls180.v:6434$2091_Y + connect \A \sdram_bankmachine2_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$ls180.v:2291$207_Y end - attribute \src "ls180.v:6436.39-6436.94" - cell $and $and$ls180.v:6436$2092 + attribute \src "ls180.v:2292.70-2292.123" + cell $ne $ne$ls180.v:2292$208 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6436$2092_Y + connect \A \sdram_bankmachine2_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$ls180.v:2292$208_Y end - attribute \src "ls180.v:6436.38-6436.145" - cell $and $and$ls180.v:6436$2094 + attribute \src "ls180.v:2416.8-2416.132" + cell $ne $ne$ls180.v:2416$230 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 13 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 13 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6436$2092_Y - connect \B $eq$ls180.v:6436$2093_Y - connect \Y $and$ls180.v:6436$2094_Y + connect \A \sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$ls180.v:2416$230_Y end - attribute \src "ls180.v:6437.39-6437.97" - cell $and $and$ls180.v:6437$2096 + attribute \src "ls180.v:2448.70-2448.123" + cell $ne $ne$ls180.v:2448$237 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 4 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6437$2095_Y - connect \Y $and$ls180.v:6437$2096_Y + connect \A \sdram_bankmachine3_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$ls180.v:2448$237_Y end - attribute \src "ls180.v:6437.38-6437.148" - cell $and $and$ls180.v:6437$2098 + attribute \src "ls180.v:2449.70-2449.123" + cell $ne $ne$ls180.v:2449$238 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6437$2096_Y - connect \B $eq$ls180.v:6437$2097_Y - connect \Y $and$ls180.v:6437$2098_Y + connect \A \sdram_bankmachine3_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$ls180.v:2449$238_Y end - attribute \src "ls180.v:6439.39-6439.94" - cell $and $and$ls180.v:6439$2099 + attribute \src "ls180.v:2941.37-2941.60" + cell $ne $ne$ls180.v:2941$636 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6439$2099_Y + connect \A \tx_fifo_level0 + connect \B 5'10000 + connect \Y $ne$ls180.v:2941$636_Y end - attribute \src "ls180.v:6439.38-6439.145" - cell $and $and$ls180.v:6439$2101 + attribute \src "ls180.v:2942.37-2942.59" + cell $ne $ne$ls180.v:2942$637 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6439$2099_Y - connect \B $eq$ls180.v:6439$2100_Y - connect \Y $and$ls180.v:6439$2101_Y + connect \A \tx_fifo_level0 + connect \B 1'0 + connect \Y $ne$ls180.v:2942$637_Y end - attribute \src "ls180.v:6440.39-6440.97" - cell $and $and$ls180.v:6440$2103 + attribute \src "ls180.v:2971.37-2971.60" + cell $ne $ne$ls180.v:2971$647 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 5 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6440$2102_Y - connect \Y $and$ls180.v:6440$2103_Y + connect \A \rx_fifo_level0 + connect \B 5'10000 + connect \Y $ne$ls180.v:2971$647_Y end - attribute \src "ls180.v:6440.38-6440.148" - cell $and $and$ls180.v:6440$2105 + attribute \src "ls180.v:2972.37-2972.59" + cell $ne $ne$ls180.v:2972$648 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6440$2103_Y - connect \B $eq$ls180.v:6440$2104_Y - connect \Y $and$ls180.v:6440$2105_Y + connect \A \rx_fifo_level0 + connect \B 1'0 + connect \Y $ne$ls180.v:2972$648_Y end - attribute \src "ls180.v:6442.41-6442.96" - cell $and $and$ls180.v:6442$2106 + attribute \src "ls180.v:3067.99-3067.143" + cell $ne $ne$ls180.v:3067$655 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6442$2106_Y + connect \A \libresocsim_libresocsim_wishbone_sel + connect \B 1'0 + connect \Y $ne$ls180.v:3067$655_Y end - attribute \src "ls180.v:6442.40-6442.147" - cell $and $and$ls180.v:6442$2108 + attribute \src "ls180.v:4351.7-4351.47" + cell $ne $ne$ls180.v:4351$1280 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 32 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 + parameter \B_WIDTH 32 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6442$2106_Y - connect \B $eq$ls180.v:6442$2107_Y - connect \Y $and$ls180.v:6442$2108_Y + connect \A \libresocsim_bus_errors + connect \B 32'11111111111111111111111111111111 + connect \Y $ne$ls180.v:4351$1280_Y end - attribute \src "ls180.v:6443.41-6443.99" - cell $and $and$ls180.v:6443$2110 + attribute \src "ls180.v:4405.9-4405.38" + cell $ne $ne$ls180.v:4405$1297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6443$2109_Y - connect \Y $and$ls180.v:6443$2110_Y + connect \A \sdram_sequencer_count + connect \B 1'0 + connect \Y $ne$ls180.v:4405$1297_Y end - attribute \src "ls180.v:6443.40-6443.150" - cell $and $and$ls180.v:6443$2112 + attribute \src "ls180.v:4441.8-4441.39" + cell $ne $ne$ls180.v:4441$1304 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6443$2110_Y - connect \B $eq$ls180.v:6443$2111_Y - connect \Y $and$ls180.v:6443$2112_Y + connect \A \sdram_sequencer_counter + connect \B 1'0 + connect \Y $ne$ls180.v:4441$1304_Y end - attribute \src "ls180.v:6445.41-6445.96" - cell $and $and$ls180.v:6445$2113 + attribute \src "ls180.v:1513.28-1513.63" + cell $not $not$ls180.v:1513$24 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6445$2113_Y + connect \A \interface0_converted_interface_cyc + connect \Y $not$ls180.v:1513$24_Y end - attribute \src "ls180.v:6445.40-6445.147" - cell $and $and$ls180.v:6445$2115 + attribute \src "ls180.v:1552.43-1552.59" + cell $not $not$ls180.v:1552$29 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6445$2113_Y - connect \B $eq$ls180.v:6445$2114_Y - connect \Y $and$ls180.v:6445$2115_Y + connect \A \converter0_skip + connect \Y $not$ls180.v:1552$29_Y end - attribute \src "ls180.v:6446.41-6446.99" - cell $and $and$ls180.v:6446$2117 + attribute \src "ls180.v:1553.43-1553.59" + cell $not $not$ls180.v:1553$30 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6446$2116_Y - connect \Y $and$ls180.v:6446$2117_Y + connect \A \converter0_skip + connect \Y $not$ls180.v:1553$30_Y end - attribute \src "ls180.v:6446.40-6446.150" - cell $and $and$ls180.v:6446$2119 + attribute \src "ls180.v:1573.28-1573.63" + cell $not $not$ls180.v:1573$35 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6446$2117_Y - connect \B $eq$ls180.v:6446$2118_Y - connect \Y $and$ls180.v:6446$2119_Y + connect \A \interface1_converted_interface_cyc + connect \Y $not$ls180.v:1573$35_Y end - attribute \src "ls180.v:6448.41-6448.96" - cell $and $and$ls180.v:6448$2120 + attribute \src "ls180.v:1612.43-1612.59" + cell $not $not$ls180.v:1612$40 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6448$2120_Y + connect \A \converter1_skip + connect \Y $not$ls180.v:1612$40_Y end - attribute \src "ls180.v:6448.40-6448.147" - cell $and $and$ls180.v:6448$2122 + attribute \src "ls180.v:1613.43-1613.59" + cell $not $not$ls180.v:1613$41 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6448$2120_Y - connect \B $eq$ls180.v:6448$2121_Y - connect \Y $and$ls180.v:6448$2122_Y + connect \A \converter1_skip + connect \Y $not$ls180.v:1613$41_Y end - attribute \src "ls180.v:6449.41-6449.99" - cell $and $and$ls180.v:6449$2124 + attribute \src "ls180.v:1633.31-1633.69" + cell $not $not$ls180.v:1633$46 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6449$2123_Y - connect \Y $and$ls180.v:6449$2124_Y + connect \A \socbushandler_converted_interface_cyc + connect \Y $not$ls180.v:1633$46_Y end - attribute \src "ls180.v:6449.40-6449.150" - cell $and $and$ls180.v:6449$2126 + attribute \src "ls180.v:1672.22-1672.41" + cell $not $not$ls180.v:1672$51 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6449$2124_Y - connect \B $eq$ls180.v:6449$2125_Y - connect \Y $and$ls180.v:6449$2126_Y + connect \A \socbushandler_skip + connect \Y $not$ls180.v:1672$51_Y end - attribute \src "ls180.v:6451.41-6451.96" - cell $and $and$ls180.v:6451$2127 + attribute \src "ls180.v:1673.22-1673.41" + cell $not $not$ls180.v:1673$52 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6451$2127_Y + connect \A \socbushandler_skip + connect \Y $not$ls180.v:1673$52_Y end - attribute \src "ls180.v:6451.40-6451.147" - cell $and $and$ls180.v:6451$2129 + attribute \src "ls180.v:1833.29-1833.54" + cell $not $not$ls180.v:1833$113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6451$2127_Y - connect \B $eq$ls180.v:6451$2128_Y - connect \Y $and$ls180.v:6451$2129_Y + connect \A \sdram_command_storage [0] + connect \Y $not$ls180.v:1833$113_Y end - attribute \src "ls180.v:6452.41-6452.99" - cell $and $and$ls180.v:6452$2131 + attribute \src "ls180.v:1834.26-1834.51" + cell $not $not$ls180.v:1834$114 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6452$2130_Y - connect \Y $and$ls180.v:6452$2131_Y + connect \A \sdram_command_storage [1] + connect \Y $not$ls180.v:1834$114_Y end - attribute \src "ls180.v:6452.40-6452.150" - cell $and $and$ls180.v:6452$2133 + attribute \src "ls180.v:1835.27-1835.52" + cell $not $not$ls180.v:1835$115 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6452$2131_Y - connect \B $eq$ls180.v:6452$2132_Y - connect \Y $and$ls180.v:6452$2133_Y + connect \A \sdram_command_storage [2] + connect \Y $not$ls180.v:1835$115_Y end - attribute \src "ls180.v:6454.37-6454.92" - cell $and $and$ls180.v:6454$2134 + attribute \src "ls180.v:1836.27-1836.52" + cell $not $not$ls180.v:1836$116 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6454$2134_Y + connect \A \sdram_command_storage [3] + connect \Y $not$ls180.v:1836$116_Y end - attribute \src "ls180.v:6454.36-6454.143" - cell $and $and$ls180.v:6454$2136 + attribute \src "ls180.v:1878.28-1878.46" + cell $not $not$ls180.v:1878$119 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6454$2134_Y - connect \B $eq$ls180.v:6454$2135_Y - connect \Y $and$ls180.v:6454$2136_Y + connect \A \sdram_timer_done0 + connect \Y $not$ls180.v:1878$119_Y end - attribute \src "ls180.v:6455.37-6455.95" - cell $and $and$ls180.v:6455$2138 + attribute \src "ls180.v:1979.53-1979.96" + cell $not $not$ls180.v:1979$149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6455$2137_Y - connect \Y $and$ls180.v:6455$2138_Y + connect \A \sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $not$ls180.v:1979$149_Y end - attribute \src "ls180.v:6455.36-6455.146" - cell $and $and$ls180.v:6455$2140 + attribute \src "ls180.v:2033.9-2033.40" + cell $not $not$ls180.v:2033$154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6455$2138_Y - connect \B $eq$ls180.v:6455$2139_Y - connect \Y $and$ls180.v:6455$2140_Y + connect \A \sdram_bankmachine0_refresh_req + connect \Y $not$ls180.v:2033$154_Y end - attribute \src "ls180.v:6457.47-6457.102" - cell $and $and$ls180.v:6457$2141 + attribute \src "ls180.v:2136.53-2136.96" + cell $not $not$ls180.v:2136$179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6457$2141_Y + connect \A \sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $not$ls180.v:2136$179_Y end - attribute \src "ls180.v:6457.46-6457.153" - cell $and $and$ls180.v:6457$2143 + attribute \src "ls180.v:2190.9-2190.40" + cell $not $not$ls180.v:2190$184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6457$2141_Y - connect \B $eq$ls180.v:6457$2142_Y - connect \Y $and$ls180.v:6457$2143_Y + connect \A \sdram_bankmachine1_refresh_req + connect \Y $not$ls180.v:2190$184_Y end - attribute \src "ls180.v:6458.47-6458.105" - cell $and $and$ls180.v:6458$2145 + attribute \src "ls180.v:2293.53-2293.96" + cell $not $not$ls180.v:2293$209 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6458$2144_Y - connect \Y $and$ls180.v:6458$2145_Y + connect \A \sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $not$ls180.v:2293$209_Y end - attribute \src "ls180.v:6458.46-6458.156" - cell $and $and$ls180.v:6458$2147 + attribute \src "ls180.v:2347.9-2347.40" + cell $not $not$ls180.v:2347$214 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6458$2145_Y - connect \B $eq$ls180.v:6458$2146_Y - connect \Y $and$ls180.v:6458$2147_Y + connect \A \sdram_bankmachine2_refresh_req + connect \Y $not$ls180.v:2347$214_Y end - attribute \src "ls180.v:6460.40-6460.95" - cell $and $and$ls180.v:6460$2148 + attribute \src "ls180.v:2450.53-2450.96" + cell $not $not$ls180.v:2450$239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6460$2148_Y + connect \A \sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $not$ls180.v:2450$239_Y end - attribute \src "ls180.v:6460.39-6460.147" - cell $and $and$ls180.v:6460$2150 + attribute \src "ls180.v:2504.9-2504.40" + cell $not $not$ls180.v:2504$244 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6460$2148_Y - connect \B $eq$ls180.v:6460$2149_Y - connect \Y $and$ls180.v:6460$2150_Y + connect \A \sdram_bankmachine3_refresh_req + connect \Y $not$ls180.v:2504$244_Y end - attribute \src "ls180.v:6461.40-6461.98" - cell $and $and$ls180.v:6461$2152 + attribute \src "ls180.v:2546.129-2546.162" + cell $not $not$ls180.v:2546$247 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6461$2151_Y - connect \Y $and$ls180.v:6461$2152_Y + connect \A \sdram_choose_req_cmd_payload_cas + connect \Y $not$ls180.v:2546$247_Y end - attribute \src "ls180.v:6461.39-6461.150" - cell $and $and$ls180.v:6461$2154 + attribute \src "ls180.v:2546.168-2546.200" + cell $not $not$ls180.v:2546$249 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6461$2152_Y - connect \B $eq$ls180.v:6461$2153_Y - connect \Y $and$ls180.v:6461$2154_Y + connect \A \sdram_choose_req_cmd_payload_we + connect \Y $not$ls180.v:2546$249_Y end - attribute \src "ls180.v:6463.40-6463.95" - cell $and $and$ls180.v:6463$2155 + attribute \src "ls180.v:2547.129-2547.162" + cell $not $not$ls180.v:2547$253 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6463$2155_Y + connect \A \sdram_choose_req_cmd_payload_cas + connect \Y $not$ls180.v:2547$253_Y end - attribute \src "ls180.v:6463.39-6463.147" - cell $and $and$ls180.v:6463$2157 + attribute \src "ls180.v:2547.168-2547.200" + cell $not $not$ls180.v:2547$255 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6463$2155_Y - connect \B $eq$ls180.v:6463$2156_Y - connect \Y $and$ls180.v:6463$2157_Y + connect \A \sdram_choose_req_cmd_payload_we + connect \Y $not$ls180.v:2547$255_Y + end + attribute \src "ls180.v:2563.38-2563.63" + cell $not $not$ls180.v:2563$283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \sdram_interface_wdata_we + connect \Y $not$ls180.v:2563$283_Y end - attribute \src "ls180.v:6464.40-6464.98" - cell $and $and$ls180.v:6464$2159 + attribute \src "ls180.v:2566.180-2566.215" + cell $not $not$ls180.v:2566$286 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6464$2158_Y - connect \Y $and$ls180.v:6464$2159_Y + connect \A \sdram_bankmachine0_cmd_payload_cas + connect \Y $not$ls180.v:2566$286_Y end - attribute \src "ls180.v:6464.39-6464.150" - cell $and $and$ls180.v:6464$2161 + attribute \src "ls180.v:2566.221-2566.255" + cell $not $not$ls180.v:2566$288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6464$2159_Y - connect \B $eq$ls180.v:6464$2160_Y - connect \Y $and$ls180.v:6464$2161_Y + connect \A \sdram_bankmachine0_cmd_payload_we + connect \Y $not$ls180.v:2566$288_Y end - attribute \src "ls180.v:6466.40-6466.95" - cell $and $and$ls180.v:6466$2162 + attribute \src "ls180.v:2566.139-2566.257" + cell $not $not$ls180.v:2566$290 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6466$2162_Y + connect \A $and$ls180.v:2566$289_Y + connect \Y $not$ls180.v:2566$290_Y end - attribute \src "ls180.v:6466.39-6466.147" - cell $and $and$ls180.v:6466$2164 + attribute \src "ls180.v:2567.180-2567.215" + cell $not $not$ls180.v:2567$299 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6466$2162_Y - connect \B $eq$ls180.v:6466$2163_Y - connect \Y $and$ls180.v:6466$2164_Y + connect \A \sdram_bankmachine1_cmd_payload_cas + connect \Y $not$ls180.v:2567$299_Y end - attribute \src "ls180.v:6467.40-6467.98" - cell $and $and$ls180.v:6467$2166 + attribute \src "ls180.v:2567.221-2567.255" + cell $not $not$ls180.v:2567$301 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6467$2165_Y - connect \Y $and$ls180.v:6467$2166_Y + connect \A \sdram_bankmachine1_cmd_payload_we + connect \Y $not$ls180.v:2567$301_Y end - attribute \src "ls180.v:6467.39-6467.150" - cell $and $and$ls180.v:6467$2168 + attribute \src "ls180.v:2567.139-2567.257" + cell $not $not$ls180.v:2567$303 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6467$2166_Y - connect \B $eq$ls180.v:6467$2167_Y - connect \Y $and$ls180.v:6467$2168_Y + connect \A $and$ls180.v:2567$302_Y + connect \Y $not$ls180.v:2567$303_Y end - attribute \src "ls180.v:6469.40-6469.95" - cell $and $and$ls180.v:6469$2169 + attribute \src "ls180.v:2568.180-2568.215" + cell $not $not$ls180.v:2568$312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6469$2169_Y + connect \A \sdram_bankmachine2_cmd_payload_cas + connect \Y $not$ls180.v:2568$312_Y end - attribute \src "ls180.v:6469.39-6469.147" - cell $and $and$ls180.v:6469$2171 + attribute \src "ls180.v:2568.221-2568.255" + cell $not $not$ls180.v:2568$314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6469$2169_Y - connect \B $eq$ls180.v:6469$2170_Y - connect \Y $and$ls180.v:6469$2171_Y + connect \A \sdram_bankmachine2_cmd_payload_we + connect \Y $not$ls180.v:2568$314_Y end - attribute \src "ls180.v:6470.40-6470.98" - cell $and $and$ls180.v:6470$2173 + attribute \src "ls180.v:2568.139-2568.257" + cell $not $not$ls180.v:2568$316 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6470$2172_Y - connect \Y $and$ls180.v:6470$2173_Y + connect \A $and$ls180.v:2568$315_Y + connect \Y $not$ls180.v:2568$316_Y end - attribute \src "ls180.v:6470.39-6470.150" - cell $and $and$ls180.v:6470$2175 + attribute \src "ls180.v:2569.180-2569.215" + cell $not $not$ls180.v:2569$325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6470$2173_Y - connect \B $eq$ls180.v:6470$2174_Y - connect \Y $and$ls180.v:6470$2175_Y + connect \A \sdram_bankmachine3_cmd_payload_cas + connect \Y $not$ls180.v:2569$325_Y end - attribute \src "ls180.v:6472.52-6472.107" - cell $and $and$ls180.v:6472$2176 + attribute \src "ls180.v:2569.221-2569.255" + cell $not $not$ls180.v:2569$327 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6472$2176_Y + connect \A \sdram_bankmachine3_cmd_payload_we + connect \Y $not$ls180.v:2569$327_Y end - attribute \src "ls180.v:6472.51-6472.159" - cell $and $and$ls180.v:6472$2178 + attribute \src "ls180.v:2569.139-2569.257" + cell $not $not$ls180.v:2569$329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6472$2176_Y - connect \B $eq$ls180.v:6472$2177_Y - connect \Y $and$ls180.v:6472$2178_Y + connect \A $and$ls180.v:2569$328_Y + connect \Y $not$ls180.v:2569$329_Y end - attribute \src "ls180.v:6473.52-6473.110" - cell $and $and$ls180.v:6473$2180 + attribute \src "ls180.v:2596.61-2596.88" + cell $not $not$ls180.v:2596$340 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6473$2179_Y - connect \Y $and$ls180.v:6473$2180_Y + connect \A \sdram_choose_cmd_cmd_valid + connect \Y $not$ls180.v:2596$340_Y end - attribute \src "ls180.v:6473.51-6473.162" - cell $and $and$ls180.v:6473$2182 + attribute \src "ls180.v:2599.180-2599.215" + cell $not $not$ls180.v:2599$344 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6473$2180_Y - connect \B $eq$ls180.v:6473$2181_Y - connect \Y $and$ls180.v:6473$2182_Y + connect \A \sdram_bankmachine0_cmd_payload_cas + connect \Y $not$ls180.v:2599$344_Y end - attribute \src "ls180.v:6475.53-6475.108" - cell $and $and$ls180.v:6475$2183 + attribute \src "ls180.v:2599.221-2599.255" + cell $not $not$ls180.v:2599$346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6475$2183_Y + connect \A \sdram_bankmachine0_cmd_payload_we + connect \Y $not$ls180.v:2599$346_Y end - attribute \src "ls180.v:6475.52-6475.160" - cell $and $and$ls180.v:6475$2185 + attribute \src "ls180.v:2599.139-2599.257" + cell $not $not$ls180.v:2599$348 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6475$2183_Y - connect \B $eq$ls180.v:6475$2184_Y - connect \Y $and$ls180.v:6475$2185_Y + connect \A $and$ls180.v:2599$347_Y + connect \Y $not$ls180.v:2599$348_Y end - attribute \src "ls180.v:6476.53-6476.111" - cell $and $and$ls180.v:6476$2187 + attribute \src "ls180.v:2600.180-2600.215" + cell $not $not$ls180.v:2600$357 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6476$2186_Y - connect \Y $and$ls180.v:6476$2187_Y + connect \A \sdram_bankmachine1_cmd_payload_cas + connect \Y $not$ls180.v:2600$357_Y end - attribute \src "ls180.v:6476.52-6476.163" - cell $and $and$ls180.v:6476$2189 + attribute \src "ls180.v:2600.221-2600.255" + cell $not $not$ls180.v:2600$359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6476$2187_Y - connect \B $eq$ls180.v:6476$2188_Y - connect \Y $and$ls180.v:6476$2189_Y + connect \A \sdram_bankmachine1_cmd_payload_we + connect \Y $not$ls180.v:2600$359_Y end - attribute \src "ls180.v:6478.44-6478.99" - cell $and $and$ls180.v:6478$2190 + attribute \src "ls180.v:2600.139-2600.257" + cell $not $not$ls180.v:2600$361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B \builder_interface12_bank_bus_we - connect \Y $and$ls180.v:6478$2190_Y + connect \A $and$ls180.v:2600$360_Y + connect \Y $not$ls180.v:2600$361_Y end - attribute \src "ls180.v:6478.43-6478.151" - cell $and $and$ls180.v:6478$2192 + attribute \src "ls180.v:2601.180-2601.215" + cell $not $not$ls180.v:2601$370 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6478$2190_Y - connect \B $eq$ls180.v:6478$2191_Y - connect \Y $and$ls180.v:6478$2192_Y + connect \A \sdram_bankmachine2_cmd_payload_cas + connect \Y $not$ls180.v:2601$370_Y end - attribute \src "ls180.v:6479.44-6479.102" - cell $and $and$ls180.v:6479$2194 + attribute \src "ls180.v:2601.221-2601.255" + cell $not $not$ls180.v:2601$372 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank12_sel - connect \B $not$ls180.v:6479$2193_Y - connect \Y $and$ls180.v:6479$2194_Y + connect \A \sdram_bankmachine2_cmd_payload_we + connect \Y $not$ls180.v:2601$372_Y end - attribute \src "ls180.v:6479.43-6479.154" - cell $and $and$ls180.v:6479$2196 + attribute \src "ls180.v:2601.139-2601.257" + cell $not $not$ls180.v:2601$374 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6479$2194_Y - connect \B $eq$ls180.v:6479$2195_Y - connect \Y $and$ls180.v:6479$2196_Y + connect \A $and$ls180.v:2601$373_Y + connect \Y $not$ls180.v:2601$374_Y end - attribute \src "ls180.v:6498.30-6498.85" - cell $and $and$ls180.v:6498$2198 + attribute \src "ls180.v:2602.180-2602.215" + cell $not $not$ls180.v:2602$383 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6498$2198_Y + connect \A \sdram_bankmachine3_cmd_payload_cas + connect \Y $not$ls180.v:2602$383_Y end - attribute \src "ls180.v:6498.29-6498.136" - cell $and $and$ls180.v:6498$2200 + attribute \src "ls180.v:2602.221-2602.255" + cell $not $not$ls180.v:2602$385 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6498$2198_Y - connect \B $eq$ls180.v:6498$2199_Y - connect \Y $and$ls180.v:6498$2200_Y + connect \A \sdram_bankmachine3_cmd_payload_we + connect \Y $not$ls180.v:2602$385_Y end - attribute \src "ls180.v:6499.30-6499.88" - cell $and $and$ls180.v:6499$2202 + attribute \src "ls180.v:2602.139-2602.257" + cell $not $not$ls180.v:2602$387 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6499$2201_Y - connect \Y $and$ls180.v:6499$2202_Y + connect \A $and$ls180.v:2602$386_Y + connect \Y $not$ls180.v:2602$387_Y end - attribute \src "ls180.v:6499.29-6499.139" - cell $and $and$ls180.v:6499$2204 + attribute \src "ls180.v:2665.61-2665.88" + cell $not $not$ls180.v:2665$426 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6499$2202_Y - connect \B $eq$ls180.v:6499$2203_Y - connect \Y $and$ls180.v:6499$2204_Y + connect \A \sdram_choose_req_cmd_valid + connect \Y $not$ls180.v:2665$426_Y end - attribute \src "ls180.v:6501.40-6501.95" - cell $and $and$ls180.v:6501$2205 + attribute \src "ls180.v:2686.97-2686.130" + cell $not $not$ls180.v:2686$429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6501$2205_Y + connect \A \sdram_choose_req_cmd_payload_cas + connect \Y $not$ls180.v:2686$429_Y end - attribute \src "ls180.v:6501.39-6501.146" - cell $and $and$ls180.v:6501$2207 + attribute \src "ls180.v:2686.136-2686.168" + cell $not $not$ls180.v:2686$431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6501$2205_Y - connect \B $eq$ls180.v:6501$2206_Y - connect \Y $and$ls180.v:6501$2207_Y + connect \A \sdram_choose_req_cmd_payload_we + connect \Y $not$ls180.v:2686$431_Y end - attribute \src "ls180.v:6502.40-6502.98" - cell $and $and$ls180.v:6502$2209 + attribute \src "ls180.v:2686.58-2686.170" + cell $not $not$ls180.v:2686$433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6502$2208_Y - connect \Y $and$ls180.v:6502$2209_Y + connect \A $and$ls180.v:2686$432_Y + connect \Y $not$ls180.v:2686$433_Y end - attribute \src "ls180.v:6502.39-6502.149" - cell $and $and$ls180.v:6502$2211 + attribute \src "ls180.v:2694.11-2694.33" + cell $not $not$ls180.v:2694$436 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6502$2209_Y - connect \B $eq$ls180.v:6502$2210_Y - connect \Y $and$ls180.v:6502$2211_Y + connect \A \sdram_write_available + connect \Y $not$ls180.v:2694$436_Y end - attribute \src "ls180.v:6504.41-6504.96" - cell $and $and$ls180.v:6504$2212 + attribute \src "ls180.v:2724.97-2724.130" + cell $not $not$ls180.v:2724$438 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6504$2212_Y + connect \A \sdram_choose_req_cmd_payload_cas + connect \Y $not$ls180.v:2724$438_Y end - attribute \src "ls180.v:6504.40-6504.147" - cell $and $and$ls180.v:6504$2214 + attribute \src "ls180.v:2724.136-2724.168" + cell $not $not$ls180.v:2724$440 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6504$2212_Y - connect \B $eq$ls180.v:6504$2213_Y - connect \Y $and$ls180.v:6504$2214_Y + connect \A \sdram_choose_req_cmd_payload_we + connect \Y $not$ls180.v:2724$440_Y end - attribute \src "ls180.v:6505.41-6505.99" - cell $and $and$ls180.v:6505$2216 + attribute \src "ls180.v:2724.58-2724.170" + cell $not $not$ls180.v:2724$442 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6505$2215_Y - connect \Y $and$ls180.v:6505$2216_Y + connect \A $and$ls180.v:2724$441_Y + connect \Y $not$ls180.v:2724$442_Y end - attribute \src "ls180.v:6505.40-6505.150" - cell $and $and$ls180.v:6505$2218 + attribute \src "ls180.v:2732.11-2732.32" + cell $not $not$ls180.v:2732$445 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6505$2216_Y - connect \B $eq$ls180.v:6505$2217_Y - connect \Y $and$ls180.v:6505$2218_Y + connect \A \sdram_read_available + connect \Y $not$ls180.v:2732$445_Y end - attribute \src "ls180.v:6507.45-6507.100" - cell $and $and$ls180.v:6507$2219 + attribute \src "ls180.v:2742.87-2742.336" + cell $not $not$ls180.v:2742$457 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6507$2219_Y + connect \A $or$ls180.v:2742$456_Y + connect \Y $not$ls180.v:2742$457_Y end - attribute \src "ls180.v:6507.44-6507.151" - cell $and $and$ls180.v:6507$2221 + attribute \src "ls180.v:2743.40-2743.68" + cell $not $not$ls180.v:2743$460 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6507$2219_Y - connect \B $eq$ls180.v:6507$2220_Y - connect \Y $and$ls180.v:6507$2221_Y + connect \A \sdram_interface_bank0_valid + connect \Y $not$ls180.v:2743$460_Y end - attribute \src "ls180.v:6508.45-6508.103" - cell $and $and$ls180.v:6508$2223 + attribute \src "ls180.v:2743.73-2743.100" + cell $not $not$ls180.v:2743$461 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6508$2222_Y - connect \Y $and$ls180.v:6508$2223_Y + connect \A \sdram_interface_bank0_lock + connect \Y $not$ls180.v:2743$461_Y end - attribute \src "ls180.v:6508.44-6508.154" - cell $and $and$ls180.v:6508$2225 + attribute \src "ls180.v:2747.87-2747.336" + cell $not $not$ls180.v:2747$473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6508$2223_Y - connect \B $eq$ls180.v:6508$2224_Y - connect \Y $and$ls180.v:6508$2225_Y + connect \A $or$ls180.v:2747$472_Y + connect \Y $not$ls180.v:2747$473_Y end - attribute \src "ls180.v:6510.46-6510.101" - cell $and $and$ls180.v:6510$2226 + attribute \src "ls180.v:2748.40-2748.68" + cell $not $not$ls180.v:2748$476 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6510$2226_Y + connect \A \sdram_interface_bank1_valid + connect \Y $not$ls180.v:2748$476_Y end - attribute \src "ls180.v:6510.45-6510.152" - cell $and $and$ls180.v:6510$2228 + attribute \src "ls180.v:2748.73-2748.100" + cell $not $not$ls180.v:2748$477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6510$2226_Y - connect \B $eq$ls180.v:6510$2227_Y - connect \Y $and$ls180.v:6510$2228_Y + connect \A \sdram_interface_bank1_lock + connect \Y $not$ls180.v:2748$477_Y end - attribute \src "ls180.v:6511.46-6511.104" - cell $and $and$ls180.v:6511$2230 + attribute \src "ls180.v:2752.87-2752.336" + cell $not $not$ls180.v:2752$489 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6511$2229_Y - connect \Y $and$ls180.v:6511$2230_Y + connect \A $or$ls180.v:2752$488_Y + connect \Y $not$ls180.v:2752$489_Y end - attribute \src "ls180.v:6511.45-6511.155" - cell $and $and$ls180.v:6511$2232 + attribute \src "ls180.v:2753.40-2753.68" + cell $not $not$ls180.v:2753$492 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6511$2230_Y - connect \B $eq$ls180.v:6511$2231_Y - connect \Y $and$ls180.v:6511$2232_Y + connect \A \sdram_interface_bank2_valid + connect \Y $not$ls180.v:2753$492_Y end - attribute \src "ls180.v:6513.44-6513.99" - cell $and $and$ls180.v:6513$2233 + attribute \src "ls180.v:2753.73-2753.100" + cell $not $not$ls180.v:2753$493 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6513$2233_Y + connect \A \sdram_interface_bank2_lock + connect \Y $not$ls180.v:2753$493_Y end - attribute \src "ls180.v:6513.43-6513.150" - cell $and $and$ls180.v:6513$2235 + attribute \src "ls180.v:2757.87-2757.336" + cell $not $not$ls180.v:2757$505 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6513$2233_Y - connect \B $eq$ls180.v:6513$2234_Y - connect \Y $and$ls180.v:6513$2235_Y + connect \A $or$ls180.v:2757$504_Y + connect \Y $not$ls180.v:2757$505_Y end - attribute \src "ls180.v:6514.44-6514.102" - cell $and $and$ls180.v:6514$2237 + attribute \src "ls180.v:2758.40-2758.68" + cell $not $not$ls180.v:2758$508 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6514$2236_Y - connect \Y $and$ls180.v:6514$2237_Y + connect \A \sdram_interface_bank3_valid + connect \Y $not$ls180.v:2758$508_Y end - attribute \src "ls180.v:6514.43-6514.153" - cell $and $and$ls180.v:6514$2239 + attribute \src "ls180.v:2758.73-2758.100" + cell $not $not$ls180.v:2758$509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6514$2237_Y - connect \B $eq$ls180.v:6514$2238_Y - connect \Y $and$ls180.v:6514$2239_Y + connect \A \sdram_interface_bank3_lock + connect \Y $not$ls180.v:2758$509_Y end - attribute \src "ls180.v:6516.41-6516.96" - cell $and $and$ls180.v:6516$2240 + attribute \src "ls180.v:2762.123-2762.372" + cell $not $not$ls180.v:2762$522 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6516$2240_Y + connect \A $or$ls180.v:2762$521_Y + connect \Y $not$ls180.v:2762$522_Y end - attribute \src "ls180.v:6516.40-6516.147" - cell $and $and$ls180.v:6516$2242 + attribute \src "ls180.v:2762.497-2762.746" + cell $not $not$ls180.v:2762$538 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6516$2240_Y - connect \B $eq$ls180.v:6516$2241_Y - connect \Y $and$ls180.v:6516$2242_Y + connect \A $or$ls180.v:2762$537_Y + connect \Y $not$ls180.v:2762$538_Y end - attribute \src "ls180.v:6517.41-6517.99" - cell $and $and$ls180.v:6517$2244 + attribute \src "ls180.v:2762.871-2762.1120" + cell $not $not$ls180.v:2762$554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6517$2243_Y - connect \Y $and$ls180.v:6517$2244_Y + connect \A $or$ls180.v:2762$553_Y + connect \Y $not$ls180.v:2762$554_Y end - attribute \src "ls180.v:6517.40-6517.150" - cell $and $and$ls180.v:6517$2246 + attribute \src "ls180.v:2762.1245-2762.1494" + cell $not $not$ls180.v:2762$570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6517$2244_Y - connect \B $eq$ls180.v:6517$2245_Y - connect \Y $and$ls180.v:6517$2246_Y + connect \A $or$ls180.v:2762$569_Y + connect \Y $not$ls180.v:2762$570_Y end - attribute \src "ls180.v:6519.40-6519.95" - cell $and $and$ls180.v:6519$2247 + attribute \src "ls180.v:2784.27-2784.40" + cell $not $not$ls180.v:2784$576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B \builder_interface13_bank_bus_we - connect \Y $and$ls180.v:6519$2247_Y + connect \A \wb_sdram_cyc + connect \Y $not$ls180.v:2784$576_Y end - attribute \src "ls180.v:6519.39-6519.146" - cell $and $and$ls180.v:6519$2249 + attribute \src "ls180.v:2823.25-2823.40" + cell $not $not$ls180.v:2823$581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6519$2247_Y - connect \B $eq$ls180.v:6519$2248_Y - connect \Y $and$ls180.v:6519$2249_Y + connect \A \converter_skip + connect \Y $not$ls180.v:2823$581_Y end - attribute \src "ls180.v:6520.40-6520.98" - cell $and $and$ls180.v:6520$2251 + attribute \src "ls180.v:2824.25-2824.40" + cell $not $not$ls180.v:2824$582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank13_sel - connect \B $not$ls180.v:6520$2250_Y - connect \Y $and$ls180.v:6520$2251_Y + connect \A \converter_skip + connect \Y $not$ls180.v:2824$582_Y end - attribute \src "ls180.v:6520.39-6520.149" - cell $and $and$ls180.v:6520$2253 + attribute \src "ls180.v:2849.22-2849.38" + cell $not $not$ls180.v:2849$588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6520$2251_Y - connect \B $eq$ls180.v:6520$2252_Y - connect \Y $and$ls180.v:6520$2253_Y + connect \A \litedram_wb_cyc + connect \Y $not$ls180.v:2849$588_Y end - attribute \src "ls180.v:6532.46-6532.101" - cell $and $and$ls180.v:6532$2255 + attribute \src "ls180.v:2850.25-2850.40" + cell $not $not$ls180.v:2850$589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank14_sel - connect \B \builder_interface14_bank_bus_we - connect \Y $and$ls180.v:6532$2255_Y + connect \A \litedram_wb_we + connect \Y $not$ls180.v:2850$589_Y end - attribute \src "ls180.v:6532.45-6532.152" - cell $and $and$ls180.v:6532$2257 + attribute \src "ls180.v:2851.65-2851.78" + cell $not $not$ls180.v:2851$591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6532$2255_Y - connect \B $eq$ls180.v:6532$2256_Y - connect \Y $and$ls180.v:6532$2257_Y + connect \A \cmd_consumed + connect \Y $not$ls180.v:2851$591_Y end - attribute \src "ls180.v:6533.46-6533.104" - cell $and $and$ls180.v:6533$2259 + attribute \src "ls180.v:2852.87-2852.102" + cell $not $not$ls180.v:2852$595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank14_sel - connect \B $not$ls180.v:6533$2258_Y - connect \Y $and$ls180.v:6533$2259_Y + connect \A \wdata_consumed + connect \Y $not$ls180.v:2852$595_Y end - attribute \src "ls180.v:6533.45-6533.155" - cell $and $and$ls180.v:6533$2261 + attribute \src "ls180.v:2853.63-2853.83" + cell $not $not$ls180.v:2853$598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6533$2259_Y - connect \B $eq$ls180.v:6533$2260_Y - connect \Y $and$ls180.v:6533$2261_Y + connect \A \port_cmd_payload_we + connect \Y $not$ls180.v:2853$598_Y end - attribute \src "ls180.v:6535.46-6535.101" - cell $and $and$ls180.v:6535$2262 + attribute \src "ls180.v:2854.71-2854.86" + cell $not $not$ls180.v:2854$601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank14_sel - connect \B \builder_interface14_bank_bus_we - connect \Y $and$ls180.v:6535$2262_Y + connect \A \litedram_wb_we + connect \Y $not$ls180.v:2854$601_Y end - attribute \src "ls180.v:6535.45-6535.152" - cell $and $and$ls180.v:6535$2264 + attribute \src "ls180.v:2870.25-2870.44" + cell $not $not$ls180.v:2870$610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6535$2262_Y - connect \B $eq$ls180.v:6535$2263_Y - connect \Y $and$ls180.v:6535$2264_Y + connect \A \tx_fifo_sink_ready + connect \Y $not$ls180.v:2870$610_Y end - attribute \src "ls180.v:6536.46-6536.104" - cell $and $and$ls180.v:6536$2266 + attribute \src "ls180.v:2871.26-2871.47" + cell $not $not$ls180.v:2871$611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank14_sel - connect \B $not$ls180.v:6536$2265_Y - connect \Y $and$ls180.v:6536$2266_Y + connect \A \tx_fifo_source_valid + connect \Y $not$ls180.v:2871$611_Y end - attribute \src "ls180.v:6536.45-6536.155" - cell $and $and$ls180.v:6536$2268 + attribute \src "ls180.v:2877.22-2877.41" + cell $not $not$ls180.v:2877$612 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6536$2266_Y - connect \B $eq$ls180.v:6536$2267_Y - connect \Y $and$ls180.v:6536$2268_Y + connect \A \tx_fifo_sink_ready + connect \Y $not$ls180.v:2877$612_Y end - attribute \src "ls180.v:6538.46-6538.101" - cell $and $and$ls180.v:6538$2269 + attribute \src "ls180.v:2883.26-2883.47" + cell $not $not$ls180.v:2883$613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank14_sel - connect \B \builder_interface14_bank_bus_we - connect \Y $and$ls180.v:6538$2269_Y + connect \A \rx_fifo_source_valid + connect \Y $not$ls180.v:2883$613_Y end - attribute \src "ls180.v:6538.45-6538.152" - cell $and $and$ls180.v:6538$2271 + attribute \src "ls180.v:2884.25-2884.44" + cell $not $not$ls180.v:2884$614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6538$2269_Y - connect \B $eq$ls180.v:6538$2270_Y - connect \Y $and$ls180.v:6538$2271_Y + connect \A \rx_fifo_sink_ready + connect \Y $not$ls180.v:2884$614_Y end - attribute \src "ls180.v:6539.46-6539.104" - cell $and $and$ls180.v:6539$2273 + attribute \src "ls180.v:2887.22-2887.43" + cell $not $not$ls180.v:2887$617 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank14_sel - connect \B $not$ls180.v:6539$2272_Y - connect \Y $and$ls180.v:6539$2273_Y + connect \A \rx_fifo_source_valid + connect \Y $not$ls180.v:2887$617_Y end - attribute \src "ls180.v:6539.45-6539.155" - cell $and $and$ls180.v:6539$2275 + attribute \src "ls180.v:2925.61-2925.78" + cell $not $not$ls180.v:2925$627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6539$2273_Y - connect \B $eq$ls180.v:6539$2274_Y - connect \Y $and$ls180.v:6539$2275_Y + connect \A \tx_fifo_readable + connect \Y $not$ls180.v:2925$627_Y end - attribute \src "ls180.v:6541.46-6541.101" - cell $and $and$ls180.v:6541$2276 + attribute \src "ls180.v:2955.61-2955.78" + cell $not $not$ls180.v:2955$638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank14_sel - connect \B \builder_interface14_bank_bus_we - connect \Y $and$ls180.v:6541$2276_Y + connect \A \rx_fifo_readable + connect \Y $not$ls180.v:2955$638_Y end - attribute \src "ls180.v:6541.45-6541.152" - cell $and $and$ls180.v:6541$2278 + attribute \src "ls180.v:3150.81-3150.104" + cell $not $not$ls180.v:3150$688 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6541$2276_Y - connect \B $eq$ls180.v:6541$2277_Y - connect \Y $and$ls180.v:6541$2278_Y + connect \A \libresocsim_shared_ack + connect \Y $not$ls180.v:3150$688_Y end - attribute \src "ls180.v:6542.46-6542.104" - cell $and $and$ls180.v:6542$2280 + attribute \src "ls180.v:3167.71-3167.106" + cell $not $not$ls180.v:3167$712 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_csrbank14_sel - connect \B $not$ls180.v:6542$2279_Y - connect \Y $and$ls180.v:6542$2280_Y + connect \A \libresocsim_interface0_bank_bus_we + connect \Y $not$ls180.v:3167$712_Y end - attribute \src "ls180.v:6542.45-6542.155" - cell $and $and$ls180.v:6542$2282 + attribute \src "ls180.v:3170.73-3170.108" + cell $not $not$ls180.v:3170$719 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6542$2280_Y - connect \B $eq$ls180.v:6542$2281_Y - connect \Y $and$ls180.v:6542$2282_Y + connect \A \libresocsim_interface0_bank_bus_we + connect \Y $not$ls180.v:3170$719_Y end - attribute \src "ls180.v:6923.109-6923.178" - cell $and $and$ls180.v:6923$2320 + attribute \src "ls180.v:3173.73-3173.108" + cell $not $not$ls180.v:3173$726 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:6923$2319_Y - connect \Y $and$ls180.v:6923$2320_Y + connect \A \libresocsim_interface0_bank_bus_we + connect \Y $not$ls180.v:3173$726_Y end - attribute \src "ls180.v:6923.184-6923.253" - cell $and $and$ls180.v:6923$2323 + attribute \src "ls180.v:3176.73-3176.108" + cell $not $not$ls180.v:3176$733 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:6923$2322_Y - connect \Y $and$ls180.v:6923$2323_Y + connect \A \libresocsim_interface0_bank_bus_we + connect \Y $not$ls180.v:3176$733_Y end - attribute \src "ls180.v:6923.259-6923.328" - cell $and $and$ls180.v:6923$2326 + attribute \src "ls180.v:3179.73-3179.108" + cell $not $not$ls180.v:3179$740 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:6923$2325_Y - connect \Y $and$ls180.v:6923$2326_Y + connect \A \libresocsim_interface0_bank_bus_we + connect \Y $not$ls180.v:3179$740_Y end - attribute \src "ls180.v:6923.40-6923.331" - cell $and $and$ls180.v:6923$2329 + attribute \src "ls180.v:3182.76-3182.111" + cell $not $not$ls180.v:3182$747 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:6923$2318_Y - connect \B $not$ls180.v:6923$2328_Y - connect \Y $and$ls180.v:6923$2329_Y + connect \A \libresocsim_interface0_bank_bus_we + connect \Y $not$ls180.v:3182$747_Y end - attribute \src "ls180.v:6923.39-6923.354" - cell $and $and$ls180.v:6923$2330 + attribute \src "ls180.v:3185.76-3185.111" + cell $not $not$ls180.v:3185$754 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6923$2329_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:6923$2330_Y + connect \A \libresocsim_interface0_bank_bus_we + connect \Y $not$ls180.v:3185$754_Y end - attribute \src "ls180.v:6947.109-6947.178" - cell $and $and$ls180.v:6947$2336 + attribute \src "ls180.v:3188.76-3188.111" + cell $not $not$ls180.v:3188$761 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:6947$2335_Y - connect \Y $and$ls180.v:6947$2336_Y + connect \A \libresocsim_interface0_bank_bus_we + connect \Y $not$ls180.v:3188$761_Y end - attribute \src "ls180.v:6947.184-6947.253" - cell $and $and$ls180.v:6947$2339 + attribute \src "ls180.v:3191.76-3191.111" + cell $not $not$ls180.v:3191$768 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:6947$2338_Y - connect \Y $and$ls180.v:6947$2339_Y + connect \A \libresocsim_interface0_bank_bus_we + connect \Y $not$ls180.v:3191$768_Y end - attribute \src "ls180.v:6947.259-6947.328" - cell $and $and$ls180.v:6947$2342 + attribute \src "ls180.v:3205.68-3205.103" + cell $not $not$ls180.v:3205$776 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:6947$2341_Y - connect \Y $and$ls180.v:6947$2342_Y + connect \A \libresocsim_interface1_bank_bus_we + connect \Y $not$ls180.v:3205$776_Y end - attribute \src "ls180.v:6947.40-6947.331" - cell $and $and$ls180.v:6947$2345 + attribute \src "ls180.v:3208.67-3208.102" + cell $not $not$ls180.v:3208$783 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:6947$2334_Y - connect \B $not$ls180.v:6947$2344_Y - connect \Y $and$ls180.v:6947$2345_Y + connect \A \libresocsim_interface1_bank_bus_we + connect \Y $not$ls180.v:3208$783_Y end - attribute \src "ls180.v:6947.39-6947.354" - cell $and $and$ls180.v:6947$2346 + attribute \src "ls180.v:3211.69-3211.104" + cell $not $not$ls180.v:3211$790 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6947$2345_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:6947$2346_Y + connect \A \libresocsim_interface1_bank_bus_we + connect \Y $not$ls180.v:3211$790_Y end - attribute \src "ls180.v:6971.109-6971.178" - cell $and $and$ls180.v:6971$2352 + attribute \src "ls180.v:3219.68-3219.103" + cell $not $not$ls180.v:3219$798 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:6971$2351_Y - connect \Y $and$ls180.v:6971$2352_Y + connect \A \libresocsim_interface2_bank_bus_we + connect \Y $not$ls180.v:3219$798_Y end - attribute \src "ls180.v:6971.184-6971.253" - cell $and $and$ls180.v:6971$2355 + attribute \src "ls180.v:3222.67-3222.102" + cell $not $not$ls180.v:3222$805 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:6971$2354_Y - connect \Y $and$ls180.v:6971$2355_Y + connect \A \libresocsim_interface2_bank_bus_we + connect \Y $not$ls180.v:3222$805_Y end - attribute \src "ls180.v:6971.259-6971.328" - cell $and $and$ls180.v:6971$2358 + attribute \src "ls180.v:3225.69-3225.104" + cell $not $not$ls180.v:3225$812 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \B $eq$ls180.v:6971$2357_Y - connect \Y $and$ls180.v:6971$2358_Y + connect \A \libresocsim_interface2_bank_bus_we + connect \Y $not$ls180.v:3225$812_Y end - attribute \src "ls180.v:6971.40-6971.331" - cell $and $and$ls180.v:6971$2361 + attribute \src "ls180.v:3233.67-3233.102" + cell $not $not$ls180.v:3233$820 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:6971$2350_Y - connect \B $not$ls180.v:6971$2360_Y - connect \Y $and$ls180.v:6971$2361_Y + connect \A \libresocsim_interface3_bank_bus_we + connect \Y $not$ls180.v:3233$820_Y end - attribute \src "ls180.v:6971.39-6971.354" - cell $and $and$ls180.v:6971$2362 + attribute \src "ls180.v:3236.66-3236.101" + cell $not $not$ls180.v:3236$827 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6971$2361_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:6971$2362_Y + connect \A \libresocsim_interface3_bank_bus_we + connect \Y $not$ls180.v:3236$827_Y end - attribute \src "ls180.v:6995.109-6995.178" - cell $and $and$ls180.v:6995$2368 + attribute \src "ls180.v:3247.78-3247.113" + cell $not $not$ls180.v:3247$835 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \B $eq$ls180.v:6995$2367_Y - connect \Y $and$ls180.v:6995$2368_Y + connect \A \libresocsim_interface4_bank_bus_we + connect \Y $not$ls180.v:3247$835_Y end - attribute \src "ls180.v:6995.184-6995.253" - cell $and $and$ls180.v:6995$2371 + attribute \src "ls180.v:3250.82-3250.117" + cell $not $not$ls180.v:3250$842 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \B $eq$ls180.v:6995$2370_Y - connect \Y $and$ls180.v:6995$2371_Y + connect \A \libresocsim_interface4_bank_bus_we + connect \Y $not$ls180.v:3250$842_Y end - attribute \src "ls180.v:6995.259-6995.328" - cell $and $and$ls180.v:6995$2374 + attribute \src "ls180.v:3253.63-3253.98" + cell $not $not$ls180.v:3253$849 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \B $eq$ls180.v:6995$2373_Y - connect \Y $and$ls180.v:6995$2374_Y + connect \A \libresocsim_interface4_bank_bus_we + connect \Y $not$ls180.v:3253$849_Y end - attribute \src "ls180.v:6995.40-6995.331" - cell $and $and$ls180.v:6995$2377 + attribute \src "ls180.v:3256.82-3256.117" + cell $not $not$ls180.v:3256$856 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:6995$2366_Y - connect \B $not$ls180.v:6995$2376_Y - connect \Y $and$ls180.v:6995$2377_Y + connect \A \libresocsim_interface4_bank_bus_we + connect \Y $not$ls180.v:3256$856_Y end - attribute \src "ls180.v:6995.39-6995.354" - cell $and $and$ls180.v:6995$2378 + attribute \src "ls180.v:3259.82-3259.117" + cell $not $not$ls180.v:3259$863 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:6995$2377_Y - connect \B \main_port_cmd_valid - connect \Y $and$ls180.v:6995$2378_Y + connect \A \libresocsim_interface4_bank_bus_we + connect \Y $not$ls180.v:3259$863_Y end - attribute \src "ls180.v:7200.39-7200.104" - cell $and $and$ls180.v:7200$2390 + attribute \src "ls180.v:3262.83-3262.118" + cell $not $not$ls180.v:3262$870 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7200$2390_Y + connect \A \libresocsim_interface4_bank_bus_we + connect \Y $not$ls180.v:3262$870_Y end - attribute \src "ls180.v:7200.38-7200.145" - cell $and $and$ls180.v:7200$2391 + attribute \src "ls180.v:3265.81-3265.116" + cell $not $not$ls180.v:3265$877 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7200$2390_Y - connect \B \main_sdram_choose_req_cmd_payload_cas - connect \Y $and$ls180.v:7200$2391_Y + connect \A \libresocsim_interface4_bank_bus_we + connect \Y $not$ls180.v:3265$877_Y end - attribute \src "ls180.v:7203.39-7203.104" - cell $and $and$ls180.v:7203$2392 + attribute \src "ls180.v:3268.81-3268.116" + cell $not $not$ls180.v:3268$884 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7203$2392_Y + connect \A \libresocsim_interface4_bank_bus_we + connect \Y $not$ls180.v:3268$884_Y end - attribute \src "ls180.v:7203.38-7203.145" - cell $and $and$ls180.v:7203$2393 + attribute \src "ls180.v:3271.81-3271.116" + cell $not $not$ls180.v:3271$891 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7203$2392_Y - connect \B \main_sdram_choose_req_cmd_payload_cas - connect \Y $and$ls180.v:7203$2393_Y + connect \A \libresocsim_interface4_bank_bus_we + connect \Y $not$ls180.v:3271$891_Y end - attribute \src "ls180.v:7206.39-7206.82" - cell $and $and$ls180.v:7206$2394 + attribute \src "ls180.v:3274.81-3274.116" + cell $not $not$ls180.v:3274$898 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_cmd_valid - connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7206$2394_Y + connect \A \libresocsim_interface4_bank_bus_we + connect \Y $not$ls180.v:3274$898_Y end - attribute \src "ls180.v:7206.38-7206.112" - cell $and $and$ls180.v:7206$2395 + attribute \src "ls180.v:3292.70-3292.105" + cell $not $not$ls180.v:3292$906 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7206$2394_Y - connect \B \main_sdram_cmd_payload_cas - connect \Y $and$ls180.v:7206$2395_Y + connect \A \libresocsim_interface5_bank_bus_we + connect \Y $not$ls180.v:3292$906_Y end - attribute \src "ls180.v:7217.39-7217.104" - cell $and $and$ls180.v:7217$2397 + attribute \src "ls180.v:3295.70-3295.105" + cell $not $not$ls180.v:3295$913 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7217$2397_Y + connect \A \libresocsim_interface5_bank_bus_we + connect \Y $not$ls180.v:3295$913_Y end - attribute \src "ls180.v:7217.38-7217.145" - cell $and $and$ls180.v:7217$2398 + attribute \src "ls180.v:3298.70-3298.105" + cell $not $not$ls180.v:3298$920 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7217$2397_Y - connect \B \main_sdram_choose_req_cmd_payload_ras - connect \Y $and$ls180.v:7217$2398_Y + connect \A \libresocsim_interface5_bank_bus_we + connect \Y $not$ls180.v:3298$920_Y end - attribute \src "ls180.v:7220.39-7220.104" - cell $and $and$ls180.v:7220$2399 + attribute \src "ls180.v:3301.70-3301.105" + cell $not $not$ls180.v:3301$927 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7220$2399_Y + connect \A \libresocsim_interface5_bank_bus_we + connect \Y $not$ls180.v:3301$927_Y end - attribute \src "ls180.v:7220.38-7220.145" - cell $and $and$ls180.v:7220$2400 + attribute \src "ls180.v:3304.72-3304.107" + cell $not $not$ls180.v:3304$934 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7220$2399_Y - connect \B \main_sdram_choose_req_cmd_payload_ras - connect \Y $and$ls180.v:7220$2400_Y + connect \A \libresocsim_interface5_bank_bus_we + connect \Y $not$ls180.v:3304$934_Y end - attribute \src "ls180.v:7223.39-7223.82" - cell $and $and$ls180.v:7223$2401 + attribute \src "ls180.v:3307.72-3307.107" + cell $not $not$ls180.v:3307$941 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_cmd_valid - connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7223$2401_Y + connect \A \libresocsim_interface5_bank_bus_we + connect \Y $not$ls180.v:3307$941_Y end - attribute \src "ls180.v:7223.38-7223.112" - cell $and $and$ls180.v:7223$2402 + attribute \src "ls180.v:3310.72-3310.107" + cell $not $not$ls180.v:3310$948 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7223$2401_Y - connect \B \main_sdram_cmd_payload_ras - connect \Y $and$ls180.v:7223$2402_Y + connect \A \libresocsim_interface5_bank_bus_we + connect \Y $not$ls180.v:3310$948_Y end - attribute \src "ls180.v:7234.39-7234.104" - cell $and $and$ls180.v:7234$2404 + attribute \src "ls180.v:3313.72-3313.107" + cell $not $not$ls180.v:3313$955 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7234$2404_Y + connect \A \libresocsim_interface5_bank_bus_we + connect \Y $not$ls180.v:3313$955_Y end - attribute \src "ls180.v:7234.38-7234.144" - cell $and $and$ls180.v:7234$2405 + attribute \src "ls180.v:3316.68-3316.103" + cell $not $not$ls180.v:3316$962 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7234$2404_Y - connect \B \main_sdram_choose_req_cmd_payload_we - connect \Y $and$ls180.v:7234$2405_Y + connect \A \libresocsim_interface5_bank_bus_we + connect \Y $not$ls180.v:3316$962_Y end - attribute \src "ls180.v:7237.39-7237.104" - cell $and $and$ls180.v:7237$2406 + attribute \src "ls180.v:3319.78-3319.113" + cell $not $not$ls180.v:3319$969 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7237$2406_Y + connect \A \libresocsim_interface5_bank_bus_we + connect \Y $not$ls180.v:3319$969_Y end - attribute \src "ls180.v:7237.38-7237.144" - cell $and $and$ls180.v:7237$2407 + attribute \src "ls180.v:3322.71-3322.106" + cell $not $not$ls180.v:3322$976 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7237$2406_Y - connect \B \main_sdram_choose_req_cmd_payload_we - connect \Y $and$ls180.v:7237$2407_Y + connect \A \libresocsim_interface5_bank_bus_we + connect \Y $not$ls180.v:3322$976_Y end - attribute \src "ls180.v:7240.39-7240.82" - cell $and $and$ls180.v:7240$2408 + attribute \src "ls180.v:3325.71-3325.106" + cell $not $not$ls180.v:3325$983 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_cmd_valid - connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7240$2408_Y + connect \A \libresocsim_interface5_bank_bus_we + connect \Y $not$ls180.v:3325$983_Y end - attribute \src "ls180.v:7240.38-7240.111" - cell $and $and$ls180.v:7240$2409 + attribute \src "ls180.v:3328.71-3328.106" + cell $not $not$ls180.v:3328$990 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7240$2408_Y - connect \B \main_sdram_cmd_payload_we - connect \Y $and$ls180.v:7240$2409_Y + connect \A \libresocsim_interface5_bank_bus_we + connect \Y $not$ls180.v:3328$990_Y end - attribute \src "ls180.v:7251.39-7251.104" - cell $and $and$ls180.v:7251$2411 + attribute \src "ls180.v:3331.71-3331.106" + cell $not $not$ls180.v:3331$997 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7251$2411_Y + connect \A \libresocsim_interface5_bank_bus_we + connect \Y $not$ls180.v:3331$997_Y end - attribute \src "ls180.v:7251.38-7251.149" - cell $and $and$ls180.v:7251$2412 + attribute \src "ls180.v:3334.75-3334.110" + cell $not $not$ls180.v:3334$1004 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7251$2411_Y - connect \B \main_sdram_choose_req_cmd_payload_is_read - connect \Y $and$ls180.v:7251$2412_Y + connect \A \libresocsim_interface5_bank_bus_we + connect \Y $not$ls180.v:3334$1004_Y end - attribute \src "ls180.v:7254.39-7254.104" - cell $and $and$ls180.v:7254$2413 + attribute \src "ls180.v:3337.76-3337.111" + cell $not $not$ls180.v:3337$1011 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7254$2413_Y + connect \A \libresocsim_interface5_bank_bus_we + connect \Y $not$ls180.v:3337$1011_Y end - attribute \src "ls180.v:7254.38-7254.149" - cell $and $and$ls180.v:7254$2414 + attribute \src "ls180.v:3340.75-3340.110" + cell $not $not$ls180.v:3340$1018 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7254$2413_Y - connect \B \main_sdram_choose_req_cmd_payload_is_read - connect \Y $and$ls180.v:7254$2414_Y + connect \A \libresocsim_interface5_bank_bus_we + connect \Y $not$ls180.v:3340$1018_Y end - attribute \src "ls180.v:7257.39-7257.82" - cell $and $and$ls180.v:7257$2415 + attribute \src "ls180.v:3360.48-3360.83" + cell $not $not$ls180.v:3360$1026 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_cmd_valid - connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7257$2415_Y + connect \A \libresocsim_interface6_bank_bus_we + connect \Y $not$ls180.v:3360$1026_Y end - attribute \src "ls180.v:7257.38-7257.116" - cell $and $and$ls180.v:7257$2416 + attribute \src "ls180.v:3363.71-3363.106" + cell $not $not$ls180.v:3363$1033 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7257$2415_Y - connect \B \main_sdram_cmd_payload_is_read - connect \Y $and$ls180.v:7257$2416_Y + connect \A \libresocsim_interface6_bank_bus_we + connect \Y $not$ls180.v:3363$1033_Y end - attribute \src "ls180.v:7268.39-7268.104" - cell $and $and$ls180.v:7268$2418 + attribute \src "ls180.v:3366.72-3366.107" + cell $not $not$ls180.v:3366$1040 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7268$2418_Y + connect \A \libresocsim_interface6_bank_bus_we + connect \Y $not$ls180.v:3366$1040_Y end - attribute \src "ls180.v:7268.38-7268.150" - cell $and $and$ls180.v:7268$2419 + attribute \src "ls180.v:3369.63-3369.98" + cell $not $not$ls180.v:3369$1047 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7268$2418_Y - connect \B \main_sdram_choose_req_cmd_payload_is_write - connect \Y $and$ls180.v:7268$2419_Y + connect \A \libresocsim_interface6_bank_bus_we + connect \Y $not$ls180.v:3369$1047_Y end - attribute \src "ls180.v:7271.39-7271.104" - cell $and $and$ls180.v:7271$2420 + attribute \src "ls180.v:3372.64-3372.99" + cell $not $not$ls180.v:3372$1054 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \B \main_sdram_choose_req_cmd_ready - connect \Y $and$ls180.v:7271$2420_Y + connect \A \libresocsim_interface6_bank_bus_we + connect \Y $not$ls180.v:3372$1054_Y end - attribute \src "ls180.v:7271.38-7271.150" - cell $and $and$ls180.v:7271$2421 + attribute \src "ls180.v:3375.75-3375.110" + cell $not $not$ls180.v:3375$1061 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7271$2420_Y - connect \B \main_sdram_choose_req_cmd_payload_is_write - connect \Y $and$ls180.v:7271$2421_Y + connect \A \libresocsim_interface6_bank_bus_we + connect \Y $not$ls180.v:3375$1061_Y end - attribute \src "ls180.v:7274.39-7274.82" - cell $and $and$ls180.v:7274$2422 + attribute \src "ls180.v:3378.72-3378.107" + cell $not $not$ls180.v:3378$1068 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_cmd_valid - connect \B \main_sdram_cmd_ready - connect \Y $and$ls180.v:7274$2422_Y + connect \A \libresocsim_interface6_bank_bus_we + connect \Y $not$ls180.v:3378$1068_Y end - attribute \src "ls180.v:7274.38-7274.117" - cell $and $and$ls180.v:7274$2423 + attribute \src "ls180.v:3381.71-3381.106" + cell $not $not$ls180.v:3381$1075 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7274$2422_Y - connect \B \main_sdram_cmd_payload_is_write - connect \Y $and$ls180.v:7274$2423_Y + connect \A \libresocsim_interface6_bank_bus_we + connect \Y $not$ls180.v:3381$1075_Y end - attribute \src "ls180.v:7493.18-7493.68" - cell $and $and$ls180.v:7493$2430 + attribute \src "ls180.v:3394.77-3394.112" + cell $not $not$ls180.v:3394$1083 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_dfi_p0_wrdata_en - connect \B \main_dfi_p0_wrdata_mask [0] - connect \Y $and$ls180.v:7493$2430_Y + connect \A \libresocsim_interface7_bank_bus_we + connect \Y $not$ls180.v:3394$1083_Y end - attribute \src "ls180.v:7494.18-7494.68" - cell $and $and$ls180.v:7494$2431 + attribute \src "ls180.v:3397.77-3397.112" + cell $not $not$ls180.v:3397$1090 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_dfi_p0_wrdata_en - connect \B \main_dfi_p0_wrdata_mask [1] - connect \Y $and$ls180.v:7494$2431_Y + connect \A \libresocsim_interface7_bank_bus_we + connect \Y $not$ls180.v:3397$1090_Y end - attribute \src "ls180.v:7496.17-7496.67" - cell $and $and$ls180.v:7496$2433 + attribute \src "ls180.v:3400.77-3400.112" + cell $not $not$ls180.v:3400$1097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7496$2432_Y - connect \B \main_sdphy_sdpads_clk - connect \Y $and$ls180.v:7496$2433_Y + connect \A \libresocsim_interface7_bank_bus_we + connect \Y $not$ls180.v:3400$1097_Y end - attribute \src "ls180.v:7575.8-7575.67" - cell $and $and$ls180.v:7575$2464 + attribute \src "ls180.v:3403.77-3403.112" + cell $not $not$ls180.v:3403$1104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_cyc - connect \B \main_libresocsim_ram_bus_stb - connect \Y $and$ls180.v:7575$2464_Y + connect \A \libresocsim_interface7_bank_bus_we + connect \Y $not$ls180.v:3403$1104_Y end - attribute \src "ls180.v:7575.7-7575.102" - cell $and $and$ls180.v:7575$2466 + attribute \src "ls180.v:3763.68-3763.317" + cell $not $not$ls180.v:3763$1146 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7575$2464_Y - connect \B $not$ls180.v:7575$2465_Y - connect \Y $and$ls180.v:7575$2466_Y + connect \A $or$ls180.v:3763$1145_Y + connect \Y $not$ls180.v:3763$1146_Y end - attribute \src "ls180.v:7594.7-7594.75" - cell $and $and$ls180.v:7594$2470 + attribute \src "ls180.v:3787.68-3787.317" + cell $not $not$ls180.v:3787$1162 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7594$2469_Y - connect \B \main_libresocsim_zero_old_trigger - connect \Y $and$ls180.v:7594$2470_Y + connect \A $or$ls180.v:3787$1161_Y + connect \Y $not$ls180.v:3787$1162_Y end - attribute \src "ls180.v:7598.8-7598.59" - cell $and $and$ls180.v:7598$2471 + attribute \src "ls180.v:3811.68-3811.317" + cell $not $not$ls180.v:3811$1178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_ram_bus_ram_bus_cyc - connect \B \main_ram_bus_ram_bus_stb - connect \Y $and$ls180.v:7598$2471_Y + connect \A $or$ls180.v:3811$1177_Y + connect \Y $not$ls180.v:3811$1178_Y end - attribute \src "ls180.v:7598.7-7598.90" - cell $and $and$ls180.v:7598$2473 + attribute \src "ls180.v:3835.68-3835.317" + cell $not $not$ls180.v:3835$1194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7598$2471_Y - connect \B $not$ls180.v:7598$2472_Y - connect \Y $and$ls180.v:7598$2473_Y + connect \A $or$ls180.v:3835$1193_Y + connect \Y $not$ls180.v:3835$1194_Y end - attribute \src "ls180.v:7606.7-7606.56" - cell $and $and$ls180.v:7606$2475 + attribute \src "ls180.v:4357.62-4357.86" + cell $not $not$ls180.v:4357$1283 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_timer_wait - connect \B $not$ls180.v:7606$2474_Y - connect \Y $and$ls180.v:7606$2475_Y + connect \A \libresocsim_ram_bus_ack + connect \Y $not$ls180.v:4357$1283_Y end - attribute \src "ls180.v:7634.7-7634.75" - cell $and $and$ls180.v:7634$2482 + attribute \src "ls180.v:4376.8-4376.33" + cell $not $not$ls180.v:4376$1287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_start1 - connect \B $eq$ls180.v:7634$2481_Y - connect \Y $and$ls180.v:7634$2482_Y + connect \A \libresocsim_zero_trigger + connect \Y $not$ls180.v:4376$1287_Y end - attribute \src "ls180.v:7676.8-7676.131" - cell $and $and$ls180.v:7676$2488 + attribute \src "ls180.v:4380.54-4380.74" + cell $not $not$ls180.v:4380$1290 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we - connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \Y $and$ls180.v:7676$2488_Y + connect \A \ram_bus_ram_bus_ack + connect \Y $not$ls180.v:4380$1290_Y end - attribute \src "ls180.v:7676.7-7676.190" - cell $and $and$ls180.v:7676$2490 + attribute \src "ls180.v:4388.27-4388.45" + cell $not $not$ls180.v:4388$1292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7676$2488_Y - connect \B $not$ls180.v:7676$2489_Y - connect \Y $and$ls180.v:7676$2490_Y + connect \A \sdram_timer_done0 + connect \Y $not$ls180.v:4388$1292_Y end - attribute \src "ls180.v:7682.8-7682.131" - cell $and $and$ls180.v:7682$2493 + attribute \src "ls180.v:4458.126-4458.174" + cell $not $not$ls180.v:4458$1307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we - connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \Y $and$ls180.v:7682$2493_Y + connect \A \sdram_bankmachine0_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:4458$1307_Y end - attribute \src "ls180.v:7682.7-7682.190" - cell $and $and$ls180.v:7682$2495 + attribute \src "ls180.v:4464.126-4464.174" + cell $not $not$ls180.v:4464$1312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7682$2493_Y - connect \B $not$ls180.v:7682$2494_Y - connect \Y $and$ls180.v:7682$2495_Y + connect \A \sdram_bankmachine0_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:4464$1312_Y end - attribute \src "ls180.v:7722.8-7722.131" - cell $and $and$ls180.v:7722$2504 + attribute \src "ls180.v:4465.8-4465.56" + cell $not $not$ls180.v:4465$1314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we - connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \Y $and$ls180.v:7722$2504_Y + connect \A \sdram_bankmachine0_cmd_buffer_lookahead_do_read + connect \Y $not$ls180.v:4465$1314_Y end - attribute \src "ls180.v:7722.7-7722.190" - cell $and $and$ls180.v:7722$2506 + attribute \src "ls180.v:4473.8-4473.51" + cell $not $not$ls180.v:4473$1317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7722$2504_Y - connect \B $not$ls180.v:7722$2505_Y - connect \Y $and$ls180.v:7722$2506_Y + connect \A \sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $not$ls180.v:4473$1317_Y end - attribute \src "ls180.v:7728.8-7728.131" - cell $and $and$ls180.v:7728$2509 + attribute \src "ls180.v:4488.8-4488.41" + cell $not $not$ls180.v:4488$1319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we - connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \Y $and$ls180.v:7728$2509_Y + connect \A \sdram_bankmachine0_twtpcon_ready + connect \Y $not$ls180.v:4488$1319_Y end - attribute \src "ls180.v:7728.7-7728.190" - cell $and $and$ls180.v:7728$2511 + attribute \src "ls180.v:4504.126-4504.174" + cell $not $not$ls180.v:4504$1323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7728$2509_Y - connect \B $not$ls180.v:7728$2510_Y - connect \Y $and$ls180.v:7728$2511_Y + connect \A \sdram_bankmachine1_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:4504$1323_Y end - attribute \src "ls180.v:7768.8-7768.131" - cell $and $and$ls180.v:7768$2520 + attribute \src "ls180.v:4510.126-4510.174" + cell $not $not$ls180.v:4510$1328 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we - connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \Y $and$ls180.v:7768$2520_Y + connect \A \sdram_bankmachine1_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:4510$1328_Y end - attribute \src "ls180.v:7768.7-7768.190" - cell $and $and$ls180.v:7768$2522 + attribute \src "ls180.v:4511.8-4511.56" + cell $not $not$ls180.v:4511$1330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7768$2520_Y - connect \B $not$ls180.v:7768$2521_Y - connect \Y $and$ls180.v:7768$2522_Y + connect \A \sdram_bankmachine1_cmd_buffer_lookahead_do_read + connect \Y $not$ls180.v:4511$1330_Y end - attribute \src "ls180.v:7774.8-7774.131" - cell $and $and$ls180.v:7774$2525 + attribute \src "ls180.v:4519.8-4519.51" + cell $not $not$ls180.v:4519$1333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we - connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \Y $and$ls180.v:7774$2525_Y + connect \A \sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $not$ls180.v:4519$1333_Y end - attribute \src "ls180.v:7774.7-7774.190" - cell $and $and$ls180.v:7774$2527 + attribute \src "ls180.v:4534.8-4534.41" + cell $not $not$ls180.v:4534$1335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7774$2525_Y - connect \B $not$ls180.v:7774$2526_Y - connect \Y $and$ls180.v:7774$2527_Y + connect \A \sdram_bankmachine1_twtpcon_ready + connect \Y $not$ls180.v:4534$1335_Y end - attribute \src "ls180.v:7814.8-7814.131" - cell $and $and$ls180.v:7814$2536 + attribute \src "ls180.v:4550.126-4550.174" + cell $not $not$ls180.v:4550$1339 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we - connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \Y $and$ls180.v:7814$2536_Y + connect \A \sdram_bankmachine2_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:4550$1339_Y end - attribute \src "ls180.v:7814.7-7814.190" - cell $and $and$ls180.v:7814$2538 + attribute \src "ls180.v:4556.126-4556.174" + cell $not $not$ls180.v:4556$1344 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7814$2536_Y - connect \B $not$ls180.v:7814$2537_Y - connect \Y $and$ls180.v:7814$2538_Y + connect \A \sdram_bankmachine2_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:4556$1344_Y end - attribute \src "ls180.v:7820.8-7820.131" - cell $and $and$ls180.v:7820$2541 + attribute \src "ls180.v:4557.8-4557.56" + cell $not $not$ls180.v:4557$1346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we - connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \Y $and$ls180.v:7820$2541_Y + connect \A \sdram_bankmachine2_cmd_buffer_lookahead_do_read + connect \Y $not$ls180.v:4557$1346_Y end - attribute \src "ls180.v:7820.7-7820.190" - cell $and $and$ls180.v:7820$2543 + attribute \src "ls180.v:4565.8-4565.51" + cell $not $not$ls180.v:4565$1349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:7820$2541_Y - connect \B $not$ls180.v:7820$2542_Y - connect \Y $and$ls180.v:7820$2543_Y + connect \A \sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $not$ls180.v:4565$1349_Y end - attribute \src "ls180.v:8017.48-8017.124" - cell $and $and$ls180.v:8017$2568 + attribute \src "ls180.v:4580.8-4580.41" + cell $not $not$ls180.v:4580$1351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8017$2567_Y - connect \B \main_sdram_interface_bank0_wdata_ready - connect \Y $and$ls180.v:8017$2568_Y + connect \A \sdram_bankmachine2_twtpcon_ready + connect \Y $not$ls180.v:4580$1351_Y end - attribute \src "ls180.v:8017.130-8017.206" - cell $and $and$ls180.v:8017$2571 + attribute \src "ls180.v:4596.126-4596.174" + cell $not $not$ls180.v:4596$1355 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8017$2570_Y - connect \B \main_sdram_interface_bank1_wdata_ready - connect \Y $and$ls180.v:8017$2571_Y + connect \A \sdram_bankmachine3_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:4596$1355_Y end - attribute \src "ls180.v:8017.212-8017.288" - cell $and $and$ls180.v:8017$2574 + attribute \src "ls180.v:4602.126-4602.174" + cell $not $not$ls180.v:4602$1360 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8017$2573_Y - connect \B \main_sdram_interface_bank2_wdata_ready - connect \Y $and$ls180.v:8017$2574_Y + connect \A \sdram_bankmachine3_cmd_buffer_lookahead_replace + connect \Y $not$ls180.v:4602$1360_Y end - attribute \src "ls180.v:8017.294-8017.370" - cell $and $and$ls180.v:8017$2577 + attribute \src "ls180.v:4603.8-4603.56" + cell $not $not$ls180.v:4603$1362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8017$2576_Y - connect \B \main_sdram_interface_bank3_wdata_ready - connect \Y $and$ls180.v:8017$2577_Y + connect \A \sdram_bankmachine3_cmd_buffer_lookahead_do_read + connect \Y $not$ls180.v:4603$1362_Y end - attribute \src "ls180.v:8018.49-8018.125" - cell $and $and$ls180.v:8018$2580 + attribute \src "ls180.v:4611.8-4611.51" + cell $not $not$ls180.v:4611$1365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8018$2579_Y - connect \B \main_sdram_interface_bank0_rdata_valid - connect \Y $and$ls180.v:8018$2580_Y + connect \A \sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $not$ls180.v:4611$1365_Y end - attribute \src "ls180.v:8018.131-8018.207" - cell $and $and$ls180.v:8018$2583 + attribute \src "ls180.v:4626.8-4626.41" + cell $not $not$ls180.v:4626$1367 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8018$2582_Y - connect \B \main_sdram_interface_bank1_rdata_valid - connect \Y $and$ls180.v:8018$2583_Y + connect \A \sdram_bankmachine3_twtpcon_ready + connect \Y $not$ls180.v:4626$1367_Y end - attribute \src "ls180.v:8018.213-8018.289" - cell $and $and$ls180.v:8018$2586 + attribute \src "ls180.v:4634.7-4634.17" + cell $not $not$ls180.v:4634$1370 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8018$2585_Y - connect \B \main_sdram_interface_bank2_rdata_valid - connect \Y $and$ls180.v:8018$2586_Y + connect \A \sdram_en0 + connect \Y $not$ls180.v:4634$1370_Y end - attribute \src "ls180.v:8018.295-8018.371" - cell $and $and$ls180.v:8018$2589 + attribute \src "ls180.v:4637.8-4637.24" + cell $not $not$ls180.v:4637$1371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8018$2588_Y - connect \B \main_sdram_interface_bank3_rdata_valid - connect \Y $and$ls180.v:8018$2589_Y + connect \A \sdram_max_time0 + connect \Y $not$ls180.v:4637$1371_Y end - attribute \src "ls180.v:8037.8-8037.49" - cell $and $and$ls180.v:8037$2592 + attribute \src "ls180.v:4641.7-4641.17" + cell $not $not$ls180.v:4641$1373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_port_cmd_valid - connect \B \main_port_cmd_ready - connect \Y $and$ls180.v:8037$2592_Y + connect \A \sdram_en1 + connect \Y $not$ls180.v:4641$1373_Y end - attribute \src "ls180.v:8040.8-8040.53" - cell $and $and$ls180.v:8040$2593 + attribute \src "ls180.v:4644.8-4644.24" + cell $not $not$ls180.v:4644$1374 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_port_wdata_valid - connect \B \main_port_wdata_ready - connect \Y $and$ls180.v:8040$2593_Y + connect \A \sdram_max_time1 + connect \Y $not$ls180.v:4644$1374_Y end - attribute \src "ls180.v:8045.8-8045.59" - cell $and $and$ls180.v:8045$2595 + attribute \src "ls180.v:4763.25-4763.38" + cell $not $not$ls180.v:4763$1376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_uart_phy_sink_valid - connect \B $not$ls180.v:8045$2594_Y - connect \Y $and$ls180.v:8045$2595_Y + connect \A \array_muxed2 + connect \Y $not$ls180.v:4763$1376_Y end - attribute \src "ls180.v:8045.7-8045.90" - cell $and $and$ls180.v:8045$2597 + attribute \src "ls180.v:4764.25-4764.38" + cell $not $not$ls180.v:4764$1377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8045$2595_Y - connect \B $not$ls180.v:8045$2596_Y - connect \Y $and$ls180.v:8045$2597_Y + connect \A \array_muxed3 + connect \Y $not$ls180.v:4764$1377_Y end - attribute \src "ls180.v:8051.8-8051.59" - cell $and $and$ls180.v:8051$2598 + attribute \src "ls180.v:4765.24-4765.37" + cell $not $not$ls180.v:4765$1378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_uart_phy_uart_clk_txen - connect \B \main_uart_phy_tx_busy - connect \Y $and$ls180.v:8051$2598_Y + connect \A \array_muxed4 + connect \Y $not$ls180.v:4765$1378_Y end - attribute \src "ls180.v:8075.8-8075.48" - cell $and $and$ls180.v:8075$2605 + attribute \src "ls180.v:4776.8-4776.28" + cell $not $not$ls180.v:4776$1379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8075$2604_Y - connect \B \main_uart_phy_rx_r - connect \Y $and$ls180.v:8075$2605_Y + connect \A \sdram_tccdcon_ready + connect \Y $not$ls180.v:4776$1379_Y end - attribute \src "ls180.v:8108.7-8108.57" - cell $and $and$ls180.v:8108$2611 + attribute \src "ls180.v:4791.8-4791.28" + cell $not $not$ls180.v:4791$1382 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8108$2610_Y - connect \B \main_uart_tx_old_trigger - connect \Y $and$ls180.v:8108$2611_Y + connect \A \sdram_twtrcon_ready + connect \Y $not$ls180.v:4791$1382_Y end - attribute \src "ls180.v:8115.7-8115.57" - cell $and $and$ls180.v:8115$2613 + attribute \src "ls180.v:4827.31-4827.48" + cell $not $not$ls180.v:4827$1412 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8115$2612_Y - connect \B \main_uart_rx_old_trigger - connect \Y $and$ls180.v:8115$2613_Y + connect \A \uart_phy_tx_busy + connect \Y $not$ls180.v:4827$1412_Y end - attribute \src "ls180.v:8125.8-8125.75" - cell $and $and$ls180.v:8125$2614 + attribute \src "ls180.v:4827.54-4827.74" + cell $not $not$ls180.v:4827$1414 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_syncfifo_we - connect \B \main_uart_tx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8125$2614_Y + connect \A \uart_phy_sink_ready + connect \Y $not$ls180.v:4827$1414_Y end - attribute \src "ls180.v:8125.7-8125.107" - cell $and $and$ls180.v:8125$2616 + attribute \src "ls180.v:4856.7-4856.24" + cell $not $not$ls180.v:4856$1421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8125$2614_Y - connect \B $not$ls180.v:8125$2615_Y - connect \Y $and$ls180.v:8125$2616_Y + connect \A \uart_phy_rx_busy + connect \Y $not$ls180.v:4856$1421_Y end - attribute \src "ls180.v:8131.8-8131.75" - cell $and $and$ls180.v:8131$2619 + attribute \src "ls180.v:4857.9-4857.21" + cell $not $not$ls180.v:4857$1422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_syncfifo_we - connect \B \main_uart_tx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8131$2619_Y + connect \A \uart_phy_rx + connect \Y $not$ls180.v:4857$1422_Y end - attribute \src "ls180.v:8131.7-8131.107" - cell $and $and$ls180.v:8131$2621 + attribute \src "ls180.v:4890.8-4890.19" + cell $not $not$ls180.v:4890$1428 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8131$2619_Y - connect \B $not$ls180.v:8131$2620_Y - connect \Y $and$ls180.v:8131$2621_Y + connect \A \tx_trigger + connect \Y $not$ls180.v:4890$1428_Y end - attribute \src "ls180.v:8147.8-8147.75" - cell $and $and$ls180.v:8147$2625 + attribute \src "ls180.v:4897.8-4897.19" + cell $not $not$ls180.v:4897$1430 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_syncfifo_we - connect \B \main_uart_rx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8147$2625_Y + connect \A \rx_trigger + connect \Y $not$ls180.v:4897$1430_Y end - attribute \src "ls180.v:8147.7-8147.107" - cell $and $and$ls180.v:8147$2627 + attribute \src "ls180.v:4907.60-4907.76" + cell $not $not$ls180.v:4907$1433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8147$2625_Y - connect \B $not$ls180.v:8147$2626_Y - connect \Y $and$ls180.v:8147$2627_Y + connect \A \tx_fifo_replace + connect \Y $not$ls180.v:4907$1433_Y end - attribute \src "ls180.v:8153.8-8153.75" - cell $and $and$ls180.v:8153$2630 + attribute \src "ls180.v:4913.60-4913.76" + cell $not $not$ls180.v:4913$1438 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_syncfifo_we - connect \B \main_uart_rx_fifo_syncfifo_writable - connect \Y $and$ls180.v:8153$2630_Y + connect \A \tx_fifo_replace + connect \Y $not$ls180.v:4913$1438_Y end - attribute \src "ls180.v:8153.7-8153.107" - cell $and $and$ls180.v:8153$2632 + attribute \src "ls180.v:4914.8-4914.24" + cell $not $not$ls180.v:4914$1440 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8153$2630_Y - connect \B $not$ls180.v:8153$2631_Y - connect \Y $and$ls180.v:8153$2632_Y + connect \A \tx_fifo_do_read + connect \Y $not$ls180.v:4914$1440_Y end - attribute \src "ls180.v:8301.7-8301.96" - cell $and $and$ls180.v:8301$2660 + attribute \src "ls180.v:4929.60-4929.76" + cell $not $not$ls180.v:4929$1444 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_converter_source_valid - connect \B \main_sdphy_cmdr_cmdr_converter_source_ready - connect \Y $and$ls180.v:8301$2660_Y + connect \A \rx_fifo_replace + connect \Y $not$ls180.v:4929$1444_Y end - attribute \src "ls180.v:8302.8-8302.93" - cell $and $and$ls180.v:8302$2661 + attribute \src "ls180.v:4935.60-4935.76" + cell $not $not$ls180.v:4935$1449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid - connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:8302$2661_Y + connect \A \rx_fifo_replace + connect \Y $not$ls180.v:4935$1449_Y end - attribute \src "ls180.v:8310.8-8310.93" - cell $and $and$ls180.v:8310$2662 + attribute \src "ls180.v:4936.8-4936.24" + cell $not $not$ls180.v:4936$1451 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_converter_sink_valid - connect \B \main_sdphy_cmdr_cmdr_converter_sink_ready - connect \Y $and$ls180.v:8310$2662_Y + connect \A \rx_fifo_do_read + connect \Y $not$ls180.v:4936$1451_Y end - attribute \src "ls180.v:8382.7-8382.98" - cell $and $and$ls180.v:8382$2672 + attribute \src "ls180.v:4970.9-4970.32" + cell $not $not$ls180.v:4970$1454 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_converter_source_valid - connect \B \main_sdphy_dataw_crcr_converter_source_ready - connect \Y $and$ls180.v:8382$2672_Y + connect \A \libresocsim_request [0] + connect \Y $not$ls180.v:4970$1454_Y end - attribute \src "ls180.v:8383.8-8383.95" - cell $and $and$ls180.v:8383$2673 + attribute \src "ls180.v:4981.9-4981.32" + cell $not $not$ls180.v:4981$1455 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_converter_sink_valid - connect \B \main_sdphy_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:8383$2673_Y + connect \A \libresocsim_request [1] + connect \Y $not$ls180.v:4981$1455_Y end - attribute \src "ls180.v:8391.8-8391.95" - cell $and $and$ls180.v:8391$2674 + attribute \src "ls180.v:4992.9-4992.32" + cell $not $not$ls180.v:4992$1456 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_converter_sink_valid - connect \B \main_sdphy_dataw_crcr_converter_sink_ready - connect \Y $and$ls180.v:8391$2674_Y + connect \A \libresocsim_request [2] + connect \Y $not$ls180.v:4992$1456_Y end - attribute \src "ls180.v:8461.7-8461.100" - cell $and $and$ls180.v:8461$2684 + attribute \src "ls180.v:5005.8-5005.25" + cell $not $not$ls180.v:5005$1457 parameter \A_SIGNED 0 parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_source_valid - connect \B \main_sdphy_datar_datar_converter_source_ready - connect \Y $and$ls180.v:8461$2684_Y + connect \A \libresocsim_done + connect \Y $not$ls180.v:5005$1457_Y end - attribute \src "ls180.v:8462.8-8462.97" - cell $and $and$ls180.v:8462$2685 + attribute \src "ls180.v:1554.10-1554.61" + cell $or $or$ls180.v:1554$31 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_sink_valid - connect \B \main_sdphy_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:8462$2685_Y + connect \A \libresocsim_libresoc_xics_icp_ack + connect \B \converter0_skip + connect \Y $or$ls180.v:1554$31_Y end - attribute \src "ls180.v:8470.8-8470.97" - cell $and $and$ls180.v:8470$2686 + attribute \src "ls180.v:1614.10-1614.61" + cell $or $or$ls180.v:1614$42 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_sink_valid - connect \B \main_sdphy_datar_datar_converter_sink_ready - connect \Y $and$ls180.v:8470$2686_Y + connect \A \libresocsim_libresoc_xics_ics_ack + connect \B \converter1_skip + connect \Y $or$ls180.v:1614$42_Y end - attribute \src "ls180.v:8561.7-8561.82" - cell $and $and$ls180.v:8561$2692 + attribute \src "ls180.v:1674.10-1674.43" + cell $or $or$ls180.v:1674$53 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_ready - connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8561$2692_Y + connect \A \wb_sdram_ack + connect \B \socbushandler_skip + connect \Y $or$ls180.v:1674$53_Y end - attribute \src "ls180.v:8564.7-8564.82" - cell $and $and$ls180.v:8564$2693 + attribute \src "ls180.v:1884.34-1884.90" + cell $or $or$ls180.v:1884$122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_ready - connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8564$2693_Y + connect \A \sdram_sequencer_start0 + connect \B $ne$ls180.v:1884$121_Y + connect \Y $or$ls180.v:1884$122_Y end - attribute \src "ls180.v:8567.7-8567.82" - cell $and $and$ls180.v:8567$2694 + attribute \src "ls180.v:1927.54-1927.125" + cell $or $or$ls180.v:1927$126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_ready - connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8567$2694_Y + connect \A \sdram_bankmachine0_req_wdata_ready + connect \B \sdram_bankmachine0_req_rdata_valid + connect \Y $or$ls180.v:1927$126_Y end - attribute \src "ls180.v:8570.7-8570.82" - cell $and $and$ls180.v:8570$2695 + attribute \src "ls180.v:1928.39-1928.136" + cell $or $or$ls180.v:1928$127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_ready - connect \B \main_sdcore_crc16_checker_sink_valid - connect \Y $and$ls180.v:8570$2695_Y + connect \A \sdram_bankmachine0_cmd_buffer_lookahead_source_valid + connect \B \sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $or$ls180.v:1928$127_Y end - attribute \src "ls180.v:8573.7-8573.82" - cell $and $and$ls180.v:8573$2696 + attribute \src "ls180.v:1936.40-1936.155" + cell $or $or$ls180.v:1936$131 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 13 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8573$2696_Y + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$ls180.v:1936$130_Y + connect \B { 4'0000 \sdram_bankmachine0_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$ls180.v:1936$131_Y end - attribute \src "ls180.v:8578.7-8578.82" - cell $and $and$ls180.v:8578$2697 + attribute \src "ls180.v:1973.117-1973.225" + cell $or $or$ls180.v:1973$144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8578$2697_Y + connect \A \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \B \sdram_bankmachine0_cmd_buffer_lookahead_replace + connect \Y $or$ls180.v:1973$144_Y end - attribute \src "ls180.v:8583.7-8583.82" - cell $and $and$ls180.v:8583$2698 + attribute \src "ls180.v:1979.52-1979.142" + cell $or $or$ls180.v:1979$150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8583$2698_Y + connect \A $not$ls180.v:1979$149_Y + connect \B \sdram_bankmachine0_cmd_buffer_source_ready + connect \Y $or$ls180.v:1979$150_Y end - attribute \src "ls180.v:8588.7-8588.82" - cell $and $and$ls180.v:8588$2699 + attribute \src "ls180.v:2084.54-2084.125" + cell $or $or$ls180.v:2084$156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8588$2699_Y + connect \A \sdram_bankmachine1_req_wdata_ready + connect \B \sdram_bankmachine1_req_rdata_valid + connect \Y $or$ls180.v:2084$156_Y end - attribute \src "ls180.v:8593.7-8593.82" - cell $and $and$ls180.v:8593$2700 + attribute \src "ls180.v:2085.39-2085.136" + cell $or $or$ls180.v:2085$157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_sink_valid - connect \B \main_sdcore_crc16_checker_sink_ready - connect \Y $and$ls180.v:8593$2700_Y + connect \A \sdram_bankmachine1_cmd_buffer_lookahead_source_valid + connect \B \sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $or$ls180.v:2085$157_Y end - attribute \src "ls180.v:8658.8-8658.83" - cell $and $and$ls180.v:8658$2703 + attribute \src "ls180.v:2093.40-2093.155" + cell $or $or$ls180.v:2093$161 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 13 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_syncfifo_we - connect \B \main_sdblock2mem_fifo_syncfifo_writable - connect \Y $and$ls180.v:8658$2703_Y + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$ls180.v:2093$160_Y + connect \B { 4'0000 \sdram_bankmachine1_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$ls180.v:2093$161_Y end - attribute \src "ls180.v:8658.7-8658.119" - cell $and $and$ls180.v:8658$2705 + attribute \src "ls180.v:2130.117-2130.225" + cell $or $or$ls180.v:2130$174 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8658$2703_Y - connect \B $not$ls180.v:8658$2704_Y - connect \Y $and$ls180.v:8658$2705_Y + connect \A \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \B \sdram_bankmachine1_cmd_buffer_lookahead_replace + connect \Y $or$ls180.v:2130$174_Y end - attribute \src "ls180.v:8664.8-8664.83" - cell $and $and$ls180.v:8664$2708 + attribute \src "ls180.v:2136.52-2136.142" + cell $or $or$ls180.v:2136$180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_syncfifo_we - connect \B \main_sdblock2mem_fifo_syncfifo_writable - connect \Y $and$ls180.v:8664$2708_Y + connect \A $not$ls180.v:2136$179_Y + connect \B \sdram_bankmachine1_cmd_buffer_source_ready + connect \Y $or$ls180.v:2136$180_Y end - attribute \src "ls180.v:8664.7-8664.119" - cell $and $and$ls180.v:8664$2710 + attribute \src "ls180.v:2241.54-2241.125" + cell $or $or$ls180.v:2241$186 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8664$2708_Y - connect \B $not$ls180.v:8664$2709_Y - connect \Y $and$ls180.v:8664$2710_Y + connect \A \sdram_bankmachine2_req_wdata_ready + connect \B \sdram_bankmachine2_req_rdata_valid + connect \Y $or$ls180.v:2241$186_Y end - attribute \src "ls180.v:8684.7-8684.88" - cell $and $and$ls180.v:8684$2717 + attribute \src "ls180.v:2242.39-2242.136" + cell $or $or$ls180.v:2242$187 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_converter_source_valid - connect \B \main_sdblock2mem_converter_source_ready - connect \Y $and$ls180.v:8684$2717_Y + connect \A \sdram_bankmachine2_cmd_buffer_lookahead_source_valid + connect \B \sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $or$ls180.v:2242$187_Y end - attribute \src "ls180.v:8685.8-8685.85" - cell $and $and$ls180.v:8685$2718 + attribute \src "ls180.v:2250.40-2250.155" + cell $or $or$ls180.v:2250$191 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 13 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_converter_sink_valid - connect \B \main_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:8685$2718_Y + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$ls180.v:2250$190_Y + connect \B { 4'0000 \sdram_bankmachine2_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$ls180.v:2250$191_Y end - attribute \src "ls180.v:8693.8-8693.85" - cell $and $and$ls180.v:8693$2719 + attribute \src "ls180.v:2287.117-2287.225" + cell $or $or$ls180.v:2287$204 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_converter_sink_valid - connect \B \main_sdblock2mem_converter_sink_ready - connect \Y $and$ls180.v:8693$2719_Y + connect \A \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \B \sdram_bankmachine2_cmd_buffer_lookahead_replace + connect \Y $or$ls180.v:2287$204_Y end - attribute \src "ls180.v:8749.7-8749.88" - cell $and $and$ls180.v:8749$2723 + attribute \src "ls180.v:2293.52-2293.142" + cell $or $or$ls180.v:2293$210 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_converter_source_valid - connect \B \main_sdmem2block_converter_source_ready - connect \Y $and$ls180.v:8749$2723_Y + connect \A $not$ls180.v:2293$209_Y + connect \B \sdram_bankmachine2_cmd_buffer_source_ready + connect \Y $or$ls180.v:2293$210_Y end - attribute \src "ls180.v:8756.8-8756.83" - cell $and $and$ls180.v:8756$2725 + attribute \src "ls180.v:2398.54-2398.125" + cell $or $or$ls180.v:2398$216 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_syncfifo_we - connect \B \main_sdmem2block_fifo_syncfifo_writable - connect \Y $and$ls180.v:8756$2725_Y + connect \A \sdram_bankmachine3_req_wdata_ready + connect \B \sdram_bankmachine3_req_rdata_valid + connect \Y $or$ls180.v:2398$216_Y end - attribute \src "ls180.v:8756.7-8756.119" - cell $and $and$ls180.v:8756$2727 + attribute \src "ls180.v:2399.39-2399.136" + cell $or $or$ls180.v:2399$217 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8756$2725_Y - connect \B $not$ls180.v:8756$2726_Y - connect \Y $and$ls180.v:8756$2727_Y + connect \A \sdram_bankmachine3_cmd_buffer_lookahead_source_valid + connect \B \sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $or$ls180.v:2399$217_Y end - attribute \src "ls180.v:8762.8-8762.83" - cell $and $and$ls180.v:8762$2730 + attribute \src "ls180.v:2407.40-2407.155" + cell $or $or$ls180.v:2407$221 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 13 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_syncfifo_we - connect \B \main_sdmem2block_fifo_syncfifo_writable - connect \Y $and$ls180.v:8762$2730_Y + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$ls180.v:2407$220_Y + connect \B { 4'0000 \sdram_bankmachine3_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$ls180.v:2407$221_Y end - attribute \src "ls180.v:8762.7-8762.119" - cell $and $and$ls180.v:8762$2732 + attribute \src "ls180.v:2444.117-2444.225" + cell $or $or$ls180.v:2444$234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A $and$ls180.v:8762$2730_Y - connect \B $not$ls180.v:8762$2731_Y - connect \Y $and$ls180.v:8762$2732_Y + connect \A \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \B \sdram_bankmachine3_cmd_buffer_lookahead_replace + connect \Y $or$ls180.v:2444$234_Y end - attribute \src "ls180.v:2841.30-2841.76" - cell $eq $eq$ls180.v:2841$30 + attribute \src "ls180.v:2450.52-2450.142" + cell $or $or$ls180.v:2450$240 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_xics_icp_sel - connect \B 1'0 - connect \Y $eq$ls180.v:2841$30_Y + connect \A $not$ls180.v:2450$239_Y + connect \B \sdram_bankmachine3_cmd_buffer_source_ready + connect \Y $or$ls180.v:2450$240_Y end - attribute \src "ls180.v:2848.11-2848.42" - cell $eq $eq$ls180.v:2848$35 + attribute \src "ls180.v:2549.92-2549.168" + cell $or $or$ls180.v:2549$260 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_converter0_counter - connect \B 1'1 - connect \Y $eq$ls180.v:2848$35_Y + connect \A \sdram_choose_req_cmd_payload_is_write + connect \B \sdram_choose_req_cmd_payload_is_read + connect \Y $or$ls180.v:2549$260_Y end - attribute \src "ls180.v:2901.30-2901.76" - cell $eq $eq$ls180.v:2901$41 + attribute \src "ls180.v:2552.34-2552.179" + cell $or $or$ls180.v:2552$266 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_xics_ics_sel - connect \B 1'0 - connect \Y $eq$ls180.v:2901$41_Y + connect \A $and$ls180.v:2552$264_Y + connect \B $and$ls180.v:2552$265_Y + connect \Y $or$ls180.v:2552$266_Y end - attribute \src "ls180.v:2908.11-2908.42" - cell $eq $eq$ls180.v:2908$46 + attribute \src "ls180.v:2552.33-2552.254" + cell $or $or$ls180.v:2552$268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_converter1_counter - connect \B 1'1 - connect \Y $eq$ls180.v:2908$46_Y + connect \A $or$ls180.v:2552$266_Y + connect \B $and$ls180.v:2552$267_Y + connect \Y $or$ls180.v:2552$268_Y end - attribute \src "ls180.v:2961.33-2961.58" - cell $eq $eq$ls180.v:2961$52 + attribute \src "ls180.v:2552.32-2552.329" + cell $or $or$ls180.v:2552$270 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_wb_sdram_sel - connect \B 1'0 - connect \Y $eq$ls180.v:2961$52_Y + connect \A $or$ls180.v:2552$268_Y + connect \B $and$ls180.v:2552$269_Y + connect \Y $or$ls180.v:2552$270_Y end - attribute \src "ls180.v:2968.11-2968.45" - cell $eq $eq$ls180.v:2968$57 + attribute \src "ls180.v:2553.35-2553.182" + cell $or $or$ls180.v:2553$273 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_socbushandler_counter - connect \B 1'1 - connect \Y $eq$ls180.v:2968$57_Y + connect \A $and$ls180.v:2553$271_Y + connect \B $and$ls180.v:2553$272_Y + connect \Y $or$ls180.v:2553$273_Y end - attribute \src "ls180.v:3172.34-3172.65" - cell $eq $eq$ls180.v:3172$122 + attribute \src "ls180.v:2553.34-2553.258" + cell $or $or$ls180.v:2553$275 parameter \A_SIGNED 0 - parameter \A_WIDTH 10 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_timer_count1 - connect \B 1'0 - connect \Y $eq$ls180.v:3172$122_Y + connect \A $or$ls180.v:2553$273_Y + connect \B $and$ls180.v:2553$274_Y + connect \Y $or$ls180.v:2553$275_Y end - attribute \src "ls180.v:3176.68-3176.102" - cell $eq $eq$ls180.v:3176$125 + attribute \src "ls180.v:2553.33-2553.334" + cell $or $or$ls180.v:2553$277 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_count - connect \B 1'0 - connect \Y $eq$ls180.v:3176$125_Y + connect \A $or$ls180.v:2553$275_Y + connect \B $and$ls180.v:2553$276_Y + connect \Y $or$ls180.v:2553$277_Y end - attribute \src "ls180.v:3220.43-3220.134" - cell $eq $eq$ls180.v:3220$130 + attribute \src "ls180.v:2566.138-2566.292" + cell $or $or$ls180.v:2566$291 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_row - connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3220$130_Y + connect \A $not$ls180.v:2566$290_Y + connect \B \sdram_choose_cmd_want_activates + connect \Y $or$ls180.v:2566$291_Y end - attribute \src "ls180.v:3237.47-3237.88" - cell $eq $eq$ls180.v:3237$143 + attribute \src "ls180.v:2566.65-2566.446" + cell $or $or$ls180.v:2566$296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_row_close - connect \B 1'0 - connect \Y $eq$ls180.v:3237$143_Y + connect \A $and$ls180.v:2566$292_Y + connect \B $and$ls180.v:2566$295_Y + connect \Y $or$ls180.v:2566$296_Y end - attribute \src "ls180.v:3377.43-3377.134" - cell $eq $eq$ls180.v:3377$160 + attribute \src "ls180.v:2567.138-2567.292" + cell $or $or$ls180.v:2567$304 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_row - connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3377$160_Y + connect \A $not$ls180.v:2567$303_Y + connect \B \sdram_choose_cmd_want_activates + connect \Y $or$ls180.v:2567$304_Y end - attribute \src "ls180.v:3394.47-3394.88" - cell $eq $eq$ls180.v:3394$173 + attribute \src "ls180.v:2567.65-2567.446" + cell $or $or$ls180.v:2567$309 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_row_close - connect \B 1'0 - connect \Y $eq$ls180.v:3394$173_Y + connect \A $and$ls180.v:2567$305_Y + connect \B $and$ls180.v:2567$308_Y + connect \Y $or$ls180.v:2567$309_Y end - attribute \src "ls180.v:3534.43-3534.134" - cell $eq $eq$ls180.v:3534$190 + attribute \src "ls180.v:2568.138-2568.292" + cell $or $or$ls180.v:2568$317 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_row - connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3534$190_Y + connect \A $not$ls180.v:2568$316_Y + connect \B \sdram_choose_cmd_want_activates + connect \Y $or$ls180.v:2568$317_Y end - attribute \src "ls180.v:3551.47-3551.88" - cell $eq $eq$ls180.v:3551$203 + attribute \src "ls180.v:2568.65-2568.446" + cell $or $or$ls180.v:2568$322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_row_close - connect \B 1'0 - connect \Y $eq$ls180.v:3551$203_Y + connect \A $and$ls180.v:2568$318_Y + connect \B $and$ls180.v:2568$321_Y + connect \Y $or$ls180.v:2568$322_Y end - attribute \src "ls180.v:3691.43-3691.134" - cell $eq $eq$ls180.v:3691$220 + attribute \src "ls180.v:2569.138-2569.292" + cell $or $or$ls180.v:2569$330 parameter \A_SIGNED 0 - parameter \A_WIDTH 13 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 13 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_row - connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - connect \Y $eq$ls180.v:3691$220_Y + connect \A $not$ls180.v:2569$329_Y + connect \B \sdram_choose_cmd_want_activates + connect \Y $or$ls180.v:2569$330_Y end - attribute \src "ls180.v:3708.47-3708.88" - cell $eq $eq$ls180.v:3708$233 + attribute \src "ls180.v:2569.65-2569.446" + cell $or $or$ls180.v:2569$335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_row_close - connect \B 1'0 - connect \Y $eq$ls180.v:3708$233_Y + connect \A $and$ls180.v:2569$331_Y + connect \B $and$ls180.v:2569$334_Y + connect \Y $or$ls180.v:2569$335_Y end - attribute \src "ls180.v:3845.32-3845.56" - cell $eq $eq$ls180.v:3845$280 + attribute \src "ls180.v:2596.31-2596.89" + cell $or $or$ls180.v:2596$341 parameter \A_SIGNED 0 - parameter \A_WIDTH 5 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_time0 - connect \B 1'0 - connect \Y $eq$ls180.v:3845$280_Y + connect \A \sdram_choose_cmd_cmd_ready + connect \B $not$ls180.v:2596$340_Y + connect \Y $or$ls180.v:2596$341_Y end - attribute \src "ls180.v:3846.32-3846.56" - cell $eq $eq$ls180.v:3846$281 + attribute \src "ls180.v:2599.138-2599.292" + cell $or $or$ls180.v:2599$349 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_time1 - connect \B 1'0 - connect \Y $eq$ls180.v:3846$281_Y + connect \A $not$ls180.v:2599$348_Y + connect \B \sdram_choose_req_want_activates + connect \Y $or$ls180.v:2599$349_Y end - attribute \src "ls180.v:3857.339-3857.418" - cell $eq $eq$ls180.v:3857$295 + attribute \src "ls180.v:2599.65-2599.446" + cell $or $or$ls180.v:2599$354 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_is_read - connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3857$295_Y + connect \A $and$ls180.v:2599$350_Y + connect \B $and$ls180.v:2599$353_Y + connect \Y $or$ls180.v:2599$354_Y end - attribute \src "ls180.v:3857.423-3857.504" - cell $eq $eq$ls180.v:3857$296 + attribute \src "ls180.v:2600.138-2600.292" + cell $or $or$ls180.v:2600$362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_is_write - connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3857$296_Y + connect \A $not$ls180.v:2600$361_Y + connect \B \sdram_choose_req_want_activates + connect \Y $or$ls180.v:2600$362_Y end - attribute \src "ls180.v:3858.339-3858.418" - cell $eq $eq$ls180.v:3858$308 + attribute \src "ls180.v:2600.65-2600.446" + cell $or $or$ls180.v:2600$367 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_is_read - connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3858$308_Y + connect \A $and$ls180.v:2600$363_Y + connect \B $and$ls180.v:2600$366_Y + connect \Y $or$ls180.v:2600$367_Y end - attribute \src "ls180.v:3858.423-3858.504" - cell $eq $eq$ls180.v:3858$309 + attribute \src "ls180.v:2601.138-2601.292" + cell $or $or$ls180.v:2601$375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_is_write - connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3858$309_Y + connect \A $not$ls180.v:2601$374_Y + connect \B \sdram_choose_req_want_activates + connect \Y $or$ls180.v:2601$375_Y end - attribute \src "ls180.v:3859.339-3859.418" - cell $eq $eq$ls180.v:3859$321 + attribute \src "ls180.v:2601.65-2601.446" + cell $or $or$ls180.v:2601$380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_is_read - connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3859$321_Y + connect \A $and$ls180.v:2601$376_Y + connect \B $and$ls180.v:2601$379_Y + connect \Y $or$ls180.v:2601$380_Y end - attribute \src "ls180.v:3859.423-3859.504" - cell $eq $eq$ls180.v:3859$322 + attribute \src "ls180.v:2602.138-2602.292" + cell $or $or$ls180.v:2602$388 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_is_write - connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3859$322_Y + connect \A $not$ls180.v:2602$387_Y + connect \B \sdram_choose_req_want_activates + connect \Y $or$ls180.v:2602$388_Y end - attribute \src "ls180.v:3860.339-3860.418" - cell $eq $eq$ls180.v:3860$334 + attribute \src "ls180.v:2602.65-2602.446" + cell $or $or$ls180.v:2602$393 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_is_read - connect \B \main_sdram_choose_cmd_want_reads - connect \Y $eq$ls180.v:3860$334_Y + connect \A $and$ls180.v:2602$389_Y + connect \B $and$ls180.v:2602$392_Y + connect \Y $or$ls180.v:2602$393_Y end - attribute \src "ls180.v:3860.423-3860.504" - cell $eq $eq$ls180.v:3860$335 + attribute \src "ls180.v:2665.31-2665.89" + cell $or $or$ls180.v:2665$427 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_is_write - connect \B \main_sdram_choose_cmd_want_writes - connect \Y $eq$ls180.v:3860$335_Y + connect \A \sdram_choose_req_cmd_ready + connect \B $not$ls180.v:2665$426_Y + connect \Y $or$ls180.v:2665$427_Y end - attribute \src "ls180.v:3890.339-3890.418" - cell $eq $eq$ls180.v:3890$353 + attribute \src "ls180.v:2686.57-2686.191" + cell $or $or$ls180.v:2686$434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_is_read - connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:3890$353_Y + connect \A $not$ls180.v:2686$433_Y + connect \B \sdram_ras_allowed + connect \Y $or$ls180.v:2686$434_Y end - attribute \src "ls180.v:3890.423-3890.504" - cell $eq $eq$ls180.v:3890$354 + attribute \src "ls180.v:2694.10-2694.52" + cell $or $or$ls180.v:2694$437 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_is_write - connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:3890$354_Y + connect \A $not$ls180.v:2694$436_Y + connect \B \sdram_max_time1 + connect \Y $or$ls180.v:2694$437_Y end - attribute \src "ls180.v:3891.339-3891.418" - cell $eq $eq$ls180.v:3891$366 + attribute \src "ls180.v:2724.57-2724.191" + cell $or $or$ls180.v:2724$443 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_is_read - connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:3891$366_Y + connect \A $not$ls180.v:2724$442_Y + connect \B \sdram_ras_allowed + connect \Y $or$ls180.v:2724$443_Y end - attribute \src "ls180.v:3891.423-3891.504" - cell $eq $eq$ls180.v:3891$367 + attribute \src "ls180.v:2732.10-2732.51" + cell $or $or$ls180.v:2732$446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_is_write - connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:3891$367_Y + connect \A $not$ls180.v:2732$445_Y + connect \B \sdram_max_time0 + connect \Y $or$ls180.v:2732$446_Y end - attribute \src "ls180.v:3892.339-3892.418" - cell $eq $eq$ls180.v:3892$379 + attribute \src "ls180.v:2742.91-2742.185" + cell $or $or$ls180.v:2742$450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_is_read - connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:3892$379_Y + connect \A \subfragments_locked0 + connect \B $and$ls180.v:2742$449_Y + connect \Y $or$ls180.v:2742$450_Y end - attribute \src "ls180.v:3892.423-3892.504" - cell $eq $eq$ls180.v:3892$380 + attribute \src "ls180.v:2742.90-2742.260" + cell $or $or$ls180.v:2742$453 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_is_write - connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:3892$380_Y + connect \A $or$ls180.v:2742$450_Y + connect \B $and$ls180.v:2742$452_Y + connect \Y $or$ls180.v:2742$453_Y end - attribute \src "ls180.v:3893.339-3893.418" - cell $eq $eq$ls180.v:3893$392 + attribute \src "ls180.v:2742.89-2742.335" + cell $or $or$ls180.v:2742$456 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_is_read - connect \B \main_sdram_choose_req_want_reads - connect \Y $eq$ls180.v:3893$392_Y + connect \A $or$ls180.v:2742$453_Y + connect \B $and$ls180.v:2742$455_Y + connect \Y $or$ls180.v:2742$456_Y end - attribute \src "ls180.v:3893.423-3893.504" - cell $eq $eq$ls180.v:3893$393 + attribute \src "ls180.v:2747.91-2747.185" + cell $or $or$ls180.v:2747$466 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_is_write - connect \B \main_sdram_choose_req_want_writes - connect \Y $eq$ls180.v:3893$393_Y + connect \A \subfragments_locked1 + connect \B $and$ls180.v:2747$465_Y + connect \Y $or$ls180.v:2747$466_Y end - attribute \src "ls180.v:3922.78-3922.113" - cell $eq $eq$ls180.v:3922$402 + attribute \src "ls180.v:2747.90-2747.260" + cell $or $or$ls180.v:2747$469 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3922$402_Y + connect \A $or$ls180.v:2747$466_Y + connect \B $and$ls180.v:2747$468_Y + connect \Y $or$ls180.v:2747$469_Y end - attribute \src "ls180.v:3925.78-3925.113" - cell $eq $eq$ls180.v:3925$405 + attribute \src "ls180.v:2747.89-2747.335" + cell $or $or$ls180.v:2747$472 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_grant - connect \B 1'0 - connect \Y $eq$ls180.v:3925$405_Y + connect \A $or$ls180.v:2747$469_Y + connect \B $and$ls180.v:2747$471_Y + connect \Y $or$ls180.v:2747$472_Y end - attribute \src "ls180.v:3931.78-3931.113" - cell $eq $eq$ls180.v:3931$409 + attribute \src "ls180.v:2752.91-2752.185" + cell $or $or$ls180.v:2752$482 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_grant - connect \B 1'1 - connect \Y $eq$ls180.v:3931$409_Y + connect \A \subfragments_locked2 + connect \B $and$ls180.v:2752$481_Y + connect \Y $or$ls180.v:2752$482_Y end - attribute \src "ls180.v:3934.78-3934.113" - cell $eq $eq$ls180.v:3934$412 + attribute \src "ls180.v:2752.90-2752.260" + cell $or $or$ls180.v:2752$485 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_grant - connect \B 1'1 - connect \Y $eq$ls180.v:3934$412_Y + connect \A $or$ls180.v:2752$482_Y + connect \B $and$ls180.v:2752$484_Y + connect \Y $or$ls180.v:2752$485_Y end - attribute \src "ls180.v:3940.78-3940.113" - cell $eq $eq$ls180.v:3940$416 + attribute \src "ls180.v:2752.89-2752.335" + cell $or $or$ls180.v:2752$488 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_grant - connect \B 2'10 - connect \Y $eq$ls180.v:3940$416_Y + connect \A $or$ls180.v:2752$485_Y + connect \B $and$ls180.v:2752$487_Y + connect \Y $or$ls180.v:2752$488_Y end - attribute \src "ls180.v:3943.78-3943.113" - cell $eq $eq$ls180.v:3943$419 + attribute \src "ls180.v:2757.91-2757.185" + cell $or $or$ls180.v:2757$498 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_grant - connect \B 2'10 - connect \Y $eq$ls180.v:3943$419_Y + connect \A \subfragments_locked3 + connect \B $and$ls180.v:2757$497_Y + connect \Y $or$ls180.v:2757$498_Y end - attribute \src "ls180.v:3949.78-3949.113" - cell $eq $eq$ls180.v:3949$423 + attribute \src "ls180.v:2757.90-2757.260" + cell $or $or$ls180.v:2757$501 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_grant - connect \B 2'11 - connect \Y $eq$ls180.v:3949$423_Y + connect \A $or$ls180.v:2757$498_Y + connect \B $and$ls180.v:2757$500_Y + connect \Y $or$ls180.v:2757$501_Y end - attribute \src "ls180.v:3952.78-3952.113" - cell $eq $eq$ls180.v:3952$426 + attribute \src "ls180.v:2757.89-2757.335" + cell $or $or$ls180.v:2757$504 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_grant - connect \B 2'11 - connect \Y $eq$ls180.v:3952$426_Y + connect \A $or$ls180.v:2757$501_Y + connect \B $and$ls180.v:2757$503_Y + connect \Y $or$ls180.v:2757$504_Y end - attribute \src "ls180.v:4033.42-4033.82" - cell $eq $eq$ls180.v:4033$449 + attribute \src "ls180.v:2762.127-2762.221" + cell $or $or$ls180.v:2762$515 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 1'0 - connect \Y $eq$ls180.v:4033$449_Y + connect \A \subfragments_locked0 + connect \B $and$ls180.v:2762$514_Y + connect \Y $or$ls180.v:2762$515_Y end - attribute \src "ls180.v:4033.145-4033.178" - cell $eq $eq$ls180.v:4033$450 + attribute \src "ls180.v:2762.126-2762.296" + cell $or $or$ls180.v:2762$518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4033$450_Y + connect \A $or$ls180.v:2762$515_Y + connect \B $and$ls180.v:2762$517_Y + connect \Y $or$ls180.v:2762$518_Y end - attribute \src "ls180.v:4033.220-4033.253" - cell $eq $eq$ls180.v:4033$453 + attribute \src "ls180.v:2762.125-2762.371" + cell $or $or$ls180.v:2762$521 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4033$453_Y + connect \A $or$ls180.v:2762$518_Y + connect \B $and$ls180.v:2762$520_Y + connect \Y $or$ls180.v:2762$521_Y end - attribute \src "ls180.v:4033.295-4033.328" - cell $eq $eq$ls180.v:4033$456 + attribute \src "ls180.v:2762.29-2762.406" + cell $or $or$ls180.v:2762$526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4033$456_Y + connect \A 1'0 + connect \B $and$ls180.v:2762$525_Y + connect \Y $or$ls180.v:2762$526_Y end - attribute \src "ls180.v:4038.42-4038.82" - cell $eq $eq$ls180.v:4038$465 + attribute \src "ls180.v:2762.501-2762.595" + cell $or $or$ls180.v:2762$531 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 1'1 - connect \Y $eq$ls180.v:4038$465_Y + connect \A \subfragments_locked1 + connect \B $and$ls180.v:2762$530_Y + connect \Y $or$ls180.v:2762$531_Y end - attribute \src "ls180.v:4038.145-4038.178" - cell $eq $eq$ls180.v:4038$466 + attribute \src "ls180.v:2762.500-2762.670" + cell $or $or$ls180.v:2762$534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4038$466_Y + connect \A $or$ls180.v:2762$531_Y + connect \B $and$ls180.v:2762$533_Y + connect \Y $or$ls180.v:2762$534_Y end - attribute \src "ls180.v:4038.220-4038.253" - cell $eq $eq$ls180.v:4038$469 + attribute \src "ls180.v:2762.499-2762.745" + cell $or $or$ls180.v:2762$537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4038$469_Y + connect \A $or$ls180.v:2762$534_Y + connect \B $and$ls180.v:2762$536_Y + connect \Y $or$ls180.v:2762$537_Y end - attribute \src "ls180.v:4038.295-4038.328" - cell $eq $eq$ls180.v:4038$472 + attribute \src "ls180.v:2762.28-2762.780" + cell $or $or$ls180.v:2762$542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4038$472_Y + connect \A $or$ls180.v:2762$526_Y + connect \B $and$ls180.v:2762$541_Y + connect \Y $or$ls180.v:2762$542_Y end - attribute \src "ls180.v:4043.42-4043.82" - cell $eq $eq$ls180.v:4043$481 + attribute \src "ls180.v:2762.875-2762.969" + cell $or $or$ls180.v:2762$547 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 2'10 - connect \Y $eq$ls180.v:4043$481_Y + connect \A \subfragments_locked2 + connect \B $and$ls180.v:2762$546_Y + connect \Y $or$ls180.v:2762$547_Y end - attribute \src "ls180.v:4043.145-4043.178" - cell $eq $eq$ls180.v:4043$482 + attribute \src "ls180.v:2762.874-2762.1044" + cell $or $or$ls180.v:2762$550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4043$482_Y + connect \A $or$ls180.v:2762$547_Y + connect \B $and$ls180.v:2762$549_Y + connect \Y $or$ls180.v:2762$550_Y end - attribute \src "ls180.v:4043.220-4043.253" - cell $eq $eq$ls180.v:4043$485 + attribute \src "ls180.v:2762.873-2762.1119" + cell $or $or$ls180.v:2762$553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4043$485_Y + connect \A $or$ls180.v:2762$550_Y + connect \B $and$ls180.v:2762$552_Y + connect \Y $or$ls180.v:2762$553_Y end - attribute \src "ls180.v:4043.295-4043.328" - cell $eq $eq$ls180.v:4043$488 + attribute \src "ls180.v:2762.27-2762.1154" + cell $or $or$ls180.v:2762$558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4043$488_Y + connect \A $or$ls180.v:2762$542_Y + connect \B $and$ls180.v:2762$557_Y + connect \Y $or$ls180.v:2762$558_Y end - attribute \src "ls180.v:4048.42-4048.82" - cell $eq $eq$ls180.v:4048$497 + attribute \src "ls180.v:2762.1249-2762.1343" + cell $or $or$ls180.v:2762$563 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 2'11 - connect \Y $eq$ls180.v:4048$497_Y + connect \A \subfragments_locked3 + connect \B $and$ls180.v:2762$562_Y + connect \Y $or$ls180.v:2762$563_Y end - attribute \src "ls180.v:4048.145-4048.178" - cell $eq $eq$ls180.v:4048$498 + attribute \src "ls180.v:2762.1248-2762.1418" + cell $or $or$ls180.v:2762$566 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4048$498_Y + connect \A $or$ls180.v:2762$563_Y + connect \B $and$ls180.v:2762$565_Y + connect \Y $or$ls180.v:2762$566_Y end - attribute \src "ls180.v:4048.220-4048.253" - cell $eq $eq$ls180.v:4048$501 + attribute \src "ls180.v:2762.1247-2762.1493" + cell $or $or$ls180.v:2762$569 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4048$501_Y + connect \A $or$ls180.v:2762$566_Y + connect \B $and$ls180.v:2762$568_Y + connect \Y $or$ls180.v:2762$569_Y end - attribute \src "ls180.v:4048.295-4048.328" - cell $eq $eq$ls180.v:4048$504 + attribute \src "ls180.v:2762.26-2762.1528" + cell $or $or$ls180.v:2762$574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4048$504_Y + connect \A $or$ls180.v:2762$558_Y + connect \B $and$ls180.v:2762$573_Y + connect \Y $or$ls180.v:2762$574_Y end - attribute \src "ls180.v:4053.44-4053.77" - cell $eq $eq$ls180.v:4053$513 + attribute \src "ls180.v:2825.10-2825.42" + cell $or $or$ls180.v:2825$583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4053$513_Y + connect \A \litedram_wb_ack + connect \B \converter_skip + connect \Y $or$ls180.v:2825$583_Y end - attribute \src "ls180.v:4053.83-4053.123" - cell $eq $eq$ls180.v:4053$514 + attribute \src "ls180.v:2852.30-2852.59" + cell $or $or$ls180.v:2852$593 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 1'0 - connect \Y $eq$ls180.v:4053$514_Y + connect \A \port_cmd_valid + connect \B \cmd_consumed + connect \Y $or$ls180.v:2852$593_Y end - attribute \src "ls180.v:4053.186-4053.219" - cell $eq $eq$ls180.v:4053$515 + attribute \src "ls180.v:2853.29-2853.58" + cell $or $or$ls180.v:2853$597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4053$515_Y + connect \A \port_cmd_valid + connect \B \cmd_consumed + connect \Y $or$ls180.v:2853$597_Y end - attribute \src "ls180.v:4053.261-4053.294" - cell $eq $eq$ls180.v:4053$518 + attribute \src "ls180.v:2854.38-2854.100" + cell $or $or$ls180.v:2854$603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4053$518_Y + connect \A $and$ls180.v:2854$600_Y + connect \B $and$ls180.v:2854$602_Y + connect \Y $or$ls180.v:2854$603_Y end - attribute \src "ls180.v:4053.336-4053.369" - cell $eq $eq$ls180.v:4053$521 + attribute \src "ls180.v:2855.19-2855.67" + cell $or $or$ls180.v:2855$606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4053$521_Y + connect \A $and$ls180.v:2855$605_Y + connect \B \cmd_consumed + connect \Y $or$ls180.v:2855$606_Y end - attribute \src "ls180.v:4053.418-4053.451" - cell $eq $eq$ls180.v:4053$529 + attribute \src "ls180.v:2856.21-2856.75" + cell $or $or$ls180.v:2856$608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4053$529_Y + connect \A $and$ls180.v:2856$607_Y + connect \B \wdata_consumed + connect \Y $or$ls180.v:2856$608_Y end - attribute \src "ls180.v:4053.457-4053.497" - cell $eq $eq$ls180.v:4053$530 + attribute \src "ls180.v:2886.32-2886.59" + cell $or $or$ls180.v:2886$616 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 1'1 - connect \Y $eq$ls180.v:4053$530_Y + connect \A \rx_clear + connect \B $and$ls180.v:2886$615_Y + connect \Y $or$ls180.v:2886$616_Y end - attribute \src "ls180.v:4053.560-4053.593" - cell $eq $eq$ls180.v:4053$531 + attribute \src "ls180.v:2910.15-2910.124" + cell $or $or$ls180.v:2910$626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4053$531_Y + connect \A $and$ls180.v:2910$624_Y + connect \B $and$ls180.v:2910$625_Y + connect \Y $or$ls180.v:2910$626_Y end - attribute \src "ls180.v:4053.635-4053.668" - cell $eq $eq$ls180.v:4053$534 + attribute \src "ls180.v:2925.60-2925.92" + cell $or $or$ls180.v:2925$628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4053$534_Y + connect \A $not$ls180.v:2925$627_Y + connect \B \tx_fifo_re + connect \Y $or$ls180.v:2925$628_Y end - attribute \src "ls180.v:4053.710-4053.743" - cell $eq $eq$ls180.v:4053$537 + attribute \src "ls180.v:2936.52-2936.95" + cell $or $or$ls180.v:2936$633 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4053$537_Y + connect \A \tx_fifo_syncfifo_writable + connect \B \tx_fifo_replace + connect \Y $or$ls180.v:2936$633_Y end - attribute \src "ls180.v:4053.792-4053.825" - cell $eq $eq$ls180.v:4053$545 + attribute \src "ls180.v:2955.60-2955.92" + cell $or $or$ls180.v:2955$639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4053$545_Y + connect \A $not$ls180.v:2955$638_Y + connect \B \rx_fifo_re + connect \Y $or$ls180.v:2955$639_Y end - attribute \src "ls180.v:4053.831-4053.871" - cell $eq $eq$ls180.v:4053$546 + attribute \src "ls180.v:2966.52-2966.95" + cell $or $or$ls180.v:2966$644 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 2'10 - connect \Y $eq$ls180.v:4053$546_Y + connect \A \rx_fifo_syncfifo_writable + connect \B \rx_fifo_replace + connect \Y $or$ls180.v:2966$644_Y end - attribute \src "ls180.v:4053.934-4053.967" - cell $eq $eq$ls180.v:4053$547 + attribute \src "ls180.v:3149.38-3149.83" + cell $or $or$ls180.v:3149$682 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4053$547_Y + connect \A \libresocsim_ram_bus_err + connect \B \ram_bus_ram_bus_err + connect \Y $or$ls180.v:3149$682_Y end - attribute \src "ls180.v:4053.1009-4053.1042" - cell $eq $eq$ls180.v:4053$550 + attribute \src "ls180.v:3149.37-3149.121" + cell $or $or$ls180.v:3149$683 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4053$550_Y + connect \A $or$ls180.v:3149$682_Y + connect \B \interface0_converted_interface_err + connect \Y $or$ls180.v:3149$683_Y end - attribute \src "ls180.v:4053.1084-4053.1117" - cell $eq $eq$ls180.v:4053$553 + attribute \src "ls180.v:3149.36-3149.159" + cell $or $or$ls180.v:3149$684 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4053$553_Y + connect \A $or$ls180.v:3149$683_Y + connect \B \interface1_converted_interface_err + connect \Y $or$ls180.v:3149$684_Y end - attribute \src "ls180.v:4053.1166-4053.1199" - cell $eq $eq$ls180.v:4053$561 + attribute \src "ls180.v:3149.35-3149.200" + cell $or $or$ls180.v:3149$685 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4053$561_Y + connect \A $or$ls180.v:3149$684_Y + connect \B \socbushandler_converted_interface_err + connect \Y $or$ls180.v:3149$685_Y end - attribute \src "ls180.v:4053.1205-4053.1245" - cell $eq $eq$ls180.v:4053$562 + attribute \src "ls180.v:3149.34-3149.251" + cell $or $or$ls180.v:3149$686 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 2'11 - connect \Y $eq$ls180.v:4053$562_Y + connect \A $or$ls180.v:3149$685_Y + connect \B \libresocsim_libresocsim_converted_interface_err + connect \Y $or$ls180.v:3149$686_Y end - attribute \src "ls180.v:4053.1308-4053.1341" - cell $eq $eq$ls180.v:4053$563 + attribute \src "ls180.v:3155.33-3155.78" + cell $or $or$ls180.v:3155$691 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4053$563_Y + connect \A \libresocsim_ram_bus_ack + connect \B \ram_bus_ram_bus_ack + connect \Y $or$ls180.v:3155$691_Y end - attribute \src "ls180.v:4053.1383-4053.1416" - cell $eq $eq$ls180.v:4053$566 + attribute \src "ls180.v:3155.32-3155.116" + cell $or $or$ls180.v:3155$692 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4053$566_Y + connect \A $or$ls180.v:3155$691_Y + connect \B \interface0_converted_interface_ack + connect \Y $or$ls180.v:3155$692_Y end - attribute \src "ls180.v:4053.1458-4053.1491" - cell $eq $eq$ls180.v:4053$569 + attribute \src "ls180.v:3155.31-3155.154" + cell $or $or$ls180.v:3155$693 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:4053$569_Y + connect \A $or$ls180.v:3155$692_Y + connect \B \interface1_converted_interface_ack + connect \Y $or$ls180.v:3155$693_Y end - attribute \src "ls180.v:4112.29-4112.57" - cell $eq $eq$ls180.v:4112$582 + attribute \src "ls180.v:3155.30-3155.195" + cell $or $or$ls180.v:3155$694 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_sel - connect \B 1'0 - connect \Y $eq$ls180.v:4112$582_Y + connect \A $or$ls180.v:3155$693_Y + connect \B \socbushandler_converted_interface_ack + connect \Y $or$ls180.v:3155$694_Y end - attribute \src "ls180.v:4119.11-4119.41" - cell $eq $eq$ls180.v:4119$587 + attribute \src "ls180.v:3155.29-3155.246" + cell $or $or$ls180.v:3155$695 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_converter_counter - connect \B 1'1 - connect \Y $eq$ls180.v:4119$587_Y + connect \A $or$ls180.v:3155$694_Y + connect \B \libresocsim_libresocsim_converted_interface_ack + connect \Y $or$ls180.v:3155$695_Y end - attribute \src "ls180.v:4287.37-4287.111" - cell $eq $eq$ls180.v:4287$654 + attribute \src "ls180.v:3156.35-3156.158" + cell $or $or$ls180.v:3156$698 parameter \A_SIGNED 0 - parameter \A_WIDTH 16 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \main_spimaster30_clk_divider - connect \B $sub$ls180.v:4287$653_Y - connect \Y $eq$ls180.v:4287$654_Y + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $and$ls180.v:3156$696_Y + connect \B $and$ls180.v:3156$697_Y + connect \Y $or$ls180.v:3156$698_Y end - attribute \src "ls180.v:4288.37-4288.105" - cell $eq $eq$ls180.v:4288$656 + attribute \src "ls180.v:3156.34-3156.235" + cell $or $or$ls180.v:3156$700 parameter \A_SIGNED 0 - parameter \A_WIDTH 16 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \main_spimaster30_clk_divider - connect \B $sub$ls180.v:4288$655_Y - connect \Y $eq$ls180.v:4288$656_Y + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:3156$698_Y + connect \B $and$ls180.v:3156$699_Y + connect \Y $or$ls180.v:3156$700_Y end - attribute \src "ls180.v:4315.10-4315.67" - cell $eq $eq$ls180.v:4315$660 + attribute \src "ls180.v:3156.33-3156.312" + cell $or $or$ls180.v:3156$702 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \main_spimaster27_count - connect \B $sub$ls180.v:4315$659_Y - connect \Y $eq$ls180.v:4315$660_Y + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:3156$700_Y + connect \B $and$ls180.v:3156$701_Y + connect \Y $or$ls180.v:3156$702_Y end - attribute \src "ls180.v:4345.35-4345.108" - cell $eq $eq$ls180.v:4345$662 + attribute \src "ls180.v:3156.32-3156.392" + cell $or $or$ls180.v:3156$704 parameter \A_SIGNED 0 - parameter \A_WIDTH 16 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \main_spisdcard_clk_divider1 - connect \B $sub$ls180.v:4345$661_Y - connect \Y $eq$ls180.v:4345$662_Y + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:3156$702_Y + connect \B $and$ls180.v:3156$703_Y + connect \Y $or$ls180.v:3156$704_Y end - attribute \src "ls180.v:4346.35-4346.102" - cell $eq $eq$ls180.v:4346$664 + attribute \src "ls180.v:3156.31-3156.482" + cell $or $or$ls180.v:3156$706 parameter \A_SIGNED 0 - parameter \A_WIDTH 16 + parameter \A_WIDTH 64 parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \main_spisdcard_clk_divider1 - connect \B $sub$ls180.v:4346$663_Y - connect \Y $eq$ls180.v:4346$664_Y + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $or$ls180.v:3156$704_Y + connect \B $and$ls180.v:3156$705_Y + connect \Y $or$ls180.v:3156$706_Y end - attribute \src "ls180.v:4374.10-4374.65" - cell $eq $eq$ls180.v:4374$668 + attribute \src "ls180.v:3436.52-3436.129" + cell $or $or$ls180.v:3436$1108 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \main_spisdcard_count - connect \B $sub$ls180.v:4374$667_Y - connect \Y $eq$ls180.v:4374$668_Y + parameter \Y_WIDTH 8 + connect \A \libresocsim_interface0_bank_bus_dat_r + connect \B \libresocsim_interface1_bank_bus_dat_r + connect \Y $or$ls180.v:3436$1108_Y end - attribute \src "ls180.v:4478.10-4478.40" - cell $eq $eq$ls180.v:4478$695 + attribute \src "ls180.v:3436.51-3436.170" + cell $or $or$ls180.v:3436$1109 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_init_count - connect \B 7'1001111 - connect \Y $eq$ls180.v:4478$695_Y + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:3436$1108_Y + connect \B \libresocsim_interface2_bank_bus_dat_r + connect \Y $or$ls180.v:3436$1109_Y end - attribute \src "ls180.v:4535.10-4535.39" - cell $eq $eq$ls180.v:4535$698 + attribute \src "ls180.v:3436.50-3436.211" + cell $or $or$ls180.v:3436$1110 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdw_count - connect \B 3'111 - connect \Y $eq$ls180.v:4535$698_Y + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:3436$1109_Y + connect \B \libresocsim_interface3_bank_bus_dat_r + connect \Y $or$ls180.v:3436$1110_Y end - attribute \src "ls180.v:4552.10-4552.39" - cell $eq $eq$ls180.v:4552$700 + attribute \src "ls180.v:3436.49-3436.252" + cell $or $or$ls180.v:3436$1111 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdw_count - connect \B 3'111 - connect \Y $eq$ls180.v:4552$700_Y - end - attribute \src "ls180.v:4580.38-4580.88" - cell $eq $eq$ls180.v:4580$702 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i - connect \B 1'0 - connect \Y $eq$ls180.v:4580$702_Y - end - attribute \src "ls180.v:4630.9-4630.40" - cell $eq $eq$ls180.v:4630$712 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_timeout - connect \B 1'0 - connect \Y $eq$ls180.v:4630$712_Y + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:3436$1110_Y + connect \B \libresocsim_interface4_bank_bus_dat_r + connect \Y $or$ls180.v:3436$1111_Y end - attribute \src "ls180.v:4639.36-4639.105" - cell $eq $eq$ls180.v:4639$714 + attribute \src "ls180.v:3436.48-3436.293" + cell $or $or$ls180.v:3436$1112 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_count - connect \B $sub$ls180.v:4639$713_Y - connect \Y $eq$ls180.v:4639$714_Y + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:3436$1111_Y + connect \B \libresocsim_interface5_bank_bus_dat_r + connect \Y $or$ls180.v:3436$1112_Y end - attribute \src "ls180.v:4658.9-4658.40" - cell $eq $eq$ls180.v:4658$718 + attribute \src "ls180.v:3436.47-3436.334" + cell $or $or$ls180.v:3436$1113 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 8 parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_timeout - connect \B 1'0 - connect \Y $eq$ls180.v:4658$718_Y + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:3436$1112_Y + connect \B \libresocsim_interface6_bank_bus_dat_r + connect \Y $or$ls180.v:3436$1113_Y end - attribute \src "ls180.v:4670.10-4670.39" - cell $eq $eq$ls180.v:4670$720 + attribute \src "ls180.v:3436.46-3436.375" + cell $or $or$ls180.v:3436$1114 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_count - connect \B 3'111 - connect \Y $eq$ls180.v:4670$720_Y + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$ls180.v:3436$1113_Y + connect \B \libresocsim_interface7_bank_bus_dat_r + connect \Y $or$ls180.v:3436$1114_Y end - attribute \src "ls180.v:4707.39-4707.94" - cell $eq $eq$ls180.v:4707$724 + attribute \src "ls180.v:3763.72-3763.166" + cell $or $or$ls180.v:3763$1139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_pads_in_payload_data_i [0] - connect \B 1'0 - connect \Y $eq$ls180.v:4707$724_Y - end - attribute \src "ls180.v:4744.32-4744.89" - cell $eq $eq$ls180.v:4744$733 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_source_source_payload_data0 - connect \B 3'101 - connect \Y $eq$ls180.v:4744$733_Y + connect \A \subfragments_locked0 + connect \B $and$ls180.v:3763$1138_Y + connect \Y $or$ls180.v:3763$1139_Y end - attribute \src "ls180.v:4792.10-4792.40" - cell $eq $eq$ls180.v:4792$737 + attribute \src "ls180.v:3763.71-3763.241" + cell $or $or$ls180.v:3763$1142 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_count - connect \B 1'1 - connect \Y $eq$ls180.v:4792$737_Y + connect \A $or$ls180.v:3763$1139_Y + connect \B $and$ls180.v:3763$1141_Y + connect \Y $or$ls180.v:3763$1142_Y end - attribute \src "ls180.v:4841.40-4841.98" - cell $eq $eq$ls180.v:4841$739 + attribute \src "ls180.v:3763.70-3763.316" + cell $or $or$ls180.v:3763$1145 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_pads_in_payload_data_i - connect \B 1'0 - connect \Y $eq$ls180.v:4841$739_Y + connect \A $or$ls180.v:3763$1142_Y + connect \B $and$ls180.v:3763$1144_Y + connect \Y $or$ls180.v:3763$1145_Y end - attribute \src "ls180.v:4892.9-4892.41" - cell $eq $eq$ls180.v:4892$749 + attribute \src "ls180.v:3787.72-3787.166" + cell $or $or$ls180.v:3787$1155 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_timeout - connect \B 1'0 - connect \Y $eq$ls180.v:4892$749_Y - end - attribute \src "ls180.v:4901.37-4901.123" - cell $eq $eq$ls180.v:4901$752 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 10 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_count - connect \B $sub$ls180.v:4901$751_Y - connect \Y $eq$ls180.v:4901$752_Y + connect \A \subfragments_locked1 + connect \B $and$ls180.v:3787$1154_Y + connect \Y $or$ls180.v:3787$1155_Y end - attribute \src "ls180.v:4924.9-4924.41" - cell $eq $eq$ls180.v:4924$755 + attribute \src "ls180.v:3787.71-3787.241" + cell $or $or$ls180.v:3787$1158 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_timeout - connect \B 1'0 - connect \Y $eq$ls180.v:4924$755_Y - end - attribute \src "ls180.v:4934.10-4934.41" - cell $eq $eq$ls180.v:4934$757 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_count - connect \B 6'100111 - connect \Y $eq$ls180.v:4934$757_Y - end - attribute \src "ls180.v:5103.9-5103.47" - cell $eq $eq$ls180.v:5103$939 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_cnt - connect \B 3'111 - connect \Y $eq$ls180.v:5103$939_Y - end - attribute \src "ls180.v:5133.10-5133.48" - cell $eq $eq$ls180.v:5133$940 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_cnt - connect \B 3'111 - connect \Y $eq$ls180.v:5133$940_Y - end - attribute \src "ls180.v:5164.10-5164.78" - cell $eq $eq$ls180.v:5164$945 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_fifo0 - connect \B \main_sdcore_crc16_checker_crctmp0 - connect \Y $eq$ls180.v:5164$945_Y - end - attribute \src "ls180.v:5164.83-5164.151" - cell $eq $eq$ls180.v:5164$946 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_fifo1 - connect \B \main_sdcore_crc16_checker_crctmp1 - connect \Y $eq$ls180.v:5164$946_Y - end - attribute \src "ls180.v:5164.157-5164.225" - cell $eq $eq$ls180.v:5164$948 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_fifo2 - connect \B \main_sdcore_crc16_checker_crctmp2 - connect \Y $eq$ls180.v:5164$948_Y + connect \A $or$ls180.v:3787$1155_Y + connect \B $and$ls180.v:3787$1157_Y + connect \Y $or$ls180.v:3787$1158_Y end - attribute \src "ls180.v:5164.231-5164.299" - cell $eq $eq$ls180.v:5164$950 + attribute \src "ls180.v:3787.70-3787.316" + cell $or $or$ls180.v:3787$1161 parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_fifo3 - connect \B \main_sdcore_crc16_checker_crctmp3 - connect \Y $eq$ls180.v:5164$950_Y - end - attribute \src "ls180.v:5172.7-5172.44" - cell $eq $eq$ls180.v:5172$954 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_cnt - connect \B 3'111 - connect \Y $eq$ls180.v:5172$954_Y + connect \A $or$ls180.v:3787$1158_Y + connect \B $and$ls180.v:3787$1160_Y + connect \Y $or$ls180.v:3787$1161_Y end - attribute \src "ls180.v:5182.7-5182.44" - cell $eq $eq$ls180.v:5182$957 + attribute \src "ls180.v:3811.72-3811.166" + cell $or $or$ls180.v:3811$1171 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_cnt - connect \B 3'111 - connect \Y $eq$ls180.v:5182$957_Y + connect \A \subfragments_locked2 + connect \B $and$ls180.v:3811$1170_Y + connect \Y $or$ls180.v:3811$1171_Y end - attribute \src "ls180.v:5192.7-5192.44" - cell $eq $eq$ls180.v:5192$960 + attribute \src "ls180.v:3811.71-3811.241" + cell $or $or$ls180.v:3811$1174 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_cnt - connect \B 3'111 - connect \Y $eq$ls180.v:5192$960_Y + connect \A $or$ls180.v:3811$1171_Y + connect \B $and$ls180.v:3811$1173_Y + connect \Y $or$ls180.v:3811$1174_Y end - attribute \src "ls180.v:5202.7-5202.44" - cell $eq $eq$ls180.v:5202$963 + attribute \src "ls180.v:3811.70-3811.316" + cell $or $or$ls180.v:3811$1177 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_cnt - connect \B 3'111 - connect \Y $eq$ls180.v:5202$963_Y + connect \A $or$ls180.v:3811$1174_Y + connect \B $and$ls180.v:3811$1176_Y + connect \Y $or$ls180.v:3811$1177_Y end - attribute \src "ls180.v:5326.36-5326.64" - cell $eq $eq$ls180.v:5326$1014 + attribute \src "ls180.v:3835.72-3835.166" + cell $or $or$ls180.v:3835$1187 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_cmd_type - connect \B 1'0 - connect \Y $eq$ls180.v:5326$1014_Y + connect \A \subfragments_locked3 + connect \B $and$ls180.v:3835$1186_Y + connect \Y $or$ls180.v:3835$1187_Y end - attribute \src "ls180.v:5332.10-5332.39" - cell $eq $eq$ls180.v:5332$1017 + attribute \src "ls180.v:3835.71-3835.241" + cell $or $or$ls180.v:3835$1190 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_cmd_count - connect \B 3'101 - connect \Y $eq$ls180.v:5332$1017_Y + connect \A $or$ls180.v:3835$1187_Y + connect \B $and$ls180.v:3835$1189_Y + connect \Y $or$ls180.v:3835$1190_Y end - attribute \src "ls180.v:5333.11-5333.39" - cell $eq $eq$ls180.v:5333$1018 + attribute \src "ls180.v:3835.70-3835.316" + cell $or $or$ls180.v:3835$1193 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_cmd_type - connect \B 1'0 - connect \Y $eq$ls180.v:5333$1018_Y + connect \A $or$ls180.v:3835$1190_Y + connect \B $and$ls180.v:3835$1192_Y + connect \Y $or$ls180.v:3835$1193_Y end - attribute \src "ls180.v:5345.34-5345.63" - cell $eq $eq$ls180.v:5345$1019 + attribute \src "ls180.v:4288.15-4288.58" + cell $or $or$ls180.v:4288$1247 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_data_type - connect \B 1'0 - connect \Y $eq$ls180.v:5345$1019_Y + connect \A \nc_1 [0] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4288$1247_Y end - attribute \src "ls180.v:5346.9-5346.37" - cell $eq $eq$ls180.v:5346$1020 + attribute \src "ls180.v:4289.15-4289.58" + cell $or $or$ls180.v:4289$1248 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_cmd_type - connect \B 2'10 - connect \Y $eq$ls180.v:5346$1020_Y + connect \A \nc_1 [1] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4289$1248_Y end - attribute \src "ls180.v:5353.10-5353.55" - cell $eq $eq$ls180.v:5353$1021 + attribute \src "ls180.v:4290.15-4290.58" + cell $or $or$ls180.v:4290$1249 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_source_payload_status - connect \B 1'1 - connect \Y $eq$ls180.v:5353$1021_Y + connect \A \nc_1 [2] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4290$1249_Y end - attribute \src "ls180.v:5359.12-5359.41" - cell $eq $eq$ls180.v:5359$1022 + attribute \src "ls180.v:4291.15-4291.58" + cell $or $or$ls180.v:4291$1250 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_data_type - connect \B 2'10 - connect \Y $eq$ls180.v:5359$1022_Y + connect \A \nc_1 [3] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4291$1250_Y end - attribute \src "ls180.v:5362.13-5362.42" - cell $eq $eq$ls180.v:5362$1023 + attribute \src "ls180.v:4292.15-4292.58" + cell $or $or$ls180.v:4292$1251 parameter \A_SIGNED 0 - parameter \A_WIDTH 2 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_data_type - connect \B 1'1 - connect \Y $eq$ls180.v:5362$1023_Y + connect \A \nc_1 [4] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4292$1251_Y end - attribute \src "ls180.v:5384.10-5384.76" - cell $eq $eq$ls180.v:5384$1028 + attribute \src "ls180.v:4293.15-4293.58" + cell $or $or$ls180.v:4293$1252 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_data_count - connect \B $sub$ls180.v:5384$1027_Y - connect \Y $eq$ls180.v:5384$1028_Y + connect \A \nc_1 [5] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4293$1252_Y end - attribute \src "ls180.v:5399.35-5399.101" - cell $eq $eq$ls180.v:5399$1031 + attribute \src "ls180.v:4294.15-4294.58" + cell $or $or$ls180.v:4294$1253 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_data_count - connect \B $sub$ls180.v:5399$1030_Y - connect \Y $eq$ls180.v:5399$1031_Y + connect \A \nc_1 [6] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4294$1253_Y end - attribute \src "ls180.v:5401.10-5401.56" - cell $eq $eq$ls180.v:5401$1032 + attribute \src "ls180.v:4295.15-4295.58" + cell $or $or$ls180.v:4295$1254 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_source_payload_status - connect \B 1'0 - connect \Y $eq$ls180.v:5401$1032_Y + connect \A \nc_1 [7] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4295$1254_Y end - attribute \src "ls180.v:5410.12-5410.78" - cell $eq $eq$ls180.v:5410$1036 + attribute \src "ls180.v:4296.15-4296.58" + cell $or $or$ls180.v:4296$1255 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdcore_data_count - connect \B $sub$ls180.v:5410$1035_Y - connect \Y $eq$ls180.v:5410$1036_Y + connect \A \nc_1 [8] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4296$1255_Y end - attribute \src "ls180.v:5417.11-5417.57" - cell $eq $eq$ls180.v:5417$1037 + attribute \src "ls180.v:4297.15-4297.58" + cell $or $or$ls180.v:4297$1256 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_source_payload_status - connect \B 1'1 - connect \Y $eq$ls180.v:5417$1037_Y + connect \A \nc_1 [9] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4297$1256_Y end - attribute \src "ls180.v:5534.10-5534.105" - cell $eq $eq$ls180.v:5534$1054 + attribute \src "ls180.v:4298.16-4298.60" + cell $or $or$ls180.v:4298$1257 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_wishbonedmawriter_offset - connect \B $sub$ls180.v:5534$1053_Y - connect \Y $eq$ls180.v:5534$1054_Y + connect \A \nc_1 [10] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4298$1257_Y end - attribute \src "ls180.v:5624.39-5624.106" - cell $eq $eq$ls180.v:5624$1060 + attribute \src "ls180.v:4299.16-4299.60" + cell $or $or$ls180.v:4299$1258 parameter \A_SIGNED 0 - parameter \A_WIDTH 32 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 32 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_dma_offset - connect \B $sub$ls180.v:5624$1059_Y - connect \Y $eq$ls180.v:5624$1060_Y + connect \A \nc_1 [11] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4299$1258_Y end - attribute \src "ls180.v:5654.44-5654.82" - cell $eq $eq$ls180.v:5654$1063 + attribute \src "ls180.v:4300.16-4300.60" + cell $or $or$ls180.v:4300$1259 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_converter_mux - connect \B 1'0 - connect \Y $eq$ls180.v:5654$1063_Y + connect \A \nc_1 [12] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4300$1259_Y end - attribute \src "ls180.v:5655.43-5655.81" - cell $eq $eq$ls180.v:5655$1064 + attribute \src "ls180.v:4301.16-4301.60" + cell $or $or$ls180.v:4301$1260 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_converter_mux - connect \B 3'111 - connect \Y $eq$ls180.v:5655$1064_Y + connect \A \nc_1 [13] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4301$1260_Y end - attribute \src "ls180.v:5767.68-5767.89" - cell $eq $eq$ls180.v:5767$1080 + attribute \src "ls180.v:4302.16-4302.60" + cell $or $or$ls180.v:4302$1261 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 1'0 - connect \Y $eq$ls180.v:5767$1080_Y + connect \A \nc_1 [14] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4302$1261_Y end - attribute \src "ls180.v:5768.68-5768.89" - cell $eq $eq$ls180.v:5768$1082 + attribute \src "ls180.v:4303.16-4303.60" + cell $or $or$ls180.v:4303$1262 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 1'1 - connect \Y $eq$ls180.v:5768$1082_Y + connect \A \nc_1 [15] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4303$1262_Y end - attribute \src "ls180.v:5769.71-5769.92" - cell $eq $eq$ls180.v:5769$1084 + attribute \src "ls180.v:4304.16-4304.60" + cell $or $or$ls180.v:4304$1263 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 2'10 - connect \Y $eq$ls180.v:5769$1084_Y + connect \A \nc_1 [16] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4304$1263_Y end - attribute \src "ls180.v:5770.57-5770.78" - cell $eq $eq$ls180.v:5770$1086 + attribute \src "ls180.v:4305.16-4305.60" + cell $or $or$ls180.v:4305$1264 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 2'11 - connect \Y $eq$ls180.v:5770$1086_Y + connect \A \nc_1 [17] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4305$1264_Y end - attribute \src "ls180.v:5771.57-5771.78" - cell $eq $eq$ls180.v:5771$1088 + attribute \src "ls180.v:4306.16-4306.60" + cell $or $or$ls180.v:4306$1265 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 3'100 - connect \Y $eq$ls180.v:5771$1088_Y + connect \A \nc_1 [18] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4306$1265_Y end - attribute \src "ls180.v:5772.68-5772.89" - cell $eq $eq$ls180.v:5772$1090 + attribute \src "ls180.v:4307.16-4307.60" + cell $or $or$ls180.v:4307$1266 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 1'0 - connect \Y $eq$ls180.v:5772$1090_Y + connect \A \nc_1 [19] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4307$1266_Y end - attribute \src "ls180.v:5773.68-5773.89" - cell $eq $eq$ls180.v:5773$1092 + attribute \src "ls180.v:4308.16-4308.60" + cell $or $or$ls180.v:4308$1267 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 1'1 - connect \Y $eq$ls180.v:5773$1092_Y + connect \A \nc_1 [20] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4308$1267_Y end - attribute \src "ls180.v:5774.71-5774.92" - cell $eq $eq$ls180.v:5774$1094 + attribute \src "ls180.v:4309.16-4309.60" + cell $or $or$ls180.v:4309$1268 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 2'10 - connect \Y $eq$ls180.v:5774$1094_Y + connect \A \nc_1 [21] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4309$1268_Y end - attribute \src "ls180.v:5775.57-5775.78" - cell $eq $eq$ls180.v:5775$1096 + attribute \src "ls180.v:4310.16-4310.60" + cell $or $or$ls180.v:4310$1269 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 2'11 - connect \Y $eq$ls180.v:5775$1096_Y + connect \A \nc_1 [22] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4310$1269_Y end - attribute \src "ls180.v:5776.57-5776.78" - cell $eq $eq$ls180.v:5776$1098 + attribute \src "ls180.v:4311.16-4311.60" + cell $or $or$ls180.v:4311$1270 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_grant - connect \B 3'100 - connect \Y $eq$ls180.v:5776$1098_Y + connect \A \nc_1 [23] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4311$1270_Y end - attribute \src "ls180.v:5780.27-5780.59" - cell $eq $eq$ls180.v:5780$1101 + attribute \src "ls180.v:4312.16-4312.60" + cell $or $or$ls180.v:4312$1271 parameter \A_SIGNED 0 - parameter \A_WIDTH 24 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:6] - connect \B 1'0 - connect \Y $eq$ls180.v:5780$1101_Y + connect \A \nc_1 [24] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4312$1271_Y end - attribute \src "ls180.v:5781.27-5781.60" - cell $eq $eq$ls180.v:5781$1102 + attribute \src "ls180.v:4313.16-4313.60" + cell $or $or$ls180.v:4313$1272 parameter \A_SIGNED 0 - parameter \A_WIDTH 26 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:4] - connect \B 4'1110 - connect \Y $eq$ls180.v:5781$1102_Y + connect \A \nc_1 [25] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4313$1272_Y end - attribute \src "ls180.v:5782.27-5782.68" - cell $eq $eq$ls180.v:5782$1103 + attribute \src "ls180.v:4314.16-4314.60" + cell $or $or$ls180.v:4314$1273 parameter \A_SIGNED 0 - parameter \A_WIDTH 28 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 27 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:2] - connect \B 27'110000000000000100000000000 - connect \Y $eq$ls180.v:5782$1103_Y + connect \A \nc_1 [26] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4314$1273_Y end - attribute \src "ls180.v:5783.27-5783.65" - cell $eq $eq$ls180.v:5783$1104 + attribute \src "ls180.v:4315.16-4315.60" + cell $or $or$ls180.v:4315$1274 parameter \A_SIGNED 0 - parameter \A_WIDTH 21 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 20 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:9] - connect \B 20'11000000000000010001 - connect \Y $eq$ls180.v:5783$1104_Y + connect \A \nc_1 [27] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4315$1274_Y end - attribute \src "ls180.v:5784.27-5784.61" - cell $eq $eq$ls180.v:5784$1105 + attribute \src "ls180.v:4316.16-4316.60" + cell $or $or$ls180.v:4316$1275 parameter \A_SIGNED 0 - parameter \A_WIDTH 8 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 7 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:22] - connect \B 7'1001000 - connect \Y $eq$ls180.v:5784$1105_Y + connect \A \nc_1 [28] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4316$1275_Y end - attribute \src "ls180.v:5785.27-5785.65" - cell $eq $eq$ls180.v:5785$1106 + attribute \src "ls180.v:4317.16-4317.60" + cell $or $or$ls180.v:4317$1276 parameter \A_SIGNED 0 - parameter \A_WIDTH 17 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 16 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_shared_adr [29:13] - connect \B 16'1100000000000000 - connect \Y $eq$ls180.v:5785$1106_Y + connect \A \nc_1 [29] + connect \B \libresocsim_libresoc_interrupt [0] + connect \Y $or$ls180.v:4317$1276_Y end - attribute \src "ls180.v:5849.24-5849.45" - cell $eq $eq$ls180.v:5849$1138 + attribute \src "ls180.v:4318.7-4318.58" + cell $or $or$ls180.v:4318$1277 parameter \A_SIGNED 0 - parameter \A_WIDTH 20 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_count - connect \B 1'0 - connect \Y $eq$ls180.v:5849$1138_Y + connect \A \libresocsim_libresoc_xics_icp_ack + connect \B \converter0_skip + connect \Y $or$ls180.v:4318$1277_Y end - attribute \src "ls180.v:5850.32-5850.77" - cell $eq $eq$ls180.v:5850$1139 + attribute \src "ls180.v:4329.7-4329.58" + cell $or $or$ls180.v:4329$1278 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [13:8] - connect \B 1'0 - connect \Y $eq$ls180.v:5850$1139_Y + connect \A \libresocsim_libresoc_xics_ics_ack + connect \B \converter1_skip + connect \Y $or$ls180.v:4329$1278_Y end - attribute \src "ls180.v:5852.97-5852.141" - cell $eq $eq$ls180.v:5852$1141 + attribute \src "ls180.v:4340.7-4340.40" + cell $or $or$ls180.v:4340$1279 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5852$1141_Y + connect \A \wb_sdram_ack + connect \B \socbushandler_skip + connect \Y $or$ls180.v:4340$1279_Y end - attribute \src "ls180.v:5853.100-5853.144" - cell $eq $eq$ls180.v:5853$1145 + attribute \src "ls180.v:4473.7-4473.97" + cell $or $or$ls180.v:4473$1318 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5853$1145_Y + connect \A $not$ls180.v:4473$1317_Y + connect \B \sdram_bankmachine0_cmd_buffer_source_ready + connect \Y $or$ls180.v:4473$1318_Y end - attribute \src "ls180.v:5855.99-5855.143" - cell $eq $eq$ls180.v:5855$1148 + attribute \src "ls180.v:4519.7-4519.97" + cell $or $or$ls180.v:4519$1334 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:5855$1148_Y + connect \A $not$ls180.v:4519$1333_Y + connect \B \sdram_bankmachine1_cmd_buffer_source_ready + connect \Y $or$ls180.v:4519$1334_Y end - attribute \src "ls180.v:5856.102-5856.146" - cell $eq $eq$ls180.v:5856$1152 + attribute \src "ls180.v:4565.7-4565.97" + cell $or $or$ls180.v:4565$1350 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:5856$1152_Y + connect \A $not$ls180.v:4565$1349_Y + connect \B \sdram_bankmachine2_cmd_buffer_source_ready + connect \Y $or$ls180.v:4565$1350_Y end - attribute \src "ls180.v:5858.99-5858.143" - cell $eq $eq$ls180.v:5858$1155 + attribute \src "ls180.v:4611.7-4611.97" + cell $or $or$ls180.v:4611$1366 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5858$1155_Y + connect \A $not$ls180.v:4611$1365_Y + connect \B \sdram_bankmachine3_cmd_buffer_source_ready + connect \Y $or$ls180.v:4611$1366_Y end - attribute \src "ls180.v:5859.102-5859.146" - cell $eq $eq$ls180.v:5859$1159 + attribute \src "ls180.v:4799.45-4799.130" + cell $or $or$ls180.v:4799$1387 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5859$1159_Y + connect \A 1'0 + connect \B $and$ls180.v:4799$1386_Y + connect \Y $or$ls180.v:4799$1387_Y end - attribute \src "ls180.v:5861.99-5861.143" - cell $eq $eq$ls180.v:5861$1162 + attribute \src "ls180.v:4799.44-4799.212" + cell $or $or$ls180.v:4799$1390 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5861$1162_Y + connect \A $or$ls180.v:4799$1387_Y + connect \B $and$ls180.v:4799$1389_Y + connect \Y $or$ls180.v:4799$1390_Y end - attribute \src "ls180.v:5862.102-5862.146" - cell $eq $eq$ls180.v:5862$1166 + attribute \src "ls180.v:4799.43-4799.294" + cell $or $or$ls180.v:4799$1393 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 2 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5862$1166_Y + connect \A $or$ls180.v:4799$1390_Y + connect \B $and$ls180.v:4799$1392_Y + connect \Y $or$ls180.v:4799$1393_Y end - attribute \src "ls180.v:5864.99-5864.143" - cell $eq $eq$ls180.v:5864$1169 + attribute \src "ls180.v:4799.42-4799.376" + cell $or $or$ls180.v:4799$1396 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5864$1169_Y + connect \A $or$ls180.v:4799$1393_Y + connect \B $and$ls180.v:4799$1395_Y + connect \Y $or$ls180.v:4799$1396_Y end - attribute \src "ls180.v:5865.102-5865.146" - cell $eq $eq$ls180.v:5865$1173 + attribute \src "ls180.v:4800.46-4800.131" + cell $or $or$ls180.v:4800$1399 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5865$1173_Y + connect \A 1'0 + connect \B $and$ls180.v:4800$1398_Y + connect \Y $or$ls180.v:4800$1399_Y end - attribute \src "ls180.v:5867.102-5867.146" - cell $eq $eq$ls180.v:5867$1176 + attribute \src "ls180.v:4800.45-4800.213" + cell $or $or$ls180.v:4800$1402 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5867$1176_Y + connect \A $or$ls180.v:4800$1399_Y + connect \B $and$ls180.v:4800$1401_Y + connect \Y $or$ls180.v:4800$1402_Y end - attribute \src "ls180.v:5868.105-5868.149" - cell $eq $eq$ls180.v:5868$1180 + attribute \src "ls180.v:4800.44-4800.295" + cell $or $or$ls180.v:4800$1405 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5868$1180_Y + connect \A $or$ls180.v:4800$1402_Y + connect \B $and$ls180.v:4800$1404_Y + connect \Y $or$ls180.v:4800$1405_Y end - attribute \src "ls180.v:5870.102-5870.146" - cell $eq $eq$ls180.v:5870$1183 + attribute \src "ls180.v:4800.43-4800.377" + cell $or $or$ls180.v:4800$1408 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:5870$1183_Y + connect \A $or$ls180.v:4800$1405_Y + connect \B $and$ls180.v:4800$1407_Y + connect \Y $or$ls180.v:4800$1408_Y end - attribute \src "ls180.v:5871.105-5871.149" - cell $eq $eq$ls180.v:5871$1187 + attribute \src "ls180.v:4804.7-4804.39" + cell $or $or$ls180.v:4804$1409 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:5871$1187_Y + connect \A \litedram_wb_ack + connect \B \converter_skip + connect \Y $or$ls180.v:4804$1409_Y end - attribute \src "ls180.v:5873.102-5873.146" - cell $eq $eq$ls180.v:5873$1190 + attribute \src "ls180.v:5729.8-5729.46" + cell $or $or$ls180.v:5729$1619 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:5873$1190_Y + connect \A \sys_rst_1 + connect \B \libresocsim_libresoc_reset + connect \Y $or$ls180.v:5729$1619_Y end - attribute \src "ls180.v:5874.105-5874.149" - cell $eq $eq$ls180.v:5874$1194 + attribute \src "ls180.v:1936.41-1936.84" + cell $sshl $sshl$ls180.v:1936$130 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:5874$1194_Y + parameter \B_WIDTH 4 + parameter \Y_WIDTH 13 + connect \A \sdram_bankmachine0_auto_precharge + connect \B 4'1010 + connect \Y $sshl$ls180.v:1936$130_Y end - attribute \src "ls180.v:5876.102-5876.146" - cell $eq $eq$ls180.v:5876$1197 + attribute \src "ls180.v:2093.41-2093.84" + cell $sshl $sshl$ls180.v:2093$160 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:5876$1197_Y + parameter \Y_WIDTH 13 + connect \A \sdram_bankmachine1_auto_precharge + connect \B 4'1010 + connect \Y $sshl$ls180.v:2093$160_Y end - attribute \src "ls180.v:5877.105-5877.149" - cell $eq $eq$ls180.v:5877$1201 + attribute \src "ls180.v:2250.41-2250.84" + cell $sshl $sshl$ls180.v:2250$190 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:5877$1201_Y + parameter \Y_WIDTH 13 + connect \A \sdram_bankmachine2_auto_precharge + connect \B 4'1010 + connect \Y $sshl$ls180.v:2250$190_Y end - attribute \src "ls180.v:5888.32-5888.77" - cell $eq $eq$ls180.v:5888$1203 + attribute \src "ls180.v:2407.41-2407.84" + cell $sshl $sshl$ls180.v:2407$220 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [13:8] - connect \B 3'110 - connect \Y $eq$ls180.v:5888$1203_Y + parameter \B_WIDTH 4 + parameter \Y_WIDTH 13 + connect \A \sdram_bankmachine3_auto_precharge + connect \B 4'1010 + connect \Y $sshl$ls180.v:2407$220_Y end - attribute \src "ls180.v:5890.94-5890.138" - cell $eq $eq$ls180.v:5890$1205 + attribute \src "ls180.v:1967.58-1967.112" + cell $sub $sub$ls180.v:1967$143 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5890$1205_Y + parameter \Y_WIDTH 3 + connect \A \sdram_bankmachine0_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $sub$ls180.v:1967$143_Y end - attribute \src "ls180.v:5891.97-5891.141" - cell $eq $eq$ls180.v:5891$1209 + attribute \src "ls180.v:2124.58-2124.112" + cell $sub $sub$ls180.v:2124$173 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5891$1209_Y + parameter \Y_WIDTH 3 + connect \A \sdram_bankmachine1_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $sub$ls180.v:2124$173_Y end - attribute \src "ls180.v:5893.94-5893.138" - cell $eq $eq$ls180.v:5893$1212 + attribute \src "ls180.v:2281.58-2281.112" + cell $sub $sub$ls180.v:2281$203 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] + parameter \Y_WIDTH 3 + connect \A \sdram_bankmachine2_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $eq$ls180.v:5893$1212_Y + connect \Y $sub$ls180.v:2281$203_Y end - attribute \src "ls180.v:5894.97-5894.141" - cell $eq $eq$ls180.v:5894$1216 + attribute \src "ls180.v:2438.58-2438.112" + cell $sub $sub$ls180.v:2438$233 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] + parameter \Y_WIDTH 3 + connect \A \sdram_bankmachine3_cmd_buffer_lookahead_produce connect \B 1'1 - connect \Y $eq$ls180.v:5894$1216_Y - end - attribute \src "ls180.v:5896.94-5896.138" - cell $eq $eq$ls180.v:5896$1219 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5896$1219_Y - end - attribute \src "ls180.v:5897.97-5897.141" - cell $eq $eq$ls180.v:5897$1223 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5897$1223_Y - end - attribute \src "ls180.v:5899.94-5899.138" - cell $eq $eq$ls180.v:5899$1226 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5899$1226_Y - end - attribute \src "ls180.v:5900.97-5900.141" - cell $eq $eq$ls180.v:5900$1230 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5900$1230_Y + connect \Y $sub$ls180.v:2438$233_Y end - attribute \src "ls180.v:5902.95-5902.139" - cell $eq $eq$ls180.v:5902$1233 + attribute \src "ls180.v:2844.33-2844.65" + cell $sub $sub$ls180.v:2844$587 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5902$1233_Y - end - attribute \src "ls180.v:5903.98-5903.142" - cell $eq $eq$ls180.v:5903$1237 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5903$1237_Y - end - attribute \src "ls180.v:5905.95-5905.139" - cell $eq $eq$ls180.v:5905$1240 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 30 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5905$1240_Y + parameter \B_WIDTH 31 + parameter \Y_WIDTH 31 + connect \A \litedram_wb_adr + connect \B 31'1001000000000000000000000000000 + connect \Y $sub$ls180.v:2844$587_Y end - attribute \src "ls180.v:5906.98-5906.142" - cell $eq $eq$ls180.v:5906$1244 + attribute \src "ls180.v:2930.26-2930.48" + cell $sub $sub$ls180.v:2930$632 parameter \A_SIGNED 0 - parameter \A_WIDTH 3 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_adr [2:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5906$1244_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \tx_fifo_produce + connect \B 1'1 + connect \Y $sub$ls180.v:2930$632_Y end - attribute \src "ls180.v:5914.32-5914.78" - cell $eq $eq$ls180.v:5914$1246 + attribute \src "ls180.v:2960.26-2960.48" + cell $sub $sub$ls180.v:2960$643 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 + parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [13:8] - connect \B 4'1100 - connect \Y $eq$ls180.v:5914$1246_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \rx_fifo_produce + connect \B 1'1 + connect \Y $sub$ls180.v:2960$643_Y end - attribute \src "ls180.v:5916.93-5916.135" - cell $eq $eq$ls180.v:5916$1248 + attribute \src "ls180.v:4364.26-4364.50" + cell $sub $sub$ls180.v:4364$1286 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 32 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [0] - connect \B 1'0 - connect \Y $eq$ls180.v:5916$1248_Y + parameter \Y_WIDTH 32 + connect \A \libresocsim_value + connect \B 1'1 + connect \Y $sub$ls180.v:4364$1286_Y end - attribute \src "ls180.v:5917.96-5917.138" - cell $eq $eq$ls180.v:5917$1252 + attribute \src "ls180.v:4389.26-4389.51" + cell $sub $sub$ls180.v:4389$1294 parameter \A_SIGNED 0 - parameter \A_WIDTH 1 + parameter \A_WIDTH 10 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [0] - connect \B 1'0 - connect \Y $eq$ls180.v:5917$1252_Y + parameter \Y_WIDTH 10 + connect \A \sdram_timer_count1 + connect \B 1'1 + connect \Y $sub$ls180.v:4389$1294_Y end - attribute \src "ls180.v:5919.92-5919.134" - cell $eq $eq$ls180.v:5919$1255 + attribute \src "ls180.v:4395.29-4395.57" + cell $sub $sub$ls180.v:4395$1295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [0] + connect \A \sdram_postponer_count connect \B 1'1 - connect \Y $eq$ls180.v:5919$1255_Y + connect \Y $sub$ls180.v:4395$1295_Y end - attribute \src "ls180.v:5920.95-5920.137" - cell $eq $eq$ls180.v:5920$1259 + attribute \src "ls180.v:4406.31-4406.59" + cell $sub $sub$ls180.v:4406$1298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_adr [0] + connect \A \sdram_sequencer_count connect \B 1'1 - connect \Y $eq$ls180.v:5920$1259_Y - end - attribute \src "ls180.v:5928.32-5928.78" - cell $eq $eq$ls180.v:5928$1261 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [13:8] - connect \B 4'1010 - connect \Y $eq$ls180.v:5928$1261_Y + connect \Y $sub$ls180.v:4406$1298_Y end - attribute \src "ls180.v:5930.98-5930.142" - cell $eq $eq$ls180.v:5930$1263 + attribute \src "ls180.v:4470.54-4470.106" + cell $sub $sub$ls180.v:4470$1316 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5930$1263_Y + parameter \Y_WIDTH 4 + connect \A \sdram_bankmachine0_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$ls180.v:4470$1316_Y end - attribute \src "ls180.v:5931.101-5931.145" - cell $eq $eq$ls180.v:5931$1267 + attribute \src "ls180.v:4489.41-4489.80" + cell $sub $sub$ls180.v:4489$1320 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5931$1267_Y + parameter \Y_WIDTH 3 + connect \A \sdram_bankmachine0_twtpcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:4489$1320_Y end - attribute \src "ls180.v:5933.97-5933.141" - cell $eq $eq$ls180.v:5933$1270 + attribute \src "ls180.v:4516.54-4516.106" + cell $sub $sub$ls180.v:4516$1332 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] + parameter \Y_WIDTH 4 + connect \A \sdram_bankmachine1_cmd_buffer_lookahead_level connect \B 1'1 - connect \Y $eq$ls180.v:5933$1270_Y + connect \Y $sub$ls180.v:4516$1332_Y end - attribute \src "ls180.v:5934.100-5934.144" - cell $eq $eq$ls180.v:5934$1274 + attribute \src "ls180.v:4535.41-4535.80" + cell $sub $sub$ls180.v:4535$1336 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] + parameter \Y_WIDTH 3 + connect \A \sdram_bankmachine1_twtpcon_count connect \B 1'1 - connect \Y $eq$ls180.v:5934$1274_Y - end - attribute \src "ls180.v:5936.97-5936.141" - cell $eq $eq$ls180.v:5936$1277 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5936$1277_Y - end - attribute \src "ls180.v:5937.100-5937.144" - cell $eq $eq$ls180.v:5937$1281 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5937$1281_Y - end - attribute \src "ls180.v:5939.97-5939.141" - cell $eq $eq$ls180.v:5939$1284 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5939$1284_Y - end - attribute \src "ls180.v:5940.100-5940.144" - cell $eq $eq$ls180.v:5940$1288 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5940$1288_Y - end - attribute \src "ls180.v:5942.97-5942.141" - cell $eq $eq$ls180.v:5942$1291 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5942$1291_Y - end - attribute \src "ls180.v:5943.100-5943.144" - cell $eq $eq$ls180.v:5943$1295 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5943$1295_Y - end - attribute \src "ls180.v:5945.98-5945.142" - cell $eq $eq$ls180.v:5945$1298 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5945$1298_Y - end - attribute \src "ls180.v:5946.101-5946.145" - cell $eq $eq$ls180.v:5946$1302 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5946$1302_Y + connect \Y $sub$ls180.v:4535$1336_Y end - attribute \src "ls180.v:5948.98-5948.142" - cell $eq $eq$ls180.v:5948$1305 + attribute \src "ls180.v:4562.54-4562.106" + cell $sub $sub$ls180.v:4562$1348 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:5948$1305_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \sdram_bankmachine2_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$ls180.v:4562$1348_Y end - attribute \src "ls180.v:5949.101-5949.145" - cell $eq $eq$ls180.v:5949$1309 + attribute \src "ls180.v:4581.41-4581.80" + cell $sub $sub$ls180.v:4581$1352 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:5949$1309_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \sdram_bankmachine2_twtpcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:4581$1352_Y end - attribute \src "ls180.v:5951.98-5951.142" - cell $eq $eq$ls180.v:5951$1312 + attribute \src "ls180.v:4608.54-4608.106" + cell $sub $sub$ls180.v:4608$1364 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:5951$1312_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \sdram_bankmachine3_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$ls180.v:4608$1364_Y end - attribute \src "ls180.v:5952.101-5952.145" - cell $eq $eq$ls180.v:5952$1316 + attribute \src "ls180.v:4627.41-4627.80" + cell $sub $sub$ls180.v:4627$1368 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:5952$1316_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \sdram_bankmachine3_twtpcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:4627$1368_Y end - attribute \src "ls180.v:5954.98-5954.142" - cell $eq $eq$ls180.v:5954$1319 + attribute \src "ls180.v:4638.20-4638.38" + cell $sub $sub$ls180.v:4638$1372 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:5954$1319_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \sdram_time0 + connect \B 1'1 + connect \Y $sub$ls180.v:4638$1372_Y end - attribute \src "ls180.v:5955.101-5955.145" - cell $eq $eq$ls180.v:5955$1323 + attribute \src "ls180.v:4645.20-4645.38" + cell $sub $sub$ls180.v:4645$1375 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:5955$1323_Y + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \sdram_time1 + connect \B 1'1 + connect \Y $sub$ls180.v:4645$1375_Y end - attribute \src "ls180.v:5965.32-5965.78" - cell $eq $eq$ls180.v:5965$1325 + attribute \src "ls180.v:4777.28-4777.54" + cell $sub $sub$ls180.v:4777$1380 parameter \A_SIGNED 0 - parameter \A_WIDTH 6 + parameter \A_WIDTH 1 parameter \B_SIGNED 0 - parameter \B_WIDTH 4 + parameter \B_WIDTH 1 parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [13:8] - connect \B 4'1011 - connect \Y $eq$ls180.v:5965$1325_Y + connect \A \sdram_tccdcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:4777$1380_Y end - attribute \src "ls180.v:5967.98-5967.142" - cell $eq $eq$ls180.v:5967$1327 + attribute \src "ls180.v:4792.28-4792.54" + cell $sub $sub$ls180.v:4792$1383 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 3 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5967$1327_Y + parameter \Y_WIDTH 3 + connect \A \sdram_twtrcon_count + connect \B 1'1 + connect \Y $sub$ls180.v:4792$1383_Y end - attribute \src "ls180.v:5968.101-5968.145" - cell $eq $eq$ls180.v:5968$1331 + attribute \src "ls180.v:4919.23-4919.44" + cell $sub $sub$ls180.v:4919$1442 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:5968$1331_Y + parameter \Y_WIDTH 5 + connect \A \tx_fifo_level0 + connect \B 1'1 + connect \Y $sub$ls180.v:4919$1442_Y end - attribute \src "ls180.v:5970.97-5970.141" - cell $eq $eq$ls180.v:5970$1334 + attribute \src "ls180.v:4941.23-4941.44" + cell $sub $sub$ls180.v:4941$1453 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 5 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] + parameter \Y_WIDTH 5 + connect \A \rx_fifo_level0 connect \B 1'1 - connect \Y $eq$ls180.v:5970$1334_Y + connect \Y $sub$ls180.v:4941$1453_Y end - attribute \src "ls180.v:5971.100-5971.144" - cell $eq $eq$ls180.v:5971$1338 + attribute \src "ls180.v:5006.26-5006.50" + cell $sub $sub$ls180.v:5006$1458 parameter \A_SIGNED 0 - parameter \A_WIDTH 4 + parameter \A_WIDTH 20 parameter \B_SIGNED 0 parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] + parameter \Y_WIDTH 20 + connect \A \libresocsim_count connect \B 1'1 - connect \Y $eq$ls180.v:5971$1338_Y + connect \Y $sub$ls180.v:5006$1458_Y end - attribute \src "ls180.v:5973.97-5973.141" - cell $eq $eq$ls180.v:5973$1341 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5973$1341_Y + attribute \module_not_derived 1 + attribute \src "ls180.v:5635.13-5961.2" + cell \test_issuer \test_issuer + connect \TAP_bus__tck \libresocsim_libresoc_jtag_tck + connect \TAP_bus__tdi \libresocsim_libresoc_jtag_tdi + connect \TAP_bus__tdo \libresocsim_libresoc_jtag_tdo + connect \TAP_bus__tms \libresocsim_libresoc_jtag_tms + connect \busy_o \libresocsim_libresoc0 + connect \clk \sys_clk_1 + connect \clk_sel_i \libresocsim_libresoc_clk_sel + connect \core_bigendian_i 1'0 + connect \dbus__ack \libresocsim_libresoc_dbus_ack + connect \dbus__adr \libresocsim_libresoc_dbus_adr + connect \dbus__bte 1'0 + connect \dbus__cti 1'0 + connect \dbus__cyc \libresocsim_libresoc_dbus_cyc + connect \dbus__dat_r \libresocsim_libresoc_dbus_dat_r + connect \dbus__dat_w \libresocsim_libresoc_dbus_dat_w + connect \dbus__err \libresocsim_libresoc_dbus_err + connect \dbus__sel \libresocsim_libresoc_dbus_sel + connect \dbus__stb \libresocsim_libresoc_dbus_stb + connect \dbus__we \libresocsim_libresoc_dbus_we + connect \eint_0__core__i \eint [0] + connect \eint_0__pad__i \eint_1 [0] + connect \eint_1__core__i \eint [1] + connect \eint_1__pad__i \eint_1 [1] + connect \eint_2__core__i \eint [2] + connect \eint_2__pad__i \eint_1 [2] + connect \gpio_e10__core__i \libresocsim_libresoc_constraintmanager_obj_gpio_i [10] + connect \gpio_e10__core__o \libresocsim_libresoc_constraintmanager_obj_gpio_o [10] + connect \gpio_e10__core__oe \libresocsim_libresoc_constraintmanager_obj_gpio_oe [10] + connect \gpio_e10__pad__i \gpio_i [10] + connect \gpio_e10__pad__o \gpio_o [10] + connect \gpio_e10__pad__oe \gpio_oe [10] + connect \gpio_e11__core__i \libresocsim_libresoc_constraintmanager_obj_gpio_i [11] + connect \gpio_e11__core__o \libresocsim_libresoc_constraintmanager_obj_gpio_o [11] + connect \gpio_e11__core__oe \libresocsim_libresoc_constraintmanager_obj_gpio_oe [11] + connect \gpio_e11__pad__i \gpio_i [11] + connect \gpio_e11__pad__o \gpio_o [11] + connect \gpio_e11__pad__oe \gpio_oe [11] + connect \gpio_e12__core__i \libresocsim_libresoc_constraintmanager_obj_gpio_i [12] + connect \gpio_e12__core__o \libresocsim_libresoc_constraintmanager_obj_gpio_o [12] + connect \gpio_e12__core__oe \libresocsim_libresoc_constraintmanager_obj_gpio_oe [12] + connect \gpio_e12__pad__i \gpio_i [12] + connect \gpio_e12__pad__o \gpio_o [12] + connect \gpio_e12__pad__oe \gpio_oe [12] + connect \gpio_e13__core__i \libresocsim_libresoc_constraintmanager_obj_gpio_i [13] + connect \gpio_e13__core__o \libresocsim_libresoc_constraintmanager_obj_gpio_o [13] + connect \gpio_e13__core__oe \libresocsim_libresoc_constraintmanager_obj_gpio_oe [13] + connect \gpio_e13__pad__i \gpio_i [13] + connect \gpio_e13__pad__o \gpio_o [13] + connect \gpio_e13__pad__oe \gpio_oe [13] + connect \gpio_e14__core__i \libresocsim_libresoc_constraintmanager_obj_gpio_i [14] + connect \gpio_e14__core__o \libresocsim_libresoc_constraintmanager_obj_gpio_o [14] + connect \gpio_e14__core__oe \libresocsim_libresoc_constraintmanager_obj_gpio_oe [14] + connect \gpio_e14__pad__i \gpio_i [14] + connect \gpio_e14__pad__o \gpio_o [14] + connect \gpio_e14__pad__oe \gpio_oe [14] + connect \gpio_e15__core__i \libresocsim_libresoc_constraintmanager_obj_gpio_i [15] + connect \gpio_e15__core__o \libresocsim_libresoc_constraintmanager_obj_gpio_o [15] + connect \gpio_e15__core__oe \libresocsim_libresoc_constraintmanager_obj_gpio_oe [15] + connect \gpio_e15__pad__i \gpio_i [15] + connect \gpio_e15__pad__o \gpio_o [15] + connect \gpio_e15__pad__oe \gpio_oe [15] + connect \gpio_e8__core__i \libresocsim_libresoc_constraintmanager_obj_gpio_i [8] + connect \gpio_e8__core__o \libresocsim_libresoc_constraintmanager_obj_gpio_o [8] + connect \gpio_e8__core__oe \libresocsim_libresoc_constraintmanager_obj_gpio_oe [8] + connect \gpio_e8__pad__i \gpio_i [8] + connect \gpio_e8__pad__o \gpio_o [8] + connect \gpio_e8__pad__oe \gpio_oe [8] + connect \gpio_e9__core__i \libresocsim_libresoc_constraintmanager_obj_gpio_i [9] + connect \gpio_e9__core__o \libresocsim_libresoc_constraintmanager_obj_gpio_o [9] + connect \gpio_e9__core__oe \libresocsim_libresoc_constraintmanager_obj_gpio_oe [9] + connect \gpio_e9__pad__i \gpio_i [9] + connect \gpio_e9__pad__o \gpio_o [9] + connect \gpio_e9__pad__oe \gpio_oe [9] + connect \gpio_s0__core__i \libresocsim_libresoc_constraintmanager_obj_gpio_i [0] + connect \gpio_s0__core__o \libresocsim_libresoc_constraintmanager_obj_gpio_o [0] + connect \gpio_s0__core__oe \libresocsim_libresoc_constraintmanager_obj_gpio_oe [0] + connect \gpio_s0__pad__i \gpio_i [0] + connect \gpio_s0__pad__o \gpio_o [0] + connect \gpio_s0__pad__oe \gpio_oe [0] + connect \gpio_s1__core__i \libresocsim_libresoc_constraintmanager_obj_gpio_i [1] + connect \gpio_s1__core__o \libresocsim_libresoc_constraintmanager_obj_gpio_o [1] + connect \gpio_s1__core__oe \libresocsim_libresoc_constraintmanager_obj_gpio_oe [1] + connect \gpio_s1__pad__i \gpio_i [1] + connect \gpio_s1__pad__o \gpio_o [1] + connect \gpio_s1__pad__oe \gpio_oe [1] + connect \gpio_s2__core__i \libresocsim_libresoc_constraintmanager_obj_gpio_i [2] + connect \gpio_s2__core__o \libresocsim_libresoc_constraintmanager_obj_gpio_o [2] + connect \gpio_s2__core__oe \libresocsim_libresoc_constraintmanager_obj_gpio_oe [2] + connect \gpio_s2__pad__i \gpio_i [2] + connect \gpio_s2__pad__o \gpio_o [2] + connect \gpio_s2__pad__oe \gpio_oe [2] + connect \gpio_s3__core__i \libresocsim_libresoc_constraintmanager_obj_gpio_i [3] + connect \gpio_s3__core__o \libresocsim_libresoc_constraintmanager_obj_gpio_o [3] + connect \gpio_s3__core__oe \libresocsim_libresoc_constraintmanager_obj_gpio_oe [3] + connect \gpio_s3__pad__i \gpio_i [3] + connect \gpio_s3__pad__o \gpio_o [3] + connect \gpio_s3__pad__oe \gpio_oe [3] + connect \gpio_s4__core__i \libresocsim_libresoc_constraintmanager_obj_gpio_i [4] + connect \gpio_s4__core__o \libresocsim_libresoc_constraintmanager_obj_gpio_o [4] + connect \gpio_s4__core__oe \libresocsim_libresoc_constraintmanager_obj_gpio_oe [4] + connect \gpio_s4__pad__i \gpio_i [4] + connect \gpio_s4__pad__o \gpio_o [4] + connect \gpio_s4__pad__oe \gpio_oe [4] + connect \gpio_s5__core__i \libresocsim_libresoc_constraintmanager_obj_gpio_i [5] + connect \gpio_s5__core__o \libresocsim_libresoc_constraintmanager_obj_gpio_o [5] + connect \gpio_s5__core__oe \libresocsim_libresoc_constraintmanager_obj_gpio_oe [5] + connect \gpio_s5__pad__i \gpio_i [5] + connect \gpio_s5__pad__o \gpio_o [5] + connect \gpio_s5__pad__oe \gpio_oe [5] + connect \gpio_s6__core__i \libresocsim_libresoc_constraintmanager_obj_gpio_i [6] + connect \gpio_s6__core__o \libresocsim_libresoc_constraintmanager_obj_gpio_o [6] + connect \gpio_s6__core__oe \libresocsim_libresoc_constraintmanager_obj_gpio_oe [6] + connect \gpio_s6__pad__i \gpio_i [6] + connect \gpio_s6__pad__o \gpio_o [6] + connect \gpio_s6__pad__oe \gpio_oe [6] + connect \gpio_s7__core__i \libresocsim_libresoc_constraintmanager_obj_gpio_i [7] + connect \gpio_s7__core__o \libresocsim_libresoc_constraintmanager_obj_gpio_o [7] + connect \gpio_s7__core__oe \libresocsim_libresoc_constraintmanager_obj_gpio_oe [7] + connect \gpio_s7__pad__i \gpio_i [7] + connect \gpio_s7__pad__o \gpio_o [7] + connect \gpio_s7__pad__oe \gpio_oe [7] + connect \ibus__ack \libresocsim_libresoc_ibus_ack + connect \ibus__adr \libresocsim_libresoc_ibus_adr + connect \ibus__bte 1'0 + connect \ibus__cti 1'0 + connect \ibus__cyc \libresocsim_libresoc_ibus_cyc + connect \ibus__dat_r \libresocsim_libresoc_ibus_dat_r + connect \ibus__dat_w \libresocsim_libresoc_ibus_dat_w + connect \ibus__err \libresocsim_libresoc_ibus_err + connect \ibus__sel \libresocsim_libresoc_ibus_sel + connect \ibus__stb \libresocsim_libresoc_ibus_stb + connect \ibus__we \libresocsim_libresoc_ibus_we + connect \icp_wb__ack \libresocsim_libresoc_xics_icp_ack + connect \icp_wb__adr \libresocsim_libresoc_xics_icp_adr + connect \icp_wb__cyc \libresocsim_libresoc_xics_icp_cyc + connect \icp_wb__dat_r \libresocsim_libresoc_xics_icp_dat_r + connect \icp_wb__dat_w \libresocsim_libresoc_xics_icp_dat_w + connect \icp_wb__err \libresocsim_libresoc_xics_icp_err + connect \icp_wb__sel \libresocsim_libresoc_xics_icp_sel + connect \icp_wb__stb \libresocsim_libresoc_xics_icp_stb + connect \icp_wb__we \libresocsim_libresoc_xics_icp_we + connect \ics_wb__ack \libresocsim_libresoc_xics_ics_ack + connect \ics_wb__adr \libresocsim_libresoc_xics_ics_adr + connect \ics_wb__cyc \libresocsim_libresoc_xics_ics_cyc + connect \ics_wb__dat_r \libresocsim_libresoc_xics_ics_dat_r + connect \ics_wb__dat_w \libresocsim_libresoc_xics_ics_dat_w + connect \ics_wb__err \libresocsim_libresoc_xics_ics_err + connect \ics_wb__sel \libresocsim_libresoc_xics_ics_sel + connect \ics_wb__stb \libresocsim_libresoc_xics_ics_stb + connect \ics_wb__we \libresocsim_libresoc_xics_ics_we + connect \int_level_i \libresocsim_libresoc_interrupt + connect \jtag_wb__ack \libresocsim_libresoc_jtag_wb_ack + connect \jtag_wb__adr \libresocsim_libresoc_jtag_wb_adr + connect \jtag_wb__cyc \libresocsim_libresoc_jtag_wb_cyc + connect \jtag_wb__dat_r \libresocsim_libresoc_jtag_wb_dat_r + connect \jtag_wb__dat_w \libresocsim_libresoc_jtag_wb_dat_w + connect \jtag_wb__err \libresocsim_libresoc_jtag_wb_err + connect \jtag_wb__sel \libresocsim_libresoc_jtag_wb_sel + connect \jtag_wb__stb \libresocsim_libresoc_jtag_wb_stb + connect \jtag_wb__we \libresocsim_libresoc_jtag_wb_we + connect \memerr_o \libresocsim_libresoc1 + connect \mspi0_clk__core__o \libresocsim_libresoc_constraintmanager_obj_spimaster_clk + connect \mspi0_clk__pad__o \spimaster_clk + connect \mspi0_cs_n__core__o \libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n + connect \mspi0_cs_n__pad__o \spimaster_cs_n + connect \mspi0_miso__core__i \libresocsim_libresoc_constraintmanager_obj_spimaster_miso + connect \mspi0_miso__pad__i \spimaster_miso + connect \mspi0_mosi__core__o \libresocsim_libresoc_constraintmanager_obj_spimaster_mosi + connect \mspi0_mosi__pad__o \spimaster_mosi + connect \mtwi_scl__core__o \libresocsim_libresoc_constraintmanager_obj_i2c_scl + connect \mtwi_scl__pad__o \i2c_scl + connect \mtwi_sda__core__i \libresocsim_libresoc_constraintmanager_obj_i2c_sda_i + connect \mtwi_sda__core__o \libresocsim_libresoc_constraintmanager_obj_i2c_sda_o + connect \mtwi_sda__core__oe \libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe + connect \mtwi_sda__pad__i \i2c_sda_i + connect \mtwi_sda__pad__o \i2c_sda_o + connect \mtwi_sda__pad__oe \i2c_sda_oe + connect \pc_i 1'0 + connect \pc_i_ok 1'0 + connect \pc_o \libresocsim_libresoc2 + connect \pll_18_o \libresocsim_libresoc_pll_18_o + connect \pll_lck_o \libresocsim_libresoc_pll_lck_o + connect \rst $or$ls180.v:5729$1619_Y + connect \sdr_a_0__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_a [0] + connect \sdr_a_0__pad__o \sdram_a [0] + connect \sdr_a_10__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_a [10] + connect \sdr_a_10__pad__o \sdram_a [10] + connect \sdr_a_11__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_a [11] + connect \sdr_a_11__pad__o \sdram_a [11] + connect \sdr_a_12__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_a [12] + connect \sdr_a_12__pad__o \sdram_a [12] + connect \sdr_a_1__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_a [1] + connect \sdr_a_1__pad__o \sdram_a [1] + connect \sdr_a_2__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_a [2] + connect \sdr_a_2__pad__o \sdram_a [2] + connect \sdr_a_3__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_a [3] + connect \sdr_a_3__pad__o \sdram_a [3] + connect \sdr_a_4__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_a [4] + connect \sdr_a_4__pad__o \sdram_a [4] + connect \sdr_a_5__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_a [5] + connect \sdr_a_5__pad__o \sdram_a [5] + connect \sdr_a_6__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_a [6] + connect \sdr_a_6__pad__o \sdram_a [6] + connect \sdr_a_7__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_a [7] + connect \sdr_a_7__pad__o \sdram_a [7] + connect \sdr_a_8__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_a [8] + connect \sdr_a_8__pad__o \sdram_a [8] + connect \sdr_a_9__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_a [9] + connect \sdr_a_9__pad__o \sdram_a [9] + connect \sdr_ba_0__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_ba [0] + connect \sdr_ba_0__pad__o \sdram_ba [0] + connect \sdr_ba_1__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_ba [1] + connect \sdr_ba_1__pad__o \sdram_ba [1] + connect \sdr_cas_n__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_cas_n + connect \sdr_cas_n__pad__o \sdram_cas_n + connect \sdr_cke__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_cke + connect \sdr_cke__pad__o \sdram_cke + connect \sdr_clock__core__o \sdram_clock + connect \sdr_clock__pad__o \sdram_clock_1 + connect \sdr_cs_n__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_cs_n + connect \sdr_cs_n__pad__o \sdram_cs_n + connect \sdr_dm_0__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_dm [0] + connect \sdr_dm_0__pad__o \sdram_dm [0] + connect \sdr_dm_1__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_dm [1] + connect \sdr_dm_1__pad__o \sdram_dm [1] + connect \sdr_dq_0__core__i \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [0] + connect \sdr_dq_0__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [0] + connect \sdr_dq_0__core__oe \libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_0__pad__i \sdram_dq_i [0] + connect \sdr_dq_0__pad__o \sdram_dq_o [0] + connect \sdr_dq_0__pad__oe \sdram_dq_oe + connect \sdr_dq_10__core__i \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [10] + connect \sdr_dq_10__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [10] + connect \sdr_dq_10__core__oe \libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_10__pad__i \sdram_dq_i [10] + connect \sdr_dq_10__pad__o \sdram_dq_o [10] + connect \sdr_dq_10__pad__oe \sdram_dq_oe + connect \sdr_dq_11__core__i \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [11] + connect \sdr_dq_11__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [11] + connect \sdr_dq_11__core__oe \libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_11__pad__i \sdram_dq_i [11] + connect \sdr_dq_11__pad__o \sdram_dq_o [11] + connect \sdr_dq_11__pad__oe \sdram_dq_oe + connect \sdr_dq_12__core__i \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [12] + connect \sdr_dq_12__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [12] + connect \sdr_dq_12__core__oe \libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_12__pad__i \sdram_dq_i [12] + connect \sdr_dq_12__pad__o \sdram_dq_o [12] + connect \sdr_dq_12__pad__oe \sdram_dq_oe + connect \sdr_dq_13__core__i \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [13] + connect \sdr_dq_13__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [13] + connect \sdr_dq_13__core__oe \libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_13__pad__i \sdram_dq_i [13] + connect \sdr_dq_13__pad__o \sdram_dq_o [13] + connect \sdr_dq_13__pad__oe \sdram_dq_oe + connect \sdr_dq_14__core__i \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [14] + connect \sdr_dq_14__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [14] + connect \sdr_dq_14__core__oe \libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_14__pad__i \sdram_dq_i [14] + connect \sdr_dq_14__pad__o \sdram_dq_o [14] + connect \sdr_dq_14__pad__oe \sdram_dq_oe + connect \sdr_dq_15__core__i \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [15] + connect \sdr_dq_15__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [15] + connect \sdr_dq_15__core__oe \libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_15__pad__i \sdram_dq_i [15] + connect \sdr_dq_15__pad__o \sdram_dq_o [15] + connect \sdr_dq_15__pad__oe \sdram_dq_oe + connect \sdr_dq_1__core__i \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [1] + connect \sdr_dq_1__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [1] + connect \sdr_dq_1__core__oe \libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_1__pad__i \sdram_dq_i [1] + connect \sdr_dq_1__pad__o \sdram_dq_o [1] + connect \sdr_dq_1__pad__oe \sdram_dq_oe + connect \sdr_dq_2__core__i \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [2] + connect \sdr_dq_2__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [2] + connect \sdr_dq_2__core__oe \libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_2__pad__i \sdram_dq_i [2] + connect \sdr_dq_2__pad__o \sdram_dq_o [2] + connect \sdr_dq_2__pad__oe \sdram_dq_oe + connect \sdr_dq_3__core__i \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [3] + connect \sdr_dq_3__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [3] + connect \sdr_dq_3__core__oe \libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_3__pad__i \sdram_dq_i [3] + connect \sdr_dq_3__pad__o \sdram_dq_o [3] + connect \sdr_dq_3__pad__oe \sdram_dq_oe + connect \sdr_dq_4__core__i \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [4] + connect \sdr_dq_4__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [4] + connect \sdr_dq_4__core__oe \libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_4__pad__i \sdram_dq_i [4] + connect \sdr_dq_4__pad__o \sdram_dq_o [4] + connect \sdr_dq_4__pad__oe \sdram_dq_oe + connect \sdr_dq_5__core__i \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [5] + connect \sdr_dq_5__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [5] + connect \sdr_dq_5__core__oe \libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_5__pad__i \sdram_dq_i [5] + connect \sdr_dq_5__pad__o \sdram_dq_o [5] + connect \sdr_dq_5__pad__oe \sdram_dq_oe + connect \sdr_dq_6__core__i \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [6] + connect \sdr_dq_6__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [6] + connect \sdr_dq_6__core__oe \libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_6__pad__i \sdram_dq_i [6] + connect \sdr_dq_6__pad__o \sdram_dq_o [6] + connect \sdr_dq_6__pad__oe \sdram_dq_oe + connect \sdr_dq_7__core__i \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [7] + connect \sdr_dq_7__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [7] + connect \sdr_dq_7__core__oe \libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_7__pad__i \sdram_dq_i [7] + connect \sdr_dq_7__pad__o \sdram_dq_o [7] + connect \sdr_dq_7__pad__oe \sdram_dq_oe + connect \sdr_dq_8__core__i \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [8] + connect \sdr_dq_8__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [8] + connect \sdr_dq_8__core__oe \libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_8__pad__i \sdram_dq_i [8] + connect \sdr_dq_8__pad__o \sdram_dq_o [8] + connect \sdr_dq_8__pad__oe \sdram_dq_oe + connect \sdr_dq_9__core__i \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [9] + connect \sdr_dq_9__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [9] + connect \sdr_dq_9__core__oe \libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe + connect \sdr_dq_9__pad__i \sdram_dq_i [9] + connect \sdr_dq_9__pad__o \sdram_dq_o [9] + connect \sdr_dq_9__pad__oe \sdram_dq_oe + connect \sdr_ras_n__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_ras_n + connect \sdr_ras_n__pad__o \sdram_ras_n + connect \sdr_we_n__core__o \libresocsim_libresoc_constraintmanager_obj_sdram_we_n + connect \sdr_we_n__pad__o \sdram_we_n end - attribute \src "ls180.v:5974.100-5974.144" - cell $eq $eq$ls180.v:5974$1345 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:5974$1345_Y + attribute \src "ls180.v:0.0-0.0" + process $proc$ls180.v:0$2136 + sync always + sync init end - attribute \src "ls180.v:5976.97-5976.141" - cell $eq $eq$ls180.v:5976$1348 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5976$1348_Y + attribute \src "ls180.v:0.0-0.0" + process $proc$ls180.v:0$2137 + sync always + sync init end - attribute \src "ls180.v:5977.100-5977.144" - cell $eq $eq$ls180.v:5977$1352 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:5977$1352_Y + attribute \src "ls180.v:1002.5-1002.41" + process $proc$ls180.v:1002$2015 + assign { } { } + assign $1\subfragments_converter0_state[0:0] 1'0 + sync always + sync init + update \subfragments_converter0_state $1\subfragments_converter0_state[0:0] end - attribute \src "ls180.v:5979.97-5979.141" - cell $eq $eq$ls180.v:5979$1355 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5979$1355_Y + attribute \src "ls180.v:1003.5-1003.46" + process $proc$ls180.v:1003$2016 + assign { } { } + assign $1\subfragments_converter0_next_state[0:0] 1'0 + sync always + sync init + update \subfragments_converter0_next_state $1\subfragments_converter0_next_state[0:0] end - attribute \src "ls180.v:5980.100-5980.144" - cell $eq $eq$ls180.v:5980$1359 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:5980$1359_Y + attribute \src "ls180.v:1004.5-1004.65" + process $proc$ls180.v:1004$2017 + assign { } { } + assign $1\converter0_counter_subfragments_converter0_next_value[0:0] 1'0 + sync always + sync init + update \converter0_counter_subfragments_converter0_next_value $1\converter0_counter_subfragments_converter0_next_value[0:0] end - attribute \src "ls180.v:5982.98-5982.142" - cell $eq $eq$ls180.v:5982$1362 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5982$1362_Y + attribute \src "ls180.v:1005.5-1005.68" + process $proc$ls180.v:1005$2018 + assign { } { } + assign $1\converter0_counter_subfragments_converter0_next_value_ce[0:0] 1'0 + sync always + sync init + update \converter0_counter_subfragments_converter0_next_value_ce $1\converter0_counter_subfragments_converter0_next_value_ce[0:0] end - attribute \src "ls180.v:5983.101-5983.145" - cell $eq $eq$ls180.v:5983$1366 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:5983$1366_Y + attribute \src "ls180.v:1006.5-1006.41" + process $proc$ls180.v:1006$2019 + assign { } { } + assign $1\subfragments_converter1_state[0:0] 1'0 + sync always + sync init + update \subfragments_converter1_state $1\subfragments_converter1_state[0:0] end - attribute \src "ls180.v:5985.98-5985.142" - cell $eq $eq$ls180.v:5985$1369 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:5985$1369_Y + attribute \src "ls180.v:1007.5-1007.46" + process $proc$ls180.v:1007$2020 + assign { } { } + assign $1\subfragments_converter1_next_state[0:0] 1'0 + sync always + sync init + update \subfragments_converter1_next_state $1\subfragments_converter1_next_state[0:0] end - attribute \src "ls180.v:5986.101-5986.145" - cell $eq $eq$ls180.v:5986$1373 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:5986$1373_Y + attribute \src "ls180.v:1008.5-1008.65" + process $proc$ls180.v:1008$2021 + assign { } { } + assign $1\converter1_counter_subfragments_converter1_next_value[0:0] 1'0 + sync always + sync init + update \converter1_counter_subfragments_converter1_next_value $1\converter1_counter_subfragments_converter1_next_value[0:0] end - attribute \src "ls180.v:5988.98-5988.142" - cell $eq $eq$ls180.v:5988$1376 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:5988$1376_Y + attribute \src "ls180.v:1009.5-1009.68" + process $proc$ls180.v:1009$2022 + assign { } { } + assign $1\converter1_counter_subfragments_converter1_next_value_ce[0:0] 1'0 + sync always + sync init + update \converter1_counter_subfragments_converter1_next_value_ce $1\converter1_counter_subfragments_converter1_next_value_ce[0:0] end - attribute \src "ls180.v:5989.101-5989.145" - cell $eq $eq$ls180.v:5989$1380 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:5989$1380_Y + attribute \src "ls180.v:1010.5-1010.41" + process $proc$ls180.v:1010$2023 + assign { } { } + assign $1\subfragments_converter2_state[0:0] 1'0 + sync always + sync init + update \subfragments_converter2_state $1\subfragments_converter2_state[0:0] end - attribute \src "ls180.v:5991.98-5991.142" - cell $eq $eq$ls180.v:5991$1383 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:5991$1383_Y + attribute \src "ls180.v:1011.5-1011.46" + process $proc$ls180.v:1011$2024 + assign { } { } + assign $1\subfragments_converter2_next_state[0:0] 1'0 + sync always + sync init + update \subfragments_converter2_next_state $1\subfragments_converter2_next_state[0:0] end - attribute \src "ls180.v:5992.101-5992.145" - cell $eq $eq$ls180.v:5992$1387 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:5992$1387_Y + attribute \src "ls180.v:1012.5-1012.68" + process $proc$ls180.v:1012$2025 + assign { } { } + assign $1\socbushandler_counter_subfragments_converter2_next_value[0:0] 1'0 + sync always + sync init + update \socbushandler_counter_subfragments_converter2_next_value $1\socbushandler_counter_subfragments_converter2_next_value[0:0] end - attribute \src "ls180.v:6002.32-6002.78" - cell $eq $eq$ls180.v:6002$1389 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [13:8] - connect \B 4'1111 - connect \Y $eq$ls180.v:6002$1389_Y + attribute \src "ls180.v:1013.5-1013.71" + process $proc$ls180.v:1013$2026 + assign { } { } + assign $1\socbushandler_counter_subfragments_converter2_next_value_ce[0:0] 1'0 + sync always + sync init + update \socbushandler_counter_subfragments_converter2_next_value_ce $1\socbushandler_counter_subfragments_converter2_next_value_ce[0:0] end - attribute \src "ls180.v:6004.100-6004.144" - cell $eq $eq$ls180.v:6004$1391 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6004$1391_Y + attribute \src "ls180.v:1014.11-1014.46" + process $proc$ls180.v:1014$2027 + assign { } { } + assign $1\subfragments_refresher_state[1:0] 2'00 + sync always + sync init + update \subfragments_refresher_state $1\subfragments_refresher_state[1:0] end - attribute \src "ls180.v:6005.103-6005.147" - cell $eq $eq$ls180.v:6005$1395 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6005$1395_Y + attribute \src "ls180.v:1015.11-1015.51" + process $proc$ls180.v:1015$2028 + assign { } { } + assign $1\subfragments_refresher_next_state[1:0] 2'00 + sync always + sync init + update \subfragments_refresher_next_state $1\subfragments_refresher_next_state[1:0] end - attribute \src "ls180.v:6007.100-6007.144" - cell $eq $eq$ls180.v:6007$1398 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6007$1398_Y + attribute \src "ls180.v:1016.11-1016.49" + process $proc$ls180.v:1016$2029 + assign { } { } + assign $1\subfragments_bankmachine0_state[2:0] 3'000 + sync always + sync init + update \subfragments_bankmachine0_state $1\subfragments_bankmachine0_state[2:0] end - attribute \src "ls180.v:6008.103-6008.147" - cell $eq $eq$ls180.v:6008$1402 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6008$1402_Y + attribute \src "ls180.v:1017.11-1017.54" + process $proc$ls180.v:1017$2030 + assign { } { } + assign $1\subfragments_bankmachine0_next_state[2:0] 3'000 + sync always + sync init + update \subfragments_bankmachine0_next_state $1\subfragments_bankmachine0_next_state[2:0] end - attribute \src "ls180.v:6010.100-6010.144" - cell $eq $eq$ls180.v:6010$1405 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6010$1405_Y + attribute \src "ls180.v:1018.11-1018.49" + process $proc$ls180.v:1018$2031 + assign { } { } + assign $1\subfragments_bankmachine1_state[2:0] 3'000 + sync always + sync init + update \subfragments_bankmachine1_state $1\subfragments_bankmachine1_state[2:0] end - attribute \src "ls180.v:6011.103-6011.147" - cell $eq $eq$ls180.v:6011$1409 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6011$1409_Y + attribute \src "ls180.v:1019.11-1019.54" + process $proc$ls180.v:1019$2032 + assign { } { } + assign $1\subfragments_bankmachine1_next_state[2:0] 3'000 + sync always + sync init + update \subfragments_bankmachine1_next_state $1\subfragments_bankmachine1_next_state[2:0] end - attribute \src "ls180.v:6013.100-6013.144" - cell $eq $eq$ls180.v:6013$1412 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6013$1412_Y + attribute \src "ls180.v:102.11-102.50" + process $proc$ls180.v:102$1642 + assign { } { } + assign $0\libresocsim_libresoc_jtag_wb_cti[2:0] 3'000 + sync always + update \libresocsim_libresoc_jtag_wb_cti $0\libresocsim_libresoc_jtag_wb_cti[2:0] + sync init end - attribute \src "ls180.v:6014.103-6014.147" - cell $eq $eq$ls180.v:6014$1416 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6014$1416_Y - end - attribute \src "ls180.v:6016.100-6016.144" - cell $eq $eq$ls180.v:6016$1419 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6016$1419_Y - end - attribute \src "ls180.v:6017.103-6017.147" - cell $eq $eq$ls180.v:6017$1423 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6017$1423_Y - end - attribute \src "ls180.v:6019.100-6019.144" - cell $eq $eq$ls180.v:6019$1426 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6019$1426_Y - end - attribute \src "ls180.v:6020.103-6020.147" - cell $eq $eq$ls180.v:6020$1430 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6020$1430_Y - end - attribute \src "ls180.v:6022.100-6022.144" - cell $eq $eq$ls180.v:6022$1433 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6022$1433_Y - end - attribute \src "ls180.v:6023.103-6023.147" - cell $eq $eq$ls180.v:6023$1437 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6023$1437_Y - end - attribute \src "ls180.v:6025.100-6025.144" - cell $eq $eq$ls180.v:6025$1440 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6025$1440_Y - end - attribute \src "ls180.v:6026.103-6026.147" - cell $eq $eq$ls180.v:6026$1444 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6026$1444_Y - end - attribute \src "ls180.v:6028.102-6028.146" - cell $eq $eq$ls180.v:6028$1447 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6028$1447_Y - end - attribute \src "ls180.v:6029.105-6029.149" - cell $eq $eq$ls180.v:6029$1451 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6029$1451_Y - end - attribute \src "ls180.v:6031.102-6031.146" - cell $eq $eq$ls180.v:6031$1454 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6031$1454_Y - end - attribute \src "ls180.v:6032.105-6032.149" - cell $eq $eq$ls180.v:6032$1458 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6032$1458_Y - end - attribute \src "ls180.v:6034.102-6034.147" - cell $eq $eq$ls180.v:6034$1461 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:6034$1461_Y - end - attribute \src "ls180.v:6035.105-6035.150" - cell $eq $eq$ls180.v:6035$1465 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:6035$1465_Y - end - attribute \src "ls180.v:6037.102-6037.147" - cell $eq $eq$ls180.v:6037$1468 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:6037$1468_Y - end - attribute \src "ls180.v:6038.105-6038.150" - cell $eq $eq$ls180.v:6038$1472 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:6038$1472_Y - end - attribute \src "ls180.v:6040.102-6040.147" - cell $eq $eq$ls180.v:6040$1475 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:6040$1475_Y - end - attribute \src "ls180.v:6041.105-6041.150" - cell $eq $eq$ls180.v:6041$1479 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:6041$1479_Y - end - attribute \src "ls180.v:6043.99-6043.144" - cell $eq $eq$ls180.v:6043$1482 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:6043$1482_Y - end - attribute \src "ls180.v:6044.102-6044.147" - cell $eq $eq$ls180.v:6044$1486 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:6044$1486_Y - end - attribute \src "ls180.v:6046.100-6046.145" - cell $eq $eq$ls180.v:6046$1489 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:6046$1489_Y - end - attribute \src "ls180.v:6047.103-6047.148" - cell $eq $eq$ls180.v:6047$1493 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_adr [3:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:6047$1493_Y - end - attribute \src "ls180.v:6064.32-6064.78" - cell $eq $eq$ls180.v:6064$1495 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [13:8] - connect \B 4'1110 - connect \Y $eq$ls180.v:6064$1495_Y - end - attribute \src "ls180.v:6066.104-6066.148" - cell $eq $eq$ls180.v:6066$1497 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6066$1497_Y - end - attribute \src "ls180.v:6067.107-6067.151" - cell $eq $eq$ls180.v:6067$1501 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6067$1501_Y - end - attribute \src "ls180.v:6069.104-6069.148" - cell $eq $eq$ls180.v:6069$1504 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6069$1504_Y - end - attribute \src "ls180.v:6070.107-6070.151" - cell $eq $eq$ls180.v:6070$1508 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6070$1508_Y - end - attribute \src "ls180.v:6072.104-6072.148" - cell $eq $eq$ls180.v:6072$1511 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6072$1511_Y - end - attribute \src "ls180.v:6073.107-6073.151" - cell $eq $eq$ls180.v:6073$1515 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6073$1515_Y - end - attribute \src "ls180.v:6075.104-6075.148" - cell $eq $eq$ls180.v:6075$1518 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6075$1518_Y - end - attribute \src "ls180.v:6076.107-6076.151" - cell $eq $eq$ls180.v:6076$1522 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6076$1522_Y - end - attribute \src "ls180.v:6078.103-6078.147" - cell $eq $eq$ls180.v:6078$1525 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6078$1525_Y - end - attribute \src "ls180.v:6079.106-6079.150" - cell $eq $eq$ls180.v:6079$1529 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6079$1529_Y - end - attribute \src "ls180.v:6081.103-6081.147" - cell $eq $eq$ls180.v:6081$1532 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6081$1532_Y - end - attribute \src "ls180.v:6082.106-6082.150" - cell $eq $eq$ls180.v:6082$1536 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6082$1536_Y - end - attribute \src "ls180.v:6084.103-6084.147" - cell $eq $eq$ls180.v:6084$1539 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6084$1539_Y - end - attribute \src "ls180.v:6085.106-6085.150" - cell $eq $eq$ls180.v:6085$1543 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6085$1543_Y - end - attribute \src "ls180.v:6087.103-6087.147" - cell $eq $eq$ls180.v:6087$1546 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6087$1546_Y - end - attribute \src "ls180.v:6088.106-6088.150" - cell $eq $eq$ls180.v:6088$1550 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6088$1550_Y - end - attribute \src "ls180.v:6090.94-6090.138" - cell $eq $eq$ls180.v:6090$1553 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6090$1553_Y - end - attribute \src "ls180.v:6091.97-6091.141" - cell $eq $eq$ls180.v:6091$1557 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6091$1557_Y - end - attribute \src "ls180.v:6093.105-6093.149" - cell $eq $eq$ls180.v:6093$1560 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6093$1560_Y - end - attribute \src "ls180.v:6094.108-6094.152" - cell $eq $eq$ls180.v:6094$1564 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6094$1564_Y - end - attribute \src "ls180.v:6096.105-6096.150" - cell $eq $eq$ls180.v:6096$1567 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:6096$1567_Y - end - attribute \src "ls180.v:6097.108-6097.153" - cell $eq $eq$ls180.v:6097$1571 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:6097$1571_Y - end - attribute \src "ls180.v:6099.105-6099.150" - cell $eq $eq$ls180.v:6099$1574 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:6099$1574_Y - end - attribute \src "ls180.v:6100.108-6100.153" - cell $eq $eq$ls180.v:6100$1578 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:6100$1578_Y - end - attribute \src "ls180.v:6102.105-6102.150" - cell $eq $eq$ls180.v:6102$1581 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:6102$1581_Y - end - attribute \src "ls180.v:6103.108-6103.153" - cell $eq $eq$ls180.v:6103$1585 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:6103$1585_Y - end - attribute \src "ls180.v:6105.105-6105.150" - cell $eq $eq$ls180.v:6105$1588 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:6105$1588_Y - end - attribute \src "ls180.v:6106.108-6106.153" - cell $eq $eq$ls180.v:6106$1592 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:6106$1592_Y - end - attribute \src "ls180.v:6108.105-6108.150" - cell $eq $eq$ls180.v:6108$1595 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:6108$1595_Y - end - attribute \src "ls180.v:6109.108-6109.153" - cell $eq $eq$ls180.v:6109$1599 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:6109$1599_Y - end - attribute \src "ls180.v:6111.104-6111.149" - cell $eq $eq$ls180.v:6111$1602 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1111 - connect \Y $eq$ls180.v:6111$1602_Y - end - attribute \src "ls180.v:6112.107-6112.152" - cell $eq $eq$ls180.v:6112$1606 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 4'1111 - connect \Y $eq$ls180.v:6112$1606_Y - end - attribute \src "ls180.v:6114.104-6114.149" - cell $eq $eq$ls180.v:6114$1609 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10000 - connect \Y $eq$ls180.v:6114$1609_Y - end - attribute \src "ls180.v:6115.107-6115.152" - cell $eq $eq$ls180.v:6115$1613 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10000 - connect \Y $eq$ls180.v:6115$1613_Y - end - attribute \src "ls180.v:6117.104-6117.149" - cell $eq $eq$ls180.v:6117$1616 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10001 - connect \Y $eq$ls180.v:6117$1616_Y - end - attribute \src "ls180.v:6118.107-6118.152" - cell $eq $eq$ls180.v:6118$1620 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10001 - connect \Y $eq$ls180.v:6118$1620_Y - end - attribute \src "ls180.v:6120.104-6120.149" - cell $eq $eq$ls180.v:6120$1623 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10010 - connect \Y $eq$ls180.v:6120$1623_Y - end - attribute \src "ls180.v:6121.107-6121.152" - cell $eq $eq$ls180.v:6121$1627 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10010 - connect \Y $eq$ls180.v:6121$1627_Y - end - attribute \src "ls180.v:6123.104-6123.149" - cell $eq $eq$ls180.v:6123$1630 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10011 - connect \Y $eq$ls180.v:6123$1630_Y - end - attribute \src "ls180.v:6124.107-6124.152" - cell $eq $eq$ls180.v:6124$1634 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10011 - connect \Y $eq$ls180.v:6124$1634_Y - end - attribute \src "ls180.v:6126.104-6126.149" - cell $eq $eq$ls180.v:6126$1637 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10100 - connect \Y $eq$ls180.v:6126$1637_Y - end - attribute \src "ls180.v:6127.107-6127.152" - cell $eq $eq$ls180.v:6127$1641 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10100 - connect \Y $eq$ls180.v:6127$1641_Y - end - attribute \src "ls180.v:6129.104-6129.149" - cell $eq $eq$ls180.v:6129$1644 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10101 - connect \Y $eq$ls180.v:6129$1644_Y - end - attribute \src "ls180.v:6130.107-6130.152" - cell $eq $eq$ls180.v:6130$1648 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10101 - connect \Y $eq$ls180.v:6130$1648_Y - end - attribute \src "ls180.v:6132.104-6132.149" - cell $eq $eq$ls180.v:6132$1651 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10110 - connect \Y $eq$ls180.v:6132$1651_Y - end - attribute \src "ls180.v:6133.107-6133.152" - cell $eq $eq$ls180.v:6133$1655 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10110 - connect \Y $eq$ls180.v:6133$1655_Y - end - attribute \src "ls180.v:6135.104-6135.149" - cell $eq $eq$ls180.v:6135$1658 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10111 - connect \Y $eq$ls180.v:6135$1658_Y - end - attribute \src "ls180.v:6136.107-6136.152" - cell $eq $eq$ls180.v:6136$1662 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'10111 - connect \Y $eq$ls180.v:6136$1662_Y - end - attribute \src "ls180.v:6138.104-6138.149" - cell $eq $eq$ls180.v:6138$1665 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11000 - connect \Y $eq$ls180.v:6138$1665_Y - end - attribute \src "ls180.v:6139.107-6139.152" - cell $eq $eq$ls180.v:6139$1669 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11000 - connect \Y $eq$ls180.v:6139$1669_Y - end - attribute \src "ls180.v:6141.100-6141.145" - cell $eq $eq$ls180.v:6141$1672 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11001 - connect \Y $eq$ls180.v:6141$1672_Y - end - attribute \src "ls180.v:6142.103-6142.148" - cell $eq $eq$ls180.v:6142$1676 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11001 - connect \Y $eq$ls180.v:6142$1676_Y - end - attribute \src "ls180.v:6144.101-6144.146" - cell $eq $eq$ls180.v:6144$1679 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11010 - connect \Y $eq$ls180.v:6144$1679_Y - end - attribute \src "ls180.v:6145.104-6145.149" - cell $eq $eq$ls180.v:6145$1683 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11010 - connect \Y $eq$ls180.v:6145$1683_Y - end - attribute \src "ls180.v:6147.104-6147.149" - cell $eq $eq$ls180.v:6147$1686 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11011 - connect \Y $eq$ls180.v:6147$1686_Y - end - attribute \src "ls180.v:6148.107-6148.152" - cell $eq $eq$ls180.v:6148$1690 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11011 - connect \Y $eq$ls180.v:6148$1690_Y - end - attribute \src "ls180.v:6150.104-6150.149" - cell $eq $eq$ls180.v:6150$1693 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11100 - connect \Y $eq$ls180.v:6150$1693_Y - end - attribute \src "ls180.v:6151.107-6151.152" - cell $eq $eq$ls180.v:6151$1697 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11100 - connect \Y $eq$ls180.v:6151$1697_Y - end - attribute \src "ls180.v:6153.103-6153.148" - cell $eq $eq$ls180.v:6153$1700 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11101 - connect \Y $eq$ls180.v:6153$1700_Y - end - attribute \src "ls180.v:6154.106-6154.151" - cell $eq $eq$ls180.v:6154$1704 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11101 - connect \Y $eq$ls180.v:6154$1704_Y - end - attribute \src "ls180.v:6156.103-6156.148" - cell $eq $eq$ls180.v:6156$1707 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11110 - connect \Y $eq$ls180.v:6156$1707_Y - end - attribute \src "ls180.v:6157.106-6157.151" - cell $eq $eq$ls180.v:6157$1711 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11110 - connect \Y $eq$ls180.v:6157$1711_Y - end - attribute \src "ls180.v:6159.103-6159.148" - cell $eq $eq$ls180.v:6159$1714 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11111 - connect \Y $eq$ls180.v:6159$1714_Y - end - attribute \src "ls180.v:6160.106-6160.151" - cell $eq $eq$ls180.v:6160$1718 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 5'11111 - connect \Y $eq$ls180.v:6160$1718_Y - end - attribute \src "ls180.v:6162.103-6162.148" - cell $eq $eq$ls180.v:6162$1721 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 6'100000 - connect \Y $eq$ls180.v:6162$1721_Y - end - attribute \src "ls180.v:6163.106-6163.151" - cell $eq $eq$ls180.v:6163$1725 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_adr [5:0] - connect \B 6'100000 - connect \Y $eq$ls180.v:6163$1725_Y - end - attribute \src "ls180.v:6199.32-6199.78" - cell $eq $eq$ls180.v:6199$1727 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [13:8] - connect \B 5'10000 - connect \Y $eq$ls180.v:6199$1727_Y - end - attribute \src "ls180.v:6201.100-6201.144" - cell $eq $eq$ls180.v:6201$1729 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6201$1729_Y - end - attribute \src "ls180.v:6202.103-6202.147" - cell $eq $eq$ls180.v:6202$1733 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6202$1733_Y - end - attribute \src "ls180.v:6204.100-6204.144" - cell $eq $eq$ls180.v:6204$1736 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6204$1736_Y - end - attribute \src "ls180.v:6205.103-6205.147" - cell $eq $eq$ls180.v:6205$1740 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6205$1740_Y - end - attribute \src "ls180.v:6207.100-6207.144" - cell $eq $eq$ls180.v:6207$1743 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6207$1743_Y - end - attribute \src "ls180.v:6208.103-6208.147" - cell $eq $eq$ls180.v:6208$1747 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6208$1747_Y - end - attribute \src "ls180.v:6210.100-6210.144" - cell $eq $eq$ls180.v:6210$1750 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6210$1750_Y - end - attribute \src "ls180.v:6211.103-6211.147" - cell $eq $eq$ls180.v:6211$1754 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6211$1754_Y - end - attribute \src "ls180.v:6213.100-6213.144" - cell $eq $eq$ls180.v:6213$1757 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6213$1757_Y - end - attribute \src "ls180.v:6214.103-6214.147" - cell $eq $eq$ls180.v:6214$1761 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6214$1761_Y - end - attribute \src "ls180.v:6216.100-6216.144" - cell $eq $eq$ls180.v:6216$1764 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6216$1764_Y - end - attribute \src "ls180.v:6217.103-6217.147" - cell $eq $eq$ls180.v:6217$1768 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6217$1768_Y - end - attribute \src "ls180.v:6219.100-6219.144" - cell $eq $eq$ls180.v:6219$1771 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6219$1771_Y - end - attribute \src "ls180.v:6220.103-6220.147" - cell $eq $eq$ls180.v:6220$1775 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6220$1775_Y - end - attribute \src "ls180.v:6222.100-6222.144" - cell $eq $eq$ls180.v:6222$1778 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6222$1778_Y - end - attribute \src "ls180.v:6223.103-6223.147" - cell $eq $eq$ls180.v:6223$1782 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6223$1782_Y - end - attribute \src "ls180.v:6225.102-6225.146" - cell $eq $eq$ls180.v:6225$1785 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6225$1785_Y - end - attribute \src "ls180.v:6226.105-6226.149" - cell $eq $eq$ls180.v:6226$1789 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6226$1789_Y - end - attribute \src "ls180.v:6228.102-6228.146" - cell $eq $eq$ls180.v:6228$1792 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6228$1792_Y - end - attribute \src "ls180.v:6229.105-6229.149" - cell $eq $eq$ls180.v:6229$1796 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6229$1796_Y - end - attribute \src "ls180.v:6231.102-6231.147" - cell $eq $eq$ls180.v:6231$1799 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:6231$1799_Y - end - attribute \src "ls180.v:6232.105-6232.150" - cell $eq $eq$ls180.v:6232$1803 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:6232$1803_Y - end - attribute \src "ls180.v:6234.102-6234.147" - cell $eq $eq$ls180.v:6234$1806 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:6234$1806_Y - end - attribute \src "ls180.v:6235.105-6235.150" - cell $eq $eq$ls180.v:6235$1810 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:6235$1810_Y - end - attribute \src "ls180.v:6237.102-6237.147" - cell $eq $eq$ls180.v:6237$1813 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:6237$1813_Y - end - attribute \src "ls180.v:6238.105-6238.150" - cell $eq $eq$ls180.v:6238$1817 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:6238$1817_Y - end - attribute \src "ls180.v:6240.99-6240.144" - cell $eq $eq$ls180.v:6240$1820 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:6240$1820_Y - end - attribute \src "ls180.v:6241.102-6241.147" - cell $eq $eq$ls180.v:6241$1824 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:6241$1824_Y - end - attribute \src "ls180.v:6243.100-6243.145" - cell $eq $eq$ls180.v:6243$1827 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:6243$1827_Y - end - attribute \src "ls180.v:6244.103-6244.148" - cell $eq $eq$ls180.v:6244$1831 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:6244$1831_Y - end - attribute \src "ls180.v:6246.102-6246.147" - cell $eq $eq$ls180.v:6246$1834 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1111 - connect \Y $eq$ls180.v:6246$1834_Y - end - attribute \src "ls180.v:6247.105-6247.150" - cell $eq $eq$ls180.v:6247$1838 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 4'1111 - connect \Y $eq$ls180.v:6247$1838_Y - end - attribute \src "ls180.v:6249.102-6249.147" - cell $eq $eq$ls180.v:6249$1841 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 5'10000 - connect \Y $eq$ls180.v:6249$1841_Y - end - attribute \src "ls180.v:6250.105-6250.150" - cell $eq $eq$ls180.v:6250$1845 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 5'10000 - connect \Y $eq$ls180.v:6250$1845_Y - end - attribute \src "ls180.v:6252.102-6252.147" - cell $eq $eq$ls180.v:6252$1848 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 5'10001 - connect \Y $eq$ls180.v:6252$1848_Y - end - attribute \src "ls180.v:6253.105-6253.150" - cell $eq $eq$ls180.v:6253$1852 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 5'10001 - connect \Y $eq$ls180.v:6253$1852_Y - end - attribute \src "ls180.v:6255.102-6255.147" - cell $eq $eq$ls180.v:6255$1855 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 5'10010 - connect \Y $eq$ls180.v:6255$1855_Y - end - attribute \src "ls180.v:6256.105-6256.150" - cell $eq $eq$ls180.v:6256$1859 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_adr [4:0] - connect \B 5'10010 - connect \Y $eq$ls180.v:6256$1859_Y - end - attribute \src "ls180.v:6278.32-6278.78" - cell $eq $eq$ls180.v:6278$1861 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [13:8] - connect \B 4'1101 - connect \Y $eq$ls180.v:6278$1861_Y - end - attribute \src "ls180.v:6280.102-6280.146" - cell $eq $eq$ls180.v:6280$1863 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [1:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6280$1863_Y - end - attribute \src "ls180.v:6281.105-6281.149" - cell $eq $eq$ls180.v:6281$1867 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [1:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6281$1867_Y - end - attribute \src "ls180.v:6283.107-6283.151" - cell $eq $eq$ls180.v:6283$1870 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [1:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6283$1870_Y - end - attribute \src "ls180.v:6284.110-6284.154" - cell $eq $eq$ls180.v:6284$1874 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [1:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6284$1874_Y - end - attribute \src "ls180.v:6286.107-6286.151" - cell $eq $eq$ls180.v:6286$1877 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [1:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6286$1877_Y - end - attribute \src "ls180.v:6287.110-6287.154" - cell $eq $eq$ls180.v:6287$1881 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [1:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6287$1881_Y - end - attribute \src "ls180.v:6289.100-6289.144" - cell $eq $eq$ls180.v:6289$1884 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [1:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6289$1884_Y - end - attribute \src "ls180.v:6290.103-6290.147" - cell $eq $eq$ls180.v:6290$1888 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_adr [1:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6290$1888_Y - end - attribute \src "ls180.v:6295.32-6295.77" - cell $eq $eq$ls180.v:6295$1890 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [13:8] - connect \B 2'11 - connect \Y $eq$ls180.v:6295$1890_Y - end - attribute \src "ls180.v:6297.104-6297.148" - cell $eq $eq$ls180.v:6297$1892 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6297$1892_Y - end - attribute \src "ls180.v:6298.107-6298.151" - cell $eq $eq$ls180.v:6298$1896 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6298$1896_Y - end - attribute \src "ls180.v:6300.108-6300.152" - cell $eq $eq$ls180.v:6300$1899 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6300$1899_Y - end - attribute \src "ls180.v:6301.111-6301.155" - cell $eq $eq$ls180.v:6301$1903 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6301$1903_Y - end - attribute \src "ls180.v:6303.98-6303.142" - cell $eq $eq$ls180.v:6303$1906 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6303$1906_Y - end - attribute \src "ls180.v:6304.101-6304.145" - cell $eq $eq$ls180.v:6304$1910 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6304$1910_Y - end - attribute \src "ls180.v:6306.108-6306.152" - cell $eq $eq$ls180.v:6306$1913 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6306$1913_Y - end - attribute \src "ls180.v:6307.111-6307.155" - cell $eq $eq$ls180.v:6307$1917 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6307$1917_Y - end - attribute \src "ls180.v:6309.108-6309.152" - cell $eq $eq$ls180.v:6309$1920 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6309$1920_Y - end - attribute \src "ls180.v:6310.111-6310.155" - cell $eq $eq$ls180.v:6310$1924 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6310$1924_Y - end - attribute \src "ls180.v:6312.109-6312.153" - cell $eq $eq$ls180.v:6312$1927 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6312$1927_Y - end - attribute \src "ls180.v:6313.112-6313.156" - cell $eq $eq$ls180.v:6313$1931 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6313$1931_Y - end - attribute \src "ls180.v:6315.107-6315.151" - cell $eq $eq$ls180.v:6315$1934 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6315$1934_Y - end - attribute \src "ls180.v:6316.110-6316.154" - cell $eq $eq$ls180.v:6316$1938 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6316$1938_Y - end - attribute \src "ls180.v:6318.107-6318.151" - cell $eq $eq$ls180.v:6318$1941 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6318$1941_Y - end - attribute \src "ls180.v:6319.110-6319.154" - cell $eq $eq$ls180.v:6319$1945 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6319$1945_Y - end - attribute \src "ls180.v:6321.107-6321.151" - cell $eq $eq$ls180.v:6321$1948 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6321$1948_Y - end - attribute \src "ls180.v:6322.110-6322.154" - cell $eq $eq$ls180.v:6322$1952 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6322$1952_Y - end - attribute \src "ls180.v:6324.107-6324.151" - cell $eq $eq$ls180.v:6324$1955 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6324$1955_Y - end - attribute \src "ls180.v:6325.110-6325.154" - cell $eq $eq$ls180.v:6325$1959 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_adr [3:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6325$1959_Y - end - attribute \src "ls180.v:6340.33-6340.79" - cell $eq $eq$ls180.v:6340$1961 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [13:8] - connect \B 4'1000 - connect \Y $eq$ls180.v:6340$1961_Y - end - attribute \src "ls180.v:6342.102-6342.147" - cell $eq $eq$ls180.v:6342$1963 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6342$1963_Y - end - attribute \src "ls180.v:6343.105-6343.150" - cell $eq $eq$ls180.v:6343$1967 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6343$1967_Y - end - attribute \src "ls180.v:6345.102-6345.147" - cell $eq $eq$ls180.v:6345$1970 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6345$1970_Y - end - attribute \src "ls180.v:6346.105-6346.150" - cell $eq $eq$ls180.v:6346$1974 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6346$1974_Y - end - attribute \src "ls180.v:6348.100-6348.145" - cell $eq $eq$ls180.v:6348$1977 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6348$1977_Y - end - attribute \src "ls180.v:6349.103-6349.148" - cell $eq $eq$ls180.v:6349$1981 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6349$1981_Y - end - attribute \src "ls180.v:6351.99-6351.144" - cell $eq $eq$ls180.v:6351$1984 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6351$1984_Y - end - attribute \src "ls180.v:6352.102-6352.147" - cell $eq $eq$ls180.v:6352$1988 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6352$1988_Y - end - attribute \src "ls180.v:6354.98-6354.143" - cell $eq $eq$ls180.v:6354$1991 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6354$1991_Y - end - attribute \src "ls180.v:6355.101-6355.146" - cell $eq $eq$ls180.v:6355$1995 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6355$1995_Y - end - attribute \src "ls180.v:6357.97-6357.142" - cell $eq $eq$ls180.v:6357$1998 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6357$1998_Y - end - attribute \src "ls180.v:6358.100-6358.145" - cell $eq $eq$ls180.v:6358$2002 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6358$2002_Y - end - attribute \src "ls180.v:6360.103-6360.148" - cell $eq $eq$ls180.v:6360$2005 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6360$2005_Y - end - attribute \src "ls180.v:6361.106-6361.151" - cell $eq $eq$ls180.v:6361$2009 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_adr [2:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6361$2009_Y - end - attribute \src "ls180.v:6380.33-6380.79" - cell $eq $eq$ls180.v:6380$2012 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [13:8] - connect \B 4'1001 - connect \Y $eq$ls180.v:6380$2012_Y - end - attribute \src "ls180.v:6382.102-6382.147" - cell $eq $eq$ls180.v:6382$2014 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6382$2014_Y - end - attribute \src "ls180.v:6383.105-6383.150" - cell $eq $eq$ls180.v:6383$2018 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6383$2018_Y - end - attribute \src "ls180.v:6385.102-6385.147" - cell $eq $eq$ls180.v:6385$2021 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6385$2021_Y - end - attribute \src "ls180.v:6386.105-6386.150" - cell $eq $eq$ls180.v:6386$2025 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6386$2025_Y - end - attribute \src "ls180.v:6388.100-6388.145" - cell $eq $eq$ls180.v:6388$2028 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6388$2028_Y - end - attribute \src "ls180.v:6389.103-6389.148" - cell $eq $eq$ls180.v:6389$2032 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6389$2032_Y - end - attribute \src "ls180.v:6391.99-6391.144" - cell $eq $eq$ls180.v:6391$2035 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6391$2035_Y - end - attribute \src "ls180.v:6392.102-6392.147" - cell $eq $eq$ls180.v:6392$2039 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6392$2039_Y - end - attribute \src "ls180.v:6394.98-6394.143" - cell $eq $eq$ls180.v:6394$2042 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6394$2042_Y - end - attribute \src "ls180.v:6395.101-6395.146" - cell $eq $eq$ls180.v:6395$2046 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6395$2046_Y - end - attribute \src "ls180.v:6397.97-6397.142" - cell $eq $eq$ls180.v:6397$2049 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6397$2049_Y - end - attribute \src "ls180.v:6398.100-6398.145" - cell $eq $eq$ls180.v:6398$2053 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6398$2053_Y - end - attribute \src "ls180.v:6400.103-6400.148" - cell $eq $eq$ls180.v:6400$2056 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6400$2056_Y - end - attribute \src "ls180.v:6401.106-6401.151" - cell $eq $eq$ls180.v:6401$2060 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6401$2060_Y - end - attribute \src "ls180.v:6403.106-6403.151" - cell $eq $eq$ls180.v:6403$2063 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6403$2063_Y - end - attribute \src "ls180.v:6404.109-6404.154" - cell $eq $eq$ls180.v:6404$2067 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6404$2067_Y - end - attribute \src "ls180.v:6406.106-6406.151" - cell $eq $eq$ls180.v:6406$2070 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6406$2070_Y - end - attribute \src "ls180.v:6407.109-6407.154" - cell $eq $eq$ls180.v:6407$2074 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_adr [3:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6407$2074_Y - end - attribute \src "ls180.v:6428.33-6428.79" - cell $eq $eq$ls180.v:6428$2077 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [13:8] - connect \B 2'10 - connect \Y $eq$ls180.v:6428$2077_Y - end - attribute \src "ls180.v:6430.99-6430.144" - cell $eq $eq$ls180.v:6430$2079 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6430$2079_Y - end - attribute \src "ls180.v:6431.102-6431.147" - cell $eq $eq$ls180.v:6431$2083 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6431$2083_Y - end - attribute \src "ls180.v:6433.99-6433.144" - cell $eq $eq$ls180.v:6433$2086 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6433$2086_Y - end - attribute \src "ls180.v:6434.102-6434.147" - cell $eq $eq$ls180.v:6434$2090 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6434$2090_Y - end - attribute \src "ls180.v:6436.99-6436.144" - cell $eq $eq$ls180.v:6436$2093 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6436$2093_Y - end - attribute \src "ls180.v:6437.102-6437.147" - cell $eq $eq$ls180.v:6437$2097 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6437$2097_Y - end - attribute \src "ls180.v:6439.99-6439.144" - cell $eq $eq$ls180.v:6439$2100 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6439$2100_Y - end - attribute \src "ls180.v:6440.102-6440.147" - cell $eq $eq$ls180.v:6440$2104 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6440$2104_Y - end - attribute \src "ls180.v:6442.101-6442.146" - cell $eq $eq$ls180.v:6442$2107 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6442$2107_Y - end - attribute \src "ls180.v:6443.104-6443.149" - cell $eq $eq$ls180.v:6443$2111 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6443$2111_Y - end - attribute \src "ls180.v:6445.101-6445.146" - cell $eq $eq$ls180.v:6445$2114 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6445$2114_Y - end - attribute \src "ls180.v:6446.104-6446.149" - cell $eq $eq$ls180.v:6446$2118 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6446$2118_Y - end - attribute \src "ls180.v:6448.101-6448.146" - cell $eq $eq$ls180.v:6448$2121 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6448$2121_Y - end - attribute \src "ls180.v:6449.104-6449.149" - cell $eq $eq$ls180.v:6449$2125 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6449$2125_Y - end - attribute \src "ls180.v:6451.101-6451.146" - cell $eq $eq$ls180.v:6451$2128 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6451$2128_Y - end - attribute \src "ls180.v:6452.104-6452.149" - cell $eq $eq$ls180.v:6452$2132 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6452$2132_Y - end - attribute \src "ls180.v:6454.97-6454.142" - cell $eq $eq$ls180.v:6454$2135 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6454$2135_Y - end - attribute \src "ls180.v:6455.100-6455.145" - cell $eq $eq$ls180.v:6455$2139 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1000 - connect \Y $eq$ls180.v:6455$2139_Y - end - attribute \src "ls180.v:6457.107-6457.152" - cell $eq $eq$ls180.v:6457$2142 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6457$2142_Y - end - attribute \src "ls180.v:6458.110-6458.155" - cell $eq $eq$ls180.v:6458$2146 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1001 - connect \Y $eq$ls180.v:6458$2146_Y - end - attribute \src "ls180.v:6460.100-6460.146" - cell $eq $eq$ls180.v:6460$2149 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:6460$2149_Y - end - attribute \src "ls180.v:6461.103-6461.149" - cell $eq $eq$ls180.v:6461$2153 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1010 - connect \Y $eq$ls180.v:6461$2153_Y - end - attribute \src "ls180.v:6463.100-6463.146" - cell $eq $eq$ls180.v:6463$2156 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:6463$2156_Y - end - attribute \src "ls180.v:6464.103-6464.149" - cell $eq $eq$ls180.v:6464$2160 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1011 - connect \Y $eq$ls180.v:6464$2160_Y - end - attribute \src "ls180.v:6466.100-6466.146" - cell $eq $eq$ls180.v:6466$2163 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:6466$2163_Y - end - attribute \src "ls180.v:6467.103-6467.149" - cell $eq $eq$ls180.v:6467$2167 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1100 - connect \Y $eq$ls180.v:6467$2167_Y - end - attribute \src "ls180.v:6469.100-6469.146" - cell $eq $eq$ls180.v:6469$2170 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:6469$2170_Y - end - attribute \src "ls180.v:6470.103-6470.149" - cell $eq $eq$ls180.v:6470$2174 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1101 - connect \Y $eq$ls180.v:6470$2174_Y - end - attribute \src "ls180.v:6472.112-6472.158" - cell $eq $eq$ls180.v:6472$2177 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:6472$2177_Y - end - attribute \src "ls180.v:6473.115-6473.161" - cell $eq $eq$ls180.v:6473$2181 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1110 - connect \Y $eq$ls180.v:6473$2181_Y - end - attribute \src "ls180.v:6475.113-6475.159" - cell $eq $eq$ls180.v:6475$2184 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1111 - connect \Y $eq$ls180.v:6475$2184_Y - end - attribute \src "ls180.v:6476.116-6476.162" - cell $eq $eq$ls180.v:6476$2188 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 4'1111 - connect \Y $eq$ls180.v:6476$2188_Y - end - attribute \src "ls180.v:6478.104-6478.150" - cell $eq $eq$ls180.v:6478$2191 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 5'10000 - connect \Y $eq$ls180.v:6478$2191_Y - end - attribute \src "ls180.v:6479.107-6479.153" - cell $eq $eq$ls180.v:6479$2195 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_adr [4:0] - connect \B 5'10000 - connect \Y $eq$ls180.v:6479$2195_Y - end - attribute \src "ls180.v:6496.33-6496.79" - cell $eq $eq$ls180.v:6496$2197 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [13:8] - connect \B 3'101 - connect \Y $eq$ls180.v:6496$2197_Y - end - attribute \src "ls180.v:6498.90-6498.135" - cell $eq $eq$ls180.v:6498$2199 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6498$2199_Y - end - attribute \src "ls180.v:6499.93-6499.138" - cell $eq $eq$ls180.v:6499$2203 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6499$2203_Y - end - attribute \src "ls180.v:6501.100-6501.145" - cell $eq $eq$ls180.v:6501$2206 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6501$2206_Y - end - attribute \src "ls180.v:6502.103-6502.148" - cell $eq $eq$ls180.v:6502$2210 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6502$2210_Y - end - attribute \src "ls180.v:6504.101-6504.146" - cell $eq $eq$ls180.v:6504$2213 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6504$2213_Y - end - attribute \src "ls180.v:6505.104-6505.149" - cell $eq $eq$ls180.v:6505$2217 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6505$2217_Y - end - attribute \src "ls180.v:6507.105-6507.150" - cell $eq $eq$ls180.v:6507$2220 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6507$2220_Y - end - attribute \src "ls180.v:6508.108-6508.153" - cell $eq $eq$ls180.v:6508$2224 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6508$2224_Y - end - attribute \src "ls180.v:6510.106-6510.151" - cell $eq $eq$ls180.v:6510$2227 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6510$2227_Y - end - attribute \src "ls180.v:6511.109-6511.154" - cell $eq $eq$ls180.v:6511$2231 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 3'100 - connect \Y $eq$ls180.v:6511$2231_Y - end - attribute \src "ls180.v:6513.104-6513.149" - cell $eq $eq$ls180.v:6513$2234 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6513$2234_Y - end - attribute \src "ls180.v:6514.107-6514.152" - cell $eq $eq$ls180.v:6514$2238 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 3'101 - connect \Y $eq$ls180.v:6514$2238_Y - end - attribute \src "ls180.v:6516.101-6516.146" - cell $eq $eq$ls180.v:6516$2241 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6516$2241_Y - end - attribute \src "ls180.v:6517.104-6517.149" - cell $eq $eq$ls180.v:6517$2245 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 3'110 - connect \Y $eq$ls180.v:6517$2245_Y - end - attribute \src "ls180.v:6519.100-6519.145" - cell $eq $eq$ls180.v:6519$2248 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6519$2248_Y - end - attribute \src "ls180.v:6520.103-6520.148" - cell $eq $eq$ls180.v:6520$2252 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_adr [2:0] - connect \B 3'111 - connect \Y $eq$ls180.v:6520$2252_Y - end - attribute \src "ls180.v:6530.33-6530.79" - cell $eq $eq$ls180.v:6530$2254 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [13:8] - connect \B 3'100 - connect \Y $eq$ls180.v:6530$2254_Y - end - attribute \src "ls180.v:6532.106-6532.151" - cell $eq $eq$ls180.v:6532$2256 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [1:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6532$2256_Y - end - attribute \src "ls180.v:6533.109-6533.154" - cell $eq $eq$ls180.v:6533$2260 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [1:0] - connect \B 1'0 - connect \Y $eq$ls180.v:6533$2260_Y - end - attribute \src "ls180.v:6535.106-6535.151" - cell $eq $eq$ls180.v:6535$2263 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [1:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6535$2263_Y - end - attribute \src "ls180.v:6536.109-6536.154" - cell $eq $eq$ls180.v:6536$2267 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [1:0] - connect \B 1'1 - connect \Y $eq$ls180.v:6536$2267_Y - end - attribute \src "ls180.v:6538.106-6538.151" - cell $eq $eq$ls180.v:6538$2270 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [1:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6538$2270_Y - end - attribute \src "ls180.v:6539.109-6539.154" - cell $eq $eq$ls180.v:6539$2274 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [1:0] - connect \B 2'10 - connect \Y $eq$ls180.v:6539$2274_Y - end - attribute \src "ls180.v:6541.106-6541.151" - cell $eq $eq$ls180.v:6541$2277 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [1:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6541$2277_Y - end - attribute \src "ls180.v:6542.109-6542.154" - cell $eq $eq$ls180.v:6542$2281 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_adr [1:0] - connect \B 2'11 - connect \Y $eq$ls180.v:6542$2281_Y - end - attribute \src "ls180.v:6923.41-6923.81" - cell $eq $eq$ls180.v:6923$2318 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 1'0 - connect \Y $eq$ls180.v:6923$2318_Y - end - attribute \src "ls180.v:6923.144-6923.177" - cell $eq $eq$ls180.v:6923$2319 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6923$2319_Y - end - attribute \src "ls180.v:6923.219-6923.252" - cell $eq $eq$ls180.v:6923$2322 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6923$2322_Y - end - attribute \src "ls180.v:6923.294-6923.327" - cell $eq $eq$ls180.v:6923$2325 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6923$2325_Y - end - attribute \src "ls180.v:6947.41-6947.81" - cell $eq $eq$ls180.v:6947$2334 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 1'1 - connect \Y $eq$ls180.v:6947$2334_Y - end - attribute \src "ls180.v:6947.144-6947.177" - cell $eq $eq$ls180.v:6947$2335 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6947$2335_Y - end - attribute \src "ls180.v:6947.219-6947.252" - cell $eq $eq$ls180.v:6947$2338 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6947$2338_Y - end - attribute \src "ls180.v:6947.294-6947.327" - cell $eq $eq$ls180.v:6947$2341 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6947$2341_Y - end - attribute \src "ls180.v:6971.41-6971.81" - cell $eq $eq$ls180.v:6971$2350 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 2'10 - connect \Y $eq$ls180.v:6971$2350_Y - end - attribute \src "ls180.v:6971.144-6971.177" - cell $eq $eq$ls180.v:6971$2351 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6971$2351_Y - end - attribute \src "ls180.v:6971.219-6971.252" - cell $eq $eq$ls180.v:6971$2354 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6971$2354_Y - end - attribute \src "ls180.v:6971.294-6971.327" - cell $eq $eq$ls180.v:6971$2357 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6971$2357_Y - end - attribute \src "ls180.v:6995.41-6995.81" - cell $eq $eq$ls180.v:6995$2366 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_addr [10:9] - connect \B 2'11 - connect \Y $eq$ls180.v:6995$2366_Y - end - attribute \src "ls180.v:6995.144-6995.177" - cell $eq $eq$ls180.v:6995$2367 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6995$2367_Y - end - attribute \src "ls180.v:6995.219-6995.252" - cell $eq $eq$ls180.v:6995$2370 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6995$2370_Y - end - attribute \src "ls180.v:6995.294-6995.327" - cell $eq $eq$ls180.v:6995$2373 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:6995$2373_Y - end - attribute \src "ls180.v:7579.8-7579.38" - cell $eq $eq$ls180.v:7579$2467 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_value - connect \B 1'0 - connect \Y $eq$ls180.v:7579$2467_Y - end - attribute \src "ls180.v:7614.8-7614.42" - cell $eq $eq$ls180.v:7614$2478 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_postponer_count - connect \B 1'0 - connect \Y $eq$ls180.v:7614$2478_Y - end - attribute \src "ls180.v:7634.38-7634.74" - cell $eq $eq$ls180.v:7634$2481 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_counter - connect \B 1'0 - connect \Y $eq$ls180.v:7634$2481_Y - end - attribute \src "ls180.v:7641.7-7641.43" - cell $eq $eq$ls180.v:7641$2483 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_counter - connect \B 2'10 - connect \Y $eq$ls180.v:7641$2483_Y - end - attribute \src "ls180.v:7648.7-7648.43" - cell $eq $eq$ls180.v:7648$2484 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_counter - connect \B 4'1000 - connect \Y $eq$ls180.v:7648$2484_Y - end - attribute \src "ls180.v:7656.7-7656.43" - cell $eq $eq$ls180.v:7656$2485 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_counter - connect \B 4'1000 - connect \Y $eq$ls180.v:7656$2485_Y - end - attribute \src "ls180.v:7708.9-7708.54" - cell $eq $eq$ls180.v:7708$2503 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_twtpcon_count - connect \B 1'1 - connect \Y $eq$ls180.v:7708$2503_Y - end - attribute \src "ls180.v:7754.9-7754.54" - cell $eq $eq$ls180.v:7754$2519 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_twtpcon_count - connect \B 1'1 - connect \Y $eq$ls180.v:7754$2519_Y - end - attribute \src "ls180.v:7800.9-7800.54" - cell $eq $eq$ls180.v:7800$2535 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_twtpcon_count - connect \B 1'1 - connect \Y $eq$ls180.v:7800$2535_Y - end - attribute \src "ls180.v:7846.9-7846.54" - cell $eq $eq$ls180.v:7846$2551 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_twtpcon_count - connect \B 1'1 - connect \Y $eq$ls180.v:7846$2551_Y - end - attribute \src "ls180.v:7996.9-7996.41" - cell $eq $eq$ls180.v:7996$2563 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_tccdcon_count - connect \B 1'1 - connect \Y $eq$ls180.v:7996$2563_Y - end - attribute \src "ls180.v:8011.9-8011.41" - cell $eq $eq$ls180.v:8011$2566 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_twtrcon_count - connect \B 1'1 - connect \Y $eq$ls180.v:8011$2566_Y - end - attribute \src "ls180.v:8017.49-8017.82" - cell $eq $eq$ls180.v:8017$2567 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:8017$2567_Y - end - attribute \src "ls180.v:8017.131-8017.164" - cell $eq $eq$ls180.v:8017$2570 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:8017$2570_Y - end - attribute \src "ls180.v:8017.213-8017.246" - cell $eq $eq$ls180.v:8017$2573 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:8017$2573_Y - end - attribute \src "ls180.v:8017.295-8017.328" - cell $eq $eq$ls180.v:8017$2576 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:8017$2576_Y - end - attribute \src "ls180.v:8018.50-8018.83" - cell $eq $eq$ls180.v:8018$2579 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin0_grant - connect \B 1'0 - connect \Y $eq$ls180.v:8018$2579_Y - end - attribute \src "ls180.v:8018.132-8018.165" - cell $eq $eq$ls180.v:8018$2582 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin1_grant - connect \B 1'0 - connect \Y $eq$ls180.v:8018$2582_Y - end - attribute \src "ls180.v:8018.214-8018.247" - cell $eq $eq$ls180.v:8018$2585 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin2_grant - connect \B 1'0 - connect \Y $eq$ls180.v:8018$2585_Y - end - attribute \src "ls180.v:8018.296-8018.329" - cell $eq $eq$ls180.v:8018$2588 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_roundrobin3_grant - connect \B 1'0 - connect \Y $eq$ls180.v:8018$2588_Y - end - attribute \src "ls180.v:8053.9-8053.42" - cell $eq $eq$ls180.v:8053$2600 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_tx_bitcount - connect \B 4'1000 - connect \Y $eq$ls180.v:8053$2600_Y - end - attribute \src "ls180.v:8056.10-8056.43" - cell $eq $eq$ls180.v:8056$2601 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_tx_bitcount - connect \B 4'1001 - connect \Y $eq$ls180.v:8056$2601_Y - end - attribute \src "ls180.v:8082.9-8082.42" - cell $eq $eq$ls180.v:8082$2607 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_rx_bitcount - connect \B 1'0 - connect \Y $eq$ls180.v:8082$2607_Y - end - attribute \src "ls180.v:8087.10-8087.43" - cell $eq $eq$ls180.v:8087$2608 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_rx_bitcount - connect \B 4'1001 - connect \Y $eq$ls180.v:8087$2608_Y - end - attribute \src "ls180.v:8294.9-8294.53" - cell $eq $eq$ls180.v:8294$2657 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_converter_demux - connect \B 3'111 - connect \Y $eq$ls180.v:8294$2657_Y - end - attribute \src "ls180.v:8375.9-8375.54" - cell $eq $eq$ls180.v:8375$2669 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_converter_demux - connect \B 3'111 - connect \Y $eq$ls180.v:8375$2669_Y - end - attribute \src "ls180.v:8454.9-8454.55" - cell $eq $eq$ls180.v:8454$2681 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_demux - connect \B 1'1 - connect \Y $eq$ls180.v:8454$2681_Y - end - attribute \src "ls180.v:8677.9-8677.49" - cell $eq $eq$ls180.v:8677$2714 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_converter_demux - connect \B 3'111 - connect \Y $eq$ls180.v:8677$2714_Y - end - attribute \src "ls180.v:8253.8-8253.54" - cell $ge $ge$ls180.v:8253$2649 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_pwm0_counter - connect \B $sub$ls180.v:8253$2648_Y - connect \Y $ge$ls180.v:8253$2649_Y - end - attribute \src "ls180.v:8267.8-8267.54" - cell $ge $ge$ls180.v:8267$2653 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_pwm1_counter - connect \B $sub$ls180.v:8267$2652_Y - connect \Y $ge$ls180.v:8267$2653_Y - end - attribute \src "ls180.v:5211.47-5211.83" - cell $gt $gt$ls180.v:5211$965 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_cnt - connect \B 3'111 - connect \Y $gt$ls180.v:5211$965_Y - end - attribute \src "ls180.v:5217.7-5217.43" - cell $lt $lt$ls180.v:5217$968 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_cnt - connect \B 4'1000 - connect \Y $lt$ls180.v:5217$968_Y - end - attribute \src "ls180.v:8248.8-8248.43" - cell $lt $lt$ls180.v:8248$2647 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_pwm0_counter - connect \B \main_pwm0_width - connect \Y $lt$ls180.v:8248$2647_Y - end - attribute \src "ls180.v:8262.8-8262.43" - cell $lt $lt$ls180.v:8262$2651 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_pwm1_counter - connect \B \main_pwm1_width - connect \Y $lt$ls180.v:8262$2651_Y - end - attribute \src "ls180.v:10164.33-10164.36" - cell $memrd $memrd$\mem$ls180.v:10164$2768 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem" - parameter \TRANSPARENT 0 - parameter \WIDTH 64 - connect \ADDR \memadr - connect \CLK 1'x - connect \DATA $memrd$\mem$ls180.v:10164$2768_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10192.25-10192.30" - cell $memrd $memrd$\mem_1$ls180.v:10192$2794 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_1" - parameter \TRANSPARENT 0 - parameter \WIDTH 64 - connect \ADDR \memadr_1 - connect \CLK 1'x - connect \DATA $memrd$\mem_1$ls180.v:10192$2794_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10203.12-10203.19" - cell $memrd $memrd$\storage$ls180.v:10203$2799 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage$ls180.v:10203$2799_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10210.68-10210.75" - cell $memrd $memrd$\storage$ls180.v:10210$2801 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage$ls180.v:10210$2801_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10217.14-10217.23" - cell $memrd $memrd$\storage_1$ls180.v:10217$2806 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_1" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_1$ls180.v:10217$2806_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10224.68-10224.77" - cell $memrd $memrd$\storage_1$ls180.v:10224$2808 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_1" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_1$ls180.v:10224$2808_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10231.14-10231.23" - cell $memrd $memrd$\storage_2$ls180.v:10231$2813 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_2" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_2$ls180.v:10231$2813_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10238.68-10238.77" - cell $memrd $memrd$\storage_2$ls180.v:10238$2815 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_2" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_2$ls180.v:10238$2815_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10245.14-10245.23" - cell $memrd $memrd$\storage_3$ls180.v:10245$2820 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_3" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_3$ls180.v:10245$2820_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10252.68-10252.77" - cell $memrd $memrd$\storage_3$ls180.v:10252$2822 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_3" - parameter \TRANSPARENT 0 - parameter \WIDTH 25 - connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_3$ls180.v:10252$2822_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10260.14-10260.23" - cell $memrd $memrd$\storage_4$ls180.v:10260$2827 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_4" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_uart_tx_fifo_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_4$ls180.v:10260$2827_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10265.15-10265.24" - cell $memrd $memrd$\storage_4$ls180.v:10265$2829 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_4" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_uart_tx_fifo_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_4$ls180.v:10265$2829_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10277.14-10277.23" - cell $memrd $memrd$\storage_5$ls180.v:10277$2834 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_5" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_uart_rx_fifo_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_5$ls180.v:10277$2834_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10282.15-10282.24" - cell $memrd $memrd$\storage_5$ls180.v:10282$2836 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_5" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_uart_rx_fifo_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_5$ls180.v:10282$2836_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10293.14-10293.23" - cell $memrd $memrd$\storage_6$ls180.v:10293$2841 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_6" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_sdblock2mem_fifo_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_6$ls180.v:10293$2841_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10300.45-10300.54" - cell $memrd $memrd$\storage_6$ls180.v:10300$2843 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_6" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_sdblock2mem_fifo_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_6$ls180.v:10300$2843_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10307.14-10307.23" - cell $memrd $memrd$\storage_7$ls180.v:10307$2848 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_7" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_sdmem2block_fifo_wrport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_7$ls180.v:10307$2848_DATA - connect \EN 1'x - end - attribute \src "ls180.v:10314.45-10314.54" - cell $memrd $memrd$\storage_7$ls180.v:10314$2850 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_7" - parameter \TRANSPARENT 0 - parameter \WIDTH 10 - connect \ADDR \main_sdmem2block_fifo_rdport_adr - connect \CLK 1'x - connect \DATA $memrd$\storage_7$ls180.v:10314$2850_DATA - connect \EN 1'x - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$2852 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem" - parameter \PRIORITY 2852 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem$ls180.v:10146$1_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10146$1_DATA - connect \EN $memwr$\mem$ls180.v:10146$1_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$2853 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem" - parameter \PRIORITY 2853 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem$ls180.v:10148$2_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10148$2_DATA - connect \EN $memwr$\mem$ls180.v:10148$2_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$2854 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem" - parameter \PRIORITY 2854 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem$ls180.v:10150$3_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10150$3_DATA - connect \EN $memwr$\mem$ls180.v:10150$3_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$2855 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem" - parameter \PRIORITY 2855 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem$ls180.v:10152$4_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10152$4_DATA - connect \EN $memwr$\mem$ls180.v:10152$4_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$2856 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem" - parameter \PRIORITY 2856 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem$ls180.v:10154$5_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10154$5_DATA - connect \EN $memwr$\mem$ls180.v:10154$5_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$2857 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem" - parameter \PRIORITY 2857 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem$ls180.v:10156$6_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10156$6_DATA - connect \EN $memwr$\mem$ls180.v:10156$6_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$2858 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem" - parameter \PRIORITY 2858 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem$ls180.v:10158$7_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10158$7_DATA - connect \EN $memwr$\mem$ls180.v:10158$7_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem$ls180.v:0$2859 - parameter \ABITS 6 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem" - parameter \PRIORITY 2859 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem$ls180.v:10160$8_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem$ls180.v:10160$8_DATA - connect \EN $memwr$\mem$ls180.v:10160$8_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$2860 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_1" - parameter \PRIORITY 2860 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_1$ls180.v:10174$9_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10174$9_DATA - connect \EN $memwr$\mem_1$ls180.v:10174$9_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$2861 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_1" - parameter \PRIORITY 2861 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_1$ls180.v:10176$10_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10176$10_DATA - connect \EN $memwr$\mem_1$ls180.v:10176$10_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$2862 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_1" - parameter \PRIORITY 2862 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_1$ls180.v:10178$11_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10178$11_DATA - connect \EN $memwr$\mem_1$ls180.v:10178$11_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$2863 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_1" - parameter \PRIORITY 2863 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_1$ls180.v:10180$12_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10180$12_DATA - connect \EN $memwr$\mem_1$ls180.v:10180$12_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$2864 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_1" - parameter \PRIORITY 2864 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_1$ls180.v:10182$13_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10182$13_DATA - connect \EN $memwr$\mem_1$ls180.v:10182$13_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$2865 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_1" - parameter \PRIORITY 2865 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_1$ls180.v:10184$14_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10184$14_DATA - connect \EN $memwr$\mem_1$ls180.v:10184$14_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$2866 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_1" - parameter \PRIORITY 2866 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_1$ls180.v:10186$15_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10186$15_DATA - connect \EN $memwr$\mem_1$ls180.v:10186$15_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\mem_1$ls180.v:0$2867 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\mem_1" - parameter \PRIORITY 2867 - parameter \WIDTH 64 - connect \ADDR $memwr$\mem_1$ls180.v:10188$16_ADDR - connect \CLK 1'x - connect \DATA $memwr$\mem_1$ls180.v:10188$16_DATA - connect \EN $memwr$\mem_1$ls180.v:10188$16_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage$ls180.v:0$2868 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage" - parameter \PRIORITY 2868 - parameter \WIDTH 25 - connect \ADDR $memwr$\storage$ls180.v:10202$17_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage$ls180.v:10202$17_DATA - connect \EN $memwr$\storage$ls180.v:10202$17_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_1$ls180.v:0$2869 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_1" - parameter \PRIORITY 2869 - parameter \WIDTH 25 - connect \ADDR $memwr$\storage_1$ls180.v:10216$18_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage_1$ls180.v:10216$18_DATA - connect \EN $memwr$\storage_1$ls180.v:10216$18_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_2$ls180.v:0$2870 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_2" - parameter \PRIORITY 2870 - parameter \WIDTH 25 - connect \ADDR $memwr$\storage_2$ls180.v:10230$19_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage_2$ls180.v:10230$19_DATA - connect \EN $memwr$\storage_2$ls180.v:10230$19_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_3$ls180.v:0$2871 - parameter \ABITS 3 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_3" - parameter \PRIORITY 2871 - parameter \WIDTH 25 - connect \ADDR $memwr$\storage_3$ls180.v:10244$20_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage_3$ls180.v:10244$20_DATA - connect \EN $memwr$\storage_3$ls180.v:10244$20_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_4$ls180.v:0$2872 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_4" - parameter \PRIORITY 2872 - parameter \WIDTH 10 - connect \ADDR $memwr$\storage_4$ls180.v:10259$21_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage_4$ls180.v:10259$21_DATA - connect \EN $memwr$\storage_4$ls180.v:10259$21_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_5$ls180.v:0$2873 - parameter \ABITS 4 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_5" - parameter \PRIORITY 2873 - parameter \WIDTH 10 - connect \ADDR $memwr$\storage_5$ls180.v:10276$22_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage_5$ls180.v:10276$22_DATA - connect \EN $memwr$\storage_5$ls180.v:10276$22_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_6$ls180.v:0$2874 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_6" - parameter \PRIORITY 2874 - parameter \WIDTH 10 - connect \ADDR $memwr$\storage_6$ls180.v:10292$23_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage_6$ls180.v:10292$23_DATA - connect \EN $memwr$\storage_6$ls180.v:10292$23_EN - end - attribute \src "ls180.v:0.0-0.0" - cell $memwr $memwr$\storage_7$ls180.v:0$2875 - parameter \ABITS 5 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\storage_7" - parameter \PRIORITY 2875 - parameter \WIDTH 10 - connect \ADDR $memwr$\storage_7$ls180.v:10306$24_ADDR - connect \CLK 1'x - connect \DATA $memwr$\storage_7$ls180.v:10306$24_DATA - connect \EN $memwr$\storage_7$ls180.v:10306$24_EN - end - attribute \src "ls180.v:3000.41-3000.71" - cell $ne $ne$ls180.v:3000$84 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_value - connect \B 1'0 - connect \Y $ne$ls180.v:3000$84_Y - end - attribute \src "ls180.v:3175.70-3175.104" - cell $ne $ne$ls180.v:3175$123 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_count - connect \B 1'0 - connect \Y $ne$ls180.v:3175$123_Y - end - attribute \src "ls180.v:3236.8-3236.142" - cell $ne $ne$ls180.v:3236$142 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr [21:9] - connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3236$142_Y - end - attribute \src "ls180.v:3268.75-3268.133" - cell $ne $ne$ls180.v:3268$149 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level - connect \B 4'1000 - connect \Y $ne$ls180.v:3268$149_Y - end - attribute \src "ls180.v:3269.75-3269.133" - cell $ne $ne$ls180.v:3269$150 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level - connect \B 1'0 - connect \Y $ne$ls180.v:3269$150_Y - end - attribute \src "ls180.v:3393.8-3393.142" - cell $ne $ne$ls180.v:3393$172 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr [21:9] - connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3393$172_Y - end - attribute \src "ls180.v:3425.75-3425.133" - cell $ne $ne$ls180.v:3425$179 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level - connect \B 4'1000 - connect \Y $ne$ls180.v:3425$179_Y - end - attribute \src "ls180.v:3426.75-3426.133" - cell $ne $ne$ls180.v:3426$180 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level - connect \B 1'0 - connect \Y $ne$ls180.v:3426$180_Y - end - attribute \src "ls180.v:3550.8-3550.142" - cell $ne $ne$ls180.v:3550$202 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr [21:9] - connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3550$202_Y - end - attribute \src "ls180.v:3582.75-3582.133" - cell $ne $ne$ls180.v:3582$209 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level - connect \B 4'1000 - connect \Y $ne$ls180.v:3582$209_Y - end - attribute \src "ls180.v:3583.75-3583.133" - cell $ne $ne$ls180.v:3583$210 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level - connect \B 1'0 - connect \Y $ne$ls180.v:3583$210_Y - end - attribute \src "ls180.v:3707.8-3707.142" - cell $ne $ne$ls180.v:3707$232 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr [21:9] - connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - connect \Y $ne$ls180.v:3707$232_Y - end - attribute \src "ls180.v:3739.75-3739.133" - cell $ne $ne$ls180.v:3739$239 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level - connect \B 4'1000 - connect \Y $ne$ls180.v:3739$239_Y - end - attribute \src "ls180.v:3740.75-3740.133" - cell $ne $ne$ls180.v:3740$240 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level - connect \B 1'0 - connect \Y $ne$ls180.v:3740$240_Y - end - attribute \src "ls180.v:4232.47-4232.80" - cell $ne $ne$ls180.v:4232$638 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_level0 - connect \B 5'10000 - connect \Y $ne$ls180.v:4232$638_Y - end - attribute \src "ls180.v:4233.47-4233.79" - cell $ne $ne$ls180.v:4233$639 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_level0 - connect \B 1'0 - connect \Y $ne$ls180.v:4233$639_Y - end - attribute \src "ls180.v:4262.47-4262.80" - cell $ne $ne$ls180.v:4262$649 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_level0 - connect \B 5'10000 - connect \Y $ne$ls180.v:4262$649_Y - end - attribute \src "ls180.v:4263.47-4263.79" - cell $ne $ne$ls180.v:4263$650 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_level0 - connect \B 1'0 - connect \Y $ne$ls180.v:4263$650_Y - end - attribute \src "ls180.v:4743.32-4743.89" - cell $ne $ne$ls180.v:4743$732 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_source_source_payload_data0 - connect \B 3'101 - connect \Y $ne$ls180.v:4743$732_Y - end - attribute \src "ls180.v:5390.10-5390.56" - cell $ne $ne$ls180.v:5390$1029 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_source_payload_status - connect \B 2'10 - connect \Y $ne$ls180.v:5390$1029_Y - end - attribute \src "ls180.v:5495.51-5495.87" - cell $ne $ne$ls180.v:5495$1043 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_level - connect \B 6'100000 - connect \Y $ne$ls180.v:5495$1043_Y - end - attribute \src "ls180.v:5496.51-5496.86" - cell $ne $ne$ls180.v:5496$1044 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_level - connect \B 1'0 - connect \Y $ne$ls180.v:5496$1044_Y - end - attribute \src "ls180.v:5715.51-5715.87" - cell $ne $ne$ls180.v:5715$1074 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_level - connect \B 6'100000 - connect \Y $ne$ls180.v:5715$1074_Y - end - attribute \src "ls180.v:5716.51-5716.86" - cell $ne $ne$ls180.v:5716$1075 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_level - connect \B 1'0 - connect \Y $ne$ls180.v:5716$1075_Y - end - attribute \src "ls180.v:5747.79-5747.119" - cell $ne $ne$ls180.v:5747$1078 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_libresocsim_wishbone_sel - connect \B 1'0 - connect \Y $ne$ls180.v:5747$1078_Y - end - attribute \src "ls180.v:7569.7-7569.52" - cell $ne $ne$ls180.v:7569$2462 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_bus_errors - connect \B 32'11111111111111111111111111111111 - connect \Y $ne$ls180.v:7569$2462_Y - end - attribute \src "ls180.v:7623.9-7623.43" - cell $ne $ne$ls180.v:7623$2479 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_count - connect \B 1'0 - connect \Y $ne$ls180.v:7623$2479_Y - end - attribute \src "ls180.v:7659.8-7659.44" - cell $ne $ne$ls180.v:7659$2486 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_counter - connect \B 1'0 - connect \Y $ne$ls180.v:7659$2486_Y - end - attribute \src "ls180.v:8597.9-8597.47" - cell $ne $ne$ls180.v:8597$2701 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_cnt - connect \B 4'1010 - connect \Y $ne$ls180.v:8597$2701_Y - end - attribute \src "ls180.v:2804.33-2804.73" - cell $not $not$ls180.v:2804$26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface0_converted_interface_cyc - connect \Y $not$ls180.v:2804$26_Y - end - attribute \src "ls180.v:2843.48-2843.69" - cell $not $not$ls180.v:2843$31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_converter0_skip - connect \Y $not$ls180.v:2843$31_Y - end - attribute \src "ls180.v:2844.48-2844.69" - cell $not $not$ls180.v:2844$32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_converter0_skip - connect \Y $not$ls180.v:2844$32_Y - end - attribute \src "ls180.v:2864.33-2864.73" - cell $not $not$ls180.v:2864$37 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_interface1_converted_interface_cyc - connect \Y $not$ls180.v:2864$37_Y - end - attribute \src "ls180.v:2903.48-2903.69" - cell $not $not$ls180.v:2903$42 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_converter1_skip - connect \Y $not$ls180.v:2903$42_Y - end - attribute \src "ls180.v:2904.48-2904.69" - cell $not $not$ls180.v:2904$43 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_converter1_skip - connect \Y $not$ls180.v:2904$43_Y - end - attribute \src "ls180.v:2924.36-2924.79" - cell $not $not$ls180.v:2924$48 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_socbushandler_converted_interface_cyc - connect \Y $not$ls180.v:2924$48_Y - end - attribute \src "ls180.v:2963.27-2963.51" - cell $not $not$ls180.v:2963$53 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_socbushandler_skip - connect \Y $not$ls180.v:2963$53_Y - end - attribute \src "ls180.v:2964.27-2964.51" - cell $not $not$ls180.v:2964$54 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_socbushandler_skip - connect \Y $not$ls180.v:2964$54_Y - end - attribute \src "ls180.v:3124.34-3124.64" - cell $not $not$ls180.v:3124$115 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_command_storage [0] - connect \Y $not$ls180.v:3124$115_Y - end - attribute \src "ls180.v:3125.31-3125.61" - cell $not $not$ls180.v:3125$116 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_command_storage [1] - connect \Y $not$ls180.v:3125$116_Y - end - attribute \src "ls180.v:3126.32-3126.62" - cell $not $not$ls180.v:3126$117 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_command_storage [2] - connect \Y $not$ls180.v:3126$117_Y - end - attribute \src "ls180.v:3127.32-3127.62" - cell $not $not$ls180.v:3127$118 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_command_storage [3] - connect \Y $not$ls180.v:3127$118_Y - end - attribute \src "ls180.v:3169.33-3169.56" - cell $not $not$ls180.v:3169$121 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_timer_done0 - connect \Y $not$ls180.v:3169$121_Y - end - attribute \src "ls180.v:3270.58-3270.106" - cell $not $not$ls180.v:3270$151 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $not$ls180.v:3270$151_Y - end - attribute \src "ls180.v:3324.9-3324.45" - cell $not $not$ls180.v:3324$156 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_refresh_req - connect \Y $not$ls180.v:3324$156_Y - end - attribute \src "ls180.v:3427.58-3427.106" - cell $not $not$ls180.v:3427$181 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $not$ls180.v:3427$181_Y - end - attribute \src "ls180.v:3481.9-3481.45" - cell $not $not$ls180.v:3481$186 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_refresh_req - connect \Y $not$ls180.v:3481$186_Y - end - attribute \src "ls180.v:3584.58-3584.106" - cell $not $not$ls180.v:3584$211 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $not$ls180.v:3584$211_Y - end - attribute \src "ls180.v:3638.9-3638.45" - cell $not $not$ls180.v:3638$216 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_refresh_req - connect \Y $not$ls180.v:3638$216_Y - end - attribute \src "ls180.v:3741.58-3741.106" - cell $not $not$ls180.v:3741$241 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $not$ls180.v:3741$241_Y - end - attribute \src "ls180.v:3795.9-3795.45" - cell $not $not$ls180.v:3795$246 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_refresh_req - connect \Y $not$ls180.v:3795$246_Y - end - attribute \src "ls180.v:3837.149-3837.187" - cell $not $not$ls180.v:3837$249 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:3837$249_Y - end - attribute \src "ls180.v:3837.193-3837.230" - cell $not $not$ls180.v:3837$251 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:3837$251_Y - end - attribute \src "ls180.v:3838.149-3838.187" - cell $not $not$ls180.v:3838$255 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:3838$255_Y - end - attribute \src "ls180.v:3838.193-3838.230" - cell $not $not$ls180.v:3838$257 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:3838$257_Y - end - attribute \src "ls180.v:3854.43-3854.73" - cell $not $not$ls180.v:3854$285 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \main_sdram_interface_wdata_we - connect \Y $not$ls180.v:3854$285_Y - end - attribute \src "ls180.v:3857.205-3857.245" - cell $not $not$ls180.v:3857$288 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_cas - connect \Y $not$ls180.v:3857$288_Y - end - attribute \src "ls180.v:3857.251-3857.290" - cell $not $not$ls180.v:3857$290 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_we - connect \Y $not$ls180.v:3857$290_Y - end - attribute \src "ls180.v:3857.159-3857.292" - cell $not $not$ls180.v:3857$292 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3857$291_Y - connect \Y $not$ls180.v:3857$292_Y - end - attribute \src "ls180.v:3858.205-3858.245" - cell $not $not$ls180.v:3858$301 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_cas - connect \Y $not$ls180.v:3858$301_Y - end - attribute \src "ls180.v:3858.251-3858.290" - cell $not $not$ls180.v:3858$303 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_we - connect \Y $not$ls180.v:3858$303_Y - end - attribute \src "ls180.v:3858.159-3858.292" - cell $not $not$ls180.v:3858$305 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3858$304_Y - connect \Y $not$ls180.v:3858$305_Y - end - attribute \src "ls180.v:3859.205-3859.245" - cell $not $not$ls180.v:3859$314 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_cas - connect \Y $not$ls180.v:3859$314_Y - end - attribute \src "ls180.v:3859.251-3859.290" - cell $not $not$ls180.v:3859$316 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_we - connect \Y $not$ls180.v:3859$316_Y - end - attribute \src "ls180.v:3859.159-3859.292" - cell $not $not$ls180.v:3859$318 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3859$317_Y - connect \Y $not$ls180.v:3859$318_Y - end - attribute \src "ls180.v:3860.205-3860.245" - cell $not $not$ls180.v:3860$327 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_cas - connect \Y $not$ls180.v:3860$327_Y - end - attribute \src "ls180.v:3860.251-3860.290" - cell $not $not$ls180.v:3860$329 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_we - connect \Y $not$ls180.v:3860$329_Y - end - attribute \src "ls180.v:3860.159-3860.292" - cell $not $not$ls180.v:3860$331 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3860$330_Y - connect \Y $not$ls180.v:3860$331_Y - end - attribute \src "ls180.v:3887.71-3887.103" - cell $not $not$ls180.v:3887$342 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_cmd_valid - connect \Y $not$ls180.v:3887$342_Y - end - attribute \src "ls180.v:3890.205-3890.245" - cell $not $not$ls180.v:3890$346 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_cas - connect \Y $not$ls180.v:3890$346_Y - end - attribute \src "ls180.v:3890.251-3890.290" - cell $not $not$ls180.v:3890$348 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_payload_we - connect \Y $not$ls180.v:3890$348_Y - end - attribute \src "ls180.v:3890.159-3890.292" - cell $not $not$ls180.v:3890$350 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3890$349_Y - connect \Y $not$ls180.v:3890$350_Y - end - attribute \src "ls180.v:3891.205-3891.245" - cell $not $not$ls180.v:3891$359 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_cas - connect \Y $not$ls180.v:3891$359_Y - end - attribute \src "ls180.v:3891.251-3891.290" - cell $not $not$ls180.v:3891$361 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_payload_we - connect \Y $not$ls180.v:3891$361_Y - end - attribute \src "ls180.v:3891.159-3891.292" - cell $not $not$ls180.v:3891$363 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3891$362_Y - connect \Y $not$ls180.v:3891$363_Y - end - attribute \src "ls180.v:3892.205-3892.245" - cell $not $not$ls180.v:3892$372 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_cas - connect \Y $not$ls180.v:3892$372_Y - end - attribute \src "ls180.v:3892.251-3892.290" - cell $not $not$ls180.v:3892$374 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_payload_we - connect \Y $not$ls180.v:3892$374_Y - end - attribute \src "ls180.v:3892.159-3892.292" - cell $not $not$ls180.v:3892$376 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3892$375_Y - connect \Y $not$ls180.v:3892$376_Y - end - attribute \src "ls180.v:3893.205-3893.245" - cell $not $not$ls180.v:3893$385 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_cas - connect \Y $not$ls180.v:3893$385_Y - end - attribute \src "ls180.v:3893.251-3893.290" - cell $not $not$ls180.v:3893$387 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_payload_we - connect \Y $not$ls180.v:3893$387_Y - end - attribute \src "ls180.v:3893.159-3893.292" - cell $not $not$ls180.v:3893$389 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3893$388_Y - connect \Y $not$ls180.v:3893$389_Y - end - attribute \src "ls180.v:3956.71-3956.103" - cell $not $not$ls180.v:3956$428 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_valid - connect \Y $not$ls180.v:3956$428_Y - end - attribute \src "ls180.v:3977.112-3977.150" - cell $not $not$ls180.v:3977$431 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:3977$431_Y - end - attribute \src "ls180.v:3977.156-3977.193" - cell $not $not$ls180.v:3977$433 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:3977$433_Y - end - attribute \src "ls180.v:3977.68-3977.195" - cell $not $not$ls180.v:3977$435 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3977$434_Y - connect \Y $not$ls180.v:3977$435_Y - end - attribute \src "ls180.v:3985.11-3985.38" - cell $not $not$ls180.v:3985$438 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_write_available - connect \Y $not$ls180.v:3985$438_Y - end - attribute \src "ls180.v:4015.112-4015.150" - cell $not $not$ls180.v:4015$440 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_cas - connect \Y $not$ls180.v:4015$440_Y - end - attribute \src "ls180.v:4015.156-4015.193" - cell $not $not$ls180.v:4015$442 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_we - connect \Y $not$ls180.v:4015$442_Y - end - attribute \src "ls180.v:4015.68-4015.195" - cell $not $not$ls180.v:4015$444 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4015$443_Y - connect \Y $not$ls180.v:4015$444_Y - end - attribute \src "ls180.v:4023.11-4023.37" - cell $not $not$ls180.v:4023$447 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_read_available - connect \Y $not$ls180.v:4023$447_Y - end - attribute \src "ls180.v:4033.87-4033.331" - cell $not $not$ls180.v:4033$459 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4033$458_Y - connect \Y $not$ls180.v:4033$459_Y - end - attribute \src "ls180.v:4034.35-4034.68" - cell $not $not$ls180.v:4034$462 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_valid - connect \Y $not$ls180.v:4034$462_Y - end - attribute \src "ls180.v:4034.73-4034.105" - cell $not $not$ls180.v:4034$463 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank0_lock - connect \Y $not$ls180.v:4034$463_Y - end - attribute \src "ls180.v:4038.87-4038.331" - cell $not $not$ls180.v:4038$475 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4038$474_Y - connect \Y $not$ls180.v:4038$475_Y - end - attribute \src "ls180.v:4039.35-4039.68" - cell $not $not$ls180.v:4039$478 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_valid - connect \Y $not$ls180.v:4039$478_Y - end - attribute \src "ls180.v:4039.73-4039.105" - cell $not $not$ls180.v:4039$479 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank1_lock - connect \Y $not$ls180.v:4039$479_Y - end - attribute \src "ls180.v:4043.87-4043.331" - cell $not $not$ls180.v:4043$491 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4043$490_Y - connect \Y $not$ls180.v:4043$491_Y - end - attribute \src "ls180.v:4044.35-4044.68" - cell $not $not$ls180.v:4044$494 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_valid - connect \Y $not$ls180.v:4044$494_Y - end - attribute \src "ls180.v:4044.73-4044.105" - cell $not $not$ls180.v:4044$495 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank2_lock - connect \Y $not$ls180.v:4044$495_Y - end - attribute \src "ls180.v:4048.87-4048.331" - cell $not $not$ls180.v:4048$507 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4048$506_Y - connect \Y $not$ls180.v:4048$507_Y - end - attribute \src "ls180.v:4049.35-4049.68" - cell $not $not$ls180.v:4049$510 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_valid - connect \Y $not$ls180.v:4049$510_Y - end - attribute \src "ls180.v:4049.73-4049.105" - cell $not $not$ls180.v:4049$511 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_interface_bank3_lock - connect \Y $not$ls180.v:4049$511_Y - end - attribute \src "ls180.v:4053.128-4053.372" - cell $not $not$ls180.v:4053$524 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4053$523_Y - connect \Y $not$ls180.v:4053$524_Y - end - attribute \src "ls180.v:4053.502-4053.746" - cell $not $not$ls180.v:4053$540 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4053$539_Y - connect \Y $not$ls180.v:4053$540_Y - end - attribute \src "ls180.v:4053.876-4053.1120" - cell $not $not$ls180.v:4053$556 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4053$555_Y - connect \Y $not$ls180.v:4053$556_Y - end - attribute \src "ls180.v:4053.1250-4053.1494" - cell $not $not$ls180.v:4053$572 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4053$571_Y - connect \Y $not$ls180.v:4053$572_Y - end - attribute \src "ls180.v:4075.32-4075.50" - cell $not $not$ls180.v:4075$578 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_wb_sdram_cyc - connect \Y $not$ls180.v:4075$578_Y - end - attribute \src "ls180.v:4114.30-4114.50" - cell $not $not$ls180.v:4114$583 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_converter_skip - connect \Y $not$ls180.v:4114$583_Y - end - attribute \src "ls180.v:4115.30-4115.50" - cell $not $not$ls180.v:4115$584 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_converter_skip - connect \Y $not$ls180.v:4115$584_Y - end - attribute \src "ls180.v:4140.27-4140.48" - cell $not $not$ls180.v:4140$590 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_cyc - connect \Y $not$ls180.v:4140$590_Y - end - attribute \src "ls180.v:4141.30-4141.50" - cell $not $not$ls180.v:4141$591 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_we - connect \Y $not$ls180.v:4141$591_Y - end - attribute \src "ls180.v:4142.80-4142.98" - cell $not $not$ls180.v:4142$593 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_cmd_consumed - connect \Y $not$ls180.v:4142$593_Y - end - attribute \src "ls180.v:4143.107-4143.127" - cell $not $not$ls180.v:4143$597 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_wdata_consumed - connect \Y $not$ls180.v:4143$597_Y - end - attribute \src "ls180.v:4144.78-4144.103" - cell $not $not$ls180.v:4144$600 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_payload_we - connect \Y $not$ls180.v:4144$600_Y - end - attribute \src "ls180.v:4145.91-4145.111" - cell $not $not$ls180.v:4145$603 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_we - connect \Y $not$ls180.v:4145$603_Y - end - attribute \src "ls180.v:4161.35-4161.64" - cell $not $not$ls180.v:4161$612 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_sink_ready - connect \Y $not$ls180.v:4161$612_Y - end - attribute \src "ls180.v:4162.36-4162.67" - cell $not $not$ls180.v:4162$613 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_source_valid - connect \Y $not$ls180.v:4162$613_Y - end - attribute \src "ls180.v:4168.32-4168.61" - cell $not $not$ls180.v:4168$614 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_sink_ready - connect \Y $not$ls180.v:4168$614_Y - end - attribute \src "ls180.v:4174.36-4174.67" - cell $not $not$ls180.v:4174$615 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_source_valid - connect \Y $not$ls180.v:4174$615_Y - end - attribute \src "ls180.v:4175.35-4175.64" - cell $not $not$ls180.v:4175$616 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_sink_ready - connect \Y $not$ls180.v:4175$616_Y - end - attribute \src "ls180.v:4178.32-4178.63" - cell $not $not$ls180.v:4178$619 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_source_valid - connect \Y $not$ls180.v:4178$619_Y - end - attribute \src "ls180.v:4216.81-4216.108" - cell $not $not$ls180.v:4216$629 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_readable - connect \Y $not$ls180.v:4216$629_Y - end - attribute \src "ls180.v:4246.81-4246.108" - cell $not $not$ls180.v:4246$640 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_readable - connect \Y $not$ls180.v:4246$640_Y - end - attribute \src "ls180.v:4457.60-4457.85" - cell $not $not$ls180.v:4457$691 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_clocker_clk_d - connect \Y $not$ls180.v:4457$691_Y - end - attribute \src "ls180.v:4598.54-4598.96" - cell $not $not$ls180.v:4598$705 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_converter_strobe_all - connect \Y $not$ls180.v:4598$705_Y - end - attribute \src "ls180.v:4601.48-4601.86" - cell $not $not$ls180.v:4601$708 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_buf_source_valid - connect \Y $not$ls180.v:4601$708_Y - end - attribute \src "ls180.v:4725.55-4725.98" - cell $not $not$ls180.v:4725$726 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_converter_strobe_all - connect \Y $not$ls180.v:4725$726_Y - end - attribute \src "ls180.v:4728.49-4728.88" - cell $not $not$ls180.v:4728$729 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_buf_source_valid - connect \Y $not$ls180.v:4728$729_Y - end - attribute \src "ls180.v:4778.30-4778.58" - cell $not $not$ls180.v:4778$735 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_sink_valid - connect \Y $not$ls180.v:4778$735_Y - end - attribute \src "ls180.v:4859.56-4859.100" - cell $not $not$ls180.v:4859$741 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_strobe_all - connect \Y $not$ls180.v:4859$741_Y - end - attribute \src "ls180.v:4862.50-4862.90" - cell $not $not$ls180.v:4862$744 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_buf_source_valid - connect \Y $not$ls180.v:4862$744_Y - end - attribute \src "ls180.v:4978.42-4978.74" - cell $not $not$ls180.v:4978$760 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_valid - connect \Y $not$ls180.v:4978$760_Y - end - attribute \src "ls180.v:5502.50-5502.88" - cell $not $not$ls180.v:5502$1045 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_converter_strobe_all - connect \Y $not$ls180.v:5502$1045_Y - end - attribute \src "ls180.v:5514.52-5514.102" - cell $not $not$ls180.v:5514$1048 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_wishbonedmawriter_enable_storage - connect \Y $not$ls180.v:5514$1048_Y - end - attribute \src "ls180.v:5573.38-5573.74" - cell $not $not$ls180.v:5573$1055 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_dma_enable_storage - connect \Y $not$ls180.v:5573$1055_Y - end - attribute \src "ls180.v:5836.69-5836.88" - cell $not $not$ls180.v:5836$1119 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_shared_ack - connect \Y $not$ls180.v:5836$1119_Y - end - attribute \src "ls180.v:5853.63-5853.94" - cell $not $not$ls180.v:5853$1143 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5853$1143_Y - end - attribute \src "ls180.v:5856.65-5856.96" - cell $not $not$ls180.v:5856$1150 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5856$1150_Y - end - attribute \src "ls180.v:5859.65-5859.96" - cell $not $not$ls180.v:5859$1157 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5859$1157_Y - end - attribute \src "ls180.v:5862.65-5862.96" - cell $not $not$ls180.v:5862$1164 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5862$1164_Y - end - attribute \src "ls180.v:5865.65-5865.96" - cell $not $not$ls180.v:5865$1171 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5865$1171_Y - end - attribute \src "ls180.v:5868.68-5868.99" - cell $not $not$ls180.v:5868$1178 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5868$1178_Y - end - attribute \src "ls180.v:5871.68-5871.99" - cell $not $not$ls180.v:5871$1185 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5871$1185_Y - end - attribute \src "ls180.v:5874.68-5874.99" - cell $not $not$ls180.v:5874$1192 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5874$1192_Y - end - attribute \src "ls180.v:5877.68-5877.99" - cell $not $not$ls180.v:5877$1199 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface0_bank_bus_we - connect \Y $not$ls180.v:5877$1199_Y - end - attribute \src "ls180.v:5891.60-5891.91" - cell $not $not$ls180.v:5891$1207 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5891$1207_Y - end - attribute \src "ls180.v:5894.60-5894.91" - cell $not $not$ls180.v:5894$1214 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5894$1214_Y - end - attribute \src "ls180.v:5897.60-5897.91" - cell $not $not$ls180.v:5897$1221 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5897$1221_Y - end - attribute \src "ls180.v:5900.60-5900.91" - cell $not $not$ls180.v:5900$1228 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5900$1228_Y - end - attribute \src "ls180.v:5903.61-5903.92" - cell $not $not$ls180.v:5903$1235 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5903$1235_Y - end - attribute \src "ls180.v:5906.61-5906.92" - cell $not $not$ls180.v:5906$1242 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface1_bank_bus_we - connect \Y $not$ls180.v:5906$1242_Y - end - attribute \src "ls180.v:5917.59-5917.90" - cell $not $not$ls180.v:5917$1250 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_we - connect \Y $not$ls180.v:5917$1250_Y - end - attribute \src "ls180.v:5920.58-5920.89" - cell $not $not$ls180.v:5920$1257 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface2_bank_bus_we - connect \Y $not$ls180.v:5920$1257_Y - end - attribute \src "ls180.v:5931.64-5931.95" - cell $not $not$ls180.v:5931$1265 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5931$1265_Y - end - attribute \src "ls180.v:5934.63-5934.94" - cell $not $not$ls180.v:5934$1272 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5934$1272_Y - end - attribute \src "ls180.v:5937.63-5937.94" - cell $not $not$ls180.v:5937$1279 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5937$1279_Y - end - attribute \src "ls180.v:5940.63-5940.94" - cell $not $not$ls180.v:5940$1286 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5940$1286_Y - end - attribute \src "ls180.v:5943.63-5943.94" - cell $not $not$ls180.v:5943$1293 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5943$1293_Y - end - attribute \src "ls180.v:5946.64-5946.95" - cell $not $not$ls180.v:5946$1300 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5946$1300_Y - end - attribute \src "ls180.v:5949.64-5949.95" - cell $not $not$ls180.v:5949$1307 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5949$1307_Y - end - attribute \src "ls180.v:5952.64-5952.95" - cell $not $not$ls180.v:5952$1314 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5952$1314_Y - end - attribute \src "ls180.v:5955.64-5955.95" - cell $not $not$ls180.v:5955$1321 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface3_bank_bus_we - connect \Y $not$ls180.v:5955$1321_Y - end - attribute \src "ls180.v:5968.64-5968.95" - cell $not $not$ls180.v:5968$1329 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5968$1329_Y - end - attribute \src "ls180.v:5971.63-5971.94" - cell $not $not$ls180.v:5971$1336 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5971$1336_Y - end - attribute \src "ls180.v:5974.63-5974.94" - cell $not $not$ls180.v:5974$1343 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5974$1343_Y - end - attribute \src "ls180.v:5977.63-5977.94" - cell $not $not$ls180.v:5977$1350 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5977$1350_Y - end - attribute \src "ls180.v:5980.63-5980.94" - cell $not $not$ls180.v:5980$1357 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5980$1357_Y - end - attribute \src "ls180.v:5983.64-5983.95" - cell $not $not$ls180.v:5983$1364 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5983$1364_Y - end - attribute \src "ls180.v:5986.64-5986.95" - cell $not $not$ls180.v:5986$1371 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5986$1371_Y - end - attribute \src "ls180.v:5989.64-5989.95" - cell $not $not$ls180.v:5989$1378 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5989$1378_Y - end - attribute \src "ls180.v:5992.64-5992.95" - cell $not $not$ls180.v:5992$1385 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface4_bank_bus_we - connect \Y $not$ls180.v:5992$1385_Y - end - attribute \src "ls180.v:6005.66-6005.97" - cell $not $not$ls180.v:6005$1393 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6005$1393_Y - end - attribute \src "ls180.v:6008.66-6008.97" - cell $not $not$ls180.v:6008$1400 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6008$1400_Y - end - attribute \src "ls180.v:6011.66-6011.97" - cell $not $not$ls180.v:6011$1407 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6011$1407_Y - end - attribute \src "ls180.v:6014.66-6014.97" - cell $not $not$ls180.v:6014$1414 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6014$1414_Y - end - attribute \src "ls180.v:6017.66-6017.97" - cell $not $not$ls180.v:6017$1421 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6017$1421_Y - end - attribute \src "ls180.v:6020.66-6020.97" - cell $not $not$ls180.v:6020$1428 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6020$1428_Y - end - attribute \src "ls180.v:6023.66-6023.97" - cell $not $not$ls180.v:6023$1435 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6023$1435_Y - end - attribute \src "ls180.v:6026.66-6026.97" - cell $not $not$ls180.v:6026$1442 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6026$1442_Y - end - attribute \src "ls180.v:6029.68-6029.99" - cell $not $not$ls180.v:6029$1449 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6029$1449_Y - end - attribute \src "ls180.v:6032.68-6032.99" - cell $not $not$ls180.v:6032$1456 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6032$1456_Y - end - attribute \src "ls180.v:6035.68-6035.99" - cell $not $not$ls180.v:6035$1463 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6035$1463_Y - end - attribute \src "ls180.v:6038.68-6038.99" - cell $not $not$ls180.v:6038$1470 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6038$1470_Y - end - attribute \src "ls180.v:6041.68-6041.99" - cell $not $not$ls180.v:6041$1477 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6041$1477_Y - end - attribute \src "ls180.v:6044.65-6044.96" - cell $not $not$ls180.v:6044$1484 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6044$1484_Y - end - attribute \src "ls180.v:6047.66-6047.97" - cell $not $not$ls180.v:6047$1491 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface5_bank_bus_we - connect \Y $not$ls180.v:6047$1491_Y - end - attribute \src "ls180.v:6067.70-6067.101" - cell $not $not$ls180.v:6067$1499 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6067$1499_Y - end - attribute \src "ls180.v:6070.70-6070.101" - cell $not $not$ls180.v:6070$1506 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6070$1506_Y - end - attribute \src "ls180.v:6073.70-6073.101" - cell $not $not$ls180.v:6073$1513 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6073$1513_Y - end - attribute \src "ls180.v:6076.70-6076.101" - cell $not $not$ls180.v:6076$1520 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6076$1520_Y - end - attribute \src "ls180.v:6079.69-6079.100" - cell $not $not$ls180.v:6079$1527 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6079$1527_Y - end - attribute \src "ls180.v:6082.69-6082.100" - cell $not $not$ls180.v:6082$1534 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6082$1534_Y - end - attribute \src "ls180.v:6085.69-6085.100" - cell $not $not$ls180.v:6085$1541 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6085$1541_Y - end - attribute \src "ls180.v:6088.69-6088.100" - cell $not $not$ls180.v:6088$1548 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6088$1548_Y - end - attribute \src "ls180.v:6091.60-6091.91" - cell $not $not$ls180.v:6091$1555 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6091$1555_Y - end - attribute \src "ls180.v:6094.71-6094.102" - cell $not $not$ls180.v:6094$1562 - parameter \A_SIGNED 0 - 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$not $not$ls180.v:6145$1681 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6145$1681_Y - end - attribute \src "ls180.v:6148.70-6148.101" - cell $not $not$ls180.v:6148$1688 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6148$1688_Y - end - attribute \src "ls180.v:6151.70-6151.101" - cell $not $not$ls180.v:6151$1695 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6151$1695_Y - end - attribute \src "ls180.v:6154.69-6154.100" - cell $not $not$ls180.v:6154$1702 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6154$1702_Y - end - attribute \src "ls180.v:6157.69-6157.100" - cell $not $not$ls180.v:6157$1709 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6157$1709_Y - end - attribute \src "ls180.v:6160.69-6160.100" - cell $not $not$ls180.v:6160$1716 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6160$1716_Y - end - attribute \src "ls180.v:6163.69-6163.100" - cell $not $not$ls180.v:6163$1723 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface6_bank_bus_we - connect \Y $not$ls180.v:6163$1723_Y - end - attribute \src "ls180.v:6202.66-6202.97" - cell $not $not$ls180.v:6202$1731 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6202$1731_Y - end - attribute \src "ls180.v:6205.66-6205.97" - cell $not $not$ls180.v:6205$1738 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter 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\builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6217$1766_Y - end - attribute \src "ls180.v:6220.66-6220.97" - cell $not $not$ls180.v:6220$1773 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6220$1773_Y - end - attribute \src "ls180.v:6223.66-6223.97" - cell $not $not$ls180.v:6223$1780 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6223$1780_Y - end - attribute \src "ls180.v:6226.68-6226.99" - cell $not $not$ls180.v:6226$1787 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6226$1787_Y - end - attribute \src "ls180.v:6229.68-6229.99" - cell $not $not$ls180.v:6229$1794 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_we - connect \Y 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$not$ls180.v:6256$1857 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface7_bank_bus_we - connect \Y $not$ls180.v:6256$1857_Y - end - attribute \src "ls180.v:6281.68-6281.99" - cell $not $not$ls180.v:6281$1865 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6281$1865_Y - end - attribute \src "ls180.v:6284.73-6284.104" - cell $not $not$ls180.v:6284$1872 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6284$1872_Y - end - attribute \src "ls180.v:6287.73-6287.104" - cell $not $not$ls180.v:6287$1879 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6287$1879_Y - end - attribute \src "ls180.v:6290.66-6290.97" - cell $not $not$ls180.v:6290$1886 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface8_bank_bus_we - connect \Y $not$ls180.v:6290$1886_Y - end - attribute \src "ls180.v:6298.70-6298.101" - cell $not $not$ls180.v:6298$1894 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6298$1894_Y - end - attribute \src "ls180.v:6301.74-6301.105" - cell $not $not$ls180.v:6301$1901 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6301$1901_Y - end - attribute \src "ls180.v:6304.64-6304.95" - cell $not $not$ls180.v:6304$1908 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface9_bank_bus_we - connect \Y $not$ls180.v:6304$1908_Y - end - attribute \src "ls180.v:6307.74-6307.105" - cell $not $not$ls180.v:6307$1915 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - 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attribute \src "ls180.v:6349.65-6349.97" - cell $not $not$ls180.v:6349$1979 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6349$1979_Y - end - attribute \src "ls180.v:6352.64-6352.96" - cell $not $not$ls180.v:6352$1986 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6352$1986_Y - end - attribute \src "ls180.v:6355.63-6355.95" - cell $not $not$ls180.v:6355$1993 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6355$1993_Y - end - attribute \src "ls180.v:6358.62-6358.94" - cell $not $not$ls180.v:6358$2000 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6358$2000_Y - end - attribute \src "ls180.v:6361.68-6361.100" - cell $not $not$ls180.v:6361$2007 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface10_bank_bus_we - connect \Y $not$ls180.v:6361$2007_Y - end - attribute \src "ls180.v:6383.67-6383.99" - cell $not $not$ls180.v:6383$2016 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6383$2016_Y - end - attribute \src "ls180.v:6386.67-6386.99" - cell $not $not$ls180.v:6386$2023 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6386$2023_Y - end - attribute \src "ls180.v:6389.65-6389.97" - cell $not $not$ls180.v:6389$2030 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6389$2030_Y - end - attribute \src "ls180.v:6392.64-6392.96" - cell $not $not$ls180.v:6392$2037 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6392$2037_Y - end - attribute \src "ls180.v:6395.63-6395.95" - cell $not $not$ls180.v:6395$2044 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6395$2044_Y - end - attribute \src "ls180.v:6398.62-6398.94" - cell $not $not$ls180.v:6398$2051 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6398$2051_Y - end - attribute \src "ls180.v:6401.68-6401.100" - cell $not $not$ls180.v:6401$2058 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6401$2058_Y - end - attribute \src "ls180.v:6404.71-6404.103" - cell $not $not$ls180.v:6404$2065 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6404$2065_Y - end - attribute \src "ls180.v:6407.71-6407.103" - cell $not $not$ls180.v:6407$2072 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface11_bank_bus_we - connect \Y $not$ls180.v:6407$2072_Y - end - attribute \src "ls180.v:6431.64-6431.96" - cell $not $not$ls180.v:6431$2081 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6431$2081_Y - end - attribute \src "ls180.v:6434.64-6434.96" - cell $not $not$ls180.v:6434$2088 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6434$2088_Y - end - attribute \src "ls180.v:6437.64-6437.96" - cell $not $not$ls180.v:6437$2095 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6437$2095_Y - end - attribute \src "ls180.v:6440.64-6440.96" - cell $not $not$ls180.v:6440$2102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6440$2102_Y - end - attribute \src "ls180.v:6443.66-6443.98" - cell $not $not$ls180.v:6443$2109 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6443$2109_Y - end - attribute \src "ls180.v:6446.66-6446.98" - cell $not $not$ls180.v:6446$2116 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6446$2116_Y - end - attribute \src "ls180.v:6449.66-6449.98" - cell $not $not$ls180.v:6449$2123 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6449$2123_Y - end - attribute \src "ls180.v:6452.66-6452.98" - cell $not $not$ls180.v:6452$2130 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6452$2130_Y - end - attribute \src "ls180.v:6455.62-6455.94" - cell $not $not$ls180.v:6455$2137 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6455$2137_Y - end - attribute \src "ls180.v:6458.72-6458.104" - cell $not $not$ls180.v:6458$2144 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6458$2144_Y - end - attribute \src "ls180.v:6461.65-6461.97" - cell $not $not$ls180.v:6461$2151 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6461$2151_Y - end - attribute \src "ls180.v:6464.65-6464.97" - cell $not $not$ls180.v:6464$2158 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6464$2158_Y - end - attribute \src "ls180.v:6467.65-6467.97" - cell $not $not$ls180.v:6467$2165 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6467$2165_Y - end - attribute \src "ls180.v:6470.65-6470.97" - cell $not $not$ls180.v:6470$2172 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6470$2172_Y - end - attribute \src "ls180.v:6473.77-6473.109" - cell $not $not$ls180.v:6473$2179 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6473$2179_Y - end - attribute \src "ls180.v:6476.78-6476.110" - cell $not $not$ls180.v:6476$2186 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6476$2186_Y - end - attribute \src "ls180.v:6479.69-6479.101" - cell $not $not$ls180.v:6479$2193 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface12_bank_bus_we - connect \Y $not$ls180.v:6479$2193_Y - end - attribute \src "ls180.v:6499.55-6499.87" - cell $not $not$ls180.v:6499$2201 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6499$2201_Y - end - attribute \src "ls180.v:6502.65-6502.97" - cell $not $not$ls180.v:6502$2208 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6502$2208_Y - end - attribute \src "ls180.v:6505.66-6505.98" - cell $not $not$ls180.v:6505$2215 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6505$2215_Y - end - attribute \src "ls180.v:6508.70-6508.102" - cell $not $not$ls180.v:6508$2222 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6508$2222_Y - end - attribute \src "ls180.v:6511.71-6511.103" - cell $not $not$ls180.v:6511$2229 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6511$2229_Y - end - attribute \src "ls180.v:6514.69-6514.101" - cell $not $not$ls180.v:6514$2236 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6514$2236_Y - end - attribute \src "ls180.v:6517.66-6517.98" - cell $not $not$ls180.v:6517$2243 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6517$2243_Y - end - attribute \src "ls180.v:6520.65-6520.97" - cell $not $not$ls180.v:6520$2250 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface13_bank_bus_we - connect \Y $not$ls180.v:6520$2250_Y - end - attribute \src "ls180.v:6533.71-6533.103" - cell $not $not$ls180.v:6533$2258 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_we - connect \Y $not$ls180.v:6533$2258_Y - end - attribute \src "ls180.v:6536.71-6536.103" - cell $not $not$ls180.v:6536$2265 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_we - connect \Y $not$ls180.v:6536$2265_Y - end - attribute \src "ls180.v:6539.71-6539.103" - cell $not $not$ls180.v:6539$2272 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_we - connect \Y $not$ls180.v:6539$2272_Y - end - attribute \src "ls180.v:6542.71-6542.103" - cell $not $not$ls180.v:6542$2279 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_interface14_bank_bus_we - connect \Y $not$ls180.v:6542$2279_Y - end - attribute \src "ls180.v:6923.86-6923.330" - cell $not $not$ls180.v:6923$2328 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6923$2327_Y - connect \Y $not$ls180.v:6923$2328_Y - end - attribute \src "ls180.v:6947.86-6947.330" - cell $not $not$ls180.v:6947$2344 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6947$2343_Y - connect \Y $not$ls180.v:6947$2344_Y - end - attribute \src "ls180.v:6971.86-6971.330" - cell $not $not$ls180.v:6971$2360 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6971$2359_Y - connect \Y $not$ls180.v:6971$2360_Y - end - attribute \src "ls180.v:6995.86-6995.330" - cell $not $not$ls180.v:6995$2376 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6995$2375_Y - connect \Y $not$ls180.v:6995$2376_Y - end - attribute \src "ls180.v:7496.18-7496.42" - cell $not $not$ls180.v:7496$2432 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_clocker_clk0 - connect \Y $not$ls180.v:7496$2432_Y - end - attribute \src "ls180.v:7575.72-7575.101" - cell $not $not$ls180.v:7575$2465 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_ack - connect \Y $not$ls180.v:7575$2465_Y - end - attribute \src "ls180.v:7594.8-7594.38" - cell $not $not$ls180.v:7594$2469 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_zero_trigger - connect \Y $not$ls180.v:7594$2469_Y - end - attribute \src "ls180.v:7598.64-7598.89" - cell $not $not$ls180.v:7598$2472 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_ram_bus_ram_bus_ack - connect \Y $not$ls180.v:7598$2472_Y - end - attribute \src "ls180.v:7606.32-7606.55" - cell $not $not$ls180.v:7606$2474 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_timer_done0 - connect \Y $not$ls180.v:7606$2474_Y - end - attribute \src "ls180.v:7676.136-7676.189" - cell $not $not$ls180.v:7676$2489 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7676$2489_Y - end - attribute \src "ls180.v:7682.136-7682.189" - cell $not $not$ls180.v:7682$2494 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7682$2494_Y - end - attribute \src "ls180.v:7683.8-7683.61" - cell $not $not$ls180.v:7683$2496 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7683$2496_Y - end - attribute \src "ls180.v:7691.8-7691.56" - cell $not $not$ls180.v:7691$2499 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $not$ls180.v:7691$2499_Y - end - attribute \src "ls180.v:7706.8-7706.46" - cell $not $not$ls180.v:7706$2501 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_twtpcon_ready - connect \Y $not$ls180.v:7706$2501_Y - end - attribute \src "ls180.v:7722.136-7722.189" - cell $not $not$ls180.v:7722$2505 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7722$2505_Y - end - attribute \src "ls180.v:7728.136-7728.189" - cell $not $not$ls180.v:7728$2510 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7728$2510_Y - end - attribute \src "ls180.v:7729.8-7729.61" - cell $not $not$ls180.v:7729$2512 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7729$2512_Y - end - attribute \src "ls180.v:7737.8-7737.56" - cell $not $not$ls180.v:7737$2515 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $not$ls180.v:7737$2515_Y - end - attribute \src "ls180.v:7752.8-7752.46" - cell $not $not$ls180.v:7752$2517 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_twtpcon_ready - connect \Y $not$ls180.v:7752$2517_Y - end - attribute \src "ls180.v:7768.136-7768.189" - cell $not $not$ls180.v:7768$2521 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7768$2521_Y - end - attribute \src "ls180.v:7774.136-7774.189" - cell $not $not$ls180.v:7774$2526 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7774$2526_Y - end - attribute \src "ls180.v:7775.8-7775.61" - cell $not $not$ls180.v:7775$2528 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7775$2528_Y - end - attribute \src "ls180.v:7783.8-7783.56" - cell $not $not$ls180.v:7783$2531 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $not$ls180.v:7783$2531_Y - end - attribute \src "ls180.v:7798.8-7798.46" - cell $not $not$ls180.v:7798$2533 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_twtpcon_ready - connect \Y $not$ls180.v:7798$2533_Y - end - attribute \src "ls180.v:7814.136-7814.189" - cell $not $not$ls180.v:7814$2537 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7814$2537_Y - end - attribute \src "ls180.v:7820.136-7820.189" - cell $not $not$ls180.v:7820$2542 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $not$ls180.v:7820$2542_Y - end - attribute \src "ls180.v:7821.8-7821.61" - cell $not $not$ls180.v:7821$2544 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - connect \Y $not$ls180.v:7821$2544_Y - end - attribute \src "ls180.v:7829.8-7829.56" - cell $not $not$ls180.v:7829$2547 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $not$ls180.v:7829$2547_Y - end - attribute \src "ls180.v:7844.8-7844.46" - cell $not $not$ls180.v:7844$2549 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_twtpcon_ready - connect \Y $not$ls180.v:7844$2549_Y - end - attribute \src "ls180.v:7852.7-7852.22" - cell $not $not$ls180.v:7852$2552 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_en0 - connect \Y $not$ls180.v:7852$2552_Y - end - attribute \src "ls180.v:7855.8-7855.29" - cell $not $not$ls180.v:7855$2553 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_max_time0 - connect \Y $not$ls180.v:7855$2553_Y - end - attribute \src "ls180.v:7859.7-7859.22" - cell $not $not$ls180.v:7859$2555 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_en1 - connect \Y $not$ls180.v:7859$2555_Y - end - attribute \src "ls180.v:7862.8-7862.29" - cell $not $not$ls180.v:7862$2556 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_max_time1 - connect \Y $not$ls180.v:7862$2556_Y - end - attribute \src "ls180.v:7981.30-7981.60" - cell $not $not$ls180.v:7981$2558 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_sync_rhs_array_muxed2 - connect \Y $not$ls180.v:7981$2558_Y - end - attribute \src "ls180.v:7982.30-7982.60" - cell $not $not$ls180.v:7982$2559 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_sync_rhs_array_muxed3 - connect \Y $not$ls180.v:7982$2559_Y - end - attribute \src "ls180.v:7983.29-7983.59" - cell $not $not$ls180.v:7983$2560 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_sync_rhs_array_muxed4 - connect \Y $not$ls180.v:7983$2560_Y - end - attribute \src "ls180.v:7994.8-7994.33" - cell $not $not$ls180.v:7994$2561 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_tccdcon_ready - connect \Y $not$ls180.v:7994$2561_Y - end - attribute \src "ls180.v:8009.8-8009.33" - cell $not $not$ls180.v:8009$2564 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_twtrcon_ready - connect \Y $not$ls180.v:8009$2564_Y - end - attribute \src "ls180.v:8045.36-8045.58" - cell $not $not$ls180.v:8045$2594 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_tx_busy - connect \Y $not$ls180.v:8045$2594_Y - end - attribute \src "ls180.v:8045.64-8045.89" - cell $not $not$ls180.v:8045$2596 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_sink_ready - connect \Y $not$ls180.v:8045$2596_Y - end - attribute \src "ls180.v:8074.7-8074.29" - cell $not $not$ls180.v:8074$2603 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_rx_busy - connect \Y $not$ls180.v:8074$2603_Y - end - attribute \src "ls180.v:8075.9-8075.26" - cell $not $not$ls180.v:8075$2604 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_phy_rx - connect \Y $not$ls180.v:8075$2604_Y - end - attribute \src "ls180.v:8108.8-8108.29" - cell $not $not$ls180.v:8108$2610 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_trigger - connect \Y $not$ls180.v:8108$2610_Y - end - attribute \src "ls180.v:8115.8-8115.29" - cell $not $not$ls180.v:8115$2612 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_trigger - connect \Y $not$ls180.v:8115$2612_Y - end - attribute \src "ls180.v:8125.80-8125.106" - cell $not $not$ls180.v:8125$2615 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_replace - connect \Y $not$ls180.v:8125$2615_Y - end - attribute \src "ls180.v:8131.80-8131.106" - cell $not $not$ls180.v:8131$2620 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_replace - connect \Y $not$ls180.v:8131$2620_Y - end - attribute \src "ls180.v:8132.8-8132.34" - cell $not $not$ls180.v:8132$2622 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_do_read - connect \Y $not$ls180.v:8132$2622_Y - end - attribute \src "ls180.v:8147.80-8147.106" - cell $not $not$ls180.v:8147$2626 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_replace - connect \Y $not$ls180.v:8147$2626_Y - end - attribute \src "ls180.v:8153.80-8153.106" - cell $not $not$ls180.v:8153$2631 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_replace - connect \Y $not$ls180.v:8153$2631_Y - end - attribute \src "ls180.v:8154.8-8154.34" - cell $not $not$ls180.v:8154$2633 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_do_read - connect \Y $not$ls180.v:8154$2633_Y - end - attribute \src "ls180.v:8185.22-8185.41" - cell $not $not$ls180.v:8185$2637 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_spimaster6_cs - connect \Y $not$ls180.v:8185$2637_Y - end - attribute \src "ls180.v:8185.46-8185.73" - cell $not $not$ls180.v:8185$2638 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_spimaster26_cs_enable - connect \Y $not$ls180.v:8185$2638_Y - end - attribute \src "ls180.v:8220.22-8220.40" - cell $not $not$ls180.v:8220$2642 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_spisdcard_cs - connect \Y $not$ls180.v:8220$2642_Y - end - attribute \src "ls180.v:8220.45-8220.70" - cell $not $not$ls180.v:8220$2643 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_spisdcard_cs_enable - connect \Y $not$ls180.v:8220$2643_Y - end - attribute \src "ls180.v:8274.7-8274.31" - cell $not $not$ls180.v:8274$2654 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_clocker_stop - connect \Y $not$ls180.v:8274$2654_Y - end - attribute \src "ls180.v:8346.8-8346.46" - cell $not $not$ls180.v:8346$2666 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_buf_source_valid - connect \Y $not$ls180.v:8346$2666_Y - end - attribute \src "ls180.v:8427.8-8427.47" - cell $not $not$ls180.v:8427$2678 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_buf_source_valid - connect \Y $not$ls180.v:8427$2678_Y - end - attribute \src "ls180.v:8488.8-8488.48" - cell $not $not$ls180.v:8488$2690 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_buf_source_valid - connect \Y $not$ls180.v:8488$2690_Y - end - attribute \src "ls180.v:8658.88-8658.118" - cell $not $not$ls180.v:8658$2704 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_replace - connect \Y $not$ls180.v:8658$2704_Y - end - attribute \src "ls180.v:8664.88-8664.118" - cell $not $not$ls180.v:8664$2709 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_replace - connect \Y $not$ls180.v:8664$2709_Y - end - attribute \src "ls180.v:8665.8-8665.38" - cell $not $not$ls180.v:8665$2711 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_do_read - connect \Y $not$ls180.v:8665$2711_Y - end - attribute \src "ls180.v:8756.88-8756.118" - cell $not $not$ls180.v:8756$2726 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_replace - connect \Y $not$ls180.v:8756$2726_Y - end - attribute \src "ls180.v:8762.88-8762.118" - cell $not $not$ls180.v:8762$2731 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_replace - connect \Y $not$ls180.v:8762$2731_Y - end - attribute \src "ls180.v:8763.8-8763.38" - cell $not $not$ls180.v:8763$2733 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_do_read - connect \Y $not$ls180.v:8763$2733_Y - end - attribute \src "ls180.v:8783.9-8783.28" - cell $not $not$ls180.v:8783$2736 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_request [0] - connect \Y $not$ls180.v:8783$2736_Y - end - attribute \src "ls180.v:8802.9-8802.28" - cell $not $not$ls180.v:8802$2737 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_request [1] - connect \Y $not$ls180.v:8802$2737_Y - end - attribute \src "ls180.v:8821.9-8821.28" - cell $not $not$ls180.v:8821$2738 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_request [2] - connect \Y $not$ls180.v:8821$2738_Y - end - attribute \src "ls180.v:8840.9-8840.28" - cell $not $not$ls180.v:8840$2739 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_request [3] - connect \Y $not$ls180.v:8840$2739_Y - end - attribute \src "ls180.v:8859.9-8859.28" - cell $not $not$ls180.v:8859$2740 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_request [4] - connect \Y $not$ls180.v:8859$2740_Y - end - attribute \src "ls180.v:8880.8-8880.21" - cell $not $not$ls180.v:8880$2741 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_done - connect \Y $not$ls180.v:8880$2741_Y - end - attribute \src "ls180.v:10416.8-10416.51" - cell $or $or$ls180.v:10416$2851 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sys_rst_1 - connect \B \main_libresocsim_libresoc_reset - connect \Y $or$ls180.v:10416$2851_Y - end - attribute \src "ls180.v:2845.10-2845.71" - cell $or $or$ls180.v:2845$33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_xics_icp_ack - connect \B \main_converter0_skip - connect \Y $or$ls180.v:2845$33_Y - end - attribute \src "ls180.v:2905.10-2905.71" - cell $or $or$ls180.v:2905$44 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_xics_ics_ack - connect \B \main_converter1_skip - connect \Y $or$ls180.v:2905$44_Y - end - attribute \src "ls180.v:2965.10-2965.53" - cell $or $or$ls180.v:2965$55 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_wb_sdram_ack - connect \B \main_socbushandler_skip - connect \Y $or$ls180.v:2965$55_Y - end - attribute \src "ls180.v:3175.39-3175.105" - cell $or $or$ls180.v:3175$124 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_start0 - connect \B $ne$ls180.v:3175$123_Y - connect \Y $or$ls180.v:3175$124_Y - end - attribute \src "ls180.v:3218.59-3218.140" - cell $or $or$ls180.v:3218$128 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_req_wdata_ready - connect \B \main_sdram_bankmachine0_req_rdata_valid - connect \Y $or$ls180.v:3218$128_Y - end - attribute \src "ls180.v:3219.44-3219.151" - cell $or $or$ls180.v:3219$129 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid - connect \Y $or$ls180.v:3219$129_Y - end - attribute \src "ls180.v:3227.45-3227.170" - cell $or $or$ls180.v:3227$133 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3227$132_Y - connect \B { 4'0000 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3227$133_Y - end - attribute \src "ls180.v:3264.127-3264.245" - cell $or $or$ls180.v:3264$146 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3264$146_Y - end - attribute \src "ls180.v:3270.57-3270.157" - cell $or $or$ls180.v:3270$152 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3270$151_Y - connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready - connect \Y $or$ls180.v:3270$152_Y - end - attribute \src "ls180.v:3375.59-3375.140" - cell $or $or$ls180.v:3375$158 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_req_wdata_ready - connect \B \main_sdram_bankmachine1_req_rdata_valid - connect \Y $or$ls180.v:3375$158_Y - end - attribute \src "ls180.v:3376.44-3376.151" - cell $or $or$ls180.v:3376$159 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid - connect \Y $or$ls180.v:3376$159_Y - end - attribute \src "ls180.v:3384.45-3384.170" - cell $or $or$ls180.v:3384$163 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3384$162_Y - connect \B { 4'0000 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3384$163_Y - end - attribute \src "ls180.v:3421.127-3421.245" - cell $or $or$ls180.v:3421$176 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3421$176_Y - end - attribute \src "ls180.v:3427.57-3427.157" - cell $or $or$ls180.v:3427$182 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3427$181_Y - connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready - connect \Y $or$ls180.v:3427$182_Y - end - attribute \src "ls180.v:3532.59-3532.140" - cell $or $or$ls180.v:3532$188 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_req_wdata_ready - connect \B \main_sdram_bankmachine2_req_rdata_valid - connect \Y $or$ls180.v:3532$188_Y - end - attribute \src "ls180.v:3533.44-3533.151" - cell $or $or$ls180.v:3533$189 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid - connect \Y $or$ls180.v:3533$189_Y - end - attribute \src "ls180.v:3541.45-3541.170" - cell $or $or$ls180.v:3541$193 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3541$192_Y - connect \B { 4'0000 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3541$193_Y - end - attribute \src "ls180.v:3578.127-3578.245" - cell $or $or$ls180.v:3578$206 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3578$206_Y - end - attribute \src "ls180.v:3584.57-3584.157" - cell $or $or$ls180.v:3584$212 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3584$211_Y - connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready - connect \Y $or$ls180.v:3584$212_Y - end - attribute \src "ls180.v:3689.59-3689.140" - cell $or $or$ls180.v:3689$218 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_req_wdata_ready - connect \B \main_sdram_bankmachine3_req_rdata_valid - connect \Y $or$ls180.v:3689$218_Y - end - attribute \src "ls180.v:3690.44-3690.151" - cell $or $or$ls180.v:3690$219 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid - connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid - connect \Y $or$ls180.v:3690$219_Y - end - attribute \src "ls180.v:3698.45-3698.170" - cell $or $or$ls180.v:3698$223 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 13 - parameter \Y_WIDTH 13 - connect \A $sshl$ls180.v:3698$222_Y - connect \B { 4'0000 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [8:0] } - connect \Y $or$ls180.v:3698$223_Y - end - attribute \src "ls180.v:3735.127-3735.245" - cell $or $or$ls180.v:3735$236 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - connect \Y $or$ls180.v:3735$236_Y - end - attribute \src "ls180.v:3741.57-3741.157" - cell $or $or$ls180.v:3741$242 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3741$241_Y - connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready - connect \Y $or$ls180.v:3741$242_Y - end - attribute \src "ls180.v:3840.107-3840.193" - cell $or $or$ls180.v:3840$262 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_payload_is_write - connect \B \main_sdram_choose_req_cmd_payload_is_read - connect \Y $or$ls180.v:3840$262_Y - end - attribute \src "ls180.v:3843.39-3843.204" - cell $or $or$ls180.v:3843$268 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3843$266_Y - connect \B $and$ls180.v:3843$267_Y - connect \Y $or$ls180.v:3843$268_Y - end - attribute \src "ls180.v:3843.38-3843.289" - cell $or $or$ls180.v:3843$270 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3843$268_Y - connect \B $and$ls180.v:3843$269_Y - connect \Y $or$ls180.v:3843$270_Y - end - attribute \src "ls180.v:3843.37-3843.374" - cell $or $or$ls180.v:3843$272 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3843$270_Y - connect \B $and$ls180.v:3843$271_Y - connect \Y $or$ls180.v:3843$272_Y - end - attribute \src "ls180.v:3844.40-3844.207" - cell $or $or$ls180.v:3844$275 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3844$273_Y - connect \B $and$ls180.v:3844$274_Y - connect \Y $or$ls180.v:3844$275_Y - end - attribute \src "ls180.v:3844.39-3844.293" - cell $or $or$ls180.v:3844$277 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3844$275_Y - connect \B $and$ls180.v:3844$276_Y - connect \Y $or$ls180.v:3844$277_Y - end - attribute \src "ls180.v:3844.38-3844.379" - cell $or $or$ls180.v:3844$279 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:3844$277_Y - connect \B $and$ls180.v:3844$278_Y - connect \Y $or$ls180.v:3844$279_Y - end - attribute \src "ls180.v:3857.158-3857.332" - cell $or $or$ls180.v:3857$293 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3857$292_Y - connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3857$293_Y - end - attribute \src "ls180.v:3857.75-3857.506" - cell $or $or$ls180.v:3857$298 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3857$294_Y - connect \B $and$ls180.v:3857$297_Y - connect \Y $or$ls180.v:3857$298_Y - end - attribute \src "ls180.v:3858.158-3858.332" - cell $or $or$ls180.v:3858$306 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3858$305_Y - connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3858$306_Y - end - attribute \src "ls180.v:3858.75-3858.506" - cell $or $or$ls180.v:3858$311 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3858$307_Y - connect \B $and$ls180.v:3858$310_Y - connect \Y $or$ls180.v:3858$311_Y - end - attribute \src "ls180.v:3859.158-3859.332" - cell $or $or$ls180.v:3859$319 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3859$318_Y - connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3859$319_Y - end - attribute \src "ls180.v:3859.75-3859.506" - cell $or $or$ls180.v:3859$324 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3859$320_Y - connect \B $and$ls180.v:3859$323_Y - connect \Y $or$ls180.v:3859$324_Y - end - attribute \src "ls180.v:3860.158-3860.332" - cell $or $or$ls180.v:3860$332 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3860$331_Y - connect \B \main_sdram_choose_cmd_want_activates - connect \Y $or$ls180.v:3860$332_Y - end - attribute \src "ls180.v:3860.75-3860.506" - cell $or $or$ls180.v:3860$337 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3860$333_Y - connect \B $and$ls180.v:3860$336_Y - connect \Y $or$ls180.v:3860$337_Y - end - attribute \src "ls180.v:3887.36-3887.104" - cell $or $or$ls180.v:3887$343 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_cmd_cmd_ready - connect \B $not$ls180.v:3887$342_Y - connect \Y $or$ls180.v:3887$343_Y - end - attribute \src "ls180.v:3890.158-3890.332" - cell $or $or$ls180.v:3890$351 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3890$350_Y - connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:3890$351_Y - end - attribute \src "ls180.v:3890.75-3890.506" - cell $or $or$ls180.v:3890$356 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3890$352_Y - connect \B $and$ls180.v:3890$355_Y - connect \Y $or$ls180.v:3890$356_Y - end - attribute \src "ls180.v:3891.158-3891.332" - cell $or $or$ls180.v:3891$364 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3891$363_Y - connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:3891$364_Y - end - attribute \src "ls180.v:3891.75-3891.506" - cell $or $or$ls180.v:3891$369 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3891$365_Y - connect \B $and$ls180.v:3891$368_Y - connect \Y $or$ls180.v:3891$369_Y - end - attribute \src "ls180.v:3892.158-3892.332" - cell $or $or$ls180.v:3892$377 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3892$376_Y - connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:3892$377_Y - end - attribute \src "ls180.v:3892.75-3892.506" - cell $or $or$ls180.v:3892$382 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3892$378_Y - connect \B $and$ls180.v:3892$381_Y - connect \Y $or$ls180.v:3892$382_Y - end - attribute \src "ls180.v:3893.158-3893.332" - cell $or $or$ls180.v:3893$390 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3893$389_Y - connect \B \main_sdram_choose_req_want_activates - connect \Y $or$ls180.v:3893$390_Y - end - attribute \src "ls180.v:3893.75-3893.506" - cell $or $or$ls180.v:3893$395 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:3893$391_Y - connect \B $and$ls180.v:3893$394_Y - connect \Y $or$ls180.v:3893$395_Y - end - attribute \src "ls180.v:3956.36-3956.104" - cell $or $or$ls180.v:3956$429 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_choose_req_cmd_ready - connect \B $not$ls180.v:3956$428_Y - connect \Y $or$ls180.v:3956$429_Y - end - attribute \src "ls180.v:3977.67-3977.221" - cell $or $or$ls180.v:3977$436 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3977$435_Y - connect \B \main_sdram_ras_allowed - connect \Y $or$ls180.v:3977$436_Y - end - attribute \src "ls180.v:3985.10-3985.62" - cell $or $or$ls180.v:3985$439 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:3985$438_Y - connect \B \main_sdram_max_time1 - connect \Y $or$ls180.v:3985$439_Y - end - attribute \src "ls180.v:4015.67-4015.221" - cell $or $or$ls180.v:4015$445 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4015$444_Y - connect \B \main_sdram_ras_allowed - connect \Y $or$ls180.v:4015$445_Y - end - attribute \src "ls180.v:4023.10-4023.61" - cell $or $or$ls180.v:4023$448 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4023$447_Y - connect \B \main_sdram_max_time0 - connect \Y $or$ls180.v:4023$448_Y - end - attribute \src "ls180.v:4033.91-4033.180" - cell $or $or$ls180.v:4033$452 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked0 - connect \B $and$ls180.v:4033$451_Y - connect \Y $or$ls180.v:4033$452_Y - end - attribute \src "ls180.v:4033.90-4033.255" - cell $or $or$ls180.v:4033$455 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4033$452_Y - connect \B $and$ls180.v:4033$454_Y - connect \Y $or$ls180.v:4033$455_Y - end - attribute \src "ls180.v:4033.89-4033.330" - cell $or $or$ls180.v:4033$458 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4033$455_Y - connect \B $and$ls180.v:4033$457_Y - connect \Y $or$ls180.v:4033$458_Y - end - attribute \src "ls180.v:4038.91-4038.180" - cell $or $or$ls180.v:4038$468 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked1 - connect \B $and$ls180.v:4038$467_Y - connect \Y $or$ls180.v:4038$468_Y - end - attribute \src "ls180.v:4038.90-4038.255" - cell $or $or$ls180.v:4038$471 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4038$468_Y - connect \B $and$ls180.v:4038$470_Y - connect \Y $or$ls180.v:4038$471_Y - end - attribute \src "ls180.v:4038.89-4038.330" - cell $or $or$ls180.v:4038$474 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4038$471_Y - connect \B $and$ls180.v:4038$473_Y - connect \Y $or$ls180.v:4038$474_Y - end - attribute \src "ls180.v:4043.91-4043.180" - cell $or $or$ls180.v:4043$484 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked2 - connect \B $and$ls180.v:4043$483_Y - connect \Y $or$ls180.v:4043$484_Y - end - attribute \src "ls180.v:4043.90-4043.255" - cell $or $or$ls180.v:4043$487 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4043$484_Y - connect \B $and$ls180.v:4043$486_Y - connect \Y $or$ls180.v:4043$487_Y - end - attribute \src "ls180.v:4043.89-4043.330" - cell $or $or$ls180.v:4043$490 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4043$487_Y - connect \B $and$ls180.v:4043$489_Y - connect \Y $or$ls180.v:4043$490_Y - end - attribute \src "ls180.v:4048.91-4048.180" - cell $or $or$ls180.v:4048$500 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked3 - connect \B $and$ls180.v:4048$499_Y - connect \Y $or$ls180.v:4048$500_Y - end - attribute \src "ls180.v:4048.90-4048.255" - cell $or $or$ls180.v:4048$503 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4048$500_Y - connect \B $and$ls180.v:4048$502_Y - connect \Y $or$ls180.v:4048$503_Y - end - attribute \src "ls180.v:4048.89-4048.330" - cell $or $or$ls180.v:4048$506 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4048$503_Y - connect \B $and$ls180.v:4048$505_Y - connect \Y $or$ls180.v:4048$506_Y - end - attribute \src "ls180.v:4053.132-4053.221" - cell $or $or$ls180.v:4053$517 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked0 - connect \B $and$ls180.v:4053$516_Y - connect \Y $or$ls180.v:4053$517_Y - end - attribute \src "ls180.v:4053.131-4053.296" - cell $or $or$ls180.v:4053$520 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4053$517_Y - connect \B $and$ls180.v:4053$519_Y - connect \Y $or$ls180.v:4053$520_Y - end - attribute \src "ls180.v:4053.130-4053.371" - cell $or $or$ls180.v:4053$523 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4053$520_Y - connect \B $and$ls180.v:4053$522_Y - connect \Y $or$ls180.v:4053$523_Y - end - attribute \src "ls180.v:4053.34-4053.411" - cell $or $or$ls180.v:4053$528 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A 1'0 - connect \B $and$ls180.v:4053$527_Y - connect \Y $or$ls180.v:4053$528_Y - end - attribute \src "ls180.v:4053.506-4053.595" - cell $or $or$ls180.v:4053$533 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked1 - connect \B $and$ls180.v:4053$532_Y - connect \Y $or$ls180.v:4053$533_Y - end - attribute \src "ls180.v:4053.505-4053.670" - cell $or $or$ls180.v:4053$536 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4053$533_Y - connect \B $and$ls180.v:4053$535_Y - connect \Y $or$ls180.v:4053$536_Y - end - attribute \src "ls180.v:4053.504-4053.745" - cell $or $or$ls180.v:4053$539 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4053$536_Y - connect \B $and$ls180.v:4053$538_Y - connect \Y $or$ls180.v:4053$539_Y - end - attribute \src "ls180.v:4053.33-4053.785" - cell $or $or$ls180.v:4053$544 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4053$528_Y - connect \B $and$ls180.v:4053$543_Y - connect \Y $or$ls180.v:4053$544_Y - end - attribute \src "ls180.v:4053.880-4053.969" - cell $or $or$ls180.v:4053$549 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked2 - connect \B $and$ls180.v:4053$548_Y - connect \Y $or$ls180.v:4053$549_Y - end - attribute \src "ls180.v:4053.879-4053.1044" - cell $or $or$ls180.v:4053$552 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4053$549_Y - connect \B $and$ls180.v:4053$551_Y - connect \Y $or$ls180.v:4053$552_Y - end - attribute \src "ls180.v:4053.878-4053.1119" - cell $or $or$ls180.v:4053$555 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4053$552_Y - connect \B $and$ls180.v:4053$554_Y - connect \Y $or$ls180.v:4053$555_Y - end - attribute \src "ls180.v:4053.32-4053.1159" - cell $or $or$ls180.v:4053$560 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4053$544_Y - connect \B $and$ls180.v:4053$559_Y - connect \Y $or$ls180.v:4053$560_Y - end - attribute \src "ls180.v:4053.1254-4053.1343" - cell $or $or$ls180.v:4053$565 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked3 - connect \B $and$ls180.v:4053$564_Y - connect \Y $or$ls180.v:4053$565_Y - end - attribute \src "ls180.v:4053.1253-4053.1418" - cell $or $or$ls180.v:4053$568 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4053$565_Y - connect \B $and$ls180.v:4053$567_Y - connect \Y $or$ls180.v:4053$568_Y - end - attribute \src "ls180.v:4053.1252-4053.1493" - cell $or $or$ls180.v:4053$571 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4053$568_Y - connect \B $and$ls180.v:4053$570_Y - connect \Y $or$ls180.v:4053$571_Y - end - attribute \src "ls180.v:4053.31-4053.1533" - cell $or $or$ls180.v:4053$576 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4053$560_Y - connect \B $and$ls180.v:4053$575_Y - connect \Y $or$ls180.v:4053$576_Y - end - attribute \src "ls180.v:4116.10-4116.52" - cell $or $or$ls180.v:4116$585 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_ack - connect \B \main_converter_skip - connect \Y $or$ls180.v:4116$585_Y - end - attribute \src "ls180.v:4143.35-4143.74" - cell $or $or$ls180.v:4143$595 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_valid - connect \B \main_cmd_consumed - connect \Y $or$ls180.v:4143$595_Y - end - attribute \src "ls180.v:4144.34-4144.73" - cell $or $or$ls180.v:4144$599 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_port_cmd_valid - connect \B \main_cmd_consumed - connect \Y $or$ls180.v:4144$599_Y - end - attribute \src "ls180.v:4145.48-4145.130" - cell $or $or$ls180.v:4145$605 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4145$602_Y - connect \B $and$ls180.v:4145$604_Y - connect \Y $or$ls180.v:4145$605_Y - end - attribute \src "ls180.v:4146.24-4146.87" - cell $or $or$ls180.v:4146$608 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4146$607_Y - connect \B \main_cmd_consumed - connect \Y $or$ls180.v:4146$608_Y - end - attribute \src "ls180.v:4147.26-4147.95" - cell $or $or$ls180.v:4147$610 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4147$609_Y - connect \B \main_wdata_consumed - connect \Y $or$ls180.v:4147$610_Y - end - attribute \src "ls180.v:4177.42-4177.89" - cell $or $or$ls180.v:4177$618 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_clear - connect \B $and$ls180.v:4177$617_Y - connect \Y $or$ls180.v:4177$618_Y - end - attribute \src "ls180.v:4201.25-4201.174" - cell $or $or$ls180.v:4201$628 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $and$ls180.v:4201$626_Y - connect \B $and$ls180.v:4201$627_Y - connect \Y $or$ls180.v:4201$628_Y - end - attribute \src "ls180.v:4216.80-4216.132" - cell $or $or$ls180.v:4216$630 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4216$629_Y - connect \B \main_uart_tx_fifo_re - connect \Y $or$ls180.v:4216$630_Y - end - attribute \src "ls180.v:4227.72-4227.135" - cell $or $or$ls180.v:4227$635 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_tx_fifo_syncfifo_writable - connect \B \main_uart_tx_fifo_replace - connect \Y $or$ls180.v:4227$635_Y - end - attribute \src "ls180.v:4246.80-4246.132" - cell $or $or$ls180.v:4246$641 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4246$640_Y - connect \B \main_uart_rx_fifo_re - connect \Y $or$ls180.v:4246$641_Y - end - attribute \src "ls180.v:4257.72-4257.135" - cell $or $or$ls180.v:4257$646 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_uart_rx_fifo_syncfifo_writable - connect \B \main_uart_rx_fifo_replace - connect \Y $or$ls180.v:4257$646_Y - end - attribute \src "ls180.v:4402.36-4402.111" - cell $or $or$ls180.v:4402$669 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_init_pads_out_payload_clk - connect \B \main_sdphy_cmdw_pads_out_payload_clk - connect \Y $or$ls180.v:4402$669_Y - end - attribute \src "ls180.v:4402.35-4402.151" - cell $or $or$ls180.v:4402$670 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4402$669_Y - connect \B \main_sdphy_cmdr_pads_out_payload_clk - connect \Y $or$ls180.v:4402$670_Y - end - attribute \src "ls180.v:4402.34-4402.192" - cell $or $or$ls180.v:4402$671 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4402$670_Y - connect \B \main_sdphy_dataw_pads_out_payload_clk - connect \Y $or$ls180.v:4402$671_Y - end - attribute \src "ls180.v:4402.33-4402.233" - cell $or $or$ls180.v:4402$672 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4402$671_Y - connect \B \main_sdphy_datar_pads_out_payload_clk - connect \Y $or$ls180.v:4402$672_Y - end - attribute \src "ls180.v:4403.39-4403.120" - cell $or $or$ls180.v:4403$673 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_init_pads_out_payload_cmd_oe - connect \B \main_sdphy_cmdw_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4403$673_Y - end - attribute \src "ls180.v:4403.38-4403.163" - cell $or $or$ls180.v:4403$674 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4403$673_Y - connect \B \main_sdphy_cmdr_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4403$674_Y - end - attribute \src "ls180.v:4403.37-4403.207" - cell $or $or$ls180.v:4403$675 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4403$674_Y - connect \B \main_sdphy_dataw_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4403$675_Y - end - attribute \src "ls180.v:4403.36-4403.251" - cell $or $or$ls180.v:4403$676 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4403$675_Y - connect \B \main_sdphy_datar_pads_out_payload_cmd_oe - connect \Y $or$ls180.v:4403$676_Y - end - attribute \src "ls180.v:4404.38-4404.117" - cell $or $or$ls180.v:4404$677 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_init_pads_out_payload_cmd_o - connect \B \main_sdphy_cmdw_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4404$677_Y - end - attribute \src "ls180.v:4404.37-4404.159" - cell $or $or$ls180.v:4404$678 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4404$677_Y - connect \B \main_sdphy_cmdr_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4404$678_Y - end - attribute \src "ls180.v:4404.36-4404.202" - cell $or $or$ls180.v:4404$679 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4404$678_Y - connect \B \main_sdphy_dataw_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4404$679_Y - end - attribute \src "ls180.v:4404.35-4404.245" - cell $or $or$ls180.v:4404$680 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4404$679_Y - connect \B \main_sdphy_datar_pads_out_payload_cmd_o - connect \Y $or$ls180.v:4404$680_Y - end - attribute \src "ls180.v:4405.40-4405.123" - cell $or $or$ls180.v:4405$681 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_init_pads_out_payload_data_oe - connect \B \main_sdphy_cmdw_pads_out_payload_data_oe - connect \Y $or$ls180.v:4405$681_Y - end - attribute \src "ls180.v:4405.39-4405.167" - cell $or $or$ls180.v:4405$682 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4405$681_Y - connect \B \main_sdphy_cmdr_pads_out_payload_data_oe - connect \Y $or$ls180.v:4405$682_Y - end - attribute \src "ls180.v:4405.38-4405.212" - cell $or $or$ls180.v:4405$683 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4405$682_Y - connect \B \main_sdphy_dataw_pads_out_payload_data_oe - connect \Y $or$ls180.v:4405$683_Y - end - attribute \src "ls180.v:4405.37-4405.257" - cell $or $or$ls180.v:4405$684 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:4405$683_Y - connect \B \main_sdphy_datar_pads_out_payload_data_oe - connect \Y $or$ls180.v:4405$684_Y - end - attribute \src "ls180.v:4406.39-4406.120" - cell $or $or$ls180.v:4406$685 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \main_sdphy_init_pads_out_payload_data_o - connect \B \main_sdphy_cmdw_pads_out_payload_data_o - connect \Y $or$ls180.v:4406$685_Y - end - attribute \src "ls180.v:4406.38-4406.163" - cell $or $or$ls180.v:4406$686 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $or$ls180.v:4406$685_Y - connect \B \main_sdphy_cmdr_pads_out_payload_data_o - connect \Y $or$ls180.v:4406$686_Y - end - attribute \src "ls180.v:4406.37-4406.207" - cell $or $or$ls180.v:4406$687 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $or$ls180.v:4406$686_Y - connect \B \main_sdphy_dataw_pads_out_payload_data_o - connect \Y $or$ls180.v:4406$687_Y - end - attribute \src "ls180.v:4406.36-4406.251" - cell $or $or$ls180.v:4406$688 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $or$ls180.v:4406$687_Y - connect \B \main_sdphy_datar_pads_out_payload_data_o - connect \Y $or$ls180.v:4406$688_Y - end - attribute \src "ls180.v:4427.35-4427.80" - cell $or $or$ls180.v:4427$689 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_stop - connect \B \main_sdphy_datar_stop - connect \Y $or$ls180.v:4427$689_Y - end - attribute \src "ls180.v:4581.91-4581.144" - cell $or $or$ls180.v:4581$703 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_start - connect \B \main_sdphy_cmdr_cmdr_run - connect \Y $or$ls180.v:4581$703_Y - end - attribute \src "ls180.v:4598.53-4598.143" - cell $or $or$ls180.v:4598$706 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4598$705_Y - connect \B \main_sdphy_cmdr_cmdr_converter_source_ready - connect \Y $or$ls180.v:4598$706_Y - end - attribute \src "ls180.v:4601.47-4601.127" - cell $or $or$ls180.v:4601$709 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4601$708_Y - connect \B \main_sdphy_cmdr_cmdr_buf_source_ready - connect \Y $or$ls180.v:4601$709_Y - end - attribute \src "ls180.v:4725.54-4725.146" - cell $or $or$ls180.v:4725$727 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4725$726_Y - connect \B \main_sdphy_dataw_crcr_converter_source_ready - connect \Y $or$ls180.v:4725$727_Y - end - attribute \src "ls180.v:4728.48-4728.130" - cell $or $or$ls180.v:4728$730 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4728$729_Y - connect \B \main_sdphy_dataw_crcr_buf_source_ready - connect \Y $or$ls180.v:4728$730_Y - end - attribute \src "ls180.v:4859.55-4859.149" - cell $or $or$ls180.v:4859$742 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4859$741_Y - connect \B \main_sdphy_datar_datar_converter_source_ready - connect \Y $or$ls180.v:4859$742_Y - end - attribute \src "ls180.v:4862.49-4862.133" - cell $or $or$ls180.v:4862$745 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:4862$744_Y - connect \B \main_sdphy_datar_datar_buf_source_ready - connect \Y $or$ls180.v:4862$745_Y - end - attribute \src "ls180.v:5491.80-5491.151" - cell $or $or$ls180.v:5491$1040 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_fifo_syncfifo_writable - connect \B \main_sdblock2mem_fifo_replace - connect \Y $or$ls180.v:5491$1040_Y - end - attribute \src "ls180.v:5502.49-5502.131" - cell $or $or$ls180.v:5502$1046 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:5502$1045_Y - connect \B \main_sdblock2mem_converter_source_ready - connect \Y $or$ls180.v:5502$1046_Y - end - attribute \src "ls180.v:5711.80-5711.151" - cell $or $or$ls180.v:5711$1071 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdmem2block_fifo_syncfifo_writable - connect \B \main_sdmem2block_fifo_replace - connect \Y $or$ls180.v:5711$1071_Y - end - attribute \src "ls180.v:5835.34-5835.89" - cell $or $or$ls180.v:5835$1113 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_err - connect \B \main_ram_bus_ram_bus_err - connect \Y $or$ls180.v:5835$1113_Y - end - attribute \src "ls180.v:5835.33-5835.132" - cell $or $or$ls180.v:5835$1114 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5835$1113_Y - connect \B \main_interface0_converted_interface_err - connect \Y $or$ls180.v:5835$1114_Y - end - attribute \src "ls180.v:5835.32-5835.175" - cell $or $or$ls180.v:5835$1115 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5835$1114_Y - connect \B \main_interface1_converted_interface_err - connect \Y $or$ls180.v:5835$1115_Y - end - attribute \src "ls180.v:5835.31-5835.221" - cell $or $or$ls180.v:5835$1116 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5835$1115_Y - connect \B \main_socbushandler_converted_interface_err - connect \Y $or$ls180.v:5835$1116_Y - end - attribute \src "ls180.v:5835.30-5835.268" - cell $or $or$ls180.v:5835$1117 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5835$1116_Y - connect \B \builder_libresocsim_converted_interface_err - connect \Y $or$ls180.v:5835$1117_Y - end - attribute \src "ls180.v:5841.29-5841.84" - cell $or $or$ls180.v:5841$1122 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_ram_bus_ack - connect \B \main_ram_bus_ram_bus_ack - connect \Y $or$ls180.v:5841$1122_Y - end - attribute \src "ls180.v:5841.28-5841.127" - cell $or $or$ls180.v:5841$1123 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5841$1122_Y - connect \B \main_interface0_converted_interface_ack - connect \Y $or$ls180.v:5841$1123_Y - end - attribute \src "ls180.v:5841.27-5841.170" - cell $or $or$ls180.v:5841$1124 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5841$1123_Y - connect \B \main_interface1_converted_interface_ack - connect \Y $or$ls180.v:5841$1124_Y - end - attribute \src "ls180.v:5841.26-5841.216" - cell $or $or$ls180.v:5841$1125 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5841$1124_Y - connect \B \main_socbushandler_converted_interface_ack - connect \Y $or$ls180.v:5841$1125_Y - end - attribute \src "ls180.v:5841.25-5841.263" - cell $or $or$ls180.v:5841$1126 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:5841$1125_Y - connect \B \builder_libresocsim_converted_interface_ack - connect \Y $or$ls180.v:5841$1126_Y - end - attribute \src "ls180.v:5842.31-5842.156" - cell $or $or$ls180.v:5842$1129 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $and$ls180.v:5842$1127_Y - connect \B $and$ls180.v:5842$1128_Y - connect \Y $or$ls180.v:5842$1129_Y - end - attribute \src "ls180.v:5842.30-5842.234" - cell $or $or$ls180.v:5842$1131 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $or$ls180.v:5842$1129_Y - connect \B $and$ls180.v:5842$1130_Y - connect \Y $or$ls180.v:5842$1131_Y - end - attribute \src "ls180.v:5842.29-5842.312" - cell $or $or$ls180.v:5842$1133 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $or$ls180.v:5842$1131_Y - connect \B $and$ls180.v:5842$1132_Y - connect \Y $or$ls180.v:5842$1133_Y - end - attribute \src "ls180.v:5842.28-5842.393" - cell $or $or$ls180.v:5842$1135 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $or$ls180.v:5842$1133_Y - connect \B $and$ls180.v:5842$1134_Y - connect \Y $or$ls180.v:5842$1135_Y - end - attribute \src "ls180.v:5842.27-5842.475" - cell $or $or$ls180.v:5842$1137 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $or$ls180.v:5842$1135_Y - connect \B $and$ls180.v:5842$1136_Y - connect \Y $or$ls180.v:5842$1137_Y - end - attribute \src "ls180.v:6596.55-6596.124" - cell $or $or$ls180.v:6596$2283 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A \builder_interface0_bank_bus_dat_r - connect \B \builder_interface1_bank_bus_dat_r - connect \Y $or$ls180.v:6596$2283_Y - end - attribute \src "ls180.v:6596.54-6596.161" - cell $or $or$ls180.v:6596$2284 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6596$2283_Y - connect \B \builder_interface2_bank_bus_dat_r - connect \Y $or$ls180.v:6596$2284_Y - end - attribute \src "ls180.v:6596.53-6596.198" - cell $or $or$ls180.v:6596$2285 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6596$2284_Y - connect \B \builder_interface3_bank_bus_dat_r - connect \Y $or$ls180.v:6596$2285_Y - end - attribute \src "ls180.v:6596.52-6596.235" - cell $or $or$ls180.v:6596$2286 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6596$2285_Y - connect \B \builder_interface4_bank_bus_dat_r - connect \Y $or$ls180.v:6596$2286_Y - end - attribute \src "ls180.v:6596.51-6596.272" - cell $or $or$ls180.v:6596$2287 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6596$2286_Y - connect \B \builder_interface5_bank_bus_dat_r - connect \Y $or$ls180.v:6596$2287_Y - end - attribute \src "ls180.v:6596.50-6596.309" - cell $or $or$ls180.v:6596$2288 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6596$2287_Y - connect \B \builder_interface6_bank_bus_dat_r - connect \Y $or$ls180.v:6596$2288_Y - end - attribute \src "ls180.v:6596.49-6596.346" - cell $or $or$ls180.v:6596$2289 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6596$2288_Y - connect \B \builder_interface7_bank_bus_dat_r - connect \Y $or$ls180.v:6596$2289_Y - end - attribute \src "ls180.v:6596.48-6596.383" - cell $or $or$ls180.v:6596$2290 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6596$2289_Y - connect \B \builder_interface8_bank_bus_dat_r - connect \Y $or$ls180.v:6596$2290_Y - end - attribute \src "ls180.v:6596.47-6596.420" - cell $or $or$ls180.v:6596$2291 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6596$2290_Y - connect \B \builder_interface9_bank_bus_dat_r - connect \Y $or$ls180.v:6596$2291_Y - end - attribute \src "ls180.v:6596.46-6596.458" - cell $or $or$ls180.v:6596$2292 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6596$2291_Y - connect \B \builder_interface10_bank_bus_dat_r - connect \Y $or$ls180.v:6596$2292_Y - end - attribute \src "ls180.v:6596.45-6596.496" - cell $or $or$ls180.v:6596$2293 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6596$2292_Y - connect \B \builder_interface11_bank_bus_dat_r - connect \Y $or$ls180.v:6596$2293_Y - end - attribute \src "ls180.v:6596.44-6596.534" - cell $or $or$ls180.v:6596$2294 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6596$2293_Y - connect \B \builder_interface12_bank_bus_dat_r - connect \Y $or$ls180.v:6596$2294_Y - end - attribute \src "ls180.v:6596.43-6596.572" - cell $or $or$ls180.v:6596$2295 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6596$2294_Y - connect \B \builder_interface13_bank_bus_dat_r - connect \Y $or$ls180.v:6596$2295_Y - end - attribute \src "ls180.v:6596.42-6596.610" - cell $or $or$ls180.v:6596$2296 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A $or$ls180.v:6596$2295_Y - connect \B \builder_interface14_bank_bus_dat_r - connect \Y $or$ls180.v:6596$2296_Y - end - attribute \src "ls180.v:6923.90-6923.179" - cell $or $or$ls180.v:6923$2321 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked0 - connect \B $and$ls180.v:6923$2320_Y - connect \Y $or$ls180.v:6923$2321_Y - end - attribute \src "ls180.v:6923.89-6923.254" - cell $or $or$ls180.v:6923$2324 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6923$2321_Y - connect \B $and$ls180.v:6923$2323_Y - connect \Y $or$ls180.v:6923$2324_Y - end - attribute \src "ls180.v:6923.88-6923.329" - cell $or $or$ls180.v:6923$2327 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6923$2324_Y - connect \B $and$ls180.v:6923$2326_Y - connect \Y $or$ls180.v:6923$2327_Y - end - attribute \src "ls180.v:6947.90-6947.179" - cell $or $or$ls180.v:6947$2337 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked1 - connect \B $and$ls180.v:6947$2336_Y - connect \Y $or$ls180.v:6947$2337_Y - end - attribute \src "ls180.v:6947.89-6947.254" - cell $or $or$ls180.v:6947$2340 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6947$2337_Y - connect \B $and$ls180.v:6947$2339_Y - connect \Y $or$ls180.v:6947$2340_Y - end - attribute \src "ls180.v:6947.88-6947.329" - cell $or $or$ls180.v:6947$2343 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6947$2340_Y - connect \B $and$ls180.v:6947$2342_Y - connect \Y $or$ls180.v:6947$2343_Y - end - attribute \src "ls180.v:6971.90-6971.179" - cell $or $or$ls180.v:6971$2353 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked2 - connect \B $and$ls180.v:6971$2352_Y - connect \Y $or$ls180.v:6971$2353_Y - end - attribute \src "ls180.v:6971.89-6971.254" - cell $or $or$ls180.v:6971$2356 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6971$2353_Y - connect \B $and$ls180.v:6971$2355_Y - connect \Y $or$ls180.v:6971$2356_Y - end - attribute \src "ls180.v:6971.88-6971.329" - cell $or $or$ls180.v:6971$2359 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6971$2356_Y - connect \B $and$ls180.v:6971$2358_Y - connect \Y $or$ls180.v:6971$2359_Y - end - attribute \src "ls180.v:6995.90-6995.179" - cell $or $or$ls180.v:6995$2369 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \builder_locked3 - connect \B $and$ls180.v:6995$2368_Y - connect \Y $or$ls180.v:6995$2369_Y - end - attribute \src "ls180.v:6995.89-6995.254" - cell $or $or$ls180.v:6995$2372 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6995$2369_Y - connect \B $and$ls180.v:6995$2371_Y - connect \Y $or$ls180.v:6995$2372_Y - end - attribute \src "ls180.v:6995.88-6995.329" - cell $or $or$ls180.v:6995$2375 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:6995$2372_Y - connect \B $and$ls180.v:6995$2374_Y - connect \Y $or$ls180.v:6995$2375_Y - end - attribute \src "ls180.v:7512.20-7512.71" - cell $or $or$ls180.v:7512$2435 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [0] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7512$2435_Y - end - attribute \src "ls180.v:7513.20-7513.71" - cell $or $or$ls180.v:7513$2436 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [1] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7513$2436_Y - end - attribute \src "ls180.v:7514.20-7514.71" - cell $or $or$ls180.v:7514$2437 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [2] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7514$2437_Y - end - attribute \src "ls180.v:7515.20-7515.71" - cell $or $or$ls180.v:7515$2438 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [3] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7515$2438_Y - end - attribute \src "ls180.v:7516.20-7516.71" - cell $or $or$ls180.v:7516$2439 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [4] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7516$2439_Y - end - attribute \src "ls180.v:7517.20-7517.71" - cell $or $or$ls180.v:7517$2440 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [5] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7517$2440_Y - end - attribute \src "ls180.v:7518.20-7518.71" - cell $or $or$ls180.v:7518$2441 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [6] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7518$2441_Y - end - attribute \src "ls180.v:7519.20-7519.71" - cell $or $or$ls180.v:7519$2442 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [7] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7519$2442_Y - end - attribute \src "ls180.v:7520.20-7520.71" - cell $or $or$ls180.v:7520$2443 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [8] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7520$2443_Y - end - attribute \src "ls180.v:7521.20-7521.71" - cell $or $or$ls180.v:7521$2444 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [9] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7521$2444_Y - end - attribute \src "ls180.v:7522.21-7522.73" - cell $or $or$ls180.v:7522$2445 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [10] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7522$2445_Y - end - attribute \src "ls180.v:7523.21-7523.73" - cell $or $or$ls180.v:7523$2446 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [11] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7523$2446_Y - end - attribute \src "ls180.v:7524.21-7524.73" - cell $or $or$ls180.v:7524$2447 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [12] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7524$2447_Y - end - attribute \src "ls180.v:7525.21-7525.73" - cell $or $or$ls180.v:7525$2448 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [13] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7525$2448_Y - end - attribute \src "ls180.v:7526.21-7526.73" - cell $or $or$ls180.v:7526$2449 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [14] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7526$2449_Y - end - attribute \src "ls180.v:7527.21-7527.73" - cell $or $or$ls180.v:7527$2450 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [15] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7527$2450_Y - end - attribute \src "ls180.v:7528.21-7528.73" - cell $or $or$ls180.v:7528$2451 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [16] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7528$2451_Y - end - attribute \src "ls180.v:7529.21-7529.73" - cell $or $or$ls180.v:7529$2452 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [17] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7529$2452_Y - end - attribute \src "ls180.v:7530.21-7530.73" - cell $or $or$ls180.v:7530$2453 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [18] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7530$2453_Y - end - attribute \src "ls180.v:7531.21-7531.73" - cell $or $or$ls180.v:7531$2454 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [19] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7531$2454_Y - end - attribute \src "ls180.v:7532.21-7532.73" - cell $or $or$ls180.v:7532$2455 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [20] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7532$2455_Y - end - attribute \src "ls180.v:7533.21-7533.73" - cell $or $or$ls180.v:7533$2456 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [21] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7533$2456_Y - end - attribute \src "ls180.v:7534.21-7534.73" - cell $or $or$ls180.v:7534$2457 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [22] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7534$2457_Y - end - attribute \src "ls180.v:7535.21-7535.73" - cell $or $or$ls180.v:7535$2458 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_nc [23] - connect \B \main_libresocsim_libresoc_interrupt [0] - connect \Y $or$ls180.v:7535$2458_Y - end - attribute \src "ls180.v:7536.7-7536.68" - cell $or $or$ls180.v:7536$2459 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_xics_icp_ack - connect \B \main_converter0_skip - connect \Y $or$ls180.v:7536$2459_Y - end - attribute \src "ls180.v:7547.7-7547.68" - cell $or $or$ls180.v:7547$2460 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_libresocsim_libresoc_xics_ics_ack - connect \B \main_converter1_skip - connect \Y $or$ls180.v:7547$2460_Y - end - attribute \src "ls180.v:7558.7-7558.50" - cell $or $or$ls180.v:7558$2461 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_wb_sdram_ack - connect \B \main_socbushandler_skip - connect \Y $or$ls180.v:7558$2461_Y - end - attribute \src "ls180.v:7691.7-7691.107" - cell $or $or$ls180.v:7691$2500 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7691$2499_Y - connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready - connect \Y $or$ls180.v:7691$2500_Y - end - attribute \src "ls180.v:7737.7-7737.107" - cell $or $or$ls180.v:7737$2516 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7737$2515_Y - connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready - connect \Y $or$ls180.v:7737$2516_Y - end - attribute \src "ls180.v:7783.7-7783.107" - cell $or $or$ls180.v:7783$2532 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7783$2531_Y - connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready - connect \Y $or$ls180.v:7783$2532_Y - end - attribute \src "ls180.v:7829.7-7829.107" - cell $or $or$ls180.v:7829$2548 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:7829$2547_Y - connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready - connect \Y $or$ls180.v:7829$2548_Y - end - attribute \src "ls180.v:8017.40-8017.125" - cell $or $or$ls180.v:8017$2569 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A 1'0 - connect \B $and$ls180.v:8017$2568_Y - connect \Y $or$ls180.v:8017$2569_Y - end - attribute \src "ls180.v:8017.39-8017.207" - cell $or $or$ls180.v:8017$2572 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8017$2569_Y - connect \B $and$ls180.v:8017$2571_Y - connect \Y $or$ls180.v:8017$2572_Y - end - attribute \src "ls180.v:8017.38-8017.289" - cell $or $or$ls180.v:8017$2575 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8017$2572_Y - connect \B $and$ls180.v:8017$2574_Y - connect \Y $or$ls180.v:8017$2575_Y - end - attribute \src "ls180.v:8017.37-8017.371" - cell $or $or$ls180.v:8017$2578 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8017$2575_Y - connect \B $and$ls180.v:8017$2577_Y - connect \Y $or$ls180.v:8017$2578_Y - end - attribute \src "ls180.v:8018.41-8018.126" - cell $or $or$ls180.v:8018$2581 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A 1'0 - connect \B $and$ls180.v:8018$2580_Y - connect \Y $or$ls180.v:8018$2581_Y - end - attribute \src "ls180.v:8018.40-8018.208" - cell $or $or$ls180.v:8018$2584 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8018$2581_Y - connect \B $and$ls180.v:8018$2583_Y - connect \Y $or$ls180.v:8018$2584_Y - end - attribute \src "ls180.v:8018.39-8018.290" - cell $or $or$ls180.v:8018$2587 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8018$2584_Y - connect \B $and$ls180.v:8018$2586_Y - connect \Y $or$ls180.v:8018$2587_Y - end - attribute \src "ls180.v:8018.38-8018.372" - cell $or $or$ls180.v:8018$2590 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $or$ls180.v:8018$2587_Y - connect \B $and$ls180.v:8018$2589_Y - connect \Y $or$ls180.v:8018$2590_Y - end - attribute \src "ls180.v:8022.7-8022.49" - cell $or $or$ls180.v:8022$2591 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_litedram_wb_ack - connect \B \main_converter_skip - connect \Y $or$ls180.v:8022$2591_Y - end - attribute \src "ls180.v:8185.21-8185.74" - cell $or $or$ls180.v:8185$2639 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8185$2637_Y - connect \B $not$ls180.v:8185$2638_Y - connect \Y $or$ls180.v:8185$2639_Y - end - attribute \src "ls180.v:8220.21-8220.71" - cell $or $or$ls180.v:8220$2644 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8220$2642_Y - connect \B $not$ls180.v:8220$2643_Y - connect \Y $or$ls180.v:8220$2644_Y - end - attribute \src "ls180.v:8288.32-8288.85" - cell $or $or$ls180.v:8288$2656 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_start - connect \B \main_sdphy_cmdr_cmdr_run - connect \Y $or$ls180.v:8288$2656_Y - end - attribute \src "ls180.v:8294.8-8294.97" - cell $or $or$ls180.v:8294$2658 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8294$2657_Y - connect \B \main_sdphy_cmdr_cmdr_converter_sink_last - connect \Y $or$ls180.v:8294$2658_Y - end - attribute \src "ls180.v:8311.52-8311.139" - cell $or $or$ls180.v:8311$2663 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_converter_sink_first - connect \B \main_sdphy_cmdr_cmdr_converter_source_first - connect \Y $or$ls180.v:8311$2663_Y - end - attribute \src "ls180.v:8312.51-8312.136" - cell $or $or$ls180.v:8312$2664 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_cmdr_cmdr_converter_sink_last - connect \B \main_sdphy_cmdr_cmdr_converter_source_last - connect \Y $or$ls180.v:8312$2664_Y - end - attribute \src "ls180.v:8346.7-8346.87" - cell $or $or$ls180.v:8346$2667 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8346$2666_Y - connect \B \main_sdphy_cmdr_cmdr_buf_source_ready - connect \Y $or$ls180.v:8346$2667_Y - end - attribute \src "ls180.v:8369.33-8369.88" - cell $or $or$ls180.v:8369$2668 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_start - connect \B \main_sdphy_dataw_crcr_run - connect \Y $or$ls180.v:8369$2668_Y - end - attribute \src "ls180.v:8375.8-8375.99" - cell $or $or$ls180.v:8375$2670 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8375$2669_Y - connect \B \main_sdphy_dataw_crcr_converter_sink_last - connect \Y $or$ls180.v:8375$2670_Y - end - attribute \src "ls180.v:8392.53-8392.142" - cell $or $or$ls180.v:8392$2675 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_converter_sink_first - connect \B \main_sdphy_dataw_crcr_converter_source_first - connect \Y $or$ls180.v:8392$2675_Y - end - attribute \src "ls180.v:8393.52-8393.139" - cell $or $or$ls180.v:8393$2676 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_dataw_crcr_converter_sink_last - connect \B \main_sdphy_dataw_crcr_converter_source_last - connect \Y $or$ls180.v:8393$2676_Y - end - attribute \src "ls180.v:8427.7-8427.89" - cell $or $or$ls180.v:8427$2679 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8427$2678_Y - connect \B \main_sdphy_dataw_crcr_buf_source_ready - connect \Y $or$ls180.v:8427$2679_Y - end - attribute \src "ls180.v:8448.34-8448.91" - cell $or $or$ls180.v:8448$2680 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_start - connect \B \main_sdphy_datar_datar_run - connect \Y $or$ls180.v:8448$2680_Y - end - attribute \src "ls180.v:8454.8-8454.101" - cell $or $or$ls180.v:8454$2682 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8454$2681_Y - connect \B \main_sdphy_datar_datar_converter_sink_last - connect \Y $or$ls180.v:8454$2682_Y - end - attribute \src "ls180.v:8471.54-8471.145" - cell $or $or$ls180.v:8471$2687 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_sink_first - connect \B \main_sdphy_datar_datar_converter_source_first - connect \Y $or$ls180.v:8471$2687_Y - end - attribute \src "ls180.v:8472.53-8472.142" - cell $or $or$ls180.v:8472$2688 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdphy_datar_datar_converter_sink_last - connect \B \main_sdphy_datar_datar_converter_source_last - connect \Y $or$ls180.v:8472$2688_Y - end - attribute \src "ls180.v:8488.7-8488.91" - cell $or $or$ls180.v:8488$2691 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $not$ls180.v:8488$2690_Y - connect \B \main_sdphy_datar_datar_buf_source_ready - connect \Y $or$ls180.v:8488$2691_Y - end - attribute \src "ls180.v:8677.8-8677.89" - cell $or $or$ls180.v:8677$2715 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $eq$ls180.v:8677$2714_Y - connect \B \main_sdblock2mem_converter_sink_last - connect \Y $or$ls180.v:8677$2715_Y - end - attribute \src "ls180.v:8694.48-8694.127" - cell $or $or$ls180.v:8694$2720 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_converter_sink_first - connect \B \main_sdblock2mem_converter_source_first - connect \Y $or$ls180.v:8694$2720_Y - end - attribute \src "ls180.v:8695.47-8695.124" - cell $or $or$ls180.v:8695$2721 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdblock2mem_converter_sink_last - connect \B \main_sdblock2mem_converter_source_last - connect \Y $or$ls180.v:8695$2721_Y - end - attribute \src "ls180.v:3227.46-3227.94" - cell $sshl $sshl$ls180.v:3227$132 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 13 - connect \A \main_sdram_bankmachine0_auto_precharge - connect \B 4'1010 - connect \Y $sshl$ls180.v:3227$132_Y - end - attribute \src "ls180.v:3384.46-3384.94" - cell $sshl $sshl$ls180.v:3384$162 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 13 - connect \A \main_sdram_bankmachine1_auto_precharge - connect \B 4'1010 - connect \Y $sshl$ls180.v:3384$162_Y - end - attribute \src "ls180.v:3541.46-3541.94" - cell $sshl $sshl$ls180.v:3541$192 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 13 - connect \A \main_sdram_bankmachine2_auto_precharge - connect \B 4'1010 - connect \Y $sshl$ls180.v:3541$192_Y - end - attribute \src "ls180.v:3698.46-3698.94" - cell $sshl $sshl$ls180.v:3698$222 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 13 - connect \A \main_sdram_bankmachine3_auto_precharge - connect \B 4'1010 - connect \Y $sshl$ls180.v:3698$222_Y - end - attribute \src "ls180.v:3258.63-3258.122" - cell $sub $sub$ls180.v:3258$145 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $sub$ls180.v:3258$145_Y - end - attribute \src "ls180.v:3415.63-3415.122" - cell $sub $sub$ls180.v:3415$175 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $sub$ls180.v:3415$175_Y - end - attribute \src "ls180.v:3572.63-3572.122" - cell $sub $sub$ls180.v:3572$205 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $sub$ls180.v:3572$205_Y - end - attribute \src "ls180.v:3729.63-3729.122" - cell $sub $sub$ls180.v:3729$235 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce - connect \B 1'1 - connect \Y $sub$ls180.v:3729$235_Y - end - attribute \src "ls180.v:4135.38-4135.75" - cell $sub $sub$ls180.v:4135$589 - parameter \A_SIGNED 0 - parameter \A_WIDTH 30 - parameter \B_SIGNED 0 - parameter \B_WIDTH 31 - parameter \Y_WIDTH 31 - connect \A \main_litedram_wb_adr - connect \B 31'1001000000000000000000000000000 - connect \Y $sub$ls180.v:4135$589_Y - end - attribute \src "ls180.v:4221.36-4221.68" - cell $sub $sub$ls180.v:4221$634 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_uart_tx_fifo_produce - connect \B 1'1 - connect \Y $sub$ls180.v:4221$634_Y - end - attribute \src "ls180.v:4251.36-4251.68" - cell $sub $sub$ls180.v:4251$645 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_uart_rx_fifo_produce - connect \B 1'1 - connect \Y $sub$ls180.v:4251$645_Y - end - attribute \src "ls180.v:4287.70-4287.110" - cell $sub $sub$ls180.v:4287$653 - parameter \A_SIGNED 0 - parameter \A_WIDTH 15 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 16 - connect \A \main_spimaster8_clk_divider [15:1] - connect \B 1'1 - connect \Y $sub$ls180.v:4287$653_Y - end - attribute \src "ls180.v:4288.70-4288.104" - cell $sub $sub$ls180.v:4288$655 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 16 - connect \A \main_spimaster8_clk_divider - connect \B 1'1 - connect \Y $sub$ls180.v:4288$655_Y - end - attribute \src "ls180.v:4315.37-4315.66" - cell $sub $sub$ls180.v:4315$659 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_spimaster1_length - connect \B 1'1 - connect \Y $sub$ls180.v:4315$659_Y - end - attribute \src "ls180.v:4345.67-4345.107" - cell $sub $sub$ls180.v:4345$661 - parameter \A_SIGNED 0 - parameter \A_WIDTH 15 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 16 - connect \A \main_spisdcard_clk_divider0 [15:1] - connect \B 1'1 - connect \Y $sub$ls180.v:4345$661_Y - end - attribute \src "ls180.v:4346.67-4346.101" - cell $sub $sub$ls180.v:4346$663 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 16 - connect \A \main_spisdcard_clk_divider0 - connect \B 1'1 - connect \Y $sub$ls180.v:4346$663_Y - end - attribute \src "ls180.v:4374.35-4374.64" - cell $sub $sub$ls180.v:4374$667 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_spisdcard_length0 - connect \B 1'1 - connect \Y $sub$ls180.v:4374$667_Y - end - attribute \src "ls180.v:4628.60-4628.90" - cell $sub $sub$ls180.v:4628$711 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdphy_cmdr_timeout - connect \B 1'1 - connect \Y $sub$ls180.v:4628$711_Y - end - attribute \src "ls180.v:4639.62-4639.104" - cell $sub $sub$ls180.v:4639$713 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \main_sdphy_cmdr_sink_payload_length - connect \B 1'1 - connect \Y $sub$ls180.v:4639$713_Y - end - attribute \src "ls180.v:4656.60-4656.90" - cell $sub $sub$ls180.v:4656$717 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdphy_cmdr_timeout - connect \B 1'1 - connect \Y $sub$ls180.v:4656$717_Y - end - attribute \src "ls180.v:4885.62-4885.93" - cell $sub $sub$ls180.v:4885$747 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdphy_datar_timeout - connect \B 1'1 - connect \Y $sub$ls180.v:4885$747_Y - end - attribute \src "ls180.v:4890.62-4890.93" - cell $sub $sub$ls180.v:4890$748 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdphy_datar_timeout - connect \B 1'1 - connect \Y $sub$ls180.v:4890$748_Y - end - attribute \src "ls180.v:4901.64-4901.122" - cell $sub $sub$ls180.v:4901$751 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 10 - connect \A $add$ls180.v:4901$750_Y - connect \B 1'1 - connect \Y $sub$ls180.v:4901$751_Y - end - attribute \src "ls180.v:4922.62-4922.93" - cell $sub $sub$ls180.v:4922$754 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdphy_datar_timeout - connect \B 1'1 - connect \Y $sub$ls180.v:4922$754_Y - end - attribute \src "ls180.v:5384.37-5384.75" - cell $sub $sub$ls180.v:5384$1027 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdcore_block_count_storage - connect \B 1'1 - connect \Y $sub$ls180.v:5384$1027_Y - end - attribute \src "ls180.v:5399.62-5399.100" - cell $sub $sub$ls180.v:5399$1030 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdcore_block_count_storage - connect \B 1'1 - connect \Y $sub$ls180.v:5399$1030_Y - end - attribute \src "ls180.v:5410.39-5410.77" - cell $sub $sub$ls180.v:5410$1035 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdcore_block_count_storage - connect \B 1'1 - connect \Y $sub$ls180.v:5410$1035_Y - end - attribute \src "ls180.v:5485.40-5485.76" - cell $sub $sub$ls180.v:5485$1039 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_sdblock2mem_fifo_produce - connect \B 1'1 - connect \Y $sub$ls180.v:5485$1039_Y - end - attribute \src "ls180.v:5534.56-5534.104" - cell $sub $sub$ls180.v:5534$1053 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdblock2mem_wishbonedmawriter_length - connect \B 1'1 - connect \Y $sub$ls180.v:5534$1053_Y - end - attribute \src "ls180.v:5624.71-5624.105" - cell $sub $sub$ls180.v:5624$1059 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_sdmem2block_dma_length - connect \B 1'1 - connect \Y $sub$ls180.v:5624$1059_Y - end - attribute \src "ls180.v:5705.40-5705.76" - cell $sub $sub$ls180.v:5705$1070 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_sdmem2block_fifo_produce - connect \B 1'1 - connect \Y $sub$ls180.v:5705$1070_Y - end - attribute \src "ls180.v:7582.31-7582.60" - cell $sub $sub$ls180.v:7582$2468 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_libresocsim_value - connect \B 1'1 - connect \Y $sub$ls180.v:7582$2468_Y - end - attribute \src "ls180.v:7607.31-7607.61" - cell $sub $sub$ls180.v:7607$2476 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 10 - connect \A \main_sdram_timer_count1 - connect \B 1'1 - connect \Y $sub$ls180.v:7607$2476_Y - end - attribute \src "ls180.v:7613.34-7613.67" - cell $sub $sub$ls180.v:7613$2477 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_postponer_count - connect \B 1'1 - connect \Y $sub$ls180.v:7613$2477_Y - end - attribute \src "ls180.v:7624.36-7624.69" - cell $sub $sub$ls180.v:7624$2480 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_sequencer_count - connect \B 1'1 - connect \Y $sub$ls180.v:7624$2480_Y - end - attribute \src "ls180.v:7688.59-7688.116" - cell $sub $sub$ls180.v:7688$2498 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level - connect \B 1'1 - connect \Y $sub$ls180.v:7688$2498_Y - end - attribute \src "ls180.v:7707.46-7707.90" - cell $sub $sub$ls180.v:7707$2502 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine0_twtpcon_count - connect \B 1'1 - connect \Y $sub$ls180.v:7707$2502_Y - end - attribute \src "ls180.v:7734.59-7734.116" - cell $sub $sub$ls180.v:7734$2514 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level - connect \B 1'1 - connect \Y $sub$ls180.v:7734$2514_Y - end - attribute \src "ls180.v:7753.46-7753.90" - cell $sub $sub$ls180.v:7753$2518 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine1_twtpcon_count - connect \B 1'1 - connect \Y $sub$ls180.v:7753$2518_Y - end - attribute \src "ls180.v:7780.59-7780.116" - cell $sub $sub$ls180.v:7780$2530 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level - connect \B 1'1 - connect \Y $sub$ls180.v:7780$2530_Y - end - attribute \src "ls180.v:7799.46-7799.90" - cell $sub $sub$ls180.v:7799$2534 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine2_twtpcon_count - connect \B 1'1 - connect \Y $sub$ls180.v:7799$2534_Y - end - attribute \src "ls180.v:7826.59-7826.116" - cell $sub $sub$ls180.v:7826$2546 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level - connect \B 1'1 - connect \Y $sub$ls180.v:7826$2546_Y - end - attribute \src "ls180.v:7845.46-7845.90" - cell $sub $sub$ls180.v:7845$2550 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_bankmachine3_twtpcon_count - connect \B 1'1 - connect \Y $sub$ls180.v:7845$2550_Y - end - attribute \src "ls180.v:7856.25-7856.48" - cell $sub $sub$ls180.v:7856$2554 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_sdram_time0 - connect \B 1'1 - connect \Y $sub$ls180.v:7856$2554_Y - end - attribute \src "ls180.v:7863.25-7863.48" - cell $sub $sub$ls180.v:7863$2557 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \main_sdram_time1 - connect \B 1'1 - connect \Y $sub$ls180.v:7863$2557_Y - end - attribute \src "ls180.v:7995.33-7995.64" - cell $sub $sub$ls180.v:7995$2562 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdram_tccdcon_count - connect \B 1'1 - connect \Y $sub$ls180.v:7995$2562_Y - end - attribute \src "ls180.v:8010.33-8010.64" - cell $sub $sub$ls180.v:8010$2565 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_sdram_twtrcon_count - connect \B 1'1 - connect \Y $sub$ls180.v:8010$2565_Y - end - attribute \src "ls180.v:8137.33-8137.64" - cell $sub $sub$ls180.v:8137$2624 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_uart_tx_fifo_level0 - connect \B 1'1 - connect \Y $sub$ls180.v:8137$2624_Y - end - attribute \src "ls180.v:8159.33-8159.64" - cell $sub $sub$ls180.v:8159$2635 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 5 - connect \A \main_uart_rx_fifo_level0 - connect \B 1'1 - connect \Y $sub$ls180.v:8159$2635_Y - end - attribute \src "ls180.v:8194.34-8194.66" - cell $sub $sub$ls180.v:8194$2640 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_spimaster34_mosi_sel - connect \B 1'1 - connect \Y $sub$ls180.v:8194$2640_Y - end - attribute \src "ls180.v:8229.32-8229.62" - cell $sub $sub$ls180.v:8229$2645 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \main_spisdcard_mosi_sel - connect \B 1'1 - connect \Y $sub$ls180.v:8229$2645_Y - end - attribute \src "ls180.v:8253.30-8253.53" - cell $sub $sub$ls180.v:8253$2648 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_pwm0_period - connect \B 1'1 - connect \Y $sub$ls180.v:8253$2648_Y - end - attribute \src "ls180.v:8267.30-8267.53" - cell $sub $sub$ls180.v:8267$2652 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 32 - connect \A \main_pwm1_period - connect \B 1'1 - connect \Y $sub$ls180.v:8267$2652_Y - end - attribute \src "ls180.v:8670.36-8670.70" - cell $sub $sub$ls180.v:8670$2713 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 6 - connect \A \main_sdblock2mem_fifo_level - connect \B 1'1 - connect \Y $sub$ls180.v:8670$2713_Y - end - attribute \src "ls180.v:8768.36-8768.70" - cell $sub $sub$ls180.v:8768$2735 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 6 - connect \A \main_sdmem2block_fifo_level - connect \B 1'1 - connect \Y $sub$ls180.v:8768$2735_Y - end - attribute \src "ls180.v:8881.22-8881.42" - cell $sub $sub$ls180.v:8881$2742 - parameter \A_SIGNED 0 - parameter \A_WIDTH 20 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 20 - connect \A \builder_count - connect \B 1'1 - connect \Y $sub$ls180.v:8881$2742_Y - end - attribute \src "ls180.v:4982.353-4982.425" - cell $xor $xor$ls180.v:4982$761 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [39] - connect \B \main_sdcore_crc7_inserter_crcreg0 [6] - connect \Y $xor$ls180.v:4982$761_Y - end - attribute \src "ls180.v:4982.200-4982.272" - cell $xor $xor$ls180.v:4982$762 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [39] - connect \B \main_sdcore_crc7_inserter_crcreg0 [6] - connect \Y $xor$ls180.v:4982$762_Y - end - attribute \src "ls180.v:4982.160-4982.273" - cell $xor $xor$ls180.v:4982$763 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg0 [2] - connect \B $xor$ls180.v:4982$762_Y - connect \Y $xor$ls180.v:4982$763_Y - end - attribute \src "ls180.v:4983.353-4983.425" - cell $xor $xor$ls180.v:4983$764 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [38] - connect \B \main_sdcore_crc7_inserter_crcreg1 [6] - connect \Y $xor$ls180.v:4983$764_Y - end - attribute \src "ls180.v:4983.200-4983.272" - cell $xor $xor$ls180.v:4983$765 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [38] - connect \B \main_sdcore_crc7_inserter_crcreg1 [6] - connect \Y $xor$ls180.v:4983$765_Y - end - attribute \src "ls180.v:4983.160-4983.273" - cell $xor $xor$ls180.v:4983$766 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg1 [2] - connect \B $xor$ls180.v:4983$765_Y - connect \Y $xor$ls180.v:4983$766_Y - end - attribute \src "ls180.v:4984.353-4984.425" - cell $xor $xor$ls180.v:4984$767 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [37] - connect \B \main_sdcore_crc7_inserter_crcreg2 [6] - connect \Y $xor$ls180.v:4984$767_Y - end - attribute \src "ls180.v:4984.200-4984.272" - cell $xor $xor$ls180.v:4984$768 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [37] - connect \B \main_sdcore_crc7_inserter_crcreg2 [6] - connect \Y $xor$ls180.v:4984$768_Y - end - attribute \src "ls180.v:4984.160-4984.273" - cell $xor $xor$ls180.v:4984$769 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg2 [2] - connect \B $xor$ls180.v:4984$768_Y - connect \Y $xor$ls180.v:4984$769_Y - end - attribute \src "ls180.v:4985.353-4985.425" - cell $xor $xor$ls180.v:4985$770 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [36] - connect \B \main_sdcore_crc7_inserter_crcreg3 [6] - connect \Y $xor$ls180.v:4985$770_Y - end - attribute \src "ls180.v:4985.200-4985.272" - cell $xor $xor$ls180.v:4985$771 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [36] - connect \B \main_sdcore_crc7_inserter_crcreg3 [6] - connect \Y $xor$ls180.v:4985$771_Y - end - attribute \src "ls180.v:4985.160-4985.273" - cell $xor $xor$ls180.v:4985$772 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg3 [2] - connect \B $xor$ls180.v:4985$771_Y - connect \Y $xor$ls180.v:4985$772_Y - end - attribute \src "ls180.v:4986.353-4986.425" - cell $xor $xor$ls180.v:4986$773 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [35] - connect \B \main_sdcore_crc7_inserter_crcreg4 [6] - connect \Y $xor$ls180.v:4986$773_Y - end - attribute \src "ls180.v:4986.200-4986.272" - cell $xor $xor$ls180.v:4986$774 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [35] - connect \B \main_sdcore_crc7_inserter_crcreg4 [6] - connect \Y $xor$ls180.v:4986$774_Y - end - attribute \src "ls180.v:4986.160-4986.273" - cell $xor $xor$ls180.v:4986$775 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg4 [2] - connect \B $xor$ls180.v:4986$774_Y - connect \Y $xor$ls180.v:4986$775_Y - end - attribute \src "ls180.v:4987.353-4987.425" - cell $xor $xor$ls180.v:4987$776 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [34] - connect \B \main_sdcore_crc7_inserter_crcreg5 [6] - connect \Y $xor$ls180.v:4987$776_Y - end - attribute \src "ls180.v:4987.200-4987.272" - cell $xor $xor$ls180.v:4987$777 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [34] - connect \B \main_sdcore_crc7_inserter_crcreg5 [6] - connect \Y $xor$ls180.v:4987$777_Y - end - attribute \src "ls180.v:4987.160-4987.273" - cell $xor $xor$ls180.v:4987$778 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg5 [2] - connect \B $xor$ls180.v:4987$777_Y - connect \Y $xor$ls180.v:4987$778_Y - end - attribute \src "ls180.v:4988.353-4988.425" - cell $xor $xor$ls180.v:4988$779 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [33] - connect \B \main_sdcore_crc7_inserter_crcreg6 [6] - connect \Y $xor$ls180.v:4988$779_Y - end - attribute \src "ls180.v:4988.200-4988.272" - cell $xor $xor$ls180.v:4988$780 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [33] - connect \B \main_sdcore_crc7_inserter_crcreg6 [6] - connect \Y $xor$ls180.v:4988$780_Y - end - attribute \src "ls180.v:4988.160-4988.273" - cell $xor $xor$ls180.v:4988$781 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg6 [2] - connect \B $xor$ls180.v:4988$780_Y - connect \Y $xor$ls180.v:4988$781_Y - end - attribute \src "ls180.v:4989.353-4989.425" - cell $xor $xor$ls180.v:4989$782 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [32] - connect \B \main_sdcore_crc7_inserter_crcreg7 [6] - connect \Y $xor$ls180.v:4989$782_Y - end - attribute \src "ls180.v:4989.200-4989.272" - cell $xor $xor$ls180.v:4989$783 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [32] - connect \B \main_sdcore_crc7_inserter_crcreg7 [6] - connect \Y $xor$ls180.v:4989$783_Y - end - attribute \src "ls180.v:4989.160-4989.273" - cell $xor $xor$ls180.v:4989$784 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg7 [2] - connect \B $xor$ls180.v:4989$783_Y - connect \Y $xor$ls180.v:4989$784_Y - end - attribute \src "ls180.v:4990.353-4990.425" - cell $xor $xor$ls180.v:4990$785 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [31] - connect \B \main_sdcore_crc7_inserter_crcreg8 [6] - connect \Y $xor$ls180.v:4990$785_Y - end - attribute \src "ls180.v:4990.200-4990.272" - cell $xor $xor$ls180.v:4990$786 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [31] - connect \B \main_sdcore_crc7_inserter_crcreg8 [6] - connect \Y $xor$ls180.v:4990$786_Y - end - attribute \src "ls180.v:4990.160-4990.273" - cell $xor $xor$ls180.v:4990$787 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg8 [2] - connect \B $xor$ls180.v:4990$786_Y - connect \Y $xor$ls180.v:4990$787_Y - end - attribute \src "ls180.v:4991.354-4991.426" - cell $xor $xor$ls180.v:4991$788 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [30] - connect \B \main_sdcore_crc7_inserter_crcreg9 [6] - connect \Y $xor$ls180.v:4991$788_Y - end - attribute \src "ls180.v:4991.201-4991.273" - cell $xor $xor$ls180.v:4991$789 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [30] - connect \B \main_sdcore_crc7_inserter_crcreg9 [6] - connect \Y $xor$ls180.v:4991$789_Y - end - attribute \src "ls180.v:4991.161-4991.274" - cell $xor $xor$ls180.v:4991$790 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg9 [2] - connect \B $xor$ls180.v:4991$789_Y - connect \Y $xor$ls180.v:4991$790_Y - end - attribute \src "ls180.v:4992.361-4992.434" - cell $xor $xor$ls180.v:4992$791 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [29] - connect \B \main_sdcore_crc7_inserter_crcreg10 [6] - connect \Y $xor$ls180.v:4992$791_Y - end - attribute \src "ls180.v:4992.205-4992.278" - cell $xor $xor$ls180.v:4992$792 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [29] - connect \B \main_sdcore_crc7_inserter_crcreg10 [6] - connect \Y $xor$ls180.v:4992$792_Y - end - attribute \src "ls180.v:4992.164-4992.279" - cell $xor $xor$ls180.v:4992$793 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg10 [2] - connect \B $xor$ls180.v:4992$792_Y - connect \Y $xor$ls180.v:4992$793_Y - end - attribute \src "ls180.v:4993.361-4993.434" - cell $xor $xor$ls180.v:4993$794 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [28] - connect \B \main_sdcore_crc7_inserter_crcreg11 [6] - connect \Y $xor$ls180.v:4993$794_Y - end - attribute \src "ls180.v:4993.205-4993.278" - cell $xor $xor$ls180.v:4993$795 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [28] - connect \B \main_sdcore_crc7_inserter_crcreg11 [6] - connect \Y $xor$ls180.v:4993$795_Y - end - attribute \src "ls180.v:4993.164-4993.279" - cell $xor $xor$ls180.v:4993$796 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg11 [2] - connect \B $xor$ls180.v:4993$795_Y - connect \Y $xor$ls180.v:4993$796_Y - end - attribute \src "ls180.v:4994.361-4994.434" - cell $xor $xor$ls180.v:4994$797 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [27] - connect \B \main_sdcore_crc7_inserter_crcreg12 [6] - connect \Y $xor$ls180.v:4994$797_Y - end - attribute \src "ls180.v:4994.205-4994.278" - cell $xor $xor$ls180.v:4994$798 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [27] - connect \B \main_sdcore_crc7_inserter_crcreg12 [6] - connect \Y $xor$ls180.v:4994$798_Y - end - attribute \src "ls180.v:4994.164-4994.279" - cell $xor $xor$ls180.v:4994$799 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg12 [2] - connect \B $xor$ls180.v:4994$798_Y - connect \Y $xor$ls180.v:4994$799_Y - end - attribute \src "ls180.v:4995.361-4995.434" - cell $xor $xor$ls180.v:4995$800 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [26] - connect \B \main_sdcore_crc7_inserter_crcreg13 [6] - connect \Y $xor$ls180.v:4995$800_Y - end - attribute \src "ls180.v:4995.205-4995.278" - cell $xor $xor$ls180.v:4995$801 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [26] - connect \B \main_sdcore_crc7_inserter_crcreg13 [6] - connect \Y $xor$ls180.v:4995$801_Y - end - attribute \src "ls180.v:4995.164-4995.279" - cell $xor $xor$ls180.v:4995$802 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg13 [2] - connect \B $xor$ls180.v:4995$801_Y - connect \Y $xor$ls180.v:4995$802_Y - end - attribute \src "ls180.v:4996.361-4996.434" - cell $xor $xor$ls180.v:4996$803 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [25] - connect \B \main_sdcore_crc7_inserter_crcreg14 [6] - connect \Y $xor$ls180.v:4996$803_Y - end - attribute \src "ls180.v:4996.205-4996.278" - cell $xor $xor$ls180.v:4996$804 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [25] - connect \B \main_sdcore_crc7_inserter_crcreg14 [6] - connect \Y $xor$ls180.v:4996$804_Y - end - attribute \src "ls180.v:4996.164-4996.279" - cell $xor $xor$ls180.v:4996$805 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg14 [2] - connect \B $xor$ls180.v:4996$804_Y - connect \Y $xor$ls180.v:4996$805_Y - end - attribute \src "ls180.v:4997.361-4997.434" - cell $xor $xor$ls180.v:4997$806 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [24] - connect \B \main_sdcore_crc7_inserter_crcreg15 [6] - connect \Y $xor$ls180.v:4997$806_Y - end - attribute \src "ls180.v:4997.205-4997.278" - cell $xor $xor$ls180.v:4997$807 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [24] - connect \B \main_sdcore_crc7_inserter_crcreg15 [6] - connect \Y $xor$ls180.v:4997$807_Y - end - attribute \src "ls180.v:4997.164-4997.279" - cell $xor $xor$ls180.v:4997$808 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg15 [2] - connect \B $xor$ls180.v:4997$807_Y - connect \Y $xor$ls180.v:4997$808_Y - end - attribute \src "ls180.v:4998.361-4998.434" - cell $xor $xor$ls180.v:4998$809 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [23] - connect \B \main_sdcore_crc7_inserter_crcreg16 [6] - connect \Y $xor$ls180.v:4998$809_Y - end - attribute \src "ls180.v:4998.205-4998.278" - cell $xor $xor$ls180.v:4998$810 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [23] - connect \B \main_sdcore_crc7_inserter_crcreg16 [6] - connect \Y $xor$ls180.v:4998$810_Y - end - attribute \src "ls180.v:4998.164-4998.279" - cell $xor $xor$ls180.v:4998$811 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg16 [2] - connect \B $xor$ls180.v:4998$810_Y - connect \Y $xor$ls180.v:4998$811_Y - end - attribute \src "ls180.v:4999.361-4999.434" - cell $xor $xor$ls180.v:4999$812 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [22] - connect \B \main_sdcore_crc7_inserter_crcreg17 [6] - connect \Y $xor$ls180.v:4999$812_Y - end - attribute \src "ls180.v:4999.205-4999.278" - cell $xor $xor$ls180.v:4999$813 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [22] - connect \B \main_sdcore_crc7_inserter_crcreg17 [6] - connect \Y $xor$ls180.v:4999$813_Y - end - attribute \src "ls180.v:4999.164-4999.279" - cell $xor $xor$ls180.v:4999$814 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg17 [2] - connect \B $xor$ls180.v:4999$813_Y - connect \Y $xor$ls180.v:4999$814_Y - end - attribute \src "ls180.v:5000.361-5000.434" - cell $xor $xor$ls180.v:5000$815 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [21] - connect \B \main_sdcore_crc7_inserter_crcreg18 [6] - connect \Y $xor$ls180.v:5000$815_Y - end - attribute \src "ls180.v:5000.205-5000.278" - cell $xor $xor$ls180.v:5000$816 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [21] - connect \B \main_sdcore_crc7_inserter_crcreg18 [6] - connect \Y $xor$ls180.v:5000$816_Y - end - attribute \src "ls180.v:5000.164-5000.279" - cell $xor $xor$ls180.v:5000$817 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg18 [2] - connect \B $xor$ls180.v:5000$816_Y - connect \Y $xor$ls180.v:5000$817_Y - end - attribute \src "ls180.v:5001.361-5001.434" - cell $xor $xor$ls180.v:5001$818 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [20] - connect \B \main_sdcore_crc7_inserter_crcreg19 [6] - connect \Y $xor$ls180.v:5001$818_Y - end - attribute \src "ls180.v:5001.205-5001.278" - cell $xor $xor$ls180.v:5001$819 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [20] - connect \B \main_sdcore_crc7_inserter_crcreg19 [6] - connect \Y $xor$ls180.v:5001$819_Y - end - attribute \src "ls180.v:5001.164-5001.279" - cell $xor $xor$ls180.v:5001$820 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg19 [2] - connect \B $xor$ls180.v:5001$819_Y - connect \Y $xor$ls180.v:5001$820_Y - end - attribute \src "ls180.v:5002.361-5002.434" - cell $xor $xor$ls180.v:5002$821 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [19] - connect \B \main_sdcore_crc7_inserter_crcreg20 [6] - connect \Y $xor$ls180.v:5002$821_Y - end - attribute \src "ls180.v:5002.205-5002.278" - cell $xor $xor$ls180.v:5002$822 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [19] - connect \B \main_sdcore_crc7_inserter_crcreg20 [6] - connect \Y $xor$ls180.v:5002$822_Y - end - attribute \src "ls180.v:5002.164-5002.279" - cell $xor $xor$ls180.v:5002$823 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg20 [2] - connect \B $xor$ls180.v:5002$822_Y - connect \Y $xor$ls180.v:5002$823_Y - end - attribute \src "ls180.v:5003.361-5003.434" - cell $xor $xor$ls180.v:5003$824 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [18] - connect \B \main_sdcore_crc7_inserter_crcreg21 [6] - connect \Y $xor$ls180.v:5003$824_Y - end - attribute \src "ls180.v:5003.205-5003.278" - cell $xor $xor$ls180.v:5003$825 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [18] - connect \B \main_sdcore_crc7_inserter_crcreg21 [6] - connect \Y $xor$ls180.v:5003$825_Y - end - attribute \src "ls180.v:5003.164-5003.279" - cell $xor $xor$ls180.v:5003$826 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg21 [2] - connect \B $xor$ls180.v:5003$825_Y - connect \Y $xor$ls180.v:5003$826_Y - end - attribute \src "ls180.v:5004.361-5004.434" - cell $xor $xor$ls180.v:5004$827 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [17] - connect \B \main_sdcore_crc7_inserter_crcreg22 [6] - connect \Y $xor$ls180.v:5004$827_Y - end - attribute \src "ls180.v:5004.205-5004.278" - cell $xor $xor$ls180.v:5004$828 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [17] - connect \B \main_sdcore_crc7_inserter_crcreg22 [6] - connect \Y $xor$ls180.v:5004$828_Y - end - attribute \src "ls180.v:5004.164-5004.279" - cell $xor $xor$ls180.v:5004$829 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg22 [2] - connect \B $xor$ls180.v:5004$828_Y - connect \Y $xor$ls180.v:5004$829_Y - end - attribute \src "ls180.v:5005.361-5005.434" - cell $xor $xor$ls180.v:5005$830 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [16] - connect \B \main_sdcore_crc7_inserter_crcreg23 [6] - connect \Y $xor$ls180.v:5005$830_Y - end - attribute \src "ls180.v:5005.205-5005.278" - cell $xor $xor$ls180.v:5005$831 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [16] - connect \B \main_sdcore_crc7_inserter_crcreg23 [6] - connect \Y $xor$ls180.v:5005$831_Y - end - attribute \src "ls180.v:5005.164-5005.279" - cell $xor $xor$ls180.v:5005$832 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg23 [2] - connect \B $xor$ls180.v:5005$831_Y - connect \Y $xor$ls180.v:5005$832_Y - end - attribute \src "ls180.v:5006.361-5006.434" - cell $xor $xor$ls180.v:5006$833 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [15] - connect \B \main_sdcore_crc7_inserter_crcreg24 [6] - connect \Y $xor$ls180.v:5006$833_Y - end - attribute \src "ls180.v:5006.205-5006.278" - cell $xor $xor$ls180.v:5006$834 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [15] - connect \B \main_sdcore_crc7_inserter_crcreg24 [6] - connect \Y $xor$ls180.v:5006$834_Y - end - attribute \src "ls180.v:5006.164-5006.279" - cell $xor $xor$ls180.v:5006$835 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg24 [2] - connect \B $xor$ls180.v:5006$834_Y - connect \Y $xor$ls180.v:5006$835_Y - end - attribute \src "ls180.v:5007.361-5007.434" - cell $xor $xor$ls180.v:5007$836 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [14] - connect \B \main_sdcore_crc7_inserter_crcreg25 [6] - connect \Y $xor$ls180.v:5007$836_Y - end - attribute \src "ls180.v:5007.205-5007.278" - cell $xor $xor$ls180.v:5007$837 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [14] - connect \B \main_sdcore_crc7_inserter_crcreg25 [6] - connect \Y $xor$ls180.v:5007$837_Y - end - attribute \src "ls180.v:5007.164-5007.279" - cell $xor $xor$ls180.v:5007$838 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg25 [2] - connect \B $xor$ls180.v:5007$837_Y - connect \Y $xor$ls180.v:5007$838_Y - end - attribute \src "ls180.v:5008.361-5008.434" - cell $xor $xor$ls180.v:5008$839 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [13] - connect \B \main_sdcore_crc7_inserter_crcreg26 [6] - connect \Y $xor$ls180.v:5008$839_Y - end - attribute \src "ls180.v:5008.205-5008.278" - cell $xor $xor$ls180.v:5008$840 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [13] - connect \B \main_sdcore_crc7_inserter_crcreg26 [6] - connect \Y $xor$ls180.v:5008$840_Y - end - attribute \src "ls180.v:5008.164-5008.279" - cell $xor $xor$ls180.v:5008$841 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg26 [2] - connect \B $xor$ls180.v:5008$840_Y - connect \Y $xor$ls180.v:5008$841_Y - end - attribute \src "ls180.v:5009.361-5009.434" - cell $xor $xor$ls180.v:5009$842 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [12] - connect \B \main_sdcore_crc7_inserter_crcreg27 [6] - connect \Y $xor$ls180.v:5009$842_Y - end - attribute \src "ls180.v:5009.205-5009.278" - cell $xor $xor$ls180.v:5009$843 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [12] - connect \B \main_sdcore_crc7_inserter_crcreg27 [6] - connect \Y $xor$ls180.v:5009$843_Y - end - attribute \src "ls180.v:5009.164-5009.279" - cell $xor $xor$ls180.v:5009$844 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg27 [2] - connect \B $xor$ls180.v:5009$843_Y - connect \Y $xor$ls180.v:5009$844_Y - end - attribute \src "ls180.v:5010.361-5010.434" - cell $xor $xor$ls180.v:5010$845 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [11] - connect \B \main_sdcore_crc7_inserter_crcreg28 [6] - connect \Y $xor$ls180.v:5010$845_Y - end - attribute \src "ls180.v:5010.205-5010.278" - cell $xor $xor$ls180.v:5010$846 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [11] - connect \B \main_sdcore_crc7_inserter_crcreg28 [6] - connect \Y $xor$ls180.v:5010$846_Y - end - attribute \src "ls180.v:5010.164-5010.279" - cell $xor $xor$ls180.v:5010$847 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg28 [2] - connect \B $xor$ls180.v:5010$846_Y - connect \Y $xor$ls180.v:5010$847_Y - end - attribute \src "ls180.v:5011.361-5011.434" - cell $xor $xor$ls180.v:5011$848 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [10] - connect \B \main_sdcore_crc7_inserter_crcreg29 [6] - connect \Y $xor$ls180.v:5011$848_Y - end - attribute \src "ls180.v:5011.205-5011.278" - cell $xor $xor$ls180.v:5011$849 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [10] - connect \B \main_sdcore_crc7_inserter_crcreg29 [6] - connect \Y $xor$ls180.v:5011$849_Y - end - attribute \src "ls180.v:5011.164-5011.279" - cell $xor $xor$ls180.v:5011$850 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg29 [2] - connect \B $xor$ls180.v:5011$849_Y - connect \Y $xor$ls180.v:5011$850_Y - end - attribute \src "ls180.v:5012.360-5012.432" - cell $xor $xor$ls180.v:5012$851 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [9] - connect \B \main_sdcore_crc7_inserter_crcreg30 [6] - connect \Y $xor$ls180.v:5012$851_Y - end - attribute \src "ls180.v:5012.205-5012.277" - cell $xor $xor$ls180.v:5012$852 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [9] - connect \B \main_sdcore_crc7_inserter_crcreg30 [6] - connect \Y $xor$ls180.v:5012$852_Y - end - attribute \src "ls180.v:5012.164-5012.278" - cell $xor $xor$ls180.v:5012$853 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg30 [2] - connect \B $xor$ls180.v:5012$852_Y - connect \Y $xor$ls180.v:5012$853_Y - end - attribute \src "ls180.v:5013.360-5013.432" - cell $xor $xor$ls180.v:5013$854 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [8] - connect \B \main_sdcore_crc7_inserter_crcreg31 [6] - connect \Y $xor$ls180.v:5013$854_Y - end - attribute \src "ls180.v:5013.205-5013.277" - cell $xor $xor$ls180.v:5013$855 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [8] - connect \B \main_sdcore_crc7_inserter_crcreg31 [6] - connect \Y $xor$ls180.v:5013$855_Y - end - attribute \src "ls180.v:5013.164-5013.278" - cell $xor $xor$ls180.v:5013$856 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg31 [2] - connect \B $xor$ls180.v:5013$855_Y - connect \Y $xor$ls180.v:5013$856_Y - end - attribute \src "ls180.v:5014.360-5014.432" - cell $xor $xor$ls180.v:5014$857 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [7] - connect \B \main_sdcore_crc7_inserter_crcreg32 [6] - connect \Y $xor$ls180.v:5014$857_Y - end - attribute \src "ls180.v:5014.205-5014.277" - cell $xor $xor$ls180.v:5014$858 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [7] - connect \B \main_sdcore_crc7_inserter_crcreg32 [6] - connect \Y $xor$ls180.v:5014$858_Y - end - attribute \src "ls180.v:5014.164-5014.278" - cell $xor $xor$ls180.v:5014$859 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg32 [2] - connect \B $xor$ls180.v:5014$858_Y - connect \Y $xor$ls180.v:5014$859_Y - end - attribute \src "ls180.v:5015.360-5015.432" - cell $xor $xor$ls180.v:5015$860 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [6] - connect \B \main_sdcore_crc7_inserter_crcreg33 [6] - connect \Y $xor$ls180.v:5015$860_Y - end - attribute \src "ls180.v:5015.205-5015.277" - cell $xor $xor$ls180.v:5015$861 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [6] - connect \B \main_sdcore_crc7_inserter_crcreg33 [6] - connect \Y $xor$ls180.v:5015$861_Y - end - attribute \src "ls180.v:5015.164-5015.278" - cell $xor $xor$ls180.v:5015$862 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg33 [2] - connect \B $xor$ls180.v:5015$861_Y - connect \Y $xor$ls180.v:5015$862_Y - end - attribute \src "ls180.v:5016.360-5016.432" - cell $xor $xor$ls180.v:5016$863 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [5] - connect \B \main_sdcore_crc7_inserter_crcreg34 [6] - connect \Y $xor$ls180.v:5016$863_Y - end - attribute \src "ls180.v:5016.205-5016.277" - cell $xor $xor$ls180.v:5016$864 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [5] - connect \B \main_sdcore_crc7_inserter_crcreg34 [6] - connect \Y $xor$ls180.v:5016$864_Y - end - attribute \src "ls180.v:5016.164-5016.278" - cell $xor $xor$ls180.v:5016$865 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg34 [2] - connect \B $xor$ls180.v:5016$864_Y - connect \Y $xor$ls180.v:5016$865_Y - end - attribute \src "ls180.v:5017.360-5017.432" - cell $xor $xor$ls180.v:5017$866 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [4] - connect \B \main_sdcore_crc7_inserter_crcreg35 [6] - connect \Y $xor$ls180.v:5017$866_Y - end - attribute \src "ls180.v:5017.205-5017.277" - cell $xor $xor$ls180.v:5017$867 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [4] - connect \B \main_sdcore_crc7_inserter_crcreg35 [6] - connect \Y $xor$ls180.v:5017$867_Y - end - attribute \src "ls180.v:5017.164-5017.278" - cell $xor $xor$ls180.v:5017$868 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg35 [2] - connect \B $xor$ls180.v:5017$867_Y - connect \Y $xor$ls180.v:5017$868_Y - end - attribute \src "ls180.v:5018.360-5018.432" - cell $xor $xor$ls180.v:5018$869 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [3] - connect \B \main_sdcore_crc7_inserter_crcreg36 [6] - connect \Y $xor$ls180.v:5018$869_Y - end - attribute \src "ls180.v:5018.205-5018.277" - cell $xor $xor$ls180.v:5018$870 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [3] - connect \B \main_sdcore_crc7_inserter_crcreg36 [6] - connect \Y $xor$ls180.v:5018$870_Y - end - attribute \src "ls180.v:5018.164-5018.278" - cell $xor $xor$ls180.v:5018$871 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg36 [2] - connect \B $xor$ls180.v:5018$870_Y - connect \Y $xor$ls180.v:5018$871_Y - end - attribute \src "ls180.v:5019.360-5019.432" - cell $xor $xor$ls180.v:5019$872 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [2] - connect \B \main_sdcore_crc7_inserter_crcreg37 [6] - connect \Y $xor$ls180.v:5019$872_Y - end - attribute \src "ls180.v:5019.205-5019.277" - cell $xor $xor$ls180.v:5019$873 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [2] - connect \B \main_sdcore_crc7_inserter_crcreg37 [6] - connect \Y $xor$ls180.v:5019$873_Y - end - attribute \src "ls180.v:5019.164-5019.278" - cell $xor $xor$ls180.v:5019$874 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg37 [2] - connect \B $xor$ls180.v:5019$873_Y - connect \Y $xor$ls180.v:5019$874_Y - end - attribute \src "ls180.v:5020.360-5020.432" - cell $xor $xor$ls180.v:5020$875 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [1] - connect \B \main_sdcore_crc7_inserter_crcreg38 [6] - connect \Y $xor$ls180.v:5020$875_Y - end - attribute \src "ls180.v:5020.205-5020.277" - cell $xor $xor$ls180.v:5020$876 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [1] - connect \B \main_sdcore_crc7_inserter_crcreg38 [6] - connect \Y $xor$ls180.v:5020$876_Y - end - attribute \src "ls180.v:5020.164-5020.278" - cell $xor $xor$ls180.v:5020$877 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg38 [2] - connect \B $xor$ls180.v:5020$876_Y - connect \Y $xor$ls180.v:5020$877_Y - end - attribute \src "ls180.v:5021.360-5021.432" - cell $xor $xor$ls180.v:5021$878 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [0] - connect \B \main_sdcore_crc7_inserter_crcreg39 [6] - connect \Y $xor$ls180.v:5021$878_Y - end - attribute \src "ls180.v:5021.205-5021.277" - cell $xor $xor$ls180.v:5021$879 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_val [0] - connect \B \main_sdcore_crc7_inserter_crcreg39 [6] - connect \Y $xor$ls180.v:5021$879_Y - end - attribute \src "ls180.v:5021.164-5021.278" - cell $xor $xor$ls180.v:5021$880 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc7_inserter_crcreg39 [2] - connect \B $xor$ls180.v:5021$879_Y - connect \Y $xor$ls180.v:5021$880_Y - end - attribute \src "ls180.v:5042.899-5042.983" - cell $xor $xor$ls180.v:5042$894 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_val [1] - connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5042$894_Y - end - attribute \src "ls180.v:5042.634-5042.718" - cell $xor $xor$ls180.v:5042$895 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_val [1] - connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5042$895_Y - end - attribute \src "ls180.v:5042.588-5042.719" - cell $xor $xor$ls180.v:5042$896 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [4] - connect \B $xor$ls180.v:5042$895_Y - connect \Y $xor$ls180.v:5042$896_Y - end - attribute \src "ls180.v:5042.234-5042.318" - cell $xor $xor$ls180.v:5042$897 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_val [1] - connect \B \main_sdcore_crc16_inserter_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5042$897_Y - end - attribute \src "ls180.v:5042.187-5042.319" - cell $xor $xor$ls180.v:5042$898 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_crcreg0 [11] - connect \B $xor$ls180.v:5042$897_Y - connect \Y $xor$ls180.v:5042$898_Y - end - attribute \src "ls180.v:5043.899-5043.983" - cell $xor $xor$ls180.v:5043$899 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_val [0] - connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5043$899_Y - end - attribute \src "ls180.v:5043.634-5043.718" - cell $xor $xor$ls180.v:5043$900 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_val [0] - connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5043$900_Y - end - attribute \src "ls180.v:5043.588-5043.719" - cell $xor $xor$ls180.v:5043$901 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [4] - connect \B $xor$ls180.v:5043$900_Y - connect \Y $xor$ls180.v:5043$901_Y - end - attribute \src "ls180.v:5043.234-5043.318" - cell $xor $xor$ls180.v:5043$902 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_val [0] - connect \B \main_sdcore_crc16_inserter_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5043$902_Y - end - attribute \src "ls180.v:5043.187-5043.319" - cell $xor $xor$ls180.v:5043$903 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc0_crcreg1 [11] - connect \B $xor$ls180.v:5043$902_Y - connect \Y $xor$ls180.v:5043$903_Y - end - attribute \src "ls180.v:5052.899-5052.983" - cell $xor $xor$ls180.v:5052$905 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_val [1] - connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5052$905_Y - end - attribute \src "ls180.v:5052.634-5052.718" - cell $xor $xor$ls180.v:5052$906 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_val [1] - connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5052$906_Y - end - attribute \src "ls180.v:5052.588-5052.719" - cell $xor $xor$ls180.v:5052$907 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [4] - connect \B $xor$ls180.v:5052$906_Y - connect \Y $xor$ls180.v:5052$907_Y - end - attribute \src "ls180.v:5052.234-5052.318" - cell $xor $xor$ls180.v:5052$908 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_val [1] - connect \B \main_sdcore_crc16_inserter_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5052$908_Y - end - attribute \src "ls180.v:5052.187-5052.319" - cell $xor $xor$ls180.v:5052$909 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_crcreg0 [11] - connect \B $xor$ls180.v:5052$908_Y - connect \Y $xor$ls180.v:5052$909_Y - end - attribute \src "ls180.v:5053.899-5053.983" - cell $xor $xor$ls180.v:5053$910 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_val [0] - connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5053$910_Y - end - attribute \src "ls180.v:5053.634-5053.718" - cell $xor $xor$ls180.v:5053$911 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_val [0] - connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5053$911_Y - end - attribute \src "ls180.v:5053.588-5053.719" - cell $xor $xor$ls180.v:5053$912 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [4] - connect \B $xor$ls180.v:5053$911_Y - connect \Y $xor$ls180.v:5053$912_Y - end - attribute \src "ls180.v:5053.234-5053.318" - cell $xor $xor$ls180.v:5053$913 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_val [0] - connect \B \main_sdcore_crc16_inserter_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5053$913_Y - end - attribute \src "ls180.v:5053.187-5053.319" - cell $xor $xor$ls180.v:5053$914 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc1_crcreg1 [11] - connect \B $xor$ls180.v:5053$913_Y - connect \Y $xor$ls180.v:5053$914_Y - end - attribute \src "ls180.v:5062.899-5062.983" - cell $xor $xor$ls180.v:5062$916 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_val [1] - connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5062$916_Y - end - attribute \src "ls180.v:5062.634-5062.718" - cell $xor $xor$ls180.v:5062$917 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_val [1] - connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5062$917_Y - end - attribute \src "ls180.v:5062.588-5062.719" - cell $xor $xor$ls180.v:5062$918 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [4] - connect \B $xor$ls180.v:5062$917_Y - connect \Y $xor$ls180.v:5062$918_Y - end - attribute \src "ls180.v:5062.234-5062.318" - cell $xor $xor$ls180.v:5062$919 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_val [1] - connect \B \main_sdcore_crc16_inserter_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5062$919_Y - end - attribute \src "ls180.v:5062.187-5062.319" - cell $xor $xor$ls180.v:5062$920 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_crcreg0 [11] - connect \B $xor$ls180.v:5062$919_Y - connect \Y $xor$ls180.v:5062$920_Y - end - attribute \src "ls180.v:5063.899-5063.983" - cell $xor $xor$ls180.v:5063$921 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_val [0] - connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5063$921_Y - end - attribute \src "ls180.v:5063.634-5063.718" - cell $xor $xor$ls180.v:5063$922 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_val [0] - connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5063$922_Y - end - attribute \src "ls180.v:5063.588-5063.719" - cell $xor $xor$ls180.v:5063$923 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [4] - connect \B $xor$ls180.v:5063$922_Y - connect \Y $xor$ls180.v:5063$923_Y - end - attribute \src "ls180.v:5063.234-5063.318" - cell $xor $xor$ls180.v:5063$924 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_val [0] - connect \B \main_sdcore_crc16_inserter_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5063$924_Y - end - attribute \src "ls180.v:5063.187-5063.319" - cell $xor $xor$ls180.v:5063$925 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc2_crcreg1 [11] - connect \B $xor$ls180.v:5063$924_Y - connect \Y $xor$ls180.v:5063$925_Y - end - attribute \src "ls180.v:5072.899-5072.983" - cell $xor $xor$ls180.v:5072$927 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_val [1] - connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5072$927_Y - end - attribute \src "ls180.v:5072.634-5072.718" - cell $xor $xor$ls180.v:5072$928 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_val [1] - connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5072$928_Y - end - attribute \src "ls180.v:5072.588-5072.719" - cell $xor $xor$ls180.v:5072$929 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [4] - connect \B $xor$ls180.v:5072$928_Y - connect \Y $xor$ls180.v:5072$929_Y - end - attribute \src "ls180.v:5072.234-5072.318" - cell $xor $xor$ls180.v:5072$930 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_val [1] - connect \B \main_sdcore_crc16_inserter_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5072$930_Y - end - attribute \src "ls180.v:5072.187-5072.319" - cell $xor $xor$ls180.v:5072$931 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_crcreg0 [11] - connect \B $xor$ls180.v:5072$930_Y - connect \Y $xor$ls180.v:5072$931_Y - end - attribute \src "ls180.v:5073.899-5073.983" - cell $xor $xor$ls180.v:5073$932 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_val [0] - connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5073$932_Y - end - attribute \src "ls180.v:5073.634-5073.718" - cell $xor $xor$ls180.v:5073$933 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_val [0] - connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5073$933_Y - end - attribute \src "ls180.v:5073.588-5073.719" - cell $xor $xor$ls180.v:5073$934 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [4] - connect \B $xor$ls180.v:5073$933_Y - connect \Y $xor$ls180.v:5073$934_Y - end - attribute \src "ls180.v:5073.234-5073.318" - cell $xor $xor$ls180.v:5073$935 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_val [0] - connect \B \main_sdcore_crc16_inserter_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5073$935_Y - end - attribute \src "ls180.v:5073.187-5073.319" - cell $xor $xor$ls180.v:5073$936 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_inserter_crc3_crcreg1 [11] - connect \B $xor$ls180.v:5073$935_Y - connect \Y $xor$ls180.v:5073$936_Y - end - attribute \src "ls180.v:5224.879-5224.961" - cell $xor $xor$ls180.v:5224$969 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_val [1] - connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5224$969_Y - end - attribute \src "ls180.v:5224.620-5224.702" - cell $xor $xor$ls180.v:5224$970 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_val [1] - connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5224$970_Y - end - attribute \src "ls180.v:5224.575-5224.703" - cell $xor $xor$ls180.v:5224$971 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [4] - connect \B $xor$ls180.v:5224$970_Y - connect \Y $xor$ls180.v:5224$971_Y - end - attribute \src "ls180.v:5224.229-5224.311" - cell $xor $xor$ls180.v:5224$972 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_val [1] - connect \B \main_sdcore_crc16_checker_crc0_crcreg0 [15] - connect \Y $xor$ls180.v:5224$972_Y - end - attribute \src "ls180.v:5224.183-5224.312" - cell $xor $xor$ls180.v:5224$973 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_crcreg0 [11] - connect \B $xor$ls180.v:5224$972_Y - connect \Y $xor$ls180.v:5224$973_Y - end - attribute \src "ls180.v:5225.879-5225.961" - cell $xor $xor$ls180.v:5225$974 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_val [0] - connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5225$974_Y - end - attribute \src "ls180.v:5225.620-5225.702" - cell $xor $xor$ls180.v:5225$975 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_val [0] - connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5225$975_Y - end - attribute \src "ls180.v:5225.575-5225.703" - cell $xor $xor$ls180.v:5225$976 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [4] - connect \B $xor$ls180.v:5225$975_Y - connect \Y $xor$ls180.v:5225$976_Y - end - attribute \src "ls180.v:5225.229-5225.311" - cell $xor $xor$ls180.v:5225$977 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_val [0] - connect \B \main_sdcore_crc16_checker_crc0_crcreg1 [15] - connect \Y $xor$ls180.v:5225$977_Y - end - attribute \src "ls180.v:5225.183-5225.312" - cell $xor $xor$ls180.v:5225$978 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc0_crcreg1 [11] - connect \B $xor$ls180.v:5225$977_Y - connect \Y $xor$ls180.v:5225$978_Y - end - attribute \src "ls180.v:5234.879-5234.961" - cell $xor $xor$ls180.v:5234$980 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_val [1] - connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5234$980_Y - end - attribute \src "ls180.v:5234.620-5234.702" - cell $xor $xor$ls180.v:5234$981 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_val [1] - connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5234$981_Y - end - attribute \src "ls180.v:5234.575-5234.703" - cell $xor $xor$ls180.v:5234$982 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [4] - connect \B $xor$ls180.v:5234$981_Y - connect \Y $xor$ls180.v:5234$982_Y - end - attribute \src "ls180.v:5234.229-5234.311" - cell $xor $xor$ls180.v:5234$983 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_val [1] - connect \B \main_sdcore_crc16_checker_crc1_crcreg0 [15] - connect \Y $xor$ls180.v:5234$983_Y - end - attribute \src "ls180.v:5234.183-5234.312" - cell $xor $xor$ls180.v:5234$984 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_crcreg0 [11] - connect \B $xor$ls180.v:5234$983_Y - connect \Y $xor$ls180.v:5234$984_Y - end - attribute \src "ls180.v:5235.879-5235.961" - cell $xor $xor$ls180.v:5235$985 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_val [0] - connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5235$985_Y - end - attribute \src "ls180.v:5235.620-5235.702" - cell $xor $xor$ls180.v:5235$986 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_val [0] - connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5235$986_Y - end - attribute \src "ls180.v:5235.575-5235.703" - cell $xor $xor$ls180.v:5235$987 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [4] - connect \B $xor$ls180.v:5235$986_Y - connect \Y $xor$ls180.v:5235$987_Y - end - attribute \src "ls180.v:5235.229-5235.311" - cell $xor $xor$ls180.v:5235$988 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_val [0] - connect \B \main_sdcore_crc16_checker_crc1_crcreg1 [15] - connect \Y $xor$ls180.v:5235$988_Y - end - attribute \src "ls180.v:5235.183-5235.312" - cell $xor $xor$ls180.v:5235$989 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc1_crcreg1 [11] - connect \B $xor$ls180.v:5235$988_Y - connect \Y $xor$ls180.v:5235$989_Y - end - attribute \src "ls180.v:5244.879-5244.961" - cell $xor $xor$ls180.v:5244$991 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_val [1] - connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5244$991_Y - end - attribute \src "ls180.v:5244.620-5244.702" - cell $xor $xor$ls180.v:5244$992 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_val [1] - connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5244$992_Y - end - attribute \src "ls180.v:5244.575-5244.703" - cell $xor $xor$ls180.v:5244$993 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [4] - connect \B $xor$ls180.v:5244$992_Y - connect \Y $xor$ls180.v:5244$993_Y - end - attribute \src "ls180.v:5244.229-5244.311" - cell $xor $xor$ls180.v:5244$994 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_val [1] - connect \B \main_sdcore_crc16_checker_crc2_crcreg0 [15] - connect \Y $xor$ls180.v:5244$994_Y - end - attribute \src "ls180.v:5244.183-5244.312" - cell $xor $xor$ls180.v:5244$995 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_crcreg0 [11] - connect \B $xor$ls180.v:5244$994_Y - connect \Y $xor$ls180.v:5244$995_Y - end - attribute \src "ls180.v:5245.183-5245.312" - cell $xor $xor$ls180.v:5245$1000 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [11] - connect \B $xor$ls180.v:5245$999_Y - connect \Y $xor$ls180.v:5245$1000_Y - end - attribute \src "ls180.v:5245.879-5245.961" - cell $xor $xor$ls180.v:5245$996 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_val [0] - connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5245$996_Y - end - attribute \src "ls180.v:5245.620-5245.702" - cell $xor $xor$ls180.v:5245$997 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_val [0] - connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5245$997_Y - end - attribute \src "ls180.v:5245.575-5245.703" - cell $xor $xor$ls180.v:5245$998 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_crcreg1 [4] - connect \B $xor$ls180.v:5245$997_Y - connect \Y $xor$ls180.v:5245$998_Y - end - attribute \src "ls180.v:5245.229-5245.311" - cell $xor $xor$ls180.v:5245$999 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc2_val [0] - connect \B \main_sdcore_crc16_checker_crc2_crcreg1 [15] - connect \Y $xor$ls180.v:5245$999_Y - end - attribute \src "ls180.v:5254.879-5254.961" - cell $xor $xor$ls180.v:5254$1002 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_val [1] - connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5254$1002_Y - end - attribute \src "ls180.v:5254.620-5254.702" - cell $xor $xor$ls180.v:5254$1003 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_val [1] - connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5254$1003_Y - end - attribute \src "ls180.v:5254.575-5254.703" - cell $xor $xor$ls180.v:5254$1004 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [4] - connect \B $xor$ls180.v:5254$1003_Y - connect \Y $xor$ls180.v:5254$1004_Y - end - attribute \src "ls180.v:5254.229-5254.311" - cell $xor $xor$ls180.v:5254$1005 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_val [1] - connect \B \main_sdcore_crc16_checker_crc3_crcreg0 [15] - connect \Y $xor$ls180.v:5254$1005_Y - end - attribute \src "ls180.v:5254.183-5254.312" - cell $xor $xor$ls180.v:5254$1006 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_crcreg0 [11] - connect \B $xor$ls180.v:5254$1005_Y - connect \Y $xor$ls180.v:5254$1006_Y - end - attribute \src "ls180.v:5255.879-5255.961" - cell $xor $xor$ls180.v:5255$1007 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_val [0] - connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5255$1007_Y - end - attribute \src "ls180.v:5255.620-5255.702" - cell $xor $xor$ls180.v:5255$1008 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_val [0] - connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5255$1008_Y - end - attribute \src "ls180.v:5255.575-5255.703" - cell $xor $xor$ls180.v:5255$1009 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [4] - connect \B $xor$ls180.v:5255$1008_Y - connect \Y $xor$ls180.v:5255$1009_Y - end - attribute \src "ls180.v:5255.229-5255.311" - cell $xor $xor$ls180.v:5255$1010 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_val [0] - connect \B \main_sdcore_crc16_checker_crc3_crcreg1 [15] - connect \Y $xor$ls180.v:5255$1010_Y - end - attribute \src "ls180.v:5255.183-5255.312" - cell $xor $xor$ls180.v:5255$1011 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \main_sdcore_crc16_checker_crc3_crcreg1 [11] - connect \B $xor$ls180.v:5255$1010_Y - connect \Y $xor$ls180.v:5255$1011_Y - end - attribute \module_not_derived 1 - attribute \src "ls180.v:10316.13-10686.2" - cell \test_issuer \test_issuer - connect \TAP_bus__tck \main_libresocsim_libresoc_jtag_tck - connect \TAP_bus__tdi \main_libresocsim_libresoc_jtag_tdi - connect \TAP_bus__tdo \main_libresocsim_libresoc_jtag_tdo - connect \TAP_bus__tms \main_libresocsim_libresoc_jtag_tms - connect \busy_o \main_libresocsim_libresoc0 - connect \clk \sys_clk_1 - connect \clk_sel_i \main_libresocsim_libresoc_clk_sel - connect \core_bigendian_i 1'0 - connect \dbus__ack \main_libresocsim_libresoc_dbus_ack - connect \dbus__adr \main_libresocsim_libresoc_dbus_adr - connect \dbus__bte 1'0 - connect \dbus__cti 1'0 - connect \dbus__cyc \main_libresocsim_libresoc_dbus_cyc - connect \dbus__dat_r \main_libresocsim_libresoc_dbus_dat_r - connect \dbus__dat_w \main_libresocsim_libresoc_dbus_dat_w - connect \dbus__err \main_libresocsim_libresoc_dbus_err - connect \dbus__sel \main_libresocsim_libresoc_dbus_sel - connect \dbus__stb \main_libresocsim_libresoc_dbus_stb - connect \dbus__we \main_libresocsim_libresoc_dbus_we - connect \eint_0__core__i \eint [0] - connect \eint_0__pad__i \eint_1 [0] - connect \eint_1__core__i \eint [1] - connect \eint_1__pad__i \eint_1 [1] - connect \eint_2__core__i \eint [2] - connect \eint_2__pad__i \eint_1 [2] - connect \gpio_e10__core__i \gpio_i [10] - connect \gpio_e10__core__o \gpio_o [10] - connect \gpio_e10__core__oe \gpio_oe [10] - connect \gpio_e10__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [10] - connect \gpio_e10__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [10] - connect \gpio_e10__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [10] - connect \gpio_e11__core__i \gpio_i [11] - connect \gpio_e11__core__o \gpio_o [11] - connect \gpio_e11__core__oe \gpio_oe [11] - connect \gpio_e11__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [11] - connect \gpio_e11__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [11] - connect \gpio_e11__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [11] - connect \gpio_e12__core__i \gpio_i [12] - connect \gpio_e12__core__o \gpio_o [12] - connect \gpio_e12__core__oe \gpio_oe [12] - connect \gpio_e12__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [12] - connect \gpio_e12__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [12] - connect \gpio_e12__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [12] - connect \gpio_e13__core__i \gpio_i [13] - connect \gpio_e13__core__o \gpio_o [13] - connect \gpio_e13__core__oe \gpio_oe [13] - connect \gpio_e13__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [13] - connect \gpio_e13__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [13] - connect \gpio_e13__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [13] - connect \gpio_e14__core__i \gpio_i [14] - connect \gpio_e14__core__o \gpio_o [14] - connect \gpio_e14__core__oe \gpio_oe [14] - connect \gpio_e14__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [14] - connect \gpio_e14__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [14] - connect \gpio_e14__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [14] - connect \gpio_e15__core__i \gpio_i [15] - connect \gpio_e15__core__o \gpio_o [15] - connect \gpio_e15__core__oe \gpio_oe [15] - connect \gpio_e15__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [15] - connect \gpio_e15__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [15] - connect \gpio_e15__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [15] - connect \gpio_e8__core__i \gpio_i [8] - connect \gpio_e8__core__o \gpio_o [8] - connect \gpio_e8__core__oe \gpio_oe [8] - connect \gpio_e8__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [8] - connect \gpio_e8__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [8] - connect \gpio_e8__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [8] - connect \gpio_e9__core__i \gpio_i [9] - connect \gpio_e9__core__o \gpio_o [9] - connect \gpio_e9__core__oe \gpio_oe [9] - connect \gpio_e9__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [9] - connect \gpio_e9__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [9] - connect \gpio_e9__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [9] - connect \gpio_s0__core__i \gpio_i [0] - connect \gpio_s0__core__o \gpio_o [0] - connect \gpio_s0__core__oe \gpio_oe [0] - connect \gpio_s0__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [0] - connect \gpio_s0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [0] - connect \gpio_s0__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [0] - connect \gpio_s1__core__i \gpio_i [1] - connect \gpio_s1__core__o \gpio_o [1] - connect \gpio_s1__core__oe \gpio_oe [1] - connect \gpio_s1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [1] - connect \gpio_s1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [1] - connect \gpio_s1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [1] - connect \gpio_s2__core__i \gpio_i [2] - connect \gpio_s2__core__o \gpio_o [2] - connect \gpio_s2__core__oe \gpio_oe [2] - connect \gpio_s2__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [2] - connect \gpio_s2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [2] - connect \gpio_s2__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [2] - connect \gpio_s3__core__i \gpio_i [3] - connect \gpio_s3__core__o \gpio_o [3] - connect \gpio_s3__core__oe \gpio_oe [3] - connect \gpio_s3__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [3] - connect \gpio_s3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [3] - connect \gpio_s3__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [3] - connect \gpio_s4__core__i \gpio_i [4] - connect \gpio_s4__core__o \gpio_o [4] - connect \gpio_s4__core__oe \gpio_oe [4] - connect \gpio_s4__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [4] - connect \gpio_s4__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [4] - connect \gpio_s4__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [4] - connect \gpio_s5__core__i \gpio_i [5] - connect \gpio_s5__core__o \gpio_o [5] - connect \gpio_s5__core__oe \gpio_oe [5] - connect \gpio_s5__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [5] - connect \gpio_s5__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [5] - connect \gpio_s5__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [5] - connect \gpio_s6__core__i \gpio_i [6] - connect \gpio_s6__core__o \gpio_o [6] - connect \gpio_s6__core__oe \gpio_oe [6] - connect \gpio_s6__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [6] - connect \gpio_s6__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [6] - connect \gpio_s6__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [6] - connect \gpio_s7__core__i \gpio_i [7] - connect \gpio_s7__core__o \gpio_o [7] - connect \gpio_s7__core__oe \gpio_oe [7] - connect \gpio_s7__pad__i \main_libresocsim_libresoc_constraintmanager_obj_gpio_i [7] - connect \gpio_s7__pad__o \main_libresocsim_libresoc_constraintmanager_obj_gpio_o [7] - connect \gpio_s7__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_gpio_oe [7] - connect \ibus__ack \main_libresocsim_libresoc_ibus_ack - connect \ibus__adr \main_libresocsim_libresoc_ibus_adr - connect \ibus__bte 1'0 - connect \ibus__cti 1'0 - connect \ibus__cyc \main_libresocsim_libresoc_ibus_cyc - connect \ibus__dat_r \main_libresocsim_libresoc_ibus_dat_r - connect \ibus__dat_w \main_libresocsim_libresoc_ibus_dat_w - connect \ibus__err \main_libresocsim_libresoc_ibus_err - connect \ibus__sel \main_libresocsim_libresoc_ibus_sel - connect \ibus__stb \main_libresocsim_libresoc_ibus_stb - connect \ibus__we \main_libresocsim_libresoc_ibus_we - connect \icp_wb__ack \main_libresocsim_libresoc_xics_icp_ack - connect \icp_wb__adr \main_libresocsim_libresoc_xics_icp_adr - connect \icp_wb__cyc \main_libresocsim_libresoc_xics_icp_cyc - connect \icp_wb__dat_r \main_libresocsim_libresoc_xics_icp_dat_r - connect \icp_wb__dat_w \main_libresocsim_libresoc_xics_icp_dat_w - connect \icp_wb__err \main_libresocsim_libresoc_xics_icp_err - connect \icp_wb__sel \main_libresocsim_libresoc_xics_icp_sel - connect \icp_wb__stb \main_libresocsim_libresoc_xics_icp_stb - connect \icp_wb__we \main_libresocsim_libresoc_xics_icp_we - connect \ics_wb__ack \main_libresocsim_libresoc_xics_ics_ack - connect \ics_wb__adr \main_libresocsim_libresoc_xics_ics_adr - connect \ics_wb__cyc \main_libresocsim_libresoc_xics_ics_cyc - connect \ics_wb__dat_r \main_libresocsim_libresoc_xics_ics_dat_r - connect \ics_wb__dat_w \main_libresocsim_libresoc_xics_ics_dat_w - connect \ics_wb__err \main_libresocsim_libresoc_xics_ics_err - connect \ics_wb__sel \main_libresocsim_libresoc_xics_ics_sel - connect \ics_wb__stb \main_libresocsim_libresoc_xics_ics_stb - connect \ics_wb__we \main_libresocsim_libresoc_xics_ics_we - connect \int_level_i \main_libresocsim_libresoc_interrupt - connect \jtag_wb__ack \main_libresocsim_libresoc_jtag_wb_ack - connect \jtag_wb__adr \main_libresocsim_libresoc_jtag_wb_adr - connect \jtag_wb__cyc \main_libresocsim_libresoc_jtag_wb_cyc - connect \jtag_wb__dat_r \main_libresocsim_libresoc_jtag_wb_dat_r - connect \jtag_wb__dat_w \main_libresocsim_libresoc_jtag_wb_dat_w - connect \jtag_wb__err \main_libresocsim_libresoc_jtag_wb_err - connect \jtag_wb__sel \main_libresocsim_libresoc_jtag_wb_sel - connect \jtag_wb__stb \main_libresocsim_libresoc_jtag_wb_stb - connect \jtag_wb__we \main_libresocsim_libresoc_jtag_wb_we - connect \memerr_o \main_libresocsim_libresoc1 - connect \mspi0_clk__core__o \spimaster_clk - connect \mspi0_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spimaster_clk - connect \mspi0_cs_n__core__o \spimaster_cs_n - connect \mspi0_cs_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n - connect \mspi0_miso__core__i \spimaster_miso - connect \mspi0_miso__pad__i \main_libresocsim_libresoc_constraintmanager_obj_spimaster_miso - connect \mspi0_mosi__core__o \spimaster_mosi - connect \mspi0_mosi__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spimaster_mosi - connect \mspi1_clk__core__o \spisdcard_clk - connect \mspi1_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_clk - connect \mspi1_cs_n__core__o \spisdcard_cs_n - connect \mspi1_cs_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_cs_n - connect \mspi1_miso__core__i \spisdcard_miso - connect \mspi1_miso__pad__i \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_miso - connect \mspi1_mosi__core__o \spisdcard_mosi - connect \mspi1_mosi__pad__o \main_libresocsim_libresoc_constraintmanager_obj_spisdcard_mosi - connect \mtwi_scl__core__o \i2c_scl - connect \mtwi_scl__pad__o \main_libresocsim_libresoc_constraintmanager_obj_i2c_scl - connect \mtwi_sda__core__i \i2c_sda_i - connect \mtwi_sda__core__o \i2c_sda_o - connect \mtwi_sda__core__oe \i2c_sda_oe - connect \mtwi_sda__pad__i \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i - connect \mtwi_sda__pad__o \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_o - connect \mtwi_sda__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe - connect \pc_i 1'0 - connect \pc_i_ok 1'0 - connect \pc_o \main_libresocsim_libresoc2 - connect \pll_18_o \main_libresocsim_libresoc_pll_18_o - connect \pll_lck_o \main_libresocsim_libresoc_pll_lck_o - connect \pwm_0__core__o \pwm [0] - connect \pwm_0__pad__o \pwm_1 [0] - connect \pwm_1__core__o \pwm [1] - connect \pwm_1__pad__o \pwm_1 [1] - connect \rst $or$ls180.v:10416$2851_Y - connect \sd0_clk__core__o \sdcard_clk - connect \sd0_clk__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_clk - connect \sd0_cmd__core__i \sdcard_cmd_i - connect \sd0_cmd__core__o \sdcard_cmd_o - connect \sd0_cmd__core__oe \sdcard_cmd_oe - connect \sd0_cmd__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i - connect \sd0_cmd__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_o - connect \sd0_cmd__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_oe - connect \sd0_data0__core__i \sdcard_data_i [0] - connect \sd0_data0__core__o \sdcard_data_o [0] - connect \sd0_data0__core__oe \sdcard_data_oe - connect \sd0_data0__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i [0] - connect \sd0_data0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_o [0] - connect \sd0_data0__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_oe - connect \sd0_data1__core__i \sdcard_data_i [1] - connect \sd0_data1__core__o \sdcard_data_o [1] - connect \sd0_data1__core__oe \sdcard_data_oe - connect \sd0_data1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i [1] - connect \sd0_data1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_o [1] - connect \sd0_data1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_oe - connect \sd0_data2__core__i \sdcard_data_i [2] - connect \sd0_data2__core__o \sdcard_data_o [2] - connect \sd0_data2__core__oe \sdcard_data_oe - connect \sd0_data2__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i [2] - connect \sd0_data2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_o [2] - connect \sd0_data2__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_oe - connect \sd0_data3__core__i \sdcard_data_i [3] - connect \sd0_data3__core__o \sdcard_data_o [3] - connect \sd0_data3__core__oe \sdcard_data_oe - connect \sd0_data3__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i [3] - connect \sd0_data3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_o [3] - connect \sd0_data3__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_oe - connect \sdr_a_0__core__o \sdram_a [0] - connect \sdr_a_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [0] - connect \sdr_a_10__core__o \sdram_a [10] - connect \sdr_a_10__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [10] - connect \sdr_a_11__core__o \sdram_a [11] - connect \sdr_a_11__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [11] - connect \sdr_a_12__core__o \sdram_a [12] - connect \sdr_a_12__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [12] - connect \sdr_a_1__core__o \sdram_a [1] - connect \sdr_a_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [1] - connect \sdr_a_2__core__o \sdram_a [2] - connect \sdr_a_2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [2] - connect \sdr_a_3__core__o \sdram_a [3] - connect \sdr_a_3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [3] - connect \sdr_a_4__core__o \sdram_a [4] - connect \sdr_a_4__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [4] - connect \sdr_a_5__core__o \sdram_a [5] - connect \sdr_a_5__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [5] - connect \sdr_a_6__core__o \sdram_a [6] - connect \sdr_a_6__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [6] - connect \sdr_a_7__core__o \sdram_a [7] - connect \sdr_a_7__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [7] - connect \sdr_a_8__core__o \sdram_a [8] - connect \sdr_a_8__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [8] - connect \sdr_a_9__core__o \sdram_a [9] - connect \sdr_a_9__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_a [9] - connect \sdr_ba_0__core__o \sdram_ba [0] - connect \sdr_ba_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba [0] - connect \sdr_ba_1__core__o \sdram_ba [1] - connect \sdr_ba_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_ba [1] - connect \sdr_cas_n__core__o \sdram_cas_n - connect \sdr_cas_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_cas_n - connect \sdr_cke__core__o \sdram_cke - connect \sdr_cke__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_cke - connect \sdr_clock__core__o \sdram_clock - connect \sdr_clock__pad__o \sdram_clock_1 - connect \sdr_cs_n__core__o \sdram_cs_n - connect \sdr_cs_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_cs_n - connect \sdr_dm_0__core__o \sdram_dm [0] - connect \sdr_dm_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm [0] - connect \sdr_dm_1__core__o \sdram_dm [1] - connect \sdr_dm_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dm [1] - connect \sdr_dq_0__core__i \sdram_dq_i [0] - connect \sdr_dq_0__core__o \sdram_dq_o [0] - connect \sdr_dq_0__core__oe \sdram_dq_oe - connect \sdr_dq_0__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [0] - connect \sdr_dq_0__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [0] - connect \sdr_dq_0__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_10__core__i \sdram_dq_i [10] - connect \sdr_dq_10__core__o \sdram_dq_o [10] - connect \sdr_dq_10__core__oe \sdram_dq_oe - connect \sdr_dq_10__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [10] - connect \sdr_dq_10__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [10] - connect \sdr_dq_10__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_11__core__i \sdram_dq_i [11] - connect \sdr_dq_11__core__o \sdram_dq_o [11] - connect \sdr_dq_11__core__oe \sdram_dq_oe - connect \sdr_dq_11__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [11] - connect \sdr_dq_11__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [11] - connect \sdr_dq_11__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_12__core__i \sdram_dq_i [12] - connect \sdr_dq_12__core__o \sdram_dq_o [12] - connect \sdr_dq_12__core__oe \sdram_dq_oe - connect \sdr_dq_12__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [12] - connect \sdr_dq_12__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [12] - connect \sdr_dq_12__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_13__core__i \sdram_dq_i [13] - connect \sdr_dq_13__core__o \sdram_dq_o [13] - connect \sdr_dq_13__core__oe \sdram_dq_oe - connect \sdr_dq_13__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [13] - connect \sdr_dq_13__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [13] - connect \sdr_dq_13__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_14__core__i \sdram_dq_i [14] - connect \sdr_dq_14__core__o \sdram_dq_o [14] - connect \sdr_dq_14__core__oe \sdram_dq_oe - connect \sdr_dq_14__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [14] - connect \sdr_dq_14__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [14] - connect \sdr_dq_14__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_15__core__i \sdram_dq_i [15] - connect \sdr_dq_15__core__o \sdram_dq_o [15] - connect \sdr_dq_15__core__oe \sdram_dq_oe - connect \sdr_dq_15__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [15] - connect \sdr_dq_15__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [15] - connect \sdr_dq_15__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_1__core__i \sdram_dq_i [1] - connect \sdr_dq_1__core__o \sdram_dq_o [1] - connect \sdr_dq_1__core__oe \sdram_dq_oe - connect \sdr_dq_1__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [1] - connect \sdr_dq_1__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [1] - connect \sdr_dq_1__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_2__core__i \sdram_dq_i [2] - connect \sdr_dq_2__core__o \sdram_dq_o [2] - connect \sdr_dq_2__core__oe \sdram_dq_oe - connect \sdr_dq_2__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [2] - connect \sdr_dq_2__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [2] - connect \sdr_dq_2__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_3__core__i \sdram_dq_i [3] - connect \sdr_dq_3__core__o \sdram_dq_o [3] - connect \sdr_dq_3__core__oe \sdram_dq_oe - connect \sdr_dq_3__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [3] - connect \sdr_dq_3__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [3] - connect \sdr_dq_3__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_4__core__i \sdram_dq_i [4] - connect \sdr_dq_4__core__o \sdram_dq_o [4] - connect \sdr_dq_4__core__oe \sdram_dq_oe - connect \sdr_dq_4__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [4] - connect \sdr_dq_4__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [4] - connect \sdr_dq_4__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_5__core__i \sdram_dq_i [5] - connect \sdr_dq_5__core__o \sdram_dq_o [5] - connect \sdr_dq_5__core__oe \sdram_dq_oe - connect \sdr_dq_5__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [5] - connect \sdr_dq_5__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [5] - connect \sdr_dq_5__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_6__core__i \sdram_dq_i [6] - connect \sdr_dq_6__core__o \sdram_dq_o [6] - connect \sdr_dq_6__core__oe \sdram_dq_oe - connect \sdr_dq_6__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [6] - connect \sdr_dq_6__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [6] - connect \sdr_dq_6__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_7__core__i \sdram_dq_i [7] - connect \sdr_dq_7__core__o \sdram_dq_o [7] - connect \sdr_dq_7__core__oe \sdram_dq_oe - connect \sdr_dq_7__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [7] - connect \sdr_dq_7__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [7] - connect \sdr_dq_7__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_8__core__i \sdram_dq_i [8] - connect \sdr_dq_8__core__o \sdram_dq_o [8] - connect \sdr_dq_8__core__oe \sdram_dq_oe - connect \sdr_dq_8__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [8] - connect \sdr_dq_8__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [8] - connect \sdr_dq_8__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_dq_9__core__i \sdram_dq_i [9] - connect \sdr_dq_9__core__o \sdram_dq_o [9] - connect \sdr_dq_9__core__oe \sdram_dq_oe - connect \sdr_dq_9__pad__i \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [9] - connect \sdr_dq_9__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_o [9] - connect \sdr_dq_9__pad__oe \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe - connect \sdr_ras_n__core__o \sdram_ras_n - connect \sdr_ras_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_ras_n - connect \sdr_we_n__core__o \sdram_we_n - connect \sdr_we_n__pad__o \main_libresocsim_libresoc_constraintmanager_obj_sdram_we_n - end - attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$3832 - sync always - sync init - end - attribute \src "ls180.v:0.0-0.0" - process $proc$ls180.v:0$3833 - sync always - sync init - end - attribute \src "ls180.v:100.11-100.56" - process $proc$ls180.v:100$2894 - assign { } { } - assign $1\main_libresocsim_libresoc_xics_ics_sel[3:0] 4'0000 - sync always - sync init - update \main_libresocsim_libresoc_xics_ics_sel $1\main_libresocsim_libresoc_xics_ics_sel[3:0] - end - attribute \src "ls180.v:1002.12-1002.53" - process $proc$ls180.v:1002$3242 - assign { } { } - assign $1\main_gpiotristateasic1_oe_storage[15:0] 16'0000000000000000 - sync always - sync init - update \main_gpiotristateasic1_oe_storage $1\main_gpiotristateasic1_oe_storage[15:0] - end - attribute \src "ls180.v:1003.5-1003.40" - process $proc$ls180.v:1003$3243 - assign { } { } - assign $1\main_gpiotristateasic1_oe_re[0:0] 1'0 - sync always - sync init - update \main_gpiotristateasic1_oe_re $1\main_gpiotristateasic1_oe_re[0:0] - end - attribute \src "ls180.v:1004.12-1004.49" - process $proc$ls180.v:1004$3244 - assign { } { } - assign $1\main_gpiotristateasic1_status[15:0] 16'0000000000000000 - sync always - sync init - update \main_gpiotristateasic1_status $1\main_gpiotristateasic1_status[15:0] - end - attribute \src "ls180.v:1006.12-1006.54" - process $proc$ls180.v:1006$3245 - assign { } { } - assign $1\main_gpiotristateasic1_out_storage[15:0] 16'0000000000000000 - sync always - sync init - update \main_gpiotristateasic1_out_storage $1\main_gpiotristateasic1_out_storage[15:0] - end - attribute \src "ls180.v:1007.5-1007.41" - process $proc$ls180.v:1007$3246 - assign { } { } - assign $1\main_gpiotristateasic1_out_re[0:0] 1'0 - sync always - sync init - update \main_gpiotristateasic1_out_re $1\main_gpiotristateasic1_out_re[0:0] - end - attribute \src "ls180.v:101.5-101.50" - process $proc$ls180.v:101$2895 - assign { } { } - assign $1\main_libresocsim_libresoc_xics_ics_cyc[0:0] 1'0 - sync always - sync init - update \main_libresocsim_libresoc_xics_ics_cyc $1\main_libresocsim_libresoc_xics_ics_cyc[0:0] - end - attribute \src "ls180.v:1013.5-1013.32" - process $proc$ls180.v:1013$3247 - assign { } { } - assign $1\main_spimaster2_done[0:0] 1'0 - sync always - sync init - update \main_spimaster2_done $1\main_spimaster2_done[0:0] - end - attribute \src "ls180.v:1014.5-1014.31" - process $proc$ls180.v:1014$3248 - assign { } { } - assign $1\main_spimaster3_irq[0:0] 1'0 - sync always - sync init - update \main_spimaster3_irq $1\main_spimaster3_irq[0:0] - end - attribute \src "ls180.v:10144.1-10162.4" - process $proc$ls180.v:10144$2743 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\mem$ls180.v:10160$8_ADDR[5:0]$2765 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10160$8_DATA[63:0]$2766 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10160$8_EN[63:0]$2767 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10158$7_ADDR[5:0]$2762 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10158$7_DATA[63:0]$2763 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10158$7_EN[63:0]$2764 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10156$6_ADDR[5:0]$2759 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10156$6_DATA[63:0]$2760 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10156$6_EN[63:0]$2761 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10154$5_ADDR[5:0]$2756 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10154$5_DATA[63:0]$2757 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10154$5_EN[63:0]$2758 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10152$4_ADDR[5:0]$2753 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10152$4_DATA[63:0]$2754 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10152$4_EN[63:0]$2755 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10150$3_ADDR[5:0]$2750 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10150$3_DATA[63:0]$2751 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10150$3_EN[63:0]$2752 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10148$2_ADDR[5:0]$2747 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10148$2_DATA[63:0]$2748 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10148$2_EN[63:0]$2749 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem$ls180.v:10146$1_ADDR[5:0]$2744 6'xxxxxx - assign $0$memwr$\mem$ls180.v:10146$1_DATA[63:0]$2745 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem$ls180.v:10146$1_EN[63:0]$2746 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\memadr[5:0] \main_libresocsim_adr - attribute \src "ls180.v:10145.2-10146.65" - switch \main_libresocsim_we [0] - attribute \src "ls180.v:10145.6-10145.28" - case 1'1 - assign $0$memwr$\mem$ls180.v:10146$1_ADDR[5:0]$2744 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10146$1_DATA[63:0]$2745 { 56'00000000000000000000000000000000000000000000000000000000 \main_libresocsim_dat_w [7:0] } - assign $0$memwr$\mem$ls180.v:10146$1_EN[63:0]$2746 64'0000000000000000000000000000000000000000000000000000000011111111 - case - end - attribute \src "ls180.v:10147.2-10148.67" - switch \main_libresocsim_we [1] - attribute \src "ls180.v:10147.6-10147.28" - case 1'1 - assign $0$memwr$\mem$ls180.v:10148$2_ADDR[5:0]$2747 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10148$2_DATA[63:0]$2748 { 48'000000000000000000000000000000000000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem$ls180.v:10148$2_EN[63:0]$2749 64'0000000000000000000000000000000000000000000000001111111100000000 - case - end - attribute \src "ls180.v:10149.2-10150.69" - switch \main_libresocsim_we [2] - attribute \src "ls180.v:10149.6-10149.28" - case 1'1 - assign $0$memwr$\mem$ls180.v:10150$3_ADDR[5:0]$2750 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10150$3_DATA[63:0]$2751 { 40'0000000000000000000000000000000000000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10150$3_EN[63:0]$2752 64'0000000000000000000000000000000000000000111111110000000000000000 - case - end - attribute \src "ls180.v:10151.2-10152.69" - switch \main_libresocsim_we [3] - attribute \src "ls180.v:10151.6-10151.28" - case 1'1 - assign $0$memwr$\mem$ls180.v:10152$4_ADDR[5:0]$2753 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10152$4_DATA[63:0]$2754 { 32'00000000000000000000000000000000 \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10152$4_EN[63:0]$2755 64'0000000000000000000000000000000011111111000000000000000000000000 - case - end - attribute \src "ls180.v:10153.2-10154.69" - switch \main_libresocsim_we [4] - attribute \src "ls180.v:10153.6-10153.28" - case 1'1 - assign $0$memwr$\mem$ls180.v:10154$5_ADDR[5:0]$2756 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10154$5_DATA[63:0]$2757 { 24'000000000000000000000000 \main_libresocsim_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10154$5_EN[63:0]$2758 64'0000000000000000000000001111111100000000000000000000000000000000 - case - end - attribute \src "ls180.v:10155.2-10156.69" - switch \main_libresocsim_we [5] - attribute \src "ls180.v:10155.6-10155.28" - case 1'1 - assign $0$memwr$\mem$ls180.v:10156$6_ADDR[5:0]$2759 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10156$6_DATA[63:0]$2760 { 16'0000000000000000 \main_libresocsim_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10156$6_EN[63:0]$2761 64'0000000000000000111111110000000000000000000000000000000000000000 - case - end - attribute \src "ls180.v:10157.2-10158.69" - switch \main_libresocsim_we [6] - attribute \src "ls180.v:10157.6-10157.28" - case 1'1 - assign $0$memwr$\mem$ls180.v:10158$7_ADDR[5:0]$2762 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10158$7_DATA[63:0]$2763 { 8'00000000 \main_libresocsim_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10158$7_EN[63:0]$2764 64'0000000011111111000000000000000000000000000000000000000000000000 - case - end - attribute \src "ls180.v:10159.2-10160.69" - switch \main_libresocsim_we [7] - attribute \src "ls180.v:10159.6-10159.28" - case 1'1 - assign $0$memwr$\mem$ls180.v:10160$8_ADDR[5:0]$2765 \main_libresocsim_adr - assign $0$memwr$\mem$ls180.v:10160$8_DATA[63:0]$2766 { \main_libresocsim_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem$ls180.v:10160$8_EN[63:0]$2767 64'1111111100000000000000000000000000000000000000000000000000000000 - case - end - sync posedge \sys_clk_1 - update \memadr $0\memadr[5:0] - update $memwr$\mem$ls180.v:10146$1_ADDR $0$memwr$\mem$ls180.v:10146$1_ADDR[5:0]$2744 - update $memwr$\mem$ls180.v:10146$1_DATA $0$memwr$\mem$ls180.v:10146$1_DATA[63:0]$2745 - update $memwr$\mem$ls180.v:10146$1_EN $0$memwr$\mem$ls180.v:10146$1_EN[63:0]$2746 - update $memwr$\mem$ls180.v:10148$2_ADDR $0$memwr$\mem$ls180.v:10148$2_ADDR[5:0]$2747 - update $memwr$\mem$ls180.v:10148$2_DATA $0$memwr$\mem$ls180.v:10148$2_DATA[63:0]$2748 - update $memwr$\mem$ls180.v:10148$2_EN $0$memwr$\mem$ls180.v:10148$2_EN[63:0]$2749 - update $memwr$\mem$ls180.v:10150$3_ADDR $0$memwr$\mem$ls180.v:10150$3_ADDR[5:0]$2750 - update $memwr$\mem$ls180.v:10150$3_DATA $0$memwr$\mem$ls180.v:10150$3_DATA[63:0]$2751 - update $memwr$\mem$ls180.v:10150$3_EN $0$memwr$\mem$ls180.v:10150$3_EN[63:0]$2752 - update $memwr$\mem$ls180.v:10152$4_ADDR $0$memwr$\mem$ls180.v:10152$4_ADDR[5:0]$2753 - update $memwr$\mem$ls180.v:10152$4_DATA $0$memwr$\mem$ls180.v:10152$4_DATA[63:0]$2754 - update $memwr$\mem$ls180.v:10152$4_EN $0$memwr$\mem$ls180.v:10152$4_EN[63:0]$2755 - update $memwr$\mem$ls180.v:10154$5_ADDR $0$memwr$\mem$ls180.v:10154$5_ADDR[5:0]$2756 - update $memwr$\mem$ls180.v:10154$5_DATA $0$memwr$\mem$ls180.v:10154$5_DATA[63:0]$2757 - update $memwr$\mem$ls180.v:10154$5_EN $0$memwr$\mem$ls180.v:10154$5_EN[63:0]$2758 - update $memwr$\mem$ls180.v:10156$6_ADDR $0$memwr$\mem$ls180.v:10156$6_ADDR[5:0]$2759 - update $memwr$\mem$ls180.v:10156$6_DATA $0$memwr$\mem$ls180.v:10156$6_DATA[63:0]$2760 - update $memwr$\mem$ls180.v:10156$6_EN $0$memwr$\mem$ls180.v:10156$6_EN[63:0]$2761 - update $memwr$\mem$ls180.v:10158$7_ADDR $0$memwr$\mem$ls180.v:10158$7_ADDR[5:0]$2762 - update $memwr$\mem$ls180.v:10158$7_DATA $0$memwr$\mem$ls180.v:10158$7_DATA[63:0]$2763 - update $memwr$\mem$ls180.v:10158$7_EN $0$memwr$\mem$ls180.v:10158$7_EN[63:0]$2764 - update $memwr$\mem$ls180.v:10160$8_ADDR $0$memwr$\mem$ls180.v:10160$8_ADDR[5:0]$2765 - update $memwr$\mem$ls180.v:10160$8_DATA $0$memwr$\mem$ls180.v:10160$8_DATA[63:0]$2766 - update $memwr$\mem$ls180.v:10160$8_EN $0$memwr$\mem$ls180.v:10160$8_EN[63:0]$2767 - end - attribute \src "ls180.v:1016.11-1016.38" - process $proc$ls180.v:1016$3249 - assign { } { } - assign $1\main_spimaster5_miso[7:0] 8'00000000 - sync always - sync init - update \main_spimaster5_miso $1\main_spimaster5_miso[7:0] - end - attribute \src "ls180.v:10172.1-10190.4" - process $proc$ls180.v:10172$2769 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\mem_1$ls180.v:10188$16_ADDR[3:0]$2791 4'xxxx - assign $0$memwr$\mem_1$ls180.v:10188$16_DATA[63:0]$2792 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10188$16_EN[63:0]$2793 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10186$15_ADDR[3:0]$2788 4'xxxx - assign $0$memwr$\mem_1$ls180.v:10186$15_DATA[63:0]$2789 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10186$15_EN[63:0]$2790 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10184$14_ADDR[3:0]$2785 4'xxxx - assign $0$memwr$\mem_1$ls180.v:10184$14_DATA[63:0]$2786 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10184$14_EN[63:0]$2787 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10182$13_ADDR[3:0]$2782 4'xxxx - assign $0$memwr$\mem_1$ls180.v:10182$13_DATA[63:0]$2783 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10182$13_EN[63:0]$2784 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10180$12_ADDR[3:0]$2779 4'xxxx - assign $0$memwr$\mem_1$ls180.v:10180$12_DATA[63:0]$2780 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10180$12_EN[63:0]$2781 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10178$11_ADDR[3:0]$2776 4'xxxx - assign $0$memwr$\mem_1$ls180.v:10178$11_DATA[63:0]$2777 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10178$11_EN[63:0]$2778 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10176$10_ADDR[3:0]$2773 4'xxxx - assign $0$memwr$\mem_1$ls180.v:10176$10_DATA[63:0]$2774 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10176$10_EN[63:0]$2775 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0$memwr$\mem_1$ls180.v:10174$9_ADDR[3:0]$2770 4'xxxx - assign $0$memwr$\mem_1$ls180.v:10174$9_DATA[63:0]$2771 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\mem_1$ls180.v:10174$9_EN[63:0]$2772 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\memadr_1[3:0] \main_ram_adr - attribute \src "ls180.v:10173.2-10174.51" - switch \main_ram_we [0] - attribute \src "ls180.v:10173.6-10173.20" - case 1'1 - assign $0$memwr$\mem_1$ls180.v:10174$9_ADDR[3:0]$2770 \main_ram_adr - assign $0$memwr$\mem_1$ls180.v:10174$9_DATA[63:0]$2771 { 56'00000000000000000000000000000000000000000000000000000000 \main_ram_dat_w [7:0] } - assign $0$memwr$\mem_1$ls180.v:10174$9_EN[63:0]$2772 64'0000000000000000000000000000000000000000000000000000000011111111 - case - end - attribute \src "ls180.v:10175.2-10176.53" - switch \main_ram_we [1] - attribute \src "ls180.v:10175.6-10175.20" - case 1'1 - assign $0$memwr$\mem_1$ls180.v:10176$10_ADDR[3:0]$2773 \main_ram_adr - assign $0$memwr$\mem_1$ls180.v:10176$10_DATA[63:0]$2774 { 48'000000000000000000000000000000000000000000000000 \main_ram_dat_w [15:8] 8'xxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10176$10_EN[63:0]$2775 64'0000000000000000000000000000000000000000000000001111111100000000 - case - end - attribute \src "ls180.v:10177.2-10178.55" - switch \main_ram_we [2] - attribute \src "ls180.v:10177.6-10177.20" - case 1'1 - assign $0$memwr$\mem_1$ls180.v:10178$11_ADDR[3:0]$2776 \main_ram_adr - assign $0$memwr$\mem_1$ls180.v:10178$11_DATA[63:0]$2777 { 40'0000000000000000000000000000000000000000 \main_ram_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10178$11_EN[63:0]$2778 64'0000000000000000000000000000000000000000111111110000000000000000 - case - end - attribute \src "ls180.v:10179.2-10180.55" - switch \main_ram_we [3] - attribute \src "ls180.v:10179.6-10179.20" - case 1'1 - assign $0$memwr$\mem_1$ls180.v:10180$12_ADDR[3:0]$2779 \main_ram_adr - assign $0$memwr$\mem_1$ls180.v:10180$12_DATA[63:0]$2780 { 32'00000000000000000000000000000000 \main_ram_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10180$12_EN[63:0]$2781 64'0000000000000000000000000000000011111111000000000000000000000000 - case - end - attribute \src "ls180.v:10181.2-10182.55" - switch \main_ram_we [4] - attribute \src "ls180.v:10181.6-10181.20" - case 1'1 - assign $0$memwr$\mem_1$ls180.v:10182$13_ADDR[3:0]$2782 \main_ram_adr - assign $0$memwr$\mem_1$ls180.v:10182$13_DATA[63:0]$2783 { 24'000000000000000000000000 \main_ram_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10182$13_EN[63:0]$2784 64'0000000000000000000000001111111100000000000000000000000000000000 - case - end - attribute \src "ls180.v:10183.2-10184.55" - switch \main_ram_we [5] - attribute \src "ls180.v:10183.6-10183.20" - case 1'1 - assign $0$memwr$\mem_1$ls180.v:10184$14_ADDR[3:0]$2785 \main_ram_adr - assign $0$memwr$\mem_1$ls180.v:10184$14_DATA[63:0]$2786 { 16'0000000000000000 \main_ram_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10184$14_EN[63:0]$2787 64'0000000000000000111111110000000000000000000000000000000000000000 - case - end - attribute \src "ls180.v:10185.2-10186.55" - switch \main_ram_we [6] - attribute \src "ls180.v:10185.6-10185.20" - case 1'1 - assign $0$memwr$\mem_1$ls180.v:10186$15_ADDR[3:0]$2788 \main_ram_adr - assign $0$memwr$\mem_1$ls180.v:10186$15_DATA[63:0]$2789 { 8'00000000 \main_ram_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10186$15_EN[63:0]$2790 64'0000000011111111000000000000000000000000000000000000000000000000 - case - end - attribute \src "ls180.v:10187.2-10188.55" - switch \main_ram_we [7] - attribute \src "ls180.v:10187.6-10187.20" - case 1'1 - assign $0$memwr$\mem_1$ls180.v:10188$16_ADDR[3:0]$2791 \main_ram_adr - assign $0$memwr$\mem_1$ls180.v:10188$16_DATA[63:0]$2792 { \main_ram_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } - assign $0$memwr$\mem_1$ls180.v:10188$16_EN[63:0]$2793 64'1111111100000000000000000000000000000000000000000000000000000000 - case - end - sync posedge \sys_clk_1 - update \memadr_1 $0\memadr_1[3:0] - update $memwr$\mem_1$ls180.v:10174$9_ADDR $0$memwr$\mem_1$ls180.v:10174$9_ADDR[3:0]$2770 - update $memwr$\mem_1$ls180.v:10174$9_DATA $0$memwr$\mem_1$ls180.v:10174$9_DATA[63:0]$2771 - update $memwr$\mem_1$ls180.v:10174$9_EN $0$memwr$\mem_1$ls180.v:10174$9_EN[63:0]$2772 - update $memwr$\mem_1$ls180.v:10176$10_ADDR $0$memwr$\mem_1$ls180.v:10176$10_ADDR[3:0]$2773 - update $memwr$\mem_1$ls180.v:10176$10_DATA $0$memwr$\mem_1$ls180.v:10176$10_DATA[63:0]$2774 - update $memwr$\mem_1$ls180.v:10176$10_EN $0$memwr$\mem_1$ls180.v:10176$10_EN[63:0]$2775 - update $memwr$\mem_1$ls180.v:10178$11_ADDR $0$memwr$\mem_1$ls180.v:10178$11_ADDR[3:0]$2776 - update $memwr$\mem_1$ls180.v:10178$11_DATA $0$memwr$\mem_1$ls180.v:10178$11_DATA[63:0]$2777 - update $memwr$\mem_1$ls180.v:10178$11_EN $0$memwr$\mem_1$ls180.v:10178$11_EN[63:0]$2778 - update $memwr$\mem_1$ls180.v:10180$12_ADDR $0$memwr$\mem_1$ls180.v:10180$12_ADDR[3:0]$2779 - update $memwr$\mem_1$ls180.v:10180$12_DATA $0$memwr$\mem_1$ls180.v:10180$12_DATA[63:0]$2780 - update $memwr$\mem_1$ls180.v:10180$12_EN $0$memwr$\mem_1$ls180.v:10180$12_EN[63:0]$2781 - update $memwr$\mem_1$ls180.v:10182$13_ADDR $0$memwr$\mem_1$ls180.v:10182$13_ADDR[3:0]$2782 - update $memwr$\mem_1$ls180.v:10182$13_DATA $0$memwr$\mem_1$ls180.v:10182$13_DATA[63:0]$2783 - update $memwr$\mem_1$ls180.v:10182$13_EN $0$memwr$\mem_1$ls180.v:10182$13_EN[63:0]$2784 - update $memwr$\mem_1$ls180.v:10184$14_ADDR $0$memwr$\mem_1$ls180.v:10184$14_ADDR[3:0]$2785 - update $memwr$\mem_1$ls180.v:10184$14_DATA $0$memwr$\mem_1$ls180.v:10184$14_DATA[63:0]$2786 - update $memwr$\mem_1$ls180.v:10184$14_EN $0$memwr$\mem_1$ls180.v:10184$14_EN[63:0]$2787 - update $memwr$\mem_1$ls180.v:10186$15_ADDR $0$memwr$\mem_1$ls180.v:10186$15_ADDR[3:0]$2788 - update $memwr$\mem_1$ls180.v:10186$15_DATA $0$memwr$\mem_1$ls180.v:10186$15_DATA[63:0]$2789 - update $memwr$\mem_1$ls180.v:10186$15_EN $0$memwr$\mem_1$ls180.v:10186$15_EN[63:0]$2790 - update $memwr$\mem_1$ls180.v:10188$16_ADDR $0$memwr$\mem_1$ls180.v:10188$16_ADDR[3:0]$2791 - update $memwr$\mem_1$ls180.v:10188$16_DATA $0$memwr$\mem_1$ls180.v:10188$16_DATA[63:0]$2792 - update $memwr$\mem_1$ls180.v:10188$16_EN $0$memwr$\mem_1$ls180.v:10188$16_EN[63:0]$2793 - end - attribute \src "ls180.v:1019.12-1019.47" - process $proc$ls180.v:1019$3250 - assign { } { } - assign $0\main_spimaster8_clk_divider[15:0] 16'0000000000000111 - sync always - update \main_spimaster8_clk_divider $0\main_spimaster8_clk_divider[15:0] - sync init - end - attribute \src "ls180.v:102.5-102.50" - process $proc$ls180.v:102$2896 - assign { } { } - assign $1\main_libresocsim_libresoc_xics_ics_stb[0:0] 1'0 - sync always - sync init - update \main_libresocsim_libresoc_xics_ics_stb $1\main_libresocsim_libresoc_xics_ics_stb[0:0] - end - attribute \src "ls180.v:1020.5-1020.33" - process $proc$ls180.v:1020$3251 - assign { } { } - assign $1\main_spimaster9_start[0:0] 1'0 - sync always - sync init - update \main_spimaster9_start $1\main_spimaster9_start[0:0] - end - attribute \src "ls180.v:10200.1-10204.4" - process $proc$ls180.v:10200$2795 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage$ls180.v:10202$17_ADDR[2:0]$2796 3'xxx - assign $0$memwr$\storage$ls180.v:10202$17_DATA[24:0]$2797 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage$ls180.v:10202$17_EN[24:0]$2798 25'0000000000000000000000000 - assign $0\memdat[24:0] $memrd$\storage$ls180.v:10203$2799_DATA - attribute \src "ls180.v:10201.2-10202.129" - switch \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10201.6-10201.60" - case 1'1 - assign $0$memwr$\storage$ls180.v:10202$17_ADDR[2:0]$2796 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage$ls180.v:10202$17_DATA[24:0]$2797 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage$ls180.v:10202$17_EN[24:0]$2798 25'1111111111111111111111111 - case - end - sync posedge \sys_clk_1 - update \memdat $0\memdat[24:0] - update $memwr$\storage$ls180.v:10202$17_ADDR $0$memwr$\storage$ls180.v:10202$17_ADDR[2:0]$2796 - update $memwr$\storage$ls180.v:10202$17_DATA $0$memwr$\storage$ls180.v:10202$17_DATA[24:0]$2797 - update $memwr$\storage$ls180.v:10202$17_EN $0$memwr$\storage$ls180.v:10202$17_EN[24:0]$2798 - end - attribute \src "ls180.v:10206.1-10207.4" - process $proc$ls180.v:10206$2800 - sync posedge \sys_clk_1 - end - attribute \src "ls180.v:10214.1-10218.4" - process $proc$ls180.v:10214$2802 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage_1$ls180.v:10216$18_ADDR[2:0]$2803 3'xxx - assign $0$memwr$\storage_1$ls180.v:10216$18_DATA[24:0]$2804 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_1$ls180.v:10216$18_EN[24:0]$2805 25'0000000000000000000000000 - assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:10217$2806_DATA - attribute \src "ls180.v:10215.2-10216.131" - switch \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10215.6-10215.60" - case 1'1 - assign $0$memwr$\storage_1$ls180.v:10216$18_ADDR[2:0]$2803 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_1$ls180.v:10216$18_DATA[24:0]$2804 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_1$ls180.v:10216$18_EN[24:0]$2805 25'1111111111111111111111111 - case - end - sync posedge \sys_clk_1 - update \memdat_1 $0\memdat_1[24:0] - update $memwr$\storage_1$ls180.v:10216$18_ADDR $0$memwr$\storage_1$ls180.v:10216$18_ADDR[2:0]$2803 - update $memwr$\storage_1$ls180.v:10216$18_DATA $0$memwr$\storage_1$ls180.v:10216$18_DATA[24:0]$2804 - update $memwr$\storage_1$ls180.v:10216$18_EN $0$memwr$\storage_1$ls180.v:10216$18_EN[24:0]$2805 - end - attribute \src "ls180.v:1022.12-1022.44" - process $proc$ls180.v:1022$3252 - assign { } { } - assign $1\main_spimaster11_storage[15:0] 16'0000000000000000 - sync always - sync init - update \main_spimaster11_storage $1\main_spimaster11_storage[15:0] - end - attribute \src "ls180.v:10220.1-10221.4" - process $proc$ls180.v:10220$2807 - sync posedge \sys_clk_1 - end - attribute \src "ls180.v:10228.1-10232.4" - process $proc$ls180.v:10228$2809 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage_2$ls180.v:10230$19_ADDR[2:0]$2810 3'xxx - assign $0$memwr$\storage_2$ls180.v:10230$19_DATA[24:0]$2811 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_2$ls180.v:10230$19_EN[24:0]$2812 25'0000000000000000000000000 - assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:10231$2813_DATA - attribute \src "ls180.v:10229.2-10230.131" - switch \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10229.6-10229.60" - case 1'1 - assign $0$memwr$\storage_2$ls180.v:10230$19_ADDR[2:0]$2810 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_2$ls180.v:10230$19_DATA[24:0]$2811 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_2$ls180.v:10230$19_EN[24:0]$2812 25'1111111111111111111111111 - case - end - sync posedge \sys_clk_1 - update \memdat_2 $0\memdat_2[24:0] - update $memwr$\storage_2$ls180.v:10230$19_ADDR $0$memwr$\storage_2$ls180.v:10230$19_ADDR[2:0]$2810 - update $memwr$\storage_2$ls180.v:10230$19_DATA $0$memwr$\storage_2$ls180.v:10230$19_DATA[24:0]$2811 - update $memwr$\storage_2$ls180.v:10230$19_EN $0$memwr$\storage_2$ls180.v:10230$19_EN[24:0]$2812 - end - attribute \src "ls180.v:1023.5-1023.31" - process $proc$ls180.v:1023$3253 - assign { } { } - assign $1\main_spimaster12_re[0:0] 1'0 - sync always - sync init - update \main_spimaster12_re $1\main_spimaster12_re[0:0] - end - attribute \src "ls180.v:10234.1-10235.4" - process $proc$ls180.v:10234$2814 - sync posedge \sys_clk_1 - end - attribute \src "ls180.v:10242.1-10246.4" - process $proc$ls180.v:10242$2816 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage_3$ls180.v:10244$20_ADDR[2:0]$2817 3'xxx - assign $0$memwr$\storage_3$ls180.v:10244$20_DATA[24:0]$2818 25'xxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\storage_3$ls180.v:10244$20_EN[24:0]$2819 25'0000000000000000000000000 - assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:10245$2820_DATA - attribute \src "ls180.v:10243.2-10244.131" - switch \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we - attribute \src "ls180.v:10243.6-10243.60" - case 1'1 - assign $0$memwr$\storage_3$ls180.v:10244$20_ADDR[2:0]$2817 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr - assign $0$memwr$\storage_3$ls180.v:10244$20_DATA[24:0]$2818 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w - assign $0$memwr$\storage_3$ls180.v:10244$20_EN[24:0]$2819 25'1111111111111111111111111 - case - end - sync posedge \sys_clk_1 - update \memdat_3 $0\memdat_3[24:0] - update $memwr$\storage_3$ls180.v:10244$20_ADDR $0$memwr$\storage_3$ls180.v:10244$20_ADDR[2:0]$2817 - update $memwr$\storage_3$ls180.v:10244$20_DATA $0$memwr$\storage_3$ls180.v:10244$20_DATA[24:0]$2818 - update $memwr$\storage_3$ls180.v:10244$20_EN $0$memwr$\storage_3$ls180.v:10244$20_EN[24:0]$2819 - end - attribute \src "ls180.v:10248.1-10249.4" - process $proc$ls180.v:10248$2821 - sync posedge \sys_clk_1 - end - attribute \src "ls180.v:10257.1-10261.4" - process $proc$ls180.v:10257$2823 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage_4$ls180.v:10259$21_ADDR[3:0]$2824 4'xxxx - assign $0$memwr$\storage_4$ls180.v:10259$21_DATA[9:0]$2825 10'xxxxxxxxxx - assign $0$memwr$\storage_4$ls180.v:10259$21_EN[9:0]$2826 10'0000000000 - assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:10260$2827_DATA - attribute \src "ls180.v:10258.2-10259.77" - switch \main_uart_tx_fifo_wrport_we - attribute \src "ls180.v:10258.6-10258.33" - case 1'1 - assign $0$memwr$\storage_4$ls180.v:10259$21_ADDR[3:0]$2824 \main_uart_tx_fifo_wrport_adr - assign $0$memwr$\storage_4$ls180.v:10259$21_DATA[9:0]$2825 \main_uart_tx_fifo_wrport_dat_w - assign $0$memwr$\storage_4$ls180.v:10259$21_EN[9:0]$2826 10'1111111111 - case - end - sync posedge \sys_clk_1 - update \memdat_4 $0\memdat_4[9:0] - update $memwr$\storage_4$ls180.v:10259$21_ADDR $0$memwr$\storage_4$ls180.v:10259$21_ADDR[3:0]$2824 - update $memwr$\storage_4$ls180.v:10259$21_DATA $0$memwr$\storage_4$ls180.v:10259$21_DATA[9:0]$2825 - update $memwr$\storage_4$ls180.v:10259$21_EN $0$memwr$\storage_4$ls180.v:10259$21_EN[9:0]$2826 - end - attribute \src "ls180.v:10263.1-10266.4" - process $proc$ls180.v:10263$2828 - assign $0\memdat_5[9:0] \memdat_5 - attribute \src "ls180.v:10264.2-10265.55" - switch \main_uart_tx_fifo_rdport_re - attribute \src "ls180.v:10264.6-10264.33" - case 1'1 - assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:10265$2829_DATA - case - end - sync posedge \sys_clk_1 - update \memdat_5 $0\memdat_5[9:0] - end - attribute \src "ls180.v:1027.11-1027.42" - process $proc$ls180.v:1027$3254 - assign { } { } - assign $1\main_spimaster16_storage[7:0] 8'00000000 - sync always - sync init - update \main_spimaster16_storage $1\main_spimaster16_storage[7:0] - end - attribute \src "ls180.v:10274.1-10278.4" - process $proc$ls180.v:10274$2830 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage_5$ls180.v:10276$22_ADDR[3:0]$2831 4'xxxx - assign $0$memwr$\storage_5$ls180.v:10276$22_DATA[9:0]$2832 10'xxxxxxxxxx - assign $0$memwr$\storage_5$ls180.v:10276$22_EN[9:0]$2833 10'0000000000 - assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:10277$2834_DATA - attribute \src "ls180.v:10275.2-10276.77" - switch \main_uart_rx_fifo_wrport_we - attribute \src "ls180.v:10275.6-10275.33" - case 1'1 - assign $0$memwr$\storage_5$ls180.v:10276$22_ADDR[3:0]$2831 \main_uart_rx_fifo_wrport_adr - assign $0$memwr$\storage_5$ls180.v:10276$22_DATA[9:0]$2832 \main_uart_rx_fifo_wrport_dat_w - assign $0$memwr$\storage_5$ls180.v:10276$22_EN[9:0]$2833 10'1111111111 - case - end - sync posedge \sys_clk_1 - update \memdat_6 $0\memdat_6[9:0] - update $memwr$\storage_5$ls180.v:10276$22_ADDR $0$memwr$\storage_5$ls180.v:10276$22_ADDR[3:0]$2831 - update $memwr$\storage_5$ls180.v:10276$22_DATA $0$memwr$\storage_5$ls180.v:10276$22_DATA[9:0]$2832 - update $memwr$\storage_5$ls180.v:10276$22_EN $0$memwr$\storage_5$ls180.v:10276$22_EN[9:0]$2833 - end - attribute \src "ls180.v:1028.5-1028.31" - process $proc$ls180.v:1028$3255 - assign { } { } - assign $1\main_spimaster17_re[0:0] 1'0 - sync always - sync init - update \main_spimaster17_re $1\main_spimaster17_re[0:0] - end - attribute \src "ls180.v:10280.1-10283.4" - process $proc$ls180.v:10280$2835 - assign $0\memdat_7[9:0] \memdat_7 - attribute \src "ls180.v:10281.2-10282.55" - switch \main_uart_rx_fifo_rdport_re - attribute \src "ls180.v:10281.6-10281.33" - case 1'1 - assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:10282$2836_DATA - case - end - sync posedge \sys_clk_1 - update \memdat_7 $0\memdat_7[9:0] - end - attribute \src "ls180.v:10290.1-10294.4" - process $proc$ls180.v:10290$2837 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage_6$ls180.v:10292$23_ADDR[4:0]$2838 5'xxxxx - assign $0$memwr$\storage_6$ls180.v:10292$23_DATA[9:0]$2839 10'xxxxxxxxxx - assign $0$memwr$\storage_6$ls180.v:10292$23_EN[9:0]$2840 10'0000000000 - assign $0\memdat_8[9:0] $memrd$\storage_6$ls180.v:10293$2841_DATA - attribute \src "ls180.v:10291.2-10292.85" - switch \main_sdblock2mem_fifo_wrport_we - attribute \src "ls180.v:10291.6-10291.37" - case 1'1 - assign $0$memwr$\storage_6$ls180.v:10292$23_ADDR[4:0]$2838 \main_sdblock2mem_fifo_wrport_adr - assign $0$memwr$\storage_6$ls180.v:10292$23_DATA[9:0]$2839 \main_sdblock2mem_fifo_wrport_dat_w - assign $0$memwr$\storage_6$ls180.v:10292$23_EN[9:0]$2840 10'1111111111 - case - end - sync posedge \sys_clk_1 - update \memdat_8 $0\memdat_8[9:0] - update $memwr$\storage_6$ls180.v:10292$23_ADDR $0$memwr$\storage_6$ls180.v:10292$23_ADDR[4:0]$2838 - update $memwr$\storage_6$ls180.v:10292$23_DATA $0$memwr$\storage_6$ls180.v:10292$23_DATA[9:0]$2839 - update $memwr$\storage_6$ls180.v:10292$23_EN $0$memwr$\storage_6$ls180.v:10292$23_EN[9:0]$2840 - end - attribute \src "ls180.v:10296.1-10297.4" - process $proc$ls180.v:10296$2842 - sync posedge \sys_clk_1 - end - attribute \src "ls180.v:10304.1-10308.4" - process $proc$ls180.v:10304$2844 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0$memwr$\storage_7$ls180.v:10306$24_ADDR[4:0]$2845 5'xxxxx - assign $0$memwr$\storage_7$ls180.v:10306$24_DATA[9:0]$2846 10'xxxxxxxxxx - assign $0$memwr$\storage_7$ls180.v:10306$24_EN[9:0]$2847 10'0000000000 - assign $0\memdat_9[9:0] $memrd$\storage_7$ls180.v:10307$2848_DATA - attribute \src "ls180.v:10305.2-10306.85" - switch \main_sdmem2block_fifo_wrport_we - attribute \src "ls180.v:10305.6-10305.37" - case 1'1 - assign $0$memwr$\storage_7$ls180.v:10306$24_ADDR[4:0]$2845 \main_sdmem2block_fifo_wrport_adr - assign $0$memwr$\storage_7$ls180.v:10306$24_DATA[9:0]$2846 \main_sdmem2block_fifo_wrport_dat_w - assign $0$memwr$\storage_7$ls180.v:10306$24_EN[9:0]$2847 10'1111111111 - case - end - sync posedge \sys_clk_1 - update \memdat_9 $0\memdat_9[9:0] - update $memwr$\storage_7$ls180.v:10306$24_ADDR $0$memwr$\storage_7$ls180.v:10306$24_ADDR[4:0]$2845 - update $memwr$\storage_7$ls180.v:10306$24_DATA $0$memwr$\storage_7$ls180.v:10306$24_DATA[9:0]$2846 - update $memwr$\storage_7$ls180.v:10306$24_EN $0$memwr$\storage_7$ls180.v:10306$24_EN[9:0]$2847 - end - attribute \src "ls180.v:10310.1-10311.4" - process $proc$ls180.v:10310$2849 - sync posedge \sys_clk_1 - end - attribute \src "ls180.v:1032.5-1032.36" - process $proc$ls180.v:1032$3256 - assign { } { } - assign $1\main_spimaster21_storage[0:0] 1'1 - sync always - sync init - update \main_spimaster21_storage $1\main_spimaster21_storage[0:0] - end - attribute \src "ls180.v:1033.5-1033.31" - process $proc$ls180.v:1033$3257 - assign { } { } - assign $1\main_spimaster22_re[0:0] 1'0 - sync always - sync init - update \main_spimaster22_re $1\main_spimaster22_re[0:0] - end - attribute \src "ls180.v:1034.5-1034.36" - process $proc$ls180.v:1034$3258 - assign { } { } - assign $1\main_spimaster23_storage[0:0] 1'0 - sync always - sync init - update \main_spimaster23_storage $1\main_spimaster23_storage[0:0] - end - attribute \src "ls180.v:1035.5-1035.31" - process $proc$ls180.v:1035$3259 - assign { } { } - assign $1\main_spimaster24_re[0:0] 1'0 - sync always - sync init - update \main_spimaster24_re $1\main_spimaster24_re[0:0] - end - attribute \src "ls180.v:1036.5-1036.39" - process $proc$ls180.v:1036$3260 - assign { } { } - assign $1\main_spimaster25_clk_enable[0:0] 1'0 - sync always - sync init - update \main_spimaster25_clk_enable $1\main_spimaster25_clk_enable[0:0] - end - attribute \src "ls180.v:1037.5-1037.38" - process $proc$ls180.v:1037$3261 - assign { } { } - assign $1\main_spimaster26_cs_enable[0:0] 1'0 - sync always - sync init - update \main_spimaster26_cs_enable $1\main_spimaster26_cs_enable[0:0] - end - attribute \src "ls180.v:1038.11-1038.40" - process $proc$ls180.v:1038$3262 - assign { } { } - assign $1\main_spimaster27_count[2:0] 3'000 - sync always - sync init - update \main_spimaster27_count $1\main_spimaster27_count[2:0] - end - attribute \src "ls180.v:1039.5-1039.39" - process $proc$ls180.v:1039$3263 - assign { } { } - assign $1\main_spimaster28_mosi_latch[0:0] 1'0 - sync always - sync init - update \main_spimaster28_mosi_latch $1\main_spimaster28_mosi_latch[0:0] - end - attribute \src "ls180.v:104.5-104.49" - process $proc$ls180.v:104$2897 - assign { } { } - assign $1\main_libresocsim_libresoc_xics_ics_we[0:0] 1'0 - sync always - sync init - update \main_libresocsim_libresoc_xics_ics_we $1\main_libresocsim_libresoc_xics_ics_we[0:0] - end - attribute \src "ls180.v:1040.5-1040.39" - process $proc$ls180.v:1040$3264 - assign { } { } - assign $1\main_spimaster29_miso_latch[0:0] 1'0 - sync always - sync init - update \main_spimaster29_miso_latch $1\main_spimaster29_miso_latch[0:0] - end - attribute \src "ls180.v:1041.12-1041.48" - process $proc$ls180.v:1041$3265 - assign { } { } - assign $1\main_spimaster30_clk_divider[15:0] 16'0000000000000000 - sync always - sync init - update \main_spimaster30_clk_divider $1\main_spimaster30_clk_divider[15:0] - end - attribute \src "ls180.v:1044.11-1044.44" - process $proc$ls180.v:1044$3266 - assign { } { } - assign $1\main_spimaster33_mosi_data[7:0] 8'00000000 - sync always - sync init - update \main_spimaster33_mosi_data $1\main_spimaster33_mosi_data[7:0] - end - attribute \src "ls180.v:1045.11-1045.43" - process $proc$ls180.v:1045$3267 - assign { } { } - assign $1\main_spimaster34_mosi_sel[2:0] 3'000 - sync always - sync init - update \main_spimaster34_mosi_sel $1\main_spimaster34_mosi_sel[2:0] - end - attribute \src "ls180.v:1046.11-1046.44" - process $proc$ls180.v:1046$3268 - assign { } { } - assign $1\main_spimaster35_miso_data[7:0] 8'00000000 - sync always - sync init - update \main_spimaster35_miso_data $1\main_spimaster35_miso_data[7:0] - end - attribute \src "ls180.v:1049.5-1049.32" - process $proc$ls180.v:1049$3269 - assign { } { } - assign $1\main_spisdcard_done0[0:0] 1'0 - sync always - sync init - update \main_spisdcard_done0 $1\main_spisdcard_done0[0:0] - end - attribute \src "ls180.v:1050.5-1050.30" - process $proc$ls180.v:1050$3270 - assign { } { } - assign $1\main_spisdcard_irq[0:0] 1'0 - sync always - sync init - update \main_spisdcard_irq $1\main_spisdcard_irq[0:0] - end - attribute \src "ls180.v:1052.11-1052.37" - process $proc$ls180.v:1052$3271 - assign { } { } - assign $1\main_spisdcard_miso[7:0] 8'00000000 - sync always - sync init - update \main_spisdcard_miso $1\main_spisdcard_miso[7:0] - end - attribute \src "ls180.v:1056.5-1056.33" - process $proc$ls180.v:1056$3272 - assign { } { } - assign $1\main_spisdcard_start1[0:0] 1'0 - sync always - sync init - update \main_spisdcard_start1 $1\main_spisdcard_start1[0:0] - end - attribute \src "ls180.v:1058.12-1058.50" - process $proc$ls180.v:1058$3273 - assign { } { } - assign $1\main_spisdcard_control_storage[15:0] 16'0000000000000000 - sync always - sync init - update \main_spisdcard_control_storage $1\main_spisdcard_control_storage[15:0] - end - attribute \src "ls180.v:1059.5-1059.37" - process $proc$ls180.v:1059$3274 - assign { } { } - assign $1\main_spisdcard_control_re[0:0] 1'0 - sync always - sync init - update \main_spisdcard_control_re $1\main_spisdcard_control_re[0:0] - end - attribute \src "ls180.v:1063.11-1063.45" - process $proc$ls180.v:1063$3275 - assign { } { } - assign $1\main_spisdcard_mosi_storage[7:0] 8'00000000 - sync always - sync init - update \main_spisdcard_mosi_storage $1\main_spisdcard_mosi_storage[7:0] - end - attribute \src "ls180.v:1064.5-1064.34" - process $proc$ls180.v:1064$3276 - assign { } { } - assign $1\main_spisdcard_mosi_re[0:0] 1'0 - sync always - sync init - update \main_spisdcard_mosi_re $1\main_spisdcard_mosi_re[0:0] - end - attribute \src "ls180.v:1068.5-1068.37" - process $proc$ls180.v:1068$3277 - assign { } { } - assign $1\main_spisdcard_cs_storage[0:0] 1'1 - sync always - sync init - update \main_spisdcard_cs_storage $1\main_spisdcard_cs_storage[0:0] - end - attribute \src "ls180.v:1069.5-1069.32" - process $proc$ls180.v:1069$3278 - assign { } { } - assign $1\main_spisdcard_cs_re[0:0] 1'0 - sync always - sync init - update \main_spisdcard_cs_re $1\main_spisdcard_cs_re[0:0] - end - attribute \src "ls180.v:1070.5-1070.43" - process $proc$ls180.v:1070$3279 - assign { } { } - assign $1\main_spisdcard_loopback_storage[0:0] 1'0 - sync always - sync init - update \main_spisdcard_loopback_storage $1\main_spisdcard_loopback_storage[0:0] - end - attribute \src "ls180.v:1071.5-1071.38" - process $proc$ls180.v:1071$3280 - assign { } { } - assign $1\main_spisdcard_loopback_re[0:0] 1'0 - sync always - sync init - update \main_spisdcard_loopback_re $1\main_spisdcard_loopback_re[0:0] - end - attribute \src "ls180.v:1072.5-1072.37" - process $proc$ls180.v:1072$3281 - assign { } { } - assign $1\main_spisdcard_clk_enable[0:0] 1'0 - sync always - sync init - update \main_spisdcard_clk_enable $1\main_spisdcard_clk_enable[0:0] - end - attribute \src "ls180.v:1073.5-1073.36" - process $proc$ls180.v:1073$3282 - assign { } { } - assign $1\main_spisdcard_cs_enable[0:0] 1'0 - sync always - sync init - update \main_spisdcard_cs_enable $1\main_spisdcard_cs_enable[0:0] - end - attribute \src "ls180.v:1074.11-1074.38" - process $proc$ls180.v:1074$3283 - assign { } { } - assign $1\main_spisdcard_count[2:0] 3'000 - sync always - sync init - update \main_spisdcard_count $1\main_spisdcard_count[2:0] - end - attribute \src "ls180.v:1075.5-1075.37" - process $proc$ls180.v:1075$3284 - assign { } { } - assign $1\main_spisdcard_mosi_latch[0:0] 1'0 - sync always - sync init - update \main_spisdcard_mosi_latch $1\main_spisdcard_mosi_latch[0:0] - end - attribute \src "ls180.v:1076.5-1076.37" - process $proc$ls180.v:1076$3285 - assign { } { } - assign $1\main_spisdcard_miso_latch[0:0] 1'0 - sync always - sync init - update \main_spisdcard_miso_latch $1\main_spisdcard_miso_latch[0:0] - end - attribute \src "ls180.v:1077.12-1077.47" - process $proc$ls180.v:1077$3286 - assign { } { } - assign $1\main_spisdcard_clk_divider1[15:0] 16'0000000000000000 - sync always - sync init - update \main_spisdcard_clk_divider1 $1\main_spisdcard_clk_divider1[15:0] - end - attribute \src "ls180.v:1080.11-1080.42" - process $proc$ls180.v:1080$3287 - assign { } { } - assign $1\main_spisdcard_mosi_data[7:0] 8'00000000 - sync always - sync init - update \main_spisdcard_mosi_data $1\main_spisdcard_mosi_data[7:0] - end - attribute \src "ls180.v:1081.11-1081.41" - process $proc$ls180.v:1081$3288 - assign { } { } - assign $1\main_spisdcard_mosi_sel[2:0] 3'000 - sync always - sync init - update \main_spisdcard_mosi_sel $1\main_spisdcard_mosi_sel[2:0] - end - attribute \src "ls180.v:1082.11-1082.42" - process $proc$ls180.v:1082$3289 - assign { } { } - assign $1\main_spisdcard_miso_data[7:0] 8'00000000 - sync always - sync init - update \main_spisdcard_miso_data $1\main_spisdcard_miso_data[7:0] - end - attribute \src "ls180.v:1083.12-1083.45" - process $proc$ls180.v:1083$3290 - assign { } { } - assign $1\main_spimaster1_storage[15:0] 16'0000000001111101 - sync always - sync init - update \main_spimaster1_storage $1\main_spimaster1_storage[15:0] - end - attribute \src "ls180.v:1084.5-1084.30" - process $proc$ls180.v:1084$3291 - assign { } { } - assign $1\main_spimaster1_re[0:0] 1'0 - sync always - sync init - update \main_spimaster1_re $1\main_spimaster1_re[0:0] - end - attribute \src "ls180.v:1086.12-1086.30" - process $proc$ls180.v:1086$3292 - assign { } { } - assign $1\main_dummy[23:0] 24'000000000000000000000000 - sync always - sync init - update \main_dummy $1\main_dummy[23:0] - end - attribute \src "ls180.v:1090.12-1090.37" - process $proc$ls180.v:1090$3293 - assign { } { } - assign $1\main_pwm0_counter[31:0] 0 - sync always - sync init - update \main_pwm0_counter $1\main_pwm0_counter[31:0] - end - attribute \src "ls180.v:1091.5-1091.36" - process $proc$ls180.v:1091$3294 - assign { } { } - assign $1\main_pwm0_enable_storage[0:0] 1'0 - sync always - sync init - update \main_pwm0_enable_storage $1\main_pwm0_enable_storage[0:0] - end - attribute \src "ls180.v:1092.5-1092.31" - process $proc$ls180.v:1092$3295 - assign { } { } - assign $1\main_pwm0_enable_re[0:0] 1'0 - sync always - sync init - update \main_pwm0_enable_re $1\main_pwm0_enable_re[0:0] - end - attribute \src "ls180.v:1093.12-1093.43" - process $proc$ls180.v:1093$3296 - assign { } { } - assign $1\main_pwm0_width_storage[31:0] 0 - sync always - sync init - update \main_pwm0_width_storage $1\main_pwm0_width_storage[31:0] - end - attribute \src "ls180.v:1094.5-1094.30" - process $proc$ls180.v:1094$3297 - assign { } { } - assign $1\main_pwm0_width_re[0:0] 1'0 - sync always - sync init - update \main_pwm0_width_re $1\main_pwm0_width_re[0:0] - end - attribute \src "ls180.v:1095.12-1095.44" - process $proc$ls180.v:1095$3298 - assign { } { } - assign $1\main_pwm0_period_storage[31:0] 0 - sync always - sync init - update \main_pwm0_period_storage $1\main_pwm0_period_storage[31:0] - end - attribute \src "ls180.v:1096.5-1096.31" - process $proc$ls180.v:1096$3299 - assign { } { } - assign $1\main_pwm0_period_re[0:0] 1'0 - sync always - sync init - update \main_pwm0_period_re $1\main_pwm0_period_re[0:0] - end - attribute \src "ls180.v:1100.12-1100.37" - process $proc$ls180.v:1100$3300 - assign { } { } - assign $1\main_pwm1_counter[31:0] 0 - sync always - sync init - update \main_pwm1_counter $1\main_pwm1_counter[31:0] - end - attribute \src "ls180.v:1101.5-1101.36" - process $proc$ls180.v:1101$3301 - assign { } { } - assign $1\main_pwm1_enable_storage[0:0] 1'0 - sync always - sync init - update \main_pwm1_enable_storage $1\main_pwm1_enable_storage[0:0] - end - attribute \src "ls180.v:1102.5-1102.31" - process $proc$ls180.v:1102$3302 - assign { } { } - assign $1\main_pwm1_enable_re[0:0] 1'0 - sync always - sync init - update \main_pwm1_enable_re $1\main_pwm1_enable_re[0:0] - end - attribute \src "ls180.v:1103.12-1103.43" - process $proc$ls180.v:1103$3303 - assign { } { } - assign $1\main_pwm1_width_storage[31:0] 0 - sync always - sync init - update \main_pwm1_width_storage $1\main_pwm1_width_storage[31:0] - end - attribute \src "ls180.v:1104.5-1104.30" - process $proc$ls180.v:1104$3304 - assign { } { } - assign $1\main_pwm1_width_re[0:0] 1'0 - sync always - sync init - update \main_pwm1_width_re $1\main_pwm1_width_re[0:0] - end - attribute \src "ls180.v:1105.12-1105.44" - process $proc$ls180.v:1105$3305 - assign { } { } - assign $1\main_pwm1_period_storage[31:0] 0 - sync always - sync init - update \main_pwm1_period_storage $1\main_pwm1_period_storage[31:0] - end - attribute \src "ls180.v:1106.5-1106.31" - process $proc$ls180.v:1106$3306 - assign { } { } - assign $1\main_pwm1_period_re[0:0] 1'0 - sync always - sync init - update \main_pwm1_period_re $1\main_pwm1_period_re[0:0] - end - attribute \src "ls180.v:1110.11-1110.34" - process $proc$ls180.v:1110$3307 - assign { } { } - assign $1\main_i2c_storage[2:0] 3'000 - sync always - sync init - update \main_i2c_storage $1\main_i2c_storage[2:0] - end - attribute \src "ls180.v:1111.5-1111.23" - process $proc$ls180.v:1111$3308 - assign { } { } - assign $1\main_i2c_re[0:0] 1'0 - sync always - sync init - update \main_i2c_re $1\main_i2c_re[0:0] - end - attribute \src "ls180.v:1117.11-1117.46" - process $proc$ls180.v:1117$3309 - assign { } { } - assign $1\main_sdphy_clocker_storage[8:0] 9'100000000 - sync always - sync init - update \main_sdphy_clocker_storage $1\main_sdphy_clocker_storage[8:0] - end - attribute \src "ls180.v:1118.5-1118.33" - process $proc$ls180.v:1118$3310 - assign { } { } - assign $1\main_sdphy_clocker_re[0:0] 1'0 - sync always - sync init - update \main_sdphy_clocker_re $1\main_sdphy_clocker_re[0:0] - end - attribute \src "ls180.v:1120.5-1120.35" - process $proc$ls180.v:1120$3311 - assign { } { } - assign $1\main_sdphy_clocker_clk0[0:0] 1'0 - sync always - sync init - update \main_sdphy_clocker_clk0 $1\main_sdphy_clocker_clk0[0:0] - end - attribute \src "ls180.v:1122.11-1122.41" - process $proc$ls180.v:1122$3312 - assign { } { } - assign $1\main_sdphy_clocker_clks[8:0] 9'000000000 - sync always - sync init - update \main_sdphy_clocker_clks $1\main_sdphy_clocker_clks[8:0] - end - attribute \src "ls180.v:1123.5-1123.35" - process $proc$ls180.v:1123$3313 - assign { } { } - assign $1\main_sdphy_clocker_clk1[0:0] 1'0 - sync always - sync init - update \main_sdphy_clocker_clk1 $1\main_sdphy_clocker_clk1[0:0] - end - attribute \src "ls180.v:1124.5-1124.36" - process $proc$ls180.v:1124$3314 - assign { } { } - assign $1\main_sdphy_clocker_clk_d[0:0] 1'0 - sync always - sync init - update \main_sdphy_clocker_clk_d $1\main_sdphy_clocker_clk_d[0:0] - end - attribute \src "ls180.v:1128.5-1128.40" - process $proc$ls180.v:1128$3315 - assign { } { } - assign $0\main_sdphy_init_initialize_w[0:0] 1'0 - sync always - update \main_sdphy_init_initialize_w $0\main_sdphy_init_initialize_w[0:0] - sync init - end - attribute \src "ls180.v:1133.5-1133.48" - process $proc$ls180.v:1133$3316 - assign { } { } - assign $1\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 - sync always - sync init - update \main_sdphy_init_pads_out_payload_clk $1\main_sdphy_init_pads_out_payload_clk[0:0] - end - attribute \src "ls180.v:1134.5-1134.50" - process $proc$ls180.v:1134$3317 - assign { } { } - assign $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 - sync always - sync init - update \main_sdphy_init_pads_out_payload_cmd_o $1\main_sdphy_init_pads_out_payload_cmd_o[0:0] - end - attribute \src "ls180.v:1135.5-1135.51" - process $proc$ls180.v:1135$3318 - assign { } { } - assign $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 - sync always - sync init - update \main_sdphy_init_pads_out_payload_cmd_oe $1\main_sdphy_init_pads_out_payload_cmd_oe[0:0] - end - attribute \src "ls180.v:1136.11-1136.57" - process $proc$ls180.v:1136$3319 - assign { } { } - assign $1\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 - sync always - sync init - update \main_sdphy_init_pads_out_payload_data_o $1\main_sdphy_init_pads_out_payload_data_o[3:0] - end - attribute \src "ls180.v:1137.5-1137.52" - process $proc$ls180.v:1137$3320 - assign { } { } - assign $1\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 - sync always - sync init - update \main_sdphy_init_pads_out_payload_data_oe $1\main_sdphy_init_pads_out_payload_data_oe[0:0] - end - attribute \src "ls180.v:1138.11-1138.39" - process $proc$ls180.v:1138$3321 - assign { } { } - assign $1\main_sdphy_init_count[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_init_count $1\main_sdphy_init_count[7:0] - end - attribute \src "ls180.v:114.11-114.55" - process $proc$ls180.v:114$2898 - assign { } { } - assign $0\main_libresocsim_libresoc_jtag_wb_cti[2:0] 3'000 - sync always - update \main_libresocsim_libresoc_jtag_wb_cti $0\main_libresocsim_libresoc_jtag_wb_cti[2:0] - sync init - end - attribute \src "ls180.v:1143.5-1143.48" - process $proc$ls180.v:1143$3322 - assign { } { } - assign $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdw_pads_out_payload_clk $1\main_sdphy_cmdw_pads_out_payload_clk[0:0] - end - attribute \src "ls180.v:1144.5-1144.50" - process $proc$ls180.v:1144$3323 - assign { } { } - assign $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdw_pads_out_payload_cmd_o $1\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] - end - attribute \src "ls180.v:1145.5-1145.51" - process $proc$ls180.v:1145$3324 - assign { } { } - assign $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdw_pads_out_payload_cmd_oe $1\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] - end - attribute \src "ls180.v:1146.11-1146.57" - process $proc$ls180.v:1146$3325 - assign { } { } - assign $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] 4'0000 - sync always - update \main_sdphy_cmdw_pads_out_payload_data_o $0\main_sdphy_cmdw_pads_out_payload_data_o[3:0] - sync init - end - attribute \src "ls180.v:1147.5-1147.52" - process $proc$ls180.v:1147$3326 - assign { } { } - assign $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] 1'0 - sync always - update \main_sdphy_cmdw_pads_out_payload_data_oe $0\main_sdphy_cmdw_pads_out_payload_data_oe[0:0] - sync init - end - attribute \src "ls180.v:1148.5-1148.38" - process $proc$ls180.v:1148$3327 - assign { } { } - assign $1\main_sdphy_cmdw_sink_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdw_sink_valid $1\main_sdphy_cmdw_sink_valid[0:0] - end - attribute \src "ls180.v:1149.5-1149.38" - process $proc$ls180.v:1149$3328 - assign { } { } - assign $1\main_sdphy_cmdw_sink_ready[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdw_sink_ready $1\main_sdphy_cmdw_sink_ready[0:0] - end - attribute \src "ls180.v:115.11-115.55" - process $proc$ls180.v:115$2899 - assign { } { } - assign $0\main_libresocsim_libresoc_jtag_wb_bte[1:0] 2'00 - sync always - update \main_libresocsim_libresoc_jtag_wb_bte $0\main_libresocsim_libresoc_jtag_wb_bte[1:0] - sync init - end - attribute \src "ls180.v:1150.5-1150.37" - process $proc$ls180.v:1150$3329 - assign { } { } - assign $1\main_sdphy_cmdw_sink_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdw_sink_last $1\main_sdphy_cmdw_sink_last[0:0] - end - attribute \src "ls180.v:1151.11-1151.51" - process $proc$ls180.v:1151$3330 - assign { } { } - assign $1\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdw_sink_payload_data $1\main_sdphy_cmdw_sink_payload_data[7:0] - end - attribute \src "ls180.v:1152.5-1152.32" - process $proc$ls180.v:1152$3331 - assign { } { } - assign $1\main_sdphy_cmdw_done[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdw_done $1\main_sdphy_cmdw_done[0:0] - end - attribute \src "ls180.v:1153.11-1153.39" - process $proc$ls180.v:1153$3332 - assign { } { } - assign $1\main_sdphy_cmdw_count[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdw_count $1\main_sdphy_cmdw_count[7:0] - end - attribute \src "ls180.v:1156.5-1156.49" - process $proc$ls180.v:1156$3333 - assign { } { } - assign $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] 1'0 - sync always - update \main_sdphy_cmdr_pads_in_pads_in_first $0\main_sdphy_cmdr_pads_in_pads_in_first[0:0] - sync init - end - attribute \src "ls180.v:1157.5-1157.48" - process $proc$ls180.v:1157$3334 - assign { } { } - assign $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] 1'0 - sync always - update \main_sdphy_cmdr_pads_in_pads_in_last $0\main_sdphy_cmdr_pads_in_pads_in_last[0:0] - sync init - end - attribute \src "ls180.v:1158.5-1158.55" - process $proc$ls180.v:1158$3335 - assign { } { } - assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] 1'0 - sync always - update \main_sdphy_cmdr_pads_in_pads_in_payload_clk $0\main_sdphy_cmdr_pads_in_pads_in_payload_clk[0:0] - sync init - end - attribute \src "ls180.v:1160.5-1160.57" - process $proc$ls180.v:1160$3336 - assign { } { } - assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] 1'0 - sync always - update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o[0:0] - sync init - end - attribute \src "ls180.v:1161.5-1161.58" - process $proc$ls180.v:1161$3337 - assign { } { } - assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 - sync always - update \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] - sync init - end - attribute \src "ls180.v:1163.11-1163.64" - process $proc$ls180.v:1163$3338 - assign { } { } - assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] 4'0000 - sync always - update \main_sdphy_cmdr_pads_in_pads_in_payload_data_o $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_o[3:0] - sync init - end - attribute \src "ls180.v:1164.5-1164.59" - process $proc$ls180.v:1164$3339 - assign { } { } - assign $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] 1'0 - sync always - update \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe $0\main_sdphy_cmdr_pads_in_pads_in_payload_data_oe[0:0] - sync init - end - attribute \src "ls180.v:1166.5-1166.48" - process $proc$ls180.v:1166$3340 - assign { } { } - assign $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_pads_out_payload_clk $1\main_sdphy_cmdr_pads_out_payload_clk[0:0] - end - attribute \src "ls180.v:1167.5-1167.50" - process $proc$ls180.v:1167$3341 - assign { } { } - assign $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_pads_out_payload_cmd_o $1\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] - end - attribute \src "ls180.v:1168.5-1168.51" - process $proc$ls180.v:1168$3342 - assign { } { } - assign $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_pads_out_payload_cmd_oe $1\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] - end - attribute \src "ls180.v:1169.11-1169.57" - process $proc$ls180.v:1169$3343 - assign { } { } - assign $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] 4'0000 - sync always - update \main_sdphy_cmdr_pads_out_payload_data_o $0\main_sdphy_cmdr_pads_out_payload_data_o[3:0] - sync init - end - attribute \src "ls180.v:1170.5-1170.52" - process $proc$ls180.v:1170$3344 - assign { } { } - assign $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] 1'0 - sync always - update \main_sdphy_cmdr_pads_out_payload_data_oe $0\main_sdphy_cmdr_pads_out_payload_data_oe[0:0] - sync init - end - attribute \src "ls180.v:1171.5-1171.38" - process $proc$ls180.v:1171$3345 - assign { } { } - assign $1\main_sdphy_cmdr_sink_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_sink_valid $1\main_sdphy_cmdr_sink_valid[0:0] - end - attribute \src "ls180.v:1172.5-1172.38" - process $proc$ls180.v:1172$3346 - assign { } { } - assign $1\main_sdphy_cmdr_sink_ready[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_sink_ready $1\main_sdphy_cmdr_sink_ready[0:0] - end - attribute \src "ls180.v:1173.5-1173.37" - process $proc$ls180.v:1173$3347 - assign { } { } - assign $1\main_sdphy_cmdr_sink_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_sink_last $1\main_sdphy_cmdr_sink_last[0:0] - end - attribute \src "ls180.v:1174.11-1174.53" - process $proc$ls180.v:1174$3348 - assign { } { } - assign $1\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdr_sink_payload_length $1\main_sdphy_cmdr_sink_payload_length[7:0] - end - attribute \src "ls180.v:1175.5-1175.40" - process $proc$ls180.v:1175$3349 - assign { } { } - assign $1\main_sdphy_cmdr_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_source_valid $1\main_sdphy_cmdr_source_valid[0:0] - end - attribute \src "ls180.v:1176.5-1176.40" - process $proc$ls180.v:1176$3350 - assign { } { } - assign $1\main_sdphy_cmdr_source_ready[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_source_ready $1\main_sdphy_cmdr_source_ready[0:0] - end - attribute \src "ls180.v:1177.5-1177.39" - process $proc$ls180.v:1177$3351 - assign { } { } - assign $1\main_sdphy_cmdr_source_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_source_last $1\main_sdphy_cmdr_source_last[0:0] - end - attribute \src "ls180.v:1178.11-1178.53" - process $proc$ls180.v:1178$3352 - assign { } { } - assign $1\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdr_source_payload_data $1\main_sdphy_cmdr_source_payload_data[7:0] - end - attribute \src "ls180.v:1179.11-1179.55" - process $proc$ls180.v:1179$3353 - assign { } { } - assign $1\main_sdphy_cmdr_source_payload_status[2:0] 3'000 - sync always - sync init - update \main_sdphy_cmdr_source_payload_status $1\main_sdphy_cmdr_source_payload_status[2:0] - end - attribute \src "ls180.v:1180.12-1180.48" - process $proc$ls180.v:1180$3354 - assign { } { } - assign $1\main_sdphy_cmdr_timeout[31:0] 500000 - sync always - sync init - update \main_sdphy_cmdr_timeout $1\main_sdphy_cmdr_timeout[31:0] - end - attribute \src "ls180.v:1181.11-1181.39" - process $proc$ls180.v:1181$3355 - assign { } { } - assign $1\main_sdphy_cmdr_count[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdr_count $1\main_sdphy_cmdr_count[7:0] - end - attribute \src "ls180.v:1183.5-1183.46" - process $proc$ls180.v:1183$3356 - assign { } { } - assign $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] 1'0 - sync always - update \main_sdphy_cmdr_cmdr_pads_in_ready $0\main_sdphy_cmdr_cmdr_pads_in_ready[0:0] - sync init - end - attribute \src "ls180.v:1194.5-1194.53" - process $proc$ls180.v:1194$3357 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_source_source_ready0 $1\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] - end - attribute \src "ls180.v:1199.5-1199.36" - process $proc$ls180.v:1199$3358 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_run[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_run $1\main_sdphy_cmdr_cmdr_run[0:0] - end - attribute \src "ls180.v:1202.5-1202.53" - process $proc$ls180.v:1202$3359 - assign { } { } - assign $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] 1'0 - sync always - update \main_sdphy_cmdr_cmdr_converter_sink_first $0\main_sdphy_cmdr_cmdr_converter_sink_first[0:0] - sync init - end - attribute \src "ls180.v:1203.5-1203.52" - process $proc$ls180.v:1203$3360 - assign { } { } - assign $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] 1'0 - sync always - update \main_sdphy_cmdr_cmdr_converter_sink_last $0\main_sdphy_cmdr_cmdr_converter_sink_last[0:0] - sync init - end - attribute \src "ls180.v:1207.5-1207.55" - process $proc$ls180.v:1207$3361 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_converter_source_first $1\main_sdphy_cmdr_cmdr_converter_source_first[0:0] - end - attribute \src "ls180.v:1208.5-1208.54" - process $proc$ls180.v:1208$3362 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_converter_source_last $1\main_sdphy_cmdr_cmdr_converter_source_last[0:0] - end - attribute \src "ls180.v:1209.11-1209.68" - process $proc$ls180.v:1209$3363 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdr_cmdr_converter_source_payload_data $1\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] - end - attribute \src "ls180.v:1210.11-1210.81" - process $proc$ls180.v:1210$3364 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] 4'0000 - sync always - sync init - update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $1\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] - end - attribute \src "ls180.v:1211.11-1211.54" - process $proc$ls180.v:1211$3365 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 - sync always - sync init - update \main_sdphy_cmdr_cmdr_converter_demux $1\main_sdphy_cmdr_cmdr_converter_demux[2:0] - end - attribute \src "ls180.v:1213.5-1213.53" - process $proc$ls180.v:1213$3366 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_converter_strobe_all $1\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] - end - attribute \src "ls180.v:1224.5-1224.49" - process $proc$ls180.v:1224$3367 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_buf_source_valid $1\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] - end - attribute \src "ls180.v:1226.5-1226.49" - process $proc$ls180.v:1226$3368 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_buf_source_first $1\main_sdphy_cmdr_cmdr_buf_source_first[0:0] - end - attribute \src "ls180.v:1227.5-1227.48" - process $proc$ls180.v:1227$3369 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_buf_source_last $1\main_sdphy_cmdr_cmdr_buf_source_last[0:0] - end - attribute \src "ls180.v:1228.11-1228.62" - process $proc$ls180.v:1228$3370 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdr_cmdr_buf_source_payload_data $1\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] - end - attribute \src "ls180.v:1229.5-1229.38" - process $proc$ls180.v:1229$3371 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_reset[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_reset $1\main_sdphy_cmdr_cmdr_reset[0:0] - end - attribute \src "ls180.v:1234.5-1234.49" - process $proc$ls180.v:1234$3372 - assign { } { } - assign $1\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_pads_out_payload_clk $1\main_sdphy_dataw_pads_out_payload_clk[0:0] - end - attribute \src "ls180.v:1235.5-1235.51" - process $proc$ls180.v:1235$3373 - assign { } { } - assign $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_out_payload_cmd_o $0\main_sdphy_dataw_pads_out_payload_cmd_o[0:0] - sync init - end - attribute \src "ls180.v:1236.5-1236.52" - process $proc$ls180.v:1236$3374 - assign { } { } - assign $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_out_payload_cmd_oe $0\main_sdphy_dataw_pads_out_payload_cmd_oe[0:0] - sync init - end - attribute \src "ls180.v:1237.11-1237.58" - process $proc$ls180.v:1237$3375 - assign { } { } - assign $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 - sync always - sync init - update \main_sdphy_dataw_pads_out_payload_data_o $1\main_sdphy_dataw_pads_out_payload_data_o[3:0] - end - attribute \src "ls180.v:1238.5-1238.53" - process $proc$ls180.v:1238$3376 - assign { } { } - assign $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_pads_out_payload_data_oe $1\main_sdphy_dataw_pads_out_payload_data_oe[0:0] - end - attribute \src "ls180.v:1239.5-1239.39" - process $proc$ls180.v:1239$3377 - assign { } { } - assign $1\main_sdphy_dataw_sink_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_sink_valid $1\main_sdphy_dataw_sink_valid[0:0] - end - attribute \src "ls180.v:1240.5-1240.39" - process $proc$ls180.v:1240$3378 - assign { } { } - assign $1\main_sdphy_dataw_sink_ready[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_sink_ready $1\main_sdphy_dataw_sink_ready[0:0] - end - attribute \src "ls180.v:1241.5-1241.39" - process $proc$ls180.v:1241$3379 - assign { } { } - assign $1\main_sdphy_dataw_sink_first[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_sink_first $1\main_sdphy_dataw_sink_first[0:0] - end - attribute \src "ls180.v:1242.5-1242.38" - process $proc$ls180.v:1242$3380 - assign { } { } - assign $1\main_sdphy_dataw_sink_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_sink_last $1\main_sdphy_dataw_sink_last[0:0] - end - attribute \src "ls180.v:1243.11-1243.52" - process $proc$ls180.v:1243$3381 - assign { } { } - assign $1\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_dataw_sink_payload_data $1\main_sdphy_dataw_sink_payload_data[7:0] - end - attribute \src "ls180.v:1244.5-1244.33" - process $proc$ls180.v:1244$3382 - assign { } { } - assign $1\main_sdphy_dataw_stop[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_stop $1\main_sdphy_dataw_stop[0:0] - end - attribute \src "ls180.v:1245.11-1245.40" - process $proc$ls180.v:1245$3383 - assign { } { } - assign $1\main_sdphy_dataw_count[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_dataw_count $1\main_sdphy_dataw_count[7:0] - end - attribute \src "ls180.v:1246.5-1246.50" - process $proc$ls180.v:1246$3384 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_in_pads_in_valid $0\main_sdphy_dataw_pads_in_pads_in_valid[0:0] - sync init - end - attribute \src "ls180.v:1248.5-1248.50" - process $proc$ls180.v:1248$3385 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_in_pads_in_first $0\main_sdphy_dataw_pads_in_pads_in_first[0:0] - sync init - end - attribute \src "ls180.v:1249.5-1249.49" - process $proc$ls180.v:1249$3386 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_in_pads_in_last $0\main_sdphy_dataw_pads_in_pads_in_last[0:0] - sync init - end - attribute \src "ls180.v:1250.5-1250.56" - process $proc$ls180.v:1250$3387 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_in_pads_in_payload_clk $0\main_sdphy_dataw_pads_in_pads_in_payload_clk[0:0] - sync init - end - attribute \src "ls180.v:1251.5-1251.58" - process $proc$ls180.v:1251$3388 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_i[0:0] - sync init - end - attribute \src "ls180.v:1252.5-1252.58" - process $proc$ls180.v:1252$3389 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_o[0:0] - sync init - end - attribute \src "ls180.v:1253.5-1253.59" - process $proc$ls180.v:1253$3390 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe[0:0] - sync init - end - attribute \src "ls180.v:1254.11-1254.65" - process $proc$ls180.v:1254$3391 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] 4'0000 - sync always - update \main_sdphy_dataw_pads_in_pads_in_payload_data_i $0\main_sdphy_dataw_pads_in_pads_in_payload_data_i[3:0] - sync init - end - attribute \src "ls180.v:1255.11-1255.65" - process $proc$ls180.v:1255$3392 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] 4'0000 - sync always - update \main_sdphy_dataw_pads_in_pads_in_payload_data_o $0\main_sdphy_dataw_pads_in_pads_in_payload_data_o[3:0] - sync init - end - attribute \src "ls180.v:1256.5-1256.60" - process $proc$ls180.v:1256$3393 - assign { } { } - assign $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] 1'0 - sync always - update \main_sdphy_dataw_pads_in_pads_in_payload_data_oe $0\main_sdphy_dataw_pads_in_pads_in_payload_data_oe[0:0] - sync init - end - attribute \src "ls180.v:1257.5-1257.34" - process $proc$ls180.v:1257$3394 - assign { } { } - assign $1\main_sdphy_dataw_start[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_start $1\main_sdphy_dataw_start[0:0] - end - attribute \src "ls180.v:1258.5-1258.34" - process $proc$ls180.v:1258$3395 - assign { } { } - assign $1\main_sdphy_dataw_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_valid $1\main_sdphy_dataw_valid[0:0] - end - attribute \src "ls180.v:1259.5-1259.34" - process $proc$ls180.v:1259$3396 - assign { } { } - assign $1\main_sdphy_dataw_error[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_error $1\main_sdphy_dataw_error[0:0] - end - attribute \src "ls180.v:1261.5-1261.47" - process $proc$ls180.v:1261$3397 - assign { } { } - assign $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] 1'0 - sync always - update \main_sdphy_dataw_crcr_pads_in_ready $0\main_sdphy_dataw_crcr_pads_in_ready[0:0] - sync init - end - attribute \src "ls180.v:1272.5-1272.54" - process $proc$ls180.v:1272$3398 - assign { } { } - assign $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_source_source_ready0 $1\main_sdphy_dataw_crcr_source_source_ready0[0:0] - end - attribute \src "ls180.v:1277.5-1277.37" - process $proc$ls180.v:1277$3399 - assign { } { } - assign $1\main_sdphy_dataw_crcr_run[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_run $1\main_sdphy_dataw_crcr_run[0:0] - end - attribute \src "ls180.v:1280.5-1280.54" - process $proc$ls180.v:1280$3400 - assign { } { } - assign $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] 1'0 - sync always - update \main_sdphy_dataw_crcr_converter_sink_first $0\main_sdphy_dataw_crcr_converter_sink_first[0:0] - sync init - end - attribute \src "ls180.v:1281.5-1281.53" - process $proc$ls180.v:1281$3401 - assign { } { } - assign $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] 1'0 - sync always - update \main_sdphy_dataw_crcr_converter_sink_last $0\main_sdphy_dataw_crcr_converter_sink_last[0:0] - sync init - end - attribute \src "ls180.v:1285.5-1285.56" - process $proc$ls180.v:1285$3402 - assign { } { } - assign $1\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_converter_source_first $1\main_sdphy_dataw_crcr_converter_source_first[0:0] - end - attribute \src "ls180.v:1286.5-1286.55" - process $proc$ls180.v:1286$3403 - assign { } { } - assign $1\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_converter_source_last $1\main_sdphy_dataw_crcr_converter_source_last[0:0] - end - attribute \src "ls180.v:1287.11-1287.69" - process $proc$ls180.v:1287$3404 - assign { } { } - assign $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_dataw_crcr_converter_source_payload_data $1\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] - end - attribute \src "ls180.v:1288.11-1288.82" - process $proc$ls180.v:1288$3405 - assign { } { } - assign $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] 4'0000 - sync always - sync init - update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $1\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] - end - attribute \src "ls180.v:1289.11-1289.55" - process $proc$ls180.v:1289$3406 - assign { } { } - assign $1\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 - sync always - sync init - update \main_sdphy_dataw_crcr_converter_demux $1\main_sdphy_dataw_crcr_converter_demux[2:0] - end - attribute \src "ls180.v:1291.5-1291.54" - process $proc$ls180.v:1291$3407 - assign { } { } - assign $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_converter_strobe_all $1\main_sdphy_dataw_crcr_converter_strobe_all[0:0] - end - attribute \src "ls180.v:1302.5-1302.50" - process $proc$ls180.v:1302$3408 - assign { } { } - assign $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_buf_source_valid $1\main_sdphy_dataw_crcr_buf_source_valid[0:0] - end - attribute \src "ls180.v:1304.5-1304.50" - process $proc$ls180.v:1304$3409 - assign { } { } - assign $1\main_sdphy_dataw_crcr_buf_source_first[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_buf_source_first $1\main_sdphy_dataw_crcr_buf_source_first[0:0] - end - attribute \src "ls180.v:1305.5-1305.49" - process $proc$ls180.v:1305$3410 - assign { } { } - assign $1\main_sdphy_dataw_crcr_buf_source_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_buf_source_last $1\main_sdphy_dataw_crcr_buf_source_last[0:0] - end - attribute \src "ls180.v:1306.11-1306.63" - process $proc$ls180.v:1306$3411 - assign { } { } - assign $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_dataw_crcr_buf_source_payload_data $1\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] - end - attribute \src "ls180.v:1307.5-1307.39" - process $proc$ls180.v:1307$3412 - assign { } { } - assign $1\main_sdphy_dataw_crcr_reset[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_reset $1\main_sdphy_dataw_crcr_reset[0:0] - end - attribute \src "ls180.v:1310.5-1310.50" - process $proc$ls180.v:1310$3413 - assign { } { } - assign $0\main_sdphy_datar_pads_in_pads_in_first[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_in_pads_in_first $0\main_sdphy_datar_pads_in_pads_in_first[0:0] - sync init - end - attribute \src "ls180.v:1311.5-1311.49" - process $proc$ls180.v:1311$3414 - assign { } { } - assign $0\main_sdphy_datar_pads_in_pads_in_last[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_in_pads_in_last $0\main_sdphy_datar_pads_in_pads_in_last[0:0] - sync init - end - attribute \src "ls180.v:1312.5-1312.56" - process $proc$ls180.v:1312$3415 - assign { } { } - assign $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_in_pads_in_payload_clk $0\main_sdphy_datar_pads_in_pads_in_payload_clk[0:0] - sync init - end - attribute \src "ls180.v:1314.5-1314.58" - process $proc$ls180.v:1314$3416 - assign { } { } - assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_in_pads_in_payload_cmd_o $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_o[0:0] - sync init - end - attribute \src "ls180.v:1315.5-1315.59" - process $proc$ls180.v:1315$3417 - assign { } { } - assign $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe $0\main_sdphy_datar_pads_in_pads_in_payload_cmd_oe[0:0] - sync init - end - attribute \src "ls180.v:1317.11-1317.65" - process $proc$ls180.v:1317$3418 - assign { } { } - assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] 4'0000 - sync always - update \main_sdphy_datar_pads_in_pads_in_payload_data_o $0\main_sdphy_datar_pads_in_pads_in_payload_data_o[3:0] - sync init - end - attribute \src "ls180.v:1318.5-1318.60" - process $proc$ls180.v:1318$3419 - assign { } { } - assign $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_in_pads_in_payload_data_oe $0\main_sdphy_datar_pads_in_pads_in_payload_data_oe[0:0] - sync init - end - attribute \src "ls180.v:1320.5-1320.49" - process $proc$ls180.v:1320$3420 - assign { } { } - assign $1\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_pads_out_payload_clk $1\main_sdphy_datar_pads_out_payload_clk[0:0] - end - attribute \src "ls180.v:1321.5-1321.51" - process $proc$ls180.v:1321$3421 - assign { } { } - assign $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_out_payload_cmd_o $0\main_sdphy_datar_pads_out_payload_cmd_o[0:0] - sync init - end - attribute \src "ls180.v:1322.5-1322.52" - process $proc$ls180.v:1322$3422 - assign { } { } - assign $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_out_payload_cmd_oe $0\main_sdphy_datar_pads_out_payload_cmd_oe[0:0] - sync init - end - attribute \src "ls180.v:1323.11-1323.58" - process $proc$ls180.v:1323$3423 - assign { } { } - assign $0\main_sdphy_datar_pads_out_payload_data_o[3:0] 4'0000 - sync always - update \main_sdphy_datar_pads_out_payload_data_o $0\main_sdphy_datar_pads_out_payload_data_o[3:0] - sync init - end - attribute \src "ls180.v:1324.5-1324.53" - process $proc$ls180.v:1324$3424 - assign { } { } - assign $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] 1'0 - sync always - update \main_sdphy_datar_pads_out_payload_data_oe $0\main_sdphy_datar_pads_out_payload_data_oe[0:0] - sync init - end - attribute \src "ls180.v:1325.5-1325.39" - process $proc$ls180.v:1325$3425 - assign { } { } - assign $1\main_sdphy_datar_sink_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_sink_valid $1\main_sdphy_datar_sink_valid[0:0] - end - attribute \src "ls180.v:1326.5-1326.39" - process $proc$ls180.v:1326$3426 - assign { } { } - assign $1\main_sdphy_datar_sink_ready[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_sink_ready $1\main_sdphy_datar_sink_ready[0:0] - end - attribute \src "ls180.v:1327.5-1327.38" - process $proc$ls180.v:1327$3427 - assign { } { } - assign $1\main_sdphy_datar_sink_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_sink_last $1\main_sdphy_datar_sink_last[0:0] - end - attribute \src "ls180.v:1328.11-1328.61" - process $proc$ls180.v:1328$3428 - assign { } { } - assign $1\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000 - sync always - sync init - update \main_sdphy_datar_sink_payload_block_length $1\main_sdphy_datar_sink_payload_block_length[9:0] - end - attribute \src "ls180.v:1329.5-1329.41" - process $proc$ls180.v:1329$3429 - assign { } { } - assign $1\main_sdphy_datar_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_source_valid $1\main_sdphy_datar_source_valid[0:0] - end - attribute \src "ls180.v:133.5-133.69" - process $proc$ls180.v:133$2900 - assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] 1'0 - sync always - update \main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i $0\main_libresocsim_libresoc_constraintmanager_obj_i2c_sda_i[0:0] - sync init - end - attribute \src "ls180.v:1330.5-1330.41" - process $proc$ls180.v:1330$3430 - assign { } { } - assign $1\main_sdphy_datar_source_ready[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_source_ready $1\main_sdphy_datar_source_ready[0:0] - end - attribute \src "ls180.v:1331.5-1331.41" - process $proc$ls180.v:1331$3431 - assign { } { } - assign $0\main_sdphy_datar_source_first[0:0] 1'0 - sync always - update \main_sdphy_datar_source_first $0\main_sdphy_datar_source_first[0:0] - sync init - end - attribute \src "ls180.v:1332.5-1332.40" - process $proc$ls180.v:1332$3432 - assign { } { } - assign $1\main_sdphy_datar_source_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_source_last $1\main_sdphy_datar_source_last[0:0] - end - attribute \src "ls180.v:1333.11-1333.54" - process $proc$ls180.v:1333$3433 - assign { } { } - assign $1\main_sdphy_datar_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_datar_source_payload_data $1\main_sdphy_datar_source_payload_data[7:0] - end - attribute \src "ls180.v:1334.11-1334.56" - process $proc$ls180.v:1334$3434 - assign { } { } - assign $1\main_sdphy_datar_source_payload_status[2:0] 3'000 - sync always - sync init - update \main_sdphy_datar_source_payload_status $1\main_sdphy_datar_source_payload_status[2:0] - end - attribute \src "ls180.v:1335.5-1335.33" - process $proc$ls180.v:1335$3435 - assign { } { } - assign $1\main_sdphy_datar_stop[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_stop $1\main_sdphy_datar_stop[0:0] - end - attribute \src "ls180.v:1336.12-1336.49" - process $proc$ls180.v:1336$3436 - assign { } { } - assign $1\main_sdphy_datar_timeout[31:0] 500000 - sync always - sync init - update \main_sdphy_datar_timeout $1\main_sdphy_datar_timeout[31:0] - end - attribute \src "ls180.v:1337.11-1337.41" - process $proc$ls180.v:1337$3437 - assign { } { } - assign $1\main_sdphy_datar_count[9:0] 10'0000000000 - sync always - sync init - update \main_sdphy_datar_count $1\main_sdphy_datar_count[9:0] - end - attribute \src "ls180.v:1339.5-1339.48" - process $proc$ls180.v:1339$3438 - assign { } { } - assign $0\main_sdphy_datar_datar_pads_in_ready[0:0] 1'0 - sync always - update \main_sdphy_datar_datar_pads_in_ready $0\main_sdphy_datar_datar_pads_in_ready[0:0] - sync init - end - attribute \src "ls180.v:1350.5-1350.55" - process $proc$ls180.v:1350$3439 - assign { } { } - assign $1\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_source_source_ready0 $1\main_sdphy_datar_datar_source_source_ready0[0:0] - end - attribute \src "ls180.v:1355.5-1355.38" - process $proc$ls180.v:1355$3440 - assign { } { } - assign $1\main_sdphy_datar_datar_run[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_run $1\main_sdphy_datar_datar_run[0:0] - end - attribute \src "ls180.v:1358.5-1358.55" - process $proc$ls180.v:1358$3441 - assign { } { } - assign $0\main_sdphy_datar_datar_converter_sink_first[0:0] 1'0 - sync always - update \main_sdphy_datar_datar_converter_sink_first $0\main_sdphy_datar_datar_converter_sink_first[0:0] - sync init - end - attribute \src "ls180.v:1359.5-1359.54" - process $proc$ls180.v:1359$3442 - assign { } { } - assign $0\main_sdphy_datar_datar_converter_sink_last[0:0] 1'0 - sync always - update \main_sdphy_datar_datar_converter_sink_last $0\main_sdphy_datar_datar_converter_sink_last[0:0] - sync init - end - attribute \src "ls180.v:1363.5-1363.57" - process $proc$ls180.v:1363$3443 - assign { } { } - assign $1\main_sdphy_datar_datar_converter_source_first[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_converter_source_first $1\main_sdphy_datar_datar_converter_source_first[0:0] - end - attribute \src "ls180.v:1364.5-1364.56" - process $proc$ls180.v:1364$3444 - assign { } { } - assign $1\main_sdphy_datar_datar_converter_source_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_converter_source_last $1\main_sdphy_datar_datar_converter_source_last[0:0] - end - attribute \src "ls180.v:1365.11-1365.70" - process $proc$ls180.v:1365$3445 - assign { } { } - assign $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_datar_datar_converter_source_payload_data $1\main_sdphy_datar_datar_converter_source_payload_data[7:0] - end - attribute \src "ls180.v:1366.11-1366.83" - process $proc$ls180.v:1366$3446 - assign { } { } - assign $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] 2'00 - sync always - sync init - update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $1\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] - end - attribute \src "ls180.v:1367.5-1367.50" - process $proc$ls180.v:1367$3447 - assign { } { } - assign $1\main_sdphy_datar_datar_converter_demux[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_converter_demux $1\main_sdphy_datar_datar_converter_demux[0:0] - end - attribute \src "ls180.v:1369.5-1369.55" - process $proc$ls180.v:1369$3448 - assign { } { } - assign $1\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_converter_strobe_all $1\main_sdphy_datar_datar_converter_strobe_all[0:0] - end - attribute \src "ls180.v:1380.5-1380.51" - process $proc$ls180.v:1380$3449 - assign { } { } - assign $1\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_buf_source_valid $1\main_sdphy_datar_datar_buf_source_valid[0:0] - end - attribute \src "ls180.v:1382.5-1382.51" - process $proc$ls180.v:1382$3450 - assign { } { } - assign $1\main_sdphy_datar_datar_buf_source_first[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_buf_source_first $1\main_sdphy_datar_datar_buf_source_first[0:0] - end - attribute \src "ls180.v:1383.5-1383.50" - process $proc$ls180.v:1383$3451 - assign { } { } - assign $1\main_sdphy_datar_datar_buf_source_last[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_buf_source_last $1\main_sdphy_datar_datar_buf_source_last[0:0] - end - attribute \src "ls180.v:1384.11-1384.64" - process $proc$ls180.v:1384$3452 - assign { } { } - assign $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_datar_datar_buf_source_payload_data $1\main_sdphy_datar_datar_buf_source_payload_data[7:0] - end - attribute \src "ls180.v:1385.5-1385.40" - process $proc$ls180.v:1385$3453 - assign { } { } - assign $1\main_sdphy_datar_datar_reset[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_reset $1\main_sdphy_datar_datar_reset[0:0] - end - attribute \src "ls180.v:1387.5-1387.35" - process $proc$ls180.v:1387$3454 - assign { } { } - assign $1\main_sdphy_sdpads_cmd_i[0:0] 1'0 - sync always - sync init - update \main_sdphy_sdpads_cmd_i $1\main_sdphy_sdpads_cmd_i[0:0] - end - attribute \src "ls180.v:1390.11-1390.42" - process $proc$ls180.v:1390$3455 - assign { } { } - assign $1\main_sdphy_sdpads_data_i[3:0] 4'0000 - sync always - sync init - update \main_sdphy_sdpads_data_i $1\main_sdphy_sdpads_data_i[3:0] - end - attribute \src "ls180.v:140.12-140.74" - process $proc$ls180.v:140$2901 - assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] 16'0000000000000000 - sync always - update \main_libresocsim_libresoc_constraintmanager_obj_gpio_i $0\main_libresocsim_libresoc_constraintmanager_obj_gpio_i[15:0] - sync init - end - attribute \src "ls180.v:1403.12-1403.52" - process $proc$ls180.v:1403$3456 - assign { } { } - assign $1\main_sdcore_cmd_argument_storage[31:0] 0 - sync always - sync init - update \main_sdcore_cmd_argument_storage $1\main_sdcore_cmd_argument_storage[31:0] - end - attribute \src "ls180.v:1404.5-1404.39" - process $proc$ls180.v:1404$3457 - assign { } { } - assign $1\main_sdcore_cmd_argument_re[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_argument_re $1\main_sdcore_cmd_argument_re[0:0] - end - attribute \src "ls180.v:1405.12-1405.51" - process $proc$ls180.v:1405$3458 - assign { } { } - assign $1\main_sdcore_cmd_command_storage[31:0] 0 - sync always - sync init - update \main_sdcore_cmd_command_storage $1\main_sdcore_cmd_command_storage[31:0] - end - attribute \src "ls180.v:1406.5-1406.38" - process $proc$ls180.v:1406$3459 - assign { } { } - assign $1\main_sdcore_cmd_command_re[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_command_re $1\main_sdcore_cmd_command_re[0:0] - end - attribute \src "ls180.v:1410.5-1410.34" - process $proc$ls180.v:1410$3460 - assign { } { } - assign $0\main_sdcore_cmd_send_w[0:0] 1'0 - sync always - update \main_sdcore_cmd_send_w $0\main_sdcore_cmd_send_w[0:0] - sync init - end - attribute \src "ls180.v:1411.13-1411.53" - process $proc$ls180.v:1411$3461 - assign { } { } - assign $1\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_sdcore_cmd_response_status $1\main_sdcore_cmd_response_status[127:0] - end - attribute \src "ls180.v:1417.11-1417.51" - process $proc$ls180.v:1417$3462 - assign { } { } - assign $1\main_sdcore_block_length_storage[9:0] 10'0000000000 - sync always - sync init - update \main_sdcore_block_length_storage $1\main_sdcore_block_length_storage[9:0] - end - attribute \src "ls180.v:1418.5-1418.39" - process $proc$ls180.v:1418$3463 - assign { } { } - assign $1\main_sdcore_block_length_re[0:0] 1'0 - sync always - sync init - update \main_sdcore_block_length_re $1\main_sdcore_block_length_re[0:0] - end - attribute \src "ls180.v:1419.12-1419.51" - process $proc$ls180.v:1419$3464 - assign { } { } - assign $1\main_sdcore_block_count_storage[31:0] 0 - sync always - sync init - update \main_sdcore_block_count_storage $1\main_sdcore_block_count_storage[31:0] - end - attribute \src "ls180.v:1420.5-1420.38" - process $proc$ls180.v:1420$3465 - assign { } { } - assign $1\main_sdcore_block_count_re[0:0] 1'0 - sync always - sync init - update \main_sdcore_block_count_re $1\main_sdcore_block_count_re[0:0] - end - attribute \src "ls180.v:1421.11-1421.51" - process $proc$ls180.v:1421$3466 - assign { } { } - assign $1\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 - sync always - sync init - update \main_sdcore_crc7_inserter_crcreg0 $1\main_sdcore_crc7_inserter_crcreg0[6:0] - end - attribute \src "ls180.v:145.5-145.72" - process $proc$ls180.v:145$2902 - assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] 1'0 - sync always - update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_cmd_i[0:0] - sync init - end - attribute \src "ls180.v:1463.11-1463.47" - process $proc$ls180.v:1463$3467 - assign { } { } - assign $1\main_sdcore_crc7_inserter_crc[6:0] 7'0000000 - sync always - sync init - update \main_sdcore_crc7_inserter_crc $1\main_sdcore_crc7_inserter_crc[6:0] - end - attribute \src "ls180.v:1467.5-1467.49" - process $proc$ls180.v:1467$3468 - assign { } { } - assign $1\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_sink_ready $1\main_sdcore_crc16_inserter_sink_ready[0:0] - end - attribute \src "ls180.v:1471.5-1471.51" - process $proc$ls180.v:1471$3469 - assign { } { } - assign $1\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_source_valid $1\main_sdcore_crc16_inserter_source_valid[0:0] - end - attribute \src "ls180.v:1472.5-1472.51" - process $proc$ls180.v:1472$3470 - assign { } { } - assign $1\main_sdcore_crc16_inserter_source_ready[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_source_ready $1\main_sdcore_crc16_inserter_source_ready[0:0] - end - attribute \src "ls180.v:1473.5-1473.51" - process $proc$ls180.v:1473$3471 - assign { } { } - assign $0\main_sdcore_crc16_inserter_source_first[0:0] 1'0 - sync always - update \main_sdcore_crc16_inserter_source_first $0\main_sdcore_crc16_inserter_source_first[0:0] - sync init - end - attribute \src "ls180.v:1474.5-1474.50" - process $proc$ls180.v:1474$3472 - assign { } { } - assign $1\main_sdcore_crc16_inserter_source_last[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_source_last $1\main_sdcore_crc16_inserter_source_last[0:0] - end - attribute \src "ls180.v:1475.11-1475.64" - process $proc$ls180.v:1475$3473 - assign { } { } - assign $1\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdcore_crc16_inserter_source_payload_data $1\main_sdcore_crc16_inserter_source_payload_data[7:0] - end - attribute \src "ls180.v:1476.11-1476.48" - process $proc$ls180.v:1476$3474 - assign { } { } - assign $1\main_sdcore_crc16_inserter_cnt[2:0] 3'000 - sync always - sync init - update \main_sdcore_crc16_inserter_cnt $1\main_sdcore_crc16_inserter_cnt[2:0] - end - attribute \src "ls180.v:1477.12-1477.59" - process $proc$ls180.v:1477$3475 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crc0_crcreg0 $1\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] - end - attribute \src "ls180.v:148.11-148.79" - process $proc$ls180.v:148$2903 - assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] 4'0000 - sync always - update \main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdcard_data_i[3:0] - sync init - end - attribute \src "ls180.v:1481.12-1481.55" - process $proc$ls180.v:1481$3476 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crc0_crc $1\main_sdcore_crc16_inserter_crc0_crc[15:0] - end - attribute \src "ls180.v:1484.12-1484.59" - process $proc$ls180.v:1484$3477 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crc1_crcreg0 $1\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] - end - attribute \src "ls180.v:1488.12-1488.55" - process $proc$ls180.v:1488$3478 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crc1_crc $1\main_sdcore_crc16_inserter_crc1_crc[15:0] - end - attribute \src "ls180.v:1491.12-1491.59" - process $proc$ls180.v:1491$3479 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crc2_crcreg0 $1\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] - end - attribute \src "ls180.v:1495.12-1495.55" - process $proc$ls180.v:1495$3480 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crc2_crc $1\main_sdcore_crc16_inserter_crc2_crc[15:0] - end - attribute \src "ls180.v:1498.12-1498.59" - process $proc$ls180.v:1498$3481 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crc3_crcreg0 $1\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] - end - attribute \src "ls180.v:1502.12-1502.55" - process $proc$ls180.v:1502$3482 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crc3_crc $1\main_sdcore_crc16_inserter_crc3_crc[15:0] - end - attribute \src "ls180.v:1505.12-1505.54" - process $proc$ls180.v:1505$3483 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp0 $1\main_sdcore_crc16_inserter_crctmp0[15:0] - end - attribute \src "ls180.v:1506.12-1506.54" - process $proc$ls180.v:1506$3484 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp1 $1\main_sdcore_crc16_inserter_crctmp1[15:0] - end - attribute \src "ls180.v:1507.12-1507.54" - process $proc$ls180.v:1507$3485 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp2 $1\main_sdcore_crc16_inserter_crctmp2[15:0] - end - attribute \src "ls180.v:1508.12-1508.54" - process $proc$ls180.v:1508$3486 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp3 $1\main_sdcore_crc16_inserter_crctmp3[15:0] - end - attribute \src "ls180.v:1509.5-1509.48" - process $proc$ls180.v:1509$3487 - assign { } { } - assign $1\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_sink_valid $1\main_sdcore_crc16_checker_sink_valid[0:0] - end - attribute \src "ls180.v:1510.5-1510.48" - process $proc$ls180.v:1510$3488 - assign { } { } - assign $1\main_sdcore_crc16_checker_sink_ready[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_sink_ready $1\main_sdcore_crc16_checker_sink_ready[0:0] - end - attribute \src "ls180.v:1511.5-1511.48" - process $proc$ls180.v:1511$3489 - assign { } { } - assign $1\main_sdcore_crc16_checker_sink_first[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_sink_first $1\main_sdcore_crc16_checker_sink_first[0:0] - end - attribute \src "ls180.v:1512.5-1512.47" - process $proc$ls180.v:1512$3490 - assign { } { } - assign $1\main_sdcore_crc16_checker_sink_last[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_sink_last $1\main_sdcore_crc16_checker_sink_last[0:0] - end - attribute \src "ls180.v:1513.11-1513.61" - process $proc$ls180.v:1513$3491 - assign { } { } - assign $1\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdcore_crc16_checker_sink_payload_data $1\main_sdcore_crc16_checker_sink_payload_data[7:0] - end - attribute \src "ls180.v:1514.5-1514.50" - process $proc$ls180.v:1514$3492 - assign { } { } - assign $1\main_sdcore_crc16_checker_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_source_valid $1\main_sdcore_crc16_checker_source_valid[0:0] - end - attribute \src "ls180.v:1516.5-1516.50" - process $proc$ls180.v:1516$3493 - assign { } { } - assign $0\main_sdcore_crc16_checker_source_first[0:0] 1'0 - sync always - update \main_sdcore_crc16_checker_source_first $0\main_sdcore_crc16_checker_source_first[0:0] - sync init - end - attribute \src "ls180.v:1519.11-1519.47" - process $proc$ls180.v:1519$3494 - assign { } { } - assign $1\main_sdcore_crc16_checker_val[7:0] 8'00000000 - sync always - sync init - update \main_sdcore_crc16_checker_val $1\main_sdcore_crc16_checker_val[7:0] - end - attribute \src "ls180.v:152.12-152.78" - process $proc$ls180.v:152$2904 - assign { } { } - assign $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] 16'0000000000000000 - sync always - update \main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i $0\main_libresocsim_libresoc_constraintmanager_obj_sdram_dq_i[15:0] - sync init - end - attribute \src "ls180.v:1520.11-1520.47" - process $proc$ls180.v:1520$3495 - assign { } { } - assign $1\main_sdcore_crc16_checker_cnt[3:0] 4'0000 - sync always - sync init - update \main_sdcore_crc16_checker_cnt $1\main_sdcore_crc16_checker_cnt[3:0] - end - attribute \src "ls180.v:1521.12-1521.58" - process $proc$ls180.v:1521$3496 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crc0_crcreg0 $1\main_sdcore_crc16_checker_crc0_crcreg0[15:0] - end - attribute \src "ls180.v:1525.12-1525.54" - process $proc$ls180.v:1525$3497 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crc0_crc $1\main_sdcore_crc16_checker_crc0_crc[15:0] - end - attribute \src "ls180.v:1526.5-1526.46" - process $proc$ls180.v:1526$3498 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_crc0_clr $1\main_sdcore_crc16_checker_crc0_clr[0:0] - end - attribute \src "ls180.v:1528.12-1528.58" - process $proc$ls180.v:1528$3499 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crc1_crcreg0 $1\main_sdcore_crc16_checker_crc1_crcreg0[15:0] - end - attribute \src "ls180.v:1532.12-1532.54" - process $proc$ls180.v:1532$3500 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crc1_crc $1\main_sdcore_crc16_checker_crc1_crc[15:0] - end - attribute \src "ls180.v:1533.5-1533.46" - process $proc$ls180.v:1533$3501 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_crc1_clr $1\main_sdcore_crc16_checker_crc1_clr[0:0] - end - attribute \src "ls180.v:1535.12-1535.58" - process $proc$ls180.v:1535$3502 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crc2_crcreg0 $1\main_sdcore_crc16_checker_crc2_crcreg0[15:0] - end - attribute \src "ls180.v:1539.12-1539.54" - process $proc$ls180.v:1539$3503 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crc2_crc $1\main_sdcore_crc16_checker_crc2_crc[15:0] - end - attribute \src "ls180.v:1540.5-1540.46" - process $proc$ls180.v:1540$3504 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_crc2_clr $1\main_sdcore_crc16_checker_crc2_clr[0:0] - end - attribute \src "ls180.v:1542.12-1542.58" - process $proc$ls180.v:1542$3505 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crc3_crcreg0 $1\main_sdcore_crc16_checker_crc3_crcreg0[15:0] - end - attribute \src "ls180.v:1546.12-1546.54" - process $proc$ls180.v:1546$3506 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crc3_crc $1\main_sdcore_crc16_checker_crc3_crc[15:0] - end - attribute \src "ls180.v:1547.5-1547.46" - process $proc$ls180.v:1547$3507 - assign { } { } - assign $1\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_crc3_clr $1\main_sdcore_crc16_checker_crc3_clr[0:0] - end - attribute \src "ls180.v:1549.12-1549.53" - process $proc$ls180.v:1549$3508 - assign { } { } - assign $1\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crctmp0 $1\main_sdcore_crc16_checker_crctmp0[15:0] - end - attribute \src "ls180.v:1550.12-1550.53" - process $proc$ls180.v:1550$3509 - assign { } { } - assign $1\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crctmp1 $1\main_sdcore_crc16_checker_crctmp1[15:0] - end - attribute \src "ls180.v:1551.12-1551.53" - process $proc$ls180.v:1551$3510 - assign { } { } - assign $1\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crctmp2 $1\main_sdcore_crc16_checker_crctmp2[15:0] - end - attribute \src "ls180.v:1552.12-1552.53" - process $proc$ls180.v:1552$3511 - assign { } { } - assign $1\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_crctmp3 $1\main_sdcore_crc16_checker_crctmp3[15:0] - end - attribute \src "ls180.v:1553.5-1553.43" - process $proc$ls180.v:1553$3512 - assign { } { } - assign $1\main_sdcore_crc16_checker_valid[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_checker_valid $1\main_sdcore_crc16_checker_valid[0:0] - end - attribute \src "ls180.v:1554.12-1554.51" - process $proc$ls180.v:1554$3513 - assign { } { } - assign $1\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_fifo0 $1\main_sdcore_crc16_checker_fifo0[15:0] - end - attribute \src "ls180.v:1555.12-1555.51" - process $proc$ls180.v:1555$3514 - assign { } { } - assign $1\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_fifo1 $1\main_sdcore_crc16_checker_fifo1[15:0] - end - attribute \src "ls180.v:1556.12-1556.51" - process $proc$ls180.v:1556$3515 - assign { } { } - assign $1\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_fifo2 $1\main_sdcore_crc16_checker_fifo2[15:0] - end - attribute \src "ls180.v:1557.12-1557.51" - process $proc$ls180.v:1557$3516 - assign { } { } - assign $1\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_checker_fifo3 $1\main_sdcore_crc16_checker_fifo3[15:0] - end - attribute \src "ls180.v:1559.11-1559.39" - process $proc$ls180.v:1559$3517 - assign { } { } - assign $1\main_sdcore_cmd_count[2:0] 3'000 - sync always - sync init - update \main_sdcore_cmd_count $1\main_sdcore_cmd_count[2:0] - end - attribute \src "ls180.v:1560.5-1560.32" - process $proc$ls180.v:1560$3518 - assign { } { } - assign $1\main_sdcore_cmd_done[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_done $1\main_sdcore_cmd_done[0:0] - end - attribute \src "ls180.v:1561.5-1561.33" - process $proc$ls180.v:1561$3519 - assign { } { } - assign $1\main_sdcore_cmd_error[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_error $1\main_sdcore_cmd_error[0:0] - end - attribute \src "ls180.v:1562.5-1562.35" - process $proc$ls180.v:1562$3520 - assign { } { } - assign $1\main_sdcore_cmd_timeout[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_timeout $1\main_sdcore_cmd_timeout[0:0] - end - attribute \src "ls180.v:1564.12-1564.42" - process $proc$ls180.v:1564$3521 - assign { } { } - assign $1\main_sdcore_data_count[31:0] 0 - sync always - sync init - update \main_sdcore_data_count $1\main_sdcore_data_count[31:0] - end - attribute \src "ls180.v:1565.5-1565.33" - process $proc$ls180.v:1565$3522 - assign { } { } - assign $1\main_sdcore_data_done[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_done $1\main_sdcore_data_done[0:0] - end - attribute \src "ls180.v:1566.5-1566.34" - process $proc$ls180.v:1566$3523 - assign { } { } - assign $1\main_sdcore_data_error[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_error $1\main_sdcore_data_error[0:0] - end - attribute \src "ls180.v:1567.5-1567.36" - process $proc$ls180.v:1567$3524 - assign { } { } - assign $1\main_sdcore_data_timeout[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_timeout $1\main_sdcore_data_timeout[0:0] - end - attribute \src "ls180.v:1576.11-1576.41" - process $proc$ls180.v:1576$3525 - assign { } { } - assign $0\main_interface0_bus_cti[2:0] 3'000 - sync always - update \main_interface0_bus_cti $0\main_interface0_bus_cti[2:0] - sync init - end - attribute \src "ls180.v:1577.11-1577.41" - process $proc$ls180.v:1577$3526 - assign { } { } - assign $0\main_interface0_bus_bte[1:0] 2'00 - sync always - update \main_interface0_bus_bte $0\main_interface0_bus_bte[1:0] - sync init - end - attribute \src "ls180.v:1600.11-1600.45" - process $proc$ls180.v:1600$3527 - assign { } { } - assign $1\main_sdblock2mem_fifo_level[5:0] 6'000000 - sync always - sync init - update \main_sdblock2mem_fifo_level $1\main_sdblock2mem_fifo_level[5:0] - end - attribute \src "ls180.v:1601.5-1601.41" - process $proc$ls180.v:1601$3528 - assign { } { } - assign $0\main_sdblock2mem_fifo_replace[0:0] 1'0 - sync always - update \main_sdblock2mem_fifo_replace $0\main_sdblock2mem_fifo_replace[0:0] - sync init - end - attribute \src "ls180.v:1602.11-1602.47" - process $proc$ls180.v:1602$3529 - assign { } { } - assign $1\main_sdblock2mem_fifo_produce[4:0] 5'00000 - sync always - sync init - update \main_sdblock2mem_fifo_produce $1\main_sdblock2mem_fifo_produce[4:0] - end - attribute \src "ls180.v:1603.11-1603.47" - process $proc$ls180.v:1603$3530 - assign { } { } - assign $1\main_sdblock2mem_fifo_consume[4:0] 5'00000 - sync always - sync init - update \main_sdblock2mem_fifo_consume $1\main_sdblock2mem_fifo_consume[4:0] - end - attribute \src "ls180.v:1604.11-1604.50" - process $proc$ls180.v:1604$3531 - assign { } { } - assign $1\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 - sync always - sync init - update \main_sdblock2mem_fifo_wrport_adr $1\main_sdblock2mem_fifo_wrport_adr[4:0] - end - attribute \src "ls180.v:1624.5-1624.51" - process $proc$ls180.v:1624$3532 - assign { } { } - assign $1\main_sdblock2mem_converter_source_first[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_converter_source_first $1\main_sdblock2mem_converter_source_first[0:0] - end - attribute \src "ls180.v:1625.5-1625.50" - process $proc$ls180.v:1625$3533 - assign { } { } - assign $1\main_sdblock2mem_converter_source_last[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_converter_source_last $1\main_sdblock2mem_converter_source_last[0:0] - end - attribute \src "ls180.v:1626.12-1626.66" - process $proc$ls180.v:1626$3534 - assign { } { } - assign $1\main_sdblock2mem_converter_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_sdblock2mem_converter_source_payload_data $1\main_sdblock2mem_converter_source_payload_data[63:0] - end - attribute \src "ls180.v:1627.11-1627.77" - process $proc$ls180.v:1627$3535 - assign { } { } - assign $1\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] 4'0000 - sync always - sync init - update \main_sdblock2mem_converter_source_payload_valid_token_count $1\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] - end - attribute \src "ls180.v:1628.11-1628.50" - process $proc$ls180.v:1628$3536 - assign { } { } - assign $1\main_sdblock2mem_converter_demux[2:0] 3'000 - sync always - sync init - update \main_sdblock2mem_converter_demux $1\main_sdblock2mem_converter_demux[2:0] - end - attribute \src "ls180.v:1630.5-1630.49" - process $proc$ls180.v:1630$3537 - assign { } { } - assign $1\main_sdblock2mem_converter_strobe_all[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_converter_strobe_all $1\main_sdblock2mem_converter_strobe_all[0:0] - end - attribute \src "ls180.v:1636.5-1636.45" - process $proc$ls180.v:1636$3538 - assign { } { } - assign $1\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_sink_sink_valid1 $1\main_sdblock2mem_sink_sink_valid1[0:0] - end - attribute \src "ls180.v:1638.12-1638.62" - process $proc$ls180.v:1638$3539 - assign { } { } - assign $1\main_sdblock2mem_sink_sink_payload_address[31:0] 0 - sync always - sync init - update \main_sdblock2mem_sink_sink_payload_address $1\main_sdblock2mem_sink_sink_payload_address[31:0] - end - attribute \src "ls180.v:1639.12-1639.60" - process $proc$ls180.v:1639$3540 - assign { } { } - assign $1\main_sdblock2mem_sink_sink_payload_data1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_sdblock2mem_sink_sink_payload_data1 $1\main_sdblock2mem_sink_sink_payload_data1[63:0] - end - attribute \src "ls180.v:1641.5-1641.57" - process $proc$ls180.v:1641$3541 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_sink_ready $1\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] - end - attribute \src "ls180.v:1645.12-1645.67" - process $proc$ls180.v:1645$3542 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_base_storage $1\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] - end - attribute \src "ls180.v:1646.5-1646.54" - process $proc$ls180.v:1646$3543 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_base_re $1\main_sdblock2mem_wishbonedmawriter_base_re[0:0] - end - attribute \src "ls180.v:1647.12-1647.69" - process $proc$ls180.v:1647$3544 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_length_storage $1\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] - end - attribute \src "ls180.v:1648.5-1648.56" - process $proc$ls180.v:1648$3545 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_length_re $1\main_sdblock2mem_wishbonedmawriter_length_re[0:0] - end - attribute \src "ls180.v:1649.5-1649.61" - process $proc$ls180.v:1649$3546 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_enable_storage $1\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] - end - attribute \src "ls180.v:1650.5-1650.56" - process $proc$ls180.v:1650$3547 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_enable_re $1\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] - end - attribute \src "ls180.v:1651.5-1651.53" - process $proc$ls180.v:1651$3548 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_status $1\main_sdblock2mem_wishbonedmawriter_status[0:0] - end - attribute \src "ls180.v:1653.5-1653.59" - process $proc$ls180.v:1653$3549 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_loop_storage $1\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] - end - attribute \src "ls180.v:1654.5-1654.54" - process $proc$ls180.v:1654$3550 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_loop_re $1\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] - end - attribute \src "ls180.v:1656.12-1656.61" - process $proc$ls180.v:1656$3551 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_offset $1\main_sdblock2mem_wishbonedmawriter_offset[31:0] - end - attribute \src "ls180.v:1659.12-1659.43" - process $proc$ls180.v:1659$3552 - assign { } { } - assign $1\main_interface1_bus_adr[31:0] 0 - sync always - sync init - update \main_interface1_bus_adr $1\main_interface1_bus_adr[31:0] - end - attribute \src "ls180.v:1660.12-1660.45" - process $proc$ls180.v:1660$3553 - assign { } { } - assign $0\main_interface1_bus_dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - update \main_interface1_bus_dat_w $0\main_interface1_bus_dat_w[63:0] - sync init - end - attribute \src "ls180.v:1662.11-1662.41" - process $proc$ls180.v:1662$3554 - assign { } { } - assign $1\main_interface1_bus_sel[7:0] 8'00000000 - sync always - sync init - update \main_interface1_bus_sel $1\main_interface1_bus_sel[7:0] - end - attribute \src "ls180.v:1663.5-1663.35" - process $proc$ls180.v:1663$3555 - assign { } { } - assign $1\main_interface1_bus_cyc[0:0] 1'0 - sync always - sync init - update \main_interface1_bus_cyc $1\main_interface1_bus_cyc[0:0] - end - attribute \src "ls180.v:1664.5-1664.35" - process $proc$ls180.v:1664$3556 - assign { } { } - assign $1\main_interface1_bus_stb[0:0] 1'0 - sync always - sync init - update \main_interface1_bus_stb $1\main_interface1_bus_stb[0:0] - end - attribute \src "ls180.v:1666.5-1666.34" - process $proc$ls180.v:1666$3557 - assign { } { } - assign $1\main_interface1_bus_we[0:0] 1'0 - sync always - sync init - update \main_interface1_bus_we $1\main_interface1_bus_we[0:0] - end - attribute \src "ls180.v:1667.11-1667.41" - process $proc$ls180.v:1667$3558 - assign { } { } - assign $0\main_interface1_bus_cti[2:0] 3'000 - sync always - update \main_interface1_bus_cti $0\main_interface1_bus_cti[2:0] - sync init - end - attribute \src "ls180.v:1668.11-1668.41" - process $proc$ls180.v:1668$3559 - assign { } { } - assign $0\main_interface1_bus_bte[1:0] 2'00 - sync always - update \main_interface1_bus_bte $0\main_interface1_bus_bte[1:0] - sync init - end - attribute \src "ls180.v:1675.5-1675.43" - process $proc$ls180.v:1675$3560 - assign { } { } - assign $1\main_sdmem2block_dma_sink_valid[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_sink_valid $1\main_sdmem2block_dma_sink_valid[0:0] - end - attribute \src "ls180.v:1676.5-1676.43" - process $proc$ls180.v:1676$3561 - assign { } { } - assign $1\main_sdmem2block_dma_sink_ready[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_sink_ready $1\main_sdmem2block_dma_sink_ready[0:0] - end - attribute \src "ls180.v:1677.5-1677.42" - process $proc$ls180.v:1677$3562 - assign { } { } - assign $1\main_sdmem2block_dma_sink_last[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_sink_last $1\main_sdmem2block_dma_sink_last[0:0] - end - attribute \src "ls180.v:1678.12-1678.61" - process $proc$ls180.v:1678$3563 - assign { } { } - assign $1\main_sdmem2block_dma_sink_payload_address[31:0] 0 - sync always - sync init - update \main_sdmem2block_dma_sink_payload_address $1\main_sdmem2block_dma_sink_payload_address[31:0] - end - attribute \src "ls180.v:1679.5-1679.45" - process $proc$ls180.v:1679$3564 - assign { } { } - assign $1\main_sdmem2block_dma_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_source_valid $1\main_sdmem2block_dma_source_valid[0:0] - end - attribute \src "ls180.v:1681.5-1681.45" - process $proc$ls180.v:1681$3565 - assign { } { } - assign $0\main_sdmem2block_dma_source_first[0:0] 1'0 - sync always - update \main_sdmem2block_dma_source_first $0\main_sdmem2block_dma_source_first[0:0] - sync init - end - attribute \src "ls180.v:1682.5-1682.44" - process $proc$ls180.v:1682$3566 - assign { } { } - assign $1\main_sdmem2block_dma_source_last[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_source_last $1\main_sdmem2block_dma_source_last[0:0] - end - attribute \src "ls180.v:1683.12-1683.60" - process $proc$ls180.v:1683$3567 - assign { } { } - assign $1\main_sdmem2block_dma_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_sdmem2block_dma_source_payload_data $1\main_sdmem2block_dma_source_payload_data[63:0] - end - attribute \src "ls180.v:1684.12-1684.45" - process $proc$ls180.v:1684$3568 - assign { } { } - assign $1\main_sdmem2block_dma_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_sdmem2block_dma_data $1\main_sdmem2block_dma_data[63:0] - end - attribute \src "ls180.v:1685.12-1685.53" - process $proc$ls180.v:1685$3569 - assign { } { } - assign $1\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_sdmem2block_dma_base_storage $1\main_sdmem2block_dma_base_storage[63:0] - end - attribute \src "ls180.v:1686.5-1686.40" - process $proc$ls180.v:1686$3570 - assign { } { } - assign $1\main_sdmem2block_dma_base_re[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_base_re $1\main_sdmem2block_dma_base_re[0:0] - end - attribute \src "ls180.v:1687.12-1687.55" - process $proc$ls180.v:1687$3571 - assign { } { } - assign $1\main_sdmem2block_dma_length_storage[31:0] 0 - sync always - sync init - update \main_sdmem2block_dma_length_storage $1\main_sdmem2block_dma_length_storage[31:0] - end - attribute \src "ls180.v:1688.5-1688.42" - process $proc$ls180.v:1688$3572 - assign { } { } - assign $1\main_sdmem2block_dma_length_re[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_length_re $1\main_sdmem2block_dma_length_re[0:0] - end - attribute \src "ls180.v:1689.5-1689.47" - process $proc$ls180.v:1689$3573 - assign { } { } - assign $1\main_sdmem2block_dma_enable_storage[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_enable_storage $1\main_sdmem2block_dma_enable_storage[0:0] - end - attribute \src "ls180.v:169.5-169.40" - process $proc$ls180.v:169$2905 - assign { } { } - assign $1\main_libresocsim_ram_bus_ack[0:0] 1'0 - sync always - sync init - update \main_libresocsim_ram_bus_ack $1\main_libresocsim_ram_bus_ack[0:0] - end - attribute \src "ls180.v:1690.5-1690.42" - process $proc$ls180.v:1690$3574 - assign { } { } - assign $1\main_sdmem2block_dma_enable_re[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_enable_re $1\main_sdmem2block_dma_enable_re[0:0] - end - attribute \src "ls180.v:1691.5-1691.44" - process $proc$ls180.v:1691$3575 - assign { } { } - assign $1\main_sdmem2block_dma_done_status[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_done_status $1\main_sdmem2block_dma_done_status[0:0] - end - attribute \src "ls180.v:1693.5-1693.45" - process $proc$ls180.v:1693$3576 - assign { } { } - assign $1\main_sdmem2block_dma_loop_storage[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_loop_storage $1\main_sdmem2block_dma_loop_storage[0:0] - end - attribute \src "ls180.v:1694.5-1694.40" - process $proc$ls180.v:1694$3577 - assign { } { } - assign $1\main_sdmem2block_dma_loop_re[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_loop_re $1\main_sdmem2block_dma_loop_re[0:0] - end - attribute \src "ls180.v:1698.12-1698.47" - process $proc$ls180.v:1698$3578 - assign { } { } - assign $1\main_sdmem2block_dma_offset[31:0] 0 - sync always - sync init - update \main_sdmem2block_dma_offset $1\main_sdmem2block_dma_offset[31:0] - end - attribute \src "ls180.v:1710.11-1710.64" - process $proc$ls180.v:1710$3579 - assign { } { } - assign $1\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 - sync always - sync init - update \main_sdmem2block_converter_source_payload_data $1\main_sdmem2block_converter_source_payload_data[7:0] - end - attribute \src "ls180.v:1712.11-1712.48" - process $proc$ls180.v:1712$3580 - assign { } { } - assign $1\main_sdmem2block_converter_mux[2:0] 3'000 - sync always - sync init - update \main_sdmem2block_converter_mux $1\main_sdmem2block_converter_mux[2:0] - end - attribute \src "ls180.v:173.5-173.40" - process $proc$ls180.v:173$2906 - assign { } { } - assign $0\main_libresocsim_ram_bus_err[0:0] 1'0 - sync always - update \main_libresocsim_ram_bus_err $0\main_libresocsim_ram_bus_err[0:0] - sync init - end - attribute \src "ls180.v:1736.11-1736.45" - process $proc$ls180.v:1736$3581 - assign { } { } - assign $1\main_sdmem2block_fifo_level[5:0] 6'000000 - sync always - sync init - update \main_sdmem2block_fifo_level $1\main_sdmem2block_fifo_level[5:0] - end - attribute \src "ls180.v:1737.5-1737.41" - process $proc$ls180.v:1737$3582 - assign { } { } - assign $0\main_sdmem2block_fifo_replace[0:0] 1'0 - sync always - update \main_sdmem2block_fifo_replace $0\main_sdmem2block_fifo_replace[0:0] - sync init - end - attribute \src "ls180.v:1738.11-1738.47" - process $proc$ls180.v:1738$3583 - assign { } { } - assign $1\main_sdmem2block_fifo_produce[4:0] 5'00000 - sync always - sync init - update \main_sdmem2block_fifo_produce $1\main_sdmem2block_fifo_produce[4:0] - end - attribute \src "ls180.v:1739.11-1739.47" - process $proc$ls180.v:1739$3584 - assign { } { } - assign $1\main_sdmem2block_fifo_consume[4:0] 5'00000 - sync always - sync init - update \main_sdmem2block_fifo_consume $1\main_sdmem2block_fifo_consume[4:0] - end - attribute \src "ls180.v:1740.11-1740.50" - process $proc$ls180.v:1740$3585 - assign { } { } - assign $1\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 - sync always - sync init - update \main_sdmem2block_fifo_wrport_adr $1\main_sdmem2block_fifo_wrport_adr[4:0] - end - attribute \src "ls180.v:1753.5-1753.36" - process $proc$ls180.v:1753$3586 - assign { } { } - assign $1\builder_converter0_state[0:0] 1'0 - sync always - sync init - update \builder_converter0_state $1\builder_converter0_state[0:0] - end - attribute \src "ls180.v:1754.5-1754.41" - process $proc$ls180.v:1754$3587 - assign { } { } - assign $1\builder_converter0_next_state[0:0] 1'0 - sync always - sync init - update \builder_converter0_next_state $1\builder_converter0_next_state[0:0] - end - attribute \src "ls180.v:1755.5-1755.57" - process $proc$ls180.v:1755$3588 - assign { } { } - assign $1\main_converter0_counter_converter0_next_value[0:0] 1'0 - sync always - sync init - update \main_converter0_counter_converter0_next_value $1\main_converter0_counter_converter0_next_value[0:0] - end - attribute \src "ls180.v:1756.5-1756.60" - process $proc$ls180.v:1756$3589 - assign { } { } - assign $1\main_converter0_counter_converter0_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_converter0_counter_converter0_next_value_ce $1\main_converter0_counter_converter0_next_value_ce[0:0] - end - attribute \src "ls180.v:1757.5-1757.36" - process $proc$ls180.v:1757$3590 - assign { } { } - assign $1\builder_converter1_state[0:0] 1'0 - sync always - sync init - update \builder_converter1_state $1\builder_converter1_state[0:0] - end - attribute \src "ls180.v:1758.5-1758.41" - process $proc$ls180.v:1758$3591 - assign { } { } - assign $1\builder_converter1_next_state[0:0] 1'0 - sync always - sync init - update \builder_converter1_next_state $1\builder_converter1_next_state[0:0] - end - attribute \src "ls180.v:1759.5-1759.57" - process $proc$ls180.v:1759$3592 - assign { } { } - assign $1\main_converter1_counter_converter1_next_value[0:0] 1'0 - sync always - sync init - update \main_converter1_counter_converter1_next_value $1\main_converter1_counter_converter1_next_value[0:0] - end - attribute \src "ls180.v:176.11-176.37" - process $proc$ls180.v:176$2907 - assign { } { } - assign $1\main_libresocsim_we[7:0] 8'00000000 - sync always - sync init - update \main_libresocsim_we $1\main_libresocsim_we[7:0] - end - attribute \src "ls180.v:1760.5-1760.60" - process $proc$ls180.v:1760$3593 - assign { } { } - assign $1\main_converter1_counter_converter1_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_converter1_counter_converter1_next_value_ce $1\main_converter1_counter_converter1_next_value_ce[0:0] - end - attribute \src "ls180.v:1761.5-1761.36" - process $proc$ls180.v:1761$3594 - assign { } { } - assign $1\builder_converter2_state[0:0] 1'0 - sync always - sync init - update \builder_converter2_state $1\builder_converter2_state[0:0] - end - attribute \src "ls180.v:1762.5-1762.41" - process $proc$ls180.v:1762$3595 - assign { } { } - assign $1\builder_converter2_next_state[0:0] 1'0 - sync always - sync init - update \builder_converter2_next_state $1\builder_converter2_next_state[0:0] - end - attribute \src "ls180.v:1763.5-1763.60" - process $proc$ls180.v:1763$3596 - assign { } { } - assign $1\main_socbushandler_counter_converter2_next_value[0:0] 1'0 - sync always - sync init - update \main_socbushandler_counter_converter2_next_value $1\main_socbushandler_counter_converter2_next_value[0:0] - end - attribute \src "ls180.v:1764.5-1764.63" - process $proc$ls180.v:1764$3597 - assign { } { } - assign $1\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_socbushandler_counter_converter2_next_value_ce $1\main_socbushandler_counter_converter2_next_value_ce[0:0] - end - attribute \src "ls180.v:1765.11-1765.41" - process $proc$ls180.v:1765$3598 - assign { } { } - assign $1\builder_refresher_state[1:0] 2'00 - sync always - sync init - update \builder_refresher_state $1\builder_refresher_state[1:0] - end - attribute \src "ls180.v:1766.11-1766.46" - process $proc$ls180.v:1766$3599 - assign { } { } - assign $1\builder_refresher_next_state[1:0] 2'00 - sync always - sync init - update \builder_refresher_next_state $1\builder_refresher_next_state[1:0] - end - attribute \src "ls180.v:1767.11-1767.44" - process $proc$ls180.v:1767$3600 - assign { } { } - assign $1\builder_bankmachine0_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine0_state $1\builder_bankmachine0_state[2:0] - end - attribute \src "ls180.v:1768.11-1768.49" - process $proc$ls180.v:1768$3601 - assign { } { } - assign $1\builder_bankmachine0_next_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine0_next_state $1\builder_bankmachine0_next_state[2:0] - end - attribute \src "ls180.v:1769.11-1769.44" - process $proc$ls180.v:1769$3602 - assign { } { } - assign $1\builder_bankmachine1_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine1_state $1\builder_bankmachine1_state[2:0] - end - attribute \src "ls180.v:1770.11-1770.49" - process $proc$ls180.v:1770$3603 - assign { } { } - assign $1\builder_bankmachine1_next_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine1_next_state $1\builder_bankmachine1_next_state[2:0] - end - attribute \src "ls180.v:1771.11-1771.44" - process $proc$ls180.v:1771$3604 - assign { } { } - assign $1\builder_bankmachine2_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine2_state $1\builder_bankmachine2_state[2:0] - end - attribute \src "ls180.v:1772.11-1772.49" - process $proc$ls180.v:1772$3605 - assign { } { } - assign $1\builder_bankmachine2_next_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine2_next_state $1\builder_bankmachine2_next_state[2:0] - end - attribute \src "ls180.v:1773.11-1773.44" - process $proc$ls180.v:1773$3606 - assign { } { } - assign $1\builder_bankmachine3_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine3_state $1\builder_bankmachine3_state[2:0] - end - attribute \src "ls180.v:1774.11-1774.49" - process $proc$ls180.v:1774$3607 - assign { } { } - assign $1\builder_bankmachine3_next_state[2:0] 3'000 - sync always - sync init - update \builder_bankmachine3_next_state $1\builder_bankmachine3_next_state[2:0] - end - attribute \src "ls180.v:1775.11-1775.43" - process $proc$ls180.v:1775$3608 - assign { } { } - assign $1\builder_multiplexer_state[2:0] 3'000 - sync always - sync init - update \builder_multiplexer_state $1\builder_multiplexer_state[2:0] - end - attribute \src "ls180.v:1776.11-1776.48" - process $proc$ls180.v:1776$3609 - assign { } { } - assign $1\builder_multiplexer_next_state[2:0] 3'000 - sync always - sync init - update \builder_multiplexer_next_state $1\builder_multiplexer_next_state[2:0] - end - attribute \src "ls180.v:178.12-178.49" - process $proc$ls180.v:178$2908 - assign { } { } - assign $1\main_libresocsim_load_storage[31:0] 0 - sync always - sync init - update \main_libresocsim_load_storage $1\main_libresocsim_load_storage[31:0] - end - attribute \src "ls180.v:1789.5-1789.27" - process $proc$ls180.v:1789$3610 - assign { } { } - assign $0\builder_locked0[0:0] 1'0 - sync always - update \builder_locked0 $0\builder_locked0[0:0] - sync init - end - attribute \src "ls180.v:179.5-179.36" - process $proc$ls180.v:179$2909 - assign { } { } - assign $1\main_libresocsim_load_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_load_re $1\main_libresocsim_load_re[0:0] - end - attribute \src "ls180.v:1790.5-1790.27" - process $proc$ls180.v:1790$3611 - assign { } { } - assign $0\builder_locked1[0:0] 1'0 - sync always - update \builder_locked1 $0\builder_locked1[0:0] - sync init - end - attribute \src "ls180.v:1791.5-1791.27" - process $proc$ls180.v:1791$3612 - assign { } { } - assign $0\builder_locked2[0:0] 1'0 - sync always - update \builder_locked2 $0\builder_locked2[0:0] - sync init - end - attribute \src "ls180.v:1792.5-1792.27" - process $proc$ls180.v:1792$3613 - assign { } { } - assign $0\builder_locked3[0:0] 1'0 - sync always - update \builder_locked3 $0\builder_locked3[0:0] - sync init - end - attribute \src "ls180.v:1793.5-1793.42" - process $proc$ls180.v:1793$3614 - assign { } { } - assign $1\builder_new_master_wdata_ready[0:0] 1'0 - sync always - sync init - update \builder_new_master_wdata_ready $1\builder_new_master_wdata_ready[0:0] - end - attribute \src "ls180.v:1794.5-1794.43" - process $proc$ls180.v:1794$3615 - assign { } { } - assign $1\builder_new_master_rdata_valid0[0:0] 1'0 - sync always - sync init - update \builder_new_master_rdata_valid0 $1\builder_new_master_rdata_valid0[0:0] - end - attribute \src "ls180.v:1795.5-1795.43" - process $proc$ls180.v:1795$3616 - assign { } { } - assign $1\builder_new_master_rdata_valid1[0:0] 1'0 - sync always - sync init - update \builder_new_master_rdata_valid1 $1\builder_new_master_rdata_valid1[0:0] - end - attribute \src "ls180.v:1796.5-1796.43" - process $proc$ls180.v:1796$3617 - assign { } { } - assign $1\builder_new_master_rdata_valid2[0:0] 1'0 - sync always - sync init - update \builder_new_master_rdata_valid2 $1\builder_new_master_rdata_valid2[0:0] - end - attribute \src "ls180.v:1797.5-1797.43" - process $proc$ls180.v:1797$3618 - assign { } { } - assign $1\builder_new_master_rdata_valid3[0:0] 1'0 - sync always - sync init - update \builder_new_master_rdata_valid3 $1\builder_new_master_rdata_valid3[0:0] - end - attribute \src "ls180.v:1798.5-1798.35" - process $proc$ls180.v:1798$3619 - assign { } { } - assign $1\builder_converter_state[0:0] 1'0 - sync always - sync init - update \builder_converter_state $1\builder_converter_state[0:0] - end - attribute \src "ls180.v:1799.5-1799.40" - process $proc$ls180.v:1799$3620 - assign { } { } - assign $1\builder_converter_next_state[0:0] 1'0 - sync always - sync init - update \builder_converter_next_state $1\builder_converter_next_state[0:0] - end - attribute \src "ls180.v:180.12-180.51" - process $proc$ls180.v:180$2910 - assign { } { } - assign $1\main_libresocsim_reload_storage[31:0] 0 - sync always - sync init - update \main_libresocsim_reload_storage $1\main_libresocsim_reload_storage[31:0] - end - attribute \src "ls180.v:1800.5-1800.55" - process $proc$ls180.v:1800$3621 - assign { } { } - assign $1\main_converter_counter_converter_next_value[0:0] 1'0 - sync always - sync init - update \main_converter_counter_converter_next_value $1\main_converter_counter_converter_next_value[0:0] - end - attribute \src "ls180.v:1801.5-1801.58" - process $proc$ls180.v:1801$3622 - assign { } { } - assign $1\main_converter_counter_converter_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_converter_counter_converter_next_value_ce $1\main_converter_counter_converter_next_value_ce[0:0] - end - attribute \src "ls180.v:1802.11-1802.42" - process $proc$ls180.v:1802$3623 - assign { } { } - assign $1\builder_spimaster0_state[1:0] 2'00 - sync always - sync init - update \builder_spimaster0_state $1\builder_spimaster0_state[1:0] - end - attribute \src "ls180.v:1803.11-1803.47" - process $proc$ls180.v:1803$3624 - assign { } { } - assign $1\builder_spimaster0_next_state[1:0] 2'00 - sync always - sync init - update \builder_spimaster0_next_state $1\builder_spimaster0_next_state[1:0] - end - attribute \src "ls180.v:1804.11-1804.62" - process $proc$ls180.v:1804$3625 - assign { } { } - assign $1\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 - sync always - sync init - update \main_spimaster27_count_spimaster0_next_value $1\main_spimaster27_count_spimaster0_next_value[2:0] - end - attribute \src "ls180.v:1805.5-1805.59" - process $proc$ls180.v:1805$3626 - assign { } { } - assign $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_spimaster27_count_spimaster0_next_value_ce $1\main_spimaster27_count_spimaster0_next_value_ce[0:0] - end - attribute \src "ls180.v:1806.11-1806.42" - process $proc$ls180.v:1806$3627 - assign { } { } - assign $1\builder_spimaster1_state[1:0] 2'00 - sync always - sync init - update \builder_spimaster1_state $1\builder_spimaster1_state[1:0] - end - attribute \src "ls180.v:1807.11-1807.47" - process $proc$ls180.v:1807$3628 - assign { } { } - assign $1\builder_spimaster1_next_state[1:0] 2'00 - sync always - sync init - update \builder_spimaster1_next_state $1\builder_spimaster1_next_state[1:0] - end - attribute \src "ls180.v:1808.11-1808.60" - process $proc$ls180.v:1808$3629 - assign { } { } - assign $1\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 - sync always - sync init - update \main_spisdcard_count_spimaster1_next_value $1\main_spisdcard_count_spimaster1_next_value[2:0] - end - attribute \src "ls180.v:1809.5-1809.57" - process $proc$ls180.v:1809$3630 - assign { } { } - assign $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_spisdcard_count_spimaster1_next_value_ce $1\main_spisdcard_count_spimaster1_next_value_ce[0:0] - end - attribute \src "ls180.v:181.5-181.38" - process $proc$ls180.v:181$2911 - assign { } { } - assign $1\main_libresocsim_reload_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_reload_re $1\main_libresocsim_reload_re[0:0] - end - attribute \src "ls180.v:1810.5-1810.41" - process $proc$ls180.v:1810$3631 - assign { } { } - assign $1\builder_sdphy_sdphyinit_state[0:0] 1'0 - sync always - sync init - update \builder_sdphy_sdphyinit_state $1\builder_sdphy_sdphyinit_state[0:0] - end - attribute \src "ls180.v:1811.5-1811.46" - process $proc$ls180.v:1811$3632 - assign { } { } - assign $1\builder_sdphy_sdphyinit_next_state[0:0] 1'0 - sync always - sync init - update \builder_sdphy_sdphyinit_next_state $1\builder_sdphy_sdphyinit_next_state[0:0] - end - attribute \src "ls180.v:1812.11-1812.66" - process $proc$ls180.v:1812$3633 - assign { } { } - assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_init_count_sdphy_sdphyinit_next_value $1\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] - end - attribute \src "ls180.v:1813.5-1813.63" - process $proc$ls180.v:1813$3634 - assign { } { } - assign $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $1\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] - end - attribute \src "ls180.v:1814.11-1814.47" - process $proc$ls180.v:1814$3635 - assign { } { } - assign $1\builder_sdphy_sdphycmdw_state[1:0] 2'00 - sync always - sync init - update \builder_sdphy_sdphycmdw_state $1\builder_sdphy_sdphycmdw_state[1:0] - end - attribute \src "ls180.v:1815.11-1815.52" - process $proc$ls180.v:1815$3636 - assign { } { } - assign $1\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 - sync always - sync init - update \builder_sdphy_sdphycmdw_next_state $1\builder_sdphy_sdphycmdw_next_state[1:0] - end - attribute \src "ls180.v:1816.11-1816.66" - process $proc$ls180.v:1816$3637 - assign { } { } - assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] - end - attribute \src "ls180.v:1817.5-1817.63" - process $proc$ls180.v:1817$3638 - assign { } { } - assign $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $1\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] - end - attribute \src "ls180.v:1818.11-1818.47" - process $proc$ls180.v:1818$3639 - assign { } { } - assign $1\builder_sdphy_sdphycmdr_state[2:0] 3'000 - sync always - sync init - update \builder_sdphy_sdphycmdr_state $1\builder_sdphy_sdphycmdr_state[2:0] - end - attribute \src "ls180.v:1819.11-1819.52" - process $proc$ls180.v:1819$3640 - assign { } { } - assign $1\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 - sync always - sync init - update \builder_sdphy_sdphycmdr_next_state $1\builder_sdphy_sdphycmdr_next_state[2:0] - end - attribute \src "ls180.v:182.5-182.39" - process $proc$ls180.v:182$2912 - assign { } { } - assign $1\main_libresocsim_en_storage[0:0] 1'0 - sync always - sync init - update \main_libresocsim_en_storage $1\main_libresocsim_en_storage[0:0] - end - attribute \src "ls180.v:1820.11-1820.67" - process $proc$ls180.v:1820$3641 - assign { } { } - assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] - end - attribute \src "ls180.v:1821.5-1821.64" - process $proc$ls180.v:1821$3642 - assign { } { } - assign $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $1\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] - end - attribute \src "ls180.v:1822.12-1822.71" - process $proc$ls180.v:1822$3643 - assign { } { } - assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 - sync always - sync init - update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] - end - attribute \src "ls180.v:1823.5-1823.66" - process $proc$ls180.v:1823$3644 - assign { } { } - assign $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $1\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] - end - attribute \src "ls180.v:1824.5-1824.66" - process $proc$ls180.v:1824$3645 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] - end - attribute \src "ls180.v:1825.5-1825.69" - process $proc$ls180.v:1825$3646 - assign { } { } - assign $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 - sync always - sync init - update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $1\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] - end - attribute \src "ls180.v:1826.5-1826.41" - process $proc$ls180.v:1826$3647 - assign { } { } - assign $1\builder_sdphy_sdphycrcr_state[0:0] 1'0 - sync always - sync init - update \builder_sdphy_sdphycrcr_state $1\builder_sdphy_sdphycrcr_state[0:0] - end - attribute \src "ls180.v:1827.5-1827.46" - process $proc$ls180.v:1827$3648 - assign { } { } - assign $1\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 - sync always - sync init - update \builder_sdphy_sdphycrcr_next_state $1\builder_sdphy_sdphycrcr_next_state[0:0] - end - attribute \src "ls180.v:1828.5-1828.66" - process $proc$ls180.v:1828$3649 - assign { } { } - assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] - end - attribute \src "ls180.v:1829.5-1829.69" - process $proc$ls180.v:1829$3650 - assign { } { } - assign $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $1\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] - end - attribute \src "ls180.v:183.5-183.34" - process $proc$ls180.v:183$2913 - assign { } { } - assign $1\main_libresocsim_en_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_en_re $1\main_libresocsim_en_re[0:0] - end - attribute \src "ls180.v:1830.11-1830.41" - process $proc$ls180.v:1830$3651 - assign { } { } - assign $1\builder_sdphy_fsm_state[2:0] 3'000 - sync always - sync init - update \builder_sdphy_fsm_state $1\builder_sdphy_fsm_state[2:0] - end - attribute \src "ls180.v:1831.11-1831.46" - process $proc$ls180.v:1831$3652 - assign { } { } - assign $1\builder_sdphy_fsm_next_state[2:0] 3'000 - sync always - sync init - update \builder_sdphy_fsm_next_state $1\builder_sdphy_fsm_next_state[2:0] - end - attribute \src "ls180.v:1832.11-1832.61" - process $proc$ls180.v:1832$3653 - assign { } { } - assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 - sync always - sync init - update \main_sdphy_dataw_count_sdphy_fsm_next_value $1\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] - end - attribute \src "ls180.v:1833.5-1833.58" - process $proc$ls180.v:1833$3654 - assign { } { } - assign $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $1\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] - end - attribute \src "ls180.v:1834.11-1834.48" - process $proc$ls180.v:1834$3655 - assign { } { } - assign $1\builder_sdphy_sdphydatar_state[2:0] 3'000 - sync always - sync init - update \builder_sdphy_sdphydatar_state $1\builder_sdphy_sdphydatar_state[2:0] - end - attribute \src "ls180.v:1835.11-1835.53" - process $proc$ls180.v:1835$3656 - assign { } { } - assign $1\builder_sdphy_sdphydatar_next_state[2:0] 3'000 - sync always - sync init - update \builder_sdphy_sdphydatar_next_state $1\builder_sdphy_sdphydatar_next_state[2:0] - end - attribute \src "ls180.v:1836.11-1836.70" - process $proc$ls180.v:1836$3657 - assign { } { } - assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 - sync always - sync init - update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] - end - attribute \src "ls180.v:1837.5-1837.66" - process $proc$ls180.v:1837$3658 - assign { } { } - assign $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $1\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] - end - attribute \src "ls180.v:1838.12-1838.73" - process $proc$ls180.v:1838$3659 - assign { } { } - assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 - sync always - sync init - update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] - end - attribute \src "ls180.v:1839.5-1839.68" - process $proc$ls180.v:1839$3660 - assign { } { } - assign $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $1\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] - end - attribute \src "ls180.v:184.5-184.49" - process $proc$ls180.v:184$2914 - assign { } { } - assign $1\main_libresocsim_update_value_storage[0:0] 1'0 - sync always - sync init - update \main_libresocsim_update_value_storage $1\main_libresocsim_update_value_storage[0:0] - end - attribute \src "ls180.v:1840.5-1840.69" - process $proc$ls180.v:1840$3661 - assign { } { } - assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] - end - attribute \src "ls180.v:1841.5-1841.72" - process $proc$ls180.v:1841$3662 - assign { } { } - assign $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 - sync always - sync init - update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $1\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] - end - attribute \src "ls180.v:1842.5-1842.52" - process $proc$ls180.v:1842$3663 - assign { } { } - assign $1\builder_sdcore_crcupstreaminserter_state[0:0] 1'0 - sync always - sync init - update \builder_sdcore_crcupstreaminserter_state $1\builder_sdcore_crcupstreaminserter_state[0:0] - end - attribute \src "ls180.v:1843.5-1843.57" - process $proc$ls180.v:1843$3664 - assign { } { } - assign $1\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 - sync always - sync init - update \builder_sdcore_crcupstreaminserter_next_state $1\builder_sdcore_crcupstreaminserter_next_state[0:0] - end - attribute \src "ls180.v:1844.12-1844.93" - process $proc$ls180.v:1844$3665 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] - end - attribute \src "ls180.v:1845.5-1845.88" - process $proc$ls180.v:1845$3666 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $1\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] - end - attribute \src "ls180.v:1846.12-1846.93" - process $proc$ls180.v:1846$3667 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] - end - attribute \src "ls180.v:1847.5-1847.88" - process $proc$ls180.v:1847$3668 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $1\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] - end - attribute \src "ls180.v:1848.12-1848.93" - process $proc$ls180.v:1848$3669 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] - end - attribute \src "ls180.v:1849.5-1849.88" - process $proc$ls180.v:1849$3670 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $1\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] - end - attribute \src "ls180.v:185.5-185.44" - process $proc$ls180.v:185$2915 - assign { } { } - assign $1\main_libresocsim_update_value_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_update_value_re $1\main_libresocsim_update_value_re[0:0] - end - attribute \src "ls180.v:1850.12-1850.93" - process $proc$ls180.v:1850$3671 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] - end - attribute \src "ls180.v:1851.5-1851.88" - process $proc$ls180.v:1851$3672 - assign { } { } - assign $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $1\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] - end - attribute \src "ls180.v:1852.11-1852.87" - process $proc$ls180.v:1852$3673 - assign { } { } - assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 - sync always - sync init - update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] - end - attribute \src "ls180.v:1853.5-1853.84" - process $proc$ls180.v:1853$3674 - assign { } { } - assign $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 - sync always - sync init - update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $1\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] - end - attribute \src "ls180.v:1854.11-1854.42" - process $proc$ls180.v:1854$3675 - assign { } { } - assign $1\builder_sdcore_fsm_state[2:0] 3'000 - sync always - sync init - update \builder_sdcore_fsm_state $1\builder_sdcore_fsm_state[2:0] - end - attribute \src "ls180.v:1855.11-1855.47" - process $proc$ls180.v:1855$3676 - assign { } { } - assign $1\builder_sdcore_fsm_next_state[2:0] 3'000 - sync always - sync init - update \builder_sdcore_fsm_next_state $1\builder_sdcore_fsm_next_state[2:0] - end - attribute \src "ls180.v:1856.5-1856.55" - process $proc$ls180.v:1856$3677 - assign { } { } - assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] - end - attribute \src "ls180.v:1857.5-1857.58" - process $proc$ls180.v:1857$3678 - assign { } { } - assign $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $1\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] - end - attribute \src "ls180.v:1858.5-1858.56" - process $proc$ls180.v:1858$3679 - assign { } { } - assign $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_done_sdcore_fsm_next_value1 $1\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] - end - attribute \src "ls180.v:1859.5-1859.59" - process $proc$ls180.v:1859$3680 - assign { } { } - assign $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $1\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] - end - attribute \src "ls180.v:186.12-186.49" - process $proc$ls180.v:186$2916 - assign { } { } - assign $1\main_libresocsim_value_status[31:0] 0 - sync always - sync init - update \main_libresocsim_value_status $1\main_libresocsim_value_status[31:0] - end - attribute \src "ls180.v:1860.11-1860.62" - process $proc$ls180.v:1860$3681 - assign { } { } - assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 - sync always - sync init - update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] - end - attribute \src "ls180.v:1861.5-1861.59" - process $proc$ls180.v:1861$3682 - assign { } { } - assign $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $1\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] - end - attribute \src "ls180.v:1862.12-1862.65" - process $proc$ls180.v:1862$3683 - assign { } { } - assign $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 - sync always - sync init - update \main_sdcore_data_count_sdcore_fsm_next_value3 $1\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] - end - attribute \src "ls180.v:1863.5-1863.60" - process $proc$ls180.v:1863$3684 - assign { } { } - assign $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $1\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] - end - attribute \src "ls180.v:1864.5-1864.56" - process $proc$ls180.v:1864$3685 - assign { } { } - assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] - end - attribute \src "ls180.v:1865.5-1865.59" - process $proc$ls180.v:1865$3686 - assign { } { } - assign $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $1\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] - end - attribute \src "ls180.v:1866.5-1866.58" - process $proc$ls180.v:1866$3687 - assign { } { } - assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] - end - attribute \src "ls180.v:1867.5-1867.61" - process $proc$ls180.v:1867$3688 - assign { } { } - assign $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $1\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] - end - attribute \src "ls180.v:1868.5-1868.57" - process $proc$ls180.v:1868$3689 - assign { } { } - assign $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_error_sdcore_fsm_next_value6 $1\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] - end - attribute \src "ls180.v:1869.5-1869.60" - process $proc$ls180.v:1869$3690 - assign { } { } - assign $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $1\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] - end - attribute \src "ls180.v:1870.5-1870.59" - process $proc$ls180.v:1870$3691 - assign { } { } - assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] - end - attribute \src "ls180.v:1871.5-1871.62" - process $proc$ls180.v:1871$3692 - assign { } { } - assign $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 - sync always - sync init - update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $1\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] - end - attribute \src "ls180.v:1872.13-1872.76" - process $proc$ls180.v:1872$3693 - assign { } { } - assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] - end - attribute \src "ls180.v:1873.5-1873.69" - process $proc$ls180.v:1873$3694 - assign { } { } - assign $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 - sync always - sync init - update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $1\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] - end - attribute \src "ls180.v:1874.11-1874.46" - process $proc$ls180.v:1874$3695 - assign { } { } - assign $1\builder_sdblock2memdma_state[1:0] 2'00 - sync always - sync init - update \builder_sdblock2memdma_state $1\builder_sdblock2memdma_state[1:0] - end - attribute \src "ls180.v:1875.11-1875.51" - process $proc$ls180.v:1875$3696 - assign { } { } - assign $1\builder_sdblock2memdma_next_state[1:0] 2'00 - sync always - sync init - update \builder_sdblock2memdma_next_state $1\builder_sdblock2memdma_next_state[1:0] - end - attribute \src "ls180.v:1876.12-1876.87" - process $proc$ls180.v:1876$3697 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] - end - attribute \src "ls180.v:1877.5-1877.82" - process $proc$ls180.v:1877$3698 - assign { } { } - assign $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $1\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] - end - attribute \src "ls180.v:1878.5-1878.44" - process $proc$ls180.v:1878$3699 - assign { } { } - assign $1\builder_sdmem2blockdma_fsm_state[0:0] 1'0 - sync always - sync init - update \builder_sdmem2blockdma_fsm_state $1\builder_sdmem2blockdma_fsm_state[0:0] - end - attribute \src "ls180.v:1879.5-1879.49" - process $proc$ls180.v:1879$3700 - assign { } { } - assign $1\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 - sync always - sync init - update \builder_sdmem2blockdma_fsm_next_state $1\builder_sdmem2blockdma_fsm_next_state[0:0] - end - attribute \src "ls180.v:1880.12-1880.75" - process $proc$ls180.v:1880$3701 - assign { } { } - assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - sync init - update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] - end - attribute \src "ls180.v:1881.5-1881.70" - process $proc$ls180.v:1881$3702 - assign { } { } - assign $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $1\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] - end - attribute \src "ls180.v:1882.11-1882.60" - process $proc$ls180.v:1882$3703 - assign { } { } - assign $1\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 - sync always - sync init - update \builder_sdmem2blockdma_resetinserter_state $1\builder_sdmem2blockdma_resetinserter_state[1:0] - end - attribute \src "ls180.v:1883.11-1883.65" - process $proc$ls180.v:1883$3704 - assign { } { } - assign $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'00 - sync always - sync init - update \builder_sdmem2blockdma_resetinserter_next_state $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] - end - attribute \src "ls180.v:1884.12-1884.87" - process $proc$ls180.v:1884$3705 - assign { } { } - assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 - sync always - sync init - update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] - end - attribute \src "ls180.v:1885.5-1885.82" - process $proc$ls180.v:1885$3706 - assign { } { } - assign $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 - sync always - sync init - update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $1\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] - end - attribute \src "ls180.v:1886.12-1886.43" - process $proc$ls180.v:1886$3707 - assign { } { } - assign $1\builder_libresocsim_adr[13:0] 14'00000000000000 - sync always - sync init - update \builder_libresocsim_adr $1\builder_libresocsim_adr[13:0] - end - attribute \src "ls180.v:1887.5-1887.34" - process $proc$ls180.v:1887$3708 - assign { } { } - assign $1\builder_libresocsim_we[0:0] 1'0 - sync always - sync init - update \builder_libresocsim_we $1\builder_libresocsim_we[0:0] - end - attribute \src "ls180.v:1888.11-1888.43" - process $proc$ls180.v:1888$3709 - assign { } { } - assign $1\builder_libresocsim_dat_w[7:0] 8'00000000 - sync always - sync init - update \builder_libresocsim_dat_w $1\builder_libresocsim_dat_w[7:0] - end - attribute \src "ls180.v:1890.12-1890.52" - process $proc$ls180.v:1890$3710 - assign { } { } - assign $0\builder_libresocsim_wishbone_adr[29:0] 30'000000000000000000000000000000 - sync always - update \builder_libresocsim_wishbone_adr $0\builder_libresocsim_wishbone_adr[29:0] - sync init - end - attribute \src "ls180.v:1891.12-1891.54" - process $proc$ls180.v:1891$3711 - assign { } { } - assign $0\builder_libresocsim_wishbone_dat_w[31:0] 0 - sync always - update \builder_libresocsim_wishbone_dat_w $0\builder_libresocsim_wishbone_dat_w[31:0] - sync init - end - attribute \src "ls180.v:1892.12-1892.54" - process $proc$ls180.v:1892$3712 - assign { } { } - assign $1\builder_libresocsim_wishbone_dat_r[31:0] 0 - sync always - sync init - update \builder_libresocsim_wishbone_dat_r $1\builder_libresocsim_wishbone_dat_r[31:0] - end - attribute \src "ls180.v:1893.11-1893.50" - process $proc$ls180.v:1893$3713 - assign { } { } - assign $0\builder_libresocsim_wishbone_sel[3:0] 4'0000 - sync always - update \builder_libresocsim_wishbone_sel $0\builder_libresocsim_wishbone_sel[3:0] - sync init - end - attribute \src "ls180.v:1894.5-1894.44" - process $proc$ls180.v:1894$3714 - assign { } { } - assign $0\builder_libresocsim_wishbone_cyc[0:0] 1'0 - sync always - update \builder_libresocsim_wishbone_cyc $0\builder_libresocsim_wishbone_cyc[0:0] - sync init - end - attribute \src "ls180.v:1895.5-1895.44" - process $proc$ls180.v:1895$3715 - assign { } { } - assign $0\builder_libresocsim_wishbone_stb[0:0] 1'0 - sync always - update \builder_libresocsim_wishbone_stb $0\builder_libresocsim_wishbone_stb[0:0] - sync init - end - attribute \src "ls180.v:1896.5-1896.44" - process $proc$ls180.v:1896$3716 - assign { } { } - assign $1\builder_libresocsim_wishbone_ack[0:0] 1'0 - sync always - sync init - update \builder_libresocsim_wishbone_ack $1\builder_libresocsim_wishbone_ack[0:0] - end - attribute \src "ls180.v:1897.5-1897.43" - process $proc$ls180.v:1897$3717 - assign { } { } - assign $0\builder_libresocsim_wishbone_we[0:0] 1'0 - sync always - update \builder_libresocsim_wishbone_we $0\builder_libresocsim_wishbone_we[0:0] - sync init - end - attribute \src "ls180.v:190.5-190.41" - process $proc$ls180.v:190$2917 - assign { } { } - assign $1\main_libresocsim_zero_pending[0:0] 1'0 - sync always - sync init - update \main_libresocsim_zero_pending $1\main_libresocsim_zero_pending[0:0] - end - attribute \src "ls180.v:1900.12-1900.65" - process $proc$ls180.v:1900$3718 - assign { } { } - assign $0\builder_libresocsim_converted_interface_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - sync always - update \builder_libresocsim_converted_interface_dat_r $0\builder_libresocsim_converted_interface_dat_r[63:0] - sync init - end - attribute \src "ls180.v:1904.5-1904.55" - process $proc$ls180.v:1904$3719 - assign { } { } - assign $0\builder_libresocsim_converted_interface_ack[0:0] 1'0 - sync always - update \builder_libresocsim_converted_interface_ack $0\builder_libresocsim_converted_interface_ack[0:0] - sync init - end - attribute \src "ls180.v:1908.5-1908.55" - process $proc$ls180.v:1908$3720 - assign { } { } - assign $0\builder_libresocsim_converted_interface_err[0:0] 1'0 - sync always - update \builder_libresocsim_converted_interface_err $0\builder_libresocsim_converted_interface_err[0:0] - sync init - end - attribute \src "ls180.v:1911.12-1911.40" - process $proc$ls180.v:1911$3721 - assign { } { } - assign $1\builder_shared_dat_r[31:0] 0 - sync always - sync init - update \builder_shared_dat_r $1\builder_shared_dat_r[31:0] - end - attribute \src "ls180.v:1915.5-1915.30" - process $proc$ls180.v:1915$3722 - assign { } { } - assign $1\builder_shared_ack[0:0] 1'0 - sync always - sync init - update \builder_shared_ack $1\builder_shared_ack[0:0] - end - attribute \src "ls180.v:192.5-192.39" - process $proc$ls180.v:192$2918 - assign { } { } - assign $1\main_libresocsim_zero_clear[0:0] 1'0 - sync always - sync init - update \main_libresocsim_zero_clear $1\main_libresocsim_zero_clear[0:0] - end - attribute \src "ls180.v:1921.11-1921.31" - process $proc$ls180.v:1921$3723 - assign { } { } - assign $1\builder_grant[2:0] 3'000 - sync always - sync init - update \builder_grant $1\builder_grant[2:0] - end - attribute \src "ls180.v:1922.11-1922.35" - process $proc$ls180.v:1922$3724 - assign { } { } - assign $1\builder_slave_sel[5:0] 6'000000 - sync always - sync init - update \builder_slave_sel $1\builder_slave_sel[5:0] - end - attribute \src "ls180.v:1923.11-1923.37" - process $proc$ls180.v:1923$3725 - assign { } { } - assign $1\builder_slave_sel_r[5:0] 6'000000 - sync always - sync init - update \builder_slave_sel_r $1\builder_slave_sel_r[5:0] - end - attribute \src "ls180.v:1924.5-1924.25" - process $proc$ls180.v:1924$3726 - assign { } { } - assign $1\builder_error[0:0] 1'0 - sync always - sync init - update \builder_error $1\builder_error[0:0] - end - attribute \src "ls180.v:1927.12-1927.39" - process $proc$ls180.v:1927$3727 - assign { } { } - assign $1\builder_count[19:0] 20'11110100001001000000 - sync always - sync init - update \builder_count $1\builder_count[19:0] - end - attribute \src "ls180.v:193.5-193.45" - process $proc$ls180.v:193$2919 - assign { } { } - assign $1\main_libresocsim_zero_old_trigger[0:0] 1'0 - sync always - sync init - update \main_libresocsim_zero_old_trigger $1\main_libresocsim_zero_old_trigger[0:0] - end - attribute \src "ls180.v:1931.11-1931.51" - process $proc$ls180.v:1931$3728 - assign { } { } - assign $1\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface0_bank_bus_dat_r $1\builder_interface0_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:1972.11-1972.51" - process $proc$ls180.v:1972$3729 - assign { } { } - assign $1\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface1_bank_bus_dat_r $1\builder_interface1_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:2001.11-2001.51" - process $proc$ls180.v:2001$3730 - assign { } { } - assign $1\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface2_bank_bus_dat_r $1\builder_interface2_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:2014.11-2014.51" - process $proc$ls180.v:2014$3731 - assign { } { } - assign $1\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface3_bank_bus_dat_r $1\builder_interface3_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:202.5-202.49" - process $proc$ls180.v:202$2920 - assign { } { } - assign $1\main_libresocsim_eventmanager_storage[0:0] 1'0 - sync always - sync init - update \main_libresocsim_eventmanager_storage $1\main_libresocsim_eventmanager_storage[0:0] - end - attribute \src "ls180.v:203.5-203.44" - process $proc$ls180.v:203$2921 - assign { } { } - assign $1\main_libresocsim_eventmanager_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_eventmanager_re $1\main_libresocsim_eventmanager_re[0:0] - end - attribute \src "ls180.v:204.12-204.42" - process $proc$ls180.v:204$2922 - assign { } { } - assign $1\main_libresocsim_value[31:0] 0 - sync always - sync init - update \main_libresocsim_value $1\main_libresocsim_value[31:0] - end - attribute \src "ls180.v:2055.11-2055.51" - process $proc$ls180.v:2055$3732 - assign { } { } - assign $1\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 - sync always - sync init - update \builder_interface4_bank_bus_dat_r $1\builder_interface4_bank_bus_dat_r[7:0] - end - attribute \src "ls180.v:2096.11-2096.51" - process $proc$ls180.v:2096$3733 + attribute \src "ls180.v:1020.11-1020.49" + process $proc$ls180.v:1020$2033 assign { } { } - assign $1\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 + assign $1\subfragments_bankmachine2_state[2:0] 3'000 sync always sync init - update \builder_interface5_bank_bus_dat_r $1\builder_interface5_bank_bus_dat_r[7:0] + update \subfragments_bankmachine2_state $1\subfragments_bankmachine2_state[2:0] end - attribute \src "ls180.v:211.5-211.36" - process $proc$ls180.v:211$2923 + attribute \src "ls180.v:1021.11-1021.54" + process $proc$ls180.v:1021$2034 assign { } { } - assign $1\main_ram_bus_ram_bus_ack[0:0] 1'0 + assign $1\subfragments_bankmachine2_next_state[2:0] 3'000 sync always sync init - update \main_ram_bus_ram_bus_ack $1\main_ram_bus_ram_bus_ack[0:0] + update \subfragments_bankmachine2_next_state $1\subfragments_bankmachine2_next_state[2:0] end - attribute \src "ls180.v:215.5-215.36" - process $proc$ls180.v:215$2924 + attribute \src "ls180.v:1022.11-1022.49" + process $proc$ls180.v:1022$2035 assign { } { } - assign $0\main_ram_bus_ram_bus_err[0:0] 1'0 + assign $1\subfragments_bankmachine3_state[2:0] 3'000 sync always - update \main_ram_bus_ram_bus_err $0\main_ram_bus_ram_bus_err[0:0] sync init + update \subfragments_bankmachine3_state $1\subfragments_bankmachine3_state[2:0] end - attribute \src "ls180.v:2161.11-2161.51" - process $proc$ls180.v:2161$3734 + attribute \src "ls180.v:1023.11-1023.54" + process $proc$ls180.v:1023$2036 assign { } { } - assign $1\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 + assign $1\subfragments_bankmachine3_next_state[2:0] 3'000 sync always sync init - update \builder_interface6_bank_bus_dat_r $1\builder_interface6_bank_bus_dat_r[7:0] + update \subfragments_bankmachine3_next_state $1\subfragments_bankmachine3_next_state[2:0] end - attribute \src "ls180.v:218.11-218.29" - process $proc$ls180.v:218$2925 + attribute \src "ls180.v:1024.11-1024.48" + process $proc$ls180.v:1024$2037 assign { } { } - assign $1\main_ram_we[7:0] 8'00000000 + assign $1\subfragments_multiplexer_state[2:0] 3'000 sync always sync init - update \main_ram_we $1\main_ram_we[7:0] + update \subfragments_multiplexer_state $1\subfragments_multiplexer_state[2:0] end - attribute \src "ls180.v:226.5-226.51" - process $proc$ls180.v:226$2926 + attribute \src "ls180.v:1025.11-1025.53" + process $proc$ls180.v:1025$2038 assign { } { } - assign $1\main_interface0_converted_interface_ack[0:0] 1'0 + assign $1\subfragments_multiplexer_next_state[2:0] 3'000 sync always sync init - update \main_interface0_converted_interface_ack $1\main_interface0_converted_interface_ack[0:0] + update \subfragments_multiplexer_next_state $1\subfragments_multiplexer_next_state[2:0] end - attribute \src "ls180.v:2294.11-2294.51" - process $proc$ls180.v:2294$3735 + attribute \src "ls180.v:103.11-103.50" + process $proc$ls180.v:103$1643 assign { } { } - assign $1\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 + assign $0\libresocsim_libresoc_jtag_wb_bte[1:0] 2'00 sync always + update \libresocsim_libresoc_jtag_wb_bte $0\libresocsim_libresoc_jtag_wb_bte[1:0] sync init - update \builder_interface7_bank_bus_dat_r $1\builder_interface7_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:230.5-230.51" - process $proc$ls180.v:230$2927 + attribute \src "ls180.v:1038.5-1038.32" + process $proc$ls180.v:1038$2039 assign { } { } - assign $0\main_interface0_converted_interface_err[0:0] 1'0 + assign $0\subfragments_locked0[0:0] 1'0 sync always - update \main_interface0_converted_interface_err $0\main_interface0_converted_interface_err[0:0] + update \subfragments_locked0 $0\subfragments_locked0[0:0] sync init end - attribute \src "ls180.v:231.5-231.32" - process $proc$ls180.v:231$2928 + attribute \src "ls180.v:1039.5-1039.32" + process $proc$ls180.v:1039$2040 assign { } { } - assign $1\main_converter0_skip[0:0] 1'0 + assign $0\subfragments_locked1[0:0] 1'0 sync always + update \subfragments_locked1 $0\subfragments_locked1[0:0] sync init - update \main_converter0_skip $1\main_converter0_skip[0:0] end - attribute \src "ls180.v:232.5-232.35" - process $proc$ls180.v:232$2929 + attribute \src "ls180.v:1040.5-1040.32" + process $proc$ls180.v:1040$2041 assign { } { } - assign $1\main_converter0_counter[0:0] 1'0 + assign $0\subfragments_locked2[0:0] 1'0 sync always + update \subfragments_locked2 $0\subfragments_locked2[0:0] sync init - update \main_converter0_counter $1\main_converter0_counter[0:0] end - attribute \src "ls180.v:234.12-234.41" - process $proc$ls180.v:234$2930 + attribute \src "ls180.v:1041.5-1041.32" + process $proc$ls180.v:1041$2042 assign { } { } - assign $1\main_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\subfragments_locked3[0:0] 1'0 sync always + update \subfragments_locked3 $0\subfragments_locked3[0:0] sync init - update \main_converter0_dat_r $1\main_converter0_dat_r[63:0] end - attribute \src "ls180.v:2375.11-2375.51" - process $proc$ls180.v:2375$3736 + attribute \src "ls180.v:1042.5-1042.47" + process $proc$ls180.v:1042$2043 assign { } { } - assign $1\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 + assign $1\subfragments_new_master_wdata_ready[0:0] 1'0 sync always sync init - update \builder_interface8_bank_bus_dat_r $1\builder_interface8_bank_bus_dat_r[7:0] + update \subfragments_new_master_wdata_ready $1\subfragments_new_master_wdata_ready[0:0] end - attribute \src "ls180.v:2392.11-2392.51" - process $proc$ls180.v:2392$3737 + attribute \src "ls180.v:1043.5-1043.48" + process $proc$ls180.v:1043$2044 assign { } { } - assign $1\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 + assign $1\subfragments_new_master_rdata_valid0[0:0] 1'0 sync always sync init - update \builder_interface9_bank_bus_dat_r $1\builder_interface9_bank_bus_dat_r[7:0] + update \subfragments_new_master_rdata_valid0 $1\subfragments_new_master_rdata_valid0[0:0] end - attribute \src "ls180.v:241.5-241.51" - process $proc$ls180.v:241$2931 + attribute \src "ls180.v:1044.5-1044.48" + process $proc$ls180.v:1044$2045 assign { } { } - assign $1\main_interface1_converted_interface_ack[0:0] 1'0 + assign $1\subfragments_new_master_rdata_valid1[0:0] 1'0 sync always sync init - update \main_interface1_converted_interface_ack $1\main_interface1_converted_interface_ack[0:0] + update \subfragments_new_master_rdata_valid1 $1\subfragments_new_master_rdata_valid1[0:0] end - attribute \src "ls180.v:2433.11-2433.52" - process $proc$ls180.v:2433$3738 + attribute \src "ls180.v:1045.5-1045.48" + process $proc$ls180.v:1045$2046 assign { } { } - assign $1\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 + assign $1\subfragments_new_master_rdata_valid2[0:0] 1'0 sync always sync init - update \builder_interface10_bank_bus_dat_r $1\builder_interface10_bank_bus_dat_r[7:0] + update \subfragments_new_master_rdata_valid2 $1\subfragments_new_master_rdata_valid2[0:0] end - attribute \src "ls180.v:245.5-245.51" - process $proc$ls180.v:245$2932 + attribute \src "ls180.v:1046.5-1046.48" + process $proc$ls180.v:1046$2047 assign { } { } - assign $0\main_interface1_converted_interface_err[0:0] 1'0 + assign $1\subfragments_new_master_rdata_valid3[0:0] 1'0 sync always - update \main_interface1_converted_interface_err $0\main_interface1_converted_interface_err[0:0] sync init + update \subfragments_new_master_rdata_valid3 $1\subfragments_new_master_rdata_valid3[0:0] end - attribute \src "ls180.v:246.5-246.32" - process $proc$ls180.v:246$2933 + attribute \src "ls180.v:1047.5-1047.30" + process $proc$ls180.v:1047$2048 assign { } { } - assign $1\main_converter1_skip[0:0] 1'0 + assign $1\subfragments_state[0:0] 1'0 sync always sync init - update \main_converter1_skip $1\main_converter1_skip[0:0] + update \subfragments_state $1\subfragments_state[0:0] end - attribute \src "ls180.v:2466.11-2466.52" - process $proc$ls180.v:2466$3739 + attribute \src "ls180.v:1048.5-1048.35" + process $proc$ls180.v:1048$2049 assign { } { } - assign $1\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 + assign $1\subfragments_next_state[0:0] 1'0 sync always sync init - update \builder_interface11_bank_bus_dat_r $1\builder_interface11_bank_bus_dat_r[7:0] + update \subfragments_next_state $1\subfragments_next_state[0:0] end - attribute \src "ls180.v:247.5-247.35" - process $proc$ls180.v:247$2934 + attribute \src "ls180.v:1049.5-1049.53" + process $proc$ls180.v:1049$2050 assign { } { } - assign $1\main_converter1_counter[0:0] 1'0 + assign $1\converter_counter_subfragments_next_value[0:0] 1'0 sync always sync init - update \main_converter1_counter $1\main_converter1_counter[0:0] + update \converter_counter_subfragments_next_value $1\converter_counter_subfragments_next_value[0:0] end - attribute \src "ls180.v:249.12-249.41" - process $proc$ls180.v:249$2935 + attribute \src "ls180.v:1050.5-1050.56" + process $proc$ls180.v:1050$2051 assign { } { } - assign $1\main_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\converter_counter_subfragments_next_value_ce[0:0] 1'0 sync always sync init - update \main_converter1_dat_r $1\main_converter1_dat_r[63:0] + update \converter_counter_subfragments_next_value_ce $1\converter_counter_subfragments_next_value_ce[0:0] end - attribute \src "ls180.v:2507.11-2507.52" - process $proc$ls180.v:2507$3740 + attribute \src "ls180.v:1051.12-1051.47" + process $proc$ls180.v:1051$2052 assign { } { } - assign $1\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 + assign $1\libresocsim_libresocsim_adr[13:0] 14'00000000000000 sync always sync init - update \builder_interface12_bank_bus_dat_r $1\builder_interface12_bank_bus_dat_r[7:0] + update \libresocsim_libresocsim_adr $1\libresocsim_libresocsim_adr[13:0] end - attribute \src "ls180.v:253.5-253.24" - process $proc$ls180.v:253$2936 + attribute \src "ls180.v:1052.5-1052.38" + process $proc$ls180.v:1052$2053 assign { } { } - assign $1\main_int_rst[0:0] 1'1 + assign $1\libresocsim_libresocsim_we[0:0] 1'0 sync always sync init - update \main_int_rst $1\main_int_rst[0:0] + update \libresocsim_libresocsim_we $1\libresocsim_libresocsim_we[0:0] end - attribute \src "ls180.v:2572.11-2572.52" - process $proc$ls180.v:2572$3741 + attribute \src "ls180.v:1053.11-1053.47" + process $proc$ls180.v:1053$2054 assign { } { } - assign $1\builder_interface13_bank_bus_dat_r[7:0] 8'00000000 + assign $1\libresocsim_libresocsim_dat_w[7:0] 8'00000000 sync always sync init - update \builder_interface13_bank_bus_dat_r $1\builder_interface13_bank_bus_dat_r[7:0] + update \libresocsim_libresocsim_dat_w $1\libresocsim_libresocsim_dat_w[7:0] end - attribute \src "ls180.v:2597.11-2597.52" - process $proc$ls180.v:2597$3742 + attribute \src "ls180.v:1055.12-1055.56" + process $proc$ls180.v:1055$2055 assign { } { } - assign $1\builder_interface14_bank_bus_dat_r[7:0] 8'00000000 + assign $0\libresocsim_libresocsim_wishbone_adr[29:0] 30'000000000000000000000000000000 sync always + update \libresocsim_libresocsim_wishbone_adr $0\libresocsim_libresocsim_wishbone_adr[29:0] sync init - update \builder_interface14_bank_bus_dat_r $1\builder_interface14_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2619.11-2619.31" - process $proc$ls180.v:2619$3743 + attribute \src "ls180.v:1056.12-1056.58" + process $proc$ls180.v:1056$2056 assign { } { } - assign $1\builder_state[1:0] 2'00 + assign $0\libresocsim_libresocsim_wishbone_dat_w[31:0] 0 sync always + update \libresocsim_libresocsim_wishbone_dat_w $0\libresocsim_libresocsim_wishbone_dat_w[31:0] sync init - update \builder_state $1\builder_state[1:0] end - attribute \src "ls180.v:2620.11-2620.36" - process $proc$ls180.v:2620$3744 + attribute \src "ls180.v:1057.12-1057.58" + process $proc$ls180.v:1057$2057 assign { } { } - assign $1\builder_next_state[1:0] 2'00 + assign $1\libresocsim_libresocsim_wishbone_dat_r[31:0] 0 sync always sync init - update \builder_next_state $1\builder_next_state[1:0] + update \libresocsim_libresocsim_wishbone_dat_r $1\libresocsim_libresocsim_wishbone_dat_r[31:0] end - attribute \src "ls180.v:2621.11-2621.55" - process $proc$ls180.v:2621$3745 + attribute \src "ls180.v:1058.11-1058.54" + process $proc$ls180.v:1058$2058 assign { } { } - assign $1\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 + assign $0\libresocsim_libresocsim_wishbone_sel[3:0] 4'0000 sync always + update \libresocsim_libresocsim_wishbone_sel $0\libresocsim_libresocsim_wishbone_sel[3:0] sync init - update \builder_libresocsim_dat_w_next_value0 $1\builder_libresocsim_dat_w_next_value0[7:0] end - attribute \src "ls180.v:2622.5-2622.52" - process $proc$ls180.v:2622$3746 + attribute \src "ls180.v:1059.5-1059.48" + process $proc$ls180.v:1059$2059 assign { } { } - assign $1\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 + assign $0\libresocsim_libresocsim_wishbone_cyc[0:0] 1'0 sync always + update \libresocsim_libresocsim_wishbone_cyc $0\libresocsim_libresocsim_wishbone_cyc[0:0] sync init - update \builder_libresocsim_dat_w_next_value_ce0 $1\builder_libresocsim_dat_w_next_value_ce0[0:0] end - attribute \src "ls180.v:2623.12-2623.55" - process $proc$ls180.v:2623$3747 + attribute \src "ls180.v:1060.5-1060.48" + process $proc$ls180.v:1060$2060 assign { } { } - assign $1\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 + assign $0\libresocsim_libresocsim_wishbone_stb[0:0] 1'0 sync always + update \libresocsim_libresocsim_wishbone_stb $0\libresocsim_libresocsim_wishbone_stb[0:0] sync init - update \builder_libresocsim_adr_next_value1 $1\builder_libresocsim_adr_next_value1[13:0] end - attribute \src "ls180.v:2624.5-2624.50" - process $proc$ls180.v:2624$3748 + attribute \src "ls180.v:1061.5-1061.48" + process $proc$ls180.v:1061$2061 assign { } { } - assign $1\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 + assign $1\libresocsim_libresocsim_wishbone_ack[0:0] 1'0 sync always sync init - update \builder_libresocsim_adr_next_value_ce1 $1\builder_libresocsim_adr_next_value_ce1[0:0] + update \libresocsim_libresocsim_wishbone_ack $1\libresocsim_libresocsim_wishbone_ack[0:0] end - attribute \src "ls180.v:2625.5-2625.46" - process $proc$ls180.v:2625$3749 + attribute \src "ls180.v:1062.5-1062.47" + process $proc$ls180.v:1062$2062 assign { } { } - assign $1\builder_libresocsim_we_next_value2[0:0] 1'0 + assign $0\libresocsim_libresocsim_wishbone_we[0:0] 1'0 sync always + update \libresocsim_libresocsim_wishbone_we $0\libresocsim_libresocsim_wishbone_we[0:0] sync init - update \builder_libresocsim_we_next_value2 $1\builder_libresocsim_we_next_value2[0:0] end - attribute \src "ls180.v:2626.5-2626.49" - process $proc$ls180.v:2626$3750 + attribute \src "ls180.v:1065.12-1065.69" + process $proc$ls180.v:1065$2063 assign { } { } - assign $1\builder_libresocsim_we_next_value_ce2[0:0] 1'0 + assign $0\libresocsim_libresocsim_converted_interface_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always + update \libresocsim_libresocsim_converted_interface_dat_r $0\libresocsim_libresocsim_converted_interface_dat_r[63:0] sync init - update \builder_libresocsim_we_next_value_ce2 $1\builder_libresocsim_we_next_value_ce2[0:0] end - attribute \src "ls180.v:2627.5-2627.41" - process $proc$ls180.v:2627$3751 + attribute \src "ls180.v:1069.5-1069.59" + process $proc$ls180.v:1069$2064 assign { } { } - assign $1\builder_comb_rhs_array_muxed0[0:0] 1'0 + assign $0\libresocsim_libresocsim_converted_interface_ack[0:0] 1'0 sync always + update \libresocsim_libresocsim_converted_interface_ack $0\libresocsim_libresocsim_converted_interface_ack[0:0] sync init - update \builder_comb_rhs_array_muxed0 $1\builder_comb_rhs_array_muxed0[0:0] end - attribute \src "ls180.v:2628.12-2628.49" - process $proc$ls180.v:2628$3752 + attribute \src "ls180.v:1073.5-1073.59" + process $proc$ls180.v:1073$2065 assign { } { } - assign $1\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 + assign $0\libresocsim_libresocsim_converted_interface_err[0:0] 1'0 sync always + update \libresocsim_libresocsim_converted_interface_err $0\libresocsim_libresocsim_converted_interface_err[0:0] sync init - update \builder_comb_rhs_array_muxed1 $1\builder_comb_rhs_array_muxed1[12:0] end - attribute \src "ls180.v:2629.11-2629.47" - process $proc$ls180.v:2629$3753 + attribute \src "ls180.v:1076.12-1076.44" + process $proc$ls180.v:1076$2066 assign { } { } - assign $1\builder_comb_rhs_array_muxed2[1:0] 2'00 + assign $1\libresocsim_shared_dat_r[31:0] 0 sync always sync init - update \builder_comb_rhs_array_muxed2 $1\builder_comb_rhs_array_muxed2[1:0] + update \libresocsim_shared_dat_r $1\libresocsim_shared_dat_r[31:0] end - attribute \src "ls180.v:2630.5-2630.41" - process $proc$ls180.v:2630$3754 + attribute \src "ls180.v:1080.5-1080.34" + process $proc$ls180.v:1080$2067 assign { } { } - assign $1\builder_comb_rhs_array_muxed3[0:0] 1'0 + assign $1\libresocsim_shared_ack[0:0] 1'0 sync always sync init - update \builder_comb_rhs_array_muxed3 $1\builder_comb_rhs_array_muxed3[0:0] + update \libresocsim_shared_ack $1\libresocsim_shared_ack[0:0] end - attribute \src "ls180.v:2631.5-2631.41" - process $proc$ls180.v:2631$3755 + attribute \src "ls180.v:1086.11-1086.35" + process $proc$ls180.v:1086$2068 assign { } { } - assign $1\builder_comb_rhs_array_muxed4[0:0] 1'0 + assign $1\libresocsim_grant[1:0] 2'00 sync always sync init - update \builder_comb_rhs_array_muxed4 $1\builder_comb_rhs_array_muxed4[0:0] + update \libresocsim_grant $1\libresocsim_grant[1:0] end - attribute \src "ls180.v:2632.5-2632.41" - process $proc$ls180.v:2632$3756 + attribute \src "ls180.v:1087.11-1087.39" + process $proc$ls180.v:1087$2069 assign { } { } - assign $1\builder_comb_rhs_array_muxed5[0:0] 1'0 + assign $1\libresocsim_slave_sel[5:0] 6'000000 sync always sync init - update \builder_comb_rhs_array_muxed5 $1\builder_comb_rhs_array_muxed5[0:0] + update \libresocsim_slave_sel $1\libresocsim_slave_sel[5:0] end - attribute \src "ls180.v:2633.5-2633.39" - process $proc$ls180.v:2633$3757 + attribute \src "ls180.v:1088.11-1088.41" + process $proc$ls180.v:1088$2070 assign { } { } - assign $1\builder_comb_t_array_muxed0[0:0] 1'0 + assign $1\libresocsim_slave_sel_r[5:0] 6'000000 sync always sync init - update \builder_comb_t_array_muxed0 $1\builder_comb_t_array_muxed0[0:0] + update \libresocsim_slave_sel_r $1\libresocsim_slave_sel_r[5:0] end - attribute \src "ls180.v:2634.5-2634.39" - process $proc$ls180.v:2634$3758 + attribute \src "ls180.v:1089.5-1089.29" + process $proc$ls180.v:1089$2071 assign { } { } - assign $1\builder_comb_t_array_muxed1[0:0] 1'0 + assign $1\libresocsim_error[0:0] 1'0 sync always sync init - update \builder_comb_t_array_muxed1 $1\builder_comb_t_array_muxed1[0:0] + update \libresocsim_error $1\libresocsim_error[0:0] end - attribute \src "ls180.v:2635.5-2635.39" - process $proc$ls180.v:2635$3759 + attribute \src "ls180.v:1092.12-1092.43" + process $proc$ls180.v:1092$2072 assign { } { } - assign $1\builder_comb_t_array_muxed2[0:0] 1'0 + assign $1\libresocsim_count[19:0] 20'11110100001001000000 sync always sync init - update \builder_comb_t_array_muxed2 $1\builder_comb_t_array_muxed2[0:0] + update \libresocsim_count $1\libresocsim_count[19:0] end - attribute \src "ls180.v:2636.5-2636.41" - process $proc$ls180.v:2636$3760 + attribute \src "ls180.v:1096.11-1096.55" + process $proc$ls180.v:1096$2073 assign { } { } - assign $1\builder_comb_rhs_array_muxed6[0:0] 1'0 + assign $1\libresocsim_interface0_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \builder_comb_rhs_array_muxed6 $1\builder_comb_rhs_array_muxed6[0:0] + update \libresocsim_interface0_bank_bus_dat_r $1\libresocsim_interface0_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2637.12-2637.49" - process $proc$ls180.v:2637$3761 + attribute \src "ls180.v:1137.11-1137.55" + process $proc$ls180.v:1137$2074 assign { } { } - assign $1\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 + assign $1\libresocsim_interface1_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \builder_comb_rhs_array_muxed7 $1\builder_comb_rhs_array_muxed7[12:0] + update \libresocsim_interface1_bank_bus_dat_r $1\libresocsim_interface1_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2638.11-2638.47" - process $proc$ls180.v:2638$3762 + attribute \src "ls180.v:1154.11-1154.55" + process $proc$ls180.v:1154$2075 assign { } { } - assign $1\builder_comb_rhs_array_muxed8[1:0] 2'00 + assign $1\libresocsim_interface2_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \builder_comb_rhs_array_muxed8 $1\builder_comb_rhs_array_muxed8[1:0] + update \libresocsim_interface2_bank_bus_dat_r $1\libresocsim_interface2_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2639.5-2639.41" - process $proc$ls180.v:2639$3763 + attribute \src "ls180.v:116.12-116.69" + process $proc$ls180.v:116$1644 assign { } { } - assign $1\builder_comb_rhs_array_muxed9[0:0] 1'0 + assign $1\libresocsim_libresoc_constraintmanager_obj_gpio_o[15:0] 16'0000000000000000 sync always sync init - update \builder_comb_rhs_array_muxed9 $1\builder_comb_rhs_array_muxed9[0:0] + update \libresocsim_libresoc_constraintmanager_obj_gpio_o $1\libresocsim_libresoc_constraintmanager_obj_gpio_o[15:0] end - attribute \src "ls180.v:2640.5-2640.42" - process $proc$ls180.v:2640$3764 + attribute \src "ls180.v:117.12-117.70" + process $proc$ls180.v:117$1645 assign { } { } - assign $1\builder_comb_rhs_array_muxed10[0:0] 1'0 + assign $1\libresocsim_libresoc_constraintmanager_obj_gpio_oe[15:0] 16'0000000000000000 sync always sync init - update \builder_comb_rhs_array_muxed10 $1\builder_comb_rhs_array_muxed10[0:0] + update \libresocsim_libresoc_constraintmanager_obj_gpio_oe $1\libresocsim_libresoc_constraintmanager_obj_gpio_oe[15:0] end - attribute \src "ls180.v:2641.5-2641.42" - process $proc$ls180.v:2641$3765 + attribute \src "ls180.v:1171.11-1171.55" + process $proc$ls180.v:1171$2076 assign { } { } - assign $1\builder_comb_rhs_array_muxed11[0:0] 1'0 + assign $1\libresocsim_interface3_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \builder_comb_rhs_array_muxed11 $1\builder_comb_rhs_array_muxed11[0:0] + update \libresocsim_interface3_bank_bus_dat_r $1\libresocsim_interface3_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2642.5-2642.39" - process $proc$ls180.v:2642$3766 + attribute \src "ls180.v:118.5-118.68" + process $proc$ls180.v:118$1646 assign { } { } - assign $1\builder_comb_t_array_muxed3[0:0] 1'0 + assign $0\libresocsim_libresoc_constraintmanager_obj_spimaster_clk[0:0] 1'0 sync always + update \libresocsim_libresoc_constraintmanager_obj_spimaster_clk $0\libresocsim_libresoc_constraintmanager_obj_spimaster_clk[0:0] sync init - update \builder_comb_t_array_muxed3 $1\builder_comb_t_array_muxed3[0:0] end - attribute \src "ls180.v:2643.5-2643.39" - process $proc$ls180.v:2643$3767 + attribute \src "ls180.v:1184.11-1184.55" + process $proc$ls180.v:1184$2077 assign { } { } - assign $1\builder_comb_t_array_muxed4[0:0] 1'0 + assign $1\libresocsim_interface4_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \builder_comb_t_array_muxed4 $1\builder_comb_t_array_muxed4[0:0] + update \libresocsim_interface4_bank_bus_dat_r $1\libresocsim_interface4_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2644.5-2644.39" - process $proc$ls180.v:2644$3768 + attribute \src "ls180.v:119.5-119.69" + process $proc$ls180.v:119$1647 assign { } { } - assign $1\builder_comb_t_array_muxed5[0:0] 1'0 + assign $0\libresocsim_libresoc_constraintmanager_obj_spimaster_mosi[0:0] 1'0 sync always + update \libresocsim_libresoc_constraintmanager_obj_spimaster_mosi $0\libresocsim_libresoc_constraintmanager_obj_spimaster_mosi[0:0] sync init - update \builder_comb_t_array_muxed5 $1\builder_comb_t_array_muxed5[0:0] end - attribute \src "ls180.v:2645.12-2645.50" - process $proc$ls180.v:2645$3769 + attribute \src "ls180.v:120.5-120.69" + process $proc$ls180.v:120$1648 assign { } { } - assign $1\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 + assign $0\libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n[0:0] 1'0 sync always + update \libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n $0\libresocsim_libresoc_constraintmanager_obj_spimaster_cs_n[0:0] sync init - update \builder_comb_rhs_array_muxed12 $1\builder_comb_rhs_array_muxed12[21:0] end - attribute \src "ls180.v:2646.5-2646.42" - process $proc$ls180.v:2646$3770 + attribute \src "ls180.v:122.5-122.62" + process $proc$ls180.v:122$1649 assign { } { } - assign $1\builder_comb_rhs_array_muxed13[0:0] 1'0 + assign $1\libresocsim_libresoc_constraintmanager_obj_uart_tx[0:0] 1'1 sync always sync init - update \builder_comb_rhs_array_muxed13 $1\builder_comb_rhs_array_muxed13[0:0] + update \libresocsim_libresoc_constraintmanager_obj_uart_tx $1\libresocsim_libresoc_constraintmanager_obj_uart_tx[0:0] end - attribute \src "ls180.v:2647.5-2647.42" - process $proc$ls180.v:2647$3771 + attribute \src "ls180.v:1225.11-1225.55" + process $proc$ls180.v:1225$2078 assign { } { } - assign $1\builder_comb_rhs_array_muxed14[0:0] 1'0 + assign $1\libresocsim_interface5_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \builder_comb_rhs_array_muxed14 $1\builder_comb_rhs_array_muxed14[0:0] + update \libresocsim_interface5_bank_bus_dat_r $1\libresocsim_interface5_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2648.12-2648.50" - process $proc$ls180.v:2648$3772 + attribute \src "ls180.v:123.5-123.62" + process $proc$ls180.v:123$1650 assign { } { } - assign $1\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 + assign $0\libresocsim_libresoc_constraintmanager_obj_uart_rx[0:0] 1'0 sync always + update \libresocsim_libresoc_constraintmanager_obj_uart_rx $0\libresocsim_libresoc_constraintmanager_obj_uart_rx[0:0] sync init - update \builder_comb_rhs_array_muxed15 $1\builder_comb_rhs_array_muxed15[21:0] end - attribute \src "ls180.v:2649.5-2649.42" - process $proc$ls180.v:2649$3773 + attribute \src "ls180.v:125.12-125.70" + process $proc$ls180.v:125$1651 assign { } { } - assign $1\builder_comb_rhs_array_muxed16[0:0] 1'0 + assign $1\libresocsim_libresoc_constraintmanager_obj_sdram_a[12:0] 13'0000000000000 sync always sync init - update \builder_comb_rhs_array_muxed16 $1\builder_comb_rhs_array_muxed16[0:0] + update \libresocsim_libresoc_constraintmanager_obj_sdram_a $1\libresocsim_libresoc_constraintmanager_obj_sdram_a[12:0] end - attribute \src "ls180.v:2650.5-2650.42" - process $proc$ls180.v:2650$3774 + attribute \src "ls180.v:127.12-127.73" + process $proc$ls180.v:127$1652 assign { } { } - assign $1\builder_comb_rhs_array_muxed17[0:0] 1'0 + assign $1\libresocsim_libresoc_constraintmanager_obj_sdram_dq_o[15:0] 16'0000000000000000 sync always sync init - update \builder_comb_rhs_array_muxed17 $1\builder_comb_rhs_array_muxed17[0:0] + update \libresocsim_libresoc_constraintmanager_obj_sdram_dq_o $1\libresocsim_libresoc_constraintmanager_obj_sdram_dq_o[15:0] end - attribute \src "ls180.v:2651.12-2651.50" - process $proc$ls180.v:2651$3775 + attribute \src "ls180.v:128.5-128.66" + process $proc$ls180.v:128$1653 assign { } { } - assign $1\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 + assign $1\libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe[0:0] 1'0 sync always sync init - update \builder_comb_rhs_array_muxed18 $1\builder_comb_rhs_array_muxed18[21:0] + update \libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe $1\libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe[0:0] end - attribute \src "ls180.v:2652.5-2652.42" - process $proc$ls180.v:2652$3776 + attribute \src "ls180.v:129.5-129.65" + process $proc$ls180.v:129$1654 assign { } { } - assign $1\builder_comb_rhs_array_muxed19[0:0] 1'0 + assign $1\libresocsim_libresoc_constraintmanager_obj_sdram_we_n[0:0] 1'0 sync always sync init - update \builder_comb_rhs_array_muxed19 $1\builder_comb_rhs_array_muxed19[0:0] + update \libresocsim_libresoc_constraintmanager_obj_sdram_we_n $1\libresocsim_libresoc_constraintmanager_obj_sdram_we_n[0:0] end - attribute \src "ls180.v:2653.5-2653.42" - process $proc$ls180.v:2653$3777 + attribute \src "ls180.v:1290.11-1290.55" + process $proc$ls180.v:1290$2079 assign { } { } - assign $1\builder_comb_rhs_array_muxed20[0:0] 1'0 + assign $1\libresocsim_interface6_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \builder_comb_rhs_array_muxed20 $1\builder_comb_rhs_array_muxed20[0:0] + update \libresocsim_interface6_bank_bus_dat_r $1\libresocsim_interface6_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2654.12-2654.50" - process $proc$ls180.v:2654$3778 + attribute \src "ls180.v:130.5-130.66" + process $proc$ls180.v:130$1655 assign { } { } - assign $1\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 + assign $1\libresocsim_libresoc_constraintmanager_obj_sdram_ras_n[0:0] 1'0 sync always sync init - update \builder_comb_rhs_array_muxed21 $1\builder_comb_rhs_array_muxed21[21:0] + update \libresocsim_libresoc_constraintmanager_obj_sdram_ras_n $1\libresocsim_libresoc_constraintmanager_obj_sdram_ras_n[0:0] end - attribute \src "ls180.v:2655.5-2655.42" - process $proc$ls180.v:2655$3779 + attribute \src "ls180.v:131.5-131.66" + process $proc$ls180.v:131$1656 assign { } { } - assign $1\builder_comb_rhs_array_muxed22[0:0] 1'0 + assign $1\libresocsim_libresoc_constraintmanager_obj_sdram_cas_n[0:0] 1'0 sync always sync init - update \builder_comb_rhs_array_muxed22 $1\builder_comb_rhs_array_muxed22[0:0] + update \libresocsim_libresoc_constraintmanager_obj_sdram_cas_n $1\libresocsim_libresoc_constraintmanager_obj_sdram_cas_n[0:0] end - attribute \src "ls180.v:2656.5-2656.42" - process $proc$ls180.v:2656$3780 + attribute \src "ls180.v:1315.11-1315.55" + process $proc$ls180.v:1315$2080 assign { } { } - assign $1\builder_comb_rhs_array_muxed23[0:0] 1'0 + assign $1\libresocsim_interface7_bank_bus_dat_r[7:0] 8'00000000 sync always sync init - update \builder_comb_rhs_array_muxed23 $1\builder_comb_rhs_array_muxed23[0:0] + update \libresocsim_interface7_bank_bus_dat_r $1\libresocsim_interface7_bank_bus_dat_r[7:0] end - attribute \src "ls180.v:2657.12-2657.50" - process $proc$ls180.v:2657$3781 + attribute \src "ls180.v:132.5-132.65" + process $proc$ls180.v:132$1657 assign { } { } - assign $1\builder_comb_rhs_array_muxed24[31:0] 0 + assign $1\libresocsim_libresoc_constraintmanager_obj_sdram_cs_n[0:0] 1'0 sync always sync init - update \builder_comb_rhs_array_muxed24 $1\builder_comb_rhs_array_muxed24[31:0] + update \libresocsim_libresoc_constraintmanager_obj_sdram_cs_n $1\libresocsim_libresoc_constraintmanager_obj_sdram_cs_n[0:0] end - attribute \src "ls180.v:2658.12-2658.50" - process $proc$ls180.v:2658$3782 + attribute \src "ls180.v:133.5-133.64" + process $proc$ls180.v:133$1658 assign { } { } - assign $1\builder_comb_rhs_array_muxed25[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\libresocsim_libresoc_constraintmanager_obj_sdram_cke[0:0] 1'0 sync always sync init - update \builder_comb_rhs_array_muxed25 $1\builder_comb_rhs_array_muxed25[63:0] + update \libresocsim_libresoc_constraintmanager_obj_sdram_cke $1\libresocsim_libresoc_constraintmanager_obj_sdram_cke[0:0] end - attribute \src "ls180.v:2659.11-2659.48" - process $proc$ls180.v:2659$3783 + attribute \src "ls180.v:1337.11-1337.35" + process $proc$ls180.v:1337$2081 assign { } { } - assign $1\builder_comb_rhs_array_muxed26[7:0] 8'00000000 + assign $1\libresocsim_state[1:0] 2'00 sync always sync init - update \builder_comb_rhs_array_muxed26 $1\builder_comb_rhs_array_muxed26[7:0] + update \libresocsim_state $1\libresocsim_state[1:0] end - attribute \src "ls180.v:2660.5-2660.42" - process $proc$ls180.v:2660$3784 + attribute \src "ls180.v:1338.11-1338.40" + process $proc$ls180.v:1338$2082 assign { } { } - assign $1\builder_comb_rhs_array_muxed27[0:0] 1'0 + assign $1\libresocsim_next_state[1:0] 2'00 sync always sync init - update \builder_comb_rhs_array_muxed27 $1\builder_comb_rhs_array_muxed27[0:0] + update \libresocsim_next_state $1\libresocsim_next_state[1:0] end - attribute \src "ls180.v:2661.5-2661.42" - process $proc$ls180.v:2661$3785 + attribute \src "ls180.v:1339.11-1339.71" + process $proc$ls180.v:1339$2083 assign { } { } - assign $1\builder_comb_rhs_array_muxed28[0:0] 1'0 + assign $1\libresocsim_libresocsim_dat_w_libresocsim_next_value0[7:0] 8'00000000 sync always sync init - update \builder_comb_rhs_array_muxed28 $1\builder_comb_rhs_array_muxed28[0:0] + update \libresocsim_libresocsim_dat_w_libresocsim_next_value0 $1\libresocsim_libresocsim_dat_w_libresocsim_next_value0[7:0] end - attribute \src "ls180.v:2662.5-2662.42" - process $proc$ls180.v:2662$3786 + attribute \src "ls180.v:134.11-134.69" + process $proc$ls180.v:134$1659 assign { } { } - assign $1\builder_comb_rhs_array_muxed29[0:0] 1'0 + assign $1\libresocsim_libresoc_constraintmanager_obj_sdram_ba[1:0] 2'00 sync always sync init - update \builder_comb_rhs_array_muxed29 $1\builder_comb_rhs_array_muxed29[0:0] + update \libresocsim_libresoc_constraintmanager_obj_sdram_ba $1\libresocsim_libresoc_constraintmanager_obj_sdram_ba[1:0] end - attribute \src "ls180.v:2663.11-2663.48" - process $proc$ls180.v:2663$3787 + attribute \src "ls180.v:1340.5-1340.68" + process $proc$ls180.v:1340$2084 assign { } { } - assign $1\builder_comb_rhs_array_muxed30[2:0] 3'000 + assign $1\libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0[0:0] 1'0 sync always sync init - update \builder_comb_rhs_array_muxed30 $1\builder_comb_rhs_array_muxed30[2:0] + update \libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0 $1\libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0[0:0] end - attribute \src "ls180.v:2664.11-2664.48" - process $proc$ls180.v:2664$3788 + attribute \src "ls180.v:1341.12-1341.71" + process $proc$ls180.v:1341$2085 assign { } { } - assign $1\builder_comb_rhs_array_muxed31[1:0] 2'00 + assign $1\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0] 14'00000000000000 sync always sync init - update \builder_comb_rhs_array_muxed31 $1\builder_comb_rhs_array_muxed31[1:0] + update \libresocsim_libresocsim_adr_libresocsim_next_value1 $1\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0] end - attribute \src "ls180.v:2665.11-2665.47" - process $proc$ls180.v:2665$3789 + attribute \src "ls180.v:1342.5-1342.66" + process $proc$ls180.v:1342$2086 assign { } { } - assign $1\builder_sync_rhs_array_muxed0[1:0] 2'00 + assign $1\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0] 1'0 sync always sync init - update \builder_sync_rhs_array_muxed0 $1\builder_sync_rhs_array_muxed0[1:0] + update \libresocsim_libresocsim_adr_libresocsim_next_value_ce1 $1\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0] end - attribute \src "ls180.v:2666.12-2666.49" - process $proc$ls180.v:2666$3790 + attribute \src "ls180.v:1343.5-1343.62" + process $proc$ls180.v:1343$2087 assign { } { } - assign $1\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 + assign $1\libresocsim_libresocsim_we_libresocsim_next_value2[0:0] 1'0 sync always sync init - update \builder_sync_rhs_array_muxed1 $1\builder_sync_rhs_array_muxed1[12:0] + update \libresocsim_libresocsim_we_libresocsim_next_value2 $1\libresocsim_libresocsim_we_libresocsim_next_value2[0:0] end - attribute \src "ls180.v:2667.5-2667.41" - process $proc$ls180.v:2667$3791 + attribute \src "ls180.v:1344.5-1344.65" + process $proc$ls180.v:1344$2088 assign { } { } - assign $1\builder_sync_rhs_array_muxed2[0:0] 1'0 + assign $1\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0] 1'0 sync always sync init - update \builder_sync_rhs_array_muxed2 $1\builder_sync_rhs_array_muxed2[0:0] + update \libresocsim_libresocsim_we_libresocsim_next_value_ce2 $1\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0] end - attribute \src "ls180.v:2668.5-2668.41" - process $proc$ls180.v:2668$3792 + attribute \src "ls180.v:1345.5-1345.28" + process $proc$ls180.v:1345$2089 assign { } { } - assign $1\builder_sync_rhs_array_muxed3[0:0] 1'0 + assign $1\rhs_array_muxed0[0:0] 1'0 sync always sync init - update \builder_sync_rhs_array_muxed3 $1\builder_sync_rhs_array_muxed3[0:0] + update \rhs_array_muxed0 $1\rhs_array_muxed0[0:0] end - attribute \src "ls180.v:2669.5-2669.41" - process $proc$ls180.v:2669$3793 + attribute \src "ls180.v:1346.12-1346.36" + process $proc$ls180.v:1346$2090 assign { } { } - assign $1\builder_sync_rhs_array_muxed4[0:0] 1'0 + assign $1\rhs_array_muxed1[12:0] 13'0000000000000 sync always sync init - update \builder_sync_rhs_array_muxed4 $1\builder_sync_rhs_array_muxed4[0:0] + update \rhs_array_muxed1 $1\rhs_array_muxed1[12:0] end - attribute \src "ls180.v:2670.5-2670.41" - process $proc$ls180.v:2670$3794 + attribute \src "ls180.v:1347.11-1347.34" + process $proc$ls180.v:1347$2091 assign { } { } - assign $1\builder_sync_rhs_array_muxed5[0:0] 1'0 + assign $1\rhs_array_muxed2[1:0] 2'00 sync always sync init - update \builder_sync_rhs_array_muxed5 $1\builder_sync_rhs_array_muxed5[0:0] + update \rhs_array_muxed2 $1\rhs_array_muxed2[1:0] end - attribute \src "ls180.v:2671.5-2671.41" - process $proc$ls180.v:2671$3795 + attribute \src "ls180.v:1348.5-1348.28" + process $proc$ls180.v:1348$2092 assign { } { } - assign $1\builder_sync_rhs_array_muxed6[0:0] 1'0 + assign $1\rhs_array_muxed3[0:0] 1'0 sync always sync init - update \builder_sync_rhs_array_muxed6 $1\builder_sync_rhs_array_muxed6[0:0] + update \rhs_array_muxed3 $1\rhs_array_muxed3[0:0] end - attribute \src "ls180.v:2672.5-2672.39" - process $proc$ls180.v:2672$3796 + attribute \src "ls180.v:1349.5-1349.28" + process $proc$ls180.v:1349$2093 assign { } { } - assign $1\builder_sync_f_array_muxed0[0:0] 1'0 + assign $1\rhs_array_muxed4[0:0] 1'0 sync always sync init - update \builder_sync_f_array_muxed0 $1\builder_sync_f_array_muxed0[0:0] + update \rhs_array_muxed4 $1\rhs_array_muxed4[0:0] end - attribute \src "ls180.v:2673.5-2673.39" - process $proc$ls180.v:2673$3797 + attribute \src "ls180.v:135.11-135.69" + process $proc$ls180.v:135$1660 assign { } { } - assign $1\builder_sync_f_array_muxed1[0:0] 1'0 + assign $1\libresocsim_libresoc_constraintmanager_obj_sdram_dm[1:0] 2'00 sync always sync init - update \builder_sync_f_array_muxed1 $1\builder_sync_f_array_muxed1[0:0] + update \libresocsim_libresoc_constraintmanager_obj_sdram_dm $1\libresocsim_libresoc_constraintmanager_obj_sdram_dm[1:0] end - attribute \src "ls180.v:268.12-268.38" - process $proc$ls180.v:268$2937 + attribute \src "ls180.v:1350.5-1350.28" + process $proc$ls180.v:1350$2094 assign { } { } - assign $1\main_dfi_p0_rddata[15:0] 16'0000000000000000 + assign $1\rhs_array_muxed5[0:0] 1'0 sync always sync init - update \main_dfi_p0_rddata $1\main_dfi_p0_rddata[15:0] + update \rhs_array_muxed5 $1\rhs_array_muxed5[0:0] end - attribute \src "ls180.v:269.5-269.36" - process $proc$ls180.v:269$2938 + attribute \src "ls180.v:1351.5-1351.26" + process $proc$ls180.v:1351$2095 assign { } { } - assign $1\main_dfi_p0_rddata_valid[0:0] 1'0 + assign $1\t_array_muxed0[0:0] 1'0 sync always sync init - update \main_dfi_p0_rddata_valid $1\main_dfi_p0_rddata_valid[0:0] + update \t_array_muxed0 $1\t_array_muxed0[0:0] end - attribute \src "ls180.v:270.11-270.32" - process $proc$ls180.v:270$2939 + attribute \src "ls180.v:1352.5-1352.26" + process $proc$ls180.v:1352$2096 assign { } { } - assign $1\main_rddata_en[2:0] 3'000 + assign $1\t_array_muxed1[0:0] 1'0 sync always sync init - update \main_rddata_en $1\main_rddata_en[2:0] + update \t_array_muxed1 $1\t_array_muxed1[0:0] end - attribute \src "ls180.v:273.5-273.36" - process $proc$ls180.v:273$2940 + attribute \src "ls180.v:1353.5-1353.26" + process $proc$ls180.v:1353$2097 assign { } { } - assign $1\main_sdram_inti_p0_cas_n[0:0] 1'1 + assign $1\t_array_muxed2[0:0] 1'0 sync always sync init - update \main_sdram_inti_p0_cas_n $1\main_sdram_inti_p0_cas_n[0:0] + update \t_array_muxed2 $1\t_array_muxed2[0:0] end - attribute \src "ls180.v:2730.32-2730.66" - process $proc$ls180.v:2730$3798 + attribute \src "ls180.v:1354.5-1354.28" + process $proc$ls180.v:1354$2098 assign { } { } - assign $1\builder_multiregimpl0_regs0[0:0] 1'0 + assign $1\rhs_array_muxed6[0:0] 1'0 sync always sync init - update \builder_multiregimpl0_regs0 $1\builder_multiregimpl0_regs0[0:0] + update \rhs_array_muxed6 $1\rhs_array_muxed6[0:0] end - attribute \src "ls180.v:2731.32-2731.66" - process $proc$ls180.v:2731$3799 + attribute \src "ls180.v:1355.12-1355.36" + process $proc$ls180.v:1355$2099 assign { } { } - assign $1\builder_multiregimpl0_regs1[0:0] 1'0 + assign $1\rhs_array_muxed7[12:0] 13'0000000000000 sync always sync init - update \builder_multiregimpl0_regs1 $1\builder_multiregimpl0_regs1[0:0] + update \rhs_array_muxed7 $1\rhs_array_muxed7[12:0] end - attribute \src "ls180.v:2732.32-2732.66" - process $proc$ls180.v:2732$3800 + attribute \src "ls180.v:1356.11-1356.34" + process $proc$ls180.v:1356$2100 assign { } { } - assign $1\builder_multiregimpl1_regs0[0:0] 1'0 + assign $1\rhs_array_muxed8[1:0] 2'00 sync always sync init - update \builder_multiregimpl1_regs0 $1\builder_multiregimpl1_regs0[0:0] + update \rhs_array_muxed8 $1\rhs_array_muxed8[1:0] end - attribute \src "ls180.v:2733.32-2733.66" - process $proc$ls180.v:2733$3801 + attribute \src "ls180.v:1357.5-1357.28" + process $proc$ls180.v:1357$2101 assign { } { } - assign $1\builder_multiregimpl1_regs1[0:0] 1'0 + assign $1\rhs_array_muxed9[0:0] 1'0 sync always sync init - update \builder_multiregimpl1_regs1 $1\builder_multiregimpl1_regs1[0:0] + update \rhs_array_muxed9 $1\rhs_array_muxed9[0:0] end - attribute \src "ls180.v:2734.32-2734.66" - process $proc$ls180.v:2734$3802 + attribute \src "ls180.v:1358.5-1358.29" + process $proc$ls180.v:1358$2102 assign { } { } - assign $1\builder_multiregimpl2_regs0[0:0] 1'0 + assign $1\rhs_array_muxed10[0:0] 1'0 sync always sync init - update \builder_multiregimpl2_regs0 $1\builder_multiregimpl2_regs0[0:0] + update \rhs_array_muxed10 $1\rhs_array_muxed10[0:0] end - attribute \src "ls180.v:2735.32-2735.66" - process $proc$ls180.v:2735$3803 + attribute \src "ls180.v:1359.5-1359.29" + process $proc$ls180.v:1359$2103 assign { } { } - assign $1\builder_multiregimpl2_regs1[0:0] 1'0 + assign $1\rhs_array_muxed11[0:0] 1'0 sync always sync init - update \builder_multiregimpl2_regs1 $1\builder_multiregimpl2_regs1[0:0] + update \rhs_array_muxed11 $1\rhs_array_muxed11[0:0] end - attribute \src "ls180.v:2736.32-2736.66" - process $proc$ls180.v:2736$3804 + attribute \src "ls180.v:136.5-136.23" + process $proc$ls180.v:136$1661 assign { } { } - assign $1\builder_multiregimpl3_regs0[0:0] 1'0 + assign $1\sdram_clock[0:0] 1'0 sync always sync init - update \builder_multiregimpl3_regs0 $1\builder_multiregimpl3_regs0[0:0] + update \sdram_clock $1\sdram_clock[0:0] end - attribute \src "ls180.v:2737.32-2737.66" - process $proc$ls180.v:2737$3805 + attribute \src "ls180.v:1360.5-1360.26" + process $proc$ls180.v:1360$2104 assign { } { } - assign $1\builder_multiregimpl3_regs1[0:0] 1'0 + assign $1\t_array_muxed3[0:0] 1'0 sync always sync init - update \builder_multiregimpl3_regs1 $1\builder_multiregimpl3_regs1[0:0] + update \t_array_muxed3 $1\t_array_muxed3[0:0] end - attribute \src "ls180.v:2738.32-2738.66" - process $proc$ls180.v:2738$3806 + attribute \src "ls180.v:1361.5-1361.26" + process $proc$ls180.v:1361$2105 assign { } { } - assign $1\builder_multiregimpl4_regs0[0:0] 1'0 + assign $1\t_array_muxed4[0:0] 1'0 sync always sync init - update \builder_multiregimpl4_regs0 $1\builder_multiregimpl4_regs0[0:0] + update \t_array_muxed4 $1\t_array_muxed4[0:0] end - attribute \src "ls180.v:2739.32-2739.66" - process $proc$ls180.v:2739$3807 + attribute \src "ls180.v:1362.5-1362.26" + process $proc$ls180.v:1362$2106 assign { } { } - assign $1\builder_multiregimpl4_regs1[0:0] 1'0 + assign $1\t_array_muxed5[0:0] 1'0 sync always sync init - update \builder_multiregimpl4_regs1 $1\builder_multiregimpl4_regs1[0:0] + update \t_array_muxed5 $1\t_array_muxed5[0:0] end - attribute \src "ls180.v:274.5-274.35" - process $proc$ls180.v:274$2941 + attribute \src "ls180.v:1363.12-1363.37" + process $proc$ls180.v:1363$2107 assign { } { } - assign $1\main_sdram_inti_p0_cs_n[0:0] 1'1 + assign $1\rhs_array_muxed12[21:0] 22'0000000000000000000000 sync always sync init - update \main_sdram_inti_p0_cs_n $1\main_sdram_inti_p0_cs_n[0:0] + update \rhs_array_muxed12 $1\rhs_array_muxed12[21:0] end - attribute \src "ls180.v:2740.32-2740.66" - process $proc$ls180.v:2740$3808 + attribute \src "ls180.v:1364.5-1364.29" + process $proc$ls180.v:1364$2108 assign { } { } - assign $1\builder_multiregimpl5_regs0[0:0] 1'0 + assign $1\rhs_array_muxed13[0:0] 1'0 sync always sync init - update \builder_multiregimpl5_regs0 $1\builder_multiregimpl5_regs0[0:0] + update \rhs_array_muxed13 $1\rhs_array_muxed13[0:0] end - attribute \src "ls180.v:2741.32-2741.66" - process $proc$ls180.v:2741$3809 + attribute \src "ls180.v:1365.5-1365.29" + process $proc$ls180.v:1365$2109 assign { } { } - assign $1\builder_multiregimpl5_regs1[0:0] 1'0 + assign $1\rhs_array_muxed14[0:0] 1'0 sync always sync init - update \builder_multiregimpl5_regs1 $1\builder_multiregimpl5_regs1[0:0] + update \rhs_array_muxed14 $1\rhs_array_muxed14[0:0] end - attribute \src "ls180.v:2742.32-2742.66" - process $proc$ls180.v:2742$3810 + attribute \src "ls180.v:1366.12-1366.37" + process $proc$ls180.v:1366$2110 assign { } { } - assign $1\builder_multiregimpl6_regs0[0:0] 1'0 + assign $1\rhs_array_muxed15[21:0] 22'0000000000000000000000 sync always sync init - update \builder_multiregimpl6_regs0 $1\builder_multiregimpl6_regs0[0:0] + update \rhs_array_muxed15 $1\rhs_array_muxed15[21:0] end - attribute \src "ls180.v:2743.32-2743.66" - process $proc$ls180.v:2743$3811 + attribute \src "ls180.v:1367.5-1367.29" + process $proc$ls180.v:1367$2111 assign { } { } - assign $1\builder_multiregimpl6_regs1[0:0] 1'0 + assign $1\rhs_array_muxed16[0:0] 1'0 sync always sync init - update \builder_multiregimpl6_regs1 $1\builder_multiregimpl6_regs1[0:0] + update \rhs_array_muxed16 $1\rhs_array_muxed16[0:0] end - attribute \src "ls180.v:2744.32-2744.66" - process $proc$ls180.v:2744$3812 + attribute \src "ls180.v:1368.5-1368.29" + process $proc$ls180.v:1368$2112 assign { } { } - assign $1\builder_multiregimpl7_regs0[0:0] 1'0 + assign $1\rhs_array_muxed17[0:0] 1'0 sync always sync init - update \builder_multiregimpl7_regs0 $1\builder_multiregimpl7_regs0[0:0] + update \rhs_array_muxed17 $1\rhs_array_muxed17[0:0] end - attribute \src "ls180.v:2745.32-2745.66" - process $proc$ls180.v:2745$3813 + attribute \src "ls180.v:1369.12-1369.37" + process $proc$ls180.v:1369$2113 assign { } { } - assign $1\builder_multiregimpl7_regs1[0:0] 1'0 + assign $1\rhs_array_muxed18[21:0] 22'0000000000000000000000 sync always sync init - update \builder_multiregimpl7_regs1 $1\builder_multiregimpl7_regs1[0:0] + update \rhs_array_muxed18 $1\rhs_array_muxed18[21:0] end - attribute \src "ls180.v:2746.32-2746.66" - process $proc$ls180.v:2746$3814 + attribute \src "ls180.v:1370.5-1370.29" + process $proc$ls180.v:1370$2114 assign { } { } - assign $1\builder_multiregimpl8_regs0[0:0] 1'0 + assign $1\rhs_array_muxed19[0:0] 1'0 sync always sync init - update \builder_multiregimpl8_regs0 $1\builder_multiregimpl8_regs0[0:0] + update \rhs_array_muxed19 $1\rhs_array_muxed19[0:0] end - attribute \src "ls180.v:2747.32-2747.66" - process $proc$ls180.v:2747$3815 + attribute \src "ls180.v:1371.5-1371.29" + process $proc$ls180.v:1371$2115 assign { } { } - assign $1\builder_multiregimpl8_regs1[0:0] 1'0 + assign $1\rhs_array_muxed20[0:0] 1'0 sync always sync init - update \builder_multiregimpl8_regs1 $1\builder_multiregimpl8_regs1[0:0] + update \rhs_array_muxed20 $1\rhs_array_muxed20[0:0] end - attribute \src "ls180.v:2748.32-2748.66" - process $proc$ls180.v:2748$3816 + attribute \src "ls180.v:1372.12-1372.37" + process $proc$ls180.v:1372$2116 assign { } { } - assign $1\builder_multiregimpl9_regs0[0:0] 1'0 + assign $1\rhs_array_muxed21[21:0] 22'0000000000000000000000 sync always sync init - update \builder_multiregimpl9_regs0 $1\builder_multiregimpl9_regs0[0:0] + update \rhs_array_muxed21 $1\rhs_array_muxed21[21:0] end - attribute \src "ls180.v:2749.32-2749.66" - process $proc$ls180.v:2749$3817 + attribute \src "ls180.v:1373.5-1373.29" + process $proc$ls180.v:1373$2117 assign { } { } - assign $1\builder_multiregimpl9_regs1[0:0] 1'0 + assign $1\rhs_array_muxed22[0:0] 1'0 sync always sync init - update \builder_multiregimpl9_regs1 $1\builder_multiregimpl9_regs1[0:0] + update \rhs_array_muxed22 $1\rhs_array_muxed22[0:0] end - attribute \src "ls180.v:275.5-275.36" - process $proc$ls180.v:275$2942 + attribute \src "ls180.v:1374.5-1374.29" + process $proc$ls180.v:1374$2118 assign { } { } - assign $1\main_sdram_inti_p0_ras_n[0:0] 1'1 + assign $1\rhs_array_muxed23[0:0] 1'0 sync always sync init - update \main_sdram_inti_p0_ras_n $1\main_sdram_inti_p0_ras_n[0:0] + update \rhs_array_muxed23 $1\rhs_array_muxed23[0:0] end - attribute \src "ls180.v:2750.32-2750.67" - process $proc$ls180.v:2750$3818 + attribute \src "ls180.v:1375.12-1375.37" + process $proc$ls180.v:1375$2119 assign { } { } - assign $1\builder_multiregimpl10_regs0[0:0] 1'0 + assign $1\rhs_array_muxed24[28:0] 29'00000000000000000000000000000 sync always sync init - update \builder_multiregimpl10_regs0 $1\builder_multiregimpl10_regs0[0:0] + update \rhs_array_muxed24 $1\rhs_array_muxed24[28:0] end - attribute \src "ls180.v:2751.32-2751.67" - process $proc$ls180.v:2751$3819 + attribute \src "ls180.v:1376.12-1376.37" + process $proc$ls180.v:1376$2120 assign { } { } - assign $1\builder_multiregimpl10_regs1[0:0] 1'0 + assign $1\rhs_array_muxed25[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \builder_multiregimpl10_regs1 $1\builder_multiregimpl10_regs1[0:0] + update \rhs_array_muxed25 $1\rhs_array_muxed25[63:0] end - attribute \src "ls180.v:2752.32-2752.67" - process $proc$ls180.v:2752$3820 + attribute \src "ls180.v:1377.11-1377.35" + process $proc$ls180.v:1377$2121 assign { } { } - assign $1\builder_multiregimpl11_regs0[0:0] 1'0 + assign $1\rhs_array_muxed26[7:0] 8'00000000 sync always sync init - update \builder_multiregimpl11_regs0 $1\builder_multiregimpl11_regs0[0:0] + update \rhs_array_muxed26 $1\rhs_array_muxed26[7:0] end - attribute \src "ls180.v:2753.32-2753.67" - process $proc$ls180.v:2753$3821 + attribute \src "ls180.v:1378.5-1378.29" + process $proc$ls180.v:1378$2122 assign { } { } - assign $1\builder_multiregimpl11_regs1[0:0] 1'0 + assign $1\rhs_array_muxed27[0:0] 1'0 sync always sync init - update \builder_multiregimpl11_regs1 $1\builder_multiregimpl11_regs1[0:0] + update \rhs_array_muxed27 $1\rhs_array_muxed27[0:0] end - attribute \src "ls180.v:2754.32-2754.67" - process $proc$ls180.v:2754$3822 + attribute \src "ls180.v:1379.5-1379.29" + process $proc$ls180.v:1379$2123 assign { } { } - assign $1\builder_multiregimpl12_regs0[0:0] 1'0 + assign $1\rhs_array_muxed28[0:0] 1'0 sync always sync init - update \builder_multiregimpl12_regs0 $1\builder_multiregimpl12_regs0[0:0] + update \rhs_array_muxed28 $1\rhs_array_muxed28[0:0] end - attribute \src "ls180.v:2755.32-2755.67" - process $proc$ls180.v:2755$3823 + attribute \src "ls180.v:1380.5-1380.29" + process $proc$ls180.v:1380$2124 assign { } { } - assign $1\builder_multiregimpl12_regs1[0:0] 1'0 + assign $1\rhs_array_muxed29[0:0] 1'0 sync always sync init - update \builder_multiregimpl12_regs1 $1\builder_multiregimpl12_regs1[0:0] + update \rhs_array_muxed29 $1\rhs_array_muxed29[0:0] end - attribute \src "ls180.v:2756.32-2756.67" - process $proc$ls180.v:2756$3824 + attribute \src "ls180.v:1381.11-1381.35" + process $proc$ls180.v:1381$2125 assign { } { } - assign $1\builder_multiregimpl13_regs0[0:0] 1'0 + assign $1\rhs_array_muxed30[2:0] 3'000 sync always sync init - update \builder_multiregimpl13_regs0 $1\builder_multiregimpl13_regs0[0:0] + update \rhs_array_muxed30 $1\rhs_array_muxed30[2:0] end - attribute \src "ls180.v:2757.32-2757.67" - process $proc$ls180.v:2757$3825 + attribute \src "ls180.v:1382.11-1382.35" + process $proc$ls180.v:1382$2126 assign { } { } - assign $1\builder_multiregimpl13_regs1[0:0] 1'0 + assign $1\rhs_array_muxed31[1:0] 2'00 sync always sync init - update \builder_multiregimpl13_regs1 $1\builder_multiregimpl13_regs1[0:0] + update \rhs_array_muxed31 $1\rhs_array_muxed31[1:0] end - attribute \src "ls180.v:2758.32-2758.67" - process $proc$ls180.v:2758$3826 + attribute \src "ls180.v:1383.11-1383.30" + process $proc$ls180.v:1383$2127 assign { } { } - assign $1\builder_multiregimpl14_regs0[0:0] 1'0 + assign $1\array_muxed0[1:0] 2'00 sync always sync init - update \builder_multiregimpl14_regs0 $1\builder_multiregimpl14_regs0[0:0] + update \array_muxed0 $1\array_muxed0[1:0] end - attribute \src "ls180.v:2759.32-2759.67" - process $proc$ls180.v:2759$3827 + attribute \src "ls180.v:1384.12-1384.32" + process $proc$ls180.v:1384$2128 assign { } { } - assign $1\builder_multiregimpl14_regs1[0:0] 1'0 + assign $1\array_muxed1[12:0] 13'0000000000000 sync always sync init - update \builder_multiregimpl14_regs1 $1\builder_multiregimpl14_regs1[0:0] + update \array_muxed1 $1\array_muxed1[12:0] end - attribute \src "ls180.v:276.5-276.35" - process $proc$ls180.v:276$2943 + attribute \src "ls180.v:1385.5-1385.24" + process $proc$ls180.v:1385$2129 assign { } { } - assign $1\main_sdram_inti_p0_we_n[0:0] 1'1 + assign $1\array_muxed2[0:0] 1'0 sync always sync init - update \main_sdram_inti_p0_we_n $1\main_sdram_inti_p0_we_n[0:0] + update \array_muxed2 $1\array_muxed2[0:0] end - attribute \src "ls180.v:2760.32-2760.67" - process $proc$ls180.v:2760$3828 + attribute \src "ls180.v:1386.5-1386.24" + process $proc$ls180.v:1386$2130 assign { } { } - assign $1\builder_multiregimpl15_regs0[0:0] 1'0 + assign $1\array_muxed3[0:0] 1'0 sync always sync init - update \builder_multiregimpl15_regs0 $1\builder_multiregimpl15_regs0[0:0] + update \array_muxed3 $1\array_muxed3[0:0] end - attribute \src "ls180.v:2761.32-2761.67" - process $proc$ls180.v:2761$3829 + attribute \src "ls180.v:1387.5-1387.24" + process $proc$ls180.v:1387$2131 assign { } { } - assign $1\builder_multiregimpl15_regs1[0:0] 1'0 + assign $1\array_muxed4[0:0] 1'0 sync always sync init - update \builder_multiregimpl15_regs1 $1\builder_multiregimpl15_regs1[0:0] + update \array_muxed4 $1\array_muxed4[0:0] end - attribute \src "ls180.v:2762.32-2762.67" - process $proc$ls180.v:2762$3830 + attribute \src "ls180.v:1388.5-1388.24" + process $proc$ls180.v:1388$2132 assign { } { } - assign $1\builder_multiregimpl16_regs0[0:0] 1'0 + assign $1\array_muxed5[0:0] 1'0 sync always sync init - update \builder_multiregimpl16_regs0 $1\builder_multiregimpl16_regs0[0:0] + update \array_muxed5 $1\array_muxed5[0:0] end - attribute \src "ls180.v:2763.32-2763.67" - process $proc$ls180.v:2763$3831 + attribute \src "ls180.v:1389.5-1389.24" + process $proc$ls180.v:1389$2133 assign { } { } - assign $1\builder_multiregimpl16_regs1[0:0] 1'0 + assign $1\array_muxed6[0:0] 1'0 sync always sync init - update \builder_multiregimpl16_regs1 $1\builder_multiregimpl16_regs1[0:0] + update \array_muxed6 $1\array_muxed6[0:0] end - attribute \src "ls180.v:2798.1-2803.4" - process $proc$ls180.v:2798$25 + attribute \src "ls180.v:1446.32-1446.44" + process $proc$ls180.v:1446$2134 assign { } { } - assign $0\main_libresocsim_libresoc_interrupt[15:0] [11:2] 10'0000000000 - assign $0\main_libresocsim_libresoc_interrupt[15:0] [15:12] { 1'0 \eint } - assign $0\main_libresocsim_libresoc_interrupt[15:0] [0] \main_libresocsim_irq - assign $0\main_libresocsim_libresoc_interrupt[15:0] [1] \main_uart_irq + assign $1\regs0[0:0] 1'0 sync always - update \main_libresocsim_libresoc_interrupt $0\main_libresocsim_libresoc_interrupt[15:0] - end - attribute \src "ls180.v:280.5-280.36" - process $proc$ls180.v:280$2944 - assign { } { } - assign $0\main_sdram_inti_p0_act_n[0:0] 1'1 - sync always - update \main_sdram_inti_p0_act_n $0\main_sdram_inti_p0_act_n[0:0] sync init + update \regs0 $1\regs0[0:0] end - attribute \src "ls180.v:2805.1-2815.4" - process $proc$ls180.v:2805$27 - assign { } { } - assign $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] 0 - attribute \src "ls180.v:2807.2-2814.9" - switch \main_converter0_counter - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] \main_interface0_converted_interface_dat_w [31:0] - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] \main_interface0_converted_interface_dat_w [63:32] - case - end - sync always - update \main_libresocsim_libresoc_xics_icp_dat_w $0\main_libresocsim_libresoc_xics_icp_dat_w[31:0] - end - attribute \src "ls180.v:2817.1-2863.4" - process $proc$ls180.v:2817$28 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_converter0_counter_converter0_next_value[0:0] 1'0 - assign $0\main_converter0_counter_converter0_next_value_ce[0:0] 1'0 - assign $0\main_interface0_converted_interface_ack[0:0] 1'0 - assign $0\main_libresocsim_libresoc_xics_icp_adr[29:0] 30'000000000000000000000000000000 - assign $0\main_libresocsim_libresoc_xics_icp_sel[3:0] 4'0000 - assign $0\main_converter0_skip[0:0] 1'0 - assign $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] 1'0 - assign $0\main_libresocsim_libresoc_xics_icp_stb[0:0] 1'0 - assign $0\main_libresocsim_libresoc_xics_icp_we[0:0] 1'0 - assign $0\builder_converter0_next_state[0:0] \builder_converter0_state - attribute \src "ls180.v:2829.2-2862.9" - switch \builder_converter0_state - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_libresocsim_libresoc_xics_icp_adr[29:0] { \main_interface0_converted_interface_adr [28:0] \main_converter0_counter } - attribute \src "ls180.v:2832.4-2839.11" - switch \main_converter0_counter - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_libresocsim_libresoc_xics_icp_sel[3:0] \main_interface0_converted_interface_sel [3:0] - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_libresocsim_libresoc_xics_icp_sel[3:0] \main_interface0_converted_interface_sel [7:4] - case - end - attribute \src "ls180.v:2840.4-2853.7" - switch $and$ls180.v:2840$29_Y - attribute \src "ls180.v:2840.8-2840.91" - case 1'1 - assign $0\main_converter0_skip[0:0] $eq$ls180.v:2841$30_Y - assign $0\main_libresocsim_libresoc_xics_icp_we[0:0] \main_interface0_converted_interface_we - assign $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] $not$ls180.v:2843$31_Y - assign $0\main_libresocsim_libresoc_xics_icp_stb[0:0] $not$ls180.v:2844$32_Y - attribute \src "ls180.v:2845.5-2852.8" - switch $or$ls180.v:2845$33_Y - attribute \src "ls180.v:2845.9-2845.72" - case 1'1 - assign $0\main_converter0_counter_converter0_next_value[0:0] $add$ls180.v:2846$34_Y - assign $0\main_converter0_counter_converter0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2848.6-2851.9" - switch $eq$ls180.v:2848$35_Y - attribute \src "ls180.v:2848.10-2848.43" - case 1'1 - assign $0\main_interface0_converted_interface_ack[0:0] 1'1 - assign $0\builder_converter0_next_state[0:0] 1'0 - case - end - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_converter0_counter_converter0_next_value[0:0] 1'0 - assign $0\main_converter0_counter_converter0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2858.4-2860.7" - switch $and$ls180.v:2858$36_Y - attribute \src "ls180.v:2858.8-2858.91" - case 1'1 - assign $0\builder_converter0_next_state[0:0] 1'1 - case - end - end - sync always - update \main_libresocsim_libresoc_xics_icp_adr $0\main_libresocsim_libresoc_xics_icp_adr[29:0] - update \main_libresocsim_libresoc_xics_icp_sel $0\main_libresocsim_libresoc_xics_icp_sel[3:0] - update \main_libresocsim_libresoc_xics_icp_cyc $0\main_libresocsim_libresoc_xics_icp_cyc[0:0] - update \main_libresocsim_libresoc_xics_icp_stb $0\main_libresocsim_libresoc_xics_icp_stb[0:0] - update \main_libresocsim_libresoc_xics_icp_we $0\main_libresocsim_libresoc_xics_icp_we[0:0] - update \main_interface0_converted_interface_ack $0\main_interface0_converted_interface_ack[0:0] - update \main_converter0_skip $0\main_converter0_skip[0:0] - update \builder_converter0_next_state $0\builder_converter0_next_state[0:0] - update \main_converter0_counter_converter0_next_value $0\main_converter0_counter_converter0_next_value[0:0] - update \main_converter0_counter_converter0_next_value_ce $0\main_converter0_counter_converter0_next_value_ce[0:0] - end - attribute \src "ls180.v:285.12-285.45" - process $proc$ls180.v:285$2945 + attribute \src "ls180.v:1447.32-1447.44" + process $proc$ls180.v:1447$2135 assign { } { } - assign $1\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 + assign $1\regs1[0:0] 1'0 sync always sync init - update \main_sdram_inti_p0_rddata $1\main_sdram_inti_p0_rddata[15:0] + update \regs1 $1\regs1[0:0] end - attribute \src "ls180.v:286.5-286.43" - process $proc$ls180.v:286$2946 + attribute \src "ls180.v:147.5-147.35" + process $proc$ls180.v:147$1662 assign { } { } - assign $1\main_sdram_inti_p0_rddata_valid[0:0] 1'0 + assign $1\libresocsim_ram_bus_ack[0:0] 1'0 sync always sync init - update \main_sdram_inti_p0_rddata_valid $1\main_sdram_inti_p0_rddata_valid[0:0] + update \libresocsim_ram_bus_ack $1\libresocsim_ram_bus_ack[0:0] end - attribute \src "ls180.v:2865.1-2875.4" - process $proc$ls180.v:2865$38 + attribute \src "ls180.v:1507.1-1512.4" + process $proc$ls180.v:1507$23 assign { } { } - assign $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] 0 - attribute \src "ls180.v:2867.2-2874.9" - switch \main_converter1_counter - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] \main_interface1_converted_interface_dat_w [31:0] - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] \main_interface1_converted_interface_dat_w [63:32] - case - end + assign $0\libresocsim_libresoc_interrupt[15:0] [12:2] 11'00000000000 + assign $0\libresocsim_libresoc_interrupt[15:0] [15:13] \eint + assign $0\libresocsim_libresoc_interrupt[15:0] [0] \libresocsim_irq + assign $0\libresocsim_libresoc_interrupt[15:0] [1] \irq sync always - update \main_libresocsim_libresoc_xics_ics_dat_w $0\main_libresocsim_libresoc_xics_ics_dat_w[31:0] + update \libresocsim_libresoc_interrupt $0\libresocsim_libresoc_interrupt[15:0] end - attribute \src "ls180.v:2877.1-2923.4" - process $proc$ls180.v:2877$39 - assign { } { } - assign { } { } + attribute \src "ls180.v:151.5-151.35" + process $proc$ls180.v:151$1663 assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_converter1_counter_converter1_next_value[0:0] 1'0 - assign $0\main_interface1_converted_interface_ack[0:0] 1'0 - assign $0\main_converter1_counter_converter1_next_value_ce[0:0] 1'0 - assign $0\main_libresocsim_libresoc_xics_ics_adr[29:0] 30'000000000000000000000000000000 - assign $0\main_libresocsim_libresoc_xics_ics_sel[3:0] 4'0000 - assign $0\main_converter1_skip[0:0] 1'0 - assign $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] 1'0 - assign $0\main_libresocsim_libresoc_xics_ics_stb[0:0] 1'0 - assign $0\main_libresocsim_libresoc_xics_ics_we[0:0] 1'0 - assign { } { } - assign $0\builder_converter1_next_state[0:0] \builder_converter1_state - attribute \src "ls180.v:2889.2-2922.9" - switch \builder_converter1_state - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_libresocsim_libresoc_xics_ics_adr[29:0] { \main_interface1_converted_interface_adr [28:0] \main_converter1_counter } - attribute \src "ls180.v:2892.4-2899.11" - switch \main_converter1_counter - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_libresocsim_libresoc_xics_ics_sel[3:0] \main_interface1_converted_interface_sel [3:0] - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_libresocsim_libresoc_xics_ics_sel[3:0] \main_interface1_converted_interface_sel [7:4] - case - end - attribute \src "ls180.v:2900.4-2913.7" - switch $and$ls180.v:2900$40_Y - attribute \src "ls180.v:2900.8-2900.91" - case 1'1 - assign $0\main_converter1_skip[0:0] $eq$ls180.v:2901$41_Y - assign $0\main_libresocsim_libresoc_xics_ics_we[0:0] \main_interface1_converted_interface_we - assign $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] $not$ls180.v:2903$42_Y - assign $0\main_libresocsim_libresoc_xics_ics_stb[0:0] $not$ls180.v:2904$43_Y - attribute \src "ls180.v:2905.5-2912.8" - switch $or$ls180.v:2905$44_Y - attribute \src "ls180.v:2905.9-2905.72" - case 1'1 - assign $0\main_converter1_counter_converter1_next_value[0:0] $add$ls180.v:2906$45_Y - assign $0\main_converter1_counter_converter1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2908.6-2911.9" - switch $eq$ls180.v:2908$46_Y - attribute \src "ls180.v:2908.10-2908.43" - case 1'1 - assign $0\main_interface1_converted_interface_ack[0:0] 1'1 - assign $0\builder_converter1_next_state[0:0] 1'0 - case - end - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_converter1_counter_converter1_next_value[0:0] 1'0 - assign $0\main_converter1_counter_converter1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2918.4-2920.7" - switch $and$ls180.v:2918$47_Y - attribute \src "ls180.v:2918.8-2918.91" - case 1'1 - assign $0\builder_converter1_next_state[0:0] 1'1 - case - end - end + assign $0\libresocsim_ram_bus_err[0:0] 1'0 sync always - update \main_libresocsim_libresoc_xics_ics_adr $0\main_libresocsim_libresoc_xics_ics_adr[29:0] - update \main_libresocsim_libresoc_xics_ics_sel $0\main_libresocsim_libresoc_xics_ics_sel[3:0] - update \main_libresocsim_libresoc_xics_ics_cyc $0\main_libresocsim_libresoc_xics_ics_cyc[0:0] - update \main_libresocsim_libresoc_xics_ics_stb $0\main_libresocsim_libresoc_xics_ics_stb[0:0] - update \main_libresocsim_libresoc_xics_ics_we $0\main_libresocsim_libresoc_xics_ics_we[0:0] - update \main_interface1_converted_interface_ack $0\main_interface1_converted_interface_ack[0:0] - update \main_converter1_skip $0\main_converter1_skip[0:0] - update \builder_converter1_next_state $0\builder_converter1_next_state[0:0] - update \main_converter1_counter_converter1_next_value $0\main_converter1_counter_converter1_next_value[0:0] - update \main_converter1_counter_converter1_next_value_ce $0\main_converter1_counter_converter1_next_value_ce[0:0] + update \libresocsim_ram_bus_err $0\libresocsim_ram_bus_err[0:0] + sync init end - attribute \src "ls180.v:2925.1-2935.4" - process $proc$ls180.v:2925$49 + attribute \src "ls180.v:1514.1-1524.4" + process $proc$ls180.v:1514$25 assign { } { } - assign $0\main_wb_sdram_dat_w[31:0] 0 - attribute \src "ls180.v:2927.2-2934.9" - switch \main_socbushandler_counter + assign $0\libresocsim_libresoc_xics_icp_dat_w[31:0] 0 + attribute \src "ls180.v:1516.2-1523.9" + switch \converter0_counter attribute \src "ls180.v:0.0-0.0" case 1'0 - assign $0\main_wb_sdram_dat_w[31:0] \main_socbushandler_converted_interface_dat_w [31:0] + assign $0\libresocsim_libresoc_xics_icp_dat_w[31:0] \interface0_converted_interface_dat_w [31:0] attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_wb_sdram_dat_w[31:0] \main_socbushandler_converted_interface_dat_w [63:32] + assign $0\libresocsim_libresoc_xics_icp_dat_w[31:0] \interface0_converted_interface_dat_w [63:32] case end sync always - update \main_wb_sdram_dat_w $0\main_wb_sdram_dat_w[31:0] + update \libresocsim_libresoc_xics_icp_dat_w $0\libresocsim_libresoc_xics_icp_dat_w[31:0] end - attribute \src "ls180.v:2937.1-2983.4" - process $proc$ls180.v:2937$50 + attribute \src "ls180.v:1526.1-1572.4" + process $proc$ls180.v:1526$26 assign { } { } assign { } { } assign { } { } @@ -288009,52 +263278,52 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_wb_sdram_we[0:0] 1'0 - assign $0\main_wb_sdram_adr[29:0] 30'000000000000000000000000000000 - assign $0\main_socbushandler_converted_interface_ack[0:0] 1'0 - assign $0\main_wb_sdram_sel[3:0] 4'0000 - assign $0\main_wb_sdram_cyc[0:0] 1'0 - assign $0\main_wb_sdram_stb[0:0] 1'0 - assign $0\main_socbushandler_skip[0:0] 1'0 + assign $0\converter0_counter_subfragments_converter0_next_value_ce[0:0] 1'0 + assign $0\converter0_skip[0:0] 1'0 + assign $0\libresocsim_libresoc_xics_icp_adr[29:0] 30'000000000000000000000000000000 + assign $0\interface0_converted_interface_ack[0:0] 1'0 + assign $0\libresocsim_libresoc_xics_icp_sel[3:0] 4'0000 + assign $0\libresocsim_libresoc_xics_icp_cyc[0:0] 1'0 + assign $0\libresocsim_libresoc_xics_icp_stb[0:0] 1'0 + assign $0\libresocsim_libresoc_xics_icp_we[0:0] 1'0 assign { } { } - assign $0\main_socbushandler_counter_converter2_next_value[0:0] 1'0 - assign $0\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'0 - assign $0\builder_converter2_next_state[0:0] \builder_converter2_state - attribute \src "ls180.v:2949.2-2982.9" - switch \builder_converter2_state + assign $0\converter0_counter_subfragments_converter0_next_value[0:0] 1'0 + assign $0\subfragments_converter0_next_state[0:0] \subfragments_converter0_state + attribute \src "ls180.v:1538.2-1571.9" + switch \subfragments_converter0_state attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_wb_sdram_adr[29:0] { \main_socbushandler_converted_interface_adr [28:0] \main_socbushandler_counter } - attribute \src "ls180.v:2952.4-2959.11" - switch \main_socbushandler_counter + assign $0\libresocsim_libresoc_xics_icp_adr[29:0] { \interface0_converted_interface_adr [28:0] \converter0_counter } + attribute \src "ls180.v:1541.4-1548.11" + switch \converter0_counter attribute \src "ls180.v:0.0-0.0" case 1'0 - assign $0\main_wb_sdram_sel[3:0] \main_socbushandler_converted_interface_sel [3:0] + assign $0\libresocsim_libresoc_xics_icp_sel[3:0] \interface0_converted_interface_sel [3:0] attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_wb_sdram_sel[3:0] \main_socbushandler_converted_interface_sel [7:4] + assign $0\libresocsim_libresoc_xics_icp_sel[3:0] \interface0_converted_interface_sel [7:4] case end - attribute \src "ls180.v:2960.4-2973.7" - switch $and$ls180.v:2960$51_Y - attribute \src "ls180.v:2960.8-2960.97" + attribute \src "ls180.v:1549.4-1562.7" + switch $and$ls180.v:1549$27_Y + attribute \src "ls180.v:1549.8-1549.81" case 1'1 - assign $0\main_socbushandler_skip[0:0] $eq$ls180.v:2961$52_Y - assign $0\main_wb_sdram_we[0:0] \main_socbushandler_converted_interface_we - assign $0\main_wb_sdram_cyc[0:0] $not$ls180.v:2963$53_Y - assign $0\main_wb_sdram_stb[0:0] $not$ls180.v:2964$54_Y - attribute \src "ls180.v:2965.5-2972.8" - switch $or$ls180.v:2965$55_Y - attribute \src "ls180.v:2965.9-2965.54" + assign $0\converter0_skip[0:0] $eq$ls180.v:1550$28_Y + assign $0\libresocsim_libresoc_xics_icp_we[0:0] \interface0_converted_interface_we + assign $0\libresocsim_libresoc_xics_icp_cyc[0:0] $not$ls180.v:1552$29_Y + assign $0\libresocsim_libresoc_xics_icp_stb[0:0] $not$ls180.v:1553$30_Y + attribute \src "ls180.v:1554.5-1561.8" + switch $or$ls180.v:1554$31_Y + attribute \src "ls180.v:1554.9-1554.62" case 1'1 - assign $0\main_socbushandler_counter_converter2_next_value[0:0] $add$ls180.v:2966$56_Y - assign $0\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2968.6-2971.9" - switch $eq$ls180.v:2968$57_Y - attribute \src "ls180.v:2968.10-2968.46" + assign $0\converter0_counter_subfragments_converter0_next_value[0:0] $add$ls180.v:1555$32_Y + assign $0\converter0_counter_subfragments_converter0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:1557.6-1560.9" + switch $eq$ls180.v:1557$33_Y + attribute \src "ls180.v:1557.10-1557.38" case 1'1 - assign $0\main_socbushandler_converted_interface_ack[0:0] 1'1 - assign $0\builder_converter2_next_state[0:0] 1'0 + assign $0\interface0_converted_interface_ack[0:0] 1'1 + assign $0\subfragments_converter0_next_state[0:0] 1'0 case end case @@ -288063,766 +263332,79 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case - assign $0\main_socbushandler_counter_converter2_next_value[0:0] 1'0 - assign $0\main_socbushandler_counter_converter2_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:2978.4-2980.7" - switch $and$ls180.v:2978$58_Y - attribute \src "ls180.v:2978.8-2978.97" + assign $0\converter0_counter_subfragments_converter0_next_value[0:0] 1'0 + assign $0\converter0_counter_subfragments_converter0_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:1567.4-1569.7" + switch $and$ls180.v:1567$34_Y + attribute \src "ls180.v:1567.8-1567.81" case 1'1 - assign $0\builder_converter2_next_state[0:0] 1'1 + assign $0\subfragments_converter0_next_state[0:0] 1'1 case end end sync always - update \main_wb_sdram_adr $0\main_wb_sdram_adr[29:0] - update \main_wb_sdram_sel $0\main_wb_sdram_sel[3:0] - update \main_wb_sdram_cyc $0\main_wb_sdram_cyc[0:0] - update \main_wb_sdram_stb $0\main_wb_sdram_stb[0:0] - update \main_wb_sdram_we $0\main_wb_sdram_we[0:0] - update \main_socbushandler_converted_interface_ack $0\main_socbushandler_converted_interface_ack[0:0] - update \main_socbushandler_skip $0\main_socbushandler_skip[0:0] - update \builder_converter2_next_state $0\builder_converter2_next_state[0:0] - update \main_socbushandler_counter_converter2_next_value $0\main_socbushandler_counter_converter2_next_value[0:0] - update \main_socbushandler_counter_converter2_next_value_ce $0\main_socbushandler_counter_converter2_next_value_ce[0:0] - end - attribute \src "ls180.v:2986.1-2996.4" - process $proc$ls180.v:2986$59 - assign { } { } - assign { } { } - assign $0\main_libresocsim_we[7:0] [0] $and$ls180.v:2988$62_Y - assign $0\main_libresocsim_we[7:0] [1] $and$ls180.v:2989$65_Y - assign $0\main_libresocsim_we[7:0] [2] $and$ls180.v:2990$68_Y - assign $0\main_libresocsim_we[7:0] [3] $and$ls180.v:2991$71_Y - assign $0\main_libresocsim_we[7:0] [4] $and$ls180.v:2992$74_Y - assign $0\main_libresocsim_we[7:0] [5] $and$ls180.v:2993$77_Y - assign $0\main_libresocsim_we[7:0] [6] $and$ls180.v:2994$80_Y - assign $0\main_libresocsim_we[7:0] [7] $and$ls180.v:2995$83_Y - sync always - update \main_libresocsim_we $0\main_libresocsim_we[7:0] - end - attribute \src "ls180.v:3002.1-3007.4" - process $proc$ls180.v:3002$85 - assign { } { } - assign $0\main_libresocsim_zero_clear[0:0] 1'0 - attribute \src "ls180.v:3004.2-3006.5" - switch $and$ls180.v:3004$86_Y - attribute \src "ls180.v:3004.6-3004.90" - case 1'1 - assign $0\main_libresocsim_zero_clear[0:0] 1'1 - case - end - sync always - update \main_libresocsim_zero_clear $0\main_libresocsim_zero_clear[0:0] - end - attribute \src "ls180.v:301.12-301.46" - process $proc$ls180.v:301$2947 - assign { } { } - assign $1\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_slave_p0_rddata $1\main_sdram_slave_p0_rddata[15:0] - end - attribute \src "ls180.v:3011.1-3021.4" - process $proc$ls180.v:3011$88 - assign { } { } - assign { } { } - assign $0\main_ram_we[7:0] [0] $and$ls180.v:3013$91_Y - assign $0\main_ram_we[7:0] [1] $and$ls180.v:3014$94_Y - assign $0\main_ram_we[7:0] [2] $and$ls180.v:3015$97_Y - assign $0\main_ram_we[7:0] [3] $and$ls180.v:3016$100_Y - assign $0\main_ram_we[7:0] [4] $and$ls180.v:3017$103_Y - assign $0\main_ram_we[7:0] [5] $and$ls180.v:3018$106_Y - assign $0\main_ram_we[7:0] [6] $and$ls180.v:3019$109_Y - assign $0\main_ram_we[7:0] [7] $and$ls180.v:3020$112_Y - sync always - update \main_ram_we $0\main_ram_we[7:0] - end - attribute \src "ls180.v:302.5-302.44" - process $proc$ls180.v:302$2948 - assign { } { } - assign $1\main_sdram_slave_p0_rddata_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_slave_p0_rddata_valid $1\main_sdram_slave_p0_rddata_valid[0:0] - end - attribute \src "ls180.v:303.12-303.48" - process $proc$ls180.v:303$2949 - assign { } { } - assign $1\main_sdram_master_p0_address[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_master_p0_address $1\main_sdram_master_p0_address[12:0] - end - attribute \src "ls180.v:304.11-304.43" - process $proc$ls180.v:304$2950 - assign { } { } - assign $1\main_sdram_master_p0_bank[1:0] 2'00 - sync always - sync init - update \main_sdram_master_p0_bank $1\main_sdram_master_p0_bank[1:0] - end - attribute \src "ls180.v:305.5-305.38" - process $proc$ls180.v:305$2951 - assign { } { } - assign $1\main_sdram_master_p0_cas_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_cas_n $1\main_sdram_master_p0_cas_n[0:0] - end - attribute \src "ls180.v:306.5-306.37" - process $proc$ls180.v:306$2952 - assign { } { } - assign $1\main_sdram_master_p0_cs_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_cs_n $1\main_sdram_master_p0_cs_n[0:0] - end - attribute \src "ls180.v:3060.1-3114.4" - process $proc$ls180.v:3060$113 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 - assign $0\main_sdram_slave_p0_rddata_valid[0:0] 1'0 - assign $0\main_sdram_master_p0_address[12:0] 13'0000000000000 - assign $0\main_sdram_master_p0_bank[1:0] 2'00 - assign $0\main_sdram_master_p0_cas_n[0:0] 1'1 - assign $0\main_sdram_master_p0_cs_n[0:0] 1'1 - assign $0\main_sdram_master_p0_ras_n[0:0] 1'1 - assign $0\main_sdram_master_p0_we_n[0:0] 1'1 - assign $0\main_sdram_master_p0_cke[0:0] 1'0 - assign $0\main_sdram_master_p0_odt[0:0] 1'0 - assign $0\main_sdram_master_p0_reset_n[0:0] 1'0 - assign $0\main_sdram_master_p0_act_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 - assign $0\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 - assign $0\main_sdram_inti_p0_rddata_valid[0:0] 1'0 - assign $0\main_sdram_master_p0_wrdata_en[0:0] 1'0 - assign $0\main_sdram_master_p0_wrdata_mask[1:0] 2'00 - assign $0\main_sdram_master_p0_rddata_en[0:0] 1'0 - attribute \src "ls180.v:3079.2-3113.5" - switch \main_sdram_sel - attribute \src "ls180.v:3079.6-3079.20" - case 1'1 - assign $0\main_sdram_master_p0_address[12:0] \main_sdram_slave_p0_address - assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_slave_p0_bank - assign $0\main_sdram_master_p0_cas_n[0:0] \main_sdram_slave_p0_cas_n - assign $0\main_sdram_master_p0_cs_n[0:0] \main_sdram_slave_p0_cs_n - assign $0\main_sdram_master_p0_ras_n[0:0] \main_sdram_slave_p0_ras_n - assign $0\main_sdram_master_p0_we_n[0:0] \main_sdram_slave_p0_we_n - assign $0\main_sdram_master_p0_cke[0:0] \main_sdram_slave_p0_cke - assign $0\main_sdram_master_p0_odt[0:0] \main_sdram_slave_p0_odt - assign $0\main_sdram_master_p0_reset_n[0:0] \main_sdram_slave_p0_reset_n - assign $0\main_sdram_master_p0_act_n[0:0] \main_sdram_slave_p0_act_n - assign $0\main_sdram_master_p0_wrdata[15:0] \main_sdram_slave_p0_wrdata - assign $0\main_sdram_master_p0_wrdata_en[0:0] \main_sdram_slave_p0_wrdata_en - assign $0\main_sdram_master_p0_wrdata_mask[1:0] \main_sdram_slave_p0_wrdata_mask - assign $0\main_sdram_master_p0_rddata_en[0:0] \main_sdram_slave_p0_rddata_en - assign $0\main_sdram_slave_p0_rddata[15:0] \main_sdram_master_p0_rddata - assign $0\main_sdram_slave_p0_rddata_valid[0:0] \main_sdram_master_p0_rddata_valid - attribute \src "ls180.v:3096.6-3096.10" - case - assign $0\main_sdram_master_p0_address[12:0] \main_sdram_inti_p0_address - assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_inti_p0_bank - assign $0\main_sdram_master_p0_cas_n[0:0] \main_sdram_inti_p0_cas_n - assign $0\main_sdram_master_p0_cs_n[0:0] \main_sdram_inti_p0_cs_n - assign $0\main_sdram_master_p0_ras_n[0:0] \main_sdram_inti_p0_ras_n - assign $0\main_sdram_master_p0_we_n[0:0] \main_sdram_inti_p0_we_n - assign $0\main_sdram_master_p0_cke[0:0] \main_sdram_inti_p0_cke - assign $0\main_sdram_master_p0_odt[0:0] \main_sdram_inti_p0_odt - assign $0\main_sdram_master_p0_reset_n[0:0] \main_sdram_inti_p0_reset_n - assign $0\main_sdram_master_p0_act_n[0:0] \main_sdram_inti_p0_act_n - assign $0\main_sdram_master_p0_wrdata[15:0] \main_sdram_inti_p0_wrdata - assign $0\main_sdram_master_p0_wrdata_en[0:0] \main_sdram_inti_p0_wrdata_en - assign $0\main_sdram_master_p0_wrdata_mask[1:0] \main_sdram_inti_p0_wrdata_mask - assign $0\main_sdram_master_p0_rddata_en[0:0] \main_sdram_inti_p0_rddata_en - assign $0\main_sdram_inti_p0_rddata[15:0] \main_sdram_master_p0_rddata - assign $0\main_sdram_inti_p0_rddata_valid[0:0] \main_sdram_master_p0_rddata_valid - end - sync always - update \main_sdram_inti_p0_rddata $0\main_sdram_inti_p0_rddata[15:0] - update \main_sdram_inti_p0_rddata_valid $0\main_sdram_inti_p0_rddata_valid[0:0] - update \main_sdram_slave_p0_rddata $0\main_sdram_slave_p0_rddata[15:0] - update \main_sdram_slave_p0_rddata_valid $0\main_sdram_slave_p0_rddata_valid[0:0] - update \main_sdram_master_p0_address $0\main_sdram_master_p0_address[12:0] - update \main_sdram_master_p0_bank $0\main_sdram_master_p0_bank[1:0] - update \main_sdram_master_p0_cas_n $0\main_sdram_master_p0_cas_n[0:0] - update \main_sdram_master_p0_cs_n $0\main_sdram_master_p0_cs_n[0:0] - update \main_sdram_master_p0_ras_n $0\main_sdram_master_p0_ras_n[0:0] - update \main_sdram_master_p0_we_n $0\main_sdram_master_p0_we_n[0:0] - update \main_sdram_master_p0_cke $0\main_sdram_master_p0_cke[0:0] - update \main_sdram_master_p0_odt $0\main_sdram_master_p0_odt[0:0] - update \main_sdram_master_p0_reset_n $0\main_sdram_master_p0_reset_n[0:0] - update \main_sdram_master_p0_act_n $0\main_sdram_master_p0_act_n[0:0] - update \main_sdram_master_p0_wrdata $0\main_sdram_master_p0_wrdata[15:0] - update \main_sdram_master_p0_wrdata_en $0\main_sdram_master_p0_wrdata_en[0:0] - update \main_sdram_master_p0_wrdata_mask $0\main_sdram_master_p0_wrdata_mask[1:0] - update \main_sdram_master_p0_rddata_en $0\main_sdram_master_p0_rddata_en[0:0] - end - attribute \src "ls180.v:307.5-307.38" - process $proc$ls180.v:307$2953 - assign { } { } - assign $1\main_sdram_master_p0_ras_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_ras_n $1\main_sdram_master_p0_ras_n[0:0] - end - attribute \src "ls180.v:308.5-308.37" - process $proc$ls180.v:308$2954 - assign { } { } - assign $1\main_sdram_master_p0_we_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_we_n $1\main_sdram_master_p0_we_n[0:0] - end - attribute \src "ls180.v:309.5-309.36" - process $proc$ls180.v:309$2955 - assign { } { } - assign $1\main_sdram_master_p0_cke[0:0] 1'0 - sync always - sync init - update \main_sdram_master_p0_cke $1\main_sdram_master_p0_cke[0:0] - end - attribute \src "ls180.v:310.5-310.36" - process $proc$ls180.v:310$2956 - assign { } { } - assign $1\main_sdram_master_p0_odt[0:0] 1'0 - sync always - sync init - update \main_sdram_master_p0_odt $1\main_sdram_master_p0_odt[0:0] - end - attribute \src "ls180.v:311.5-311.40" - process $proc$ls180.v:311$2957 - assign { } { } - assign $1\main_sdram_master_p0_reset_n[0:0] 1'0 - sync always - sync init - update \main_sdram_master_p0_reset_n $1\main_sdram_master_p0_reset_n[0:0] - end - attribute \src "ls180.v:3118.1-3134.4" - process $proc$ls180.v:3118$114 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 - attribute \src "ls180.v:3123.2-3133.5" - switch \main_sdram_command_issue_re - attribute \src "ls180.v:3123.6-3123.33" - case 1'1 - assign $0\main_sdram_inti_p0_cs_n[0:0] $not$ls180.v:3124$115_Y - assign $0\main_sdram_inti_p0_we_n[0:0] $not$ls180.v:3125$116_Y - assign $0\main_sdram_inti_p0_cas_n[0:0] $not$ls180.v:3126$117_Y - assign $0\main_sdram_inti_p0_ras_n[0:0] $not$ls180.v:3127$118_Y - attribute \src "ls180.v:3128.6-3128.10" - case - assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 - assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 - end - sync always - update \main_sdram_inti_p0_cas_n $0\main_sdram_inti_p0_cas_n[0:0] - update \main_sdram_inti_p0_cs_n $0\main_sdram_inti_p0_cs_n[0:0] - update \main_sdram_inti_p0_ras_n $0\main_sdram_inti_p0_ras_n[0:0] - update \main_sdram_inti_p0_we_n $0\main_sdram_inti_p0_we_n[0:0] - end - attribute \src "ls180.v:312.5-312.38" - process $proc$ls180.v:312$2958 - assign { } { } - assign $1\main_sdram_master_p0_act_n[0:0] 1'1 - sync always - sync init - update \main_sdram_master_p0_act_n $1\main_sdram_master_p0_act_n[0:0] - end - attribute \src "ls180.v:313.12-313.47" - process $proc$ls180.v:313$2959 - assign { } { } - assign $1\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_master_p0_wrdata $1\main_sdram_master_p0_wrdata[15:0] + update \libresocsim_libresoc_xics_icp_adr $0\libresocsim_libresoc_xics_icp_adr[29:0] + update \libresocsim_libresoc_xics_icp_sel $0\libresocsim_libresoc_xics_icp_sel[3:0] + update \libresocsim_libresoc_xics_icp_cyc $0\libresocsim_libresoc_xics_icp_cyc[0:0] + update \libresocsim_libresoc_xics_icp_stb $0\libresocsim_libresoc_xics_icp_stb[0:0] + update \libresocsim_libresoc_xics_icp_we $0\libresocsim_libresoc_xics_icp_we[0:0] + update \interface0_converted_interface_ack $0\interface0_converted_interface_ack[0:0] + update \converter0_skip $0\converter0_skip[0:0] + update \subfragments_converter0_next_state $0\subfragments_converter0_next_state[0:0] + update \converter0_counter_subfragments_converter0_next_value $0\converter0_counter_subfragments_converter0_next_value[0:0] + update \converter0_counter_subfragments_converter0_next_value_ce $0\converter0_counter_subfragments_converter0_next_value_ce[0:0] end - attribute \src "ls180.v:314.5-314.42" - process $proc$ls180.v:314$2960 + attribute \src "ls180.v:154.11-154.32" + process $proc$ls180.v:154$1664 assign { } { } - assign $1\main_sdram_master_p0_wrdata_en[0:0] 1'0 + assign $1\libresocsim_we[7:0] 8'00000000 sync always sync init - update \main_sdram_master_p0_wrdata_en $1\main_sdram_master_p0_wrdata_en[0:0] + update \libresocsim_we $1\libresocsim_we[7:0] end - attribute \src "ls180.v:315.11-315.50" - process $proc$ls180.v:315$2961 + attribute \src "ls180.v:156.12-156.44" + process $proc$ls180.v:156$1665 assign { } { } - assign $1\main_sdram_master_p0_wrdata_mask[1:0] 2'00 + assign $1\libresocsim_load_storage[31:0] 0 sync always sync init - update \main_sdram_master_p0_wrdata_mask $1\main_sdram_master_p0_wrdata_mask[1:0] + update \libresocsim_load_storage $1\libresocsim_load_storage[31:0] end - attribute \src "ls180.v:316.5-316.42" - process $proc$ls180.v:316$2962 + attribute \src "ls180.v:157.5-157.31" + process $proc$ls180.v:157$1666 assign { } { } - assign $1\main_sdram_master_p0_rddata_en[0:0] 1'0 + assign $1\libresocsim_load_re[0:0] 1'0 sync always sync init - update \main_sdram_master_p0_rddata_en $1\main_sdram_master_p0_rddata_en[0:0] + update \libresocsim_load_re $1\libresocsim_load_re[0:0] end - attribute \src "ls180.v:3177.1-3207.4" - process $proc$ls180.v:3177$127 - assign { } { } - assign { } { } + attribute \src "ls180.v:1574.1-1584.4" + process $proc$ls180.v:1574$36 assign { } { } - assign { } { } - assign $0\main_sdram_cmd_last[0:0] 1'0 - assign $0\main_sdram_sequencer_start0[0:0] 1'0 - assign $0\main_sdram_cmd_valid[0:0] 1'0 - assign { } { } - assign $0\builder_refresher_next_state[1:0] \builder_refresher_state - attribute \src "ls180.v:3183.2-3206.9" - switch \builder_refresher_state - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\main_sdram_cmd_valid[0:0] 1'1 - attribute \src "ls180.v:3186.4-3189.7" - switch \main_sdram_cmd_ready - attribute \src "ls180.v:3186.8-3186.28" - case 1'1 - assign $0\main_sdram_sequencer_start0[0:0] 1'1 - assign $0\builder_refresher_next_state[1:0] 2'10 - case - end + assign $0\libresocsim_libresoc_xics_ics_dat_w[31:0] 0 + attribute \src "ls180.v:1576.2-1583.9" + switch \converter1_counter attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\main_sdram_cmd_valid[0:0] 1'1 - attribute \src "ls180.v:3193.4-3197.7" - switch \main_sdram_sequencer_done0 - attribute \src "ls180.v:3193.8-3193.34" - case 1'1 - assign $0\main_sdram_cmd_valid[0:0] 1'0 - assign $0\main_sdram_cmd_last[0:0] 1'1 - assign $0\builder_refresher_next_state[1:0] 2'00 - case - end + case 1'0 + assign $0\libresocsim_libresoc_xics_ics_dat_w[31:0] \interface1_converted_interface_dat_w [31:0] attribute \src "ls180.v:0.0-0.0" - case - attribute \src "ls180.v:3200.4-3204.7" - switch 1'1 - attribute \src "ls180.v:3200.8-3200.12" - case 1'1 - attribute \src "ls180.v:3201.5-3203.8" - switch \main_sdram_wants_refresh - attribute \src "ls180.v:3201.9-3201.33" - case 1'1 - assign $0\builder_refresher_next_state[1:0] 2'01 - case - end - case - end - end - sync always - update \main_sdram_cmd_valid $0\main_sdram_cmd_valid[0:0] - update \main_sdram_cmd_last $0\main_sdram_cmd_last[0:0] - update \main_sdram_sequencer_start0 $0\main_sdram_sequencer_start0[0:0] - update \builder_refresher_next_state $0\builder_refresher_next_state[1:0] - end - attribute \src "ls180.v:3222.1-3229.4" - process $proc$ls180.v:3222$131 - assign { } { } - assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3224.2-3228.5" - switch \main_sdram_bankmachine0_row_col_n_addr_sel - attribute \src "ls180.v:3224.6-3224.48" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3226.6-3226.10" - case - assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:3227$133_Y - end - sync always - update \main_sdram_bankmachine0_cmd_payload_a $0\main_sdram_bankmachine0_cmd_payload_a[12:0] - end - attribute \src "ls180.v:323.11-323.36" - process $proc$ls180.v:323$2963 - assign { } { } - assign $1\main_sdram_storage[3:0] 4'0001 - sync always - sync init - update \main_sdram_storage $1\main_sdram_storage[3:0] - end - attribute \src "ls180.v:3233.1-3240.4" - process $proc$ls180.v:3233$140 - assign { } { } - assign $0\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3235.2-3239.5" - switch $and$ls180.v:3235$141_Y - attribute \src "ls180.v:3235.6-3235.115" - case 1'1 - attribute \src "ls180.v:3236.3-3238.6" - switch $ne$ls180.v:3236$142_Y - attribute \src "ls180.v:3236.7-3236.143" - case 1'1 - assign $0\main_sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:3237$143_Y - case - end - case - end - sync always - update \main_sdram_bankmachine0_auto_precharge $0\main_sdram_bankmachine0_auto_precharge[0:0] - end - attribute \src "ls180.v:324.5-324.25" - process $proc$ls180.v:324$2964 - assign { } { } - assign $1\main_sdram_re[0:0] 1'0 - sync always - sync init - update \main_sdram_re $1\main_sdram_re[0:0] - end - attribute \src "ls180.v:325.11-325.44" - process $proc$ls180.v:325$2965 - assign { } { } - assign $1\main_sdram_command_storage[5:0] 6'000000 - sync always - sync init - update \main_sdram_command_storage $1\main_sdram_command_storage[5:0] - end - attribute \src "ls180.v:3255.1-3262.4" - process $proc$ls180.v:3255$144 - assign { } { } - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3257.2-3261.5" - switch \main_sdram_bankmachine0_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3257.6-3257.58" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3258$145_Y - attribute \src "ls180.v:3259.6-3259.10" - case - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_produce - end - sync always - update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:326.5-326.33" - process $proc$ls180.v:326$2966 - assign { } { } - assign $1\main_sdram_command_re[0:0] 1'0 - sync always - sync init - update \main_sdram_command_re $1\main_sdram_command_re[0:0] - end - attribute \src "ls180.v:3271.1-3364.4" - process $proc$ls180.v:3271$153 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_bankmachine0_row_close[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 - assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 - assign { } { } - assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 - assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine0_row_open[0:0] 1'0 - assign $0\builder_bankmachine0_next_state[2:0] \builder_bankmachine0_state - attribute \src "ls180.v:3287.2-3363.9" - switch \builder_bankmachine0_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 - attribute \src "ls180.v:3289.4-3297.7" - switch $and$ls180.v:3289$154_Y - attribute \src "ls180.v:3289.8-3289.87" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3291.5-3293.8" - switch \main_sdram_bankmachine0_cmd_ready - attribute \src "ls180.v:3291.9-3291.42" - case 1'1 - assign $0\builder_bankmachine0_next_state[2:0] 3'101 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 - attribute \src "ls180.v:3301.4-3303.7" - switch $and$ls180.v:3301$155_Y - attribute \src "ls180.v:3301.8-3301.87" - case 1'1 - assign $0\builder_bankmachine0_next_state[2:0] 3'101 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - attribute \src "ls180.v:3307.4-3316.7" - switch \main_sdram_bankmachine0_trccon_ready - attribute \src "ls180.v:3307.8-3307.44" - case 1'1 - assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'1 - assign $0\main_sdram_bankmachine0_row_open[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3312.5-3314.8" - switch \main_sdram_bankmachine0_cmd_ready - attribute \src "ls180.v:3312.9-3312.42" - case 1'1 - assign $0\builder_bankmachine0_next_state[2:0] 3'110 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3319.4-3321.7" - switch \main_sdram_bankmachine0_twtpcon_ready - attribute \src "ls180.v:3319.8-3319.45" - case 1'1 - assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'1 - case - end - attribute \src "ls180.v:3324.4-3326.7" - switch $not$ls180.v:3324$156_Y - attribute \src "ls180.v:3324.8-3324.46" - case 1'1 - assign $0\builder_bankmachine0_next_state[2:0] 3'000 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_bankmachine0_next_state[2:0] 3'011 - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_bankmachine0_next_state[2:0] 3'000 - attribute \src "ls180.v:0.0-0.0" + assign $0\libresocsim_libresoc_xics_ics_dat_w[31:0] \interface1_converted_interface_dat_w [63:32] case - attribute \src "ls180.v:3335.4-3361.7" - switch \main_sdram_bankmachine0_refresh_req - attribute \src "ls180.v:3335.8-3335.43" - case 1'1 - assign $0\builder_bankmachine0_next_state[2:0] 3'100 - attribute \src "ls180.v:3337.8-3337.12" - case - attribute \src "ls180.v:3338.5-3360.8" - switch \main_sdram_bankmachine0_cmd_buffer_source_valid - attribute \src "ls180.v:3338.9-3338.56" - case 1'1 - attribute \src "ls180.v:3339.6-3359.9" - switch \main_sdram_bankmachine0_row_opened - attribute \src "ls180.v:3339.10-3339.44" - case 1'1 - attribute \src "ls180.v:3340.7-3356.10" - switch \main_sdram_bankmachine0_row_hit - attribute \src "ls180.v:3340.11-3340.42" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3342.8-3349.11" - switch \main_sdram_bankmachine0_cmd_buffer_source_payload_we - attribute \src "ls180.v:3342.12-3342.64" - case 1'1 - assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] \main_sdram_bankmachine0_cmd_ready - assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'1 - assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3346.12-3346.16" - case - assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] \main_sdram_bankmachine0_cmd_ready - assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'1 - end - attribute \src "ls180.v:3351.8-3353.11" - switch $and$ls180.v:3351$157_Y - attribute \src "ls180.v:3351.12-3351.88" - case 1'1 - assign $0\builder_bankmachine0_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:3354.11-3354.15" - case - assign $0\builder_bankmachine0_next_state[2:0] 3'001 - end - attribute \src "ls180.v:3357.10-3357.14" - case - assign $0\builder_bankmachine0_next_state[2:0] 3'011 - end - case - end - end end sync always - update \main_sdram_bankmachine0_req_wdata_ready $0\main_sdram_bankmachine0_req_wdata_ready[0:0] - update \main_sdram_bankmachine0_req_rdata_valid $0\main_sdram_bankmachine0_req_rdata_valid[0:0] - update \main_sdram_bankmachine0_refresh_gnt $0\main_sdram_bankmachine0_refresh_gnt[0:0] - update \main_sdram_bankmachine0_cmd_valid $0\main_sdram_bankmachine0_cmd_valid[0:0] - update \main_sdram_bankmachine0_cmd_payload_cas $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] - update \main_sdram_bankmachine0_cmd_payload_ras $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] - update \main_sdram_bankmachine0_cmd_payload_we $0\main_sdram_bankmachine0_cmd_payload_we[0:0] - update \main_sdram_bankmachine0_cmd_payload_is_cmd $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] - update \main_sdram_bankmachine0_cmd_payload_is_read $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] - update \main_sdram_bankmachine0_cmd_payload_is_write $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] - update \main_sdram_bankmachine0_row_open $0\main_sdram_bankmachine0_row_open[0:0] - update \main_sdram_bankmachine0_row_close $0\main_sdram_bankmachine0_row_close[0:0] - update \main_sdram_bankmachine0_row_col_n_addr_sel $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] - update \builder_bankmachine0_next_state $0\builder_bankmachine0_next_state[2:0] - end - attribute \src "ls180.v:330.5-330.38" - process $proc$ls180.v:330$2967 - assign { } { } - assign $0\main_sdram_command_issue_w[0:0] 1'0 - sync always - update \main_sdram_command_issue_w $0\main_sdram_command_issue_w[0:0] - sync init - end - attribute \src "ls180.v:331.12-331.46" - process $proc$ls180.v:331$2968 - assign { } { } - assign $1\main_sdram_address_storage[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_address_storage $1\main_sdram_address_storage[12:0] - end - attribute \src "ls180.v:332.5-332.33" - process $proc$ls180.v:332$2969 - assign { } { } - assign $1\main_sdram_address_re[0:0] 1'0 - sync always - sync init - update \main_sdram_address_re $1\main_sdram_address_re[0:0] - end - attribute \src "ls180.v:333.11-333.45" - process $proc$ls180.v:333$2970 - assign { } { } - assign $1\main_sdram_baddress_storage[1:0] 2'00 - sync always - sync init - update \main_sdram_baddress_storage $1\main_sdram_baddress_storage[1:0] - end - attribute \src "ls180.v:334.5-334.34" - process $proc$ls180.v:334$2971 - assign { } { } - assign $1\main_sdram_baddress_re[0:0] 1'0 - sync always - sync init - update \main_sdram_baddress_re $1\main_sdram_baddress_re[0:0] - end - attribute \src "ls180.v:335.12-335.45" - process $proc$ls180.v:335$2972 - assign { } { } - assign $1\main_sdram_wrdata_storage[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_wrdata_storage $1\main_sdram_wrdata_storage[15:0] - end - attribute \src "ls180.v:336.5-336.32" - process $proc$ls180.v:336$2973 - assign { } { } - assign $1\main_sdram_wrdata_re[0:0] 1'0 - sync always - sync init - update \main_sdram_wrdata_re $1\main_sdram_wrdata_re[0:0] + update \libresocsim_libresoc_xics_ics_dat_w $0\libresocsim_libresoc_xics_ics_dat_w[31:0] end - attribute \src "ls180.v:337.12-337.37" - process $proc$ls180.v:337$2974 + attribute \src "ls180.v:158.12-158.46" + process $proc$ls180.v:158$1667 assign { } { } - assign $1\main_sdram_status[15:0] 16'0000000000000000 + assign $1\libresocsim_reload_storage[31:0] 0 sync always sync init - update \main_sdram_status $1\main_sdram_status[15:0] - end - attribute \src "ls180.v:3379.1-3386.4" - process $proc$ls180.v:3379$161 - assign { } { } - assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3381.2-3385.5" - switch \main_sdram_bankmachine1_row_col_n_addr_sel - attribute \src "ls180.v:3381.6-3381.48" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3383.6-3383.10" - case - assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:3384$163_Y - end - sync always - update \main_sdram_bankmachine1_cmd_payload_a $0\main_sdram_bankmachine1_cmd_payload_a[12:0] - end - attribute \src "ls180.v:3390.1-3397.4" - process $proc$ls180.v:3390$170 - assign { } { } - assign $0\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3392.2-3396.5" - switch $and$ls180.v:3392$171_Y - attribute \src "ls180.v:3392.6-3392.115" - case 1'1 - attribute \src "ls180.v:3393.3-3395.6" - switch $ne$ls180.v:3393$172_Y - attribute \src "ls180.v:3393.7-3393.143" - case 1'1 - assign $0\main_sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:3394$173_Y - case - end - case - end - sync always - update \main_sdram_bankmachine1_auto_precharge $0\main_sdram_bankmachine1_auto_precharge[0:0] - end - attribute \src "ls180.v:3412.1-3419.4" - process $proc$ls180.v:3412$174 - assign { } { } - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3414.2-3418.5" - switch \main_sdram_bankmachine1_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3414.6-3414.58" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3415$175_Y - attribute \src "ls180.v:3416.6-3416.10" - case - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_produce - end - sync always - update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + update \libresocsim_reload_storage $1\libresocsim_reload_storage[31:0] end - attribute \src "ls180.v:3428.1-3521.4" - process $proc$ls180.v:3428$183 - assign { } { } + attribute \src "ls180.v:1586.1-1632.4" + process $proc$ls180.v:1586$37 assign { } { } assign { } { } assign { } { } @@ -288833,1192 +263415,149 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\libresocsim_libresoc_xics_ics_adr[29:0] 30'000000000000000000000000000000 + assign $0\libresocsim_libresoc_xics_ics_sel[3:0] 4'0000 + assign $0\libresocsim_libresoc_xics_ics_cyc[0:0] 1'0 + assign $0\libresocsim_libresoc_xics_ics_stb[0:0] 1'0 + assign $0\interface1_converted_interface_ack[0:0] 1'0 + assign $0\libresocsim_libresoc_xics_ics_we[0:0] 1'0 + assign $0\converter1_skip[0:0] 1'0 assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_bankmachine1_row_open[0:0] 1'0 - assign { } { } - assign $0\main_sdram_bankmachine1_row_close[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 - assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 - assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 - assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 - assign $0\builder_bankmachine1_next_state[2:0] \builder_bankmachine1_state - attribute \src "ls180.v:3444.2-3520.9" - switch \builder_bankmachine1_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 - attribute \src "ls180.v:3446.4-3454.7" - switch $and$ls180.v:3446$184_Y - attribute \src "ls180.v:3446.8-3446.87" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3448.5-3450.8" - switch \main_sdram_bankmachine1_cmd_ready - attribute \src "ls180.v:3448.9-3448.42" - case 1'1 - assign $0\builder_bankmachine1_next_state[2:0] 3'101 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 - attribute \src "ls180.v:3458.4-3460.7" - switch $and$ls180.v:3458$185_Y - attribute \src "ls180.v:3458.8-3458.87" - case 1'1 - assign $0\builder_bankmachine1_next_state[2:0] 3'101 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - attribute \src "ls180.v:3464.4-3473.7" - switch \main_sdram_bankmachine1_trccon_ready - attribute \src "ls180.v:3464.8-3464.44" - case 1'1 - assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'1 - assign $0\main_sdram_bankmachine1_row_open[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3469.5-3471.8" - switch \main_sdram_bankmachine1_cmd_ready - attribute \src "ls180.v:3469.9-3469.42" - case 1'1 - assign $0\builder_bankmachine1_next_state[2:0] 3'110 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3476.4-3478.7" - switch \main_sdram_bankmachine1_twtpcon_ready - attribute \src "ls180.v:3476.8-3476.45" - case 1'1 - assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'1 - case - end - attribute \src "ls180.v:3481.4-3483.7" - switch $not$ls180.v:3481$186_Y - attribute \src "ls180.v:3481.8-3481.46" - case 1'1 - assign $0\builder_bankmachine1_next_state[2:0] 3'000 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_bankmachine1_next_state[2:0] 3'011 - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_bankmachine1_next_state[2:0] 3'000 + assign $0\converter1_counter_subfragments_converter1_next_value[0:0] 1'0 + assign $0\converter1_counter_subfragments_converter1_next_value_ce[0:0] 1'0 + assign $0\subfragments_converter1_next_state[0:0] \subfragments_converter1_state + attribute \src "ls180.v:1598.2-1631.9" + switch \subfragments_converter1_state attribute \src "ls180.v:0.0-0.0" - case - attribute \src "ls180.v:3492.4-3518.7" - switch \main_sdram_bankmachine1_refresh_req - attribute \src "ls180.v:3492.8-3492.43" - case 1'1 - assign $0\builder_bankmachine1_next_state[2:0] 3'100 - attribute \src "ls180.v:3494.8-3494.12" - case - attribute \src "ls180.v:3495.5-3517.8" - switch \main_sdram_bankmachine1_cmd_buffer_source_valid - attribute \src "ls180.v:3495.9-3495.56" - case 1'1 - attribute \src "ls180.v:3496.6-3516.9" - switch \main_sdram_bankmachine1_row_opened - attribute \src "ls180.v:3496.10-3496.44" - case 1'1 - attribute \src "ls180.v:3497.7-3513.10" - switch \main_sdram_bankmachine1_row_hit - attribute \src "ls180.v:3497.11-3497.42" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3499.8-3506.11" - switch \main_sdram_bankmachine1_cmd_buffer_source_payload_we - attribute \src "ls180.v:3499.12-3499.64" - case 1'1 - assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] \main_sdram_bankmachine1_cmd_ready - assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'1 - assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3503.12-3503.16" - case - assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] \main_sdram_bankmachine1_cmd_ready - assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'1 - end - attribute \src "ls180.v:3508.8-3510.11" - switch $and$ls180.v:3508$187_Y - attribute \src "ls180.v:3508.12-3508.88" - case 1'1 - assign $0\builder_bankmachine1_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:3511.11-3511.15" - case - assign $0\builder_bankmachine1_next_state[2:0] 3'001 - end - attribute \src "ls180.v:3514.10-3514.14" - case - assign $0\builder_bankmachine1_next_state[2:0] 3'011 - end - case - end - end - end - sync always - update \main_sdram_bankmachine1_req_wdata_ready $0\main_sdram_bankmachine1_req_wdata_ready[0:0] - update \main_sdram_bankmachine1_req_rdata_valid $0\main_sdram_bankmachine1_req_rdata_valid[0:0] - update \main_sdram_bankmachine1_refresh_gnt $0\main_sdram_bankmachine1_refresh_gnt[0:0] - update \main_sdram_bankmachine1_cmd_valid $0\main_sdram_bankmachine1_cmd_valid[0:0] - update \main_sdram_bankmachine1_cmd_payload_cas $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] - update \main_sdram_bankmachine1_cmd_payload_ras $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] - update \main_sdram_bankmachine1_cmd_payload_we $0\main_sdram_bankmachine1_cmd_payload_we[0:0] - update \main_sdram_bankmachine1_cmd_payload_is_cmd $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] - update \main_sdram_bankmachine1_cmd_payload_is_read $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] - update \main_sdram_bankmachine1_cmd_payload_is_write $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] - update \main_sdram_bankmachine1_row_open $0\main_sdram_bankmachine1_row_open[0:0] - update \main_sdram_bankmachine1_row_close $0\main_sdram_bankmachine1_row_close[0:0] - update \main_sdram_bankmachine1_row_col_n_addr_sel $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] - update \builder_bankmachine1_next_state $0\builder_bankmachine1_next_state[2:0] - end - attribute \src "ls180.v:3536.1-3543.4" - process $proc$ls180.v:3536$191 - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3538.2-3542.5" - switch \main_sdram_bankmachine2_row_col_n_addr_sel - attribute \src "ls180.v:3538.6-3538.48" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3540.6-3540.10" - case - assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:3541$193_Y - end - sync always - update \main_sdram_bankmachine2_cmd_payload_a $0\main_sdram_bankmachine2_cmd_payload_a[12:0] - end - attribute \src "ls180.v:3547.1-3554.4" - process $proc$ls180.v:3547$200 - assign { } { } - assign $0\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3549.2-3553.5" - switch $and$ls180.v:3549$201_Y - attribute \src "ls180.v:3549.6-3549.115" - case 1'1 - attribute \src "ls180.v:3550.3-3552.6" - switch $ne$ls180.v:3550$202_Y - attribute \src "ls180.v:3550.7-3550.143" - case 1'1 - assign $0\main_sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:3551$203_Y - case - end - case - end - sync always - update \main_sdram_bankmachine2_auto_precharge $0\main_sdram_bankmachine2_auto_precharge[0:0] - end - attribute \src "ls180.v:3569.1-3576.4" - process $proc$ls180.v:3569$204 - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3571.2-3575.5" - switch \main_sdram_bankmachine2_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3571.6-3571.58" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3572$205_Y - attribute \src "ls180.v:3573.6-3573.10" - case - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_produce - end - sync always - update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:3585.1-3678.4" - process $proc$ls180.v:3585$213 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 - assign { } { } - assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 - assign $0\main_sdram_bankmachine2_row_open[0:0] 1'0 - assign $0\main_sdram_bankmachine2_row_close[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 - assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 - assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 - assign $0\builder_bankmachine2_next_state[2:0] \builder_bankmachine2_state - attribute \src "ls180.v:3601.2-3677.9" - switch \builder_bankmachine2_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 - attribute \src "ls180.v:3603.4-3611.7" - switch $and$ls180.v:3603$214_Y - attribute \src "ls180.v:3603.8-3603.87" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3605.5-3607.8" - switch \main_sdram_bankmachine2_cmd_ready - attribute \src "ls180.v:3605.9-3605.42" - case 1'1 - assign $0\builder_bankmachine2_next_state[2:0] 3'101 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 - attribute \src "ls180.v:3615.4-3617.7" - switch $and$ls180.v:3615$215_Y - attribute \src "ls180.v:3615.8-3615.87" - case 1'1 - assign $0\builder_bankmachine2_next_state[2:0] 3'101 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - attribute \src "ls180.v:3621.4-3630.7" - switch \main_sdram_bankmachine2_trccon_ready - attribute \src "ls180.v:3621.8-3621.44" - case 1'1 - assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'1 - assign $0\main_sdram_bankmachine2_row_open[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3626.5-3628.8" - switch \main_sdram_bankmachine2_cmd_ready - attribute \src "ls180.v:3626.9-3626.42" - case 1'1 - assign $0\builder_bankmachine2_next_state[2:0] 3'110 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3633.4-3635.7" - switch \main_sdram_bankmachine2_twtpcon_ready - attribute \src "ls180.v:3633.8-3633.45" - case 1'1 - assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'1 - case - end - attribute \src "ls180.v:3638.4-3640.7" - switch $not$ls180.v:3638$216_Y - attribute \src "ls180.v:3638.8-3638.46" + assign $0\libresocsim_libresoc_xics_ics_adr[29:0] { \interface1_converted_interface_adr [28:0] \converter1_counter } + attribute \src "ls180.v:1601.4-1608.11" + switch \converter1_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\libresocsim_libresoc_xics_ics_sel[3:0] \interface1_converted_interface_sel [3:0] + attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\builder_bankmachine2_next_state[2:0] 3'000 + assign $0\libresocsim_libresoc_xics_ics_sel[3:0] \interface1_converted_interface_sel [7:4] case end - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_bankmachine2_next_state[2:0] 3'011 - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_bankmachine2_next_state[2:0] 3'000 - attribute \src "ls180.v:0.0-0.0" - case - attribute \src "ls180.v:3649.4-3675.7" - switch \main_sdram_bankmachine2_refresh_req - attribute \src "ls180.v:3649.8-3649.43" + attribute \src "ls180.v:1609.4-1622.7" + switch $and$ls180.v:1609$38_Y + attribute \src "ls180.v:1609.8-1609.81" case 1'1 - assign $0\builder_bankmachine2_next_state[2:0] 3'100 - attribute \src "ls180.v:3651.8-3651.12" - case - attribute \src "ls180.v:3652.5-3674.8" - switch \main_sdram_bankmachine2_cmd_buffer_source_valid - attribute \src "ls180.v:3652.9-3652.56" + assign $0\converter1_skip[0:0] $eq$ls180.v:1610$39_Y + assign $0\libresocsim_libresoc_xics_ics_we[0:0] \interface1_converted_interface_we + assign $0\libresocsim_libresoc_xics_ics_cyc[0:0] $not$ls180.v:1612$40_Y + assign $0\libresocsim_libresoc_xics_ics_stb[0:0] $not$ls180.v:1613$41_Y + attribute \src "ls180.v:1614.5-1621.8" + switch $or$ls180.v:1614$42_Y + attribute \src "ls180.v:1614.9-1614.62" case 1'1 - attribute \src "ls180.v:3653.6-3673.9" - switch \main_sdram_bankmachine2_row_opened - attribute \src "ls180.v:3653.10-3653.44" + assign $0\converter1_counter_subfragments_converter1_next_value[0:0] $add$ls180.v:1615$43_Y + assign $0\converter1_counter_subfragments_converter1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:1617.6-1620.9" + switch $eq$ls180.v:1617$44_Y + attribute \src "ls180.v:1617.10-1617.38" case 1'1 - attribute \src "ls180.v:3654.7-3670.10" - switch \main_sdram_bankmachine2_row_hit - attribute \src "ls180.v:3654.11-3654.42" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3656.8-3663.11" - switch \main_sdram_bankmachine2_cmd_buffer_source_payload_we - attribute \src "ls180.v:3656.12-3656.64" - case 1'1 - assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] \main_sdram_bankmachine2_cmd_ready - assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'1 - assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3660.12-3660.16" - case - assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] \main_sdram_bankmachine2_cmd_ready - assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'1 - end - attribute \src "ls180.v:3665.8-3667.11" - switch $and$ls180.v:3665$217_Y - attribute \src "ls180.v:3665.12-3665.88" - case 1'1 - assign $0\builder_bankmachine2_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:3668.11-3668.15" - case - assign $0\builder_bankmachine2_next_state[2:0] 3'001 - end - attribute \src "ls180.v:3671.10-3671.14" + assign $0\interface1_converted_interface_ack[0:0] 1'1 + assign $0\subfragments_converter1_next_state[0:0] 1'0 case - assign $0\builder_bankmachine2_next_state[2:0] 3'011 end case end - end - end - sync always - update \main_sdram_bankmachine2_req_wdata_ready $0\main_sdram_bankmachine2_req_wdata_ready[0:0] - update \main_sdram_bankmachine2_req_rdata_valid $0\main_sdram_bankmachine2_req_rdata_valid[0:0] - update \main_sdram_bankmachine2_refresh_gnt $0\main_sdram_bankmachine2_refresh_gnt[0:0] - update \main_sdram_bankmachine2_cmd_valid $0\main_sdram_bankmachine2_cmd_valid[0:0] - update \main_sdram_bankmachine2_cmd_payload_cas $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] - update \main_sdram_bankmachine2_cmd_payload_ras $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] - update \main_sdram_bankmachine2_cmd_payload_we $0\main_sdram_bankmachine2_cmd_payload_we[0:0] - update \main_sdram_bankmachine2_cmd_payload_is_cmd $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] - update \main_sdram_bankmachine2_cmd_payload_is_read $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] - update \main_sdram_bankmachine2_cmd_payload_is_write $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] - update \main_sdram_bankmachine2_row_open $0\main_sdram_bankmachine2_row_open[0:0] - update \main_sdram_bankmachine2_row_close $0\main_sdram_bankmachine2_row_close[0:0] - update \main_sdram_bankmachine2_row_col_n_addr_sel $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] - update \builder_bankmachine2_next_state $0\builder_bankmachine2_next_state[2:0] - end - attribute \src "ls180.v:367.12-367.46" - process $proc$ls180.v:367$2975 - assign { } { } - assign $1\main_sdram_interface_wdata[15:0] 16'0000000000000000 - sync always - sync init - update \main_sdram_interface_wdata $1\main_sdram_interface_wdata[15:0] - end - attribute \src "ls180.v:368.11-368.47" - process $proc$ls180.v:368$2976 - assign { } { } - assign $1\main_sdram_interface_wdata_we[1:0] 2'00 - sync always - sync init - update \main_sdram_interface_wdata_we $1\main_sdram_interface_wdata_we[1:0] - end - attribute \src "ls180.v:3693.1-3700.4" - process $proc$ls180.v:3693$221 - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 - attribute \src "ls180.v:3695.2-3699.5" - switch \main_sdram_bankmachine3_row_col_n_addr_sel - attribute \src "ls180.v:3695.6-3695.48" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] - attribute \src "ls180.v:3697.6-3697.10" - case - assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:3698$223_Y - end - sync always - update \main_sdram_bankmachine3_cmd_payload_a $0\main_sdram_bankmachine3_cmd_payload_a[12:0] - end - attribute \src "ls180.v:370.12-370.45" - process $proc$ls180.v:370$2977 - assign { } { } - assign $1\main_sdram_dfi_p0_address[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_dfi_p0_address $1\main_sdram_dfi_p0_address[12:0] - end - attribute \src "ls180.v:3704.1-3711.4" - process $proc$ls180.v:3704$230 - assign { } { } - assign $0\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 - attribute \src "ls180.v:3706.2-3710.5" - switch $and$ls180.v:3706$231_Y - attribute \src "ls180.v:3706.6-3706.115" - case 1'1 - attribute \src "ls180.v:3707.3-3709.6" - switch $ne$ls180.v:3707$232_Y - attribute \src "ls180.v:3707.7-3707.143" - case 1'1 - assign $0\main_sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:3708$233_Y - case - end - case - end - sync always - update \main_sdram_bankmachine3_auto_precharge $0\main_sdram_bankmachine3_auto_precharge[0:0] - end - attribute \src "ls180.v:371.11-371.40" - process $proc$ls180.v:371$2978 - assign { } { } - assign $1\main_sdram_dfi_p0_bank[1:0] 2'00 - sync always - sync init - update \main_sdram_dfi_p0_bank $1\main_sdram_dfi_p0_bank[1:0] - end - attribute \src "ls180.v:372.5-372.35" - process $proc$ls180.v:372$2979 - assign { } { } - assign $1\main_sdram_dfi_p0_cas_n[0:0] 1'1 - sync always - sync init - update \main_sdram_dfi_p0_cas_n $1\main_sdram_dfi_p0_cas_n[0:0] - end - attribute \src "ls180.v:3726.1-3733.4" - process $proc$ls180.v:3726$234 - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - attribute \src "ls180.v:3728.2-3732.5" - switch \main_sdram_bankmachine3_cmd_buffer_lookahead_replace - attribute \src "ls180.v:3728.6-3728.58" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:3729$235_Y - attribute \src "ls180.v:3730.6-3730.10" - case - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_produce - end - sync always - update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:373.5-373.34" - process $proc$ls180.v:373$2980 - assign { } { } - assign $1\main_sdram_dfi_p0_cs_n[0:0] 1'1 - sync always - sync init - update \main_sdram_dfi_p0_cs_n $1\main_sdram_dfi_p0_cs_n[0:0] - end - attribute \src "ls180.v:374.5-374.35" - process $proc$ls180.v:374$2981 - assign { } { } - assign $1\main_sdram_dfi_p0_ras_n[0:0] 1'1 - sync always - sync init - update \main_sdram_dfi_p0_ras_n $1\main_sdram_dfi_p0_ras_n[0:0] - end - attribute \src "ls180.v:3742.1-3835.4" - process $proc$ls180.v:3742$243 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 - assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 - assign { } { } - assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 - assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine3_row_open[0:0] 1'0 - assign $0\main_sdram_bankmachine3_row_close[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 - assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 - assign $0\builder_bankmachine3_next_state[2:0] \builder_bankmachine3_state - attribute \src "ls180.v:3758.2-3834.9" - switch \builder_bankmachine3_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 - attribute \src "ls180.v:3760.4-3768.7" - switch $and$ls180.v:3760$244_Y - attribute \src "ls180.v:3760.8-3760.87" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3762.5-3764.8" - switch \main_sdram_bankmachine3_cmd_ready - attribute \src "ls180.v:3762.9-3762.42" - case 1'1 - assign $0\builder_bankmachine3_next_state[2:0] 3'101 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 - attribute \src "ls180.v:3772.4-3774.7" - switch $and$ls180.v:3772$245_Y - attribute \src "ls180.v:3772.8-3772.87" - case 1'1 - assign $0\builder_bankmachine3_next_state[2:0] 3'101 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - attribute \src "ls180.v:3778.4-3787.7" - switch \main_sdram_bankmachine3_trccon_ready - attribute \src "ls180.v:3778.8-3778.44" - case 1'1 - assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'1 - assign $0\main_sdram_bankmachine3_row_open[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 - attribute \src "ls180.v:3783.5-3785.8" - switch \main_sdram_bankmachine3_cmd_ready - attribute \src "ls180.v:3783.9-3783.42" - case 1'1 - assign $0\builder_bankmachine3_next_state[2:0] 3'110 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 - attribute \src "ls180.v:3790.4-3792.7" - switch \main_sdram_bankmachine3_twtpcon_ready - attribute \src "ls180.v:3790.8-3790.45" - case 1'1 - assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'1 - case - end - attribute \src "ls180.v:3795.4-3797.7" - switch $not$ls180.v:3795$246_Y - attribute \src "ls180.v:3795.8-3795.46" - case 1'1 - assign $0\builder_bankmachine3_next_state[2:0] 3'000 case end attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_bankmachine3_next_state[2:0] 3'011 - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_bankmachine3_next_state[2:0] 3'000 - attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:3806.4-3832.7" - switch \main_sdram_bankmachine3_refresh_req - attribute \src "ls180.v:3806.8-3806.43" + assign $0\converter1_counter_subfragments_converter1_next_value[0:0] 1'0 + assign $0\converter1_counter_subfragments_converter1_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:1627.4-1629.7" + switch $and$ls180.v:1627$45_Y + attribute \src "ls180.v:1627.8-1627.81" case 1'1 - assign $0\builder_bankmachine3_next_state[2:0] 3'100 - attribute \src "ls180.v:3808.8-3808.12" + assign $0\subfragments_converter1_next_state[0:0] 1'1 case - attribute \src "ls180.v:3809.5-3831.8" - switch \main_sdram_bankmachine3_cmd_buffer_source_valid - attribute \src "ls180.v:3809.9-3809.56" - case 1'1 - attribute \src "ls180.v:3810.6-3830.9" - switch \main_sdram_bankmachine3_row_opened - attribute \src "ls180.v:3810.10-3810.44" - case 1'1 - attribute \src "ls180.v:3811.7-3827.10" - switch \main_sdram_bankmachine3_row_hit - attribute \src "ls180.v:3811.11-3811.42" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'1 - attribute \src "ls180.v:3813.8-3820.11" - switch \main_sdram_bankmachine3_cmd_buffer_source_payload_we - attribute \src "ls180.v:3813.12-3813.64" - case 1'1 - assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] \main_sdram_bankmachine3_cmd_ready - assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'1 - assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 - attribute \src "ls180.v:3817.12-3817.16" - case - assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] \main_sdram_bankmachine3_cmd_ready - assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'1 - end - attribute \src "ls180.v:3822.8-3824.11" - switch $and$ls180.v:3822$247_Y - attribute \src "ls180.v:3822.12-3822.88" - case 1'1 - assign $0\builder_bankmachine3_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:3825.11-3825.15" - case - assign $0\builder_bankmachine3_next_state[2:0] 3'001 - end - attribute \src "ls180.v:3828.10-3828.14" - case - assign $0\builder_bankmachine3_next_state[2:0] 3'011 - end - case - end end end sync always - update \main_sdram_bankmachine3_req_wdata_ready $0\main_sdram_bankmachine3_req_wdata_ready[0:0] - update \main_sdram_bankmachine3_req_rdata_valid $0\main_sdram_bankmachine3_req_rdata_valid[0:0] - update \main_sdram_bankmachine3_refresh_gnt $0\main_sdram_bankmachine3_refresh_gnt[0:0] - update \main_sdram_bankmachine3_cmd_valid $0\main_sdram_bankmachine3_cmd_valid[0:0] - update \main_sdram_bankmachine3_cmd_payload_cas $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] - update \main_sdram_bankmachine3_cmd_payload_ras $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] - update \main_sdram_bankmachine3_cmd_payload_we $0\main_sdram_bankmachine3_cmd_payload_we[0:0] - update \main_sdram_bankmachine3_cmd_payload_is_cmd $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] - update \main_sdram_bankmachine3_cmd_payload_is_read $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] - update \main_sdram_bankmachine3_cmd_payload_is_write $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] - update \main_sdram_bankmachine3_row_open $0\main_sdram_bankmachine3_row_open[0:0] - update \main_sdram_bankmachine3_row_close $0\main_sdram_bankmachine3_row_close[0:0] - update \main_sdram_bankmachine3_row_col_n_addr_sel $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] - update \builder_bankmachine3_next_state $0\builder_bankmachine3_next_state[2:0] - end - attribute \src "ls180.v:375.5-375.34" - process $proc$ls180.v:375$2982 - assign { } { } - assign $1\main_sdram_dfi_p0_we_n[0:0] 1'1 - sync always - sync init - update \main_sdram_dfi_p0_we_n $1\main_sdram_dfi_p0_we_n[0:0] - end - attribute \src "ls180.v:379.5-379.35" - process $proc$ls180.v:379$2983 - assign { } { } - assign $0\main_sdram_dfi_p0_act_n[0:0] 1'1 - sync always - update \main_sdram_dfi_p0_act_n $0\main_sdram_dfi_p0_act_n[0:0] - sync init - end - attribute \src "ls180.v:381.5-381.39" - process $proc$ls180.v:381$2984 - assign { } { } - assign $1\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 - sync always - sync init - update \main_sdram_dfi_p0_wrdata_en $1\main_sdram_dfi_p0_wrdata_en[0:0] - end - attribute \src "ls180.v:383.5-383.39" - process $proc$ls180.v:383$2985 - assign { } { } - assign $1\main_sdram_dfi_p0_rddata_en[0:0] 1'0 - sync always - sync init - update \main_sdram_dfi_p0_rddata_en $1\main_sdram_dfi_p0_rddata_en[0:0] - end - attribute \src "ls180.v:3855.1-3861.4" - process $proc$ls180.v:3855$286 - assign { } { } - assign { } { } - assign $0\main_sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:3857$299_Y - assign $0\main_sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:3858$312_Y - assign $0\main_sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:3859$325_Y - assign $0\main_sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:3860$338_Y - sync always - update \main_sdram_choose_cmd_valids $0\main_sdram_choose_cmd_valids[3:0] - end - attribute \src "ls180.v:386.5-386.32" - process $proc$ls180.v:386$2986 - assign { } { } - assign $1\main_sdram_cmd_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_valid $1\main_sdram_cmd_valid[0:0] - end - attribute \src "ls180.v:3869.1-3874.4" - process $proc$ls180.v:3869$339 - assign { } { } - assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 - attribute \src "ls180.v:3871.2-3873.5" - switch \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:3871.6-3871.37" - case 1'1 - assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] \builder_comb_t_array_muxed0 - case - end - sync always - update \main_sdram_choose_cmd_cmd_payload_cas $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:387.5-387.32" - process $proc$ls180.v:387$2987 - assign { } { } - assign $1\main_sdram_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_ready $1\main_sdram_cmd_ready[0:0] - end - attribute \src "ls180.v:3875.1-3880.4" - process $proc$ls180.v:3875$340 - assign { } { } - assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 - attribute \src "ls180.v:3877.2-3879.5" - switch \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:3877.6-3877.37" - case 1'1 - assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] \builder_comb_t_array_muxed1 - case - end - sync always - update \main_sdram_choose_cmd_cmd_payload_ras $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:388.5-388.31" - process $proc$ls180.v:388$2988 - assign { } { } - assign $1\main_sdram_cmd_last[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_last $1\main_sdram_cmd_last[0:0] - end - attribute \src "ls180.v:3881.1-3886.4" - process $proc$ls180.v:3881$341 - assign { } { } - assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 - attribute \src "ls180.v:3883.2-3885.5" - switch \main_sdram_choose_cmd_cmd_valid - attribute \src "ls180.v:3883.6-3883.37" - case 1'1 - assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] \builder_comb_t_array_muxed2 - case - end - sync always - update \main_sdram_choose_cmd_cmd_payload_we $0\main_sdram_choose_cmd_cmd_payload_we[0:0] - end - attribute \src "ls180.v:3888.1-3894.4" - process $proc$ls180.v:3888$344 - assign { } { } - assign { } { } - assign $0\main_sdram_choose_req_valids[3:0] [0] $and$ls180.v:3890$357_Y - assign $0\main_sdram_choose_req_valids[3:0] [1] $and$ls180.v:3891$370_Y - assign $0\main_sdram_choose_req_valids[3:0] [2] $and$ls180.v:3892$383_Y - assign $0\main_sdram_choose_req_valids[3:0] [3] $and$ls180.v:3893$396_Y - sync always - update \main_sdram_choose_req_valids $0\main_sdram_choose_req_valids[3:0] - end - attribute \src "ls180.v:389.12-389.44" - process $proc$ls180.v:389$2989 - assign { } { } - assign $1\main_sdram_cmd_payload_a[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_cmd_payload_a $1\main_sdram_cmd_payload_a[12:0] - end - attribute \src "ls180.v:390.11-390.43" - process $proc$ls180.v:390$2990 - assign { } { } - assign $1\main_sdram_cmd_payload_ba[1:0] 2'00 - sync always - sync init - update \main_sdram_cmd_payload_ba $1\main_sdram_cmd_payload_ba[1:0] - end - attribute \src "ls180.v:3902.1-3907.4" - process $proc$ls180.v:3902$397 - assign { } { } - assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 - attribute \src "ls180.v:3904.2-3906.5" - switch \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:3904.6-3904.37" - case 1'1 - assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] \builder_comb_t_array_muxed3 - case - end - sync always - update \main_sdram_choose_req_cmd_payload_cas $0\main_sdram_choose_req_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:3908.1-3913.4" - process $proc$ls180.v:3908$398 - assign { } { } - assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 - attribute \src "ls180.v:3910.2-3912.5" - switch \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:3910.6-3910.37" - case 1'1 - assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] \builder_comb_t_array_muxed4 - case - end - sync always - update \main_sdram_choose_req_cmd_payload_ras $0\main_sdram_choose_req_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:391.5-391.38" - process $proc$ls180.v:391$2991 - assign { } { } - assign $1\main_sdram_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_payload_cas $1\main_sdram_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:3914.1-3919.4" - process $proc$ls180.v:3914$399 - assign { } { } - assign $0\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 - attribute \src "ls180.v:3916.2-3918.5" - switch \main_sdram_choose_req_cmd_valid - attribute \src "ls180.v:3916.6-3916.37" - case 1'1 - assign $0\main_sdram_choose_req_cmd_payload_we[0:0] \builder_comb_t_array_muxed5 - case - end - sync always - update \main_sdram_choose_req_cmd_payload_we $0\main_sdram_choose_req_cmd_payload_we[0:0] - end - attribute \src "ls180.v:392.5-392.38" - process $proc$ls180.v:392$2992 - assign { } { } - assign $1\main_sdram_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_payload_ras $1\main_sdram_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:3920.1-3928.4" - process $proc$ls180.v:3920$400 - assign { } { } - assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:3922.2-3924.5" - switch $and$ls180.v:3922$403_Y - attribute \src "ls180.v:3922.6-3922.115" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 - case - end - attribute \src "ls180.v:3925.2-3927.5" - switch $and$ls180.v:3925$406_Y - attribute \src "ls180.v:3925.6-3925.115" - case 1'1 - assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 - case - end - sync always - update \main_sdram_bankmachine0_cmd_ready $0\main_sdram_bankmachine0_cmd_ready[0:0] - end - attribute \src "ls180.v:3929.1-3937.4" - process $proc$ls180.v:3929$407 - assign { } { } - assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:3931.2-3933.5" - switch $and$ls180.v:3931$410_Y - attribute \src "ls180.v:3931.6-3931.115" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 - case - end - attribute \src "ls180.v:3934.2-3936.5" - switch $and$ls180.v:3934$413_Y - attribute \src "ls180.v:3934.6-3934.115" - case 1'1 - assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 - case - end - sync always - update \main_sdram_bankmachine1_cmd_ready $0\main_sdram_bankmachine1_cmd_ready[0:0] - end - attribute \src "ls180.v:393.5-393.37" - process $proc$ls180.v:393$2993 - assign { } { } - assign $1\main_sdram_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_cmd_payload_we $1\main_sdram_cmd_payload_we[0:0] - end - attribute \src "ls180.v:3938.1-3946.4" - process $proc$ls180.v:3938$414 - assign { } { } - assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:3940.2-3942.5" - switch $and$ls180.v:3940$417_Y - attribute \src "ls180.v:3940.6-3940.115" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 - case - end - attribute \src "ls180.v:3943.2-3945.5" - switch $and$ls180.v:3943$420_Y - attribute \src "ls180.v:3943.6-3943.115" - case 1'1 - assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 - case - end - sync always - update \main_sdram_bankmachine2_cmd_ready $0\main_sdram_bankmachine2_cmd_ready[0:0] - end - attribute \src "ls180.v:394.5-394.42" - process $proc$ls180.v:394$2994 - assign { } { } - assign $0\main_sdram_cmd_payload_is_read[0:0] 1'0 - sync always - update \main_sdram_cmd_payload_is_read $0\main_sdram_cmd_payload_is_read[0:0] - sync init - end - attribute \src "ls180.v:3947.1-3955.4" - process $proc$ls180.v:3947$421 - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 - attribute \src "ls180.v:3949.2-3951.5" - switch $and$ls180.v:3949$424_Y - attribute \src "ls180.v:3949.6-3949.115" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 - case - end - attribute \src "ls180.v:3952.2-3954.5" - switch $and$ls180.v:3952$427_Y - attribute \src "ls180.v:3952.6-3952.115" - case 1'1 - assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 - case - end - sync always - update \main_sdram_bankmachine3_cmd_ready $0\main_sdram_bankmachine3_cmd_ready[0:0] + update \libresocsim_libresoc_xics_ics_adr $0\libresocsim_libresoc_xics_ics_adr[29:0] + update \libresocsim_libresoc_xics_ics_sel $0\libresocsim_libresoc_xics_ics_sel[3:0] + update \libresocsim_libresoc_xics_ics_cyc $0\libresocsim_libresoc_xics_ics_cyc[0:0] + update \libresocsim_libresoc_xics_ics_stb $0\libresocsim_libresoc_xics_ics_stb[0:0] + update \libresocsim_libresoc_xics_ics_we $0\libresocsim_libresoc_xics_ics_we[0:0] + update \interface1_converted_interface_ack $0\interface1_converted_interface_ack[0:0] + update \converter1_skip $0\converter1_skip[0:0] + update \subfragments_converter1_next_state $0\subfragments_converter1_next_state[0:0] + update \converter1_counter_subfragments_converter1_next_value $0\converter1_counter_subfragments_converter1_next_value[0:0] + update \converter1_counter_subfragments_converter1_next_value_ce $0\converter1_counter_subfragments_converter1_next_value_ce[0:0] end - attribute \src "ls180.v:395.5-395.43" - process $proc$ls180.v:395$2995 + attribute \src "ls180.v:159.5-159.33" + process $proc$ls180.v:159$1668 assign { } { } - assign $0\main_sdram_cmd_payload_is_write[0:0] 1'0 + assign $1\libresocsim_reload_re[0:0] 1'0 sync always - update \main_sdram_cmd_payload_is_write $0\main_sdram_cmd_payload_is_write[0:0] sync init + update \libresocsim_reload_re $1\libresocsim_reload_re[0:0] end - attribute \src "ls180.v:3960.1-4032.4" - process $proc$ls180.v:3960$430 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_en1[0:0] 1'0 - assign $0\main_sdram_choose_req_want_reads[0:0] 1'0 - assign $0\main_sdram_choose_req_want_writes[0:0] 1'0 - assign $0\main_sdram_cmd_ready[0:0] 1'0 - assign { } { } - assign $0\main_sdram_choose_req_cmd_ready[0:0] 1'0 - assign $0\main_sdram_steerer_sel[1:0] 2'00 - assign $0\main_sdram_en0[0:0] 1'0 - assign { } { } - assign $0\main_sdram_choose_req_want_activates[0:0] \main_sdram_ras_allowed - assign $0\builder_multiplexer_next_state[2:0] \builder_multiplexer_state - attribute \src "ls180.v:3972.2-4031.9" - switch \builder_multiplexer_state - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdram_en1[0:0] 1'1 - assign $0\main_sdram_choose_req_want_writes[0:0] 1'1 - assign $0\main_sdram_steerer_sel[1:0] 2'10 - attribute \src "ls180.v:3976.4-3982.7" - switch 1'1 - attribute \src "ls180.v:3976.8-3976.12" - case 1'1 - assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:3977$437_Y - case - end - attribute \src "ls180.v:3984.4-3988.7" - switch \main_sdram_read_available - attribute \src "ls180.v:3984.8-3984.33" - case 1'1 - attribute \src "ls180.v:3985.5-3987.8" - switch $or$ls180.v:3985$439_Y - attribute \src "ls180.v:3985.9-3985.63" - case 1'1 - assign $0\builder_multiplexer_next_state[2:0] 3'011 - case - end - case - end - attribute \src "ls180.v:3989.4-3991.7" - switch \main_sdram_go_to_refresh - attribute \src "ls180.v:3989.8-3989.32" - case 1'1 - assign $0\builder_multiplexer_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdram_steerer_sel[1:0] 2'11 - assign $0\main_sdram_cmd_ready[0:0] 1'1 - attribute \src "ls180.v:3996.4-3998.7" - switch \main_sdram_cmd_last - attribute \src "ls180.v:3996.8-3996.27" - case 1'1 - assign $0\builder_multiplexer_next_state[2:0] 3'000 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - attribute \src "ls180.v:4001.4-4003.7" - switch \main_sdram_twtrcon_ready - attribute \src "ls180.v:4001.8-4001.32" - case 1'1 - assign $0\builder_multiplexer_next_state[2:0] 3'000 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\builder_multiplexer_next_state[2:0] 3'101 - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_multiplexer_next_state[2:0] 3'001 - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdram_en0[0:0] 1'1 - assign $0\main_sdram_choose_req_want_reads[0:0] 1'1 - assign $0\main_sdram_steerer_sel[1:0] 2'10 - attribute \src "ls180.v:4014.4-4020.7" - switch 1'1 - attribute \src "ls180.v:4014.8-4014.12" - case 1'1 - assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$ls180.v:4015$446_Y - case - end - attribute \src "ls180.v:4022.4-4026.7" - switch \main_sdram_write_available - attribute \src "ls180.v:4022.8-4022.34" - case 1'1 - attribute \src "ls180.v:4023.5-4025.8" - switch $or$ls180.v:4023$448_Y - attribute \src "ls180.v:4023.9-4023.62" - case 1'1 - assign $0\builder_multiplexer_next_state[2:0] 3'100 - case - end - case - end - attribute \src "ls180.v:4027.4-4029.7" - switch \main_sdram_go_to_refresh - attribute \src "ls180.v:4027.8-4027.32" - case 1'1 - assign $0\builder_multiplexer_next_state[2:0] 3'010 - case - end - end - sync always - update \main_sdram_cmd_ready $0\main_sdram_cmd_ready[0:0] - update \main_sdram_choose_req_want_reads $0\main_sdram_choose_req_want_reads[0:0] - update \main_sdram_choose_req_want_writes $0\main_sdram_choose_req_want_writes[0:0] - update \main_sdram_choose_req_want_activates $0\main_sdram_choose_req_want_activates[0:0] - update \main_sdram_choose_req_cmd_ready $0\main_sdram_choose_req_cmd_ready[0:0] - update \main_sdram_steerer_sel $0\main_sdram_steerer_sel[1:0] - update \main_sdram_en0 $0\main_sdram_en0[0:0] - update \main_sdram_en1 $0\main_sdram_en1[0:0] - update \builder_multiplexer_next_state $0\builder_multiplexer_next_state[2:0] - end - attribute \src "ls180.v:401.11-401.44" - process $proc$ls180.v:401$2996 + attribute \src "ls180.v:160.5-160.34" + process $proc$ls180.v:160$1669 assign { } { } - assign $1\main_sdram_timer_count1[9:0] 10'1100001101 + assign $1\libresocsim_en_storage[0:0] 1'0 sync always sync init - update \main_sdram_timer_count1 $1\main_sdram_timer_count1[9:0] + update \libresocsim_en_storage $1\libresocsim_en_storage[0:0] end - attribute \src "ls180.v:403.5-403.38" - process $proc$ls180.v:403$2997 + attribute \src "ls180.v:161.5-161.29" + process $proc$ls180.v:161$1670 assign { } { } - assign $1\main_sdram_postponer_req_o[0:0] 1'0 + assign $1\libresocsim_en_re[0:0] 1'0 sync always sync init - update \main_sdram_postponer_req_o $1\main_sdram_postponer_req_o[0:0] + update \libresocsim_en_re $1\libresocsim_en_re[0:0] end - attribute \src "ls180.v:404.5-404.38" - process $proc$ls180.v:404$2998 + attribute \src "ls180.v:162.5-162.44" + process $proc$ls180.v:162$1671 assign { } { } - assign $1\main_sdram_postponer_count[0:0] 1'0 + assign $1\libresocsim_update_value_storage[0:0] 1'0 sync always sync init - update \main_sdram_postponer_count $1\main_sdram_postponer_count[0:0] + update \libresocsim_update_value_storage $1\libresocsim_update_value_storage[0:0] end - attribute \src "ls180.v:405.5-405.39" - process $proc$ls180.v:405$2999 + attribute \src "ls180.v:163.5-163.39" + process $proc$ls180.v:163$1672 assign { } { } - assign $1\main_sdram_sequencer_start0[0:0] 1'0 + assign $1\libresocsim_update_value_re[0:0] 1'0 sync always sync init - update \main_sdram_sequencer_start0 $1\main_sdram_sequencer_start0[0:0] - end - attribute \src "ls180.v:4056.1-4069.4" - process $proc$ls180.v:4056$577 - assign { } { } - assign { } { } - assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000 - assign $0\main_sdram_interface_wdata_we[1:0] 2'00 - attribute \src "ls180.v:4059.2-4068.9" - switch \builder_new_master_wdata_ready - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_sdram_interface_wdata[15:0] \main_port_wdata_payload_data - assign $0\main_sdram_interface_wdata_we[1:0] \main_port_wdata_payload_we - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000 - assign $0\main_sdram_interface_wdata_we[1:0] 2'00 - end - sync always - update \main_sdram_interface_wdata $0\main_sdram_interface_wdata[15:0] - update \main_sdram_interface_wdata_we $0\main_sdram_interface_wdata_we[1:0] + update \libresocsim_update_value_re $1\libresocsim_update_value_re[0:0] end - attribute \src "ls180.v:4076.1-4086.4" - process $proc$ls180.v:4076$579 + attribute \src "ls180.v:1634.1-1644.4" + process $proc$ls180.v:1634$47 assign { } { } - assign $0\main_litedram_wb_dat_w[15:0] 16'0000000000000000 - attribute \src "ls180.v:4078.2-4085.9" - switch \main_converter_counter + assign $0\wb_sdram_dat_w[31:0] 0 + attribute \src "ls180.v:1636.2-1643.9" + switch \socbushandler_counter attribute \src "ls180.v:0.0-0.0" case 1'0 - assign $0\main_litedram_wb_dat_w[15:0] \main_wb_sdram_dat_w [15:0] + assign $0\wb_sdram_dat_w[31:0] \socbushandler_converted_interface_dat_w [31:0] attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_litedram_wb_dat_w[15:0] \main_wb_sdram_dat_w [31:16] + assign $0\wb_sdram_dat_w[31:0] \socbushandler_converted_interface_dat_w [63:32] case end sync always - update \main_litedram_wb_dat_w $0\main_litedram_wb_dat_w[15:0] + update \wb_sdram_dat_w $0\wb_sdram_dat_w[31:0] end - attribute \src "ls180.v:408.5-408.38" - process $proc$ls180.v:408$3000 + attribute \src "ls180.v:164.12-164.44" + process $proc$ls180.v:164$1673 assign { } { } - assign $1\main_sdram_sequencer_done1[0:0] 1'0 + assign $1\libresocsim_value_status[31:0] 0 sync always sync init - update \main_sdram_sequencer_done1 $1\main_sdram_sequencer_done1[0:0] + update \libresocsim_value_status $1\libresocsim_value_status[31:0] end - attribute \src "ls180.v:4088.1-4134.4" - process $proc$ls180.v:4088$580 + attribute \src "ls180.v:1646.1-1692.4" + process $proc$ls180.v:1646$48 assign { } { } assign { } { } assign { } { } @@ -290029,52 +263568,52 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_litedram_wb_cyc[0:0] 1'0 + assign $0\wb_sdram_sel[3:0] 4'0000 + assign $0\wb_sdram_cyc[0:0] 1'0 + assign $0\wb_sdram_stb[0:0] 1'0 + assign $0\socbushandler_skip[0:0] 1'0 + assign $0\wb_sdram_we[0:0] 1'0 assign { } { } - assign $0\main_litedram_wb_stb[0:0] 1'0 - assign $0\main_converter_counter_converter_next_value[0:0] 1'0 - assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'0 - assign $0\main_litedram_wb_we[0:0] 1'0 - assign $0\main_converter_skip[0:0] 1'0 - assign $0\main_wb_sdram_ack[0:0] 1'0 - assign $0\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 - assign $0\main_litedram_wb_sel[1:0] 2'00 - assign $0\builder_converter_next_state[0:0] \builder_converter_state - attribute \src "ls180.v:4100.2-4133.9" - switch \builder_converter_state + assign $0\socbushandler_counter_subfragments_converter2_next_value[0:0] 1'0 + assign $0\socbushandler_counter_subfragments_converter2_next_value_ce[0:0] 1'0 + assign $0\wb_sdram_adr[29:0] 30'000000000000000000000000000000 + assign $0\socbushandler_converted_interface_ack[0:0] 1'0 + assign $0\subfragments_converter2_next_state[0:0] \subfragments_converter2_state + attribute \src "ls180.v:1658.2-1691.9" + switch \subfragments_converter2_state attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_litedram_wb_adr[29:0] { \main_wb_sdram_adr [28:0] \main_converter_counter } - attribute \src "ls180.v:4103.4-4110.11" - switch \main_converter_counter + assign $0\wb_sdram_adr[29:0] { \socbushandler_converted_interface_adr [28:0] \socbushandler_counter } + attribute \src "ls180.v:1661.4-1668.11" + switch \socbushandler_counter attribute \src "ls180.v:0.0-0.0" case 1'0 - assign $0\main_litedram_wb_sel[1:0] \main_wb_sdram_sel [1:0] + assign $0\wb_sdram_sel[3:0] \socbushandler_converted_interface_sel [3:0] attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_litedram_wb_sel[1:0] \main_wb_sdram_sel [3:2] + assign $0\wb_sdram_sel[3:0] \socbushandler_converted_interface_sel [7:4] case end - attribute \src "ls180.v:4111.4-4124.7" - switch $and$ls180.v:4111$581_Y - attribute \src "ls180.v:4111.8-4111.47" + attribute \src "ls180.v:1669.4-1682.7" + switch $and$ls180.v:1669$49_Y + attribute \src "ls180.v:1669.8-1669.87" case 1'1 - assign $0\main_converter_skip[0:0] $eq$ls180.v:4112$582_Y - assign $0\main_litedram_wb_we[0:0] \main_wb_sdram_we - assign $0\main_litedram_wb_cyc[0:0] $not$ls180.v:4114$583_Y - assign $0\main_litedram_wb_stb[0:0] $not$ls180.v:4115$584_Y - attribute \src "ls180.v:4116.5-4123.8" - switch $or$ls180.v:4116$585_Y - attribute \src "ls180.v:4116.9-4116.53" + assign $0\socbushandler_skip[0:0] $eq$ls180.v:1670$50_Y + assign $0\wb_sdram_we[0:0] \socbushandler_converted_interface_we + assign $0\wb_sdram_cyc[0:0] $not$ls180.v:1672$51_Y + assign $0\wb_sdram_stb[0:0] $not$ls180.v:1673$52_Y + attribute \src "ls180.v:1674.5-1681.8" + switch $or$ls180.v:1674$53_Y + attribute \src "ls180.v:1674.9-1674.44" case 1'1 - assign $0\main_converter_counter_converter_next_value[0:0] $add$ls180.v:4117$586_Y - assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4119.6-4122.9" - switch $eq$ls180.v:4119$587_Y - attribute \src "ls180.v:4119.10-4119.42" + assign $0\socbushandler_counter_subfragments_converter2_next_value[0:0] $add$ls180.v:1675$54_Y + assign $0\socbushandler_counter_subfragments_converter2_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:1677.6-1680.9" + switch $eq$ls180.v:1677$55_Y + attribute \src "ls180.v:1677.10-1677.41" case 1'1 - assign $0\main_wb_sdram_ack[0:0] 1'1 - assign $0\builder_converter_next_state[0:0] 1'0 + assign $0\socbushandler_converted_interface_ack[0:0] 1'1 + assign $0\subfragments_converter2_next_state[0:0] 1'0 case end case @@ -290083,353 +263622,98 @@ module \ls180 end attribute \src "ls180.v:0.0-0.0" case - assign $0\main_converter_counter_converter_next_value[0:0] 1'0 - assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4129.4-4131.7" - switch $and$ls180.v:4129$588_Y - attribute \src "ls180.v:4129.8-4129.47" + assign $0\socbushandler_counter_subfragments_converter2_next_value[0:0] 1'0 + assign $0\socbushandler_counter_subfragments_converter2_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:1687.4-1689.7" + switch $and$ls180.v:1687$56_Y + attribute \src "ls180.v:1687.8-1687.87" case 1'1 - assign $0\builder_converter_next_state[0:0] 1'1 + assign $0\subfragments_converter2_next_state[0:0] 1'1 case end end sync always - update \main_wb_sdram_ack $0\main_wb_sdram_ack[0:0] - update \main_litedram_wb_adr $0\main_litedram_wb_adr[29:0] - update \main_litedram_wb_sel $0\main_litedram_wb_sel[1:0] - update \main_litedram_wb_cyc $0\main_litedram_wb_cyc[0:0] - update \main_litedram_wb_stb $0\main_litedram_wb_stb[0:0] - update \main_litedram_wb_we $0\main_litedram_wb_we[0:0] - update \main_converter_skip $0\main_converter_skip[0:0] - update \builder_converter_next_state $0\builder_converter_next_state[0:0] - update \main_converter_counter_converter_next_value $0\main_converter_counter_converter_next_value[0:0] - update \main_converter_counter_converter_next_value_ce $0\main_converter_counter_converter_next_value_ce[0:0] - end - attribute \src "ls180.v:409.11-409.46" - process $proc$ls180.v:409$3001 - assign { } { } - assign $1\main_sdram_sequencer_counter[3:0] 4'0000 - sync always - sync init - update \main_sdram_sequencer_counter $1\main_sdram_sequencer_counter[3:0] - end - attribute \src "ls180.v:410.5-410.38" - process $proc$ls180.v:410$3002 - assign { } { } - assign $1\main_sdram_sequencer_count[0:0] 1'0 - sync always - sync init - update \main_sdram_sequencer_count $1\main_sdram_sequencer_count[0:0] - end - attribute \src "ls180.v:416.5-416.51" - process $proc$ls180.v:416$3003 - assign { } { } - assign $1\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_req_wdata_ready $1\main_sdram_bankmachine0_req_wdata_ready[0:0] - end - attribute \src "ls180.v:417.5-417.51" - process $proc$ls180.v:417$3004 - assign { } { } - assign $1\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_req_rdata_valid $1\main_sdram_bankmachine0_req_rdata_valid[0:0] - end - attribute \src "ls180.v:4179.1-4184.4" - process $proc$ls180.v:4179$620 - assign { } { } - assign $0\main_uart_tx_clear[0:0] 1'0 - attribute \src "ls180.v:4181.2-4183.5" - switch $and$ls180.v:4181$621_Y - attribute \src "ls180.v:4181.6-4181.79" - case 1'1 - assign $0\main_uart_tx_clear[0:0] 1'1 - case - end - sync always - update \main_uart_tx_clear $0\main_uart_tx_clear[0:0] - end - attribute \src "ls180.v:4185.1-4189.4" - process $proc$ls180.v:4185$622 - assign { } { } - assign { } { } - assign $0\main_uart_eventmanager_status_w[1:0] [0] \main_uart_tx_status - assign $0\main_uart_eventmanager_status_w[1:0] [1] \main_uart_rx_status - sync always - update \main_uart_eventmanager_status_w $0\main_uart_eventmanager_status_w[1:0] - end - attribute \src "ls180.v:419.5-419.47" - process $proc$ls180.v:419$3005 - assign { } { } - assign $1\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_refresh_gnt $1\main_sdram_bankmachine0_refresh_gnt[0:0] - end - attribute \src "ls180.v:4190.1-4195.4" - process $proc$ls180.v:4190$623 - assign { } { } - assign $0\main_uart_rx_clear[0:0] 1'0 - attribute \src "ls180.v:4192.2-4194.5" - switch $and$ls180.v:4192$624_Y - attribute \src "ls180.v:4192.6-4192.79" - case 1'1 - assign $0\main_uart_rx_clear[0:0] 1'1 - case - end - sync always - update \main_uart_rx_clear $0\main_uart_rx_clear[0:0] - end - attribute \src "ls180.v:4196.1-4200.4" - process $proc$ls180.v:4196$625 - assign { } { } - assign { } { } - assign $0\main_uart_eventmanager_pending_w[1:0] [0] \main_uart_tx_pending - assign $0\main_uart_eventmanager_pending_w[1:0] [1] \main_uart_rx_pending - sync always - update \main_uart_eventmanager_pending_w $0\main_uart_eventmanager_pending_w[1:0] + update \wb_sdram_adr $0\wb_sdram_adr[29:0] + update \wb_sdram_sel $0\wb_sdram_sel[3:0] + update \wb_sdram_cyc $0\wb_sdram_cyc[0:0] + update \wb_sdram_stb $0\wb_sdram_stb[0:0] + update \wb_sdram_we $0\wb_sdram_we[0:0] + update \socbushandler_converted_interface_ack $0\socbushandler_converted_interface_ack[0:0] + update \socbushandler_skip $0\socbushandler_skip[0:0] + update \subfragments_converter2_next_state $0\subfragments_converter2_next_state[0:0] + update \socbushandler_counter_subfragments_converter2_next_value $0\socbushandler_counter_subfragments_converter2_next_value[0:0] + update \socbushandler_counter_subfragments_converter2_next_value_ce $0\socbushandler_counter_subfragments_converter2_next_value_ce[0:0] end - attribute \src "ls180.v:420.5-420.45" - process $proc$ls180.v:420$3006 + attribute \src "ls180.v:168.5-168.36" + process $proc$ls180.v:168$1674 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 + assign $1\libresocsim_zero_pending[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_valid $1\main_sdram_bankmachine0_cmd_valid[0:0] + update \libresocsim_zero_pending $1\libresocsim_zero_pending[0:0] end - attribute \src "ls180.v:421.5-421.45" - process $proc$ls180.v:421$3007 + attribute \src "ls180.v:1695.1-1705.4" + process $proc$ls180.v:1695$57 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_ready $1\main_sdram_bankmachine0_cmd_ready[0:0] - end - attribute \src "ls180.v:4218.1-4225.4" - process $proc$ls180.v:4218$633 assign { } { } - assign $0\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 - attribute \src "ls180.v:4220.2-4224.5" - switch \main_uart_tx_fifo_replace - attribute \src "ls180.v:4220.6-4220.31" - case 1'1 - assign $0\main_uart_tx_fifo_wrport_adr[3:0] $sub$ls180.v:4221$634_Y - attribute \src "ls180.v:4222.6-4222.10" - case - assign $0\main_uart_tx_fifo_wrport_adr[3:0] \main_uart_tx_fifo_produce - end + assign $0\libresocsim_we[7:0] [0] $and$ls180.v:1697$60_Y + assign $0\libresocsim_we[7:0] [1] $and$ls180.v:1698$63_Y + assign $0\libresocsim_we[7:0] [2] $and$ls180.v:1699$66_Y + assign $0\libresocsim_we[7:0] [3] $and$ls180.v:1700$69_Y + assign $0\libresocsim_we[7:0] [4] $and$ls180.v:1701$72_Y + assign $0\libresocsim_we[7:0] [5] $and$ls180.v:1702$75_Y + assign $0\libresocsim_we[7:0] [6] $and$ls180.v:1703$78_Y + assign $0\libresocsim_we[7:0] [7] $and$ls180.v:1704$81_Y sync always - update \main_uart_tx_fifo_wrport_adr $0\main_uart_tx_fifo_wrport_adr[3:0] + update \libresocsim_we $0\libresocsim_we[7:0] end - attribute \src "ls180.v:422.12-422.57" - process $proc$ls180.v:422$3008 + attribute \src "ls180.v:170.5-170.34" + process $proc$ls180.v:170$1675 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 + assign $1\libresocsim_zero_clear[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_payload_a $1\main_sdram_bankmachine0_cmd_payload_a[12:0] + update \libresocsim_zero_clear $1\libresocsim_zero_clear[0:0] end - attribute \src "ls180.v:424.5-424.51" - process $proc$ls180.v:424$3009 + attribute \src "ls180.v:171.5-171.40" + process $proc$ls180.v:171$1676 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 + assign $1\libresocsim_zero_old_trigger[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_payload_cas $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] + update \libresocsim_zero_old_trigger $1\libresocsim_zero_old_trigger[0:0] end - attribute \src "ls180.v:4248.1-4255.4" - process $proc$ls180.v:4248$644 + attribute \src "ls180.v:1711.1-1716.4" + process $proc$ls180.v:1711$83 assign { } { } - assign $0\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 - attribute \src "ls180.v:4250.2-4254.5" - switch \main_uart_rx_fifo_replace - attribute \src "ls180.v:4250.6-4250.31" + assign $0\libresocsim_zero_clear[0:0] 1'0 + attribute \src "ls180.v:1713.2-1715.5" + switch $and$ls180.v:1713$84_Y + attribute \src "ls180.v:1713.6-1713.80" case 1'1 - assign $0\main_uart_rx_fifo_wrport_adr[3:0] $sub$ls180.v:4251$645_Y - attribute \src "ls180.v:4252.6-4252.10" - case - assign $0\main_uart_rx_fifo_wrport_adr[3:0] \main_uart_rx_fifo_produce - end - sync always - update \main_uart_rx_fifo_wrport_adr $0\main_uart_rx_fifo_wrport_adr[3:0] - end - attribute \src "ls180.v:425.5-425.51" - process $proc$ls180.v:425$3010 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_ras $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] - end - attribute \src "ls180.v:426.5-426.50" - process $proc$ls180.v:426$3011 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_we $1\main_sdram_bankmachine0_cmd_payload_we[0:0] - end - attribute \src "ls180.v:4268.1-4272.4" - process $proc$ls180.v:4268$651 - assign { } { } - assign { } { } - assign { } { } - assign $0\gpio_o[15:0] \main_gpiotristateasic1_pads_o - sync always - update \gpio_o $0\gpio_o[15:0] - end - attribute \src "ls180.v:427.5-427.54" - process $proc$ls180.v:427$3012 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_is_cmd $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] - end - attribute \src "ls180.v:4273.1-4277.4" - process $proc$ls180.v:4273$652 - assign { } { } - assign { } { } - assign { } { } - assign $0\gpio_oe[15:0] \main_gpiotristateasic1_pads_oe - sync always - update \gpio_oe $0\gpio_oe[15:0] - end - attribute \src "ls180.v:428.5-428.55" - process $proc$ls180.v:428$3013 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_is_read $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] - end - attribute \src "ls180.v:4289.1-4337.4" - process $proc$ls180.v:4289$657 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 - assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'0 - assign $0\main_spimaster25_clk_enable[0:0] 1'0 - assign $0\main_spimaster26_cs_enable[0:0] 1'0 - assign $0\main_spimaster28_mosi_latch[0:0] 1'0 - assign $0\main_spimaster2_done[0:0] 1'0 - assign $0\main_spimaster29_miso_latch[0:0] 1'0 - assign $0\main_spimaster3_irq[0:0] 1'0 - assign { } { } - assign $0\builder_spimaster0_next_state[1:0] \builder_spimaster0_state - attribute \src "ls180.v:4300.2-4336.9" - switch \builder_spimaster0_state - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\main_spimaster27_count_spimaster0_next_value[2:0] 3'000 - assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4304.4-4307.7" - switch \main_spimaster32_clk_fall - attribute \src "ls180.v:4304.8-4304.33" - case 1'1 - assign $0\main_spimaster26_cs_enable[0:0] 1'1 - assign $0\builder_spimaster0_next_state[1:0] 2'10 - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\main_spimaster25_clk_enable[0:0] 1'1 - assign $0\main_spimaster26_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4312.4-4318.7" - switch \main_spimaster32_clk_fall - attribute \src "ls180.v:4312.8-4312.33" - case 1'1 - assign $0\main_spimaster27_count_spimaster0_next_value[2:0] $add$ls180.v:4313$658_Y - assign $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4315.5-4317.8" - switch $eq$ls180.v:4315$660_Y - attribute \src "ls180.v:4315.9-4315.68" - case 1'1 - assign $0\builder_spimaster0_next_state[1:0] 2'11 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'11 - assign $0\main_spimaster26_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4322.4-4326.7" - switch \main_spimaster31_clk_rise - attribute \src "ls180.v:4322.8-4322.33" - case 1'1 - assign $0\main_spimaster29_miso_latch[0:0] 1'1 - assign $0\main_spimaster3_irq[0:0] 1'1 - assign $0\builder_spimaster0_next_state[1:0] 2'00 - case - end - attribute \src "ls180.v:0.0-0.0" + assign $0\libresocsim_zero_clear[0:0] 1'1 case - assign $0\main_spimaster2_done[0:0] 1'1 - attribute \src "ls180.v:4330.4-4334.7" - switch \main_spimaster0_start - attribute \src "ls180.v:4330.8-4330.29" - case 1'1 - assign $0\main_spimaster2_done[0:0] 1'0 - assign $0\main_spimaster28_mosi_latch[0:0] 1'1 - assign $0\builder_spimaster0_next_state[1:0] 2'01 - case - end end sync always - update \main_spimaster2_done $0\main_spimaster2_done[0:0] - update \main_spimaster3_irq $0\main_spimaster3_irq[0:0] - update \main_spimaster25_clk_enable $0\main_spimaster25_clk_enable[0:0] - update \main_spimaster26_cs_enable $0\main_spimaster26_cs_enable[0:0] - update \main_spimaster28_mosi_latch $0\main_spimaster28_mosi_latch[0:0] - update \main_spimaster29_miso_latch $0\main_spimaster29_miso_latch[0:0] - update \builder_spimaster0_next_state $0\builder_spimaster0_next_state[1:0] - update \main_spimaster27_count_spimaster0_next_value $0\main_spimaster27_count_spimaster0_next_value[2:0] - update \main_spimaster27_count_spimaster0_next_value_ce $0\main_spimaster27_count_spimaster0_next_value_ce[0:0] - end - attribute \src "ls180.v:429.5-429.56" - process $proc$ls180.v:429$3014 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_payload_is_write $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] - end - attribute \src "ls180.v:430.5-430.50" - process $proc$ls180.v:430$3015 - assign { } { } - assign $1\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_auto_precharge $1\main_sdram_bankmachine0_auto_precharge[0:0] + update \libresocsim_zero_clear $0\libresocsim_zero_clear[0:0] end - attribute \src "ls180.v:433.5-433.67" - process $proc$ls180.v:433$3016 + attribute \src "ls180.v:1720.1-1730.4" + process $proc$ls180.v:1720$86 assign { } { } - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0 - sync always - update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] - sync init - end - attribute \src "ls180.v:434.5-434.66" - process $proc$ls180.v:434$3017 assign { } { } - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0 + assign $0\ram_we[7:0] [0] $and$ls180.v:1722$89_Y + assign $0\ram_we[7:0] [1] $and$ls180.v:1723$92_Y + assign $0\ram_we[7:0] [2] $and$ls180.v:1724$95_Y + assign $0\ram_we[7:0] [3] $and$ls180.v:1725$98_Y + assign $0\ram_we[7:0] [4] $and$ls180.v:1726$101_Y + assign $0\ram_we[7:0] [5] $and$ls180.v:1727$104_Y + assign $0\ram_we[7:0] [6] $and$ls180.v:1728$107_Y + assign $0\ram_we[7:0] [7] $and$ls180.v:1729$110_Y sync always - update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] - sync init + update \ram_we $0\ram_we[7:0] end - attribute \src "ls180.v:4348.1-4396.4" - process $proc$ls180.v:4348$665 - assign { } { } + attribute \src "ls180.v:1769.1-1823.4" + process $proc$ls180.v:1769$111 assign { } { } assign { } { } assign { } { } @@ -290438,121 +263722,7 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_spisdcard_clk_enable[0:0] 1'0 - assign $0\main_spisdcard_cs_enable[0:0] 1'0 - assign $0\main_spisdcard_mosi_latch[0:0] 1'0 - assign $0\main_spisdcard_done0[0:0] 1'0 - assign $0\main_spisdcard_miso_latch[0:0] 1'0 - assign $0\main_spisdcard_irq[0:0] 1'0 - assign { } { } - assign $0\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 - assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'0 - assign $0\builder_spimaster1_next_state[1:0] \builder_spimaster1_state - attribute \src "ls180.v:4359.2-4395.9" - switch \builder_spimaster1_state - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\main_spisdcard_count_spimaster1_next_value[2:0] 3'000 - assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4363.4-4366.7" - switch \main_spisdcard_clk_fall - attribute \src "ls180.v:4363.8-4363.31" - case 1'1 - assign $0\main_spisdcard_cs_enable[0:0] 1'1 - assign $0\builder_spimaster1_next_state[1:0] 2'10 - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\main_spisdcard_clk_enable[0:0] 1'1 - assign $0\main_spisdcard_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4371.4-4377.7" - switch \main_spisdcard_clk_fall - attribute \src "ls180.v:4371.8-4371.31" - case 1'1 - assign $0\main_spisdcard_count_spimaster1_next_value[2:0] $add$ls180.v:4372$666_Y - assign $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4374.5-4376.8" - switch $eq$ls180.v:4374$668_Y - attribute \src "ls180.v:4374.9-4374.66" - case 1'1 - assign $0\builder_spimaster1_next_state[1:0] 2'11 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 2'11 - assign $0\main_spisdcard_cs_enable[0:0] 1'1 - attribute \src "ls180.v:4381.4-4385.7" - switch \main_spisdcard_clk_rise - attribute \src "ls180.v:4381.8-4381.31" - case 1'1 - assign $0\main_spisdcard_miso_latch[0:0] 1'1 - assign $0\main_spisdcard_irq[0:0] 1'1 - assign $0\builder_spimaster1_next_state[1:0] 2'00 - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_spisdcard_done0[0:0] 1'1 - attribute \src "ls180.v:4389.4-4393.7" - switch \main_spisdcard_start0 - attribute \src "ls180.v:4389.8-4389.29" - case 1'1 - assign $0\main_spisdcard_done0[0:0] 1'0 - assign $0\main_spisdcard_mosi_latch[0:0] 1'1 - assign $0\builder_spimaster1_next_state[1:0] 2'01 - case - end - end - sync always - update \main_spisdcard_done0 $0\main_spisdcard_done0[0:0] - update \main_spisdcard_irq $0\main_spisdcard_irq[0:0] - update \main_spisdcard_clk_enable $0\main_spisdcard_clk_enable[0:0] - update \main_spisdcard_cs_enable $0\main_spisdcard_cs_enable[0:0] - update \main_spisdcard_mosi_latch $0\main_spisdcard_mosi_latch[0:0] - update \main_spisdcard_miso_latch $0\main_spisdcard_miso_latch[0:0] - update \builder_spimaster1_next_state $0\builder_spimaster1_next_state[1:0] - update \main_spisdcard_count_spimaster1_next_value $0\main_spisdcard_count_spimaster1_next_value[2:0] - update \main_spisdcard_count_spimaster1_next_value_ce $0\main_spisdcard_count_spimaster1_next_value_ce[0:0] - end - attribute \src "ls180.v:4428.1-4456.4" - process $proc$ls180.v:4428$690 assign { } { } - assign $0\main_sdphy_clocker_clk1[0:0] 1'0 - attribute \src "ls180.v:4430.2-4455.9" - switch \main_sdphy_clocker_storage - attribute \src "ls180.v:0.0-0.0" - case 9'000000100 - assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [1] - attribute \src "ls180.v:0.0-0.0" - case 9'000001000 - assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [2] - attribute \src "ls180.v:0.0-0.0" - case 9'000010000 - assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [3] - attribute \src "ls180.v:0.0-0.0" - case 9'000100000 - assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [4] - attribute \src "ls180.v:0.0-0.0" - case 9'001000000 - assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [5] - attribute \src "ls180.v:0.0-0.0" - case 9'010000000 - assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [6] - attribute \src "ls180.v:0.0-0.0" - case 9'100000000 - assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [7] - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdphy_clocker_clk1[0:0] \main_sdphy_clocker_clks [0] - end - sync always - update \main_sdphy_clocker_clk1 $0\main_sdphy_clocker_clk1[0:0] - end - attribute \src "ls180.v:4458.1-4491.4" - process $proc$ls180.v:4458$693 assign { } { } assign { } { } assign { } { } @@ -290561,227 +263731,275 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'0 assign { } { } - assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 - assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 - assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'0 - assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'0 - assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'0 - assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'0000 - assign $0\builder_sdphy_sdphyinit_next_state[0:0] \builder_sdphy_sdphyinit_state - attribute \src "ls180.v:4468.2-4490.9" - switch \builder_sdphy_sdphyinit_state - attribute \src "ls180.v:0.0-0.0" + assign $0\sdram_slave_p0_rddata[15:0] 16'0000000000000000 + assign $0\sdram_slave_p0_rddata_valid[0:0] 1'0 + assign $0\sdram_master_p0_address[12:0] 13'0000000000000 + assign $0\sdram_master_p0_bank[1:0] 2'00 + assign $0\sdram_master_p0_cas_n[0:0] 1'1 + assign $0\sdram_master_p0_cs_n[0:0] 1'1 + assign $0\sdram_master_p0_ras_n[0:0] 1'1 + assign $0\sdram_master_p0_we_n[0:0] 1'1 + assign $0\sdram_master_p0_cke[0:0] 1'0 + assign $0\sdram_master_p0_odt[0:0] 1'0 + assign $0\sdram_master_p0_reset_n[0:0] 1'0 + assign $0\sdram_inti_p0_rddata[15:0] 16'0000000000000000 + assign $0\sdram_master_p0_act_n[0:0] 1'1 + assign $0\sdram_inti_p0_rddata_valid[0:0] 1'0 + assign $0\sdram_master_p0_wrdata[15:0] 16'0000000000000000 + assign $0\sdram_master_p0_wrdata_en[0:0] 1'0 + assign $0\sdram_master_p0_wrdata_mask[1:0] 2'00 + assign $0\sdram_master_p0_rddata_en[0:0] 1'0 + attribute \src "ls180.v:1788.2-1822.5" + switch \sdram_sel + attribute \src "ls180.v:1788.6-1788.15" case 1'1 - assign $0\main_sdphy_init_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] 1'1 - assign $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] 1'1 - assign $0\main_sdphy_init_pads_out_payload_data_oe[0:0] 1'1 - assign $0\main_sdphy_init_pads_out_payload_data_o[3:0] 4'1111 - attribute \src "ls180.v:4475.4-4481.7" - switch \main_sdphy_init_pads_out_ready - attribute \src "ls180.v:4475.8-4475.38" - case 1'1 - assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] $add$ls180.v:4476$694_Y - assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4478.5-4480.8" - switch $eq$ls180.v:4478$695_Y - attribute \src "ls180.v:4478.9-4478.41" - case 1'1 - assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'0 - case - end - case - end - attribute \src "ls180.v:0.0-0.0" + assign $0\sdram_master_p0_address[12:0] \sdram_slave_p0_address + assign $0\sdram_master_p0_bank[1:0] \sdram_slave_p0_bank + assign $0\sdram_master_p0_cas_n[0:0] \sdram_slave_p0_cas_n + assign $0\sdram_master_p0_cs_n[0:0] \sdram_slave_p0_cs_n + assign $0\sdram_master_p0_ras_n[0:0] \sdram_slave_p0_ras_n + assign $0\sdram_master_p0_we_n[0:0] \sdram_slave_p0_we_n + assign $0\sdram_master_p0_cke[0:0] \sdram_slave_p0_cke + assign $0\sdram_master_p0_odt[0:0] \sdram_slave_p0_odt + assign $0\sdram_master_p0_reset_n[0:0] \sdram_slave_p0_reset_n + assign $0\sdram_master_p0_act_n[0:0] \sdram_slave_p0_act_n + assign $0\sdram_master_p0_wrdata[15:0] \sdram_slave_p0_wrdata + assign $0\sdram_master_p0_wrdata_en[0:0] \sdram_slave_p0_wrdata_en + assign $0\sdram_master_p0_wrdata_mask[1:0] \sdram_slave_p0_wrdata_mask + assign $0\sdram_master_p0_rddata_en[0:0] \sdram_slave_p0_rddata_en + assign $0\sdram_slave_p0_rddata[15:0] \sdram_master_p0_rddata + assign $0\sdram_slave_p0_rddata_valid[0:0] \sdram_master_p0_rddata_valid + attribute \src "ls180.v:1805.6-1805.10" case - assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 - assign $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4486.4-4488.7" - switch \main_sdphy_init_initialize_re - attribute \src "ls180.v:4486.8-4486.37" - case 1'1 - assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'1 - case - end + assign $0\sdram_master_p0_address[12:0] \sdram_inti_p0_address + assign $0\sdram_master_p0_bank[1:0] \sdram_inti_p0_bank + assign $0\sdram_master_p0_cas_n[0:0] \sdram_inti_p0_cas_n + assign $0\sdram_master_p0_cs_n[0:0] \sdram_inti_p0_cs_n + assign $0\sdram_master_p0_ras_n[0:0] \sdram_inti_p0_ras_n + assign $0\sdram_master_p0_we_n[0:0] \sdram_inti_p0_we_n + assign $0\sdram_master_p0_cke[0:0] \sdram_inti_p0_cke + assign $0\sdram_master_p0_odt[0:0] \sdram_inti_p0_odt + assign $0\sdram_master_p0_reset_n[0:0] \sdram_inti_p0_reset_n + assign $0\sdram_master_p0_act_n[0:0] \sdram_inti_p0_act_n + assign $0\sdram_master_p0_wrdata[15:0] \sdram_inti_p0_wrdata + assign $0\sdram_master_p0_wrdata_en[0:0] \sdram_inti_p0_wrdata_en + assign $0\sdram_master_p0_wrdata_mask[1:0] \sdram_inti_p0_wrdata_mask + assign $0\sdram_master_p0_rddata_en[0:0] \sdram_inti_p0_rddata_en + assign $0\sdram_inti_p0_rddata[15:0] \sdram_master_p0_rddata + assign $0\sdram_inti_p0_rddata_valid[0:0] \sdram_master_p0_rddata_valid end sync always - update \main_sdphy_init_pads_out_payload_clk $0\main_sdphy_init_pads_out_payload_clk[0:0] - update \main_sdphy_init_pads_out_payload_cmd_o $0\main_sdphy_init_pads_out_payload_cmd_o[0:0] - update \main_sdphy_init_pads_out_payload_cmd_oe $0\main_sdphy_init_pads_out_payload_cmd_oe[0:0] - update \main_sdphy_init_pads_out_payload_data_o $0\main_sdphy_init_pads_out_payload_data_o[3:0] - update \main_sdphy_init_pads_out_payload_data_oe $0\main_sdphy_init_pads_out_payload_data_oe[0:0] - update \builder_sdphy_sdphyinit_next_state $0\builder_sdphy_sdphyinit_next_state[0:0] - update \main_sdphy_init_count_sdphy_sdphyinit_next_value $0\main_sdphy_init_count_sdphy_sdphyinit_next_value[7:0] - update \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce $0\main_sdphy_init_count_sdphy_sdphyinit_next_value_ce[0:0] + update \sdram_inti_p0_rddata $0\sdram_inti_p0_rddata[15:0] + update \sdram_inti_p0_rddata_valid $0\sdram_inti_p0_rddata_valid[0:0] + update \sdram_slave_p0_rddata $0\sdram_slave_p0_rddata[15:0] + update \sdram_slave_p0_rddata_valid $0\sdram_slave_p0_rddata_valid[0:0] + update \sdram_master_p0_address $0\sdram_master_p0_address[12:0] + update \sdram_master_p0_bank $0\sdram_master_p0_bank[1:0] + update \sdram_master_p0_cas_n $0\sdram_master_p0_cas_n[0:0] + update \sdram_master_p0_cs_n $0\sdram_master_p0_cs_n[0:0] + update \sdram_master_p0_ras_n $0\sdram_master_p0_ras_n[0:0] + update \sdram_master_p0_we_n $0\sdram_master_p0_we_n[0:0] + update \sdram_master_p0_cke $0\sdram_master_p0_cke[0:0] + update \sdram_master_p0_odt $0\sdram_master_p0_odt[0:0] + update \sdram_master_p0_reset_n $0\sdram_master_p0_reset_n[0:0] + update \sdram_master_p0_act_n $0\sdram_master_p0_act_n[0:0] + update \sdram_master_p0_wrdata $0\sdram_master_p0_wrdata[15:0] + update \sdram_master_p0_wrdata_en $0\sdram_master_p0_wrdata_en[0:0] + update \sdram_master_p0_wrdata_mask $0\sdram_master_p0_wrdata_mask[1:0] + update \sdram_master_p0_rddata_en $0\sdram_master_p0_rddata_en[0:0] end - attribute \src "ls180.v:449.11-449.68" - process $proc$ls180.v:449$3018 + attribute \src "ls180.v:180.5-180.44" + process $proc$ls180.v:180$1677 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $1\libresocsim_eventmanager_storage[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + update \libresocsim_eventmanager_storage $1\libresocsim_eventmanager_storage[0:0] end - attribute \src "ls180.v:4492.1-4568.4" - process $proc$ls180.v:4492$696 - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "ls180.v:181.5-181.39" + process $proc$ls180.v:181$1678 assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdphy_cmdw_done[0:0] 1'0 - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 - assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'0 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'0 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 - assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'0 - assign $0\builder_sdphy_sdphycmdw_next_state[1:0] \builder_sdphy_sdphycmdw_state - attribute \src "ls180.v:4502.2-4567.9" - switch \builder_sdphy_sdphycmdw_state - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 - attribute \src "ls180.v:4506.4-4531.11" - switch \main_sdphy_cmdw_count - attribute \src "ls180.v:0.0-0.0" - case 8'00000000 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [7] - attribute \src "ls180.v:0.0-0.0" - case 8'00000001 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [6] - attribute \src "ls180.v:0.0-0.0" - case 8'00000010 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [5] - attribute \src "ls180.v:0.0-0.0" - case 8'00000011 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [4] - attribute \src "ls180.v:0.0-0.0" - case 8'00000100 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [3] - attribute \src "ls180.v:0.0-0.0" - case 8'00000101 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [2] - attribute \src "ls180.v:0.0-0.0" - case 8'00000110 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [1] - attribute \src "ls180.v:0.0-0.0" - case 8'00000111 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] \main_sdphy_cmdw_sink_payload_data [0] - case - end - attribute \src "ls180.v:4532.4-4543.7" - switch \main_sdphy_cmdw_pads_out_ready - attribute \src "ls180.v:4532.8-4532.38" + assign $1\libresocsim_eventmanager_re[0:0] 1'0 + sync always + sync init + update \libresocsim_eventmanager_re $1\libresocsim_eventmanager_re[0:0] + end + attribute \src "ls180.v:182.12-182.37" + process $proc$ls180.v:182$1679 + assign { } { } + assign $1\libresocsim_value[31:0] 0 + sync always + sync init + update \libresocsim_value $1\libresocsim_value[31:0] + end + attribute \src "ls180.v:1827.1-1843.4" + process $proc$ls180.v:1827$112 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\sdram_inti_p0_we_n[0:0] 1'1 + assign $0\sdram_inti_p0_cas_n[0:0] 1'1 + assign $0\sdram_inti_p0_cs_n[0:0] 1'1 + assign $0\sdram_inti_p0_ras_n[0:0] 1'1 + attribute \src "ls180.v:1832.2-1842.5" + switch \sdram_command_issue_re + attribute \src "ls180.v:1832.6-1832.28" + case 1'1 + assign $0\sdram_inti_p0_cs_n[0:0] $not$ls180.v:1833$113_Y + assign $0\sdram_inti_p0_we_n[0:0] $not$ls180.v:1834$114_Y + assign $0\sdram_inti_p0_cas_n[0:0] $not$ls180.v:1835$115_Y + assign $0\sdram_inti_p0_ras_n[0:0] $not$ls180.v:1836$116_Y + attribute \src "ls180.v:1837.6-1837.10" + case + assign $0\sdram_inti_p0_cs_n[0:0] 1'1 + assign $0\sdram_inti_p0_we_n[0:0] 1'1 + assign $0\sdram_inti_p0_cas_n[0:0] 1'1 + assign $0\sdram_inti_p0_ras_n[0:0] 1'1 + end + sync always + update \sdram_inti_p0_cas_n $0\sdram_inti_p0_cas_n[0:0] + update \sdram_inti_p0_cs_n $0\sdram_inti_p0_cs_n[0:0] + update \sdram_inti_p0_ras_n $0\sdram_inti_p0_ras_n[0:0] + update \sdram_inti_p0_we_n $0\sdram_inti_p0_we_n[0:0] + end + attribute \src "ls180.v:1886.1-1916.4" + process $proc$ls180.v:1886$125 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\sdram_sequencer_start0[0:0] 1'0 + assign { } { } + assign $0\sdram_cmd_valid[0:0] 1'0 + assign $0\sdram_cmd_last[0:0] 1'0 + assign $0\subfragments_refresher_next_state[1:0] \subfragments_refresher_state + attribute \src "ls180.v:1892.2-1915.9" + switch \subfragments_refresher_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\sdram_cmd_valid[0:0] 1'1 + attribute \src "ls180.v:1895.4-1898.7" + switch \sdram_cmd_ready + attribute \src "ls180.v:1895.8-1895.23" case 1'1 - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4533$697_Y - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4535.5-4542.8" - switch $eq$ls180.v:4535$698_Y - attribute \src "ls180.v:4535.9-4535.40" - case 1'1 - attribute \src "ls180.v:4536.6-4541.9" - switch \main_sdphy_cmdw_sink_last - attribute \src "ls180.v:4536.10-4536.35" - case 1'1 - assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'10 - attribute \src "ls180.v:4538.10-4538.14" - case - assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1 - assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 - end - case - end + assign $0\sdram_sequencer_start0[0:0] 1'1 + assign $0\subfragments_refresher_next_state[1:0] 2'10 case end attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 - assign $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] 1'1 - attribute \src "ls180.v:4549.4-4556.7" - switch \main_sdphy_cmdw_pads_out_ready - attribute \src "ls180.v:4549.8-4549.38" + assign $0\sdram_cmd_valid[0:0] 1'1 + attribute \src "ls180.v:1902.4-1906.7" + switch \sdram_sequencer_done0 + attribute \src "ls180.v:1902.8-1902.29" case 1'1 - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$ls180.v:4550$699_Y - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4552.5-4555.8" - switch $eq$ls180.v:4552$700_Y - attribute \src "ls180.v:4552.9-4552.40" - case 1'1 - assign $0\main_sdphy_cmdw_sink_ready[0:0] 1'1 - assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 - case - end + assign $0\sdram_cmd_valid[0:0] 1'0 + assign $0\sdram_cmd_last[0:0] 1'1 + assign $0\subfragments_refresher_next_state[1:0] 2'00 case end attribute \src "ls180.v:0.0-0.0" case - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 - assign $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4561.4-4565.7" - switch $and$ls180.v:4561$701_Y - attribute \src "ls180.v:4561.8-4561.69" + attribute \src "ls180.v:1909.4-1913.7" + switch 1'1 + attribute \src "ls180.v:1909.8-1909.12" case 1'1 - assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'01 - attribute \src "ls180.v:4563.8-4563.12" + attribute \src "ls180.v:1910.5-1912.8" + switch \sdram_wants_refresh + attribute \src "ls180.v:1910.9-1910.28" + case 1'1 + assign $0\subfragments_refresher_next_state[1:0] 2'01 + case + end case - assign $0\main_sdphy_cmdw_done[0:0] 1'1 end end sync always - update \main_sdphy_cmdw_pads_out_payload_clk $0\main_sdphy_cmdw_pads_out_payload_clk[0:0] - update \main_sdphy_cmdw_pads_out_payload_cmd_o $0\main_sdphy_cmdw_pads_out_payload_cmd_o[0:0] - update \main_sdphy_cmdw_pads_out_payload_cmd_oe $0\main_sdphy_cmdw_pads_out_payload_cmd_oe[0:0] - update \main_sdphy_cmdw_sink_ready $0\main_sdphy_cmdw_sink_ready[0:0] - update \main_sdphy_cmdw_done $0\main_sdphy_cmdw_done[0:0] - update \builder_sdphy_sdphycmdw_next_state $0\builder_sdphy_sdphycmdw_next_state[1:0] - update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value[7:0] - update \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce $0\main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] + update \sdram_cmd_valid $0\sdram_cmd_valid[0:0] + update \sdram_cmd_last $0\sdram_cmd_last[0:0] + update \sdram_sequencer_start0 $0\sdram_sequencer_start0[0:0] + update \subfragments_refresher_next_state $0\subfragments_refresher_next_state[1:0] end - attribute \src "ls180.v:450.5-450.64" - process $proc$ls180.v:450$3019 + attribute \src "ls180.v:189.5-189.31" + process $proc$ls180.v:189$1680 assign { } { } - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0 + assign $1\ram_bus_ram_bus_ack[0:0] 1'0 sync always - update \main_sdram_bankmachine0_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] sync init + update \ram_bus_ram_bus_ack $1\ram_bus_ram_bus_ack[0:0] end - attribute \src "ls180.v:451.11-451.70" - process $proc$ls180.v:451$3020 + attribute \src "ls180.v:193.5-193.31" + process $proc$ls180.v:193$1681 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\ram_bus_ram_bus_err[0:0] 1'0 sync always + update \ram_bus_ram_bus_err $0\ram_bus_ram_bus_err[0:0] sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] end - attribute \src "ls180.v:452.11-452.70" - process $proc$ls180.v:452$3021 + attribute \src "ls180.v:1931.1-1938.4" + process $proc$ls180.v:1931$129 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "ls180.v:1933.2-1937.5" + switch \sdram_bankmachine0_row_col_n_addr_sel + attribute \src "ls180.v:1933.6-1933.43" + case 1'1 + assign $0\sdram_bankmachine0_cmd_payload_a[12:0] \sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + attribute \src "ls180.v:1935.6-1935.10" + case + assign $0\sdram_bankmachine0_cmd_payload_a[12:0] $or$ls180.v:1936$131_Y + end sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + update \sdram_bankmachine0_cmd_payload_a $0\sdram_bankmachine0_cmd_payload_a[12:0] + end + attribute \src "ls180.v:1942.1-1949.4" + process $proc$ls180.v:1942$138 + assign { } { } + assign $0\sdram_bankmachine0_auto_precharge[0:0] 1'0 + attribute \src "ls180.v:1944.2-1948.5" + switch $and$ls180.v:1944$139_Y + attribute \src "ls180.v:1944.6-1944.105" + case 1'1 + attribute \src "ls180.v:1945.3-1947.6" + switch $ne$ls180.v:1945$140_Y + attribute \src "ls180.v:1945.7-1945.133" + case 1'1 + assign $0\sdram_bankmachine0_auto_precharge[0:0] $eq$ls180.v:1946$141_Y + case + end + case + end + sync always + update \sdram_bankmachine0_auto_precharge $0\sdram_bankmachine0_auto_precharge[0:0] end - attribute \src "ls180.v:453.11-453.73" - process $proc$ls180.v:453$3022 + attribute \src "ls180.v:196.11-196.24" + process $proc$ls180.v:196$1682 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + assign $1\ram_we[7:0] 8'00000000 sync always sync init - update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + update \ram_we $1\ram_we[7:0] end - attribute \src "ls180.v:4602.1-4695.4" - process $proc$ls180.v:4602$710 - assign { } { } + attribute \src "ls180.v:1964.1-1971.4" + process $proc$ls180.v:1964$142 assign { } { } + assign $0\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "ls180.v:1966.2-1970.5" + switch \sdram_bankmachine0_cmd_buffer_lookahead_replace + attribute \src "ls180.v:1966.6-1966.53" + case 1'1 + assign $0\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:1967$143_Y + attribute \src "ls180.v:1968.6-1968.10" + case + assign $0\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] \sdram_bankmachine0_cmd_buffer_lookahead_produce + end + sync always + update \sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $0\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:1980.1-2073.4" + process $proc$ls180.v:1980$151 assign { } { } assign { } { } assign { } { } @@ -290796,218 +264014,261 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdphy_cmdr_source_last[0:0] 1'0 - assign $0\main_sdphy_cmdr_source_payload_data[7:0] 8'00000000 - assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000 + assign $0\sdram_bankmachine0_refresh_gnt[0:0] 1'0 + assign $0\sdram_bankmachine0_cmd_valid[0:0] 1'0 assign { } { } - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 - assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'0 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 - assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'0 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 - assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 - assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'0 - assign $0\main_sdphy_cmdr_source_valid[0:0] 1'0 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] \builder_sdphy_sdphycmdr_state - attribute \src "ls180.v:4620.2-4694.9" - switch \builder_sdphy_sdphycmdr_state + assign $0\sdram_bankmachine0_row_open[0:0] 1'0 + assign $0\sdram_bankmachine0_row_close[0:0] 1'0 + assign $0\sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 + assign $0\sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 + assign $0\sdram_bankmachine0_cmd_payload_we[0:0] 1'0 + assign $0\sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 + assign $0\sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 + assign $0\sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 + assign $0\sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 + assign $0\sdram_bankmachine0_req_wdata_ready[0:0] 1'0 + assign $0\sdram_bankmachine0_req_rdata_valid[0:0] 1'0 + assign $0\subfragments_bankmachine0_next_state[2:0] \subfragments_bankmachine0_state + attribute \src "ls180.v:1996.2-2072.9" + switch \subfragments_bankmachine0_state attribute \src "ls180.v:0.0-0.0" case 3'001 - assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4628$711_Y - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4625.4-4627.7" - switch \main_sdphy_cmdr_cmdr_source_source_valid0 - attribute \src "ls180.v:4625.8-4625.49" - case 1'1 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:4630.4-4633.7" - switch $eq$ls180.v:4630$712_Y - attribute \src "ls180.v:4630.8-4630.41" - case 1'1 - assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_cmdr_source_valid[0:0] \main_sdphy_cmdr_cmdr_source_source_valid0 - assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'000 - assign $0\main_sdphy_cmdr_source_last[0:0] $eq$ls180.v:4639$714_Y - assign $0\main_sdphy_cmdr_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_source_source_payload_data0 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$ls180.v:4656$717_Y - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4641.4-4655.7" - switch $and$ls180.v:4641$715_Y - attribute \src "ls180.v:4641.8-4641.69" + assign $0\sdram_bankmachine0_row_close[0:0] 1'1 + attribute \src "ls180.v:1998.4-2006.7" + switch $and$ls180.v:1998$152_Y + attribute \src "ls180.v:1998.8-1998.77" case 1'1 - assign $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] 1'1 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4643$716_Y - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4645.5-4654.8" - switch \main_sdphy_cmdr_source_last - attribute \src "ls180.v:4645.9-4645.36" + assign $0\sdram_bankmachine0_cmd_valid[0:0] 1'1 + assign $0\sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 + assign $0\sdram_bankmachine0_cmd_payload_we[0:0] 1'1 + assign $0\sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:2000.5-2002.8" + switch \sdram_bankmachine0_cmd_ready + attribute \src "ls180.v:2000.9-2000.37" case 1'1 - assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 - attribute \src "ls180.v:4647.6-4653.9" - switch \main_sdphy_cmdr_sink_last - attribute \src "ls180.v:4647.10-4647.35" - case 1'1 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'011 - attribute \src "ls180.v:4651.10-4651.14" - case - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 - end + assign $0\subfragments_bankmachine0_next_state[2:0] 3'101 case end case end - attribute \src "ls180.v:4658.4-4661.7" - switch $eq$ls180.v:4658$718_Y - attribute \src "ls180.v:4658.8-4658.41" + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\sdram_bankmachine0_row_close[0:0] 1'1 + attribute \src "ls180.v:2010.4-2012.7" + switch $and$ls180.v:2010$153_Y + attribute \src "ls180.v:2010.8-2010.77" case 1'1 - assign $0\main_sdphy_cmdr_sink_ready[0:0] 1'1 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 + assign $0\subfragments_bankmachine0_next_state[2:0] 3'101 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - assign $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] 1'1 - assign $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] 1'1 - attribute \src "ls180.v:4667.4-4673.7" - switch \main_sdphy_cmdr_pads_out_ready - attribute \src "ls180.v:4667.8-4667.38" + attribute \src "ls180.v:2016.4-2025.7" + switch \sdram_bankmachine0_trccon_ready + attribute \src "ls180.v:2016.8-2016.39" case 1'1 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$ls180.v:4668$719_Y - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4670.5-4672.8" - switch $eq$ls180.v:4670$720_Y - attribute \src "ls180.v:4670.9-4670.40" + assign $0\sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'1 + assign $0\sdram_bankmachine0_row_open[0:0] 1'1 + assign $0\sdram_bankmachine0_cmd_valid[0:0] 1'1 + assign $0\sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 + assign $0\sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 + attribute \src "ls180.v:2021.5-2023.8" + switch \sdram_bankmachine0_cmd_ready + attribute \src "ls180.v:2021.9-2021.37" case 1'1 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 + assign $0\subfragments_bankmachine0_next_state[2:0] 3'110 case end case end attribute \src "ls180.v:0.0-0.0" case 3'100 - assign $0\main_sdphy_cmdr_source_valid[0:0] 1'1 - assign $0\main_sdphy_cmdr_source_payload_status[2:0] 3'001 - assign $0\main_sdphy_cmdr_source_last[0:0] 1'1 - attribute \src "ls180.v:4679.4-4681.7" - switch $and$ls180.v:4679$721_Y - attribute \src "ls180.v:4679.8-4679.69" + assign $0\sdram_bankmachine0_row_close[0:0] 1'1 + assign $0\sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:2028.4-2030.7" + switch \sdram_bankmachine0_twtpcon_ready + attribute \src "ls180.v:2028.8-2028.40" + case 1'1 + assign $0\sdram_bankmachine0_refresh_gnt[0:0] 1'1 + case + end + attribute \src "ls180.v:2033.4-2035.7" + switch $not$ls180.v:2033$154_Y + attribute \src "ls180.v:2033.8-2033.41" case 1'1 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 + assign $0\subfragments_bankmachine0_next_state[2:0] 3'000 case end attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\subfragments_bankmachine0_next_state[2:0] 3'011 + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\subfragments_bankmachine0_next_state[2:0] 3'000 + attribute \src "ls180.v:0.0-0.0" case - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 - assign $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 500000 - assign $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4688.4-4692.7" - switch $and$ls180.v:4688$723_Y - attribute \src "ls180.v:4688.8-4688.94" + attribute \src "ls180.v:2044.4-2070.7" + switch \sdram_bankmachine0_refresh_req + attribute \src "ls180.v:2044.8-2044.38" case 1'1 - assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'1 - assign $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 - assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'001 + assign $0\subfragments_bankmachine0_next_state[2:0] 3'100 + attribute \src "ls180.v:2046.8-2046.12" case + attribute \src "ls180.v:2047.5-2069.8" + switch \sdram_bankmachine0_cmd_buffer_source_valid + attribute \src "ls180.v:2047.9-2047.51" + case 1'1 + attribute \src "ls180.v:2048.6-2068.9" + switch \sdram_bankmachine0_row_opened + attribute \src "ls180.v:2048.10-2048.39" + case 1'1 + attribute \src "ls180.v:2049.7-2065.10" + switch \sdram_bankmachine0_row_hit + attribute \src "ls180.v:2049.11-2049.37" + case 1'1 + assign $0\sdram_bankmachine0_cmd_valid[0:0] 1'1 + assign $0\sdram_bankmachine0_cmd_payload_cas[0:0] 1'1 + attribute \src "ls180.v:2051.8-2058.11" + switch \sdram_bankmachine0_cmd_buffer_source_payload_we + attribute \src "ls180.v:2051.12-2051.59" + case 1'1 + assign $0\sdram_bankmachine0_req_wdata_ready[0:0] \sdram_bankmachine0_cmd_ready + assign $0\sdram_bankmachine0_cmd_payload_is_write[0:0] 1'1 + assign $0\sdram_bankmachine0_cmd_payload_we[0:0] 1'1 + attribute \src "ls180.v:2055.12-2055.16" + case + assign $0\sdram_bankmachine0_req_rdata_valid[0:0] \sdram_bankmachine0_cmd_ready + assign $0\sdram_bankmachine0_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "ls180.v:2060.8-2062.11" + switch $and$ls180.v:2060$155_Y + attribute \src "ls180.v:2060.12-2060.78" + case 1'1 + assign $0\subfragments_bankmachine0_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:2063.11-2063.15" + case + assign $0\subfragments_bankmachine0_next_state[2:0] 3'001 + end + attribute \src "ls180.v:2066.10-2066.14" + case + assign $0\subfragments_bankmachine0_next_state[2:0] 3'011 + end + case + end end end sync always - update \main_sdphy_cmdr_pads_out_payload_clk $0\main_sdphy_cmdr_pads_out_payload_clk[0:0] - update \main_sdphy_cmdr_pads_out_payload_cmd_o $0\main_sdphy_cmdr_pads_out_payload_cmd_o[0:0] - update \main_sdphy_cmdr_pads_out_payload_cmd_oe $0\main_sdphy_cmdr_pads_out_payload_cmd_oe[0:0] - update \main_sdphy_cmdr_sink_ready $0\main_sdphy_cmdr_sink_ready[0:0] - update \main_sdphy_cmdr_source_valid $0\main_sdphy_cmdr_source_valid[0:0] - update \main_sdphy_cmdr_source_last $0\main_sdphy_cmdr_source_last[0:0] - update \main_sdphy_cmdr_source_payload_data $0\main_sdphy_cmdr_source_payload_data[7:0] - update \main_sdphy_cmdr_source_payload_status $0\main_sdphy_cmdr_source_payload_status[2:0] - update \main_sdphy_cmdr_cmdr_source_source_ready0 $0\main_sdphy_cmdr_cmdr_source_source_ready0[0:0] - update \builder_sdphy_sdphycmdr_next_state $0\builder_sdphy_sdphycmdr_next_state[2:0] - update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] - update \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $0\main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] - update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] - update \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $0\main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] - update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] - update \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $0\main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] + update \sdram_bankmachine0_req_wdata_ready $0\sdram_bankmachine0_req_wdata_ready[0:0] + update \sdram_bankmachine0_req_rdata_valid $0\sdram_bankmachine0_req_rdata_valid[0:0] + update \sdram_bankmachine0_refresh_gnt $0\sdram_bankmachine0_refresh_gnt[0:0] + update \sdram_bankmachine0_cmd_valid $0\sdram_bankmachine0_cmd_valid[0:0] + update \sdram_bankmachine0_cmd_payload_cas $0\sdram_bankmachine0_cmd_payload_cas[0:0] + update \sdram_bankmachine0_cmd_payload_ras $0\sdram_bankmachine0_cmd_payload_ras[0:0] + update \sdram_bankmachine0_cmd_payload_we $0\sdram_bankmachine0_cmd_payload_we[0:0] + update \sdram_bankmachine0_cmd_payload_is_cmd $0\sdram_bankmachine0_cmd_payload_is_cmd[0:0] + update \sdram_bankmachine0_cmd_payload_is_read $0\sdram_bankmachine0_cmd_payload_is_read[0:0] + update \sdram_bankmachine0_cmd_payload_is_write $0\sdram_bankmachine0_cmd_payload_is_write[0:0] + update \sdram_bankmachine0_row_open $0\sdram_bankmachine0_row_open[0:0] + update \sdram_bankmachine0_row_close $0\sdram_bankmachine0_row_close[0:0] + update \sdram_bankmachine0_row_col_n_addr_sel $0\sdram_bankmachine0_row_col_n_addr_sel[0:0] + update \subfragments_bankmachine0_next_state $0\subfragments_bankmachine0_next_state[2:0] end - attribute \src "ls180.v:4729.1-4756.4" - process $proc$ls180.v:4729$731 - assign { } { } - assign { } { } + attribute \src "ls180.v:204.5-204.46" + process $proc$ls180.v:204$1683 assign { } { } + assign $1\interface0_converted_interface_ack[0:0] 1'0 + sync always + sync init + update \interface0_converted_interface_ack $1\interface0_converted_interface_ack[0:0] + end + attribute \src "ls180.v:208.5-208.46" + process $proc$ls180.v:208$1684 assign { } { } + assign $0\interface0_converted_interface_err[0:0] 1'0 + sync always + update \interface0_converted_interface_err $0\interface0_converted_interface_err[0:0] + sync init + end + attribute \src "ls180.v:2088.1-2095.4" + process $proc$ls180.v:2088$159 assign { } { } + assign $0\sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "ls180.v:2090.2-2094.5" + switch \sdram_bankmachine1_row_col_n_addr_sel + attribute \src "ls180.v:2090.6-2090.43" + case 1'1 + assign $0\sdram_bankmachine1_cmd_payload_a[12:0] \sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + attribute \src "ls180.v:2092.6-2092.10" + case + assign $0\sdram_bankmachine1_cmd_payload_a[12:0] $or$ls180.v:2093$161_Y + end + sync always + update \sdram_bankmachine1_cmd_payload_a $0\sdram_bankmachine1_cmd_payload_a[12:0] + end + attribute \src "ls180.v:209.5-209.27" + process $proc$ls180.v:209$1685 assign { } { } - assign $0\main_sdphy_dataw_valid[0:0] 1'0 - assign $0\main_sdphy_dataw_error[0:0] 1'0 + assign $1\converter0_skip[0:0] 1'0 + sync always + sync init + update \converter0_skip $1\converter0_skip[0:0] + end + attribute \src "ls180.v:2099.1-2106.4" + process $proc$ls180.v:2099$168 assign { } { } - assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 - assign $0\builder_sdphy_sdphycrcr_next_state[0:0] \builder_sdphy_sdphycrcr_state - attribute \src "ls180.v:4737.2-4755.9" - switch \builder_sdphy_sdphycrcr_state - attribute \src "ls180.v:0.0-0.0" + assign $0\sdram_bankmachine1_auto_precharge[0:0] 1'0 + attribute \src "ls180.v:2101.2-2105.5" + switch $and$ls180.v:2101$169_Y + attribute \src "ls180.v:2101.6-2101.105" case 1'1 - assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 - assign $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] 1'1 - attribute \src "ls180.v:4742.4-4746.7" - switch \main_sdphy_dataw_crcr_source_source_valid0 - attribute \src "ls180.v:4742.8-4742.50" + attribute \src "ls180.v:2102.3-2104.6" + switch $ne$ls180.v:2102$170_Y + attribute \src "ls180.v:2102.7-2102.133" case 1'1 - assign $0\main_sdphy_dataw_valid[0:0] $ne$ls180.v:4743$732_Y - assign $0\main_sdphy_dataw_error[0:0] $eq$ls180.v:4744$733_Y - assign $0\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 + assign $0\sdram_bankmachine1_auto_precharge[0:0] $eq$ls180.v:2103$171_Y case end - attribute \src "ls180.v:0.0-0.0" case - attribute \src "ls180.v:4749.4-4753.7" - switch \main_sdphy_dataw_start - attribute \src "ls180.v:4749.8-4749.30" - case 1'1 - assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'1 - assign $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 - assign $0\builder_sdphy_sdphycrcr_next_state[0:0] 1'1 - case - end end sync always - update \main_sdphy_dataw_valid $0\main_sdphy_dataw_valid[0:0] - update \main_sdphy_dataw_error $0\main_sdphy_dataw_error[0:0] - update \main_sdphy_dataw_crcr_source_source_ready0 $0\main_sdphy_dataw_crcr_source_source_ready0[0:0] - update \builder_sdphy_sdphycrcr_next_state $0\builder_sdphy_sdphycrcr_next_state[0:0] - update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] - update \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $0\main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] + update \sdram_bankmachine1_auto_precharge $0\sdram_bankmachine1_auto_precharge[0:0] + end + attribute \src "ls180.v:210.5-210.30" + process $proc$ls180.v:210$1686 + assign { } { } + assign $1\converter0_counter[0:0] 1'0 + sync always + sync init + update \converter0_counter $1\converter0_counter[0:0] end - attribute \src "ls180.v:474.5-474.59" - process $proc$ls180.v:474$3023 + attribute \src "ls180.v:212.12-212.36" + process $proc$ls180.v:212$1687 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 + assign $1\converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \main_sdram_bankmachine0_cmd_buffer_source_valid $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] + update \converter0_dat_r $1\converter0_dat_r[63:0] + end + attribute \src "ls180.v:2121.1-2128.4" + process $proc$ls180.v:2121$172 + assign { } { } + assign $0\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "ls180.v:2123.2-2127.5" + switch \sdram_bankmachine1_cmd_buffer_lookahead_replace + attribute \src "ls180.v:2123.6-2123.53" + case 1'1 + assign $0\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:2124$173_Y + attribute \src "ls180.v:2125.6-2125.10" + case + assign $0\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] \sdram_bankmachine1_cmd_buffer_lookahead_produce + end + sync always + update \sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $0\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:4757.1-4829.4" - process $proc$ls180.v:4757$734 + attribute \src "ls180.v:2137.1-2230.4" + process $proc$ls180.v:2137$181 assign { } { } assign { } { } assign { } { } @@ -291017,198 +264278,266 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 - assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'0 - assign $0\main_sdphy_dataw_sink_ready[0:0] 1'0 assign { } { } - assign $0\main_sdphy_dataw_start[0:0] 1'0 - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 - assign $0\main_sdphy_dataw_stop[0:0] 1'0 - assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'0 - assign $0\builder_sdphy_fsm_next_state[2:0] \builder_sdphy_fsm_state - attribute \src "ls180.v:4768.2-4828.9" - switch \builder_sdphy_fsm_state + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 + assign { } { } + assign $0\sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 + assign $0\sdram_bankmachine1_req_wdata_ready[0:0] 1'0 + assign $0\sdram_bankmachine1_req_rdata_valid[0:0] 1'0 + assign $0\sdram_bankmachine1_refresh_gnt[0:0] 1'0 + assign $0\sdram_bankmachine1_cmd_valid[0:0] 1'0 + assign $0\sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 + assign $0\sdram_bankmachine1_row_open[0:0] 1'0 + assign $0\sdram_bankmachine1_row_close[0:0] 1'0 + assign $0\sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 + assign $0\sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 + assign $0\sdram_bankmachine1_cmd_payload_we[0:0] 1'0 + assign $0\sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 + assign $0\subfragments_bankmachine1_next_state[2:0] \subfragments_bankmachine1_state + attribute \src "ls180.v:2153.2-2229.9" + switch \subfragments_bankmachine1_state attribute \src "ls180.v:0.0-0.0" case 3'001 - assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 - assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'0000 - attribute \src "ls180.v:4773.4-4775.7" - switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4773.8-4773.39" + assign $0\sdram_bankmachine1_row_close[0:0] 1'1 + attribute \src "ls180.v:2155.4-2163.7" + switch $and$ls180.v:2155$182_Y + attribute \src "ls180.v:2155.8-2155.77" case 1'1 - assign $0\builder_sdphy_fsm_next_state[2:0] 3'010 + assign $0\sdram_bankmachine1_cmd_valid[0:0] 1'1 + assign $0\sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 + assign $0\sdram_bankmachine1_cmd_payload_we[0:0] 1'1 + assign $0\sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:2157.5-2159.8" + switch \sdram_bankmachine1_cmd_ready + attribute \src "ls180.v:2157.9-2157.37" + case 1'1 + assign $0\subfragments_bankmachine1_next_state[2:0] 3'101 + case + end case end attribute \src "ls180.v:0.0-0.0" case 3'010 - assign $0\main_sdphy_dataw_stop[0:0] $not$ls180.v:4778$735_Y - assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 - attribute \src "ls180.v:4781.4-4788.11" - switch \main_sdphy_dataw_count - attribute \src "ls180.v:0.0-0.0" - case 8'00000000 - assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] \main_sdphy_dataw_sink_payload_data [7:4] - attribute \src "ls180.v:0.0-0.0" - case 8'00000001 - assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] \main_sdphy_dataw_sink_payload_data [3:0] + assign $0\sdram_bankmachine1_row_close[0:0] 1'1 + attribute \src "ls180.v:2167.4-2169.7" + switch $and$ls180.v:2167$183_Y + attribute \src "ls180.v:2167.8-2167.77" + case 1'1 + assign $0\subfragments_bankmachine1_next_state[2:0] 3'101 case end - attribute \src "ls180.v:4789.4-4801.7" - switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4789.8-4789.39" + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:2173.4-2182.7" + switch \sdram_bankmachine1_trccon_ready + attribute \src "ls180.v:2173.8-2173.39" case 1'1 - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] $add$ls180.v:4790$736_Y - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4792.5-4800.8" - switch $eq$ls180.v:4792$737_Y - attribute \src "ls180.v:4792.9-4792.41" + assign $0\sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'1 + assign $0\sdram_bankmachine1_row_open[0:0] 1'1 + assign $0\sdram_bankmachine1_cmd_valid[0:0] 1'1 + assign $0\sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 + assign $0\sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 + attribute \src "ls180.v:2178.5-2180.8" + switch \sdram_bankmachine1_cmd_ready + attribute \src "ls180.v:2178.9-2178.37" case 1'1 - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4795.6-4799.9" - switch \main_sdphy_dataw_sink_last - attribute \src "ls180.v:4795.10-4795.36" - case 1'1 - assign $0\builder_sdphy_fsm_next_state[2:0] 3'011 - attribute \src "ls180.v:4797.10-4797.14" - case - assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1 - end + assign $0\subfragments_bankmachine1_next_state[2:0] 3'110 case end case end attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] 1'1 - assign $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] 4'1111 - attribute \src "ls180.v:4807.4-4810.7" - switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4807.8-4807.39" + case 3'100 + assign $0\sdram_bankmachine1_row_close[0:0] 1'1 + assign $0\sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:2185.4-2187.7" + switch \sdram_bankmachine1_twtpcon_ready + attribute \src "ls180.v:2185.8-2185.40" case 1'1 - assign $0\main_sdphy_dataw_start[0:0] 1'1 - assign $0\builder_sdphy_fsm_next_state[2:0] 3'100 + assign $0\sdram_bankmachine1_refresh_gnt[0:0] 1'1 case end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdphy_dataw_pads_out_payload_clk[0:0] 1'1 - attribute \src "ls180.v:4814.4-4819.7" - switch \main_sdphy_dataw_pads_out_ready - attribute \src "ls180.v:4814.8-4814.39" + attribute \src "ls180.v:2190.4-2192.7" + switch $not$ls180.v:2190$184_Y + attribute \src "ls180.v:2190.8-2190.41" case 1'1 - attribute \src "ls180.v:4815.5-4818.8" - switch \main_sdphy_dataw_pads_in_payload_data_i [0] - attribute \src "ls180.v:4815.9-4815.51" - case 1'1 - assign $0\main_sdphy_dataw_sink_ready[0:0] 1'1 - assign $0\builder_sdphy_fsm_next_state[2:0] 3'000 - case - end + assign $0\subfragments_bankmachine1_next_state[2:0] 3'000 case end attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\subfragments_bankmachine1_next_state[2:0] 3'011 + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\subfragments_bankmachine1_next_state[2:0] 3'000 + attribute \src "ls180.v:0.0-0.0" case - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 - assign $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:4824.4-4826.7" - switch $and$ls180.v:4824$738_Y - attribute \src "ls180.v:4824.8-4824.71" + attribute \src "ls180.v:2201.4-2227.7" + switch \sdram_bankmachine1_refresh_req + attribute \src "ls180.v:2201.8-2201.38" case 1'1 - assign $0\builder_sdphy_fsm_next_state[2:0] 3'001 + assign $0\subfragments_bankmachine1_next_state[2:0] 3'100 + attribute \src "ls180.v:2203.8-2203.12" case + attribute \src "ls180.v:2204.5-2226.8" + switch \sdram_bankmachine1_cmd_buffer_source_valid + attribute \src "ls180.v:2204.9-2204.51" + case 1'1 + attribute \src "ls180.v:2205.6-2225.9" + switch \sdram_bankmachine1_row_opened + attribute \src "ls180.v:2205.10-2205.39" + case 1'1 + attribute \src "ls180.v:2206.7-2222.10" + switch \sdram_bankmachine1_row_hit + attribute \src "ls180.v:2206.11-2206.37" + case 1'1 + assign $0\sdram_bankmachine1_cmd_valid[0:0] 1'1 + assign $0\sdram_bankmachine1_cmd_payload_cas[0:0] 1'1 + attribute \src "ls180.v:2208.8-2215.11" + switch \sdram_bankmachine1_cmd_buffer_source_payload_we + attribute \src "ls180.v:2208.12-2208.59" + case 1'1 + assign $0\sdram_bankmachine1_req_wdata_ready[0:0] \sdram_bankmachine1_cmd_ready + assign $0\sdram_bankmachine1_cmd_payload_is_write[0:0] 1'1 + assign $0\sdram_bankmachine1_cmd_payload_we[0:0] 1'1 + attribute \src "ls180.v:2212.12-2212.16" + case + assign $0\sdram_bankmachine1_req_rdata_valid[0:0] \sdram_bankmachine1_cmd_ready + assign $0\sdram_bankmachine1_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "ls180.v:2217.8-2219.11" + switch $and$ls180.v:2217$185_Y + attribute \src "ls180.v:2217.12-2217.78" + case 1'1 + assign $0\subfragments_bankmachine1_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:2220.11-2220.15" + case + assign $0\subfragments_bankmachine1_next_state[2:0] 3'001 + end + attribute \src "ls180.v:2223.10-2223.14" + case + assign $0\subfragments_bankmachine1_next_state[2:0] 3'011 + end + case + end end end sync always - update \main_sdphy_dataw_pads_out_payload_clk $0\main_sdphy_dataw_pads_out_payload_clk[0:0] - update \main_sdphy_dataw_pads_out_payload_data_o $0\main_sdphy_dataw_pads_out_payload_data_o[3:0] - update \main_sdphy_dataw_pads_out_payload_data_oe $0\main_sdphy_dataw_pads_out_payload_data_oe[0:0] - update \main_sdphy_dataw_sink_ready $0\main_sdphy_dataw_sink_ready[0:0] - update \main_sdphy_dataw_stop $0\main_sdphy_dataw_stop[0:0] - update \main_sdphy_dataw_start $0\main_sdphy_dataw_start[0:0] - update \builder_sdphy_fsm_next_state $0\builder_sdphy_fsm_next_state[2:0] - update \main_sdphy_dataw_count_sdphy_fsm_next_value $0\main_sdphy_dataw_count_sdphy_fsm_next_value[7:0] - update \main_sdphy_dataw_count_sdphy_fsm_next_value_ce $0\main_sdphy_dataw_count_sdphy_fsm_next_value_ce[0:0] - end - attribute \src "ls180.v:476.5-476.59" - process $proc$ls180.v:476$3024 - assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_cmd_buffer_source_first $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] + update \sdram_bankmachine1_req_wdata_ready $0\sdram_bankmachine1_req_wdata_ready[0:0] + update \sdram_bankmachine1_req_rdata_valid $0\sdram_bankmachine1_req_rdata_valid[0:0] + update \sdram_bankmachine1_refresh_gnt $0\sdram_bankmachine1_refresh_gnt[0:0] + update \sdram_bankmachine1_cmd_valid $0\sdram_bankmachine1_cmd_valid[0:0] + update \sdram_bankmachine1_cmd_payload_cas $0\sdram_bankmachine1_cmd_payload_cas[0:0] + update \sdram_bankmachine1_cmd_payload_ras $0\sdram_bankmachine1_cmd_payload_ras[0:0] + update \sdram_bankmachine1_cmd_payload_we $0\sdram_bankmachine1_cmd_payload_we[0:0] + update \sdram_bankmachine1_cmd_payload_is_cmd $0\sdram_bankmachine1_cmd_payload_is_cmd[0:0] + update \sdram_bankmachine1_cmd_payload_is_read $0\sdram_bankmachine1_cmd_payload_is_read[0:0] + update \sdram_bankmachine1_cmd_payload_is_write $0\sdram_bankmachine1_cmd_payload_is_write[0:0] + update \sdram_bankmachine1_row_open $0\sdram_bankmachine1_row_open[0:0] + update \sdram_bankmachine1_row_close $0\sdram_bankmachine1_row_close[0:0] + update \sdram_bankmachine1_row_col_n_addr_sel $0\sdram_bankmachine1_row_col_n_addr_sel[0:0] + update \subfragments_bankmachine1_next_state $0\subfragments_bankmachine1_next_state[2:0] end - attribute \src "ls180.v:477.5-477.58" - process $proc$ls180.v:477$3025 + attribute \src "ls180.v:219.5-219.46" + process $proc$ls180.v:219$1688 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0 + assign $1\interface1_converted_interface_ack[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_buffer_source_last $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] + update \interface1_converted_interface_ack $1\interface1_converted_interface_ack[0:0] end - attribute \src "ls180.v:478.5-478.64" - process $proc$ls180.v:478$3026 + attribute \src "ls180.v:223.5-223.46" + process $proc$ls180.v:223$1689 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0 + assign $0\interface1_converted_interface_err[0:0] 1'0 sync always + update \interface1_converted_interface_err $0\interface1_converted_interface_err[0:0] sync init - update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] end - attribute \src "ls180.v:479.12-479.74" - process $proc$ls180.v:479$3027 + attribute \src "ls180.v:224.5-224.27" + process $proc$ls180.v:224$1690 assign { } { } - assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + assign $1\converter1_skip[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + update \converter1_skip $1\converter1_skip[0:0] end - attribute \src "ls180.v:480.12-480.47" - process $proc$ls180.v:480$3028 + attribute \src "ls180.v:2245.1-2252.4" + process $proc$ls180.v:2245$189 assign { } { } - assign $1\main_sdram_bankmachine0_row[12:0] 13'0000000000000 + assign $0\sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "ls180.v:2247.2-2251.5" + switch \sdram_bankmachine2_row_col_n_addr_sel + attribute \src "ls180.v:2247.6-2247.43" + case 1'1 + assign $0\sdram_bankmachine2_cmd_payload_a[12:0] \sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + attribute \src "ls180.v:2249.6-2249.10" + case + assign $0\sdram_bankmachine2_cmd_payload_a[12:0] $or$ls180.v:2250$191_Y + end sync always - sync init - update \main_sdram_bankmachine0_row $1\main_sdram_bankmachine0_row[12:0] + update \sdram_bankmachine2_cmd_payload_a $0\sdram_bankmachine2_cmd_payload_a[12:0] end - attribute \src "ls180.v:481.5-481.46" - process $proc$ls180.v:481$3029 + attribute \src "ls180.v:225.5-225.30" + process $proc$ls180.v:225$1691 assign { } { } - assign $1\main_sdram_bankmachine0_row_opened[0:0] 1'0 + assign $1\converter1_counter[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine0_row_opened $1\main_sdram_bankmachine0_row_opened[0:0] + update \converter1_counter $1\converter1_counter[0:0] end - attribute \src "ls180.v:483.5-483.44" - process $proc$ls180.v:483$3030 + attribute \src "ls180.v:2256.1-2263.4" + process $proc$ls180.v:2256$198 assign { } { } - assign $1\main_sdram_bankmachine0_row_open[0:0] 1'0 + assign $0\sdram_bankmachine2_auto_precharge[0:0] 1'0 + attribute \src "ls180.v:2258.2-2262.5" + switch $and$ls180.v:2258$199_Y + attribute \src "ls180.v:2258.6-2258.105" + case 1'1 + attribute \src "ls180.v:2259.3-2261.6" + switch $ne$ls180.v:2259$200_Y + attribute \src "ls180.v:2259.7-2259.133" + case 1'1 + assign $0\sdram_bankmachine2_auto_precharge[0:0] $eq$ls180.v:2260$201_Y + case + end + case + end sync always - sync init - update \main_sdram_bankmachine0_row_open $1\main_sdram_bankmachine0_row_open[0:0] + update \sdram_bankmachine2_auto_precharge $0\sdram_bankmachine2_auto_precharge[0:0] end - attribute \src "ls180.v:484.5-484.45" - process $proc$ls180.v:484$3031 + attribute \src "ls180.v:227.12-227.36" + process $proc$ls180.v:227$1692 assign { } { } - assign $1\main_sdram_bankmachine0_row_close[0:0] 1'0 + assign $1\converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \main_sdram_bankmachine0_row_close $1\main_sdram_bankmachine0_row_close[0:0] + update \converter1_dat_r $1\converter1_dat_r[63:0] end - attribute \src "ls180.v:485.5-485.54" - process $proc$ls180.v:485$3032 + attribute \src "ls180.v:2278.1-2285.4" + process $proc$ls180.v:2278$202 assign { } { } - assign $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 + assign $0\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "ls180.v:2280.2-2284.5" + switch \sdram_bankmachine2_cmd_buffer_lookahead_replace + attribute \src "ls180.v:2280.6-2280.53" + case 1'1 + assign $0\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:2281$203_Y + attribute \src "ls180.v:2282.6-2282.10" + case + assign $0\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] \sdram_bankmachine2_cmd_buffer_lookahead_produce + end sync always - sync init - update \main_sdram_bankmachine0_row_col_n_addr_sel $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + update \sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $0\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:4863.1-4964.4" - process $proc$ls180.v:4863$746 - assign { } { } + attribute \src "ls180.v:2294.1-2387.4" + process $proc$ls180.v:2294$211 assign { } { } assign { } { } assign { } { } @@ -291223,358 +264552,229 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 - assign $0\main_sdphy_datar_stop[0:0] 1'0 - assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'0 - assign $0\main_sdphy_datar_sink_ready[0:0] 1'0 + assign $0\sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 + assign $0\sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 + assign $0\sdram_bankmachine2_cmd_payload_we[0:0] 1'0 + assign $0\sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 + assign $0\sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 + assign $0\sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 + assign $0\sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 + assign $0\sdram_bankmachine2_req_wdata_ready[0:0] 1'0 + assign $0\sdram_bankmachine2_req_rdata_valid[0:0] 1'0 + assign $0\sdram_bankmachine2_refresh_gnt[0:0] 1'0 + assign $0\sdram_bankmachine2_cmd_valid[0:0] 1'0 + assign $0\sdram_bankmachine2_row_close[0:0] 1'0 + assign $0\sdram_bankmachine2_row_open[0:0] 1'0 assign { } { } - assign $0\main_sdphy_datar_source_payload_data[7:0] 8'00000000 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 - assign $0\main_sdphy_datar_source_valid[0:0] 1'0 - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 - assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 - assign $0\main_sdphy_datar_source_last[0:0] 1'0 - assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'0 - assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] \builder_sdphy_sdphydatar_state - attribute \src "ls180.v:4880.2-4963.9" - switch \builder_sdphy_sdphydatar_state + assign $0\subfragments_bankmachine2_next_state[2:0] \subfragments_bankmachine2_state + attribute \src "ls180.v:2310.2-2386.9" + switch \subfragments_bankmachine2_state attribute \src "ls180.v:0.0-0.0" case 3'001 - assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 - assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'1 - assign { } { } - assign { } { } - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4890$748_Y - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4887.4-4889.7" - switch \main_sdphy_datar_datar_source_source_valid0 - attribute \src "ls180.v:4887.8-4887.51" - case 1'1 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'010 - case - end - attribute \src "ls180.v:4892.4-4895.7" - switch $eq$ls180.v:4892$749_Y - attribute \src "ls180.v:4892.8-4892.42" - case 1'1 - assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 - assign $0\main_sdphy_datar_source_valid[0:0] \main_sdphy_datar_datar_source_source_valid0 - assign $0\main_sdphy_datar_source_payload_status[2:0] 3'000 - assign $0\main_sdphy_datar_source_last[0:0] $eq$ls180.v:4901$752_Y - assign $0\main_sdphy_datar_source_payload_data[7:0] \main_sdphy_datar_datar_source_source_payload_data0 - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$ls180.v:4922$754_Y - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 - attribute \src "ls180.v:4903.4-4921.7" - switch \main_sdphy_datar_source_valid - attribute \src "ls180.v:4903.8-4903.37" + assign $0\sdram_bankmachine2_row_close[0:0] 1'1 + attribute \src "ls180.v:2312.4-2320.7" + switch $and$ls180.v:2312$212_Y + attribute \src "ls180.v:2312.8-2312.77" case 1'1 - attribute \src "ls180.v:4904.5-4920.8" - switch \main_sdphy_datar_source_ready - attribute \src "ls180.v:4904.9-4904.38" + assign $0\sdram_bankmachine2_cmd_valid[0:0] 1'1 + assign $0\sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 + assign $0\sdram_bankmachine2_cmd_payload_we[0:0] 1'1 + assign $0\sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:2314.5-2316.8" + switch \sdram_bankmachine2_cmd_ready + attribute \src "ls180.v:2314.9-2314.37" case 1'1 - assign $0\main_sdphy_datar_datar_source_source_ready0[0:0] 1'1 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4906$753_Y - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4908.6-4917.9" - switch \main_sdphy_datar_source_last - attribute \src "ls180.v:4908.10-4908.38" - case 1'1 - assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 - attribute \src "ls180.v:4910.7-4916.10" - switch \main_sdphy_datar_sink_last - attribute \src "ls180.v:4910.11-4910.37" - case 1'1 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'011 - attribute \src "ls180.v:4914.11-4914.15" - case - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 - end - case - end - attribute \src "ls180.v:4918.9-4918.13" + assign $0\subfragments_bankmachine2_next_state[2:0] 3'101 case - assign $0\main_sdphy_datar_stop[0:0] 1'1 end case end - attribute \src "ls180.v:4924.4-4927.7" - switch $eq$ls180.v:4924$755_Y - attribute \src "ls180.v:4924.8-4924.42" + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\sdram_bankmachine2_row_close[0:0] 1'1 + attribute \src "ls180.v:2324.4-2326.7" + switch $and$ls180.v:2324$213_Y + attribute \src "ls180.v:2324.8-2324.77" case 1'1 - assign $0\main_sdphy_datar_sink_ready[0:0] 1'1 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 + assign $0\subfragments_bankmachine2_next_state[2:0] 3'101 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 - attribute \src "ls180.v:4931.4-4937.7" - switch \main_sdphy_datar_pads_out_ready - attribute \src "ls180.v:4931.8-4931.39" + attribute \src "ls180.v:2330.4-2339.7" + switch \sdram_bankmachine2_trccon_ready + attribute \src "ls180.v:2330.8-2330.39" case 1'1 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$ls180.v:4932$756_Y - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4934.5-4936.8" - switch $eq$ls180.v:4934$757_Y - attribute \src "ls180.v:4934.9-4934.42" + assign $0\sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'1 + assign $0\sdram_bankmachine2_row_open[0:0] 1'1 + assign $0\sdram_bankmachine2_cmd_valid[0:0] 1'1 + assign $0\sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 + assign $0\sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 + attribute \src "ls180.v:2335.5-2337.8" + switch \sdram_bankmachine2_cmd_ready + attribute \src "ls180.v:2335.9-2335.37" case 1'1 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 + assign $0\subfragments_bankmachine2_next_state[2:0] 3'110 case end case end attribute \src "ls180.v:0.0-0.0" case 3'100 - assign $0\main_sdphy_datar_source_valid[0:0] 1'1 - assign $0\main_sdphy_datar_source_payload_status[2:0] 3'001 - assign $0\main_sdphy_datar_source_last[0:0] 1'1 - attribute \src "ls180.v:4943.4-4945.7" - switch $and$ls180.v:4943$758_Y - attribute \src "ls180.v:4943.8-4943.71" + assign $0\sdram_bankmachine2_row_close[0:0] 1'1 + assign $0\sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:2342.4-2344.7" + switch \sdram_bankmachine2_twtpcon_ready + attribute \src "ls180.v:2342.8-2342.40" + case 1'1 + assign $0\sdram_bankmachine2_refresh_gnt[0:0] 1'1 + case + end + attribute \src "ls180.v:2347.4-2349.7" + switch $not$ls180.v:2347$214_Y + attribute \src "ls180.v:2347.8-2347.41" case 1'1 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 + assign $0\subfragments_bankmachine2_next_state[2:0] 3'000 case end attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\subfragments_bankmachine2_next_state[2:0] 3'011 + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\subfragments_bankmachine2_next_state[2:0] 3'000 + attribute \src "ls180.v:0.0-0.0" case - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:4950.4-4961.7" - switch $and$ls180.v:4950$759_Y - attribute \src "ls180.v:4950.8-4950.71" + attribute \src "ls180.v:2358.4-2384.7" + switch \sdram_bankmachine2_refresh_req + attribute \src "ls180.v:2358.8-2358.38" case 1'1 - assign $0\main_sdphy_datar_pads_out_payload_clk[0:0] 1'1 - attribute \src "ls180.v:4952.5-4960.8" - switch \main_sdphy_datar_pads_out_ready - attribute \src "ls180.v:4952.9-4952.40" + assign $0\subfragments_bankmachine2_next_state[2:0] 3'100 + attribute \src "ls180.v:2360.8-2360.12" + case + attribute \src "ls180.v:2361.5-2383.8" + switch \sdram_bankmachine2_cmd_buffer_source_valid + attribute \src "ls180.v:2361.9-2361.51" case 1'1 - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 500000 - assign $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 - assign $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 - assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'1 - assign $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'1 - assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'001 + attribute \src "ls180.v:2362.6-2382.9" + switch \sdram_bankmachine2_row_opened + attribute \src "ls180.v:2362.10-2362.39" + case 1'1 + attribute \src "ls180.v:2363.7-2379.10" + switch \sdram_bankmachine2_row_hit + attribute \src "ls180.v:2363.11-2363.37" + case 1'1 + assign $0\sdram_bankmachine2_cmd_valid[0:0] 1'1 + assign $0\sdram_bankmachine2_cmd_payload_cas[0:0] 1'1 + attribute \src "ls180.v:2365.8-2372.11" + switch \sdram_bankmachine2_cmd_buffer_source_payload_we + attribute \src "ls180.v:2365.12-2365.59" + case 1'1 + assign $0\sdram_bankmachine2_req_wdata_ready[0:0] \sdram_bankmachine2_cmd_ready + assign $0\sdram_bankmachine2_cmd_payload_is_write[0:0] 1'1 + assign $0\sdram_bankmachine2_cmd_payload_we[0:0] 1'1 + attribute \src "ls180.v:2369.12-2369.16" + case + assign $0\sdram_bankmachine2_req_rdata_valid[0:0] \sdram_bankmachine2_cmd_ready + assign $0\sdram_bankmachine2_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "ls180.v:2374.8-2376.11" + switch $and$ls180.v:2374$215_Y + attribute \src "ls180.v:2374.12-2374.78" + case 1'1 + assign $0\subfragments_bankmachine2_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:2377.11-2377.15" + case + assign $0\subfragments_bankmachine2_next_state[2:0] 3'001 + end + attribute \src "ls180.v:2380.10-2380.14" + case + assign $0\subfragments_bankmachine2_next_state[2:0] 3'011 + end case end - case end end sync always - update \main_sdphy_datar_pads_out_payload_clk $0\main_sdphy_datar_pads_out_payload_clk[0:0] - update \main_sdphy_datar_sink_ready $0\main_sdphy_datar_sink_ready[0:0] - update \main_sdphy_datar_source_valid $0\main_sdphy_datar_source_valid[0:0] - update \main_sdphy_datar_source_last $0\main_sdphy_datar_source_last[0:0] - update \main_sdphy_datar_source_payload_data $0\main_sdphy_datar_source_payload_data[7:0] - update \main_sdphy_datar_source_payload_status $0\main_sdphy_datar_source_payload_status[2:0] - update \main_sdphy_datar_stop $0\main_sdphy_datar_stop[0:0] - update \main_sdphy_datar_datar_source_source_ready0 $0\main_sdphy_datar_datar_source_source_ready0[0:0] - update \builder_sdphy_sdphydatar_next_state $0\builder_sdphy_sdphydatar_next_state[2:0] - update \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value0[9:0] - update \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 $0\main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] - update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1[31:0] - update \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 $0\main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] - update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] - update \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $0\main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] - end - attribute \src "ls180.v:487.32-487.76" - process $proc$ls180.v:487$3033 - assign { } { } - assign $1\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine0_twtpcon_ready $1\main_sdram_bankmachine0_twtpcon_ready[0:0] - end - attribute \src "ls180.v:488.11-488.55" - process $proc$ls180.v:488$3034 - assign { } { } - assign $1\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine0_twtpcon_count $1\main_sdram_bankmachine0_twtpcon_count[2:0] - end - attribute \src "ls180.v:490.32-490.75" - process $proc$ls180.v:490$3035 - assign { } { } - assign $0\main_sdram_bankmachine0_trccon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine0_trccon_ready $0\main_sdram_bankmachine0_trccon_ready[0:0] - sync init - end - attribute \src "ls180.v:492.32-492.76" - process $proc$ls180.v:492$3036 - assign { } { } - assign $0\main_sdram_bankmachine0_trascon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine0_trascon_ready $0\main_sdram_bankmachine0_trascon_ready[0:0] - sync init - end - attribute \src "ls180.v:498.5-498.51" - process $proc$ls180.v:498$3037 - assign { } { } - assign $1\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_req_wdata_ready $1\main_sdram_bankmachine1_req_wdata_ready[0:0] - end - attribute \src "ls180.v:499.5-499.51" - process $proc$ls180.v:499$3038 - assign { } { } - assign $1\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_req_rdata_valid $1\main_sdram_bankmachine1_req_rdata_valid[0:0] - end - attribute \src "ls180.v:501.5-501.47" - process $proc$ls180.v:501$3039 - assign { } { } - assign $1\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_refresh_gnt $1\main_sdram_bankmachine1_refresh_gnt[0:0] - end - attribute \src "ls180.v:502.5-502.45" - process $proc$ls180.v:502$3040 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_valid $1\main_sdram_bankmachine1_cmd_valid[0:0] - end - attribute \src "ls180.v:5022.1-5029.4" - process $proc$ls180.v:5022$881 - assign { } { } - assign $0\main_sdcore_crc7_inserter_crc[6:0] 7'0000000 - attribute \src "ls180.v:5024.2-5028.5" - switch \main_sdcore_crc7_inserter_enable - attribute \src "ls180.v:5024.6-5024.38" - case 1'1 - assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg40 - attribute \src "ls180.v:5026.6-5026.10" - case - assign $0\main_sdcore_crc7_inserter_crc[6:0] \main_sdcore_crc7_inserter_crcreg0 - end - sync always - update \main_sdcore_crc7_inserter_crc $0\main_sdcore_crc7_inserter_crc[6:0] - end - attribute \src "ls180.v:503.5-503.45" - process $proc$ls180.v:503$3041 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_ready $1\main_sdram_bankmachine1_cmd_ready[0:0] + update \sdram_bankmachine2_req_wdata_ready $0\sdram_bankmachine2_req_wdata_ready[0:0] + update \sdram_bankmachine2_req_rdata_valid $0\sdram_bankmachine2_req_rdata_valid[0:0] + update \sdram_bankmachine2_refresh_gnt $0\sdram_bankmachine2_refresh_gnt[0:0] + update \sdram_bankmachine2_cmd_valid $0\sdram_bankmachine2_cmd_valid[0:0] + update \sdram_bankmachine2_cmd_payload_cas $0\sdram_bankmachine2_cmd_payload_cas[0:0] + update \sdram_bankmachine2_cmd_payload_ras $0\sdram_bankmachine2_cmd_payload_ras[0:0] + update \sdram_bankmachine2_cmd_payload_we $0\sdram_bankmachine2_cmd_payload_we[0:0] + update \sdram_bankmachine2_cmd_payload_is_cmd $0\sdram_bankmachine2_cmd_payload_is_cmd[0:0] + update \sdram_bankmachine2_cmd_payload_is_read $0\sdram_bankmachine2_cmd_payload_is_read[0:0] + update \sdram_bankmachine2_cmd_payload_is_write $0\sdram_bankmachine2_cmd_payload_is_write[0:0] + update \sdram_bankmachine2_row_open $0\sdram_bankmachine2_row_open[0:0] + update \sdram_bankmachine2_row_close $0\sdram_bankmachine2_row_close[0:0] + update \sdram_bankmachine2_row_col_n_addr_sel $0\sdram_bankmachine2_row_col_n_addr_sel[0:0] + update \subfragments_bankmachine2_next_state $0\subfragments_bankmachine2_next_state[2:0] end - attribute \src "ls180.v:504.12-504.57" - process $proc$ls180.v:504$3042 + attribute \src "ls180.v:231.5-231.19" + process $proc$ls180.v:231$1693 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 + assign $1\int_rst[0:0] 1'1 sync always sync init - update \main_sdram_bankmachine1_cmd_payload_a $1\main_sdram_bankmachine1_cmd_payload_a[12:0] - end - attribute \src "ls180.v:5044.1-5051.4" - process $proc$ls180.v:5044$904 - assign { } { } - assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5046.2-5050.5" - switch \main_sdcore_crc16_inserter_crc0_enable - attribute \src "ls180.v:5046.6-5046.44" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2 - attribute \src "ls180.v:5048.6-5048.10" - case - assign $0\main_sdcore_crc16_inserter_crc0_crc[15:0] \main_sdcore_crc16_inserter_crc0_crcreg0 - end - sync always - update \main_sdcore_crc16_inserter_crc0_crc $0\main_sdcore_crc16_inserter_crc0_crc[15:0] + update \int_rst $1\int_rst[0:0] end - attribute \src "ls180.v:5054.1-5061.4" - process $proc$ls180.v:5054$915 + attribute \src "ls180.v:2402.1-2409.4" + process $proc$ls180.v:2402$219 assign { } { } - assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5056.2-5060.5" - switch \main_sdcore_crc16_inserter_crc1_enable - attribute \src "ls180.v:5056.6-5056.44" + assign $0\sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "ls180.v:2404.2-2408.5" + switch \sdram_bankmachine3_row_col_n_addr_sel + attribute \src "ls180.v:2404.6-2404.43" case 1'1 - assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2 - attribute \src "ls180.v:5058.6-5058.10" + assign $0\sdram_bankmachine3_cmd_payload_a[12:0] \sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + attribute \src "ls180.v:2406.6-2406.10" case - assign $0\main_sdcore_crc16_inserter_crc1_crc[15:0] \main_sdcore_crc16_inserter_crc1_crcreg0 + assign $0\sdram_bankmachine3_cmd_payload_a[12:0] $or$ls180.v:2407$221_Y end sync always - update \main_sdcore_crc16_inserter_crc1_crc $0\main_sdcore_crc16_inserter_crc1_crc[15:0] - end - attribute \src "ls180.v:506.5-506.51" - process $proc$ls180.v:506$3043 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_cas $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] + update \sdram_bankmachine3_cmd_payload_a $0\sdram_bankmachine3_cmd_payload_a[12:0] end - attribute \src "ls180.v:5064.1-5071.4" - process $proc$ls180.v:5064$926 + attribute \src "ls180.v:2413.1-2420.4" + process $proc$ls180.v:2413$228 assign { } { } - assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5066.2-5070.5" - switch \main_sdcore_crc16_inserter_crc2_enable - attribute \src "ls180.v:5066.6-5066.44" + assign $0\sdram_bankmachine3_auto_precharge[0:0] 1'0 + attribute \src "ls180.v:2415.2-2419.5" + switch $and$ls180.v:2415$229_Y + attribute \src "ls180.v:2415.6-2415.105" case 1'1 - assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2 - attribute \src "ls180.v:5068.6-5068.10" + attribute \src "ls180.v:2416.3-2418.6" + switch $ne$ls180.v:2416$230_Y + attribute \src "ls180.v:2416.7-2416.133" + case 1'1 + assign $0\sdram_bankmachine3_auto_precharge[0:0] $eq$ls180.v:2417$231_Y + case + end case - assign $0\main_sdcore_crc16_inserter_crc2_crc[15:0] \main_sdcore_crc16_inserter_crc2_crcreg0 end sync always - update \main_sdcore_crc16_inserter_crc2_crc $0\main_sdcore_crc16_inserter_crc2_crc[15:0] - end - attribute \src "ls180.v:507.5-507.51" - process $proc$ls180.v:507$3044 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_ras $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] + update \sdram_bankmachine3_auto_precharge $0\sdram_bankmachine3_auto_precharge[0:0] end - attribute \src "ls180.v:5074.1-5081.4" - process $proc$ls180.v:5074$937 + attribute \src "ls180.v:2435.1-2442.4" + process $proc$ls180.v:2435$232 assign { } { } - assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5076.2-5080.5" - switch \main_sdcore_crc16_inserter_crc3_enable - attribute \src "ls180.v:5076.6-5076.44" + assign $0\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "ls180.v:2437.2-2441.5" + switch \sdram_bankmachine3_cmd_buffer_lookahead_replace + attribute \src "ls180.v:2437.6-2437.53" case 1'1 - assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2 - attribute \src "ls180.v:5078.6-5078.10" + assign $0\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$ls180.v:2438$233_Y + attribute \src "ls180.v:2439.6-2439.10" case - assign $0\main_sdcore_crc16_inserter_crc3_crc[15:0] \main_sdcore_crc16_inserter_crc3_crcreg0 + assign $0\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] \sdram_bankmachine3_cmd_buffer_lookahead_produce end sync always - update \main_sdcore_crc16_inserter_crc3_crc $0\main_sdcore_crc16_inserter_crc3_crc[15:0] - end - attribute \src "ls180.v:508.5-508.50" - process $proc$ls180.v:508$3045 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_payload_we $1\main_sdram_bankmachine1_cmd_payload_we[0:0] + update \sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $0\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] end - attribute \src "ls180.v:5082.1-5161.4" - process $proc$ls180.v:5082$938 + attribute \src "ls180.v:2451.1-2544.4" + process $proc$ls180.v:2451$241 assign { } { } assign { } { } assign { } { } @@ -291589,359 +264789,439 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\sdram_bankmachine3_row_open[0:0] 1'0 + assign $0\sdram_bankmachine3_row_close[0:0] 1'0 + assign $0\sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 + assign $0\sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 + assign $0\sdram_bankmachine3_cmd_payload_we[0:0] 1'0 + assign $0\sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 + assign $0\sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 + assign $0\sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 + assign $0\sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 + assign $0\sdram_bankmachine3_req_wdata_ready[0:0] 1'0 + assign $0\sdram_bankmachine3_req_rdata_valid[0:0] 1'0 assign { } { } - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 - assign { } { } - assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 - assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 - assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] \builder_sdcore_crcupstreaminserter_state - attribute \src "ls180.v:5099.2-5160.9" - switch \builder_sdcore_crcupstreaminserter_state + assign $0\sdram_bankmachine3_refresh_gnt[0:0] 1'0 + assign $0\sdram_bankmachine3_cmd_valid[0:0] 1'0 + assign $0\subfragments_bankmachine3_next_state[2:0] \subfragments_bankmachine3_state + attribute \src "ls180.v:2467.2-2543.9" + switch \subfragments_bankmachine3_state attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_source_valid[0:0] 1'1 - attribute \src "ls180.v:5103.4-5105.7" - switch $eq$ls180.v:5103$939_Y - attribute \src "ls180.v:5103.8-5103.48" + case 3'001 + assign $0\sdram_bankmachine3_row_close[0:0] 1'1 + attribute \src "ls180.v:2469.4-2477.7" + switch $and$ls180.v:2469$242_Y + attribute \src "ls180.v:2469.8-2469.77" case 1'1 - assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'1 + assign $0\sdram_bankmachine3_cmd_valid[0:0] 1'1 + assign $0\sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 + assign $0\sdram_bankmachine3_cmd_payload_we[0:0] 1'1 + assign $0\sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:2471.5-2473.8" + switch \sdram_bankmachine3_cmd_ready + attribute \src "ls180.v:2471.9-2471.37" + case 1'1 + assign $0\subfragments_bankmachine3_next_state[2:0] 3'101 + case + end case end - attribute \src "ls180.v:5106.4-5131.11" - switch \main_sdcore_crc16_inserter_cnt - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [15] \main_sdcore_crc16_inserter_crctmp2 [15] \main_sdcore_crc16_inserter_crctmp1 [15] \main_sdcore_crc16_inserter_crctmp0 [15] \main_sdcore_crc16_inserter_crctmp3 [14] \main_sdcore_crc16_inserter_crctmp2 [14] \main_sdcore_crc16_inserter_crctmp1 [14] \main_sdcore_crc16_inserter_crctmp0 [14] } - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [13] \main_sdcore_crc16_inserter_crctmp2 [13] \main_sdcore_crc16_inserter_crctmp1 [13] \main_sdcore_crc16_inserter_crctmp0 [13] \main_sdcore_crc16_inserter_crctmp3 [12] \main_sdcore_crc16_inserter_crctmp2 [12] \main_sdcore_crc16_inserter_crctmp1 [12] \main_sdcore_crc16_inserter_crctmp0 [12] } - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [11] \main_sdcore_crc16_inserter_crctmp2 [11] \main_sdcore_crc16_inserter_crctmp1 [11] \main_sdcore_crc16_inserter_crctmp0 [11] \main_sdcore_crc16_inserter_crctmp3 [10] \main_sdcore_crc16_inserter_crctmp2 [10] \main_sdcore_crc16_inserter_crctmp1 [10] \main_sdcore_crc16_inserter_crctmp0 [10] } - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [9] \main_sdcore_crc16_inserter_crctmp2 [9] \main_sdcore_crc16_inserter_crctmp1 [9] \main_sdcore_crc16_inserter_crctmp0 [9] \main_sdcore_crc16_inserter_crctmp3 [8] \main_sdcore_crc16_inserter_crctmp2 [8] \main_sdcore_crc16_inserter_crctmp1 [8] \main_sdcore_crc16_inserter_crctmp0 [8] } - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [7] \main_sdcore_crc16_inserter_crctmp2 [7] \main_sdcore_crc16_inserter_crctmp1 [7] \main_sdcore_crc16_inserter_crctmp0 [7] \main_sdcore_crc16_inserter_crctmp3 [6] \main_sdcore_crc16_inserter_crctmp2 [6] \main_sdcore_crc16_inserter_crctmp1 [6] \main_sdcore_crc16_inserter_crctmp0 [6] } - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [5] \main_sdcore_crc16_inserter_crctmp2 [5] \main_sdcore_crc16_inserter_crctmp1 [5] \main_sdcore_crc16_inserter_crctmp0 [5] \main_sdcore_crc16_inserter_crctmp3 [4] \main_sdcore_crc16_inserter_crctmp2 [4] \main_sdcore_crc16_inserter_crctmp1 [4] \main_sdcore_crc16_inserter_crctmp0 [4] } - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [3] \main_sdcore_crc16_inserter_crctmp2 [3] \main_sdcore_crc16_inserter_crctmp1 [3] \main_sdcore_crc16_inserter_crctmp0 [3] \main_sdcore_crc16_inserter_crctmp3 [2] \main_sdcore_crc16_inserter_crctmp2 [2] \main_sdcore_crc16_inserter_crctmp1 [2] \main_sdcore_crc16_inserter_crctmp0 [2] } - attribute \src "ls180.v:0.0-0.0" - case 3'111 - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] { \main_sdcore_crc16_inserter_crctmp3 [1] \main_sdcore_crc16_inserter_crctmp2 [1] \main_sdcore_crc16_inserter_crctmp1 [1] \main_sdcore_crc16_inserter_crctmp0 [1] \main_sdcore_crc16_inserter_crctmp3 [0] \main_sdcore_crc16_inserter_crctmp2 [0] \main_sdcore_crc16_inserter_crctmp1 [0] \main_sdcore_crc16_inserter_crctmp0 [0] } + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\sdram_bankmachine3_row_close[0:0] 1'1 + attribute \src "ls180.v:2481.4-2483.7" + switch $and$ls180.v:2481$243_Y + attribute \src "ls180.v:2481.8-2481.77" + case 1'1 + assign $0\subfragments_bankmachine3_next_state[2:0] 3'101 case end - attribute \src "ls180.v:5132.4-5139.7" - switch \main_sdcore_crc16_inserter_source_ready - attribute \src "ls180.v:5132.8-5132.47" + attribute \src "ls180.v:0.0-0.0" + case 3'011 + attribute \src "ls180.v:2487.4-2496.7" + switch \sdram_bankmachine3_trccon_ready + attribute \src "ls180.v:2487.8-2487.39" case 1'1 - attribute \src "ls180.v:5133.5-5138.8" - switch $eq$ls180.v:5133$940_Y - attribute \src "ls180.v:5133.9-5133.49" + assign $0\sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'1 + assign $0\sdram_bankmachine3_row_open[0:0] 1'1 + assign $0\sdram_bankmachine3_cmd_valid[0:0] 1'1 + assign $0\sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 + assign $0\sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 + attribute \src "ls180.v:2492.5-2494.8" + switch \sdram_bankmachine3_cmd_ready + attribute \src "ls180.v:2492.9-2492.37" case 1'1 - assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 - attribute \src "ls180.v:5135.9-5135.13" + assign $0\subfragments_bankmachine3_next_state[2:0] 3'110 case - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] $add$ls180.v:5136$941_Y - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'1 end case end attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\sdram_bankmachine3_row_close[0:0] 1'1 + assign $0\sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "ls180.v:2499.4-2501.7" + switch \sdram_bankmachine3_twtpcon_ready + attribute \src "ls180.v:2499.8-2499.40" + case 1'1 + assign $0\sdram_bankmachine3_refresh_gnt[0:0] 1'1 + case + end + attribute \src "ls180.v:2504.4-2506.7" + switch $not$ls180.v:2504$244_Y + attribute \src "ls180.v:2504.8-2504.41" + case 1'1 + assign $0\subfragments_bankmachine3_next_state[2:0] 3'000 + case + end + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\subfragments_bankmachine3_next_state[2:0] 3'011 + attribute \src "ls180.v:0.0-0.0" + case 3'110 + assign $0\subfragments_bankmachine3_next_state[2:0] 3'000 + attribute \src "ls180.v:0.0-0.0" case - assign $0\main_sdcore_crc16_inserter_source_payload_data[7:0] \main_sdcore_crc16_inserter_sink_payload_data - assign $0\main_sdcore_crc16_inserter_source_valid[0:0] \main_sdcore_crc16_inserter_sink_valid - assign $0\main_sdcore_crc16_inserter_sink_ready[0:0] \main_sdcore_crc16_inserter_source_ready - assign $0\main_sdcore_crc16_inserter_source_last[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] \main_sdcore_crc16_inserter_crc0_crc - assign $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'1 - assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] \main_sdcore_crc16_inserter_crc1_crc - assign $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'1 - assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] \main_sdcore_crc16_inserter_crc2_crc - assign $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'1 - assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] \main_sdcore_crc16_inserter_crc3_crc - assign $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5154.4-5158.7" - switch $and$ls180.v:5154$943_Y - attribute \src "ls180.v:5154.8-5154.128" + attribute \src "ls180.v:2515.4-2541.7" + switch \sdram_bankmachine3_refresh_req + attribute \src "ls180.v:2515.8-2515.38" case 1'1 - assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'1 - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 - assign $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'1 + assign $0\subfragments_bankmachine3_next_state[2:0] 3'100 + attribute \src "ls180.v:2517.8-2517.12" case + attribute \src "ls180.v:2518.5-2540.8" + switch \sdram_bankmachine3_cmd_buffer_source_valid + attribute \src "ls180.v:2518.9-2518.51" + case 1'1 + attribute \src "ls180.v:2519.6-2539.9" + switch \sdram_bankmachine3_row_opened + attribute \src "ls180.v:2519.10-2519.39" + case 1'1 + attribute \src "ls180.v:2520.7-2536.10" + switch \sdram_bankmachine3_row_hit + attribute \src "ls180.v:2520.11-2520.37" + case 1'1 + assign $0\sdram_bankmachine3_cmd_valid[0:0] 1'1 + assign $0\sdram_bankmachine3_cmd_payload_cas[0:0] 1'1 + attribute \src "ls180.v:2522.8-2529.11" + switch \sdram_bankmachine3_cmd_buffer_source_payload_we + attribute \src "ls180.v:2522.12-2522.59" + case 1'1 + assign $0\sdram_bankmachine3_req_wdata_ready[0:0] \sdram_bankmachine3_cmd_ready + assign $0\sdram_bankmachine3_cmd_payload_is_write[0:0] 1'1 + assign $0\sdram_bankmachine3_cmd_payload_we[0:0] 1'1 + attribute \src "ls180.v:2526.12-2526.16" + case + assign $0\sdram_bankmachine3_req_rdata_valid[0:0] \sdram_bankmachine3_cmd_ready + assign $0\sdram_bankmachine3_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "ls180.v:2531.8-2533.11" + switch $and$ls180.v:2531$245_Y + attribute \src "ls180.v:2531.12-2531.78" + case 1'1 + assign $0\subfragments_bankmachine3_next_state[2:0] 3'010 + case + end + attribute \src "ls180.v:2534.11-2534.15" + case + assign $0\subfragments_bankmachine3_next_state[2:0] 3'001 + end + attribute \src "ls180.v:2537.10-2537.14" + case + assign $0\subfragments_bankmachine3_next_state[2:0] 3'011 + end + case + end end end sync always - update \main_sdcore_crc16_inserter_sink_ready $0\main_sdcore_crc16_inserter_sink_ready[0:0] - update \main_sdcore_crc16_inserter_source_valid $0\main_sdcore_crc16_inserter_source_valid[0:0] - update \main_sdcore_crc16_inserter_source_last $0\main_sdcore_crc16_inserter_source_last[0:0] - update \main_sdcore_crc16_inserter_source_payload_data $0\main_sdcore_crc16_inserter_source_payload_data[7:0] - update \builder_sdcore_crcupstreaminserter_next_state $0\builder_sdcore_crcupstreaminserter_next_state[0:0] - update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] - update \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $0\main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] - update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] - update \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $0\main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] - update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] - update \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $0\main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] - update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] - update \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $0\main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] - update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] - update \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $0\main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] + update \sdram_bankmachine3_req_wdata_ready $0\sdram_bankmachine3_req_wdata_ready[0:0] + update \sdram_bankmachine3_req_rdata_valid $0\sdram_bankmachine3_req_rdata_valid[0:0] + update \sdram_bankmachine3_refresh_gnt $0\sdram_bankmachine3_refresh_gnt[0:0] + update \sdram_bankmachine3_cmd_valid $0\sdram_bankmachine3_cmd_valid[0:0] + update \sdram_bankmachine3_cmd_payload_cas $0\sdram_bankmachine3_cmd_payload_cas[0:0] + update \sdram_bankmachine3_cmd_payload_ras $0\sdram_bankmachine3_cmd_payload_ras[0:0] + update \sdram_bankmachine3_cmd_payload_we $0\sdram_bankmachine3_cmd_payload_we[0:0] + update \sdram_bankmachine3_cmd_payload_is_cmd $0\sdram_bankmachine3_cmd_payload_is_cmd[0:0] + update \sdram_bankmachine3_cmd_payload_is_read $0\sdram_bankmachine3_cmd_payload_is_read[0:0] + update \sdram_bankmachine3_cmd_payload_is_write $0\sdram_bankmachine3_cmd_payload_is_write[0:0] + update \sdram_bankmachine3_row_open $0\sdram_bankmachine3_row_open[0:0] + update \sdram_bankmachine3_row_close $0\sdram_bankmachine3_row_close[0:0] + update \sdram_bankmachine3_row_col_n_addr_sel $0\sdram_bankmachine3_row_col_n_addr_sel[0:0] + update \subfragments_bankmachine3_next_state $0\subfragments_bankmachine3_next_state[2:0] end - attribute \src "ls180.v:509.5-509.54" - process $proc$ls180.v:509$3046 + attribute \src "ls180.v:246.12-246.33" + process $proc$ls180.v:246$1694 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 + assign $1\dfi_p0_rddata[15:0] 16'0000000000000000 sync always sync init - update \main_sdram_bankmachine1_cmd_payload_is_cmd $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + update \dfi_p0_rddata $1\dfi_p0_rddata[15:0] end - attribute \src "ls180.v:510.5-510.55" - process $proc$ls180.v:510$3047 + attribute \src "ls180.v:247.5-247.31" + process $proc$ls180.v:247$1695 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 + assign $1\dfi_p0_rddata_valid[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_cmd_payload_is_read $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + update \dfi_p0_rddata_valid $1\dfi_p0_rddata_valid[0:0] end - attribute \src "ls180.v:511.5-511.56" - process $proc$ls180.v:511$3048 + attribute \src "ls180.v:248.11-248.27" + process $proc$ls180.v:248$1696 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 + assign $1\rddata_en[2:0] 3'000 sync always sync init - update \main_sdram_bankmachine1_cmd_payload_is_write $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + update \rddata_en $1\rddata_en[2:0] end - attribute \src "ls180.v:512.5-512.50" - process $proc$ls180.v:512$3049 + attribute \src "ls180.v:251.5-251.31" + process $proc$ls180.v:251$1697 assign { } { } - assign $1\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 + assign $1\sdram_inti_p0_cas_n[0:0] 1'1 sync always sync init - update \main_sdram_bankmachine1_auto_precharge $1\main_sdram_bankmachine1_auto_precharge[0:0] + update \sdram_inti_p0_cas_n $1\sdram_inti_p0_cas_n[0:0] end - attribute \src "ls180.v:515.5-515.67" - process $proc$ls180.v:515$3050 + attribute \src "ls180.v:252.5-252.30" + process $proc$ls180.v:252$1698 assign { } { } - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0 + assign $1\sdram_inti_p0_cs_n[0:0] 1'1 sync always - update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] sync init + update \sdram_inti_p0_cs_n $1\sdram_inti_p0_cs_n[0:0] end - attribute \src "ls180.v:516.5-516.66" - process $proc$ls180.v:516$3051 + attribute \src "ls180.v:253.5-253.31" + process $proc$ls180.v:253$1699 assign { } { } - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0 + assign $1\sdram_inti_p0_ras_n[0:0] 1'1 sync always - update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] sync init + update \sdram_inti_p0_ras_n $1\sdram_inti_p0_ras_n[0:0] end - attribute \src "ls180.v:5162.1-5167.4" - process $proc$ls180.v:5162$944 + attribute \src "ls180.v:254.5-254.30" + process $proc$ls180.v:254$1700 assign { } { } - assign $0\main_sdcore_crc16_checker_valid[0:0] 1'0 - attribute \src "ls180.v:5164.2-5166.5" - switch $and$ls180.v:5164$951_Y - attribute \src "ls180.v:5164.6-5164.301" - case 1'1 - assign $0\main_sdcore_crc16_checker_valid[0:0] 1'1 - case - end + assign $1\sdram_inti_p0_we_n[0:0] 1'1 + sync always + sync init + update \sdram_inti_p0_we_n $1\sdram_inti_p0_we_n[0:0] + end + attribute \src "ls180.v:2564.1-2570.4" + process $proc$ls180.v:2564$284 + assign { } { } + assign { } { } + assign $0\sdram_choose_cmd_valids[3:0] [0] $and$ls180.v:2566$297_Y + assign $0\sdram_choose_cmd_valids[3:0] [1] $and$ls180.v:2567$310_Y + assign $0\sdram_choose_cmd_valids[3:0] [2] $and$ls180.v:2568$323_Y + assign $0\sdram_choose_cmd_valids[3:0] [3] $and$ls180.v:2569$336_Y sync always - update \main_sdcore_crc16_checker_valid $0\main_sdcore_crc16_checker_valid[0:0] + update \sdram_choose_cmd_valids $0\sdram_choose_cmd_valids[3:0] end - attribute \src "ls180.v:5170.1-5177.4" - process $proc$ls180.v:5170$953 + attribute \src "ls180.v:2578.1-2583.4" + process $proc$ls180.v:2578$337 assign { } { } - assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 - attribute \src "ls180.v:5172.2-5176.5" - switch $eq$ls180.v:5172$954_Y - attribute \src "ls180.v:5172.6-5172.45" + assign $0\sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 + attribute \src "ls180.v:2580.2-2582.5" + switch \sdram_choose_cmd_cmd_valid + attribute \src "ls180.v:2580.6-2580.32" case 1'1 - assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'1 - attribute \src "ls180.v:5174.6-5174.10" + assign $0\sdram_choose_cmd_cmd_payload_cas[0:0] \t_array_muxed0 case - assign $0\main_sdcore_crc16_checker_crc0_clr[0:0] 1'0 end sync always - update \main_sdcore_crc16_checker_crc0_clr $0\main_sdcore_crc16_checker_crc0_clr[0:0] + update \sdram_choose_cmd_cmd_payload_cas $0\sdram_choose_cmd_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:258.5-258.31" + process $proc$ls180.v:258$1701 + assign { } { } + assign $0\sdram_inti_p0_act_n[0:0] 1'1 + sync always + update \sdram_inti_p0_act_n $0\sdram_inti_p0_act_n[0:0] + sync init end - attribute \src "ls180.v:5180.1-5187.4" - process $proc$ls180.v:5180$956 + attribute \src "ls180.v:2584.1-2589.4" + process $proc$ls180.v:2584$338 assign { } { } - assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 - attribute \src "ls180.v:5182.2-5186.5" - switch $eq$ls180.v:5182$957_Y - attribute \src "ls180.v:5182.6-5182.45" + assign $0\sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 + attribute \src "ls180.v:2586.2-2588.5" + switch \sdram_choose_cmd_cmd_valid + attribute \src "ls180.v:2586.6-2586.32" case 1'1 - assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'1 - attribute \src "ls180.v:5184.6-5184.10" + assign $0\sdram_choose_cmd_cmd_payload_ras[0:0] \t_array_muxed1 case - assign $0\main_sdcore_crc16_checker_crc1_clr[0:0] 1'0 end sync always - update \main_sdcore_crc16_checker_crc1_clr $0\main_sdcore_crc16_checker_crc1_clr[0:0] + update \sdram_choose_cmd_cmd_payload_ras $0\sdram_choose_cmd_cmd_payload_ras[0:0] end - attribute \src "ls180.v:5190.1-5197.4" - process $proc$ls180.v:5190$959 + attribute \src "ls180.v:2590.1-2595.4" + process $proc$ls180.v:2590$339 assign { } { } - assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 - attribute \src "ls180.v:5192.2-5196.5" - switch $eq$ls180.v:5192$960_Y - attribute \src "ls180.v:5192.6-5192.45" + assign $0\sdram_choose_cmd_cmd_payload_we[0:0] 1'0 + attribute \src "ls180.v:2592.2-2594.5" + switch \sdram_choose_cmd_cmd_valid + attribute \src "ls180.v:2592.6-2592.32" case 1'1 - assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'1 - attribute \src "ls180.v:5194.6-5194.10" + assign $0\sdram_choose_cmd_cmd_payload_we[0:0] \t_array_muxed2 case - assign $0\main_sdcore_crc16_checker_crc2_clr[0:0] 1'0 end sync always - update \main_sdcore_crc16_checker_crc2_clr $0\main_sdcore_crc16_checker_crc2_clr[0:0] + update \sdram_choose_cmd_cmd_payload_we $0\sdram_choose_cmd_cmd_payload_we[0:0] end - attribute \src "ls180.v:5200.1-5207.4" - process $proc$ls180.v:5200$962 + attribute \src "ls180.v:2597.1-2603.4" + process $proc$ls180.v:2597$342 assign { } { } - assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 - attribute \src "ls180.v:5202.2-5206.5" - switch $eq$ls180.v:5202$963_Y - attribute \src "ls180.v:5202.6-5202.45" + assign { } { } + assign $0\sdram_choose_req_valids[3:0] [0] $and$ls180.v:2599$355_Y + assign $0\sdram_choose_req_valids[3:0] [1] $and$ls180.v:2600$368_Y + assign $0\sdram_choose_req_valids[3:0] [2] $and$ls180.v:2601$381_Y + assign $0\sdram_choose_req_valids[3:0] [3] $and$ls180.v:2602$394_Y + sync always + update \sdram_choose_req_valids $0\sdram_choose_req_valids[3:0] + end + attribute \src "ls180.v:2611.1-2616.4" + process $proc$ls180.v:2611$395 + assign { } { } + assign $0\sdram_choose_req_cmd_payload_cas[0:0] 1'0 + attribute \src "ls180.v:2613.2-2615.5" + switch \sdram_choose_req_cmd_valid + attribute \src "ls180.v:2613.6-2613.32" case 1'1 - assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'1 - attribute \src "ls180.v:5204.6-5204.10" + assign $0\sdram_choose_req_cmd_payload_cas[0:0] \t_array_muxed3 case - assign $0\main_sdcore_crc16_checker_crc3_clr[0:0] 1'0 end sync always - update \main_sdcore_crc16_checker_crc3_clr $0\main_sdcore_crc16_checker_crc3_clr[0:0] + update \sdram_choose_req_cmd_payload_cas $0\sdram_choose_req_cmd_payload_cas[0:0] end - attribute \src "ls180.v:5209.1-5214.4" - process $proc$ls180.v:5209$964 + attribute \src "ls180.v:2617.1-2622.4" + process $proc$ls180.v:2617$396 assign { } { } - assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'0 - attribute \src "ls180.v:5211.2-5213.5" - switch $and$ls180.v:5211$966_Y - attribute \src "ls180.v:5211.6-5211.85" + assign $0\sdram_choose_req_cmd_payload_ras[0:0] 1'0 + attribute \src "ls180.v:2619.2-2621.5" + switch \sdram_choose_req_cmd_valid + attribute \src "ls180.v:2619.6-2619.32" case 1'1 - assign $0\main_sdcore_crc16_checker_source_valid[0:0] 1'1 + assign $0\sdram_choose_req_cmd_payload_ras[0:0] \t_array_muxed4 case end sync always - update \main_sdcore_crc16_checker_source_valid $0\main_sdcore_crc16_checker_source_valid[0:0] + update \sdram_choose_req_cmd_payload_ras $0\sdram_choose_req_cmd_payload_ras[0:0] end - attribute \src "ls180.v:5215.1-5222.4" - process $proc$ls180.v:5215$967 + attribute \src "ls180.v:2623.1-2628.4" + process $proc$ls180.v:2623$397 assign { } { } - assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'0 - attribute \src "ls180.v:5217.2-5221.5" - switch $lt$ls180.v:5217$968_Y - attribute \src "ls180.v:5217.6-5217.44" + assign $0\sdram_choose_req_cmd_payload_we[0:0] 1'0 + attribute \src "ls180.v:2625.2-2627.5" + switch \sdram_choose_req_cmd_valid + attribute \src "ls180.v:2625.6-2625.32" case 1'1 - assign $0\main_sdcore_crc16_checker_sink_ready[0:0] 1'1 - attribute \src "ls180.v:5219.6-5219.10" + assign $0\sdram_choose_req_cmd_payload_we[0:0] \t_array_muxed5 case - assign $0\main_sdcore_crc16_checker_sink_ready[0:0] \main_sdcore_crc16_checker_source_ready end sync always - update \main_sdcore_crc16_checker_sink_ready $0\main_sdcore_crc16_checker_sink_ready[0:0] + update \sdram_choose_req_cmd_payload_we $0\sdram_choose_req_cmd_payload_we[0:0] end - attribute \src "ls180.v:5226.1-5233.4" - process $proc$ls180.v:5226$979 + attribute \src "ls180.v:2629.1-2637.4" + process $proc$ls180.v:2629$398 assign { } { } - assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5228.2-5232.5" - switch \main_sdcore_crc16_checker_crc0_enable - attribute \src "ls180.v:5228.6-5228.43" + assign $0\sdram_bankmachine0_cmd_ready[0:0] 1'0 + attribute \src "ls180.v:2631.2-2633.5" + switch $and$ls180.v:2631$401_Y + attribute \src "ls180.v:2631.6-2631.100" case 1'1 - assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg2 - attribute \src "ls180.v:5230.6-5230.10" + assign $0\sdram_bankmachine0_cmd_ready[0:0] 1'1 case - assign $0\main_sdcore_crc16_checker_crc0_crc[15:0] \main_sdcore_crc16_checker_crc0_crcreg0 end + attribute \src "ls180.v:2634.2-2636.5" + switch $and$ls180.v:2634$404_Y + attribute \src "ls180.v:2634.6-2634.100" + case 1'1 + assign $0\sdram_bankmachine0_cmd_ready[0:0] 1'1 + case + end + sync always + update \sdram_bankmachine0_cmd_ready $0\sdram_bankmachine0_cmd_ready[0:0] + end + attribute \src "ls180.v:263.12-263.40" + process $proc$ls180.v:263$1702 + assign { } { } + assign $1\sdram_inti_p0_rddata[15:0] 16'0000000000000000 sync always - update \main_sdcore_crc16_checker_crc0_crc $0\main_sdcore_crc16_checker_crc0_crc[15:0] + sync init + update \sdram_inti_p0_rddata $1\sdram_inti_p0_rddata[15:0] end - attribute \src "ls180.v:5236.1-5243.4" - process $proc$ls180.v:5236$990 + attribute \src "ls180.v:2638.1-2646.4" + process $proc$ls180.v:2638$405 assign { } { } - assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5238.2-5242.5" - switch \main_sdcore_crc16_checker_crc1_enable - attribute \src "ls180.v:5238.6-5238.43" + assign $0\sdram_bankmachine1_cmd_ready[0:0] 1'0 + attribute \src "ls180.v:2640.2-2642.5" + switch $and$ls180.v:2640$408_Y + attribute \src "ls180.v:2640.6-2640.100" + case 1'1 + assign $0\sdram_bankmachine1_cmd_ready[0:0] 1'1 + case + end + attribute \src "ls180.v:2643.2-2645.5" + switch $and$ls180.v:2643$411_Y + attribute \src "ls180.v:2643.6-2643.100" case 1'1 - assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg2 - attribute \src "ls180.v:5240.6-5240.10" + assign $0\sdram_bankmachine1_cmd_ready[0:0] 1'1 case - assign $0\main_sdcore_crc16_checker_crc1_crc[15:0] \main_sdcore_crc16_checker_crc1_crcreg0 end sync always - update \main_sdcore_crc16_checker_crc1_crc $0\main_sdcore_crc16_checker_crc1_crc[15:0] + update \sdram_bankmachine1_cmd_ready $0\sdram_bankmachine1_cmd_ready[0:0] + end + attribute \src "ls180.v:264.5-264.38" + process $proc$ls180.v:264$1703 + assign { } { } + assign $1\sdram_inti_p0_rddata_valid[0:0] 1'0 + sync always + sync init + update \sdram_inti_p0_rddata_valid $1\sdram_inti_p0_rddata_valid[0:0] end - attribute \src "ls180.v:5246.1-5253.4" - process $proc$ls180.v:5246$1001 + attribute \src "ls180.v:2647.1-2655.4" + process $proc$ls180.v:2647$412 assign { } { } - assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5248.2-5252.5" - switch \main_sdcore_crc16_checker_crc2_enable - attribute \src "ls180.v:5248.6-5248.43" + assign $0\sdram_bankmachine2_cmd_ready[0:0] 1'0 + attribute \src "ls180.v:2649.2-2651.5" + switch $and$ls180.v:2649$415_Y + attribute \src "ls180.v:2649.6-2649.100" + case 1'1 + assign $0\sdram_bankmachine2_cmd_ready[0:0] 1'1 + case + end + attribute \src "ls180.v:2652.2-2654.5" + switch $and$ls180.v:2652$418_Y + attribute \src "ls180.v:2652.6-2652.100" case 1'1 - assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg2 - attribute \src "ls180.v:5250.6-5250.10" + assign $0\sdram_bankmachine2_cmd_ready[0:0] 1'1 case - assign $0\main_sdcore_crc16_checker_crc2_crc[15:0] \main_sdcore_crc16_checker_crc2_crcreg0 end sync always - update \main_sdcore_crc16_checker_crc2_crc $0\main_sdcore_crc16_checker_crc2_crc[15:0] + update \sdram_bankmachine2_cmd_ready $0\sdram_bankmachine2_cmd_ready[0:0] end - attribute \src "ls180.v:5256.1-5263.4" - process $proc$ls180.v:5256$1012 + attribute \src "ls180.v:2656.1-2664.4" + process $proc$ls180.v:2656$419 assign { } { } - assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 - attribute \src "ls180.v:5258.2-5262.5" - switch \main_sdcore_crc16_checker_crc3_enable - attribute \src "ls180.v:5258.6-5258.43" + assign $0\sdram_bankmachine3_cmd_ready[0:0] 1'0 + attribute \src "ls180.v:2658.2-2660.5" + switch $and$ls180.v:2658$422_Y + attribute \src "ls180.v:2658.6-2658.100" + case 1'1 + assign $0\sdram_bankmachine3_cmd_ready[0:0] 1'1 + case + end + attribute \src "ls180.v:2661.2-2663.5" + switch $and$ls180.v:2661$425_Y + attribute \src "ls180.v:2661.6-2661.100" case 1'1 - assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg2 - attribute \src "ls180.v:5260.6-5260.10" + assign $0\sdram_bankmachine3_cmd_ready[0:0] 1'1 case - assign $0\main_sdcore_crc16_checker_crc3_crc[15:0] \main_sdcore_crc16_checker_crc3_crcreg0 end sync always - update \main_sdcore_crc16_checker_crc3_crc $0\main_sdcore_crc16_checker_crc3_crc[15:0] + update \sdram_bankmachine3_cmd_ready $0\sdram_bankmachine3_cmd_ready[0:0] end - attribute \src "ls180.v:5264.1-5454.4" - process $proc$ls180.v:5264$1013 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "ls180.v:2669.1-2741.4" + process $proc$ls180.v:2669$428 assign { } { } assign { } { } assign { } { } @@ -291951,475 +265231,169 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\sdram_choose_req_cmd_ready[0:0] 1'0 + assign $0\sdram_steerer_sel[1:0] 2'00 + assign $0\sdram_en0[0:0] 1'0 + assign $0\sdram_en1[0:0] 1'0 + assign $0\sdram_choose_req_want_reads[0:0] 1'0 assign { } { } + assign $0\sdram_choose_req_want_writes[0:0] 1'0 + assign $0\sdram_cmd_ready[0:0] 1'0 assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 - assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 - assign $0\main_sdcore_crc16_checker_sink_first[0:0] 1'0 - assign $0\main_sdcore_crc16_checker_sink_last[0:0] 1'0 - assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 - assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 - assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 - assign $0\main_sdcore_crc16_inserter_source_ready[0:0] 1'0 - assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 - assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 - assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 - assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 - assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 - assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 - assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 - assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 - assign $0\main_sdphy_dataw_sink_valid[0:0] 1'0 - assign $0\main_sdphy_datar_sink_valid[0:0] 1'0 - assign $0\main_sdphy_dataw_sink_first[0:0] 1'0 - assign $0\main_sdphy_datar_sink_last[0:0] 1'0 - assign $0\main_sdphy_dataw_sink_last[0:0] 1'0 - assign $0\main_sdphy_datar_sink_payload_block_length[9:0] 10'0000000000 - assign $0\main_sdphy_dataw_sink_payload_data[7:0] 8'00000000 - assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'0 - assign $0\main_sdphy_datar_source_ready[0:0] 1'0 - assign $0\main_sdphy_cmdr_sink_last[0:0] 1'0 - assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000000 - assign $0\main_sdphy_cmdr_source_ready[0:0] 1'0 - assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 - assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'0 - assign $0\main_sdphy_cmdw_sink_last[0:0] 1'0 - assign $0\main_sdphy_cmdw_sink_payload_data[7:0] 8'00000000 - assign { } { } - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 - assign $0\main_sdcore_crc16_checker_sink_valid[0:0] 1'0 - assign $0\builder_sdcore_fsm_next_state[2:0] \builder_sdcore_fsm_state - attribute \src "ls180.v:5305.2-5453.9" - switch \builder_sdcore_fsm_state + assign $0\sdram_choose_req_want_activates[0:0] \sdram_ras_allowed + assign $0\subfragments_multiplexer_next_state[2:0] \subfragments_multiplexer_state + attribute \src "ls180.v:2681.2-2740.9" + switch \subfragments_multiplexer_state attribute \src "ls180.v:0.0-0.0" case 3'001 - assign $0\main_sdphy_cmdw_sink_valid[0:0] 1'1 - attribute \src "ls180.v:5308.4-5328.11" - switch \main_sdcore_cmd_count - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\main_sdphy_cmdw_sink_payload_data[7:0] { 2'01 \main_sdcore_cmd_command_storage [13:8] } - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [31:24] - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [23:16] - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [15:8] - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdphy_cmdw_sink_payload_data[7:0] \main_sdcore_cmd_argument_storage [7:0] - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\main_sdphy_cmdw_sink_payload_data[7:0] { \main_sdcore_crc7_inserter_crc 1'1 } - assign $0\main_sdphy_cmdw_sink_last[0:0] $eq$ls180.v:5326$1014_Y + assign $0\sdram_en1[0:0] 1'1 + assign $0\sdram_choose_req_want_writes[0:0] 1'1 + assign $0\sdram_steerer_sel[1:0] 2'10 + attribute \src "ls180.v:2685.4-2691.7" + switch 1'1 + attribute \src "ls180.v:2685.8-2685.12" + case 1'1 + assign $0\sdram_choose_req_cmd_ready[0:0] $and$ls180.v:2686$435_Y case end - attribute \src "ls180.v:5329.4-5341.7" - switch $and$ls180.v:5329$1015_Y - attribute \src "ls180.v:5329.8-5329.65" + attribute \src "ls180.v:2693.4-2697.7" + switch \sdram_read_available + attribute \src "ls180.v:2693.8-2693.28" case 1'1 - assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] $add$ls180.v:5330$1016_Y - assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 - attribute \src "ls180.v:5332.5-5340.8" - switch $eq$ls180.v:5332$1017_Y - attribute \src "ls180.v:5332.9-5332.40" + attribute \src "ls180.v:2694.5-2696.8" + switch $or$ls180.v:2694$437_Y + attribute \src "ls180.v:2694.9-2694.53" case 1'1 - attribute \src "ls180.v:5333.6-5339.9" - switch $eq$ls180.v:5333$1018_Y - attribute \src "ls180.v:5333.10-5333.40" - case 1'1 - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'1 - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - attribute \src "ls180.v:5337.10-5337.14" - case - assign $0\builder_sdcore_fsm_next_state[2:0] 3'010 - end + assign $0\subfragments_multiplexer_next_state[2:0] 3'011 case end case end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdphy_cmdr_sink_valid[0:0] 1'1 - assign $0\main_sdphy_cmdr_sink_last[0:0] $eq$ls180.v:5345$1019_Y - assign $0\main_sdphy_cmdr_source_ready[0:0] 1'1 - attribute \src "ls180.v:5346.4-5350.7" - switch $eq$ls180.v:5346$1020_Y - attribute \src "ls180.v:5346.8-5346.38" + attribute \src "ls180.v:2698.4-2700.7" + switch \sdram_go_to_refresh + attribute \src "ls180.v:2698.8-2698.27" case 1'1 - assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00010001 - attribute \src "ls180.v:5348.8-5348.12" + assign $0\subfragments_multiplexer_next_state[2:0] 3'010 case - assign $0\main_sdphy_cmdr_sink_payload_length[7:0] 8'00000110 end - attribute \src "ls180.v:5352.4-5373.7" - switch \main_sdphy_cmdr_source_valid - attribute \src "ls180.v:5352.8-5352.36" + attribute \src "ls180.v:0.0-0.0" + case 3'010 + assign $0\sdram_steerer_sel[1:0] 2'11 + assign $0\sdram_cmd_ready[0:0] 1'1 + attribute \src "ls180.v:2705.4-2707.7" + switch \sdram_cmd_last + attribute \src "ls180.v:2705.8-2705.22" case 1'1 - attribute \src "ls180.v:5353.5-5372.8" - switch $eq$ls180.v:5353$1021_Y - attribute \src "ls180.v:5353.9-5353.56" - case 1'1 - assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'1 - assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - attribute \src "ls180.v:5357.9-5357.13" - case - attribute \src "ls180.v:5358.6-5371.9" - switch \main_sdphy_cmdr_source_last - attribute \src "ls180.v:5358.10-5358.37" - case 1'1 - attribute \src "ls180.v:5359.7-5367.10" - switch $eq$ls180.v:5359$1022_Y - attribute \src "ls180.v:5359.11-5359.42" - case 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'011 - attribute \src "ls180.v:5361.11-5361.15" - case - attribute \src "ls180.v:5362.8-5366.11" - switch $eq$ls180.v:5362$1023_Y - attribute \src "ls180.v:5362.12-5362.43" - case 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 - attribute \src "ls180.v:5364.12-5364.16" - case - assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - end - end - attribute \src "ls180.v:5368.10-5368.14" - case - assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] { \main_sdcore_cmd_response_status [119:0] \main_sdphy_cmdr_source_payload_data } - assign $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'1 - end - end + assign $0\subfragments_multiplexer_next_state[2:0] 3'000 case end attribute \src "ls180.v:0.0-0.0" case 3'011 - assign $0\main_sdphy_dataw_sink_valid[0:0] \main_sdcore_crc16_inserter_source_valid - assign $0\main_sdcore_crc16_inserter_source_ready[0:0] \main_sdphy_dataw_sink_ready - assign $0\main_sdphy_dataw_sink_first[0:0] \main_sdcore_crc16_inserter_source_first - assign $0\main_sdphy_dataw_sink_last[0:0] \main_sdcore_crc16_inserter_source_last - assign $0\main_sdphy_dataw_sink_payload_data[7:0] \main_sdcore_crc16_inserter_source_payload_data - assign $0\main_sdphy_datar_source_ready[0:0] 1'1 - attribute \src "ls180.v:5381.4-5387.7" - switch $and$ls180.v:5381$1025_Y - attribute \src "ls180.v:5381.8-5381.98" + attribute \src "ls180.v:2710.4-2712.7" + switch \sdram_twtrcon_ready + attribute \src "ls180.v:2710.8-2710.27" case 1'1 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5382$1026_Y - assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5384.5-5386.8" - switch $eq$ls180.v:5384$1028_Y - attribute \src "ls180.v:5384.9-5384.77" - case 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - case - end + assign $0\subfragments_multiplexer_next_state[2:0] 3'000 case end - attribute \src "ls180.v:5389.4-5394.7" - switch \main_sdphy_datar_source_valid - attribute \src "ls180.v:5389.8-5389.37" + attribute \src "ls180.v:0.0-0.0" + case 3'100 + assign $0\subfragments_multiplexer_next_state[2:0] 3'101 + attribute \src "ls180.v:0.0-0.0" + case 3'101 + assign $0\subfragments_multiplexer_next_state[2:0] 3'001 + attribute \src "ls180.v:0.0-0.0" + case + assign $0\sdram_en0[0:0] 1'1 + assign $0\sdram_choose_req_want_reads[0:0] 1'1 + assign $0\sdram_steerer_sel[1:0] 2'10 + attribute \src "ls180.v:2723.4-2729.7" + switch 1'1 + attribute \src "ls180.v:2723.8-2723.12" case 1'1 - attribute \src "ls180.v:5390.5-5393.8" - switch $ne$ls180.v:5390$1029_Y - attribute \src "ls180.v:5390.9-5390.57" - case 1'1 - assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'1 - assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'1 - case - end + assign $0\sdram_choose_req_cmd_ready[0:0] $and$ls180.v:2724$444_Y case end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdphy_datar_sink_valid[0:0] 1'1 - assign $0\main_sdphy_datar_sink_payload_block_length[9:0] \main_sdcore_block_length_storage - assign $0\main_sdphy_datar_sink_last[0:0] $eq$ls180.v:5399$1031_Y - attribute \src "ls180.v:5400.4-5426.7" - switch \main_sdphy_datar_source_valid - attribute \src "ls180.v:5400.8-5400.37" + attribute \src "ls180.v:2731.4-2735.7" + switch \sdram_write_available + attribute \src "ls180.v:2731.8-2731.29" case 1'1 - attribute \src "ls180.v:5401.5-5425.8" - switch $eq$ls180.v:5401$1032_Y - attribute \src "ls180.v:5401.9-5401.57" + attribute \src "ls180.v:2732.5-2734.8" + switch $or$ls180.v:2732$446_Y + attribute \src "ls180.v:2732.9-2732.52" case 1'1 - assign $0\main_sdcore_crc16_checker_sink_valid[0:0] \main_sdphy_datar_source_valid - assign $0\main_sdphy_datar_source_ready[0:0] \main_sdcore_crc16_checker_sink_ready - assign $0\main_sdcore_crc16_checker_sink_first[0:0] \main_sdphy_datar_source_first - assign $0\main_sdcore_crc16_checker_sink_last[0:0] \main_sdphy_datar_source_last - assign $0\main_sdcore_crc16_checker_sink_payload_data[7:0] \main_sdphy_datar_source_payload_data - attribute \src "ls180.v:5407.6-5415.9" - switch $and$ls180.v:5407$1033_Y - attribute \src "ls180.v:5407.10-5407.72" - case 1'1 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$ls180.v:5408$1034_Y - assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5410.7-5414.10" - switch $eq$ls180.v:5410$1036_Y - attribute \src "ls180.v:5410.11-5410.79" - case 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - attribute \src "ls180.v:5412.11-5412.15" - case - assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 - end - case - end - attribute \src "ls180.v:5416.9-5416.13" + assign $0\subfragments_multiplexer_next_state[2:0] 3'100 case - attribute \src "ls180.v:5417.6-5424.9" - switch $eq$ls180.v:5417$1037_Y - attribute \src "ls180.v:5417.10-5417.58" - case 1'1 - assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'1 - assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'1 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - assign $0\main_sdphy_datar_source_ready[0:0] 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 - case - end end case end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'1 - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 - assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'1 - assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'1 - assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 - assign $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 - assign $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 - attribute \src "ls180.v:5437.4-5451.7" - switch \main_sdcore_cmd_send_re - attribute \src "ls180.v:5437.8-5437.31" + attribute \src "ls180.v:2736.4-2738.7" + switch \sdram_go_to_refresh + attribute \src "ls180.v:2736.8-2736.27" case 1'1 - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 - assign $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 - assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 - assign $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'1 - assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 - assign $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'1 - assign $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 - assign $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'1 - assign $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 - assign $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'1 - assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 - assign $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'1 - assign $0\builder_sdcore_fsm_next_state[2:0] 3'001 + assign $0\subfragments_multiplexer_next_state[2:0] 3'010 case end end sync always - update \main_sdphy_cmdw_sink_valid $0\main_sdphy_cmdw_sink_valid[0:0] - update \main_sdphy_cmdw_sink_last $0\main_sdphy_cmdw_sink_last[0:0] - update \main_sdphy_cmdw_sink_payload_data $0\main_sdphy_cmdw_sink_payload_data[7:0] - update \main_sdphy_cmdr_sink_valid $0\main_sdphy_cmdr_sink_valid[0:0] - update \main_sdphy_cmdr_sink_last $0\main_sdphy_cmdr_sink_last[0:0] - update \main_sdphy_cmdr_sink_payload_length $0\main_sdphy_cmdr_sink_payload_length[7:0] - update \main_sdphy_cmdr_source_ready $0\main_sdphy_cmdr_source_ready[0:0] - update \main_sdphy_dataw_sink_valid $0\main_sdphy_dataw_sink_valid[0:0] - update \main_sdphy_dataw_sink_first $0\main_sdphy_dataw_sink_first[0:0] - update \main_sdphy_dataw_sink_last $0\main_sdphy_dataw_sink_last[0:0] - update \main_sdphy_dataw_sink_payload_data $0\main_sdphy_dataw_sink_payload_data[7:0] - update \main_sdphy_datar_sink_valid $0\main_sdphy_datar_sink_valid[0:0] - update \main_sdphy_datar_sink_last $0\main_sdphy_datar_sink_last[0:0] - update \main_sdphy_datar_sink_payload_block_length $0\main_sdphy_datar_sink_payload_block_length[9:0] - update \main_sdphy_datar_source_ready $0\main_sdphy_datar_source_ready[0:0] - update \main_sdcore_crc16_inserter_source_ready $0\main_sdcore_crc16_inserter_source_ready[0:0] - update \main_sdcore_crc16_checker_sink_valid $0\main_sdcore_crc16_checker_sink_valid[0:0] - update \main_sdcore_crc16_checker_sink_first $0\main_sdcore_crc16_checker_sink_first[0:0] - update \main_sdcore_crc16_checker_sink_last $0\main_sdcore_crc16_checker_sink_last[0:0] - update \main_sdcore_crc16_checker_sink_payload_data $0\main_sdcore_crc16_checker_sink_payload_data[7:0] - update \builder_sdcore_fsm_next_state $0\builder_sdcore_fsm_next_state[2:0] - update \main_sdcore_cmd_done_sdcore_fsm_next_value0 $0\main_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] - update \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $0\main_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] - update \main_sdcore_data_done_sdcore_fsm_next_value1 $0\main_sdcore_data_done_sdcore_fsm_next_value1[0:0] - update \main_sdcore_data_done_sdcore_fsm_next_value_ce1 $0\main_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] - update \main_sdcore_cmd_count_sdcore_fsm_next_value2 $0\main_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] - update \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $0\main_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] - update \main_sdcore_data_count_sdcore_fsm_next_value3 $0\main_sdcore_data_count_sdcore_fsm_next_value3[31:0] - update \main_sdcore_data_count_sdcore_fsm_next_value_ce3 $0\main_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] - update \main_sdcore_cmd_error_sdcore_fsm_next_value4 $0\main_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] - update \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $0\main_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] - update \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] - update \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $0\main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] - update \main_sdcore_data_error_sdcore_fsm_next_value6 $0\main_sdcore_data_error_sdcore_fsm_next_value6[0:0] - update \main_sdcore_data_error_sdcore_fsm_next_value_ce6 $0\main_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] - update \main_sdcore_data_timeout_sdcore_fsm_next_value7 $0\main_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] - update \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $0\main_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] - update \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] - update \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $0\main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] - end - attribute \src "ls180.v:531.11-531.68" - process $proc$ls180.v:531$3052 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] - end - attribute \src "ls180.v:532.5-532.64" - process $proc$ls180.v:532$3053 - assign { } { } - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0 - sync always - update \main_sdram_bankmachine1_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] - sync init - end - attribute \src "ls180.v:533.11-533.70" - process $proc$ls180.v:533$3054 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] - end - attribute \src "ls180.v:534.11-534.70" - process $proc$ls180.v:534$3055 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + update \sdram_cmd_ready $0\sdram_cmd_ready[0:0] + update \sdram_choose_req_want_reads $0\sdram_choose_req_want_reads[0:0] + update \sdram_choose_req_want_writes $0\sdram_choose_req_want_writes[0:0] + update \sdram_choose_req_want_activates $0\sdram_choose_req_want_activates[0:0] + update \sdram_choose_req_cmd_ready $0\sdram_choose_req_cmd_ready[0:0] + update \sdram_steerer_sel $0\sdram_steerer_sel[1:0] + update \sdram_en0 $0\sdram_en0[0:0] + update \sdram_en1 $0\sdram_en1[0:0] + update \subfragments_multiplexer_next_state $0\subfragments_multiplexer_next_state[2:0] end - attribute \src "ls180.v:535.11-535.73" - process $proc$ls180.v:535$3056 + attribute \src "ls180.v:2765.1-2778.4" + process $proc$ls180.v:2765$575 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:5482.1-5489.4" - process $proc$ls180.v:5482$1038 assign { } { } - assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 - attribute \src "ls180.v:5484.2-5488.5" - switch \main_sdblock2mem_fifo_replace - attribute \src "ls180.v:5484.6-5484.35" + assign $0\sdram_interface_wdata_we[1:0] 2'00 + assign $0\sdram_interface_wdata[15:0] 16'0000000000000000 + attribute \src "ls180.v:2768.2-2777.9" + switch \subfragments_new_master_wdata_ready + attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] $sub$ls180.v:5485$1039_Y - attribute \src "ls180.v:5486.6-5486.10" + assign $0\sdram_interface_wdata[15:0] \port_wdata_payload_data + assign $0\sdram_interface_wdata_we[1:0] \port_wdata_payload_we + attribute \src "ls180.v:0.0-0.0" case - assign $0\main_sdblock2mem_fifo_wrport_adr[4:0] \main_sdblock2mem_fifo_produce + assign $0\sdram_interface_wdata[15:0] 16'0000000000000000 + assign $0\sdram_interface_wdata_we[1:0] 2'00 end sync always - update \main_sdblock2mem_fifo_wrport_adr $0\main_sdblock2mem_fifo_wrport_adr[4:0] - end - attribute \src "ls180.v:55.5-55.42" - process $proc$ls180.v:55$2876 - assign { } { } - assign $1\main_libresocsim_reset_storage[0:0] 1'0 - sync always - sync init - update \main_libresocsim_reset_storage $1\main_libresocsim_reset_storage[0:0] + update \sdram_interface_wdata $0\sdram_interface_wdata[15:0] + update \sdram_interface_wdata_we $0\sdram_interface_wdata_we[1:0] end - attribute \src "ls180.v:5515.1-5554.4" - process $proc$ls180.v:5515$1049 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + attribute \src "ls180.v:2785.1-2795.4" + process $proc$ls180.v:2785$577 assign { } { } - assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] 0 - assign $0\main_sdblock2mem_sink_sink_payload_data1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 - assign { } { } - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 - assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 - assign $0\main_sdblock2mem_sink_sink_valid1[0:0] 1'0 - assign $0\builder_sdblock2memdma_next_state[1:0] \builder_sdblock2memdma_state - attribute \src "ls180.v:5525.2-5553.9" - switch \builder_sdblock2memdma_state - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\main_sdblock2mem_sink_sink_valid1[0:0] \main_sdblock2mem_wishbonedmawriter_sink_valid - assign $0\main_sdblock2mem_sink_sink_payload_data1[63:0] \main_sdblock2mem_wishbonedmawriter_sink_payload_data - assign $0\main_sdblock2mem_sink_sink_payload_address[31:0] $add$ls180.v:5529$1050_Y - assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] \main_sdblock2mem_sink_sink_ready1 - attribute \src "ls180.v:5531.4-5542.7" - switch $and$ls180.v:5531$1051_Y - attribute \src "ls180.v:5531.8-5531.103" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] $add$ls180.v:5532$1052_Y - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5534.5-5541.8" - switch $eq$ls180.v:5534$1054_Y - attribute \src "ls180.v:5534.9-5534.106" - case 1'1 - attribute \src "ls180.v:5535.6-5540.9" - switch \main_sdblock2mem_wishbonedmawriter_loop_storage - attribute \src "ls180.v:5535.10-5535.57" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5538.10-5538.14" - case - assign $0\builder_sdblock2memdma_next_state[1:0] 2'10 - end - case - end - case - end + assign $0\litedram_wb_dat_w[15:0] 16'0000000000000000 + attribute \src "ls180.v:2787.2-2794.9" + switch \converter_counter attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\main_sdblock2mem_wishbonedmawriter_status[0:0] 1'1 + case 1'0 + assign $0\litedram_wb_dat_w[15:0] \wb_sdram_dat_w [15:0] attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\litedram_wb_dat_w[15:0] \wb_sdram_dat_w [31:16] case - assign $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 - assign $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 - assign $0\builder_sdblock2memdma_next_state[1:0] 2'01 end sync always - update \main_sdblock2mem_sink_sink_valid1 $0\main_sdblock2mem_sink_sink_valid1[0:0] - update \main_sdblock2mem_sink_sink_payload_address $0\main_sdblock2mem_sink_sink_payload_address[31:0] - update \main_sdblock2mem_sink_sink_payload_data1 $0\main_sdblock2mem_sink_sink_payload_data1[63:0] - update \main_sdblock2mem_wishbonedmawriter_sink_ready $0\main_sdblock2mem_wishbonedmawriter_sink_ready[0:0] - update \main_sdblock2mem_wishbonedmawriter_status $0\main_sdblock2mem_wishbonedmawriter_status[0:0] - update \builder_sdblock2memdma_next_state $0\builder_sdblock2memdma_next_state[1:0] - update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] - update \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $0\main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] + update \litedram_wb_dat_w $0\litedram_wb_dat_w[15:0] end - attribute \src "ls180.v:556.5-556.59" - process $proc$ls180.v:556$3057 + attribute \src "ls180.v:279.12-279.41" + process $proc$ls180.v:279$1704 assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 + assign $1\sdram_slave_p0_rddata[15:0] 16'0000000000000000 sync always sync init - update \main_sdram_bankmachine1_cmd_buffer_source_valid $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] + update \sdram_slave_p0_rddata $1\sdram_slave_p0_rddata[15:0] end - attribute \src "ls180.v:5574.1-5611.4" - process $proc$ls180.v:5574$1056 - assign { } { } + attribute \src "ls180.v:2797.1-2843.4" + process $proc$ls180.v:2797$578 assign { } { } assign { } { } assign { } { } @@ -292430,2550 +265404,1762 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\converter_counter_subfragments_next_value[0:0] 1'0 + assign $0\converter_counter_subfragments_next_value_ce[0:0] 1'0 + assign $0\wb_sdram_ack[0:0] 1'0 + assign $0\litedram_wb_adr[29:0] 30'000000000000000000000000000000 + assign $0\litedram_wb_sel[1:0] 2'00 + assign $0\litedram_wb_cyc[0:0] 1'0 + assign $0\litedram_wb_stb[0:0] 1'0 + assign $0\litedram_wb_we[0:0] 1'0 + assign $0\converter_skip[0:0] 1'0 assign { } { } - assign $0\main_interface1_bus_adr[31:0] 0 - assign { } { } - assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'0 - assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\main_interface1_bus_sel[7:0] 8'00000000 - assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 - assign $0\main_interface1_bus_cyc[0:0] 1'0 - assign $0\main_interface1_bus_stb[0:0] 1'0 - assign $0\main_sdmem2block_dma_source_valid[0:0] 1'0 - assign $0\main_interface1_bus_we[0:0] 1'0 - assign $0\main_sdmem2block_dma_source_last[0:0] 1'0 - assign $0\main_sdmem2block_dma_source_payload_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] \builder_sdmem2blockdma_fsm_state - attribute \src "ls180.v:5588.2-5610.9" - switch \builder_sdmem2blockdma_fsm_state + assign $0\subfragments_next_state[0:0] \subfragments_state + attribute \src "ls180.v:2809.2-2842.9" + switch \subfragments_state attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_sdmem2block_dma_source_valid[0:0] 1'1 - assign $0\main_sdmem2block_dma_source_last[0:0] \main_sdmem2block_dma_sink_last - assign $0\main_sdmem2block_dma_source_payload_data[63:0] \main_sdmem2block_dma_data - attribute \src "ls180.v:5593.4-5596.7" - switch \main_sdmem2block_dma_source_ready - attribute \src "ls180.v:5593.8-5593.41" - case 1'1 - assign $0\main_sdmem2block_dma_sink_ready[0:0] 1'1 - assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 - case - end - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_interface1_bus_stb[0:0] \main_sdmem2block_dma_sink_valid - assign $0\main_interface1_bus_cyc[0:0] \main_sdmem2block_dma_sink_valid - assign $0\main_interface1_bus_we[0:0] 1'0 - assign $0\main_interface1_bus_sel[7:0] 8'11111111 - assign $0\main_interface1_bus_adr[31:0] \main_sdmem2block_dma_sink_payload_address - attribute \src "ls180.v:5604.4-5608.7" - switch $and$ls180.v:5604$1057_Y - attribute \src "ls180.v:5604.8-5604.59" + assign $0\litedram_wb_adr[29:0] { \wb_sdram_adr [28:0] \converter_counter } + attribute \src "ls180.v:2812.4-2819.11" + switch \converter_counter + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\litedram_wb_sel[1:0] \wb_sdram_sel [1:0] + attribute \src "ls180.v:0.0-0.0" case 1'1 - assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] { \main_interface1_bus_dat_r [7:0] \main_interface1_bus_dat_r [15:8] \main_interface1_bus_dat_r [23:16] \main_interface1_bus_dat_r [31:24] \main_interface1_bus_dat_r [39:32] \main_interface1_bus_dat_r [47:40] \main_interface1_bus_dat_r [55:48] \main_interface1_bus_dat_r [63:56] } - assign $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'1 - assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'1 + assign $0\litedram_wb_sel[1:0] \wb_sdram_sel [3:2] case end - end - sync always - update \main_interface1_bus_adr $0\main_interface1_bus_adr[31:0] - update \main_interface1_bus_sel $0\main_interface1_bus_sel[7:0] - update \main_interface1_bus_cyc $0\main_interface1_bus_cyc[0:0] - update \main_interface1_bus_stb $0\main_interface1_bus_stb[0:0] - update \main_interface1_bus_we $0\main_interface1_bus_we[0:0] - update \main_sdmem2block_dma_sink_ready $0\main_sdmem2block_dma_sink_ready[0:0] - update \main_sdmem2block_dma_source_valid $0\main_sdmem2block_dma_source_valid[0:0] - update \main_sdmem2block_dma_source_last $0\main_sdmem2block_dma_source_last[0:0] - update \main_sdmem2block_dma_source_payload_data $0\main_sdmem2block_dma_source_payload_data[63:0] - update \builder_sdmem2blockdma_fsm_next_state $0\builder_sdmem2blockdma_fsm_next_state[0:0] - update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[63:0] - update \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $0\main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] - end - attribute \src "ls180.v:558.5-558.59" - process $proc$ls180.v:558$3058 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_source_first $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] - end - attribute \src "ls180.v:559.5-559.58" - process $proc$ls180.v:559$3059 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_source_last $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] - end - attribute \src "ls180.v:56.5-56.37" - process $proc$ls180.v:56$2877 - assign { } { } - assign $1\main_libresocsim_reset_re[0:0] 1'0 - sync always - sync init - update \main_libresocsim_reset_re $1\main_libresocsim_reset_re[0:0] - end - attribute \src "ls180.v:560.5-560.64" - process $proc$ls180.v:560$3060 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] - end - attribute \src "ls180.v:561.12-561.74" - process $proc$ls180.v:561$3061 - assign { } { } - assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 - sync always - sync init - update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] - end - attribute \src "ls180.v:5612.1-5648.4" - process $proc$ls180.v:5612$1058 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdmem2block_dma_sink_payload_address[31:0] 0 - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 - assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'0 - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 - assign { } { } - assign $0\main_sdmem2block_dma_done_status[0:0] 1'0 - assign $0\main_sdmem2block_dma_sink_last[0:0] 1'0 - assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] \builder_sdmem2blockdma_resetinserter_state - attribute \src "ls180.v:5621.2-5647.9" - switch \builder_sdmem2blockdma_resetinserter_state - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\main_sdmem2block_dma_sink_valid[0:0] 1'1 - assign $0\main_sdmem2block_dma_sink_last[0:0] $eq$ls180.v:5624$1060_Y - assign $0\main_sdmem2block_dma_sink_payload_address[31:0] $add$ls180.v:5625$1061_Y - attribute \src "ls180.v:5626.4-5637.7" - switch \main_sdmem2block_dma_sink_ready - attribute \src "ls180.v:5626.8-5626.39" + attribute \src "ls180.v:2820.4-2833.7" + switch $and$ls180.v:2820$579_Y + attribute \src "ls180.v:2820.8-2820.37" case 1'1 - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] $add$ls180.v:5627$1062_Y - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5629.5-5636.8" - switch \main_sdmem2block_dma_sink_last - attribute \src "ls180.v:5629.9-5629.39" + assign $0\converter_skip[0:0] $eq$ls180.v:2821$580_Y + assign $0\litedram_wb_we[0:0] \wb_sdram_we + assign $0\litedram_wb_cyc[0:0] $not$ls180.v:2823$581_Y + assign $0\litedram_wb_stb[0:0] $not$ls180.v:2824$582_Y + attribute \src "ls180.v:2825.5-2832.8" + switch $or$ls180.v:2825$583_Y + attribute \src "ls180.v:2825.9-2825.43" case 1'1 - attribute \src "ls180.v:5630.6-5635.9" - switch \main_sdmem2block_dma_loop_storage - attribute \src "ls180.v:5630.10-5630.43" + assign $0\converter_counter_subfragments_next_value[0:0] $add$ls180.v:2826$584_Y + assign $0\converter_counter_subfragments_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2828.6-2831.9" + switch $eq$ls180.v:2828$585_Y + attribute \src "ls180.v:2828.10-2828.37" case 1'1 - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 - attribute \src "ls180.v:5633.10-5633.14" + assign $0\wb_sdram_ack[0:0] 1'1 + assign $0\subfragments_next_state[0:0] 1'0 case - assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'10 end case end case end attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\main_sdmem2block_dma_done_status[0:0] 1'1 - attribute \src "ls180.v:0.0-0.0" case - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 - assign $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 - assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'01 + assign $0\converter_counter_subfragments_next_value[0:0] 1'0 + assign $0\converter_counter_subfragments_next_value_ce[0:0] 1'1 + attribute \src "ls180.v:2838.4-2840.7" + switch $and$ls180.v:2838$586_Y + attribute \src "ls180.v:2838.8-2838.37" + case 1'1 + assign $0\subfragments_next_state[0:0] 1'1 + case + end end sync always - update \main_sdmem2block_dma_sink_valid $0\main_sdmem2block_dma_sink_valid[0:0] - update \main_sdmem2block_dma_sink_last $0\main_sdmem2block_dma_sink_last[0:0] - update \main_sdmem2block_dma_sink_payload_address $0\main_sdmem2block_dma_sink_payload_address[31:0] - update \main_sdmem2block_dma_done_status $0\main_sdmem2block_dma_done_status[0:0] - update \builder_sdmem2blockdma_resetinserter_next_state $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] - update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] - update \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $0\main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] + update \wb_sdram_ack $0\wb_sdram_ack[0:0] + update \litedram_wb_adr $0\litedram_wb_adr[29:0] + update \litedram_wb_sel $0\litedram_wb_sel[1:0] + update \litedram_wb_cyc $0\litedram_wb_cyc[0:0] + update \litedram_wb_stb $0\litedram_wb_stb[0:0] + update \litedram_wb_we $0\litedram_wb_we[0:0] + update \converter_skip $0\converter_skip[0:0] + update \subfragments_next_state $0\subfragments_next_state[0:0] + update \converter_counter_subfragments_next_value $0\converter_counter_subfragments_next_value[0:0] + update \converter_counter_subfragments_next_value_ce $0\converter_counter_subfragments_next_value_ce[0:0] end - attribute \src "ls180.v:562.12-562.47" - process $proc$ls180.v:562$3062 + attribute \src "ls180.v:280.5-280.39" + process $proc$ls180.v:280$1705 assign { } { } - assign $1\main_sdram_bankmachine1_row[12:0] 13'0000000000000 + assign $1\sdram_slave_p0_rddata_valid[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_row $1\main_sdram_bankmachine1_row[12:0] + update \sdram_slave_p0_rddata_valid $1\sdram_slave_p0_rddata_valid[0:0] end - attribute \src "ls180.v:563.5-563.46" - process $proc$ls180.v:563$3063 + attribute \src "ls180.v:281.12-281.43" + process $proc$ls180.v:281$1706 assign { } { } - assign $1\main_sdram_bankmachine1_row_opened[0:0] 1'0 + assign $1\sdram_master_p0_address[12:0] 13'0000000000000 sync always sync init - update \main_sdram_bankmachine1_row_opened $1\main_sdram_bankmachine1_row_opened[0:0] + update \sdram_master_p0_address $1\sdram_master_p0_address[12:0] end - attribute \src "ls180.v:565.5-565.44" - process $proc$ls180.v:565$3064 + attribute \src "ls180.v:282.11-282.38" + process $proc$ls180.v:282$1707 assign { } { } - assign $1\main_sdram_bankmachine1_row_open[0:0] 1'0 + assign $1\sdram_master_p0_bank[1:0] 2'00 sync always sync init - update \main_sdram_bankmachine1_row_open $1\main_sdram_bankmachine1_row_open[0:0] + update \sdram_master_p0_bank $1\sdram_master_p0_bank[1:0] end - attribute \src "ls180.v:566.5-566.45" - process $proc$ls180.v:566$3065 + attribute \src "ls180.v:283.5-283.33" + process $proc$ls180.v:283$1708 assign { } { } - assign $1\main_sdram_bankmachine1_row_close[0:0] 1'0 + assign $1\sdram_master_p0_cas_n[0:0] 1'1 sync always sync init - update \main_sdram_bankmachine1_row_close $1\main_sdram_bankmachine1_row_close[0:0] + update \sdram_master_p0_cas_n $1\sdram_master_p0_cas_n[0:0] end - attribute \src "ls180.v:5660.1-5688.4" - process $proc$ls180.v:5660$1068 + attribute \src "ls180.v:284.5-284.32" + process $proc$ls180.v:284$1709 assign { } { } - assign $0\main_sdmem2block_converter_source_payload_data[7:0] 8'00000000 - attribute \src "ls180.v:5662.2-5687.9" - switch \main_sdmem2block_converter_mux - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [63:56] - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [55:48] - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [47:40] - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [39:32] - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [31:24] - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [23:16] - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [15:8] - attribute \src "ls180.v:0.0-0.0" - case - assign $0\main_sdmem2block_converter_source_payload_data[7:0] \main_sdmem2block_converter_sink_payload_data [7:0] - end + assign $1\sdram_master_p0_cs_n[0:0] 1'1 sync always - update \main_sdmem2block_converter_source_payload_data $0\main_sdmem2block_converter_source_payload_data[7:0] + sync init + update \sdram_master_p0_cs_n $1\sdram_master_p0_cs_n[0:0] end - attribute \src "ls180.v:567.5-567.54" - process $proc$ls180.v:567$3066 + attribute \src "ls180.v:285.5-285.33" + process $proc$ls180.v:285$1710 assign { } { } - assign $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 + assign $1\sdram_master_p0_ras_n[0:0] 1'1 sync always sync init - update \main_sdram_bankmachine1_row_col_n_addr_sel $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] + update \sdram_master_p0_ras_n $1\sdram_master_p0_ras_n[0:0] end - attribute \src "ls180.v:569.32-569.76" - process $proc$ls180.v:569$3067 + attribute \src "ls180.v:286.5-286.32" + process $proc$ls180.v:286$1711 assign { } { } - assign $1\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 + assign $1\sdram_master_p0_we_n[0:0] 1'1 sync always sync init - update \main_sdram_bankmachine1_twtpcon_ready $1\main_sdram_bankmachine1_twtpcon_ready[0:0] + update \sdram_master_p0_we_n $1\sdram_master_p0_we_n[0:0] end - attribute \src "ls180.v:57.12-57.60" - process $proc$ls180.v:57$2878 + attribute \src "ls180.v:287.5-287.31" + process $proc$ls180.v:287$1712 assign { } { } - assign $1\main_libresocsim_scratch_storage[31:0] 305419896 + assign $1\sdram_master_p0_cke[0:0] 1'0 sync always sync init - update \main_libresocsim_scratch_storage $1\main_libresocsim_scratch_storage[31:0] + update \sdram_master_p0_cke $1\sdram_master_p0_cke[0:0] end - attribute \src "ls180.v:570.11-570.55" - process $proc$ls180.v:570$3068 + attribute \src "ls180.v:288.5-288.31" + process $proc$ls180.v:288$1713 assign { } { } - assign $1\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 + assign $1\sdram_master_p0_odt[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine1_twtpcon_count $1\main_sdram_bankmachine1_twtpcon_count[2:0] + update \sdram_master_p0_odt $1\sdram_master_p0_odt[0:0] end - attribute \src "ls180.v:5702.1-5709.4" - process $proc$ls180.v:5702$1069 + attribute \src "ls180.v:2888.1-2893.4" + process $proc$ls180.v:2888$618 assign { } { } - assign $0\main_sdmem2block_fifo_wrport_adr[4:0] 5'00000 - attribute \src "ls180.v:5704.2-5708.5" - switch \main_sdmem2block_fifo_replace - attribute \src "ls180.v:5704.6-5704.35" + assign $0\tx_clear[0:0] 1'0 + attribute \src "ls180.v:2890.2-2892.5" + switch $and$ls180.v:2890$619_Y + attribute \src "ls180.v:2890.6-2890.59" case 1'1 - assign $0\main_sdmem2block_fifo_wrport_adr[4:0] $sub$ls180.v:5705$1070_Y - attribute \src "ls180.v:5706.6-5706.10" - case - assign $0\main_sdmem2block_fifo_wrport_adr[4:0] \main_sdmem2block_fifo_produce - end - sync always - update \main_sdmem2block_fifo_wrport_adr $0\main_sdmem2block_fifo_wrport_adr[4:0] - end - attribute \src "ls180.v:5717.1-5753.4" - process $proc$ls180.v:5717$1076 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\builder_libresocsim_wishbone_ack[0:0] 1'0 - assign { } { } - assign $0\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 - assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 - assign $0\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 - assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 - assign $0\builder_libresocsim_we_next_value2[0:0] 1'0 - assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'0 - assign $0\builder_libresocsim_wishbone_dat_r[31:0] 0 - assign $0\builder_next_state[1:0] \builder_state - attribute \src "ls180.v:5728.2-5752.9" - switch \builder_state - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 - assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'1 - assign $0\builder_libresocsim_we_next_value2[0:0] 1'0 - assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'1 - assign $0\builder_next_state[1:0] 2'10 - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_libresocsim_wishbone_ack[0:0] 1'1 - assign $0\builder_libresocsim_wishbone_dat_r[31:0] { 24'000000000000000000000000 \builder_libresocsim_dat_r } - assign $0\builder_next_state[1:0] 2'00 - attribute \src "ls180.v:0.0-0.0" + assign $0\tx_clear[0:0] 1'1 case - assign $0\builder_libresocsim_dat_w_next_value0[7:0] \builder_libresocsim_wishbone_dat_w [7:0] - assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'1 - attribute \src "ls180.v:5744.4-5750.7" - switch $and$ls180.v:5744$1077_Y - attribute \src "ls180.v:5744.8-5744.77" - case 1'1 - assign $0\builder_libresocsim_adr_next_value1[13:0] \builder_libresocsim_wishbone_adr [13:0] - assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'1 - assign $0\builder_libresocsim_we_next_value2[0:0] $and$ls180.v:5747$1079_Y - assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'1 - assign $0\builder_next_state[1:0] 2'01 - case - end end sync always - update \builder_libresocsim_wishbone_dat_r $0\builder_libresocsim_wishbone_dat_r[31:0] - update \builder_libresocsim_wishbone_ack $0\builder_libresocsim_wishbone_ack[0:0] - update \builder_next_state $0\builder_next_state[1:0] - update \builder_libresocsim_dat_w_next_value0 $0\builder_libresocsim_dat_w_next_value0[7:0] - update \builder_libresocsim_dat_w_next_value_ce0 $0\builder_libresocsim_dat_w_next_value_ce0[0:0] - update \builder_libresocsim_adr_next_value1 $0\builder_libresocsim_adr_next_value1[13:0] - update \builder_libresocsim_adr_next_value_ce1 $0\builder_libresocsim_adr_next_value_ce1[0:0] - update \builder_libresocsim_we_next_value2 $0\builder_libresocsim_we_next_value2[0:0] - update \builder_libresocsim_we_next_value_ce2 $0\builder_libresocsim_we_next_value_ce2[0:0] + update \tx_clear $0\tx_clear[0:0] end - attribute \src "ls180.v:572.32-572.75" - process $proc$ls180.v:572$3069 + attribute \src "ls180.v:289.5-289.35" + process $proc$ls180.v:289$1714 assign { } { } - assign $0\main_sdram_bankmachine1_trccon_ready[0:0] 1'1 + assign $1\sdram_master_p0_reset_n[0:0] 1'0 sync always - update \main_sdram_bankmachine1_trccon_ready $0\main_sdram_bankmachine1_trccon_ready[0:0] sync init + update \sdram_master_p0_reset_n $1\sdram_master_p0_reset_n[0:0] end - attribute \src "ls180.v:574.32-574.76" - process $proc$ls180.v:574$3070 + attribute \src "ls180.v:2894.1-2898.4" + process $proc$ls180.v:2894$620 + assign { } { } assign { } { } - assign $0\main_sdram_bankmachine1_trascon_ready[0:0] 1'1 + assign $0\eventmanager_status_w[1:0] [0] \tx_status + assign $0\eventmanager_status_w[1:0] [1] \rx_status sync always - update \main_sdram_bankmachine1_trascon_ready $0\main_sdram_bankmachine1_trascon_ready[0:0] - sync init + update \eventmanager_status_w $0\eventmanager_status_w[1:0] end - attribute \src "ls180.v:5778.1-5786.4" - process $proc$ls180.v:5778$1100 - assign { } { } + attribute \src "ls180.v:2899.1-2904.4" + process $proc$ls180.v:2899$621 assign { } { } - assign $0\builder_slave_sel[5:0] [0] $eq$ls180.v:5780$1101_Y - assign $0\builder_slave_sel[5:0] [1] $eq$ls180.v:5781$1102_Y - assign $0\builder_slave_sel[5:0] [2] $eq$ls180.v:5782$1103_Y - assign $0\builder_slave_sel[5:0] [3] $eq$ls180.v:5783$1104_Y - assign $0\builder_slave_sel[5:0] [4] $eq$ls180.v:5784$1105_Y - assign $0\builder_slave_sel[5:0] [5] $eq$ls180.v:5785$1106_Y + assign $0\rx_clear[0:0] 1'0 + attribute \src "ls180.v:2901.2-2903.5" + switch $and$ls180.v:2901$622_Y + attribute \src "ls180.v:2901.6-2901.59" + case 1'1 + assign $0\rx_clear[0:0] 1'1 + case + end sync always - update \builder_slave_sel $0\builder_slave_sel[5:0] + update \rx_clear $0\rx_clear[0:0] end - attribute \src "ls180.v:58.5-58.39" - process $proc$ls180.v:58$2879 + attribute \src "ls180.v:290.5-290.33" + process $proc$ls180.v:290$1715 assign { } { } - assign $1\main_libresocsim_scratch_re[0:0] 1'0 + assign $1\sdram_master_p0_act_n[0:0] 1'1 sync always sync init - update \main_libresocsim_scratch_re $1\main_libresocsim_scratch_re[0:0] + update \sdram_master_p0_act_n $1\sdram_master_p0_act_n[0:0] end - attribute \src "ls180.v:580.5-580.51" - process $proc$ls180.v:580$3071 + attribute \src "ls180.v:2905.1-2909.4" + process $proc$ls180.v:2905$623 + assign { } { } assign { } { } - assign $1\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 + assign $0\eventmanager_pending_w[1:0] [0] \tx_pending + assign $0\eventmanager_pending_w[1:0] [1] \rx_pending sync always - sync init - update \main_sdram_bankmachine2_req_wdata_ready $1\main_sdram_bankmachine2_req_wdata_ready[0:0] + update \eventmanager_pending_w $0\eventmanager_pending_w[1:0] end - attribute \src "ls180.v:581.5-581.51" - process $proc$ls180.v:581$3072 + attribute \src "ls180.v:291.12-291.42" + process $proc$ls180.v:291$1716 assign { } { } - assign $1\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 + assign $1\sdram_master_p0_wrdata[15:0] 16'0000000000000000 sync always sync init - update \main_sdram_bankmachine2_req_rdata_valid $1\main_sdram_bankmachine2_req_rdata_valid[0:0] + update \sdram_master_p0_wrdata $1\sdram_master_p0_wrdata[15:0] end - attribute \src "ls180.v:583.5-583.47" - process $proc$ls180.v:583$3073 + attribute \src "ls180.v:292.5-292.37" + process $proc$ls180.v:292$1717 assign { } { } - assign $1\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 + assign $1\sdram_master_p0_wrdata_en[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_refresh_gnt $1\main_sdram_bankmachine2_refresh_gnt[0:0] + update \sdram_master_p0_wrdata_en $1\sdram_master_p0_wrdata_en[0:0] end - attribute \src "ls180.v:5837.1-5848.4" - process $proc$ls180.v:5837$1121 - assign { } { } + attribute \src "ls180.v:2927.1-2934.4" + process $proc$ls180.v:2927$631 assign { } { } - assign { } { } - assign { } { } - assign $0\builder_error[0:0] 1'0 - assign { } { } - assign $0\builder_shared_ack[0:0] $or$ls180.v:5841$1126_Y - assign $0\builder_shared_dat_r[31:0] $or$ls180.v:5842$1137_Y [31:0] - attribute \src "ls180.v:5843.2-5847.5" - switch \builder_done - attribute \src "ls180.v:5843.6-5843.18" + assign $0\tx_fifo_wrport_adr[3:0] 4'0000 + attribute \src "ls180.v:2929.2-2933.5" + switch \tx_fifo_replace + attribute \src "ls180.v:2929.6-2929.21" case 1'1 - assign $0\builder_shared_dat_r[31:0] 32'11111111111111111111111111111111 - assign $0\builder_shared_ack[0:0] 1'1 - assign $0\builder_error[0:0] 1'1 + assign $0\tx_fifo_wrport_adr[3:0] $sub$ls180.v:2930$632_Y + attribute \src "ls180.v:2931.6-2931.10" case + assign $0\tx_fifo_wrport_adr[3:0] \tx_fifo_produce end sync always - update \builder_shared_dat_r $0\builder_shared_dat_r[31:0] - update \builder_shared_ack $0\builder_shared_ack[0:0] - update \builder_error $0\builder_error[0:0] + update \tx_fifo_wrport_adr $0\tx_fifo_wrport_adr[3:0] end - attribute \src "ls180.v:584.5-584.45" - process $proc$ls180.v:584$3074 + attribute \src "ls180.v:293.11-293.45" + process $proc$ls180.v:293$1718 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 + assign $1\sdram_master_p0_wrdata_mask[1:0] 2'00 sync always sync init - update \main_sdram_bankmachine2_cmd_valid $1\main_sdram_bankmachine2_cmd_valid[0:0] + update \sdram_master_p0_wrdata_mask $1\sdram_master_p0_wrdata_mask[1:0] end - attribute \src "ls180.v:585.5-585.45" - process $proc$ls180.v:585$3075 + attribute \src "ls180.v:294.5-294.37" + process $proc$ls180.v:294$1719 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 + assign $1\sdram_master_p0_rddata_en[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_cmd_ready $1\main_sdram_bankmachine2_cmd_ready[0:0] + update \sdram_master_p0_rddata_en $1\sdram_master_p0_rddata_en[0:0] end - attribute \src "ls180.v:586.12-586.57" - process $proc$ls180.v:586$3076 + attribute \src "ls180.v:2957.1-2964.4" + process $proc$ls180.v:2957$642 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 + assign $0\rx_fifo_wrport_adr[3:0] 4'0000 + attribute \src "ls180.v:2959.2-2963.5" + switch \rx_fifo_replace + attribute \src "ls180.v:2959.6-2959.21" + case 1'1 + assign $0\rx_fifo_wrport_adr[3:0] $sub$ls180.v:2960$643_Y + attribute \src "ls180.v:2961.6-2961.10" + case + assign $0\rx_fifo_wrport_adr[3:0] \rx_fifo_produce + end sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_a $1\main_sdram_bankmachine2_cmd_payload_a[12:0] + update \rx_fifo_wrport_adr $0\rx_fifo_wrport_adr[3:0] end - attribute \src "ls180.v:588.5-588.51" - process $proc$ls180.v:588$3077 + attribute \src "ls180.v:2973.1-2983.4" + process $proc$ls180.v:2973$649 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_cas $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:589.5-589.51" - process $proc$ls180.v:589$3078 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 + assign $0\gpio0_pads_gpio0i[7:0] [0] \libresocsim_libresoc_constraintmanager_obj_gpio_i [0] + assign $0\gpio0_pads_gpio0i[7:0] [1] \libresocsim_libresoc_constraintmanager_obj_gpio_i [1] + assign $0\gpio0_pads_gpio0i[7:0] [2] \libresocsim_libresoc_constraintmanager_obj_gpio_i [2] + assign $0\gpio0_pads_gpio0i[7:0] [3] \libresocsim_libresoc_constraintmanager_obj_gpio_i [3] + assign $0\gpio0_pads_gpio0i[7:0] [4] \libresocsim_libresoc_constraintmanager_obj_gpio_i [4] + assign $0\gpio0_pads_gpio0i[7:0] [5] \libresocsim_libresoc_constraintmanager_obj_gpio_i [5] + assign $0\gpio0_pads_gpio0i[7:0] [6] \libresocsim_libresoc_constraintmanager_obj_gpio_i [6] + assign $0\gpio0_pads_gpio0i[7:0] [7] \libresocsim_libresoc_constraintmanager_obj_gpio_i [7] sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_ras $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] + update \gpio0_pads_gpio0i $0\gpio0_pads_gpio0i[7:0] end - attribute \src "ls180.v:590.5-590.50" - process $proc$ls180.v:590$3079 + attribute \src "ls180.v:2984.1-2994.4" + process $proc$ls180.v:2984$650 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_we $1\main_sdram_bankmachine2_cmd_payload_we[0:0] - end - attribute \src "ls180.v:591.5-591.54" - process $proc$ls180.v:591$3080 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 + assign $0\gpio1_pads_gpio1i[7:0] [0] \libresocsim_libresoc_constraintmanager_obj_gpio_i [8] + assign $0\gpio1_pads_gpio1i[7:0] [1] \libresocsim_libresoc_constraintmanager_obj_gpio_i [9] + assign $0\gpio1_pads_gpio1i[7:0] [2] \libresocsim_libresoc_constraintmanager_obj_gpio_i [10] + assign $0\gpio1_pads_gpio1i[7:0] [3] \libresocsim_libresoc_constraintmanager_obj_gpio_i [11] + assign $0\gpio1_pads_gpio1i[7:0] [4] \libresocsim_libresoc_constraintmanager_obj_gpio_i [12] + assign $0\gpio1_pads_gpio1i[7:0] [5] \libresocsim_libresoc_constraintmanager_obj_gpio_i [13] + assign $0\gpio1_pads_gpio1i[7:0] [6] \libresocsim_libresoc_constraintmanager_obj_gpio_i [14] + assign $0\gpio1_pads_gpio1i[7:0] [7] \libresocsim_libresoc_constraintmanager_obj_gpio_i [15] sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_is_cmd $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] + update \gpio1_pads_gpio1i $0\gpio1_pads_gpio1i[7:0] end - attribute \src "ls180.v:592.5-592.55" - process $proc$ls180.v:592$3081 + attribute \src "ls180.v:2995.1-3013.4" + process $proc$ls180.v:2995$651 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_is_read $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] - end - attribute \src "ls180.v:593.5-593.56" - process $proc$ls180.v:593$3082 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 + assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_o[15:0] [0] \gpio0_pads_gpio0o [0] + assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_o[15:0] [1] \gpio0_pads_gpio0o [1] + assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_o[15:0] [2] \gpio0_pads_gpio0o [2] + assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_o[15:0] [3] \gpio0_pads_gpio0o [3] + assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_o[15:0] [4] \gpio0_pads_gpio0o [4] + assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_o[15:0] [5] \gpio0_pads_gpio0o [5] + assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_o[15:0] [6] \gpio0_pads_gpio0o [6] + assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_o[15:0] [7] \gpio0_pads_gpio0o [7] + assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_o[15:0] [8] \gpio1_pads_gpio1o [0] + assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_o[15:0] [9] \gpio1_pads_gpio1o [1] + assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_o[15:0] [10] \gpio1_pads_gpio1o [2] + assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_o[15:0] [11] \gpio1_pads_gpio1o [3] + assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_o[15:0] [12] \gpio1_pads_gpio1o [4] + assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_o[15:0] [13] \gpio1_pads_gpio1o [5] + assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_o[15:0] [14] \gpio1_pads_gpio1o [6] + assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_o[15:0] [15] \gpio1_pads_gpio1o [7] sync always - sync init - update \main_sdram_bankmachine2_cmd_payload_is_write $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] + update \libresocsim_libresoc_constraintmanager_obj_gpio_o $0\libresocsim_libresoc_constraintmanager_obj_gpio_o[15:0] end - attribute \src "ls180.v:594.5-594.50" - process $proc$ls180.v:594$3083 + attribute \src "ls180.v:301.11-301.31" + process $proc$ls180.v:301$1720 assign { } { } - assign $1\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 + assign $1\sdram_storage[3:0] 4'0001 sync always sync init - update \main_sdram_bankmachine2_auto_precharge $1\main_sdram_bankmachine2_auto_precharge[0:0] + update \sdram_storage $1\sdram_storage[3:0] end - attribute \src "ls180.v:597.5-597.67" - process $proc$ls180.v:597$3084 + attribute \src "ls180.v:3014.1-3032.4" + process $proc$ls180.v:3014$652 assign { } { } - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] 1'0 - sync always - update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] - sync init - end - attribute \src "ls180.v:598.5-598.66" - process $proc$ls180.v:598$3085 assign { } { } - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] 1'0 + assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_oe[15:0] [0] \gpio0_pads_gpio0oe [0] + assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_oe[15:0] [1] \gpio0_pads_gpio0oe [1] + assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_oe[15:0] [2] \gpio0_pads_gpio0oe [2] + assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_oe[15:0] [3] \gpio0_pads_gpio0oe [3] + assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_oe[15:0] [4] \gpio0_pads_gpio0oe [4] + assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_oe[15:0] [5] \gpio0_pads_gpio0oe [5] + assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_oe[15:0] [6] \gpio0_pads_gpio0oe [6] + assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_oe[15:0] [7] \gpio0_pads_gpio0oe [7] + assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_oe[15:0] [8] \gpio1_pads_gpio1oe [0] + assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_oe[15:0] [9] \gpio1_pads_gpio1oe [1] + assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_oe[15:0] [10] \gpio1_pads_gpio1oe [2] + assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_oe[15:0] [11] \gpio1_pads_gpio1oe [3] + assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_oe[15:0] [12] \gpio1_pads_gpio1oe [4] + assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_oe[15:0] [13] \gpio1_pads_gpio1oe [5] + assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_oe[15:0] [14] \gpio1_pads_gpio1oe [6] + assign $0\libresocsim_libresoc_constraintmanager_obj_gpio_oe[15:0] [15] \gpio1_pads_gpio1oe [7] sync always - update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] - sync init + update \libresocsim_libresoc_constraintmanager_obj_gpio_oe $0\libresocsim_libresoc_constraintmanager_obj_gpio_oe[15:0] end - attribute \src "ls180.v:613.11-613.68" - process $proc$ls180.v:613$3086 + attribute \src "ls180.v:302.5-302.20" + process $proc$ls180.v:302$1721 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $1\sdram_re[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + update \sdram_re $1\sdram_re[0:0] end - attribute \src "ls180.v:614.5-614.64" - process $proc$ls180.v:614$3087 + attribute \src "ls180.v:303.11-303.39" + process $proc$ls180.v:303$1722 assign { } { } - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] 1'0 + assign $1\sdram_command_storage[5:0] 6'000000 sync always - update \main_sdram_bankmachine2_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] sync init + update \sdram_command_storage $1\sdram_command_storage[5:0] end - attribute \src "ls180.v:615.11-615.70" - process $proc$ls180.v:615$3088 + attribute \src "ls180.v:3037.1-3073.4" + process $proc$ls180.v:3037$653 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] - end - attribute \src "ls180.v:616.11-616.70" - process $proc$ls180.v:616$3089 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] - end - attribute \src "ls180.v:617.11-617.73" - process $proc$ls180.v:617$3090 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] - end - attribute \src "ls180.v:63.12-63.47" - process $proc$ls180.v:63$2880 assign { } { } - assign $1\main_libresocsim_bus_errors[31:0] 0 - sync always - sync init - update \main_libresocsim_bus_errors $1\main_libresocsim_bus_errors[31:0] - end - attribute \src "ls180.v:6362.1-6367.4" - process $proc$ls180.v:6362$2011 assign { } { } - assign $0\main_spimaster9_start[0:0] 1'0 - attribute \src "ls180.v:6364.2-6366.5" - switch \main_spimaster12_re - attribute \src "ls180.v:6364.6-6364.25" - case 1'1 - assign $0\main_spimaster9_start[0:0] \main_spimaster11_storage [0] - case - end - sync always - update \main_spimaster9_start $0\main_spimaster9_start[0:0] - end - attribute \src "ls180.v:638.5-638.59" - process $proc$ls180.v:638$3091 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_valid $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] - end - attribute \src "ls180.v:640.5-640.59" - process $proc$ls180.v:640$3092 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine2_cmd_buffer_source_first $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] - end - attribute \src "ls180.v:6408.1-6413.4" - process $proc$ls180.v:6408$2076 assign { } { } - assign $0\main_spisdcard_start1[0:0] 1'0 - attribute \src "ls180.v:6410.2-6412.5" - switch \main_spisdcard_control_re - attribute \src "ls180.v:6410.6-6410.31" - case 1'1 - assign $0\main_spisdcard_start1[0:0] \main_spisdcard_control_storage [0] + assign { } { } + assign $0\libresocsim_libresocsim_wishbone_dat_r[31:0] 0 + assign $0\libresocsim_libresocsim_wishbone_ack[0:0] 1'0 + assign { } { } + assign $0\libresocsim_libresocsim_dat_w_libresocsim_next_value0[7:0] 8'00000000 + assign $0\libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0[0:0] 1'0 + assign $0\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0] 14'00000000000000 + assign $0\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0] 1'0 + assign $0\libresocsim_libresocsim_we_libresocsim_next_value2[0:0] 1'0 + assign $0\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0] 1'0 + assign $0\libresocsim_next_state[1:0] \libresocsim_state + attribute \src "ls180.v:3048.2-3072.9" + switch \libresocsim_state + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0] 14'00000000000000 + assign $0\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0] 1'1 + assign $0\libresocsim_libresocsim_we_libresocsim_next_value2[0:0] 1'0 + assign $0\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0] 1'1 + assign $0\libresocsim_next_state[1:0] 2'10 + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\libresocsim_libresocsim_wishbone_ack[0:0] 1'1 + assign $0\libresocsim_libresocsim_wishbone_dat_r[31:0] { 24'000000000000000000000000 \libresocsim_libresocsim_dat_r } + assign $0\libresocsim_next_state[1:0] 2'00 + attribute \src "ls180.v:0.0-0.0" case + assign $0\libresocsim_libresocsim_dat_w_libresocsim_next_value0[7:0] \libresocsim_libresocsim_wishbone_dat_w [7:0] + assign $0\libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0[0:0] 1'1 + attribute \src "ls180.v:3064.4-3070.7" + switch $and$ls180.v:3064$654_Y + attribute \src "ls180.v:3064.8-3064.85" + case 1'1 + assign $0\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0] \libresocsim_libresocsim_wishbone_adr [13:0] + assign $0\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0] 1'1 + assign $0\libresocsim_libresocsim_we_libresocsim_next_value2[0:0] $and$ls180.v:3067$656_Y + assign $0\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0] 1'1 + assign $0\libresocsim_next_state[1:0] 2'01 + case + end end sync always - update \main_spisdcard_start1 $0\main_spisdcard_start1[0:0] + update \libresocsim_libresocsim_wishbone_dat_r $0\libresocsim_libresocsim_wishbone_dat_r[31:0] + update \libresocsim_libresocsim_wishbone_ack $0\libresocsim_libresocsim_wishbone_ack[0:0] + update \libresocsim_next_state $0\libresocsim_next_state[1:0] + update \libresocsim_libresocsim_dat_w_libresocsim_next_value0 $0\libresocsim_libresocsim_dat_w_libresocsim_next_value0[7:0] + update \libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0 $0\libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0[0:0] + update \libresocsim_libresocsim_adr_libresocsim_next_value1 $0\libresocsim_libresocsim_adr_libresocsim_next_value1[13:0] + update \libresocsim_libresocsim_adr_libresocsim_next_value_ce1 $0\libresocsim_libresocsim_adr_libresocsim_next_value_ce1[0:0] + update \libresocsim_libresocsim_we_libresocsim_next_value2 $0\libresocsim_libresocsim_we_libresocsim_next_value2[0:0] + update \libresocsim_libresocsim_we_libresocsim_next_value_ce2 $0\libresocsim_libresocsim_we_libresocsim_next_value_ce2[0:0] end - attribute \src "ls180.v:641.5-641.58" - process $proc$ls180.v:641$3093 + attribute \src "ls180.v:304.5-304.28" + process $proc$ls180.v:304$1723 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0 + assign $1\sdram_command_re[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_cmd_buffer_source_last $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] + update \sdram_command_re $1\sdram_command_re[0:0] end - attribute \src "ls180.v:642.5-642.64" - process $proc$ls180.v:642$3094 + attribute \src "ls180.v:308.5-308.33" + process $proc$ls180.v:308$1724 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0 + assign $0\sdram_command_issue_w[0:0] 1'0 sync always + update \sdram_command_issue_w $0\sdram_command_issue_w[0:0] sync init - update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] end - attribute \src "ls180.v:643.12-643.74" - process $proc$ls180.v:643$3095 + attribute \src "ls180.v:309.12-309.41" + process $proc$ls180.v:309$1725 assign { } { } - assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + assign $1\sdram_address_storage[12:0] 13'0000000000000 sync always sync init - update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + update \sdram_address_storage $1\sdram_address_storage[12:0] end - attribute \src "ls180.v:644.12-644.47" - process $proc$ls180.v:644$3096 + attribute \src "ls180.v:3092.1-3100.4" + process $proc$ls180.v:3092$669 assign { } { } - assign $1\main_sdram_bankmachine2_row[12:0] 13'0000000000000 - sync always - sync init - update \main_sdram_bankmachine2_row $1\main_sdram_bankmachine2_row[12:0] - end - attribute \src "ls180.v:645.5-645.46" - process $proc$ls180.v:645$3097 assign { } { } - assign $1\main_sdram_bankmachine2_row_opened[0:0] 1'0 + assign $0\libresocsim_slave_sel[5:0] [0] $eq$ls180.v:3094$670_Y + assign $0\libresocsim_slave_sel[5:0] [1] $eq$ls180.v:3095$671_Y + assign $0\libresocsim_slave_sel[5:0] [2] $eq$ls180.v:3096$672_Y + assign $0\libresocsim_slave_sel[5:0] [3] $eq$ls180.v:3097$673_Y + assign $0\libresocsim_slave_sel[5:0] [4] $eq$ls180.v:3098$674_Y + assign $0\libresocsim_slave_sel[5:0] [5] $eq$ls180.v:3099$675_Y sync always - sync init - update \main_sdram_bankmachine2_row_opened $1\main_sdram_bankmachine2_row_opened[0:0] + update \libresocsim_slave_sel $0\libresocsim_slave_sel[5:0] end - attribute \src "ls180.v:647.5-647.44" - process $proc$ls180.v:647$3098 + attribute \src "ls180.v:310.5-310.28" + process $proc$ls180.v:310$1726 assign { } { } - assign $1\main_sdram_bankmachine2_row_open[0:0] 1'0 + assign $1\sdram_address_re[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_row_open $1\main_sdram_bankmachine2_row_open[0:0] + update \sdram_address_re $1\sdram_address_re[0:0] end - attribute \src "ls180.v:648.5-648.45" - process $proc$ls180.v:648$3099 + attribute \src "ls180.v:311.11-311.40" + process $proc$ls180.v:311$1727 assign { } { } - assign $1\main_sdram_bankmachine2_row_close[0:0] 1'0 + assign $1\sdram_baddress_storage[1:0] 2'00 sync always sync init - update \main_sdram_bankmachine2_row_close $1\main_sdram_bankmachine2_row_close[0:0] + update \sdram_baddress_storage $1\sdram_baddress_storage[1:0] end - attribute \src "ls180.v:649.5-649.54" - process $proc$ls180.v:649$3100 + attribute \src "ls180.v:312.5-312.29" + process $proc$ls180.v:312$1728 assign { } { } - assign $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 + assign $1\sdram_baddress_re[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_row_col_n_addr_sel $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] + update \sdram_baddress_re $1\sdram_baddress_re[0:0] end - attribute \src "ls180.v:65.12-65.55" - process $proc$ls180.v:65$2881 + attribute \src "ls180.v:313.12-313.40" + process $proc$ls180.v:313$1729 assign { } { } - assign $1\main_libresocsim_libresoc_interrupt[15:0] 16'0000000000000000 + assign $1\sdram_wrdata_storage[15:0] 16'0000000000000000 sync always sync init - update \main_libresocsim_libresoc_interrupt $1\main_libresocsim_libresoc_interrupt[15:0] + update \sdram_wrdata_storage $1\sdram_wrdata_storage[15:0] end - attribute \src "ls180.v:651.32-651.76" - process $proc$ls180.v:651$3101 + attribute \src "ls180.v:314.5-314.27" + process $proc$ls180.v:314$1730 assign { } { } - assign $1\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 + assign $1\sdram_wrdata_re[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine2_twtpcon_ready $1\main_sdram_bankmachine2_twtpcon_ready[0:0] + update \sdram_wrdata_re $1\sdram_wrdata_re[0:0] end - attribute \src "ls180.v:652.11-652.55" - process $proc$ls180.v:652$3102 + attribute \src "ls180.v:315.12-315.32" + process $proc$ls180.v:315$1731 assign { } { } - assign $1\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 + assign $1\sdram_status[15:0] 16'0000000000000000 sync always sync init - update \main_sdram_bankmachine2_twtpcon_count $1\main_sdram_bankmachine2_twtpcon_count[2:0] + update \sdram_status $1\sdram_status[15:0] end - attribute \src "ls180.v:654.32-654.75" - process $proc$ls180.v:654$3103 + attribute \src "ls180.v:3151.1-3162.4" + process $proc$ls180.v:3151$690 assign { } { } - assign $0\main_sdram_bankmachine2_trccon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine2_trccon_ready $0\main_sdram_bankmachine2_trccon_ready[0:0] - sync init - end - attribute \src "ls180.v:656.32-656.76" - process $proc$ls180.v:656$3104 assign { } { } - assign $0\main_sdram_bankmachine2_trascon_ready[0:0] 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $0\libresocsim_error[0:0] 1'0 + assign $0\libresocsim_shared_ack[0:0] $or$ls180.v:3155$695_Y + assign $0\libresocsim_shared_dat_r[31:0] $or$ls180.v:3156$706_Y [31:0] + attribute \src "ls180.v:3157.2-3161.5" + switch \libresocsim_done + attribute \src "ls180.v:3157.6-3157.22" + case 1'1 + assign $0\libresocsim_shared_dat_r[31:0] 32'11111111111111111111111111111111 + assign $0\libresocsim_shared_ack[0:0] 1'1 + assign $0\libresocsim_error[0:0] 1'1 + case + end sync always - update \main_sdram_bankmachine2_trascon_ready $0\main_sdram_bankmachine2_trascon_ready[0:0] - sync init + update \libresocsim_shared_dat_r $0\libresocsim_shared_dat_r[31:0] + update \libresocsim_shared_ack $0\libresocsim_shared_ack[0:0] + update \libresocsim_error $0\libresocsim_error[0:0] end - attribute \src "ls180.v:6597.1-6613.4" - process $proc$ls180.v:6597$2297 + attribute \src "ls180.v:3437.1-3453.4" + process $proc$ls180.v:3437$1115 assign { } { } - assign $0\builder_comb_rhs_array_muxed0[0:0] 1'0 - attribute \src "ls180.v:6599.2-6612.9" - switch \main_sdram_choose_cmd_grant + assign $0\rhs_array_muxed0[0:0] 1'0 + attribute \src "ls180.v:3439.2-3452.9" + switch \sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [0] + assign $0\rhs_array_muxed0[0:0] \sdram_choose_cmd_valids [0] attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [1] + assign $0\rhs_array_muxed0[0:0] \sdram_choose_cmd_valids [1] attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [2] + assign $0\rhs_array_muxed0[0:0] \sdram_choose_cmd_valids [2] attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [3] + assign $0\rhs_array_muxed0[0:0] \sdram_choose_cmd_valids [3] end sync always - update \builder_comb_rhs_array_muxed0 $0\builder_comb_rhs_array_muxed0[0:0] + update \rhs_array_muxed0 $0\rhs_array_muxed0[0:0] + end + attribute \src "ls180.v:345.12-345.41" + process $proc$ls180.v:345$1732 + assign { } { } + assign $1\sdram_interface_wdata[15:0] 16'0000000000000000 + sync always + sync init + update \sdram_interface_wdata $1\sdram_interface_wdata[15:0] end - attribute \src "ls180.v:6614.1-6630.4" - process $proc$ls180.v:6614$2298 + attribute \src "ls180.v:3454.1-3470.4" + process $proc$ls180.v:3454$1116 assign { } { } - assign $0\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 - attribute \src "ls180.v:6616.2-6629.9" - switch \main_sdram_choose_cmd_grant + assign $0\rhs_array_muxed1[12:0] 13'0000000000000 + attribute \src "ls180.v:3456.2-3469.9" + switch \sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine0_cmd_payload_a + assign $0\rhs_array_muxed1[12:0] \sdram_bankmachine0_cmd_payload_a attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine1_cmd_payload_a + assign $0\rhs_array_muxed1[12:0] \sdram_bankmachine1_cmd_payload_a attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine2_cmd_payload_a + assign $0\rhs_array_muxed1[12:0] \sdram_bankmachine2_cmd_payload_a attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine3_cmd_payload_a + assign $0\rhs_array_muxed1[12:0] \sdram_bankmachine3_cmd_payload_a end sync always - update \builder_comb_rhs_array_muxed1 $0\builder_comb_rhs_array_muxed1[12:0] - end - attribute \src "ls180.v:662.5-662.51" - process $proc$ls180.v:662$3105 - assign { } { } - assign $1\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_req_wdata_ready $1\main_sdram_bankmachine3_req_wdata_ready[0:0] + update \rhs_array_muxed1 $0\rhs_array_muxed1[12:0] end - attribute \src "ls180.v:663.5-663.51" - process $proc$ls180.v:663$3106 + attribute \src "ls180.v:346.11-346.42" + process $proc$ls180.v:346$1733 assign { } { } - assign $1\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 + assign $1\sdram_interface_wdata_we[1:0] 2'00 sync always sync init - update \main_sdram_bankmachine3_req_rdata_valid $1\main_sdram_bankmachine3_req_rdata_valid[0:0] + update \sdram_interface_wdata_we $1\sdram_interface_wdata_we[1:0] end - attribute \src "ls180.v:6631.1-6647.4" - process $proc$ls180.v:6631$2299 + attribute \src "ls180.v:3471.1-3487.4" + process $proc$ls180.v:3471$1117 assign { } { } - assign $0\builder_comb_rhs_array_muxed2[1:0] 2'00 - attribute \src "ls180.v:6633.2-6646.9" - switch \main_sdram_choose_cmd_grant + assign $0\rhs_array_muxed2[1:0] 2'00 + attribute \src "ls180.v:3473.2-3486.9" + switch \sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine0_cmd_payload_ba + assign $0\rhs_array_muxed2[1:0] \sdram_bankmachine0_cmd_payload_ba attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine1_cmd_payload_ba + assign $0\rhs_array_muxed2[1:0] \sdram_bankmachine1_cmd_payload_ba attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine2_cmd_payload_ba + assign $0\rhs_array_muxed2[1:0] \sdram_bankmachine2_cmd_payload_ba attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine3_cmd_payload_ba + assign $0\rhs_array_muxed2[1:0] \sdram_bankmachine3_cmd_payload_ba end sync always - update \builder_comb_rhs_array_muxed2 $0\builder_comb_rhs_array_muxed2[1:0] + update \rhs_array_muxed2 $0\rhs_array_muxed2[1:0] + end + attribute \src "ls180.v:348.12-348.40" + process $proc$ls180.v:348$1734 + assign { } { } + assign $1\sdram_dfi_p0_address[12:0] 13'0000000000000 + sync always + sync init + update \sdram_dfi_p0_address $1\sdram_dfi_p0_address[12:0] end - attribute \src "ls180.v:6648.1-6664.4" - process $proc$ls180.v:6648$2300 + attribute \src "ls180.v:3488.1-3504.4" + process $proc$ls180.v:3488$1118 assign { } { } - assign $0\builder_comb_rhs_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:6650.2-6663.9" - switch \main_sdram_choose_cmd_grant + assign $0\rhs_array_muxed3[0:0] 1'0 + attribute \src "ls180.v:3490.2-3503.9" + switch \sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine0_cmd_payload_is_read + assign $0\rhs_array_muxed3[0:0] \sdram_bankmachine0_cmd_payload_is_read attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine1_cmd_payload_is_read + assign $0\rhs_array_muxed3[0:0] \sdram_bankmachine1_cmd_payload_is_read attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine2_cmd_payload_is_read + assign $0\rhs_array_muxed3[0:0] \sdram_bankmachine2_cmd_payload_is_read attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine3_cmd_payload_is_read + assign $0\rhs_array_muxed3[0:0] \sdram_bankmachine3_cmd_payload_is_read end sync always - update \builder_comb_rhs_array_muxed3 $0\builder_comb_rhs_array_muxed3[0:0] + update \rhs_array_muxed3 $0\rhs_array_muxed3[0:0] end - attribute \src "ls180.v:665.5-665.47" - process $proc$ls180.v:665$3107 + attribute \src "ls180.v:349.11-349.35" + process $proc$ls180.v:349$1735 assign { } { } - assign $1\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 + assign $1\sdram_dfi_p0_bank[1:0] 2'00 sync always sync init - update \main_sdram_bankmachine3_refresh_gnt $1\main_sdram_bankmachine3_refresh_gnt[0:0] + update \sdram_dfi_p0_bank $1\sdram_dfi_p0_bank[1:0] end - attribute \src "ls180.v:666.5-666.45" - process $proc$ls180.v:666$3108 + attribute \src "ls180.v:350.5-350.30" + process $proc$ls180.v:350$1736 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 + assign $1\sdram_dfi_p0_cas_n[0:0] 1'1 sync always sync init - update \main_sdram_bankmachine3_cmd_valid $1\main_sdram_bankmachine3_cmd_valid[0:0] + update \sdram_dfi_p0_cas_n $1\sdram_dfi_p0_cas_n[0:0] end - attribute \src "ls180.v:6665.1-6681.4" - process $proc$ls180.v:6665$2301 + attribute \src "ls180.v:3505.1-3521.4" + process $proc$ls180.v:3505$1119 assign { } { } - assign $0\builder_comb_rhs_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:6667.2-6680.9" - switch \main_sdram_choose_cmd_grant + assign $0\rhs_array_muxed4[0:0] 1'0 + attribute \src "ls180.v:3507.2-3520.9" + switch \sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine0_cmd_payload_is_write + assign $0\rhs_array_muxed4[0:0] \sdram_bankmachine0_cmd_payload_is_write attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine1_cmd_payload_is_write + assign $0\rhs_array_muxed4[0:0] \sdram_bankmachine1_cmd_payload_is_write attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine2_cmd_payload_is_write + assign $0\rhs_array_muxed4[0:0] \sdram_bankmachine2_cmd_payload_is_write attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine3_cmd_payload_is_write + assign $0\rhs_array_muxed4[0:0] \sdram_bankmachine3_cmd_payload_is_write end sync always - update \builder_comb_rhs_array_muxed4 $0\builder_comb_rhs_array_muxed4[0:0] + update \rhs_array_muxed4 $0\rhs_array_muxed4[0:0] end - attribute \src "ls180.v:667.5-667.45" - process $proc$ls180.v:667$3109 + attribute \src "ls180.v:351.5-351.29" + process $proc$ls180.v:351$1737 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 + assign $1\sdram_dfi_p0_cs_n[0:0] 1'1 sync always sync init - update \main_sdram_bankmachine3_cmd_ready $1\main_sdram_bankmachine3_cmd_ready[0:0] + update \sdram_dfi_p0_cs_n $1\sdram_dfi_p0_cs_n[0:0] end - attribute \src "ls180.v:668.12-668.57" - process $proc$ls180.v:668$3110 + attribute \src "ls180.v:352.5-352.30" + process $proc$ls180.v:352$1738 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 + assign $1\sdram_dfi_p0_ras_n[0:0] 1'1 sync always sync init - update \main_sdram_bankmachine3_cmd_payload_a $1\main_sdram_bankmachine3_cmd_payload_a[12:0] + update \sdram_dfi_p0_ras_n $1\sdram_dfi_p0_ras_n[0:0] end - attribute \src "ls180.v:6682.1-6698.4" - process $proc$ls180.v:6682$2302 + attribute \src "ls180.v:3522.1-3538.4" + process $proc$ls180.v:3522$1120 assign { } { } - assign $0\builder_comb_rhs_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:6684.2-6697.9" - switch \main_sdram_choose_cmd_grant + assign $0\rhs_array_muxed5[0:0] 1'0 + attribute \src "ls180.v:3524.2-3537.9" + switch \sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine0_cmd_payload_is_cmd + assign $0\rhs_array_muxed5[0:0] \sdram_bankmachine0_cmd_payload_is_cmd attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine1_cmd_payload_is_cmd + assign $0\rhs_array_muxed5[0:0] \sdram_bankmachine1_cmd_payload_is_cmd attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine2_cmd_payload_is_cmd + assign $0\rhs_array_muxed5[0:0] \sdram_bankmachine2_cmd_payload_is_cmd attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine3_cmd_payload_is_cmd + assign $0\rhs_array_muxed5[0:0] \sdram_bankmachine3_cmd_payload_is_cmd end sync always - update \builder_comb_rhs_array_muxed5 $0\builder_comb_rhs_array_muxed5[0:0] + update \rhs_array_muxed5 $0\rhs_array_muxed5[0:0] + end + attribute \src "ls180.v:353.5-353.29" + process $proc$ls180.v:353$1739 + assign { } { } + assign $1\sdram_dfi_p0_we_n[0:0] 1'1 + sync always + sync init + update \sdram_dfi_p0_we_n $1\sdram_dfi_p0_we_n[0:0] end - attribute \src "ls180.v:6699.1-6715.4" - process $proc$ls180.v:6699$2303 + attribute \src "ls180.v:3539.1-3555.4" + process $proc$ls180.v:3539$1121 assign { } { } - assign $0\builder_comb_t_array_muxed0[0:0] 1'0 - attribute \src "ls180.v:6701.2-6714.9" - switch \main_sdram_choose_cmd_grant + assign $0\t_array_muxed0[0:0] 1'0 + attribute \src "ls180.v:3541.2-3554.9" + switch \sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine0_cmd_payload_cas + assign $0\t_array_muxed0[0:0] \sdram_bankmachine0_cmd_payload_cas attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine1_cmd_payload_cas + assign $0\t_array_muxed0[0:0] \sdram_bankmachine1_cmd_payload_cas attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine2_cmd_payload_cas + assign $0\t_array_muxed0[0:0] \sdram_bankmachine2_cmd_payload_cas attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine3_cmd_payload_cas + assign $0\t_array_muxed0[0:0] \sdram_bankmachine3_cmd_payload_cas end sync always - update \builder_comb_t_array_muxed0 $0\builder_comb_t_array_muxed0[0:0] - end - attribute \src "ls180.v:670.5-670.51" - process $proc$ls180.v:670$3111 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_cas $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:671.5-671.51" - process $proc$ls180.v:671$3112 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_ras $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] + update \t_array_muxed0 $0\t_array_muxed0[0:0] end - attribute \src "ls180.v:6716.1-6732.4" - process $proc$ls180.v:6716$2304 + attribute \src "ls180.v:3556.1-3572.4" + process $proc$ls180.v:3556$1122 assign { } { } - assign $0\builder_comb_t_array_muxed1[0:0] 1'0 - attribute \src "ls180.v:6718.2-6731.9" - switch \main_sdram_choose_cmd_grant + assign $0\t_array_muxed1[0:0] 1'0 + attribute \src "ls180.v:3558.2-3571.9" + switch \sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine0_cmd_payload_ras + assign $0\t_array_muxed1[0:0] \sdram_bankmachine0_cmd_payload_ras attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine1_cmd_payload_ras + assign $0\t_array_muxed1[0:0] \sdram_bankmachine1_cmd_payload_ras attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine2_cmd_payload_ras + assign $0\t_array_muxed1[0:0] \sdram_bankmachine2_cmd_payload_ras attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine3_cmd_payload_ras + assign $0\t_array_muxed1[0:0] \sdram_bankmachine3_cmd_payload_ras end sync always - update \builder_comb_t_array_muxed1 $0\builder_comb_t_array_muxed1[0:0] - end - attribute \src "ls180.v:672.5-672.50" - process $proc$ls180.v:672$3113 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_we $1\main_sdram_bankmachine3_cmd_payload_we[0:0] + update \t_array_muxed1 $0\t_array_muxed1[0:0] end - attribute \src "ls180.v:673.5-673.54" - process $proc$ls180.v:673$3114 + attribute \src "ls180.v:357.5-357.30" + process $proc$ls180.v:357$1740 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 + assign $0\sdram_dfi_p0_act_n[0:0] 1'1 sync always + update \sdram_dfi_p0_act_n $0\sdram_dfi_p0_act_n[0:0] sync init - update \main_sdram_bankmachine3_cmd_payload_is_cmd $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] end - attribute \src "ls180.v:6733.1-6749.4" - process $proc$ls180.v:6733$2305 + attribute \src "ls180.v:3573.1-3589.4" + process $proc$ls180.v:3573$1123 assign { } { } - assign $0\builder_comb_t_array_muxed2[0:0] 1'0 - attribute \src "ls180.v:6735.2-6748.9" - switch \main_sdram_choose_cmd_grant + assign $0\t_array_muxed2[0:0] 1'0 + attribute \src "ls180.v:3575.2-3588.9" + switch \sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine0_cmd_payload_we + assign $0\t_array_muxed2[0:0] \sdram_bankmachine0_cmd_payload_we attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine1_cmd_payload_we + assign $0\t_array_muxed2[0:0] \sdram_bankmachine1_cmd_payload_we attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine2_cmd_payload_we + assign $0\t_array_muxed2[0:0] \sdram_bankmachine2_cmd_payload_we attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine3_cmd_payload_we + assign $0\t_array_muxed2[0:0] \sdram_bankmachine3_cmd_payload_we end sync always - update \builder_comb_t_array_muxed2 $0\builder_comb_t_array_muxed2[0:0] - end - attribute \src "ls180.v:674.5-674.55" - process $proc$ls180.v:674$3115 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_payload_is_read $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] + update \t_array_muxed2 $0\t_array_muxed2[0:0] end - attribute \src "ls180.v:675.5-675.56" - process $proc$ls180.v:675$3116 + attribute \src "ls180.v:359.5-359.34" + process $proc$ls180.v:359$1741 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 + assign $1\sdram_dfi_p0_wrdata_en[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_cmd_payload_is_write $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + update \sdram_dfi_p0_wrdata_en $1\sdram_dfi_p0_wrdata_en[0:0] end - attribute \src "ls180.v:6750.1-6766.4" - process $proc$ls180.v:6750$2306 + attribute \src "ls180.v:3590.1-3606.4" + process $proc$ls180.v:3590$1124 assign { } { } - assign $0\builder_comb_rhs_array_muxed6[0:0] 1'0 - attribute \src "ls180.v:6752.2-6765.9" - switch \main_sdram_choose_req_grant + assign $0\rhs_array_muxed6[0:0] 1'0 + attribute \src "ls180.v:3592.2-3605.9" + switch \sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [0] + assign $0\rhs_array_muxed6[0:0] \sdram_choose_req_valids [0] attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [1] + assign $0\rhs_array_muxed6[0:0] \sdram_choose_req_valids [1] attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [2] + assign $0\rhs_array_muxed6[0:0] \sdram_choose_req_valids [2] attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [3] + assign $0\rhs_array_muxed6[0:0] \sdram_choose_req_valids [3] end sync always - update \builder_comb_rhs_array_muxed6 $0\builder_comb_rhs_array_muxed6[0:0] - end - attribute \src "ls180.v:676.5-676.50" - process $proc$ls180.v:676$3117 - assign { } { } - assign $1\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_auto_precharge $1\main_sdram_bankmachine3_auto_precharge[0:0] + update \rhs_array_muxed6 $0\rhs_array_muxed6[0:0] end - attribute \src "ls180.v:6767.1-6783.4" - process $proc$ls180.v:6767$2307 + attribute \src "ls180.v:3607.1-3623.4" + process $proc$ls180.v:3607$1125 assign { } { } - assign $0\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 - attribute \src "ls180.v:6769.2-6782.9" - switch \main_sdram_choose_req_grant + assign $0\rhs_array_muxed7[12:0] 13'0000000000000 + attribute \src "ls180.v:3609.2-3622.9" + switch \sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine0_cmd_payload_a + assign $0\rhs_array_muxed7[12:0] \sdram_bankmachine0_cmd_payload_a attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine1_cmd_payload_a + assign $0\rhs_array_muxed7[12:0] \sdram_bankmachine1_cmd_payload_a attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine2_cmd_payload_a + assign $0\rhs_array_muxed7[12:0] \sdram_bankmachine2_cmd_payload_a attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine3_cmd_payload_a + assign $0\rhs_array_muxed7[12:0] \sdram_bankmachine3_cmd_payload_a end sync always - update \builder_comb_rhs_array_muxed7 $0\builder_comb_rhs_array_muxed7[12:0] + update \rhs_array_muxed7 $0\rhs_array_muxed7[12:0] + end + attribute \src "ls180.v:361.5-361.34" + process $proc$ls180.v:361$1742 + assign { } { } + assign $1\sdram_dfi_p0_rddata_en[0:0] 1'0 + sync always + sync init + update \sdram_dfi_p0_rddata_en $1\sdram_dfi_p0_rddata_en[0:0] end - attribute \src "ls180.v:6784.1-6800.4" - process $proc$ls180.v:6784$2308 + attribute \src "ls180.v:3624.1-3640.4" + process $proc$ls180.v:3624$1126 assign { } { } - assign $0\builder_comb_rhs_array_muxed8[1:0] 2'00 - attribute \src "ls180.v:6786.2-6799.9" - switch \main_sdram_choose_req_grant + assign $0\rhs_array_muxed8[1:0] 2'00 + attribute \src "ls180.v:3626.2-3639.9" + switch \sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine0_cmd_payload_ba + assign $0\rhs_array_muxed8[1:0] \sdram_bankmachine0_cmd_payload_ba attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine1_cmd_payload_ba + assign $0\rhs_array_muxed8[1:0] \sdram_bankmachine1_cmd_payload_ba attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine2_cmd_payload_ba + assign $0\rhs_array_muxed8[1:0] \sdram_bankmachine2_cmd_payload_ba attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine3_cmd_payload_ba + assign $0\rhs_array_muxed8[1:0] \sdram_bankmachine3_cmd_payload_ba end sync always - update \builder_comb_rhs_array_muxed8 $0\builder_comb_rhs_array_muxed8[1:0] - end - attribute \src "ls180.v:679.5-679.67" - process $proc$ls180.v:679$3118 - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0 - sync always - update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] - sync init + update \rhs_array_muxed8 $0\rhs_array_muxed8[1:0] end - attribute \src "ls180.v:680.5-680.66" - process $proc$ls180.v:680$3119 + attribute \src "ls180.v:364.5-364.27" + process $proc$ls180.v:364$1743 assign { } { } - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0 + assign $1\sdram_cmd_valid[0:0] 1'0 sync always - update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] sync init + update \sdram_cmd_valid $1\sdram_cmd_valid[0:0] end - attribute \src "ls180.v:6801.1-6817.4" - process $proc$ls180.v:6801$2309 + attribute \src "ls180.v:3641.1-3657.4" + process $proc$ls180.v:3641$1127 assign { } { } - assign $0\builder_comb_rhs_array_muxed9[0:0] 1'0 - attribute \src "ls180.v:6803.2-6816.9" - switch \main_sdram_choose_req_grant + assign $0\rhs_array_muxed9[0:0] 1'0 + attribute \src "ls180.v:3643.2-3656.9" + switch \sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine0_cmd_payload_is_read + assign $0\rhs_array_muxed9[0:0] \sdram_bankmachine0_cmd_payload_is_read attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine1_cmd_payload_is_read + assign $0\rhs_array_muxed9[0:0] \sdram_bankmachine1_cmd_payload_is_read attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine2_cmd_payload_is_read + assign $0\rhs_array_muxed9[0:0] \sdram_bankmachine2_cmd_payload_is_read attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine3_cmd_payload_is_read + assign $0\rhs_array_muxed9[0:0] \sdram_bankmachine3_cmd_payload_is_read end sync always - update \builder_comb_rhs_array_muxed9 $0\builder_comb_rhs_array_muxed9[0:0] + update \rhs_array_muxed9 $0\rhs_array_muxed9[0:0] + end + attribute \src "ls180.v:365.5-365.27" + process $proc$ls180.v:365$1744 + assign { } { } + assign $1\sdram_cmd_ready[0:0] 1'0 + sync always + sync init + update \sdram_cmd_ready $1\sdram_cmd_ready[0:0] end - attribute \src "ls180.v:6818.1-6834.4" - process $proc$ls180.v:6818$2310 + attribute \src "ls180.v:3658.1-3674.4" + process $proc$ls180.v:3658$1128 assign { } { } - assign $0\builder_comb_rhs_array_muxed10[0:0] 1'0 - attribute \src "ls180.v:6820.2-6833.9" - switch \main_sdram_choose_req_grant + assign $0\rhs_array_muxed10[0:0] 1'0 + attribute \src "ls180.v:3660.2-3673.9" + switch \sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine0_cmd_payload_is_write + assign $0\rhs_array_muxed10[0:0] \sdram_bankmachine0_cmd_payload_is_write attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine1_cmd_payload_is_write + assign $0\rhs_array_muxed10[0:0] \sdram_bankmachine1_cmd_payload_is_write attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine2_cmd_payload_is_write + assign $0\rhs_array_muxed10[0:0] \sdram_bankmachine2_cmd_payload_is_write attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine3_cmd_payload_is_write + assign $0\rhs_array_muxed10[0:0] \sdram_bankmachine3_cmd_payload_is_write end sync always - update \builder_comb_rhs_array_muxed10 $0\builder_comb_rhs_array_muxed10[0:0] + update \rhs_array_muxed10 $0\rhs_array_muxed10[0:0] + end + attribute \src "ls180.v:366.5-366.26" + process $proc$ls180.v:366$1745 + assign { } { } + assign $1\sdram_cmd_last[0:0] 1'0 + sync always + sync init + update \sdram_cmd_last $1\sdram_cmd_last[0:0] + end + attribute \src "ls180.v:367.12-367.39" + process $proc$ls180.v:367$1746 + assign { } { } + assign $1\sdram_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \sdram_cmd_payload_a $1\sdram_cmd_payload_a[12:0] end - attribute \src "ls180.v:6835.1-6851.4" - process $proc$ls180.v:6835$2311 + attribute \src "ls180.v:3675.1-3691.4" + process $proc$ls180.v:3675$1129 assign { } { } - assign $0\builder_comb_rhs_array_muxed11[0:0] 1'0 - attribute \src "ls180.v:6837.2-6850.9" - switch \main_sdram_choose_req_grant + assign $0\rhs_array_muxed11[0:0] 1'0 + attribute \src "ls180.v:3677.2-3690.9" + switch \sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine0_cmd_payload_is_cmd + assign $0\rhs_array_muxed11[0:0] \sdram_bankmachine0_cmd_payload_is_cmd attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine1_cmd_payload_is_cmd + assign $0\rhs_array_muxed11[0:0] \sdram_bankmachine1_cmd_payload_is_cmd attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine2_cmd_payload_is_cmd + assign $0\rhs_array_muxed11[0:0] \sdram_bankmachine2_cmd_payload_is_cmd attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine3_cmd_payload_is_cmd + assign $0\rhs_array_muxed11[0:0] \sdram_bankmachine3_cmd_payload_is_cmd end sync always - update \builder_comb_rhs_array_muxed11 $0\builder_comb_rhs_array_muxed11[0:0] + update \rhs_array_muxed11 $0\rhs_array_muxed11[0:0] + end + attribute \src "ls180.v:368.11-368.38" + process $proc$ls180.v:368$1747 + assign { } { } + assign $1\sdram_cmd_payload_ba[1:0] 2'00 + sync always + sync init + update \sdram_cmd_payload_ba $1\sdram_cmd_payload_ba[1:0] + end + attribute \src "ls180.v:369.5-369.33" + process $proc$ls180.v:369$1748 + assign { } { } + assign $1\sdram_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \sdram_cmd_payload_cas $1\sdram_cmd_payload_cas[0:0] end - attribute \src "ls180.v:6852.1-6868.4" - process $proc$ls180.v:6852$2312 + attribute \src "ls180.v:3692.1-3708.4" + process $proc$ls180.v:3692$1130 assign { } { } - assign $0\builder_comb_t_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:6854.2-6867.9" - switch \main_sdram_choose_req_grant + assign $0\t_array_muxed3[0:0] 1'0 + attribute \src "ls180.v:3694.2-3707.9" + switch \sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine0_cmd_payload_cas + assign $0\t_array_muxed3[0:0] \sdram_bankmachine0_cmd_payload_cas attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine1_cmd_payload_cas + assign $0\t_array_muxed3[0:0] \sdram_bankmachine1_cmd_payload_cas attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine2_cmd_payload_cas + assign $0\t_array_muxed3[0:0] \sdram_bankmachine2_cmd_payload_cas attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine3_cmd_payload_cas + assign $0\t_array_muxed3[0:0] \sdram_bankmachine3_cmd_payload_cas end sync always - update \builder_comb_t_array_muxed3 $0\builder_comb_t_array_muxed3[0:0] + update \t_array_muxed3 $0\t_array_muxed3[0:0] + end + attribute \src "ls180.v:370.5-370.33" + process $proc$ls180.v:370$1749 + assign { } { } + assign $1\sdram_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \sdram_cmd_payload_ras $1\sdram_cmd_payload_ras[0:0] end - attribute \src "ls180.v:6869.1-6885.4" - process $proc$ls180.v:6869$2313 + attribute \src "ls180.v:3709.1-3725.4" + process $proc$ls180.v:3709$1131 assign { } { } - assign $0\builder_comb_t_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:6871.2-6884.9" - switch \main_sdram_choose_req_grant + assign $0\t_array_muxed4[0:0] 1'0 + attribute \src "ls180.v:3711.2-3724.9" + switch \sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine0_cmd_payload_ras + assign $0\t_array_muxed4[0:0] \sdram_bankmachine0_cmd_payload_ras attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine1_cmd_payload_ras + assign $0\t_array_muxed4[0:0] \sdram_bankmachine1_cmd_payload_ras attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine2_cmd_payload_ras + assign $0\t_array_muxed4[0:0] \sdram_bankmachine2_cmd_payload_ras attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine3_cmd_payload_ras + assign $0\t_array_muxed4[0:0] \sdram_bankmachine3_cmd_payload_ras end sync always - update \builder_comb_t_array_muxed4 $0\builder_comb_t_array_muxed4[0:0] + update \t_array_muxed4 $0\t_array_muxed4[0:0] + end + attribute \src "ls180.v:371.5-371.32" + process $proc$ls180.v:371$1750 + assign { } { } + assign $1\sdram_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \sdram_cmd_payload_we $1\sdram_cmd_payload_we[0:0] + end + attribute \src "ls180.v:372.5-372.37" + process $proc$ls180.v:372$1751 + assign { } { } + assign $0\sdram_cmd_payload_is_read[0:0] 1'0 + sync always + update \sdram_cmd_payload_is_read $0\sdram_cmd_payload_is_read[0:0] + sync init end - attribute \src "ls180.v:6886.1-6902.4" - process $proc$ls180.v:6886$2314 + attribute \src "ls180.v:3726.1-3742.4" + process $proc$ls180.v:3726$1132 assign { } { } - assign $0\builder_comb_t_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:6888.2-6901.9" - switch \main_sdram_choose_req_grant + assign $0\t_array_muxed5[0:0] 1'0 + attribute \src "ls180.v:3728.2-3741.9" + switch \sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine0_cmd_payload_we + assign $0\t_array_muxed5[0:0] \sdram_bankmachine0_cmd_payload_we attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine1_cmd_payload_we + assign $0\t_array_muxed5[0:0] \sdram_bankmachine1_cmd_payload_we attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine2_cmd_payload_we + assign $0\t_array_muxed5[0:0] \sdram_bankmachine2_cmd_payload_we attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine3_cmd_payload_we + assign $0\t_array_muxed5[0:0] \sdram_bankmachine3_cmd_payload_we end sync always - update \builder_comb_t_array_muxed5 $0\builder_comb_t_array_muxed5[0:0] + update \t_array_muxed5 $0\t_array_muxed5[0:0] + end + attribute \src "ls180.v:373.5-373.38" + process $proc$ls180.v:373$1752 + assign { } { } + assign $0\sdram_cmd_payload_is_write[0:0] 1'0 + sync always + update \sdram_cmd_payload_is_write $0\sdram_cmd_payload_is_write[0:0] + sync init end - attribute \src "ls180.v:6903.1-6910.4" - process $proc$ls180.v:6903$2315 + attribute \src "ls180.v:3743.1-3750.4" + process $proc$ls180.v:3743$1133 assign { } { } - assign $0\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:6905.2-6909.9" - switch \builder_roundrobin0_grant + assign $0\rhs_array_muxed12[21:0] 22'0000000000000000000000 + attribute \src "ls180.v:3745.2-3749.9" + switch \subfragments_roundrobin0_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed12[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } + assign $0\rhs_array_muxed12[21:0] { \port_cmd_payload_addr [23:11] \port_cmd_payload_addr [8:0] } end sync always - update \builder_comb_rhs_array_muxed12 $0\builder_comb_rhs_array_muxed12[21:0] + update \rhs_array_muxed12 $0\rhs_array_muxed12[21:0] end - attribute \src "ls180.v:6911.1-6918.4" - process $proc$ls180.v:6911$2316 + attribute \src "ls180.v:3751.1-3758.4" + process $proc$ls180.v:3751$1134 assign { } { } - assign $0\builder_comb_rhs_array_muxed13[0:0] 1'0 - attribute \src "ls180.v:6913.2-6917.9" - switch \builder_roundrobin0_grant + assign $0\rhs_array_muxed13[0:0] 1'0 + attribute \src "ls180.v:3753.2-3757.9" + switch \subfragments_roundrobin0_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed13[0:0] \main_port_cmd_payload_we + assign $0\rhs_array_muxed13[0:0] \port_cmd_payload_we end sync always - update \builder_comb_rhs_array_muxed13 $0\builder_comb_rhs_array_muxed13[0:0] + update \rhs_array_muxed13 $0\rhs_array_muxed13[0:0] end - attribute \src "ls180.v:6919.1-6926.4" - process $proc$ls180.v:6919$2317 + attribute \src "ls180.v:3759.1-3766.4" + process $proc$ls180.v:3759$1135 assign { } { } - assign $0\builder_comb_rhs_array_muxed14[0:0] 1'0 - attribute \src "ls180.v:6921.2-6925.9" - switch \builder_roundrobin0_grant + assign $0\rhs_array_muxed14[0:0] 1'0 + attribute \src "ls180.v:3761.2-3765.9" + switch \subfragments_roundrobin0_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed14[0:0] $and$ls180.v:6923$2330_Y + assign $0\rhs_array_muxed14[0:0] $and$ls180.v:3763$1148_Y end sync always - update \builder_comb_rhs_array_muxed14 $0\builder_comb_rhs_array_muxed14[0:0] + update \rhs_array_muxed14 $0\rhs_array_muxed14[0:0] end - attribute \src "ls180.v:6927.1-6934.4" - process $proc$ls180.v:6927$2331 + attribute \src "ls180.v:3767.1-3774.4" + process $proc$ls180.v:3767$1149 assign { } { } - assign $0\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:6929.2-6933.9" - switch \builder_roundrobin1_grant + assign $0\rhs_array_muxed15[21:0] 22'0000000000000000000000 + attribute \src "ls180.v:3769.2-3773.9" + switch \subfragments_roundrobin1_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed15[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } + assign $0\rhs_array_muxed15[21:0] { \port_cmd_payload_addr [23:11] \port_cmd_payload_addr [8:0] } end sync always - update \builder_comb_rhs_array_muxed15 $0\builder_comb_rhs_array_muxed15[21:0] + update \rhs_array_muxed15 $0\rhs_array_muxed15[21:0] end - attribute \src "ls180.v:6935.1-6942.4" - process $proc$ls180.v:6935$2332 + attribute \src "ls180.v:3775.1-3782.4" + process $proc$ls180.v:3775$1150 assign { } { } - assign $0\builder_comb_rhs_array_muxed16[0:0] 1'0 - attribute \src "ls180.v:6937.2-6941.9" - switch \builder_roundrobin1_grant + assign $0\rhs_array_muxed16[0:0] 1'0 + attribute \src "ls180.v:3777.2-3781.9" + switch \subfragments_roundrobin1_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed16[0:0] \main_port_cmd_payload_we + assign $0\rhs_array_muxed16[0:0] \port_cmd_payload_we end sync always - update \builder_comb_rhs_array_muxed16 $0\builder_comb_rhs_array_muxed16[0:0] + update \rhs_array_muxed16 $0\rhs_array_muxed16[0:0] end - attribute \src "ls180.v:6943.1-6950.4" - process $proc$ls180.v:6943$2333 + attribute \src "ls180.v:3783.1-3790.4" + process $proc$ls180.v:3783$1151 assign { } { } - assign $0\builder_comb_rhs_array_muxed17[0:0] 1'0 - attribute \src "ls180.v:6945.2-6949.9" - switch \builder_roundrobin1_grant + assign $0\rhs_array_muxed17[0:0] 1'0 + attribute \src "ls180.v:3785.2-3789.9" + switch \subfragments_roundrobin1_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed17[0:0] $and$ls180.v:6947$2346_Y + assign $0\rhs_array_muxed17[0:0] $and$ls180.v:3787$1164_Y end sync always - update \builder_comb_rhs_array_muxed17 $0\builder_comb_rhs_array_muxed17[0:0] + update \rhs_array_muxed17 $0\rhs_array_muxed17[0:0] end - attribute \src "ls180.v:695.11-695.68" - process $proc$ls180.v:695$3120 + attribute \src "ls180.v:379.11-379.39" + process $proc$ls180.v:379$1753 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $1\sdram_timer_count1[9:0] 10'1100001101 sync always sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + update \sdram_timer_count1 $1\sdram_timer_count1[9:0] end - attribute \src "ls180.v:6951.1-6958.4" - process $proc$ls180.v:6951$2347 + attribute \src "ls180.v:3791.1-3798.4" + process $proc$ls180.v:3791$1165 assign { } { } - assign $0\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:6953.2-6957.9" - switch \builder_roundrobin2_grant + assign $0\rhs_array_muxed18[21:0] 22'0000000000000000000000 + attribute \src "ls180.v:3793.2-3797.9" + switch \subfragments_roundrobin2_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed18[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } + assign $0\rhs_array_muxed18[21:0] { \port_cmd_payload_addr [23:11] \port_cmd_payload_addr [8:0] } end sync always - update \builder_comb_rhs_array_muxed18 $0\builder_comb_rhs_array_muxed18[21:0] + update \rhs_array_muxed18 $0\rhs_array_muxed18[21:0] end - attribute \src "ls180.v:6959.1-6966.4" - process $proc$ls180.v:6959$2348 + attribute \src "ls180.v:3799.1-3806.4" + process $proc$ls180.v:3799$1166 assign { } { } - assign $0\builder_comb_rhs_array_muxed19[0:0] 1'0 - attribute \src "ls180.v:6961.2-6965.9" - switch \builder_roundrobin2_grant + assign $0\rhs_array_muxed19[0:0] 1'0 + attribute \src "ls180.v:3801.2-3805.9" + switch \subfragments_roundrobin2_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed19[0:0] \main_port_cmd_payload_we + assign $0\rhs_array_muxed19[0:0] \port_cmd_payload_we end sync always - update \builder_comb_rhs_array_muxed19 $0\builder_comb_rhs_array_muxed19[0:0] - end - attribute \src "ls180.v:696.5-696.64" - process $proc$ls180.v:696$3121 - assign { } { } - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0 - sync always - update \main_sdram_bankmachine3_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] - sync init + update \rhs_array_muxed19 $0\rhs_array_muxed19[0:0] end - attribute \src "ls180.v:6967.1-6974.4" - process $proc$ls180.v:6967$2349 + attribute \src "ls180.v:3807.1-3814.4" + process $proc$ls180.v:3807$1167 assign { } { } - assign $0\builder_comb_rhs_array_muxed20[0:0] 1'0 - attribute \src "ls180.v:6969.2-6973.9" - switch \builder_roundrobin2_grant + assign $0\rhs_array_muxed20[0:0] 1'0 + attribute \src "ls180.v:3809.2-3813.9" + switch \subfragments_roundrobin2_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed20[0:0] $and$ls180.v:6971$2362_Y + assign $0\rhs_array_muxed20[0:0] $and$ls180.v:3811$1180_Y end sync always - update \builder_comb_rhs_array_muxed20 $0\builder_comb_rhs_array_muxed20[0:0] + update \rhs_array_muxed20 $0\rhs_array_muxed20[0:0] end - attribute \src "ls180.v:697.11-697.70" - process $proc$ls180.v:697$3122 + attribute \src "ls180.v:381.5-381.33" + process $proc$ls180.v:381$1754 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $1\sdram_postponer_req_o[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + update \sdram_postponer_req_o $1\sdram_postponer_req_o[0:0] end - attribute \src "ls180.v:6975.1-6982.4" - process $proc$ls180.v:6975$2363 + attribute \src "ls180.v:3815.1-3822.4" + process $proc$ls180.v:3815$1181 assign { } { } - assign $0\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 - attribute \src "ls180.v:6977.2-6981.9" - switch \builder_roundrobin3_grant + assign $0\rhs_array_muxed21[21:0] 22'0000000000000000000000 + attribute \src "ls180.v:3817.2-3821.9" + switch \subfragments_roundrobin3_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed21[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } + assign $0\rhs_array_muxed21[21:0] { \port_cmd_payload_addr [23:11] \port_cmd_payload_addr [8:0] } end sync always - update \builder_comb_rhs_array_muxed21 $0\builder_comb_rhs_array_muxed21[21:0] + update \rhs_array_muxed21 $0\rhs_array_muxed21[21:0] end - attribute \src "ls180.v:698.11-698.70" - process $proc$ls180.v:698$3123 + attribute \src "ls180.v:382.5-382.33" + process $proc$ls180.v:382$1755 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $1\sdram_postponer_count[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + update \sdram_postponer_count $1\sdram_postponer_count[0:0] end - attribute \src "ls180.v:6983.1-6990.4" - process $proc$ls180.v:6983$2364 + attribute \src "ls180.v:3823.1-3830.4" + process $proc$ls180.v:3823$1182 assign { } { } - assign $0\builder_comb_rhs_array_muxed22[0:0] 1'0 - attribute \src "ls180.v:6985.2-6989.9" - switch \builder_roundrobin3_grant + assign $0\rhs_array_muxed22[0:0] 1'0 + attribute \src "ls180.v:3825.2-3829.9" + switch \subfragments_roundrobin3_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed22[0:0] \main_port_cmd_payload_we + assign $0\rhs_array_muxed22[0:0] \port_cmd_payload_we end sync always - update \builder_comb_rhs_array_muxed22 $0\builder_comb_rhs_array_muxed22[0:0] + update \rhs_array_muxed22 $0\rhs_array_muxed22[0:0] end - attribute \src "ls180.v:699.11-699.73" - process $proc$ls180.v:699$3124 + attribute \src "ls180.v:383.5-383.34" + process $proc$ls180.v:383$1756 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + assign $1\sdram_sequencer_start0[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + update \sdram_sequencer_start0 $1\sdram_sequencer_start0[0:0] end - attribute \src "ls180.v:6991.1-6998.4" - process $proc$ls180.v:6991$2365 + attribute \src "ls180.v:3831.1-3838.4" + process $proc$ls180.v:3831$1183 assign { } { } - assign $0\builder_comb_rhs_array_muxed23[0:0] 1'0 - attribute \src "ls180.v:6993.2-6997.9" - switch \builder_roundrobin3_grant + assign $0\rhs_array_muxed23[0:0] 1'0 + attribute \src "ls180.v:3833.2-3837.9" + switch \subfragments_roundrobin3_grant attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed23[0:0] $and$ls180.v:6995$2378_Y + assign $0\rhs_array_muxed23[0:0] $and$ls180.v:3835$1196_Y end sync always - update \builder_comb_rhs_array_muxed23 $0\builder_comb_rhs_array_muxed23[0:0] + update \rhs_array_muxed23 $0\rhs_array_muxed23[0:0] end - attribute \src "ls180.v:6999.1-7018.4" - process $proc$ls180.v:6999$2379 + attribute \src "ls180.v:3839.1-3852.4" + process $proc$ls180.v:3839$1197 assign { } { } - assign $0\builder_comb_rhs_array_muxed24[31:0] 0 - attribute \src "ls180.v:7001.2-7017.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_comb_rhs_array_muxed24[31:0] { 3'000 \main_libresocsim_libresoc_ibus_adr } - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_comb_rhs_array_muxed24[31:0] { 3'000 \main_libresocsim_libresoc_dbus_adr } + assign $0\rhs_array_muxed24[28:0] 29'00000000000000000000000000000 + attribute \src "ls180.v:3841.2-3851.9" + switch \libresocsim_grant attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_comb_rhs_array_muxed24[31:0] { 3'000 \main_libresocsim_libresoc_jtag_wb_adr } + case 2'00 + assign $0\rhs_array_muxed24[28:0] \libresocsim_libresoc_ibus_adr attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_comb_rhs_array_muxed24[31:0] \main_interface0_bus_adr + case 2'01 + assign $0\rhs_array_muxed24[28:0] \libresocsim_libresoc_dbus_adr attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed24[31:0] \main_interface1_bus_adr + assign $0\rhs_array_muxed24[28:0] \libresocsim_libresoc_jtag_wb_adr end sync always - update \builder_comb_rhs_array_muxed24 $0\builder_comb_rhs_array_muxed24[31:0] + update \rhs_array_muxed24 $0\rhs_array_muxed24[28:0] end - attribute \src "ls180.v:7019.1-7038.4" - process $proc$ls180.v:7019$2380 + attribute \src "ls180.v:3853.1-3866.4" + process $proc$ls180.v:3853$1198 assign { } { } - assign $0\builder_comb_rhs_array_muxed25[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "ls180.v:7021.2-7037.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_comb_rhs_array_muxed25[63:0] \main_libresocsim_libresoc_ibus_dat_w - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_comb_rhs_array_muxed25[63:0] \main_libresocsim_libresoc_dbus_dat_w + assign $0\rhs_array_muxed25[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "ls180.v:3855.2-3865.9" + switch \libresocsim_grant attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_comb_rhs_array_muxed25[63:0] \main_libresocsim_libresoc_jtag_wb_dat_w + case 2'00 + assign $0\rhs_array_muxed25[63:0] \libresocsim_libresoc_ibus_dat_w attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_comb_rhs_array_muxed25[63:0] \main_interface0_bus_dat_w + case 2'01 + assign $0\rhs_array_muxed25[63:0] \libresocsim_libresoc_dbus_dat_w attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed25[63:0] \main_interface1_bus_dat_w + assign $0\rhs_array_muxed25[63:0] \libresocsim_libresoc_jtag_wb_dat_w end sync always - update \builder_comb_rhs_array_muxed25 $0\builder_comb_rhs_array_muxed25[63:0] + update \rhs_array_muxed25 $0\rhs_array_muxed25[63:0] end - attribute \src "ls180.v:7039.1-7058.4" - process $proc$ls180.v:7039$2381 + attribute \src "ls180.v:386.5-386.33" + process $proc$ls180.v:386$1757 assign { } { } - assign $0\builder_comb_rhs_array_muxed26[7:0] 8'00000000 - attribute \src "ls180.v:7041.2-7057.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_comb_rhs_array_muxed26[7:0] \main_libresocsim_libresoc_ibus_sel - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_comb_rhs_array_muxed26[7:0] \main_libresocsim_libresoc_dbus_sel - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_comb_rhs_array_muxed26[7:0] \main_libresocsim_libresoc_jtag_wb_sel - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_comb_rhs_array_muxed26[7:0] \main_interface0_bus_sel - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed26[7:0] \main_interface1_bus_sel - end + assign $1\sdram_sequencer_done1[0:0] 1'0 sync always - update \builder_comb_rhs_array_muxed26 $0\builder_comb_rhs_array_muxed26[7:0] + sync init + update \sdram_sequencer_done1 $1\sdram_sequencer_done1[0:0] end - attribute \src "ls180.v:7059.1-7078.4" - process $proc$ls180.v:7059$2382 + attribute \src "ls180.v:3867.1-3880.4" + process $proc$ls180.v:3867$1199 assign { } { } - assign $0\builder_comb_rhs_array_muxed27[0:0] 1'0 - attribute \src "ls180.v:7061.2-7077.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_libresoc_ibus_cyc - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_libresoc_dbus_cyc + assign $0\rhs_array_muxed26[7:0] 8'00000000 + attribute \src "ls180.v:3869.2-3879.9" + switch \libresocsim_grant attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_libresoc_jtag_wb_cyc + case 2'00 + assign $0\rhs_array_muxed26[7:0] \libresocsim_libresoc_ibus_sel attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_comb_rhs_array_muxed27[0:0] \main_interface0_bus_cyc + case 2'01 + assign $0\rhs_array_muxed26[7:0] \libresocsim_libresoc_dbus_sel attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed27[0:0] \main_interface1_bus_cyc + assign $0\rhs_array_muxed26[7:0] \libresocsim_libresoc_jtag_wb_sel end sync always - update \builder_comb_rhs_array_muxed27 $0\builder_comb_rhs_array_muxed27[0:0] + update \rhs_array_muxed26 $0\rhs_array_muxed26[7:0] end - attribute \src "ls180.v:7079.1-7098.4" - process $proc$ls180.v:7079$2383 + attribute \src "ls180.v:387.11-387.41" + process $proc$ls180.v:387$1758 assign { } { } - assign $0\builder_comb_rhs_array_muxed28[0:0] 1'0 - attribute \src "ls180.v:7081.2-7097.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_libresoc_ibus_stb - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_libresoc_dbus_stb - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_libresoc_jtag_wb_stb - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_comb_rhs_array_muxed28[0:0] \main_interface0_bus_stb - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed28[0:0] \main_interface1_bus_stb - end + assign $1\sdram_sequencer_counter[3:0] 4'0000 sync always - update \builder_comb_rhs_array_muxed28 $0\builder_comb_rhs_array_muxed28[0:0] + sync init + update \sdram_sequencer_counter $1\sdram_sequencer_counter[3:0] end - attribute \src "ls180.v:7099.1-7118.4" - process $proc$ls180.v:7099$2384 + attribute \src "ls180.v:388.5-388.33" + process $proc$ls180.v:388$1759 assign { } { } - assign $0\builder_comb_rhs_array_muxed29[0:0] 1'0 - attribute \src "ls180.v:7101.2-7117.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_libresoc_ibus_we - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_libresoc_dbus_we - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_libresoc_jtag_wb_we - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_comb_rhs_array_muxed29[0:0] \main_interface0_bus_we - attribute \src "ls180.v:0.0-0.0" - case - assign $0\builder_comb_rhs_array_muxed29[0:0] \main_interface1_bus_we - end + assign $1\sdram_sequencer_count[0:0] 1'0 sync always - update \builder_comb_rhs_array_muxed29 $0\builder_comb_rhs_array_muxed29[0:0] + sync init + update \sdram_sequencer_count $1\sdram_sequencer_count[0:0] end - attribute \src "ls180.v:7119.1-7138.4" - process $proc$ls180.v:7119$2385 + attribute \src "ls180.v:3881.1-3894.4" + process $proc$ls180.v:3881$1200 assign { } { } - assign $0\builder_comb_rhs_array_muxed30[2:0] 3'000 - attribute \src "ls180.v:7121.2-7137.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_libresoc_ibus_cti - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_libresoc_dbus_cti + assign $0\rhs_array_muxed27[0:0] 1'0 + attribute \src "ls180.v:3883.2-3893.9" + switch \libresocsim_grant attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_libresoc_jtag_wb_cti + case 2'00 + assign $0\rhs_array_muxed27[0:0] \libresocsim_libresoc_ibus_cyc attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_comb_rhs_array_muxed30[2:0] \main_interface0_bus_cti + case 2'01 + assign $0\rhs_array_muxed27[0:0] \libresocsim_libresoc_dbus_cyc attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed30[2:0] \main_interface1_bus_cti + assign $0\rhs_array_muxed27[0:0] \libresocsim_libresoc_jtag_wb_cyc end sync always - update \builder_comb_rhs_array_muxed30 $0\builder_comb_rhs_array_muxed30[2:0] + update \rhs_array_muxed27 $0\rhs_array_muxed27[0:0] end - attribute \src "ls180.v:7139.1-7158.4" - process $proc$ls180.v:7139$2386 + attribute \src "ls180.v:3895.1-3908.4" + process $proc$ls180.v:3895$1201 assign { } { } - assign $0\builder_comb_rhs_array_muxed31[1:0] 2'00 - attribute \src "ls180.v:7141.2-7157.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_libresoc_ibus_bte - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_libresoc_dbus_bte + assign $0\rhs_array_muxed28[0:0] 1'0 + attribute \src "ls180.v:3897.2-3907.9" + switch \libresocsim_grant attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_libresoc_jtag_wb_bte + case 2'00 + assign $0\rhs_array_muxed28[0:0] \libresocsim_libresoc_ibus_stb attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_comb_rhs_array_muxed31[1:0] \main_interface0_bus_bte + case 2'01 + assign $0\rhs_array_muxed28[0:0] \libresocsim_libresoc_dbus_stb attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_comb_rhs_array_muxed31[1:0] \main_interface1_bus_bte + assign $0\rhs_array_muxed28[0:0] \libresocsim_libresoc_jtag_wb_stb end sync always - update \builder_comb_rhs_array_muxed31 $0\builder_comb_rhs_array_muxed31[1:0] + update \rhs_array_muxed28 $0\rhs_array_muxed28[0:0] end - attribute \src "ls180.v:7159.1-7175.4" - process $proc$ls180.v:7159$2387 + attribute \src "ls180.v:3909.1-3922.4" + process $proc$ls180.v:3909$1202 assign { } { } - assign $0\builder_sync_rhs_array_muxed0[1:0] 2'00 - attribute \src "ls180.v:7161.2-7174.9" - switch \main_sdram_steerer_sel + assign $0\rhs_array_muxed29[0:0] 1'0 + attribute \src "ls180.v:3911.2-3921.9" + switch \libresocsim_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_nop_ba + assign $0\rhs_array_muxed29[0:0] \libresocsim_libresoc_ibus_we attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_choose_req_cmd_payload_ba - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_choose_req_cmd_payload_ba + assign $0\rhs_array_muxed29[0:0] \libresocsim_libresoc_dbus_we attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_cmd_payload_ba + assign $0\rhs_array_muxed29[0:0] \libresocsim_libresoc_jtag_wb_we end sync always - update \builder_sync_rhs_array_muxed0 $0\builder_sync_rhs_array_muxed0[1:0] + update \rhs_array_muxed29 $0\rhs_array_muxed29[0:0] end - attribute \src "ls180.v:7176.1-7192.4" - process $proc$ls180.v:7176$2388 + attribute \src "ls180.v:3923.1-3936.4" + process $proc$ls180.v:3923$1203 assign { } { } - assign $0\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 - attribute \src "ls180.v:7178.2-7191.9" - switch \main_sdram_steerer_sel + assign $0\rhs_array_muxed30[2:0] 3'000 + attribute \src "ls180.v:3925.2-3935.9" + switch \libresocsim_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_nop_a + assign $0\rhs_array_muxed30[2:0] \libresocsim_libresoc_ibus_cti attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_choose_req_cmd_payload_a - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_choose_req_cmd_payload_a + assign $0\rhs_array_muxed30[2:0] \libresocsim_libresoc_dbus_cti attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_cmd_payload_a + assign $0\rhs_array_muxed30[2:0] \libresocsim_libresoc_jtag_wb_cti end sync always - update \builder_sync_rhs_array_muxed1 $0\builder_sync_rhs_array_muxed1[12:0] + update \rhs_array_muxed30 $0\rhs_array_muxed30[2:0] end - attribute \src "ls180.v:7193.1-7209.4" - process $proc$ls180.v:7193$2389 + attribute \src "ls180.v:3937.1-3950.4" + process $proc$ls180.v:3937$1204 assign { } { } - assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 - attribute \src "ls180.v:7195.2-7208.9" - switch \main_sdram_steerer_sel + assign $0\rhs_array_muxed31[1:0] 2'00 + attribute \src "ls180.v:3939.2-3949.9" + switch \libresocsim_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 + assign $0\rhs_array_muxed31[1:0] \libresocsim_libresoc_ibus_bte attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7200$2391_Y - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7203$2393_Y + assign $0\rhs_array_muxed31[1:0] \libresocsim_libresoc_dbus_bte attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed2[0:0] $and$ls180.v:7206$2395_Y + assign $0\rhs_array_muxed31[1:0] \libresocsim_libresoc_jtag_wb_bte end sync always - update \builder_sync_rhs_array_muxed2 $0\builder_sync_rhs_array_muxed2[0:0] + update \rhs_array_muxed31 $0\rhs_array_muxed31[1:0] + end + attribute \src "ls180.v:394.5-394.46" + process $proc$ls180.v:394$1760 + assign { } { } + assign $1\sdram_bankmachine0_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine0_req_wdata_ready $1\sdram_bankmachine0_req_wdata_ready[0:0] end - attribute \src "ls180.v:720.5-720.59" - process $proc$ls180.v:720$3125 + attribute \src "ls180.v:395.5-395.46" + process $proc$ls180.v:395$1761 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 + assign $1\sdram_bankmachine0_req_rdata_valid[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_cmd_buffer_source_valid $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] + update \sdram_bankmachine0_req_rdata_valid $1\sdram_bankmachine0_req_rdata_valid[0:0] end - attribute \src "ls180.v:7210.1-7226.4" - process $proc$ls180.v:7210$2396 + attribute \src "ls180.v:3951.1-3967.4" + process $proc$ls180.v:3951$1205 assign { } { } - assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 - attribute \src "ls180.v:7212.2-7225.9" - switch \main_sdram_steerer_sel + assign $0\array_muxed0[1:0] 2'00 + attribute \src "ls180.v:3953.2-3966.9" + switch \sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 + assign $0\array_muxed0[1:0] \sdram_nop_ba attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7217$2398_Y + assign $0\array_muxed0[1:0] \sdram_choose_req_cmd_payload_ba attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7220$2400_Y + assign $0\array_muxed0[1:0] \sdram_choose_req_cmd_payload_ba attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed3[0:0] $and$ls180.v:7223$2402_Y + assign $0\array_muxed0[1:0] \sdram_cmd_payload_ba end sync always - update \builder_sync_rhs_array_muxed3 $0\builder_sync_rhs_array_muxed3[0:0] - end - attribute \src "ls180.v:722.5-722.59" - process $proc$ls180.v:722$3126 - assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_cmd_buffer_source_first $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] + update \array_muxed0 $0\array_muxed0[1:0] end - attribute \src "ls180.v:7227.1-7243.4" - process $proc$ls180.v:7227$2403 + attribute \src "ls180.v:3968.1-3984.4" + process $proc$ls180.v:3968$1206 assign { } { } - assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 - attribute \src "ls180.v:7229.2-7242.9" - switch \main_sdram_steerer_sel + assign $0\array_muxed1[12:0] 13'0000000000000 + attribute \src "ls180.v:3970.2-3983.9" + switch \sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 + assign $0\array_muxed1[12:0] \sdram_nop_a attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7234$2405_Y + assign $0\array_muxed1[12:0] \sdram_choose_req_cmd_payload_a attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7237$2407_Y + assign $0\array_muxed1[12:0] \sdram_choose_req_cmd_payload_a attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed4[0:0] $and$ls180.v:7240$2409_Y + assign $0\array_muxed1[12:0] \sdram_cmd_payload_a end sync always - update \builder_sync_rhs_array_muxed4 $0\builder_sync_rhs_array_muxed4[0:0] + update \array_muxed1 $0\array_muxed1[12:0] end - attribute \src "ls180.v:723.5-723.58" - process $proc$ls180.v:723$3127 + attribute \src "ls180.v:397.5-397.42" + process $proc$ls180.v:397$1762 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0 + assign $1\sdram_bankmachine0_refresh_gnt[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_cmd_buffer_source_last $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] + update \sdram_bankmachine0_refresh_gnt $1\sdram_bankmachine0_refresh_gnt[0:0] end - attribute \src "ls180.v:724.5-724.64" - process $proc$ls180.v:724$3128 + attribute \src "ls180.v:398.5-398.40" + process $proc$ls180.v:398$1763 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0 + assign $1\sdram_bankmachine0_cmd_valid[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + update \sdram_bankmachine0_cmd_valid $1\sdram_bankmachine0_cmd_valid[0:0] end - attribute \src "ls180.v:7244.1-7260.4" - process $proc$ls180.v:7244$2410 + attribute \src "ls180.v:3985.1-4001.4" + process $proc$ls180.v:3985$1207 assign { } { } - assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 - attribute \src "ls180.v:7246.2-7259.9" - switch \main_sdram_steerer_sel + assign $0\array_muxed2[0:0] 1'0 + attribute \src "ls180.v:3987.2-4000.9" + switch \sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 + assign $0\array_muxed2[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7251$2412_Y + assign $0\array_muxed2[0:0] $and$ls180.v:3992$1209_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7254$2414_Y + assign $0\array_muxed2[0:0] $and$ls180.v:3995$1211_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed5[0:0] $and$ls180.v:7257$2416_Y + assign $0\array_muxed2[0:0] $and$ls180.v:3998$1213_Y end sync always - update \builder_sync_rhs_array_muxed5 $0\builder_sync_rhs_array_muxed5[0:0] + update \array_muxed2 $0\array_muxed2[0:0] end - attribute \src "ls180.v:725.12-725.74" - process $proc$ls180.v:725$3129 + attribute \src "ls180.v:399.5-399.40" + process $proc$ls180.v:399$1764 assign { } { } - assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + assign $1\sdram_bankmachine0_cmd_ready[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + update \sdram_bankmachine0_cmd_ready $1\sdram_bankmachine0_cmd_ready[0:0] end - attribute \src "ls180.v:726.12-726.47" - process $proc$ls180.v:726$3130 + attribute \src "ls180.v:400.12-400.52" + process $proc$ls180.v:400$1765 assign { } { } - assign $1\main_sdram_bankmachine3_row[12:0] 13'0000000000000 + assign $1\sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 sync always sync init - update \main_sdram_bankmachine3_row $1\main_sdram_bankmachine3_row[12:0] + update \sdram_bankmachine0_cmd_payload_a $1\sdram_bankmachine0_cmd_payload_a[12:0] end - attribute \src "ls180.v:7261.1-7277.4" - process $proc$ls180.v:7261$2417 + attribute \src "ls180.v:4002.1-4018.4" + process $proc$ls180.v:4002$1214 assign { } { } - assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 - attribute \src "ls180.v:7263.2-7276.9" - switch \main_sdram_steerer_sel + assign $0\array_muxed3[0:0] 1'0 + attribute \src "ls180.v:4004.2-4017.9" + switch \sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 + assign $0\array_muxed3[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7268$2419_Y + assign $0\array_muxed3[0:0] $and$ls180.v:4009$1216_Y attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7271$2421_Y + assign $0\array_muxed3[0:0] $and$ls180.v:4012$1218_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_rhs_array_muxed6[0:0] $and$ls180.v:7274$2423_Y + assign $0\array_muxed3[0:0] $and$ls180.v:4015$1220_Y end sync always - update \builder_sync_rhs_array_muxed6 $0\builder_sync_rhs_array_muxed6[0:0] - end - attribute \src "ls180.v:727.5-727.46" - process $proc$ls180.v:727$3131 - assign { } { } - assign $1\main_sdram_bankmachine3_row_opened[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_row_opened $1\main_sdram_bankmachine3_row_opened[0:0] + update \array_muxed3 $0\array_muxed3[0:0] end - attribute \src "ls180.v:7278.1-7306.4" - process $proc$ls180.v:7278$2424 + attribute \src "ls180.v:4019.1-4035.4" + process $proc$ls180.v:4019$1221 assign { } { } - assign $0\builder_sync_f_array_muxed0[0:0] 1'0 - attribute \src "ls180.v:7280.2-7305.9" - switch \main_spimaster34_mosi_sel - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [0] - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [1] - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [2] - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [3] + assign $0\array_muxed4[0:0] 1'0 + attribute \src "ls180.v:4021.2-4034.9" + switch \sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [4] + case 2'00 + assign $0\array_muxed4[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [5] + case 2'01 + assign $0\array_muxed4[0:0] $and$ls180.v:4026$1223_Y attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [6] + case 2'10 + assign $0\array_muxed4[0:0] $and$ls180.v:4029$1225_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_f_array_muxed0[0:0] \main_spimaster33_mosi_data [7] + assign $0\array_muxed4[0:0] $and$ls180.v:4032$1227_Y end sync always - update \builder_sync_f_array_muxed0 $0\builder_sync_f_array_muxed0[0:0] + update \array_muxed4 $0\array_muxed4[0:0] end - attribute \src "ls180.v:729.5-729.44" - process $proc$ls180.v:729$3132 + attribute \src "ls180.v:402.5-402.46" + process $proc$ls180.v:402$1766 assign { } { } - assign $1\main_sdram_bankmachine3_row_open[0:0] 1'0 + assign $1\sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_row_open $1\main_sdram_bankmachine3_row_open[0:0] + update \sdram_bankmachine0_cmd_payload_cas $1\sdram_bankmachine0_cmd_payload_cas[0:0] end - attribute \src "ls180.v:730.5-730.45" - process $proc$ls180.v:730$3133 + attribute \src "ls180.v:403.5-403.46" + process $proc$ls180.v:403$1767 assign { } { } - assign $1\main_sdram_bankmachine3_row_close[0:0] 1'0 + assign $1\sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 sync always sync init - update \main_sdram_bankmachine3_row_close $1\main_sdram_bankmachine3_row_close[0:0] + update \sdram_bankmachine0_cmd_payload_ras $1\sdram_bankmachine0_cmd_payload_ras[0:0] end - attribute \src "ls180.v:7307.1-7335.4" - process $proc$ls180.v:7307$2425 + attribute \src "ls180.v:4036.1-4052.4" + process $proc$ls180.v:4036$1228 assign { } { } - assign $0\builder_sync_f_array_muxed1[0:0] 1'0 - attribute \src "ls180.v:7309.2-7334.9" - switch \main_spisdcard_mosi_sel - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [0] - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [1] - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [2] - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [3] + assign $0\array_muxed5[0:0] 1'0 + attribute \src "ls180.v:4038.2-4051.9" + switch \sdram_steerer_sel attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [4] + case 2'00 + assign $0\array_muxed5[0:0] 1'0 attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [5] + case 2'01 + assign $0\array_muxed5[0:0] $and$ls180.v:4043$1230_Y attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [6] + case 2'10 + assign $0\array_muxed5[0:0] $and$ls180.v:4046$1232_Y attribute \src "ls180.v:0.0-0.0" case - assign $0\builder_sync_f_array_muxed1[0:0] \main_spisdcard_mosi_data [7] + assign $0\array_muxed5[0:0] $and$ls180.v:4049$1234_Y end sync always - update \builder_sync_f_array_muxed1 $0\builder_sync_f_array_muxed1[0:0] - end - attribute \src "ls180.v:731.5-731.54" - process $proc$ls180.v:731$3134 - assign { } { } - assign $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_row_col_n_addr_sel $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] - end - attribute \src "ls180.v:733.32-733.76" - process $proc$ls180.v:733$3135 - assign { } { } - assign $1\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 - sync always - sync init - update \main_sdram_bankmachine3_twtpcon_ready $1\main_sdram_bankmachine3_twtpcon_ready[0:0] - end - attribute \src "ls180.v:734.11-734.55" - process $proc$ls180.v:734$3136 - assign { } { } - assign $1\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 - sync always - sync init - update \main_sdram_bankmachine3_twtpcon_count $1\main_sdram_bankmachine3_twtpcon_count[2:0] - end - attribute \src "ls180.v:736.32-736.75" - process $proc$ls180.v:736$3137 - assign { } { } - assign $0\main_sdram_bankmachine3_trccon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine3_trccon_ready $0\main_sdram_bankmachine3_trccon_ready[0:0] - sync init - end - attribute \src "ls180.v:738.32-738.76" - process $proc$ls180.v:738$3138 - assign { } { } - assign $0\main_sdram_bankmachine3_trascon_ready[0:0] 1'1 - sync always - update \main_sdram_bankmachine3_trascon_ready $0\main_sdram_bankmachine3_trascon_ready[0:0] - sync init - end - attribute \src "ls180.v:7393.1-7403.4" - process $proc$ls180.v:7393$2426 - assign { } { } - assign $0\main_gpiotristateasic0_status[15:0] [15:8] 8'00000000 - assign $0\main_gpiotristateasic0_status[15:0] [0] \builder_multiregimpl1_regs1 - assign $0\main_gpiotristateasic0_status[15:0] [1] \builder_multiregimpl2_regs1 - assign $0\main_gpiotristateasic0_status[15:0] [2] \builder_multiregimpl3_regs1 - assign $0\main_gpiotristateasic0_status[15:0] [3] \builder_multiregimpl4_regs1 - assign $0\main_gpiotristateasic0_status[15:0] [4] \builder_multiregimpl5_regs1 - assign $0\main_gpiotristateasic0_status[15:0] [5] \builder_multiregimpl6_regs1 - assign $0\main_gpiotristateasic0_status[15:0] [6] \builder_multiregimpl7_regs1 - assign $0\main_gpiotristateasic0_status[15:0] [7] \builder_multiregimpl8_regs1 - sync always - update \main_gpiotristateasic0_status $0\main_gpiotristateasic0_status[15:0] - end - attribute \src "ls180.v:74.11-74.52" - process $proc$ls180.v:74$2882 - assign { } { } - assign $0\main_libresocsim_libresoc_dbus_cti[2:0] 3'000 - sync always - update \main_libresocsim_libresoc_dbus_cti $0\main_libresocsim_libresoc_dbus_cti[2:0] - sync init - end - attribute \src "ls180.v:7404.1-7414.4" - process $proc$ls180.v:7404$2427 - assign { } { } - assign $0\main_gpiotristateasic1_status[15:0] [7:0] 8'00000000 - assign $0\main_gpiotristateasic1_status[15:0] [8] \builder_multiregimpl9_regs1 - assign $0\main_gpiotristateasic1_status[15:0] [9] \builder_multiregimpl10_regs1 - assign $0\main_gpiotristateasic1_status[15:0] [10] \builder_multiregimpl11_regs1 - assign $0\main_gpiotristateasic1_status[15:0] [11] \builder_multiregimpl12_regs1 - assign $0\main_gpiotristateasic1_status[15:0] [12] \builder_multiregimpl13_regs1 - assign $0\main_gpiotristateasic1_status[15:0] [13] \builder_multiregimpl14_regs1 - assign $0\main_gpiotristateasic1_status[15:0] [14] \builder_multiregimpl15_regs1 - assign $0\main_gpiotristateasic1_status[15:0] [15] \builder_multiregimpl16_regs1 - sync always - update \main_gpiotristateasic1_status $0\main_gpiotristateasic1_status[15:0] - end - attribute \src "ls180.v:741.5-741.44" - process $proc$ls180.v:741$3139 - assign { } { } - assign $0\main_sdram_choose_cmd_want_reads[0:0] 1'0 - sync always - update \main_sdram_choose_cmd_want_reads $0\main_sdram_choose_cmd_want_reads[0:0] - sync init - end - attribute \src "ls180.v:742.5-742.45" - process $proc$ls180.v:742$3140 - assign { } { } - assign $0\main_sdram_choose_cmd_want_writes[0:0] 1'0 - sync always - update \main_sdram_choose_cmd_want_writes $0\main_sdram_choose_cmd_want_writes[0:0] - sync init - end - attribute \src "ls180.v:743.5-743.43" - process $proc$ls180.v:743$3141 - assign { } { } - assign $0\main_sdram_choose_cmd_want_cmds[0:0] 1'0 - sync always - update \main_sdram_choose_cmd_want_cmds $0\main_sdram_choose_cmd_want_cmds[0:0] - sync init - end - attribute \src "ls180.v:7435.1-7437.4" - process $proc$ls180.v:7435$2428 - assign { } { } - assign $0\main_int_rst[0:0] \sys_rst - sync posedge \por_clk - update \main_int_rst $0\main_int_rst[0:0] - end - attribute \src "ls180.v:7439.1-7509.4" - process $proc$ls180.v:7439$2429 - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\sdram_a[12:0] [0] \main_dfi_p0_address [0] - assign $0\sdram_a[12:0] [1] \main_dfi_p0_address [1] - assign $0\sdram_a[12:0] [2] \main_dfi_p0_address [2] - assign $0\sdram_a[12:0] [3] \main_dfi_p0_address [3] - assign $0\sdram_a[12:0] [4] \main_dfi_p0_address [4] - assign $0\sdram_a[12:0] [5] \main_dfi_p0_address [5] - assign $0\sdram_a[12:0] [6] \main_dfi_p0_address [6] - assign $0\sdram_a[12:0] [7] \main_dfi_p0_address [7] - assign $0\sdram_a[12:0] [8] \main_dfi_p0_address [8] - assign $0\sdram_a[12:0] [9] \main_dfi_p0_address [9] - assign $0\sdram_a[12:0] [10] \main_dfi_p0_address [10] - assign $0\sdram_a[12:0] [11] \main_dfi_p0_address [11] - assign $0\sdram_a[12:0] [12] \main_dfi_p0_address [12] - assign $0\sdram_ba[1:0] [0] \main_dfi_p0_bank [0] - assign $0\sdram_ba[1:0] [1] \main_dfi_p0_bank [1] - assign $0\sdram_cas_n[0:0] \main_dfi_p0_cas_n - assign $0\sdram_ras_n[0:0] \main_dfi_p0_ras_n - assign $0\sdram_we_n[0:0] \main_dfi_p0_we_n - assign $0\sdram_cke[0:0] \main_dfi_p0_cke - assign $0\sdram_cs_n[0:0] \main_dfi_p0_cs_n - assign $0\sdram_dq_oe[0:0] \main_dfi_p0_wrdata_en - assign $0\sdram_dq_o[15:0] [0] \main_dfi_p0_wrdata [0] - assign $0\main_dfi_p0_rddata[15:0] [0] \sdram_dq_i [0] - assign $0\sdram_dq_o[15:0] [1] \main_dfi_p0_wrdata [1] - assign $0\main_dfi_p0_rddata[15:0] [1] \sdram_dq_i [1] - assign $0\sdram_dq_o[15:0] [2] \main_dfi_p0_wrdata [2] - assign $0\main_dfi_p0_rddata[15:0] [2] \sdram_dq_i [2] - assign $0\sdram_dq_o[15:0] [3] \main_dfi_p0_wrdata [3] - assign $0\main_dfi_p0_rddata[15:0] [3] \sdram_dq_i [3] - assign $0\sdram_dq_o[15:0] [4] \main_dfi_p0_wrdata [4] - assign $0\main_dfi_p0_rddata[15:0] [4] \sdram_dq_i [4] - assign $0\sdram_dq_o[15:0] [5] \main_dfi_p0_wrdata [5] - assign $0\main_dfi_p0_rddata[15:0] [5] \sdram_dq_i [5] - assign $0\sdram_dq_o[15:0] [6] \main_dfi_p0_wrdata [6] - assign $0\main_dfi_p0_rddata[15:0] [6] \sdram_dq_i [6] - assign $0\sdram_dq_o[15:0] [7] \main_dfi_p0_wrdata [7] - assign $0\main_dfi_p0_rddata[15:0] [7] \sdram_dq_i [7] - assign $0\sdram_dq_o[15:0] [8] \main_dfi_p0_wrdata [8] - assign $0\main_dfi_p0_rddata[15:0] [8] \sdram_dq_i [8] - assign $0\sdram_dq_o[15:0] [9] \main_dfi_p0_wrdata [9] - assign $0\main_dfi_p0_rddata[15:0] [9] \sdram_dq_i [9] - assign $0\sdram_dq_o[15:0] [10] \main_dfi_p0_wrdata [10] - assign $0\main_dfi_p0_rddata[15:0] [10] \sdram_dq_i [10] - assign $0\sdram_dq_o[15:0] [11] \main_dfi_p0_wrdata [11] - assign $0\main_dfi_p0_rddata[15:0] [11] \sdram_dq_i [11] - assign $0\sdram_dq_o[15:0] [12] \main_dfi_p0_wrdata [12] - assign $0\main_dfi_p0_rddata[15:0] [12] \sdram_dq_i [12] - assign $0\sdram_dq_o[15:0] [13] \main_dfi_p0_wrdata [13] - assign $0\main_dfi_p0_rddata[15:0] [13] \sdram_dq_i [13] - assign $0\sdram_dq_o[15:0] [14] \main_dfi_p0_wrdata [14] - assign $0\main_dfi_p0_rddata[15:0] [14] \sdram_dq_i [14] - assign $0\sdram_dq_o[15:0] [15] \main_dfi_p0_wrdata [15] - assign $0\main_dfi_p0_rddata[15:0] [15] \sdram_dq_i [15] - assign $0\sdram_dm[1:0] [0] $and$ls180.v:7493$2430_Y - assign $0\sdram_dm[1:0] [1] $and$ls180.v:7494$2431_Y - assign $0\sdram_clock[0:0] \sys_clk_1 - assign $0\sdcard_clk[0:0] $and$ls180.v:7496$2433_Y - assign $0\sdcard_cmd_oe[0:0] \main_sdphy_sdpads_cmd_oe - assign $0\sdcard_cmd_o[0:0] \main_sdphy_sdpads_cmd_o - assign $0\main_sdphy_sdpads_cmd_i[0:0] \sdcard_cmd_i - assign $0\sdcard_data_oe[0:0] \main_sdphy_sdpads_data_oe - assign $0\sdcard_data_o[3:0] [0] \main_sdphy_sdpads_data_o [0] - assign $0\main_sdphy_sdpads_data_i[3:0] [0] \sdcard_data_i [0] - assign $0\sdcard_data_o[3:0] [1] \main_sdphy_sdpads_data_o [1] - assign $0\main_sdphy_sdpads_data_i[3:0] [1] \sdcard_data_i [1] - assign $0\sdcard_data_o[3:0] [2] \main_sdphy_sdpads_data_o [2] - assign $0\main_sdphy_sdpads_data_i[3:0] [2] \sdcard_data_i [2] - assign $0\sdcard_data_o[3:0] [3] \main_sdphy_sdpads_data_o [3] - assign $0\main_sdphy_sdpads_data_i[3:0] [3] \sdcard_data_i [3] - sync posedge \sdrio_clk - update \sdcard_clk $0\sdcard_clk[0:0] - update \sdcard_cmd_o $0\sdcard_cmd_o[0:0] - update \sdcard_cmd_oe $0\sdcard_cmd_oe[0:0] - update \sdcard_data_o $0\sdcard_data_o[3:0] - update \sdcard_data_oe $0\sdcard_data_oe[0:0] - update \sdram_a $0\sdram_a[12:0] - update \sdram_dq_o $0\sdram_dq_o[15:0] - update \sdram_dq_oe $0\sdram_dq_oe[0:0] - update \sdram_we_n $0\sdram_we_n[0:0] - update \sdram_ras_n $0\sdram_ras_n[0:0] - update \sdram_cas_n $0\sdram_cas_n[0:0] - update \sdram_cs_n $0\sdram_cs_n[0:0] - update \sdram_cke $0\sdram_cke[0:0] - update \sdram_ba $0\sdram_ba[1:0] - update \sdram_dm $0\sdram_dm[1:0] - update \sdram_clock $0\sdram_clock[0:0] - update \main_dfi_p0_rddata $0\main_dfi_p0_rddata[15:0] - update \main_sdphy_sdpads_cmd_i $0\main_sdphy_sdpads_cmd_i[0:0] - update \main_sdphy_sdpads_data_i $0\main_sdphy_sdpads_data_i[3:0] - end - attribute \src "ls180.v:744.5-744.48" - process $proc$ls180.v:744$3142 - assign { } { } - assign $0\main_sdram_choose_cmd_want_activates[0:0] 1'0 - sync always - update \main_sdram_choose_cmd_want_activates $0\main_sdram_choose_cmd_want_activates[0:0] - sync init - end - attribute \src "ls180.v:746.5-746.43" - process $proc$ls180.v:746$3143 - assign { } { } - assign $0\main_sdram_choose_cmd_cmd_ready[0:0] 1'0 - sync always - update \main_sdram_choose_cmd_cmd_ready $0\main_sdram_choose_cmd_cmd_ready[0:0] - sync init - end - attribute \src "ls180.v:749.5-749.49" - process $proc$ls180.v:749$3144 - assign { } { } - assign $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 - sync always - sync init - update \main_sdram_choose_cmd_cmd_payload_cas $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] - end - attribute \src "ls180.v:75.11-75.52" - process $proc$ls180.v:75$2883 - assign { } { } - assign $0\main_libresocsim_libresoc_dbus_bte[1:0] 2'00 - sync always - update \main_libresocsim_libresoc_dbus_bte $0\main_libresocsim_libresoc_dbus_bte[1:0] - sync init + update \array_muxed5 $0\array_muxed5[0:0] end - attribute \src "ls180.v:750.5-750.49" - process $proc$ls180.v:750$3145 + attribute \src "ls180.v:404.5-404.45" + process $proc$ls180.v:404$1768 assign { } { } - assign $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 + assign $1\sdram_bankmachine0_cmd_payload_we[0:0] 1'0 sync always sync init - update \main_sdram_choose_cmd_cmd_payload_ras $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] + update \sdram_bankmachine0_cmd_payload_we $1\sdram_bankmachine0_cmd_payload_we[0:0] end - attribute \src "ls180.v:751.5-751.48" - process $proc$ls180.v:751$3146 + attribute \src "ls180.v:405.5-405.49" + process $proc$ls180.v:405$1769 assign { } { } - assign $1\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 + assign $1\sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 sync always sync init - update \main_sdram_choose_cmd_cmd_payload_we $1\main_sdram_choose_cmd_cmd_payload_we[0:0] - end - attribute \src "ls180.v:7511.1-10140.4" - process $proc$ls180.v:7511$2434 - assign $0\spimaster_clk[0:0] \spimaster_clk - assign $0\spimaster_mosi[0:0] \spimaster_mosi - assign { } { } - assign $0\spisdcard_clk[0:0] \spisdcard_clk - assign $0\spisdcard_mosi[0:0] \spisdcard_mosi - assign { } { } - assign $0\uart_tx[0:0] \uart_tx - assign $0\pwm[1:0] \pwm - assign $0\main_libresocsim_reset_storage[0:0] \main_libresocsim_reset_storage - assign { } { } - assign $0\main_libresocsim_scratch_storage[31:0] \main_libresocsim_scratch_storage - assign { } { } - assign $0\main_libresocsim_bus_errors[31:0] \main_libresocsim_bus_errors - assign { } { } - assign $0\main_libresocsim_load_storage[31:0] \main_libresocsim_load_storage - assign { } { } - assign $0\main_libresocsim_reload_storage[31:0] \main_libresocsim_reload_storage - assign { } { } - assign $0\main_libresocsim_en_storage[0:0] \main_libresocsim_en_storage - assign { } { } - assign $0\main_libresocsim_update_value_storage[0:0] \main_libresocsim_update_value_storage - assign { } { } - assign $0\main_libresocsim_value_status[31:0] \main_libresocsim_value_status - assign $0\main_libresocsim_zero_pending[0:0] \main_libresocsim_zero_pending - assign { } { } - assign $0\main_libresocsim_eventmanager_storage[0:0] \main_libresocsim_eventmanager_storage - assign { } { } - assign $0\main_libresocsim_value[31:0] \main_libresocsim_value - assign { } { } - assign $0\main_converter0_counter[0:0] \main_converter0_counter - assign $0\main_converter0_dat_r[63:0] \main_converter0_dat_r - assign $0\main_converter1_counter[0:0] \main_converter1_counter - assign $0\main_converter1_dat_r[63:0] \main_converter1_dat_r - assign { } { } - assign { } { } - assign $0\main_sdram_storage[3:0] \main_sdram_storage - assign { } { } - assign $0\main_sdram_command_storage[5:0] \main_sdram_command_storage - assign { } { } - assign $0\main_sdram_address_storage[12:0] \main_sdram_address_storage - assign { } { } - assign $0\main_sdram_baddress_storage[1:0] \main_sdram_baddress_storage - assign { } { } - assign $0\main_sdram_wrdata_storage[15:0] \main_sdram_wrdata_storage - assign { } { } - assign $0\main_sdram_status[15:0] \main_sdram_status - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign $0\main_sdram_timer_count1[9:0] \main_sdram_timer_count1 - assign { } { } - assign $0\main_sdram_postponer_count[0:0] \main_sdram_postponer_count - assign { } { } - assign $0\main_sdram_sequencer_counter[3:0] \main_sdram_sequencer_counter - assign $0\main_sdram_sequencer_count[0:0] \main_sdram_sequencer_count - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_level - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_produce - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_consume - assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_source_valid - assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_source_first - assign $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] \main_sdram_bankmachine0_cmd_buffer_source_last - assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_we - assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr - assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_row - assign $0\main_sdram_bankmachine0_row_opened[0:0] \main_sdram_bankmachine0_row_opened - assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] \main_sdram_bankmachine0_twtpcon_ready - assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] \main_sdram_bankmachine0_twtpcon_count - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_level - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_produce - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_consume - assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_source_valid - assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_source_first - assign $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] \main_sdram_bankmachine1_cmd_buffer_source_last - assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_we - assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr - assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_row - assign $0\main_sdram_bankmachine1_row_opened[0:0] \main_sdram_bankmachine1_row_opened - assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] \main_sdram_bankmachine1_twtpcon_ready - assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] \main_sdram_bankmachine1_twtpcon_count - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_level - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_produce - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_consume - assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_source_valid - assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_source_first - assign $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] \main_sdram_bankmachine2_cmd_buffer_source_last - assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_we - assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr - assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_row - assign $0\main_sdram_bankmachine2_row_opened[0:0] \main_sdram_bankmachine2_row_opened - assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] \main_sdram_bankmachine2_twtpcon_ready - assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] \main_sdram_bankmachine2_twtpcon_count - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_level - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_produce - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_consume - assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_source_valid - assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_source_first - assign $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] \main_sdram_bankmachine3_cmd_buffer_source_last - assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_we - assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr - assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_row - assign $0\main_sdram_bankmachine3_row_opened[0:0] \main_sdram_bankmachine3_row_opened - assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] \main_sdram_bankmachine3_twtpcon_ready - assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] \main_sdram_bankmachine3_twtpcon_count - assign $0\main_sdram_choose_cmd_grant[1:0] \main_sdram_choose_cmd_grant - assign $0\main_sdram_choose_req_grant[1:0] \main_sdram_choose_req_grant - assign $0\main_sdram_tccdcon_ready[0:0] \main_sdram_tccdcon_ready - assign $0\main_sdram_tccdcon_count[0:0] \main_sdram_tccdcon_count - assign $0\main_sdram_twtrcon_ready[0:0] \main_sdram_twtrcon_ready - assign $0\main_sdram_twtrcon_count[2:0] \main_sdram_twtrcon_count - assign $0\main_sdram_time0[4:0] \main_sdram_time0 - assign $0\main_sdram_time1[3:0] \main_sdram_time1 - assign $0\main_socbushandler_counter[0:0] \main_socbushandler_counter - assign $0\main_socbushandler_dat_r[63:0] \main_socbushandler_dat_r - assign $0\main_converter_counter[0:0] \main_converter_counter - assign $0\main_converter_dat_r[31:0] \main_converter_dat_r - assign $0\main_cmd_consumed[0:0] \main_cmd_consumed - assign $0\main_wdata_consumed[0:0] \main_wdata_consumed - assign $0\main_uart_phy_storage[31:0] \main_uart_phy_storage - assign { } { } - assign { } { } - assign $0\main_uart_phy_uart_clk_txen[0:0] \main_uart_phy_uart_clk_txen - assign $0\main_uart_phy_phase_accumulator_tx[31:0] \main_uart_phy_phase_accumulator_tx - assign $0\main_uart_phy_tx_reg[7:0] \main_uart_phy_tx_reg - assign $0\main_uart_phy_tx_bitcount[3:0] \main_uart_phy_tx_bitcount - assign $0\main_uart_phy_tx_busy[0:0] \main_uart_phy_tx_busy - assign { } { } - assign $0\main_uart_phy_source_payload_data[7:0] \main_uart_phy_source_payload_data - assign $0\main_uart_phy_uart_clk_rxen[0:0] \main_uart_phy_uart_clk_rxen - assign $0\main_uart_phy_phase_accumulator_rx[31:0] \main_uart_phy_phase_accumulator_rx - assign { } { } - assign $0\main_uart_phy_rx_reg[7:0] \main_uart_phy_rx_reg - assign $0\main_uart_phy_rx_bitcount[3:0] \main_uart_phy_rx_bitcount - assign $0\main_uart_phy_rx_busy[0:0] \main_uart_phy_rx_busy - assign $0\main_uart_tx_pending[0:0] \main_uart_tx_pending - assign { } { } - assign $0\main_uart_rx_pending[0:0] \main_uart_rx_pending - assign { } { } - assign $0\main_uart_eventmanager_storage[1:0] \main_uart_eventmanager_storage - assign { } { } - assign $0\main_uart_tx_fifo_readable[0:0] \main_uart_tx_fifo_readable - assign $0\main_uart_tx_fifo_level0[4:0] \main_uart_tx_fifo_level0 - assign $0\main_uart_tx_fifo_produce[3:0] \main_uart_tx_fifo_produce - assign $0\main_uart_tx_fifo_consume[3:0] \main_uart_tx_fifo_consume - assign $0\main_uart_rx_fifo_readable[0:0] \main_uart_rx_fifo_readable - assign $0\main_uart_rx_fifo_level0[4:0] \main_uart_rx_fifo_level0 - assign $0\main_uart_rx_fifo_produce[3:0] \main_uart_rx_fifo_produce - assign $0\main_uart_rx_fifo_consume[3:0] \main_uart_rx_fifo_consume - assign $0\main_gpiotristateasic1_oe_storage[15:0] \main_gpiotristateasic1_oe_storage - assign { } { } - assign $0\main_gpiotristateasic1_out_storage[15:0] \main_gpiotristateasic1_out_storage - assign { } { } - assign $0\main_spimaster5_miso[7:0] \main_spimaster5_miso - assign $0\main_spimaster11_storage[15:0] \main_spimaster11_storage - assign { } { } - assign $0\main_spimaster16_storage[7:0] \main_spimaster16_storage - assign { } { } - assign $0\main_spimaster21_storage[0:0] \main_spimaster21_storage - assign { } { } - assign $0\main_spimaster23_storage[0:0] \main_spimaster23_storage - assign { } { } - assign $0\main_spimaster27_count[2:0] \main_spimaster27_count - assign { } { } - assign $0\main_spimaster33_mosi_data[7:0] \main_spimaster33_mosi_data - assign $0\main_spimaster34_mosi_sel[2:0] \main_spimaster34_mosi_sel - assign $0\main_spimaster35_miso_data[7:0] \main_spimaster35_miso_data - assign $0\main_spisdcard_miso[7:0] \main_spisdcard_miso - assign $0\main_spisdcard_control_storage[15:0] \main_spisdcard_control_storage - assign { } { } - assign $0\main_spisdcard_mosi_storage[7:0] \main_spisdcard_mosi_storage - assign { } { } - assign $0\main_spisdcard_cs_storage[0:0] \main_spisdcard_cs_storage - assign { } { } - assign $0\main_spisdcard_loopback_storage[0:0] \main_spisdcard_loopback_storage - assign { } { } - assign $0\main_spisdcard_count[2:0] \main_spisdcard_count - assign { } { } - assign $0\main_spisdcard_mosi_data[7:0] \main_spisdcard_mosi_data - assign $0\main_spisdcard_mosi_sel[2:0] \main_spisdcard_mosi_sel - assign $0\main_spisdcard_miso_data[7:0] \main_spisdcard_miso_data - assign $0\main_spimaster1_storage[15:0] \main_spimaster1_storage - assign { } { } - assign { } { } - assign $0\main_pwm0_counter[31:0] \main_pwm0_counter - assign $0\main_pwm0_enable_storage[0:0] \main_pwm0_enable_storage - assign { } { } - assign $0\main_pwm0_width_storage[31:0] \main_pwm0_width_storage - assign { } { } - assign $0\main_pwm0_period_storage[31:0] \main_pwm0_period_storage - assign { } { } - assign $0\main_pwm1_counter[31:0] \main_pwm1_counter - assign $0\main_pwm1_enable_storage[0:0] \main_pwm1_enable_storage - assign { } { } - assign $0\main_pwm1_width_storage[31:0] \main_pwm1_width_storage - assign { } { } - assign $0\main_pwm1_period_storage[31:0] \main_pwm1_period_storage - assign { } { } - assign $0\main_i2c_storage[2:0] \main_i2c_storage - assign { } { } - assign $0\main_sdphy_clocker_storage[8:0] \main_sdphy_clocker_storage - assign { } { } - assign { } { } - assign $0\main_sdphy_clocker_clks[8:0] \main_sdphy_clocker_clks - assign { } { } - assign $0\main_sdphy_init_count[7:0] \main_sdphy_init_count - assign $0\main_sdphy_cmdw_count[7:0] \main_sdphy_cmdw_count - assign $0\main_sdphy_cmdr_timeout[31:0] \main_sdphy_cmdr_timeout - assign $0\main_sdphy_cmdr_count[7:0] \main_sdphy_cmdr_count - assign $0\main_sdphy_cmdr_cmdr_run[0:0] \main_sdphy_cmdr_cmdr_run - assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] \main_sdphy_cmdr_cmdr_converter_source_first - assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] \main_sdphy_cmdr_cmdr_converter_source_last - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_converter_source_payload_data - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count - assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] \main_sdphy_cmdr_cmdr_converter_demux - assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] \main_sdphy_cmdr_cmdr_converter_strobe_all - assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] \main_sdphy_cmdr_cmdr_buf_source_valid - assign $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] \main_sdphy_cmdr_cmdr_buf_source_first - assign $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] \main_sdphy_cmdr_cmdr_buf_source_last - assign $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_buf_source_payload_data - assign $0\main_sdphy_cmdr_cmdr_reset[0:0] \main_sdphy_cmdr_cmdr_reset - assign $0\main_sdphy_dataw_count[7:0] \main_sdphy_dataw_count - assign $0\main_sdphy_dataw_crcr_run[0:0] \main_sdphy_dataw_crcr_run - assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] \main_sdphy_dataw_crcr_converter_source_first - assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] \main_sdphy_dataw_crcr_converter_source_last - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] \main_sdphy_dataw_crcr_converter_source_payload_data - assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count - assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] \main_sdphy_dataw_crcr_converter_demux - assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] \main_sdphy_dataw_crcr_converter_strobe_all - assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] \main_sdphy_dataw_crcr_buf_source_valid - assign $0\main_sdphy_dataw_crcr_buf_source_first[0:0] \main_sdphy_dataw_crcr_buf_source_first - assign $0\main_sdphy_dataw_crcr_buf_source_last[0:0] \main_sdphy_dataw_crcr_buf_source_last - assign $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] \main_sdphy_dataw_crcr_buf_source_payload_data - assign $0\main_sdphy_dataw_crcr_reset[0:0] \main_sdphy_dataw_crcr_reset - assign $0\main_sdphy_datar_timeout[31:0] \main_sdphy_datar_timeout - assign $0\main_sdphy_datar_count[9:0] \main_sdphy_datar_count - assign $0\main_sdphy_datar_datar_run[0:0] \main_sdphy_datar_datar_run - assign $0\main_sdphy_datar_datar_converter_source_first[0:0] \main_sdphy_datar_datar_converter_source_first - assign $0\main_sdphy_datar_datar_converter_source_last[0:0] \main_sdphy_datar_datar_converter_source_last - assign $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] \main_sdphy_datar_datar_converter_source_payload_data - assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] \main_sdphy_datar_datar_converter_source_payload_valid_token_count - assign $0\main_sdphy_datar_datar_converter_demux[0:0] \main_sdphy_datar_datar_converter_demux - assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] \main_sdphy_datar_datar_converter_strobe_all - assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] \main_sdphy_datar_datar_buf_source_valid - assign $0\main_sdphy_datar_datar_buf_source_first[0:0] \main_sdphy_datar_datar_buf_source_first - assign $0\main_sdphy_datar_datar_buf_source_last[0:0] \main_sdphy_datar_datar_buf_source_last - assign $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] \main_sdphy_datar_datar_buf_source_payload_data - assign $0\main_sdphy_datar_datar_reset[0:0] \main_sdphy_datar_datar_reset - assign $0\main_sdcore_cmd_argument_storage[31:0] \main_sdcore_cmd_argument_storage - assign { } { } - assign $0\main_sdcore_cmd_command_storage[31:0] \main_sdcore_cmd_command_storage - assign { } { } - assign $0\main_sdcore_cmd_response_status[127:0] \main_sdcore_cmd_response_status - assign $0\main_sdcore_block_length_storage[9:0] \main_sdcore_block_length_storage - assign { } { } - assign $0\main_sdcore_block_count_storage[31:0] \main_sdcore_block_count_storage - assign { } { } - assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] \main_sdcore_crc7_inserter_crcreg0 - assign $0\main_sdcore_crc16_inserter_cnt[2:0] \main_sdcore_crc16_inserter_cnt - assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] \main_sdcore_crc16_inserter_crc0_crcreg0 - assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] \main_sdcore_crc16_inserter_crc1_crcreg0 - assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] \main_sdcore_crc16_inserter_crc2_crcreg0 - assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] \main_sdcore_crc16_inserter_crc3_crcreg0 - assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] \main_sdcore_crc16_inserter_crctmp0 - assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] \main_sdcore_crc16_inserter_crctmp1 - assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] \main_sdcore_crc16_inserter_crctmp2 - assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] \main_sdcore_crc16_inserter_crctmp3 - assign $0\main_sdcore_crc16_checker_val[7:0] \main_sdcore_crc16_checker_val - assign $0\main_sdcore_crc16_checker_cnt[3:0] \main_sdcore_crc16_checker_cnt - assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] \main_sdcore_crc16_checker_crc0_crcreg0 - assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] \main_sdcore_crc16_checker_crc1_crcreg0 - assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] \main_sdcore_crc16_checker_crc2_crcreg0 - assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] \main_sdcore_crc16_checker_crc3_crcreg0 - assign $0\main_sdcore_crc16_checker_crctmp0[15:0] \main_sdcore_crc16_checker_crctmp0 - assign $0\main_sdcore_crc16_checker_crctmp1[15:0] \main_sdcore_crc16_checker_crctmp1 - assign $0\main_sdcore_crc16_checker_crctmp2[15:0] \main_sdcore_crc16_checker_crctmp2 - assign $0\main_sdcore_crc16_checker_crctmp3[15:0] \main_sdcore_crc16_checker_crctmp3 - assign $0\main_sdcore_crc16_checker_fifo0[15:0] \main_sdcore_crc16_checker_fifo0 - assign $0\main_sdcore_crc16_checker_fifo1[15:0] \main_sdcore_crc16_checker_fifo1 - assign $0\main_sdcore_crc16_checker_fifo2[15:0] \main_sdcore_crc16_checker_fifo2 - assign $0\main_sdcore_crc16_checker_fifo3[15:0] \main_sdcore_crc16_checker_fifo3 - assign $0\main_sdcore_cmd_count[2:0] \main_sdcore_cmd_count - assign $0\main_sdcore_cmd_done[0:0] \main_sdcore_cmd_done - assign $0\main_sdcore_cmd_error[0:0] \main_sdcore_cmd_error - assign $0\main_sdcore_cmd_timeout[0:0] \main_sdcore_cmd_timeout - assign $0\main_sdcore_data_count[31:0] \main_sdcore_data_count - assign $0\main_sdcore_data_done[0:0] \main_sdcore_data_done - assign $0\main_sdcore_data_error[0:0] \main_sdcore_data_error - assign $0\main_sdcore_data_timeout[0:0] \main_sdcore_data_timeout - assign $0\main_sdblock2mem_fifo_level[5:0] \main_sdblock2mem_fifo_level - assign $0\main_sdblock2mem_fifo_produce[4:0] \main_sdblock2mem_fifo_produce - assign $0\main_sdblock2mem_fifo_consume[4:0] \main_sdblock2mem_fifo_consume - assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_source_first - assign $0\main_sdblock2mem_converter_source_last[0:0] \main_sdblock2mem_converter_source_last - assign $0\main_sdblock2mem_converter_source_payload_data[63:0] \main_sdblock2mem_converter_source_payload_data - assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] \main_sdblock2mem_converter_source_payload_valid_token_count - assign $0\main_sdblock2mem_converter_demux[2:0] \main_sdblock2mem_converter_demux - assign $0\main_sdblock2mem_converter_strobe_all[0:0] \main_sdblock2mem_converter_strobe_all - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] \main_sdblock2mem_wishbonedmawriter_base_storage - assign { } { } - assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] \main_sdblock2mem_wishbonedmawriter_length_storage - assign { } { } - assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \main_sdblock2mem_wishbonedmawriter_enable_storage - assign { } { } - assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \main_sdblock2mem_wishbonedmawriter_loop_storage - assign { } { } - assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] \main_sdblock2mem_wishbonedmawriter_offset - assign $0\main_sdmem2block_dma_data[63:0] \main_sdmem2block_dma_data - assign $0\main_sdmem2block_dma_base_storage[63:0] \main_sdmem2block_dma_base_storage - assign { } { } - assign $0\main_sdmem2block_dma_length_storage[31:0] \main_sdmem2block_dma_length_storage - assign { } { } - assign $0\main_sdmem2block_dma_enable_storage[0:0] \main_sdmem2block_dma_enable_storage - assign { } { } - assign $0\main_sdmem2block_dma_loop_storage[0:0] \main_sdmem2block_dma_loop_storage - assign { } { } - assign $0\main_sdmem2block_dma_offset[31:0] \main_sdmem2block_dma_offset - assign $0\main_sdmem2block_converter_mux[2:0] \main_sdmem2block_converter_mux - assign $0\main_sdmem2block_fifo_level[5:0] \main_sdmem2block_fifo_level - assign $0\main_sdmem2block_fifo_produce[4:0] \main_sdmem2block_fifo_produce - assign $0\main_sdmem2block_fifo_consume[4:0] \main_sdmem2block_fifo_consume - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } - assign { } { } + update \sdram_bankmachine0_cmd_payload_is_cmd $1\sdram_bankmachine0_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:4053.1-4069.4" + process $proc$ls180.v:4053$1235 assign { } { } + assign $0\array_muxed6[0:0] 1'0 + attribute \src "ls180.v:4055.2-4068.9" + switch \sdram_steerer_sel + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\array_muxed6[0:0] 1'0 + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\array_muxed6[0:0] $and$ls180.v:4060$1237_Y + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\array_muxed6[0:0] $and$ls180.v:4063$1239_Y + attribute \src "ls180.v:0.0-0.0" + case + assign $0\array_muxed6[0:0] $and$ls180.v:4066$1241_Y + end + sync always + update \array_muxed6 $0\array_muxed6[0:0] + end + attribute \src "ls180.v:406.5-406.50" + process $proc$ls180.v:406$1770 assign { } { } + assign $1\sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine0_cmd_payload_is_read $1\sdram_bankmachine0_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:407.5-407.51" + process $proc$ls180.v:407$1771 assign { } { } + assign $1\sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine0_cmd_payload_is_write $1\sdram_bankmachine0_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:408.5-408.45" + process $proc$ls180.v:408$1772 assign { } { } + assign $1\sdram_bankmachine0_auto_precharge[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine0_auto_precharge $1\sdram_bankmachine0_auto_precharge[0:0] + end + attribute \src "ls180.v:411.5-411.62" + process $proc$ls180.v:411$1773 assign { } { } + assign $0\sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \sdram_bankmachine0_cmd_buffer_lookahead_sink_first $0\sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:412.5-412.61" + process $proc$ls180.v:412$1774 assign { } { } + assign $0\sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \sdram_bankmachine0_cmd_buffer_lookahead_sink_last $0\sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:4176.1-4178.4" + process $proc$ls180.v:4176$1242 assign { } { } + assign $0\int_rst[0:0] \sys_rst + sync posedge \por_clk + update \int_rst $0\int_rst[0:0] + end + attribute \src "ls180.v:4180.1-4285.4" + process $proc$ls180.v:4180$1243 assign { } { } assign { } { } assign { } { } @@ -294982,12 +267168,7 @@ module \ls180 assign { } { } assign { } { } assign { } { } - assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr - assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we - assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w - assign $0\builder_grant[2:0] \builder_grant assign { } { } - assign $0\builder_count[19:0] \builder_count assign { } { } assign { } { } assign { } { } @@ -294997,25 +267178,187 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_a[12:0] [0] \dfi_p0_address [0] + assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_a[12:0] [1] \dfi_p0_address [1] + assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_a[12:0] [2] \dfi_p0_address [2] + assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_a[12:0] [3] \dfi_p0_address [3] + assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_a[12:0] [4] \dfi_p0_address [4] + assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_a[12:0] [5] \dfi_p0_address [5] + assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_a[12:0] [6] \dfi_p0_address [6] + assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_a[12:0] [7] \dfi_p0_address [7] + assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_a[12:0] [8] \dfi_p0_address [8] + assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_a[12:0] [9] \dfi_p0_address [9] + assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_a[12:0] [10] \dfi_p0_address [10] + assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_a[12:0] [11] \dfi_p0_address [11] + assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_a[12:0] [12] \dfi_p0_address [12] + assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_ba[1:0] [0] \dfi_p0_bank [0] + assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_ba[1:0] [1] \dfi_p0_bank [1] + assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_cas_n[0:0] \dfi_p0_cas_n + assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_ras_n[0:0] \dfi_p0_ras_n + assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_we_n[0:0] \dfi_p0_we_n + assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_cke[0:0] \dfi_p0_cke + assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_cs_n[0:0] \dfi_p0_cs_n + assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe[0:0] \dfi_p0_wrdata_en + assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_dq_o[15:0] [0] \dfi_p0_wrdata [0] + assign $0\dfi_p0_rddata[15:0] [0] \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [0] + assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_dq_o[15:0] [1] \dfi_p0_wrdata [1] + assign $0\dfi_p0_rddata[15:0] [1] \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [1] + assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_dq_o[15:0] [2] \dfi_p0_wrdata [2] + assign $0\dfi_p0_rddata[15:0] [2] \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [2] + assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_dq_o[15:0] [3] \dfi_p0_wrdata [3] + assign $0\dfi_p0_rddata[15:0] [3] \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [3] + assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_dq_o[15:0] [4] \dfi_p0_wrdata [4] + assign $0\dfi_p0_rddata[15:0] [4] \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [4] + assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_dq_o[15:0] [5] \dfi_p0_wrdata [5] + assign $0\dfi_p0_rddata[15:0] [5] \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [5] + assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_dq_o[15:0] [6] \dfi_p0_wrdata [6] + assign $0\dfi_p0_rddata[15:0] [6] \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [6] + assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_dq_o[15:0] [7] \dfi_p0_wrdata [7] + assign $0\dfi_p0_rddata[15:0] [7] \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [7] + assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_dq_o[15:0] [8] \dfi_p0_wrdata [8] + assign $0\dfi_p0_rddata[15:0] [8] \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [8] + assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_dq_o[15:0] [9] \dfi_p0_wrdata [9] + assign $0\dfi_p0_rddata[15:0] [9] \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [9] + assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_dq_o[15:0] [10] \dfi_p0_wrdata [10] + assign $0\dfi_p0_rddata[15:0] [10] \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [10] + assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_dq_o[15:0] [11] \dfi_p0_wrdata [11] + assign $0\dfi_p0_rddata[15:0] [11] \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [11] + assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_dq_o[15:0] [12] \dfi_p0_wrdata [12] + assign $0\dfi_p0_rddata[15:0] [12] \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [12] + assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_dq_o[15:0] [13] \dfi_p0_wrdata [13] + assign $0\dfi_p0_rddata[15:0] [13] \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [13] + assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_dq_o[15:0] [14] \dfi_p0_wrdata [14] + assign $0\dfi_p0_rddata[15:0] [14] \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [14] + assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_dq_o[15:0] [15] \dfi_p0_wrdata [15] + assign $0\dfi_p0_rddata[15:0] [15] \libresocsim_libresoc_constraintmanager_obj_sdram_dq_i [15] + assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_dm[1:0] [0] $and$ls180.v:4234$1244_Y + assign $0\libresocsim_libresoc_constraintmanager_obj_sdram_dm[1:0] [1] $and$ls180.v:4235$1245_Y + assign $0\sdram_clock[0:0] \sys_clk_1 + assign $0\gpio0_pads_gpio0oe[7:0] [0] \gpio0_oe_storage [0] + assign $0\gpio0_pads_gpio0o[7:0] [0] \gpio0_out_storage [0] + assign $0\gpio0_status[7:0] [0] \gpio0_pads_gpio0i [0] + assign $0\gpio0_pads_gpio0oe[7:0] [1] \gpio0_oe_storage [1] + assign $0\gpio0_pads_gpio0o[7:0] [1] \gpio0_out_storage [1] + assign $0\gpio0_status[7:0] [1] \gpio0_pads_gpio0i [1] + assign $0\gpio0_pads_gpio0oe[7:0] [2] \gpio0_oe_storage [2] + assign $0\gpio0_pads_gpio0o[7:0] [2] \gpio0_out_storage [2] + assign $0\gpio0_status[7:0] [2] \gpio0_pads_gpio0i [2] + assign $0\gpio0_pads_gpio0oe[7:0] [3] \gpio0_oe_storage [3] + assign $0\gpio0_pads_gpio0o[7:0] [3] \gpio0_out_storage [3] + assign $0\gpio0_status[7:0] [3] \gpio0_pads_gpio0i [3] + assign $0\gpio0_pads_gpio0oe[7:0] [4] \gpio0_oe_storage [4] + assign $0\gpio0_pads_gpio0o[7:0] [4] \gpio0_out_storage [4] + assign $0\gpio0_status[7:0] [4] \gpio0_pads_gpio0i [4] + assign $0\gpio0_pads_gpio0oe[7:0] [5] \gpio0_oe_storage [5] + assign $0\gpio0_pads_gpio0o[7:0] [5] \gpio0_out_storage [5] + assign $0\gpio0_status[7:0] [5] \gpio0_pads_gpio0i [5] + assign $0\gpio0_pads_gpio0oe[7:0] [6] \gpio0_oe_storage [6] + assign $0\gpio0_pads_gpio0o[7:0] [6] \gpio0_out_storage [6] + assign $0\gpio0_status[7:0] [6] \gpio0_pads_gpio0i [6] + assign $0\gpio0_pads_gpio0oe[7:0] [7] \gpio0_oe_storage [7] + assign $0\gpio0_pads_gpio0o[7:0] [7] \gpio0_out_storage [7] + assign $0\gpio0_status[7:0] [7] \gpio0_pads_gpio0i [7] + assign $0\gpio1_pads_gpio1oe[7:0] [0] \gpio1_oe_storage [0] + assign $0\gpio1_pads_gpio1o[7:0] [0] \gpio1_out_storage [0] + assign $0\gpio1_status[7:0] [0] \gpio1_pads_gpio1i [0] + assign $0\gpio1_pads_gpio1oe[7:0] [1] \gpio1_oe_storage [1] + assign $0\gpio1_pads_gpio1o[7:0] [1] \gpio1_out_storage [1] + assign $0\gpio1_status[7:0] [1] \gpio1_pads_gpio1i [1] + assign $0\gpio1_pads_gpio1oe[7:0] [2] \gpio1_oe_storage [2] + assign $0\gpio1_pads_gpio1o[7:0] [2] \gpio1_out_storage [2] + assign $0\gpio1_status[7:0] [2] \gpio1_pads_gpio1i [2] + assign $0\gpio1_pads_gpio1oe[7:0] [3] \gpio1_oe_storage [3] + assign $0\gpio1_pads_gpio1o[7:0] [3] \gpio1_out_storage [3] + assign $0\gpio1_status[7:0] [3] \gpio1_pads_gpio1i [3] + assign $0\gpio1_pads_gpio1oe[7:0] [4] \gpio1_oe_storage [4] + assign $0\gpio1_pads_gpio1o[7:0] [4] \gpio1_out_storage [4] + assign $0\gpio1_status[7:0] [4] \gpio1_pads_gpio1i [4] + assign $0\gpio1_pads_gpio1oe[7:0] [5] \gpio1_oe_storage [5] + assign $0\gpio1_pads_gpio1o[7:0] [5] \gpio1_out_storage [5] + assign $0\gpio1_status[7:0] [5] \gpio1_pads_gpio1i [5] + assign $0\gpio1_pads_gpio1oe[7:0] [6] \gpio1_oe_storage [6] + assign $0\gpio1_pads_gpio1o[7:0] [6] \gpio1_out_storage [6] + assign $0\gpio1_status[7:0] [6] \gpio1_pads_gpio1i [6] + assign $0\gpio1_pads_gpio1oe[7:0] [7] \gpio1_oe_storage [7] + assign $0\gpio1_pads_gpio1o[7:0] [7] \gpio1_out_storage [7] + assign $0\gpio1_status[7:0] [7] \gpio1_pads_gpio1i [7] + sync posedge \sdrio_clk + update \libresocsim_libresoc_constraintmanager_obj_sdram_a $0\libresocsim_libresoc_constraintmanager_obj_sdram_a[12:0] + update \libresocsim_libresoc_constraintmanager_obj_sdram_dq_o $0\libresocsim_libresoc_constraintmanager_obj_sdram_dq_o[15:0] + update \libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe $0\libresocsim_libresoc_constraintmanager_obj_sdram_dq_oe[0:0] + update \libresocsim_libresoc_constraintmanager_obj_sdram_we_n $0\libresocsim_libresoc_constraintmanager_obj_sdram_we_n[0:0] + update \libresocsim_libresoc_constraintmanager_obj_sdram_ras_n $0\libresocsim_libresoc_constraintmanager_obj_sdram_ras_n[0:0] + update \libresocsim_libresoc_constraintmanager_obj_sdram_cas_n $0\libresocsim_libresoc_constraintmanager_obj_sdram_cas_n[0:0] + update \libresocsim_libresoc_constraintmanager_obj_sdram_cs_n $0\libresocsim_libresoc_constraintmanager_obj_sdram_cs_n[0:0] + update \libresocsim_libresoc_constraintmanager_obj_sdram_cke $0\libresocsim_libresoc_constraintmanager_obj_sdram_cke[0:0] + update \libresocsim_libresoc_constraintmanager_obj_sdram_ba $0\libresocsim_libresoc_constraintmanager_obj_sdram_ba[1:0] + update \libresocsim_libresoc_constraintmanager_obj_sdram_dm $0\libresocsim_libresoc_constraintmanager_obj_sdram_dm[1:0] + update \sdram_clock $0\sdram_clock[0:0] + update \dfi_p0_rddata $0\dfi_p0_rddata[15:0] + update \gpio0_status $0\gpio0_status[7:0] + update \gpio0_pads_gpio0o $0\gpio0_pads_gpio0o[7:0] + update \gpio0_pads_gpio0oe $0\gpio0_pads_gpio0oe[7:0] + update \gpio1_status $0\gpio1_status[7:0] + update \gpio1_pads_gpio1o $0\gpio1_pads_gpio1o[7:0] + update \gpio1_pads_gpio1oe $0\gpio1_pads_gpio1oe[7:0] + end + attribute \src "ls180.v:427.11-427.63" + process $proc$ls180.v:427$1775 assign { } { } + assign $1\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \sdram_bankmachine0_cmd_buffer_lookahead_level $1\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + end + attribute \src "ls180.v:428.5-428.59" + process $proc$ls180.v:428$1776 assign { } { } + assign $0\sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \sdram_bankmachine0_cmd_buffer_lookahead_replace $0\sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:4287.1-5487.4" + process $proc$ls180.v:4287$1246 + assign $0\libresocsim_reset_storage[0:0] \libresocsim_reset_storage assign { } { } + assign $0\libresocsim_scratch_storage[31:0] \libresocsim_scratch_storage assign { } { } + assign $0\libresocsim_bus_errors[31:0] \libresocsim_bus_errors + assign $0\libresocsim_libresoc_constraintmanager_obj_uart_tx[0:0] \libresocsim_libresoc_constraintmanager_obj_uart_tx assign { } { } + assign $0\libresocsim_load_storage[31:0] \libresocsim_load_storage assign { } { } + assign $0\libresocsim_reload_storage[31:0] \libresocsim_reload_storage assign { } { } + assign $0\libresocsim_en_storage[0:0] \libresocsim_en_storage assign { } { } + assign $0\libresocsim_update_value_storage[0:0] \libresocsim_update_value_storage assign { } { } + assign $0\libresocsim_value_status[31:0] \libresocsim_value_status + assign $0\libresocsim_zero_pending[0:0] \libresocsim_zero_pending assign { } { } + assign $0\libresocsim_eventmanager_storage[0:0] \libresocsim_eventmanager_storage assign { } { } + assign $0\libresocsim_value[31:0] \libresocsim_value assign { } { } + assign $0\converter0_counter[0:0] \converter0_counter + assign $0\converter0_dat_r[63:0] \converter0_dat_r + assign $0\converter1_counter[0:0] \converter1_counter + assign $0\converter1_dat_r[63:0] \converter1_dat_r assign { } { } assign { } { } + assign $0\sdram_storage[3:0] \sdram_storage assign { } { } + assign $0\sdram_command_storage[5:0] \sdram_command_storage assign { } { } + assign $0\sdram_address_storage[12:0] \sdram_address_storage assign { } { } + assign $0\sdram_baddress_storage[1:0] \sdram_baddress_storage assign { } { } + assign $0\sdram_wrdata_storage[15:0] \sdram_wrdata_storage assign { } { } + assign $0\sdram_status[15:0] \sdram_status assign { } { } assign { } { } assign { } { } @@ -295029,926 +267372,980 @@ module \ls180 assign { } { } assign { } { } assign { } { } + assign $0\sdram_timer_count1[9:0] \sdram_timer_count1 assign { } { } + assign $0\sdram_postponer_count[0:0] \sdram_postponer_count assign { } { } + assign $0\sdram_sequencer_counter[3:0] \sdram_sequencer_counter + assign $0\sdram_sequencer_count[0:0] \sdram_sequencer_count + assign $0\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] \sdram_bankmachine0_cmd_buffer_lookahead_level + assign $0\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] \sdram_bankmachine0_cmd_buffer_lookahead_produce + assign $0\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] \sdram_bankmachine0_cmd_buffer_lookahead_consume + assign $0\sdram_bankmachine0_cmd_buffer_source_valid[0:0] \sdram_bankmachine0_cmd_buffer_source_valid + assign $0\sdram_bankmachine0_cmd_buffer_source_first[0:0] \sdram_bankmachine0_cmd_buffer_source_first + assign $0\sdram_bankmachine0_cmd_buffer_source_last[0:0] \sdram_bankmachine0_cmd_buffer_source_last + assign $0\sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] \sdram_bankmachine0_cmd_buffer_source_payload_we + assign $0\sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \sdram_bankmachine0_cmd_buffer_source_payload_addr + assign $0\sdram_bankmachine0_row[12:0] \sdram_bankmachine0_row + assign $0\sdram_bankmachine0_row_opened[0:0] \sdram_bankmachine0_row_opened + assign $0\sdram_bankmachine0_twtpcon_ready[0:0] \sdram_bankmachine0_twtpcon_ready + assign $0\sdram_bankmachine0_twtpcon_count[2:0] \sdram_bankmachine0_twtpcon_count + assign $0\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] \sdram_bankmachine1_cmd_buffer_lookahead_level + assign $0\sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] \sdram_bankmachine1_cmd_buffer_lookahead_produce + assign $0\sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] \sdram_bankmachine1_cmd_buffer_lookahead_consume + assign $0\sdram_bankmachine1_cmd_buffer_source_valid[0:0] \sdram_bankmachine1_cmd_buffer_source_valid + assign $0\sdram_bankmachine1_cmd_buffer_source_first[0:0] \sdram_bankmachine1_cmd_buffer_source_first + assign $0\sdram_bankmachine1_cmd_buffer_source_last[0:0] \sdram_bankmachine1_cmd_buffer_source_last + assign $0\sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] \sdram_bankmachine1_cmd_buffer_source_payload_we + assign $0\sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \sdram_bankmachine1_cmd_buffer_source_payload_addr + assign $0\sdram_bankmachine1_row[12:0] \sdram_bankmachine1_row + assign $0\sdram_bankmachine1_row_opened[0:0] \sdram_bankmachine1_row_opened + assign $0\sdram_bankmachine1_twtpcon_ready[0:0] \sdram_bankmachine1_twtpcon_ready + assign $0\sdram_bankmachine1_twtpcon_count[2:0] \sdram_bankmachine1_twtpcon_count + assign $0\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] \sdram_bankmachine2_cmd_buffer_lookahead_level + assign $0\sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] \sdram_bankmachine2_cmd_buffer_lookahead_produce + assign $0\sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] \sdram_bankmachine2_cmd_buffer_lookahead_consume + assign $0\sdram_bankmachine2_cmd_buffer_source_valid[0:0] \sdram_bankmachine2_cmd_buffer_source_valid + assign $0\sdram_bankmachine2_cmd_buffer_source_first[0:0] \sdram_bankmachine2_cmd_buffer_source_first + assign $0\sdram_bankmachine2_cmd_buffer_source_last[0:0] \sdram_bankmachine2_cmd_buffer_source_last + assign $0\sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] \sdram_bankmachine2_cmd_buffer_source_payload_we + assign $0\sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \sdram_bankmachine2_cmd_buffer_source_payload_addr + assign $0\sdram_bankmachine2_row[12:0] \sdram_bankmachine2_row + assign $0\sdram_bankmachine2_row_opened[0:0] \sdram_bankmachine2_row_opened + assign $0\sdram_bankmachine2_twtpcon_ready[0:0] \sdram_bankmachine2_twtpcon_ready + assign $0\sdram_bankmachine2_twtpcon_count[2:0] \sdram_bankmachine2_twtpcon_count + assign $0\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] \sdram_bankmachine3_cmd_buffer_lookahead_level + assign $0\sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] \sdram_bankmachine3_cmd_buffer_lookahead_produce + assign $0\sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] \sdram_bankmachine3_cmd_buffer_lookahead_consume + assign $0\sdram_bankmachine3_cmd_buffer_source_valid[0:0] \sdram_bankmachine3_cmd_buffer_source_valid + assign $0\sdram_bankmachine3_cmd_buffer_source_first[0:0] \sdram_bankmachine3_cmd_buffer_source_first + assign $0\sdram_bankmachine3_cmd_buffer_source_last[0:0] \sdram_bankmachine3_cmd_buffer_source_last + assign $0\sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] \sdram_bankmachine3_cmd_buffer_source_payload_we + assign $0\sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \sdram_bankmachine3_cmd_buffer_source_payload_addr + assign $0\sdram_bankmachine3_row[12:0] \sdram_bankmachine3_row + assign $0\sdram_bankmachine3_row_opened[0:0] \sdram_bankmachine3_row_opened + assign $0\sdram_bankmachine3_twtpcon_ready[0:0] \sdram_bankmachine3_twtpcon_ready + assign $0\sdram_bankmachine3_twtpcon_count[2:0] \sdram_bankmachine3_twtpcon_count + assign $0\sdram_choose_cmd_grant[1:0] \sdram_choose_cmd_grant + assign $0\sdram_choose_req_grant[1:0] \sdram_choose_req_grant + assign $0\sdram_tccdcon_ready[0:0] \sdram_tccdcon_ready + assign $0\sdram_tccdcon_count[0:0] \sdram_tccdcon_count + assign $0\sdram_twtrcon_ready[0:0] \sdram_twtrcon_ready + assign $0\sdram_twtrcon_count[2:0] \sdram_twtrcon_count + assign $0\sdram_time0[4:0] \sdram_time0 + assign $0\sdram_time1[3:0] \sdram_time1 + assign $0\socbushandler_counter[0:0] \socbushandler_counter + assign $0\socbushandler_dat_r[63:0] \socbushandler_dat_r + assign $0\converter_counter[0:0] \converter_counter + assign $0\converter_dat_r[31:0] \converter_dat_r + assign $0\cmd_consumed[0:0] \cmd_consumed + assign $0\wdata_consumed[0:0] \wdata_consumed + assign $0\uart_phy_storage[31:0] \uart_phy_storage assign { } { } assign { } { } + assign $0\uart_phy_uart_clk_txen[0:0] \uart_phy_uart_clk_txen + assign $0\uart_phy_phase_accumulator_tx[31:0] \uart_phy_phase_accumulator_tx + assign $0\uart_phy_tx_reg[7:0] \uart_phy_tx_reg + assign $0\uart_phy_tx_bitcount[3:0] \uart_phy_tx_bitcount + assign $0\uart_phy_tx_busy[0:0] \uart_phy_tx_busy assign { } { } + assign $0\uart_phy_source_payload_data[7:0] \uart_phy_source_payload_data + assign $0\uart_phy_uart_clk_rxen[0:0] \uart_phy_uart_clk_rxen + assign $0\uart_phy_phase_accumulator_rx[31:0] \uart_phy_phase_accumulator_rx assign { } { } + assign $0\uart_phy_rx_reg[7:0] \uart_phy_rx_reg + assign $0\uart_phy_rx_bitcount[3:0] \uart_phy_rx_bitcount + assign $0\uart_phy_rx_busy[0:0] \uart_phy_rx_busy + assign $0\tx_pending[0:0] \tx_pending assign { } { } + assign $0\rx_pending[0:0] \rx_pending assign { } { } + assign $0\eventmanager_storage[1:0] \eventmanager_storage assign { } { } - assign $0\main_dummy[23:0] [0] $or$ls180.v:7512$2435_Y - assign $0\main_dummy[23:0] [1] $or$ls180.v:7513$2436_Y - assign $0\main_dummy[23:0] [2] $or$ls180.v:7514$2437_Y - assign $0\main_dummy[23:0] [3] $or$ls180.v:7515$2438_Y - assign $0\main_dummy[23:0] [4] $or$ls180.v:7516$2439_Y - assign $0\main_dummy[23:0] [5] $or$ls180.v:7517$2440_Y - assign $0\main_dummy[23:0] [6] $or$ls180.v:7518$2441_Y - assign $0\main_dummy[23:0] [7] $or$ls180.v:7519$2442_Y - assign $0\main_dummy[23:0] [8] $or$ls180.v:7520$2443_Y - assign $0\main_dummy[23:0] [9] $or$ls180.v:7521$2444_Y - assign $0\main_dummy[23:0] [10] $or$ls180.v:7522$2445_Y - assign $0\main_dummy[23:0] [11] $or$ls180.v:7523$2446_Y - assign $0\main_dummy[23:0] [12] $or$ls180.v:7524$2447_Y - assign $0\main_dummy[23:0] [13] $or$ls180.v:7525$2448_Y - assign $0\main_dummy[23:0] [14] $or$ls180.v:7526$2449_Y - assign $0\main_dummy[23:0] [15] $or$ls180.v:7527$2450_Y - assign $0\main_dummy[23:0] [16] $or$ls180.v:7528$2451_Y - assign $0\main_dummy[23:0] [17] $or$ls180.v:7529$2452_Y - assign $0\main_dummy[23:0] [18] $or$ls180.v:7530$2453_Y - assign $0\main_dummy[23:0] [19] $or$ls180.v:7531$2454_Y - assign $0\main_dummy[23:0] [20] $or$ls180.v:7532$2455_Y - assign $0\main_dummy[23:0] [21] $or$ls180.v:7533$2456_Y - assign $0\main_dummy[23:0] [22] $or$ls180.v:7534$2457_Y - assign $0\main_dummy[23:0] [23] $or$ls180.v:7535$2458_Y - assign $0\builder_converter0_state[0:0] \builder_converter0_next_state - assign $0\builder_converter1_state[0:0] \builder_converter1_next_state - assign $0\builder_converter2_state[0:0] \builder_converter2_next_state - assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 - assign $0\main_libresocsim_zero_old_trigger[0:0] \main_libresocsim_zero_trigger - assign $0\main_ram_bus_ram_bus_ack[0:0] 1'0 - assign $0\main_rddata_en[2:0] { \main_rddata_en [1:0] \main_dfi_p0_rddata_en } - assign $0\main_dfi_p0_rddata_valid[0:0] \main_rddata_en [2] - assign $0\main_sdram_postponer_req_o[0:0] 1'0 - assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 - assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 - assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_cmd_payload_ras[0:0] 1'0 - assign $0\main_sdram_cmd_payload_we[0:0] 1'0 - assign $0\main_sdram_sequencer_done1[0:0] 1'0 - assign $0\builder_refresher_state[1:0] \builder_refresher_next_state - assign $0\builder_bankmachine0_state[2:0] \builder_bankmachine0_next_state - assign $0\builder_bankmachine1_state[2:0] \builder_bankmachine1_next_state - assign $0\builder_bankmachine2_state[2:0] \builder_bankmachine2_next_state - assign $0\builder_bankmachine3_state[2:0] \builder_bankmachine3_next_state - assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'0 - assign $0\main_sdram_dfi_p0_bank[1:0] \builder_sync_rhs_array_muxed0 - assign $0\main_sdram_dfi_p0_address[12:0] \builder_sync_rhs_array_muxed1 - assign $0\main_sdram_dfi_p0_cas_n[0:0] $not$ls180.v:7981$2558_Y - assign $0\main_sdram_dfi_p0_ras_n[0:0] $not$ls180.v:7982$2559_Y - assign $0\main_sdram_dfi_p0_we_n[0:0] $not$ls180.v:7983$2560_Y - assign $0\main_sdram_dfi_p0_rddata_en[0:0] \builder_sync_rhs_array_muxed5 - assign $0\main_sdram_dfi_p0_wrdata_en[0:0] \builder_sync_rhs_array_muxed6 - assign $0\builder_multiplexer_state[2:0] \builder_multiplexer_next_state - assign $0\builder_new_master_wdata_ready[0:0] $or$ls180.v:8017$2578_Y - assign $0\builder_new_master_rdata_valid0[0:0] $or$ls180.v:8018$2590_Y - assign $0\builder_new_master_rdata_valid1[0:0] \builder_new_master_rdata_valid0 - assign $0\builder_new_master_rdata_valid2[0:0] \builder_new_master_rdata_valid1 - assign $0\builder_new_master_rdata_valid3[0:0] \builder_new_master_rdata_valid2 - assign $0\builder_converter_state[0:0] \builder_converter_next_state - assign $0\main_uart_phy_sink_ready[0:0] 1'0 - assign $0\main_uart_phy_source_valid[0:0] 1'0 - assign $0\main_uart_phy_rx_r[0:0] \main_uart_phy_rx - assign $0\main_uart_tx_old_trigger[0:0] \main_uart_tx_trigger - assign $0\main_uart_rx_old_trigger[0:0] \main_uart_rx_trigger - assign $0\main_spimaster30_clk_divider[15:0] $add$ls180.v:8176$2636_Y - assign $0\spisdcard_cs_n[0:0] $or$ls180.v:8185$2639_Y - assign $0\builder_spimaster0_state[1:0] \builder_spimaster0_next_state - assign $0\main_spisdcard_clk_divider1[15:0] $add$ls180.v:8211$2641_Y - assign $0\spimaster_cs_n[0:0] $or$ls180.v:8220$2644_Y - assign $0\builder_spimaster1_state[1:0] \builder_spimaster1_next_state - assign $0\main_sdphy_clocker_clk_d[0:0] \main_sdphy_clocker_clk1 - assign $0\main_sdphy_clocker_clk0[0:0] \main_sdphy_clocker_clk1 - assign $0\builder_sdphy_sdphyinit_state[0:0] \builder_sdphy_sdphyinit_next_state - assign $0\builder_sdphy_sdphycmdw_state[1:0] \builder_sdphy_sdphycmdw_next_state - assign $0\builder_sdphy_sdphycmdr_state[2:0] \builder_sdphy_sdphycmdr_next_state - assign $0\builder_sdphy_sdphycrcr_state[0:0] \builder_sdphy_sdphycrcr_next_state - assign $0\builder_sdphy_fsm_state[2:0] \builder_sdphy_fsm_next_state - assign $0\builder_sdphy_sdphydatar_state[2:0] \builder_sdphy_sdphydatar_next_state - assign $0\builder_sdcore_crcupstreaminserter_state[0:0] \builder_sdcore_crcupstreaminserter_next_state - assign $0\builder_sdcore_fsm_state[2:0] \builder_sdcore_fsm_next_state - assign $0\builder_sdblock2memdma_state[1:0] \builder_sdblock2memdma_next_state - assign $0\builder_sdmem2blockdma_fsm_state[0:0] \builder_sdmem2blockdma_fsm_next_state - assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] \builder_sdmem2blockdma_resetinserter_next_state - assign $0\builder_state[1:0] \builder_next_state - assign $0\builder_slave_sel_r[5:0] \builder_slave_sel - assign $0\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_libresocsim_reset_re[0:0] \builder_csrbank0_reset0_re - assign $0\main_libresocsim_scratch_re[0:0] \builder_csrbank0_scratch0_re - assign $0\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_gpiotristateasic1_oe_re[0:0] \builder_csrbank1_oe0_re - assign $0\main_gpiotristateasic1_out_re[0:0] \builder_csrbank1_out0_re - assign $0\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_i2c_re[0:0] \builder_csrbank2_w0_re - assign $0\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_pwm0_enable_re[0:0] \builder_csrbank3_enable0_re - assign $0\main_pwm0_width_re[0:0] \builder_csrbank3_width0_re - assign $0\main_pwm0_period_re[0:0] \builder_csrbank3_period0_re - assign $0\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_pwm1_enable_re[0:0] \builder_csrbank4_enable0_re - assign $0\main_pwm1_width_re[0:0] \builder_csrbank4_width0_re - assign $0\main_pwm1_period_re[0:0] \builder_csrbank4_period0_re - assign $0\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] \builder_csrbank5_dma_base0_re - assign $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] \builder_csrbank5_dma_length0_re - assign $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] \builder_csrbank5_dma_enable0_re - assign $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] \builder_csrbank5_dma_loop0_re - assign $0\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_sdcore_cmd_argument_re[0:0] \builder_csrbank6_cmd_argument0_re - assign $0\main_sdcore_cmd_command_re[0:0] \builder_csrbank6_cmd_command0_re - assign $0\main_sdcore_block_length_re[0:0] \builder_csrbank6_block_length0_re - assign $0\main_sdcore_block_count_re[0:0] \builder_csrbank6_block_count0_re - assign $0\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_sdmem2block_dma_base_re[0:0] \builder_csrbank7_dma_base0_re - assign $0\main_sdmem2block_dma_length_re[0:0] \builder_csrbank7_dma_length0_re - assign $0\main_sdmem2block_dma_enable_re[0:0] \builder_csrbank7_dma_enable0_re - assign $0\main_sdmem2block_dma_loop_re[0:0] \builder_csrbank7_dma_loop0_re - assign $0\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_sdphy_clocker_re[0:0] \builder_csrbank8_clocker_divider0_re - assign $0\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_sdram_re[0:0] \builder_csrbank9_dfii_control0_re - assign $0\main_sdram_command_re[0:0] \builder_csrbank9_dfii_pi0_command0_re - assign $0\main_sdram_address_re[0:0] \builder_csrbank9_dfii_pi0_address0_re - assign $0\main_sdram_baddress_re[0:0] \builder_csrbank9_dfii_pi0_baddress0_re - assign $0\main_sdram_wrdata_re[0:0] \builder_csrbank9_dfii_pi0_wrdata0_re - assign $0\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_spimaster12_re[0:0] \builder_csrbank10_control0_re - assign $0\main_spimaster17_re[0:0] \builder_csrbank10_mosi0_re - assign $0\main_spimaster22_re[0:0] \builder_csrbank10_cs0_re - assign $0\main_spimaster24_re[0:0] \builder_csrbank10_loopback0_re - assign $0\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_spisdcard_control_re[0:0] \builder_csrbank11_control0_re - assign $0\main_spisdcard_mosi_re[0:0] \builder_csrbank11_mosi0_re - assign $0\main_spisdcard_cs_re[0:0] \builder_csrbank11_cs0_re - assign $0\main_spisdcard_loopback_re[0:0] \builder_csrbank11_loopback0_re - assign $0\main_spimaster1_re[0:0] \builder_csrbank11_clk_divider0_re - assign $0\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_libresocsim_load_re[0:0] \builder_csrbank12_load0_re - assign $0\main_libresocsim_reload_re[0:0] \builder_csrbank12_reload0_re - assign $0\main_libresocsim_en_re[0:0] \builder_csrbank12_en0_re - assign $0\main_libresocsim_update_value_re[0:0] \builder_csrbank12_update_value0_re - assign $0\main_libresocsim_eventmanager_re[0:0] \builder_csrbank12_ev_enable0_re - assign $0\builder_interface13_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_uart_eventmanager_re[0:0] \builder_csrbank13_ev_enable0_re - assign $0\builder_interface14_bank_bus_dat_r[7:0] 8'00000000 - assign $0\main_uart_phy_re[0:0] \builder_csrbank14_tuning_word0_re - assign $0\builder_multiregimpl0_regs0[0:0] \uart_rx - assign $0\builder_multiregimpl0_regs1[0:0] \builder_multiregimpl0_regs0 - assign $0\builder_multiregimpl1_regs0[0:0] \main_gpiotristateasic0_pads_i [0] - assign $0\builder_multiregimpl1_regs1[0:0] \builder_multiregimpl1_regs0 - assign $0\builder_multiregimpl2_regs0[0:0] \main_gpiotristateasic0_pads_i [1] - assign $0\builder_multiregimpl2_regs1[0:0] \builder_multiregimpl2_regs0 - assign $0\builder_multiregimpl3_regs0[0:0] \main_gpiotristateasic0_pads_i [2] - assign $0\builder_multiregimpl3_regs1[0:0] \builder_multiregimpl3_regs0 - assign $0\builder_multiregimpl4_regs0[0:0] \main_gpiotristateasic0_pads_i [3] - assign $0\builder_multiregimpl4_regs1[0:0] \builder_multiregimpl4_regs0 - assign $0\builder_multiregimpl5_regs0[0:0] \main_gpiotristateasic0_pads_i [4] - assign $0\builder_multiregimpl5_regs1[0:0] \builder_multiregimpl5_regs0 - assign $0\builder_multiregimpl6_regs0[0:0] \main_gpiotristateasic0_pads_i [5] - assign $0\builder_multiregimpl6_regs1[0:0] \builder_multiregimpl6_regs0 - assign $0\builder_multiregimpl7_regs0[0:0] \main_gpiotristateasic0_pads_i [6] - assign $0\builder_multiregimpl7_regs1[0:0] \builder_multiregimpl7_regs0 - assign $0\builder_multiregimpl8_regs0[0:0] \main_gpiotristateasic0_pads_i [7] - assign $0\builder_multiregimpl8_regs1[0:0] \builder_multiregimpl8_regs0 - assign $0\builder_multiregimpl9_regs0[0:0] \main_gpiotristateasic1_pads_i [8] - assign $0\builder_multiregimpl9_regs1[0:0] \builder_multiregimpl9_regs0 - assign $0\builder_multiregimpl10_regs0[0:0] \main_gpiotristateasic1_pads_i [9] - assign $0\builder_multiregimpl10_regs1[0:0] \builder_multiregimpl10_regs0 - assign $0\builder_multiregimpl11_regs0[0:0] \main_gpiotristateasic1_pads_i [10] - assign $0\builder_multiregimpl11_regs1[0:0] \builder_multiregimpl11_regs0 - assign $0\builder_multiregimpl12_regs0[0:0] \main_gpiotristateasic1_pads_i [11] - assign $0\builder_multiregimpl12_regs1[0:0] \builder_multiregimpl12_regs0 - assign $0\builder_multiregimpl13_regs0[0:0] \main_gpiotristateasic1_pads_i [12] - assign $0\builder_multiregimpl13_regs1[0:0] \builder_multiregimpl13_regs0 - assign $0\builder_multiregimpl14_regs0[0:0] \main_gpiotristateasic1_pads_i [13] - assign $0\builder_multiregimpl14_regs1[0:0] \builder_multiregimpl14_regs0 - assign $0\builder_multiregimpl15_regs0[0:0] \main_gpiotristateasic1_pads_i [14] - assign $0\builder_multiregimpl15_regs1[0:0] \builder_multiregimpl15_regs0 - assign $0\builder_multiregimpl16_regs0[0:0] \main_gpiotristateasic1_pads_i [15] - assign $0\builder_multiregimpl16_regs1[0:0] \builder_multiregimpl16_regs0 - attribute \src "ls180.v:7536.2-7538.5" - switch $or$ls180.v:7536$2459_Y - attribute \src "ls180.v:7536.6-7536.69" - case 1'1 - assign $0\main_converter0_dat_r[63:0] \main_interface0_converted_interface_dat_r - case - end - attribute \src "ls180.v:7540.2-7542.5" - switch \main_converter0_counter_converter0_next_value_ce - attribute \src "ls180.v:7540.6-7540.54" - case 1'1 - assign $0\main_converter0_counter[0:0] \main_converter0_counter_converter0_next_value - case - end - attribute \src "ls180.v:7543.2-7546.5" - switch \main_converter0_reset - attribute \src "ls180.v:7543.6-7543.27" - case 1'1 - assign $0\main_converter0_counter[0:0] 1'0 - assign $0\builder_converter0_state[0:0] 1'0 - case - end - attribute \src "ls180.v:7547.2-7549.5" - switch $or$ls180.v:7547$2460_Y - attribute \src "ls180.v:7547.6-7547.69" - case 1'1 - assign $0\main_converter1_dat_r[63:0] \main_interface1_converted_interface_dat_r - case - end - attribute \src "ls180.v:7551.2-7553.5" - switch \main_converter1_counter_converter1_next_value_ce - attribute \src "ls180.v:7551.6-7551.54" - case 1'1 - assign $0\main_converter1_counter[0:0] \main_converter1_counter_converter1_next_value - case - end - attribute \src "ls180.v:7554.2-7557.5" - switch \main_converter1_reset - attribute \src "ls180.v:7554.6-7554.27" - case 1'1 - assign $0\main_converter1_counter[0:0] 1'0 - assign $0\builder_converter1_state[0:0] 1'0 - case - end - attribute \src "ls180.v:7558.2-7560.5" - switch $or$ls180.v:7558$2461_Y - attribute \src "ls180.v:7558.6-7558.51" - case 1'1 - assign $0\main_socbushandler_dat_r[63:0] \main_socbushandler_converted_interface_dat_r - case - end - attribute \src "ls180.v:7562.2-7564.5" - switch \main_socbushandler_counter_converter2_next_value_ce - attribute \src "ls180.v:7562.6-7562.57" - case 1'1 - assign $0\main_socbushandler_counter[0:0] \main_socbushandler_counter_converter2_next_value - case - end - attribute \src "ls180.v:7565.2-7568.5" - switch \main_socbushandler_reset - attribute \src "ls180.v:7565.6-7565.30" + assign $0\tx_fifo_readable[0:0] \tx_fifo_readable + assign $0\tx_fifo_level0[4:0] \tx_fifo_level0 + assign $0\tx_fifo_produce[3:0] \tx_fifo_produce + assign $0\tx_fifo_consume[3:0] \tx_fifo_consume + assign $0\rx_fifo_readable[0:0] \rx_fifo_readable + assign $0\rx_fifo_level0[4:0] \rx_fifo_level0 + assign $0\rx_fifo_produce[3:0] \rx_fifo_produce + assign $0\rx_fifo_consume[3:0] \rx_fifo_consume + assign $0\gpio0_oe_storage[7:0] \gpio0_oe_storage + assign { } { } + assign $0\gpio0_out_storage[7:0] \gpio0_out_storage + assign { } { } + assign $0\gpio1_oe_storage[7:0] \gpio1_oe_storage + assign { } { } + assign $0\gpio1_out_storage[7:0] \gpio1_out_storage + assign { } { } + assign { } { } + assign $0\i2c_storage[2:0] \i2c_storage + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\libresocsim_libresocsim_adr[13:0] \libresocsim_libresocsim_adr + assign $0\libresocsim_libresocsim_we[0:0] \libresocsim_libresocsim_we + assign $0\libresocsim_libresocsim_dat_w[7:0] \libresocsim_libresocsim_dat_w + assign $0\libresocsim_grant[1:0] \libresocsim_grant + assign { } { } + assign $0\libresocsim_count[19:0] \libresocsim_count + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\dummy[29:0] [0] $or$ls180.v:4288$1247_Y + assign $0\dummy[29:0] [1] $or$ls180.v:4289$1248_Y + assign $0\dummy[29:0] [2] $or$ls180.v:4290$1249_Y + assign $0\dummy[29:0] [3] $or$ls180.v:4291$1250_Y + assign $0\dummy[29:0] [4] $or$ls180.v:4292$1251_Y + assign $0\dummy[29:0] [5] $or$ls180.v:4293$1252_Y + assign $0\dummy[29:0] [6] $or$ls180.v:4294$1253_Y + assign $0\dummy[29:0] [7] $or$ls180.v:4295$1254_Y + assign $0\dummy[29:0] [8] $or$ls180.v:4296$1255_Y + assign $0\dummy[29:0] [9] $or$ls180.v:4297$1256_Y + assign $0\dummy[29:0] [10] $or$ls180.v:4298$1257_Y + assign $0\dummy[29:0] [11] $or$ls180.v:4299$1258_Y + assign $0\dummy[29:0] [12] $or$ls180.v:4300$1259_Y + assign $0\dummy[29:0] [13] $or$ls180.v:4301$1260_Y + assign $0\dummy[29:0] [14] $or$ls180.v:4302$1261_Y + assign $0\dummy[29:0] [15] $or$ls180.v:4303$1262_Y + assign $0\dummy[29:0] [16] $or$ls180.v:4304$1263_Y + assign $0\dummy[29:0] [17] $or$ls180.v:4305$1264_Y + assign $0\dummy[29:0] [18] $or$ls180.v:4306$1265_Y + assign $0\dummy[29:0] [19] $or$ls180.v:4307$1266_Y + assign $0\dummy[29:0] [20] $or$ls180.v:4308$1267_Y + assign $0\dummy[29:0] [21] $or$ls180.v:4309$1268_Y + assign $0\dummy[29:0] [22] $or$ls180.v:4310$1269_Y + assign $0\dummy[29:0] [23] $or$ls180.v:4311$1270_Y + assign $0\dummy[29:0] [24] $or$ls180.v:4312$1271_Y + assign $0\dummy[29:0] [25] $or$ls180.v:4313$1272_Y + assign $0\dummy[29:0] [26] $or$ls180.v:4314$1273_Y + assign $0\dummy[29:0] [27] $or$ls180.v:4315$1274_Y + assign $0\dummy[29:0] [28] $or$ls180.v:4316$1275_Y + assign $0\dummy[29:0] [29] $or$ls180.v:4317$1276_Y + assign $0\subfragments_converter0_state[0:0] \subfragments_converter0_next_state + assign $0\subfragments_converter1_state[0:0] \subfragments_converter1_next_state + assign $0\subfragments_converter2_state[0:0] \subfragments_converter2_next_state + assign $0\libresocsim_ram_bus_ack[0:0] 1'0 + assign $0\libresocsim_zero_old_trigger[0:0] \libresocsim_zero_trigger + assign $0\ram_bus_ram_bus_ack[0:0] 1'0 + assign $0\rddata_en[2:0] { \rddata_en [1:0] \dfi_p0_rddata_en } + assign $0\dfi_p0_rddata_valid[0:0] \rddata_en [2] + assign $0\sdram_postponer_req_o[0:0] 1'0 + assign $0\sdram_cmd_payload_a[12:0] 13'0000000000000 + assign $0\sdram_cmd_payload_ba[1:0] 2'00 + assign $0\sdram_cmd_payload_cas[0:0] 1'0 + assign $0\sdram_cmd_payload_ras[0:0] 1'0 + assign $0\sdram_cmd_payload_we[0:0] 1'0 + assign $0\sdram_sequencer_done1[0:0] 1'0 + assign $0\subfragments_refresher_state[1:0] \subfragments_refresher_next_state + assign $0\subfragments_bankmachine0_state[2:0] \subfragments_bankmachine0_next_state + assign $0\subfragments_bankmachine1_state[2:0] \subfragments_bankmachine1_next_state + assign $0\subfragments_bankmachine2_state[2:0] \subfragments_bankmachine2_next_state + assign $0\subfragments_bankmachine3_state[2:0] \subfragments_bankmachine3_next_state + assign $0\sdram_dfi_p0_cs_n[0:0] 1'0 + assign $0\sdram_dfi_p0_bank[1:0] \array_muxed0 + assign $0\sdram_dfi_p0_address[12:0] \array_muxed1 + assign $0\sdram_dfi_p0_cas_n[0:0] $not$ls180.v:4763$1376_Y + assign $0\sdram_dfi_p0_ras_n[0:0] $not$ls180.v:4764$1377_Y + assign $0\sdram_dfi_p0_we_n[0:0] $not$ls180.v:4765$1378_Y + assign $0\sdram_dfi_p0_rddata_en[0:0] \array_muxed5 + assign $0\sdram_dfi_p0_wrdata_en[0:0] \array_muxed6 + assign $0\subfragments_multiplexer_state[2:0] \subfragments_multiplexer_next_state + assign $0\subfragments_new_master_wdata_ready[0:0] $or$ls180.v:4799$1396_Y + assign $0\subfragments_new_master_rdata_valid0[0:0] $or$ls180.v:4800$1408_Y + assign $0\subfragments_new_master_rdata_valid1[0:0] \subfragments_new_master_rdata_valid0 + assign $0\subfragments_new_master_rdata_valid2[0:0] \subfragments_new_master_rdata_valid1 + assign $0\subfragments_new_master_rdata_valid3[0:0] \subfragments_new_master_rdata_valid2 + assign $0\subfragments_state[0:0] \subfragments_next_state + assign $0\uart_phy_sink_ready[0:0] 1'0 + assign $0\uart_phy_source_valid[0:0] 1'0 + assign $0\uart_phy_rx_r[0:0] \uart_phy_rx + assign $0\tx_old_trigger[0:0] \tx_trigger + assign $0\rx_old_trigger[0:0] \rx_trigger + assign $0\libresocsim_state[1:0] \libresocsim_next_state + assign $0\libresocsim_slave_sel_r[5:0] \libresocsim_slave_sel + assign $0\libresocsim_interface0_bank_bus_dat_r[7:0] 8'00000000 + assign $0\libresocsim_reset_re[0:0] \libresocsim_csrbank0_reset0_re + assign $0\libresocsim_scratch_re[0:0] \libresocsim_csrbank0_scratch0_re + assign $0\libresocsim_interface1_bank_bus_dat_r[7:0] 8'00000000 + assign $0\gpio0_oe_re[0:0] \libresocsim_csrbank1_oe0_re + assign $0\gpio0_out_re[0:0] \libresocsim_csrbank1_out0_re + assign $0\libresocsim_interface2_bank_bus_dat_r[7:0] 8'00000000 + assign $0\gpio1_oe_re[0:0] \libresocsim_csrbank2_oe0_re + assign $0\gpio1_out_re[0:0] \libresocsim_csrbank2_out0_re + assign $0\libresocsim_interface3_bank_bus_dat_r[7:0] 8'00000000 + assign $0\i2c_re[0:0] \libresocsim_csrbank3_w0_re + assign $0\libresocsim_interface4_bank_bus_dat_r[7:0] 8'00000000 + assign $0\sdram_re[0:0] \libresocsim_csrbank4_dfii_control0_re + assign $0\sdram_command_re[0:0] \libresocsim_csrbank4_dfii_pi0_command0_re + assign $0\sdram_address_re[0:0] \libresocsim_csrbank4_dfii_pi0_address0_re + assign $0\sdram_baddress_re[0:0] \libresocsim_csrbank4_dfii_pi0_baddress0_re + assign $0\sdram_wrdata_re[0:0] \libresocsim_csrbank4_dfii_pi0_wrdata0_re + assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] 8'00000000 + assign $0\libresocsim_load_re[0:0] \libresocsim_csrbank5_load0_re + assign $0\libresocsim_reload_re[0:0] \libresocsim_csrbank5_reload0_re + assign $0\libresocsim_en_re[0:0] \libresocsim_csrbank5_en0_re + assign $0\libresocsim_update_value_re[0:0] \libresocsim_csrbank5_update_value0_re + assign $0\libresocsim_eventmanager_re[0:0] \libresocsim_csrbank5_ev_enable0_re + assign $0\libresocsim_interface6_bank_bus_dat_r[7:0] 8'00000000 + assign $0\eventmanager_re[0:0] \libresocsim_csrbank6_ev_enable0_re + assign $0\libresocsim_interface7_bank_bus_dat_r[7:0] 8'00000000 + assign $0\uart_phy_re[0:0] \libresocsim_csrbank7_tuning_word0_re + assign $0\regs0[0:0] \libresocsim_libresoc_constraintmanager_obj_uart_rx + assign $0\regs1[0:0] \regs0 + attribute \src "ls180.v:4318.2-4320.5" + switch $or$ls180.v:4318$1277_Y + attribute \src "ls180.v:4318.6-4318.59" + case 1'1 + assign $0\converter0_dat_r[63:0] \interface0_converted_interface_dat_r + case + end + attribute \src "ls180.v:4322.2-4324.5" + switch \converter0_counter_subfragments_converter0_next_value_ce + attribute \src "ls180.v:4322.6-4322.62" + case 1'1 + assign $0\converter0_counter[0:0] \converter0_counter_subfragments_converter0_next_value + case + end + attribute \src "ls180.v:4325.2-4328.5" + switch \converter0_reset + attribute \src "ls180.v:4325.6-4325.22" + case 1'1 + assign $0\converter0_counter[0:0] 1'0 + assign $0\subfragments_converter0_state[0:0] 1'0 + case + end + attribute \src "ls180.v:4329.2-4331.5" + switch $or$ls180.v:4329$1278_Y + attribute \src "ls180.v:4329.6-4329.59" + case 1'1 + assign $0\converter1_dat_r[63:0] \interface1_converted_interface_dat_r + case + end + attribute \src "ls180.v:4333.2-4335.5" + switch \converter1_counter_subfragments_converter1_next_value_ce + attribute \src "ls180.v:4333.6-4333.62" + case 1'1 + assign $0\converter1_counter[0:0] \converter1_counter_subfragments_converter1_next_value + case + end + attribute \src "ls180.v:4336.2-4339.5" + switch \converter1_reset + attribute \src "ls180.v:4336.6-4336.22" + case 1'1 + assign $0\converter1_counter[0:0] 1'0 + assign $0\subfragments_converter1_state[0:0] 1'0 + case + end + attribute \src "ls180.v:4340.2-4342.5" + switch $or$ls180.v:4340$1279_Y + attribute \src "ls180.v:4340.6-4340.41" + case 1'1 + assign $0\socbushandler_dat_r[63:0] \socbushandler_converted_interface_dat_r + case + end + attribute \src "ls180.v:4344.2-4346.5" + switch \socbushandler_counter_subfragments_converter2_next_value_ce + attribute \src "ls180.v:4344.6-4344.65" + case 1'1 + assign $0\socbushandler_counter[0:0] \socbushandler_counter_subfragments_converter2_next_value + case + end + attribute \src "ls180.v:4347.2-4350.5" + switch \socbushandler_reset + attribute \src "ls180.v:4347.6-4347.25" case 1'1 - assign $0\main_socbushandler_counter[0:0] 1'0 - assign $0\builder_converter2_state[0:0] 1'0 + assign $0\socbushandler_counter[0:0] 1'0 + assign $0\subfragments_converter2_state[0:0] 1'0 case end - attribute \src "ls180.v:7569.2-7573.5" - switch $ne$ls180.v:7569$2462_Y - attribute \src "ls180.v:7569.6-7569.53" + attribute \src "ls180.v:4351.2-4355.5" + switch $ne$ls180.v:4351$1280_Y + attribute \src "ls180.v:4351.6-4351.48" case 1'1 - attribute \src "ls180.v:7570.3-7572.6" - switch \main_libresocsim_bus_error - attribute \src "ls180.v:7570.7-7570.33" + attribute \src "ls180.v:4352.3-4354.6" + switch \libresocsim_bus_error + attribute \src "ls180.v:4352.7-4352.28" case 1'1 - assign $0\main_libresocsim_bus_errors[31:0] $add$ls180.v:7571$2463_Y + assign $0\libresocsim_bus_errors[31:0] $add$ls180.v:4353$1281_Y case end case end - attribute \src "ls180.v:7575.2-7577.5" - switch $and$ls180.v:7575$2466_Y - attribute \src "ls180.v:7575.6-7575.103" + attribute \src "ls180.v:4357.2-4359.5" + switch $and$ls180.v:4357$1284_Y + attribute \src "ls180.v:4357.6-4357.88" case 1'1 - assign $0\main_libresocsim_ram_bus_ack[0:0] 1'1 + assign $0\libresocsim_ram_bus_ack[0:0] 1'1 case end - attribute \src "ls180.v:7578.2-7586.5" - switch \main_libresocsim_en_storage - attribute \src "ls180.v:7578.6-7578.33" + attribute \src "ls180.v:4360.2-4368.5" + switch \libresocsim_en_storage + attribute \src "ls180.v:4360.6-4360.28" case 1'1 - attribute \src "ls180.v:7579.3-7583.6" - switch $eq$ls180.v:7579$2467_Y - attribute \src "ls180.v:7579.7-7579.39" + attribute \src "ls180.v:4361.3-4365.6" + switch $eq$ls180.v:4361$1285_Y + attribute \src "ls180.v:4361.7-4361.34" case 1'1 - assign $0\main_libresocsim_value[31:0] \main_libresocsim_reload_storage - attribute \src "ls180.v:7581.7-7581.11" + assign $0\libresocsim_value[31:0] \libresocsim_reload_storage + attribute \src "ls180.v:4363.7-4363.11" case - assign $0\main_libresocsim_value[31:0] $sub$ls180.v:7582$2468_Y + assign $0\libresocsim_value[31:0] $sub$ls180.v:4364$1286_Y end - attribute \src "ls180.v:7584.6-7584.10" + attribute \src "ls180.v:4366.6-4366.10" case - assign $0\main_libresocsim_value[31:0] \main_libresocsim_load_storage + assign $0\libresocsim_value[31:0] \libresocsim_load_storage end - attribute \src "ls180.v:7587.2-7589.5" - switch \main_libresocsim_update_value_re - attribute \src "ls180.v:7587.6-7587.38" + attribute \src "ls180.v:4369.2-4371.5" + switch \libresocsim_update_value_re + attribute \src "ls180.v:4369.6-4369.33" case 1'1 - assign $0\main_libresocsim_value_status[31:0] \main_libresocsim_value + assign $0\libresocsim_value_status[31:0] \libresocsim_value case end - attribute \src "ls180.v:7590.2-7592.5" - switch \main_libresocsim_zero_clear - attribute \src "ls180.v:7590.6-7590.33" + attribute \src "ls180.v:4372.2-4374.5" + switch \libresocsim_zero_clear + attribute \src "ls180.v:4372.6-4372.28" case 1'1 - assign $0\main_libresocsim_zero_pending[0:0] 1'0 + assign $0\libresocsim_zero_pending[0:0] 1'0 case end - attribute \src "ls180.v:7594.2-7596.5" - switch $and$ls180.v:7594$2470_Y - attribute \src "ls180.v:7594.6-7594.76" + attribute \src "ls180.v:4376.2-4378.5" + switch $and$ls180.v:4376$1288_Y + attribute \src "ls180.v:4376.6-4376.66" case 1'1 - assign $0\main_libresocsim_zero_pending[0:0] 1'1 + assign $0\libresocsim_zero_pending[0:0] 1'1 case end - attribute \src "ls180.v:7598.2-7600.5" - switch $and$ls180.v:7598$2473_Y - attribute \src "ls180.v:7598.6-7598.91" + attribute \src "ls180.v:4380.2-4382.5" + switch $and$ls180.v:4380$1291_Y + attribute \src "ls180.v:4380.6-4380.76" case 1'1 - assign $0\main_ram_bus_ram_bus_ack[0:0] 1'1 + assign $0\ram_bus_ram_bus_ack[0:0] 1'1 case end - attribute \src "ls180.v:7603.2-7605.5" - switch \main_sdram_inti_p0_rddata_valid - attribute \src "ls180.v:7603.6-7603.37" + attribute \src "ls180.v:4385.2-4387.5" + switch \sdram_inti_p0_rddata_valid + attribute \src "ls180.v:4385.6-4385.32" case 1'1 - assign $0\main_sdram_status[15:0] \main_sdram_inti_p0_rddata + assign $0\sdram_status[15:0] \sdram_inti_p0_rddata case end - attribute \src "ls180.v:7606.2-7610.5" - switch $and$ls180.v:7606$2475_Y - attribute \src "ls180.v:7606.6-7606.57" + attribute \src "ls180.v:4388.2-4392.5" + switch $and$ls180.v:4388$1293_Y + attribute \src "ls180.v:4388.6-4388.47" case 1'1 - assign $0\main_sdram_timer_count1[9:0] $sub$ls180.v:7607$2476_Y - attribute \src "ls180.v:7608.6-7608.10" + assign $0\sdram_timer_count1[9:0] $sub$ls180.v:4389$1294_Y + attribute \src "ls180.v:4390.6-4390.10" case - assign $0\main_sdram_timer_count1[9:0] 10'1100001101 + assign $0\sdram_timer_count1[9:0] 10'1100001101 end - attribute \src "ls180.v:7612.2-7618.5" - switch \main_sdram_postponer_req_i - attribute \src "ls180.v:7612.6-7612.32" + attribute \src "ls180.v:4394.2-4400.5" + switch \sdram_postponer_req_i + attribute \src "ls180.v:4394.6-4394.27" case 1'1 - assign $0\main_sdram_postponer_count[0:0] $sub$ls180.v:7613$2477_Y - attribute \src "ls180.v:7614.3-7617.6" - switch $eq$ls180.v:7614$2478_Y - attribute \src "ls180.v:7614.7-7614.43" + assign $0\sdram_postponer_count[0:0] $sub$ls180.v:4395$1295_Y + attribute \src "ls180.v:4396.3-4399.6" + switch $eq$ls180.v:4396$1296_Y + attribute \src "ls180.v:4396.7-4396.38" case 1'1 - assign $0\main_sdram_postponer_count[0:0] 1'0 - assign $0\main_sdram_postponer_req_o[0:0] 1'1 + assign $0\sdram_postponer_count[0:0] 1'0 + assign $0\sdram_postponer_req_o[0:0] 1'1 case end case end - attribute \src "ls180.v:7619.2-7627.5" - switch \main_sdram_sequencer_start0 - attribute \src "ls180.v:7619.6-7619.33" + attribute \src "ls180.v:4401.2-4409.5" + switch \sdram_sequencer_start0 + attribute \src "ls180.v:4401.6-4401.28" case 1'1 - assign $0\main_sdram_sequencer_count[0:0] 1'0 - attribute \src "ls180.v:7621.6-7621.10" + assign $0\sdram_sequencer_count[0:0] 1'0 + attribute \src "ls180.v:4403.6-4403.10" case - attribute \src "ls180.v:7622.3-7626.6" - switch \main_sdram_sequencer_done1 - attribute \src "ls180.v:7622.7-7622.33" + attribute \src "ls180.v:4404.3-4408.6" + switch \sdram_sequencer_done1 + attribute \src "ls180.v:4404.7-4404.28" case 1'1 - attribute \src "ls180.v:7623.4-7625.7" - switch $ne$ls180.v:7623$2479_Y - attribute \src "ls180.v:7623.8-7623.44" + attribute \src "ls180.v:4405.4-4407.7" + switch $ne$ls180.v:4405$1297_Y + attribute \src "ls180.v:4405.8-4405.39" case 1'1 - assign $0\main_sdram_sequencer_count[0:0] $sub$ls180.v:7624$2480_Y + assign $0\sdram_sequencer_count[0:0] $sub$ls180.v:4406$1298_Y case end case end end - attribute \src "ls180.v:7634.2-7640.5" - switch $and$ls180.v:7634$2482_Y - attribute \src "ls180.v:7634.6-7634.76" + attribute \src "ls180.v:4416.2-4422.5" + switch $and$ls180.v:4416$1300_Y + attribute \src "ls180.v:4416.6-4416.66" case 1'1 - assign $0\main_sdram_cmd_payload_a[12:0] 13'0010000000000 - assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 - assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_cmd_payload_ras[0:0] 1'1 - assign $0\main_sdram_cmd_payload_we[0:0] 1'1 + assign $0\sdram_cmd_payload_a[12:0] 13'0010000000000 + assign $0\sdram_cmd_payload_ba[1:0] 2'00 + assign $0\sdram_cmd_payload_cas[0:0] 1'0 + assign $0\sdram_cmd_payload_ras[0:0] 1'1 + assign $0\sdram_cmd_payload_we[0:0] 1'1 case end - attribute \src "ls180.v:7641.2-7647.5" - switch $eq$ls180.v:7641$2483_Y - attribute \src "ls180.v:7641.6-7641.44" + attribute \src "ls180.v:4423.2-4429.5" + switch $eq$ls180.v:4423$1301_Y + attribute \src "ls180.v:4423.6-4423.39" case 1'1 - assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 - assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 - assign $0\main_sdram_cmd_payload_cas[0:0] 1'1 - assign $0\main_sdram_cmd_payload_ras[0:0] 1'1 - assign $0\main_sdram_cmd_payload_we[0:0] 1'0 + assign $0\sdram_cmd_payload_a[12:0] 13'0000000000000 + assign $0\sdram_cmd_payload_ba[1:0] 2'00 + assign $0\sdram_cmd_payload_cas[0:0] 1'1 + assign $0\sdram_cmd_payload_ras[0:0] 1'1 + assign $0\sdram_cmd_payload_we[0:0] 1'0 case end - attribute \src "ls180.v:7648.2-7655.5" - switch $eq$ls180.v:7648$2484_Y - attribute \src "ls180.v:7648.6-7648.44" + attribute \src "ls180.v:4430.2-4437.5" + switch $eq$ls180.v:4430$1302_Y + attribute \src "ls180.v:4430.6-4430.39" case 1'1 - assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 - assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 - assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 - assign $0\main_sdram_cmd_payload_ras[0:0] 1'0 - assign $0\main_sdram_cmd_payload_we[0:0] 1'0 - assign $0\main_sdram_sequencer_done1[0:0] 1'1 + assign $0\sdram_cmd_payload_a[12:0] 13'0000000000000 + assign $0\sdram_cmd_payload_ba[1:0] 2'00 + assign $0\sdram_cmd_payload_cas[0:0] 1'0 + assign $0\sdram_cmd_payload_ras[0:0] 1'0 + assign $0\sdram_cmd_payload_we[0:0] 1'0 + assign $0\sdram_sequencer_done1[0:0] 1'1 case end - attribute \src "ls180.v:7656.2-7666.5" - switch $eq$ls180.v:7656$2485_Y - attribute \src "ls180.v:7656.6-7656.44" + attribute \src "ls180.v:4438.2-4448.5" + switch $eq$ls180.v:4438$1303_Y + attribute \src "ls180.v:4438.6-4438.39" case 1'1 - assign $0\main_sdram_sequencer_counter[3:0] 4'0000 - attribute \src "ls180.v:7658.6-7658.10" + assign $0\sdram_sequencer_counter[3:0] 4'0000 + attribute \src "ls180.v:4440.6-4440.10" case - attribute \src "ls180.v:7659.3-7665.6" - switch $ne$ls180.v:7659$2486_Y - attribute \src "ls180.v:7659.7-7659.45" + attribute \src "ls180.v:4441.3-4447.6" + switch $ne$ls180.v:4441$1304_Y + attribute \src "ls180.v:4441.7-4441.40" case 1'1 - assign $0\main_sdram_sequencer_counter[3:0] $add$ls180.v:7660$2487_Y - attribute \src "ls180.v:7661.7-7661.11" + assign $0\sdram_sequencer_counter[3:0] $add$ls180.v:4442$1305_Y + attribute \src "ls180.v:4443.7-4443.11" case - attribute \src "ls180.v:7662.4-7664.7" - switch \main_sdram_sequencer_start1 - attribute \src "ls180.v:7662.8-7662.35" + attribute \src "ls180.v:4444.4-4446.7" + switch \sdram_sequencer_start1 + attribute \src "ls180.v:4444.8-4444.30" case 1'1 - assign $0\main_sdram_sequencer_counter[3:0] 4'0001 + assign $0\sdram_sequencer_counter[3:0] 4'0001 case end end end - attribute \src "ls180.v:7668.2-7675.5" - switch \main_sdram_bankmachine0_row_close - attribute \src "ls180.v:7668.6-7668.39" + attribute \src "ls180.v:4450.2-4457.5" + switch \sdram_bankmachine0_row_close + attribute \src "ls180.v:4450.6-4450.34" case 1'1 - assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0 - attribute \src "ls180.v:7670.6-7670.10" + assign $0\sdram_bankmachine0_row_opened[0:0] 1'0 + attribute \src "ls180.v:4452.6-4452.10" case - attribute \src "ls180.v:7671.3-7674.6" - switch \main_sdram_bankmachine0_row_open - attribute \src "ls180.v:7671.7-7671.39" + attribute \src "ls180.v:4453.3-4456.6" + switch \sdram_bankmachine0_row_open + attribute \src "ls180.v:4453.7-4453.34" case 1'1 - assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'1 - assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + assign $0\sdram_bankmachine0_row_opened[0:0] 1'1 + assign $0\sdram_bankmachine0_row[12:0] \sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] case end end - attribute \src "ls180.v:7676.2-7678.5" - switch $and$ls180.v:7676$2490_Y - attribute \src "ls180.v:7676.6-7676.191" + attribute \src "ls180.v:4458.2-4460.5" + switch $and$ls180.v:4458$1308_Y + attribute \src "ls180.v:4458.6-4458.176" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7677$2491_Y + assign $0\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:4459$1309_Y case end - attribute \src "ls180.v:7679.2-7681.5" - switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7679.6-7679.58" + attribute \src "ls180.v:4461.2-4463.5" + switch \sdram_bankmachine0_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:4461.6-4461.53" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7680$2492_Y + assign $0\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:4462$1310_Y case end - attribute \src "ls180.v:7682.2-7690.5" - switch $and$ls180.v:7682$2495_Y - attribute \src "ls180.v:7682.6-7682.191" + attribute \src "ls180.v:4464.2-4472.5" + switch $and$ls180.v:4464$1313_Y + attribute \src "ls180.v:4464.6-4464.176" case 1'1 - attribute \src "ls180.v:7683.3-7685.6" - switch $not$ls180.v:7683$2496_Y - attribute \src "ls180.v:7683.7-7683.62" + attribute \src "ls180.v:4465.3-4467.6" + switch $not$ls180.v:4465$1314_Y + attribute \src "ls180.v:4465.7-4465.57" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7684$2497_Y + assign $0\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$ls180.v:4466$1315_Y case end - attribute \src "ls180.v:7686.6-7686.10" + attribute \src "ls180.v:4468.6-4468.10" case - attribute \src "ls180.v:7687.3-7689.6" - switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7687.7-7687.59" + attribute \src "ls180.v:4469.3-4471.6" + switch \sdram_bankmachine0_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:4469.7-4469.54" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7688$2498_Y + assign $0\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:4470$1316_Y case end end - attribute \src "ls180.v:7691.2-7697.5" - switch $or$ls180.v:7691$2500_Y - attribute \src "ls180.v:7691.6-7691.108" + attribute \src "ls180.v:4473.2-4479.5" + switch $or$ls180.v:4473$1318_Y + attribute \src "ls180.v:4473.6-4473.98" case 1'1 - assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_valid - assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_first - assign $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_last - assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_we - assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr + assign $0\sdram_bankmachine0_cmd_buffer_source_valid[0:0] \sdram_bankmachine0_cmd_buffer_sink_valid + assign $0\sdram_bankmachine0_cmd_buffer_source_first[0:0] \sdram_bankmachine0_cmd_buffer_sink_first + assign $0\sdram_bankmachine0_cmd_buffer_source_last[0:0] \sdram_bankmachine0_cmd_buffer_sink_last + assign $0\sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] \sdram_bankmachine0_cmd_buffer_sink_payload_we + assign $0\sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \sdram_bankmachine0_cmd_buffer_sink_payload_addr case end - attribute \src "ls180.v:7698.2-7712.5" - switch \main_sdram_bankmachine0_twtpcon_valid - attribute \src "ls180.v:7698.6-7698.43" + attribute \src "ls180.v:4480.2-4494.5" + switch \sdram_bankmachine0_twtpcon_valid + attribute \src "ls180.v:4480.6-4480.38" case 1'1 - assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7700.3-7704.6" + assign $0\sdram_bankmachine0_twtpcon_count[2:0] 3'100 + attribute \src "ls180.v:4482.3-4486.6" switch 1'0 - attribute \src "ls180.v:7702.7-7702.11" + attribute \src "ls180.v:4484.7-4484.11" case - assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 + assign $0\sdram_bankmachine0_twtpcon_ready[0:0] 1'0 end - attribute \src "ls180.v:7705.6-7705.10" + attribute \src "ls180.v:4487.6-4487.10" case - attribute \src "ls180.v:7706.3-7711.6" - switch $not$ls180.v:7706$2501_Y - attribute \src "ls180.v:7706.7-7706.47" + attribute \src "ls180.v:4488.3-4493.6" + switch $not$ls180.v:4488$1319_Y + attribute \src "ls180.v:4488.7-4488.42" case 1'1 - assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:7707$2502_Y - attribute \src "ls180.v:7708.4-7710.7" - switch $eq$ls180.v:7708$2503_Y - attribute \src "ls180.v:7708.8-7708.55" + assign $0\sdram_bankmachine0_twtpcon_count[2:0] $sub$ls180.v:4489$1320_Y + attribute \src "ls180.v:4490.4-4492.7" + switch $eq$ls180.v:4490$1321_Y + attribute \src "ls180.v:4490.8-4490.50" case 1'1 - assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'1 + assign $0\sdram_bankmachine0_twtpcon_ready[0:0] 1'1 case end case end end - attribute \src "ls180.v:7714.2-7721.5" - switch \main_sdram_bankmachine1_row_close - attribute \src "ls180.v:7714.6-7714.39" + attribute \src "ls180.v:4496.2-4503.5" + switch \sdram_bankmachine1_row_close + attribute \src "ls180.v:4496.6-4496.34" case 1'1 - assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0 - attribute \src "ls180.v:7716.6-7716.10" + assign $0\sdram_bankmachine1_row_opened[0:0] 1'0 + attribute \src "ls180.v:4498.6-4498.10" case - attribute \src "ls180.v:7717.3-7720.6" - switch \main_sdram_bankmachine1_row_open - attribute \src "ls180.v:7717.7-7717.39" + attribute \src "ls180.v:4499.3-4502.6" + switch \sdram_bankmachine1_row_open + attribute \src "ls180.v:4499.7-4499.34" case 1'1 - assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'1 - assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + assign $0\sdram_bankmachine1_row_opened[0:0] 1'1 + assign $0\sdram_bankmachine1_row[12:0] \sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] case end end - attribute \src "ls180.v:7722.2-7724.5" - switch $and$ls180.v:7722$2506_Y - attribute \src "ls180.v:7722.6-7722.191" + attribute \src "ls180.v:4504.2-4506.5" + switch $and$ls180.v:4504$1324_Y + attribute \src "ls180.v:4504.6-4504.176" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7723$2507_Y + assign $0\sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:4505$1325_Y case end - attribute \src "ls180.v:7725.2-7727.5" - switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7725.6-7725.58" + attribute \src "ls180.v:4507.2-4509.5" + switch \sdram_bankmachine1_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:4507.6-4507.53" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7726$2508_Y + assign $0\sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:4508$1326_Y case end - attribute \src "ls180.v:7728.2-7736.5" - switch $and$ls180.v:7728$2511_Y - attribute \src "ls180.v:7728.6-7728.191" + attribute \src "ls180.v:4510.2-4518.5" + switch $and$ls180.v:4510$1329_Y + attribute \src "ls180.v:4510.6-4510.176" case 1'1 - attribute \src "ls180.v:7729.3-7731.6" - switch $not$ls180.v:7729$2512_Y - attribute \src "ls180.v:7729.7-7729.62" + attribute \src "ls180.v:4511.3-4513.6" + switch $not$ls180.v:4511$1330_Y + attribute \src "ls180.v:4511.7-4511.57" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7730$2513_Y + assign $0\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$ls180.v:4512$1331_Y case end - attribute \src "ls180.v:7732.6-7732.10" + attribute \src "ls180.v:4514.6-4514.10" case - attribute \src "ls180.v:7733.3-7735.6" - switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7733.7-7733.59" + attribute \src "ls180.v:4515.3-4517.6" + switch \sdram_bankmachine1_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:4515.7-4515.54" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7734$2514_Y + assign $0\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:4516$1332_Y case end end - attribute \src "ls180.v:7737.2-7743.5" - switch $or$ls180.v:7737$2516_Y - attribute \src "ls180.v:7737.6-7737.108" + attribute \src "ls180.v:4519.2-4525.5" + switch $or$ls180.v:4519$1334_Y + attribute \src "ls180.v:4519.6-4519.98" case 1'1 - assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_valid - assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_first - assign $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_last - assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_we - assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr + assign $0\sdram_bankmachine1_cmd_buffer_source_valid[0:0] \sdram_bankmachine1_cmd_buffer_sink_valid + assign $0\sdram_bankmachine1_cmd_buffer_source_first[0:0] \sdram_bankmachine1_cmd_buffer_sink_first + assign $0\sdram_bankmachine1_cmd_buffer_source_last[0:0] \sdram_bankmachine1_cmd_buffer_sink_last + assign $0\sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] \sdram_bankmachine1_cmd_buffer_sink_payload_we + assign $0\sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \sdram_bankmachine1_cmd_buffer_sink_payload_addr case end - attribute \src "ls180.v:7744.2-7758.5" - switch \main_sdram_bankmachine1_twtpcon_valid - attribute \src "ls180.v:7744.6-7744.43" + attribute \src "ls180.v:4526.2-4540.5" + switch \sdram_bankmachine1_twtpcon_valid + attribute \src "ls180.v:4526.6-4526.38" case 1'1 - assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7746.3-7750.6" + assign $0\sdram_bankmachine1_twtpcon_count[2:0] 3'100 + attribute \src "ls180.v:4528.3-4532.6" switch 1'0 - attribute \src "ls180.v:7748.7-7748.11" + attribute \src "ls180.v:4530.7-4530.11" case - assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 + assign $0\sdram_bankmachine1_twtpcon_ready[0:0] 1'0 end - attribute \src "ls180.v:7751.6-7751.10" + attribute \src "ls180.v:4533.6-4533.10" case - attribute \src "ls180.v:7752.3-7757.6" - switch $not$ls180.v:7752$2517_Y - attribute \src "ls180.v:7752.7-7752.47" + attribute \src "ls180.v:4534.3-4539.6" + switch $not$ls180.v:4534$1335_Y + attribute \src "ls180.v:4534.7-4534.42" case 1'1 - assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:7753$2518_Y - attribute \src "ls180.v:7754.4-7756.7" - switch $eq$ls180.v:7754$2519_Y - attribute \src "ls180.v:7754.8-7754.55" + assign $0\sdram_bankmachine1_twtpcon_count[2:0] $sub$ls180.v:4535$1336_Y + attribute \src "ls180.v:4536.4-4538.7" + switch $eq$ls180.v:4536$1337_Y + attribute \src "ls180.v:4536.8-4536.50" case 1'1 - assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'1 + assign $0\sdram_bankmachine1_twtpcon_ready[0:0] 1'1 case end case end end - attribute \src "ls180.v:7760.2-7767.5" - switch \main_sdram_bankmachine2_row_close - attribute \src "ls180.v:7760.6-7760.39" + attribute \src "ls180.v:4542.2-4549.5" + switch \sdram_bankmachine2_row_close + attribute \src "ls180.v:4542.6-4542.34" case 1'1 - assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0 - attribute \src "ls180.v:7762.6-7762.10" + assign $0\sdram_bankmachine2_row_opened[0:0] 1'0 + attribute \src "ls180.v:4544.6-4544.10" case - attribute \src "ls180.v:7763.3-7766.6" - switch \main_sdram_bankmachine2_row_open - attribute \src "ls180.v:7763.7-7763.39" + attribute \src "ls180.v:4545.3-4548.6" + switch \sdram_bankmachine2_row_open + attribute \src "ls180.v:4545.7-4545.34" case 1'1 - assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'1 - assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + assign $0\sdram_bankmachine2_row_opened[0:0] 1'1 + assign $0\sdram_bankmachine2_row[12:0] \sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] case end end - attribute \src "ls180.v:7768.2-7770.5" - switch $and$ls180.v:7768$2522_Y - attribute \src "ls180.v:7768.6-7768.191" + attribute \src "ls180.v:4550.2-4552.5" + switch $and$ls180.v:4550$1340_Y + attribute \src "ls180.v:4550.6-4550.176" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7769$2523_Y + assign $0\sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:4551$1341_Y case end - attribute \src "ls180.v:7771.2-7773.5" - switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7771.6-7771.58" + attribute \src "ls180.v:4553.2-4555.5" + switch \sdram_bankmachine2_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:4553.6-4553.53" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7772$2524_Y + assign $0\sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:4554$1342_Y case end - attribute \src "ls180.v:7774.2-7782.5" - switch $and$ls180.v:7774$2527_Y - attribute \src "ls180.v:7774.6-7774.191" + attribute \src "ls180.v:4556.2-4564.5" + switch $and$ls180.v:4556$1345_Y + attribute \src "ls180.v:4556.6-4556.176" case 1'1 - attribute \src "ls180.v:7775.3-7777.6" - switch $not$ls180.v:7775$2528_Y - attribute \src "ls180.v:7775.7-7775.62" + attribute \src "ls180.v:4557.3-4559.6" + switch $not$ls180.v:4557$1346_Y + attribute \src "ls180.v:4557.7-4557.57" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7776$2529_Y + assign $0\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$ls180.v:4558$1347_Y case end - attribute \src "ls180.v:7778.6-7778.10" + attribute \src "ls180.v:4560.6-4560.10" case - attribute \src "ls180.v:7779.3-7781.6" - switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7779.7-7779.59" + attribute \src "ls180.v:4561.3-4563.6" + switch \sdram_bankmachine2_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:4561.7-4561.54" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7780$2530_Y + assign $0\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:4562$1348_Y case end end - attribute \src "ls180.v:7783.2-7789.5" - switch $or$ls180.v:7783$2532_Y - attribute \src "ls180.v:7783.6-7783.108" + attribute \src "ls180.v:4565.2-4571.5" + switch $or$ls180.v:4565$1350_Y + attribute \src "ls180.v:4565.6-4565.98" case 1'1 - assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_valid - assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_first - assign $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_last - assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_we - assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr + assign $0\sdram_bankmachine2_cmd_buffer_source_valid[0:0] \sdram_bankmachine2_cmd_buffer_sink_valid + assign $0\sdram_bankmachine2_cmd_buffer_source_first[0:0] \sdram_bankmachine2_cmd_buffer_sink_first + assign $0\sdram_bankmachine2_cmd_buffer_source_last[0:0] \sdram_bankmachine2_cmd_buffer_sink_last + assign $0\sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] \sdram_bankmachine2_cmd_buffer_sink_payload_we + assign $0\sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \sdram_bankmachine2_cmd_buffer_sink_payload_addr case end - attribute \src "ls180.v:7790.2-7804.5" - switch \main_sdram_bankmachine2_twtpcon_valid - attribute \src "ls180.v:7790.6-7790.43" + attribute \src "ls180.v:4572.2-4586.5" + switch \sdram_bankmachine2_twtpcon_valid + attribute \src "ls180.v:4572.6-4572.38" case 1'1 - assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7792.3-7796.6" + assign $0\sdram_bankmachine2_twtpcon_count[2:0] 3'100 + attribute \src "ls180.v:4574.3-4578.6" switch 1'0 - attribute \src "ls180.v:7794.7-7794.11" + attribute \src "ls180.v:4576.7-4576.11" case - assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 + assign $0\sdram_bankmachine2_twtpcon_ready[0:0] 1'0 end - attribute \src "ls180.v:7797.6-7797.10" + attribute \src "ls180.v:4579.6-4579.10" case - attribute \src "ls180.v:7798.3-7803.6" - switch $not$ls180.v:7798$2533_Y - attribute \src "ls180.v:7798.7-7798.47" + attribute \src "ls180.v:4580.3-4585.6" + switch $not$ls180.v:4580$1351_Y + attribute \src "ls180.v:4580.7-4580.42" case 1'1 - assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:7799$2534_Y - attribute \src "ls180.v:7800.4-7802.7" - switch $eq$ls180.v:7800$2535_Y - attribute \src "ls180.v:7800.8-7800.55" + assign $0\sdram_bankmachine2_twtpcon_count[2:0] $sub$ls180.v:4581$1352_Y + attribute \src "ls180.v:4582.4-4584.7" + switch $eq$ls180.v:4582$1353_Y + attribute \src "ls180.v:4582.8-4582.50" case 1'1 - assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'1 + assign $0\sdram_bankmachine2_twtpcon_ready[0:0] 1'1 case end case end end - attribute \src "ls180.v:7806.2-7813.5" - switch \main_sdram_bankmachine3_row_close - attribute \src "ls180.v:7806.6-7806.39" + attribute \src "ls180.v:4588.2-4595.5" + switch \sdram_bankmachine3_row_close + attribute \src "ls180.v:4588.6-4588.34" case 1'1 - assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0 - attribute \src "ls180.v:7808.6-7808.10" + assign $0\sdram_bankmachine3_row_opened[0:0] 1'0 + attribute \src "ls180.v:4590.6-4590.10" case - attribute \src "ls180.v:7809.3-7812.6" - switch \main_sdram_bankmachine3_row_open - attribute \src "ls180.v:7809.7-7809.39" + attribute \src "ls180.v:4591.3-4594.6" + switch \sdram_bankmachine3_row_open + attribute \src "ls180.v:4591.7-4591.34" case 1'1 - assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'1 - assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + assign $0\sdram_bankmachine3_row_opened[0:0] 1'1 + assign $0\sdram_bankmachine3_row[12:0] \sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] case end end - attribute \src "ls180.v:7814.2-7816.5" - switch $and$ls180.v:7814$2538_Y - attribute \src "ls180.v:7814.6-7814.191" + attribute \src "ls180.v:4596.2-4598.5" + switch $and$ls180.v:4596$1356_Y + attribute \src "ls180.v:4596.6-4596.176" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:7815$2539_Y + assign $0\sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$ls180.v:4597$1357_Y case end - attribute \src "ls180.v:7817.2-7819.5" - switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7817.6-7817.58" + attribute \src "ls180.v:4599.2-4601.5" + switch \sdram_bankmachine3_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:4599.6-4599.53" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:7818$2540_Y + assign $0\sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$ls180.v:4600$1358_Y case end - attribute \src "ls180.v:7820.2-7828.5" - switch $and$ls180.v:7820$2543_Y - attribute \src "ls180.v:7820.6-7820.191" + attribute \src "ls180.v:4602.2-4610.5" + switch $and$ls180.v:4602$1361_Y + attribute \src "ls180.v:4602.6-4602.176" case 1'1 - attribute \src "ls180.v:7821.3-7823.6" - switch $not$ls180.v:7821$2544_Y - attribute \src "ls180.v:7821.7-7821.62" + attribute \src "ls180.v:4603.3-4605.6" + switch $not$ls180.v:4603$1362_Y + attribute \src "ls180.v:4603.7-4603.57" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:7822$2545_Y + assign $0\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$ls180.v:4604$1363_Y case end - attribute \src "ls180.v:7824.6-7824.10" + attribute \src "ls180.v:4606.6-4606.10" case - attribute \src "ls180.v:7825.3-7827.6" - switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read - attribute \src "ls180.v:7825.7-7825.59" + attribute \src "ls180.v:4607.3-4609.6" + switch \sdram_bankmachine3_cmd_buffer_lookahead_do_read + attribute \src "ls180.v:4607.7-4607.54" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:7826$2546_Y + assign $0\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$ls180.v:4608$1364_Y case end end - attribute \src "ls180.v:7829.2-7835.5" - switch $or$ls180.v:7829$2548_Y - attribute \src "ls180.v:7829.6-7829.108" + attribute \src "ls180.v:4611.2-4617.5" + switch $or$ls180.v:4611$1366_Y + attribute \src "ls180.v:4611.6-4611.98" case 1'1 - assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_valid - assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_first - assign $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_last - assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_we - assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr + assign $0\sdram_bankmachine3_cmd_buffer_source_valid[0:0] \sdram_bankmachine3_cmd_buffer_sink_valid + assign $0\sdram_bankmachine3_cmd_buffer_source_first[0:0] \sdram_bankmachine3_cmd_buffer_sink_first + assign $0\sdram_bankmachine3_cmd_buffer_source_last[0:0] \sdram_bankmachine3_cmd_buffer_sink_last + assign $0\sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] \sdram_bankmachine3_cmd_buffer_sink_payload_we + assign $0\sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \sdram_bankmachine3_cmd_buffer_sink_payload_addr case end - attribute \src "ls180.v:7836.2-7850.5" - switch \main_sdram_bankmachine3_twtpcon_valid - attribute \src "ls180.v:7836.6-7836.43" + attribute \src "ls180.v:4618.2-4632.5" + switch \sdram_bankmachine3_twtpcon_valid + attribute \src "ls180.v:4618.6-4618.38" case 1'1 - assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'100 - attribute \src "ls180.v:7838.3-7842.6" + assign $0\sdram_bankmachine3_twtpcon_count[2:0] 3'100 + attribute \src "ls180.v:4620.3-4624.6" switch 1'0 - attribute \src "ls180.v:7840.7-7840.11" + attribute \src "ls180.v:4622.7-4622.11" case - assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 + assign $0\sdram_bankmachine3_twtpcon_ready[0:0] 1'0 end - attribute \src "ls180.v:7843.6-7843.10" + attribute \src "ls180.v:4625.6-4625.10" case - attribute \src "ls180.v:7844.3-7849.6" - switch $not$ls180.v:7844$2549_Y - attribute \src "ls180.v:7844.7-7844.47" + attribute \src "ls180.v:4626.3-4631.6" + switch $not$ls180.v:4626$1367_Y + attribute \src "ls180.v:4626.7-4626.42" case 1'1 - assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:7845$2550_Y - attribute \src "ls180.v:7846.4-7848.7" - switch $eq$ls180.v:7846$2551_Y - attribute \src "ls180.v:7846.8-7846.55" + assign $0\sdram_bankmachine3_twtpcon_count[2:0] $sub$ls180.v:4627$1368_Y + attribute \src "ls180.v:4628.4-4630.7" + switch $eq$ls180.v:4628$1369_Y + attribute \src "ls180.v:4628.8-4628.50" case 1'1 - assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'1 + assign $0\sdram_bankmachine3_twtpcon_ready[0:0] 1'1 case end case end end - attribute \src "ls180.v:7852.2-7858.5" - switch $not$ls180.v:7852$2552_Y - attribute \src "ls180.v:7852.6-7852.23" + attribute \src "ls180.v:4634.2-4640.5" + switch $not$ls180.v:4634$1370_Y + attribute \src "ls180.v:4634.6-4634.18" case 1'1 - assign $0\main_sdram_time0[4:0] 5'11111 - attribute \src "ls180.v:7854.6-7854.10" + assign $0\sdram_time0[4:0] 5'11111 + attribute \src "ls180.v:4636.6-4636.10" case - attribute \src "ls180.v:7855.3-7857.6" - switch $not$ls180.v:7855$2553_Y - attribute \src "ls180.v:7855.7-7855.30" + attribute \src "ls180.v:4637.3-4639.6" + switch $not$ls180.v:4637$1371_Y + attribute \src "ls180.v:4637.7-4637.25" case 1'1 - assign $0\main_sdram_time0[4:0] $sub$ls180.v:7856$2554_Y + assign $0\sdram_time0[4:0] $sub$ls180.v:4638$1372_Y case end end - attribute \src "ls180.v:7859.2-7865.5" - switch $not$ls180.v:7859$2555_Y - attribute \src "ls180.v:7859.6-7859.23" + attribute \src "ls180.v:4641.2-4647.5" + switch $not$ls180.v:4641$1373_Y + attribute \src "ls180.v:4641.6-4641.18" case 1'1 - assign $0\main_sdram_time1[3:0] 4'1111 - attribute \src "ls180.v:7861.6-7861.10" + assign $0\sdram_time1[3:0] 4'1111 + attribute \src "ls180.v:4643.6-4643.10" case - attribute \src "ls180.v:7862.3-7864.6" - switch $not$ls180.v:7862$2556_Y - attribute \src "ls180.v:7862.7-7862.30" + attribute \src "ls180.v:4644.3-4646.6" + switch $not$ls180.v:4644$1374_Y + attribute \src "ls180.v:4644.7-4644.25" case 1'1 - assign $0\main_sdram_time1[3:0] $sub$ls180.v:7863$2557_Y + assign $0\sdram_time1[3:0] $sub$ls180.v:4645$1375_Y case end end - attribute \src "ls180.v:7866.2-7921.5" - switch \main_sdram_choose_cmd_ce - attribute \src "ls180.v:7866.6-7866.30" + attribute \src "ls180.v:4648.2-4703.5" + switch \sdram_choose_cmd_ce + attribute \src "ls180.v:4648.6-4648.25" case 1'1 - attribute \src "ls180.v:7867.3-7920.10" - switch \main_sdram_choose_cmd_grant + attribute \src "ls180.v:4649.3-4702.10" + switch \sdram_choose_cmd_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - attribute \src "ls180.v:7869.5-7879.8" - switch \main_sdram_choose_cmd_request [1] - attribute \src "ls180.v:7869.9-7869.41" + attribute \src "ls180.v:4651.5-4661.8" + switch \sdram_choose_cmd_request [1] + attribute \src "ls180.v:4651.9-4651.36" case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 - attribute \src "ls180.v:7871.9-7871.13" + assign $0\sdram_choose_cmd_grant[1:0] 2'01 + attribute \src "ls180.v:4653.9-4653.13" case - attribute \src "ls180.v:7872.6-7878.9" - switch \main_sdram_choose_cmd_request [2] - attribute \src "ls180.v:7872.10-7872.42" + attribute \src "ls180.v:4654.6-4660.9" + switch \sdram_choose_cmd_request [2] + attribute \src "ls180.v:4654.10-4654.37" case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 - attribute \src "ls180.v:7874.10-7874.14" + assign $0\sdram_choose_cmd_grant[1:0] 2'10 + attribute \src "ls180.v:4656.10-4656.14" case - attribute \src "ls180.v:7875.7-7877.10" - switch \main_sdram_choose_cmd_request [3] - attribute \src "ls180.v:7875.11-7875.43" + attribute \src "ls180.v:4657.7-4659.10" + switch \sdram_choose_cmd_request [3] + attribute \src "ls180.v:4657.11-4657.38" case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 + assign $0\sdram_choose_cmd_grant[1:0] 2'11 case end end end attribute \src "ls180.v:0.0-0.0" case 2'01 - attribute \src "ls180.v:7882.5-7892.8" - switch \main_sdram_choose_cmd_request [2] - attribute \src "ls180.v:7882.9-7882.41" + attribute \src "ls180.v:4664.5-4674.8" + switch \sdram_choose_cmd_request [2] + attribute \src "ls180.v:4664.9-4664.36" case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 - attribute \src "ls180.v:7884.9-7884.13" + assign $0\sdram_choose_cmd_grant[1:0] 2'10 + attribute \src "ls180.v:4666.9-4666.13" case - attribute \src "ls180.v:7885.6-7891.9" - switch \main_sdram_choose_cmd_request [3] - attribute \src "ls180.v:7885.10-7885.42" + attribute \src "ls180.v:4667.6-4673.9" + switch \sdram_choose_cmd_request [3] + attribute \src "ls180.v:4667.10-4667.37" case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 - attribute \src "ls180.v:7887.10-7887.14" + assign $0\sdram_choose_cmd_grant[1:0] 2'11 + attribute \src "ls180.v:4669.10-4669.14" case - attribute \src "ls180.v:7888.7-7890.10" - switch \main_sdram_choose_cmd_request [0] - attribute \src "ls180.v:7888.11-7888.43" + attribute \src "ls180.v:4670.7-4672.10" + switch \sdram_choose_cmd_request [0] + attribute \src "ls180.v:4670.11-4670.38" case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 + assign $0\sdram_choose_cmd_grant[1:0] 2'00 case end end end attribute \src "ls180.v:0.0-0.0" case 2'10 - attribute \src "ls180.v:7895.5-7905.8" - switch \main_sdram_choose_cmd_request [3] - attribute \src "ls180.v:7895.9-7895.41" + attribute \src "ls180.v:4677.5-4687.8" + switch \sdram_choose_cmd_request [3] + attribute \src "ls180.v:4677.9-4677.36" case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 - attribute \src "ls180.v:7897.9-7897.13" + assign $0\sdram_choose_cmd_grant[1:0] 2'11 + attribute \src "ls180.v:4679.9-4679.13" case - attribute \src "ls180.v:7898.6-7904.9" - switch \main_sdram_choose_cmd_request [0] - attribute \src "ls180.v:7898.10-7898.42" + attribute \src "ls180.v:4680.6-4686.9" + switch \sdram_choose_cmd_request [0] + attribute \src "ls180.v:4680.10-4680.37" case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 - attribute \src "ls180.v:7900.10-7900.14" + assign $0\sdram_choose_cmd_grant[1:0] 2'00 + attribute \src "ls180.v:4682.10-4682.14" case - attribute \src "ls180.v:7901.7-7903.10" - switch \main_sdram_choose_cmd_request [1] - attribute \src "ls180.v:7901.11-7901.43" + attribute \src "ls180.v:4683.7-4685.10" + switch \sdram_choose_cmd_request [1] + attribute \src "ls180.v:4683.11-4683.38" case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 + assign $0\sdram_choose_cmd_grant[1:0] 2'01 case end end end attribute \src "ls180.v:0.0-0.0" case 2'11 - attribute \src "ls180.v:7908.5-7918.8" - switch \main_sdram_choose_cmd_request [0] - attribute \src "ls180.v:7908.9-7908.41" + attribute \src "ls180.v:4690.5-4700.8" + switch \sdram_choose_cmd_request [0] + attribute \src "ls180.v:4690.9-4690.36" case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 - attribute \src "ls180.v:7910.9-7910.13" + assign $0\sdram_choose_cmd_grant[1:0] 2'00 + attribute \src "ls180.v:4692.9-4692.13" case - attribute \src "ls180.v:7911.6-7917.9" - switch \main_sdram_choose_cmd_request [1] - attribute \src "ls180.v:7911.10-7911.42" + attribute \src "ls180.v:4693.6-4699.9" + switch \sdram_choose_cmd_request [1] + attribute \src "ls180.v:4693.10-4693.37" case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 - attribute \src "ls180.v:7913.10-7913.14" + assign $0\sdram_choose_cmd_grant[1:0] 2'01 + attribute \src "ls180.v:4695.10-4695.14" case - attribute \src "ls180.v:7914.7-7916.10" - switch \main_sdram_choose_cmd_request [2] - attribute \src "ls180.v:7914.11-7914.43" + attribute \src "ls180.v:4696.7-4698.10" + switch \sdram_choose_cmd_request [2] + attribute \src "ls180.v:4696.11-4696.38" case 1'1 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 + assign $0\sdram_choose_cmd_grant[1:0] 2'10 case end end @@ -295957,108 +268354,108 @@ module \ls180 end case end - attribute \src "ls180.v:7922.2-7977.5" - switch \main_sdram_choose_req_ce - attribute \src "ls180.v:7922.6-7922.30" + attribute \src "ls180.v:4704.2-4759.5" + switch \sdram_choose_req_ce + attribute \src "ls180.v:4704.6-4704.25" case 1'1 - attribute \src "ls180.v:7923.3-7976.10" - switch \main_sdram_choose_req_grant + attribute \src "ls180.v:4705.3-4758.10" + switch \sdram_choose_req_grant attribute \src "ls180.v:0.0-0.0" case 2'00 - attribute \src "ls180.v:7925.5-7935.8" - switch \main_sdram_choose_req_request [1] - attribute \src "ls180.v:7925.9-7925.41" + attribute \src "ls180.v:4707.5-4717.8" + switch \sdram_choose_req_request [1] + attribute \src "ls180.v:4707.9-4707.36" case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'01 - attribute \src "ls180.v:7927.9-7927.13" + assign $0\sdram_choose_req_grant[1:0] 2'01 + attribute \src "ls180.v:4709.9-4709.13" case - attribute \src "ls180.v:7928.6-7934.9" - switch \main_sdram_choose_req_request [2] - attribute \src "ls180.v:7928.10-7928.42" + attribute \src "ls180.v:4710.6-4716.9" + switch \sdram_choose_req_request [2] + attribute \src "ls180.v:4710.10-4710.37" case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'10 - attribute \src "ls180.v:7930.10-7930.14" + assign $0\sdram_choose_req_grant[1:0] 2'10 + attribute \src "ls180.v:4712.10-4712.14" case - attribute \src "ls180.v:7931.7-7933.10" - switch \main_sdram_choose_req_request [3] - attribute \src "ls180.v:7931.11-7931.43" + attribute \src "ls180.v:4713.7-4715.10" + switch \sdram_choose_req_request [3] + attribute \src "ls180.v:4713.11-4713.38" case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'11 + assign $0\sdram_choose_req_grant[1:0] 2'11 case end end end attribute \src "ls180.v:0.0-0.0" case 2'01 - attribute \src "ls180.v:7938.5-7948.8" - switch \main_sdram_choose_req_request [2] - attribute \src "ls180.v:7938.9-7938.41" + attribute \src "ls180.v:4720.5-4730.8" + switch \sdram_choose_req_request [2] + attribute \src "ls180.v:4720.9-4720.36" case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'10 - attribute \src "ls180.v:7940.9-7940.13" + assign $0\sdram_choose_req_grant[1:0] 2'10 + attribute \src "ls180.v:4722.9-4722.13" case - attribute \src "ls180.v:7941.6-7947.9" - switch \main_sdram_choose_req_request [3] - attribute \src "ls180.v:7941.10-7941.42" + attribute \src "ls180.v:4723.6-4729.9" + switch \sdram_choose_req_request [3] + attribute \src "ls180.v:4723.10-4723.37" case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'11 - attribute \src "ls180.v:7943.10-7943.14" + assign $0\sdram_choose_req_grant[1:0] 2'11 + attribute \src "ls180.v:4725.10-4725.14" case - attribute \src "ls180.v:7944.7-7946.10" - switch \main_sdram_choose_req_request [0] - attribute \src "ls180.v:7944.11-7944.43" + attribute \src "ls180.v:4726.7-4728.10" + switch \sdram_choose_req_request [0] + attribute \src "ls180.v:4726.11-4726.38" case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'00 + assign $0\sdram_choose_req_grant[1:0] 2'00 case end end end attribute \src "ls180.v:0.0-0.0" case 2'10 - attribute \src "ls180.v:7951.5-7961.8" - switch \main_sdram_choose_req_request [3] - attribute \src "ls180.v:7951.9-7951.41" + attribute \src "ls180.v:4733.5-4743.8" + switch \sdram_choose_req_request [3] + attribute \src "ls180.v:4733.9-4733.36" case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'11 - attribute \src "ls180.v:7953.9-7953.13" + assign $0\sdram_choose_req_grant[1:0] 2'11 + attribute \src "ls180.v:4735.9-4735.13" case - attribute \src "ls180.v:7954.6-7960.9" - switch \main_sdram_choose_req_request [0] - attribute \src "ls180.v:7954.10-7954.42" + attribute \src "ls180.v:4736.6-4742.9" + switch \sdram_choose_req_request [0] + attribute \src "ls180.v:4736.10-4736.37" case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'00 - attribute \src "ls180.v:7956.10-7956.14" + assign $0\sdram_choose_req_grant[1:0] 2'00 + attribute \src "ls180.v:4738.10-4738.14" case - attribute \src "ls180.v:7957.7-7959.10" - switch \main_sdram_choose_req_request [1] - attribute \src "ls180.v:7957.11-7957.43" + attribute \src "ls180.v:4739.7-4741.10" + switch \sdram_choose_req_request [1] + attribute \src "ls180.v:4739.11-4739.38" case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'01 + assign $0\sdram_choose_req_grant[1:0] 2'01 case end end end attribute \src "ls180.v:0.0-0.0" case 2'11 - attribute \src "ls180.v:7964.5-7974.8" - switch \main_sdram_choose_req_request [0] - attribute \src "ls180.v:7964.9-7964.41" + attribute \src "ls180.v:4746.5-4756.8" + switch \sdram_choose_req_request [0] + attribute \src "ls180.v:4746.9-4746.36" case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'00 - attribute \src "ls180.v:7966.9-7966.13" + assign $0\sdram_choose_req_grant[1:0] 2'00 + attribute \src "ls180.v:4748.9-4748.13" case - attribute \src "ls180.v:7967.6-7973.9" - switch \main_sdram_choose_req_request [1] - attribute \src "ls180.v:7967.10-7967.42" + attribute \src "ls180.v:4749.6-4755.9" + switch \sdram_choose_req_request [1] + attribute \src "ls180.v:4749.10-4749.37" case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'01 - attribute \src "ls180.v:7969.10-7969.14" + assign $0\sdram_choose_req_grant[1:0] 2'01 + attribute \src "ls180.v:4751.10-4751.14" case - attribute \src "ls180.v:7970.7-7972.10" - switch \main_sdram_choose_req_request [2] - attribute \src "ls180.v:7970.11-7970.43" + attribute \src "ls180.v:4752.7-4754.10" + switch \sdram_choose_req_request [2] + attribute \src "ls180.v:4752.11-4752.38" case 1'1 - assign $0\main_sdram_choose_req_grant[1:0] 2'10 + assign $0\sdram_choose_req_grant[1:0] 2'10 case end end @@ -296067,6260 +268464,4884 @@ module \ls180 end case end - attribute \src "ls180.v:7986.2-8000.5" - switch \main_sdram_tccdcon_valid - attribute \src "ls180.v:7986.6-7986.30" + attribute \src "ls180.v:4768.2-4782.5" + switch \sdram_tccdcon_valid + attribute \src "ls180.v:4768.6-4768.25" case 1'1 - assign $0\main_sdram_tccdcon_count[0:0] 1'0 - attribute \src "ls180.v:7988.3-7992.6" + assign $0\sdram_tccdcon_count[0:0] 1'0 + attribute \src "ls180.v:4770.3-4774.6" switch 1'1 - attribute \src "ls180.v:7988.7-7988.11" + attribute \src "ls180.v:4770.7-4770.11" case 1'1 - assign $0\main_sdram_tccdcon_ready[0:0] 1'1 + assign $0\sdram_tccdcon_ready[0:0] 1'1 case end - attribute \src "ls180.v:7993.6-7993.10" + attribute \src "ls180.v:4775.6-4775.10" case - attribute \src "ls180.v:7994.3-7999.6" - switch $not$ls180.v:7994$2561_Y - attribute \src "ls180.v:7994.7-7994.34" + attribute \src "ls180.v:4776.3-4781.6" + switch $not$ls180.v:4776$1379_Y + attribute \src "ls180.v:4776.7-4776.29" case 1'1 - assign $0\main_sdram_tccdcon_count[0:0] $sub$ls180.v:7995$2562_Y - attribute \src "ls180.v:7996.4-7998.7" - switch $eq$ls180.v:7996$2563_Y - attribute \src "ls180.v:7996.8-7996.42" + assign $0\sdram_tccdcon_count[0:0] $sub$ls180.v:4777$1380_Y + attribute \src "ls180.v:4778.4-4780.7" + switch $eq$ls180.v:4778$1381_Y + attribute \src "ls180.v:4778.8-4778.37" case 1'1 - assign $0\main_sdram_tccdcon_ready[0:0] 1'1 + assign $0\sdram_tccdcon_ready[0:0] 1'1 case end case end end - attribute \src "ls180.v:8001.2-8015.5" - switch \main_sdram_twtrcon_valid - attribute \src "ls180.v:8001.6-8001.30" + attribute \src "ls180.v:4783.2-4797.5" + switch \sdram_twtrcon_valid + attribute \src "ls180.v:4783.6-4783.25" case 1'1 - assign $0\main_sdram_twtrcon_count[2:0] 3'100 - attribute \src "ls180.v:8003.3-8007.6" + assign $0\sdram_twtrcon_count[2:0] 3'100 + attribute \src "ls180.v:4785.3-4789.6" switch 1'0 - attribute \src "ls180.v:8005.7-8005.11" + attribute \src "ls180.v:4787.7-4787.11" case - assign $0\main_sdram_twtrcon_ready[0:0] 1'0 + assign $0\sdram_twtrcon_ready[0:0] 1'0 end - attribute \src "ls180.v:8008.6-8008.10" + attribute \src "ls180.v:4790.6-4790.10" case - attribute \src "ls180.v:8009.3-8014.6" - switch $not$ls180.v:8009$2564_Y - attribute \src "ls180.v:8009.7-8009.34" + attribute \src "ls180.v:4791.3-4796.6" + switch $not$ls180.v:4791$1382_Y + attribute \src "ls180.v:4791.7-4791.29" case 1'1 - assign $0\main_sdram_twtrcon_count[2:0] $sub$ls180.v:8010$2565_Y - attribute \src "ls180.v:8011.4-8013.7" - switch $eq$ls180.v:8011$2566_Y - attribute \src "ls180.v:8011.8-8011.42" + assign $0\sdram_twtrcon_count[2:0] $sub$ls180.v:4792$1383_Y + attribute \src "ls180.v:4793.4-4795.7" + switch $eq$ls180.v:4793$1384_Y + attribute \src "ls180.v:4793.8-4793.37" case 1'1 - assign $0\main_sdram_twtrcon_ready[0:0] 1'1 + assign $0\sdram_twtrcon_ready[0:0] 1'1 case end case end end - attribute \src "ls180.v:8022.2-8024.5" - switch $or$ls180.v:8022$2591_Y - attribute \src "ls180.v:8022.6-8022.50" + attribute \src "ls180.v:4804.2-4806.5" + switch $or$ls180.v:4804$1409_Y + attribute \src "ls180.v:4804.6-4804.40" case 1'1 - assign $0\main_converter_dat_r[31:0] \main_wb_sdram_dat_r + assign $0\converter_dat_r[31:0] \wb_sdram_dat_r case end - attribute \src "ls180.v:8026.2-8028.5" - switch \main_converter_counter_converter_next_value_ce - attribute \src "ls180.v:8026.6-8026.52" + attribute \src "ls180.v:4808.2-4810.5" + switch \converter_counter_subfragments_next_value_ce + attribute \src "ls180.v:4808.6-4808.50" case 1'1 - assign $0\main_converter_counter[0:0] \main_converter_counter_converter_next_value + assign $0\converter_counter[0:0] \converter_counter_subfragments_next_value case end - attribute \src "ls180.v:8029.2-8032.5" - switch \main_converter_reset - attribute \src "ls180.v:8029.6-8029.26" + attribute \src "ls180.v:4811.2-4814.5" + switch \converter_reset + attribute \src "ls180.v:4811.6-4811.21" case 1'1 - assign $0\main_converter_counter[0:0] 1'0 - assign $0\builder_converter_state[0:0] 1'0 + assign $0\converter_counter[0:0] 1'0 + assign $0\subfragments_state[0:0] 1'0 case end - attribute \src "ls180.v:8033.2-8043.5" - switch \main_litedram_wb_ack - attribute \src "ls180.v:8033.6-8033.26" + attribute \src "ls180.v:4815.2-4825.5" + switch \litedram_wb_ack + attribute \src "ls180.v:4815.6-4815.21" case 1'1 - assign $0\main_cmd_consumed[0:0] 1'0 - assign $0\main_wdata_consumed[0:0] 1'0 - attribute \src "ls180.v:8036.6-8036.10" + assign $0\cmd_consumed[0:0] 1'0 + assign $0\wdata_consumed[0:0] 1'0 + attribute \src "ls180.v:4818.6-4818.10" case - attribute \src "ls180.v:8037.3-8039.6" - switch $and$ls180.v:8037$2592_Y - attribute \src "ls180.v:8037.7-8037.50" + attribute \src "ls180.v:4819.3-4821.6" + switch $and$ls180.v:4819$1410_Y + attribute \src "ls180.v:4819.7-4819.40" case 1'1 - assign $0\main_cmd_consumed[0:0] 1'1 + assign $0\cmd_consumed[0:0] 1'1 case end - attribute \src "ls180.v:8040.3-8042.6" - switch $and$ls180.v:8040$2593_Y - attribute \src "ls180.v:8040.7-8040.54" + attribute \src "ls180.v:4822.3-4824.6" + switch $and$ls180.v:4822$1411_Y + attribute \src "ls180.v:4822.7-4822.44" case 1'1 - assign $0\main_wdata_consumed[0:0] 1'1 + assign $0\wdata_consumed[0:0] 1'1 case end end - attribute \src "ls180.v:8045.2-8066.5" - switch $and$ls180.v:8045$2597_Y - attribute \src "ls180.v:8045.6-8045.91" + attribute \src "ls180.v:4827.2-4848.5" + switch $and$ls180.v:4827$1415_Y + attribute \src "ls180.v:4827.6-4827.76" case 1'1 - assign $0\main_uart_phy_tx_reg[7:0] \main_uart_phy_sink_payload_data - assign $0\main_uart_phy_tx_bitcount[3:0] 4'0000 - assign $0\main_uart_phy_tx_busy[0:0] 1'1 - assign $0\uart_tx[0:0] 1'0 - attribute \src "ls180.v:8050.6-8050.10" + assign $0\uart_phy_tx_reg[7:0] \uart_phy_sink_payload_data + assign $0\uart_phy_tx_bitcount[3:0] 4'0000 + assign $0\uart_phy_tx_busy[0:0] 1'1 + assign $0\libresocsim_libresoc_constraintmanager_obj_uart_tx[0:0] 1'0 + attribute \src "ls180.v:4832.6-4832.10" case - attribute \src "ls180.v:8051.3-8065.6" - switch $and$ls180.v:8051$2598_Y - attribute \src "ls180.v:8051.7-8051.60" + attribute \src "ls180.v:4833.3-4847.6" + switch $and$ls180.v:4833$1416_Y + attribute \src "ls180.v:4833.7-4833.50" case 1'1 - assign $0\main_uart_phy_tx_bitcount[3:0] $add$ls180.v:8052$2599_Y - attribute \src "ls180.v:8053.4-8064.7" - switch $eq$ls180.v:8053$2600_Y - attribute \src "ls180.v:8053.8-8053.43" + assign $0\uart_phy_tx_bitcount[3:0] $add$ls180.v:4834$1417_Y + attribute \src "ls180.v:4835.4-4846.7" + switch $eq$ls180.v:4835$1418_Y + attribute \src "ls180.v:4835.8-4835.38" case 1'1 - assign $0\uart_tx[0:0] 1'1 - attribute \src "ls180.v:8055.8-8055.12" + assign $0\libresocsim_libresoc_constraintmanager_obj_uart_tx[0:0] 1'1 + attribute \src "ls180.v:4837.8-4837.12" case - attribute \src "ls180.v:8056.5-8063.8" - switch $eq$ls180.v:8056$2601_Y - attribute \src "ls180.v:8056.9-8056.44" + attribute \src "ls180.v:4838.5-4845.8" + switch $eq$ls180.v:4838$1419_Y + attribute \src "ls180.v:4838.9-4838.39" case 1'1 - assign $0\uart_tx[0:0] 1'1 - assign $0\main_uart_phy_tx_busy[0:0] 1'0 - assign $0\main_uart_phy_sink_ready[0:0] 1'1 - attribute \src "ls180.v:8060.9-8060.13" + assign $0\libresocsim_libresoc_constraintmanager_obj_uart_tx[0:0] 1'1 + assign $0\uart_phy_tx_busy[0:0] 1'0 + assign $0\uart_phy_sink_ready[0:0] 1'1 + attribute \src "ls180.v:4842.9-4842.13" case - assign $0\uart_tx[0:0] \main_uart_phy_tx_reg [0] - assign $0\main_uart_phy_tx_reg[7:0] { 1'0 \main_uart_phy_tx_reg [7:1] } + assign $0\libresocsim_libresoc_constraintmanager_obj_uart_tx[0:0] \uart_phy_tx_reg [0] + assign $0\uart_phy_tx_reg[7:0] { 1'0 \uart_phy_tx_reg [7:1] } end end case end end - attribute \src "ls180.v:8067.2-8071.5" - switch \main_uart_phy_tx_busy - attribute \src "ls180.v:8067.6-8067.27" + attribute \src "ls180.v:4849.2-4853.5" + switch \uart_phy_tx_busy + attribute \src "ls180.v:4849.6-4849.22" case 1'1 - assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:8068$2602_Y - attribute \src "ls180.v:8069.6-8069.10" + assign { $0\uart_phy_uart_clk_txen[0:0] $0\uart_phy_phase_accumulator_tx[31:0] } $add$ls180.v:4850$1420_Y + attribute \src "ls180.v:4851.6-4851.10" case - assign { $0\main_uart_phy_uart_clk_txen[0:0] $0\main_uart_phy_phase_accumulator_tx[31:0] } { 1'0 \main_uart_phy_storage } + assign { $0\uart_phy_uart_clk_txen[0:0] $0\uart_phy_phase_accumulator_tx[31:0] } { 1'0 \uart_phy_storage } end - attribute \src "ls180.v:8074.2-8098.5" - switch $not$ls180.v:8074$2603_Y - attribute \src "ls180.v:8074.6-8074.30" + attribute \src "ls180.v:4856.2-4880.5" + switch $not$ls180.v:4856$1421_Y + attribute \src "ls180.v:4856.6-4856.25" case 1'1 - attribute \src "ls180.v:8075.3-8078.6" - switch $and$ls180.v:8075$2605_Y - attribute \src "ls180.v:8075.7-8075.49" + attribute \src "ls180.v:4857.3-4860.6" + switch $and$ls180.v:4857$1423_Y + attribute \src "ls180.v:4857.7-4857.39" case 1'1 - assign $0\main_uart_phy_rx_busy[0:0] 1'1 - assign $0\main_uart_phy_rx_bitcount[3:0] 4'0000 + assign $0\uart_phy_rx_busy[0:0] 1'1 + assign $0\uart_phy_rx_bitcount[3:0] 4'0000 case end - attribute \src "ls180.v:8079.6-8079.10" + attribute \src "ls180.v:4861.6-4861.10" case - attribute \src "ls180.v:8080.3-8097.6" - switch \main_uart_phy_uart_clk_rxen - attribute \src "ls180.v:8080.7-8080.34" + attribute \src "ls180.v:4862.3-4879.6" + switch \uart_phy_uart_clk_rxen + attribute \src "ls180.v:4862.7-4862.29" case 1'1 - assign $0\main_uart_phy_rx_bitcount[3:0] $add$ls180.v:8081$2606_Y - attribute \src "ls180.v:8082.4-8096.7" - switch $eq$ls180.v:8082$2607_Y - attribute \src "ls180.v:8082.8-8082.43" + assign $0\uart_phy_rx_bitcount[3:0] $add$ls180.v:4863$1424_Y + attribute \src "ls180.v:4864.4-4878.7" + switch $eq$ls180.v:4864$1425_Y + attribute \src "ls180.v:4864.8-4864.38" case 1'1 - attribute \src "ls180.v:8083.5-8085.8" - switch \main_uart_phy_rx - attribute \src "ls180.v:8083.9-8083.25" + attribute \src "ls180.v:4865.5-4867.8" + switch \uart_phy_rx + attribute \src "ls180.v:4865.9-4865.20" case 1'1 - assign $0\main_uart_phy_rx_busy[0:0] 1'0 + assign $0\uart_phy_rx_busy[0:0] 1'0 case end - attribute \src "ls180.v:8086.8-8086.12" + attribute \src "ls180.v:4868.8-4868.12" case - attribute \src "ls180.v:8087.5-8095.8" - switch $eq$ls180.v:8087$2608_Y - attribute \src "ls180.v:8087.9-8087.44" + attribute \src "ls180.v:4869.5-4877.8" + switch $eq$ls180.v:4869$1426_Y + attribute \src "ls180.v:4869.9-4869.39" case 1'1 - assign $0\main_uart_phy_rx_busy[0:0] 1'0 - attribute \src "ls180.v:8089.6-8092.9" - switch \main_uart_phy_rx - attribute \src "ls180.v:8089.10-8089.26" + assign $0\uart_phy_rx_busy[0:0] 1'0 + attribute \src "ls180.v:4871.6-4874.9" + switch \uart_phy_rx + attribute \src "ls180.v:4871.10-4871.21" case 1'1 - assign $0\main_uart_phy_source_payload_data[7:0] \main_uart_phy_rx_reg - assign $0\main_uart_phy_source_valid[0:0] 1'1 + assign $0\uart_phy_source_payload_data[7:0] \uart_phy_rx_reg + assign $0\uart_phy_source_valid[0:0] 1'1 case end - attribute \src "ls180.v:8093.9-8093.13" + attribute \src "ls180.v:4875.9-4875.13" case - assign $0\main_uart_phy_rx_reg[7:0] { \main_uart_phy_rx \main_uart_phy_rx_reg [7:1] } + assign $0\uart_phy_rx_reg[7:0] { \uart_phy_rx \uart_phy_rx_reg [7:1] } end end case end end - attribute \src "ls180.v:8099.2-8103.5" - switch \main_uart_phy_rx_busy - attribute \src "ls180.v:8099.6-8099.27" - case 1'1 - assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:8100$2609_Y - attribute \src "ls180.v:8101.6-8101.10" - case - assign { $0\main_uart_phy_uart_clk_rxen[0:0] $0\main_uart_phy_phase_accumulator_rx[31:0] } 33'010000000000000000000000000000000 - end - attribute \src "ls180.v:8104.2-8106.5" - switch \main_uart_tx_clear - attribute \src "ls180.v:8104.6-8104.24" - case 1'1 - assign $0\main_uart_tx_pending[0:0] 1'0 - case - end - attribute \src "ls180.v:8108.2-8110.5" - switch $and$ls180.v:8108$2611_Y - attribute \src "ls180.v:8108.6-8108.58" - case 1'1 - assign $0\main_uart_tx_pending[0:0] 1'1 - case - end - attribute \src "ls180.v:8111.2-8113.5" - switch \main_uart_rx_clear - attribute \src "ls180.v:8111.6-8111.24" - case 1'1 - assign $0\main_uart_rx_pending[0:0] 1'0 - case - end - attribute \src "ls180.v:8115.2-8117.5" - switch $and$ls180.v:8115$2613_Y - attribute \src "ls180.v:8115.6-8115.58" - case 1'1 - assign $0\main_uart_rx_pending[0:0] 1'1 - case - end - attribute \src "ls180.v:8118.2-8124.5" - switch \main_uart_tx_fifo_syncfifo_re - attribute \src "ls180.v:8118.6-8118.35" - case 1'1 - assign $0\main_uart_tx_fifo_readable[0:0] 1'1 - attribute \src "ls180.v:8120.6-8120.10" - case - attribute \src "ls180.v:8121.3-8123.6" - switch \main_uart_tx_fifo_re - attribute \src "ls180.v:8121.7-8121.27" - case 1'1 - assign $0\main_uart_tx_fifo_readable[0:0] 1'0 - case - end - end - attribute \src "ls180.v:8125.2-8127.5" - switch $and$ls180.v:8125$2616_Y - attribute \src "ls180.v:8125.6-8125.108" - case 1'1 - assign $0\main_uart_tx_fifo_produce[3:0] $add$ls180.v:8126$2617_Y - case - end - attribute \src "ls180.v:8128.2-8130.5" - switch \main_uart_tx_fifo_do_read - attribute \src "ls180.v:8128.6-8128.31" - case 1'1 - assign $0\main_uart_tx_fifo_consume[3:0] $add$ls180.v:8129$2618_Y - case - end - attribute \src "ls180.v:8131.2-8139.5" - switch $and$ls180.v:8131$2621_Y - attribute \src "ls180.v:8131.6-8131.108" - case 1'1 - attribute \src "ls180.v:8132.3-8134.6" - switch $not$ls180.v:8132$2622_Y - attribute \src "ls180.v:8132.7-8132.35" - case 1'1 - assign $0\main_uart_tx_fifo_level0[4:0] $add$ls180.v:8133$2623_Y - case - end - attribute \src "ls180.v:8135.6-8135.10" - case - attribute \src "ls180.v:8136.3-8138.6" - switch \main_uart_tx_fifo_do_read - attribute \src "ls180.v:8136.7-8136.32" - case 1'1 - assign $0\main_uart_tx_fifo_level0[4:0] $sub$ls180.v:8137$2624_Y - case - end - end - attribute \src "ls180.v:8140.2-8146.5" - switch \main_uart_rx_fifo_syncfifo_re - attribute \src "ls180.v:8140.6-8140.35" - case 1'1 - assign $0\main_uart_rx_fifo_readable[0:0] 1'1 - attribute \src "ls180.v:8142.6-8142.10" - case - attribute \src "ls180.v:8143.3-8145.6" - switch \main_uart_rx_fifo_re - attribute \src "ls180.v:8143.7-8143.27" - case 1'1 - assign $0\main_uart_rx_fifo_readable[0:0] 1'0 - case - end - end - attribute \src "ls180.v:8147.2-8149.5" - switch $and$ls180.v:8147$2627_Y - attribute \src "ls180.v:8147.6-8147.108" - case 1'1 - assign $0\main_uart_rx_fifo_produce[3:0] $add$ls180.v:8148$2628_Y - case - end - attribute \src "ls180.v:8150.2-8152.5" - switch \main_uart_rx_fifo_do_read - attribute \src "ls180.v:8150.6-8150.31" - case 1'1 - assign $0\main_uart_rx_fifo_consume[3:0] $add$ls180.v:8151$2629_Y - case - end - attribute \src "ls180.v:8153.2-8161.5" - switch $and$ls180.v:8153$2632_Y - attribute \src "ls180.v:8153.6-8153.108" - case 1'1 - attribute \src "ls180.v:8154.3-8156.6" - switch $not$ls180.v:8154$2633_Y - attribute \src "ls180.v:8154.7-8154.35" - case 1'1 - assign $0\main_uart_rx_fifo_level0[4:0] $add$ls180.v:8155$2634_Y - case - end - attribute \src "ls180.v:8157.6-8157.10" - case - attribute \src "ls180.v:8158.3-8160.6" - switch \main_uart_rx_fifo_do_read - attribute \src "ls180.v:8158.7-8158.32" - case 1'1 - assign $0\main_uart_rx_fifo_level0[4:0] $sub$ls180.v:8159$2635_Y - case - end - end - attribute \src "ls180.v:8162.2-8175.5" - switch \main_uart_reset - attribute \src "ls180.v:8162.6-8162.21" - case 1'1 - assign $0\main_uart_tx_pending[0:0] 1'0 - assign $0\main_uart_tx_old_trigger[0:0] 1'0 - assign $0\main_uart_rx_pending[0:0] 1'0 - assign $0\main_uart_rx_old_trigger[0:0] 1'0 - assign $0\main_uart_tx_fifo_readable[0:0] 1'0 - assign $0\main_uart_tx_fifo_level0[4:0] 5'00000 - assign $0\main_uart_tx_fifo_produce[3:0] 4'0000 - assign $0\main_uart_tx_fifo_consume[3:0] 4'0000 - assign $0\main_uart_rx_fifo_readable[0:0] 1'0 - assign $0\main_uart_rx_fifo_level0[4:0] 5'00000 - assign $0\main_uart_rx_fifo_produce[3:0] 4'0000 - assign $0\main_uart_rx_fifo_consume[3:0] 4'0000 - case - end - attribute \src "ls180.v:8177.2-8184.5" - switch \main_spimaster31_clk_rise - attribute \src "ls180.v:8177.6-8177.31" - case 1'1 - assign $0\spisdcard_clk[0:0] \main_spimaster25_clk_enable - attribute \src "ls180.v:8179.6-8179.10" - case - attribute \src "ls180.v:8180.3-8183.6" - switch \main_spimaster32_clk_fall - attribute \src "ls180.v:8180.7-8180.32" - case 1'1 - assign $0\main_spimaster30_clk_divider[15:0] 16'0000000000000000 - assign $0\spisdcard_clk[0:0] 1'0 - case - end - end - attribute \src "ls180.v:8186.2-8196.5" - switch \main_spimaster28_mosi_latch - attribute \src "ls180.v:8186.6-8186.33" - case 1'1 - assign $0\main_spimaster33_mosi_data[7:0] \main_spimaster4_mosi - assign $0\main_spimaster34_mosi_sel[2:0] 3'111 - attribute \src "ls180.v:8189.6-8189.10" - case - attribute \src "ls180.v:8190.3-8195.6" - switch \main_spimaster32_clk_fall - attribute \src "ls180.v:8190.7-8190.32" - case 1'1 - assign $0\main_spimaster34_mosi_sel[2:0] $sub$ls180.v:8194$2640_Y - attribute \src "ls180.v:8191.4-8193.7" - switch \main_spimaster26_cs_enable - attribute \src "ls180.v:8191.8-8191.34" - case 1'1 - assign $0\spisdcard_mosi[0:0] \builder_sync_f_array_muxed0 - case - end - case - end - end - attribute \src "ls180.v:8197.2-8203.5" - switch \main_spimaster31_clk_rise - attribute \src "ls180.v:8197.6-8197.31" - case 1'1 - attribute \src "ls180.v:8198.3-8202.6" - switch \main_spimaster7_loopback - attribute \src "ls180.v:8198.7-8198.31" - case 1'1 - assign $0\main_spimaster35_miso_data[7:0] { \main_spimaster35_miso_data [6:0] \spisdcard_mosi } - attribute \src "ls180.v:8200.7-8200.11" - case - assign $0\main_spimaster35_miso_data[7:0] { \main_spimaster35_miso_data [6:0] \spisdcard_miso } - end - case - end - attribute \src "ls180.v:8204.2-8206.5" - switch \main_spimaster29_miso_latch - attribute \src "ls180.v:8204.6-8204.33" - case 1'1 - assign $0\main_spimaster5_miso[7:0] \main_spimaster35_miso_data - case - end - attribute \src "ls180.v:8208.2-8210.5" - switch \main_spimaster27_count_spimaster0_next_value_ce - attribute \src "ls180.v:8208.6-8208.53" - case 1'1 - assign $0\main_spimaster27_count[2:0] \main_spimaster27_count_spimaster0_next_value - case - end - attribute \src "ls180.v:8212.2-8219.5" - switch \main_spisdcard_clk_rise - attribute \src "ls180.v:8212.6-8212.29" - case 1'1 - assign $0\spimaster_clk[0:0] \main_spisdcard_clk_enable - attribute \src "ls180.v:8214.6-8214.10" - case - attribute \src "ls180.v:8215.3-8218.6" - switch \main_spisdcard_clk_fall - attribute \src "ls180.v:8215.7-8215.30" - case 1'1 - assign $0\main_spisdcard_clk_divider1[15:0] 16'0000000000000000 - assign $0\spimaster_clk[0:0] 1'0 - case - end - end - attribute \src "ls180.v:8221.2-8231.5" - switch \main_spisdcard_mosi_latch - attribute \src "ls180.v:8221.6-8221.31" - case 1'1 - assign $0\main_spisdcard_mosi_data[7:0] \main_spisdcard_mosi - assign $0\main_spisdcard_mosi_sel[2:0] 3'111 - attribute \src "ls180.v:8224.6-8224.10" - case - attribute \src "ls180.v:8225.3-8230.6" - switch \main_spisdcard_clk_fall - attribute \src "ls180.v:8225.7-8225.30" - case 1'1 - assign $0\main_spisdcard_mosi_sel[2:0] $sub$ls180.v:8229$2645_Y - attribute \src "ls180.v:8226.4-8228.7" - switch \main_spisdcard_cs_enable - attribute \src "ls180.v:8226.8-8226.32" - case 1'1 - assign $0\spimaster_mosi[0:0] \builder_sync_f_array_muxed1 - case - end - case - end - end - attribute \src "ls180.v:8232.2-8238.5" - switch \main_spisdcard_clk_rise - attribute \src "ls180.v:8232.6-8232.29" - case 1'1 - attribute \src "ls180.v:8233.3-8237.6" - switch \main_spisdcard_loopback - attribute \src "ls180.v:8233.7-8233.30" - case 1'1 - assign $0\main_spisdcard_miso_data[7:0] { \main_spisdcard_miso_data [6:0] \spimaster_mosi } - attribute \src "ls180.v:8235.7-8235.11" - case - assign $0\main_spisdcard_miso_data[7:0] { \main_spisdcard_miso_data [6:0] \spimaster_miso } - end - case - end - attribute \src "ls180.v:8239.2-8241.5" - switch \main_spisdcard_miso_latch - attribute \src "ls180.v:8239.6-8239.31" - case 1'1 - assign $0\main_spisdcard_miso[7:0] \main_spisdcard_miso_data - case - end - attribute \src "ls180.v:8243.2-8245.5" - switch \main_spisdcard_count_spimaster1_next_value_ce - attribute \src "ls180.v:8243.6-8243.51" - case 1'1 - assign $0\main_spisdcard_count[2:0] \main_spisdcard_count_spimaster1_next_value - case - end - attribute \src "ls180.v:8246.2-8259.5" - switch \main_pwm0_enable - attribute \src "ls180.v:8246.6-8246.22" - case 1'1 - assign $0\main_pwm0_counter[31:0] $add$ls180.v:8247$2646_Y - attribute \src "ls180.v:8248.3-8252.6" - switch $lt$ls180.v:8248$2647_Y - attribute \src "ls180.v:8248.7-8248.44" - case 1'1 - assign $0\pwm[1:0] [0] 1'1 - attribute \src "ls180.v:8250.7-8250.11" - case - assign $0\pwm[1:0] [0] 1'0 - end - attribute \src "ls180.v:8253.3-8255.6" - switch $ge$ls180.v:8253$2649_Y - attribute \src "ls180.v:8253.7-8253.55" - case 1'1 - assign $0\main_pwm0_counter[31:0] 0 - case - end - attribute \src "ls180.v:8256.6-8256.10" - case - assign $0\main_pwm0_counter[31:0] 0 - assign $0\pwm[1:0] [0] 1'0 - end - attribute \src "ls180.v:8260.2-8273.5" - switch \main_pwm1_enable - attribute \src "ls180.v:8260.6-8260.22" - case 1'1 - assign $0\main_pwm1_counter[31:0] $add$ls180.v:8261$2650_Y - attribute \src "ls180.v:8262.3-8266.6" - switch $lt$ls180.v:8262$2651_Y - attribute \src "ls180.v:8262.7-8262.44" - case 1'1 - assign $0\pwm[1:0] [1] 1'1 - attribute \src "ls180.v:8264.7-8264.11" - case - assign $0\pwm[1:0] [1] 1'0 - end - attribute \src "ls180.v:8267.3-8269.6" - switch $ge$ls180.v:8267$2653_Y - attribute \src "ls180.v:8267.7-8267.55" - case 1'1 - assign $0\main_pwm1_counter[31:0] 0 - case - end - attribute \src "ls180.v:8270.6-8270.10" - case - assign $0\main_pwm1_counter[31:0] 0 - assign $0\pwm[1:0] [1] 1'0 - end - attribute \src "ls180.v:8274.2-8276.5" - switch $not$ls180.v:8274$2654_Y - attribute \src "ls180.v:8274.6-8274.32" - case 1'1 - assign $0\main_sdphy_clocker_clks[8:0] $add$ls180.v:8275$2655_Y - case - end - attribute \src "ls180.v:8280.2-8282.5" - switch \main_sdphy_init_count_sdphy_sdphyinit_next_value_ce - attribute \src "ls180.v:8280.6-8280.57" - case 1'1 - assign $0\main_sdphy_init_count[7:0] \main_sdphy_init_count_sdphy_sdphyinit_next_value - case - end - attribute \src "ls180.v:8284.2-8286.5" - switch \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value_ce - attribute \src "ls180.v:8284.6-8284.57" - case 1'1 - assign $0\main_sdphy_cmdw_count[7:0] \main_sdphy_cmdw_count_sdphy_sdphycmdw_next_value - case - end - attribute \src "ls180.v:8287.2-8289.5" - switch \main_sdphy_cmdr_cmdr_pads_in_valid - attribute \src "ls180.v:8287.6-8287.40" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_run[0:0] $or$ls180.v:8288$2656_Y - case - end - attribute \src "ls180.v:8290.2-8292.5" - switch \main_sdphy_cmdr_cmdr_converter_source_ready - attribute \src "ls180.v:8290.6-8290.49" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 - case - end - attribute \src "ls180.v:8293.2-8300.5" - switch \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:8293.6-8293.46" - case 1'1 - attribute \src "ls180.v:8294.3-8299.6" - switch $or$ls180.v:8294$2658_Y - attribute \src "ls180.v:8294.7-8294.98" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 - assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8297.7-8297.11" - case - assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] $add$ls180.v:8298$2659_Y - end - case - end - attribute \src "ls180.v:8301.2-8314.5" - switch $and$ls180.v:8301$2660_Y - attribute \src "ls180.v:8301.6-8301.97" - case 1'1 - attribute \src "ls180.v:8302.3-8308.6" - switch $and$ls180.v:8302$2661_Y - attribute \src "ls180.v:8302.7-8302.94" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] \main_sdphy_cmdr_cmdr_converter_sink_first - assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] \main_sdphy_cmdr_cmdr_converter_sink_last - attribute \src "ls180.v:8305.7-8305.11" - case - assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] 1'0 - end - attribute \src "ls180.v:8309.6-8309.10" - case - attribute \src "ls180.v:8310.3-8313.6" - switch $and$ls180.v:8310$2662_Y - attribute \src "ls180.v:8310.7-8310.94" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] $or$ls180.v:8311$2663_Y - assign $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] $or$ls180.v:8312$2664_Y - case - end - end - attribute \src "ls180.v:8315.2-8342.5" - switch \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:8315.6-8315.46" - case 1'1 - attribute \src "ls180.v:8316.3-8341.10" - switch \main_sdphy_cmdr_cmdr_converter_demux - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [7] \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [6] \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [5] \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [4] \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [3] \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [2] \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [1] \main_sdphy_cmdr_cmdr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'111 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] [0] \main_sdphy_cmdr_cmdr_converter_sink_payload_data - case - end - case - end - attribute \src "ls180.v:8343.2-8345.5" - switch \main_sdphy_cmdr_cmdr_converter_load_part - attribute \src "ls180.v:8343.6-8343.46" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8344$2665_Y - case - end - attribute \src "ls180.v:8346.2-8351.5" - switch $or$ls180.v:8346$2667_Y - attribute \src "ls180.v:8346.6-8346.88" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] \main_sdphy_cmdr_cmdr_buf_sink_valid - assign $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] \main_sdphy_cmdr_cmdr_buf_sink_first - assign $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] \main_sdphy_cmdr_cmdr_buf_sink_last - assign $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] \main_sdphy_cmdr_cmdr_buf_sink_payload_data - case - end - attribute \src "ls180.v:8352.2-8357.5" - switch \main_sdphy_cmdr_cmdr_reset - attribute \src "ls180.v:8352.6-8352.32" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_run[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 - assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 - case - end - attribute \src "ls180.v:8359.2-8361.5" - switch \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value_ce0 - attribute \src "ls180.v:8359.6-8359.58" - case 1'1 - assign $0\main_sdphy_cmdr_count[7:0] \main_sdphy_cmdr_count_sdphy_sdphycmdr_next_value0 - case - end - attribute \src "ls180.v:8362.2-8364.5" - switch \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 - attribute \src "ls180.v:8362.6-8362.60" - case 1'1 - assign $0\main_sdphy_cmdr_timeout[31:0] \main_sdphy_cmdr_timeout_sdphy_sdphycmdr_next_value1 - case - end - attribute \src "ls180.v:8365.2-8367.5" - switch \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 - attribute \src "ls180.v:8365.6-8365.63" - case 1'1 - assign $0\main_sdphy_cmdr_cmdr_reset[0:0] \main_sdphy_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 - case - end - attribute \src "ls180.v:8368.2-8370.5" - switch \main_sdphy_dataw_crcr_pads_in_valid - attribute \src "ls180.v:8368.6-8368.41" - case 1'1 - assign $0\main_sdphy_dataw_crcr_run[0:0] $or$ls180.v:8369$2668_Y - case - end - attribute \src "ls180.v:8371.2-8373.5" - switch \main_sdphy_dataw_crcr_converter_source_ready - attribute \src "ls180.v:8371.6-8371.50" - case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 - case - end - attribute \src "ls180.v:8374.2-8381.5" - switch \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:8374.6-8374.47" - case 1'1 - attribute \src "ls180.v:8375.3-8380.6" - switch $or$ls180.v:8375$2670_Y - attribute \src "ls180.v:8375.7-8375.100" - case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 - assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8378.7-8378.11" - case - assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] $add$ls180.v:8379$2671_Y - end - case - end - attribute \src "ls180.v:8382.2-8395.5" - switch $and$ls180.v:8382$2672_Y - attribute \src "ls180.v:8382.6-8382.99" - case 1'1 - attribute \src "ls180.v:8383.3-8389.6" - switch $and$ls180.v:8383$2673_Y - attribute \src "ls180.v:8383.7-8383.96" - case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] \main_sdphy_dataw_crcr_converter_sink_first - assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] \main_sdphy_dataw_crcr_converter_sink_last - attribute \src "ls180.v:8386.7-8386.11" - case - assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] 1'0 - end - attribute \src "ls180.v:8390.6-8390.10" - case - attribute \src "ls180.v:8391.3-8394.6" - switch $and$ls180.v:8391$2674_Y - attribute \src "ls180.v:8391.7-8391.96" - case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_source_first[0:0] $or$ls180.v:8392$2675_Y - assign $0\main_sdphy_dataw_crcr_converter_source_last[0:0] $or$ls180.v:8393$2676_Y - case - end - end - attribute \src "ls180.v:8396.2-8423.5" - switch \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:8396.6-8396.47" - case 1'1 - attribute \src "ls180.v:8397.3-8422.10" - switch \main_sdphy_dataw_crcr_converter_demux - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [7] \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [6] \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [5] \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [4] \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [3] \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [2] \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [1] \main_sdphy_dataw_crcr_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'111 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] [0] \main_sdphy_dataw_crcr_converter_sink_payload_data - case - end - case - end - attribute \src "ls180.v:8424.2-8426.5" - switch \main_sdphy_dataw_crcr_converter_load_part - attribute \src "ls180.v:8424.6-8424.47" - case 1'1 - assign $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8425$2677_Y - case - end - attribute \src "ls180.v:8427.2-8432.5" - switch $or$ls180.v:8427$2679_Y - attribute \src "ls180.v:8427.6-8427.90" - case 1'1 - assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] \main_sdphy_dataw_crcr_buf_sink_valid - assign $0\main_sdphy_dataw_crcr_buf_source_first[0:0] \main_sdphy_dataw_crcr_buf_sink_first - assign $0\main_sdphy_dataw_crcr_buf_source_last[0:0] \main_sdphy_dataw_crcr_buf_sink_last - assign $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] \main_sdphy_dataw_crcr_buf_sink_payload_data - case - end - attribute \src "ls180.v:8433.2-8438.5" - switch \main_sdphy_dataw_crcr_reset - attribute \src "ls180.v:8433.6-8433.33" - case 1'1 - assign $0\main_sdphy_dataw_crcr_run[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 - assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 - case - end - attribute \src "ls180.v:8440.2-8442.5" - switch \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce - attribute \src "ls180.v:8440.6-8440.63" - case 1'1 - assign $0\main_sdphy_dataw_crcr_reset[0:0] \main_sdphy_dataw_crcr_reset_sdphy_sdphycrcr_next_value - case - end - attribute \src "ls180.v:8444.2-8446.5" - switch \main_sdphy_dataw_count_sdphy_fsm_next_value_ce - attribute \src "ls180.v:8444.6-8444.52" - case 1'1 - assign $0\main_sdphy_dataw_count[7:0] \main_sdphy_dataw_count_sdphy_fsm_next_value - case - end - attribute \src "ls180.v:8447.2-8449.5" - switch \main_sdphy_datar_datar_pads_in_valid - attribute \src "ls180.v:8447.6-8447.42" - case 1'1 - assign $0\main_sdphy_datar_datar_run[0:0] $or$ls180.v:8448$2680_Y - case - end - attribute \src "ls180.v:8450.2-8452.5" - switch \main_sdphy_datar_datar_converter_source_ready - attribute \src "ls180.v:8450.6-8450.51" - case 1'1 - assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 - case - end - attribute \src "ls180.v:8453.2-8460.5" - switch \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:8453.6-8453.48" - case 1'1 - attribute \src "ls180.v:8454.3-8459.6" - switch $or$ls180.v:8454$2682_Y - attribute \src "ls180.v:8454.7-8454.102" - case 1'1 - assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 - assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8457.7-8457.11" - case - assign $0\main_sdphy_datar_datar_converter_demux[0:0] $add$ls180.v:8458$2683_Y - end - case - end - attribute \src "ls180.v:8461.2-8474.5" - switch $and$ls180.v:8461$2684_Y - attribute \src "ls180.v:8461.6-8461.101" - case 1'1 - attribute \src "ls180.v:8462.3-8468.6" - switch $and$ls180.v:8462$2685_Y - attribute \src "ls180.v:8462.7-8462.98" - case 1'1 - assign $0\main_sdphy_datar_datar_converter_source_first[0:0] \main_sdphy_datar_datar_converter_sink_first - assign $0\main_sdphy_datar_datar_converter_source_last[0:0] \main_sdphy_datar_datar_converter_sink_last - attribute \src "ls180.v:8465.7-8465.11" - case - assign $0\main_sdphy_datar_datar_converter_source_first[0:0] 1'0 - assign $0\main_sdphy_datar_datar_converter_source_last[0:0] 1'0 - end - attribute \src "ls180.v:8469.6-8469.10" - case - attribute \src "ls180.v:8470.3-8473.6" - switch $and$ls180.v:8470$2686_Y - attribute \src "ls180.v:8470.7-8470.98" - case 1'1 - assign $0\main_sdphy_datar_datar_converter_source_first[0:0] $or$ls180.v:8471$2687_Y - assign $0\main_sdphy_datar_datar_converter_source_last[0:0] $or$ls180.v:8472$2688_Y - case - end - end - attribute \src "ls180.v:8475.2-8484.5" - switch \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:8475.6-8475.48" - case 1'1 - attribute \src "ls180.v:8476.3-8483.10" - switch \main_sdphy_datar_datar_converter_demux - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] [7:4] \main_sdphy_datar_datar_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 1'1 - assign $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] [3:0] \main_sdphy_datar_datar_converter_sink_payload_data - case - end - case - end - attribute \src "ls180.v:8485.2-8487.5" - switch \main_sdphy_datar_datar_converter_load_part - attribute \src "ls180.v:8485.6-8485.48" - case 1'1 - assign $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] $add$ls180.v:8486$2689_Y - case - end - attribute \src "ls180.v:8488.2-8493.5" - switch $or$ls180.v:8488$2691_Y - attribute \src "ls180.v:8488.6-8488.92" - case 1'1 - assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] \main_sdphy_datar_datar_buf_sink_valid - assign $0\main_sdphy_datar_datar_buf_source_first[0:0] \main_sdphy_datar_datar_buf_sink_first - assign $0\main_sdphy_datar_datar_buf_source_last[0:0] \main_sdphy_datar_datar_buf_sink_last - assign $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] \main_sdphy_datar_datar_buf_sink_payload_data - case - end - attribute \src "ls180.v:8494.2-8499.5" - switch \main_sdphy_datar_datar_reset - attribute \src "ls180.v:8494.6-8494.34" - case 1'1 - assign $0\main_sdphy_datar_datar_run[0:0] 1'0 - assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 - assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 - assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 - case - end - attribute \src "ls180.v:8501.2-8503.5" - switch \main_sdphy_datar_count_sdphy_sdphydatar_next_value_ce0 - attribute \src "ls180.v:8501.6-8501.60" - case 1'1 - assign $0\main_sdphy_datar_count[9:0] \main_sdphy_datar_count_sdphy_sdphydatar_next_value0 - case - end - attribute \src "ls180.v:8504.2-8506.5" - switch \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value_ce1 - attribute \src "ls180.v:8504.6-8504.62" - case 1'1 - assign $0\main_sdphy_datar_timeout[31:0] \main_sdphy_datar_timeout_sdphy_sdphydatar_next_value1 - case - end - attribute \src "ls180.v:8507.2-8509.5" - switch \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 - attribute \src "ls180.v:8507.6-8507.66" - case 1'1 - assign $0\main_sdphy_datar_datar_reset[0:0] \main_sdphy_datar_datar_reset_sdphy_sdphydatar_next_value2 - case - end - attribute \src "ls180.v:8510.2-8516.5" - switch \main_sdcore_crc7_inserter_clr - attribute \src "ls180.v:8510.6-8510.35" - case 1'1 - assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 - attribute \src "ls180.v:8512.6-8512.10" - case - attribute \src "ls180.v:8513.3-8515.6" - switch \main_sdcore_crc7_inserter_enable - attribute \src "ls180.v:8513.7-8513.39" - case 1'1 - assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] \main_sdcore_crc7_inserter_crcreg40 - case - end - end - attribute \src "ls180.v:8517.2-8523.5" - switch \main_sdcore_crc16_inserter_crc0_clr - attribute \src "ls180.v:8517.6-8517.41" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8519.6-8519.10" - case - attribute \src "ls180.v:8520.3-8522.6" - switch \main_sdcore_crc16_inserter_crc0_enable - attribute \src "ls180.v:8520.7-8520.45" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] \main_sdcore_crc16_inserter_crc0_crcreg2 - case - end - end - attribute \src "ls180.v:8524.2-8530.5" - switch \main_sdcore_crc16_inserter_crc1_clr - attribute \src "ls180.v:8524.6-8524.41" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8526.6-8526.10" - case - attribute \src "ls180.v:8527.3-8529.6" - switch \main_sdcore_crc16_inserter_crc1_enable - attribute \src "ls180.v:8527.7-8527.45" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] \main_sdcore_crc16_inserter_crc1_crcreg2 - case - end - end - attribute \src "ls180.v:8531.2-8537.5" - switch \main_sdcore_crc16_inserter_crc2_clr - attribute \src "ls180.v:8531.6-8531.41" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8533.6-8533.10" - case - attribute \src "ls180.v:8534.3-8536.6" - switch \main_sdcore_crc16_inserter_crc2_enable - attribute \src "ls180.v:8534.7-8534.45" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] \main_sdcore_crc16_inserter_crc2_crcreg2 - case - end - end - attribute \src "ls180.v:8538.2-8544.5" - switch \main_sdcore_crc16_inserter_crc3_clr - attribute \src "ls180.v:8538.6-8538.41" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8540.6-8540.10" - case - attribute \src "ls180.v:8541.3-8543.6" - switch \main_sdcore_crc16_inserter_crc3_enable - attribute \src "ls180.v:8541.7-8541.45" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] \main_sdcore_crc16_inserter_crc3_crcreg2 - case - end - end - attribute \src "ls180.v:8546.2-8548.5" - switch \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 - attribute \src "ls180.v:8546.6-8546.82" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] \main_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 - case - end - attribute \src "ls180.v:8549.2-8551.5" - switch \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 - attribute \src "ls180.v:8549.6-8549.82" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] \main_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 - case - end - attribute \src "ls180.v:8552.2-8554.5" - switch \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 - attribute \src "ls180.v:8552.6-8552.82" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] \main_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 - case - end - attribute \src "ls180.v:8555.2-8557.5" - switch \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 - attribute \src "ls180.v:8555.6-8555.82" - case 1'1 - assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] \main_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 - case - end - attribute \src "ls180.v:8558.2-8560.5" - switch \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 - attribute \src "ls180.v:8558.6-8558.78" - case 1'1 - assign $0\main_sdcore_crc16_inserter_cnt[2:0] \main_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 - case - end - attribute \src "ls180.v:8561.2-8563.5" - switch $and$ls180.v:8561$2692_Y - attribute \src "ls180.v:8561.6-8561.83" - case 1'1 - assign $0\main_sdcore_crc16_checker_crctmp0[15:0] \main_sdcore_crc16_checker_crc0_crc - case - end - attribute \src "ls180.v:8564.2-8566.5" - switch $and$ls180.v:8564$2693_Y - attribute \src "ls180.v:8564.6-8564.83" - case 1'1 - assign $0\main_sdcore_crc16_checker_crctmp1[15:0] \main_sdcore_crc16_checker_crc1_crc - case - end - attribute \src "ls180.v:8567.2-8569.5" - switch $and$ls180.v:8567$2694_Y - attribute \src "ls180.v:8567.6-8567.83" - case 1'1 - assign $0\main_sdcore_crc16_checker_crctmp2[15:0] \main_sdcore_crc16_checker_crc2_crc - case - end - attribute \src "ls180.v:8570.2-8572.5" - switch $and$ls180.v:8570$2695_Y - attribute \src "ls180.v:8570.6-8570.83" - case 1'1 - assign $0\main_sdcore_crc16_checker_crctmp3[15:0] \main_sdcore_crc16_checker_crc3_crc - case - end - attribute \src "ls180.v:8573.2-8577.5" - switch $and$ls180.v:8573$2696_Y - attribute \src "ls180.v:8573.6-8573.83" - case 1'1 - assign $0\main_sdcore_crc16_checker_fifo0[15:0] { \main_sdcore_crc16_checker_fifo0 [13:0] \main_sdcore_crc16_checker_sink_payload_data [7] \main_sdcore_crc16_checker_sink_payload_data [3] } - assign $0\main_sdcore_crc16_checker_val[7:0] [7] \main_sdcore_crc16_checker_fifo0 [13] - assign $0\main_sdcore_crc16_checker_val[7:0] [3] \main_sdcore_crc16_checker_fifo0 [12] - case - end - attribute \src "ls180.v:8578.2-8582.5" - switch $and$ls180.v:8578$2697_Y - attribute \src "ls180.v:8578.6-8578.83" - case 1'1 - assign $0\main_sdcore_crc16_checker_fifo1[15:0] { \main_sdcore_crc16_checker_fifo1 [13:0] \main_sdcore_crc16_checker_sink_payload_data [6] \main_sdcore_crc16_checker_sink_payload_data [2] } - assign $0\main_sdcore_crc16_checker_val[7:0] [6] \main_sdcore_crc16_checker_fifo1 [13] - assign $0\main_sdcore_crc16_checker_val[7:0] [2] \main_sdcore_crc16_checker_fifo1 [12] - case - end - attribute \src "ls180.v:8583.2-8587.5" - switch $and$ls180.v:8583$2698_Y - attribute \src "ls180.v:8583.6-8583.83" - case 1'1 - assign $0\main_sdcore_crc16_checker_fifo2[15:0] { \main_sdcore_crc16_checker_fifo2 [13:0] \main_sdcore_crc16_checker_sink_payload_data [5] \main_sdcore_crc16_checker_sink_payload_data [1] } - assign $0\main_sdcore_crc16_checker_val[7:0] [5] \main_sdcore_crc16_checker_fifo2 [13] - assign $0\main_sdcore_crc16_checker_val[7:0] [1] \main_sdcore_crc16_checker_fifo2 [12] - case - end - attribute \src "ls180.v:8588.2-8592.5" - switch $and$ls180.v:8588$2699_Y - attribute \src "ls180.v:8588.6-8588.83" - case 1'1 - assign $0\main_sdcore_crc16_checker_fifo3[15:0] { \main_sdcore_crc16_checker_fifo3 [13:0] \main_sdcore_crc16_checker_sink_payload_data [4] \main_sdcore_crc16_checker_sink_payload_data [0] } - assign $0\main_sdcore_crc16_checker_val[7:0] [4] \main_sdcore_crc16_checker_fifo3 [13] - assign $0\main_sdcore_crc16_checker_val[7:0] [0] \main_sdcore_crc16_checker_fifo3 [12] - case - end - attribute \src "ls180.v:8593.2-8601.5" - switch $and$ls180.v:8593$2700_Y - attribute \src "ls180.v:8593.6-8593.83" - case 1'1 - attribute \src "ls180.v:8594.3-8600.6" - switch \main_sdcore_crc16_checker_sink_last - attribute \src "ls180.v:8594.7-8594.42" - case 1'1 - assign $0\main_sdcore_crc16_checker_cnt[3:0] 4'0000 - attribute \src "ls180.v:8596.7-8596.11" - case - attribute \src "ls180.v:8597.4-8599.7" - switch $ne$ls180.v:8597$2701_Y - attribute \src "ls180.v:8597.8-8597.48" - case 1'1 - assign $0\main_sdcore_crc16_checker_cnt[3:0] $add$ls180.v:8598$2702_Y - case - end - end - case - end - attribute \src "ls180.v:8602.2-8608.5" - switch \main_sdcore_crc16_checker_crc0_clr - attribute \src "ls180.v:8602.6-8602.40" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8604.6-8604.10" - case - attribute \src "ls180.v:8605.3-8607.6" - switch \main_sdcore_crc16_checker_crc0_enable - attribute \src "ls180.v:8605.7-8605.44" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] \main_sdcore_crc16_checker_crc0_crcreg2 - case - end - end - attribute \src "ls180.v:8609.2-8615.5" - switch \main_sdcore_crc16_checker_crc1_clr - attribute \src "ls180.v:8609.6-8609.40" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8611.6-8611.10" - case - attribute \src "ls180.v:8612.3-8614.6" - switch \main_sdcore_crc16_checker_crc1_enable - attribute \src "ls180.v:8612.7-8612.44" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] \main_sdcore_crc16_checker_crc1_crcreg2 - case - end - end - attribute \src "ls180.v:8616.2-8622.5" - switch \main_sdcore_crc16_checker_crc2_clr - attribute \src "ls180.v:8616.6-8616.40" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8618.6-8618.10" - case - attribute \src "ls180.v:8619.3-8621.6" - switch \main_sdcore_crc16_checker_crc2_enable - attribute \src "ls180.v:8619.7-8619.44" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] \main_sdcore_crc16_checker_crc2_crcreg2 - case - end - end - attribute \src "ls180.v:8623.2-8629.5" - switch \main_sdcore_crc16_checker_crc3_clr - attribute \src "ls180.v:8623.6-8623.40" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 - attribute \src "ls180.v:8625.6-8625.10" - case - attribute \src "ls180.v:8626.3-8628.6" - switch \main_sdcore_crc16_checker_crc3_enable - attribute \src "ls180.v:8626.7-8626.44" - case 1'1 - assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] \main_sdcore_crc16_checker_crc3_crcreg2 - case - end - end - attribute \src "ls180.v:8631.2-8633.5" - switch \main_sdcore_cmd_done_sdcore_fsm_next_value_ce0 - attribute \src "ls180.v:8631.6-8631.52" - case 1'1 - assign $0\main_sdcore_cmd_done[0:0] \main_sdcore_cmd_done_sdcore_fsm_next_value0 - case - end - attribute \src "ls180.v:8634.2-8636.5" - switch \main_sdcore_data_done_sdcore_fsm_next_value_ce1 - attribute \src "ls180.v:8634.6-8634.53" - case 1'1 - assign $0\main_sdcore_data_done[0:0] \main_sdcore_data_done_sdcore_fsm_next_value1 - case - end - attribute \src "ls180.v:8637.2-8639.5" - switch \main_sdcore_cmd_count_sdcore_fsm_next_value_ce2 - attribute \src "ls180.v:8637.6-8637.53" - case 1'1 - assign $0\main_sdcore_cmd_count[2:0] \main_sdcore_cmd_count_sdcore_fsm_next_value2 - case - end - attribute \src "ls180.v:8640.2-8642.5" - switch \main_sdcore_data_count_sdcore_fsm_next_value_ce3 - attribute \src "ls180.v:8640.6-8640.54" - case 1'1 - assign $0\main_sdcore_data_count[31:0] \main_sdcore_data_count_sdcore_fsm_next_value3 - case - end - attribute \src "ls180.v:8643.2-8645.5" - switch \main_sdcore_cmd_error_sdcore_fsm_next_value_ce4 - attribute \src "ls180.v:8643.6-8643.53" - case 1'1 - assign $0\main_sdcore_cmd_error[0:0] \main_sdcore_cmd_error_sdcore_fsm_next_value4 - case - end - attribute \src "ls180.v:8646.2-8648.5" - switch \main_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 - attribute \src "ls180.v:8646.6-8646.55" - case 1'1 - assign $0\main_sdcore_cmd_timeout[0:0] \main_sdcore_cmd_timeout_sdcore_fsm_next_value5 - case - end - attribute \src "ls180.v:8649.2-8651.5" - switch \main_sdcore_data_error_sdcore_fsm_next_value_ce6 - attribute \src "ls180.v:8649.6-8649.54" - case 1'1 - assign $0\main_sdcore_data_error[0:0] \main_sdcore_data_error_sdcore_fsm_next_value6 - case - end - attribute \src "ls180.v:8652.2-8654.5" - switch \main_sdcore_data_timeout_sdcore_fsm_next_value_ce7 - attribute \src "ls180.v:8652.6-8652.56" - case 1'1 - assign $0\main_sdcore_data_timeout[0:0] \main_sdcore_data_timeout_sdcore_fsm_next_value7 - case - end - attribute \src "ls180.v:8655.2-8657.5" - switch \main_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 - attribute \src "ls180.v:8655.6-8655.63" - case 1'1 - assign $0\main_sdcore_cmd_response_status[127:0] \main_sdcore_cmd_response_status_sdcore_fsm_next_value8 - case - end - attribute \src "ls180.v:8658.2-8660.5" - switch $and$ls180.v:8658$2705_Y - attribute \src "ls180.v:8658.6-8658.120" - case 1'1 - assign $0\main_sdblock2mem_fifo_produce[4:0] $add$ls180.v:8659$2706_Y - case - end - attribute \src "ls180.v:8661.2-8663.5" - switch \main_sdblock2mem_fifo_do_read - attribute \src "ls180.v:8661.6-8661.35" - case 1'1 - assign $0\main_sdblock2mem_fifo_consume[4:0] $add$ls180.v:8662$2707_Y - case - end - attribute \src "ls180.v:8664.2-8672.5" - switch $and$ls180.v:8664$2710_Y - attribute \src "ls180.v:8664.6-8664.120" - case 1'1 - attribute \src "ls180.v:8665.3-8667.6" - switch $not$ls180.v:8665$2711_Y - attribute \src "ls180.v:8665.7-8665.39" - case 1'1 - assign $0\main_sdblock2mem_fifo_level[5:0] $add$ls180.v:8666$2712_Y - case - end - attribute \src "ls180.v:8668.6-8668.10" - case - attribute \src "ls180.v:8669.3-8671.6" - switch \main_sdblock2mem_fifo_do_read - attribute \src "ls180.v:8669.7-8669.36" - case 1'1 - assign $0\main_sdblock2mem_fifo_level[5:0] $sub$ls180.v:8670$2713_Y - case - end - end - attribute \src "ls180.v:8673.2-8675.5" - switch \main_sdblock2mem_converter_source_ready - attribute \src "ls180.v:8673.6-8673.45" - case 1'1 - assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'0 - case - end - attribute \src "ls180.v:8676.2-8683.5" - switch \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:8676.6-8676.42" - case 1'1 - attribute \src "ls180.v:8677.3-8682.6" - switch $or$ls180.v:8677$2715_Y - attribute \src "ls180.v:8677.7-8677.90" - case 1'1 - assign $0\main_sdblock2mem_converter_demux[2:0] 3'000 - assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'1 - attribute \src "ls180.v:8680.7-8680.11" - case - assign $0\main_sdblock2mem_converter_demux[2:0] $add$ls180.v:8681$2716_Y - end - case - end - attribute \src "ls180.v:8684.2-8697.5" - switch $and$ls180.v:8684$2717_Y - attribute \src "ls180.v:8684.6-8684.89" - case 1'1 - attribute \src "ls180.v:8685.3-8691.6" - switch $and$ls180.v:8685$2718_Y - attribute \src "ls180.v:8685.7-8685.86" - case 1'1 - assign $0\main_sdblock2mem_converter_source_first[0:0] \main_sdblock2mem_converter_sink_first - assign $0\main_sdblock2mem_converter_source_last[0:0] \main_sdblock2mem_converter_sink_last - attribute \src "ls180.v:8688.7-8688.11" - case - assign $0\main_sdblock2mem_converter_source_first[0:0] 1'0 - assign $0\main_sdblock2mem_converter_source_last[0:0] 1'0 - end - attribute \src "ls180.v:8692.6-8692.10" - case - attribute \src "ls180.v:8693.3-8696.6" - switch $and$ls180.v:8693$2719_Y - attribute \src "ls180.v:8693.7-8693.86" - case 1'1 - assign $0\main_sdblock2mem_converter_source_first[0:0] $or$ls180.v:8694$2720_Y - assign $0\main_sdblock2mem_converter_source_last[0:0] $or$ls180.v:8695$2721_Y - case - end - end - attribute \src "ls180.v:8698.2-8725.5" - switch \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:8698.6-8698.42" - case 1'1 - attribute \src "ls180.v:8699.3-8724.10" - switch \main_sdblock2mem_converter_demux - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [63:56] \main_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [55:48] \main_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [47:40] \main_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [39:32] \main_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [31:24] \main_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [23:16] \main_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [15:8] \main_sdblock2mem_converter_sink_payload_data - attribute \src "ls180.v:0.0-0.0" - case 3'111 - assign $0\main_sdblock2mem_converter_source_payload_data[63:0] [7:0] \main_sdblock2mem_converter_sink_payload_data - case - end - case - end - attribute \src "ls180.v:8726.2-8728.5" - switch \main_sdblock2mem_converter_load_part - attribute \src "ls180.v:8726.6-8726.42" + attribute \src "ls180.v:4881.2-4885.5" + switch \uart_phy_rx_busy + attribute \src "ls180.v:4881.6-4881.22" case 1'1 - assign $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] $add$ls180.v:8727$2722_Y + assign { $0\uart_phy_uart_clk_rxen[0:0] $0\uart_phy_phase_accumulator_rx[31:0] } $add$ls180.v:4882$1427_Y + attribute \src "ls180.v:4883.6-4883.10" case + assign { $0\uart_phy_uart_clk_rxen[0:0] $0\uart_phy_phase_accumulator_rx[31:0] } 33'010000000000000000000000000000000 end - attribute \src "ls180.v:8730.2-8732.5" - switch \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce - attribute \src "ls180.v:8730.6-8730.76" + attribute \src "ls180.v:4886.2-4888.5" + switch \tx_clear + attribute \src "ls180.v:4886.6-4886.14" case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] \main_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value + assign $0\tx_pending[0:0] 1'0 case end - attribute \src "ls180.v:8733.2-8736.5" - switch \main_sdblock2mem_wishbonedmawriter_reset - attribute \src "ls180.v:8733.6-8733.46" + attribute \src "ls180.v:4890.2-4892.5" + switch $and$ls180.v:4890$1429_Y + attribute \src "ls180.v:4890.6-4890.38" case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 - assign $0\builder_sdblock2memdma_state[1:0] 2'00 + assign $0\tx_pending[0:0] 1'1 case end - attribute \src "ls180.v:8738.2-8740.5" - switch \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce - attribute \src "ls180.v:8738.6-8738.64" + attribute \src "ls180.v:4893.2-4895.5" + switch \rx_clear + attribute \src "ls180.v:4893.6-4893.14" case 1'1 - assign $0\main_sdmem2block_dma_data[63:0] \main_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value + assign $0\rx_pending[0:0] 1'0 case end - attribute \src "ls180.v:8742.2-8744.5" - switch \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce - attribute \src "ls180.v:8742.6-8742.76" + attribute \src "ls180.v:4897.2-4899.5" + switch $and$ls180.v:4897$1431_Y + attribute \src "ls180.v:4897.6-4897.38" case 1'1 - assign $0\main_sdmem2block_dma_offset[31:0] \main_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value + assign $0\rx_pending[0:0] 1'1 case end - attribute \src "ls180.v:8745.2-8748.5" - switch \main_sdmem2block_dma_reset - attribute \src "ls180.v:8745.6-8745.32" + attribute \src "ls180.v:4900.2-4906.5" + switch \tx_fifo_syncfifo_re + attribute \src "ls180.v:4900.6-4900.25" case 1'1 - assign $0\main_sdmem2block_dma_offset[31:0] 0 - assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 + assign $0\tx_fifo_readable[0:0] 1'1 + attribute \src "ls180.v:4902.6-4902.10" case - end - attribute \src "ls180.v:8749.2-8755.5" - switch $and$ls180.v:8749$2723_Y - attribute \src "ls180.v:8749.6-8749.89" - case 1'1 - attribute \src "ls180.v:8750.3-8754.6" - switch \main_sdmem2block_converter_last - attribute \src "ls180.v:8750.7-8750.38" + attribute \src "ls180.v:4903.3-4905.6" + switch \tx_fifo_re + attribute \src "ls180.v:4903.7-4903.17" case 1'1 - assign $0\main_sdmem2block_converter_mux[2:0] 3'000 - attribute \src "ls180.v:8752.7-8752.11" + assign $0\tx_fifo_readable[0:0] 1'0 case - assign $0\main_sdmem2block_converter_mux[2:0] $add$ls180.v:8753$2724_Y end - case end - attribute \src "ls180.v:8756.2-8758.5" - switch $and$ls180.v:8756$2727_Y - attribute \src "ls180.v:8756.6-8756.120" + attribute \src "ls180.v:4907.2-4909.5" + switch $and$ls180.v:4907$1434_Y + attribute \src "ls180.v:4907.6-4907.78" case 1'1 - assign $0\main_sdmem2block_fifo_produce[4:0] $add$ls180.v:8757$2728_Y + assign $0\tx_fifo_produce[3:0] $add$ls180.v:4908$1435_Y case end - attribute \src "ls180.v:8759.2-8761.5" - switch \main_sdmem2block_fifo_do_read - attribute \src "ls180.v:8759.6-8759.35" + attribute \src "ls180.v:4910.2-4912.5" + switch \tx_fifo_do_read + attribute \src "ls180.v:4910.6-4910.21" case 1'1 - assign $0\main_sdmem2block_fifo_consume[4:0] $add$ls180.v:8760$2729_Y + assign $0\tx_fifo_consume[3:0] $add$ls180.v:4911$1436_Y case end - attribute \src "ls180.v:8762.2-8770.5" - switch $and$ls180.v:8762$2732_Y - attribute \src "ls180.v:8762.6-8762.120" + attribute \src "ls180.v:4913.2-4921.5" + switch $and$ls180.v:4913$1439_Y + attribute \src "ls180.v:4913.6-4913.78" case 1'1 - attribute \src "ls180.v:8763.3-8765.6" - switch $not$ls180.v:8763$2733_Y - attribute \src "ls180.v:8763.7-8763.39" + attribute \src "ls180.v:4914.3-4916.6" + switch $not$ls180.v:4914$1440_Y + attribute \src "ls180.v:4914.7-4914.25" case 1'1 - assign $0\main_sdmem2block_fifo_level[5:0] $add$ls180.v:8764$2734_Y + assign $0\tx_fifo_level0[4:0] $add$ls180.v:4915$1441_Y case end - attribute \src "ls180.v:8766.6-8766.10" + attribute \src "ls180.v:4917.6-4917.10" case - attribute \src "ls180.v:8767.3-8769.6" - switch \main_sdmem2block_fifo_do_read - attribute \src "ls180.v:8767.7-8767.36" + attribute \src "ls180.v:4918.3-4920.6" + switch \tx_fifo_do_read + attribute \src "ls180.v:4918.7-4918.22" case 1'1 - assign $0\main_sdmem2block_fifo_level[5:0] $sub$ls180.v:8768$2735_Y + assign $0\tx_fifo_level0[4:0] $sub$ls180.v:4919$1442_Y case end end - attribute \src "ls180.v:8772.2-8774.5" - switch \builder_libresocsim_dat_w_next_value_ce0 - attribute \src "ls180.v:8772.6-8772.46" - case 1'1 - assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w_next_value0 - case - end - attribute \src "ls180.v:8775.2-8777.5" - switch \builder_libresocsim_adr_next_value_ce1 - attribute \src "ls180.v:8775.6-8775.44" - case 1'1 - assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr_next_value1 - case - end - attribute \src "ls180.v:8778.2-8780.5" - switch \builder_libresocsim_we_next_value_ce2 - attribute \src "ls180.v:8778.6-8778.43" + attribute \src "ls180.v:4922.2-4928.5" + switch \rx_fifo_syncfifo_re + attribute \src "ls180.v:4922.6-4922.25" case 1'1 - assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we_next_value2 - case - end - attribute \src "ls180.v:8781.2-8877.9" - switch \builder_grant - attribute \src "ls180.v:0.0-0.0" - case 3'000 - attribute \src "ls180.v:8783.4-8799.7" - switch $not$ls180.v:8783$2736_Y - attribute \src "ls180.v:8783.8-8783.29" - case 1'1 - attribute \src "ls180.v:8784.5-8798.8" - switch \builder_request [1] - attribute \src "ls180.v:8784.9-8784.27" - case 1'1 - assign $0\builder_grant[2:0] 3'001 - attribute \src "ls180.v:8786.9-8786.13" - case - attribute \src "ls180.v:8787.6-8797.9" - switch \builder_request [2] - attribute \src "ls180.v:8787.10-8787.28" - case 1'1 - assign $0\builder_grant[2:0] 3'010 - attribute \src "ls180.v:8789.10-8789.14" - case - attribute \src "ls180.v:8790.7-8796.10" - switch \builder_request [3] - attribute \src "ls180.v:8790.11-8790.29" - case 1'1 - assign $0\builder_grant[2:0] 3'011 - attribute \src "ls180.v:8792.11-8792.15" - case - attribute \src "ls180.v:8793.8-8795.11" - switch \builder_request [4] - attribute \src "ls180.v:8793.12-8793.30" - case 1'1 - assign $0\builder_grant[2:0] 3'100 - case - end - end - end - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'001 - attribute \src "ls180.v:8802.4-8818.7" - switch $not$ls180.v:8802$2737_Y - attribute \src "ls180.v:8802.8-8802.29" - case 1'1 - attribute \src "ls180.v:8803.5-8817.8" - switch \builder_request [2] - attribute \src "ls180.v:8803.9-8803.27" - case 1'1 - assign $0\builder_grant[2:0] 3'010 - attribute \src "ls180.v:8805.9-8805.13" - case - attribute \src "ls180.v:8806.6-8816.9" - switch \builder_request [3] - attribute \src "ls180.v:8806.10-8806.28" - case 1'1 - assign $0\builder_grant[2:0] 3'011 - attribute \src "ls180.v:8808.10-8808.14" - case - attribute \src "ls180.v:8809.7-8815.10" - switch \builder_request [4] - attribute \src "ls180.v:8809.11-8809.29" - case 1'1 - assign $0\builder_grant[2:0] 3'100 - attribute \src "ls180.v:8811.11-8811.15" - case - attribute \src "ls180.v:8812.8-8814.11" - switch \builder_request [0] - attribute \src "ls180.v:8812.12-8812.30" - case 1'1 - assign $0\builder_grant[2:0] 3'000 - case - end - end - end - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'010 - attribute \src "ls180.v:8821.4-8837.7" - switch $not$ls180.v:8821$2738_Y - attribute \src "ls180.v:8821.8-8821.29" - case 1'1 - attribute \src "ls180.v:8822.5-8836.8" - switch \builder_request [3] - attribute \src "ls180.v:8822.9-8822.27" - case 1'1 - assign $0\builder_grant[2:0] 3'011 - attribute \src "ls180.v:8824.9-8824.13" - case - attribute \src "ls180.v:8825.6-8835.9" - switch \builder_request [4] - attribute \src "ls180.v:8825.10-8825.28" - case 1'1 - assign $0\builder_grant[2:0] 3'100 - attribute \src "ls180.v:8827.10-8827.14" - case - attribute \src "ls180.v:8828.7-8834.10" - switch \builder_request [0] - attribute \src "ls180.v:8828.11-8828.29" - case 1'1 - assign $0\builder_grant[2:0] 3'000 - attribute \src "ls180.v:8830.11-8830.15" - case - attribute \src "ls180.v:8831.8-8833.11" - switch \builder_request [1] - attribute \src "ls180.v:8831.12-8831.30" - case 1'1 - assign $0\builder_grant[2:0] 3'001 - case - end - end - end - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'011 - attribute \src "ls180.v:8840.4-8856.7" - switch $not$ls180.v:8840$2739_Y - attribute \src "ls180.v:8840.8-8840.29" - case 1'1 - attribute \src "ls180.v:8841.5-8855.8" - switch \builder_request [4] - attribute \src "ls180.v:8841.9-8841.27" - case 1'1 - assign $0\builder_grant[2:0] 3'100 - attribute \src "ls180.v:8843.9-8843.13" - case - attribute \src "ls180.v:8844.6-8854.9" - switch \builder_request [0] - attribute \src "ls180.v:8844.10-8844.28" - case 1'1 - assign $0\builder_grant[2:0] 3'000 - attribute \src "ls180.v:8846.10-8846.14" - case - attribute \src "ls180.v:8847.7-8853.10" - switch \builder_request [1] - attribute \src "ls180.v:8847.11-8847.29" - case 1'1 - assign $0\builder_grant[2:0] 3'001 - attribute \src "ls180.v:8849.11-8849.15" - case - attribute \src "ls180.v:8850.8-8852.11" - switch \builder_request [2] - attribute \src "ls180.v:8850.12-8850.30" - case 1'1 - assign $0\builder_grant[2:0] 3'010 - case - end - end - end - end - case - end - attribute \src "ls180.v:0.0-0.0" - case 3'100 - attribute \src "ls180.v:8859.4-8875.7" - switch $not$ls180.v:8859$2740_Y - attribute \src "ls180.v:8859.8-8859.29" - case 1'1 - attribute \src "ls180.v:8860.5-8874.8" - switch \builder_request [0] - attribute \src "ls180.v:8860.9-8860.27" - case 1'1 - assign $0\builder_grant[2:0] 3'000 - attribute \src "ls180.v:8862.9-8862.13" - case - attribute \src "ls180.v:8863.6-8873.9" - switch \builder_request [1] - attribute \src "ls180.v:8863.10-8863.28" - case 1'1 - assign $0\builder_grant[2:0] 3'001 - attribute \src "ls180.v:8865.10-8865.14" - case - attribute \src "ls180.v:8866.7-8872.10" - switch \builder_request [2] - attribute \src "ls180.v:8866.11-8866.29" - case 1'1 - assign $0\builder_grant[2:0] 3'010 - attribute \src "ls180.v:8868.11-8868.15" - case - attribute \src "ls180.v:8869.8-8871.11" - switch \builder_request [3] - attribute \src "ls180.v:8869.12-8869.30" - case 1'1 - assign $0\builder_grant[2:0] 3'011 - case - end - end - end - end - case - end + assign $0\rx_fifo_readable[0:0] 1'1 + attribute \src "ls180.v:4924.6-4924.10" case - end - attribute \src "ls180.v:8879.2-8885.5" - switch \builder_wait - attribute \src "ls180.v:8879.6-8879.18" - case 1'1 - attribute \src "ls180.v:8880.3-8882.6" - switch $not$ls180.v:8880$2741_Y - attribute \src "ls180.v:8880.7-8880.22" + attribute \src "ls180.v:4925.3-4927.6" + switch \rx_fifo_re + attribute \src "ls180.v:4925.7-4925.17" case 1'1 - assign $0\builder_count[19:0] $sub$ls180.v:8881$2742_Y - case - end - attribute \src "ls180.v:8883.6-8883.10" - case - assign $0\builder_count[19:0] 20'11110100001001000000 - end - attribute \src "ls180.v:8887.2-8917.5" - switch \builder_csrbank0_sel - attribute \src "ls180.v:8887.6-8887.26" - case 1'1 - attribute \src "ls180.v:8888.3-8916.10" - switch \builder_interface0_bank_bus_adr [3:0] - attribute \src "ls180.v:0.0-0.0" - case 4'0000 - assign $0\builder_interface0_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank0_reset0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0001 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch3_w - attribute \src "ls180.v:0.0-0.0" - case 4'0010 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch2_w - attribute \src "ls180.v:0.0-0.0" - case 4'0011 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch1_w - attribute \src "ls180.v:0.0-0.0" - case 4'0100 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch0_w - attribute \src "ls180.v:0.0-0.0" - case 4'0101 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors3_w - attribute \src "ls180.v:0.0-0.0" - case 4'0110 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors2_w - attribute \src "ls180.v:0.0-0.0" - case 4'0111 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors1_w - attribute \src "ls180.v:0.0-0.0" - case 4'1000 - assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors0_w - case - end - case - end - attribute \src "ls180.v:8918.2-8920.5" - switch \builder_csrbank0_reset0_re - attribute \src "ls180.v:8918.6-8918.32" - case 1'1 - assign $0\main_libresocsim_reset_storage[0:0] \builder_csrbank0_reset0_r - case - end - attribute \src "ls180.v:8922.2-8924.5" - switch \builder_csrbank0_scratch3_re - attribute \src "ls180.v:8922.6-8922.34" - case 1'1 - assign $0\main_libresocsim_scratch_storage[31:0] [31:24] \builder_csrbank0_scratch3_r - case - end - attribute \src "ls180.v:8925.2-8927.5" - switch \builder_csrbank0_scratch2_re - attribute \src "ls180.v:8925.6-8925.34" - case 1'1 - assign $0\main_libresocsim_scratch_storage[31:0] [23:16] \builder_csrbank0_scratch2_r - case - end - attribute \src "ls180.v:8928.2-8930.5" - switch \builder_csrbank0_scratch1_re - attribute \src "ls180.v:8928.6-8928.34" - case 1'1 - assign $0\main_libresocsim_scratch_storage[31:0] [15:8] \builder_csrbank0_scratch1_r - case - end - attribute \src "ls180.v:8931.2-8933.5" - switch \builder_csrbank0_scratch0_re - attribute \src "ls180.v:8931.6-8931.34" - case 1'1 - assign $0\main_libresocsim_scratch_storage[31:0] [7:0] \builder_csrbank0_scratch0_r - case - end - attribute \src "ls180.v:8936.2-8957.5" - switch \builder_csrbank1_sel - attribute \src "ls180.v:8936.6-8936.26" - case 1'1 - attribute \src "ls180.v:8937.3-8956.10" - switch \builder_interface1_bank_bus_adr [2:0] - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_oe1_w - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_oe0_w - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_in1_w - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_in0_w - attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_out1_w - attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_out0_w + assign $0\rx_fifo_readable[0:0] 1'0 case end - case - end - attribute \src "ls180.v:8958.2-8960.5" - switch \builder_csrbank1_oe1_re - attribute \src "ls180.v:8958.6-8958.29" - case 1'1 - assign $0\main_gpiotristateasic1_oe_storage[15:0] [15:8] \builder_csrbank1_oe1_r - case - end - attribute \src "ls180.v:8961.2-8963.5" - switch \builder_csrbank1_oe0_re - attribute \src "ls180.v:8961.6-8961.29" - case 1'1 - assign $0\main_gpiotristateasic1_oe_storage[15:0] [7:0] \builder_csrbank1_oe0_r - case end - attribute \src "ls180.v:8965.2-8967.5" - switch \builder_csrbank1_out1_re - attribute \src "ls180.v:8965.6-8965.30" + attribute \src "ls180.v:4929.2-4931.5" + switch $and$ls180.v:4929$1445_Y + attribute \src "ls180.v:4929.6-4929.78" case 1'1 - assign $0\main_gpiotristateasic1_out_storage[15:0] [15:8] \builder_csrbank1_out1_r + assign $0\rx_fifo_produce[3:0] $add$ls180.v:4930$1446_Y case end - attribute \src "ls180.v:8968.2-8970.5" - switch \builder_csrbank1_out0_re - attribute \src "ls180.v:8968.6-8968.30" + attribute \src "ls180.v:4932.2-4934.5" + switch \rx_fifo_do_read + attribute \src "ls180.v:4932.6-4932.21" case 1'1 - assign $0\main_gpiotristateasic1_out_storage[15:0] [7:0] \builder_csrbank1_out0_r + assign $0\rx_fifo_consume[3:0] $add$ls180.v:4933$1447_Y case end - attribute \src "ls180.v:8973.2-8982.5" - switch \builder_csrbank2_sel - attribute \src "ls180.v:8973.6-8973.26" + attribute \src "ls180.v:4935.2-4943.5" + switch $and$ls180.v:4935$1450_Y + attribute \src "ls180.v:4935.6-4935.78" case 1'1 - attribute \src "ls180.v:8974.3-8981.10" - switch \builder_interface2_bank_bus_adr [0] - attribute \src "ls180.v:0.0-0.0" - case 1'0 - assign $0\builder_interface2_bank_bus_dat_r[7:0] { 5'00000 \builder_csrbank2_w0_w } - attribute \src "ls180.v:0.0-0.0" + attribute \src "ls180.v:4936.3-4938.6" + switch $not$ls180.v:4936$1451_Y + attribute \src "ls180.v:4936.7-4936.25" case 1'1 - assign $0\builder_interface2_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank2_r_w } - case - end - case - end - attribute \src "ls180.v:8983.2-8985.5" - switch \builder_csrbank2_w0_re - attribute \src "ls180.v:8983.6-8983.28" - case 1'1 - assign $0\main_i2c_storage[2:0] \builder_csrbank2_w0_r - case - end - attribute \src "ls180.v:8988.2-9018.5" - switch \builder_csrbank3_sel - attribute \src "ls180.v:8988.6-8988.26" - case 1'1 - attribute \src "ls180.v:8989.3-9017.10" - switch \builder_interface3_bank_bus_adr [3:0] - attribute \src "ls180.v:0.0-0.0" - case 4'0000 - assign $0\builder_interface3_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank3_enable0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0001 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width3_w - attribute \src "ls180.v:0.0-0.0" - case 4'0010 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width2_w - attribute \src "ls180.v:0.0-0.0" - case 4'0011 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width1_w - attribute \src "ls180.v:0.0-0.0" - case 4'0100 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_width0_w - attribute \src "ls180.v:0.0-0.0" - case 4'0101 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period3_w - attribute \src "ls180.v:0.0-0.0" - case 4'0110 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period2_w - attribute \src "ls180.v:0.0-0.0" - case 4'0111 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period1_w - attribute \src "ls180.v:0.0-0.0" - case 4'1000 - assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_period0_w - case - end - case - end - attribute \src "ls180.v:9019.2-9021.5" - switch \builder_csrbank3_enable0_re - attribute \src "ls180.v:9019.6-9019.33" - case 1'1 - assign $0\main_pwm0_enable_storage[0:0] \builder_csrbank3_enable0_r - case - end - attribute \src "ls180.v:9023.2-9025.5" - switch \builder_csrbank3_width3_re - attribute \src "ls180.v:9023.6-9023.32" - case 1'1 - assign $0\main_pwm0_width_storage[31:0] [31:24] \builder_csrbank3_width3_r - case - end - attribute \src "ls180.v:9026.2-9028.5" - switch \builder_csrbank3_width2_re - attribute \src "ls180.v:9026.6-9026.32" - case 1'1 - assign $0\main_pwm0_width_storage[31:0] [23:16] \builder_csrbank3_width2_r - case - end - attribute \src "ls180.v:9029.2-9031.5" - switch \builder_csrbank3_width1_re - attribute \src "ls180.v:9029.6-9029.32" - case 1'1 - assign $0\main_pwm0_width_storage[31:0] [15:8] \builder_csrbank3_width1_r - case - end - attribute \src "ls180.v:9032.2-9034.5" - switch \builder_csrbank3_width0_re - attribute \src "ls180.v:9032.6-9032.32" - case 1'1 - assign $0\main_pwm0_width_storage[31:0] [7:0] \builder_csrbank3_width0_r - case - end - attribute \src "ls180.v:9036.2-9038.5" - switch \builder_csrbank3_period3_re - attribute \src "ls180.v:9036.6-9036.33" - case 1'1 - assign $0\main_pwm0_period_storage[31:0] [31:24] \builder_csrbank3_period3_r - case - end - attribute \src "ls180.v:9039.2-9041.5" - switch \builder_csrbank3_period2_re - attribute \src "ls180.v:9039.6-9039.33" - case 1'1 - assign $0\main_pwm0_period_storage[31:0] [23:16] \builder_csrbank3_period2_r - case - end - attribute \src "ls180.v:9042.2-9044.5" - switch \builder_csrbank3_period1_re - attribute \src "ls180.v:9042.6-9042.33" - case 1'1 - assign $0\main_pwm0_period_storage[31:0] [15:8] \builder_csrbank3_period1_r - case - end - attribute \src "ls180.v:9045.2-9047.5" - switch \builder_csrbank3_period0_re - attribute \src "ls180.v:9045.6-9045.33" - case 1'1 - assign $0\main_pwm0_period_storage[31:0] [7:0] \builder_csrbank3_period0_r - case - end - attribute \src "ls180.v:9050.2-9080.5" - switch \builder_csrbank4_sel - attribute \src "ls180.v:9050.6-9050.26" - case 1'1 - attribute \src "ls180.v:9051.3-9079.10" - switch \builder_interface4_bank_bus_adr [3:0] - attribute \src "ls180.v:0.0-0.0" - case 4'0000 - assign $0\builder_interface4_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank4_enable0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'0001 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width3_w - attribute \src "ls180.v:0.0-0.0" - case 4'0010 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width2_w - attribute \src "ls180.v:0.0-0.0" - case 4'0011 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width1_w - attribute \src "ls180.v:0.0-0.0" - case 4'0100 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_width0_w - attribute \src "ls180.v:0.0-0.0" - case 4'0101 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period3_w - attribute \src "ls180.v:0.0-0.0" - case 4'0110 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period2_w - attribute \src "ls180.v:0.0-0.0" - case 4'0111 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period1_w - attribute \src "ls180.v:0.0-0.0" - case 4'1000 - assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_period0_w - case - end - case - end - attribute \src "ls180.v:9081.2-9083.5" - switch \builder_csrbank4_enable0_re - attribute \src "ls180.v:9081.6-9081.33" - case 1'1 - assign $0\main_pwm1_enable_storage[0:0] \builder_csrbank4_enable0_r - case - end - attribute \src "ls180.v:9085.2-9087.5" - switch \builder_csrbank4_width3_re - attribute \src "ls180.v:9085.6-9085.32" - case 1'1 - assign $0\main_pwm1_width_storage[31:0] [31:24] \builder_csrbank4_width3_r - case - end - attribute \src "ls180.v:9088.2-9090.5" - switch \builder_csrbank4_width2_re - attribute \src "ls180.v:9088.6-9088.32" - case 1'1 - assign $0\main_pwm1_width_storage[31:0] [23:16] \builder_csrbank4_width2_r - case - end - attribute \src "ls180.v:9091.2-9093.5" - switch \builder_csrbank4_width1_re - attribute \src "ls180.v:9091.6-9091.32" - case 1'1 - assign $0\main_pwm1_width_storage[31:0] [15:8] \builder_csrbank4_width1_r - case - end - attribute \src "ls180.v:9094.2-9096.5" - switch \builder_csrbank4_width0_re - attribute \src "ls180.v:9094.6-9094.32" - case 1'1 - assign $0\main_pwm1_width_storage[31:0] [7:0] \builder_csrbank4_width0_r - case - end - attribute \src "ls180.v:9098.2-9100.5" - switch \builder_csrbank4_period3_re - attribute \src "ls180.v:9098.6-9098.33" - case 1'1 - assign $0\main_pwm1_period_storage[31:0] [31:24] \builder_csrbank4_period3_r - case - end - attribute \src "ls180.v:9101.2-9103.5" - switch \builder_csrbank4_period2_re - attribute \src "ls180.v:9101.6-9101.33" - case 1'1 - assign $0\main_pwm1_period_storage[31:0] [23:16] \builder_csrbank4_period2_r - case - end - attribute \src "ls180.v:9104.2-9106.5" - switch \builder_csrbank4_period1_re - attribute \src "ls180.v:9104.6-9104.33" - case 1'1 - assign $0\main_pwm1_period_storage[31:0] [15:8] \builder_csrbank4_period1_r - case - end - attribute \src "ls180.v:9107.2-9109.5" - switch \builder_csrbank4_period0_re - attribute \src "ls180.v:9107.6-9107.33" - case 1'1 - assign $0\main_pwm1_period_storage[31:0] [7:0] \builder_csrbank4_period0_r - case - end - attribute \src "ls180.v:9112.2-9160.5" - switch \builder_csrbank5_sel - attribute \src "ls180.v:9112.6-9112.26" - case 1'1 - attribute \src "ls180.v:9113.3-9159.10" - switch \builder_interface5_bank_bus_adr [3:0] - attribute \src "ls180.v:0.0-0.0" - case 4'0000 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base7_w - attribute \src "ls180.v:0.0-0.0" - case 4'0001 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base6_w - attribute \src "ls180.v:0.0-0.0" - case 4'0010 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base5_w - attribute \src "ls180.v:0.0-0.0" - case 4'0011 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base4_w - attribute \src "ls180.v:0.0-0.0" - case 4'0100 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base3_w - attribute \src "ls180.v:0.0-0.0" - case 4'0101 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base2_w - attribute \src "ls180.v:0.0-0.0" - case 4'0110 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base1_w - attribute \src "ls180.v:0.0-0.0" - case 4'0111 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base0_w - attribute \src "ls180.v:0.0-0.0" - case 4'1000 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length3_w - attribute \src "ls180.v:0.0-0.0" - case 4'1001 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length2_w - attribute \src "ls180.v:0.0-0.0" - case 4'1010 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length1_w - attribute \src "ls180.v:0.0-0.0" - case 4'1011 - assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length0_w - attribute \src "ls180.v:0.0-0.0" - case 4'1100 - assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_enable0_w } - attribute \src "ls180.v:0.0-0.0" - case 4'1101 - assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_done_w } - attribute \src "ls180.v:0.0-0.0" - case 4'1110 - assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_loop0_w } - case - end - case - end - attribute \src "ls180.v:9161.2-9163.5" - switch \builder_csrbank5_dma_base7_re - attribute \src "ls180.v:9161.6-9161.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [63:56] \builder_csrbank5_dma_base7_r - case - end - attribute \src "ls180.v:9164.2-9166.5" - switch \builder_csrbank5_dma_base6_re - attribute \src "ls180.v:9164.6-9164.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [55:48] \builder_csrbank5_dma_base6_r - case - end - attribute \src "ls180.v:9167.2-9169.5" - switch \builder_csrbank5_dma_base5_re - attribute \src "ls180.v:9167.6-9167.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [47:40] \builder_csrbank5_dma_base5_r - case - end - attribute \src "ls180.v:9170.2-9172.5" - switch \builder_csrbank5_dma_base4_re - attribute \src "ls180.v:9170.6-9170.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [39:32] \builder_csrbank5_dma_base4_r - case - end - attribute \src "ls180.v:9173.2-9175.5" - switch \builder_csrbank5_dma_base3_re - attribute \src "ls180.v:9173.6-9173.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [31:24] \builder_csrbank5_dma_base3_r - case - end - attribute \src "ls180.v:9176.2-9178.5" - switch \builder_csrbank5_dma_base2_re - attribute \src "ls180.v:9176.6-9176.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [23:16] \builder_csrbank5_dma_base2_r - case - end - attribute \src "ls180.v:9179.2-9181.5" - switch \builder_csrbank5_dma_base1_re - attribute \src "ls180.v:9179.6-9179.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [15:8] \builder_csrbank5_dma_base1_r - case - end - attribute \src "ls180.v:9182.2-9184.5" - switch \builder_csrbank5_dma_base0_re - attribute \src "ls180.v:9182.6-9182.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] [7:0] \builder_csrbank5_dma_base0_r - case - end - attribute \src "ls180.v:9186.2-9188.5" - switch \builder_csrbank5_dma_length3_re - attribute \src "ls180.v:9186.6-9186.37" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [31:24] \builder_csrbank5_dma_length3_r - case - end - attribute \src "ls180.v:9189.2-9191.5" - switch \builder_csrbank5_dma_length2_re - attribute \src "ls180.v:9189.6-9189.37" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [23:16] \builder_csrbank5_dma_length2_r - case - end - attribute \src "ls180.v:9192.2-9194.5" - switch \builder_csrbank5_dma_length1_re - attribute \src "ls180.v:9192.6-9192.37" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [15:8] \builder_csrbank5_dma_length1_r - case - end - attribute \src "ls180.v:9195.2-9197.5" - switch \builder_csrbank5_dma_length0_re - attribute \src "ls180.v:9195.6-9195.37" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] [7:0] \builder_csrbank5_dma_length0_r - case - end - attribute \src "ls180.v:9199.2-9201.5" - switch \builder_csrbank5_dma_enable0_re - attribute \src "ls180.v:9199.6-9199.37" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \builder_csrbank5_dma_enable0_r - case - end - attribute \src "ls180.v:9203.2-9205.5" - switch \builder_csrbank5_dma_loop0_re - attribute \src "ls180.v:9203.6-9203.35" - case 1'1 - assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \builder_csrbank5_dma_loop0_r - case - end - attribute \src "ls180.v:9208.2-9310.5" - switch \builder_csrbank6_sel - attribute \src "ls180.v:9208.6-9208.26" - case 1'1 - attribute \src "ls180.v:9209.3-9309.10" - switch \builder_interface6_bank_bus_adr [5:0] - attribute \src "ls180.v:0.0-0.0" - case 6'000000 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument3_w - attribute \src "ls180.v:0.0-0.0" - case 6'000001 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument2_w - attribute \src "ls180.v:0.0-0.0" - case 6'000010 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument1_w - attribute \src "ls180.v:0.0-0.0" - case 6'000011 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_argument0_w - attribute \src "ls180.v:0.0-0.0" - case 6'000100 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command3_w - attribute \src "ls180.v:0.0-0.0" - case 6'000101 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command2_w - attribute \src "ls180.v:0.0-0.0" - case 6'000110 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command1_w - attribute \src "ls180.v:0.0-0.0" - case 6'000111 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_command0_w - attribute \src "ls180.v:0.0-0.0" - case 6'001000 - assign $0\builder_interface6_bank_bus_dat_r[7:0] { 7'0000000 \main_sdcore_cmd_send_w } - attribute \src "ls180.v:0.0-0.0" - case 6'001001 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response15_w - attribute \src "ls180.v:0.0-0.0" - case 6'001010 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response14_w - attribute \src "ls180.v:0.0-0.0" - case 6'001011 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response13_w - attribute \src "ls180.v:0.0-0.0" - case 6'001100 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response12_w - attribute \src "ls180.v:0.0-0.0" - case 6'001101 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response11_w - attribute \src "ls180.v:0.0-0.0" - case 6'001110 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response10_w - attribute \src "ls180.v:0.0-0.0" - case 6'001111 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response9_w - attribute \src "ls180.v:0.0-0.0" - case 6'010000 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response8_w - attribute \src "ls180.v:0.0-0.0" - case 6'010001 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response7_w - attribute \src "ls180.v:0.0-0.0" - case 6'010010 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response6_w - attribute \src "ls180.v:0.0-0.0" - case 6'010011 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response5_w - attribute \src "ls180.v:0.0-0.0" - case 6'010100 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response4_w - attribute \src "ls180.v:0.0-0.0" - case 6'010101 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response3_w - attribute \src "ls180.v:0.0-0.0" - case 6'010110 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response2_w - attribute \src "ls180.v:0.0-0.0" - case 6'010111 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response1_w - attribute \src "ls180.v:0.0-0.0" - case 6'011000 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_cmd_response0_w - attribute \src "ls180.v:0.0-0.0" - case 6'011001 - assign $0\builder_interface6_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank6_cmd_event_w } - attribute \src "ls180.v:0.0-0.0" - case 6'011010 - assign $0\builder_interface6_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank6_data_event_w } - attribute \src "ls180.v:0.0-0.0" - case 6'011011 - assign $0\builder_interface6_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank6_block_length1_w } - attribute \src "ls180.v:0.0-0.0" - case 6'011100 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_length0_w - attribute \src "ls180.v:0.0-0.0" - case 6'011101 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count3_w - attribute \src "ls180.v:0.0-0.0" - case 6'011110 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count2_w - attribute \src "ls180.v:0.0-0.0" - case 6'011111 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count1_w - attribute \src "ls180.v:0.0-0.0" - case 6'100000 - assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_block_count0_w - case - end - case - end - attribute \src "ls180.v:9311.2-9313.5" - switch \builder_csrbank6_cmd_argument3_re - attribute \src "ls180.v:9311.6-9311.39" - case 1'1 - assign $0\main_sdcore_cmd_argument_storage[31:0] [31:24] \builder_csrbank6_cmd_argument3_r - case - end - attribute \src "ls180.v:9314.2-9316.5" - switch \builder_csrbank6_cmd_argument2_re - attribute \src "ls180.v:9314.6-9314.39" - case 1'1 - assign $0\main_sdcore_cmd_argument_storage[31:0] [23:16] \builder_csrbank6_cmd_argument2_r - case - end - attribute \src "ls180.v:9317.2-9319.5" - switch \builder_csrbank6_cmd_argument1_re - attribute \src "ls180.v:9317.6-9317.39" - case 1'1 - assign $0\main_sdcore_cmd_argument_storage[31:0] [15:8] \builder_csrbank6_cmd_argument1_r - case - end - attribute \src "ls180.v:9320.2-9322.5" - switch \builder_csrbank6_cmd_argument0_re - attribute \src "ls180.v:9320.6-9320.39" - case 1'1 - assign $0\main_sdcore_cmd_argument_storage[31:0] [7:0] \builder_csrbank6_cmd_argument0_r - case - end - attribute \src "ls180.v:9324.2-9326.5" - switch \builder_csrbank6_cmd_command3_re - attribute \src "ls180.v:9324.6-9324.38" - case 1'1 - assign $0\main_sdcore_cmd_command_storage[31:0] [31:24] \builder_csrbank6_cmd_command3_r - case - end - attribute \src "ls180.v:9327.2-9329.5" - switch \builder_csrbank6_cmd_command2_re - attribute \src "ls180.v:9327.6-9327.38" - case 1'1 - assign $0\main_sdcore_cmd_command_storage[31:0] [23:16] \builder_csrbank6_cmd_command2_r - case - end - attribute \src "ls180.v:9330.2-9332.5" - switch \builder_csrbank6_cmd_command1_re - attribute \src "ls180.v:9330.6-9330.38" - case 1'1 - assign $0\main_sdcore_cmd_command_storage[31:0] [15:8] \builder_csrbank6_cmd_command1_r - case - end - attribute \src "ls180.v:9333.2-9335.5" - switch \builder_csrbank6_cmd_command0_re - attribute \src "ls180.v:9333.6-9333.38" - case 1'1 - assign $0\main_sdcore_cmd_command_storage[31:0] [7:0] \builder_csrbank6_cmd_command0_r - case - end - attribute \src "ls180.v:9337.2-9339.5" - switch \builder_csrbank6_block_length1_re - attribute \src "ls180.v:9337.6-9337.39" - case 1'1 - assign $0\main_sdcore_block_length_storage[9:0] [9:8] \builder_csrbank6_block_length1_r - case - end - attribute \src "ls180.v:9340.2-9342.5" - switch \builder_csrbank6_block_length0_re - attribute \src "ls180.v:9340.6-9340.39" - case 1'1 - assign $0\main_sdcore_block_length_storage[9:0] [7:0] \builder_csrbank6_block_length0_r - case - end - attribute \src "ls180.v:9344.2-9346.5" - switch \builder_csrbank6_block_count3_re - attribute \src "ls180.v:9344.6-9344.38" - case 1'1 - assign $0\main_sdcore_block_count_storage[31:0] [31:24] \builder_csrbank6_block_count3_r - case - end - attribute \src "ls180.v:9347.2-9349.5" - switch \builder_csrbank6_block_count2_re - attribute \src "ls180.v:9347.6-9347.38" - case 1'1 - assign $0\main_sdcore_block_count_storage[31:0] [23:16] \builder_csrbank6_block_count2_r - case - end - attribute \src "ls180.v:9350.2-9352.5" - switch \builder_csrbank6_block_count1_re - attribute \src "ls180.v:9350.6-9350.38" - case 1'1 - assign $0\main_sdcore_block_count_storage[31:0] [15:8] \builder_csrbank6_block_count1_r - case - end - attribute \src "ls180.v:9353.2-9355.5" - switch \builder_csrbank6_block_count0_re - attribute \src "ls180.v:9353.6-9353.38" - case 1'1 - assign $0\main_sdcore_block_count_storage[31:0] [7:0] \builder_csrbank6_block_count0_r - case - end - attribute \src "ls180.v:9358.2-9418.5" - switch \builder_csrbank7_sel - attribute \src "ls180.v:9358.6-9358.26" - case 1'1 - attribute \src "ls180.v:9359.3-9417.10" - switch \builder_interface7_bank_bus_adr [4:0] - attribute \src "ls180.v:0.0-0.0" - case 5'00000 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base7_w - attribute \src "ls180.v:0.0-0.0" - case 5'00001 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base6_w - attribute \src "ls180.v:0.0-0.0" - case 5'00010 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base5_w - attribute \src "ls180.v:0.0-0.0" - case 5'00011 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base4_w - attribute \src "ls180.v:0.0-0.0" - case 5'00100 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base3_w - attribute \src "ls180.v:0.0-0.0" - case 5'00101 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base2_w - attribute \src "ls180.v:0.0-0.0" - case 5'00110 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base1_w - attribute \src "ls180.v:0.0-0.0" - case 5'00111 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_base0_w - attribute \src "ls180.v:0.0-0.0" - case 5'01000 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length3_w - attribute \src "ls180.v:0.0-0.0" - case 5'01001 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length2_w - attribute \src "ls180.v:0.0-0.0" - case 5'01010 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length1_w - attribute \src "ls180.v:0.0-0.0" - case 5'01011 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_length0_w - attribute \src "ls180.v:0.0-0.0" - case 5'01100 - assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_dma_enable0_w } - attribute \src "ls180.v:0.0-0.0" - case 5'01101 - assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_dma_done_w } - attribute \src "ls180.v:0.0-0.0" - case 5'01110 - assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank7_dma_loop0_w } - attribute \src "ls180.v:0.0-0.0" - case 5'01111 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset3_w - attribute \src "ls180.v:0.0-0.0" - case 5'10000 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset2_w - attribute \src "ls180.v:0.0-0.0" - case 5'10001 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset1_w - attribute \src "ls180.v:0.0-0.0" - case 5'10010 - assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dma_offset0_w - case - end - case - end - attribute \src "ls180.v:9419.2-9421.5" - switch \builder_csrbank7_dma_base7_re - attribute \src "ls180.v:9419.6-9419.35" - case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [63:56] \builder_csrbank7_dma_base7_r - case - end - attribute \src "ls180.v:9422.2-9424.5" - switch \builder_csrbank7_dma_base6_re - attribute \src "ls180.v:9422.6-9422.35" - case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [55:48] \builder_csrbank7_dma_base6_r - case - end - attribute \src "ls180.v:9425.2-9427.5" - switch \builder_csrbank7_dma_base5_re - attribute \src "ls180.v:9425.6-9425.35" - case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [47:40] \builder_csrbank7_dma_base5_r - case - end - attribute \src "ls180.v:9428.2-9430.5" - switch \builder_csrbank7_dma_base4_re - attribute \src "ls180.v:9428.6-9428.35" - case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [39:32] \builder_csrbank7_dma_base4_r - case - end - attribute \src "ls180.v:9431.2-9433.5" - switch \builder_csrbank7_dma_base3_re - attribute \src "ls180.v:9431.6-9431.35" - case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [31:24] \builder_csrbank7_dma_base3_r - case - end - attribute \src "ls180.v:9434.2-9436.5" - switch \builder_csrbank7_dma_base2_re - attribute \src "ls180.v:9434.6-9434.35" - case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [23:16] \builder_csrbank7_dma_base2_r - case - end - attribute \src "ls180.v:9437.2-9439.5" - switch \builder_csrbank7_dma_base1_re - attribute \src "ls180.v:9437.6-9437.35" - case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [15:8] \builder_csrbank7_dma_base1_r - case - end - attribute \src "ls180.v:9440.2-9442.5" - switch \builder_csrbank7_dma_base0_re - attribute \src "ls180.v:9440.6-9440.35" - case 1'1 - assign $0\main_sdmem2block_dma_base_storage[63:0] [7:0] \builder_csrbank7_dma_base0_r - case - end - attribute \src "ls180.v:9444.2-9446.5" - switch \builder_csrbank7_dma_length3_re - attribute \src "ls180.v:9444.6-9444.37" - case 1'1 - assign $0\main_sdmem2block_dma_length_storage[31:0] [31:24] \builder_csrbank7_dma_length3_r - case - end - attribute \src "ls180.v:9447.2-9449.5" - switch \builder_csrbank7_dma_length2_re - attribute \src "ls180.v:9447.6-9447.37" - case 1'1 - assign $0\main_sdmem2block_dma_length_storage[31:0] [23:16] \builder_csrbank7_dma_length2_r + assign $0\rx_fifo_level0[4:0] $add$ls180.v:4937$1452_Y + case + end + attribute \src "ls180.v:4939.6-4939.10" case + attribute \src "ls180.v:4940.3-4942.6" + switch \rx_fifo_do_read + attribute \src "ls180.v:4940.7-4940.22" + case 1'1 + assign $0\rx_fifo_level0[4:0] $sub$ls180.v:4941$1453_Y + case + end end - attribute \src "ls180.v:9450.2-9452.5" - switch \builder_csrbank7_dma_length1_re - attribute \src "ls180.v:9450.6-9450.37" + attribute \src "ls180.v:4944.2-4957.5" + switch \reset + attribute \src "ls180.v:4944.6-4944.11" case 1'1 - assign $0\main_sdmem2block_dma_length_storage[31:0] [15:8] \builder_csrbank7_dma_length1_r + assign $0\tx_pending[0:0] 1'0 + assign $0\tx_old_trigger[0:0] 1'0 + assign $0\rx_pending[0:0] 1'0 + assign $0\rx_old_trigger[0:0] 1'0 + assign $0\tx_fifo_readable[0:0] 1'0 + assign $0\tx_fifo_level0[4:0] 5'00000 + assign $0\tx_fifo_produce[3:0] 4'0000 + assign $0\tx_fifo_consume[3:0] 4'0000 + assign $0\rx_fifo_readable[0:0] 1'0 + assign $0\rx_fifo_level0[4:0] 5'00000 + assign $0\rx_fifo_produce[3:0] 4'0000 + assign $0\rx_fifo_consume[3:0] 4'0000 case end - attribute \src "ls180.v:9453.2-9455.5" - switch \builder_csrbank7_dma_length0_re - attribute \src "ls180.v:9453.6-9453.37" + attribute \src "ls180.v:4959.2-4961.5" + switch \libresocsim_libresocsim_dat_w_libresocsim_next_value_ce0 + attribute \src "ls180.v:4959.6-4959.62" case 1'1 - assign $0\main_sdmem2block_dma_length_storage[31:0] [7:0] \builder_csrbank7_dma_length0_r + assign $0\libresocsim_libresocsim_dat_w[7:0] \libresocsim_libresocsim_dat_w_libresocsim_next_value0 case end - attribute \src "ls180.v:9457.2-9459.5" - switch \builder_csrbank7_dma_enable0_re - attribute \src "ls180.v:9457.6-9457.37" + attribute \src "ls180.v:4962.2-4964.5" + switch \libresocsim_libresocsim_adr_libresocsim_next_value_ce1 + attribute \src "ls180.v:4962.6-4962.60" case 1'1 - assign $0\main_sdmem2block_dma_enable_storage[0:0] \builder_csrbank7_dma_enable0_r + assign $0\libresocsim_libresocsim_adr[13:0] \libresocsim_libresocsim_adr_libresocsim_next_value1 case end - attribute \src "ls180.v:9461.2-9463.5" - switch \builder_csrbank7_dma_loop0_re - attribute \src "ls180.v:9461.6-9461.35" + attribute \src "ls180.v:4965.2-4967.5" + switch \libresocsim_libresocsim_we_libresocsim_next_value_ce2 + attribute \src "ls180.v:4965.6-4965.59" case 1'1 - assign $0\main_sdmem2block_dma_loop_storage[0:0] \builder_csrbank7_dma_loop0_r + assign $0\libresocsim_libresocsim_we[0:0] \libresocsim_libresocsim_we_libresocsim_next_value2 case end - attribute \src "ls180.v:9466.2-9481.5" - switch \builder_csrbank8_sel - attribute \src "ls180.v:9466.6-9466.26" - case 1'1 - attribute \src "ls180.v:9467.3-9480.10" - switch \builder_interface8_bank_bus_adr [1:0] - attribute \src "ls180.v:0.0-0.0" - case 2'00 - assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank8_card_detect_w } - attribute \src "ls180.v:0.0-0.0" - case 2'01 - assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank8_clocker_divider1_w } - attribute \src "ls180.v:0.0-0.0" - case 2'10 - assign $0\builder_interface8_bank_bus_dat_r[7:0] \builder_csrbank8_clocker_divider0_w - attribute \src "ls180.v:0.0-0.0" - case 2'11 - assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \main_sdphy_init_initialize_w } + attribute \src "ls180.v:4968.2-5002.9" + switch \libresocsim_grant + attribute \src "ls180.v:0.0-0.0" + case 2'00 + attribute \src "ls180.v:4970.4-4978.7" + switch $not$ls180.v:4970$1454_Y + attribute \src "ls180.v:4970.8-4970.33" + case 1'1 + attribute \src "ls180.v:4971.5-4977.8" + switch \libresocsim_request [1] + attribute \src "ls180.v:4971.9-4971.31" + case 1'1 + assign $0\libresocsim_grant[1:0] 2'01 + attribute \src "ls180.v:4973.9-4973.13" + case + attribute \src "ls180.v:4974.6-4976.9" + switch \libresocsim_request [2] + attribute \src "ls180.v:4974.10-4974.32" + case 1'1 + assign $0\libresocsim_grant[1:0] 2'10 + case + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'01 + attribute \src "ls180.v:4981.4-4989.7" + switch $not$ls180.v:4981$1455_Y + attribute \src "ls180.v:4981.8-4981.33" + case 1'1 + attribute \src "ls180.v:4982.5-4988.8" + switch \libresocsim_request [2] + attribute \src "ls180.v:4982.9-4982.31" + case 1'1 + assign $0\libresocsim_grant[1:0] 2'10 + attribute \src "ls180.v:4984.9-4984.13" + case + attribute \src "ls180.v:4985.6-4987.9" + switch \libresocsim_request [0] + attribute \src "ls180.v:4985.10-4985.32" + case 1'1 + assign $0\libresocsim_grant[1:0] 2'00 + case + end + end + case + end + attribute \src "ls180.v:0.0-0.0" + case 2'10 + attribute \src "ls180.v:4992.4-5000.7" + switch $not$ls180.v:4992$1456_Y + attribute \src "ls180.v:4992.8-4992.33" + case 1'1 + attribute \src "ls180.v:4993.5-4999.8" + switch \libresocsim_request [0] + attribute \src "ls180.v:4993.9-4993.31" + case 1'1 + assign $0\libresocsim_grant[1:0] 2'00 + attribute \src "ls180.v:4995.9-4995.13" + case + attribute \src "ls180.v:4996.6-4998.9" + switch \libresocsim_request [1] + attribute \src "ls180.v:4996.10-4996.32" + case 1'1 + assign $0\libresocsim_grant[1:0] 2'01 + case + end + end case end case end - attribute \src "ls180.v:9482.2-9484.5" - switch \builder_csrbank8_clocker_divider1_re - attribute \src "ls180.v:9482.6-9482.42" - case 1'1 - assign $0\main_sdphy_clocker_storage[8:0] [8] \builder_csrbank8_clocker_divider1_r - case - end - attribute \src "ls180.v:9485.2-9487.5" - switch \builder_csrbank8_clocker_divider0_re - attribute \src "ls180.v:9485.6-9485.42" + attribute \src "ls180.v:5004.2-5010.5" + switch \libresocsim_wait + attribute \src "ls180.v:5004.6-5004.22" case 1'1 - assign $0\main_sdphy_clocker_storage[8:0] [7:0] \builder_csrbank8_clocker_divider0_r + attribute \src "ls180.v:5005.3-5007.6" + switch $not$ls180.v:5005$1457_Y + attribute \src "ls180.v:5005.7-5005.26" + case 1'1 + assign $0\libresocsim_count[19:0] $sub$ls180.v:5006$1458_Y + case + end + attribute \src "ls180.v:5008.6-5008.10" case + assign $0\libresocsim_count[19:0] 20'11110100001001000000 end - attribute \src "ls180.v:9490.2-9523.5" - switch \builder_csrbank9_sel - attribute \src "ls180.v:9490.6-9490.26" + attribute \src "ls180.v:5012.2-5042.5" + switch \libresocsim_csrbank0_sel + attribute \src "ls180.v:5012.6-5012.30" case 1'1 - attribute \src "ls180.v:9491.3-9522.10" - switch \builder_interface9_bank_bus_adr [3:0] + attribute \src "ls180.v:5013.3-5041.10" + switch \libresocsim_interface0_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 - assign $0\builder_interface9_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank9_dfii_control0_w } + assign $0\libresocsim_interface0_bank_bus_dat_r[7:0] { 7'0000000 \libresocsim_csrbank0_reset0_w } attribute \src "ls180.v:0.0-0.0" case 4'0001 - assign $0\builder_interface9_bank_bus_dat_r[7:0] { 2'00 \builder_csrbank9_dfii_pi0_command0_w } + assign $0\libresocsim_interface0_bank_bus_dat_r[7:0] \libresocsim_csrbank0_scratch3_w attribute \src "ls180.v:0.0-0.0" case 4'0010 - assign $0\builder_interface9_bank_bus_dat_r[7:0] { 7'0000000 \main_sdram_command_issue_w } + assign $0\libresocsim_interface0_bank_bus_dat_r[7:0] \libresocsim_csrbank0_scratch2_w attribute \src "ls180.v:0.0-0.0" case 4'0011 - assign $0\builder_interface9_bank_bus_dat_r[7:0] { 3'000 \builder_csrbank9_dfii_pi0_address1_w } + assign $0\libresocsim_interface0_bank_bus_dat_r[7:0] \libresocsim_csrbank0_scratch1_w attribute \src "ls180.v:0.0-0.0" case 4'0100 - assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_address0_w + assign $0\libresocsim_interface0_bank_bus_dat_r[7:0] \libresocsim_csrbank0_scratch0_w attribute \src "ls180.v:0.0-0.0" case 4'0101 - assign $0\builder_interface9_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank9_dfii_pi0_baddress0_w } + assign $0\libresocsim_interface0_bank_bus_dat_r[7:0] \libresocsim_csrbank0_bus_errors3_w attribute \src "ls180.v:0.0-0.0" case 4'0110 - assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_wrdata1_w + assign $0\libresocsim_interface0_bank_bus_dat_r[7:0] \libresocsim_csrbank0_bus_errors2_w attribute \src "ls180.v:0.0-0.0" case 4'0111 - assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_wrdata0_w + assign $0\libresocsim_interface0_bank_bus_dat_r[7:0] \libresocsim_csrbank0_bus_errors1_w attribute \src "ls180.v:0.0-0.0" case 4'1000 - assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_rddata1_w - attribute \src "ls180.v:0.0-0.0" - case 4'1001 - assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_dfii_pi0_rddata0_w + assign $0\libresocsim_interface0_bank_bus_dat_r[7:0] \libresocsim_csrbank0_bus_errors0_w case end case end - attribute \src "ls180.v:9524.2-9526.5" - switch \builder_csrbank9_dfii_control0_re - attribute \src "ls180.v:9524.6-9524.39" + attribute \src "ls180.v:5043.2-5045.5" + switch \libresocsim_csrbank0_reset0_re + attribute \src "ls180.v:5043.6-5043.36" case 1'1 - assign $0\main_sdram_storage[3:0] \builder_csrbank9_dfii_control0_r + assign $0\libresocsim_reset_storage[0:0] \libresocsim_csrbank0_reset0_r case end - attribute \src "ls180.v:9528.2-9530.5" - switch \builder_csrbank9_dfii_pi0_command0_re - attribute \src "ls180.v:9528.6-9528.43" + attribute \src "ls180.v:5047.2-5049.5" + switch \libresocsim_csrbank0_scratch3_re + attribute \src "ls180.v:5047.6-5047.38" case 1'1 - assign $0\main_sdram_command_storage[5:0] \builder_csrbank9_dfii_pi0_command0_r + assign $0\libresocsim_scratch_storage[31:0] [31:24] \libresocsim_csrbank0_scratch3_r case end - attribute \src "ls180.v:9532.2-9534.5" - switch \builder_csrbank9_dfii_pi0_address1_re - attribute \src "ls180.v:9532.6-9532.43" + attribute \src "ls180.v:5050.2-5052.5" + switch \libresocsim_csrbank0_scratch2_re + attribute \src "ls180.v:5050.6-5050.38" case 1'1 - assign $0\main_sdram_address_storage[12:0] [12:8] \builder_csrbank9_dfii_pi0_address1_r + assign $0\libresocsim_scratch_storage[31:0] [23:16] \libresocsim_csrbank0_scratch2_r case end - attribute \src "ls180.v:9535.2-9537.5" - switch \builder_csrbank9_dfii_pi0_address0_re - attribute \src "ls180.v:9535.6-9535.43" + attribute \src "ls180.v:5053.2-5055.5" + switch \libresocsim_csrbank0_scratch1_re + attribute \src "ls180.v:5053.6-5053.38" case 1'1 - assign $0\main_sdram_address_storage[12:0] [7:0] \builder_csrbank9_dfii_pi0_address0_r + assign $0\libresocsim_scratch_storage[31:0] [15:8] \libresocsim_csrbank0_scratch1_r case end - attribute \src "ls180.v:9539.2-9541.5" - switch \builder_csrbank9_dfii_pi0_baddress0_re - attribute \src "ls180.v:9539.6-9539.44" + attribute \src "ls180.v:5056.2-5058.5" + switch \libresocsim_csrbank0_scratch0_re + attribute \src "ls180.v:5056.6-5056.38" case 1'1 - assign $0\main_sdram_baddress_storage[1:0] \builder_csrbank9_dfii_pi0_baddress0_r + assign $0\libresocsim_scratch_storage[31:0] [7:0] \libresocsim_csrbank0_scratch0_r case end - attribute \src "ls180.v:9543.2-9545.5" - switch \builder_csrbank9_dfii_pi0_wrdata1_re - attribute \src "ls180.v:9543.6-9543.42" + attribute \src "ls180.v:5061.2-5073.5" + switch \libresocsim_csrbank1_sel + attribute \src "ls180.v:5061.6-5061.30" case 1'1 - assign $0\main_sdram_wrdata_storage[15:0] [15:8] \builder_csrbank9_dfii_pi0_wrdata1_r + attribute \src "ls180.v:5062.3-5072.10" + switch \libresocsim_interface1_bank_bus_adr [1:0] + attribute \src "ls180.v:0.0-0.0" + case 2'00 + assign $0\libresocsim_interface1_bank_bus_dat_r[7:0] \libresocsim_csrbank1_oe0_w + attribute \src "ls180.v:0.0-0.0" + case 2'01 + assign $0\libresocsim_interface1_bank_bus_dat_r[7:0] \libresocsim_csrbank1_in_w + attribute \src "ls180.v:0.0-0.0" + case 2'10 + assign $0\libresocsim_interface1_bank_bus_dat_r[7:0] \libresocsim_csrbank1_out0_w + case + end case end - attribute \src "ls180.v:9546.2-9548.5" - switch \builder_csrbank9_dfii_pi0_wrdata0_re - attribute \src "ls180.v:9546.6-9546.42" + attribute \src "ls180.v:5074.2-5076.5" + switch \libresocsim_csrbank1_oe0_re + attribute \src "ls180.v:5074.6-5074.33" case 1'1 - assign $0\main_sdram_wrdata_storage[15:0] [7:0] \builder_csrbank9_dfii_pi0_wrdata0_r + assign $0\gpio0_oe_storage[7:0] \libresocsim_csrbank1_oe0_r case end - attribute \src "ls180.v:9551.2-9575.5" - switch \builder_csrbank10_sel - attribute \src "ls180.v:9551.6-9551.27" + attribute \src "ls180.v:5078.2-5080.5" + switch \libresocsim_csrbank1_out0_re + attribute \src "ls180.v:5078.6-5078.34" case 1'1 - attribute \src "ls180.v:9552.3-9574.10" - switch \builder_interface10_bank_bus_adr [2:0] - attribute \src "ls180.v:0.0-0.0" - case 3'000 - assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_control1_w - attribute \src "ls180.v:0.0-0.0" - case 3'001 - assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_control0_w - attribute \src "ls180.v:0.0-0.0" - case 3'010 - assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_status_w } - attribute \src "ls180.v:0.0-0.0" - case 3'011 - assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_mosi0_w + assign $0\gpio0_out_storage[7:0] \libresocsim_csrbank1_out0_r + case + end + attribute \src "ls180.v:5083.2-5095.5" + switch \libresocsim_csrbank2_sel + attribute \src "ls180.v:5083.6-5083.30" + case 1'1 + attribute \src "ls180.v:5084.3-5094.10" + switch \libresocsim_interface2_bank_bus_adr [1:0] attribute \src "ls180.v:0.0-0.0" - case 3'100 - assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_miso_w + case 2'00 + assign $0\libresocsim_interface2_bank_bus_dat_r[7:0] \libresocsim_csrbank2_oe0_w attribute \src "ls180.v:0.0-0.0" - case 3'101 - assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_cs0_w } + case 2'01 + assign $0\libresocsim_interface2_bank_bus_dat_r[7:0] \libresocsim_csrbank2_in_w attribute \src "ls180.v:0.0-0.0" - case 3'110 - assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_loopback0_w } + case 2'10 + assign $0\libresocsim_interface2_bank_bus_dat_r[7:0] \libresocsim_csrbank2_out0_w case end case end - attribute \src "ls180.v:9576.2-9578.5" - switch \builder_csrbank10_control1_re - attribute \src "ls180.v:9576.6-9576.35" - case 1'1 - assign $0\main_spimaster11_storage[15:0] [15:8] \builder_csrbank10_control1_r - case - end - attribute \src "ls180.v:9579.2-9581.5" - switch \builder_csrbank10_control0_re - attribute \src "ls180.v:9579.6-9579.35" + attribute \src "ls180.v:5096.2-5098.5" + switch \libresocsim_csrbank2_oe0_re + attribute \src "ls180.v:5096.6-5096.33" case 1'1 - assign $0\main_spimaster11_storage[15:0] [7:0] \builder_csrbank10_control0_r + assign $0\gpio1_oe_storage[7:0] \libresocsim_csrbank2_oe0_r case end - attribute \src "ls180.v:9583.2-9585.5" - switch \builder_csrbank10_mosi0_re - attribute \src "ls180.v:9583.6-9583.32" + attribute \src "ls180.v:5100.2-5102.5" + switch \libresocsim_csrbank2_out0_re + attribute \src "ls180.v:5100.6-5100.34" case 1'1 - assign $0\main_spimaster16_storage[7:0] \builder_csrbank10_mosi0_r + assign $0\gpio1_out_storage[7:0] \libresocsim_csrbank2_out0_r case end - attribute \src "ls180.v:9587.2-9589.5" - switch \builder_csrbank10_cs0_re - attribute \src "ls180.v:9587.6-9587.30" + attribute \src "ls180.v:5105.2-5114.5" + switch \libresocsim_csrbank3_sel + attribute \src "ls180.v:5105.6-5105.30" case 1'1 - assign $0\main_spimaster21_storage[0:0] \builder_csrbank10_cs0_r + attribute \src "ls180.v:5106.3-5113.10" + switch \libresocsim_interface3_bank_bus_adr [0] + attribute \src "ls180.v:0.0-0.0" + case 1'0 + assign $0\libresocsim_interface3_bank_bus_dat_r[7:0] { 5'00000 \libresocsim_csrbank3_w0_w } + attribute \src "ls180.v:0.0-0.0" + case 1'1 + assign $0\libresocsim_interface3_bank_bus_dat_r[7:0] { 7'0000000 \libresocsim_csrbank3_r_w } + case + end case end - attribute \src "ls180.v:9591.2-9593.5" - switch \builder_csrbank10_loopback0_re - attribute \src "ls180.v:9591.6-9591.36" + attribute \src "ls180.v:5115.2-5117.5" + switch \libresocsim_csrbank3_w0_re + attribute \src "ls180.v:5115.6-5115.32" case 1'1 - assign $0\main_spimaster23_storage[0:0] \builder_csrbank10_loopback0_r + assign $0\i2c_storage[2:0] \libresocsim_csrbank3_w0_r case end - attribute \src "ls180.v:9596.2-9626.5" - switch \builder_csrbank11_sel - attribute \src "ls180.v:9596.6-9596.27" + attribute \src "ls180.v:5120.2-5153.5" + switch \libresocsim_csrbank4_sel + attribute \src "ls180.v:5120.6-5120.30" case 1'1 - attribute \src "ls180.v:9597.3-9625.10" - switch \builder_interface11_bank_bus_adr [3:0] + attribute \src "ls180.v:5121.3-5152.10" + switch \libresocsim_interface4_bank_bus_adr [3:0] attribute \src "ls180.v:0.0-0.0" case 4'0000 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_control1_w + assign $0\libresocsim_interface4_bank_bus_dat_r[7:0] { 4'0000 \libresocsim_csrbank4_dfii_control0_w } attribute \src "ls180.v:0.0-0.0" case 4'0001 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_control0_w + assign $0\libresocsim_interface4_bank_bus_dat_r[7:0] { 2'00 \libresocsim_csrbank4_dfii_pi0_command0_w } attribute \src "ls180.v:0.0-0.0" case 4'0010 - assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_status_w } + assign $0\libresocsim_interface4_bank_bus_dat_r[7:0] { 7'0000000 \sdram_command_issue_w } attribute \src "ls180.v:0.0-0.0" case 4'0011 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_mosi0_w + assign $0\libresocsim_interface4_bank_bus_dat_r[7:0] { 3'000 \libresocsim_csrbank4_dfii_pi0_address1_w } attribute \src "ls180.v:0.0-0.0" case 4'0100 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_miso_w + assign $0\libresocsim_interface4_bank_bus_dat_r[7:0] \libresocsim_csrbank4_dfii_pi0_address0_w attribute \src "ls180.v:0.0-0.0" case 4'0101 - assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_cs0_w } + assign $0\libresocsim_interface4_bank_bus_dat_r[7:0] { 6'000000 \libresocsim_csrbank4_dfii_pi0_baddress0_w } attribute \src "ls180.v:0.0-0.0" case 4'0110 - assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_loopback0_w } + assign $0\libresocsim_interface4_bank_bus_dat_r[7:0] \libresocsim_csrbank4_dfii_pi0_wrdata1_w attribute \src "ls180.v:0.0-0.0" case 4'0111 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_clk_divider1_w + assign $0\libresocsim_interface4_bank_bus_dat_r[7:0] \libresocsim_csrbank4_dfii_pi0_wrdata0_w attribute \src "ls180.v:0.0-0.0" case 4'1000 - assign $0\builder_interface11_bank_bus_dat_r[7:0] \builder_csrbank11_clk_divider0_w + assign $0\libresocsim_interface4_bank_bus_dat_r[7:0] \libresocsim_csrbank4_dfii_pi0_rddata1_w + attribute \src "ls180.v:0.0-0.0" + case 4'1001 + assign $0\libresocsim_interface4_bank_bus_dat_r[7:0] \libresocsim_csrbank4_dfii_pi0_rddata0_w case end case end - attribute \src "ls180.v:9627.2-9629.5" - switch \builder_csrbank11_control1_re - attribute \src "ls180.v:9627.6-9627.35" + attribute \src "ls180.v:5154.2-5156.5" + switch \libresocsim_csrbank4_dfii_control0_re + attribute \src "ls180.v:5154.6-5154.43" case 1'1 - assign $0\main_spisdcard_control_storage[15:0] [15:8] \builder_csrbank11_control1_r + assign $0\sdram_storage[3:0] \libresocsim_csrbank4_dfii_control0_r case end - attribute \src "ls180.v:9630.2-9632.5" - switch \builder_csrbank11_control0_re - attribute \src "ls180.v:9630.6-9630.35" + attribute \src "ls180.v:5158.2-5160.5" + switch \libresocsim_csrbank4_dfii_pi0_command0_re + attribute \src "ls180.v:5158.6-5158.47" case 1'1 - assign $0\main_spisdcard_control_storage[15:0] [7:0] \builder_csrbank11_control0_r + assign $0\sdram_command_storage[5:0] \libresocsim_csrbank4_dfii_pi0_command0_r case end - attribute \src "ls180.v:9634.2-9636.5" - switch \builder_csrbank11_mosi0_re - attribute \src "ls180.v:9634.6-9634.32" + attribute \src "ls180.v:5162.2-5164.5" + switch \libresocsim_csrbank4_dfii_pi0_address1_re + attribute \src "ls180.v:5162.6-5162.47" case 1'1 - assign $0\main_spisdcard_mosi_storage[7:0] \builder_csrbank11_mosi0_r + assign $0\sdram_address_storage[12:0] [12:8] \libresocsim_csrbank4_dfii_pi0_address1_r case end - attribute \src "ls180.v:9638.2-9640.5" - switch \builder_csrbank11_cs0_re - attribute \src "ls180.v:9638.6-9638.30" + attribute \src "ls180.v:5165.2-5167.5" + switch \libresocsim_csrbank4_dfii_pi0_address0_re + attribute \src "ls180.v:5165.6-5165.47" case 1'1 - assign $0\main_spisdcard_cs_storage[0:0] \builder_csrbank11_cs0_r + assign $0\sdram_address_storage[12:0] [7:0] \libresocsim_csrbank4_dfii_pi0_address0_r case end - attribute \src "ls180.v:9642.2-9644.5" - switch \builder_csrbank11_loopback0_re - attribute \src "ls180.v:9642.6-9642.36" + attribute \src "ls180.v:5169.2-5171.5" + switch \libresocsim_csrbank4_dfii_pi0_baddress0_re + attribute \src "ls180.v:5169.6-5169.48" case 1'1 - assign $0\main_spisdcard_loopback_storage[0:0] \builder_csrbank11_loopback0_r + assign $0\sdram_baddress_storage[1:0] \libresocsim_csrbank4_dfii_pi0_baddress0_r case end - attribute \src "ls180.v:9646.2-9648.5" - switch \builder_csrbank11_clk_divider1_re - attribute \src "ls180.v:9646.6-9646.39" + attribute \src "ls180.v:5173.2-5175.5" + switch \libresocsim_csrbank4_dfii_pi0_wrdata1_re + attribute \src "ls180.v:5173.6-5173.46" case 1'1 - assign $0\main_spimaster1_storage[15:0] [15:8] \builder_csrbank11_clk_divider1_r + assign $0\sdram_wrdata_storage[15:0] [15:8] \libresocsim_csrbank4_dfii_pi0_wrdata1_r case end - attribute \src "ls180.v:9649.2-9651.5" - switch \builder_csrbank11_clk_divider0_re - attribute \src "ls180.v:9649.6-9649.39" + attribute \src "ls180.v:5176.2-5178.5" + switch \libresocsim_csrbank4_dfii_pi0_wrdata0_re + attribute \src "ls180.v:5176.6-5176.46" case 1'1 - assign $0\main_spimaster1_storage[15:0] [7:0] \builder_csrbank11_clk_divider0_r + assign $0\sdram_wrdata_storage[15:0] [7:0] \libresocsim_csrbank4_dfii_pi0_wrdata0_r case end - attribute \src "ls180.v:9654.2-9708.5" - switch \builder_csrbank12_sel - attribute \src "ls180.v:9654.6-9654.27" + attribute \src "ls180.v:5181.2-5235.5" + switch \libresocsim_csrbank5_sel + attribute \src "ls180.v:5181.6-5181.30" case 1'1 - attribute \src "ls180.v:9655.3-9707.10" - switch \builder_interface12_bank_bus_adr [4:0] + attribute \src "ls180.v:5182.3-5234.10" + switch \libresocsim_interface5_bank_bus_adr [4:0] attribute \src "ls180.v:0.0-0.0" case 5'00000 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load3_w + assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] \libresocsim_csrbank5_load3_w attribute \src "ls180.v:0.0-0.0" case 5'00001 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load2_w + assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] \libresocsim_csrbank5_load2_w attribute \src "ls180.v:0.0-0.0" case 5'00010 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load1_w + assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] \libresocsim_csrbank5_load1_w attribute \src "ls180.v:0.0-0.0" case 5'00011 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_load0_w + assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] \libresocsim_csrbank5_load0_w attribute \src "ls180.v:0.0-0.0" case 5'00100 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload3_w + assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] \libresocsim_csrbank5_reload3_w attribute \src "ls180.v:0.0-0.0" case 5'00101 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload2_w + assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] \libresocsim_csrbank5_reload2_w attribute \src "ls180.v:0.0-0.0" case 5'00110 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload1_w + assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] \libresocsim_csrbank5_reload1_w attribute \src "ls180.v:0.0-0.0" case 5'00111 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_reload0_w + assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] \libresocsim_csrbank5_reload0_w attribute \src "ls180.v:0.0-0.0" case 5'01000 - assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_en0_w } + assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] { 7'0000000 \libresocsim_csrbank5_en0_w } attribute \src "ls180.v:0.0-0.0" case 5'01001 - assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_update_value0_w } + assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] { 7'0000000 \libresocsim_csrbank5_update_value0_w } attribute \src "ls180.v:0.0-0.0" case 5'01010 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value3_w + assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] \libresocsim_csrbank5_value3_w attribute \src "ls180.v:0.0-0.0" case 5'01011 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value2_w + assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] \libresocsim_csrbank5_value2_w attribute \src "ls180.v:0.0-0.0" case 5'01100 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value1_w + assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] \libresocsim_csrbank5_value1_w attribute \src "ls180.v:0.0-0.0" case 5'01101 - assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_value0_w + assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] \libresocsim_csrbank5_value0_w attribute \src "ls180.v:0.0-0.0" case 5'01110 - assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \main_libresocsim_eventmanager_status_w } + assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] { 7'0000000 \libresocsim_eventmanager_status_w } attribute \src "ls180.v:0.0-0.0" case 5'01111 - assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \main_libresocsim_eventmanager_pending_w } + assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] { 7'0000000 \libresocsim_eventmanager_pending_w } attribute \src "ls180.v:0.0-0.0" case 5'10000 - assign $0\builder_interface12_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank12_ev_enable0_w } + assign $0\libresocsim_interface5_bank_bus_dat_r[7:0] { 7'0000000 \libresocsim_csrbank5_ev_enable0_w } case end case end - attribute \src "ls180.v:9709.2-9711.5" - switch \builder_csrbank12_load3_re - attribute \src "ls180.v:9709.6-9709.32" + attribute \src "ls180.v:5236.2-5238.5" + switch \libresocsim_csrbank5_load3_re + attribute \src "ls180.v:5236.6-5236.35" case 1'1 - assign $0\main_libresocsim_load_storage[31:0] [31:24] \builder_csrbank12_load3_r + assign $0\libresocsim_load_storage[31:0] [31:24] \libresocsim_csrbank5_load3_r case end - attribute \src "ls180.v:9712.2-9714.5" - switch \builder_csrbank12_load2_re - attribute \src "ls180.v:9712.6-9712.32" + attribute \src "ls180.v:5239.2-5241.5" + switch \libresocsim_csrbank5_load2_re + attribute \src "ls180.v:5239.6-5239.35" case 1'1 - assign $0\main_libresocsim_load_storage[31:0] [23:16] \builder_csrbank12_load2_r + assign $0\libresocsim_load_storage[31:0] [23:16] \libresocsim_csrbank5_load2_r case end - attribute \src "ls180.v:9715.2-9717.5" - switch \builder_csrbank12_load1_re - attribute \src "ls180.v:9715.6-9715.32" + attribute \src "ls180.v:5242.2-5244.5" + switch \libresocsim_csrbank5_load1_re + attribute \src "ls180.v:5242.6-5242.35" case 1'1 - assign $0\main_libresocsim_load_storage[31:0] [15:8] \builder_csrbank12_load1_r + assign $0\libresocsim_load_storage[31:0] [15:8] \libresocsim_csrbank5_load1_r case end - attribute \src "ls180.v:9718.2-9720.5" - switch \builder_csrbank12_load0_re - attribute \src "ls180.v:9718.6-9718.32" + attribute \src "ls180.v:5245.2-5247.5" + switch \libresocsim_csrbank5_load0_re + attribute \src "ls180.v:5245.6-5245.35" case 1'1 - assign $0\main_libresocsim_load_storage[31:0] [7:0] \builder_csrbank12_load0_r + assign $0\libresocsim_load_storage[31:0] [7:0] \libresocsim_csrbank5_load0_r case end - attribute \src "ls180.v:9722.2-9724.5" - switch \builder_csrbank12_reload3_re - attribute \src "ls180.v:9722.6-9722.34" + attribute \src "ls180.v:5249.2-5251.5" + switch \libresocsim_csrbank5_reload3_re + attribute \src "ls180.v:5249.6-5249.37" case 1'1 - assign $0\main_libresocsim_reload_storage[31:0] [31:24] \builder_csrbank12_reload3_r + assign $0\libresocsim_reload_storage[31:0] [31:24] \libresocsim_csrbank5_reload3_r case end - attribute \src "ls180.v:9725.2-9727.5" - switch \builder_csrbank12_reload2_re - attribute \src "ls180.v:9725.6-9725.34" + attribute \src "ls180.v:5252.2-5254.5" + switch \libresocsim_csrbank5_reload2_re + attribute \src "ls180.v:5252.6-5252.37" case 1'1 - assign $0\main_libresocsim_reload_storage[31:0] [23:16] \builder_csrbank12_reload2_r + assign $0\libresocsim_reload_storage[31:0] [23:16] \libresocsim_csrbank5_reload2_r case end - attribute \src "ls180.v:9728.2-9730.5" - switch \builder_csrbank12_reload1_re - attribute \src "ls180.v:9728.6-9728.34" + attribute \src "ls180.v:5255.2-5257.5" + switch \libresocsim_csrbank5_reload1_re + attribute \src "ls180.v:5255.6-5255.37" case 1'1 - assign $0\main_libresocsim_reload_storage[31:0] [15:8] \builder_csrbank12_reload1_r + assign $0\libresocsim_reload_storage[31:0] [15:8] \libresocsim_csrbank5_reload1_r case end - attribute \src "ls180.v:9731.2-9733.5" - switch \builder_csrbank12_reload0_re - attribute \src "ls180.v:9731.6-9731.34" + attribute \src "ls180.v:5258.2-5260.5" + switch \libresocsim_csrbank5_reload0_re + attribute \src "ls180.v:5258.6-5258.37" case 1'1 - assign $0\main_libresocsim_reload_storage[31:0] [7:0] \builder_csrbank12_reload0_r + assign $0\libresocsim_reload_storage[31:0] [7:0] \libresocsim_csrbank5_reload0_r case end - attribute \src "ls180.v:9735.2-9737.5" - switch \builder_csrbank12_en0_re - attribute \src "ls180.v:9735.6-9735.30" + attribute \src "ls180.v:5262.2-5264.5" + switch \libresocsim_csrbank5_en0_re + attribute \src "ls180.v:5262.6-5262.33" case 1'1 - assign $0\main_libresocsim_en_storage[0:0] \builder_csrbank12_en0_r + assign $0\libresocsim_en_storage[0:0] \libresocsim_csrbank5_en0_r case end - attribute \src "ls180.v:9739.2-9741.5" - switch \builder_csrbank12_update_value0_re - attribute \src "ls180.v:9739.6-9739.40" + attribute \src "ls180.v:5266.2-5268.5" + switch \libresocsim_csrbank5_update_value0_re + attribute \src "ls180.v:5266.6-5266.43" case 1'1 - assign $0\main_libresocsim_update_value_storage[0:0] \builder_csrbank12_update_value0_r + assign $0\libresocsim_update_value_storage[0:0] \libresocsim_csrbank5_update_value0_r case end - attribute \src "ls180.v:9743.2-9745.5" - switch \builder_csrbank12_ev_enable0_re - attribute \src "ls180.v:9743.6-9743.37" + attribute \src "ls180.v:5270.2-5272.5" + switch \libresocsim_csrbank5_ev_enable0_re + attribute \src "ls180.v:5270.6-5270.40" case 1'1 - assign $0\main_libresocsim_eventmanager_storage[0:0] \builder_csrbank12_ev_enable0_r + assign $0\libresocsim_eventmanager_storage[0:0] \libresocsim_csrbank5_ev_enable0_r case end - attribute \src "ls180.v:9748.2-9775.5" - switch \builder_csrbank13_sel - attribute \src "ls180.v:9748.6-9748.27" + attribute \src "ls180.v:5275.2-5302.5" + switch \libresocsim_csrbank6_sel + attribute \src "ls180.v:5275.6-5275.30" case 1'1 - attribute \src "ls180.v:9749.3-9774.10" - switch \builder_interface13_bank_bus_adr [2:0] + attribute \src "ls180.v:5276.3-5301.10" + switch \libresocsim_interface6_bank_bus_adr [2:0] attribute \src "ls180.v:0.0-0.0" case 3'000 - assign $0\builder_interface13_bank_bus_dat_r[7:0] \main_uart_rxtx_w + assign $0\libresocsim_interface6_bank_bus_dat_r[7:0] \rxtx_w attribute \src "ls180.v:0.0-0.0" case 3'001 - assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_txfull_w } + assign $0\libresocsim_interface6_bank_bus_dat_r[7:0] { 7'0000000 \libresocsim_csrbank6_txfull_w } attribute \src "ls180.v:0.0-0.0" case 3'010 - assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_rxempty_w } + assign $0\libresocsim_interface6_bank_bus_dat_r[7:0] { 7'0000000 \libresocsim_csrbank6_rxempty_w } attribute \src "ls180.v:0.0-0.0" case 3'011 - assign $0\builder_interface13_bank_bus_dat_r[7:0] { 6'000000 \main_uart_eventmanager_status_w } + assign $0\libresocsim_interface6_bank_bus_dat_r[7:0] { 6'000000 \eventmanager_status_w } attribute \src "ls180.v:0.0-0.0" case 3'100 - assign $0\builder_interface13_bank_bus_dat_r[7:0] { 6'000000 \main_uart_eventmanager_pending_w } + assign $0\libresocsim_interface6_bank_bus_dat_r[7:0] { 6'000000 \eventmanager_pending_w } attribute \src "ls180.v:0.0-0.0" case 3'101 - assign $0\builder_interface13_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank13_ev_enable0_w } + assign $0\libresocsim_interface6_bank_bus_dat_r[7:0] { 6'000000 \libresocsim_csrbank6_ev_enable0_w } attribute \src "ls180.v:0.0-0.0" case 3'110 - assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_txempty_w } + assign $0\libresocsim_interface6_bank_bus_dat_r[7:0] { 7'0000000 \libresocsim_csrbank6_txempty_w } attribute \src "ls180.v:0.0-0.0" case 3'111 - assign $0\builder_interface13_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank13_rxfull_w } + assign $0\libresocsim_interface6_bank_bus_dat_r[7:0] { 7'0000000 \libresocsim_csrbank6_rxfull_w } case end case end - attribute \src "ls180.v:9776.2-9778.5" - switch \builder_csrbank13_ev_enable0_re - attribute \src "ls180.v:9776.6-9776.37" + attribute \src "ls180.v:5303.2-5305.5" + switch \libresocsim_csrbank6_ev_enable0_re + attribute \src "ls180.v:5303.6-5303.40" case 1'1 - assign $0\main_uart_eventmanager_storage[1:0] \builder_csrbank13_ev_enable0_r + assign $0\eventmanager_storage[1:0] \libresocsim_csrbank6_ev_enable0_r case end - attribute \src "ls180.v:9781.2-9796.5" - switch \builder_csrbank14_sel - attribute \src "ls180.v:9781.6-9781.27" + attribute \src "ls180.v:5308.2-5323.5" + switch \libresocsim_csrbank7_sel + attribute \src "ls180.v:5308.6-5308.30" case 1'1 - attribute \src "ls180.v:9782.3-9795.10" - switch \builder_interface14_bank_bus_adr [1:0] + attribute \src "ls180.v:5309.3-5322.10" + switch \libresocsim_interface7_bank_bus_adr [1:0] attribute \src "ls180.v:0.0-0.0" case 2'00 - assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word3_w + assign $0\libresocsim_interface7_bank_bus_dat_r[7:0] \libresocsim_csrbank7_tuning_word3_w attribute \src "ls180.v:0.0-0.0" case 2'01 - assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word2_w + assign $0\libresocsim_interface7_bank_bus_dat_r[7:0] \libresocsim_csrbank7_tuning_word2_w attribute \src "ls180.v:0.0-0.0" case 2'10 - assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word1_w + assign $0\libresocsim_interface7_bank_bus_dat_r[7:0] \libresocsim_csrbank7_tuning_word1_w attribute \src "ls180.v:0.0-0.0" case 2'11 - assign $0\builder_interface14_bank_bus_dat_r[7:0] \builder_csrbank14_tuning_word0_w + assign $0\libresocsim_interface7_bank_bus_dat_r[7:0] \libresocsim_csrbank7_tuning_word0_w case end case end - attribute \src "ls180.v:9797.2-9799.5" - switch \builder_csrbank14_tuning_word3_re - attribute \src "ls180.v:9797.6-9797.39" + attribute \src "ls180.v:5324.2-5326.5" + switch \libresocsim_csrbank7_tuning_word3_re + attribute \src "ls180.v:5324.6-5324.42" case 1'1 - assign $0\main_uart_phy_storage[31:0] [31:24] \builder_csrbank14_tuning_word3_r + assign $0\uart_phy_storage[31:0] [31:24] \libresocsim_csrbank7_tuning_word3_r case end - attribute \src "ls180.v:9800.2-9802.5" - switch \builder_csrbank14_tuning_word2_re - attribute \src "ls180.v:9800.6-9800.39" + attribute \src "ls180.v:5327.2-5329.5" + switch \libresocsim_csrbank7_tuning_word2_re + attribute \src "ls180.v:5327.6-5327.42" case 1'1 - assign $0\main_uart_phy_storage[31:0] [23:16] \builder_csrbank14_tuning_word2_r + assign $0\uart_phy_storage[31:0] [23:16] \libresocsim_csrbank7_tuning_word2_r case end - attribute \src "ls180.v:9803.2-9805.5" - switch \builder_csrbank14_tuning_word1_re - attribute \src "ls180.v:9803.6-9803.39" + attribute \src "ls180.v:5330.2-5332.5" + switch \libresocsim_csrbank7_tuning_word1_re + attribute \src "ls180.v:5330.6-5330.42" case 1'1 - assign $0\main_uart_phy_storage[31:0] [15:8] \builder_csrbank14_tuning_word1_r + assign $0\uart_phy_storage[31:0] [15:8] \libresocsim_csrbank7_tuning_word1_r case end - attribute \src "ls180.v:9806.2-9808.5" - switch \builder_csrbank14_tuning_word0_re - attribute \src "ls180.v:9806.6-9806.39" + attribute \src "ls180.v:5333.2-5335.5" + switch \libresocsim_csrbank7_tuning_word0_re + attribute \src "ls180.v:5333.6-5333.42" case 1'1 - assign $0\main_uart_phy_storage[31:0] [7:0] \builder_csrbank14_tuning_word0_r + assign $0\uart_phy_storage[31:0] [7:0] \libresocsim_csrbank7_tuning_word0_r case end - attribute \src "ls180.v:9810.2-10105.5" + attribute \src "ls180.v:5337.2-5484.5" switch \sys_rst_1 - attribute \src "ls180.v:9810.6-9810.15" - case 1'1 - assign $0\main_libresocsim_reset_storage[0:0] 1'0 - assign $0\main_libresocsim_reset_re[0:0] 1'0 - assign $0\main_libresocsim_scratch_storage[31:0] 305419896 - assign $0\main_libresocsim_scratch_re[0:0] 1'0 - assign $0\main_libresocsim_bus_errors[31:0] 0 - assign $0\spimaster_clk[0:0] 1'0 - assign $0\spimaster_mosi[0:0] 1'0 - assign $0\spimaster_cs_n[0:0] 1'0 - assign $0\spisdcard_clk[0:0] 1'0 - assign $0\spisdcard_mosi[0:0] 1'0 - assign $0\spisdcard_cs_n[0:0] 1'0 - assign $0\uart_tx[0:0] 1'1 - assign $0\pwm[1:0] 2'00 - assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 - assign $0\main_libresocsim_load_storage[31:0] 0 - assign $0\main_libresocsim_load_re[0:0] 1'0 - assign $0\main_libresocsim_reload_storage[31:0] 0 - assign $0\main_libresocsim_reload_re[0:0] 1'0 - assign $0\main_libresocsim_en_storage[0:0] 1'0 - assign $0\main_libresocsim_en_re[0:0] 1'0 - assign $0\main_libresocsim_update_value_storage[0:0] 1'0 - assign $0\main_libresocsim_update_value_re[0:0] 1'0 - assign $0\main_libresocsim_value_status[31:0] 0 - assign $0\main_libresocsim_zero_pending[0:0] 1'0 - assign $0\main_libresocsim_zero_old_trigger[0:0] 1'0 - assign $0\main_libresocsim_eventmanager_storage[0:0] 1'0 - assign $0\main_libresocsim_eventmanager_re[0:0] 1'0 - assign $0\main_libresocsim_value[31:0] 0 - assign $0\main_ram_bus_ram_bus_ack[0:0] 1'0 - assign $0\main_converter0_counter[0:0] 1'0 - assign $0\main_converter1_counter[0:0] 1'0 - assign $0\main_dfi_p0_rddata_valid[0:0] 1'0 - assign $0\main_rddata_en[2:0] 3'000 - assign $0\main_sdram_storage[3:0] 4'0001 - assign $0\main_sdram_re[0:0] 1'0 - assign $0\main_sdram_command_storage[5:0] 6'000000 - assign $0\main_sdram_command_re[0:0] 1'0 - assign $0\main_sdram_address_re[0:0] 1'0 - assign $0\main_sdram_baddress_re[0:0] 1'0 - assign $0\main_sdram_wrdata_re[0:0] 1'0 - assign $0\main_sdram_status[15:0] 16'0000000000000000 - assign $0\main_sdram_dfi_p0_address[12:0] 13'0000000000000 - assign $0\main_sdram_dfi_p0_bank[1:0] 2'00 - assign $0\main_sdram_dfi_p0_cas_n[0:0] 1'1 - assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'1 - assign $0\main_sdram_dfi_p0_ras_n[0:0] 1'1 - assign $0\main_sdram_dfi_p0_we_n[0:0] 1'1 - assign $0\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 - assign $0\main_sdram_dfi_p0_rddata_en[0:0] 1'0 - assign $0\main_sdram_timer_count1[9:0] 10'1100001101 - assign $0\main_sdram_postponer_req_o[0:0] 1'0 - assign $0\main_sdram_postponer_count[0:0] 1'0 - assign $0\main_sdram_sequencer_done1[0:0] 1'0 - assign $0\main_sdram_sequencer_counter[3:0] 4'0000 - assign $0\main_sdram_sequencer_count[0:0] 1'0 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 - assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 - assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine0_row[12:0] 13'0000000000000 - assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0 - assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 - assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 - assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine1_row[12:0] 13'0000000000000 - assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0 - assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 - assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 - assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine2_row[12:0] 13'0000000000000 - assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0 - assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 - assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 - assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 - assign $0\main_sdram_bankmachine3_row[12:0] 13'0000000000000 - assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0 - assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 - assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 - assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 - assign $0\main_sdram_choose_req_grant[1:0] 2'00 - assign $0\main_sdram_tccdcon_ready[0:0] 1'0 - assign $0\main_sdram_tccdcon_count[0:0] 1'0 - assign $0\main_sdram_twtrcon_ready[0:0] 1'0 - assign $0\main_sdram_twtrcon_count[2:0] 3'000 - assign $0\main_sdram_time0[4:0] 5'00000 - assign $0\main_sdram_time1[3:0] 4'0000 - assign $0\main_socbushandler_counter[0:0] 1'0 - assign $0\main_converter_counter[0:0] 1'0 - assign $0\main_cmd_consumed[0:0] 1'0 - assign $0\main_wdata_consumed[0:0] 1'0 - assign $0\main_uart_phy_storage[31:0] 9895604 - assign $0\main_uart_phy_re[0:0] 1'0 - assign $0\main_uart_phy_sink_ready[0:0] 1'0 - assign $0\main_uart_phy_uart_clk_txen[0:0] 1'0 - assign $0\main_uart_phy_tx_busy[0:0] 1'0 - assign $0\main_uart_phy_source_valid[0:0] 1'0 - assign $0\main_uart_phy_uart_clk_rxen[0:0] 1'0 - assign $0\main_uart_phy_rx_r[0:0] 1'0 - assign $0\main_uart_phy_rx_busy[0:0] 1'0 - assign $0\main_uart_tx_pending[0:0] 1'0 - assign $0\main_uart_tx_old_trigger[0:0] 1'0 - assign $0\main_uart_rx_pending[0:0] 1'0 - assign $0\main_uart_rx_old_trigger[0:0] 1'0 - assign $0\main_uart_eventmanager_storage[1:0] 2'00 - assign $0\main_uart_eventmanager_re[0:0] 1'0 - assign $0\main_uart_tx_fifo_readable[0:0] 1'0 - assign $0\main_uart_tx_fifo_level0[4:0] 5'00000 - assign $0\main_uart_tx_fifo_produce[3:0] 4'0000 - assign $0\main_uart_tx_fifo_consume[3:0] 4'0000 - assign $0\main_uart_rx_fifo_readable[0:0] 1'0 - assign $0\main_uart_rx_fifo_level0[4:0] 5'00000 - assign $0\main_uart_rx_fifo_produce[3:0] 4'0000 - assign $0\main_uart_rx_fifo_consume[3:0] 4'0000 - assign $0\main_gpiotristateasic1_oe_storage[15:0] 16'0000000000000000 - assign $0\main_gpiotristateasic1_oe_re[0:0] 1'0 - assign $0\main_gpiotristateasic1_out_storage[15:0] 16'0000000000000000 - assign $0\main_gpiotristateasic1_out_re[0:0] 1'0 - assign $0\main_spimaster5_miso[7:0] 8'00000000 - assign $0\main_spimaster11_storage[15:0] 16'0000000000000000 - assign $0\main_spimaster12_re[0:0] 1'0 - assign $0\main_spimaster17_re[0:0] 1'0 - assign $0\main_spimaster21_storage[0:0] 1'1 - assign $0\main_spimaster22_re[0:0] 1'0 - assign $0\main_spimaster23_storage[0:0] 1'0 - assign $0\main_spimaster24_re[0:0] 1'0 - assign $0\main_spimaster27_count[2:0] 3'000 - assign $0\main_spimaster30_clk_divider[15:0] 16'0000000000000000 - assign $0\main_spimaster33_mosi_data[7:0] 8'00000000 - assign $0\main_spimaster34_mosi_sel[2:0] 3'000 - assign $0\main_spimaster35_miso_data[7:0] 8'00000000 - assign $0\main_spisdcard_miso[7:0] 8'00000000 - assign $0\main_spisdcard_control_storage[15:0] 16'0000000000000000 - assign $0\main_spisdcard_control_re[0:0] 1'0 - assign $0\main_spisdcard_mosi_re[0:0] 1'0 - assign $0\main_spisdcard_cs_storage[0:0] 1'1 - assign $0\main_spisdcard_cs_re[0:0] 1'0 - assign $0\main_spisdcard_loopback_storage[0:0] 1'0 - assign $0\main_spisdcard_loopback_re[0:0] 1'0 - assign $0\main_spisdcard_count[2:0] 3'000 - assign $0\main_spisdcard_clk_divider1[15:0] 16'0000000000000000 - assign $0\main_spisdcard_mosi_data[7:0] 8'00000000 - assign $0\main_spisdcard_mosi_sel[2:0] 3'000 - assign $0\main_spisdcard_miso_data[7:0] 8'00000000 - assign $0\main_spimaster1_storage[15:0] 16'0000000001111101 - assign $0\main_spimaster1_re[0:0] 1'0 - assign $0\main_dummy[23:0] 24'000000000000000000000000 - assign $0\main_pwm0_enable_storage[0:0] 1'0 - assign $0\main_pwm0_enable_re[0:0] 1'0 - assign $0\main_pwm0_width_re[0:0] 1'0 - assign $0\main_pwm0_period_re[0:0] 1'0 - assign $0\main_pwm1_enable_storage[0:0] 1'0 - assign $0\main_pwm1_enable_re[0:0] 1'0 - assign $0\main_pwm1_width_re[0:0] 1'0 - assign $0\main_pwm1_period_re[0:0] 1'0 - assign $0\main_i2c_storage[2:0] 3'000 - assign $0\main_i2c_re[0:0] 1'0 - assign $0\main_sdphy_clocker_storage[8:0] 9'100000000 - assign $0\main_sdphy_clocker_re[0:0] 1'0 - assign $0\main_sdphy_clocker_clk0[0:0] 1'0 - assign $0\main_sdphy_clocker_clks[8:0] 9'000000000 - assign $0\main_sdphy_clocker_clk_d[0:0] 1'0 - assign $0\main_sdphy_init_count[7:0] 8'00000000 - assign $0\main_sdphy_cmdw_count[7:0] 8'00000000 - assign $0\main_sdphy_cmdr_timeout[31:0] 500000 - assign $0\main_sdphy_cmdr_count[7:0] 8'00000000 - assign $0\main_sdphy_cmdr_cmdr_run[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] 3'000 - assign $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] 1'0 - assign $0\main_sdphy_cmdr_cmdr_reset[0:0] 1'0 - assign $0\main_sdphy_dataw_count[7:0] 8'00000000 - assign $0\main_sdphy_dataw_crcr_run[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_converter_demux[2:0] 3'000 - assign $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] 1'0 - assign $0\main_sdphy_dataw_crcr_reset[0:0] 1'0 - assign $0\main_sdphy_datar_timeout[31:0] 500000 - assign $0\main_sdphy_datar_count[9:0] 10'0000000000 - assign $0\main_sdphy_datar_datar_run[0:0] 1'0 - assign $0\main_sdphy_datar_datar_converter_demux[0:0] 1'0 - assign $0\main_sdphy_datar_datar_converter_strobe_all[0:0] 1'0 - assign $0\main_sdphy_datar_datar_buf_source_valid[0:0] 1'0 - assign $0\main_sdphy_datar_datar_reset[0:0] 1'0 - assign $0\main_sdcore_cmd_argument_storage[31:0] 0 - assign $0\main_sdcore_cmd_argument_re[0:0] 1'0 - assign $0\main_sdcore_cmd_command_storage[31:0] 0 - assign $0\main_sdcore_cmd_command_re[0:0] 1'0 - assign $0\main_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign $0\main_sdcore_block_length_storage[9:0] 10'0000000000 - assign $0\main_sdcore_block_length_re[0:0] 1'0 - assign $0\main_sdcore_block_count_storage[31:0] 0 - assign $0\main_sdcore_block_count_re[0:0] 1'0 - assign $0\main_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 - assign $0\main_sdcore_crc16_inserter_cnt[2:0] 3'000 - assign $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_val[7:0] 8'00000000 - assign $0\main_sdcore_crc16_checker_cnt[3:0] 4'0000 - assign $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000 - assign $0\main_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000 - assign $0\main_sdcore_cmd_count[2:0] 3'000 - assign $0\main_sdcore_cmd_done[0:0] 1'0 - assign $0\main_sdcore_cmd_error[0:0] 1'0 - assign $0\main_sdcore_cmd_timeout[0:0] 1'0 - assign $0\main_sdcore_data_count[31:0] 0 - assign $0\main_sdcore_data_done[0:0] 1'0 - assign $0\main_sdcore_data_error[0:0] 1'0 - assign $0\main_sdcore_data_timeout[0:0] 1'0 - assign $0\main_sdblock2mem_fifo_level[5:0] 6'000000 - assign $0\main_sdblock2mem_fifo_produce[4:0] 5'00000 - assign $0\main_sdblock2mem_fifo_consume[4:0] 5'00000 - assign $0\main_sdblock2mem_converter_demux[2:0] 3'000 - assign $0\main_sdblock2mem_converter_strobe_all[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0 - assign $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0 - assign $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] 0 - assign $0\main_sdmem2block_dma_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\main_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\main_sdmem2block_dma_base_re[0:0] 1'0 - assign $0\main_sdmem2block_dma_length_storage[31:0] 0 - assign $0\main_sdmem2block_dma_length_re[0:0] 1'0 - assign $0\main_sdmem2block_dma_enable_storage[0:0] 1'0 - assign $0\main_sdmem2block_dma_enable_re[0:0] 1'0 - assign $0\main_sdmem2block_dma_loop_storage[0:0] 1'0 - assign $0\main_sdmem2block_dma_loop_re[0:0] 1'0 - assign $0\main_sdmem2block_dma_offset[31:0] 0 - assign $0\main_sdmem2block_converter_mux[2:0] 3'000 - assign $0\main_sdmem2block_fifo_level[5:0] 6'000000 - assign $0\main_sdmem2block_fifo_produce[4:0] 5'00000 - assign $0\main_sdmem2block_fifo_consume[4:0] 5'00000 - assign $0\builder_converter0_state[0:0] 1'0 - assign $0\builder_converter1_state[0:0] 1'0 - assign $0\builder_converter2_state[0:0] 1'0 - assign $0\builder_refresher_state[1:0] 2'00 - assign $0\builder_bankmachine0_state[2:0] 3'000 - assign $0\builder_bankmachine1_state[2:0] 3'000 - assign $0\builder_bankmachine2_state[2:0] 3'000 - assign $0\builder_bankmachine3_state[2:0] 3'000 - assign $0\builder_multiplexer_state[2:0] 3'000 - assign $0\builder_new_master_wdata_ready[0:0] 1'0 - assign $0\builder_new_master_rdata_valid0[0:0] 1'0 - assign $0\builder_new_master_rdata_valid1[0:0] 1'0 - assign $0\builder_new_master_rdata_valid2[0:0] 1'0 - assign $0\builder_new_master_rdata_valid3[0:0] 1'0 - assign $0\builder_converter_state[0:0] 1'0 - assign $0\builder_spimaster0_state[1:0] 2'00 - assign $0\builder_spimaster1_state[1:0] 2'00 - assign $0\builder_sdphy_sdphyinit_state[0:0] 1'0 - assign $0\builder_sdphy_sdphycmdw_state[1:0] 2'00 - assign $0\builder_sdphy_sdphycmdr_state[2:0] 3'000 - assign $0\builder_sdphy_sdphycrcr_state[0:0] 1'0 - assign $0\builder_sdphy_fsm_state[2:0] 3'000 - assign $0\builder_sdphy_sdphydatar_state[2:0] 3'000 - assign $0\builder_sdcore_crcupstreaminserter_state[0:0] 1'0 - assign $0\builder_sdcore_fsm_state[2:0] 3'000 - assign $0\builder_sdblock2memdma_state[1:0] 2'00 - assign $0\builder_sdmem2blockdma_fsm_state[0:0] 1'0 - assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 - assign $0\builder_libresocsim_we[0:0] 1'0 - assign $0\builder_grant[2:0] 3'000 - assign $0\builder_slave_sel_r[5:0] 6'000000 - assign $0\builder_count[19:0] 20'11110100001001000000 - assign $0\builder_state[1:0] 2'00 + attribute \src "ls180.v:5337.6-5337.15" + case 1'1 + assign $0\libresocsim_reset_storage[0:0] 1'0 + assign $0\libresocsim_reset_re[0:0] 1'0 + assign $0\libresocsim_scratch_storage[31:0] 305419896 + assign $0\libresocsim_scratch_re[0:0] 1'0 + assign $0\libresocsim_bus_errors[31:0] 0 + assign $0\libresocsim_libresoc_constraintmanager_obj_uart_tx[0:0] 1'1 + assign $0\libresocsim_ram_bus_ack[0:0] 1'0 + assign $0\libresocsim_load_storage[31:0] 0 + assign $0\libresocsim_load_re[0:0] 1'0 + assign $0\libresocsim_reload_storage[31:0] 0 + assign $0\libresocsim_reload_re[0:0] 1'0 + assign $0\libresocsim_en_storage[0:0] 1'0 + assign $0\libresocsim_en_re[0:0] 1'0 + assign $0\libresocsim_update_value_storage[0:0] 1'0 + assign $0\libresocsim_update_value_re[0:0] 1'0 + assign $0\libresocsim_value_status[31:0] 0 + assign $0\libresocsim_zero_pending[0:0] 1'0 + assign $0\libresocsim_zero_old_trigger[0:0] 1'0 + assign $0\libresocsim_eventmanager_storage[0:0] 1'0 + assign $0\libresocsim_eventmanager_re[0:0] 1'0 + assign $0\libresocsim_value[31:0] 0 + assign $0\ram_bus_ram_bus_ack[0:0] 1'0 + assign $0\converter0_counter[0:0] 1'0 + assign $0\converter1_counter[0:0] 1'0 + assign $0\dfi_p0_rddata_valid[0:0] 1'0 + assign $0\rddata_en[2:0] 3'000 + assign $0\sdram_storage[3:0] 4'0001 + assign $0\sdram_re[0:0] 1'0 + assign $0\sdram_command_storage[5:0] 6'000000 + assign $0\sdram_command_re[0:0] 1'0 + assign $0\sdram_address_re[0:0] 1'0 + assign $0\sdram_baddress_re[0:0] 1'0 + assign $0\sdram_wrdata_re[0:0] 1'0 + assign $0\sdram_status[15:0] 16'0000000000000000 + assign $0\sdram_dfi_p0_address[12:0] 13'0000000000000 + assign $0\sdram_dfi_p0_bank[1:0] 2'00 + assign $0\sdram_dfi_p0_cas_n[0:0] 1'1 + assign $0\sdram_dfi_p0_cs_n[0:0] 1'1 + assign $0\sdram_dfi_p0_ras_n[0:0] 1'1 + assign $0\sdram_dfi_p0_we_n[0:0] 1'1 + assign $0\sdram_dfi_p0_wrdata_en[0:0] 1'0 + assign $0\sdram_dfi_p0_rddata_en[0:0] 1'0 + assign $0\sdram_timer_count1[9:0] 10'1100001101 + assign $0\sdram_postponer_req_o[0:0] 1'0 + assign $0\sdram_postponer_count[0:0] 1'0 + assign $0\sdram_sequencer_done1[0:0] 1'0 + assign $0\sdram_sequencer_counter[3:0] 4'0000 + assign $0\sdram_sequencer_count[0:0] 1'0 + assign $0\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 + assign $0\sdram_bankmachine0_row[12:0] 13'0000000000000 + assign $0\sdram_bankmachine0_row_opened[0:0] 1'0 + assign $0\sdram_bankmachine0_twtpcon_ready[0:0] 1'0 + assign $0\sdram_bankmachine0_twtpcon_count[2:0] 3'000 + assign $0\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 + assign $0\sdram_bankmachine1_row[12:0] 13'0000000000000 + assign $0\sdram_bankmachine1_row_opened[0:0] 1'0 + assign $0\sdram_bankmachine1_twtpcon_ready[0:0] 1'0 + assign $0\sdram_bankmachine1_twtpcon_count[2:0] 3'000 + assign $0\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 + assign $0\sdram_bankmachine2_row[12:0] 13'0000000000000 + assign $0\sdram_bankmachine2_row_opened[0:0] 1'0 + assign $0\sdram_bankmachine2_twtpcon_ready[0:0] 1'0 + assign $0\sdram_bankmachine2_twtpcon_count[2:0] 3'000 + assign $0\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 + assign $0\sdram_bankmachine3_row[12:0] 13'0000000000000 + assign $0\sdram_bankmachine3_row_opened[0:0] 1'0 + assign $0\sdram_bankmachine3_twtpcon_ready[0:0] 1'0 + assign $0\sdram_bankmachine3_twtpcon_count[2:0] 3'000 + assign $0\sdram_choose_cmd_grant[1:0] 2'00 + assign $0\sdram_choose_req_grant[1:0] 2'00 + assign $0\sdram_tccdcon_ready[0:0] 1'0 + assign $0\sdram_tccdcon_count[0:0] 1'0 + assign $0\sdram_twtrcon_ready[0:0] 1'0 + assign $0\sdram_twtrcon_count[2:0] 3'000 + assign $0\sdram_time0[4:0] 5'00000 + assign $0\sdram_time1[3:0] 4'0000 + assign $0\socbushandler_counter[0:0] 1'0 + assign $0\converter_counter[0:0] 1'0 + assign $0\cmd_consumed[0:0] 1'0 + assign $0\wdata_consumed[0:0] 1'0 + assign $0\uart_phy_storage[31:0] 9895604 + assign $0\uart_phy_re[0:0] 1'0 + assign $0\uart_phy_sink_ready[0:0] 1'0 + assign $0\uart_phy_uart_clk_txen[0:0] 1'0 + assign $0\uart_phy_tx_busy[0:0] 1'0 + assign $0\uart_phy_source_valid[0:0] 1'0 + assign $0\uart_phy_uart_clk_rxen[0:0] 1'0 + assign $0\uart_phy_rx_r[0:0] 1'0 + assign $0\uart_phy_rx_busy[0:0] 1'0 + assign $0\tx_pending[0:0] 1'0 + assign $0\tx_old_trigger[0:0] 1'0 + assign $0\rx_pending[0:0] 1'0 + assign $0\rx_old_trigger[0:0] 1'0 + assign $0\eventmanager_storage[1:0] 2'00 + assign $0\eventmanager_re[0:0] 1'0 + assign $0\tx_fifo_readable[0:0] 1'0 + assign $0\tx_fifo_level0[4:0] 5'00000 + assign $0\tx_fifo_produce[3:0] 4'0000 + assign $0\tx_fifo_consume[3:0] 4'0000 + assign $0\rx_fifo_readable[0:0] 1'0 + assign $0\rx_fifo_level0[4:0] 5'00000 + assign $0\rx_fifo_produce[3:0] 4'0000 + assign $0\rx_fifo_consume[3:0] 4'0000 + assign $0\gpio0_oe_storage[7:0] 8'00000000 + assign $0\gpio0_oe_re[0:0] 1'0 + assign $0\gpio0_out_storage[7:0] 8'00000000 + assign $0\gpio0_out_re[0:0] 1'0 + assign $0\gpio1_oe_storage[7:0] 8'00000000 + assign $0\gpio1_oe_re[0:0] 1'0 + assign $0\gpio1_out_storage[7:0] 8'00000000 + assign $0\gpio1_out_re[0:0] 1'0 + assign $0\dummy[29:0] 30'000000000000000000000000000000 + assign $0\i2c_storage[2:0] 3'000 + assign $0\i2c_re[0:0] 1'0 + assign $0\subfragments_converter0_state[0:0] 1'0 + assign $0\subfragments_converter1_state[0:0] 1'0 + assign $0\subfragments_converter2_state[0:0] 1'0 + assign $0\subfragments_refresher_state[1:0] 2'00 + assign $0\subfragments_bankmachine0_state[2:0] 3'000 + assign $0\subfragments_bankmachine1_state[2:0] 3'000 + assign $0\subfragments_bankmachine2_state[2:0] 3'000 + assign $0\subfragments_bankmachine3_state[2:0] 3'000 + assign $0\subfragments_multiplexer_state[2:0] 3'000 + assign $0\subfragments_new_master_wdata_ready[0:0] 1'0 + assign $0\subfragments_new_master_rdata_valid0[0:0] 1'0 + assign $0\subfragments_new_master_rdata_valid1[0:0] 1'0 + assign $0\subfragments_new_master_rdata_valid2[0:0] 1'0 + assign $0\subfragments_new_master_rdata_valid3[0:0] 1'0 + assign $0\subfragments_state[0:0] 1'0 + assign $0\libresocsim_libresocsim_we[0:0] 1'0 + assign $0\libresocsim_grant[1:0] 2'00 + assign $0\libresocsim_slave_sel_r[5:0] 6'000000 + assign $0\libresocsim_count[19:0] 20'11110100001001000000 + assign $0\libresocsim_state[1:0] 2'00 + case + end + sync posedge \sys_clk_1 + update \libresocsim_reset_storage $0\libresocsim_reset_storage[0:0] + update \libresocsim_reset_re $0\libresocsim_reset_re[0:0] + update \libresocsim_scratch_storage $0\libresocsim_scratch_storage[31:0] + update \libresocsim_scratch_re $0\libresocsim_scratch_re[0:0] + update \libresocsim_bus_errors $0\libresocsim_bus_errors[31:0] + update \libresocsim_libresoc_constraintmanager_obj_uart_tx $0\libresocsim_libresoc_constraintmanager_obj_uart_tx[0:0] + update \libresocsim_ram_bus_ack $0\libresocsim_ram_bus_ack[0:0] + update \libresocsim_load_storage $0\libresocsim_load_storage[31:0] + update \libresocsim_load_re $0\libresocsim_load_re[0:0] + update \libresocsim_reload_storage $0\libresocsim_reload_storage[31:0] + update \libresocsim_reload_re $0\libresocsim_reload_re[0:0] + update \libresocsim_en_storage $0\libresocsim_en_storage[0:0] + update \libresocsim_en_re $0\libresocsim_en_re[0:0] + update \libresocsim_update_value_storage $0\libresocsim_update_value_storage[0:0] + update \libresocsim_update_value_re $0\libresocsim_update_value_re[0:0] + update \libresocsim_value_status $0\libresocsim_value_status[31:0] + update \libresocsim_zero_pending $0\libresocsim_zero_pending[0:0] + update \libresocsim_zero_old_trigger $0\libresocsim_zero_old_trigger[0:0] + update \libresocsim_eventmanager_storage $0\libresocsim_eventmanager_storage[0:0] + update \libresocsim_eventmanager_re $0\libresocsim_eventmanager_re[0:0] + update \libresocsim_value $0\libresocsim_value[31:0] + update \ram_bus_ram_bus_ack $0\ram_bus_ram_bus_ack[0:0] + update \converter0_counter $0\converter0_counter[0:0] + update \converter0_dat_r $0\converter0_dat_r[63:0] + update \converter1_counter $0\converter1_counter[0:0] + update \converter1_dat_r $0\converter1_dat_r[63:0] + update \dfi_p0_rddata_valid $0\dfi_p0_rddata_valid[0:0] + update \rddata_en $0\rddata_en[2:0] + update \sdram_storage $0\sdram_storage[3:0] + update \sdram_re $0\sdram_re[0:0] + update \sdram_command_storage $0\sdram_command_storage[5:0] + update \sdram_command_re $0\sdram_command_re[0:0] + update \sdram_address_storage $0\sdram_address_storage[12:0] + update \sdram_address_re $0\sdram_address_re[0:0] + update \sdram_baddress_storage $0\sdram_baddress_storage[1:0] + update \sdram_baddress_re $0\sdram_baddress_re[0:0] + update \sdram_wrdata_storage $0\sdram_wrdata_storage[15:0] + update \sdram_wrdata_re $0\sdram_wrdata_re[0:0] + update \sdram_status $0\sdram_status[15:0] + update \sdram_dfi_p0_address $0\sdram_dfi_p0_address[12:0] + update \sdram_dfi_p0_bank $0\sdram_dfi_p0_bank[1:0] + update \sdram_dfi_p0_cas_n $0\sdram_dfi_p0_cas_n[0:0] + update \sdram_dfi_p0_cs_n $0\sdram_dfi_p0_cs_n[0:0] + update \sdram_dfi_p0_ras_n $0\sdram_dfi_p0_ras_n[0:0] + update \sdram_dfi_p0_we_n $0\sdram_dfi_p0_we_n[0:0] + update \sdram_dfi_p0_wrdata_en $0\sdram_dfi_p0_wrdata_en[0:0] + update \sdram_dfi_p0_rddata_en $0\sdram_dfi_p0_rddata_en[0:0] + update \sdram_cmd_payload_a $0\sdram_cmd_payload_a[12:0] + update \sdram_cmd_payload_ba $0\sdram_cmd_payload_ba[1:0] + update \sdram_cmd_payload_cas $0\sdram_cmd_payload_cas[0:0] + update \sdram_cmd_payload_ras $0\sdram_cmd_payload_ras[0:0] + update \sdram_cmd_payload_we $0\sdram_cmd_payload_we[0:0] + update \sdram_timer_count1 $0\sdram_timer_count1[9:0] + update \sdram_postponer_req_o $0\sdram_postponer_req_o[0:0] + update \sdram_postponer_count $0\sdram_postponer_count[0:0] + update \sdram_sequencer_done1 $0\sdram_sequencer_done1[0:0] + update \sdram_sequencer_counter $0\sdram_sequencer_counter[3:0] + update \sdram_sequencer_count $0\sdram_sequencer_count[0:0] + update \sdram_bankmachine0_cmd_buffer_lookahead_level $0\sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + update \sdram_bankmachine0_cmd_buffer_lookahead_produce $0\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + update \sdram_bankmachine0_cmd_buffer_lookahead_consume $0\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + update \sdram_bankmachine0_cmd_buffer_source_valid $0\sdram_bankmachine0_cmd_buffer_source_valid[0:0] + update \sdram_bankmachine0_cmd_buffer_source_first $0\sdram_bankmachine0_cmd_buffer_source_first[0:0] + update \sdram_bankmachine0_cmd_buffer_source_last $0\sdram_bankmachine0_cmd_buffer_source_last[0:0] + update \sdram_bankmachine0_cmd_buffer_source_payload_we $0\sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + update \sdram_bankmachine0_cmd_buffer_source_payload_addr $0\sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + update \sdram_bankmachine0_row $0\sdram_bankmachine0_row[12:0] + update \sdram_bankmachine0_row_opened $0\sdram_bankmachine0_row_opened[0:0] + update \sdram_bankmachine0_twtpcon_ready $0\sdram_bankmachine0_twtpcon_ready[0:0] + update \sdram_bankmachine0_twtpcon_count $0\sdram_bankmachine0_twtpcon_count[2:0] + update \sdram_bankmachine1_cmd_buffer_lookahead_level $0\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + update \sdram_bankmachine1_cmd_buffer_lookahead_produce $0\sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + update \sdram_bankmachine1_cmd_buffer_lookahead_consume $0\sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + update \sdram_bankmachine1_cmd_buffer_source_valid $0\sdram_bankmachine1_cmd_buffer_source_valid[0:0] + update \sdram_bankmachine1_cmd_buffer_source_first $0\sdram_bankmachine1_cmd_buffer_source_first[0:0] + update \sdram_bankmachine1_cmd_buffer_source_last $0\sdram_bankmachine1_cmd_buffer_source_last[0:0] + update \sdram_bankmachine1_cmd_buffer_source_payload_we $0\sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + update \sdram_bankmachine1_cmd_buffer_source_payload_addr $0\sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + update \sdram_bankmachine1_row $0\sdram_bankmachine1_row[12:0] + update \sdram_bankmachine1_row_opened $0\sdram_bankmachine1_row_opened[0:0] + update \sdram_bankmachine1_twtpcon_ready $0\sdram_bankmachine1_twtpcon_ready[0:0] + update \sdram_bankmachine1_twtpcon_count $0\sdram_bankmachine1_twtpcon_count[2:0] + update \sdram_bankmachine2_cmd_buffer_lookahead_level $0\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + update \sdram_bankmachine2_cmd_buffer_lookahead_produce $0\sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + update \sdram_bankmachine2_cmd_buffer_lookahead_consume $0\sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + update \sdram_bankmachine2_cmd_buffer_source_valid $0\sdram_bankmachine2_cmd_buffer_source_valid[0:0] + update \sdram_bankmachine2_cmd_buffer_source_first $0\sdram_bankmachine2_cmd_buffer_source_first[0:0] + update \sdram_bankmachine2_cmd_buffer_source_last $0\sdram_bankmachine2_cmd_buffer_source_last[0:0] + update \sdram_bankmachine2_cmd_buffer_source_payload_we $0\sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + update \sdram_bankmachine2_cmd_buffer_source_payload_addr $0\sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + update \sdram_bankmachine2_row $0\sdram_bankmachine2_row[12:0] + update \sdram_bankmachine2_row_opened $0\sdram_bankmachine2_row_opened[0:0] + update \sdram_bankmachine2_twtpcon_ready $0\sdram_bankmachine2_twtpcon_ready[0:0] + update \sdram_bankmachine2_twtpcon_count $0\sdram_bankmachine2_twtpcon_count[2:0] + update \sdram_bankmachine3_cmd_buffer_lookahead_level $0\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + update \sdram_bankmachine3_cmd_buffer_lookahead_produce $0\sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + update \sdram_bankmachine3_cmd_buffer_lookahead_consume $0\sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + update \sdram_bankmachine3_cmd_buffer_source_valid $0\sdram_bankmachine3_cmd_buffer_source_valid[0:0] + update \sdram_bankmachine3_cmd_buffer_source_first $0\sdram_bankmachine3_cmd_buffer_source_first[0:0] + update \sdram_bankmachine3_cmd_buffer_source_last $0\sdram_bankmachine3_cmd_buffer_source_last[0:0] + update \sdram_bankmachine3_cmd_buffer_source_payload_we $0\sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + update \sdram_bankmachine3_cmd_buffer_source_payload_addr $0\sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + update \sdram_bankmachine3_row $0\sdram_bankmachine3_row[12:0] + update \sdram_bankmachine3_row_opened $0\sdram_bankmachine3_row_opened[0:0] + update \sdram_bankmachine3_twtpcon_ready $0\sdram_bankmachine3_twtpcon_ready[0:0] + update \sdram_bankmachine3_twtpcon_count $0\sdram_bankmachine3_twtpcon_count[2:0] + update \sdram_choose_cmd_grant $0\sdram_choose_cmd_grant[1:0] + update \sdram_choose_req_grant $0\sdram_choose_req_grant[1:0] + update \sdram_tccdcon_ready $0\sdram_tccdcon_ready[0:0] + update \sdram_tccdcon_count $0\sdram_tccdcon_count[0:0] + update \sdram_twtrcon_ready $0\sdram_twtrcon_ready[0:0] + update \sdram_twtrcon_count $0\sdram_twtrcon_count[2:0] + update \sdram_time0 $0\sdram_time0[4:0] + update \sdram_time1 $0\sdram_time1[3:0] + update \socbushandler_counter $0\socbushandler_counter[0:0] + update \socbushandler_dat_r $0\socbushandler_dat_r[63:0] + update \converter_counter $0\converter_counter[0:0] + update \converter_dat_r $0\converter_dat_r[31:0] + update \cmd_consumed $0\cmd_consumed[0:0] + update \wdata_consumed $0\wdata_consumed[0:0] + update \uart_phy_storage $0\uart_phy_storage[31:0] + update \uart_phy_re $0\uart_phy_re[0:0] + update \uart_phy_sink_ready $0\uart_phy_sink_ready[0:0] + update \uart_phy_uart_clk_txen $0\uart_phy_uart_clk_txen[0:0] + update \uart_phy_phase_accumulator_tx $0\uart_phy_phase_accumulator_tx[31:0] + update \uart_phy_tx_reg $0\uart_phy_tx_reg[7:0] + update \uart_phy_tx_bitcount $0\uart_phy_tx_bitcount[3:0] + update \uart_phy_tx_busy $0\uart_phy_tx_busy[0:0] + update \uart_phy_source_valid $0\uart_phy_source_valid[0:0] + update \uart_phy_source_payload_data $0\uart_phy_source_payload_data[7:0] + update \uart_phy_uart_clk_rxen $0\uart_phy_uart_clk_rxen[0:0] + update \uart_phy_phase_accumulator_rx $0\uart_phy_phase_accumulator_rx[31:0] + update \uart_phy_rx_r $0\uart_phy_rx_r[0:0] + update \uart_phy_rx_reg $0\uart_phy_rx_reg[7:0] + update \uart_phy_rx_bitcount $0\uart_phy_rx_bitcount[3:0] + update \uart_phy_rx_busy $0\uart_phy_rx_busy[0:0] + update \tx_pending $0\tx_pending[0:0] + update \tx_old_trigger $0\tx_old_trigger[0:0] + update \rx_pending $0\rx_pending[0:0] + update \rx_old_trigger $0\rx_old_trigger[0:0] + update \eventmanager_storage $0\eventmanager_storage[1:0] + update \eventmanager_re $0\eventmanager_re[0:0] + update \tx_fifo_readable $0\tx_fifo_readable[0:0] + update \tx_fifo_level0 $0\tx_fifo_level0[4:0] + update \tx_fifo_produce $0\tx_fifo_produce[3:0] + update \tx_fifo_consume $0\tx_fifo_consume[3:0] + update \rx_fifo_readable $0\rx_fifo_readable[0:0] + update \rx_fifo_level0 $0\rx_fifo_level0[4:0] + update \rx_fifo_produce $0\rx_fifo_produce[3:0] + update \rx_fifo_consume $0\rx_fifo_consume[3:0] + update \gpio0_oe_storage $0\gpio0_oe_storage[7:0] + update \gpio0_oe_re $0\gpio0_oe_re[0:0] + update \gpio0_out_storage $0\gpio0_out_storage[7:0] + update \gpio0_out_re $0\gpio0_out_re[0:0] + update \gpio1_oe_storage $0\gpio1_oe_storage[7:0] + update \gpio1_oe_re $0\gpio1_oe_re[0:0] + update \gpio1_out_storage $0\gpio1_out_storage[7:0] + update \gpio1_out_re $0\gpio1_out_re[0:0] + update \dummy $0\dummy[29:0] + update \i2c_storage $0\i2c_storage[2:0] + update \i2c_re $0\i2c_re[0:0] + update \subfragments_converter0_state $0\subfragments_converter0_state[0:0] + update \subfragments_converter1_state $0\subfragments_converter1_state[0:0] + update \subfragments_converter2_state $0\subfragments_converter2_state[0:0] + update \subfragments_refresher_state $0\subfragments_refresher_state[1:0] + update \subfragments_bankmachine0_state $0\subfragments_bankmachine0_state[2:0] + update \subfragments_bankmachine1_state $0\subfragments_bankmachine1_state[2:0] + update \subfragments_bankmachine2_state $0\subfragments_bankmachine2_state[2:0] + update \subfragments_bankmachine3_state $0\subfragments_bankmachine3_state[2:0] + update \subfragments_multiplexer_state $0\subfragments_multiplexer_state[2:0] + update \subfragments_new_master_wdata_ready $0\subfragments_new_master_wdata_ready[0:0] + update \subfragments_new_master_rdata_valid0 $0\subfragments_new_master_rdata_valid0[0:0] + update \subfragments_new_master_rdata_valid1 $0\subfragments_new_master_rdata_valid1[0:0] + update \subfragments_new_master_rdata_valid2 $0\subfragments_new_master_rdata_valid2[0:0] + update \subfragments_new_master_rdata_valid3 $0\subfragments_new_master_rdata_valid3[0:0] + update \subfragments_state $0\subfragments_state[0:0] + update \libresocsim_libresocsim_adr $0\libresocsim_libresocsim_adr[13:0] + update \libresocsim_libresocsim_we $0\libresocsim_libresocsim_we[0:0] + update \libresocsim_libresocsim_dat_w $0\libresocsim_libresocsim_dat_w[7:0] + update \libresocsim_grant $0\libresocsim_grant[1:0] + update \libresocsim_slave_sel_r $0\libresocsim_slave_sel_r[5:0] + update \libresocsim_count $0\libresocsim_count[19:0] + update \libresocsim_interface0_bank_bus_dat_r $0\libresocsim_interface0_bank_bus_dat_r[7:0] + update \libresocsim_interface1_bank_bus_dat_r $0\libresocsim_interface1_bank_bus_dat_r[7:0] + update \libresocsim_interface2_bank_bus_dat_r $0\libresocsim_interface2_bank_bus_dat_r[7:0] + update \libresocsim_interface3_bank_bus_dat_r $0\libresocsim_interface3_bank_bus_dat_r[7:0] + update \libresocsim_interface4_bank_bus_dat_r $0\libresocsim_interface4_bank_bus_dat_r[7:0] + update \libresocsim_interface5_bank_bus_dat_r $0\libresocsim_interface5_bank_bus_dat_r[7:0] + update \libresocsim_interface6_bank_bus_dat_r $0\libresocsim_interface6_bank_bus_dat_r[7:0] + update \libresocsim_interface7_bank_bus_dat_r $0\libresocsim_interface7_bank_bus_dat_r[7:0] + update \libresocsim_state $0\libresocsim_state[1:0] + update \regs0 $0\regs0[0:0] + update \regs1 $0\regs1[0:0] + end + attribute \src "ls180.v:429.11-429.65" + process $proc$ls180.v:429$1777 + assign { } { } + assign $1\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \sdram_bankmachine0_cmd_buffer_lookahead_produce $1\sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:43.5-43.37" + process $proc$ls180.v:43$1620 + assign { } { } + assign $1\libresocsim_reset_storage[0:0] 1'0 + sync always + sync init + update \libresocsim_reset_storage $1\libresocsim_reset_storage[0:0] + end + attribute \src "ls180.v:430.11-430.65" + process $proc$ls180.v:430$1778 + assign { } { } + assign $1\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \sdram_bankmachine0_cmd_buffer_lookahead_consume $1\sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:431.11-431.68" + process $proc$ls180.v:431$1779 + assign { } { } + assign $1\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $1\sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:44.5-44.32" + process $proc$ls180.v:44$1621 + assign { } { } + assign $1\libresocsim_reset_re[0:0] 1'0 + sync always + sync init + update \libresocsim_reset_re $1\libresocsim_reset_re[0:0] + end + attribute \src "ls180.v:45.12-45.55" + process $proc$ls180.v:45$1622 + assign { } { } + assign $1\libresocsim_scratch_storage[31:0] 305419896 + sync always + sync init + update \libresocsim_scratch_storage $1\libresocsim_scratch_storage[31:0] + end + attribute \src "ls180.v:452.5-452.54" + process $proc$ls180.v:452$1780 + assign { } { } + assign $1\sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine0_cmd_buffer_source_valid $1\sdram_bankmachine0_cmd_buffer_source_valid[0:0] + end + attribute \src "ls180.v:454.5-454.54" + process $proc$ls180.v:454$1781 + assign { } { } + assign $1\sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine0_cmd_buffer_source_first $1\sdram_bankmachine0_cmd_buffer_source_first[0:0] + end + attribute \src "ls180.v:455.5-455.53" + process $proc$ls180.v:455$1782 + assign { } { } + assign $1\sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine0_cmd_buffer_source_last $1\sdram_bankmachine0_cmd_buffer_source_last[0:0] + end + attribute \src "ls180.v:456.5-456.59" + process $proc$ls180.v:456$1783 + assign { } { } + assign $1\sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine0_cmd_buffer_source_payload_we $1\sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + end + attribute \src "ls180.v:457.12-457.69" + process $proc$ls180.v:457$1784 + assign { } { } + assign $1\sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \sdram_bankmachine0_cmd_buffer_source_payload_addr $1\sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "ls180.v:458.12-458.42" + process $proc$ls180.v:458$1785 + assign { } { } + assign $1\sdram_bankmachine0_row[12:0] 13'0000000000000 + sync always + sync init + update \sdram_bankmachine0_row $1\sdram_bankmachine0_row[12:0] + end + attribute \src "ls180.v:459.5-459.41" + process $proc$ls180.v:459$1786 + assign { } { } + assign $1\sdram_bankmachine0_row_opened[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine0_row_opened $1\sdram_bankmachine0_row_opened[0:0] + end + attribute \src "ls180.v:46.5-46.34" + process $proc$ls180.v:46$1623 + assign { } { } + assign $1\libresocsim_scratch_re[0:0] 1'0 + sync always + sync init + update \libresocsim_scratch_re $1\libresocsim_scratch_re[0:0] + end + attribute \src "ls180.v:461.5-461.39" + process $proc$ls180.v:461$1787 + assign { } { } + assign $1\sdram_bankmachine0_row_open[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine0_row_open $1\sdram_bankmachine0_row_open[0:0] + end + attribute \src "ls180.v:462.5-462.40" + process $proc$ls180.v:462$1788 + assign { } { } + assign $1\sdram_bankmachine0_row_close[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine0_row_close $1\sdram_bankmachine0_row_close[0:0] + end + attribute \src "ls180.v:463.5-463.49" + process $proc$ls180.v:463$1789 + assign { } { } + assign $1\sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine0_row_col_n_addr_sel $1\sdram_bankmachine0_row_col_n_addr_sel[0:0] + end + attribute \src "ls180.v:465.32-465.71" + process $proc$ls180.v:465$1790 + assign { } { } + assign $1\sdram_bankmachine0_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine0_twtpcon_ready $1\sdram_bankmachine0_twtpcon_ready[0:0] + end + attribute \src "ls180.v:466.11-466.50" + process $proc$ls180.v:466$1791 + assign { } { } + assign $1\sdram_bankmachine0_twtpcon_count[2:0] 3'000 + sync always + sync init + update \sdram_bankmachine0_twtpcon_count $1\sdram_bankmachine0_twtpcon_count[2:0] + end + attribute \src "ls180.v:468.32-468.70" + process $proc$ls180.v:468$1792 + assign { } { } + assign $0\sdram_bankmachine0_trccon_ready[0:0] 1'1 + sync always + update \sdram_bankmachine0_trccon_ready $0\sdram_bankmachine0_trccon_ready[0:0] + sync init + end + attribute \src "ls180.v:470.32-470.71" + process $proc$ls180.v:470$1793 + assign { } { } + assign $0\sdram_bankmachine0_trascon_ready[0:0] 1'1 + sync always + update \sdram_bankmachine0_trascon_ready $0\sdram_bankmachine0_trascon_ready[0:0] + sync init + end + attribute \src "ls180.v:476.5-476.46" + process $proc$ls180.v:476$1794 + assign { } { } + assign $1\sdram_bankmachine1_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine1_req_wdata_ready $1\sdram_bankmachine1_req_wdata_ready[0:0] + end + attribute \src "ls180.v:477.5-477.46" + process $proc$ls180.v:477$1795 + assign { } { } + assign $1\sdram_bankmachine1_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine1_req_rdata_valid $1\sdram_bankmachine1_req_rdata_valid[0:0] + end + attribute \src "ls180.v:479.5-479.42" + process $proc$ls180.v:479$1796 + assign { } { } + assign $1\sdram_bankmachine1_refresh_gnt[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine1_refresh_gnt $1\sdram_bankmachine1_refresh_gnt[0:0] + end + attribute \src "ls180.v:480.5-480.40" + process $proc$ls180.v:480$1797 + assign { } { } + assign $1\sdram_bankmachine1_cmd_valid[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine1_cmd_valid $1\sdram_bankmachine1_cmd_valid[0:0] + end + attribute \src "ls180.v:481.5-481.40" + process $proc$ls180.v:481$1798 + assign { } { } + assign $1\sdram_bankmachine1_cmd_ready[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine1_cmd_ready $1\sdram_bankmachine1_cmd_ready[0:0] + end + attribute \src "ls180.v:482.12-482.52" + process $proc$ls180.v:482$1799 + assign { } { } + assign $1\sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \sdram_bankmachine1_cmd_payload_a $1\sdram_bankmachine1_cmd_payload_a[12:0] + end + attribute \src "ls180.v:484.5-484.46" + process $proc$ls180.v:484$1800 + assign { } { } + assign $1\sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine1_cmd_payload_cas $1\sdram_bankmachine1_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:485.5-485.46" + process $proc$ls180.v:485$1801 + assign { } { } + assign $1\sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine1_cmd_payload_ras $1\sdram_bankmachine1_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:486.5-486.45" + process $proc$ls180.v:486$1802 + assign { } { } + assign $1\sdram_bankmachine1_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine1_cmd_payload_we $1\sdram_bankmachine1_cmd_payload_we[0:0] + end + attribute \src "ls180.v:487.5-487.49" + process $proc$ls180.v:487$1803 + assign { } { } + assign $1\sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine1_cmd_payload_is_cmd $1\sdram_bankmachine1_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:488.5-488.50" + process $proc$ls180.v:488$1804 + assign { } { } + assign $1\sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine1_cmd_payload_is_read $1\sdram_bankmachine1_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:489.5-489.51" + process $proc$ls180.v:489$1805 + assign { } { } + assign $1\sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine1_cmd_payload_is_write $1\sdram_bankmachine1_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:490.5-490.45" + process $proc$ls180.v:490$1806 + assign { } { } + assign $1\sdram_bankmachine1_auto_precharge[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine1_auto_precharge $1\sdram_bankmachine1_auto_precharge[0:0] + end + attribute \src "ls180.v:493.5-493.62" + process $proc$ls180.v:493$1807 + assign { } { } + assign $0\sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \sdram_bankmachine1_cmd_buffer_lookahead_sink_first $0\sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:494.5-494.61" + process $proc$ls180.v:494$1808 + assign { } { } + assign $0\sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \sdram_bankmachine1_cmd_buffer_lookahead_sink_last $0\sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:509.11-509.63" + process $proc$ls180.v:509$1809 + assign { } { } + assign $1\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \sdram_bankmachine1_cmd_buffer_lookahead_level $1\sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + end + attribute \src "ls180.v:51.12-51.42" + process $proc$ls180.v:51$1624 + assign { } { } + assign $1\libresocsim_bus_errors[31:0] 0 + sync always + sync init + update \libresocsim_bus_errors $1\libresocsim_bus_errors[31:0] + end + attribute \src "ls180.v:510.5-510.59" + process $proc$ls180.v:510$1810 + assign { } { } + assign $0\sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \sdram_bankmachine1_cmd_buffer_lookahead_replace $0\sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:511.11-511.65" + process $proc$ls180.v:511$1811 + assign { } { } + assign $1\sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \sdram_bankmachine1_cmd_buffer_lookahead_produce $1\sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:512.11-512.65" + process $proc$ls180.v:512$1812 + assign { } { } + assign $1\sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \sdram_bankmachine1_cmd_buffer_lookahead_consume $1\sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:513.11-513.68" + process $proc$ls180.v:513$1813 + assign { } { } + assign $1\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:53.12-53.50" + process $proc$ls180.v:53$1625 + assign { } { } + assign $1\libresocsim_libresoc_interrupt[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_libresoc_interrupt $1\libresocsim_libresoc_interrupt[15:0] + end + attribute \src "ls180.v:534.5-534.54" + process $proc$ls180.v:534$1814 + assign { } { } + assign $1\sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine1_cmd_buffer_source_valid $1\sdram_bankmachine1_cmd_buffer_source_valid[0:0] + end + attribute \src "ls180.v:536.5-536.54" + process $proc$ls180.v:536$1815 + assign { } { } + assign $1\sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine1_cmd_buffer_source_first $1\sdram_bankmachine1_cmd_buffer_source_first[0:0] + end + attribute \src "ls180.v:537.5-537.53" + process $proc$ls180.v:537$1816 + assign { } { } + assign $1\sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine1_cmd_buffer_source_last $1\sdram_bankmachine1_cmd_buffer_source_last[0:0] + end + attribute \src "ls180.v:538.5-538.59" + process $proc$ls180.v:538$1817 + assign { } { } + assign $1\sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine1_cmd_buffer_source_payload_we $1\sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + end + attribute \src "ls180.v:539.12-539.69" + process $proc$ls180.v:539$1818 + assign { } { } + assign $1\sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \sdram_bankmachine1_cmd_buffer_source_payload_addr $1\sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "ls180.v:540.12-540.42" + process $proc$ls180.v:540$1819 + assign { } { } + assign $1\sdram_bankmachine1_row[12:0] 13'0000000000000 + sync always + sync init + update \sdram_bankmachine1_row $1\sdram_bankmachine1_row[12:0] + end + attribute \src "ls180.v:541.5-541.41" + process $proc$ls180.v:541$1820 + assign { } { } + assign $1\sdram_bankmachine1_row_opened[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine1_row_opened $1\sdram_bankmachine1_row_opened[0:0] + end + attribute \src "ls180.v:543.5-543.39" + process $proc$ls180.v:543$1821 + assign { } { } + assign $1\sdram_bankmachine1_row_open[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine1_row_open $1\sdram_bankmachine1_row_open[0:0] + end + attribute \src "ls180.v:544.5-544.40" + process $proc$ls180.v:544$1822 + assign { } { } + assign $1\sdram_bankmachine1_row_close[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine1_row_close $1\sdram_bankmachine1_row_close[0:0] + end + attribute \src "ls180.v:545.5-545.49" + process $proc$ls180.v:545$1823 + assign { } { } + assign $1\sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine1_row_col_n_addr_sel $1\sdram_bankmachine1_row_col_n_addr_sel[0:0] + end + attribute \src "ls180.v:547.32-547.71" + process $proc$ls180.v:547$1824 + assign { } { } + assign $1\sdram_bankmachine1_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine1_twtpcon_ready $1\sdram_bankmachine1_twtpcon_ready[0:0] + end + attribute \src "ls180.v:548.11-548.50" + process $proc$ls180.v:548$1825 + assign { } { } + assign $1\sdram_bankmachine1_twtpcon_count[2:0] 3'000 + sync always + sync init + update \sdram_bankmachine1_twtpcon_count $1\sdram_bankmachine1_twtpcon_count[2:0] + end + attribute \src "ls180.v:5491.1-5509.4" + process $proc$ls180.v:5491$1459 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\mem$ls180.v:5493$1_ADDR[5:0]$1460 $1$memwr$\mem$ls180.v:5493$1_ADDR[5:0]$1484 + assign $0$memwr$\mem$ls180.v:5493$1_DATA[63:0]$1461 $1$memwr$\mem$ls180.v:5493$1_DATA[63:0]$1485 + assign $0$memwr$\mem$ls180.v:5493$1_EN[63:0]$1462 $1$memwr$\mem$ls180.v:5493$1_EN[63:0]$1486 + assign $0$memwr$\mem$ls180.v:5495$2_ADDR[5:0]$1463 $1$memwr$\mem$ls180.v:5495$2_ADDR[5:0]$1487 + assign $0$memwr$\mem$ls180.v:5495$2_DATA[63:0]$1464 $1$memwr$\mem$ls180.v:5495$2_DATA[63:0]$1488 + assign $0$memwr$\mem$ls180.v:5495$2_EN[63:0]$1465 $1$memwr$\mem$ls180.v:5495$2_EN[63:0]$1489 + assign $0$memwr$\mem$ls180.v:5497$3_ADDR[5:0]$1466 $1$memwr$\mem$ls180.v:5497$3_ADDR[5:0]$1490 + assign $0$memwr$\mem$ls180.v:5497$3_DATA[63:0]$1467 $1$memwr$\mem$ls180.v:5497$3_DATA[63:0]$1491 + assign $0$memwr$\mem$ls180.v:5497$3_EN[63:0]$1468 $1$memwr$\mem$ls180.v:5497$3_EN[63:0]$1492 + assign $0$memwr$\mem$ls180.v:5499$4_ADDR[5:0]$1469 $1$memwr$\mem$ls180.v:5499$4_ADDR[5:0]$1493 + assign $0$memwr$\mem$ls180.v:5499$4_DATA[63:0]$1470 $1$memwr$\mem$ls180.v:5499$4_DATA[63:0]$1494 + assign $0$memwr$\mem$ls180.v:5499$4_EN[63:0]$1471 $1$memwr$\mem$ls180.v:5499$4_EN[63:0]$1495 + assign $0$memwr$\mem$ls180.v:5501$5_ADDR[5:0]$1472 $1$memwr$\mem$ls180.v:5501$5_ADDR[5:0]$1496 + assign $0$memwr$\mem$ls180.v:5501$5_DATA[63:0]$1473 $1$memwr$\mem$ls180.v:5501$5_DATA[63:0]$1497 + assign $0$memwr$\mem$ls180.v:5501$5_EN[63:0]$1474 $1$memwr$\mem$ls180.v:5501$5_EN[63:0]$1498 + assign $0$memwr$\mem$ls180.v:5503$6_ADDR[5:0]$1475 $1$memwr$\mem$ls180.v:5503$6_ADDR[5:0]$1499 + assign $0$memwr$\mem$ls180.v:5503$6_DATA[63:0]$1476 $1$memwr$\mem$ls180.v:5503$6_DATA[63:0]$1500 + assign $0$memwr$\mem$ls180.v:5503$6_EN[63:0]$1477 $1$memwr$\mem$ls180.v:5503$6_EN[63:0]$1501 + assign $0$memwr$\mem$ls180.v:5505$7_ADDR[5:0]$1478 $1$memwr$\mem$ls180.v:5505$7_ADDR[5:0]$1502 + assign $0$memwr$\mem$ls180.v:5505$7_DATA[63:0]$1479 $1$memwr$\mem$ls180.v:5505$7_DATA[63:0]$1503 + assign $0$memwr$\mem$ls180.v:5505$7_EN[63:0]$1480 $1$memwr$\mem$ls180.v:5505$7_EN[63:0]$1504 + assign $0$memwr$\mem$ls180.v:5507$8_ADDR[5:0]$1481 $1$memwr$\mem$ls180.v:5507$8_ADDR[5:0]$1505 + assign $0$memwr$\mem$ls180.v:5507$8_DATA[63:0]$1482 $1$memwr$\mem$ls180.v:5507$8_DATA[63:0]$1506 + assign $0$memwr$\mem$ls180.v:5507$8_EN[63:0]$1483 $1$memwr$\mem$ls180.v:5507$8_EN[63:0]$1507 + assign $0\memadr[5:0] \libresocsim_adr + attribute \src "ls180.v:5492.2-5493.55" + switch \libresocsim_we [0] + attribute \src "ls180.v:5492.6-5492.23" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\mem$ls180.v:5493$1_ADDR[5:0]$1484 \libresocsim_adr + assign $1$memwr$\mem$ls180.v:5493$1_DATA[63:0]$1485 { 56'00000000000000000000000000000000000000000000000000000000 \libresocsim_dat_w [7:0] } + assign $1$memwr$\mem$ls180.v:5493$1_EN[63:0]$1486 64'0000000000000000000000000000000000000000000000000000000011111111 + case + assign $1$memwr$\mem$ls180.v:5493$1_ADDR[5:0]$1484 6'xxxxxx + assign $1$memwr$\mem$ls180.v:5493$1_DATA[63:0]$1485 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\mem$ls180.v:5493$1_EN[63:0]$1486 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "ls180.v:5494.2-5495.57" + switch \libresocsim_we [1] + attribute \src "ls180.v:5494.6-5494.23" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\mem$ls180.v:5495$2_ADDR[5:0]$1487 \libresocsim_adr + assign $1$memwr$\mem$ls180.v:5495$2_DATA[63:0]$1488 { 48'000000000000000000000000000000000000000000000000 \libresocsim_dat_w [15:8] 8'xxxxxxxx } + assign $1$memwr$\mem$ls180.v:5495$2_EN[63:0]$1489 64'0000000000000000000000000000000000000000000000001111111100000000 + case + assign $1$memwr$\mem$ls180.v:5495$2_ADDR[5:0]$1487 6'xxxxxx + assign $1$memwr$\mem$ls180.v:5495$2_DATA[63:0]$1488 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\mem$ls180.v:5495$2_EN[63:0]$1489 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "ls180.v:5496.2-5497.59" + switch \libresocsim_we [2] + attribute \src "ls180.v:5496.6-5496.23" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\mem$ls180.v:5497$3_ADDR[5:0]$1490 \libresocsim_adr + assign $1$memwr$\mem$ls180.v:5497$3_DATA[63:0]$1491 { 40'0000000000000000000000000000000000000000 \libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $1$memwr$\mem$ls180.v:5497$3_EN[63:0]$1492 64'0000000000000000000000000000000000000000111111110000000000000000 + case + assign $1$memwr$\mem$ls180.v:5497$3_ADDR[5:0]$1490 6'xxxxxx + assign $1$memwr$\mem$ls180.v:5497$3_DATA[63:0]$1491 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\mem$ls180.v:5497$3_EN[63:0]$1492 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "ls180.v:5498.2-5499.59" + switch \libresocsim_we [3] + attribute \src "ls180.v:5498.6-5498.23" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\mem$ls180.v:5499$4_ADDR[5:0]$1493 \libresocsim_adr + assign $1$memwr$\mem$ls180.v:5499$4_DATA[63:0]$1494 { 32'00000000000000000000000000000000 \libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $1$memwr$\mem$ls180.v:5499$4_EN[63:0]$1495 64'0000000000000000000000000000000011111111000000000000000000000000 + case + assign $1$memwr$\mem$ls180.v:5499$4_ADDR[5:0]$1493 6'xxxxxx + assign $1$memwr$\mem$ls180.v:5499$4_DATA[63:0]$1494 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\mem$ls180.v:5499$4_EN[63:0]$1495 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "ls180.v:5500.2-5501.59" + switch \libresocsim_we [4] + attribute \src "ls180.v:5500.6-5500.23" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\mem$ls180.v:5501$5_ADDR[5:0]$1496 \libresocsim_adr + assign $1$memwr$\mem$ls180.v:5501$5_DATA[63:0]$1497 { 24'000000000000000000000000 \libresocsim_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $1$memwr$\mem$ls180.v:5501$5_EN[63:0]$1498 64'0000000000000000000000001111111100000000000000000000000000000000 + case + assign $1$memwr$\mem$ls180.v:5501$5_ADDR[5:0]$1496 6'xxxxxx + assign $1$memwr$\mem$ls180.v:5501$5_DATA[63:0]$1497 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\mem$ls180.v:5501$5_EN[63:0]$1498 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "ls180.v:5502.2-5503.59" + switch \libresocsim_we [5] + attribute \src "ls180.v:5502.6-5502.23" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\mem$ls180.v:5503$6_ADDR[5:0]$1499 \libresocsim_adr + assign $1$memwr$\mem$ls180.v:5503$6_DATA[63:0]$1500 { 16'0000000000000000 \libresocsim_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $1$memwr$\mem$ls180.v:5503$6_EN[63:0]$1501 64'0000000000000000111111110000000000000000000000000000000000000000 + case + assign $1$memwr$\mem$ls180.v:5503$6_ADDR[5:0]$1499 6'xxxxxx + assign $1$memwr$\mem$ls180.v:5503$6_DATA[63:0]$1500 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\mem$ls180.v:5503$6_EN[63:0]$1501 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "ls180.v:5504.2-5505.59" + switch \libresocsim_we [6] + attribute \src "ls180.v:5504.6-5504.23" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\mem$ls180.v:5505$7_ADDR[5:0]$1502 \libresocsim_adr + assign $1$memwr$\mem$ls180.v:5505$7_DATA[63:0]$1503 { 8'00000000 \libresocsim_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $1$memwr$\mem$ls180.v:5505$7_EN[63:0]$1504 64'0000000011111111000000000000000000000000000000000000000000000000 + case + assign $1$memwr$\mem$ls180.v:5505$7_ADDR[5:0]$1502 6'xxxxxx + assign $1$memwr$\mem$ls180.v:5505$7_DATA[63:0]$1503 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\mem$ls180.v:5505$7_EN[63:0]$1504 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "ls180.v:5506.2-5507.59" + switch \libresocsim_we [7] + attribute \src "ls180.v:5506.6-5506.23" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\mem$ls180.v:5507$8_ADDR[5:0]$1505 \libresocsim_adr + assign $1$memwr$\mem$ls180.v:5507$8_DATA[63:0]$1506 { \libresocsim_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $1$memwr$\mem$ls180.v:5507$8_EN[63:0]$1507 64'1111111100000000000000000000000000000000000000000000000000000000 + case + assign $1$memwr$\mem$ls180.v:5507$8_ADDR[5:0]$1505 6'xxxxxx + assign $1$memwr$\mem$ls180.v:5507$8_DATA[63:0]$1506 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\mem$ls180.v:5507$8_EN[63:0]$1507 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync posedge \sys_clk_1 + update \memadr $0\memadr[5:0] + update $memwr$\mem$ls180.v:5493$1_ADDR $0$memwr$\mem$ls180.v:5493$1_ADDR[5:0]$1460 + update $memwr$\mem$ls180.v:5493$1_DATA $0$memwr$\mem$ls180.v:5493$1_DATA[63:0]$1461 + update $memwr$\mem$ls180.v:5493$1_EN $0$memwr$\mem$ls180.v:5493$1_EN[63:0]$1462 + update $memwr$\mem$ls180.v:5495$2_ADDR $0$memwr$\mem$ls180.v:5495$2_ADDR[5:0]$1463 + update $memwr$\mem$ls180.v:5495$2_DATA $0$memwr$\mem$ls180.v:5495$2_DATA[63:0]$1464 + update $memwr$\mem$ls180.v:5495$2_EN $0$memwr$\mem$ls180.v:5495$2_EN[63:0]$1465 + update $memwr$\mem$ls180.v:5497$3_ADDR $0$memwr$\mem$ls180.v:5497$3_ADDR[5:0]$1466 + update $memwr$\mem$ls180.v:5497$3_DATA $0$memwr$\mem$ls180.v:5497$3_DATA[63:0]$1467 + update $memwr$\mem$ls180.v:5497$3_EN $0$memwr$\mem$ls180.v:5497$3_EN[63:0]$1468 + update $memwr$\mem$ls180.v:5499$4_ADDR $0$memwr$\mem$ls180.v:5499$4_ADDR[5:0]$1469 + update $memwr$\mem$ls180.v:5499$4_DATA $0$memwr$\mem$ls180.v:5499$4_DATA[63:0]$1470 + update $memwr$\mem$ls180.v:5499$4_EN $0$memwr$\mem$ls180.v:5499$4_EN[63:0]$1471 + update $memwr$\mem$ls180.v:5501$5_ADDR $0$memwr$\mem$ls180.v:5501$5_ADDR[5:0]$1472 + update $memwr$\mem$ls180.v:5501$5_DATA $0$memwr$\mem$ls180.v:5501$5_DATA[63:0]$1473 + update $memwr$\mem$ls180.v:5501$5_EN $0$memwr$\mem$ls180.v:5501$5_EN[63:0]$1474 + update $memwr$\mem$ls180.v:5503$6_ADDR $0$memwr$\mem$ls180.v:5503$6_ADDR[5:0]$1475 + update $memwr$\mem$ls180.v:5503$6_DATA $0$memwr$\mem$ls180.v:5503$6_DATA[63:0]$1476 + update $memwr$\mem$ls180.v:5503$6_EN $0$memwr$\mem$ls180.v:5503$6_EN[63:0]$1477 + update $memwr$\mem$ls180.v:5505$7_ADDR $0$memwr$\mem$ls180.v:5505$7_ADDR[5:0]$1478 + update $memwr$\mem$ls180.v:5505$7_DATA $0$memwr$\mem$ls180.v:5505$7_DATA[63:0]$1479 + update $memwr$\mem$ls180.v:5505$7_EN $0$memwr$\mem$ls180.v:5505$7_EN[63:0]$1480 + update $memwr$\mem$ls180.v:5507$8_ADDR $0$memwr$\mem$ls180.v:5507$8_ADDR[5:0]$1481 + update $memwr$\mem$ls180.v:5507$8_DATA $0$memwr$\mem$ls180.v:5507$8_DATA[63:0]$1482 + update $memwr$\mem$ls180.v:5507$8_EN $0$memwr$\mem$ls180.v:5507$8_EN[63:0]$1483 + attribute \src "ls180.v:5493.3-5493.54" + memwr \mem $1$memwr$\mem$ls180.v:5493$1_ADDR[5:0]$1484 $1$memwr$\mem$ls180.v:5493$1_DATA[63:0]$1485 $1$memwr$\mem$ls180.v:5493$1_EN[63:0]$1486 0' + attribute \src "ls180.v:5495.3-5495.56" + memwr \mem $1$memwr$\mem$ls180.v:5495$2_ADDR[5:0]$1487 $1$memwr$\mem$ls180.v:5495$2_DATA[63:0]$1488 $1$memwr$\mem$ls180.v:5495$2_EN[63:0]$1489 1'1 + attribute \src "ls180.v:5497.3-5497.58" + memwr \mem $1$memwr$\mem$ls180.v:5497$3_ADDR[5:0]$1490 $1$memwr$\mem$ls180.v:5497$3_DATA[63:0]$1491 $1$memwr$\mem$ls180.v:5497$3_EN[63:0]$1492 2'11 + attribute \src "ls180.v:5499.3-5499.58" + memwr \mem $1$memwr$\mem$ls180.v:5499$4_ADDR[5:0]$1493 $1$memwr$\mem$ls180.v:5499$4_DATA[63:0]$1494 $1$memwr$\mem$ls180.v:5499$4_EN[63:0]$1495 3'111 + attribute \src "ls180.v:5501.3-5501.58" + memwr \mem $1$memwr$\mem$ls180.v:5501$5_ADDR[5:0]$1496 $1$memwr$\mem$ls180.v:5501$5_DATA[63:0]$1497 $1$memwr$\mem$ls180.v:5501$5_EN[63:0]$1498 4'1111 + attribute \src "ls180.v:5503.3-5503.58" + memwr \mem $1$memwr$\mem$ls180.v:5503$6_ADDR[5:0]$1499 $1$memwr$\mem$ls180.v:5503$6_DATA[63:0]$1500 $1$memwr$\mem$ls180.v:5503$6_EN[63:0]$1501 5'11111 + attribute \src "ls180.v:5505.3-5505.58" + memwr \mem $1$memwr$\mem$ls180.v:5505$7_ADDR[5:0]$1502 $1$memwr$\mem$ls180.v:5505$7_DATA[63:0]$1503 $1$memwr$\mem$ls180.v:5505$7_EN[63:0]$1504 6'111111 + attribute \src "ls180.v:5507.3-5507.58" + memwr \mem $1$memwr$\mem$ls180.v:5507$8_ADDR[5:0]$1505 $1$memwr$\mem$ls180.v:5507$8_DATA[63:0]$1506 $1$memwr$\mem$ls180.v:5507$8_EN[63:0]$1507 7'1111111 + end + attribute \src "ls180.v:550.32-550.70" + process $proc$ls180.v:550$1826 + assign { } { } + assign $0\sdram_bankmachine1_trccon_ready[0:0] 1'1 + sync always + update \sdram_bankmachine1_trccon_ready $0\sdram_bankmachine1_trccon_ready[0:0] + sync init + end + attribute \src "ls180.v:5519.1-5537.4" + process $proc$ls180.v:5519$1509 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\mem_1$ls180.v:5521$9_ADDR[3:0]$1510 $1$memwr$\mem_1$ls180.v:5521$9_ADDR[3:0]$1534 + assign $0$memwr$\mem_1$ls180.v:5521$9_DATA[63:0]$1511 $1$memwr$\mem_1$ls180.v:5521$9_DATA[63:0]$1535 + assign $0$memwr$\mem_1$ls180.v:5521$9_EN[63:0]$1512 $1$memwr$\mem_1$ls180.v:5521$9_EN[63:0]$1536 + assign $0$memwr$\mem_1$ls180.v:5523$10_ADDR[3:0]$1513 $1$memwr$\mem_1$ls180.v:5523$10_ADDR[3:0]$1537 + assign $0$memwr$\mem_1$ls180.v:5523$10_DATA[63:0]$1514 $1$memwr$\mem_1$ls180.v:5523$10_DATA[63:0]$1538 + assign $0$memwr$\mem_1$ls180.v:5523$10_EN[63:0]$1515 $1$memwr$\mem_1$ls180.v:5523$10_EN[63:0]$1539 + assign $0$memwr$\mem_1$ls180.v:5525$11_ADDR[3:0]$1516 $1$memwr$\mem_1$ls180.v:5525$11_ADDR[3:0]$1540 + assign $0$memwr$\mem_1$ls180.v:5525$11_DATA[63:0]$1517 $1$memwr$\mem_1$ls180.v:5525$11_DATA[63:0]$1541 + assign $0$memwr$\mem_1$ls180.v:5525$11_EN[63:0]$1518 $1$memwr$\mem_1$ls180.v:5525$11_EN[63:0]$1542 + assign $0$memwr$\mem_1$ls180.v:5527$12_ADDR[3:0]$1519 $1$memwr$\mem_1$ls180.v:5527$12_ADDR[3:0]$1543 + assign $0$memwr$\mem_1$ls180.v:5527$12_DATA[63:0]$1520 $1$memwr$\mem_1$ls180.v:5527$12_DATA[63:0]$1544 + assign $0$memwr$\mem_1$ls180.v:5527$12_EN[63:0]$1521 $1$memwr$\mem_1$ls180.v:5527$12_EN[63:0]$1545 + assign $0$memwr$\mem_1$ls180.v:5529$13_ADDR[3:0]$1522 $1$memwr$\mem_1$ls180.v:5529$13_ADDR[3:0]$1546 + assign $0$memwr$\mem_1$ls180.v:5529$13_DATA[63:0]$1523 $1$memwr$\mem_1$ls180.v:5529$13_DATA[63:0]$1547 + assign $0$memwr$\mem_1$ls180.v:5529$13_EN[63:0]$1524 $1$memwr$\mem_1$ls180.v:5529$13_EN[63:0]$1548 + assign $0$memwr$\mem_1$ls180.v:5531$14_ADDR[3:0]$1525 $1$memwr$\mem_1$ls180.v:5531$14_ADDR[3:0]$1549 + assign $0$memwr$\mem_1$ls180.v:5531$14_DATA[63:0]$1526 $1$memwr$\mem_1$ls180.v:5531$14_DATA[63:0]$1550 + assign $0$memwr$\mem_1$ls180.v:5531$14_EN[63:0]$1527 $1$memwr$\mem_1$ls180.v:5531$14_EN[63:0]$1551 + assign $0$memwr$\mem_1$ls180.v:5533$15_ADDR[3:0]$1528 $1$memwr$\mem_1$ls180.v:5533$15_ADDR[3:0]$1552 + assign $0$memwr$\mem_1$ls180.v:5533$15_DATA[63:0]$1529 $1$memwr$\mem_1$ls180.v:5533$15_DATA[63:0]$1553 + assign $0$memwr$\mem_1$ls180.v:5533$15_EN[63:0]$1530 $1$memwr$\mem_1$ls180.v:5533$15_EN[63:0]$1554 + assign $0$memwr$\mem_1$ls180.v:5535$16_ADDR[3:0]$1531 $1$memwr$\mem_1$ls180.v:5535$16_ADDR[3:0]$1555 + assign $0$memwr$\mem_1$ls180.v:5535$16_DATA[63:0]$1532 $1$memwr$\mem_1$ls180.v:5535$16_DATA[63:0]$1556 + assign $0$memwr$\mem_1$ls180.v:5535$16_EN[63:0]$1533 $1$memwr$\mem_1$ls180.v:5535$16_EN[63:0]$1557 + assign $0\memadr_1[3:0] \ram_adr + attribute \src "ls180.v:5520.2-5521.41" + switch \ram_we [0] + attribute \src "ls180.v:5520.6-5520.15" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\mem_1$ls180.v:5521$9_ADDR[3:0]$1534 \ram_adr + assign $1$memwr$\mem_1$ls180.v:5521$9_DATA[63:0]$1535 { 56'00000000000000000000000000000000000000000000000000000000 \ram_dat_w [7:0] } + assign $1$memwr$\mem_1$ls180.v:5521$9_EN[63:0]$1536 64'0000000000000000000000000000000000000000000000000000000011111111 + case + assign $1$memwr$\mem_1$ls180.v:5521$9_ADDR[3:0]$1534 4'xxxx + assign $1$memwr$\mem_1$ls180.v:5521$9_DATA[63:0]$1535 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\mem_1$ls180.v:5521$9_EN[63:0]$1536 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "ls180.v:5522.2-5523.43" + switch \ram_we [1] + attribute \src "ls180.v:5522.6-5522.15" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\mem_1$ls180.v:5523$10_ADDR[3:0]$1537 \ram_adr + assign $1$memwr$\mem_1$ls180.v:5523$10_DATA[63:0]$1538 { 48'000000000000000000000000000000000000000000000000 \ram_dat_w [15:8] 8'xxxxxxxx } + assign $1$memwr$\mem_1$ls180.v:5523$10_EN[63:0]$1539 64'0000000000000000000000000000000000000000000000001111111100000000 + case + assign $1$memwr$\mem_1$ls180.v:5523$10_ADDR[3:0]$1537 4'xxxx + assign $1$memwr$\mem_1$ls180.v:5523$10_DATA[63:0]$1538 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\mem_1$ls180.v:5523$10_EN[63:0]$1539 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "ls180.v:5524.2-5525.45" + switch \ram_we [2] + attribute \src "ls180.v:5524.6-5524.15" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\mem_1$ls180.v:5525$11_ADDR[3:0]$1540 \ram_adr + assign $1$memwr$\mem_1$ls180.v:5525$11_DATA[63:0]$1541 { 40'0000000000000000000000000000000000000000 \ram_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $1$memwr$\mem_1$ls180.v:5525$11_EN[63:0]$1542 64'0000000000000000000000000000000000000000111111110000000000000000 + case + assign $1$memwr$\mem_1$ls180.v:5525$11_ADDR[3:0]$1540 4'xxxx + assign $1$memwr$\mem_1$ls180.v:5525$11_DATA[63:0]$1541 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\mem_1$ls180.v:5525$11_EN[63:0]$1542 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "ls180.v:5526.2-5527.45" + switch \ram_we [3] + attribute \src "ls180.v:5526.6-5526.15" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\mem_1$ls180.v:5527$12_ADDR[3:0]$1543 \ram_adr + assign $1$memwr$\mem_1$ls180.v:5527$12_DATA[63:0]$1544 { 32'00000000000000000000000000000000 \ram_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $1$memwr$\mem_1$ls180.v:5527$12_EN[63:0]$1545 64'0000000000000000000000000000000011111111000000000000000000000000 + case + assign $1$memwr$\mem_1$ls180.v:5527$12_ADDR[3:0]$1543 4'xxxx + assign $1$memwr$\mem_1$ls180.v:5527$12_DATA[63:0]$1544 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\mem_1$ls180.v:5527$12_EN[63:0]$1545 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "ls180.v:5528.2-5529.45" + switch \ram_we [4] + attribute \src "ls180.v:5528.6-5528.15" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\mem_1$ls180.v:5529$13_ADDR[3:0]$1546 \ram_adr + assign $1$memwr$\mem_1$ls180.v:5529$13_DATA[63:0]$1547 { 24'000000000000000000000000 \ram_dat_w [39:32] 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $1$memwr$\mem_1$ls180.v:5529$13_EN[63:0]$1548 64'0000000000000000000000001111111100000000000000000000000000000000 + case + assign $1$memwr$\mem_1$ls180.v:5529$13_ADDR[3:0]$1546 4'xxxx + assign $1$memwr$\mem_1$ls180.v:5529$13_DATA[63:0]$1547 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\mem_1$ls180.v:5529$13_EN[63:0]$1548 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "ls180.v:5530.2-5531.45" + switch \ram_we [5] + attribute \src "ls180.v:5530.6-5530.15" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\mem_1$ls180.v:5531$14_ADDR[3:0]$1549 \ram_adr + assign $1$memwr$\mem_1$ls180.v:5531$14_DATA[63:0]$1550 { 16'0000000000000000 \ram_dat_w [47:40] 40'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $1$memwr$\mem_1$ls180.v:5531$14_EN[63:0]$1551 64'0000000000000000111111110000000000000000000000000000000000000000 + case + assign $1$memwr$\mem_1$ls180.v:5531$14_ADDR[3:0]$1549 4'xxxx + assign $1$memwr$\mem_1$ls180.v:5531$14_DATA[63:0]$1550 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\mem_1$ls180.v:5531$14_EN[63:0]$1551 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "ls180.v:5532.2-5533.45" + switch \ram_we [6] + attribute \src "ls180.v:5532.6-5532.15" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\mem_1$ls180.v:5533$15_ADDR[3:0]$1552 \ram_adr + assign $1$memwr$\mem_1$ls180.v:5533$15_DATA[63:0]$1553 { 8'00000000 \ram_dat_w [55:48] 48'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $1$memwr$\mem_1$ls180.v:5533$15_EN[63:0]$1554 64'0000000011111111000000000000000000000000000000000000000000000000 + case + assign $1$memwr$\mem_1$ls180.v:5533$15_ADDR[3:0]$1552 4'xxxx + assign $1$memwr$\mem_1$ls180.v:5533$15_DATA[63:0]$1553 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\mem_1$ls180.v:5533$15_EN[63:0]$1554 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "ls180.v:5534.2-5535.45" + switch \ram_we [7] + attribute \src "ls180.v:5534.6-5534.15" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\mem_1$ls180.v:5535$16_ADDR[3:0]$1555 \ram_adr + assign $1$memwr$\mem_1$ls180.v:5535$16_DATA[63:0]$1556 { \ram_dat_w [63:56] 56'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } + assign $1$memwr$\mem_1$ls180.v:5535$16_EN[63:0]$1557 64'1111111100000000000000000000000000000000000000000000000000000000 case + assign $1$memwr$\mem_1$ls180.v:5535$16_ADDR[3:0]$1555 4'xxxx + assign $1$memwr$\mem_1$ls180.v:5535$16_DATA[63:0]$1556 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\mem_1$ls180.v:5535$16_EN[63:0]$1557 64'0000000000000000000000000000000000000000000000000000000000000000 end sync posedge \sys_clk_1 - update \spimaster_clk $0\spimaster_clk[0:0] - update \spimaster_mosi $0\spimaster_mosi[0:0] - update \spimaster_cs_n $0\spimaster_cs_n[0:0] - update \spisdcard_clk $0\spisdcard_clk[0:0] - update \spisdcard_mosi $0\spisdcard_mosi[0:0] - update \spisdcard_cs_n $0\spisdcard_cs_n[0:0] - update \uart_tx $0\uart_tx[0:0] - update \pwm $0\pwm[1:0] - update \main_libresocsim_reset_storage $0\main_libresocsim_reset_storage[0:0] - update \main_libresocsim_reset_re $0\main_libresocsim_reset_re[0:0] - update \main_libresocsim_scratch_storage $0\main_libresocsim_scratch_storage[31:0] - update \main_libresocsim_scratch_re $0\main_libresocsim_scratch_re[0:0] - update \main_libresocsim_bus_errors $0\main_libresocsim_bus_errors[31:0] - update \main_libresocsim_ram_bus_ack $0\main_libresocsim_ram_bus_ack[0:0] - update \main_libresocsim_load_storage $0\main_libresocsim_load_storage[31:0] - update \main_libresocsim_load_re $0\main_libresocsim_load_re[0:0] - update \main_libresocsim_reload_storage $0\main_libresocsim_reload_storage[31:0] - update \main_libresocsim_reload_re $0\main_libresocsim_reload_re[0:0] - update \main_libresocsim_en_storage $0\main_libresocsim_en_storage[0:0] - update \main_libresocsim_en_re $0\main_libresocsim_en_re[0:0] - update \main_libresocsim_update_value_storage $0\main_libresocsim_update_value_storage[0:0] - update \main_libresocsim_update_value_re $0\main_libresocsim_update_value_re[0:0] - update \main_libresocsim_value_status $0\main_libresocsim_value_status[31:0] - update \main_libresocsim_zero_pending $0\main_libresocsim_zero_pending[0:0] - update \main_libresocsim_zero_old_trigger $0\main_libresocsim_zero_old_trigger[0:0] - update \main_libresocsim_eventmanager_storage $0\main_libresocsim_eventmanager_storage[0:0] - update \main_libresocsim_eventmanager_re $0\main_libresocsim_eventmanager_re[0:0] - update \main_libresocsim_value $0\main_libresocsim_value[31:0] - update \main_ram_bus_ram_bus_ack $0\main_ram_bus_ram_bus_ack[0:0] - update \main_converter0_counter $0\main_converter0_counter[0:0] - update \main_converter0_dat_r $0\main_converter0_dat_r[63:0] - update \main_converter1_counter $0\main_converter1_counter[0:0] - update \main_converter1_dat_r $0\main_converter1_dat_r[63:0] - update \main_dfi_p0_rddata_valid $0\main_dfi_p0_rddata_valid[0:0] - update \main_rddata_en $0\main_rddata_en[2:0] - update \main_sdram_storage $0\main_sdram_storage[3:0] - update \main_sdram_re $0\main_sdram_re[0:0] - update \main_sdram_command_storage $0\main_sdram_command_storage[5:0] - update \main_sdram_command_re $0\main_sdram_command_re[0:0] - update \main_sdram_address_storage $0\main_sdram_address_storage[12:0] - update \main_sdram_address_re $0\main_sdram_address_re[0:0] - update \main_sdram_baddress_storage $0\main_sdram_baddress_storage[1:0] - update \main_sdram_baddress_re $0\main_sdram_baddress_re[0:0] - update \main_sdram_wrdata_storage $0\main_sdram_wrdata_storage[15:0] - update \main_sdram_wrdata_re $0\main_sdram_wrdata_re[0:0] - update \main_sdram_status $0\main_sdram_status[15:0] - update \main_sdram_dfi_p0_address $0\main_sdram_dfi_p0_address[12:0] - update \main_sdram_dfi_p0_bank $0\main_sdram_dfi_p0_bank[1:0] - update \main_sdram_dfi_p0_cas_n $0\main_sdram_dfi_p0_cas_n[0:0] - update \main_sdram_dfi_p0_cs_n $0\main_sdram_dfi_p0_cs_n[0:0] - update \main_sdram_dfi_p0_ras_n $0\main_sdram_dfi_p0_ras_n[0:0] - update \main_sdram_dfi_p0_we_n $0\main_sdram_dfi_p0_we_n[0:0] - update \main_sdram_dfi_p0_wrdata_en $0\main_sdram_dfi_p0_wrdata_en[0:0] - update \main_sdram_dfi_p0_rddata_en $0\main_sdram_dfi_p0_rddata_en[0:0] - update \main_sdram_cmd_payload_a $0\main_sdram_cmd_payload_a[12:0] - update \main_sdram_cmd_payload_ba $0\main_sdram_cmd_payload_ba[1:0] - update \main_sdram_cmd_payload_cas $0\main_sdram_cmd_payload_cas[0:0] - update \main_sdram_cmd_payload_ras $0\main_sdram_cmd_payload_ras[0:0] - update \main_sdram_cmd_payload_we $0\main_sdram_cmd_payload_we[0:0] - update \main_sdram_timer_count1 $0\main_sdram_timer_count1[9:0] - update \main_sdram_postponer_req_o $0\main_sdram_postponer_req_o[0:0] - update \main_sdram_postponer_count $0\main_sdram_postponer_count[0:0] - update \main_sdram_sequencer_done1 $0\main_sdram_sequencer_done1[0:0] - update \main_sdram_sequencer_counter $0\main_sdram_sequencer_counter[3:0] - update \main_sdram_sequencer_count $0\main_sdram_sequencer_count[0:0] - update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] - update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] - update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] - update \main_sdram_bankmachine0_cmd_buffer_source_valid $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] - update \main_sdram_bankmachine0_cmd_buffer_source_first $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] - update \main_sdram_bankmachine0_cmd_buffer_source_last $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] - update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] - update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] - update \main_sdram_bankmachine0_row $0\main_sdram_bankmachine0_row[12:0] - update \main_sdram_bankmachine0_row_opened $0\main_sdram_bankmachine0_row_opened[0:0] - update \main_sdram_bankmachine0_twtpcon_ready $0\main_sdram_bankmachine0_twtpcon_ready[0:0] - update \main_sdram_bankmachine0_twtpcon_count $0\main_sdram_bankmachine0_twtpcon_count[2:0] - update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] - update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] - update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] - update \main_sdram_bankmachine1_cmd_buffer_source_valid $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] - update \main_sdram_bankmachine1_cmd_buffer_source_first $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] - update \main_sdram_bankmachine1_cmd_buffer_source_last $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] - update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] - update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] - update \main_sdram_bankmachine1_row $0\main_sdram_bankmachine1_row[12:0] - update \main_sdram_bankmachine1_row_opened $0\main_sdram_bankmachine1_row_opened[0:0] - update \main_sdram_bankmachine1_twtpcon_ready $0\main_sdram_bankmachine1_twtpcon_ready[0:0] - update \main_sdram_bankmachine1_twtpcon_count $0\main_sdram_bankmachine1_twtpcon_count[2:0] - update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] - update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] - update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] - update \main_sdram_bankmachine2_cmd_buffer_source_valid $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] - update \main_sdram_bankmachine2_cmd_buffer_source_first $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] - update \main_sdram_bankmachine2_cmd_buffer_source_last $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] - update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] - update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] - update \main_sdram_bankmachine2_row $0\main_sdram_bankmachine2_row[12:0] - update \main_sdram_bankmachine2_row_opened $0\main_sdram_bankmachine2_row_opened[0:0] - update \main_sdram_bankmachine2_twtpcon_ready $0\main_sdram_bankmachine2_twtpcon_ready[0:0] - update \main_sdram_bankmachine2_twtpcon_count $0\main_sdram_bankmachine2_twtpcon_count[2:0] - update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] - update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] - update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] - update \main_sdram_bankmachine3_cmd_buffer_source_valid $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] - update \main_sdram_bankmachine3_cmd_buffer_source_first $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] - update \main_sdram_bankmachine3_cmd_buffer_source_last $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] - update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] - update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] - update \main_sdram_bankmachine3_row $0\main_sdram_bankmachine3_row[12:0] - update \main_sdram_bankmachine3_row_opened $0\main_sdram_bankmachine3_row_opened[0:0] - update \main_sdram_bankmachine3_twtpcon_ready $0\main_sdram_bankmachine3_twtpcon_ready[0:0] - update \main_sdram_bankmachine3_twtpcon_count $0\main_sdram_bankmachine3_twtpcon_count[2:0] - update \main_sdram_choose_cmd_grant $0\main_sdram_choose_cmd_grant[1:0] - update \main_sdram_choose_req_grant $0\main_sdram_choose_req_grant[1:0] - update \main_sdram_tccdcon_ready $0\main_sdram_tccdcon_ready[0:0] - update \main_sdram_tccdcon_count $0\main_sdram_tccdcon_count[0:0] - update \main_sdram_twtrcon_ready $0\main_sdram_twtrcon_ready[0:0] - update \main_sdram_twtrcon_count $0\main_sdram_twtrcon_count[2:0] - update \main_sdram_time0 $0\main_sdram_time0[4:0] - update \main_sdram_time1 $0\main_sdram_time1[3:0] - update \main_socbushandler_counter $0\main_socbushandler_counter[0:0] - update \main_socbushandler_dat_r $0\main_socbushandler_dat_r[63:0] - update \main_converter_counter $0\main_converter_counter[0:0] - update \main_converter_dat_r $0\main_converter_dat_r[31:0] - update \main_cmd_consumed $0\main_cmd_consumed[0:0] - update \main_wdata_consumed $0\main_wdata_consumed[0:0] - update \main_uart_phy_storage $0\main_uart_phy_storage[31:0] - update \main_uart_phy_re $0\main_uart_phy_re[0:0] - update \main_uart_phy_sink_ready $0\main_uart_phy_sink_ready[0:0] - update \main_uart_phy_uart_clk_txen $0\main_uart_phy_uart_clk_txen[0:0] - update \main_uart_phy_phase_accumulator_tx $0\main_uart_phy_phase_accumulator_tx[31:0] - update \main_uart_phy_tx_reg $0\main_uart_phy_tx_reg[7:0] - update \main_uart_phy_tx_bitcount $0\main_uart_phy_tx_bitcount[3:0] - update \main_uart_phy_tx_busy $0\main_uart_phy_tx_busy[0:0] - update \main_uart_phy_source_valid $0\main_uart_phy_source_valid[0:0] - update \main_uart_phy_source_payload_data $0\main_uart_phy_source_payload_data[7:0] - update \main_uart_phy_uart_clk_rxen $0\main_uart_phy_uart_clk_rxen[0:0] - update \main_uart_phy_phase_accumulator_rx $0\main_uart_phy_phase_accumulator_rx[31:0] - update \main_uart_phy_rx_r $0\main_uart_phy_rx_r[0:0] - update \main_uart_phy_rx_reg $0\main_uart_phy_rx_reg[7:0] - update \main_uart_phy_rx_bitcount $0\main_uart_phy_rx_bitcount[3:0] - update \main_uart_phy_rx_busy $0\main_uart_phy_rx_busy[0:0] - update \main_uart_tx_pending $0\main_uart_tx_pending[0:0] - update \main_uart_tx_old_trigger $0\main_uart_tx_old_trigger[0:0] - update \main_uart_rx_pending $0\main_uart_rx_pending[0:0] - update \main_uart_rx_old_trigger $0\main_uart_rx_old_trigger[0:0] - update \main_uart_eventmanager_storage $0\main_uart_eventmanager_storage[1:0] - update \main_uart_eventmanager_re $0\main_uart_eventmanager_re[0:0] - update \main_uart_tx_fifo_readable $0\main_uart_tx_fifo_readable[0:0] - update \main_uart_tx_fifo_level0 $0\main_uart_tx_fifo_level0[4:0] - update \main_uart_tx_fifo_produce $0\main_uart_tx_fifo_produce[3:0] - update \main_uart_tx_fifo_consume $0\main_uart_tx_fifo_consume[3:0] - update \main_uart_rx_fifo_readable $0\main_uart_rx_fifo_readable[0:0] - update \main_uart_rx_fifo_level0 $0\main_uart_rx_fifo_level0[4:0] - update \main_uart_rx_fifo_produce $0\main_uart_rx_fifo_produce[3:0] - update \main_uart_rx_fifo_consume $0\main_uart_rx_fifo_consume[3:0] - update \main_gpiotristateasic1_oe_storage $0\main_gpiotristateasic1_oe_storage[15:0] - update \main_gpiotristateasic1_oe_re $0\main_gpiotristateasic1_oe_re[0:0] - update \main_gpiotristateasic1_out_storage $0\main_gpiotristateasic1_out_storage[15:0] - update \main_gpiotristateasic1_out_re $0\main_gpiotristateasic1_out_re[0:0] - update \main_spimaster5_miso $0\main_spimaster5_miso[7:0] - update \main_spimaster11_storage $0\main_spimaster11_storage[15:0] - update \main_spimaster12_re $0\main_spimaster12_re[0:0] - update \main_spimaster16_storage $0\main_spimaster16_storage[7:0] - update \main_spimaster17_re $0\main_spimaster17_re[0:0] - update \main_spimaster21_storage $0\main_spimaster21_storage[0:0] - update \main_spimaster22_re $0\main_spimaster22_re[0:0] - update \main_spimaster23_storage $0\main_spimaster23_storage[0:0] - update \main_spimaster24_re $0\main_spimaster24_re[0:0] - update \main_spimaster27_count $0\main_spimaster27_count[2:0] - update \main_spimaster30_clk_divider $0\main_spimaster30_clk_divider[15:0] - update \main_spimaster33_mosi_data $0\main_spimaster33_mosi_data[7:0] - update \main_spimaster34_mosi_sel $0\main_spimaster34_mosi_sel[2:0] - update \main_spimaster35_miso_data $0\main_spimaster35_miso_data[7:0] - update \main_spisdcard_miso $0\main_spisdcard_miso[7:0] - update \main_spisdcard_control_storage $0\main_spisdcard_control_storage[15:0] - update \main_spisdcard_control_re $0\main_spisdcard_control_re[0:0] - update \main_spisdcard_mosi_storage $0\main_spisdcard_mosi_storage[7:0] - update \main_spisdcard_mosi_re $0\main_spisdcard_mosi_re[0:0] - update \main_spisdcard_cs_storage $0\main_spisdcard_cs_storage[0:0] - update \main_spisdcard_cs_re $0\main_spisdcard_cs_re[0:0] - update \main_spisdcard_loopback_storage $0\main_spisdcard_loopback_storage[0:0] - update \main_spisdcard_loopback_re $0\main_spisdcard_loopback_re[0:0] - update \main_spisdcard_count $0\main_spisdcard_count[2:0] - update \main_spisdcard_clk_divider1 $0\main_spisdcard_clk_divider1[15:0] - update \main_spisdcard_mosi_data $0\main_spisdcard_mosi_data[7:0] - update \main_spisdcard_mosi_sel $0\main_spisdcard_mosi_sel[2:0] - update \main_spisdcard_miso_data $0\main_spisdcard_miso_data[7:0] - update \main_spimaster1_storage $0\main_spimaster1_storage[15:0] - update \main_spimaster1_re $0\main_spimaster1_re[0:0] - update \main_dummy $0\main_dummy[23:0] - update \main_pwm0_counter $0\main_pwm0_counter[31:0] - update \main_pwm0_enable_storage $0\main_pwm0_enable_storage[0:0] - update \main_pwm0_enable_re $0\main_pwm0_enable_re[0:0] - update \main_pwm0_width_storage $0\main_pwm0_width_storage[31:0] - update \main_pwm0_width_re $0\main_pwm0_width_re[0:0] - update \main_pwm0_period_storage $0\main_pwm0_period_storage[31:0] - update \main_pwm0_period_re $0\main_pwm0_period_re[0:0] - update \main_pwm1_counter $0\main_pwm1_counter[31:0] - update \main_pwm1_enable_storage $0\main_pwm1_enable_storage[0:0] - update \main_pwm1_enable_re $0\main_pwm1_enable_re[0:0] - update \main_pwm1_width_storage $0\main_pwm1_width_storage[31:0] - update \main_pwm1_width_re $0\main_pwm1_width_re[0:0] - update \main_pwm1_period_storage $0\main_pwm1_period_storage[31:0] - update \main_pwm1_period_re $0\main_pwm1_period_re[0:0] - update \main_i2c_storage $0\main_i2c_storage[2:0] - update \main_i2c_re $0\main_i2c_re[0:0] - update \main_sdphy_clocker_storage $0\main_sdphy_clocker_storage[8:0] - update \main_sdphy_clocker_re $0\main_sdphy_clocker_re[0:0] - update \main_sdphy_clocker_clk0 $0\main_sdphy_clocker_clk0[0:0] - update \main_sdphy_clocker_clks $0\main_sdphy_clocker_clks[8:0] - update \main_sdphy_clocker_clk_d $0\main_sdphy_clocker_clk_d[0:0] - update \main_sdphy_init_count $0\main_sdphy_init_count[7:0] - update \main_sdphy_cmdw_count $0\main_sdphy_cmdw_count[7:0] - update \main_sdphy_cmdr_timeout $0\main_sdphy_cmdr_timeout[31:0] - update \main_sdphy_cmdr_count $0\main_sdphy_cmdr_count[7:0] - update \main_sdphy_cmdr_cmdr_run $0\main_sdphy_cmdr_cmdr_run[0:0] - update \main_sdphy_cmdr_cmdr_converter_source_first $0\main_sdphy_cmdr_cmdr_converter_source_first[0:0] - update \main_sdphy_cmdr_cmdr_converter_source_last $0\main_sdphy_cmdr_cmdr_converter_source_last[0:0] - update \main_sdphy_cmdr_cmdr_converter_source_payload_data $0\main_sdphy_cmdr_cmdr_converter_source_payload_data[7:0] - update \main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count $0\main_sdphy_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] - update \main_sdphy_cmdr_cmdr_converter_demux $0\main_sdphy_cmdr_cmdr_converter_demux[2:0] - update \main_sdphy_cmdr_cmdr_converter_strobe_all $0\main_sdphy_cmdr_cmdr_converter_strobe_all[0:0] - update \main_sdphy_cmdr_cmdr_buf_source_valid $0\main_sdphy_cmdr_cmdr_buf_source_valid[0:0] - update \main_sdphy_cmdr_cmdr_buf_source_first $0\main_sdphy_cmdr_cmdr_buf_source_first[0:0] - update \main_sdphy_cmdr_cmdr_buf_source_last $0\main_sdphy_cmdr_cmdr_buf_source_last[0:0] - update \main_sdphy_cmdr_cmdr_buf_source_payload_data $0\main_sdphy_cmdr_cmdr_buf_source_payload_data[7:0] - update \main_sdphy_cmdr_cmdr_reset $0\main_sdphy_cmdr_cmdr_reset[0:0] - update \main_sdphy_dataw_count $0\main_sdphy_dataw_count[7:0] - update \main_sdphy_dataw_crcr_run $0\main_sdphy_dataw_crcr_run[0:0] - update \main_sdphy_dataw_crcr_converter_source_first $0\main_sdphy_dataw_crcr_converter_source_first[0:0] - update \main_sdphy_dataw_crcr_converter_source_last $0\main_sdphy_dataw_crcr_converter_source_last[0:0] - update \main_sdphy_dataw_crcr_converter_source_payload_data $0\main_sdphy_dataw_crcr_converter_source_payload_data[7:0] - update \main_sdphy_dataw_crcr_converter_source_payload_valid_token_count $0\main_sdphy_dataw_crcr_converter_source_payload_valid_token_count[3:0] - update \main_sdphy_dataw_crcr_converter_demux $0\main_sdphy_dataw_crcr_converter_demux[2:0] - update \main_sdphy_dataw_crcr_converter_strobe_all $0\main_sdphy_dataw_crcr_converter_strobe_all[0:0] - update \main_sdphy_dataw_crcr_buf_source_valid $0\main_sdphy_dataw_crcr_buf_source_valid[0:0] - update \main_sdphy_dataw_crcr_buf_source_first $0\main_sdphy_dataw_crcr_buf_source_first[0:0] - update \main_sdphy_dataw_crcr_buf_source_last $0\main_sdphy_dataw_crcr_buf_source_last[0:0] - update \main_sdphy_dataw_crcr_buf_source_payload_data $0\main_sdphy_dataw_crcr_buf_source_payload_data[7:0] - update \main_sdphy_dataw_crcr_reset $0\main_sdphy_dataw_crcr_reset[0:0] - update \main_sdphy_datar_timeout $0\main_sdphy_datar_timeout[31:0] - update \main_sdphy_datar_count $0\main_sdphy_datar_count[9:0] - update \main_sdphy_datar_datar_run $0\main_sdphy_datar_datar_run[0:0] - update \main_sdphy_datar_datar_converter_source_first $0\main_sdphy_datar_datar_converter_source_first[0:0] - update \main_sdphy_datar_datar_converter_source_last $0\main_sdphy_datar_datar_converter_source_last[0:0] - update \main_sdphy_datar_datar_converter_source_payload_data $0\main_sdphy_datar_datar_converter_source_payload_data[7:0] - update \main_sdphy_datar_datar_converter_source_payload_valid_token_count $0\main_sdphy_datar_datar_converter_source_payload_valid_token_count[1:0] - update \main_sdphy_datar_datar_converter_demux $0\main_sdphy_datar_datar_converter_demux[0:0] - update \main_sdphy_datar_datar_converter_strobe_all $0\main_sdphy_datar_datar_converter_strobe_all[0:0] - update \main_sdphy_datar_datar_buf_source_valid $0\main_sdphy_datar_datar_buf_source_valid[0:0] - update \main_sdphy_datar_datar_buf_source_first $0\main_sdphy_datar_datar_buf_source_first[0:0] - update \main_sdphy_datar_datar_buf_source_last $0\main_sdphy_datar_datar_buf_source_last[0:0] - update \main_sdphy_datar_datar_buf_source_payload_data $0\main_sdphy_datar_datar_buf_source_payload_data[7:0] - update \main_sdphy_datar_datar_reset $0\main_sdphy_datar_datar_reset[0:0] - update \main_sdcore_cmd_argument_storage $0\main_sdcore_cmd_argument_storage[31:0] - update \main_sdcore_cmd_argument_re $0\main_sdcore_cmd_argument_re[0:0] - update \main_sdcore_cmd_command_storage $0\main_sdcore_cmd_command_storage[31:0] - update \main_sdcore_cmd_command_re $0\main_sdcore_cmd_command_re[0:0] - update \main_sdcore_cmd_response_status $0\main_sdcore_cmd_response_status[127:0] - update \main_sdcore_block_length_storage $0\main_sdcore_block_length_storage[9:0] - update \main_sdcore_block_length_re $0\main_sdcore_block_length_re[0:0] - update \main_sdcore_block_count_storage $0\main_sdcore_block_count_storage[31:0] - update \main_sdcore_block_count_re $0\main_sdcore_block_count_re[0:0] - update \main_sdcore_crc7_inserter_crcreg0 $0\main_sdcore_crc7_inserter_crcreg0[6:0] - update \main_sdcore_crc16_inserter_cnt $0\main_sdcore_crc16_inserter_cnt[2:0] - update \main_sdcore_crc16_inserter_crc0_crcreg0 $0\main_sdcore_crc16_inserter_crc0_crcreg0[15:0] - update \main_sdcore_crc16_inserter_crc1_crcreg0 $0\main_sdcore_crc16_inserter_crc1_crcreg0[15:0] - update \main_sdcore_crc16_inserter_crc2_crcreg0 $0\main_sdcore_crc16_inserter_crc2_crcreg0[15:0] - update \main_sdcore_crc16_inserter_crc3_crcreg0 $0\main_sdcore_crc16_inserter_crc3_crcreg0[15:0] - update \main_sdcore_crc16_inserter_crctmp0 $0\main_sdcore_crc16_inserter_crctmp0[15:0] - update \main_sdcore_crc16_inserter_crctmp1 $0\main_sdcore_crc16_inserter_crctmp1[15:0] - update \main_sdcore_crc16_inserter_crctmp2 $0\main_sdcore_crc16_inserter_crctmp2[15:0] - update \main_sdcore_crc16_inserter_crctmp3 $0\main_sdcore_crc16_inserter_crctmp3[15:0] - update \main_sdcore_crc16_checker_val $0\main_sdcore_crc16_checker_val[7:0] - update \main_sdcore_crc16_checker_cnt $0\main_sdcore_crc16_checker_cnt[3:0] - update \main_sdcore_crc16_checker_crc0_crcreg0 $0\main_sdcore_crc16_checker_crc0_crcreg0[15:0] - update \main_sdcore_crc16_checker_crc1_crcreg0 $0\main_sdcore_crc16_checker_crc1_crcreg0[15:0] - update \main_sdcore_crc16_checker_crc2_crcreg0 $0\main_sdcore_crc16_checker_crc2_crcreg0[15:0] - update \main_sdcore_crc16_checker_crc3_crcreg0 $0\main_sdcore_crc16_checker_crc3_crcreg0[15:0] - update \main_sdcore_crc16_checker_crctmp0 $0\main_sdcore_crc16_checker_crctmp0[15:0] - update \main_sdcore_crc16_checker_crctmp1 $0\main_sdcore_crc16_checker_crctmp1[15:0] - update \main_sdcore_crc16_checker_crctmp2 $0\main_sdcore_crc16_checker_crctmp2[15:0] - update \main_sdcore_crc16_checker_crctmp3 $0\main_sdcore_crc16_checker_crctmp3[15:0] - update \main_sdcore_crc16_checker_fifo0 $0\main_sdcore_crc16_checker_fifo0[15:0] - update \main_sdcore_crc16_checker_fifo1 $0\main_sdcore_crc16_checker_fifo1[15:0] - update \main_sdcore_crc16_checker_fifo2 $0\main_sdcore_crc16_checker_fifo2[15:0] - update \main_sdcore_crc16_checker_fifo3 $0\main_sdcore_crc16_checker_fifo3[15:0] - update \main_sdcore_cmd_count $0\main_sdcore_cmd_count[2:0] - update \main_sdcore_cmd_done $0\main_sdcore_cmd_done[0:0] - update \main_sdcore_cmd_error $0\main_sdcore_cmd_error[0:0] - update \main_sdcore_cmd_timeout $0\main_sdcore_cmd_timeout[0:0] - update \main_sdcore_data_count $0\main_sdcore_data_count[31:0] - update \main_sdcore_data_done $0\main_sdcore_data_done[0:0] - update \main_sdcore_data_error $0\main_sdcore_data_error[0:0] - update \main_sdcore_data_timeout $0\main_sdcore_data_timeout[0:0] - update \main_sdblock2mem_fifo_level $0\main_sdblock2mem_fifo_level[5:0] - update \main_sdblock2mem_fifo_produce $0\main_sdblock2mem_fifo_produce[4:0] - update \main_sdblock2mem_fifo_consume $0\main_sdblock2mem_fifo_consume[4:0] - update \main_sdblock2mem_converter_source_first $0\main_sdblock2mem_converter_source_first[0:0] - update \main_sdblock2mem_converter_source_last $0\main_sdblock2mem_converter_source_last[0:0] - update \main_sdblock2mem_converter_source_payload_data $0\main_sdblock2mem_converter_source_payload_data[63:0] - update \main_sdblock2mem_converter_source_payload_valid_token_count $0\main_sdblock2mem_converter_source_payload_valid_token_count[3:0] - update \main_sdblock2mem_converter_demux $0\main_sdblock2mem_converter_demux[2:0] - update \main_sdblock2mem_converter_strobe_all $0\main_sdblock2mem_converter_strobe_all[0:0] - update \main_sdblock2mem_wishbonedmawriter_base_storage $0\main_sdblock2mem_wishbonedmawriter_base_storage[63:0] - update \main_sdblock2mem_wishbonedmawriter_base_re $0\main_sdblock2mem_wishbonedmawriter_base_re[0:0] - update \main_sdblock2mem_wishbonedmawriter_length_storage $0\main_sdblock2mem_wishbonedmawriter_length_storage[31:0] - update \main_sdblock2mem_wishbonedmawriter_length_re $0\main_sdblock2mem_wishbonedmawriter_length_re[0:0] - update \main_sdblock2mem_wishbonedmawriter_enable_storage $0\main_sdblock2mem_wishbonedmawriter_enable_storage[0:0] - update \main_sdblock2mem_wishbonedmawriter_enable_re $0\main_sdblock2mem_wishbonedmawriter_enable_re[0:0] - update \main_sdblock2mem_wishbonedmawriter_loop_storage $0\main_sdblock2mem_wishbonedmawriter_loop_storage[0:0] - update \main_sdblock2mem_wishbonedmawriter_loop_re $0\main_sdblock2mem_wishbonedmawriter_loop_re[0:0] - update \main_sdblock2mem_wishbonedmawriter_offset $0\main_sdblock2mem_wishbonedmawriter_offset[31:0] - update \main_sdmem2block_dma_data $0\main_sdmem2block_dma_data[63:0] - update \main_sdmem2block_dma_base_storage $0\main_sdmem2block_dma_base_storage[63:0] - update \main_sdmem2block_dma_base_re $0\main_sdmem2block_dma_base_re[0:0] - update \main_sdmem2block_dma_length_storage $0\main_sdmem2block_dma_length_storage[31:0] - update \main_sdmem2block_dma_length_re $0\main_sdmem2block_dma_length_re[0:0] - update \main_sdmem2block_dma_enable_storage $0\main_sdmem2block_dma_enable_storage[0:0] - update \main_sdmem2block_dma_enable_re $0\main_sdmem2block_dma_enable_re[0:0] - update \main_sdmem2block_dma_loop_storage $0\main_sdmem2block_dma_loop_storage[0:0] - update \main_sdmem2block_dma_loop_re $0\main_sdmem2block_dma_loop_re[0:0] - update \main_sdmem2block_dma_offset $0\main_sdmem2block_dma_offset[31:0] - update \main_sdmem2block_converter_mux $0\main_sdmem2block_converter_mux[2:0] - update \main_sdmem2block_fifo_level $0\main_sdmem2block_fifo_level[5:0] - update \main_sdmem2block_fifo_produce $0\main_sdmem2block_fifo_produce[4:0] - update \main_sdmem2block_fifo_consume $0\main_sdmem2block_fifo_consume[4:0] - update \builder_converter0_state $0\builder_converter0_state[0:0] - update \builder_converter1_state $0\builder_converter1_state[0:0] - update \builder_converter2_state $0\builder_converter2_state[0:0] - update \builder_refresher_state $0\builder_refresher_state[1:0] - update \builder_bankmachine0_state $0\builder_bankmachine0_state[2:0] - update \builder_bankmachine1_state $0\builder_bankmachine1_state[2:0] - update \builder_bankmachine2_state $0\builder_bankmachine2_state[2:0] - update \builder_bankmachine3_state $0\builder_bankmachine3_state[2:0] - update \builder_multiplexer_state $0\builder_multiplexer_state[2:0] - update \builder_new_master_wdata_ready $0\builder_new_master_wdata_ready[0:0] - update \builder_new_master_rdata_valid0 $0\builder_new_master_rdata_valid0[0:0] - update \builder_new_master_rdata_valid1 $0\builder_new_master_rdata_valid1[0:0] - update \builder_new_master_rdata_valid2 $0\builder_new_master_rdata_valid2[0:0] - update \builder_new_master_rdata_valid3 $0\builder_new_master_rdata_valid3[0:0] - update \builder_converter_state $0\builder_converter_state[0:0] - update \builder_spimaster0_state $0\builder_spimaster0_state[1:0] - update \builder_spimaster1_state $0\builder_spimaster1_state[1:0] - update \builder_sdphy_sdphyinit_state $0\builder_sdphy_sdphyinit_state[0:0] - update \builder_sdphy_sdphycmdw_state $0\builder_sdphy_sdphycmdw_state[1:0] - update \builder_sdphy_sdphycmdr_state $0\builder_sdphy_sdphycmdr_state[2:0] - update \builder_sdphy_sdphycrcr_state $0\builder_sdphy_sdphycrcr_state[0:0] - update \builder_sdphy_fsm_state $0\builder_sdphy_fsm_state[2:0] - update \builder_sdphy_sdphydatar_state $0\builder_sdphy_sdphydatar_state[2:0] - update \builder_sdcore_crcupstreaminserter_state $0\builder_sdcore_crcupstreaminserter_state[0:0] - update \builder_sdcore_fsm_state $0\builder_sdcore_fsm_state[2:0] - update \builder_sdblock2memdma_state $0\builder_sdblock2memdma_state[1:0] - update \builder_sdmem2blockdma_fsm_state $0\builder_sdmem2blockdma_fsm_state[0:0] - update \builder_sdmem2blockdma_resetinserter_state $0\builder_sdmem2blockdma_resetinserter_state[1:0] - update \builder_libresocsim_adr $0\builder_libresocsim_adr[13:0] - update \builder_libresocsim_we $0\builder_libresocsim_we[0:0] - update \builder_libresocsim_dat_w $0\builder_libresocsim_dat_w[7:0] - update \builder_grant $0\builder_grant[2:0] - update \builder_slave_sel_r $0\builder_slave_sel_r[5:0] - update \builder_count $0\builder_count[19:0] - update \builder_interface0_bank_bus_dat_r $0\builder_interface0_bank_bus_dat_r[7:0] - update \builder_interface1_bank_bus_dat_r $0\builder_interface1_bank_bus_dat_r[7:0] - update \builder_interface2_bank_bus_dat_r $0\builder_interface2_bank_bus_dat_r[7:0] - update \builder_interface3_bank_bus_dat_r $0\builder_interface3_bank_bus_dat_r[7:0] - update \builder_interface4_bank_bus_dat_r $0\builder_interface4_bank_bus_dat_r[7:0] - update \builder_interface5_bank_bus_dat_r $0\builder_interface5_bank_bus_dat_r[7:0] - update \builder_interface6_bank_bus_dat_r $0\builder_interface6_bank_bus_dat_r[7:0] - update \builder_interface7_bank_bus_dat_r $0\builder_interface7_bank_bus_dat_r[7:0] - update \builder_interface8_bank_bus_dat_r $0\builder_interface8_bank_bus_dat_r[7:0] - update \builder_interface9_bank_bus_dat_r $0\builder_interface9_bank_bus_dat_r[7:0] - update \builder_interface10_bank_bus_dat_r $0\builder_interface10_bank_bus_dat_r[7:0] - update \builder_interface11_bank_bus_dat_r $0\builder_interface11_bank_bus_dat_r[7:0] - update \builder_interface12_bank_bus_dat_r $0\builder_interface12_bank_bus_dat_r[7:0] - update \builder_interface13_bank_bus_dat_r $0\builder_interface13_bank_bus_dat_r[7:0] - update \builder_interface14_bank_bus_dat_r $0\builder_interface14_bank_bus_dat_r[7:0] - update \builder_state $0\builder_state[1:0] - update \builder_multiregimpl0_regs0 $0\builder_multiregimpl0_regs0[0:0] - update \builder_multiregimpl0_regs1 $0\builder_multiregimpl0_regs1[0:0] - update \builder_multiregimpl1_regs0 $0\builder_multiregimpl1_regs0[0:0] - update \builder_multiregimpl1_regs1 $0\builder_multiregimpl1_regs1[0:0] - update \builder_multiregimpl2_regs0 $0\builder_multiregimpl2_regs0[0:0] - update \builder_multiregimpl2_regs1 $0\builder_multiregimpl2_regs1[0:0] - update \builder_multiregimpl3_regs0 $0\builder_multiregimpl3_regs0[0:0] - update \builder_multiregimpl3_regs1 $0\builder_multiregimpl3_regs1[0:0] - update \builder_multiregimpl4_regs0 $0\builder_multiregimpl4_regs0[0:0] - update \builder_multiregimpl4_regs1 $0\builder_multiregimpl4_regs1[0:0] - update \builder_multiregimpl5_regs0 $0\builder_multiregimpl5_regs0[0:0] - update \builder_multiregimpl5_regs1 $0\builder_multiregimpl5_regs1[0:0] - update \builder_multiregimpl6_regs0 $0\builder_multiregimpl6_regs0[0:0] - update \builder_multiregimpl6_regs1 $0\builder_multiregimpl6_regs1[0:0] - update \builder_multiregimpl7_regs0 $0\builder_multiregimpl7_regs0[0:0] - update \builder_multiregimpl7_regs1 $0\builder_multiregimpl7_regs1[0:0] - update \builder_multiregimpl8_regs0 $0\builder_multiregimpl8_regs0[0:0] - update \builder_multiregimpl8_regs1 $0\builder_multiregimpl8_regs1[0:0] - update \builder_multiregimpl9_regs0 $0\builder_multiregimpl9_regs0[0:0] - update \builder_multiregimpl9_regs1 $0\builder_multiregimpl9_regs1[0:0] - update \builder_multiregimpl10_regs0 $0\builder_multiregimpl10_regs0[0:0] - update \builder_multiregimpl10_regs1 $0\builder_multiregimpl10_regs1[0:0] - update \builder_multiregimpl11_regs0 $0\builder_multiregimpl11_regs0[0:0] - update \builder_multiregimpl11_regs1 $0\builder_multiregimpl11_regs1[0:0] - update \builder_multiregimpl12_regs0 $0\builder_multiregimpl12_regs0[0:0] - update \builder_multiregimpl12_regs1 $0\builder_multiregimpl12_regs1[0:0] - update \builder_multiregimpl13_regs0 $0\builder_multiregimpl13_regs0[0:0] - update \builder_multiregimpl13_regs1 $0\builder_multiregimpl13_regs1[0:0] - update \builder_multiregimpl14_regs0 $0\builder_multiregimpl14_regs0[0:0] - update \builder_multiregimpl14_regs1 $0\builder_multiregimpl14_regs1[0:0] - update \builder_multiregimpl15_regs0 $0\builder_multiregimpl15_regs0[0:0] - update \builder_multiregimpl15_regs1 $0\builder_multiregimpl15_regs1[0:0] - update \builder_multiregimpl16_regs0 $0\builder_multiregimpl16_regs0[0:0] - update \builder_multiregimpl16_regs1 $0\builder_multiregimpl16_regs1[0:0] + update \memadr_1 $0\memadr_1[3:0] + update $memwr$\mem_1$ls180.v:5521$9_ADDR $0$memwr$\mem_1$ls180.v:5521$9_ADDR[3:0]$1510 + update $memwr$\mem_1$ls180.v:5521$9_DATA $0$memwr$\mem_1$ls180.v:5521$9_DATA[63:0]$1511 + update $memwr$\mem_1$ls180.v:5521$9_EN $0$memwr$\mem_1$ls180.v:5521$9_EN[63:0]$1512 + update $memwr$\mem_1$ls180.v:5523$10_ADDR $0$memwr$\mem_1$ls180.v:5523$10_ADDR[3:0]$1513 + update $memwr$\mem_1$ls180.v:5523$10_DATA $0$memwr$\mem_1$ls180.v:5523$10_DATA[63:0]$1514 + update $memwr$\mem_1$ls180.v:5523$10_EN $0$memwr$\mem_1$ls180.v:5523$10_EN[63:0]$1515 + update $memwr$\mem_1$ls180.v:5525$11_ADDR $0$memwr$\mem_1$ls180.v:5525$11_ADDR[3:0]$1516 + update $memwr$\mem_1$ls180.v:5525$11_DATA $0$memwr$\mem_1$ls180.v:5525$11_DATA[63:0]$1517 + update $memwr$\mem_1$ls180.v:5525$11_EN $0$memwr$\mem_1$ls180.v:5525$11_EN[63:0]$1518 + update $memwr$\mem_1$ls180.v:5527$12_ADDR $0$memwr$\mem_1$ls180.v:5527$12_ADDR[3:0]$1519 + update $memwr$\mem_1$ls180.v:5527$12_DATA $0$memwr$\mem_1$ls180.v:5527$12_DATA[63:0]$1520 + update $memwr$\mem_1$ls180.v:5527$12_EN $0$memwr$\mem_1$ls180.v:5527$12_EN[63:0]$1521 + update $memwr$\mem_1$ls180.v:5529$13_ADDR $0$memwr$\mem_1$ls180.v:5529$13_ADDR[3:0]$1522 + update $memwr$\mem_1$ls180.v:5529$13_DATA $0$memwr$\mem_1$ls180.v:5529$13_DATA[63:0]$1523 + update $memwr$\mem_1$ls180.v:5529$13_EN $0$memwr$\mem_1$ls180.v:5529$13_EN[63:0]$1524 + update $memwr$\mem_1$ls180.v:5531$14_ADDR $0$memwr$\mem_1$ls180.v:5531$14_ADDR[3:0]$1525 + update $memwr$\mem_1$ls180.v:5531$14_DATA $0$memwr$\mem_1$ls180.v:5531$14_DATA[63:0]$1526 + update $memwr$\mem_1$ls180.v:5531$14_EN $0$memwr$\mem_1$ls180.v:5531$14_EN[63:0]$1527 + update $memwr$\mem_1$ls180.v:5533$15_ADDR $0$memwr$\mem_1$ls180.v:5533$15_ADDR[3:0]$1528 + update $memwr$\mem_1$ls180.v:5533$15_DATA $0$memwr$\mem_1$ls180.v:5533$15_DATA[63:0]$1529 + update $memwr$\mem_1$ls180.v:5533$15_EN $0$memwr$\mem_1$ls180.v:5533$15_EN[63:0]$1530 + update $memwr$\mem_1$ls180.v:5535$16_ADDR $0$memwr$\mem_1$ls180.v:5535$16_ADDR[3:0]$1531 + update $memwr$\mem_1$ls180.v:5535$16_DATA $0$memwr$\mem_1$ls180.v:5535$16_DATA[63:0]$1532 + update $memwr$\mem_1$ls180.v:5535$16_EN $0$memwr$\mem_1$ls180.v:5535$16_EN[63:0]$1533 + attribute \src "ls180.v:5521.3-5521.40" + memwr \mem_1 $1$memwr$\mem_1$ls180.v:5521$9_ADDR[3:0]$1534 $1$memwr$\mem_1$ls180.v:5521$9_DATA[63:0]$1535 $1$memwr$\mem_1$ls180.v:5521$9_EN[63:0]$1536 0' + attribute \src "ls180.v:5523.3-5523.42" + memwr \mem_1 $1$memwr$\mem_1$ls180.v:5523$10_ADDR[3:0]$1537 $1$memwr$\mem_1$ls180.v:5523$10_DATA[63:0]$1538 $1$memwr$\mem_1$ls180.v:5523$10_EN[63:0]$1539 1'1 + attribute \src "ls180.v:5525.3-5525.44" + memwr \mem_1 $1$memwr$\mem_1$ls180.v:5525$11_ADDR[3:0]$1540 $1$memwr$\mem_1$ls180.v:5525$11_DATA[63:0]$1541 $1$memwr$\mem_1$ls180.v:5525$11_EN[63:0]$1542 2'11 + attribute \src "ls180.v:5527.3-5527.44" + memwr \mem_1 $1$memwr$\mem_1$ls180.v:5527$12_ADDR[3:0]$1543 $1$memwr$\mem_1$ls180.v:5527$12_DATA[63:0]$1544 $1$memwr$\mem_1$ls180.v:5527$12_EN[63:0]$1545 3'111 + attribute \src "ls180.v:5529.3-5529.44" + memwr \mem_1 $1$memwr$\mem_1$ls180.v:5529$13_ADDR[3:0]$1546 $1$memwr$\mem_1$ls180.v:5529$13_DATA[63:0]$1547 $1$memwr$\mem_1$ls180.v:5529$13_EN[63:0]$1548 4'1111 + attribute \src "ls180.v:5531.3-5531.44" + memwr \mem_1 $1$memwr$\mem_1$ls180.v:5531$14_ADDR[3:0]$1549 $1$memwr$\mem_1$ls180.v:5531$14_DATA[63:0]$1550 $1$memwr$\mem_1$ls180.v:5531$14_EN[63:0]$1551 5'11111 + attribute \src "ls180.v:5533.3-5533.44" + memwr \mem_1 $1$memwr$\mem_1$ls180.v:5533$15_ADDR[3:0]$1552 $1$memwr$\mem_1$ls180.v:5533$15_DATA[63:0]$1553 $1$memwr$\mem_1$ls180.v:5533$15_EN[63:0]$1554 6'111111 + attribute \src "ls180.v:5535.3-5535.44" + memwr \mem_1 $1$memwr$\mem_1$ls180.v:5535$16_ADDR[3:0]$1555 $1$memwr$\mem_1$ls180.v:5535$16_DATA[63:0]$1556 $1$memwr$\mem_1$ls180.v:5535$16_EN[63:0]$1557 7'1111111 + end + attribute \src "ls180.v:552.32-552.71" + process $proc$ls180.v:552$1827 + assign { } { } + assign $0\sdram_bankmachine1_trascon_ready[0:0] 1'1 + sync always + update \sdram_bankmachine1_trascon_ready $0\sdram_bankmachine1_trascon_ready[0:0] + sync init + end + attribute \src "ls180.v:5547.1-5551.4" + process $proc$ls180.v:5547$1559 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage$ls180.v:5549$17_ADDR[2:0]$1560 $1$memwr$\storage$ls180.v:5549$17_ADDR[2:0]$1563 + assign $0$memwr$\storage$ls180.v:5549$17_DATA[24:0]$1561 $1$memwr$\storage$ls180.v:5549$17_DATA[24:0]$1564 + assign $0$memwr$\storage$ls180.v:5549$17_EN[24:0]$1562 $1$memwr$\storage$ls180.v:5549$17_EN[24:0]$1565 + assign $0\memdat[24:0] $memrd$\storage$ls180.v:5550$1566_DATA + attribute \src "ls180.v:5548.2-5549.119" + switch \sdram_bankmachine0_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:5548.6-5548.55" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\storage$ls180.v:5549$17_ADDR[2:0]$1563 \sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + assign $1$memwr$\storage$ls180.v:5549$17_DATA[24:0]$1564 \sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w + assign $1$memwr$\storage$ls180.v:5549$17_EN[24:0]$1565 25'1111111111111111111111111 + case + assign $1$memwr$\storage$ls180.v:5549$17_ADDR[2:0]$1563 3'xxx + assign $1$memwr$\storage$ls180.v:5549$17_DATA[24:0]$1564 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\storage$ls180.v:5549$17_EN[24:0]$1565 25'0000000000000000000000000 + end + sync posedge \sys_clk_1 + update \memdat $0\memdat[24:0] + update $memwr$\storage$ls180.v:5549$17_ADDR $0$memwr$\storage$ls180.v:5549$17_ADDR[2:0]$1560 + update $memwr$\storage$ls180.v:5549$17_DATA $0$memwr$\storage$ls180.v:5549$17_DATA[24:0]$1561 + update $memwr$\storage$ls180.v:5549$17_EN $0$memwr$\storage$ls180.v:5549$17_EN[24:0]$1562 + attribute \src "ls180.v:5549.3-5549.118" + memwr \storage $1$memwr$\storage$ls180.v:5549$17_ADDR[2:0]$1563 $1$memwr$\storage$ls180.v:5549$17_DATA[24:0]$1564 $1$memwr$\storage$ls180.v:5549$17_EN[24:0]$1565 0' + end + attribute \src "ls180.v:5553.1-5554.4" + process $proc$ls180.v:5553$1567 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:5561.1-5565.4" + process $proc$ls180.v:5561$1569 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_1$ls180.v:5563$18_ADDR[2:0]$1570 $1$memwr$\storage_1$ls180.v:5563$18_ADDR[2:0]$1573 + assign $0$memwr$\storage_1$ls180.v:5563$18_DATA[24:0]$1571 $1$memwr$\storage_1$ls180.v:5563$18_DATA[24:0]$1574 + assign $0$memwr$\storage_1$ls180.v:5563$18_EN[24:0]$1572 $1$memwr$\storage_1$ls180.v:5563$18_EN[24:0]$1575 + assign $0\memdat_1[24:0] $memrd$\storage_1$ls180.v:5564$1576_DATA + attribute \src "ls180.v:5562.2-5563.121" + switch \sdram_bankmachine1_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:5562.6-5562.55" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\storage_1$ls180.v:5563$18_ADDR[2:0]$1573 \sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + assign $1$memwr$\storage_1$ls180.v:5563$18_DATA[24:0]$1574 \sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w + assign $1$memwr$\storage_1$ls180.v:5563$18_EN[24:0]$1575 25'1111111111111111111111111 + case + assign $1$memwr$\storage_1$ls180.v:5563$18_ADDR[2:0]$1573 3'xxx + assign $1$memwr$\storage_1$ls180.v:5563$18_DATA[24:0]$1574 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\storage_1$ls180.v:5563$18_EN[24:0]$1575 25'0000000000000000000000000 + end + sync posedge \sys_clk_1 + update \memdat_1 $0\memdat_1[24:0] + update $memwr$\storage_1$ls180.v:5563$18_ADDR $0$memwr$\storage_1$ls180.v:5563$18_ADDR[2:0]$1570 + update $memwr$\storage_1$ls180.v:5563$18_DATA $0$memwr$\storage_1$ls180.v:5563$18_DATA[24:0]$1571 + update $memwr$\storage_1$ls180.v:5563$18_EN $0$memwr$\storage_1$ls180.v:5563$18_EN[24:0]$1572 + attribute \src "ls180.v:5563.3-5563.120" + memwr \storage_1 $1$memwr$\storage_1$ls180.v:5563$18_ADDR[2:0]$1573 $1$memwr$\storage_1$ls180.v:5563$18_DATA[24:0]$1574 $1$memwr$\storage_1$ls180.v:5563$18_EN[24:0]$1575 0' + end + attribute \src "ls180.v:5567.1-5568.4" + process $proc$ls180.v:5567$1577 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:5575.1-5579.4" + process $proc$ls180.v:5575$1579 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_2$ls180.v:5577$19_ADDR[2:0]$1580 $1$memwr$\storage_2$ls180.v:5577$19_ADDR[2:0]$1583 + assign $0$memwr$\storage_2$ls180.v:5577$19_DATA[24:0]$1581 $1$memwr$\storage_2$ls180.v:5577$19_DATA[24:0]$1584 + assign $0$memwr$\storage_2$ls180.v:5577$19_EN[24:0]$1582 $1$memwr$\storage_2$ls180.v:5577$19_EN[24:0]$1585 + assign $0\memdat_2[24:0] $memrd$\storage_2$ls180.v:5578$1586_DATA + attribute \src "ls180.v:5576.2-5577.121" + switch \sdram_bankmachine2_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:5576.6-5576.55" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\storage_2$ls180.v:5577$19_ADDR[2:0]$1583 \sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + assign $1$memwr$\storage_2$ls180.v:5577$19_DATA[24:0]$1584 \sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w + assign $1$memwr$\storage_2$ls180.v:5577$19_EN[24:0]$1585 25'1111111111111111111111111 + case + assign $1$memwr$\storage_2$ls180.v:5577$19_ADDR[2:0]$1583 3'xxx + assign $1$memwr$\storage_2$ls180.v:5577$19_DATA[24:0]$1584 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\storage_2$ls180.v:5577$19_EN[24:0]$1585 25'0000000000000000000000000 + end + sync posedge \sys_clk_1 + update \memdat_2 $0\memdat_2[24:0] + update $memwr$\storage_2$ls180.v:5577$19_ADDR $0$memwr$\storage_2$ls180.v:5577$19_ADDR[2:0]$1580 + update $memwr$\storage_2$ls180.v:5577$19_DATA $0$memwr$\storage_2$ls180.v:5577$19_DATA[24:0]$1581 + update $memwr$\storage_2$ls180.v:5577$19_EN $0$memwr$\storage_2$ls180.v:5577$19_EN[24:0]$1582 + attribute \src "ls180.v:5577.3-5577.120" + memwr \storage_2 $1$memwr$\storage_2$ls180.v:5577$19_ADDR[2:0]$1583 $1$memwr$\storage_2$ls180.v:5577$19_DATA[24:0]$1584 $1$memwr$\storage_2$ls180.v:5577$19_EN[24:0]$1585 0' + end + attribute \src "ls180.v:558.5-558.46" + process $proc$ls180.v:558$1828 + assign { } { } + assign $1\sdram_bankmachine2_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine2_req_wdata_ready $1\sdram_bankmachine2_req_wdata_ready[0:0] + end + attribute \src "ls180.v:5581.1-5582.4" + process $proc$ls180.v:5581$1587 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:5589.1-5593.4" + process $proc$ls180.v:5589$1589 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_3$ls180.v:5591$20_ADDR[2:0]$1590 $1$memwr$\storage_3$ls180.v:5591$20_ADDR[2:0]$1593 + assign $0$memwr$\storage_3$ls180.v:5591$20_DATA[24:0]$1591 $1$memwr$\storage_3$ls180.v:5591$20_DATA[24:0]$1594 + assign $0$memwr$\storage_3$ls180.v:5591$20_EN[24:0]$1592 $1$memwr$\storage_3$ls180.v:5591$20_EN[24:0]$1595 + assign $0\memdat_3[24:0] $memrd$\storage_3$ls180.v:5592$1596_DATA + attribute \src "ls180.v:5590.2-5591.121" + switch \sdram_bankmachine3_cmd_buffer_lookahead_wrport_we + attribute \src "ls180.v:5590.6-5590.55" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\storage_3$ls180.v:5591$20_ADDR[2:0]$1593 \sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + assign $1$memwr$\storage_3$ls180.v:5591$20_DATA[24:0]$1594 \sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w + assign $1$memwr$\storage_3$ls180.v:5591$20_EN[24:0]$1595 25'1111111111111111111111111 + case + assign $1$memwr$\storage_3$ls180.v:5591$20_ADDR[2:0]$1593 3'xxx + assign $1$memwr$\storage_3$ls180.v:5591$20_DATA[24:0]$1594 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\storage_3$ls180.v:5591$20_EN[24:0]$1595 25'0000000000000000000000000 + end + sync posedge \sys_clk_1 + update \memdat_3 $0\memdat_3[24:0] + update $memwr$\storage_3$ls180.v:5591$20_ADDR $0$memwr$\storage_3$ls180.v:5591$20_ADDR[2:0]$1590 + update $memwr$\storage_3$ls180.v:5591$20_DATA $0$memwr$\storage_3$ls180.v:5591$20_DATA[24:0]$1591 + update $memwr$\storage_3$ls180.v:5591$20_EN $0$memwr$\storage_3$ls180.v:5591$20_EN[24:0]$1592 + attribute \src "ls180.v:5591.3-5591.120" + memwr \storage_3 $1$memwr$\storage_3$ls180.v:5591$20_ADDR[2:0]$1593 $1$memwr$\storage_3$ls180.v:5591$20_DATA[24:0]$1594 $1$memwr$\storage_3$ls180.v:5591$20_EN[24:0]$1595 0' + end + attribute \src "ls180.v:559.5-559.46" + process $proc$ls180.v:559$1829 + assign { } { } + assign $1\sdram_bankmachine2_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine2_req_rdata_valid $1\sdram_bankmachine2_req_rdata_valid[0:0] + end + attribute \src "ls180.v:5595.1-5596.4" + process $proc$ls180.v:5595$1597 + sync posedge \sys_clk_1 + end + attribute \src "ls180.v:5604.1-5608.4" + process $proc$ls180.v:5604$1599 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_4$ls180.v:5606$21_ADDR[3:0]$1600 $1$memwr$\storage_4$ls180.v:5606$21_ADDR[3:0]$1603 + assign $0$memwr$\storage_4$ls180.v:5606$21_DATA[9:0]$1601 $1$memwr$\storage_4$ls180.v:5606$21_DATA[9:0]$1604 + assign $0$memwr$\storage_4$ls180.v:5606$21_EN[9:0]$1602 $1$memwr$\storage_4$ls180.v:5606$21_EN[9:0]$1605 + assign $0\memdat_4[9:0] $memrd$\storage_4$ls180.v:5607$1606_DATA + attribute \src "ls180.v:5605.2-5606.57" + switch \tx_fifo_wrport_we + attribute \src "ls180.v:5605.6-5605.23" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\storage_4$ls180.v:5606$21_ADDR[3:0]$1603 \tx_fifo_wrport_adr + assign $1$memwr$\storage_4$ls180.v:5606$21_DATA[9:0]$1604 \tx_fifo_wrport_dat_w + assign $1$memwr$\storage_4$ls180.v:5606$21_EN[9:0]$1605 10'1111111111 + case + assign $1$memwr$\storage_4$ls180.v:5606$21_ADDR[3:0]$1603 4'xxxx + assign $1$memwr$\storage_4$ls180.v:5606$21_DATA[9:0]$1604 10'xxxxxxxxxx + assign $1$memwr$\storage_4$ls180.v:5606$21_EN[9:0]$1605 10'0000000000 + end + sync posedge \sys_clk_1 + update \memdat_4 $0\memdat_4[9:0] + update $memwr$\storage_4$ls180.v:5606$21_ADDR $0$memwr$\storage_4$ls180.v:5606$21_ADDR[3:0]$1600 + update $memwr$\storage_4$ls180.v:5606$21_DATA $0$memwr$\storage_4$ls180.v:5606$21_DATA[9:0]$1601 + update $memwr$\storage_4$ls180.v:5606$21_EN $0$memwr$\storage_4$ls180.v:5606$21_EN[9:0]$1602 + attribute \src "ls180.v:5606.3-5606.56" + memwr \storage_4 $1$memwr$\storage_4$ls180.v:5606$21_ADDR[3:0]$1603 $1$memwr$\storage_4$ls180.v:5606$21_DATA[9:0]$1604 $1$memwr$\storage_4$ls180.v:5606$21_EN[9:0]$1605 0' + end + attribute \src "ls180.v:561.5-561.42" + process $proc$ls180.v:561$1830 + assign { } { } + assign $1\sdram_bankmachine2_refresh_gnt[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine2_refresh_gnt $1\sdram_bankmachine2_refresh_gnt[0:0] + end + attribute \src "ls180.v:5610.1-5613.4" + process $proc$ls180.v:5610$1607 + assign $0\memdat_5[9:0] \memdat_5 + attribute \src "ls180.v:5611.2-5612.45" + switch \tx_fifo_rdport_re + attribute \src "ls180.v:5611.6-5611.23" + case 1'1 + assign $0\memdat_5[9:0] $memrd$\storage_4$ls180.v:5612$1608_DATA + case + end + sync posedge \sys_clk_1 + update \memdat_5 $0\memdat_5[9:0] + end + attribute \src "ls180.v:562.5-562.40" + process $proc$ls180.v:562$1831 + assign { } { } + assign $1\sdram_bankmachine2_cmd_valid[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine2_cmd_valid $1\sdram_bankmachine2_cmd_valid[0:0] + end + attribute \src "ls180.v:5621.1-5625.4" + process $proc$ls180.v:5621$1609 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_5$ls180.v:5623$22_ADDR[3:0]$1610 $1$memwr$\storage_5$ls180.v:5623$22_ADDR[3:0]$1613 + assign $0$memwr$\storage_5$ls180.v:5623$22_DATA[9:0]$1611 $1$memwr$\storage_5$ls180.v:5623$22_DATA[9:0]$1614 + assign $0$memwr$\storage_5$ls180.v:5623$22_EN[9:0]$1612 $1$memwr$\storage_5$ls180.v:5623$22_EN[9:0]$1615 + assign $0\memdat_6[9:0] $memrd$\storage_5$ls180.v:5624$1616_DATA + attribute \src "ls180.v:5622.2-5623.57" + switch \rx_fifo_wrport_we + attribute \src "ls180.v:5622.6-5622.23" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\storage_5$ls180.v:5623$22_ADDR[3:0]$1613 \rx_fifo_wrport_adr + assign $1$memwr$\storage_5$ls180.v:5623$22_DATA[9:0]$1614 \rx_fifo_wrport_dat_w + assign $1$memwr$\storage_5$ls180.v:5623$22_EN[9:0]$1615 10'1111111111 + case + assign $1$memwr$\storage_5$ls180.v:5623$22_ADDR[3:0]$1613 4'xxxx + assign $1$memwr$\storage_5$ls180.v:5623$22_DATA[9:0]$1614 10'xxxxxxxxxx + assign $1$memwr$\storage_5$ls180.v:5623$22_EN[9:0]$1615 10'0000000000 + end + sync posedge \sys_clk_1 + update \memdat_6 $0\memdat_6[9:0] + update $memwr$\storage_5$ls180.v:5623$22_ADDR $0$memwr$\storage_5$ls180.v:5623$22_ADDR[3:0]$1610 + update $memwr$\storage_5$ls180.v:5623$22_DATA $0$memwr$\storage_5$ls180.v:5623$22_DATA[9:0]$1611 + update $memwr$\storage_5$ls180.v:5623$22_EN $0$memwr$\storage_5$ls180.v:5623$22_EN[9:0]$1612 + attribute \src "ls180.v:5623.3-5623.56" + memwr \storage_5 $1$memwr$\storage_5$ls180.v:5623$22_ADDR[3:0]$1613 $1$memwr$\storage_5$ls180.v:5623$22_DATA[9:0]$1614 $1$memwr$\storage_5$ls180.v:5623$22_EN[9:0]$1615 0' + end + attribute \src "ls180.v:5627.1-5630.4" + process $proc$ls180.v:5627$1617 + assign $0\memdat_7[9:0] \memdat_7 + attribute \src "ls180.v:5628.2-5629.45" + switch \rx_fifo_rdport_re + attribute \src "ls180.v:5628.6-5628.23" + case 1'1 + assign $0\memdat_7[9:0] $memrd$\storage_5$ls180.v:5629$1618_DATA + case + end + sync posedge \sys_clk_1 + update \memdat_7 $0\memdat_7[9:0] + end + attribute \src "ls180.v:563.5-563.40" + process $proc$ls180.v:563$1832 + assign { } { } + assign $1\sdram_bankmachine2_cmd_ready[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine2_cmd_ready $1\sdram_bankmachine2_cmd_ready[0:0] + end + attribute \src "ls180.v:564.12-564.52" + process $proc$ls180.v:564$1833 + assign { } { } + assign $1\sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \sdram_bankmachine2_cmd_payload_a $1\sdram_bankmachine2_cmd_payload_a[12:0] + end + attribute \src "ls180.v:566.5-566.46" + process $proc$ls180.v:566$1834 + assign { } { } + assign $1\sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine2_cmd_payload_cas $1\sdram_bankmachine2_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:567.5-567.46" + process $proc$ls180.v:567$1835 + assign { } { } + assign $1\sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine2_cmd_payload_ras $1\sdram_bankmachine2_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:568.5-568.45" + process $proc$ls180.v:568$1836 + assign { } { } + assign $1\sdram_bankmachine2_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine2_cmd_payload_we $1\sdram_bankmachine2_cmd_payload_we[0:0] + end + attribute \src "ls180.v:569.5-569.49" + process $proc$ls180.v:569$1837 + assign { } { } + assign $1\sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine2_cmd_payload_is_cmd $1\sdram_bankmachine2_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:570.5-570.50" + process $proc$ls180.v:570$1838 + assign { } { } + assign $1\sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine2_cmd_payload_is_read $1\sdram_bankmachine2_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:571.5-571.51" + process $proc$ls180.v:571$1839 + assign { } { } + assign $1\sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine2_cmd_payload_is_write $1\sdram_bankmachine2_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:572.5-572.45" + process $proc$ls180.v:572$1840 + assign { } { } + assign $1\sdram_bankmachine2_auto_precharge[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine2_auto_precharge $1\sdram_bankmachine2_auto_precharge[0:0] + end + attribute \src "ls180.v:575.5-575.62" + process $proc$ls180.v:575$1841 + assign { } { } + assign $0\sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \sdram_bankmachine2_cmd_buffer_lookahead_sink_first $0\sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:576.5-576.61" + process $proc$ls180.v:576$1842 + assign { } { } + assign $0\sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \sdram_bankmachine2_cmd_buffer_lookahead_sink_last $0\sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:591.11-591.63" + process $proc$ls180.v:591$1843 + assign { } { } + assign $1\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \sdram_bankmachine2_cmd_buffer_lookahead_level $1\sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + end + attribute \src "ls180.v:592.5-592.59" + process $proc$ls180.v:592$1844 + assign { } { } + assign $0\sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \sdram_bankmachine2_cmd_buffer_lookahead_replace $0\sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:593.11-593.65" + process $proc$ls180.v:593$1845 + assign { } { } + assign $1\sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \sdram_bankmachine2_cmd_buffer_lookahead_produce $1\sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:594.11-594.65" + process $proc$ls180.v:594$1846 + assign { } { } + assign $1\sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \sdram_bankmachine2_cmd_buffer_lookahead_consume $1\sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:595.11-595.68" + process $proc$ls180.v:595$1847 + assign { } { } + assign $1\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $1\sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:616.5-616.54" + process $proc$ls180.v:616$1848 + assign { } { } + assign $1\sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine2_cmd_buffer_source_valid $1\sdram_bankmachine2_cmd_buffer_source_valid[0:0] + end + attribute \src "ls180.v:618.5-618.54" + process $proc$ls180.v:618$1849 + assign { } { } + assign $1\sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine2_cmd_buffer_source_first $1\sdram_bankmachine2_cmd_buffer_source_first[0:0] + end + attribute \src "ls180.v:619.5-619.53" + process $proc$ls180.v:619$1850 + assign { } { } + assign $1\sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine2_cmd_buffer_source_last $1\sdram_bankmachine2_cmd_buffer_source_last[0:0] + end + attribute \src "ls180.v:62.11-62.47" + process $proc$ls180.v:62$1626 + assign { } { } + assign $0\libresocsim_libresoc_dbus_cti[2:0] 3'000 + sync always + update \libresocsim_libresoc_dbus_cti $0\libresocsim_libresoc_dbus_cti[2:0] + sync init + end + attribute \src "ls180.v:620.5-620.59" + process $proc$ls180.v:620$1851 + assign { } { } + assign $1\sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine2_cmd_buffer_source_payload_we $1\sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + end + attribute \src "ls180.v:621.12-621.69" + process $proc$ls180.v:621$1852 + assign { } { } + assign $1\sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \sdram_bankmachine2_cmd_buffer_source_payload_addr $1\sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "ls180.v:622.12-622.42" + process $proc$ls180.v:622$1853 + assign { } { } + assign $1\sdram_bankmachine2_row[12:0] 13'0000000000000 + sync always + sync init + update \sdram_bankmachine2_row $1\sdram_bankmachine2_row[12:0] + end + attribute \src "ls180.v:623.5-623.41" + process $proc$ls180.v:623$1854 + assign { } { } + assign $1\sdram_bankmachine2_row_opened[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine2_row_opened $1\sdram_bankmachine2_row_opened[0:0] + end + attribute \src "ls180.v:625.5-625.39" + process $proc$ls180.v:625$1855 + assign { } { } + assign $1\sdram_bankmachine2_row_open[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine2_row_open $1\sdram_bankmachine2_row_open[0:0] + end + attribute \src "ls180.v:626.5-626.40" + process $proc$ls180.v:626$1856 + assign { } { } + assign $1\sdram_bankmachine2_row_close[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine2_row_close $1\sdram_bankmachine2_row_close[0:0] + end + attribute \src "ls180.v:627.5-627.49" + process $proc$ls180.v:627$1857 + assign { } { } + assign $1\sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine2_row_col_n_addr_sel $1\sdram_bankmachine2_row_col_n_addr_sel[0:0] + end + attribute \src "ls180.v:629.32-629.71" + process $proc$ls180.v:629$1858 + assign { } { } + assign $1\sdram_bankmachine2_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine2_twtpcon_ready $1\sdram_bankmachine2_twtpcon_ready[0:0] + end + attribute \src "ls180.v:63.11-63.47" + process $proc$ls180.v:63$1627 + assign { } { } + assign $0\libresocsim_libresoc_dbus_bte[1:0] 2'00 + sync always + update \libresocsim_libresoc_dbus_bte $0\libresocsim_libresoc_dbus_bte[1:0] + sync init + end + attribute \src "ls180.v:630.11-630.50" + process $proc$ls180.v:630$1859 + assign { } { } + assign $1\sdram_bankmachine2_twtpcon_count[2:0] 3'000 + sync always + sync init + update \sdram_bankmachine2_twtpcon_count $1\sdram_bankmachine2_twtpcon_count[2:0] + end + attribute \src "ls180.v:632.32-632.70" + process $proc$ls180.v:632$1860 + assign { } { } + assign $0\sdram_bankmachine2_trccon_ready[0:0] 1'1 + sync always + update \sdram_bankmachine2_trccon_ready $0\sdram_bankmachine2_trccon_ready[0:0] + sync init + end + attribute \src "ls180.v:634.32-634.71" + process $proc$ls180.v:634$1861 + assign { } { } + assign $0\sdram_bankmachine2_trascon_ready[0:0] 1'1 + sync always + update \sdram_bankmachine2_trascon_ready $0\sdram_bankmachine2_trascon_ready[0:0] + sync init + end + attribute \src "ls180.v:640.5-640.46" + process $proc$ls180.v:640$1862 + assign { } { } + assign $1\sdram_bankmachine3_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine3_req_wdata_ready $1\sdram_bankmachine3_req_wdata_ready[0:0] + end + attribute \src "ls180.v:641.5-641.46" + process $proc$ls180.v:641$1863 + assign { } { } + assign $1\sdram_bankmachine3_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine3_req_rdata_valid $1\sdram_bankmachine3_req_rdata_valid[0:0] + end + attribute \src "ls180.v:643.5-643.42" + process $proc$ls180.v:643$1864 + assign { } { } + assign $1\sdram_bankmachine3_refresh_gnt[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine3_refresh_gnt $1\sdram_bankmachine3_refresh_gnt[0:0] + end + attribute \src "ls180.v:644.5-644.40" + process $proc$ls180.v:644$1865 + assign { } { } + assign $1\sdram_bankmachine3_cmd_valid[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine3_cmd_valid $1\sdram_bankmachine3_cmd_valid[0:0] + end + attribute \src "ls180.v:645.5-645.40" + process $proc$ls180.v:645$1866 + assign { } { } + assign $1\sdram_bankmachine3_cmd_ready[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine3_cmd_ready $1\sdram_bankmachine3_cmd_ready[0:0] + end + attribute \src "ls180.v:646.12-646.52" + process $proc$ls180.v:646$1867 + assign { } { } + assign $1\sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \sdram_bankmachine3_cmd_payload_a $1\sdram_bankmachine3_cmd_payload_a[12:0] + end + attribute \src "ls180.v:648.5-648.46" + process $proc$ls180.v:648$1868 + assign { } { } + assign $1\sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine3_cmd_payload_cas $1\sdram_bankmachine3_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:649.5-649.46" + process $proc$ls180.v:649$1869 + assign { } { } + assign $1\sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine3_cmd_payload_ras $1\sdram_bankmachine3_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:650.5-650.45" + process $proc$ls180.v:650$1870 + assign { } { } + assign $1\sdram_bankmachine3_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine3_cmd_payload_we $1\sdram_bankmachine3_cmd_payload_we[0:0] + end + attribute \src "ls180.v:651.5-651.49" + process $proc$ls180.v:651$1871 + assign { } { } + assign $1\sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine3_cmd_payload_is_cmd $1\sdram_bankmachine3_cmd_payload_is_cmd[0:0] + end + attribute \src "ls180.v:652.5-652.50" + process $proc$ls180.v:652$1872 + assign { } { } + assign $1\sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine3_cmd_payload_is_read $1\sdram_bankmachine3_cmd_payload_is_read[0:0] + end + attribute \src "ls180.v:653.5-653.51" + process $proc$ls180.v:653$1873 + assign { } { } + assign $1\sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine3_cmd_payload_is_write $1\sdram_bankmachine3_cmd_payload_is_write[0:0] + end + attribute \src "ls180.v:654.5-654.45" + process $proc$ls180.v:654$1874 + assign { } { } + assign $1\sdram_bankmachine3_auto_precharge[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine3_auto_precharge $1\sdram_bankmachine3_auto_precharge[0:0] + end + attribute \src "ls180.v:657.5-657.62" + process $proc$ls180.v:657$1875 + assign { } { } + assign $0\sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \sdram_bankmachine3_cmd_buffer_lookahead_sink_first $0\sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "ls180.v:658.5-658.61" + process $proc$ls180.v:658$1876 + assign { } { } + assign $0\sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \sdram_bankmachine3_cmd_buffer_lookahead_sink_last $0\sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "ls180.v:673.11-673.63" + process $proc$ls180.v:673$1877 + assign { } { } + assign $1\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \sdram_bankmachine3_cmd_buffer_lookahead_level $1\sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + end + attribute \src "ls180.v:674.5-674.59" + process $proc$ls180.v:674$1878 + assign { } { } + assign $0\sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \sdram_bankmachine3_cmd_buffer_lookahead_replace $0\sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "ls180.v:675.11-675.65" + process $proc$ls180.v:675$1879 + assign { } { } + assign $1\sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \sdram_bankmachine3_cmd_buffer_lookahead_produce $1\sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "ls180.v:676.11-676.65" + process $proc$ls180.v:676$1880 + assign { } { } + assign $1\sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \sdram_bankmachine3_cmd_buffer_lookahead_consume $1\sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "ls180.v:677.11-677.68" + process $proc$ls180.v:677$1881 + assign { } { } + assign $1\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "ls180.v:698.5-698.54" + process $proc$ls180.v:698$1882 + assign { } { } + assign $1\sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine3_cmd_buffer_source_valid $1\sdram_bankmachine3_cmd_buffer_source_valid[0:0] + end + attribute \src "ls180.v:700.5-700.54" + process $proc$ls180.v:700$1883 + assign { } { } + assign $1\sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine3_cmd_buffer_source_first $1\sdram_bankmachine3_cmd_buffer_source_first[0:0] + end + attribute \src "ls180.v:701.5-701.53" + process $proc$ls180.v:701$1884 + assign { } { } + assign $1\sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine3_cmd_buffer_source_last $1\sdram_bankmachine3_cmd_buffer_source_last[0:0] + end + attribute \src "ls180.v:702.5-702.59" + process $proc$ls180.v:702$1885 + assign { } { } + assign $1\sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine3_cmd_buffer_source_payload_we $1\sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + end + attribute \src "ls180.v:703.12-703.69" + process $proc$ls180.v:703$1886 + assign { } { } + assign $1\sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \sdram_bankmachine3_cmd_buffer_source_payload_addr $1\sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "ls180.v:704.12-704.42" + process $proc$ls180.v:704$1887 + assign { } { } + assign $1\sdram_bankmachine3_row[12:0] 13'0000000000000 + sync always + sync init + update \sdram_bankmachine3_row $1\sdram_bankmachine3_row[12:0] + end + attribute \src "ls180.v:705.5-705.41" + process $proc$ls180.v:705$1888 + assign { } { } + assign $1\sdram_bankmachine3_row_opened[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine3_row_opened $1\sdram_bankmachine3_row_opened[0:0] + end + attribute \src "ls180.v:707.5-707.39" + process $proc$ls180.v:707$1889 + assign { } { } + assign $1\sdram_bankmachine3_row_open[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine3_row_open $1\sdram_bankmachine3_row_open[0:0] + end + attribute \src "ls180.v:708.5-708.40" + process $proc$ls180.v:708$1890 + assign { } { } + assign $1\sdram_bankmachine3_row_close[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine3_row_close $1\sdram_bankmachine3_row_close[0:0] + end + attribute \src "ls180.v:709.5-709.49" + process $proc$ls180.v:709$1891 + assign { } { } + assign $1\sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine3_row_col_n_addr_sel $1\sdram_bankmachine3_row_col_n_addr_sel[0:0] + end + attribute \src "ls180.v:711.32-711.71" + process $proc$ls180.v:711$1892 + assign { } { } + assign $1\sdram_bankmachine3_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \sdram_bankmachine3_twtpcon_ready $1\sdram_bankmachine3_twtpcon_ready[0:0] + end + attribute \src "ls180.v:712.11-712.50" + process $proc$ls180.v:712$1893 + assign { } { } + assign $1\sdram_bankmachine3_twtpcon_count[2:0] 3'000 + sync always + sync init + update \sdram_bankmachine3_twtpcon_count $1\sdram_bankmachine3_twtpcon_count[2:0] + end + attribute \src "ls180.v:714.32-714.70" + process $proc$ls180.v:714$1894 + assign { } { } + assign $0\sdram_bankmachine3_trccon_ready[0:0] 1'1 + sync always + update \sdram_bankmachine3_trccon_ready $0\sdram_bankmachine3_trccon_ready[0:0] + sync init + end + attribute \src "ls180.v:716.32-716.71" + process $proc$ls180.v:716$1895 + assign { } { } + assign $0\sdram_bankmachine3_trascon_ready[0:0] 1'1 + sync always + update \sdram_bankmachine3_trascon_ready $0\sdram_bankmachine3_trascon_ready[0:0] + sync init + end + attribute \src "ls180.v:719.5-719.39" + process $proc$ls180.v:719$1896 + assign { } { } + assign $0\sdram_choose_cmd_want_reads[0:0] 1'0 + sync always + update \sdram_choose_cmd_want_reads $0\sdram_choose_cmd_want_reads[0:0] + sync init + end + attribute \src "ls180.v:720.5-720.40" + process $proc$ls180.v:720$1897 + assign { } { } + assign $0\sdram_choose_cmd_want_writes[0:0] 1'0 + sync always + update \sdram_choose_cmd_want_writes $0\sdram_choose_cmd_want_writes[0:0] + sync init + end + attribute \src "ls180.v:721.5-721.38" + process $proc$ls180.v:721$1898 + assign { } { } + assign $0\sdram_choose_cmd_want_cmds[0:0] 1'0 + sync always + update \sdram_choose_cmd_want_cmds $0\sdram_choose_cmd_want_cmds[0:0] + sync init + end + attribute \src "ls180.v:722.5-722.43" + process $proc$ls180.v:722$1899 + assign { } { } + assign $0\sdram_choose_cmd_want_activates[0:0] 1'0 + sync always + update \sdram_choose_cmd_want_activates $0\sdram_choose_cmd_want_activates[0:0] + sync init + end + attribute \src "ls180.v:724.5-724.38" + process $proc$ls180.v:724$1900 + assign { } { } + assign $0\sdram_choose_cmd_cmd_ready[0:0] 1'0 + sync always + update \sdram_choose_cmd_cmd_ready $0\sdram_choose_cmd_cmd_ready[0:0] + sync init + end + attribute \src "ls180.v:727.5-727.44" + process $proc$ls180.v:727$1901 + assign { } { } + assign $1\sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \sdram_choose_cmd_cmd_payload_cas $1\sdram_choose_cmd_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:728.5-728.44" + process $proc$ls180.v:728$1902 + assign { } { } + assign $1\sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \sdram_choose_cmd_cmd_payload_ras $1\sdram_choose_cmd_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:729.5-729.43" + process $proc$ls180.v:729$1903 + assign { } { } + assign $1\sdram_choose_cmd_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \sdram_choose_cmd_cmd_payload_we $1\sdram_choose_cmd_cmd_payload_we[0:0] + end + attribute \src "ls180.v:73.11-73.47" + process $proc$ls180.v:73$1628 + assign { } { } + assign $0\libresocsim_libresoc_ibus_cti[2:0] 3'000 + sync always + update \libresocsim_libresoc_ibus_cti $0\libresocsim_libresoc_ibus_cti[2:0] + sync init + end + attribute \src "ls180.v:733.11-733.41" + process $proc$ls180.v:733$1904 + assign { } { } + assign $1\sdram_choose_cmd_valids[3:0] 4'0000 + sync always + sync init + update \sdram_choose_cmd_valids $1\sdram_choose_cmd_valids[3:0] + end + attribute \src "ls180.v:735.11-735.40" + process $proc$ls180.v:735$1905 + assign { } { } + assign $1\sdram_choose_cmd_grant[1:0] 2'00 + sync always + sync init + update \sdram_choose_cmd_grant $1\sdram_choose_cmd_grant[1:0] + end + attribute \src "ls180.v:737.5-737.39" + process $proc$ls180.v:737$1906 + assign { } { } + assign $1\sdram_choose_req_want_reads[0:0] 1'0 + sync always + sync init + update \sdram_choose_req_want_reads $1\sdram_choose_req_want_reads[0:0] + end + attribute \src "ls180.v:738.5-738.40" + process $proc$ls180.v:738$1907 + assign { } { } + assign $1\sdram_choose_req_want_writes[0:0] 1'0 + sync always + sync init + update \sdram_choose_req_want_writes $1\sdram_choose_req_want_writes[0:0] + end + attribute \src "ls180.v:74.11-74.47" + process $proc$ls180.v:74$1629 + assign { } { } + assign $0\libresocsim_libresoc_ibus_bte[1:0] 2'00 + sync always + update \libresocsim_libresoc_ibus_bte $0\libresocsim_libresoc_ibus_bte[1:0] + sync init + end + attribute \src "ls180.v:740.5-740.43" + process $proc$ls180.v:740$1908 + assign { } { } + assign $1\sdram_choose_req_want_activates[0:0] 1'0 + sync always + sync init + update \sdram_choose_req_want_activates $1\sdram_choose_req_want_activates[0:0] + end + attribute \src "ls180.v:742.5-742.38" + process $proc$ls180.v:742$1909 + assign { } { } + assign $1\sdram_choose_req_cmd_ready[0:0] 1'0 + sync always + sync init + update \sdram_choose_req_cmd_ready $1\sdram_choose_req_cmd_ready[0:0] + end + attribute \src "ls180.v:745.5-745.44" + process $proc$ls180.v:745$1910 + assign { } { } + assign $1\sdram_choose_req_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \sdram_choose_req_cmd_payload_cas $1\sdram_choose_req_cmd_payload_cas[0:0] + end + attribute \src "ls180.v:746.5-746.44" + process $proc$ls180.v:746$1911 + assign { } { } + assign $1\sdram_choose_req_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \sdram_choose_req_cmd_payload_ras $1\sdram_choose_req_cmd_payload_ras[0:0] + end + attribute \src "ls180.v:747.5-747.43" + process $proc$ls180.v:747$1912 + assign { } { } + assign $1\sdram_choose_req_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \sdram_choose_req_cmd_payload_we $1\sdram_choose_req_cmd_payload_we[0:0] + end + attribute \src "ls180.v:751.11-751.41" + process $proc$ls180.v:751$1913 + assign { } { } + assign $1\sdram_choose_req_valids[3:0] 4'0000 + sync always + sync init + update \sdram_choose_req_valids $1\sdram_choose_req_valids[3:0] + end + attribute \src "ls180.v:753.11-753.40" + process $proc$ls180.v:753$1914 + assign { } { } + assign $1\sdram_choose_req_grant[1:0] 2'00 + sync always + sync init + update \sdram_choose_req_grant $1\sdram_choose_req_grant[1:0] + end + attribute \src "ls180.v:755.12-755.31" + process $proc$ls180.v:755$1915 + assign { } { } + assign $0\sdram_nop_a[12:0] 13'0000000000000 + sync always + update \sdram_nop_a $0\sdram_nop_a[12:0] + sync init + end + attribute \src "ls180.v:756.11-756.30" + process $proc$ls180.v:756$1916 + assign { } { } + assign $0\sdram_nop_ba[1:0] 2'00 + sync always + update \sdram_nop_ba $0\sdram_nop_ba[1:0] + sync init + end + attribute \src "ls180.v:757.11-757.35" + process $proc$ls180.v:757$1917 + assign { } { } + assign $1\sdram_steerer_sel[1:0] 2'00 + sync always + sync init + update \sdram_steerer_sel $1\sdram_steerer_sel[1:0] + end + attribute \src "ls180.v:758.5-758.26" + process $proc$ls180.v:758$1918 + assign { } { } + assign $0\sdram_steerer0[0:0] 1'1 + sync always + update \sdram_steerer0 $0\sdram_steerer0[0:0] + sync init + end + attribute \src "ls180.v:759.5-759.26" + process $proc$ls180.v:759$1919 + assign { } { } + assign $0\sdram_steerer1[0:0] 1'1 + sync always + update \sdram_steerer1 $0\sdram_steerer1[0:0] + sync init + end + attribute \src "ls180.v:76.12-76.53" + process $proc$ls180.v:76$1630 + assign { } { } + assign $1\libresocsim_libresoc_xics_icp_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \libresocsim_libresoc_xics_icp_adr $1\libresocsim_libresoc_xics_icp_adr[29:0] + end + attribute \src "ls180.v:761.32-761.58" + process $proc$ls180.v:761$1920 + assign { } { } + assign $0\sdram_trrdcon_ready[0:0] 1'1 + sync always + update \sdram_trrdcon_ready $0\sdram_trrdcon_ready[0:0] + sync init + end + attribute \src "ls180.v:763.32-763.58" + process $proc$ls180.v:763$1921 + assign { } { } + assign $0\sdram_tfawcon_ready[0:0] 1'1 + sync always + update \sdram_tfawcon_ready $0\sdram_tfawcon_ready[0:0] + sync init + end + attribute \src "ls180.v:765.32-765.58" + process $proc$ls180.v:765$1922 + assign { } { } + assign $1\sdram_tccdcon_ready[0:0] 1'0 + sync always + sync init + update \sdram_tccdcon_ready $1\sdram_tccdcon_ready[0:0] + end + attribute \src "ls180.v:766.5-766.31" + process $proc$ls180.v:766$1923 + assign { } { } + assign $1\sdram_tccdcon_count[0:0] 1'0 + sync always + sync init + update \sdram_tccdcon_count $1\sdram_tccdcon_count[0:0] + end + attribute \src "ls180.v:768.32-768.58" + process $proc$ls180.v:768$1924 + assign { } { } + assign $1\sdram_twtrcon_ready[0:0] 1'0 + sync always + sync init + update \sdram_twtrcon_ready $1\sdram_twtrcon_ready[0:0] end - attribute \src "ls180.v:755.11-755.46" - process $proc$ls180.v:755$3147 + attribute \src "ls180.v:769.11-769.37" + process $proc$ls180.v:769$1925 assign { } { } - assign $1\main_sdram_choose_cmd_valids[3:0] 4'0000 + assign $1\sdram_twtrcon_count[2:0] 3'000 sync always sync init - update \main_sdram_choose_cmd_valids $1\main_sdram_choose_cmd_valids[3:0] + update \sdram_twtrcon_count $1\sdram_twtrcon_count[2:0] end - attribute \src "ls180.v:757.11-757.45" - process $proc$ls180.v:757$3148 + attribute \src "ls180.v:77.12-77.55" + process $proc$ls180.v:77$1631 assign { } { } - assign $1\main_sdram_choose_cmd_grant[1:0] 2'00 + assign $1\libresocsim_libresoc_xics_icp_dat_w[31:0] 0 sync always sync init - update \main_sdram_choose_cmd_grant $1\main_sdram_choose_cmd_grant[1:0] + update \libresocsim_libresoc_xics_icp_dat_w $1\libresocsim_libresoc_xics_icp_dat_w[31:0] end - attribute \src "ls180.v:759.5-759.44" - process $proc$ls180.v:759$3149 + attribute \src "ls180.v:772.5-772.21" + process $proc$ls180.v:772$1926 assign { } { } - assign $1\main_sdram_choose_req_want_reads[0:0] 1'0 + assign $1\sdram_en0[0:0] 1'0 sync always sync init - update \main_sdram_choose_req_want_reads $1\main_sdram_choose_req_want_reads[0:0] + update \sdram_en0 $1\sdram_en0[0:0] end - attribute \src "ls180.v:760.5-760.45" - process $proc$ls180.v:760$3150 + attribute \src "ls180.v:774.11-774.29" + process $proc$ls180.v:774$1927 assign { } { } - assign $1\main_sdram_choose_req_want_writes[0:0] 1'0 + assign $1\sdram_time0[4:0] 5'00000 sync always sync init - update \main_sdram_choose_req_want_writes $1\main_sdram_choose_req_want_writes[0:0] + update \sdram_time0 $1\sdram_time0[4:0] end - attribute \src "ls180.v:762.5-762.48" - process $proc$ls180.v:762$3151 + attribute \src "ls180.v:775.5-775.21" + process $proc$ls180.v:775$1928 assign { } { } - assign $1\main_sdram_choose_req_want_activates[0:0] 1'0 + assign $1\sdram_en1[0:0] 1'0 sync always sync init - update \main_sdram_choose_req_want_activates $1\main_sdram_choose_req_want_activates[0:0] + update \sdram_en1 $1\sdram_en1[0:0] end - attribute \src "ls180.v:764.5-764.43" - process $proc$ls180.v:764$3152 + attribute \src "ls180.v:777.11-777.29" + process $proc$ls180.v:777$1929 assign { } { } - assign $1\main_sdram_choose_req_cmd_ready[0:0] 1'0 + assign $1\sdram_time1[3:0] 4'0000 sync always sync init - update \main_sdram_choose_req_cmd_ready $1\main_sdram_choose_req_cmd_ready[0:0] + update \sdram_time1 $1\sdram_time1[3:0] end - attribute \src "ls180.v:767.5-767.49" - process $proc$ls180.v:767$3153 + attribute \src "ls180.v:79.11-79.51" + process $proc$ls180.v:79$1632 assign { } { } - assign $1\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 + assign $1\libresocsim_libresoc_xics_icp_sel[3:0] 4'0000 sync always sync init - update \main_sdram_choose_req_cmd_payload_cas $1\main_sdram_choose_req_cmd_payload_cas[0:0] + update \libresocsim_libresoc_xics_icp_sel $1\libresocsim_libresoc_xics_icp_sel[3:0] end - attribute \src "ls180.v:768.5-768.49" - process $proc$ls180.v:768$3154 + attribute \src "ls180.v:792.12-792.32" + process $proc$ls180.v:792$1930 assign { } { } - assign $1\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 + assign $1\wb_sdram_adr[29:0] 30'000000000000000000000000000000 sync always sync init - update \main_sdram_choose_req_cmd_payload_ras $1\main_sdram_choose_req_cmd_payload_ras[0:0] + update \wb_sdram_adr $1\wb_sdram_adr[29:0] end - attribute \src "ls180.v:769.5-769.48" - process $proc$ls180.v:769$3155 + attribute \src "ls180.v:793.12-793.34" + process $proc$ls180.v:793$1931 assign { } { } - assign $1\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 + assign $1\wb_sdram_dat_w[31:0] 0 sync always sync init - update \main_sdram_choose_req_cmd_payload_we $1\main_sdram_choose_req_cmd_payload_we[0:0] + update \wb_sdram_dat_w $1\wb_sdram_dat_w[31:0] end - attribute \src "ls180.v:773.11-773.46" - process $proc$ls180.v:773$3156 + attribute \src "ls180.v:795.11-795.30" + process $proc$ls180.v:795$1932 assign { } { } - assign $1\main_sdram_choose_req_valids[3:0] 4'0000 + assign $1\wb_sdram_sel[3:0] 4'0000 sync always sync init - update \main_sdram_choose_req_valids $1\main_sdram_choose_req_valids[3:0] + update \wb_sdram_sel $1\wb_sdram_sel[3:0] end - attribute \src "ls180.v:775.11-775.45" - process $proc$ls180.v:775$3157 + attribute \src "ls180.v:796.5-796.24" + process $proc$ls180.v:796$1933 assign { } { } - assign $1\main_sdram_choose_req_grant[1:0] 2'00 + assign $1\wb_sdram_cyc[0:0] 1'0 sync always sync init - update \main_sdram_choose_req_grant $1\main_sdram_choose_req_grant[1:0] + update \wb_sdram_cyc $1\wb_sdram_cyc[0:0] end - attribute \src "ls180.v:777.12-777.36" - process $proc$ls180.v:777$3158 + attribute \src "ls180.v:797.5-797.24" + process $proc$ls180.v:797$1934 assign { } { } - assign $0\main_sdram_nop_a[12:0] 13'0000000000000 + assign $1\wb_sdram_stb[0:0] 1'0 sync always - update \main_sdram_nop_a $0\main_sdram_nop_a[12:0] sync init + update \wb_sdram_stb $1\wb_sdram_stb[0:0] end - attribute \src "ls180.v:778.11-778.35" - process $proc$ls180.v:778$3159 + attribute \src "ls180.v:798.5-798.24" + process $proc$ls180.v:798$1935 assign { } { } - assign $0\main_sdram_nop_ba[1:0] 2'00 + assign $1\wb_sdram_ack[0:0] 1'0 sync always - update \main_sdram_nop_ba $0\main_sdram_nop_ba[1:0] sync init + update \wb_sdram_ack $1\wb_sdram_ack[0:0] end - attribute \src "ls180.v:779.11-779.40" - process $proc$ls180.v:779$3160 + attribute \src "ls180.v:799.5-799.23" + process $proc$ls180.v:799$1936 assign { } { } - assign $1\main_sdram_steerer_sel[1:0] 2'00 + assign $1\wb_sdram_we[0:0] 1'0 sync always sync init - update \main_sdram_steerer_sel $1\main_sdram_steerer_sel[1:0] + update \wb_sdram_we $1\wb_sdram_we[0:0] end - attribute \src "ls180.v:780.5-780.31" - process $proc$ls180.v:780$3161 + attribute \src "ls180.v:80.5-80.45" + process $proc$ls180.v:80$1633 assign { } { } - assign $0\main_sdram_steerer0[0:0] 1'1 + assign $1\libresocsim_libresoc_xics_icp_cyc[0:0] 1'0 sync always - update \main_sdram_steerer0 $0\main_sdram_steerer0[0:0] sync init + update \libresocsim_libresoc_xics_icp_cyc $1\libresocsim_libresoc_xics_icp_cyc[0:0] end - attribute \src "ls180.v:781.5-781.31" - process $proc$ls180.v:781$3162 + attribute \src "ls180.v:806.5-806.49" + process $proc$ls180.v:806$1937 assign { } { } - assign $0\main_sdram_steerer1[0:0] 1'1 + assign $1\socbushandler_converted_interface_ack[0:0] 1'0 sync always - update \main_sdram_steerer1 $0\main_sdram_steerer1[0:0] sync init + update \socbushandler_converted_interface_ack $1\socbushandler_converted_interface_ack[0:0] end - attribute \src "ls180.v:783.32-783.63" - process $proc$ls180.v:783$3163 + attribute \src "ls180.v:81.5-81.45" + process $proc$ls180.v:81$1634 assign { } { } - assign $0\main_sdram_trrdcon_ready[0:0] 1'1 + assign $1\libresocsim_libresoc_xics_icp_stb[0:0] 1'0 sync always - update \main_sdram_trrdcon_ready $0\main_sdram_trrdcon_ready[0:0] sync init + update \libresocsim_libresoc_xics_icp_stb $1\libresocsim_libresoc_xics_icp_stb[0:0] end - attribute \src "ls180.v:785.32-785.63" - process $proc$ls180.v:785$3164 + attribute \src "ls180.v:810.5-810.49" + process $proc$ls180.v:810$1938 assign { } { } - assign $0\main_sdram_tfawcon_ready[0:0] 1'1 + assign $0\socbushandler_converted_interface_err[0:0] 1'0 sync always - update \main_sdram_tfawcon_ready $0\main_sdram_tfawcon_ready[0:0] + update \socbushandler_converted_interface_err $0\socbushandler_converted_interface_err[0:0] sync init end - attribute \src "ls180.v:787.32-787.63" - process $proc$ls180.v:787$3165 + attribute \src "ls180.v:811.5-811.30" + process $proc$ls180.v:811$1939 assign { } { } - assign $1\main_sdram_tccdcon_ready[0:0] 1'0 + assign $1\socbushandler_skip[0:0] 1'0 sync always sync init - update \main_sdram_tccdcon_ready $1\main_sdram_tccdcon_ready[0:0] + update \socbushandler_skip $1\socbushandler_skip[0:0] end - attribute \src "ls180.v:788.5-788.36" - process $proc$ls180.v:788$3166 + attribute \src "ls180.v:812.5-812.33" + process $proc$ls180.v:812$1940 assign { } { } - assign $1\main_sdram_tccdcon_count[0:0] 1'0 + assign $1\socbushandler_counter[0:0] 1'0 sync always sync init - update \main_sdram_tccdcon_count $1\main_sdram_tccdcon_count[0:0] + update \socbushandler_counter $1\socbushandler_counter[0:0] end - attribute \src "ls180.v:790.32-790.63" - process $proc$ls180.v:790$3167 + attribute \src "ls180.v:814.12-814.39" + process $proc$ls180.v:814$1941 assign { } { } - assign $1\main_sdram_twtrcon_ready[0:0] 1'0 + assign $1\socbushandler_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \main_sdram_twtrcon_ready $1\main_sdram_twtrcon_ready[0:0] + update \socbushandler_dat_r $1\socbushandler_dat_r[63:0] end - attribute \src "ls180.v:791.11-791.42" - process $proc$ls180.v:791$3168 + attribute \src "ls180.v:815.12-815.35" + process $proc$ls180.v:815$1942 assign { } { } - assign $1\main_sdram_twtrcon_count[2:0] 3'000 + assign $1\litedram_wb_adr[29:0] 30'000000000000000000000000000000 sync always sync init - update \main_sdram_twtrcon_count $1\main_sdram_twtrcon_count[2:0] + update \litedram_wb_adr $1\litedram_wb_adr[29:0] end - attribute \src "ls180.v:794.5-794.26" - process $proc$ls180.v:794$3169 + attribute \src "ls180.v:816.12-816.37" + process $proc$ls180.v:816$1943 assign { } { } - assign $1\main_sdram_en0[0:0] 1'0 + assign $1\litedram_wb_dat_w[15:0] 16'0000000000000000 sync always sync init - update \main_sdram_en0 $1\main_sdram_en0[0:0] + update \litedram_wb_dat_w $1\litedram_wb_dat_w[15:0] end - attribute \src "ls180.v:796.11-796.34" - process $proc$ls180.v:796$3170 + attribute \src "ls180.v:818.11-818.33" + process $proc$ls180.v:818$1944 assign { } { } - assign $1\main_sdram_time0[4:0] 5'00000 + assign $1\litedram_wb_sel[1:0] 2'00 sync always sync init - update \main_sdram_time0 $1\main_sdram_time0[4:0] + update \litedram_wb_sel $1\litedram_wb_sel[1:0] end - attribute \src "ls180.v:797.5-797.26" - process $proc$ls180.v:797$3171 + attribute \src "ls180.v:819.5-819.27" + process $proc$ls180.v:819$1945 assign { } { } - assign $1\main_sdram_en1[0:0] 1'0 + assign $1\litedram_wb_cyc[0:0] 1'0 sync always sync init - update \main_sdram_en1 $1\main_sdram_en1[0:0] + update \litedram_wb_cyc $1\litedram_wb_cyc[0:0] end - attribute \src "ls180.v:799.11-799.34" - process $proc$ls180.v:799$3172 + attribute \src "ls180.v:820.5-820.27" + process $proc$ls180.v:820$1946 assign { } { } - assign $1\main_sdram_time1[3:0] 4'0000 + assign $1\litedram_wb_stb[0:0] 1'0 sync always sync init - update \main_sdram_time1 $1\main_sdram_time1[3:0] + update \litedram_wb_stb $1\litedram_wb_stb[0:0] end - attribute \src "ls180.v:814.12-814.37" - process $proc$ls180.v:814$3173 + attribute \src "ls180.v:822.5-822.26" + process $proc$ls180.v:822$1947 assign { } { } - assign $1\main_wb_sdram_adr[29:0] 30'000000000000000000000000000000 + assign $1\litedram_wb_we[0:0] 1'0 sync always sync init - update \main_wb_sdram_adr $1\main_wb_sdram_adr[29:0] + update \litedram_wb_we $1\litedram_wb_we[0:0] end - attribute \src "ls180.v:815.12-815.39" - process $proc$ls180.v:815$3174 + attribute \src "ls180.v:823.5-823.26" + process $proc$ls180.v:823$1948 assign { } { } - assign $1\main_wb_sdram_dat_w[31:0] 0 + assign $1\converter_skip[0:0] 1'0 sync always sync init - update \main_wb_sdram_dat_w $1\main_wb_sdram_dat_w[31:0] + update \converter_skip $1\converter_skip[0:0] end - attribute \src "ls180.v:817.11-817.35" - process $proc$ls180.v:817$3175 + attribute \src "ls180.v:824.5-824.29" + process $proc$ls180.v:824$1949 assign { } { } - assign $1\main_wb_sdram_sel[3:0] 4'0000 + assign $1\converter_counter[0:0] 1'0 sync always sync init - update \main_wb_sdram_sel $1\main_wb_sdram_sel[3:0] + update \converter_counter $1\converter_counter[0:0] end - attribute \src "ls180.v:818.5-818.29" - process $proc$ls180.v:818$3176 + attribute \src "ls180.v:826.12-826.35" + process $proc$ls180.v:826$1950 assign { } { } - assign $1\main_wb_sdram_cyc[0:0] 1'0 + assign $1\converter_dat_r[31:0] 0 sync always sync init - update \main_wb_sdram_cyc $1\main_wb_sdram_cyc[0:0] + update \converter_dat_r $1\converter_dat_r[31:0] end - attribute \src "ls180.v:819.5-819.29" - process $proc$ls180.v:819$3177 + attribute \src "ls180.v:827.5-827.24" + process $proc$ls180.v:827$1951 assign { } { } - assign $1\main_wb_sdram_stb[0:0] 1'0 + assign $1\cmd_consumed[0:0] 1'0 sync always sync init - update \main_wb_sdram_stb $1\main_wb_sdram_stb[0:0] + update \cmd_consumed $1\cmd_consumed[0:0] end - attribute \src "ls180.v:820.5-820.29" - process $proc$ls180.v:820$3178 + attribute \src "ls180.v:828.5-828.26" + process $proc$ls180.v:828$1952 assign { } { } - assign $1\main_wb_sdram_ack[0:0] 1'0 + assign $1\wdata_consumed[0:0] 1'0 sync always sync init - update \main_wb_sdram_ack $1\main_wb_sdram_ack[0:0] + update \wdata_consumed $1\wdata_consumed[0:0] end - attribute \src "ls180.v:821.5-821.28" - process $proc$ls180.v:821$3179 + attribute \src "ls180.v:83.5-83.44" + process $proc$ls180.v:83$1635 assign { } { } - assign $1\main_wb_sdram_we[0:0] 1'0 + assign $1\libresocsim_libresoc_xics_icp_we[0:0] 1'0 sync always sync init - update \main_wb_sdram_we $1\main_wb_sdram_we[0:0] + update \libresocsim_libresoc_xics_icp_we $1\libresocsim_libresoc_xics_icp_we[0:0] end - attribute \src "ls180.v:828.5-828.54" - process $proc$ls180.v:828$3180 + attribute \src "ls180.v:832.12-832.42" + process $proc$ls180.v:832$1953 assign { } { } - assign $1\main_socbushandler_converted_interface_ack[0:0] 1'0 + assign $1\uart_phy_storage[31:0] 9895604 sync always sync init - update \main_socbushandler_converted_interface_ack $1\main_socbushandler_converted_interface_ack[0:0] + update \uart_phy_storage $1\uart_phy_storage[31:0] end - attribute \src "ls180.v:832.5-832.54" - process $proc$ls180.v:832$3181 + attribute \src "ls180.v:833.5-833.23" + process $proc$ls180.v:833$1954 assign { } { } - assign $0\main_socbushandler_converted_interface_err[0:0] 1'0 + assign $1\uart_phy_re[0:0] 1'0 sync always - update \main_socbushandler_converted_interface_err $0\main_socbushandler_converted_interface_err[0:0] sync init + update \uart_phy_re $1\uart_phy_re[0:0] end - attribute \src "ls180.v:833.5-833.35" - process $proc$ls180.v:833$3182 + attribute \src "ls180.v:835.5-835.31" + process $proc$ls180.v:835$1955 assign { } { } - assign $1\main_socbushandler_skip[0:0] 1'0 + assign $1\uart_phy_sink_ready[0:0] 1'0 sync always sync init - update \main_socbushandler_skip $1\main_socbushandler_skip[0:0] + update \uart_phy_sink_ready $1\uart_phy_sink_ready[0:0] end - attribute \src "ls180.v:834.5-834.38" - process $proc$ls180.v:834$3183 + attribute \src "ls180.v:839.5-839.34" + process $proc$ls180.v:839$1956 assign { } { } - assign $1\main_socbushandler_counter[0:0] 1'0 + assign $1\uart_phy_uart_clk_txen[0:0] 1'0 sync always sync init - update \main_socbushandler_counter $1\main_socbushandler_counter[0:0] + update \uart_phy_uart_clk_txen $1\uart_phy_uart_clk_txen[0:0] end - attribute \src "ls180.v:836.12-836.44" - process $proc$ls180.v:836$3184 + attribute \src "ls180.v:840.12-840.49" + process $proc$ls180.v:840$1957 assign { } { } - assign $1\main_socbushandler_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\uart_phy_phase_accumulator_tx[31:0] 0 sync always sync init - update \main_socbushandler_dat_r $1\main_socbushandler_dat_r[63:0] + update \uart_phy_phase_accumulator_tx $1\uart_phy_phase_accumulator_tx[31:0] end - attribute \src "ls180.v:837.12-837.40" - process $proc$ls180.v:837$3185 + attribute \src "ls180.v:841.11-841.33" + process $proc$ls180.v:841$1958 assign { } { } - assign $1\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 + assign $1\uart_phy_tx_reg[7:0] 8'00000000 sync always sync init - update \main_litedram_wb_adr $1\main_litedram_wb_adr[29:0] + update \uart_phy_tx_reg $1\uart_phy_tx_reg[7:0] end - attribute \src "ls180.v:838.12-838.42" - process $proc$ls180.v:838$3186 + attribute \src "ls180.v:842.11-842.38" + process $proc$ls180.v:842$1959 assign { } { } - assign $1\main_litedram_wb_dat_w[15:0] 16'0000000000000000 + assign $1\uart_phy_tx_bitcount[3:0] 4'0000 sync always sync init - update \main_litedram_wb_dat_w $1\main_litedram_wb_dat_w[15:0] + update \uart_phy_tx_bitcount $1\uart_phy_tx_bitcount[3:0] end - attribute \src "ls180.v:840.11-840.38" - process $proc$ls180.v:840$3187 + attribute \src "ls180.v:843.5-843.28" + process $proc$ls180.v:843$1960 assign { } { } - assign $1\main_litedram_wb_sel[1:0] 2'00 + assign $1\uart_phy_tx_busy[0:0] 1'0 sync always sync init - update \main_litedram_wb_sel $1\main_litedram_wb_sel[1:0] + update \uart_phy_tx_busy $1\uart_phy_tx_busy[0:0] end - attribute \src "ls180.v:841.5-841.32" - process $proc$ls180.v:841$3188 + attribute \src "ls180.v:844.5-844.33" + process $proc$ls180.v:844$1961 assign { } { } - assign $1\main_litedram_wb_cyc[0:0] 1'0 + assign $1\uart_phy_source_valid[0:0] 1'0 sync always sync init - update \main_litedram_wb_cyc $1\main_litedram_wb_cyc[0:0] + update \uart_phy_source_valid $1\uart_phy_source_valid[0:0] end - attribute \src "ls180.v:842.5-842.32" - process $proc$ls180.v:842$3189 + attribute \src "ls180.v:846.5-846.33" + process $proc$ls180.v:846$1962 assign { } { } - assign $1\main_litedram_wb_stb[0:0] 1'0 + assign $0\uart_phy_source_first[0:0] 1'0 sync always + update \uart_phy_source_first $0\uart_phy_source_first[0:0] sync init - update \main_litedram_wb_stb $1\main_litedram_wb_stb[0:0] end - attribute \src "ls180.v:844.5-844.31" - process $proc$ls180.v:844$3190 + attribute \src "ls180.v:847.5-847.32" + process $proc$ls180.v:847$1963 assign { } { } - assign $1\main_litedram_wb_we[0:0] 1'0 + assign $0\uart_phy_source_last[0:0] 1'0 sync always + update \uart_phy_source_last $0\uart_phy_source_last[0:0] sync init - update \main_litedram_wb_we $1\main_litedram_wb_we[0:0] end - attribute \src "ls180.v:845.5-845.31" - process $proc$ls180.v:845$3191 + attribute \src "ls180.v:848.11-848.46" + process $proc$ls180.v:848$1964 assign { } { } - assign $1\main_converter_skip[0:0] 1'0 + assign $1\uart_phy_source_payload_data[7:0] 8'00000000 sync always sync init - update \main_converter_skip $1\main_converter_skip[0:0] + update \uart_phy_source_payload_data $1\uart_phy_source_payload_data[7:0] end - attribute \src "ls180.v:846.5-846.34" - process $proc$ls180.v:846$3192 + attribute \src "ls180.v:849.5-849.34" + process $proc$ls180.v:849$1965 assign { } { } - assign $1\main_converter_counter[0:0] 1'0 + assign $1\uart_phy_uart_clk_rxen[0:0] 1'0 sync always sync init - update \main_converter_counter $1\main_converter_counter[0:0] + update \uart_phy_uart_clk_rxen $1\uart_phy_uart_clk_rxen[0:0] end - attribute \src "ls180.v:848.12-848.40" - process $proc$ls180.v:848$3193 + attribute \src "ls180.v:85.12-85.53" + process $proc$ls180.v:85$1636 assign { } { } - assign $1\main_converter_dat_r[31:0] 0 + assign $1\libresocsim_libresoc_xics_ics_adr[29:0] 30'000000000000000000000000000000 sync always sync init - update \main_converter_dat_r $1\main_converter_dat_r[31:0] + update \libresocsim_libresoc_xics_ics_adr $1\libresocsim_libresoc_xics_ics_adr[29:0] end - attribute \src "ls180.v:849.5-849.29" - process $proc$ls180.v:849$3194 + attribute \src "ls180.v:850.12-850.49" + process $proc$ls180.v:850$1966 assign { } { } - assign $1\main_cmd_consumed[0:0] 1'0 + assign $1\uart_phy_phase_accumulator_rx[31:0] 0 sync always sync init - update \main_cmd_consumed $1\main_cmd_consumed[0:0] + update \uart_phy_phase_accumulator_rx $1\uart_phy_phase_accumulator_rx[31:0] end - attribute \src "ls180.v:85.11-85.52" - process $proc$ls180.v:85$2884 + attribute \src "ls180.v:852.5-852.25" + process $proc$ls180.v:852$1967 assign { } { } - assign $0\main_libresocsim_libresoc_ibus_cti[2:0] 3'000 + assign $1\uart_phy_rx_r[0:0] 1'0 sync always - update \main_libresocsim_libresoc_ibus_cti $0\main_libresocsim_libresoc_ibus_cti[2:0] sync init + update \uart_phy_rx_r $1\uart_phy_rx_r[0:0] end - attribute \src "ls180.v:850.5-850.31" - process $proc$ls180.v:850$3195 + attribute \src "ls180.v:853.11-853.33" + process $proc$ls180.v:853$1968 assign { } { } - assign $1\main_wdata_consumed[0:0] 1'0 + assign $1\uart_phy_rx_reg[7:0] 8'00000000 sync always sync init - update \main_wdata_consumed $1\main_wdata_consumed[0:0] + update \uart_phy_rx_reg $1\uart_phy_rx_reg[7:0] end - attribute \src "ls180.v:854.12-854.47" - process $proc$ls180.v:854$3196 + attribute \src "ls180.v:854.11-854.38" + process $proc$ls180.v:854$1969 assign { } { } - assign $1\main_uart_phy_storage[31:0] 9895604 + assign $1\uart_phy_rx_bitcount[3:0] 4'0000 sync always sync init - update \main_uart_phy_storage $1\main_uart_phy_storage[31:0] + update \uart_phy_rx_bitcount $1\uart_phy_rx_bitcount[3:0] end attribute \src "ls180.v:855.5-855.28" - process $proc$ls180.v:855$3197 + process $proc$ls180.v:855$1970 assign { } { } - assign $1\main_uart_phy_re[0:0] 1'0 + assign $1\uart_phy_rx_busy[0:0] 1'0 sync always sync init - update \main_uart_phy_re $1\main_uart_phy_re[0:0] + update \uart_phy_rx_busy $1\uart_phy_rx_busy[0:0] end - attribute \src "ls180.v:857.5-857.36" - process $proc$ls180.v:857$3198 + attribute \src "ls180.v:86.12-86.55" + process $proc$ls180.v:86$1637 assign { } { } - assign $1\main_uart_phy_sink_ready[0:0] 1'0 + assign $1\libresocsim_libresoc_xics_ics_dat_w[31:0] 0 sync always sync init - update \main_uart_phy_sink_ready $1\main_uart_phy_sink_ready[0:0] + update \libresocsim_libresoc_xics_ics_dat_w $1\libresocsim_libresoc_xics_ics_dat_w[31:0] end - attribute \src "ls180.v:86.11-86.52" - process $proc$ls180.v:86$2885 + attribute \src "ls180.v:866.5-866.22" + process $proc$ls180.v:866$1971 assign { } { } - assign $0\main_libresocsim_libresoc_ibus_bte[1:0] 2'00 + assign $1\tx_pending[0:0] 1'0 sync always - update \main_libresocsim_libresoc_ibus_bte $0\main_libresocsim_libresoc_ibus_bte[1:0] sync init + update \tx_pending $1\tx_pending[0:0] end - attribute \src "ls180.v:861.5-861.39" - process $proc$ls180.v:861$3199 + attribute \src "ls180.v:868.5-868.20" + process $proc$ls180.v:868$1972 assign { } { } - assign $1\main_uart_phy_uart_clk_txen[0:0] 1'0 + assign $1\tx_clear[0:0] 1'0 sync always sync init - update \main_uart_phy_uart_clk_txen $1\main_uart_phy_uart_clk_txen[0:0] + update \tx_clear $1\tx_clear[0:0] end - attribute \src "ls180.v:862.12-862.54" - process $proc$ls180.v:862$3200 + attribute \src "ls180.v:869.5-869.26" + process $proc$ls180.v:869$1973 assign { } { } - assign $1\main_uart_phy_phase_accumulator_tx[31:0] 0 + assign $1\tx_old_trigger[0:0] 1'0 sync always sync init - update \main_uart_phy_phase_accumulator_tx $1\main_uart_phy_phase_accumulator_tx[31:0] + update \tx_old_trigger $1\tx_old_trigger[0:0] end - attribute \src "ls180.v:863.11-863.38" - process $proc$ls180.v:863$3201 + attribute \src "ls180.v:871.5-871.22" + process $proc$ls180.v:871$1974 assign { } { } - assign $1\main_uart_phy_tx_reg[7:0] 8'00000000 + assign $1\rx_pending[0:0] 1'0 sync always sync init - update \main_uart_phy_tx_reg $1\main_uart_phy_tx_reg[7:0] + update \rx_pending $1\rx_pending[0:0] end - attribute \src "ls180.v:864.11-864.43" - process $proc$ls180.v:864$3202 + attribute \src "ls180.v:873.5-873.20" + process $proc$ls180.v:873$1975 assign { } { } - assign $1\main_uart_phy_tx_bitcount[3:0] 4'0000 + assign $1\rx_clear[0:0] 1'0 sync always sync init - update \main_uart_phy_tx_bitcount $1\main_uart_phy_tx_bitcount[3:0] + update \rx_clear $1\rx_clear[0:0] end - attribute \src "ls180.v:865.5-865.33" - process $proc$ls180.v:865$3203 + attribute \src "ls180.v:874.5-874.26" + process $proc$ls180.v:874$1976 assign { } { } - assign $1\main_uart_phy_tx_busy[0:0] 1'0 + assign $1\rx_old_trigger[0:0] 1'0 sync always sync init - update \main_uart_phy_tx_busy $1\main_uart_phy_tx_busy[0:0] + update \rx_old_trigger $1\rx_old_trigger[0:0] end - attribute \src "ls180.v:866.5-866.38" - process $proc$ls180.v:866$3204 + attribute \src "ls180.v:878.11-878.39" + process $proc$ls180.v:878$1977 assign { } { } - assign $1\main_uart_phy_source_valid[0:0] 1'0 + assign $1\eventmanager_status_w[1:0] 2'00 sync always sync init - update \main_uart_phy_source_valid $1\main_uart_phy_source_valid[0:0] + update \eventmanager_status_w $1\eventmanager_status_w[1:0] end - attribute \src "ls180.v:868.5-868.38" - process $proc$ls180.v:868$3205 + attribute \src "ls180.v:88.11-88.51" + process $proc$ls180.v:88$1638 assign { } { } - assign $0\main_uart_phy_source_first[0:0] 1'0 + assign $1\libresocsim_libresoc_xics_ics_sel[3:0] 4'0000 sync always - update \main_uart_phy_source_first $0\main_uart_phy_source_first[0:0] sync init + update \libresocsim_libresoc_xics_ics_sel $1\libresocsim_libresoc_xics_ics_sel[3:0] end - attribute \src "ls180.v:869.5-869.37" - process $proc$ls180.v:869$3206 + attribute \src "ls180.v:882.11-882.40" + process $proc$ls180.v:882$1978 assign { } { } - assign $0\main_uart_phy_source_last[0:0] 1'0 + assign $1\eventmanager_pending_w[1:0] 2'00 sync always - update \main_uart_phy_source_last $0\main_uart_phy_source_last[0:0] sync init + update \eventmanager_pending_w $1\eventmanager_pending_w[1:0] end - attribute \src "ls180.v:870.11-870.51" - process $proc$ls180.v:870$3207 + attribute \src "ls180.v:883.11-883.38" + process $proc$ls180.v:883$1979 assign { } { } - assign $1\main_uart_phy_source_payload_data[7:0] 8'00000000 + assign $1\eventmanager_storage[1:0] 2'00 sync always sync init - update \main_uart_phy_source_payload_data $1\main_uart_phy_source_payload_data[7:0] + update \eventmanager_storage $1\eventmanager_storage[1:0] end - attribute \src "ls180.v:871.5-871.39" - process $proc$ls180.v:871$3208 + attribute \src "ls180.v:884.5-884.27" + process $proc$ls180.v:884$1980 assign { } { } - assign $1\main_uart_phy_uart_clk_rxen[0:0] 1'0 + assign $1\eventmanager_re[0:0] 1'0 sync always sync init - update \main_uart_phy_uart_clk_rxen $1\main_uart_phy_uart_clk_rxen[0:0] + update \eventmanager_re $1\eventmanager_re[0:0] end - attribute \src "ls180.v:872.12-872.54" - process $proc$ls180.v:872$3209 + attribute \src "ls180.v:89.5-89.45" + process $proc$ls180.v:89$1639 assign { } { } - assign $1\main_uart_phy_phase_accumulator_rx[31:0] 0 + assign $1\libresocsim_libresoc_xics_ics_cyc[0:0] 1'0 sync always sync init - update \main_uart_phy_phase_accumulator_rx $1\main_uart_phy_phase_accumulator_rx[31:0] + update \libresocsim_libresoc_xics_ics_cyc $1\libresocsim_libresoc_xics_ics_cyc[0:0] end - attribute \src "ls180.v:874.5-874.30" - process $proc$ls180.v:874$3210 + attribute \src "ls180.v:90.5-90.45" + process $proc$ls180.v:90$1640 assign { } { } - assign $1\main_uart_phy_rx_r[0:0] 1'0 + assign $1\libresocsim_libresoc_xics_ics_stb[0:0] 1'0 sync always sync init - update \main_uart_phy_rx_r $1\main_uart_phy_rx_r[0:0] + update \libresocsim_libresoc_xics_ics_stb $1\libresocsim_libresoc_xics_ics_stb[0:0] end - attribute \src "ls180.v:875.11-875.38" - process $proc$ls180.v:875$3211 + attribute \src "ls180.v:901.5-901.30" + process $proc$ls180.v:901$1981 assign { } { } - assign $1\main_uart_phy_rx_reg[7:0] 8'00000000 + assign $0\tx_fifo_sink_first[0:0] 1'0 sync always + update \tx_fifo_sink_first $0\tx_fifo_sink_first[0:0] sync init - update \main_uart_phy_rx_reg $1\main_uart_phy_rx_reg[7:0] end - attribute \src "ls180.v:876.11-876.43" - process $proc$ls180.v:876$3212 + attribute \src "ls180.v:902.5-902.29" + process $proc$ls180.v:902$1982 assign { } { } - assign $1\main_uart_phy_rx_bitcount[3:0] 4'0000 + assign $0\tx_fifo_sink_last[0:0] 1'0 sync always + update \tx_fifo_sink_last $0\tx_fifo_sink_last[0:0] sync init - update \main_uart_phy_rx_bitcount $1\main_uart_phy_rx_bitcount[3:0] end - attribute \src "ls180.v:877.5-877.33" - process $proc$ls180.v:877$3213 + attribute \src "ls180.v:910.5-910.28" + process $proc$ls180.v:910$1983 assign { } { } - assign $1\main_uart_phy_rx_busy[0:0] 1'0 + assign $1\tx_fifo_readable[0:0] 1'0 sync always sync init - update \main_uart_phy_rx_busy $1\main_uart_phy_rx_busy[0:0] + update \tx_fifo_readable $1\tx_fifo_readable[0:0] end - attribute \src "ls180.v:88.12-88.58" - process $proc$ls180.v:88$2886 + attribute \src "ls180.v:917.11-917.32" + process $proc$ls180.v:917$1984 assign { } { } - assign $1\main_libresocsim_libresoc_xics_icp_adr[29:0] 30'000000000000000000000000000000 + assign $1\tx_fifo_level0[4:0] 5'00000 sync always sync init - update \main_libresocsim_libresoc_xics_icp_adr $1\main_libresocsim_libresoc_xics_icp_adr[29:0] + update \tx_fifo_level0 $1\tx_fifo_level0[4:0] end - attribute \src "ls180.v:888.5-888.32" - process $proc$ls180.v:888$3214 + attribute \src "ls180.v:918.5-918.27" + process $proc$ls180.v:918$1985 assign { } { } - assign $1\main_uart_tx_pending[0:0] 1'0 + assign $0\tx_fifo_replace[0:0] 1'0 sync always + update \tx_fifo_replace $0\tx_fifo_replace[0:0] sync init - update \main_uart_tx_pending $1\main_uart_tx_pending[0:0] end - attribute \src "ls180.v:89.12-89.60" - process $proc$ls180.v:89$2887 + attribute \src "ls180.v:919.11-919.33" + process $proc$ls180.v:919$1986 assign { } { } - assign $1\main_libresocsim_libresoc_xics_icp_dat_w[31:0] 0 + assign $1\tx_fifo_produce[3:0] 4'0000 sync always sync init - update \main_libresocsim_libresoc_xics_icp_dat_w $1\main_libresocsim_libresoc_xics_icp_dat_w[31:0] + update \tx_fifo_produce $1\tx_fifo_produce[3:0] end - attribute \src "ls180.v:890.5-890.30" - process $proc$ls180.v:890$3215 + attribute \src "ls180.v:92.5-92.44" + process $proc$ls180.v:92$1641 assign { } { } - assign $1\main_uart_tx_clear[0:0] 1'0 + assign $1\libresocsim_libresoc_xics_ics_we[0:0] 1'0 sync always sync init - update \main_uart_tx_clear $1\main_uart_tx_clear[0:0] + update \libresocsim_libresoc_xics_ics_we $1\libresocsim_libresoc_xics_ics_we[0:0] end - attribute \src "ls180.v:891.5-891.36" - process $proc$ls180.v:891$3216 + attribute \src "ls180.v:920.11-920.33" + process $proc$ls180.v:920$1987 assign { } { } - assign $1\main_uart_tx_old_trigger[0:0] 1'0 + assign $1\tx_fifo_consume[3:0] 4'0000 sync always sync init - update \main_uart_tx_old_trigger $1\main_uart_tx_old_trigger[0:0] + update \tx_fifo_consume $1\tx_fifo_consume[3:0] end - attribute \src "ls180.v:893.5-893.32" - process $proc$ls180.v:893$3217 + attribute \src "ls180.v:921.11-921.36" + process $proc$ls180.v:921$1988 assign { } { } - assign $1\main_uart_rx_pending[0:0] 1'0 + assign $1\tx_fifo_wrport_adr[3:0] 4'0000 sync always sync init - update \main_uart_rx_pending $1\main_uart_rx_pending[0:0] + update \tx_fifo_wrport_adr $1\tx_fifo_wrport_adr[3:0] end - attribute \src "ls180.v:895.5-895.30" - process $proc$ls180.v:895$3218 + attribute \src "ls180.v:947.5-947.28" + process $proc$ls180.v:947$1989 assign { } { } - assign $1\main_uart_rx_clear[0:0] 1'0 + assign $1\rx_fifo_readable[0:0] 1'0 sync always sync init - update \main_uart_rx_clear $1\main_uart_rx_clear[0:0] + update \rx_fifo_readable $1\rx_fifo_readable[0:0] end - attribute \src "ls180.v:896.5-896.36" - process $proc$ls180.v:896$3219 + attribute \src "ls180.v:954.11-954.32" + process $proc$ls180.v:954$1990 assign { } { } - assign $1\main_uart_rx_old_trigger[0:0] 1'0 + assign $1\rx_fifo_level0[4:0] 5'00000 sync always sync init - update \main_uart_rx_old_trigger $1\main_uart_rx_old_trigger[0:0] + update \rx_fifo_level0 $1\rx_fifo_level0[4:0] end - attribute \src "ls180.v:900.11-900.49" - process $proc$ls180.v:900$3220 + attribute \src "ls180.v:955.5-955.27" + process $proc$ls180.v:955$1991 assign { } { } - assign $1\main_uart_eventmanager_status_w[1:0] 2'00 + assign $0\rx_fifo_replace[0:0] 1'0 sync always + update \rx_fifo_replace $0\rx_fifo_replace[0:0] sync init - update \main_uart_eventmanager_status_w $1\main_uart_eventmanager_status_w[1:0] end - attribute \src "ls180.v:904.11-904.50" - process $proc$ls180.v:904$3221 + attribute \src "ls180.v:956.11-956.33" + process $proc$ls180.v:956$1992 assign { } { } - assign $1\main_uart_eventmanager_pending_w[1:0] 2'00 + assign $1\rx_fifo_produce[3:0] 4'0000 sync always sync init - update \main_uart_eventmanager_pending_w $1\main_uart_eventmanager_pending_w[1:0] + update \rx_fifo_produce $1\rx_fifo_produce[3:0] end - attribute \src "ls180.v:905.11-905.48" - process $proc$ls180.v:905$3222 + attribute \src "ls180.v:957.11-957.33" + process $proc$ls180.v:957$1993 assign { } { } - assign $1\main_uart_eventmanager_storage[1:0] 2'00 + assign $1\rx_fifo_consume[3:0] 4'0000 sync always sync init - update \main_uart_eventmanager_storage $1\main_uart_eventmanager_storage[1:0] + update \rx_fifo_consume $1\rx_fifo_consume[3:0] end - attribute \src "ls180.v:906.5-906.37" - process $proc$ls180.v:906$3223 + attribute \src "ls180.v:958.11-958.36" + process $proc$ls180.v:958$1994 assign { } { } - assign $1\main_uart_eventmanager_re[0:0] 1'0 + assign $1\rx_fifo_wrport_adr[3:0] 4'0000 sync always sync init - update \main_uart_eventmanager_re $1\main_uart_eventmanager_re[0:0] + update \rx_fifo_wrport_adr $1\rx_fifo_wrport_adr[3:0] end - attribute \src "ls180.v:91.11-91.56" - process $proc$ls180.v:91$2888 + attribute \src "ls180.v:973.5-973.17" + process $proc$ls180.v:973$1995 assign { } { } - assign $1\main_libresocsim_libresoc_xics_icp_sel[3:0] 4'0000 + assign $0\reset[0:0] 1'0 sync always + update \reset $0\reset[0:0] sync init - update \main_libresocsim_libresoc_xics_icp_sel $1\main_libresocsim_libresoc_xics_icp_sel[3:0] end - attribute \src "ls180.v:92.5-92.50" - process $proc$ls180.v:92$2889 + attribute \src "ls180.v:974.11-974.34" + process $proc$ls180.v:974$1996 assign { } { } - assign $1\main_libresocsim_libresoc_xics_icp_cyc[0:0] 1'0 + assign $1\gpio0_oe_storage[7:0] 8'00000000 sync always sync init - update \main_libresocsim_libresoc_xics_icp_cyc $1\main_libresocsim_libresoc_xics_icp_cyc[0:0] + update \gpio0_oe_storage $1\gpio0_oe_storage[7:0] end - attribute \src "ls180.v:923.5-923.40" - process $proc$ls180.v:923$3224 + attribute \src "ls180.v:975.5-975.23" + process $proc$ls180.v:975$1997 assign { } { } - assign $0\main_uart_tx_fifo_sink_first[0:0] 1'0 + assign $1\gpio0_oe_re[0:0] 1'0 sync always - update \main_uart_tx_fifo_sink_first $0\main_uart_tx_fifo_sink_first[0:0] sync init + update \gpio0_oe_re $1\gpio0_oe_re[0:0] end - attribute \src "ls180.v:924.5-924.39" - process $proc$ls180.v:924$3225 + attribute \src "ls180.v:976.11-976.30" + process $proc$ls180.v:976$1998 assign { } { } - assign $0\main_uart_tx_fifo_sink_last[0:0] 1'0 + assign $1\gpio0_status[7:0] 8'00000000 sync always - update \main_uart_tx_fifo_sink_last $0\main_uart_tx_fifo_sink_last[0:0] sync init + update \gpio0_status $1\gpio0_status[7:0] end - attribute \src "ls180.v:93.5-93.50" - process $proc$ls180.v:93$2890 + attribute \src "ls180.v:978.11-978.35" + process $proc$ls180.v:978$1999 assign { } { } - assign $1\main_libresocsim_libresoc_xics_icp_stb[0:0] 1'0 + assign $1\gpio0_out_storage[7:0] 8'00000000 sync always sync init - update \main_libresocsim_libresoc_xics_icp_stb $1\main_libresocsim_libresoc_xics_icp_stb[0:0] + update \gpio0_out_storage $1\gpio0_out_storage[7:0] end - attribute \src "ls180.v:932.5-932.38" - process $proc$ls180.v:932$3226 + attribute \src "ls180.v:979.5-979.24" + process $proc$ls180.v:979$2000 assign { } { } - assign $1\main_uart_tx_fifo_readable[0:0] 1'0 + assign $1\gpio0_out_re[0:0] 1'0 sync always sync init - update \main_uart_tx_fifo_readable $1\main_uart_tx_fifo_readable[0:0] + update \gpio0_out_re $1\gpio0_out_re[0:0] end - attribute \src "ls180.v:939.11-939.42" - process $proc$ls180.v:939$3227 + attribute \src "ls180.v:980.11-980.35" + process $proc$ls180.v:980$2001 assign { } { } - assign $1\main_uart_tx_fifo_level0[4:0] 5'00000 + assign $1\gpio0_pads_gpio0i[7:0] 8'00000000 sync always sync init - update \main_uart_tx_fifo_level0 $1\main_uart_tx_fifo_level0[4:0] + update \gpio0_pads_gpio0i $1\gpio0_pads_gpio0i[7:0] end - attribute \src "ls180.v:940.5-940.37" - process $proc$ls180.v:940$3228 + attribute \src "ls180.v:981.11-981.35" + process $proc$ls180.v:981$2002 assign { } { } - assign $0\main_uart_tx_fifo_replace[0:0] 1'0 + assign $1\gpio0_pads_gpio0o[7:0] 8'00000000 sync always - update \main_uart_tx_fifo_replace $0\main_uart_tx_fifo_replace[0:0] sync init + update \gpio0_pads_gpio0o $1\gpio0_pads_gpio0o[7:0] end - attribute \src "ls180.v:941.11-941.43" - process $proc$ls180.v:941$3229 + attribute \src "ls180.v:982.11-982.36" + process $proc$ls180.v:982$2003 assign { } { } - assign $1\main_uart_tx_fifo_produce[3:0] 4'0000 + assign $1\gpio0_pads_gpio0oe[7:0] 8'00000000 sync always sync init - update \main_uart_tx_fifo_produce $1\main_uart_tx_fifo_produce[3:0] + update \gpio0_pads_gpio0oe $1\gpio0_pads_gpio0oe[7:0] end - attribute \src "ls180.v:942.11-942.43" - process $proc$ls180.v:942$3230 + attribute \src "ls180.v:983.11-983.34" + process $proc$ls180.v:983$2004 assign { } { } - assign $1\main_uart_tx_fifo_consume[3:0] 4'0000 + assign $1\gpio1_oe_storage[7:0] 8'00000000 sync always sync init - update \main_uart_tx_fifo_consume $1\main_uart_tx_fifo_consume[3:0] + update \gpio1_oe_storage $1\gpio1_oe_storage[7:0] end - attribute \src "ls180.v:943.11-943.46" - process $proc$ls180.v:943$3231 + attribute \src "ls180.v:984.5-984.23" + process $proc$ls180.v:984$2005 assign { } { } - assign $1\main_uart_tx_fifo_wrport_adr[3:0] 4'0000 + assign $1\gpio1_oe_re[0:0] 1'0 sync always sync init - update \main_uart_tx_fifo_wrport_adr $1\main_uart_tx_fifo_wrport_adr[3:0] + update \gpio1_oe_re $1\gpio1_oe_re[0:0] end - attribute \src "ls180.v:95.5-95.49" - process $proc$ls180.v:95$2891 + attribute \src "ls180.v:985.11-985.30" + process $proc$ls180.v:985$2006 assign { } { } - assign $1\main_libresocsim_libresoc_xics_icp_we[0:0] 1'0 + assign $1\gpio1_status[7:0] 8'00000000 sync always sync init - update \main_libresocsim_libresoc_xics_icp_we $1\main_libresocsim_libresoc_xics_icp_we[0:0] + update \gpio1_status $1\gpio1_status[7:0] end - attribute \src "ls180.v:969.5-969.38" - process $proc$ls180.v:969$3232 + attribute \src "ls180.v:987.11-987.35" + process $proc$ls180.v:987$2007 assign { } { } - assign $1\main_uart_rx_fifo_readable[0:0] 1'0 + assign $1\gpio1_out_storage[7:0] 8'00000000 sync always sync init - update \main_uart_rx_fifo_readable $1\main_uart_rx_fifo_readable[0:0] + update \gpio1_out_storage $1\gpio1_out_storage[7:0] end - attribute \src "ls180.v:97.12-97.58" - process $proc$ls180.v:97$2892 + attribute \src "ls180.v:988.5-988.24" + process $proc$ls180.v:988$2008 assign { } { } - assign $1\main_libresocsim_libresoc_xics_ics_adr[29:0] 30'000000000000000000000000000000 + assign $1\gpio1_out_re[0:0] 1'0 sync always sync init - update \main_libresocsim_libresoc_xics_ics_adr $1\main_libresocsim_libresoc_xics_ics_adr[29:0] + update \gpio1_out_re $1\gpio1_out_re[0:0] end - attribute \src "ls180.v:976.11-976.42" - process $proc$ls180.v:976$3233 + attribute \src "ls180.v:989.11-989.35" + process $proc$ls180.v:989$2009 assign { } { } - assign $1\main_uart_rx_fifo_level0[4:0] 5'00000 + assign $1\gpio1_pads_gpio1i[7:0] 8'00000000 sync always sync init - update \main_uart_rx_fifo_level0 $1\main_uart_rx_fifo_level0[4:0] + update \gpio1_pads_gpio1i $1\gpio1_pads_gpio1i[7:0] end - attribute \src "ls180.v:977.5-977.37" - process $proc$ls180.v:977$3234 + attribute \src "ls180.v:990.11-990.35" + process $proc$ls180.v:990$2010 assign { } { } - assign $0\main_uart_rx_fifo_replace[0:0] 1'0 + assign $1\gpio1_pads_gpio1o[7:0] 8'00000000 sync always - update \main_uart_rx_fifo_replace $0\main_uart_rx_fifo_replace[0:0] sync init + update \gpio1_pads_gpio1o $1\gpio1_pads_gpio1o[7:0] end - attribute \src "ls180.v:978.11-978.43" - process $proc$ls180.v:978$3235 + attribute \src "ls180.v:991.11-991.36" + process $proc$ls180.v:991$2011 assign { } { } - assign $1\main_uart_rx_fifo_produce[3:0] 4'0000 + assign $1\gpio1_pads_gpio1oe[7:0] 8'00000000 sync always sync init - update \main_uart_rx_fifo_produce $1\main_uart_rx_fifo_produce[3:0] + update \gpio1_pads_gpio1oe $1\gpio1_pads_gpio1oe[7:0] end - attribute \src "ls180.v:979.11-979.43" - process $proc$ls180.v:979$3236 + attribute \src "ls180.v:993.12-993.25" + process $proc$ls180.v:993$2012 assign { } { } - assign $1\main_uart_rx_fifo_consume[3:0] 4'0000 + assign $1\dummy[29:0] 30'000000000000000000000000000000 sync always sync init - update \main_uart_rx_fifo_consume $1\main_uart_rx_fifo_consume[3:0] + update \dummy $1\dummy[29:0] end - attribute \src "ls180.v:98.12-98.60" - process $proc$ls180.v:98$2893 + attribute \src "ls180.v:997.11-997.29" + process $proc$ls180.v:997$2013 assign { } { } - assign $1\main_libresocsim_libresoc_xics_ics_dat_w[31:0] 0 + assign $1\i2c_storage[2:0] 3'000 sync always sync init - update \main_libresocsim_libresoc_xics_ics_dat_w $1\main_libresocsim_libresoc_xics_ics_dat_w[31:0] + update \i2c_storage $1\i2c_storage[2:0] end - attribute \src "ls180.v:980.11-980.46" - process $proc$ls180.v:980$3237 + attribute \src "ls180.v:998.5-998.18" + process $proc$ls180.v:998$2014 assign { } { } - assign $1\main_uart_rx_fifo_wrport_adr[3:0] 4'0000 + assign $1\i2c_re[0:0] 1'0 sync always sync init - update \main_uart_rx_fifo_wrport_adr $1\main_uart_rx_fifo_wrport_adr[3:0] + update \i2c_re $1\i2c_re[0:0] end - attribute \src "ls180.v:995.5-995.27" - process $proc$ls180.v:995$3238 - assign { } { } - assign $0\main_uart_reset[0:0] 1'0 - sync always - update \main_uart_reset $0\main_uart_reset[0:0] - sync init - end - attribute \src "ls180.v:996.12-996.53" - process $proc$ls180.v:996$3239 - assign { } { } - assign $0\main_gpiotristateasic0_oe_storage[15:0] 16'0000000000000000 - sync always - update \main_gpiotristateasic0_oe_storage $0\main_gpiotristateasic0_oe_storage[15:0] - sync init - end - attribute \src "ls180.v:997.12-997.49" - process $proc$ls180.v:997$3240 - assign { } { } - assign $1\main_gpiotristateasic0_status[15:0] 16'0000000000000000 - sync always - sync init - update \main_gpiotristateasic0_status $1\main_gpiotristateasic0_status[15:0] - end - attribute \src "ls180.v:998.12-998.54" - process $proc$ls180.v:998$3241 - assign { } { } - assign $0\main_gpiotristateasic0_out_storage[15:0] 16'0000000000000000 - sync always - update \main_gpiotristateasic0_out_storage $0\main_gpiotristateasic0_out_storage[15:0] - sync init - end - connect \main_libresocsim_libresoc_reset \main_libresocsim_reset - connect \main_libresocsim_libresoc_clk_sel \sys_clksel_i - connect \sys_pll_18_o \main_libresocsim_libresoc_pll_18_o - connect \sys_pll_lck_o \main_libresocsim_libresoc_pll_lck_o - connect \main_libresocsim_libresoc_jtag_tck \jtag_tck - connect \main_libresocsim_libresoc_jtag_tms \jtag_tms - connect \main_libresocsim_libresoc_jtag_tdi \jtag_tdi - connect \jtag_tdo \main_libresocsim_libresoc_jtag_tdo - connect \main_nc \nc - connect \main_sdblock2mem_sink_sink_valid0 \main_sdcore_source_source_valid - connect \main_sdcore_source_source_ready \main_sdblock2mem_sink_sink_ready0 - connect \main_sdblock2mem_sink_sink_first \main_sdcore_source_source_first - connect \main_sdblock2mem_sink_sink_last \main_sdcore_source_source_last - connect \main_sdblock2mem_sink_sink_payload_data0 \main_sdcore_source_source_payload_data - connect \main_sdcore_sink_sink_valid \main_sdmem2block_source_source_valid0 - connect \main_sdmem2block_source_source_ready0 \main_sdcore_sink_sink_ready - connect \main_sdcore_sink_sink_first \main_sdmem2block_source_source_first0 - connect \main_sdcore_sink_sink_last \main_sdmem2block_source_source_last0 - connect \main_sdcore_sink_sink_payload_data \main_sdmem2block_source_source_payload_data0 - connect \main_libresocsim_bus_error \builder_error - connect \main_converter0_reset $not$ls180.v:2804$26_Y - connect \main_interface0_converted_interface_dat_r { \main_libresocsim_libresoc_xics_icp_dat_r \main_converter0_dat_r [63:32] } - connect \main_converter1_reset $not$ls180.v:2864$37_Y - connect \main_interface1_converted_interface_dat_r { \main_libresocsim_libresoc_xics_ics_dat_r \main_converter1_dat_r [63:32] } - connect \main_socbushandler_reset $not$ls180.v:2924$48_Y - connect \main_socbushandler_converted_interface_dat_r { \main_wb_sdram_dat_r \main_socbushandler_dat_r [63:32] } - connect \main_libresocsim_reset \main_libresocsim_reset_re - connect \main_libresocsim_bus_errors_status \main_libresocsim_bus_errors - connect \main_libresocsim_adr \main_libresocsim_ram_bus_adr [5:0] - connect \main_libresocsim_ram_bus_dat_r \main_libresocsim_dat_r - connect \main_libresocsim_dat_w \main_libresocsim_ram_bus_dat_w - connect \main_libresocsim_zero_trigger $ne$ls180.v:3000$84_Y - connect \main_libresocsim_eventmanager_status_w \main_libresocsim_zero_status - connect \main_libresocsim_eventmanager_pending_w \main_libresocsim_zero_pending - connect \main_libresocsim_irq $and$ls180.v:3009$87_Y - connect \main_libresocsim_zero_status \main_libresocsim_zero_trigger - connect \main_ram_adr \main_ram_bus_ram_bus_adr [3:0] - connect \main_ram_bus_ram_bus_dat_r \main_ram_dat_r - connect \main_ram_dat_w \main_ram_bus_ram_bus_dat_w + connect \libresocsim_libresoc_reset \libresocsim_reset + connect \libresocsim_libresoc_clk_sel \sys_clksel_i + connect \sys_pll_18_o \libresocsim_libresoc_pll_18_o + connect \sys_pll_lck_o \libresocsim_libresoc_pll_lck_o + connect \libresocsim_libresoc_jtag_tck \jtag_tck + connect \libresocsim_libresoc_jtag_tms \jtag_tms + connect \libresocsim_libresoc_jtag_tdi \jtag_tdi + connect \jtag_tdo \libresocsim_libresoc_jtag_tdo + connect \nc_1 \nc + connect \libresocsim_bus_error \libresocsim_error + connect \converter0_reset $not$ls180.v:1513$24_Y + connect \interface0_converted_interface_dat_r { \libresocsim_libresoc_xics_icp_dat_r \converter0_dat_r [63:32] } + connect \converter1_reset $not$ls180.v:1573$35_Y + connect \interface1_converted_interface_dat_r { \libresocsim_libresoc_xics_ics_dat_r \converter1_dat_r [63:32] } + connect \socbushandler_reset $not$ls180.v:1633$46_Y + connect \socbushandler_converted_interface_dat_r { \wb_sdram_dat_r \socbushandler_dat_r [63:32] } + connect \libresocsim_reset \libresocsim_reset_re + connect \libresocsim_bus_errors_status \libresocsim_bus_errors + connect \libresocsim_adr \libresocsim_ram_bus_adr [5:0] + connect \libresocsim_ram_bus_dat_r \libresocsim_dat_r + connect \libresocsim_dat_w \libresocsim_ram_bus_dat_w + connect \libresocsim_zero_trigger $ne$ls180.v:1709$82_Y + connect \libresocsim_eventmanager_status_w \libresocsim_zero_status + connect \libresocsim_eventmanager_pending_w \libresocsim_zero_pending + connect \libresocsim_irq $and$ls180.v:1718$85_Y + connect \libresocsim_zero_status \libresocsim_zero_trigger + connect \ram_adr \ram_bus_ram_bus_adr [3:0] + connect \ram_bus_ram_bus_dat_r \ram_dat_r + connect \ram_dat_w \ram_bus_ram_bus_dat_w connect \sys_clk_1 \sys_clk connect \por_clk \sys_clk - connect \sys_rst_1 \main_int_rst - connect \main_dfi_p0_address \main_sdram_master_p0_address - connect \main_dfi_p0_bank \main_sdram_master_p0_bank - connect \main_dfi_p0_cas_n \main_sdram_master_p0_cas_n - connect \main_dfi_p0_cs_n \main_sdram_master_p0_cs_n - connect \main_dfi_p0_ras_n \main_sdram_master_p0_ras_n - connect \main_dfi_p0_we_n \main_sdram_master_p0_we_n - connect \main_dfi_p0_cke \main_sdram_master_p0_cke - connect \main_dfi_p0_odt \main_sdram_master_p0_odt - connect \main_dfi_p0_reset_n \main_sdram_master_p0_reset_n - connect \main_dfi_p0_act_n \main_sdram_master_p0_act_n - connect \main_dfi_p0_wrdata \main_sdram_master_p0_wrdata - connect \main_dfi_p0_wrdata_en \main_sdram_master_p0_wrdata_en - connect \main_dfi_p0_wrdata_mask \main_sdram_master_p0_wrdata_mask - connect \main_dfi_p0_rddata_en \main_sdram_master_p0_rddata_en - connect \main_sdram_master_p0_rddata \main_dfi_p0_rddata - connect \main_sdram_master_p0_rddata_valid \main_dfi_p0_rddata_valid - connect \main_sdram_slave_p0_address \main_sdram_dfi_p0_address - connect \main_sdram_slave_p0_bank \main_sdram_dfi_p0_bank - connect \main_sdram_slave_p0_cas_n \main_sdram_dfi_p0_cas_n - connect \main_sdram_slave_p0_cs_n \main_sdram_dfi_p0_cs_n - connect \main_sdram_slave_p0_ras_n \main_sdram_dfi_p0_ras_n - connect \main_sdram_slave_p0_we_n \main_sdram_dfi_p0_we_n - connect \main_sdram_slave_p0_cke \main_sdram_dfi_p0_cke - connect \main_sdram_slave_p0_odt \main_sdram_dfi_p0_odt - connect \main_sdram_slave_p0_reset_n \main_sdram_dfi_p0_reset_n - connect \main_sdram_slave_p0_act_n \main_sdram_dfi_p0_act_n - connect \main_sdram_slave_p0_wrdata \main_sdram_dfi_p0_wrdata - connect \main_sdram_slave_p0_wrdata_en \main_sdram_dfi_p0_wrdata_en - connect \main_sdram_slave_p0_wrdata_mask \main_sdram_dfi_p0_wrdata_mask - connect \main_sdram_slave_p0_rddata_en \main_sdram_dfi_p0_rddata_en - connect \main_sdram_dfi_p0_rddata \main_sdram_slave_p0_rddata - connect \main_sdram_dfi_p0_rddata_valid \main_sdram_slave_p0_rddata_valid - connect \main_sdram_inti_p0_cke \main_sdram_cke - connect \main_sdram_inti_p0_odt \main_sdram_odt - connect \main_sdram_inti_p0_reset_n \main_sdram_reset_n - connect \main_sdram_inti_p0_address \main_sdram_address_storage - connect \main_sdram_inti_p0_bank \main_sdram_baddress_storage - connect \main_sdram_inti_p0_wrdata_en $and$ls180.v:3137$119_Y - connect \main_sdram_inti_p0_rddata_en $and$ls180.v:3138$120_Y - connect \main_sdram_inti_p0_wrdata \main_sdram_wrdata_storage - connect \main_sdram_inti_p0_wrdata_mask 2'00 - connect \main_sdram_bankmachine0_req_valid \main_sdram_interface_bank0_valid - connect \main_sdram_interface_bank0_ready \main_sdram_bankmachine0_req_ready - connect \main_sdram_bankmachine0_req_we \main_sdram_interface_bank0_we - connect \main_sdram_bankmachine0_req_addr \main_sdram_interface_bank0_addr - connect \main_sdram_interface_bank0_lock \main_sdram_bankmachine0_req_lock - connect \main_sdram_interface_bank0_wdata_ready \main_sdram_bankmachine0_req_wdata_ready - connect \main_sdram_interface_bank0_rdata_valid \main_sdram_bankmachine0_req_rdata_valid - connect \main_sdram_bankmachine1_req_valid \main_sdram_interface_bank1_valid - connect \main_sdram_interface_bank1_ready \main_sdram_bankmachine1_req_ready - connect \main_sdram_bankmachine1_req_we \main_sdram_interface_bank1_we - connect \main_sdram_bankmachine1_req_addr \main_sdram_interface_bank1_addr - connect \main_sdram_interface_bank1_lock \main_sdram_bankmachine1_req_lock - connect \main_sdram_interface_bank1_wdata_ready \main_sdram_bankmachine1_req_wdata_ready - connect \main_sdram_interface_bank1_rdata_valid \main_sdram_bankmachine1_req_rdata_valid - connect \main_sdram_bankmachine2_req_valid \main_sdram_interface_bank2_valid - connect \main_sdram_interface_bank2_ready \main_sdram_bankmachine2_req_ready - connect \main_sdram_bankmachine2_req_we \main_sdram_interface_bank2_we - connect \main_sdram_bankmachine2_req_addr \main_sdram_interface_bank2_addr - connect \main_sdram_interface_bank2_lock \main_sdram_bankmachine2_req_lock - connect \main_sdram_interface_bank2_wdata_ready \main_sdram_bankmachine2_req_wdata_ready - connect \main_sdram_interface_bank2_rdata_valid \main_sdram_bankmachine2_req_rdata_valid - connect \main_sdram_bankmachine3_req_valid \main_sdram_interface_bank3_valid - connect \main_sdram_interface_bank3_ready \main_sdram_bankmachine3_req_ready - connect \main_sdram_bankmachine3_req_we \main_sdram_interface_bank3_we - connect \main_sdram_bankmachine3_req_addr \main_sdram_interface_bank3_addr - connect \main_sdram_interface_bank3_lock \main_sdram_bankmachine3_req_lock - connect \main_sdram_interface_bank3_wdata_ready \main_sdram_bankmachine3_req_wdata_ready - connect \main_sdram_interface_bank3_rdata_valid \main_sdram_bankmachine3_req_rdata_valid - connect \main_sdram_timer_wait $not$ls180.v:3169$121_Y - connect \main_sdram_postponer_req_i \main_sdram_timer_done0 - connect \main_sdram_wants_refresh \main_sdram_postponer_req_o - connect \main_sdram_timer_done1 $eq$ls180.v:3172$122_Y - connect \main_sdram_timer_done0 \main_sdram_timer_done1 - connect \main_sdram_timer_count0 \main_sdram_timer_count1 - connect \main_sdram_sequencer_start1 $or$ls180.v:3175$124_Y - connect \main_sdram_sequencer_done0 $and$ls180.v:3176$126_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine0_req_valid - connect \main_sdram_bankmachine0_req_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine0_req_we - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine0_req_addr - connect \main_sdram_bankmachine0_cmd_buffer_sink_valid \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine0_cmd_buffer_sink_ready - connect \main_sdram_bankmachine0_cmd_buffer_sink_first \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first - connect \main_sdram_bankmachine0_cmd_buffer_sink_last \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last - connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we - connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:3218$128_Y - connect \main_sdram_bankmachine0_req_lock $or$ls180.v:3219$129_Y - connect \main_sdram_bankmachine0_row_hit $eq$ls180.v:3220$130_Y - connect \main_sdram_bankmachine0_cmd_payload_ba 2'00 - connect \main_sdram_bankmachine0_twtpcon_valid $and$ls180.v:3230$135_Y - connect \main_sdram_bankmachine0_trccon_valid $and$ls180.v:3231$137_Y - connect \main_sdram_bankmachine0_trascon_valid $and$ls180.v:3232$139_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we } - connect { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:3264$147_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:3265$148_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine0_cmd_buffer_lookahead_consume - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:3268$149_Y - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:3269$150_Y - connect \main_sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:3270$152_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine1_req_valid - connect \main_sdram_bankmachine1_req_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine1_req_we - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine1_req_addr - connect \main_sdram_bankmachine1_cmd_buffer_sink_valid \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine1_cmd_buffer_sink_ready - connect \main_sdram_bankmachine1_cmd_buffer_sink_first \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first - connect \main_sdram_bankmachine1_cmd_buffer_sink_last \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last - connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we - connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:3375$158_Y - connect \main_sdram_bankmachine1_req_lock $or$ls180.v:3376$159_Y - connect \main_sdram_bankmachine1_row_hit $eq$ls180.v:3377$160_Y - connect \main_sdram_bankmachine1_cmd_payload_ba 2'01 - connect \main_sdram_bankmachine1_twtpcon_valid $and$ls180.v:3387$165_Y - connect \main_sdram_bankmachine1_trccon_valid $and$ls180.v:3388$167_Y - connect \main_sdram_bankmachine1_trascon_valid $and$ls180.v:3389$169_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we } - connect { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:3421$177_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:3422$178_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine1_cmd_buffer_lookahead_consume - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:3425$179_Y - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:3426$180_Y - connect \main_sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:3427$182_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine2_req_valid - connect \main_sdram_bankmachine2_req_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine2_req_we - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine2_req_addr - connect \main_sdram_bankmachine2_cmd_buffer_sink_valid \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine2_cmd_buffer_sink_ready - connect \main_sdram_bankmachine2_cmd_buffer_sink_first \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first - connect \main_sdram_bankmachine2_cmd_buffer_sink_last \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last - connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we - connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:3532$188_Y - connect \main_sdram_bankmachine2_req_lock $or$ls180.v:3533$189_Y - connect \main_sdram_bankmachine2_row_hit $eq$ls180.v:3534$190_Y - connect \main_sdram_bankmachine2_cmd_payload_ba 2'10 - connect \main_sdram_bankmachine2_twtpcon_valid $and$ls180.v:3544$195_Y - connect \main_sdram_bankmachine2_trccon_valid $and$ls180.v:3545$197_Y - connect \main_sdram_bankmachine2_trascon_valid $and$ls180.v:3546$199_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we } - connect { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:3578$207_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:3579$208_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine2_cmd_buffer_lookahead_consume - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:3582$209_Y - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:3583$210_Y - connect \main_sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:3584$212_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine3_req_valid - connect \main_sdram_bankmachine3_req_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine3_req_we - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine3_req_addr - connect \main_sdram_bankmachine3_cmd_buffer_sink_valid \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine3_cmd_buffer_sink_ready - connect \main_sdram_bankmachine3_cmd_buffer_sink_first \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first - connect \main_sdram_bankmachine3_cmd_buffer_sink_last \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last - connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we - connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr - connect \main_sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:3689$218_Y - connect \main_sdram_bankmachine3_req_lock $or$ls180.v:3690$219_Y - connect \main_sdram_bankmachine3_row_hit $eq$ls180.v:3691$220_Y - connect \main_sdram_bankmachine3_cmd_payload_ba 2'11 - connect \main_sdram_bankmachine3_twtpcon_valid $and$ls180.v:3701$225_Y - connect \main_sdram_bankmachine3_trccon_valid $and$ls180.v:3702$227_Y - connect \main_sdram_bankmachine3_trascon_valid $and$ls180.v:3703$229_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we } - connect { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:3735$237_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:3736$238_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine3_cmd_buffer_lookahead_consume - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:3739$239_Y - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:3740$240_Y - connect \main_sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:3741$242_Y - connect \main_sdram_choose_req_want_cmds 1'1 - connect \main_sdram_trrdcon_valid $and$ls180.v:3837$253_Y - connect \main_sdram_tfawcon_valid $and$ls180.v:3838$259_Y - connect \main_sdram_ras_allowed $and$ls180.v:3839$260_Y - connect \main_sdram_tccdcon_valid $and$ls180.v:3840$263_Y - connect \main_sdram_cas_allowed \main_sdram_tccdcon_ready - connect \main_sdram_twtrcon_valid $and$ls180.v:3842$265_Y - connect \main_sdram_read_available $or$ls180.v:3843$272_Y - connect \main_sdram_write_available $or$ls180.v:3844$279_Y - connect \main_sdram_max_time0 $eq$ls180.v:3845$280_Y - connect \main_sdram_max_time1 $eq$ls180.v:3846$281_Y - connect \main_sdram_bankmachine0_refresh_req \main_sdram_cmd_valid - connect \main_sdram_bankmachine1_refresh_req \main_sdram_cmd_valid - connect \main_sdram_bankmachine2_refresh_req \main_sdram_cmd_valid - connect \main_sdram_bankmachine3_refresh_req \main_sdram_cmd_valid - connect \main_sdram_go_to_refresh $and$ls180.v:3851$284_Y - connect \main_sdram_interface_rdata \main_sdram_dfi_p0_rddata - connect \main_sdram_dfi_p0_wrdata \main_sdram_interface_wdata - connect \main_sdram_dfi_p0_wrdata_mask $not$ls180.v:3854$285_Y - connect \main_sdram_choose_cmd_request \main_sdram_choose_cmd_valids - connect \main_sdram_choose_cmd_cmd_valid \builder_comb_rhs_array_muxed0 - connect \main_sdram_choose_cmd_cmd_payload_a \builder_comb_rhs_array_muxed1 - connect \main_sdram_choose_cmd_cmd_payload_ba \builder_comb_rhs_array_muxed2 - connect \main_sdram_choose_cmd_cmd_payload_is_read \builder_comb_rhs_array_muxed3 - connect \main_sdram_choose_cmd_cmd_payload_is_write \builder_comb_rhs_array_muxed4 - connect \main_sdram_choose_cmd_cmd_payload_is_cmd \builder_comb_rhs_array_muxed5 - connect \main_sdram_choose_cmd_ce $or$ls180.v:3887$343_Y - connect \main_sdram_choose_req_request \main_sdram_choose_req_valids - connect \main_sdram_choose_req_cmd_valid \builder_comb_rhs_array_muxed6 - connect \main_sdram_choose_req_cmd_payload_a \builder_comb_rhs_array_muxed7 - connect \main_sdram_choose_req_cmd_payload_ba \builder_comb_rhs_array_muxed8 - connect \main_sdram_choose_req_cmd_payload_is_read \builder_comb_rhs_array_muxed9 - connect \main_sdram_choose_req_cmd_payload_is_write \builder_comb_rhs_array_muxed10 - connect \main_sdram_choose_req_cmd_payload_is_cmd \builder_comb_rhs_array_muxed11 - connect \main_sdram_choose_req_ce $or$ls180.v:3956$429_Y - connect \main_sdram_dfi_p0_reset_n 1'1 - connect \main_sdram_dfi_p0_cke \main_sdram_steerer0 - connect \main_sdram_dfi_p0_odt \main_sdram_steerer1 - connect \builder_roundrobin0_request $and$ls180.v:4033$461_Y - connect \builder_roundrobin0_ce $and$ls180.v:4034$464_Y - connect \main_sdram_interface_bank0_addr \builder_comb_rhs_array_muxed12 - connect \main_sdram_interface_bank0_we \builder_comb_rhs_array_muxed13 - connect \main_sdram_interface_bank0_valid \builder_comb_rhs_array_muxed14 - connect \builder_roundrobin1_request $and$ls180.v:4038$477_Y - connect \builder_roundrobin1_ce $and$ls180.v:4039$480_Y - connect \main_sdram_interface_bank1_addr \builder_comb_rhs_array_muxed15 - connect \main_sdram_interface_bank1_we \builder_comb_rhs_array_muxed16 - connect \main_sdram_interface_bank1_valid \builder_comb_rhs_array_muxed17 - connect \builder_roundrobin2_request $and$ls180.v:4043$493_Y - connect \builder_roundrobin2_ce $and$ls180.v:4044$496_Y - connect \main_sdram_interface_bank2_addr \builder_comb_rhs_array_muxed18 - connect \main_sdram_interface_bank2_we \builder_comb_rhs_array_muxed19 - connect \main_sdram_interface_bank2_valid \builder_comb_rhs_array_muxed20 - connect \builder_roundrobin3_request $and$ls180.v:4048$509_Y - connect \builder_roundrobin3_ce $and$ls180.v:4049$512_Y - connect \main_sdram_interface_bank3_addr \builder_comb_rhs_array_muxed21 - connect \main_sdram_interface_bank3_we \builder_comb_rhs_array_muxed22 - connect \main_sdram_interface_bank3_valid \builder_comb_rhs_array_muxed23 - connect \main_port_cmd_ready $or$ls180.v:4053$576_Y - connect \main_port_wdata_ready \builder_new_master_wdata_ready - connect \main_port_rdata_valid \builder_new_master_rdata_valid3 - connect \main_port_rdata_payload_data \main_sdram_interface_rdata - connect \builder_roundrobin0_grant 1'0 - connect \builder_roundrobin1_grant 1'0 - connect \builder_roundrobin2_grant 1'0 - connect \builder_roundrobin3_grant 1'0 - connect \main_converter_reset $not$ls180.v:4075$578_Y - connect \main_wb_sdram_dat_r { \main_litedram_wb_dat_r \main_converter_dat_r [31:16] } - connect \main_port_cmd_payload_addr $sub$ls180.v:4135$589_Y [23:0] - connect \main_port_cmd_payload_we \main_litedram_wb_we - connect \main_port_wdata_payload_data \main_litedram_wb_dat_w - connect \main_port_wdata_payload_we \main_litedram_wb_sel - connect \main_litedram_wb_dat_r \main_port_rdata_payload_data - connect \main_port_flush $not$ls180.v:4140$590_Y - connect \main_port_cmd_last $not$ls180.v:4141$591_Y - connect \main_port_cmd_valid $and$ls180.v:4142$594_Y - connect \main_port_wdata_valid $and$ls180.v:4143$598_Y - connect \main_port_rdata_ready $and$ls180.v:4144$601_Y - connect \main_litedram_wb_ack $and$ls180.v:4145$606_Y - connect \main_ack_cmd $or$ls180.v:4146$608_Y - connect \main_ack_wdata $or$ls180.v:4147$610_Y - connect \main_ack_rdata $and$ls180.v:4148$611_Y - connect \main_uart_uart_sink_valid \main_uart_phy_source_valid - connect \main_uart_phy_source_ready \main_uart_uart_sink_ready - connect \main_uart_uart_sink_first \main_uart_phy_source_first - connect \main_uart_uart_sink_last \main_uart_phy_source_last - connect \main_uart_uart_sink_payload_data \main_uart_phy_source_payload_data - connect \main_uart_phy_sink_valid \main_uart_uart_source_valid - connect \main_uart_uart_source_ready \main_uart_phy_sink_ready - connect \main_uart_phy_sink_first \main_uart_uart_source_first - connect \main_uart_phy_sink_last \main_uart_uart_source_last - connect \main_uart_phy_sink_payload_data \main_uart_uart_source_payload_data - connect \main_uart_tx_fifo_sink_valid \main_uart_rxtx_re - connect \main_uart_tx_fifo_sink_payload_data \main_uart_rxtx_r - connect \main_uart_txfull_status $not$ls180.v:4161$612_Y - connect \main_uart_txempty_status $not$ls180.v:4162$613_Y - connect \main_uart_uart_source_valid \main_uart_tx_fifo_source_valid - connect \main_uart_tx_fifo_source_ready \main_uart_uart_source_ready - connect \main_uart_uart_source_first \main_uart_tx_fifo_source_first - connect \main_uart_uart_source_last \main_uart_tx_fifo_source_last - connect \main_uart_uart_source_payload_data \main_uart_tx_fifo_source_payload_data - connect \main_uart_tx_trigger $not$ls180.v:4168$614_Y - connect \main_uart_rx_fifo_sink_valid \main_uart_uart_sink_valid - connect \main_uart_uart_sink_ready \main_uart_rx_fifo_sink_ready - connect \main_uart_rx_fifo_sink_first \main_uart_uart_sink_first - connect \main_uart_rx_fifo_sink_last \main_uart_uart_sink_last - connect \main_uart_rx_fifo_sink_payload_data \main_uart_uart_sink_payload_data - connect \main_uart_rxempty_status $not$ls180.v:4174$615_Y - connect \main_uart_rxfull_status $not$ls180.v:4175$616_Y - connect \main_uart_rxtx_w \main_uart_rx_fifo_source_payload_data - connect \main_uart_rx_fifo_source_ready $or$ls180.v:4177$618_Y - connect \main_uart_rx_trigger $not$ls180.v:4178$619_Y - connect \main_uart_irq $or$ls180.v:4201$628_Y - connect \main_uart_tx_status \main_uart_tx_trigger - connect \main_uart_rx_status \main_uart_rx_trigger - connect \main_uart_tx_fifo_syncfifo_din { \main_uart_tx_fifo_fifo_in_last \main_uart_tx_fifo_fifo_in_first \main_uart_tx_fifo_fifo_in_payload_data } - connect { \main_uart_tx_fifo_fifo_out_last \main_uart_tx_fifo_fifo_out_first \main_uart_tx_fifo_fifo_out_payload_data } \main_uart_tx_fifo_syncfifo_dout - connect \main_uart_tx_fifo_sink_ready \main_uart_tx_fifo_syncfifo_writable - connect \main_uart_tx_fifo_syncfifo_we \main_uart_tx_fifo_sink_valid - connect \main_uart_tx_fifo_fifo_in_first \main_uart_tx_fifo_sink_first - connect \main_uart_tx_fifo_fifo_in_last \main_uart_tx_fifo_sink_last - connect \main_uart_tx_fifo_fifo_in_payload_data \main_uart_tx_fifo_sink_payload_data - connect \main_uart_tx_fifo_source_valid \main_uart_tx_fifo_readable - connect \main_uart_tx_fifo_source_first \main_uart_tx_fifo_fifo_out_first - connect \main_uart_tx_fifo_source_last \main_uart_tx_fifo_fifo_out_last - connect \main_uart_tx_fifo_source_payload_data \main_uart_tx_fifo_fifo_out_payload_data - connect \main_uart_tx_fifo_re \main_uart_tx_fifo_source_ready - connect \main_uart_tx_fifo_syncfifo_re $and$ls180.v:4216$631_Y - connect \main_uart_tx_fifo_level1 $add$ls180.v:4217$632_Y - connect \main_uart_tx_fifo_wrport_dat_w \main_uart_tx_fifo_syncfifo_din - connect \main_uart_tx_fifo_wrport_we $and$ls180.v:4227$636_Y - connect \main_uart_tx_fifo_do_read $and$ls180.v:4228$637_Y - connect \main_uart_tx_fifo_rdport_adr \main_uart_tx_fifo_consume - connect \main_uart_tx_fifo_syncfifo_dout \main_uart_tx_fifo_rdport_dat_r - connect \main_uart_tx_fifo_rdport_re \main_uart_tx_fifo_do_read - connect \main_uart_tx_fifo_syncfifo_writable $ne$ls180.v:4232$638_Y - connect \main_uart_tx_fifo_syncfifo_readable $ne$ls180.v:4233$639_Y - connect \main_uart_rx_fifo_syncfifo_din { \main_uart_rx_fifo_fifo_in_last \main_uart_rx_fifo_fifo_in_first \main_uart_rx_fifo_fifo_in_payload_data } - connect { \main_uart_rx_fifo_fifo_out_last \main_uart_rx_fifo_fifo_out_first \main_uart_rx_fifo_fifo_out_payload_data } \main_uart_rx_fifo_syncfifo_dout - connect \main_uart_rx_fifo_sink_ready \main_uart_rx_fifo_syncfifo_writable - connect \main_uart_rx_fifo_syncfifo_we \main_uart_rx_fifo_sink_valid - connect \main_uart_rx_fifo_fifo_in_first \main_uart_rx_fifo_sink_first - connect \main_uart_rx_fifo_fifo_in_last \main_uart_rx_fifo_sink_last - connect \main_uart_rx_fifo_fifo_in_payload_data \main_uart_rx_fifo_sink_payload_data - connect \main_uart_rx_fifo_source_valid \main_uart_rx_fifo_readable - connect \main_uart_rx_fifo_source_first \main_uart_rx_fifo_fifo_out_first - connect \main_uart_rx_fifo_source_last \main_uart_rx_fifo_fifo_out_last - connect \main_uart_rx_fifo_source_payload_data \main_uart_rx_fifo_fifo_out_payload_data - connect \main_uart_rx_fifo_re \main_uart_rx_fifo_source_ready - connect \main_uart_rx_fifo_syncfifo_re $and$ls180.v:4246$642_Y - connect \main_uart_rx_fifo_level1 $add$ls180.v:4247$643_Y - connect \main_uart_rx_fifo_wrport_dat_w \main_uart_rx_fifo_syncfifo_din - connect \main_uart_rx_fifo_wrport_we $and$ls180.v:4257$647_Y - connect \main_uart_rx_fifo_do_read $and$ls180.v:4258$648_Y - connect \main_uart_rx_fifo_rdport_adr \main_uart_rx_fifo_consume - connect \main_uart_rx_fifo_syncfifo_dout \main_uart_rx_fifo_rdport_dat_r - connect \main_uart_rx_fifo_rdport_re \main_uart_rx_fifo_do_read - connect \main_uart_rx_fifo_syncfifo_writable $ne$ls180.v:4262$649_Y - connect \main_uart_rx_fifo_syncfifo_readable $ne$ls180.v:4263$650_Y - connect \main_gpiotristateasic0_pads_i \gpio_i - connect \main_gpiotristateasic0_pads_oe \main_gpiotristateasic0_oe_storage - connect \main_gpiotristateasic0_pads_o \main_gpiotristateasic0_out_storage - connect \main_gpiotristateasic1_pads_i \gpio_i - connect \main_gpiotristateasic1_pads_oe \main_gpiotristateasic1_oe_storage - connect \main_gpiotristateasic1_pads_o \main_gpiotristateasic1_out_storage - connect \main_spimaster0_start \main_spimaster9_start - connect \main_spimaster1_length \main_spimaster10_length - connect \main_spimaster4_mosi \main_spimaster16_storage - connect \main_spimaster13_done \main_spimaster2_done - connect \main_spimaster18_status \main_spimaster5_miso - connect \main_spimaster6_cs \main_spimaster21_storage - connect \main_spimaster7_loopback \main_spimaster23_storage - connect \main_spimaster31_clk_rise $eq$ls180.v:4287$654_Y - connect \main_spimaster32_clk_fall $eq$ls180.v:4288$656_Y - connect \main_spisdcard_start0 \main_spisdcard_start1 - connect \main_spisdcard_length0 \main_spisdcard_length1 - connect \main_spisdcard_mosi \main_spisdcard_mosi_storage - connect \main_spisdcard_done1 \main_spisdcard_done0 - connect \main_spisdcard_miso_status \main_spisdcard_miso - connect \main_spisdcard_cs \main_spisdcard_cs_storage - connect \main_spisdcard_loopback \main_spisdcard_loopback_storage - connect \main_spisdcard_clk_rise $eq$ls180.v:4345$662_Y - connect \main_spisdcard_clk_fall $eq$ls180.v:4346$664_Y - connect \main_spisdcard_clk_divider0 \main_spimaster1_storage - connect \i2c_scl \main_i2c_scl - connect \i2c_sda_oe \main_i2c_oe - connect \i2c_sda_o \main_i2c_sda0 - connect \main_i2c_sda1 \i2c_sda_i - connect \main_sdphy_status 1'0 - connect \main_sdphy_sdpads_clk $or$ls180.v:4402$672_Y - connect \main_sdphy_sdpads_cmd_oe $or$ls180.v:4403$676_Y - connect \main_sdphy_sdpads_cmd_o $or$ls180.v:4404$680_Y - connect \main_sdphy_sdpads_data_oe $or$ls180.v:4405$684_Y - connect \main_sdphy_sdpads_data_o $or$ls180.v:4406$688_Y - connect \main_sdphy_init_pads_out_ready \main_sdphy_clocker_ce - connect \main_sdphy_cmdw_pads_out_ready \main_sdphy_clocker_ce - connect \main_sdphy_cmdr_pads_out_ready \main_sdphy_clocker_ce - connect \main_sdphy_dataw_pads_out_ready \main_sdphy_clocker_ce - connect \main_sdphy_datar_pads_out_ready \main_sdphy_clocker_ce - connect \main_sdphy_init_pads_in_valid \main_sdphy_clocker_ce - connect \main_sdphy_init_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i - connect \main_sdphy_init_pads_in_payload_data_i \main_sdphy_sdpads_data_i - connect \main_sdphy_cmdw_pads_in_valid \main_sdphy_clocker_ce - connect \main_sdphy_cmdw_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i - connect \main_sdphy_cmdw_pads_in_payload_data_i \main_sdphy_sdpads_data_i - connect \main_sdphy_cmdr_pads_in_pads_in_valid \main_sdphy_clocker_ce - connect \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i - connect \main_sdphy_cmdr_pads_in_pads_in_payload_data_i \main_sdphy_sdpads_data_i - connect \main_sdphy_dataw_pads_in_valid \main_sdphy_clocker_ce - connect \main_sdphy_dataw_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i - connect \main_sdphy_dataw_pads_in_payload_data_i \main_sdphy_sdpads_data_i - connect \main_sdphy_datar_pads_in_pads_in_valid \main_sdphy_clocker_ce - connect \main_sdphy_datar_pads_in_pads_in_payload_cmd_i \main_sdphy_sdpads_cmd_i - connect \main_sdphy_datar_pads_in_pads_in_payload_data_i \main_sdphy_sdpads_data_i - connect \main_sdphy_clocker_stop $or$ls180.v:4427$689_Y - connect \main_sdphy_clocker_ce $and$ls180.v:4457$692_Y - connect \main_sdphy_cmdr_cmdr_pads_in_valid \main_sdphy_cmdr_pads_in_pads_in_valid - connect \main_sdphy_cmdr_pads_in_pads_in_ready \main_sdphy_cmdr_cmdr_pads_in_ready - connect \main_sdphy_cmdr_cmdr_pads_in_first \main_sdphy_cmdr_pads_in_pads_in_first - connect \main_sdphy_cmdr_cmdr_pads_in_last \main_sdphy_cmdr_pads_in_pads_in_last - connect \main_sdphy_cmdr_cmdr_pads_in_payload_clk \main_sdphy_cmdr_pads_in_pads_in_payload_clk - connect \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_i - connect \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_o \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_o - connect \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_oe \main_sdphy_cmdr_pads_in_pads_in_payload_cmd_oe - connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_i \main_sdphy_cmdr_pads_in_pads_in_payload_data_i - connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_o \main_sdphy_cmdr_pads_in_pads_in_payload_data_o - connect \main_sdphy_cmdr_cmdr_pads_in_payload_data_oe \main_sdphy_cmdr_pads_in_pads_in_payload_data_oe - connect \main_sdphy_cmdr_cmdr_start $eq$ls180.v:4580$702_Y - connect \main_sdphy_cmdr_cmdr_converter_sink_valid $and$ls180.v:4581$704_Y - connect \main_sdphy_cmdr_cmdr_converter_sink_payload_data \main_sdphy_cmdr_cmdr_pads_in_payload_cmd_i - connect \main_sdphy_cmdr_cmdr_buf_sink_valid \main_sdphy_cmdr_cmdr_source_source_valid1 - connect \main_sdphy_cmdr_cmdr_source_source_ready1 \main_sdphy_cmdr_cmdr_buf_sink_ready - connect \main_sdphy_cmdr_cmdr_buf_sink_first \main_sdphy_cmdr_cmdr_source_source_first1 - connect \main_sdphy_cmdr_cmdr_buf_sink_last \main_sdphy_cmdr_cmdr_source_source_last1 - connect \main_sdphy_cmdr_cmdr_buf_sink_payload_data \main_sdphy_cmdr_cmdr_source_source_payload_data1 - connect \main_sdphy_cmdr_cmdr_source_source_valid0 \main_sdphy_cmdr_cmdr_buf_source_valid - connect \main_sdphy_cmdr_cmdr_buf_source_ready \main_sdphy_cmdr_cmdr_source_source_ready0 - connect \main_sdphy_cmdr_cmdr_source_source_first0 \main_sdphy_cmdr_cmdr_buf_source_first - connect \main_sdphy_cmdr_cmdr_source_source_last0 \main_sdphy_cmdr_cmdr_buf_source_last - connect \main_sdphy_cmdr_cmdr_source_source_payload_data0 \main_sdphy_cmdr_cmdr_buf_source_payload_data - connect \main_sdphy_cmdr_cmdr_source_source_valid1 \main_sdphy_cmdr_cmdr_converter_source_valid - connect \main_sdphy_cmdr_cmdr_converter_source_ready \main_sdphy_cmdr_cmdr_source_source_ready1 - connect \main_sdphy_cmdr_cmdr_source_source_first1 \main_sdphy_cmdr_cmdr_converter_source_first - connect \main_sdphy_cmdr_cmdr_source_source_last1 \main_sdphy_cmdr_cmdr_converter_source_last - connect \main_sdphy_cmdr_cmdr_source_source_payload_data1 \main_sdphy_cmdr_cmdr_converter_source_payload_data - connect \main_sdphy_cmdr_cmdr_converter_sink_ready $or$ls180.v:4598$706_Y - connect \main_sdphy_cmdr_cmdr_converter_source_valid \main_sdphy_cmdr_cmdr_converter_strobe_all - connect \main_sdphy_cmdr_cmdr_converter_load_part $and$ls180.v:4600$707_Y - connect \main_sdphy_cmdr_cmdr_buf_sink_ready $or$ls180.v:4601$709_Y - connect \main_sdphy_dataw_crcr_pads_in_valid \main_sdphy_dataw_pads_in_pads_in_valid - connect \main_sdphy_dataw_pads_in_pads_in_ready \main_sdphy_dataw_crcr_pads_in_ready - connect \main_sdphy_dataw_crcr_pads_in_first \main_sdphy_dataw_pads_in_pads_in_first - connect \main_sdphy_dataw_crcr_pads_in_last \main_sdphy_dataw_pads_in_pads_in_last - connect \main_sdphy_dataw_crcr_pads_in_payload_clk \main_sdphy_dataw_pads_in_pads_in_payload_clk - connect \main_sdphy_dataw_crcr_pads_in_payload_cmd_i \main_sdphy_dataw_pads_in_pads_in_payload_cmd_i - connect \main_sdphy_dataw_crcr_pads_in_payload_cmd_o \main_sdphy_dataw_pads_in_pads_in_payload_cmd_o - connect \main_sdphy_dataw_crcr_pads_in_payload_cmd_oe \main_sdphy_dataw_pads_in_pads_in_payload_cmd_oe - connect \main_sdphy_dataw_crcr_pads_in_payload_data_i \main_sdphy_dataw_pads_in_pads_in_payload_data_i - connect \main_sdphy_dataw_crcr_pads_in_payload_data_o \main_sdphy_dataw_pads_in_pads_in_payload_data_o - connect \main_sdphy_dataw_crcr_pads_in_payload_data_oe \main_sdphy_dataw_pads_in_pads_in_payload_data_oe - connect \main_sdphy_dataw_crcr_start $eq$ls180.v:4707$724_Y - connect \main_sdphy_dataw_crcr_converter_sink_valid $and$ls180.v:4708$725_Y - connect \main_sdphy_dataw_crcr_converter_sink_payload_data \main_sdphy_dataw_crcr_pads_in_payload_data_i [0] - connect \main_sdphy_dataw_crcr_buf_sink_valid \main_sdphy_dataw_crcr_source_source_valid1 - connect \main_sdphy_dataw_crcr_source_source_ready1 \main_sdphy_dataw_crcr_buf_sink_ready - connect \main_sdphy_dataw_crcr_buf_sink_first \main_sdphy_dataw_crcr_source_source_first1 - connect \main_sdphy_dataw_crcr_buf_sink_last \main_sdphy_dataw_crcr_source_source_last1 - connect \main_sdphy_dataw_crcr_buf_sink_payload_data \main_sdphy_dataw_crcr_source_source_payload_data1 - connect \main_sdphy_dataw_crcr_source_source_valid0 \main_sdphy_dataw_crcr_buf_source_valid - connect \main_sdphy_dataw_crcr_buf_source_ready \main_sdphy_dataw_crcr_source_source_ready0 - connect \main_sdphy_dataw_crcr_source_source_first0 \main_sdphy_dataw_crcr_buf_source_first - connect \main_sdphy_dataw_crcr_source_source_last0 \main_sdphy_dataw_crcr_buf_source_last - connect \main_sdphy_dataw_crcr_source_source_payload_data0 \main_sdphy_dataw_crcr_buf_source_payload_data - connect \main_sdphy_dataw_crcr_source_source_valid1 \main_sdphy_dataw_crcr_converter_source_valid - connect \main_sdphy_dataw_crcr_converter_source_ready \main_sdphy_dataw_crcr_source_source_ready1 - connect \main_sdphy_dataw_crcr_source_source_first1 \main_sdphy_dataw_crcr_converter_source_first - connect \main_sdphy_dataw_crcr_source_source_last1 \main_sdphy_dataw_crcr_converter_source_last - connect \main_sdphy_dataw_crcr_source_source_payload_data1 \main_sdphy_dataw_crcr_converter_source_payload_data - connect \main_sdphy_dataw_crcr_converter_sink_ready $or$ls180.v:4725$727_Y - connect \main_sdphy_dataw_crcr_converter_source_valid \main_sdphy_dataw_crcr_converter_strobe_all - connect \main_sdphy_dataw_crcr_converter_load_part $and$ls180.v:4727$728_Y - connect \main_sdphy_dataw_crcr_buf_sink_ready $or$ls180.v:4728$730_Y - connect \main_sdphy_datar_datar_pads_in_valid \main_sdphy_datar_pads_in_pads_in_valid - connect \main_sdphy_datar_pads_in_pads_in_ready \main_sdphy_datar_datar_pads_in_ready - connect \main_sdphy_datar_datar_pads_in_first \main_sdphy_datar_pads_in_pads_in_first - connect \main_sdphy_datar_datar_pads_in_last \main_sdphy_datar_pads_in_pads_in_last - connect \main_sdphy_datar_datar_pads_in_payload_clk \main_sdphy_datar_pads_in_pads_in_payload_clk - connect \main_sdphy_datar_datar_pads_in_payload_cmd_i \main_sdphy_datar_pads_in_pads_in_payload_cmd_i - connect \main_sdphy_datar_datar_pads_in_payload_cmd_o \main_sdphy_datar_pads_in_pads_in_payload_cmd_o - connect \main_sdphy_datar_datar_pads_in_payload_cmd_oe \main_sdphy_datar_pads_in_pads_in_payload_cmd_oe - connect \main_sdphy_datar_datar_pads_in_payload_data_i \main_sdphy_datar_pads_in_pads_in_payload_data_i - connect \main_sdphy_datar_datar_pads_in_payload_data_o \main_sdphy_datar_pads_in_pads_in_payload_data_o - connect \main_sdphy_datar_datar_pads_in_payload_data_oe \main_sdphy_datar_pads_in_pads_in_payload_data_oe - connect \main_sdphy_datar_datar_start $eq$ls180.v:4841$739_Y - connect \main_sdphy_datar_datar_converter_sink_valid $and$ls180.v:4842$740_Y - connect \main_sdphy_datar_datar_converter_sink_payload_data \main_sdphy_datar_datar_pads_in_payload_data_i - connect \main_sdphy_datar_datar_buf_sink_valid \main_sdphy_datar_datar_source_source_valid1 - connect \main_sdphy_datar_datar_source_source_ready1 \main_sdphy_datar_datar_buf_sink_ready - connect \main_sdphy_datar_datar_buf_sink_first \main_sdphy_datar_datar_source_source_first1 - connect \main_sdphy_datar_datar_buf_sink_last \main_sdphy_datar_datar_source_source_last1 - connect \main_sdphy_datar_datar_buf_sink_payload_data \main_sdphy_datar_datar_source_source_payload_data1 - connect \main_sdphy_datar_datar_source_source_valid0 \main_sdphy_datar_datar_buf_source_valid - connect \main_sdphy_datar_datar_buf_source_ready \main_sdphy_datar_datar_source_source_ready0 - connect \main_sdphy_datar_datar_source_source_first0 \main_sdphy_datar_datar_buf_source_first - connect \main_sdphy_datar_datar_source_source_last0 \main_sdphy_datar_datar_buf_source_last - connect \main_sdphy_datar_datar_source_source_payload_data0 \main_sdphy_datar_datar_buf_source_payload_data - connect \main_sdphy_datar_datar_source_source_valid1 \main_sdphy_datar_datar_converter_source_valid - connect \main_sdphy_datar_datar_converter_source_ready \main_sdphy_datar_datar_source_source_ready1 - connect \main_sdphy_datar_datar_source_source_first1 \main_sdphy_datar_datar_converter_source_first - connect \main_sdphy_datar_datar_source_source_last1 \main_sdphy_datar_datar_converter_source_last - connect \main_sdphy_datar_datar_source_source_payload_data1 \main_sdphy_datar_datar_converter_source_payload_data - connect \main_sdphy_datar_datar_converter_sink_ready $or$ls180.v:4859$742_Y - connect \main_sdphy_datar_datar_converter_source_valid \main_sdphy_datar_datar_converter_strobe_all - connect \main_sdphy_datar_datar_converter_load_part $and$ls180.v:4861$743_Y - connect \main_sdphy_datar_datar_buf_sink_ready $or$ls180.v:4862$745_Y - connect \main_sdcore_crc16_inserter_sink_valid \main_sdcore_sink_sink_valid - connect \main_sdcore_sink_sink_ready \main_sdcore_crc16_inserter_sink_ready - connect \main_sdcore_crc16_inserter_sink_first \main_sdcore_sink_sink_first - connect \main_sdcore_crc16_inserter_sink_last \main_sdcore_sink_sink_last - connect \main_sdcore_crc16_inserter_sink_payload_data \main_sdcore_sink_sink_payload_data - connect \main_sdcore_source_source_valid \main_sdcore_crc16_checker_source_valid - connect \main_sdcore_crc16_checker_source_ready \main_sdcore_source_source_ready - connect \main_sdcore_source_source_first \main_sdcore_crc16_checker_source_first - connect \main_sdcore_source_source_last \main_sdcore_crc16_checker_source_last - connect \main_sdcore_source_source_payload_data \main_sdcore_crc16_checker_source_payload_data - connect \main_sdcore_cmd_type \main_sdcore_cmd_command_storage [1:0] - connect \main_sdcore_data_type \main_sdcore_cmd_command_storage [6:5] - connect \main_sdcore_cmd_event_status { 1'0 \main_sdcore_cmd_timeout \main_sdcore_cmd_error \main_sdcore_cmd_done } - connect \main_sdcore_data_event_status { $not$ls180.v:4978$760_Y \main_sdcore_data_timeout \main_sdcore_data_error \main_sdcore_data_done } - connect \main_sdcore_crc7_inserter_val { 2'01 \main_sdcore_cmd_command_storage [13:8] \main_sdcore_cmd_argument_storage } - connect \main_sdcore_crc7_inserter_clr 1'1 - connect \main_sdcore_crc7_inserter_enable 1'1 - connect \main_sdcore_crc7_inserter_crcreg1 { \main_sdcore_crc7_inserter_crcreg0 [5:3] $xor$ls180.v:4982$763_Y \main_sdcore_crc7_inserter_crcreg0 [1:0] $xor$ls180.v:4982$761_Y } - connect \main_sdcore_crc7_inserter_crcreg2 { \main_sdcore_crc7_inserter_crcreg1 [5:3] $xor$ls180.v:4983$766_Y \main_sdcore_crc7_inserter_crcreg1 [1:0] $xor$ls180.v:4983$764_Y } - connect \main_sdcore_crc7_inserter_crcreg3 { \main_sdcore_crc7_inserter_crcreg2 [5:3] $xor$ls180.v:4984$769_Y \main_sdcore_crc7_inserter_crcreg2 [1:0] $xor$ls180.v:4984$767_Y } - connect \main_sdcore_crc7_inserter_crcreg4 { \main_sdcore_crc7_inserter_crcreg3 [5:3] $xor$ls180.v:4985$772_Y \main_sdcore_crc7_inserter_crcreg3 [1:0] $xor$ls180.v:4985$770_Y } - connect \main_sdcore_crc7_inserter_crcreg5 { \main_sdcore_crc7_inserter_crcreg4 [5:3] $xor$ls180.v:4986$775_Y \main_sdcore_crc7_inserter_crcreg4 [1:0] $xor$ls180.v:4986$773_Y } - connect \main_sdcore_crc7_inserter_crcreg6 { \main_sdcore_crc7_inserter_crcreg5 [5:3] $xor$ls180.v:4987$778_Y \main_sdcore_crc7_inserter_crcreg5 [1:0] $xor$ls180.v:4987$776_Y } - connect \main_sdcore_crc7_inserter_crcreg7 { \main_sdcore_crc7_inserter_crcreg6 [5:3] $xor$ls180.v:4988$781_Y \main_sdcore_crc7_inserter_crcreg6 [1:0] $xor$ls180.v:4988$779_Y } - connect \main_sdcore_crc7_inserter_crcreg8 { \main_sdcore_crc7_inserter_crcreg7 [5:3] $xor$ls180.v:4989$784_Y \main_sdcore_crc7_inserter_crcreg7 [1:0] $xor$ls180.v:4989$782_Y } - connect \main_sdcore_crc7_inserter_crcreg9 { \main_sdcore_crc7_inserter_crcreg8 [5:3] $xor$ls180.v:4990$787_Y \main_sdcore_crc7_inserter_crcreg8 [1:0] $xor$ls180.v:4990$785_Y } - connect \main_sdcore_crc7_inserter_crcreg10 { \main_sdcore_crc7_inserter_crcreg9 [5:3] $xor$ls180.v:4991$790_Y \main_sdcore_crc7_inserter_crcreg9 [1:0] $xor$ls180.v:4991$788_Y } - connect \main_sdcore_crc7_inserter_crcreg11 { \main_sdcore_crc7_inserter_crcreg10 [5:3] $xor$ls180.v:4992$793_Y \main_sdcore_crc7_inserter_crcreg10 [1:0] $xor$ls180.v:4992$791_Y } - connect \main_sdcore_crc7_inserter_crcreg12 { \main_sdcore_crc7_inserter_crcreg11 [5:3] $xor$ls180.v:4993$796_Y \main_sdcore_crc7_inserter_crcreg11 [1:0] $xor$ls180.v:4993$794_Y } - connect \main_sdcore_crc7_inserter_crcreg13 { \main_sdcore_crc7_inserter_crcreg12 [5:3] $xor$ls180.v:4994$799_Y \main_sdcore_crc7_inserter_crcreg12 [1:0] $xor$ls180.v:4994$797_Y } - connect \main_sdcore_crc7_inserter_crcreg14 { \main_sdcore_crc7_inserter_crcreg13 [5:3] $xor$ls180.v:4995$802_Y \main_sdcore_crc7_inserter_crcreg13 [1:0] $xor$ls180.v:4995$800_Y } - connect \main_sdcore_crc7_inserter_crcreg15 { \main_sdcore_crc7_inserter_crcreg14 [5:3] $xor$ls180.v:4996$805_Y \main_sdcore_crc7_inserter_crcreg14 [1:0] $xor$ls180.v:4996$803_Y } - connect \main_sdcore_crc7_inserter_crcreg16 { \main_sdcore_crc7_inserter_crcreg15 [5:3] $xor$ls180.v:4997$808_Y \main_sdcore_crc7_inserter_crcreg15 [1:0] $xor$ls180.v:4997$806_Y } - connect \main_sdcore_crc7_inserter_crcreg17 { \main_sdcore_crc7_inserter_crcreg16 [5:3] $xor$ls180.v:4998$811_Y \main_sdcore_crc7_inserter_crcreg16 [1:0] $xor$ls180.v:4998$809_Y } - connect \main_sdcore_crc7_inserter_crcreg18 { \main_sdcore_crc7_inserter_crcreg17 [5:3] $xor$ls180.v:4999$814_Y \main_sdcore_crc7_inserter_crcreg17 [1:0] $xor$ls180.v:4999$812_Y } - connect \main_sdcore_crc7_inserter_crcreg19 { \main_sdcore_crc7_inserter_crcreg18 [5:3] $xor$ls180.v:5000$817_Y \main_sdcore_crc7_inserter_crcreg18 [1:0] $xor$ls180.v:5000$815_Y } - connect \main_sdcore_crc7_inserter_crcreg20 { \main_sdcore_crc7_inserter_crcreg19 [5:3] $xor$ls180.v:5001$820_Y \main_sdcore_crc7_inserter_crcreg19 [1:0] $xor$ls180.v:5001$818_Y } - connect \main_sdcore_crc7_inserter_crcreg21 { \main_sdcore_crc7_inserter_crcreg20 [5:3] $xor$ls180.v:5002$823_Y \main_sdcore_crc7_inserter_crcreg20 [1:0] $xor$ls180.v:5002$821_Y } - connect \main_sdcore_crc7_inserter_crcreg22 { \main_sdcore_crc7_inserter_crcreg21 [5:3] $xor$ls180.v:5003$826_Y \main_sdcore_crc7_inserter_crcreg21 [1:0] $xor$ls180.v:5003$824_Y } - connect \main_sdcore_crc7_inserter_crcreg23 { \main_sdcore_crc7_inserter_crcreg22 [5:3] $xor$ls180.v:5004$829_Y \main_sdcore_crc7_inserter_crcreg22 [1:0] $xor$ls180.v:5004$827_Y } - connect \main_sdcore_crc7_inserter_crcreg24 { \main_sdcore_crc7_inserter_crcreg23 [5:3] $xor$ls180.v:5005$832_Y \main_sdcore_crc7_inserter_crcreg23 [1:0] $xor$ls180.v:5005$830_Y } - connect \main_sdcore_crc7_inserter_crcreg25 { \main_sdcore_crc7_inserter_crcreg24 [5:3] $xor$ls180.v:5006$835_Y \main_sdcore_crc7_inserter_crcreg24 [1:0] $xor$ls180.v:5006$833_Y } - connect \main_sdcore_crc7_inserter_crcreg26 { \main_sdcore_crc7_inserter_crcreg25 [5:3] $xor$ls180.v:5007$838_Y \main_sdcore_crc7_inserter_crcreg25 [1:0] $xor$ls180.v:5007$836_Y } - connect \main_sdcore_crc7_inserter_crcreg27 { \main_sdcore_crc7_inserter_crcreg26 [5:3] $xor$ls180.v:5008$841_Y \main_sdcore_crc7_inserter_crcreg26 [1:0] $xor$ls180.v:5008$839_Y } - connect \main_sdcore_crc7_inserter_crcreg28 { \main_sdcore_crc7_inserter_crcreg27 [5:3] $xor$ls180.v:5009$844_Y \main_sdcore_crc7_inserter_crcreg27 [1:0] $xor$ls180.v:5009$842_Y } - connect \main_sdcore_crc7_inserter_crcreg29 { \main_sdcore_crc7_inserter_crcreg28 [5:3] $xor$ls180.v:5010$847_Y \main_sdcore_crc7_inserter_crcreg28 [1:0] $xor$ls180.v:5010$845_Y } - connect \main_sdcore_crc7_inserter_crcreg30 { \main_sdcore_crc7_inserter_crcreg29 [5:3] $xor$ls180.v:5011$850_Y \main_sdcore_crc7_inserter_crcreg29 [1:0] $xor$ls180.v:5011$848_Y } - connect \main_sdcore_crc7_inserter_crcreg31 { \main_sdcore_crc7_inserter_crcreg30 [5:3] $xor$ls180.v:5012$853_Y \main_sdcore_crc7_inserter_crcreg30 [1:0] $xor$ls180.v:5012$851_Y } - connect \main_sdcore_crc7_inserter_crcreg32 { \main_sdcore_crc7_inserter_crcreg31 [5:3] $xor$ls180.v:5013$856_Y \main_sdcore_crc7_inserter_crcreg31 [1:0] $xor$ls180.v:5013$854_Y } - connect \main_sdcore_crc7_inserter_crcreg33 { \main_sdcore_crc7_inserter_crcreg32 [5:3] $xor$ls180.v:5014$859_Y \main_sdcore_crc7_inserter_crcreg32 [1:0] $xor$ls180.v:5014$857_Y } - connect \main_sdcore_crc7_inserter_crcreg34 { \main_sdcore_crc7_inserter_crcreg33 [5:3] $xor$ls180.v:5015$862_Y \main_sdcore_crc7_inserter_crcreg33 [1:0] $xor$ls180.v:5015$860_Y } - connect \main_sdcore_crc7_inserter_crcreg35 { \main_sdcore_crc7_inserter_crcreg34 [5:3] $xor$ls180.v:5016$865_Y \main_sdcore_crc7_inserter_crcreg34 [1:0] $xor$ls180.v:5016$863_Y } - connect \main_sdcore_crc7_inserter_crcreg36 { \main_sdcore_crc7_inserter_crcreg35 [5:3] $xor$ls180.v:5017$868_Y \main_sdcore_crc7_inserter_crcreg35 [1:0] $xor$ls180.v:5017$866_Y } - connect \main_sdcore_crc7_inserter_crcreg37 { \main_sdcore_crc7_inserter_crcreg36 [5:3] $xor$ls180.v:5018$871_Y \main_sdcore_crc7_inserter_crcreg36 [1:0] $xor$ls180.v:5018$869_Y } - connect \main_sdcore_crc7_inserter_crcreg38 { \main_sdcore_crc7_inserter_crcreg37 [5:3] $xor$ls180.v:5019$874_Y \main_sdcore_crc7_inserter_crcreg37 [1:0] $xor$ls180.v:5019$872_Y } - connect \main_sdcore_crc7_inserter_crcreg39 { \main_sdcore_crc7_inserter_crcreg38 [5:3] $xor$ls180.v:5020$877_Y \main_sdcore_crc7_inserter_crcreg38 [1:0] $xor$ls180.v:5020$875_Y } - connect \main_sdcore_crc7_inserter_crcreg40 { \main_sdcore_crc7_inserter_crcreg39 [5:3] $xor$ls180.v:5021$880_Y \main_sdcore_crc7_inserter_crcreg39 [1:0] $xor$ls180.v:5021$878_Y } - connect \main_sdcore_crc16_inserter_crc0_val { \main_sdcore_crc16_inserter_sink_payload_data [4] \main_sdcore_crc16_inserter_sink_payload_data [0] } - connect \main_sdcore_crc16_inserter_crc0_clr $and$ls180.v:5031$883_Y - connect \main_sdcore_crc16_inserter_crc0_enable $and$ls180.v:5032$884_Y - connect \main_sdcore_crc16_inserter_crc1_val { \main_sdcore_crc16_inserter_sink_payload_data [5] \main_sdcore_crc16_inserter_sink_payload_data [1] } - connect \main_sdcore_crc16_inserter_crc1_clr $and$ls180.v:5034$886_Y - connect \main_sdcore_crc16_inserter_crc1_enable $and$ls180.v:5035$887_Y - connect \main_sdcore_crc16_inserter_crc2_val { \main_sdcore_crc16_inserter_sink_payload_data [6] \main_sdcore_crc16_inserter_sink_payload_data [2] } - connect \main_sdcore_crc16_inserter_crc2_clr $and$ls180.v:5037$889_Y - connect \main_sdcore_crc16_inserter_crc2_enable $and$ls180.v:5038$890_Y - connect \main_sdcore_crc16_inserter_crc3_val { \main_sdcore_crc16_inserter_sink_payload_data [7] \main_sdcore_crc16_inserter_sink_payload_data [3] } - connect \main_sdcore_crc16_inserter_crc3_clr $and$ls180.v:5040$892_Y - connect \main_sdcore_crc16_inserter_crc3_enable $and$ls180.v:5041$893_Y - connect \main_sdcore_crc16_inserter_crc0_crcreg1 { \main_sdcore_crc16_inserter_crc0_crcreg0 [14:12] $xor$ls180.v:5042$898_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [10:5] $xor$ls180.v:5042$896_Y \main_sdcore_crc16_inserter_crc0_crcreg0 [3:0] $xor$ls180.v:5042$894_Y } - connect \main_sdcore_crc16_inserter_crc0_crcreg2 { \main_sdcore_crc16_inserter_crc0_crcreg1 [14:12] $xor$ls180.v:5043$903_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [10:5] $xor$ls180.v:5043$901_Y \main_sdcore_crc16_inserter_crc0_crcreg1 [3:0] $xor$ls180.v:5043$899_Y } - connect \main_sdcore_crc16_inserter_crc1_crcreg1 { \main_sdcore_crc16_inserter_crc1_crcreg0 [14:12] $xor$ls180.v:5052$909_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [10:5] $xor$ls180.v:5052$907_Y \main_sdcore_crc16_inserter_crc1_crcreg0 [3:0] $xor$ls180.v:5052$905_Y } - connect \main_sdcore_crc16_inserter_crc1_crcreg2 { \main_sdcore_crc16_inserter_crc1_crcreg1 [14:12] $xor$ls180.v:5053$914_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [10:5] $xor$ls180.v:5053$912_Y \main_sdcore_crc16_inserter_crc1_crcreg1 [3:0] $xor$ls180.v:5053$910_Y } - connect \main_sdcore_crc16_inserter_crc2_crcreg1 { \main_sdcore_crc16_inserter_crc2_crcreg0 [14:12] $xor$ls180.v:5062$920_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [10:5] $xor$ls180.v:5062$918_Y \main_sdcore_crc16_inserter_crc2_crcreg0 [3:0] $xor$ls180.v:5062$916_Y } - connect \main_sdcore_crc16_inserter_crc2_crcreg2 { \main_sdcore_crc16_inserter_crc2_crcreg1 [14:12] $xor$ls180.v:5063$925_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [10:5] $xor$ls180.v:5063$923_Y \main_sdcore_crc16_inserter_crc2_crcreg1 [3:0] $xor$ls180.v:5063$921_Y } - connect \main_sdcore_crc16_inserter_crc3_crcreg1 { \main_sdcore_crc16_inserter_crc3_crcreg0 [14:12] $xor$ls180.v:5072$931_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [10:5] $xor$ls180.v:5072$929_Y \main_sdcore_crc16_inserter_crc3_crcreg0 [3:0] $xor$ls180.v:5072$927_Y } - connect \main_sdcore_crc16_inserter_crc3_crcreg2 { \main_sdcore_crc16_inserter_crc3_crcreg1 [14:12] $xor$ls180.v:5073$936_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [10:5] $xor$ls180.v:5073$934_Y \main_sdcore_crc16_inserter_crc3_crcreg1 [3:0] $xor$ls180.v:5073$932_Y } - connect \main_sdcore_crc16_checker_crc0_val { \main_sdcore_crc16_checker_val [7] \main_sdcore_crc16_checker_val [3] } - connect \main_sdcore_crc16_checker_crc0_enable $and$ls180.v:5169$952_Y - connect \main_sdcore_crc16_checker_crc1_val { \main_sdcore_crc16_checker_val [6] \main_sdcore_crc16_checker_val [2] } - connect \main_sdcore_crc16_checker_crc1_enable $and$ls180.v:5179$955_Y - connect \main_sdcore_crc16_checker_crc2_val { \main_sdcore_crc16_checker_val [5] \main_sdcore_crc16_checker_val [1] } - connect \main_sdcore_crc16_checker_crc2_enable $and$ls180.v:5189$958_Y - connect \main_sdcore_crc16_checker_crc3_val { \main_sdcore_crc16_checker_val [4] \main_sdcore_crc16_checker_val [0] } - connect \main_sdcore_crc16_checker_crc3_enable $and$ls180.v:5199$961_Y - connect \main_sdcore_crc16_checker_source_payload_data \main_sdcore_crc16_checker_val - connect \main_sdcore_crc16_checker_source_last \main_sdcore_crc16_checker_sink_last - connect \main_sdcore_crc16_checker_crc0_crcreg1 { \main_sdcore_crc16_checker_crc0_crcreg0 [14:12] $xor$ls180.v:5224$973_Y \main_sdcore_crc16_checker_crc0_crcreg0 [10:5] $xor$ls180.v:5224$971_Y \main_sdcore_crc16_checker_crc0_crcreg0 [3:0] $xor$ls180.v:5224$969_Y } - connect \main_sdcore_crc16_checker_crc0_crcreg2 { \main_sdcore_crc16_checker_crc0_crcreg1 [14:12] $xor$ls180.v:5225$978_Y \main_sdcore_crc16_checker_crc0_crcreg1 [10:5] $xor$ls180.v:5225$976_Y \main_sdcore_crc16_checker_crc0_crcreg1 [3:0] $xor$ls180.v:5225$974_Y } - connect \main_sdcore_crc16_checker_crc1_crcreg1 { \main_sdcore_crc16_checker_crc1_crcreg0 [14:12] $xor$ls180.v:5234$984_Y \main_sdcore_crc16_checker_crc1_crcreg0 [10:5] $xor$ls180.v:5234$982_Y \main_sdcore_crc16_checker_crc1_crcreg0 [3:0] $xor$ls180.v:5234$980_Y } - connect \main_sdcore_crc16_checker_crc1_crcreg2 { \main_sdcore_crc16_checker_crc1_crcreg1 [14:12] $xor$ls180.v:5235$989_Y \main_sdcore_crc16_checker_crc1_crcreg1 [10:5] $xor$ls180.v:5235$987_Y \main_sdcore_crc16_checker_crc1_crcreg1 [3:0] $xor$ls180.v:5235$985_Y } - connect \main_sdcore_crc16_checker_crc2_crcreg1 { \main_sdcore_crc16_checker_crc2_crcreg0 [14:12] $xor$ls180.v:5244$995_Y \main_sdcore_crc16_checker_crc2_crcreg0 [10:5] $xor$ls180.v:5244$993_Y \main_sdcore_crc16_checker_crc2_crcreg0 [3:0] $xor$ls180.v:5244$991_Y } - connect \main_sdcore_crc16_checker_crc2_crcreg2 { \main_sdcore_crc16_checker_crc2_crcreg1 [14:12] $xor$ls180.v:5245$1000_Y \main_sdcore_crc16_checker_crc2_crcreg1 [10:5] $xor$ls180.v:5245$998_Y \main_sdcore_crc16_checker_crc2_crcreg1 [3:0] $xor$ls180.v:5245$996_Y } - connect \main_sdcore_crc16_checker_crc3_crcreg1 { \main_sdcore_crc16_checker_crc3_crcreg0 [14:12] $xor$ls180.v:5254$1006_Y \main_sdcore_crc16_checker_crc3_crcreg0 [10:5] $xor$ls180.v:5254$1004_Y \main_sdcore_crc16_checker_crc3_crcreg0 [3:0] $xor$ls180.v:5254$1002_Y } - connect \main_sdcore_crc16_checker_crc3_crcreg2 { \main_sdcore_crc16_checker_crc3_crcreg1 [14:12] $xor$ls180.v:5255$1011_Y \main_sdcore_crc16_checker_crc3_crcreg1 [10:5] $xor$ls180.v:5255$1009_Y \main_sdcore_crc16_checker_crc3_crcreg1 [3:0] $xor$ls180.v:5255$1007_Y } - connect \main_sdblock2mem_fifo_sink_valid \main_sdblock2mem_sink_sink_valid0 - connect \main_sdblock2mem_sink_sink_ready0 \main_sdblock2mem_fifo_sink_ready - connect \main_sdblock2mem_fifo_sink_first \main_sdblock2mem_sink_sink_first - connect \main_sdblock2mem_fifo_sink_last \main_sdblock2mem_sink_sink_last - connect \main_sdblock2mem_fifo_sink_payload_data \main_sdblock2mem_sink_sink_payload_data0 - connect \main_sdblock2mem_converter_sink_valid \main_sdblock2mem_fifo_source_valid - connect \main_sdblock2mem_fifo_source_ready \main_sdblock2mem_converter_sink_ready - connect \main_sdblock2mem_converter_sink_first \main_sdblock2mem_fifo_source_first - connect \main_sdblock2mem_converter_sink_last \main_sdblock2mem_fifo_source_last - connect \main_sdblock2mem_converter_sink_payload_data \main_sdblock2mem_fifo_source_payload_data - connect \main_sdblock2mem_wishbonedmawriter_sink_valid \main_sdblock2mem_source_source_valid - connect \main_sdblock2mem_source_source_ready \main_sdblock2mem_wishbonedmawriter_sink_ready - connect \main_sdblock2mem_wishbonedmawriter_sink_first \main_sdblock2mem_source_source_first - connect \main_sdblock2mem_wishbonedmawriter_sink_last \main_sdblock2mem_source_source_last - connect \main_sdblock2mem_wishbonedmawriter_sink_payload_data \main_sdblock2mem_source_source_payload_data - connect \main_sdblock2mem_fifo_syncfifo_din { \main_sdblock2mem_fifo_fifo_in_last \main_sdblock2mem_fifo_fifo_in_first \main_sdblock2mem_fifo_fifo_in_payload_data } - connect { \main_sdblock2mem_fifo_fifo_out_last \main_sdblock2mem_fifo_fifo_out_first \main_sdblock2mem_fifo_fifo_out_payload_data } \main_sdblock2mem_fifo_syncfifo_dout - connect \main_sdblock2mem_fifo_sink_ready \main_sdblock2mem_fifo_syncfifo_writable - connect \main_sdblock2mem_fifo_syncfifo_we \main_sdblock2mem_fifo_sink_valid - connect \main_sdblock2mem_fifo_fifo_in_first \main_sdblock2mem_fifo_sink_first - connect \main_sdblock2mem_fifo_fifo_in_last \main_sdblock2mem_fifo_sink_last - connect \main_sdblock2mem_fifo_fifo_in_payload_data \main_sdblock2mem_fifo_sink_payload_data - connect \main_sdblock2mem_fifo_source_valid \main_sdblock2mem_fifo_syncfifo_readable - connect \main_sdblock2mem_fifo_source_first \main_sdblock2mem_fifo_fifo_out_first - connect \main_sdblock2mem_fifo_source_last \main_sdblock2mem_fifo_fifo_out_last - connect \main_sdblock2mem_fifo_source_payload_data \main_sdblock2mem_fifo_fifo_out_payload_data - connect \main_sdblock2mem_fifo_syncfifo_re \main_sdblock2mem_fifo_source_ready - connect \main_sdblock2mem_fifo_wrport_dat_w \main_sdblock2mem_fifo_syncfifo_din - connect \main_sdblock2mem_fifo_wrport_we $and$ls180.v:5491$1041_Y - connect \main_sdblock2mem_fifo_do_read $and$ls180.v:5492$1042_Y - connect \main_sdblock2mem_fifo_rdport_adr \main_sdblock2mem_fifo_consume - connect \main_sdblock2mem_fifo_syncfifo_dout \main_sdblock2mem_fifo_rdport_dat_r - connect \main_sdblock2mem_fifo_syncfifo_writable $ne$ls180.v:5495$1043_Y - connect \main_sdblock2mem_fifo_syncfifo_readable $ne$ls180.v:5496$1044_Y - connect \main_sdblock2mem_source_source_valid \main_sdblock2mem_converter_source_valid - connect \main_sdblock2mem_converter_source_ready \main_sdblock2mem_source_source_ready - connect \main_sdblock2mem_source_source_first \main_sdblock2mem_converter_source_first - connect \main_sdblock2mem_source_source_last \main_sdblock2mem_converter_source_last - connect \main_sdblock2mem_source_source_payload_data \main_sdblock2mem_converter_source_payload_data - connect \main_sdblock2mem_converter_sink_ready $or$ls180.v:5502$1046_Y - connect \main_sdblock2mem_converter_source_valid \main_sdblock2mem_converter_strobe_all - connect \main_sdblock2mem_converter_load_part $and$ls180.v:5504$1047_Y - connect \main_interface0_bus_stb \main_sdblock2mem_sink_sink_valid1 - connect \main_interface0_bus_cyc \main_sdblock2mem_sink_sink_valid1 - connect \main_interface0_bus_we 1'1 - connect \main_interface0_bus_sel 8'11111111 - connect \main_interface0_bus_adr \main_sdblock2mem_sink_sink_payload_address - connect \main_interface0_bus_dat_w { \main_sdblock2mem_sink_sink_payload_data1 [7:0] \main_sdblock2mem_sink_sink_payload_data1 [15:8] \main_sdblock2mem_sink_sink_payload_data1 [23:16] \main_sdblock2mem_sink_sink_payload_data1 [31:24] \main_sdblock2mem_sink_sink_payload_data1 [39:32] \main_sdblock2mem_sink_sink_payload_data1 [47:40] \main_sdblock2mem_sink_sink_payload_data1 [55:48] \main_sdblock2mem_sink_sink_payload_data1 [63:56] } - connect \main_sdblock2mem_sink_sink_ready1 \main_interface0_bus_ack - connect \main_sdblock2mem_wishbonedmawriter_base \main_sdblock2mem_wishbonedmawriter_base_storage [34:3] - connect \main_sdblock2mem_wishbonedmawriter_length { 3'000 \main_sdblock2mem_wishbonedmawriter_length_storage [31:3] } - connect \main_sdblock2mem_wishbonedmawriter_reset $not$ls180.v:5514$1048_Y - connect \main_sdmem2block_converter_sink_valid \main_sdmem2block_dma_source_valid - connect \main_sdmem2block_dma_source_ready \main_sdmem2block_converter_sink_ready - connect \main_sdmem2block_converter_sink_first \main_sdmem2block_dma_source_first - connect \main_sdmem2block_converter_sink_last \main_sdmem2block_dma_source_last - connect \main_sdmem2block_converter_sink_payload_data \main_sdmem2block_dma_source_payload_data - connect \main_sdmem2block_fifo_sink_valid \main_sdmem2block_source_source_valid1 - connect \main_sdmem2block_source_source_ready1 \main_sdmem2block_fifo_sink_ready - connect \main_sdmem2block_fifo_sink_first \main_sdmem2block_source_source_first1 - connect \main_sdmem2block_fifo_sink_last \main_sdmem2block_source_source_last1 - connect \main_sdmem2block_fifo_sink_payload_data \main_sdmem2block_source_source_payload_data1 - connect \main_sdmem2block_source_source_valid0 \main_sdmem2block_fifo_source_valid - connect \main_sdmem2block_fifo_source_ready \main_sdmem2block_source_source_ready0 - connect \main_sdmem2block_source_source_first0 \main_sdmem2block_fifo_source_first - connect \main_sdmem2block_source_source_last0 \main_sdmem2block_fifo_source_last - connect \main_sdmem2block_source_source_payload_data0 \main_sdmem2block_fifo_source_payload_data - connect \main_sdmem2block_dma_base \main_sdmem2block_dma_base_storage [34:3] - connect \main_sdmem2block_dma_length { 3'000 \main_sdmem2block_dma_length_storage [31:3] } - connect \main_sdmem2block_dma_offset_status \main_sdmem2block_dma_offset - connect \main_sdmem2block_dma_reset $not$ls180.v:5573$1055_Y - connect \main_sdmem2block_source_source_valid1 \main_sdmem2block_converter_source_valid - connect \main_sdmem2block_converter_source_ready \main_sdmem2block_source_source_ready1 - connect \main_sdmem2block_source_source_first1 \main_sdmem2block_converter_source_first - connect \main_sdmem2block_source_source_last1 \main_sdmem2block_converter_source_last - connect \main_sdmem2block_source_source_payload_data1 \main_sdmem2block_converter_source_payload_data - connect \main_sdmem2block_converter_first $eq$ls180.v:5654$1063_Y - connect \main_sdmem2block_converter_last $eq$ls180.v:5655$1064_Y - connect \main_sdmem2block_converter_source_valid \main_sdmem2block_converter_sink_valid - connect \main_sdmem2block_converter_source_first $and$ls180.v:5657$1065_Y - connect \main_sdmem2block_converter_source_last $and$ls180.v:5658$1066_Y - connect \main_sdmem2block_converter_sink_ready $and$ls180.v:5659$1067_Y - connect \main_sdmem2block_converter_source_payload_valid_token_count \main_sdmem2block_converter_last - connect \main_sdmem2block_fifo_syncfifo_din { \main_sdmem2block_fifo_fifo_in_last \main_sdmem2block_fifo_fifo_in_first \main_sdmem2block_fifo_fifo_in_payload_data } - connect { \main_sdmem2block_fifo_fifo_out_last \main_sdmem2block_fifo_fifo_out_first \main_sdmem2block_fifo_fifo_out_payload_data } \main_sdmem2block_fifo_syncfifo_dout - connect \main_sdmem2block_fifo_sink_ready \main_sdmem2block_fifo_syncfifo_writable - connect \main_sdmem2block_fifo_syncfifo_we \main_sdmem2block_fifo_sink_valid - connect \main_sdmem2block_fifo_fifo_in_first \main_sdmem2block_fifo_sink_first - connect \main_sdmem2block_fifo_fifo_in_last \main_sdmem2block_fifo_sink_last - connect \main_sdmem2block_fifo_fifo_in_payload_data \main_sdmem2block_fifo_sink_payload_data - connect \main_sdmem2block_fifo_source_valid \main_sdmem2block_fifo_syncfifo_readable - connect \main_sdmem2block_fifo_source_first \main_sdmem2block_fifo_fifo_out_first - connect \main_sdmem2block_fifo_source_last \main_sdmem2block_fifo_fifo_out_last - connect \main_sdmem2block_fifo_source_payload_data \main_sdmem2block_fifo_fifo_out_payload_data - connect \main_sdmem2block_fifo_syncfifo_re \main_sdmem2block_fifo_source_ready - connect \main_sdmem2block_fifo_wrport_dat_w \main_sdmem2block_fifo_syncfifo_din - connect \main_sdmem2block_fifo_wrport_we $and$ls180.v:5711$1072_Y - connect \main_sdmem2block_fifo_do_read $and$ls180.v:5712$1073_Y - connect \main_sdmem2block_fifo_rdport_adr \main_sdmem2block_fifo_consume - connect \main_sdmem2block_fifo_syncfifo_dout \main_sdmem2block_fifo_rdport_dat_r - connect \main_sdmem2block_fifo_syncfifo_writable $ne$ls180.v:5715$1074_Y - connect \main_sdmem2block_fifo_syncfifo_readable $ne$ls180.v:5716$1075_Y - connect \builder_shared_adr \builder_comb_rhs_array_muxed24 [29:0] - connect \builder_shared_dat_w \builder_comb_rhs_array_muxed25 [31:0] - connect \builder_shared_sel \builder_comb_rhs_array_muxed26 [3:0] - connect \builder_shared_cyc \builder_comb_rhs_array_muxed27 - connect \builder_shared_stb \builder_comb_rhs_array_muxed28 - connect \builder_shared_we \builder_comb_rhs_array_muxed29 - connect \builder_shared_cti \builder_comb_rhs_array_muxed30 - connect \builder_shared_bte \builder_comb_rhs_array_muxed31 - connect \main_libresocsim_libresoc_ibus_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } - connect \main_libresocsim_libresoc_dbus_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } - connect \main_libresocsim_libresoc_jtag_wb_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } - connect \main_interface0_bus_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } - connect \main_interface1_bus_dat_r { 32'00000000000000000000000000000000 \builder_shared_dat_r } - connect \main_libresocsim_libresoc_ibus_ack $and$ls180.v:5767$1081_Y - connect \main_libresocsim_libresoc_dbus_ack $and$ls180.v:5768$1083_Y - connect \main_libresocsim_libresoc_jtag_wb_ack $and$ls180.v:5769$1085_Y - connect \main_interface0_bus_ack $and$ls180.v:5770$1087_Y - connect \main_interface1_bus_ack $and$ls180.v:5771$1089_Y - connect \main_libresocsim_libresoc_ibus_err $and$ls180.v:5772$1091_Y - connect \main_libresocsim_libresoc_dbus_err $and$ls180.v:5773$1093_Y - connect \main_libresocsim_libresoc_jtag_wb_err $and$ls180.v:5774$1095_Y - connect \main_interface0_bus_err $and$ls180.v:5775$1097_Y - connect \main_interface1_bus_err $and$ls180.v:5776$1099_Y - connect \builder_request { \main_interface1_bus_cyc \main_interface0_bus_cyc \main_libresocsim_libresoc_jtag_wb_cyc \main_libresocsim_libresoc_dbus_cyc \main_libresocsim_libresoc_ibus_cyc } - connect \main_libresocsim_ram_bus_adr \builder_shared_adr - connect \main_libresocsim_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } - connect \main_libresocsim_ram_bus_sel { 4'0000 \builder_shared_sel } - connect \main_libresocsim_ram_bus_stb \builder_shared_stb - connect \main_libresocsim_ram_bus_we \builder_shared_we - connect \main_libresocsim_ram_bus_cti \builder_shared_cti - connect \main_libresocsim_ram_bus_bte \builder_shared_bte - connect \main_ram_bus_ram_bus_adr \builder_shared_adr - connect \main_ram_bus_ram_bus_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } - connect \main_ram_bus_ram_bus_sel { 4'0000 \builder_shared_sel } - connect \main_ram_bus_ram_bus_stb \builder_shared_stb - connect \main_ram_bus_ram_bus_we \builder_shared_we - connect \main_ram_bus_ram_bus_cti \builder_shared_cti - connect \main_ram_bus_ram_bus_bte \builder_shared_bte - connect \main_interface0_converted_interface_adr \builder_shared_adr - connect \main_interface0_converted_interface_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } - connect \main_interface0_converted_interface_sel { 4'0000 \builder_shared_sel } - connect \main_interface0_converted_interface_stb \builder_shared_stb - connect \main_interface0_converted_interface_we \builder_shared_we - connect \main_interface0_converted_interface_cti \builder_shared_cti - connect \main_interface0_converted_interface_bte \builder_shared_bte - connect \main_interface1_converted_interface_adr \builder_shared_adr - connect \main_interface1_converted_interface_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } - connect \main_interface1_converted_interface_sel { 4'0000 \builder_shared_sel } - connect \main_interface1_converted_interface_stb \builder_shared_stb - connect \main_interface1_converted_interface_we \builder_shared_we - connect \main_interface1_converted_interface_cti \builder_shared_cti - connect \main_interface1_converted_interface_bte \builder_shared_bte - connect \main_socbushandler_converted_interface_adr \builder_shared_adr - connect \main_socbushandler_converted_interface_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } - connect \main_socbushandler_converted_interface_sel { 4'0000 \builder_shared_sel } - connect \main_socbushandler_converted_interface_stb \builder_shared_stb - connect \main_socbushandler_converted_interface_we \builder_shared_we - connect \main_socbushandler_converted_interface_cti \builder_shared_cti - connect \main_socbushandler_converted_interface_bte \builder_shared_bte - connect \builder_libresocsim_converted_interface_adr \builder_shared_adr - connect \builder_libresocsim_converted_interface_dat_w { 32'00000000000000000000000000000000 \builder_shared_dat_w } - connect \builder_libresocsim_converted_interface_sel { 4'0000 \builder_shared_sel } - connect \builder_libresocsim_converted_interface_stb \builder_shared_stb - connect \builder_libresocsim_converted_interface_we \builder_shared_we - connect \builder_libresocsim_converted_interface_cti \builder_shared_cti - connect \builder_libresocsim_converted_interface_bte \builder_shared_bte - connect \main_libresocsim_ram_bus_cyc $and$ls180.v:5829$1107_Y - connect \main_ram_bus_ram_bus_cyc $and$ls180.v:5830$1108_Y - connect \main_interface0_converted_interface_cyc $and$ls180.v:5831$1109_Y - connect \main_interface1_converted_interface_cyc $and$ls180.v:5832$1110_Y - connect \main_socbushandler_converted_interface_cyc $and$ls180.v:5833$1111_Y - connect \builder_libresocsim_converted_interface_cyc $and$ls180.v:5834$1112_Y - connect \builder_shared_err $or$ls180.v:5835$1117_Y - connect \builder_wait $and$ls180.v:5836$1120_Y - connect \builder_done $eq$ls180.v:5849$1138_Y - connect \builder_csrbank0_sel $eq$ls180.v:5850$1139_Y - connect \builder_csrbank0_reset0_r \builder_interface0_bank_bus_dat_w [0] - connect \builder_csrbank0_reset0_re $and$ls180.v:5852$1142_Y - connect \builder_csrbank0_reset0_we $and$ls180.v:5853$1146_Y - connect \builder_csrbank0_scratch3_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch3_re $and$ls180.v:5855$1149_Y - connect \builder_csrbank0_scratch3_we $and$ls180.v:5856$1153_Y - connect \builder_csrbank0_scratch2_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch2_re $and$ls180.v:5858$1156_Y - connect \builder_csrbank0_scratch2_we $and$ls180.v:5859$1160_Y - connect \builder_csrbank0_scratch1_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch1_re $and$ls180.v:5861$1163_Y - connect \builder_csrbank0_scratch1_we $and$ls180.v:5862$1167_Y - connect \builder_csrbank0_scratch0_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_scratch0_re $and$ls180.v:5864$1170_Y - connect \builder_csrbank0_scratch0_we $and$ls180.v:5865$1174_Y - connect \builder_csrbank0_bus_errors3_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors3_re $and$ls180.v:5867$1177_Y - connect \builder_csrbank0_bus_errors3_we $and$ls180.v:5868$1181_Y - connect \builder_csrbank0_bus_errors2_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors2_re $and$ls180.v:5870$1184_Y - connect \builder_csrbank0_bus_errors2_we $and$ls180.v:5871$1188_Y - connect \builder_csrbank0_bus_errors1_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors1_re $and$ls180.v:5873$1191_Y - connect \builder_csrbank0_bus_errors1_we $and$ls180.v:5874$1195_Y - connect \builder_csrbank0_bus_errors0_r \builder_interface0_bank_bus_dat_w - connect \builder_csrbank0_bus_errors0_re $and$ls180.v:5876$1198_Y - connect \builder_csrbank0_bus_errors0_we $and$ls180.v:5877$1202_Y - connect \builder_csrbank0_reset0_w \main_libresocsim_reset_storage - connect \builder_csrbank0_scratch3_w \main_libresocsim_scratch_storage [31:24] - connect \builder_csrbank0_scratch2_w \main_libresocsim_scratch_storage [23:16] - connect \builder_csrbank0_scratch1_w \main_libresocsim_scratch_storage [15:8] - connect \builder_csrbank0_scratch0_w \main_libresocsim_scratch_storage [7:0] - connect \builder_csrbank0_bus_errors3_w \main_libresocsim_bus_errors_status [31:24] - connect \builder_csrbank0_bus_errors2_w \main_libresocsim_bus_errors_status [23:16] - connect \builder_csrbank0_bus_errors1_w \main_libresocsim_bus_errors_status [15:8] - connect \builder_csrbank0_bus_errors0_w \main_libresocsim_bus_errors_status [7:0] - connect \main_libresocsim_bus_errors_we \builder_csrbank0_bus_errors0_we - connect \builder_csrbank1_sel $eq$ls180.v:5888$1203_Y - connect \builder_csrbank1_oe1_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_oe1_re $and$ls180.v:5890$1206_Y - connect \builder_csrbank1_oe1_we $and$ls180.v:5891$1210_Y - connect \builder_csrbank1_oe0_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_oe0_re $and$ls180.v:5893$1213_Y - connect \builder_csrbank1_oe0_we $and$ls180.v:5894$1217_Y - connect \builder_csrbank1_in1_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_in1_re $and$ls180.v:5896$1220_Y - connect \builder_csrbank1_in1_we $and$ls180.v:5897$1224_Y - connect \builder_csrbank1_in0_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_in0_re $and$ls180.v:5899$1227_Y - connect \builder_csrbank1_in0_we $and$ls180.v:5900$1231_Y - connect \builder_csrbank1_out1_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_out1_re $and$ls180.v:5902$1234_Y - connect \builder_csrbank1_out1_we $and$ls180.v:5903$1238_Y - connect \builder_csrbank1_out0_r \builder_interface1_bank_bus_dat_w - connect \builder_csrbank1_out0_re $and$ls180.v:5905$1241_Y - connect \builder_csrbank1_out0_we $and$ls180.v:5906$1245_Y - connect \builder_csrbank1_oe1_w \main_gpiotristateasic1_oe_storage [15:8] - connect \builder_csrbank1_oe0_w \main_gpiotristateasic1_oe_storage [7:0] - connect \builder_csrbank1_in1_w \main_gpiotristateasic1_status [15:8] - connect \builder_csrbank1_in0_w \main_gpiotristateasic1_status [7:0] - connect \main_gpiotristateasic1_we \builder_csrbank1_in0_we - connect \builder_csrbank1_out1_w \main_gpiotristateasic1_out_storage [15:8] - connect \builder_csrbank1_out0_w \main_gpiotristateasic1_out_storage [7:0] - connect \builder_csrbank2_sel $eq$ls180.v:5914$1246_Y - connect \builder_csrbank2_w0_r \builder_interface2_bank_bus_dat_w [2:0] - connect \builder_csrbank2_w0_re $and$ls180.v:5916$1249_Y - connect \builder_csrbank2_w0_we $and$ls180.v:5917$1253_Y - connect \builder_csrbank2_r_r \builder_interface2_bank_bus_dat_w [0] - connect \builder_csrbank2_r_re $and$ls180.v:5919$1256_Y - connect \builder_csrbank2_r_we $and$ls180.v:5920$1260_Y - connect \main_i2c_scl \main_i2c_storage [0] - connect \main_i2c_oe \main_i2c_storage [1] - connect \main_i2c_sda0 \main_i2c_storage [2] - connect \builder_csrbank2_w0_w \main_i2c_storage - connect \main_i2c_status \main_i2c_sda1 - connect \builder_csrbank2_r_w \main_i2c_status - connect \main_i2c_we \builder_csrbank2_r_we - connect \builder_csrbank3_sel $eq$ls180.v:5928$1261_Y - connect \builder_csrbank3_enable0_r \builder_interface3_bank_bus_dat_w [0] - connect \builder_csrbank3_enable0_re $and$ls180.v:5930$1264_Y - connect \builder_csrbank3_enable0_we $and$ls180.v:5931$1268_Y - connect \builder_csrbank3_width3_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width3_re $and$ls180.v:5933$1271_Y - connect \builder_csrbank3_width3_we $and$ls180.v:5934$1275_Y - connect \builder_csrbank3_width2_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width2_re $and$ls180.v:5936$1278_Y - connect \builder_csrbank3_width2_we $and$ls180.v:5937$1282_Y - connect \builder_csrbank3_width1_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width1_re $and$ls180.v:5939$1285_Y - connect \builder_csrbank3_width1_we $and$ls180.v:5940$1289_Y - connect \builder_csrbank3_width0_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_width0_re $and$ls180.v:5942$1292_Y - connect \builder_csrbank3_width0_we $and$ls180.v:5943$1296_Y - connect \builder_csrbank3_period3_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period3_re $and$ls180.v:5945$1299_Y - connect \builder_csrbank3_period3_we $and$ls180.v:5946$1303_Y - connect \builder_csrbank3_period2_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period2_re $and$ls180.v:5948$1306_Y - connect \builder_csrbank3_period2_we $and$ls180.v:5949$1310_Y - connect \builder_csrbank3_period1_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period1_re $and$ls180.v:5951$1313_Y - connect \builder_csrbank3_period1_we $and$ls180.v:5952$1317_Y - connect \builder_csrbank3_period0_r \builder_interface3_bank_bus_dat_w - connect \builder_csrbank3_period0_re $and$ls180.v:5954$1320_Y - connect \builder_csrbank3_period0_we $and$ls180.v:5955$1324_Y - connect \builder_csrbank3_enable0_w \main_pwm0_enable_storage - connect \builder_csrbank3_width3_w \main_pwm0_width_storage [31:24] - connect \builder_csrbank3_width2_w \main_pwm0_width_storage [23:16] - connect \builder_csrbank3_width1_w \main_pwm0_width_storage [15:8] - connect \builder_csrbank3_width0_w \main_pwm0_width_storage [7:0] - connect \builder_csrbank3_period3_w \main_pwm0_period_storage [31:24] - connect \builder_csrbank3_period2_w \main_pwm0_period_storage [23:16] - connect \builder_csrbank3_period1_w \main_pwm0_period_storage [15:8] - connect \builder_csrbank3_period0_w \main_pwm0_period_storage [7:0] - connect \builder_csrbank4_sel $eq$ls180.v:5965$1325_Y - connect \builder_csrbank4_enable0_r \builder_interface4_bank_bus_dat_w [0] - connect \builder_csrbank4_enable0_re $and$ls180.v:5967$1328_Y - connect \builder_csrbank4_enable0_we $and$ls180.v:5968$1332_Y - connect \builder_csrbank4_width3_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_width3_re $and$ls180.v:5970$1335_Y - connect \builder_csrbank4_width3_we $and$ls180.v:5971$1339_Y - connect \builder_csrbank4_width2_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_width2_re $and$ls180.v:5973$1342_Y - connect \builder_csrbank4_width2_we $and$ls180.v:5974$1346_Y - connect \builder_csrbank4_width1_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_width1_re $and$ls180.v:5976$1349_Y - connect \builder_csrbank4_width1_we $and$ls180.v:5977$1353_Y - connect \builder_csrbank4_width0_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_width0_re $and$ls180.v:5979$1356_Y - connect \builder_csrbank4_width0_we $and$ls180.v:5980$1360_Y - connect \builder_csrbank4_period3_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_period3_re $and$ls180.v:5982$1363_Y - connect \builder_csrbank4_period3_we $and$ls180.v:5983$1367_Y - connect \builder_csrbank4_period2_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_period2_re $and$ls180.v:5985$1370_Y - connect \builder_csrbank4_period2_we $and$ls180.v:5986$1374_Y - connect \builder_csrbank4_period1_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_period1_re $and$ls180.v:5988$1377_Y - connect \builder_csrbank4_period1_we $and$ls180.v:5989$1381_Y - connect \builder_csrbank4_period0_r \builder_interface4_bank_bus_dat_w - connect \builder_csrbank4_period0_re $and$ls180.v:5991$1384_Y - connect \builder_csrbank4_period0_we $and$ls180.v:5992$1388_Y - connect \builder_csrbank4_enable0_w \main_pwm1_enable_storage - connect \builder_csrbank4_width3_w \main_pwm1_width_storage [31:24] - connect \builder_csrbank4_width2_w \main_pwm1_width_storage [23:16] - connect \builder_csrbank4_width1_w \main_pwm1_width_storage [15:8] - connect \builder_csrbank4_width0_w \main_pwm1_width_storage [7:0] - connect \builder_csrbank4_period3_w \main_pwm1_period_storage [31:24] - connect \builder_csrbank4_period2_w \main_pwm1_period_storage [23:16] - connect \builder_csrbank4_period1_w \main_pwm1_period_storage [15:8] - connect \builder_csrbank4_period0_w \main_pwm1_period_storage [7:0] - connect \builder_csrbank5_sel $eq$ls180.v:6002$1389_Y - connect \builder_csrbank5_dma_base7_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base7_re $and$ls180.v:6004$1392_Y - connect \builder_csrbank5_dma_base7_we $and$ls180.v:6005$1396_Y - connect \builder_csrbank5_dma_base6_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base6_re $and$ls180.v:6007$1399_Y - connect \builder_csrbank5_dma_base6_we $and$ls180.v:6008$1403_Y - connect \builder_csrbank5_dma_base5_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base5_re $and$ls180.v:6010$1406_Y - connect \builder_csrbank5_dma_base5_we $and$ls180.v:6011$1410_Y - connect \builder_csrbank5_dma_base4_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base4_re $and$ls180.v:6013$1413_Y - connect \builder_csrbank5_dma_base4_we $and$ls180.v:6014$1417_Y - connect \builder_csrbank5_dma_base3_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base3_re $and$ls180.v:6016$1420_Y - connect \builder_csrbank5_dma_base3_we $and$ls180.v:6017$1424_Y - connect \builder_csrbank5_dma_base2_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base2_re $and$ls180.v:6019$1427_Y - connect \builder_csrbank5_dma_base2_we $and$ls180.v:6020$1431_Y - connect \builder_csrbank5_dma_base1_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base1_re $and$ls180.v:6022$1434_Y - connect \builder_csrbank5_dma_base1_we $and$ls180.v:6023$1438_Y - connect \builder_csrbank5_dma_base0_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_base0_re $and$ls180.v:6025$1441_Y - connect \builder_csrbank5_dma_base0_we $and$ls180.v:6026$1445_Y - connect \builder_csrbank5_dma_length3_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length3_re $and$ls180.v:6028$1448_Y - connect \builder_csrbank5_dma_length3_we $and$ls180.v:6029$1452_Y - connect \builder_csrbank5_dma_length2_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length2_re $and$ls180.v:6031$1455_Y - connect \builder_csrbank5_dma_length2_we $and$ls180.v:6032$1459_Y - connect \builder_csrbank5_dma_length1_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length1_re $and$ls180.v:6034$1462_Y - connect \builder_csrbank5_dma_length1_we $and$ls180.v:6035$1466_Y - connect \builder_csrbank5_dma_length0_r \builder_interface5_bank_bus_dat_w - connect \builder_csrbank5_dma_length0_re $and$ls180.v:6037$1469_Y - connect \builder_csrbank5_dma_length0_we $and$ls180.v:6038$1473_Y - connect \builder_csrbank5_dma_enable0_r \builder_interface5_bank_bus_dat_w [0] - connect \builder_csrbank5_dma_enable0_re $and$ls180.v:6040$1476_Y - connect \builder_csrbank5_dma_enable0_we $and$ls180.v:6041$1480_Y - connect \builder_csrbank5_dma_done_r \builder_interface5_bank_bus_dat_w [0] - connect \builder_csrbank5_dma_done_re $and$ls180.v:6043$1483_Y - connect \builder_csrbank5_dma_done_we $and$ls180.v:6044$1487_Y - connect \builder_csrbank5_dma_loop0_r \builder_interface5_bank_bus_dat_w [0] - connect \builder_csrbank5_dma_loop0_re $and$ls180.v:6046$1490_Y - connect \builder_csrbank5_dma_loop0_we $and$ls180.v:6047$1494_Y - connect \builder_csrbank5_dma_base7_w \main_sdblock2mem_wishbonedmawriter_base_storage [63:56] - connect \builder_csrbank5_dma_base6_w \main_sdblock2mem_wishbonedmawriter_base_storage [55:48] - connect \builder_csrbank5_dma_base5_w \main_sdblock2mem_wishbonedmawriter_base_storage [47:40] - connect \builder_csrbank5_dma_base4_w \main_sdblock2mem_wishbonedmawriter_base_storage [39:32] - connect \builder_csrbank5_dma_base3_w \main_sdblock2mem_wishbonedmawriter_base_storage [31:24] - connect \builder_csrbank5_dma_base2_w \main_sdblock2mem_wishbonedmawriter_base_storage [23:16] - connect \builder_csrbank5_dma_base1_w \main_sdblock2mem_wishbonedmawriter_base_storage [15:8] - connect \builder_csrbank5_dma_base0_w \main_sdblock2mem_wishbonedmawriter_base_storage [7:0] - connect \builder_csrbank5_dma_length3_w \main_sdblock2mem_wishbonedmawriter_length_storage [31:24] - connect \builder_csrbank5_dma_length2_w \main_sdblock2mem_wishbonedmawriter_length_storage [23:16] - connect \builder_csrbank5_dma_length1_w \main_sdblock2mem_wishbonedmawriter_length_storage [15:8] - connect \builder_csrbank5_dma_length0_w \main_sdblock2mem_wishbonedmawriter_length_storage [7:0] - connect \builder_csrbank5_dma_enable0_w \main_sdblock2mem_wishbonedmawriter_enable_storage - connect \builder_csrbank5_dma_done_w \main_sdblock2mem_wishbonedmawriter_status - connect \main_sdblock2mem_wishbonedmawriter_we \builder_csrbank5_dma_done_we - connect \builder_csrbank5_dma_loop0_w \main_sdblock2mem_wishbonedmawriter_loop_storage - connect \builder_csrbank6_sel $eq$ls180.v:6064$1495_Y - connect \builder_csrbank6_cmd_argument3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_argument3_re $and$ls180.v:6066$1498_Y - connect \builder_csrbank6_cmd_argument3_we $and$ls180.v:6067$1502_Y - connect \builder_csrbank6_cmd_argument2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_argument2_re $and$ls180.v:6069$1505_Y - connect \builder_csrbank6_cmd_argument2_we $and$ls180.v:6070$1509_Y - connect \builder_csrbank6_cmd_argument1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_argument1_re $and$ls180.v:6072$1512_Y - connect \builder_csrbank6_cmd_argument1_we $and$ls180.v:6073$1516_Y - connect \builder_csrbank6_cmd_argument0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_argument0_re $and$ls180.v:6075$1519_Y - connect \builder_csrbank6_cmd_argument0_we $and$ls180.v:6076$1523_Y - connect \builder_csrbank6_cmd_command3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_command3_re $and$ls180.v:6078$1526_Y - connect \builder_csrbank6_cmd_command3_we $and$ls180.v:6079$1530_Y - connect \builder_csrbank6_cmd_command2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_command2_re $and$ls180.v:6081$1533_Y - connect \builder_csrbank6_cmd_command2_we $and$ls180.v:6082$1537_Y - connect \builder_csrbank6_cmd_command1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_command1_re $and$ls180.v:6084$1540_Y - connect \builder_csrbank6_cmd_command1_we $and$ls180.v:6085$1544_Y - connect \builder_csrbank6_cmd_command0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_command0_re $and$ls180.v:6087$1547_Y - connect \builder_csrbank6_cmd_command0_we $and$ls180.v:6088$1551_Y - connect \main_sdcore_cmd_send_r \builder_interface6_bank_bus_dat_w [0] - connect \main_sdcore_cmd_send_re $and$ls180.v:6090$1554_Y - connect \main_sdcore_cmd_send_we $and$ls180.v:6091$1558_Y - connect \builder_csrbank6_cmd_response15_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response15_re $and$ls180.v:6093$1561_Y - connect \builder_csrbank6_cmd_response15_we $and$ls180.v:6094$1565_Y - connect \builder_csrbank6_cmd_response14_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response14_re $and$ls180.v:6096$1568_Y - connect \builder_csrbank6_cmd_response14_we $and$ls180.v:6097$1572_Y - connect \builder_csrbank6_cmd_response13_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response13_re $and$ls180.v:6099$1575_Y - connect \builder_csrbank6_cmd_response13_we $and$ls180.v:6100$1579_Y - connect \builder_csrbank6_cmd_response12_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response12_re $and$ls180.v:6102$1582_Y - connect \builder_csrbank6_cmd_response12_we $and$ls180.v:6103$1586_Y - connect \builder_csrbank6_cmd_response11_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response11_re $and$ls180.v:6105$1589_Y - connect \builder_csrbank6_cmd_response11_we $and$ls180.v:6106$1593_Y - connect \builder_csrbank6_cmd_response10_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response10_re $and$ls180.v:6108$1596_Y - connect \builder_csrbank6_cmd_response10_we $and$ls180.v:6109$1600_Y - connect \builder_csrbank6_cmd_response9_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response9_re $and$ls180.v:6111$1603_Y - connect \builder_csrbank6_cmd_response9_we $and$ls180.v:6112$1607_Y - connect \builder_csrbank6_cmd_response8_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response8_re $and$ls180.v:6114$1610_Y - connect \builder_csrbank6_cmd_response8_we $and$ls180.v:6115$1614_Y - connect \builder_csrbank6_cmd_response7_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response7_re $and$ls180.v:6117$1617_Y - connect \builder_csrbank6_cmd_response7_we $and$ls180.v:6118$1621_Y - connect \builder_csrbank6_cmd_response6_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response6_re $and$ls180.v:6120$1624_Y - connect \builder_csrbank6_cmd_response6_we $and$ls180.v:6121$1628_Y - connect \builder_csrbank6_cmd_response5_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response5_re $and$ls180.v:6123$1631_Y - connect \builder_csrbank6_cmd_response5_we $and$ls180.v:6124$1635_Y - connect \builder_csrbank6_cmd_response4_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response4_re $and$ls180.v:6126$1638_Y - connect \builder_csrbank6_cmd_response4_we $and$ls180.v:6127$1642_Y - connect \builder_csrbank6_cmd_response3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response3_re $and$ls180.v:6129$1645_Y - connect \builder_csrbank6_cmd_response3_we $and$ls180.v:6130$1649_Y - connect \builder_csrbank6_cmd_response2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response2_re $and$ls180.v:6132$1652_Y - connect \builder_csrbank6_cmd_response2_we $and$ls180.v:6133$1656_Y - connect \builder_csrbank6_cmd_response1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response1_re $and$ls180.v:6135$1659_Y - connect \builder_csrbank6_cmd_response1_we $and$ls180.v:6136$1663_Y - connect \builder_csrbank6_cmd_response0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_cmd_response0_re $and$ls180.v:6138$1666_Y - connect \builder_csrbank6_cmd_response0_we $and$ls180.v:6139$1670_Y - connect \builder_csrbank6_cmd_event_r \builder_interface6_bank_bus_dat_w [3:0] - connect \builder_csrbank6_cmd_event_re $and$ls180.v:6141$1673_Y - connect \builder_csrbank6_cmd_event_we $and$ls180.v:6142$1677_Y - connect \builder_csrbank6_data_event_r \builder_interface6_bank_bus_dat_w [3:0] - connect \builder_csrbank6_data_event_re $and$ls180.v:6144$1680_Y - connect \builder_csrbank6_data_event_we $and$ls180.v:6145$1684_Y - connect \builder_csrbank6_block_length1_r \builder_interface6_bank_bus_dat_w [1:0] - connect \builder_csrbank6_block_length1_re $and$ls180.v:6147$1687_Y - connect \builder_csrbank6_block_length1_we $and$ls180.v:6148$1691_Y - connect \builder_csrbank6_block_length0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_length0_re $and$ls180.v:6150$1694_Y - connect \builder_csrbank6_block_length0_we $and$ls180.v:6151$1698_Y - connect \builder_csrbank6_block_count3_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_count3_re $and$ls180.v:6153$1701_Y - connect \builder_csrbank6_block_count3_we $and$ls180.v:6154$1705_Y - connect \builder_csrbank6_block_count2_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_count2_re $and$ls180.v:6156$1708_Y - connect \builder_csrbank6_block_count2_we $and$ls180.v:6157$1712_Y - connect \builder_csrbank6_block_count1_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_count1_re $and$ls180.v:6159$1715_Y - connect \builder_csrbank6_block_count1_we $and$ls180.v:6160$1719_Y - connect \builder_csrbank6_block_count0_r \builder_interface6_bank_bus_dat_w - connect \builder_csrbank6_block_count0_re $and$ls180.v:6162$1722_Y - connect \builder_csrbank6_block_count0_we $and$ls180.v:6163$1726_Y - connect \builder_csrbank6_cmd_argument3_w \main_sdcore_cmd_argument_storage [31:24] - connect \builder_csrbank6_cmd_argument2_w \main_sdcore_cmd_argument_storage [23:16] - connect \builder_csrbank6_cmd_argument1_w \main_sdcore_cmd_argument_storage [15:8] - connect \builder_csrbank6_cmd_argument0_w \main_sdcore_cmd_argument_storage [7:0] - connect \builder_csrbank6_cmd_command3_w \main_sdcore_cmd_command_storage [31:24] - connect \builder_csrbank6_cmd_command2_w \main_sdcore_cmd_command_storage [23:16] - connect \builder_csrbank6_cmd_command1_w \main_sdcore_cmd_command_storage [15:8] - connect \builder_csrbank6_cmd_command0_w \main_sdcore_cmd_command_storage [7:0] - connect \builder_csrbank6_cmd_response15_w \main_sdcore_cmd_response_status [127:120] - connect \builder_csrbank6_cmd_response14_w \main_sdcore_cmd_response_status [119:112] - connect \builder_csrbank6_cmd_response13_w \main_sdcore_cmd_response_status [111:104] - connect \builder_csrbank6_cmd_response12_w \main_sdcore_cmd_response_status [103:96] - connect \builder_csrbank6_cmd_response11_w \main_sdcore_cmd_response_status [95:88] - connect \builder_csrbank6_cmd_response10_w \main_sdcore_cmd_response_status [87:80] - connect \builder_csrbank6_cmd_response9_w \main_sdcore_cmd_response_status [79:72] - connect \builder_csrbank6_cmd_response8_w \main_sdcore_cmd_response_status [71:64] - connect \builder_csrbank6_cmd_response7_w \main_sdcore_cmd_response_status [63:56] - connect \builder_csrbank6_cmd_response6_w \main_sdcore_cmd_response_status [55:48] - connect \builder_csrbank6_cmd_response5_w \main_sdcore_cmd_response_status [47:40] - connect \builder_csrbank6_cmd_response4_w \main_sdcore_cmd_response_status [39:32] - connect \builder_csrbank6_cmd_response3_w \main_sdcore_cmd_response_status [31:24] - connect \builder_csrbank6_cmd_response2_w \main_sdcore_cmd_response_status [23:16] - connect \builder_csrbank6_cmd_response1_w \main_sdcore_cmd_response_status [15:8] - connect \builder_csrbank6_cmd_response0_w \main_sdcore_cmd_response_status [7:0] - connect \main_sdcore_cmd_response_we \builder_csrbank6_cmd_response0_we - connect \builder_csrbank6_cmd_event_w \main_sdcore_cmd_event_status - connect \main_sdcore_cmd_event_we \builder_csrbank6_cmd_event_we - connect \builder_csrbank6_data_event_w \main_sdcore_data_event_status - connect \main_sdcore_data_event_we \builder_csrbank6_data_event_we - connect \builder_csrbank6_block_length1_w \main_sdcore_block_length_storage [9:8] - connect \builder_csrbank6_block_length0_w \main_sdcore_block_length_storage [7:0] - connect \builder_csrbank6_block_count3_w \main_sdcore_block_count_storage [31:24] - connect \builder_csrbank6_block_count2_w \main_sdcore_block_count_storage [23:16] - connect \builder_csrbank6_block_count1_w \main_sdcore_block_count_storage [15:8] - connect \builder_csrbank6_block_count0_w \main_sdcore_block_count_storage [7:0] - connect \builder_csrbank7_sel $eq$ls180.v:6199$1727_Y - connect \builder_csrbank7_dma_base7_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base7_re $and$ls180.v:6201$1730_Y - connect \builder_csrbank7_dma_base7_we $and$ls180.v:6202$1734_Y - connect \builder_csrbank7_dma_base6_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base6_re $and$ls180.v:6204$1737_Y - connect \builder_csrbank7_dma_base6_we $and$ls180.v:6205$1741_Y - connect \builder_csrbank7_dma_base5_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base5_re $and$ls180.v:6207$1744_Y - connect \builder_csrbank7_dma_base5_we $and$ls180.v:6208$1748_Y - connect \builder_csrbank7_dma_base4_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base4_re $and$ls180.v:6210$1751_Y - connect \builder_csrbank7_dma_base4_we $and$ls180.v:6211$1755_Y - connect \builder_csrbank7_dma_base3_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base3_re $and$ls180.v:6213$1758_Y - connect \builder_csrbank7_dma_base3_we $and$ls180.v:6214$1762_Y - connect \builder_csrbank7_dma_base2_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base2_re $and$ls180.v:6216$1765_Y - connect \builder_csrbank7_dma_base2_we $and$ls180.v:6217$1769_Y - connect \builder_csrbank7_dma_base1_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base1_re $and$ls180.v:6219$1772_Y - connect \builder_csrbank7_dma_base1_we $and$ls180.v:6220$1776_Y - connect \builder_csrbank7_dma_base0_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_base0_re $and$ls180.v:6222$1779_Y - connect \builder_csrbank7_dma_base0_we $and$ls180.v:6223$1783_Y - connect \builder_csrbank7_dma_length3_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_length3_re $and$ls180.v:6225$1786_Y - connect \builder_csrbank7_dma_length3_we $and$ls180.v:6226$1790_Y - connect \builder_csrbank7_dma_length2_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_length2_re $and$ls180.v:6228$1793_Y - connect \builder_csrbank7_dma_length2_we $and$ls180.v:6229$1797_Y - connect \builder_csrbank7_dma_length1_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_length1_re $and$ls180.v:6231$1800_Y - connect \builder_csrbank7_dma_length1_we $and$ls180.v:6232$1804_Y - connect \builder_csrbank7_dma_length0_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_length0_re $and$ls180.v:6234$1807_Y - connect \builder_csrbank7_dma_length0_we $and$ls180.v:6235$1811_Y - connect \builder_csrbank7_dma_enable0_r \builder_interface7_bank_bus_dat_w [0] - connect \builder_csrbank7_dma_enable0_re $and$ls180.v:6237$1814_Y - connect \builder_csrbank7_dma_enable0_we $and$ls180.v:6238$1818_Y - connect \builder_csrbank7_dma_done_r \builder_interface7_bank_bus_dat_w [0] - connect \builder_csrbank7_dma_done_re $and$ls180.v:6240$1821_Y - connect \builder_csrbank7_dma_done_we $and$ls180.v:6241$1825_Y - connect \builder_csrbank7_dma_loop0_r \builder_interface7_bank_bus_dat_w [0] - connect \builder_csrbank7_dma_loop0_re $and$ls180.v:6243$1828_Y - connect \builder_csrbank7_dma_loop0_we $and$ls180.v:6244$1832_Y - connect \builder_csrbank7_dma_offset3_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_offset3_re $and$ls180.v:6246$1835_Y - connect \builder_csrbank7_dma_offset3_we $and$ls180.v:6247$1839_Y - connect \builder_csrbank7_dma_offset2_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_offset2_re $and$ls180.v:6249$1842_Y - connect \builder_csrbank7_dma_offset2_we $and$ls180.v:6250$1846_Y - connect \builder_csrbank7_dma_offset1_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_offset1_re $and$ls180.v:6252$1849_Y - connect \builder_csrbank7_dma_offset1_we $and$ls180.v:6253$1853_Y - connect \builder_csrbank7_dma_offset0_r \builder_interface7_bank_bus_dat_w - connect \builder_csrbank7_dma_offset0_re $and$ls180.v:6255$1856_Y - connect \builder_csrbank7_dma_offset0_we $and$ls180.v:6256$1860_Y - connect \builder_csrbank7_dma_base7_w \main_sdmem2block_dma_base_storage [63:56] - connect \builder_csrbank7_dma_base6_w \main_sdmem2block_dma_base_storage [55:48] - connect \builder_csrbank7_dma_base5_w \main_sdmem2block_dma_base_storage [47:40] - connect \builder_csrbank7_dma_base4_w \main_sdmem2block_dma_base_storage [39:32] - connect \builder_csrbank7_dma_base3_w \main_sdmem2block_dma_base_storage [31:24] - connect \builder_csrbank7_dma_base2_w \main_sdmem2block_dma_base_storage [23:16] - connect \builder_csrbank7_dma_base1_w \main_sdmem2block_dma_base_storage [15:8] - connect \builder_csrbank7_dma_base0_w \main_sdmem2block_dma_base_storage [7:0] - connect \builder_csrbank7_dma_length3_w \main_sdmem2block_dma_length_storage [31:24] - connect \builder_csrbank7_dma_length2_w \main_sdmem2block_dma_length_storage [23:16] - connect \builder_csrbank7_dma_length1_w \main_sdmem2block_dma_length_storage [15:8] - connect \builder_csrbank7_dma_length0_w \main_sdmem2block_dma_length_storage [7:0] - connect \builder_csrbank7_dma_enable0_w \main_sdmem2block_dma_enable_storage - connect \builder_csrbank7_dma_done_w \main_sdmem2block_dma_done_status - connect \main_sdmem2block_dma_done_we \builder_csrbank7_dma_done_we - connect \builder_csrbank7_dma_loop0_w \main_sdmem2block_dma_loop_storage - connect \builder_csrbank7_dma_offset3_w \main_sdmem2block_dma_offset_status [31:24] - connect \builder_csrbank7_dma_offset2_w \main_sdmem2block_dma_offset_status [23:16] - connect \builder_csrbank7_dma_offset1_w \main_sdmem2block_dma_offset_status [15:8] - connect \builder_csrbank7_dma_offset0_w \main_sdmem2block_dma_offset_status [7:0] - connect \main_sdmem2block_dma_offset_we \builder_csrbank7_dma_offset0_we - connect \builder_csrbank8_sel $eq$ls180.v:6278$1861_Y - connect \builder_csrbank8_card_detect_r \builder_interface8_bank_bus_dat_w [0] - connect \builder_csrbank8_card_detect_re $and$ls180.v:6280$1864_Y - connect \builder_csrbank8_card_detect_we $and$ls180.v:6281$1868_Y - connect \builder_csrbank8_clocker_divider1_r \builder_interface8_bank_bus_dat_w [0] - connect \builder_csrbank8_clocker_divider1_re $and$ls180.v:6283$1871_Y - connect \builder_csrbank8_clocker_divider1_we $and$ls180.v:6284$1875_Y - connect \builder_csrbank8_clocker_divider0_r \builder_interface8_bank_bus_dat_w - connect \builder_csrbank8_clocker_divider0_re $and$ls180.v:6286$1878_Y - connect \builder_csrbank8_clocker_divider0_we $and$ls180.v:6287$1882_Y - connect \main_sdphy_init_initialize_r \builder_interface8_bank_bus_dat_w [0] - connect \main_sdphy_init_initialize_re $and$ls180.v:6289$1885_Y - connect \main_sdphy_init_initialize_we $and$ls180.v:6290$1889_Y - connect \builder_csrbank8_card_detect_w \main_sdphy_status - connect \main_sdphy_we \builder_csrbank8_card_detect_we - connect \builder_csrbank8_clocker_divider1_w \main_sdphy_clocker_storage [8] - connect \builder_csrbank8_clocker_divider0_w \main_sdphy_clocker_storage [7:0] - connect \builder_csrbank9_sel $eq$ls180.v:6295$1890_Y - connect \builder_csrbank9_dfii_control0_r \builder_interface9_bank_bus_dat_w [3:0] - connect \builder_csrbank9_dfii_control0_re $and$ls180.v:6297$1893_Y - connect \builder_csrbank9_dfii_control0_we $and$ls180.v:6298$1897_Y - connect \builder_csrbank9_dfii_pi0_command0_r \builder_interface9_bank_bus_dat_w [5:0] - connect \builder_csrbank9_dfii_pi0_command0_re $and$ls180.v:6300$1900_Y - connect \builder_csrbank9_dfii_pi0_command0_we $and$ls180.v:6301$1904_Y - connect \main_sdram_command_issue_r \builder_interface9_bank_bus_dat_w [0] - connect \main_sdram_command_issue_re $and$ls180.v:6303$1907_Y - connect \main_sdram_command_issue_we $and$ls180.v:6304$1911_Y - connect \builder_csrbank9_dfii_pi0_address1_r \builder_interface9_bank_bus_dat_w [4:0] - connect \builder_csrbank9_dfii_pi0_address1_re $and$ls180.v:6306$1914_Y - connect \builder_csrbank9_dfii_pi0_address1_we $and$ls180.v:6307$1918_Y - connect \builder_csrbank9_dfii_pi0_address0_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_address0_re $and$ls180.v:6309$1921_Y - connect \builder_csrbank9_dfii_pi0_address0_we $and$ls180.v:6310$1925_Y - connect \builder_csrbank9_dfii_pi0_baddress0_r \builder_interface9_bank_bus_dat_w [1:0] - connect \builder_csrbank9_dfii_pi0_baddress0_re $and$ls180.v:6312$1928_Y - connect \builder_csrbank9_dfii_pi0_baddress0_we $and$ls180.v:6313$1932_Y - connect \builder_csrbank9_dfii_pi0_wrdata1_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_wrdata1_re $and$ls180.v:6315$1935_Y - connect \builder_csrbank9_dfii_pi0_wrdata1_we $and$ls180.v:6316$1939_Y - connect \builder_csrbank9_dfii_pi0_wrdata0_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_wrdata0_re $and$ls180.v:6318$1942_Y - connect \builder_csrbank9_dfii_pi0_wrdata0_we $and$ls180.v:6319$1946_Y - connect \builder_csrbank9_dfii_pi0_rddata1_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_rddata1_re $and$ls180.v:6321$1949_Y - connect \builder_csrbank9_dfii_pi0_rddata1_we $and$ls180.v:6322$1953_Y - connect \builder_csrbank9_dfii_pi0_rddata0_r \builder_interface9_bank_bus_dat_w - connect \builder_csrbank9_dfii_pi0_rddata0_re $and$ls180.v:6324$1956_Y - connect \builder_csrbank9_dfii_pi0_rddata0_we $and$ls180.v:6325$1960_Y - connect \main_sdram_sel \main_sdram_storage [0] - connect \main_sdram_cke \main_sdram_storage [1] - connect \main_sdram_odt \main_sdram_storage [2] - connect \main_sdram_reset_n \main_sdram_storage [3] - connect \builder_csrbank9_dfii_control0_w \main_sdram_storage - connect \builder_csrbank9_dfii_pi0_command0_w \main_sdram_command_storage - connect \builder_csrbank9_dfii_pi0_address1_w \main_sdram_address_storage [12:8] - connect \builder_csrbank9_dfii_pi0_address0_w \main_sdram_address_storage [7:0] - connect \builder_csrbank9_dfii_pi0_baddress0_w \main_sdram_baddress_storage - connect \builder_csrbank9_dfii_pi0_wrdata1_w \main_sdram_wrdata_storage [15:8] - connect \builder_csrbank9_dfii_pi0_wrdata0_w \main_sdram_wrdata_storage [7:0] - connect \builder_csrbank9_dfii_pi0_rddata1_w \main_sdram_status [15:8] - connect \builder_csrbank9_dfii_pi0_rddata0_w \main_sdram_status [7:0] - connect \main_sdram_we \builder_csrbank9_dfii_pi0_rddata0_we - connect \builder_csrbank10_sel $eq$ls180.v:6340$1961_Y - connect \builder_csrbank10_control1_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_control1_re $and$ls180.v:6342$1964_Y - connect \builder_csrbank10_control1_we $and$ls180.v:6343$1968_Y - connect \builder_csrbank10_control0_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_control0_re $and$ls180.v:6345$1971_Y - connect \builder_csrbank10_control0_we $and$ls180.v:6346$1975_Y - connect \builder_csrbank10_status_r \builder_interface10_bank_bus_dat_w [0] - connect \builder_csrbank10_status_re $and$ls180.v:6348$1978_Y - connect \builder_csrbank10_status_we $and$ls180.v:6349$1982_Y - connect \builder_csrbank10_mosi0_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_mosi0_re $and$ls180.v:6351$1985_Y - connect \builder_csrbank10_mosi0_we $and$ls180.v:6352$1989_Y - connect \builder_csrbank10_miso_r \builder_interface10_bank_bus_dat_w - connect \builder_csrbank10_miso_re $and$ls180.v:6354$1992_Y - connect \builder_csrbank10_miso_we $and$ls180.v:6355$1996_Y - connect \builder_csrbank10_cs0_r \builder_interface10_bank_bus_dat_w [0] - connect \builder_csrbank10_cs0_re $and$ls180.v:6357$1999_Y - connect \builder_csrbank10_cs0_we $and$ls180.v:6358$2003_Y - connect \builder_csrbank10_loopback0_r \builder_interface10_bank_bus_dat_w [0] - connect \builder_csrbank10_loopback0_re $and$ls180.v:6360$2006_Y - connect \builder_csrbank10_loopback0_we $and$ls180.v:6361$2010_Y - connect \main_spimaster10_length \main_spimaster11_storage [15:8] - connect \builder_csrbank10_control1_w \main_spimaster11_storage [15:8] - connect \builder_csrbank10_control0_w \main_spimaster11_storage [7:0] - connect \main_spimaster14_status \main_spimaster13_done - connect \builder_csrbank10_status_w \main_spimaster14_status - connect \main_spimaster15_we \builder_csrbank10_status_we - connect \builder_csrbank10_mosi0_w \main_spimaster16_storage - connect \builder_csrbank10_miso_w \main_spimaster18_status - connect \main_spimaster19_we \builder_csrbank10_miso_we - connect \main_spimaster20_sel \main_spimaster21_storage - connect \builder_csrbank10_cs0_w \main_spimaster21_storage - connect \builder_csrbank10_loopback0_w \main_spimaster23_storage - connect \builder_csrbank11_sel $eq$ls180.v:6380$2012_Y - connect \builder_csrbank11_control1_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_control1_re $and$ls180.v:6382$2015_Y - connect \builder_csrbank11_control1_we $and$ls180.v:6383$2019_Y - connect \builder_csrbank11_control0_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_control0_re $and$ls180.v:6385$2022_Y - connect \builder_csrbank11_control0_we $and$ls180.v:6386$2026_Y - connect \builder_csrbank11_status_r \builder_interface11_bank_bus_dat_w [0] - connect \builder_csrbank11_status_re $and$ls180.v:6388$2029_Y - connect \builder_csrbank11_status_we $and$ls180.v:6389$2033_Y - connect \builder_csrbank11_mosi0_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_mosi0_re $and$ls180.v:6391$2036_Y - connect \builder_csrbank11_mosi0_we $and$ls180.v:6392$2040_Y - connect \builder_csrbank11_miso_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_miso_re $and$ls180.v:6394$2043_Y - connect \builder_csrbank11_miso_we $and$ls180.v:6395$2047_Y - connect \builder_csrbank11_cs0_r \builder_interface11_bank_bus_dat_w [0] - connect \builder_csrbank11_cs0_re $and$ls180.v:6397$2050_Y - connect \builder_csrbank11_cs0_we $and$ls180.v:6398$2054_Y - connect \builder_csrbank11_loopback0_r \builder_interface11_bank_bus_dat_w [0] - connect \builder_csrbank11_loopback0_re $and$ls180.v:6400$2057_Y - connect \builder_csrbank11_loopback0_we $and$ls180.v:6401$2061_Y - connect \builder_csrbank11_clk_divider1_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_clk_divider1_re $and$ls180.v:6403$2064_Y - connect \builder_csrbank11_clk_divider1_we $and$ls180.v:6404$2068_Y - connect \builder_csrbank11_clk_divider0_r \builder_interface11_bank_bus_dat_w - connect \builder_csrbank11_clk_divider0_re $and$ls180.v:6406$2071_Y - connect \builder_csrbank11_clk_divider0_we $and$ls180.v:6407$2075_Y - connect \main_spisdcard_length1 \main_spisdcard_control_storage [15:8] - connect \builder_csrbank11_control1_w \main_spisdcard_control_storage [15:8] - connect \builder_csrbank11_control0_w \main_spisdcard_control_storage [7:0] - connect \main_spisdcard_status_status \main_spisdcard_done1 - connect \builder_csrbank11_status_w \main_spisdcard_status_status - connect \main_spisdcard_status_we \builder_csrbank11_status_we - connect \builder_csrbank11_mosi0_w \main_spisdcard_mosi_storage - connect \builder_csrbank11_miso_w \main_spisdcard_miso_status - connect \main_spisdcard_miso_we \builder_csrbank11_miso_we - connect \main_spisdcard_sel \main_spisdcard_cs_storage - connect \builder_csrbank11_cs0_w \main_spisdcard_cs_storage - connect \builder_csrbank11_loopback0_w \main_spisdcard_loopback_storage - connect \builder_csrbank11_clk_divider1_w \main_spimaster1_storage [15:8] - connect \builder_csrbank11_clk_divider0_w \main_spimaster1_storage [7:0] - connect \builder_csrbank12_sel $eq$ls180.v:6428$2077_Y - connect \builder_csrbank12_load3_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_load3_re $and$ls180.v:6430$2080_Y - connect \builder_csrbank12_load3_we $and$ls180.v:6431$2084_Y - connect \builder_csrbank12_load2_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_load2_re $and$ls180.v:6433$2087_Y - connect \builder_csrbank12_load2_we $and$ls180.v:6434$2091_Y - connect \builder_csrbank12_load1_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_load1_re $and$ls180.v:6436$2094_Y - connect \builder_csrbank12_load1_we $and$ls180.v:6437$2098_Y - connect \builder_csrbank12_load0_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_load0_re $and$ls180.v:6439$2101_Y - connect \builder_csrbank12_load0_we $and$ls180.v:6440$2105_Y - connect \builder_csrbank12_reload3_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_reload3_re $and$ls180.v:6442$2108_Y - connect \builder_csrbank12_reload3_we $and$ls180.v:6443$2112_Y - connect \builder_csrbank12_reload2_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_reload2_re $and$ls180.v:6445$2115_Y - connect \builder_csrbank12_reload2_we $and$ls180.v:6446$2119_Y - connect \builder_csrbank12_reload1_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_reload1_re $and$ls180.v:6448$2122_Y - connect \builder_csrbank12_reload1_we $and$ls180.v:6449$2126_Y - connect \builder_csrbank12_reload0_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_reload0_re $and$ls180.v:6451$2129_Y - connect \builder_csrbank12_reload0_we $and$ls180.v:6452$2133_Y - connect \builder_csrbank12_en0_r \builder_interface12_bank_bus_dat_w [0] - connect \builder_csrbank12_en0_re $and$ls180.v:6454$2136_Y - connect \builder_csrbank12_en0_we $and$ls180.v:6455$2140_Y - connect \builder_csrbank12_update_value0_r \builder_interface12_bank_bus_dat_w [0] - connect \builder_csrbank12_update_value0_re $and$ls180.v:6457$2143_Y - connect \builder_csrbank12_update_value0_we $and$ls180.v:6458$2147_Y - connect \builder_csrbank12_value3_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_value3_re $and$ls180.v:6460$2150_Y - connect \builder_csrbank12_value3_we $and$ls180.v:6461$2154_Y - connect \builder_csrbank12_value2_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_value2_re $and$ls180.v:6463$2157_Y - connect \builder_csrbank12_value2_we $and$ls180.v:6464$2161_Y - connect \builder_csrbank12_value1_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_value1_re $and$ls180.v:6466$2164_Y - connect \builder_csrbank12_value1_we $and$ls180.v:6467$2168_Y - connect \builder_csrbank12_value0_r \builder_interface12_bank_bus_dat_w - connect \builder_csrbank12_value0_re $and$ls180.v:6469$2171_Y - connect \builder_csrbank12_value0_we $and$ls180.v:6470$2175_Y - connect \main_libresocsim_eventmanager_status_r \builder_interface12_bank_bus_dat_w [0] - connect \main_libresocsim_eventmanager_status_re $and$ls180.v:6472$2178_Y - connect \main_libresocsim_eventmanager_status_we $and$ls180.v:6473$2182_Y - connect \main_libresocsim_eventmanager_pending_r \builder_interface12_bank_bus_dat_w [0] - connect \main_libresocsim_eventmanager_pending_re $and$ls180.v:6475$2185_Y - connect \main_libresocsim_eventmanager_pending_we $and$ls180.v:6476$2189_Y - connect \builder_csrbank12_ev_enable0_r \builder_interface12_bank_bus_dat_w [0] - connect \builder_csrbank12_ev_enable0_re $and$ls180.v:6478$2192_Y - connect \builder_csrbank12_ev_enable0_we $and$ls180.v:6479$2196_Y - connect \builder_csrbank12_load3_w \main_libresocsim_load_storage [31:24] - connect \builder_csrbank12_load2_w \main_libresocsim_load_storage [23:16] - connect \builder_csrbank12_load1_w \main_libresocsim_load_storage [15:8] - connect \builder_csrbank12_load0_w \main_libresocsim_load_storage [7:0] - connect \builder_csrbank12_reload3_w \main_libresocsim_reload_storage [31:24] - connect \builder_csrbank12_reload2_w \main_libresocsim_reload_storage [23:16] - connect \builder_csrbank12_reload1_w \main_libresocsim_reload_storage [15:8] - connect \builder_csrbank12_reload0_w \main_libresocsim_reload_storage [7:0] - connect \builder_csrbank12_en0_w \main_libresocsim_en_storage - connect \builder_csrbank12_update_value0_w \main_libresocsim_update_value_storage - connect \builder_csrbank12_value3_w \main_libresocsim_value_status [31:24] - connect \builder_csrbank12_value2_w \main_libresocsim_value_status [23:16] - connect \builder_csrbank12_value1_w \main_libresocsim_value_status [15:8] - connect \builder_csrbank12_value0_w \main_libresocsim_value_status [7:0] - connect \main_libresocsim_value_we \builder_csrbank12_value0_we - connect \builder_csrbank12_ev_enable0_w \main_libresocsim_eventmanager_storage - connect \builder_csrbank13_sel $eq$ls180.v:6496$2197_Y - connect \main_uart_rxtx_r \builder_interface13_bank_bus_dat_w - connect \main_uart_rxtx_re $and$ls180.v:6498$2200_Y - connect \main_uart_rxtx_we $and$ls180.v:6499$2204_Y - connect \builder_csrbank13_txfull_r \builder_interface13_bank_bus_dat_w [0] - connect \builder_csrbank13_txfull_re $and$ls180.v:6501$2207_Y - connect \builder_csrbank13_txfull_we $and$ls180.v:6502$2211_Y - connect \builder_csrbank13_rxempty_r \builder_interface13_bank_bus_dat_w [0] - connect \builder_csrbank13_rxempty_re $and$ls180.v:6504$2214_Y - connect \builder_csrbank13_rxempty_we $and$ls180.v:6505$2218_Y - connect \main_uart_eventmanager_status_r \builder_interface13_bank_bus_dat_w [1:0] - connect \main_uart_eventmanager_status_re $and$ls180.v:6507$2221_Y - connect \main_uart_eventmanager_status_we $and$ls180.v:6508$2225_Y - connect \main_uart_eventmanager_pending_r \builder_interface13_bank_bus_dat_w [1:0] - connect \main_uart_eventmanager_pending_re $and$ls180.v:6510$2228_Y - connect \main_uart_eventmanager_pending_we $and$ls180.v:6511$2232_Y - connect \builder_csrbank13_ev_enable0_r \builder_interface13_bank_bus_dat_w [1:0] - connect \builder_csrbank13_ev_enable0_re $and$ls180.v:6513$2235_Y - connect \builder_csrbank13_ev_enable0_we $and$ls180.v:6514$2239_Y - connect \builder_csrbank13_txempty_r \builder_interface13_bank_bus_dat_w [0] - connect \builder_csrbank13_txempty_re $and$ls180.v:6516$2242_Y - connect \builder_csrbank13_txempty_we $and$ls180.v:6517$2246_Y - connect \builder_csrbank13_rxfull_r \builder_interface13_bank_bus_dat_w [0] - connect \builder_csrbank13_rxfull_re $and$ls180.v:6519$2249_Y - connect \builder_csrbank13_rxfull_we $and$ls180.v:6520$2253_Y - connect \builder_csrbank13_txfull_w \main_uart_txfull_status - connect \main_uart_txfull_we \builder_csrbank13_txfull_we - connect \builder_csrbank13_rxempty_w \main_uart_rxempty_status - connect \main_uart_rxempty_we \builder_csrbank13_rxempty_we - connect \builder_csrbank13_ev_enable0_w \main_uart_eventmanager_storage - connect \builder_csrbank13_txempty_w \main_uart_txempty_status - connect \main_uart_txempty_we \builder_csrbank13_txempty_we - connect \builder_csrbank13_rxfull_w \main_uart_rxfull_status - connect \main_uart_rxfull_we \builder_csrbank13_rxfull_we - connect \builder_csrbank14_sel $eq$ls180.v:6530$2254_Y - connect \builder_csrbank14_tuning_word3_r \builder_interface14_bank_bus_dat_w - connect \builder_csrbank14_tuning_word3_re $and$ls180.v:6532$2257_Y - connect \builder_csrbank14_tuning_word3_we $and$ls180.v:6533$2261_Y - connect \builder_csrbank14_tuning_word2_r \builder_interface14_bank_bus_dat_w - connect \builder_csrbank14_tuning_word2_re $and$ls180.v:6535$2264_Y - connect \builder_csrbank14_tuning_word2_we $and$ls180.v:6536$2268_Y - connect \builder_csrbank14_tuning_word1_r \builder_interface14_bank_bus_dat_w - connect \builder_csrbank14_tuning_word1_re $and$ls180.v:6538$2271_Y - connect \builder_csrbank14_tuning_word1_we $and$ls180.v:6539$2275_Y - connect \builder_csrbank14_tuning_word0_r \builder_interface14_bank_bus_dat_w - connect \builder_csrbank14_tuning_word0_re $and$ls180.v:6541$2278_Y - connect \builder_csrbank14_tuning_word0_we $and$ls180.v:6542$2282_Y - connect \builder_csrbank14_tuning_word3_w \main_uart_phy_storage [31:24] - connect \builder_csrbank14_tuning_word2_w \main_uart_phy_storage [23:16] - connect \builder_csrbank14_tuning_word1_w \main_uart_phy_storage [15:8] - connect \builder_csrbank14_tuning_word0_w \main_uart_phy_storage [7:0] - connect \builder_csr_interconnect_adr \builder_libresocsim_adr - connect \builder_csr_interconnect_we \builder_libresocsim_we - connect \builder_csr_interconnect_dat_w \builder_libresocsim_dat_w - connect \builder_libresocsim_dat_r \builder_csr_interconnect_dat_r - connect \builder_interface0_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface1_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface2_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface3_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface4_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface5_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface6_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface7_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface8_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface9_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface10_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface11_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface12_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface13_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface14_bank_bus_adr \builder_csr_interconnect_adr - connect \builder_interface0_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface1_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface2_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface3_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface4_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface5_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface6_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface7_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface8_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface9_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface10_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface11_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface12_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface13_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface14_bank_bus_we \builder_csr_interconnect_we - connect \builder_interface0_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface1_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface2_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface3_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface4_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface5_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface6_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface7_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface8_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface9_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface10_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface11_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface12_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface13_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_interface14_bank_bus_dat_w \builder_csr_interconnect_dat_w - connect \builder_csr_interconnect_dat_r $or$ls180.v:6596$2296_Y + connect \sys_rst_1 \int_rst + connect \dfi_p0_address \sdram_master_p0_address + connect \dfi_p0_bank \sdram_master_p0_bank + connect \dfi_p0_cas_n \sdram_master_p0_cas_n + connect \dfi_p0_cs_n \sdram_master_p0_cs_n + connect \dfi_p0_ras_n \sdram_master_p0_ras_n + connect \dfi_p0_we_n \sdram_master_p0_we_n + connect \dfi_p0_cke \sdram_master_p0_cke + connect \dfi_p0_odt \sdram_master_p0_odt + connect \dfi_p0_reset_n \sdram_master_p0_reset_n + connect \dfi_p0_act_n \sdram_master_p0_act_n + connect \dfi_p0_wrdata \sdram_master_p0_wrdata + connect \dfi_p0_wrdata_en \sdram_master_p0_wrdata_en + connect \dfi_p0_wrdata_mask \sdram_master_p0_wrdata_mask + connect \dfi_p0_rddata_en \sdram_master_p0_rddata_en + connect \sdram_master_p0_rddata \dfi_p0_rddata + connect \sdram_master_p0_rddata_valid \dfi_p0_rddata_valid + connect \sdram_slave_p0_address \sdram_dfi_p0_address + connect \sdram_slave_p0_bank \sdram_dfi_p0_bank + connect \sdram_slave_p0_cas_n \sdram_dfi_p0_cas_n + connect \sdram_slave_p0_cs_n \sdram_dfi_p0_cs_n + connect \sdram_slave_p0_ras_n \sdram_dfi_p0_ras_n + connect \sdram_slave_p0_we_n \sdram_dfi_p0_we_n + connect \sdram_slave_p0_cke \sdram_dfi_p0_cke + connect \sdram_slave_p0_odt \sdram_dfi_p0_odt + connect \sdram_slave_p0_reset_n \sdram_dfi_p0_reset_n + connect \sdram_slave_p0_act_n \sdram_dfi_p0_act_n + connect \sdram_slave_p0_wrdata \sdram_dfi_p0_wrdata + connect \sdram_slave_p0_wrdata_en \sdram_dfi_p0_wrdata_en + connect \sdram_slave_p0_wrdata_mask \sdram_dfi_p0_wrdata_mask + connect \sdram_slave_p0_rddata_en \sdram_dfi_p0_rddata_en + connect \sdram_dfi_p0_rddata \sdram_slave_p0_rddata + connect \sdram_dfi_p0_rddata_valid \sdram_slave_p0_rddata_valid + connect \sdram_inti_p0_cke \sdram_cke_1 + connect \sdram_inti_p0_odt \sdram_odt + connect \sdram_inti_p0_reset_n \sdram_reset_n + connect \sdram_inti_p0_address \sdram_address_storage + connect \sdram_inti_p0_bank \sdram_baddress_storage + connect \sdram_inti_p0_wrdata_en $and$ls180.v:1846$117_Y + connect \sdram_inti_p0_rddata_en $and$ls180.v:1847$118_Y + connect \sdram_inti_p0_wrdata \sdram_wrdata_storage + connect \sdram_inti_p0_wrdata_mask 2'00 + connect \sdram_bankmachine0_req_valid \sdram_interface_bank0_valid + connect \sdram_interface_bank0_ready \sdram_bankmachine0_req_ready + connect \sdram_bankmachine0_req_we \sdram_interface_bank0_we + connect \sdram_bankmachine0_req_addr \sdram_interface_bank0_addr + connect \sdram_interface_bank0_lock \sdram_bankmachine0_req_lock + connect \sdram_interface_bank0_wdata_ready \sdram_bankmachine0_req_wdata_ready + connect \sdram_interface_bank0_rdata_valid \sdram_bankmachine0_req_rdata_valid + connect \sdram_bankmachine1_req_valid \sdram_interface_bank1_valid + connect \sdram_interface_bank1_ready \sdram_bankmachine1_req_ready + connect \sdram_bankmachine1_req_we \sdram_interface_bank1_we + connect \sdram_bankmachine1_req_addr \sdram_interface_bank1_addr + connect \sdram_interface_bank1_lock \sdram_bankmachine1_req_lock + connect \sdram_interface_bank1_wdata_ready \sdram_bankmachine1_req_wdata_ready + connect \sdram_interface_bank1_rdata_valid \sdram_bankmachine1_req_rdata_valid + connect \sdram_bankmachine2_req_valid \sdram_interface_bank2_valid + connect \sdram_interface_bank2_ready \sdram_bankmachine2_req_ready + connect \sdram_bankmachine2_req_we \sdram_interface_bank2_we + connect \sdram_bankmachine2_req_addr \sdram_interface_bank2_addr + connect \sdram_interface_bank2_lock \sdram_bankmachine2_req_lock + connect \sdram_interface_bank2_wdata_ready \sdram_bankmachine2_req_wdata_ready + connect \sdram_interface_bank2_rdata_valid \sdram_bankmachine2_req_rdata_valid + connect \sdram_bankmachine3_req_valid \sdram_interface_bank3_valid + connect \sdram_interface_bank3_ready \sdram_bankmachine3_req_ready + connect \sdram_bankmachine3_req_we \sdram_interface_bank3_we + connect \sdram_bankmachine3_req_addr \sdram_interface_bank3_addr + connect \sdram_interface_bank3_lock \sdram_bankmachine3_req_lock + connect \sdram_interface_bank3_wdata_ready \sdram_bankmachine3_req_wdata_ready + connect \sdram_interface_bank3_rdata_valid \sdram_bankmachine3_req_rdata_valid + connect \sdram_timer_wait $not$ls180.v:1878$119_Y + connect \sdram_postponer_req_i \sdram_timer_done0 + connect \sdram_wants_refresh \sdram_postponer_req_o + connect \sdram_timer_done1 $eq$ls180.v:1881$120_Y + connect \sdram_timer_done0 \sdram_timer_done1 + connect \sdram_timer_count0 \sdram_timer_count1 + connect \sdram_sequencer_start1 $or$ls180.v:1884$122_Y + connect \sdram_sequencer_done0 $and$ls180.v:1885$124_Y + connect \sdram_bankmachine0_cmd_buffer_lookahead_sink_valid \sdram_bankmachine0_req_valid + connect \sdram_bankmachine0_req_ready \sdram_bankmachine0_cmd_buffer_lookahead_sink_ready + connect \sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we \sdram_bankmachine0_req_we + connect \sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr \sdram_bankmachine0_req_addr + connect \sdram_bankmachine0_cmd_buffer_sink_valid \sdram_bankmachine0_cmd_buffer_lookahead_source_valid + connect \sdram_bankmachine0_cmd_buffer_lookahead_source_ready \sdram_bankmachine0_cmd_buffer_sink_ready + connect \sdram_bankmachine0_cmd_buffer_sink_first \sdram_bankmachine0_cmd_buffer_lookahead_source_first + connect \sdram_bankmachine0_cmd_buffer_sink_last \sdram_bankmachine0_cmd_buffer_lookahead_source_last + connect \sdram_bankmachine0_cmd_buffer_sink_payload_we \sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we + connect \sdram_bankmachine0_cmd_buffer_sink_payload_addr \sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr + connect \sdram_bankmachine0_cmd_buffer_source_ready $or$ls180.v:1927$126_Y + connect \sdram_bankmachine0_req_lock $or$ls180.v:1928$127_Y + connect \sdram_bankmachine0_row_hit $eq$ls180.v:1929$128_Y + connect \sdram_bankmachine0_cmd_payload_ba 2'00 + connect \sdram_bankmachine0_twtpcon_valid $and$ls180.v:1939$133_Y + connect \sdram_bankmachine0_trccon_valid $and$ls180.v:1940$135_Y + connect \sdram_bankmachine0_trascon_valid $and$ls180.v:1941$137_Y + connect \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din { \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we } \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout + connect \sdram_bankmachine0_cmd_buffer_lookahead_sink_ready \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we \sdram_bankmachine0_cmd_buffer_lookahead_sink_valid + connect \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \sdram_bankmachine0_cmd_buffer_lookahead_sink_first + connect \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \sdram_bankmachine0_cmd_buffer_lookahead_sink_last + connect \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we \sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we + connect \sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr + connect \sdram_bankmachine0_cmd_buffer_lookahead_source_valid \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable + connect \sdram_bankmachine0_cmd_buffer_lookahead_source_first \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first + connect \sdram_bankmachine0_cmd_buffer_lookahead_source_last \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last + connect \sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we + connect \sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr \sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr + connect \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re \sdram_bankmachine0_cmd_buffer_lookahead_source_ready + connect \sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din + connect \sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$ls180.v:1973$145_Y + connect \sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$ls180.v:1974$146_Y + connect \sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr \sdram_bankmachine0_cmd_buffer_lookahead_consume + connect \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout \sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r + connect \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$ls180.v:1977$147_Y + connect \sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$ls180.v:1978$148_Y + connect \sdram_bankmachine0_cmd_buffer_sink_ready $or$ls180.v:1979$150_Y + connect \sdram_bankmachine1_cmd_buffer_lookahead_sink_valid \sdram_bankmachine1_req_valid + connect \sdram_bankmachine1_req_ready \sdram_bankmachine1_cmd_buffer_lookahead_sink_ready + connect \sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we \sdram_bankmachine1_req_we + connect \sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr \sdram_bankmachine1_req_addr + connect \sdram_bankmachine1_cmd_buffer_sink_valid \sdram_bankmachine1_cmd_buffer_lookahead_source_valid + connect \sdram_bankmachine1_cmd_buffer_lookahead_source_ready \sdram_bankmachine1_cmd_buffer_sink_ready + connect \sdram_bankmachine1_cmd_buffer_sink_first \sdram_bankmachine1_cmd_buffer_lookahead_source_first + connect \sdram_bankmachine1_cmd_buffer_sink_last \sdram_bankmachine1_cmd_buffer_lookahead_source_last + connect \sdram_bankmachine1_cmd_buffer_sink_payload_we \sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we + connect \sdram_bankmachine1_cmd_buffer_sink_payload_addr \sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr + connect \sdram_bankmachine1_cmd_buffer_source_ready $or$ls180.v:2084$156_Y + connect \sdram_bankmachine1_req_lock $or$ls180.v:2085$157_Y + connect \sdram_bankmachine1_row_hit $eq$ls180.v:2086$158_Y + connect \sdram_bankmachine1_cmd_payload_ba 2'01 + connect \sdram_bankmachine1_twtpcon_valid $and$ls180.v:2096$163_Y + connect \sdram_bankmachine1_trccon_valid $and$ls180.v:2097$165_Y + connect \sdram_bankmachine1_trascon_valid $and$ls180.v:2098$167_Y + connect \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din { \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we } \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout + connect \sdram_bankmachine1_cmd_buffer_lookahead_sink_ready \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we \sdram_bankmachine1_cmd_buffer_lookahead_sink_valid + connect \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \sdram_bankmachine1_cmd_buffer_lookahead_sink_first + connect \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \sdram_bankmachine1_cmd_buffer_lookahead_sink_last + connect \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we \sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we + connect \sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr + connect \sdram_bankmachine1_cmd_buffer_lookahead_source_valid \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable + connect \sdram_bankmachine1_cmd_buffer_lookahead_source_first \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first + connect \sdram_bankmachine1_cmd_buffer_lookahead_source_last \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last + connect \sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we + connect \sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr \sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr + connect \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re \sdram_bankmachine1_cmd_buffer_lookahead_source_ready + connect \sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din + connect \sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$ls180.v:2130$175_Y + connect \sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$ls180.v:2131$176_Y + connect \sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr \sdram_bankmachine1_cmd_buffer_lookahead_consume + connect \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout \sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r + connect \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$ls180.v:2134$177_Y + connect \sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$ls180.v:2135$178_Y + connect \sdram_bankmachine1_cmd_buffer_sink_ready $or$ls180.v:2136$180_Y + connect \sdram_bankmachine2_cmd_buffer_lookahead_sink_valid \sdram_bankmachine2_req_valid + connect \sdram_bankmachine2_req_ready \sdram_bankmachine2_cmd_buffer_lookahead_sink_ready + connect \sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we \sdram_bankmachine2_req_we + connect \sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr \sdram_bankmachine2_req_addr + connect \sdram_bankmachine2_cmd_buffer_sink_valid \sdram_bankmachine2_cmd_buffer_lookahead_source_valid + connect \sdram_bankmachine2_cmd_buffer_lookahead_source_ready \sdram_bankmachine2_cmd_buffer_sink_ready + connect \sdram_bankmachine2_cmd_buffer_sink_first \sdram_bankmachine2_cmd_buffer_lookahead_source_first + connect \sdram_bankmachine2_cmd_buffer_sink_last \sdram_bankmachine2_cmd_buffer_lookahead_source_last + connect \sdram_bankmachine2_cmd_buffer_sink_payload_we \sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we + connect \sdram_bankmachine2_cmd_buffer_sink_payload_addr \sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr + connect \sdram_bankmachine2_cmd_buffer_source_ready $or$ls180.v:2241$186_Y + connect \sdram_bankmachine2_req_lock $or$ls180.v:2242$187_Y + connect \sdram_bankmachine2_row_hit $eq$ls180.v:2243$188_Y + connect \sdram_bankmachine2_cmd_payload_ba 2'10 + connect \sdram_bankmachine2_twtpcon_valid $and$ls180.v:2253$193_Y + connect \sdram_bankmachine2_trccon_valid $and$ls180.v:2254$195_Y + connect \sdram_bankmachine2_trascon_valid $and$ls180.v:2255$197_Y + connect \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din { \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we } \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout + connect \sdram_bankmachine2_cmd_buffer_lookahead_sink_ready \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we \sdram_bankmachine2_cmd_buffer_lookahead_sink_valid + connect \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \sdram_bankmachine2_cmd_buffer_lookahead_sink_first + connect \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \sdram_bankmachine2_cmd_buffer_lookahead_sink_last + connect \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we \sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we + connect \sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr + connect \sdram_bankmachine2_cmd_buffer_lookahead_source_valid \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable + connect \sdram_bankmachine2_cmd_buffer_lookahead_source_first \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first + connect \sdram_bankmachine2_cmd_buffer_lookahead_source_last \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last + connect \sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we + connect \sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr \sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr + connect \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re \sdram_bankmachine2_cmd_buffer_lookahead_source_ready + connect \sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din + connect \sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$ls180.v:2287$205_Y + connect \sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$ls180.v:2288$206_Y + connect \sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr \sdram_bankmachine2_cmd_buffer_lookahead_consume + connect \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout \sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r + connect \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$ls180.v:2291$207_Y + connect \sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$ls180.v:2292$208_Y + connect \sdram_bankmachine2_cmd_buffer_sink_ready $or$ls180.v:2293$210_Y + connect \sdram_bankmachine3_cmd_buffer_lookahead_sink_valid \sdram_bankmachine3_req_valid + connect \sdram_bankmachine3_req_ready \sdram_bankmachine3_cmd_buffer_lookahead_sink_ready + connect \sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we \sdram_bankmachine3_req_we + connect \sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr \sdram_bankmachine3_req_addr + connect \sdram_bankmachine3_cmd_buffer_sink_valid \sdram_bankmachine3_cmd_buffer_lookahead_source_valid + connect \sdram_bankmachine3_cmd_buffer_lookahead_source_ready \sdram_bankmachine3_cmd_buffer_sink_ready + connect \sdram_bankmachine3_cmd_buffer_sink_first \sdram_bankmachine3_cmd_buffer_lookahead_source_first + connect \sdram_bankmachine3_cmd_buffer_sink_last \sdram_bankmachine3_cmd_buffer_lookahead_source_last + connect \sdram_bankmachine3_cmd_buffer_sink_payload_we \sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we + connect \sdram_bankmachine3_cmd_buffer_sink_payload_addr \sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr + connect \sdram_bankmachine3_cmd_buffer_source_ready $or$ls180.v:2398$216_Y + connect \sdram_bankmachine3_req_lock $or$ls180.v:2399$217_Y + connect \sdram_bankmachine3_row_hit $eq$ls180.v:2400$218_Y + connect \sdram_bankmachine3_cmd_payload_ba 2'11 + connect \sdram_bankmachine3_twtpcon_valid $and$ls180.v:2410$223_Y + connect \sdram_bankmachine3_trccon_valid $and$ls180.v:2411$225_Y + connect \sdram_bankmachine3_trascon_valid $and$ls180.v:2412$227_Y + connect \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din { \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we } \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout + connect \sdram_bankmachine3_cmd_buffer_lookahead_sink_ready \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we \sdram_bankmachine3_cmd_buffer_lookahead_sink_valid + connect \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \sdram_bankmachine3_cmd_buffer_lookahead_sink_first + connect \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \sdram_bankmachine3_cmd_buffer_lookahead_sink_last + connect \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we \sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we + connect \sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr + connect \sdram_bankmachine3_cmd_buffer_lookahead_source_valid \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable + connect \sdram_bankmachine3_cmd_buffer_lookahead_source_first \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first + connect \sdram_bankmachine3_cmd_buffer_lookahead_source_last \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last + connect \sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we + connect \sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr \sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr + connect \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re \sdram_bankmachine3_cmd_buffer_lookahead_source_ready + connect \sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din + connect \sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$ls180.v:2444$235_Y + connect \sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$ls180.v:2445$236_Y + connect \sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr \sdram_bankmachine3_cmd_buffer_lookahead_consume + connect \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout \sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r + connect \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$ls180.v:2448$237_Y + connect \sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$ls180.v:2449$238_Y + connect \sdram_bankmachine3_cmd_buffer_sink_ready $or$ls180.v:2450$240_Y + connect \sdram_choose_req_want_cmds 1'1 + connect \sdram_trrdcon_valid $and$ls180.v:2546$251_Y + connect \sdram_tfawcon_valid $and$ls180.v:2547$257_Y + connect \sdram_ras_allowed $and$ls180.v:2548$258_Y + connect \sdram_tccdcon_valid $and$ls180.v:2549$261_Y + connect \sdram_cas_allowed \sdram_tccdcon_ready + connect \sdram_twtrcon_valid $and$ls180.v:2551$263_Y + connect \sdram_read_available $or$ls180.v:2552$270_Y + connect \sdram_write_available $or$ls180.v:2553$277_Y + connect \sdram_max_time0 $eq$ls180.v:2554$278_Y + connect \sdram_max_time1 $eq$ls180.v:2555$279_Y + connect \sdram_bankmachine0_refresh_req \sdram_cmd_valid + connect \sdram_bankmachine1_refresh_req \sdram_cmd_valid + connect \sdram_bankmachine2_refresh_req \sdram_cmd_valid + connect \sdram_bankmachine3_refresh_req \sdram_cmd_valid + connect \sdram_go_to_refresh $and$ls180.v:2560$282_Y + connect \sdram_interface_rdata \sdram_dfi_p0_rddata + connect \sdram_dfi_p0_wrdata \sdram_interface_wdata + connect \sdram_dfi_p0_wrdata_mask $not$ls180.v:2563$283_Y + connect \sdram_choose_cmd_request \sdram_choose_cmd_valids + connect \sdram_choose_cmd_cmd_valid \rhs_array_muxed0 + connect \sdram_choose_cmd_cmd_payload_a \rhs_array_muxed1 + connect \sdram_choose_cmd_cmd_payload_ba \rhs_array_muxed2 + connect \sdram_choose_cmd_cmd_payload_is_read \rhs_array_muxed3 + connect \sdram_choose_cmd_cmd_payload_is_write \rhs_array_muxed4 + connect \sdram_choose_cmd_cmd_payload_is_cmd \rhs_array_muxed5 + connect \sdram_choose_cmd_ce $or$ls180.v:2596$341_Y + connect \sdram_choose_req_request \sdram_choose_req_valids + connect \sdram_choose_req_cmd_valid \rhs_array_muxed6 + connect \sdram_choose_req_cmd_payload_a \rhs_array_muxed7 + connect \sdram_choose_req_cmd_payload_ba \rhs_array_muxed8 + connect \sdram_choose_req_cmd_payload_is_read \rhs_array_muxed9 + connect \sdram_choose_req_cmd_payload_is_write \rhs_array_muxed10 + connect \sdram_choose_req_cmd_payload_is_cmd \rhs_array_muxed11 + connect \sdram_choose_req_ce $or$ls180.v:2665$427_Y + connect \sdram_dfi_p0_reset_n 1'1 + connect \sdram_dfi_p0_cke \sdram_steerer0 + connect \sdram_dfi_p0_odt \sdram_steerer1 + connect \subfragments_roundrobin0_request $and$ls180.v:2742$459_Y + connect \subfragments_roundrobin0_ce $and$ls180.v:2743$462_Y + connect \sdram_interface_bank0_addr \rhs_array_muxed12 + connect \sdram_interface_bank0_we \rhs_array_muxed13 + connect \sdram_interface_bank0_valid \rhs_array_muxed14 + connect \subfragments_roundrobin1_request $and$ls180.v:2747$475_Y + connect \subfragments_roundrobin1_ce $and$ls180.v:2748$478_Y + connect \sdram_interface_bank1_addr \rhs_array_muxed15 + connect \sdram_interface_bank1_we \rhs_array_muxed16 + connect \sdram_interface_bank1_valid \rhs_array_muxed17 + connect \subfragments_roundrobin2_request $and$ls180.v:2752$491_Y + connect \subfragments_roundrobin2_ce $and$ls180.v:2753$494_Y + connect \sdram_interface_bank2_addr \rhs_array_muxed18 + connect \sdram_interface_bank2_we \rhs_array_muxed19 + connect \sdram_interface_bank2_valid \rhs_array_muxed20 + connect \subfragments_roundrobin3_request $and$ls180.v:2757$507_Y + connect \subfragments_roundrobin3_ce $and$ls180.v:2758$510_Y + connect \sdram_interface_bank3_addr \rhs_array_muxed21 + connect \sdram_interface_bank3_we \rhs_array_muxed22 + connect \sdram_interface_bank3_valid \rhs_array_muxed23 + connect \port_cmd_ready $or$ls180.v:2762$574_Y + connect \port_wdata_ready \subfragments_new_master_wdata_ready + connect \port_rdata_valid \subfragments_new_master_rdata_valid3 + connect \port_rdata_payload_data \sdram_interface_rdata + connect \subfragments_roundrobin0_grant 1'0 + connect \subfragments_roundrobin1_grant 1'0 + connect \subfragments_roundrobin2_grant 1'0 + connect \subfragments_roundrobin3_grant 1'0 + connect \converter_reset $not$ls180.v:2784$576_Y + connect \wb_sdram_dat_r { \litedram_wb_dat_r \converter_dat_r [31:16] } + connect \port_cmd_payload_addr $sub$ls180.v:2844$587_Y [23:0] + connect \port_cmd_payload_we \litedram_wb_we + connect \port_wdata_payload_data \litedram_wb_dat_w + connect \port_wdata_payload_we \litedram_wb_sel + connect \litedram_wb_dat_r \port_rdata_payload_data + connect \port_flush $not$ls180.v:2849$588_Y + connect \port_cmd_last $not$ls180.v:2850$589_Y + connect \port_cmd_valid $and$ls180.v:2851$592_Y + connect \port_wdata_valid $and$ls180.v:2852$596_Y + connect \port_rdata_ready $and$ls180.v:2853$599_Y + connect \litedram_wb_ack $and$ls180.v:2854$604_Y + connect \ack_cmd $or$ls180.v:2855$606_Y + connect \ack_wdata $or$ls180.v:2856$608_Y + connect \ack_rdata $and$ls180.v:2857$609_Y + connect \uart_sink_valid \uart_phy_source_valid + connect \uart_phy_source_ready \uart_sink_ready + connect \uart_sink_first \uart_phy_source_first + connect \uart_sink_last \uart_phy_source_last + connect \uart_sink_payload_data \uart_phy_source_payload_data + connect \uart_phy_sink_valid \uart_source_valid + connect \uart_source_ready \uart_phy_sink_ready + connect \uart_phy_sink_first \uart_source_first + connect \uart_phy_sink_last \uart_source_last + connect \uart_phy_sink_payload_data \uart_source_payload_data + connect \tx_fifo_sink_valid \rxtx_re + connect \tx_fifo_sink_payload_data \rxtx_r + connect \txfull_status $not$ls180.v:2870$610_Y + connect \txempty_status $not$ls180.v:2871$611_Y + connect \uart_source_valid \tx_fifo_source_valid + connect \tx_fifo_source_ready \uart_source_ready + connect \uart_source_first \tx_fifo_source_first + connect \uart_source_last \tx_fifo_source_last + connect \uart_source_payload_data \tx_fifo_source_payload_data + connect \tx_trigger $not$ls180.v:2877$612_Y + connect \rx_fifo_sink_valid \uart_sink_valid + connect \uart_sink_ready \rx_fifo_sink_ready + connect \rx_fifo_sink_first \uart_sink_first + connect \rx_fifo_sink_last \uart_sink_last + connect \rx_fifo_sink_payload_data \uart_sink_payload_data + connect \rxempty_status $not$ls180.v:2883$613_Y + connect \rxfull_status $not$ls180.v:2884$614_Y + connect \rxtx_w \rx_fifo_source_payload_data + connect \rx_fifo_source_ready $or$ls180.v:2886$616_Y + connect \rx_trigger $not$ls180.v:2887$617_Y + connect \irq $or$ls180.v:2910$626_Y + connect \tx_status \tx_trigger + connect \rx_status \rx_trigger + connect \tx_fifo_syncfifo_din { \tx_fifo_fifo_in_last \tx_fifo_fifo_in_first \tx_fifo_fifo_in_payload_data } + connect { \tx_fifo_fifo_out_last \tx_fifo_fifo_out_first \tx_fifo_fifo_out_payload_data } \tx_fifo_syncfifo_dout + connect \tx_fifo_sink_ready \tx_fifo_syncfifo_writable + connect \tx_fifo_syncfifo_we \tx_fifo_sink_valid + connect \tx_fifo_fifo_in_first \tx_fifo_sink_first + connect \tx_fifo_fifo_in_last \tx_fifo_sink_last + connect \tx_fifo_fifo_in_payload_data \tx_fifo_sink_payload_data + connect \tx_fifo_source_valid \tx_fifo_readable + connect \tx_fifo_source_first \tx_fifo_fifo_out_first + connect \tx_fifo_source_last \tx_fifo_fifo_out_last + connect \tx_fifo_source_payload_data \tx_fifo_fifo_out_payload_data + connect \tx_fifo_re \tx_fifo_source_ready + connect \tx_fifo_syncfifo_re $and$ls180.v:2925$629_Y + connect \tx_fifo_level1 $add$ls180.v:2926$630_Y + connect \tx_fifo_wrport_dat_w \tx_fifo_syncfifo_din + connect \tx_fifo_wrport_we $and$ls180.v:2936$634_Y + connect \tx_fifo_do_read $and$ls180.v:2937$635_Y + connect \tx_fifo_rdport_adr \tx_fifo_consume + connect \tx_fifo_syncfifo_dout \tx_fifo_rdport_dat_r + connect \tx_fifo_rdport_re \tx_fifo_do_read + connect \tx_fifo_syncfifo_writable $ne$ls180.v:2941$636_Y + connect \tx_fifo_syncfifo_readable $ne$ls180.v:2942$637_Y + connect \rx_fifo_syncfifo_din { \rx_fifo_fifo_in_last \rx_fifo_fifo_in_first \rx_fifo_fifo_in_payload_data } + connect { \rx_fifo_fifo_out_last \rx_fifo_fifo_out_first \rx_fifo_fifo_out_payload_data } \rx_fifo_syncfifo_dout + connect \rx_fifo_sink_ready \rx_fifo_syncfifo_writable + connect \rx_fifo_syncfifo_we \rx_fifo_sink_valid + connect \rx_fifo_fifo_in_first \rx_fifo_sink_first + connect \rx_fifo_fifo_in_last \rx_fifo_sink_last + connect \rx_fifo_fifo_in_payload_data \rx_fifo_sink_payload_data + connect \rx_fifo_source_valid \rx_fifo_readable + connect \rx_fifo_source_first \rx_fifo_fifo_out_first + connect \rx_fifo_source_last \rx_fifo_fifo_out_last + connect \rx_fifo_source_payload_data \rx_fifo_fifo_out_payload_data + connect \rx_fifo_re \rx_fifo_source_ready + connect \rx_fifo_syncfifo_re $and$ls180.v:2955$640_Y + connect \rx_fifo_level1 $add$ls180.v:2956$641_Y + connect \rx_fifo_wrport_dat_w \rx_fifo_syncfifo_din + connect \rx_fifo_wrport_we $and$ls180.v:2966$645_Y + connect \rx_fifo_do_read $and$ls180.v:2967$646_Y + connect \rx_fifo_rdport_adr \rx_fifo_consume + connect \rx_fifo_syncfifo_dout \rx_fifo_rdport_dat_r + connect \rx_fifo_rdport_re \rx_fifo_do_read + connect \rx_fifo_syncfifo_writable $ne$ls180.v:2971$647_Y + connect \rx_fifo_syncfifo_readable $ne$ls180.v:2972$648_Y + connect \libresocsim_libresoc_constraintmanager_obj_i2c_scl \i2c_scl_1 + connect \libresocsim_libresoc_constraintmanager_obj_i2c_sda_oe \i2c_oe + connect \libresocsim_libresoc_constraintmanager_obj_i2c_sda_o \i2c_sda0 + connect \i2c_sda1 \libresocsim_libresoc_constraintmanager_obj_i2c_sda_i + connect \libresocsim_shared_adr { 1'0 \rhs_array_muxed24 } + connect \libresocsim_shared_dat_w \rhs_array_muxed25 [31:0] + connect \libresocsim_shared_sel \rhs_array_muxed26 [3:0] + connect \libresocsim_shared_cyc \rhs_array_muxed27 + connect \libresocsim_shared_stb \rhs_array_muxed28 + connect \libresocsim_shared_we \rhs_array_muxed29 + connect \libresocsim_shared_cti \rhs_array_muxed30 + connect \libresocsim_shared_bte \rhs_array_muxed31 + connect \libresocsim_libresoc_ibus_dat_r { 32'00000000000000000000000000000000 \libresocsim_shared_dat_r } + connect \libresocsim_libresoc_dbus_dat_r { 32'00000000000000000000000000000000 \libresocsim_shared_dat_r } + connect \libresocsim_libresoc_jtag_wb_dat_r { 32'00000000000000000000000000000000 \libresocsim_shared_dat_r } + connect \libresocsim_libresoc_ibus_ack $and$ls180.v:3085$658_Y + connect \libresocsim_libresoc_dbus_ack $and$ls180.v:3086$660_Y + connect \libresocsim_libresoc_jtag_wb_ack $and$ls180.v:3087$662_Y + connect \libresocsim_libresoc_ibus_err $and$ls180.v:3088$664_Y + connect \libresocsim_libresoc_dbus_err $and$ls180.v:3089$666_Y + connect \libresocsim_libresoc_jtag_wb_err $and$ls180.v:3090$668_Y + connect \libresocsim_request { \libresocsim_libresoc_jtag_wb_cyc \libresocsim_libresoc_dbus_cyc \libresocsim_libresoc_ibus_cyc } + connect \libresocsim_ram_bus_adr \libresocsim_shared_adr + connect \libresocsim_ram_bus_dat_w { 32'00000000000000000000000000000000 \libresocsim_shared_dat_w } + connect \libresocsim_ram_bus_sel { 4'0000 \libresocsim_shared_sel } + connect \libresocsim_ram_bus_stb \libresocsim_shared_stb + connect \libresocsim_ram_bus_we \libresocsim_shared_we + connect \libresocsim_ram_bus_cti \libresocsim_shared_cti + connect \libresocsim_ram_bus_bte \libresocsim_shared_bte + connect \ram_bus_ram_bus_adr \libresocsim_shared_adr + connect \ram_bus_ram_bus_dat_w { 32'00000000000000000000000000000000 \libresocsim_shared_dat_w } + connect \ram_bus_ram_bus_sel { 4'0000 \libresocsim_shared_sel } + connect \ram_bus_ram_bus_stb \libresocsim_shared_stb + connect \ram_bus_ram_bus_we \libresocsim_shared_we + connect \ram_bus_ram_bus_cti \libresocsim_shared_cti + connect \ram_bus_ram_bus_bte \libresocsim_shared_bte + connect \interface0_converted_interface_adr \libresocsim_shared_adr + connect \interface0_converted_interface_dat_w { 32'00000000000000000000000000000000 \libresocsim_shared_dat_w } + connect \interface0_converted_interface_sel { 4'0000 \libresocsim_shared_sel } + connect \interface0_converted_interface_stb \libresocsim_shared_stb + connect \interface0_converted_interface_we \libresocsim_shared_we + connect \interface0_converted_interface_cti \libresocsim_shared_cti + connect \interface0_converted_interface_bte \libresocsim_shared_bte + connect \interface1_converted_interface_adr \libresocsim_shared_adr + connect \interface1_converted_interface_dat_w { 32'00000000000000000000000000000000 \libresocsim_shared_dat_w } + connect \interface1_converted_interface_sel { 4'0000 \libresocsim_shared_sel } + connect \interface1_converted_interface_stb \libresocsim_shared_stb + connect \interface1_converted_interface_we \libresocsim_shared_we + connect \interface1_converted_interface_cti \libresocsim_shared_cti + connect \interface1_converted_interface_bte \libresocsim_shared_bte + connect \socbushandler_converted_interface_adr \libresocsim_shared_adr + connect \socbushandler_converted_interface_dat_w { 32'00000000000000000000000000000000 \libresocsim_shared_dat_w } + connect \socbushandler_converted_interface_sel { 4'0000 \libresocsim_shared_sel } + connect \socbushandler_converted_interface_stb \libresocsim_shared_stb + connect \socbushandler_converted_interface_we \libresocsim_shared_we + connect \socbushandler_converted_interface_cti \libresocsim_shared_cti + connect \socbushandler_converted_interface_bte \libresocsim_shared_bte + connect \libresocsim_libresocsim_converted_interface_adr \libresocsim_shared_adr + connect \libresocsim_libresocsim_converted_interface_dat_w { 32'00000000000000000000000000000000 \libresocsim_shared_dat_w } + connect \libresocsim_libresocsim_converted_interface_sel { 4'0000 \libresocsim_shared_sel } + connect \libresocsim_libresocsim_converted_interface_stb \libresocsim_shared_stb + connect \libresocsim_libresocsim_converted_interface_we \libresocsim_shared_we + connect \libresocsim_libresocsim_converted_interface_cti \libresocsim_shared_cti + connect \libresocsim_libresocsim_converted_interface_bte \libresocsim_shared_bte + connect \libresocsim_ram_bus_cyc $and$ls180.v:3143$676_Y + connect \ram_bus_ram_bus_cyc $and$ls180.v:3144$677_Y + connect \interface0_converted_interface_cyc $and$ls180.v:3145$678_Y + connect \interface1_converted_interface_cyc $and$ls180.v:3146$679_Y + connect \socbushandler_converted_interface_cyc $and$ls180.v:3147$680_Y + connect \libresocsim_libresocsim_converted_interface_cyc $and$ls180.v:3148$681_Y + connect \libresocsim_shared_err $or$ls180.v:3149$686_Y + connect \libresocsim_wait $and$ls180.v:3150$689_Y + connect \libresocsim_done $eq$ls180.v:3163$707_Y + connect \libresocsim_csrbank0_sel $eq$ls180.v:3164$708_Y + connect \libresocsim_csrbank0_reset0_r \libresocsim_interface0_bank_bus_dat_w [0] + connect \libresocsim_csrbank0_reset0_re $and$ls180.v:3166$711_Y + connect \libresocsim_csrbank0_reset0_we $and$ls180.v:3167$715_Y + connect \libresocsim_csrbank0_scratch3_r \libresocsim_interface0_bank_bus_dat_w + connect \libresocsim_csrbank0_scratch3_re $and$ls180.v:3169$718_Y + connect \libresocsim_csrbank0_scratch3_we $and$ls180.v:3170$722_Y + connect \libresocsim_csrbank0_scratch2_r \libresocsim_interface0_bank_bus_dat_w + connect \libresocsim_csrbank0_scratch2_re $and$ls180.v:3172$725_Y + connect \libresocsim_csrbank0_scratch2_we $and$ls180.v:3173$729_Y + connect \libresocsim_csrbank0_scratch1_r \libresocsim_interface0_bank_bus_dat_w + connect \libresocsim_csrbank0_scratch1_re $and$ls180.v:3175$732_Y + connect \libresocsim_csrbank0_scratch1_we $and$ls180.v:3176$736_Y + connect \libresocsim_csrbank0_scratch0_r \libresocsim_interface0_bank_bus_dat_w + connect \libresocsim_csrbank0_scratch0_re $and$ls180.v:3178$739_Y + connect \libresocsim_csrbank0_scratch0_we $and$ls180.v:3179$743_Y + connect \libresocsim_csrbank0_bus_errors3_r \libresocsim_interface0_bank_bus_dat_w + connect \libresocsim_csrbank0_bus_errors3_re $and$ls180.v:3181$746_Y + connect \libresocsim_csrbank0_bus_errors3_we $and$ls180.v:3182$750_Y + connect \libresocsim_csrbank0_bus_errors2_r \libresocsim_interface0_bank_bus_dat_w + connect \libresocsim_csrbank0_bus_errors2_re $and$ls180.v:3184$753_Y + connect \libresocsim_csrbank0_bus_errors2_we $and$ls180.v:3185$757_Y + connect \libresocsim_csrbank0_bus_errors1_r \libresocsim_interface0_bank_bus_dat_w + connect \libresocsim_csrbank0_bus_errors1_re $and$ls180.v:3187$760_Y + connect \libresocsim_csrbank0_bus_errors1_we $and$ls180.v:3188$764_Y + connect \libresocsim_csrbank0_bus_errors0_r \libresocsim_interface0_bank_bus_dat_w + connect \libresocsim_csrbank0_bus_errors0_re $and$ls180.v:3190$767_Y + connect \libresocsim_csrbank0_bus_errors0_we $and$ls180.v:3191$771_Y + connect \libresocsim_csrbank0_reset0_w \libresocsim_reset_storage + connect \libresocsim_csrbank0_scratch3_w \libresocsim_scratch_storage [31:24] + connect \libresocsim_csrbank0_scratch2_w \libresocsim_scratch_storage [23:16] + connect \libresocsim_csrbank0_scratch1_w \libresocsim_scratch_storage [15:8] + connect \libresocsim_csrbank0_scratch0_w \libresocsim_scratch_storage [7:0] + connect \libresocsim_csrbank0_bus_errors3_w \libresocsim_bus_errors_status [31:24] + connect \libresocsim_csrbank0_bus_errors2_w \libresocsim_bus_errors_status [23:16] + connect \libresocsim_csrbank0_bus_errors1_w \libresocsim_bus_errors_status [15:8] + connect \libresocsim_csrbank0_bus_errors0_w \libresocsim_bus_errors_status [7:0] + connect \libresocsim_bus_errors_we \libresocsim_csrbank0_bus_errors0_we + connect \libresocsim_csrbank1_sel $eq$ls180.v:3202$772_Y + connect \libresocsim_csrbank1_oe0_r \libresocsim_interface1_bank_bus_dat_w + connect \libresocsim_csrbank1_oe0_re $and$ls180.v:3204$775_Y + connect \libresocsim_csrbank1_oe0_we $and$ls180.v:3205$779_Y + connect \libresocsim_csrbank1_in_r \libresocsim_interface1_bank_bus_dat_w + connect \libresocsim_csrbank1_in_re $and$ls180.v:3207$782_Y + connect \libresocsim_csrbank1_in_we $and$ls180.v:3208$786_Y + connect \libresocsim_csrbank1_out0_r \libresocsim_interface1_bank_bus_dat_w + connect \libresocsim_csrbank1_out0_re $and$ls180.v:3210$789_Y + connect \libresocsim_csrbank1_out0_we $and$ls180.v:3211$793_Y + connect \libresocsim_csrbank1_oe0_w \gpio0_oe_storage + connect \libresocsim_csrbank1_in_w \gpio0_status + connect \gpio0_we \libresocsim_csrbank1_in_we + connect \libresocsim_csrbank1_out0_w \gpio0_out_storage + connect \libresocsim_csrbank2_sel $eq$ls180.v:3216$794_Y + connect \libresocsim_csrbank2_oe0_r \libresocsim_interface2_bank_bus_dat_w + connect \libresocsim_csrbank2_oe0_re $and$ls180.v:3218$797_Y + connect \libresocsim_csrbank2_oe0_we $and$ls180.v:3219$801_Y + connect \libresocsim_csrbank2_in_r \libresocsim_interface2_bank_bus_dat_w + connect \libresocsim_csrbank2_in_re $and$ls180.v:3221$804_Y + connect \libresocsim_csrbank2_in_we $and$ls180.v:3222$808_Y + connect \libresocsim_csrbank2_out0_r \libresocsim_interface2_bank_bus_dat_w + connect \libresocsim_csrbank2_out0_re $and$ls180.v:3224$811_Y + connect \libresocsim_csrbank2_out0_we $and$ls180.v:3225$815_Y + connect \libresocsim_csrbank2_oe0_w \gpio1_oe_storage + connect \libresocsim_csrbank2_in_w \gpio1_status + connect \gpio1_we \libresocsim_csrbank2_in_we + connect \libresocsim_csrbank2_out0_w \gpio1_out_storage + connect \libresocsim_csrbank3_sel $eq$ls180.v:3230$816_Y + connect \libresocsim_csrbank3_w0_r \libresocsim_interface3_bank_bus_dat_w [2:0] + connect \libresocsim_csrbank3_w0_re $and$ls180.v:3232$819_Y + connect \libresocsim_csrbank3_w0_we $and$ls180.v:3233$823_Y + connect \libresocsim_csrbank3_r_r \libresocsim_interface3_bank_bus_dat_w [0] + connect \libresocsim_csrbank3_r_re $and$ls180.v:3235$826_Y + connect \libresocsim_csrbank3_r_we $and$ls180.v:3236$830_Y + connect \i2c_scl_1 \i2c_storage [0] + connect \i2c_oe \i2c_storage [1] + connect \i2c_sda0 \i2c_storage [2] + connect \libresocsim_csrbank3_w0_w \i2c_storage + connect \i2c_status \i2c_sda1 + connect \libresocsim_csrbank3_r_w \i2c_status + connect \i2c_we \libresocsim_csrbank3_r_we + connect \libresocsim_csrbank4_sel $eq$ls180.v:3244$831_Y + connect \libresocsim_csrbank4_dfii_control0_r \libresocsim_interface4_bank_bus_dat_w [3:0] + connect \libresocsim_csrbank4_dfii_control0_re $and$ls180.v:3246$834_Y + connect \libresocsim_csrbank4_dfii_control0_we $and$ls180.v:3247$838_Y + connect \libresocsim_csrbank4_dfii_pi0_command0_r \libresocsim_interface4_bank_bus_dat_w [5:0] + connect \libresocsim_csrbank4_dfii_pi0_command0_re $and$ls180.v:3249$841_Y + connect \libresocsim_csrbank4_dfii_pi0_command0_we $and$ls180.v:3250$845_Y + connect \sdram_command_issue_r \libresocsim_interface4_bank_bus_dat_w [0] + connect \sdram_command_issue_re $and$ls180.v:3252$848_Y + connect \sdram_command_issue_we $and$ls180.v:3253$852_Y + connect \libresocsim_csrbank4_dfii_pi0_address1_r \libresocsim_interface4_bank_bus_dat_w [4:0] + connect \libresocsim_csrbank4_dfii_pi0_address1_re $and$ls180.v:3255$855_Y + connect \libresocsim_csrbank4_dfii_pi0_address1_we $and$ls180.v:3256$859_Y + connect \libresocsim_csrbank4_dfii_pi0_address0_r \libresocsim_interface4_bank_bus_dat_w + connect \libresocsim_csrbank4_dfii_pi0_address0_re $and$ls180.v:3258$862_Y + connect \libresocsim_csrbank4_dfii_pi0_address0_we $and$ls180.v:3259$866_Y + connect \libresocsim_csrbank4_dfii_pi0_baddress0_r \libresocsim_interface4_bank_bus_dat_w [1:0] + connect \libresocsim_csrbank4_dfii_pi0_baddress0_re $and$ls180.v:3261$869_Y + connect \libresocsim_csrbank4_dfii_pi0_baddress0_we $and$ls180.v:3262$873_Y + connect \libresocsim_csrbank4_dfii_pi0_wrdata1_r \libresocsim_interface4_bank_bus_dat_w + connect \libresocsim_csrbank4_dfii_pi0_wrdata1_re $and$ls180.v:3264$876_Y + connect \libresocsim_csrbank4_dfii_pi0_wrdata1_we $and$ls180.v:3265$880_Y + connect \libresocsim_csrbank4_dfii_pi0_wrdata0_r \libresocsim_interface4_bank_bus_dat_w + connect \libresocsim_csrbank4_dfii_pi0_wrdata0_re $and$ls180.v:3267$883_Y + connect \libresocsim_csrbank4_dfii_pi0_wrdata0_we $and$ls180.v:3268$887_Y + connect \libresocsim_csrbank4_dfii_pi0_rddata1_r \libresocsim_interface4_bank_bus_dat_w + connect \libresocsim_csrbank4_dfii_pi0_rddata1_re $and$ls180.v:3270$890_Y + connect \libresocsim_csrbank4_dfii_pi0_rddata1_we $and$ls180.v:3271$894_Y + connect \libresocsim_csrbank4_dfii_pi0_rddata0_r \libresocsim_interface4_bank_bus_dat_w + connect \libresocsim_csrbank4_dfii_pi0_rddata0_re $and$ls180.v:3273$897_Y + connect \libresocsim_csrbank4_dfii_pi0_rddata0_we $and$ls180.v:3274$901_Y + connect \sdram_sel \sdram_storage [0] + connect \sdram_cke_1 \sdram_storage [1] + connect \sdram_odt \sdram_storage [2] + connect \sdram_reset_n \sdram_storage [3] + connect \libresocsim_csrbank4_dfii_control0_w \sdram_storage + connect \libresocsim_csrbank4_dfii_pi0_command0_w \sdram_command_storage + connect \libresocsim_csrbank4_dfii_pi0_address1_w \sdram_address_storage [12:8] + connect \libresocsim_csrbank4_dfii_pi0_address0_w \sdram_address_storage [7:0] + connect \libresocsim_csrbank4_dfii_pi0_baddress0_w \sdram_baddress_storage + connect \libresocsim_csrbank4_dfii_pi0_wrdata1_w \sdram_wrdata_storage [15:8] + connect \libresocsim_csrbank4_dfii_pi0_wrdata0_w \sdram_wrdata_storage [7:0] + connect \libresocsim_csrbank4_dfii_pi0_rddata1_w \sdram_status [15:8] + connect \libresocsim_csrbank4_dfii_pi0_rddata0_w \sdram_status [7:0] + connect \sdram_we \libresocsim_csrbank4_dfii_pi0_rddata0_we + connect \libresocsim_csrbank5_sel $eq$ls180.v:3289$902_Y + connect \libresocsim_csrbank5_load3_r \libresocsim_interface5_bank_bus_dat_w + connect \libresocsim_csrbank5_load3_re $and$ls180.v:3291$905_Y + connect \libresocsim_csrbank5_load3_we $and$ls180.v:3292$909_Y + connect \libresocsim_csrbank5_load2_r \libresocsim_interface5_bank_bus_dat_w + connect \libresocsim_csrbank5_load2_re $and$ls180.v:3294$912_Y + connect \libresocsim_csrbank5_load2_we $and$ls180.v:3295$916_Y + connect \libresocsim_csrbank5_load1_r \libresocsim_interface5_bank_bus_dat_w + connect \libresocsim_csrbank5_load1_re $and$ls180.v:3297$919_Y + connect \libresocsim_csrbank5_load1_we $and$ls180.v:3298$923_Y + connect \libresocsim_csrbank5_load0_r \libresocsim_interface5_bank_bus_dat_w + connect \libresocsim_csrbank5_load0_re $and$ls180.v:3300$926_Y + connect \libresocsim_csrbank5_load0_we $and$ls180.v:3301$930_Y + connect \libresocsim_csrbank5_reload3_r \libresocsim_interface5_bank_bus_dat_w + connect \libresocsim_csrbank5_reload3_re $and$ls180.v:3303$933_Y + connect \libresocsim_csrbank5_reload3_we $and$ls180.v:3304$937_Y + connect \libresocsim_csrbank5_reload2_r \libresocsim_interface5_bank_bus_dat_w + connect \libresocsim_csrbank5_reload2_re $and$ls180.v:3306$940_Y + connect \libresocsim_csrbank5_reload2_we $and$ls180.v:3307$944_Y + connect \libresocsim_csrbank5_reload1_r \libresocsim_interface5_bank_bus_dat_w + connect \libresocsim_csrbank5_reload1_re $and$ls180.v:3309$947_Y + connect \libresocsim_csrbank5_reload1_we $and$ls180.v:3310$951_Y + connect \libresocsim_csrbank5_reload0_r \libresocsim_interface5_bank_bus_dat_w + connect \libresocsim_csrbank5_reload0_re $and$ls180.v:3312$954_Y + connect \libresocsim_csrbank5_reload0_we $and$ls180.v:3313$958_Y + connect \libresocsim_csrbank5_en0_r \libresocsim_interface5_bank_bus_dat_w [0] + connect \libresocsim_csrbank5_en0_re $and$ls180.v:3315$961_Y + connect \libresocsim_csrbank5_en0_we $and$ls180.v:3316$965_Y + connect \libresocsim_csrbank5_update_value0_r \libresocsim_interface5_bank_bus_dat_w [0] + connect \libresocsim_csrbank5_update_value0_re $and$ls180.v:3318$968_Y + connect \libresocsim_csrbank5_update_value0_we $and$ls180.v:3319$972_Y + connect \libresocsim_csrbank5_value3_r \libresocsim_interface5_bank_bus_dat_w + connect \libresocsim_csrbank5_value3_re $and$ls180.v:3321$975_Y + connect \libresocsim_csrbank5_value3_we $and$ls180.v:3322$979_Y + connect \libresocsim_csrbank5_value2_r \libresocsim_interface5_bank_bus_dat_w + connect \libresocsim_csrbank5_value2_re $and$ls180.v:3324$982_Y + connect \libresocsim_csrbank5_value2_we $and$ls180.v:3325$986_Y + connect \libresocsim_csrbank5_value1_r \libresocsim_interface5_bank_bus_dat_w + connect \libresocsim_csrbank5_value1_re $and$ls180.v:3327$989_Y + connect \libresocsim_csrbank5_value1_we $and$ls180.v:3328$993_Y + connect \libresocsim_csrbank5_value0_r \libresocsim_interface5_bank_bus_dat_w + connect \libresocsim_csrbank5_value0_re $and$ls180.v:3330$996_Y + connect \libresocsim_csrbank5_value0_we $and$ls180.v:3331$1000_Y + connect \libresocsim_eventmanager_status_r \libresocsim_interface5_bank_bus_dat_w [0] + connect \libresocsim_eventmanager_status_re $and$ls180.v:3333$1003_Y + connect \libresocsim_eventmanager_status_we $and$ls180.v:3334$1007_Y + connect \libresocsim_eventmanager_pending_r \libresocsim_interface5_bank_bus_dat_w [0] + connect \libresocsim_eventmanager_pending_re $and$ls180.v:3336$1010_Y + connect \libresocsim_eventmanager_pending_we $and$ls180.v:3337$1014_Y + connect \libresocsim_csrbank5_ev_enable0_r \libresocsim_interface5_bank_bus_dat_w [0] + connect \libresocsim_csrbank5_ev_enable0_re $and$ls180.v:3339$1017_Y + connect \libresocsim_csrbank5_ev_enable0_we $and$ls180.v:3340$1021_Y + connect \libresocsim_csrbank5_load3_w \libresocsim_load_storage [31:24] + connect \libresocsim_csrbank5_load2_w \libresocsim_load_storage [23:16] + connect \libresocsim_csrbank5_load1_w \libresocsim_load_storage [15:8] + connect \libresocsim_csrbank5_load0_w \libresocsim_load_storage [7:0] + connect \libresocsim_csrbank5_reload3_w \libresocsim_reload_storage [31:24] + connect \libresocsim_csrbank5_reload2_w \libresocsim_reload_storage [23:16] + connect \libresocsim_csrbank5_reload1_w \libresocsim_reload_storage [15:8] + connect \libresocsim_csrbank5_reload0_w \libresocsim_reload_storage [7:0] + connect \libresocsim_csrbank5_en0_w \libresocsim_en_storage + connect \libresocsim_csrbank5_update_value0_w \libresocsim_update_value_storage + connect \libresocsim_csrbank5_value3_w \libresocsim_value_status [31:24] + connect \libresocsim_csrbank5_value2_w \libresocsim_value_status [23:16] + connect \libresocsim_csrbank5_value1_w \libresocsim_value_status [15:8] + connect \libresocsim_csrbank5_value0_w \libresocsim_value_status [7:0] + connect \libresocsim_value_we \libresocsim_csrbank5_value0_we + connect \libresocsim_csrbank5_ev_enable0_w \libresocsim_eventmanager_storage + connect \libresocsim_csrbank6_sel $eq$ls180.v:3357$1022_Y + connect \rxtx_r \libresocsim_interface6_bank_bus_dat_w + connect \rxtx_re $and$ls180.v:3359$1025_Y + connect \rxtx_we $and$ls180.v:3360$1029_Y + connect \libresocsim_csrbank6_txfull_r \libresocsim_interface6_bank_bus_dat_w [0] + connect \libresocsim_csrbank6_txfull_re $and$ls180.v:3362$1032_Y + connect \libresocsim_csrbank6_txfull_we $and$ls180.v:3363$1036_Y + connect \libresocsim_csrbank6_rxempty_r \libresocsim_interface6_bank_bus_dat_w [0] + connect \libresocsim_csrbank6_rxempty_re $and$ls180.v:3365$1039_Y + connect \libresocsim_csrbank6_rxempty_we $and$ls180.v:3366$1043_Y + connect \eventmanager_status_r \libresocsim_interface6_bank_bus_dat_w [1:0] + connect \eventmanager_status_re $and$ls180.v:3368$1046_Y + connect \eventmanager_status_we $and$ls180.v:3369$1050_Y + connect \eventmanager_pending_r \libresocsim_interface6_bank_bus_dat_w [1:0] + connect \eventmanager_pending_re $and$ls180.v:3371$1053_Y + connect \eventmanager_pending_we $and$ls180.v:3372$1057_Y + connect \libresocsim_csrbank6_ev_enable0_r \libresocsim_interface6_bank_bus_dat_w [1:0] + connect \libresocsim_csrbank6_ev_enable0_re $and$ls180.v:3374$1060_Y + connect \libresocsim_csrbank6_ev_enable0_we $and$ls180.v:3375$1064_Y + connect \libresocsim_csrbank6_txempty_r \libresocsim_interface6_bank_bus_dat_w [0] + connect \libresocsim_csrbank6_txempty_re $and$ls180.v:3377$1067_Y + connect \libresocsim_csrbank6_txempty_we $and$ls180.v:3378$1071_Y + connect \libresocsim_csrbank6_rxfull_r \libresocsim_interface6_bank_bus_dat_w [0] + connect \libresocsim_csrbank6_rxfull_re $and$ls180.v:3380$1074_Y + connect \libresocsim_csrbank6_rxfull_we $and$ls180.v:3381$1078_Y + connect \libresocsim_csrbank6_txfull_w \txfull_status + connect \txfull_we \libresocsim_csrbank6_txfull_we + connect \libresocsim_csrbank6_rxempty_w \rxempty_status + connect \rxempty_we \libresocsim_csrbank6_rxempty_we + connect \libresocsim_csrbank6_ev_enable0_w \eventmanager_storage + connect \libresocsim_csrbank6_txempty_w \txempty_status + connect \txempty_we \libresocsim_csrbank6_txempty_we + connect \libresocsim_csrbank6_rxfull_w \rxfull_status + connect \rxfull_we \libresocsim_csrbank6_rxfull_we + connect \libresocsim_csrbank7_sel $eq$ls180.v:3391$1079_Y + connect \libresocsim_csrbank7_tuning_word3_r \libresocsim_interface7_bank_bus_dat_w + connect \libresocsim_csrbank7_tuning_word3_re $and$ls180.v:3393$1082_Y + connect \libresocsim_csrbank7_tuning_word3_we $and$ls180.v:3394$1086_Y + connect \libresocsim_csrbank7_tuning_word2_r \libresocsim_interface7_bank_bus_dat_w + connect \libresocsim_csrbank7_tuning_word2_re $and$ls180.v:3396$1089_Y + connect \libresocsim_csrbank7_tuning_word2_we $and$ls180.v:3397$1093_Y + connect \libresocsim_csrbank7_tuning_word1_r \libresocsim_interface7_bank_bus_dat_w + connect \libresocsim_csrbank7_tuning_word1_re $and$ls180.v:3399$1096_Y + connect \libresocsim_csrbank7_tuning_word1_we $and$ls180.v:3400$1100_Y + connect \libresocsim_csrbank7_tuning_word0_r \libresocsim_interface7_bank_bus_dat_w + connect \libresocsim_csrbank7_tuning_word0_re $and$ls180.v:3402$1103_Y + connect \libresocsim_csrbank7_tuning_word0_we $and$ls180.v:3403$1107_Y + connect \libresocsim_csrbank7_tuning_word3_w \uart_phy_storage [31:24] + connect \libresocsim_csrbank7_tuning_word2_w \uart_phy_storage [23:16] + connect \libresocsim_csrbank7_tuning_word1_w \uart_phy_storage [15:8] + connect \libresocsim_csrbank7_tuning_word0_w \uart_phy_storage [7:0] + connect \libresocsim_csr_interconnect_adr \libresocsim_libresocsim_adr + connect \libresocsim_csr_interconnect_we \libresocsim_libresocsim_we + connect \libresocsim_csr_interconnect_dat_w \libresocsim_libresocsim_dat_w + connect \libresocsim_libresocsim_dat_r \libresocsim_csr_interconnect_dat_r + connect \libresocsim_interface0_bank_bus_adr \libresocsim_csr_interconnect_adr + connect \libresocsim_interface1_bank_bus_adr \libresocsim_csr_interconnect_adr + connect \libresocsim_interface2_bank_bus_adr \libresocsim_csr_interconnect_adr + connect \libresocsim_interface3_bank_bus_adr \libresocsim_csr_interconnect_adr + connect \libresocsim_interface4_bank_bus_adr \libresocsim_csr_interconnect_adr + connect \libresocsim_interface5_bank_bus_adr \libresocsim_csr_interconnect_adr + connect \libresocsim_interface6_bank_bus_adr \libresocsim_csr_interconnect_adr + connect \libresocsim_interface7_bank_bus_adr \libresocsim_csr_interconnect_adr + connect \libresocsim_interface0_bank_bus_we \libresocsim_csr_interconnect_we + connect \libresocsim_interface1_bank_bus_we \libresocsim_csr_interconnect_we + connect \libresocsim_interface2_bank_bus_we \libresocsim_csr_interconnect_we + connect \libresocsim_interface3_bank_bus_we \libresocsim_csr_interconnect_we + connect \libresocsim_interface4_bank_bus_we \libresocsim_csr_interconnect_we + connect \libresocsim_interface5_bank_bus_we \libresocsim_csr_interconnect_we + connect \libresocsim_interface6_bank_bus_we \libresocsim_csr_interconnect_we + connect \libresocsim_interface7_bank_bus_we \libresocsim_csr_interconnect_we + connect \libresocsim_interface0_bank_bus_dat_w \libresocsim_csr_interconnect_dat_w + connect \libresocsim_interface1_bank_bus_dat_w \libresocsim_csr_interconnect_dat_w + connect \libresocsim_interface2_bank_bus_dat_w \libresocsim_csr_interconnect_dat_w + connect \libresocsim_interface3_bank_bus_dat_w \libresocsim_csr_interconnect_dat_w + connect \libresocsim_interface4_bank_bus_dat_w \libresocsim_csr_interconnect_dat_w + connect \libresocsim_interface5_bank_bus_dat_w \libresocsim_csr_interconnect_dat_w + connect \libresocsim_interface6_bank_bus_dat_w \libresocsim_csr_interconnect_dat_w + connect \libresocsim_interface7_bank_bus_dat_w \libresocsim_csr_interconnect_dat_w + connect \libresocsim_csr_interconnect_dat_r $or$ls180.v:3436$1114_Y connect \sdrio_clk \sys_clk_1 connect \sdrio_clk_1 \sys_clk_1 connect \sdrio_clk_2 \sys_clk_1 @@ -302377,13 +273398,7 @@ module \ls180 connect \sdrio_clk_53 \sys_clk_1 connect \sdrio_clk_54 \sys_clk_1 connect \sdrio_clk_55 \sys_clk_1 - connect \main_uart_phy_rx \builder_multiregimpl0_regs1 - connect \main_pwm0_enable \main_pwm0_enable_storage - connect \main_pwm0_width \main_pwm0_width_storage - connect \main_pwm0_period \main_pwm0_period_storage - connect \main_pwm1_enable \main_pwm1_enable_storage - connect \main_pwm1_width \main_pwm1_width_storage - connect \main_pwm1_period \main_pwm1_period_storage + connect \uart_phy_rx \regs1 connect \sdrio_clk_56 \sys_clk_1 connect \sdrio_clk_57 \sys_clk_1 connect \sdrio_clk_58 \sys_clk_1 @@ -302397,56 +273412,87 @@ module \ls180 connect \sdrio_clk_66 \sys_clk_1 connect \sdrio_clk_67 \sys_clk_1 connect \sdrio_clk_68 \sys_clk_1 - connect \main_libresocsim_dat_r $memrd$\mem$ls180.v:10164$2768_DATA - connect \main_ram_dat_r $memrd$\mem_1$ls180.v:10192$2794_DATA - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r \memdat - connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:10210$2801_DATA - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r \memdat_1 - connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:10224$2808_DATA - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r \memdat_2 - connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:10238$2815_DATA - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r \memdat_3 - connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:10252$2822_DATA - connect \main_uart_tx_fifo_wrport_dat_r \memdat_4 - connect \main_uart_tx_fifo_rdport_dat_r \memdat_5 - connect \main_uart_rx_fifo_wrport_dat_r \memdat_6 - connect \main_uart_rx_fifo_rdport_dat_r \memdat_7 - connect \main_sdblock2mem_fifo_wrport_dat_r \memdat_8 - connect \main_sdblock2mem_fifo_rdport_dat_r $memrd$\storage_6$ls180.v:10300$2843_DATA - connect \main_sdmem2block_fifo_wrport_dat_r \memdat_9 - connect \main_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$ls180.v:10314$2850_DATA + connect \sdrio_clk_69 \sys_clk_1 + connect \sdrio_clk_70 \sys_clk_1 + connect \sdrio_clk_71 \sys_clk_1 + connect \sdrio_clk_72 \sys_clk_1 + connect \sdrio_clk_73 \sys_clk_1 + connect \sdrio_clk_74 \sys_clk_1 + connect \sdrio_clk_75 \sys_clk_1 + connect \sdrio_clk_76 \sys_clk_1 + connect \sdrio_clk_77 \sys_clk_1 + connect \sdrio_clk_78 \sys_clk_1 + connect \sdrio_clk_79 \sys_clk_1 + connect \sdrio_clk_80 \sys_clk_1 + connect \sdrio_clk_81 \sys_clk_1 + connect \sdrio_clk_82 \sys_clk_1 + connect \sdrio_clk_83 \sys_clk_1 + connect \sdrio_clk_84 \sys_clk_1 + connect \sdrio_clk_85 \sys_clk_1 + connect \sdrio_clk_86 \sys_clk_1 + connect \sdrio_clk_87 \sys_clk_1 + connect \sdrio_clk_88 \sys_clk_1 + connect \sdrio_clk_89 \sys_clk_1 + connect \sdrio_clk_90 \sys_clk_1 + connect \sdrio_clk_91 \sys_clk_1 + connect \sdrio_clk_92 \sys_clk_1 + connect \sdrio_clk_93 \sys_clk_1 + connect \sdrio_clk_94 \sys_clk_1 + connect \sdrio_clk_95 \sys_clk_1 + connect \sdrio_clk_96 \sys_clk_1 + connect \sdrio_clk_97 \sys_clk_1 + connect \sdrio_clk_98 \sys_clk_1 + connect \sdrio_clk_99 \sys_clk_1 + connect \sdrio_clk_100 \sys_clk_1 + connect \sdrio_clk_101 \sys_clk_1 + connect \sdrio_clk_102 \sys_clk_1 + connect \sdrio_clk_103 \sys_clk_1 + connect \libresocsim_dat_r $memrd$\mem$ls180.v:5511$1508_DATA + connect \ram_dat_r $memrd$\mem_1$ls180.v:5539$1558_DATA + connect \sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r \memdat + connect \sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage$ls180.v:5557$1568_DATA + connect \sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r \memdat_1 + connect \sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_1$ls180.v:5571$1578_DATA + connect \sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r \memdat_2 + connect \sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$ls180.v:5585$1588_DATA + connect \sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r \memdat_3 + connect \sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$ls180.v:5599$1598_DATA + connect \tx_fifo_wrport_dat_r \memdat_4 + connect \tx_fifo_rdport_dat_r \memdat_5 + connect \rx_fifo_wrport_dat_r \memdat_6 + connect \rx_fifo_rdport_dat_r \memdat_7 end -attribute \src "libresoc.v:146561.1-146619.10" +attribute \src "libresoc.v:147441.1-147499.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.lsd_l" attribute \generator "nMigen" module \lsd_l - attribute \src "libresoc.v:146562.7-146562.20" + attribute \src "libresoc.v:147442.7-147442.20" wire $0\initial[0:0] - attribute \src "libresoc.v:146607.3-146615.6" - wire $0\q_int$next[0:0]$7149 - attribute \src "libresoc.v:146605.3-146606.27" + attribute \src "libresoc.v:147487.3-147495.6" + wire $0\q_int$next[0:0]$7133 + attribute \src "libresoc.v:147485.3-147486.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:146607.3-146615.6" - wire $1\q_int$next[0:0]$7150 - attribute \src "libresoc.v:146584.7-146584.19" + attribute \src "libresoc.v:147487.3-147495.6" + wire $1\q_int$next[0:0]$7134 + attribute \src "libresoc.v:147464.7-147464.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:146597.17-146597.96" - wire $and$libresoc.v:146597$7139_Y - attribute \src "libresoc.v:146602.17-146602.96" - wire $and$libresoc.v:146602$7144_Y - attribute \src "libresoc.v:146599.18-146599.93" - wire $not$libresoc.v:146599$7141_Y - attribute \src "libresoc.v:146601.17-146601.92" - wire $not$libresoc.v:146601$7143_Y - attribute \src "libresoc.v:146604.17-146604.92" - wire $not$libresoc.v:146604$7146_Y - attribute \src "libresoc.v:146598.18-146598.98" - wire $or$libresoc.v:146598$7140_Y - attribute \src "libresoc.v:146600.18-146600.99" - wire $or$libresoc.v:146600$7142_Y - attribute \src "libresoc.v:146603.17-146603.97" - wire $or$libresoc.v:146603$7145_Y + attribute \src "libresoc.v:147477.17-147477.96" + wire $and$libresoc.v:147477$7123_Y + attribute \src "libresoc.v:147482.17-147482.96" + wire $and$libresoc.v:147482$7128_Y + attribute \src "libresoc.v:147479.18-147479.93" + wire $not$libresoc.v:147479$7125_Y + attribute \src "libresoc.v:147481.17-147481.92" + wire $not$libresoc.v:147481$7127_Y + attribute \src "libresoc.v:147484.17-147484.92" + wire $not$libresoc.v:147484$7130_Y + attribute \src "libresoc.v:147478.18-147478.98" + wire $or$libresoc.v:147478$7124_Y + attribute \src "libresoc.v:147480.18-147480.99" + wire $or$libresoc.v:147480$7126_Y + attribute \src "libresoc.v:147483.17-147483.97" + wire $or$libresoc.v:147483$7129_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -302463,11 +273509,11 @@ module \lsd_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:146562.7-146562.15" + attribute \src "libresoc.v:147442.7-147442.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -302484,7 +273530,7 @@ module \lsd_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_lsd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:146597$7139 + cell $and $and$libresoc.v:147477$7123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -302492,10 +273538,10 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:146597$7139_Y + connect \Y $and$libresoc.v:147477$7123_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:146602$7144 + cell $and $and$libresoc.v:147482$7128 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -302503,34 +273549,34 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:146602$7144_Y + connect \Y $and$libresoc.v:147482$7128_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:146599$7141 + cell $not $not$libresoc.v:147479$7125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_lsd - connect \Y $not$libresoc.v:146599$7141_Y + connect \Y $not$libresoc.v:147479$7125_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:146601$7143 + cell $not $not$libresoc.v:147481$7127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_lsd - connect \Y $not$libresoc.v:146601$7143_Y + connect \Y $not$libresoc.v:147481$7127_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:146604$7146 + cell $not $not$libresoc.v:147484$7130 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_lsd - connect \Y $not$libresoc.v:146604$7146_Y + connect \Y $not$libresoc.v:147484$7130_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:146598$7140 + cell $or $or$libresoc.v:147478$7124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -302538,10 +273584,10 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_lsd - connect \Y $or$libresoc.v:146598$7140_Y + connect \Y $or$libresoc.v:147478$7124_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:146600$7142 + cell $or $or$libresoc.v:147480$7126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -302549,10 +273595,10 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \q_lsd connect \B \q_int - connect \Y $or$libresoc.v:146600$7142_Y + connect \Y $or$libresoc.v:147480$7126_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:146603$7145 + cell $or $or$libresoc.v:147483$7129 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -302560,39 +273606,39 @@ module \lsd_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_lsd - connect \Y $or$libresoc.v:146603$7145_Y + connect \Y $or$libresoc.v:147483$7129_Y end - attribute \src "libresoc.v:146562.7-146562.20" - process $proc$libresoc.v:146562$7151 + attribute \src "libresoc.v:147442.7-147442.20" + process $proc$libresoc.v:147442$7135 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:146584.7-146584.19" - process $proc$libresoc.v:146584$7152 + attribute \src "libresoc.v:147464.7-147464.19" + process $proc$libresoc.v:147464$7136 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:146605.3-146606.27" - process $proc$libresoc.v:146605$7147 + attribute \src "libresoc.v:147485.3-147486.27" + process $proc$libresoc.v:147485$7131 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:146607.3-146615.6" - process $proc$libresoc.v:146607$7148 + attribute \src "libresoc.v:147487.3-147495.6" + process $proc$libresoc.v:147487$7132 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$7149 $1\q_int$next[0:0]$7150 - attribute \src "libresoc.v:146608.5-146608.29" + assign $0\q_int$next[0:0]$7133 $1\q_int$next[0:0]$7134 + attribute \src "libresoc.v:147488.5-147488.29" switch \initial - attribute \src "libresoc.v:146608.9-146608.17" + attribute \src "libresoc.v:147488.9-147488.17" case 1'1 case end @@ -302601,266 +273647,266 @@ module \lsd_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$7150 1'0 + assign $1\q_int$next[0:0]$7134 1'0 case - assign $1\q_int$next[0:0]$7150 \$5 + assign $1\q_int$next[0:0]$7134 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$7149 + update \q_int$next $0\q_int$next[0:0]$7133 end - connect \$9 $and$libresoc.v:146597$7139_Y - connect \$11 $or$libresoc.v:146598$7140_Y - connect \$13 $not$libresoc.v:146599$7141_Y - connect \$15 $or$libresoc.v:146600$7142_Y - connect \$1 $not$libresoc.v:146601$7143_Y - connect \$3 $and$libresoc.v:146602$7144_Y - connect \$5 $or$libresoc.v:146603$7145_Y - connect \$7 $not$libresoc.v:146604$7146_Y + connect \$9 $and$libresoc.v:147477$7123_Y + connect \$11 $or$libresoc.v:147478$7124_Y + connect \$13 $not$libresoc.v:147479$7125_Y + connect \$15 $or$libresoc.v:147480$7126_Y + connect \$1 $not$libresoc.v:147481$7127_Y + connect \$3 $and$libresoc.v:147482$7128_Y + connect \$5 $or$libresoc.v:147483$7129_Y + connect \$7 $not$libresoc.v:147484$7130_Y connect \qlq_lsd \$15 connect \qn_lsd \$13 connect \q_lsd \$11 end -attribute \src "libresoc.v:146623.1-147157.10" +attribute \src "libresoc.v:147503.1-148037.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.lsmem" attribute \generator "nMigen" module \lsmem - attribute \src "libresoc.v:147011.3-147036.6" - wire width 45 $0\dbus__adr$next[44:0]$7238 - attribute \src "libresoc.v:146861.3-146862.35" + attribute \src "libresoc.v:147891.3-147916.6" + wire width 45 $0\dbus__adr$next[44:0]$7222 + attribute \src "libresoc.v:147741.3-147742.35" wire width 45 $0\dbus__adr[44:0] - attribute \src "libresoc.v:146871.3-146898.6" - wire $0\dbus__cyc$next[0:0]$7212 - attribute \src "libresoc.v:146869.3-146870.35" + attribute \src "libresoc.v:147751.3-147778.6" + wire $0\dbus__cyc$next[0:0]$7196 + attribute \src "libresoc.v:147749.3-147750.35" wire $0\dbus__cyc[0:0] - attribute \src "libresoc.v:147063.3-147088.6" - wire width 64 $0\dbus__dat_w$next[63:0]$7248 - attribute \src "libresoc.v:146857.3-146858.39" + attribute \src "libresoc.v:147943.3-147968.6" + wire width 64 $0\dbus__dat_w$next[63:0]$7232 + attribute \src "libresoc.v:147737.3-147738.39" wire width 64 $0\dbus__dat_w[63:0] - attribute \src "libresoc.v:146955.3-146985.6" - wire width 8 $0\dbus__sel$next[7:0]$7226 - attribute \src "libresoc.v:146865.3-146866.35" + attribute \src "libresoc.v:147835.3-147865.6" + wire width 8 $0\dbus__sel$next[7:0]$7210 + attribute \src "libresoc.v:147745.3-147746.35" wire width 8 $0\dbus__sel[7:0] - attribute \src "libresoc.v:146899.3-146926.6" - wire $0\dbus__stb$next[0:0]$7218 - attribute \src "libresoc.v:146867.3-146868.35" + attribute \src "libresoc.v:147779.3-147806.6" + wire $0\dbus__stb$next[0:0]$7202 + attribute \src "libresoc.v:147747.3-147748.35" wire $0\dbus__stb[0:0] - attribute \src "libresoc.v:147037.3-147062.6" - wire $0\dbus__we$next[0:0]$7243 - attribute \src "libresoc.v:146859.3-146860.33" + attribute \src "libresoc.v:147917.3-147942.6" + wire $0\dbus__we$next[0:0]$7227 + attribute \src "libresoc.v:147739.3-147740.33" wire $0\dbus__we[0:0] - attribute \src "libresoc.v:146624.7-146624.20" + attribute \src "libresoc.v:147504.7-147504.20" wire $0\initial[0:0] - attribute \src "libresoc.v:147135.3-147154.6" - wire width 45 $0\m_badaddr_o$next[44:0]$7263 - attribute \src "libresoc.v:146851.3-146852.39" + attribute \src "libresoc.v:148015.3-148034.6" + wire width 45 $0\m_badaddr_o$next[44:0]$7247 + attribute \src "libresoc.v:147731.3-147732.39" wire width 45 $0\m_badaddr_o[44:0] - attribute \src "libresoc.v:146937.3-146954.6" + attribute \src "libresoc.v:147817.3-147834.6" wire $0\m_busy_o[0:0] - attribute \src "libresoc.v:146986.3-147010.6" - wire width 64 $0\m_ld_data_o$next[63:0]$7232 - attribute \src "libresoc.v:146863.3-146864.39" + attribute \src "libresoc.v:147866.3-147890.6" + wire width 64 $0\m_ld_data_o$next[63:0]$7216 + attribute \src "libresoc.v:147743.3-147744.39" wire width 64 $0\m_ld_data_o[63:0] - attribute \src "libresoc.v:147089.3-147111.6" - wire $0\m_load_err_o$next[0:0]$7253 - attribute \src "libresoc.v:146855.3-146856.41" + attribute \src "libresoc.v:147969.3-147991.6" + wire $0\m_load_err_o$next[0:0]$7237 + attribute \src "libresoc.v:147735.3-147736.41" wire $0\m_load_err_o[0:0] - attribute \src "libresoc.v:147112.3-147134.6" - wire $0\m_store_err_o$next[0:0]$7258 - attribute \src "libresoc.v:146853.3-146854.43" + attribute \src "libresoc.v:147992.3-148014.6" + wire $0\m_store_err_o$next[0:0]$7242 + attribute \src "libresoc.v:147733.3-147734.43" wire $0\m_store_err_o[0:0] - attribute \src "libresoc.v:146927.3-146936.6" + attribute \src "libresoc.v:147807.3-147816.6" wire $0\x_busy_o[0:0] - attribute \src "libresoc.v:147011.3-147036.6" - wire width 45 $1\dbus__adr$next[44:0]$7239 - attribute \src "libresoc.v:146729.14-146729.42" + attribute \src "libresoc.v:147891.3-147916.6" + wire width 45 $1\dbus__adr$next[44:0]$7223 + attribute \src "libresoc.v:147609.14-147609.42" wire width 45 $1\dbus__adr[44:0] - attribute \src "libresoc.v:146871.3-146898.6" - wire $1\dbus__cyc$next[0:0]$7213 - attribute \src "libresoc.v:146734.7-146734.23" + attribute \src "libresoc.v:147751.3-147778.6" + wire $1\dbus__cyc$next[0:0]$7197 + attribute \src "libresoc.v:147614.7-147614.23" wire $1\dbus__cyc[0:0] - attribute \src "libresoc.v:147063.3-147088.6" - wire width 64 $1\dbus__dat_w$next[63:0]$7249 - attribute \src "libresoc.v:146741.14-146741.48" + attribute \src "libresoc.v:147943.3-147968.6" + wire width 64 $1\dbus__dat_w$next[63:0]$7233 + attribute \src "libresoc.v:147621.14-147621.48" wire width 64 $1\dbus__dat_w[63:0] - attribute \src "libresoc.v:146955.3-146985.6" - wire width 8 $1\dbus__sel$next[7:0]$7227 - attribute \src "libresoc.v:146748.13-146748.30" + attribute \src "libresoc.v:147835.3-147865.6" + wire width 8 $1\dbus__sel$next[7:0]$7211 + attribute \src "libresoc.v:147628.13-147628.30" wire width 8 $1\dbus__sel[7:0] - attribute \src "libresoc.v:146899.3-146926.6" - wire $1\dbus__stb$next[0:0]$7219 - attribute \src "libresoc.v:146753.7-146753.23" + attribute \src "libresoc.v:147779.3-147806.6" + wire $1\dbus__stb$next[0:0]$7203 + attribute \src "libresoc.v:147633.7-147633.23" wire $1\dbus__stb[0:0] - attribute \src "libresoc.v:147037.3-147062.6" - wire $1\dbus__we$next[0:0]$7244 - attribute \src "libresoc.v:146758.7-146758.22" + attribute \src "libresoc.v:147917.3-147942.6" + wire $1\dbus__we$next[0:0]$7228 + attribute \src "libresoc.v:147638.7-147638.22" wire $1\dbus__we[0:0] - attribute \src "libresoc.v:147135.3-147154.6" - wire width 45 $1\m_badaddr_o$next[44:0]$7264 - attribute \src "libresoc.v:146762.14-146762.44" + attribute \src "libresoc.v:148015.3-148034.6" + wire width 45 $1\m_badaddr_o$next[44:0]$7248 + attribute \src "libresoc.v:147642.14-147642.44" wire width 45 $1\m_badaddr_o[44:0] - attribute \src "libresoc.v:146937.3-146954.6" + attribute \src "libresoc.v:147817.3-147834.6" wire $1\m_busy_o[0:0] - attribute \src "libresoc.v:146986.3-147010.6" - wire width 64 $1\m_ld_data_o$next[63:0]$7233 - attribute \src "libresoc.v:146769.14-146769.48" + attribute \src "libresoc.v:147866.3-147890.6" + wire width 64 $1\m_ld_data_o$next[63:0]$7217 + attribute \src "libresoc.v:147649.14-147649.48" wire width 64 $1\m_ld_data_o[63:0] - attribute \src "libresoc.v:147089.3-147111.6" - wire $1\m_load_err_o$next[0:0]$7254 - attribute \src "libresoc.v:146773.7-146773.26" + attribute \src "libresoc.v:147969.3-147991.6" + wire $1\m_load_err_o$next[0:0]$7238 + attribute \src "libresoc.v:147653.7-147653.26" wire $1\m_load_err_o[0:0] - attribute \src "libresoc.v:147112.3-147134.6" - wire $1\m_store_err_o$next[0:0]$7259 - attribute \src "libresoc.v:146779.7-146779.27" + attribute \src "libresoc.v:147992.3-148014.6" + wire $1\m_store_err_o$next[0:0]$7243 + attribute \src "libresoc.v:147659.7-147659.27" wire $1\m_store_err_o[0:0] - attribute \src "libresoc.v:146927.3-146936.6" + attribute \src "libresoc.v:147807.3-147816.6" wire $1\x_busy_o[0:0] - attribute \src "libresoc.v:147011.3-147036.6" - wire width 45 $2\dbus__adr$next[44:0]$7240 - attribute \src "libresoc.v:146871.3-146898.6" - wire $2\dbus__cyc$next[0:0]$7214 - attribute \src "libresoc.v:147063.3-147088.6" - wire width 64 $2\dbus__dat_w$next[63:0]$7250 - attribute \src "libresoc.v:146955.3-146985.6" - wire width 8 $2\dbus__sel$next[7:0]$7228 - attribute \src "libresoc.v:146899.3-146926.6" - wire $2\dbus__stb$next[0:0]$7220 - attribute \src "libresoc.v:147037.3-147062.6" - wire $2\dbus__we$next[0:0]$7245 - attribute \src "libresoc.v:147135.3-147154.6" - wire width 45 $2\m_badaddr_o$next[44:0]$7265 - attribute \src "libresoc.v:146937.3-146954.6" + attribute \src "libresoc.v:147891.3-147916.6" + wire width 45 $2\dbus__adr$next[44:0]$7224 + attribute \src "libresoc.v:147751.3-147778.6" + wire $2\dbus__cyc$next[0:0]$7198 + attribute \src "libresoc.v:147943.3-147968.6" + wire width 64 $2\dbus__dat_w$next[63:0]$7234 + attribute \src "libresoc.v:147835.3-147865.6" + wire width 8 $2\dbus__sel$next[7:0]$7212 + attribute \src "libresoc.v:147779.3-147806.6" + wire $2\dbus__stb$next[0:0]$7204 + attribute \src "libresoc.v:147917.3-147942.6" + wire $2\dbus__we$next[0:0]$7229 + attribute \src "libresoc.v:148015.3-148034.6" + wire width 45 $2\m_badaddr_o$next[44:0]$7249 + attribute \src "libresoc.v:147817.3-147834.6" wire $2\m_busy_o[0:0] - attribute \src "libresoc.v:146986.3-147010.6" - wire width 64 $2\m_ld_data_o$next[63:0]$7234 - attribute \src "libresoc.v:147089.3-147111.6" - wire $2\m_load_err_o$next[0:0]$7255 - attribute \src "libresoc.v:147112.3-147134.6" - wire $2\m_store_err_o$next[0:0]$7260 - attribute \src "libresoc.v:147011.3-147036.6" - wire width 45 $3\dbus__adr$next[44:0]$7241 - attribute \src "libresoc.v:146871.3-146898.6" - wire $3\dbus__cyc$next[0:0]$7215 - attribute \src "libresoc.v:147063.3-147088.6" - wire width 64 $3\dbus__dat_w$next[63:0]$7251 - attribute \src "libresoc.v:146955.3-146985.6" - wire width 8 $3\dbus__sel$next[7:0]$7229 - attribute \src "libresoc.v:146899.3-146926.6" - wire $3\dbus__stb$next[0:0]$7221 - attribute \src "libresoc.v:147037.3-147062.6" - wire $3\dbus__we$next[0:0]$7246 - attribute \src "libresoc.v:147135.3-147154.6" - wire width 45 $3\m_badaddr_o$next[44:0]$7266 - attribute \src "libresoc.v:146986.3-147010.6" - wire width 64 $3\m_ld_data_o$next[63:0]$7235 - attribute \src "libresoc.v:147089.3-147111.6" - wire $3\m_load_err_o$next[0:0]$7256 - attribute \src "libresoc.v:147112.3-147134.6" - wire $3\m_store_err_o$next[0:0]$7261 - attribute \src "libresoc.v:146871.3-146898.6" - wire $4\dbus__cyc$next[0:0]$7216 - attribute \src "libresoc.v:146955.3-146985.6" - wire width 8 $4\dbus__sel$next[7:0]$7230 - attribute \src "libresoc.v:146899.3-146926.6" - wire $4\dbus__stb$next[0:0]$7222 - attribute \src "libresoc.v:146986.3-147010.6" - wire width 64 $4\m_ld_data_o$next[63:0]$7236 - attribute \src "libresoc.v:146807.18-146807.116" - wire $and$libresoc.v:146807$7157_Y - attribute \src "libresoc.v:146810.18-146810.111" - wire $and$libresoc.v:146810$7160_Y - attribute \src "libresoc.v:146815.18-146815.116" - wire $and$libresoc.v:146815$7165_Y - attribute \src "libresoc.v:146817.18-146817.111" - wire $and$libresoc.v:146817$7167_Y - attribute \src "libresoc.v:146819.17-146819.114" - wire $and$libresoc.v:146819$7169_Y - attribute \src "libresoc.v:146823.18-146823.116" - wire $and$libresoc.v:146823$7173_Y - attribute \src "libresoc.v:146825.18-146825.111" - wire $and$libresoc.v:146825$7175_Y - attribute \src "libresoc.v:146831.18-146831.116" - wire $and$libresoc.v:146831$7181_Y - attribute \src "libresoc.v:146833.18-146833.111" - wire $and$libresoc.v:146833$7183_Y - attribute \src "libresoc.v:146835.18-146835.116" - wire $and$libresoc.v:146835$7185_Y - attribute \src "libresoc.v:146837.18-146837.111" - wire $and$libresoc.v:146837$7187_Y - attribute \src "libresoc.v:146839.18-146839.116" - wire $and$libresoc.v:146839$7189_Y - attribute \src "libresoc.v:146841.17-146841.108" - wire $and$libresoc.v:146841$7191_Y - attribute \src "libresoc.v:146842.18-146842.111" - wire $and$libresoc.v:146842$7192_Y - attribute \src "libresoc.v:146843.18-146843.120" - wire $and$libresoc.v:146843$7193_Y - attribute \src "libresoc.v:146846.18-146846.120" - wire $and$libresoc.v:146846$7196_Y - attribute \src "libresoc.v:146848.18-146848.120" - wire $and$libresoc.v:146848$7198_Y - attribute \src "libresoc.v:146804.18-146804.110" - wire $not$libresoc.v:146804$7154_Y - attribute \src "libresoc.v:146809.18-146809.110" - wire $not$libresoc.v:146809$7159_Y - attribute \src "libresoc.v:146812.18-146812.110" - wire $not$libresoc.v:146812$7162_Y - attribute \src "libresoc.v:146816.18-146816.110" - wire $not$libresoc.v:146816$7166_Y - attribute \src "libresoc.v:146820.18-146820.110" - wire $not$libresoc.v:146820$7170_Y - attribute \src "libresoc.v:146824.18-146824.110" - wire $not$libresoc.v:146824$7174_Y - attribute \src "libresoc.v:146827.18-146827.110" - wire $not$libresoc.v:146827$7177_Y - attribute \src "libresoc.v:146830.17-146830.109" - wire $not$libresoc.v:146830$7180_Y - attribute \src "libresoc.v:146832.18-146832.110" - wire $not$libresoc.v:146832$7182_Y - attribute \src "libresoc.v:146836.18-146836.110" - wire $not$libresoc.v:146836$7186_Y - attribute \src "libresoc.v:146840.18-146840.110" - wire $not$libresoc.v:146840$7190_Y - attribute \src "libresoc.v:146844.18-146844.110" - wire $not$libresoc.v:146844$7194_Y - attribute \src "libresoc.v:146845.18-146845.109" - wire $not$libresoc.v:146845$7195_Y - attribute \src "libresoc.v:146847.18-146847.110" - wire $not$libresoc.v:146847$7197_Y - attribute \src "libresoc.v:146849.18-146849.110" - wire $not$libresoc.v:146849$7199_Y - attribute \src "libresoc.v:146803.17-146803.119" - wire $or$libresoc.v:146803$7153_Y - attribute \src "libresoc.v:146805.18-146805.110" - wire $or$libresoc.v:146805$7155_Y - attribute \src "libresoc.v:146806.18-146806.114" - wire $or$libresoc.v:146806$7156_Y - attribute \src "libresoc.v:146808.17-146808.113" - wire $or$libresoc.v:146808$7158_Y - attribute \src "libresoc.v:146811.18-146811.120" - wire $or$libresoc.v:146811$7161_Y - attribute \src "libresoc.v:146813.18-146813.111" - wire $or$libresoc.v:146813$7163_Y - attribute \src "libresoc.v:146814.18-146814.114" - wire $or$libresoc.v:146814$7164_Y - attribute \src "libresoc.v:146818.18-146818.120" - wire $or$libresoc.v:146818$7168_Y - attribute \src "libresoc.v:146821.18-146821.111" - wire $or$libresoc.v:146821$7171_Y - attribute \src "libresoc.v:146822.18-146822.114" - wire $or$libresoc.v:146822$7172_Y - attribute \src "libresoc.v:146826.18-146826.120" - wire $or$libresoc.v:146826$7176_Y - attribute \src "libresoc.v:146828.18-146828.111" - wire $or$libresoc.v:146828$7178_Y - attribute \src "libresoc.v:146829.18-146829.114" - wire $or$libresoc.v:146829$7179_Y - attribute \src "libresoc.v:146834.18-146834.114" - wire $or$libresoc.v:146834$7184_Y - attribute \src "libresoc.v:146838.18-146838.114" - wire $or$libresoc.v:146838$7188_Y - attribute \src "libresoc.v:146850.18-146850.127" - wire $or$libresoc.v:146850$7200_Y + attribute \src "libresoc.v:147866.3-147890.6" + wire width 64 $2\m_ld_data_o$next[63:0]$7218 + attribute \src "libresoc.v:147969.3-147991.6" + wire $2\m_load_err_o$next[0:0]$7239 + attribute \src "libresoc.v:147992.3-148014.6" + wire $2\m_store_err_o$next[0:0]$7244 + attribute \src "libresoc.v:147891.3-147916.6" + wire width 45 $3\dbus__adr$next[44:0]$7225 + attribute \src "libresoc.v:147751.3-147778.6" + wire $3\dbus__cyc$next[0:0]$7199 + attribute \src "libresoc.v:147943.3-147968.6" + wire width 64 $3\dbus__dat_w$next[63:0]$7235 + attribute \src "libresoc.v:147835.3-147865.6" + wire width 8 $3\dbus__sel$next[7:0]$7213 + attribute \src "libresoc.v:147779.3-147806.6" + wire $3\dbus__stb$next[0:0]$7205 + attribute \src "libresoc.v:147917.3-147942.6" + wire $3\dbus__we$next[0:0]$7230 + attribute \src "libresoc.v:148015.3-148034.6" + wire width 45 $3\m_badaddr_o$next[44:0]$7250 + attribute \src "libresoc.v:147866.3-147890.6" + wire width 64 $3\m_ld_data_o$next[63:0]$7219 + attribute \src "libresoc.v:147969.3-147991.6" + wire $3\m_load_err_o$next[0:0]$7240 + attribute \src "libresoc.v:147992.3-148014.6" + wire $3\m_store_err_o$next[0:0]$7245 + attribute \src "libresoc.v:147751.3-147778.6" + wire $4\dbus__cyc$next[0:0]$7200 + attribute \src "libresoc.v:147835.3-147865.6" + wire width 8 $4\dbus__sel$next[7:0]$7214 + attribute \src "libresoc.v:147779.3-147806.6" + wire $4\dbus__stb$next[0:0]$7206 + attribute \src "libresoc.v:147866.3-147890.6" + wire width 64 $4\m_ld_data_o$next[63:0]$7220 + attribute \src "libresoc.v:147687.18-147687.116" + wire $and$libresoc.v:147687$7141_Y + attribute \src "libresoc.v:147690.18-147690.111" + wire $and$libresoc.v:147690$7144_Y + attribute \src "libresoc.v:147695.18-147695.116" + wire $and$libresoc.v:147695$7149_Y + attribute \src "libresoc.v:147697.18-147697.111" + wire $and$libresoc.v:147697$7151_Y + attribute \src "libresoc.v:147699.17-147699.114" + wire $and$libresoc.v:147699$7153_Y + attribute \src "libresoc.v:147703.18-147703.116" + wire $and$libresoc.v:147703$7157_Y + attribute \src "libresoc.v:147705.18-147705.111" + wire $and$libresoc.v:147705$7159_Y + attribute \src "libresoc.v:147711.18-147711.116" + wire $and$libresoc.v:147711$7165_Y + attribute \src "libresoc.v:147713.18-147713.111" + wire $and$libresoc.v:147713$7167_Y + attribute \src "libresoc.v:147715.18-147715.116" + wire $and$libresoc.v:147715$7169_Y + attribute \src "libresoc.v:147717.18-147717.111" + wire $and$libresoc.v:147717$7171_Y + attribute \src "libresoc.v:147719.18-147719.116" + wire $and$libresoc.v:147719$7173_Y + attribute \src "libresoc.v:147721.17-147721.108" + wire $and$libresoc.v:147721$7175_Y + attribute \src "libresoc.v:147722.18-147722.111" + wire $and$libresoc.v:147722$7176_Y + attribute \src "libresoc.v:147723.18-147723.120" + wire $and$libresoc.v:147723$7177_Y + attribute \src "libresoc.v:147726.18-147726.120" + wire $and$libresoc.v:147726$7180_Y + attribute \src "libresoc.v:147728.18-147728.120" + wire $and$libresoc.v:147728$7182_Y + attribute \src "libresoc.v:147684.18-147684.110" + wire $not$libresoc.v:147684$7138_Y + attribute \src "libresoc.v:147689.18-147689.110" + wire $not$libresoc.v:147689$7143_Y + attribute \src "libresoc.v:147692.18-147692.110" + wire $not$libresoc.v:147692$7146_Y + attribute \src "libresoc.v:147696.18-147696.110" + wire $not$libresoc.v:147696$7150_Y + attribute \src "libresoc.v:147700.18-147700.110" + wire $not$libresoc.v:147700$7154_Y + attribute \src "libresoc.v:147704.18-147704.110" + wire $not$libresoc.v:147704$7158_Y + attribute \src "libresoc.v:147707.18-147707.110" + wire $not$libresoc.v:147707$7161_Y + attribute \src "libresoc.v:147710.17-147710.109" + wire $not$libresoc.v:147710$7164_Y + attribute \src "libresoc.v:147712.18-147712.110" + wire $not$libresoc.v:147712$7166_Y + attribute \src "libresoc.v:147716.18-147716.110" + wire $not$libresoc.v:147716$7170_Y + attribute \src "libresoc.v:147720.18-147720.110" + wire $not$libresoc.v:147720$7174_Y + attribute \src "libresoc.v:147724.18-147724.110" + wire $not$libresoc.v:147724$7178_Y + attribute \src "libresoc.v:147725.18-147725.109" + wire $not$libresoc.v:147725$7179_Y + attribute \src "libresoc.v:147727.18-147727.110" + wire $not$libresoc.v:147727$7181_Y + attribute \src "libresoc.v:147729.18-147729.110" + wire $not$libresoc.v:147729$7183_Y + attribute \src "libresoc.v:147683.17-147683.119" + wire $or$libresoc.v:147683$7137_Y + attribute \src "libresoc.v:147685.18-147685.110" + wire $or$libresoc.v:147685$7139_Y + attribute \src "libresoc.v:147686.18-147686.114" + wire $or$libresoc.v:147686$7140_Y + attribute \src "libresoc.v:147688.17-147688.113" + wire $or$libresoc.v:147688$7142_Y + attribute \src "libresoc.v:147691.18-147691.120" + wire $or$libresoc.v:147691$7145_Y + attribute \src "libresoc.v:147693.18-147693.111" + wire $or$libresoc.v:147693$7147_Y + attribute \src "libresoc.v:147694.18-147694.114" + wire $or$libresoc.v:147694$7148_Y + attribute \src "libresoc.v:147698.18-147698.120" + wire $or$libresoc.v:147698$7152_Y + attribute \src "libresoc.v:147701.18-147701.111" + wire $or$libresoc.v:147701$7155_Y + attribute \src "libresoc.v:147702.18-147702.114" + wire $or$libresoc.v:147702$7156_Y + attribute \src "libresoc.v:147706.18-147706.120" + wire $or$libresoc.v:147706$7160_Y + attribute \src "libresoc.v:147708.18-147708.111" + wire $or$libresoc.v:147708$7162_Y + attribute \src "libresoc.v:147709.18-147709.114" + wire $or$libresoc.v:147709$7163_Y + attribute \src "libresoc.v:147714.18-147714.114" + wire $or$libresoc.v:147714$7168_Y + attribute \src "libresoc.v:147718.18-147718.114" + wire $or$libresoc.v:147718$7172_Y + attribute \src "libresoc.v:147730.18-147730.127" + wire $or$libresoc.v:147730$7184_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" @@ -302957,9 +274003,9 @@ module \lsmem wire \$93 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" wire \$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 21 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire input 13 \dbus__ack @@ -302991,7 +274037,7 @@ module \lsmem wire output 19 \dbus__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" wire \dbus__we$next - attribute \src "libresoc.v:146624.7-146624.15" + attribute \src "libresoc.v:147504.7-147504.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:77" wire width 45 \m_badaddr_o @@ -303034,7 +274080,7 @@ module \lsmem attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57" wire input 10 \x_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:146807$7157 + cell $and $and$libresoc.v:147687$7141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303042,10 +274088,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$15 connect \B \x_valid_i - connect \Y $and$libresoc.v:146807$7157_Y + connect \Y $and$libresoc.v:147687$7141_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:146810$7160 + cell $and $and$libresoc.v:147690$7144 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303053,10 +274099,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$17 connect \B \$19 - connect \Y $and$libresoc.v:146810$7160_Y + connect \Y $and$libresoc.v:147690$7144_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:146815$7165 + cell $and $and$libresoc.v:147695$7149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303064,10 +274110,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$29 connect \B \x_valid_i - connect \Y $and$libresoc.v:146815$7165_Y + connect \Y $and$libresoc.v:147695$7149_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:146817$7167 + cell $and $and$libresoc.v:147697$7151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303075,10 +274121,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$31 connect \B \$33 - connect \Y $and$libresoc.v:146817$7167_Y + connect \Y $and$libresoc.v:147697$7151_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:146819$7169 + cell $and $and$libresoc.v:147699$7153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303086,10 +274132,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$1 connect \B \x_valid_i - connect \Y $and$libresoc.v:146819$7169_Y + connect \Y $and$libresoc.v:147699$7153_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:146823$7173 + cell $and $and$libresoc.v:147703$7157 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303097,10 +274143,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$43 connect \B \x_valid_i - connect \Y $and$libresoc.v:146823$7173_Y + connect \Y $and$libresoc.v:147703$7157_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:146825$7175 + cell $and $and$libresoc.v:147705$7159 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303108,10 +274154,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$45 connect \B \$47 - connect \Y $and$libresoc.v:146825$7175_Y + connect \Y $and$libresoc.v:147705$7159_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:146831$7181 + cell $and $and$libresoc.v:147711$7165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303119,10 +274165,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$57 connect \B \x_valid_i - connect \Y $and$libresoc.v:146831$7181_Y + connect \Y $and$libresoc.v:147711$7165_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:146833$7183 + cell $and $and$libresoc.v:147713$7167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303130,10 +274176,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$59 connect \B \$61 - connect \Y $and$libresoc.v:146833$7183_Y + connect \Y $and$libresoc.v:147713$7167_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:146835$7185 + cell $and $and$libresoc.v:147715$7169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303141,10 +274187,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$65 connect \B \x_valid_i - connect \Y $and$libresoc.v:146835$7185_Y + connect \Y $and$libresoc.v:147715$7169_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:146837$7187 + cell $and $and$libresoc.v:147717$7171 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303152,10 +274198,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$67 connect \B \$69 - connect \Y $and$libresoc.v:146837$7187_Y + connect \Y $and$libresoc.v:147717$7171_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:146839$7189 + cell $and $and$libresoc.v:147719$7173 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303163,10 +274209,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$73 connect \B \x_valid_i - connect \Y $and$libresoc.v:146839$7189_Y + connect \Y $and$libresoc.v:147719$7173_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:146841$7191 + cell $and $and$libresoc.v:147721$7175 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303174,10 +274220,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 - connect \Y $and$libresoc.v:146841$7191_Y + connect \Y $and$libresoc.v:147721$7175_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $and $and$libresoc.v:146842$7192 + cell $and $and$libresoc.v:147722$7176 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303185,10 +274231,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$75 connect \B \$77 - connect \Y $and$libresoc.v:146842$7192_Y + connect \Y $and$libresoc.v:147722$7176_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" - cell $and $and$libresoc.v:146843$7193 + cell $and $and$libresoc.v:147723$7177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303196,10 +274242,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__cyc connect \B \dbus__err - connect \Y $and$libresoc.v:146843$7193_Y + connect \Y $and$libresoc.v:147723$7177_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" - cell $and $and$libresoc.v:146846$7196 + cell $and $and$libresoc.v:147726$7180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303207,10 +274253,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__cyc connect \B \dbus__err - connect \Y $and$libresoc.v:146846$7196_Y + connect \Y $and$libresoc.v:147726$7180_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" - cell $and $and$libresoc.v:146848$7198 + cell $and $and$libresoc.v:147728$7182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303218,130 +274264,130 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__cyc connect \B \dbus__err - connect \Y $and$libresoc.v:146848$7198_Y + connect \Y $and$libresoc.v:147728$7182_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $not $not$libresoc.v:146804$7154 + cell $not $not$libresoc.v:147684$7138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_valid_i - connect \Y $not$libresoc.v:146804$7154_Y + connect \Y $not$libresoc.v:147684$7138_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:146809$7159 + cell $not $not$libresoc.v:147689$7143 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:146809$7159_Y + connect \Y $not$libresoc.v:147689$7143_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $not $not$libresoc.v:146812$7162 + cell $not $not$libresoc.v:147692$7146 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_valid_i - connect \Y $not$libresoc.v:146812$7162_Y + connect \Y $not$libresoc.v:147692$7146_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:146816$7166 + cell $not $not$libresoc.v:147696$7150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:146816$7166_Y + connect \Y $not$libresoc.v:147696$7150_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $not $not$libresoc.v:146820$7170 + cell $not $not$libresoc.v:147700$7154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_valid_i - connect \Y $not$libresoc.v:146820$7170_Y + connect \Y $not$libresoc.v:147700$7154_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:146824$7174 + cell $not $not$libresoc.v:147704$7158 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:146824$7174_Y + connect \Y $not$libresoc.v:147704$7158_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $not $not$libresoc.v:146827$7177 + cell $not $not$libresoc.v:147707$7161 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_valid_i - connect \Y $not$libresoc.v:146827$7177_Y + connect \Y $not$libresoc.v:147707$7161_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:146830$7180 + cell $not $not$libresoc.v:147710$7164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:146830$7180_Y + connect \Y $not$libresoc.v:147710$7164_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:146832$7182 + cell $not $not$libresoc.v:147712$7166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:146832$7182_Y + connect \Y $not$libresoc.v:147712$7166_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:146836$7186 + cell $not $not$libresoc.v:147716$7170 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:146836$7186_Y + connect \Y $not$libresoc.v:147716$7170_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $not $not$libresoc.v:146840$7190 + cell $not $not$libresoc.v:147720$7174 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_stall_i - connect \Y $not$libresoc.v:146840$7190_Y + connect \Y $not$libresoc.v:147720$7174_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" - cell $not $not$libresoc.v:146844$7194 + cell $not $not$libresoc.v:147724$7178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_stall_i - connect \Y $not$libresoc.v:146844$7194_Y + connect \Y $not$libresoc.v:147724$7178_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:142" - cell $not $not$libresoc.v:146845$7195 + cell $not $not$libresoc.v:147725$7179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbus__we - connect \Y $not$libresoc.v:146845$7195_Y + connect \Y $not$libresoc.v:147725$7179_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" - cell $not $not$libresoc.v:146847$7197 + cell $not $not$libresoc.v:147727$7181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_stall_i - connect \Y $not$libresoc.v:146847$7197_Y + connect \Y $not$libresoc.v:147727$7181_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:146" - cell $not $not$libresoc.v:146849$7199 + cell $not $not$libresoc.v:147729$7183 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \m_stall_i - connect \Y $not$libresoc.v:146849$7199_Y + connect \Y $not$libresoc.v:147729$7183_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:146803$7153 + cell $or $or$libresoc.v:147683$7137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303349,10 +274395,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__ack connect \B \dbus__err - connect \Y $or$libresoc.v:146803$7153_Y + connect \Y $or$libresoc.v:147683$7137_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:146805$7155 + cell $or $or$libresoc.v:147685$7139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303360,10 +274406,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$9 connect \B \$11 - connect \Y $or$libresoc.v:146805$7155_Y + connect \Y $or$libresoc.v:147685$7139_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:146806$7156 + cell $or $or$libresoc.v:147686$7140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303371,10 +274417,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:146806$7156_Y + connect \Y $or$libresoc.v:147686$7140_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:146808$7158 + cell $or $or$libresoc.v:147688$7142 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303382,10 +274428,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:146808$7158_Y + connect \Y $or$libresoc.v:147688$7142_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:146811$7161 + cell $or $or$libresoc.v:147691$7145 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303393,10 +274439,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__ack connect \B \dbus__err - connect \Y $or$libresoc.v:146811$7161_Y + connect \Y $or$libresoc.v:147691$7145_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:146813$7163 + cell $or $or$libresoc.v:147693$7147 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303404,10 +274450,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$23 connect \B \$25 - connect \Y $or$libresoc.v:146813$7163_Y + connect \Y $or$libresoc.v:147693$7147_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:146814$7164 + cell $or $or$libresoc.v:147694$7148 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303415,10 +274461,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:146814$7164_Y + connect \Y $or$libresoc.v:147694$7148_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:146818$7168 + cell $or $or$libresoc.v:147698$7152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303426,10 +274472,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__ack connect \B \dbus__err - connect \Y $or$libresoc.v:146818$7168_Y + connect \Y $or$libresoc.v:147698$7152_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:146821$7171 + cell $or $or$libresoc.v:147701$7155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303437,10 +274483,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$37 connect \B \$39 - connect \Y $or$libresoc.v:146821$7171_Y + connect \Y $or$libresoc.v:147701$7155_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:146822$7172 + cell $or $or$libresoc.v:147702$7156 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303448,10 +274494,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:146822$7172_Y + connect \Y $or$libresoc.v:147702$7156_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:146826$7176 + cell $or $or$libresoc.v:147706$7160 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303459,10 +274505,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \dbus__ack connect \B \dbus__err - connect \Y $or$libresoc.v:146826$7176_Y + connect \Y $or$libresoc.v:147706$7160_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" - cell $or $or$libresoc.v:146828$7178 + cell $or $or$libresoc.v:147708$7162 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303470,10 +274516,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \$51 connect \B \$53 - connect \Y $or$libresoc.v:146828$7178_Y + connect \Y $or$libresoc.v:147708$7162_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:146829$7179 + cell $or $or$libresoc.v:147709$7163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303481,10 +274527,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:146829$7179_Y + connect \Y $or$libresoc.v:147709$7163_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:146834$7184 + cell $or $or$libresoc.v:147714$7168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303492,10 +274538,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:146834$7184_Y + connect \Y $or$libresoc.v:147714$7168_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - cell $or $or$libresoc.v:146838$7188 + cell $or $or$libresoc.v:147718$7172 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303503,10 +274549,10 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \x_ld_i connect \B \x_st_i - connect \Y $or$libresoc.v:146838$7188_Y + connect \Y $or$libresoc.v:147718$7172_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:154" - cell $or $or$libresoc.v:146850$7200 + cell $or $or$libresoc.v:147730$7184 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -303514,175 +274560,175 @@ module \lsmem parameter \Y_WIDTH 1 connect \A \m_load_err_o connect \B \m_store_err_o - connect \Y $or$libresoc.v:146850$7200_Y + connect \Y $or$libresoc.v:147730$7184_Y end - attribute \src "libresoc.v:146624.7-146624.20" - process $proc$libresoc.v:146624$7267 + attribute \src "libresoc.v:147504.7-147504.20" + process $proc$libresoc.v:147504$7251 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:146729.14-146729.42" - process $proc$libresoc.v:146729$7268 + attribute \src "libresoc.v:147609.14-147609.42" + process $proc$libresoc.v:147609$7252 assign { } { } assign $1\dbus__adr[44:0] 45'000000000000000000000000000000000000000000000 sync always sync init update \dbus__adr $1\dbus__adr[44:0] end - attribute \src "libresoc.v:146734.7-146734.23" - process $proc$libresoc.v:146734$7269 + attribute \src "libresoc.v:147614.7-147614.23" + process $proc$libresoc.v:147614$7253 assign { } { } assign $1\dbus__cyc[0:0] 1'0 sync always sync init update \dbus__cyc $1\dbus__cyc[0:0] end - attribute \src "libresoc.v:146741.14-146741.48" - process $proc$libresoc.v:146741$7270 + attribute \src "libresoc.v:147621.14-147621.48" + process $proc$libresoc.v:147621$7254 assign { } { } assign $1\dbus__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dbus__dat_w $1\dbus__dat_w[63:0] end - attribute \src "libresoc.v:146748.13-146748.30" - process $proc$libresoc.v:146748$7271 + attribute \src "libresoc.v:147628.13-147628.30" + process $proc$libresoc.v:147628$7255 assign { } { } assign $1\dbus__sel[7:0] 8'00000000 sync always sync init update \dbus__sel $1\dbus__sel[7:0] end - attribute \src "libresoc.v:146753.7-146753.23" - process $proc$libresoc.v:146753$7272 + attribute \src "libresoc.v:147633.7-147633.23" + process $proc$libresoc.v:147633$7256 assign { } { } assign $1\dbus__stb[0:0] 1'0 sync always sync init update \dbus__stb $1\dbus__stb[0:0] end - attribute \src "libresoc.v:146758.7-146758.22" - process $proc$libresoc.v:146758$7273 + attribute \src "libresoc.v:147638.7-147638.22" + process $proc$libresoc.v:147638$7257 assign { } { } assign $1\dbus__we[0:0] 1'0 sync always sync init update \dbus__we $1\dbus__we[0:0] end - attribute \src "libresoc.v:146762.14-146762.44" - process $proc$libresoc.v:146762$7274 + attribute \src "libresoc.v:147642.14-147642.44" + process $proc$libresoc.v:147642$7258 assign { } { } assign $1\m_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 sync always sync init update \m_badaddr_o $1\m_badaddr_o[44:0] end - attribute \src "libresoc.v:146769.14-146769.48" - process $proc$libresoc.v:146769$7275 + attribute \src "libresoc.v:147649.14-147649.48" + process $proc$libresoc.v:147649$7259 assign { } { } assign $1\m_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \m_ld_data_o $1\m_ld_data_o[63:0] end - attribute \src "libresoc.v:146773.7-146773.26" - process $proc$libresoc.v:146773$7276 + attribute \src "libresoc.v:147653.7-147653.26" + process $proc$libresoc.v:147653$7260 assign { } { } assign $1\m_load_err_o[0:0] 1'0 sync always sync init update \m_load_err_o $1\m_load_err_o[0:0] end - attribute \src "libresoc.v:146779.7-146779.27" - process $proc$libresoc.v:146779$7277 + attribute \src "libresoc.v:147659.7-147659.27" + process $proc$libresoc.v:147659$7261 assign { } { } assign $1\m_store_err_o[0:0] 1'0 sync always sync init update \m_store_err_o $1\m_store_err_o[0:0] end - attribute \src "libresoc.v:146851.3-146852.39" - process $proc$libresoc.v:146851$7201 + attribute \src "libresoc.v:147731.3-147732.39" + process $proc$libresoc.v:147731$7185 assign { } { } assign $0\m_badaddr_o[44:0] \m_badaddr_o$next sync posedge \coresync_clk update \m_badaddr_o $0\m_badaddr_o[44:0] end - attribute \src "libresoc.v:146853.3-146854.43" - process $proc$libresoc.v:146853$7202 + attribute \src "libresoc.v:147733.3-147734.43" + process $proc$libresoc.v:147733$7186 assign { } { } assign $0\m_store_err_o[0:0] \m_store_err_o$next sync posedge \coresync_clk update \m_store_err_o $0\m_store_err_o[0:0] end - attribute \src "libresoc.v:146855.3-146856.41" - process $proc$libresoc.v:146855$7203 + attribute \src "libresoc.v:147735.3-147736.41" + process $proc$libresoc.v:147735$7187 assign { } { } assign $0\m_load_err_o[0:0] \m_load_err_o$next sync posedge \coresync_clk update \m_load_err_o $0\m_load_err_o[0:0] end - attribute \src "libresoc.v:146857.3-146858.39" - process $proc$libresoc.v:146857$7204 + attribute \src "libresoc.v:147737.3-147738.39" + process $proc$libresoc.v:147737$7188 assign { } { } assign $0\dbus__dat_w[63:0] \dbus__dat_w$next sync posedge \coresync_clk update \dbus__dat_w $0\dbus__dat_w[63:0] end - attribute \src "libresoc.v:146859.3-146860.33" - process $proc$libresoc.v:146859$7205 + attribute \src "libresoc.v:147739.3-147740.33" + process $proc$libresoc.v:147739$7189 assign { } { } assign $0\dbus__we[0:0] \dbus__we$next sync posedge \coresync_clk update \dbus__we $0\dbus__we[0:0] end - attribute \src "libresoc.v:146861.3-146862.35" - process $proc$libresoc.v:146861$7206 + attribute \src "libresoc.v:147741.3-147742.35" + process $proc$libresoc.v:147741$7190 assign { } { } assign $0\dbus__adr[44:0] \dbus__adr$next sync posedge \coresync_clk update \dbus__adr $0\dbus__adr[44:0] end - attribute \src "libresoc.v:146863.3-146864.39" - process $proc$libresoc.v:146863$7207 + attribute \src "libresoc.v:147743.3-147744.39" + process $proc$libresoc.v:147743$7191 assign { } { } assign $0\m_ld_data_o[63:0] \m_ld_data_o$next sync posedge \coresync_clk update \m_ld_data_o $0\m_ld_data_o[63:0] end - attribute \src "libresoc.v:146865.3-146866.35" - process $proc$libresoc.v:146865$7208 + attribute \src "libresoc.v:147745.3-147746.35" + process $proc$libresoc.v:147745$7192 assign { } { } assign $0\dbus__sel[7:0] \dbus__sel$next sync posedge \coresync_clk update \dbus__sel $0\dbus__sel[7:0] end - attribute \src "libresoc.v:146867.3-146868.35" - process $proc$libresoc.v:146867$7209 + attribute \src "libresoc.v:147747.3-147748.35" + process $proc$libresoc.v:147747$7193 assign { } { } assign $0\dbus__stb[0:0] \dbus__stb$next sync posedge \coresync_clk update \dbus__stb $0\dbus__stb[0:0] end - attribute \src "libresoc.v:146869.3-146870.35" - process $proc$libresoc.v:146869$7210 + attribute \src "libresoc.v:147749.3-147750.35" + process $proc$libresoc.v:147749$7194 assign { } { } assign $0\dbus__cyc[0:0] \dbus__cyc$next sync posedge \coresync_clk update \dbus__cyc $0\dbus__cyc[0:0] end - attribute \src "libresoc.v:146871.3-146898.6" - process $proc$libresoc.v:146871$7211 + attribute \src "libresoc.v:147751.3-147778.6" + process $proc$libresoc.v:147751$7195 assign { } { } assign { } { } assign { } { } - assign $0\dbus__cyc$next[0:0]$7212 $4\dbus__cyc$next[0:0]$7216 - attribute \src "libresoc.v:146872.5-146872.29" + assign $0\dbus__cyc$next[0:0]$7196 $4\dbus__cyc$next[0:0]$7200 + attribute \src "libresoc.v:147752.5-147752.29" switch \initial - attribute \src "libresoc.v:146872.9-146872.17" + attribute \src "libresoc.v:147752.9-147752.17" case 1'1 case end @@ -303691,53 +274737,53 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbus__cyc$next[0:0]$7213 $2\dbus__cyc$next[0:0]$7214 + assign $1\dbus__cyc$next[0:0]$7197 $2\dbus__cyc$next[0:0]$7198 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$7 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\dbus__cyc$next[0:0]$7214 $3\dbus__cyc$next[0:0]$7215 + assign $2\dbus__cyc$next[0:0]$7198 $3\dbus__cyc$next[0:0]$7199 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" switch \$13 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dbus__cyc$next[0:0]$7215 1'0 + assign $3\dbus__cyc$next[0:0]$7199 1'0 case - assign $3\dbus__cyc$next[0:0]$7215 \dbus__cyc + assign $3\dbus__cyc$next[0:0]$7199 \dbus__cyc end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\dbus__cyc$next[0:0]$7214 1'1 + assign $2\dbus__cyc$next[0:0]$7198 1'1 case - assign $2\dbus__cyc$next[0:0]$7214 \dbus__cyc + assign $2\dbus__cyc$next[0:0]$7198 \dbus__cyc end case - assign $1\dbus__cyc$next[0:0]$7213 \dbus__cyc + assign $1\dbus__cyc$next[0:0]$7197 \dbus__cyc end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\dbus__cyc$next[0:0]$7216 1'0 + assign $4\dbus__cyc$next[0:0]$7200 1'0 case - assign $4\dbus__cyc$next[0:0]$7216 $1\dbus__cyc$next[0:0]$7213 + assign $4\dbus__cyc$next[0:0]$7200 $1\dbus__cyc$next[0:0]$7197 end sync always - update \dbus__cyc$next $0\dbus__cyc$next[0:0]$7212 + update \dbus__cyc$next $0\dbus__cyc$next[0:0]$7196 end - attribute \src "libresoc.v:146899.3-146926.6" - process $proc$libresoc.v:146899$7217 + attribute \src "libresoc.v:147779.3-147806.6" + process $proc$libresoc.v:147779$7201 assign { } { } assign { } { } assign { } { } - assign $0\dbus__stb$next[0:0]$7218 $4\dbus__stb$next[0:0]$7222 - attribute \src "libresoc.v:146900.5-146900.29" + assign $0\dbus__stb$next[0:0]$7202 $4\dbus__stb$next[0:0]$7206 + attribute \src "libresoc.v:147780.5-147780.29" switch \initial - attribute \src "libresoc.v:146900.9-146900.17" + attribute \src "libresoc.v:147780.9-147780.17" case 1'1 case end @@ -303746,52 +274792,52 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbus__stb$next[0:0]$7219 $2\dbus__stb$next[0:0]$7220 + assign $1\dbus__stb$next[0:0]$7203 $2\dbus__stb$next[0:0]$7204 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$21 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\dbus__stb$next[0:0]$7220 $3\dbus__stb$next[0:0]$7221 + assign $2\dbus__stb$next[0:0]$7204 $3\dbus__stb$next[0:0]$7205 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" switch \$27 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dbus__stb$next[0:0]$7221 1'0 + assign $3\dbus__stb$next[0:0]$7205 1'0 case - assign $3\dbus__stb$next[0:0]$7221 \dbus__stb + assign $3\dbus__stb$next[0:0]$7205 \dbus__stb end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\dbus__stb$next[0:0]$7220 1'1 + assign $2\dbus__stb$next[0:0]$7204 1'1 case - assign $2\dbus__stb$next[0:0]$7220 \dbus__stb + assign $2\dbus__stb$next[0:0]$7204 \dbus__stb end case - assign $1\dbus__stb$next[0:0]$7219 \dbus__stb + assign $1\dbus__stb$next[0:0]$7203 \dbus__stb end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\dbus__stb$next[0:0]$7222 1'0 + assign $4\dbus__stb$next[0:0]$7206 1'0 case - assign $4\dbus__stb$next[0:0]$7222 $1\dbus__stb$next[0:0]$7219 + assign $4\dbus__stb$next[0:0]$7206 $1\dbus__stb$next[0:0]$7203 end sync always - update \dbus__stb$next $0\dbus__stb$next[0:0]$7218 + update \dbus__stb$next $0\dbus__stb$next[0:0]$7202 end - attribute \src "libresoc.v:146927.3-146936.6" - process $proc$libresoc.v:146927$7223 + attribute \src "libresoc.v:147807.3-147816.6" + process $proc$libresoc.v:147807$7207 assign { } { } assign { } { } assign $0\x_busy_o[0:0] $1\x_busy_o[0:0] - attribute \src "libresoc.v:146928.5-146928.29" + attribute \src "libresoc.v:147808.5-147808.29" switch \initial - attribute \src "libresoc.v:146928.9-146928.17" + attribute \src "libresoc.v:147808.9-147808.17" case 1'1 case end @@ -303807,14 +274853,14 @@ module \lsmem sync always update \x_busy_o $0\x_busy_o[0:0] end - attribute \src "libresoc.v:146937.3-146954.6" - process $proc$libresoc.v:146937$7224 + attribute \src "libresoc.v:147817.3-147834.6" + process $proc$libresoc.v:147817$7208 assign { } { } assign { } { } assign $0\m_busy_o[0:0] $1\m_busy_o[0:0] - attribute \src "libresoc.v:146938.5-146938.29" + attribute \src "libresoc.v:147818.5-147818.29" switch \initial - attribute \src "libresoc.v:146938.9-146938.17" + attribute \src "libresoc.v:147818.9-147818.17" case 1'1 case end @@ -303841,15 +274887,15 @@ module \lsmem sync always update \m_busy_o $0\m_busy_o[0:0] end - attribute \src "libresoc.v:146955.3-146985.6" - process $proc$libresoc.v:146955$7225 + attribute \src "libresoc.v:147835.3-147865.6" + process $proc$libresoc.v:147835$7209 assign { } { } assign { } { } assign { } { } - assign $0\dbus__sel$next[7:0]$7226 $4\dbus__sel$next[7:0]$7230 - attribute \src "libresoc.v:146956.5-146956.29" + assign $0\dbus__sel$next[7:0]$7210 $4\dbus__sel$next[7:0]$7214 + attribute \src "libresoc.v:147836.5-147836.29" switch \initial - attribute \src "libresoc.v:146956.9-146956.17" + attribute \src "libresoc.v:147836.9-147836.17" case 1'1 case end @@ -303858,55 +274904,55 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbus__sel$next[7:0]$7227 $2\dbus__sel$next[7:0]$7228 + assign $1\dbus__sel$next[7:0]$7211 $2\dbus__sel$next[7:0]$7212 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$35 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\dbus__sel$next[7:0]$7228 $3\dbus__sel$next[7:0]$7229 + assign $2\dbus__sel$next[7:0]$7212 $3\dbus__sel$next[7:0]$7213 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" switch \$41 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dbus__sel$next[7:0]$7229 8'00000000 + assign $3\dbus__sel$next[7:0]$7213 8'00000000 case - assign $3\dbus__sel$next[7:0]$7229 \dbus__sel + assign $3\dbus__sel$next[7:0]$7213 \dbus__sel end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\dbus__sel$next[7:0]$7228 \x_mask_i + assign $2\dbus__sel$next[7:0]$7212 \x_mask_i attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\dbus__sel$next[7:0]$7228 8'00000000 + assign $2\dbus__sel$next[7:0]$7212 8'00000000 end case - assign $1\dbus__sel$next[7:0]$7227 \dbus__sel + assign $1\dbus__sel$next[7:0]$7211 \dbus__sel end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\dbus__sel$next[7:0]$7230 8'00000000 + assign $4\dbus__sel$next[7:0]$7214 8'00000000 case - assign $4\dbus__sel$next[7:0]$7230 $1\dbus__sel$next[7:0]$7227 + assign $4\dbus__sel$next[7:0]$7214 $1\dbus__sel$next[7:0]$7211 end sync always - update \dbus__sel$next $0\dbus__sel$next[7:0]$7226 + update \dbus__sel$next $0\dbus__sel$next[7:0]$7210 end - attribute \src "libresoc.v:146986.3-147010.6" - process $proc$libresoc.v:146986$7231 + attribute \src "libresoc.v:147866.3-147890.6" + process $proc$libresoc.v:147866$7215 assign { } { } assign { } { } assign { } { } - assign $0\m_ld_data_o$next[63:0]$7232 $4\m_ld_data_o$next[63:0]$7236 - attribute \src "libresoc.v:146987.5-146987.29" + assign $0\m_ld_data_o$next[63:0]$7216 $4\m_ld_data_o$next[63:0]$7220 + attribute \src "libresoc.v:147867.5-147867.29" switch \initial - attribute \src "libresoc.v:146987.9-146987.17" + attribute \src "libresoc.v:147867.9-147867.17" case 1'1 case end @@ -303915,49 +274961,49 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\m_ld_data_o$next[63:0]$7233 $2\m_ld_data_o$next[63:0]$7234 + assign $1\m_ld_data_o$next[63:0]$7217 $2\m_ld_data_o$next[63:0]$7218 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$49 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\m_ld_data_o$next[63:0]$7234 $3\m_ld_data_o$next[63:0]$7235 + assign $2\m_ld_data_o$next[63:0]$7218 $3\m_ld_data_o$next[63:0]$7219 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:114" switch \$55 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\m_ld_data_o$next[63:0]$7235 \dbus__dat_r + assign $3\m_ld_data_o$next[63:0]$7219 \dbus__dat_r case - assign $3\m_ld_data_o$next[63:0]$7235 \m_ld_data_o + assign $3\m_ld_data_o$next[63:0]$7219 \m_ld_data_o end case - assign $2\m_ld_data_o$next[63:0]$7234 \m_ld_data_o + assign $2\m_ld_data_o$next[63:0]$7218 \m_ld_data_o end case - assign $1\m_ld_data_o$next[63:0]$7233 \m_ld_data_o + assign $1\m_ld_data_o$next[63:0]$7217 \m_ld_data_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\m_ld_data_o$next[63:0]$7236 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $4\m_ld_data_o$next[63:0]$7220 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $4\m_ld_data_o$next[63:0]$7236 $1\m_ld_data_o$next[63:0]$7233 + assign $4\m_ld_data_o$next[63:0]$7220 $1\m_ld_data_o$next[63:0]$7217 end sync always - update \m_ld_data_o$next $0\m_ld_data_o$next[63:0]$7232 + update \m_ld_data_o$next $0\m_ld_data_o$next[63:0]$7216 end - attribute \src "libresoc.v:147011.3-147036.6" - process $proc$libresoc.v:147011$7237 + attribute \src "libresoc.v:147891.3-147916.6" + process $proc$libresoc.v:147891$7221 assign { } { } assign { } { } assign { } { } - assign $0\dbus__adr$next[44:0]$7238 $3\dbus__adr$next[44:0]$7241 - attribute \src "libresoc.v:147012.5-147012.29" + assign $0\dbus__adr$next[44:0]$7222 $3\dbus__adr$next[44:0]$7225 + attribute \src "libresoc.v:147892.5-147892.29" switch \initial - attribute \src "libresoc.v:147012.9-147012.17" + attribute \src "libresoc.v:147892.9-147892.17" case 1'1 case end @@ -303966,45 +275012,45 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbus__adr$next[44:0]$7239 $2\dbus__adr$next[44:0]$7240 + assign $1\dbus__adr$next[44:0]$7223 $2\dbus__adr$next[44:0]$7224 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$63 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 - assign $2\dbus__adr$next[44:0]$7240 \dbus__adr + assign $2\dbus__adr$next[44:0]$7224 \dbus__adr attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\dbus__adr$next[44:0]$7240 \x_addr_i [47:3] + assign $2\dbus__adr$next[44:0]$7224 \x_addr_i [47:3] attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\dbus__adr$next[44:0]$7240 45'000000000000000000000000000000000000000000000 + assign $2\dbus__adr$next[44:0]$7224 45'000000000000000000000000000000000000000000000 end case - assign $1\dbus__adr$next[44:0]$7239 \dbus__adr + assign $1\dbus__adr$next[44:0]$7223 \dbus__adr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dbus__adr$next[44:0]$7241 45'000000000000000000000000000000000000000000000 + assign $3\dbus__adr$next[44:0]$7225 45'000000000000000000000000000000000000000000000 case - assign $3\dbus__adr$next[44:0]$7241 $1\dbus__adr$next[44:0]$7239 + assign $3\dbus__adr$next[44:0]$7225 $1\dbus__adr$next[44:0]$7223 end sync always - update \dbus__adr$next $0\dbus__adr$next[44:0]$7238 + update \dbus__adr$next $0\dbus__adr$next[44:0]$7222 end - attribute \src "libresoc.v:147037.3-147062.6" - process $proc$libresoc.v:147037$7242 + attribute \src "libresoc.v:147917.3-147942.6" + process $proc$libresoc.v:147917$7226 assign { } { } assign { } { } assign { } { } - assign $0\dbus__we$next[0:0]$7243 $3\dbus__we$next[0:0]$7246 - attribute \src "libresoc.v:147038.5-147038.29" + assign $0\dbus__we$next[0:0]$7227 $3\dbus__we$next[0:0]$7230 + attribute \src "libresoc.v:147918.5-147918.29" switch \initial - attribute \src "libresoc.v:147038.9-147038.17" + attribute \src "libresoc.v:147918.9-147918.17" case 1'1 case end @@ -304013,45 +275059,45 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbus__we$next[0:0]$7244 $2\dbus__we$next[0:0]$7245 + assign $1\dbus__we$next[0:0]$7228 $2\dbus__we$next[0:0]$7229 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$71 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 - assign $2\dbus__we$next[0:0]$7245 \dbus__we + assign $2\dbus__we$next[0:0]$7229 \dbus__we attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\dbus__we$next[0:0]$7245 \x_st_i + assign $2\dbus__we$next[0:0]$7229 \x_st_i attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\dbus__we$next[0:0]$7245 1'0 + assign $2\dbus__we$next[0:0]$7229 1'0 end case - assign $1\dbus__we$next[0:0]$7244 \dbus__we + assign $1\dbus__we$next[0:0]$7228 \dbus__we end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dbus__we$next[0:0]$7246 1'0 + assign $3\dbus__we$next[0:0]$7230 1'0 case - assign $3\dbus__we$next[0:0]$7246 $1\dbus__we$next[0:0]$7244 + assign $3\dbus__we$next[0:0]$7230 $1\dbus__we$next[0:0]$7228 end sync always - update \dbus__we$next $0\dbus__we$next[0:0]$7243 + update \dbus__we$next $0\dbus__we$next[0:0]$7227 end - attribute \src "libresoc.v:147063.3-147088.6" - process $proc$libresoc.v:147063$7247 + attribute \src "libresoc.v:147943.3-147968.6" + process $proc$libresoc.v:147943$7231 assign { } { } assign { } { } assign { } { } - assign $0\dbus__dat_w$next[63:0]$7248 $3\dbus__dat_w$next[63:0]$7251 - attribute \src "libresoc.v:147064.5-147064.29" + assign $0\dbus__dat_w$next[63:0]$7232 $3\dbus__dat_w$next[63:0]$7235 + attribute \src "libresoc.v:147944.5-147944.29" switch \initial - attribute \src "libresoc.v:147064.9-147064.17" + attribute \src "libresoc.v:147944.9-147944.17" case 1'1 case end @@ -304060,45 +275106,45 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbus__dat_w$next[63:0]$7249 $2\dbus__dat_w$next[63:0]$7250 + assign $1\dbus__dat_w$next[63:0]$7233 $2\dbus__dat_w$next[63:0]$7234 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" switch { \$79 \dbus__cyc } attribute \src "libresoc.v:0.0-0.0" case 2'-1 - assign $2\dbus__dat_w$next[63:0]$7250 \dbus__dat_w + assign $2\dbus__dat_w$next[63:0]$7234 \dbus__dat_w attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\dbus__dat_w$next[63:0]$7250 \x_st_data_i + assign $2\dbus__dat_w$next[63:0]$7234 \x_st_data_i attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\dbus__dat_w$next[63:0]$7250 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\dbus__dat_w$next[63:0]$7234 64'0000000000000000000000000000000000000000000000000000000000000000 end case - assign $1\dbus__dat_w$next[63:0]$7249 \dbus__dat_w + assign $1\dbus__dat_w$next[63:0]$7233 \dbus__dat_w end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dbus__dat_w$next[63:0]$7251 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dbus__dat_w$next[63:0]$7235 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\dbus__dat_w$next[63:0]$7251 $1\dbus__dat_w$next[63:0]$7249 + assign $3\dbus__dat_w$next[63:0]$7235 $1\dbus__dat_w$next[63:0]$7233 end sync always - update \dbus__dat_w$next $0\dbus__dat_w$next[63:0]$7248 + update \dbus__dat_w$next $0\dbus__dat_w$next[63:0]$7232 end - attribute \src "libresoc.v:147089.3-147111.6" - process $proc$libresoc.v:147089$7252 + attribute \src "libresoc.v:147969.3-147991.6" + process $proc$libresoc.v:147969$7236 assign { } { } assign { } { } assign { } { } - assign $0\m_load_err_o$next[0:0]$7253 $3\m_load_err_o$next[0:0]$7256 - attribute \src "libresoc.v:147090.5-147090.29" + assign $0\m_load_err_o$next[0:0]$7237 $3\m_load_err_o$next[0:0]$7240 + attribute \src "libresoc.v:147970.5-147970.29" switch \initial - attribute \src "libresoc.v:147090.9-147090.17" + attribute \src "libresoc.v:147970.9-147970.17" case 1'1 case end @@ -304107,44 +275153,44 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\m_load_err_o$next[0:0]$7254 $2\m_load_err_o$next[0:0]$7255 + assign $1\m_load_err_o$next[0:0]$7238 $2\m_load_err_o$next[0:0]$7239 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" switch { \$83 \$81 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\m_load_err_o$next[0:0]$7255 \$85 + assign $2\m_load_err_o$next[0:0]$7239 \$85 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\m_load_err_o$next[0:0]$7255 1'0 + assign $2\m_load_err_o$next[0:0]$7239 1'0 case - assign $2\m_load_err_o$next[0:0]$7255 \m_load_err_o + assign $2\m_load_err_o$next[0:0]$7239 \m_load_err_o end case - assign $1\m_load_err_o$next[0:0]$7254 \m_load_err_o + assign $1\m_load_err_o$next[0:0]$7238 \m_load_err_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\m_load_err_o$next[0:0]$7256 1'0 + assign $3\m_load_err_o$next[0:0]$7240 1'0 case - assign $3\m_load_err_o$next[0:0]$7256 $1\m_load_err_o$next[0:0]$7254 + assign $3\m_load_err_o$next[0:0]$7240 $1\m_load_err_o$next[0:0]$7238 end sync always - update \m_load_err_o$next $0\m_load_err_o$next[0:0]$7253 + update \m_load_err_o$next $0\m_load_err_o$next[0:0]$7237 end - attribute \src "libresoc.v:147112.3-147134.6" - process $proc$libresoc.v:147112$7257 + attribute \src "libresoc.v:147992.3-148014.6" + process $proc$libresoc.v:147992$7241 assign { } { } assign { } { } assign { } { } - assign $0\m_store_err_o$next[0:0]$7258 $3\m_store_err_o$next[0:0]$7261 - attribute \src "libresoc.v:147113.5-147113.29" + assign $0\m_store_err_o$next[0:0]$7242 $3\m_store_err_o$next[0:0]$7245 + attribute \src "libresoc.v:147993.5-147993.29" switch \initial - attribute \src "libresoc.v:147113.9-147113.17" + attribute \src "libresoc.v:147993.9-147993.17" case 1'1 case end @@ -304153,44 +275199,44 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\m_store_err_o$next[0:0]$7259 $2\m_store_err_o$next[0:0]$7260 + assign $1\m_store_err_o$next[0:0]$7243 $2\m_store_err_o$next[0:0]$7244 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" switch { \$89 \$87 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\m_store_err_o$next[0:0]$7260 \dbus__we + assign $2\m_store_err_o$next[0:0]$7244 \dbus__we attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $2\m_store_err_o$next[0:0]$7260 1'0 + assign $2\m_store_err_o$next[0:0]$7244 1'0 case - assign $2\m_store_err_o$next[0:0]$7260 \m_store_err_o + assign $2\m_store_err_o$next[0:0]$7244 \m_store_err_o end case - assign $1\m_store_err_o$next[0:0]$7259 \m_store_err_o + assign $1\m_store_err_o$next[0:0]$7243 \m_store_err_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\m_store_err_o$next[0:0]$7261 1'0 + assign $3\m_store_err_o$next[0:0]$7245 1'0 case - assign $3\m_store_err_o$next[0:0]$7261 $1\m_store_err_o$next[0:0]$7259 + assign $3\m_store_err_o$next[0:0]$7245 $1\m_store_err_o$next[0:0]$7243 end sync always - update \m_store_err_o$next $0\m_store_err_o$next[0:0]$7258 + update \m_store_err_o$next $0\m_store_err_o$next[0:0]$7242 end - attribute \src "libresoc.v:147135.3-147154.6" - process $proc$libresoc.v:147135$7262 + attribute \src "libresoc.v:148015.3-148034.6" + process $proc$libresoc.v:148015$7246 assign { } { } assign { } { } assign { } { } - assign $0\m_badaddr_o$next[44:0]$7263 $3\m_badaddr_o$next[44:0]$7266 - attribute \src "libresoc.v:147136.5-147136.29" + assign $0\m_badaddr_o$next[44:0]$7247 $3\m_badaddr_o$next[44:0]$7250 + attribute \src "libresoc.v:148016.5-148016.29" switch \initial - attribute \src "libresoc.v:147136.9-147136.17" + attribute \src "libresoc.v:148016.9-148016.17" case 1'1 case end @@ -304199,343 +275245,343 @@ module \lsmem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\m_badaddr_o$next[44:0]$7264 $2\m_badaddr_o$next[44:0]$7265 + assign $1\m_badaddr_o$next[44:0]$7248 $2\m_badaddr_o$next[44:0]$7249 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:140" switch { \$93 \$91 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $2\m_badaddr_o$next[44:0]$7265 \dbus__adr + assign $2\m_badaddr_o$next[44:0]$7249 \dbus__adr case - assign $2\m_badaddr_o$next[44:0]$7265 \m_badaddr_o + assign $2\m_badaddr_o$next[44:0]$7249 \m_badaddr_o end case - assign $1\m_badaddr_o$next[44:0]$7264 \m_badaddr_o + assign $1\m_badaddr_o$next[44:0]$7248 \m_badaddr_o end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\m_badaddr_o$next[44:0]$7266 45'000000000000000000000000000000000000000000000 - case - assign $3\m_badaddr_o$next[44:0]$7266 $1\m_badaddr_o$next[44:0]$7264 - end - sync always - update \m_badaddr_o$next $0\m_badaddr_o$next[44:0]$7263 - end - connect \$9 $or$libresoc.v:146803$7153_Y - connect \$11 $not$libresoc.v:146804$7154_Y - connect \$13 $or$libresoc.v:146805$7155_Y - connect \$15 $or$libresoc.v:146806$7156_Y - connect \$17 $and$libresoc.v:146807$7157_Y - connect \$1 $or$libresoc.v:146808$7158_Y - connect \$19 $not$libresoc.v:146809$7159_Y - connect \$21 $and$libresoc.v:146810$7160_Y - connect \$23 $or$libresoc.v:146811$7161_Y - connect \$25 $not$libresoc.v:146812$7162_Y - connect \$27 $or$libresoc.v:146813$7163_Y - connect \$29 $or$libresoc.v:146814$7164_Y - connect \$31 $and$libresoc.v:146815$7165_Y - connect \$33 $not$libresoc.v:146816$7166_Y - connect \$35 $and$libresoc.v:146817$7167_Y - connect \$37 $or$libresoc.v:146818$7168_Y - connect \$3 $and$libresoc.v:146819$7169_Y - connect \$39 $not$libresoc.v:146820$7170_Y - connect \$41 $or$libresoc.v:146821$7171_Y - connect \$43 $or$libresoc.v:146822$7172_Y - connect \$45 $and$libresoc.v:146823$7173_Y - connect \$47 $not$libresoc.v:146824$7174_Y - connect \$49 $and$libresoc.v:146825$7175_Y - connect \$51 $or$libresoc.v:146826$7176_Y - connect \$53 $not$libresoc.v:146827$7177_Y - connect \$55 $or$libresoc.v:146828$7178_Y - connect \$57 $or$libresoc.v:146829$7179_Y - connect \$5 $not$libresoc.v:146830$7180_Y - connect \$59 $and$libresoc.v:146831$7181_Y - connect \$61 $not$libresoc.v:146832$7182_Y - connect \$63 $and$libresoc.v:146833$7183_Y - connect \$65 $or$libresoc.v:146834$7184_Y - connect \$67 $and$libresoc.v:146835$7185_Y - connect \$69 $not$libresoc.v:146836$7186_Y - connect \$71 $and$libresoc.v:146837$7187_Y - connect \$73 $or$libresoc.v:146838$7188_Y - connect \$75 $and$libresoc.v:146839$7189_Y - connect \$77 $not$libresoc.v:146840$7190_Y - connect \$7 $and$libresoc.v:146841$7191_Y - connect \$79 $and$libresoc.v:146842$7192_Y - connect \$81 $and$libresoc.v:146843$7193_Y - connect \$83 $not$libresoc.v:146844$7194_Y - connect \$85 $not$libresoc.v:146845$7195_Y - connect \$87 $and$libresoc.v:146846$7196_Y - connect \$89 $not$libresoc.v:146847$7197_Y - connect \$91 $and$libresoc.v:146848$7198_Y - connect \$93 $not$libresoc.v:146849$7199_Y - connect \$95 $or$libresoc.v:146850$7200_Y + assign $3\m_badaddr_o$next[44:0]$7250 45'000000000000000000000000000000000000000000000 + case + assign $3\m_badaddr_o$next[44:0]$7250 $1\m_badaddr_o$next[44:0]$7248 + end + sync always + update \m_badaddr_o$next $0\m_badaddr_o$next[44:0]$7247 + end + connect \$9 $or$libresoc.v:147683$7137_Y + connect \$11 $not$libresoc.v:147684$7138_Y + connect \$13 $or$libresoc.v:147685$7139_Y + connect \$15 $or$libresoc.v:147686$7140_Y + connect \$17 $and$libresoc.v:147687$7141_Y + connect \$1 $or$libresoc.v:147688$7142_Y + connect \$19 $not$libresoc.v:147689$7143_Y + connect \$21 $and$libresoc.v:147690$7144_Y + connect \$23 $or$libresoc.v:147691$7145_Y + connect \$25 $not$libresoc.v:147692$7146_Y + connect \$27 $or$libresoc.v:147693$7147_Y + connect \$29 $or$libresoc.v:147694$7148_Y + connect \$31 $and$libresoc.v:147695$7149_Y + connect \$33 $not$libresoc.v:147696$7150_Y + connect \$35 $and$libresoc.v:147697$7151_Y + connect \$37 $or$libresoc.v:147698$7152_Y + connect \$3 $and$libresoc.v:147699$7153_Y + connect \$39 $not$libresoc.v:147700$7154_Y + connect \$41 $or$libresoc.v:147701$7155_Y + connect \$43 $or$libresoc.v:147702$7156_Y + connect \$45 $and$libresoc.v:147703$7157_Y + connect \$47 $not$libresoc.v:147704$7158_Y + connect \$49 $and$libresoc.v:147705$7159_Y + connect \$51 $or$libresoc.v:147706$7160_Y + connect \$53 $not$libresoc.v:147707$7161_Y + connect \$55 $or$libresoc.v:147708$7162_Y + connect \$57 $or$libresoc.v:147709$7163_Y + connect \$5 $not$libresoc.v:147710$7164_Y + connect \$59 $and$libresoc.v:147711$7165_Y + connect \$61 $not$libresoc.v:147712$7166_Y + connect \$63 $and$libresoc.v:147713$7167_Y + connect \$65 $or$libresoc.v:147714$7168_Y + connect \$67 $and$libresoc.v:147715$7169_Y + connect \$69 $not$libresoc.v:147716$7170_Y + connect \$71 $and$libresoc.v:147717$7171_Y + connect \$73 $or$libresoc.v:147718$7172_Y + connect \$75 $and$libresoc.v:147719$7173_Y + connect \$77 $not$libresoc.v:147720$7174_Y + connect \$7 $and$libresoc.v:147721$7175_Y + connect \$79 $and$libresoc.v:147722$7176_Y + connect \$81 $and$libresoc.v:147723$7177_Y + connect \$83 $not$libresoc.v:147724$7178_Y + connect \$85 $not$libresoc.v:147725$7179_Y + connect \$87 $and$libresoc.v:147726$7180_Y + connect \$89 $not$libresoc.v:147727$7181_Y + connect \$91 $and$libresoc.v:147728$7182_Y + connect \$93 $not$libresoc.v:147729$7183_Y + connect \$95 $or$libresoc.v:147730$7184_Y connect \x_stall_i 1'0 connect \m_stall_i 1'0 end -attribute \src "libresoc.v:147161.1-148122.10" +attribute \src "libresoc.v:148041.1-149074.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.main" attribute \generator "nMigen" module \main - attribute \src "libresoc.v:147694.3-147716.6" + attribute \src "libresoc.v:148574.3-148596.6" wire width 64 $0\a_i[63:0] - attribute \src "libresoc.v:147793.3-147819.6" + attribute \src "libresoc.v:148673.3-148699.6" wire $0\a_lt[0:0] - attribute \src "libresoc.v:148074.3-148084.6" + attribute \src "libresoc.v:149026.3-149036.6" wire width 64 $0\a_n[63:0] - attribute \src "libresoc.v:148044.3-148053.6" + attribute \src "libresoc.v:148996.3-149005.6" wire width 66 $0\add_a[65:0] - attribute \src "libresoc.v:148054.3-148063.6" + attribute \src "libresoc.v:149006.3-149015.6" wire width 66 $0\add_b[65:0] - attribute \src "libresoc.v:148064.3-148073.6" + attribute \src "libresoc.v:149016.3-149025.6" wire width 66 $0\add_o[65:0] - attribute \src "libresoc.v:147932.3-147954.6" + attribute \src "libresoc.v:148840.3-148862.6" wire width 64 $0\b_i[63:0] - attribute \src "libresoc.v:147918.3-147931.6" + attribute \src "libresoc.v:148822.3-148839.6" wire width 2 $0\ca[1:0] - attribute \src "libresoc.v:148085.3-148095.6" + attribute \src "libresoc.v:149037.3-149047.6" wire $0\carry_32[0:0] - attribute \src "libresoc.v:148096.3-148106.6" + attribute \src "libresoc.v:149048.3-149058.6" wire $0\carry_64[0:0] - attribute \src "libresoc.v:147820.3-147845.6" + attribute \src "libresoc.v:148700.3-148733.6" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:147846.3-147860.6" + attribute \src "libresoc.v:148734.3-148756.6" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:148024.3-148043.6" + attribute \src "libresoc.v:148964.3-148995.6" wire width 8 $0\eqs[7:0] - attribute \src "libresoc.v:147162.7-147162.20" + attribute \src "libresoc.v:148042.7-148042.20" wire $0\initial[0:0] - attribute \src "libresoc.v:147684.3-147693.6" + attribute \src "libresoc.v:148564.3-148573.6" wire $0\is_32bit[0:0] - attribute \src "libresoc.v:147755.3-147773.6" + attribute \src "libresoc.v:148635.3-148653.6" wire $0\msb_a[0:0] - attribute \src "libresoc.v:147774.3-147792.6" + attribute \src "libresoc.v:148654.3-148672.6" wire $0\msb_b[0:0] - attribute \src "libresoc.v:147861.3-147898.6" + attribute \src "libresoc.v:148757.3-148798.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:147899.3-147917.6" + attribute \src "libresoc.v:148799.3-148821.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:147977.3-147990.6" + attribute \src "libresoc.v:148893.3-148910.6" wire width 2 $0\ov[1:0] - attribute \src "libresoc.v:148013.3-148023.6" + attribute \src "libresoc.v:148941.3-148963.6" wire width 8 $0\src1[7:0] - attribute \src "libresoc.v:147728.3-147754.6" + attribute \src "libresoc.v:148608.3-148634.6" wire width 5 $0\tval[4:0] - attribute \src "libresoc.v:147955.3-147965.6" - wire width 2 $0\xer_ca$20[1:0]$7353 - attribute \src "libresoc.v:147966.3-147976.6" + attribute \src "libresoc.v:148863.3-148877.6" + wire width 2 $0\xer_ca$20[1:0]$7337 + attribute \src "libresoc.v:148878.3-148892.6" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:147991.3-148001.6" + attribute \src "libresoc.v:148911.3-148925.6" wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:148002.3-148012.6" + attribute \src "libresoc.v:148926.3-148940.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:147717.3-147727.6" + attribute \src "libresoc.v:148597.3-148607.6" wire $0\zerohi[0:0] - attribute \src "libresoc.v:148107.3-148117.6" + attribute \src "libresoc.v:149059.3-149069.6" wire $0\zerolo[0:0] - attribute \src "libresoc.v:147694.3-147716.6" + attribute \src "libresoc.v:148574.3-148596.6" wire width 64 $1\a_i[63:0] - attribute \src "libresoc.v:147793.3-147819.6" + attribute \src "libresoc.v:148673.3-148699.6" wire $1\a_lt[0:0] - attribute \src "libresoc.v:148074.3-148084.6" + attribute \src "libresoc.v:149026.3-149036.6" wire width 64 $1\a_n[63:0] - attribute \src "libresoc.v:148044.3-148053.6" + attribute \src "libresoc.v:148996.3-149005.6" wire width 66 $1\add_a[65:0] - attribute \src "libresoc.v:148054.3-148063.6" + attribute \src "libresoc.v:149006.3-149015.6" wire width 66 $1\add_b[65:0] - attribute \src "libresoc.v:148064.3-148073.6" + attribute \src "libresoc.v:149016.3-149025.6" wire width 66 $1\add_o[65:0] - attribute \src "libresoc.v:147932.3-147954.6" + attribute \src "libresoc.v:148840.3-148862.6" wire width 64 $1\b_i[63:0] - attribute \src "libresoc.v:147918.3-147931.6" + attribute \src "libresoc.v:148822.3-148839.6" wire width 2 $1\ca[1:0] - attribute \src "libresoc.v:148085.3-148095.6" + attribute \src "libresoc.v:149037.3-149047.6" wire $1\carry_32[0:0] - attribute \src "libresoc.v:148096.3-148106.6" + attribute \src "libresoc.v:149048.3-149058.6" wire $1\carry_64[0:0] - attribute \src "libresoc.v:147820.3-147845.6" + attribute \src "libresoc.v:148700.3-148733.6" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:147846.3-147860.6" + attribute \src "libresoc.v:148734.3-148756.6" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:148024.3-148043.6" + attribute \src "libresoc.v:148964.3-148995.6" wire width 8 $1\eqs[7:0] - attribute \src "libresoc.v:147684.3-147693.6" + attribute \src "libresoc.v:148564.3-148573.6" wire $1\is_32bit[0:0] - attribute \src "libresoc.v:147755.3-147773.6" + attribute \src "libresoc.v:148635.3-148653.6" wire $1\msb_a[0:0] - attribute \src "libresoc.v:147774.3-147792.6" + attribute \src "libresoc.v:148654.3-148672.6" wire $1\msb_b[0:0] - attribute \src "libresoc.v:147861.3-147898.6" + attribute \src "libresoc.v:148757.3-148798.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:147899.3-147917.6" + attribute \src "libresoc.v:148799.3-148821.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:147977.3-147990.6" + attribute \src "libresoc.v:148893.3-148910.6" wire width 2 $1\ov[1:0] - attribute \src "libresoc.v:148013.3-148023.6" + attribute \src "libresoc.v:148941.3-148963.6" wire width 8 $1\src1[7:0] - attribute \src "libresoc.v:147728.3-147754.6" + attribute \src "libresoc.v:148608.3-148634.6" wire width 5 $1\tval[4:0] - attribute \src "libresoc.v:147955.3-147965.6" - wire width 2 $1\xer_ca$20[1:0]$7354 - attribute \src "libresoc.v:147966.3-147976.6" + attribute \src "libresoc.v:148863.3-148877.6" + wire width 2 $1\xer_ca$20[1:0]$7338 + attribute \src "libresoc.v:148878.3-148892.6" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:147991.3-148001.6" + attribute \src "libresoc.v:148911.3-148925.6" wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:148002.3-148012.6" + attribute \src "libresoc.v:148926.3-148940.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:147717.3-147727.6" + attribute \src "libresoc.v:148597.3-148607.6" wire $1\zerohi[0:0] - attribute \src "libresoc.v:148107.3-148117.6" + attribute \src "libresoc.v:149059.3-149069.6" wire $1\zerolo[0:0] - attribute \src "libresoc.v:147694.3-147716.6" + attribute \src "libresoc.v:148574.3-148596.6" wire width 64 $2\a_i[63:0] - attribute \src "libresoc.v:147793.3-147819.6" + attribute \src "libresoc.v:148673.3-148699.6" wire $2\a_lt[0:0] - attribute \src "libresoc.v:147932.3-147954.6" + attribute \src "libresoc.v:148840.3-148862.6" wire width 64 $2\b_i[63:0] - attribute \src "libresoc.v:147820.3-147845.6" + attribute \src "libresoc.v:148700.3-148733.6" wire width 2 $2\cr_a[3:2] - attribute \src "libresoc.v:147755.3-147773.6" + attribute \src "libresoc.v:148635.3-148653.6" wire $2\msb_a[0:0] - attribute \src "libresoc.v:147774.3-147792.6" + attribute \src "libresoc.v:148654.3-148672.6" wire $2\msb_b[0:0] - attribute \src "libresoc.v:147861.3-147898.6" + attribute \src "libresoc.v:148757.3-148798.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:147728.3-147754.6" + attribute \src "libresoc.v:148608.3-148634.6" wire width 5 $2\tval[4:0] - attribute \src "libresoc.v:147793.3-147819.6" + attribute \src "libresoc.v:148673.3-148699.6" wire $3\a_lt[0:0] - attribute \src "libresoc.v:147861.3-147898.6" + attribute \src "libresoc.v:148757.3-148798.6" wire width 64 $3\o[63:0] - attribute \src "libresoc.v:147728.3-147754.6" + attribute \src "libresoc.v:148608.3-148634.6" wire width 5 $3\tval[4:0] - attribute \src "libresoc.v:147861.3-147898.6" + attribute \src "libresoc.v:148757.3-148798.6" wire width 64 $4\o[63:0] - attribute \src "libresoc.v:147659.18-147659.105" - wire width 67 $add$libresoc.v:147659$7314_Y - attribute \src "libresoc.v:147633.19-147633.107" - wire $and$libresoc.v:147633$7288_Y - attribute \src "libresoc.v:147637.19-147637.107" - wire $and$libresoc.v:147637$7292_Y - attribute \src "libresoc.v:147670.18-147670.106" - wire $and$libresoc.v:147670$7325_Y - attribute \src "libresoc.v:147675.18-147675.106" - wire $and$libresoc.v:147675$7330_Y - attribute \src "libresoc.v:147678.18-147678.106" - wire $and$libresoc.v:147678$7333_Y - attribute \src "libresoc.v:147681.18-147681.106" - wire $and$libresoc.v:147681$7336_Y - attribute \src "libresoc.v:147624.19-147624.118" - wire $eq$libresoc.v:147624$7279_Y - attribute \src "libresoc.v:147625.19-147625.118" - wire $eq$libresoc.v:147625$7280_Y - attribute \src "libresoc.v:147626.19-147626.118" - wire $eq$libresoc.v:147626$7281_Y - attribute \src "libresoc.v:147638.19-147638.109" - wire $eq$libresoc.v:147638$7293_Y - attribute \src "libresoc.v:147639.19-147639.110" - wire $eq$libresoc.v:147639$7294_Y - attribute \src "libresoc.v:147640.19-147640.111" - wire $eq$libresoc.v:147640$7295_Y - attribute \src "libresoc.v:147641.19-147641.111" - wire $eq$libresoc.v:147641$7296_Y - attribute \src "libresoc.v:147642.19-147642.111" - wire $eq$libresoc.v:147642$7297_Y - attribute \src "libresoc.v:147643.19-147643.111" - wire $eq$libresoc.v:147643$7298_Y - attribute \src "libresoc.v:147644.19-147644.111" - wire $eq$libresoc.v:147644$7299_Y - attribute \src "libresoc.v:147645.19-147645.111" - wire $eq$libresoc.v:147645$7300_Y - attribute \src "libresoc.v:147646.18-147646.118" - wire $eq$libresoc.v:147646$7301_Y - attribute \src "libresoc.v:147648.18-147648.118" - wire $eq$libresoc.v:147648$7303_Y - attribute \src "libresoc.v:147649.18-147649.118" - wire $eq$libresoc.v:147649$7304_Y - attribute \src "libresoc.v:147650.18-147650.118" - wire $eq$libresoc.v:147650$7305_Y - attribute \src "libresoc.v:147651.18-147651.118" - wire $eq$libresoc.v:147651$7306_Y - attribute \src "libresoc.v:147653.18-147653.118" - wire $eq$libresoc.v:147653$7308_Y - attribute \src "libresoc.v:147654.18-147654.118" - wire $eq$libresoc.v:147654$7309_Y - attribute \src "libresoc.v:147656.18-147656.118" - wire $eq$libresoc.v:147656$7311_Y - attribute \src "libresoc.v:147657.18-147657.118" - wire $eq$libresoc.v:147657$7312_Y - attribute \src "libresoc.v:147671.18-147671.107" - wire $ne$libresoc.v:147671$7326_Y - attribute \src "libresoc.v:147682.18-147682.107" - wire $ne$libresoc.v:147682$7337_Y - attribute \src "libresoc.v:147632.19-147632.100" - wire $not$libresoc.v:147632$7287_Y - attribute \src "libresoc.v:147636.19-147636.100" - wire $not$libresoc.v:147636$7291_Y - attribute \src "libresoc.v:147647.18-147647.110" - wire $not$libresoc.v:147647$7302_Y - attribute \src "libresoc.v:147660.18-147660.97" - wire width 64 $not$libresoc.v:147660$7315_Y - attribute \src "libresoc.v:147665.18-147665.99" - wire $not$libresoc.v:147665$7320_Y - attribute \src "libresoc.v:147668.18-147668.99" - wire $not$libresoc.v:147668$7323_Y - attribute \src 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"libresoc.v:147661.18-147661.111" - wire $xor$libresoc.v:147661$7316_Y - attribute \src "libresoc.v:147662.18-147662.107" - wire $xor$libresoc.v:147662$7317_Y - attribute \src "libresoc.v:147663.18-147663.113" - wire width 32 $xor$libresoc.v:147663$7318_Y - attribute \src "libresoc.v:147666.18-147666.115" - wire width 32 $xor$libresoc.v:147666$7321_Y + attribute \src "libresoc.v:148539.18-148539.105" + wire width 67 $add$libresoc.v:148539$7298_Y + attribute \src "libresoc.v:148513.19-148513.107" + wire $and$libresoc.v:148513$7272_Y + attribute \src "libresoc.v:148517.19-148517.107" + wire $and$libresoc.v:148517$7276_Y + attribute \src "libresoc.v:148550.18-148550.106" + wire $and$libresoc.v:148550$7309_Y + attribute \src "libresoc.v:148555.18-148555.106" + wire $and$libresoc.v:148555$7314_Y + attribute \src "libresoc.v:148558.18-148558.106" + wire $and$libresoc.v:148558$7317_Y + attribute \src "libresoc.v:148561.18-148561.106" + wire $and$libresoc.v:148561$7320_Y + attribute \src "libresoc.v:148504.19-148504.118" + wire $eq$libresoc.v:148504$7263_Y + attribute \src "libresoc.v:148505.19-148505.118" + wire $eq$libresoc.v:148505$7264_Y + attribute \src "libresoc.v:148506.19-148506.118" + wire $eq$libresoc.v:148506$7265_Y + attribute \src "libresoc.v:148518.19-148518.109" + wire $eq$libresoc.v:148518$7277_Y + attribute \src "libresoc.v:148519.19-148519.110" + wire $eq$libresoc.v:148519$7278_Y + attribute \src "libresoc.v:148520.19-148520.111" + wire $eq$libresoc.v:148520$7279_Y + attribute \src "libresoc.v:148521.19-148521.111" + wire $eq$libresoc.v:148521$7280_Y + attribute \src "libresoc.v:148522.19-148522.111" + wire $eq$libresoc.v:148522$7281_Y + attribute \src "libresoc.v:148523.19-148523.111" + wire $eq$libresoc.v:148523$7282_Y + attribute \src "libresoc.v:148524.19-148524.111" + wire $eq$libresoc.v:148524$7283_Y + attribute \src "libresoc.v:148525.19-148525.111" + wire $eq$libresoc.v:148525$7284_Y + attribute \src "libresoc.v:148526.18-148526.118" + wire $eq$libresoc.v:148526$7285_Y + attribute \src "libresoc.v:148528.18-148528.118" + wire $eq$libresoc.v:148528$7287_Y + attribute \src "libresoc.v:148529.18-148529.118" + wire $eq$libresoc.v:148529$7288_Y + attribute \src "libresoc.v:148530.18-148530.118" + wire $eq$libresoc.v:148530$7289_Y + attribute \src "libresoc.v:148531.18-148531.118" + wire $eq$libresoc.v:148531$7290_Y + attribute \src "libresoc.v:148533.18-148533.118" + wire $eq$libresoc.v:148533$7292_Y + attribute \src "libresoc.v:148534.18-148534.118" + wire $eq$libresoc.v:148534$7293_Y + attribute \src "libresoc.v:148536.18-148536.118" + wire $eq$libresoc.v:148536$7295_Y + attribute \src "libresoc.v:148537.18-148537.118" + wire $eq$libresoc.v:148537$7296_Y + attribute \src "libresoc.v:148551.18-148551.107" + wire $ne$libresoc.v:148551$7310_Y + attribute \src "libresoc.v:148562.18-148562.107" + wire $ne$libresoc.v:148562$7321_Y + attribute \src "libresoc.v:148512.19-148512.100" + wire $not$libresoc.v:148512$7271_Y + attribute \src "libresoc.v:148516.19-148516.100" + wire $not$libresoc.v:148516$7275_Y + attribute \src "libresoc.v:148527.18-148527.110" + wire $not$libresoc.v:148527$7286_Y + attribute \src "libresoc.v:148540.18-148540.97" + wire width 64 $not$libresoc.v:148540$7299_Y + attribute \src "libresoc.v:148545.18-148545.99" + wire $not$libresoc.v:148545$7304_Y + attribute \src "libresoc.v:148548.18-148548.99" + wire $not$libresoc.v:148548$7307_Y + attribute \src "libresoc.v:148552.18-148552.99" + wire $not$libresoc.v:148552$7311_Y + attribute \src "libresoc.v:148553.18-148553.99" + wire $not$libresoc.v:148553$7312_Y + attribute \src "libresoc.v:148532.18-148532.104" + wire $or$libresoc.v:148532$7291_Y + attribute \src "libresoc.v:148535.18-148535.104" + wire $or$libresoc.v:148535$7294_Y + attribute \src "libresoc.v:148538.18-148538.104" + wire $or$libresoc.v:148538$7297_Y + attribute \src "libresoc.v:148549.18-148549.110" + wire $or$libresoc.v:148549$7308_Y + attribute \src "libresoc.v:148554.18-148554.110" + wire $or$libresoc.v:148554$7313_Y + attribute \src "libresoc.v:148557.18-148557.110" + wire $or$libresoc.v:148557$7316_Y + attribute \src "libresoc.v:148560.18-148560.110" + wire $or$libresoc.v:148560$7319_Y + attribute \src "libresoc.v:148503.18-148503.98" + wire $reduce_or$libresoc.v:148503$7262_Y + attribute \src "libresoc.v:148507.19-148507.99" + wire $reduce_or$libresoc.v:148507$7266_Y + attribute \src "libresoc.v:148544.18-148544.99" + wire $reduce_or$libresoc.v:148544$7303_Y + attribute \src "libresoc.v:148547.18-148547.99" + wire $reduce_or$libresoc.v:148547$7306_Y + attribute \src "libresoc.v:148556.18-148556.121" + wire $ternary$libresoc.v:148556$7315_Y + attribute \src "libresoc.v:148559.18-148559.119" + wire $ternary$libresoc.v:148559$7318_Y + attribute \src "libresoc.v:148563.18-148563.123" + wire $ternary$libresoc.v:148563$7322_Y + attribute \src "libresoc.v:148508.19-148508.111" + wire $xor$libresoc.v:148508$7267_Y + attribute \src "libresoc.v:148509.19-148509.111" + wire $xor$libresoc.v:148509$7268_Y + attribute \src "libresoc.v:148510.19-148510.110" + wire $xor$libresoc.v:148510$7269_Y + attribute \src "libresoc.v:148511.19-148511.110" + wire $xor$libresoc.v:148511$7270_Y + attribute \src "libresoc.v:148514.19-148514.110" + wire $xor$libresoc.v:148514$7273_Y + attribute \src "libresoc.v:148515.19-148515.110" + wire $xor$libresoc.v:148515$7274_Y + attribute \src "libresoc.v:148541.18-148541.111" + wire $xor$libresoc.v:148541$7300_Y + attribute \src "libresoc.v:148542.18-148542.107" + wire $xor$libresoc.v:148542$7301_Y + attribute \src "libresoc.v:148543.18-148543.113" + wire width 32 $xor$libresoc.v:148543$7302_Y + attribute \src "libresoc.v:148546.18-148546.115" + wire width 32 $xor$libresoc.v:148546$7305_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" @@ -304946,7 +275992,7 @@ module \main wire output 45 \cr_a_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" wire width 8 \eqs - attribute \src "libresoc.v:147162.7-147162.15" + attribute \src "libresoc.v:148042.7-148042.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:54" wire \is_32bit @@ -304991,7 +276037,7 @@ module \main attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:102" wire \zerolo attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:86" - cell $add $add$libresoc.v:147659$7314 + cell $add $add$libresoc.v:148539$7298 parameter \A_SIGNED 0 parameter \A_WIDTH 66 parameter \B_SIGNED 0 @@ -304999,10 +276045,10 @@ module \main parameter \Y_WIDTH 67 connect \A \add_a connect \B \add_b - connect \Y $add$libresoc.v:147659$7314_Y + connect \Y $add$libresoc.v:148539$7298_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $and $and$libresoc.v:147633$7288 + cell $and $and$libresoc.v:148513$7272 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305010,10 +276056,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$113 connect \B \$115 - connect \Y $and$libresoc.v:147633$7288_Y + connect \Y $and$libresoc.v:148513$7272_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $and $and$libresoc.v:147637$7292 + cell $and $and$libresoc.v:148517$7276 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305021,10 +276067,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$121 connect \B \$123 - connect \Y $and$libresoc.v:147637$7292_Y + connect \Y $and$libresoc.v:148517$7276_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $and $and$libresoc.v:147670$7325 + cell $and $and$libresoc.v:148550$7309 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305032,10 +276078,10 @@ module \main parameter \Y_WIDTH 1 connect \A \zerolo connect \B \$69 - connect \Y $and$libresoc.v:147670$7325_Y + connect \Y $and$libresoc.v:148550$7309_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $and $and$libresoc.v:147675$7330 + cell $and $and$libresoc.v:148555$7314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305043,10 +276089,10 @@ module \main parameter \Y_WIDTH 1 connect \A \zerolo connect \B \$79 - connect \Y $and$libresoc.v:147675$7330_Y + connect \Y $and$libresoc.v:148555$7314_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $and $and$libresoc.v:147678$7333 + cell $and $and$libresoc.v:148558$7317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305054,10 +276100,10 @@ module \main parameter \Y_WIDTH 1 connect \A \zerolo connect \B \$85 - connect \Y $and$libresoc.v:147678$7333_Y + connect \Y $and$libresoc.v:148558$7317_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $and $and$libresoc.v:147681$7336 + cell $and $and$libresoc.v:148561$7320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305065,10 +276111,10 @@ module \main parameter \Y_WIDTH 1 connect \A \zerolo connect \B \$91 - connect \Y $and$libresoc.v:147681$7336_Y + connect \Y $and$libresoc.v:148561$7320_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" - cell $eq $eq$libresoc.v:147624$7279 + cell $eq $eq$libresoc.v:148504$7263 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -305076,10 +276122,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__data_len connect \B 1'1 - connect \Y $eq$libresoc.v:147624$7279_Y + connect \Y $eq$libresoc.v:148504$7263_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:168" - cell $eq $eq$libresoc.v:147625$7280 + cell $eq $eq$libresoc.v:148505$7264 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -305087,10 +276133,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__data_len connect \B 2'10 - connect \Y $eq$libresoc.v:147625$7280_Y + connect \Y $eq$libresoc.v:148505$7264_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:170" - cell $eq $eq$libresoc.v:147626$7281 + cell $eq $eq$libresoc.v:148506$7265 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -305098,10 +276144,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__data_len connect \B 3'100 - connect \Y $eq$libresoc.v:147626$7281_Y + connect \Y $eq$libresoc.v:148506$7265_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:147638$7293 + cell $eq $eq$libresoc.v:148518$7277 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -305109,10 +276155,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [7:0] - connect \Y $eq$libresoc.v:147638$7293_Y + connect \Y $eq$libresoc.v:148518$7277_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:147639$7294 + cell $eq $eq$libresoc.v:148519$7278 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -305120,10 +276166,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [15:8] - connect \Y $eq$libresoc.v:147639$7294_Y + connect \Y $eq$libresoc.v:148519$7278_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:147640$7295 + cell $eq $eq$libresoc.v:148520$7279 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -305131,10 +276177,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [23:16] - connect \Y $eq$libresoc.v:147640$7295_Y + connect \Y $eq$libresoc.v:148520$7279_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:147641$7296 + cell $eq $eq$libresoc.v:148521$7280 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -305142,10 +276188,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [31:24] - connect \Y $eq$libresoc.v:147641$7296_Y + connect \Y $eq$libresoc.v:148521$7280_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:147642$7297 + cell $eq $eq$libresoc.v:148522$7281 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -305153,10 +276199,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [39:32] - connect \Y $eq$libresoc.v:147642$7297_Y + connect \Y $eq$libresoc.v:148522$7281_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:147643$7298 + cell $eq $eq$libresoc.v:148523$7282 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -305164,10 +276210,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [47:40] - connect \Y $eq$libresoc.v:147643$7298_Y + connect \Y $eq$libresoc.v:148523$7282_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:147644$7299 + cell $eq $eq$libresoc.v:148524$7283 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -305175,10 +276221,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [55:48] - connect \Y $eq$libresoc.v:147644$7299_Y + connect \Y $eq$libresoc.v:148524$7283_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:182" - cell $eq $eq$libresoc.v:147645$7300 + cell $eq $eq$libresoc.v:148525$7284 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -305186,10 +276232,10 @@ module \main parameter \Y_WIDTH 1 connect \A \src1 connect \B \rb [63:56] - connect \Y $eq$libresoc.v:147645$7300_Y + connect \Y $eq$libresoc.v:148525$7284_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:56" - cell $eq $eq$libresoc.v:147646$7301 + cell $eq $eq$libresoc.v:148526$7285 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -305197,10 +276243,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:147646$7301_Y + connect \Y $eq$libresoc.v:148526$7285_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" - cell $eq $eq$libresoc.v:147648$7303 + cell $eq $eq$libresoc.v:148528$7287 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -305208,10 +276254,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:147648$7303_Y + connect \Y $eq$libresoc.v:148528$7287_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" - cell $eq $eq$libresoc.v:147649$7304 + cell $eq $eq$libresoc.v:148529$7288 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -305219,10 +276265,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:147649$7304_Y + connect \Y $eq$libresoc.v:148529$7288_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" - cell $eq $eq$libresoc.v:147650$7305 + cell $eq $eq$libresoc.v:148530$7289 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -305230,10 +276276,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0000010 - connect \Y $eq$libresoc.v:147650$7305_Y + connect \Y $eq$libresoc.v:148530$7289_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $eq $eq$libresoc.v:147651$7306 + cell $eq $eq$libresoc.v:148531$7290 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -305241,10 +276287,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:147651$7306_Y + connect \Y $eq$libresoc.v:148531$7290_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" - cell $eq $eq$libresoc.v:147653$7308 + cell $eq $eq$libresoc.v:148533$7292 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -305252,10 +276298,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0000010 - connect \Y $eq$libresoc.v:147653$7308_Y + connect \Y $eq$libresoc.v:148533$7292_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $eq $eq$libresoc.v:147654$7309 + cell $eq $eq$libresoc.v:148534$7293 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -305263,10 +276309,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:147654$7309_Y + connect \Y $eq$libresoc.v:148534$7293_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:81" - cell $eq $eq$libresoc.v:147656$7311 + cell $eq $eq$libresoc.v:148536$7295 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -305274,10 +276320,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0000010 - connect \Y $eq$libresoc.v:147656$7311_Y + connect \Y $eq$libresoc.v:148536$7295_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $eq $eq$libresoc.v:147657$7312 + cell $eq $eq$libresoc.v:148537$7296 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -305285,10 +276331,10 @@ module \main parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:147657$7312_Y + connect \Y $eq$libresoc.v:148537$7296_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" - cell $ne $ne$libresoc.v:147671$7326 + cell $ne $ne$libresoc.v:148551$7310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305296,10 +276342,10 @@ module \main parameter \Y_WIDTH 1 connect \A \msb_a connect \B \msb_b - connect \Y $ne$libresoc.v:147671$7326_Y + connect \Y $ne$libresoc.v:148551$7310_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:123" - cell $ne $ne$libresoc.v:147682$7337 + cell $ne $ne$libresoc.v:148562$7321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305307,74 +276353,74 @@ module \main parameter \Y_WIDTH 1 connect \A \msb_a connect \B \msb_b - connect \Y $ne$libresoc.v:147682$7337_Y + connect \Y $ne$libresoc.v:148562$7321_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $not $not$libresoc.v:147632$7287 + cell $not $not$libresoc.v:148512$7271 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$116 - connect \Y $not$libresoc.v:147632$7287_Y + connect \Y $not$libresoc.v:148512$7271_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $not $not$libresoc.v:147636$7291 + cell $not $not$libresoc.v:148516$7275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$124 - connect \Y $not$libresoc.v:147636$7291_Y + connect \Y $not$libresoc.v:148516$7275_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:57" - cell $not $not$libresoc.v:147647$7302 + cell $not $not$libresoc.v:148527$7286 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_op__insn [21] - connect \Y $not$libresoc.v:147647$7302_Y + connect \Y $not$libresoc.v:148527$7286_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" - cell $not $not$libresoc.v:147660$7315 + cell $not $not$libresoc.v:148540$7299 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ra - connect \Y $not$libresoc.v:147660$7315_Y + connect \Y $not$libresoc.v:148540$7299_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" - cell $not $not$libresoc.v:147665$7320 + cell $not $not$libresoc.v:148545$7304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$58 - connect \Y $not$libresoc.v:147665$7320_Y + connect \Y $not$libresoc.v:148545$7304_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - cell $not $not$libresoc.v:147668$7323 + cell $not $not$libresoc.v:148548$7307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$64 - connect \Y $not$libresoc.v:147668$7323_Y + connect \Y $not$libresoc.v:148548$7307_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" - cell $not $not$libresoc.v:147672$7327 + cell $not $not$libresoc.v:148552$7311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_lt - connect \Y $not$libresoc.v:147672$7327_Y + connect \Y $not$libresoc.v:148552$7311_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" - cell $not $not$libresoc.v:147673$7328 + cell $not $not$libresoc.v:148553$7312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \a_lt - connect \Y $not$libresoc.v:147673$7328_Y + connect \Y $not$libresoc.v:148553$7312_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $or $or$libresoc.v:147652$7307 + cell $or $or$libresoc.v:148532$7291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305382,10 +276428,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$30 connect \B \$32 - connect \Y $or$libresoc.v:147652$7307_Y + connect \Y $or$libresoc.v:148532$7291_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $or $or$libresoc.v:147655$7310 + cell $or $or$libresoc.v:148535$7294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305393,10 +276439,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$36 connect \B \$38 - connect \Y $or$libresoc.v:147655$7310_Y + connect \Y $or$libresoc.v:148535$7294_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $or $or$libresoc.v:147658$7313 + cell $or $or$libresoc.v:148538$7297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305404,10 +276450,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$42 connect \B \$44 - connect \Y $or$libresoc.v:147658$7313_Y + connect \Y $or$libresoc.v:148538$7297_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $or $or$libresoc.v:147669$7324 + cell $or $or$libresoc.v:148549$7308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305415,10 +276461,10 @@ module \main parameter \Y_WIDTH 1 connect \A \is_32bit connect \B \zerohi - connect \Y $or$libresoc.v:147669$7324_Y + connect \Y $or$libresoc.v:148549$7308_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $or $or$libresoc.v:147674$7329 + cell $or $or$libresoc.v:148554$7313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305426,10 +276472,10 @@ module \main parameter \Y_WIDTH 1 connect \A \is_32bit connect \B \zerohi - connect \Y $or$libresoc.v:147674$7329_Y + connect \Y $or$libresoc.v:148554$7313_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $or $or$libresoc.v:147677$7332 + cell $or $or$libresoc.v:148557$7316 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305437,10 +276483,10 @@ module \main parameter \Y_WIDTH 1 connect \A \is_32bit connect \B \zerohi - connect \Y $or$libresoc.v:147677$7332_Y + connect \Y $or$libresoc.v:148557$7316_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $or $or$libresoc.v:147680$7335 + cell $or $or$libresoc.v:148560$7319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305448,66 +276494,66 @@ module \main parameter \Y_WIDTH 1 connect \A \is_32bit connect \B \zerohi - connect \Y $or$libresoc.v:147680$7335_Y + connect \Y $or$libresoc.v:148560$7319_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:185" - cell $reduce_or $reduce_or$libresoc.v:147623$7278 + cell $reduce_or $reduce_or$libresoc.v:148503$7262 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \eqs - connect \Y $reduce_or$libresoc.v:147623$7278_Y + connect \Y $reduce_or$libresoc.v:148503$7262_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:183" - cell $reduce_or $reduce_or$libresoc.v:147627$7282 + cell $reduce_or $reduce_or$libresoc.v:148507$7266 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \eqs - connect \Y $reduce_or$libresoc.v:147627$7282_Y + connect \Y $reduce_or$libresoc.v:148507$7266_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" - cell $reduce_or $reduce_or$libresoc.v:147664$7319 + cell $reduce_or $reduce_or$libresoc.v:148544$7303 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 1 connect \A \$59 - connect \Y $reduce_or$libresoc.v:147664$7319_Y + connect \Y $reduce_or$libresoc.v:148544$7303_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - cell $reduce_or $reduce_or$libresoc.v:147667$7322 + cell $reduce_or $reduce_or$libresoc.v:148547$7306 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 1 connect \A \$65 - connect \Y $reduce_or$libresoc.v:147667$7322_Y + connect \Y $reduce_or$libresoc.v:148547$7306_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:120" - cell $mux $ternary$libresoc.v:147676$7331 + cell $mux $ternary$libresoc.v:148556$7315 parameter \WIDTH 1 connect \A \a_n [63] connect \B \a_n [31] connect \S \is_32bit - connect \Y $ternary$libresoc.v:147676$7331_Y + connect \Y $ternary$libresoc.v:148556$7315_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:121" - cell $mux $ternary$libresoc.v:147679$7334 + cell $mux $ternary$libresoc.v:148559$7318 parameter \WIDTH 1 connect \A \rb [63] connect \B \rb [31] connect \S \is_32bit - connect \Y $ternary$libresoc.v:147679$7334_Y + connect \Y $ternary$libresoc.v:148559$7318_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:131" - cell $mux $ternary$libresoc.v:147683$7338 + cell $mux $ternary$libresoc.v:148563$7322 parameter \WIDTH 1 connect \A \carry_64 connect \B \carry_32 connect \S \is_32bit - connect \Y $ternary$libresoc.v:147683$7338_Y + connect \Y $ternary$libresoc.v:148563$7322_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" - cell $xor $xor$libresoc.v:147628$7283 + cell $xor $xor$libresoc.v:148508$7267 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305515,10 +276561,10 @@ module \main parameter \Y_WIDTH 1 connect \A \a_i [32] connect \B \b_i [32] - connect \Y $xor$libresoc.v:147628$7283_Y + connect \Y $xor$libresoc.v:148508$7267_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" - cell $xor $xor$libresoc.v:147629$7284 + cell $xor $xor$libresoc.v:148509$7268 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305526,10 +276572,10 @@ module \main parameter \Y_WIDTH 1 connect \A \add_o [33] connect \B \$109 - connect \Y $xor$libresoc.v:147629$7284_Y + connect \Y $xor$libresoc.v:148509$7268_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $xor $xor$libresoc.v:147630$7285 + cell $xor $xor$libresoc.v:148510$7269 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305537,10 +276583,10 @@ module \main parameter \Y_WIDTH 1 connect \A \ca [0] connect \B \add_o [64] - connect \Y $xor$libresoc.v:147630$7285_Y + connect \Y $xor$libresoc.v:148510$7269_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $xor $xor$libresoc.v:147631$7286 + cell $xor $xor$libresoc.v:148511$7270 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305548,10 +276594,10 @@ module \main parameter \Y_WIDTH 1 connect \A \a_i [63] connect \B \b_i [63] - connect \Y $xor$libresoc.v:147631$7286_Y + connect \Y $xor$libresoc.v:148511$7270_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $xor $xor$libresoc.v:147634$7289 + cell $xor $xor$libresoc.v:148514$7273 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305559,10 +276605,10 @@ module \main parameter \Y_WIDTH 1 connect \A \ca [1] connect \B \add_o [32] - connect \Y $xor$libresoc.v:147634$7289_Y + connect \Y $xor$libresoc.v:148514$7273_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:25" - cell $xor $xor$libresoc.v:147635$7290 + cell $xor $xor$libresoc.v:148515$7274 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305570,10 +276616,10 @@ module \main parameter \Y_WIDTH 1 connect \A \a_i [31] connect \B \b_i [31] - connect \Y $xor$libresoc.v:147635$7290_Y + connect \Y $xor$libresoc.v:148515$7274_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" - cell $xor $xor$libresoc.v:147661$7316 + cell $xor $xor$libresoc.v:148541$7300 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305581,10 +276627,10 @@ module \main parameter \Y_WIDTH 1 connect \A \add_o [33] connect \B \ra [32] - connect \Y $xor$libresoc.v:147661$7316_Y + connect \Y $xor$libresoc.v:148541$7300_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" - cell $xor $xor$libresoc.v:147662$7317 + cell $xor $xor$libresoc.v:148542$7301 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -305592,10 +276638,10 @@ module \main parameter \Y_WIDTH 1 connect \A \$53 connect \B \rb [32] - connect \Y $xor$libresoc.v:147662$7317_Y + connect \Y $xor$libresoc.v:148542$7301_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:113" - cell $xor $xor$libresoc.v:147663$7318 + cell $xor $xor$libresoc.v:148543$7302 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -305603,10 +276649,10 @@ module \main parameter \Y_WIDTH 32 connect \A \a_n [31:0] connect \B \rb [31:0] - connect \Y $xor$libresoc.v:147663$7318_Y + connect \Y $xor$libresoc.v:148543$7302_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:114" - cell $xor $xor$libresoc.v:147666$7321 + cell $xor $xor$libresoc.v:148546$7305 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -305614,24 +276660,24 @@ module \main parameter \Y_WIDTH 32 connect \A \a_n [63:32] connect \B \rb [63:32] - connect \Y $xor$libresoc.v:147666$7321_Y + connect \Y $xor$libresoc.v:148546$7305_Y end - attribute \src "libresoc.v:147162.7-147162.20" - process $proc$libresoc.v:147162$7368 + attribute \src "libresoc.v:148042.7-148042.20" + process $proc$libresoc.v:148042$7352 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:147684.3-147693.6" - process $proc$libresoc.v:147684$7339 + attribute \src "libresoc.v:148564.3-148573.6" + process $proc$libresoc.v:148564$7323 assign { } { } assign { } { } assign $0\is_32bit[0:0] $1\is_32bit[0:0] - attribute \src "libresoc.v:147685.5-147685.29" + attribute \src "libresoc.v:148565.5-148565.29" switch \initial - attribute \src "libresoc.v:147685.9-147685.17" + attribute \src "libresoc.v:148565.9-148565.17" case 1'1 case end @@ -305647,13 +276693,13 @@ module \main sync always update \is_32bit $0\is_32bit[0:0] end - attribute \src "libresoc.v:147694.3-147716.6" - process $proc$libresoc.v:147694$7340 + attribute \src "libresoc.v:148574.3-148596.6" + process $proc$libresoc.v:148574$7324 assign { } { } assign $0\a_i[63:0] $1\a_i[63:0] - attribute \src "libresoc.v:147695.5-147695.29" + attribute \src "libresoc.v:148575.5-148575.29" switch \initial - attribute \src "libresoc.v:147695.9-147695.17" + attribute \src "libresoc.v:148575.9-148575.17" case 1'1 case end @@ -305686,14 +276732,14 @@ module \main sync always update \a_i $0\a_i[63:0] end - attribute \src "libresoc.v:147717.3-147727.6" - process $proc$libresoc.v:147717$7341 + attribute \src "libresoc.v:148597.3-148607.6" + process $proc$libresoc.v:148597$7325 assign { } { } assign { } { } assign $0\zerohi[0:0] $1\zerohi[0:0] - attribute \src "libresoc.v:147718.5-147718.29" + attribute \src "libresoc.v:148598.5-148598.29" switch \initial - attribute \src "libresoc.v:147718.9-147718.17" + attribute \src "libresoc.v:148598.9-148598.17" case 1'1 case end @@ -305709,14 +276755,14 @@ module \main sync always update \zerohi $0\zerohi[0:0] end - attribute \src "libresoc.v:147728.3-147754.6" - process $proc$libresoc.v:147728$7342 + attribute \src "libresoc.v:148608.3-148634.6" + process $proc$libresoc.v:148608$7326 assign { } { } assign { } { } assign $0\tval[4:0] $1\tval[4:0] - attribute \src "libresoc.v:147729.5-147729.29" + attribute \src "libresoc.v:148609.5-148609.29" switch \initial - attribute \src "libresoc.v:147729.9-147729.17" + attribute \src "libresoc.v:148609.9-148609.17" case 1'1 case end @@ -305754,14 +276800,14 @@ module \main sync always update \tval $0\tval[4:0] end - attribute \src "libresoc.v:147755.3-147773.6" - process $proc$libresoc.v:147755$7343 + attribute \src "libresoc.v:148635.3-148653.6" + process $proc$libresoc.v:148635$7327 assign { } { } assign { } { } assign $0\msb_a[0:0] $1\msb_a[0:0] - attribute \src "libresoc.v:147756.5-147756.29" + attribute \src "libresoc.v:148636.5-148636.29" switch \initial - attribute \src "libresoc.v:147756.9-147756.17" + attribute \src "libresoc.v:148636.9-148636.17" case 1'1 case end @@ -305787,14 +276833,14 @@ module \main sync always update \msb_a $0\msb_a[0:0] end - attribute \src "libresoc.v:147774.3-147792.6" - process $proc$libresoc.v:147774$7344 + attribute \src "libresoc.v:148654.3-148672.6" + process $proc$libresoc.v:148654$7328 assign { } { } assign { } { } assign $0\msb_b[0:0] $1\msb_b[0:0] - attribute \src "libresoc.v:147775.5-147775.29" + attribute \src "libresoc.v:148655.5-148655.29" switch \initial - attribute \src "libresoc.v:147775.9-147775.17" + attribute \src "libresoc.v:148655.9-148655.17" case 1'1 case end @@ -305820,14 +276866,14 @@ module \main sync always update \msb_b $0\msb_b[0:0] end - attribute \src "libresoc.v:147793.3-147819.6" - process $proc$libresoc.v:147793$7345 + attribute \src "libresoc.v:148673.3-148699.6" + process $proc$libresoc.v:148673$7329 assign { } { } assign { } { } assign $0\a_lt[0:0] $1\a_lt[0:0] - attribute \src "libresoc.v:147794.5-147794.29" + attribute \src "libresoc.v:148674.5-148674.29" switch \initial - attribute \src "libresoc.v:147794.9-147794.17" + attribute \src "libresoc.v:148674.9-148674.17" case 1'1 case end @@ -305863,14 +276909,14 @@ module \main sync always update \a_lt $0\a_lt[0:0] end - attribute \src "libresoc.v:147820.3-147845.6" - process $proc$libresoc.v:147820$7346 + attribute \src "libresoc.v:148700.3-148733.6" + process $proc$libresoc.v:148700$7330 assign { } { } assign { } { } assign $0\cr_a[3:0] $1\cr_a[3:0] - attribute \src "libresoc.v:147821.5-147821.29" + attribute \src "libresoc.v:148701.5-148701.29" switch \initial - attribute \src "libresoc.v:147821.9-147821.17" + attribute \src "libresoc.v:148701.9-148701.17" case 1'1 case end @@ -305893,6 +276939,12 @@ module \main assign $2\cr_a[3:2] \tval [1:0] end attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign $1\cr_a[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0011111 + assign $1\cr_a[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" case 7'0001100 assign { } { } assign $1\cr_a[3:0] { 1'0 \$99 2'00 } @@ -305902,14 +276954,14 @@ module \main sync always update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:147846.3-147860.6" - process $proc$libresoc.v:147846$7347 + attribute \src "libresoc.v:148734.3-148756.6" + process $proc$libresoc.v:148734$7331 assign { } { } assign { } { } assign $0\cr_a_ok[0:0] $1\cr_a_ok[0:0] - attribute \src "libresoc.v:147847.5-147847.29" + attribute \src "libresoc.v:148735.5-148735.29" switch \initial - attribute \src "libresoc.v:147847.9-147847.17" + attribute \src "libresoc.v:148735.9-148735.17" case 1'1 case end @@ -305920,6 +276972,12 @@ module \main assign { } { } assign $1\cr_a_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign $1\cr_a_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0011111 + assign $1\cr_a_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 7'0001100 assign { } { } assign $1\cr_a_ok[0:0] 1'1 @@ -305929,20 +276987,23 @@ module \main sync always update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:147861.3-147898.6" - process $proc$libresoc.v:147861$7348 + attribute \src "libresoc.v:148757.3-148798.6" + process $proc$libresoc.v:148757$7332 assign { } { } assign { } { } assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:147862.5-147862.29" + attribute \src "libresoc.v:148758.5-148758.29" switch \initial - attribute \src "libresoc.v:147862.9-147862.17" + attribute \src "libresoc.v:148758.9-148758.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 7'0000010 assign { } { } assign $1\o[63:0] \add_o [64:1] @@ -305989,20 +277050,23 @@ module \main sync always update \o $0\o[63:0] end - attribute \src "libresoc.v:147899.3-147917.6" - process $proc$libresoc.v:147899$7349 + attribute \src "libresoc.v:148799.3-148821.6" + process $proc$libresoc.v:148799$7333 assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:147900.5-147900.29" + attribute \src "libresoc.v:148800.5-148800.29" switch \initial - attribute \src "libresoc.v:147900.9-147900.17" + attribute \src "libresoc.v:148800.9-148800.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign $1\o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 7'0000010 assign { } { } assign $1\o_ok[0:0] 1'1 @@ -306020,20 +277084,23 @@ module \main sync always update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:147918.3-147931.6" - process $proc$libresoc.v:147918$7350 + attribute \src "libresoc.v:148822.3-148839.6" + process $proc$libresoc.v:148822$7334 assign { } { } assign { } { } assign $0\ca[1:0] $1\ca[1:0] - attribute \src "libresoc.v:147919.5-147919.29" + attribute \src "libresoc.v:148823.5-148823.29" switch \initial - attribute \src "libresoc.v:147919.9-147919.17" + attribute \src "libresoc.v:148823.9-148823.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign $1\ca[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" case 7'0000010 assign { } { } assign $1\ca[1:0] [0] \add_o [65] @@ -306044,13 +277111,13 @@ module \main sync always update \ca $0\ca[1:0] end - attribute \src "libresoc.v:147932.3-147954.6" - process $proc$libresoc.v:147932$7351 + attribute \src "libresoc.v:148840.3-148862.6" + process $proc$libresoc.v:148840$7335 assign { } { } assign $0\b_i[63:0] $1\b_i[63:0] - attribute \src "libresoc.v:147933.5-147933.29" + attribute \src "libresoc.v:148841.5-148841.29" switch \initial - attribute \src "libresoc.v:147933.9-147933.17" + attribute \src "libresoc.v:148841.9-148841.17" case 1'1 case end @@ -306083,43 +277150,49 @@ module \main sync always update \b_i $0\b_i[63:0] end - attribute \src "libresoc.v:147955.3-147965.6" - process $proc$libresoc.v:147955$7352 + attribute \src "libresoc.v:148863.3-148877.6" + process $proc$libresoc.v:148863$7336 assign { } { } assign { } { } - assign $0\xer_ca$20[1:0]$7353 $1\xer_ca$20[1:0]$7354 - attribute \src "libresoc.v:147956.5-147956.29" + assign $0\xer_ca$20[1:0]$7337 $1\xer_ca$20[1:0]$7338 + attribute \src "libresoc.v:148864.5-148864.29" switch \initial - attribute \src "libresoc.v:147956.9-147956.17" + attribute \src "libresoc.v:148864.9-148864.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign $1\xer_ca$20[1:0]$7338 2'00 + attribute \src "libresoc.v:0.0-0.0" case 7'0000010 assign { } { } - assign $1\xer_ca$20[1:0]$7354 \ca + assign $1\xer_ca$20[1:0]$7338 \ca case - assign $1\xer_ca$20[1:0]$7354 2'00 + assign $1\xer_ca$20[1:0]$7338 2'00 end sync always - update \xer_ca$20 $0\xer_ca$20[1:0]$7353 + update \xer_ca$20 $0\xer_ca$20[1:0]$7337 end - attribute \src "libresoc.v:147966.3-147976.6" - process $proc$libresoc.v:147966$7355 + attribute \src "libresoc.v:148878.3-148892.6" + process $proc$libresoc.v:148878$7339 assign { } { } assign { } { } assign $0\xer_ca_ok[0:0] $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:147967.5-147967.29" + attribute \src "libresoc.v:148879.5-148879.29" switch \initial - attribute \src "libresoc.v:147967.9-147967.17" + attribute \src "libresoc.v:148879.9-148879.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign $1\xer_ca_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 7'0000010 assign { } { } assign $1\xer_ca_ok[0:0] 1'1 @@ -306129,20 +277202,23 @@ module \main sync always update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:147977.3-147990.6" - process $proc$libresoc.v:147977$7356 + attribute \src "libresoc.v:148893.3-148910.6" + process $proc$libresoc.v:148893$7340 assign { } { } assign { } { } assign $0\ov[1:0] $1\ov[1:0] - attribute \src "libresoc.v:147978.5-147978.29" + attribute \src "libresoc.v:148894.5-148894.29" switch \initial - attribute \src "libresoc.v:147978.9-147978.17" + attribute \src "libresoc.v:148894.9-148894.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign $1\ov[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" case 7'0000010 assign { } { } assign $1\ov[1:0] [0] \$119 @@ -306153,20 +277229,23 @@ module \main sync always update \ov $0\ov[1:0] end - attribute \src "libresoc.v:147991.3-148001.6" - process $proc$libresoc.v:147991$7357 + attribute \src "libresoc.v:148911.3-148925.6" + process $proc$libresoc.v:148911$7341 assign { } { } assign { } { } assign $0\xer_ov[1:0] $1\xer_ov[1:0] - attribute \src "libresoc.v:147992.5-147992.29" + attribute \src "libresoc.v:148912.5-148912.29" switch \initial - attribute \src "libresoc.v:147992.9-147992.17" + attribute \src "libresoc.v:148912.9-148912.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign $1\xer_ov[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" case 7'0000010 assign { } { } assign $1\xer_ov[1:0] \ov @@ -306176,20 +277255,23 @@ module \main sync always update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:148002.3-148012.6" - process $proc$libresoc.v:148002$7358 + attribute \src "libresoc.v:148926.3-148940.6" + process $proc$libresoc.v:148926$7342 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:148003.5-148003.29" + attribute \src "libresoc.v:148927.5-148927.29" switch \initial - attribute \src "libresoc.v:148003.9-148003.17" + attribute \src "libresoc.v:148927.9-148927.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign $1\xer_ov_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 7'0000010 assign { } { } assign $1\xer_ov_ok[0:0] 1'1 @@ -306199,20 +277281,29 @@ module \main sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:148013.3-148023.6" - process $proc$libresoc.v:148013$7359 + attribute \src "libresoc.v:148941.3-148963.6" + process $proc$libresoc.v:148941$7343 assign { } { } assign { } { } assign $0\src1[7:0] $1\src1[7:0] - attribute \src "libresoc.v:148014.5-148014.29" + attribute \src "libresoc.v:148942.5-148942.29" switch \initial - attribute \src "libresoc.v:148014.9-148014.17" + attribute \src "libresoc.v:148942.9-148942.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign $1\src1[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign $1\src1[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0011111 + assign $1\src1[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" case 7'0001100 assign { } { } assign $1\src1[7:0] \ra [7:0] @@ -306222,20 +277313,29 @@ module \main sync always update \src1 $0\src1[7:0] end - attribute \src "libresoc.v:148024.3-148043.6" - process $proc$libresoc.v:148024$7360 + attribute \src "libresoc.v:148964.3-148995.6" + process $proc$libresoc.v:148964$7344 assign { } { } assign { } { } assign $0\eqs[7:0] $1\eqs[7:0] - attribute \src "libresoc.v:148025.5-148025.29" + attribute \src "libresoc.v:148965.5-148965.29" switch \initial - attribute \src "libresoc.v:148025.9-148025.17" + attribute \src "libresoc.v:148965.9-148965.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91" switch \alu_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0001010 + assign $1\eqs[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0000010 + assign $1\eqs[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0011111 + assign $1\eqs[7:0] 8'00000000 + attribute \src "libresoc.v:0.0-0.0" case 7'0001100 assign { } { } assign $1\eqs[7:0] [0] \$129 @@ -306252,14 +277352,14 @@ module \main sync always update \eqs $0\eqs[7:0] end - attribute \src "libresoc.v:148044.3-148053.6" - process $proc$libresoc.v:148044$7361 + attribute \src "libresoc.v:148996.3-149005.6" + process $proc$libresoc.v:148996$7345 assign { } { } assign { } { } assign $0\add_a[65:0] $1\add_a[65:0] - attribute \src "libresoc.v:148045.5-148045.29" + attribute \src "libresoc.v:148997.5-148997.29" switch \initial - attribute \src "libresoc.v:148045.9-148045.17" + attribute \src "libresoc.v:148997.9-148997.17" case 1'1 case end @@ -306275,14 +277375,14 @@ module \main sync always update \add_a $0\add_a[65:0] end - attribute \src "libresoc.v:148054.3-148063.6" - process $proc$libresoc.v:148054$7362 + attribute \src "libresoc.v:149006.3-149015.6" + process $proc$libresoc.v:149006$7346 assign { } { } assign { } { } assign $0\add_b[65:0] $1\add_b[65:0] - attribute \src "libresoc.v:148055.5-148055.29" + attribute \src "libresoc.v:149007.5-149007.29" switch \initial - attribute \src "libresoc.v:148055.9-148055.17" + attribute \src "libresoc.v:149007.9-149007.17" case 1'1 case end @@ -306298,14 +277398,14 @@ module \main sync always update \add_b $0\add_b[65:0] end - attribute \src "libresoc.v:148064.3-148073.6" - process $proc$libresoc.v:148064$7363 + attribute \src "libresoc.v:149016.3-149025.6" + process $proc$libresoc.v:149016$7347 assign { } { } assign { } { } assign $0\add_o[65:0] $1\add_o[65:0] - attribute \src "libresoc.v:148065.5-148065.29" + attribute \src "libresoc.v:149017.5-149017.29" switch \initial - attribute \src "libresoc.v:148065.9-148065.17" + attribute \src "libresoc.v:149017.9-149017.17" case 1'1 case end @@ -306321,14 +277421,14 @@ module \main sync always update \add_o $0\add_o[65:0] end - attribute \src "libresoc.v:148074.3-148084.6" - process $proc$libresoc.v:148074$7364 + attribute \src "libresoc.v:149026.3-149036.6" + process $proc$libresoc.v:149026$7348 assign { } { } assign { } { } assign $0\a_n[63:0] $1\a_n[63:0] - attribute \src "libresoc.v:148075.5-148075.29" + attribute \src "libresoc.v:149027.5-149027.29" switch \initial - attribute \src "libresoc.v:148075.9-148075.17" + attribute \src "libresoc.v:149027.9-149027.17" case 1'1 case end @@ -306344,14 +277444,14 @@ module \main sync always update \a_n $0\a_n[63:0] end - attribute \src "libresoc.v:148085.3-148095.6" - process $proc$libresoc.v:148085$7365 + attribute \src "libresoc.v:149037.3-149047.6" + process $proc$libresoc.v:149037$7349 assign { } { } assign { } { } assign $0\carry_32[0:0] $1\carry_32[0:0] - attribute \src "libresoc.v:148086.5-148086.29" + attribute \src "libresoc.v:149038.5-149038.29" switch \initial - attribute \src "libresoc.v:148086.9-148086.17" + attribute \src "libresoc.v:149038.9-149038.17" case 1'1 case end @@ -306367,14 +277467,14 @@ module \main sync always update \carry_32 $0\carry_32[0:0] end - attribute \src "libresoc.v:148096.3-148106.6" - process $proc$libresoc.v:148096$7366 + attribute \src "libresoc.v:149048.3-149058.6" + process $proc$libresoc.v:149048$7350 assign { } { } assign { } { } assign $0\carry_64[0:0] $1\carry_64[0:0] - attribute \src "libresoc.v:148097.5-148097.29" + attribute \src "libresoc.v:149049.5-149049.29" switch \initial - attribute \src "libresoc.v:148097.9-148097.17" + attribute \src "libresoc.v:149049.9-149049.17" case 1'1 case end @@ -306390,14 +277490,14 @@ module \main sync always update \carry_64 $0\carry_64[0:0] end - attribute \src "libresoc.v:148107.3-148117.6" - process $proc$libresoc.v:148107$7367 + attribute \src "libresoc.v:149059.3-149069.6" + process $proc$libresoc.v:149059$7351 assign { } { } assign { } { } assign $0\zerolo[0:0] $1\zerolo[0:0] - attribute \src "libresoc.v:148108.5-148108.29" + attribute \src "libresoc.v:149060.5-149060.29" switch \initial - attribute \src "libresoc.v:148108.9-148108.17" + attribute \src "libresoc.v:149060.9-149060.17" case 1'1 case end @@ -306413,88 +277513,88 @@ module \main sync always update \zerolo $0\zerolo[0:0] end - connect \$99 $reduce_or$libresoc.v:147623$7278_Y - connect \$101 $eq$libresoc.v:147624$7279_Y - connect \$103 $eq$libresoc.v:147625$7280_Y - connect \$105 $eq$libresoc.v:147626$7281_Y - connect \$107 $reduce_or$libresoc.v:147627$7282_Y - connect \$109 $xor$libresoc.v:147628$7283_Y - connect \$111 $xor$libresoc.v:147629$7284_Y - connect \$113 $xor$libresoc.v:147630$7285_Y - connect \$116 $xor$libresoc.v:147631$7286_Y - connect \$115 $not$libresoc.v:147632$7287_Y - connect \$119 $and$libresoc.v:147633$7288_Y - connect \$121 $xor$libresoc.v:147634$7289_Y - connect \$124 $xor$libresoc.v:147635$7290_Y - connect \$123 $not$libresoc.v:147636$7291_Y - connect \$127 $and$libresoc.v:147637$7292_Y - connect \$129 $eq$libresoc.v:147638$7293_Y - connect \$131 $eq$libresoc.v:147639$7294_Y - connect \$133 $eq$libresoc.v:147640$7295_Y - connect \$135 $eq$libresoc.v:147641$7296_Y - connect \$137 $eq$libresoc.v:147642$7297_Y - connect \$139 $eq$libresoc.v:147643$7298_Y - connect \$141 $eq$libresoc.v:147644$7299_Y - connect \$143 $eq$libresoc.v:147645$7300_Y - connect \$22 $eq$libresoc.v:147646$7301_Y - connect \$24 $not$libresoc.v:147647$7302_Y - connect \$26 $eq$libresoc.v:147648$7303_Y - connect \$28 $eq$libresoc.v:147649$7304_Y - connect \$30 $eq$libresoc.v:147650$7305_Y - connect \$32 $eq$libresoc.v:147651$7306_Y - connect \$34 $or$libresoc.v:147652$7307_Y - connect \$36 $eq$libresoc.v:147653$7308_Y - connect \$38 $eq$libresoc.v:147654$7309_Y - connect \$40 $or$libresoc.v:147655$7310_Y - connect \$42 $eq$libresoc.v:147656$7311_Y - connect \$44 $eq$libresoc.v:147657$7312_Y - connect \$46 $or$libresoc.v:147658$7313_Y - connect \$49 $add$libresoc.v:147659$7314_Y - connect \$51 $not$libresoc.v:147660$7315_Y - connect \$53 $xor$libresoc.v:147661$7316_Y - connect \$55 $xor$libresoc.v:147662$7317_Y - connect \$59 $xor$libresoc.v:147663$7318_Y - connect \$58 $reduce_or$libresoc.v:147664$7319_Y - connect \$57 $not$libresoc.v:147665$7320_Y - connect \$65 $xor$libresoc.v:147666$7321_Y - connect \$64 $reduce_or$libresoc.v:147667$7322_Y - connect \$63 $not$libresoc.v:147668$7323_Y - connect \$69 $or$libresoc.v:147669$7324_Y - connect \$71 $and$libresoc.v:147670$7325_Y - connect \$73 $ne$libresoc.v:147671$7326_Y - connect \$75 $not$libresoc.v:147672$7327_Y - connect \$77 $not$libresoc.v:147673$7328_Y - connect \$79 $or$libresoc.v:147674$7329_Y - connect \$81 $and$libresoc.v:147675$7330_Y - connect \$83 $ternary$libresoc.v:147676$7331_Y - connect \$85 $or$libresoc.v:147677$7332_Y - connect \$87 $and$libresoc.v:147678$7333_Y - connect \$89 $ternary$libresoc.v:147679$7334_Y - connect \$91 $or$libresoc.v:147680$7335_Y - connect \$93 $and$libresoc.v:147681$7336_Y - connect \$95 $ne$libresoc.v:147682$7337_Y - connect \$97 $ternary$libresoc.v:147683$7338_Y + connect \$99 $reduce_or$libresoc.v:148503$7262_Y + connect \$101 $eq$libresoc.v:148504$7263_Y + connect \$103 $eq$libresoc.v:148505$7264_Y + connect \$105 $eq$libresoc.v:148506$7265_Y + connect \$107 $reduce_or$libresoc.v:148507$7266_Y + connect \$109 $xor$libresoc.v:148508$7267_Y + connect \$111 $xor$libresoc.v:148509$7268_Y + connect \$113 $xor$libresoc.v:148510$7269_Y + connect \$116 $xor$libresoc.v:148511$7270_Y + connect \$115 $not$libresoc.v:148512$7271_Y + connect \$119 $and$libresoc.v:148513$7272_Y + connect \$121 $xor$libresoc.v:148514$7273_Y + connect \$124 $xor$libresoc.v:148515$7274_Y + connect \$123 $not$libresoc.v:148516$7275_Y + connect \$127 $and$libresoc.v:148517$7276_Y + connect \$129 $eq$libresoc.v:148518$7277_Y + connect \$131 $eq$libresoc.v:148519$7278_Y + connect \$133 $eq$libresoc.v:148520$7279_Y + connect \$135 $eq$libresoc.v:148521$7280_Y + connect \$137 $eq$libresoc.v:148522$7281_Y + connect \$139 $eq$libresoc.v:148523$7282_Y + connect \$141 $eq$libresoc.v:148524$7283_Y + connect \$143 $eq$libresoc.v:148525$7284_Y + connect \$22 $eq$libresoc.v:148526$7285_Y + connect \$24 $not$libresoc.v:148527$7286_Y + connect \$26 $eq$libresoc.v:148528$7287_Y + connect \$28 $eq$libresoc.v:148529$7288_Y + connect \$30 $eq$libresoc.v:148530$7289_Y + connect \$32 $eq$libresoc.v:148531$7290_Y + connect \$34 $or$libresoc.v:148532$7291_Y + connect \$36 $eq$libresoc.v:148533$7292_Y + connect \$38 $eq$libresoc.v:148534$7293_Y + connect \$40 $or$libresoc.v:148535$7294_Y + connect \$42 $eq$libresoc.v:148536$7295_Y + connect \$44 $eq$libresoc.v:148537$7296_Y + connect \$46 $or$libresoc.v:148538$7297_Y + connect \$49 $add$libresoc.v:148539$7298_Y + connect \$51 $not$libresoc.v:148540$7299_Y + connect \$53 $xor$libresoc.v:148541$7300_Y + connect \$55 $xor$libresoc.v:148542$7301_Y + connect \$59 $xor$libresoc.v:148543$7302_Y + connect \$58 $reduce_or$libresoc.v:148544$7303_Y + connect \$57 $not$libresoc.v:148545$7304_Y + connect \$65 $xor$libresoc.v:148546$7305_Y + connect \$64 $reduce_or$libresoc.v:148547$7306_Y + connect \$63 $not$libresoc.v:148548$7307_Y + connect \$69 $or$libresoc.v:148549$7308_Y + connect \$71 $and$libresoc.v:148550$7309_Y + connect \$73 $ne$libresoc.v:148551$7310_Y + connect \$75 $not$libresoc.v:148552$7311_Y + connect \$77 $not$libresoc.v:148553$7312_Y + connect \$79 $or$libresoc.v:148554$7313_Y + connect \$81 $and$libresoc.v:148555$7314_Y + connect \$83 $ternary$libresoc.v:148556$7315_Y + connect \$85 $or$libresoc.v:148557$7316_Y + connect \$87 $and$libresoc.v:148558$7317_Y + connect \$89 $ternary$libresoc.v:148559$7318_Y + connect \$91 $or$libresoc.v:148560$7319_Y + connect \$93 $and$libresoc.v:148561$7320_Y + connect \$95 $ne$libresoc.v:148562$7321_Y + connect \$97 $ternary$libresoc.v:148563$7322_Y connect \$48 \$49 connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } connect \muxid$1 \muxid connect \xer_so$21 \xer_so end -attribute \src "libresoc.v:148126.1-148540.10" +attribute \src "libresoc.v:149078.1-149492.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main" attribute \generator "nMigen" module \main$114 - attribute \src "libresoc.v:148127.7-148127.20" + attribute \src "libresoc.v:149079.7-149079.20" wire $0\initial[0:0] - attribute \src "libresoc.v:148492.3-148522.6" + attribute \src "libresoc.v:149444.3-149474.6" wire width 4 $0\mode[3:0] - attribute \src "libresoc.v:148457.3-148491.6" + attribute \src "libresoc.v:149409.3-149443.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:148492.3-148522.6" + attribute \src "libresoc.v:149444.3-149474.6" wire width 4 $1\mode[3:0] - attribute \src "libresoc.v:148457.3-148491.6" + attribute \src "libresoc.v:149409.3-149443.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:148127.7-148127.15" + attribute \src "libresoc.v:149079.7-149079.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:46" wire width 5 \mb @@ -306809,7 +277909,7 @@ module \main$114 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 42 \xer_so$19 attribute \module_not_derived 1 - attribute \src "libresoc.v:148441.11-148456.4" + attribute \src "libresoc.v:149393.11-149408.4" cell \rotator \rotator connect \arith \rotator_arith connect \carry_out_o \rotator_carry_out_o @@ -306826,22 +277926,22 @@ module \main$114 connect \shift \rotator_shift connect \sign_ext_rs \rotator_sign_ext_rs end - attribute \src "libresoc.v:148127.7-148127.20" - process $proc$libresoc.v:148127$7371 + attribute \src "libresoc.v:149079.7-149079.20" + process $proc$libresoc.v:149079$7355 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:148457.3-148491.6" - process $proc$libresoc.v:148457$7369 + attribute \src "libresoc.v:149409.3-149443.6" + process $proc$libresoc.v:149409$7353 assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:148458.5-148458.29" + attribute \src "libresoc.v:149410.5-149410.29" switch \initial - attribute \src "libresoc.v:148458.9-148458.17" + attribute \src "libresoc.v:149410.9-149410.17" case 1'1 case end @@ -306873,14 +277973,14 @@ module \main$114 sync always update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:148492.3-148522.6" - process $proc$libresoc.v:148492$7370 + attribute \src "libresoc.v:149444.3-149474.6" + process $proc$libresoc.v:149444$7354 assign { } { } assign { } { } assign $0\mode[3:0] $1\mode[3:0] - attribute \src "libresoc.v:148493.5-148493.29" + attribute \src "libresoc.v:149445.5-149445.29" switch \initial - attribute \src "libresoc.v:148493.9-148493.17" + attribute \src "libresoc.v:149445.9-149445.17" case 1'1 case end @@ -306934,109 +278034,109 @@ module \main$114 connect \me \sr_op__insn [5:1] connect \mb \sr_op__insn [10:6] end -attribute \src "libresoc.v:148544.1-149080.10" +attribute \src "libresoc.v:149496.1-150036.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.main" attribute \generator "nMigen" module \main$22 - attribute \src "libresoc.v:148987.3-149010.6" + attribute \src "libresoc.v:149943.3-149966.6" wire $0\bc_taken[0:0] - attribute \src "libresoc.v:148866.3-148877.6" + attribute \src "libresoc.v:149818.3-149829.6" wire width 64 $0\br_addr[63:0] - attribute \src "libresoc.v:148878.3-148904.6" + attribute \src "libresoc.v:149830.3-149856.6" wire width 64 $0\br_imm_addr[63:0] - attribute \src "libresoc.v:148905.3-148923.6" + attribute \src "libresoc.v:149857.3-149875.6" wire $0\br_taken[0:0] - attribute \src "libresoc.v:148959.3-148973.6" + attribute \src "libresoc.v:149915.3-149929.6" wire $0\cr_bit[0:0] - attribute \src "libresoc.v:149037.3-149057.6" + attribute \src "libresoc.v:149993.3-150013.6" wire width 64 $0\ctr_m[63:0] - attribute \src "libresoc.v:149011.3-149023.6" + attribute \src "libresoc.v:149967.3-149979.6" wire width 64 $0\ctr_n[63:0] - attribute \src "libresoc.v:148974.3-148986.6" + attribute \src "libresoc.v:149930.3-149942.6" wire $0\ctr_write[0:0] - attribute \src "libresoc.v:149058.3-149070.6" + attribute \src "libresoc.v:150014.3-150026.6" wire $0\ctr_zero_bo1[0:0] - attribute \src "libresoc.v:149024.3-149036.6" - wire width 64 $0\fast1$10[63:0]$7404 - attribute \src "libresoc.v:148924.3-148938.6" + attribute \src "libresoc.v:149980.3-149992.6" + wire width 64 $0\fast1$10[63:0]$7388 + attribute \src "libresoc.v:149876.3-149894.6" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:148939.3-148948.6" - wire width 64 $0\fast2$11[63:0]$7396 - attribute \src "libresoc.v:148949.3-148958.6" + attribute \src "libresoc.v:149895.3-149904.6" + wire width 64 $0\fast2$11[63:0]$7380 + attribute \src "libresoc.v:149905.3-149914.6" wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:148545.7-148545.20" + attribute \src "libresoc.v:149497.7-149497.20" wire $0\initial[0:0] - attribute \src "libresoc.v:148987.3-149010.6" + attribute \src "libresoc.v:149943.3-149966.6" wire $1\bc_taken[0:0] - attribute \src "libresoc.v:148866.3-148877.6" + attribute \src "libresoc.v:149818.3-149829.6" wire width 64 $1\br_addr[63:0] - attribute \src "libresoc.v:148878.3-148904.6" + attribute \src "libresoc.v:149830.3-149856.6" wire width 64 $1\br_imm_addr[63:0] - attribute \src "libresoc.v:148905.3-148923.6" + attribute \src "libresoc.v:149857.3-149875.6" wire $1\br_taken[0:0] - attribute \src "libresoc.v:148959.3-148973.6" + attribute \src "libresoc.v:149915.3-149929.6" wire $1\cr_bit[0:0] - attribute \src "libresoc.v:149037.3-149057.6" + attribute \src "libresoc.v:149993.3-150013.6" wire width 64 $1\ctr_m[63:0] - attribute \src "libresoc.v:149011.3-149023.6" + attribute \src "libresoc.v:149967.3-149979.6" wire width 64 $1\ctr_n[63:0] - attribute \src "libresoc.v:148974.3-148986.6" + attribute \src "libresoc.v:149930.3-149942.6" wire $1\ctr_write[0:0] - attribute \src "libresoc.v:149058.3-149070.6" + attribute \src "libresoc.v:150014.3-150026.6" wire $1\ctr_zero_bo1[0:0] - attribute \src "libresoc.v:149024.3-149036.6" - wire width 64 $1\fast1$10[63:0]$7405 - attribute \src "libresoc.v:148924.3-148938.6" + attribute \src "libresoc.v:149980.3-149992.6" + wire width 64 $1\fast1$10[63:0]$7389 + attribute \src "libresoc.v:149876.3-149894.6" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:148939.3-148948.6" - wire width 64 $1\fast2$11[63:0]$7397 - attribute \src "libresoc.v:148949.3-148958.6" + attribute \src "libresoc.v:149895.3-149904.6" + wire width 64 $1\fast2$11[63:0]$7381 + attribute \src "libresoc.v:149905.3-149914.6" wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:148987.3-149010.6" + attribute \src "libresoc.v:149943.3-149966.6" wire $2\bc_taken[0:0] - attribute \src "libresoc.v:148878.3-148904.6" + attribute \src "libresoc.v:149830.3-149856.6" wire width 64 $2\br_imm_addr[63:0] - attribute \src "libresoc.v:149037.3-149057.6" + attribute \src "libresoc.v:149993.3-150013.6" wire width 64 $2\ctr_m[63:0] - attribute \src "libresoc.v:148850.18-148850.119" - wire width 65 $add$libresoc.v:148850$7374_Y - attribute \src "libresoc.v:148865.18-148865.113" - wire width 65 $add$libresoc.v:148865$7390_Y - attribute \src "libresoc.v:148857.18-148857.115" - wire $and$libresoc.v:148857$7381_Y - attribute \src "libresoc.v:148858.18-148858.117" - wire $and$libresoc.v:148858$7382_Y - attribute \src "libresoc.v:148864.18-148864.118" - wire $and$libresoc.v:148864$7389_Y - attribute \src "libresoc.v:148848.18-148848.120" - wire $eq$libresoc.v:148848$7372_Y - attribute \src "libresoc.v:148851.18-148851.111" - wire $eq$libresoc.v:148851$7375_Y - attribute \src "libresoc.v:148853.18-148853.111" - wire $eq$libresoc.v:148853$7377_Y - attribute \src "libresoc.v:148854.18-148854.111" - wire $eq$libresoc.v:148854$7378_Y - attribute \src "libresoc.v:148855.18-148855.109" - wire $eq$libresoc.v:148855$7379_Y - attribute \src "libresoc.v:148860.18-148860.98" - wire width 64 $extend$libresoc.v:148860$7384_Y - attribute \src "libresoc.v:148856.18-148856.104" - wire $not$libresoc.v:148856$7380_Y - attribute \src "libresoc.v:148863.18-148863.112" - wire $not$libresoc.v:148863$7388_Y - attribute \src "libresoc.v:148849.18-148849.116" - wire $or$libresoc.v:148849$7373_Y - attribute \src "libresoc.v:148852.18-148852.109" - wire $or$libresoc.v:148852$7376_Y - attribute \src "libresoc.v:148860.18-148860.98" - wire width 64 $pos$libresoc.v:148860$7385_Y - attribute \src "libresoc.v:148861.18-148861.103" - wire $reduce_or$libresoc.v:148861$7386_Y - attribute \src "libresoc.v:148859.18-148859.108" - wire width 65 $sub$libresoc.v:148859$7383_Y - attribute \src "libresoc.v:148862.18-148862.108" - wire $xor$libresoc.v:148862$7387_Y + attribute \src "libresoc.v:149802.18-149802.119" + wire width 65 $add$libresoc.v:149802$7358_Y + attribute \src "libresoc.v:149817.18-149817.113" + wire width 65 $add$libresoc.v:149817$7374_Y + attribute \src "libresoc.v:149809.18-149809.115" + wire $and$libresoc.v:149809$7365_Y + attribute \src "libresoc.v:149810.18-149810.117" + wire $and$libresoc.v:149810$7366_Y + attribute \src "libresoc.v:149816.18-149816.118" + wire $and$libresoc.v:149816$7373_Y + attribute \src "libresoc.v:149800.18-149800.120" + wire $eq$libresoc.v:149800$7356_Y + attribute \src "libresoc.v:149803.18-149803.111" + wire $eq$libresoc.v:149803$7359_Y + attribute \src "libresoc.v:149805.18-149805.111" + wire $eq$libresoc.v:149805$7361_Y + attribute \src "libresoc.v:149806.18-149806.111" + wire $eq$libresoc.v:149806$7362_Y + attribute \src "libresoc.v:149807.18-149807.109" + wire $eq$libresoc.v:149807$7363_Y + attribute \src "libresoc.v:149812.18-149812.98" + wire width 64 $extend$libresoc.v:149812$7368_Y + attribute \src "libresoc.v:149808.18-149808.104" + wire $not$libresoc.v:149808$7364_Y + attribute \src "libresoc.v:149815.18-149815.112" + wire $not$libresoc.v:149815$7372_Y + attribute \src "libresoc.v:149801.18-149801.116" + wire $or$libresoc.v:149801$7357_Y + attribute \src "libresoc.v:149804.18-149804.109" + wire $or$libresoc.v:149804$7360_Y + attribute \src "libresoc.v:149812.18-149812.98" + wire width 64 $pos$libresoc.v:149812$7369_Y + attribute \src "libresoc.v:149813.18-149813.103" + wire $reduce_or$libresoc.v:149813$7370_Y + attribute \src "libresoc.v:149811.18-149811.108" + wire width 65 $sub$libresoc.v:149811$7367_Y + attribute \src "libresoc.v:149814.18-149814.108" + wire $xor$libresoc.v:149814$7371_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" wire \$12 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" @@ -307327,7 +278427,7 @@ module \main$22 wire width 64 output 23 \fast2$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 24 \fast2_ok - attribute \src "libresoc.v:148545.7-148545.15" + attribute \src "libresoc.v:149497.7-149497.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 27 \muxid @@ -307338,7 +278438,7 @@ module \main$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 26 \nia_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" - cell $add $add$libresoc.v:148850$7374 + cell $add $add$libresoc.v:149802$7358 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -307346,10 +278446,10 @@ module \main$22 parameter \Y_WIDTH 65 connect \A \br_imm_addr connect \B \br_op__cia - connect \Y $add$libresoc.v:148850$7374_Y + connect \Y $add$libresoc.v:149802$7358_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" - cell $add $add$libresoc.v:148865$7390 + cell $add $add$libresoc.v:149817$7374 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -307357,10 +278457,10 @@ module \main$22 parameter \Y_WIDTH 65 connect \A \br_op__cia connect \B 3'100 - connect \Y $add$libresoc.v:148865$7390_Y + connect \Y $add$libresoc.v:149817$7374_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" - cell $and $and$libresoc.v:148857$7381 + cell $and $and$libresoc.v:149809$7365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -307368,10 +278468,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \ctr_zero_bo1 connect \B \$29 - connect \Y $and$libresoc.v:148857$7381_Y + connect \Y $and$libresoc.v:149809$7365_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:140" - cell $and $and$libresoc.v:148858$7382 + cell $and $and$libresoc.v:149810$7366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -307379,10 +278479,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \ctr_zero_bo1 connect \B \cr_bit - connect \Y $and$libresoc.v:148858$7382_Y + connect \Y $and$libresoc.v:149810$7366_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" - cell $and $and$libresoc.v:148864$7389 + cell $and $and$libresoc.v:149816$7373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -307390,10 +278490,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \br_op__insn [10] connect \B \$44 - connect \Y $and$libresoc.v:148864$7389_Y + connect \Y $and$libresoc.v:149816$7373_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" - cell $eq $eq$libresoc.v:148848$7372 + cell $eq $eq$libresoc.v:149800$7356 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -307401,10 +278501,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \br_op__insn_type connect \B 7'0001000 - connect \Y $eq$libresoc.v:148848$7372_Y + connect \Y $eq$libresoc.v:149800$7356_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" - cell $eq $eq$libresoc.v:148851$7375 + cell $eq $eq$libresoc.v:149803$7359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -307412,10 +278512,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \cr_bit connect \B \bo [3] - connect \Y $eq$libresoc.v:148851$7375_Y + connect \Y $eq$libresoc.v:149803$7359_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" - cell $eq $eq$libresoc.v:148853$7377 + cell $eq $eq$libresoc.v:149805$7361 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -307423,10 +278523,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \bo [4:3] connect \B 1'0 - connect \Y $eq$libresoc.v:148853$7377_Y + connect \Y $eq$libresoc.v:149805$7361_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" - cell $eq $eq$libresoc.v:148854$7378 + cell $eq $eq$libresoc.v:149806$7362 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -307434,10 +278534,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \bo [4:3] connect \B 1'1 - connect \Y $eq$libresoc.v:148854$7378_Y + connect \Y $eq$libresoc.v:149806$7362_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" - cell $eq $eq$libresoc.v:148855$7379 + cell $eq $eq$libresoc.v:149807$7363 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -307445,34 +278545,34 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \bo [4] connect \B 1'1 - connect \Y $eq$libresoc.v:148855$7379_Y + connect \Y $eq$libresoc.v:149807$7363_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:148860$7384 + cell $pos $extend$libresoc.v:149812$7368 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \fast1 [31:0] - connect \Y $extend$libresoc.v:148860$7384_Y + connect \Y $extend$libresoc.v:149812$7368_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" - cell $not $not$libresoc.v:148856$7380 + cell $not $not$libresoc.v:149808$7364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cr_bit - connect \Y $not$libresoc.v:148856$7380_Y + connect \Y $not$libresoc.v:149808$7364_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" - cell $not $not$libresoc.v:148863$7388 + cell $not $not$libresoc.v:149815$7372 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \br_op__insn [6] - connect \Y $not$libresoc.v:148863$7388_Y + connect \Y $not$libresoc.v:149815$7372_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" - cell $or $or$libresoc.v:148849$7373 + cell $or $or$libresoc.v:149801$7357 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -307480,10 +278580,10 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \br_op__insn [1] connect \B \$12 - connect \Y $or$libresoc.v:148849$7373_Y + connect \Y $or$libresoc.v:149801$7357_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" - cell $or $or$libresoc.v:148852$7376 + cell $or $or$libresoc.v:149804$7360 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -307491,26 +278591,26 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \$19 connect \B \bo [4] - connect \Y $or$libresoc.v:148852$7376_Y + connect \Y $or$libresoc.v:149804$7360_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:148860$7385 + cell $pos $pos$libresoc.v:149812$7369 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:148860$7384_Y - connect \Y $pos$libresoc.v:148860$7385_Y + connect \A $extend$libresoc.v:149812$7368_Y + connect \Y $pos$libresoc.v:149812$7369_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" - cell $reduce_or $reduce_or$libresoc.v:148861$7386 + cell $reduce_or $reduce_or$libresoc.v:149813$7370 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \ctr_n - connect \Y $reduce_or$libresoc.v:148861$7386_Y + connect \Y $reduce_or$libresoc.v:149813$7370_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" - cell $sub $sub$libresoc.v:148859$7383 + cell $sub $sub$libresoc.v:149811$7367 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -307518,10 +278618,10 @@ module \main$22 parameter \Y_WIDTH 65 connect \A \fast1 connect \B 1'1 - connect \Y $sub$libresoc.v:148859$7383_Y + connect \Y $sub$libresoc.v:149811$7367_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" - cell $xor $xor$libresoc.v:148862$7387 + cell $xor $xor$libresoc.v:149814$7371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -307529,23 +278629,23 @@ module \main$22 parameter \Y_WIDTH 1 connect \A \bo [1] connect \B \$40 - connect \Y $xor$libresoc.v:148862$7387_Y + connect \Y $xor$libresoc.v:149814$7371_Y end - attribute \src "libresoc.v:148545.7-148545.20" - process $proc$libresoc.v:148545$7408 + attribute \src "libresoc.v:149497.7-149497.20" + process $proc$libresoc.v:149497$7392 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:148866.3-148877.6" - process $proc$libresoc.v:148866$7391 + attribute \src "libresoc.v:149818.3-149829.6" + process $proc$libresoc.v:149818$7375 assign { } { } assign $0\br_addr[63:0] $1\br_addr[63:0] - attribute \src "libresoc.v:148867.5-148867.29" + attribute \src "libresoc.v:149819.5-149819.29" switch \initial - attribute \src "libresoc.v:148867.9-148867.17" + attribute \src "libresoc.v:149819.9-149819.17" case 1'1 case end @@ -307563,14 +278663,14 @@ module \main$22 sync always update \br_addr $0\br_addr[63:0] end - attribute \src "libresoc.v:148878.3-148904.6" - process $proc$libresoc.v:148878$7392 + attribute \src "libresoc.v:149830.3-149856.6" + process $proc$libresoc.v:149830$7376 assign { } { } assign { } { } assign $0\br_imm_addr[63:0] $1\br_imm_addr[63:0] - attribute \src "libresoc.v:148879.5-148879.29" + attribute \src "libresoc.v:149831.5-149831.29" switch \initial - attribute \src "libresoc.v:148879.9-148879.17" + attribute \src "libresoc.v:149831.9-149831.17" case 1'1 case end @@ -307605,14 +278705,14 @@ module \main$22 sync always update \br_imm_addr $0\br_imm_addr[63:0] end - attribute \src "libresoc.v:148905.3-148923.6" - process $proc$libresoc.v:148905$7393 + attribute \src "libresoc.v:149857.3-149875.6" + process $proc$libresoc.v:149857$7377 assign { } { } assign { } { } assign $0\br_taken[0:0] $1\br_taken[0:0] - attribute \src "libresoc.v:148906.5-148906.29" + attribute \src "libresoc.v:149858.5-149858.29" switch \initial - attribute \src "libresoc.v:148906.9-148906.17" + attribute \src "libresoc.v:149858.9-149858.17" case 1'1 case end @@ -307636,20 +278736,23 @@ module \main$22 sync always update \br_taken $0\br_taken[0:0] end - attribute \src "libresoc.v:148924.3-148938.6" - process $proc$libresoc.v:148924$7394 + attribute \src "libresoc.v:149876.3-149894.6" + process $proc$libresoc.v:149876$7378 assign { } { } assign { } { } assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] - attribute \src "libresoc.v:148925.5-148925.29" + attribute \src "libresoc.v:149877.5-149877.29" switch \initial - attribute \src "libresoc.v:148925.9-148925.17" + attribute \src "libresoc.v:149877.9-149877.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" switch \br_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0000110 + assign $1\fast1_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 7'0000111 assign { } { } assign $1\fast1_ok[0:0] \ctr_write @@ -307663,14 +278766,14 @@ module \main$22 sync always update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:148939.3-148948.6" - process $proc$libresoc.v:148939$7395 + attribute \src "libresoc.v:149895.3-149904.6" + process $proc$libresoc.v:149895$7379 assign { } { } assign { } { } - assign $0\fast2$11[63:0]$7396 $1\fast2$11[63:0]$7397 - attribute \src "libresoc.v:148940.5-148940.29" + assign $0\fast2$11[63:0]$7380 $1\fast2$11[63:0]$7381 + attribute \src "libresoc.v:149896.5-149896.29" switch \initial - attribute \src "libresoc.v:148940.9-148940.17" + attribute \src "libresoc.v:149896.9-149896.17" case 1'1 case end @@ -307679,21 +278782,21 @@ module \main$22 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\fast2$11[63:0]$7397 \$48 [63:0] + assign $1\fast2$11[63:0]$7381 \$48 [63:0] case - assign $1\fast2$11[63:0]$7397 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast2$11[63:0]$7381 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fast2$11 $0\fast2$11[63:0]$7396 + update \fast2$11 $0\fast2$11[63:0]$7380 end - attribute \src "libresoc.v:148949.3-148958.6" - process $proc$libresoc.v:148949$7398 + attribute \src "libresoc.v:149905.3-149914.6" + process $proc$libresoc.v:149905$7382 assign { } { } assign { } { } assign $0\fast2_ok[0:0] $1\fast2_ok[0:0] - attribute \src "libresoc.v:148950.5-148950.29" + attribute \src "libresoc.v:149906.5-149906.29" switch \initial - attribute \src "libresoc.v:148950.9-148950.17" + attribute \src "libresoc.v:149906.9-149906.17" case 1'1 case end @@ -307709,14 +278812,14 @@ module \main$22 sync always update \fast2_ok $0\fast2_ok[0:0] end - attribute \src "libresoc.v:148959.3-148973.6" - process $proc$libresoc.v:148959$7399 + attribute \src "libresoc.v:149915.3-149929.6" + process $proc$libresoc.v:149915$7383 assign { } { } assign { } { } assign $0\cr_bit[0:0] $1\cr_bit[0:0] - attribute \src "libresoc.v:148960.5-148960.29" + attribute \src "libresoc.v:149916.5-149916.29" switch \initial - attribute \src "libresoc.v:148960.9-148960.17" + attribute \src "libresoc.v:149916.9-149916.17" case 1'1 case end @@ -307744,14 +278847,14 @@ module \main$22 sync always update \cr_bit $0\cr_bit[0:0] end - attribute \src "libresoc.v:148974.3-148986.6" - process $proc$libresoc.v:148974$7400 + attribute \src "libresoc.v:149930.3-149942.6" + process $proc$libresoc.v:149930$7384 assign { } { } assign { } { } assign $0\ctr_write[0:0] $1\ctr_write[0:0] - attribute \src "libresoc.v:148975.5-148975.29" + attribute \src "libresoc.v:149931.5-149931.29" switch \initial - attribute \src "libresoc.v:148975.9-148975.17" + attribute \src "libresoc.v:149931.9-149931.17" case 1'1 case end @@ -307768,14 +278871,14 @@ module \main$22 sync always update \ctr_write $0\ctr_write[0:0] end - attribute \src "libresoc.v:148987.3-149010.6" - process $proc$libresoc.v:148987$7401 + attribute \src "libresoc.v:149943.3-149966.6" + process $proc$libresoc.v:149943$7385 assign { } { } assign { } { } assign $0\bc_taken[0:0] $1\bc_taken[0:0] - attribute \src "libresoc.v:148988.5-148988.29" + attribute \src "libresoc.v:149944.5-149944.29" switch \initial - attribute \src "libresoc.v:148988.9-148988.17" + attribute \src "libresoc.v:149944.9-149944.17" case 1'1 case end @@ -307810,14 +278913,14 @@ module \main$22 sync always update \bc_taken $0\bc_taken[0:0] end - attribute \src "libresoc.v:149011.3-149023.6" - process $proc$libresoc.v:149011$7402 + attribute \src "libresoc.v:149967.3-149979.6" + process $proc$libresoc.v:149967$7386 assign { } { } assign { } { } assign $0\ctr_n[63:0] $1\ctr_n[63:0] - attribute \src "libresoc.v:149012.5-149012.29" + attribute \src "libresoc.v:149968.5-149968.29" switch \initial - attribute \src "libresoc.v:149012.9-149012.17" + attribute \src "libresoc.v:149968.9-149968.17" case 1'1 case end @@ -307834,14 +278937,14 @@ module \main$22 sync always update \ctr_n $0\ctr_n[63:0] end - attribute \src "libresoc.v:149024.3-149036.6" - process $proc$libresoc.v:149024$7403 + attribute \src "libresoc.v:149980.3-149992.6" + process $proc$libresoc.v:149980$7387 assign { } { } assign { } { } - assign $0\fast1$10[63:0]$7404 $1\fast1$10[63:0]$7405 - attribute \src "libresoc.v:149025.5-149025.29" + assign $0\fast1$10[63:0]$7388 $1\fast1$10[63:0]$7389 + attribute \src "libresoc.v:149981.5-149981.29" switch \initial - attribute \src "libresoc.v:149025.9-149025.17" + attribute \src "libresoc.v:149981.9-149981.17" case 1'1 case end @@ -307849,23 +278952,23 @@ module \main$22 switch \bo [2] attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $1\fast1$10[63:0]$7405 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$10[63:0]$7389 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\fast1$10[63:0]$7405 \ctr_n + assign $1\fast1$10[63:0]$7389 \ctr_n end sync always - update \fast1$10 $0\fast1$10[63:0]$7404 + update \fast1$10 $0\fast1$10[63:0]$7388 end - attribute \src "libresoc.v:149037.3-149057.6" - process $proc$libresoc.v:149037$7406 + attribute \src "libresoc.v:149993.3-150013.6" + process $proc$libresoc.v:149993$7390 assign { } { } assign { } { } assign $0\ctr_m[63:0] $1\ctr_m[63:0] - attribute \src "libresoc.v:149038.5-149038.29" + attribute \src "libresoc.v:149994.5-149994.29" switch \initial - attribute \src "libresoc.v:149038.9-149038.17" + attribute \src "libresoc.v:149994.9-149994.17" case 1'1 case end @@ -307893,14 +278996,14 @@ module \main$22 sync always update \ctr_m $0\ctr_m[63:0] end - attribute \src "libresoc.v:149058.3-149070.6" - process $proc$libresoc.v:149058$7407 + attribute \src "libresoc.v:150014.3-150026.6" + process $proc$libresoc.v:150014$7391 assign { } { } assign { } { } assign $0\ctr_zero_bo1[0:0] $1\ctr_zero_bo1[0:0] - attribute \src "libresoc.v:149059.5-149059.29" + attribute \src "libresoc.v:150015.5-150015.29" switch \initial - attribute \src "libresoc.v:149059.9-149059.17" + attribute \src "libresoc.v:150015.9-150015.17" case 1'1 case end @@ -307917,24 +279020,24 @@ module \main$22 sync always update \ctr_zero_bo1 $0\ctr_zero_bo1[0:0] end - connect \$12 $eq$libresoc.v:148848$7372_Y - connect \$14 $or$libresoc.v:148849$7373_Y - connect \$17 $add$libresoc.v:148850$7374_Y - connect \$19 $eq$libresoc.v:148851$7375_Y - connect \$21 $or$libresoc.v:148852$7376_Y - connect \$23 $eq$libresoc.v:148853$7377_Y - connect \$25 $eq$libresoc.v:148854$7378_Y - connect \$27 $eq$libresoc.v:148855$7379_Y - connect \$29 $not$libresoc.v:148856$7380_Y - connect \$31 $and$libresoc.v:148857$7381_Y - connect \$33 $and$libresoc.v:148858$7382_Y - connect \$36 $sub$libresoc.v:148859$7383_Y - connect \$38 $pos$libresoc.v:148860$7385_Y - connect \$40 $reduce_or$libresoc.v:148861$7386_Y - connect \$42 $xor$libresoc.v:148862$7387_Y - connect \$44 $not$libresoc.v:148863$7388_Y - connect \$46 $and$libresoc.v:148864$7389_Y - connect \$49 $add$libresoc.v:148865$7390_Y + connect \$12 $eq$libresoc.v:149800$7356_Y + connect \$14 $or$libresoc.v:149801$7357_Y + connect \$17 $add$libresoc.v:149802$7358_Y + connect \$19 $eq$libresoc.v:149803$7359_Y + connect \$21 $or$libresoc.v:149804$7360_Y + connect \$23 $eq$libresoc.v:149805$7361_Y + connect \$25 $eq$libresoc.v:149806$7362_Y + connect \$27 $eq$libresoc.v:149807$7363_Y + connect \$29 $not$libresoc.v:149808$7364_Y + connect \$31 $and$libresoc.v:149809$7365_Y + connect \$33 $and$libresoc.v:149810$7366_Y + connect \$36 $sub$libresoc.v:149811$7367_Y + connect \$38 $pos$libresoc.v:149812$7369_Y + connect \$40 $reduce_or$libresoc.v:149813$7370_Y + connect \$42 $xor$libresoc.v:149814$7371_Y + connect \$44 $not$libresoc.v:149815$7372_Y + connect \$46 $and$libresoc.v:149816$7373_Y + connect \$49 $add$libresoc.v:149817$7374_Y connect \$16 \$17 connect \$35 \$36 connect \$48 \$49 @@ -307945,279 +279048,279 @@ module \main$22 connect \bi \br_op__insn [17:16] connect \bo \br_op__insn [25:21] end -attribute \src "libresoc.v:149084.1-150034.10" +attribute \src "libresoc.v:150040.1-150990.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.main" attribute \generator "nMigen" module \main$38 - attribute \src "libresoc.v:149999.3-150010.6" + attribute \src "libresoc.v:150955.3-150966.6" wire width 64 $0\a[63:0] - attribute \src "libresoc.v:149497.3-149508.6" + attribute \src "libresoc.v:150453.3-150464.6" wire width 64 $0\a_s[63:0] - attribute \src "libresoc.v:150011.3-150022.6" + attribute \src "libresoc.v:150967.3-150978.6" wire width 64 $0\b[63:0] - attribute \src "libresoc.v:149780.3-149791.6" + attribute \src "libresoc.v:150736.3-150747.6" wire width 64 $0\b_s[63:0] - attribute \src "libresoc.v:149573.3-149604.6" - wire width 64 $0\fast1$11[63:0]$7454 - attribute \src "libresoc.v:149605.3-149636.6" + attribute \src "libresoc.v:150529.3-150560.6" + wire width 64 $0\fast1$11[63:0]$7438 + attribute \src "libresoc.v:150561.3-150592.6" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:149637.3-149719.6" - wire width 64 $0\fast2$12[63:0]$7459 - attribute \src "libresoc.v:149720.3-149751.6" + attribute \src "libresoc.v:150593.3-150675.6" + wire width 64 $0\fast2$12[63:0]$7443 + attribute \src "libresoc.v:150676.3-150707.6" wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:149085.7-149085.20" + attribute \src "libresoc.v:150041.7-150041.20" wire $0\initial[0:0] - attribute \src "libresoc.v:149792.3-149960.6" + attribute \src "libresoc.v:150748.3-150916.6" wire width 64 $0\msr[63:0] - attribute \src "libresoc.v:149792.3-149960.6" + attribute \src "libresoc.v:150748.3-150916.6" wire $0\msr_ok[0:0] - attribute \src "libresoc.v:149509.3-149540.6" + attribute \src "libresoc.v:150465.3-150496.6" wire width 64 $0\nia[63:0] - attribute \src "libresoc.v:149541.3-149572.6" + attribute \src "libresoc.v:150497.3-150528.6" wire $0\nia_ok[0:0] - attribute \src "libresoc.v:149961.3-149979.6" + attribute \src "libresoc.v:150917.3-150935.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:149980.3-149998.6" + attribute \src "libresoc.v:150936.3-150954.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:149752.3-149779.6" - wire $0\trapexc_$signal$60[0:0]$7473 - attribute \src "libresoc.v:149752.3-149779.6" - wire $0\trapexc_$signal$61[0:0]$7474 - attribute \src "libresoc.v:149752.3-149779.6" - wire $0\trapexc_$signal$62[0:0]$7475 - attribute \src "libresoc.v:149752.3-149779.6" - wire $0\trapexc_$signal$67[0:0]$7476 - attribute \src "libresoc.v:149752.3-149779.6" - wire $0\trapexc_$signal$68[0:0]$7477 - attribute \src "libresoc.v:149752.3-149779.6" - wire $0\trapexc_$signal$69[0:0]$7478 - attribute \src "libresoc.v:149752.3-149779.6" - wire $0\trapexc_$signal$70[0:0]$7479 - attribute \src "libresoc.v:149752.3-149779.6" - wire $0\trapexc_$signal[0:0]$7472 - attribute \src "libresoc.v:149637.3-149719.6" - wire $10\fast2$12[19:19]$7469 - attribute \src "libresoc.v:149792.3-149960.6" + attribute \src "libresoc.v:150708.3-150735.6" + wire $0\trapexc_$signal$60[0:0]$7457 + attribute \src "libresoc.v:150708.3-150735.6" + wire $0\trapexc_$signal$61[0:0]$7458 + attribute \src "libresoc.v:150708.3-150735.6" + wire $0\trapexc_$signal$62[0:0]$7459 + attribute \src "libresoc.v:150708.3-150735.6" + wire $0\trapexc_$signal$67[0:0]$7460 + attribute \src "libresoc.v:150708.3-150735.6" + wire $0\trapexc_$signal$68[0:0]$7461 + attribute \src "libresoc.v:150708.3-150735.6" + wire $0\trapexc_$signal$69[0:0]$7462 + attribute \src "libresoc.v:150708.3-150735.6" + wire $0\trapexc_$signal$70[0:0]$7463 + attribute \src "libresoc.v:150708.3-150735.6" + wire $0\trapexc_$signal[0:0]$7456 + attribute \src "libresoc.v:150593.3-150675.6" + wire $10\fast2$12[19:19]$7453 + attribute \src "libresoc.v:150748.3-150916.6" wire width 2 $10\msr[5:4] - attribute \src "libresoc.v:149792.3-149960.6" + attribute \src "libresoc.v:150748.3-150916.6" wire $11\msr[15:15] - attribute \src "libresoc.v:149792.3-149960.6" + attribute \src "libresoc.v:150748.3-150916.6" wire $12\msr[12:12] - attribute \src "libresoc.v:149792.3-149960.6" + attribute \src "libresoc.v:150748.3-150916.6" wire $13\msr[60:60] - attribute \src "libresoc.v:149792.3-149960.6" + attribute \src "libresoc.v:150748.3-150916.6" wire $14\msr[12:12] - attribute \src "libresoc.v:149792.3-149960.6" + attribute \src "libresoc.v:150748.3-150916.6" wire $15\msr[12:12] - attribute \src "libresoc.v:149792.3-149960.6" + attribute \src "libresoc.v:150748.3-150916.6" wire width 2 $16\msr[5:4] - attribute \src "libresoc.v:149792.3-149960.6" + attribute \src "libresoc.v:150748.3-150916.6" wire $17\msr[15:15] - attribute \src "libresoc.v:149792.3-149960.6" + attribute \src "libresoc.v:150748.3-150916.6" wire width 3 $18\msr[34:32] - attribute \src "libresoc.v:149999.3-150010.6" + attribute \src "libresoc.v:150955.3-150966.6" wire width 64 $1\a[63:0] - attribute \src "libresoc.v:149497.3-149508.6" + attribute \src "libresoc.v:150453.3-150464.6" wire width 64 $1\a_s[63:0] - attribute \src "libresoc.v:150011.3-150022.6" + attribute \src "libresoc.v:150967.3-150978.6" wire width 64 $1\b[63:0] - attribute \src "libresoc.v:149780.3-149791.6" + attribute \src "libresoc.v:150736.3-150747.6" wire width 64 $1\b_s[63:0] - attribute \src "libresoc.v:149573.3-149604.6" - wire width 64 $1\fast1$11[63:0]$7455 - attribute \src "libresoc.v:149605.3-149636.6" + attribute \src "libresoc.v:150529.3-150560.6" + wire width 64 $1\fast1$11[63:0]$7439 + attribute \src "libresoc.v:150561.3-150592.6" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:149637.3-149719.6" - wire width 64 $1\fast2$12[63:0]$7460 - attribute \src "libresoc.v:149720.3-149751.6" + attribute \src "libresoc.v:150593.3-150675.6" + wire width 64 $1\fast2$12[63:0]$7444 + attribute \src "libresoc.v:150676.3-150707.6" wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:149792.3-149960.6" + attribute \src "libresoc.v:150748.3-150916.6" wire width 64 $1\msr[63:0] - attribute \src "libresoc.v:149792.3-149960.6" + attribute \src "libresoc.v:150748.3-150916.6" wire $1\msr_ok[0:0] - attribute \src "libresoc.v:149509.3-149540.6" + attribute \src "libresoc.v:150465.3-150496.6" wire width 64 $1\nia[63:0] - attribute \src "libresoc.v:149541.3-149572.6" + attribute \src "libresoc.v:150497.3-150528.6" wire $1\nia_ok[0:0] - attribute \src "libresoc.v:149961.3-149979.6" + attribute \src "libresoc.v:150917.3-150935.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:149980.3-149998.6" + attribute \src "libresoc.v:150936.3-150954.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:149752.3-149779.6" - wire $1\trapexc_$signal$60[0:0]$7481 - attribute \src "libresoc.v:149752.3-149779.6" - wire $1\trapexc_$signal$61[0:0]$7482 - attribute \src "libresoc.v:149752.3-149779.6" - wire $1\trapexc_$signal$62[0:0]$7483 - attribute \src "libresoc.v:149752.3-149779.6" - wire $1\trapexc_$signal$67[0:0]$7484 - attribute \src "libresoc.v:149752.3-149779.6" - wire $1\trapexc_$signal$68[0:0]$7485 - attribute \src "libresoc.v:149752.3-149779.6" - wire $1\trapexc_$signal$69[0:0]$7486 - attribute \src "libresoc.v:149752.3-149779.6" - wire $1\trapexc_$signal$70[0:0]$7487 - attribute \src "libresoc.v:149752.3-149779.6" - wire $1\trapexc_$signal[0:0]$7480 - attribute \src "libresoc.v:149573.3-149604.6" - wire width 64 $2\fast1$11[63:0]$7456 - attribute \src "libresoc.v:149605.3-149636.6" + attribute \src "libresoc.v:150708.3-150735.6" + wire $1\trapexc_$signal$60[0:0]$7465 + attribute \src "libresoc.v:150708.3-150735.6" + wire $1\trapexc_$signal$61[0:0]$7466 + attribute \src "libresoc.v:150708.3-150735.6" + wire $1\trapexc_$signal$62[0:0]$7467 + attribute \src "libresoc.v:150708.3-150735.6" + wire $1\trapexc_$signal$67[0:0]$7468 + attribute \src "libresoc.v:150708.3-150735.6" + wire $1\trapexc_$signal$68[0:0]$7469 + attribute \src "libresoc.v:150708.3-150735.6" + wire $1\trapexc_$signal$69[0:0]$7470 + attribute \src "libresoc.v:150708.3-150735.6" + wire $1\trapexc_$signal$70[0:0]$7471 + attribute \src "libresoc.v:150708.3-150735.6" + wire $1\trapexc_$signal[0:0]$7464 + attribute \src "libresoc.v:150529.3-150560.6" + wire width 64 $2\fast1$11[63:0]$7440 + attribute \src "libresoc.v:150561.3-150592.6" wire $2\fast1_ok[0:0] - attribute \src "libresoc.v:149637.3-149719.6" - wire width 64 $2\fast2$12[63:0]$7461 - attribute \src "libresoc.v:149720.3-149751.6" + attribute \src "libresoc.v:150593.3-150675.6" + wire width 64 $2\fast2$12[63:0]$7445 + attribute \src "libresoc.v:150676.3-150707.6" wire $2\fast2_ok[0:0] - attribute \src "libresoc.v:149792.3-149960.6" + attribute \src "libresoc.v:150748.3-150916.6" wire width 64 $2\msr[63:0] - attribute \src "libresoc.v:149792.3-149960.6" + attribute \src "libresoc.v:150748.3-150916.6" wire $2\msr_ok[0:0] - attribute \src "libresoc.v:149509.3-149540.6" + attribute \src "libresoc.v:150465.3-150496.6" wire width 64 $2\nia[63:0] - attribute \src "libresoc.v:149541.3-149572.6" + attribute \src "libresoc.v:150497.3-150528.6" wire $2\nia_ok[0:0] - attribute \src "libresoc.v:149752.3-149779.6" - wire $2\trapexc_$signal$60[0:0]$7489 - attribute \src "libresoc.v:149752.3-149779.6" - wire $2\trapexc_$signal$61[0:0]$7490 - attribute \src "libresoc.v:149752.3-149779.6" - wire $2\trapexc_$signal$62[0:0]$7491 - attribute \src "libresoc.v:149752.3-149779.6" - wire $2\trapexc_$signal$67[0:0]$7492 - attribute \src "libresoc.v:149752.3-149779.6" - wire $2\trapexc_$signal$68[0:0]$7493 - attribute \src "libresoc.v:149752.3-149779.6" - wire $2\trapexc_$signal$69[0:0]$7494 - attribute \src "libresoc.v:149752.3-149779.6" - wire $2\trapexc_$signal$70[0:0]$7495 - attribute \src "libresoc.v:149752.3-149779.6" - wire $2\trapexc_$signal[0:0]$7488 - attribute \src "libresoc.v:149637.3-149719.6" - wire $3\fast2$12[17:17]$7462 - attribute \src "libresoc.v:149792.3-149960.6" + attribute \src "libresoc.v:150708.3-150735.6" + wire $2\trapexc_$signal$60[0:0]$7473 + attribute \src "libresoc.v:150708.3-150735.6" + wire $2\trapexc_$signal$61[0:0]$7474 + attribute \src "libresoc.v:150708.3-150735.6" + wire $2\trapexc_$signal$62[0:0]$7475 + attribute \src "libresoc.v:150708.3-150735.6" + wire $2\trapexc_$signal$67[0:0]$7476 + attribute \src "libresoc.v:150708.3-150735.6" + wire $2\trapexc_$signal$68[0:0]$7477 + attribute \src "libresoc.v:150708.3-150735.6" + wire $2\trapexc_$signal$69[0:0]$7478 + attribute \src "libresoc.v:150708.3-150735.6" + wire $2\trapexc_$signal$70[0:0]$7479 + attribute \src "libresoc.v:150708.3-150735.6" + wire $2\trapexc_$signal[0:0]$7472 + attribute \src "libresoc.v:150593.3-150675.6" + wire $3\fast2$12[17:17]$7446 + attribute \src "libresoc.v:150748.3-150916.6" wire width 11 $3\msr[11:1] - attribute \src "libresoc.v:149752.3-149779.6" - wire $3\trapexc_$signal$60[0:0]$7497 - attribute \src "libresoc.v:149752.3-149779.6" - wire $3\trapexc_$signal$61[0:0]$7498 - attribute \src "libresoc.v:149752.3-149779.6" - wire $3\trapexc_$signal$62[0:0]$7499 - attribute \src "libresoc.v:149752.3-149779.6" - wire $3\trapexc_$signal$67[0:0]$7500 - attribute \src "libresoc.v:149752.3-149779.6" - wire $3\trapexc_$signal$68[0:0]$7501 - attribute \src "libresoc.v:149752.3-149779.6" - wire $3\trapexc_$signal$69[0:0]$7502 - attribute \src "libresoc.v:149752.3-149779.6" - wire $3\trapexc_$signal$70[0:0]$7503 - attribute \src "libresoc.v:149752.3-149779.6" - wire $3\trapexc_$signal[0:0]$7496 - attribute \src "libresoc.v:149637.3-149719.6" - wire $4\fast2$12[18:18]$7463 - attribute \src "libresoc.v:149792.3-149960.6" + attribute \src "libresoc.v:150708.3-150735.6" + wire $3\trapexc_$signal$60[0:0]$7481 + attribute \src "libresoc.v:150708.3-150735.6" + wire $3\trapexc_$signal$61[0:0]$7482 + attribute \src "libresoc.v:150708.3-150735.6" + wire $3\trapexc_$signal$62[0:0]$7483 + attribute \src "libresoc.v:150708.3-150735.6" + wire $3\trapexc_$signal$67[0:0]$7484 + attribute \src "libresoc.v:150708.3-150735.6" + wire $3\trapexc_$signal$68[0:0]$7485 + attribute \src "libresoc.v:150708.3-150735.6" + wire $3\trapexc_$signal$69[0:0]$7486 + attribute \src "libresoc.v:150708.3-150735.6" + wire $3\trapexc_$signal$70[0:0]$7487 + attribute \src "libresoc.v:150708.3-150735.6" + wire $3\trapexc_$signal[0:0]$7480 + attribute \src "libresoc.v:150593.3-150675.6" + wire $4\fast2$12[18:18]$7447 + attribute \src "libresoc.v:150748.3-150916.6" wire width 47 $4\msr[59:13] - attribute \src "libresoc.v:149637.3-149719.6" - wire $5\fast2$12[20:20]$7464 - attribute \src "libresoc.v:149792.3-149960.6" + attribute \src "libresoc.v:150593.3-150675.6" + wire $5\fast2$12[20:20]$7448 + attribute \src "libresoc.v:150748.3-150916.6" wire width 3 $5\msr[63:61] - attribute \src "libresoc.v:149637.3-149719.6" - wire $6\fast2$12[16:16]$7465 - attribute \src "libresoc.v:149792.3-149960.6" + attribute \src "libresoc.v:150593.3-150675.6" + wire $6\fast2$12[16:16]$7449 + attribute \src "libresoc.v:150748.3-150916.6" wire width 11 $6\msr[11:1] - attribute \src "libresoc.v:149637.3-149719.6" - wire width 2 $7\fast2$12[19:18]$7466 - attribute \src "libresoc.v:149792.3-149960.6" + attribute \src "libresoc.v:150593.3-150675.6" + wire width 2 $7\fast2$12[19:18]$7450 + attribute \src "libresoc.v:150748.3-150916.6" wire width 47 $7\msr[59:13] - attribute \src "libresoc.v:149637.3-149719.6" - wire $8\fast2$12[28:28]$7467 - attribute \src "libresoc.v:149792.3-149960.6" + attribute \src "libresoc.v:150593.3-150675.6" + wire $8\fast2$12[28:28]$7451 + attribute \src "libresoc.v:150748.3-150916.6" wire width 3 $8\msr[63:61] - attribute \src "libresoc.v:149637.3-149719.6" - wire $9\fast2$12[30:30]$7468 - attribute \src "libresoc.v:149792.3-149960.6" + attribute \src "libresoc.v:150593.3-150675.6" + wire $9\fast2$12[30:30]$7452 + attribute \src "libresoc.v:150748.3-150916.6" wire width 3 $9\msr[34:32] - attribute \src "libresoc.v:149473.18-149473.113" - wire width 65 $add$libresoc.v:149473$7425_Y - attribute \src "libresoc.v:149467.18-149467.108" - wire width 5 $and$libresoc.v:149467$7418_Y - attribute \src "libresoc.v:149475.18-149475.118" - wire width 8 $and$libresoc.v:149475$7427_Y - attribute \src "libresoc.v:149477.18-149477.118" - wire width 8 $and$libresoc.v:149477$7429_Y - attribute \src "libresoc.v:149479.18-149479.118" - wire width 8 $and$libresoc.v:149479$7431_Y - attribute \src "libresoc.v:149481.18-149481.119" - wire width 8 $and$libresoc.v:149481$7433_Y - attribute \src "libresoc.v:149483.18-149483.119" - wire width 8 $and$libresoc.v:149483$7435_Y - attribute \src "libresoc.v:149485.18-149485.119" - wire width 8 $and$libresoc.v:149485$7437_Y - attribute \src "libresoc.v:149491.18-149491.106" - wire $and$libresoc.v:149491$7444_Y - attribute \src "libresoc.v:149496.18-149496.106" - wire $and$libresoc.v:149496$7449_Y - attribute \src "libresoc.v:149466.18-149466.100" - wire $eq$libresoc.v:149466$7417_Y - attribute \src "libresoc.v:149474.18-149474.119" - wire $eq$libresoc.v:149474$7426_Y - attribute \src "libresoc.v:149488.18-149488.121" - wire $eq$libresoc.v:149488$7441_Y - attribute \src "libresoc.v:149489.18-149489.121" - wire $eq$libresoc.v:149489$7442_Y - attribute \src "libresoc.v:149490.18-149490.111" - wire $eq$libresoc.v:149490$7443_Y - attribute \src "libresoc.v:149494.18-149494.121" - wire $eq$libresoc.v:149494$7447_Y - attribute \src "libresoc.v:149495.18-149495.114" - wire $eq$libresoc.v:149495$7448_Y - attribute \src "libresoc.v:149460.18-149460.95" - wire width 64 $extend$libresoc.v:149460$7409_Y - attribute \src "libresoc.v:149461.18-149461.95" - wire width 64 $extend$libresoc.v:149461$7411_Y - attribute \src "libresoc.v:149472.18-149472.100" - wire width 64 $extend$libresoc.v:149472$7423_Y - attribute \src "libresoc.v:149487.18-149487.109" - wire width 65 $extend$libresoc.v:149487$7439_Y - attribute \src "libresoc.v:149463.18-149463.121" - wire $gt$libresoc.v:149463$7414_Y - attribute \src "libresoc.v:149465.18-149465.99" - wire $gt$libresoc.v:149465$7416_Y - attribute \src "libresoc.v:149462.18-149462.121" - wire $lt$libresoc.v:149462$7413_Y - attribute \src "libresoc.v:149464.18-149464.99" - wire $lt$libresoc.v:149464$7415_Y - attribute \src "libresoc.v:149492.18-149492.112" - wire $not$libresoc.v:149492$7445_Y - attribute \src "libresoc.v:149493.18-149493.112" - wire $not$libresoc.v:149493$7446_Y - attribute \src "libresoc.v:149470.18-149470.106" - wire $or$libresoc.v:149470$7421_Y - attribute \src "libresoc.v:149460.18-149460.95" - wire width 64 $pos$libresoc.v:149460$7410_Y - attribute \src "libresoc.v:149461.18-149461.95" - wire width 64 $pos$libresoc.v:149461$7412_Y - attribute \src "libresoc.v:149472.18-149472.100" - wire width 64 $pos$libresoc.v:149472$7424_Y - attribute \src "libresoc.v:149487.18-149487.109" - wire width 65 $pos$libresoc.v:149487$7440_Y - attribute \src "libresoc.v:149468.18-149468.100" - wire $reduce_or$libresoc.v:149468$7419_Y - attribute \src "libresoc.v:149469.18-149469.113" - wire $reduce_or$libresoc.v:149469$7420_Y - attribute \src "libresoc.v:149476.18-149476.91" - wire $reduce_or$libresoc.v:149476$7428_Y - attribute \src "libresoc.v:149478.18-149478.91" - wire $reduce_or$libresoc.v:149478$7430_Y - attribute \src "libresoc.v:149480.18-149480.91" - wire $reduce_or$libresoc.v:149480$7432_Y - attribute \src "libresoc.v:149482.18-149482.91" - wire $reduce_or$libresoc.v:149482$7434_Y - attribute \src "libresoc.v:149484.18-149484.91" - wire $reduce_or$libresoc.v:149484$7436_Y - attribute \src "libresoc.v:149486.18-149486.91" - wire $reduce_or$libresoc.v:149486$7438_Y - attribute \src "libresoc.v:149471.18-149471.120" - wire width 20 $sshl$libresoc.v:149471$7422_Y + attribute \src "libresoc.v:150429.18-150429.113" + wire width 65 $add$libresoc.v:150429$7409_Y + attribute \src "libresoc.v:150423.18-150423.108" + wire width 5 $and$libresoc.v:150423$7402_Y + attribute \src "libresoc.v:150431.18-150431.118" + wire width 8 $and$libresoc.v:150431$7411_Y + attribute \src "libresoc.v:150433.18-150433.118" + wire width 8 $and$libresoc.v:150433$7413_Y + attribute \src "libresoc.v:150435.18-150435.118" + wire width 8 $and$libresoc.v:150435$7415_Y + attribute \src "libresoc.v:150437.18-150437.119" + wire width 8 $and$libresoc.v:150437$7417_Y + attribute \src "libresoc.v:150439.18-150439.119" + wire width 8 $and$libresoc.v:150439$7419_Y + attribute \src "libresoc.v:150441.18-150441.119" + wire width 8 $and$libresoc.v:150441$7421_Y + attribute \src "libresoc.v:150447.18-150447.106" + wire $and$libresoc.v:150447$7428_Y + attribute \src "libresoc.v:150452.18-150452.106" + wire $and$libresoc.v:150452$7433_Y + attribute \src "libresoc.v:150422.18-150422.100" + wire $eq$libresoc.v:150422$7401_Y + attribute \src "libresoc.v:150430.18-150430.119" + wire $eq$libresoc.v:150430$7410_Y + attribute \src "libresoc.v:150444.18-150444.121" + wire $eq$libresoc.v:150444$7425_Y + attribute \src "libresoc.v:150445.18-150445.121" + wire $eq$libresoc.v:150445$7426_Y + attribute \src "libresoc.v:150446.18-150446.111" + wire $eq$libresoc.v:150446$7427_Y + attribute \src "libresoc.v:150450.18-150450.121" + wire $eq$libresoc.v:150450$7431_Y + attribute \src "libresoc.v:150451.18-150451.114" + wire $eq$libresoc.v:150451$7432_Y + attribute \src "libresoc.v:150416.18-150416.95" + wire width 64 $extend$libresoc.v:150416$7393_Y + attribute \src "libresoc.v:150417.18-150417.95" + wire width 64 $extend$libresoc.v:150417$7395_Y + attribute \src "libresoc.v:150428.18-150428.100" + wire width 64 $extend$libresoc.v:150428$7407_Y + attribute \src "libresoc.v:150443.18-150443.109" + wire width 65 $extend$libresoc.v:150443$7423_Y + attribute \src "libresoc.v:150419.18-150419.121" + wire $gt$libresoc.v:150419$7398_Y + attribute \src "libresoc.v:150421.18-150421.99" + wire $gt$libresoc.v:150421$7400_Y + attribute \src "libresoc.v:150418.18-150418.121" + wire $lt$libresoc.v:150418$7397_Y + attribute \src "libresoc.v:150420.18-150420.99" + wire $lt$libresoc.v:150420$7399_Y + attribute \src "libresoc.v:150448.18-150448.112" + wire $not$libresoc.v:150448$7429_Y + attribute \src "libresoc.v:150449.18-150449.112" + wire $not$libresoc.v:150449$7430_Y + attribute \src "libresoc.v:150426.18-150426.106" + wire $or$libresoc.v:150426$7405_Y + attribute \src "libresoc.v:150416.18-150416.95" + wire width 64 $pos$libresoc.v:150416$7394_Y + attribute \src "libresoc.v:150417.18-150417.95" + wire width 64 $pos$libresoc.v:150417$7396_Y + attribute \src "libresoc.v:150428.18-150428.100" + wire width 64 $pos$libresoc.v:150428$7408_Y + attribute \src "libresoc.v:150443.18-150443.109" + wire width 65 $pos$libresoc.v:150443$7424_Y + attribute \src "libresoc.v:150424.18-150424.100" + wire $reduce_or$libresoc.v:150424$7403_Y + attribute \src "libresoc.v:150425.18-150425.113" + wire $reduce_or$libresoc.v:150425$7404_Y + attribute \src "libresoc.v:150432.18-150432.91" + wire $reduce_or$libresoc.v:150432$7412_Y + attribute \src "libresoc.v:150434.18-150434.91" + wire $reduce_or$libresoc.v:150434$7414_Y + attribute \src "libresoc.v:150436.18-150436.91" + wire $reduce_or$libresoc.v:150436$7416_Y + attribute \src "libresoc.v:150438.18-150438.91" + wire $reduce_or$libresoc.v:150438$7418_Y + attribute \src "libresoc.v:150440.18-150440.91" + wire $reduce_or$libresoc.v:150440$7420_Y + attribute \src "libresoc.v:150442.18-150442.91" + wire $reduce_or$libresoc.v:150442$7422_Y + attribute \src "libresoc.v:150427.18-150427.120" + wire width 20 $sshl$libresoc.v:150427$7406_Y attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" wire width 64 \$13 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" @@ -308320,7 +279423,7 @@ module \main$38 wire \gt_s attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:160" wire \gt_u - attribute \src "libresoc.v:149085.7-149085.15" + attribute \src "libresoc.v:150041.7-150041.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:157" wire \lt_s @@ -308585,7 +279688,7 @@ module \main$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/mem_types.py:16" wire \trapexc_$signal$70 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:315" - cell $add $add$libresoc.v:149473$7425 + cell $add $add$libresoc.v:150429$7409 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -308593,10 +279696,10 @@ module \main$38 parameter \Y_WIDTH 65 connect \A \trap_op__cia connect \B 3'100 - connect \Y $add$libresoc.v:149473$7425_Y + connect \Y $add$libresoc.v:150429$7409_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" - cell $and $and$libresoc.v:149467$7418 + cell $and $and$libresoc.v:150423$7402 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -308604,10 +279707,10 @@ module \main$38 parameter \Y_WIDTH 5 connect \A \trap_bits connect \B \to - connect \Y $and$libresoc.v:149467$7418_Y + connect \Y $and$libresoc.v:150423$7402_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" - cell $and $and$libresoc.v:149475$7427 + cell $and $and$libresoc.v:150431$7411 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308615,10 +279718,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 2'10 - connect \Y $and$libresoc.v:149475$7427_Y + connect \Y $and$libresoc.v:150431$7411_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" - cell $and $and$libresoc.v:149477$7429 + cell $and $and$libresoc.v:150433$7413 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308626,10 +279729,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 1'1 - connect \Y $and$libresoc.v:149477$7429_Y + connect \Y $and$libresoc.v:150433$7413_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" - cell $and $and$libresoc.v:149479$7431 + cell $and $and$libresoc.v:150435$7415 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308637,10 +279740,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 4'1000 - connect \Y $and$libresoc.v:149479$7431_Y + connect \Y $and$libresoc.v:150435$7415_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" - cell $and $and$libresoc.v:149481$7433 + cell $and $and$libresoc.v:150437$7417 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308648,10 +279751,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 7'1000000 - connect \Y $and$libresoc.v:149481$7433_Y + connect \Y $and$libresoc.v:150437$7417_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213" - cell $and $and$libresoc.v:149483$7435 + cell $and $and$libresoc.v:150439$7419 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308659,10 +279762,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 8'10000000 - connect \Y $and$libresoc.v:149483$7435_Y + connect \Y $and$libresoc.v:150439$7419_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" - cell $and $and$libresoc.v:149485$7437 + cell $and $and$libresoc.v:150441$7421 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308670,10 +279773,10 @@ module \main$38 parameter \Y_WIDTH 8 connect \A \trap_op__traptype connect \B 7'1000000 - connect \Y $and$libresoc.v:149485$7437_Y + connect \Y $and$libresoc.v:150441$7421_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" - cell $and $and$libresoc.v:149491$7444 + cell $and $and$libresoc.v:150447$7428 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308681,10 +279784,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \$79 connect \B \$81 - connect \Y $and$libresoc.v:149491$7444_Y + connect \Y $and$libresoc.v:150447$7428_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" - cell $and $and$libresoc.v:149496$7449 + cell $and $and$libresoc.v:150452$7433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308692,10 +279795,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \$89 connect \B \$91 - connect \Y $and$libresoc.v:149496$7449_Y + connect \Y $and$libresoc.v:150452$7433_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167" - cell $eq $eq$libresoc.v:149466$7417 + cell $eq $eq$libresoc.v:150422$7401 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -308703,10 +279806,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \a connect \B \b - connect \Y $eq$libresoc.v:149466$7417_Y + connect \Y $eq$libresoc.v:150422$7401_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190" - cell $eq $eq$libresoc.v:149474$7426 + cell $eq $eq$libresoc.v:150430$7410 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -308714,10 +279817,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \trap_op__traptype connect \B 1'0 - connect \Y $eq$libresoc.v:149474$7426_Y + connect \Y $eq$libresoc.v:150430$7410_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:234" - cell $eq $eq$libresoc.v:149488$7441 + cell $eq $eq$libresoc.v:150444$7425 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -308725,10 +279828,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \trap_op__insn_type connect \B 7'1001000 - connect \Y $eq$libresoc.v:149488$7441_Y + connect \Y $eq$libresoc.v:150444$7425_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:240" - cell $eq $eq$libresoc.v:149489$7442 + cell $eq $eq$libresoc.v:150445$7426 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -308736,10 +279839,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \trap_op__msr [34:32] connect \B 3'010 - connect \Y $eq$libresoc.v:149489$7442_Y + connect \Y $eq$libresoc.v:150445$7426_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:241" - cell $eq $eq$libresoc.v:149490$7443 + cell $eq $eq$libresoc.v:150446$7427 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -308747,10 +279850,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \ra [34:32] connect \B 3'000 - connect \Y $eq$libresoc.v:149490$7443_Y + connect \Y $eq$libresoc.v:150446$7427_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" - cell $eq $eq$libresoc.v:149494$7447 + cell $eq $eq$libresoc.v:150450$7431 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -308758,10 +279861,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \trap_op__msr [34:32] connect \B 3'010 - connect \Y $eq$libresoc.v:149494$7447_Y + connect \Y $eq$libresoc.v:150450$7431_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:296" - cell $eq $eq$libresoc.v:149495$7448 + cell $eq $eq$libresoc.v:150451$7432 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -308769,42 +279872,42 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \fast2 [34:32] connect \B 3'000 - connect \Y $eq$libresoc.v:149495$7448_Y + connect \Y $eq$libresoc.v:150451$7432_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:149460$7409 + cell $pos $extend$libresoc.v:150416$7393 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \ra [31:0] - connect \Y $extend$libresoc.v:149460$7409_Y + connect \Y $extend$libresoc.v:150416$7393_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:149461$7411 + cell $pos $extend$libresoc.v:150417$7395 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \rb [31:0] - connect \Y $extend$libresoc.v:149461$7411_Y + connect \Y $extend$libresoc.v:150417$7395_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" - cell $pos $extend$libresoc.v:149472$7423 + cell $pos $extend$libresoc.v:150428$7407 parameter \A_SIGNED 0 parameter \A_WIDTH 20 parameter \Y_WIDTH 64 connect \A \$36 - connect \Y $extend$libresoc.v:149472$7423_Y + connect \Y $extend$libresoc.v:150428$7407_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $extend$libresoc.v:149487$7439 + cell $pos $extend$libresoc.v:150443$7423 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \trap_op__msr - connect \Y $extend$libresoc.v:149487$7439_Y + connect \Y $extend$libresoc.v:150443$7423_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164" - cell $gt $gt$libresoc.v:149463$7414 + cell $gt $gt$libresoc.v:150419$7398 parameter \A_SIGNED 1 parameter \A_WIDTH 64 parameter \B_SIGNED 1 @@ -308812,10 +279915,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \a_s connect \B \b_s - connect \Y $gt$libresoc.v:149463$7414_Y + connect \Y $gt$libresoc.v:150419$7398_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:166" - cell $gt $gt$libresoc.v:149465$7416 + cell $gt $gt$libresoc.v:150421$7400 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -308823,10 +279926,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \a connect \B \b - connect \Y $gt$libresoc.v:149465$7416_Y + connect \Y $gt$libresoc.v:150421$7400_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163" - cell $lt $lt$libresoc.v:149462$7413 + cell $lt $lt$libresoc.v:150418$7397 parameter \A_SIGNED 1 parameter \A_WIDTH 64 parameter \B_SIGNED 1 @@ -308834,10 +279937,10 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \a_s connect \B \b_s - connect \Y $lt$libresoc.v:149462$7413_Y + connect \Y $lt$libresoc.v:150418$7397_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:165" - cell $lt $lt$libresoc.v:149464$7415 + cell $lt $lt$libresoc.v:150420$7399 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -308845,26 +279948,26 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \a connect \B \b - connect \Y $lt$libresoc.v:149464$7415_Y + connect \Y $lt$libresoc.v:150420$7399_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" - cell $not $not$libresoc.v:149492$7445 + cell $not $not$libresoc.v:150448$7429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \trap_op__msr [60] - connect \Y $not$libresoc.v:149492$7445_Y + connect \Y $not$libresoc.v:150448$7429_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:282" - cell $not $not$libresoc.v:149493$7446 + cell $not $not$libresoc.v:150449$7430 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \trap_op__insn [9] - connect \Y $not$libresoc.v:149493$7446_Y + connect \Y $not$libresoc.v:150449$7430_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" - cell $or $or$libresoc.v:149470$7421 + cell $or $or$libresoc.v:150426$7405 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -308872,106 +279975,106 @@ module \main$38 parameter \Y_WIDTH 1 connect \A \$27 connect \B \$31 - connect \Y $or$libresoc.v:149470$7421_Y + connect \Y $or$libresoc.v:150426$7405_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:149460$7410 + cell $pos $pos$libresoc.v:150416$7394 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:149460$7409_Y - connect \Y $pos$libresoc.v:149460$7410_Y + connect \A $extend$libresoc.v:150416$7393_Y + connect \Y $pos$libresoc.v:150416$7394_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:149461$7412 + cell $pos $pos$libresoc.v:150417$7396 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:149461$7411_Y - connect \Y $pos$libresoc.v:149461$7412_Y + connect \A $extend$libresoc.v:150417$7395_Y + connect \Y $pos$libresoc.v:150417$7396_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" - cell $pos $pos$libresoc.v:149472$7424 + cell $pos $pos$libresoc.v:150428$7408 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:149472$7423_Y - connect \Y $pos$libresoc.v:149472$7424_Y + connect \A $extend$libresoc.v:150428$7407_Y + connect \Y $pos$libresoc.v:150428$7408_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $pos$libresoc.v:149487$7440 + cell $pos $pos$libresoc.v:150443$7424 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:149487$7439_Y - connect \Y $pos$libresoc.v:149487$7440_Y + connect \A $extend$libresoc.v:150443$7423_Y + connect \Y $pos$libresoc.v:150443$7424_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" - cell $reduce_or $reduce_or$libresoc.v:149468$7419 + cell $reduce_or $reduce_or$libresoc.v:150424$7403 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $reduce_or$libresoc.v:149468$7419_Y + connect \Y $reduce_or$libresoc.v:150424$7403_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177" - cell $reduce_or $reduce_or$libresoc.v:149469$7420 + cell $reduce_or $reduce_or$libresoc.v:150425$7404 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \trap_op__traptype - connect \Y $reduce_or$libresoc.v:149469$7420_Y + connect \Y $reduce_or$libresoc.v:150425$7404_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:149476$7428 + cell $reduce_or $reduce_or$libresoc.v:150432$7412 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$45 - connect \Y $reduce_or$libresoc.v:149476$7428_Y + connect \Y $reduce_or$libresoc.v:150432$7412_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:149478$7430 + cell $reduce_or $reduce_or$libresoc.v:150434$7414 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$49 - connect \Y $reduce_or$libresoc.v:149478$7430_Y + connect \Y $reduce_or$libresoc.v:150434$7414_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:149480$7432 + cell $reduce_or $reduce_or$libresoc.v:150436$7416 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$53 - connect \Y $reduce_or$libresoc.v:149480$7432_Y + connect \Y $reduce_or$libresoc.v:150436$7416_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:149482$7434 + cell $reduce_or $reduce_or$libresoc.v:150438$7418 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$57 - connect \Y $reduce_or$libresoc.v:149482$7434_Y + connect \Y $reduce_or$libresoc.v:150438$7418_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:149484$7436 + cell $reduce_or $reduce_or$libresoc.v:150440$7420 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$64 - connect \Y $reduce_or$libresoc.v:149484$7436_Y + connect \Y $reduce_or$libresoc.v:150440$7420_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:149486$7438 + cell $reduce_or $reduce_or$libresoc.v:150442$7422 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \$72 - connect \Y $reduce_or$libresoc.v:149486$7438_Y + connect \Y $reduce_or$libresoc.v:150442$7422_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" - cell $sshl $sshl$libresoc.v:149471$7422 + cell $sshl $sshl$libresoc.v:150427$7406 parameter \A_SIGNED 0 parameter \A_WIDTH 13 parameter \B_SIGNED 0 @@ -308979,23 +280082,23 @@ module \main$38 parameter \Y_WIDTH 20 connect \A \trap_op__trapaddr connect \B 3'100 - connect \Y $sshl$libresoc.v:149471$7422_Y + connect \Y $sshl$libresoc.v:150427$7406_Y end - attribute \src "libresoc.v:149085.7-149085.20" - process $proc$libresoc.v:149085$7510 + attribute \src "libresoc.v:150041.7-150041.20" + process $proc$libresoc.v:150041$7494 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:149497.3-149508.6" - process $proc$libresoc.v:149497$7450 + attribute \src "libresoc.v:150453.3-150464.6" + process $proc$libresoc.v:150453$7434 assign { } { } assign $0\a_s[63:0] $1\a_s[63:0] - attribute \src "libresoc.v:149498.5-149498.29" + attribute \src "libresoc.v:150454.5-150454.29" switch \initial - attribute \src "libresoc.v:149498.9-149498.17" + attribute \src "libresoc.v:150454.9-150454.17" case 1'1 case end @@ -309013,14 +280116,14 @@ module \main$38 sync always update \a_s $0\a_s[63:0] end - attribute \src "libresoc.v:149509.3-149540.6" - process $proc$libresoc.v:149509$7451 + attribute \src "libresoc.v:150465.3-150496.6" + process $proc$libresoc.v:150465$7435 assign { } { } assign { } { } assign $0\nia[63:0] $1\nia[63:0] - attribute \src "libresoc.v:149510.5-149510.29" + attribute \src "libresoc.v:150466.5-150466.29" switch \initial - attribute \src "libresoc.v:149510.9-149510.17" + attribute \src "libresoc.v:150466.9-150466.17" case 1'1 case end @@ -309059,14 +280162,14 @@ module \main$38 sync always update \nia $0\nia[63:0] end - attribute \src "libresoc.v:149541.3-149572.6" - process $proc$libresoc.v:149541$7452 + attribute \src "libresoc.v:150497.3-150528.6" + process $proc$libresoc.v:150497$7436 assign { } { } assign { } { } assign $0\nia_ok[0:0] $1\nia_ok[0:0] - attribute \src "libresoc.v:149542.5-149542.29" + attribute \src "libresoc.v:150498.5-150498.29" switch \initial - attribute \src "libresoc.v:149542.9-149542.17" + attribute \src "libresoc.v:150498.9-150498.17" case 1'1 case end @@ -309105,14 +280208,14 @@ module \main$38 sync always update \nia_ok $0\nia_ok[0:0] end - attribute \src "libresoc.v:149573.3-149604.6" - process $proc$libresoc.v:149573$7453 + attribute \src "libresoc.v:150529.3-150560.6" + process $proc$libresoc.v:150529$7437 assign { } { } assign { } { } - assign $0\fast1$11[63:0]$7454 $1\fast1$11[63:0]$7455 - attribute \src "libresoc.v:149574.5-149574.29" + assign $0\fast1$11[63:0]$7438 $1\fast1$11[63:0]$7439 + attribute \src "libresoc.v:150530.5-150530.29" switch \initial - attribute \src "libresoc.v:149574.9-149574.17" + attribute \src "libresoc.v:150530.9-150530.17" case 1'1 case end @@ -309121,43 +280224,43 @@ module \main$38 attribute \src "libresoc.v:0.0-0.0" case 7'0111111 assign { } { } - assign $1\fast1$11[63:0]$7455 $2\fast1$11[63:0]$7456 + assign $1\fast1$11[63:0]$7439 $2\fast1$11[63:0]$7440 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" switch \should_trap attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast1$11[63:0]$7456 \trap_op__cia + assign $2\fast1$11[63:0]$7440 \trap_op__cia case - assign $2\fast1$11[63:0]$7456 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fast1$11[63:0]$7440 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" case 7'1001000 , 7'1001010 - assign $1\fast1$11[63:0]$7455 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$11[63:0]$7439 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000111 - assign $1\fast1$11[63:0]$7455 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$11[63:0]$7439 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000110 - assign $1\fast1$11[63:0]$7455 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$11[63:0]$7439 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1001001 assign { } { } - assign $1\fast1$11[63:0]$7455 \$39 [63:0] + assign $1\fast1$11[63:0]$7439 \$39 [63:0] case - assign $1\fast1$11[63:0]$7455 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$11[63:0]$7439 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fast1$11 $0\fast1$11[63:0]$7454 + update \fast1$11 $0\fast1$11[63:0]$7438 end - attribute \src "libresoc.v:149605.3-149636.6" - process $proc$libresoc.v:149605$7457 + attribute \src "libresoc.v:150561.3-150592.6" + process $proc$libresoc.v:150561$7441 assign { } { } assign { } { } assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] - attribute \src "libresoc.v:149606.5-149606.29" + attribute \src "libresoc.v:150562.5-150562.29" switch \initial - attribute \src "libresoc.v:149606.9-149606.17" + attribute \src "libresoc.v:150562.9-150562.17" case 1'1 case end @@ -309195,14 +280298,14 @@ module \main$38 sync always update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:149637.3-149719.6" - process $proc$libresoc.v:149637$7458 + attribute \src "libresoc.v:150593.3-150675.6" + process $proc$libresoc.v:150593$7442 assign { } { } assign { } { } - assign $0\fast2$12[63:0]$7459 $1\fast2$12[63:0]$7460 - attribute \src "libresoc.v:149638.5-149638.29" + assign $0\fast2$12[63:0]$7443 $1\fast2$12[63:0]$7444 + attribute \src "libresoc.v:150594.5-150594.29" switch \initial - attribute \src "libresoc.v:149638.9-149638.17" + attribute \src "libresoc.v:150594.9-150594.17" case 1'1 case end @@ -309211,59 +280314,59 @@ module \main$38 attribute \src "libresoc.v:0.0-0.0" case 7'0111111 assign { } { } - assign $1\fast2$12[63:0]$7460 $2\fast2$12[63:0]$7461 + assign $1\fast2$12[63:0]$7444 $2\fast2$12[63:0]$7445 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" switch \should_trap attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign { $2\fast2$12[63:0]$7461 [29] $2\fast2$12[63:0]$7461 [27] $2\fast2$12[63:0]$7461 [21] } 3'000 - assign $2\fast2$12[63:0]$7461 [15:0] \trap_op__msr [15:0] - assign $2\fast2$12[63:0]$7461 [26:22] \trap_op__msr [26:22] - assign $2\fast2$12[63:0]$7461 [63:31] \trap_op__msr [63:31] - assign $2\fast2$12[63:0]$7461 [17] $3\fast2$12[17:17]$7462 - assign { } { } - assign $2\fast2$12[63:0]$7461 [20] $5\fast2$12[20:20]$7464 - assign $2\fast2$12[63:0]$7461 [16] $6\fast2$12[16:16]$7465 - assign $2\fast2$12[63:0]$7461 [18] $7\fast2$12[19:18]$7466 [0] - assign $2\fast2$12[63:0]$7461 [28] $8\fast2$12[28:28]$7467 - assign $2\fast2$12[63:0]$7461 [30] $9\fast2$12[30:30]$7468 - assign $2\fast2$12[63:0]$7461 [19] $10\fast2$12[19:19]$7469 + assign { $2\fast2$12[63:0]$7445 [29] $2\fast2$12[63:0]$7445 [27] $2\fast2$12[63:0]$7445 [21] } 3'000 + assign $2\fast2$12[63:0]$7445 [15:0] \trap_op__msr [15:0] + assign $2\fast2$12[63:0]$7445 [26:22] \trap_op__msr [26:22] + assign $2\fast2$12[63:0]$7445 [63:31] \trap_op__msr [63:31] + assign $2\fast2$12[63:0]$7445 [17] $3\fast2$12[17:17]$7446 + assign { } { } + assign $2\fast2$12[63:0]$7445 [20] $5\fast2$12[20:20]$7448 + assign $2\fast2$12[63:0]$7445 [16] $6\fast2$12[16:16]$7449 + assign $2\fast2$12[63:0]$7445 [18] $7\fast2$12[19:18]$7450 [0] + assign $2\fast2$12[63:0]$7445 [28] $8\fast2$12[28:28]$7451 + assign $2\fast2$12[63:0]$7445 [30] $9\fast2$12[30:30]$7452 + assign $2\fast2$12[63:0]$7445 [19] $10\fast2$12[19:19]$7453 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:190" switch \$42 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fast2$12[17:17]$7462 1'1 + assign $3\fast2$12[17:17]$7446 1'1 case - assign $3\fast2$12[17:17]$7462 1'0 + assign $3\fast2$12[17:17]$7446 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:193" switch \$44 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\fast2$12[18:18]$7463 1'1 + assign $4\fast2$12[18:18]$7447 1'1 case - assign $4\fast2$12[18:18]$7463 1'0 + assign $4\fast2$12[18:18]$7447 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195" switch \$48 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fast2$12[20:20]$7464 1'1 + assign $5\fast2$12[20:20]$7448 1'1 case - assign $5\fast2$12[20:20]$7464 1'0 + assign $5\fast2$12[20:20]$7448 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:197" switch \$52 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\fast2$12[16:16]$7465 1'1 + assign $6\fast2$12[16:16]$7449 1'1 case - assign $6\fast2$12[16:16]$7465 1'0 + assign $6\fast2$12[16:16]$7449 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" switch \$56 @@ -309272,57 +280375,57 @@ module \main$38 assign { } { } assign { } { } assign { } { } - assign $9\fast2$12[30:30]$7468 \trapexc_$signal - assign $8\fast2$12[28:28]$7467 \trapexc_$signal$60 - assign $7\fast2$12[19:18]$7466 [1] \trapexc_$signal$61 - assign $7\fast2$12[19:18]$7466 [0] \trapexc_$signal$62 + assign $9\fast2$12[30:30]$7452 \trapexc_$signal + assign $8\fast2$12[28:28]$7451 \trapexc_$signal$60 + assign $7\fast2$12[19:18]$7450 [1] \trapexc_$signal$61 + assign $7\fast2$12[19:18]$7450 [0] \trapexc_$signal$62 case - assign $7\fast2$12[19:18]$7466 { 1'0 $4\fast2$12[18:18]$7463 } - assign $8\fast2$12[28:28]$7467 1'0 - assign $9\fast2$12[30:30]$7468 1'0 + assign $7\fast2$12[19:18]$7450 { 1'0 $4\fast2$12[18:18]$7447 } + assign $8\fast2$12[28:28]$7451 1'0 + assign $9\fast2$12[30:30]$7452 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213" switch \$63 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $10\fast2$12[19:19]$7469 1'1 + assign $10\fast2$12[19:19]$7453 1'1 case - assign $10\fast2$12[19:19]$7469 $7\fast2$12[19:18]$7466 [1] + assign $10\fast2$12[19:19]$7453 $7\fast2$12[19:18]$7450 [1] end case - assign $2\fast2$12[63:0]$7461 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fast2$12[63:0]$7445 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" case 7'1001000 , 7'1001010 - assign $1\fast2$12[63:0]$7460 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast2$12[63:0]$7444 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000111 - assign $1\fast2$12[63:0]$7460 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast2$12[63:0]$7444 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1000110 - assign $1\fast2$12[63:0]$7460 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast2$12[63:0]$7444 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case 7'1001001 assign { } { } - assign { $1\fast2$12[63:0]$7460 [30:27] $1\fast2$12[63:0]$7460 [21:16] } 10'0000000000 - assign $1\fast2$12[63:0]$7460 [15:0] \trap_op__msr [15:0] - assign $1\fast2$12[63:0]$7460 [26:22] \trap_op__msr [26:22] - assign $1\fast2$12[63:0]$7460 [63:31] \trap_op__msr [63:31] + assign { $1\fast2$12[63:0]$7444 [30:27] $1\fast2$12[63:0]$7444 [21:16] } 10'0000000000 + assign $1\fast2$12[63:0]$7444 [15:0] \trap_op__msr [15:0] + assign $1\fast2$12[63:0]$7444 [26:22] \trap_op__msr [26:22] + assign $1\fast2$12[63:0]$7444 [63:31] \trap_op__msr [63:31] case - assign $1\fast2$12[63:0]$7460 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast2$12[63:0]$7444 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fast2$12 $0\fast2$12[63:0]$7459 + update \fast2$12 $0\fast2$12[63:0]$7443 end - attribute \src "libresoc.v:149720.3-149751.6" - process $proc$libresoc.v:149720$7470 + attribute \src "libresoc.v:150676.3-150707.6" + process $proc$libresoc.v:150676$7454 assign { } { } assign { } { } assign $0\fast2_ok[0:0] $1\fast2_ok[0:0] - attribute \src "libresoc.v:149721.5-149721.29" + attribute \src "libresoc.v:150677.5-150677.29" switch \initial - attribute \src "libresoc.v:149721.9-149721.17" + attribute \src "libresoc.v:150677.9-150677.17" case 1'1 case end @@ -309360,8 +280463,8 @@ module \main$38 sync always update \fast2_ok $0\fast2_ok[0:0] end - attribute \src "libresoc.v:149752.3-149779.6" - process $proc$libresoc.v:149752$7471 + attribute \src "libresoc.v:150708.3-150735.6" + process $proc$libresoc.v:150708$7455 assign { } { } assign { } { } assign { } { } @@ -309378,17 +280481,17 @@ module \main$38 assign { } { } assign { } { } assign { } { } - assign $0\trapexc_$signal[0:0]$7472 $1\trapexc_$signal[0:0]$7480 - assign $0\trapexc_$signal$60[0:0]$7473 $1\trapexc_$signal$60[0:0]$7481 - assign $0\trapexc_$signal$61[0:0]$7474 $1\trapexc_$signal$61[0:0]$7482 - assign $0\trapexc_$signal$62[0:0]$7475 $1\trapexc_$signal$62[0:0]$7483 - assign $0\trapexc_$signal$67[0:0]$7476 $1\trapexc_$signal$67[0:0]$7484 - assign $0\trapexc_$signal$68[0:0]$7477 $1\trapexc_$signal$68[0:0]$7485 - assign $0\trapexc_$signal$69[0:0]$7478 $1\trapexc_$signal$69[0:0]$7486 - assign $0\trapexc_$signal$70[0:0]$7479 $1\trapexc_$signal$70[0:0]$7487 - attribute \src "libresoc.v:149753.5-149753.29" + assign $0\trapexc_$signal[0:0]$7456 $1\trapexc_$signal[0:0]$7464 + assign $0\trapexc_$signal$60[0:0]$7457 $1\trapexc_$signal$60[0:0]$7465 + assign $0\trapexc_$signal$61[0:0]$7458 $1\trapexc_$signal$61[0:0]$7466 + assign $0\trapexc_$signal$62[0:0]$7459 $1\trapexc_$signal$62[0:0]$7467 + assign $0\trapexc_$signal$67[0:0]$7460 $1\trapexc_$signal$67[0:0]$7468 + assign $0\trapexc_$signal$68[0:0]$7461 $1\trapexc_$signal$68[0:0]$7469 + assign $0\trapexc_$signal$69[0:0]$7462 $1\trapexc_$signal$69[0:0]$7470 + assign $0\trapexc_$signal$70[0:0]$7463 $1\trapexc_$signal$70[0:0]$7471 + attribute \src "libresoc.v:150709.5-150709.29" switch \initial - attribute \src "libresoc.v:149753.9-149753.17" + attribute \src "libresoc.v:150709.9-150709.17" case 1'1 case end @@ -309404,14 +280507,14 @@ module \main$38 assign { } { } assign { } { } assign { } { } - assign $1\trapexc_$signal[0:0]$7480 $2\trapexc_$signal[0:0]$7488 - assign $1\trapexc_$signal$60[0:0]$7481 $2\trapexc_$signal$60[0:0]$7489 - assign $1\trapexc_$signal$61[0:0]$7482 $2\trapexc_$signal$61[0:0]$7490 - assign $1\trapexc_$signal$62[0:0]$7483 $2\trapexc_$signal$62[0:0]$7491 - assign $1\trapexc_$signal$67[0:0]$7484 $2\trapexc_$signal$67[0:0]$7492 - assign $1\trapexc_$signal$68[0:0]$7485 $2\trapexc_$signal$68[0:0]$7493 - assign $1\trapexc_$signal$69[0:0]$7486 $2\trapexc_$signal$69[0:0]$7494 - assign $1\trapexc_$signal$70[0:0]$7487 $2\trapexc_$signal$70[0:0]$7495 + assign $1\trapexc_$signal[0:0]$7464 $2\trapexc_$signal[0:0]$7472 + assign $1\trapexc_$signal$60[0:0]$7465 $2\trapexc_$signal$60[0:0]$7473 + assign $1\trapexc_$signal$61[0:0]$7466 $2\trapexc_$signal$61[0:0]$7474 + assign $1\trapexc_$signal$62[0:0]$7467 $2\trapexc_$signal$62[0:0]$7475 + assign $1\trapexc_$signal$67[0:0]$7468 $2\trapexc_$signal$67[0:0]$7476 + assign $1\trapexc_$signal$68[0:0]$7469 $2\trapexc_$signal$68[0:0]$7477 + assign $1\trapexc_$signal$69[0:0]$7470 $2\trapexc_$signal$69[0:0]$7478 + assign $1\trapexc_$signal$70[0:0]$7471 $2\trapexc_$signal$70[0:0]$7479 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187" switch \should_trap attribute \src "libresoc.v:0.0-0.0" @@ -309424,14 +280527,14 @@ module \main$38 assign { } { } assign { } { } assign { } { } - assign $2\trapexc_$signal[0:0]$7488 $3\trapexc_$signal[0:0]$7496 - assign $2\trapexc_$signal$60[0:0]$7489 $3\trapexc_$signal$60[0:0]$7497 - assign $2\trapexc_$signal$61[0:0]$7490 $3\trapexc_$signal$61[0:0]$7498 - assign $2\trapexc_$signal$62[0:0]$7491 $3\trapexc_$signal$62[0:0]$7499 - assign $2\trapexc_$signal$67[0:0]$7492 $3\trapexc_$signal$67[0:0]$7500 - assign $2\trapexc_$signal$68[0:0]$7493 $3\trapexc_$signal$68[0:0]$7501 - assign $2\trapexc_$signal$69[0:0]$7494 $3\trapexc_$signal$69[0:0]$7502 - assign $2\trapexc_$signal$70[0:0]$7495 $3\trapexc_$signal$70[0:0]$7503 + assign $2\trapexc_$signal[0:0]$7472 $3\trapexc_$signal[0:0]$7480 + assign $2\trapexc_$signal$60[0:0]$7473 $3\trapexc_$signal$60[0:0]$7481 + assign $2\trapexc_$signal$61[0:0]$7474 $3\trapexc_$signal$61[0:0]$7482 + assign $2\trapexc_$signal$62[0:0]$7475 $3\trapexc_$signal$62[0:0]$7483 + assign $2\trapexc_$signal$67[0:0]$7476 $3\trapexc_$signal$67[0:0]$7484 + assign $2\trapexc_$signal$68[0:0]$7477 $3\trapexc_$signal$68[0:0]$7485 + assign $2\trapexc_$signal$69[0:0]$7478 $3\trapexc_$signal$69[0:0]$7486 + assign $2\trapexc_$signal$70[0:0]$7479 $3\trapexc_$signal$70[0:0]$7487 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199" switch \$71 attribute \src "libresoc.v:0.0-0.0" @@ -309444,54 +280547,54 @@ module \main$38 assign { } { } assign { } { } assign { } { } - assign { $3\trapexc_$signal$70[0:0]$7503 $3\trapexc_$signal$62[0:0]$7499 $3\trapexc_$signal$60[0:0]$7497 $3\trapexc_$signal$61[0:0]$7498 $3\trapexc_$signal[0:0]$7496 $3\trapexc_$signal$69[0:0]$7502 $3\trapexc_$signal$68[0:0]$7501 $3\trapexc_$signal$67[0:0]$7500 } \trap_op__ldst_exc + assign { $3\trapexc_$signal$70[0:0]$7487 $3\trapexc_$signal$62[0:0]$7483 $3\trapexc_$signal$60[0:0]$7481 $3\trapexc_$signal$61[0:0]$7482 $3\trapexc_$signal[0:0]$7480 $3\trapexc_$signal$69[0:0]$7486 $3\trapexc_$signal$68[0:0]$7485 $3\trapexc_$signal$67[0:0]$7484 } \trap_op__ldst_exc case - assign $3\trapexc_$signal[0:0]$7496 1'0 - assign $3\trapexc_$signal$60[0:0]$7497 1'0 - assign $3\trapexc_$signal$61[0:0]$7498 1'0 - assign $3\trapexc_$signal$62[0:0]$7499 1'0 - assign $3\trapexc_$signal$67[0:0]$7500 1'0 - assign $3\trapexc_$signal$68[0:0]$7501 1'0 - assign $3\trapexc_$signal$69[0:0]$7502 1'0 - assign $3\trapexc_$signal$70[0:0]$7503 1'0 + assign $3\trapexc_$signal[0:0]$7480 1'0 + assign $3\trapexc_$signal$60[0:0]$7481 1'0 + assign $3\trapexc_$signal$61[0:0]$7482 1'0 + assign $3\trapexc_$signal$62[0:0]$7483 1'0 + assign $3\trapexc_$signal$67[0:0]$7484 1'0 + assign $3\trapexc_$signal$68[0:0]$7485 1'0 + assign $3\trapexc_$signal$69[0:0]$7486 1'0 + assign $3\trapexc_$signal$70[0:0]$7487 1'0 end case - assign $2\trapexc_$signal[0:0]$7488 1'0 - assign $2\trapexc_$signal$60[0:0]$7489 1'0 - assign $2\trapexc_$signal$61[0:0]$7490 1'0 - assign $2\trapexc_$signal$62[0:0]$7491 1'0 - assign $2\trapexc_$signal$67[0:0]$7492 1'0 - assign $2\trapexc_$signal$68[0:0]$7493 1'0 - assign $2\trapexc_$signal$69[0:0]$7494 1'0 - assign $2\trapexc_$signal$70[0:0]$7495 1'0 - end - case - assign $1\trapexc_$signal[0:0]$7480 1'0 - assign $1\trapexc_$signal$60[0:0]$7481 1'0 - assign $1\trapexc_$signal$61[0:0]$7482 1'0 - assign $1\trapexc_$signal$62[0:0]$7483 1'0 - assign $1\trapexc_$signal$67[0:0]$7484 1'0 - assign $1\trapexc_$signal$68[0:0]$7485 1'0 - assign $1\trapexc_$signal$69[0:0]$7486 1'0 - assign $1\trapexc_$signal$70[0:0]$7487 1'0 - end - sync always - update \trapexc_$signal $0\trapexc_$signal[0:0]$7472 - update \trapexc_$signal$60 $0\trapexc_$signal$60[0:0]$7473 - update \trapexc_$signal$61 $0\trapexc_$signal$61[0:0]$7474 - update \trapexc_$signal$62 $0\trapexc_$signal$62[0:0]$7475 - update \trapexc_$signal$67 $0\trapexc_$signal$67[0:0]$7476 - update \trapexc_$signal$68 $0\trapexc_$signal$68[0:0]$7477 - update \trapexc_$signal$69 $0\trapexc_$signal$69[0:0]$7478 - update \trapexc_$signal$70 $0\trapexc_$signal$70[0:0]$7479 - end - attribute \src "libresoc.v:149780.3-149791.6" - process $proc$libresoc.v:149780$7504 + assign $2\trapexc_$signal[0:0]$7472 1'0 + assign $2\trapexc_$signal$60[0:0]$7473 1'0 + assign $2\trapexc_$signal$61[0:0]$7474 1'0 + assign $2\trapexc_$signal$62[0:0]$7475 1'0 + assign $2\trapexc_$signal$67[0:0]$7476 1'0 + assign $2\trapexc_$signal$68[0:0]$7477 1'0 + assign $2\trapexc_$signal$69[0:0]$7478 1'0 + assign $2\trapexc_$signal$70[0:0]$7479 1'0 + end + case + assign $1\trapexc_$signal[0:0]$7464 1'0 + assign $1\trapexc_$signal$60[0:0]$7465 1'0 + assign $1\trapexc_$signal$61[0:0]$7466 1'0 + assign $1\trapexc_$signal$62[0:0]$7467 1'0 + assign $1\trapexc_$signal$67[0:0]$7468 1'0 + assign $1\trapexc_$signal$68[0:0]$7469 1'0 + assign $1\trapexc_$signal$69[0:0]$7470 1'0 + assign $1\trapexc_$signal$70[0:0]$7471 1'0 + end + sync always + update \trapexc_$signal $0\trapexc_$signal[0:0]$7456 + update \trapexc_$signal$60 $0\trapexc_$signal$60[0:0]$7457 + update \trapexc_$signal$61 $0\trapexc_$signal$61[0:0]$7458 + update \trapexc_$signal$62 $0\trapexc_$signal$62[0:0]$7459 + update \trapexc_$signal$67 $0\trapexc_$signal$67[0:0]$7460 + update \trapexc_$signal$68 $0\trapexc_$signal$68[0:0]$7461 + update \trapexc_$signal$69 $0\trapexc_$signal$69[0:0]$7462 + update \trapexc_$signal$70 $0\trapexc_$signal$70[0:0]$7463 + end + attribute \src "libresoc.v:150736.3-150747.6" + process $proc$libresoc.v:150736$7488 assign { } { } assign $0\b_s[63:0] $1\b_s[63:0] - attribute \src "libresoc.v:149781.5-149781.29" + attribute \src "libresoc.v:150737.5-150737.29" switch \initial - attribute \src "libresoc.v:149781.9-149781.17" + attribute \src "libresoc.v:150737.9-150737.17" case 1'1 case end @@ -309509,17 +280612,17 @@ module \main$38 sync always update \b_s $0\b_s[63:0] end - attribute \src "libresoc.v:149792.3-149960.6" - process $proc$libresoc.v:149792$7505 + attribute \src "libresoc.v:150748.3-150916.6" + process $proc$libresoc.v:150748$7489 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\msr[63:0] $1\msr[63:0] assign $0\msr_ok[0:0] $1\msr_ok[0:0] - attribute \src "libresoc.v:149793.5-149793.29" + attribute \src "libresoc.v:150749.5-150749.29" switch \initial - attribute \src "libresoc.v:149793.9-149793.17" + attribute \src "libresoc.v:150749.9-150749.17" case 1'1 case end @@ -309733,14 +280836,14 @@ module \main$38 update \msr $0\msr[63:0] update \msr_ok $0\msr_ok[0:0] end - attribute \src "libresoc.v:149961.3-149979.6" - process $proc$libresoc.v:149961$7506 + attribute \src "libresoc.v:150917.3-150935.6" + process $proc$libresoc.v:150917$7490 assign { } { } assign { } { } assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:149962.5-149962.29" + attribute \src "libresoc.v:150918.5-150918.29" switch \initial - attribute \src "libresoc.v:149962.9-149962.17" + attribute \src "libresoc.v:150918.9-150918.17" case 1'1 case end @@ -309762,14 +280865,14 @@ module \main$38 sync always update \o $0\o[63:0] end - attribute \src "libresoc.v:149980.3-149998.6" - process $proc$libresoc.v:149980$7507 + attribute \src "libresoc.v:150936.3-150954.6" + process $proc$libresoc.v:150936$7491 assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:149981.5-149981.29" + attribute \src "libresoc.v:150937.5-150937.29" switch \initial - attribute \src "libresoc.v:149981.9-149981.17" + attribute \src "libresoc.v:150937.9-150937.17" case 1'1 case end @@ -309791,13 +280894,13 @@ module \main$38 sync always update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:149999.3-150010.6" - process $proc$libresoc.v:149999$7508 + attribute \src "libresoc.v:150955.3-150966.6" + process $proc$libresoc.v:150955$7492 assign { } { } assign $0\a[63:0] $1\a[63:0] - attribute \src "libresoc.v:150000.5-150000.29" + attribute \src "libresoc.v:150956.5-150956.29" switch \initial - attribute \src "libresoc.v:150000.9-150000.17" + attribute \src "libresoc.v:150956.9-150956.17" case 1'1 case end @@ -309815,13 +280918,13 @@ module \main$38 sync always update \a $0\a[63:0] end - attribute \src "libresoc.v:150011.3-150022.6" - process $proc$libresoc.v:150011$7509 + attribute \src "libresoc.v:150967.3-150978.6" + process $proc$libresoc.v:150967$7493 assign { } { } assign $0\b[63:0] $1\b[63:0] - attribute \src "libresoc.v:150012.5-150012.29" + attribute \src "libresoc.v:150968.5-150968.29" switch \initial - attribute \src "libresoc.v:150012.9-150012.17" + attribute \src "libresoc.v:150968.9-150968.17" case 1'1 case end @@ -309839,43 +280942,43 @@ module \main$38 sync always update \b $0\b[63:0] end - connect \$13 $pos$libresoc.v:149460$7410_Y - connect \$15 $pos$libresoc.v:149461$7412_Y - connect \$17 $lt$libresoc.v:149462$7413_Y - connect \$19 $gt$libresoc.v:149463$7414_Y - connect \$21 $lt$libresoc.v:149464$7415_Y - connect \$23 $gt$libresoc.v:149465$7416_Y - connect \$25 $eq$libresoc.v:149466$7417_Y - connect \$28 $and$libresoc.v:149467$7418_Y - connect \$27 $reduce_or$libresoc.v:149468$7419_Y - connect \$31 $reduce_or$libresoc.v:149469$7420_Y - connect \$33 $or$libresoc.v:149470$7421_Y - connect \$36 $sshl$libresoc.v:149471$7422_Y - connect \$35 $pos$libresoc.v:149472$7424_Y - connect \$40 $add$libresoc.v:149473$7425_Y - connect \$42 $eq$libresoc.v:149474$7426_Y - connect \$45 $and$libresoc.v:149475$7427_Y - connect \$44 $reduce_or$libresoc.v:149476$7428_Y - connect \$49 $and$libresoc.v:149477$7429_Y - connect \$48 $reduce_or$libresoc.v:149478$7430_Y - connect \$53 $and$libresoc.v:149479$7431_Y - connect \$52 $reduce_or$libresoc.v:149480$7432_Y - connect \$57 $and$libresoc.v:149481$7433_Y - connect \$56 $reduce_or$libresoc.v:149482$7434_Y - connect \$64 $and$libresoc.v:149483$7435_Y - connect \$63 $reduce_or$libresoc.v:149484$7436_Y - connect \$72 $and$libresoc.v:149485$7437_Y - connect \$71 $reduce_or$libresoc.v:149486$7438_Y - connect \$75 $pos$libresoc.v:149487$7440_Y - connect \$77 $eq$libresoc.v:149488$7441_Y - connect \$79 $eq$libresoc.v:149489$7442_Y - connect \$81 $eq$libresoc.v:149490$7443_Y - connect \$83 $and$libresoc.v:149491$7444_Y - connect \$85 $not$libresoc.v:149492$7445_Y - connect \$87 $not$libresoc.v:149493$7446_Y - connect \$89 $eq$libresoc.v:149494$7447_Y - connect \$91 $eq$libresoc.v:149495$7448_Y - connect \$93 $and$libresoc.v:149496$7449_Y + connect \$13 $pos$libresoc.v:150416$7394_Y + connect \$15 $pos$libresoc.v:150417$7396_Y + connect \$17 $lt$libresoc.v:150418$7397_Y + connect \$19 $gt$libresoc.v:150419$7398_Y + connect \$21 $lt$libresoc.v:150420$7399_Y + connect \$23 $gt$libresoc.v:150421$7400_Y + connect \$25 $eq$libresoc.v:150422$7401_Y + connect \$28 $and$libresoc.v:150423$7402_Y + connect \$27 $reduce_or$libresoc.v:150424$7403_Y + connect \$31 $reduce_or$libresoc.v:150425$7404_Y + connect \$33 $or$libresoc.v:150426$7405_Y + connect \$36 $sshl$libresoc.v:150427$7406_Y + connect \$35 $pos$libresoc.v:150428$7408_Y + connect \$40 $add$libresoc.v:150429$7409_Y + connect \$42 $eq$libresoc.v:150430$7410_Y + connect \$45 $and$libresoc.v:150431$7411_Y + connect \$44 $reduce_or$libresoc.v:150432$7412_Y + connect \$49 $and$libresoc.v:150433$7413_Y + connect \$48 $reduce_or$libresoc.v:150434$7414_Y + connect \$53 $and$libresoc.v:150435$7415_Y + connect \$52 $reduce_or$libresoc.v:150436$7416_Y + connect \$57 $and$libresoc.v:150437$7417_Y + connect \$56 $reduce_or$libresoc.v:150438$7418_Y + connect \$64 $and$libresoc.v:150439$7419_Y + connect \$63 $reduce_or$libresoc.v:150440$7420_Y + connect \$72 $and$libresoc.v:150441$7421_Y + connect \$71 $reduce_or$libresoc.v:150442$7422_Y + connect \$75 $pos$libresoc.v:150443$7424_Y + connect \$77 $eq$libresoc.v:150444$7425_Y + connect \$79 $eq$libresoc.v:150445$7426_Y + connect \$81 $eq$libresoc.v:150446$7427_Y + connect \$83 $and$libresoc.v:150447$7428_Y + connect \$85 $not$libresoc.v:150448$7429_Y + connect \$87 $not$libresoc.v:150449$7430_Y + connect \$89 $eq$libresoc.v:150450$7431_Y + connect \$91 $eq$libresoc.v:150451$7432_Y + connect \$93 $and$libresoc.v:150452$7433_Y connect \$39 \$40 connect { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } connect \muxid$1 \muxid @@ -309888,239 +280991,239 @@ module \main$38 connect \lt_s \$17 connect \to \trap_op__insn [25:21] end -attribute \src "libresoc.v:150038.1-150787.10" +attribute \src "libresoc.v:150994.1-151983.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main" attribute \generator "nMigen" module \main$51 - attribute \src "libresoc.v:150754.3-150764.6" + attribute \src "libresoc.v:151902.3-151936.6" wire width 32 $0\a32[31:0] - attribute \src "libresoc.v:150699.3-150709.6" + attribute \src "libresoc.v:151751.3-151777.6" wire width 64 $0\b[63:0] - attribute \src "libresoc.v:150677.3-150687.6" + attribute \src "libresoc.v:151685.3-151723.6" wire width 64 $0\bpermd_rb[63:0] - attribute \src "libresoc.v:150666.3-150676.6" + attribute \src "libresoc.v:151646.3-151684.6" wire width 64 $0\bpermd_rs[63:0] - attribute \src "libresoc.v:150655.3-150665.6" + attribute \src "libresoc.v:151611.3-151645.6" wire width 64 $0\clz_sig_in[63:0] - attribute \src "libresoc.v:150765.3-150783.6" + attribute \src "libresoc.v:151937.3-151979.6" wire width 64 $0\cntz_i[63:0] - attribute \src "libresoc.v:150743.3-150753.6" + attribute \src "libresoc.v:151867.3-151901.6" wire $0\count_right[0:0] - attribute \src "libresoc.v:150039.7-150039.20" + attribute \src "libresoc.v:150995.7-150995.20" wire $0\initial[0:0] - attribute \src "libresoc.v:150600.3-150654.6" + attribute \src "libresoc.v:151556.3-151610.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:150600.3-150654.6" + attribute \src "libresoc.v:151556.3-151610.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:150721.3-150731.6" + attribute \src "libresoc.v:151805.3-151835.6" wire $0\par0[0:0] - attribute \src "libresoc.v:150732.3-150742.6" + attribute \src "libresoc.v:151836.3-151866.6" wire $0\par1[0:0] - attribute \src "libresoc.v:150688.3-150698.6" + attribute \src "libresoc.v:151724.3-151750.6" wire width 64 $0\popcount_a[63:0] - attribute \src "libresoc.v:150710.3-150720.6" + attribute \src "libresoc.v:151778.3-151804.6" wire width 64 $0\popcount_data_len[63:0] - attribute \src "libresoc.v:150754.3-150764.6" + attribute \src "libresoc.v:151902.3-151936.6" wire width 32 $1\a32[31:0] - attribute \src "libresoc.v:150699.3-150709.6" + attribute \src "libresoc.v:151751.3-151777.6" wire width 64 $1\b[63:0] - attribute \src "libresoc.v:150677.3-150687.6" + attribute \src "libresoc.v:151685.3-151723.6" wire width 64 $1\bpermd_rb[63:0] - attribute \src "libresoc.v:150666.3-150676.6" + attribute \src "libresoc.v:151646.3-151684.6" wire width 64 $1\bpermd_rs[63:0] - attribute \src "libresoc.v:150655.3-150665.6" + attribute \src "libresoc.v:151611.3-151645.6" wire width 64 $1\clz_sig_in[63:0] - attribute \src "libresoc.v:150765.3-150783.6" + attribute \src "libresoc.v:151937.3-151979.6" wire width 64 $1\cntz_i[63:0] - attribute \src "libresoc.v:150743.3-150753.6" + attribute \src "libresoc.v:151867.3-151901.6" wire $1\count_right[0:0] - attribute \src "libresoc.v:150600.3-150654.6" + attribute \src "libresoc.v:151556.3-151610.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:150600.3-150654.6" + attribute \src "libresoc.v:151556.3-151610.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:150721.3-150731.6" + attribute \src "libresoc.v:151805.3-151835.6" wire $1\par0[0:0] - attribute \src "libresoc.v:150732.3-150742.6" + attribute \src "libresoc.v:151836.3-151866.6" wire $1\par1[0:0] - attribute \src "libresoc.v:150688.3-150698.6" + attribute \src "libresoc.v:151724.3-151750.6" wire width 64 $1\popcount_a[63:0] - attribute \src "libresoc.v:150710.3-150720.6" + attribute \src "libresoc.v:151778.3-151804.6" wire width 64 $1\popcount_data_len[63:0] - attribute \src "libresoc.v:150765.3-150783.6" + attribute \src "libresoc.v:151937.3-151979.6" wire width 64 $2\cntz_i[63:0] - attribute \src "libresoc.v:150600.3-150654.6" + attribute \src "libresoc.v:151556.3-151610.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:150547.18-150547.103" - wire width 64 $and$libresoc.v:150547$7557_Y - attribute \src "libresoc.v:150506.18-150506.118" - wire $eq$libresoc.v:150506$7511_Y - attribute \src "libresoc.v:150507.19-150507.119" - wire $eq$libresoc.v:150507$7512_Y - attribute \src "libresoc.v:150508.19-150508.119" - wire $eq$libresoc.v:150508$7513_Y - attribute \src "libresoc.v:150509.19-150509.119" - wire $eq$libresoc.v:150509$7514_Y - attribute \src "libresoc.v:150510.19-150510.119" - wire $eq$libresoc.v:150510$7515_Y - attribute \src "libresoc.v:150511.19-150511.119" - wire $eq$libresoc.v:150511$7516_Y - attribute \src "libresoc.v:150512.19-150512.119" - wire $eq$libresoc.v:150512$7517_Y - attribute \src "libresoc.v:150513.19-150513.119" - wire $eq$libresoc.v:150513$7518_Y - attribute \src "libresoc.v:150514.19-150514.119" - wire $eq$libresoc.v:150514$7519_Y - attribute \src "libresoc.v:150515.19-150515.119" - wire $eq$libresoc.v:150515$7520_Y - attribute \src "libresoc.v:150516.19-150516.119" - wire $eq$libresoc.v:150516$7521_Y - attribute \src "libresoc.v:150517.19-150517.119" - wire $eq$libresoc.v:150517$7522_Y - attribute \src "libresoc.v:150518.19-150518.119" - wire $eq$libresoc.v:150518$7523_Y - attribute \src "libresoc.v:150519.19-150519.119" - wire $eq$libresoc.v:150519$7524_Y - attribute \src "libresoc.v:150520.19-150520.119" - wire $eq$libresoc.v:150520$7525_Y - attribute \src "libresoc.v:150521.19-150521.119" - wire $eq$libresoc.v:150521$7526_Y - attribute \src "libresoc.v:150522.19-150522.119" - wire $eq$libresoc.v:150522$7527_Y - attribute \src "libresoc.v:150523.19-150523.119" - wire $eq$libresoc.v:150523$7528_Y - attribute \src "libresoc.v:150524.19-150524.119" - wire $eq$libresoc.v:150524$7529_Y - attribute \src "libresoc.v:150525.19-150525.119" - wire $eq$libresoc.v:150525$7530_Y - attribute \src "libresoc.v:150526.19-150526.119" - wire $eq$libresoc.v:150526$7531_Y - attribute \src "libresoc.v:150527.19-150527.119" - wire $eq$libresoc.v:150527$7532_Y - attribute \src "libresoc.v:150528.19-150528.119" - wire $eq$libresoc.v:150528$7533_Y - attribute \src "libresoc.v:150529.19-150529.119" - wire $eq$libresoc.v:150529$7534_Y - attribute \src "libresoc.v:150530.19-150530.119" - wire $eq$libresoc.v:150530$7535_Y - attribute \src "libresoc.v:150531.19-150531.119" - wire $eq$libresoc.v:150531$7536_Y - attribute \src "libresoc.v:150532.19-150532.119" - wire $eq$libresoc.v:150532$7537_Y - attribute \src "libresoc.v:150533.19-150533.119" - wire $eq$libresoc.v:150533$7538_Y - attribute \src "libresoc.v:150534.19-150534.128" - wire $eq$libresoc.v:150534$7539_Y - attribute \src "libresoc.v:150550.18-150550.114" - wire $eq$libresoc.v:150550$7560_Y - attribute \src "libresoc.v:150551.18-150551.114" - wire $eq$libresoc.v:150551$7561_Y - attribute \src "libresoc.v:150552.18-150552.114" - wire $eq$libresoc.v:150552$7562_Y - attribute \src "libresoc.v:150553.18-150553.114" - wire $eq$libresoc.v:150553$7563_Y - attribute \src "libresoc.v:150554.18-150554.114" - wire $eq$libresoc.v:150554$7564_Y - attribute \src "libresoc.v:150555.18-150555.114" - wire $eq$libresoc.v:150555$7565_Y - attribute \src "libresoc.v:150556.18-150556.114" - wire $eq$libresoc.v:150556$7566_Y - attribute \src "libresoc.v:150557.18-150557.114" - wire $eq$libresoc.v:150557$7567_Y - attribute \src "libresoc.v:150558.18-150558.116" - wire $eq$libresoc.v:150558$7568_Y - attribute \src "libresoc.v:150559.18-150559.116" - wire $eq$libresoc.v:150559$7569_Y - attribute \src "libresoc.v:150560.18-150560.116" - wire $eq$libresoc.v:150560$7570_Y - attribute \src "libresoc.v:150561.18-150561.116" - wire $eq$libresoc.v:150561$7571_Y - attribute \src "libresoc.v:150562.18-150562.116" - wire $eq$libresoc.v:150562$7572_Y - attribute \src "libresoc.v:150563.18-150563.116" - wire $eq$libresoc.v:150563$7573_Y - attribute \src "libresoc.v:150564.18-150564.116" - wire $eq$libresoc.v:150564$7574_Y - attribute \src "libresoc.v:150565.18-150565.116" - wire $eq$libresoc.v:150565$7575_Y - attribute \src "libresoc.v:150566.18-150566.118" - wire $eq$libresoc.v:150566$7576_Y - attribute \src "libresoc.v:150567.18-150567.118" - wire $eq$libresoc.v:150567$7577_Y - attribute \src "libresoc.v:150568.18-150568.118" - wire $eq$libresoc.v:150568$7578_Y - attribute \src "libresoc.v:150569.18-150569.118" - wire $eq$libresoc.v:150569$7579_Y - attribute \src "libresoc.v:150570.18-150570.118" - wire $eq$libresoc.v:150570$7580_Y - attribute \src "libresoc.v:150571.18-150571.118" - wire $eq$libresoc.v:150571$7581_Y - attribute \src "libresoc.v:150572.18-150572.118" - wire $eq$libresoc.v:150572$7582_Y - attribute \src "libresoc.v:150573.18-150573.118" - wire $eq$libresoc.v:150573$7583_Y - attribute \src "libresoc.v:150574.18-150574.118" - wire $eq$libresoc.v:150574$7584_Y - attribute \src "libresoc.v:150575.18-150575.118" - wire $eq$libresoc.v:150575$7585_Y - attribute \src "libresoc.v:150576.18-150576.118" - wire $eq$libresoc.v:150576$7586_Y - attribute \src "libresoc.v:150577.18-150577.118" - wire $eq$libresoc.v:150577$7587_Y - attribute \src "libresoc.v:150578.18-150578.118" - wire $eq$libresoc.v:150578$7588_Y - attribute \src "libresoc.v:150579.18-150579.118" - wire $eq$libresoc.v:150579$7589_Y - attribute \src "libresoc.v:150580.18-150580.118" - wire $eq$libresoc.v:150580$7590_Y - attribute \src "libresoc.v:150581.18-150581.118" - wire $eq$libresoc.v:150581$7591_Y - attribute \src "libresoc.v:150582.18-150582.118" - wire $eq$libresoc.v:150582$7592_Y - attribute \src "libresoc.v:150583.18-150583.118" - wire $eq$libresoc.v:150583$7593_Y - attribute \src "libresoc.v:150584.18-150584.118" - wire $eq$libresoc.v:150584$7594_Y - attribute \src "libresoc.v:150585.18-150585.118" - wire $eq$libresoc.v:150585$7595_Y - attribute \src "libresoc.v:150536.19-150536.104" - wire width 64 $extend$libresoc.v:150536$7541_Y - attribute \src "libresoc.v:150538.19-150538.93" - wire width 8 $extend$libresoc.v:150538$7544_Y - attribute \src "libresoc.v:150540.19-150540.105" - wire width 64 $extend$libresoc.v:150540$7547_Y - attribute \src "libresoc.v:150541.19-150541.118" - wire width 64 $extend$libresoc.v:150541$7549_Y - attribute \src "libresoc.v:150545.19-150545.105" - wire width 64 $extend$libresoc.v:150545$7554_Y - attribute \src "libresoc.v:150548.18-150548.103" - wire width 64 $or$libresoc.v:150548$7558_Y - attribute \src "libresoc.v:150536.19-150536.104" - wire width 64 $pos$libresoc.v:150536$7542_Y - attribute \src "libresoc.v:150538.19-150538.93" - wire width 8 $pos$libresoc.v:150538$7545_Y - attribute \src "libresoc.v:150540.19-150540.105" - wire width 64 $pos$libresoc.v:150540$7548_Y - attribute \src "libresoc.v:150541.19-150541.118" - wire width 64 $pos$libresoc.v:150541$7550_Y - attribute \src "libresoc.v:150545.19-150545.105" - wire width 64 $pos$libresoc.v:150545$7555_Y - attribute \src "libresoc.v:150542.19-150542.131" - wire $reduce_xor$libresoc.v:150542$7551_Y - attribute \src "libresoc.v:150543.19-150543.133" - wire $reduce_xor$libresoc.v:150543$7552_Y - attribute \src "libresoc.v:150537.19-150537.112" - wire width 8 $sub$libresoc.v:150537$7543_Y - attribute \src "libresoc.v:150539.19-150539.135" - wire width 8 $ternary$libresoc.v:150539$7546_Y - attribute \src "libresoc.v:150544.19-150544.398" - wire width 32 $ternary$libresoc.v:150544$7553_Y - attribute \src "libresoc.v:150546.19-150546.621" - wire width 64 $ternary$libresoc.v:150546$7556_Y - attribute \src "libresoc.v:150535.19-150535.108" - wire $xor$libresoc.v:150535$7540_Y - attribute \src "libresoc.v:150549.18-150549.103" - wire width 64 $xor$libresoc.v:150549$7559_Y + attribute \src "libresoc.v:151503.18-151503.103" + wire width 64 $and$libresoc.v:151503$7541_Y + attribute \src "libresoc.v:151462.18-151462.118" + wire $eq$libresoc.v:151462$7495_Y + attribute \src "libresoc.v:151463.19-151463.119" + wire $eq$libresoc.v:151463$7496_Y + attribute \src "libresoc.v:151464.19-151464.119" + wire $eq$libresoc.v:151464$7497_Y + attribute \src "libresoc.v:151465.19-151465.119" + wire $eq$libresoc.v:151465$7498_Y + attribute \src "libresoc.v:151466.19-151466.119" + wire $eq$libresoc.v:151466$7499_Y + attribute \src "libresoc.v:151467.19-151467.119" + wire $eq$libresoc.v:151467$7500_Y + attribute \src "libresoc.v:151468.19-151468.119" + wire $eq$libresoc.v:151468$7501_Y + attribute \src "libresoc.v:151469.19-151469.119" + wire $eq$libresoc.v:151469$7502_Y + attribute \src "libresoc.v:151470.19-151470.119" + wire $eq$libresoc.v:151470$7503_Y + attribute \src "libresoc.v:151471.19-151471.119" + wire $eq$libresoc.v:151471$7504_Y + attribute \src "libresoc.v:151472.19-151472.119" + wire $eq$libresoc.v:151472$7505_Y + attribute \src "libresoc.v:151473.19-151473.119" + wire $eq$libresoc.v:151473$7506_Y + attribute \src "libresoc.v:151474.19-151474.119" + wire $eq$libresoc.v:151474$7507_Y + attribute \src "libresoc.v:151475.19-151475.119" + wire $eq$libresoc.v:151475$7508_Y + attribute \src "libresoc.v:151476.19-151476.119" + wire $eq$libresoc.v:151476$7509_Y + attribute \src "libresoc.v:151477.19-151477.119" + wire $eq$libresoc.v:151477$7510_Y + attribute \src "libresoc.v:151478.19-151478.119" + wire $eq$libresoc.v:151478$7511_Y + attribute \src "libresoc.v:151479.19-151479.119" + wire $eq$libresoc.v:151479$7512_Y + attribute \src "libresoc.v:151480.19-151480.119" + wire $eq$libresoc.v:151480$7513_Y + attribute \src "libresoc.v:151481.19-151481.119" + wire $eq$libresoc.v:151481$7514_Y + attribute \src "libresoc.v:151482.19-151482.119" + wire $eq$libresoc.v:151482$7515_Y + attribute \src "libresoc.v:151483.19-151483.119" + wire $eq$libresoc.v:151483$7516_Y + attribute \src "libresoc.v:151484.19-151484.119" + wire $eq$libresoc.v:151484$7517_Y + attribute \src "libresoc.v:151485.19-151485.119" + wire $eq$libresoc.v:151485$7518_Y + attribute \src "libresoc.v:151486.19-151486.119" + wire $eq$libresoc.v:151486$7519_Y + attribute \src "libresoc.v:151487.19-151487.119" + wire $eq$libresoc.v:151487$7520_Y + attribute \src "libresoc.v:151488.19-151488.119" + wire $eq$libresoc.v:151488$7521_Y + attribute \src "libresoc.v:151489.19-151489.119" + wire $eq$libresoc.v:151489$7522_Y + attribute \src "libresoc.v:151490.19-151490.128" + wire $eq$libresoc.v:151490$7523_Y + attribute \src "libresoc.v:151506.18-151506.114" + wire $eq$libresoc.v:151506$7544_Y + attribute \src "libresoc.v:151507.18-151507.114" + wire $eq$libresoc.v:151507$7545_Y + attribute \src "libresoc.v:151508.18-151508.114" + wire $eq$libresoc.v:151508$7546_Y + attribute \src "libresoc.v:151509.18-151509.114" + wire $eq$libresoc.v:151509$7547_Y + attribute \src "libresoc.v:151510.18-151510.114" + wire $eq$libresoc.v:151510$7548_Y + attribute \src "libresoc.v:151511.18-151511.114" + wire $eq$libresoc.v:151511$7549_Y + attribute \src "libresoc.v:151512.18-151512.114" + wire $eq$libresoc.v:151512$7550_Y + attribute \src "libresoc.v:151513.18-151513.114" + wire $eq$libresoc.v:151513$7551_Y + attribute \src "libresoc.v:151514.18-151514.116" + wire $eq$libresoc.v:151514$7552_Y + attribute \src "libresoc.v:151515.18-151515.116" + wire $eq$libresoc.v:151515$7553_Y + attribute \src "libresoc.v:151516.18-151516.116" + wire $eq$libresoc.v:151516$7554_Y + attribute \src "libresoc.v:151517.18-151517.116" + wire $eq$libresoc.v:151517$7555_Y + attribute \src "libresoc.v:151518.18-151518.116" + wire $eq$libresoc.v:151518$7556_Y + attribute \src "libresoc.v:151519.18-151519.116" + wire $eq$libresoc.v:151519$7557_Y + attribute \src "libresoc.v:151520.18-151520.116" + wire $eq$libresoc.v:151520$7558_Y + attribute \src "libresoc.v:151521.18-151521.116" + wire $eq$libresoc.v:151521$7559_Y + attribute \src "libresoc.v:151522.18-151522.118" + wire $eq$libresoc.v:151522$7560_Y + attribute \src "libresoc.v:151523.18-151523.118" + wire $eq$libresoc.v:151523$7561_Y + attribute \src "libresoc.v:151524.18-151524.118" + wire $eq$libresoc.v:151524$7562_Y + attribute \src "libresoc.v:151525.18-151525.118" + wire $eq$libresoc.v:151525$7563_Y + attribute \src "libresoc.v:151526.18-151526.118" + wire $eq$libresoc.v:151526$7564_Y + attribute \src "libresoc.v:151527.18-151527.118" + wire $eq$libresoc.v:151527$7565_Y + attribute \src "libresoc.v:151528.18-151528.118" + wire $eq$libresoc.v:151528$7566_Y + attribute \src "libresoc.v:151529.18-151529.118" + wire $eq$libresoc.v:151529$7567_Y + attribute \src "libresoc.v:151530.18-151530.118" + wire $eq$libresoc.v:151530$7568_Y + attribute \src "libresoc.v:151531.18-151531.118" + wire $eq$libresoc.v:151531$7569_Y + attribute \src "libresoc.v:151532.18-151532.118" + wire $eq$libresoc.v:151532$7570_Y + attribute \src "libresoc.v:151533.18-151533.118" + wire $eq$libresoc.v:151533$7571_Y + attribute \src "libresoc.v:151534.18-151534.118" + wire $eq$libresoc.v:151534$7572_Y + attribute \src "libresoc.v:151535.18-151535.118" + wire $eq$libresoc.v:151535$7573_Y + attribute \src "libresoc.v:151536.18-151536.118" + wire $eq$libresoc.v:151536$7574_Y + attribute \src "libresoc.v:151537.18-151537.118" + wire $eq$libresoc.v:151537$7575_Y + attribute \src "libresoc.v:151538.18-151538.118" + wire $eq$libresoc.v:151538$7576_Y + attribute \src "libresoc.v:151539.18-151539.118" + wire $eq$libresoc.v:151539$7577_Y + attribute \src "libresoc.v:151540.18-151540.118" + wire $eq$libresoc.v:151540$7578_Y + attribute \src "libresoc.v:151541.18-151541.118" + wire $eq$libresoc.v:151541$7579_Y + attribute \src "libresoc.v:151492.19-151492.104" + wire width 64 $extend$libresoc.v:151492$7525_Y + attribute \src "libresoc.v:151494.19-151494.93" + wire width 8 $extend$libresoc.v:151494$7528_Y + attribute \src "libresoc.v:151496.19-151496.105" + wire width 64 $extend$libresoc.v:151496$7531_Y + attribute \src "libresoc.v:151497.19-151497.118" + wire width 64 $extend$libresoc.v:151497$7533_Y + attribute \src "libresoc.v:151501.19-151501.105" + wire width 64 $extend$libresoc.v:151501$7538_Y + attribute \src "libresoc.v:151504.18-151504.103" + wire width 64 $or$libresoc.v:151504$7542_Y + attribute \src "libresoc.v:151492.19-151492.104" + wire width 64 $pos$libresoc.v:151492$7526_Y + attribute \src "libresoc.v:151494.19-151494.93" + wire width 8 $pos$libresoc.v:151494$7529_Y + attribute \src "libresoc.v:151496.19-151496.105" + wire width 64 $pos$libresoc.v:151496$7532_Y + attribute \src "libresoc.v:151497.19-151497.118" + wire width 64 $pos$libresoc.v:151497$7534_Y + attribute \src "libresoc.v:151501.19-151501.105" + wire width 64 $pos$libresoc.v:151501$7539_Y + attribute \src "libresoc.v:151498.19-151498.131" + wire $reduce_xor$libresoc.v:151498$7535_Y + attribute \src "libresoc.v:151499.19-151499.133" + wire $reduce_xor$libresoc.v:151499$7536_Y + attribute \src "libresoc.v:151493.19-151493.112" + wire width 8 $sub$libresoc.v:151493$7527_Y + attribute \src "libresoc.v:151495.19-151495.135" + wire width 8 $ternary$libresoc.v:151495$7530_Y + attribute \src "libresoc.v:151500.19-151500.398" + wire width 32 $ternary$libresoc.v:151500$7537_Y + attribute \src "libresoc.v:151502.19-151502.621" + wire width 64 $ternary$libresoc.v:151502$7540_Y + attribute \src "libresoc.v:151491.19-151491.108" + wire $xor$libresoc.v:151491$7524_Y + attribute \src "libresoc.v:151505.18-151505.103" + wire width 64 $xor$libresoc.v:151505$7543_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" @@ -310299,7 +281402,7 @@ module \main$51 wire width 64 \cntz_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:99" wire \count_right - attribute \src "libresoc.v:150039.7-150039.15" + attribute \src "libresoc.v:150995.7-150995.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len @@ -310588,7 +281691,7 @@ module \main$51 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 43 \xer_so$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" - cell $and $and$libresoc.v:150547$7557 + cell $and $and$libresoc.v:151503$7541 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -310596,10 +281699,10 @@ module \main$51 parameter \Y_WIDTH 64 connect \A \ra connect \B \rb - connect \Y $and$libresoc.v:150547$7557_Y + connect \Y $and$libresoc.v:151503$7541_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150506$7511 + cell $eq $eq$libresoc.v:151462$7495 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -310607,10 +281710,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:150506$7511_Y + connect \Y $eq$libresoc.v:151462$7495_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150507$7512 + cell $eq $eq$libresoc.v:151463$7496 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -310618,10 +281721,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:150507$7512_Y + connect \Y $eq$libresoc.v:151463$7496_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150508$7513 + cell $eq $eq$libresoc.v:151464$7497 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -310629,10 +281732,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:150508$7513_Y + connect \Y $eq$libresoc.v:151464$7497_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150509$7514 + cell $eq $eq$libresoc.v:151465$7498 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -310640,10 +281743,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:150509$7514_Y + connect \Y $eq$libresoc.v:151465$7498_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150510$7515 + cell $eq $eq$libresoc.v:151466$7499 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -310651,10 +281754,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:150510$7515_Y + connect \Y $eq$libresoc.v:151466$7499_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150511$7516 + cell $eq $eq$libresoc.v:151467$7500 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -310662,10 +281765,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:150511$7516_Y + connect \Y $eq$libresoc.v:151467$7500_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150512$7517 + cell $eq $eq$libresoc.v:151468$7501 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -310673,10 +281776,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:150512$7517_Y + connect \Y $eq$libresoc.v:151468$7501_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150513$7518 + cell $eq $eq$libresoc.v:151469$7502 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -310684,10 +281787,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:150513$7518_Y + connect \Y $eq$libresoc.v:151469$7502_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150514$7519 + cell $eq $eq$libresoc.v:151470$7503 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -310695,10 +281798,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:150514$7519_Y + connect \Y $eq$libresoc.v:151470$7503_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150515$7520 + cell $eq $eq$libresoc.v:151471$7504 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -310706,10 +281809,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:150515$7520_Y + connect \Y $eq$libresoc.v:151471$7504_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150516$7521 + cell $eq $eq$libresoc.v:151472$7505 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -310717,10 +281820,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:150516$7521_Y + connect \Y $eq$libresoc.v:151472$7505_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150517$7522 + cell $eq $eq$libresoc.v:151473$7506 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -310728,10 +281831,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [47:40] connect \B \rb [47:40] - connect \Y $eq$libresoc.v:150517$7522_Y + connect \Y $eq$libresoc.v:151473$7506_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150518$7523 + cell $eq $eq$libresoc.v:151474$7507 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -310739,10 +281842,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:150518$7523_Y + connect \Y $eq$libresoc.v:151474$7507_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150519$7524 + cell $eq $eq$libresoc.v:151475$7508 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -310750,10 +281853,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:150519$7524_Y + connect \Y $eq$libresoc.v:151475$7508_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150520$7525 + cell $eq $eq$libresoc.v:151476$7509 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -310761,10 +281864,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:150520$7525_Y + connect \Y $eq$libresoc.v:151476$7509_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150521$7526 + cell $eq $eq$libresoc.v:151477$7510 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -310772,10 +281875,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:150521$7526_Y + connect \Y $eq$libresoc.v:151477$7510_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150522$7527 + cell $eq $eq$libresoc.v:151478$7511 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -310783,10 +281886,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:150522$7527_Y + connect \Y $eq$libresoc.v:151478$7511_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150523$7528 + cell $eq $eq$libresoc.v:151479$7512 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -310794,10 +281897,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:150523$7528_Y + connect \Y $eq$libresoc.v:151479$7512_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150524$7529 + cell $eq $eq$libresoc.v:151480$7513 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -310805,10 +281908,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:150524$7529_Y + connect \Y $eq$libresoc.v:151480$7513_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150525$7530 + cell $eq $eq$libresoc.v:151481$7514 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -310816,10 +281919,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [55:48] connect \B \rb [55:48] - connect \Y $eq$libresoc.v:150525$7530_Y + connect \Y $eq$libresoc.v:151481$7514_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150526$7531 + cell $eq $eq$libresoc.v:151482$7515 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -310827,10 +281930,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:150526$7531_Y + connect \Y $eq$libresoc.v:151482$7515_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150527$7532 + cell $eq $eq$libresoc.v:151483$7516 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -310838,10 +281941,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:150527$7532_Y + connect \Y $eq$libresoc.v:151483$7516_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150528$7533 + cell $eq $eq$libresoc.v:151484$7517 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -310849,10 +281952,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:150528$7533_Y + connect \Y $eq$libresoc.v:151484$7517_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150529$7534 + cell $eq $eq$libresoc.v:151485$7518 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -310860,10 +281963,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:150529$7534_Y + connect \Y $eq$libresoc.v:151485$7518_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150530$7535 + cell $eq $eq$libresoc.v:151486$7519 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -310871,10 +281974,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:150530$7535_Y + connect \Y $eq$libresoc.v:151486$7519_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150531$7536 + cell $eq $eq$libresoc.v:151487$7520 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -310882,10 +281985,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:150531$7536_Y + connect \Y $eq$libresoc.v:151487$7520_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150532$7537 + cell $eq $eq$libresoc.v:151488$7521 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -310893,10 +281996,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:150532$7537_Y + connect \Y $eq$libresoc.v:151488$7521_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150533$7538 + cell $eq $eq$libresoc.v:151489$7522 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -310904,10 +282007,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [63:56] connect \B \rb [63:56] - connect \Y $eq$libresoc.v:150533$7538_Y + connect \Y $eq$libresoc.v:151489$7522_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" - cell $eq $eq$libresoc.v:150534$7539 + cell $eq $eq$libresoc.v:151490$7523 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -310915,10 +282018,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \logical_op__data_len [3] connect \B 1'1 - connect \Y $eq$libresoc.v:150534$7539_Y + connect \Y $eq$libresoc.v:151490$7523_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150550$7560 + cell $eq $eq$libresoc.v:151506$7544 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -310926,10 +282029,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:150550$7560_Y + connect \Y $eq$libresoc.v:151506$7544_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150551$7561 + cell $eq $eq$libresoc.v:151507$7545 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -310937,10 +282040,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:150551$7561_Y + connect \Y $eq$libresoc.v:151507$7545_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150552$7562 + cell $eq $eq$libresoc.v:151508$7546 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -310948,10 +282051,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:150552$7562_Y + connect \Y $eq$libresoc.v:151508$7546_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150553$7563 + cell $eq $eq$libresoc.v:151509$7547 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -310959,10 +282062,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:150553$7563_Y + connect \Y $eq$libresoc.v:151509$7547_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150554$7564 + cell $eq $eq$libresoc.v:151510$7548 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -310970,10 +282073,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:150554$7564_Y + connect \Y $eq$libresoc.v:151510$7548_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150555$7565 + cell $eq $eq$libresoc.v:151511$7549 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -310981,10 +282084,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:150555$7565_Y + connect \Y $eq$libresoc.v:151511$7549_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150556$7566 + cell $eq $eq$libresoc.v:151512$7550 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -310992,10 +282095,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:150556$7566_Y + connect \Y $eq$libresoc.v:151512$7550_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150557$7567 + cell $eq $eq$libresoc.v:151513$7551 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311003,10 +282106,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [7:0] connect \B \rb [7:0] - connect \Y $eq$libresoc.v:150557$7567_Y + connect \Y $eq$libresoc.v:151513$7551_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150558$7568 + cell $eq $eq$libresoc.v:151514$7552 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311014,10 +282117,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:150558$7568_Y + connect \Y $eq$libresoc.v:151514$7552_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150559$7569 + cell $eq $eq$libresoc.v:151515$7553 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311025,10 +282128,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:150559$7569_Y + connect \Y $eq$libresoc.v:151515$7553_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150560$7570 + cell $eq $eq$libresoc.v:151516$7554 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311036,10 +282139,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:150560$7570_Y + connect \Y $eq$libresoc.v:151516$7554_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150561$7571 + cell $eq $eq$libresoc.v:151517$7555 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311047,10 +282150,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:150561$7571_Y + connect \Y $eq$libresoc.v:151517$7555_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150562$7572 + cell $eq $eq$libresoc.v:151518$7556 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311058,10 +282161,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:150562$7572_Y + connect \Y $eq$libresoc.v:151518$7556_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150563$7573 + cell $eq $eq$libresoc.v:151519$7557 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311069,10 +282172,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:150563$7573_Y + connect \Y $eq$libresoc.v:151519$7557_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150564$7574 + cell $eq $eq$libresoc.v:151520$7558 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311080,10 +282183,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:150564$7574_Y + connect \Y $eq$libresoc.v:151520$7558_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150565$7575 + cell $eq $eq$libresoc.v:151521$7559 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311091,10 +282194,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [15:8] connect \B \rb [15:8] - connect \Y $eq$libresoc.v:150565$7575_Y + connect \Y $eq$libresoc.v:151521$7559_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150566$7576 + cell $eq $eq$libresoc.v:151522$7560 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311102,10 +282205,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:150566$7576_Y + connect \Y $eq$libresoc.v:151522$7560_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150567$7577 + cell $eq $eq$libresoc.v:151523$7561 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311113,10 +282216,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:150567$7577_Y + connect \Y $eq$libresoc.v:151523$7561_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150568$7578 + cell $eq $eq$libresoc.v:151524$7562 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311124,10 +282227,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:150568$7578_Y + connect \Y $eq$libresoc.v:151524$7562_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150569$7579 + cell $eq $eq$libresoc.v:151525$7563 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311135,10 +282238,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:150569$7579_Y + connect \Y $eq$libresoc.v:151525$7563_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150570$7580 + cell $eq $eq$libresoc.v:151526$7564 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311146,10 +282249,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:150570$7580_Y + connect \Y $eq$libresoc.v:151526$7564_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150571$7581 + cell $eq $eq$libresoc.v:151527$7565 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311157,10 +282260,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:150571$7581_Y + connect \Y $eq$libresoc.v:151527$7565_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150572$7582 + cell $eq $eq$libresoc.v:151528$7566 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311168,10 +282271,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:150572$7582_Y + connect \Y $eq$libresoc.v:151528$7566_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150573$7583 + cell $eq $eq$libresoc.v:151529$7567 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311179,10 +282282,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [23:16] connect \B \rb [23:16] - connect \Y $eq$libresoc.v:150573$7583_Y + connect \Y $eq$libresoc.v:151529$7567_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150574$7584 + cell $eq $eq$libresoc.v:151530$7568 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311190,10 +282293,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:150574$7584_Y + connect \Y $eq$libresoc.v:151530$7568_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150575$7585 + cell $eq $eq$libresoc.v:151531$7569 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311201,10 +282304,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:150575$7585_Y + connect \Y $eq$libresoc.v:151531$7569_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150576$7586 + cell $eq $eq$libresoc.v:151532$7570 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311212,10 +282315,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:150576$7586_Y + connect \Y $eq$libresoc.v:151532$7570_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150577$7587 + cell $eq $eq$libresoc.v:151533$7571 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311223,10 +282326,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:150577$7587_Y + connect \Y $eq$libresoc.v:151533$7571_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150578$7588 + cell $eq $eq$libresoc.v:151534$7572 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311234,10 +282337,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:150578$7588_Y + connect \Y $eq$libresoc.v:151534$7572_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150579$7589 + cell $eq $eq$libresoc.v:151535$7573 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311245,10 +282348,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:150579$7589_Y + connect \Y $eq$libresoc.v:151535$7573_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150580$7590 + cell $eq $eq$libresoc.v:151536$7574 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311256,10 +282359,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:150580$7590_Y + connect \Y $eq$libresoc.v:151536$7574_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150581$7591 + cell $eq $eq$libresoc.v:151537$7575 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311267,10 +282370,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [31:24] connect \B \rb [31:24] - connect \Y $eq$libresoc.v:150581$7591_Y + connect \Y $eq$libresoc.v:151537$7575_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150582$7592 + cell $eq $eq$libresoc.v:151538$7576 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311278,10 +282381,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:150582$7592_Y + connect \Y $eq$libresoc.v:151538$7576_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150583$7593 + cell $eq $eq$libresoc.v:151539$7577 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311289,10 +282392,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:150583$7593_Y + connect \Y $eq$libresoc.v:151539$7577_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150584$7594 + cell $eq $eq$libresoc.v:151540$7578 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311300,10 +282403,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:150584$7594_Y + connect \Y $eq$libresoc.v:151540$7578_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $eq$libresoc.v:150585$7595 + cell $eq $eq$libresoc.v:151541$7579 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -311311,50 +282414,50 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \ra [39:32] connect \B \rb [39:32] - connect \Y $eq$libresoc.v:150585$7595_Y + connect \Y $eq$libresoc.v:151541$7579_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - cell $pos $extend$libresoc.v:150536$7541 + cell $pos $extend$libresoc.v:151492$7525 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 64 connect \A \$158 - connect \Y $extend$libresoc.v:150536$7541_Y + connect \Y $extend$libresoc.v:151492$7525_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" - cell $pos $extend$libresoc.v:150538$7544 + cell $pos $extend$libresoc.v:151494$7528 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 8 connect \A \clz_lz - connect \Y $extend$libresoc.v:150538$7544_Y + connect \Y $extend$libresoc.v:151494$7528_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $pos $extend$libresoc.v:150540$7547 + cell $pos $extend$libresoc.v:151496$7531 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 64 connect \A \$166 - connect \Y $extend$libresoc.v:150540$7547_Y + connect \Y $extend$libresoc.v:151496$7531_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $extend$libresoc.v:150541$7549 + cell $pos $extend$libresoc.v:151497$7533 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 64 connect \A \logical_op__data_len - connect \Y $extend$libresoc.v:150541$7549_Y + connect \Y $extend$libresoc.v:151497$7533_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - cell $pos $extend$libresoc.v:150545$7554 + cell $pos $extend$libresoc.v:151501$7538 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \$176 - connect \Y $extend$libresoc.v:150545$7554_Y + connect \Y $extend$libresoc.v:151501$7538_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" - cell $or $or$libresoc.v:150548$7558 + cell $or $or$libresoc.v:151504$7542 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -311362,66 +282465,66 @@ module \main$51 parameter \Y_WIDTH 64 connect \A \ra connect \B \rb - connect \Y $or$libresoc.v:150548$7558_Y + connect \Y $or$libresoc.v:151504$7542_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - cell $pos $pos$libresoc.v:150536$7542 + cell $pos $pos$libresoc.v:151492$7526 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:150536$7541_Y - connect \Y $pos$libresoc.v:150536$7542_Y + connect \A $extend$libresoc.v:151492$7525_Y + connect \Y $pos$libresoc.v:151492$7526_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:18" - cell $pos $pos$libresoc.v:150538$7545 + cell $pos $pos$libresoc.v:151494$7529 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:150538$7544_Y - connect \Y $pos$libresoc.v:150538$7545_Y + connect \A $extend$libresoc.v:151494$7528_Y + connect \Y $pos$libresoc.v:151494$7529_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $pos $pos$libresoc.v:150540$7548 + cell $pos $pos$libresoc.v:151496$7532 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:150540$7547_Y - connect \Y $pos$libresoc.v:150540$7548_Y + connect \A $extend$libresoc.v:151496$7531_Y + connect \Y $pos$libresoc.v:151496$7532_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $pos$libresoc.v:150541$7550 + cell $pos $pos$libresoc.v:151497$7534 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:150541$7549_Y - connect \Y $pos$libresoc.v:150541$7550_Y + connect \A $extend$libresoc.v:151497$7533_Y + connect \Y $pos$libresoc.v:151497$7534_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - cell $pos $pos$libresoc.v:150545$7555 + cell $pos $pos$libresoc.v:151501$7539 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:150545$7554_Y - connect \Y $pos$libresoc.v:150545$7555_Y + connect \A $extend$libresoc.v:151501$7538_Y + connect \Y $pos$libresoc.v:151501$7539_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86" - cell $reduce_xor $reduce_xor$libresoc.v:150542$7551 + cell $reduce_xor $reduce_xor$libresoc.v:151498$7535 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \ra [24] \ra [16] \ra [8] \ra [0] } - connect \Y $reduce_xor$libresoc.v:150542$7551_Y + connect \Y $reduce_xor$libresoc.v:151498$7535_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87" - cell $reduce_xor $reduce_xor$libresoc.v:150543$7552 + cell $reduce_xor $reduce_xor$libresoc.v:151499$7536 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \ra [56] \ra [48] \ra [40] \ra [32] } - connect \Y $reduce_xor$libresoc.v:150543$7552_Y + connect \Y $reduce_xor$libresoc.v:151499$7536_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $sub $sub$libresoc.v:150537$7543 + cell $sub $sub$libresoc.v:151493$7527 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -311429,34 +282532,34 @@ module \main$51 parameter \Y_WIDTH 8 connect \A \clz_lz connect \B 6'100000 - connect \Y $sub$libresoc.v:150537$7543_Y + connect \Y $sub$libresoc.v:151493$7527_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $mux $ternary$libresoc.v:150539$7546 + cell $mux $ternary$libresoc.v:151495$7530 parameter \WIDTH 8 connect \A \$164 connect \B \$162 connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:150539$7546_Y + connect \Y $ternary$libresoc.v:151495$7530_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - cell $mux $ternary$libresoc.v:150544$7553 + cell $mux $ternary$libresoc.v:151500$7537 parameter \WIDTH 32 connect \A \a32 connect \B { \a32 [0] \a32 [1] \a32 [2] \a32 [3] \a32 [4] \a32 [5] \a32 [6] \a32 [7] \a32 [8] \a32 [9] \a32 [10] \a32 [11] \a32 [12] \a32 [13] \a32 [14] \a32 [15] \a32 [16] \a32 [17] \a32 [18] \a32 [19] \a32 [20] \a32 [21] \a32 [22] \a32 [23] \a32 [24] \a32 [25] \a32 [26] \a32 [27] \a32 [28] \a32 [29] \a32 [30] \a32 [31] } connect \S \count_right - connect \Y $ternary$libresoc.v:150544$7553_Y + connect \Y $ternary$libresoc.v:151500$7537_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:109" - cell $mux $ternary$libresoc.v:150546$7556 + cell $mux $ternary$libresoc.v:151502$7540 parameter \WIDTH 64 connect \A \ra connect \B { \ra [0] \ra [1] \ra [2] \ra [3] \ra [4] \ra [5] \ra [6] \ra [7] \ra [8] \ra [9] \ra [10] \ra [11] \ra [12] \ra [13] \ra [14] \ra [15] \ra [16] \ra [17] \ra [18] \ra [19] \ra [20] \ra [21] \ra [22] \ra [23] \ra [24] \ra [25] \ra [26] \ra [27] \ra [28] \ra [29] \ra [30] \ra [31] \ra [32] \ra [33] \ra [34] \ra [35] \ra [36] \ra [37] \ra [38] \ra [39] \ra [40] \ra [41] \ra [42] \ra [43] \ra [44] \ra [45] \ra [46] \ra [47] \ra [48] \ra [49] \ra [50] \ra [51] \ra [52] \ra [53] \ra [54] \ra [55] \ra [56] \ra [57] \ra [58] \ra [59] \ra [60] \ra [61] \ra [62] \ra [63] } connect \S \count_right - connect \Y $ternary$libresoc.v:150546$7556_Y + connect \Y $ternary$libresoc.v:151502$7540_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - cell $xor $xor$libresoc.v:150535$7540 + cell $xor $xor$libresoc.v:151491$7524 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -311464,10 +282567,10 @@ module \main$51 parameter \Y_WIDTH 1 connect \A \par0 connect \B \par1 - connect \Y $xor$libresoc.v:150535$7540_Y + connect \Y $xor$libresoc.v:151491$7524_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58" - cell $xor $xor$libresoc.v:150549$7559 + cell $xor $xor$libresoc.v:151505$7543 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -311475,47 +282578,47 @@ module \main$51 parameter \Y_WIDTH 64 connect \A \ra connect \B \rb - connect \Y $xor$libresoc.v:150549$7559_Y + connect \Y $xor$libresoc.v:151505$7543_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:150586.10-150590.4" + attribute \src "libresoc.v:151542.10-151546.4" cell \bpermd \bpermd connect \ra \bpermd_ra connect \rb \bpermd_rb connect \rs \bpermd_rs end attribute \module_not_derived 1 - attribute \src "libresoc.v:150591.7-150594.4" + attribute \src "libresoc.v:151547.7-151550.4" cell \clz \clz connect \lz \clz_lz connect \sig_in \clz_sig_in end attribute \module_not_derived 1 - attribute \src "libresoc.v:150595.12-150599.4" + attribute \src "libresoc.v:151551.12-151555.4" cell \popcount \popcount connect \a \popcount_a connect \data_len \popcount_data_len connect \o \popcount_o end - attribute \src "libresoc.v:150039.7-150039.20" - process $proc$libresoc.v:150039$7608 + attribute \src "libresoc.v:150995.7-150995.20" + process $proc$libresoc.v:150995$7592 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:150600.3-150654.6" - process $proc$libresoc.v:150600$7596 + attribute \src "libresoc.v:151556.3-151610.6" + process $proc$libresoc.v:151556$7580 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:150601.5-150601.29" + attribute \src "libresoc.v:151557.5-151557.29" switch \initial - attribute \src "libresoc.v:150601.9-150601.17" + attribute \src "libresoc.v:151557.9-151557.17" case 1'1 case end @@ -311583,20 +282686,38 @@ module \main$51 update \o_ok $0\o_ok[0:0] update \o $0\o[63:0] end - attribute \src "libresoc.v:150655.3-150665.6" - process $proc$libresoc.v:150655$7597 + attribute \src "libresoc.v:151611.3-151645.6" + process $proc$libresoc.v:151611$7581 assign { } { } assign { } { } assign $0\clz_sig_in[63:0] $1\clz_sig_in[63:0] - attribute \src "libresoc.v:150656.5-150656.29" + attribute \src "libresoc.v:151612.5-151612.29" switch \initial - attribute \src "libresoc.v:150656.9-150656.17" + attribute \src "libresoc.v:151612.9-151612.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0000100 + assign $1\clz_sig_in[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110101 + assign $1\clz_sig_in[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000011 + assign $1\clz_sig_in[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001011 + assign $1\clz_sig_in[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110110 + assign $1\clz_sig_in[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110111 + assign $1\clz_sig_in[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 7'0001110 assign { } { } assign $1\clz_sig_in[63:0] \cntz_i @@ -311606,20 +282727,41 @@ module \main$51 sync always update \clz_sig_in $0\clz_sig_in[63:0] end - attribute \src "libresoc.v:150666.3-150676.6" - process $proc$libresoc.v:150666$7598 + attribute \src "libresoc.v:151646.3-151684.6" + process $proc$libresoc.v:151646$7582 assign { } { } assign { } { } assign $0\bpermd_rs[63:0] $1\bpermd_rs[63:0] - attribute \src "libresoc.v:150667.5-150667.29" + attribute \src "libresoc.v:151647.5-151647.29" switch \initial - attribute \src "libresoc.v:150667.9-150667.17" + attribute \src "libresoc.v:151647.9-151647.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0000100 + assign $1\bpermd_rs[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110101 + assign $1\bpermd_rs[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000011 + assign $1\bpermd_rs[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001011 + assign $1\bpermd_rs[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110110 + assign $1\bpermd_rs[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110111 + assign $1\bpermd_rs[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001110 + assign $1\bpermd_rs[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 7'0001001 assign { } { } assign $1\bpermd_rs[63:0] \ra @@ -311629,20 +282771,41 @@ module \main$51 sync always update \bpermd_rs $0\bpermd_rs[63:0] end - attribute \src "libresoc.v:150677.3-150687.6" - process $proc$libresoc.v:150677$7599 + attribute \src "libresoc.v:151685.3-151723.6" + process $proc$libresoc.v:151685$7583 assign { } { } assign { } { } assign $0\bpermd_rb[63:0] $1\bpermd_rb[63:0] - attribute \src "libresoc.v:150678.5-150678.29" + attribute \src "libresoc.v:151686.5-151686.29" switch \initial - attribute \src "libresoc.v:150678.9-150678.17" + attribute \src "libresoc.v:151686.9-151686.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0000100 + assign $1\bpermd_rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110101 + assign $1\bpermd_rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000011 + assign $1\bpermd_rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001011 + assign $1\bpermd_rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110110 + assign $1\bpermd_rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110111 + assign $1\bpermd_rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001110 + assign $1\bpermd_rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 7'0001001 assign { } { } assign $1\bpermd_rb[63:0] \rb @@ -311652,20 +282815,32 @@ module \main$51 sync always update \bpermd_rb $0\bpermd_rb[63:0] end - attribute \src "libresoc.v:150688.3-150698.6" - process $proc$libresoc.v:150688$7600 + attribute \src "libresoc.v:151724.3-151750.6" + process $proc$libresoc.v:151724$7584 assign { } { } assign { } { } assign $0\popcount_a[63:0] $1\popcount_a[63:0] - attribute \src "libresoc.v:150689.5-150689.29" + attribute \src "libresoc.v:151725.5-151725.29" switch \initial - attribute \src "libresoc.v:150689.9-150689.17" + attribute \src "libresoc.v:151725.9-151725.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0000100 + assign $1\popcount_a[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110101 + assign $1\popcount_a[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000011 + assign $1\popcount_a[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001011 + assign $1\popcount_a[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 7'0110110 assign { } { } assign $1\popcount_a[63:0] \ra @@ -311675,20 +282850,32 @@ module \main$51 sync always update \popcount_a $0\popcount_a[63:0] end - attribute \src "libresoc.v:150699.3-150709.6" - process $proc$libresoc.v:150699$7601 + attribute \src "libresoc.v:151751.3-151777.6" + process $proc$libresoc.v:151751$7585 assign { } { } assign { } { } assign $0\b[63:0] $1\b[63:0] - attribute \src "libresoc.v:150700.5-150700.29" + attribute \src "libresoc.v:151752.5-151752.29" switch \initial - attribute \src "libresoc.v:150700.9-150700.17" + attribute \src "libresoc.v:151752.9-151752.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0000100 + assign $1\b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110101 + assign $1\b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000011 + assign $1\b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001011 + assign $1\b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 7'0110110 assign { } { } assign $1\b[63:0] \rb @@ -311698,20 +282885,32 @@ module \main$51 sync always update \b $0\b[63:0] end - attribute \src "libresoc.v:150710.3-150720.6" - process $proc$libresoc.v:150710$7602 + attribute \src "libresoc.v:151778.3-151804.6" + process $proc$libresoc.v:151778$7586 assign { } { } assign { } { } assign $0\popcount_data_len[63:0] $1\popcount_data_len[63:0] - attribute \src "libresoc.v:150711.5-150711.29" + attribute \src "libresoc.v:151779.5-151779.29" switch \initial - attribute \src "libresoc.v:150711.9-150711.17" + attribute \src "libresoc.v:151779.9-151779.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0000100 + assign $1\popcount_data_len[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110101 + assign $1\popcount_data_len[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000011 + assign $1\popcount_data_len[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001011 + assign $1\popcount_data_len[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 7'0110110 assign { } { } assign $1\popcount_data_len[63:0] \$169 @@ -311721,20 +282920,35 @@ module \main$51 sync always update \popcount_data_len $0\popcount_data_len[63:0] end - attribute \src "libresoc.v:150721.3-150731.6" - process $proc$libresoc.v:150721$7603 + attribute \src "libresoc.v:151805.3-151835.6" + process $proc$libresoc.v:151805$7587 assign { } { } assign { } { } assign $0\par0[0:0] $1\par0[0:0] - attribute \src "libresoc.v:150722.5-150722.29" + attribute \src "libresoc.v:151806.5-151806.29" switch \initial - attribute \src "libresoc.v:150722.9-150722.17" + attribute \src "libresoc.v:151806.9-151806.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0000100 + assign $1\par0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110101 + assign $1\par0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000011 + assign $1\par0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001011 + assign $1\par0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110110 + assign $1\par0[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 7'0110111 assign { } { } assign $1\par0[0:0] \$171 @@ -311744,20 +282958,35 @@ module \main$51 sync always update \par0 $0\par0[0:0] end - attribute \src "libresoc.v:150732.3-150742.6" - process $proc$libresoc.v:150732$7604 + attribute \src "libresoc.v:151836.3-151866.6" + process $proc$libresoc.v:151836$7588 assign { } { } assign { } { } assign $0\par1[0:0] $1\par1[0:0] - attribute \src "libresoc.v:150733.5-150733.29" + attribute \src "libresoc.v:151837.5-151837.29" switch \initial - attribute \src "libresoc.v:150733.9-150733.17" + attribute \src "libresoc.v:151837.9-151837.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0000100 + assign $1\par1[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110101 + assign $1\par1[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000011 + assign $1\par1[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001011 + assign $1\par1[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110110 + assign $1\par1[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 7'0110111 assign { } { } assign $1\par1[0:0] \$173 @@ -311767,20 +282996,38 @@ module \main$51 sync always update \par1 $0\par1[0:0] end - attribute \src "libresoc.v:150743.3-150753.6" - process $proc$libresoc.v:150743$7605 + attribute \src "libresoc.v:151867.3-151901.6" + process $proc$libresoc.v:151867$7589 assign { } { } assign { } { } assign $0\count_right[0:0] $1\count_right[0:0] - attribute \src "libresoc.v:150744.5-150744.29" + attribute \src "libresoc.v:151868.5-151868.29" switch \initial - attribute \src "libresoc.v:150744.9-150744.17" + attribute \src "libresoc.v:151868.9-151868.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0000100 + assign $1\count_right[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110101 + assign $1\count_right[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000011 + assign $1\count_right[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001011 + assign $1\count_right[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110110 + assign $1\count_right[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110111 + assign $1\count_right[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 7'0001110 assign { } { } assign $1\count_right[0:0] \logical_op__insn [10] @@ -311790,20 +283037,38 @@ module \main$51 sync always update \count_right $0\count_right[0:0] end - attribute \src "libresoc.v:150754.3-150764.6" - process $proc$libresoc.v:150754$7606 + attribute \src "libresoc.v:151902.3-151936.6" + process $proc$libresoc.v:151902$7590 assign { } { } assign { } { } assign $0\a32[31:0] $1\a32[31:0] - attribute \src "libresoc.v:150755.5-150755.29" + attribute \src "libresoc.v:151903.5-151903.29" switch \initial - attribute \src "libresoc.v:150755.9-150755.17" + attribute \src "libresoc.v:151903.9-151903.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0000100 + assign $1\a32[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110101 + assign $1\a32[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000011 + assign $1\a32[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001011 + assign $1\a32[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110110 + assign $1\a32[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110111 + assign $1\a32[31:0] 0 + attribute \src "libresoc.v:0.0-0.0" case 7'0001110 assign { } { } assign $1\a32[31:0] \ra [31:0] @@ -311813,20 +283078,38 @@ module \main$51 sync always update \a32 $0\a32[31:0] end - attribute \src "libresoc.v:150765.3-150783.6" - process $proc$libresoc.v:150765$7607 + attribute \src "libresoc.v:151937.3-151979.6" + process $proc$libresoc.v:151937$7591 assign { } { } assign { } { } assign $0\cntz_i[63:0] $1\cntz_i[63:0] - attribute \src "libresoc.v:150766.5-150766.29" + attribute \src "libresoc.v:151938.5-151938.29" switch \initial - attribute \src "libresoc.v:150766.9-150766.17" + attribute \src "libresoc.v:151938.9-151938.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" switch \logical_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0000100 + assign $1\cntz_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110101 + assign $1\cntz_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000011 + assign $1\cntz_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0001011 + assign $1\cntz_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110110 + assign $1\cntz_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110111 + assign $1\cntz_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 7'0001110 assign { } { } assign $1\cntz_i[63:0] $2\cntz_i[63:0] @@ -311847,193 +283130,193 @@ module \main$51 sync always update \cntz_i $0\cntz_i[63:0] end - connect \$99 $eq$libresoc.v:150506$7511_Y - connect \$101 $eq$libresoc.v:150507$7512_Y - connect \$103 $eq$libresoc.v:150508$7513_Y - connect \$105 $eq$libresoc.v:150509$7514_Y - connect \$107 $eq$libresoc.v:150510$7515_Y - connect \$109 $eq$libresoc.v:150511$7516_Y - connect \$111 $eq$libresoc.v:150512$7517_Y - connect \$113 $eq$libresoc.v:150513$7518_Y - connect \$115 $eq$libresoc.v:150514$7519_Y - connect \$117 $eq$libresoc.v:150515$7520_Y - connect \$119 $eq$libresoc.v:150516$7521_Y - connect \$121 $eq$libresoc.v:150517$7522_Y - connect \$123 $eq$libresoc.v:150518$7523_Y - connect \$125 $eq$libresoc.v:150519$7524_Y - connect \$127 $eq$libresoc.v:150520$7525_Y - connect \$129 $eq$libresoc.v:150521$7526_Y - connect \$131 $eq$libresoc.v:150522$7527_Y - connect \$133 $eq$libresoc.v:150523$7528_Y - connect \$135 $eq$libresoc.v:150524$7529_Y - connect \$137 $eq$libresoc.v:150525$7530_Y - connect \$139 $eq$libresoc.v:150526$7531_Y - connect \$141 $eq$libresoc.v:150527$7532_Y - connect \$143 $eq$libresoc.v:150528$7533_Y - connect \$145 $eq$libresoc.v:150529$7534_Y - connect \$147 $eq$libresoc.v:150530$7535_Y - connect \$149 $eq$libresoc.v:150531$7536_Y - connect \$151 $eq$libresoc.v:150532$7537_Y - connect \$153 $eq$libresoc.v:150533$7538_Y - connect \$155 $eq$libresoc.v:150534$7539_Y - connect \$158 $xor$libresoc.v:150535$7540_Y - connect \$157 $pos$libresoc.v:150536$7542_Y - connect \$162 $sub$libresoc.v:150537$7543_Y - connect \$164 $pos$libresoc.v:150538$7545_Y - connect \$166 $ternary$libresoc.v:150539$7546_Y - connect \$161 $pos$libresoc.v:150540$7548_Y - connect \$169 $pos$libresoc.v:150541$7550_Y - connect \$171 $reduce_xor$libresoc.v:150542$7551_Y - connect \$173 $reduce_xor$libresoc.v:150543$7552_Y - connect \$176 $ternary$libresoc.v:150544$7553_Y - connect \$175 $pos$libresoc.v:150545$7555_Y - connect \$179 $ternary$libresoc.v:150546$7556_Y - connect \$21 $and$libresoc.v:150547$7557_Y - connect \$23 $or$libresoc.v:150548$7558_Y - connect \$25 $xor$libresoc.v:150549$7559_Y - connect \$27 $eq$libresoc.v:150550$7560_Y - connect \$29 $eq$libresoc.v:150551$7561_Y - connect \$31 $eq$libresoc.v:150552$7562_Y - connect \$33 $eq$libresoc.v:150553$7563_Y - connect \$35 $eq$libresoc.v:150554$7564_Y - connect \$37 $eq$libresoc.v:150555$7565_Y - connect \$39 $eq$libresoc.v:150556$7566_Y - connect \$41 $eq$libresoc.v:150557$7567_Y - connect \$43 $eq$libresoc.v:150558$7568_Y - connect \$45 $eq$libresoc.v:150559$7569_Y - connect \$47 $eq$libresoc.v:150560$7570_Y - connect \$49 $eq$libresoc.v:150561$7571_Y - connect \$51 $eq$libresoc.v:150562$7572_Y - connect \$53 $eq$libresoc.v:150563$7573_Y - connect \$55 $eq$libresoc.v:150564$7574_Y - connect \$57 $eq$libresoc.v:150565$7575_Y - connect \$59 $eq$libresoc.v:150566$7576_Y - connect \$61 $eq$libresoc.v:150567$7577_Y - connect \$63 $eq$libresoc.v:150568$7578_Y - connect \$65 $eq$libresoc.v:150569$7579_Y - connect \$67 $eq$libresoc.v:150570$7580_Y - connect \$69 $eq$libresoc.v:150571$7581_Y - connect \$71 $eq$libresoc.v:150572$7582_Y - connect \$73 $eq$libresoc.v:150573$7583_Y - connect \$75 $eq$libresoc.v:150574$7584_Y - connect \$77 $eq$libresoc.v:150575$7585_Y - connect \$79 $eq$libresoc.v:150576$7586_Y - connect \$81 $eq$libresoc.v:150577$7587_Y - connect \$83 $eq$libresoc.v:150578$7588_Y - connect \$85 $eq$libresoc.v:150579$7589_Y - connect \$87 $eq$libresoc.v:150580$7590_Y - connect \$89 $eq$libresoc.v:150581$7591_Y - connect \$91 $eq$libresoc.v:150582$7592_Y - connect \$93 $eq$libresoc.v:150583$7593_Y - connect \$95 $eq$libresoc.v:150584$7594_Y - connect \$97 $eq$libresoc.v:150585$7595_Y + connect \$99 $eq$libresoc.v:151462$7495_Y + connect \$101 $eq$libresoc.v:151463$7496_Y + connect \$103 $eq$libresoc.v:151464$7497_Y + connect \$105 $eq$libresoc.v:151465$7498_Y + connect \$107 $eq$libresoc.v:151466$7499_Y + connect \$109 $eq$libresoc.v:151467$7500_Y + connect \$111 $eq$libresoc.v:151468$7501_Y + connect \$113 $eq$libresoc.v:151469$7502_Y + connect \$115 $eq$libresoc.v:151470$7503_Y + connect \$117 $eq$libresoc.v:151471$7504_Y + connect \$119 $eq$libresoc.v:151472$7505_Y + connect \$121 $eq$libresoc.v:151473$7506_Y + connect \$123 $eq$libresoc.v:151474$7507_Y + connect \$125 $eq$libresoc.v:151475$7508_Y + connect \$127 $eq$libresoc.v:151476$7509_Y + connect \$129 $eq$libresoc.v:151477$7510_Y + connect \$131 $eq$libresoc.v:151478$7511_Y + connect \$133 $eq$libresoc.v:151479$7512_Y + connect \$135 $eq$libresoc.v:151480$7513_Y + connect \$137 $eq$libresoc.v:151481$7514_Y + connect \$139 $eq$libresoc.v:151482$7515_Y + connect \$141 $eq$libresoc.v:151483$7516_Y + connect \$143 $eq$libresoc.v:151484$7517_Y + connect \$145 $eq$libresoc.v:151485$7518_Y + connect \$147 $eq$libresoc.v:151486$7519_Y + connect \$149 $eq$libresoc.v:151487$7520_Y + connect \$151 $eq$libresoc.v:151488$7521_Y + connect \$153 $eq$libresoc.v:151489$7522_Y + connect \$155 $eq$libresoc.v:151490$7523_Y + connect \$158 $xor$libresoc.v:151491$7524_Y + connect \$157 $pos$libresoc.v:151492$7526_Y + connect \$162 $sub$libresoc.v:151493$7527_Y + connect \$164 $pos$libresoc.v:151494$7529_Y + connect \$166 $ternary$libresoc.v:151495$7530_Y + connect \$161 $pos$libresoc.v:151496$7532_Y + connect \$169 $pos$libresoc.v:151497$7534_Y + connect \$171 $reduce_xor$libresoc.v:151498$7535_Y + connect \$173 $reduce_xor$libresoc.v:151499$7536_Y + connect \$176 $ternary$libresoc.v:151500$7537_Y + connect \$175 $pos$libresoc.v:151501$7539_Y + connect \$179 $ternary$libresoc.v:151502$7540_Y + connect \$21 $and$libresoc.v:151503$7541_Y + connect \$23 $or$libresoc.v:151504$7542_Y + connect \$25 $xor$libresoc.v:151505$7543_Y + connect \$27 $eq$libresoc.v:151506$7544_Y + connect \$29 $eq$libresoc.v:151507$7545_Y + connect \$31 $eq$libresoc.v:151508$7546_Y + connect \$33 $eq$libresoc.v:151509$7547_Y + connect \$35 $eq$libresoc.v:151510$7548_Y + connect \$37 $eq$libresoc.v:151511$7549_Y + connect \$39 $eq$libresoc.v:151512$7550_Y + connect \$41 $eq$libresoc.v:151513$7551_Y + connect \$43 $eq$libresoc.v:151514$7552_Y + connect \$45 $eq$libresoc.v:151515$7553_Y + connect \$47 $eq$libresoc.v:151516$7554_Y + connect \$49 $eq$libresoc.v:151517$7555_Y + connect \$51 $eq$libresoc.v:151518$7556_Y + connect \$53 $eq$libresoc.v:151519$7557_Y + connect \$55 $eq$libresoc.v:151520$7558_Y + connect \$57 $eq$libresoc.v:151521$7559_Y + connect \$59 $eq$libresoc.v:151522$7560_Y + connect \$61 $eq$libresoc.v:151523$7561_Y + connect \$63 $eq$libresoc.v:151524$7562_Y + connect \$65 $eq$libresoc.v:151525$7563_Y + connect \$67 $eq$libresoc.v:151526$7564_Y + connect \$69 $eq$libresoc.v:151527$7565_Y + connect \$71 $eq$libresoc.v:151528$7566_Y + connect \$73 $eq$libresoc.v:151529$7567_Y + connect \$75 $eq$libresoc.v:151530$7568_Y + connect \$77 $eq$libresoc.v:151531$7569_Y + connect \$79 $eq$libresoc.v:151532$7570_Y + connect \$81 $eq$libresoc.v:151533$7571_Y + connect \$83 $eq$libresoc.v:151534$7572_Y + connect \$85 $eq$libresoc.v:151535$7573_Y + connect \$87 $eq$libresoc.v:151536$7574_Y + connect \$89 $eq$libresoc.v:151537$7575_Y + connect \$91 $eq$libresoc.v:151538$7576_Y + connect \$93 $eq$libresoc.v:151539$7577_Y + connect \$95 $eq$libresoc.v:151540$7578_Y + connect \$97 $eq$libresoc.v:151541$7579_Y connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid connect \xer_so$20 \xer_so end -attribute \src "libresoc.v:150791.1-151306.10" +attribute \src "libresoc.v:151987.1-152590.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.main" attribute \generator "nMigen" module \main$9 - attribute \src "libresoc.v:151161.3-151171.6" + attribute \src "libresoc.v:152377.3-152403.6" wire width 2 $0\BC[1:0] - attribute \src "libresoc.v:151215.3-151225.6" + attribute \src "libresoc.v:152471.3-152485.6" wire width 2 $0\ba[1:0] - attribute \src "libresoc.v:151226.3-151236.6" + attribute \src "libresoc.v:152486.3-152500.6" wire width 2 $0\bb[1:0] - attribute \src "libresoc.v:151237.3-151257.6" + attribute \src "libresoc.v:152501.3-152525.6" wire $0\bit_a[0:0] - attribute \src "libresoc.v:151258.3-151278.6" + attribute \src "libresoc.v:152526.3-152550.6" wire $0\bit_b[0:0] - attribute \src "libresoc.v:151279.3-151289.6" + attribute \src "libresoc.v:152551.3-152565.6" wire $0\bit_o[0:0] - attribute \src "libresoc.v:151204.3-151214.6" + attribute \src "libresoc.v:152456.3-152470.6" wire width 2 $0\bt[1:0] - attribute \src "libresoc.v:151073.3-151107.6" - wire width 4 $0\cr_a$6[3:0]$7623 - attribute \src "libresoc.v:151073.3-151107.6" + attribute \src "libresoc.v:152269.3-152303.6" + wire width 4 $0\cr_a$6[3:0]$7607 + attribute \src "libresoc.v:152269.3-152303.6" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:151172.3-151192.6" + attribute \src "libresoc.v:152404.3-152440.6" wire $0\cr_bit[0:0] - attribute \src "libresoc.v:151290.3-151300.6" - wire width 32 $0\full_cr$5[31:0]$7638 - attribute \src "libresoc.v:151108.3-151118.6" + attribute \src "libresoc.v:152566.3-152584.6" + wire width 32 $0\full_cr$5[31:0]$7622 + attribute \src "libresoc.v:152304.3-152322.6" wire $0\full_cr_ok[0:0] - attribute \src "libresoc.v:150792.7-150792.20" + attribute \src "libresoc.v:151988.7-151988.20" wire $0\initial[0:0] - attribute \src "libresoc.v:151193.3-151203.6" + attribute \src "libresoc.v:152441.3-152455.6" wire width 4 $0\lut[3:0] - attribute \src "libresoc.v:151119.3-151160.6" + attribute \src "libresoc.v:152323.3-152376.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:151119.3-151160.6" + attribute \src "libresoc.v:152323.3-152376.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:151161.3-151171.6" + attribute \src "libresoc.v:152377.3-152403.6" wire width 2 $1\BC[1:0] - attribute \src "libresoc.v:151215.3-151225.6" + attribute \src "libresoc.v:152471.3-152485.6" wire width 2 $1\ba[1:0] - attribute \src "libresoc.v:151226.3-151236.6" + attribute \src "libresoc.v:152486.3-152500.6" wire width 2 $1\bb[1:0] - attribute \src "libresoc.v:151237.3-151257.6" + attribute \src "libresoc.v:152501.3-152525.6" wire $1\bit_a[0:0] - attribute \src "libresoc.v:151258.3-151278.6" + attribute \src "libresoc.v:152526.3-152550.6" wire $1\bit_b[0:0] - attribute \src "libresoc.v:151279.3-151289.6" + attribute \src "libresoc.v:152551.3-152565.6" wire $1\bit_o[0:0] - attribute \src "libresoc.v:151204.3-151214.6" + attribute \src "libresoc.v:152456.3-152470.6" wire width 2 $1\bt[1:0] - attribute \src "libresoc.v:151073.3-151107.6" - wire width 4 $1\cr_a$6[3:0]$7624 - attribute \src "libresoc.v:151073.3-151107.6" + attribute \src "libresoc.v:152269.3-152303.6" + wire width 4 $1\cr_a$6[3:0]$7608 + attribute \src "libresoc.v:152269.3-152303.6" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:151172.3-151192.6" + attribute \src "libresoc.v:152404.3-152440.6" wire $1\cr_bit[0:0] - attribute \src "libresoc.v:151290.3-151300.6" - wire width 32 $1\full_cr$5[31:0]$7639 - attribute \src "libresoc.v:151108.3-151118.6" + attribute \src "libresoc.v:152566.3-152584.6" + wire width 32 $1\full_cr$5[31:0]$7623 + attribute \src "libresoc.v:152304.3-152322.6" wire $1\full_cr_ok[0:0] - attribute \src "libresoc.v:151193.3-151203.6" + attribute \src "libresoc.v:152441.3-152455.6" wire width 4 $1\lut[3:0] - attribute \src "libresoc.v:151119.3-151160.6" + attribute \src "libresoc.v:152323.3-152376.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:151119.3-151160.6" + attribute \src "libresoc.v:152323.3-152376.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:151237.3-151257.6" + attribute \src "libresoc.v:152501.3-152525.6" wire $2\bit_a[0:0] - attribute \src "libresoc.v:151258.3-151278.6" + attribute \src "libresoc.v:152526.3-152550.6" wire $2\bit_b[0:0] - attribute \src "libresoc.v:151073.3-151107.6" - wire width 4 $2\cr_a$6[3:0]$7625 - attribute \src "libresoc.v:151172.3-151192.6" + attribute \src "libresoc.v:152269.3-152303.6" + wire width 4 $2\cr_a$6[3:0]$7609 + attribute \src "libresoc.v:152404.3-152440.6" wire $2\cr_bit[0:0] - attribute \src "libresoc.v:151119.3-151160.6" + attribute \src "libresoc.v:152323.3-152376.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:151069.18-151069.96" - wire width 64 $extend$libresoc.v:151069$7615_Y - attribute \src "libresoc.v:151071.18-151071.98" - wire width 65 $extend$libresoc.v:151071$7618_Y - attribute \src "libresoc.v:151072.17-151072.92" - wire width 5 $extend$libresoc.v:151072$7620_Y - attribute \src "libresoc.v:151069.18-151069.96" - wire width 64 $pos$libresoc.v:151069$7616_Y - attribute \src "libresoc.v:151071.18-151071.98" - wire width 65 $pos$libresoc.v:151071$7619_Y - attribute \src "libresoc.v:151072.17-151072.92" - wire width 5 $pos$libresoc.v:151072$7621_Y - attribute \src "libresoc.v:151063.18-151063.116" - wire width 3 $sub$libresoc.v:151063$7609_Y - attribute \src "libresoc.v:151064.18-151064.116" - wire width 3 $sub$libresoc.v:151064$7610_Y - attribute \src "libresoc.v:151065.18-151065.116" - wire width 3 $sub$libresoc.v:151065$7611_Y - attribute \src "libresoc.v:151066.18-151066.114" - wire $ternary$libresoc.v:151066$7612_Y - attribute \src "libresoc.v:151067.18-151067.115" - wire $ternary$libresoc.v:151067$7613_Y - attribute \src "libresoc.v:151068.18-151068.112" - wire $ternary$libresoc.v:151068$7614_Y - attribute \src "libresoc.v:151070.18-151070.108" - wire width 64 $ternary$libresoc.v:151070$7617_Y + attribute \src "libresoc.v:152265.18-152265.96" + wire width 64 $extend$libresoc.v:152265$7599_Y + attribute \src "libresoc.v:152267.18-152267.98" + wire width 65 $extend$libresoc.v:152267$7602_Y + attribute \src "libresoc.v:152268.17-152268.92" + wire width 5 $extend$libresoc.v:152268$7604_Y + attribute \src "libresoc.v:152265.18-152265.96" + wire width 64 $pos$libresoc.v:152265$7600_Y + attribute \src "libresoc.v:152267.18-152267.98" + wire width 65 $pos$libresoc.v:152267$7603_Y + attribute \src "libresoc.v:152268.17-152268.92" + wire width 5 $pos$libresoc.v:152268$7605_Y + attribute \src "libresoc.v:152259.18-152259.116" + wire width 3 $sub$libresoc.v:152259$7593_Y + attribute \src "libresoc.v:152260.18-152260.116" + wire width 3 $sub$libresoc.v:152260$7594_Y + attribute \src "libresoc.v:152261.18-152261.116" + wire width 3 $sub$libresoc.v:152261$7595_Y + attribute \src "libresoc.v:152262.18-152262.114" + wire $ternary$libresoc.v:152262$7596_Y + attribute \src "libresoc.v:152263.18-152263.115" + wire $ternary$libresoc.v:152263$7597_Y + attribute \src "libresoc.v:152264.18-152264.112" + wire $ternary$libresoc.v:152264$7598_Y + attribute \src "libresoc.v:152266.18-152266.108" + wire width 64 $ternary$libresoc.v:152266$7601_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" wire width 3 \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" @@ -312284,7 +283567,7 @@ module \main$9 wire width 32 output 16 \full_cr$5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 17 \full_cr_ok - attribute \src "libresoc.v:150792.7-150792.15" + attribute \src "libresoc.v:151988.7-151988.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" wire width 4 \lut @@ -312301,55 +283584,55 @@ module \main$9 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 5 \rb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:151069$7615 + cell $pos $extend$libresoc.v:152265$7599 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \full_cr - connect \Y $extend$libresoc.v:151069$7615_Y + connect \Y $extend$libresoc.v:152265$7599_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" - cell $pos $extend$libresoc.v:151071$7618 + cell $pos $extend$libresoc.v:152267$7602 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \$27 - connect \Y $extend$libresoc.v:151071$7618_Y + connect \Y $extend$libresoc.v:152267$7602_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:151072$7620 + cell $pos $extend$libresoc.v:152268$7604 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 5 connect \A \cr_a - connect \Y $extend$libresoc.v:151072$7620_Y + connect \Y $extend$libresoc.v:152268$7604_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:151069$7616 + cell $pos $pos$libresoc.v:152265$7600 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:151069$7615_Y - connect \Y $pos$libresoc.v:151069$7616_Y + connect \A $extend$libresoc.v:152265$7599_Y + connect \Y $pos$libresoc.v:152265$7600_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" - cell $pos $pos$libresoc.v:151071$7619 + cell $pos $pos$libresoc.v:152267$7603 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:151071$7618_Y - connect \Y $pos$libresoc.v:151071$7619_Y + connect \A $extend$libresoc.v:152267$7602_Y + connect \Y $pos$libresoc.v:152267$7603_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:151072$7621 + cell $pos $pos$libresoc.v:152268$7605 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 - connect \A $extend$libresoc.v:151072$7620_Y - connect \Y $pos$libresoc.v:151072$7621_Y + connect \A $extend$libresoc.v:152268$7604_Y + connect \Y $pos$libresoc.v:152268$7605_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" - cell $sub $sub$libresoc.v:151063$7609 + cell $sub $sub$libresoc.v:152259$7593 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -312357,10 +283640,10 @@ module \main$9 parameter \Y_WIDTH 3 connect \A 2'11 connect \B \cr_op__insn [22:21] - connect \Y $sub$libresoc.v:151063$7609_Y + connect \Y $sub$libresoc.v:152259$7593_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" - cell $sub $sub$libresoc.v:151064$7610 + cell $sub $sub$libresoc.v:152260$7594 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -312368,10 +283651,10 @@ module \main$9 parameter \Y_WIDTH 3 connect \A 2'11 connect \B \cr_op__insn [17:16] - connect \Y $sub$libresoc.v:151064$7610_Y + connect \Y $sub$libresoc.v:152260$7594_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" - cell $sub $sub$libresoc.v:151065$7611 + cell $sub $sub$libresoc.v:152261$7595 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -312379,59 +283662,59 @@ module \main$9 parameter \Y_WIDTH 3 connect \A 2'11 connect \B \cr_op__insn [12:11] - connect \Y $sub$libresoc.v:151065$7611_Y + connect \Y $sub$libresoc.v:152261$7595_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:99" - cell $mux $ternary$libresoc.v:151066$7612 + cell $mux $ternary$libresoc.v:152262$7596 parameter \WIDTH 1 connect \A \lut [1] connect \B \lut [3] connect \S \bit_a - connect \Y $ternary$libresoc.v:151066$7612_Y + connect \Y $ternary$libresoc.v:152262$7596_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" - cell $mux $ternary$libresoc.v:151067$7613 + cell $mux $ternary$libresoc.v:152263$7597 parameter \WIDTH 1 connect \A \lut [0] connect \B \lut [2] connect \S \bit_a - connect \Y $ternary$libresoc.v:151067$7613_Y + connect \Y $ternary$libresoc.v:152263$7597_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" - cell $mux $ternary$libresoc.v:151068$7614 + cell $mux $ternary$libresoc.v:152264$7598 parameter \WIDTH 1 connect \A \$20 connect \B \$18 connect \S \bit_b - connect \Y $ternary$libresoc.v:151068$7614_Y + connect \Y $ternary$libresoc.v:152264$7598_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" - cell $mux $ternary$libresoc.v:151070$7617 + cell $mux $ternary$libresoc.v:152266$7601 parameter \WIDTH 64 connect \A \rb connect \B \ra connect \S \cr_bit - connect \Y $ternary$libresoc.v:151070$7617_Y + connect \Y $ternary$libresoc.v:152266$7601_Y end - attribute \src "libresoc.v:150792.7-150792.20" - process $proc$libresoc.v:150792$7640 + attribute \src "libresoc.v:151988.7-151988.20" + process $proc$libresoc.v:151988$7624 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:151073.3-151107.6" - process $proc$libresoc.v:151073$7622 + attribute \src "libresoc.v:152269.3-152303.6" + process $proc$libresoc.v:152269$7606 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\cr_a_ok[0:0] $1\cr_a_ok[0:0] - assign $0\cr_a$6[3:0]$7623 $1\cr_a$6[3:0]$7624 - attribute \src "libresoc.v:151074.5-151074.29" + assign $0\cr_a$6[3:0]$7607 $1\cr_a$6[3:0]$7608 + attribute \src "libresoc.v:152270.5-152270.29" switch \initial - attribute \src "libresoc.v:151074.9-151074.17" + attribute \src "libresoc.v:152270.9-152270.17" case 1'1 case end @@ -312441,58 +283724,64 @@ module \main$9 case 7'0101010 assign { } { } assign { } { } - assign $1\cr_a$6[3:0]$7624 \$7 [3:0] + assign $1\cr_a$6[3:0]$7608 \$7 [3:0] assign $1\cr_a_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" case 7'1000101 assign { } { } assign { } { } assign { } { } - assign $1\cr_a$6[3:0]$7624 $2\cr_a$6[3:0]$7625 + assign $1\cr_a$6[3:0]$7608 $2\cr_a$6[3:0]$7609 assign $1\cr_a_ok[0:0] 1'1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:105" switch \bt attribute \src "libresoc.v:0.0-0.0" case 2'00 - assign $2\cr_a$6[3:0]$7625 [3:1] \cr_c [3:1] - assign $2\cr_a$6[3:0]$7625 [0] \bit_o + assign $2\cr_a$6[3:0]$7609 [3:1] \cr_c [3:1] + assign $2\cr_a$6[3:0]$7609 [0] \bit_o attribute \src "libresoc.v:0.0-0.0" case 2'01 - assign { $2\cr_a$6[3:0]$7625 [3:2] $2\cr_a$6[3:0]$7625 [0] } { \cr_c [3:2] \cr_c [0] } - assign $2\cr_a$6[3:0]$7625 [1] \bit_o + assign { $2\cr_a$6[3:0]$7609 [3:2] $2\cr_a$6[3:0]$7609 [0] } { \cr_c [3:2] \cr_c [0] } + assign $2\cr_a$6[3:0]$7609 [1] \bit_o attribute \src "libresoc.v:0.0-0.0" case 2'10 - assign { $2\cr_a$6[3:0]$7625 [3] $2\cr_a$6[3:0]$7625 [1:0] } { \cr_c [3] \cr_c [1:0] } - assign $2\cr_a$6[3:0]$7625 [2] \bit_o + assign { $2\cr_a$6[3:0]$7609 [3] $2\cr_a$6[3:0]$7609 [1:0] } { \cr_c [3] \cr_c [1:0] } + assign $2\cr_a$6[3:0]$7609 [2] \bit_o attribute \src "libresoc.v:0.0-0.0" case 2'-- - assign $2\cr_a$6[3:0]$7625 [2:0] \cr_c [2:0] - assign $2\cr_a$6[3:0]$7625 [3] \bit_o + assign $2\cr_a$6[3:0]$7609 [2:0] \cr_c [2:0] + assign $2\cr_a$6[3:0]$7609 [3] \bit_o case - assign $2\cr_a$6[3:0]$7625 \cr_c + assign $2\cr_a$6[3:0]$7609 \cr_c end case assign $1\cr_a_ok[0:0] 1'0 - assign $1\cr_a$6[3:0]$7624 4'0000 + assign $1\cr_a$6[3:0]$7608 4'0000 end sync always update \cr_a_ok $0\cr_a_ok[0:0] - update \cr_a$6 $0\cr_a$6[3:0]$7623 + update \cr_a$6 $0\cr_a$6[3:0]$7607 end - attribute \src "libresoc.v:151108.3-151118.6" - process $proc$libresoc.v:151108$7626 + attribute \src "libresoc.v:152304.3-152322.6" + process $proc$libresoc.v:152304$7610 assign { } { } assign { } { } assign $0\full_cr_ok[0:0] $1\full_cr_ok[0:0] - attribute \src "libresoc.v:151109.5-151109.29" + attribute \src "libresoc.v:152305.5-152305.29" switch \initial - attribute \src "libresoc.v:151109.9-151109.17" + attribute \src "libresoc.v:152305.9-152305.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0101010 + assign $1\full_cr_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign $1\full_cr_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 7'0110000 assign { } { } assign $1\full_cr_ok[0:0] 1'1 @@ -312502,23 +283791,35 @@ module \main$9 sync always update \full_cr_ok $0\full_cr_ok[0:0] end - attribute \src "libresoc.v:151119.3-151160.6" - process $proc$libresoc.v:151119$7627 + attribute \src "libresoc.v:152323.3-152376.6" + process $proc$libresoc.v:152323$7611 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:151120.5-151120.29" + attribute \src "libresoc.v:152324.5-152324.29" switch \initial - attribute \src "libresoc.v:151120.9-151120.17" + attribute \src "libresoc.v:152324.9-152324.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0101010 + assign $1\o_ok[0:0] 1'0 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign $1\o_ok[0:0] 1'0 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110000 + assign $1\o_ok[0:0] 1'0 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 7'0101101 assign { } { } assign { } { } @@ -312559,20 +283860,32 @@ module \main$9 update \o_ok $0\o_ok[0:0] update \o $0\o[63:0] end - attribute \src "libresoc.v:151161.3-151171.6" - process $proc$libresoc.v:151161$7628 + attribute \src "libresoc.v:152377.3-152403.6" + process $proc$libresoc.v:152377$7612 assign { } { } assign { } { } assign $0\BC[1:0] $1\BC[1:0] - attribute \src "libresoc.v:151162.5-151162.29" + attribute \src "libresoc.v:152378.5-152378.29" switch \initial - attribute \src "libresoc.v:151162.9-151162.17" + attribute \src "libresoc.v:152378.9-152378.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0101010 + assign $1\BC[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign $1\BC[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110000 + assign $1\BC[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 7'0101101 + assign $1\BC[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" case 7'0100011 assign { } { } assign $1\BC[1:0] \cr_op__insn [7:6] @@ -312582,20 +283895,32 @@ module \main$9 sync always update \BC $0\BC[1:0] end - attribute \src "libresoc.v:151172.3-151192.6" - process $proc$libresoc.v:151172$7629 + attribute \src "libresoc.v:152404.3-152440.6" + process $proc$libresoc.v:152404$7613 assign { } { } assign { } { } assign $0\cr_bit[0:0] $1\cr_bit[0:0] - attribute \src "libresoc.v:151173.5-151173.29" + attribute \src "libresoc.v:152405.5-152405.29" switch \initial - attribute \src "libresoc.v:151173.9-151173.17" + attribute \src "libresoc.v:152405.9-152405.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0101010 + assign $1\cr_bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign $1\cr_bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110000 + assign $1\cr_bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0101101 + assign $1\cr_bit[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 7'0100011 assign { } { } assign $1\cr_bit[0:0] $2\cr_bit[0:0] @@ -312626,20 +283951,23 @@ module \main$9 sync always update \cr_bit $0\cr_bit[0:0] end - attribute \src "libresoc.v:151193.3-151203.6" - process $proc$libresoc.v:151193$7630 + attribute \src "libresoc.v:152441.3-152455.6" + process $proc$libresoc.v:152441$7614 assign { } { } assign { } { } assign $0\lut[3:0] $1\lut[3:0] - attribute \src "libresoc.v:151194.5-151194.29" + attribute \src "libresoc.v:152442.5-152442.29" switch \initial - attribute \src "libresoc.v:151194.9-151194.17" + attribute \src "libresoc.v:152442.9-152442.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0101010 + assign $1\lut[3:0] 4'0000 + attribute \src "libresoc.v:0.0-0.0" case 7'1000101 assign { } { } assign $1\lut[3:0] \cr_op__insn [9:6] @@ -312649,20 +283977,23 @@ module \main$9 sync always update \lut $0\lut[3:0] end - attribute \src "libresoc.v:151204.3-151214.6" - process $proc$libresoc.v:151204$7631 + attribute \src "libresoc.v:152456.3-152470.6" + process $proc$libresoc.v:152456$7615 assign { } { } assign { } { } assign $0\bt[1:0] $1\bt[1:0] - attribute \src "libresoc.v:151205.5-151205.29" + attribute \src "libresoc.v:152457.5-152457.29" switch \initial - attribute \src "libresoc.v:151205.9-151205.17" + attribute \src "libresoc.v:152457.9-152457.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0101010 + assign $1\bt[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" case 7'1000101 assign { } { } assign $1\bt[1:0] \$9 [1:0] @@ -312672,20 +284003,23 @@ module \main$9 sync always update \bt $0\bt[1:0] end - attribute \src "libresoc.v:151215.3-151225.6" - process $proc$libresoc.v:151215$7632 + attribute \src "libresoc.v:152471.3-152485.6" + process $proc$libresoc.v:152471$7616 assign { } { } assign { } { } assign $0\ba[1:0] $1\ba[1:0] - attribute \src "libresoc.v:151216.5-151216.29" + attribute \src "libresoc.v:152472.5-152472.29" switch \initial - attribute \src "libresoc.v:151216.9-151216.17" + attribute \src "libresoc.v:152472.9-152472.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0101010 + assign $1\ba[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" case 7'1000101 assign { } { } assign $1\ba[1:0] \$12 [1:0] @@ -312695,20 +284029,23 @@ module \main$9 sync always update \ba $0\ba[1:0] end - attribute \src "libresoc.v:151226.3-151236.6" - process $proc$libresoc.v:151226$7633 + attribute \src "libresoc.v:152486.3-152500.6" + process $proc$libresoc.v:152486$7617 assign { } { } assign { } { } assign $0\bb[1:0] $1\bb[1:0] - attribute \src "libresoc.v:151227.5-151227.29" + attribute \src "libresoc.v:152487.5-152487.29" switch \initial - attribute \src "libresoc.v:151227.9-151227.17" + attribute \src "libresoc.v:152487.9-152487.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0101010 + assign $1\bb[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" case 7'1000101 assign { } { } assign $1\bb[1:0] \$15 [1:0] @@ -312718,20 +284055,23 @@ module \main$9 sync always update \bb $0\bb[1:0] end - attribute \src "libresoc.v:151237.3-151257.6" - process $proc$libresoc.v:151237$7634 + attribute \src "libresoc.v:152501.3-152525.6" + process $proc$libresoc.v:152501$7618 assign { } { } assign { } { } assign $0\bit_a[0:0] $1\bit_a[0:0] - attribute \src "libresoc.v:151238.5-151238.29" + attribute \src "libresoc.v:152502.5-152502.29" switch \initial - attribute \src "libresoc.v:151238.9-151238.17" + attribute \src "libresoc.v:152502.9-152502.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0101010 + assign $1\bit_a[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 7'1000101 assign { } { } assign $1\bit_a[0:0] $2\bit_a[0:0] @@ -312762,20 +284102,23 @@ module \main$9 sync always update \bit_a $0\bit_a[0:0] end - attribute \src "libresoc.v:151258.3-151278.6" - process $proc$libresoc.v:151258$7635 + attribute \src "libresoc.v:152526.3-152550.6" + process $proc$libresoc.v:152526$7619 assign { } { } assign { } { } assign $0\bit_b[0:0] $1\bit_b[0:0] - attribute \src "libresoc.v:151259.5-151259.29" + attribute \src "libresoc.v:152527.5-152527.29" switch \initial - attribute \src "libresoc.v:151259.9-151259.17" + attribute \src "libresoc.v:152527.9-152527.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0101010 + assign $1\bit_b[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 7'1000101 assign { } { } assign $1\bit_b[0:0] $2\bit_b[0:0] @@ -312806,20 +284149,23 @@ module \main$9 sync always update \bit_b $0\bit_b[0:0] end - attribute \src "libresoc.v:151279.3-151289.6" - process $proc$libresoc.v:151279$7636 + attribute \src "libresoc.v:152551.3-152565.6" + process $proc$libresoc.v:152551$7620 assign { } { } assign { } { } assign $0\bit_o[0:0] $1\bit_o[0:0] - attribute \src "libresoc.v:151280.5-151280.29" + attribute \src "libresoc.v:152552.5-152552.29" switch \initial - attribute \src "libresoc.v:151280.9-151280.17" + attribute \src "libresoc.v:152552.9-152552.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0101010 + assign $1\bit_o[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 7'1000101 assign { } { } assign $1\bit_o[0:0] \$22 @@ -312829,524 +284175,530 @@ module \main$9 sync always update \bit_o $0\bit_o[0:0] end - attribute \src "libresoc.v:151290.3-151300.6" - process $proc$libresoc.v:151290$7637 + attribute \src "libresoc.v:152566.3-152584.6" + process $proc$libresoc.v:152566$7621 assign { } { } assign { } { } - assign $0\full_cr$5[31:0]$7638 $1\full_cr$5[31:0]$7639 - attribute \src "libresoc.v:151291.5-151291.29" + assign $0\full_cr$5[31:0]$7622 $1\full_cr$5[31:0]$7623 + attribute \src "libresoc.v:152567.5-152567.29" switch \initial - attribute \src "libresoc.v:151291.9-151291.17" + attribute \src "libresoc.v:152567.9-152567.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" switch \cr_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0101010 + assign $1\full_cr$5[31:0]$7623 0 + attribute \src "libresoc.v:0.0-0.0" + case 7'1000101 + assign $1\full_cr$5[31:0]$7623 0 + attribute \src "libresoc.v:0.0-0.0" case 7'0110000 assign { } { } - assign $1\full_cr$5[31:0]$7639 \ra [31:0] + assign $1\full_cr$5[31:0]$7623 \ra [31:0] case - assign $1\full_cr$5[31:0]$7639 0 + assign $1\full_cr$5[31:0]$7623 0 end sync always - update \full_cr$5 $0\full_cr$5[31:0]$7638 + update \full_cr$5 $0\full_cr$5[31:0]$7622 end - connect \$10 $sub$libresoc.v:151063$7609_Y - connect \$13 $sub$libresoc.v:151064$7610_Y - connect \$16 $sub$libresoc.v:151065$7611_Y - connect \$18 $ternary$libresoc.v:151066$7612_Y - connect \$20 $ternary$libresoc.v:151067$7613_Y - connect \$22 $ternary$libresoc.v:151068$7614_Y - connect \$24 $pos$libresoc.v:151069$7616_Y - connect \$27 $ternary$libresoc.v:151070$7617_Y - connect \$26 $pos$libresoc.v:151071$7619_Y - connect \$7 $pos$libresoc.v:151072$7621_Y + connect \$10 $sub$libresoc.v:152259$7593_Y + connect \$13 $sub$libresoc.v:152260$7594_Y + connect \$16 $sub$libresoc.v:152261$7595_Y + connect \$18 $ternary$libresoc.v:152262$7596_Y + connect \$20 $ternary$libresoc.v:152263$7597_Y + connect \$22 $ternary$libresoc.v:152264$7598_Y + connect \$24 $pos$libresoc.v:152265$7600_Y + connect \$27 $ternary$libresoc.v:152266$7601_Y + connect \$26 $pos$libresoc.v:152267$7603_Y + connect \$7 $pos$libresoc.v:152268$7605_Y connect \$9 \$10 connect \$12 \$13 connect \$15 \$16 connect { \cr_op__insn$4 \cr_op__fn_unit$3 \cr_op__insn_type$2 } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } connect \muxid$1 \muxid end -attribute \src "libresoc.v:151310.1-152471.10" +attribute \src "libresoc.v:152594.1-153755.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0" attribute \generator "nMigen" module \mul0 - attribute \src "libresoc.v:152042.3-152043.25" + attribute \src "libresoc.v:153326.3-153327.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:152040.3-152041.40" + attribute \src "libresoc.v:153324.3-153325.40" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:152383.3-152391.6" - wire $0\alu_l_r_alu$next[0:0]$7846 - attribute \src "libresoc.v:151968.3-151969.39" + attribute \src "libresoc.v:153667.3-153675.6" + wire $0\alu_l_r_alu$next[0:0]$7830 + attribute \src "libresoc.v:153252.3-153253.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:152223.3-152255.6" - wire width 14 $0\alu_mul0_mul_op__fn_unit$next[13:0]$7771 - attribute \src "libresoc.v:151996.3-151997.65" + attribute \src "libresoc.v:153507.3-153539.6" + wire width 14 $0\alu_mul0_mul_op__fn_unit$next[13:0]$7755 + attribute \src "libresoc.v:153280.3-153281.65" wire width 14 $0\alu_mul0_mul_op__fn_unit[13:0] - attribute \src "libresoc.v:152223.3-152255.6" - wire width 64 $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7772 - attribute \src "libresoc.v:151998.3-151999.79" + attribute \src "libresoc.v:153507.3-153539.6" + wire width 64 $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7756 + attribute \src "libresoc.v:153282.3-153283.79" wire width 64 $0\alu_mul0_mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:152223.3-152255.6" - wire $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7773 - attribute \src "libresoc.v:152000.3-152001.75" + attribute \src "libresoc.v:153507.3-153539.6" + wire $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7757 + attribute \src "libresoc.v:153284.3-153285.75" wire $0\alu_mul0_mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:152223.3-152255.6" - wire width 32 $0\alu_mul0_mul_op__insn$next[31:0]$7774 - attribute \src "libresoc.v:152016.3-152017.59" + attribute \src "libresoc.v:153507.3-153539.6" + wire width 32 $0\alu_mul0_mul_op__insn$next[31:0]$7758 + attribute \src "libresoc.v:153300.3-153301.59" wire width 32 $0\alu_mul0_mul_op__insn[31:0] - attribute \src "libresoc.v:152223.3-152255.6" - wire width 7 $0\alu_mul0_mul_op__insn_type$next[6:0]$7775 - attribute \src "libresoc.v:151994.3-151995.69" + attribute \src "libresoc.v:153507.3-153539.6" + wire width 7 $0\alu_mul0_mul_op__insn_type$next[6:0]$7759 + attribute \src "libresoc.v:153278.3-153279.69" wire width 7 $0\alu_mul0_mul_op__insn_type[6:0] - attribute \src "libresoc.v:152223.3-152255.6" - wire $0\alu_mul0_mul_op__is_32bit$next[0:0]$7776 - attribute \src "libresoc.v:152012.3-152013.67" + attribute \src "libresoc.v:153507.3-153539.6" + wire $0\alu_mul0_mul_op__is_32bit$next[0:0]$7760 + attribute \src "libresoc.v:153296.3-153297.67" wire $0\alu_mul0_mul_op__is_32bit[0:0] - attribute \src "libresoc.v:152223.3-152255.6" - wire $0\alu_mul0_mul_op__is_signed$next[0:0]$7777 - attribute \src "libresoc.v:152014.3-152015.69" + attribute \src "libresoc.v:153507.3-153539.6" + wire $0\alu_mul0_mul_op__is_signed$next[0:0]$7761 + attribute \src "libresoc.v:153298.3-153299.69" wire $0\alu_mul0_mul_op__is_signed[0:0] - attribute \src "libresoc.v:152223.3-152255.6" - wire $0\alu_mul0_mul_op__oe__oe$next[0:0]$7778 - attribute \src "libresoc.v:152006.3-152007.63" + attribute \src "libresoc.v:153507.3-153539.6" + wire $0\alu_mul0_mul_op__oe__oe$next[0:0]$7762 + attribute \src "libresoc.v:153290.3-153291.63" wire $0\alu_mul0_mul_op__oe__oe[0:0] - attribute \src "libresoc.v:152223.3-152255.6" - wire $0\alu_mul0_mul_op__oe__ok$next[0:0]$7779 - attribute \src "libresoc.v:152008.3-152009.63" + attribute \src "libresoc.v:153507.3-153539.6" + wire $0\alu_mul0_mul_op__oe__ok$next[0:0]$7763 + attribute \src "libresoc.v:153292.3-153293.63" wire $0\alu_mul0_mul_op__oe__ok[0:0] - attribute \src "libresoc.v:152223.3-152255.6" - wire $0\alu_mul0_mul_op__rc__ok$next[0:0]$7780 - attribute \src "libresoc.v:152004.3-152005.63" + attribute \src "libresoc.v:153507.3-153539.6" + wire $0\alu_mul0_mul_op__rc__ok$next[0:0]$7764 + attribute \src "libresoc.v:153288.3-153289.63" wire $0\alu_mul0_mul_op__rc__ok[0:0] - attribute \src "libresoc.v:152223.3-152255.6" - wire $0\alu_mul0_mul_op__rc__rc$next[0:0]$7781 - attribute \src "libresoc.v:152002.3-152003.63" + attribute \src "libresoc.v:153507.3-153539.6" + wire $0\alu_mul0_mul_op__rc__rc$next[0:0]$7765 + attribute \src "libresoc.v:153286.3-153287.63" wire $0\alu_mul0_mul_op__rc__rc[0:0] - attribute \src "libresoc.v:152223.3-152255.6" - wire $0\alu_mul0_mul_op__write_cr0$next[0:0]$7782 - attribute \src "libresoc.v:152010.3-152011.69" + attribute \src "libresoc.v:153507.3-153539.6" + wire $0\alu_mul0_mul_op__write_cr0$next[0:0]$7766 + attribute \src "libresoc.v:153294.3-153295.69" wire $0\alu_mul0_mul_op__write_cr0[0:0] - attribute \src "libresoc.v:152374.3-152382.6" - wire $0\alui_l_r_alui$next[0:0]$7843 - attribute \src "libresoc.v:151970.3-151971.43" + attribute \src "libresoc.v:153658.3-153666.6" + wire $0\alui_l_r_alui$next[0:0]$7827 + attribute \src "libresoc.v:153254.3-153255.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:152256.3-152277.6" - wire width 64 $0\data_r0__o$next[63:0]$7802 - attribute \src "libresoc.v:151990.3-151991.37" + attribute \src "libresoc.v:153540.3-153561.6" + wire width 64 $0\data_r0__o$next[63:0]$7786 + attribute \src "libresoc.v:153274.3-153275.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:152256.3-152277.6" - wire $0\data_r0__o_ok$next[0:0]$7803 - attribute \src "libresoc.v:151992.3-151993.43" + attribute \src "libresoc.v:153540.3-153561.6" + wire $0\data_r0__o_ok$next[0:0]$7787 + attribute \src "libresoc.v:153276.3-153277.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:152278.3-152299.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$7810 - attribute \src "libresoc.v:151986.3-151987.43" + attribute \src "libresoc.v:153562.3-153583.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$7794 + attribute \src "libresoc.v:153270.3-153271.43" wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:152278.3-152299.6" - wire $0\data_r1__cr_a_ok$next[0:0]$7811 - attribute \src "libresoc.v:151988.3-151989.49" + attribute \src "libresoc.v:153562.3-153583.6" + wire $0\data_r1__cr_a_ok$next[0:0]$7795 + attribute \src "libresoc.v:153272.3-153273.49" wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:152300.3-152321.6" - wire width 2 $0\data_r2__xer_ov$next[1:0]$7818 - attribute \src "libresoc.v:151982.3-151983.47" + attribute \src "libresoc.v:153584.3-153605.6" + wire width 2 $0\data_r2__xer_ov$next[1:0]$7802 + attribute \src "libresoc.v:153266.3-153267.47" wire width 2 $0\data_r2__xer_ov[1:0] - attribute \src "libresoc.v:152300.3-152321.6" - wire $0\data_r2__xer_ov_ok$next[0:0]$7819 - attribute \src "libresoc.v:151984.3-151985.53" + attribute \src "libresoc.v:153584.3-153605.6" + wire $0\data_r2__xer_ov_ok$next[0:0]$7803 + attribute \src "libresoc.v:153268.3-153269.53" wire $0\data_r2__xer_ov_ok[0:0] - attribute \src "libresoc.v:152322.3-152343.6" - wire $0\data_r3__xer_so$next[0:0]$7826 - attribute \src "libresoc.v:151978.3-151979.47" + attribute \src "libresoc.v:153606.3-153627.6" + wire $0\data_r3__xer_so$next[0:0]$7810 + attribute \src "libresoc.v:153262.3-153263.47" wire $0\data_r3__xer_so[0:0] - attribute \src "libresoc.v:152322.3-152343.6" - wire $0\data_r3__xer_so_ok$next[0:0]$7827 - attribute \src "libresoc.v:151980.3-151981.53" + attribute \src "libresoc.v:153606.3-153627.6" + wire $0\data_r3__xer_so_ok$next[0:0]$7811 + attribute \src "libresoc.v:153264.3-153265.53" wire $0\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:152392.3-152401.6" + attribute \src "libresoc.v:153676.3-153685.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:152402.3-152411.6" + attribute \src "libresoc.v:153686.3-153695.6" wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:152412.3-152421.6" + attribute \src "libresoc.v:153696.3-153705.6" wire width 2 $0\dest3_o[1:0] - attribute \src "libresoc.v:152422.3-152431.6" + attribute \src "libresoc.v:153706.3-153715.6" wire $0\dest4_o[0:0] - attribute \src "libresoc.v:151311.7-151311.20" + attribute \src "libresoc.v:152595.7-152595.20" wire $0\initial[0:0] - attribute \src "libresoc.v:152178.3-152186.6" - wire $0\opc_l_r_opc$next[0:0]$7756 - attribute \src "libresoc.v:152026.3-152027.39" + attribute \src "libresoc.v:153462.3-153470.6" + wire $0\opc_l_r_opc$next[0:0]$7740 + attribute \src "libresoc.v:153310.3-153311.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:152169.3-152177.6" - wire $0\opc_l_s_opc$next[0:0]$7753 - attribute \src "libresoc.v:152028.3-152029.39" + attribute \src "libresoc.v:153453.3-153461.6" + wire $0\opc_l_s_opc$next[0:0]$7737 + attribute \src "libresoc.v:153312.3-153313.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:152432.3-152440.6" - wire width 4 $0\prev_wr_go$next[3:0]$7853 - attribute \src "libresoc.v:152038.3-152039.37" + attribute \src "libresoc.v:153716.3-153724.6" + wire width 4 $0\prev_wr_go$next[3:0]$7837 + attribute \src "libresoc.v:153322.3-153323.37" wire width 4 $0\prev_wr_go[3:0] - attribute \src "libresoc.v:152123.3-152132.6" + attribute \src "libresoc.v:153407.3-153416.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:152214.3-152222.6" - wire width 4 $0\req_l_r_req$next[3:0]$7768 - attribute \src "libresoc.v:152018.3-152019.39" + attribute \src "libresoc.v:153498.3-153506.6" + wire width 4 $0\req_l_r_req$next[3:0]$7752 + attribute \src "libresoc.v:153302.3-153303.39" wire width 4 $0\req_l_r_req[3:0] - attribute \src "libresoc.v:152205.3-152213.6" - wire width 4 $0\req_l_s_req$next[3:0]$7765 - attribute \src "libresoc.v:152020.3-152021.39" + attribute \src "libresoc.v:153489.3-153497.6" + wire width 4 $0\req_l_s_req$next[3:0]$7749 + attribute \src "libresoc.v:153304.3-153305.39" wire width 4 $0\req_l_s_req[3:0] - attribute \src "libresoc.v:152142.3-152150.6" - wire $0\rok_l_r_rdok$next[0:0]$7744 - attribute \src "libresoc.v:152034.3-152035.41" + attribute \src "libresoc.v:153426.3-153434.6" + wire $0\rok_l_r_rdok$next[0:0]$7728 + attribute \src "libresoc.v:153318.3-153319.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:152133.3-152141.6" - wire $0\rok_l_s_rdok$next[0:0]$7741 - attribute \src "libresoc.v:152036.3-152037.41" + attribute \src "libresoc.v:153417.3-153425.6" + wire $0\rok_l_s_rdok$next[0:0]$7725 + attribute \src "libresoc.v:153320.3-153321.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:152160.3-152168.6" - wire $0\rst_l_r_rst$next[0:0]$7750 - attribute \src "libresoc.v:152030.3-152031.39" + attribute \src "libresoc.v:153444.3-153452.6" + wire $0\rst_l_r_rst$next[0:0]$7734 + attribute \src "libresoc.v:153314.3-153315.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:152151.3-152159.6" - wire $0\rst_l_s_rst$next[0:0]$7747 - attribute \src "libresoc.v:152032.3-152033.39" + attribute \src "libresoc.v:153435.3-153443.6" + wire $0\rst_l_s_rst$next[0:0]$7731 + attribute \src "libresoc.v:153316.3-153317.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:152196.3-152204.6" - wire width 3 $0\src_l_r_src$next[2:0]$7762 - attribute \src "libresoc.v:152022.3-152023.39" + attribute \src "libresoc.v:153480.3-153488.6" + wire width 3 $0\src_l_r_src$next[2:0]$7746 + attribute \src "libresoc.v:153306.3-153307.39" wire width 3 $0\src_l_r_src[2:0] - attribute \src "libresoc.v:152187.3-152195.6" - wire width 3 $0\src_l_s_src$next[2:0]$7759 - attribute \src "libresoc.v:152024.3-152025.39" + attribute \src "libresoc.v:153471.3-153479.6" + wire width 3 $0\src_l_s_src$next[2:0]$7743 + attribute \src "libresoc.v:153308.3-153309.39" wire width 3 $0\src_l_s_src[2:0] - attribute \src "libresoc.v:152344.3-152353.6" - wire width 64 $0\src_r0$next[63:0]$7834 - attribute \src "libresoc.v:151976.3-151977.29" + attribute \src "libresoc.v:153628.3-153637.6" + wire width 64 $0\src_r0$next[63:0]$7818 + attribute \src "libresoc.v:153260.3-153261.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:152354.3-152363.6" - wire width 64 $0\src_r1$next[63:0]$7837 - attribute \src "libresoc.v:151974.3-151975.29" + attribute \src "libresoc.v:153638.3-153647.6" + wire width 64 $0\src_r1$next[63:0]$7821 + attribute \src "libresoc.v:153258.3-153259.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:152364.3-152373.6" - wire $0\src_r2$next[0:0]$7840 - attribute \src "libresoc.v:151972.3-151973.29" + attribute \src "libresoc.v:153648.3-153657.6" + wire $0\src_r2$next[0:0]$7824 + attribute \src "libresoc.v:153256.3-153257.29" wire $0\src_r2[0:0] - attribute \src "libresoc.v:151435.7-151435.24" + attribute \src "libresoc.v:152719.7-152719.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:151445.7-151445.26" + attribute \src "libresoc.v:152729.7-152729.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:152383.3-152391.6" - wire $1\alu_l_r_alu$next[0:0]$7847 - attribute \src "libresoc.v:151453.7-151453.25" + attribute \src "libresoc.v:153667.3-153675.6" + wire $1\alu_l_r_alu$next[0:0]$7831 + attribute \src "libresoc.v:152737.7-152737.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:152223.3-152255.6" - wire width 14 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7783 - attribute \src "libresoc.v:151476.14-151476.49" + attribute \src "libresoc.v:153507.3-153539.6" + wire width 14 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7767 + attribute \src "libresoc.v:152760.14-152760.49" wire width 14 $1\alu_mul0_mul_op__fn_unit[13:0] - attribute \src "libresoc.v:152223.3-152255.6" - wire width 64 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7784 - attribute \src "libresoc.v:151480.14-151480.68" + attribute \src "libresoc.v:153507.3-153539.6" + wire width 64 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7768 + attribute \src "libresoc.v:152764.14-152764.68" wire width 64 $1\alu_mul0_mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:152223.3-152255.6" - wire $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7785 - attribute \src "libresoc.v:151484.7-151484.43" + attribute \src "libresoc.v:153507.3-153539.6" + wire $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7769 + attribute \src "libresoc.v:152768.7-152768.43" wire $1\alu_mul0_mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:152223.3-152255.6" - wire width 32 $1\alu_mul0_mul_op__insn$next[31:0]$7786 - attribute \src "libresoc.v:151488.14-151488.43" + attribute \src "libresoc.v:153507.3-153539.6" + wire width 32 $1\alu_mul0_mul_op__insn$next[31:0]$7770 + attribute \src "libresoc.v:152772.14-152772.43" wire width 32 $1\alu_mul0_mul_op__insn[31:0] - attribute \src "libresoc.v:152223.3-152255.6" - wire width 7 $1\alu_mul0_mul_op__insn_type$next[6:0]$7787 - attribute \src "libresoc.v:151567.13-151567.47" + attribute \src "libresoc.v:153507.3-153539.6" + wire width 7 $1\alu_mul0_mul_op__insn_type$next[6:0]$7771 + attribute \src "libresoc.v:152851.13-152851.47" wire width 7 $1\alu_mul0_mul_op__insn_type[6:0] - attribute \src "libresoc.v:152223.3-152255.6" - wire $1\alu_mul0_mul_op__is_32bit$next[0:0]$7788 - attribute \src "libresoc.v:151571.7-151571.39" + attribute \src "libresoc.v:153507.3-153539.6" + wire $1\alu_mul0_mul_op__is_32bit$next[0:0]$7772 + attribute \src "libresoc.v:152855.7-152855.39" wire $1\alu_mul0_mul_op__is_32bit[0:0] - attribute \src "libresoc.v:152223.3-152255.6" - wire $1\alu_mul0_mul_op__is_signed$next[0:0]$7789 - attribute \src "libresoc.v:151575.7-151575.40" + attribute \src "libresoc.v:153507.3-153539.6" + wire $1\alu_mul0_mul_op__is_signed$next[0:0]$7773 + attribute \src "libresoc.v:152859.7-152859.40" wire $1\alu_mul0_mul_op__is_signed[0:0] - attribute \src "libresoc.v:152223.3-152255.6" - wire $1\alu_mul0_mul_op__oe__oe$next[0:0]$7790 - attribute \src "libresoc.v:151579.7-151579.37" + attribute \src "libresoc.v:153507.3-153539.6" + wire $1\alu_mul0_mul_op__oe__oe$next[0:0]$7774 + attribute \src "libresoc.v:152863.7-152863.37" wire $1\alu_mul0_mul_op__oe__oe[0:0] - attribute \src "libresoc.v:152223.3-152255.6" - wire $1\alu_mul0_mul_op__oe__ok$next[0:0]$7791 - attribute \src "libresoc.v:151583.7-151583.37" + attribute \src "libresoc.v:153507.3-153539.6" + wire $1\alu_mul0_mul_op__oe__ok$next[0:0]$7775 + attribute \src "libresoc.v:152867.7-152867.37" wire $1\alu_mul0_mul_op__oe__ok[0:0] - attribute \src "libresoc.v:152223.3-152255.6" - wire $1\alu_mul0_mul_op__rc__ok$next[0:0]$7792 - attribute \src "libresoc.v:151587.7-151587.37" + attribute \src "libresoc.v:153507.3-153539.6" + wire $1\alu_mul0_mul_op__rc__ok$next[0:0]$7776 + attribute \src "libresoc.v:152871.7-152871.37" wire $1\alu_mul0_mul_op__rc__ok[0:0] - attribute \src "libresoc.v:152223.3-152255.6" - wire $1\alu_mul0_mul_op__rc__rc$next[0:0]$7793 - attribute \src "libresoc.v:151591.7-151591.37" + attribute \src "libresoc.v:153507.3-153539.6" + wire $1\alu_mul0_mul_op__rc__rc$next[0:0]$7777 + attribute \src "libresoc.v:152875.7-152875.37" wire $1\alu_mul0_mul_op__rc__rc[0:0] - attribute \src "libresoc.v:152223.3-152255.6" - wire $1\alu_mul0_mul_op__write_cr0$next[0:0]$7794 - attribute \src "libresoc.v:151595.7-151595.40" + attribute \src "libresoc.v:153507.3-153539.6" + wire $1\alu_mul0_mul_op__write_cr0$next[0:0]$7778 + attribute \src "libresoc.v:152879.7-152879.40" wire $1\alu_mul0_mul_op__write_cr0[0:0] - attribute \src "libresoc.v:152374.3-152382.6" - wire $1\alui_l_r_alui$next[0:0]$7844 - attribute \src "libresoc.v:151625.7-151625.27" + attribute \src "libresoc.v:153658.3-153666.6" + wire $1\alui_l_r_alui$next[0:0]$7828 + attribute \src "libresoc.v:152909.7-152909.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:152256.3-152277.6" - wire width 64 $1\data_r0__o$next[63:0]$7804 - attribute \src "libresoc.v:151659.14-151659.47" + attribute \src "libresoc.v:153540.3-153561.6" + wire width 64 $1\data_r0__o$next[63:0]$7788 + attribute \src "libresoc.v:152943.14-152943.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:152256.3-152277.6" - wire $1\data_r0__o_ok$next[0:0]$7805 - attribute \src "libresoc.v:151663.7-151663.27" + attribute \src "libresoc.v:153540.3-153561.6" + wire $1\data_r0__o_ok$next[0:0]$7789 + attribute \src "libresoc.v:152947.7-152947.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:152278.3-152299.6" - wire width 4 $1\data_r1__cr_a$next[3:0]$7812 - attribute \src "libresoc.v:151667.13-151667.33" + attribute \src "libresoc.v:153562.3-153583.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$7796 + attribute \src "libresoc.v:152951.13-152951.33" wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:152278.3-152299.6" - wire $1\data_r1__cr_a_ok$next[0:0]$7813 - attribute \src "libresoc.v:151671.7-151671.30" + attribute \src "libresoc.v:153562.3-153583.6" + wire $1\data_r1__cr_a_ok$next[0:0]$7797 + attribute \src "libresoc.v:152955.7-152955.30" wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:152300.3-152321.6" - wire width 2 $1\data_r2__xer_ov$next[1:0]$7820 - attribute \src "libresoc.v:151675.13-151675.35" + attribute \src "libresoc.v:153584.3-153605.6" + wire width 2 $1\data_r2__xer_ov$next[1:0]$7804 + attribute \src "libresoc.v:152959.13-152959.35" wire width 2 $1\data_r2__xer_ov[1:0] - attribute \src "libresoc.v:152300.3-152321.6" - wire $1\data_r2__xer_ov_ok$next[0:0]$7821 - attribute \src "libresoc.v:151679.7-151679.32" + attribute \src "libresoc.v:153584.3-153605.6" + wire $1\data_r2__xer_ov_ok$next[0:0]$7805 + attribute \src "libresoc.v:152963.7-152963.32" wire $1\data_r2__xer_ov_ok[0:0] - attribute \src "libresoc.v:152322.3-152343.6" - wire $1\data_r3__xer_so$next[0:0]$7828 - attribute \src "libresoc.v:151683.7-151683.29" + attribute \src "libresoc.v:153606.3-153627.6" + wire $1\data_r3__xer_so$next[0:0]$7812 + attribute \src "libresoc.v:152967.7-152967.29" wire $1\data_r3__xer_so[0:0] - attribute \src "libresoc.v:152322.3-152343.6" - wire $1\data_r3__xer_so_ok$next[0:0]$7829 - attribute \src "libresoc.v:151687.7-151687.32" + attribute \src "libresoc.v:153606.3-153627.6" + wire $1\data_r3__xer_so_ok$next[0:0]$7813 + attribute \src "libresoc.v:152971.7-152971.32" wire $1\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:152392.3-152401.6" + attribute \src "libresoc.v:153676.3-153685.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:152402.3-152411.6" + attribute \src "libresoc.v:153686.3-153695.6" wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:152412.3-152421.6" + attribute \src "libresoc.v:153696.3-153705.6" wire width 2 $1\dest3_o[1:0] - attribute \src "libresoc.v:152422.3-152431.6" + attribute \src "libresoc.v:153706.3-153715.6" wire $1\dest4_o[0:0] - attribute \src "libresoc.v:152178.3-152186.6" - wire $1\opc_l_r_opc$next[0:0]$7757 - attribute \src "libresoc.v:151707.7-151707.25" + attribute \src "libresoc.v:153462.3-153470.6" + wire $1\opc_l_r_opc$next[0:0]$7741 + attribute \src "libresoc.v:152991.7-152991.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:152169.3-152177.6" - wire $1\opc_l_s_opc$next[0:0]$7754 - attribute \src "libresoc.v:151711.7-151711.25" + attribute \src "libresoc.v:153453.3-153461.6" + wire $1\opc_l_s_opc$next[0:0]$7738 + attribute \src "libresoc.v:152995.7-152995.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:152432.3-152440.6" - wire width 4 $1\prev_wr_go$next[3:0]$7854 - attribute \src "libresoc.v:151829.13-151829.30" + attribute \src "libresoc.v:153716.3-153724.6" + wire width 4 $1\prev_wr_go$next[3:0]$7838 + attribute \src "libresoc.v:153113.13-153113.30" wire width 4 $1\prev_wr_go[3:0] - attribute \src "libresoc.v:152123.3-152132.6" + attribute \src "libresoc.v:153407.3-153416.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:152214.3-152222.6" - wire width 4 $1\req_l_r_req$next[3:0]$7769 - attribute \src "libresoc.v:151837.13-151837.31" + attribute \src "libresoc.v:153498.3-153506.6" + wire width 4 $1\req_l_r_req$next[3:0]$7753 + attribute \src "libresoc.v:153121.13-153121.31" wire width 4 $1\req_l_r_req[3:0] - attribute \src "libresoc.v:152205.3-152213.6" - wire width 4 $1\req_l_s_req$next[3:0]$7766 - attribute \src "libresoc.v:151841.13-151841.31" + attribute \src "libresoc.v:153489.3-153497.6" + wire width 4 $1\req_l_s_req$next[3:0]$7750 + attribute \src "libresoc.v:153125.13-153125.31" wire width 4 $1\req_l_s_req[3:0] - attribute \src "libresoc.v:152142.3-152150.6" - wire $1\rok_l_r_rdok$next[0:0]$7745 - attribute \src "libresoc.v:151853.7-151853.26" + attribute \src "libresoc.v:153426.3-153434.6" + wire $1\rok_l_r_rdok$next[0:0]$7729 + attribute \src "libresoc.v:153137.7-153137.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:152133.3-152141.6" - wire $1\rok_l_s_rdok$next[0:0]$7742 - attribute \src "libresoc.v:151857.7-151857.26" + attribute \src "libresoc.v:153417.3-153425.6" + wire $1\rok_l_s_rdok$next[0:0]$7726 + attribute \src "libresoc.v:153141.7-153141.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:152160.3-152168.6" - wire $1\rst_l_r_rst$next[0:0]$7751 - attribute \src "libresoc.v:151861.7-151861.25" + attribute \src "libresoc.v:153444.3-153452.6" + wire $1\rst_l_r_rst$next[0:0]$7735 + attribute \src "libresoc.v:153145.7-153145.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:152151.3-152159.6" - wire $1\rst_l_s_rst$next[0:0]$7748 - attribute \src "libresoc.v:151865.7-151865.25" + attribute \src "libresoc.v:153435.3-153443.6" + wire $1\rst_l_s_rst$next[0:0]$7732 + attribute \src "libresoc.v:153149.7-153149.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:152196.3-152204.6" - wire width 3 $1\src_l_r_src$next[2:0]$7763 - attribute \src "libresoc.v:151879.13-151879.31" + attribute \src "libresoc.v:153480.3-153488.6" + wire width 3 $1\src_l_r_src$next[2:0]$7747 + attribute \src "libresoc.v:153163.13-153163.31" wire width 3 $1\src_l_r_src[2:0] - attribute \src "libresoc.v:152187.3-152195.6" - wire width 3 $1\src_l_s_src$next[2:0]$7760 - attribute \src "libresoc.v:151883.13-151883.31" + attribute \src "libresoc.v:153471.3-153479.6" + wire width 3 $1\src_l_s_src$next[2:0]$7744 + attribute \src "libresoc.v:153167.13-153167.31" wire width 3 $1\src_l_s_src[2:0] - attribute \src "libresoc.v:152344.3-152353.6" - wire width 64 $1\src_r0$next[63:0]$7835 - attribute \src "libresoc.v:151889.14-151889.43" + attribute \src "libresoc.v:153628.3-153637.6" + wire width 64 $1\src_r0$next[63:0]$7819 + attribute \src "libresoc.v:153173.14-153173.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:152354.3-152363.6" - wire width 64 $1\src_r1$next[63:0]$7838 - attribute \src "libresoc.v:151893.14-151893.43" + attribute \src "libresoc.v:153638.3-153647.6" + wire width 64 $1\src_r1$next[63:0]$7822 + attribute \src "libresoc.v:153177.14-153177.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:152364.3-152373.6" - wire $1\src_r2$next[0:0]$7841 - attribute \src "libresoc.v:151897.7-151897.20" + attribute \src "libresoc.v:153648.3-153657.6" + wire $1\src_r2$next[0:0]$7825 + attribute \src "libresoc.v:153181.7-153181.20" wire $1\src_r2[0:0] - attribute \src "libresoc.v:152223.3-152255.6" - wire width 64 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7795 - attribute \src "libresoc.v:152223.3-152255.6" - wire $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7796 - attribute \src "libresoc.v:152223.3-152255.6" - wire $2\alu_mul0_mul_op__oe__oe$next[0:0]$7797 - attribute \src "libresoc.v:152223.3-152255.6" - wire $2\alu_mul0_mul_op__oe__ok$next[0:0]$7798 - attribute \src "libresoc.v:152223.3-152255.6" - wire $2\alu_mul0_mul_op__rc__ok$next[0:0]$7799 - attribute \src "libresoc.v:152223.3-152255.6" - wire $2\alu_mul0_mul_op__rc__rc$next[0:0]$7800 - attribute \src "libresoc.v:152256.3-152277.6" - wire width 64 $2\data_r0__o$next[63:0]$7806 - attribute \src "libresoc.v:152256.3-152277.6" - wire $2\data_r0__o_ok$next[0:0]$7807 - attribute \src "libresoc.v:152278.3-152299.6" - wire width 4 $2\data_r1__cr_a$next[3:0]$7814 - attribute \src "libresoc.v:152278.3-152299.6" - wire $2\data_r1__cr_a_ok$next[0:0]$7815 - attribute \src "libresoc.v:152300.3-152321.6" - wire width 2 $2\data_r2__xer_ov$next[1:0]$7822 - attribute \src "libresoc.v:152300.3-152321.6" - wire $2\data_r2__xer_ov_ok$next[0:0]$7823 - attribute \src "libresoc.v:152322.3-152343.6" - wire $2\data_r3__xer_so$next[0:0]$7830 - attribute \src "libresoc.v:152322.3-152343.6" - wire $2\data_r3__xer_so_ok$next[0:0]$7831 - attribute \src "libresoc.v:152256.3-152277.6" - wire $3\data_r0__o_ok$next[0:0]$7808 - attribute \src "libresoc.v:152278.3-152299.6" - wire $3\data_r1__cr_a_ok$next[0:0]$7816 - attribute \src "libresoc.v:152300.3-152321.6" - wire $3\data_r2__xer_ov_ok$next[0:0]$7824 - attribute \src "libresoc.v:152322.3-152343.6" - wire $3\data_r3__xer_so_ok$next[0:0]$7832 - attribute \src "libresoc.v:151908.19-151908.113" - wire width 3 $and$libresoc.v:151908$7641_Y - attribute \src "libresoc.v:151909.19-151909.125" - wire $and$libresoc.v:151909$7642_Y - attribute \src "libresoc.v:151910.19-151910.125" - wire $and$libresoc.v:151910$7643_Y - attribute \src "libresoc.v:151911.19-151911.125" - wire $and$libresoc.v:151911$7644_Y - attribute \src "libresoc.v:151912.19-151912.125" - wire $and$libresoc.v:151912$7645_Y - attribute \src "libresoc.v:151913.18-151913.110" - wire $and$libresoc.v:151913$7646_Y - attribute \src "libresoc.v:151914.19-151914.149" - wire width 4 $and$libresoc.v:151914$7647_Y - attribute \src "libresoc.v:151915.19-151915.121" - wire width 4 $and$libresoc.v:151915$7648_Y - attribute \src "libresoc.v:151916.19-151916.127" - wire $and$libresoc.v:151916$7649_Y - attribute \src "libresoc.v:151917.19-151917.127" - wire $and$libresoc.v:151917$7650_Y - attribute \src "libresoc.v:151918.19-151918.127" - wire $and$libresoc.v:151918$7651_Y - attribute \src "libresoc.v:151919.19-151919.127" - wire $and$libresoc.v:151919$7652_Y - attribute \src "libresoc.v:151921.18-151921.98" - wire $and$libresoc.v:151921$7654_Y - attribute \src "libresoc.v:151923.18-151923.100" - wire $and$libresoc.v:151923$7656_Y - attribute \src "libresoc.v:151924.18-151924.160" - wire width 4 $and$libresoc.v:151924$7657_Y - attribute \src "libresoc.v:151926.18-151926.119" - wire width 4 $and$libresoc.v:151926$7659_Y - attribute \src "libresoc.v:151929.17-151929.123" - wire $and$libresoc.v:151929$7662_Y - attribute \src "libresoc.v:151930.18-151930.116" - wire $and$libresoc.v:151930$7663_Y - attribute \src "libresoc.v:151935.18-151935.113" - wire $and$libresoc.v:151935$7668_Y - attribute \src "libresoc.v:151936.18-151936.125" - wire width 4 $and$libresoc.v:151936$7669_Y - attribute \src "libresoc.v:151938.18-151938.112" - wire $and$libresoc.v:151938$7671_Y - attribute \src "libresoc.v:151940.18-151940.126" - wire $and$libresoc.v:151940$7673_Y - attribute \src "libresoc.v:151941.18-151941.126" - wire $and$libresoc.v:151941$7674_Y - attribute \src "libresoc.v:151942.18-151942.117" - wire $and$libresoc.v:151942$7675_Y - attribute \src "libresoc.v:151948.18-151948.130" - wire $and$libresoc.v:151948$7681_Y - attribute \src "libresoc.v:151949.18-151949.124" - wire width 4 $and$libresoc.v:151949$7682_Y - attribute \src "libresoc.v:151951.18-151951.116" - wire $and$libresoc.v:151951$7684_Y - attribute \src "libresoc.v:151952.18-151952.119" - wire $and$libresoc.v:151952$7685_Y - attribute \src "libresoc.v:151953.18-151953.121" - wire $and$libresoc.v:151953$7686_Y - attribute \src "libresoc.v:151954.18-151954.121" - wire $and$libresoc.v:151954$7687_Y - attribute \src "libresoc.v:151961.18-151961.134" - wire $and$libresoc.v:151961$7694_Y - attribute \src "libresoc.v:151963.18-151963.132" - wire $and$libresoc.v:151963$7696_Y - attribute \src "libresoc.v:151964.18-151964.149" - wire width 3 $and$libresoc.v:151964$7697_Y - attribute \src "libresoc.v:151966.18-151966.129" - wire width 3 $and$libresoc.v:151966$7699_Y - attribute \src "libresoc.v:151937.18-151937.113" - wire $eq$libresoc.v:151937$7670_Y - attribute \src "libresoc.v:151939.18-151939.119" - wire $eq$libresoc.v:151939$7672_Y - attribute \src "libresoc.v:151920.18-151920.97" - wire $not$libresoc.v:151920$7653_Y - attribute \src "libresoc.v:151922.18-151922.99" - wire $not$libresoc.v:151922$7655_Y - attribute \src "libresoc.v:151925.18-151925.113" - wire width 4 $not$libresoc.v:151925$7658_Y - attribute \src "libresoc.v:151928.18-151928.106" - wire $not$libresoc.v:151928$7661_Y - attribute \src "libresoc.v:151934.18-151934.120" - wire $not$libresoc.v:151934$7667_Y - attribute \src "libresoc.v:151945.17-151945.113" - wire width 3 $not$libresoc.v:151945$7678_Y - attribute \src "libresoc.v:151965.18-151965.131" - wire $not$libresoc.v:151965$7698_Y - attribute \src "libresoc.v:151967.18-151967.114" - wire width 3 $not$libresoc.v:151967$7700_Y - attribute \src "libresoc.v:151933.18-151933.112" - wire $or$libresoc.v:151933$7666_Y - attribute \src "libresoc.v:151943.18-151943.122" - wire $or$libresoc.v:151943$7676_Y - attribute \src "libresoc.v:151944.18-151944.124" - wire $or$libresoc.v:151944$7677_Y - attribute \src "libresoc.v:151946.18-151946.168" - wire width 4 $or$libresoc.v:151946$7679_Y - attribute \src "libresoc.v:151947.18-151947.155" - wire width 3 $or$libresoc.v:151947$7680_Y - attribute \src "libresoc.v:151950.18-151950.120" - wire width 4 $or$libresoc.v:151950$7683_Y - attribute \src "libresoc.v:151956.17-151956.117" - wire width 3 $or$libresoc.v:151956$7689_Y - attribute \src "libresoc.v:151962.17-151962.104" - wire $reduce_and$libresoc.v:151962$7695_Y - attribute \src "libresoc.v:151927.18-151927.106" - wire $reduce_or$libresoc.v:151927$7660_Y - attribute \src "libresoc.v:151931.18-151931.113" - wire $reduce_or$libresoc.v:151931$7664_Y - attribute \src "libresoc.v:151932.18-151932.112" - wire $reduce_or$libresoc.v:151932$7665_Y - attribute \src "libresoc.v:151955.18-151955.160" - wire $ternary$libresoc.v:151955$7688_Y - attribute \src "libresoc.v:151957.18-151957.172" - wire width 64 $ternary$libresoc.v:151957$7690_Y - attribute \src "libresoc.v:151958.18-151958.118" - wire width 64 $ternary$libresoc.v:151958$7691_Y - attribute \src "libresoc.v:151959.18-151959.115" - wire width 64 $ternary$libresoc.v:151959$7692_Y - attribute \src "libresoc.v:151960.18-151960.118" - wire $ternary$libresoc.v:151960$7693_Y + attribute \src "libresoc.v:153507.3-153539.6" + wire width 64 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7779 + attribute \src "libresoc.v:153507.3-153539.6" + wire $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7780 + attribute \src "libresoc.v:153507.3-153539.6" + wire $2\alu_mul0_mul_op__oe__oe$next[0:0]$7781 + attribute \src "libresoc.v:153507.3-153539.6" + wire $2\alu_mul0_mul_op__oe__ok$next[0:0]$7782 + attribute \src "libresoc.v:153507.3-153539.6" + wire $2\alu_mul0_mul_op__rc__ok$next[0:0]$7783 + attribute \src "libresoc.v:153507.3-153539.6" + wire $2\alu_mul0_mul_op__rc__rc$next[0:0]$7784 + attribute \src "libresoc.v:153540.3-153561.6" + wire width 64 $2\data_r0__o$next[63:0]$7790 + attribute \src "libresoc.v:153540.3-153561.6" + wire $2\data_r0__o_ok$next[0:0]$7791 + attribute \src "libresoc.v:153562.3-153583.6" + wire width 4 $2\data_r1__cr_a$next[3:0]$7798 + attribute \src "libresoc.v:153562.3-153583.6" + wire $2\data_r1__cr_a_ok$next[0:0]$7799 + attribute \src "libresoc.v:153584.3-153605.6" + wire width 2 $2\data_r2__xer_ov$next[1:0]$7806 + attribute \src "libresoc.v:153584.3-153605.6" + wire $2\data_r2__xer_ov_ok$next[0:0]$7807 + attribute \src "libresoc.v:153606.3-153627.6" + wire $2\data_r3__xer_so$next[0:0]$7814 + attribute \src "libresoc.v:153606.3-153627.6" + wire $2\data_r3__xer_so_ok$next[0:0]$7815 + attribute \src "libresoc.v:153540.3-153561.6" + wire $3\data_r0__o_ok$next[0:0]$7792 + attribute \src "libresoc.v:153562.3-153583.6" + wire $3\data_r1__cr_a_ok$next[0:0]$7800 + attribute \src "libresoc.v:153584.3-153605.6" + wire $3\data_r2__xer_ov_ok$next[0:0]$7808 + attribute \src "libresoc.v:153606.3-153627.6" + wire $3\data_r3__xer_so_ok$next[0:0]$7816 + attribute \src "libresoc.v:153192.19-153192.113" + wire width 3 $and$libresoc.v:153192$7625_Y + attribute \src "libresoc.v:153193.19-153193.125" + wire $and$libresoc.v:153193$7626_Y + attribute \src "libresoc.v:153194.19-153194.125" + wire $and$libresoc.v:153194$7627_Y + attribute \src "libresoc.v:153195.19-153195.125" + wire $and$libresoc.v:153195$7628_Y + attribute \src "libresoc.v:153196.19-153196.125" + wire $and$libresoc.v:153196$7629_Y + attribute \src "libresoc.v:153197.18-153197.110" + wire $and$libresoc.v:153197$7630_Y + attribute \src "libresoc.v:153198.19-153198.149" + wire width 4 $and$libresoc.v:153198$7631_Y + attribute \src "libresoc.v:153199.19-153199.121" + wire width 4 $and$libresoc.v:153199$7632_Y + attribute \src "libresoc.v:153200.19-153200.127" + wire $and$libresoc.v:153200$7633_Y + attribute \src "libresoc.v:153201.19-153201.127" + wire $and$libresoc.v:153201$7634_Y + attribute \src "libresoc.v:153202.19-153202.127" + wire $and$libresoc.v:153202$7635_Y + attribute \src "libresoc.v:153203.19-153203.127" + wire $and$libresoc.v:153203$7636_Y + attribute \src "libresoc.v:153205.18-153205.98" + wire $and$libresoc.v:153205$7638_Y + attribute \src "libresoc.v:153207.18-153207.100" + wire $and$libresoc.v:153207$7640_Y + attribute \src "libresoc.v:153208.18-153208.160" + wire width 4 $and$libresoc.v:153208$7641_Y + attribute \src "libresoc.v:153210.18-153210.119" + wire width 4 $and$libresoc.v:153210$7643_Y + attribute \src "libresoc.v:153213.17-153213.123" + wire $and$libresoc.v:153213$7646_Y + attribute \src "libresoc.v:153214.18-153214.116" + wire $and$libresoc.v:153214$7647_Y + attribute \src "libresoc.v:153219.18-153219.113" + wire $and$libresoc.v:153219$7652_Y + attribute \src "libresoc.v:153220.18-153220.125" + wire width 4 $and$libresoc.v:153220$7653_Y + attribute \src "libresoc.v:153222.18-153222.112" + wire $and$libresoc.v:153222$7655_Y + attribute \src "libresoc.v:153224.18-153224.126" + wire $and$libresoc.v:153224$7657_Y + attribute \src "libresoc.v:153225.18-153225.126" + wire $and$libresoc.v:153225$7658_Y + attribute \src "libresoc.v:153226.18-153226.117" + wire $and$libresoc.v:153226$7659_Y + attribute \src "libresoc.v:153232.18-153232.130" + wire $and$libresoc.v:153232$7665_Y + attribute \src "libresoc.v:153233.18-153233.124" + wire width 4 $and$libresoc.v:153233$7666_Y + attribute \src "libresoc.v:153235.18-153235.116" + wire $and$libresoc.v:153235$7668_Y + attribute \src "libresoc.v:153236.18-153236.119" + wire $and$libresoc.v:153236$7669_Y + attribute \src "libresoc.v:153237.18-153237.121" + wire $and$libresoc.v:153237$7670_Y + attribute \src "libresoc.v:153238.18-153238.121" + wire $and$libresoc.v:153238$7671_Y + attribute \src "libresoc.v:153245.18-153245.134" + wire $and$libresoc.v:153245$7678_Y + attribute \src "libresoc.v:153247.18-153247.132" + wire $and$libresoc.v:153247$7680_Y + attribute \src "libresoc.v:153248.18-153248.149" + wire width 3 $and$libresoc.v:153248$7681_Y + attribute \src "libresoc.v:153250.18-153250.129" + wire width 3 $and$libresoc.v:153250$7683_Y + attribute \src "libresoc.v:153221.18-153221.113" + wire $eq$libresoc.v:153221$7654_Y + attribute \src "libresoc.v:153223.18-153223.119" + wire $eq$libresoc.v:153223$7656_Y + attribute \src "libresoc.v:153204.18-153204.97" + wire $not$libresoc.v:153204$7637_Y + attribute \src "libresoc.v:153206.18-153206.99" + wire $not$libresoc.v:153206$7639_Y + attribute \src "libresoc.v:153209.18-153209.113" + wire width 4 $not$libresoc.v:153209$7642_Y + attribute \src "libresoc.v:153212.18-153212.106" + wire $not$libresoc.v:153212$7645_Y + attribute \src "libresoc.v:153218.18-153218.120" + wire $not$libresoc.v:153218$7651_Y + attribute \src "libresoc.v:153229.17-153229.113" + wire width 3 $not$libresoc.v:153229$7662_Y + attribute \src "libresoc.v:153249.18-153249.131" + wire $not$libresoc.v:153249$7682_Y + attribute \src "libresoc.v:153251.18-153251.114" + wire width 3 $not$libresoc.v:153251$7684_Y + attribute \src "libresoc.v:153217.18-153217.112" + wire $or$libresoc.v:153217$7650_Y + attribute \src "libresoc.v:153227.18-153227.122" + wire $or$libresoc.v:153227$7660_Y + attribute \src "libresoc.v:153228.18-153228.124" + wire $or$libresoc.v:153228$7661_Y + attribute \src "libresoc.v:153230.18-153230.168" + wire width 4 $or$libresoc.v:153230$7663_Y + attribute \src "libresoc.v:153231.18-153231.155" + wire width 3 $or$libresoc.v:153231$7664_Y + attribute \src "libresoc.v:153234.18-153234.120" + wire width 4 $or$libresoc.v:153234$7667_Y + attribute \src "libresoc.v:153240.17-153240.117" + wire width 3 $or$libresoc.v:153240$7673_Y + attribute \src "libresoc.v:153246.17-153246.104" + wire $reduce_and$libresoc.v:153246$7679_Y + attribute \src "libresoc.v:153211.18-153211.106" + wire $reduce_or$libresoc.v:153211$7644_Y + attribute \src "libresoc.v:153215.18-153215.113" + wire $reduce_or$libresoc.v:153215$7648_Y + attribute \src "libresoc.v:153216.18-153216.112" + wire $reduce_or$libresoc.v:153216$7649_Y + attribute \src "libresoc.v:153239.18-153239.160" + wire $ternary$libresoc.v:153239$7672_Y + attribute \src "libresoc.v:153241.18-153241.172" + wire width 64 $ternary$libresoc.v:153241$7674_Y + attribute \src "libresoc.v:153242.18-153242.118" + wire width 64 $ternary$libresoc.v:153242$7675_Y + attribute \src "libresoc.v:153243.18-153243.115" + wire width 64 $ternary$libresoc.v:153243$7676_Y + attribute \src "libresoc.v:153244.18-153244.118" + wire $ternary$libresoc.v:153244$7677_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -313665,9 +285017,9 @@ module \mul0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 32 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 26 \cr_a_ok @@ -313733,7 +285085,7 @@ module \mul0 wire width 2 output 29 \dest3_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire output 31 \dest4_o - attribute \src "libresoc.v:151311.7-151311.15" + attribute \src "libresoc.v:152595.7-152595.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 22 \o_ok @@ -313942,7 +285294,7 @@ module \mul0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 30 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:151908$7641 + cell $and $and$libresoc.v:153192$7625 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -313950,10 +285302,10 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \$96 connect \B \$98 - connect \Y $and$libresoc.v:151908$7641_Y + connect \Y $and$libresoc.v:153192$7625_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:151909$7642 + cell $and $and$libresoc.v:153193$7626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -313961,10 +285313,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:151909$7642_Y + connect \Y $and$libresoc.v:153193$7626_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:151910$7643 + cell $and $and$libresoc.v:153194$7627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -313972,10 +285324,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:151910$7643_Y + connect \Y $and$libresoc.v:153194$7627_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:151911$7644 + cell $and $and$libresoc.v:153195$7628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -313983,10 +285335,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:151911$7644_Y + connect \Y $and$libresoc.v:153195$7628_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:151912$7645 + cell $and $and$libresoc.v:153196$7629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -313994,10 +285346,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:151912$7645_Y + connect \Y $and$libresoc.v:153196$7629_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:151913$7646 + cell $and $and$libresoc.v:153197$7630 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314005,10 +285357,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$2 connect \B \$4 - connect \Y $and$libresoc.v:151913$7646_Y + connect \Y $and$libresoc.v:153197$7630_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:151914$7647 + cell $and $and$libresoc.v:153198$7631 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -314016,10 +285368,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \req_l_q_req connect \B { \$102 \$104 \$106 \$108 } - connect \Y $and$libresoc.v:151914$7647_Y + connect \Y $and$libresoc.v:153198$7631_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:151915$7648 + cell $and $and$libresoc.v:153199$7632 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -314027,10 +285379,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \$110 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:151915$7648_Y + connect \Y $and$libresoc.v:153199$7632_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:151916$7649 + cell $and $and$libresoc.v:153200$7633 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314038,10 +285390,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:151916$7649_Y + connect \Y $and$libresoc.v:153200$7633_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:151917$7650 + cell $and $and$libresoc.v:153201$7634 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314049,10 +285401,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:151917$7650_Y + connect \Y $and$libresoc.v:153201$7634_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:151918$7651 + cell $and $and$libresoc.v:153202$7635 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314060,10 +285412,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:151918$7651_Y + connect \Y $and$libresoc.v:153202$7635_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:151919$7652 + cell $and $and$libresoc.v:153203$7636 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314071,10 +285423,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o - connect \Y $and$libresoc.v:151919$7652_Y + connect \Y $and$libresoc.v:153203$7636_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:151921$7654 + cell $and $and$libresoc.v:153205$7638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314082,10 +285434,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$12 - connect \Y $and$libresoc.v:151921$7654_Y + connect \Y $and$libresoc.v:153205$7638_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:151923$7656 + cell $and $and$libresoc.v:153207$7640 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314093,10 +285445,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$16 - connect \Y $and$libresoc.v:151923$7656_Y + connect \Y $and$libresoc.v:153207$7640_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:151924$7657 + cell $and $and$libresoc.v:153208$7641 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -314104,10 +285456,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:151924$7657_Y + connect \Y $and$libresoc.v:153208$7641_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:151926$7659 + cell $and $and$libresoc.v:153210$7643 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -314115,10 +285467,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \cu_wr__rel_o connect \B \$24 - connect \Y $and$libresoc.v:151926$7659_Y + connect \Y $and$libresoc.v:153210$7643_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:151929$7662 + cell $and $and$libresoc.v:153213$7646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314126,10 +285478,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:151929$7662_Y + connect \Y $and$libresoc.v:153213$7646_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:151930$7663 + cell $and $and$libresoc.v:153214$7647 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314137,10 +285489,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$22 - connect \Y $and$libresoc.v:151930$7663_Y + connect \Y $and$libresoc.v:153214$7647_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:151935$7668 + cell $and $and$libresoc.v:153219$7652 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314148,10 +285500,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$38 - connect \Y $and$libresoc.v:151935$7668_Y + connect \Y $and$libresoc.v:153219$7652_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:151936$7669 + cell $and $and$libresoc.v:153220$7653 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -314159,10 +285511,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:151936$7669_Y + connect \Y $and$libresoc.v:153220$7653_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:151938$7671 + cell $and $and$libresoc.v:153222$7655 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314170,10 +285522,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$40 connect \B \$44 - connect \Y $and$libresoc.v:151938$7671_Y + connect \Y $and$libresoc.v:153222$7655_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:151940$7673 + cell $and $and$libresoc.v:153224$7657 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314181,10 +285533,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$48 connect \B \alu_mul0_n_ready_i - connect \Y $and$libresoc.v:151940$7673_Y + connect \Y $and$libresoc.v:153224$7657_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:151941$7674 + cell $and $and$libresoc.v:153225$7658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314192,10 +285544,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$50 connect \B \alu_mul0_n_valid_o - connect \Y $and$libresoc.v:151941$7674_Y + connect \Y $and$libresoc.v:153225$7658_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:151942$7675 + cell $and $and$libresoc.v:153226$7659 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314203,10 +285555,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$52 connect \B \cu_busy_o - connect \Y $and$libresoc.v:151942$7675_Y + connect \Y $and$libresoc.v:153226$7659_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:151948$7681 + cell $and $and$libresoc.v:153232$7665 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314214,10 +285566,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \alu_mul0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:151948$7681_Y + connect \Y $and$libresoc.v:153232$7665_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:151949$7682 + cell $and $and$libresoc.v:153233$7666 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -314225,10 +285577,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:151949$7682_Y + connect \Y $and$libresoc.v:153233$7666_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:151951$7684 + cell $and $and$libresoc.v:153235$7668 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314236,10 +285588,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:151951$7684_Y + connect \Y $and$libresoc.v:153235$7668_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:151952$7685 + cell $and $and$libresoc.v:153236$7669 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314247,10 +285599,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:151952$7685_Y + connect \Y $and$libresoc.v:153236$7669_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:151953$7686 + cell $and $and$libresoc.v:153237$7670 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314258,10 +285610,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \xer_ov_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:151953$7686_Y + connect \Y $and$libresoc.v:153237$7670_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:151954$7687 + cell $and $and$libresoc.v:153238$7671 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314269,10 +285621,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \xer_so_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:151954$7687_Y + connect \Y $and$libresoc.v:153238$7671_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:151961$7694 + cell $and $and$libresoc.v:153245$7678 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314280,10 +285632,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \alu_mul0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:151961$7694_Y + connect \Y $and$libresoc.v:153245$7678_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:151963$7696 + cell $and $and$libresoc.v:153247$7680 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314291,10 +285643,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \alu_mul0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:151963$7696_Y + connect \Y $and$libresoc.v:153247$7680_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:151964$7697 + cell $and $and$libresoc.v:153248$7681 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -314302,10 +285654,10 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:151964$7697_Y + connect \Y $and$libresoc.v:153248$7681_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:151966$7699 + cell $and $and$libresoc.v:153250$7683 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -314313,10 +285665,10 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \$92 connect \B { 1'1 \$94 1'1 } - connect \Y $and$libresoc.v:151966$7699_Y + connect \Y $and$libresoc.v:153250$7683_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:151937$7670 + cell $eq $eq$libresoc.v:153221$7654 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -314324,10 +285676,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$42 connect \B 1'0 - connect \Y $eq$libresoc.v:151937$7670_Y + connect \Y $eq$libresoc.v:153221$7654_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:151939$7672 + cell $eq $eq$libresoc.v:153223$7656 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -314335,74 +285687,74 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:151939$7672_Y + connect \Y $eq$libresoc.v:153223$7656_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:151920$7653 + cell $not $not$libresoc.v:153204$7637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:151920$7653_Y + connect \Y $not$libresoc.v:153204$7637_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:151922$7655 + cell $not $not$libresoc.v:153206$7639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:151922$7655_Y + connect \Y $not$libresoc.v:153206$7639_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:151925$7658 + cell $not $not$libresoc.v:153209$7642 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:151925$7658_Y + connect \Y $not$libresoc.v:153209$7642_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:151928$7661 + cell $not $not$libresoc.v:153212$7645 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$23 - connect \Y $not$libresoc.v:151928$7661_Y + connect \Y $not$libresoc.v:153212$7645_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:151934$7667 + cell $not $not$libresoc.v:153218$7651 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_mul0_n_ready_i - connect \Y $not$libresoc.v:151934$7667_Y + connect \Y $not$libresoc.v:153218$7651_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:151945$7678 + cell $not $not$libresoc.v:153229$7662 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:151945$7678_Y + connect \Y $not$libresoc.v:153229$7662_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:151965$7698 + cell $not $not$libresoc.v:153249$7682 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_mul0_mul_op__imm_data__ok - connect \Y $not$libresoc.v:151965$7698_Y + connect \Y $not$libresoc.v:153249$7682_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:151967$7700 + cell $not $not$libresoc.v:153251$7684 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:151967$7700_Y + connect \Y $not$libresoc.v:153251$7684_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:151933$7666 + cell $or $or$libresoc.v:153217$7650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314410,10 +285762,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \$32 connect \B \$34 - connect \Y $or$libresoc.v:151933$7666_Y + connect \Y $or$libresoc.v:153217$7650_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:151943$7676 + cell $or $or$libresoc.v:153227$7660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314421,10 +285773,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:151943$7676_Y + connect \Y $or$libresoc.v:153227$7660_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:151944$7677 + cell $or $or$libresoc.v:153228$7661 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -314432,10 +285784,10 @@ module \mul0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:151944$7677_Y + connect \Y $or$libresoc.v:153228$7661_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:151946$7679 + cell $or $or$libresoc.v:153230$7663 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -314443,10 +285795,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:151946$7679_Y + connect \Y $or$libresoc.v:153230$7663_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:151947$7680 + cell $or $or$libresoc.v:153231$7664 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -314454,10 +285806,10 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:151947$7680_Y + connect \Y $or$libresoc.v:153231$7664_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:151950$7683 + cell $or $or$libresoc.v:153234$7667 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -314465,10 +285817,10 @@ module \mul0 parameter \Y_WIDTH 4 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:151950$7683_Y + connect \Y $or$libresoc.v:153234$7667_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:151956$7689 + cell $or $or$libresoc.v:153240$7673 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -314476,82 +285828,82 @@ module \mul0 parameter \Y_WIDTH 3 connect \A \$5 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:151956$7689_Y + connect \Y $or$libresoc.v:153240$7673_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:151962$7695 + cell $reduce_and $reduce_and$libresoc.v:153246$7679 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$7 - connect \Y $reduce_and$libresoc.v:151962$7695_Y + connect \Y $reduce_and$libresoc.v:153246$7679_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:151927$7660 + cell $reduce_or $reduce_or$libresoc.v:153211$7644 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \$26 - connect \Y $reduce_or$libresoc.v:151927$7660_Y + connect \Y $reduce_or$libresoc.v:153211$7644_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:151931$7664 + cell $reduce_or $reduce_or$libresoc.v:153215$7648 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:151931$7664_Y + connect \Y $reduce_or$libresoc.v:153215$7648_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:151932$7665 + cell $reduce_or $reduce_or$libresoc.v:153216$7649 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:151932$7665_Y + connect \Y $reduce_or$libresoc.v:153216$7649_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:151955$7688 + cell $mux $ternary$libresoc.v:153239$7672 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_mul0_mul_op__imm_data__ok - connect \Y $ternary$libresoc.v:151955$7688_Y + connect \Y $ternary$libresoc.v:153239$7672_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:151957$7690 + cell $mux $ternary$libresoc.v:153241$7674 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_mul0_mul_op__imm_data__data connect \S \alu_mul0_mul_op__imm_data__ok - connect \Y $ternary$libresoc.v:151957$7690_Y + connect \Y $ternary$libresoc.v:153241$7674_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:151958$7691 + cell $mux $ternary$libresoc.v:153242$7675 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:151958$7691_Y + connect \Y $ternary$libresoc.v:153242$7675_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:151959$7692 + cell $mux $ternary$libresoc.v:153243$7676 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:151959$7692_Y + connect \Y $ternary$libresoc.v:153243$7676_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:151960$7693 + cell $mux $ternary$libresoc.v:153244$7677 parameter \WIDTH 1 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:151960$7693_Y + connect \Y $ternary$libresoc.v:153244$7677_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:152044.15-152050.4" + attribute \src "libresoc.v:153328.15-153334.4" cell \alu_l$107 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -314560,7 +285912,7 @@ module \mul0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:152051.12-152081.4" + attribute \src "libresoc.v:153335.12-153365.4" cell \alu_mul0 \alu_mul0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -314593,7 +285945,7 @@ module \mul0 connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:152082.16-152088.4" + attribute \src "libresoc.v:153366.16-153372.4" cell \alui_l$106 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -314602,7 +285954,7 @@ module \mul0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:152089.15-152095.4" + attribute \src "libresoc.v:153373.15-153379.4" cell \opc_l$102 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -314611,7 +285963,7 @@ module \mul0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:152096.15-152102.4" + attribute \src "libresoc.v:153380.15-153386.4" cell \req_l$103 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -314620,7 +285972,7 @@ module \mul0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:152103.15-152109.4" + attribute \src "libresoc.v:153387.15-153393.4" cell \rok_l$105 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -314629,7 +285981,7 @@ module \mul0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:152110.15-152115.4" + attribute \src "libresoc.v:153394.15-153399.4" cell \rst_l$104 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -314637,7 +285989,7 @@ module \mul0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:152116.15-152122.4" + attribute \src "libresoc.v:153400.15-153406.4" cell \src_l$101 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -314645,592 +285997,592 @@ module \mul0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:151311.7-151311.20" - process $proc$libresoc.v:151311$7855 + attribute \src "libresoc.v:152595.7-152595.20" + process $proc$libresoc.v:152595$7839 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:151435.7-151435.24" - process $proc$libresoc.v:151435$7856 + attribute \src "libresoc.v:152719.7-152719.24" + process $proc$libresoc.v:152719$7840 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:151445.7-151445.26" - process $proc$libresoc.v:151445$7857 + attribute \src "libresoc.v:152729.7-152729.26" + process $proc$libresoc.v:152729$7841 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:151453.7-151453.25" - process $proc$libresoc.v:151453$7858 + attribute \src "libresoc.v:152737.7-152737.25" + process $proc$libresoc.v:152737$7842 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:151476.14-151476.49" - process $proc$libresoc.v:151476$7859 + attribute \src "libresoc.v:152760.14-152760.49" + process $proc$libresoc.v:152760$7843 assign { } { } assign $1\alu_mul0_mul_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_mul0_mul_op__fn_unit $1\alu_mul0_mul_op__fn_unit[13:0] end - attribute \src "libresoc.v:151480.14-151480.68" - process $proc$libresoc.v:151480$7860 + attribute \src "libresoc.v:152764.14-152764.68" + process $proc$libresoc.v:152764$7844 assign { } { } assign $1\alu_mul0_mul_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_mul0_mul_op__imm_data__data $1\alu_mul0_mul_op__imm_data__data[63:0] end - attribute \src "libresoc.v:151484.7-151484.43" - process $proc$libresoc.v:151484$7861 + attribute \src "libresoc.v:152768.7-152768.43" + process $proc$libresoc.v:152768$7845 assign { } { } assign $1\alu_mul0_mul_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__imm_data__ok $1\alu_mul0_mul_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:151488.14-151488.43" - process $proc$libresoc.v:151488$7862 + attribute \src "libresoc.v:152772.14-152772.43" + process $proc$libresoc.v:152772$7846 assign { } { } assign $1\alu_mul0_mul_op__insn[31:0] 0 sync always sync init update \alu_mul0_mul_op__insn $1\alu_mul0_mul_op__insn[31:0] end - attribute \src "libresoc.v:151567.13-151567.47" - process $proc$libresoc.v:151567$7863 + attribute \src "libresoc.v:152851.13-152851.47" + process $proc$libresoc.v:152851$7847 assign { } { } assign $1\alu_mul0_mul_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_mul0_mul_op__insn_type $1\alu_mul0_mul_op__insn_type[6:0] end - attribute \src "libresoc.v:151571.7-151571.39" - process $proc$libresoc.v:151571$7864 + attribute \src "libresoc.v:152855.7-152855.39" + process $proc$libresoc.v:152855$7848 assign { } { } assign $1\alu_mul0_mul_op__is_32bit[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__is_32bit $1\alu_mul0_mul_op__is_32bit[0:0] end - attribute \src "libresoc.v:151575.7-151575.40" - process $proc$libresoc.v:151575$7865 + attribute \src "libresoc.v:152859.7-152859.40" + process $proc$libresoc.v:152859$7849 assign { } { } assign $1\alu_mul0_mul_op__is_signed[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__is_signed $1\alu_mul0_mul_op__is_signed[0:0] end - attribute \src "libresoc.v:151579.7-151579.37" - process $proc$libresoc.v:151579$7866 + attribute \src "libresoc.v:152863.7-152863.37" + process $proc$libresoc.v:152863$7850 assign { } { } assign $1\alu_mul0_mul_op__oe__oe[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__oe__oe $1\alu_mul0_mul_op__oe__oe[0:0] end - attribute \src "libresoc.v:151583.7-151583.37" - process $proc$libresoc.v:151583$7867 + attribute \src "libresoc.v:152867.7-152867.37" + process $proc$libresoc.v:152867$7851 assign { } { } assign $1\alu_mul0_mul_op__oe__ok[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__oe__ok $1\alu_mul0_mul_op__oe__ok[0:0] end - attribute \src "libresoc.v:151587.7-151587.37" - process $proc$libresoc.v:151587$7868 + attribute \src "libresoc.v:152871.7-152871.37" + process $proc$libresoc.v:152871$7852 assign { } { } assign $1\alu_mul0_mul_op__rc__ok[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__rc__ok $1\alu_mul0_mul_op__rc__ok[0:0] end - attribute \src "libresoc.v:151591.7-151591.37" - process $proc$libresoc.v:151591$7869 + attribute \src "libresoc.v:152875.7-152875.37" + process $proc$libresoc.v:152875$7853 assign { } { } assign $1\alu_mul0_mul_op__rc__rc[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__rc__rc $1\alu_mul0_mul_op__rc__rc[0:0] end - attribute \src "libresoc.v:151595.7-151595.40" - process $proc$libresoc.v:151595$7870 + attribute \src "libresoc.v:152879.7-152879.40" + process $proc$libresoc.v:152879$7854 assign { } { } assign $1\alu_mul0_mul_op__write_cr0[0:0] 1'0 sync always sync init update \alu_mul0_mul_op__write_cr0 $1\alu_mul0_mul_op__write_cr0[0:0] end - attribute \src "libresoc.v:151625.7-151625.27" - process $proc$libresoc.v:151625$7871 + attribute \src "libresoc.v:152909.7-152909.27" + process $proc$libresoc.v:152909$7855 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:151659.14-151659.47" - process $proc$libresoc.v:151659$7872 + attribute \src "libresoc.v:152943.14-152943.47" + process $proc$libresoc.v:152943$7856 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:151663.7-151663.27" - process $proc$libresoc.v:151663$7873 + attribute \src "libresoc.v:152947.7-152947.27" + process $proc$libresoc.v:152947$7857 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:151667.13-151667.33" - process $proc$libresoc.v:151667$7874 + attribute \src "libresoc.v:152951.13-152951.33" + process $proc$libresoc.v:152951$7858 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:151671.7-151671.30" - process $proc$libresoc.v:151671$7875 + attribute \src "libresoc.v:152955.7-152955.30" + process $proc$libresoc.v:152955$7859 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:151675.13-151675.35" - process $proc$libresoc.v:151675$7876 + attribute \src "libresoc.v:152959.13-152959.35" + process $proc$libresoc.v:152959$7860 assign { } { } assign $1\data_r2__xer_ov[1:0] 2'00 sync always sync init update \data_r2__xer_ov $1\data_r2__xer_ov[1:0] end - attribute \src "libresoc.v:151679.7-151679.32" - process $proc$libresoc.v:151679$7877 + attribute \src "libresoc.v:152963.7-152963.32" + process $proc$libresoc.v:152963$7861 assign { } { } assign $1\data_r2__xer_ov_ok[0:0] 1'0 sync always sync init update \data_r2__xer_ov_ok $1\data_r2__xer_ov_ok[0:0] end - attribute \src "libresoc.v:151683.7-151683.29" - process $proc$libresoc.v:151683$7878 + attribute \src "libresoc.v:152967.7-152967.29" + process $proc$libresoc.v:152967$7862 assign { } { } assign $1\data_r3__xer_so[0:0] 1'0 sync always sync init update \data_r3__xer_so $1\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:151687.7-151687.32" - process $proc$libresoc.v:151687$7879 + attribute \src "libresoc.v:152971.7-152971.32" + process $proc$libresoc.v:152971$7863 assign { } { } assign $1\data_r3__xer_so_ok[0:0] 1'0 sync always sync init update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:151707.7-151707.25" - process $proc$libresoc.v:151707$7880 + attribute \src "libresoc.v:152991.7-152991.25" + process $proc$libresoc.v:152991$7864 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:151711.7-151711.25" - process $proc$libresoc.v:151711$7881 + attribute \src "libresoc.v:152995.7-152995.25" + process $proc$libresoc.v:152995$7865 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:151829.13-151829.30" - process $proc$libresoc.v:151829$7882 + attribute \src "libresoc.v:153113.13-153113.30" + process $proc$libresoc.v:153113$7866 assign { } { } assign $1\prev_wr_go[3:0] 4'0000 sync always sync init update \prev_wr_go $1\prev_wr_go[3:0] end - attribute \src "libresoc.v:151837.13-151837.31" - process $proc$libresoc.v:151837$7883 + attribute \src "libresoc.v:153121.13-153121.31" + process $proc$libresoc.v:153121$7867 assign { } { } assign $1\req_l_r_req[3:0] 4'1111 sync always sync init update \req_l_r_req $1\req_l_r_req[3:0] end - attribute \src "libresoc.v:151841.13-151841.31" - process $proc$libresoc.v:151841$7884 + attribute \src "libresoc.v:153125.13-153125.31" + process $proc$libresoc.v:153125$7868 assign { } { } assign $1\req_l_s_req[3:0] 4'0000 sync always sync init update \req_l_s_req $1\req_l_s_req[3:0] end - attribute \src "libresoc.v:151853.7-151853.26" - process $proc$libresoc.v:151853$7885 + attribute \src "libresoc.v:153137.7-153137.26" + process $proc$libresoc.v:153137$7869 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:151857.7-151857.26" - process $proc$libresoc.v:151857$7886 + attribute \src "libresoc.v:153141.7-153141.26" + process $proc$libresoc.v:153141$7870 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:151861.7-151861.25" - process $proc$libresoc.v:151861$7887 + attribute \src "libresoc.v:153145.7-153145.25" + process $proc$libresoc.v:153145$7871 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:151865.7-151865.25" - process $proc$libresoc.v:151865$7888 + attribute \src "libresoc.v:153149.7-153149.25" + process $proc$libresoc.v:153149$7872 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:151879.13-151879.31" - process $proc$libresoc.v:151879$7889 + attribute \src "libresoc.v:153163.13-153163.31" + process $proc$libresoc.v:153163$7873 assign { } { } assign $1\src_l_r_src[2:0] 3'111 sync always sync init update \src_l_r_src $1\src_l_r_src[2:0] end - attribute \src "libresoc.v:151883.13-151883.31" - process $proc$libresoc.v:151883$7890 + attribute \src "libresoc.v:153167.13-153167.31" + process $proc$libresoc.v:153167$7874 assign { } { } assign $1\src_l_s_src[2:0] 3'000 sync always sync init update \src_l_s_src $1\src_l_s_src[2:0] end - attribute \src "libresoc.v:151889.14-151889.43" - process $proc$libresoc.v:151889$7891 + attribute \src "libresoc.v:153173.14-153173.43" + process $proc$libresoc.v:153173$7875 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:151893.14-151893.43" - process $proc$libresoc.v:151893$7892 + attribute \src "libresoc.v:153177.14-153177.43" + process $proc$libresoc.v:153177$7876 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:151897.7-151897.20" - process $proc$libresoc.v:151897$7893 + attribute \src "libresoc.v:153181.7-153181.20" + process $proc$libresoc.v:153181$7877 assign { } { } assign $1\src_r2[0:0] 1'0 sync always sync init update \src_r2 $1\src_r2[0:0] end - attribute \src "libresoc.v:151968.3-151969.39" - process $proc$libresoc.v:151968$7701 + attribute \src "libresoc.v:153252.3-153253.39" + process $proc$libresoc.v:153252$7685 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:151970.3-151971.43" - process $proc$libresoc.v:151970$7702 + attribute \src "libresoc.v:153254.3-153255.43" + process $proc$libresoc.v:153254$7686 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:151972.3-151973.29" - process $proc$libresoc.v:151972$7703 + attribute \src "libresoc.v:153256.3-153257.29" + process $proc$libresoc.v:153256$7687 assign { } { } assign $0\src_r2[0:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[0:0] end - attribute \src "libresoc.v:151974.3-151975.29" - process $proc$libresoc.v:151974$7704 + attribute \src "libresoc.v:153258.3-153259.29" + process $proc$libresoc.v:153258$7688 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:151976.3-151977.29" - process $proc$libresoc.v:151976$7705 + attribute \src "libresoc.v:153260.3-153261.29" + process $proc$libresoc.v:153260$7689 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:151978.3-151979.47" - process $proc$libresoc.v:151978$7706 + attribute \src "libresoc.v:153262.3-153263.47" + process $proc$libresoc.v:153262$7690 assign { } { } assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next sync posedge \coresync_clk update \data_r3__xer_so $0\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:151980.3-151981.53" - process $proc$libresoc.v:151980$7707 + attribute \src "libresoc.v:153264.3-153265.53" + process $proc$libresoc.v:153264$7691 assign { } { } assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next sync posedge \coresync_clk update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:151982.3-151983.47" - process $proc$libresoc.v:151982$7708 + attribute \src "libresoc.v:153266.3-153267.47" + process $proc$libresoc.v:153266$7692 assign { } { } assign $0\data_r2__xer_ov[1:0] \data_r2__xer_ov$next sync posedge \coresync_clk update \data_r2__xer_ov $0\data_r2__xer_ov[1:0] end - attribute \src "libresoc.v:151984.3-151985.53" - process $proc$libresoc.v:151984$7709 + attribute \src "libresoc.v:153268.3-153269.53" + process $proc$libresoc.v:153268$7693 assign { } { } assign $0\data_r2__xer_ov_ok[0:0] \data_r2__xer_ov_ok$next sync posedge \coresync_clk update \data_r2__xer_ov_ok $0\data_r2__xer_ov_ok[0:0] end - attribute \src "libresoc.v:151986.3-151987.43" - process $proc$libresoc.v:151986$7710 + attribute \src "libresoc.v:153270.3-153271.43" + process $proc$libresoc.v:153270$7694 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:151988.3-151989.49" - process $proc$libresoc.v:151988$7711 + attribute \src "libresoc.v:153272.3-153273.49" + process $proc$libresoc.v:153272$7695 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:151990.3-151991.37" - process $proc$libresoc.v:151990$7712 + attribute \src "libresoc.v:153274.3-153275.37" + process $proc$libresoc.v:153274$7696 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:151992.3-151993.43" - process $proc$libresoc.v:151992$7713 + attribute \src "libresoc.v:153276.3-153277.43" + process $proc$libresoc.v:153276$7697 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:151994.3-151995.69" - process $proc$libresoc.v:151994$7714 + attribute \src "libresoc.v:153278.3-153279.69" + process $proc$libresoc.v:153278$7698 assign { } { } assign $0\alu_mul0_mul_op__insn_type[6:0] \alu_mul0_mul_op__insn_type$next sync posedge \coresync_clk update \alu_mul0_mul_op__insn_type $0\alu_mul0_mul_op__insn_type[6:0] end - attribute \src "libresoc.v:151996.3-151997.65" - process $proc$libresoc.v:151996$7715 + attribute \src "libresoc.v:153280.3-153281.65" + process $proc$libresoc.v:153280$7699 assign { } { } assign $0\alu_mul0_mul_op__fn_unit[13:0] \alu_mul0_mul_op__fn_unit$next sync posedge \coresync_clk update \alu_mul0_mul_op__fn_unit $0\alu_mul0_mul_op__fn_unit[13:0] end - attribute \src "libresoc.v:151998.3-151999.79" - process $proc$libresoc.v:151998$7716 + attribute \src "libresoc.v:153282.3-153283.79" + process $proc$libresoc.v:153282$7700 assign { } { } assign $0\alu_mul0_mul_op__imm_data__data[63:0] \alu_mul0_mul_op__imm_data__data$next sync posedge \coresync_clk update \alu_mul0_mul_op__imm_data__data $0\alu_mul0_mul_op__imm_data__data[63:0] end - attribute \src "libresoc.v:152000.3-152001.75" - process $proc$libresoc.v:152000$7717 + attribute \src "libresoc.v:153284.3-153285.75" + process $proc$libresoc.v:153284$7701 assign { } { } assign $0\alu_mul0_mul_op__imm_data__ok[0:0] \alu_mul0_mul_op__imm_data__ok$next sync posedge \coresync_clk update \alu_mul0_mul_op__imm_data__ok $0\alu_mul0_mul_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:152002.3-152003.63" - process $proc$libresoc.v:152002$7718 + attribute \src "libresoc.v:153286.3-153287.63" + process $proc$libresoc.v:153286$7702 assign { } { } assign $0\alu_mul0_mul_op__rc__rc[0:0] \alu_mul0_mul_op__rc__rc$next sync posedge \coresync_clk update \alu_mul0_mul_op__rc__rc $0\alu_mul0_mul_op__rc__rc[0:0] end - attribute \src "libresoc.v:152004.3-152005.63" - process $proc$libresoc.v:152004$7719 + attribute \src "libresoc.v:153288.3-153289.63" + process $proc$libresoc.v:153288$7703 assign { } { } assign $0\alu_mul0_mul_op__rc__ok[0:0] \alu_mul0_mul_op__rc__ok$next sync posedge \coresync_clk update \alu_mul0_mul_op__rc__ok $0\alu_mul0_mul_op__rc__ok[0:0] end - attribute \src "libresoc.v:152006.3-152007.63" - process $proc$libresoc.v:152006$7720 + attribute \src "libresoc.v:153290.3-153291.63" + process $proc$libresoc.v:153290$7704 assign { } { } assign $0\alu_mul0_mul_op__oe__oe[0:0] \alu_mul0_mul_op__oe__oe$next sync posedge \coresync_clk update \alu_mul0_mul_op__oe__oe $0\alu_mul0_mul_op__oe__oe[0:0] end - attribute \src "libresoc.v:152008.3-152009.63" - process $proc$libresoc.v:152008$7721 + attribute \src "libresoc.v:153292.3-153293.63" + process $proc$libresoc.v:153292$7705 assign { } { } assign $0\alu_mul0_mul_op__oe__ok[0:0] \alu_mul0_mul_op__oe__ok$next sync posedge \coresync_clk update \alu_mul0_mul_op__oe__ok $0\alu_mul0_mul_op__oe__ok[0:0] end - attribute \src "libresoc.v:152010.3-152011.69" - process $proc$libresoc.v:152010$7722 + attribute \src "libresoc.v:153294.3-153295.69" + process $proc$libresoc.v:153294$7706 assign { } { } assign $0\alu_mul0_mul_op__write_cr0[0:0] \alu_mul0_mul_op__write_cr0$next sync posedge \coresync_clk update \alu_mul0_mul_op__write_cr0 $0\alu_mul0_mul_op__write_cr0[0:0] end - attribute \src "libresoc.v:152012.3-152013.67" - process $proc$libresoc.v:152012$7723 + attribute \src "libresoc.v:153296.3-153297.67" + process $proc$libresoc.v:153296$7707 assign { } { } assign $0\alu_mul0_mul_op__is_32bit[0:0] \alu_mul0_mul_op__is_32bit$next sync posedge \coresync_clk update \alu_mul0_mul_op__is_32bit $0\alu_mul0_mul_op__is_32bit[0:0] end - attribute \src "libresoc.v:152014.3-152015.69" - process $proc$libresoc.v:152014$7724 + attribute \src "libresoc.v:153298.3-153299.69" + process $proc$libresoc.v:153298$7708 assign { } { } assign $0\alu_mul0_mul_op__is_signed[0:0] \alu_mul0_mul_op__is_signed$next sync posedge \coresync_clk update \alu_mul0_mul_op__is_signed $0\alu_mul0_mul_op__is_signed[0:0] end - attribute \src "libresoc.v:152016.3-152017.59" - process $proc$libresoc.v:152016$7725 + attribute \src "libresoc.v:153300.3-153301.59" + process $proc$libresoc.v:153300$7709 assign { } { } assign $0\alu_mul0_mul_op__insn[31:0] \alu_mul0_mul_op__insn$next sync posedge \coresync_clk update \alu_mul0_mul_op__insn $0\alu_mul0_mul_op__insn[31:0] end - attribute \src "libresoc.v:152018.3-152019.39" - process $proc$libresoc.v:152018$7726 + attribute \src "libresoc.v:153302.3-153303.39" + process $proc$libresoc.v:153302$7710 assign { } { } assign $0\req_l_r_req[3:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[3:0] end - attribute \src "libresoc.v:152020.3-152021.39" - process $proc$libresoc.v:152020$7727 + attribute \src "libresoc.v:153304.3-153305.39" + process $proc$libresoc.v:153304$7711 assign { } { } assign $0\req_l_s_req[3:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[3:0] end - attribute \src "libresoc.v:152022.3-152023.39" - process $proc$libresoc.v:152022$7728 + attribute \src "libresoc.v:153306.3-153307.39" + process $proc$libresoc.v:153306$7712 assign { } { } assign $0\src_l_r_src[2:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[2:0] end - attribute \src "libresoc.v:152024.3-152025.39" - process $proc$libresoc.v:152024$7729 + attribute \src "libresoc.v:153308.3-153309.39" + process $proc$libresoc.v:153308$7713 assign { } { } assign $0\src_l_s_src[2:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[2:0] end - attribute \src "libresoc.v:152026.3-152027.39" - process $proc$libresoc.v:152026$7730 + attribute \src "libresoc.v:153310.3-153311.39" + process $proc$libresoc.v:153310$7714 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:152028.3-152029.39" - process $proc$libresoc.v:152028$7731 + attribute \src "libresoc.v:153312.3-153313.39" + process $proc$libresoc.v:153312$7715 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:152030.3-152031.39" - process $proc$libresoc.v:152030$7732 + attribute \src "libresoc.v:153314.3-153315.39" + process $proc$libresoc.v:153314$7716 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:152032.3-152033.39" - process $proc$libresoc.v:152032$7733 + attribute \src "libresoc.v:153316.3-153317.39" + process $proc$libresoc.v:153316$7717 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:152034.3-152035.41" - process $proc$libresoc.v:152034$7734 + attribute \src "libresoc.v:153318.3-153319.41" + process $proc$libresoc.v:153318$7718 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:152036.3-152037.41" - process $proc$libresoc.v:152036$7735 + attribute \src "libresoc.v:153320.3-153321.41" + process $proc$libresoc.v:153320$7719 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:152038.3-152039.37" - process $proc$libresoc.v:152038$7736 + attribute \src "libresoc.v:153322.3-153323.37" + process $proc$libresoc.v:153322$7720 assign { } { } assign $0\prev_wr_go[3:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[3:0] end - attribute \src "libresoc.v:152040.3-152041.40" - process $proc$libresoc.v:152040$7737 + attribute \src "libresoc.v:153324.3-153325.40" + process $proc$libresoc.v:153324$7721 assign { } { } assign $0\alu_done_dly[0:0] \alu_mul0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:152042.3-152043.25" - process $proc$libresoc.v:152042$7738 + attribute \src "libresoc.v:153326.3-153327.25" + process $proc$libresoc.v:153326$7722 assign { } { } assign $0\all_rd_dly[0:0] \$10 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:152123.3-152132.6" - process $proc$libresoc.v:152123$7739 + attribute \src "libresoc.v:153407.3-153416.6" + process $proc$libresoc.v:153407$7723 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:152124.5-152124.29" + attribute \src "libresoc.v:153408.5-153408.29" switch \initial - attribute \src "libresoc.v:152124.9-152124.17" + attribute \src "libresoc.v:153408.9-153408.17" case 1'1 case end @@ -315246,14 +286598,14 @@ module \mul0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:152133.3-152141.6" - process $proc$libresoc.v:152133$7740 + attribute \src "libresoc.v:153417.3-153425.6" + process $proc$libresoc.v:153417$7724 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$7741 $1\rok_l_s_rdok$next[0:0]$7742 - attribute \src "libresoc.v:152134.5-152134.29" + assign $0\rok_l_s_rdok$next[0:0]$7725 $1\rok_l_s_rdok$next[0:0]$7726 + attribute \src "libresoc.v:153418.5-153418.29" switch \initial - attribute \src "libresoc.v:152134.9-152134.17" + attribute \src "libresoc.v:153418.9-153418.17" case 1'1 case end @@ -315262,21 +286614,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$7742 1'0 + assign $1\rok_l_s_rdok$next[0:0]$7726 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$7742 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$7726 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$7741 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$7725 end - attribute \src "libresoc.v:152142.3-152150.6" - process $proc$libresoc.v:152142$7743 + attribute \src "libresoc.v:153426.3-153434.6" + process $proc$libresoc.v:153426$7727 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$7744 $1\rok_l_r_rdok$next[0:0]$7745 - attribute \src "libresoc.v:152143.5-152143.29" + assign $0\rok_l_r_rdok$next[0:0]$7728 $1\rok_l_r_rdok$next[0:0]$7729 + attribute \src "libresoc.v:153427.5-153427.29" switch \initial - attribute \src "libresoc.v:152143.9-152143.17" + attribute \src "libresoc.v:153427.9-153427.17" case 1'1 case end @@ -315285,21 +286637,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$7745 1'1 + assign $1\rok_l_r_rdok$next[0:0]$7729 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$7745 \$64 + assign $1\rok_l_r_rdok$next[0:0]$7729 \$64 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$7744 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$7728 end - attribute \src "libresoc.v:152151.3-152159.6" - process $proc$libresoc.v:152151$7746 + attribute \src "libresoc.v:153435.3-153443.6" + process $proc$libresoc.v:153435$7730 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$7747 $1\rst_l_s_rst$next[0:0]$7748 - attribute \src "libresoc.v:152152.5-152152.29" + assign $0\rst_l_s_rst$next[0:0]$7731 $1\rst_l_s_rst$next[0:0]$7732 + attribute \src "libresoc.v:153436.5-153436.29" switch \initial - attribute \src "libresoc.v:152152.9-152152.17" + attribute \src "libresoc.v:153436.9-153436.17" case 1'1 case end @@ -315308,21 +286660,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$7748 1'0 + assign $1\rst_l_s_rst$next[0:0]$7732 1'0 case - assign $1\rst_l_s_rst$next[0:0]$7748 \all_rd + assign $1\rst_l_s_rst$next[0:0]$7732 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$7747 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$7731 end - attribute \src "libresoc.v:152160.3-152168.6" - process $proc$libresoc.v:152160$7749 + attribute \src "libresoc.v:153444.3-153452.6" + process $proc$libresoc.v:153444$7733 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$7750 $1\rst_l_r_rst$next[0:0]$7751 - attribute \src "libresoc.v:152161.5-152161.29" + assign $0\rst_l_r_rst$next[0:0]$7734 $1\rst_l_r_rst$next[0:0]$7735 + attribute \src "libresoc.v:153445.5-153445.29" switch \initial - attribute \src "libresoc.v:152161.9-152161.17" + attribute \src "libresoc.v:153445.9-153445.17" case 1'1 case end @@ -315331,21 +286683,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$7751 1'1 + assign $1\rst_l_r_rst$next[0:0]$7735 1'1 case - assign $1\rst_l_r_rst$next[0:0]$7751 \rst_r + assign $1\rst_l_r_rst$next[0:0]$7735 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$7750 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$7734 end - attribute \src "libresoc.v:152169.3-152177.6" - process $proc$libresoc.v:152169$7752 + attribute \src "libresoc.v:153453.3-153461.6" + process $proc$libresoc.v:153453$7736 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$7753 $1\opc_l_s_opc$next[0:0]$7754 - attribute \src "libresoc.v:152170.5-152170.29" + assign $0\opc_l_s_opc$next[0:0]$7737 $1\opc_l_s_opc$next[0:0]$7738 + attribute \src "libresoc.v:153454.5-153454.29" switch \initial - attribute \src "libresoc.v:152170.9-152170.17" + attribute \src "libresoc.v:153454.9-153454.17" case 1'1 case end @@ -315354,21 +286706,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$7754 1'0 + assign $1\opc_l_s_opc$next[0:0]$7738 1'0 case - assign $1\opc_l_s_opc$next[0:0]$7754 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$7738 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$7753 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$7737 end - attribute \src "libresoc.v:152178.3-152186.6" - process $proc$libresoc.v:152178$7755 + attribute \src "libresoc.v:153462.3-153470.6" + process $proc$libresoc.v:153462$7739 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$7756 $1\opc_l_r_opc$next[0:0]$7757 - attribute \src "libresoc.v:152179.5-152179.29" + assign $0\opc_l_r_opc$next[0:0]$7740 $1\opc_l_r_opc$next[0:0]$7741 + attribute \src "libresoc.v:153463.5-153463.29" switch \initial - attribute \src "libresoc.v:152179.9-152179.17" + attribute \src "libresoc.v:153463.9-153463.17" case 1'1 case end @@ -315377,21 +286729,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$7757 1'1 + assign $1\opc_l_r_opc$next[0:0]$7741 1'1 case - assign $1\opc_l_r_opc$next[0:0]$7757 \req_done + assign $1\opc_l_r_opc$next[0:0]$7741 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$7756 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$7740 end - attribute \src "libresoc.v:152187.3-152195.6" - process $proc$libresoc.v:152187$7758 + attribute \src "libresoc.v:153471.3-153479.6" + process $proc$libresoc.v:153471$7742 assign { } { } assign { } { } - assign $0\src_l_s_src$next[2:0]$7759 $1\src_l_s_src$next[2:0]$7760 - attribute \src "libresoc.v:152188.5-152188.29" + assign $0\src_l_s_src$next[2:0]$7743 $1\src_l_s_src$next[2:0]$7744 + attribute \src "libresoc.v:153472.5-153472.29" switch \initial - attribute \src "libresoc.v:152188.9-152188.17" + attribute \src "libresoc.v:153472.9-153472.17" case 1'1 case end @@ -315400,21 +286752,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[2:0]$7760 3'000 + assign $1\src_l_s_src$next[2:0]$7744 3'000 case - assign $1\src_l_s_src$next[2:0]$7760 { \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[2:0]$7744 { \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[2:0]$7759 + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$7743 end - attribute \src "libresoc.v:152196.3-152204.6" - process $proc$libresoc.v:152196$7761 + attribute \src "libresoc.v:153480.3-153488.6" + process $proc$libresoc.v:153480$7745 assign { } { } assign { } { } - assign $0\src_l_r_src$next[2:0]$7762 $1\src_l_r_src$next[2:0]$7763 - attribute \src "libresoc.v:152197.5-152197.29" + assign $0\src_l_r_src$next[2:0]$7746 $1\src_l_r_src$next[2:0]$7747 + attribute \src "libresoc.v:153481.5-153481.29" switch \initial - attribute \src "libresoc.v:152197.9-152197.17" + attribute \src "libresoc.v:153481.9-153481.17" case 1'1 case end @@ -315423,21 +286775,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[2:0]$7763 3'111 + assign $1\src_l_r_src$next[2:0]$7747 3'111 case - assign $1\src_l_r_src$next[2:0]$7763 \reset_r + assign $1\src_l_r_src$next[2:0]$7747 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[2:0]$7762 + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$7746 end - attribute \src "libresoc.v:152205.3-152213.6" - process $proc$libresoc.v:152205$7764 + attribute \src "libresoc.v:153489.3-153497.6" + process $proc$libresoc.v:153489$7748 assign { } { } assign { } { } - assign $0\req_l_s_req$next[3:0]$7765 $1\req_l_s_req$next[3:0]$7766 - attribute \src "libresoc.v:152206.5-152206.29" + assign $0\req_l_s_req$next[3:0]$7749 $1\req_l_s_req$next[3:0]$7750 + attribute \src "libresoc.v:153490.5-153490.29" switch \initial - attribute \src "libresoc.v:152206.9-152206.17" + attribute \src "libresoc.v:153490.9-153490.17" case 1'1 case end @@ -315446,21 +286798,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[3:0]$7766 4'0000 + assign $1\req_l_s_req$next[3:0]$7750 4'0000 case - assign $1\req_l_s_req$next[3:0]$7766 \$66 + assign $1\req_l_s_req$next[3:0]$7750 \$66 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[3:0]$7765 + update \req_l_s_req$next $0\req_l_s_req$next[3:0]$7749 end - attribute \src "libresoc.v:152214.3-152222.6" - process $proc$libresoc.v:152214$7767 + attribute \src "libresoc.v:153498.3-153506.6" + process $proc$libresoc.v:153498$7751 assign { } { } assign { } { } - assign $0\req_l_r_req$next[3:0]$7768 $1\req_l_r_req$next[3:0]$7769 - attribute \src "libresoc.v:152215.5-152215.29" + assign $0\req_l_r_req$next[3:0]$7752 $1\req_l_r_req$next[3:0]$7753 + attribute \src "libresoc.v:153499.5-153499.29" switch \initial - attribute \src "libresoc.v:152215.9-152215.17" + attribute \src "libresoc.v:153499.9-153499.17" case 1'1 case end @@ -315469,15 +286821,15 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[3:0]$7769 4'1111 + assign $1\req_l_r_req$next[3:0]$7753 4'1111 case - assign $1\req_l_r_req$next[3:0]$7769 \$68 + assign $1\req_l_r_req$next[3:0]$7753 \$68 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[3:0]$7768 + update \req_l_r_req$next $0\req_l_r_req$next[3:0]$7752 end - attribute \src "libresoc.v:152223.3-152255.6" - process $proc$libresoc.v:152223$7770 + attribute \src "libresoc.v:153507.3-153539.6" + process $proc$libresoc.v:153507$7754 assign { } { } assign { } { } assign { } { } @@ -315502,27 +286854,27 @@ module \mul0 assign { } { } assign { } { } assign { } { } - assign $0\alu_mul0_mul_op__fn_unit$next[13:0]$7771 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7783 + assign $0\alu_mul0_mul_op__fn_unit$next[13:0]$7755 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7767 assign { } { } assign { } { } - assign $0\alu_mul0_mul_op__insn$next[31:0]$7774 $1\alu_mul0_mul_op__insn$next[31:0]$7786 - assign $0\alu_mul0_mul_op__insn_type$next[6:0]$7775 $1\alu_mul0_mul_op__insn_type$next[6:0]$7787 - assign $0\alu_mul0_mul_op__is_32bit$next[0:0]$7776 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7788 - assign $0\alu_mul0_mul_op__is_signed$next[0:0]$7777 $1\alu_mul0_mul_op__is_signed$next[0:0]$7789 + assign $0\alu_mul0_mul_op__insn$next[31:0]$7758 $1\alu_mul0_mul_op__insn$next[31:0]$7770 + assign $0\alu_mul0_mul_op__insn_type$next[6:0]$7759 $1\alu_mul0_mul_op__insn_type$next[6:0]$7771 + assign $0\alu_mul0_mul_op__is_32bit$next[0:0]$7760 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7772 + assign $0\alu_mul0_mul_op__is_signed$next[0:0]$7761 $1\alu_mul0_mul_op__is_signed$next[0:0]$7773 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\alu_mul0_mul_op__write_cr0$next[0:0]$7782 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7794 - assign $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7772 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7795 - assign $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7773 $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7796 - assign $0\alu_mul0_mul_op__oe__oe$next[0:0]$7778 $2\alu_mul0_mul_op__oe__oe$next[0:0]$7797 - assign $0\alu_mul0_mul_op__oe__ok$next[0:0]$7779 $2\alu_mul0_mul_op__oe__ok$next[0:0]$7798 - assign $0\alu_mul0_mul_op__rc__ok$next[0:0]$7780 $2\alu_mul0_mul_op__rc__ok$next[0:0]$7799 - assign $0\alu_mul0_mul_op__rc__rc$next[0:0]$7781 $2\alu_mul0_mul_op__rc__rc$next[0:0]$7800 - attribute \src "libresoc.v:152224.5-152224.29" + assign $0\alu_mul0_mul_op__write_cr0$next[0:0]$7766 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7778 + assign $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7756 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7779 + assign $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7757 $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7780 + assign $0\alu_mul0_mul_op__oe__oe$next[0:0]$7762 $2\alu_mul0_mul_op__oe__oe$next[0:0]$7781 + assign $0\alu_mul0_mul_op__oe__ok$next[0:0]$7763 $2\alu_mul0_mul_op__oe__ok$next[0:0]$7782 + assign $0\alu_mul0_mul_op__rc__ok$next[0:0]$7764 $2\alu_mul0_mul_op__rc__ok$next[0:0]$7783 + assign $0\alu_mul0_mul_op__rc__rc$next[0:0]$7765 $2\alu_mul0_mul_op__rc__rc$next[0:0]$7784 + attribute \src "libresoc.v:153508.5-153508.29" switch \initial - attribute \src "libresoc.v:152224.9-152224.17" + attribute \src "libresoc.v:153508.9-153508.17" case 1'1 case end @@ -315542,20 +286894,20 @@ module \mul0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_mul0_mul_op__insn$next[31:0]$7786 $1\alu_mul0_mul_op__is_signed$next[0:0]$7789 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7788 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7794 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7791 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7790 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7792 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7793 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7785 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7784 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7783 $1\alu_mul0_mul_op__insn_type$next[6:0]$7787 } { \oper_i_alu_mul0__insn \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__oe__ok \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__imm_data__ok \oper_i_alu_mul0__imm_data__data \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__insn_type } + assign { $1\alu_mul0_mul_op__insn$next[31:0]$7770 $1\alu_mul0_mul_op__is_signed$next[0:0]$7773 $1\alu_mul0_mul_op__is_32bit$next[0:0]$7772 $1\alu_mul0_mul_op__write_cr0$next[0:0]$7778 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7775 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7774 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7776 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7777 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7769 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7768 $1\alu_mul0_mul_op__fn_unit$next[13:0]$7767 $1\alu_mul0_mul_op__insn_type$next[6:0]$7771 } { \oper_i_alu_mul0__insn \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__oe__ok \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__imm_data__ok \oper_i_alu_mul0__imm_data__data \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__insn_type } case - assign $1\alu_mul0_mul_op__fn_unit$next[13:0]$7783 \alu_mul0_mul_op__fn_unit - assign $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7784 \alu_mul0_mul_op__imm_data__data - assign $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7785 \alu_mul0_mul_op__imm_data__ok - assign $1\alu_mul0_mul_op__insn$next[31:0]$7786 \alu_mul0_mul_op__insn - assign $1\alu_mul0_mul_op__insn_type$next[6:0]$7787 \alu_mul0_mul_op__insn_type - assign $1\alu_mul0_mul_op__is_32bit$next[0:0]$7788 \alu_mul0_mul_op__is_32bit - assign $1\alu_mul0_mul_op__is_signed$next[0:0]$7789 \alu_mul0_mul_op__is_signed - assign $1\alu_mul0_mul_op__oe__oe$next[0:0]$7790 \alu_mul0_mul_op__oe__oe - assign $1\alu_mul0_mul_op__oe__ok$next[0:0]$7791 \alu_mul0_mul_op__oe__ok - assign $1\alu_mul0_mul_op__rc__ok$next[0:0]$7792 \alu_mul0_mul_op__rc__ok - assign $1\alu_mul0_mul_op__rc__rc$next[0:0]$7793 \alu_mul0_mul_op__rc__rc - assign $1\alu_mul0_mul_op__write_cr0$next[0:0]$7794 \alu_mul0_mul_op__write_cr0 + assign $1\alu_mul0_mul_op__fn_unit$next[13:0]$7767 \alu_mul0_mul_op__fn_unit + assign $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7768 \alu_mul0_mul_op__imm_data__data + assign $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7769 \alu_mul0_mul_op__imm_data__ok + assign $1\alu_mul0_mul_op__insn$next[31:0]$7770 \alu_mul0_mul_op__insn + assign $1\alu_mul0_mul_op__insn_type$next[6:0]$7771 \alu_mul0_mul_op__insn_type + assign $1\alu_mul0_mul_op__is_32bit$next[0:0]$7772 \alu_mul0_mul_op__is_32bit + assign $1\alu_mul0_mul_op__is_signed$next[0:0]$7773 \alu_mul0_mul_op__is_signed + assign $1\alu_mul0_mul_op__oe__oe$next[0:0]$7774 \alu_mul0_mul_op__oe__oe + assign $1\alu_mul0_mul_op__oe__ok$next[0:0]$7775 \alu_mul0_mul_op__oe__ok + assign $1\alu_mul0_mul_op__rc__ok$next[0:0]$7776 \alu_mul0_mul_op__rc__ok + assign $1\alu_mul0_mul_op__rc__rc$next[0:0]$7777 \alu_mul0_mul_op__rc__rc + assign $1\alu_mul0_mul_op__write_cr0$next[0:0]$7778 \alu_mul0_mul_op__write_cr0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -315567,48 +286919,48 @@ module \mul0 assign { } { } assign { } { } assign { } { } - assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7795 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7796 1'0 - assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7800 1'0 - assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7799 1'0 - assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7797 1'0 - assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7798 1'0 + assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7779 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7780 1'0 + assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7784 1'0 + assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7783 1'0 + assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7781 1'0 + assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7782 1'0 case - assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7795 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7784 - assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7796 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7785 - assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7797 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7790 - assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7798 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7791 - assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7799 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7792 - assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7800 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7793 + assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$7779 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$7768 + assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$7780 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$7769 + assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$7781 $1\alu_mul0_mul_op__oe__oe$next[0:0]$7774 + assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$7782 $1\alu_mul0_mul_op__oe__ok$next[0:0]$7775 + assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$7783 $1\alu_mul0_mul_op__rc__ok$next[0:0]$7776 + assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$7784 $1\alu_mul0_mul_op__rc__rc$next[0:0]$7777 end sync always - update \alu_mul0_mul_op__fn_unit$next $0\alu_mul0_mul_op__fn_unit$next[13:0]$7771 - update \alu_mul0_mul_op__imm_data__data$next $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7772 - update \alu_mul0_mul_op__imm_data__ok$next $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7773 - update \alu_mul0_mul_op__insn$next $0\alu_mul0_mul_op__insn$next[31:0]$7774 - update \alu_mul0_mul_op__insn_type$next $0\alu_mul0_mul_op__insn_type$next[6:0]$7775 - update \alu_mul0_mul_op__is_32bit$next $0\alu_mul0_mul_op__is_32bit$next[0:0]$7776 - update \alu_mul0_mul_op__is_signed$next $0\alu_mul0_mul_op__is_signed$next[0:0]$7777 - update \alu_mul0_mul_op__oe__oe$next $0\alu_mul0_mul_op__oe__oe$next[0:0]$7778 - update \alu_mul0_mul_op__oe__ok$next $0\alu_mul0_mul_op__oe__ok$next[0:0]$7779 - update \alu_mul0_mul_op__rc__ok$next $0\alu_mul0_mul_op__rc__ok$next[0:0]$7780 - update \alu_mul0_mul_op__rc__rc$next $0\alu_mul0_mul_op__rc__rc$next[0:0]$7781 - update \alu_mul0_mul_op__write_cr0$next $0\alu_mul0_mul_op__write_cr0$next[0:0]$7782 + update \alu_mul0_mul_op__fn_unit$next $0\alu_mul0_mul_op__fn_unit$next[13:0]$7755 + update \alu_mul0_mul_op__imm_data__data$next $0\alu_mul0_mul_op__imm_data__data$next[63:0]$7756 + update \alu_mul0_mul_op__imm_data__ok$next $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$7757 + update \alu_mul0_mul_op__insn$next $0\alu_mul0_mul_op__insn$next[31:0]$7758 + update \alu_mul0_mul_op__insn_type$next $0\alu_mul0_mul_op__insn_type$next[6:0]$7759 + update \alu_mul0_mul_op__is_32bit$next $0\alu_mul0_mul_op__is_32bit$next[0:0]$7760 + update \alu_mul0_mul_op__is_signed$next $0\alu_mul0_mul_op__is_signed$next[0:0]$7761 + update \alu_mul0_mul_op__oe__oe$next $0\alu_mul0_mul_op__oe__oe$next[0:0]$7762 + update \alu_mul0_mul_op__oe__ok$next $0\alu_mul0_mul_op__oe__ok$next[0:0]$7763 + update \alu_mul0_mul_op__rc__ok$next $0\alu_mul0_mul_op__rc__ok$next[0:0]$7764 + update \alu_mul0_mul_op__rc__rc$next $0\alu_mul0_mul_op__rc__rc$next[0:0]$7765 + update \alu_mul0_mul_op__write_cr0$next $0\alu_mul0_mul_op__write_cr0$next[0:0]$7766 end - attribute \src "libresoc.v:152256.3-152277.6" - process $proc$libresoc.v:152256$7801 + attribute \src "libresoc.v:153540.3-153561.6" + process $proc$libresoc.v:153540$7785 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$7802 $2\data_r0__o$next[63:0]$7806 + assign $0\data_r0__o$next[63:0]$7786 $2\data_r0__o$next[63:0]$7790 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$7803 $3\data_r0__o_ok$next[0:0]$7808 - attribute \src "libresoc.v:152257.5-152257.29" + assign $0\data_r0__o_ok$next[0:0]$7787 $3\data_r0__o_ok$next[0:0]$7792 + attribute \src "libresoc.v:153541.5-153541.29" switch \initial - attribute \src "libresoc.v:152257.9-152257.17" + attribute \src "libresoc.v:153541.9-153541.17" case 1'1 case end @@ -315618,10 +286970,10 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$7805 $1\data_r0__o$next[63:0]$7804 } { \o_ok \alu_mul0_o } + assign { $1\data_r0__o_ok$next[0:0]$7789 $1\data_r0__o$next[63:0]$7788 } { \o_ok \alu_mul0_o } case - assign $1\data_r0__o$next[63:0]$7804 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$7805 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$7788 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$7789 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -315629,38 +286981,38 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$7807 $2\data_r0__o$next[63:0]$7806 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$7791 $2\data_r0__o$next[63:0]$7790 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$7806 $1\data_r0__o$next[63:0]$7804 - assign $2\data_r0__o_ok$next[0:0]$7807 $1\data_r0__o_ok$next[0:0]$7805 + assign $2\data_r0__o$next[63:0]$7790 $1\data_r0__o$next[63:0]$7788 + assign $2\data_r0__o_ok$next[0:0]$7791 $1\data_r0__o_ok$next[0:0]$7789 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$7808 1'0 + assign $3\data_r0__o_ok$next[0:0]$7792 1'0 case - assign $3\data_r0__o_ok$next[0:0]$7808 $2\data_r0__o_ok$next[0:0]$7807 + assign $3\data_r0__o_ok$next[0:0]$7792 $2\data_r0__o_ok$next[0:0]$7791 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$7802 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$7803 + update \data_r0__o$next $0\data_r0__o$next[63:0]$7786 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$7787 end - attribute \src "libresoc.v:152278.3-152299.6" - process $proc$libresoc.v:152278$7809 + attribute \src "libresoc.v:153562.3-153583.6" + process $proc$libresoc.v:153562$7793 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__cr_a$next[3:0]$7810 $2\data_r1__cr_a$next[3:0]$7814 + assign $0\data_r1__cr_a$next[3:0]$7794 $2\data_r1__cr_a$next[3:0]$7798 assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$7811 $3\data_r1__cr_a_ok$next[0:0]$7816 - attribute \src "libresoc.v:152279.5-152279.29" + assign $0\data_r1__cr_a_ok$next[0:0]$7795 $3\data_r1__cr_a_ok$next[0:0]$7800 + attribute \src "libresoc.v:153563.5-153563.29" switch \initial - attribute \src "libresoc.v:152279.9-152279.17" + attribute \src "libresoc.v:153563.9-153563.17" case 1'1 case end @@ -315670,10 +287022,10 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$7813 $1\data_r1__cr_a$next[3:0]$7812 } { \cr_a_ok \alu_mul0_cr_a } + assign { $1\data_r1__cr_a_ok$next[0:0]$7797 $1\data_r1__cr_a$next[3:0]$7796 } { \cr_a_ok \alu_mul0_cr_a } case - assign $1\data_r1__cr_a$next[3:0]$7812 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$7813 \data_r1__cr_a_ok + assign $1\data_r1__cr_a$next[3:0]$7796 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$7797 \data_r1__cr_a_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -315681,38 +287033,38 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$7815 $2\data_r1__cr_a$next[3:0]$7814 } 5'00000 + assign { $2\data_r1__cr_a_ok$next[0:0]$7799 $2\data_r1__cr_a$next[3:0]$7798 } 5'00000 case - assign $2\data_r1__cr_a$next[3:0]$7814 $1\data_r1__cr_a$next[3:0]$7812 - assign $2\data_r1__cr_a_ok$next[0:0]$7815 $1\data_r1__cr_a_ok$next[0:0]$7813 + assign $2\data_r1__cr_a$next[3:0]$7798 $1\data_r1__cr_a$next[3:0]$7796 + assign $2\data_r1__cr_a_ok$next[0:0]$7799 $1\data_r1__cr_a_ok$next[0:0]$7797 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$7816 1'0 + assign $3\data_r1__cr_a_ok$next[0:0]$7800 1'0 case - assign $3\data_r1__cr_a_ok$next[0:0]$7816 $2\data_r1__cr_a_ok$next[0:0]$7815 + assign $3\data_r1__cr_a_ok$next[0:0]$7800 $2\data_r1__cr_a_ok$next[0:0]$7799 end sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$7810 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$7811 + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$7794 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$7795 end - attribute \src "libresoc.v:152300.3-152321.6" - process $proc$libresoc.v:152300$7817 + attribute \src "libresoc.v:153584.3-153605.6" + process $proc$libresoc.v:153584$7801 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__xer_ov$next[1:0]$7818 $2\data_r2__xer_ov$next[1:0]$7822 + assign $0\data_r2__xer_ov$next[1:0]$7802 $2\data_r2__xer_ov$next[1:0]$7806 assign { } { } - assign $0\data_r2__xer_ov_ok$next[0:0]$7819 $3\data_r2__xer_ov_ok$next[0:0]$7824 - attribute \src "libresoc.v:152301.5-152301.29" + assign $0\data_r2__xer_ov_ok$next[0:0]$7803 $3\data_r2__xer_ov_ok$next[0:0]$7808 + attribute \src "libresoc.v:153585.5-153585.29" switch \initial - attribute \src "libresoc.v:152301.9-152301.17" + attribute \src "libresoc.v:153585.9-153585.17" case 1'1 case end @@ -315722,10 +287074,10 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__xer_ov_ok$next[0:0]$7821 $1\data_r2__xer_ov$next[1:0]$7820 } { \xer_ov_ok \alu_mul0_xer_ov } + assign { $1\data_r2__xer_ov_ok$next[0:0]$7805 $1\data_r2__xer_ov$next[1:0]$7804 } { \xer_ov_ok \alu_mul0_xer_ov } case - assign $1\data_r2__xer_ov$next[1:0]$7820 \data_r2__xer_ov - assign $1\data_r2__xer_ov_ok$next[0:0]$7821 \data_r2__xer_ov_ok + assign $1\data_r2__xer_ov$next[1:0]$7804 \data_r2__xer_ov + assign $1\data_r2__xer_ov_ok$next[0:0]$7805 \data_r2__xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -315733,38 +287085,38 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__xer_ov_ok$next[0:0]$7823 $2\data_r2__xer_ov$next[1:0]$7822 } 3'000 + assign { $2\data_r2__xer_ov_ok$next[0:0]$7807 $2\data_r2__xer_ov$next[1:0]$7806 } 3'000 case - assign $2\data_r2__xer_ov$next[1:0]$7822 $1\data_r2__xer_ov$next[1:0]$7820 - assign $2\data_r2__xer_ov_ok$next[0:0]$7823 $1\data_r2__xer_ov_ok$next[0:0]$7821 + assign $2\data_r2__xer_ov$next[1:0]$7806 $1\data_r2__xer_ov$next[1:0]$7804 + assign $2\data_r2__xer_ov_ok$next[0:0]$7807 $1\data_r2__xer_ov_ok$next[0:0]$7805 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__xer_ov_ok$next[0:0]$7824 1'0 + assign $3\data_r2__xer_ov_ok$next[0:0]$7808 1'0 case - assign $3\data_r2__xer_ov_ok$next[0:0]$7824 $2\data_r2__xer_ov_ok$next[0:0]$7823 + assign $3\data_r2__xer_ov_ok$next[0:0]$7808 $2\data_r2__xer_ov_ok$next[0:0]$7807 end sync always - update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$7818 - update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$7819 + update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$7802 + update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$7803 end - attribute \src "libresoc.v:152322.3-152343.6" - process $proc$libresoc.v:152322$7825 + attribute \src "libresoc.v:153606.3-153627.6" + process $proc$libresoc.v:153606$7809 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r3__xer_so$next[0:0]$7826 $2\data_r3__xer_so$next[0:0]$7830 + assign $0\data_r3__xer_so$next[0:0]$7810 $2\data_r3__xer_so$next[0:0]$7814 assign { } { } - assign $0\data_r3__xer_so_ok$next[0:0]$7827 $3\data_r3__xer_so_ok$next[0:0]$7832 - attribute \src "libresoc.v:152323.5-152323.29" + assign $0\data_r3__xer_so_ok$next[0:0]$7811 $3\data_r3__xer_so_ok$next[0:0]$7816 + attribute \src "libresoc.v:153607.5-153607.29" switch \initial - attribute \src "libresoc.v:152323.9-152323.17" + attribute \src "libresoc.v:153607.9-153607.17" case 1'1 case end @@ -315774,10 +287126,10 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r3__xer_so_ok$next[0:0]$7829 $1\data_r3__xer_so$next[0:0]$7828 } { \xer_so_ok \alu_mul0_xer_so } + assign { $1\data_r3__xer_so_ok$next[0:0]$7813 $1\data_r3__xer_so$next[0:0]$7812 } { \xer_so_ok \alu_mul0_xer_so } case - assign $1\data_r3__xer_so$next[0:0]$7828 \data_r3__xer_so - assign $1\data_r3__xer_so_ok$next[0:0]$7829 \data_r3__xer_so_ok + assign $1\data_r3__xer_so$next[0:0]$7812 \data_r3__xer_so + assign $1\data_r3__xer_so_ok$next[0:0]$7813 \data_r3__xer_so_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -315785,32 +287137,32 @@ module \mul0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r3__xer_so_ok$next[0:0]$7831 $2\data_r3__xer_so$next[0:0]$7830 } 2'00 + assign { $2\data_r3__xer_so_ok$next[0:0]$7815 $2\data_r3__xer_so$next[0:0]$7814 } 2'00 case - assign $2\data_r3__xer_so$next[0:0]$7830 $1\data_r3__xer_so$next[0:0]$7828 - assign $2\data_r3__xer_so_ok$next[0:0]$7831 $1\data_r3__xer_so_ok$next[0:0]$7829 + assign $2\data_r3__xer_so$next[0:0]$7814 $1\data_r3__xer_so$next[0:0]$7812 + assign $2\data_r3__xer_so_ok$next[0:0]$7815 $1\data_r3__xer_so_ok$next[0:0]$7813 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r3__xer_so_ok$next[0:0]$7832 1'0 + assign $3\data_r3__xer_so_ok$next[0:0]$7816 1'0 case - assign $3\data_r3__xer_so_ok$next[0:0]$7832 $2\data_r3__xer_so_ok$next[0:0]$7831 + assign $3\data_r3__xer_so_ok$next[0:0]$7816 $2\data_r3__xer_so_ok$next[0:0]$7815 end sync always - update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$7826 - update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$7827 + update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$7810 + update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$7811 end - attribute \src "libresoc.v:152344.3-152353.6" - process $proc$libresoc.v:152344$7833 + attribute \src "libresoc.v:153628.3-153637.6" + process $proc$libresoc.v:153628$7817 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$7834 $1\src_r0$next[63:0]$7835 - attribute \src "libresoc.v:152345.5-152345.29" + assign $0\src_r0$next[63:0]$7818 $1\src_r0$next[63:0]$7819 + attribute \src "libresoc.v:153629.5-153629.29" switch \initial - attribute \src "libresoc.v:152345.9-152345.17" + attribute \src "libresoc.v:153629.9-153629.17" case 1'1 case end @@ -315819,21 +287171,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$7835 \src1_i + assign $1\src_r0$next[63:0]$7819 \src1_i case - assign $1\src_r0$next[63:0]$7835 \src_r0 + assign $1\src_r0$next[63:0]$7819 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$7834 + update \src_r0$next $0\src_r0$next[63:0]$7818 end - attribute \src "libresoc.v:152354.3-152363.6" - process $proc$libresoc.v:152354$7836 + attribute \src "libresoc.v:153638.3-153647.6" + process $proc$libresoc.v:153638$7820 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$7837 $1\src_r1$next[63:0]$7838 - attribute \src "libresoc.v:152355.5-152355.29" + assign $0\src_r1$next[63:0]$7821 $1\src_r1$next[63:0]$7822 + attribute \src "libresoc.v:153639.5-153639.29" switch \initial - attribute \src "libresoc.v:152355.9-152355.17" + attribute \src "libresoc.v:153639.9-153639.17" case 1'1 case end @@ -315842,21 +287194,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$7838 \src_or_imm + assign $1\src_r1$next[63:0]$7822 \src_or_imm case - assign $1\src_r1$next[63:0]$7838 \src_r1 + assign $1\src_r1$next[63:0]$7822 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$7837 + update \src_r1$next $0\src_r1$next[63:0]$7821 end - attribute \src "libresoc.v:152364.3-152373.6" - process $proc$libresoc.v:152364$7839 + attribute \src "libresoc.v:153648.3-153657.6" + process $proc$libresoc.v:153648$7823 assign { } { } assign { } { } - assign $0\src_r2$next[0:0]$7840 $1\src_r2$next[0:0]$7841 - attribute \src "libresoc.v:152365.5-152365.29" + assign $0\src_r2$next[0:0]$7824 $1\src_r2$next[0:0]$7825 + attribute \src "libresoc.v:153649.5-153649.29" switch \initial - attribute \src "libresoc.v:152365.9-152365.17" + attribute \src "libresoc.v:153649.9-153649.17" case 1'1 case end @@ -315865,21 +287217,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[0:0]$7841 \src3_i + assign $1\src_r2$next[0:0]$7825 \src3_i case - assign $1\src_r2$next[0:0]$7841 \src_r2 + assign $1\src_r2$next[0:0]$7825 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[0:0]$7840 + update \src_r2$next $0\src_r2$next[0:0]$7824 end - attribute \src "libresoc.v:152374.3-152382.6" - process $proc$libresoc.v:152374$7842 + attribute \src "libresoc.v:153658.3-153666.6" + process $proc$libresoc.v:153658$7826 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$7843 $1\alui_l_r_alui$next[0:0]$7844 - attribute \src "libresoc.v:152375.5-152375.29" + assign $0\alui_l_r_alui$next[0:0]$7827 $1\alui_l_r_alui$next[0:0]$7828 + attribute \src "libresoc.v:153659.5-153659.29" switch \initial - attribute \src "libresoc.v:152375.9-152375.17" + attribute \src "libresoc.v:153659.9-153659.17" case 1'1 case end @@ -315888,21 +287240,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$7844 1'1 + assign $1\alui_l_r_alui$next[0:0]$7828 1'1 case - assign $1\alui_l_r_alui$next[0:0]$7844 \$88 + assign $1\alui_l_r_alui$next[0:0]$7828 \$88 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$7843 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$7827 end - attribute \src "libresoc.v:152383.3-152391.6" - process $proc$libresoc.v:152383$7845 + attribute \src "libresoc.v:153667.3-153675.6" + process $proc$libresoc.v:153667$7829 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$7846 $1\alu_l_r_alu$next[0:0]$7847 - attribute \src "libresoc.v:152384.5-152384.29" + assign $0\alu_l_r_alu$next[0:0]$7830 $1\alu_l_r_alu$next[0:0]$7831 + attribute \src "libresoc.v:153668.5-153668.29" switch \initial - attribute \src "libresoc.v:152384.9-152384.17" + attribute \src "libresoc.v:153668.9-153668.17" case 1'1 case end @@ -315911,21 +287263,21 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$7847 1'1 + assign $1\alu_l_r_alu$next[0:0]$7831 1'1 case - assign $1\alu_l_r_alu$next[0:0]$7847 \$90 + assign $1\alu_l_r_alu$next[0:0]$7831 \$90 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$7846 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$7830 end - attribute \src "libresoc.v:152392.3-152401.6" - process $proc$libresoc.v:152392$7848 + attribute \src "libresoc.v:153676.3-153685.6" + process $proc$libresoc.v:153676$7832 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:152393.5-152393.29" + attribute \src "libresoc.v:153677.5-153677.29" switch \initial - attribute \src "libresoc.v:152393.9-152393.17" + attribute \src "libresoc.v:153677.9-153677.17" case 1'1 case end @@ -315941,14 +287293,14 @@ module \mul0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:152402.3-152411.6" - process $proc$libresoc.v:152402$7849 + attribute \src "libresoc.v:153686.3-153695.6" + process $proc$libresoc.v:153686$7833 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:152403.5-152403.29" + attribute \src "libresoc.v:153687.5-153687.29" switch \initial - attribute \src "libresoc.v:152403.9-152403.17" + attribute \src "libresoc.v:153687.9-153687.17" case 1'1 case end @@ -315964,14 +287316,14 @@ module \mul0 sync always update \dest2_o $0\dest2_o[3:0] end - attribute \src "libresoc.v:152412.3-152421.6" - process $proc$libresoc.v:152412$7850 + attribute \src "libresoc.v:153696.3-153705.6" + process $proc$libresoc.v:153696$7834 assign { } { } assign { } { } assign $0\dest3_o[1:0] $1\dest3_o[1:0] - attribute \src "libresoc.v:152413.5-152413.29" + attribute \src "libresoc.v:153697.5-153697.29" switch \initial - attribute \src "libresoc.v:152413.9-152413.17" + attribute \src "libresoc.v:153697.9-153697.17" case 1'1 case end @@ -315987,14 +287339,14 @@ module \mul0 sync always update \dest3_o $0\dest3_o[1:0] end - attribute \src "libresoc.v:152422.3-152431.6" - process $proc$libresoc.v:152422$7851 + attribute \src "libresoc.v:153706.3-153715.6" + process $proc$libresoc.v:153706$7835 assign { } { } assign { } { } assign $0\dest4_o[0:0] $1\dest4_o[0:0] - attribute \src "libresoc.v:152423.5-152423.29" + attribute \src "libresoc.v:153707.5-153707.29" switch \initial - attribute \src "libresoc.v:152423.9-152423.17" + attribute \src "libresoc.v:153707.9-153707.17" case 1'1 case end @@ -316010,14 +287362,14 @@ module \mul0 sync always update \dest4_o $0\dest4_o[0:0] end - attribute \src "libresoc.v:152432.3-152440.6" - process $proc$libresoc.v:152432$7852 + attribute \src "libresoc.v:153716.3-153724.6" + process $proc$libresoc.v:153716$7836 assign { } { } assign { } { } - assign $0\prev_wr_go$next[3:0]$7853 $1\prev_wr_go$next[3:0]$7854 - attribute \src "libresoc.v:152433.5-152433.29" + assign $0\prev_wr_go$next[3:0]$7837 $1\prev_wr_go$next[3:0]$7838 + attribute \src "libresoc.v:153717.5-153717.29" switch \initial - attribute \src "libresoc.v:152433.9-152433.17" + attribute \src "libresoc.v:153717.9-153717.17" case 1'1 case end @@ -316026,73 +287378,73 @@ module \mul0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[3:0]$7854 4'0000 - case - assign $1\prev_wr_go$next[3:0]$7854 \$20 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[3:0]$7853 - end - connect \$100 $and$libresoc.v:151908$7641_Y - connect \$102 $and$libresoc.v:151909$7642_Y - connect \$104 $and$libresoc.v:151910$7643_Y - connect \$106 $and$libresoc.v:151911$7644_Y - connect \$108 $and$libresoc.v:151912$7645_Y - connect \$10 $and$libresoc.v:151913$7646_Y - connect \$110 $and$libresoc.v:151914$7647_Y - connect \$112 $and$libresoc.v:151915$7648_Y - connect \$114 $and$libresoc.v:151916$7649_Y - connect \$116 $and$libresoc.v:151917$7650_Y - connect \$118 $and$libresoc.v:151918$7651_Y - connect \$120 $and$libresoc.v:151919$7652_Y - connect \$12 $not$libresoc.v:151920$7653_Y - connect \$14 $and$libresoc.v:151921$7654_Y - connect \$16 $not$libresoc.v:151922$7655_Y - connect \$18 $and$libresoc.v:151923$7656_Y - connect \$20 $and$libresoc.v:151924$7657_Y - connect \$24 $not$libresoc.v:151925$7658_Y - connect \$26 $and$libresoc.v:151926$7659_Y - connect \$23 $reduce_or$libresoc.v:151927$7660_Y - connect \$22 $not$libresoc.v:151928$7661_Y - connect \$2 $and$libresoc.v:151929$7662_Y - connect \$30 $and$libresoc.v:151930$7663_Y - connect \$32 $reduce_or$libresoc.v:151931$7664_Y - connect \$34 $reduce_or$libresoc.v:151932$7665_Y - connect \$36 $or$libresoc.v:151933$7666_Y - connect \$38 $not$libresoc.v:151934$7667_Y - connect \$40 $and$libresoc.v:151935$7668_Y - connect \$42 $and$libresoc.v:151936$7669_Y - connect \$44 $eq$libresoc.v:151937$7670_Y - connect \$46 $and$libresoc.v:151938$7671_Y - connect \$48 $eq$libresoc.v:151939$7672_Y - connect \$50 $and$libresoc.v:151940$7673_Y - connect \$52 $and$libresoc.v:151941$7674_Y - connect \$54 $and$libresoc.v:151942$7675_Y - connect \$56 $or$libresoc.v:151943$7676_Y - connect \$58 $or$libresoc.v:151944$7677_Y - connect \$5 $not$libresoc.v:151945$7678_Y - connect \$60 $or$libresoc.v:151946$7679_Y - connect \$62 $or$libresoc.v:151947$7680_Y - connect \$64 $and$libresoc.v:151948$7681_Y - connect \$66 $and$libresoc.v:151949$7682_Y - connect \$68 $or$libresoc.v:151950$7683_Y - connect \$70 $and$libresoc.v:151951$7684_Y - connect \$72 $and$libresoc.v:151952$7685_Y - connect \$74 $and$libresoc.v:151953$7686_Y - connect \$76 $and$libresoc.v:151954$7687_Y - connect \$78 $ternary$libresoc.v:151955$7688_Y - connect \$7 $or$libresoc.v:151956$7689_Y - connect \$80 $ternary$libresoc.v:151957$7690_Y - connect \$82 $ternary$libresoc.v:151958$7691_Y - connect \$84 $ternary$libresoc.v:151959$7692_Y - connect \$86 $ternary$libresoc.v:151960$7693_Y - connect \$88 $and$libresoc.v:151961$7694_Y - connect \$4 $reduce_and$libresoc.v:151962$7695_Y - connect \$90 $and$libresoc.v:151963$7696_Y - connect \$92 $and$libresoc.v:151964$7697_Y - connect \$94 $not$libresoc.v:151965$7698_Y - connect \$96 $and$libresoc.v:151966$7699_Y - connect \$98 $not$libresoc.v:151967$7700_Y + assign $1\prev_wr_go$next[3:0]$7838 4'0000 + case + assign $1\prev_wr_go$next[3:0]$7838 \$20 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[3:0]$7837 + end + connect \$100 $and$libresoc.v:153192$7625_Y + connect \$102 $and$libresoc.v:153193$7626_Y + connect \$104 $and$libresoc.v:153194$7627_Y + connect \$106 $and$libresoc.v:153195$7628_Y + connect \$108 $and$libresoc.v:153196$7629_Y + connect \$10 $and$libresoc.v:153197$7630_Y + connect \$110 $and$libresoc.v:153198$7631_Y + connect \$112 $and$libresoc.v:153199$7632_Y + connect \$114 $and$libresoc.v:153200$7633_Y + connect \$116 $and$libresoc.v:153201$7634_Y + connect \$118 $and$libresoc.v:153202$7635_Y + connect \$120 $and$libresoc.v:153203$7636_Y + connect \$12 $not$libresoc.v:153204$7637_Y + connect \$14 $and$libresoc.v:153205$7638_Y + connect \$16 $not$libresoc.v:153206$7639_Y + connect \$18 $and$libresoc.v:153207$7640_Y + connect \$20 $and$libresoc.v:153208$7641_Y + connect \$24 $not$libresoc.v:153209$7642_Y + connect \$26 $and$libresoc.v:153210$7643_Y + connect \$23 $reduce_or$libresoc.v:153211$7644_Y + connect \$22 $not$libresoc.v:153212$7645_Y + connect \$2 $and$libresoc.v:153213$7646_Y + connect \$30 $and$libresoc.v:153214$7647_Y + connect \$32 $reduce_or$libresoc.v:153215$7648_Y + connect \$34 $reduce_or$libresoc.v:153216$7649_Y + connect \$36 $or$libresoc.v:153217$7650_Y + connect \$38 $not$libresoc.v:153218$7651_Y + connect \$40 $and$libresoc.v:153219$7652_Y + connect \$42 $and$libresoc.v:153220$7653_Y + connect \$44 $eq$libresoc.v:153221$7654_Y + connect \$46 $and$libresoc.v:153222$7655_Y + connect \$48 $eq$libresoc.v:153223$7656_Y + connect \$50 $and$libresoc.v:153224$7657_Y + connect \$52 $and$libresoc.v:153225$7658_Y + connect \$54 $and$libresoc.v:153226$7659_Y + connect \$56 $or$libresoc.v:153227$7660_Y + connect \$58 $or$libresoc.v:153228$7661_Y + connect \$5 $not$libresoc.v:153229$7662_Y + connect \$60 $or$libresoc.v:153230$7663_Y + connect \$62 $or$libresoc.v:153231$7664_Y + connect \$64 $and$libresoc.v:153232$7665_Y + connect \$66 $and$libresoc.v:153233$7666_Y + connect \$68 $or$libresoc.v:153234$7667_Y + connect \$70 $and$libresoc.v:153235$7668_Y + connect \$72 $and$libresoc.v:153236$7669_Y + connect \$74 $and$libresoc.v:153237$7670_Y + connect \$76 $and$libresoc.v:153238$7671_Y + connect \$78 $ternary$libresoc.v:153239$7672_Y + connect \$7 $or$libresoc.v:153240$7673_Y + connect \$80 $ternary$libresoc.v:153241$7674_Y + connect \$82 $ternary$libresoc.v:153242$7675_Y + connect \$84 $ternary$libresoc.v:153243$7676_Y + connect \$86 $ternary$libresoc.v:153244$7677_Y + connect \$88 $and$libresoc.v:153245$7678_Y + connect \$4 $reduce_and$libresoc.v:153246$7679_Y + connect \$90 $and$libresoc.v:153247$7680_Y + connect \$92 $and$libresoc.v:153248$7681_Y + connect \$94 $not$libresoc.v:153249$7682_Y + connect \$96 $and$libresoc.v:153250$7683_Y + connect \$98 $not$libresoc.v:153251$7684_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$112 @@ -316124,51 +287476,51 @@ module \mul0 connect \all_rd_dly$next \all_rd connect \all_rd \$10 end -attribute \src "libresoc.v:152475.1-152808.10" +attribute \src "libresoc.v:153759.1-154092.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.mul1" attribute \generator "nMigen" module \mul1 - attribute \src "libresoc.v:152775.18-152775.116" - wire $and$libresoc.v:152775$7895_Y - attribute \src "libresoc.v:152777.18-152777.116" - wire $and$libresoc.v:152777$7897_Y - attribute \src "libresoc.v:152778.18-152778.117" - wire $and$libresoc.v:152778$7898_Y - attribute \src "libresoc.v:152779.18-152779.117" - wire $and$libresoc.v:152779$7899_Y - attribute \src "libresoc.v:152782.18-152782.95" - wire width 65 $extend$libresoc.v:152782$7902_Y - attribute \src "libresoc.v:152783.18-152783.91" - wire width 65 $extend$libresoc.v:152783$7904_Y - attribute \src "libresoc.v:152785.18-152785.95" - wire width 65 $extend$libresoc.v:152785$7907_Y - attribute \src "libresoc.v:152786.18-152786.91" - wire width 65 $extend$libresoc.v:152786$7909_Y - attribute \src "libresoc.v:152782.18-152782.95" - wire width 65 $neg$libresoc.v:152782$7903_Y - attribute \src "libresoc.v:152785.18-152785.95" - wire width 65 $neg$libresoc.v:152785$7908_Y - attribute \src "libresoc.v:152783.18-152783.91" - wire width 65 $pos$libresoc.v:152783$7905_Y - attribute \src "libresoc.v:152786.18-152786.91" - wire width 65 $pos$libresoc.v:152786$7910_Y - attribute \src "libresoc.v:152774.18-152774.125" - wire $ternary$libresoc.v:152774$7894_Y - attribute \src "libresoc.v:152776.18-152776.125" - wire $ternary$libresoc.v:152776$7896_Y - attribute \src "libresoc.v:152784.18-152784.112" - wire width 65 $ternary$libresoc.v:152784$7906_Y - attribute \src "libresoc.v:152787.18-152787.112" - wire width 65 $ternary$libresoc.v:152787$7911_Y - attribute \src "libresoc.v:152788.18-152788.116" - wire width 32 $ternary$libresoc.v:152788$7912_Y - attribute \src "libresoc.v:152789.18-152789.116" - wire width 32 $ternary$libresoc.v:152789$7913_Y - attribute \src "libresoc.v:152780.18-152780.106" - wire $xor$libresoc.v:152780$7900_Y - attribute \src "libresoc.v:152781.18-152781.110" - wire $xor$libresoc.v:152781$7901_Y + attribute \src "libresoc.v:154059.18-154059.116" + wire $and$libresoc.v:154059$7879_Y + attribute \src "libresoc.v:154061.18-154061.116" + wire $and$libresoc.v:154061$7881_Y + attribute \src "libresoc.v:154062.18-154062.117" + wire $and$libresoc.v:154062$7882_Y + attribute \src "libresoc.v:154063.18-154063.117" + wire $and$libresoc.v:154063$7883_Y + attribute \src "libresoc.v:154066.18-154066.95" + wire width 65 $extend$libresoc.v:154066$7886_Y + attribute \src "libresoc.v:154067.18-154067.91" + wire width 65 $extend$libresoc.v:154067$7888_Y + attribute \src "libresoc.v:154069.18-154069.95" + wire width 65 $extend$libresoc.v:154069$7891_Y + attribute \src "libresoc.v:154070.18-154070.91" + wire width 65 $extend$libresoc.v:154070$7893_Y + attribute \src "libresoc.v:154066.18-154066.95" + wire width 65 $neg$libresoc.v:154066$7887_Y + attribute \src "libresoc.v:154069.18-154069.95" + wire width 65 $neg$libresoc.v:154069$7892_Y + attribute \src "libresoc.v:154067.18-154067.91" + wire width 65 $pos$libresoc.v:154067$7889_Y + attribute \src "libresoc.v:154070.18-154070.91" + wire width 65 $pos$libresoc.v:154070$7894_Y + attribute \src "libresoc.v:154058.18-154058.125" + wire $ternary$libresoc.v:154058$7878_Y + attribute \src "libresoc.v:154060.18-154060.125" + wire $ternary$libresoc.v:154060$7880_Y + attribute \src "libresoc.v:154068.18-154068.112" + wire width 65 $ternary$libresoc.v:154068$7890_Y + attribute \src "libresoc.v:154071.18-154071.112" + wire width 65 $ternary$libresoc.v:154071$7895_Y + attribute \src "libresoc.v:154072.18-154072.116" + wire width 32 $ternary$libresoc.v:154072$7896_Y + attribute \src "libresoc.v:154073.18-154073.116" + wire width 32 $ternary$libresoc.v:154073$7897_Y + attribute \src "libresoc.v:154064.18-154064.106" + wire $xor$libresoc.v:154064$7884_Y + attribute \src "libresoc.v:154065.18-154065.110" + wire $xor$libresoc.v:154065$7885_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" wire \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" @@ -316468,7 +287820,7 @@ module \mul1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 31 \xer_so$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" - cell $and $and$libresoc.v:152775$7895 + cell $and $and$libresoc.v:154059$7879 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -316476,10 +287828,10 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \$17 connect \B \mul_op__is_signed - connect \Y $and$libresoc.v:152775$7895_Y + connect \Y $and$libresoc.v:154059$7879_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" - cell $and $and$libresoc.v:152777$7897 + cell $and $and$libresoc.v:154061$7881 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -316487,10 +287839,10 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \$21 connect \B \mul_op__is_signed - connect \Y $and$libresoc.v:152777$7897_Y + connect \Y $and$libresoc.v:154061$7881_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:40" - cell $and $and$libresoc.v:152778$7898 + cell $and $and$libresoc.v:154062$7882 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -316498,10 +287850,10 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \ra [31] connect \B \mul_op__is_signed - connect \Y $and$libresoc.v:152778$7898_Y + connect \Y $and$libresoc.v:154062$7882_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:41" - cell $and $and$libresoc.v:152779$7899 + cell $and $and$libresoc.v:154063$7883 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -316509,122 +287861,122 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \rb [31] connect \B \mul_op__is_signed - connect \Y $and$libresoc.v:152779$7899_Y + connect \Y $and$libresoc.v:154063$7883_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" - cell $pos $extend$libresoc.v:152782$7902 + cell $pos $extend$libresoc.v:154066$7886 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \ra - connect \Y $extend$libresoc.v:152782$7902_Y + connect \Y $extend$libresoc.v:154066$7886_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:152783$7904 + cell $pos $extend$libresoc.v:154067$7888 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \ra - connect \Y $extend$libresoc.v:152783$7904_Y + connect \Y $extend$libresoc.v:154067$7888_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" - cell $pos $extend$libresoc.v:152785$7907 + cell $pos $extend$libresoc.v:154069$7891 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \rb - connect \Y $extend$libresoc.v:152785$7907_Y + connect \Y $extend$libresoc.v:154069$7891_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:152786$7909 + cell $pos $extend$libresoc.v:154070$7893 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \rb - connect \Y $extend$libresoc.v:152786$7909_Y + connect \Y $extend$libresoc.v:154070$7893_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" - cell $neg $neg$libresoc.v:152782$7903 + cell $neg $neg$libresoc.v:154066$7887 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:152782$7902_Y - connect \Y $neg$libresoc.v:152782$7903_Y + connect \A $extend$libresoc.v:154066$7886_Y + connect \Y $neg$libresoc.v:154066$7887_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" - cell $neg $neg$libresoc.v:152785$7908 + cell $neg $neg$libresoc.v:154069$7892 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:152785$7907_Y - connect \Y $neg$libresoc.v:152785$7908_Y + connect \A $extend$libresoc.v:154069$7891_Y + connect \Y $neg$libresoc.v:154069$7892_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:152783$7905 + cell $pos $pos$libresoc.v:154067$7889 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:152783$7904_Y - connect \Y $pos$libresoc.v:152783$7905_Y + connect \A $extend$libresoc.v:154067$7888_Y + connect \Y $pos$libresoc.v:154067$7889_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:152786$7910 + cell $pos $pos$libresoc.v:154070$7894 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:152786$7909_Y - connect \Y $pos$libresoc.v:152786$7910_Y + connect \A $extend$libresoc.v:154070$7893_Y + connect \Y $pos$libresoc.v:154070$7894_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" - cell $mux $ternary$libresoc.v:152774$7894 + cell $mux $ternary$libresoc.v:154058$7878 parameter \WIDTH 1 connect \A \ra [63] connect \B \ra [31] connect \S \mul_op__is_32bit - connect \Y $ternary$libresoc.v:152774$7894_Y + connect \Y $ternary$libresoc.v:154058$7878_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" - cell $mux $ternary$libresoc.v:152776$7896 + cell $mux $ternary$libresoc.v:154060$7880 parameter \WIDTH 1 connect \A \rb [63] connect \B \rb [31] connect \S \mul_op__is_32bit - connect \Y $ternary$libresoc.v:152776$7896_Y + connect \Y $ternary$libresoc.v:154060$7880_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" - cell $mux $ternary$libresoc.v:152784$7906 + cell $mux $ternary$libresoc.v:154068$7890 parameter \WIDTH 65 connect \A \$36 connect \B \$34 connect \S \sign_a - connect \Y $ternary$libresoc.v:152784$7906_Y + connect \Y $ternary$libresoc.v:154068$7890_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" - cell $mux $ternary$libresoc.v:152787$7911 + cell $mux $ternary$libresoc.v:154071$7895 parameter \WIDTH 65 connect \A \$43 connect \B \$41 connect \S \sign_b - connect \Y $ternary$libresoc.v:152787$7911_Y + connect \Y $ternary$libresoc.v:154071$7895_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" - cell $mux $ternary$libresoc.v:152788$7912 + cell $mux $ternary$libresoc.v:154072$7896 parameter \WIDTH 32 connect \A \abs_a [63:32] connect \B 0 connect \S \is_32bit - connect \Y $ternary$libresoc.v:152788$7912_Y + connect \Y $ternary$libresoc.v:154072$7896_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" - cell $mux $ternary$libresoc.v:152789$7913 + cell $mux $ternary$libresoc.v:154073$7897 parameter \WIDTH 32 connect \A \abs_b [63:32] connect \B 0 connect \S \is_32bit - connect \Y $ternary$libresoc.v:152789$7913_Y + connect \Y $ternary$libresoc.v:154073$7897_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44" - cell $xor $xor$libresoc.v:152780$7900 + cell $xor $xor$libresoc.v:154064$7884 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -316632,10 +287984,10 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \sign_a connect \B \sign_b - connect \Y $xor$libresoc.v:152780$7900_Y + connect \Y $xor$libresoc.v:154064$7884_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45" - cell $xor $xor$libresoc.v:152781$7901 + cell $xor $xor$libresoc.v:154065$7885 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -316643,24 +287995,24 @@ module \mul1 parameter \Y_WIDTH 1 connect \A \sign32_a connect \B \sign32_b - connect \Y $xor$libresoc.v:152781$7901_Y - end - connect \$17 $ternary$libresoc.v:152774$7894_Y - connect \$19 $and$libresoc.v:152775$7895_Y - connect \$21 $ternary$libresoc.v:152776$7896_Y - connect \$23 $and$libresoc.v:152777$7897_Y - connect \$25 $and$libresoc.v:152778$7898_Y - connect \$27 $and$libresoc.v:152779$7899_Y - connect \$29 $xor$libresoc.v:152780$7900_Y - connect \$31 $xor$libresoc.v:152781$7901_Y - connect \$34 $neg$libresoc.v:152782$7903_Y - connect \$36 $pos$libresoc.v:152783$7905_Y - connect \$38 $ternary$libresoc.v:152784$7906_Y - connect \$41 $neg$libresoc.v:152785$7908_Y - connect \$43 $pos$libresoc.v:152786$7910_Y - connect \$45 $ternary$libresoc.v:152787$7911_Y - connect \$47 $ternary$libresoc.v:152788$7912_Y - connect \$49 $ternary$libresoc.v:152789$7913_Y + connect \Y $xor$libresoc.v:154065$7885_Y + end + connect \$17 $ternary$libresoc.v:154058$7878_Y + connect \$19 $and$libresoc.v:154059$7879_Y + connect \$21 $ternary$libresoc.v:154060$7880_Y + connect \$23 $and$libresoc.v:154061$7881_Y + connect \$25 $and$libresoc.v:154062$7882_Y + connect \$27 $and$libresoc.v:154063$7883_Y + connect \$29 $xor$libresoc.v:154064$7884_Y + connect \$31 $xor$libresoc.v:154065$7885_Y + connect \$34 $neg$libresoc.v:154066$7887_Y + connect \$36 $pos$libresoc.v:154067$7889_Y + connect \$38 $ternary$libresoc.v:154068$7890_Y + connect \$41 $neg$libresoc.v:154069$7892_Y + connect \$43 $pos$libresoc.v:154070$7894_Y + connect \$45 $ternary$libresoc.v:154071$7895_Y + connect \$47 $ternary$libresoc.v:154072$7896_Y + connect \$49 $ternary$libresoc.v:154073$7897_Y connect \$33 \$38 connect \$40 \$45 connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } @@ -316680,17 +288032,17 @@ module \mul1 connect \sign_a \$19 connect \is_32bit \mul_op__is_32bit end -attribute \src "libresoc.v:152812.1-153075.10" +attribute \src "libresoc.v:154096.1-154359.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.mul2" attribute \generator "nMigen" module \mul2 - attribute \src "libresoc.v:153068.18-153068.98" - wire width 129 $extend$libresoc.v:153068$7915_Y - attribute \src "libresoc.v:153067.18-153067.99" - wire width 128 $mul$libresoc.v:153067$7914_Y - attribute \src "libresoc.v:153068.18-153068.98" - wire width 129 $pos$libresoc.v:153068$7916_Y + attribute \src "libresoc.v:154352.18-154352.98" + wire width 129 $extend$libresoc.v:154352$7899_Y + attribute \src "libresoc.v:154351.18-154351.99" + wire width 128 $mul$libresoc.v:154351$7898_Y + attribute \src "libresoc.v:154352.18-154352.98" + wire width 129 $pos$libresoc.v:154352$7900_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" wire width 129 \$17 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" @@ -316946,15 +288298,15 @@ module \mul2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 32 \xer_so$14 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" - cell $pos $extend$libresoc.v:153068$7915 + cell $pos $extend$libresoc.v:154352$7899 parameter \A_SIGNED 0 parameter \A_WIDTH 128 parameter \Y_WIDTH 129 connect \A \$18 - connect \Y $extend$libresoc.v:153068$7915_Y + connect \Y $extend$libresoc.v:154352$7899_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" - cell $mul $mul$libresoc.v:153067$7914 + cell $mul $mul$libresoc.v:154351$7898 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -316962,18 +288314,18 @@ module \mul2 parameter \Y_WIDTH 128 connect \A \ra connect \B \rb - connect \Y $mul$libresoc.v:153067$7914_Y + connect \Y $mul$libresoc.v:154351$7898_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" - cell $pos $pos$libresoc.v:153068$7916 + cell $pos $pos$libresoc.v:154352$7900 parameter \A_SIGNED 0 parameter \A_WIDTH 129 parameter \Y_WIDTH 129 - connect \A $extend$libresoc.v:153068$7915_Y - connect \Y $pos$libresoc.v:153068$7916_Y + connect \A $extend$libresoc.v:154352$7899_Y + connect \Y $pos$libresoc.v:154352$7900_Y end - connect \$18 $mul$libresoc.v:153067$7914_Y - connect \$17 $pos$libresoc.v:153068$7916_Y + connect \$18 $mul$libresoc.v:154351$7898_Y + connect \$17 $pos$libresoc.v:154352$7900_Y connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \muxid$1 \muxid connect \xer_so$14 \xer_so @@ -316981,65 +288333,65 @@ module \mul2 connect \neg_res$15 \neg_res connect \o \$17 end -attribute \src "libresoc.v:153079.1-153464.10" +attribute \src "libresoc.v:154363.1-154772.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.mul3" attribute \generator "nMigen" module \mul3 - attribute \src "libresoc.v:153080.7-153080.20" + attribute \src "libresoc.v:154364.7-154364.20" wire $0\initial[0:0] - attribute \src "libresoc.v:153417.3-153435.6" + attribute \src "libresoc.v:154701.3-154727.6" wire $0\mul_ov[0:0] - attribute \src "libresoc.v:153379.3-153397.6" - wire width 64 $0\o$14[63:0]$7933 - attribute \src "libresoc.v:153398.3-153416.6" + attribute \src "libresoc.v:154663.3-154681.6" + wire width 64 $0\o$14[63:0]$7917 + attribute \src "libresoc.v:154682.3-154700.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:153436.3-153446.6" + attribute \src "libresoc.v:154728.3-154746.6" wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:153447.3-153457.6" + attribute \src "libresoc.v:154747.3-154765.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:153417.3-153435.6" + attribute \src "libresoc.v:154701.3-154727.6" wire $1\mul_ov[0:0] - attribute \src "libresoc.v:153379.3-153397.6" - wire width 64 $1\o$14[63:0]$7934 - attribute \src "libresoc.v:153398.3-153416.6" + attribute \src "libresoc.v:154663.3-154681.6" + wire width 64 $1\o$14[63:0]$7918 + attribute \src "libresoc.v:154682.3-154700.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:153436.3-153446.6" + attribute \src "libresoc.v:154728.3-154746.6" wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:153447.3-153457.6" + attribute \src "libresoc.v:154747.3-154765.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:153417.3-153435.6" + attribute \src "libresoc.v:154701.3-154727.6" wire $2\mul_ov[0:0] - attribute \src "libresoc.v:153373.18-153373.104" - wire $and$libresoc.v:153373$7925_Y - attribute \src "libresoc.v:153377.18-153377.104" - wire $and$libresoc.v:153377$7929_Y - attribute \src "libresoc.v:153367.18-153367.95" - wire width 130 $extend$libresoc.v:153367$7917_Y - attribute \src "libresoc.v:153368.18-153368.90" - wire width 130 $extend$libresoc.v:153368$7919_Y - attribute \src "libresoc.v:153378.18-153378.95" - wire width 2 $extend$libresoc.v:153378$7930_Y - attribute \src "libresoc.v:153367.18-153367.95" - wire width 130 $neg$libresoc.v:153367$7918_Y - attribute \src "libresoc.v:153372.18-153372.98" - wire $not$libresoc.v:153372$7924_Y - attribute \src "libresoc.v:153376.18-153376.98" - wire $not$libresoc.v:153376$7928_Y - attribute \src "libresoc.v:153368.18-153368.90" - wire width 130 $pos$libresoc.v:153368$7920_Y - attribute \src "libresoc.v:153378.18-153378.95" - wire width 2 $pos$libresoc.v:153378$7931_Y - attribute \src "libresoc.v:153371.18-153371.106" - wire $reduce_and$libresoc.v:153371$7923_Y - attribute \src "libresoc.v:153375.18-153375.107" - wire $reduce_and$libresoc.v:153375$7927_Y - attribute \src "libresoc.v:153370.18-153370.106" - wire $reduce_or$libresoc.v:153370$7922_Y - attribute \src "libresoc.v:153374.18-153374.107" - wire $reduce_or$libresoc.v:153374$7926_Y - attribute \src "libresoc.v:153369.18-153369.114" - wire width 130 $ternary$libresoc.v:153369$7921_Y + attribute \src "libresoc.v:154657.18-154657.104" + wire $and$libresoc.v:154657$7909_Y + attribute \src "libresoc.v:154661.18-154661.104" + wire $and$libresoc.v:154661$7913_Y + attribute \src "libresoc.v:154651.18-154651.95" + wire width 130 $extend$libresoc.v:154651$7901_Y + attribute \src "libresoc.v:154652.18-154652.90" + wire width 130 $extend$libresoc.v:154652$7903_Y + attribute \src "libresoc.v:154662.18-154662.95" + wire width 2 $extend$libresoc.v:154662$7914_Y + attribute \src "libresoc.v:154651.18-154651.95" + wire width 130 $neg$libresoc.v:154651$7902_Y + attribute \src "libresoc.v:154656.18-154656.98" + wire $not$libresoc.v:154656$7908_Y + attribute \src "libresoc.v:154660.18-154660.98" + wire $not$libresoc.v:154660$7912_Y + attribute \src "libresoc.v:154652.18-154652.90" + wire width 130 $pos$libresoc.v:154652$7904_Y + attribute \src "libresoc.v:154662.18-154662.95" + wire width 2 $pos$libresoc.v:154662$7915_Y + attribute \src "libresoc.v:154655.18-154655.106" + wire $reduce_and$libresoc.v:154655$7907_Y + attribute \src "libresoc.v:154659.18-154659.107" + wire $reduce_and$libresoc.v:154659$7911_Y + attribute \src "libresoc.v:154654.18-154654.106" + wire $reduce_or$libresoc.v:154654$7906_Y + attribute \src "libresoc.v:154658.18-154658.107" + wire $reduce_or$libresoc.v:154658$7910_Y + attribute \src "libresoc.v:154653.18-154653.114" + wire width 130 $ternary$libresoc.v:154653$7905_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" wire width 130 \$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" @@ -317066,7 +288418,7 @@ module \mul3 wire \$37 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 2 \$39 - attribute \src "libresoc.v:153080.7-153080.15" + attribute \src "libresoc.v:154364.7-154364.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:36" wire \is_32bit @@ -317325,7 +288677,7 @@ module \mul3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 34 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $and $and$libresoc.v:153373$7925 + cell $and $and$libresoc.v:154657$7909 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317333,10 +288685,10 @@ module \mul3 parameter \Y_WIDTH 1 connect \A \$23 connect \B \$25 - connect \Y $and$libresoc.v:153373$7925_Y + connect \Y $and$libresoc.v:154657$7909_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $and $and$libresoc.v:153377$7929 + cell $and $and$libresoc.v:154661$7913 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -317344,128 +288696,128 @@ module \mul3 parameter \Y_WIDTH 1 connect \A \$31 connect \B \$33 - connect \Y $and$libresoc.v:153377$7929_Y + connect \Y $and$libresoc.v:154661$7913_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - cell $pos $extend$libresoc.v:153367$7917 + cell $pos $extend$libresoc.v:154651$7901 parameter \A_SIGNED 0 parameter \A_WIDTH 129 parameter \Y_WIDTH 130 connect \A \o - connect \Y $extend$libresoc.v:153367$7917_Y + connect \Y $extend$libresoc.v:154651$7901_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:153368$7919 + cell $pos $extend$libresoc.v:154652$7903 parameter \A_SIGNED 0 parameter \A_WIDTH 129 parameter \Y_WIDTH 130 connect \A \o - connect \Y $extend$libresoc.v:153368$7919_Y + connect \Y $extend$libresoc.v:154652$7903_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:153378$7930 + cell $pos $extend$libresoc.v:154662$7914 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 2 connect \A \xer_so - connect \Y $extend$libresoc.v:153378$7930_Y + connect \Y $extend$libresoc.v:154662$7914_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - cell $neg $neg$libresoc.v:153367$7918 + cell $neg $neg$libresoc.v:154651$7902 parameter \A_SIGNED 0 parameter \A_WIDTH 130 parameter \Y_WIDTH 130 - connect \A $extend$libresoc.v:153367$7917_Y - connect \Y $neg$libresoc.v:153367$7918_Y + connect \A $extend$libresoc.v:154651$7901_Y + connect \Y $neg$libresoc.v:154651$7902_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $not $not$libresoc.v:153372$7924 + cell $not $not$libresoc.v:154656$7908 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$26 - connect \Y $not$libresoc.v:153372$7924_Y + connect \Y $not$libresoc.v:154656$7908_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $not $not$libresoc.v:153376$7928 + cell $not $not$libresoc.v:154660$7912 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$34 - connect \Y $not$libresoc.v:153376$7928_Y + connect \Y $not$libresoc.v:154660$7912_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:153368$7920 + cell $pos $pos$libresoc.v:154652$7904 parameter \A_SIGNED 0 parameter \A_WIDTH 130 parameter \Y_WIDTH 130 - connect \A $extend$libresoc.v:153368$7919_Y - connect \Y $pos$libresoc.v:153368$7920_Y + connect \A $extend$libresoc.v:154652$7903_Y + connect \Y $pos$libresoc.v:154652$7904_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:153378$7931 + cell $pos $pos$libresoc.v:154662$7915 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 - connect \A $extend$libresoc.v:153378$7930_Y - connect \Y $pos$libresoc.v:153378$7931_Y + connect \A $extend$libresoc.v:154662$7914_Y + connect \Y $pos$libresoc.v:154662$7915_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $reduce_and $reduce_and$libresoc.v:153371$7923 + cell $reduce_and $reduce_and$libresoc.v:154655$7907 parameter \A_SIGNED 0 parameter \A_WIDTH 33 parameter \Y_WIDTH 1 connect \A \mul_o [63:31] - connect \Y $reduce_and$libresoc.v:153371$7923_Y + connect \Y $reduce_and$libresoc.v:154655$7907_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $reduce_and $reduce_and$libresoc.v:153375$7927 + cell $reduce_and $reduce_and$libresoc.v:154659$7911 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 1 connect \A \mul_o [127:63] - connect \Y $reduce_and$libresoc.v:153375$7927_Y + connect \Y $reduce_and$libresoc.v:154659$7911_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $reduce_or $reduce_or$libresoc.v:153370$7922 + cell $reduce_or $reduce_or$libresoc.v:154654$7906 parameter \A_SIGNED 0 parameter \A_WIDTH 33 parameter \Y_WIDTH 1 connect \A \mul_o [63:31] - connect \Y $reduce_or$libresoc.v:153370$7922_Y + connect \Y $reduce_or$libresoc.v:154654$7906_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $reduce_or $reduce_or$libresoc.v:153374$7926 + cell $reduce_or $reduce_or$libresoc.v:154658$7910 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 1 connect \A \mul_o [127:63] - connect \Y $reduce_or$libresoc.v:153374$7926_Y + connect \Y $reduce_or$libresoc.v:154658$7910_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - cell $mux $ternary$libresoc.v:153369$7921 + cell $mux $ternary$libresoc.v:154653$7905 parameter \WIDTH 130 connect \A \$19 connect \B \$17 connect \S \neg_res - connect \Y $ternary$libresoc.v:153369$7921_Y + connect \Y $ternary$libresoc.v:154653$7905_Y end - attribute \src "libresoc.v:153080.7-153080.20" - process $proc$libresoc.v:153080$7939 + attribute \src "libresoc.v:154364.7-154364.20" + process $proc$libresoc.v:154364$7923 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:153379.3-153397.6" - process $proc$libresoc.v:153379$7932 + attribute \src "libresoc.v:154663.3-154681.6" + process $proc$libresoc.v:154663$7916 assign { } { } assign { } { } - assign $0\o$14[63:0]$7933 $1\o$14[63:0]$7934 - attribute \src "libresoc.v:153380.5-153380.29" + assign $0\o$14[63:0]$7917 $1\o$14[63:0]$7918 + attribute \src "libresoc.v:154664.5-154664.29" switch \initial - attribute \src "libresoc.v:153380.9-153380.17" + attribute \src "libresoc.v:154664.9-154664.17" case 1'1 case end @@ -317474,29 +288826,29 @@ module \mul3 attribute \src "libresoc.v:0.0-0.0" case 7'0110100 assign { } { } - assign $1\o$14[63:0]$7934 { \mul_o [63:32] \mul_o [63:32] } + assign $1\o$14[63:0]$7918 { \mul_o [63:32] \mul_o [63:32] } attribute \src "libresoc.v:0.0-0.0" case 7'0110011 assign { } { } - assign $1\o$14[63:0]$7934 \mul_o [127:64] + assign $1\o$14[63:0]$7918 \mul_o [127:64] attribute \src "libresoc.v:0.0-0.0" case 7'0110010 assign { } { } - assign $1\o$14[63:0]$7934 \mul_o [63:0] + assign $1\o$14[63:0]$7918 \mul_o [63:0] case - assign $1\o$14[63:0]$7934 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\o$14[63:0]$7918 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \o$14 $0\o$14[63:0]$7933 + update \o$14 $0\o$14[63:0]$7917 end - attribute \src "libresoc.v:153398.3-153416.6" - process $proc$libresoc.v:153398$7935 + attribute \src "libresoc.v:154682.3-154700.6" + process $proc$libresoc.v:154682$7919 assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] - attribute \src "libresoc.v:153399.5-153399.29" + attribute \src "libresoc.v:154683.5-154683.29" switch \initial - attribute \src "libresoc.v:153399.9-153399.17" + attribute \src "libresoc.v:154683.9-154683.17" case 1'1 case end @@ -317520,20 +288872,26 @@ module \mul3 sync always update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:153417.3-153435.6" - process $proc$libresoc.v:153417$7936 + attribute \src "libresoc.v:154701.3-154727.6" + process $proc$libresoc.v:154701$7920 assign { } { } assign { } { } assign $0\mul_ov[0:0] $1\mul_ov[0:0] - attribute \src "libresoc.v:153418.5-153418.29" + attribute \src "libresoc.v:154702.5-154702.29" switch \initial - attribute \src "libresoc.v:153418.9-153418.17" + attribute \src "libresoc.v:154702.9-154702.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" switch \mul_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0110100 + assign $1\mul_ov[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 + assign $1\mul_ov[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 7'0110010 assign { } { } assign $1\mul_ov[0:0] $2\mul_ov[0:0] @@ -317554,20 +288912,26 @@ module \mul3 sync always update \mul_ov $0\mul_ov[0:0] end - attribute \src "libresoc.v:153436.3-153446.6" - process $proc$libresoc.v:153436$7937 + attribute \src "libresoc.v:154728.3-154746.6" + process $proc$libresoc.v:154728$7921 assign { } { } assign { } { } assign $0\xer_ov[1:0] $1\xer_ov[1:0] - attribute \src "libresoc.v:153437.5-153437.29" + attribute \src "libresoc.v:154729.5-154729.29" switch \initial - attribute \src "libresoc.v:153437.9-153437.17" + attribute \src "libresoc.v:154729.9-154729.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" switch \mul_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0110100 + assign $1\xer_ov[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 + assign $1\xer_ov[1:0] 2'00 + attribute \src "libresoc.v:0.0-0.0" case 7'0110010 assign { } { } assign $1\xer_ov[1:0] { \mul_ov \mul_ov } @@ -317577,20 +288941,26 @@ module \mul3 sync always update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:153447.3-153457.6" - process $proc$libresoc.v:153447$7938 + attribute \src "libresoc.v:154747.3-154765.6" + process $proc$libresoc.v:154747$7922 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:153448.5-153448.29" + attribute \src "libresoc.v:154748.5-154748.29" switch \initial - attribute \src "libresoc.v:153448.9-153448.17" + attribute \src "libresoc.v:154748.9-154748.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" switch \mul_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0110100 + assign $1\xer_ov_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 7'0110011 + assign $1\xer_ov_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 7'0110010 assign { } { } assign $1\xer_ov_ok[0:0] 1'1 @@ -317600,18 +288970,18 @@ module \mul3 sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - connect \$17 $neg$libresoc.v:153367$7918_Y - connect \$19 $pos$libresoc.v:153368$7920_Y - connect \$21 $ternary$libresoc.v:153369$7921_Y - connect \$23 $reduce_or$libresoc.v:153370$7922_Y - connect \$26 $reduce_and$libresoc.v:153371$7923_Y - connect \$25 $not$libresoc.v:153372$7924_Y - connect \$29 $and$libresoc.v:153373$7925_Y - connect \$31 $reduce_or$libresoc.v:153374$7926_Y - connect \$34 $reduce_and$libresoc.v:153375$7927_Y - connect \$33 $not$libresoc.v:153376$7928_Y - connect \$37 $and$libresoc.v:153377$7929_Y - connect \$39 $pos$libresoc.v:153378$7931_Y + connect \$17 $neg$libresoc.v:154651$7902_Y + connect \$19 $pos$libresoc.v:154652$7904_Y + connect \$21 $ternary$libresoc.v:154653$7905_Y + connect \$23 $reduce_or$libresoc.v:154654$7906_Y + connect \$26 $reduce_and$libresoc.v:154655$7907_Y + connect \$25 $not$libresoc.v:154656$7908_Y + connect \$29 $and$libresoc.v:154657$7909_Y + connect \$31 $reduce_or$libresoc.v:154658$7910_Y + connect \$34 $reduce_and$libresoc.v:154659$7911_Y + connect \$33 $not$libresoc.v:154660$7912_Y + connect \$37 $and$libresoc.v:154661$7913_Y + connect \$39 $pos$libresoc.v:154662$7915_Y connect \$16 \$21 connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \muxid$1 \muxid @@ -317619,188 +288989,188 @@ module \mul3 connect \mul_o \$21 [128:0] connect \is_32bit \mul_op__is_32bit end -attribute \src "libresoc.v:153468.1-154685.10" +attribute \src "libresoc.v:154776.1-155993.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1" attribute \generator "nMigen" module \mul_pipe1 - attribute \src "libresoc.v:153469.7-153469.20" + attribute \src "libresoc.v:154777.7-154777.20" wire $0\initial[0:0] - attribute \src "libresoc.v:154562.3-154597.6" - wire width 14 $0\mul_op__fn_unit$next[13:0]$7968 - attribute \src "libresoc.v:154427.3-154428.47" + attribute \src "libresoc.v:155870.3-155905.6" + wire width 14 $0\mul_op__fn_unit$next[13:0]$7952 + attribute \src "libresoc.v:155735.3-155736.47" wire width 14 $0\mul_op__fn_unit[13:0] - attribute \src "libresoc.v:154562.3-154597.6" - wire width 64 $0\mul_op__imm_data__data$next[63:0]$7969 - attribute \src "libresoc.v:154429.3-154430.61" + attribute \src "libresoc.v:155870.3-155905.6" + wire width 64 $0\mul_op__imm_data__data$next[63:0]$7953 + attribute \src "libresoc.v:155737.3-155738.61" wire width 64 $0\mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:154562.3-154597.6" - wire $0\mul_op__imm_data__ok$next[0:0]$7970 - attribute \src "libresoc.v:154431.3-154432.57" + attribute \src "libresoc.v:155870.3-155905.6" + wire $0\mul_op__imm_data__ok$next[0:0]$7954 + attribute \src "libresoc.v:155739.3-155740.57" wire $0\mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:154562.3-154597.6" - wire width 32 $0\mul_op__insn$next[31:0]$7971 - attribute \src "libresoc.v:154447.3-154448.41" + attribute \src "libresoc.v:155870.3-155905.6" + wire width 32 $0\mul_op__insn$next[31:0]$7955 + attribute \src "libresoc.v:155755.3-155756.41" wire width 32 $0\mul_op__insn[31:0] - attribute \src "libresoc.v:154562.3-154597.6" - wire width 7 $0\mul_op__insn_type$next[6:0]$7972 - attribute \src "libresoc.v:154425.3-154426.51" + attribute \src "libresoc.v:155870.3-155905.6" + wire width 7 $0\mul_op__insn_type$next[6:0]$7956 + attribute \src "libresoc.v:155733.3-155734.51" wire width 7 $0\mul_op__insn_type[6:0] - attribute \src "libresoc.v:154562.3-154597.6" - wire $0\mul_op__is_32bit$next[0:0]$7973 - attribute \src "libresoc.v:154443.3-154444.49" + attribute \src "libresoc.v:155870.3-155905.6" + wire $0\mul_op__is_32bit$next[0:0]$7957 + attribute \src "libresoc.v:155751.3-155752.49" wire $0\mul_op__is_32bit[0:0] - attribute \src "libresoc.v:154562.3-154597.6" - wire $0\mul_op__is_signed$next[0:0]$7974 - attribute \src "libresoc.v:154445.3-154446.51" + attribute \src "libresoc.v:155870.3-155905.6" + wire $0\mul_op__is_signed$next[0:0]$7958 + attribute \src "libresoc.v:155753.3-155754.51" wire $0\mul_op__is_signed[0:0] - attribute \src "libresoc.v:154562.3-154597.6" - wire $0\mul_op__oe__oe$next[0:0]$7975 - attribute \src "libresoc.v:154437.3-154438.45" + attribute \src "libresoc.v:155870.3-155905.6" + wire $0\mul_op__oe__oe$next[0:0]$7959 + attribute \src "libresoc.v:155745.3-155746.45" wire $0\mul_op__oe__oe[0:0] - attribute \src "libresoc.v:154562.3-154597.6" - wire $0\mul_op__oe__ok$next[0:0]$7976 - attribute \src "libresoc.v:154439.3-154440.45" + attribute \src "libresoc.v:155870.3-155905.6" + wire $0\mul_op__oe__ok$next[0:0]$7960 + attribute \src "libresoc.v:155747.3-155748.45" wire $0\mul_op__oe__ok[0:0] - attribute \src "libresoc.v:154562.3-154597.6" - wire $0\mul_op__rc__ok$next[0:0]$7977 - attribute \src "libresoc.v:154435.3-154436.45" + attribute \src "libresoc.v:155870.3-155905.6" + wire $0\mul_op__rc__ok$next[0:0]$7961 + attribute \src "libresoc.v:155743.3-155744.45" wire $0\mul_op__rc__ok[0:0] - attribute \src "libresoc.v:154562.3-154597.6" - wire $0\mul_op__rc__rc$next[0:0]$7978 - attribute \src "libresoc.v:154433.3-154434.45" + attribute \src "libresoc.v:155870.3-155905.6" + wire $0\mul_op__rc__rc$next[0:0]$7962 + attribute \src "libresoc.v:155741.3-155742.45" wire $0\mul_op__rc__rc[0:0] - attribute \src "libresoc.v:154562.3-154597.6" - wire $0\mul_op__write_cr0$next[0:0]$7979 - attribute \src "libresoc.v:154441.3-154442.51" + attribute \src "libresoc.v:155870.3-155905.6" + wire $0\mul_op__write_cr0$next[0:0]$7963 + attribute \src "libresoc.v:155749.3-155750.51" wire $0\mul_op__write_cr0[0:0] - attribute \src "libresoc.v:154549.3-154561.6" - wire width 2 $0\muxid$next[1:0]$7965 - attribute \src "libresoc.v:154449.3-154450.27" + attribute \src "libresoc.v:155857.3-155869.6" + wire width 2 $0\muxid$next[1:0]$7949 + attribute \src "libresoc.v:155757.3-155758.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:154637.3-154649.6" - wire $0\neg_res$next[0:0]$8008 - attribute \src "libresoc.v:154650.3-154662.6" - wire $0\neg_res32$next[0:0]$8011 - attribute \src "libresoc.v:154415.3-154416.35" + attribute \src "libresoc.v:155945.3-155957.6" + wire $0\neg_res$next[0:0]$7992 + attribute \src "libresoc.v:155958.3-155970.6" + wire $0\neg_res32$next[0:0]$7995 + attribute \src "libresoc.v:155723.3-155724.35" wire $0\neg_res32[0:0] - attribute \src "libresoc.v:154417.3-154418.31" + attribute \src "libresoc.v:155725.3-155726.31" wire $0\neg_res[0:0] - attribute \src "libresoc.v:154531.3-154548.6" - wire $0\r_busy$next[0:0]$7961 - attribute \src "libresoc.v:154451.3-154452.29" + attribute \src "libresoc.v:155839.3-155856.6" + wire $0\r_busy$next[0:0]$7945 + attribute \src "libresoc.v:155759.3-155760.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:154598.3-154610.6" - wire width 64 $0\ra$next[63:0]$7999 - attribute \src "libresoc.v:154423.3-154424.21" + attribute \src "libresoc.v:155906.3-155918.6" + wire width 64 $0\ra$next[63:0]$7983 + attribute \src "libresoc.v:155731.3-155732.21" wire width 64 $0\ra[63:0] - attribute \src "libresoc.v:154611.3-154623.6" - wire width 64 $0\rb$next[63:0]$8002 - attribute \src "libresoc.v:154421.3-154422.21" + attribute \src "libresoc.v:155919.3-155931.6" + wire width 64 $0\rb$next[63:0]$7986 + attribute \src "libresoc.v:155729.3-155730.21" wire width 64 $0\rb[63:0] - attribute \src "libresoc.v:154624.3-154636.6" - wire $0\xer_so$next[0:0]$8005 - attribute \src "libresoc.v:154419.3-154420.29" + attribute \src "libresoc.v:155932.3-155944.6" + wire $0\xer_so$next[0:0]$7989 + attribute \src "libresoc.v:155727.3-155728.29" wire $0\xer_so[0:0] - attribute \src "libresoc.v:154562.3-154597.6" - wire width 14 $1\mul_op__fn_unit$next[13:0]$7980 - attribute \src "libresoc.v:153985.14-153985.40" + attribute \src "libresoc.v:155870.3-155905.6" + wire width 14 $1\mul_op__fn_unit$next[13:0]$7964 + attribute \src "libresoc.v:155293.14-155293.40" wire width 14 $1\mul_op__fn_unit[13:0] - attribute \src "libresoc.v:154562.3-154597.6" - wire width 64 $1\mul_op__imm_data__data$next[63:0]$7981 - attribute \src "libresoc.v:154024.14-154024.59" + attribute \src "libresoc.v:155870.3-155905.6" + wire width 64 $1\mul_op__imm_data__data$next[63:0]$7965 + attribute \src "libresoc.v:155332.14-155332.59" wire width 64 $1\mul_op__imm_data__data[63:0] - attribute \src "libresoc.v:154562.3-154597.6" - wire $1\mul_op__imm_data__ok$next[0:0]$7982 - attribute \src "libresoc.v:154033.7-154033.34" + attribute \src "libresoc.v:155870.3-155905.6" + wire $1\mul_op__imm_data__ok$next[0:0]$7966 + attribute \src "libresoc.v:155341.7-155341.34" wire $1\mul_op__imm_data__ok[0:0] - attribute \src "libresoc.v:154562.3-154597.6" - wire width 32 $1\mul_op__insn$next[31:0]$7983 - attribute \src "libresoc.v:154042.14-154042.34" + attribute \src "libresoc.v:155870.3-155905.6" + wire width 32 $1\mul_op__insn$next[31:0]$7967 + attribute \src "libresoc.v:155350.14-155350.34" wire width 32 $1\mul_op__insn[31:0] - attribute \src "libresoc.v:154562.3-154597.6" - wire width 7 $1\mul_op__insn_type$next[6:0]$7984 - attribute \src "libresoc.v:154126.13-154126.38" + attribute \src "libresoc.v:155870.3-155905.6" + wire width 7 $1\mul_op__insn_type$next[6:0]$7968 + attribute \src "libresoc.v:155434.13-155434.38" wire width 7 $1\mul_op__insn_type[6:0] - attribute \src "libresoc.v:154562.3-154597.6" - wire $1\mul_op__is_32bit$next[0:0]$7985 - attribute \src "libresoc.v:154285.7-154285.30" + attribute \src "libresoc.v:155870.3-155905.6" + wire $1\mul_op__is_32bit$next[0:0]$7969 + attribute \src "libresoc.v:155593.7-155593.30" wire $1\mul_op__is_32bit[0:0] - attribute \src "libresoc.v:154562.3-154597.6" - wire $1\mul_op__is_signed$next[0:0]$7986 - attribute \src "libresoc.v:154294.7-154294.31" + attribute \src "libresoc.v:155870.3-155905.6" + wire $1\mul_op__is_signed$next[0:0]$7970 + attribute \src "libresoc.v:155602.7-155602.31" wire $1\mul_op__is_signed[0:0] - attribute \src "libresoc.v:154562.3-154597.6" - wire $1\mul_op__oe__oe$next[0:0]$7987 - attribute \src "libresoc.v:154303.7-154303.28" + attribute \src "libresoc.v:155870.3-155905.6" + wire $1\mul_op__oe__oe$next[0:0]$7971 + attribute \src "libresoc.v:155611.7-155611.28" wire $1\mul_op__oe__oe[0:0] - attribute \src "libresoc.v:154562.3-154597.6" - wire $1\mul_op__oe__ok$next[0:0]$7988 - attribute \src "libresoc.v:154312.7-154312.28" + attribute \src "libresoc.v:155870.3-155905.6" + wire $1\mul_op__oe__ok$next[0:0]$7972 + attribute \src "libresoc.v:155620.7-155620.28" wire $1\mul_op__oe__ok[0:0] - attribute \src "libresoc.v:154562.3-154597.6" - wire $1\mul_op__rc__ok$next[0:0]$7989 - attribute \src "libresoc.v:154321.7-154321.28" + attribute \src "libresoc.v:155870.3-155905.6" + wire $1\mul_op__rc__ok$next[0:0]$7973 + attribute \src "libresoc.v:155629.7-155629.28" wire $1\mul_op__rc__ok[0:0] - attribute \src "libresoc.v:154562.3-154597.6" - wire $1\mul_op__rc__rc$next[0:0]$7990 - attribute \src "libresoc.v:154330.7-154330.28" + attribute \src "libresoc.v:155870.3-155905.6" + wire $1\mul_op__rc__rc$next[0:0]$7974 + attribute \src "libresoc.v:155638.7-155638.28" wire $1\mul_op__rc__rc[0:0] - attribute \src "libresoc.v:154562.3-154597.6" - wire $1\mul_op__write_cr0$next[0:0]$7991 - attribute \src "libresoc.v:154339.7-154339.31" + attribute \src "libresoc.v:155870.3-155905.6" + wire $1\mul_op__write_cr0$next[0:0]$7975 + attribute \src "libresoc.v:155647.7-155647.31" wire $1\mul_op__write_cr0[0:0] - attribute \src "libresoc.v:154549.3-154561.6" - wire width 2 $1\muxid$next[1:0]$7966 - attribute \src "libresoc.v:154348.13-154348.25" + attribute \src "libresoc.v:155857.3-155869.6" + wire width 2 $1\muxid$next[1:0]$7950 + attribute \src "libresoc.v:155656.13-155656.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:154637.3-154649.6" - wire $1\neg_res$next[0:0]$8009 - attribute \src "libresoc.v:154650.3-154662.6" - wire $1\neg_res32$next[0:0]$8012 - attribute \src "libresoc.v:154370.7-154370.23" + attribute \src "libresoc.v:155945.3-155957.6" + wire $1\neg_res$next[0:0]$7993 + attribute \src "libresoc.v:155958.3-155970.6" + wire $1\neg_res32$next[0:0]$7996 + attribute \src "libresoc.v:155678.7-155678.23" wire $1\neg_res32[0:0] - attribute \src "libresoc.v:154363.7-154363.21" + attribute \src "libresoc.v:155671.7-155671.21" wire $1\neg_res[0:0] - attribute \src "libresoc.v:154531.3-154548.6" - wire $1\r_busy$next[0:0]$7962 - attribute \src "libresoc.v:154384.7-154384.20" + attribute \src "libresoc.v:155839.3-155856.6" + wire $1\r_busy$next[0:0]$7946 + attribute \src "libresoc.v:155692.7-155692.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:154598.3-154610.6" - wire width 64 $1\ra$next[63:0]$8000 - attribute \src "libresoc.v:154389.14-154389.39" + attribute \src "libresoc.v:155906.3-155918.6" + wire width 64 $1\ra$next[63:0]$7984 + attribute \src "libresoc.v:155697.14-155697.39" wire width 64 $1\ra[63:0] - attribute \src "libresoc.v:154611.3-154623.6" - wire width 64 $1\rb$next[63:0]$8003 - attribute \src "libresoc.v:154398.14-154398.39" + attribute \src "libresoc.v:155919.3-155931.6" + wire width 64 $1\rb$next[63:0]$7987 + attribute \src "libresoc.v:155706.14-155706.39" wire width 64 $1\rb[63:0] - attribute \src "libresoc.v:154624.3-154636.6" - wire $1\xer_so$next[0:0]$8006 - attribute \src "libresoc.v:154407.7-154407.20" + attribute \src "libresoc.v:155932.3-155944.6" + wire $1\xer_so$next[0:0]$7990 + attribute \src "libresoc.v:155715.7-155715.20" wire $1\xer_so[0:0] - attribute \src "libresoc.v:154562.3-154597.6" - wire width 64 $2\mul_op__imm_data__data$next[63:0]$7992 - attribute \src "libresoc.v:154562.3-154597.6" - wire $2\mul_op__imm_data__ok$next[0:0]$7993 - attribute \src "libresoc.v:154562.3-154597.6" - wire $2\mul_op__oe__oe$next[0:0]$7994 - attribute \src "libresoc.v:154562.3-154597.6" - wire $2\mul_op__oe__ok$next[0:0]$7995 - attribute \src "libresoc.v:154562.3-154597.6" - wire $2\mul_op__rc__ok$next[0:0]$7996 - attribute \src "libresoc.v:154562.3-154597.6" - wire $2\mul_op__rc__rc$next[0:0]$7997 - attribute \src "libresoc.v:154531.3-154548.6" - wire $2\r_busy$next[0:0]$7963 - attribute \src "libresoc.v:154414.18-154414.118" - wire $and$libresoc.v:154414$7940_Y + attribute \src "libresoc.v:155870.3-155905.6" + wire width 64 $2\mul_op__imm_data__data$next[63:0]$7976 + attribute \src "libresoc.v:155870.3-155905.6" + wire $2\mul_op__imm_data__ok$next[0:0]$7977 + attribute \src "libresoc.v:155870.3-155905.6" + wire $2\mul_op__oe__oe$next[0:0]$7978 + attribute \src "libresoc.v:155870.3-155905.6" + wire $2\mul_op__oe__ok$next[0:0]$7979 + attribute \src "libresoc.v:155870.3-155905.6" + wire $2\mul_op__rc__ok$next[0:0]$7980 + attribute \src "libresoc.v:155870.3-155905.6" + wire $2\mul_op__rc__rc$next[0:0]$7981 + attribute \src "libresoc.v:155839.3-155856.6" + wire $2\r_busy$next[0:0]$7947 + attribute \src "libresoc.v:155722.18-155722.118" + wire $and$libresoc.v:155722$7924_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 40 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:153469.7-153469.15" + attribute \src "libresoc.v:154777.7-154777.15" wire \initial attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -318723,7 +290093,7 @@ module \mul_pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \xer_so$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:154414$7940 + cell $and $and$libresoc.v:155722$7924 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -318731,10 +290101,10 @@ module \mul_pipe1 parameter \Y_WIDTH 1 connect \A \p_valid_i$49 connect \B \p_ready_o - connect \Y $and$libresoc.v:154414$7940_Y + connect \Y $and$libresoc.v:155722$7924_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:154453.14-154486.4" + attribute \src "libresoc.v:155761.14-155794.4" cell \input$95 \input connect \mul_op__fn_unit \input_mul_op__fn_unit connect \mul_op__fn_unit$3 \input_mul_op__fn_unit$19 @@ -318770,7 +290140,7 @@ module \mul_pipe1 connect \xer_so$16 \input_xer_so$32 end attribute \module_not_derived 1 - attribute \src "libresoc.v:154487.8-154522.4" + attribute \src "libresoc.v:155795.8-155830.4" cell \mul1 \mul1 connect \mul_op__fn_unit \mul1_mul_op__fn_unit connect \mul_op__fn_unit$3 \mul1_mul_op__fn_unit$35 @@ -318808,319 +290178,319 @@ module \mul_pipe1 connect \xer_so$16 \mul1_xer_so$48 end attribute \module_not_derived 1 - attribute \src "libresoc.v:154523.10-154526.4" + attribute \src "libresoc.v:155831.10-155834.4" cell \n$94 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:154527.10-154530.4" + attribute \src "libresoc.v:155835.10-155838.4" cell \p$93 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:153469.7-153469.20" - process $proc$libresoc.v:153469$8013 + attribute \src "libresoc.v:154777.7-154777.20" + process $proc$libresoc.v:154777$7997 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:153985.14-153985.40" - process $proc$libresoc.v:153985$8014 + attribute \src "libresoc.v:155293.14-155293.40" + process $proc$libresoc.v:155293$7998 assign { } { } assign $1\mul_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \mul_op__fn_unit $1\mul_op__fn_unit[13:0] end - attribute \src "libresoc.v:154024.14-154024.59" - process $proc$libresoc.v:154024$8015 + attribute \src "libresoc.v:155332.14-155332.59" + process $proc$libresoc.v:155332$7999 assign { } { } assign $1\mul_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \mul_op__imm_data__data $1\mul_op__imm_data__data[63:0] end - attribute \src "libresoc.v:154033.7-154033.34" - process $proc$libresoc.v:154033$8016 + attribute \src "libresoc.v:155341.7-155341.34" + process $proc$libresoc.v:155341$8000 assign { } { } assign $1\mul_op__imm_data__ok[0:0] 1'0 sync always sync init update \mul_op__imm_data__ok $1\mul_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:154042.14-154042.34" - process $proc$libresoc.v:154042$8017 + attribute \src "libresoc.v:155350.14-155350.34" + process $proc$libresoc.v:155350$8001 assign { } { } assign $1\mul_op__insn[31:0] 0 sync always sync init update \mul_op__insn $1\mul_op__insn[31:0] end - attribute \src "libresoc.v:154126.13-154126.38" - process $proc$libresoc.v:154126$8018 + attribute \src "libresoc.v:155434.13-155434.38" + process $proc$libresoc.v:155434$8002 assign { } { } assign $1\mul_op__insn_type[6:0] 7'0000000 sync always sync init update \mul_op__insn_type $1\mul_op__insn_type[6:0] end - attribute \src "libresoc.v:154285.7-154285.30" - process $proc$libresoc.v:154285$8019 + attribute \src "libresoc.v:155593.7-155593.30" + process $proc$libresoc.v:155593$8003 assign { } { } assign $1\mul_op__is_32bit[0:0] 1'0 sync always sync init update \mul_op__is_32bit $1\mul_op__is_32bit[0:0] end - attribute \src "libresoc.v:154294.7-154294.31" - process $proc$libresoc.v:154294$8020 + attribute \src "libresoc.v:155602.7-155602.31" + process $proc$libresoc.v:155602$8004 assign { } { } assign $1\mul_op__is_signed[0:0] 1'0 sync always sync init update \mul_op__is_signed $1\mul_op__is_signed[0:0] end - attribute \src "libresoc.v:154303.7-154303.28" - process $proc$libresoc.v:154303$8021 + attribute \src "libresoc.v:155611.7-155611.28" + process $proc$libresoc.v:155611$8005 assign { } { } assign $1\mul_op__oe__oe[0:0] 1'0 sync always sync init update \mul_op__oe__oe $1\mul_op__oe__oe[0:0] end - attribute \src "libresoc.v:154312.7-154312.28" - process $proc$libresoc.v:154312$8022 + attribute \src "libresoc.v:155620.7-155620.28" + process $proc$libresoc.v:155620$8006 assign { } { } assign $1\mul_op__oe__ok[0:0] 1'0 sync always sync init update \mul_op__oe__ok $1\mul_op__oe__ok[0:0] end - attribute \src "libresoc.v:154321.7-154321.28" - process $proc$libresoc.v:154321$8023 + attribute \src "libresoc.v:155629.7-155629.28" + process $proc$libresoc.v:155629$8007 assign { } { } assign $1\mul_op__rc__ok[0:0] 1'0 sync always sync init update \mul_op__rc__ok $1\mul_op__rc__ok[0:0] end - attribute \src "libresoc.v:154330.7-154330.28" - process $proc$libresoc.v:154330$8024 + attribute \src "libresoc.v:155638.7-155638.28" + process $proc$libresoc.v:155638$8008 assign { } { } assign $1\mul_op__rc__rc[0:0] 1'0 sync always sync init update \mul_op__rc__rc $1\mul_op__rc__rc[0:0] end - attribute \src "libresoc.v:154339.7-154339.31" - process $proc$libresoc.v:154339$8025 + attribute \src "libresoc.v:155647.7-155647.31" + process $proc$libresoc.v:155647$8009 assign { } { } assign $1\mul_op__write_cr0[0:0] 1'0 sync always sync init update \mul_op__write_cr0 $1\mul_op__write_cr0[0:0] end - attribute \src "libresoc.v:154348.13-154348.25" - process $proc$libresoc.v:154348$8026 + attribute \src "libresoc.v:155656.13-155656.25" + process $proc$libresoc.v:155656$8010 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:154363.7-154363.21" - process $proc$libresoc.v:154363$8027 + attribute \src "libresoc.v:155671.7-155671.21" + process $proc$libresoc.v:155671$8011 assign { } { } assign $1\neg_res[0:0] 1'0 sync always sync init update \neg_res $1\neg_res[0:0] end - attribute \src "libresoc.v:154370.7-154370.23" - process $proc$libresoc.v:154370$8028 + attribute \src "libresoc.v:155678.7-155678.23" + process $proc$libresoc.v:155678$8012 assign { } { } assign $1\neg_res32[0:0] 1'0 sync always sync init update \neg_res32 $1\neg_res32[0:0] end - attribute \src "libresoc.v:154384.7-154384.20" - process $proc$libresoc.v:154384$8029 + attribute \src "libresoc.v:155692.7-155692.20" + process $proc$libresoc.v:155692$8013 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:154389.14-154389.39" - process $proc$libresoc.v:154389$8030 + attribute \src "libresoc.v:155697.14-155697.39" + process $proc$libresoc.v:155697$8014 assign { } { } assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ra $1\ra[63:0] end - attribute \src "libresoc.v:154398.14-154398.39" - process $proc$libresoc.v:154398$8031 + attribute \src "libresoc.v:155706.14-155706.39" + process $proc$libresoc.v:155706$8015 assign { } { } assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \rb $1\rb[63:0] end - attribute \src "libresoc.v:154407.7-154407.20" - process $proc$libresoc.v:154407$8032 + attribute \src "libresoc.v:155715.7-155715.20" + process $proc$libresoc.v:155715$8016 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:154415.3-154416.35" - process $proc$libresoc.v:154415$7941 + attribute \src "libresoc.v:155723.3-155724.35" + process $proc$libresoc.v:155723$7925 assign { } { } assign $0\neg_res32[0:0] \neg_res32$next sync posedge \coresync_clk update \neg_res32 $0\neg_res32[0:0] end - attribute \src "libresoc.v:154417.3-154418.31" - process $proc$libresoc.v:154417$7942 + attribute \src "libresoc.v:155725.3-155726.31" + process $proc$libresoc.v:155725$7926 assign { } { } assign $0\neg_res[0:0] \neg_res$next sync posedge \coresync_clk update \neg_res $0\neg_res[0:0] end - attribute \src "libresoc.v:154419.3-154420.29" - process $proc$libresoc.v:154419$7943 + attribute \src "libresoc.v:155727.3-155728.29" + process $proc$libresoc.v:155727$7927 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:154421.3-154422.21" - process $proc$libresoc.v:154421$7944 + attribute \src "libresoc.v:155729.3-155730.21" + process $proc$libresoc.v:155729$7928 assign { } { } assign $0\rb[63:0] \rb$next sync posedge \coresync_clk update \rb $0\rb[63:0] end - attribute \src "libresoc.v:154423.3-154424.21" - process $proc$libresoc.v:154423$7945 + attribute \src "libresoc.v:155731.3-155732.21" + process $proc$libresoc.v:155731$7929 assign { } { } assign $0\ra[63:0] \ra$next sync posedge \coresync_clk update \ra $0\ra[63:0] end - attribute \src "libresoc.v:154425.3-154426.51" - process $proc$libresoc.v:154425$7946 + attribute \src "libresoc.v:155733.3-155734.51" + process $proc$libresoc.v:155733$7930 assign { } { } assign $0\mul_op__insn_type[6:0] \mul_op__insn_type$next sync posedge \coresync_clk update \mul_op__insn_type $0\mul_op__insn_type[6:0] end - attribute \src "libresoc.v:154427.3-154428.47" - process $proc$libresoc.v:154427$7947 + attribute \src "libresoc.v:155735.3-155736.47" + process $proc$libresoc.v:155735$7931 assign { } { } assign $0\mul_op__fn_unit[13:0] \mul_op__fn_unit$next sync posedge \coresync_clk update \mul_op__fn_unit $0\mul_op__fn_unit[13:0] end - attribute \src "libresoc.v:154429.3-154430.61" - process $proc$libresoc.v:154429$7948 + attribute \src "libresoc.v:155737.3-155738.61" + process $proc$libresoc.v:155737$7932 assign { } { } assign $0\mul_op__imm_data__data[63:0] \mul_op__imm_data__data$next sync posedge \coresync_clk update \mul_op__imm_data__data $0\mul_op__imm_data__data[63:0] end - attribute \src "libresoc.v:154431.3-154432.57" - process $proc$libresoc.v:154431$7949 + attribute \src "libresoc.v:155739.3-155740.57" + process $proc$libresoc.v:155739$7933 assign { } { } assign $0\mul_op__imm_data__ok[0:0] \mul_op__imm_data__ok$next sync posedge \coresync_clk update \mul_op__imm_data__ok $0\mul_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:154433.3-154434.45" - process $proc$libresoc.v:154433$7950 + attribute \src "libresoc.v:155741.3-155742.45" + process $proc$libresoc.v:155741$7934 assign { } { } assign $0\mul_op__rc__rc[0:0] \mul_op__rc__rc$next sync posedge \coresync_clk update \mul_op__rc__rc $0\mul_op__rc__rc[0:0] end - attribute \src "libresoc.v:154435.3-154436.45" - process $proc$libresoc.v:154435$7951 + attribute \src "libresoc.v:155743.3-155744.45" + process $proc$libresoc.v:155743$7935 assign { } { } assign $0\mul_op__rc__ok[0:0] \mul_op__rc__ok$next sync posedge \coresync_clk update \mul_op__rc__ok $0\mul_op__rc__ok[0:0] end - attribute \src "libresoc.v:154437.3-154438.45" - process $proc$libresoc.v:154437$7952 + attribute \src "libresoc.v:155745.3-155746.45" + process $proc$libresoc.v:155745$7936 assign { } { } assign $0\mul_op__oe__oe[0:0] \mul_op__oe__oe$next sync posedge \coresync_clk update \mul_op__oe__oe $0\mul_op__oe__oe[0:0] end - attribute \src "libresoc.v:154439.3-154440.45" - process $proc$libresoc.v:154439$7953 + attribute \src "libresoc.v:155747.3-155748.45" + process $proc$libresoc.v:155747$7937 assign { } { } assign $0\mul_op__oe__ok[0:0] \mul_op__oe__ok$next sync posedge \coresync_clk update \mul_op__oe__ok $0\mul_op__oe__ok[0:0] end - attribute \src "libresoc.v:154441.3-154442.51" - process $proc$libresoc.v:154441$7954 + attribute \src "libresoc.v:155749.3-155750.51" + process $proc$libresoc.v:155749$7938 assign { } { } assign $0\mul_op__write_cr0[0:0] \mul_op__write_cr0$next sync posedge \coresync_clk update \mul_op__write_cr0 $0\mul_op__write_cr0[0:0] end - attribute \src "libresoc.v:154443.3-154444.49" - process $proc$libresoc.v:154443$7955 + attribute \src "libresoc.v:155751.3-155752.49" + process $proc$libresoc.v:155751$7939 assign { } { } assign $0\mul_op__is_32bit[0:0] \mul_op__is_32bit$next sync posedge \coresync_clk update \mul_op__is_32bit $0\mul_op__is_32bit[0:0] end - attribute \src "libresoc.v:154445.3-154446.51" - process $proc$libresoc.v:154445$7956 + attribute \src "libresoc.v:155753.3-155754.51" + process $proc$libresoc.v:155753$7940 assign { } { } assign $0\mul_op__is_signed[0:0] \mul_op__is_signed$next sync posedge \coresync_clk update \mul_op__is_signed $0\mul_op__is_signed[0:0] end - attribute \src "libresoc.v:154447.3-154448.41" - process $proc$libresoc.v:154447$7957 + attribute \src "libresoc.v:155755.3-155756.41" + process $proc$libresoc.v:155755$7941 assign { } { } assign $0\mul_op__insn[31:0] \mul_op__insn$next sync posedge \coresync_clk update \mul_op__insn $0\mul_op__insn[31:0] end - attribute \src "libresoc.v:154449.3-154450.27" - process $proc$libresoc.v:154449$7958 + attribute \src "libresoc.v:155757.3-155758.27" + process $proc$libresoc.v:155757$7942 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:154451.3-154452.29" - process $proc$libresoc.v:154451$7959 + attribute \src "libresoc.v:155759.3-155760.29" + process $proc$libresoc.v:155759$7943 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:154531.3-154548.6" - process $proc$libresoc.v:154531$7960 + attribute \src "libresoc.v:155839.3-155856.6" + process $proc$libresoc.v:155839$7944 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$7961 $2\r_busy$next[0:0]$7963 - attribute \src "libresoc.v:154532.5-154532.29" + assign $0\r_busy$next[0:0]$7945 $2\r_busy$next[0:0]$7947 + attribute \src "libresoc.v:155840.5-155840.29" switch \initial - attribute \src "libresoc.v:154532.9-154532.17" + attribute \src "libresoc.v:155840.9-155840.17" case 1'1 case end @@ -319129,34 +290499,34 @@ module \mul_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$7962 1'1 + assign $1\r_busy$next[0:0]$7946 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$7962 1'0 + assign $1\r_busy$next[0:0]$7946 1'0 case - assign $1\r_busy$next[0:0]$7962 \r_busy + assign $1\r_busy$next[0:0]$7946 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$7963 1'0 + assign $2\r_busy$next[0:0]$7947 1'0 case - assign $2\r_busy$next[0:0]$7963 $1\r_busy$next[0:0]$7962 + assign $2\r_busy$next[0:0]$7947 $1\r_busy$next[0:0]$7946 end sync always - update \r_busy$next $0\r_busy$next[0:0]$7961 + update \r_busy$next $0\r_busy$next[0:0]$7945 end - attribute \src "libresoc.v:154549.3-154561.6" - process $proc$libresoc.v:154549$7964 + attribute \src "libresoc.v:155857.3-155869.6" + process $proc$libresoc.v:155857$7948 assign { } { } assign { } { } - assign $0\muxid$next[1:0]$7965 $1\muxid$next[1:0]$7966 - attribute \src "libresoc.v:154550.5-154550.29" + assign $0\muxid$next[1:0]$7949 $1\muxid$next[1:0]$7950 + attribute \src "libresoc.v:155858.5-155858.29" switch \initial - attribute \src "libresoc.v:154550.9-154550.17" + attribute \src "libresoc.v:155858.9-155858.17" case 1'1 case end @@ -319165,19 +290535,19 @@ module \mul_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$next[1:0]$7966 \muxid$52 + assign $1\muxid$next[1:0]$7950 \muxid$52 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$next[1:0]$7966 \muxid$52 + assign $1\muxid$next[1:0]$7950 \muxid$52 case - assign $1\muxid$next[1:0]$7966 \muxid + assign $1\muxid$next[1:0]$7950 \muxid end sync always - update \muxid$next $0\muxid$next[1:0]$7965 + update \muxid$next $0\muxid$next[1:0]$7949 end - attribute \src "libresoc.v:154562.3-154597.6" - process $proc$libresoc.v:154562$7967 + attribute \src "libresoc.v:155870.3-155905.6" + process $proc$libresoc.v:155870$7951 assign { } { } assign { } { } assign { } { } @@ -319202,27 +290572,27 @@ module \mul_pipe1 assign { } { } assign { } { } assign { } { } - assign $0\mul_op__fn_unit$next[13:0]$7968 $1\mul_op__fn_unit$next[13:0]$7980 + assign $0\mul_op__fn_unit$next[13:0]$7952 $1\mul_op__fn_unit$next[13:0]$7964 assign { } { } assign { } { } - assign $0\mul_op__insn$next[31:0]$7971 $1\mul_op__insn$next[31:0]$7983 - assign $0\mul_op__insn_type$next[6:0]$7972 $1\mul_op__insn_type$next[6:0]$7984 - assign $0\mul_op__is_32bit$next[0:0]$7973 $1\mul_op__is_32bit$next[0:0]$7985 - assign $0\mul_op__is_signed$next[0:0]$7974 $1\mul_op__is_signed$next[0:0]$7986 + assign $0\mul_op__insn$next[31:0]$7955 $1\mul_op__insn$next[31:0]$7967 + assign $0\mul_op__insn_type$next[6:0]$7956 $1\mul_op__insn_type$next[6:0]$7968 + assign $0\mul_op__is_32bit$next[0:0]$7957 $1\mul_op__is_32bit$next[0:0]$7969 + assign $0\mul_op__is_signed$next[0:0]$7958 $1\mul_op__is_signed$next[0:0]$7970 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\mul_op__write_cr0$next[0:0]$7979 $1\mul_op__write_cr0$next[0:0]$7991 - assign $0\mul_op__imm_data__data$next[63:0]$7969 $2\mul_op__imm_data__data$next[63:0]$7992 - assign $0\mul_op__imm_data__ok$next[0:0]$7970 $2\mul_op__imm_data__ok$next[0:0]$7993 - assign $0\mul_op__oe__oe$next[0:0]$7975 $2\mul_op__oe__oe$next[0:0]$7994 - assign $0\mul_op__oe__ok$next[0:0]$7976 $2\mul_op__oe__ok$next[0:0]$7995 - assign $0\mul_op__rc__ok$next[0:0]$7977 $2\mul_op__rc__ok$next[0:0]$7996 - assign $0\mul_op__rc__rc$next[0:0]$7978 $2\mul_op__rc__rc$next[0:0]$7997 - attribute \src "libresoc.v:154563.5-154563.29" + assign $0\mul_op__write_cr0$next[0:0]$7963 $1\mul_op__write_cr0$next[0:0]$7975 + assign $0\mul_op__imm_data__data$next[63:0]$7953 $2\mul_op__imm_data__data$next[63:0]$7976 + assign $0\mul_op__imm_data__ok$next[0:0]$7954 $2\mul_op__imm_data__ok$next[0:0]$7977 + assign $0\mul_op__oe__oe$next[0:0]$7959 $2\mul_op__oe__oe$next[0:0]$7978 + assign $0\mul_op__oe__ok$next[0:0]$7960 $2\mul_op__oe__ok$next[0:0]$7979 + assign $0\mul_op__rc__ok$next[0:0]$7961 $2\mul_op__rc__ok$next[0:0]$7980 + assign $0\mul_op__rc__rc$next[0:0]$7962 $2\mul_op__rc__rc$next[0:0]$7981 + attribute \src "libresoc.v:155871.5-155871.29" switch \initial - attribute \src "libresoc.v:154563.9-154563.17" + attribute \src "libresoc.v:155871.9-155871.17" case 1'1 case end @@ -319242,7 +290612,7 @@ module \mul_pipe1 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$next[31:0]$7983 $1\mul_op__is_signed$next[0:0]$7986 $1\mul_op__is_32bit$next[0:0]$7985 $1\mul_op__write_cr0$next[0:0]$7991 $1\mul_op__oe__ok$next[0:0]$7988 $1\mul_op__oe__oe$next[0:0]$7987 $1\mul_op__rc__ok$next[0:0]$7989 $1\mul_op__rc__rc$next[0:0]$7990 $1\mul_op__imm_data__ok$next[0:0]$7982 $1\mul_op__imm_data__data$next[63:0]$7981 $1\mul_op__fn_unit$next[13:0]$7980 $1\mul_op__insn_type$next[6:0]$7984 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } + assign { $1\mul_op__insn$next[31:0]$7967 $1\mul_op__is_signed$next[0:0]$7970 $1\mul_op__is_32bit$next[0:0]$7969 $1\mul_op__write_cr0$next[0:0]$7975 $1\mul_op__oe__ok$next[0:0]$7972 $1\mul_op__oe__oe$next[0:0]$7971 $1\mul_op__rc__ok$next[0:0]$7973 $1\mul_op__rc__rc$next[0:0]$7974 $1\mul_op__imm_data__ok$next[0:0]$7966 $1\mul_op__imm_data__data$next[63:0]$7965 $1\mul_op__fn_unit$next[13:0]$7964 $1\mul_op__insn_type$next[6:0]$7968 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -319257,20 +290627,20 @@ module \mul_pipe1 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$next[31:0]$7983 $1\mul_op__is_signed$next[0:0]$7986 $1\mul_op__is_32bit$next[0:0]$7985 $1\mul_op__write_cr0$next[0:0]$7991 $1\mul_op__oe__ok$next[0:0]$7988 $1\mul_op__oe__oe$next[0:0]$7987 $1\mul_op__rc__ok$next[0:0]$7989 $1\mul_op__rc__rc$next[0:0]$7990 $1\mul_op__imm_data__ok$next[0:0]$7982 $1\mul_op__imm_data__data$next[63:0]$7981 $1\mul_op__fn_unit$next[13:0]$7980 $1\mul_op__insn_type$next[6:0]$7984 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } + assign { $1\mul_op__insn$next[31:0]$7967 $1\mul_op__is_signed$next[0:0]$7970 $1\mul_op__is_32bit$next[0:0]$7969 $1\mul_op__write_cr0$next[0:0]$7975 $1\mul_op__oe__ok$next[0:0]$7972 $1\mul_op__oe__oe$next[0:0]$7971 $1\mul_op__rc__ok$next[0:0]$7973 $1\mul_op__rc__rc$next[0:0]$7974 $1\mul_op__imm_data__ok$next[0:0]$7966 $1\mul_op__imm_data__data$next[63:0]$7965 $1\mul_op__fn_unit$next[13:0]$7964 $1\mul_op__insn_type$next[6:0]$7968 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } case - assign $1\mul_op__fn_unit$next[13:0]$7980 \mul_op__fn_unit - assign $1\mul_op__imm_data__data$next[63:0]$7981 \mul_op__imm_data__data - assign $1\mul_op__imm_data__ok$next[0:0]$7982 \mul_op__imm_data__ok - assign $1\mul_op__insn$next[31:0]$7983 \mul_op__insn - assign $1\mul_op__insn_type$next[6:0]$7984 \mul_op__insn_type - assign $1\mul_op__is_32bit$next[0:0]$7985 \mul_op__is_32bit - assign $1\mul_op__is_signed$next[0:0]$7986 \mul_op__is_signed - assign $1\mul_op__oe__oe$next[0:0]$7987 \mul_op__oe__oe - assign $1\mul_op__oe__ok$next[0:0]$7988 \mul_op__oe__ok - assign $1\mul_op__rc__ok$next[0:0]$7989 \mul_op__rc__ok - assign $1\mul_op__rc__rc$next[0:0]$7990 \mul_op__rc__rc - assign $1\mul_op__write_cr0$next[0:0]$7991 \mul_op__write_cr0 + assign $1\mul_op__fn_unit$next[13:0]$7964 \mul_op__fn_unit + assign $1\mul_op__imm_data__data$next[63:0]$7965 \mul_op__imm_data__data + assign $1\mul_op__imm_data__ok$next[0:0]$7966 \mul_op__imm_data__ok + assign $1\mul_op__insn$next[31:0]$7967 \mul_op__insn + assign $1\mul_op__insn_type$next[6:0]$7968 \mul_op__insn_type + assign $1\mul_op__is_32bit$next[0:0]$7969 \mul_op__is_32bit + assign $1\mul_op__is_signed$next[0:0]$7970 \mul_op__is_signed + assign $1\mul_op__oe__oe$next[0:0]$7971 \mul_op__oe__oe + assign $1\mul_op__oe__ok$next[0:0]$7972 \mul_op__oe__ok + assign $1\mul_op__rc__ok$next[0:0]$7973 \mul_op__rc__ok + assign $1\mul_op__rc__rc$next[0:0]$7974 \mul_op__rc__rc + assign $1\mul_op__write_cr0$next[0:0]$7975 \mul_op__write_cr0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -319282,42 +290652,42 @@ module \mul_pipe1 assign { } { } assign { } { } assign { } { } - assign $2\mul_op__imm_data__data$next[63:0]$7992 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\mul_op__imm_data__ok$next[0:0]$7993 1'0 - assign $2\mul_op__rc__rc$next[0:0]$7997 1'0 - assign $2\mul_op__rc__ok$next[0:0]$7996 1'0 - assign $2\mul_op__oe__oe$next[0:0]$7994 1'0 - assign $2\mul_op__oe__ok$next[0:0]$7995 1'0 + assign $2\mul_op__imm_data__data$next[63:0]$7976 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\mul_op__imm_data__ok$next[0:0]$7977 1'0 + assign $2\mul_op__rc__rc$next[0:0]$7981 1'0 + assign $2\mul_op__rc__ok$next[0:0]$7980 1'0 + assign $2\mul_op__oe__oe$next[0:0]$7978 1'0 + assign $2\mul_op__oe__ok$next[0:0]$7979 1'0 case - assign $2\mul_op__imm_data__data$next[63:0]$7992 $1\mul_op__imm_data__data$next[63:0]$7981 - assign $2\mul_op__imm_data__ok$next[0:0]$7993 $1\mul_op__imm_data__ok$next[0:0]$7982 - assign $2\mul_op__oe__oe$next[0:0]$7994 $1\mul_op__oe__oe$next[0:0]$7987 - assign $2\mul_op__oe__ok$next[0:0]$7995 $1\mul_op__oe__ok$next[0:0]$7988 - assign $2\mul_op__rc__ok$next[0:0]$7996 $1\mul_op__rc__ok$next[0:0]$7989 - assign $2\mul_op__rc__rc$next[0:0]$7997 $1\mul_op__rc__rc$next[0:0]$7990 + assign $2\mul_op__imm_data__data$next[63:0]$7976 $1\mul_op__imm_data__data$next[63:0]$7965 + assign $2\mul_op__imm_data__ok$next[0:0]$7977 $1\mul_op__imm_data__ok$next[0:0]$7966 + assign $2\mul_op__oe__oe$next[0:0]$7978 $1\mul_op__oe__oe$next[0:0]$7971 + assign $2\mul_op__oe__ok$next[0:0]$7979 $1\mul_op__oe__ok$next[0:0]$7972 + assign $2\mul_op__rc__ok$next[0:0]$7980 $1\mul_op__rc__ok$next[0:0]$7973 + assign $2\mul_op__rc__rc$next[0:0]$7981 $1\mul_op__rc__rc$next[0:0]$7974 end sync always - update \mul_op__fn_unit$next $0\mul_op__fn_unit$next[13:0]$7968 - update \mul_op__imm_data__data$next $0\mul_op__imm_data__data$next[63:0]$7969 - update \mul_op__imm_data__ok$next $0\mul_op__imm_data__ok$next[0:0]$7970 - update \mul_op__insn$next $0\mul_op__insn$next[31:0]$7971 - update \mul_op__insn_type$next $0\mul_op__insn_type$next[6:0]$7972 - update \mul_op__is_32bit$next $0\mul_op__is_32bit$next[0:0]$7973 - update \mul_op__is_signed$next $0\mul_op__is_signed$next[0:0]$7974 - update \mul_op__oe__oe$next $0\mul_op__oe__oe$next[0:0]$7975 - update \mul_op__oe__ok$next $0\mul_op__oe__ok$next[0:0]$7976 - update \mul_op__rc__ok$next $0\mul_op__rc__ok$next[0:0]$7977 - update \mul_op__rc__rc$next $0\mul_op__rc__rc$next[0:0]$7978 - update \mul_op__write_cr0$next $0\mul_op__write_cr0$next[0:0]$7979 + update \mul_op__fn_unit$next $0\mul_op__fn_unit$next[13:0]$7952 + update \mul_op__imm_data__data$next $0\mul_op__imm_data__data$next[63:0]$7953 + update \mul_op__imm_data__ok$next $0\mul_op__imm_data__ok$next[0:0]$7954 + update \mul_op__insn$next $0\mul_op__insn$next[31:0]$7955 + update \mul_op__insn_type$next $0\mul_op__insn_type$next[6:0]$7956 + update \mul_op__is_32bit$next $0\mul_op__is_32bit$next[0:0]$7957 + update \mul_op__is_signed$next $0\mul_op__is_signed$next[0:0]$7958 + update \mul_op__oe__oe$next $0\mul_op__oe__oe$next[0:0]$7959 + update \mul_op__oe__ok$next $0\mul_op__oe__ok$next[0:0]$7960 + update \mul_op__rc__ok$next $0\mul_op__rc__ok$next[0:0]$7961 + update \mul_op__rc__rc$next $0\mul_op__rc__rc$next[0:0]$7962 + update \mul_op__write_cr0$next $0\mul_op__write_cr0$next[0:0]$7963 end - attribute \src "libresoc.v:154598.3-154610.6" - process $proc$libresoc.v:154598$7998 + attribute \src "libresoc.v:155906.3-155918.6" + process $proc$libresoc.v:155906$7982 assign { } { } assign { } { } - assign $0\ra$next[63:0]$7999 $1\ra$next[63:0]$8000 - attribute \src "libresoc.v:154599.5-154599.29" + assign $0\ra$next[63:0]$7983 $1\ra$next[63:0]$7984 + attribute \src "libresoc.v:155907.5-155907.29" switch \initial - attribute \src "libresoc.v:154599.9-154599.17" + attribute \src "libresoc.v:155907.9-155907.17" case 1'1 case end @@ -319326,25 +290696,25 @@ module \mul_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\ra$next[63:0]$8000 \ra$65 + assign $1\ra$next[63:0]$7984 \ra$65 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\ra$next[63:0]$8000 \ra$65 + assign $1\ra$next[63:0]$7984 \ra$65 case - assign $1\ra$next[63:0]$8000 \ra + assign $1\ra$next[63:0]$7984 \ra end sync always - update \ra$next $0\ra$next[63:0]$7999 + update \ra$next $0\ra$next[63:0]$7983 end - attribute \src "libresoc.v:154611.3-154623.6" - process $proc$libresoc.v:154611$8001 + attribute \src "libresoc.v:155919.3-155931.6" + process $proc$libresoc.v:155919$7985 assign { } { } assign { } { } - assign $0\rb$next[63:0]$8002 $1\rb$next[63:0]$8003 - attribute \src "libresoc.v:154612.5-154612.29" + assign $0\rb$next[63:0]$7986 $1\rb$next[63:0]$7987 + attribute \src "libresoc.v:155920.5-155920.29" switch \initial - attribute \src "libresoc.v:154612.9-154612.17" + attribute \src "libresoc.v:155920.9-155920.17" case 1'1 case end @@ -319353,25 +290723,25 @@ module \mul_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\rb$next[63:0]$8003 \rb$66 + assign $1\rb$next[63:0]$7987 \rb$66 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\rb$next[63:0]$8003 \rb$66 + assign $1\rb$next[63:0]$7987 \rb$66 case - assign $1\rb$next[63:0]$8003 \rb + assign $1\rb$next[63:0]$7987 \rb end sync always - update \rb$next $0\rb$next[63:0]$8002 + update \rb$next $0\rb$next[63:0]$7986 end - attribute \src "libresoc.v:154624.3-154636.6" - process $proc$libresoc.v:154624$8004 + attribute \src "libresoc.v:155932.3-155944.6" + process $proc$libresoc.v:155932$7988 assign { } { } assign { } { } - assign $0\xer_so$next[0:0]$8005 $1\xer_so$next[0:0]$8006 - attribute \src "libresoc.v:154625.5-154625.29" + assign $0\xer_so$next[0:0]$7989 $1\xer_so$next[0:0]$7990 + attribute \src "libresoc.v:155933.5-155933.29" switch \initial - attribute \src "libresoc.v:154625.9-154625.17" + attribute \src "libresoc.v:155933.9-155933.17" case 1'1 case end @@ -319380,25 +290750,25 @@ module \mul_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\xer_so$next[0:0]$8006 \xer_so$67 + assign $1\xer_so$next[0:0]$7990 \xer_so$67 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\xer_so$next[0:0]$8006 \xer_so$67 + assign $1\xer_so$next[0:0]$7990 \xer_so$67 case - assign $1\xer_so$next[0:0]$8006 \xer_so + assign $1\xer_so$next[0:0]$7990 \xer_so end sync always - update \xer_so$next $0\xer_so$next[0:0]$8005 + update \xer_so$next $0\xer_so$next[0:0]$7989 end - attribute \src "libresoc.v:154637.3-154649.6" - process $proc$libresoc.v:154637$8007 + attribute \src "libresoc.v:155945.3-155957.6" + process $proc$libresoc.v:155945$7991 assign { } { } assign { } { } - assign $0\neg_res$next[0:0]$8008 $1\neg_res$next[0:0]$8009 - attribute \src "libresoc.v:154638.5-154638.29" + assign $0\neg_res$next[0:0]$7992 $1\neg_res$next[0:0]$7993 + attribute \src "libresoc.v:155946.5-155946.29" switch \initial - attribute \src "libresoc.v:154638.9-154638.17" + attribute \src "libresoc.v:155946.9-155946.17" case 1'1 case end @@ -319407,25 +290777,25 @@ module \mul_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\neg_res$next[0:0]$8009 \neg_res$68 + assign $1\neg_res$next[0:0]$7993 \neg_res$68 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\neg_res$next[0:0]$8009 \neg_res$68 + assign $1\neg_res$next[0:0]$7993 \neg_res$68 case - assign $1\neg_res$next[0:0]$8009 \neg_res + assign $1\neg_res$next[0:0]$7993 \neg_res end sync always - update \neg_res$next $0\neg_res$next[0:0]$8008 + update \neg_res$next $0\neg_res$next[0:0]$7992 end - attribute \src "libresoc.v:154650.3-154662.6" - process $proc$libresoc.v:154650$8010 + attribute \src "libresoc.v:155958.3-155970.6" + process $proc$libresoc.v:155958$7994 assign { } { } assign { } { } - assign $0\neg_res32$next[0:0]$8011 $1\neg_res32$next[0:0]$8012 - attribute \src "libresoc.v:154651.5-154651.29" + assign $0\neg_res32$next[0:0]$7995 $1\neg_res32$next[0:0]$7996 + attribute \src "libresoc.v:155959.5-155959.29" switch \initial - attribute \src "libresoc.v:154651.9-154651.17" + attribute \src "libresoc.v:155959.9-155959.17" case 1'1 case end @@ -319434,18 +290804,18 @@ module \mul_pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\neg_res32$next[0:0]$8012 \neg_res32$69 + assign $1\neg_res32$next[0:0]$7996 \neg_res32$69 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\neg_res32$next[0:0]$8012 \neg_res32$69 + assign $1\neg_res32$next[0:0]$7996 \neg_res32$69 case - assign $1\neg_res32$next[0:0]$8012 \neg_res32 + assign $1\neg_res32$next[0:0]$7996 \neg_res32 end sync always - update \neg_res32$next $0\neg_res32$next[0:0]$8011 + update \neg_res32$next $0\neg_res32$next[0:0]$7995 end - connect \$50 $and$libresoc.v:154414$7940_Y + connect \$50 $and$libresoc.v:155722$7924_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect \neg_res32$69 \mul1_neg_res32 @@ -319469,180 +290839,180 @@ module \mul_pipe1 connect { \input_mul_op__insn \input_mul_op__is_signed \input_mul_op__is_32bit \input_mul_op__write_cr0 \input_mul_op__oe__ok \input_mul_op__oe__oe \input_mul_op__rc__ok \input_mul_op__rc__rc \input_mul_op__imm_data__ok \input_mul_op__imm_data__data \input_mul_op__fn_unit \input_mul_op__insn_type } { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:154689.1-155609.10" +attribute \src "libresoc.v:155997.1-156917.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2" attribute \generator "nMigen" module \mul_pipe2 - attribute \src "libresoc.v:154690.7-154690.20" + attribute \src "libresoc.v:155998.7-155998.20" wire $0\initial[0:0] - attribute \src "libresoc.v:155503.3-155538.6" - wire width 14 $0\mul_op__fn_unit$3$next[13:0]$8076 - attribute \src "libresoc.v:155401.3-155402.53" - wire width 14 $0\mul_op__fn_unit$3[13:0]$8044 - attribute \src "libresoc.v:154981.14-154981.44" - wire width 14 $0\mul_op__fn_unit$3[13:0]$8120 - attribute \src "libresoc.v:155503.3-155538.6" - wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$8077 - attribute \src "libresoc.v:155403.3-155404.67" - wire width 64 $0\mul_op__imm_data__data$4[63:0]$8046 - attribute \src "libresoc.v:155007.14-155007.63" - wire width 64 $0\mul_op__imm_data__data$4[63:0]$8122 - attribute \src "libresoc.v:155503.3-155538.6" - wire $0\mul_op__imm_data__ok$5$next[0:0]$8078 - attribute \src "libresoc.v:155405.3-155406.63" - wire $0\mul_op__imm_data__ok$5[0:0]$8048 - attribute \src "libresoc.v:155016.7-155016.38" - wire $0\mul_op__imm_data__ok$5[0:0]$8124 - attribute \src "libresoc.v:155503.3-155538.6" - wire width 32 $0\mul_op__insn$13$next[31:0]$8079 - attribute \src "libresoc.v:155421.3-155422.49" - wire width 32 $0\mul_op__insn$13[31:0]$8064 - attribute \src "libresoc.v:155023.14-155023.39" - wire width 32 $0\mul_op__insn$13[31:0]$8126 - attribute \src "libresoc.v:155503.3-155538.6" - wire width 7 $0\mul_op__insn_type$2$next[6:0]$8080 - attribute \src "libresoc.v:155399.3-155400.57" - wire width 7 $0\mul_op__insn_type$2[6:0]$8042 - attribute \src "libresoc.v:155182.13-155182.42" - wire width 7 $0\mul_op__insn_type$2[6:0]$8128 - attribute \src "libresoc.v:155503.3-155538.6" - wire $0\mul_op__is_32bit$11$next[0:0]$8081 - attribute \src "libresoc.v:155417.3-155418.57" - wire $0\mul_op__is_32bit$11[0:0]$8060 - attribute \src "libresoc.v:155266.7-155266.35" - wire $0\mul_op__is_32bit$11[0:0]$8130 - attribute \src "libresoc.v:155503.3-155538.6" - wire $0\mul_op__is_signed$12$next[0:0]$8082 - attribute \src "libresoc.v:155419.3-155420.59" - wire $0\mul_op__is_signed$12[0:0]$8062 - attribute \src "libresoc.v:155275.7-155275.36" - wire $0\mul_op__is_signed$12[0:0]$8132 - attribute \src "libresoc.v:155503.3-155538.6" - wire $0\mul_op__oe__oe$8$next[0:0]$8083 - attribute \src "libresoc.v:155411.3-155412.51" - wire $0\mul_op__oe__oe$8[0:0]$8054 - attribute \src "libresoc.v:155286.7-155286.32" - wire $0\mul_op__oe__oe$8[0:0]$8134 - attribute \src "libresoc.v:155503.3-155538.6" - wire $0\mul_op__oe__ok$9$next[0:0]$8084 - attribute \src "libresoc.v:155413.3-155414.51" - wire $0\mul_op__oe__ok$9[0:0]$8056 - attribute \src "libresoc.v:155295.7-155295.32" - wire $0\mul_op__oe__ok$9[0:0]$8136 - attribute \src "libresoc.v:155503.3-155538.6" - wire $0\mul_op__rc__ok$7$next[0:0]$8085 - attribute \src "libresoc.v:155409.3-155410.51" - wire $0\mul_op__rc__ok$7[0:0]$8052 - attribute \src "libresoc.v:155304.7-155304.32" - wire $0\mul_op__rc__ok$7[0:0]$8138 - attribute \src "libresoc.v:155503.3-155538.6" - wire $0\mul_op__rc__rc$6$next[0:0]$8086 - attribute \src "libresoc.v:155407.3-155408.51" - wire $0\mul_op__rc__rc$6[0:0]$8050 - attribute \src "libresoc.v:155313.7-155313.32" - wire $0\mul_op__rc__rc$6[0:0]$8140 - attribute \src "libresoc.v:155503.3-155538.6" - wire $0\mul_op__write_cr0$10$next[0:0]$8087 - attribute \src "libresoc.v:155415.3-155416.59" - wire $0\mul_op__write_cr0$10[0:0]$8058 - attribute \src "libresoc.v:155320.7-155320.36" - wire $0\mul_op__write_cr0$10[0:0]$8142 - attribute \src "libresoc.v:155490.3-155502.6" - wire width 2 $0\muxid$1$next[1:0]$8073 - attribute \src "libresoc.v:155423.3-155424.33" - wire width 2 $0\muxid$1[1:0]$8066 - attribute \src "libresoc.v:155329.13-155329.29" - wire width 2 $0\muxid$1[1:0]$8144 - attribute \src "libresoc.v:155565.3-155577.6" - wire $0\neg_res$15$next[0:0]$8113 - attribute \src "libresoc.v:155393.3-155394.39" - wire $0\neg_res$15[0:0]$8037 - attribute \src "libresoc.v:155344.7-155344.26" - wire $0\neg_res$15[0:0]$8146 - attribute \src "libresoc.v:155578.3-155590.6" - wire $0\neg_res32$16$next[0:0]$8116 - attribute \src "libresoc.v:155391.3-155392.43" - wire $0\neg_res32$16[0:0]$8035 - attribute \src "libresoc.v:155353.7-155353.28" - wire $0\neg_res32$16[0:0]$8148 - attribute \src "libresoc.v:155539.3-155551.6" - wire width 129 $0\o$next[128:0]$8107 - attribute \src "libresoc.v:155397.3-155398.19" + attribute \src "libresoc.v:156811.3-156846.6" + wire width 14 $0\mul_op__fn_unit$3$next[13:0]$8060 + attribute \src "libresoc.v:156709.3-156710.53" + wire width 14 $0\mul_op__fn_unit$3[13:0]$8028 + attribute \src "libresoc.v:156289.14-156289.44" + wire width 14 $0\mul_op__fn_unit$3[13:0]$8104 + attribute \src "libresoc.v:156811.3-156846.6" + wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$8061 + attribute \src "libresoc.v:156711.3-156712.67" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$8030 + attribute \src "libresoc.v:156315.14-156315.63" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$8106 + attribute \src "libresoc.v:156811.3-156846.6" + wire $0\mul_op__imm_data__ok$5$next[0:0]$8062 + attribute \src "libresoc.v:156713.3-156714.63" + wire $0\mul_op__imm_data__ok$5[0:0]$8032 + attribute \src "libresoc.v:156324.7-156324.38" + wire $0\mul_op__imm_data__ok$5[0:0]$8108 + attribute \src "libresoc.v:156811.3-156846.6" + wire width 32 $0\mul_op__insn$13$next[31:0]$8063 + attribute \src "libresoc.v:156729.3-156730.49" + wire width 32 $0\mul_op__insn$13[31:0]$8048 + attribute \src "libresoc.v:156331.14-156331.39" + wire width 32 $0\mul_op__insn$13[31:0]$8110 + attribute \src "libresoc.v:156811.3-156846.6" + wire width 7 $0\mul_op__insn_type$2$next[6:0]$8064 + attribute \src "libresoc.v:156707.3-156708.57" + wire width 7 $0\mul_op__insn_type$2[6:0]$8026 + attribute \src "libresoc.v:156490.13-156490.42" + wire width 7 $0\mul_op__insn_type$2[6:0]$8112 + attribute \src "libresoc.v:156811.3-156846.6" + wire $0\mul_op__is_32bit$11$next[0:0]$8065 + attribute \src "libresoc.v:156725.3-156726.57" + wire $0\mul_op__is_32bit$11[0:0]$8044 + attribute \src "libresoc.v:156574.7-156574.35" + wire $0\mul_op__is_32bit$11[0:0]$8114 + attribute \src "libresoc.v:156811.3-156846.6" + wire $0\mul_op__is_signed$12$next[0:0]$8066 + attribute \src "libresoc.v:156727.3-156728.59" + wire $0\mul_op__is_signed$12[0:0]$8046 + attribute \src "libresoc.v:156583.7-156583.36" + wire $0\mul_op__is_signed$12[0:0]$8116 + attribute \src "libresoc.v:156811.3-156846.6" + wire $0\mul_op__oe__oe$8$next[0:0]$8067 + attribute \src "libresoc.v:156719.3-156720.51" + wire $0\mul_op__oe__oe$8[0:0]$8038 + attribute \src "libresoc.v:156594.7-156594.32" + wire $0\mul_op__oe__oe$8[0:0]$8118 + attribute \src "libresoc.v:156811.3-156846.6" + wire $0\mul_op__oe__ok$9$next[0:0]$8068 + attribute \src "libresoc.v:156721.3-156722.51" + wire $0\mul_op__oe__ok$9[0:0]$8040 + attribute \src "libresoc.v:156603.7-156603.32" + wire $0\mul_op__oe__ok$9[0:0]$8120 + attribute \src "libresoc.v:156811.3-156846.6" + wire $0\mul_op__rc__ok$7$next[0:0]$8069 + attribute \src "libresoc.v:156717.3-156718.51" + wire $0\mul_op__rc__ok$7[0:0]$8036 + attribute \src "libresoc.v:156612.7-156612.32" + wire $0\mul_op__rc__ok$7[0:0]$8122 + attribute \src "libresoc.v:156811.3-156846.6" + wire $0\mul_op__rc__rc$6$next[0:0]$8070 + attribute \src "libresoc.v:156715.3-156716.51" + wire $0\mul_op__rc__rc$6[0:0]$8034 + attribute \src "libresoc.v:156621.7-156621.32" + wire $0\mul_op__rc__rc$6[0:0]$8124 + attribute \src "libresoc.v:156811.3-156846.6" + wire $0\mul_op__write_cr0$10$next[0:0]$8071 + attribute \src "libresoc.v:156723.3-156724.59" + wire $0\mul_op__write_cr0$10[0:0]$8042 + attribute \src "libresoc.v:156628.7-156628.36" + wire $0\mul_op__write_cr0$10[0:0]$8126 + attribute \src "libresoc.v:156798.3-156810.6" + wire width 2 $0\muxid$1$next[1:0]$8057 + attribute \src "libresoc.v:156731.3-156732.33" + wire width 2 $0\muxid$1[1:0]$8050 + attribute \src "libresoc.v:156637.13-156637.29" + wire width 2 $0\muxid$1[1:0]$8128 + attribute \src "libresoc.v:156873.3-156885.6" + wire $0\neg_res$15$next[0:0]$8097 + attribute \src "libresoc.v:156701.3-156702.39" + wire $0\neg_res$15[0:0]$8021 + attribute \src "libresoc.v:156652.7-156652.26" + wire $0\neg_res$15[0:0]$8130 + attribute \src "libresoc.v:156886.3-156898.6" + wire $0\neg_res32$16$next[0:0]$8100 + attribute \src "libresoc.v:156699.3-156700.43" + wire $0\neg_res32$16[0:0]$8019 + attribute \src "libresoc.v:156661.7-156661.28" + wire $0\neg_res32$16[0:0]$8132 + attribute \src "libresoc.v:156847.3-156859.6" + wire width 129 $0\o$next[128:0]$8091 + attribute \src "libresoc.v:156705.3-156706.19" wire width 129 $0\o[128:0] - attribute \src "libresoc.v:155472.3-155489.6" - wire $0\r_busy$next[0:0]$8069 - attribute \src "libresoc.v:155425.3-155426.29" + attribute \src "libresoc.v:156780.3-156797.6" + wire $0\r_busy$next[0:0]$8053 + attribute \src "libresoc.v:156733.3-156734.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:155552.3-155564.6" - wire $0\xer_so$14$next[0:0]$8110 - attribute \src "libresoc.v:155395.3-155396.37" - wire $0\xer_so$14[0:0]$8039 - attribute \src "libresoc.v:155385.7-155385.25" - wire $0\xer_so$14[0:0]$8152 - attribute \src "libresoc.v:155503.3-155538.6" - wire width 14 $1\mul_op__fn_unit$3$next[13:0]$8088 - attribute \src "libresoc.v:155503.3-155538.6" - wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$8089 - attribute \src "libresoc.v:155503.3-155538.6" - wire $1\mul_op__imm_data__ok$5$next[0:0]$8090 - attribute \src "libresoc.v:155503.3-155538.6" - wire width 32 $1\mul_op__insn$13$next[31:0]$8091 - attribute \src "libresoc.v:155503.3-155538.6" - wire width 7 $1\mul_op__insn_type$2$next[6:0]$8092 - attribute \src "libresoc.v:155503.3-155538.6" - wire $1\mul_op__is_32bit$11$next[0:0]$8093 - attribute \src "libresoc.v:155503.3-155538.6" - wire $1\mul_op__is_signed$12$next[0:0]$8094 - attribute \src "libresoc.v:155503.3-155538.6" - wire $1\mul_op__oe__oe$8$next[0:0]$8095 - attribute \src "libresoc.v:155503.3-155538.6" - wire $1\mul_op__oe__ok$9$next[0:0]$8096 - attribute \src "libresoc.v:155503.3-155538.6" - wire $1\mul_op__rc__ok$7$next[0:0]$8097 - attribute \src "libresoc.v:155503.3-155538.6" - wire $1\mul_op__rc__rc$6$next[0:0]$8098 - attribute \src "libresoc.v:155503.3-155538.6" - wire $1\mul_op__write_cr0$10$next[0:0]$8099 - attribute \src "libresoc.v:155490.3-155502.6" - wire width 2 $1\muxid$1$next[1:0]$8074 - attribute \src "libresoc.v:155565.3-155577.6" - wire $1\neg_res$15$next[0:0]$8114 - attribute \src "libresoc.v:155578.3-155590.6" - wire $1\neg_res32$16$next[0:0]$8117 - attribute \src "libresoc.v:155539.3-155551.6" - wire width 129 $1\o$next[128:0]$8108 - attribute \src "libresoc.v:155360.15-155360.57" + attribute \src "libresoc.v:156860.3-156872.6" + wire $0\xer_so$14$next[0:0]$8094 + attribute \src "libresoc.v:156703.3-156704.37" + wire $0\xer_so$14[0:0]$8023 + attribute \src "libresoc.v:156693.7-156693.25" + wire $0\xer_so$14[0:0]$8136 + attribute \src "libresoc.v:156811.3-156846.6" + wire width 14 $1\mul_op__fn_unit$3$next[13:0]$8072 + attribute \src "libresoc.v:156811.3-156846.6" + wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$8073 + attribute \src "libresoc.v:156811.3-156846.6" + wire $1\mul_op__imm_data__ok$5$next[0:0]$8074 + attribute \src "libresoc.v:156811.3-156846.6" + wire width 32 $1\mul_op__insn$13$next[31:0]$8075 + attribute \src "libresoc.v:156811.3-156846.6" + wire width 7 $1\mul_op__insn_type$2$next[6:0]$8076 + attribute \src "libresoc.v:156811.3-156846.6" + wire $1\mul_op__is_32bit$11$next[0:0]$8077 + attribute \src "libresoc.v:156811.3-156846.6" + wire $1\mul_op__is_signed$12$next[0:0]$8078 + attribute \src "libresoc.v:156811.3-156846.6" + wire $1\mul_op__oe__oe$8$next[0:0]$8079 + attribute \src "libresoc.v:156811.3-156846.6" + wire $1\mul_op__oe__ok$9$next[0:0]$8080 + attribute \src "libresoc.v:156811.3-156846.6" + wire $1\mul_op__rc__ok$7$next[0:0]$8081 + attribute \src "libresoc.v:156811.3-156846.6" + wire $1\mul_op__rc__rc$6$next[0:0]$8082 + attribute \src "libresoc.v:156811.3-156846.6" + wire $1\mul_op__write_cr0$10$next[0:0]$8083 + attribute \src "libresoc.v:156798.3-156810.6" + wire width 2 $1\muxid$1$next[1:0]$8058 + attribute \src "libresoc.v:156873.3-156885.6" + wire $1\neg_res$15$next[0:0]$8098 + attribute \src "libresoc.v:156886.3-156898.6" + wire $1\neg_res32$16$next[0:0]$8101 + attribute \src "libresoc.v:156847.3-156859.6" + wire width 129 $1\o$next[128:0]$8092 + attribute \src "libresoc.v:156668.15-156668.57" wire width 129 $1\o[128:0] - attribute \src "libresoc.v:155472.3-155489.6" - wire $1\r_busy$next[0:0]$8070 - attribute \src "libresoc.v:155374.7-155374.20" + attribute \src "libresoc.v:156780.3-156797.6" + wire $1\r_busy$next[0:0]$8054 + attribute \src "libresoc.v:156682.7-156682.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:155552.3-155564.6" - wire $1\xer_so$14$next[0:0]$8111 - attribute \src "libresoc.v:155503.3-155538.6" - wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8100 - attribute \src "libresoc.v:155503.3-155538.6" - wire $2\mul_op__imm_data__ok$5$next[0:0]$8101 - attribute \src "libresoc.v:155503.3-155538.6" - wire $2\mul_op__oe__oe$8$next[0:0]$8102 - attribute \src "libresoc.v:155503.3-155538.6" - wire $2\mul_op__oe__ok$9$next[0:0]$8103 - attribute \src "libresoc.v:155503.3-155538.6" - wire $2\mul_op__rc__ok$7$next[0:0]$8104 - attribute \src "libresoc.v:155503.3-155538.6" - wire $2\mul_op__rc__rc$6$next[0:0]$8105 - attribute \src "libresoc.v:155472.3-155489.6" - wire $2\r_busy$next[0:0]$8071 - attribute \src "libresoc.v:155390.18-155390.118" - wire $and$libresoc.v:155390$8033_Y + attribute \src "libresoc.v:156860.3-156872.6" + wire $1\xer_so$14$next[0:0]$8095 + attribute \src "libresoc.v:156811.3-156846.6" + wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8084 + attribute \src "libresoc.v:156811.3-156846.6" + wire $2\mul_op__imm_data__ok$5$next[0:0]$8085 + attribute \src "libresoc.v:156811.3-156846.6" + wire $2\mul_op__oe__oe$8$next[0:0]$8086 + attribute \src "libresoc.v:156811.3-156846.6" + wire $2\mul_op__oe__ok$9$next[0:0]$8087 + attribute \src "libresoc.v:156811.3-156846.6" + wire $2\mul_op__rc__ok$7$next[0:0]$8088 + attribute \src "libresoc.v:156811.3-156846.6" + wire $2\mul_op__rc__rc$6$next[0:0]$8089 + attribute \src "libresoc.v:156780.3-156797.6" + wire $2\r_busy$next[0:0]$8055 + attribute \src "libresoc.v:156698.18-156698.118" + wire $and$libresoc.v:156698$8017_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 41 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:154690.7-154690.15" + attribute \src "libresoc.v:155998.7-155998.15" wire \initial attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -320321,7 +291691,7 @@ module \mul_pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \xer_so$50 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:155390$8033 + cell $and $and$libresoc.v:156698$8017 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -320329,10 +291699,10 @@ module \mul_pipe2 parameter \Y_WIDTH 1 connect \A \p_valid_i$33 connect \B \p_ready_o - connect \Y $and$libresoc.v:155390$8033_Y + connect \Y $and$libresoc.v:156698$8017_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:155427.8-155463.4" + attribute \src "libresoc.v:156735.8-156771.4" cell \mul2 \mul2 connect \mul_op__fn_unit \mul2_mul_op__fn_unit connect \mul_op__fn_unit$3 \mul2_mul_op__fn_unit$19 @@ -320371,304 +291741,304 @@ module \mul_pipe2 connect \xer_so$14 \mul2_xer_so$30 end attribute \module_not_derived 1 - attribute \src "libresoc.v:155464.10-155467.4" + attribute \src "libresoc.v:156772.10-156775.4" cell \n$97 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:155468.10-155471.4" + attribute \src "libresoc.v:156776.10-156779.4" cell \p$96 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:154690.7-154690.20" - process $proc$libresoc.v:154690$8118 + attribute \src "libresoc.v:155998.7-155998.20" + process $proc$libresoc.v:155998$8102 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:154981.14-154981.44" - process $proc$libresoc.v:154981$8119 + attribute \src "libresoc.v:156289.14-156289.44" + process $proc$libresoc.v:156289$8103 assign { } { } - assign $0\mul_op__fn_unit$3[13:0]$8120 14'00000000000000 + assign $0\mul_op__fn_unit$3[13:0]$8104 14'00000000000000 sync always sync init - update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8120 + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8104 end - attribute \src "libresoc.v:155007.14-155007.63" - process $proc$libresoc.v:155007$8121 + attribute \src "libresoc.v:156315.14-156315.63" + process $proc$libresoc.v:156315$8105 assign { } { } - assign $0\mul_op__imm_data__data$4[63:0]$8122 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\mul_op__imm_data__data$4[63:0]$8106 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8122 + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8106 end - attribute \src "libresoc.v:155016.7-155016.38" - process $proc$libresoc.v:155016$8123 + attribute \src "libresoc.v:156324.7-156324.38" + process $proc$libresoc.v:156324$8107 assign { } { } - assign $0\mul_op__imm_data__ok$5[0:0]$8124 1'0 + assign $0\mul_op__imm_data__ok$5[0:0]$8108 1'0 sync always sync init - update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8124 + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8108 end - attribute \src "libresoc.v:155023.14-155023.39" - process $proc$libresoc.v:155023$8125 + attribute \src "libresoc.v:156331.14-156331.39" + process $proc$libresoc.v:156331$8109 assign { } { } - assign $0\mul_op__insn$13[31:0]$8126 0 + assign $0\mul_op__insn$13[31:0]$8110 0 sync always sync init - update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8126 + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8110 end - attribute \src "libresoc.v:155182.13-155182.42" - process $proc$libresoc.v:155182$8127 + attribute \src "libresoc.v:156490.13-156490.42" + process $proc$libresoc.v:156490$8111 assign { } { } - assign $0\mul_op__insn_type$2[6:0]$8128 7'0000000 + assign $0\mul_op__insn_type$2[6:0]$8112 7'0000000 sync always sync init - update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8128 + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8112 end - attribute \src "libresoc.v:155266.7-155266.35" - process $proc$libresoc.v:155266$8129 + attribute \src "libresoc.v:156574.7-156574.35" + process $proc$libresoc.v:156574$8113 assign { } { } - assign $0\mul_op__is_32bit$11[0:0]$8130 1'0 + assign $0\mul_op__is_32bit$11[0:0]$8114 1'0 sync always sync init - update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8130 + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8114 end - attribute \src "libresoc.v:155275.7-155275.36" - process $proc$libresoc.v:155275$8131 + attribute \src "libresoc.v:156583.7-156583.36" + process $proc$libresoc.v:156583$8115 assign { } { } - assign $0\mul_op__is_signed$12[0:0]$8132 1'0 + assign $0\mul_op__is_signed$12[0:0]$8116 1'0 sync always sync init - update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8132 + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8116 end - attribute \src "libresoc.v:155286.7-155286.32" - process $proc$libresoc.v:155286$8133 + attribute \src "libresoc.v:156594.7-156594.32" + process $proc$libresoc.v:156594$8117 assign { } { } - assign $0\mul_op__oe__oe$8[0:0]$8134 1'0 + assign $0\mul_op__oe__oe$8[0:0]$8118 1'0 sync always sync init - update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8134 + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8118 end - attribute \src "libresoc.v:155295.7-155295.32" - process $proc$libresoc.v:155295$8135 + attribute \src "libresoc.v:156603.7-156603.32" + process $proc$libresoc.v:156603$8119 assign { } { } - assign $0\mul_op__oe__ok$9[0:0]$8136 1'0 + assign $0\mul_op__oe__ok$9[0:0]$8120 1'0 sync always sync init - update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8136 + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8120 end - attribute \src "libresoc.v:155304.7-155304.32" - process $proc$libresoc.v:155304$8137 + attribute \src "libresoc.v:156612.7-156612.32" + process $proc$libresoc.v:156612$8121 assign { } { } - assign $0\mul_op__rc__ok$7[0:0]$8138 1'0 + assign $0\mul_op__rc__ok$7[0:0]$8122 1'0 sync always sync init - update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8138 + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8122 end - attribute \src "libresoc.v:155313.7-155313.32" - process $proc$libresoc.v:155313$8139 + attribute \src "libresoc.v:156621.7-156621.32" + process $proc$libresoc.v:156621$8123 assign { } { } - assign $0\mul_op__rc__rc$6[0:0]$8140 1'0 + assign $0\mul_op__rc__rc$6[0:0]$8124 1'0 sync always sync init - update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8140 + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8124 end - attribute \src "libresoc.v:155320.7-155320.36" - process $proc$libresoc.v:155320$8141 + attribute \src "libresoc.v:156628.7-156628.36" + process $proc$libresoc.v:156628$8125 assign { } { } - assign $0\mul_op__write_cr0$10[0:0]$8142 1'0 + assign $0\mul_op__write_cr0$10[0:0]$8126 1'0 sync always sync init - update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8142 + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8126 end - attribute \src "libresoc.v:155329.13-155329.29" - process $proc$libresoc.v:155329$8143 + attribute \src "libresoc.v:156637.13-156637.29" + process $proc$libresoc.v:156637$8127 assign { } { } - assign $0\muxid$1[1:0]$8144 2'00 + assign $0\muxid$1[1:0]$8128 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$8144 + update \muxid$1 $0\muxid$1[1:0]$8128 end - attribute \src "libresoc.v:155344.7-155344.26" - process $proc$libresoc.v:155344$8145 + attribute \src "libresoc.v:156652.7-156652.26" + process $proc$libresoc.v:156652$8129 assign { } { } - assign $0\neg_res$15[0:0]$8146 1'0 + assign $0\neg_res$15[0:0]$8130 1'0 sync always sync init - update \neg_res$15 $0\neg_res$15[0:0]$8146 + update \neg_res$15 $0\neg_res$15[0:0]$8130 end - attribute \src "libresoc.v:155353.7-155353.28" - process $proc$libresoc.v:155353$8147 + attribute \src "libresoc.v:156661.7-156661.28" + process $proc$libresoc.v:156661$8131 assign { } { } - assign $0\neg_res32$16[0:0]$8148 1'0 + assign $0\neg_res32$16[0:0]$8132 1'0 sync always sync init - update \neg_res32$16 $0\neg_res32$16[0:0]$8148 + update \neg_res32$16 $0\neg_res32$16[0:0]$8132 end - attribute \src "libresoc.v:155360.15-155360.57" - process $proc$libresoc.v:155360$8149 + attribute \src "libresoc.v:156668.15-156668.57" + process $proc$libresoc.v:156668$8133 assign { } { } assign $1\o[128:0] 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[128:0] end - attribute \src "libresoc.v:155374.7-155374.20" - process $proc$libresoc.v:155374$8150 + attribute \src "libresoc.v:156682.7-156682.20" + process $proc$libresoc.v:156682$8134 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:155385.7-155385.25" - process $proc$libresoc.v:155385$8151 + attribute \src "libresoc.v:156693.7-156693.25" + process $proc$libresoc.v:156693$8135 assign { } { } - assign $0\xer_so$14[0:0]$8152 1'0 + assign $0\xer_so$14[0:0]$8136 1'0 sync always sync init - update \xer_so$14 $0\xer_so$14[0:0]$8152 + update \xer_so$14 $0\xer_so$14[0:0]$8136 end - attribute \src "libresoc.v:155391.3-155392.43" - process $proc$libresoc.v:155391$8034 + attribute \src "libresoc.v:156699.3-156700.43" + process $proc$libresoc.v:156699$8018 assign { } { } - assign $0\neg_res32$16[0:0]$8035 \neg_res32$16$next + assign $0\neg_res32$16[0:0]$8019 \neg_res32$16$next sync posedge \coresync_clk - update \neg_res32$16 $0\neg_res32$16[0:0]$8035 + update \neg_res32$16 $0\neg_res32$16[0:0]$8019 end - attribute \src "libresoc.v:155393.3-155394.39" - process $proc$libresoc.v:155393$8036 + attribute \src "libresoc.v:156701.3-156702.39" + process $proc$libresoc.v:156701$8020 assign { } { } - assign $0\neg_res$15[0:0]$8037 \neg_res$15$next + assign $0\neg_res$15[0:0]$8021 \neg_res$15$next sync posedge \coresync_clk - update \neg_res$15 $0\neg_res$15[0:0]$8037 + update \neg_res$15 $0\neg_res$15[0:0]$8021 end - attribute \src "libresoc.v:155395.3-155396.37" - process $proc$libresoc.v:155395$8038 + attribute \src "libresoc.v:156703.3-156704.37" + process $proc$libresoc.v:156703$8022 assign { } { } - assign $0\xer_so$14[0:0]$8039 \xer_so$14$next + assign $0\xer_so$14[0:0]$8023 \xer_so$14$next sync posedge \coresync_clk - update \xer_so$14 $0\xer_so$14[0:0]$8039 + update \xer_so$14 $0\xer_so$14[0:0]$8023 end - attribute \src "libresoc.v:155397.3-155398.19" - process $proc$libresoc.v:155397$8040 + attribute \src "libresoc.v:156705.3-156706.19" + process $proc$libresoc.v:156705$8024 assign { } { } assign $0\o[128:0] \o$next sync posedge \coresync_clk update \o $0\o[128:0] end - attribute \src "libresoc.v:155399.3-155400.57" - process $proc$libresoc.v:155399$8041 + attribute \src "libresoc.v:156707.3-156708.57" + process $proc$libresoc.v:156707$8025 assign { } { } - assign $0\mul_op__insn_type$2[6:0]$8042 \mul_op__insn_type$2$next + assign $0\mul_op__insn_type$2[6:0]$8026 \mul_op__insn_type$2$next sync posedge \coresync_clk - update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8042 + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8026 end - attribute \src "libresoc.v:155401.3-155402.53" - process $proc$libresoc.v:155401$8043 + attribute \src "libresoc.v:156709.3-156710.53" + process $proc$libresoc.v:156709$8027 assign { } { } - assign $0\mul_op__fn_unit$3[13:0]$8044 \mul_op__fn_unit$3$next + assign $0\mul_op__fn_unit$3[13:0]$8028 \mul_op__fn_unit$3$next sync posedge \coresync_clk - update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8044 + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8028 end - attribute \src "libresoc.v:155403.3-155404.67" - process $proc$libresoc.v:155403$8045 + attribute \src "libresoc.v:156711.3-156712.67" + process $proc$libresoc.v:156711$8029 assign { } { } - assign $0\mul_op__imm_data__data$4[63:0]$8046 \mul_op__imm_data__data$4$next + assign $0\mul_op__imm_data__data$4[63:0]$8030 \mul_op__imm_data__data$4$next sync posedge \coresync_clk - update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8046 + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8030 end - attribute \src "libresoc.v:155405.3-155406.63" - process $proc$libresoc.v:155405$8047 + attribute \src "libresoc.v:156713.3-156714.63" + process $proc$libresoc.v:156713$8031 assign { } { } - assign $0\mul_op__imm_data__ok$5[0:0]$8048 \mul_op__imm_data__ok$5$next + assign $0\mul_op__imm_data__ok$5[0:0]$8032 \mul_op__imm_data__ok$5$next sync posedge \coresync_clk - update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8048 + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8032 end - attribute \src "libresoc.v:155407.3-155408.51" - process $proc$libresoc.v:155407$8049 + attribute \src "libresoc.v:156715.3-156716.51" + process $proc$libresoc.v:156715$8033 assign { } { } - assign $0\mul_op__rc__rc$6[0:0]$8050 \mul_op__rc__rc$6$next + assign $0\mul_op__rc__rc$6[0:0]$8034 \mul_op__rc__rc$6$next sync posedge \coresync_clk - update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8050 + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8034 end - attribute \src "libresoc.v:155409.3-155410.51" - process $proc$libresoc.v:155409$8051 + attribute \src "libresoc.v:156717.3-156718.51" + process $proc$libresoc.v:156717$8035 assign { } { } - assign $0\mul_op__rc__ok$7[0:0]$8052 \mul_op__rc__ok$7$next + assign $0\mul_op__rc__ok$7[0:0]$8036 \mul_op__rc__ok$7$next sync posedge \coresync_clk - update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8052 + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8036 end - attribute \src "libresoc.v:155411.3-155412.51" - process $proc$libresoc.v:155411$8053 + attribute \src "libresoc.v:156719.3-156720.51" + process $proc$libresoc.v:156719$8037 assign { } { } - assign $0\mul_op__oe__oe$8[0:0]$8054 \mul_op__oe__oe$8$next + assign $0\mul_op__oe__oe$8[0:0]$8038 \mul_op__oe__oe$8$next sync posedge \coresync_clk - update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8054 + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8038 end - attribute \src "libresoc.v:155413.3-155414.51" - process $proc$libresoc.v:155413$8055 + attribute \src "libresoc.v:156721.3-156722.51" + process $proc$libresoc.v:156721$8039 assign { } { } - assign $0\mul_op__oe__ok$9[0:0]$8056 \mul_op__oe__ok$9$next + assign $0\mul_op__oe__ok$9[0:0]$8040 \mul_op__oe__ok$9$next sync posedge \coresync_clk - update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8056 + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8040 end - attribute \src "libresoc.v:155415.3-155416.59" - process $proc$libresoc.v:155415$8057 + attribute \src "libresoc.v:156723.3-156724.59" + process $proc$libresoc.v:156723$8041 assign { } { } - assign $0\mul_op__write_cr0$10[0:0]$8058 \mul_op__write_cr0$10$next + assign $0\mul_op__write_cr0$10[0:0]$8042 \mul_op__write_cr0$10$next sync posedge \coresync_clk - update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8058 + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8042 end - attribute \src "libresoc.v:155417.3-155418.57" - process $proc$libresoc.v:155417$8059 + attribute \src "libresoc.v:156725.3-156726.57" + process $proc$libresoc.v:156725$8043 assign { } { } - assign $0\mul_op__is_32bit$11[0:0]$8060 \mul_op__is_32bit$11$next + assign $0\mul_op__is_32bit$11[0:0]$8044 \mul_op__is_32bit$11$next sync posedge \coresync_clk - update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8060 + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8044 end - attribute \src "libresoc.v:155419.3-155420.59" - process $proc$libresoc.v:155419$8061 + attribute \src "libresoc.v:156727.3-156728.59" + process $proc$libresoc.v:156727$8045 assign { } { } - assign $0\mul_op__is_signed$12[0:0]$8062 \mul_op__is_signed$12$next + assign $0\mul_op__is_signed$12[0:0]$8046 \mul_op__is_signed$12$next sync posedge \coresync_clk - update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8062 + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8046 end - attribute \src "libresoc.v:155421.3-155422.49" - process $proc$libresoc.v:155421$8063 + attribute \src "libresoc.v:156729.3-156730.49" + process $proc$libresoc.v:156729$8047 assign { } { } - assign $0\mul_op__insn$13[31:0]$8064 \mul_op__insn$13$next + assign $0\mul_op__insn$13[31:0]$8048 \mul_op__insn$13$next sync posedge \coresync_clk - update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8064 + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8048 end - attribute \src "libresoc.v:155423.3-155424.33" - process $proc$libresoc.v:155423$8065 + attribute \src "libresoc.v:156731.3-156732.33" + process $proc$libresoc.v:156731$8049 assign { } { } - assign $0\muxid$1[1:0]$8066 \muxid$1$next + assign $0\muxid$1[1:0]$8050 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8066 + update \muxid$1 $0\muxid$1[1:0]$8050 end - attribute \src "libresoc.v:155425.3-155426.29" - process $proc$libresoc.v:155425$8067 + attribute \src "libresoc.v:156733.3-156734.29" + process $proc$libresoc.v:156733$8051 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:155472.3-155489.6" - process $proc$libresoc.v:155472$8068 + attribute \src "libresoc.v:156780.3-156797.6" + process $proc$libresoc.v:156780$8052 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$8069 $2\r_busy$next[0:0]$8071 - attribute \src "libresoc.v:155473.5-155473.29" + assign $0\r_busy$next[0:0]$8053 $2\r_busy$next[0:0]$8055 + attribute \src "libresoc.v:156781.5-156781.29" switch \initial - attribute \src "libresoc.v:155473.9-155473.17" + attribute \src "libresoc.v:156781.9-156781.17" case 1'1 case end @@ -320677,34 +292047,34 @@ module \mul_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$8070 1'1 + assign $1\r_busy$next[0:0]$8054 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$8070 1'0 + assign $1\r_busy$next[0:0]$8054 1'0 case - assign $1\r_busy$next[0:0]$8070 \r_busy + assign $1\r_busy$next[0:0]$8054 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$8071 1'0 + assign $2\r_busy$next[0:0]$8055 1'0 case - assign $2\r_busy$next[0:0]$8071 $1\r_busy$next[0:0]$8070 + assign $2\r_busy$next[0:0]$8055 $1\r_busy$next[0:0]$8054 end sync always - update \r_busy$next $0\r_busy$next[0:0]$8069 + update \r_busy$next $0\r_busy$next[0:0]$8053 end - attribute \src "libresoc.v:155490.3-155502.6" - process $proc$libresoc.v:155490$8072 + attribute \src "libresoc.v:156798.3-156810.6" + process $proc$libresoc.v:156798$8056 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$8073 $1\muxid$1$next[1:0]$8074 - attribute \src "libresoc.v:155491.5-155491.29" + assign $0\muxid$1$next[1:0]$8057 $1\muxid$1$next[1:0]$8058 + attribute \src "libresoc.v:156799.5-156799.29" switch \initial - attribute \src "libresoc.v:155491.9-155491.17" + attribute \src "libresoc.v:156799.9-156799.17" case 1'1 case end @@ -320713,19 +292083,19 @@ module \mul_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$8074 \muxid$36 + assign $1\muxid$1$next[1:0]$8058 \muxid$36 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$8074 \muxid$36 + assign $1\muxid$1$next[1:0]$8058 \muxid$36 case - assign $1\muxid$1$next[1:0]$8074 \muxid$1 + assign $1\muxid$1$next[1:0]$8058 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8073 + update \muxid$1$next $0\muxid$1$next[1:0]$8057 end - attribute \src "libresoc.v:155503.3-155538.6" - process $proc$libresoc.v:155503$8075 + attribute \src "libresoc.v:156811.3-156846.6" + process $proc$libresoc.v:156811$8059 assign { } { } assign { } { } assign { } { } @@ -320750,27 +292120,27 @@ module \mul_pipe2 assign { } { } assign { } { } assign { } { } - assign $0\mul_op__fn_unit$3$next[13:0]$8076 $1\mul_op__fn_unit$3$next[13:0]$8088 + assign $0\mul_op__fn_unit$3$next[13:0]$8060 $1\mul_op__fn_unit$3$next[13:0]$8072 assign { } { } assign { } { } - assign $0\mul_op__insn$13$next[31:0]$8079 $1\mul_op__insn$13$next[31:0]$8091 - assign $0\mul_op__insn_type$2$next[6:0]$8080 $1\mul_op__insn_type$2$next[6:0]$8092 - assign $0\mul_op__is_32bit$11$next[0:0]$8081 $1\mul_op__is_32bit$11$next[0:0]$8093 - assign $0\mul_op__is_signed$12$next[0:0]$8082 $1\mul_op__is_signed$12$next[0:0]$8094 + assign $0\mul_op__insn$13$next[31:0]$8063 $1\mul_op__insn$13$next[31:0]$8075 + assign $0\mul_op__insn_type$2$next[6:0]$8064 $1\mul_op__insn_type$2$next[6:0]$8076 + assign $0\mul_op__is_32bit$11$next[0:0]$8065 $1\mul_op__is_32bit$11$next[0:0]$8077 + assign $0\mul_op__is_signed$12$next[0:0]$8066 $1\mul_op__is_signed$12$next[0:0]$8078 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\mul_op__write_cr0$10$next[0:0]$8087 $1\mul_op__write_cr0$10$next[0:0]$8099 - assign $0\mul_op__imm_data__data$4$next[63:0]$8077 $2\mul_op__imm_data__data$4$next[63:0]$8100 - assign $0\mul_op__imm_data__ok$5$next[0:0]$8078 $2\mul_op__imm_data__ok$5$next[0:0]$8101 - assign $0\mul_op__oe__oe$8$next[0:0]$8083 $2\mul_op__oe__oe$8$next[0:0]$8102 - assign $0\mul_op__oe__ok$9$next[0:0]$8084 $2\mul_op__oe__ok$9$next[0:0]$8103 - assign $0\mul_op__rc__ok$7$next[0:0]$8085 $2\mul_op__rc__ok$7$next[0:0]$8104 - assign $0\mul_op__rc__rc$6$next[0:0]$8086 $2\mul_op__rc__rc$6$next[0:0]$8105 - attribute \src "libresoc.v:155504.5-155504.29" + assign $0\mul_op__write_cr0$10$next[0:0]$8071 $1\mul_op__write_cr0$10$next[0:0]$8083 + assign $0\mul_op__imm_data__data$4$next[63:0]$8061 $2\mul_op__imm_data__data$4$next[63:0]$8084 + assign $0\mul_op__imm_data__ok$5$next[0:0]$8062 $2\mul_op__imm_data__ok$5$next[0:0]$8085 + assign $0\mul_op__oe__oe$8$next[0:0]$8067 $2\mul_op__oe__oe$8$next[0:0]$8086 + assign $0\mul_op__oe__ok$9$next[0:0]$8068 $2\mul_op__oe__ok$9$next[0:0]$8087 + assign $0\mul_op__rc__ok$7$next[0:0]$8069 $2\mul_op__rc__ok$7$next[0:0]$8088 + assign $0\mul_op__rc__rc$6$next[0:0]$8070 $2\mul_op__rc__rc$6$next[0:0]$8089 + attribute \src "libresoc.v:156812.5-156812.29" switch \initial - attribute \src "libresoc.v:155504.9-155504.17" + attribute \src "libresoc.v:156812.9-156812.17" case 1'1 case end @@ -320790,7 +292160,7 @@ module \mul_pipe2 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$13$next[31:0]$8091 $1\mul_op__is_signed$12$next[0:0]$8094 $1\mul_op__is_32bit$11$next[0:0]$8093 $1\mul_op__write_cr0$10$next[0:0]$8099 $1\mul_op__oe__ok$9$next[0:0]$8096 $1\mul_op__oe__oe$8$next[0:0]$8095 $1\mul_op__rc__ok$7$next[0:0]$8097 $1\mul_op__rc__rc$6$next[0:0]$8098 $1\mul_op__imm_data__ok$5$next[0:0]$8090 $1\mul_op__imm_data__data$4$next[63:0]$8089 $1\mul_op__fn_unit$3$next[13:0]$8088 $1\mul_op__insn_type$2$next[6:0]$8092 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } + assign { $1\mul_op__insn$13$next[31:0]$8075 $1\mul_op__is_signed$12$next[0:0]$8078 $1\mul_op__is_32bit$11$next[0:0]$8077 $1\mul_op__write_cr0$10$next[0:0]$8083 $1\mul_op__oe__ok$9$next[0:0]$8080 $1\mul_op__oe__oe$8$next[0:0]$8079 $1\mul_op__rc__ok$7$next[0:0]$8081 $1\mul_op__rc__rc$6$next[0:0]$8082 $1\mul_op__imm_data__ok$5$next[0:0]$8074 $1\mul_op__imm_data__data$4$next[63:0]$8073 $1\mul_op__fn_unit$3$next[13:0]$8072 $1\mul_op__insn_type$2$next[6:0]$8076 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -320805,20 +292175,20 @@ module \mul_pipe2 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$13$next[31:0]$8091 $1\mul_op__is_signed$12$next[0:0]$8094 $1\mul_op__is_32bit$11$next[0:0]$8093 $1\mul_op__write_cr0$10$next[0:0]$8099 $1\mul_op__oe__ok$9$next[0:0]$8096 $1\mul_op__oe__oe$8$next[0:0]$8095 $1\mul_op__rc__ok$7$next[0:0]$8097 $1\mul_op__rc__rc$6$next[0:0]$8098 $1\mul_op__imm_data__ok$5$next[0:0]$8090 $1\mul_op__imm_data__data$4$next[63:0]$8089 $1\mul_op__fn_unit$3$next[13:0]$8088 $1\mul_op__insn_type$2$next[6:0]$8092 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } + assign { $1\mul_op__insn$13$next[31:0]$8075 $1\mul_op__is_signed$12$next[0:0]$8078 $1\mul_op__is_32bit$11$next[0:0]$8077 $1\mul_op__write_cr0$10$next[0:0]$8083 $1\mul_op__oe__ok$9$next[0:0]$8080 $1\mul_op__oe__oe$8$next[0:0]$8079 $1\mul_op__rc__ok$7$next[0:0]$8081 $1\mul_op__rc__rc$6$next[0:0]$8082 $1\mul_op__imm_data__ok$5$next[0:0]$8074 $1\mul_op__imm_data__data$4$next[63:0]$8073 $1\mul_op__fn_unit$3$next[13:0]$8072 $1\mul_op__insn_type$2$next[6:0]$8076 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } case - assign $1\mul_op__fn_unit$3$next[13:0]$8088 \mul_op__fn_unit$3 - assign $1\mul_op__imm_data__data$4$next[63:0]$8089 \mul_op__imm_data__data$4 - assign $1\mul_op__imm_data__ok$5$next[0:0]$8090 \mul_op__imm_data__ok$5 - assign $1\mul_op__insn$13$next[31:0]$8091 \mul_op__insn$13 - assign $1\mul_op__insn_type$2$next[6:0]$8092 \mul_op__insn_type$2 - assign $1\mul_op__is_32bit$11$next[0:0]$8093 \mul_op__is_32bit$11 - assign $1\mul_op__is_signed$12$next[0:0]$8094 \mul_op__is_signed$12 - assign $1\mul_op__oe__oe$8$next[0:0]$8095 \mul_op__oe__oe$8 - assign $1\mul_op__oe__ok$9$next[0:0]$8096 \mul_op__oe__ok$9 - assign $1\mul_op__rc__ok$7$next[0:0]$8097 \mul_op__rc__ok$7 - assign $1\mul_op__rc__rc$6$next[0:0]$8098 \mul_op__rc__rc$6 - assign $1\mul_op__write_cr0$10$next[0:0]$8099 \mul_op__write_cr0$10 + assign $1\mul_op__fn_unit$3$next[13:0]$8072 \mul_op__fn_unit$3 + assign $1\mul_op__imm_data__data$4$next[63:0]$8073 \mul_op__imm_data__data$4 + assign $1\mul_op__imm_data__ok$5$next[0:0]$8074 \mul_op__imm_data__ok$5 + assign $1\mul_op__insn$13$next[31:0]$8075 \mul_op__insn$13 + assign $1\mul_op__insn_type$2$next[6:0]$8076 \mul_op__insn_type$2 + assign $1\mul_op__is_32bit$11$next[0:0]$8077 \mul_op__is_32bit$11 + assign $1\mul_op__is_signed$12$next[0:0]$8078 \mul_op__is_signed$12 + assign $1\mul_op__oe__oe$8$next[0:0]$8079 \mul_op__oe__oe$8 + assign $1\mul_op__oe__ok$9$next[0:0]$8080 \mul_op__oe__ok$9 + assign $1\mul_op__rc__ok$7$next[0:0]$8081 \mul_op__rc__ok$7 + assign $1\mul_op__rc__rc$6$next[0:0]$8082 \mul_op__rc__rc$6 + assign $1\mul_op__write_cr0$10$next[0:0]$8083 \mul_op__write_cr0$10 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -320830,42 +292200,42 @@ module \mul_pipe2 assign { } { } assign { } { } assign { } { } - assign $2\mul_op__imm_data__data$4$next[63:0]$8100 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\mul_op__imm_data__ok$5$next[0:0]$8101 1'0 - assign $2\mul_op__rc__rc$6$next[0:0]$8105 1'0 - assign $2\mul_op__rc__ok$7$next[0:0]$8104 1'0 - assign $2\mul_op__oe__oe$8$next[0:0]$8102 1'0 - assign $2\mul_op__oe__ok$9$next[0:0]$8103 1'0 + assign $2\mul_op__imm_data__data$4$next[63:0]$8084 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\mul_op__imm_data__ok$5$next[0:0]$8085 1'0 + assign $2\mul_op__rc__rc$6$next[0:0]$8089 1'0 + assign $2\mul_op__rc__ok$7$next[0:0]$8088 1'0 + assign $2\mul_op__oe__oe$8$next[0:0]$8086 1'0 + assign $2\mul_op__oe__ok$9$next[0:0]$8087 1'0 case - assign $2\mul_op__imm_data__data$4$next[63:0]$8100 $1\mul_op__imm_data__data$4$next[63:0]$8089 - assign $2\mul_op__imm_data__ok$5$next[0:0]$8101 $1\mul_op__imm_data__ok$5$next[0:0]$8090 - assign $2\mul_op__oe__oe$8$next[0:0]$8102 $1\mul_op__oe__oe$8$next[0:0]$8095 - assign $2\mul_op__oe__ok$9$next[0:0]$8103 $1\mul_op__oe__ok$9$next[0:0]$8096 - assign $2\mul_op__rc__ok$7$next[0:0]$8104 $1\mul_op__rc__ok$7$next[0:0]$8097 - assign $2\mul_op__rc__rc$6$next[0:0]$8105 $1\mul_op__rc__rc$6$next[0:0]$8098 + assign $2\mul_op__imm_data__data$4$next[63:0]$8084 $1\mul_op__imm_data__data$4$next[63:0]$8073 + assign $2\mul_op__imm_data__ok$5$next[0:0]$8085 $1\mul_op__imm_data__ok$5$next[0:0]$8074 + assign $2\mul_op__oe__oe$8$next[0:0]$8086 $1\mul_op__oe__oe$8$next[0:0]$8079 + assign $2\mul_op__oe__ok$9$next[0:0]$8087 $1\mul_op__oe__ok$9$next[0:0]$8080 + assign $2\mul_op__rc__ok$7$next[0:0]$8088 $1\mul_op__rc__ok$7$next[0:0]$8081 + assign $2\mul_op__rc__rc$6$next[0:0]$8089 $1\mul_op__rc__rc$6$next[0:0]$8082 end sync always - update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[13:0]$8076 - update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$8077 - update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$8078 - update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$8079 - update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$8080 - update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$8081 - update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$8082 - update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$8083 - update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$8084 - update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$8085 - update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$8086 - update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$8087 + update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[13:0]$8060 + update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$8061 + update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$8062 + update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$8063 + update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$8064 + update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$8065 + update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$8066 + update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$8067 + update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$8068 + update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$8069 + update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$8070 + update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$8071 end - attribute \src "libresoc.v:155539.3-155551.6" - process $proc$libresoc.v:155539$8106 + attribute \src "libresoc.v:156847.3-156859.6" + process $proc$libresoc.v:156847$8090 assign { } { } assign { } { } - assign $0\o$next[128:0]$8107 $1\o$next[128:0]$8108 - attribute \src "libresoc.v:155540.5-155540.29" + assign $0\o$next[128:0]$8091 $1\o$next[128:0]$8092 + attribute \src "libresoc.v:156848.5-156848.29" switch \initial - attribute \src "libresoc.v:155540.9-155540.17" + attribute \src "libresoc.v:156848.9-156848.17" case 1'1 case end @@ -320874,25 +292244,25 @@ module \mul_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\o$next[128:0]$8108 \o$49 + assign $1\o$next[128:0]$8092 \o$49 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\o$next[128:0]$8108 \o$49 + assign $1\o$next[128:0]$8092 \o$49 case - assign $1\o$next[128:0]$8108 \o + assign $1\o$next[128:0]$8092 \o end sync always - update \o$next $0\o$next[128:0]$8107 + update \o$next $0\o$next[128:0]$8091 end - attribute \src "libresoc.v:155552.3-155564.6" - process $proc$libresoc.v:155552$8109 + attribute \src "libresoc.v:156860.3-156872.6" + process $proc$libresoc.v:156860$8093 assign { } { } assign { } { } - assign $0\xer_so$14$next[0:0]$8110 $1\xer_so$14$next[0:0]$8111 - attribute \src "libresoc.v:155553.5-155553.29" + assign $0\xer_so$14$next[0:0]$8094 $1\xer_so$14$next[0:0]$8095 + attribute \src "libresoc.v:156861.5-156861.29" switch \initial - attribute \src "libresoc.v:155553.9-155553.17" + attribute \src "libresoc.v:156861.9-156861.17" case 1'1 case end @@ -320901,25 +292271,25 @@ module \mul_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\xer_so$14$next[0:0]$8111 \xer_so$50 + assign $1\xer_so$14$next[0:0]$8095 \xer_so$50 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\xer_so$14$next[0:0]$8111 \xer_so$50 + assign $1\xer_so$14$next[0:0]$8095 \xer_so$50 case - assign $1\xer_so$14$next[0:0]$8111 \xer_so$14 + assign $1\xer_so$14$next[0:0]$8095 \xer_so$14 end sync always - update \xer_so$14$next $0\xer_so$14$next[0:0]$8110 + update \xer_so$14$next $0\xer_so$14$next[0:0]$8094 end - attribute \src "libresoc.v:155565.3-155577.6" - process $proc$libresoc.v:155565$8112 + attribute \src "libresoc.v:156873.3-156885.6" + process $proc$libresoc.v:156873$8096 assign { } { } assign { } { } - assign $0\neg_res$15$next[0:0]$8113 $1\neg_res$15$next[0:0]$8114 - attribute \src "libresoc.v:155566.5-155566.29" + assign $0\neg_res$15$next[0:0]$8097 $1\neg_res$15$next[0:0]$8098 + attribute \src "libresoc.v:156874.5-156874.29" switch \initial - attribute \src "libresoc.v:155566.9-155566.17" + attribute \src "libresoc.v:156874.9-156874.17" case 1'1 case end @@ -320928,25 +292298,25 @@ module \mul_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\neg_res$15$next[0:0]$8114 \neg_res$51 + assign $1\neg_res$15$next[0:0]$8098 \neg_res$51 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\neg_res$15$next[0:0]$8114 \neg_res$51 + assign $1\neg_res$15$next[0:0]$8098 \neg_res$51 case - assign $1\neg_res$15$next[0:0]$8114 \neg_res$15 + assign $1\neg_res$15$next[0:0]$8098 \neg_res$15 end sync always - update \neg_res$15$next $0\neg_res$15$next[0:0]$8113 + update \neg_res$15$next $0\neg_res$15$next[0:0]$8097 end - attribute \src "libresoc.v:155578.3-155590.6" - process $proc$libresoc.v:155578$8115 + attribute \src "libresoc.v:156886.3-156898.6" + process $proc$libresoc.v:156886$8099 assign { } { } assign { } { } - assign $0\neg_res32$16$next[0:0]$8116 $1\neg_res32$16$next[0:0]$8117 - attribute \src "libresoc.v:155579.5-155579.29" + assign $0\neg_res32$16$next[0:0]$8100 $1\neg_res32$16$next[0:0]$8101 + attribute \src "libresoc.v:156887.5-156887.29" switch \initial - attribute \src "libresoc.v:155579.9-155579.17" + attribute \src "libresoc.v:156887.9-156887.17" case 1'1 case end @@ -320955,18 +292325,18 @@ module \mul_pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\neg_res32$16$next[0:0]$8117 \neg_res32$52 + assign $1\neg_res32$16$next[0:0]$8101 \neg_res32$52 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\neg_res32$16$next[0:0]$8117 \neg_res32$52 + assign $1\neg_res32$16$next[0:0]$8101 \neg_res32$52 case - assign $1\neg_res32$16$next[0:0]$8117 \neg_res32$16 + assign $1\neg_res32$16$next[0:0]$8101 \neg_res32$16 end sync always - update \neg_res32$16$next $0\neg_res32$16$next[0:0]$8116 + update \neg_res32$16$next $0\neg_res32$16$next[0:0]$8100 end - connect \$34 $and$libresoc.v:155390$8033_Y + connect \$34 $and$libresoc.v:156698$8017_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect \neg_res32$52 \mul2_neg_res32$32 @@ -320986,218 +292356,218 @@ module \mul_pipe2 connect { \mul2_mul_op__insn \mul2_mul_op__is_signed \mul2_mul_op__is_32bit \mul2_mul_op__write_cr0 \mul2_mul_op__oe__ok \mul2_mul_op__oe__oe \mul2_mul_op__rc__ok \mul2_mul_op__rc__rc \mul2_mul_op__imm_data__ok \mul2_mul_op__imm_data__data \mul2_mul_op__fn_unit \mul2_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \mul2_muxid \muxid end -attribute \src "libresoc.v:155613.1-156909.10" +attribute \src "libresoc.v:156921.1-158217.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3" attribute \generator "nMigen" module \mul_pipe3 - attribute \src "libresoc.v:156827.3-156845.6" - wire width 4 $0\cr_a$next[3:0]$8236 - attribute \src "libresoc.v:156619.3-156620.25" + attribute \src "libresoc.v:158135.3-158153.6" + wire width 4 $0\cr_a$next[3:0]$8220 + attribute \src "libresoc.v:157927.3-157928.25" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:156827.3-156845.6" - wire $0\cr_a_ok$next[0:0]$8237 - attribute \src "libresoc.v:156621.3-156622.31" + attribute \src "libresoc.v:158135.3-158153.6" + wire $0\cr_a_ok$next[0:0]$8221 + attribute \src "libresoc.v:157929.3-157930.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:155614.7-155614.20" + attribute \src "libresoc.v:156922.7-156922.20" wire $0\initial[0:0] - attribute \src "libresoc.v:156772.3-156807.6" - wire width 14 $0\mul_op__fn_unit$3$next[13:0]$8199 - attribute \src "libresoc.v:156629.3-156630.53" - wire width 14 $0\mul_op__fn_unit$3[13:0]$8167 - attribute \src "libresoc.v:155925.14-155925.44" - wire width 14 $0\mul_op__fn_unit$3[13:0]$8257 - attribute \src "libresoc.v:156772.3-156807.6" - wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$8200 - attribute \src "libresoc.v:156631.3-156632.67" - wire width 64 $0\mul_op__imm_data__data$4[63:0]$8169 - attribute \src "libresoc.v:155949.14-155949.63" - wire width 64 $0\mul_op__imm_data__data$4[63:0]$8259 - attribute \src "libresoc.v:156772.3-156807.6" - wire $0\mul_op__imm_data__ok$5$next[0:0]$8201 - attribute \src "libresoc.v:156633.3-156634.63" - wire $0\mul_op__imm_data__ok$5[0:0]$8171 - attribute \src "libresoc.v:155958.7-155958.38" - wire $0\mul_op__imm_data__ok$5[0:0]$8261 - attribute \src "libresoc.v:156772.3-156807.6" - wire width 32 $0\mul_op__insn$13$next[31:0]$8202 - attribute \src "libresoc.v:156649.3-156650.49" - wire width 32 $0\mul_op__insn$13[31:0]$8187 - attribute \src "libresoc.v:155967.14-155967.39" - wire width 32 $0\mul_op__insn$13[31:0]$8263 - attribute \src "libresoc.v:156772.3-156807.6" - wire width 7 $0\mul_op__insn_type$2$next[6:0]$8203 - attribute \src "libresoc.v:156627.3-156628.57" - wire width 7 $0\mul_op__insn_type$2[6:0]$8165 - attribute \src "libresoc.v:156126.13-156126.42" - wire width 7 $0\mul_op__insn_type$2[6:0]$8265 - attribute \src "libresoc.v:156772.3-156807.6" - wire $0\mul_op__is_32bit$11$next[0:0]$8204 - attribute \src "libresoc.v:156645.3-156646.57" - wire $0\mul_op__is_32bit$11[0:0]$8183 - attribute \src "libresoc.v:156210.7-156210.35" - wire $0\mul_op__is_32bit$11[0:0]$8267 - attribute \src "libresoc.v:156772.3-156807.6" - wire $0\mul_op__is_signed$12$next[0:0]$8205 - attribute \src "libresoc.v:156647.3-156648.59" - wire $0\mul_op__is_signed$12[0:0]$8185 - attribute \src "libresoc.v:156219.7-156219.36" - wire $0\mul_op__is_signed$12[0:0]$8269 - attribute \src "libresoc.v:156772.3-156807.6" - wire $0\mul_op__oe__oe$8$next[0:0]$8206 - attribute \src "libresoc.v:156639.3-156640.51" - wire $0\mul_op__oe__oe$8[0:0]$8177 - attribute \src "libresoc.v:156230.7-156230.32" - wire $0\mul_op__oe__oe$8[0:0]$8271 - attribute \src "libresoc.v:156772.3-156807.6" - wire $0\mul_op__oe__ok$9$next[0:0]$8207 - attribute \src "libresoc.v:156641.3-156642.51" - wire $0\mul_op__oe__ok$9[0:0]$8179 - attribute \src "libresoc.v:156239.7-156239.32" - wire $0\mul_op__oe__ok$9[0:0]$8273 - attribute \src "libresoc.v:156772.3-156807.6" - wire $0\mul_op__rc__ok$7$next[0:0]$8208 - attribute \src "libresoc.v:156637.3-156638.51" - wire $0\mul_op__rc__ok$7[0:0]$8175 - attribute \src "libresoc.v:156248.7-156248.32" - wire $0\mul_op__rc__ok$7[0:0]$8275 - attribute \src "libresoc.v:156772.3-156807.6" - wire $0\mul_op__rc__rc$6$next[0:0]$8209 - attribute \src "libresoc.v:156635.3-156636.51" - wire $0\mul_op__rc__rc$6[0:0]$8173 - attribute \src "libresoc.v:156255.7-156255.32" - wire $0\mul_op__rc__rc$6[0:0]$8277 - attribute \src "libresoc.v:156772.3-156807.6" - wire $0\mul_op__write_cr0$10$next[0:0]$8210 - attribute \src "libresoc.v:156643.3-156644.59" - wire $0\mul_op__write_cr0$10[0:0]$8181 - attribute \src "libresoc.v:156264.7-156264.36" - wire $0\mul_op__write_cr0$10[0:0]$8279 - attribute \src "libresoc.v:156759.3-156771.6" - wire width 2 $0\muxid$1$next[1:0]$8196 - attribute \src "libresoc.v:156651.3-156652.33" - wire width 2 $0\muxid$1[1:0]$8189 - attribute \src "libresoc.v:156273.13-156273.29" - wire width 2 $0\muxid$1[1:0]$8281 - attribute \src "libresoc.v:156808.3-156826.6" - wire width 64 $0\o$14$next[63:0]$8231 - attribute \src "libresoc.v:156623.3-156624.27" - wire width 64 $0\o$14[63:0]$8162 - attribute \src "libresoc.v:156294.14-156294.43" - wire width 64 $0\o$14[63:0]$8283 - attribute \src "libresoc.v:156808.3-156826.6" - wire $0\o_ok$next[0:0]$8230 - attribute \src "libresoc.v:156625.3-156626.25" + attribute \src "libresoc.v:158080.3-158115.6" + wire width 14 $0\mul_op__fn_unit$3$next[13:0]$8183 + attribute \src "libresoc.v:157937.3-157938.53" + wire width 14 $0\mul_op__fn_unit$3[13:0]$8151 + attribute \src "libresoc.v:157233.14-157233.44" + wire width 14 $0\mul_op__fn_unit$3[13:0]$8241 + attribute \src "libresoc.v:158080.3-158115.6" + wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$8184 + attribute \src "libresoc.v:157939.3-157940.67" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$8153 + attribute \src "libresoc.v:157257.14-157257.63" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$8243 + attribute \src "libresoc.v:158080.3-158115.6" + wire $0\mul_op__imm_data__ok$5$next[0:0]$8185 + attribute \src "libresoc.v:157941.3-157942.63" + wire $0\mul_op__imm_data__ok$5[0:0]$8155 + attribute \src "libresoc.v:157266.7-157266.38" + wire $0\mul_op__imm_data__ok$5[0:0]$8245 + attribute \src "libresoc.v:158080.3-158115.6" + wire width 32 $0\mul_op__insn$13$next[31:0]$8186 + attribute \src "libresoc.v:157957.3-157958.49" + wire width 32 $0\mul_op__insn$13[31:0]$8171 + attribute \src "libresoc.v:157275.14-157275.39" + wire width 32 $0\mul_op__insn$13[31:0]$8247 + attribute \src "libresoc.v:158080.3-158115.6" + wire width 7 $0\mul_op__insn_type$2$next[6:0]$8187 + attribute \src "libresoc.v:157935.3-157936.57" + wire width 7 $0\mul_op__insn_type$2[6:0]$8149 + attribute \src "libresoc.v:157434.13-157434.42" + wire width 7 $0\mul_op__insn_type$2[6:0]$8249 + attribute \src "libresoc.v:158080.3-158115.6" + wire $0\mul_op__is_32bit$11$next[0:0]$8188 + attribute \src "libresoc.v:157953.3-157954.57" + wire $0\mul_op__is_32bit$11[0:0]$8167 + attribute \src "libresoc.v:157518.7-157518.35" + wire $0\mul_op__is_32bit$11[0:0]$8251 + attribute \src "libresoc.v:158080.3-158115.6" + wire $0\mul_op__is_signed$12$next[0:0]$8189 + attribute \src "libresoc.v:157955.3-157956.59" + wire $0\mul_op__is_signed$12[0:0]$8169 + attribute \src "libresoc.v:157527.7-157527.36" + wire $0\mul_op__is_signed$12[0:0]$8253 + attribute \src "libresoc.v:158080.3-158115.6" + wire $0\mul_op__oe__oe$8$next[0:0]$8190 + attribute \src "libresoc.v:157947.3-157948.51" + wire $0\mul_op__oe__oe$8[0:0]$8161 + attribute \src "libresoc.v:157538.7-157538.32" + wire $0\mul_op__oe__oe$8[0:0]$8255 + attribute \src "libresoc.v:158080.3-158115.6" + wire $0\mul_op__oe__ok$9$next[0:0]$8191 + attribute \src "libresoc.v:157949.3-157950.51" + wire $0\mul_op__oe__ok$9[0:0]$8163 + attribute \src "libresoc.v:157547.7-157547.32" + wire $0\mul_op__oe__ok$9[0:0]$8257 + attribute \src "libresoc.v:158080.3-158115.6" + wire $0\mul_op__rc__ok$7$next[0:0]$8192 + attribute \src "libresoc.v:157945.3-157946.51" + wire $0\mul_op__rc__ok$7[0:0]$8159 + attribute \src "libresoc.v:157556.7-157556.32" + wire $0\mul_op__rc__ok$7[0:0]$8259 + attribute \src "libresoc.v:158080.3-158115.6" + wire $0\mul_op__rc__rc$6$next[0:0]$8193 + attribute \src "libresoc.v:157943.3-157944.51" + wire $0\mul_op__rc__rc$6[0:0]$8157 + attribute \src "libresoc.v:157563.7-157563.32" + wire $0\mul_op__rc__rc$6[0:0]$8261 + attribute \src "libresoc.v:158080.3-158115.6" + wire $0\mul_op__write_cr0$10$next[0:0]$8194 + attribute \src "libresoc.v:157951.3-157952.59" + wire $0\mul_op__write_cr0$10[0:0]$8165 + attribute \src "libresoc.v:157572.7-157572.36" + wire $0\mul_op__write_cr0$10[0:0]$8263 + attribute \src "libresoc.v:158067.3-158079.6" + wire width 2 $0\muxid$1$next[1:0]$8180 + attribute \src "libresoc.v:157959.3-157960.33" + wire width 2 $0\muxid$1[1:0]$8173 + attribute \src "libresoc.v:157581.13-157581.29" + wire width 2 $0\muxid$1[1:0]$8265 + attribute \src "libresoc.v:158116.3-158134.6" + wire width 64 $0\o$14$next[63:0]$8215 + attribute \src "libresoc.v:157931.3-157932.27" + wire width 64 $0\o$14[63:0]$8146 + attribute \src "libresoc.v:157602.14-157602.43" + wire width 64 $0\o$14[63:0]$8267 + attribute \src "libresoc.v:158116.3-158134.6" + wire $0\o_ok$next[0:0]$8214 + attribute \src "libresoc.v:157933.3-157934.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:156741.3-156758.6" - wire $0\r_busy$next[0:0]$8192 - attribute \src "libresoc.v:156653.3-156654.29" + attribute \src "libresoc.v:158049.3-158066.6" + wire $0\r_busy$next[0:0]$8176 + attribute \src "libresoc.v:157961.3-157962.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:156846.3-156864.6" - wire width 2 $0\xer_ov$next[1:0]$8242 - attribute \src "libresoc.v:156615.3-156616.29" + attribute \src "libresoc.v:158154.3-158172.6" + wire width 2 $0\xer_ov$next[1:0]$8226 + attribute \src "libresoc.v:157923.3-157924.29" wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:156846.3-156864.6" - wire $0\xer_ov_ok$next[0:0]$8243 - attribute \src "libresoc.v:156617.3-156618.35" + attribute \src "libresoc.v:158154.3-158172.6" + wire $0\xer_ov_ok$next[0:0]$8227 + attribute \src "libresoc.v:157925.3-157926.35" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:156865.3-156883.6" - wire $0\xer_so$15$next[0:0]$8249 - attribute \src "libresoc.v:156611.3-156612.37" - wire $0\xer_so$15[0:0]$8155 - attribute \src "libresoc.v:156596.7-156596.25" - wire $0\xer_so$15[0:0]$8289 - attribute \src "libresoc.v:156865.3-156883.6" - wire $0\xer_so_ok$next[0:0]$8248 - attribute \src "libresoc.v:156613.3-156614.35" + attribute \src "libresoc.v:158173.3-158191.6" + wire $0\xer_so$15$next[0:0]$8233 + attribute \src "libresoc.v:157919.3-157920.37" + wire $0\xer_so$15[0:0]$8139 + attribute \src "libresoc.v:157904.7-157904.25" + wire $0\xer_so$15[0:0]$8273 + attribute \src "libresoc.v:158173.3-158191.6" + wire $0\xer_so_ok$next[0:0]$8232 + attribute \src "libresoc.v:157921.3-157922.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:156827.3-156845.6" - wire width 4 $1\cr_a$next[3:0]$8238 - attribute \src "libresoc.v:155623.13-155623.24" + attribute \src "libresoc.v:158135.3-158153.6" + wire width 4 $1\cr_a$next[3:0]$8222 + attribute \src "libresoc.v:156931.13-156931.24" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:156827.3-156845.6" - wire $1\cr_a_ok$next[0:0]$8239 - attribute \src "libresoc.v:155632.7-155632.21" + attribute \src "libresoc.v:158135.3-158153.6" + wire $1\cr_a_ok$next[0:0]$8223 + attribute \src "libresoc.v:156940.7-156940.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:156772.3-156807.6" - wire width 14 $1\mul_op__fn_unit$3$next[13:0]$8211 - attribute \src "libresoc.v:156772.3-156807.6" - wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$8212 - attribute \src "libresoc.v:156772.3-156807.6" - wire $1\mul_op__imm_data__ok$5$next[0:0]$8213 - attribute \src "libresoc.v:156772.3-156807.6" - wire width 32 $1\mul_op__insn$13$next[31:0]$8214 - attribute \src "libresoc.v:156772.3-156807.6" - wire width 7 $1\mul_op__insn_type$2$next[6:0]$8215 - attribute \src "libresoc.v:156772.3-156807.6" - wire $1\mul_op__is_32bit$11$next[0:0]$8216 - attribute \src "libresoc.v:156772.3-156807.6" - wire $1\mul_op__is_signed$12$next[0:0]$8217 - attribute \src "libresoc.v:156772.3-156807.6" - wire $1\mul_op__oe__oe$8$next[0:0]$8218 - attribute \src "libresoc.v:156772.3-156807.6" - wire $1\mul_op__oe__ok$9$next[0:0]$8219 - attribute \src "libresoc.v:156772.3-156807.6" - wire $1\mul_op__rc__ok$7$next[0:0]$8220 - attribute \src "libresoc.v:156772.3-156807.6" - wire $1\mul_op__rc__rc$6$next[0:0]$8221 - attribute \src "libresoc.v:156772.3-156807.6" - wire $1\mul_op__write_cr0$10$next[0:0]$8222 - attribute \src "libresoc.v:156759.3-156771.6" - wire width 2 $1\muxid$1$next[1:0]$8197 - attribute \src "libresoc.v:156808.3-156826.6" - wire width 64 $1\o$14$next[63:0]$8233 - attribute \src "libresoc.v:156808.3-156826.6" - wire $1\o_ok$next[0:0]$8232 - attribute \src "libresoc.v:156301.7-156301.18" + attribute \src "libresoc.v:158080.3-158115.6" + wire width 14 $1\mul_op__fn_unit$3$next[13:0]$8195 + attribute \src "libresoc.v:158080.3-158115.6" + wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$8196 + attribute \src "libresoc.v:158080.3-158115.6" + wire $1\mul_op__imm_data__ok$5$next[0:0]$8197 + attribute \src "libresoc.v:158080.3-158115.6" + wire width 32 $1\mul_op__insn$13$next[31:0]$8198 + attribute \src "libresoc.v:158080.3-158115.6" + wire width 7 $1\mul_op__insn_type$2$next[6:0]$8199 + attribute \src "libresoc.v:158080.3-158115.6" + wire $1\mul_op__is_32bit$11$next[0:0]$8200 + attribute \src "libresoc.v:158080.3-158115.6" + wire $1\mul_op__is_signed$12$next[0:0]$8201 + attribute \src "libresoc.v:158080.3-158115.6" + wire $1\mul_op__oe__oe$8$next[0:0]$8202 + attribute \src "libresoc.v:158080.3-158115.6" + wire $1\mul_op__oe__ok$9$next[0:0]$8203 + attribute \src "libresoc.v:158080.3-158115.6" + wire $1\mul_op__rc__ok$7$next[0:0]$8204 + attribute \src "libresoc.v:158080.3-158115.6" + wire $1\mul_op__rc__rc$6$next[0:0]$8205 + attribute \src "libresoc.v:158080.3-158115.6" + wire $1\mul_op__write_cr0$10$next[0:0]$8206 + attribute \src "libresoc.v:158067.3-158079.6" + wire width 2 $1\muxid$1$next[1:0]$8181 + attribute \src "libresoc.v:158116.3-158134.6" + wire width 64 $1\o$14$next[63:0]$8217 + attribute \src "libresoc.v:158116.3-158134.6" + wire $1\o_ok$next[0:0]$8216 + attribute \src "libresoc.v:157609.7-157609.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:156741.3-156758.6" - wire $1\r_busy$next[0:0]$8193 - attribute \src "libresoc.v:156573.7-156573.20" + attribute \src "libresoc.v:158049.3-158066.6" + wire $1\r_busy$next[0:0]$8177 + attribute \src "libresoc.v:157881.7-157881.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:156846.3-156864.6" - wire width 2 $1\xer_ov$next[1:0]$8244 - attribute \src "libresoc.v:156578.13-156578.26" + attribute \src "libresoc.v:158154.3-158172.6" + wire width 2 $1\xer_ov$next[1:0]$8228 + attribute \src "libresoc.v:157886.13-157886.26" wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:156846.3-156864.6" - wire $1\xer_ov_ok$next[0:0]$8245 - attribute \src "libresoc.v:156585.7-156585.23" + attribute \src "libresoc.v:158154.3-158172.6" + wire $1\xer_ov_ok$next[0:0]$8229 + attribute \src "libresoc.v:157893.7-157893.23" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:156865.3-156883.6" - wire $1\xer_so$15$next[0:0]$8251 - attribute \src "libresoc.v:156865.3-156883.6" - wire $1\xer_so_ok$next[0:0]$8250 - attribute \src "libresoc.v:156603.7-156603.23" + attribute \src "libresoc.v:158173.3-158191.6" + wire $1\xer_so$15$next[0:0]$8235 + attribute \src "libresoc.v:158173.3-158191.6" + wire $1\xer_so_ok$next[0:0]$8234 + attribute \src "libresoc.v:157911.7-157911.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:156827.3-156845.6" - wire $2\cr_a_ok$next[0:0]$8240 - attribute \src "libresoc.v:156772.3-156807.6" - wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8223 - attribute \src "libresoc.v:156772.3-156807.6" - wire $2\mul_op__imm_data__ok$5$next[0:0]$8224 - attribute \src "libresoc.v:156772.3-156807.6" - wire $2\mul_op__oe__oe$8$next[0:0]$8225 - attribute \src "libresoc.v:156772.3-156807.6" - wire $2\mul_op__oe__ok$9$next[0:0]$8226 - attribute \src "libresoc.v:156772.3-156807.6" - wire $2\mul_op__rc__ok$7$next[0:0]$8227 - attribute \src "libresoc.v:156772.3-156807.6" - wire $2\mul_op__rc__rc$6$next[0:0]$8228 - attribute \src "libresoc.v:156808.3-156826.6" - wire $2\o_ok$next[0:0]$8234 - attribute \src "libresoc.v:156741.3-156758.6" - wire $2\r_busy$next[0:0]$8194 - attribute \src "libresoc.v:156846.3-156864.6" - wire $2\xer_ov_ok$next[0:0]$8246 - attribute \src "libresoc.v:156865.3-156883.6" - wire $2\xer_so_ok$next[0:0]$8252 - attribute \src "libresoc.v:156610.18-156610.118" - wire $and$libresoc.v:156610$8153_Y + attribute \src "libresoc.v:158135.3-158153.6" + wire $2\cr_a_ok$next[0:0]$8224 + attribute \src "libresoc.v:158080.3-158115.6" + wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$8207 + attribute \src "libresoc.v:158080.3-158115.6" + wire $2\mul_op__imm_data__ok$5$next[0:0]$8208 + attribute \src "libresoc.v:158080.3-158115.6" + wire $2\mul_op__oe__oe$8$next[0:0]$8209 + attribute \src "libresoc.v:158080.3-158115.6" + wire $2\mul_op__oe__ok$9$next[0:0]$8210 + attribute \src "libresoc.v:158080.3-158115.6" + wire $2\mul_op__rc__ok$7$next[0:0]$8211 + attribute \src "libresoc.v:158080.3-158115.6" + wire $2\mul_op__rc__rc$6$next[0:0]$8212 + attribute \src "libresoc.v:158116.3-158134.6" + wire $2\o_ok$next[0:0]$8218 + attribute \src "libresoc.v:158049.3-158066.6" + wire $2\r_busy$next[0:0]$8178 + attribute \src "libresoc.v:158154.3-158172.6" + wire $2\xer_ov_ok$next[0:0]$8230 + attribute \src "libresoc.v:158173.3-158191.6" + wire $2\xer_so_ok$next[0:0]$8236 + attribute \src "libresoc.v:157918.18-157918.118" + wire $and$libresoc.v:157918$8137_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 44 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 38 \cr_a @@ -321217,7 +292587,7 @@ module \mul_pipe3 wire \cr_a_ok$74 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$next - attribute \src "libresoc.v:155614.7-155614.15" + attribute \src "libresoc.v:156922.7-156922.15" wire \initial attribute \enum_base_type "Function" attribute \enum_value_00000000000000 "NONE" @@ -322170,7 +293540,7 @@ module \mul_pipe3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:156610$8153 + cell $and $and$libresoc.v:157918$8137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -322178,10 +293548,10 @@ module \mul_pipe3 parameter \Y_WIDTH 1 connect \A \p_valid_i$55 connect \B \p_ready_o - connect \Y $and$libresoc.v:156610$8153_Y + connect \Y $and$libresoc.v:157918$8137_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:156655.8-156691.4" + attribute \src "libresoc.v:157963.8-157999.4" cell \mul3 \mul3 connect \mul_op__fn_unit \mul3_mul_op__fn_unit connect \mul_op__fn_unit$3 \mul3_mul_op__fn_unit$18 @@ -322220,13 +293590,13 @@ module \mul_pipe3 connect \xer_so_ok \mul3_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:156692.10-156695.4" + attribute \src "libresoc.v:158000.10-158003.4" cell \n$99 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:156696.16-156736.4" + attribute \src "libresoc.v:158004.16-158044.4" cell \output$100 \output connect \cr_a \output_cr_a connect \cr_a$16 \output_cr_a$46 @@ -322269,358 +293639,358 @@ module \mul_pipe3 connect \xer_so_ok \output_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:156737.10-156740.4" + attribute \src "libresoc.v:158045.10-158048.4" cell \p$98 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:155614.7-155614.20" - process $proc$libresoc.v:155614$8253 + attribute \src "libresoc.v:156922.7-156922.20" + process $proc$libresoc.v:156922$8237 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:155623.13-155623.24" - process $proc$libresoc.v:155623$8254 + attribute \src "libresoc.v:156931.13-156931.24" + process $proc$libresoc.v:156931$8238 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:155632.7-155632.21" - process $proc$libresoc.v:155632$8255 + attribute \src "libresoc.v:156940.7-156940.21" + process $proc$libresoc.v:156940$8239 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:155925.14-155925.44" - process $proc$libresoc.v:155925$8256 + attribute \src "libresoc.v:157233.14-157233.44" + process $proc$libresoc.v:157233$8240 assign { } { } - assign $0\mul_op__fn_unit$3[13:0]$8257 14'00000000000000 + assign $0\mul_op__fn_unit$3[13:0]$8241 14'00000000000000 sync always sync init - update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8257 + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8241 end - attribute \src "libresoc.v:155949.14-155949.63" - process $proc$libresoc.v:155949$8258 + attribute \src "libresoc.v:157257.14-157257.63" + process $proc$libresoc.v:157257$8242 assign { } { } - assign $0\mul_op__imm_data__data$4[63:0]$8259 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\mul_op__imm_data__data$4[63:0]$8243 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8259 + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8243 end - attribute \src "libresoc.v:155958.7-155958.38" - process $proc$libresoc.v:155958$8260 + attribute \src "libresoc.v:157266.7-157266.38" + process $proc$libresoc.v:157266$8244 assign { } { } - assign $0\mul_op__imm_data__ok$5[0:0]$8261 1'0 + assign $0\mul_op__imm_data__ok$5[0:0]$8245 1'0 sync always sync init - update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8261 + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8245 end - attribute \src "libresoc.v:155967.14-155967.39" - process $proc$libresoc.v:155967$8262 + attribute \src "libresoc.v:157275.14-157275.39" + process $proc$libresoc.v:157275$8246 assign { } { } - assign $0\mul_op__insn$13[31:0]$8263 0 + assign $0\mul_op__insn$13[31:0]$8247 0 sync always sync init - update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8263 + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8247 end - attribute \src "libresoc.v:156126.13-156126.42" - process $proc$libresoc.v:156126$8264 + attribute \src "libresoc.v:157434.13-157434.42" + process $proc$libresoc.v:157434$8248 assign { } { } - assign $0\mul_op__insn_type$2[6:0]$8265 7'0000000 + assign $0\mul_op__insn_type$2[6:0]$8249 7'0000000 sync always sync init - update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8265 + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8249 end - attribute \src "libresoc.v:156210.7-156210.35" - process $proc$libresoc.v:156210$8266 + attribute \src "libresoc.v:157518.7-157518.35" + process $proc$libresoc.v:157518$8250 assign { } { } - assign $0\mul_op__is_32bit$11[0:0]$8267 1'0 + assign $0\mul_op__is_32bit$11[0:0]$8251 1'0 sync always sync init - update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8267 + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8251 end - attribute \src "libresoc.v:156219.7-156219.36" - process $proc$libresoc.v:156219$8268 + attribute \src "libresoc.v:157527.7-157527.36" + process $proc$libresoc.v:157527$8252 assign { } { } - assign $0\mul_op__is_signed$12[0:0]$8269 1'0 + assign $0\mul_op__is_signed$12[0:0]$8253 1'0 sync always sync init - update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8269 + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8253 end - attribute \src "libresoc.v:156230.7-156230.32" - process $proc$libresoc.v:156230$8270 + attribute \src "libresoc.v:157538.7-157538.32" + process $proc$libresoc.v:157538$8254 assign { } { } - assign $0\mul_op__oe__oe$8[0:0]$8271 1'0 + assign $0\mul_op__oe__oe$8[0:0]$8255 1'0 sync always sync init - update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8271 + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8255 end - attribute \src "libresoc.v:156239.7-156239.32" - process $proc$libresoc.v:156239$8272 + attribute \src "libresoc.v:157547.7-157547.32" + process $proc$libresoc.v:157547$8256 assign { } { } - assign $0\mul_op__oe__ok$9[0:0]$8273 1'0 + assign $0\mul_op__oe__ok$9[0:0]$8257 1'0 sync always sync init - update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8273 + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8257 end - attribute \src "libresoc.v:156248.7-156248.32" - process $proc$libresoc.v:156248$8274 + attribute \src "libresoc.v:157556.7-157556.32" + process $proc$libresoc.v:157556$8258 assign { } { } - assign $0\mul_op__rc__ok$7[0:0]$8275 1'0 + assign $0\mul_op__rc__ok$7[0:0]$8259 1'0 sync always sync init - update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8275 + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8259 end - attribute \src "libresoc.v:156255.7-156255.32" - process $proc$libresoc.v:156255$8276 + attribute \src "libresoc.v:157563.7-157563.32" + process $proc$libresoc.v:157563$8260 assign { } { } - assign $0\mul_op__rc__rc$6[0:0]$8277 1'0 + assign $0\mul_op__rc__rc$6[0:0]$8261 1'0 sync always sync init - update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8277 + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8261 end - attribute \src "libresoc.v:156264.7-156264.36" - process $proc$libresoc.v:156264$8278 + attribute \src "libresoc.v:157572.7-157572.36" + process $proc$libresoc.v:157572$8262 assign { } { } - assign $0\mul_op__write_cr0$10[0:0]$8279 1'0 + assign $0\mul_op__write_cr0$10[0:0]$8263 1'0 sync always sync init - update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8279 + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8263 end - attribute \src "libresoc.v:156273.13-156273.29" - process $proc$libresoc.v:156273$8280 + attribute \src "libresoc.v:157581.13-157581.29" + process $proc$libresoc.v:157581$8264 assign { } { } - assign $0\muxid$1[1:0]$8281 2'00 + assign $0\muxid$1[1:0]$8265 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$8281 + update \muxid$1 $0\muxid$1[1:0]$8265 end - attribute \src "libresoc.v:156294.14-156294.43" - process $proc$libresoc.v:156294$8282 + attribute \src "libresoc.v:157602.14-157602.43" + process $proc$libresoc.v:157602$8266 assign { } { } - assign $0\o$14[63:0]$8283 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\o$14[63:0]$8267 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \o$14 $0\o$14[63:0]$8283 + update \o$14 $0\o$14[63:0]$8267 end - attribute \src "libresoc.v:156301.7-156301.18" - process $proc$libresoc.v:156301$8284 + attribute \src "libresoc.v:157609.7-157609.18" + process $proc$libresoc.v:157609$8268 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:156573.7-156573.20" - process $proc$libresoc.v:156573$8285 + attribute \src "libresoc.v:157881.7-157881.20" + process $proc$libresoc.v:157881$8269 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:156578.13-156578.26" - process $proc$libresoc.v:156578$8286 + attribute \src "libresoc.v:157886.13-157886.26" + process $proc$libresoc.v:157886$8270 assign { } { } assign $1\xer_ov[1:0] 2'00 sync always sync init update \xer_ov $1\xer_ov[1:0] end - attribute \src "libresoc.v:156585.7-156585.23" - process $proc$libresoc.v:156585$8287 + attribute \src "libresoc.v:157893.7-157893.23" + process $proc$libresoc.v:157893$8271 assign { } { } assign $1\xer_ov_ok[0:0] 1'0 sync always sync init update \xer_ov_ok $1\xer_ov_ok[0:0] end - attribute \src "libresoc.v:156596.7-156596.25" - process $proc$libresoc.v:156596$8288 + attribute \src "libresoc.v:157904.7-157904.25" + process $proc$libresoc.v:157904$8272 assign { } { } - assign $0\xer_so$15[0:0]$8289 1'0 + assign $0\xer_so$15[0:0]$8273 1'0 sync always sync init - update \xer_so$15 $0\xer_so$15[0:0]$8289 + update \xer_so$15 $0\xer_so$15[0:0]$8273 end - attribute \src "libresoc.v:156603.7-156603.23" - process $proc$libresoc.v:156603$8290 + attribute \src "libresoc.v:157911.7-157911.23" + process $proc$libresoc.v:157911$8274 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:156611.3-156612.37" - process $proc$libresoc.v:156611$8154 + attribute \src "libresoc.v:157919.3-157920.37" + process $proc$libresoc.v:157919$8138 assign { } { } - assign $0\xer_so$15[0:0]$8155 \xer_so$15$next + assign $0\xer_so$15[0:0]$8139 \xer_so$15$next sync posedge \coresync_clk - update \xer_so$15 $0\xer_so$15[0:0]$8155 + update \xer_so$15 $0\xer_so$15[0:0]$8139 end - attribute \src "libresoc.v:156613.3-156614.35" - process $proc$libresoc.v:156613$8156 + attribute \src "libresoc.v:157921.3-157922.35" + process $proc$libresoc.v:157921$8140 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:156615.3-156616.29" - process $proc$libresoc.v:156615$8157 + attribute \src "libresoc.v:157923.3-157924.29" + process $proc$libresoc.v:157923$8141 assign { } { } assign $0\xer_ov[1:0] \xer_ov$next sync posedge \coresync_clk update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:156617.3-156618.35" - process $proc$libresoc.v:156617$8158 + attribute \src "libresoc.v:157925.3-157926.35" + process $proc$libresoc.v:157925$8142 assign { } { } assign $0\xer_ov_ok[0:0] \xer_ov_ok$next sync posedge \coresync_clk update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:156619.3-156620.25" - process $proc$libresoc.v:156619$8159 + attribute \src "libresoc.v:157927.3-157928.25" + process $proc$libresoc.v:157927$8143 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:156621.3-156622.31" - process $proc$libresoc.v:156621$8160 + attribute \src "libresoc.v:157929.3-157930.31" + process $proc$libresoc.v:157929$8144 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:156623.3-156624.27" - process $proc$libresoc.v:156623$8161 + attribute \src "libresoc.v:157931.3-157932.27" + process $proc$libresoc.v:157931$8145 assign { } { } - assign $0\o$14[63:0]$8162 \o$14$next + assign $0\o$14[63:0]$8146 \o$14$next sync posedge \coresync_clk - update \o$14 $0\o$14[63:0]$8162 + update \o$14 $0\o$14[63:0]$8146 end - attribute \src "libresoc.v:156625.3-156626.25" - process $proc$libresoc.v:156625$8163 + attribute \src "libresoc.v:157933.3-157934.25" + process $proc$libresoc.v:157933$8147 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:156627.3-156628.57" - process $proc$libresoc.v:156627$8164 + attribute \src "libresoc.v:157935.3-157936.57" + process $proc$libresoc.v:157935$8148 assign { } { } - assign $0\mul_op__insn_type$2[6:0]$8165 \mul_op__insn_type$2$next + assign $0\mul_op__insn_type$2[6:0]$8149 \mul_op__insn_type$2$next sync posedge \coresync_clk - update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8165 + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$8149 end - attribute \src "libresoc.v:156629.3-156630.53" - process $proc$libresoc.v:156629$8166 + attribute \src "libresoc.v:157937.3-157938.53" + process $proc$libresoc.v:157937$8150 assign { } { } - assign $0\mul_op__fn_unit$3[13:0]$8167 \mul_op__fn_unit$3$next + assign $0\mul_op__fn_unit$3[13:0]$8151 \mul_op__fn_unit$3$next sync posedge \coresync_clk - update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8167 + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[13:0]$8151 end - attribute \src "libresoc.v:156631.3-156632.67" - process $proc$libresoc.v:156631$8168 + attribute \src "libresoc.v:157939.3-157940.67" + process $proc$libresoc.v:157939$8152 assign { } { } - assign $0\mul_op__imm_data__data$4[63:0]$8169 \mul_op__imm_data__data$4$next + assign $0\mul_op__imm_data__data$4[63:0]$8153 \mul_op__imm_data__data$4$next sync posedge \coresync_clk - update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8169 + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$8153 end - attribute \src "libresoc.v:156633.3-156634.63" - process $proc$libresoc.v:156633$8170 + attribute \src "libresoc.v:157941.3-157942.63" + process $proc$libresoc.v:157941$8154 assign { } { } - assign $0\mul_op__imm_data__ok$5[0:0]$8171 \mul_op__imm_data__ok$5$next + assign $0\mul_op__imm_data__ok$5[0:0]$8155 \mul_op__imm_data__ok$5$next sync posedge \coresync_clk - update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8171 + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$8155 end - attribute \src "libresoc.v:156635.3-156636.51" - process $proc$libresoc.v:156635$8172 + attribute \src "libresoc.v:157943.3-157944.51" + process $proc$libresoc.v:157943$8156 assign { } { } - assign $0\mul_op__rc__rc$6[0:0]$8173 \mul_op__rc__rc$6$next + assign $0\mul_op__rc__rc$6[0:0]$8157 \mul_op__rc__rc$6$next sync posedge \coresync_clk - update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8173 + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$8157 end - attribute \src "libresoc.v:156637.3-156638.51" - process $proc$libresoc.v:156637$8174 + attribute \src "libresoc.v:157945.3-157946.51" + process $proc$libresoc.v:157945$8158 assign { } { } - assign $0\mul_op__rc__ok$7[0:0]$8175 \mul_op__rc__ok$7$next + assign $0\mul_op__rc__ok$7[0:0]$8159 \mul_op__rc__ok$7$next sync posedge \coresync_clk - update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8175 + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$8159 end - attribute \src "libresoc.v:156639.3-156640.51" - process $proc$libresoc.v:156639$8176 + attribute \src "libresoc.v:157947.3-157948.51" + process $proc$libresoc.v:157947$8160 assign { } { } - assign $0\mul_op__oe__oe$8[0:0]$8177 \mul_op__oe__oe$8$next + assign $0\mul_op__oe__oe$8[0:0]$8161 \mul_op__oe__oe$8$next sync posedge \coresync_clk - update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8177 + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$8161 end - attribute \src "libresoc.v:156641.3-156642.51" - process $proc$libresoc.v:156641$8178 + attribute \src "libresoc.v:157949.3-157950.51" + process $proc$libresoc.v:157949$8162 assign { } { } - assign $0\mul_op__oe__ok$9[0:0]$8179 \mul_op__oe__ok$9$next + assign $0\mul_op__oe__ok$9[0:0]$8163 \mul_op__oe__ok$9$next sync posedge \coresync_clk - update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8179 + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$8163 end - attribute \src "libresoc.v:156643.3-156644.59" - process $proc$libresoc.v:156643$8180 + attribute \src "libresoc.v:157951.3-157952.59" + process $proc$libresoc.v:157951$8164 assign { } { } - assign $0\mul_op__write_cr0$10[0:0]$8181 \mul_op__write_cr0$10$next + assign $0\mul_op__write_cr0$10[0:0]$8165 \mul_op__write_cr0$10$next sync posedge \coresync_clk - update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8181 + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$8165 end - attribute \src "libresoc.v:156645.3-156646.57" - process $proc$libresoc.v:156645$8182 + attribute \src "libresoc.v:157953.3-157954.57" + process $proc$libresoc.v:157953$8166 assign { } { } - assign $0\mul_op__is_32bit$11[0:0]$8183 \mul_op__is_32bit$11$next + assign $0\mul_op__is_32bit$11[0:0]$8167 \mul_op__is_32bit$11$next sync posedge \coresync_clk - update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8183 + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$8167 end - attribute \src "libresoc.v:156647.3-156648.59" - process $proc$libresoc.v:156647$8184 + attribute \src "libresoc.v:157955.3-157956.59" + process $proc$libresoc.v:157955$8168 assign { } { } - assign $0\mul_op__is_signed$12[0:0]$8185 \mul_op__is_signed$12$next + assign $0\mul_op__is_signed$12[0:0]$8169 \mul_op__is_signed$12$next sync posedge \coresync_clk - update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8185 + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$8169 end - attribute \src "libresoc.v:156649.3-156650.49" - process $proc$libresoc.v:156649$8186 + attribute \src "libresoc.v:157957.3-157958.49" + process $proc$libresoc.v:157957$8170 assign { } { } - assign $0\mul_op__insn$13[31:0]$8187 \mul_op__insn$13$next + assign $0\mul_op__insn$13[31:0]$8171 \mul_op__insn$13$next sync posedge \coresync_clk - update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8187 + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$8171 end - attribute \src "libresoc.v:156651.3-156652.33" - process $proc$libresoc.v:156651$8188 + attribute \src "libresoc.v:157959.3-157960.33" + process $proc$libresoc.v:157959$8172 assign { } { } - assign $0\muxid$1[1:0]$8189 \muxid$1$next + assign $0\muxid$1[1:0]$8173 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8189 + update \muxid$1 $0\muxid$1[1:0]$8173 end - attribute \src "libresoc.v:156653.3-156654.29" - process $proc$libresoc.v:156653$8190 + attribute \src "libresoc.v:157961.3-157962.29" + process $proc$libresoc.v:157961$8174 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:156741.3-156758.6" - process $proc$libresoc.v:156741$8191 + attribute \src "libresoc.v:158049.3-158066.6" + process $proc$libresoc.v:158049$8175 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$8192 $2\r_busy$next[0:0]$8194 - attribute \src "libresoc.v:156742.5-156742.29" + assign $0\r_busy$next[0:0]$8176 $2\r_busy$next[0:0]$8178 + attribute \src "libresoc.v:158050.5-158050.29" switch \initial - attribute \src "libresoc.v:156742.9-156742.17" + attribute \src "libresoc.v:158050.9-158050.17" case 1'1 case end @@ -322629,34 +293999,34 @@ module \mul_pipe3 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$8193 1'1 + assign $1\r_busy$next[0:0]$8177 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$8193 1'0 + assign $1\r_busy$next[0:0]$8177 1'0 case - assign $1\r_busy$next[0:0]$8193 \r_busy + assign $1\r_busy$next[0:0]$8177 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$8194 1'0 + assign $2\r_busy$next[0:0]$8178 1'0 case - assign $2\r_busy$next[0:0]$8194 $1\r_busy$next[0:0]$8193 + assign $2\r_busy$next[0:0]$8178 $1\r_busy$next[0:0]$8177 end sync always - update \r_busy$next $0\r_busy$next[0:0]$8192 + update \r_busy$next $0\r_busy$next[0:0]$8176 end - attribute \src "libresoc.v:156759.3-156771.6" - process $proc$libresoc.v:156759$8195 + attribute \src "libresoc.v:158067.3-158079.6" + process $proc$libresoc.v:158067$8179 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$8196 $1\muxid$1$next[1:0]$8197 - attribute \src "libresoc.v:156760.5-156760.29" + assign $0\muxid$1$next[1:0]$8180 $1\muxid$1$next[1:0]$8181 + attribute \src "libresoc.v:158068.5-158068.29" switch \initial - attribute \src "libresoc.v:156760.9-156760.17" + attribute \src "libresoc.v:158068.9-158068.17" case 1'1 case end @@ -322665,19 +294035,19 @@ module \mul_pipe3 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$8197 \muxid$58 + assign $1\muxid$1$next[1:0]$8181 \muxid$58 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$8197 \muxid$58 + assign $1\muxid$1$next[1:0]$8181 \muxid$58 case - assign $1\muxid$1$next[1:0]$8197 \muxid$1 + assign $1\muxid$1$next[1:0]$8181 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8196 + update \muxid$1$next $0\muxid$1$next[1:0]$8180 end - attribute \src "libresoc.v:156772.3-156807.6" - process $proc$libresoc.v:156772$8198 + attribute \src "libresoc.v:158080.3-158115.6" + process $proc$libresoc.v:158080$8182 assign { } { } assign { } { } assign { } { } @@ -322702,27 +294072,27 @@ module \mul_pipe3 assign { } { } assign { } { } assign { } { } - assign $0\mul_op__fn_unit$3$next[13:0]$8199 $1\mul_op__fn_unit$3$next[13:0]$8211 + assign $0\mul_op__fn_unit$3$next[13:0]$8183 $1\mul_op__fn_unit$3$next[13:0]$8195 assign { } { } assign { } { } - assign $0\mul_op__insn$13$next[31:0]$8202 $1\mul_op__insn$13$next[31:0]$8214 - assign $0\mul_op__insn_type$2$next[6:0]$8203 $1\mul_op__insn_type$2$next[6:0]$8215 - assign $0\mul_op__is_32bit$11$next[0:0]$8204 $1\mul_op__is_32bit$11$next[0:0]$8216 - assign $0\mul_op__is_signed$12$next[0:0]$8205 $1\mul_op__is_signed$12$next[0:0]$8217 + assign $0\mul_op__insn$13$next[31:0]$8186 $1\mul_op__insn$13$next[31:0]$8198 + assign $0\mul_op__insn_type$2$next[6:0]$8187 $1\mul_op__insn_type$2$next[6:0]$8199 + assign $0\mul_op__is_32bit$11$next[0:0]$8188 $1\mul_op__is_32bit$11$next[0:0]$8200 + assign $0\mul_op__is_signed$12$next[0:0]$8189 $1\mul_op__is_signed$12$next[0:0]$8201 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\mul_op__write_cr0$10$next[0:0]$8210 $1\mul_op__write_cr0$10$next[0:0]$8222 - assign $0\mul_op__imm_data__data$4$next[63:0]$8200 $2\mul_op__imm_data__data$4$next[63:0]$8223 - assign $0\mul_op__imm_data__ok$5$next[0:0]$8201 $2\mul_op__imm_data__ok$5$next[0:0]$8224 - assign $0\mul_op__oe__oe$8$next[0:0]$8206 $2\mul_op__oe__oe$8$next[0:0]$8225 - assign $0\mul_op__oe__ok$9$next[0:0]$8207 $2\mul_op__oe__ok$9$next[0:0]$8226 - assign $0\mul_op__rc__ok$7$next[0:0]$8208 $2\mul_op__rc__ok$7$next[0:0]$8227 - assign $0\mul_op__rc__rc$6$next[0:0]$8209 $2\mul_op__rc__rc$6$next[0:0]$8228 - attribute \src "libresoc.v:156773.5-156773.29" + assign $0\mul_op__write_cr0$10$next[0:0]$8194 $1\mul_op__write_cr0$10$next[0:0]$8206 + assign $0\mul_op__imm_data__data$4$next[63:0]$8184 $2\mul_op__imm_data__data$4$next[63:0]$8207 + assign $0\mul_op__imm_data__ok$5$next[0:0]$8185 $2\mul_op__imm_data__ok$5$next[0:0]$8208 + assign $0\mul_op__oe__oe$8$next[0:0]$8190 $2\mul_op__oe__oe$8$next[0:0]$8209 + assign $0\mul_op__oe__ok$9$next[0:0]$8191 $2\mul_op__oe__ok$9$next[0:0]$8210 + assign $0\mul_op__rc__ok$7$next[0:0]$8192 $2\mul_op__rc__ok$7$next[0:0]$8211 + assign $0\mul_op__rc__rc$6$next[0:0]$8193 $2\mul_op__rc__rc$6$next[0:0]$8212 + attribute \src "libresoc.v:158081.5-158081.29" switch \initial - attribute \src "libresoc.v:156773.9-156773.17" + attribute \src "libresoc.v:158081.9-158081.17" case 1'1 case end @@ -322742,7 +294112,7 @@ module \mul_pipe3 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$13$next[31:0]$8214 $1\mul_op__is_signed$12$next[0:0]$8217 $1\mul_op__is_32bit$11$next[0:0]$8216 $1\mul_op__write_cr0$10$next[0:0]$8222 $1\mul_op__oe__ok$9$next[0:0]$8219 $1\mul_op__oe__oe$8$next[0:0]$8218 $1\mul_op__rc__ok$7$next[0:0]$8220 $1\mul_op__rc__rc$6$next[0:0]$8221 $1\mul_op__imm_data__ok$5$next[0:0]$8213 $1\mul_op__imm_data__data$4$next[63:0]$8212 $1\mul_op__fn_unit$3$next[13:0]$8211 $1\mul_op__insn_type$2$next[6:0]$8215 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } + assign { $1\mul_op__insn$13$next[31:0]$8198 $1\mul_op__is_signed$12$next[0:0]$8201 $1\mul_op__is_32bit$11$next[0:0]$8200 $1\mul_op__write_cr0$10$next[0:0]$8206 $1\mul_op__oe__ok$9$next[0:0]$8203 $1\mul_op__oe__oe$8$next[0:0]$8202 $1\mul_op__rc__ok$7$next[0:0]$8204 $1\mul_op__rc__rc$6$next[0:0]$8205 $1\mul_op__imm_data__ok$5$next[0:0]$8197 $1\mul_op__imm_data__data$4$next[63:0]$8196 $1\mul_op__fn_unit$3$next[13:0]$8195 $1\mul_op__insn_type$2$next[6:0]$8199 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -322757,20 +294127,20 @@ module \mul_pipe3 assign { } { } assign { } { } assign { } { } - assign { $1\mul_op__insn$13$next[31:0]$8214 $1\mul_op__is_signed$12$next[0:0]$8217 $1\mul_op__is_32bit$11$next[0:0]$8216 $1\mul_op__write_cr0$10$next[0:0]$8222 $1\mul_op__oe__ok$9$next[0:0]$8219 $1\mul_op__oe__oe$8$next[0:0]$8218 $1\mul_op__rc__ok$7$next[0:0]$8220 $1\mul_op__rc__rc$6$next[0:0]$8221 $1\mul_op__imm_data__ok$5$next[0:0]$8213 $1\mul_op__imm_data__data$4$next[63:0]$8212 $1\mul_op__fn_unit$3$next[13:0]$8211 $1\mul_op__insn_type$2$next[6:0]$8215 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } + assign { $1\mul_op__insn$13$next[31:0]$8198 $1\mul_op__is_signed$12$next[0:0]$8201 $1\mul_op__is_32bit$11$next[0:0]$8200 $1\mul_op__write_cr0$10$next[0:0]$8206 $1\mul_op__oe__ok$9$next[0:0]$8203 $1\mul_op__oe__oe$8$next[0:0]$8202 $1\mul_op__rc__ok$7$next[0:0]$8204 $1\mul_op__rc__rc$6$next[0:0]$8205 $1\mul_op__imm_data__ok$5$next[0:0]$8197 $1\mul_op__imm_data__data$4$next[63:0]$8196 $1\mul_op__fn_unit$3$next[13:0]$8195 $1\mul_op__insn_type$2$next[6:0]$8199 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } case - assign $1\mul_op__fn_unit$3$next[13:0]$8211 \mul_op__fn_unit$3 - assign $1\mul_op__imm_data__data$4$next[63:0]$8212 \mul_op__imm_data__data$4 - assign $1\mul_op__imm_data__ok$5$next[0:0]$8213 \mul_op__imm_data__ok$5 - assign $1\mul_op__insn$13$next[31:0]$8214 \mul_op__insn$13 - assign $1\mul_op__insn_type$2$next[6:0]$8215 \mul_op__insn_type$2 - assign $1\mul_op__is_32bit$11$next[0:0]$8216 \mul_op__is_32bit$11 - assign $1\mul_op__is_signed$12$next[0:0]$8217 \mul_op__is_signed$12 - assign $1\mul_op__oe__oe$8$next[0:0]$8218 \mul_op__oe__oe$8 - assign $1\mul_op__oe__ok$9$next[0:0]$8219 \mul_op__oe__ok$9 - assign $1\mul_op__rc__ok$7$next[0:0]$8220 \mul_op__rc__ok$7 - assign $1\mul_op__rc__rc$6$next[0:0]$8221 \mul_op__rc__rc$6 - assign $1\mul_op__write_cr0$10$next[0:0]$8222 \mul_op__write_cr0$10 + assign $1\mul_op__fn_unit$3$next[13:0]$8195 \mul_op__fn_unit$3 + assign $1\mul_op__imm_data__data$4$next[63:0]$8196 \mul_op__imm_data__data$4 + assign $1\mul_op__imm_data__ok$5$next[0:0]$8197 \mul_op__imm_data__ok$5 + assign $1\mul_op__insn$13$next[31:0]$8198 \mul_op__insn$13 + assign $1\mul_op__insn_type$2$next[6:0]$8199 \mul_op__insn_type$2 + assign $1\mul_op__is_32bit$11$next[0:0]$8200 \mul_op__is_32bit$11 + assign $1\mul_op__is_signed$12$next[0:0]$8201 \mul_op__is_signed$12 + assign $1\mul_op__oe__oe$8$next[0:0]$8202 \mul_op__oe__oe$8 + assign $1\mul_op__oe__ok$9$next[0:0]$8203 \mul_op__oe__ok$9 + assign $1\mul_op__rc__ok$7$next[0:0]$8204 \mul_op__rc__ok$7 + assign $1\mul_op__rc__rc$6$next[0:0]$8205 \mul_op__rc__rc$6 + assign $1\mul_op__write_cr0$10$next[0:0]$8206 \mul_op__write_cr0$10 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -322782,46 +294152,46 @@ module \mul_pipe3 assign { } { } assign { } { } assign { } { } - assign $2\mul_op__imm_data__data$4$next[63:0]$8223 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\mul_op__imm_data__ok$5$next[0:0]$8224 1'0 - assign $2\mul_op__rc__rc$6$next[0:0]$8228 1'0 - assign $2\mul_op__rc__ok$7$next[0:0]$8227 1'0 - assign $2\mul_op__oe__oe$8$next[0:0]$8225 1'0 - assign $2\mul_op__oe__ok$9$next[0:0]$8226 1'0 + assign $2\mul_op__imm_data__data$4$next[63:0]$8207 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\mul_op__imm_data__ok$5$next[0:0]$8208 1'0 + assign $2\mul_op__rc__rc$6$next[0:0]$8212 1'0 + assign $2\mul_op__rc__ok$7$next[0:0]$8211 1'0 + assign $2\mul_op__oe__oe$8$next[0:0]$8209 1'0 + assign $2\mul_op__oe__ok$9$next[0:0]$8210 1'0 case - assign $2\mul_op__imm_data__data$4$next[63:0]$8223 $1\mul_op__imm_data__data$4$next[63:0]$8212 - assign $2\mul_op__imm_data__ok$5$next[0:0]$8224 $1\mul_op__imm_data__ok$5$next[0:0]$8213 - assign $2\mul_op__oe__oe$8$next[0:0]$8225 $1\mul_op__oe__oe$8$next[0:0]$8218 - assign $2\mul_op__oe__ok$9$next[0:0]$8226 $1\mul_op__oe__ok$9$next[0:0]$8219 - assign $2\mul_op__rc__ok$7$next[0:0]$8227 $1\mul_op__rc__ok$7$next[0:0]$8220 - assign $2\mul_op__rc__rc$6$next[0:0]$8228 $1\mul_op__rc__rc$6$next[0:0]$8221 + assign $2\mul_op__imm_data__data$4$next[63:0]$8207 $1\mul_op__imm_data__data$4$next[63:0]$8196 + assign $2\mul_op__imm_data__ok$5$next[0:0]$8208 $1\mul_op__imm_data__ok$5$next[0:0]$8197 + assign $2\mul_op__oe__oe$8$next[0:0]$8209 $1\mul_op__oe__oe$8$next[0:0]$8202 + assign $2\mul_op__oe__ok$9$next[0:0]$8210 $1\mul_op__oe__ok$9$next[0:0]$8203 + assign $2\mul_op__rc__ok$7$next[0:0]$8211 $1\mul_op__rc__ok$7$next[0:0]$8204 + assign $2\mul_op__rc__rc$6$next[0:0]$8212 $1\mul_op__rc__rc$6$next[0:0]$8205 end sync always - update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[13:0]$8199 - update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$8200 - update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$8201 - update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$8202 - update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$8203 - update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$8204 - update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$8205 - update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$8206 - update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$8207 - update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$8208 - update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$8209 - update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$8210 + update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[13:0]$8183 + update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$8184 + update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$8185 + update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$8186 + update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$8187 + update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$8188 + update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$8189 + update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$8190 + update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$8191 + update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$8192 + update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$8193 + update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$8194 end - attribute \src "libresoc.v:156808.3-156826.6" - process $proc$libresoc.v:156808$8229 + attribute \src "libresoc.v:158116.3-158134.6" + process $proc$libresoc.v:158116$8213 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$14$next[63:0]$8231 $1\o$14$next[63:0]$8233 - assign $0\o_ok$next[0:0]$8230 $2\o_ok$next[0:0]$8234 - attribute \src "libresoc.v:156809.5-156809.29" + assign $0\o$14$next[63:0]$8215 $1\o$14$next[63:0]$8217 + assign $0\o_ok$next[0:0]$8214 $2\o_ok$next[0:0]$8218 + attribute \src "libresoc.v:158117.5-158117.29" switch \initial - attribute \src "libresoc.v:156809.9-156809.17" + attribute \src "libresoc.v:158117.9-158117.17" case 1'1 case end @@ -322831,41 +294201,41 @@ module \mul_pipe3 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$8232 $1\o$14$next[63:0]$8233 } { \o_ok$72 \o$71 } + assign { $1\o_ok$next[0:0]$8216 $1\o$14$next[63:0]$8217 } { \o_ok$72 \o$71 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$8232 $1\o$14$next[63:0]$8233 } { \o_ok$72 \o$71 } + assign { $1\o_ok$next[0:0]$8216 $1\o$14$next[63:0]$8217 } { \o_ok$72 \o$71 } case - assign $1\o_ok$next[0:0]$8232 \o_ok - assign $1\o$14$next[63:0]$8233 \o$14 + assign $1\o_ok$next[0:0]$8216 \o_ok + assign $1\o$14$next[63:0]$8217 \o$14 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$8234 1'0 + assign $2\o_ok$next[0:0]$8218 1'0 case - assign $2\o_ok$next[0:0]$8234 $1\o_ok$next[0:0]$8232 + assign $2\o_ok$next[0:0]$8218 $1\o_ok$next[0:0]$8216 end sync always - update \o_ok$next $0\o_ok$next[0:0]$8230 - update \o$14$next $0\o$14$next[63:0]$8231 + update \o_ok$next $0\o_ok$next[0:0]$8214 + update \o$14$next $0\o$14$next[63:0]$8215 end - attribute \src "libresoc.v:156827.3-156845.6" - process $proc$libresoc.v:156827$8235 + attribute \src "libresoc.v:158135.3-158153.6" + process $proc$libresoc.v:158135$8219 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$next[3:0]$8236 $1\cr_a$next[3:0]$8238 + assign $0\cr_a$next[3:0]$8220 $1\cr_a$next[3:0]$8222 assign { } { } - assign $0\cr_a_ok$next[0:0]$8237 $2\cr_a_ok$next[0:0]$8240 - attribute \src "libresoc.v:156828.5-156828.29" + assign $0\cr_a_ok$next[0:0]$8221 $2\cr_a_ok$next[0:0]$8224 + attribute \src "libresoc.v:158136.5-158136.29" switch \initial - attribute \src "libresoc.v:156828.9-156828.17" + attribute \src "libresoc.v:158136.9-158136.17" case 1'1 case end @@ -322875,41 +294245,41 @@ module \mul_pipe3 case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$8239 $1\cr_a$next[3:0]$8238 } { \cr_a_ok$74 \cr_a$73 } + assign { $1\cr_a_ok$next[0:0]$8223 $1\cr_a$next[3:0]$8222 } { \cr_a_ok$74 \cr_a$73 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$8239 $1\cr_a$next[3:0]$8238 } { \cr_a_ok$74 \cr_a$73 } + assign { $1\cr_a_ok$next[0:0]$8223 $1\cr_a$next[3:0]$8222 } { \cr_a_ok$74 \cr_a$73 } case - assign $1\cr_a$next[3:0]$8238 \cr_a - assign $1\cr_a_ok$next[0:0]$8239 \cr_a_ok + assign $1\cr_a$next[3:0]$8222 \cr_a + assign $1\cr_a_ok$next[0:0]$8223 \cr_a_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$8240 1'0 + assign $2\cr_a_ok$next[0:0]$8224 1'0 case - assign $2\cr_a_ok$next[0:0]$8240 $1\cr_a_ok$next[0:0]$8239 + assign $2\cr_a_ok$next[0:0]$8224 $1\cr_a_ok$next[0:0]$8223 end sync always - update \cr_a$next $0\cr_a$next[3:0]$8236 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8237 + update \cr_a$next $0\cr_a$next[3:0]$8220 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8221 end - attribute \src "libresoc.v:156846.3-156864.6" - process $proc$libresoc.v:156846$8241 + attribute \src "libresoc.v:158154.3-158172.6" + process $proc$libresoc.v:158154$8225 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ov$next[1:0]$8242 $1\xer_ov$next[1:0]$8244 + assign $0\xer_ov$next[1:0]$8226 $1\xer_ov$next[1:0]$8228 assign { } { } - assign $0\xer_ov_ok$next[0:0]$8243 $2\xer_ov_ok$next[0:0]$8246 - attribute \src "libresoc.v:156847.5-156847.29" + assign $0\xer_ov_ok$next[0:0]$8227 $2\xer_ov_ok$next[0:0]$8230 + attribute \src "libresoc.v:158155.5-158155.29" switch \initial - attribute \src "libresoc.v:156847.9-156847.17" + attribute \src "libresoc.v:158155.9-158155.17" case 1'1 case end @@ -322919,41 +294289,41 @@ module \mul_pipe3 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8245 $1\xer_ov$next[1:0]$8244 } { \xer_ov_ok$76 \xer_ov$75 } + assign { $1\xer_ov_ok$next[0:0]$8229 $1\xer_ov$next[1:0]$8228 } { \xer_ov_ok$76 \xer_ov$75 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8245 $1\xer_ov$next[1:0]$8244 } { \xer_ov_ok$76 \xer_ov$75 } + assign { $1\xer_ov_ok$next[0:0]$8229 $1\xer_ov$next[1:0]$8228 } { \xer_ov_ok$76 \xer_ov$75 } case - assign $1\xer_ov$next[1:0]$8244 \xer_ov - assign $1\xer_ov_ok$next[0:0]$8245 \xer_ov_ok + assign $1\xer_ov$next[1:0]$8228 \xer_ov + assign $1\xer_ov_ok$next[0:0]$8229 \xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ov_ok$next[0:0]$8246 1'0 + assign $2\xer_ov_ok$next[0:0]$8230 1'0 case - assign $2\xer_ov_ok$next[0:0]$8246 $1\xer_ov_ok$next[0:0]$8245 + assign $2\xer_ov_ok$next[0:0]$8230 $1\xer_ov_ok$next[0:0]$8229 end sync always - update \xer_ov$next $0\xer_ov$next[1:0]$8242 - update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8243 + update \xer_ov$next $0\xer_ov$next[1:0]$8226 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8227 end - attribute \src "libresoc.v:156865.3-156883.6" - process $proc$libresoc.v:156865$8247 + attribute \src "libresoc.v:158173.3-158191.6" + process $proc$libresoc.v:158173$8231 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$15$next[0:0]$8249 $1\xer_so$15$next[0:0]$8251 - assign $0\xer_so_ok$next[0:0]$8248 $2\xer_so_ok$next[0:0]$8252 - attribute \src "libresoc.v:156866.5-156866.29" + assign $0\xer_so$15$next[0:0]$8233 $1\xer_so$15$next[0:0]$8235 + assign $0\xer_so_ok$next[0:0]$8232 $2\xer_so_ok$next[0:0]$8236 + attribute \src "libresoc.v:158174.5-158174.29" switch \initial - attribute \src "libresoc.v:156866.9-156866.17" + attribute \src "libresoc.v:158174.9-158174.17" case 1'1 case end @@ -322963,30 +294333,30 @@ module \mul_pipe3 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$8250 $1\xer_so$15$next[0:0]$8251 } { \xer_so_ok$78 \xer_so$77 } + assign { $1\xer_so_ok$next[0:0]$8234 $1\xer_so$15$next[0:0]$8235 } { \xer_so_ok$78 \xer_so$77 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$8250 $1\xer_so$15$next[0:0]$8251 } { \xer_so_ok$78 \xer_so$77 } + assign { $1\xer_so_ok$next[0:0]$8234 $1\xer_so$15$next[0:0]$8235 } { \xer_so_ok$78 \xer_so$77 } case - assign $1\xer_so_ok$next[0:0]$8250 \xer_so_ok - assign $1\xer_so$15$next[0:0]$8251 \xer_so$15 + assign $1\xer_so_ok$next[0:0]$8234 \xer_so_ok + assign $1\xer_so$15$next[0:0]$8235 \xer_so$15 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$8252 1'0 + assign $2\xer_so_ok$next[0:0]$8236 1'0 case - assign $2\xer_so_ok$next[0:0]$8252 $1\xer_so_ok$next[0:0]$8250 + assign $2\xer_so_ok$next[0:0]$8236 $1\xer_so_ok$next[0:0]$8234 end sync always - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8248 - update \xer_so$15$next $0\xer_so$15$next[0:0]$8249 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8232 + update \xer_so$15$next $0\xer_so$15$next[0:0]$8233 end - connect \$56 $and$libresoc.v:156610$8153_Y + connect \$56 $and$libresoc.v:157918$8137_Y connect \cr_a$51 4'0000 connect \cr_a_ok$52 1'0 connect \p_ready_o \n_i_rdy_data @@ -323013,13 +294383,13 @@ module \mul_pipe3 connect { \mul3_mul_op__insn \mul3_mul_op__is_signed \mul3_mul_op__is_32bit \mul3_mul_op__write_cr0 \mul3_mul_op__oe__ok \mul3_mul_op__oe__oe \mul3_mul_op__rc__ok \mul3_mul_op__rc__rc \mul3_mul_op__imm_data__ok \mul3_mul_op__imm_data__data \mul3_mul_op__fn_unit \mul3_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \mul3_muxid \muxid end -attribute \src "libresoc.v:156913.1-156924.10" +attribute \src "libresoc.v:158221.1-158232.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.n" attribute \generator "nMigen" module \n - attribute \src "libresoc.v:156922.17-156922.111" - wire $and$libresoc.v:156922$8291_Y + attribute \src "libresoc.v:158230.17-158230.111" + wire $and$libresoc.v:158230$8275_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323029,7 +294399,7 @@ module \n attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:156922$8291 + cell $and $and$libresoc.v:158230$8275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323037,18 +294407,18 @@ module \n parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:156922$8291_Y + connect \Y $and$libresoc.v:158230$8275_Y end - connect \$1 $and$libresoc.v:156922$8291_Y + connect \$1 $and$libresoc.v:158230$8275_Y connect \trigger \$1 end -attribute \src "libresoc.v:156928.1-156939.10" +attribute \src "libresoc.v:158236.1-158247.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.n" attribute \generator "nMigen" module \n$109 - attribute \src "libresoc.v:156937.17-156937.111" - wire $and$libresoc.v:156937$8292_Y + attribute \src "libresoc.v:158245.17-158245.111" + wire $and$libresoc.v:158245$8276_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323058,7 +294428,7 @@ module \n$109 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:156937$8292 + cell $and $and$libresoc.v:158245$8276 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323066,18 +294436,18 @@ module \n$109 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:156937$8292_Y + connect \Y $and$libresoc.v:158245$8276_Y end - connect \$1 $and$libresoc.v:156937$8292_Y + connect \$1 $and$libresoc.v:158245$8276_Y connect \trigger \$1 end -attribute \src "libresoc.v:156943.1-156954.10" +attribute \src "libresoc.v:158251.1-158262.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.n" attribute \generator "nMigen" module \n$112 - attribute \src "libresoc.v:156952.17-156952.111" - wire $and$libresoc.v:156952$8293_Y + attribute \src "libresoc.v:158260.17-158260.111" + wire $and$libresoc.v:158260$8277_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323087,7 +294457,7 @@ module \n$112 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:156952$8293 + cell $and $and$libresoc.v:158260$8277 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323095,18 +294465,18 @@ module \n$112 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:156952$8293_Y + connect \Y $and$libresoc.v:158260$8277_Y end - connect \$1 $and$libresoc.v:156952$8293_Y + connect \$1 $and$libresoc.v:158260$8277_Y connect \trigger \$1 end -attribute \src "libresoc.v:156958.1-156969.10" +attribute \src "libresoc.v:158266.1-158277.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.n" attribute \generator "nMigen" module \n$117 - attribute \src "libresoc.v:156967.17-156967.111" - wire $and$libresoc.v:156967$8294_Y + attribute \src "libresoc.v:158275.17-158275.111" + wire $and$libresoc.v:158275$8278_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323116,7 +294486,7 @@ module \n$117 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:156967$8294 + cell $and $and$libresoc.v:158275$8278 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323124,18 +294494,18 @@ module \n$117 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:156967$8294_Y + connect \Y $and$libresoc.v:158275$8278_Y end - connect \$1 $and$libresoc.v:156967$8294_Y + connect \$1 $and$libresoc.v:158275$8278_Y connect \trigger \$1 end -attribute \src "libresoc.v:156973.1-156984.10" +attribute \src "libresoc.v:158281.1-158292.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.n" attribute \generator "nMigen" module \n$18 - attribute \src "libresoc.v:156982.17-156982.111" - wire $and$libresoc.v:156982$8295_Y + attribute \src "libresoc.v:158290.17-158290.111" + wire $and$libresoc.v:158290$8279_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323145,7 +294515,7 @@ module \n$18 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:156982$8295 + cell $and $and$libresoc.v:158290$8279 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323153,18 +294523,18 @@ module \n$18 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:156982$8295_Y + connect \Y $and$libresoc.v:158290$8279_Y end - connect \$1 $and$libresoc.v:156982$8295_Y + connect \$1 $and$libresoc.v:158290$8279_Y connect \trigger \$1 end -attribute \src "libresoc.v:156988.1-156999.10" +attribute \src "libresoc.v:158296.1-158307.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.n" attribute \generator "nMigen" module \n$2 - attribute \src "libresoc.v:156997.17-156997.111" - wire $and$libresoc.v:156997$8296_Y + attribute \src "libresoc.v:158305.17-158305.111" + wire $and$libresoc.v:158305$8280_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323174,7 +294544,7 @@ module \n$2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:156997$8296 + cell $and $and$libresoc.v:158305$8280 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323182,18 +294552,18 @@ module \n$2 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:156997$8296_Y + connect \Y $and$libresoc.v:158305$8280_Y end - connect \$1 $and$libresoc.v:156997$8296_Y + connect \$1 $and$libresoc.v:158305$8280_Y connect \trigger \$1 end -attribute \src "libresoc.v:157003.1-157014.10" +attribute \src "libresoc.v:158311.1-158322.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.n" attribute \generator "nMigen" module \n$21 - attribute \src "libresoc.v:157012.17-157012.111" - wire $and$libresoc.v:157012$8297_Y + attribute \src "libresoc.v:158320.17-158320.111" + wire $and$libresoc.v:158320$8281_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323203,7 +294573,7 @@ module \n$21 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157012$8297 + cell $and $and$libresoc.v:158320$8281 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323211,18 +294581,18 @@ module \n$21 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157012$8297_Y + connect \Y $and$libresoc.v:158320$8281_Y end - connect \$1 $and$libresoc.v:157012$8297_Y + connect \$1 $and$libresoc.v:158320$8281_Y connect \trigger \$1 end -attribute \src "libresoc.v:157018.1-157029.10" +attribute \src "libresoc.v:158326.1-158337.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.n" attribute \generator "nMigen" module \n$31 - attribute \src "libresoc.v:157027.17-157027.111" - wire $and$libresoc.v:157027$8298_Y + attribute \src "libresoc.v:158335.17-158335.111" + wire $and$libresoc.v:158335$8282_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323232,7 +294602,7 @@ module \n$31 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157027$8298 + cell $and $and$libresoc.v:158335$8282 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323240,18 +294610,18 @@ module \n$31 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157027$8298_Y + connect \Y $and$libresoc.v:158335$8282_Y end - connect \$1 $and$libresoc.v:157027$8298_Y + connect \$1 $and$libresoc.v:158335$8282_Y connect \trigger \$1 end -attribute \src "libresoc.v:157033.1-157044.10" +attribute \src "libresoc.v:158341.1-158352.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.n" attribute \generator "nMigen" module \n$34 - attribute \src "libresoc.v:157042.17-157042.111" - wire $and$libresoc.v:157042$8299_Y + attribute \src "libresoc.v:158350.17-158350.111" + wire $and$libresoc.v:158350$8283_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323261,7 +294631,7 @@ module \n$34 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157042$8299 + cell $and $and$libresoc.v:158350$8283 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323269,18 +294639,18 @@ module \n$34 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157042$8299_Y + connect \Y $and$libresoc.v:158350$8283_Y end - connect \$1 $and$libresoc.v:157042$8299_Y + connect \$1 $and$libresoc.v:158350$8283_Y connect \trigger \$1 end -attribute \src "libresoc.v:157048.1-157059.10" +attribute \src "libresoc.v:158356.1-158367.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.n" attribute \generator "nMigen" module \n$37 - attribute \src "libresoc.v:157057.17-157057.111" - wire $and$libresoc.v:157057$8300_Y + attribute \src "libresoc.v:158365.17-158365.111" + wire $and$libresoc.v:158365$8284_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323290,7 +294660,7 @@ module \n$37 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157057$8300 + cell $and $and$libresoc.v:158365$8284 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323298,18 +294668,18 @@ module \n$37 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157057$8300_Y + connect \Y $and$libresoc.v:158365$8284_Y end - connect \$1 $and$libresoc.v:157057$8300_Y + connect \$1 $and$libresoc.v:158365$8284_Y connect \trigger \$1 end -attribute \src "libresoc.v:157063.1-157074.10" +attribute \src "libresoc.v:158371.1-158382.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.n" attribute \generator "nMigen" module \n$4 - attribute \src "libresoc.v:157072.17-157072.111" - wire $and$libresoc.v:157072$8301_Y + attribute \src "libresoc.v:158380.17-158380.111" + wire $and$libresoc.v:158380$8285_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323319,7 +294689,7 @@ module \n$4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157072$8301 + cell $and $and$libresoc.v:158380$8285 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323327,18 +294697,18 @@ module \n$4 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157072$8301_Y + connect \Y $and$libresoc.v:158380$8285_Y end - connect \$1 $and$libresoc.v:157072$8301_Y + connect \$1 $and$libresoc.v:158380$8285_Y connect \trigger \$1 end -attribute \src "libresoc.v:157078.1-157089.10" +attribute \src "libresoc.v:158386.1-158397.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.n" attribute \generator "nMigen" module \n$47 - attribute \src "libresoc.v:157087.17-157087.111" - wire $and$libresoc.v:157087$8302_Y + attribute \src "libresoc.v:158395.17-158395.111" + wire $and$libresoc.v:158395$8286_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323348,7 +294718,7 @@ module \n$47 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157087$8302 + cell $and $and$libresoc.v:158395$8286 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323356,18 +294726,18 @@ module \n$47 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157087$8302_Y + connect \Y $and$libresoc.v:158395$8286_Y end - connect \$1 $and$libresoc.v:157087$8302_Y + connect \$1 $and$libresoc.v:158395$8286_Y connect \trigger \$1 end -attribute \src "libresoc.v:157093.1-157104.10" +attribute \src "libresoc.v:158401.1-158412.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.n" attribute \generator "nMigen" module \n$49 - attribute \src "libresoc.v:157102.17-157102.111" - wire $and$libresoc.v:157102$8303_Y + attribute \src "libresoc.v:158410.17-158410.111" + wire $and$libresoc.v:158410$8287_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323377,7 +294747,7 @@ module \n$49 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157102$8303 + cell $and $and$libresoc.v:158410$8287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323385,18 +294755,18 @@ module \n$49 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157102$8303_Y + connect \Y $and$libresoc.v:158410$8287_Y end - connect \$1 $and$libresoc.v:157102$8303_Y + connect \$1 $and$libresoc.v:158410$8287_Y connect \trigger \$1 end -attribute \src "libresoc.v:157108.1-157119.10" +attribute \src "libresoc.v:158416.1-158427.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.n" attribute \generator "nMigen" module \n$53 - attribute \src "libresoc.v:157117.17-157117.111" - wire $and$libresoc.v:157117$8304_Y + attribute \src "libresoc.v:158425.17-158425.111" + wire $and$libresoc.v:158425$8288_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323406,7 +294776,7 @@ module \n$53 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157117$8304 + cell $and $and$libresoc.v:158425$8288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323414,18 +294784,18 @@ module \n$53 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157117$8304_Y + connect \Y $and$libresoc.v:158425$8288_Y end - connect \$1 $and$libresoc.v:157117$8304_Y + connect \$1 $and$libresoc.v:158425$8288_Y connect \trigger \$1 end -attribute \src "libresoc.v:157123.1-157134.10" +attribute \src "libresoc.v:158431.1-158442.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.n" attribute \generator "nMigen" module \n$6 - attribute \src "libresoc.v:157132.17-157132.111" - wire $and$libresoc.v:157132$8305_Y + attribute \src "libresoc.v:158440.17-158440.111" + wire $and$libresoc.v:158440$8289_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323435,7 +294805,7 @@ module \n$6 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157132$8305 + cell $and $and$libresoc.v:158440$8289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323443,18 +294813,18 @@ module \n$6 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157132$8305_Y + connect \Y $and$libresoc.v:158440$8289_Y end - connect \$1 $and$libresoc.v:157132$8305_Y + connect \$1 $and$libresoc.v:158440$8289_Y connect \trigger \$1 end -attribute \src "libresoc.v:157138.1-157149.10" +attribute \src "libresoc.v:158446.1-158457.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.n" attribute \generator "nMigen" module \n$63 - attribute \src "libresoc.v:157147.17-157147.111" - wire $and$libresoc.v:157147$8306_Y + attribute \src "libresoc.v:158455.17-158455.111" + wire $and$libresoc.v:158455$8290_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323464,7 +294834,7 @@ module \n$63 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157147$8306 + cell $and $and$libresoc.v:158455$8290 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323472,18 +294842,18 @@ module \n$63 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157147$8306_Y + connect \Y $and$libresoc.v:158455$8290_Y end - connect \$1 $and$libresoc.v:157147$8306_Y + connect \$1 $and$libresoc.v:158455$8290_Y connect \trigger \$1 end -attribute \src "libresoc.v:157153.1-157164.10" +attribute \src "libresoc.v:158461.1-158472.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.n" attribute \generator "nMigen" module \n$66 - attribute \src "libresoc.v:157162.17-157162.111" - wire $and$libresoc.v:157162$8307_Y + attribute \src "libresoc.v:158470.17-158470.111" + wire $and$libresoc.v:158470$8291_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323493,7 +294863,7 @@ module \n$66 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157162$8307 + cell $and $and$libresoc.v:158470$8291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323501,18 +294871,18 @@ module \n$66 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157162$8307_Y + connect \Y $and$libresoc.v:158470$8291_Y end - connect \$1 $and$libresoc.v:157162$8307_Y + connect \$1 $and$libresoc.v:158470$8291_Y connect \trigger \$1 end -attribute \src "libresoc.v:157168.1-157179.10" +attribute \src "libresoc.v:158476.1-158487.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.n" attribute \generator "nMigen" module \n$75 - attribute \src "libresoc.v:157177.17-157177.111" - wire $and$libresoc.v:157177$8308_Y + attribute \src "libresoc.v:158485.17-158485.111" + wire $and$libresoc.v:158485$8292_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323522,7 +294892,7 @@ module \n$75 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157177$8308 + cell $and $and$libresoc.v:158485$8292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323530,18 +294900,18 @@ module \n$75 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157177$8308_Y + connect \Y $and$libresoc.v:158485$8292_Y end - connect \$1 $and$libresoc.v:157177$8308_Y + connect \$1 $and$libresoc.v:158485$8292_Y connect \trigger \$1 end -attribute \src "libresoc.v:157183.1-157194.10" +attribute \src "libresoc.v:158491.1-158502.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.n" attribute \generator "nMigen" module \n$77 - attribute \src "libresoc.v:157192.17-157192.111" - wire $and$libresoc.v:157192$8309_Y + attribute \src "libresoc.v:158500.17-158500.111" + wire $and$libresoc.v:158500$8293_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323551,7 +294921,7 @@ module \n$77 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157192$8309 + cell $and $and$libresoc.v:158500$8293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323559,18 +294929,18 @@ module \n$77 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157192$8309_Y + connect \Y $and$libresoc.v:158500$8293_Y end - connect \$1 $and$libresoc.v:157192$8309_Y + connect \$1 $and$libresoc.v:158500$8293_Y connect \trigger \$1 end -attribute \src "libresoc.v:157198.1-157209.10" +attribute \src "libresoc.v:158506.1-158517.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.n" attribute \generator "nMigen" module \n$8 - attribute \src "libresoc.v:157207.17-157207.111" - wire $and$libresoc.v:157207$8310_Y + attribute \src "libresoc.v:158515.17-158515.111" + wire $and$libresoc.v:158515$8294_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323580,7 +294950,7 @@ module \n$8 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157207$8310 + cell $and $and$libresoc.v:158515$8294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323588,18 +294958,18 @@ module \n$8 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157207$8310_Y + connect \Y $and$libresoc.v:158515$8294_Y end - connect \$1 $and$libresoc.v:157207$8310_Y + connect \$1 $and$libresoc.v:158515$8294_Y connect \trigger \$1 end -attribute \src "libresoc.v:157213.1-157224.10" +attribute \src "libresoc.v:158521.1-158532.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.n" attribute \generator "nMigen" module \n$80 - attribute \src "libresoc.v:157222.17-157222.111" - wire $and$libresoc.v:157222$8311_Y + attribute \src "libresoc.v:158530.17-158530.111" + wire $and$libresoc.v:158530$8295_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323609,7 +294979,7 @@ module \n$80 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157222$8311 + cell $and $and$libresoc.v:158530$8295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323617,18 +294987,18 @@ module \n$80 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157222$8311_Y + connect \Y $and$libresoc.v:158530$8295_Y end - connect \$1 $and$libresoc.v:157222$8311_Y + connect \$1 $and$libresoc.v:158530$8295_Y connect \trigger \$1 end -attribute \src "libresoc.v:157228.1-157239.10" +attribute \src "libresoc.v:158536.1-158547.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.n" attribute \generator "nMigen" module \n$82 - attribute \src "libresoc.v:157237.17-157237.111" - wire $and$libresoc.v:157237$8312_Y + attribute \src "libresoc.v:158545.17-158545.111" + wire $and$libresoc.v:158545$8296_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323638,7 +295008,7 @@ module \n$82 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157237$8312 + cell $and $and$libresoc.v:158545$8296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323646,18 +295016,18 @@ module \n$82 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157237$8312_Y + connect \Y $and$libresoc.v:158545$8296_Y end - connect \$1 $and$libresoc.v:157237$8312_Y + connect \$1 $and$libresoc.v:158545$8296_Y connect \trigger \$1 end -attribute \src "libresoc.v:157243.1-157254.10" +attribute \src "libresoc.v:158551.1-158562.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.n" attribute \generator "nMigen" module \n$92 - attribute \src "libresoc.v:157252.17-157252.111" - wire $and$libresoc.v:157252$8313_Y + attribute \src "libresoc.v:158560.17-158560.111" + wire $and$libresoc.v:158560$8297_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323667,7 +295037,7 @@ module \n$92 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157252$8313 + cell $and $and$libresoc.v:158560$8297 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323675,18 +295045,18 @@ module \n$92 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157252$8313_Y + connect \Y $and$libresoc.v:158560$8297_Y end - connect \$1 $and$libresoc.v:157252$8313_Y + connect \$1 $and$libresoc.v:158560$8297_Y connect \trigger \$1 end -attribute \src "libresoc.v:157258.1-157269.10" +attribute \src "libresoc.v:158566.1-158577.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.n" attribute \generator "nMigen" module \n$94 - attribute \src "libresoc.v:157267.17-157267.111" - wire $and$libresoc.v:157267$8314_Y + attribute \src "libresoc.v:158575.17-158575.111" + wire $and$libresoc.v:158575$8298_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323696,7 +295066,7 @@ module \n$94 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157267$8314 + cell $and $and$libresoc.v:158575$8298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323704,18 +295074,18 @@ module \n$94 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157267$8314_Y + connect \Y $and$libresoc.v:158575$8298_Y end - connect \$1 $and$libresoc.v:157267$8314_Y + connect \$1 $and$libresoc.v:158575$8298_Y connect \trigger \$1 end -attribute \src "libresoc.v:157273.1-157284.10" +attribute \src "libresoc.v:158581.1-158592.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.n" attribute \generator "nMigen" module \n$97 - attribute \src "libresoc.v:157282.17-157282.111" - wire $and$libresoc.v:157282$8315_Y + attribute \src "libresoc.v:158590.17-158590.111" + wire $and$libresoc.v:158590$8299_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323725,7 +295095,7 @@ module \n$97 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157282$8315 + cell $and $and$libresoc.v:158590$8299 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323733,18 +295103,18 @@ module \n$97 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157282$8315_Y + connect \Y $and$libresoc.v:158590$8299_Y end - connect \$1 $and$libresoc.v:157282$8315_Y + connect \$1 $and$libresoc.v:158590$8299_Y connect \trigger \$1 end -attribute \src "libresoc.v:157288.1-157299.10" +attribute \src "libresoc.v:158596.1-158607.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.n" attribute \generator "nMigen" module \n$99 - attribute \src "libresoc.v:157297.17-157297.111" - wire $and$libresoc.v:157297$8316_Y + attribute \src "libresoc.v:158605.17-158605.111" + wire $and$libresoc.v:158605$8300_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:253" @@ -323754,7 +295124,7 @@ module \n$99 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:257" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:304" - cell $and $and$libresoc.v:157297$8316 + cell $and $and$libresoc.v:158605$8300 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323762,42 +295132,42 @@ module \n$99 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:157297$8316_Y + connect \Y $and$libresoc.v:158605$8300_Y end - connect \$1 $and$libresoc.v:157297$8316_Y + connect \$1 $and$libresoc.v:158605$8300_Y connect \trigger \$1 end -attribute \src "libresoc.v:157303.1-157361.10" +attribute \src "libresoc.v:158611.1-158669.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.opc_l" attribute \generator "nMigen" module \opc_l - attribute \src "libresoc.v:157304.7-157304.20" + attribute \src "libresoc.v:158612.7-158612.20" wire $0\initial[0:0] - attribute \src "libresoc.v:157349.3-157357.6" - wire $0\q_int$next[0:0]$8327 - attribute \src "libresoc.v:157347.3-157348.27" + attribute \src "libresoc.v:158657.3-158665.6" + wire $0\q_int$next[0:0]$8311 + attribute \src "libresoc.v:158655.3-158656.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:157349.3-157357.6" - wire $1\q_int$next[0:0]$8328 - attribute \src "libresoc.v:157326.7-157326.19" + attribute \src "libresoc.v:158657.3-158665.6" + wire $1\q_int$next[0:0]$8312 + attribute \src "libresoc.v:158634.7-158634.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:157339.17-157339.96" - wire $and$libresoc.v:157339$8317_Y - attribute \src "libresoc.v:157344.17-157344.96" - wire $and$libresoc.v:157344$8322_Y - attribute \src "libresoc.v:157341.18-157341.93" - wire $not$libresoc.v:157341$8319_Y - attribute \src "libresoc.v:157343.17-157343.92" - wire $not$libresoc.v:157343$8321_Y - attribute \src "libresoc.v:157346.17-157346.92" - wire $not$libresoc.v:157346$8324_Y - attribute \src "libresoc.v:157340.18-157340.98" - wire $or$libresoc.v:157340$8318_Y - attribute \src "libresoc.v:157342.18-157342.99" - wire $or$libresoc.v:157342$8320_Y - attribute \src "libresoc.v:157345.17-157345.97" - wire $or$libresoc.v:157345$8323_Y + attribute \src "libresoc.v:158647.17-158647.96" + wire $and$libresoc.v:158647$8301_Y + attribute \src "libresoc.v:158652.17-158652.96" + wire $and$libresoc.v:158652$8306_Y + attribute \src "libresoc.v:158649.18-158649.93" + wire $not$libresoc.v:158649$8303_Y + attribute \src "libresoc.v:158651.17-158651.92" + wire $not$libresoc.v:158651$8305_Y + attribute \src "libresoc.v:158654.17-158654.92" + wire $not$libresoc.v:158654$8308_Y + attribute \src "libresoc.v:158648.18-158648.98" + wire $or$libresoc.v:158648$8302_Y + attribute \src "libresoc.v:158650.18-158650.99" + wire $or$libresoc.v:158650$8304_Y + attribute \src "libresoc.v:158653.17-158653.97" + wire $or$libresoc.v:158653$8307_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -323814,11 +295184,11 @@ module \opc_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:157304.7-157304.15" + attribute \src "libresoc.v:158612.7-158612.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -323835,7 +295205,7 @@ module \opc_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:157339$8317 + cell $and $and$libresoc.v:158647$8301 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323843,10 +295213,10 @@ module \opc_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:157339$8317_Y + connect \Y $and$libresoc.v:158647$8301_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:157344$8322 + cell $and $and$libresoc.v:158652$8306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323854,34 +295224,34 @@ module \opc_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:157344$8322_Y + connect \Y $and$libresoc.v:158652$8306_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:157341$8319 + cell $not $not$libresoc.v:158649$8303 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:157341$8319_Y + connect \Y $not$libresoc.v:158649$8303_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:157343$8321 + cell $not $not$libresoc.v:158651$8305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157343$8321_Y + connect \Y $not$libresoc.v:158651$8305_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:157346$8324 + cell $not $not$libresoc.v:158654$8308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157346$8324_Y + connect \Y $not$libresoc.v:158654$8308_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:157340$8318 + cell $or $or$libresoc.v:158648$8302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323889,10 +295259,10 @@ module \opc_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:157340$8318_Y + connect \Y $or$libresoc.v:158648$8302_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:157342$8320 + cell $or $or$libresoc.v:158650$8304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323900,10 +295270,10 @@ module \opc_l parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:157342$8320_Y + connect \Y $or$libresoc.v:158650$8304_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:157345$8323 + cell $or $or$libresoc.v:158653$8307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -323911,39 +295281,39 @@ module \opc_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:157345$8323_Y + connect \Y $or$libresoc.v:158653$8307_Y end - attribute \src "libresoc.v:157304.7-157304.20" - process $proc$libresoc.v:157304$8329 + attribute \src "libresoc.v:158612.7-158612.20" + process $proc$libresoc.v:158612$8313 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:157326.7-157326.19" - process $proc$libresoc.v:157326$8330 + attribute \src "libresoc.v:158634.7-158634.19" + process $proc$libresoc.v:158634$8314 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:157347.3-157348.27" - process $proc$libresoc.v:157347$8325 + attribute \src "libresoc.v:158655.3-158656.27" + process $proc$libresoc.v:158655$8309 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:157349.3-157357.6" - process $proc$libresoc.v:157349$8326 + attribute \src "libresoc.v:158657.3-158665.6" + process $proc$libresoc.v:158657$8310 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8327 $1\q_int$next[0:0]$8328 - attribute \src "libresoc.v:157350.5-157350.29" + assign $0\q_int$next[0:0]$8311 $1\q_int$next[0:0]$8312 + attribute \src "libresoc.v:158658.5-158658.29" switch \initial - attribute \src "libresoc.v:157350.9-157350.17" + attribute \src "libresoc.v:158658.9-158658.17" case 1'1 case end @@ -323952,56 +295322,56 @@ module \opc_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8328 1'0 + assign $1\q_int$next[0:0]$8312 1'0 case - assign $1\q_int$next[0:0]$8328 \$5 + assign $1\q_int$next[0:0]$8312 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8327 + update \q_int$next $0\q_int$next[0:0]$8311 end - connect \$9 $and$libresoc.v:157339$8317_Y - connect \$11 $or$libresoc.v:157340$8318_Y - connect \$13 $not$libresoc.v:157341$8319_Y - connect \$15 $or$libresoc.v:157342$8320_Y - connect \$1 $not$libresoc.v:157343$8321_Y - connect \$3 $and$libresoc.v:157344$8322_Y - connect \$5 $or$libresoc.v:157345$8323_Y - connect \$7 $not$libresoc.v:157346$8324_Y + connect \$9 $and$libresoc.v:158647$8301_Y + connect \$11 $or$libresoc.v:158648$8302_Y + connect \$13 $not$libresoc.v:158649$8303_Y + connect \$15 $or$libresoc.v:158650$8304_Y + connect \$1 $not$libresoc.v:158651$8305_Y + connect \$3 $and$libresoc.v:158652$8306_Y + connect \$5 $or$libresoc.v:158653$8307_Y + connect \$7 $not$libresoc.v:158654$8308_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:157365.1-157423.10" +attribute \src "libresoc.v:158673.1-158731.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.opc_l" attribute \generator "nMigen" module \opc_l$102 - attribute \src "libresoc.v:157366.7-157366.20" + attribute \src "libresoc.v:158674.7-158674.20" wire $0\initial[0:0] - attribute \src "libresoc.v:157411.3-157419.6" - wire $0\q_int$next[0:0]$8341 - attribute \src "libresoc.v:157409.3-157410.27" + attribute \src "libresoc.v:158719.3-158727.6" + wire $0\q_int$next[0:0]$8325 + attribute \src "libresoc.v:158717.3-158718.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:157411.3-157419.6" - wire $1\q_int$next[0:0]$8342 - attribute \src "libresoc.v:157388.7-157388.19" + attribute \src "libresoc.v:158719.3-158727.6" + wire $1\q_int$next[0:0]$8326 + attribute \src "libresoc.v:158696.7-158696.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:157401.17-157401.96" - wire $and$libresoc.v:157401$8331_Y - attribute \src "libresoc.v:157406.17-157406.96" - wire $and$libresoc.v:157406$8336_Y - attribute \src "libresoc.v:157403.18-157403.93" - wire $not$libresoc.v:157403$8333_Y - attribute \src "libresoc.v:157405.17-157405.92" - wire $not$libresoc.v:157405$8335_Y - attribute \src "libresoc.v:157408.17-157408.92" - wire $not$libresoc.v:157408$8338_Y - attribute \src "libresoc.v:157402.18-157402.98" - wire $or$libresoc.v:157402$8332_Y - attribute \src "libresoc.v:157404.18-157404.99" - wire $or$libresoc.v:157404$8334_Y - attribute \src "libresoc.v:157407.17-157407.97" - wire $or$libresoc.v:157407$8337_Y + attribute \src "libresoc.v:158709.17-158709.96" + wire $and$libresoc.v:158709$8315_Y + attribute \src "libresoc.v:158714.17-158714.96" + wire $and$libresoc.v:158714$8320_Y + attribute \src "libresoc.v:158711.18-158711.93" + wire $not$libresoc.v:158711$8317_Y + attribute \src "libresoc.v:158713.17-158713.92" + wire $not$libresoc.v:158713$8319_Y + attribute \src "libresoc.v:158716.17-158716.92" + wire $not$libresoc.v:158716$8322_Y + attribute \src "libresoc.v:158710.18-158710.98" + wire $or$libresoc.v:158710$8316_Y + attribute \src "libresoc.v:158712.18-158712.99" + wire $or$libresoc.v:158712$8318_Y + attribute \src "libresoc.v:158715.17-158715.97" + wire $or$libresoc.v:158715$8321_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -324018,11 +295388,11 @@ module \opc_l$102 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:157366.7-157366.15" + attribute \src "libresoc.v:158674.7-158674.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -324039,7 +295409,7 @@ module \opc_l$102 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:157401$8331 + cell $and $and$libresoc.v:158709$8315 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324047,10 +295417,10 @@ module \opc_l$102 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:157401$8331_Y + connect \Y $and$libresoc.v:158709$8315_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:157406$8336 + cell $and $and$libresoc.v:158714$8320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324058,34 +295428,34 @@ module \opc_l$102 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:157406$8336_Y + connect \Y $and$libresoc.v:158714$8320_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:157403$8333 + cell $not $not$libresoc.v:158711$8317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:157403$8333_Y + connect \Y $not$libresoc.v:158711$8317_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:157405$8335 + cell $not $not$libresoc.v:158713$8319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157405$8335_Y + connect \Y $not$libresoc.v:158713$8319_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:157408$8338 + cell $not $not$libresoc.v:158716$8322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157408$8338_Y + connect \Y $not$libresoc.v:158716$8322_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:157402$8332 + cell $or $or$libresoc.v:158710$8316 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324093,10 +295463,10 @@ module \opc_l$102 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:157402$8332_Y + connect \Y $or$libresoc.v:158710$8316_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:157404$8334 + cell $or $or$libresoc.v:158712$8318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324104,10 +295474,10 @@ module \opc_l$102 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:157404$8334_Y + connect \Y $or$libresoc.v:158712$8318_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:157407$8337 + cell $or $or$libresoc.v:158715$8321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324115,39 +295485,39 @@ module \opc_l$102 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:157407$8337_Y + connect \Y $or$libresoc.v:158715$8321_Y end - attribute \src "libresoc.v:157366.7-157366.20" - process $proc$libresoc.v:157366$8343 + attribute \src "libresoc.v:158674.7-158674.20" + process $proc$libresoc.v:158674$8327 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:157388.7-157388.19" - process $proc$libresoc.v:157388$8344 + attribute \src "libresoc.v:158696.7-158696.19" + process $proc$libresoc.v:158696$8328 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:157409.3-157410.27" - process $proc$libresoc.v:157409$8339 + attribute \src "libresoc.v:158717.3-158718.27" + process $proc$libresoc.v:158717$8323 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:157411.3-157419.6" - process $proc$libresoc.v:157411$8340 + attribute \src "libresoc.v:158719.3-158727.6" + process $proc$libresoc.v:158719$8324 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8341 $1\q_int$next[0:0]$8342 - attribute \src "libresoc.v:157412.5-157412.29" + assign $0\q_int$next[0:0]$8325 $1\q_int$next[0:0]$8326 + attribute \src "libresoc.v:158720.5-158720.29" switch \initial - attribute \src "libresoc.v:157412.9-157412.17" + attribute \src "libresoc.v:158720.9-158720.17" case 1'1 case end @@ -324156,56 +295526,56 @@ module \opc_l$102 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8342 1'0 + assign $1\q_int$next[0:0]$8326 1'0 case - assign $1\q_int$next[0:0]$8342 \$5 + assign $1\q_int$next[0:0]$8326 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8341 + update \q_int$next $0\q_int$next[0:0]$8325 end - connect \$9 $and$libresoc.v:157401$8331_Y - connect \$11 $or$libresoc.v:157402$8332_Y - connect \$13 $not$libresoc.v:157403$8333_Y - connect \$15 $or$libresoc.v:157404$8334_Y - connect \$1 $not$libresoc.v:157405$8335_Y - connect \$3 $and$libresoc.v:157406$8336_Y - connect \$5 $or$libresoc.v:157407$8337_Y - connect \$7 $not$libresoc.v:157408$8338_Y + connect \$9 $and$libresoc.v:158709$8315_Y + connect \$11 $or$libresoc.v:158710$8316_Y + connect \$13 $not$libresoc.v:158711$8317_Y + connect \$15 $or$libresoc.v:158712$8318_Y + connect \$1 $not$libresoc.v:158713$8319_Y + connect \$3 $and$libresoc.v:158714$8320_Y + connect \$5 $or$libresoc.v:158715$8321_Y + connect \$7 $not$libresoc.v:158716$8322_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:157427.1-157485.10" +attribute \src "libresoc.v:158735.1-158793.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.opc_l" attribute \generator "nMigen" module \opc_l$11 - attribute \src "libresoc.v:157428.7-157428.20" + attribute \src "libresoc.v:158736.7-158736.20" wire $0\initial[0:0] - attribute \src "libresoc.v:157473.3-157481.6" - wire $0\q_int$next[0:0]$8355 - attribute \src "libresoc.v:157471.3-157472.27" + attribute \src "libresoc.v:158781.3-158789.6" + wire $0\q_int$next[0:0]$8339 + attribute \src "libresoc.v:158779.3-158780.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:157473.3-157481.6" - wire $1\q_int$next[0:0]$8356 - attribute \src "libresoc.v:157450.7-157450.19" + attribute \src "libresoc.v:158781.3-158789.6" + wire $1\q_int$next[0:0]$8340 + attribute \src "libresoc.v:158758.7-158758.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:157463.17-157463.96" - wire $and$libresoc.v:157463$8345_Y - attribute \src "libresoc.v:157468.17-157468.96" - wire $and$libresoc.v:157468$8350_Y - attribute \src "libresoc.v:157465.18-157465.93" - wire $not$libresoc.v:157465$8347_Y - attribute \src "libresoc.v:157467.17-157467.92" - wire $not$libresoc.v:157467$8349_Y - attribute \src "libresoc.v:157470.17-157470.92" - wire $not$libresoc.v:157470$8352_Y - attribute \src "libresoc.v:157464.18-157464.98" - wire $or$libresoc.v:157464$8346_Y - attribute \src "libresoc.v:157466.18-157466.99" - wire $or$libresoc.v:157466$8348_Y - attribute \src "libresoc.v:157469.17-157469.97" - wire $or$libresoc.v:157469$8351_Y + attribute \src "libresoc.v:158771.17-158771.96" + wire $and$libresoc.v:158771$8329_Y + attribute \src "libresoc.v:158776.17-158776.96" + wire $and$libresoc.v:158776$8334_Y + attribute \src "libresoc.v:158773.18-158773.93" + wire $not$libresoc.v:158773$8331_Y + attribute \src "libresoc.v:158775.17-158775.92" + wire $not$libresoc.v:158775$8333_Y + attribute \src "libresoc.v:158778.17-158778.92" + wire $not$libresoc.v:158778$8336_Y + attribute \src "libresoc.v:158772.18-158772.98" + wire $or$libresoc.v:158772$8330_Y + attribute \src "libresoc.v:158774.18-158774.99" + wire $or$libresoc.v:158774$8332_Y + attribute \src "libresoc.v:158777.17-158777.97" + wire $or$libresoc.v:158777$8335_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -324222,11 +295592,11 @@ module \opc_l$11 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:157428.7-157428.15" + attribute \src "libresoc.v:158736.7-158736.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -324243,7 +295613,7 @@ module \opc_l$11 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:157463$8345 + cell $and $and$libresoc.v:158771$8329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324251,10 +295621,10 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:157463$8345_Y + connect \Y $and$libresoc.v:158771$8329_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:157468$8350 + cell $and $and$libresoc.v:158776$8334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324262,34 +295632,34 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:157468$8350_Y + connect \Y $and$libresoc.v:158776$8334_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:157465$8347 + cell $not $not$libresoc.v:158773$8331 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:157465$8347_Y + connect \Y $not$libresoc.v:158773$8331_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:157467$8349 + cell $not $not$libresoc.v:158775$8333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157467$8349_Y + connect \Y $not$libresoc.v:158775$8333_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:157470$8352 + cell $not $not$libresoc.v:158778$8336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157470$8352_Y + connect \Y $not$libresoc.v:158778$8336_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:157464$8346 + cell $or $or$libresoc.v:158772$8330 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324297,10 +295667,10 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:157464$8346_Y + connect \Y $or$libresoc.v:158772$8330_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:157466$8348 + cell $or $or$libresoc.v:158774$8332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324308,10 +295678,10 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:157466$8348_Y + connect \Y $or$libresoc.v:158774$8332_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:157469$8351 + cell $or $or$libresoc.v:158777$8335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324319,39 +295689,39 @@ module \opc_l$11 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:157469$8351_Y + connect \Y $or$libresoc.v:158777$8335_Y end - attribute \src "libresoc.v:157428.7-157428.20" - process $proc$libresoc.v:157428$8357 + attribute \src "libresoc.v:158736.7-158736.20" + process $proc$libresoc.v:158736$8341 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:157450.7-157450.19" - process $proc$libresoc.v:157450$8358 + attribute \src "libresoc.v:158758.7-158758.19" + process $proc$libresoc.v:158758$8342 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:157471.3-157472.27" - process $proc$libresoc.v:157471$8353 + attribute \src "libresoc.v:158779.3-158780.27" + process $proc$libresoc.v:158779$8337 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:157473.3-157481.6" - process $proc$libresoc.v:157473$8354 + attribute \src "libresoc.v:158781.3-158789.6" + process $proc$libresoc.v:158781$8338 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8355 $1\q_int$next[0:0]$8356 - attribute \src "libresoc.v:157474.5-157474.29" + assign $0\q_int$next[0:0]$8339 $1\q_int$next[0:0]$8340 + attribute \src "libresoc.v:158782.5-158782.29" switch \initial - attribute \src "libresoc.v:157474.9-157474.17" + attribute \src "libresoc.v:158782.9-158782.17" case 1'1 case end @@ -324360,56 +295730,56 @@ module \opc_l$11 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8356 1'0 + assign $1\q_int$next[0:0]$8340 1'0 case - assign $1\q_int$next[0:0]$8356 \$5 + assign $1\q_int$next[0:0]$8340 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8355 + update \q_int$next $0\q_int$next[0:0]$8339 end - connect \$9 $and$libresoc.v:157463$8345_Y - connect \$11 $or$libresoc.v:157464$8346_Y - connect \$13 $not$libresoc.v:157465$8347_Y - connect \$15 $or$libresoc.v:157466$8348_Y - connect \$1 $not$libresoc.v:157467$8349_Y - connect \$3 $and$libresoc.v:157468$8350_Y - connect \$5 $or$libresoc.v:157469$8351_Y - connect \$7 $not$libresoc.v:157470$8352_Y + connect \$9 $and$libresoc.v:158771$8329_Y + connect \$11 $or$libresoc.v:158772$8330_Y + connect \$13 $not$libresoc.v:158773$8331_Y + connect \$15 $or$libresoc.v:158774$8332_Y + connect \$1 $not$libresoc.v:158775$8333_Y + connect \$3 $and$libresoc.v:158776$8334_Y + connect \$5 $or$libresoc.v:158777$8335_Y + connect \$7 $not$libresoc.v:158778$8336_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:157489.1-157547.10" +attribute \src "libresoc.v:158797.1-158855.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.opc_l" attribute \generator "nMigen" module \opc_l$120 - attribute \src "libresoc.v:157490.7-157490.20" + attribute \src "libresoc.v:158798.7-158798.20" wire $0\initial[0:0] - attribute \src "libresoc.v:157535.3-157543.6" - wire $0\q_int$next[0:0]$8369 - attribute \src "libresoc.v:157533.3-157534.27" + attribute \src "libresoc.v:158843.3-158851.6" + wire $0\q_int$next[0:0]$8353 + attribute \src "libresoc.v:158841.3-158842.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:157535.3-157543.6" - wire $1\q_int$next[0:0]$8370 - attribute \src "libresoc.v:157512.7-157512.19" + attribute \src "libresoc.v:158843.3-158851.6" + wire $1\q_int$next[0:0]$8354 + attribute \src "libresoc.v:158820.7-158820.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:157525.17-157525.96" - wire $and$libresoc.v:157525$8359_Y - attribute \src "libresoc.v:157530.17-157530.96" - wire $and$libresoc.v:157530$8364_Y - attribute \src "libresoc.v:157527.18-157527.93" - wire $not$libresoc.v:157527$8361_Y - attribute \src "libresoc.v:157529.17-157529.92" - wire $not$libresoc.v:157529$8363_Y - attribute \src "libresoc.v:157532.17-157532.92" - wire $not$libresoc.v:157532$8366_Y - attribute \src "libresoc.v:157526.18-157526.98" - wire $or$libresoc.v:157526$8360_Y - attribute \src "libresoc.v:157528.18-157528.99" - wire $or$libresoc.v:157528$8362_Y - attribute \src "libresoc.v:157531.17-157531.97" - wire $or$libresoc.v:157531$8365_Y + attribute \src "libresoc.v:158833.17-158833.96" + wire $and$libresoc.v:158833$8343_Y + attribute \src "libresoc.v:158838.17-158838.96" + wire $and$libresoc.v:158838$8348_Y + attribute \src "libresoc.v:158835.18-158835.93" + wire $not$libresoc.v:158835$8345_Y + attribute \src "libresoc.v:158837.17-158837.92" + wire $not$libresoc.v:158837$8347_Y + attribute \src "libresoc.v:158840.17-158840.92" + wire $not$libresoc.v:158840$8350_Y + attribute \src "libresoc.v:158834.18-158834.98" + wire $or$libresoc.v:158834$8344_Y + attribute \src "libresoc.v:158836.18-158836.99" + wire $or$libresoc.v:158836$8346_Y + attribute \src "libresoc.v:158839.17-158839.97" + wire $or$libresoc.v:158839$8349_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -324426,11 +295796,11 @@ module \opc_l$120 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:157490.7-157490.15" + attribute \src "libresoc.v:158798.7-158798.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -324447,7 +295817,7 @@ module \opc_l$120 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:157525$8359 + cell $and $and$libresoc.v:158833$8343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324455,10 +295825,10 @@ module \opc_l$120 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:157525$8359_Y + connect \Y $and$libresoc.v:158833$8343_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:157530$8364 + cell $and $and$libresoc.v:158838$8348 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324466,34 +295836,34 @@ module \opc_l$120 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:157530$8364_Y + connect \Y $and$libresoc.v:158838$8348_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:157527$8361 + cell $not $not$libresoc.v:158835$8345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:157527$8361_Y + connect \Y $not$libresoc.v:158835$8345_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:157529$8363 + cell $not $not$libresoc.v:158837$8347 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157529$8363_Y + connect \Y $not$libresoc.v:158837$8347_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:157532$8366 + cell $not $not$libresoc.v:158840$8350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157532$8366_Y + connect \Y $not$libresoc.v:158840$8350_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:157526$8360 + cell $or $or$libresoc.v:158834$8344 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324501,10 +295871,10 @@ module \opc_l$120 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:157526$8360_Y + connect \Y $or$libresoc.v:158834$8344_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:157528$8362 + cell $or $or$libresoc.v:158836$8346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324512,10 +295882,10 @@ module \opc_l$120 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:157528$8362_Y + connect \Y $or$libresoc.v:158836$8346_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:157531$8365 + cell $or $or$libresoc.v:158839$8349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324523,39 +295893,39 @@ module \opc_l$120 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:157531$8365_Y + connect \Y $or$libresoc.v:158839$8349_Y end - attribute \src "libresoc.v:157490.7-157490.20" - process $proc$libresoc.v:157490$8371 + attribute \src "libresoc.v:158798.7-158798.20" + process $proc$libresoc.v:158798$8355 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:157512.7-157512.19" - process $proc$libresoc.v:157512$8372 + attribute \src "libresoc.v:158820.7-158820.19" + process $proc$libresoc.v:158820$8356 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:157533.3-157534.27" - process $proc$libresoc.v:157533$8367 + attribute \src "libresoc.v:158841.3-158842.27" + process $proc$libresoc.v:158841$8351 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:157535.3-157543.6" - process $proc$libresoc.v:157535$8368 + attribute \src "libresoc.v:158843.3-158851.6" + process $proc$libresoc.v:158843$8352 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8369 $1\q_int$next[0:0]$8370 - attribute \src "libresoc.v:157536.5-157536.29" + assign $0\q_int$next[0:0]$8353 $1\q_int$next[0:0]$8354 + attribute \src "libresoc.v:158844.5-158844.29" switch \initial - attribute \src "libresoc.v:157536.9-157536.17" + attribute \src "libresoc.v:158844.9-158844.17" case 1'1 case end @@ -324564,56 +295934,56 @@ module \opc_l$120 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8370 1'0 + assign $1\q_int$next[0:0]$8354 1'0 case - assign $1\q_int$next[0:0]$8370 \$5 + assign $1\q_int$next[0:0]$8354 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8369 + update \q_int$next $0\q_int$next[0:0]$8353 end - connect \$9 $and$libresoc.v:157525$8359_Y - connect \$11 $or$libresoc.v:157526$8360_Y - connect \$13 $not$libresoc.v:157527$8361_Y - connect \$15 $or$libresoc.v:157528$8362_Y - connect \$1 $not$libresoc.v:157529$8363_Y - connect \$3 $and$libresoc.v:157530$8364_Y - connect \$5 $or$libresoc.v:157531$8365_Y - connect \$7 $not$libresoc.v:157532$8366_Y + connect \$9 $and$libresoc.v:158833$8343_Y + connect \$11 $or$libresoc.v:158834$8344_Y + connect \$13 $not$libresoc.v:158835$8345_Y + connect \$15 $or$libresoc.v:158836$8346_Y + connect \$1 $not$libresoc.v:158837$8347_Y + connect \$3 $and$libresoc.v:158838$8348_Y + connect \$5 $or$libresoc.v:158839$8349_Y + connect \$7 $not$libresoc.v:158840$8350_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:157551.1-157609.10" +attribute \src "libresoc.v:158859.1-158917.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.opc_l" attribute \generator "nMigen" module \opc_l$126 - attribute \src "libresoc.v:157552.7-157552.20" + attribute \src "libresoc.v:158860.7-158860.20" wire $0\initial[0:0] - attribute \src "libresoc.v:157597.3-157605.6" - wire $0\q_int$next[0:0]$8383 - attribute \src "libresoc.v:157595.3-157596.27" + attribute \src "libresoc.v:158905.3-158913.6" + wire $0\q_int$next[0:0]$8367 + attribute \src "libresoc.v:158903.3-158904.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:157597.3-157605.6" - wire $1\q_int$next[0:0]$8384 - attribute \src "libresoc.v:157574.7-157574.19" + attribute \src "libresoc.v:158905.3-158913.6" + wire $1\q_int$next[0:0]$8368 + attribute \src "libresoc.v:158882.7-158882.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:157587.17-157587.96" - wire $and$libresoc.v:157587$8373_Y - attribute \src "libresoc.v:157592.17-157592.96" - wire $and$libresoc.v:157592$8378_Y - attribute \src "libresoc.v:157589.18-157589.93" - wire $not$libresoc.v:157589$8375_Y - attribute \src "libresoc.v:157591.17-157591.92" - wire $not$libresoc.v:157591$8377_Y - attribute \src "libresoc.v:157594.17-157594.92" - wire $not$libresoc.v:157594$8380_Y - attribute \src "libresoc.v:157588.18-157588.98" - wire $or$libresoc.v:157588$8374_Y - attribute \src "libresoc.v:157590.18-157590.99" - wire $or$libresoc.v:157590$8376_Y - attribute \src "libresoc.v:157593.17-157593.97" - wire $or$libresoc.v:157593$8379_Y + attribute \src "libresoc.v:158895.17-158895.96" + wire $and$libresoc.v:158895$8357_Y + attribute \src "libresoc.v:158900.17-158900.96" + wire $and$libresoc.v:158900$8362_Y + attribute \src "libresoc.v:158897.18-158897.93" + wire $not$libresoc.v:158897$8359_Y + attribute \src "libresoc.v:158899.17-158899.92" + wire $not$libresoc.v:158899$8361_Y + attribute \src "libresoc.v:158902.17-158902.92" + wire $not$libresoc.v:158902$8364_Y + attribute \src "libresoc.v:158896.18-158896.98" + wire $or$libresoc.v:158896$8358_Y + attribute \src "libresoc.v:158898.18-158898.99" + wire $or$libresoc.v:158898$8360_Y + attribute \src "libresoc.v:158901.17-158901.97" + wire $or$libresoc.v:158901$8363_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -324630,11 +296000,11 @@ module \opc_l$126 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:157552.7-157552.15" + attribute \src "libresoc.v:158860.7-158860.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -324651,7 +296021,7 @@ module \opc_l$126 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:157587$8373 + cell $and $and$libresoc.v:158895$8357 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324659,10 +296029,10 @@ module \opc_l$126 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:157587$8373_Y + connect \Y $and$libresoc.v:158895$8357_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:157592$8378 + cell $and $and$libresoc.v:158900$8362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324670,34 +296040,34 @@ module \opc_l$126 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:157592$8378_Y + connect \Y $and$libresoc.v:158900$8362_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:157589$8375 + cell $not $not$libresoc.v:158897$8359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:157589$8375_Y + connect \Y $not$libresoc.v:158897$8359_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:157591$8377 + cell $not $not$libresoc.v:158899$8361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157591$8377_Y + connect \Y $not$libresoc.v:158899$8361_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:157594$8380 + cell $not $not$libresoc.v:158902$8364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157594$8380_Y + connect \Y $not$libresoc.v:158902$8364_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:157588$8374 + cell $or $or$libresoc.v:158896$8358 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324705,10 +296075,10 @@ module \opc_l$126 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:157588$8374_Y + connect \Y $or$libresoc.v:158896$8358_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:157590$8376 + cell $or $or$libresoc.v:158898$8360 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324716,10 +296086,10 @@ module \opc_l$126 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:157590$8376_Y + connect \Y $or$libresoc.v:158898$8360_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:157593$8379 + cell $or $or$libresoc.v:158901$8363 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324727,39 +296097,39 @@ module \opc_l$126 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:157593$8379_Y + connect \Y $or$libresoc.v:158901$8363_Y end - attribute \src "libresoc.v:157552.7-157552.20" - process $proc$libresoc.v:157552$8385 + attribute \src "libresoc.v:158860.7-158860.20" + process $proc$libresoc.v:158860$8369 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:157574.7-157574.19" - process $proc$libresoc.v:157574$8386 + attribute \src "libresoc.v:158882.7-158882.19" + process $proc$libresoc.v:158882$8370 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:157595.3-157596.27" - process $proc$libresoc.v:157595$8381 + attribute \src "libresoc.v:158903.3-158904.27" + process $proc$libresoc.v:158903$8365 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:157597.3-157605.6" - process $proc$libresoc.v:157597$8382 + attribute \src "libresoc.v:158905.3-158913.6" + process $proc$libresoc.v:158905$8366 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8383 $1\q_int$next[0:0]$8384 - attribute \src "libresoc.v:157598.5-157598.29" + assign $0\q_int$next[0:0]$8367 $1\q_int$next[0:0]$8368 + attribute \src "libresoc.v:158906.5-158906.29" switch \initial - attribute \src "libresoc.v:157598.9-157598.17" + attribute \src "libresoc.v:158906.9-158906.17" case 1'1 case end @@ -324768,56 +296138,56 @@ module \opc_l$126 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8384 1'0 + assign $1\q_int$next[0:0]$8368 1'0 case - assign $1\q_int$next[0:0]$8384 \$5 + assign $1\q_int$next[0:0]$8368 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8383 + update \q_int$next $0\q_int$next[0:0]$8367 end - connect \$9 $and$libresoc.v:157587$8373_Y - connect \$11 $or$libresoc.v:157588$8374_Y - connect \$13 $not$libresoc.v:157589$8375_Y - connect \$15 $or$libresoc.v:157590$8376_Y - connect \$1 $not$libresoc.v:157591$8377_Y - connect \$3 $and$libresoc.v:157592$8378_Y - connect \$5 $or$libresoc.v:157593$8379_Y - connect \$7 $not$libresoc.v:157594$8380_Y + connect \$9 $and$libresoc.v:158895$8357_Y + connect \$11 $or$libresoc.v:158896$8358_Y + connect \$13 $not$libresoc.v:158897$8359_Y + connect \$15 $or$libresoc.v:158898$8360_Y + connect \$1 $not$libresoc.v:158899$8361_Y + connect \$3 $and$libresoc.v:158900$8362_Y + connect \$5 $or$libresoc.v:158901$8363_Y + connect \$7 $not$libresoc.v:158902$8364_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:157613.1-157671.10" +attribute \src "libresoc.v:158921.1-158979.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.opc_l" attribute \generator "nMigen" module \opc_l$24 - attribute \src "libresoc.v:157614.7-157614.20" + attribute \src "libresoc.v:158922.7-158922.20" wire $0\initial[0:0] - attribute \src "libresoc.v:157659.3-157667.6" - wire $0\q_int$next[0:0]$8397 - attribute \src "libresoc.v:157657.3-157658.27" + attribute \src "libresoc.v:158967.3-158975.6" + wire $0\q_int$next[0:0]$8381 + attribute \src "libresoc.v:158965.3-158966.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:157659.3-157667.6" - wire $1\q_int$next[0:0]$8398 - attribute \src "libresoc.v:157636.7-157636.19" + attribute \src "libresoc.v:158967.3-158975.6" + wire $1\q_int$next[0:0]$8382 + attribute \src "libresoc.v:158944.7-158944.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:157649.17-157649.96" - wire $and$libresoc.v:157649$8387_Y - attribute \src "libresoc.v:157654.17-157654.96" - wire $and$libresoc.v:157654$8392_Y - attribute \src "libresoc.v:157651.18-157651.93" - wire $not$libresoc.v:157651$8389_Y - attribute \src "libresoc.v:157653.17-157653.92" - wire $not$libresoc.v:157653$8391_Y - attribute \src "libresoc.v:157656.17-157656.92" - wire $not$libresoc.v:157656$8394_Y - attribute \src "libresoc.v:157650.18-157650.98" - wire $or$libresoc.v:157650$8388_Y - attribute \src "libresoc.v:157652.18-157652.99" - wire $or$libresoc.v:157652$8390_Y - attribute \src "libresoc.v:157655.17-157655.97" - wire $or$libresoc.v:157655$8393_Y + attribute \src "libresoc.v:158957.17-158957.96" + wire $and$libresoc.v:158957$8371_Y + attribute \src "libresoc.v:158962.17-158962.96" + wire $and$libresoc.v:158962$8376_Y + attribute \src "libresoc.v:158959.18-158959.93" + wire $not$libresoc.v:158959$8373_Y + attribute \src "libresoc.v:158961.17-158961.92" + wire $not$libresoc.v:158961$8375_Y + attribute \src "libresoc.v:158964.17-158964.92" + wire $not$libresoc.v:158964$8378_Y + attribute \src "libresoc.v:158958.18-158958.98" + wire $or$libresoc.v:158958$8372_Y + attribute \src "libresoc.v:158960.18-158960.99" + wire $or$libresoc.v:158960$8374_Y + attribute \src "libresoc.v:158963.17-158963.97" + wire $or$libresoc.v:158963$8377_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -324834,11 +296204,11 @@ module \opc_l$24 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:157614.7-157614.15" + attribute \src "libresoc.v:158922.7-158922.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -324855,7 +296225,7 @@ module \opc_l$24 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:157649$8387 + cell $and $and$libresoc.v:158957$8371 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324863,10 +296233,10 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:157649$8387_Y + connect \Y $and$libresoc.v:158957$8371_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:157654$8392 + cell $and $and$libresoc.v:158962$8376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324874,34 +296244,34 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:157654$8392_Y + connect \Y $and$libresoc.v:158962$8376_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:157651$8389 + cell $not $not$libresoc.v:158959$8373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:157651$8389_Y + connect \Y $not$libresoc.v:158959$8373_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:157653$8391 + cell $not $not$libresoc.v:158961$8375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157653$8391_Y + connect \Y $not$libresoc.v:158961$8375_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:157656$8394 + cell $not $not$libresoc.v:158964$8378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157656$8394_Y + connect \Y $not$libresoc.v:158964$8378_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:157650$8388 + cell $or $or$libresoc.v:158958$8372 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324909,10 +296279,10 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:157650$8388_Y + connect \Y $or$libresoc.v:158958$8372_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:157652$8390 + cell $or $or$libresoc.v:158960$8374 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324920,10 +296290,10 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:157652$8390_Y + connect \Y $or$libresoc.v:158960$8374_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:157655$8393 + cell $or $or$libresoc.v:158963$8377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -324931,39 +296301,39 @@ module \opc_l$24 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:157655$8393_Y + connect \Y $or$libresoc.v:158963$8377_Y end - attribute \src "libresoc.v:157614.7-157614.20" - process $proc$libresoc.v:157614$8399 + attribute \src "libresoc.v:158922.7-158922.20" + process $proc$libresoc.v:158922$8383 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:157636.7-157636.19" - process $proc$libresoc.v:157636$8400 + attribute \src "libresoc.v:158944.7-158944.19" + process $proc$libresoc.v:158944$8384 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:157657.3-157658.27" - process $proc$libresoc.v:157657$8395 + attribute \src "libresoc.v:158965.3-158966.27" + process $proc$libresoc.v:158965$8379 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:157659.3-157667.6" - process $proc$libresoc.v:157659$8396 + attribute \src "libresoc.v:158967.3-158975.6" + process $proc$libresoc.v:158967$8380 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8397 $1\q_int$next[0:0]$8398 - attribute \src "libresoc.v:157660.5-157660.29" + assign $0\q_int$next[0:0]$8381 $1\q_int$next[0:0]$8382 + attribute \src "libresoc.v:158968.5-158968.29" switch \initial - attribute \src "libresoc.v:157660.9-157660.17" + attribute \src "libresoc.v:158968.9-158968.17" case 1'1 case end @@ -324972,56 +296342,56 @@ module \opc_l$24 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8398 1'0 + assign $1\q_int$next[0:0]$8382 1'0 case - assign $1\q_int$next[0:0]$8398 \$5 + assign $1\q_int$next[0:0]$8382 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8397 + update \q_int$next $0\q_int$next[0:0]$8381 end - connect \$9 $and$libresoc.v:157649$8387_Y - connect \$11 $or$libresoc.v:157650$8388_Y - connect \$13 $not$libresoc.v:157651$8389_Y - connect \$15 $or$libresoc.v:157652$8390_Y - connect \$1 $not$libresoc.v:157653$8391_Y - connect \$3 $and$libresoc.v:157654$8392_Y - connect \$5 $or$libresoc.v:157655$8393_Y - connect \$7 $not$libresoc.v:157656$8394_Y + connect \$9 $and$libresoc.v:158957$8371_Y + connect \$11 $or$libresoc.v:158958$8372_Y + connect \$13 $not$libresoc.v:158959$8373_Y + connect \$15 $or$libresoc.v:158960$8374_Y + connect \$1 $not$libresoc.v:158961$8375_Y + connect \$3 $and$libresoc.v:158962$8376_Y + connect \$5 $or$libresoc.v:158963$8377_Y + connect \$7 $not$libresoc.v:158964$8378_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:157675.1-157733.10" +attribute \src "libresoc.v:158983.1-159041.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.opc_l" attribute \generator "nMigen" module \opc_l$40 - attribute \src "libresoc.v:157676.7-157676.20" + attribute \src "libresoc.v:158984.7-158984.20" wire $0\initial[0:0] - attribute \src "libresoc.v:157721.3-157729.6" - wire $0\q_int$next[0:0]$8411 - attribute \src "libresoc.v:157719.3-157720.27" + attribute \src "libresoc.v:159029.3-159037.6" + wire $0\q_int$next[0:0]$8395 + attribute \src "libresoc.v:159027.3-159028.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:157721.3-157729.6" - wire $1\q_int$next[0:0]$8412 - attribute \src "libresoc.v:157698.7-157698.19" + attribute \src "libresoc.v:159029.3-159037.6" + wire $1\q_int$next[0:0]$8396 + attribute \src "libresoc.v:159006.7-159006.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:157711.17-157711.96" - wire $and$libresoc.v:157711$8401_Y - attribute \src "libresoc.v:157716.17-157716.96" - wire $and$libresoc.v:157716$8406_Y - attribute \src "libresoc.v:157713.18-157713.93" - wire $not$libresoc.v:157713$8403_Y - attribute \src "libresoc.v:157715.17-157715.92" - wire $not$libresoc.v:157715$8405_Y - attribute \src "libresoc.v:157718.17-157718.92" - wire $not$libresoc.v:157718$8408_Y - attribute \src "libresoc.v:157712.18-157712.98" - wire $or$libresoc.v:157712$8402_Y - attribute \src "libresoc.v:157714.18-157714.99" - wire $or$libresoc.v:157714$8404_Y - attribute \src "libresoc.v:157717.17-157717.97" - wire $or$libresoc.v:157717$8407_Y + attribute \src "libresoc.v:159019.17-159019.96" + wire $and$libresoc.v:159019$8385_Y + attribute \src "libresoc.v:159024.17-159024.96" + wire $and$libresoc.v:159024$8390_Y + attribute \src "libresoc.v:159021.18-159021.93" + wire $not$libresoc.v:159021$8387_Y + attribute \src "libresoc.v:159023.17-159023.92" + wire $not$libresoc.v:159023$8389_Y + attribute \src "libresoc.v:159026.17-159026.92" + wire $not$libresoc.v:159026$8392_Y + attribute \src "libresoc.v:159020.18-159020.98" + wire $or$libresoc.v:159020$8386_Y + attribute \src "libresoc.v:159022.18-159022.99" + wire $or$libresoc.v:159022$8388_Y + attribute \src "libresoc.v:159025.17-159025.97" + wire $or$libresoc.v:159025$8391_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -325038,11 +296408,11 @@ module \opc_l$40 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:157676.7-157676.15" + attribute \src "libresoc.v:158984.7-158984.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -325059,7 +296429,7 @@ module \opc_l$40 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:157711$8401 + cell $and $and$libresoc.v:159019$8385 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325067,10 +296437,10 @@ module \opc_l$40 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:157711$8401_Y + connect \Y $and$libresoc.v:159019$8385_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:157716$8406 + cell $and $and$libresoc.v:159024$8390 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325078,34 +296448,34 @@ module \opc_l$40 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:157716$8406_Y + connect \Y $and$libresoc.v:159024$8390_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:157713$8403 + cell $not $not$libresoc.v:159021$8387 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:157713$8403_Y + connect \Y $not$libresoc.v:159021$8387_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:157715$8405 + cell $not $not$libresoc.v:159023$8389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157715$8405_Y + connect \Y $not$libresoc.v:159023$8389_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:157718$8408 + cell $not $not$libresoc.v:159026$8392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157718$8408_Y + connect \Y $not$libresoc.v:159026$8392_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:157712$8402 + cell $or $or$libresoc.v:159020$8386 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325113,10 +296483,10 @@ module \opc_l$40 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:157712$8402_Y + connect \Y $or$libresoc.v:159020$8386_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:157714$8404 + cell $or $or$libresoc.v:159022$8388 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325124,10 +296494,10 @@ module \opc_l$40 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:157714$8404_Y + connect \Y $or$libresoc.v:159022$8388_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:157717$8407 + cell $or $or$libresoc.v:159025$8391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325135,39 +296505,39 @@ module \opc_l$40 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:157717$8407_Y + connect \Y $or$libresoc.v:159025$8391_Y end - attribute \src "libresoc.v:157676.7-157676.20" - process $proc$libresoc.v:157676$8413 + attribute \src "libresoc.v:158984.7-158984.20" + process $proc$libresoc.v:158984$8397 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:157698.7-157698.19" - process $proc$libresoc.v:157698$8414 + attribute \src "libresoc.v:159006.7-159006.19" + process $proc$libresoc.v:159006$8398 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:157719.3-157720.27" - process $proc$libresoc.v:157719$8409 + attribute \src "libresoc.v:159027.3-159028.27" + process $proc$libresoc.v:159027$8393 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:157721.3-157729.6" - process $proc$libresoc.v:157721$8410 + attribute \src "libresoc.v:159029.3-159037.6" + process $proc$libresoc.v:159029$8394 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8411 $1\q_int$next[0:0]$8412 - attribute \src "libresoc.v:157722.5-157722.29" + assign $0\q_int$next[0:0]$8395 $1\q_int$next[0:0]$8396 + attribute \src "libresoc.v:159030.5-159030.29" switch \initial - attribute \src "libresoc.v:157722.9-157722.17" + attribute \src "libresoc.v:159030.9-159030.17" case 1'1 case end @@ -325176,56 +296546,56 @@ module \opc_l$40 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8412 1'0 + assign $1\q_int$next[0:0]$8396 1'0 case - assign $1\q_int$next[0:0]$8412 \$5 + assign $1\q_int$next[0:0]$8396 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8411 + update \q_int$next $0\q_int$next[0:0]$8395 end - connect \$9 $and$libresoc.v:157711$8401_Y - connect \$11 $or$libresoc.v:157712$8402_Y - connect \$13 $not$libresoc.v:157713$8403_Y - connect \$15 $or$libresoc.v:157714$8404_Y - connect \$1 $not$libresoc.v:157715$8405_Y - connect \$3 $and$libresoc.v:157716$8406_Y - connect \$5 $or$libresoc.v:157717$8407_Y - connect \$7 $not$libresoc.v:157718$8408_Y + connect \$9 $and$libresoc.v:159019$8385_Y + connect \$11 $or$libresoc.v:159020$8386_Y + connect \$13 $not$libresoc.v:159021$8387_Y + connect \$15 $or$libresoc.v:159022$8388_Y + connect \$1 $not$libresoc.v:159023$8389_Y + connect \$3 $and$libresoc.v:159024$8390_Y + connect \$5 $or$libresoc.v:159025$8391_Y + connect \$7 $not$libresoc.v:159026$8392_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:157737.1-157795.10" +attribute \src "libresoc.v:159045.1-159103.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.opc_l" attribute \generator "nMigen" module \opc_l$56 - attribute \src "libresoc.v:157738.7-157738.20" + attribute \src "libresoc.v:159046.7-159046.20" wire $0\initial[0:0] - attribute \src "libresoc.v:157783.3-157791.6" - wire $0\q_int$next[0:0]$8425 - attribute \src "libresoc.v:157781.3-157782.27" + attribute \src "libresoc.v:159091.3-159099.6" + wire $0\q_int$next[0:0]$8409 + attribute \src "libresoc.v:159089.3-159090.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:157783.3-157791.6" - wire $1\q_int$next[0:0]$8426 - attribute \src "libresoc.v:157760.7-157760.19" + attribute \src "libresoc.v:159091.3-159099.6" + wire $1\q_int$next[0:0]$8410 + attribute \src "libresoc.v:159068.7-159068.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:157773.17-157773.96" - wire $and$libresoc.v:157773$8415_Y - attribute \src "libresoc.v:157778.17-157778.96" - wire $and$libresoc.v:157778$8420_Y - attribute \src "libresoc.v:157775.18-157775.93" - wire $not$libresoc.v:157775$8417_Y - attribute \src "libresoc.v:157777.17-157777.92" - wire $not$libresoc.v:157777$8419_Y - attribute \src "libresoc.v:157780.17-157780.92" - wire $not$libresoc.v:157780$8422_Y - attribute \src "libresoc.v:157774.18-157774.98" - wire $or$libresoc.v:157774$8416_Y - attribute \src "libresoc.v:157776.18-157776.99" - wire $or$libresoc.v:157776$8418_Y - attribute \src "libresoc.v:157779.17-157779.97" - wire $or$libresoc.v:157779$8421_Y + attribute \src "libresoc.v:159081.17-159081.96" + wire $and$libresoc.v:159081$8399_Y + attribute \src "libresoc.v:159086.17-159086.96" + wire $and$libresoc.v:159086$8404_Y + attribute \src "libresoc.v:159083.18-159083.93" + wire $not$libresoc.v:159083$8401_Y + attribute \src "libresoc.v:159085.17-159085.92" + wire $not$libresoc.v:159085$8403_Y + attribute \src "libresoc.v:159088.17-159088.92" + wire $not$libresoc.v:159088$8406_Y + attribute \src "libresoc.v:159082.18-159082.98" + wire $or$libresoc.v:159082$8400_Y + attribute \src "libresoc.v:159084.18-159084.99" + wire $or$libresoc.v:159084$8402_Y + attribute \src "libresoc.v:159087.17-159087.97" + wire $or$libresoc.v:159087$8405_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -325242,11 +296612,11 @@ module \opc_l$56 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:157738.7-157738.15" + attribute \src "libresoc.v:159046.7-159046.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -325263,7 +296633,7 @@ module \opc_l$56 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:157773$8415 + cell $and $and$libresoc.v:159081$8399 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325271,10 +296641,10 @@ module \opc_l$56 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:157773$8415_Y + connect \Y $and$libresoc.v:159081$8399_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:157778$8420 + cell $and $and$libresoc.v:159086$8404 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325282,34 +296652,34 @@ module \opc_l$56 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:157778$8420_Y + connect \Y $and$libresoc.v:159086$8404_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:157775$8417 + cell $not $not$libresoc.v:159083$8401 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:157775$8417_Y + connect \Y $not$libresoc.v:159083$8401_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:157777$8419 + cell $not $not$libresoc.v:159085$8403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157777$8419_Y + connect \Y $not$libresoc.v:159085$8403_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:157780$8422 + cell $not $not$libresoc.v:159088$8406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157780$8422_Y + connect \Y $not$libresoc.v:159088$8406_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:157774$8416 + cell $or $or$libresoc.v:159082$8400 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325317,10 +296687,10 @@ module \opc_l$56 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:157774$8416_Y + connect \Y $or$libresoc.v:159082$8400_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:157776$8418 + cell $or $or$libresoc.v:159084$8402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325328,10 +296698,10 @@ module \opc_l$56 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:157776$8418_Y + connect \Y $or$libresoc.v:159084$8402_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:157779$8421 + cell $or $or$libresoc.v:159087$8405 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325339,39 +296709,39 @@ module \opc_l$56 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:157779$8421_Y + connect \Y $or$libresoc.v:159087$8405_Y end - attribute \src "libresoc.v:157738.7-157738.20" - process $proc$libresoc.v:157738$8427 + attribute \src "libresoc.v:159046.7-159046.20" + process $proc$libresoc.v:159046$8411 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:157760.7-157760.19" - process $proc$libresoc.v:157760$8428 + attribute \src "libresoc.v:159068.7-159068.19" + process $proc$libresoc.v:159068$8412 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:157781.3-157782.27" - process $proc$libresoc.v:157781$8423 + attribute \src "libresoc.v:159089.3-159090.27" + process $proc$libresoc.v:159089$8407 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:157783.3-157791.6" - process $proc$libresoc.v:157783$8424 + attribute \src "libresoc.v:159091.3-159099.6" + process $proc$libresoc.v:159091$8408 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8425 $1\q_int$next[0:0]$8426 - attribute \src "libresoc.v:157784.5-157784.29" + assign $0\q_int$next[0:0]$8409 $1\q_int$next[0:0]$8410 + attribute \src "libresoc.v:159092.5-159092.29" switch \initial - attribute \src "libresoc.v:157784.9-157784.17" + attribute \src "libresoc.v:159092.9-159092.17" case 1'1 case end @@ -325380,56 +296750,56 @@ module \opc_l$56 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8426 1'0 + assign $1\q_int$next[0:0]$8410 1'0 case - assign $1\q_int$next[0:0]$8426 \$5 + assign $1\q_int$next[0:0]$8410 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8425 + update \q_int$next $0\q_int$next[0:0]$8409 end - connect \$9 $and$libresoc.v:157773$8415_Y - connect \$11 $or$libresoc.v:157774$8416_Y - connect \$13 $not$libresoc.v:157775$8417_Y - connect \$15 $or$libresoc.v:157776$8418_Y - connect \$1 $not$libresoc.v:157777$8419_Y - connect \$3 $and$libresoc.v:157778$8420_Y - connect \$5 $or$libresoc.v:157779$8421_Y - connect \$7 $not$libresoc.v:157780$8422_Y + connect \$9 $and$libresoc.v:159081$8399_Y + connect \$11 $or$libresoc.v:159082$8400_Y + connect \$13 $not$libresoc.v:159083$8401_Y + connect \$15 $or$libresoc.v:159084$8402_Y + connect \$1 $not$libresoc.v:159085$8403_Y + connect \$3 $and$libresoc.v:159086$8404_Y + connect \$5 $or$libresoc.v:159087$8405_Y + connect \$7 $not$libresoc.v:159088$8406_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:157799.1-157857.10" +attribute \src "libresoc.v:159107.1-159165.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.opc_l" attribute \generator "nMigen" module \opc_l$68 - attribute \src "libresoc.v:157800.7-157800.20" + attribute \src "libresoc.v:159108.7-159108.20" wire $0\initial[0:0] - attribute \src "libresoc.v:157845.3-157853.6" - wire $0\q_int$next[0:0]$8439 - attribute \src "libresoc.v:157843.3-157844.27" + attribute \src "libresoc.v:159153.3-159161.6" + wire $0\q_int$next[0:0]$8423 + attribute \src "libresoc.v:159151.3-159152.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:157845.3-157853.6" - wire $1\q_int$next[0:0]$8440 - attribute \src "libresoc.v:157822.7-157822.19" + attribute \src "libresoc.v:159153.3-159161.6" + wire $1\q_int$next[0:0]$8424 + attribute \src "libresoc.v:159130.7-159130.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:157835.17-157835.96" - wire $and$libresoc.v:157835$8429_Y - attribute \src "libresoc.v:157840.17-157840.96" - wire $and$libresoc.v:157840$8434_Y - attribute \src "libresoc.v:157837.18-157837.93" - wire $not$libresoc.v:157837$8431_Y - attribute \src "libresoc.v:157839.17-157839.92" - wire $not$libresoc.v:157839$8433_Y - attribute \src "libresoc.v:157842.17-157842.92" - wire $not$libresoc.v:157842$8436_Y - attribute \src "libresoc.v:157836.18-157836.98" - wire $or$libresoc.v:157836$8430_Y - attribute \src "libresoc.v:157838.18-157838.99" - wire $or$libresoc.v:157838$8432_Y - attribute \src "libresoc.v:157841.17-157841.97" - wire $or$libresoc.v:157841$8435_Y + attribute \src "libresoc.v:159143.17-159143.96" + wire $and$libresoc.v:159143$8413_Y + attribute \src "libresoc.v:159148.17-159148.96" + wire $and$libresoc.v:159148$8418_Y + attribute \src "libresoc.v:159145.18-159145.93" + wire $not$libresoc.v:159145$8415_Y + attribute \src "libresoc.v:159147.17-159147.92" + wire $not$libresoc.v:159147$8417_Y + attribute \src "libresoc.v:159150.17-159150.92" + wire $not$libresoc.v:159150$8420_Y + attribute \src "libresoc.v:159144.18-159144.98" + wire $or$libresoc.v:159144$8414_Y + attribute \src "libresoc.v:159146.18-159146.99" + wire $or$libresoc.v:159146$8416_Y + attribute \src "libresoc.v:159149.17-159149.97" + wire $or$libresoc.v:159149$8419_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -325446,11 +296816,11 @@ module \opc_l$68 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:157800.7-157800.15" + attribute \src "libresoc.v:159108.7-159108.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -325467,7 +296837,7 @@ module \opc_l$68 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:157835$8429 + cell $and $and$libresoc.v:159143$8413 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325475,10 +296845,10 @@ module \opc_l$68 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:157835$8429_Y + connect \Y $and$libresoc.v:159143$8413_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:157840$8434 + cell $and $and$libresoc.v:159148$8418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325486,34 +296856,34 @@ module \opc_l$68 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:157840$8434_Y + connect \Y $and$libresoc.v:159148$8418_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:157837$8431 + cell $not $not$libresoc.v:159145$8415 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:157837$8431_Y + connect \Y $not$libresoc.v:159145$8415_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:157839$8433 + cell $not $not$libresoc.v:159147$8417 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157839$8433_Y + connect \Y $not$libresoc.v:159147$8417_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:157842$8436 + cell $not $not$libresoc.v:159150$8420 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157842$8436_Y + connect \Y $not$libresoc.v:159150$8420_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:157836$8430 + cell $or $or$libresoc.v:159144$8414 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325521,10 +296891,10 @@ module \opc_l$68 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:157836$8430_Y + connect \Y $or$libresoc.v:159144$8414_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:157838$8432 + cell $or $or$libresoc.v:159146$8416 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325532,10 +296902,10 @@ module \opc_l$68 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:157838$8432_Y + connect \Y $or$libresoc.v:159146$8416_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:157841$8435 + cell $or $or$libresoc.v:159149$8419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325543,39 +296913,39 @@ module \opc_l$68 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:157841$8435_Y + connect \Y $or$libresoc.v:159149$8419_Y end - attribute \src "libresoc.v:157800.7-157800.20" - process $proc$libresoc.v:157800$8441 + attribute \src "libresoc.v:159108.7-159108.20" + process $proc$libresoc.v:159108$8425 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:157822.7-157822.19" - process $proc$libresoc.v:157822$8442 + attribute \src "libresoc.v:159130.7-159130.19" + process $proc$libresoc.v:159130$8426 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:157843.3-157844.27" - process $proc$libresoc.v:157843$8437 + attribute \src "libresoc.v:159151.3-159152.27" + process $proc$libresoc.v:159151$8421 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:157845.3-157853.6" - process $proc$libresoc.v:157845$8438 + attribute \src "libresoc.v:159153.3-159161.6" + process $proc$libresoc.v:159153$8422 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8439 $1\q_int$next[0:0]$8440 - attribute \src "libresoc.v:157846.5-157846.29" + assign $0\q_int$next[0:0]$8423 $1\q_int$next[0:0]$8424 + attribute \src "libresoc.v:159154.5-159154.29" switch \initial - attribute \src "libresoc.v:157846.9-157846.17" + attribute \src "libresoc.v:159154.9-159154.17" case 1'1 case end @@ -325584,56 +296954,56 @@ module \opc_l$68 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8440 1'0 + assign $1\q_int$next[0:0]$8424 1'0 case - assign $1\q_int$next[0:0]$8440 \$5 + assign $1\q_int$next[0:0]$8424 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8439 + update \q_int$next $0\q_int$next[0:0]$8423 end - connect \$9 $and$libresoc.v:157835$8429_Y - connect \$11 $or$libresoc.v:157836$8430_Y - connect \$13 $not$libresoc.v:157837$8431_Y - connect \$15 $or$libresoc.v:157838$8432_Y - connect \$1 $not$libresoc.v:157839$8433_Y - connect \$3 $and$libresoc.v:157840$8434_Y - connect \$5 $or$libresoc.v:157841$8435_Y - connect \$7 $not$libresoc.v:157842$8436_Y + connect \$9 $and$libresoc.v:159143$8413_Y + connect \$11 $or$libresoc.v:159144$8414_Y + connect \$13 $not$libresoc.v:159145$8415_Y + connect \$15 $or$libresoc.v:159146$8416_Y + connect \$1 $not$libresoc.v:159147$8417_Y + connect \$3 $and$libresoc.v:159148$8418_Y + connect \$5 $or$libresoc.v:159149$8419_Y + connect \$7 $not$libresoc.v:159150$8420_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:157861.1-157919.10" +attribute \src "libresoc.v:159169.1-159227.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.opc_l" attribute \generator "nMigen" module \opc_l$85 - attribute \src "libresoc.v:157862.7-157862.20" + attribute \src "libresoc.v:159170.7-159170.20" wire $0\initial[0:0] - attribute \src "libresoc.v:157907.3-157915.6" - wire $0\q_int$next[0:0]$8453 - attribute \src "libresoc.v:157905.3-157906.27" + attribute \src "libresoc.v:159215.3-159223.6" + wire $0\q_int$next[0:0]$8437 + attribute \src "libresoc.v:159213.3-159214.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:157907.3-157915.6" - wire $1\q_int$next[0:0]$8454 - attribute \src "libresoc.v:157884.7-157884.19" + attribute \src "libresoc.v:159215.3-159223.6" + wire $1\q_int$next[0:0]$8438 + attribute \src "libresoc.v:159192.7-159192.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:157897.17-157897.96" - wire $and$libresoc.v:157897$8443_Y - attribute \src "libresoc.v:157902.17-157902.96" - wire $and$libresoc.v:157902$8448_Y - attribute \src "libresoc.v:157899.18-157899.93" - wire $not$libresoc.v:157899$8445_Y - attribute \src "libresoc.v:157901.17-157901.92" - wire $not$libresoc.v:157901$8447_Y - attribute \src "libresoc.v:157904.17-157904.92" - wire $not$libresoc.v:157904$8450_Y - attribute \src "libresoc.v:157898.18-157898.98" - wire $or$libresoc.v:157898$8444_Y - attribute \src "libresoc.v:157900.18-157900.99" - wire $or$libresoc.v:157900$8446_Y - attribute \src "libresoc.v:157903.17-157903.97" - wire $or$libresoc.v:157903$8449_Y + attribute \src "libresoc.v:159205.17-159205.96" + wire $and$libresoc.v:159205$8427_Y + attribute \src "libresoc.v:159210.17-159210.96" + wire $and$libresoc.v:159210$8432_Y + attribute \src "libresoc.v:159207.18-159207.93" + wire $not$libresoc.v:159207$8429_Y + attribute \src "libresoc.v:159209.17-159209.92" + wire $not$libresoc.v:159209$8431_Y + attribute \src "libresoc.v:159212.17-159212.92" + wire $not$libresoc.v:159212$8434_Y + attribute \src "libresoc.v:159206.18-159206.98" + wire $or$libresoc.v:159206$8428_Y + attribute \src "libresoc.v:159208.18-159208.99" + wire $or$libresoc.v:159208$8430_Y + attribute \src "libresoc.v:159211.17-159211.97" + wire $or$libresoc.v:159211$8433_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -325650,11 +297020,11 @@ module \opc_l$85 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:157862.7-157862.15" + attribute \src "libresoc.v:159170.7-159170.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -325671,7 +297041,7 @@ module \opc_l$85 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_opc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:157897$8443 + cell $and $and$libresoc.v:159205$8427 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325679,10 +297049,10 @@ module \opc_l$85 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:157897$8443_Y + connect \Y $and$libresoc.v:159205$8427_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:157902$8448 + cell $and $and$libresoc.v:159210$8432 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325690,34 +297060,34 @@ module \opc_l$85 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:157902$8448_Y + connect \Y $and$libresoc.v:159210$8432_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:157899$8445 + cell $not $not$libresoc.v:159207$8429 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_opc - connect \Y $not$libresoc.v:157899$8445_Y + connect \Y $not$libresoc.v:159207$8429_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:157901$8447 + cell $not $not$libresoc.v:159209$8431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157901$8447_Y + connect \Y $not$libresoc.v:159209$8431_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:157904$8450 + cell $not $not$libresoc.v:159212$8434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_opc - connect \Y $not$libresoc.v:157904$8450_Y + connect \Y $not$libresoc.v:159212$8434_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:157898$8444 + cell $or $or$libresoc.v:159206$8428 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325725,10 +297095,10 @@ module \opc_l$85 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_opc - connect \Y $or$libresoc.v:157898$8444_Y + connect \Y $or$libresoc.v:159206$8428_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:157900$8446 + cell $or $or$libresoc.v:159208$8430 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325736,10 +297106,10 @@ module \opc_l$85 parameter \Y_WIDTH 1 connect \A \q_opc connect \B \q_int - connect \Y $or$libresoc.v:157900$8446_Y + connect \Y $or$libresoc.v:159208$8430_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:157903$8449 + cell $or $or$libresoc.v:159211$8433 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -325747,39 +297117,39 @@ module \opc_l$85 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_opc - connect \Y $or$libresoc.v:157903$8449_Y + connect \Y $or$libresoc.v:159211$8433_Y end - attribute \src "libresoc.v:157862.7-157862.20" - process $proc$libresoc.v:157862$8455 + attribute \src "libresoc.v:159170.7-159170.20" + process $proc$libresoc.v:159170$8439 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:157884.7-157884.19" - process $proc$libresoc.v:157884$8456 + attribute \src "libresoc.v:159192.7-159192.19" + process $proc$libresoc.v:159192$8440 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:157905.3-157906.27" - process $proc$libresoc.v:157905$8451 + attribute \src "libresoc.v:159213.3-159214.27" + process $proc$libresoc.v:159213$8435 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:157907.3-157915.6" - process $proc$libresoc.v:157907$8452 + attribute \src "libresoc.v:159215.3-159223.6" + process $proc$libresoc.v:159215$8436 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$8453 $1\q_int$next[0:0]$8454 - attribute \src "libresoc.v:157908.5-157908.29" + assign $0\q_int$next[0:0]$8437 $1\q_int$next[0:0]$8438 + attribute \src "libresoc.v:159216.5-159216.29" switch \initial - attribute \src "libresoc.v:157908.9-157908.17" + attribute \src "libresoc.v:159216.9-159216.17" case 1'1 case end @@ -325788,90 +297158,90 @@ module \opc_l$85 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$8454 1'0 + assign $1\q_int$next[0:0]$8438 1'0 case - assign $1\q_int$next[0:0]$8454 \$5 + assign $1\q_int$next[0:0]$8438 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$8453 + update \q_int$next $0\q_int$next[0:0]$8437 end - connect \$9 $and$libresoc.v:157897$8443_Y - connect \$11 $or$libresoc.v:157898$8444_Y - connect \$13 $not$libresoc.v:157899$8445_Y - connect \$15 $or$libresoc.v:157900$8446_Y - connect \$1 $not$libresoc.v:157901$8447_Y - connect \$3 $and$libresoc.v:157902$8448_Y - connect \$5 $or$libresoc.v:157903$8449_Y - connect \$7 $not$libresoc.v:157904$8450_Y + connect \$9 $and$libresoc.v:159205$8427_Y + connect \$11 $or$libresoc.v:159206$8428_Y + connect \$13 $not$libresoc.v:159207$8429_Y + connect \$15 $or$libresoc.v:159208$8430_Y + connect \$1 $not$libresoc.v:159209$8431_Y + connect \$3 $and$libresoc.v:159210$8432_Y + connect \$5 $or$libresoc.v:159211$8433_Y + connect \$7 $not$libresoc.v:159212$8434_Y connect \qlq_opc \$15 connect \qn_opc \$13 connect \q_opc \$11 end -attribute \src "libresoc.v:157923.1-158381.10" +attribute \src "libresoc.v:159231.1-159689.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.output" attribute \generator "nMigen" module \output - attribute \src "libresoc.v:158300.3-158311.6" + attribute \src "libresoc.v:159608.3-159619.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:157924.7-157924.20" + attribute \src "libresoc.v:159232.7-159232.20" wire $0\initial[0:0] - attribute \src "libresoc.v:158312.3-158323.6" - wire width 65 $0\o$28[64:0]$8475 - attribute \src "libresoc.v:158288.3-158299.6" + attribute \src "libresoc.v:159620.3-159631.6" + wire width 65 $0\o$28[64:0]$8459 + attribute \src "libresoc.v:159596.3-159607.6" wire $0\so[0:0] - attribute \src "libresoc.v:158344.3-158353.6" - wire width 2 $0\xer_ov$24[1:0]$8482 - attribute \src "libresoc.v:158354.3-158363.6" + attribute \src "libresoc.v:159652.3-159661.6" + wire width 2 $0\xer_ov$24[1:0]$8466 + attribute \src "libresoc.v:159662.3-159671.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:158324.3-158333.6" - wire $0\xer_so$25[0:0]$8478 - attribute \src "libresoc.v:158334.3-158343.6" + attribute \src "libresoc.v:159632.3-159641.6" + wire $0\xer_so$25[0:0]$8462 + attribute \src "libresoc.v:159642.3-159651.6" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:158300.3-158311.6" + attribute \src "libresoc.v:159608.3-159619.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:158312.3-158323.6" - wire width 65 $1\o$28[64:0]$8476 - attribute \src "libresoc.v:158288.3-158299.6" + attribute \src "libresoc.v:159620.3-159631.6" + wire width 65 $1\o$28[64:0]$8460 + attribute \src "libresoc.v:159596.3-159607.6" wire $1\so[0:0] - attribute \src "libresoc.v:158344.3-158353.6" - wire width 2 $1\xer_ov$24[1:0]$8483 - attribute \src "libresoc.v:158354.3-158363.6" + attribute \src "libresoc.v:159652.3-159661.6" + wire width 2 $1\xer_ov$24[1:0]$8467 + attribute \src "libresoc.v:159662.3-159671.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:158324.3-158333.6" - wire $1\xer_so$25[0:0]$8479 - attribute \src "libresoc.v:158334.3-158343.6" + attribute \src "libresoc.v:159632.3-159641.6" + wire $1\xer_so$25[0:0]$8463 + attribute \src "libresoc.v:159642.3-159651.6" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:158275.18-158275.128" - wire $and$libresoc.v:158275$8457_Y - attribute \src "libresoc.v:158283.18-158283.112" - wire $and$libresoc.v:158283$8467_Y - attribute \src "libresoc.v:158286.18-158286.125" - wire $and$libresoc.v:158286$8470_Y - attribute \src "libresoc.v:158279.18-158279.123" - wire $eq$libresoc.v:158279$8463_Y - attribute \src "libresoc.v:158280.18-158280.123" - wire $eq$libresoc.v:158280$8464_Y - attribute \src "libresoc.v:158277.18-158277.103" - wire width 65 $extend$libresoc.v:158277$8459_Y - attribute \src "libresoc.v:158278.18-158278.101" - wire width 65 $extend$libresoc.v:158278$8461_Y - attribute \src "libresoc.v:158276.18-158276.100" - wire width 64 $not$libresoc.v:158276$8458_Y - attribute \src "libresoc.v:158282.18-158282.107" - wire $not$libresoc.v:158282$8466_Y - attribute \src "libresoc.v:158285.18-158285.107" - wire $not$libresoc.v:158285$8469_Y - attribute \src "libresoc.v:158284.18-158284.115" - wire $or$libresoc.v:158284$8468_Y - attribute \src "libresoc.v:158287.18-158287.112" - wire $or$libresoc.v:158287$8471_Y - attribute \src "libresoc.v:158277.18-158277.103" - wire width 65 $pos$libresoc.v:158277$8460_Y - attribute \src "libresoc.v:158278.18-158278.101" - wire width 65 $pos$libresoc.v:158278$8462_Y - attribute \src "libresoc.v:158281.18-158281.105" - wire $reduce_or$libresoc.v:158281$8465_Y + attribute \src "libresoc.v:159583.18-159583.128" + wire $and$libresoc.v:159583$8441_Y + attribute \src "libresoc.v:159591.18-159591.112" + wire $and$libresoc.v:159591$8451_Y + attribute \src "libresoc.v:159594.18-159594.125" + wire $and$libresoc.v:159594$8454_Y + attribute \src "libresoc.v:159587.18-159587.123" + wire $eq$libresoc.v:159587$8447_Y + attribute \src "libresoc.v:159588.18-159588.123" + wire $eq$libresoc.v:159588$8448_Y + attribute \src "libresoc.v:159585.18-159585.103" + wire width 65 $extend$libresoc.v:159585$8443_Y + attribute \src "libresoc.v:159586.18-159586.101" + wire width 65 $extend$libresoc.v:159586$8445_Y + attribute \src "libresoc.v:159584.18-159584.100" + wire width 64 $not$libresoc.v:159584$8442_Y + attribute \src "libresoc.v:159590.18-159590.107" + wire $not$libresoc.v:159590$8450_Y + attribute \src "libresoc.v:159593.18-159593.107" + wire $not$libresoc.v:159593$8453_Y + attribute \src "libresoc.v:159592.18-159592.115" + wire $or$libresoc.v:159592$8452_Y + attribute \src "libresoc.v:159595.18-159595.112" + wire $or$libresoc.v:159595$8455_Y + attribute \src "libresoc.v:159585.18-159585.103" + wire width 65 $pos$libresoc.v:159585$8444_Y + attribute \src "libresoc.v:159586.18-159586.101" + wire width 65 $pos$libresoc.v:159586$8446_Y + attribute \src "libresoc.v:159589.18-159589.105" + wire $reduce_or$libresoc.v:159589$8449_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" wire \$26 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" @@ -326166,7 +297536,7 @@ module \output wire width 4 output 46 \cr_a$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 47 \cr_a_ok - attribute \src "libresoc.v:157924.7-157924.15" + attribute \src "libresoc.v:159232.7-159232.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -326221,7 +297591,7 @@ module \output attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 53 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" - cell $and $and$libresoc.v:158275$8457 + cell $and $and$libresoc.v:159583$8441 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326229,10 +297599,10 @@ module \output parameter \Y_WIDTH 1 connect \A \alu_op__oe__oe connect \B \alu_op__oe__ok - connect \Y $and$libresoc.v:158275$8457_Y + connect \Y $and$libresoc.v:159583$8441_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:158283$8467 + cell $and $and$libresoc.v:159591$8451 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326240,10 +297610,10 @@ module \output parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$41 - connect \Y $and$libresoc.v:158283$8467_Y + connect \Y $and$libresoc.v:159591$8451_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - cell $and $and$libresoc.v:158286$8470 + cell $and $and$libresoc.v:159594$8454 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326251,10 +297621,10 @@ module \output parameter \Y_WIDTH 1 connect \A \alu_op__oe__oe connect \B \alu_op__oe__ok - connect \Y $and$libresoc.v:158286$8470_Y + connect \Y $and$libresoc.v:159594$8454_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:158279$8463 + cell $eq $eq$libresoc.v:159587$8447 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -326262,10 +297632,10 @@ module \output parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:158279$8463_Y + connect \Y $eq$libresoc.v:159587$8447_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:158280$8464 + cell $eq $eq$libresoc.v:159588$8448 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -326273,50 +297643,50 @@ module \output parameter \Y_WIDTH 1 connect \A \alu_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:158280$8464_Y + connect \Y $eq$libresoc.v:159588$8448_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $extend$libresoc.v:158277$8459 + cell $pos $extend$libresoc.v:159585$8443 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \$30 - connect \Y $extend$libresoc.v:158277$8459_Y + connect \Y $extend$libresoc.v:159585$8443_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:158278$8461 + cell $pos $extend$libresoc.v:159586$8445 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:158278$8461_Y + connect \Y $extend$libresoc.v:159586$8445_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $not $not$libresoc.v:158276$8458 + cell $not $not$libresoc.v:159584$8442 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \o - connect \Y $not$libresoc.v:158276$8458_Y + connect \Y $not$libresoc.v:159584$8442_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:158282$8466 + cell $not $not$libresoc.v:159590$8450 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:158282$8466_Y + connect \Y $not$libresoc.v:159590$8450_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:158285$8469 + cell $not $not$libresoc.v:159593$8453 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:158285$8469_Y + connect \Y $not$libresoc.v:159593$8453_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:158284$8468 + cell $or $or$libresoc.v:159592$8452 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326324,10 +297694,10 @@ module \output parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:158284$8468_Y + connect \Y $or$libresoc.v:159592$8452_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - cell $or $or$libresoc.v:158287$8471 + cell $or $or$libresoc.v:159595$8455 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326335,47 +297705,47 @@ module \output parameter \Y_WIDTH 1 connect \A \xer_so connect \B \xer_ov [0] - connect \Y $or$libresoc.v:158287$8471_Y + connect \Y $or$libresoc.v:159595$8455_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $pos$libresoc.v:158277$8460 + cell $pos $pos$libresoc.v:159585$8444 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:158277$8459_Y - connect \Y $pos$libresoc.v:158277$8460_Y + connect \A $extend$libresoc.v:159585$8443_Y + connect \Y $pos$libresoc.v:159585$8444_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:158278$8462 + cell $pos $pos$libresoc.v:159586$8446 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:158278$8461_Y - connect \Y $pos$libresoc.v:158278$8462_Y + connect \A $extend$libresoc.v:159586$8445_Y + connect \Y $pos$libresoc.v:159586$8446_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:158281$8465 + cell $reduce_or $reduce_or$libresoc.v:159589$8449 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:158281$8465_Y + connect \Y $reduce_or$libresoc.v:159589$8449_Y end - attribute \src "libresoc.v:157924.7-157924.20" - process $proc$libresoc.v:157924$8485 + attribute \src "libresoc.v:159232.7-159232.20" + process $proc$libresoc.v:159232$8469 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:158288.3-158299.6" - process $proc$libresoc.v:158288$8472 + attribute \src "libresoc.v:159596.3-159607.6" + process $proc$libresoc.v:159596$8456 assign { } { } assign $0\so[0:0] $1\so[0:0] - attribute \src "libresoc.v:158289.5-158289.29" + attribute \src "libresoc.v:159597.5-159597.29" switch \initial - attribute \src "libresoc.v:158289.9-158289.17" + attribute \src "libresoc.v:159597.9-159597.17" case 1'1 case end @@ -326393,13 +297763,13 @@ module \output sync always update \so $0\so[0:0] end - attribute \src "libresoc.v:158300.3-158311.6" - process $proc$libresoc.v:158300$8473 + attribute \src "libresoc.v:159608.3-159619.6" + process $proc$libresoc.v:159608$8457 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:158301.5-158301.29" + attribute \src "libresoc.v:159609.5-159609.29" switch \initial - attribute \src "libresoc.v:158301.9-158301.17" + attribute \src "libresoc.v:159609.9-159609.17" case 1'1 case end @@ -326417,13 +297787,13 @@ module \output sync always update \cr0 $0\cr0[3:0] end - attribute \src "libresoc.v:158312.3-158323.6" - process $proc$libresoc.v:158312$8474 + attribute \src "libresoc.v:159620.3-159631.6" + process $proc$libresoc.v:159620$8458 assign { } { } - assign $0\o$28[64:0]$8475 $1\o$28[64:0]$8476 - attribute \src "libresoc.v:158313.5-158313.29" + assign $0\o$28[64:0]$8459 $1\o$28[64:0]$8460 + attribute \src "libresoc.v:159621.5-159621.29" switch \initial - attribute \src "libresoc.v:158313.9-158313.17" + attribute \src "libresoc.v:159621.9-159621.17" case 1'1 case end @@ -326432,23 +297802,23 @@ module \output attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\o$28[64:0]$8476 \$29 + assign $1\o$28[64:0]$8460 \$29 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\o$28[64:0]$8476 \$33 + assign $1\o$28[64:0]$8460 \$33 end sync always - update \o$28 $0\o$28[64:0]$8475 + update \o$28 $0\o$28[64:0]$8459 end - attribute \src "libresoc.v:158324.3-158333.6" - process $proc$libresoc.v:158324$8477 + attribute \src "libresoc.v:159632.3-159641.6" + process $proc$libresoc.v:159632$8461 assign { } { } assign { } { } - assign $0\xer_so$25[0:0]$8478 $1\xer_so$25[0:0]$8479 - attribute \src "libresoc.v:158325.5-158325.29" + assign $0\xer_so$25[0:0]$8462 $1\xer_so$25[0:0]$8463 + attribute \src "libresoc.v:159633.5-159633.29" switch \initial - attribute \src "libresoc.v:158325.9-158325.17" + attribute \src "libresoc.v:159633.9-159633.17" case 1'1 case end @@ -326457,21 +297827,21 @@ module \output attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_so$25[0:0]$8479 \$52 + assign $1\xer_so$25[0:0]$8463 \$52 case - assign $1\xer_so$25[0:0]$8479 1'0 + assign $1\xer_so$25[0:0]$8463 1'0 end sync always - update \xer_so$25 $0\xer_so$25[0:0]$8478 + update \xer_so$25 $0\xer_so$25[0:0]$8462 end - attribute \src "libresoc.v:158334.3-158343.6" - process $proc$libresoc.v:158334$8480 + attribute \src "libresoc.v:159642.3-159651.6" + process $proc$libresoc.v:159642$8464 assign { } { } assign { } { } assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "libresoc.v:158335.5-158335.29" + attribute \src "libresoc.v:159643.5-159643.29" switch \initial - attribute \src "libresoc.v:158335.9-158335.17" + attribute \src "libresoc.v:159643.9-159643.17" case 1'1 case end @@ -326487,14 +297857,14 @@ module \output sync always update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:158344.3-158353.6" - process $proc$libresoc.v:158344$8481 + attribute \src "libresoc.v:159652.3-159661.6" + process $proc$libresoc.v:159652$8465 assign { } { } assign { } { } - assign $0\xer_ov$24[1:0]$8482 $1\xer_ov$24[1:0]$8483 - attribute \src "libresoc.v:158345.5-158345.29" + assign $0\xer_ov$24[1:0]$8466 $1\xer_ov$24[1:0]$8467 + attribute \src "libresoc.v:159653.5-159653.29" switch \initial - attribute \src "libresoc.v:158345.9-158345.17" + attribute \src "libresoc.v:159653.9-159653.17" case 1'1 case end @@ -326503,21 +297873,21 @@ module \output attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_ov$24[1:0]$8483 \xer_ov + assign $1\xer_ov$24[1:0]$8467 \xer_ov case - assign $1\xer_ov$24[1:0]$8483 2'00 + assign $1\xer_ov$24[1:0]$8467 2'00 end sync always - update \xer_ov$24 $0\xer_ov$24[1:0]$8482 + update \xer_ov$24 $0\xer_ov$24[1:0]$8466 end - attribute \src "libresoc.v:158354.3-158363.6" - process $proc$libresoc.v:158354$8484 + attribute \src "libresoc.v:159662.3-159671.6" + process $proc$libresoc.v:159662$8468 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:158355.5-158355.29" + attribute \src "libresoc.v:159663.5-159663.29" switch \initial - attribute \src "libresoc.v:158355.9-158355.17" + attribute \src "libresoc.v:159663.9-159663.17" case 1'1 case end @@ -326533,19 +297903,19 @@ module \output sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - connect \$26 $and$libresoc.v:158275$8457_Y - connect \$30 $not$libresoc.v:158276$8458_Y - connect \$29 $pos$libresoc.v:158277$8460_Y - connect \$33 $pos$libresoc.v:158278$8462_Y - connect \$35 $eq$libresoc.v:158279$8463_Y - connect \$37 $eq$libresoc.v:158280$8464_Y - connect \$39 $reduce_or$libresoc.v:158281$8465_Y - connect \$41 $not$libresoc.v:158282$8466_Y - connect \$43 $and$libresoc.v:158283$8467_Y - connect \$45 $or$libresoc.v:158284$8468_Y - connect \$47 $not$libresoc.v:158285$8469_Y - connect \$50 $and$libresoc.v:158286$8470_Y - connect \$52 $or$libresoc.v:158287$8471_Y + connect \$26 $and$libresoc.v:159583$8441_Y + connect \$30 $not$libresoc.v:159584$8442_Y + connect \$29 $pos$libresoc.v:159585$8444_Y + connect \$33 $pos$libresoc.v:159586$8446_Y + connect \$35 $eq$libresoc.v:159587$8447_Y + connect \$37 $eq$libresoc.v:159588$8448_Y + connect \$39 $reduce_or$libresoc.v:159589$8449_Y + connect \$41 $not$libresoc.v:159590$8450_Y + connect \$43 $and$libresoc.v:159591$8451_Y + connect \$45 $or$libresoc.v:159592$8452_Y + connect \$47 $not$libresoc.v:159593$8453_Y + connect \$50 $and$libresoc.v:159594$8454_Y + connect \$52 $or$libresoc.v:159595$8455_Y connect \oe$49 \$50 connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } connect \muxid$1 \muxid @@ -326564,61 +297934,61 @@ module \output connect \target \o$28 [63:0] connect \oe \$26 end -attribute \src "libresoc.v:158385.1-158786.10" +attribute \src "libresoc.v:159693.1-160094.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.output" attribute \generator "nMigen" module \output$100 - attribute \src "libresoc.v:158718.3-158729.6" + attribute \src "libresoc.v:160026.3-160037.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:158386.7-158386.20" + attribute \src "libresoc.v:159694.7-159694.20" wire $0\initial[0:0] - attribute \src "libresoc.v:158706.3-158717.6" + attribute \src "libresoc.v:160014.3-160025.6" wire $0\so[0:0] - attribute \src "libresoc.v:158750.3-158759.6" - wire width 2 $0\xer_ov$17[1:0]$8505 - attribute \src "libresoc.v:158760.3-158769.6" + attribute \src "libresoc.v:160058.3-160067.6" + wire width 2 $0\xer_ov$17[1:0]$8489 + attribute \src "libresoc.v:160068.3-160077.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:158730.3-158739.6" - wire $0\xer_so$18[0:0]$8501 - attribute \src "libresoc.v:158740.3-158749.6" + attribute \src "libresoc.v:160038.3-160047.6" + wire $0\xer_so$18[0:0]$8485 + attribute \src "libresoc.v:160048.3-160057.6" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:158718.3-158729.6" + attribute \src "libresoc.v:160026.3-160037.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:158706.3-158717.6" + attribute \src "libresoc.v:160014.3-160025.6" wire $1\so[0:0] - attribute \src "libresoc.v:158750.3-158759.6" - wire width 2 $1\xer_ov$17[1:0]$8506 - attribute \src "libresoc.v:158760.3-158769.6" + attribute \src "libresoc.v:160058.3-160067.6" + wire width 2 $1\xer_ov$17[1:0]$8490 + attribute \src "libresoc.v:160068.3-160077.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:158730.3-158739.6" - wire $1\xer_so$18[0:0]$8502 - attribute \src "libresoc.v:158740.3-158749.6" + attribute \src "libresoc.v:160038.3-160047.6" + wire $1\xer_so$18[0:0]$8486 + attribute \src "libresoc.v:160048.3-160057.6" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:158695.18-158695.128" - wire $and$libresoc.v:158695$8486_Y - attribute \src "libresoc.v:158701.18-158701.112" - wire $and$libresoc.v:158701$8493_Y - attribute \src "libresoc.v:158704.18-158704.125" - wire $and$libresoc.v:158704$8496_Y - attribute \src "libresoc.v:158697.18-158697.123" - wire $eq$libresoc.v:158697$8489_Y - attribute \src "libresoc.v:158698.18-158698.123" - wire $eq$libresoc.v:158698$8490_Y - attribute \src "libresoc.v:158696.18-158696.101" - wire width 65 $extend$libresoc.v:158696$8487_Y - attribute \src "libresoc.v:158700.18-158700.107" - wire $not$libresoc.v:158700$8492_Y - attribute \src "libresoc.v:158703.18-158703.107" - wire $not$libresoc.v:158703$8495_Y - attribute \src "libresoc.v:158702.18-158702.115" - wire $or$libresoc.v:158702$8494_Y - attribute \src "libresoc.v:158705.18-158705.112" - wire $or$libresoc.v:158705$8497_Y - attribute \src "libresoc.v:158696.18-158696.101" - wire width 65 $pos$libresoc.v:158696$8488_Y - attribute \src "libresoc.v:158699.18-158699.105" - wire $reduce_or$libresoc.v:158699$8491_Y + attribute \src "libresoc.v:160003.18-160003.128" + wire $and$libresoc.v:160003$8470_Y + attribute \src "libresoc.v:160009.18-160009.112" + wire $and$libresoc.v:160009$8477_Y + attribute \src "libresoc.v:160012.18-160012.125" + wire $and$libresoc.v:160012$8480_Y + attribute \src "libresoc.v:160005.18-160005.123" + wire $eq$libresoc.v:160005$8473_Y + attribute \src "libresoc.v:160006.18-160006.123" + wire $eq$libresoc.v:160006$8474_Y + attribute \src "libresoc.v:160004.18-160004.101" + wire width 65 $extend$libresoc.v:160004$8471_Y + attribute \src "libresoc.v:160008.18-160008.107" + wire $not$libresoc.v:160008$8476_Y + attribute \src "libresoc.v:160011.18-160011.107" + wire $not$libresoc.v:160011$8479_Y + attribute \src "libresoc.v:160010.18-160010.115" + wire $or$libresoc.v:160010$8478_Y + attribute \src "libresoc.v:160013.18-160013.112" + wire $or$libresoc.v:160013$8481_Y + attribute \src "libresoc.v:160004.18-160004.101" + wire width 65 $pos$libresoc.v:160004$8472_Y + attribute \src "libresoc.v:160007.18-160007.105" + wire $reduce_or$libresoc.v:160007$8475_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" wire \$19 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" @@ -326649,7 +298019,7 @@ module \output$100 wire width 4 output 33 \cr_a$16 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 34 \cr_a_ok - attribute \src "libresoc.v:158386.7-158386.15" + attribute \src "libresoc.v:159694.7-159694.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -326926,7 +298296,7 @@ module \output$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 38 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" - cell $and $and$libresoc.v:158695$8486 + cell $and $and$libresoc.v:160003$8470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326934,10 +298304,10 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \mul_op__oe__oe connect \B \mul_op__oe__ok - connect \Y $and$libresoc.v:158695$8486_Y + connect \Y $and$libresoc.v:160003$8470_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:158701$8493 + cell $and $and$libresoc.v:160009$8477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326945,10 +298315,10 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$30 - connect \Y $and$libresoc.v:158701$8493_Y + connect \Y $and$libresoc.v:160009$8477_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - cell $and $and$libresoc.v:158704$8496 + cell $and $and$libresoc.v:160012$8480 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -326956,10 +298326,10 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \mul_op__oe__oe connect \B \mul_op__oe__ok - connect \Y $and$libresoc.v:158704$8496_Y + connect \Y $and$libresoc.v:160012$8480_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:158697$8489 + cell $eq $eq$libresoc.v:160005$8473 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -326967,10 +298337,10 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \mul_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:158697$8489_Y + connect \Y $eq$libresoc.v:160005$8473_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:158698$8490 + cell $eq $eq$libresoc.v:160006$8474 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -326978,34 +298348,34 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \mul_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:158698$8490_Y + connect \Y $eq$libresoc.v:160006$8474_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:158696$8487 + cell $pos $extend$libresoc.v:160004$8471 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:158696$8487_Y + connect \Y $extend$libresoc.v:160004$8471_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:158700$8492 + cell $not $not$libresoc.v:160008$8476 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:158700$8492_Y + connect \Y $not$libresoc.v:160008$8476_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:158703$8495 + cell $not $not$libresoc.v:160011$8479 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:158703$8495_Y + connect \Y $not$libresoc.v:160011$8479_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:158702$8494 + cell $or $or$libresoc.v:160010$8478 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327013,10 +298383,10 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:158702$8494_Y + connect \Y $or$libresoc.v:160010$8478_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - cell $or $or$libresoc.v:158705$8497 + cell $or $or$libresoc.v:160013$8481 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327024,39 +298394,39 @@ module \output$100 parameter \Y_WIDTH 1 connect \A \xer_so connect \B \xer_ov [0] - connect \Y $or$libresoc.v:158705$8497_Y + connect \Y $or$libresoc.v:160013$8481_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:158696$8488 + cell $pos $pos$libresoc.v:160004$8472 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:158696$8487_Y - connect \Y $pos$libresoc.v:158696$8488_Y + connect \A $extend$libresoc.v:160004$8471_Y + connect \Y $pos$libresoc.v:160004$8472_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:158699$8491 + cell $reduce_or $reduce_or$libresoc.v:160007$8475 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:158699$8491_Y + connect \Y $reduce_or$libresoc.v:160007$8475_Y end - attribute \src "libresoc.v:158386.7-158386.20" - process $proc$libresoc.v:158386$8508 + attribute \src "libresoc.v:159694.7-159694.20" + process $proc$libresoc.v:159694$8492 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:158706.3-158717.6" - process $proc$libresoc.v:158706$8498 + attribute \src "libresoc.v:160014.3-160025.6" + process $proc$libresoc.v:160014$8482 assign { } { } assign $0\so[0:0] $1\so[0:0] - attribute \src "libresoc.v:158707.5-158707.29" + attribute \src "libresoc.v:160015.5-160015.29" switch \initial - attribute \src "libresoc.v:158707.9-158707.17" + attribute \src "libresoc.v:160015.9-160015.17" case 1'1 case end @@ -327074,13 +298444,13 @@ module \output$100 sync always update \so $0\so[0:0] end - attribute \src "libresoc.v:158718.3-158729.6" - process $proc$libresoc.v:158718$8499 + attribute \src "libresoc.v:160026.3-160037.6" + process $proc$libresoc.v:160026$8483 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:158719.5-158719.29" + attribute \src "libresoc.v:160027.5-160027.29" switch \initial - attribute \src "libresoc.v:158719.9-158719.17" + attribute \src "libresoc.v:160027.9-160027.17" case 1'1 case end @@ -327098,14 +298468,14 @@ module \output$100 sync always update \cr0 $0\cr0[3:0] end - attribute \src "libresoc.v:158730.3-158739.6" - process $proc$libresoc.v:158730$8500 + attribute \src "libresoc.v:160038.3-160047.6" + process $proc$libresoc.v:160038$8484 assign { } { } assign { } { } - assign $0\xer_so$18[0:0]$8501 $1\xer_so$18[0:0]$8502 - attribute \src "libresoc.v:158731.5-158731.29" + assign $0\xer_so$18[0:0]$8485 $1\xer_so$18[0:0]$8486 + attribute \src "libresoc.v:160039.5-160039.29" switch \initial - attribute \src "libresoc.v:158731.9-158731.17" + attribute \src "libresoc.v:160039.9-160039.17" case 1'1 case end @@ -327114,21 +298484,21 @@ module \output$100 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_so$18[0:0]$8502 \$41 + assign $1\xer_so$18[0:0]$8486 \$41 case - assign $1\xer_so$18[0:0]$8502 1'0 + assign $1\xer_so$18[0:0]$8486 1'0 end sync always - update \xer_so$18 $0\xer_so$18[0:0]$8501 + update \xer_so$18 $0\xer_so$18[0:0]$8485 end - attribute \src "libresoc.v:158740.3-158749.6" - process $proc$libresoc.v:158740$8503 + attribute \src "libresoc.v:160048.3-160057.6" + process $proc$libresoc.v:160048$8487 assign { } { } assign { } { } assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "libresoc.v:158741.5-158741.29" + attribute \src "libresoc.v:160049.5-160049.29" switch \initial - attribute \src "libresoc.v:158741.9-158741.17" + attribute \src "libresoc.v:160049.9-160049.17" case 1'1 case end @@ -327144,14 +298514,14 @@ module \output$100 sync always update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:158750.3-158759.6" - process $proc$libresoc.v:158750$8504 + attribute \src "libresoc.v:160058.3-160067.6" + process $proc$libresoc.v:160058$8488 assign { } { } assign { } { } - assign $0\xer_ov$17[1:0]$8505 $1\xer_ov$17[1:0]$8506 - attribute \src "libresoc.v:158751.5-158751.29" + assign $0\xer_ov$17[1:0]$8489 $1\xer_ov$17[1:0]$8490 + attribute \src "libresoc.v:160059.5-160059.29" switch \initial - attribute \src "libresoc.v:158751.9-158751.17" + attribute \src "libresoc.v:160059.9-160059.17" case 1'1 case end @@ -327160,21 +298530,21 @@ module \output$100 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_ov$17[1:0]$8506 \xer_ov + assign $1\xer_ov$17[1:0]$8490 \xer_ov case - assign $1\xer_ov$17[1:0]$8506 2'00 + assign $1\xer_ov$17[1:0]$8490 2'00 end sync always - update \xer_ov$17 $0\xer_ov$17[1:0]$8505 + update \xer_ov$17 $0\xer_ov$17[1:0]$8489 end - attribute \src "libresoc.v:158760.3-158769.6" - process $proc$libresoc.v:158760$8507 + attribute \src "libresoc.v:160068.3-160077.6" + process $proc$libresoc.v:160068$8491 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:158761.5-158761.29" + attribute \src "libresoc.v:160069.5-160069.29" switch \initial - attribute \src "libresoc.v:158761.9-158761.17" + attribute \src "libresoc.v:160069.9-160069.17" case 1'1 case end @@ -327190,17 +298560,17 @@ module \output$100 sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - connect \$19 $and$libresoc.v:158695$8486_Y - connect \$22 $pos$libresoc.v:158696$8488_Y - connect \$24 $eq$libresoc.v:158697$8489_Y - connect \$26 $eq$libresoc.v:158698$8490_Y - connect \$28 $reduce_or$libresoc.v:158699$8491_Y - connect \$30 $not$libresoc.v:158700$8492_Y - connect \$32 $and$libresoc.v:158701$8493_Y - connect \$34 $or$libresoc.v:158702$8494_Y - connect \$36 $not$libresoc.v:158703$8495_Y - connect \$39 $and$libresoc.v:158704$8496_Y - connect \$41 $or$libresoc.v:158705$8497_Y + connect \$19 $and$libresoc.v:160003$8470_Y + connect \$22 $pos$libresoc.v:160004$8472_Y + connect \$24 $eq$libresoc.v:160005$8473_Y + connect \$26 $eq$libresoc.v:160006$8474_Y + connect \$28 $reduce_or$libresoc.v:160007$8475_Y + connect \$30 $not$libresoc.v:160008$8476_Y + connect \$32 $and$libresoc.v:160009$8477_Y + connect \$34 $or$libresoc.v:160010$8478_Y + connect \$36 $not$libresoc.v:160011$8479_Y + connect \$39 $and$libresoc.v:160012$8480_Y + connect \$41 $or$libresoc.v:160013$8481_Y connect \oe$38 \$39 connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } connect \muxid$1 \muxid @@ -327218,35 +298588,35 @@ module \output$100 connect \o$21 \$22 connect \oe \$19 end -attribute \src "libresoc.v:158790.1-159144.10" +attribute \src "libresoc.v:160098.1-160452.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.output" attribute \generator "nMigen" module \output$118 - attribute \src "libresoc.v:159116.3-159127.6" + attribute \src "libresoc.v:160424.3-160435.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:158791.7-158791.20" + attribute \src "libresoc.v:160099.7-160099.20" wire $0\initial[0:0] - attribute \src "libresoc.v:159116.3-159127.6" + attribute \src "libresoc.v:160424.3-160435.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:159113.18-159113.112" - wire $and$libresoc.v:159113$8515_Y - attribute \src "libresoc.v:159109.18-159109.122" - wire $eq$libresoc.v:159109$8511_Y - attribute \src "libresoc.v:159110.18-159110.122" - wire $eq$libresoc.v:159110$8512_Y - attribute \src "libresoc.v:159108.18-159108.101" - wire width 65 $extend$libresoc.v:159108$8509_Y - attribute \src "libresoc.v:159112.18-159112.107" - wire $not$libresoc.v:159112$8514_Y - attribute \src "libresoc.v:159115.18-159115.107" - wire $not$libresoc.v:159115$8517_Y - attribute \src "libresoc.v:159114.18-159114.115" - wire $or$libresoc.v:159114$8516_Y - attribute \src "libresoc.v:159108.18-159108.101" - wire width 65 $pos$libresoc.v:159108$8510_Y - attribute \src "libresoc.v:159111.18-159111.105" - wire $reduce_or$libresoc.v:159111$8513_Y + attribute \src "libresoc.v:160421.18-160421.112" + wire $and$libresoc.v:160421$8499_Y + attribute \src "libresoc.v:160417.18-160417.122" + wire $eq$libresoc.v:160417$8495_Y + attribute \src "libresoc.v:160418.18-160418.122" + wire $eq$libresoc.v:160418$8496_Y + attribute \src "libresoc.v:160416.18-160416.101" + wire width 65 $extend$libresoc.v:160416$8493_Y + attribute \src "libresoc.v:160420.18-160420.107" + wire $not$libresoc.v:160420$8498_Y + attribute \src "libresoc.v:160423.18-160423.107" + wire $not$libresoc.v:160423$8501_Y + attribute \src "libresoc.v:160422.18-160422.115" + wire $or$libresoc.v:160422$8500_Y + attribute \src "libresoc.v:160416.18-160416.101" + wire width 65 $pos$libresoc.v:160416$8494_Y + attribute \src "libresoc.v:160419.18-160419.105" + wire $reduce_or$libresoc.v:160419$8497_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 65 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" @@ -327271,7 +298641,7 @@ module \output$118 wire width 4 output 43 \cr_a$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 44 \cr_a_ok - attribute \src "libresoc.v:158791.7-158791.15" + attribute \src "libresoc.v:160099.7-160099.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -327566,7 +298936,7 @@ module \output$118 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 21 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:159113$8515 + cell $and $and$libresoc.v:160421$8499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327574,10 +298944,10 @@ module \output$118 parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$32 - connect \Y $and$libresoc.v:159113$8515_Y + connect \Y $and$libresoc.v:160421$8499_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:159109$8511 + cell $eq $eq$libresoc.v:160417$8495 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -327585,10 +298955,10 @@ module \output$118 parameter \Y_WIDTH 1 connect \A \sr_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:159109$8511_Y + connect \Y $eq$libresoc.v:160417$8495_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:159110$8512 + cell $eq $eq$libresoc.v:160418$8496 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -327596,34 +298966,34 @@ module \output$118 parameter \Y_WIDTH 1 connect \A \sr_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:159110$8512_Y + connect \Y $eq$libresoc.v:160418$8496_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:159108$8509 + cell $pos $extend$libresoc.v:160416$8493 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:159108$8509_Y + connect \Y $extend$libresoc.v:160416$8493_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:159112$8514 + cell $not $not$libresoc.v:160420$8498 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:159112$8514_Y + connect \Y $not$libresoc.v:160420$8498_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:159115$8517 + cell $not $not$libresoc.v:160423$8501 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:159115$8517_Y + connect \Y $not$libresoc.v:160423$8501_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:159114$8516 + cell $or $or$libresoc.v:160422$8500 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -327631,39 +299001,39 @@ module \output$118 parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:159114$8516_Y + connect \Y $or$libresoc.v:160422$8500_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:159108$8510 + cell $pos $pos$libresoc.v:160416$8494 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:159108$8509_Y - connect \Y $pos$libresoc.v:159108$8510_Y + connect \A $extend$libresoc.v:160416$8493_Y + connect \Y $pos$libresoc.v:160416$8494_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:159111$8513 + cell $reduce_or $reduce_or$libresoc.v:160419$8497 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:159111$8513_Y + connect \Y $reduce_or$libresoc.v:160419$8497_Y end - attribute \src "libresoc.v:158791.7-158791.20" - process $proc$libresoc.v:158791$8519 + attribute \src "libresoc.v:160099.7-160099.20" + process $proc$libresoc.v:160099$8503 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:159116.3-159127.6" - process $proc$libresoc.v:159116$8518 + attribute \src "libresoc.v:160424.3-160435.6" + process $proc$libresoc.v:160424$8502 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:159117.5-159117.29" + attribute \src "libresoc.v:160425.5-160425.29" switch \initial - attribute \src "libresoc.v:159117.9-159117.17" + attribute \src "libresoc.v:160425.9-160425.17" case 1'1 case end @@ -327681,14 +299051,14 @@ module \output$118 sync always update \cr0 $0\cr0[3:0] end - connect \$24 $pos$libresoc.v:159108$8510_Y - connect \$26 $eq$libresoc.v:159109$8511_Y - connect \$28 $eq$libresoc.v:159110$8512_Y - connect \$30 $reduce_or$libresoc.v:159111$8513_Y - connect \$32 $not$libresoc.v:159112$8514_Y - connect \$34 $and$libresoc.v:159113$8515_Y - connect \$36 $or$libresoc.v:159114$8516_Y - connect \$38 $not$libresoc.v:159115$8517_Y + connect \$24 $pos$libresoc.v:160416$8494_Y + connect \$26 $eq$libresoc.v:160417$8495_Y + connect \$28 $eq$libresoc.v:160418$8496_Y + connect \$30 $reduce_or$libresoc.v:160419$8497_Y + connect \$32 $not$libresoc.v:160420$8498_Y + connect \$34 $and$libresoc.v:160421$8499_Y + connect \$36 $or$libresoc.v:160422$8500_Y + connect \$38 $not$libresoc.v:160423$8501_Y connect { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } connect \muxid$1 \muxid connect \cr_a_ok \sr_op__write_cr0 @@ -327706,45 +299076,45 @@ module \output$118 connect \target \o$23 [63:0] connect \o$23 \$24 end -attribute \src "libresoc.v:159148.1-159515.10" +attribute \src "libresoc.v:160456.1-160823.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.output" attribute \generator "nMigen" module \output$54 - attribute \src "libresoc.v:159490.3-159501.6" + attribute \src "libresoc.v:160798.3-160809.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:159149.7-159149.20" + attribute \src "libresoc.v:160457.7-160457.20" wire $0\initial[0:0] - attribute \src "libresoc.v:159478.3-159489.6" - wire width 65 $0\o$23[64:0]$8533 - attribute \src "libresoc.v:159490.3-159501.6" + attribute \src "libresoc.v:160786.3-160797.6" + wire width 65 $0\o$23[64:0]$8517 + attribute \src "libresoc.v:160798.3-160809.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:159478.3-159489.6" - wire width 65 $1\o$23[64:0]$8534 - attribute \src "libresoc.v:159475.18-159475.112" - wire $and$libresoc.v:159475$8529_Y - attribute \src "libresoc.v:159471.18-159471.127" - wire $eq$libresoc.v:159471$8525_Y - attribute \src "libresoc.v:159472.18-159472.127" - wire $eq$libresoc.v:159472$8526_Y - attribute \src "libresoc.v:159469.18-159469.103" - wire width 65 $extend$libresoc.v:159469$8521_Y - attribute \src "libresoc.v:159470.18-159470.101" - wire width 65 $extend$libresoc.v:159470$8523_Y - attribute \src "libresoc.v:159468.18-159468.100" - wire width 64 $not$libresoc.v:159468$8520_Y - attribute \src "libresoc.v:159474.18-159474.107" - wire $not$libresoc.v:159474$8528_Y - attribute \src "libresoc.v:159477.18-159477.107" - wire $not$libresoc.v:159477$8531_Y - attribute \src "libresoc.v:159476.18-159476.115" - wire $or$libresoc.v:159476$8530_Y - attribute \src "libresoc.v:159469.18-159469.103" - wire width 65 $pos$libresoc.v:159469$8522_Y - attribute \src "libresoc.v:159470.18-159470.101" - wire width 65 $pos$libresoc.v:159470$8524_Y - attribute \src "libresoc.v:159473.18-159473.105" - wire $reduce_or$libresoc.v:159473$8527_Y + attribute \src "libresoc.v:160786.3-160797.6" + wire width 65 $1\o$23[64:0]$8518 + attribute \src "libresoc.v:160783.18-160783.112" + wire $and$libresoc.v:160783$8513_Y + attribute \src "libresoc.v:160779.18-160779.127" + wire $eq$libresoc.v:160779$8509_Y + attribute \src "libresoc.v:160780.18-160780.127" + wire $eq$libresoc.v:160780$8510_Y + attribute \src "libresoc.v:160777.18-160777.103" + wire width 65 $extend$libresoc.v:160777$8505_Y + attribute \src "libresoc.v:160778.18-160778.101" + wire width 65 $extend$libresoc.v:160778$8507_Y + attribute \src "libresoc.v:160776.18-160776.100" + wire width 64 $not$libresoc.v:160776$8504_Y + attribute \src "libresoc.v:160782.18-160782.107" + wire $not$libresoc.v:160782$8512_Y + attribute \src "libresoc.v:160785.18-160785.107" + wire $not$libresoc.v:160785$8515_Y + attribute \src "libresoc.v:160784.18-160784.115" + wire $or$libresoc.v:160784$8514_Y + attribute \src "libresoc.v:160777.18-160777.103" + wire width 65 $pos$libresoc.v:160777$8506_Y + attribute \src "libresoc.v:160778.18-160778.101" + wire width 65 $pos$libresoc.v:160778$8508_Y + attribute \src "libresoc.v:160781.18-160781.105" + wire $reduce_or$libresoc.v:160781$8511_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" wire width 65 \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" @@ -327773,7 +299143,7 @@ module \output$54 wire width 4 output 44 \cr_a$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 45 \cr_a_ok - attribute \src "libresoc.v:159149.7-159149.15" + attribute \src "libresoc.v:160457.7-160457.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -328066,7 +299436,7 @@ module \output$54 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 22 \xer_so attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:159475$8529 + cell $and $and$libresoc.v:160783$8513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328074,10 +299444,10 @@ module \output$54 parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$36 - connect \Y $and$libresoc.v:159475$8529_Y + connect \Y $and$libresoc.v:160783$8513_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:159471$8525 + cell $eq $eq$libresoc.v:160779$8509 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -328085,10 +299455,10 @@ module \output$54 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:159471$8525_Y + connect \Y $eq$libresoc.v:160779$8509_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:159472$8526 + cell $eq $eq$libresoc.v:160780$8510 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -328096,50 +299466,50 @@ module \output$54 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:159472$8526_Y + connect \Y $eq$libresoc.v:160780$8510_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $extend$libresoc.v:159469$8521 + cell $pos $extend$libresoc.v:160777$8505 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \$25 - connect \Y $extend$libresoc.v:159469$8521_Y + connect \Y $extend$libresoc.v:160777$8505_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:159470$8523 + cell $pos $extend$libresoc.v:160778$8507 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:159470$8523_Y + connect \Y $extend$libresoc.v:160778$8507_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $not $not$libresoc.v:159468$8520 + cell $not $not$libresoc.v:160776$8504 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \o - connect \Y $not$libresoc.v:159468$8520_Y + connect \Y $not$libresoc.v:160776$8504_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:159474$8528 + cell $not $not$libresoc.v:160782$8512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:159474$8528_Y + connect \Y $not$libresoc.v:160782$8512_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:159477$8531 + cell $not $not$libresoc.v:160785$8515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:159477$8531_Y + connect \Y $not$libresoc.v:160785$8515_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:159476$8530 + cell $or $or$libresoc.v:160784$8514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328147,47 +299517,47 @@ module \output$54 parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:159476$8530_Y + connect \Y $or$libresoc.v:160784$8514_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $pos$libresoc.v:159469$8522 + cell $pos $pos$libresoc.v:160777$8506 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:159469$8521_Y - connect \Y $pos$libresoc.v:159469$8522_Y + connect \A $extend$libresoc.v:160777$8505_Y + connect \Y $pos$libresoc.v:160777$8506_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:159470$8524 + cell $pos $pos$libresoc.v:160778$8508 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:159470$8523_Y - connect \Y $pos$libresoc.v:159470$8524_Y + connect \A $extend$libresoc.v:160778$8507_Y + connect \Y $pos$libresoc.v:160778$8508_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:159473$8527 + cell $reduce_or $reduce_or$libresoc.v:160781$8511 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:159473$8527_Y + connect \Y $reduce_or$libresoc.v:160781$8511_Y end - attribute \src "libresoc.v:159149.7-159149.20" - process $proc$libresoc.v:159149$8536 + attribute \src "libresoc.v:160457.7-160457.20" + process $proc$libresoc.v:160457$8520 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:159478.3-159489.6" - process $proc$libresoc.v:159478$8532 + attribute \src "libresoc.v:160786.3-160797.6" + process $proc$libresoc.v:160786$8516 assign { } { } - assign $0\o$23[64:0]$8533 $1\o$23[64:0]$8534 - attribute \src "libresoc.v:159479.5-159479.29" + assign $0\o$23[64:0]$8517 $1\o$23[64:0]$8518 + attribute \src "libresoc.v:160787.5-160787.29" switch \initial - attribute \src "libresoc.v:159479.9-159479.17" + attribute \src "libresoc.v:160787.9-160787.17" case 1'1 case end @@ -328196,22 +299566,22 @@ module \output$54 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\o$23[64:0]$8534 \$24 + assign $1\o$23[64:0]$8518 \$24 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\o$23[64:0]$8534 \$28 + assign $1\o$23[64:0]$8518 \$28 end sync always - update \o$23 $0\o$23[64:0]$8533 + update \o$23 $0\o$23[64:0]$8517 end - attribute \src "libresoc.v:159490.3-159501.6" - process $proc$libresoc.v:159490$8535 + attribute \src "libresoc.v:160798.3-160809.6" + process $proc$libresoc.v:160798$8519 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:159491.5-159491.29" + attribute \src "libresoc.v:160799.5-160799.29" switch \initial - attribute \src "libresoc.v:159491.9-159491.17" + attribute \src "libresoc.v:160799.9-160799.17" case 1'1 case end @@ -328229,16 +299599,16 @@ module \output$54 sync always update \cr0 $0\cr0[3:0] end - connect \$25 $not$libresoc.v:159468$8520_Y - connect \$24 $pos$libresoc.v:159469$8522_Y - connect \$28 $pos$libresoc.v:159470$8524_Y - connect \$30 $eq$libresoc.v:159471$8525_Y - connect \$32 $eq$libresoc.v:159472$8526_Y - connect \$34 $reduce_or$libresoc.v:159473$8527_Y - connect \$36 $not$libresoc.v:159474$8528_Y - connect \$38 $and$libresoc.v:159475$8529_Y - connect \$40 $or$libresoc.v:159476$8530_Y - connect \$42 $not$libresoc.v:159477$8531_Y + connect \$25 $not$libresoc.v:160776$8504_Y + connect \$24 $pos$libresoc.v:160777$8506_Y + connect \$28 $pos$libresoc.v:160778$8508_Y + connect \$30 $eq$libresoc.v:160779$8509_Y + connect \$32 $eq$libresoc.v:160780$8510_Y + connect \$34 $reduce_or$libresoc.v:160781$8511_Y + connect \$36 $not$libresoc.v:160782$8512_Y + connect \$38 $and$libresoc.v:160783$8513_Y + connect \$40 $or$libresoc.v:160784$8514_Y + connect \$42 $not$libresoc.v:160785$8515_Y connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid connect \cr_a_ok \logical_op__write_cr0 @@ -328253,71 +299623,71 @@ module \output$54 connect \is_cmp \$30 connect \target \o$23 [63:0] end -attribute \src "libresoc.v:159519.1-159969.10" +attribute \src "libresoc.v:160827.1-161277.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.output" attribute \generator "nMigen" module \output$83 - attribute \src "libresoc.v:159890.3-159901.6" + attribute \src "libresoc.v:161198.3-161209.6" wire width 4 $0\cr0[3:0] - attribute \src "libresoc.v:159520.7-159520.20" + attribute \src "libresoc.v:160828.7-160828.20" wire $0\initial[0:0] - attribute \src "libresoc.v:159902.3-159913.6" - wire width 65 $0\o$27[64:0]$8555 - attribute \src "libresoc.v:159878.3-159889.6" + attribute \src "libresoc.v:161210.3-161221.6" + wire width 65 $0\o$27[64:0]$8539 + attribute \src "libresoc.v:161186.3-161197.6" wire $0\so[0:0] - attribute \src "libresoc.v:159934.3-159943.6" - wire width 2 $0\xer_ov$23[1:0]$8562 - attribute \src "libresoc.v:159944.3-159953.6" + attribute \src "libresoc.v:161242.3-161251.6" + wire width 2 $0\xer_ov$23[1:0]$8546 + attribute \src "libresoc.v:161252.3-161261.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:159914.3-159923.6" - wire $0\xer_so$24[0:0]$8558 - attribute \src "libresoc.v:159924.3-159933.6" + attribute \src "libresoc.v:161222.3-161231.6" + wire $0\xer_so$24[0:0]$8542 + attribute \src "libresoc.v:161232.3-161241.6" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:159890.3-159901.6" + attribute \src "libresoc.v:161198.3-161209.6" wire width 4 $1\cr0[3:0] - attribute \src "libresoc.v:159902.3-159913.6" - wire width 65 $1\o$27[64:0]$8556 - attribute \src "libresoc.v:159878.3-159889.6" + attribute \src "libresoc.v:161210.3-161221.6" + wire width 65 $1\o$27[64:0]$8540 + attribute \src "libresoc.v:161186.3-161197.6" wire $1\so[0:0] - attribute \src "libresoc.v:159934.3-159943.6" - wire width 2 $1\xer_ov$23[1:0]$8563 - attribute \src "libresoc.v:159944.3-159953.6" + attribute \src "libresoc.v:161242.3-161251.6" + wire width 2 $1\xer_ov$23[1:0]$8547 + attribute \src "libresoc.v:161252.3-161261.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:159914.3-159923.6" - wire $1\xer_so$24[0:0]$8559 - attribute \src "libresoc.v:159924.3-159933.6" + attribute \src "libresoc.v:161222.3-161231.6" + wire $1\xer_so$24[0:0]$8543 + attribute \src "libresoc.v:161232.3-161241.6" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:159865.18-159865.136" - wire $and$libresoc.v:159865$8537_Y - attribute \src "libresoc.v:159873.18-159873.112" - wire $and$libresoc.v:159873$8547_Y - attribute \src "libresoc.v:159876.18-159876.133" - wire $and$libresoc.v:159876$8550_Y - attribute \src "libresoc.v:159869.18-159869.127" - wire $eq$libresoc.v:159869$8543_Y - attribute \src "libresoc.v:159870.18-159870.127" - wire $eq$libresoc.v:159870$8544_Y - attribute \src "libresoc.v:159867.18-159867.103" - wire width 65 $extend$libresoc.v:159867$8539_Y - attribute \src "libresoc.v:159868.18-159868.101" - wire width 65 $extend$libresoc.v:159868$8541_Y - attribute \src "libresoc.v:159866.18-159866.100" - wire width 64 $not$libresoc.v:159866$8538_Y - attribute \src "libresoc.v:159872.18-159872.107" - wire $not$libresoc.v:159872$8546_Y - attribute \src "libresoc.v:159875.18-159875.107" - wire $not$libresoc.v:159875$8549_Y - attribute \src "libresoc.v:159874.18-159874.115" - wire $or$libresoc.v:159874$8548_Y - attribute \src "libresoc.v:159877.18-159877.112" - wire $or$libresoc.v:159877$8551_Y - attribute \src "libresoc.v:159867.18-159867.103" - wire width 65 $pos$libresoc.v:159867$8540_Y - attribute \src "libresoc.v:159868.18-159868.101" - wire width 65 $pos$libresoc.v:159868$8542_Y - attribute \src "libresoc.v:159871.18-159871.105" - wire $reduce_or$libresoc.v:159871$8545_Y + attribute \src "libresoc.v:161173.18-161173.136" + wire $and$libresoc.v:161173$8521_Y + attribute \src "libresoc.v:161181.18-161181.112" + wire $and$libresoc.v:161181$8531_Y + attribute \src "libresoc.v:161184.18-161184.133" + wire $and$libresoc.v:161184$8534_Y + attribute \src "libresoc.v:161177.18-161177.127" + wire $eq$libresoc.v:161177$8527_Y + attribute \src "libresoc.v:161178.18-161178.127" + wire $eq$libresoc.v:161178$8528_Y + attribute \src "libresoc.v:161175.18-161175.103" + wire width 65 $extend$libresoc.v:161175$8523_Y + attribute \src "libresoc.v:161176.18-161176.101" + wire width 65 $extend$libresoc.v:161176$8525_Y + attribute \src "libresoc.v:161174.18-161174.100" + wire width 64 $not$libresoc.v:161174$8522_Y + attribute \src "libresoc.v:161180.18-161180.107" + wire $not$libresoc.v:161180$8530_Y + attribute \src "libresoc.v:161183.18-161183.107" + wire $not$libresoc.v:161183$8533_Y + attribute \src "libresoc.v:161182.18-161182.115" + wire $or$libresoc.v:161182$8532_Y + attribute \src "libresoc.v:161185.18-161185.112" + wire $or$libresoc.v:161185$8535_Y + attribute \src "libresoc.v:161175.18-161175.103" + wire width 65 $pos$libresoc.v:161175$8524_Y + attribute \src "libresoc.v:161176.18-161176.101" + wire width 65 $pos$libresoc.v:161176$8526_Y + attribute \src "libresoc.v:161179.18-161179.105" + wire $reduce_or$libresoc.v:161179$8529_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" wire \$25 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" @@ -328352,7 +299722,7 @@ module \output$83 wire width 4 output 45 \cr_a$22 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 46 \cr_a_ok - attribute \src "libresoc.v:159520.7-159520.15" + attribute \src "libresoc.v:160828.7-160828.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" wire \is_cmp @@ -328661,7 +300031,7 @@ module \output$83 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 50 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" - cell $and $and$libresoc.v:159865$8537 + cell $and $and$libresoc.v:161173$8521 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328669,10 +300039,10 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \logical_op__oe__oe connect \B \logical_op__oe__ok - connect \Y $and$libresoc.v:159865$8537_Y + connect \Y $and$libresoc.v:161173$8521_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $and$libresoc.v:159873$8547 + cell $and $and$libresoc.v:161181$8531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328680,10 +300050,10 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \is_nzero connect \B \$40 - connect \Y $and$libresoc.v:159873$8547_Y + connect \Y $and$libresoc.v:161181$8531_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - cell $and $and$libresoc.v:159876$8550 + cell $and $and$libresoc.v:161184$8534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328691,10 +300061,10 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \logical_op__oe__oe connect \B \logical_op__oe__ok - connect \Y $and$libresoc.v:159876$8550_Y + connect \Y $and$libresoc.v:161184$8534_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $eq$libresoc.v:159869$8543 + cell $eq $eq$libresoc.v:161177$8527 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -328702,10 +300072,10 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001010 - connect \Y $eq$libresoc.v:159869$8543_Y + connect \Y $eq$libresoc.v:161177$8527_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $eq$libresoc.v:159870$8544 + cell $eq $eq$libresoc.v:161178$8528 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -328713,50 +300083,50 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0001100 - connect \Y $eq$libresoc.v:159870$8544_Y + connect \Y $eq$libresoc.v:161178$8528_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $extend$libresoc.v:159867$8539 + cell $pos $extend$libresoc.v:161175$8523 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \$29 - connect \Y $extend$libresoc.v:159867$8539_Y + connect \Y $extend$libresoc.v:161175$8523_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:159868$8541 + cell $pos $extend$libresoc.v:161176$8525 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \o - connect \Y $extend$libresoc.v:159868$8541_Y + connect \Y $extend$libresoc.v:161176$8525_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $not $not$libresoc.v:159866$8538 + cell $not $not$libresoc.v:161174$8522 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \o - connect \Y $not$libresoc.v:159866$8538_Y + connect \Y $not$libresoc.v:161174$8522_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $not$libresoc.v:159872$8546 + cell $not $not$libresoc.v:161180$8530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msb_test - connect \Y $not$libresoc.v:159872$8546_Y + connect \Y $not$libresoc.v:161180$8530_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $not$libresoc.v:159875$8549 + cell $not $not$libresoc.v:161183$8533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_nzero - connect \Y $not$libresoc.v:159875$8549_Y + connect \Y $not$libresoc.v:161183$8533_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $or$libresoc.v:159874$8548 + cell $or $or$libresoc.v:161182$8532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328764,10 +300134,10 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \is_cmpeqb connect \B \is_cmp - connect \Y $or$libresoc.v:159874$8548_Y + connect \Y $or$libresoc.v:161182$8532_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - cell $or $or$libresoc.v:159877$8551 + cell $or $or$libresoc.v:161185$8535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -328775,47 +300145,47 @@ module \output$83 parameter \Y_WIDTH 1 connect \A \xer_so connect \B \xer_ov [0] - connect \Y $or$libresoc.v:159877$8551_Y + connect \Y $or$libresoc.v:161185$8535_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $pos$libresoc.v:159867$8540 + cell $pos $pos$libresoc.v:161175$8524 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:159867$8539_Y - connect \Y $pos$libresoc.v:159867$8540_Y + connect \A $extend$libresoc.v:161175$8523_Y + connect \Y $pos$libresoc.v:161175$8524_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:159868$8542 + cell $pos $pos$libresoc.v:161176$8526 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:159868$8541_Y - connect \Y $pos$libresoc.v:159868$8542_Y + connect \A $extend$libresoc.v:161176$8525_Y + connect \Y $pos$libresoc.v:161176$8526_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_or $reduce_or$libresoc.v:159871$8545 + cell $reduce_or $reduce_or$libresoc.v:161179$8529 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \target - connect \Y $reduce_or$libresoc.v:159871$8545_Y + connect \Y $reduce_or$libresoc.v:161179$8529_Y end - attribute \src "libresoc.v:159520.7-159520.20" - process $proc$libresoc.v:159520$8565 + attribute \src "libresoc.v:160828.7-160828.20" + process $proc$libresoc.v:160828$8549 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:159878.3-159889.6" - process $proc$libresoc.v:159878$8552 + attribute \src "libresoc.v:161186.3-161197.6" + process $proc$libresoc.v:161186$8536 assign { } { } assign $0\so[0:0] $1\so[0:0] - attribute \src "libresoc.v:159879.5-159879.29" + attribute \src "libresoc.v:161187.5-161187.29" switch \initial - attribute \src "libresoc.v:159879.9-159879.17" + attribute \src "libresoc.v:161187.9-161187.17" case 1'1 case end @@ -328833,13 +300203,13 @@ module \output$83 sync always update \so $0\so[0:0] end - attribute \src "libresoc.v:159890.3-159901.6" - process $proc$libresoc.v:159890$8553 + attribute \src "libresoc.v:161198.3-161209.6" + process $proc$libresoc.v:161198$8537 assign { } { } assign $0\cr0[3:0] $1\cr0[3:0] - attribute \src "libresoc.v:159891.5-159891.29" + attribute \src "libresoc.v:161199.5-161199.29" switch \initial - attribute \src "libresoc.v:159891.9-159891.17" + attribute \src "libresoc.v:161199.9-161199.17" case 1'1 case end @@ -328857,13 +300227,13 @@ module \output$83 sync always update \cr0 $0\cr0[3:0] end - attribute \src "libresoc.v:159902.3-159913.6" - process $proc$libresoc.v:159902$8554 + attribute \src "libresoc.v:161210.3-161221.6" + process $proc$libresoc.v:161210$8538 assign { } { } - assign $0\o$27[64:0]$8555 $1\o$27[64:0]$8556 - attribute \src "libresoc.v:159903.5-159903.29" + assign $0\o$27[64:0]$8539 $1\o$27[64:0]$8540 + attribute \src "libresoc.v:161211.5-161211.29" switch \initial - attribute \src "libresoc.v:159903.9-159903.17" + attribute \src "libresoc.v:161211.9-161211.17" case 1'1 case end @@ -328872,23 +300242,23 @@ module \output$83 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\o$27[64:0]$8556 \$28 + assign $1\o$27[64:0]$8540 \$28 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\o$27[64:0]$8556 \$32 + assign $1\o$27[64:0]$8540 \$32 end sync always - update \o$27 $0\o$27[64:0]$8555 + update \o$27 $0\o$27[64:0]$8539 end - attribute \src "libresoc.v:159914.3-159923.6" - process $proc$libresoc.v:159914$8557 + attribute \src "libresoc.v:161222.3-161231.6" + process $proc$libresoc.v:161222$8541 assign { } { } assign { } { } - assign $0\xer_so$24[0:0]$8558 $1\xer_so$24[0:0]$8559 - attribute \src "libresoc.v:159915.5-159915.29" + assign $0\xer_so$24[0:0]$8542 $1\xer_so$24[0:0]$8543 + attribute \src "libresoc.v:161223.5-161223.29" switch \initial - attribute \src "libresoc.v:159915.9-159915.17" + attribute \src "libresoc.v:161223.9-161223.17" case 1'1 case end @@ -328897,21 +300267,21 @@ module \output$83 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_so$24[0:0]$8559 \$51 + assign $1\xer_so$24[0:0]$8543 \$51 case - assign $1\xer_so$24[0:0]$8559 1'0 + assign $1\xer_so$24[0:0]$8543 1'0 end sync always - update \xer_so$24 $0\xer_so$24[0:0]$8558 + update \xer_so$24 $0\xer_so$24[0:0]$8542 end - attribute \src "libresoc.v:159924.3-159933.6" - process $proc$libresoc.v:159924$8560 + attribute \src "libresoc.v:161232.3-161241.6" + process $proc$libresoc.v:161232$8544 assign { } { } assign { } { } assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "libresoc.v:159925.5-159925.29" + attribute \src "libresoc.v:161233.5-161233.29" switch \initial - attribute \src "libresoc.v:159925.9-159925.17" + attribute \src "libresoc.v:161233.9-161233.17" case 1'1 case end @@ -328927,14 +300297,14 @@ module \output$83 sync always update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:159934.3-159943.6" - process $proc$libresoc.v:159934$8561 + attribute \src "libresoc.v:161242.3-161251.6" + process $proc$libresoc.v:161242$8545 assign { } { } assign { } { } - assign $0\xer_ov$23[1:0]$8562 $1\xer_ov$23[1:0]$8563 - attribute \src "libresoc.v:159935.5-159935.29" + assign $0\xer_ov$23[1:0]$8546 $1\xer_ov$23[1:0]$8547 + attribute \src "libresoc.v:161243.5-161243.29" switch \initial - attribute \src "libresoc.v:159935.9-159935.17" + attribute \src "libresoc.v:161243.9-161243.17" case 1'1 case end @@ -328943,21 +300313,21 @@ module \output$83 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_ov$23[1:0]$8563 \xer_ov + assign $1\xer_ov$23[1:0]$8547 \xer_ov case - assign $1\xer_ov$23[1:0]$8563 2'00 + assign $1\xer_ov$23[1:0]$8547 2'00 end sync always - update \xer_ov$23 $0\xer_ov$23[1:0]$8562 + update \xer_ov$23 $0\xer_ov$23[1:0]$8546 end - attribute \src "libresoc.v:159944.3-159953.6" - process $proc$libresoc.v:159944$8564 + attribute \src "libresoc.v:161252.3-161261.6" + process $proc$libresoc.v:161252$8548 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:159945.5-159945.29" + attribute \src "libresoc.v:161253.5-161253.29" switch \initial - attribute \src "libresoc.v:159945.9-159945.17" + attribute \src "libresoc.v:161253.9-161253.17" case 1'1 case end @@ -328973,19 +300343,19 @@ module \output$83 sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - connect \$25 $and$libresoc.v:159865$8537_Y - connect \$29 $not$libresoc.v:159866$8538_Y - connect \$28 $pos$libresoc.v:159867$8540_Y - connect \$32 $pos$libresoc.v:159868$8542_Y - connect \$34 $eq$libresoc.v:159869$8543_Y - connect \$36 $eq$libresoc.v:159870$8544_Y - connect \$38 $reduce_or$libresoc.v:159871$8545_Y - connect \$40 $not$libresoc.v:159872$8546_Y - connect \$42 $and$libresoc.v:159873$8547_Y - connect \$44 $or$libresoc.v:159874$8548_Y - connect \$46 $not$libresoc.v:159875$8549_Y - connect \$49 $and$libresoc.v:159876$8550_Y - connect \$51 $or$libresoc.v:159877$8551_Y + connect \$25 $and$libresoc.v:161173$8521_Y + connect \$29 $not$libresoc.v:161174$8522_Y + connect \$28 $pos$libresoc.v:161175$8524_Y + connect \$32 $pos$libresoc.v:161176$8526_Y + connect \$34 $eq$libresoc.v:161177$8527_Y + connect \$36 $eq$libresoc.v:161178$8528_Y + connect \$38 $reduce_or$libresoc.v:161179$8529_Y + connect \$40 $not$libresoc.v:161180$8530_Y + connect \$42 $and$libresoc.v:161181$8531_Y + connect \$44 $or$libresoc.v:161182$8532_Y + connect \$46 $not$libresoc.v:161183$8533_Y + connect \$49 $and$libresoc.v:161184$8534_Y + connect \$51 $or$libresoc.v:161185$8535_Y connect \oe$48 \$49 connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid @@ -329002,93 +300372,93 @@ module \output$83 connect \target \o$27 [63:0] connect \oe \$25 end -attribute \src "libresoc.v:159973.1-160455.10" +attribute \src "libresoc.v:161281.1-161763.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.output_stage" attribute \generator "nMigen" module \output_stage - attribute \src "libresoc.v:159974.7-159974.20" + attribute \src "libresoc.v:161282.7-161282.20" wire $0\initial[0:0] - attribute \src "libresoc.v:160336.3-160407.6" + attribute \src "libresoc.v:161644.3-161715.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:160408.3-160441.6" + attribute \src "libresoc.v:161716.3-161749.6" wire $0\ov[0:0] - attribute \src "libresoc.v:160336.3-160407.6" + attribute \src "libresoc.v:161644.3-161715.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:160408.3-160441.6" + attribute \src "libresoc.v:161716.3-161749.6" wire $1\ov[0:0] - attribute \src "libresoc.v:160336.3-160407.6" + attribute \src "libresoc.v:161644.3-161715.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:160408.3-160441.6" + attribute \src "libresoc.v:161716.3-161749.6" wire $2\ov[0:0] - attribute \src "libresoc.v:160336.3-160407.6" + attribute \src "libresoc.v:161644.3-161715.6" wire width 64 $3\o[63:0] - attribute \src "libresoc.v:160408.3-160441.6" + attribute \src "libresoc.v:161716.3-161749.6" wire $3\ov[0:0] - attribute \src "libresoc.v:160336.3-160407.6" + attribute \src "libresoc.v:161644.3-161715.6" wire width 64 $4\o[63:0] - attribute \src "libresoc.v:160336.3-160407.6" + attribute \src "libresoc.v:161644.3-161715.6" wire width 64 $5\o[63:0] - attribute \src "libresoc.v:160336.3-160407.6" + attribute \src "libresoc.v:161644.3-161715.6" wire width 64 $6\o[63:0] - attribute \src "libresoc.v:160336.3-160407.6" + attribute \src "libresoc.v:161644.3-161715.6" wire width 64 $7\o[63:0] - attribute \src "libresoc.v:160336.3-160407.6" + attribute \src "libresoc.v:161644.3-161715.6" wire width 64 $8\o[63:0] - attribute \src "libresoc.v:160327.18-160327.122" - wire $and$libresoc.v:160327$8579_Y - attribute \src "libresoc.v:160319.18-160319.109" - wire width 65 $extend$libresoc.v:160319$8567_Y - attribute \src "libresoc.v:160320.18-160320.100" - wire width 65 $extend$libresoc.v:160320$8569_Y - attribute \src "libresoc.v:160322.18-160322.113" - wire width 65 $extend$libresoc.v:160322$8572_Y - attribute \src "libresoc.v:160323.18-160323.104" - wire width 65 $extend$libresoc.v:160323$8574_Y - attribute \src "libresoc.v:160331.18-160331.114" - wire width 64 $extend$libresoc.v:160331$8583_Y - attribute \src "libresoc.v:160332.18-160332.114" - wire width 64 $extend$libresoc.v:160332$8585_Y - attribute \src "libresoc.v:160333.18-160333.114" - wire width 64 $extend$libresoc.v:160333$8587_Y - attribute \src "libresoc.v:160334.18-160334.114" - wire width 64 $extend$libresoc.v:160334$8589_Y - attribute \src "libresoc.v:160335.18-160335.115" - wire width 64 $extend$libresoc.v:160335$8591_Y - attribute \src "libresoc.v:160328.18-160328.128" - wire $ne$libresoc.v:160328$8580_Y - attribute \src "libresoc.v:160319.18-160319.109" - wire width 65 $neg$libresoc.v:160319$8568_Y - attribute \src "libresoc.v:160322.18-160322.113" - wire width 65 $neg$libresoc.v:160322$8573_Y - attribute \src "libresoc.v:160325.18-160325.116" - wire $not$libresoc.v:160325$8577_Y - attribute \src "libresoc.v:160330.18-160330.99" - wire $not$libresoc.v:160330$8582_Y - attribute \src "libresoc.v:160320.18-160320.100" - wire width 65 $pos$libresoc.v:160320$8570_Y - attribute \src "libresoc.v:160323.18-160323.104" - wire width 65 $pos$libresoc.v:160323$8575_Y - attribute \src "libresoc.v:160329.18-160329.118" - wire width 64 $pos$libresoc.v:160329$8581_Y - attribute \src "libresoc.v:160331.18-160331.114" - wire width 64 $pos$libresoc.v:160331$8584_Y - attribute \src "libresoc.v:160332.18-160332.114" - wire width 64 $pos$libresoc.v:160332$8586_Y - attribute \src "libresoc.v:160333.18-160333.114" - wire width 64 $pos$libresoc.v:160333$8588_Y - attribute \src "libresoc.v:160334.18-160334.114" - wire width 64 $pos$libresoc.v:160334$8590_Y - attribute \src "libresoc.v:160335.18-160335.115" - wire width 64 $pos$libresoc.v:160335$8592_Y - attribute \src "libresoc.v:160321.18-160321.121" - wire width 65 $ternary$libresoc.v:160321$8571_Y - attribute \src "libresoc.v:160324.18-160324.122" - wire width 65 $ternary$libresoc.v:160324$8576_Y - attribute \src "libresoc.v:160318.18-160318.120" - wire $xor$libresoc.v:160318$8566_Y - attribute \src "libresoc.v:160326.18-160326.127" - wire $xor$libresoc.v:160326$8578_Y + attribute \src "libresoc.v:161635.18-161635.122" + wire $and$libresoc.v:161635$8563_Y + attribute \src "libresoc.v:161627.18-161627.109" + wire width 65 $extend$libresoc.v:161627$8551_Y + attribute \src "libresoc.v:161628.18-161628.100" + wire width 65 $extend$libresoc.v:161628$8553_Y + attribute \src "libresoc.v:161630.18-161630.113" + wire width 65 $extend$libresoc.v:161630$8556_Y + attribute \src "libresoc.v:161631.18-161631.104" + wire width 65 $extend$libresoc.v:161631$8558_Y + attribute \src "libresoc.v:161639.18-161639.114" + wire width 64 $extend$libresoc.v:161639$8567_Y + attribute \src "libresoc.v:161640.18-161640.114" + wire width 64 $extend$libresoc.v:161640$8569_Y + attribute \src "libresoc.v:161641.18-161641.114" + wire width 64 $extend$libresoc.v:161641$8571_Y + attribute \src "libresoc.v:161642.18-161642.114" + wire width 64 $extend$libresoc.v:161642$8573_Y + attribute \src "libresoc.v:161643.18-161643.115" + wire width 64 $extend$libresoc.v:161643$8575_Y + attribute \src "libresoc.v:161636.18-161636.128" + wire $ne$libresoc.v:161636$8564_Y + attribute \src "libresoc.v:161627.18-161627.109" + wire width 65 $neg$libresoc.v:161627$8552_Y + attribute \src "libresoc.v:161630.18-161630.113" + wire width 65 $neg$libresoc.v:161630$8557_Y + attribute \src "libresoc.v:161633.18-161633.116" + wire $not$libresoc.v:161633$8561_Y + attribute \src "libresoc.v:161638.18-161638.99" + wire $not$libresoc.v:161638$8566_Y + attribute \src "libresoc.v:161628.18-161628.100" + wire width 65 $pos$libresoc.v:161628$8554_Y + attribute \src "libresoc.v:161631.18-161631.104" + wire width 65 $pos$libresoc.v:161631$8559_Y + attribute \src "libresoc.v:161637.18-161637.118" + wire width 64 signed $pos$libresoc.v:161637$8565_Y + attribute \src "libresoc.v:161639.18-161639.114" + wire width 64 $pos$libresoc.v:161639$8568_Y + attribute \src "libresoc.v:161640.18-161640.114" + wire width 64 $pos$libresoc.v:161640$8570_Y + attribute \src "libresoc.v:161641.18-161641.114" + wire width 64 $pos$libresoc.v:161641$8572_Y + attribute \src "libresoc.v:161642.18-161642.114" + wire width 64 $pos$libresoc.v:161642$8574_Y + attribute \src "libresoc.v:161643.18-161643.115" + wire width 64 $pos$libresoc.v:161643$8576_Y + attribute \src "libresoc.v:161629.18-161629.121" + wire width 65 $ternary$libresoc.v:161629$8555_Y + attribute \src "libresoc.v:161632.18-161632.122" + wire width 65 $ternary$libresoc.v:161632$8560_Y + attribute \src "libresoc.v:161626.18-161626.120" + wire $xor$libresoc.v:161626$8550_Y + attribute \src "libresoc.v:161634.18-161634.127" + wire $xor$libresoc.v:161634$8562_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" wire \$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" @@ -329137,7 +300507,7 @@ module \output_stage wire input 21 \dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" wire input 20 \divisor_neg - attribute \src "libresoc.v:159974.7-159974.15" + attribute \src "libresoc.v:161282.7-161282.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len @@ -329434,7 +300804,7 @@ module \output_stage attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 50 \xer_so$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - cell $and $and$libresoc.v:160327$8579 + cell $and $and$libresoc.v:161635$8563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329442,82 +300812,82 @@ module \output_stage parameter \Y_WIDTH 1 connect \A \logical_op__is_signed connect \B \$38 - connect \Y $and$libresoc.v:160327$8579_Y + connect \Y $and$libresoc.v:161635$8563_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - cell $pos $extend$libresoc.v:160319$8567 + cell $pos $extend$libresoc.v:161627$8551 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \quotient_root - connect \Y $extend$libresoc.v:160319$8567_Y + connect \Y $extend$libresoc.v:161627$8551_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - cell $pos $extend$libresoc.v:160320$8569 + cell $pos $extend$libresoc.v:161628$8553 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \quotient_root - connect \Y $extend$libresoc.v:160320$8569_Y + connect \Y $extend$libresoc.v:161628$8553_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - cell $pos $extend$libresoc.v:160322$8572 + cell $pos $extend$libresoc.v:161630$8556 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \remainder [127:64] - connect \Y $extend$libresoc.v:160322$8572_Y + connect \Y $extend$libresoc.v:161630$8556_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:160323$8574 + cell $pos $extend$libresoc.v:161631$8558 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \remainder [127:64] - connect \Y $extend$libresoc.v:160323$8574_Y + connect \Y $extend$libresoc.v:161631$8558_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" - cell $pos $extend$libresoc.v:160331$8583 + cell $pos $extend$libresoc.v:161639$8567 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \quotient_65 [31:0] - connect \Y $extend$libresoc.v:160331$8583_Y + connect \Y $extend$libresoc.v:161639$8567_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" - cell $pos $extend$libresoc.v:160332$8585 + cell $pos $extend$libresoc.v:161640$8569 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \quotient_65 [31:0] - connect \Y $extend$libresoc.v:160332$8585_Y + connect \Y $extend$libresoc.v:161640$8569_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" - cell $pos $extend$libresoc.v:160333$8587 + cell $pos $extend$libresoc.v:161641$8571 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \quotient_65 [31:0] - connect \Y $extend$libresoc.v:160333$8587_Y + connect \Y $extend$libresoc.v:161641$8571_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" - cell $pos $extend$libresoc.v:160334$8589 + cell $pos $extend$libresoc.v:161642$8573 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \quotient_65 [31:0] - connect \Y $extend$libresoc.v:160334$8589_Y + connect \Y $extend$libresoc.v:161642$8573_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" - cell $pos $extend$libresoc.v:160335$8591 + cell $pos $extend$libresoc.v:161643$8575 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \remainder_64 [31:0] - connect \Y $extend$libresoc.v:160335$8591_Y + connect \Y $extend$libresoc.v:161643$8575_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" - cell $ne $ne$libresoc.v:160328$8580 + cell $ne $ne$libresoc.v:161636$8564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329525,122 +300895,122 @@ module \output_stage parameter \Y_WIDTH 1 connect \A \quotient_65 [32] connect \B \quotient_65 [31] - connect \Y $ne$libresoc.v:160328$8580_Y + connect \Y $ne$libresoc.v:161636$8564_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - cell $neg $neg$libresoc.v:160319$8568 + cell $neg $neg$libresoc.v:161627$8552 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:160319$8567_Y - connect \Y $neg$libresoc.v:160319$8568_Y + connect \A $extend$libresoc.v:161627$8551_Y + connect \Y $neg$libresoc.v:161627$8552_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - cell $neg $neg$libresoc.v:160322$8573 + cell $neg $neg$libresoc.v:161630$8557 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:160322$8572_Y - connect \Y $neg$libresoc.v:160322$8573_Y + connect \A $extend$libresoc.v:161630$8556_Y + connect \Y $neg$libresoc.v:161630$8557_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" - cell $not $not$libresoc.v:160325$8577 + cell $not $not$libresoc.v:161633$8561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \logical_op__is_32bit - connect \Y $not$libresoc.v:160325$8577_Y + connect \Y $not$libresoc.v:161633$8561_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" - cell $not $not$libresoc.v:160330$8582 + cell $not $not$libresoc.v:161638$8566 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ov - connect \Y $not$libresoc.v:160330$8582_Y + connect \Y $not$libresoc.v:161638$8566_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - cell $pos $pos$libresoc.v:160320$8570 + cell $pos $pos$libresoc.v:161628$8554 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:160320$8569_Y - connect \Y $pos$libresoc.v:160320$8570_Y + connect \A $extend$libresoc.v:161628$8553_Y + connect \Y $pos$libresoc.v:161628$8554_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:160323$8575 + cell $pos $pos$libresoc.v:161631$8559 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:160323$8574_Y - connect \Y $pos$libresoc.v:160323$8575_Y + connect \A $extend$libresoc.v:161631$8558_Y + connect \Y $pos$libresoc.v:161631$8559_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" - cell $pos $pos$libresoc.v:160329$8581 + cell $pos $pos$libresoc.v:161637$8565 parameter \A_SIGNED 1 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 [31] \remainder_s32 } - connect \Y $pos$libresoc.v:160329$8581_Y + connect \Y $pos$libresoc.v:161637$8565_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" - cell $pos $pos$libresoc.v:160331$8584 + cell $pos $pos$libresoc.v:161639$8568 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:160331$8583_Y - connect \Y $pos$libresoc.v:160331$8584_Y + connect \A $extend$libresoc.v:161639$8567_Y + connect \Y $pos$libresoc.v:161639$8568_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:110" - cell $pos $pos$libresoc.v:160332$8586 + cell $pos $pos$libresoc.v:161640$8570 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:160332$8585_Y - connect \Y $pos$libresoc.v:160332$8586_Y + connect \A $extend$libresoc.v:161640$8569_Y + connect \Y $pos$libresoc.v:161640$8570_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" - cell $pos $pos$libresoc.v:160333$8588 + cell $pos $pos$libresoc.v:161641$8572 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:160333$8587_Y - connect \Y $pos$libresoc.v:160333$8588_Y + connect \A $extend$libresoc.v:161641$8571_Y + connect \Y $pos$libresoc.v:161641$8572_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:119" - cell $pos $pos$libresoc.v:160334$8590 + cell $pos $pos$libresoc.v:161642$8574 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:160334$8589_Y - connect \Y $pos$libresoc.v:160334$8590_Y + connect \A $extend$libresoc.v:161642$8573_Y + connect \Y $pos$libresoc.v:161642$8574_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:128" - cell $pos $pos$libresoc.v:160335$8592 + cell $pos $pos$libresoc.v:161643$8576 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:160335$8591_Y - connect \Y $pos$libresoc.v:160335$8592_Y + connect \A $extend$libresoc.v:161643$8575_Y + connect \Y $pos$libresoc.v:161643$8576_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - cell $mux $ternary$libresoc.v:160321$8571 + cell $mux $ternary$libresoc.v:161629$8555 parameter \WIDTH 65 connect \A \$25 connect \B \$23 connect \S \quotient_neg - connect \Y $ternary$libresoc.v:160321$8571_Y + connect \Y $ternary$libresoc.v:161629$8555_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - cell $mux $ternary$libresoc.v:160324$8576 + cell $mux $ternary$libresoc.v:161632$8560 parameter \WIDTH 65 connect \A \$32 connect \B \$30 connect \S \remainder_neg - connect \Y $ternary$libresoc.v:160324$8576_Y + connect \Y $ternary$libresoc.v:161632$8560_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" - cell $xor $xor$libresoc.v:160318$8566 + cell $xor $xor$libresoc.v:161626$8550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329648,10 +301018,10 @@ module \output_stage parameter \Y_WIDTH 1 connect \A \dividend_neg connect \B \divisor_neg - connect \Y $xor$libresoc.v:160318$8566_Y + connect \Y $xor$libresoc.v:161626$8550_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - cell $xor $xor$libresoc.v:160326$8578 + cell $xor $xor$libresoc.v:161634$8562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329659,24 +301029,24 @@ module \output_stage parameter \Y_WIDTH 1 connect \A \quotient_65 [64] connect \B \quotient_65 [63] - connect \Y $xor$libresoc.v:160326$8578_Y + connect \Y $xor$libresoc.v:161634$8562_Y end - attribute \src "libresoc.v:159974.7-159974.20" - process $proc$libresoc.v:159974$8595 + attribute \src "libresoc.v:161282.7-161282.20" + process $proc$libresoc.v:161282$8579 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:160336.3-160407.6" - process $proc$libresoc.v:160336$8593 + attribute \src "libresoc.v:161644.3-161715.6" + process $proc$libresoc.v:161644$8577 assign { } { } assign { } { } assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:160337.5-160337.29" + attribute \src "libresoc.v:161645.5-161645.29" switch \initial - attribute \src "libresoc.v:160337.9-160337.17" + attribute \src "libresoc.v:161645.9-161645.17" case 1'1 case end @@ -329775,13 +301145,13 @@ module \output_stage sync always update \o $0\o[63:0] end - attribute \src "libresoc.v:160408.3-160441.6" - process $proc$libresoc.v:160408$8594 + attribute \src "libresoc.v:161716.3-161749.6" + process $proc$libresoc.v:161716$8578 assign { } { } assign $0\ov[0:0] $1\ov[0:0] - attribute \src "libresoc.v:160409.5-160409.29" + attribute \src "libresoc.v:161717.5-161717.29" switch \initial - attribute \src "libresoc.v:160409.9-160409.17" + attribute \src "libresoc.v:161717.9-161717.17" case 1'1 case end @@ -329827,24 +301197,24 @@ module \output_stage sync always update \ov $0\ov[0:0] end - connect \$21 $xor$libresoc.v:160318$8566_Y - connect \$23 $neg$libresoc.v:160319$8568_Y - connect \$25 $pos$libresoc.v:160320$8570_Y - connect \$27 $ternary$libresoc.v:160321$8571_Y - connect \$30 $neg$libresoc.v:160322$8573_Y - connect \$32 $pos$libresoc.v:160323$8575_Y - connect \$34 $ternary$libresoc.v:160324$8576_Y - connect \$36 $not$libresoc.v:160325$8577_Y - connect \$38 $xor$libresoc.v:160326$8578_Y - connect \$40 $and$libresoc.v:160327$8579_Y - connect \$42 $ne$libresoc.v:160328$8580_Y - connect \$44 $pos$libresoc.v:160329$8581_Y - connect \$46 $not$libresoc.v:160330$8582_Y - connect \$48 $pos$libresoc.v:160331$8584_Y - connect \$50 $pos$libresoc.v:160332$8586_Y - connect \$52 $pos$libresoc.v:160333$8588_Y - connect \$54 $pos$libresoc.v:160334$8590_Y - connect \$56 $pos$libresoc.v:160335$8592_Y + connect \$21 $xor$libresoc.v:161626$8550_Y + connect \$23 $neg$libresoc.v:161627$8552_Y + connect \$25 $pos$libresoc.v:161628$8554_Y + connect \$27 $ternary$libresoc.v:161629$8555_Y + connect \$30 $neg$libresoc.v:161630$8557_Y + connect \$32 $pos$libresoc.v:161631$8559_Y + connect \$34 $ternary$libresoc.v:161632$8560_Y + connect \$36 $not$libresoc.v:161633$8561_Y + connect \$38 $xor$libresoc.v:161634$8562_Y + connect \$40 $and$libresoc.v:161635$8563_Y + connect \$42 $ne$libresoc.v:161636$8564_Y + connect \$44 $pos$libresoc.v:161637$8565_Y + connect \$46 $not$libresoc.v:161638$8566_Y + connect \$48 $pos$libresoc.v:161639$8568_Y + connect \$50 $pos$libresoc.v:161640$8570_Y + connect \$52 $pos$libresoc.v:161641$8572_Y + connect \$54 $pos$libresoc.v:161642$8574_Y + connect \$56 $pos$libresoc.v:161643$8576_Y connect \$29 \$34 connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \muxid$1 \muxid @@ -329859,13 +301229,13 @@ module \output_stage connect \remainder_neg \dividend_neg connect \quotient_neg \$21 end -attribute \src "libresoc.v:160459.1-160470.10" +attribute \src "libresoc.v:161767.1-161778.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.p" attribute \generator "nMigen" module \p - attribute \src "libresoc.v:160468.17-160468.111" - wire $and$libresoc.v:160468$8596_Y + attribute \src "libresoc.v:161776.17-161776.111" + wire $and$libresoc.v:161776$8580_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -329875,7 +301245,7 @@ module \p attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160468$8596 + cell $and $and$libresoc.v:161776$8580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329883,18 +301253,18 @@ module \p parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160468$8596_Y + connect \Y $and$libresoc.v:161776$8580_Y end - connect \$1 $and$libresoc.v:160468$8596_Y + connect \$1 $and$libresoc.v:161776$8580_Y connect \trigger \$1 end -attribute \src "libresoc.v:160474.1-160485.10" +attribute \src "libresoc.v:161782.1-161793.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1.p" attribute \generator "nMigen" module \p$1 - attribute \src "libresoc.v:160483.17-160483.111" - wire $and$libresoc.v:160483$8597_Y + attribute \src "libresoc.v:161791.17-161791.111" + wire $and$libresoc.v:161791$8581_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -329904,7 +301274,7 @@ module \p$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160483$8597 + cell $and $and$libresoc.v:161791$8581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329912,18 +301282,18 @@ module \p$1 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160483$8597_Y + connect \Y $and$libresoc.v:161791$8581_Y end - connect \$1 $and$libresoc.v:160483$8597_Y + connect \$1 $and$libresoc.v:161791$8581_Y connect \trigger \$1 end -attribute \src "libresoc.v:160489.1-160500.10" +attribute \src "libresoc.v:161797.1-161808.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.p" attribute \generator "nMigen" module \p$108 - attribute \src "libresoc.v:160498.17-160498.111" - wire $and$libresoc.v:160498$8598_Y + attribute \src "libresoc.v:161806.17-161806.111" + wire $and$libresoc.v:161806$8582_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -329933,7 +301303,7 @@ module \p$108 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160498$8598 + cell $and $and$libresoc.v:161806$8582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329941,18 +301311,18 @@ module \p$108 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160498$8598_Y + connect \Y $and$libresoc.v:161806$8582_Y end - connect \$1 $and$libresoc.v:160498$8598_Y + connect \$1 $and$libresoc.v:161806$8582_Y connect \trigger \$1 end -attribute \src "libresoc.v:160504.1-160515.10" +attribute \src "libresoc.v:161812.1-161823.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.p" attribute \generator "nMigen" module \p$111 - attribute \src "libresoc.v:160513.17-160513.111" - wire $and$libresoc.v:160513$8599_Y + attribute \src "libresoc.v:161821.17-161821.111" + wire $and$libresoc.v:161821$8583_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -329962,7 +301332,7 @@ module \p$111 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160513$8599 + cell $and $and$libresoc.v:161821$8583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329970,18 +301340,18 @@ module \p$111 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160513$8599_Y + connect \Y $and$libresoc.v:161821$8583_Y end - connect \$1 $and$libresoc.v:160513$8599_Y + connect \$1 $and$libresoc.v:161821$8583_Y connect \trigger \$1 end -attribute \src "libresoc.v:160519.1-160530.10" +attribute \src "libresoc.v:161827.1-161838.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2.p" attribute \generator "nMigen" module \p$116 - attribute \src "libresoc.v:160528.17-160528.111" - wire $and$libresoc.v:160528$8600_Y + attribute \src "libresoc.v:161836.17-161836.111" + wire $and$libresoc.v:161836$8584_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -329991,7 +301361,7 @@ module \p$116 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160528$8600 + cell $and $and$libresoc.v:161836$8584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -329999,18 +301369,18 @@ module \p$116 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160528$8600_Y + connect \Y $and$libresoc.v:161836$8584_Y end - connect \$1 $and$libresoc.v:160528$8600_Y + connect \$1 $and$libresoc.v:161836$8584_Y connect \trigger \$1 end -attribute \src "libresoc.v:160534.1-160545.10" +attribute \src "libresoc.v:161842.1-161853.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.p" attribute \generator "nMigen" module \p$17 - attribute \src "libresoc.v:160543.17-160543.111" - wire $and$libresoc.v:160543$8601_Y + attribute \src "libresoc.v:161851.17-161851.111" + wire $and$libresoc.v:161851$8585_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330020,7 +301390,7 @@ module \p$17 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160543$8601 + cell $and $and$libresoc.v:161851$8585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330028,18 +301398,18 @@ module \p$17 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160543$8601_Y + connect \Y $and$libresoc.v:161851$8585_Y end - connect \$1 $and$libresoc.v:160543$8601_Y + connect \$1 $and$libresoc.v:161851$8585_Y connect \trigger \$1 end -attribute \src "libresoc.v:160549.1-160560.10" +attribute \src "libresoc.v:161857.1-161868.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe.p" attribute \generator "nMigen" module \p$20 - attribute \src "libresoc.v:160558.17-160558.111" - wire $and$libresoc.v:160558$8602_Y + attribute \src "libresoc.v:161866.17-161866.111" + wire $and$libresoc.v:161866$8586_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330049,7 +301419,7 @@ module \p$20 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160558$8602 + cell $and $and$libresoc.v:161866$8586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330057,18 +301427,18 @@ module \p$20 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160558$8602_Y + connect \Y $and$libresoc.v:161866$8586_Y end - connect \$1 $and$libresoc.v:160558$8602_Y + connect \$1 $and$libresoc.v:161866$8586_Y connect \trigger \$1 end -attribute \src "libresoc.v:160564.1-160575.10" +attribute \src "libresoc.v:161872.1-161883.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2.p" attribute \generator "nMigen" module \p$3 - attribute \src "libresoc.v:160573.17-160573.111" - wire $and$libresoc.v:160573$8603_Y + attribute \src "libresoc.v:161881.17-161881.111" + wire $and$libresoc.v:161881$8587_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330078,7 +301448,7 @@ module \p$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160573$8603 + cell $and $and$libresoc.v:161881$8587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330086,18 +301456,18 @@ module \p$3 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160573$8603_Y + connect \Y $and$libresoc.v:161881$8587_Y end - connect \$1 $and$libresoc.v:160573$8603_Y + connect \$1 $and$libresoc.v:161881$8587_Y connect \trigger \$1 end -attribute \src "libresoc.v:160579.1-160590.10" +attribute \src "libresoc.v:161887.1-161898.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.p" attribute \generator "nMigen" module \p$30 - attribute \src "libresoc.v:160588.17-160588.111" - wire $and$libresoc.v:160588$8604_Y + attribute \src "libresoc.v:161896.17-161896.111" + wire $and$libresoc.v:161896$8588_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330107,7 +301477,7 @@ module \p$30 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160588$8604 + cell $and $and$libresoc.v:161896$8588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330115,18 +301485,18 @@ module \p$30 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160588$8604_Y + connect \Y $and$libresoc.v:161896$8588_Y end - connect \$1 $and$libresoc.v:160588$8604_Y + connect \$1 $and$libresoc.v:161896$8588_Y connect \trigger \$1 end -attribute \src "libresoc.v:160594.1-160605.10" +attribute \src "libresoc.v:161902.1-161913.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1.p" attribute \generator "nMigen" module \p$33 - attribute \src "libresoc.v:160603.17-160603.111" - wire $and$libresoc.v:160603$8605_Y + attribute \src "libresoc.v:161911.17-161911.111" + wire $and$libresoc.v:161911$8589_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330136,7 +301506,7 @@ module \p$33 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160603$8605 + cell $and $and$libresoc.v:161911$8589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330144,18 +301514,18 @@ module \p$33 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160603$8605_Y + connect \Y $and$libresoc.v:161911$8589_Y end - connect \$1 $and$libresoc.v:160603$8605_Y + connect \$1 $and$libresoc.v:161911$8589_Y connect \trigger \$1 end -attribute \src "libresoc.v:160609.1-160620.10" +attribute \src "libresoc.v:161917.1-161928.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2.p" attribute \generator "nMigen" module \p$36 - attribute \src "libresoc.v:160618.17-160618.111" - wire $and$libresoc.v:160618$8606_Y + attribute \src "libresoc.v:161926.17-161926.111" + wire $and$libresoc.v:161926$8590_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330165,7 +301535,7 @@ module \p$36 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160618$8606 + cell $and $and$libresoc.v:161926$8590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330173,18 +301543,18 @@ module \p$36 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160618$8606_Y + connect \Y $and$libresoc.v:161926$8590_Y end - connect \$1 $and$libresoc.v:160618$8606_Y + connect \$1 $and$libresoc.v:161926$8590_Y connect \trigger \$1 end -attribute \src "libresoc.v:160624.1-160635.10" +attribute \src "libresoc.v:161932.1-161943.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.p" attribute \generator "nMigen" module \p$46 - attribute \src "libresoc.v:160633.17-160633.111" - wire $and$libresoc.v:160633$8607_Y + attribute \src "libresoc.v:161941.17-161941.111" + wire $and$libresoc.v:161941$8591_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330194,7 +301564,7 @@ module \p$46 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160633$8607 + cell $and $and$libresoc.v:161941$8591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330202,18 +301572,18 @@ module \p$46 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160633$8607_Y + connect \Y $and$libresoc.v:161941$8591_Y end - connect \$1 $and$libresoc.v:160633$8607_Y + connect \$1 $and$libresoc.v:161941$8591_Y connect \trigger \$1 end -attribute \src "libresoc.v:160639.1-160650.10" +attribute \src "libresoc.v:161947.1-161958.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.p" attribute \generator "nMigen" module \p$48 - attribute \src "libresoc.v:160648.17-160648.111" - wire $and$libresoc.v:160648$8608_Y + attribute \src "libresoc.v:161956.17-161956.111" + wire $and$libresoc.v:161956$8592_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330223,7 +301593,7 @@ module \p$48 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160648$8608 + cell $and $and$libresoc.v:161956$8592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330231,18 +301601,18 @@ module \p$48 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160648$8608_Y + connect \Y $and$libresoc.v:161956$8592_Y end - connect \$1 $and$libresoc.v:160648$8608_Y + connect \$1 $and$libresoc.v:161956$8592_Y connect \trigger \$1 end -attribute \src "libresoc.v:160654.1-160665.10" +attribute \src "libresoc.v:161962.1-161973.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.p" attribute \generator "nMigen" module \p$5 - attribute \src "libresoc.v:160663.17-160663.111" - wire $and$libresoc.v:160663$8609_Y + attribute \src "libresoc.v:161971.17-161971.111" + wire $and$libresoc.v:161971$8593_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330252,7 +301622,7 @@ module \p$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160663$8609 + cell $and $and$libresoc.v:161971$8593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330260,18 +301630,18 @@ module \p$5 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160663$8609_Y + connect \Y $and$libresoc.v:161971$8593_Y end - connect \$1 $and$libresoc.v:160663$8609_Y + connect \$1 $and$libresoc.v:161971$8593_Y connect \trigger \$1 end -attribute \src "libresoc.v:160669.1-160680.10" +attribute \src "libresoc.v:161977.1-161988.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe2.p" attribute \generator "nMigen" module \p$52 - attribute \src "libresoc.v:160678.17-160678.111" - wire $and$libresoc.v:160678$8610_Y + attribute \src "libresoc.v:161986.17-161986.111" + wire $and$libresoc.v:161986$8594_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330281,7 +301651,7 @@ module \p$52 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160678$8610 + cell $and $and$libresoc.v:161986$8594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330289,18 +301659,18 @@ module \p$52 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160678$8610_Y + connect \Y $and$libresoc.v:161986$8594_Y end - connect \$1 $and$libresoc.v:160678$8610_Y + connect \$1 $and$libresoc.v:161986$8594_Y connect \trigger \$1 end -attribute \src "libresoc.v:160684.1-160695.10" +attribute \src "libresoc.v:161992.1-162003.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.p" attribute \generator "nMigen" module \p$62 - attribute \src "libresoc.v:160693.17-160693.111" - wire $and$libresoc.v:160693$8611_Y + attribute \src "libresoc.v:162001.17-162001.111" + wire $and$libresoc.v:162001$8595_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330310,7 +301680,7 @@ module \p$62 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160693$8611 + cell $and $and$libresoc.v:162001$8595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330318,18 +301688,18 @@ module \p$62 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160693$8611_Y + connect \Y $and$libresoc.v:162001$8595_Y end - connect \$1 $and$libresoc.v:160693$8611_Y + connect \$1 $and$libresoc.v:162001$8595_Y connect \trigger \$1 end -attribute \src "libresoc.v:160699.1-160710.10" +attribute \src "libresoc.v:162007.1-162018.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.p" attribute \generator "nMigen" module \p$65 - attribute \src "libresoc.v:160708.17-160708.111" - wire $and$libresoc.v:160708$8612_Y + attribute \src "libresoc.v:162016.17-162016.111" + wire $and$libresoc.v:162016$8596_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330339,7 +301709,7 @@ module \p$65 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160708$8612 + cell $and $and$libresoc.v:162016$8596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330347,18 +301717,18 @@ module \p$65 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160708$8612_Y + connect \Y $and$libresoc.v:162016$8596_Y end - connect \$1 $and$libresoc.v:160708$8612_Y + connect \$1 $and$libresoc.v:162016$8596_Y connect \trigger \$1 end -attribute \src "libresoc.v:160714.1-160725.10" +attribute \src "libresoc.v:162022.1-162033.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe.p" attribute \generator "nMigen" module \p$7 - attribute \src "libresoc.v:160723.17-160723.111" - wire $and$libresoc.v:160723$8613_Y + attribute \src "libresoc.v:162031.17-162031.111" + wire $and$libresoc.v:162031$8597_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330368,7 +301738,7 @@ module \p$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160723$8613 + cell $and $and$libresoc.v:162031$8597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330376,18 +301746,18 @@ module \p$7 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160723$8613_Y + connect \Y $and$libresoc.v:162031$8597_Y end - connect \$1 $and$libresoc.v:160723$8613_Y + connect \$1 $and$libresoc.v:162031$8597_Y connect \trigger \$1 end -attribute \src "libresoc.v:160729.1-160740.10" +attribute \src "libresoc.v:162037.1-162048.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.p" attribute \generator "nMigen" module \p$74 - attribute \src "libresoc.v:160738.17-160738.111" - wire $and$libresoc.v:160738$8614_Y + attribute \src "libresoc.v:162046.17-162046.111" + wire $and$libresoc.v:162046$8598_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330397,7 +301767,7 @@ module \p$74 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160738$8614 + cell $and $and$libresoc.v:162046$8598 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330405,18 +301775,18 @@ module \p$74 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160738$8614_Y + connect \Y $and$libresoc.v:162046$8598_Y end - connect \$1 $and$libresoc.v:160738$8614_Y + connect \$1 $and$libresoc.v:162046$8598_Y connect \trigger \$1 end -attribute \src "libresoc.v:160744.1-160755.10" +attribute \src "libresoc.v:162052.1-162063.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.p" attribute \generator "nMigen" module \p$76 - attribute \src "libresoc.v:160753.17-160753.111" - wire $and$libresoc.v:160753$8615_Y + attribute \src "libresoc.v:162061.17-162061.111" + wire $and$libresoc.v:162061$8599_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330426,7 +301796,7 @@ module \p$76 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160753$8615 + cell $and $and$libresoc.v:162061$8599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330434,18 +301804,18 @@ module \p$76 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160753$8615_Y + connect \Y $and$libresoc.v:162061$8599_Y end - connect \$1 $and$libresoc.v:160753$8615_Y + connect \$1 $and$libresoc.v:162061$8599_Y connect \trigger \$1 end -attribute \src "libresoc.v:160759.1-160770.10" +attribute \src "libresoc.v:162067.1-162078.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0.p" attribute \generator "nMigen" module \p$79 - attribute \src "libresoc.v:160768.17-160768.111" - wire $and$libresoc.v:160768$8616_Y + attribute \src "libresoc.v:162076.17-162076.111" + wire $and$libresoc.v:162076$8600_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330455,7 +301825,7 @@ module \p$79 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160768$8616 + cell $and $and$libresoc.v:162076$8600 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330463,18 +301833,18 @@ module \p$79 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160768$8616_Y + connect \Y $and$libresoc.v:162076$8600_Y end - connect \$1 $and$libresoc.v:160768$8616_Y + connect \$1 $and$libresoc.v:162076$8600_Y connect \trigger \$1 end -attribute \src "libresoc.v:160774.1-160785.10" +attribute \src "libresoc.v:162082.1-162093.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end.p" attribute \generator "nMigen" module \p$81 - attribute \src "libresoc.v:160783.17-160783.111" - wire $and$libresoc.v:160783$8617_Y + attribute \src "libresoc.v:162091.17-162091.111" + wire $and$libresoc.v:162091$8601_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330484,7 +301854,7 @@ module \p$81 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160783$8617 + cell $and $and$libresoc.v:162091$8601 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330492,18 +301862,18 @@ module \p$81 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160783$8617_Y + connect \Y $and$libresoc.v:162091$8601_Y end - connect \$1 $and$libresoc.v:160783$8617_Y + connect \$1 $and$libresoc.v:162091$8601_Y connect \trigger \$1 end -attribute \src "libresoc.v:160789.1-160800.10" +attribute \src "libresoc.v:162097.1-162108.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.p" attribute \generator "nMigen" module \p$91 - attribute \src "libresoc.v:160798.17-160798.111" - wire $and$libresoc.v:160798$8618_Y + attribute \src "libresoc.v:162106.17-162106.111" + wire $and$libresoc.v:162106$8602_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330513,7 +301883,7 @@ module \p$91 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160798$8618 + cell $and $and$libresoc.v:162106$8602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330521,18 +301891,18 @@ module \p$91 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160798$8618_Y + connect \Y $and$libresoc.v:162106$8602_Y end - connect \$1 $and$libresoc.v:160798$8618_Y + connect \$1 $and$libresoc.v:162106$8602_Y connect \trigger \$1 end -attribute \src "libresoc.v:160804.1-160815.10" +attribute \src "libresoc.v:162112.1-162123.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe1.p" attribute \generator "nMigen" module \p$93 - attribute \src "libresoc.v:160813.17-160813.111" - wire $and$libresoc.v:160813$8619_Y + attribute \src "libresoc.v:162121.17-162121.111" + wire $and$libresoc.v:162121$8603_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330542,7 +301912,7 @@ module \p$93 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160813$8619 + cell $and $and$libresoc.v:162121$8603 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330550,18 +301920,18 @@ module \p$93 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160813$8619_Y + connect \Y $and$libresoc.v:162121$8603_Y end - connect \$1 $and$libresoc.v:160813$8619_Y + connect \$1 $and$libresoc.v:162121$8603_Y connect \trigger \$1 end -attribute \src "libresoc.v:160819.1-160830.10" +attribute \src "libresoc.v:162127.1-162138.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe2.p" attribute \generator "nMigen" module \p$96 - attribute \src "libresoc.v:160828.17-160828.111" - wire $and$libresoc.v:160828$8620_Y + attribute \src "libresoc.v:162136.17-162136.111" + wire $and$libresoc.v:162136$8604_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330571,7 +301941,7 @@ module \p$96 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160828$8620 + cell $and $and$libresoc.v:162136$8604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330579,18 +301949,18 @@ module \p$96 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160828$8620_Y + connect \Y $and$libresoc.v:162136$8604_Y end - connect \$1 $and$libresoc.v:160828$8620_Y + connect \$1 $and$libresoc.v:162136$8604_Y connect \trigger \$1 end -attribute \src "libresoc.v:160834.1-160845.10" +attribute \src "libresoc.v:162142.1-162153.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.alu_mul0.mul_pipe3.p" attribute \generator "nMigen" module \p$98 - attribute \src "libresoc.v:160843.17-160843.111" - wire $and$libresoc.v:160843$8621_Y + attribute \src "libresoc.v:162151.17-162151.111" + wire $and$libresoc.v:162151$8605_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:160" @@ -330600,7 +301970,7 @@ module \p$98 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:164" wire \trigger attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:211" - cell $and $and$libresoc.v:160843$8621 + cell $and $and$libresoc.v:162151$8605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330608,36 +301978,36 @@ module \p$98 parameter \Y_WIDTH 1 connect \A \p_valid_i connect \B \p_ready_o - connect \Y $and$libresoc.v:160843$8621_Y + connect \Y $and$libresoc.v:162151$8605_Y end - connect \$1 $and$libresoc.v:160843$8621_Y + connect \$1 $and$libresoc.v:162151$8605_Y connect \trigger \$1 end -attribute \src "libresoc.v:160849.1-160872.10" +attribute \src "libresoc.v:162157.1-162180.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.pick" attribute \generator "nMigen" module \pick - attribute \src "libresoc.v:160850.7-160850.20" + attribute \src "libresoc.v:162158.7-162158.20" wire $0\initial[0:0] - attribute \src "libresoc.v:160861.3-160870.6" + attribute \src "libresoc.v:162169.3-162178.6" wire $0\o[0:0] - attribute \src "libresoc.v:160861.3-160870.6" + attribute \src "libresoc.v:162169.3-162178.6" wire $1\o[0:0] - attribute \src "libresoc.v:160860.17-160860.95" - wire $eq$libresoc.v:160860$8622_Y + attribute \src "libresoc.v:162168.17-162168.95" + wire $eq$libresoc.v:162168$8606_Y attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" wire input 3 \i - attribute \src "libresoc.v:160850.7-160850.15" + attribute \src "libresoc.v:162158.7-162158.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" wire output 2 \n attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" wire output 1 \o attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $eq$libresoc.v:160860$8622 + cell $eq $eq$libresoc.v:162168$8606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -330645,24 +302015,24 @@ module \pick parameter \Y_WIDTH 1 connect \A \i connect \B 1'0 - connect \Y $eq$libresoc.v:160860$8622_Y + connect \Y $eq$libresoc.v:162168$8606_Y end - attribute \src "libresoc.v:160850.7-160850.20" - process $proc$libresoc.v:160850$8624 + attribute \src "libresoc.v:162158.7-162158.20" + process $proc$libresoc.v:162158$8608 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:160861.3-160870.6" - process $proc$libresoc.v:160861$8623 + attribute \src "libresoc.v:162169.3-162178.6" + process $proc$libresoc.v:162169$8607 assign { } { } assign { } { } assign $0\o[0:0] $1\o[0:0] - attribute \src "libresoc.v:160862.5-160862.29" + attribute \src "libresoc.v:162170.5-162170.29" switch \initial - attribute \src "libresoc.v:160862.9-160862.17" + attribute \src "libresoc.v:162170.9-162170.17" case 1'1 case end @@ -330678,296 +302048,296 @@ module \pick sync always update \o $0\o[0:0] end - connect \$1 $eq$libresoc.v:160860$8622_Y + connect \$1 $eq$libresoc.v:162168$8606_Y connect \n \$1 end -attribute \src "libresoc.v:160876.1-161690.10" +attribute \src "libresoc.v:162184.1-162998.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem" attribute \generator "nMigen" module \pimem - attribute \src "libresoc.v:161653.3-161668.6" + attribute \src "libresoc.v:162961.3-162976.6" wire $0\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:161617.3-161652.6" - wire $0\adrok_l_s_addr_acked$next[0:0]$8714 - attribute \src "libresoc.v:161175.3-161176.57" + attribute \src "libresoc.v:162925.3-162960.6" + wire $0\adrok_l_s_addr_acked$next[0:0]$8698 + attribute \src "libresoc.v:162483.3-162484.57" wire $0\adrok_l_s_addr_acked[0:0] - attribute \src "libresoc.v:161267.3-161275.6" - wire $0\busy_delay$next[0:0]$8682 - attribute \src "libresoc.v:161173.3-161174.37" + attribute \src "libresoc.v:162575.3-162583.6" + wire $0\busy_delay$next[0:0]$8666 + attribute \src "libresoc.v:162481.3-162482.37" wire $0\busy_delay[0:0] - attribute \src "libresoc.v:161601.3-161616.6" + attribute \src "libresoc.v:162909.3-162924.6" wire $0\busy_l_r_busy[0:0] - attribute \src "libresoc.v:161591.3-161600.6" + attribute \src "libresoc.v:162899.3-162908.6" wire $0\busy_l_s_busy[0:0] - attribute \src "libresoc.v:161581.3-161590.6" + attribute \src "libresoc.v:162889.3-162898.6" wire $0\cyc_l_r_cyc[0:0] - attribute \src "libresoc.v:161562.3-161571.6" + attribute \src "libresoc.v:162870.3-162879.6" wire $0\cyc_l_s_cyc[0:0] - attribute \src "libresoc.v:161523.3-161561.6" - wire width 2 $0\fsm_state$next[1:0]$8700 - attribute \src "libresoc.v:161165.3-161166.35" + attribute \src "libresoc.v:162831.3-162869.6" + wire width 2 $0\fsm_state$next[1:0]$8684 + attribute \src "libresoc.v:162473.3-162474.35" wire width 2 $0\fsm_state[1:0] - attribute \src "libresoc.v:160877.7-160877.20" + attribute \src "libresoc.v:162185.7-162185.20" wire $0\initial[0:0] - attribute \src "libresoc.v:161463.3-161472.6" + attribute \src "libresoc.v:162771.3-162780.6" wire $0\ld_active_r_ld_active[0:0] - attribute \src "libresoc.v:161171.3-161172.35" + attribute \src "libresoc.v:162479.3-162480.35" wire $0\lds_dly[0:0] - attribute \src "libresoc.v:161396.3-161426.6" + attribute \src "libresoc.v:162704.3-162734.6" wire $0\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:161453.3-161462.6" + attribute \src "libresoc.v:162761.3-162770.6" wire width 64 $0\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:161473.3-161482.6" + attribute \src "libresoc.v:162781.3-162790.6" wire $0\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:161302.3-161317.6" + attribute \src "libresoc.v:162610.3-162625.6" wire width 4 $0\lenexp_addr_i[3:0] - attribute \src "libresoc.v:161286.3-161301.6" + attribute \src "libresoc.v:162594.3-162609.6" wire width 4 $0\lenexp_len_i[3:0] - attribute \src "libresoc.v:161572.3-161580.6" - wire $0\lsui_active_dly$next[0:0]$8708 - attribute \src "libresoc.v:161163.3-161164.47" + attribute \src "libresoc.v:162880.3-162888.6" + wire $0\lsui_active_dly$next[0:0]$8692 + attribute \src "libresoc.v:162471.3-162472.47" wire $0\lsui_active_dly[0:0] - attribute \src "libresoc.v:161503.3-161522.6" + attribute \src "libresoc.v:162811.3-162830.6" wire $0\lsui_busy[0:0] - attribute \src "libresoc.v:161167.3-161168.36" + attribute \src "libresoc.v:162475.3-162476.36" wire $0\reset_delay[0:0] - attribute \src "libresoc.v:161443.3-161452.6" + attribute \src "libresoc.v:162751.3-162760.6" wire $0\reset_l_r_reset[0:0] - attribute \src "libresoc.v:161427.3-161442.6" + attribute \src "libresoc.v:162735.3-162750.6" wire $0\reset_l_s_reset[0:0] - attribute \src "libresoc.v:161276.3-161285.6" + attribute \src "libresoc.v:162584.3-162593.6" wire $0\st_active_r_st_active[0:0] - attribute \src "libresoc.v:161257.3-161266.6" + attribute \src "libresoc.v:162565.3-162574.6" wire $0\st_done_r_st_done[0:0] - attribute \src "libresoc.v:161242.3-161256.6" - wire $0\st_done_s_st_done$next[0:0]$8677 - attribute \src "libresoc.v:161177.3-161178.51" + attribute \src "libresoc.v:162550.3-162564.6" + wire $0\st_done_s_st_done$next[0:0]$8661 + attribute \src "libresoc.v:162485.3-162486.51" wire $0\st_done_s_st_done[0:0] - attribute \src "libresoc.v:161483.3-161492.6" + attribute \src "libresoc.v:162791.3-162800.6" wire width 64 $0\stdata[63:0] - attribute \src "libresoc.v:161169.3-161170.35" + attribute \src "libresoc.v:162477.3-162478.35" wire $0\sts_dly[0:0] - attribute \src "libresoc.v:161318.3-161343.6" + attribute \src "libresoc.v:162626.3-162651.6" wire $0\valid_l_s_valid[0:0] - attribute \src "libresoc.v:161370.3-161395.6" + attribute \src "libresoc.v:162678.3-162703.6" wire width 48 $0\x_addr_i[47:0] - attribute \src "libresoc.v:161344.3-161369.6" + attribute \src "libresoc.v:162652.3-162677.6" wire width 8 $0\x_mask_i[7:0] - attribute \src "libresoc.v:161493.3-161502.6" + attribute \src "libresoc.v:162801.3-162810.6" wire width 64 $0\x_st_data_i[63:0] - attribute \src "libresoc.v:161653.3-161668.6" + attribute \src "libresoc.v:162961.3-162976.6" wire $1\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:161617.3-161652.6" - wire $1\adrok_l_s_addr_acked$next[0:0]$8715 - attribute \src "libresoc.v:160971.7-160971.34" + attribute \src "libresoc.v:162925.3-162960.6" + wire $1\adrok_l_s_addr_acked$next[0:0]$8699 + attribute \src "libresoc.v:162279.7-162279.34" wire $1\adrok_l_s_addr_acked[0:0] - attribute \src "libresoc.v:161267.3-161275.6" - wire $1\busy_delay$next[0:0]$8683 - attribute \src "libresoc.v:160975.7-160975.24" + attribute \src "libresoc.v:162575.3-162583.6" + wire $1\busy_delay$next[0:0]$8667 + attribute \src "libresoc.v:162283.7-162283.24" wire $1\busy_delay[0:0] - attribute \src "libresoc.v:161601.3-161616.6" + attribute \src "libresoc.v:162909.3-162924.6" wire $1\busy_l_r_busy[0:0] - attribute \src "libresoc.v:161591.3-161600.6" + attribute \src "libresoc.v:162899.3-162908.6" wire $1\busy_l_s_busy[0:0] - attribute \src "libresoc.v:161581.3-161590.6" + attribute \src "libresoc.v:162889.3-162898.6" wire $1\cyc_l_r_cyc[0:0] - attribute \src "libresoc.v:161562.3-161571.6" + attribute \src "libresoc.v:162870.3-162879.6" wire $1\cyc_l_s_cyc[0:0] - attribute \src "libresoc.v:161523.3-161561.6" - wire width 2 $1\fsm_state$next[1:0]$8701 - attribute \src "libresoc.v:160997.13-160997.29" + attribute \src "libresoc.v:162831.3-162869.6" + wire width 2 $1\fsm_state$next[1:0]$8685 + attribute \src "libresoc.v:162305.13-162305.29" wire width 2 $1\fsm_state[1:0] - attribute \src "libresoc.v:161463.3-161472.6" + attribute \src "libresoc.v:162771.3-162780.6" wire $1\ld_active_r_ld_active[0:0] - attribute \src "libresoc.v:161011.7-161011.21" + attribute \src "libresoc.v:162319.7-162319.21" wire $1\lds_dly[0:0] - attribute \src "libresoc.v:161396.3-161426.6" + attribute \src "libresoc.v:162704.3-162734.6" wire $1\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:161453.3-161462.6" + attribute \src "libresoc.v:162761.3-162770.6" wire width 64 $1\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:161473.3-161482.6" + attribute \src "libresoc.v:162781.3-162790.6" wire $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:161302.3-161317.6" + attribute \src "libresoc.v:162610.3-162625.6" wire width 4 $1\lenexp_addr_i[3:0] - attribute \src "libresoc.v:161286.3-161301.6" + attribute \src "libresoc.v:162594.3-162609.6" wire width 4 $1\lenexp_len_i[3:0] - attribute \src "libresoc.v:161572.3-161580.6" - wire $1\lsui_active_dly$next[0:0]$8709 - attribute \src "libresoc.v:161054.7-161054.29" + attribute \src "libresoc.v:162880.3-162888.6" + wire $1\lsui_active_dly$next[0:0]$8693 + attribute \src "libresoc.v:162362.7-162362.29" wire $1\lsui_active_dly[0:0] - attribute \src "libresoc.v:161503.3-161522.6" + attribute \src "libresoc.v:162811.3-162830.6" wire $1\lsui_busy[0:0] - attribute \src "libresoc.v:161066.7-161066.25" + attribute \src "libresoc.v:162374.7-162374.25" wire $1\reset_delay[0:0] - attribute \src "libresoc.v:161443.3-161452.6" + attribute \src "libresoc.v:162751.3-162760.6" wire $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:161427.3-161442.6" + attribute \src "libresoc.v:162735.3-162750.6" wire $1\reset_l_s_reset[0:0] - attribute \src "libresoc.v:161276.3-161285.6" + attribute \src "libresoc.v:162584.3-162593.6" wire $1\st_active_r_st_active[0:0] - attribute \src "libresoc.v:161257.3-161266.6" + attribute \src "libresoc.v:162565.3-162574.6" wire $1\st_done_r_st_done[0:0] - attribute \src "libresoc.v:161242.3-161256.6" - wire $1\st_done_s_st_done$next[0:0]$8678 - attribute \src "libresoc.v:161086.7-161086.31" + attribute \src "libresoc.v:162550.3-162564.6" + wire $1\st_done_s_st_done$next[0:0]$8662 + attribute \src "libresoc.v:162394.7-162394.31" wire $1\st_done_s_st_done[0:0] - attribute \src "libresoc.v:161483.3-161492.6" + attribute \src "libresoc.v:162791.3-162800.6" wire width 64 $1\stdata[63:0] - attribute \src "libresoc.v:161094.7-161094.21" + attribute \src "libresoc.v:162402.7-162402.21" wire $1\sts_dly[0:0] - attribute \src "libresoc.v:161318.3-161343.6" + attribute \src "libresoc.v:162626.3-162651.6" wire $1\valid_l_s_valid[0:0] - attribute \src "libresoc.v:161370.3-161395.6" + attribute \src "libresoc.v:162678.3-162703.6" wire width 48 $1\x_addr_i[47:0] - attribute \src "libresoc.v:161344.3-161369.6" + attribute \src "libresoc.v:162652.3-162677.6" wire width 8 $1\x_mask_i[7:0] - attribute \src "libresoc.v:161493.3-161502.6" + attribute \src "libresoc.v:162801.3-162810.6" wire width 64 $1\x_st_data_i[63:0] - attribute \src "libresoc.v:161653.3-161668.6" + attribute \src "libresoc.v:162961.3-162976.6" wire $2\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:161617.3-161652.6" - wire $2\adrok_l_s_addr_acked$next[0:0]$8716 - attribute \src "libresoc.v:161601.3-161616.6" + attribute \src "libresoc.v:162925.3-162960.6" + wire $2\adrok_l_s_addr_acked$next[0:0]$8700 + attribute \src "libresoc.v:162909.3-162924.6" wire $2\busy_l_r_busy[0:0] - attribute \src "libresoc.v:161523.3-161561.6" - wire width 2 $2\fsm_state$next[1:0]$8702 - attribute \src "libresoc.v:161396.3-161426.6" + attribute \src "libresoc.v:162831.3-162869.6" + wire width 2 $2\fsm_state$next[1:0]$8686 + attribute \src "libresoc.v:162704.3-162734.6" wire $2\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:161302.3-161317.6" + attribute \src "libresoc.v:162610.3-162625.6" wire width 4 $2\lenexp_addr_i[3:0] - attribute \src "libresoc.v:161286.3-161301.6" + attribute \src "libresoc.v:162594.3-162609.6" wire width 4 $2\lenexp_len_i[3:0] - attribute \src "libresoc.v:161503.3-161522.6" + attribute \src "libresoc.v:162811.3-162830.6" wire $2\lsui_busy[0:0] - attribute \src "libresoc.v:161427.3-161442.6" + attribute \src "libresoc.v:162735.3-162750.6" wire $2\reset_l_s_reset[0:0] - attribute \src "libresoc.v:161242.3-161256.6" - wire $2\st_done_s_st_done$next[0:0]$8679 - attribute \src "libresoc.v:161318.3-161343.6" + attribute \src "libresoc.v:162550.3-162564.6" + wire $2\st_done_s_st_done$next[0:0]$8663 + attribute \src "libresoc.v:162626.3-162651.6" wire $2\valid_l_s_valid[0:0] - attribute \src "libresoc.v:161370.3-161395.6" + attribute \src "libresoc.v:162678.3-162703.6" wire width 48 $2\x_addr_i[47:0] - attribute \src "libresoc.v:161344.3-161369.6" + attribute \src "libresoc.v:162652.3-162677.6" wire width 8 $2\x_mask_i[7:0] - attribute \src "libresoc.v:161617.3-161652.6" - wire $3\adrok_l_s_addr_acked$next[0:0]$8717 - attribute \src "libresoc.v:161523.3-161561.6" - wire width 2 $3\fsm_state$next[1:0]$8703 - attribute \src "libresoc.v:161396.3-161426.6" + attribute \src "libresoc.v:162925.3-162960.6" + wire $3\adrok_l_s_addr_acked$next[0:0]$8701 + attribute \src "libresoc.v:162831.3-162869.6" + wire width 2 $3\fsm_state$next[1:0]$8687 + attribute \src "libresoc.v:162704.3-162734.6" wire $3\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:161318.3-161343.6" + attribute \src "libresoc.v:162626.3-162651.6" wire $3\valid_l_s_valid[0:0] - attribute \src "libresoc.v:161370.3-161395.6" + attribute \src "libresoc.v:162678.3-162703.6" wire width 48 $3\x_addr_i[47:0] - attribute \src "libresoc.v:161344.3-161369.6" + attribute \src "libresoc.v:162652.3-162677.6" wire width 8 $3\x_mask_i[7:0] - attribute \src "libresoc.v:161617.3-161652.6" - wire $4\adrok_l_s_addr_acked$next[0:0]$8718 - attribute \src "libresoc.v:161523.3-161561.6" - wire width 2 $4\fsm_state$next[1:0]$8704 - attribute \src "libresoc.v:161396.3-161426.6" + attribute \src "libresoc.v:162925.3-162960.6" + wire $4\adrok_l_s_addr_acked$next[0:0]$8702 + attribute \src "libresoc.v:162831.3-162869.6" + wire width 2 $4\fsm_state$next[1:0]$8688 + attribute \src "libresoc.v:162704.3-162734.6" wire $4\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:161318.3-161343.6" + attribute \src "libresoc.v:162626.3-162651.6" wire $4\valid_l_s_valid[0:0] - attribute \src "libresoc.v:161370.3-161395.6" + attribute \src "libresoc.v:162678.3-162703.6" wire width 48 $4\x_addr_i[47:0] - attribute \src "libresoc.v:161344.3-161369.6" + attribute \src "libresoc.v:162652.3-162677.6" wire width 8 $4\x_mask_i[7:0] - attribute \src "libresoc.v:161617.3-161652.6" - wire $5\adrok_l_s_addr_acked$next[0:0]$8719 - attribute \src "libresoc.v:161523.3-161561.6" - wire width 2 $5\fsm_state$next[1:0]$8705 - attribute \src "libresoc.v:161396.3-161426.6" + attribute \src "libresoc.v:162925.3-162960.6" + wire $5\adrok_l_s_addr_acked$next[0:0]$8703 + attribute \src "libresoc.v:162831.3-162869.6" + wire width 2 $5\fsm_state$next[1:0]$8689 + attribute \src "libresoc.v:162704.3-162734.6" wire $5\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:161617.3-161652.6" - wire $6\adrok_l_s_addr_acked$next[0:0]$8720 - attribute \src "libresoc.v:161123.18-161123.115" - wire $and$libresoc.v:161123$8626_Y - attribute \src "libresoc.v:161125.18-161125.95" - wire $and$libresoc.v:161125$8628_Y - attribute \src "libresoc.v:161127.17-161127.138" - wire $and$libresoc.v:161127$8630_Y - attribute \src "libresoc.v:161128.18-161128.95" - wire $and$libresoc.v:161128$8631_Y - attribute \src "libresoc.v:161131.18-161131.136" - wire $and$libresoc.v:161131$8636_Y - attribute \src "libresoc.v:161132.18-161132.136" - wire $and$libresoc.v:161132$8637_Y - attribute \src "libresoc.v:161133.18-161133.136" - wire $and$libresoc.v:161133$8638_Y - attribute \src "libresoc.v:161134.18-161134.136" - wire $and$libresoc.v:161134$8639_Y - attribute \src "libresoc.v:161135.18-161135.136" - wire $and$libresoc.v:161135$8640_Y - attribute \src "libresoc.v:161140.18-161140.119" - wire width 176 $and$libresoc.v:161140$8645_Y - attribute \src "libresoc.v:161143.18-161143.136" - wire $and$libresoc.v:161143$8648_Y - attribute \src "libresoc.v:161144.18-161144.136" - wire $and$libresoc.v:161144$8649_Y - attribute \src "libresoc.v:161146.18-161146.139" - wire $and$libresoc.v:161146$8651_Y - attribute \src "libresoc.v:161150.18-161150.139" - wire $and$libresoc.v:161150$8655_Y - attribute \src "libresoc.v:161152.18-161152.114" - wire $and$libresoc.v:161152$8657_Y - attribute \src "libresoc.v:161154.18-161154.114" - wire $and$libresoc.v:161154$8659_Y - attribute \src "libresoc.v:161158.18-161158.103" - wire $and$libresoc.v:161158$8663_Y - attribute \src "libresoc.v:161159.17-161159.135" - wire $and$libresoc.v:161159$8664_Y - attribute \src "libresoc.v:161162.18-161162.103" - wire $and$libresoc.v:161162$8667_Y - attribute \src "libresoc.v:161129.18-161129.109" - wire width 4 $extend$libresoc.v:161129$8632_Y - attribute \src "libresoc.v:161130.18-161130.109" - wire width 4 $extend$libresoc.v:161130$8634_Y - attribute \src "libresoc.v:161141.18-161141.112" - wire width 8 $mul$libresoc.v:161141$8646_Y - attribute \src "libresoc.v:161147.18-161147.112" - wire width 8 $mul$libresoc.v:161147$8652_Y - attribute \src "libresoc.v:161122.17-161122.103" - wire $not$libresoc.v:161122$8625_Y - attribute \src "libresoc.v:161124.18-161124.94" - wire $not$libresoc.v:161124$8627_Y - attribute \src "libresoc.v:161126.18-161126.94" - wire $not$libresoc.v:161126$8629_Y - attribute \src "libresoc.v:161136.18-161136.102" - wire $not$libresoc.v:161136$8641_Y - attribute \src "libresoc.v:161139.18-161139.97" - wire $not$libresoc.v:161139$8644_Y - attribute \src "libresoc.v:161145.18-161145.102" - wire $not$libresoc.v:161145$8650_Y - attribute \src "libresoc.v:161148.17-161148.103" - wire $not$libresoc.v:161148$8653_Y - attribute \src "libresoc.v:161155.18-161155.101" - wire $not$libresoc.v:161155$8660_Y - attribute \src "libresoc.v:161156.18-161156.111" - wire $not$libresoc.v:161156$8661_Y - attribute \src "libresoc.v:161157.18-161157.110" - wire $not$libresoc.v:161157$8662_Y - attribute \src "libresoc.v:161160.18-161160.102" - wire $not$libresoc.v:161160$8665_Y - attribute \src "libresoc.v:161161.18-161161.102" - wire $not$libresoc.v:161161$8666_Y - attribute \src "libresoc.v:161137.18-161137.111" - wire $or$libresoc.v:161137$8642_Y - attribute \src "libresoc.v:161138.17-161138.130" - wire $or$libresoc.v:161138$8643_Y - attribute \src "libresoc.v:161151.18-161151.130" - wire $or$libresoc.v:161151$8656_Y - attribute \src "libresoc.v:161153.18-161153.130" - wire $or$libresoc.v:161153$8658_Y - attribute \src "libresoc.v:161129.18-161129.109" - wire width 4 $pos$libresoc.v:161129$8633_Y - attribute \src "libresoc.v:161130.18-161130.109" - wire width 4 $pos$libresoc.v:161130$8635_Y - attribute \src "libresoc.v:161149.18-161149.121" - wire width 319 $sshl$libresoc.v:161149$8654_Y - attribute \src "libresoc.v:161142.18-161142.106" - wire width 176 $sshr$libresoc.v:161142$8647_Y + attribute \src "libresoc.v:162925.3-162960.6" + wire $6\adrok_l_s_addr_acked$next[0:0]$8704 + attribute \src "libresoc.v:162431.18-162431.115" + wire $and$libresoc.v:162431$8610_Y + attribute \src "libresoc.v:162433.18-162433.95" + wire $and$libresoc.v:162433$8612_Y + attribute \src "libresoc.v:162435.17-162435.138" + wire $and$libresoc.v:162435$8614_Y + attribute \src "libresoc.v:162436.18-162436.95" + wire $and$libresoc.v:162436$8615_Y + attribute \src "libresoc.v:162439.18-162439.136" + wire $and$libresoc.v:162439$8620_Y + attribute \src "libresoc.v:162440.18-162440.136" + wire $and$libresoc.v:162440$8621_Y + attribute \src "libresoc.v:162441.18-162441.136" + wire $and$libresoc.v:162441$8622_Y + attribute \src "libresoc.v:162442.18-162442.136" + wire $and$libresoc.v:162442$8623_Y + attribute \src "libresoc.v:162443.18-162443.136" + wire $and$libresoc.v:162443$8624_Y + attribute \src "libresoc.v:162448.18-162448.119" + wire width 176 $and$libresoc.v:162448$8629_Y + attribute \src "libresoc.v:162451.18-162451.136" + wire $and$libresoc.v:162451$8632_Y + attribute \src "libresoc.v:162452.18-162452.136" + wire $and$libresoc.v:162452$8633_Y + attribute \src "libresoc.v:162454.18-162454.139" + wire $and$libresoc.v:162454$8635_Y + attribute \src "libresoc.v:162458.18-162458.139" + wire $and$libresoc.v:162458$8639_Y + attribute \src "libresoc.v:162460.18-162460.114" + wire $and$libresoc.v:162460$8641_Y + attribute \src "libresoc.v:162462.18-162462.114" + wire $and$libresoc.v:162462$8643_Y + attribute \src "libresoc.v:162466.18-162466.103" + wire $and$libresoc.v:162466$8647_Y + attribute \src "libresoc.v:162467.17-162467.135" + wire $and$libresoc.v:162467$8648_Y + attribute \src "libresoc.v:162470.18-162470.103" + wire $and$libresoc.v:162470$8651_Y + attribute \src "libresoc.v:162437.18-162437.109" + wire width 4 $extend$libresoc.v:162437$8616_Y + attribute \src "libresoc.v:162438.18-162438.109" + wire width 4 $extend$libresoc.v:162438$8618_Y + attribute \src "libresoc.v:162449.18-162449.112" + wire width 8 $mul$libresoc.v:162449$8630_Y + attribute \src "libresoc.v:162455.18-162455.112" + wire width 8 $mul$libresoc.v:162455$8636_Y + attribute \src "libresoc.v:162430.17-162430.103" + wire $not$libresoc.v:162430$8609_Y + attribute \src "libresoc.v:162432.18-162432.94" + wire $not$libresoc.v:162432$8611_Y + attribute \src "libresoc.v:162434.18-162434.94" + wire $not$libresoc.v:162434$8613_Y + attribute \src "libresoc.v:162444.18-162444.102" + wire $not$libresoc.v:162444$8625_Y + attribute \src "libresoc.v:162447.18-162447.97" + wire $not$libresoc.v:162447$8628_Y + attribute \src "libresoc.v:162453.18-162453.102" + wire $not$libresoc.v:162453$8634_Y + attribute \src "libresoc.v:162456.17-162456.103" + wire $not$libresoc.v:162456$8637_Y + attribute \src "libresoc.v:162463.18-162463.101" + wire $not$libresoc.v:162463$8644_Y + attribute \src "libresoc.v:162464.18-162464.111" + wire $not$libresoc.v:162464$8645_Y + attribute \src "libresoc.v:162465.18-162465.110" + wire $not$libresoc.v:162465$8646_Y + attribute \src "libresoc.v:162468.18-162468.102" + wire $not$libresoc.v:162468$8649_Y + attribute \src "libresoc.v:162469.18-162469.102" + wire $not$libresoc.v:162469$8650_Y + attribute \src "libresoc.v:162445.18-162445.111" + wire $or$libresoc.v:162445$8626_Y + attribute \src "libresoc.v:162446.17-162446.130" + wire $or$libresoc.v:162446$8627_Y + attribute \src "libresoc.v:162459.18-162459.130" + wire $or$libresoc.v:162459$8640_Y + attribute \src "libresoc.v:162461.18-162461.130" + wire $or$libresoc.v:162461$8642_Y + attribute \src "libresoc.v:162437.18-162437.109" + wire width 4 $pos$libresoc.v:162437$8617_Y + attribute \src "libresoc.v:162438.18-162438.109" + wire width 4 $pos$libresoc.v:162438$8619_Y + attribute \src "libresoc.v:162457.18-162457.121" + wire width 319 $sshl$libresoc.v:162457$8638_Y + attribute \src "libresoc.v:162450.18-162450.106" + wire width 176 $sshr$libresoc.v:162450$8631_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" @@ -331076,9 +302446,9 @@ module \pimem wire \busy_l_r_busy attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \busy_l_s_busy - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 23 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \cyc_l_q_cyc @@ -331090,7 +302460,7 @@ module \pimem wire width 2 \fsm_state attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" wire width 2 \fsm_state$next - attribute \src "libresoc.v:160877.7-160877.15" + attribute \src "libresoc.v:162185.7-162185.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:67" wire \ld_active_q_ld_active @@ -331209,7 +302579,7 @@ module \pimem attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:57" wire output 22 \x_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" - cell $and $and$libresoc.v:161123$8626 + cell $and $and$libresoc.v:162431$8610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331217,10 +302587,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o connect \B \$9 - connect \Y $and$libresoc.v:161123$8626_Y + connect \Y $and$libresoc.v:162431$8610_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:161125$8628 + cell $and $and$libresoc.v:162433$8612 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331228,10 +302598,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \lds connect \B \$13 - connect \Y $and$libresoc.v:161125$8628_Y + connect \Y $and$libresoc.v:162433$8612_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" - cell $and $and$libresoc.v:161127$8630 + cell $and $and$libresoc.v:162435$8614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331239,10 +302609,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \st_active_q_st_active connect \B \ldst_port0_st_data_i_ok - connect \Y $and$libresoc.v:161127$8630_Y + connect \Y $and$libresoc.v:162435$8614_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:161128$8631 + cell $and $and$libresoc.v:162436$8615 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331250,10 +302620,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \sts connect \B \$17 - connect \Y $and$libresoc.v:161128$8631_Y + connect \Y $and$libresoc.v:162436$8615_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:161131$8636 + cell $and $and$libresoc.v:162439$8620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331261,10 +302631,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:161131$8636_Y + connect \Y $and$libresoc.v:162439$8620_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:161132$8637 + cell $and $and$libresoc.v:162440$8621 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331272,10 +302642,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:161132$8637_Y + connect \Y $and$libresoc.v:162440$8621_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:161133$8638 + cell $and $and$libresoc.v:162441$8622 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331283,10 +302653,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:161133$8638_Y + connect \Y $and$libresoc.v:162441$8622_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:161134$8639 + cell $and $and$libresoc.v:162442$8623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331294,10 +302664,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:161134$8639_Y + connect \Y $and$libresoc.v:162442$8623_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - cell $and $and$libresoc.v:161135$8640 + cell $and $and$libresoc.v:162443$8624 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331305,10 +302675,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ld_active_q_ld_active connect \B \adrok_l_q_addr_acked - connect \Y $and$libresoc.v:161135$8640_Y + connect \Y $and$libresoc.v:162443$8624_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:257" - cell $and $and$libresoc.v:161140$8645 + cell $and $and$libresoc.v:162448$8629 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -331316,10 +302686,10 @@ module \pimem parameter \Y_WIDTH 176 connect \A \m_ld_data_o connect \B \lenexp_rexp_o - connect \Y $and$libresoc.v:161140$8645_Y + connect \Y $and$libresoc.v:162448$8629_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - cell $and $and$libresoc.v:161143$8648 + cell $and $and$libresoc.v:162451$8632 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331327,10 +302697,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ld_active_q_ld_active connect \B \adrok_l_q_addr_acked - connect \Y $and$libresoc.v:161143$8648_Y + connect \Y $and$libresoc.v:162451$8632_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - cell $and $and$libresoc.v:161144$8649 + cell $and $and$libresoc.v:162452$8633 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331338,10 +302708,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ld_active_q_ld_active connect \B \adrok_l_q_addr_acked - connect \Y $and$libresoc.v:161144$8649_Y + connect \Y $and$libresoc.v:162452$8633_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" - cell $and $and$libresoc.v:161146$8651 + cell $and $and$libresoc.v:162454$8635 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331349,10 +302719,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \st_active_q_st_active connect \B \ldst_port0_st_data_i_ok - connect \Y $and$libresoc.v:161146$8651_Y + connect \Y $and$libresoc.v:162454$8635_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:267" - cell $and $and$libresoc.v:161150$8655 + cell $and $and$libresoc.v:162458$8639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331360,10 +302730,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \st_active_q_st_active connect \B \ldst_port0_st_data_i_ok - connect \Y $and$libresoc.v:161150$8655_Y + connect \Y $and$libresoc.v:162458$8639_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $and $and$libresoc.v:161152$8657 + cell $and $and$libresoc.v:162460$8641 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331371,10 +302741,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \$63 connect \B \valid_l_q_valid - connect \Y $and$libresoc.v:161152$8657_Y + connect \Y $and$libresoc.v:162460$8641_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $and $and$libresoc.v:161154$8659 + cell $and $and$libresoc.v:162462$8643 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331382,10 +302752,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \$67 connect \B \valid_l_q_valid - connect \Y $and$libresoc.v:161154$8659_Y + connect \Y $and$libresoc.v:162462$8643_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - cell $and $and$libresoc.v:161158$8663 + cell $and $and$libresoc.v:162466$8647 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331393,10 +302763,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \$73 connect \B \$75 - connect \Y $and$libresoc.v:161158$8663_Y + connect \Y $and$libresoc.v:162466$8647_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" - cell $and $and$libresoc.v:161159$8664 + cell $and $and$libresoc.v:162467$8648 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331404,10 +302774,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_addr_i_ok connect \B \adrok_l_qn_addr_acked - connect \Y $and$libresoc.v:161159$8664_Y + connect \Y $and$libresoc.v:162467$8648_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:161162$8667 + cell $and $and$libresoc.v:162470$8651 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331415,26 +302785,26 @@ module \pimem parameter \Y_WIDTH 1 connect \A \lsui_active connect \B \$81 - connect \Y $and$libresoc.v:161162$8667_Y + connect \Y $and$libresoc.v:162470$8651_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:161129$8632 + cell $pos $extend$libresoc.v:162437$8616 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 4 connect \A \ldst_port0_addr_i [2:0] - connect \Y $extend$libresoc.v:161129$8632_Y + connect \Y $extend$libresoc.v:162437$8616_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $extend$libresoc.v:161130$8634 + cell $pos $extend$libresoc.v:162438$8618 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 4 connect \A \ldst_port0_addr_i [2:0] - connect \Y $extend$libresoc.v:161130$8634_Y + connect \Y $extend$libresoc.v:162438$8618_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" - cell $mul $mul$libresoc.v:161141$8646 + cell $mul $mul$libresoc.v:162449$8630 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -331442,10 +302812,10 @@ module \pimem parameter \Y_WIDTH 8 connect \A \lenexp_addr_i connect \B 4'1000 - connect \Y $mul$libresoc.v:161141$8646_Y + connect \Y $mul$libresoc.v:162449$8630_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" - cell $mul $mul$libresoc.v:161147$8652 + cell $mul $mul$libresoc.v:162455$8636 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -331453,106 +302823,106 @@ module \pimem parameter \Y_WIDTH 8 connect \A \lenexp_addr_i connect \B 4'1000 - connect \Y $mul$libresoc.v:161147$8652_Y + connect \Y $mul$libresoc.v:162455$8636_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" - cell $not $not$libresoc.v:161122$8625 + cell $not $not$libresoc.v:162430$8609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \busy_delay - connect \Y $not$libresoc.v:161122$8625_Y + connect \Y $not$libresoc.v:162430$8609_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:161124$8627 + cell $not $not$libresoc.v:162432$8611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lds_dly - connect \Y $not$libresoc.v:161124$8627_Y + connect \Y $not$libresoc.v:162432$8611_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:161126$8629 + cell $not $not$libresoc.v:162434$8613 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sts_dly - connect \Y $not$libresoc.v:161126$8629_Y + connect \Y $not$libresoc.v:162434$8613_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" - cell $not $not$libresoc.v:161136$8641 + cell $not $not$libresoc.v:162444$8625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lsui_busy - connect \Y $not$libresoc.v:161136$8641_Y + connect \Y $not$libresoc.v:162444$8625_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" - cell $not $not$libresoc.v:161139$8644 + cell $not $not$libresoc.v:162447$8628 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$38 - connect \Y $not$libresoc.v:161139$8644_Y + connect \Y $not$libresoc.v:162447$8628_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" - cell $not $not$libresoc.v:161145$8650 + cell $not $not$libresoc.v:162453$8634 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lsui_busy - connect \Y $not$libresoc.v:161145$8650_Y + connect \Y $not$libresoc.v:162453$8634_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:224" - cell $not $not$libresoc.v:161148$8653 + cell $not $not$libresoc.v:162456$8637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \busy_delay - connect \Y $not$libresoc.v:161148$8653_Y + connect \Y $not$libresoc.v:162456$8637_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" - cell $not $not$libresoc.v:161155$8660 + cell $not $not$libresoc.v:162463$8644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_busy_o - connect \Y $not$libresoc.v:161155$8660_Y + connect \Y $not$libresoc.v:162463$8644_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - cell $not $not$libresoc.v:161156$8661 + cell $not $not$libresoc.v:162464$8645 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_is_st_i - connect \Y $not$libresoc.v:161156$8661_Y + connect \Y $not$libresoc.v:162464$8645_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - cell $not $not$libresoc.v:161157$8662 + cell $not $not$libresoc.v:162465$8646 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \ldst_port0_busy_o - connect \Y $not$libresoc.v:161157$8662_Y + connect \Y $not$libresoc.v:162465$8646_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:108" - cell $not $not$libresoc.v:161160$8665 + cell $not $not$libresoc.v:162468$8649 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \x_busy_o - connect \Y $not$libresoc.v:161160$8665_Y + connect \Y $not$libresoc.v:162468$8649_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:161161$8666 + cell $not $not$libresoc.v:162469$8650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \lsui_active_dly - connect \Y $not$libresoc.v:161161$8666_Y + connect \Y $not$libresoc.v:162469$8650_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" - cell $or $or$libresoc.v:161137$8642 + cell $or $or$libresoc.v:162445$8626 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331560,10 +302930,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \x_busy_o connect \B \lsui_busy - connect \Y $or$libresoc.v:161137$8642_Y + connect \Y $or$libresoc.v:162445$8626_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" - cell $or $or$libresoc.v:161138$8643 + cell $or $or$libresoc.v:162446$8627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331571,10 +302941,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_is_ld_i connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:161138$8643_Y + connect \Y $or$libresoc.v:162446$8627_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $or $or$libresoc.v:161151$8656 + cell $or $or$libresoc.v:162459$8640 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331582,10 +302952,10 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_is_ld_i connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:161151$8656_Y + connect \Y $or$libresoc.v:162459$8640_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $or $or$libresoc.v:161153$8658 + cell $or $or$libresoc.v:162461$8642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -331593,26 +302963,26 @@ module \pimem parameter \Y_WIDTH 1 connect \A \ldst_port0_is_ld_i connect \B \ldst_port0_is_st_i - connect \Y $or$libresoc.v:161153$8658_Y + connect \Y $or$libresoc.v:162461$8642_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:161129$8633 + cell $pos $pos$libresoc.v:162437$8617 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $extend$libresoc.v:161129$8632_Y - connect \Y $pos$libresoc.v:161129$8633_Y + connect \A $extend$libresoc.v:162437$8616_Y + connect \Y $pos$libresoc.v:162437$8617_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $pos$libresoc.v:161130$8635 + cell $pos $pos$libresoc.v:162438$8619 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 - connect \A $extend$libresoc.v:161130$8634_Y - connect \Y $pos$libresoc.v:161130$8635_Y + connect \A $extend$libresoc.v:162438$8618_Y + connect \Y $pos$libresoc.v:162438$8619_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" - cell $sshl $sshl$libresoc.v:161149$8654 + cell $sshl $sshl$libresoc.v:162457$8638 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -331620,10 +302990,10 @@ module \pimem parameter \Y_WIDTH 319 connect \A \ldst_port0_st_data_i connect \B \$57 - connect \Y $sshl$libresoc.v:161149$8654_Y + connect \Y $sshl$libresoc.v:162457$8638_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:258" - cell $sshr $sshr$libresoc.v:161142$8647 + cell $sshr $sshr$libresoc.v:162450$8631 parameter \A_SIGNED 0 parameter \A_WIDTH 176 parameter \B_SIGNED 0 @@ -331631,10 +303001,10 @@ module \pimem parameter \Y_WIDTH 176 connect \A \$42 connect \B \$44 - connect \Y $sshr$libresoc.v:161142$8647_Y + connect \Y $sshr$libresoc.v:162450$8631_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:161179.11-161186.4" + attribute \src "libresoc.v:162487.11-162494.4" cell \adrok_l \adrok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -331644,7 +303014,7 @@ module \pimem connect \s_addr_acked \adrok_l_s_addr_acked end attribute \module_not_derived 1 - attribute \src "libresoc.v:161187.10-161193.4" + attribute \src "libresoc.v:162495.10-162501.4" cell \busy_l \busy_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -331653,7 +303023,7 @@ module \pimem connect \s_busy \busy_l_s_busy end attribute \module_not_derived 1 - attribute \src "libresoc.v:161194.9-161200.4" + attribute \src "libresoc.v:162502.9-162508.4" cell \cyc_l \cyc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -331662,7 +303032,7 @@ module \pimem connect \s_cyc \cyc_l_s_cyc end attribute \module_not_derived 1 - attribute \src "libresoc.v:161201.13-161207.4" + attribute \src "libresoc.v:162509.13-162515.4" cell \ld_active \ld_active connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -331671,7 +303041,7 @@ module \pimem connect \s_ld_active \ld_active_s_ld_active end attribute \module_not_derived 1 - attribute \src "libresoc.v:161208.10-161213.4" + attribute \src "libresoc.v:162516.10-162521.4" cell \lenexp \lenexp connect \addr_i \lenexp_addr_i connect \len_i \lenexp_len_i @@ -331679,7 +303049,7 @@ module \pimem connect \rexp_o \lenexp_rexp_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:161214.11-161220.4" + attribute \src "libresoc.v:162522.11-162528.4" cell \reset_l \reset_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -331688,7 +303058,7 @@ module \pimem connect \s_reset \reset_l_s_reset end attribute \module_not_derived 1 - attribute \src "libresoc.v:161221.13-161227.4" + attribute \src "libresoc.v:162529.13-162535.4" cell \st_active \st_active connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -331697,7 +303067,7 @@ module \pimem connect \s_st_active \st_active_s_st_active end attribute \module_not_derived 1 - attribute \src "libresoc.v:161228.11-161234.4" + attribute \src "libresoc.v:162536.11-162542.4" cell \st_done \st_done connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -331706,7 +303076,7 @@ module \pimem connect \s_st_done \st_done_s_st_done end attribute \module_not_derived 1 - attribute \src "libresoc.v:161235.11-161241.4" + attribute \src "libresoc.v:162543.11-162549.4" cell \valid_l \valid_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -331714,143 +303084,143 @@ module \pimem connect \r_valid \valid_l_r_valid connect \s_valid \valid_l_s_valid end - attribute \src "libresoc.v:160877.7-160877.20" - process $proc$libresoc.v:160877$8722 + attribute \src "libresoc.v:162185.7-162185.20" + process $proc$libresoc.v:162185$8706 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:160971.7-160971.34" - process $proc$libresoc.v:160971$8723 + attribute \src "libresoc.v:162279.7-162279.34" + process $proc$libresoc.v:162279$8707 assign { } { } assign $1\adrok_l_s_addr_acked[0:0] 1'0 sync always sync init update \adrok_l_s_addr_acked $1\adrok_l_s_addr_acked[0:0] end - attribute \src "libresoc.v:160975.7-160975.24" - process $proc$libresoc.v:160975$8724 + attribute \src "libresoc.v:162283.7-162283.24" + process $proc$libresoc.v:162283$8708 assign { } { } assign $1\busy_delay[0:0] 1'0 sync always sync init update \busy_delay $1\busy_delay[0:0] end - attribute \src "libresoc.v:160997.13-160997.29" - process $proc$libresoc.v:160997$8725 + attribute \src "libresoc.v:162305.13-162305.29" + process $proc$libresoc.v:162305$8709 assign { } { } assign $1\fsm_state[1:0] 2'00 sync always sync init update \fsm_state $1\fsm_state[1:0] end - attribute \src "libresoc.v:161011.7-161011.21" - process $proc$libresoc.v:161011$8726 + attribute \src "libresoc.v:162319.7-162319.21" + process $proc$libresoc.v:162319$8710 assign { } { } assign $1\lds_dly[0:0] 1'0 sync always sync init update \lds_dly $1\lds_dly[0:0] end - attribute \src "libresoc.v:161054.7-161054.29" - process $proc$libresoc.v:161054$8727 + attribute \src "libresoc.v:162362.7-162362.29" + process $proc$libresoc.v:162362$8711 assign { } { } assign $1\lsui_active_dly[0:0] 1'0 sync always sync init update \lsui_active_dly $1\lsui_active_dly[0:0] end - attribute \src "libresoc.v:161066.7-161066.25" - process $proc$libresoc.v:161066$8728 + attribute \src "libresoc.v:162374.7-162374.25" + process $proc$libresoc.v:162374$8712 assign { } { } assign $1\reset_delay[0:0] 1'0 sync always sync init update \reset_delay $1\reset_delay[0:0] end - attribute \src "libresoc.v:161086.7-161086.31" - process $proc$libresoc.v:161086$8729 + attribute \src "libresoc.v:162394.7-162394.31" + process $proc$libresoc.v:162394$8713 assign { } { } assign $1\st_done_s_st_done[0:0] 1'0 sync always sync init update \st_done_s_st_done $1\st_done_s_st_done[0:0] end - attribute \src "libresoc.v:161094.7-161094.21" - process $proc$libresoc.v:161094$8730 + attribute \src "libresoc.v:162402.7-162402.21" + process $proc$libresoc.v:162402$8714 assign { } { } assign $1\sts_dly[0:0] 1'0 sync always sync init update \sts_dly $1\sts_dly[0:0] end - attribute \src "libresoc.v:161163.3-161164.47" - process $proc$libresoc.v:161163$8668 + attribute \src "libresoc.v:162471.3-162472.47" + process $proc$libresoc.v:162471$8652 assign { } { } assign $0\lsui_active_dly[0:0] \lsui_active_dly$next sync posedge \coresync_clk update \lsui_active_dly $0\lsui_active_dly[0:0] end - attribute \src "libresoc.v:161165.3-161166.35" - process $proc$libresoc.v:161165$8669 + attribute \src "libresoc.v:162473.3-162474.35" + process $proc$libresoc.v:162473$8653 assign { } { } assign $0\fsm_state[1:0] \fsm_state$next sync posedge \coresync_clk update \fsm_state $0\fsm_state[1:0] end - attribute \src "libresoc.v:161167.3-161168.36" - process $proc$libresoc.v:161167$8670 + attribute \src "libresoc.v:162475.3-162476.36" + process $proc$libresoc.v:162475$8654 assign { } { } assign $0\reset_delay[0:0] \reset_l_q_reset sync posedge \coresync_clk update \reset_delay $0\reset_delay[0:0] end - attribute \src "libresoc.v:161169.3-161170.35" - process $proc$libresoc.v:161169$8671 + attribute \src "libresoc.v:162477.3-162478.35" + process $proc$libresoc.v:162477$8655 assign { } { } assign $0\sts_dly[0:0] \ldst_port0_is_st_i sync posedge \coresync_clk update \sts_dly $0\sts_dly[0:0] end - attribute \src "libresoc.v:161171.3-161172.35" - process $proc$libresoc.v:161171$8672 + attribute \src "libresoc.v:162479.3-162480.35" + process $proc$libresoc.v:162479$8656 assign { } { } assign $0\lds_dly[0:0] \ldst_port0_is_ld_i sync posedge \coresync_clk update \lds_dly $0\lds_dly[0:0] end - attribute \src "libresoc.v:161173.3-161174.37" - process $proc$libresoc.v:161173$8673 + attribute \src "libresoc.v:162481.3-162482.37" + process $proc$libresoc.v:162481$8657 assign { } { } assign $0\busy_delay[0:0] \busy_delay$next sync posedge \coresync_clk update \busy_delay $0\busy_delay[0:0] end - attribute \src "libresoc.v:161175.3-161176.57" - process $proc$libresoc.v:161175$8674 + attribute \src "libresoc.v:162483.3-162484.57" + process $proc$libresoc.v:162483$8658 assign { } { } assign $0\adrok_l_s_addr_acked[0:0] \adrok_l_s_addr_acked$next sync posedge \coresync_clk update \adrok_l_s_addr_acked $0\adrok_l_s_addr_acked[0:0] end - attribute \src "libresoc.v:161177.3-161178.51" - process $proc$libresoc.v:161177$8675 + attribute \src "libresoc.v:162485.3-162486.51" + process $proc$libresoc.v:162485$8659 assign { } { } assign $0\st_done_s_st_done[0:0] \st_done_s_st_done$next sync posedge \coresync_clk update \st_done_s_st_done $0\st_done_s_st_done[0:0] end - attribute \src "libresoc.v:161242.3-161256.6" - process $proc$libresoc.v:161242$8676 + attribute \src "libresoc.v:162550.3-162564.6" + process $proc$libresoc.v:162550$8660 assign { } { } assign { } { } assign { } { } - assign $0\st_done_s_st_done$next[0:0]$8677 $2\st_done_s_st_done$next[0:0]$8679 - attribute \src "libresoc.v:161243.5-161243.29" + assign $0\st_done_s_st_done$next[0:0]$8661 $2\st_done_s_st_done$next[0:0]$8663 + attribute \src "libresoc.v:162551.5-162551.29" switch \initial - attribute \src "libresoc.v:161243.9-161243.17" + attribute \src "libresoc.v:162551.9-162551.17" case 1'1 case end @@ -331859,30 +303229,30 @@ module \pimem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\st_done_s_st_done$next[0:0]$8678 1'1 + assign $1\st_done_s_st_done$next[0:0]$8662 1'1 case - assign $1\st_done_s_st_done$next[0:0]$8678 1'0 + assign $1\st_done_s_st_done$next[0:0]$8662 1'0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\st_done_s_st_done$next[0:0]$8679 1'0 + assign $2\st_done_s_st_done$next[0:0]$8663 1'0 case - assign $2\st_done_s_st_done$next[0:0]$8679 $1\st_done_s_st_done$next[0:0]$8678 + assign $2\st_done_s_st_done$next[0:0]$8663 $1\st_done_s_st_done$next[0:0]$8662 end sync always - update \st_done_s_st_done$next $0\st_done_s_st_done$next[0:0]$8677 + update \st_done_s_st_done$next $0\st_done_s_st_done$next[0:0]$8661 end - attribute \src "libresoc.v:161257.3-161266.6" - process $proc$libresoc.v:161257$8680 + attribute \src "libresoc.v:162565.3-162574.6" + process $proc$libresoc.v:162565$8664 assign { } { } assign { } { } assign $0\st_done_r_st_done[0:0] $1\st_done_r_st_done[0:0] - attribute \src "libresoc.v:161258.5-161258.29" + attribute \src "libresoc.v:162566.5-162566.29" switch \initial - attribute \src "libresoc.v:161258.9-161258.17" + attribute \src "libresoc.v:162566.9-162566.17" case 1'1 case end @@ -331898,14 +303268,14 @@ module \pimem sync always update \st_done_r_st_done $0\st_done_r_st_done[0:0] end - attribute \src "libresoc.v:161267.3-161275.6" - process $proc$libresoc.v:161267$8681 + attribute \src "libresoc.v:162575.3-162583.6" + process $proc$libresoc.v:162575$8665 assign { } { } assign { } { } - assign $0\busy_delay$next[0:0]$8682 $1\busy_delay$next[0:0]$8683 - attribute \src "libresoc.v:161268.5-161268.29" + assign $0\busy_delay$next[0:0]$8666 $1\busy_delay$next[0:0]$8667 + attribute \src "libresoc.v:162576.5-162576.29" switch \initial - attribute \src "libresoc.v:161268.9-161268.17" + attribute \src "libresoc.v:162576.9-162576.17" case 1'1 case end @@ -331914,21 +303284,21 @@ module \pimem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\busy_delay$next[0:0]$8683 1'0 + assign $1\busy_delay$next[0:0]$8667 1'0 case - assign $1\busy_delay$next[0:0]$8683 \ldst_port0_busy_o + assign $1\busy_delay$next[0:0]$8667 \ldst_port0_busy_o end sync always - update \busy_delay$next $0\busy_delay$next[0:0]$8682 + update \busy_delay$next $0\busy_delay$next[0:0]$8666 end - attribute \src "libresoc.v:161276.3-161285.6" - process $proc$libresoc.v:161276$8684 + attribute \src "libresoc.v:162584.3-162593.6" + process $proc$libresoc.v:162584$8668 assign { } { } assign { } { } assign $0\st_active_r_st_active[0:0] $1\st_active_r_st_active[0:0] - attribute \src "libresoc.v:161277.5-161277.29" + attribute \src "libresoc.v:162585.5-162585.29" switch \initial - attribute \src "libresoc.v:161277.9-161277.17" + attribute \src "libresoc.v:162585.9-162585.17" case 1'1 case end @@ -331944,15 +303314,15 @@ module \pimem sync always update \st_active_r_st_active $0\st_active_r_st_active[0:0] end - attribute \src "libresoc.v:161286.3-161301.6" - process $proc$libresoc.v:161286$8685 + attribute \src "libresoc.v:162594.3-162609.6" + process $proc$libresoc.v:162594$8669 assign { } { } assign { } { } assign { } { } assign $0\lenexp_len_i[3:0] $2\lenexp_len_i[3:0] - attribute \src "libresoc.v:161287.5-161287.29" + attribute \src "libresoc.v:162595.5-162595.29" switch \initial - attribute \src "libresoc.v:161287.9-161287.17" + attribute \src "libresoc.v:162595.9-162595.17" case 1'1 case end @@ -331977,15 +303347,15 @@ module \pimem sync always update \lenexp_len_i $0\lenexp_len_i[3:0] end - attribute \src "libresoc.v:161302.3-161317.6" - process $proc$libresoc.v:161302$8686 + attribute \src "libresoc.v:162610.3-162625.6" + process $proc$libresoc.v:162610$8670 assign { } { } assign { } { } assign { } { } assign $0\lenexp_addr_i[3:0] $2\lenexp_addr_i[3:0] - attribute \src "libresoc.v:161303.5-161303.29" + attribute \src "libresoc.v:162611.5-162611.29" switch \initial - attribute \src "libresoc.v:161303.9-161303.17" + attribute \src "libresoc.v:162611.9-162611.17" case 1'1 case end @@ -332010,15 +303380,15 @@ module \pimem sync always update \lenexp_addr_i $0\lenexp_addr_i[3:0] end - attribute \src "libresoc.v:161318.3-161343.6" - process $proc$libresoc.v:161318$8687 + attribute \src "libresoc.v:162626.3-162651.6" + process $proc$libresoc.v:162626$8671 assign { } { } assign { } { } assign { } { } assign $0\valid_l_s_valid[0:0] $3\valid_l_s_valid[0:0] - attribute \src "libresoc.v:161319.5-161319.29" + attribute \src "libresoc.v:162627.5-162627.29" switch \initial - attribute \src "libresoc.v:161319.9-161319.17" + attribute \src "libresoc.v:162627.9-162627.17" case 1'1 case end @@ -332061,15 +303431,15 @@ module \pimem sync always update \valid_l_s_valid $0\valid_l_s_valid[0:0] end - attribute \src "libresoc.v:161344.3-161369.6" - process $proc$libresoc.v:161344$8688 + attribute \src "libresoc.v:162652.3-162677.6" + process $proc$libresoc.v:162652$8672 assign { } { } assign { } { } assign { } { } assign $0\x_mask_i[7:0] $3\x_mask_i[7:0] - attribute \src "libresoc.v:161345.5-161345.29" + attribute \src "libresoc.v:162653.5-162653.29" switch \initial - attribute \src "libresoc.v:161345.9-161345.17" + attribute \src "libresoc.v:162653.9-162653.17" case 1'1 case end @@ -332112,15 +303482,15 @@ module \pimem sync always update \x_mask_i $0\x_mask_i[7:0] end - attribute \src "libresoc.v:161370.3-161395.6" - process $proc$libresoc.v:161370$8689 + attribute \src "libresoc.v:162678.3-162703.6" + process $proc$libresoc.v:162678$8673 assign { } { } assign { } { } assign { } { } assign $0\x_addr_i[47:0] $3\x_addr_i[47:0] - attribute \src "libresoc.v:161371.5-161371.29" + attribute \src "libresoc.v:162679.5-162679.29" switch \initial - attribute \src "libresoc.v:161371.9-161371.17" + attribute \src "libresoc.v:162679.9-162679.17" case 1'1 case end @@ -332163,15 +303533,15 @@ module \pimem sync always update \x_addr_i $0\x_addr_i[47:0] end - attribute \src "libresoc.v:161396.3-161426.6" - process $proc$libresoc.v:161396$8690 + attribute \src "libresoc.v:162704.3-162734.6" + process $proc$libresoc.v:162704$8674 assign { } { } assign { } { } assign { } { } assign $0\ldst_port0_addr_ok_o[0:0] $3\ldst_port0_addr_ok_o[0:0] - attribute \src "libresoc.v:161397.5-161397.29" + attribute \src "libresoc.v:162705.5-162705.29" switch \initial - attribute \src "libresoc.v:161397.9-161397.17" + attribute \src "libresoc.v:162705.9-162705.17" case 1'1 case end @@ -332223,15 +303593,15 @@ module \pimem sync always update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0] end - attribute \src "libresoc.v:161427.3-161442.6" - process $proc$libresoc.v:161427$8691 + attribute \src "libresoc.v:162735.3-162750.6" + process $proc$libresoc.v:162735$8675 assign { } { } assign { } { } assign { } { } assign $0\reset_l_s_reset[0:0] $2\reset_l_s_reset[0:0] - attribute \src "libresoc.v:161428.5-161428.29" + attribute \src "libresoc.v:162736.5-162736.29" switch \initial - attribute \src "libresoc.v:161428.9-161428.17" + attribute \src "libresoc.v:162736.9-162736.17" case 1'1 case end @@ -332256,14 +303626,14 @@ module \pimem sync always update \reset_l_s_reset $0\reset_l_s_reset[0:0] end - attribute \src "libresoc.v:161443.3-161452.6" - process $proc$libresoc.v:161443$8692 + attribute \src "libresoc.v:162751.3-162760.6" + process $proc$libresoc.v:162751$8676 assign { } { } assign { } { } assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0] - attribute \src "libresoc.v:161444.5-161444.29" + attribute \src "libresoc.v:162752.5-162752.29" switch \initial - attribute \src "libresoc.v:161444.9-161444.17" + attribute \src "libresoc.v:162752.9-162752.17" case 1'1 case end @@ -332279,14 +303649,14 @@ module \pimem sync always update \reset_l_r_reset $0\reset_l_r_reset[0:0] end - attribute \src "libresoc.v:161453.3-161462.6" - process $proc$libresoc.v:161453$8693 + attribute \src "libresoc.v:162761.3-162770.6" + process $proc$libresoc.v:162761$8677 assign { } { } assign { } { } assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0] - attribute \src "libresoc.v:161454.5-161454.29" + attribute \src "libresoc.v:162762.5-162762.29" switch \initial - attribute \src "libresoc.v:161454.9-161454.17" + attribute \src "libresoc.v:162762.9-162762.17" case 1'1 case end @@ -332302,14 +303672,14 @@ module \pimem sync always update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0] end - attribute \src "libresoc.v:161463.3-161472.6" - process $proc$libresoc.v:161463$8694 + attribute \src "libresoc.v:162771.3-162780.6" + process $proc$libresoc.v:162771$8678 assign { } { } assign { } { } assign $0\ld_active_r_ld_active[0:0] $1\ld_active_r_ld_active[0:0] - attribute \src "libresoc.v:161464.5-161464.29" + attribute \src "libresoc.v:162772.5-162772.29" switch \initial - attribute \src "libresoc.v:161464.9-161464.17" + attribute \src "libresoc.v:162772.9-162772.17" case 1'1 case end @@ -332325,14 +303695,14 @@ module \pimem sync always update \ld_active_r_ld_active $0\ld_active_r_ld_active[0:0] end - attribute \src "libresoc.v:161473.3-161482.6" - process $proc$libresoc.v:161473$8695 + attribute \src "libresoc.v:162781.3-162790.6" + process $proc$libresoc.v:162781$8679 assign { } { } assign { } { } assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0] - attribute \src "libresoc.v:161474.5-161474.29" + attribute \src "libresoc.v:162782.5-162782.29" switch \initial - attribute \src "libresoc.v:161474.9-161474.17" + attribute \src "libresoc.v:162782.9-162782.17" case 1'1 case end @@ -332348,14 +303718,14 @@ module \pimem sync always update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0] end - attribute \src "libresoc.v:161483.3-161492.6" - process $proc$libresoc.v:161483$8696 + attribute \src "libresoc.v:162791.3-162800.6" + process $proc$libresoc.v:162791$8680 assign { } { } assign { } { } assign $0\stdata[63:0] $1\stdata[63:0] - attribute \src "libresoc.v:161484.5-161484.29" + attribute \src "libresoc.v:162792.5-162792.29" switch \initial - attribute \src "libresoc.v:161484.9-161484.17" + attribute \src "libresoc.v:162792.9-162792.17" case 1'1 case end @@ -332371,14 +303741,14 @@ module \pimem sync always update \stdata $0\stdata[63:0] end - attribute \src "libresoc.v:161493.3-161502.6" - process $proc$libresoc.v:161493$8697 + attribute \src "libresoc.v:162801.3-162810.6" + process $proc$libresoc.v:162801$8681 assign { } { } assign { } { } assign $0\x_st_data_i[63:0] $1\x_st_data_i[63:0] - attribute \src "libresoc.v:161494.5-161494.29" + attribute \src "libresoc.v:162802.5-162802.29" switch \initial - attribute \src "libresoc.v:161494.9-161494.17" + attribute \src "libresoc.v:162802.9-162802.17" case 1'1 case end @@ -332394,14 +303764,14 @@ module \pimem sync always update \x_st_data_i $0\x_st_data_i[63:0] end - attribute \src "libresoc.v:161503.3-161522.6" - process $proc$libresoc.v:161503$8698 + attribute \src "libresoc.v:162811.3-162830.6" + process $proc$libresoc.v:162811$8682 assign { } { } assign { } { } assign $0\lsui_busy[0:0] $1\lsui_busy[0:0] - attribute \src "libresoc.v:161504.5-161504.29" + attribute \src "libresoc.v:162812.5-162812.29" switch \initial - attribute \src "libresoc.v:161504.9-161504.17" + attribute \src "libresoc.v:162812.9-162812.17" case 1'1 case end @@ -332430,15 +303800,15 @@ module \pimem sync always update \lsui_busy $0\lsui_busy[0:0] end - attribute \src "libresoc.v:161523.3-161561.6" - process $proc$libresoc.v:161523$8699 + attribute \src "libresoc.v:162831.3-162869.6" + process $proc$libresoc.v:162831$8683 assign { } { } assign { } { } assign { } { } - assign $0\fsm_state$next[1:0]$8700 $5\fsm_state$next[1:0]$8705 - attribute \src "libresoc.v:161524.5-161524.29" + assign $0\fsm_state$next[1:0]$8684 $5\fsm_state$next[1:0]$8689 + attribute \src "libresoc.v:162832.5-162832.29" switch \initial - attribute \src "libresoc.v:161524.9-161524.17" + attribute \src "libresoc.v:162832.9-162832.17" case 1'1 case end @@ -332447,65 +303817,65 @@ module \pimem attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\fsm_state$next[1:0]$8701 $2\fsm_state$next[1:0]$8702 + assign $1\fsm_state$next[1:0]$8685 $2\fsm_state$next[1:0]$8686 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" switch \$69 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fsm_state$next[1:0]$8702 2'01 + assign $2\fsm_state$next[1:0]$8686 2'01 case - assign $2\fsm_state$next[1:0]$8702 \fsm_state + assign $2\fsm_state$next[1:0]$8686 \fsm_state end attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\fsm_state$next[1:0]$8701 $3\fsm_state$next[1:0]$8703 + assign $1\fsm_state$next[1:0]$8685 $3\fsm_state$next[1:0]$8687 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" switch \$71 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\fsm_state$next[1:0]$8703 2'10 + assign $3\fsm_state$next[1:0]$8687 2'10 case - assign $3\fsm_state$next[1:0]$8703 \fsm_state + assign $3\fsm_state$next[1:0]$8687 \fsm_state end attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\fsm_state$next[1:0]$8701 $4\fsm_state$next[1:0]$8704 + assign $1\fsm_state$next[1:0]$8685 $4\fsm_state$next[1:0]$8688 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" switch \$77 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\fsm_state$next[1:0]$8704 2'00 + assign $4\fsm_state$next[1:0]$8688 2'00 case - assign $4\fsm_state$next[1:0]$8704 \fsm_state + assign $4\fsm_state$next[1:0]$8688 \fsm_state end case - assign $1\fsm_state$next[1:0]$8701 \fsm_state + assign $1\fsm_state$next[1:0]$8685 \fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fsm_state$next[1:0]$8705 2'00 + assign $5\fsm_state$next[1:0]$8689 2'00 case - assign $5\fsm_state$next[1:0]$8705 $1\fsm_state$next[1:0]$8701 + assign $5\fsm_state$next[1:0]$8689 $1\fsm_state$next[1:0]$8685 end sync always - update \fsm_state$next $0\fsm_state$next[1:0]$8700 + update \fsm_state$next $0\fsm_state$next[1:0]$8684 end - attribute \src "libresoc.v:161562.3-161571.6" - process $proc$libresoc.v:161562$8706 + attribute \src "libresoc.v:162870.3-162879.6" + process $proc$libresoc.v:162870$8690 assign { } { } assign { } { } assign $0\cyc_l_s_cyc[0:0] $1\cyc_l_s_cyc[0:0] - attribute \src "libresoc.v:161563.5-161563.29" + attribute \src "libresoc.v:162871.5-162871.29" switch \initial - attribute \src "libresoc.v:161563.9-161563.17" + attribute \src "libresoc.v:162871.9-162871.17" case 1'1 case end @@ -332521,14 +303891,14 @@ module \pimem sync always update \cyc_l_s_cyc $0\cyc_l_s_cyc[0:0] end - attribute \src "libresoc.v:161572.3-161580.6" - process $proc$libresoc.v:161572$8707 + attribute \src "libresoc.v:162880.3-162888.6" + process $proc$libresoc.v:162880$8691 assign { } { } assign { } { } - assign $0\lsui_active_dly$next[0:0]$8708 $1\lsui_active_dly$next[0:0]$8709 - attribute \src "libresoc.v:161573.5-161573.29" + assign $0\lsui_active_dly$next[0:0]$8692 $1\lsui_active_dly$next[0:0]$8693 + attribute \src "libresoc.v:162881.5-162881.29" switch \initial - attribute \src "libresoc.v:161573.9-161573.17" + attribute \src "libresoc.v:162881.9-162881.17" case 1'1 case end @@ -332537,21 +303907,21 @@ module \pimem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\lsui_active_dly$next[0:0]$8709 1'0 + assign $1\lsui_active_dly$next[0:0]$8693 1'0 case - assign $1\lsui_active_dly$next[0:0]$8709 \lsui_active + assign $1\lsui_active_dly$next[0:0]$8693 \lsui_active end sync always - update \lsui_active_dly$next $0\lsui_active_dly$next[0:0]$8708 + update \lsui_active_dly$next $0\lsui_active_dly$next[0:0]$8692 end - attribute \src "libresoc.v:161581.3-161590.6" - process $proc$libresoc.v:161581$8710 + attribute \src "libresoc.v:162889.3-162898.6" + process $proc$libresoc.v:162889$8694 assign { } { } assign { } { } assign $0\cyc_l_r_cyc[0:0] $1\cyc_l_r_cyc[0:0] - attribute \src "libresoc.v:161582.5-161582.29" + attribute \src "libresoc.v:162890.5-162890.29" switch \initial - attribute \src "libresoc.v:161582.9-161582.17" + attribute \src "libresoc.v:162890.9-162890.17" case 1'1 case end @@ -332567,14 +303937,14 @@ module \pimem sync always update \cyc_l_r_cyc $0\cyc_l_r_cyc[0:0] end - attribute \src "libresoc.v:161591.3-161600.6" - process $proc$libresoc.v:161591$8711 + attribute \src "libresoc.v:162899.3-162908.6" + process $proc$libresoc.v:162899$8695 assign { } { } assign { } { } assign $0\busy_l_s_busy[0:0] $1\busy_l_s_busy[0:0] - attribute \src "libresoc.v:161592.5-161592.29" + attribute \src "libresoc.v:162900.5-162900.29" switch \initial - attribute \src "libresoc.v:161592.9-161592.17" + attribute \src "libresoc.v:162900.9-162900.17" case 1'1 case end @@ -332590,15 +303960,15 @@ module \pimem sync always update \busy_l_s_busy $0\busy_l_s_busy[0:0] end - attribute \src "libresoc.v:161601.3-161616.6" - process $proc$libresoc.v:161601$8712 + attribute \src "libresoc.v:162909.3-162924.6" + process $proc$libresoc.v:162909$8696 assign { } { } assign { } { } assign { } { } assign $0\busy_l_r_busy[0:0] $2\busy_l_r_busy[0:0] - attribute \src "libresoc.v:161602.5-161602.29" + attribute \src "libresoc.v:162910.5-162910.29" switch \initial - attribute \src "libresoc.v:161602.9-161602.17" + attribute \src "libresoc.v:162910.9-162910.17" case 1'1 case end @@ -332623,16 +303993,16 @@ module \pimem sync always update \busy_l_r_busy $0\busy_l_r_busy[0:0] end - attribute \src "libresoc.v:161617.3-161652.6" - process $proc$libresoc.v:161617$8713 + attribute \src "libresoc.v:162925.3-162960.6" + process $proc$libresoc.v:162925$8697 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\adrok_l_s_addr_acked$next[0:0]$8714 $6\adrok_l_s_addr_acked$next[0:0]$8720 - attribute \src "libresoc.v:161618.5-161618.29" + assign $0\adrok_l_s_addr_acked$next[0:0]$8698 $6\adrok_l_s_addr_acked$next[0:0]$8704 + attribute \src "libresoc.v:162926.5-162926.29" switch \initial - attribute \src "libresoc.v:161618.9-161618.17" + attribute \src "libresoc.v:162926.9-162926.17" case 1'1 case end @@ -332641,67 +304011,67 @@ module \pimem attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\adrok_l_s_addr_acked$next[0:0]$8715 $2\adrok_l_s_addr_acked$next[0:0]$8716 + assign $1\adrok_l_s_addr_acked$next[0:0]$8699 $2\adrok_l_s_addr_acked$next[0:0]$8700 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233" switch \$7 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\adrok_l_s_addr_acked$next[0:0]$8716 1'1 + assign $2\adrok_l_s_addr_acked$next[0:0]$8700 1'1 case - assign $2\adrok_l_s_addr_acked$next[0:0]$8716 1'0 + assign $2\adrok_l_s_addr_acked$next[0:0]$8700 1'0 end case - assign $1\adrok_l_s_addr_acked$next[0:0]$8715 1'0 + assign $1\adrok_l_s_addr_acked$next[0:0]$8699 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" switch \st_active_q_st_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\adrok_l_s_addr_acked$next[0:0]$8717 $4\adrok_l_s_addr_acked$next[0:0]$8718 + assign $3\adrok_l_s_addr_acked$next[0:0]$8701 $4\adrok_l_s_addr_acked$next[0:0]$8702 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:245" switch \ldst_port0_addr_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\adrok_l_s_addr_acked$next[0:0]$8718 $5\adrok_l_s_addr_acked$next[0:0]$8719 + assign $4\adrok_l_s_addr_acked$next[0:0]$8702 $5\adrok_l_s_addr_acked$next[0:0]$8703 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" switch \adrok_l_qn_addr_acked attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\adrok_l_s_addr_acked$next[0:0]$8719 1'1 + assign $5\adrok_l_s_addr_acked$next[0:0]$8703 1'1 case - assign $5\adrok_l_s_addr_acked$next[0:0]$8719 $1\adrok_l_s_addr_acked$next[0:0]$8715 + assign $5\adrok_l_s_addr_acked$next[0:0]$8703 $1\adrok_l_s_addr_acked$next[0:0]$8699 end case - assign $4\adrok_l_s_addr_acked$next[0:0]$8718 $1\adrok_l_s_addr_acked$next[0:0]$8715 + assign $4\adrok_l_s_addr_acked$next[0:0]$8702 $1\adrok_l_s_addr_acked$next[0:0]$8699 end case - assign $3\adrok_l_s_addr_acked$next[0:0]$8717 $1\adrok_l_s_addr_acked$next[0:0]$8715 + assign $3\adrok_l_s_addr_acked$next[0:0]$8701 $1\adrok_l_s_addr_acked$next[0:0]$8699 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\adrok_l_s_addr_acked$next[0:0]$8720 1'0 + assign $6\adrok_l_s_addr_acked$next[0:0]$8704 1'0 case - assign $6\adrok_l_s_addr_acked$next[0:0]$8720 $3\adrok_l_s_addr_acked$next[0:0]$8717 + assign $6\adrok_l_s_addr_acked$next[0:0]$8704 $3\adrok_l_s_addr_acked$next[0:0]$8701 end sync always - update \adrok_l_s_addr_acked$next $0\adrok_l_s_addr_acked$next[0:0]$8714 + update \adrok_l_s_addr_acked$next $0\adrok_l_s_addr_acked$next[0:0]$8698 end - attribute \src "libresoc.v:161653.3-161668.6" - process $proc$libresoc.v:161653$8721 + attribute \src "libresoc.v:162961.3-162976.6" + process $proc$libresoc.v:162961$8705 assign { } { } assign { } { } assign { } { } assign $0\adrok_l_r_addr_acked[0:0] $2\adrok_l_r_addr_acked[0:0] - attribute \src "libresoc.v:161654.5-161654.29" + attribute \src "libresoc.v:162962.5-162962.29" switch \initial - attribute \src "libresoc.v:161654.9-161654.17" + attribute \src "libresoc.v:162962.9-162962.17" case 1'1 case end @@ -332726,47 +304096,47 @@ module \pimem sync always update \adrok_l_r_addr_acked $0\adrok_l_r_addr_acked[0:0] end - connect \$9 $not$libresoc.v:161122$8625_Y - connect \$11 $and$libresoc.v:161123$8626_Y - connect \$13 $not$libresoc.v:161124$8627_Y - connect \$15 $and$libresoc.v:161125$8628_Y - connect \$17 $not$libresoc.v:161126$8629_Y - connect \$1 $and$libresoc.v:161127$8630_Y - connect \$19 $and$libresoc.v:161128$8631_Y - connect \$21 $pos$libresoc.v:161129$8633_Y - connect \$23 $pos$libresoc.v:161130$8635_Y - connect \$25 $and$libresoc.v:161131$8636_Y - connect \$27 $and$libresoc.v:161132$8637_Y - connect \$29 $and$libresoc.v:161133$8638_Y - connect \$31 $and$libresoc.v:161134$8639_Y - connect \$33 $and$libresoc.v:161135$8640_Y - connect \$35 $not$libresoc.v:161136$8641_Y - connect \$38 $or$libresoc.v:161137$8642_Y - connect \$3 $or$libresoc.v:161138$8643_Y - connect \$37 $not$libresoc.v:161139$8644_Y - connect \$42 $and$libresoc.v:161140$8645_Y - connect \$44 $mul$libresoc.v:161141$8646_Y - connect \$46 $sshr$libresoc.v:161142$8647_Y - connect \$48 $and$libresoc.v:161143$8648_Y - connect \$50 $and$libresoc.v:161144$8649_Y - connect \$52 $not$libresoc.v:161145$8650_Y - connect \$54 $and$libresoc.v:161146$8651_Y - connect \$57 $mul$libresoc.v:161147$8652_Y - connect \$5 $not$libresoc.v:161148$8653_Y - connect \$59 $sshl$libresoc.v:161149$8654_Y - connect \$61 $and$libresoc.v:161150$8655_Y - connect \$63 $or$libresoc.v:161151$8656_Y - connect \$65 $and$libresoc.v:161152$8657_Y - connect \$67 $or$libresoc.v:161153$8658_Y - connect \$69 $and$libresoc.v:161154$8659_Y - connect \$71 $not$libresoc.v:161155$8660_Y - connect \$73 $not$libresoc.v:161156$8661_Y - connect \$75 $not$libresoc.v:161157$8662_Y - connect \$77 $and$libresoc.v:161158$8663_Y - connect \$7 $and$libresoc.v:161159$8664_Y - connect \$79 $not$libresoc.v:161160$8665_Y - connect \$81 $not$libresoc.v:161161$8666_Y - connect \$83 $and$libresoc.v:161162$8667_Y + connect \$9 $not$libresoc.v:162430$8609_Y + connect \$11 $and$libresoc.v:162431$8610_Y + connect \$13 $not$libresoc.v:162432$8611_Y + connect \$15 $and$libresoc.v:162433$8612_Y + connect \$17 $not$libresoc.v:162434$8613_Y + connect \$1 $and$libresoc.v:162435$8614_Y + connect \$19 $and$libresoc.v:162436$8615_Y + connect \$21 $pos$libresoc.v:162437$8617_Y + connect \$23 $pos$libresoc.v:162438$8619_Y + connect \$25 $and$libresoc.v:162439$8620_Y + connect \$27 $and$libresoc.v:162440$8621_Y + connect \$29 $and$libresoc.v:162441$8622_Y + connect \$31 $and$libresoc.v:162442$8623_Y + connect \$33 $and$libresoc.v:162443$8624_Y + connect \$35 $not$libresoc.v:162444$8625_Y + connect \$38 $or$libresoc.v:162445$8626_Y + connect \$3 $or$libresoc.v:162446$8627_Y + connect \$37 $not$libresoc.v:162447$8628_Y + connect \$42 $and$libresoc.v:162448$8629_Y + connect \$44 $mul$libresoc.v:162449$8630_Y + connect \$46 $sshr$libresoc.v:162450$8631_Y + connect \$48 $and$libresoc.v:162451$8632_Y + connect \$50 $and$libresoc.v:162452$8633_Y + connect \$52 $not$libresoc.v:162453$8634_Y + connect \$54 $and$libresoc.v:162454$8635_Y + connect \$57 $mul$libresoc.v:162455$8636_Y + connect \$5 $not$libresoc.v:162456$8637_Y + connect \$59 $sshl$libresoc.v:162457$8638_Y + connect \$61 $and$libresoc.v:162458$8639_Y + connect \$63 $or$libresoc.v:162459$8640_Y + connect \$65 $and$libresoc.v:162460$8641_Y + connect \$67 $or$libresoc.v:162461$8642_Y + connect \$69 $and$libresoc.v:162462$8643_Y + connect \$71 $not$libresoc.v:162463$8644_Y + connect \$73 $not$libresoc.v:162464$8645_Y + connect \$75 $not$libresoc.v:162465$8646_Y + connect \$77 $and$libresoc.v:162466$8647_Y + connect \$7 $and$libresoc.v:162467$8648_Y + connect \$79 $not$libresoc.v:162468$8649_Y + connect \$81 $not$libresoc.v:162469$8650_Y + connect \$83 $and$libresoc.v:162470$8651_Y connect \$41 \$46 connect \$56 \$59 connect \valid_l_r_valid \lsui_active_rise @@ -332789,116 +304159,116 @@ module \pimem connect \sts \ldst_port0_is_st_i connect \lds \ldst_port0_is_ld_i end -attribute \src "libresoc.v:161694.1-162474.10" +attribute \src "libresoc.v:163002.1-163782.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.alu_cr0.pipe" attribute \generator "nMigen" module \pipe - attribute \src "libresoc.v:162437.3-162455.6" - wire width 4 $0\cr_a$6$next[3:0]$8777 - attribute \src "libresoc.v:162301.3-162302.31" - wire width 4 $0\cr_a$6[3:0]$8733 - attribute \src "libresoc.v:161708.13-161708.28" - wire width 4 $0\cr_a$6[3:0]$8783 - attribute \src "libresoc.v:162437.3-162455.6" - wire $0\cr_a_ok$next[0:0]$8776 - attribute \src "libresoc.v:162303.3-162304.31" + attribute \src "libresoc.v:163745.3-163763.6" + wire width 4 $0\cr_a$6$next[3:0]$8761 + attribute \src "libresoc.v:163609.3-163610.31" + wire width 4 $0\cr_a$6[3:0]$8717 + attribute \src "libresoc.v:163016.13-163016.28" + wire width 4 $0\cr_a$6[3:0]$8767 + attribute \src "libresoc.v:163745.3-163763.6" + wire $0\cr_a_ok$next[0:0]$8760 + attribute \src "libresoc.v:163611.3-163612.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:162384.3-162398.6" - wire width 14 $0\cr_op__fn_unit$3$next[13:0]$8757 - attribute \src "libresoc.v:162315.3-162316.51" - wire width 14 $0\cr_op__fn_unit$3[13:0]$8743 - attribute \src "libresoc.v:161773.14-161773.43" - wire width 14 $0\cr_op__fn_unit$3[13:0]$8786 - attribute \src "libresoc.v:162384.3-162398.6" - wire width 32 $0\cr_op__insn$4$next[31:0]$8758 - attribute \src "libresoc.v:162317.3-162318.45" - wire width 32 $0\cr_op__insn$4[31:0]$8745 - attribute \src "libresoc.v:161782.14-161782.37" - wire width 32 $0\cr_op__insn$4[31:0]$8788 - attribute \src "libresoc.v:162384.3-162398.6" - wire width 7 $0\cr_op__insn_type$2$next[6:0]$8759 - attribute \src "libresoc.v:162313.3-162314.55" - wire width 7 $0\cr_op__insn_type$2[6:0]$8741 - attribute \src "libresoc.v:162016.13-162016.41" - wire width 7 $0\cr_op__insn_type$2[6:0]$8790 - attribute \src "libresoc.v:162418.3-162436.6" - wire width 32 $0\full_cr$5$next[31:0]$8770 - attribute \src "libresoc.v:162305.3-162306.37" - wire width 32 $0\full_cr$5[31:0]$8736 - attribute \src "libresoc.v:162025.14-162025.33" - wire width 32 $0\full_cr$5[31:0]$8792 - attribute \src "libresoc.v:162418.3-162436.6" - wire $0\full_cr_ok$next[0:0]$8771 - attribute \src "libresoc.v:162307.3-162308.37" + attribute \src "libresoc.v:163692.3-163706.6" + wire width 14 $0\cr_op__fn_unit$3$next[13:0]$8741 + attribute \src "libresoc.v:163623.3-163624.51" + wire width 14 $0\cr_op__fn_unit$3[13:0]$8727 + attribute \src "libresoc.v:163081.14-163081.43" + wire width 14 $0\cr_op__fn_unit$3[13:0]$8770 + attribute \src "libresoc.v:163692.3-163706.6" + wire width 32 $0\cr_op__insn$4$next[31:0]$8742 + attribute \src "libresoc.v:163625.3-163626.45" + wire width 32 $0\cr_op__insn$4[31:0]$8729 + attribute \src "libresoc.v:163090.14-163090.37" + wire width 32 $0\cr_op__insn$4[31:0]$8772 + attribute \src "libresoc.v:163692.3-163706.6" + wire width 7 $0\cr_op__insn_type$2$next[6:0]$8743 + attribute \src "libresoc.v:163621.3-163622.55" + wire width 7 $0\cr_op__insn_type$2[6:0]$8725 + attribute \src "libresoc.v:163324.13-163324.41" + wire width 7 $0\cr_op__insn_type$2[6:0]$8774 + attribute \src "libresoc.v:163726.3-163744.6" + wire width 32 $0\full_cr$5$next[31:0]$8754 + attribute \src "libresoc.v:163613.3-163614.37" + wire width 32 $0\full_cr$5[31:0]$8720 + attribute \src "libresoc.v:163333.14-163333.33" + wire width 32 $0\full_cr$5[31:0]$8776 + attribute \src "libresoc.v:163726.3-163744.6" + wire $0\full_cr_ok$next[0:0]$8755 + attribute \src "libresoc.v:163615.3-163616.37" wire $0\full_cr_ok[0:0] - attribute \src "libresoc.v:161695.7-161695.20" + attribute \src "libresoc.v:163003.7-163003.20" wire $0\initial[0:0] - attribute \src "libresoc.v:162371.3-162383.6" - wire width 2 $0\muxid$1$next[1:0]$8754 - attribute \src "libresoc.v:162319.3-162320.33" - wire width 2 $0\muxid$1[1:0]$8747 - attribute \src "libresoc.v:162259.13-162259.29" - wire width 2 $0\muxid$1[1:0]$8795 - attribute \src "libresoc.v:162399.3-162417.6" - wire width 64 $0\o$next[63:0]$8764 - attribute \src "libresoc.v:162309.3-162310.19" + attribute \src "libresoc.v:163679.3-163691.6" + wire width 2 $0\muxid$1$next[1:0]$8738 + attribute \src "libresoc.v:163627.3-163628.33" + wire width 2 $0\muxid$1[1:0]$8731 + attribute \src "libresoc.v:163567.13-163567.29" + wire width 2 $0\muxid$1[1:0]$8779 + attribute \src "libresoc.v:163707.3-163725.6" + wire width 64 $0\o$next[63:0]$8748 + attribute \src "libresoc.v:163617.3-163618.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:162399.3-162417.6" - wire $0\o_ok$next[0:0]$8765 - attribute \src "libresoc.v:162311.3-162312.25" + attribute \src "libresoc.v:163707.3-163725.6" + wire $0\o_ok$next[0:0]$8749 + attribute \src "libresoc.v:163619.3-163620.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:162353.3-162370.6" - wire $0\r_busy$next[0:0]$8750 - attribute \src "libresoc.v:162321.3-162322.29" + attribute \src "libresoc.v:163661.3-163678.6" + wire $0\r_busy$next[0:0]$8734 + attribute \src "libresoc.v:163629.3-163630.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:162437.3-162455.6" - wire width 4 $1\cr_a$6$next[3:0]$8779 - attribute \src "libresoc.v:162437.3-162455.6" - wire $1\cr_a_ok$next[0:0]$8778 - attribute \src "libresoc.v:161713.7-161713.21" + attribute \src "libresoc.v:163745.3-163763.6" + wire width 4 $1\cr_a$6$next[3:0]$8763 + attribute \src "libresoc.v:163745.3-163763.6" + wire $1\cr_a_ok$next[0:0]$8762 + attribute \src "libresoc.v:163021.7-163021.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:162384.3-162398.6" - wire width 14 $1\cr_op__fn_unit$3$next[13:0]$8760 - attribute \src "libresoc.v:162384.3-162398.6" - wire width 32 $1\cr_op__insn$4$next[31:0]$8761 - attribute \src "libresoc.v:162384.3-162398.6" - wire width 7 $1\cr_op__insn_type$2$next[6:0]$8762 - attribute \src "libresoc.v:162418.3-162436.6" - wire width 32 $1\full_cr$5$next[31:0]$8772 - attribute \src "libresoc.v:162418.3-162436.6" - wire $1\full_cr_ok$next[0:0]$8773 - attribute \src "libresoc.v:162030.7-162030.24" + attribute \src "libresoc.v:163692.3-163706.6" + wire width 14 $1\cr_op__fn_unit$3$next[13:0]$8744 + attribute \src "libresoc.v:163692.3-163706.6" + wire width 32 $1\cr_op__insn$4$next[31:0]$8745 + attribute \src "libresoc.v:163692.3-163706.6" + wire width 7 $1\cr_op__insn_type$2$next[6:0]$8746 + attribute \src "libresoc.v:163726.3-163744.6" + wire width 32 $1\full_cr$5$next[31:0]$8756 + attribute \src "libresoc.v:163726.3-163744.6" + wire $1\full_cr_ok$next[0:0]$8757 + attribute \src "libresoc.v:163338.7-163338.24" wire $1\full_cr_ok[0:0] - attribute \src "libresoc.v:162371.3-162383.6" - wire width 2 $1\muxid$1$next[1:0]$8755 - attribute \src "libresoc.v:162399.3-162417.6" - wire width 64 $1\o$next[63:0]$8766 - attribute \src "libresoc.v:162272.14-162272.38" + attribute \src "libresoc.v:163679.3-163691.6" + wire width 2 $1\muxid$1$next[1:0]$8739 + attribute \src "libresoc.v:163707.3-163725.6" + wire width 64 $1\o$next[63:0]$8750 + attribute \src "libresoc.v:163580.14-163580.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:162399.3-162417.6" - wire $1\o_ok$next[0:0]$8767 - attribute \src "libresoc.v:162279.7-162279.18" + attribute \src "libresoc.v:163707.3-163725.6" + wire $1\o_ok$next[0:0]$8751 + attribute \src "libresoc.v:163587.7-163587.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:162353.3-162370.6" - wire $1\r_busy$next[0:0]$8751 - attribute \src "libresoc.v:162293.7-162293.20" + attribute \src "libresoc.v:163661.3-163678.6" + wire $1\r_busy$next[0:0]$8735 + attribute \src "libresoc.v:163601.7-163601.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:162437.3-162455.6" - wire $2\cr_a_ok$next[0:0]$8780 - attribute \src "libresoc.v:162418.3-162436.6" - wire $2\full_cr_ok$next[0:0]$8774 - attribute \src "libresoc.v:162399.3-162417.6" - wire $2\o_ok$next[0:0]$8768 - attribute \src "libresoc.v:162353.3-162370.6" - wire $2\r_busy$next[0:0]$8752 - attribute \src "libresoc.v:162300.18-162300.118" - wire $and$libresoc.v:162300$8731_Y + attribute \src "libresoc.v:163745.3-163763.6" + wire $2\cr_a_ok$next[0:0]$8764 + attribute \src "libresoc.v:163726.3-163744.6" + wire $2\full_cr_ok$next[0:0]$8758 + attribute \src "libresoc.v:163707.3-163725.6" + wire $2\o_ok$next[0:0]$8752 + attribute \src "libresoc.v:163661.3-163678.6" + wire $2\r_busy$next[0:0]$8736 + attribute \src "libresoc.v:163608.18-163608.118" + wire $and$libresoc.v:163608$8715_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 26 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 11 \cr_a @@ -333226,7 +304596,7 @@ module \pipe wire \full_cr_ok$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \full_cr_ok$next - attribute \src "libresoc.v:161695.7-161695.15" + attribute \src "libresoc.v:163003.7-163003.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 \main_cr_a @@ -333491,7 +304861,7 @@ module \pipe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 9 \rb attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:162300$8731 + cell $and $and$libresoc.v:163608$8715 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -333499,10 +304869,10 @@ module \pipe parameter \Y_WIDTH 1 connect \A \p_valid_i$13 connect \B \p_ready_o - connect \Y $and$libresoc.v:162300$8731_Y + connect \Y $and$libresoc.v:163608$8715_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:162323.12-162344.4" + attribute \src "libresoc.v:163631.12-163652.4" cell \main$9 \main connect \cr_a \main_cr_a connect \cr_a$6 \main_cr_a$12 @@ -333526,199 +304896,199 @@ module \pipe connect \rb \main_rb end attribute \module_not_derived 1 - attribute \src "libresoc.v:162345.9-162348.4" + attribute \src "libresoc.v:163653.9-163656.4" cell \n$8 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:162349.9-162352.4" + attribute \src "libresoc.v:163657.9-163660.4" cell \p$7 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:161695.7-161695.20" - process $proc$libresoc.v:161695$8781 + attribute \src "libresoc.v:163003.7-163003.20" + process $proc$libresoc.v:163003$8765 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:161708.13-161708.28" - process $proc$libresoc.v:161708$8782 + attribute \src "libresoc.v:163016.13-163016.28" + process $proc$libresoc.v:163016$8766 assign { } { } - assign $0\cr_a$6[3:0]$8783 4'0000 + assign $0\cr_a$6[3:0]$8767 4'0000 sync always sync init - update \cr_a$6 $0\cr_a$6[3:0]$8783 + update \cr_a$6 $0\cr_a$6[3:0]$8767 end - attribute \src "libresoc.v:161713.7-161713.21" - process $proc$libresoc.v:161713$8784 + attribute \src "libresoc.v:163021.7-163021.21" + process $proc$libresoc.v:163021$8768 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:161773.14-161773.43" - process $proc$libresoc.v:161773$8785 + attribute \src "libresoc.v:163081.14-163081.43" + process $proc$libresoc.v:163081$8769 assign { } { } - assign $0\cr_op__fn_unit$3[13:0]$8786 14'00000000000000 + assign $0\cr_op__fn_unit$3[13:0]$8770 14'00000000000000 sync always sync init - update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[13:0]$8786 + update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[13:0]$8770 end - attribute \src "libresoc.v:161782.14-161782.37" - process $proc$libresoc.v:161782$8787 + attribute \src "libresoc.v:163090.14-163090.37" + process $proc$libresoc.v:163090$8771 assign { } { } - assign $0\cr_op__insn$4[31:0]$8788 0 + assign $0\cr_op__insn$4[31:0]$8772 0 sync always sync init - update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8788 + update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8772 end - attribute \src "libresoc.v:162016.13-162016.41" - process $proc$libresoc.v:162016$8789 + attribute \src "libresoc.v:163324.13-163324.41" + process $proc$libresoc.v:163324$8773 assign { } { } - assign $0\cr_op__insn_type$2[6:0]$8790 7'0000000 + assign $0\cr_op__insn_type$2[6:0]$8774 7'0000000 sync always sync init - update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8790 + update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8774 end - attribute \src "libresoc.v:162025.14-162025.33" - process $proc$libresoc.v:162025$8791 + attribute \src "libresoc.v:163333.14-163333.33" + process $proc$libresoc.v:163333$8775 assign { } { } - assign $0\full_cr$5[31:0]$8792 0 + assign $0\full_cr$5[31:0]$8776 0 sync always sync init - update \full_cr$5 $0\full_cr$5[31:0]$8792 + update \full_cr$5 $0\full_cr$5[31:0]$8776 end - attribute \src "libresoc.v:162030.7-162030.24" - process $proc$libresoc.v:162030$8793 + attribute \src "libresoc.v:163338.7-163338.24" + process $proc$libresoc.v:163338$8777 assign { } { } assign $1\full_cr_ok[0:0] 1'0 sync always sync init update \full_cr_ok $1\full_cr_ok[0:0] end - attribute \src "libresoc.v:162259.13-162259.29" - process $proc$libresoc.v:162259$8794 + attribute \src "libresoc.v:163567.13-163567.29" + process $proc$libresoc.v:163567$8778 assign { } { } - assign $0\muxid$1[1:0]$8795 2'00 + assign $0\muxid$1[1:0]$8779 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$8795 + update \muxid$1 $0\muxid$1[1:0]$8779 end - attribute \src "libresoc.v:162272.14-162272.38" - process $proc$libresoc.v:162272$8796 + attribute \src "libresoc.v:163580.14-163580.38" + process $proc$libresoc.v:163580$8780 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:162279.7-162279.18" - process $proc$libresoc.v:162279$8797 + attribute \src "libresoc.v:163587.7-163587.18" + process $proc$libresoc.v:163587$8781 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:162293.7-162293.20" - process $proc$libresoc.v:162293$8798 + attribute \src "libresoc.v:163601.7-163601.20" + process $proc$libresoc.v:163601$8782 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:162301.3-162302.31" - process $proc$libresoc.v:162301$8732 + attribute \src "libresoc.v:163609.3-163610.31" + process $proc$libresoc.v:163609$8716 assign { } { } - assign $0\cr_a$6[3:0]$8733 \cr_a$6$next + assign $0\cr_a$6[3:0]$8717 \cr_a$6$next sync posedge \coresync_clk - update \cr_a$6 $0\cr_a$6[3:0]$8733 + update \cr_a$6 $0\cr_a$6[3:0]$8717 end - attribute \src "libresoc.v:162303.3-162304.31" - process $proc$libresoc.v:162303$8734 + attribute \src "libresoc.v:163611.3-163612.31" + process $proc$libresoc.v:163611$8718 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:162305.3-162306.37" - process $proc$libresoc.v:162305$8735 + attribute \src "libresoc.v:163613.3-163614.37" + process $proc$libresoc.v:163613$8719 assign { } { } - assign $0\full_cr$5[31:0]$8736 \full_cr$5$next + assign $0\full_cr$5[31:0]$8720 \full_cr$5$next sync posedge \coresync_clk - update \full_cr$5 $0\full_cr$5[31:0]$8736 + update \full_cr$5 $0\full_cr$5[31:0]$8720 end - attribute \src "libresoc.v:162307.3-162308.37" - process $proc$libresoc.v:162307$8737 + attribute \src "libresoc.v:163615.3-163616.37" + process $proc$libresoc.v:163615$8721 assign { } { } assign $0\full_cr_ok[0:0] \full_cr_ok$next sync posedge \coresync_clk update \full_cr_ok $0\full_cr_ok[0:0] end - attribute \src "libresoc.v:162309.3-162310.19" - process $proc$libresoc.v:162309$8738 + attribute \src "libresoc.v:163617.3-163618.19" + process $proc$libresoc.v:163617$8722 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:162311.3-162312.25" - process $proc$libresoc.v:162311$8739 + attribute \src "libresoc.v:163619.3-163620.25" + process $proc$libresoc.v:163619$8723 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:162313.3-162314.55" - process $proc$libresoc.v:162313$8740 + attribute \src "libresoc.v:163621.3-163622.55" + process $proc$libresoc.v:163621$8724 assign { } { } - assign $0\cr_op__insn_type$2[6:0]$8741 \cr_op__insn_type$2$next + assign $0\cr_op__insn_type$2[6:0]$8725 \cr_op__insn_type$2$next sync posedge \coresync_clk - update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8741 + update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$8725 end - attribute \src "libresoc.v:162315.3-162316.51" - process $proc$libresoc.v:162315$8742 + attribute \src "libresoc.v:163623.3-163624.51" + process $proc$libresoc.v:163623$8726 assign { } { } - assign $0\cr_op__fn_unit$3[13:0]$8743 \cr_op__fn_unit$3$next + assign $0\cr_op__fn_unit$3[13:0]$8727 \cr_op__fn_unit$3$next sync posedge \coresync_clk - update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[13:0]$8743 + update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[13:0]$8727 end - attribute \src "libresoc.v:162317.3-162318.45" - process $proc$libresoc.v:162317$8744 + attribute \src "libresoc.v:163625.3-163626.45" + process $proc$libresoc.v:163625$8728 assign { } { } - assign $0\cr_op__insn$4[31:0]$8745 \cr_op__insn$4$next + assign $0\cr_op__insn$4[31:0]$8729 \cr_op__insn$4$next sync posedge \coresync_clk - update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8745 + update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$8729 end - attribute \src "libresoc.v:162319.3-162320.33" - process $proc$libresoc.v:162319$8746 + attribute \src "libresoc.v:163627.3-163628.33" + process $proc$libresoc.v:163627$8730 assign { } { } - assign $0\muxid$1[1:0]$8747 \muxid$1$next + assign $0\muxid$1[1:0]$8731 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8747 + update \muxid$1 $0\muxid$1[1:0]$8731 end - attribute \src "libresoc.v:162321.3-162322.29" - process $proc$libresoc.v:162321$8748 + attribute \src "libresoc.v:163629.3-163630.29" + process $proc$libresoc.v:163629$8732 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:162353.3-162370.6" - process $proc$libresoc.v:162353$8749 + attribute \src "libresoc.v:163661.3-163678.6" + process $proc$libresoc.v:163661$8733 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$8750 $2\r_busy$next[0:0]$8752 - attribute \src "libresoc.v:162354.5-162354.29" + assign $0\r_busy$next[0:0]$8734 $2\r_busy$next[0:0]$8736 + attribute \src "libresoc.v:163662.5-163662.29" switch \initial - attribute \src "libresoc.v:162354.9-162354.17" + attribute \src "libresoc.v:163662.9-163662.17" case 1'1 case end @@ -333727,34 +305097,34 @@ module \pipe attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$8751 1'1 + assign $1\r_busy$next[0:0]$8735 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$8751 1'0 + assign $1\r_busy$next[0:0]$8735 1'0 case - assign $1\r_busy$next[0:0]$8751 \r_busy + assign $1\r_busy$next[0:0]$8735 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$8752 1'0 + assign $2\r_busy$next[0:0]$8736 1'0 case - assign $2\r_busy$next[0:0]$8752 $1\r_busy$next[0:0]$8751 + assign $2\r_busy$next[0:0]$8736 $1\r_busy$next[0:0]$8735 end sync always - update \r_busy$next $0\r_busy$next[0:0]$8750 + update \r_busy$next $0\r_busy$next[0:0]$8734 end - attribute \src "libresoc.v:162371.3-162383.6" - process $proc$libresoc.v:162371$8753 + attribute \src "libresoc.v:163679.3-163691.6" + process $proc$libresoc.v:163679$8737 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$8754 $1\muxid$1$next[1:0]$8755 - attribute \src "libresoc.v:162372.5-162372.29" + assign $0\muxid$1$next[1:0]$8738 $1\muxid$1$next[1:0]$8739 + attribute \src "libresoc.v:163680.5-163680.29" switch \initial - attribute \src "libresoc.v:162372.9-162372.17" + attribute \src "libresoc.v:163680.9-163680.17" case 1'1 case end @@ -333763,31 +305133,31 @@ module \pipe attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$8755 \muxid$16 + assign $1\muxid$1$next[1:0]$8739 \muxid$16 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$8755 \muxid$16 + assign $1\muxid$1$next[1:0]$8739 \muxid$16 case - assign $1\muxid$1$next[1:0]$8755 \muxid$1 + assign $1\muxid$1$next[1:0]$8739 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8754 + update \muxid$1$next $0\muxid$1$next[1:0]$8738 end - attribute \src "libresoc.v:162384.3-162398.6" - process $proc$libresoc.v:162384$8756 + attribute \src "libresoc.v:163692.3-163706.6" + process $proc$libresoc.v:163692$8740 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_op__fn_unit$3$next[13:0]$8757 $1\cr_op__fn_unit$3$next[13:0]$8760 - assign $0\cr_op__insn$4$next[31:0]$8758 $1\cr_op__insn$4$next[31:0]$8761 - assign $0\cr_op__insn_type$2$next[6:0]$8759 $1\cr_op__insn_type$2$next[6:0]$8762 - attribute \src "libresoc.v:162385.5-162385.29" + assign $0\cr_op__fn_unit$3$next[13:0]$8741 $1\cr_op__fn_unit$3$next[13:0]$8744 + assign $0\cr_op__insn$4$next[31:0]$8742 $1\cr_op__insn$4$next[31:0]$8745 + assign $0\cr_op__insn_type$2$next[6:0]$8743 $1\cr_op__insn_type$2$next[6:0]$8746 + attribute \src "libresoc.v:163693.5-163693.29" switch \initial - attribute \src "libresoc.v:162385.9-162385.17" + attribute \src "libresoc.v:163693.9-163693.17" case 1'1 case end @@ -333798,35 +305168,35 @@ module \pipe assign { } { } assign { } { } assign { } { } - assign { $1\cr_op__insn$4$next[31:0]$8761 $1\cr_op__fn_unit$3$next[13:0]$8760 $1\cr_op__insn_type$2$next[6:0]$8762 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } + assign { $1\cr_op__insn$4$next[31:0]$8745 $1\cr_op__fn_unit$3$next[13:0]$8744 $1\cr_op__insn_type$2$next[6:0]$8746 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { } { } - assign { $1\cr_op__insn$4$next[31:0]$8761 $1\cr_op__fn_unit$3$next[13:0]$8760 $1\cr_op__insn_type$2$next[6:0]$8762 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } + assign { $1\cr_op__insn$4$next[31:0]$8745 $1\cr_op__fn_unit$3$next[13:0]$8744 $1\cr_op__insn_type$2$next[6:0]$8746 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } case - assign $1\cr_op__fn_unit$3$next[13:0]$8760 \cr_op__fn_unit$3 - assign $1\cr_op__insn$4$next[31:0]$8761 \cr_op__insn$4 - assign $1\cr_op__insn_type$2$next[6:0]$8762 \cr_op__insn_type$2 + assign $1\cr_op__fn_unit$3$next[13:0]$8744 \cr_op__fn_unit$3 + assign $1\cr_op__insn$4$next[31:0]$8745 \cr_op__insn$4 + assign $1\cr_op__insn_type$2$next[6:0]$8746 \cr_op__insn_type$2 end sync always - update \cr_op__fn_unit$3$next $0\cr_op__fn_unit$3$next[13:0]$8757 - update \cr_op__insn$4$next $0\cr_op__insn$4$next[31:0]$8758 - update \cr_op__insn_type$2$next $0\cr_op__insn_type$2$next[6:0]$8759 + update \cr_op__fn_unit$3$next $0\cr_op__fn_unit$3$next[13:0]$8741 + update \cr_op__insn$4$next $0\cr_op__insn$4$next[31:0]$8742 + update \cr_op__insn_type$2$next $0\cr_op__insn_type$2$next[6:0]$8743 end - attribute \src "libresoc.v:162399.3-162417.6" - process $proc$libresoc.v:162399$8763 + attribute \src "libresoc.v:163707.3-163725.6" + process $proc$libresoc.v:163707$8747 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$8764 $1\o$next[63:0]$8766 + assign $0\o$next[63:0]$8748 $1\o$next[63:0]$8750 assign { } { } - assign $0\o_ok$next[0:0]$8765 $2\o_ok$next[0:0]$8768 - attribute \src "libresoc.v:162400.5-162400.29" + assign $0\o_ok$next[0:0]$8749 $2\o_ok$next[0:0]$8752 + attribute \src "libresoc.v:163708.5-163708.29" switch \initial - attribute \src "libresoc.v:162400.9-162400.17" + attribute \src "libresoc.v:163708.9-163708.17" case 1'1 case end @@ -333836,41 +305206,41 @@ module \pipe case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$8767 $1\o$next[63:0]$8766 } { \o_ok$21 \o$20 } + assign { $1\o_ok$next[0:0]$8751 $1\o$next[63:0]$8750 } { \o_ok$21 \o$20 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$8767 $1\o$next[63:0]$8766 } { \o_ok$21 \o$20 } + assign { $1\o_ok$next[0:0]$8751 $1\o$next[63:0]$8750 } { \o_ok$21 \o$20 } case - assign $1\o$next[63:0]$8766 \o - assign $1\o_ok$next[0:0]$8767 \o_ok + assign $1\o$next[63:0]$8750 \o + assign $1\o_ok$next[0:0]$8751 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$8768 1'0 + assign $2\o_ok$next[0:0]$8752 1'0 case - assign $2\o_ok$next[0:0]$8768 $1\o_ok$next[0:0]$8767 + assign $2\o_ok$next[0:0]$8752 $1\o_ok$next[0:0]$8751 end sync always - update \o$next $0\o$next[63:0]$8764 - update \o_ok$next $0\o_ok$next[0:0]$8765 + update \o$next $0\o$next[63:0]$8748 + update \o_ok$next $0\o_ok$next[0:0]$8749 end - attribute \src "libresoc.v:162418.3-162436.6" - process $proc$libresoc.v:162418$8769 + attribute \src "libresoc.v:163726.3-163744.6" + process $proc$libresoc.v:163726$8753 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\full_cr$5$next[31:0]$8770 $1\full_cr$5$next[31:0]$8772 + assign $0\full_cr$5$next[31:0]$8754 $1\full_cr$5$next[31:0]$8756 assign { } { } - assign $0\full_cr_ok$next[0:0]$8771 $2\full_cr_ok$next[0:0]$8774 - attribute \src "libresoc.v:162419.5-162419.29" + assign $0\full_cr_ok$next[0:0]$8755 $2\full_cr_ok$next[0:0]$8758 + attribute \src "libresoc.v:163727.5-163727.29" switch \initial - attribute \src "libresoc.v:162419.9-162419.17" + attribute \src "libresoc.v:163727.9-163727.17" case 1'1 case end @@ -333880,41 +305250,41 @@ module \pipe case 2'-1 assign { } { } assign { } { } - assign { $1\full_cr_ok$next[0:0]$8773 $1\full_cr$5$next[31:0]$8772 } { \full_cr_ok$23 \full_cr$22 } + assign { $1\full_cr_ok$next[0:0]$8757 $1\full_cr$5$next[31:0]$8756 } { \full_cr_ok$23 \full_cr$22 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\full_cr_ok$next[0:0]$8773 $1\full_cr$5$next[31:0]$8772 } { \full_cr_ok$23 \full_cr$22 } + assign { $1\full_cr_ok$next[0:0]$8757 $1\full_cr$5$next[31:0]$8756 } { \full_cr_ok$23 \full_cr$22 } case - assign $1\full_cr$5$next[31:0]$8772 \full_cr$5 - assign $1\full_cr_ok$next[0:0]$8773 \full_cr_ok + assign $1\full_cr$5$next[31:0]$8756 \full_cr$5 + assign $1\full_cr_ok$next[0:0]$8757 \full_cr_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\full_cr_ok$next[0:0]$8774 1'0 + assign $2\full_cr_ok$next[0:0]$8758 1'0 case - assign $2\full_cr_ok$next[0:0]$8774 $1\full_cr_ok$next[0:0]$8773 + assign $2\full_cr_ok$next[0:0]$8758 $1\full_cr_ok$next[0:0]$8757 end sync always - update \full_cr$5$next $0\full_cr$5$next[31:0]$8770 - update \full_cr_ok$next $0\full_cr_ok$next[0:0]$8771 + update \full_cr$5$next $0\full_cr$5$next[31:0]$8754 + update \full_cr_ok$next $0\full_cr_ok$next[0:0]$8755 end - attribute \src "libresoc.v:162437.3-162455.6" - process $proc$libresoc.v:162437$8775 + attribute \src "libresoc.v:163745.3-163763.6" + process $proc$libresoc.v:163745$8759 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$6$next[3:0]$8777 $1\cr_a$6$next[3:0]$8779 - assign $0\cr_a_ok$next[0:0]$8776 $2\cr_a_ok$next[0:0]$8780 - attribute \src "libresoc.v:162438.5-162438.29" + assign $0\cr_a$6$next[3:0]$8761 $1\cr_a$6$next[3:0]$8763 + assign $0\cr_a_ok$next[0:0]$8760 $2\cr_a_ok$next[0:0]$8764 + attribute \src "libresoc.v:163746.5-163746.29" switch \initial - attribute \src "libresoc.v:162438.9-162438.17" + attribute \src "libresoc.v:163746.9-163746.17" case 1'1 case end @@ -333924,30 +305294,30 @@ module \pipe case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$8778 $1\cr_a$6$next[3:0]$8779 } { \cr_a_ok$25 \cr_a$24 } + assign { $1\cr_a_ok$next[0:0]$8762 $1\cr_a$6$next[3:0]$8763 } { \cr_a_ok$25 \cr_a$24 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$8778 $1\cr_a$6$next[3:0]$8779 } { \cr_a_ok$25 \cr_a$24 } + assign { $1\cr_a_ok$next[0:0]$8762 $1\cr_a$6$next[3:0]$8763 } { \cr_a_ok$25 \cr_a$24 } case - assign $1\cr_a_ok$next[0:0]$8778 \cr_a_ok - assign $1\cr_a$6$next[3:0]$8779 \cr_a$6 + assign $1\cr_a_ok$next[0:0]$8762 \cr_a_ok + assign $1\cr_a$6$next[3:0]$8763 \cr_a$6 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$8780 1'0 + assign $2\cr_a_ok$next[0:0]$8764 1'0 case - assign $2\cr_a_ok$next[0:0]$8780 $1\cr_a_ok$next[0:0]$8778 + assign $2\cr_a_ok$next[0:0]$8764 $1\cr_a_ok$next[0:0]$8762 end sync always - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8776 - update \cr_a$6$next $0\cr_a$6$next[3:0]$8777 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8760 + update \cr_a$6$next $0\cr_a$6$next[3:0]$8761 end - connect \$14 $and$libresoc.v:162300$8731_Y + connect \$14 $and$libresoc.v:163608$8715_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \cr_a_ok$25 \cr_a$24 } { \main_cr_a_ok \main_cr_a$12 } @@ -333967,155 +305337,155 @@ module \pipe connect { \main_cr_op__insn \main_cr_op__fn_unit \main_cr_op__insn_type } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } connect \main_muxid \muxid end -attribute \src "libresoc.v:162478.1-163338.10" +attribute \src "libresoc.v:163786.1-164646.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.alu_branch0.pipe" attribute \generator "nMigen" module \pipe$19 - attribute \src "libresoc.v:163238.3-163265.6" - wire width 64 $0\br_op__cia$2$next[63:0]$8835 - attribute \src "libresoc.v:163150.3-163151.43" - wire width 64 $0\br_op__cia$2[63:0]$8809 - attribute \src "libresoc.v:162486.14-162486.51" - wire width 64 $0\br_op__cia$2[63:0]$8873 - attribute \src "libresoc.v:163238.3-163265.6" - wire width 14 $0\br_op__fn_unit$4$next[13:0]$8836 - attribute \src "libresoc.v:163154.3-163155.51" - wire width 14 $0\br_op__fn_unit$4[13:0]$8813 - attribute \src "libresoc.v:162542.14-162542.43" - wire width 14 $0\br_op__fn_unit$4[13:0]$8875 - attribute \src "libresoc.v:163238.3-163265.6" - wire width 64 $0\br_op__imm_data__data$6$next[63:0]$8837 - attribute \src "libresoc.v:163158.3-163159.65" - wire width 64 $0\br_op__imm_data__data$6[63:0]$8817 - attribute \src "libresoc.v:162551.14-162551.62" - wire width 64 $0\br_op__imm_data__data$6[63:0]$8877 - attribute \src "libresoc.v:163238.3-163265.6" - wire $0\br_op__imm_data__ok$7$next[0:0]$8838 - attribute \src "libresoc.v:163160.3-163161.61" - wire $0\br_op__imm_data__ok$7[0:0]$8819 - attribute \src "libresoc.v:162560.7-162560.37" - wire $0\br_op__imm_data__ok$7[0:0]$8879 - attribute \src "libresoc.v:163238.3-163265.6" - wire width 32 $0\br_op__insn$5$next[31:0]$8839 - attribute \src "libresoc.v:163156.3-163157.45" - wire width 32 $0\br_op__insn$5[31:0]$8815 - attribute \src "libresoc.v:162569.14-162569.37" - wire width 32 $0\br_op__insn$5[31:0]$8881 - attribute \src "libresoc.v:163238.3-163265.6" - wire width 7 $0\br_op__insn_type$3$next[6:0]$8840 - attribute \src "libresoc.v:163152.3-163153.55" - wire width 7 $0\br_op__insn_type$3[6:0]$8811 - attribute \src "libresoc.v:162803.13-162803.41" - wire width 7 $0\br_op__insn_type$3[6:0]$8883 - attribute \src "libresoc.v:163238.3-163265.6" - wire $0\br_op__is_32bit$9$next[0:0]$8841 - attribute \src "libresoc.v:163164.3-163165.53" - wire $0\br_op__is_32bit$9[0:0]$8823 - attribute \src "libresoc.v:162812.7-162812.33" - wire $0\br_op__is_32bit$9[0:0]$8885 - attribute \src "libresoc.v:163238.3-163265.6" - wire $0\br_op__lk$8$next[0:0]$8842 - attribute \src "libresoc.v:163162.3-163163.41" - wire $0\br_op__lk$8[0:0]$8821 - attribute \src "libresoc.v:162821.7-162821.27" - wire $0\br_op__lk$8[0:0]$8887 - attribute \src "libresoc.v:163266.3-163284.6" - wire width 64 $0\fast1$10$next[63:0]$8854 - attribute \src "libresoc.v:163146.3-163147.35" - wire width 64 $0\fast1$10[63:0]$8806 - attribute \src "libresoc.v:162834.14-162834.47" - wire width 64 $0\fast1$10[63:0]$8889 - attribute \src "libresoc.v:163266.3-163284.6" - wire $0\fast1_ok$next[0:0]$8855 - attribute \src "libresoc.v:163148.3-163149.33" + attribute \src "libresoc.v:164546.3-164573.6" + wire width 64 $0\br_op__cia$2$next[63:0]$8819 + attribute \src "libresoc.v:164458.3-164459.43" + wire width 64 $0\br_op__cia$2[63:0]$8793 + attribute \src "libresoc.v:163794.14-163794.51" + wire width 64 $0\br_op__cia$2[63:0]$8857 + attribute \src "libresoc.v:164546.3-164573.6" + wire width 14 $0\br_op__fn_unit$4$next[13:0]$8820 + attribute \src "libresoc.v:164462.3-164463.51" + wire width 14 $0\br_op__fn_unit$4[13:0]$8797 + attribute \src "libresoc.v:163850.14-163850.43" + wire width 14 $0\br_op__fn_unit$4[13:0]$8859 + attribute \src "libresoc.v:164546.3-164573.6" + wire width 64 $0\br_op__imm_data__data$6$next[63:0]$8821 + attribute \src "libresoc.v:164466.3-164467.65" + wire width 64 $0\br_op__imm_data__data$6[63:0]$8801 + attribute \src "libresoc.v:163859.14-163859.62" + wire width 64 $0\br_op__imm_data__data$6[63:0]$8861 + attribute \src "libresoc.v:164546.3-164573.6" + wire $0\br_op__imm_data__ok$7$next[0:0]$8822 + attribute \src "libresoc.v:164468.3-164469.61" + wire $0\br_op__imm_data__ok$7[0:0]$8803 + attribute \src "libresoc.v:163868.7-163868.37" + wire $0\br_op__imm_data__ok$7[0:0]$8863 + attribute \src "libresoc.v:164546.3-164573.6" + wire width 32 $0\br_op__insn$5$next[31:0]$8823 + attribute \src "libresoc.v:164464.3-164465.45" + wire width 32 $0\br_op__insn$5[31:0]$8799 + attribute \src "libresoc.v:163877.14-163877.37" + wire width 32 $0\br_op__insn$5[31:0]$8865 + attribute \src "libresoc.v:164546.3-164573.6" + wire width 7 $0\br_op__insn_type$3$next[6:0]$8824 + attribute \src "libresoc.v:164460.3-164461.55" + wire width 7 $0\br_op__insn_type$3[6:0]$8795 + attribute \src "libresoc.v:164111.13-164111.41" + wire width 7 $0\br_op__insn_type$3[6:0]$8867 + attribute \src "libresoc.v:164546.3-164573.6" + wire $0\br_op__is_32bit$9$next[0:0]$8825 + attribute \src "libresoc.v:164472.3-164473.53" + wire $0\br_op__is_32bit$9[0:0]$8807 + attribute \src "libresoc.v:164120.7-164120.33" + wire $0\br_op__is_32bit$9[0:0]$8869 + attribute \src "libresoc.v:164546.3-164573.6" + wire $0\br_op__lk$8$next[0:0]$8826 + attribute \src "libresoc.v:164470.3-164471.41" + wire $0\br_op__lk$8[0:0]$8805 + attribute \src "libresoc.v:164129.7-164129.27" + wire $0\br_op__lk$8[0:0]$8871 + attribute \src "libresoc.v:164574.3-164592.6" + wire width 64 $0\fast1$10$next[63:0]$8838 + attribute \src "libresoc.v:164454.3-164455.35" + wire width 64 $0\fast1$10[63:0]$8790 + attribute \src "libresoc.v:164142.14-164142.47" + wire width 64 $0\fast1$10[63:0]$8873 + attribute \src "libresoc.v:164574.3-164592.6" + wire $0\fast1_ok$next[0:0]$8839 + attribute \src "libresoc.v:164456.3-164457.33" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:163285.3-163303.6" - wire width 64 $0\fast2$11$next[63:0]$8860 - attribute \src "libresoc.v:163142.3-163143.35" - wire width 64 $0\fast2$11[63:0]$8803 - attribute \src "libresoc.v:162850.14-162850.47" - wire width 64 $0\fast2$11[63:0]$8892 - attribute \src "libresoc.v:163285.3-163303.6" - wire $0\fast2_ok$next[0:0]$8861 - attribute \src "libresoc.v:163144.3-163145.33" + attribute \src "libresoc.v:164593.3-164611.6" + wire width 64 $0\fast2$11$next[63:0]$8844 + attribute \src "libresoc.v:164450.3-164451.35" + wire width 64 $0\fast2$11[63:0]$8787 + attribute \src "libresoc.v:164158.14-164158.47" + wire width 64 $0\fast2$11[63:0]$8876 + attribute \src "libresoc.v:164593.3-164611.6" + wire $0\fast2_ok$next[0:0]$8845 + attribute \src "libresoc.v:164452.3-164453.33" wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:162479.7-162479.20" + attribute \src "libresoc.v:163787.7-163787.20" wire $0\initial[0:0] - attribute \src "libresoc.v:163225.3-163237.6" - wire width 2 $0\muxid$1$next[1:0]$8832 - attribute \src "libresoc.v:163166.3-163167.33" - wire width 2 $0\muxid$1[1:0]$8825 - attribute \src "libresoc.v:163100.13-163100.29" - wire width 2 $0\muxid$1[1:0]$8895 - attribute \src "libresoc.v:163304.3-163322.6" - wire width 64 $0\nia$next[63:0]$8866 - attribute \src "libresoc.v:163138.3-163139.23" + attribute \src "libresoc.v:164533.3-164545.6" + wire width 2 $0\muxid$1$next[1:0]$8816 + attribute \src "libresoc.v:164474.3-164475.33" + wire width 2 $0\muxid$1[1:0]$8809 + attribute \src "libresoc.v:164408.13-164408.29" + wire width 2 $0\muxid$1[1:0]$8879 + attribute \src "libresoc.v:164612.3-164630.6" + wire width 64 $0\nia$next[63:0]$8850 + attribute \src "libresoc.v:164446.3-164447.23" wire width 64 $0\nia[63:0] - attribute \src "libresoc.v:163304.3-163322.6" - wire $0\nia_ok$next[0:0]$8867 - attribute \src "libresoc.v:163140.3-163141.29" + attribute \src "libresoc.v:164612.3-164630.6" + wire $0\nia_ok$next[0:0]$8851 + attribute \src "libresoc.v:164448.3-164449.29" wire $0\nia_ok[0:0] - attribute \src "libresoc.v:163207.3-163224.6" - wire $0\r_busy$next[0:0]$8828 - attribute \src "libresoc.v:163168.3-163169.29" + attribute \src "libresoc.v:164515.3-164532.6" + wire $0\r_busy$next[0:0]$8812 + attribute \src "libresoc.v:164476.3-164477.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:163238.3-163265.6" - wire width 64 $1\br_op__cia$2$next[63:0]$8843 - attribute \src "libresoc.v:163238.3-163265.6" - wire width 14 $1\br_op__fn_unit$4$next[13:0]$8844 - attribute \src "libresoc.v:163238.3-163265.6" - wire width 64 $1\br_op__imm_data__data$6$next[63:0]$8845 - attribute \src "libresoc.v:163238.3-163265.6" - wire $1\br_op__imm_data__ok$7$next[0:0]$8846 - attribute \src "libresoc.v:163238.3-163265.6" - wire width 32 $1\br_op__insn$5$next[31:0]$8847 - attribute \src "libresoc.v:163238.3-163265.6" - wire width 7 $1\br_op__insn_type$3$next[6:0]$8848 - attribute \src "libresoc.v:163238.3-163265.6" - wire $1\br_op__is_32bit$9$next[0:0]$8849 - attribute \src "libresoc.v:163238.3-163265.6" - wire $1\br_op__lk$8$next[0:0]$8850 - attribute \src "libresoc.v:163266.3-163284.6" - wire width 64 $1\fast1$10$next[63:0]$8856 - attribute \src "libresoc.v:163266.3-163284.6" - wire $1\fast1_ok$next[0:0]$8857 - attribute \src "libresoc.v:162841.7-162841.22" + attribute \src "libresoc.v:164546.3-164573.6" + wire width 64 $1\br_op__cia$2$next[63:0]$8827 + attribute \src "libresoc.v:164546.3-164573.6" + wire width 14 $1\br_op__fn_unit$4$next[13:0]$8828 + attribute \src "libresoc.v:164546.3-164573.6" + wire width 64 $1\br_op__imm_data__data$6$next[63:0]$8829 + attribute \src "libresoc.v:164546.3-164573.6" + wire $1\br_op__imm_data__ok$7$next[0:0]$8830 + attribute \src "libresoc.v:164546.3-164573.6" + wire width 32 $1\br_op__insn$5$next[31:0]$8831 + attribute \src "libresoc.v:164546.3-164573.6" + wire width 7 $1\br_op__insn_type$3$next[6:0]$8832 + attribute \src "libresoc.v:164546.3-164573.6" + wire $1\br_op__is_32bit$9$next[0:0]$8833 + attribute \src "libresoc.v:164546.3-164573.6" + wire $1\br_op__lk$8$next[0:0]$8834 + attribute \src "libresoc.v:164574.3-164592.6" + wire width 64 $1\fast1$10$next[63:0]$8840 + attribute \src "libresoc.v:164574.3-164592.6" + wire $1\fast1_ok$next[0:0]$8841 + attribute \src "libresoc.v:164149.7-164149.22" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:163285.3-163303.6" - wire width 64 $1\fast2$11$next[63:0]$8862 - attribute \src "libresoc.v:163285.3-163303.6" - wire $1\fast2_ok$next[0:0]$8863 - attribute \src "libresoc.v:162857.7-162857.22" + attribute \src "libresoc.v:164593.3-164611.6" + wire width 64 $1\fast2$11$next[63:0]$8846 + attribute \src "libresoc.v:164593.3-164611.6" + wire $1\fast2_ok$next[0:0]$8847 + attribute \src "libresoc.v:164165.7-164165.22" wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:163225.3-163237.6" - wire width 2 $1\muxid$1$next[1:0]$8833 - attribute \src "libresoc.v:163304.3-163322.6" - wire width 64 $1\nia$next[63:0]$8868 - attribute \src "libresoc.v:163113.14-163113.40" + attribute \src "libresoc.v:164533.3-164545.6" + wire width 2 $1\muxid$1$next[1:0]$8817 + attribute \src "libresoc.v:164612.3-164630.6" + wire width 64 $1\nia$next[63:0]$8852 + attribute \src "libresoc.v:164421.14-164421.40" wire width 64 $1\nia[63:0] - attribute \src "libresoc.v:163304.3-163322.6" - wire $1\nia_ok$next[0:0]$8869 - attribute \src "libresoc.v:163120.7-163120.20" + attribute \src "libresoc.v:164612.3-164630.6" + wire $1\nia_ok$next[0:0]$8853 + attribute \src "libresoc.v:164428.7-164428.20" wire $1\nia_ok[0:0] - attribute \src "libresoc.v:163207.3-163224.6" - wire $1\r_busy$next[0:0]$8829 - attribute \src "libresoc.v:163134.7-163134.20" + attribute \src "libresoc.v:164515.3-164532.6" + wire $1\r_busy$next[0:0]$8813 + attribute \src "libresoc.v:164442.7-164442.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:163238.3-163265.6" - wire width 64 $2\br_op__imm_data__data$6$next[63:0]$8851 - attribute \src "libresoc.v:163238.3-163265.6" - wire $2\br_op__imm_data__ok$7$next[0:0]$8852 - attribute \src "libresoc.v:163266.3-163284.6" - wire $2\fast1_ok$next[0:0]$8858 - attribute \src "libresoc.v:163285.3-163303.6" - wire $2\fast2_ok$next[0:0]$8864 - attribute \src "libresoc.v:163304.3-163322.6" - wire $2\nia_ok$next[0:0]$8870 - attribute \src "libresoc.v:163207.3-163224.6" - wire $2\r_busy$next[0:0]$8830 - attribute \src "libresoc.v:163137.18-163137.118" - wire $and$libresoc.v:163137$8799_Y + attribute \src "libresoc.v:164546.3-164573.6" + wire width 64 $2\br_op__imm_data__data$6$next[63:0]$8835 + attribute \src "libresoc.v:164546.3-164573.6" + wire $2\br_op__imm_data__ok$7$next[0:0]$8836 + attribute \src "libresoc.v:164574.3-164592.6" + wire $2\fast1_ok$next[0:0]$8842 + attribute \src "libresoc.v:164593.3-164611.6" + wire $2\fast2_ok$next[0:0]$8848 + attribute \src "libresoc.v:164612.3-164630.6" + wire $2\nia_ok$next[0:0]$8854 + attribute \src "libresoc.v:164515.3-164532.6" + wire $2\r_busy$next[0:0]$8814 + attribute \src "libresoc.v:164445.18-164445.118" + wire $and$libresoc.v:164445$8783_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$24 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -334452,9 +305822,9 @@ module \pipe$19 wire output 25 \br_op__lk$8 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \br_op__lk$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 33 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 4 input 15 \cr_a @@ -334486,7 +305856,7 @@ module \pipe$19 wire \fast2_ok$38 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fast2_ok$next - attribute \src "libresoc.v:162479.7-162479.15" + attribute \src "libresoc.v:163787.7-163787.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 64 \main_br_op__cia @@ -334761,7 +306131,7 @@ module \pipe$19 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" wire \r_busy$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:163137$8799 + cell $and $and$libresoc.v:164445$8783 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -334769,10 +306139,10 @@ module \pipe$19 parameter \Y_WIDTH 1 connect \A \p_valid_i$23 connect \B \p_ready_o - connect \Y $and$libresoc.v:163137$8799_Y + connect \Y $and$libresoc.v:164445$8783_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:163170.13-163198.4" + attribute \src "libresoc.v:164478.13-164506.4" cell \main$22 \main connect \br_op__cia \main_br_op__cia connect \br_op__cia$2 \main_br_op__cia$13 @@ -334803,274 +306173,274 @@ module \pipe$19 connect \nia_ok \main_nia_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:163199.10-163202.4" + attribute \src "libresoc.v:164507.10-164510.4" cell \n$21 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:163203.10-163206.4" + attribute \src "libresoc.v:164511.10-164514.4" cell \p$20 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:162479.7-162479.20" - process $proc$libresoc.v:162479$8871 + attribute \src "libresoc.v:163787.7-163787.20" + process $proc$libresoc.v:163787$8855 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:162486.14-162486.51" - process $proc$libresoc.v:162486$8872 + attribute \src "libresoc.v:163794.14-163794.51" + process $proc$libresoc.v:163794$8856 assign { } { } - assign $0\br_op__cia$2[63:0]$8873 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\br_op__cia$2[63:0]$8857 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \br_op__cia$2 $0\br_op__cia$2[63:0]$8873 + update \br_op__cia$2 $0\br_op__cia$2[63:0]$8857 end - attribute \src "libresoc.v:162542.14-162542.43" - process $proc$libresoc.v:162542$8874 + attribute \src "libresoc.v:163850.14-163850.43" + process $proc$libresoc.v:163850$8858 assign { } { } - assign $0\br_op__fn_unit$4[13:0]$8875 14'00000000000000 + assign $0\br_op__fn_unit$4[13:0]$8859 14'00000000000000 sync always sync init - update \br_op__fn_unit$4 $0\br_op__fn_unit$4[13:0]$8875 + update \br_op__fn_unit$4 $0\br_op__fn_unit$4[13:0]$8859 end - attribute \src "libresoc.v:162551.14-162551.62" - process $proc$libresoc.v:162551$8876 + attribute \src "libresoc.v:163859.14-163859.62" + process $proc$libresoc.v:163859$8860 assign { } { } - assign $0\br_op__imm_data__data$6[63:0]$8877 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\br_op__imm_data__data$6[63:0]$8861 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8877 + update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8861 end - attribute \src "libresoc.v:162560.7-162560.37" - process $proc$libresoc.v:162560$8878 + attribute \src "libresoc.v:163868.7-163868.37" + process $proc$libresoc.v:163868$8862 assign { } { } - assign $0\br_op__imm_data__ok$7[0:0]$8879 1'0 + assign $0\br_op__imm_data__ok$7[0:0]$8863 1'0 sync always sync init - update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8879 + update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8863 end - attribute \src "libresoc.v:162569.14-162569.37" - process $proc$libresoc.v:162569$8880 + attribute \src "libresoc.v:163877.14-163877.37" + process $proc$libresoc.v:163877$8864 assign { } { } - assign $0\br_op__insn$5[31:0]$8881 0 + assign $0\br_op__insn$5[31:0]$8865 0 sync always sync init - update \br_op__insn$5 $0\br_op__insn$5[31:0]$8881 + update \br_op__insn$5 $0\br_op__insn$5[31:0]$8865 end - attribute \src "libresoc.v:162803.13-162803.41" - process $proc$libresoc.v:162803$8882 + attribute \src "libresoc.v:164111.13-164111.41" + process $proc$libresoc.v:164111$8866 assign { } { } - assign $0\br_op__insn_type$3[6:0]$8883 7'0000000 + assign $0\br_op__insn_type$3[6:0]$8867 7'0000000 sync always sync init - update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8883 + update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8867 end - attribute \src "libresoc.v:162812.7-162812.33" - process $proc$libresoc.v:162812$8884 + attribute \src "libresoc.v:164120.7-164120.33" + process $proc$libresoc.v:164120$8868 assign { } { } - assign $0\br_op__is_32bit$9[0:0]$8885 1'0 + assign $0\br_op__is_32bit$9[0:0]$8869 1'0 sync always sync init - update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8885 + update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8869 end - attribute \src "libresoc.v:162821.7-162821.27" - process $proc$libresoc.v:162821$8886 + attribute \src "libresoc.v:164129.7-164129.27" + process $proc$libresoc.v:164129$8870 assign { } { } - assign $0\br_op__lk$8[0:0]$8887 1'0 + assign $0\br_op__lk$8[0:0]$8871 1'0 sync always sync init - update \br_op__lk$8 $0\br_op__lk$8[0:0]$8887 + update \br_op__lk$8 $0\br_op__lk$8[0:0]$8871 end - attribute \src "libresoc.v:162834.14-162834.47" - process $proc$libresoc.v:162834$8888 + attribute \src "libresoc.v:164142.14-164142.47" + process $proc$libresoc.v:164142$8872 assign { } { } - assign $0\fast1$10[63:0]$8889 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\fast1$10[63:0]$8873 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \fast1$10 $0\fast1$10[63:0]$8889 + update \fast1$10 $0\fast1$10[63:0]$8873 end - attribute \src "libresoc.v:162841.7-162841.22" - process $proc$libresoc.v:162841$8890 + attribute \src "libresoc.v:164149.7-164149.22" + process $proc$libresoc.v:164149$8874 assign { } { } assign $1\fast1_ok[0:0] 1'0 sync always sync init update \fast1_ok $1\fast1_ok[0:0] end - attribute \src "libresoc.v:162850.14-162850.47" - process $proc$libresoc.v:162850$8891 + attribute \src "libresoc.v:164158.14-164158.47" + process $proc$libresoc.v:164158$8875 assign { } { } - assign $0\fast2$11[63:0]$8892 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\fast2$11[63:0]$8876 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \fast2$11 $0\fast2$11[63:0]$8892 + update \fast2$11 $0\fast2$11[63:0]$8876 end - attribute \src "libresoc.v:162857.7-162857.22" - process $proc$libresoc.v:162857$8893 + attribute \src "libresoc.v:164165.7-164165.22" + process $proc$libresoc.v:164165$8877 assign { } { } assign $1\fast2_ok[0:0] 1'0 sync always sync init update \fast2_ok $1\fast2_ok[0:0] end - attribute \src "libresoc.v:163100.13-163100.29" - process $proc$libresoc.v:163100$8894 + attribute \src "libresoc.v:164408.13-164408.29" + process $proc$libresoc.v:164408$8878 assign { } { } - assign $0\muxid$1[1:0]$8895 2'00 + assign $0\muxid$1[1:0]$8879 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$8895 + update \muxid$1 $0\muxid$1[1:0]$8879 end - attribute \src "libresoc.v:163113.14-163113.40" - process $proc$libresoc.v:163113$8896 + attribute \src "libresoc.v:164421.14-164421.40" + process $proc$libresoc.v:164421$8880 assign { } { } assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \nia $1\nia[63:0] end - attribute \src "libresoc.v:163120.7-163120.20" - process $proc$libresoc.v:163120$8897 + attribute \src "libresoc.v:164428.7-164428.20" + process $proc$libresoc.v:164428$8881 assign { } { } assign $1\nia_ok[0:0] 1'0 sync always sync init update \nia_ok $1\nia_ok[0:0] end - attribute \src "libresoc.v:163134.7-163134.20" - process $proc$libresoc.v:163134$8898 + attribute \src "libresoc.v:164442.7-164442.20" + process $proc$libresoc.v:164442$8882 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:163138.3-163139.23" - process $proc$libresoc.v:163138$8800 + attribute \src "libresoc.v:164446.3-164447.23" + process $proc$libresoc.v:164446$8784 assign { } { } assign $0\nia[63:0] \nia$next sync posedge \coresync_clk update \nia $0\nia[63:0] end - attribute \src "libresoc.v:163140.3-163141.29" - process $proc$libresoc.v:163140$8801 + attribute \src "libresoc.v:164448.3-164449.29" + process $proc$libresoc.v:164448$8785 assign { } { } assign $0\nia_ok[0:0] \nia_ok$next sync posedge \coresync_clk update \nia_ok $0\nia_ok[0:0] end - attribute \src "libresoc.v:163142.3-163143.35" - process $proc$libresoc.v:163142$8802 + attribute \src "libresoc.v:164450.3-164451.35" + process $proc$libresoc.v:164450$8786 assign { } { } - assign $0\fast2$11[63:0]$8803 \fast2$11$next + assign $0\fast2$11[63:0]$8787 \fast2$11$next sync posedge \coresync_clk - update \fast2$11 $0\fast2$11[63:0]$8803 + update \fast2$11 $0\fast2$11[63:0]$8787 end - attribute \src "libresoc.v:163144.3-163145.33" - process $proc$libresoc.v:163144$8804 + attribute \src "libresoc.v:164452.3-164453.33" + process $proc$libresoc.v:164452$8788 assign { } { } assign $0\fast2_ok[0:0] \fast2_ok$next sync posedge \coresync_clk update \fast2_ok $0\fast2_ok[0:0] end - attribute \src "libresoc.v:163146.3-163147.35" - process $proc$libresoc.v:163146$8805 + attribute \src "libresoc.v:164454.3-164455.35" + process $proc$libresoc.v:164454$8789 assign { } { } - assign $0\fast1$10[63:0]$8806 \fast1$10$next + assign $0\fast1$10[63:0]$8790 \fast1$10$next sync posedge \coresync_clk - update \fast1$10 $0\fast1$10[63:0]$8806 + update \fast1$10 $0\fast1$10[63:0]$8790 end - attribute \src "libresoc.v:163148.3-163149.33" - process $proc$libresoc.v:163148$8807 + attribute \src "libresoc.v:164456.3-164457.33" + process $proc$libresoc.v:164456$8791 assign { } { } assign $0\fast1_ok[0:0] \fast1_ok$next sync posedge \coresync_clk update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:163150.3-163151.43" - process $proc$libresoc.v:163150$8808 + attribute \src "libresoc.v:164458.3-164459.43" + process $proc$libresoc.v:164458$8792 assign { } { } - assign $0\br_op__cia$2[63:0]$8809 \br_op__cia$2$next + assign $0\br_op__cia$2[63:0]$8793 \br_op__cia$2$next sync posedge \coresync_clk - update \br_op__cia$2 $0\br_op__cia$2[63:0]$8809 + update \br_op__cia$2 $0\br_op__cia$2[63:0]$8793 end - attribute \src "libresoc.v:163152.3-163153.55" - process $proc$libresoc.v:163152$8810 + attribute \src "libresoc.v:164460.3-164461.55" + process $proc$libresoc.v:164460$8794 assign { } { } - assign $0\br_op__insn_type$3[6:0]$8811 \br_op__insn_type$3$next + assign $0\br_op__insn_type$3[6:0]$8795 \br_op__insn_type$3$next sync posedge \coresync_clk - update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8811 + update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$8795 end - attribute \src "libresoc.v:163154.3-163155.51" - process $proc$libresoc.v:163154$8812 + attribute \src "libresoc.v:164462.3-164463.51" + process $proc$libresoc.v:164462$8796 assign { } { } - assign $0\br_op__fn_unit$4[13:0]$8813 \br_op__fn_unit$4$next + assign $0\br_op__fn_unit$4[13:0]$8797 \br_op__fn_unit$4$next sync posedge \coresync_clk - update \br_op__fn_unit$4 $0\br_op__fn_unit$4[13:0]$8813 + update \br_op__fn_unit$4 $0\br_op__fn_unit$4[13:0]$8797 end - attribute \src "libresoc.v:163156.3-163157.45" - process $proc$libresoc.v:163156$8814 + attribute \src "libresoc.v:164464.3-164465.45" + process $proc$libresoc.v:164464$8798 assign { } { } - assign $0\br_op__insn$5[31:0]$8815 \br_op__insn$5$next + assign $0\br_op__insn$5[31:0]$8799 \br_op__insn$5$next sync posedge \coresync_clk - update \br_op__insn$5 $0\br_op__insn$5[31:0]$8815 + update \br_op__insn$5 $0\br_op__insn$5[31:0]$8799 end - attribute \src "libresoc.v:163158.3-163159.65" - process $proc$libresoc.v:163158$8816 + attribute \src "libresoc.v:164466.3-164467.65" + process $proc$libresoc.v:164466$8800 assign { } { } - assign $0\br_op__imm_data__data$6[63:0]$8817 \br_op__imm_data__data$6$next + assign $0\br_op__imm_data__data$6[63:0]$8801 \br_op__imm_data__data$6$next sync posedge \coresync_clk - update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8817 + update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$8801 end - attribute \src "libresoc.v:163160.3-163161.61" - process $proc$libresoc.v:163160$8818 + attribute \src "libresoc.v:164468.3-164469.61" + process $proc$libresoc.v:164468$8802 assign { } { } - assign $0\br_op__imm_data__ok$7[0:0]$8819 \br_op__imm_data__ok$7$next + assign $0\br_op__imm_data__ok$7[0:0]$8803 \br_op__imm_data__ok$7$next sync posedge \coresync_clk - update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8819 + update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$8803 end - attribute \src "libresoc.v:163162.3-163163.41" - process $proc$libresoc.v:163162$8820 + attribute \src "libresoc.v:164470.3-164471.41" + process $proc$libresoc.v:164470$8804 assign { } { } - assign $0\br_op__lk$8[0:0]$8821 \br_op__lk$8$next + assign $0\br_op__lk$8[0:0]$8805 \br_op__lk$8$next sync posedge \coresync_clk - update \br_op__lk$8 $0\br_op__lk$8[0:0]$8821 + update \br_op__lk$8 $0\br_op__lk$8[0:0]$8805 end - attribute \src "libresoc.v:163164.3-163165.53" - process $proc$libresoc.v:163164$8822 + attribute \src "libresoc.v:164472.3-164473.53" + process $proc$libresoc.v:164472$8806 assign { } { } - assign $0\br_op__is_32bit$9[0:0]$8823 \br_op__is_32bit$9$next + assign $0\br_op__is_32bit$9[0:0]$8807 \br_op__is_32bit$9$next sync posedge \coresync_clk - update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8823 + update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$8807 end - attribute \src "libresoc.v:163166.3-163167.33" - process $proc$libresoc.v:163166$8824 + attribute \src "libresoc.v:164474.3-164475.33" + process $proc$libresoc.v:164474$8808 assign { } { } - assign $0\muxid$1[1:0]$8825 \muxid$1$next + assign $0\muxid$1[1:0]$8809 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8825 + update \muxid$1 $0\muxid$1[1:0]$8809 end - attribute \src "libresoc.v:163168.3-163169.29" - process $proc$libresoc.v:163168$8826 + attribute \src "libresoc.v:164476.3-164477.29" + process $proc$libresoc.v:164476$8810 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:163207.3-163224.6" - process $proc$libresoc.v:163207$8827 + attribute \src "libresoc.v:164515.3-164532.6" + process $proc$libresoc.v:164515$8811 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$8828 $2\r_busy$next[0:0]$8830 - attribute \src "libresoc.v:163208.5-163208.29" + assign $0\r_busy$next[0:0]$8812 $2\r_busy$next[0:0]$8814 + attribute \src "libresoc.v:164516.5-164516.29" switch \initial - attribute \src "libresoc.v:163208.9-163208.17" + attribute \src "libresoc.v:164516.9-164516.17" case 1'1 case end @@ -335079,34 +306449,34 @@ module \pipe$19 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$8829 1'1 + assign $1\r_busy$next[0:0]$8813 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$8829 1'0 + assign $1\r_busy$next[0:0]$8813 1'0 case - assign $1\r_busy$next[0:0]$8829 \r_busy + assign $1\r_busy$next[0:0]$8813 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$8830 1'0 + assign $2\r_busy$next[0:0]$8814 1'0 case - assign $2\r_busy$next[0:0]$8830 $1\r_busy$next[0:0]$8829 + assign $2\r_busy$next[0:0]$8814 $1\r_busy$next[0:0]$8813 end sync always - update \r_busy$next $0\r_busy$next[0:0]$8828 + update \r_busy$next $0\r_busy$next[0:0]$8812 end - attribute \src "libresoc.v:163225.3-163237.6" - process $proc$libresoc.v:163225$8831 + attribute \src "libresoc.v:164533.3-164545.6" + process $proc$libresoc.v:164533$8815 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$8832 $1\muxid$1$next[1:0]$8833 - attribute \src "libresoc.v:163226.5-163226.29" + assign $0\muxid$1$next[1:0]$8816 $1\muxid$1$next[1:0]$8817 + attribute \src "libresoc.v:164534.5-164534.29" switch \initial - attribute \src "libresoc.v:163226.9-163226.17" + attribute \src "libresoc.v:164534.9-164534.17" case 1'1 case end @@ -335115,19 +306485,19 @@ module \pipe$19 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$8833 \muxid$26 + assign $1\muxid$1$next[1:0]$8817 \muxid$26 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$8833 \muxid$26 + assign $1\muxid$1$next[1:0]$8817 \muxid$26 case - assign $1\muxid$1$next[1:0]$8833 \muxid$1 + assign $1\muxid$1$next[1:0]$8817 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8832 + update \muxid$1$next $0\muxid$1$next[1:0]$8816 end - attribute \src "libresoc.v:163238.3-163265.6" - process $proc$libresoc.v:163238$8834 + attribute \src "libresoc.v:164546.3-164573.6" + process $proc$libresoc.v:164546$8818 assign { } { } assign { } { } assign { } { } @@ -335144,19 +306514,19 @@ module \pipe$19 assign { } { } assign { } { } assign { } { } - assign $0\br_op__cia$2$next[63:0]$8835 $1\br_op__cia$2$next[63:0]$8843 - assign $0\br_op__fn_unit$4$next[13:0]$8836 $1\br_op__fn_unit$4$next[13:0]$8844 + assign $0\br_op__cia$2$next[63:0]$8819 $1\br_op__cia$2$next[63:0]$8827 + assign $0\br_op__fn_unit$4$next[13:0]$8820 $1\br_op__fn_unit$4$next[13:0]$8828 assign { } { } assign { } { } - assign $0\br_op__insn$5$next[31:0]$8839 $1\br_op__insn$5$next[31:0]$8847 - assign $0\br_op__insn_type$3$next[6:0]$8840 $1\br_op__insn_type$3$next[6:0]$8848 - assign $0\br_op__is_32bit$9$next[0:0]$8841 $1\br_op__is_32bit$9$next[0:0]$8849 - assign $0\br_op__lk$8$next[0:0]$8842 $1\br_op__lk$8$next[0:0]$8850 - assign $0\br_op__imm_data__data$6$next[63:0]$8837 $2\br_op__imm_data__data$6$next[63:0]$8851 - assign $0\br_op__imm_data__ok$7$next[0:0]$8838 $2\br_op__imm_data__ok$7$next[0:0]$8852 - attribute \src "libresoc.v:163239.5-163239.29" + assign $0\br_op__insn$5$next[31:0]$8823 $1\br_op__insn$5$next[31:0]$8831 + assign $0\br_op__insn_type$3$next[6:0]$8824 $1\br_op__insn_type$3$next[6:0]$8832 + assign $0\br_op__is_32bit$9$next[0:0]$8825 $1\br_op__is_32bit$9$next[0:0]$8833 + assign $0\br_op__lk$8$next[0:0]$8826 $1\br_op__lk$8$next[0:0]$8834 + assign $0\br_op__imm_data__data$6$next[63:0]$8821 $2\br_op__imm_data__data$6$next[63:0]$8835 + assign $0\br_op__imm_data__ok$7$next[0:0]$8822 $2\br_op__imm_data__ok$7$next[0:0]$8836 + attribute \src "libresoc.v:164547.5-164547.29" switch \initial - attribute \src "libresoc.v:163239.9-163239.17" + attribute \src "libresoc.v:164547.9-164547.17" case 1'1 case end @@ -335172,7 +306542,7 @@ module \pipe$19 assign { } { } assign { } { } assign { } { } - assign { $1\br_op__is_32bit$9$next[0:0]$8849 $1\br_op__lk$8$next[0:0]$8850 $1\br_op__imm_data__ok$7$next[0:0]$8846 $1\br_op__imm_data__data$6$next[63:0]$8845 $1\br_op__insn$5$next[31:0]$8847 $1\br_op__fn_unit$4$next[13:0]$8844 $1\br_op__insn_type$3$next[6:0]$8848 $1\br_op__cia$2$next[63:0]$8843 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } + assign { $1\br_op__is_32bit$9$next[0:0]$8833 $1\br_op__lk$8$next[0:0]$8834 $1\br_op__imm_data__ok$7$next[0:0]$8830 $1\br_op__imm_data__data$6$next[63:0]$8829 $1\br_op__insn$5$next[31:0]$8831 $1\br_op__fn_unit$4$next[13:0]$8828 $1\br_op__insn_type$3$next[6:0]$8832 $1\br_op__cia$2$next[63:0]$8827 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -335183,16 +306553,16 @@ module \pipe$19 assign { } { } assign { } { } assign { } { } - assign { $1\br_op__is_32bit$9$next[0:0]$8849 $1\br_op__lk$8$next[0:0]$8850 $1\br_op__imm_data__ok$7$next[0:0]$8846 $1\br_op__imm_data__data$6$next[63:0]$8845 $1\br_op__insn$5$next[31:0]$8847 $1\br_op__fn_unit$4$next[13:0]$8844 $1\br_op__insn_type$3$next[6:0]$8848 $1\br_op__cia$2$next[63:0]$8843 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } + assign { $1\br_op__is_32bit$9$next[0:0]$8833 $1\br_op__lk$8$next[0:0]$8834 $1\br_op__imm_data__ok$7$next[0:0]$8830 $1\br_op__imm_data__data$6$next[63:0]$8829 $1\br_op__insn$5$next[31:0]$8831 $1\br_op__fn_unit$4$next[13:0]$8828 $1\br_op__insn_type$3$next[6:0]$8832 $1\br_op__cia$2$next[63:0]$8827 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } case - assign $1\br_op__cia$2$next[63:0]$8843 \br_op__cia$2 - assign $1\br_op__fn_unit$4$next[13:0]$8844 \br_op__fn_unit$4 - assign $1\br_op__imm_data__data$6$next[63:0]$8845 \br_op__imm_data__data$6 - assign $1\br_op__imm_data__ok$7$next[0:0]$8846 \br_op__imm_data__ok$7 - assign $1\br_op__insn$5$next[31:0]$8847 \br_op__insn$5 - assign $1\br_op__insn_type$3$next[6:0]$8848 \br_op__insn_type$3 - assign $1\br_op__is_32bit$9$next[0:0]$8849 \br_op__is_32bit$9 - assign $1\br_op__lk$8$next[0:0]$8850 \br_op__lk$8 + assign $1\br_op__cia$2$next[63:0]$8827 \br_op__cia$2 + assign $1\br_op__fn_unit$4$next[13:0]$8828 \br_op__fn_unit$4 + assign $1\br_op__imm_data__data$6$next[63:0]$8829 \br_op__imm_data__data$6 + assign $1\br_op__imm_data__ok$7$next[0:0]$8830 \br_op__imm_data__ok$7 + assign $1\br_op__insn$5$next[31:0]$8831 \br_op__insn$5 + assign $1\br_op__insn_type$3$next[6:0]$8832 \br_op__insn_type$3 + assign $1\br_op__is_32bit$9$next[0:0]$8833 \br_op__is_32bit$9 + assign $1\br_op__lk$8$next[0:0]$8834 \br_op__lk$8 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -335200,34 +306570,34 @@ module \pipe$19 case 1'1 assign { } { } assign { } { } - assign $2\br_op__imm_data__data$6$next[63:0]$8851 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\br_op__imm_data__ok$7$next[0:0]$8852 1'0 + assign $2\br_op__imm_data__data$6$next[63:0]$8835 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\br_op__imm_data__ok$7$next[0:0]$8836 1'0 case - assign $2\br_op__imm_data__data$6$next[63:0]$8851 $1\br_op__imm_data__data$6$next[63:0]$8845 - assign $2\br_op__imm_data__ok$7$next[0:0]$8852 $1\br_op__imm_data__ok$7$next[0:0]$8846 + assign $2\br_op__imm_data__data$6$next[63:0]$8835 $1\br_op__imm_data__data$6$next[63:0]$8829 + assign $2\br_op__imm_data__ok$7$next[0:0]$8836 $1\br_op__imm_data__ok$7$next[0:0]$8830 end sync always - update \br_op__cia$2$next $0\br_op__cia$2$next[63:0]$8835 - update \br_op__fn_unit$4$next $0\br_op__fn_unit$4$next[13:0]$8836 - update \br_op__imm_data__data$6$next $0\br_op__imm_data__data$6$next[63:0]$8837 - update \br_op__imm_data__ok$7$next $0\br_op__imm_data__ok$7$next[0:0]$8838 - update \br_op__insn$5$next $0\br_op__insn$5$next[31:0]$8839 - update \br_op__insn_type$3$next $0\br_op__insn_type$3$next[6:0]$8840 - update \br_op__is_32bit$9$next $0\br_op__is_32bit$9$next[0:0]$8841 - update \br_op__lk$8$next $0\br_op__lk$8$next[0:0]$8842 + update \br_op__cia$2$next $0\br_op__cia$2$next[63:0]$8819 + update \br_op__fn_unit$4$next $0\br_op__fn_unit$4$next[13:0]$8820 + update \br_op__imm_data__data$6$next $0\br_op__imm_data__data$6$next[63:0]$8821 + update \br_op__imm_data__ok$7$next $0\br_op__imm_data__ok$7$next[0:0]$8822 + update \br_op__insn$5$next $0\br_op__insn$5$next[31:0]$8823 + update \br_op__insn_type$3$next $0\br_op__insn_type$3$next[6:0]$8824 + update \br_op__is_32bit$9$next $0\br_op__is_32bit$9$next[0:0]$8825 + update \br_op__lk$8$next $0\br_op__lk$8$next[0:0]$8826 end - attribute \src "libresoc.v:163266.3-163284.6" - process $proc$libresoc.v:163266$8853 + attribute \src "libresoc.v:164574.3-164592.6" + process $proc$libresoc.v:164574$8837 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\fast1$10$next[63:0]$8854 $1\fast1$10$next[63:0]$8856 + assign $0\fast1$10$next[63:0]$8838 $1\fast1$10$next[63:0]$8840 assign { } { } - assign $0\fast1_ok$next[0:0]$8855 $2\fast1_ok$next[0:0]$8858 - attribute \src "libresoc.v:163267.5-163267.29" + assign $0\fast1_ok$next[0:0]$8839 $2\fast1_ok$next[0:0]$8842 + attribute \src "libresoc.v:164575.5-164575.29" switch \initial - attribute \src "libresoc.v:163267.9-163267.17" + attribute \src "libresoc.v:164575.9-164575.17" case 1'1 case end @@ -335237,41 +306607,41 @@ module \pipe$19 case 2'-1 assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$8857 $1\fast1$10$next[63:0]$8856 } { \fast1_ok$36 \fast1$35 } + assign { $1\fast1_ok$next[0:0]$8841 $1\fast1$10$next[63:0]$8840 } { \fast1_ok$36 \fast1$35 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$8857 $1\fast1$10$next[63:0]$8856 } { \fast1_ok$36 \fast1$35 } + assign { $1\fast1_ok$next[0:0]$8841 $1\fast1$10$next[63:0]$8840 } { \fast1_ok$36 \fast1$35 } case - assign $1\fast1$10$next[63:0]$8856 \fast1$10 - assign $1\fast1_ok$next[0:0]$8857 \fast1_ok + assign $1\fast1$10$next[63:0]$8840 \fast1$10 + assign $1\fast1_ok$next[0:0]$8841 \fast1_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast1_ok$next[0:0]$8858 1'0 + assign $2\fast1_ok$next[0:0]$8842 1'0 case - assign $2\fast1_ok$next[0:0]$8858 $1\fast1_ok$next[0:0]$8857 + assign $2\fast1_ok$next[0:0]$8842 $1\fast1_ok$next[0:0]$8841 end sync always - update \fast1$10$next $0\fast1$10$next[63:0]$8854 - update \fast1_ok$next $0\fast1_ok$next[0:0]$8855 + update \fast1$10$next $0\fast1$10$next[63:0]$8838 + update \fast1_ok$next $0\fast1_ok$next[0:0]$8839 end - attribute \src "libresoc.v:163285.3-163303.6" - process $proc$libresoc.v:163285$8859 + attribute \src "libresoc.v:164593.3-164611.6" + process $proc$libresoc.v:164593$8843 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\fast2$11$next[63:0]$8860 $1\fast2$11$next[63:0]$8862 + assign $0\fast2$11$next[63:0]$8844 $1\fast2$11$next[63:0]$8846 assign { } { } - assign $0\fast2_ok$next[0:0]$8861 $2\fast2_ok$next[0:0]$8864 - attribute \src "libresoc.v:163286.5-163286.29" + assign $0\fast2_ok$next[0:0]$8845 $2\fast2_ok$next[0:0]$8848 + attribute \src "libresoc.v:164594.5-164594.29" switch \initial - attribute \src "libresoc.v:163286.9-163286.17" + attribute \src "libresoc.v:164594.9-164594.17" case 1'1 case end @@ -335281,41 +306651,41 @@ module \pipe$19 case 2'-1 assign { } { } assign { } { } - assign { $1\fast2_ok$next[0:0]$8863 $1\fast2$11$next[63:0]$8862 } { \fast2_ok$38 \fast2$37 } + assign { $1\fast2_ok$next[0:0]$8847 $1\fast2$11$next[63:0]$8846 } { \fast2_ok$38 \fast2$37 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\fast2_ok$next[0:0]$8863 $1\fast2$11$next[63:0]$8862 } { \fast2_ok$38 \fast2$37 } + assign { $1\fast2_ok$next[0:0]$8847 $1\fast2$11$next[63:0]$8846 } { \fast2_ok$38 \fast2$37 } case - assign $1\fast2$11$next[63:0]$8862 \fast2$11 - assign $1\fast2_ok$next[0:0]$8863 \fast2_ok + assign $1\fast2$11$next[63:0]$8846 \fast2$11 + assign $1\fast2_ok$next[0:0]$8847 \fast2_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast2_ok$next[0:0]$8864 1'0 + assign $2\fast2_ok$next[0:0]$8848 1'0 case - assign $2\fast2_ok$next[0:0]$8864 $1\fast2_ok$next[0:0]$8863 + assign $2\fast2_ok$next[0:0]$8848 $1\fast2_ok$next[0:0]$8847 end sync always - update \fast2$11$next $0\fast2$11$next[63:0]$8860 - update \fast2_ok$next $0\fast2_ok$next[0:0]$8861 + update \fast2$11$next $0\fast2$11$next[63:0]$8844 + update \fast2_ok$next $0\fast2_ok$next[0:0]$8845 end - attribute \src "libresoc.v:163304.3-163322.6" - process $proc$libresoc.v:163304$8865 + attribute \src "libresoc.v:164612.3-164630.6" + process $proc$libresoc.v:164612$8849 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\nia$next[63:0]$8866 $1\nia$next[63:0]$8868 + assign $0\nia$next[63:0]$8850 $1\nia$next[63:0]$8852 assign { } { } - assign $0\nia_ok$next[0:0]$8867 $2\nia_ok$next[0:0]$8870 - attribute \src "libresoc.v:163305.5-163305.29" + assign $0\nia_ok$next[0:0]$8851 $2\nia_ok$next[0:0]$8854 + attribute \src "libresoc.v:164613.5-164613.29" switch \initial - attribute \src "libresoc.v:163305.9-163305.17" + attribute \src "libresoc.v:164613.9-164613.17" case 1'1 case end @@ -335325,30 +306695,30 @@ module \pipe$19 case 2'-1 assign { } { } assign { } { } - assign { $1\nia_ok$next[0:0]$8869 $1\nia$next[63:0]$8868 } { \nia_ok$40 \nia$39 } + assign { $1\nia_ok$next[0:0]$8853 $1\nia$next[63:0]$8852 } { \nia_ok$40 \nia$39 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\nia_ok$next[0:0]$8869 $1\nia$next[63:0]$8868 } { \nia_ok$40 \nia$39 } + assign { $1\nia_ok$next[0:0]$8853 $1\nia$next[63:0]$8852 } { \nia_ok$40 \nia$39 } case - assign $1\nia$next[63:0]$8868 \nia - assign $1\nia_ok$next[0:0]$8869 \nia_ok + assign $1\nia$next[63:0]$8852 \nia + assign $1\nia_ok$next[0:0]$8853 \nia_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\nia_ok$next[0:0]$8870 1'0 + assign $2\nia_ok$next[0:0]$8854 1'0 case - assign $2\nia_ok$next[0:0]$8870 $1\nia_ok$next[0:0]$8869 + assign $2\nia_ok$next[0:0]$8854 $1\nia_ok$next[0:0]$8853 end sync always - update \nia$next $0\nia$next[63:0]$8866 - update \nia_ok$next $0\nia_ok$next[0:0]$8867 + update \nia$next $0\nia$next[63:0]$8850 + update \nia_ok$next $0\nia_ok$next[0:0]$8851 end - connect \$24 $and$libresoc.v:163137$8799_Y + connect \$24 $and$libresoc.v:164445$8783_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \nia_ok$40 \nia$39 } { \main_nia_ok \main_nia } @@ -335365,178 +306735,178 @@ module \pipe$19 connect { \main_br_op__is_32bit \main_br_op__lk \main_br_op__imm_data__ok \main_br_op__imm_data__data \main_br_op__insn \main_br_op__fn_unit \main_br_op__insn_type \main_br_op__cia } { \br_op__is_32bit \br_op__lk \br_op__imm_data__ok \br_op__imm_data__data \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } connect \main_muxid \muxid end -attribute \src "libresoc.v:163342.1-164272.10" +attribute \src "libresoc.v:164650.1-165580.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe" attribute \generator "nMigen" module \pipe$64 - attribute \src "libresoc.v:164175.3-164193.6" - wire width 64 $0\fast1$7$next[63:0]$8958 - attribute \src "libresoc.v:164028.3-164029.33" - wire width 64 $0\fast1$7[63:0]$8910 - attribute \src "libresoc.v:163356.14-163356.46" - wire width 64 $0\fast1$7[63:0]$8982 - attribute \src "libresoc.v:164175.3-164193.6" - wire $0\fast1_ok$next[0:0]$8957 - attribute \src "libresoc.v:164030.3-164031.33" + attribute \src "libresoc.v:165483.3-165501.6" + wire width 64 $0\fast1$7$next[63:0]$8942 + attribute \src "libresoc.v:165336.3-165337.33" + wire width 64 $0\fast1$7[63:0]$8894 + attribute \src "libresoc.v:164664.14-164664.46" + wire width 64 $0\fast1$7[63:0]$8966 + attribute \src "libresoc.v:165483.3-165501.6" + wire $0\fast1_ok$next[0:0]$8941 + attribute \src "libresoc.v:165338.3-165339.33" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:163343.7-163343.20" + attribute \src "libresoc.v:164651.7-164651.20" wire $0\initial[0:0] - attribute \src "libresoc.v:164108.3-164120.6" - wire width 2 $0\muxid$1$next[1:0]$8933 - attribute \src "libresoc.v:164048.3-164049.33" - wire width 2 $0\muxid$1[1:0]$8926 - attribute \src "libresoc.v:163370.13-163370.29" - wire width 2 $0\muxid$1[1:0]$8985 - attribute \src "libresoc.v:164137.3-164155.6" - wire width 64 $0\o$next[63:0]$8945 - attribute \src "libresoc.v:164036.3-164037.19" + attribute \src "libresoc.v:165416.3-165428.6" + wire width 2 $0\muxid$1$next[1:0]$8917 + attribute \src "libresoc.v:165356.3-165357.33" + wire width 2 $0\muxid$1[1:0]$8910 + attribute \src "libresoc.v:164678.13-164678.29" + wire width 2 $0\muxid$1[1:0]$8969 + attribute \src "libresoc.v:165445.3-165463.6" + wire width 64 $0\o$next[63:0]$8929 + attribute \src "libresoc.v:165344.3-165345.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:164137.3-164155.6" - wire $0\o_ok$next[0:0]$8946 - attribute \src "libresoc.v:164038.3-164039.25" + attribute \src "libresoc.v:165445.3-165463.6" + wire $0\o_ok$next[0:0]$8930 + attribute \src "libresoc.v:165346.3-165347.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:164090.3-164107.6" - wire $0\r_busy$next[0:0]$8929 - attribute \src "libresoc.v:164050.3-164051.29" + attribute \src "libresoc.v:165398.3-165415.6" + wire $0\r_busy$next[0:0]$8913 + attribute \src "libresoc.v:165358.3-165359.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:164156.3-164174.6" - wire width 64 $0\spr1$6$next[63:0]$8951 - attribute \src "libresoc.v:164032.3-164033.31" - wire width 64 $0\spr1$6[63:0]$8913 - attribute \src "libresoc.v:163415.14-163415.45" - wire width 64 $0\spr1$6[63:0]$8990 - attribute \src "libresoc.v:164156.3-164174.6" - wire $0\spr1_ok$next[0:0]$8952 - attribute \src "libresoc.v:164034.3-164035.31" + attribute \src "libresoc.v:165464.3-165482.6" + wire width 64 $0\spr1$6$next[63:0]$8935 + attribute \src "libresoc.v:165340.3-165341.31" + wire width 64 $0\spr1$6[63:0]$8897 + attribute \src "libresoc.v:164723.14-164723.45" + wire width 64 $0\spr1$6[63:0]$8974 + attribute \src "libresoc.v:165464.3-165482.6" + wire $0\spr1_ok$next[0:0]$8936 + attribute \src "libresoc.v:165342.3-165343.31" wire $0\spr1_ok[0:0] - attribute \src "libresoc.v:164121.3-164136.6" - wire width 14 $0\spr_op__fn_unit$3$next[13:0]$8936 - attribute \src "libresoc.v:164042.3-164043.53" - wire width 14 $0\spr_op__fn_unit$3[13:0]$8920 - attribute \src "libresoc.v:163712.14-163712.44" - wire width 14 $0\spr_op__fn_unit$3[13:0]$8993 - attribute \src "libresoc.v:164121.3-164136.6" - wire width 32 $0\spr_op__insn$4$next[31:0]$8937 - attribute \src "libresoc.v:164044.3-164045.47" - wire width 32 $0\spr_op__insn$4[31:0]$8922 - attribute \src "libresoc.v:163721.14-163721.38" - wire width 32 $0\spr_op__insn$4[31:0]$8995 - attribute \src "libresoc.v:164121.3-164136.6" - wire width 7 $0\spr_op__insn_type$2$next[6:0]$8938 - attribute \src "libresoc.v:164040.3-164041.57" - wire width 7 $0\spr_op__insn_type$2[6:0]$8918 - attribute \src "libresoc.v:163878.13-163878.42" - wire width 7 $0\spr_op__insn_type$2[6:0]$8997 - attribute \src "libresoc.v:164121.3-164136.6" - wire $0\spr_op__is_32bit$5$next[0:0]$8939 - attribute \src "libresoc.v:164046.3-164047.55" - wire $0\spr_op__is_32bit$5[0:0]$8924 - attribute \src "libresoc.v:163964.7-163964.34" - wire $0\spr_op__is_32bit$5[0:0]$8999 - attribute \src "libresoc.v:164232.3-164250.6" - wire width 2 $0\xer_ca$10$next[1:0]$8975 - attribute \src "libresoc.v:164016.3-164017.37" - wire width 2 $0\xer_ca$10[1:0]$8901 - attribute \src "libresoc.v:163971.13-163971.31" - wire width 2 $0\xer_ca$10[1:0]$9001 - attribute \src "libresoc.v:164232.3-164250.6" - wire $0\xer_ca_ok$next[0:0]$8976 - attribute \src "libresoc.v:164018.3-164019.35" + attribute \src "libresoc.v:165429.3-165444.6" + wire width 14 $0\spr_op__fn_unit$3$next[13:0]$8920 + attribute \src "libresoc.v:165350.3-165351.53" + wire width 14 $0\spr_op__fn_unit$3[13:0]$8904 + attribute \src "libresoc.v:165020.14-165020.44" + wire width 14 $0\spr_op__fn_unit$3[13:0]$8977 + attribute \src "libresoc.v:165429.3-165444.6" + wire width 32 $0\spr_op__insn$4$next[31:0]$8921 + attribute \src "libresoc.v:165352.3-165353.47" + wire width 32 $0\spr_op__insn$4[31:0]$8906 + attribute \src "libresoc.v:165029.14-165029.38" + wire width 32 $0\spr_op__insn$4[31:0]$8979 + attribute \src "libresoc.v:165429.3-165444.6" + wire width 7 $0\spr_op__insn_type$2$next[6:0]$8922 + attribute \src "libresoc.v:165348.3-165349.57" + wire width 7 $0\spr_op__insn_type$2[6:0]$8902 + attribute \src "libresoc.v:165186.13-165186.42" + wire width 7 $0\spr_op__insn_type$2[6:0]$8981 + attribute \src "libresoc.v:165429.3-165444.6" + wire $0\spr_op__is_32bit$5$next[0:0]$8923 + attribute \src "libresoc.v:165354.3-165355.55" + wire $0\spr_op__is_32bit$5[0:0]$8908 + attribute \src "libresoc.v:165272.7-165272.34" + wire $0\spr_op__is_32bit$5[0:0]$8983 + attribute \src "libresoc.v:165540.3-165558.6" + wire width 2 $0\xer_ca$10$next[1:0]$8959 + attribute \src "libresoc.v:165324.3-165325.37" + wire width 2 $0\xer_ca$10[1:0]$8885 + attribute \src "libresoc.v:165279.13-165279.31" + wire width 2 $0\xer_ca$10[1:0]$8985 + attribute \src "libresoc.v:165540.3-165558.6" + wire $0\xer_ca_ok$next[0:0]$8960 + attribute \src "libresoc.v:165326.3-165327.35" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:164213.3-164231.6" - wire width 2 $0\xer_ov$9$next[1:0]$8970 - attribute \src "libresoc.v:164020.3-164021.35" - wire width 2 $0\xer_ov$9[1:0]$8904 - attribute \src "libresoc.v:163989.13-163989.30" - wire width 2 $0\xer_ov$9[1:0]$9004 - attribute \src "libresoc.v:164213.3-164231.6" - wire $0\xer_ov_ok$next[0:0]$8969 - attribute \src "libresoc.v:164022.3-164023.35" + attribute \src "libresoc.v:165521.3-165539.6" + wire width 2 $0\xer_ov$9$next[1:0]$8954 + attribute \src "libresoc.v:165328.3-165329.35" + wire width 2 $0\xer_ov$9[1:0]$8888 + attribute \src "libresoc.v:165297.13-165297.30" + wire width 2 $0\xer_ov$9[1:0]$8988 + attribute \src "libresoc.v:165521.3-165539.6" + wire $0\xer_ov_ok$next[0:0]$8953 + attribute \src "libresoc.v:165330.3-165331.35" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:164194.3-164212.6" - wire $0\xer_so$8$next[0:0]$8964 - attribute \src "libresoc.v:164024.3-164025.35" - wire $0\xer_so$8[0:0]$8907 - attribute \src "libresoc.v:164005.7-164005.24" - wire $0\xer_so$8[0:0]$9007 - attribute \src "libresoc.v:164194.3-164212.6" - wire $0\xer_so_ok$next[0:0]$8963 - attribute \src "libresoc.v:164026.3-164027.35" + attribute \src "libresoc.v:165502.3-165520.6" + wire $0\xer_so$8$next[0:0]$8948 + attribute \src "libresoc.v:165332.3-165333.35" + wire $0\xer_so$8[0:0]$8891 + attribute \src "libresoc.v:165313.7-165313.24" + wire $0\xer_so$8[0:0]$8991 + attribute \src "libresoc.v:165502.3-165520.6" + wire $0\xer_so_ok$next[0:0]$8947 + attribute \src "libresoc.v:165334.3-165335.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:164175.3-164193.6" - wire width 64 $1\fast1$7$next[63:0]$8960 - attribute \src "libresoc.v:164175.3-164193.6" - wire $1\fast1_ok$next[0:0]$8959 - attribute \src "libresoc.v:163361.7-163361.22" + attribute \src "libresoc.v:165483.3-165501.6" + wire width 64 $1\fast1$7$next[63:0]$8944 + attribute \src "libresoc.v:165483.3-165501.6" + wire $1\fast1_ok$next[0:0]$8943 + attribute \src "libresoc.v:164669.7-164669.22" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:164108.3-164120.6" - wire width 2 $1\muxid$1$next[1:0]$8934 - attribute \src "libresoc.v:164137.3-164155.6" - wire width 64 $1\o$next[63:0]$8947 - attribute \src "libresoc.v:163383.14-163383.38" + attribute \src "libresoc.v:165416.3-165428.6" + wire width 2 $1\muxid$1$next[1:0]$8918 + attribute \src "libresoc.v:165445.3-165463.6" + wire width 64 $1\o$next[63:0]$8931 + attribute \src "libresoc.v:164691.14-164691.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:164137.3-164155.6" - wire $1\o_ok$next[0:0]$8948 - attribute \src "libresoc.v:163390.7-163390.18" + attribute \src "libresoc.v:165445.3-165463.6" + wire $1\o_ok$next[0:0]$8932 + attribute \src "libresoc.v:164698.7-164698.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:164090.3-164107.6" - wire $1\r_busy$next[0:0]$8930 - attribute \src "libresoc.v:163404.7-163404.20" + attribute \src "libresoc.v:165398.3-165415.6" + wire $1\r_busy$next[0:0]$8914 + attribute \src "libresoc.v:164712.7-164712.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:164156.3-164174.6" - wire width 64 $1\spr1$6$next[63:0]$8953 - attribute \src "libresoc.v:164156.3-164174.6" - wire $1\spr1_ok$next[0:0]$8954 - attribute \src "libresoc.v:163420.7-163420.21" + attribute \src "libresoc.v:165464.3-165482.6" + wire width 64 $1\spr1$6$next[63:0]$8937 + attribute \src "libresoc.v:165464.3-165482.6" + wire $1\spr1_ok$next[0:0]$8938 + attribute \src "libresoc.v:164728.7-164728.21" wire $1\spr1_ok[0:0] - attribute \src "libresoc.v:164121.3-164136.6" - wire width 14 $1\spr_op__fn_unit$3$next[13:0]$8940 - attribute \src "libresoc.v:164121.3-164136.6" - wire width 32 $1\spr_op__insn$4$next[31:0]$8941 - attribute \src "libresoc.v:164121.3-164136.6" - wire width 7 $1\spr_op__insn_type$2$next[6:0]$8942 - attribute \src "libresoc.v:164121.3-164136.6" - wire $1\spr_op__is_32bit$5$next[0:0]$8943 - attribute \src "libresoc.v:164232.3-164250.6" - wire width 2 $1\xer_ca$10$next[1:0]$8977 - attribute \src "libresoc.v:164232.3-164250.6" - wire $1\xer_ca_ok$next[0:0]$8978 - attribute \src "libresoc.v:163978.7-163978.23" + attribute \src "libresoc.v:165429.3-165444.6" + wire width 14 $1\spr_op__fn_unit$3$next[13:0]$8924 + attribute \src "libresoc.v:165429.3-165444.6" + wire width 32 $1\spr_op__insn$4$next[31:0]$8925 + attribute \src "libresoc.v:165429.3-165444.6" + wire width 7 $1\spr_op__insn_type$2$next[6:0]$8926 + attribute \src "libresoc.v:165429.3-165444.6" + wire $1\spr_op__is_32bit$5$next[0:0]$8927 + attribute \src "libresoc.v:165540.3-165558.6" + wire width 2 $1\xer_ca$10$next[1:0]$8961 + attribute \src "libresoc.v:165540.3-165558.6" + wire $1\xer_ca_ok$next[0:0]$8962 + attribute \src "libresoc.v:165286.7-165286.23" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:164213.3-164231.6" - wire width 2 $1\xer_ov$9$next[1:0]$8972 - attribute \src "libresoc.v:164213.3-164231.6" - wire $1\xer_ov_ok$next[0:0]$8971 - attribute \src "libresoc.v:163994.7-163994.23" + attribute \src "libresoc.v:165521.3-165539.6" + wire width 2 $1\xer_ov$9$next[1:0]$8956 + attribute \src "libresoc.v:165521.3-165539.6" + wire $1\xer_ov_ok$next[0:0]$8955 + attribute \src "libresoc.v:165302.7-165302.23" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:164194.3-164212.6" - wire $1\xer_so$8$next[0:0]$8966 - attribute \src "libresoc.v:164194.3-164212.6" - wire $1\xer_so_ok$next[0:0]$8965 - attribute \src "libresoc.v:164010.7-164010.23" + attribute \src "libresoc.v:165502.3-165520.6" + wire $1\xer_so$8$next[0:0]$8950 + attribute \src "libresoc.v:165502.3-165520.6" + wire $1\xer_so_ok$next[0:0]$8949 + attribute \src "libresoc.v:165318.7-165318.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:164175.3-164193.6" - wire $2\fast1_ok$next[0:0]$8961 - attribute \src "libresoc.v:164137.3-164155.6" - wire $2\o_ok$next[0:0]$8949 - attribute \src "libresoc.v:164090.3-164107.6" - wire $2\r_busy$next[0:0]$8931 - attribute \src "libresoc.v:164156.3-164174.6" - wire $2\spr1_ok$next[0:0]$8955 - attribute \src "libresoc.v:164232.3-164250.6" - wire $2\xer_ca_ok$next[0:0]$8979 - attribute \src "libresoc.v:164213.3-164231.6" - wire $2\xer_ov_ok$next[0:0]$8973 - attribute \src "libresoc.v:164194.3-164212.6" - wire $2\xer_so_ok$next[0:0]$8967 - attribute \src "libresoc.v:164015.18-164015.118" - wire $and$libresoc.v:164015$8899_Y + attribute \src "libresoc.v:165483.3-165501.6" + wire $2\fast1_ok$next[0:0]$8945 + attribute \src "libresoc.v:165445.3-165463.6" + wire $2\o_ok$next[0:0]$8933 + attribute \src "libresoc.v:165398.3-165415.6" + wire $2\r_busy$next[0:0]$8915 + attribute \src "libresoc.v:165464.3-165482.6" + wire $2\spr1_ok$next[0:0]$8939 + attribute \src "libresoc.v:165540.3-165558.6" + wire $2\xer_ca_ok$next[0:0]$8963 + attribute \src "libresoc.v:165521.3-165539.6" + wire $2\xer_ov_ok$next[0:0]$8957 + attribute \src "libresoc.v:165502.3-165520.6" + wire $2\xer_so_ok$next[0:0]$8951 + attribute \src "libresoc.v:165323.18-165323.118" + wire $and$libresoc.v:165323$8883_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 34 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 11 \fast1 @@ -335552,7 +306922,7 @@ module \pipe$64 wire \fast1_ok$34 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fast1_ok$next - attribute \src "libresoc.v:163343.7-163343.15" + attribute \src "libresoc.v:164651.7-164651.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 4 \muxid @@ -336189,7 +307559,7 @@ module \pipe$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:164015$8899 + cell $and $and$libresoc.v:165323$8883 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -336197,22 +307567,22 @@ module \pipe$64 parameter \Y_WIDTH 1 connect \A \p_valid_i$21 connect \B \p_ready_o - connect \Y $and$libresoc.v:164015$8899_Y + connect \Y $and$libresoc.v:165323$8883_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:164052.10-164055.4" + attribute \src "libresoc.v:165360.10-165363.4" cell \n$66 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:164056.10-164059.4" + attribute \src "libresoc.v:165364.10-165367.4" cell \p$65 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:164060.12-164089.4" + attribute \src "libresoc.v:165368.12-165397.4" cell \spr_main \spr_main connect \fast1 \spr_main_fast1 connect \fast1$7 \spr_main_fast1$17 @@ -336243,293 +307613,293 @@ module \pipe$64 connect \xer_so$8 \spr_main_xer_so$18 connect \xer_so_ok \spr_main_xer_so_ok end - attribute \src "libresoc.v:163343.7-163343.20" - process $proc$libresoc.v:163343$8980 + attribute \src "libresoc.v:164651.7-164651.20" + process $proc$libresoc.v:164651$8964 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:163356.14-163356.46" - process $proc$libresoc.v:163356$8981 + attribute \src "libresoc.v:164664.14-164664.46" + process $proc$libresoc.v:164664$8965 assign { } { } - assign $0\fast1$7[63:0]$8982 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\fast1$7[63:0]$8966 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \fast1$7 $0\fast1$7[63:0]$8982 + update \fast1$7 $0\fast1$7[63:0]$8966 end - attribute \src "libresoc.v:163361.7-163361.22" - process $proc$libresoc.v:163361$8983 + attribute \src "libresoc.v:164669.7-164669.22" + process $proc$libresoc.v:164669$8967 assign { } { } assign $1\fast1_ok[0:0] 1'0 sync always sync init update \fast1_ok $1\fast1_ok[0:0] end - attribute \src "libresoc.v:163370.13-163370.29" - process $proc$libresoc.v:163370$8984 + attribute \src "libresoc.v:164678.13-164678.29" + process $proc$libresoc.v:164678$8968 assign { } { } - assign $0\muxid$1[1:0]$8985 2'00 + assign $0\muxid$1[1:0]$8969 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$8985 + update \muxid$1 $0\muxid$1[1:0]$8969 end - attribute \src "libresoc.v:163383.14-163383.38" - process $proc$libresoc.v:163383$8986 + attribute \src "libresoc.v:164691.14-164691.38" + process $proc$libresoc.v:164691$8970 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:163390.7-163390.18" - process $proc$libresoc.v:163390$8987 + attribute \src "libresoc.v:164698.7-164698.18" + process $proc$libresoc.v:164698$8971 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:163404.7-163404.20" - process $proc$libresoc.v:163404$8988 + attribute \src "libresoc.v:164712.7-164712.20" + process $proc$libresoc.v:164712$8972 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:163415.14-163415.45" - process $proc$libresoc.v:163415$8989 + attribute \src "libresoc.v:164723.14-164723.45" + process $proc$libresoc.v:164723$8973 assign { } { } - assign $0\spr1$6[63:0]$8990 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\spr1$6[63:0]$8974 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \spr1$6 $0\spr1$6[63:0]$8990 + update \spr1$6 $0\spr1$6[63:0]$8974 end - attribute \src "libresoc.v:163420.7-163420.21" - process $proc$libresoc.v:163420$8991 + attribute \src "libresoc.v:164728.7-164728.21" + process $proc$libresoc.v:164728$8975 assign { } { } assign $1\spr1_ok[0:0] 1'0 sync always sync init update \spr1_ok $1\spr1_ok[0:0] end - attribute \src "libresoc.v:163712.14-163712.44" - process $proc$libresoc.v:163712$8992 + attribute \src "libresoc.v:165020.14-165020.44" + process $proc$libresoc.v:165020$8976 assign { } { } - assign $0\spr_op__fn_unit$3[13:0]$8993 14'00000000000000 + assign $0\spr_op__fn_unit$3[13:0]$8977 14'00000000000000 sync always sync init - update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[13:0]$8993 + update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[13:0]$8977 end - attribute \src "libresoc.v:163721.14-163721.38" - process $proc$libresoc.v:163721$8994 + attribute \src "libresoc.v:165029.14-165029.38" + process $proc$libresoc.v:165029$8978 assign { } { } - assign $0\spr_op__insn$4[31:0]$8995 0 + assign $0\spr_op__insn$4[31:0]$8979 0 sync always sync init - update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8995 + update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8979 end - attribute \src "libresoc.v:163878.13-163878.42" - process $proc$libresoc.v:163878$8996 + attribute \src "libresoc.v:165186.13-165186.42" + process $proc$libresoc.v:165186$8980 assign { } { } - assign $0\spr_op__insn_type$2[6:0]$8997 7'0000000 + assign $0\spr_op__insn_type$2[6:0]$8981 7'0000000 sync always sync init - update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8997 + update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8981 end - attribute \src "libresoc.v:163964.7-163964.34" - process $proc$libresoc.v:163964$8998 + attribute \src "libresoc.v:165272.7-165272.34" + process $proc$libresoc.v:165272$8982 assign { } { } - assign $0\spr_op__is_32bit$5[0:0]$8999 1'0 + assign $0\spr_op__is_32bit$5[0:0]$8983 1'0 sync always sync init - update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8999 + update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8983 end - attribute \src "libresoc.v:163971.13-163971.31" - process $proc$libresoc.v:163971$9000 + attribute \src "libresoc.v:165279.13-165279.31" + process $proc$libresoc.v:165279$8984 assign { } { } - assign $0\xer_ca$10[1:0]$9001 2'00 + assign $0\xer_ca$10[1:0]$8985 2'00 sync always sync init - update \xer_ca$10 $0\xer_ca$10[1:0]$9001 + update \xer_ca$10 $0\xer_ca$10[1:0]$8985 end - attribute \src "libresoc.v:163978.7-163978.23" - process $proc$libresoc.v:163978$9002 + attribute \src "libresoc.v:165286.7-165286.23" + process $proc$libresoc.v:165286$8986 assign { } { } assign $1\xer_ca_ok[0:0] 1'0 sync always sync init update \xer_ca_ok $1\xer_ca_ok[0:0] end - attribute \src "libresoc.v:163989.13-163989.30" - process $proc$libresoc.v:163989$9003 + attribute \src "libresoc.v:165297.13-165297.30" + process $proc$libresoc.v:165297$8987 assign { } { } - assign $0\xer_ov$9[1:0]$9004 2'00 + assign $0\xer_ov$9[1:0]$8988 2'00 sync always sync init - update \xer_ov$9 $0\xer_ov$9[1:0]$9004 + update \xer_ov$9 $0\xer_ov$9[1:0]$8988 end - attribute \src "libresoc.v:163994.7-163994.23" - process $proc$libresoc.v:163994$9005 + attribute \src "libresoc.v:165302.7-165302.23" + process $proc$libresoc.v:165302$8989 assign { } { } assign $1\xer_ov_ok[0:0] 1'0 sync always sync init update \xer_ov_ok $1\xer_ov_ok[0:0] end - attribute \src "libresoc.v:164005.7-164005.24" - process $proc$libresoc.v:164005$9006 + attribute \src "libresoc.v:165313.7-165313.24" + process $proc$libresoc.v:165313$8990 assign { } { } - assign $0\xer_so$8[0:0]$9007 1'0 + assign $0\xer_so$8[0:0]$8991 1'0 sync always sync init - update \xer_so$8 $0\xer_so$8[0:0]$9007 + update \xer_so$8 $0\xer_so$8[0:0]$8991 end - attribute \src "libresoc.v:164010.7-164010.23" - process $proc$libresoc.v:164010$9008 + attribute \src "libresoc.v:165318.7-165318.23" + process $proc$libresoc.v:165318$8992 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:164016.3-164017.37" - process $proc$libresoc.v:164016$8900 + attribute \src "libresoc.v:165324.3-165325.37" + process $proc$libresoc.v:165324$8884 assign { } { } - assign $0\xer_ca$10[1:0]$8901 \xer_ca$10$next + assign $0\xer_ca$10[1:0]$8885 \xer_ca$10$next sync posedge \coresync_clk - update \xer_ca$10 $0\xer_ca$10[1:0]$8901 + update \xer_ca$10 $0\xer_ca$10[1:0]$8885 end - attribute \src "libresoc.v:164018.3-164019.35" - process $proc$libresoc.v:164018$8902 + attribute \src "libresoc.v:165326.3-165327.35" + process $proc$libresoc.v:165326$8886 assign { } { } assign $0\xer_ca_ok[0:0] \xer_ca_ok$next sync posedge \coresync_clk update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:164020.3-164021.35" - process $proc$libresoc.v:164020$8903 + attribute \src "libresoc.v:165328.3-165329.35" + process $proc$libresoc.v:165328$8887 assign { } { } - assign $0\xer_ov$9[1:0]$8904 \xer_ov$9$next + assign $0\xer_ov$9[1:0]$8888 \xer_ov$9$next sync posedge \coresync_clk - update \xer_ov$9 $0\xer_ov$9[1:0]$8904 + update \xer_ov$9 $0\xer_ov$9[1:0]$8888 end - attribute \src "libresoc.v:164022.3-164023.35" - process $proc$libresoc.v:164022$8905 + attribute \src "libresoc.v:165330.3-165331.35" + process $proc$libresoc.v:165330$8889 assign { } { } assign $0\xer_ov_ok[0:0] \xer_ov_ok$next sync posedge \coresync_clk update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:164024.3-164025.35" - process $proc$libresoc.v:164024$8906 + attribute \src "libresoc.v:165332.3-165333.35" + process $proc$libresoc.v:165332$8890 assign { } { } - assign $0\xer_so$8[0:0]$8907 \xer_so$8$next + assign $0\xer_so$8[0:0]$8891 \xer_so$8$next sync posedge \coresync_clk - update \xer_so$8 $0\xer_so$8[0:0]$8907 + update \xer_so$8 $0\xer_so$8[0:0]$8891 end - attribute \src "libresoc.v:164026.3-164027.35" - process $proc$libresoc.v:164026$8908 + attribute \src "libresoc.v:165334.3-165335.35" + process $proc$libresoc.v:165334$8892 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:164028.3-164029.33" - process $proc$libresoc.v:164028$8909 + attribute \src "libresoc.v:165336.3-165337.33" + process $proc$libresoc.v:165336$8893 assign { } { } - assign $0\fast1$7[63:0]$8910 \fast1$7$next + assign $0\fast1$7[63:0]$8894 \fast1$7$next sync posedge \coresync_clk - update \fast1$7 $0\fast1$7[63:0]$8910 + update \fast1$7 $0\fast1$7[63:0]$8894 end - attribute \src "libresoc.v:164030.3-164031.33" - process $proc$libresoc.v:164030$8911 + attribute \src "libresoc.v:165338.3-165339.33" + process $proc$libresoc.v:165338$8895 assign { } { } assign $0\fast1_ok[0:0] \fast1_ok$next sync posedge \coresync_clk update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:164032.3-164033.31" - process $proc$libresoc.v:164032$8912 + attribute \src "libresoc.v:165340.3-165341.31" + process $proc$libresoc.v:165340$8896 assign { } { } - assign $0\spr1$6[63:0]$8913 \spr1$6$next + assign $0\spr1$6[63:0]$8897 \spr1$6$next sync posedge \coresync_clk - update \spr1$6 $0\spr1$6[63:0]$8913 + update \spr1$6 $0\spr1$6[63:0]$8897 end - attribute \src "libresoc.v:164034.3-164035.31" - process $proc$libresoc.v:164034$8914 + attribute \src "libresoc.v:165342.3-165343.31" + process $proc$libresoc.v:165342$8898 assign { } { } assign $0\spr1_ok[0:0] \spr1_ok$next sync posedge \coresync_clk update \spr1_ok $0\spr1_ok[0:0] end - attribute \src "libresoc.v:164036.3-164037.19" - process $proc$libresoc.v:164036$8915 + attribute \src "libresoc.v:165344.3-165345.19" + process $proc$libresoc.v:165344$8899 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:164038.3-164039.25" - process $proc$libresoc.v:164038$8916 + attribute \src "libresoc.v:165346.3-165347.25" + process $proc$libresoc.v:165346$8900 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:164040.3-164041.57" - process $proc$libresoc.v:164040$8917 + attribute \src "libresoc.v:165348.3-165349.57" + process $proc$libresoc.v:165348$8901 assign { } { } - assign $0\spr_op__insn_type$2[6:0]$8918 \spr_op__insn_type$2$next + assign $0\spr_op__insn_type$2[6:0]$8902 \spr_op__insn_type$2$next sync posedge \coresync_clk - update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8918 + update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8902 end - attribute \src "libresoc.v:164042.3-164043.53" - process $proc$libresoc.v:164042$8919 + attribute \src "libresoc.v:165350.3-165351.53" + process $proc$libresoc.v:165350$8903 assign { } { } - assign $0\spr_op__fn_unit$3[13:0]$8920 \spr_op__fn_unit$3$next + assign $0\spr_op__fn_unit$3[13:0]$8904 \spr_op__fn_unit$3$next sync posedge \coresync_clk - update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[13:0]$8920 + update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[13:0]$8904 end - attribute \src "libresoc.v:164044.3-164045.47" - process $proc$libresoc.v:164044$8921 + attribute \src "libresoc.v:165352.3-165353.47" + process $proc$libresoc.v:165352$8905 assign { } { } - assign $0\spr_op__insn$4[31:0]$8922 \spr_op__insn$4$next + assign $0\spr_op__insn$4[31:0]$8906 \spr_op__insn$4$next sync posedge \coresync_clk - update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8922 + update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8906 end - attribute \src "libresoc.v:164046.3-164047.55" - process $proc$libresoc.v:164046$8923 + attribute \src "libresoc.v:165354.3-165355.55" + process $proc$libresoc.v:165354$8907 assign { } { } - assign $0\spr_op__is_32bit$5[0:0]$8924 \spr_op__is_32bit$5$next + assign $0\spr_op__is_32bit$5[0:0]$8908 \spr_op__is_32bit$5$next sync posedge \coresync_clk - update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8924 + update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8908 end - attribute \src "libresoc.v:164048.3-164049.33" - process $proc$libresoc.v:164048$8925 + attribute \src "libresoc.v:165356.3-165357.33" + process $proc$libresoc.v:165356$8909 assign { } { } - assign $0\muxid$1[1:0]$8926 \muxid$1$next + assign $0\muxid$1[1:0]$8910 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$8926 + update \muxid$1 $0\muxid$1[1:0]$8910 end - attribute \src "libresoc.v:164050.3-164051.29" - process $proc$libresoc.v:164050$8927 + attribute \src "libresoc.v:165358.3-165359.29" + process $proc$libresoc.v:165358$8911 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:164090.3-164107.6" - process $proc$libresoc.v:164090$8928 + attribute \src "libresoc.v:165398.3-165415.6" + process $proc$libresoc.v:165398$8912 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$8929 $2\r_busy$next[0:0]$8931 - attribute \src "libresoc.v:164091.5-164091.29" + assign $0\r_busy$next[0:0]$8913 $2\r_busy$next[0:0]$8915 + attribute \src "libresoc.v:165399.5-165399.29" switch \initial - attribute \src "libresoc.v:164091.9-164091.17" + attribute \src "libresoc.v:165399.9-165399.17" case 1'1 case end @@ -336538,34 +307908,34 @@ module \pipe$64 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$8930 1'1 + assign $1\r_busy$next[0:0]$8914 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$8930 1'0 + assign $1\r_busy$next[0:0]$8914 1'0 case - assign $1\r_busy$next[0:0]$8930 \r_busy + assign $1\r_busy$next[0:0]$8914 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$8931 1'0 + assign $2\r_busy$next[0:0]$8915 1'0 case - assign $2\r_busy$next[0:0]$8931 $1\r_busy$next[0:0]$8930 + assign $2\r_busy$next[0:0]$8915 $1\r_busy$next[0:0]$8914 end sync always - update \r_busy$next $0\r_busy$next[0:0]$8929 + update \r_busy$next $0\r_busy$next[0:0]$8913 end - attribute \src "libresoc.v:164108.3-164120.6" - process $proc$libresoc.v:164108$8932 + attribute \src "libresoc.v:165416.3-165428.6" + process $proc$libresoc.v:165416$8916 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$8933 $1\muxid$1$next[1:0]$8934 - attribute \src "libresoc.v:164109.5-164109.29" + assign $0\muxid$1$next[1:0]$8917 $1\muxid$1$next[1:0]$8918 + attribute \src "libresoc.v:165417.5-165417.29" switch \initial - attribute \src "libresoc.v:164109.9-164109.17" + attribute \src "libresoc.v:165417.9-165417.17" case 1'1 case end @@ -336574,19 +307944,19 @@ module \pipe$64 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$8934 \muxid$24 + assign $1\muxid$1$next[1:0]$8918 \muxid$24 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$8934 \muxid$24 + assign $1\muxid$1$next[1:0]$8918 \muxid$24 case - assign $1\muxid$1$next[1:0]$8934 \muxid$1 + assign $1\muxid$1$next[1:0]$8918 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$8933 + update \muxid$1$next $0\muxid$1$next[1:0]$8917 end - attribute \src "libresoc.v:164121.3-164136.6" - process $proc$libresoc.v:164121$8935 + attribute \src "libresoc.v:165429.3-165444.6" + process $proc$libresoc.v:165429$8919 assign { } { } assign { } { } assign { } { } @@ -336595,13 +307965,13 @@ module \pipe$64 assign { } { } assign { } { } assign { } { } - assign $0\spr_op__fn_unit$3$next[13:0]$8936 $1\spr_op__fn_unit$3$next[13:0]$8940 - assign $0\spr_op__insn$4$next[31:0]$8937 $1\spr_op__insn$4$next[31:0]$8941 - assign $0\spr_op__insn_type$2$next[6:0]$8938 $1\spr_op__insn_type$2$next[6:0]$8942 - assign $0\spr_op__is_32bit$5$next[0:0]$8939 $1\spr_op__is_32bit$5$next[0:0]$8943 - attribute \src "libresoc.v:164122.5-164122.29" + assign $0\spr_op__fn_unit$3$next[13:0]$8920 $1\spr_op__fn_unit$3$next[13:0]$8924 + assign $0\spr_op__insn$4$next[31:0]$8921 $1\spr_op__insn$4$next[31:0]$8925 + assign $0\spr_op__insn_type$2$next[6:0]$8922 $1\spr_op__insn_type$2$next[6:0]$8926 + assign $0\spr_op__is_32bit$5$next[0:0]$8923 $1\spr_op__is_32bit$5$next[0:0]$8927 + attribute \src "libresoc.v:165430.5-165430.29" switch \initial - attribute \src "libresoc.v:164122.9-164122.17" + attribute \src "libresoc.v:165430.9-165430.17" case 1'1 case end @@ -336613,38 +307983,38 @@ module \pipe$64 assign { } { } assign { } { } assign { } { } - assign { $1\spr_op__is_32bit$5$next[0:0]$8943 $1\spr_op__insn$4$next[31:0]$8941 $1\spr_op__fn_unit$3$next[13:0]$8940 $1\spr_op__insn_type$2$next[6:0]$8942 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } + assign { $1\spr_op__is_32bit$5$next[0:0]$8927 $1\spr_op__insn$4$next[31:0]$8925 $1\spr_op__fn_unit$3$next[13:0]$8924 $1\spr_op__insn_type$2$next[6:0]$8926 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } assign { } { } assign { } { } - assign { $1\spr_op__is_32bit$5$next[0:0]$8943 $1\spr_op__insn$4$next[31:0]$8941 $1\spr_op__fn_unit$3$next[13:0]$8940 $1\spr_op__insn_type$2$next[6:0]$8942 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } + assign { $1\spr_op__is_32bit$5$next[0:0]$8927 $1\spr_op__insn$4$next[31:0]$8925 $1\spr_op__fn_unit$3$next[13:0]$8924 $1\spr_op__insn_type$2$next[6:0]$8926 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } case - assign $1\spr_op__fn_unit$3$next[13:0]$8940 \spr_op__fn_unit$3 - assign $1\spr_op__insn$4$next[31:0]$8941 \spr_op__insn$4 - assign $1\spr_op__insn_type$2$next[6:0]$8942 \spr_op__insn_type$2 - assign $1\spr_op__is_32bit$5$next[0:0]$8943 \spr_op__is_32bit$5 + assign $1\spr_op__fn_unit$3$next[13:0]$8924 \spr_op__fn_unit$3 + assign $1\spr_op__insn$4$next[31:0]$8925 \spr_op__insn$4 + assign $1\spr_op__insn_type$2$next[6:0]$8926 \spr_op__insn_type$2 + assign $1\spr_op__is_32bit$5$next[0:0]$8927 \spr_op__is_32bit$5 end sync always - update \spr_op__fn_unit$3$next $0\spr_op__fn_unit$3$next[13:0]$8936 - update \spr_op__insn$4$next $0\spr_op__insn$4$next[31:0]$8937 - update \spr_op__insn_type$2$next $0\spr_op__insn_type$2$next[6:0]$8938 - update \spr_op__is_32bit$5$next $0\spr_op__is_32bit$5$next[0:0]$8939 + update \spr_op__fn_unit$3$next $0\spr_op__fn_unit$3$next[13:0]$8920 + update \spr_op__insn$4$next $0\spr_op__insn$4$next[31:0]$8921 + update \spr_op__insn_type$2$next $0\spr_op__insn_type$2$next[6:0]$8922 + update \spr_op__is_32bit$5$next $0\spr_op__is_32bit$5$next[0:0]$8923 end - attribute \src "libresoc.v:164137.3-164155.6" - process $proc$libresoc.v:164137$8944 + attribute \src "libresoc.v:165445.3-165463.6" + process $proc$libresoc.v:165445$8928 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$8945 $1\o$next[63:0]$8947 + assign $0\o$next[63:0]$8929 $1\o$next[63:0]$8931 assign { } { } - assign $0\o_ok$next[0:0]$8946 $2\o_ok$next[0:0]$8949 - attribute \src "libresoc.v:164138.5-164138.29" + assign $0\o_ok$next[0:0]$8930 $2\o_ok$next[0:0]$8933 + attribute \src "libresoc.v:165446.5-165446.29" switch \initial - attribute \src "libresoc.v:164138.9-164138.17" + attribute \src "libresoc.v:165446.9-165446.17" case 1'1 case end @@ -336654,41 +308024,41 @@ module \pipe$64 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$8948 $1\o$next[63:0]$8947 } { \o_ok$30 \o$29 } + assign { $1\o_ok$next[0:0]$8932 $1\o$next[63:0]$8931 } { \o_ok$30 \o$29 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$8948 $1\o$next[63:0]$8947 } { \o_ok$30 \o$29 } + assign { $1\o_ok$next[0:0]$8932 $1\o$next[63:0]$8931 } { \o_ok$30 \o$29 } case - assign $1\o$next[63:0]$8947 \o - assign $1\o_ok$next[0:0]$8948 \o_ok + assign $1\o$next[63:0]$8931 \o + assign $1\o_ok$next[0:0]$8932 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$8949 1'0 + assign $2\o_ok$next[0:0]$8933 1'0 case - assign $2\o_ok$next[0:0]$8949 $1\o_ok$next[0:0]$8948 + assign $2\o_ok$next[0:0]$8933 $1\o_ok$next[0:0]$8932 end sync always - update \o$next $0\o$next[63:0]$8945 - update \o_ok$next $0\o_ok$next[0:0]$8946 + update \o$next $0\o$next[63:0]$8929 + update \o_ok$next $0\o_ok$next[0:0]$8930 end - attribute \src "libresoc.v:164156.3-164174.6" - process $proc$libresoc.v:164156$8950 + attribute \src "libresoc.v:165464.3-165482.6" + process $proc$libresoc.v:165464$8934 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\spr1$6$next[63:0]$8951 $1\spr1$6$next[63:0]$8953 + assign $0\spr1$6$next[63:0]$8935 $1\spr1$6$next[63:0]$8937 assign { } { } - assign $0\spr1_ok$next[0:0]$8952 $2\spr1_ok$next[0:0]$8955 - attribute \src "libresoc.v:164157.5-164157.29" + assign $0\spr1_ok$next[0:0]$8936 $2\spr1_ok$next[0:0]$8939 + attribute \src "libresoc.v:165465.5-165465.29" switch \initial - attribute \src "libresoc.v:164157.9-164157.17" + attribute \src "libresoc.v:165465.9-165465.17" case 1'1 case end @@ -336698,41 +308068,41 @@ module \pipe$64 case 2'-1 assign { } { } assign { } { } - assign { $1\spr1_ok$next[0:0]$8954 $1\spr1$6$next[63:0]$8953 } { \spr1_ok$32 \spr1$31 } + assign { $1\spr1_ok$next[0:0]$8938 $1\spr1$6$next[63:0]$8937 } { \spr1_ok$32 \spr1$31 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\spr1_ok$next[0:0]$8954 $1\spr1$6$next[63:0]$8953 } { \spr1_ok$32 \spr1$31 } + assign { $1\spr1_ok$next[0:0]$8938 $1\spr1$6$next[63:0]$8937 } { \spr1_ok$32 \spr1$31 } case - assign $1\spr1$6$next[63:0]$8953 \spr1$6 - assign $1\spr1_ok$next[0:0]$8954 \spr1_ok + assign $1\spr1$6$next[63:0]$8937 \spr1$6 + assign $1\spr1_ok$next[0:0]$8938 \spr1_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\spr1_ok$next[0:0]$8955 1'0 + assign $2\spr1_ok$next[0:0]$8939 1'0 case - assign $2\spr1_ok$next[0:0]$8955 $1\spr1_ok$next[0:0]$8954 + assign $2\spr1_ok$next[0:0]$8939 $1\spr1_ok$next[0:0]$8938 end sync always - update \spr1$6$next $0\spr1$6$next[63:0]$8951 - update \spr1_ok$next $0\spr1_ok$next[0:0]$8952 + update \spr1$6$next $0\spr1$6$next[63:0]$8935 + update \spr1_ok$next $0\spr1_ok$next[0:0]$8936 end - attribute \src "libresoc.v:164175.3-164193.6" - process $proc$libresoc.v:164175$8956 + attribute \src "libresoc.v:165483.3-165501.6" + process $proc$libresoc.v:165483$8940 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\fast1$7$next[63:0]$8958 $1\fast1$7$next[63:0]$8960 - assign $0\fast1_ok$next[0:0]$8957 $2\fast1_ok$next[0:0]$8961 - attribute \src "libresoc.v:164176.5-164176.29" + assign $0\fast1$7$next[63:0]$8942 $1\fast1$7$next[63:0]$8944 + assign $0\fast1_ok$next[0:0]$8941 $2\fast1_ok$next[0:0]$8945 + attribute \src "libresoc.v:165484.5-165484.29" switch \initial - attribute \src "libresoc.v:164176.9-164176.17" + attribute \src "libresoc.v:165484.9-165484.17" case 1'1 case end @@ -336742,41 +308112,41 @@ module \pipe$64 case 2'-1 assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$8959 $1\fast1$7$next[63:0]$8960 } { \fast1_ok$34 \fast1$33 } + assign { $1\fast1_ok$next[0:0]$8943 $1\fast1$7$next[63:0]$8944 } { \fast1_ok$34 \fast1$33 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$8959 $1\fast1$7$next[63:0]$8960 } { \fast1_ok$34 \fast1$33 } + assign { $1\fast1_ok$next[0:0]$8943 $1\fast1$7$next[63:0]$8944 } { \fast1_ok$34 \fast1$33 } case - assign $1\fast1_ok$next[0:0]$8959 \fast1_ok - assign $1\fast1$7$next[63:0]$8960 \fast1$7 + assign $1\fast1_ok$next[0:0]$8943 \fast1_ok + assign $1\fast1$7$next[63:0]$8944 \fast1$7 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast1_ok$next[0:0]$8961 1'0 + assign $2\fast1_ok$next[0:0]$8945 1'0 case - assign $2\fast1_ok$next[0:0]$8961 $1\fast1_ok$next[0:0]$8959 + assign $2\fast1_ok$next[0:0]$8945 $1\fast1_ok$next[0:0]$8943 end sync always - update \fast1_ok$next $0\fast1_ok$next[0:0]$8957 - update \fast1$7$next $0\fast1$7$next[63:0]$8958 + update \fast1_ok$next $0\fast1_ok$next[0:0]$8941 + update \fast1$7$next $0\fast1$7$next[63:0]$8942 end - attribute \src "libresoc.v:164194.3-164212.6" - process $proc$libresoc.v:164194$8962 + attribute \src "libresoc.v:165502.3-165520.6" + process $proc$libresoc.v:165502$8946 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$8$next[0:0]$8964 $1\xer_so$8$next[0:0]$8966 - assign $0\xer_so_ok$next[0:0]$8963 $2\xer_so_ok$next[0:0]$8967 - attribute \src "libresoc.v:164195.5-164195.29" + assign $0\xer_so$8$next[0:0]$8948 $1\xer_so$8$next[0:0]$8950 + assign $0\xer_so_ok$next[0:0]$8947 $2\xer_so_ok$next[0:0]$8951 + attribute \src "libresoc.v:165503.5-165503.29" switch \initial - attribute \src "libresoc.v:164195.9-164195.17" + attribute \src "libresoc.v:165503.9-165503.17" case 1'1 case end @@ -336786,41 +308156,41 @@ module \pipe$64 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$8965 $1\xer_so$8$next[0:0]$8966 } { \xer_so_ok$36 \xer_so$35 } + assign { $1\xer_so_ok$next[0:0]$8949 $1\xer_so$8$next[0:0]$8950 } { \xer_so_ok$36 \xer_so$35 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$8965 $1\xer_so$8$next[0:0]$8966 } { \xer_so_ok$36 \xer_so$35 } + assign { $1\xer_so_ok$next[0:0]$8949 $1\xer_so$8$next[0:0]$8950 } { \xer_so_ok$36 \xer_so$35 } case - assign $1\xer_so_ok$next[0:0]$8965 \xer_so_ok - assign $1\xer_so$8$next[0:0]$8966 \xer_so$8 + assign $1\xer_so_ok$next[0:0]$8949 \xer_so_ok + assign $1\xer_so$8$next[0:0]$8950 \xer_so$8 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$8967 1'0 + assign $2\xer_so_ok$next[0:0]$8951 1'0 case - assign $2\xer_so_ok$next[0:0]$8967 $1\xer_so_ok$next[0:0]$8965 + assign $2\xer_so_ok$next[0:0]$8951 $1\xer_so_ok$next[0:0]$8949 end sync always - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8963 - update \xer_so$8$next $0\xer_so$8$next[0:0]$8964 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8947 + update \xer_so$8$next $0\xer_so$8$next[0:0]$8948 end - attribute \src "libresoc.v:164213.3-164231.6" - process $proc$libresoc.v:164213$8968 + attribute \src "libresoc.v:165521.3-165539.6" + process $proc$libresoc.v:165521$8952 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ov$9$next[1:0]$8970 $1\xer_ov$9$next[1:0]$8972 - assign $0\xer_ov_ok$next[0:0]$8969 $2\xer_ov_ok$next[0:0]$8973 - attribute \src "libresoc.v:164214.5-164214.29" + assign $0\xer_ov$9$next[1:0]$8954 $1\xer_ov$9$next[1:0]$8956 + assign $0\xer_ov_ok$next[0:0]$8953 $2\xer_ov_ok$next[0:0]$8957 + attribute \src "libresoc.v:165522.5-165522.29" switch \initial - attribute \src "libresoc.v:164214.9-164214.17" + attribute \src "libresoc.v:165522.9-165522.17" case 1'1 case end @@ -336830,41 +308200,41 @@ module \pipe$64 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8971 $1\xer_ov$9$next[1:0]$8972 } { \xer_ov_ok$38 \xer_ov$37 } + assign { $1\xer_ov_ok$next[0:0]$8955 $1\xer_ov$9$next[1:0]$8956 } { \xer_ov_ok$38 \xer_ov$37 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$8971 $1\xer_ov$9$next[1:0]$8972 } { \xer_ov_ok$38 \xer_ov$37 } + assign { $1\xer_ov_ok$next[0:0]$8955 $1\xer_ov$9$next[1:0]$8956 } { \xer_ov_ok$38 \xer_ov$37 } case - assign $1\xer_ov_ok$next[0:0]$8971 \xer_ov_ok - assign $1\xer_ov$9$next[1:0]$8972 \xer_ov$9 + assign $1\xer_ov_ok$next[0:0]$8955 \xer_ov_ok + assign $1\xer_ov$9$next[1:0]$8956 \xer_ov$9 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ov_ok$next[0:0]$8973 1'0 + assign $2\xer_ov_ok$next[0:0]$8957 1'0 case - assign $2\xer_ov_ok$next[0:0]$8973 $1\xer_ov_ok$next[0:0]$8971 + assign $2\xer_ov_ok$next[0:0]$8957 $1\xer_ov_ok$next[0:0]$8955 end sync always - update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8969 - update \xer_ov$9$next $0\xer_ov$9$next[1:0]$8970 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8953 + update \xer_ov$9$next $0\xer_ov$9$next[1:0]$8954 end - attribute \src "libresoc.v:164232.3-164250.6" - process $proc$libresoc.v:164232$8974 + attribute \src "libresoc.v:165540.3-165558.6" + process $proc$libresoc.v:165540$8958 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ca$10$next[1:0]$8975 $1\xer_ca$10$next[1:0]$8977 + assign $0\xer_ca$10$next[1:0]$8959 $1\xer_ca$10$next[1:0]$8961 assign { } { } - assign $0\xer_ca_ok$next[0:0]$8976 $2\xer_ca_ok$next[0:0]$8979 - attribute \src "libresoc.v:164233.5-164233.29" + assign $0\xer_ca_ok$next[0:0]$8960 $2\xer_ca_ok$next[0:0]$8963 + attribute \src "libresoc.v:165541.5-165541.29" switch \initial - attribute \src "libresoc.v:164233.9-164233.17" + attribute \src "libresoc.v:165541.9-165541.17" case 1'1 case end @@ -336874,30 +308244,30 @@ module \pipe$64 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ca_ok$next[0:0]$8978 $1\xer_ca$10$next[1:0]$8977 } { \xer_ca_ok$40 \xer_ca$39 } + assign { $1\xer_ca_ok$next[0:0]$8962 $1\xer_ca$10$next[1:0]$8961 } { \xer_ca_ok$40 \xer_ca$39 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ca_ok$next[0:0]$8978 $1\xer_ca$10$next[1:0]$8977 } { \xer_ca_ok$40 \xer_ca$39 } + assign { $1\xer_ca_ok$next[0:0]$8962 $1\xer_ca$10$next[1:0]$8961 } { \xer_ca_ok$40 \xer_ca$39 } case - assign $1\xer_ca$10$next[1:0]$8977 \xer_ca$10 - assign $1\xer_ca_ok$next[0:0]$8978 \xer_ca_ok + assign $1\xer_ca$10$next[1:0]$8961 \xer_ca$10 + assign $1\xer_ca_ok$next[0:0]$8962 \xer_ca_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ca_ok$next[0:0]$8979 1'0 + assign $2\xer_ca_ok$next[0:0]$8963 1'0 case - assign $2\xer_ca_ok$next[0:0]$8979 $1\xer_ca_ok$next[0:0]$8978 + assign $2\xer_ca_ok$next[0:0]$8963 $1\xer_ca_ok$next[0:0]$8962 end sync always - update \xer_ca$10$next $0\xer_ca$10$next[1:0]$8975 - update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8976 + update \xer_ca$10$next $0\xer_ca$10$next[1:0]$8959 + update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8960 end - connect \$22 $and$libresoc.v:164015$8899_Y + connect \$22 $and$libresoc.v:165323$8883_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \xer_ca_ok$40 \xer_ca$39 } { \spr_main_xer_ca_ok \spr_main_xer_ca$20 } @@ -336920,279 +308290,279 @@ module \pipe$64 connect { \spr_main_spr_op__is_32bit \spr_main_spr_op__insn \spr_main_spr_op__fn_unit \spr_main_spr_op__insn_type } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } connect \spr_main_muxid \muxid end -attribute \src "libresoc.v:164276.1-165768.10" +attribute \src "libresoc.v:165584.1-167076.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe1" attribute \generator "nMigen" module \pipe1 - attribute \src "libresoc.v:165682.3-165723.6" - wire width 4 $0\alu_op__data_len$next[3:0]$9072 - attribute \src "libresoc.v:165458.3-165459.49" + attribute \src "libresoc.v:166990.3-167031.6" + wire width 4 $0\alu_op__data_len$next[3:0]$9056 + attribute \src "libresoc.v:166766.3-166767.49" wire width 4 $0\alu_op__data_len[3:0] - attribute \src "libresoc.v:165682.3-165723.6" - wire width 14 $0\alu_op__fn_unit$next[13:0]$9073 - attribute \src "libresoc.v:165428.3-165429.47" + attribute \src "libresoc.v:166990.3-167031.6" + wire width 14 $0\alu_op__fn_unit$next[13:0]$9057 + attribute \src "libresoc.v:166736.3-166737.47" wire width 14 $0\alu_op__fn_unit[13:0] - attribute \src "libresoc.v:165682.3-165723.6" - wire width 64 $0\alu_op__imm_data__data$next[63:0]$9074 - attribute \src "libresoc.v:165430.3-165431.61" + attribute \src "libresoc.v:166990.3-167031.6" + wire width 64 $0\alu_op__imm_data__data$next[63:0]$9058 + attribute \src "libresoc.v:166738.3-166739.61" wire width 64 $0\alu_op__imm_data__data[63:0] - attribute \src "libresoc.v:165682.3-165723.6" - wire $0\alu_op__imm_data__ok$next[0:0]$9075 - attribute \src "libresoc.v:165432.3-165433.57" + attribute \src "libresoc.v:166990.3-167031.6" + wire $0\alu_op__imm_data__ok$next[0:0]$9059 + attribute \src "libresoc.v:166740.3-166741.57" wire $0\alu_op__imm_data__ok[0:0] - attribute \src "libresoc.v:165682.3-165723.6" - wire width 2 $0\alu_op__input_carry$next[1:0]$9076 - attribute \src "libresoc.v:165450.3-165451.55" + attribute \src "libresoc.v:166990.3-167031.6" + wire width 2 $0\alu_op__input_carry$next[1:0]$9060 + attribute \src "libresoc.v:166758.3-166759.55" wire width 2 $0\alu_op__input_carry[1:0] - attribute \src "libresoc.v:165682.3-165723.6" - wire width 32 $0\alu_op__insn$next[31:0]$9077 - attribute \src "libresoc.v:165460.3-165461.41" + attribute \src "libresoc.v:166990.3-167031.6" + wire width 32 $0\alu_op__insn$next[31:0]$9061 + attribute \src "libresoc.v:166768.3-166769.41" wire width 32 $0\alu_op__insn[31:0] - attribute \src "libresoc.v:165682.3-165723.6" - wire width 7 $0\alu_op__insn_type$next[6:0]$9078 - attribute \src "libresoc.v:165426.3-165427.51" + attribute \src "libresoc.v:166990.3-167031.6" + wire width 7 $0\alu_op__insn_type$next[6:0]$9062 + attribute \src "libresoc.v:166734.3-166735.51" wire width 7 $0\alu_op__insn_type[6:0] - attribute \src "libresoc.v:165682.3-165723.6" - wire $0\alu_op__invert_in$next[0:0]$9079 - attribute \src "libresoc.v:165442.3-165443.51" + attribute \src "libresoc.v:166990.3-167031.6" + wire $0\alu_op__invert_in$next[0:0]$9063 + attribute \src "libresoc.v:166750.3-166751.51" wire $0\alu_op__invert_in[0:0] - attribute \src "libresoc.v:165682.3-165723.6" - wire $0\alu_op__invert_out$next[0:0]$9080 - attribute \src "libresoc.v:165446.3-165447.53" + attribute \src "libresoc.v:166990.3-167031.6" + wire $0\alu_op__invert_out$next[0:0]$9064 + attribute \src "libresoc.v:166754.3-166755.53" wire $0\alu_op__invert_out[0:0] - attribute \src "libresoc.v:165682.3-165723.6" - wire $0\alu_op__is_32bit$next[0:0]$9081 - attribute \src "libresoc.v:165454.3-165455.49" + attribute \src "libresoc.v:166990.3-167031.6" + wire $0\alu_op__is_32bit$next[0:0]$9065 + attribute \src "libresoc.v:166762.3-166763.49" wire $0\alu_op__is_32bit[0:0] - attribute \src "libresoc.v:165682.3-165723.6" - wire $0\alu_op__is_signed$next[0:0]$9082 - attribute \src "libresoc.v:165456.3-165457.51" + attribute \src "libresoc.v:166990.3-167031.6" + wire $0\alu_op__is_signed$next[0:0]$9066 + attribute \src "libresoc.v:166764.3-166765.51" wire $0\alu_op__is_signed[0:0] - attribute \src "libresoc.v:165682.3-165723.6" - wire $0\alu_op__oe__oe$next[0:0]$9083 - attribute \src "libresoc.v:165438.3-165439.45" + attribute \src "libresoc.v:166990.3-167031.6" + wire $0\alu_op__oe__oe$next[0:0]$9067 + attribute \src "libresoc.v:166746.3-166747.45" wire $0\alu_op__oe__oe[0:0] - attribute \src "libresoc.v:165682.3-165723.6" - wire $0\alu_op__oe__ok$next[0:0]$9084 - attribute \src "libresoc.v:165440.3-165441.45" + attribute \src "libresoc.v:166990.3-167031.6" + wire $0\alu_op__oe__ok$next[0:0]$9068 + attribute \src "libresoc.v:166748.3-166749.45" wire $0\alu_op__oe__ok[0:0] - attribute \src "libresoc.v:165682.3-165723.6" - wire $0\alu_op__output_carry$next[0:0]$9085 - attribute \src "libresoc.v:165452.3-165453.57" + attribute \src "libresoc.v:166990.3-167031.6" + wire $0\alu_op__output_carry$next[0:0]$9069 + attribute \src "libresoc.v:166760.3-166761.57" wire $0\alu_op__output_carry[0:0] - attribute \src "libresoc.v:165682.3-165723.6" - wire $0\alu_op__rc__ok$next[0:0]$9086 - attribute \src "libresoc.v:165436.3-165437.45" + attribute \src "libresoc.v:166990.3-167031.6" + wire $0\alu_op__rc__ok$next[0:0]$9070 + attribute \src "libresoc.v:166744.3-166745.45" wire $0\alu_op__rc__ok[0:0] - attribute \src "libresoc.v:165682.3-165723.6" - wire $0\alu_op__rc__rc$next[0:0]$9087 - attribute \src "libresoc.v:165434.3-165435.45" + attribute \src "libresoc.v:166990.3-167031.6" + wire $0\alu_op__rc__rc$next[0:0]$9071 + attribute \src "libresoc.v:166742.3-166743.45" wire $0\alu_op__rc__rc[0:0] - attribute \src "libresoc.v:165682.3-165723.6" - wire $0\alu_op__write_cr0$next[0:0]$9088 - attribute \src "libresoc.v:165448.3-165449.51" + attribute \src "libresoc.v:166990.3-167031.6" + wire $0\alu_op__write_cr0$next[0:0]$9072 + attribute \src "libresoc.v:166756.3-166757.51" wire $0\alu_op__write_cr0[0:0] - attribute \src "libresoc.v:165682.3-165723.6" - wire $0\alu_op__zero_a$next[0:0]$9089 - attribute \src "libresoc.v:165444.3-165445.45" + attribute \src "libresoc.v:166990.3-167031.6" + wire $0\alu_op__zero_a$next[0:0]$9073 + attribute \src "libresoc.v:166752.3-166753.45" wire $0\alu_op__zero_a[0:0] - attribute \src "libresoc.v:165575.3-165593.6" - wire width 4 $0\cr_a$next[3:0]$9041 - attribute \src "libresoc.v:165418.3-165419.25" + attribute \src "libresoc.v:166883.3-166901.6" + wire width 4 $0\cr_a$next[3:0]$9025 + attribute \src "libresoc.v:166726.3-166727.25" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:165575.3-165593.6" - wire $0\cr_a_ok$next[0:0]$9042 - attribute \src "libresoc.v:165420.3-165421.31" + attribute \src "libresoc.v:166883.3-166901.6" + wire $0\cr_a_ok$next[0:0]$9026 + attribute \src "libresoc.v:166728.3-166729.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:164277.7-164277.20" + attribute \src "libresoc.v:165585.7-165585.20" wire $0\initial[0:0] - attribute \src "libresoc.v:165669.3-165681.6" - wire width 2 $0\muxid$next[1:0]$9069 - attribute \src "libresoc.v:165462.3-165463.27" + attribute \src "libresoc.v:166977.3-166989.6" + wire width 2 $0\muxid$next[1:0]$9053 + attribute \src "libresoc.v:166770.3-166771.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:165724.3-165742.6" - wire width 64 $0\o$next[63:0]$9115 - attribute \src "libresoc.v:165422.3-165423.19" + attribute \src "libresoc.v:167032.3-167050.6" + wire width 64 $0\o$next[63:0]$9099 + attribute \src "libresoc.v:166730.3-166731.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:165724.3-165742.6" - wire $0\o_ok$next[0:0]$9116 - attribute \src "libresoc.v:165424.3-165425.25" + attribute \src "libresoc.v:167032.3-167050.6" + wire $0\o_ok$next[0:0]$9100 + attribute \src "libresoc.v:166732.3-166733.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:165651.3-165668.6" - wire $0\r_busy$next[0:0]$9065 - attribute \src "libresoc.v:165464.3-165465.29" + attribute \src "libresoc.v:166959.3-166976.6" + wire $0\r_busy$next[0:0]$9049 + attribute \src "libresoc.v:166772.3-166773.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:165594.3-165612.6" - wire width 2 $0\xer_ca$next[1:0]$9048 - attribute \src "libresoc.v:165414.3-165415.29" + attribute \src "libresoc.v:166902.3-166920.6" + wire width 2 $0\xer_ca$next[1:0]$9032 + attribute \src "libresoc.v:166722.3-166723.29" wire width 2 $0\xer_ca[1:0] - attribute \src "libresoc.v:165594.3-165612.6" - wire $0\xer_ca_ok$next[0:0]$9047 - attribute \src "libresoc.v:165416.3-165417.35" + attribute \src "libresoc.v:166902.3-166920.6" + wire $0\xer_ca_ok$next[0:0]$9031 + attribute \src "libresoc.v:166724.3-166725.35" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:165613.3-165631.6" - wire width 2 $0\xer_ov$next[1:0]$9053 - attribute \src "libresoc.v:165410.3-165411.29" + attribute \src "libresoc.v:166921.3-166939.6" + wire width 2 $0\xer_ov$next[1:0]$9037 + attribute \src "libresoc.v:166718.3-166719.29" wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:165613.3-165631.6" - wire $0\xer_ov_ok$next[0:0]$9054 - attribute \src "libresoc.v:165412.3-165413.35" + attribute \src "libresoc.v:166921.3-166939.6" + wire $0\xer_ov_ok$next[0:0]$9038 + attribute \src "libresoc.v:166720.3-166721.35" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:165632.3-165650.6" - wire $0\xer_so$next[0:0]$9059 - attribute \src "libresoc.v:165406.3-165407.29" + attribute \src "libresoc.v:166940.3-166958.6" + wire $0\xer_so$next[0:0]$9043 + attribute \src "libresoc.v:166714.3-166715.29" wire $0\xer_so[0:0] - attribute \src "libresoc.v:165632.3-165650.6" - wire $0\xer_so_ok$next[0:0]$9060 - attribute \src "libresoc.v:165408.3-165409.35" + attribute \src "libresoc.v:166940.3-166958.6" + wire $0\xer_so_ok$next[0:0]$9044 + attribute \src "libresoc.v:166716.3-166717.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:165682.3-165723.6" - wire width 4 $1\alu_op__data_len$next[3:0]$9090 - attribute \src "libresoc.v:164282.13-164282.36" + attribute \src "libresoc.v:166990.3-167031.6" + wire width 4 $1\alu_op__data_len$next[3:0]$9074 + attribute \src "libresoc.v:165590.13-165590.36" wire width 4 $1\alu_op__data_len[3:0] - attribute \src "libresoc.v:165682.3-165723.6" - wire width 14 $1\alu_op__fn_unit$next[13:0]$9091 - attribute \src "libresoc.v:164306.14-164306.40" + attribute \src "libresoc.v:166990.3-167031.6" + wire width 14 $1\alu_op__fn_unit$next[13:0]$9075 + attribute \src "libresoc.v:165614.14-165614.40" wire width 14 $1\alu_op__fn_unit[13:0] - attribute \src "libresoc.v:165682.3-165723.6" - wire width 64 $1\alu_op__imm_data__data$next[63:0]$9092 - attribute \src "libresoc.v:164345.14-164345.59" + attribute \src "libresoc.v:166990.3-167031.6" + wire width 64 $1\alu_op__imm_data__data$next[63:0]$9076 + attribute \src "libresoc.v:165653.14-165653.59" wire width 64 $1\alu_op__imm_data__data[63:0] - attribute \src "libresoc.v:165682.3-165723.6" - wire $1\alu_op__imm_data__ok$next[0:0]$9093 - attribute \src "libresoc.v:164354.7-164354.34" + attribute \src "libresoc.v:166990.3-167031.6" + wire $1\alu_op__imm_data__ok$next[0:0]$9077 + attribute \src "libresoc.v:165662.7-165662.34" wire $1\alu_op__imm_data__ok[0:0] - attribute \src "libresoc.v:165682.3-165723.6" - wire width 2 $1\alu_op__input_carry$next[1:0]$9094 - attribute \src "libresoc.v:164367.13-164367.39" + attribute \src "libresoc.v:166990.3-167031.6" + wire width 2 $1\alu_op__input_carry$next[1:0]$9078 + attribute \src "libresoc.v:165675.13-165675.39" wire width 2 $1\alu_op__input_carry[1:0] - attribute \src "libresoc.v:165682.3-165723.6" - wire width 32 $1\alu_op__insn$next[31:0]$9095 - attribute \src "libresoc.v:164384.14-164384.34" + attribute \src "libresoc.v:166990.3-167031.6" + wire width 32 $1\alu_op__insn$next[31:0]$9079 + attribute \src "libresoc.v:165692.14-165692.34" wire width 32 $1\alu_op__insn[31:0] - attribute \src "libresoc.v:165682.3-165723.6" - wire width 7 $1\alu_op__insn_type$next[6:0]$9096 - attribute \src "libresoc.v:164468.13-164468.38" + attribute \src "libresoc.v:166990.3-167031.6" + wire width 7 $1\alu_op__insn_type$next[6:0]$9080 + attribute \src "libresoc.v:165776.13-165776.38" wire width 7 $1\alu_op__insn_type[6:0] - attribute \src "libresoc.v:165682.3-165723.6" - wire $1\alu_op__invert_in$next[0:0]$9097 - attribute \src "libresoc.v:164627.7-164627.31" + attribute \src "libresoc.v:166990.3-167031.6" + wire $1\alu_op__invert_in$next[0:0]$9081 + attribute \src "libresoc.v:165935.7-165935.31" wire $1\alu_op__invert_in[0:0] - attribute \src "libresoc.v:165682.3-165723.6" - wire $1\alu_op__invert_out$next[0:0]$9098 - attribute \src "libresoc.v:164636.7-164636.32" + attribute \src "libresoc.v:166990.3-167031.6" + wire $1\alu_op__invert_out$next[0:0]$9082 + attribute \src "libresoc.v:165944.7-165944.32" wire $1\alu_op__invert_out[0:0] - attribute \src "libresoc.v:165682.3-165723.6" - wire $1\alu_op__is_32bit$next[0:0]$9099 - attribute \src "libresoc.v:164645.7-164645.30" + attribute \src "libresoc.v:166990.3-167031.6" + wire $1\alu_op__is_32bit$next[0:0]$9083 + attribute \src "libresoc.v:165953.7-165953.30" wire $1\alu_op__is_32bit[0:0] - attribute \src "libresoc.v:165682.3-165723.6" - wire $1\alu_op__is_signed$next[0:0]$9100 - attribute \src "libresoc.v:164654.7-164654.31" + attribute \src "libresoc.v:166990.3-167031.6" + wire $1\alu_op__is_signed$next[0:0]$9084 + attribute \src "libresoc.v:165962.7-165962.31" wire $1\alu_op__is_signed[0:0] - attribute \src "libresoc.v:165682.3-165723.6" - wire $1\alu_op__oe__oe$next[0:0]$9101 - attribute \src "libresoc.v:164663.7-164663.28" + attribute \src "libresoc.v:166990.3-167031.6" + wire $1\alu_op__oe__oe$next[0:0]$9085 + attribute \src "libresoc.v:165971.7-165971.28" wire $1\alu_op__oe__oe[0:0] - attribute \src "libresoc.v:165682.3-165723.6" - wire $1\alu_op__oe__ok$next[0:0]$9102 - attribute \src "libresoc.v:164672.7-164672.28" + attribute \src "libresoc.v:166990.3-167031.6" + wire $1\alu_op__oe__ok$next[0:0]$9086 + attribute \src "libresoc.v:165980.7-165980.28" wire $1\alu_op__oe__ok[0:0] - attribute \src "libresoc.v:165682.3-165723.6" - wire $1\alu_op__output_carry$next[0:0]$9103 - attribute \src "libresoc.v:164681.7-164681.34" + attribute \src "libresoc.v:166990.3-167031.6" + wire $1\alu_op__output_carry$next[0:0]$9087 + attribute \src "libresoc.v:165989.7-165989.34" wire $1\alu_op__output_carry[0:0] - attribute \src "libresoc.v:165682.3-165723.6" - wire $1\alu_op__rc__ok$next[0:0]$9104 - attribute \src "libresoc.v:164690.7-164690.28" + attribute \src "libresoc.v:166990.3-167031.6" + wire $1\alu_op__rc__ok$next[0:0]$9088 + attribute \src "libresoc.v:165998.7-165998.28" wire $1\alu_op__rc__ok[0:0] - attribute \src "libresoc.v:165682.3-165723.6" - wire $1\alu_op__rc__rc$next[0:0]$9105 - attribute \src "libresoc.v:164699.7-164699.28" + attribute \src "libresoc.v:166990.3-167031.6" + wire $1\alu_op__rc__rc$next[0:0]$9089 + attribute \src "libresoc.v:166007.7-166007.28" wire $1\alu_op__rc__rc[0:0] - attribute \src "libresoc.v:165682.3-165723.6" - wire $1\alu_op__write_cr0$next[0:0]$9106 - attribute \src "libresoc.v:164708.7-164708.31" + attribute \src "libresoc.v:166990.3-167031.6" + wire $1\alu_op__write_cr0$next[0:0]$9090 + attribute \src "libresoc.v:166016.7-166016.31" wire $1\alu_op__write_cr0[0:0] - attribute \src "libresoc.v:165682.3-165723.6" - wire $1\alu_op__zero_a$next[0:0]$9107 - attribute \src "libresoc.v:164717.7-164717.28" + attribute \src "libresoc.v:166990.3-167031.6" + wire $1\alu_op__zero_a$next[0:0]$9091 + attribute \src "libresoc.v:166025.7-166025.28" wire $1\alu_op__zero_a[0:0] - attribute \src "libresoc.v:165575.3-165593.6" - wire width 4 $1\cr_a$next[3:0]$9043 - attribute \src "libresoc.v:164730.13-164730.24" + attribute \src "libresoc.v:166883.3-166901.6" + wire width 4 $1\cr_a$next[3:0]$9027 + attribute \src "libresoc.v:166038.13-166038.24" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:165575.3-165593.6" - wire $1\cr_a_ok$next[0:0]$9044 - attribute \src "libresoc.v:164737.7-164737.21" + attribute \src "libresoc.v:166883.3-166901.6" + wire $1\cr_a_ok$next[0:0]$9028 + attribute \src "libresoc.v:166045.7-166045.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:165669.3-165681.6" - wire width 2 $1\muxid$next[1:0]$9070 - attribute \src "libresoc.v:165314.13-165314.25" + attribute \src "libresoc.v:166977.3-166989.6" + wire width 2 $1\muxid$next[1:0]$9054 + attribute \src "libresoc.v:166622.13-166622.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:165724.3-165742.6" - wire width 64 $1\o$next[63:0]$9117 - attribute \src "libresoc.v:165329.14-165329.38" + attribute \src "libresoc.v:167032.3-167050.6" + wire width 64 $1\o$next[63:0]$9101 + attribute \src "libresoc.v:166637.14-166637.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:165724.3-165742.6" - wire $1\o_ok$next[0:0]$9118 - attribute \src "libresoc.v:165336.7-165336.18" + attribute \src "libresoc.v:167032.3-167050.6" + wire $1\o_ok$next[0:0]$9102 + attribute \src "libresoc.v:166644.7-166644.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:165651.3-165668.6" - wire $1\r_busy$next[0:0]$9066 - attribute \src "libresoc.v:165350.7-165350.20" + attribute \src "libresoc.v:166959.3-166976.6" + wire $1\r_busy$next[0:0]$9050 + attribute \src "libresoc.v:166658.7-166658.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:165594.3-165612.6" - wire width 2 $1\xer_ca$next[1:0]$9050 - attribute \src "libresoc.v:165359.13-165359.26" + attribute \src "libresoc.v:166902.3-166920.6" + wire width 2 $1\xer_ca$next[1:0]$9034 + attribute \src "libresoc.v:166667.13-166667.26" wire width 2 $1\xer_ca[1:0] - attribute \src "libresoc.v:165594.3-165612.6" - wire $1\xer_ca_ok$next[0:0]$9049 - attribute \src "libresoc.v:165368.7-165368.23" + attribute \src "libresoc.v:166902.3-166920.6" + wire $1\xer_ca_ok$next[0:0]$9033 + attribute \src "libresoc.v:166676.7-166676.23" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:165613.3-165631.6" - wire width 2 $1\xer_ov$next[1:0]$9055 - attribute \src "libresoc.v:165375.13-165375.26" + attribute \src "libresoc.v:166921.3-166939.6" + wire width 2 $1\xer_ov$next[1:0]$9039 + attribute \src "libresoc.v:166683.13-166683.26" wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:165613.3-165631.6" - wire $1\xer_ov_ok$next[0:0]$9056 - attribute \src "libresoc.v:165382.7-165382.23" + attribute \src "libresoc.v:166921.3-166939.6" + wire $1\xer_ov_ok$next[0:0]$9040 + attribute \src "libresoc.v:166690.7-166690.23" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:165632.3-165650.6" - wire $1\xer_so$next[0:0]$9061 - attribute \src "libresoc.v:165389.7-165389.20" + attribute \src "libresoc.v:166940.3-166958.6" + wire $1\xer_so$next[0:0]$9045 + attribute \src "libresoc.v:166697.7-166697.20" wire $1\xer_so[0:0] - attribute \src "libresoc.v:165632.3-165650.6" - wire $1\xer_so_ok$next[0:0]$9062 - attribute \src "libresoc.v:165398.7-165398.23" + attribute \src "libresoc.v:166940.3-166958.6" + wire $1\xer_so_ok$next[0:0]$9046 + attribute \src "libresoc.v:166706.7-166706.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:165682.3-165723.6" - wire width 64 $2\alu_op__imm_data__data$next[63:0]$9108 - attribute \src "libresoc.v:165682.3-165723.6" - wire $2\alu_op__imm_data__ok$next[0:0]$9109 - attribute \src "libresoc.v:165682.3-165723.6" - wire $2\alu_op__oe__oe$next[0:0]$9110 - attribute \src "libresoc.v:165682.3-165723.6" - wire $2\alu_op__oe__ok$next[0:0]$9111 - attribute \src "libresoc.v:165682.3-165723.6" - wire $2\alu_op__rc__ok$next[0:0]$9112 - attribute \src "libresoc.v:165682.3-165723.6" - wire $2\alu_op__rc__rc$next[0:0]$9113 - attribute \src "libresoc.v:165575.3-165593.6" - wire $2\cr_a_ok$next[0:0]$9045 - attribute \src "libresoc.v:165724.3-165742.6" - wire $2\o_ok$next[0:0]$9119 - attribute \src "libresoc.v:165651.3-165668.6" - wire $2\r_busy$next[0:0]$9067 - attribute \src "libresoc.v:165594.3-165612.6" - wire $2\xer_ca_ok$next[0:0]$9051 - attribute \src "libresoc.v:165613.3-165631.6" - wire $2\xer_ov_ok$next[0:0]$9057 - attribute \src "libresoc.v:165632.3-165650.6" - wire $2\xer_so_ok$next[0:0]$9063 - attribute \src "libresoc.v:165405.18-165405.118" - wire $and$libresoc.v:165405$9009_Y + attribute \src "libresoc.v:166990.3-167031.6" + wire width 64 $2\alu_op__imm_data__data$next[63:0]$9092 + attribute \src "libresoc.v:166990.3-167031.6" + wire $2\alu_op__imm_data__ok$next[0:0]$9093 + attribute \src "libresoc.v:166990.3-167031.6" + wire $2\alu_op__oe__oe$next[0:0]$9094 + attribute \src "libresoc.v:166990.3-167031.6" + wire $2\alu_op__oe__ok$next[0:0]$9095 + attribute \src "libresoc.v:166990.3-167031.6" + wire $2\alu_op__rc__ok$next[0:0]$9096 + attribute \src "libresoc.v:166990.3-167031.6" + wire $2\alu_op__rc__rc$next[0:0]$9097 + attribute \src "libresoc.v:166883.3-166901.6" + wire $2\cr_a_ok$next[0:0]$9029 + attribute \src "libresoc.v:167032.3-167050.6" + wire $2\o_ok$next[0:0]$9103 + attribute \src "libresoc.v:166959.3-166976.6" + wire $2\r_busy$next[0:0]$9051 + attribute \src "libresoc.v:166902.3-166920.6" + wire $2\xer_ca_ok$next[0:0]$9035 + attribute \src "libresoc.v:166921.3-166939.6" + wire $2\xer_ov_ok$next[0:0]$9041 + attribute \src "libresoc.v:166940.3-166958.6" + wire $2\xer_so_ok$next[0:0]$9047 + attribute \src "libresoc.v:166713.18-166713.118" + wire $and$libresoc.v:166713$8993_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$67 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -337621,9 +308991,9 @@ module \pipe1 wire \alu_op__zero_a$79 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__zero_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 58 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 25 \cr_a @@ -337637,7 +309007,7 @@ module \pipe1 wire \cr_a_ok$91 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$next - attribute \src "libresoc.v:164277.7-164277.15" + attribute \src "libresoc.v:165585.7-165585.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \input_alu_op__data_len @@ -338294,7 +309664,7 @@ module \pipe1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:165405$9009 + cell $and $and$libresoc.v:166713$8993 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -338302,10 +309672,10 @@ module \pipe1 parameter \Y_WIDTH 1 connect \A \p_valid_i$66 connect \B \p_ready_o - connect \Y $and$libresoc.v:165405$9009_Y + connect \Y $and$libresoc.v:166713$8993_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:165466.11-165513.4" + attribute \src "libresoc.v:166774.11-166821.4" cell \input \input connect \alu_op__data_len \input_alu_op__data_len connect \alu_op__data_len$18 \input_alu_op__data_len$39 @@ -338355,7 +309725,7 @@ module \pipe1 connect \xer_so$22 \input_xer_so$43 end attribute \module_not_derived 1 - attribute \src "libresoc.v:165514.8-165566.4" + attribute \src "libresoc.v:166822.8-166874.4" cell \main \main connect \alu_op__data_len \main_alu_op__data_len connect \alu_op__data_len$18 \main_alu_op__data_len$62 @@ -338410,487 +309780,487 @@ module \pipe1 connect \xer_so$21 \main_xer_so$65 end attribute \module_not_derived 1 - attribute \src "libresoc.v:165567.9-165570.4" + attribute \src "libresoc.v:166875.9-166878.4" cell \n$2 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:165571.9-165574.4" + attribute \src "libresoc.v:166879.9-166882.4" cell \p$1 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:164277.7-164277.20" - process $proc$libresoc.v:164277$9120 + attribute \src "libresoc.v:165585.7-165585.20" + process $proc$libresoc.v:165585$9104 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:164282.13-164282.36" - process $proc$libresoc.v:164282$9121 + attribute \src "libresoc.v:165590.13-165590.36" + process $proc$libresoc.v:165590$9105 assign { } { } assign $1\alu_op__data_len[3:0] 4'0000 sync always sync init update \alu_op__data_len $1\alu_op__data_len[3:0] end - attribute \src "libresoc.v:164306.14-164306.40" - process $proc$libresoc.v:164306$9122 + attribute \src "libresoc.v:165614.14-165614.40" + process $proc$libresoc.v:165614$9106 assign { } { } assign $1\alu_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_op__fn_unit $1\alu_op__fn_unit[13:0] end - attribute \src "libresoc.v:164345.14-164345.59" - process $proc$libresoc.v:164345$9123 + attribute \src "libresoc.v:165653.14-165653.59" + process $proc$libresoc.v:165653$9107 assign { } { } assign $1\alu_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_op__imm_data__data $1\alu_op__imm_data__data[63:0] end - attribute \src "libresoc.v:164354.7-164354.34" - process $proc$libresoc.v:164354$9124 + attribute \src "libresoc.v:165662.7-165662.34" + process $proc$libresoc.v:165662$9108 assign { } { } assign $1\alu_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_op__imm_data__ok $1\alu_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:164367.13-164367.39" - process $proc$libresoc.v:164367$9125 + attribute \src "libresoc.v:165675.13-165675.39" + process $proc$libresoc.v:165675$9109 assign { } { } assign $1\alu_op__input_carry[1:0] 2'00 sync always sync init update \alu_op__input_carry $1\alu_op__input_carry[1:0] end - attribute \src "libresoc.v:164384.14-164384.34" - process $proc$libresoc.v:164384$9126 + attribute \src "libresoc.v:165692.14-165692.34" + process $proc$libresoc.v:165692$9110 assign { } { } assign $1\alu_op__insn[31:0] 0 sync always sync init update \alu_op__insn $1\alu_op__insn[31:0] end - attribute \src "libresoc.v:164468.13-164468.38" - process $proc$libresoc.v:164468$9127 + attribute \src "libresoc.v:165776.13-165776.38" + process $proc$libresoc.v:165776$9111 assign { } { } assign $1\alu_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_op__insn_type $1\alu_op__insn_type[6:0] end - attribute \src "libresoc.v:164627.7-164627.31" - process $proc$libresoc.v:164627$9128 + attribute \src "libresoc.v:165935.7-165935.31" + process $proc$libresoc.v:165935$9112 assign { } { } assign $1\alu_op__invert_in[0:0] 1'0 sync always sync init update \alu_op__invert_in $1\alu_op__invert_in[0:0] end - attribute \src "libresoc.v:164636.7-164636.32" - process $proc$libresoc.v:164636$9129 + attribute \src "libresoc.v:165944.7-165944.32" + process $proc$libresoc.v:165944$9113 assign { } { } assign $1\alu_op__invert_out[0:0] 1'0 sync always sync init update \alu_op__invert_out $1\alu_op__invert_out[0:0] end - attribute \src "libresoc.v:164645.7-164645.30" - process $proc$libresoc.v:164645$9130 + attribute \src "libresoc.v:165953.7-165953.30" + process $proc$libresoc.v:165953$9114 assign { } { } assign $1\alu_op__is_32bit[0:0] 1'0 sync always sync init update \alu_op__is_32bit $1\alu_op__is_32bit[0:0] end - attribute \src "libresoc.v:164654.7-164654.31" - process $proc$libresoc.v:164654$9131 + attribute \src "libresoc.v:165962.7-165962.31" + process $proc$libresoc.v:165962$9115 assign { } { } assign $1\alu_op__is_signed[0:0] 1'0 sync always sync init update \alu_op__is_signed $1\alu_op__is_signed[0:0] end - attribute \src "libresoc.v:164663.7-164663.28" - process $proc$libresoc.v:164663$9132 + attribute \src "libresoc.v:165971.7-165971.28" + process $proc$libresoc.v:165971$9116 assign { } { } assign $1\alu_op__oe__oe[0:0] 1'0 sync always sync init update \alu_op__oe__oe $1\alu_op__oe__oe[0:0] end - attribute \src "libresoc.v:164672.7-164672.28" - process $proc$libresoc.v:164672$9133 + attribute \src "libresoc.v:165980.7-165980.28" + process $proc$libresoc.v:165980$9117 assign { } { } assign $1\alu_op__oe__ok[0:0] 1'0 sync always sync init update \alu_op__oe__ok $1\alu_op__oe__ok[0:0] end - attribute \src "libresoc.v:164681.7-164681.34" - process $proc$libresoc.v:164681$9134 + attribute \src "libresoc.v:165989.7-165989.34" + process $proc$libresoc.v:165989$9118 assign { } { } assign $1\alu_op__output_carry[0:0] 1'0 sync always sync init update \alu_op__output_carry $1\alu_op__output_carry[0:0] end - attribute \src "libresoc.v:164690.7-164690.28" - process $proc$libresoc.v:164690$9135 + attribute \src "libresoc.v:165998.7-165998.28" + process $proc$libresoc.v:165998$9119 assign { } { } assign $1\alu_op__rc__ok[0:0] 1'0 sync always sync init update \alu_op__rc__ok $1\alu_op__rc__ok[0:0] end - attribute \src "libresoc.v:164699.7-164699.28" - process $proc$libresoc.v:164699$9136 + attribute \src "libresoc.v:166007.7-166007.28" + process $proc$libresoc.v:166007$9120 assign { } { } assign $1\alu_op__rc__rc[0:0] 1'0 sync always sync init update \alu_op__rc__rc $1\alu_op__rc__rc[0:0] end - attribute \src "libresoc.v:164708.7-164708.31" - process $proc$libresoc.v:164708$9137 + attribute \src "libresoc.v:166016.7-166016.31" + process $proc$libresoc.v:166016$9121 assign { } { } assign $1\alu_op__write_cr0[0:0] 1'0 sync always sync init update \alu_op__write_cr0 $1\alu_op__write_cr0[0:0] end - attribute \src "libresoc.v:164717.7-164717.28" - process $proc$libresoc.v:164717$9138 + attribute \src "libresoc.v:166025.7-166025.28" + process $proc$libresoc.v:166025$9122 assign { } { } assign $1\alu_op__zero_a[0:0] 1'0 sync always sync init update \alu_op__zero_a $1\alu_op__zero_a[0:0] end - attribute \src "libresoc.v:164730.13-164730.24" - process $proc$libresoc.v:164730$9139 + attribute \src "libresoc.v:166038.13-166038.24" + process $proc$libresoc.v:166038$9123 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:164737.7-164737.21" - process $proc$libresoc.v:164737$9140 + attribute \src "libresoc.v:166045.7-166045.21" + process $proc$libresoc.v:166045$9124 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:165314.13-165314.25" - process $proc$libresoc.v:165314$9141 + attribute \src "libresoc.v:166622.13-166622.25" + process $proc$libresoc.v:166622$9125 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:165329.14-165329.38" - process $proc$libresoc.v:165329$9142 + attribute \src "libresoc.v:166637.14-166637.38" + process $proc$libresoc.v:166637$9126 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:165336.7-165336.18" - process $proc$libresoc.v:165336$9143 + attribute \src "libresoc.v:166644.7-166644.18" + process $proc$libresoc.v:166644$9127 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:165350.7-165350.20" - process $proc$libresoc.v:165350$9144 + attribute \src "libresoc.v:166658.7-166658.20" + process $proc$libresoc.v:166658$9128 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:165359.13-165359.26" - process $proc$libresoc.v:165359$9145 + attribute \src "libresoc.v:166667.13-166667.26" + process $proc$libresoc.v:166667$9129 assign { } { } assign $1\xer_ca[1:0] 2'00 sync always sync init update \xer_ca $1\xer_ca[1:0] end - attribute \src "libresoc.v:165368.7-165368.23" - process $proc$libresoc.v:165368$9146 + attribute \src "libresoc.v:166676.7-166676.23" + process $proc$libresoc.v:166676$9130 assign { } { } assign $1\xer_ca_ok[0:0] 1'0 sync always sync init update \xer_ca_ok $1\xer_ca_ok[0:0] end - attribute \src "libresoc.v:165375.13-165375.26" - process $proc$libresoc.v:165375$9147 + attribute \src "libresoc.v:166683.13-166683.26" + process $proc$libresoc.v:166683$9131 assign { } { } assign $1\xer_ov[1:0] 2'00 sync always sync init update \xer_ov $1\xer_ov[1:0] end - attribute \src "libresoc.v:165382.7-165382.23" - process $proc$libresoc.v:165382$9148 + attribute \src "libresoc.v:166690.7-166690.23" + process $proc$libresoc.v:166690$9132 assign { } { } assign $1\xer_ov_ok[0:0] 1'0 sync always sync init update \xer_ov_ok $1\xer_ov_ok[0:0] end - attribute \src "libresoc.v:165389.7-165389.20" - process $proc$libresoc.v:165389$9149 + attribute \src "libresoc.v:166697.7-166697.20" + process $proc$libresoc.v:166697$9133 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:165398.7-165398.23" - process $proc$libresoc.v:165398$9150 + attribute \src "libresoc.v:166706.7-166706.23" + process $proc$libresoc.v:166706$9134 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:165406.3-165407.29" - process $proc$libresoc.v:165406$9010 + attribute \src "libresoc.v:166714.3-166715.29" + process $proc$libresoc.v:166714$8994 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:165408.3-165409.35" - process $proc$libresoc.v:165408$9011 + attribute \src "libresoc.v:166716.3-166717.35" + process $proc$libresoc.v:166716$8995 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:165410.3-165411.29" - process $proc$libresoc.v:165410$9012 + attribute \src "libresoc.v:166718.3-166719.29" + process $proc$libresoc.v:166718$8996 assign { } { } assign $0\xer_ov[1:0] \xer_ov$next sync posedge \coresync_clk update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:165412.3-165413.35" - process $proc$libresoc.v:165412$9013 + attribute \src "libresoc.v:166720.3-166721.35" + process $proc$libresoc.v:166720$8997 assign { } { } assign $0\xer_ov_ok[0:0] \xer_ov_ok$next sync posedge \coresync_clk update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:165414.3-165415.29" - process $proc$libresoc.v:165414$9014 + attribute \src "libresoc.v:166722.3-166723.29" + process $proc$libresoc.v:166722$8998 assign { } { } assign $0\xer_ca[1:0] \xer_ca$next sync posedge \coresync_clk update \xer_ca $0\xer_ca[1:0] end - attribute \src "libresoc.v:165416.3-165417.35" - process $proc$libresoc.v:165416$9015 + attribute \src "libresoc.v:166724.3-166725.35" + process $proc$libresoc.v:166724$8999 assign { } { } assign $0\xer_ca_ok[0:0] \xer_ca_ok$next sync posedge \coresync_clk update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:165418.3-165419.25" - process $proc$libresoc.v:165418$9016 + attribute \src "libresoc.v:166726.3-166727.25" + process $proc$libresoc.v:166726$9000 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:165420.3-165421.31" - process $proc$libresoc.v:165420$9017 + attribute \src "libresoc.v:166728.3-166729.31" + process $proc$libresoc.v:166728$9001 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:165422.3-165423.19" - process $proc$libresoc.v:165422$9018 + attribute \src "libresoc.v:166730.3-166731.19" + process $proc$libresoc.v:166730$9002 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:165424.3-165425.25" - process $proc$libresoc.v:165424$9019 + attribute \src "libresoc.v:166732.3-166733.25" + process $proc$libresoc.v:166732$9003 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:165426.3-165427.51" - process $proc$libresoc.v:165426$9020 + attribute \src "libresoc.v:166734.3-166735.51" + process $proc$libresoc.v:166734$9004 assign { } { } assign $0\alu_op__insn_type[6:0] \alu_op__insn_type$next sync posedge \coresync_clk update \alu_op__insn_type $0\alu_op__insn_type[6:0] end - attribute \src "libresoc.v:165428.3-165429.47" - process $proc$libresoc.v:165428$9021 + attribute \src "libresoc.v:166736.3-166737.47" + process $proc$libresoc.v:166736$9005 assign { } { } assign $0\alu_op__fn_unit[13:0] \alu_op__fn_unit$next sync posedge \coresync_clk update \alu_op__fn_unit $0\alu_op__fn_unit[13:0] end - attribute \src "libresoc.v:165430.3-165431.61" - process $proc$libresoc.v:165430$9022 + attribute \src "libresoc.v:166738.3-166739.61" + process $proc$libresoc.v:166738$9006 assign { } { } assign $0\alu_op__imm_data__data[63:0] \alu_op__imm_data__data$next sync posedge \coresync_clk update \alu_op__imm_data__data $0\alu_op__imm_data__data[63:0] end - attribute \src "libresoc.v:165432.3-165433.57" - process $proc$libresoc.v:165432$9023 + attribute \src "libresoc.v:166740.3-166741.57" + process $proc$libresoc.v:166740$9007 assign { } { } assign $0\alu_op__imm_data__ok[0:0] \alu_op__imm_data__ok$next sync posedge \coresync_clk update \alu_op__imm_data__ok $0\alu_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:165434.3-165435.45" - process $proc$libresoc.v:165434$9024 + attribute \src "libresoc.v:166742.3-166743.45" + process $proc$libresoc.v:166742$9008 assign { } { } assign $0\alu_op__rc__rc[0:0] \alu_op__rc__rc$next sync posedge \coresync_clk update \alu_op__rc__rc $0\alu_op__rc__rc[0:0] end - attribute \src "libresoc.v:165436.3-165437.45" - process $proc$libresoc.v:165436$9025 + attribute \src "libresoc.v:166744.3-166745.45" + process $proc$libresoc.v:166744$9009 assign { } { } assign $0\alu_op__rc__ok[0:0] \alu_op__rc__ok$next sync posedge \coresync_clk update \alu_op__rc__ok $0\alu_op__rc__ok[0:0] end - attribute \src "libresoc.v:165438.3-165439.45" - process $proc$libresoc.v:165438$9026 + attribute \src "libresoc.v:166746.3-166747.45" + process $proc$libresoc.v:166746$9010 assign { } { } assign $0\alu_op__oe__oe[0:0] \alu_op__oe__oe$next sync posedge \coresync_clk update \alu_op__oe__oe $0\alu_op__oe__oe[0:0] end - attribute \src "libresoc.v:165440.3-165441.45" - process $proc$libresoc.v:165440$9027 + attribute \src "libresoc.v:166748.3-166749.45" + process $proc$libresoc.v:166748$9011 assign { } { } assign $0\alu_op__oe__ok[0:0] \alu_op__oe__ok$next sync posedge \coresync_clk update \alu_op__oe__ok $0\alu_op__oe__ok[0:0] end - attribute \src "libresoc.v:165442.3-165443.51" - process $proc$libresoc.v:165442$9028 + attribute \src "libresoc.v:166750.3-166751.51" + process $proc$libresoc.v:166750$9012 assign { } { } assign $0\alu_op__invert_in[0:0] \alu_op__invert_in$next sync posedge \coresync_clk update \alu_op__invert_in $0\alu_op__invert_in[0:0] end - attribute \src "libresoc.v:165444.3-165445.45" - process $proc$libresoc.v:165444$9029 + attribute \src "libresoc.v:166752.3-166753.45" + process $proc$libresoc.v:166752$9013 assign { } { } assign $0\alu_op__zero_a[0:0] \alu_op__zero_a$next sync posedge \coresync_clk update \alu_op__zero_a $0\alu_op__zero_a[0:0] end - attribute \src "libresoc.v:165446.3-165447.53" - process $proc$libresoc.v:165446$9030 + attribute \src "libresoc.v:166754.3-166755.53" + process $proc$libresoc.v:166754$9014 assign { } { } assign $0\alu_op__invert_out[0:0] \alu_op__invert_out$next sync posedge \coresync_clk update \alu_op__invert_out $0\alu_op__invert_out[0:0] end - attribute \src "libresoc.v:165448.3-165449.51" - process $proc$libresoc.v:165448$9031 + attribute \src "libresoc.v:166756.3-166757.51" + process $proc$libresoc.v:166756$9015 assign { } { } assign $0\alu_op__write_cr0[0:0] \alu_op__write_cr0$next sync posedge \coresync_clk update \alu_op__write_cr0 $0\alu_op__write_cr0[0:0] end - attribute \src "libresoc.v:165450.3-165451.55" - process $proc$libresoc.v:165450$9032 + attribute \src "libresoc.v:166758.3-166759.55" + process $proc$libresoc.v:166758$9016 assign { } { } assign $0\alu_op__input_carry[1:0] \alu_op__input_carry$next sync posedge \coresync_clk update \alu_op__input_carry $0\alu_op__input_carry[1:0] end - attribute \src "libresoc.v:165452.3-165453.57" - process $proc$libresoc.v:165452$9033 + attribute \src "libresoc.v:166760.3-166761.57" + process $proc$libresoc.v:166760$9017 assign { } { } assign $0\alu_op__output_carry[0:0] \alu_op__output_carry$next sync posedge \coresync_clk update \alu_op__output_carry $0\alu_op__output_carry[0:0] end - attribute \src "libresoc.v:165454.3-165455.49" - process $proc$libresoc.v:165454$9034 + attribute \src "libresoc.v:166762.3-166763.49" + process $proc$libresoc.v:166762$9018 assign { } { } assign $0\alu_op__is_32bit[0:0] \alu_op__is_32bit$next sync posedge \coresync_clk update \alu_op__is_32bit $0\alu_op__is_32bit[0:0] end - attribute \src "libresoc.v:165456.3-165457.51" - process $proc$libresoc.v:165456$9035 + attribute \src "libresoc.v:166764.3-166765.51" + process $proc$libresoc.v:166764$9019 assign { } { } assign $0\alu_op__is_signed[0:0] \alu_op__is_signed$next sync posedge \coresync_clk update \alu_op__is_signed $0\alu_op__is_signed[0:0] end - attribute \src "libresoc.v:165458.3-165459.49" - process $proc$libresoc.v:165458$9036 + attribute \src "libresoc.v:166766.3-166767.49" + process $proc$libresoc.v:166766$9020 assign { } { } assign $0\alu_op__data_len[3:0] \alu_op__data_len$next sync posedge \coresync_clk update \alu_op__data_len $0\alu_op__data_len[3:0] end - attribute \src "libresoc.v:165460.3-165461.41" - process $proc$libresoc.v:165460$9037 + attribute \src "libresoc.v:166768.3-166769.41" + process $proc$libresoc.v:166768$9021 assign { } { } assign $0\alu_op__insn[31:0] \alu_op__insn$next sync posedge \coresync_clk update \alu_op__insn $0\alu_op__insn[31:0] end - attribute \src "libresoc.v:165462.3-165463.27" - process $proc$libresoc.v:165462$9038 + attribute \src "libresoc.v:166770.3-166771.27" + process $proc$libresoc.v:166770$9022 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:165464.3-165465.29" - process $proc$libresoc.v:165464$9039 + attribute \src "libresoc.v:166772.3-166773.29" + process $proc$libresoc.v:166772$9023 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:165575.3-165593.6" - process $proc$libresoc.v:165575$9040 + attribute \src "libresoc.v:166883.3-166901.6" + process $proc$libresoc.v:166883$9024 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$next[3:0]$9041 $1\cr_a$next[3:0]$9043 + assign $0\cr_a$next[3:0]$9025 $1\cr_a$next[3:0]$9027 assign { } { } - assign $0\cr_a_ok$next[0:0]$9042 $2\cr_a_ok$next[0:0]$9045 - attribute \src "libresoc.v:165576.5-165576.29" + assign $0\cr_a_ok$next[0:0]$9026 $2\cr_a_ok$next[0:0]$9029 + attribute \src "libresoc.v:166884.5-166884.29" switch \initial - attribute \src "libresoc.v:165576.9-165576.17" + attribute \src "libresoc.v:166884.9-166884.17" case 1'1 case end @@ -338900,41 +310270,41 @@ module \pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$9044 $1\cr_a$next[3:0]$9043 } { \cr_a_ok$91 \cr_a$90 } + assign { $1\cr_a_ok$next[0:0]$9028 $1\cr_a$next[3:0]$9027 } { \cr_a_ok$91 \cr_a$90 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$9044 $1\cr_a$next[3:0]$9043 } { \cr_a_ok$91 \cr_a$90 } + assign { $1\cr_a_ok$next[0:0]$9028 $1\cr_a$next[3:0]$9027 } { \cr_a_ok$91 \cr_a$90 } case - assign $1\cr_a$next[3:0]$9043 \cr_a - assign $1\cr_a_ok$next[0:0]$9044 \cr_a_ok + assign $1\cr_a$next[3:0]$9027 \cr_a + assign $1\cr_a_ok$next[0:0]$9028 \cr_a_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$9045 1'0 + assign $2\cr_a_ok$next[0:0]$9029 1'0 case - assign $2\cr_a_ok$next[0:0]$9045 $1\cr_a_ok$next[0:0]$9044 + assign $2\cr_a_ok$next[0:0]$9029 $1\cr_a_ok$next[0:0]$9028 end sync always - update \cr_a$next $0\cr_a$next[3:0]$9041 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9042 + update \cr_a$next $0\cr_a$next[3:0]$9025 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9026 end - attribute \src "libresoc.v:165594.3-165612.6" - process $proc$libresoc.v:165594$9046 + attribute \src "libresoc.v:166902.3-166920.6" + process $proc$libresoc.v:166902$9030 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ca$next[1:0]$9048 $1\xer_ca$next[1:0]$9050 - assign $0\xer_ca_ok$next[0:0]$9047 $2\xer_ca_ok$next[0:0]$9051 - attribute \src "libresoc.v:165595.5-165595.29" + assign $0\xer_ca$next[1:0]$9032 $1\xer_ca$next[1:0]$9034 + assign $0\xer_ca_ok$next[0:0]$9031 $2\xer_ca_ok$next[0:0]$9035 + attribute \src "libresoc.v:166903.5-166903.29" switch \initial - attribute \src "libresoc.v:165595.9-165595.17" + attribute \src "libresoc.v:166903.9-166903.17" case 1'1 case end @@ -338944,41 +310314,41 @@ module \pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ca_ok$next[0:0]$9049 $1\xer_ca$next[1:0]$9050 } { \xer_ca_ok$93 \xer_ca$92 } + assign { $1\xer_ca_ok$next[0:0]$9033 $1\xer_ca$next[1:0]$9034 } { \xer_ca_ok$93 \xer_ca$92 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ca_ok$next[0:0]$9049 $1\xer_ca$next[1:0]$9050 } { \xer_ca_ok$93 \xer_ca$92 } + assign { $1\xer_ca_ok$next[0:0]$9033 $1\xer_ca$next[1:0]$9034 } { \xer_ca_ok$93 \xer_ca$92 } case - assign $1\xer_ca_ok$next[0:0]$9049 \xer_ca_ok - assign $1\xer_ca$next[1:0]$9050 \xer_ca + assign $1\xer_ca_ok$next[0:0]$9033 \xer_ca_ok + assign $1\xer_ca$next[1:0]$9034 \xer_ca end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ca_ok$next[0:0]$9051 1'0 + assign $2\xer_ca_ok$next[0:0]$9035 1'0 case - assign $2\xer_ca_ok$next[0:0]$9051 $1\xer_ca_ok$next[0:0]$9049 + assign $2\xer_ca_ok$next[0:0]$9035 $1\xer_ca_ok$next[0:0]$9033 end sync always - update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$9047 - update \xer_ca$next $0\xer_ca$next[1:0]$9048 + update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$9031 + update \xer_ca$next $0\xer_ca$next[1:0]$9032 end - attribute \src "libresoc.v:165613.3-165631.6" - process $proc$libresoc.v:165613$9052 + attribute \src "libresoc.v:166921.3-166939.6" + process $proc$libresoc.v:166921$9036 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ov$next[1:0]$9053 $1\xer_ov$next[1:0]$9055 + assign $0\xer_ov$next[1:0]$9037 $1\xer_ov$next[1:0]$9039 assign { } { } - assign $0\xer_ov_ok$next[0:0]$9054 $2\xer_ov_ok$next[0:0]$9057 - attribute \src "libresoc.v:165614.5-165614.29" + assign $0\xer_ov_ok$next[0:0]$9038 $2\xer_ov_ok$next[0:0]$9041 + attribute \src "libresoc.v:166922.5-166922.29" switch \initial - attribute \src "libresoc.v:165614.9-165614.17" + attribute \src "libresoc.v:166922.9-166922.17" case 1'1 case end @@ -338988,41 +310358,41 @@ module \pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$9056 $1\xer_ov$next[1:0]$9055 } { \xer_ov_ok$95 \xer_ov$94 } + assign { $1\xer_ov_ok$next[0:0]$9040 $1\xer_ov$next[1:0]$9039 } { \xer_ov_ok$95 \xer_ov$94 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$9056 $1\xer_ov$next[1:0]$9055 } { \xer_ov_ok$95 \xer_ov$94 } + assign { $1\xer_ov_ok$next[0:0]$9040 $1\xer_ov$next[1:0]$9039 } { \xer_ov_ok$95 \xer_ov$94 } case - assign $1\xer_ov$next[1:0]$9055 \xer_ov - assign $1\xer_ov_ok$next[0:0]$9056 \xer_ov_ok + assign $1\xer_ov$next[1:0]$9039 \xer_ov + assign $1\xer_ov_ok$next[0:0]$9040 \xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ov_ok$next[0:0]$9057 1'0 + assign $2\xer_ov_ok$next[0:0]$9041 1'0 case - assign $2\xer_ov_ok$next[0:0]$9057 $1\xer_ov_ok$next[0:0]$9056 + assign $2\xer_ov_ok$next[0:0]$9041 $1\xer_ov_ok$next[0:0]$9040 end sync always - update \xer_ov$next $0\xer_ov$next[1:0]$9053 - update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9054 + update \xer_ov$next $0\xer_ov$next[1:0]$9037 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9038 end - attribute \src "libresoc.v:165632.3-165650.6" - process $proc$libresoc.v:165632$9058 + attribute \src "libresoc.v:166940.3-166958.6" + process $proc$libresoc.v:166940$9042 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$next[0:0]$9059 $1\xer_so$next[0:0]$9061 + assign $0\xer_so$next[0:0]$9043 $1\xer_so$next[0:0]$9045 assign { } { } - assign $0\xer_so_ok$next[0:0]$9060 $2\xer_so_ok$next[0:0]$9063 - attribute \src "libresoc.v:165633.5-165633.29" + assign $0\xer_so_ok$next[0:0]$9044 $2\xer_so_ok$next[0:0]$9047 + attribute \src "libresoc.v:166941.5-166941.29" switch \initial - attribute \src "libresoc.v:165633.9-165633.17" + attribute \src "libresoc.v:166941.9-166941.17" case 1'1 case end @@ -339032,38 +310402,38 @@ module \pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$9062 $1\xer_so$next[0:0]$9061 } { \xer_so_ok$97 \xer_so$96 } + assign { $1\xer_so_ok$next[0:0]$9046 $1\xer_so$next[0:0]$9045 } { \xer_so_ok$97 \xer_so$96 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$9062 $1\xer_so$next[0:0]$9061 } { \xer_so_ok$97 \xer_so$96 } + assign { $1\xer_so_ok$next[0:0]$9046 $1\xer_so$next[0:0]$9045 } { \xer_so_ok$97 \xer_so$96 } case - assign $1\xer_so$next[0:0]$9061 \xer_so - assign $1\xer_so_ok$next[0:0]$9062 \xer_so_ok + assign $1\xer_so$next[0:0]$9045 \xer_so + assign $1\xer_so_ok$next[0:0]$9046 \xer_so_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$9063 1'0 + assign $2\xer_so_ok$next[0:0]$9047 1'0 case - assign $2\xer_so_ok$next[0:0]$9063 $1\xer_so_ok$next[0:0]$9062 + assign $2\xer_so_ok$next[0:0]$9047 $1\xer_so_ok$next[0:0]$9046 end sync always - update \xer_so$next $0\xer_so$next[0:0]$9059 - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9060 + update \xer_so$next $0\xer_so$next[0:0]$9043 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9044 end - attribute \src "libresoc.v:165651.3-165668.6" - process $proc$libresoc.v:165651$9064 + attribute \src "libresoc.v:166959.3-166976.6" + process $proc$libresoc.v:166959$9048 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9065 $2\r_busy$next[0:0]$9067 - attribute \src "libresoc.v:165652.5-165652.29" + assign $0\r_busy$next[0:0]$9049 $2\r_busy$next[0:0]$9051 + attribute \src "libresoc.v:166960.5-166960.29" switch \initial - attribute \src "libresoc.v:165652.9-165652.17" + attribute \src "libresoc.v:166960.9-166960.17" case 1'1 case end @@ -339072,34 +310442,34 @@ module \pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9066 1'1 + assign $1\r_busy$next[0:0]$9050 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9066 1'0 + assign $1\r_busy$next[0:0]$9050 1'0 case - assign $1\r_busy$next[0:0]$9066 \r_busy + assign $1\r_busy$next[0:0]$9050 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9067 1'0 + assign $2\r_busy$next[0:0]$9051 1'0 case - assign $2\r_busy$next[0:0]$9067 $1\r_busy$next[0:0]$9066 + assign $2\r_busy$next[0:0]$9051 $1\r_busy$next[0:0]$9050 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9065 + update \r_busy$next $0\r_busy$next[0:0]$9049 end - attribute \src "libresoc.v:165669.3-165681.6" - process $proc$libresoc.v:165669$9068 + attribute \src "libresoc.v:166977.3-166989.6" + process $proc$libresoc.v:166977$9052 assign { } { } assign { } { } - assign $0\muxid$next[1:0]$9069 $1\muxid$next[1:0]$9070 - attribute \src "libresoc.v:165670.5-165670.29" + assign $0\muxid$next[1:0]$9053 $1\muxid$next[1:0]$9054 + attribute \src "libresoc.v:166978.5-166978.29" switch \initial - attribute \src "libresoc.v:165670.9-165670.17" + attribute \src "libresoc.v:166978.9-166978.17" case 1'1 case end @@ -339108,19 +310478,19 @@ module \pipe1 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$next[1:0]$9070 \muxid$69 + assign $1\muxid$next[1:0]$9054 \muxid$69 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$next[1:0]$9070 \muxid$69 + assign $1\muxid$next[1:0]$9054 \muxid$69 case - assign $1\muxid$next[1:0]$9070 \muxid + assign $1\muxid$next[1:0]$9054 \muxid end sync always - update \muxid$next $0\muxid$next[1:0]$9069 + update \muxid$next $0\muxid$next[1:0]$9053 end - attribute \src "libresoc.v:165682.3-165723.6" - process $proc$libresoc.v:165682$9071 + attribute \src "libresoc.v:166990.3-167031.6" + process $proc$libresoc.v:166990$9055 assign { } { } assign { } { } assign { } { } @@ -339157,33 +310527,33 @@ module \pipe1 assign { } { } assign { } { } assign { } { } - assign $0\alu_op__data_len$next[3:0]$9072 $1\alu_op__data_len$next[3:0]$9090 - assign $0\alu_op__fn_unit$next[13:0]$9073 $1\alu_op__fn_unit$next[13:0]$9091 + assign $0\alu_op__data_len$next[3:0]$9056 $1\alu_op__data_len$next[3:0]$9074 + assign $0\alu_op__fn_unit$next[13:0]$9057 $1\alu_op__fn_unit$next[13:0]$9075 assign { } { } assign { } { } - assign $0\alu_op__input_carry$next[1:0]$9076 $1\alu_op__input_carry$next[1:0]$9094 - assign $0\alu_op__insn$next[31:0]$9077 $1\alu_op__insn$next[31:0]$9095 - assign $0\alu_op__insn_type$next[6:0]$9078 $1\alu_op__insn_type$next[6:0]$9096 - assign $0\alu_op__invert_in$next[0:0]$9079 $1\alu_op__invert_in$next[0:0]$9097 - assign $0\alu_op__invert_out$next[0:0]$9080 $1\alu_op__invert_out$next[0:0]$9098 - assign $0\alu_op__is_32bit$next[0:0]$9081 $1\alu_op__is_32bit$next[0:0]$9099 - assign $0\alu_op__is_signed$next[0:0]$9082 $1\alu_op__is_signed$next[0:0]$9100 + assign $0\alu_op__input_carry$next[1:0]$9060 $1\alu_op__input_carry$next[1:0]$9078 + assign $0\alu_op__insn$next[31:0]$9061 $1\alu_op__insn$next[31:0]$9079 + assign $0\alu_op__insn_type$next[6:0]$9062 $1\alu_op__insn_type$next[6:0]$9080 + assign $0\alu_op__invert_in$next[0:0]$9063 $1\alu_op__invert_in$next[0:0]$9081 + assign $0\alu_op__invert_out$next[0:0]$9064 $1\alu_op__invert_out$next[0:0]$9082 + assign $0\alu_op__is_32bit$next[0:0]$9065 $1\alu_op__is_32bit$next[0:0]$9083 + assign $0\alu_op__is_signed$next[0:0]$9066 $1\alu_op__is_signed$next[0:0]$9084 assign { } { } assign { } { } - assign $0\alu_op__output_carry$next[0:0]$9085 $1\alu_op__output_carry$next[0:0]$9103 + assign $0\alu_op__output_carry$next[0:0]$9069 $1\alu_op__output_carry$next[0:0]$9087 assign { } { } assign { } { } - assign $0\alu_op__write_cr0$next[0:0]$9088 $1\alu_op__write_cr0$next[0:0]$9106 - assign $0\alu_op__zero_a$next[0:0]$9089 $1\alu_op__zero_a$next[0:0]$9107 - assign $0\alu_op__imm_data__data$next[63:0]$9074 $2\alu_op__imm_data__data$next[63:0]$9108 - assign $0\alu_op__imm_data__ok$next[0:0]$9075 $2\alu_op__imm_data__ok$next[0:0]$9109 - assign $0\alu_op__oe__oe$next[0:0]$9083 $2\alu_op__oe__oe$next[0:0]$9110 - assign $0\alu_op__oe__ok$next[0:0]$9084 $2\alu_op__oe__ok$next[0:0]$9111 - assign $0\alu_op__rc__ok$next[0:0]$9086 $2\alu_op__rc__ok$next[0:0]$9112 - assign $0\alu_op__rc__rc$next[0:0]$9087 $2\alu_op__rc__rc$next[0:0]$9113 - attribute \src "libresoc.v:165683.5-165683.29" + assign $0\alu_op__write_cr0$next[0:0]$9072 $1\alu_op__write_cr0$next[0:0]$9090 + assign $0\alu_op__zero_a$next[0:0]$9073 $1\alu_op__zero_a$next[0:0]$9091 + assign $0\alu_op__imm_data__data$next[63:0]$9058 $2\alu_op__imm_data__data$next[63:0]$9092 + assign $0\alu_op__imm_data__ok$next[0:0]$9059 $2\alu_op__imm_data__ok$next[0:0]$9093 + assign $0\alu_op__oe__oe$next[0:0]$9067 $2\alu_op__oe__oe$next[0:0]$9094 + assign $0\alu_op__oe__ok$next[0:0]$9068 $2\alu_op__oe__ok$next[0:0]$9095 + assign $0\alu_op__rc__ok$next[0:0]$9070 $2\alu_op__rc__ok$next[0:0]$9096 + assign $0\alu_op__rc__rc$next[0:0]$9071 $2\alu_op__rc__rc$next[0:0]$9097 + attribute \src "libresoc.v:166991.5-166991.29" switch \initial - attribute \src "libresoc.v:165683.9-165683.17" + attribute \src "libresoc.v:166991.9-166991.17" case 1'1 case end @@ -339209,7 +310579,7 @@ module \pipe1 assign { } { } assign { } { } assign { } { } - assign { $1\alu_op__insn$next[31:0]$9095 $1\alu_op__data_len$next[3:0]$9090 $1\alu_op__is_signed$next[0:0]$9100 $1\alu_op__is_32bit$next[0:0]$9099 $1\alu_op__output_carry$next[0:0]$9103 $1\alu_op__input_carry$next[1:0]$9094 $1\alu_op__write_cr0$next[0:0]$9106 $1\alu_op__invert_out$next[0:0]$9098 $1\alu_op__zero_a$next[0:0]$9107 $1\alu_op__invert_in$next[0:0]$9097 $1\alu_op__oe__ok$next[0:0]$9102 $1\alu_op__oe__oe$next[0:0]$9101 $1\alu_op__rc__ok$next[0:0]$9104 $1\alu_op__rc__rc$next[0:0]$9105 $1\alu_op__imm_data__ok$next[0:0]$9093 $1\alu_op__imm_data__data$next[63:0]$9092 $1\alu_op__fn_unit$next[13:0]$9091 $1\alu_op__insn_type$next[6:0]$9096 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } + assign { $1\alu_op__insn$next[31:0]$9079 $1\alu_op__data_len$next[3:0]$9074 $1\alu_op__is_signed$next[0:0]$9084 $1\alu_op__is_32bit$next[0:0]$9083 $1\alu_op__output_carry$next[0:0]$9087 $1\alu_op__input_carry$next[1:0]$9078 $1\alu_op__write_cr0$next[0:0]$9090 $1\alu_op__invert_out$next[0:0]$9082 $1\alu_op__zero_a$next[0:0]$9091 $1\alu_op__invert_in$next[0:0]$9081 $1\alu_op__oe__ok$next[0:0]$9086 $1\alu_op__oe__oe$next[0:0]$9085 $1\alu_op__rc__ok$next[0:0]$9088 $1\alu_op__rc__rc$next[0:0]$9089 $1\alu_op__imm_data__ok$next[0:0]$9077 $1\alu_op__imm_data__data$next[63:0]$9076 $1\alu_op__fn_unit$next[13:0]$9075 $1\alu_op__insn_type$next[6:0]$9080 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -339230,26 +310600,26 @@ module \pipe1 assign { } { } assign { } { } assign { } { } - assign { $1\alu_op__insn$next[31:0]$9095 $1\alu_op__data_len$next[3:0]$9090 $1\alu_op__is_signed$next[0:0]$9100 $1\alu_op__is_32bit$next[0:0]$9099 $1\alu_op__output_carry$next[0:0]$9103 $1\alu_op__input_carry$next[1:0]$9094 $1\alu_op__write_cr0$next[0:0]$9106 $1\alu_op__invert_out$next[0:0]$9098 $1\alu_op__zero_a$next[0:0]$9107 $1\alu_op__invert_in$next[0:0]$9097 $1\alu_op__oe__ok$next[0:0]$9102 $1\alu_op__oe__oe$next[0:0]$9101 $1\alu_op__rc__ok$next[0:0]$9104 $1\alu_op__rc__rc$next[0:0]$9105 $1\alu_op__imm_data__ok$next[0:0]$9093 $1\alu_op__imm_data__data$next[63:0]$9092 $1\alu_op__fn_unit$next[13:0]$9091 $1\alu_op__insn_type$next[6:0]$9096 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } + assign { $1\alu_op__insn$next[31:0]$9079 $1\alu_op__data_len$next[3:0]$9074 $1\alu_op__is_signed$next[0:0]$9084 $1\alu_op__is_32bit$next[0:0]$9083 $1\alu_op__output_carry$next[0:0]$9087 $1\alu_op__input_carry$next[1:0]$9078 $1\alu_op__write_cr0$next[0:0]$9090 $1\alu_op__invert_out$next[0:0]$9082 $1\alu_op__zero_a$next[0:0]$9091 $1\alu_op__invert_in$next[0:0]$9081 $1\alu_op__oe__ok$next[0:0]$9086 $1\alu_op__oe__oe$next[0:0]$9085 $1\alu_op__rc__ok$next[0:0]$9088 $1\alu_op__rc__rc$next[0:0]$9089 $1\alu_op__imm_data__ok$next[0:0]$9077 $1\alu_op__imm_data__data$next[63:0]$9076 $1\alu_op__fn_unit$next[13:0]$9075 $1\alu_op__insn_type$next[6:0]$9080 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } case - assign $1\alu_op__data_len$next[3:0]$9090 \alu_op__data_len - assign $1\alu_op__fn_unit$next[13:0]$9091 \alu_op__fn_unit - assign $1\alu_op__imm_data__data$next[63:0]$9092 \alu_op__imm_data__data - assign $1\alu_op__imm_data__ok$next[0:0]$9093 \alu_op__imm_data__ok - assign $1\alu_op__input_carry$next[1:0]$9094 \alu_op__input_carry - assign $1\alu_op__insn$next[31:0]$9095 \alu_op__insn - assign $1\alu_op__insn_type$next[6:0]$9096 \alu_op__insn_type - assign $1\alu_op__invert_in$next[0:0]$9097 \alu_op__invert_in - assign $1\alu_op__invert_out$next[0:0]$9098 \alu_op__invert_out - assign $1\alu_op__is_32bit$next[0:0]$9099 \alu_op__is_32bit - assign $1\alu_op__is_signed$next[0:0]$9100 \alu_op__is_signed - assign $1\alu_op__oe__oe$next[0:0]$9101 \alu_op__oe__oe - assign $1\alu_op__oe__ok$next[0:0]$9102 \alu_op__oe__ok - assign $1\alu_op__output_carry$next[0:0]$9103 \alu_op__output_carry - assign $1\alu_op__rc__ok$next[0:0]$9104 \alu_op__rc__ok - assign $1\alu_op__rc__rc$next[0:0]$9105 \alu_op__rc__rc - assign $1\alu_op__write_cr0$next[0:0]$9106 \alu_op__write_cr0 - assign $1\alu_op__zero_a$next[0:0]$9107 \alu_op__zero_a + assign $1\alu_op__data_len$next[3:0]$9074 \alu_op__data_len + assign $1\alu_op__fn_unit$next[13:0]$9075 \alu_op__fn_unit + assign $1\alu_op__imm_data__data$next[63:0]$9076 \alu_op__imm_data__data + assign $1\alu_op__imm_data__ok$next[0:0]$9077 \alu_op__imm_data__ok + assign $1\alu_op__input_carry$next[1:0]$9078 \alu_op__input_carry + assign $1\alu_op__insn$next[31:0]$9079 \alu_op__insn + assign $1\alu_op__insn_type$next[6:0]$9080 \alu_op__insn_type + assign $1\alu_op__invert_in$next[0:0]$9081 \alu_op__invert_in + assign $1\alu_op__invert_out$next[0:0]$9082 \alu_op__invert_out + assign $1\alu_op__is_32bit$next[0:0]$9083 \alu_op__is_32bit + assign $1\alu_op__is_signed$next[0:0]$9084 \alu_op__is_signed + assign $1\alu_op__oe__oe$next[0:0]$9085 \alu_op__oe__oe + assign $1\alu_op__oe__ok$next[0:0]$9086 \alu_op__oe__ok + assign $1\alu_op__output_carry$next[0:0]$9087 \alu_op__output_carry + assign $1\alu_op__rc__ok$next[0:0]$9088 \alu_op__rc__ok + assign $1\alu_op__rc__rc$next[0:0]$9089 \alu_op__rc__rc + assign $1\alu_op__write_cr0$next[0:0]$9090 \alu_op__write_cr0 + assign $1\alu_op__zero_a$next[0:0]$9091 \alu_op__zero_a end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -339261,52 +310631,52 @@ module \pipe1 assign { } { } assign { } { } assign { } { } - assign $2\alu_op__imm_data__data$next[63:0]$9108 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_op__imm_data__ok$next[0:0]$9109 1'0 - assign $2\alu_op__rc__rc$next[0:0]$9113 1'0 - assign $2\alu_op__rc__ok$next[0:0]$9112 1'0 - assign $2\alu_op__oe__oe$next[0:0]$9110 1'0 - assign $2\alu_op__oe__ok$next[0:0]$9111 1'0 + assign $2\alu_op__imm_data__data$next[63:0]$9092 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_op__imm_data__ok$next[0:0]$9093 1'0 + assign $2\alu_op__rc__rc$next[0:0]$9097 1'0 + assign $2\alu_op__rc__ok$next[0:0]$9096 1'0 + assign $2\alu_op__oe__oe$next[0:0]$9094 1'0 + assign $2\alu_op__oe__ok$next[0:0]$9095 1'0 case - assign $2\alu_op__imm_data__data$next[63:0]$9108 $1\alu_op__imm_data__data$next[63:0]$9092 - assign $2\alu_op__imm_data__ok$next[0:0]$9109 $1\alu_op__imm_data__ok$next[0:0]$9093 - assign $2\alu_op__oe__oe$next[0:0]$9110 $1\alu_op__oe__oe$next[0:0]$9101 - assign $2\alu_op__oe__ok$next[0:0]$9111 $1\alu_op__oe__ok$next[0:0]$9102 - assign $2\alu_op__rc__ok$next[0:0]$9112 $1\alu_op__rc__ok$next[0:0]$9104 - assign $2\alu_op__rc__rc$next[0:0]$9113 $1\alu_op__rc__rc$next[0:0]$9105 + assign $2\alu_op__imm_data__data$next[63:0]$9092 $1\alu_op__imm_data__data$next[63:0]$9076 + assign $2\alu_op__imm_data__ok$next[0:0]$9093 $1\alu_op__imm_data__ok$next[0:0]$9077 + assign $2\alu_op__oe__oe$next[0:0]$9094 $1\alu_op__oe__oe$next[0:0]$9085 + assign $2\alu_op__oe__ok$next[0:0]$9095 $1\alu_op__oe__ok$next[0:0]$9086 + assign $2\alu_op__rc__ok$next[0:0]$9096 $1\alu_op__rc__ok$next[0:0]$9088 + assign $2\alu_op__rc__rc$next[0:0]$9097 $1\alu_op__rc__rc$next[0:0]$9089 end sync always - update \alu_op__data_len$next $0\alu_op__data_len$next[3:0]$9072 - update \alu_op__fn_unit$next $0\alu_op__fn_unit$next[13:0]$9073 - update \alu_op__imm_data__data$next $0\alu_op__imm_data__data$next[63:0]$9074 - update \alu_op__imm_data__ok$next $0\alu_op__imm_data__ok$next[0:0]$9075 - update \alu_op__input_carry$next $0\alu_op__input_carry$next[1:0]$9076 - update \alu_op__insn$next $0\alu_op__insn$next[31:0]$9077 - update \alu_op__insn_type$next $0\alu_op__insn_type$next[6:0]$9078 - update \alu_op__invert_in$next $0\alu_op__invert_in$next[0:0]$9079 - update \alu_op__invert_out$next $0\alu_op__invert_out$next[0:0]$9080 - update \alu_op__is_32bit$next $0\alu_op__is_32bit$next[0:0]$9081 - update \alu_op__is_signed$next $0\alu_op__is_signed$next[0:0]$9082 - update \alu_op__oe__oe$next $0\alu_op__oe__oe$next[0:0]$9083 - update \alu_op__oe__ok$next $0\alu_op__oe__ok$next[0:0]$9084 - update \alu_op__output_carry$next $0\alu_op__output_carry$next[0:0]$9085 - update \alu_op__rc__ok$next $0\alu_op__rc__ok$next[0:0]$9086 - update \alu_op__rc__rc$next $0\alu_op__rc__rc$next[0:0]$9087 - update \alu_op__write_cr0$next $0\alu_op__write_cr0$next[0:0]$9088 - update \alu_op__zero_a$next $0\alu_op__zero_a$next[0:0]$9089 + update \alu_op__data_len$next $0\alu_op__data_len$next[3:0]$9056 + update \alu_op__fn_unit$next $0\alu_op__fn_unit$next[13:0]$9057 + update \alu_op__imm_data__data$next $0\alu_op__imm_data__data$next[63:0]$9058 + update \alu_op__imm_data__ok$next $0\alu_op__imm_data__ok$next[0:0]$9059 + update \alu_op__input_carry$next $0\alu_op__input_carry$next[1:0]$9060 + update \alu_op__insn$next $0\alu_op__insn$next[31:0]$9061 + update \alu_op__insn_type$next $0\alu_op__insn_type$next[6:0]$9062 + update \alu_op__invert_in$next $0\alu_op__invert_in$next[0:0]$9063 + update \alu_op__invert_out$next $0\alu_op__invert_out$next[0:0]$9064 + update \alu_op__is_32bit$next $0\alu_op__is_32bit$next[0:0]$9065 + update \alu_op__is_signed$next $0\alu_op__is_signed$next[0:0]$9066 + update \alu_op__oe__oe$next $0\alu_op__oe__oe$next[0:0]$9067 + update \alu_op__oe__ok$next $0\alu_op__oe__ok$next[0:0]$9068 + update \alu_op__output_carry$next $0\alu_op__output_carry$next[0:0]$9069 + update \alu_op__rc__ok$next $0\alu_op__rc__ok$next[0:0]$9070 + update \alu_op__rc__rc$next $0\alu_op__rc__rc$next[0:0]$9071 + update \alu_op__write_cr0$next $0\alu_op__write_cr0$next[0:0]$9072 + update \alu_op__zero_a$next $0\alu_op__zero_a$next[0:0]$9073 end - attribute \src "libresoc.v:165724.3-165742.6" - process $proc$libresoc.v:165724$9114 + attribute \src "libresoc.v:167032.3-167050.6" + process $proc$libresoc.v:167032$9098 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$9115 $1\o$next[63:0]$9117 + assign $0\o$next[63:0]$9099 $1\o$next[63:0]$9101 assign { } { } - assign $0\o_ok$next[0:0]$9116 $2\o_ok$next[0:0]$9119 - attribute \src "libresoc.v:165725.5-165725.29" + assign $0\o_ok$next[0:0]$9100 $2\o_ok$next[0:0]$9103 + attribute \src "libresoc.v:167033.5-167033.29" switch \initial - attribute \src "libresoc.v:165725.9-165725.17" + attribute \src "libresoc.v:167033.9-167033.17" case 1'1 case end @@ -339316,30 +310686,30 @@ module \pipe1 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9118 $1\o$next[63:0]$9117 } { \o_ok$89 \o$88 } + assign { $1\o_ok$next[0:0]$9102 $1\o$next[63:0]$9101 } { \o_ok$89 \o$88 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9118 $1\o$next[63:0]$9117 } { \o_ok$89 \o$88 } + assign { $1\o_ok$next[0:0]$9102 $1\o$next[63:0]$9101 } { \o_ok$89 \o$88 } case - assign $1\o$next[63:0]$9117 \o - assign $1\o_ok$next[0:0]$9118 \o_ok + assign $1\o$next[63:0]$9101 \o + assign $1\o_ok$next[0:0]$9102 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$9119 1'0 + assign $2\o_ok$next[0:0]$9103 1'0 case - assign $2\o_ok$next[0:0]$9119 $1\o_ok$next[0:0]$9118 + assign $2\o_ok$next[0:0]$9103 $1\o_ok$next[0:0]$9102 end sync always - update \o$next $0\o$next[63:0]$9115 - update \o_ok$next $0\o_ok$next[0:0]$9116 + update \o$next $0\o$next[63:0]$9099 + update \o_ok$next $0\o_ok$next[0:0]$9100 end - connect \$67 $and$libresoc.v:165405$9009_Y + connect \$67 $and$libresoc.v:166713$8993_Y connect \xer_so_ok$98 1'0 connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy @@ -339366,258 +310736,258 @@ module \pipe1 connect { \input_alu_op__insn \input_alu_op__data_len \input_alu_op__is_signed \input_alu_op__is_32bit \input_alu_op__output_carry \input_alu_op__input_carry \input_alu_op__write_cr0 \input_alu_op__invert_out \input_alu_op__zero_a \input_alu_op__invert_in \input_alu_op__oe__ok \input_alu_op__oe__oe \input_alu_op__rc__ok \input_alu_op__rc__rc \input_alu_op__imm_data__ok \input_alu_op__imm_data__data \input_alu_op__fn_unit \input_alu_op__insn_type } { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:165772.1-167208.10" +attribute \src "libresoc.v:167080.1-168516.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1" attribute \generator "nMigen" module \pipe1$110 - attribute \src "libresoc.v:167141.3-167159.6" - wire width 4 $0\cr_a$next[3:0]$9240 - attribute \src "libresoc.v:166883.3-166884.25" + attribute \src "libresoc.v:168449.3-168467.6" + wire width 4 $0\cr_a$next[3:0]$9224 + attribute \src "libresoc.v:168191.3-168192.25" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:167141.3-167159.6" - wire $0\cr_a_ok$next[0:0]$9241 - attribute \src "libresoc.v:166885.3-166886.31" + attribute \src "libresoc.v:168449.3-168467.6" + wire $0\cr_a_ok$next[0:0]$9225 + attribute \src "libresoc.v:168193.3-168194.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:165773.7-165773.20" + attribute \src "libresoc.v:167081.7-167081.20" wire $0\initial[0:0] - attribute \src "libresoc.v:167068.3-167080.6" - wire width 2 $0\muxid$next[1:0]$9190 - attribute \src "libresoc.v:166925.3-166926.27" + attribute \src "libresoc.v:168376.3-168388.6" + wire width 2 $0\muxid$next[1:0]$9174 + attribute \src "libresoc.v:168233.3-168234.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:167122.3-167140.6" - wire width 64 $0\o$next[63:0]$9234 - attribute \src "libresoc.v:166887.3-166888.19" + attribute \src "libresoc.v:168430.3-168448.6" + wire width 64 $0\o$next[63:0]$9218 + attribute \src "libresoc.v:168195.3-168196.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:167122.3-167140.6" - wire $0\o_ok$next[0:0]$9235 - attribute \src "libresoc.v:166889.3-166890.25" + attribute \src "libresoc.v:168430.3-168448.6" + wire $0\o_ok$next[0:0]$9219 + attribute \src "libresoc.v:168197.3-168198.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:167050.3-167067.6" - wire $0\r_busy$next[0:0]$9186 - attribute \src "libresoc.v:166927.3-166928.29" + attribute \src "libresoc.v:168358.3-168375.6" + wire $0\r_busy$next[0:0]$9170 + attribute \src "libresoc.v:168235.3-168236.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:167081.3-167121.6" - wire width 14 $0\sr_op__fn_unit$next[13:0]$9193 - attribute \src "libresoc.v:166893.3-166894.45" + attribute \src "libresoc.v:168389.3-168429.6" + wire width 14 $0\sr_op__fn_unit$next[13:0]$9177 + attribute \src "libresoc.v:168201.3-168202.45" wire width 14 $0\sr_op__fn_unit[13:0] - attribute \src "libresoc.v:167081.3-167121.6" - wire width 64 $0\sr_op__imm_data__data$next[63:0]$9194 - attribute \src "libresoc.v:166895.3-166896.59" + attribute \src "libresoc.v:168389.3-168429.6" + wire width 64 $0\sr_op__imm_data__data$next[63:0]$9178 + attribute \src "libresoc.v:168203.3-168204.59" wire width 64 $0\sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:167081.3-167121.6" - wire $0\sr_op__imm_data__ok$next[0:0]$9195 - attribute \src "libresoc.v:166897.3-166898.55" + attribute \src "libresoc.v:168389.3-168429.6" + wire $0\sr_op__imm_data__ok$next[0:0]$9179 + attribute \src "libresoc.v:168205.3-168206.55" wire $0\sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:167081.3-167121.6" - wire width 2 $0\sr_op__input_carry$next[1:0]$9196 - attribute \src "libresoc.v:166911.3-166912.53" + attribute \src "libresoc.v:168389.3-168429.6" + wire width 2 $0\sr_op__input_carry$next[1:0]$9180 + attribute \src "libresoc.v:168219.3-168220.53" wire width 2 $0\sr_op__input_carry[1:0] - attribute \src "libresoc.v:167081.3-167121.6" - wire $0\sr_op__input_cr$next[0:0]$9197 - attribute \src "libresoc.v:166915.3-166916.47" + attribute \src "libresoc.v:168389.3-168429.6" + wire $0\sr_op__input_cr$next[0:0]$9181 + attribute \src "libresoc.v:168223.3-168224.47" wire $0\sr_op__input_cr[0:0] - attribute \src "libresoc.v:167081.3-167121.6" - wire width 32 $0\sr_op__insn$next[31:0]$9198 - attribute \src "libresoc.v:166923.3-166924.39" + attribute \src "libresoc.v:168389.3-168429.6" + wire width 32 $0\sr_op__insn$next[31:0]$9182 + attribute \src "libresoc.v:168231.3-168232.39" wire width 32 $0\sr_op__insn[31:0] - attribute \src "libresoc.v:167081.3-167121.6" - wire width 7 $0\sr_op__insn_type$next[6:0]$9199 - attribute \src "libresoc.v:166891.3-166892.49" + attribute \src "libresoc.v:168389.3-168429.6" + wire width 7 $0\sr_op__insn_type$next[6:0]$9183 + attribute \src "libresoc.v:168199.3-168200.49" wire width 7 $0\sr_op__insn_type[6:0] - attribute \src "libresoc.v:167081.3-167121.6" - wire $0\sr_op__invert_in$next[0:0]$9200 - attribute \src "libresoc.v:166909.3-166910.49" + attribute \src "libresoc.v:168389.3-168429.6" + wire $0\sr_op__invert_in$next[0:0]$9184 + attribute \src "libresoc.v:168217.3-168218.49" wire $0\sr_op__invert_in[0:0] - attribute \src "libresoc.v:167081.3-167121.6" - wire $0\sr_op__is_32bit$next[0:0]$9201 - attribute \src "libresoc.v:166919.3-166920.47" + attribute \src "libresoc.v:168389.3-168429.6" + wire $0\sr_op__is_32bit$next[0:0]$9185 + attribute \src "libresoc.v:168227.3-168228.47" wire $0\sr_op__is_32bit[0:0] - attribute \src "libresoc.v:167081.3-167121.6" - wire $0\sr_op__is_signed$next[0:0]$9202 - attribute \src "libresoc.v:166921.3-166922.49" + attribute \src "libresoc.v:168389.3-168429.6" + wire $0\sr_op__is_signed$next[0:0]$9186 + attribute \src "libresoc.v:168229.3-168230.49" wire $0\sr_op__is_signed[0:0] - attribute \src "libresoc.v:167081.3-167121.6" - wire $0\sr_op__oe__oe$next[0:0]$9203 - attribute \src "libresoc.v:166903.3-166904.43" + attribute \src "libresoc.v:168389.3-168429.6" + wire $0\sr_op__oe__oe$next[0:0]$9187 + attribute \src "libresoc.v:168211.3-168212.43" wire $0\sr_op__oe__oe[0:0] - attribute \src "libresoc.v:167081.3-167121.6" - wire $0\sr_op__oe__ok$next[0:0]$9204 - attribute \src "libresoc.v:166905.3-166906.43" + attribute \src "libresoc.v:168389.3-168429.6" + wire $0\sr_op__oe__ok$next[0:0]$9188 + attribute \src "libresoc.v:168213.3-168214.43" wire $0\sr_op__oe__ok[0:0] - attribute \src "libresoc.v:167081.3-167121.6" - wire $0\sr_op__output_carry$next[0:0]$9205 - attribute \src "libresoc.v:166913.3-166914.55" + attribute \src "libresoc.v:168389.3-168429.6" + wire $0\sr_op__output_carry$next[0:0]$9189 + attribute \src "libresoc.v:168221.3-168222.55" wire $0\sr_op__output_carry[0:0] - attribute \src "libresoc.v:167081.3-167121.6" - wire $0\sr_op__output_cr$next[0:0]$9206 - attribute \src "libresoc.v:166917.3-166918.49" + attribute \src "libresoc.v:168389.3-168429.6" + wire $0\sr_op__output_cr$next[0:0]$9190 + attribute \src "libresoc.v:168225.3-168226.49" wire $0\sr_op__output_cr[0:0] - attribute \src "libresoc.v:167081.3-167121.6" - wire $0\sr_op__rc__ok$next[0:0]$9207 - attribute \src "libresoc.v:166901.3-166902.43" + attribute \src "libresoc.v:168389.3-168429.6" + wire $0\sr_op__rc__ok$next[0:0]$9191 + attribute \src "libresoc.v:168209.3-168210.43" wire $0\sr_op__rc__ok[0:0] - attribute \src "libresoc.v:167081.3-167121.6" - wire $0\sr_op__rc__rc$next[0:0]$9208 - attribute \src "libresoc.v:166899.3-166900.43" + attribute \src "libresoc.v:168389.3-168429.6" + wire $0\sr_op__rc__rc$next[0:0]$9192 + attribute \src "libresoc.v:168207.3-168208.43" wire $0\sr_op__rc__rc[0:0] - attribute \src "libresoc.v:167081.3-167121.6" - wire $0\sr_op__write_cr0$next[0:0]$9209 - attribute \src "libresoc.v:166907.3-166908.49" + attribute \src "libresoc.v:168389.3-168429.6" + wire $0\sr_op__write_cr0$next[0:0]$9193 + attribute \src "libresoc.v:168215.3-168216.49" wire $0\sr_op__write_cr0[0:0] - attribute \src "libresoc.v:167031.3-167049.6" - wire width 2 $0\xer_ca$next[1:0]$9181 - attribute \src "libresoc.v:166875.3-166876.29" + attribute \src "libresoc.v:168339.3-168357.6" + wire width 2 $0\xer_ca$next[1:0]$9165 + attribute \src "libresoc.v:168183.3-168184.29" wire width 2 $0\xer_ca[1:0] - attribute \src "libresoc.v:167031.3-167049.6" - wire $0\xer_ca_ok$next[0:0]$9180 - attribute \src "libresoc.v:166877.3-166878.35" + attribute \src "libresoc.v:168339.3-168357.6" + wire $0\xer_ca_ok$next[0:0]$9164 + attribute \src "libresoc.v:168185.3-168186.35" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:167160.3-167178.6" - wire $0\xer_so$next[0:0]$9246 - attribute \src "libresoc.v:166879.3-166880.29" + attribute \src "libresoc.v:168468.3-168486.6" + wire $0\xer_so$next[0:0]$9230 + attribute \src "libresoc.v:168187.3-168188.29" wire $0\xer_so[0:0] - attribute \src "libresoc.v:167160.3-167178.6" - wire $0\xer_so_ok$next[0:0]$9247 - attribute \src "libresoc.v:166881.3-166882.35" + attribute \src "libresoc.v:168468.3-168486.6" + wire $0\xer_so_ok$next[0:0]$9231 + attribute \src "libresoc.v:168189.3-168190.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:167141.3-167159.6" - wire width 4 $1\cr_a$next[3:0]$9242 - attribute \src "libresoc.v:165782.13-165782.24" + attribute \src "libresoc.v:168449.3-168467.6" + wire width 4 $1\cr_a$next[3:0]$9226 + attribute \src "libresoc.v:167090.13-167090.24" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:167141.3-167159.6" - wire $1\cr_a_ok$next[0:0]$9243 - attribute \src "libresoc.v:165791.7-165791.21" + attribute \src "libresoc.v:168449.3-168467.6" + wire $1\cr_a_ok$next[0:0]$9227 + attribute \src "libresoc.v:167099.7-167099.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:167068.3-167080.6" - wire width 2 $1\muxid$next[1:0]$9191 - attribute \src "libresoc.v:166356.13-166356.25" + attribute \src "libresoc.v:168376.3-168388.6" + wire width 2 $1\muxid$next[1:0]$9175 + attribute \src "libresoc.v:167664.13-167664.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:167122.3-167140.6" - wire width 64 $1\o$next[63:0]$9236 - attribute \src "libresoc.v:166371.14-166371.38" + attribute \src "libresoc.v:168430.3-168448.6" + wire width 64 $1\o$next[63:0]$9220 + attribute \src "libresoc.v:167679.14-167679.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:167122.3-167140.6" - wire $1\o_ok$next[0:0]$9237 - attribute \src "libresoc.v:166378.7-166378.18" + attribute \src "libresoc.v:168430.3-168448.6" + wire $1\o_ok$next[0:0]$9221 + attribute \src "libresoc.v:167686.7-167686.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:167050.3-167067.6" - wire $1\r_busy$next[0:0]$9187 - attribute \src "libresoc.v:166392.7-166392.20" + attribute \src "libresoc.v:168358.3-168375.6" + wire $1\r_busy$next[0:0]$9171 + attribute \src "libresoc.v:167700.7-167700.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:167081.3-167121.6" - wire width 14 $1\sr_op__fn_unit$next[13:0]$9210 - attribute \src "libresoc.v:166418.14-166418.39" + attribute \src "libresoc.v:168389.3-168429.6" + wire width 14 $1\sr_op__fn_unit$next[13:0]$9194 + attribute \src "libresoc.v:167726.14-167726.39" wire width 14 $1\sr_op__fn_unit[13:0] - attribute \src "libresoc.v:167081.3-167121.6" - wire width 64 $1\sr_op__imm_data__data$next[63:0]$9211 - attribute \src "libresoc.v:166457.14-166457.58" + attribute \src "libresoc.v:168389.3-168429.6" + wire width 64 $1\sr_op__imm_data__data$next[63:0]$9195 + attribute \src "libresoc.v:167765.14-167765.58" wire width 64 $1\sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:167081.3-167121.6" - wire $1\sr_op__imm_data__ok$next[0:0]$9212 - attribute \src "libresoc.v:166466.7-166466.33" + attribute \src "libresoc.v:168389.3-168429.6" + wire $1\sr_op__imm_data__ok$next[0:0]$9196 + attribute \src "libresoc.v:167774.7-167774.33" wire $1\sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:167081.3-167121.6" - wire width 2 $1\sr_op__input_carry$next[1:0]$9213 - attribute \src "libresoc.v:166479.13-166479.38" + attribute \src "libresoc.v:168389.3-168429.6" + wire width 2 $1\sr_op__input_carry$next[1:0]$9197 + attribute \src "libresoc.v:167787.13-167787.38" wire width 2 $1\sr_op__input_carry[1:0] - attribute \src "libresoc.v:167081.3-167121.6" - wire $1\sr_op__input_cr$next[0:0]$9214 - attribute \src "libresoc.v:166496.7-166496.29" + attribute \src "libresoc.v:168389.3-168429.6" + wire $1\sr_op__input_cr$next[0:0]$9198 + attribute \src "libresoc.v:167804.7-167804.29" wire $1\sr_op__input_cr[0:0] - attribute \src "libresoc.v:167081.3-167121.6" - wire width 32 $1\sr_op__insn$next[31:0]$9215 - attribute \src "libresoc.v:166505.14-166505.33" + attribute \src "libresoc.v:168389.3-168429.6" + wire width 32 $1\sr_op__insn$next[31:0]$9199 + attribute \src "libresoc.v:167813.14-167813.33" wire width 32 $1\sr_op__insn[31:0] - attribute \src "libresoc.v:167081.3-167121.6" - wire width 7 $1\sr_op__insn_type$next[6:0]$9216 - attribute \src "libresoc.v:166589.13-166589.37" + attribute \src "libresoc.v:168389.3-168429.6" + wire width 7 $1\sr_op__insn_type$next[6:0]$9200 + attribute \src "libresoc.v:167897.13-167897.37" wire width 7 $1\sr_op__insn_type[6:0] - attribute \src "libresoc.v:167081.3-167121.6" - wire $1\sr_op__invert_in$next[0:0]$9217 - attribute \src "libresoc.v:166748.7-166748.30" + attribute \src "libresoc.v:168389.3-168429.6" + wire $1\sr_op__invert_in$next[0:0]$9201 + attribute \src "libresoc.v:168056.7-168056.30" wire $1\sr_op__invert_in[0:0] - attribute \src "libresoc.v:167081.3-167121.6" - wire $1\sr_op__is_32bit$next[0:0]$9218 - attribute \src "libresoc.v:166757.7-166757.29" + attribute \src "libresoc.v:168389.3-168429.6" + wire $1\sr_op__is_32bit$next[0:0]$9202 + attribute \src "libresoc.v:168065.7-168065.29" wire $1\sr_op__is_32bit[0:0] - attribute \src "libresoc.v:167081.3-167121.6" - wire $1\sr_op__is_signed$next[0:0]$9219 - attribute \src "libresoc.v:166766.7-166766.30" + attribute \src "libresoc.v:168389.3-168429.6" + wire $1\sr_op__is_signed$next[0:0]$9203 + attribute \src "libresoc.v:168074.7-168074.30" wire $1\sr_op__is_signed[0:0] - attribute \src "libresoc.v:167081.3-167121.6" - wire $1\sr_op__oe__oe$next[0:0]$9220 - attribute \src "libresoc.v:166775.7-166775.27" + attribute \src "libresoc.v:168389.3-168429.6" + wire $1\sr_op__oe__oe$next[0:0]$9204 + attribute \src "libresoc.v:168083.7-168083.27" wire $1\sr_op__oe__oe[0:0] - attribute \src "libresoc.v:167081.3-167121.6" - wire $1\sr_op__oe__ok$next[0:0]$9221 - attribute \src "libresoc.v:166784.7-166784.27" + attribute \src "libresoc.v:168389.3-168429.6" + wire $1\sr_op__oe__ok$next[0:0]$9205 + attribute \src "libresoc.v:168092.7-168092.27" wire $1\sr_op__oe__ok[0:0] - attribute \src "libresoc.v:167081.3-167121.6" - wire $1\sr_op__output_carry$next[0:0]$9222 - attribute \src "libresoc.v:166793.7-166793.33" + attribute \src "libresoc.v:168389.3-168429.6" + wire $1\sr_op__output_carry$next[0:0]$9206 + attribute \src "libresoc.v:168101.7-168101.33" wire $1\sr_op__output_carry[0:0] - attribute \src "libresoc.v:167081.3-167121.6" - wire $1\sr_op__output_cr$next[0:0]$9223 - attribute \src "libresoc.v:166802.7-166802.30" + attribute \src "libresoc.v:168389.3-168429.6" + wire $1\sr_op__output_cr$next[0:0]$9207 + attribute \src "libresoc.v:168110.7-168110.30" wire $1\sr_op__output_cr[0:0] - attribute \src "libresoc.v:167081.3-167121.6" - wire $1\sr_op__rc__ok$next[0:0]$9224 - attribute \src "libresoc.v:166811.7-166811.27" + attribute \src "libresoc.v:168389.3-168429.6" + wire $1\sr_op__rc__ok$next[0:0]$9208 + attribute \src "libresoc.v:168119.7-168119.27" wire $1\sr_op__rc__ok[0:0] - attribute \src "libresoc.v:167081.3-167121.6" - wire $1\sr_op__rc__rc$next[0:0]$9225 - attribute \src "libresoc.v:166820.7-166820.27" + attribute \src "libresoc.v:168389.3-168429.6" + wire $1\sr_op__rc__rc$next[0:0]$9209 + attribute \src "libresoc.v:168128.7-168128.27" wire $1\sr_op__rc__rc[0:0] - attribute \src "libresoc.v:167081.3-167121.6" - wire $1\sr_op__write_cr0$next[0:0]$9226 - attribute \src "libresoc.v:166829.7-166829.30" + attribute \src "libresoc.v:168389.3-168429.6" + wire $1\sr_op__write_cr0$next[0:0]$9210 + attribute \src "libresoc.v:168137.7-168137.30" wire $1\sr_op__write_cr0[0:0] - attribute \src "libresoc.v:167031.3-167049.6" - wire width 2 $1\xer_ca$next[1:0]$9183 - attribute \src "libresoc.v:166838.13-166838.26" + attribute \src "libresoc.v:168339.3-168357.6" + wire width 2 $1\xer_ca$next[1:0]$9167 + attribute \src "libresoc.v:168146.13-168146.26" wire width 2 $1\xer_ca[1:0] - attribute \src "libresoc.v:167031.3-167049.6" - wire $1\xer_ca_ok$next[0:0]$9182 - attribute \src "libresoc.v:166849.7-166849.23" + attribute \src "libresoc.v:168339.3-168357.6" + wire $1\xer_ca_ok$next[0:0]$9166 + attribute \src "libresoc.v:168157.7-168157.23" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:167160.3-167178.6" - wire $1\xer_so$next[0:0]$9248 - attribute \src "libresoc.v:166858.7-166858.20" + attribute \src "libresoc.v:168468.3-168486.6" + wire $1\xer_so$next[0:0]$9232 + attribute \src "libresoc.v:168166.7-168166.20" wire $1\xer_so[0:0] - attribute \src "libresoc.v:167160.3-167178.6" - wire $1\xer_so_ok$next[0:0]$9249 - attribute \src "libresoc.v:166867.7-166867.23" + attribute \src "libresoc.v:168468.3-168486.6" + wire $1\xer_so_ok$next[0:0]$9233 + attribute \src "libresoc.v:168175.7-168175.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:167141.3-167159.6" - wire $2\cr_a_ok$next[0:0]$9244 - attribute \src "libresoc.v:167122.3-167140.6" - wire $2\o_ok$next[0:0]$9238 - attribute \src "libresoc.v:167050.3-167067.6" - wire $2\r_busy$next[0:0]$9188 - attribute \src "libresoc.v:167081.3-167121.6" - wire width 64 $2\sr_op__imm_data__data$next[63:0]$9227 - attribute \src "libresoc.v:167081.3-167121.6" - wire $2\sr_op__imm_data__ok$next[0:0]$9228 - attribute \src "libresoc.v:167081.3-167121.6" - wire $2\sr_op__oe__oe$next[0:0]$9229 - attribute \src "libresoc.v:167081.3-167121.6" - wire $2\sr_op__oe__ok$next[0:0]$9230 - attribute \src "libresoc.v:167081.3-167121.6" - wire $2\sr_op__rc__ok$next[0:0]$9231 - attribute \src "libresoc.v:167081.3-167121.6" - wire $2\sr_op__rc__rc$next[0:0]$9232 - attribute \src "libresoc.v:167031.3-167049.6" - wire $2\xer_ca_ok$next[0:0]$9184 - attribute \src "libresoc.v:167160.3-167178.6" - wire $2\xer_so_ok$next[0:0]$9250 - attribute \src "libresoc.v:166874.18-166874.118" - wire $and$libresoc.v:166874$9151_Y + attribute \src "libresoc.v:168449.3-168467.6" + wire $2\cr_a_ok$next[0:0]$9228 + attribute \src "libresoc.v:168430.3-168448.6" + wire $2\o_ok$next[0:0]$9222 + attribute \src "libresoc.v:168358.3-168375.6" + wire $2\r_busy$next[0:0]$9172 + attribute \src "libresoc.v:168389.3-168429.6" + wire width 64 $2\sr_op__imm_data__data$next[63:0]$9211 + attribute \src "libresoc.v:168389.3-168429.6" + wire $2\sr_op__imm_data__ok$next[0:0]$9212 + attribute \src "libresoc.v:168389.3-168429.6" + wire $2\sr_op__oe__oe$next[0:0]$9213 + attribute \src "libresoc.v:168389.3-168429.6" + wire $2\sr_op__oe__ok$next[0:0]$9214 + attribute \src "libresoc.v:168389.3-168429.6" + wire $2\sr_op__rc__ok$next[0:0]$9215 + attribute \src "libresoc.v:168389.3-168429.6" + wire $2\sr_op__rc__rc$next[0:0]$9216 + attribute \src "libresoc.v:168339.3-168357.6" + wire $2\xer_ca_ok$next[0:0]$9168 + attribute \src "libresoc.v:168468.3-168486.6" + wire $2\xer_so_ok$next[0:0]$9234 + attribute \src "libresoc.v:168182.18-168182.118" + wire $and$libresoc.v:168182$9135_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 55 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 24 \cr_a @@ -339635,7 +311005,7 @@ module \pipe1$110 wire \cr_a_ok$90 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$next - attribute \src "libresoc.v:165773.7-165773.15" + attribute \src "libresoc.v:167081.7-167081.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 \input_muxid @@ -340690,7 +312060,7 @@ module \pipe1$110 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:166874$9151 + cell $and $and$libresoc.v:168182$9135 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -340698,10 +312068,10 @@ module \pipe1$110 parameter \Y_WIDTH 1 connect \A \p_valid_i$64 connect \B \p_ready_o - connect \Y $and$libresoc.v:166874$9151_Y + connect \Y $and$libresoc.v:168182$9135_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:166929.15-166976.4" + attribute \src "libresoc.v:168237.15-168284.4" cell \input$113 \input connect \muxid \input_muxid connect \muxid$1 \input_muxid$21 @@ -340751,7 +312121,7 @@ module \pipe1$110 connect \xer_so$22 \input_xer_so$42 end attribute \module_not_derived 1 - attribute \src "libresoc.v:166977.14-167022.4" + attribute \src "libresoc.v:168285.14-168330.4" cell \main$114 \main connect \muxid \main_muxid connect \muxid$1 \main_muxid$44 @@ -340799,442 +312169,442 @@ module \pipe1$110 connect \xer_so$19 \main_xer_so$62 end attribute \module_not_derived 1 - attribute \src "libresoc.v:167023.11-167026.4" + attribute \src "libresoc.v:168331.11-168334.4" cell \n$112 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:167027.11-167030.4" + attribute \src "libresoc.v:168335.11-168338.4" cell \p$111 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:165773.7-165773.20" - process $proc$libresoc.v:165773$9251 + attribute \src "libresoc.v:167081.7-167081.20" + process $proc$libresoc.v:167081$9235 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:165782.13-165782.24" - process $proc$libresoc.v:165782$9252 + attribute \src "libresoc.v:167090.13-167090.24" + process $proc$libresoc.v:167090$9236 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:165791.7-165791.21" - process $proc$libresoc.v:165791$9253 + attribute \src "libresoc.v:167099.7-167099.21" + process $proc$libresoc.v:167099$9237 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:166356.13-166356.25" - process $proc$libresoc.v:166356$9254 + attribute \src "libresoc.v:167664.13-167664.25" + process $proc$libresoc.v:167664$9238 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:166371.14-166371.38" - process $proc$libresoc.v:166371$9255 + attribute \src "libresoc.v:167679.14-167679.38" + process $proc$libresoc.v:167679$9239 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:166378.7-166378.18" - process $proc$libresoc.v:166378$9256 + attribute \src "libresoc.v:167686.7-167686.18" + process $proc$libresoc.v:167686$9240 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:166392.7-166392.20" - process $proc$libresoc.v:166392$9257 + attribute \src "libresoc.v:167700.7-167700.20" + process $proc$libresoc.v:167700$9241 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:166418.14-166418.39" - process $proc$libresoc.v:166418$9258 + attribute \src "libresoc.v:167726.14-167726.39" + process $proc$libresoc.v:167726$9242 assign { } { } assign $1\sr_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \sr_op__fn_unit $1\sr_op__fn_unit[13:0] end - attribute \src "libresoc.v:166457.14-166457.58" - process $proc$libresoc.v:166457$9259 + attribute \src "libresoc.v:167765.14-167765.58" + process $proc$libresoc.v:167765$9243 assign { } { } assign $1\sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \sr_op__imm_data__data $1\sr_op__imm_data__data[63:0] end - attribute \src "libresoc.v:166466.7-166466.33" - process $proc$libresoc.v:166466$9260 + attribute \src "libresoc.v:167774.7-167774.33" + process $proc$libresoc.v:167774$9244 assign { } { } assign $1\sr_op__imm_data__ok[0:0] 1'0 sync always sync init update \sr_op__imm_data__ok $1\sr_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:166479.13-166479.38" - process $proc$libresoc.v:166479$9261 + attribute \src "libresoc.v:167787.13-167787.38" + process $proc$libresoc.v:167787$9245 assign { } { } assign $1\sr_op__input_carry[1:0] 2'00 sync always sync init update \sr_op__input_carry $1\sr_op__input_carry[1:0] end - attribute \src "libresoc.v:166496.7-166496.29" - process $proc$libresoc.v:166496$9262 + attribute \src "libresoc.v:167804.7-167804.29" + process $proc$libresoc.v:167804$9246 assign { } { } assign $1\sr_op__input_cr[0:0] 1'0 sync always sync init update \sr_op__input_cr $1\sr_op__input_cr[0:0] end - attribute \src "libresoc.v:166505.14-166505.33" - process $proc$libresoc.v:166505$9263 + attribute \src "libresoc.v:167813.14-167813.33" + process $proc$libresoc.v:167813$9247 assign { } { } assign $1\sr_op__insn[31:0] 0 sync always sync init update \sr_op__insn $1\sr_op__insn[31:0] end - attribute \src "libresoc.v:166589.13-166589.37" - process $proc$libresoc.v:166589$9264 + attribute \src "libresoc.v:167897.13-167897.37" + process $proc$libresoc.v:167897$9248 assign { } { } assign $1\sr_op__insn_type[6:0] 7'0000000 sync always sync init update \sr_op__insn_type $1\sr_op__insn_type[6:0] end - attribute \src "libresoc.v:166748.7-166748.30" - process $proc$libresoc.v:166748$9265 + attribute \src "libresoc.v:168056.7-168056.30" + process $proc$libresoc.v:168056$9249 assign { } { } assign $1\sr_op__invert_in[0:0] 1'0 sync always sync init update \sr_op__invert_in $1\sr_op__invert_in[0:0] end - attribute \src "libresoc.v:166757.7-166757.29" - process $proc$libresoc.v:166757$9266 + attribute \src "libresoc.v:168065.7-168065.29" + process $proc$libresoc.v:168065$9250 assign { } { } assign $1\sr_op__is_32bit[0:0] 1'0 sync always sync init update \sr_op__is_32bit $1\sr_op__is_32bit[0:0] end - attribute \src "libresoc.v:166766.7-166766.30" - process $proc$libresoc.v:166766$9267 + attribute \src "libresoc.v:168074.7-168074.30" + process $proc$libresoc.v:168074$9251 assign { } { } assign $1\sr_op__is_signed[0:0] 1'0 sync always sync init update \sr_op__is_signed $1\sr_op__is_signed[0:0] end - attribute \src "libresoc.v:166775.7-166775.27" - process $proc$libresoc.v:166775$9268 + attribute \src "libresoc.v:168083.7-168083.27" + process $proc$libresoc.v:168083$9252 assign { } { } assign $1\sr_op__oe__oe[0:0] 1'0 sync always sync init update \sr_op__oe__oe $1\sr_op__oe__oe[0:0] end - attribute \src "libresoc.v:166784.7-166784.27" - process $proc$libresoc.v:166784$9269 + attribute \src "libresoc.v:168092.7-168092.27" + process $proc$libresoc.v:168092$9253 assign { } { } assign $1\sr_op__oe__ok[0:0] 1'0 sync always sync init update \sr_op__oe__ok $1\sr_op__oe__ok[0:0] end - attribute \src "libresoc.v:166793.7-166793.33" - process $proc$libresoc.v:166793$9270 + attribute \src "libresoc.v:168101.7-168101.33" + process $proc$libresoc.v:168101$9254 assign { } { } assign $1\sr_op__output_carry[0:0] 1'0 sync always sync init update \sr_op__output_carry $1\sr_op__output_carry[0:0] end - attribute \src "libresoc.v:166802.7-166802.30" - process $proc$libresoc.v:166802$9271 + attribute \src "libresoc.v:168110.7-168110.30" + process $proc$libresoc.v:168110$9255 assign { } { } assign $1\sr_op__output_cr[0:0] 1'0 sync always sync init update \sr_op__output_cr $1\sr_op__output_cr[0:0] end - attribute \src "libresoc.v:166811.7-166811.27" - process $proc$libresoc.v:166811$9272 + attribute \src "libresoc.v:168119.7-168119.27" + process $proc$libresoc.v:168119$9256 assign { } { } assign $1\sr_op__rc__ok[0:0] 1'0 sync always sync init update \sr_op__rc__ok $1\sr_op__rc__ok[0:0] end - attribute \src "libresoc.v:166820.7-166820.27" - process $proc$libresoc.v:166820$9273 + attribute \src "libresoc.v:168128.7-168128.27" + process $proc$libresoc.v:168128$9257 assign { } { } assign $1\sr_op__rc__rc[0:0] 1'0 sync always sync init update \sr_op__rc__rc $1\sr_op__rc__rc[0:0] end - attribute \src "libresoc.v:166829.7-166829.30" - process $proc$libresoc.v:166829$9274 + attribute \src "libresoc.v:168137.7-168137.30" + process $proc$libresoc.v:168137$9258 assign { } { } assign $1\sr_op__write_cr0[0:0] 1'0 sync always sync init update \sr_op__write_cr0 $1\sr_op__write_cr0[0:0] end - attribute \src "libresoc.v:166838.13-166838.26" - process $proc$libresoc.v:166838$9275 + attribute \src "libresoc.v:168146.13-168146.26" + process $proc$libresoc.v:168146$9259 assign { } { } assign $1\xer_ca[1:0] 2'00 sync always sync init update \xer_ca $1\xer_ca[1:0] end - attribute \src "libresoc.v:166849.7-166849.23" - process $proc$libresoc.v:166849$9276 + attribute \src "libresoc.v:168157.7-168157.23" + process $proc$libresoc.v:168157$9260 assign { } { } assign $1\xer_ca_ok[0:0] 1'0 sync always sync init update \xer_ca_ok $1\xer_ca_ok[0:0] end - attribute \src "libresoc.v:166858.7-166858.20" - process $proc$libresoc.v:166858$9277 + attribute \src "libresoc.v:168166.7-168166.20" + process $proc$libresoc.v:168166$9261 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:166867.7-166867.23" - process $proc$libresoc.v:166867$9278 + attribute \src "libresoc.v:168175.7-168175.23" + process $proc$libresoc.v:168175$9262 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:166875.3-166876.29" - process $proc$libresoc.v:166875$9152 + attribute \src "libresoc.v:168183.3-168184.29" + process $proc$libresoc.v:168183$9136 assign { } { } assign $0\xer_ca[1:0] \xer_ca$next sync posedge \coresync_clk update \xer_ca $0\xer_ca[1:0] end - attribute \src "libresoc.v:166877.3-166878.35" - process $proc$libresoc.v:166877$9153 + attribute \src "libresoc.v:168185.3-168186.35" + process $proc$libresoc.v:168185$9137 assign { } { } assign $0\xer_ca_ok[0:0] \xer_ca_ok$next sync posedge \coresync_clk update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:166879.3-166880.29" - process $proc$libresoc.v:166879$9154 + attribute \src "libresoc.v:168187.3-168188.29" + process $proc$libresoc.v:168187$9138 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:166881.3-166882.35" - process $proc$libresoc.v:166881$9155 + attribute \src "libresoc.v:168189.3-168190.35" + process $proc$libresoc.v:168189$9139 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:166883.3-166884.25" - process $proc$libresoc.v:166883$9156 + attribute \src "libresoc.v:168191.3-168192.25" + process $proc$libresoc.v:168191$9140 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:166885.3-166886.31" - process $proc$libresoc.v:166885$9157 + attribute \src "libresoc.v:168193.3-168194.31" + process $proc$libresoc.v:168193$9141 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:166887.3-166888.19" - process $proc$libresoc.v:166887$9158 + attribute \src "libresoc.v:168195.3-168196.19" + process $proc$libresoc.v:168195$9142 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:166889.3-166890.25" - process $proc$libresoc.v:166889$9159 + attribute \src "libresoc.v:168197.3-168198.25" + process $proc$libresoc.v:168197$9143 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:166891.3-166892.49" - process $proc$libresoc.v:166891$9160 + attribute \src "libresoc.v:168199.3-168200.49" + process $proc$libresoc.v:168199$9144 assign { } { } assign $0\sr_op__insn_type[6:0] \sr_op__insn_type$next sync posedge \coresync_clk update \sr_op__insn_type $0\sr_op__insn_type[6:0] end - attribute \src "libresoc.v:166893.3-166894.45" - process $proc$libresoc.v:166893$9161 + attribute \src "libresoc.v:168201.3-168202.45" + process $proc$libresoc.v:168201$9145 assign { } { } assign $0\sr_op__fn_unit[13:0] \sr_op__fn_unit$next sync posedge \coresync_clk update \sr_op__fn_unit $0\sr_op__fn_unit[13:0] end - attribute \src "libresoc.v:166895.3-166896.59" - process $proc$libresoc.v:166895$9162 + attribute \src "libresoc.v:168203.3-168204.59" + process $proc$libresoc.v:168203$9146 assign { } { } assign $0\sr_op__imm_data__data[63:0] \sr_op__imm_data__data$next sync posedge \coresync_clk update \sr_op__imm_data__data $0\sr_op__imm_data__data[63:0] end - attribute \src "libresoc.v:166897.3-166898.55" - process $proc$libresoc.v:166897$9163 + attribute \src "libresoc.v:168205.3-168206.55" + process $proc$libresoc.v:168205$9147 assign { } { } assign $0\sr_op__imm_data__ok[0:0] \sr_op__imm_data__ok$next sync posedge \coresync_clk update \sr_op__imm_data__ok $0\sr_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:166899.3-166900.43" - process $proc$libresoc.v:166899$9164 + attribute \src "libresoc.v:168207.3-168208.43" + process $proc$libresoc.v:168207$9148 assign { } { } assign $0\sr_op__rc__rc[0:0] \sr_op__rc__rc$next sync posedge \coresync_clk update \sr_op__rc__rc $0\sr_op__rc__rc[0:0] end - attribute \src "libresoc.v:166901.3-166902.43" - process $proc$libresoc.v:166901$9165 + attribute \src "libresoc.v:168209.3-168210.43" + process $proc$libresoc.v:168209$9149 assign { } { } assign $0\sr_op__rc__ok[0:0] \sr_op__rc__ok$next sync posedge \coresync_clk update \sr_op__rc__ok $0\sr_op__rc__ok[0:0] end - attribute \src "libresoc.v:166903.3-166904.43" - process $proc$libresoc.v:166903$9166 + attribute \src "libresoc.v:168211.3-168212.43" + process $proc$libresoc.v:168211$9150 assign { } { } assign $0\sr_op__oe__oe[0:0] \sr_op__oe__oe$next sync posedge \coresync_clk update \sr_op__oe__oe $0\sr_op__oe__oe[0:0] end - attribute \src "libresoc.v:166905.3-166906.43" - process $proc$libresoc.v:166905$9167 + attribute \src "libresoc.v:168213.3-168214.43" + process $proc$libresoc.v:168213$9151 assign { } { } assign $0\sr_op__oe__ok[0:0] \sr_op__oe__ok$next sync posedge \coresync_clk update \sr_op__oe__ok $0\sr_op__oe__ok[0:0] end - attribute \src "libresoc.v:166907.3-166908.49" - process $proc$libresoc.v:166907$9168 + attribute \src "libresoc.v:168215.3-168216.49" + process $proc$libresoc.v:168215$9152 assign { } { } assign $0\sr_op__write_cr0[0:0] \sr_op__write_cr0$next sync posedge \coresync_clk update \sr_op__write_cr0 $0\sr_op__write_cr0[0:0] end - attribute \src "libresoc.v:166909.3-166910.49" - process $proc$libresoc.v:166909$9169 + attribute \src "libresoc.v:168217.3-168218.49" + process $proc$libresoc.v:168217$9153 assign { } { } assign $0\sr_op__invert_in[0:0] \sr_op__invert_in$next sync posedge \coresync_clk update \sr_op__invert_in $0\sr_op__invert_in[0:0] end - attribute \src "libresoc.v:166911.3-166912.53" - process $proc$libresoc.v:166911$9170 + attribute \src "libresoc.v:168219.3-168220.53" + process $proc$libresoc.v:168219$9154 assign { } { } assign $0\sr_op__input_carry[1:0] \sr_op__input_carry$next sync posedge \coresync_clk update \sr_op__input_carry $0\sr_op__input_carry[1:0] end - attribute \src "libresoc.v:166913.3-166914.55" - process $proc$libresoc.v:166913$9171 + attribute \src "libresoc.v:168221.3-168222.55" + process $proc$libresoc.v:168221$9155 assign { } { } assign $0\sr_op__output_carry[0:0] \sr_op__output_carry$next sync posedge \coresync_clk update \sr_op__output_carry $0\sr_op__output_carry[0:0] end - attribute \src "libresoc.v:166915.3-166916.47" - process $proc$libresoc.v:166915$9172 + attribute \src "libresoc.v:168223.3-168224.47" + process $proc$libresoc.v:168223$9156 assign { } { } assign $0\sr_op__input_cr[0:0] \sr_op__input_cr$next sync posedge \coresync_clk update \sr_op__input_cr $0\sr_op__input_cr[0:0] end - attribute \src "libresoc.v:166917.3-166918.49" - process $proc$libresoc.v:166917$9173 + attribute \src "libresoc.v:168225.3-168226.49" + process $proc$libresoc.v:168225$9157 assign { } { } assign $0\sr_op__output_cr[0:0] \sr_op__output_cr$next sync posedge \coresync_clk update \sr_op__output_cr $0\sr_op__output_cr[0:0] end - attribute \src "libresoc.v:166919.3-166920.47" - process $proc$libresoc.v:166919$9174 + attribute \src "libresoc.v:168227.3-168228.47" + process $proc$libresoc.v:168227$9158 assign { } { } assign $0\sr_op__is_32bit[0:0] \sr_op__is_32bit$next sync posedge \coresync_clk update \sr_op__is_32bit $0\sr_op__is_32bit[0:0] end - attribute \src "libresoc.v:166921.3-166922.49" - process $proc$libresoc.v:166921$9175 + attribute \src "libresoc.v:168229.3-168230.49" + process $proc$libresoc.v:168229$9159 assign { } { } assign $0\sr_op__is_signed[0:0] \sr_op__is_signed$next sync posedge \coresync_clk update \sr_op__is_signed $0\sr_op__is_signed[0:0] end - attribute \src "libresoc.v:166923.3-166924.39" - process $proc$libresoc.v:166923$9176 + attribute \src "libresoc.v:168231.3-168232.39" + process $proc$libresoc.v:168231$9160 assign { } { } assign $0\sr_op__insn[31:0] \sr_op__insn$next sync posedge \coresync_clk update \sr_op__insn $0\sr_op__insn[31:0] end - attribute \src "libresoc.v:166925.3-166926.27" - process $proc$libresoc.v:166925$9177 + attribute \src "libresoc.v:168233.3-168234.27" + process $proc$libresoc.v:168233$9161 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:166927.3-166928.29" - process $proc$libresoc.v:166927$9178 + attribute \src "libresoc.v:168235.3-168236.29" + process $proc$libresoc.v:168235$9162 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:167031.3-167049.6" - process $proc$libresoc.v:167031$9179 + attribute \src "libresoc.v:168339.3-168357.6" + process $proc$libresoc.v:168339$9163 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ca$next[1:0]$9181 $1\xer_ca$next[1:0]$9183 - assign $0\xer_ca_ok$next[0:0]$9180 $2\xer_ca_ok$next[0:0]$9184 - attribute \src "libresoc.v:167032.5-167032.29" + assign $0\xer_ca$next[1:0]$9165 $1\xer_ca$next[1:0]$9167 + assign $0\xer_ca_ok$next[0:0]$9164 $2\xer_ca_ok$next[0:0]$9168 + attribute \src "libresoc.v:168340.5-168340.29" switch \initial - attribute \src "libresoc.v:167032.9-167032.17" + attribute \src "libresoc.v:168340.9-168340.17" case 1'1 case end @@ -341244,38 +312614,38 @@ module \pipe1$110 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ca_ok$next[0:0]$9182 $1\xer_ca$next[1:0]$9183 } { \xer_ca_ok$95 \xer_ca$94 } + assign { $1\xer_ca_ok$next[0:0]$9166 $1\xer_ca$next[1:0]$9167 } { \xer_ca_ok$95 \xer_ca$94 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ca_ok$next[0:0]$9182 $1\xer_ca$next[1:0]$9183 } { \xer_ca_ok$95 \xer_ca$94 } + assign { $1\xer_ca_ok$next[0:0]$9166 $1\xer_ca$next[1:0]$9167 } { \xer_ca_ok$95 \xer_ca$94 } case - assign $1\xer_ca_ok$next[0:0]$9182 \xer_ca_ok - assign $1\xer_ca$next[1:0]$9183 \xer_ca + assign $1\xer_ca_ok$next[0:0]$9166 \xer_ca_ok + assign $1\xer_ca$next[1:0]$9167 \xer_ca end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ca_ok$next[0:0]$9184 1'0 + assign $2\xer_ca_ok$next[0:0]$9168 1'0 case - assign $2\xer_ca_ok$next[0:0]$9184 $1\xer_ca_ok$next[0:0]$9182 + assign $2\xer_ca_ok$next[0:0]$9168 $1\xer_ca_ok$next[0:0]$9166 end sync always - update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$9180 - update \xer_ca$next $0\xer_ca$next[1:0]$9181 + update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$9164 + update \xer_ca$next $0\xer_ca$next[1:0]$9165 end - attribute \src "libresoc.v:167050.3-167067.6" - process $proc$libresoc.v:167050$9185 + attribute \src "libresoc.v:168358.3-168375.6" + process $proc$libresoc.v:168358$9169 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9186 $2\r_busy$next[0:0]$9188 - attribute \src "libresoc.v:167051.5-167051.29" + assign $0\r_busy$next[0:0]$9170 $2\r_busy$next[0:0]$9172 + attribute \src "libresoc.v:168359.5-168359.29" switch \initial - attribute \src "libresoc.v:167051.9-167051.17" + attribute \src "libresoc.v:168359.9-168359.17" case 1'1 case end @@ -341284,34 +312654,34 @@ module \pipe1$110 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9187 1'1 + assign $1\r_busy$next[0:0]$9171 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9187 1'0 + assign $1\r_busy$next[0:0]$9171 1'0 case - assign $1\r_busy$next[0:0]$9187 \r_busy + assign $1\r_busy$next[0:0]$9171 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9188 1'0 + assign $2\r_busy$next[0:0]$9172 1'0 case - assign $2\r_busy$next[0:0]$9188 $1\r_busy$next[0:0]$9187 + assign $2\r_busy$next[0:0]$9172 $1\r_busy$next[0:0]$9171 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9186 + update \r_busy$next $0\r_busy$next[0:0]$9170 end - attribute \src "libresoc.v:167068.3-167080.6" - process $proc$libresoc.v:167068$9189 + attribute \src "libresoc.v:168376.3-168388.6" + process $proc$libresoc.v:168376$9173 assign { } { } assign { } { } - assign $0\muxid$next[1:0]$9190 $1\muxid$next[1:0]$9191 - attribute \src "libresoc.v:167069.5-167069.29" + assign $0\muxid$next[1:0]$9174 $1\muxid$next[1:0]$9175 + attribute \src "libresoc.v:168377.5-168377.29" switch \initial - attribute \src "libresoc.v:167069.9-167069.17" + attribute \src "libresoc.v:168377.9-168377.17" case 1'1 case end @@ -341320,19 +312690,19 @@ module \pipe1$110 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$next[1:0]$9191 \muxid$67 + assign $1\muxid$next[1:0]$9175 \muxid$67 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$next[1:0]$9191 \muxid$67 + assign $1\muxid$next[1:0]$9175 \muxid$67 case - assign $1\muxid$next[1:0]$9191 \muxid + assign $1\muxid$next[1:0]$9175 \muxid end sync always - update \muxid$next $0\muxid$next[1:0]$9190 + update \muxid$next $0\muxid$next[1:0]$9174 end - attribute \src "libresoc.v:167081.3-167121.6" - process $proc$libresoc.v:167081$9192 + attribute \src "libresoc.v:168389.3-168429.6" + process $proc$libresoc.v:168389$9176 assign { } { } assign { } { } assign { } { } @@ -341367,32 +312737,32 @@ module \pipe1$110 assign { } { } assign { } { } assign { } { } - assign $0\sr_op__fn_unit$next[13:0]$9193 $1\sr_op__fn_unit$next[13:0]$9210 + assign $0\sr_op__fn_unit$next[13:0]$9177 $1\sr_op__fn_unit$next[13:0]$9194 assign { } { } assign { } { } - assign $0\sr_op__input_carry$next[1:0]$9196 $1\sr_op__input_carry$next[1:0]$9213 - assign $0\sr_op__input_cr$next[0:0]$9197 $1\sr_op__input_cr$next[0:0]$9214 - assign $0\sr_op__insn$next[31:0]$9198 $1\sr_op__insn$next[31:0]$9215 - assign $0\sr_op__insn_type$next[6:0]$9199 $1\sr_op__insn_type$next[6:0]$9216 - assign $0\sr_op__invert_in$next[0:0]$9200 $1\sr_op__invert_in$next[0:0]$9217 - assign $0\sr_op__is_32bit$next[0:0]$9201 $1\sr_op__is_32bit$next[0:0]$9218 - assign $0\sr_op__is_signed$next[0:0]$9202 $1\sr_op__is_signed$next[0:0]$9219 + assign $0\sr_op__input_carry$next[1:0]$9180 $1\sr_op__input_carry$next[1:0]$9197 + assign $0\sr_op__input_cr$next[0:0]$9181 $1\sr_op__input_cr$next[0:0]$9198 + assign $0\sr_op__insn$next[31:0]$9182 $1\sr_op__insn$next[31:0]$9199 + assign $0\sr_op__insn_type$next[6:0]$9183 $1\sr_op__insn_type$next[6:0]$9200 + assign $0\sr_op__invert_in$next[0:0]$9184 $1\sr_op__invert_in$next[0:0]$9201 + assign $0\sr_op__is_32bit$next[0:0]$9185 $1\sr_op__is_32bit$next[0:0]$9202 + assign $0\sr_op__is_signed$next[0:0]$9186 $1\sr_op__is_signed$next[0:0]$9203 assign { } { } assign { } { } - assign $0\sr_op__output_carry$next[0:0]$9205 $1\sr_op__output_carry$next[0:0]$9222 - assign $0\sr_op__output_cr$next[0:0]$9206 $1\sr_op__output_cr$next[0:0]$9223 + assign $0\sr_op__output_carry$next[0:0]$9189 $1\sr_op__output_carry$next[0:0]$9206 + assign $0\sr_op__output_cr$next[0:0]$9190 $1\sr_op__output_cr$next[0:0]$9207 assign { } { } assign { } { } - assign $0\sr_op__write_cr0$next[0:0]$9209 $1\sr_op__write_cr0$next[0:0]$9226 - assign $0\sr_op__imm_data__data$next[63:0]$9194 $2\sr_op__imm_data__data$next[63:0]$9227 - assign $0\sr_op__imm_data__ok$next[0:0]$9195 $2\sr_op__imm_data__ok$next[0:0]$9228 - assign $0\sr_op__oe__oe$next[0:0]$9203 $2\sr_op__oe__oe$next[0:0]$9229 - assign $0\sr_op__oe__ok$next[0:0]$9204 $2\sr_op__oe__ok$next[0:0]$9230 - assign $0\sr_op__rc__ok$next[0:0]$9207 $2\sr_op__rc__ok$next[0:0]$9231 - assign $0\sr_op__rc__rc$next[0:0]$9208 $2\sr_op__rc__rc$next[0:0]$9232 - attribute \src "libresoc.v:167082.5-167082.29" + assign $0\sr_op__write_cr0$next[0:0]$9193 $1\sr_op__write_cr0$next[0:0]$9210 + assign $0\sr_op__imm_data__data$next[63:0]$9178 $2\sr_op__imm_data__data$next[63:0]$9211 + assign $0\sr_op__imm_data__ok$next[0:0]$9179 $2\sr_op__imm_data__ok$next[0:0]$9212 + assign $0\sr_op__oe__oe$next[0:0]$9187 $2\sr_op__oe__oe$next[0:0]$9213 + assign $0\sr_op__oe__ok$next[0:0]$9188 $2\sr_op__oe__ok$next[0:0]$9214 + assign $0\sr_op__rc__ok$next[0:0]$9191 $2\sr_op__rc__ok$next[0:0]$9215 + assign $0\sr_op__rc__rc$next[0:0]$9192 $2\sr_op__rc__rc$next[0:0]$9216 + attribute \src "libresoc.v:168390.5-168390.29" switch \initial - attribute \src "libresoc.v:167082.9-167082.17" + attribute \src "libresoc.v:168390.9-168390.17" case 1'1 case end @@ -341417,7 +312787,7 @@ module \pipe1$110 assign { } { } assign { } { } assign { } { } - assign { $1\sr_op__insn$next[31:0]$9215 $1\sr_op__is_signed$next[0:0]$9219 $1\sr_op__is_32bit$next[0:0]$9218 $1\sr_op__output_cr$next[0:0]$9223 $1\sr_op__input_cr$next[0:0]$9214 $1\sr_op__output_carry$next[0:0]$9222 $1\sr_op__input_carry$next[1:0]$9213 $1\sr_op__invert_in$next[0:0]$9217 $1\sr_op__write_cr0$next[0:0]$9226 $1\sr_op__oe__ok$next[0:0]$9221 $1\sr_op__oe__oe$next[0:0]$9220 $1\sr_op__rc__ok$next[0:0]$9224 $1\sr_op__rc__rc$next[0:0]$9225 $1\sr_op__imm_data__ok$next[0:0]$9212 $1\sr_op__imm_data__data$next[63:0]$9211 $1\sr_op__fn_unit$next[13:0]$9210 $1\sr_op__insn_type$next[6:0]$9216 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } + assign { $1\sr_op__insn$next[31:0]$9199 $1\sr_op__is_signed$next[0:0]$9203 $1\sr_op__is_32bit$next[0:0]$9202 $1\sr_op__output_cr$next[0:0]$9207 $1\sr_op__input_cr$next[0:0]$9198 $1\sr_op__output_carry$next[0:0]$9206 $1\sr_op__input_carry$next[1:0]$9197 $1\sr_op__invert_in$next[0:0]$9201 $1\sr_op__write_cr0$next[0:0]$9210 $1\sr_op__oe__ok$next[0:0]$9205 $1\sr_op__oe__oe$next[0:0]$9204 $1\sr_op__rc__ok$next[0:0]$9208 $1\sr_op__rc__rc$next[0:0]$9209 $1\sr_op__imm_data__ok$next[0:0]$9196 $1\sr_op__imm_data__data$next[63:0]$9195 $1\sr_op__fn_unit$next[13:0]$9194 $1\sr_op__insn_type$next[6:0]$9200 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -341437,25 +312807,25 @@ module \pipe1$110 assign { } { } assign { } { } assign { } { } - assign { $1\sr_op__insn$next[31:0]$9215 $1\sr_op__is_signed$next[0:0]$9219 $1\sr_op__is_32bit$next[0:0]$9218 $1\sr_op__output_cr$next[0:0]$9223 $1\sr_op__input_cr$next[0:0]$9214 $1\sr_op__output_carry$next[0:0]$9222 $1\sr_op__input_carry$next[1:0]$9213 $1\sr_op__invert_in$next[0:0]$9217 $1\sr_op__write_cr0$next[0:0]$9226 $1\sr_op__oe__ok$next[0:0]$9221 $1\sr_op__oe__oe$next[0:0]$9220 $1\sr_op__rc__ok$next[0:0]$9224 $1\sr_op__rc__rc$next[0:0]$9225 $1\sr_op__imm_data__ok$next[0:0]$9212 $1\sr_op__imm_data__data$next[63:0]$9211 $1\sr_op__fn_unit$next[13:0]$9210 $1\sr_op__insn_type$next[6:0]$9216 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } + assign { $1\sr_op__insn$next[31:0]$9199 $1\sr_op__is_signed$next[0:0]$9203 $1\sr_op__is_32bit$next[0:0]$9202 $1\sr_op__output_cr$next[0:0]$9207 $1\sr_op__input_cr$next[0:0]$9198 $1\sr_op__output_carry$next[0:0]$9206 $1\sr_op__input_carry$next[1:0]$9197 $1\sr_op__invert_in$next[0:0]$9201 $1\sr_op__write_cr0$next[0:0]$9210 $1\sr_op__oe__ok$next[0:0]$9205 $1\sr_op__oe__oe$next[0:0]$9204 $1\sr_op__rc__ok$next[0:0]$9208 $1\sr_op__rc__rc$next[0:0]$9209 $1\sr_op__imm_data__ok$next[0:0]$9196 $1\sr_op__imm_data__data$next[63:0]$9195 $1\sr_op__fn_unit$next[13:0]$9194 $1\sr_op__insn_type$next[6:0]$9200 } { \sr_op__insn$84 \sr_op__is_signed$83 \sr_op__is_32bit$82 \sr_op__output_cr$81 \sr_op__input_cr$80 \sr_op__output_carry$79 \sr_op__input_carry$78 \sr_op__invert_in$77 \sr_op__write_cr0$76 \sr_op__oe__ok$75 \sr_op__oe__oe$74 \sr_op__rc__ok$73 \sr_op__rc__rc$72 \sr_op__imm_data__ok$71 \sr_op__imm_data__data$70 \sr_op__fn_unit$69 \sr_op__insn_type$68 } case - assign $1\sr_op__fn_unit$next[13:0]$9210 \sr_op__fn_unit - assign $1\sr_op__imm_data__data$next[63:0]$9211 \sr_op__imm_data__data - assign $1\sr_op__imm_data__ok$next[0:0]$9212 \sr_op__imm_data__ok - assign $1\sr_op__input_carry$next[1:0]$9213 \sr_op__input_carry - assign $1\sr_op__input_cr$next[0:0]$9214 \sr_op__input_cr - assign $1\sr_op__insn$next[31:0]$9215 \sr_op__insn - assign $1\sr_op__insn_type$next[6:0]$9216 \sr_op__insn_type - assign $1\sr_op__invert_in$next[0:0]$9217 \sr_op__invert_in - assign $1\sr_op__is_32bit$next[0:0]$9218 \sr_op__is_32bit - assign $1\sr_op__is_signed$next[0:0]$9219 \sr_op__is_signed - assign $1\sr_op__oe__oe$next[0:0]$9220 \sr_op__oe__oe - assign $1\sr_op__oe__ok$next[0:0]$9221 \sr_op__oe__ok - assign $1\sr_op__output_carry$next[0:0]$9222 \sr_op__output_carry - assign $1\sr_op__output_cr$next[0:0]$9223 \sr_op__output_cr - assign $1\sr_op__rc__ok$next[0:0]$9224 \sr_op__rc__ok - assign $1\sr_op__rc__rc$next[0:0]$9225 \sr_op__rc__rc - assign $1\sr_op__write_cr0$next[0:0]$9226 \sr_op__write_cr0 + assign $1\sr_op__fn_unit$next[13:0]$9194 \sr_op__fn_unit + assign $1\sr_op__imm_data__data$next[63:0]$9195 \sr_op__imm_data__data + assign $1\sr_op__imm_data__ok$next[0:0]$9196 \sr_op__imm_data__ok + assign $1\sr_op__input_carry$next[1:0]$9197 \sr_op__input_carry + assign $1\sr_op__input_cr$next[0:0]$9198 \sr_op__input_cr + assign $1\sr_op__insn$next[31:0]$9199 \sr_op__insn + assign $1\sr_op__insn_type$next[6:0]$9200 \sr_op__insn_type + assign $1\sr_op__invert_in$next[0:0]$9201 \sr_op__invert_in + assign $1\sr_op__is_32bit$next[0:0]$9202 \sr_op__is_32bit + assign $1\sr_op__is_signed$next[0:0]$9203 \sr_op__is_signed + assign $1\sr_op__oe__oe$next[0:0]$9204 \sr_op__oe__oe + assign $1\sr_op__oe__ok$next[0:0]$9205 \sr_op__oe__ok + assign $1\sr_op__output_carry$next[0:0]$9206 \sr_op__output_carry + assign $1\sr_op__output_cr$next[0:0]$9207 \sr_op__output_cr + assign $1\sr_op__rc__ok$next[0:0]$9208 \sr_op__rc__ok + assign $1\sr_op__rc__rc$next[0:0]$9209 \sr_op__rc__rc + assign $1\sr_op__write_cr0$next[0:0]$9210 \sr_op__write_cr0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -341467,51 +312837,51 @@ module \pipe1$110 assign { } { } assign { } { } assign { } { } - assign $2\sr_op__imm_data__data$next[63:0]$9227 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\sr_op__imm_data__ok$next[0:0]$9228 1'0 - assign $2\sr_op__rc__rc$next[0:0]$9232 1'0 - assign $2\sr_op__rc__ok$next[0:0]$9231 1'0 - assign $2\sr_op__oe__oe$next[0:0]$9229 1'0 - assign $2\sr_op__oe__ok$next[0:0]$9230 1'0 + assign $2\sr_op__imm_data__data$next[63:0]$9211 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sr_op__imm_data__ok$next[0:0]$9212 1'0 + assign $2\sr_op__rc__rc$next[0:0]$9216 1'0 + assign $2\sr_op__rc__ok$next[0:0]$9215 1'0 + assign $2\sr_op__oe__oe$next[0:0]$9213 1'0 + assign $2\sr_op__oe__ok$next[0:0]$9214 1'0 case - assign $2\sr_op__imm_data__data$next[63:0]$9227 $1\sr_op__imm_data__data$next[63:0]$9211 - assign $2\sr_op__imm_data__ok$next[0:0]$9228 $1\sr_op__imm_data__ok$next[0:0]$9212 - assign $2\sr_op__oe__oe$next[0:0]$9229 $1\sr_op__oe__oe$next[0:0]$9220 - assign $2\sr_op__oe__ok$next[0:0]$9230 $1\sr_op__oe__ok$next[0:0]$9221 - assign $2\sr_op__rc__ok$next[0:0]$9231 $1\sr_op__rc__ok$next[0:0]$9224 - assign $2\sr_op__rc__rc$next[0:0]$9232 $1\sr_op__rc__rc$next[0:0]$9225 + assign $2\sr_op__imm_data__data$next[63:0]$9211 $1\sr_op__imm_data__data$next[63:0]$9195 + assign $2\sr_op__imm_data__ok$next[0:0]$9212 $1\sr_op__imm_data__ok$next[0:0]$9196 + assign $2\sr_op__oe__oe$next[0:0]$9213 $1\sr_op__oe__oe$next[0:0]$9204 + assign $2\sr_op__oe__ok$next[0:0]$9214 $1\sr_op__oe__ok$next[0:0]$9205 + assign $2\sr_op__rc__ok$next[0:0]$9215 $1\sr_op__rc__ok$next[0:0]$9208 + assign $2\sr_op__rc__rc$next[0:0]$9216 $1\sr_op__rc__rc$next[0:0]$9209 end sync always - update \sr_op__fn_unit$next $0\sr_op__fn_unit$next[13:0]$9193 - update \sr_op__imm_data__data$next $0\sr_op__imm_data__data$next[63:0]$9194 - update \sr_op__imm_data__ok$next $0\sr_op__imm_data__ok$next[0:0]$9195 - update \sr_op__input_carry$next $0\sr_op__input_carry$next[1:0]$9196 - update \sr_op__input_cr$next $0\sr_op__input_cr$next[0:0]$9197 - update \sr_op__insn$next $0\sr_op__insn$next[31:0]$9198 - update \sr_op__insn_type$next $0\sr_op__insn_type$next[6:0]$9199 - update \sr_op__invert_in$next $0\sr_op__invert_in$next[0:0]$9200 - update \sr_op__is_32bit$next $0\sr_op__is_32bit$next[0:0]$9201 - update \sr_op__is_signed$next $0\sr_op__is_signed$next[0:0]$9202 - update \sr_op__oe__oe$next $0\sr_op__oe__oe$next[0:0]$9203 - update \sr_op__oe__ok$next $0\sr_op__oe__ok$next[0:0]$9204 - update \sr_op__output_carry$next $0\sr_op__output_carry$next[0:0]$9205 - update \sr_op__output_cr$next $0\sr_op__output_cr$next[0:0]$9206 - update \sr_op__rc__ok$next $0\sr_op__rc__ok$next[0:0]$9207 - update \sr_op__rc__rc$next $0\sr_op__rc__rc$next[0:0]$9208 - update \sr_op__write_cr0$next $0\sr_op__write_cr0$next[0:0]$9209 + update \sr_op__fn_unit$next $0\sr_op__fn_unit$next[13:0]$9177 + update \sr_op__imm_data__data$next $0\sr_op__imm_data__data$next[63:0]$9178 + update \sr_op__imm_data__ok$next $0\sr_op__imm_data__ok$next[0:0]$9179 + update \sr_op__input_carry$next $0\sr_op__input_carry$next[1:0]$9180 + update \sr_op__input_cr$next $0\sr_op__input_cr$next[0:0]$9181 + update \sr_op__insn$next $0\sr_op__insn$next[31:0]$9182 + update \sr_op__insn_type$next $0\sr_op__insn_type$next[6:0]$9183 + update \sr_op__invert_in$next $0\sr_op__invert_in$next[0:0]$9184 + update \sr_op__is_32bit$next $0\sr_op__is_32bit$next[0:0]$9185 + update \sr_op__is_signed$next $0\sr_op__is_signed$next[0:0]$9186 + update \sr_op__oe__oe$next $0\sr_op__oe__oe$next[0:0]$9187 + update \sr_op__oe__ok$next $0\sr_op__oe__ok$next[0:0]$9188 + update \sr_op__output_carry$next $0\sr_op__output_carry$next[0:0]$9189 + update \sr_op__output_cr$next $0\sr_op__output_cr$next[0:0]$9190 + update \sr_op__rc__ok$next $0\sr_op__rc__ok$next[0:0]$9191 + update \sr_op__rc__rc$next $0\sr_op__rc__rc$next[0:0]$9192 + update \sr_op__write_cr0$next $0\sr_op__write_cr0$next[0:0]$9193 end - attribute \src "libresoc.v:167122.3-167140.6" - process $proc$libresoc.v:167122$9233 + attribute \src "libresoc.v:168430.3-168448.6" + process $proc$libresoc.v:168430$9217 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$9234 $1\o$next[63:0]$9236 + assign $0\o$next[63:0]$9218 $1\o$next[63:0]$9220 assign { } { } - assign $0\o_ok$next[0:0]$9235 $2\o_ok$next[0:0]$9238 - attribute \src "libresoc.v:167123.5-167123.29" + assign $0\o_ok$next[0:0]$9219 $2\o_ok$next[0:0]$9222 + attribute \src "libresoc.v:168431.5-168431.29" switch \initial - attribute \src "libresoc.v:167123.9-167123.17" + attribute \src "libresoc.v:168431.9-168431.17" case 1'1 case end @@ -341521,41 +312891,41 @@ module \pipe1$110 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9237 $1\o$next[63:0]$9236 } { \o_ok$86 \o$85 } + assign { $1\o_ok$next[0:0]$9221 $1\o$next[63:0]$9220 } { \o_ok$86 \o$85 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9237 $1\o$next[63:0]$9236 } { \o_ok$86 \o$85 } + assign { $1\o_ok$next[0:0]$9221 $1\o$next[63:0]$9220 } { \o_ok$86 \o$85 } case - assign $1\o$next[63:0]$9236 \o - assign $1\o_ok$next[0:0]$9237 \o_ok + assign $1\o$next[63:0]$9220 \o + assign $1\o_ok$next[0:0]$9221 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$9238 1'0 + assign $2\o_ok$next[0:0]$9222 1'0 case - assign $2\o_ok$next[0:0]$9238 $1\o_ok$next[0:0]$9237 + assign $2\o_ok$next[0:0]$9222 $1\o_ok$next[0:0]$9221 end sync always - update \o$next $0\o$next[63:0]$9234 - update \o_ok$next $0\o_ok$next[0:0]$9235 + update \o$next $0\o$next[63:0]$9218 + update \o_ok$next $0\o_ok$next[0:0]$9219 end - attribute \src "libresoc.v:167141.3-167159.6" - process $proc$libresoc.v:167141$9239 + attribute \src "libresoc.v:168449.3-168467.6" + process $proc$libresoc.v:168449$9223 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$next[3:0]$9240 $1\cr_a$next[3:0]$9242 + assign $0\cr_a$next[3:0]$9224 $1\cr_a$next[3:0]$9226 assign { } { } - assign $0\cr_a_ok$next[0:0]$9241 $2\cr_a_ok$next[0:0]$9244 - attribute \src "libresoc.v:167142.5-167142.29" + assign $0\cr_a_ok$next[0:0]$9225 $2\cr_a_ok$next[0:0]$9228 + attribute \src "libresoc.v:168450.5-168450.29" switch \initial - attribute \src "libresoc.v:167142.9-167142.17" + attribute \src "libresoc.v:168450.9-168450.17" case 1'1 case end @@ -341565,41 +312935,41 @@ module \pipe1$110 case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$9243 $1\cr_a$next[3:0]$9242 } { \cr_a_ok$88 \cr_a$87 } + assign { $1\cr_a_ok$next[0:0]$9227 $1\cr_a$next[3:0]$9226 } { \cr_a_ok$88 \cr_a$87 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$9243 $1\cr_a$next[3:0]$9242 } { \cr_a_ok$88 \cr_a$87 } + assign { $1\cr_a_ok$next[0:0]$9227 $1\cr_a$next[3:0]$9226 } { \cr_a_ok$88 \cr_a$87 } case - assign $1\cr_a$next[3:0]$9242 \cr_a - assign $1\cr_a_ok$next[0:0]$9243 \cr_a_ok + assign $1\cr_a$next[3:0]$9226 \cr_a + assign $1\cr_a_ok$next[0:0]$9227 \cr_a_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$9244 1'0 + assign $2\cr_a_ok$next[0:0]$9228 1'0 case - assign $2\cr_a_ok$next[0:0]$9244 $1\cr_a_ok$next[0:0]$9243 + assign $2\cr_a_ok$next[0:0]$9228 $1\cr_a_ok$next[0:0]$9227 end sync always - update \cr_a$next $0\cr_a$next[3:0]$9240 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9241 + update \cr_a$next $0\cr_a$next[3:0]$9224 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9225 end - attribute \src "libresoc.v:167160.3-167178.6" - process $proc$libresoc.v:167160$9245 + attribute \src "libresoc.v:168468.3-168486.6" + process $proc$libresoc.v:168468$9229 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$next[0:0]$9246 $1\xer_so$next[0:0]$9248 + assign $0\xer_so$next[0:0]$9230 $1\xer_so$next[0:0]$9232 assign { } { } - assign $0\xer_so_ok$next[0:0]$9247 $2\xer_so_ok$next[0:0]$9250 - attribute \src "libresoc.v:167161.5-167161.29" + assign $0\xer_so_ok$next[0:0]$9231 $2\xer_so_ok$next[0:0]$9234 + attribute \src "libresoc.v:168469.5-168469.29" switch \initial - attribute \src "libresoc.v:167161.9-167161.17" + attribute \src "libresoc.v:168469.9-168469.17" case 1'1 case end @@ -341609,30 +312979,30 @@ module \pipe1$110 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$9249 $1\xer_so$next[0:0]$9248 } { \xer_so_ok$92 \xer_so$91 } + assign { $1\xer_so_ok$next[0:0]$9233 $1\xer_so$next[0:0]$9232 } { \xer_so_ok$92 \xer_so$91 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$9249 $1\xer_so$next[0:0]$9248 } { \xer_so_ok$92 \xer_so$91 } + assign { $1\xer_so_ok$next[0:0]$9233 $1\xer_so$next[0:0]$9232 } { \xer_so_ok$92 \xer_so$91 } case - assign $1\xer_so$next[0:0]$9248 \xer_so - assign $1\xer_so_ok$next[0:0]$9249 \xer_so_ok + assign $1\xer_so$next[0:0]$9232 \xer_so + assign $1\xer_so_ok$next[0:0]$9233 \xer_so_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$9250 1'0 + assign $2\xer_so_ok$next[0:0]$9234 1'0 case - assign $2\xer_so_ok$next[0:0]$9250 $1\xer_so_ok$next[0:0]$9249 + assign $2\xer_so_ok$next[0:0]$9234 $1\xer_so_ok$next[0:0]$9233 end sync always - update \xer_so$next $0\xer_so$next[0:0]$9246 - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9247 + update \xer_so$next $0\xer_so$next[0:0]$9230 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9231 end - connect \$65 $and$libresoc.v:166874$9151_Y + connect \$65 $and$libresoc.v:168182$9135_Y connect \cr_a$89 4'0000 connect \cr_a_ok$90 1'0 connect \xer_so_ok$93 1'0 @@ -341663,142 +313033,142 @@ module \pipe1$110 connect { \input_sr_op__insn \input_sr_op__is_signed \input_sr_op__is_32bit \input_sr_op__output_cr \input_sr_op__input_cr \input_sr_op__output_carry \input_sr_op__input_carry \input_sr_op__invert_in \input_sr_op__write_cr0 \input_sr_op__oe__ok \input_sr_op__oe__oe \input_sr_op__rc__ok \input_sr_op__rc__rc \input_sr_op__imm_data__ok \input_sr_op__imm_data__data \input_sr_op__fn_unit \input_sr_op__insn_type } { \sr_op__insn$18 \sr_op__is_signed$17 \sr_op__is_32bit$16 \sr_op__output_cr$15 \sr_op__input_cr$14 \sr_op__output_carry$13 \sr_op__input_carry$12 \sr_op__invert_in$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:167212.1-168060.10" +attribute \src "libresoc.v:168520.1-169368.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe1" attribute \generator "nMigen" module \pipe1$32 - attribute \src "libresoc.v:168017.3-168029.6" - wire width 64 $0\fast1$next[63:0]$9328 - attribute \src "libresoc.v:167873.3-167874.27" + attribute \src "libresoc.v:169325.3-169337.6" + wire width 64 $0\fast1$next[63:0]$9312 + attribute \src "libresoc.v:169181.3-169182.27" wire width 64 $0\fast1[63:0] - attribute \src "libresoc.v:168030.3-168042.6" - wire width 64 $0\fast2$next[63:0]$9331 - attribute \src "libresoc.v:167871.3-167872.27" + attribute \src "libresoc.v:169338.3-169350.6" + wire width 64 $0\fast2$next[63:0]$9315 + attribute \src "libresoc.v:169179.3-169180.27" wire width 64 $0\fast2[63:0] - attribute \src "libresoc.v:167213.7-167213.20" + attribute \src "libresoc.v:168521.7-168521.20" wire $0\initial[0:0] - attribute \src "libresoc.v:167957.3-167969.6" - wire width 2 $0\muxid$next[1:0]$9300 - attribute \src "libresoc.v:167897.3-167898.27" + attribute \src "libresoc.v:169265.3-169277.6" + wire width 2 $0\muxid$next[1:0]$9284 + attribute \src "libresoc.v:169205.3-169206.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:167939.3-167956.6" - wire $0\r_busy$next[0:0]$9296 - attribute \src "libresoc.v:167899.3-167900.29" + attribute \src "libresoc.v:169247.3-169264.6" + wire $0\r_busy$next[0:0]$9280 + attribute \src "libresoc.v:169207.3-169208.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:167991.3-168003.6" - wire width 64 $0\ra$next[63:0]$9322 - attribute \src "libresoc.v:167877.3-167878.21" + attribute \src "libresoc.v:169299.3-169311.6" + wire width 64 $0\ra$next[63:0]$9306 + attribute \src "libresoc.v:169185.3-169186.21" wire width 64 $0\ra[63:0] - attribute \src "libresoc.v:168004.3-168016.6" - wire width 64 $0\rb$next[63:0]$9325 - attribute \src "libresoc.v:167875.3-167876.21" + attribute \src "libresoc.v:169312.3-169324.6" + wire width 64 $0\rb$next[63:0]$9309 + attribute \src "libresoc.v:169183.3-169184.21" wire width 64 $0\rb[63:0] - attribute \src "libresoc.v:167970.3-167990.6" - wire width 64 $0\trap_op__cia$next[63:0]$9303 - attribute \src "libresoc.v:167887.3-167888.41" + attribute \src "libresoc.v:169278.3-169298.6" + wire width 64 $0\trap_op__cia$next[63:0]$9287 + attribute \src "libresoc.v:169195.3-169196.41" wire width 64 $0\trap_op__cia[63:0] - attribute \src "libresoc.v:167970.3-167990.6" - wire width 14 $0\trap_op__fn_unit$next[13:0]$9304 - attribute \src "libresoc.v:167881.3-167882.49" + attribute \src "libresoc.v:169278.3-169298.6" + wire width 14 $0\trap_op__fn_unit$next[13:0]$9288 + attribute \src "libresoc.v:169189.3-169190.49" wire width 14 $0\trap_op__fn_unit[13:0] - attribute \src "libresoc.v:167970.3-167990.6" - wire width 32 $0\trap_op__insn$next[31:0]$9305 - attribute \src "libresoc.v:167883.3-167884.43" + attribute \src "libresoc.v:169278.3-169298.6" + wire width 32 $0\trap_op__insn$next[31:0]$9289 + attribute \src "libresoc.v:169191.3-169192.43" wire width 32 $0\trap_op__insn[31:0] - attribute \src "libresoc.v:167970.3-167990.6" - wire width 7 $0\trap_op__insn_type$next[6:0]$9306 - attribute \src "libresoc.v:167879.3-167880.53" + attribute \src "libresoc.v:169278.3-169298.6" + wire width 7 $0\trap_op__insn_type$next[6:0]$9290 + attribute \src "libresoc.v:169187.3-169188.53" wire width 7 $0\trap_op__insn_type[6:0] - attribute \src "libresoc.v:167970.3-167990.6" - wire $0\trap_op__is_32bit$next[0:0]$9307 - attribute \src "libresoc.v:167889.3-167890.51" + attribute \src "libresoc.v:169278.3-169298.6" + wire $0\trap_op__is_32bit$next[0:0]$9291 + attribute \src "libresoc.v:169197.3-169198.51" wire $0\trap_op__is_32bit[0:0] - attribute \src "libresoc.v:167970.3-167990.6" - wire width 8 $0\trap_op__ldst_exc$next[7:0]$9308 - attribute \src "libresoc.v:167895.3-167896.51" + attribute \src "libresoc.v:169278.3-169298.6" + wire width 8 $0\trap_op__ldst_exc$next[7:0]$9292 + attribute \src "libresoc.v:169203.3-169204.51" wire width 8 $0\trap_op__ldst_exc[7:0] - attribute \src "libresoc.v:167970.3-167990.6" - wire width 64 $0\trap_op__msr$next[63:0]$9309 - attribute \src "libresoc.v:167885.3-167886.41" + attribute \src "libresoc.v:169278.3-169298.6" + wire width 64 $0\trap_op__msr$next[63:0]$9293 + attribute \src "libresoc.v:169193.3-169194.41" wire width 64 $0\trap_op__msr[63:0] - attribute \src "libresoc.v:167970.3-167990.6" - wire width 13 $0\trap_op__trapaddr$next[12:0]$9310 - attribute \src "libresoc.v:167893.3-167894.51" + attribute \src "libresoc.v:169278.3-169298.6" + wire width 13 $0\trap_op__trapaddr$next[12:0]$9294 + attribute \src "libresoc.v:169201.3-169202.51" wire width 13 $0\trap_op__trapaddr[12:0] - attribute \src "libresoc.v:167970.3-167990.6" - wire width 8 $0\trap_op__traptype$next[7:0]$9311 - attribute \src "libresoc.v:167891.3-167892.51" + attribute \src "libresoc.v:169278.3-169298.6" + wire width 8 $0\trap_op__traptype$next[7:0]$9295 + attribute \src "libresoc.v:169199.3-169200.51" wire width 8 $0\trap_op__traptype[7:0] - attribute \src "libresoc.v:168017.3-168029.6" - wire width 64 $1\fast1$next[63:0]$9329 - attribute \src "libresoc.v:167458.14-167458.42" + attribute \src "libresoc.v:169325.3-169337.6" + wire width 64 $1\fast1$next[63:0]$9313 + attribute \src "libresoc.v:168766.14-168766.42" wire width 64 $1\fast1[63:0] - attribute \src "libresoc.v:168030.3-168042.6" - wire width 64 $1\fast2$next[63:0]$9332 - attribute \src "libresoc.v:167467.14-167467.42" + attribute \src "libresoc.v:169338.3-169350.6" + wire width 64 $1\fast2$next[63:0]$9316 + attribute \src "libresoc.v:168775.14-168775.42" wire width 64 $1\fast2[63:0] - attribute \src "libresoc.v:167957.3-167969.6" - wire width 2 $1\muxid$next[1:0]$9301 - attribute \src "libresoc.v:167476.13-167476.25" + attribute \src "libresoc.v:169265.3-169277.6" + wire width 2 $1\muxid$next[1:0]$9285 + attribute \src "libresoc.v:168784.13-168784.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:167939.3-167956.6" - wire $1\r_busy$next[0:0]$9297 - attribute \src "libresoc.v:167498.7-167498.20" + attribute \src "libresoc.v:169247.3-169264.6" + wire $1\r_busy$next[0:0]$9281 + attribute \src "libresoc.v:168806.7-168806.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:167991.3-168003.6" - wire width 64 $1\ra$next[63:0]$9323 - attribute \src "libresoc.v:167503.14-167503.39" + attribute \src "libresoc.v:169299.3-169311.6" + wire width 64 $1\ra$next[63:0]$9307 + attribute \src "libresoc.v:168811.14-168811.39" wire width 64 $1\ra[63:0] - attribute \src "libresoc.v:168004.3-168016.6" - wire width 64 $1\rb$next[63:0]$9326 - attribute \src "libresoc.v:167512.14-167512.39" + attribute \src "libresoc.v:169312.3-169324.6" + wire width 64 $1\rb$next[63:0]$9310 + attribute \src "libresoc.v:168820.14-168820.39" wire width 64 $1\rb[63:0] - attribute \src "libresoc.v:167970.3-167990.6" - wire width 64 $1\trap_op__cia$next[63:0]$9312 - attribute \src "libresoc.v:167521.14-167521.49" + attribute \src "libresoc.v:169278.3-169298.6" + wire width 64 $1\trap_op__cia$next[63:0]$9296 + attribute \src "libresoc.v:168829.14-168829.49" wire width 64 $1\trap_op__cia[63:0] - attribute \src "libresoc.v:167970.3-167990.6" - wire width 14 $1\trap_op__fn_unit$next[13:0]$9313 - attribute \src "libresoc.v:167545.14-167545.41" + attribute \src "libresoc.v:169278.3-169298.6" + wire width 14 $1\trap_op__fn_unit$next[13:0]$9297 + attribute \src "libresoc.v:168853.14-168853.41" wire width 14 $1\trap_op__fn_unit[13:0] - attribute \src "libresoc.v:167970.3-167990.6" - wire width 32 $1\trap_op__insn$next[31:0]$9314 - attribute \src "libresoc.v:167584.14-167584.35" + attribute \src "libresoc.v:169278.3-169298.6" + wire width 32 $1\trap_op__insn$next[31:0]$9298 + attribute \src "libresoc.v:168892.14-168892.35" wire width 32 $1\trap_op__insn[31:0] - attribute \src "libresoc.v:167970.3-167990.6" - wire width 7 $1\trap_op__insn_type$next[6:0]$9315 - attribute \src "libresoc.v:167668.13-167668.39" + attribute \src "libresoc.v:169278.3-169298.6" + wire width 7 $1\trap_op__insn_type$next[6:0]$9299 + attribute \src "libresoc.v:168976.13-168976.39" wire width 7 $1\trap_op__insn_type[6:0] - attribute \src "libresoc.v:167970.3-167990.6" - wire $1\trap_op__is_32bit$next[0:0]$9316 - attribute \src "libresoc.v:167827.7-167827.31" + attribute \src "libresoc.v:169278.3-169298.6" + wire $1\trap_op__is_32bit$next[0:0]$9300 + attribute \src "libresoc.v:169135.7-169135.31" wire $1\trap_op__is_32bit[0:0] - attribute \src "libresoc.v:167970.3-167990.6" - wire width 8 $1\trap_op__ldst_exc$next[7:0]$9317 - attribute \src "libresoc.v:167836.13-167836.38" + attribute \src "libresoc.v:169278.3-169298.6" + wire width 8 $1\trap_op__ldst_exc$next[7:0]$9301 + attribute \src "libresoc.v:169144.13-169144.38" wire width 8 $1\trap_op__ldst_exc[7:0] - attribute \src "libresoc.v:167970.3-167990.6" - wire width 64 $1\trap_op__msr$next[63:0]$9318 - attribute \src "libresoc.v:167845.14-167845.49" + attribute \src "libresoc.v:169278.3-169298.6" + wire width 64 $1\trap_op__msr$next[63:0]$9302 + attribute \src "libresoc.v:169153.14-169153.49" wire width 64 $1\trap_op__msr[63:0] - attribute \src "libresoc.v:167970.3-167990.6" - wire width 13 $1\trap_op__trapaddr$next[12:0]$9319 - attribute \src "libresoc.v:167854.14-167854.42" + attribute \src "libresoc.v:169278.3-169298.6" + wire width 13 $1\trap_op__trapaddr$next[12:0]$9303 + attribute \src "libresoc.v:169162.14-169162.42" wire width 13 $1\trap_op__trapaddr[12:0] - attribute \src "libresoc.v:167970.3-167990.6" - wire width 8 $1\trap_op__traptype$next[7:0]$9320 - attribute \src "libresoc.v:167863.13-167863.38" + attribute \src "libresoc.v:169278.3-169298.6" + wire width 8 $1\trap_op__traptype$next[7:0]$9304 + attribute \src "libresoc.v:169171.13-169171.38" wire width 8 $1\trap_op__traptype[7:0] - attribute \src "libresoc.v:167939.3-167956.6" - wire $2\r_busy$next[0:0]$9298 - attribute \src "libresoc.v:167870.18-167870.118" - wire $and$libresoc.v:167870$9279_Y + attribute \src "libresoc.v:169247.3-169264.6" + wire $2\r_busy$next[0:0]$9282 + attribute \src "libresoc.v:169178.18-169178.118" + wire $and$libresoc.v:169178$9263_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 34 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \dummy_fast1 @@ -342052,7 +313422,7 @@ module \pipe1$32 wire width 64 \fast2$45 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \fast2$next - attribute \src "libresoc.v:167213.7-167213.15" + attribute \src "libresoc.v:168521.7-168521.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 output 4 \muxid @@ -342439,7 +313809,7 @@ module \pipe1$32 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \trap_op__traptype$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:167870$9279 + cell $and $and$libresoc.v:169178$9263 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -342447,10 +313817,10 @@ module \pipe1$32 parameter \Y_WIDTH 1 connect \A \p_valid_i$29 connect \B \p_ready_o - connect \Y $and$libresoc.v:167870$9279_Y + connect \Y $and$libresoc.v:169178$9263_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:167901.9-167930.4" + attribute \src "libresoc.v:169209.9-169238.4" cell \dummy \dummy connect \fast1 \dummy_fast1 connect \fast1$13 \dummy_fast1$27 @@ -342482,259 +313852,259 @@ module \pipe1$32 connect \trap_op__traptype$8 \dummy_trap_op__traptype$22 end attribute \module_not_derived 1 - attribute \src "libresoc.v:167931.10-167934.4" + attribute \src "libresoc.v:169239.10-169242.4" cell \n$34 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:167935.10-167938.4" + attribute \src "libresoc.v:169243.10-169246.4" cell \p$33 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:167213.7-167213.20" - process $proc$libresoc.v:167213$9333 + attribute \src "libresoc.v:168521.7-168521.20" + process $proc$libresoc.v:168521$9317 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:167458.14-167458.42" - process $proc$libresoc.v:167458$9334 + attribute \src "libresoc.v:168766.14-168766.42" + process $proc$libresoc.v:168766$9318 assign { } { } assign $1\fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \fast1 $1\fast1[63:0] end - attribute \src "libresoc.v:167467.14-167467.42" - process $proc$libresoc.v:167467$9335 + attribute \src "libresoc.v:168775.14-168775.42" + process $proc$libresoc.v:168775$9319 assign { } { } assign $1\fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \fast2 $1\fast2[63:0] end - attribute \src "libresoc.v:167476.13-167476.25" - process $proc$libresoc.v:167476$9336 + attribute \src "libresoc.v:168784.13-168784.25" + process $proc$libresoc.v:168784$9320 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:167498.7-167498.20" - process $proc$libresoc.v:167498$9337 + attribute \src "libresoc.v:168806.7-168806.20" + process $proc$libresoc.v:168806$9321 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:167503.14-167503.39" - process $proc$libresoc.v:167503$9338 + attribute \src "libresoc.v:168811.14-168811.39" + process $proc$libresoc.v:168811$9322 assign { } { } assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ra $1\ra[63:0] end - attribute \src "libresoc.v:167512.14-167512.39" - process $proc$libresoc.v:167512$9339 + attribute \src "libresoc.v:168820.14-168820.39" + process $proc$libresoc.v:168820$9323 assign { } { } assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \rb $1\rb[63:0] end - attribute \src "libresoc.v:167521.14-167521.49" - process $proc$libresoc.v:167521$9340 + attribute \src "libresoc.v:168829.14-168829.49" + process $proc$libresoc.v:168829$9324 assign { } { } assign $1\trap_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \trap_op__cia $1\trap_op__cia[63:0] end - attribute \src "libresoc.v:167545.14-167545.41" - process $proc$libresoc.v:167545$9341 + attribute \src "libresoc.v:168853.14-168853.41" + process $proc$libresoc.v:168853$9325 assign { } { } assign $1\trap_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \trap_op__fn_unit $1\trap_op__fn_unit[13:0] end - attribute \src "libresoc.v:167584.14-167584.35" - process $proc$libresoc.v:167584$9342 + attribute \src "libresoc.v:168892.14-168892.35" + process $proc$libresoc.v:168892$9326 assign { } { } assign $1\trap_op__insn[31:0] 0 sync always sync init update \trap_op__insn $1\trap_op__insn[31:0] end - attribute \src "libresoc.v:167668.13-167668.39" - process $proc$libresoc.v:167668$9343 + attribute \src "libresoc.v:168976.13-168976.39" + process $proc$libresoc.v:168976$9327 assign { } { } assign $1\trap_op__insn_type[6:0] 7'0000000 sync always sync init update \trap_op__insn_type $1\trap_op__insn_type[6:0] end - attribute \src "libresoc.v:167827.7-167827.31" - process $proc$libresoc.v:167827$9344 + attribute \src "libresoc.v:169135.7-169135.31" + process $proc$libresoc.v:169135$9328 assign { } { } assign $1\trap_op__is_32bit[0:0] 1'0 sync always sync init update \trap_op__is_32bit $1\trap_op__is_32bit[0:0] end - attribute \src "libresoc.v:167836.13-167836.38" - process $proc$libresoc.v:167836$9345 + attribute \src "libresoc.v:169144.13-169144.38" + process $proc$libresoc.v:169144$9329 assign { } { } assign $1\trap_op__ldst_exc[7:0] 8'00000000 sync always sync init update \trap_op__ldst_exc $1\trap_op__ldst_exc[7:0] end - attribute \src "libresoc.v:167845.14-167845.49" - process $proc$libresoc.v:167845$9346 + attribute \src "libresoc.v:169153.14-169153.49" + process $proc$libresoc.v:169153$9330 assign { } { } assign $1\trap_op__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \trap_op__msr $1\trap_op__msr[63:0] end - attribute \src "libresoc.v:167854.14-167854.42" - process $proc$libresoc.v:167854$9347 + attribute \src "libresoc.v:169162.14-169162.42" + process $proc$libresoc.v:169162$9331 assign { } { } assign $1\trap_op__trapaddr[12:0] 13'0000000000000 sync always sync init update \trap_op__trapaddr $1\trap_op__trapaddr[12:0] end - attribute \src "libresoc.v:167863.13-167863.38" - process $proc$libresoc.v:167863$9348 + attribute \src "libresoc.v:169171.13-169171.38" + process $proc$libresoc.v:169171$9332 assign { } { } assign $1\trap_op__traptype[7:0] 8'00000000 sync always sync init update \trap_op__traptype $1\trap_op__traptype[7:0] end - attribute \src "libresoc.v:167871.3-167872.27" - process $proc$libresoc.v:167871$9280 + attribute \src "libresoc.v:169179.3-169180.27" + process $proc$libresoc.v:169179$9264 assign { } { } assign $0\fast2[63:0] \fast2$next sync posedge \coresync_clk update \fast2 $0\fast2[63:0] end - attribute \src "libresoc.v:167873.3-167874.27" - process $proc$libresoc.v:167873$9281 + attribute \src "libresoc.v:169181.3-169182.27" + process $proc$libresoc.v:169181$9265 assign { } { } assign $0\fast1[63:0] \fast1$next sync posedge \coresync_clk update \fast1 $0\fast1[63:0] end - attribute \src "libresoc.v:167875.3-167876.21" - process $proc$libresoc.v:167875$9282 + attribute \src "libresoc.v:169183.3-169184.21" + process $proc$libresoc.v:169183$9266 assign { } { } assign $0\rb[63:0] \rb$next sync posedge \coresync_clk update \rb $0\rb[63:0] end - attribute \src "libresoc.v:167877.3-167878.21" - process $proc$libresoc.v:167877$9283 + attribute \src "libresoc.v:169185.3-169186.21" + process $proc$libresoc.v:169185$9267 assign { } { } assign $0\ra[63:0] \ra$next sync posedge \coresync_clk update \ra $0\ra[63:0] end - attribute \src "libresoc.v:167879.3-167880.53" - process $proc$libresoc.v:167879$9284 + attribute \src "libresoc.v:169187.3-169188.53" + process $proc$libresoc.v:169187$9268 assign { } { } assign $0\trap_op__insn_type[6:0] \trap_op__insn_type$next sync posedge \coresync_clk update \trap_op__insn_type $0\trap_op__insn_type[6:0] end - attribute \src "libresoc.v:167881.3-167882.49" - process $proc$libresoc.v:167881$9285 + attribute \src "libresoc.v:169189.3-169190.49" + process $proc$libresoc.v:169189$9269 assign { } { } assign $0\trap_op__fn_unit[13:0] \trap_op__fn_unit$next sync posedge \coresync_clk update \trap_op__fn_unit $0\trap_op__fn_unit[13:0] end - attribute \src "libresoc.v:167883.3-167884.43" - process $proc$libresoc.v:167883$9286 + attribute \src "libresoc.v:169191.3-169192.43" + process $proc$libresoc.v:169191$9270 assign { } { } assign $0\trap_op__insn[31:0] \trap_op__insn$next sync posedge \coresync_clk update \trap_op__insn $0\trap_op__insn[31:0] end - attribute \src "libresoc.v:167885.3-167886.41" - process $proc$libresoc.v:167885$9287 + attribute \src "libresoc.v:169193.3-169194.41" + process $proc$libresoc.v:169193$9271 assign { } { } assign $0\trap_op__msr[63:0] \trap_op__msr$next sync posedge \coresync_clk update \trap_op__msr $0\trap_op__msr[63:0] end - attribute \src "libresoc.v:167887.3-167888.41" - process $proc$libresoc.v:167887$9288 + attribute \src "libresoc.v:169195.3-169196.41" + process $proc$libresoc.v:169195$9272 assign { } { } assign $0\trap_op__cia[63:0] \trap_op__cia$next sync posedge \coresync_clk update \trap_op__cia $0\trap_op__cia[63:0] end - attribute \src "libresoc.v:167889.3-167890.51" - process $proc$libresoc.v:167889$9289 + attribute \src "libresoc.v:169197.3-169198.51" + process $proc$libresoc.v:169197$9273 assign { } { } assign $0\trap_op__is_32bit[0:0] \trap_op__is_32bit$next sync posedge \coresync_clk update \trap_op__is_32bit $0\trap_op__is_32bit[0:0] end - attribute \src "libresoc.v:167891.3-167892.51" - process $proc$libresoc.v:167891$9290 + attribute \src "libresoc.v:169199.3-169200.51" + process $proc$libresoc.v:169199$9274 assign { } { } assign $0\trap_op__traptype[7:0] \trap_op__traptype$next sync posedge \coresync_clk update \trap_op__traptype $0\trap_op__traptype[7:0] end - attribute \src "libresoc.v:167893.3-167894.51" - process $proc$libresoc.v:167893$9291 + attribute \src "libresoc.v:169201.3-169202.51" + process $proc$libresoc.v:169201$9275 assign { } { } assign $0\trap_op__trapaddr[12:0] \trap_op__trapaddr$next sync posedge \coresync_clk update \trap_op__trapaddr $0\trap_op__trapaddr[12:0] end - attribute \src "libresoc.v:167895.3-167896.51" - process $proc$libresoc.v:167895$9292 + attribute \src "libresoc.v:169203.3-169204.51" + process $proc$libresoc.v:169203$9276 assign { } { } assign $0\trap_op__ldst_exc[7:0] \trap_op__ldst_exc$next sync posedge \coresync_clk update \trap_op__ldst_exc $0\trap_op__ldst_exc[7:0] end - attribute \src "libresoc.v:167897.3-167898.27" - process $proc$libresoc.v:167897$9293 + attribute \src "libresoc.v:169205.3-169206.27" + process $proc$libresoc.v:169205$9277 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:167899.3-167900.29" - process $proc$libresoc.v:167899$9294 + attribute \src "libresoc.v:169207.3-169208.29" + process $proc$libresoc.v:169207$9278 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:167939.3-167956.6" - process $proc$libresoc.v:167939$9295 + attribute \src "libresoc.v:169247.3-169264.6" + process $proc$libresoc.v:169247$9279 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9296 $2\r_busy$next[0:0]$9298 - attribute \src "libresoc.v:167940.5-167940.29" + assign $0\r_busy$next[0:0]$9280 $2\r_busy$next[0:0]$9282 + attribute \src "libresoc.v:169248.5-169248.29" switch \initial - attribute \src "libresoc.v:167940.9-167940.17" + attribute \src "libresoc.v:169248.9-169248.17" case 1'1 case end @@ -342743,34 +314113,34 @@ module \pipe1$32 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9297 1'1 + assign $1\r_busy$next[0:0]$9281 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9297 1'0 + assign $1\r_busy$next[0:0]$9281 1'0 case - assign $1\r_busy$next[0:0]$9297 \r_busy + assign $1\r_busy$next[0:0]$9281 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9298 1'0 + assign $2\r_busy$next[0:0]$9282 1'0 case - assign $2\r_busy$next[0:0]$9298 $1\r_busy$next[0:0]$9297 + assign $2\r_busy$next[0:0]$9282 $1\r_busy$next[0:0]$9281 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9296 + update \r_busy$next $0\r_busy$next[0:0]$9280 end - attribute \src "libresoc.v:167957.3-167969.6" - process $proc$libresoc.v:167957$9299 + attribute \src "libresoc.v:169265.3-169277.6" + process $proc$libresoc.v:169265$9283 assign { } { } assign { } { } - assign $0\muxid$next[1:0]$9300 $1\muxid$next[1:0]$9301 - attribute \src "libresoc.v:167958.5-167958.29" + assign $0\muxid$next[1:0]$9284 $1\muxid$next[1:0]$9285 + attribute \src "libresoc.v:169266.5-169266.29" switch \initial - attribute \src "libresoc.v:167958.9-167958.17" + attribute \src "libresoc.v:169266.9-169266.17" case 1'1 case end @@ -342779,19 +314149,19 @@ module \pipe1$32 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$next[1:0]$9301 \muxid$32 + assign $1\muxid$next[1:0]$9285 \muxid$32 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$next[1:0]$9301 \muxid$32 + assign $1\muxid$next[1:0]$9285 \muxid$32 case - assign $1\muxid$next[1:0]$9301 \muxid + assign $1\muxid$next[1:0]$9285 \muxid end sync always - update \muxid$next $0\muxid$next[1:0]$9300 + update \muxid$next $0\muxid$next[1:0]$9284 end - attribute \src "libresoc.v:167970.3-167990.6" - process $proc$libresoc.v:167970$9302 + attribute \src "libresoc.v:169278.3-169298.6" + process $proc$libresoc.v:169278$9286 assign { } { } assign { } { } assign { } { } @@ -342810,18 +314180,18 @@ module \pipe1$32 assign { } { } assign { } { } assign { } { } - assign $0\trap_op__cia$next[63:0]$9303 $1\trap_op__cia$next[63:0]$9312 - assign $0\trap_op__fn_unit$next[13:0]$9304 $1\trap_op__fn_unit$next[13:0]$9313 - assign $0\trap_op__insn$next[31:0]$9305 $1\trap_op__insn$next[31:0]$9314 - assign $0\trap_op__insn_type$next[6:0]$9306 $1\trap_op__insn_type$next[6:0]$9315 - assign $0\trap_op__is_32bit$next[0:0]$9307 $1\trap_op__is_32bit$next[0:0]$9316 - assign $0\trap_op__ldst_exc$next[7:0]$9308 $1\trap_op__ldst_exc$next[7:0]$9317 - assign $0\trap_op__msr$next[63:0]$9309 $1\trap_op__msr$next[63:0]$9318 - assign $0\trap_op__trapaddr$next[12:0]$9310 $1\trap_op__trapaddr$next[12:0]$9319 - assign $0\trap_op__traptype$next[7:0]$9311 $1\trap_op__traptype$next[7:0]$9320 - attribute \src "libresoc.v:167971.5-167971.29" + assign $0\trap_op__cia$next[63:0]$9287 $1\trap_op__cia$next[63:0]$9296 + assign $0\trap_op__fn_unit$next[13:0]$9288 $1\trap_op__fn_unit$next[13:0]$9297 + assign $0\trap_op__insn$next[31:0]$9289 $1\trap_op__insn$next[31:0]$9298 + assign $0\trap_op__insn_type$next[6:0]$9290 $1\trap_op__insn_type$next[6:0]$9299 + assign $0\trap_op__is_32bit$next[0:0]$9291 $1\trap_op__is_32bit$next[0:0]$9300 + assign $0\trap_op__ldst_exc$next[7:0]$9292 $1\trap_op__ldst_exc$next[7:0]$9301 + assign $0\trap_op__msr$next[63:0]$9293 $1\trap_op__msr$next[63:0]$9302 + assign $0\trap_op__trapaddr$next[12:0]$9294 $1\trap_op__trapaddr$next[12:0]$9303 + assign $0\trap_op__traptype$next[7:0]$9295 $1\trap_op__traptype$next[7:0]$9304 + attribute \src "libresoc.v:169279.5-169279.29" switch \initial - attribute \src "libresoc.v:167971.9-167971.17" + attribute \src "libresoc.v:169279.9-169279.17" case 1'1 case end @@ -342838,7 +314208,7 @@ module \pipe1$32 assign { } { } assign { } { } assign { } { } - assign { $1\trap_op__ldst_exc$next[7:0]$9317 $1\trap_op__trapaddr$next[12:0]$9319 $1\trap_op__traptype$next[7:0]$9320 $1\trap_op__is_32bit$next[0:0]$9316 $1\trap_op__cia$next[63:0]$9312 $1\trap_op__msr$next[63:0]$9318 $1\trap_op__insn$next[31:0]$9314 $1\trap_op__fn_unit$next[13:0]$9313 $1\trap_op__insn_type$next[6:0]$9315 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } + assign { $1\trap_op__ldst_exc$next[7:0]$9301 $1\trap_op__trapaddr$next[12:0]$9303 $1\trap_op__traptype$next[7:0]$9304 $1\trap_op__is_32bit$next[0:0]$9300 $1\trap_op__cia$next[63:0]$9296 $1\trap_op__msr$next[63:0]$9302 $1\trap_op__insn$next[31:0]$9298 $1\trap_op__fn_unit$next[13:0]$9297 $1\trap_op__insn_type$next[6:0]$9299 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -342850,37 +314220,37 @@ module \pipe1$32 assign { } { } assign { } { } assign { } { } - assign { $1\trap_op__ldst_exc$next[7:0]$9317 $1\trap_op__trapaddr$next[12:0]$9319 $1\trap_op__traptype$next[7:0]$9320 $1\trap_op__is_32bit$next[0:0]$9316 $1\trap_op__cia$next[63:0]$9312 $1\trap_op__msr$next[63:0]$9318 $1\trap_op__insn$next[31:0]$9314 $1\trap_op__fn_unit$next[13:0]$9313 $1\trap_op__insn_type$next[6:0]$9315 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } + assign { $1\trap_op__ldst_exc$next[7:0]$9301 $1\trap_op__trapaddr$next[12:0]$9303 $1\trap_op__traptype$next[7:0]$9304 $1\trap_op__is_32bit$next[0:0]$9300 $1\trap_op__cia$next[63:0]$9296 $1\trap_op__msr$next[63:0]$9302 $1\trap_op__insn$next[31:0]$9298 $1\trap_op__fn_unit$next[13:0]$9297 $1\trap_op__insn_type$next[6:0]$9299 } { \trap_op__ldst_exc$41 \trap_op__trapaddr$40 \trap_op__traptype$39 \trap_op__is_32bit$38 \trap_op__cia$37 \trap_op__msr$36 \trap_op__insn$35 \trap_op__fn_unit$34 \trap_op__insn_type$33 } case - assign $1\trap_op__cia$next[63:0]$9312 \trap_op__cia - assign $1\trap_op__fn_unit$next[13:0]$9313 \trap_op__fn_unit - assign $1\trap_op__insn$next[31:0]$9314 \trap_op__insn - assign $1\trap_op__insn_type$next[6:0]$9315 \trap_op__insn_type - assign $1\trap_op__is_32bit$next[0:0]$9316 \trap_op__is_32bit - assign $1\trap_op__ldst_exc$next[7:0]$9317 \trap_op__ldst_exc - assign $1\trap_op__msr$next[63:0]$9318 \trap_op__msr - assign $1\trap_op__trapaddr$next[12:0]$9319 \trap_op__trapaddr - assign $1\trap_op__traptype$next[7:0]$9320 \trap_op__traptype + assign $1\trap_op__cia$next[63:0]$9296 \trap_op__cia + assign $1\trap_op__fn_unit$next[13:0]$9297 \trap_op__fn_unit + assign $1\trap_op__insn$next[31:0]$9298 \trap_op__insn + assign $1\trap_op__insn_type$next[6:0]$9299 \trap_op__insn_type + assign $1\trap_op__is_32bit$next[0:0]$9300 \trap_op__is_32bit + assign $1\trap_op__ldst_exc$next[7:0]$9301 \trap_op__ldst_exc + assign $1\trap_op__msr$next[63:0]$9302 \trap_op__msr + assign $1\trap_op__trapaddr$next[12:0]$9303 \trap_op__trapaddr + assign $1\trap_op__traptype$next[7:0]$9304 \trap_op__traptype end sync always - update \trap_op__cia$next $0\trap_op__cia$next[63:0]$9303 - update \trap_op__fn_unit$next $0\trap_op__fn_unit$next[13:0]$9304 - update \trap_op__insn$next $0\trap_op__insn$next[31:0]$9305 - update \trap_op__insn_type$next $0\trap_op__insn_type$next[6:0]$9306 - update \trap_op__is_32bit$next $0\trap_op__is_32bit$next[0:0]$9307 - update \trap_op__ldst_exc$next $0\trap_op__ldst_exc$next[7:0]$9308 - update \trap_op__msr$next $0\trap_op__msr$next[63:0]$9309 - update \trap_op__trapaddr$next $0\trap_op__trapaddr$next[12:0]$9310 - update \trap_op__traptype$next $0\trap_op__traptype$next[7:0]$9311 + update \trap_op__cia$next $0\trap_op__cia$next[63:0]$9287 + update \trap_op__fn_unit$next $0\trap_op__fn_unit$next[13:0]$9288 + update \trap_op__insn$next $0\trap_op__insn$next[31:0]$9289 + update \trap_op__insn_type$next $0\trap_op__insn_type$next[6:0]$9290 + update \trap_op__is_32bit$next $0\trap_op__is_32bit$next[0:0]$9291 + update \trap_op__ldst_exc$next $0\trap_op__ldst_exc$next[7:0]$9292 + update \trap_op__msr$next $0\trap_op__msr$next[63:0]$9293 + update \trap_op__trapaddr$next $0\trap_op__trapaddr$next[12:0]$9294 + update \trap_op__traptype$next $0\trap_op__traptype$next[7:0]$9295 end - attribute \src "libresoc.v:167991.3-168003.6" - process $proc$libresoc.v:167991$9321 + attribute \src "libresoc.v:169299.3-169311.6" + process $proc$libresoc.v:169299$9305 assign { } { } assign { } { } - assign $0\ra$next[63:0]$9322 $1\ra$next[63:0]$9323 - attribute \src "libresoc.v:167992.5-167992.29" + assign $0\ra$next[63:0]$9306 $1\ra$next[63:0]$9307 + attribute \src "libresoc.v:169300.5-169300.29" switch \initial - attribute \src "libresoc.v:167992.9-167992.17" + attribute \src "libresoc.v:169300.9-169300.17" case 1'1 case end @@ -342889,25 +314259,25 @@ module \pipe1$32 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\ra$next[63:0]$9323 \ra$42 + assign $1\ra$next[63:0]$9307 \ra$42 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\ra$next[63:0]$9323 \ra$42 + assign $1\ra$next[63:0]$9307 \ra$42 case - assign $1\ra$next[63:0]$9323 \ra + assign $1\ra$next[63:0]$9307 \ra end sync always - update \ra$next $0\ra$next[63:0]$9322 + update \ra$next $0\ra$next[63:0]$9306 end - attribute \src "libresoc.v:168004.3-168016.6" - process $proc$libresoc.v:168004$9324 + attribute \src "libresoc.v:169312.3-169324.6" + process $proc$libresoc.v:169312$9308 assign { } { } assign { } { } - assign $0\rb$next[63:0]$9325 $1\rb$next[63:0]$9326 - attribute \src "libresoc.v:168005.5-168005.29" + assign $0\rb$next[63:0]$9309 $1\rb$next[63:0]$9310 + attribute \src "libresoc.v:169313.5-169313.29" switch \initial - attribute \src "libresoc.v:168005.9-168005.17" + attribute \src "libresoc.v:169313.9-169313.17" case 1'1 case end @@ -342916,25 +314286,25 @@ module \pipe1$32 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\rb$next[63:0]$9326 \rb$43 + assign $1\rb$next[63:0]$9310 \rb$43 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\rb$next[63:0]$9326 \rb$43 + assign $1\rb$next[63:0]$9310 \rb$43 case - assign $1\rb$next[63:0]$9326 \rb + assign $1\rb$next[63:0]$9310 \rb end sync always - update \rb$next $0\rb$next[63:0]$9325 + update \rb$next $0\rb$next[63:0]$9309 end - attribute \src "libresoc.v:168017.3-168029.6" - process $proc$libresoc.v:168017$9327 + attribute \src "libresoc.v:169325.3-169337.6" + process $proc$libresoc.v:169325$9311 assign { } { } assign { } { } - assign $0\fast1$next[63:0]$9328 $1\fast1$next[63:0]$9329 - attribute \src "libresoc.v:168018.5-168018.29" + assign $0\fast1$next[63:0]$9312 $1\fast1$next[63:0]$9313 + attribute \src "libresoc.v:169326.5-169326.29" switch \initial - attribute \src "libresoc.v:168018.9-168018.17" + attribute \src "libresoc.v:169326.9-169326.17" case 1'1 case end @@ -342943,25 +314313,25 @@ module \pipe1$32 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\fast1$next[63:0]$9329 \fast1$44 + assign $1\fast1$next[63:0]$9313 \fast1$44 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\fast1$next[63:0]$9329 \fast1$44 + assign $1\fast1$next[63:0]$9313 \fast1$44 case - assign $1\fast1$next[63:0]$9329 \fast1 + assign $1\fast1$next[63:0]$9313 \fast1 end sync always - update \fast1$next $0\fast1$next[63:0]$9328 + update \fast1$next $0\fast1$next[63:0]$9312 end - attribute \src "libresoc.v:168030.3-168042.6" - process $proc$libresoc.v:168030$9330 + attribute \src "libresoc.v:169338.3-169350.6" + process $proc$libresoc.v:169338$9314 assign { } { } assign { } { } - assign $0\fast2$next[63:0]$9331 $1\fast2$next[63:0]$9332 - attribute \src "libresoc.v:168031.5-168031.29" + assign $0\fast2$next[63:0]$9315 $1\fast2$next[63:0]$9316 + attribute \src "libresoc.v:169339.5-169339.29" switch \initial - attribute \src "libresoc.v:168031.9-168031.17" + attribute \src "libresoc.v:169339.9-169339.17" case 1'1 case end @@ -342970,18 +314340,18 @@ module \pipe1$32 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\fast2$next[63:0]$9332 \fast2$45 + assign $1\fast2$next[63:0]$9316 \fast2$45 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\fast2$next[63:0]$9332 \fast2$45 + assign $1\fast2$next[63:0]$9316 \fast2$45 case - assign $1\fast2$next[63:0]$9332 \fast2 + assign $1\fast2$next[63:0]$9316 \fast2 end sync always - update \fast2$next $0\fast2$next[63:0]$9331 + update \fast2$next $0\fast2$next[63:0]$9315 end - connect \$30 $and$libresoc.v:167870$9279_Y + connect \$30 $and$libresoc.v:169178$9263_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect \fast2$45 \dummy_fast2$28 @@ -343000,279 +314370,279 @@ module \pipe1$32 connect { \dummy_trap_op__ldst_exc \dummy_trap_op__trapaddr \dummy_trap_op__traptype \dummy_trap_op__is_32bit \dummy_trap_op__cia \dummy_trap_op__msr \dummy_trap_op__insn \dummy_trap_op__fn_unit \dummy_trap_op__insn_type } { \trap_op__ldst_exc$10 \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } connect \dummy_muxid \muxid$1 end -attribute \src "libresoc.v:168064.1-169249.10" +attribute \src "libresoc.v:169372.1-170557.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.alu_alu0.pipe2" attribute \generator "nMigen" module \pipe2 - attribute \src "libresoc.v:169093.3-169134.6" - wire width 4 $0\alu_op__data_len$18$next[3:0]$9417 - attribute \src "libresoc.v:168990.3-168991.57" - wire width 4 $0\alu_op__data_len$18[3:0]$9403 - attribute \src "libresoc.v:168072.13-168072.41" - wire width 4 $0\alu_op__data_len$18[3:0]$9491 - attribute \src "libresoc.v:169093.3-169134.6" - wire width 14 $0\alu_op__fn_unit$3$next[13:0]$9418 - attribute \src "libresoc.v:168960.3-168961.53" - wire width 14 $0\alu_op__fn_unit$3[13:0]$9373 - attribute \src "libresoc.v:168111.14-168111.44" - wire width 14 $0\alu_op__fn_unit$3[13:0]$9493 - attribute \src "libresoc.v:169093.3-169134.6" - wire width 64 $0\alu_op__imm_data__data$4$next[63:0]$9419 - attribute \src "libresoc.v:168962.3-168963.67" - wire width 64 $0\alu_op__imm_data__data$4[63:0]$9375 - attribute \src "libresoc.v:168135.14-168135.63" - wire width 64 $0\alu_op__imm_data__data$4[63:0]$9495 - attribute \src "libresoc.v:169093.3-169134.6" - wire $0\alu_op__imm_data__ok$5$next[0:0]$9420 - attribute \src "libresoc.v:168964.3-168965.63" - wire $0\alu_op__imm_data__ok$5[0:0]$9377 - attribute \src "libresoc.v:168144.7-168144.38" - wire $0\alu_op__imm_data__ok$5[0:0]$9497 - attribute \src "libresoc.v:169093.3-169134.6" - wire width 2 $0\alu_op__input_carry$14$next[1:0]$9421 - attribute \src "libresoc.v:168982.3-168983.63" - wire width 2 $0\alu_op__input_carry$14[1:0]$9395 - attribute \src "libresoc.v:168161.13-168161.44" - wire width 2 $0\alu_op__input_carry$14[1:0]$9499 - attribute \src "libresoc.v:169093.3-169134.6" - wire width 32 $0\alu_op__insn$19$next[31:0]$9422 - attribute \src "libresoc.v:168992.3-168993.49" - wire width 32 $0\alu_op__insn$19[31:0]$9405 - attribute \src "libresoc.v:168174.14-168174.39" - wire width 32 $0\alu_op__insn$19[31:0]$9501 - attribute \src "libresoc.v:169093.3-169134.6" - wire width 7 $0\alu_op__insn_type$2$next[6:0]$9423 - attribute \src "libresoc.v:168958.3-168959.57" - wire width 7 $0\alu_op__insn_type$2[6:0]$9371 - attribute \src "libresoc.v:168333.13-168333.42" - wire width 7 $0\alu_op__insn_type$2[6:0]$9503 - attribute \src "libresoc.v:169093.3-169134.6" - wire $0\alu_op__invert_in$10$next[0:0]$9424 - attribute \src "libresoc.v:168974.3-168975.59" - wire $0\alu_op__invert_in$10[0:0]$9387 - attribute \src "libresoc.v:168417.7-168417.36" - wire $0\alu_op__invert_in$10[0:0]$9505 - attribute \src "libresoc.v:169093.3-169134.6" - wire $0\alu_op__invert_out$12$next[0:0]$9425 - attribute \src "libresoc.v:168978.3-168979.61" - wire $0\alu_op__invert_out$12[0:0]$9391 - attribute \src "libresoc.v:168426.7-168426.37" - wire $0\alu_op__invert_out$12[0:0]$9507 - attribute \src "libresoc.v:169093.3-169134.6" - wire $0\alu_op__is_32bit$16$next[0:0]$9426 - attribute \src "libresoc.v:168986.3-168987.57" - wire $0\alu_op__is_32bit$16[0:0]$9399 - attribute \src "libresoc.v:168435.7-168435.35" - wire $0\alu_op__is_32bit$16[0:0]$9509 - attribute \src "libresoc.v:169093.3-169134.6" - wire $0\alu_op__is_signed$17$next[0:0]$9427 - attribute \src "libresoc.v:168988.3-168989.59" - wire $0\alu_op__is_signed$17[0:0]$9401 - attribute \src "libresoc.v:168444.7-168444.36" - wire $0\alu_op__is_signed$17[0:0]$9511 - attribute \src "libresoc.v:169093.3-169134.6" - wire $0\alu_op__oe__oe$8$next[0:0]$9428 - attribute \src "libresoc.v:168970.3-168971.51" - wire $0\alu_op__oe__oe$8[0:0]$9383 - attribute \src "libresoc.v:168455.7-168455.32" - wire $0\alu_op__oe__oe$8[0:0]$9513 - attribute \src "libresoc.v:169093.3-169134.6" - wire $0\alu_op__oe__ok$9$next[0:0]$9429 - attribute \src "libresoc.v:168972.3-168973.51" - wire $0\alu_op__oe__ok$9[0:0]$9385 - attribute \src "libresoc.v:168464.7-168464.32" - wire $0\alu_op__oe__ok$9[0:0]$9515 - attribute \src "libresoc.v:169093.3-169134.6" - wire $0\alu_op__output_carry$15$next[0:0]$9430 - attribute \src "libresoc.v:168984.3-168985.65" - wire $0\alu_op__output_carry$15[0:0]$9397 - attribute \src "libresoc.v:168471.7-168471.39" - wire $0\alu_op__output_carry$15[0:0]$9517 - attribute \src "libresoc.v:169093.3-169134.6" - wire $0\alu_op__rc__ok$7$next[0:0]$9431 - attribute \src "libresoc.v:168968.3-168969.51" - wire $0\alu_op__rc__ok$7[0:0]$9381 - attribute \src "libresoc.v:168482.7-168482.32" - wire $0\alu_op__rc__ok$7[0:0]$9519 - attribute \src "libresoc.v:169093.3-169134.6" - wire $0\alu_op__rc__rc$6$next[0:0]$9432 - attribute \src "libresoc.v:168966.3-168967.51" - wire $0\alu_op__rc__rc$6[0:0]$9379 - attribute \src "libresoc.v:168489.7-168489.32" - wire $0\alu_op__rc__rc$6[0:0]$9521 - attribute \src "libresoc.v:169093.3-169134.6" - wire $0\alu_op__write_cr0$13$next[0:0]$9433 - attribute \src "libresoc.v:168980.3-168981.59" - wire $0\alu_op__write_cr0$13[0:0]$9393 - attribute \src "libresoc.v:168498.7-168498.36" - wire $0\alu_op__write_cr0$13[0:0]$9523 - attribute \src "libresoc.v:169093.3-169134.6" - wire $0\alu_op__zero_a$11$next[0:0]$9434 - attribute \src "libresoc.v:168976.3-168977.53" - wire $0\alu_op__zero_a$11[0:0]$9389 - attribute \src "libresoc.v:168507.7-168507.33" - wire $0\alu_op__zero_a$11[0:0]$9525 - attribute \src "libresoc.v:169154.3-169172.6" - wire width 4 $0\cr_a$22$next[3:0]$9466 - attribute \src "libresoc.v:168950.3-168951.33" - wire width 4 $0\cr_a$22[3:0]$9363 - attribute \src "libresoc.v:168520.13-168520.29" - wire width 4 $0\cr_a$22[3:0]$9527 - attribute \src "libresoc.v:169154.3-169172.6" - wire $0\cr_a_ok$23$next[0:0]$9467 - attribute \src "libresoc.v:168952.3-168953.39" - wire $0\cr_a_ok$23[0:0]$9365 - attribute \src "libresoc.v:168529.7-168529.26" - wire $0\cr_a_ok$23[0:0]$9529 - attribute \src "libresoc.v:168065.7-168065.20" + attribute \src "libresoc.v:170401.3-170442.6" + wire width 4 $0\alu_op__data_len$18$next[3:0]$9401 + attribute \src "libresoc.v:170298.3-170299.57" + wire width 4 $0\alu_op__data_len$18[3:0]$9387 + attribute \src "libresoc.v:169380.13-169380.41" + wire width 4 $0\alu_op__data_len$18[3:0]$9475 + attribute \src "libresoc.v:170401.3-170442.6" + wire width 14 $0\alu_op__fn_unit$3$next[13:0]$9402 + attribute \src "libresoc.v:170268.3-170269.53" + wire width 14 $0\alu_op__fn_unit$3[13:0]$9357 + attribute \src "libresoc.v:169419.14-169419.44" + wire width 14 $0\alu_op__fn_unit$3[13:0]$9477 + attribute \src "libresoc.v:170401.3-170442.6" + wire width 64 $0\alu_op__imm_data__data$4$next[63:0]$9403 + attribute \src "libresoc.v:170270.3-170271.67" + wire width 64 $0\alu_op__imm_data__data$4[63:0]$9359 + attribute \src "libresoc.v:169443.14-169443.63" + wire width 64 $0\alu_op__imm_data__data$4[63:0]$9479 + attribute \src "libresoc.v:170401.3-170442.6" + wire $0\alu_op__imm_data__ok$5$next[0:0]$9404 + attribute \src "libresoc.v:170272.3-170273.63" + wire $0\alu_op__imm_data__ok$5[0:0]$9361 + attribute \src "libresoc.v:169452.7-169452.38" + wire $0\alu_op__imm_data__ok$5[0:0]$9481 + attribute \src "libresoc.v:170401.3-170442.6" + wire width 2 $0\alu_op__input_carry$14$next[1:0]$9405 + attribute \src "libresoc.v:170290.3-170291.63" + wire width 2 $0\alu_op__input_carry$14[1:0]$9379 + attribute \src "libresoc.v:169469.13-169469.44" + wire width 2 $0\alu_op__input_carry$14[1:0]$9483 + attribute \src "libresoc.v:170401.3-170442.6" + wire width 32 $0\alu_op__insn$19$next[31:0]$9406 + attribute \src "libresoc.v:170300.3-170301.49" + wire width 32 $0\alu_op__insn$19[31:0]$9389 + attribute \src "libresoc.v:169482.14-169482.39" + wire width 32 $0\alu_op__insn$19[31:0]$9485 + attribute \src "libresoc.v:170401.3-170442.6" + wire width 7 $0\alu_op__insn_type$2$next[6:0]$9407 + attribute \src "libresoc.v:170266.3-170267.57" + wire width 7 $0\alu_op__insn_type$2[6:0]$9355 + attribute \src "libresoc.v:169641.13-169641.42" + wire width 7 $0\alu_op__insn_type$2[6:0]$9487 + attribute \src "libresoc.v:170401.3-170442.6" + wire $0\alu_op__invert_in$10$next[0:0]$9408 + attribute \src "libresoc.v:170282.3-170283.59" + wire $0\alu_op__invert_in$10[0:0]$9371 + attribute \src "libresoc.v:169725.7-169725.36" + wire $0\alu_op__invert_in$10[0:0]$9489 + attribute \src "libresoc.v:170401.3-170442.6" + wire $0\alu_op__invert_out$12$next[0:0]$9409 + attribute \src "libresoc.v:170286.3-170287.61" + wire $0\alu_op__invert_out$12[0:0]$9375 + attribute \src "libresoc.v:169734.7-169734.37" + wire $0\alu_op__invert_out$12[0:0]$9491 + attribute \src "libresoc.v:170401.3-170442.6" + wire $0\alu_op__is_32bit$16$next[0:0]$9410 + attribute \src "libresoc.v:170294.3-170295.57" + wire $0\alu_op__is_32bit$16[0:0]$9383 + attribute \src "libresoc.v:169743.7-169743.35" + wire $0\alu_op__is_32bit$16[0:0]$9493 + attribute \src "libresoc.v:170401.3-170442.6" + wire $0\alu_op__is_signed$17$next[0:0]$9411 + attribute \src "libresoc.v:170296.3-170297.59" + wire $0\alu_op__is_signed$17[0:0]$9385 + attribute \src "libresoc.v:169752.7-169752.36" + wire $0\alu_op__is_signed$17[0:0]$9495 + attribute \src "libresoc.v:170401.3-170442.6" + wire $0\alu_op__oe__oe$8$next[0:0]$9412 + attribute \src "libresoc.v:170278.3-170279.51" + wire $0\alu_op__oe__oe$8[0:0]$9367 + attribute \src "libresoc.v:169763.7-169763.32" + wire $0\alu_op__oe__oe$8[0:0]$9497 + attribute \src "libresoc.v:170401.3-170442.6" + wire $0\alu_op__oe__ok$9$next[0:0]$9413 + attribute \src "libresoc.v:170280.3-170281.51" + wire $0\alu_op__oe__ok$9[0:0]$9369 + attribute \src "libresoc.v:169772.7-169772.32" + wire $0\alu_op__oe__ok$9[0:0]$9499 + attribute \src "libresoc.v:170401.3-170442.6" + wire $0\alu_op__output_carry$15$next[0:0]$9414 + attribute \src "libresoc.v:170292.3-170293.65" + wire $0\alu_op__output_carry$15[0:0]$9381 + attribute \src "libresoc.v:169779.7-169779.39" + wire $0\alu_op__output_carry$15[0:0]$9501 + attribute \src "libresoc.v:170401.3-170442.6" + wire $0\alu_op__rc__ok$7$next[0:0]$9415 + attribute \src "libresoc.v:170276.3-170277.51" + wire $0\alu_op__rc__ok$7[0:0]$9365 + attribute \src "libresoc.v:169790.7-169790.32" + wire $0\alu_op__rc__ok$7[0:0]$9503 + attribute \src "libresoc.v:170401.3-170442.6" + wire $0\alu_op__rc__rc$6$next[0:0]$9416 + attribute \src "libresoc.v:170274.3-170275.51" + wire $0\alu_op__rc__rc$6[0:0]$9363 + attribute \src "libresoc.v:169797.7-169797.32" + wire $0\alu_op__rc__rc$6[0:0]$9505 + attribute \src "libresoc.v:170401.3-170442.6" + wire $0\alu_op__write_cr0$13$next[0:0]$9417 + attribute \src "libresoc.v:170288.3-170289.59" + wire $0\alu_op__write_cr0$13[0:0]$9377 + attribute \src "libresoc.v:169806.7-169806.36" + wire $0\alu_op__write_cr0$13[0:0]$9507 + attribute \src "libresoc.v:170401.3-170442.6" + wire $0\alu_op__zero_a$11$next[0:0]$9418 + attribute \src "libresoc.v:170284.3-170285.53" + wire $0\alu_op__zero_a$11[0:0]$9373 + attribute \src "libresoc.v:169815.7-169815.33" + wire $0\alu_op__zero_a$11[0:0]$9509 + attribute \src "libresoc.v:170462.3-170480.6" + wire width 4 $0\cr_a$22$next[3:0]$9450 + attribute \src "libresoc.v:170258.3-170259.33" + wire width 4 $0\cr_a$22[3:0]$9347 + attribute \src "libresoc.v:169828.13-169828.29" + wire width 4 $0\cr_a$22[3:0]$9511 + attribute \src "libresoc.v:170462.3-170480.6" + wire $0\cr_a_ok$23$next[0:0]$9451 + attribute \src "libresoc.v:170260.3-170261.39" + wire $0\cr_a_ok$23[0:0]$9349 + attribute \src "libresoc.v:169837.7-169837.26" + wire $0\cr_a_ok$23[0:0]$9513 + attribute \src "libresoc.v:169373.7-169373.20" wire $0\initial[0:0] - attribute \src "libresoc.v:169080.3-169092.6" - wire width 2 $0\muxid$1$next[1:0]$9414 - attribute \src "libresoc.v:168994.3-168995.33" - wire width 2 $0\muxid$1[1:0]$9407 - attribute \src "libresoc.v:168540.13-168540.29" - wire width 2 $0\muxid$1[1:0]$9531 - attribute \src "libresoc.v:169135.3-169153.6" - wire width 64 $0\o$20$next[63:0]$9460 - attribute \src "libresoc.v:168954.3-168955.27" - wire width 64 $0\o$20[63:0]$9367 - attribute \src "libresoc.v:168555.14-168555.43" - wire width 64 $0\o$20[63:0]$9533 - attribute \src "libresoc.v:169135.3-169153.6" - wire $0\o_ok$21$next[0:0]$9461 - attribute \src "libresoc.v:168956.3-168957.33" - wire $0\o_ok$21[0:0]$9369 - attribute \src "libresoc.v:168564.7-168564.23" - wire $0\o_ok$21[0:0]$9535 - attribute \src "libresoc.v:169062.3-169079.6" - wire $0\r_busy$next[0:0]$9410 - attribute \src "libresoc.v:168996.3-168997.29" + attribute \src "libresoc.v:170388.3-170400.6" + wire width 2 $0\muxid$1$next[1:0]$9398 + attribute \src "libresoc.v:170302.3-170303.33" + wire width 2 $0\muxid$1[1:0]$9391 + attribute \src "libresoc.v:169848.13-169848.29" + wire width 2 $0\muxid$1[1:0]$9515 + attribute \src "libresoc.v:170443.3-170461.6" + wire width 64 $0\o$20$next[63:0]$9444 + attribute \src "libresoc.v:170262.3-170263.27" + wire width 64 $0\o$20[63:0]$9351 + attribute \src "libresoc.v:169863.14-169863.43" + wire width 64 $0\o$20[63:0]$9517 + attribute \src "libresoc.v:170443.3-170461.6" + wire $0\o_ok$21$next[0:0]$9445 + attribute \src "libresoc.v:170264.3-170265.33" + wire $0\o_ok$21[0:0]$9353 + attribute \src "libresoc.v:169872.7-169872.23" + wire $0\o_ok$21[0:0]$9519 + attribute \src "libresoc.v:170370.3-170387.6" + wire $0\r_busy$next[0:0]$9394 + attribute \src "libresoc.v:170304.3-170305.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:169173.3-169191.6" - wire width 2 $0\xer_ca$24$next[1:0]$9472 - attribute \src "libresoc.v:168946.3-168947.37" - wire width 2 $0\xer_ca$24[1:0]$9359 - attribute \src "libresoc.v:168881.13-168881.31" - wire width 2 $0\xer_ca$24[1:0]$9538 - attribute \src "libresoc.v:169173.3-169191.6" - wire $0\xer_ca_ok$25$next[0:0]$9473 - attribute \src "libresoc.v:168948.3-168949.43" - wire $0\xer_ca_ok$25[0:0]$9361 - attribute \src "libresoc.v:168890.7-168890.28" - wire $0\xer_ca_ok$25[0:0]$9540 - attribute \src "libresoc.v:169192.3-169210.6" - wire width 2 $0\xer_ov$26$next[1:0]$9478 - attribute \src "libresoc.v:168942.3-168943.37" - wire width 2 $0\xer_ov$26[1:0]$9355 - attribute \src "libresoc.v:168901.13-168901.31" - wire width 2 $0\xer_ov$26[1:0]$9542 - attribute \src "libresoc.v:169192.3-169210.6" - wire $0\xer_ov_ok$27$next[0:0]$9479 - attribute \src "libresoc.v:168944.3-168945.43" - wire $0\xer_ov_ok$27[0:0]$9357 - attribute \src "libresoc.v:168910.7-168910.28" - wire $0\xer_ov_ok$27[0:0]$9544 - attribute \src "libresoc.v:169211.3-169229.6" - wire $0\xer_so$28$next[0:0]$9484 - attribute \src "libresoc.v:168938.3-168939.37" - wire $0\xer_so$28[0:0]$9351 - attribute \src "libresoc.v:168921.7-168921.25" - wire $0\xer_so$28[0:0]$9546 - attribute \src "libresoc.v:169211.3-169229.6" - wire $0\xer_so_ok$29$next[0:0]$9485 - attribute \src "libresoc.v:168940.3-168941.43" - wire $0\xer_so_ok$29[0:0]$9353 - attribute \src "libresoc.v:168930.7-168930.28" - wire $0\xer_so_ok$29[0:0]$9548 - attribute \src "libresoc.v:169093.3-169134.6" - wire width 4 $1\alu_op__data_len$18$next[3:0]$9435 - attribute \src "libresoc.v:169093.3-169134.6" - wire width 14 $1\alu_op__fn_unit$3$next[13:0]$9436 - attribute \src "libresoc.v:169093.3-169134.6" - wire width 64 $1\alu_op__imm_data__data$4$next[63:0]$9437 - attribute \src "libresoc.v:169093.3-169134.6" - wire $1\alu_op__imm_data__ok$5$next[0:0]$9438 - attribute \src "libresoc.v:169093.3-169134.6" - wire width 2 $1\alu_op__input_carry$14$next[1:0]$9439 - attribute \src "libresoc.v:169093.3-169134.6" - wire width 32 $1\alu_op__insn$19$next[31:0]$9440 - attribute \src "libresoc.v:169093.3-169134.6" - wire width 7 $1\alu_op__insn_type$2$next[6:0]$9441 - attribute \src "libresoc.v:169093.3-169134.6" - wire $1\alu_op__invert_in$10$next[0:0]$9442 - attribute \src "libresoc.v:169093.3-169134.6" - wire $1\alu_op__invert_out$12$next[0:0]$9443 - attribute \src "libresoc.v:169093.3-169134.6" - wire $1\alu_op__is_32bit$16$next[0:0]$9444 - attribute \src "libresoc.v:169093.3-169134.6" - wire $1\alu_op__is_signed$17$next[0:0]$9445 - attribute \src "libresoc.v:169093.3-169134.6" - wire $1\alu_op__oe__oe$8$next[0:0]$9446 - attribute \src "libresoc.v:169093.3-169134.6" - wire $1\alu_op__oe__ok$9$next[0:0]$9447 - attribute \src "libresoc.v:169093.3-169134.6" - wire $1\alu_op__output_carry$15$next[0:0]$9448 - attribute \src "libresoc.v:169093.3-169134.6" - wire $1\alu_op__rc__ok$7$next[0:0]$9449 - attribute \src "libresoc.v:169093.3-169134.6" - wire $1\alu_op__rc__rc$6$next[0:0]$9450 - attribute \src "libresoc.v:169093.3-169134.6" - wire $1\alu_op__write_cr0$13$next[0:0]$9451 - attribute \src "libresoc.v:169093.3-169134.6" - wire $1\alu_op__zero_a$11$next[0:0]$9452 - attribute \src "libresoc.v:169154.3-169172.6" - wire width 4 $1\cr_a$22$next[3:0]$9468 - attribute \src "libresoc.v:169154.3-169172.6" - wire $1\cr_a_ok$23$next[0:0]$9469 - attribute \src "libresoc.v:169080.3-169092.6" - wire width 2 $1\muxid$1$next[1:0]$9415 - attribute \src "libresoc.v:169135.3-169153.6" - wire width 64 $1\o$20$next[63:0]$9462 - attribute \src "libresoc.v:169135.3-169153.6" - wire $1\o_ok$21$next[0:0]$9463 - attribute \src "libresoc.v:169062.3-169079.6" - wire $1\r_busy$next[0:0]$9411 - attribute \src "libresoc.v:168874.7-168874.20" + attribute \src "libresoc.v:170481.3-170499.6" + wire width 2 $0\xer_ca$24$next[1:0]$9456 + attribute \src "libresoc.v:170254.3-170255.37" + wire width 2 $0\xer_ca$24[1:0]$9343 + attribute \src "libresoc.v:170189.13-170189.31" + wire width 2 $0\xer_ca$24[1:0]$9522 + attribute \src "libresoc.v:170481.3-170499.6" + wire $0\xer_ca_ok$25$next[0:0]$9457 + attribute \src "libresoc.v:170256.3-170257.43" + wire $0\xer_ca_ok$25[0:0]$9345 + attribute \src "libresoc.v:170198.7-170198.28" + wire $0\xer_ca_ok$25[0:0]$9524 + attribute \src "libresoc.v:170500.3-170518.6" + wire width 2 $0\xer_ov$26$next[1:0]$9462 + attribute \src "libresoc.v:170250.3-170251.37" + wire width 2 $0\xer_ov$26[1:0]$9339 + attribute \src "libresoc.v:170209.13-170209.31" + wire width 2 $0\xer_ov$26[1:0]$9526 + attribute \src "libresoc.v:170500.3-170518.6" + wire $0\xer_ov_ok$27$next[0:0]$9463 + attribute \src "libresoc.v:170252.3-170253.43" + wire $0\xer_ov_ok$27[0:0]$9341 + attribute \src "libresoc.v:170218.7-170218.28" + wire $0\xer_ov_ok$27[0:0]$9528 + attribute \src "libresoc.v:170519.3-170537.6" + wire $0\xer_so$28$next[0:0]$9468 + attribute \src "libresoc.v:170246.3-170247.37" + wire $0\xer_so$28[0:0]$9335 + attribute \src "libresoc.v:170229.7-170229.25" + wire $0\xer_so$28[0:0]$9530 + attribute \src "libresoc.v:170519.3-170537.6" + wire $0\xer_so_ok$29$next[0:0]$9469 + attribute \src "libresoc.v:170248.3-170249.43" + wire $0\xer_so_ok$29[0:0]$9337 + attribute \src "libresoc.v:170238.7-170238.28" + wire $0\xer_so_ok$29[0:0]$9532 + attribute \src "libresoc.v:170401.3-170442.6" + wire width 4 $1\alu_op__data_len$18$next[3:0]$9419 + attribute \src "libresoc.v:170401.3-170442.6" + wire width 14 $1\alu_op__fn_unit$3$next[13:0]$9420 + attribute \src "libresoc.v:170401.3-170442.6" + wire width 64 $1\alu_op__imm_data__data$4$next[63:0]$9421 + attribute \src "libresoc.v:170401.3-170442.6" + wire $1\alu_op__imm_data__ok$5$next[0:0]$9422 + attribute \src "libresoc.v:170401.3-170442.6" + wire width 2 $1\alu_op__input_carry$14$next[1:0]$9423 + attribute \src "libresoc.v:170401.3-170442.6" + wire width 32 $1\alu_op__insn$19$next[31:0]$9424 + attribute \src "libresoc.v:170401.3-170442.6" + wire width 7 $1\alu_op__insn_type$2$next[6:0]$9425 + attribute \src "libresoc.v:170401.3-170442.6" + wire $1\alu_op__invert_in$10$next[0:0]$9426 + attribute \src "libresoc.v:170401.3-170442.6" + wire $1\alu_op__invert_out$12$next[0:0]$9427 + attribute \src "libresoc.v:170401.3-170442.6" + wire $1\alu_op__is_32bit$16$next[0:0]$9428 + attribute \src "libresoc.v:170401.3-170442.6" + wire $1\alu_op__is_signed$17$next[0:0]$9429 + attribute \src "libresoc.v:170401.3-170442.6" + wire $1\alu_op__oe__oe$8$next[0:0]$9430 + attribute \src "libresoc.v:170401.3-170442.6" + wire $1\alu_op__oe__ok$9$next[0:0]$9431 + attribute \src "libresoc.v:170401.3-170442.6" + wire $1\alu_op__output_carry$15$next[0:0]$9432 + attribute \src "libresoc.v:170401.3-170442.6" + wire $1\alu_op__rc__ok$7$next[0:0]$9433 + attribute \src "libresoc.v:170401.3-170442.6" + wire $1\alu_op__rc__rc$6$next[0:0]$9434 + attribute \src "libresoc.v:170401.3-170442.6" + wire $1\alu_op__write_cr0$13$next[0:0]$9435 + attribute \src "libresoc.v:170401.3-170442.6" + wire $1\alu_op__zero_a$11$next[0:0]$9436 + attribute \src "libresoc.v:170462.3-170480.6" + wire width 4 $1\cr_a$22$next[3:0]$9452 + attribute \src "libresoc.v:170462.3-170480.6" + wire $1\cr_a_ok$23$next[0:0]$9453 + attribute \src "libresoc.v:170388.3-170400.6" + wire width 2 $1\muxid$1$next[1:0]$9399 + attribute \src "libresoc.v:170443.3-170461.6" + wire width 64 $1\o$20$next[63:0]$9446 + attribute \src "libresoc.v:170443.3-170461.6" + wire $1\o_ok$21$next[0:0]$9447 + attribute \src "libresoc.v:170370.3-170387.6" + wire $1\r_busy$next[0:0]$9395 + attribute \src "libresoc.v:170182.7-170182.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:169173.3-169191.6" - wire width 2 $1\xer_ca$24$next[1:0]$9474 - attribute \src "libresoc.v:169173.3-169191.6" - wire $1\xer_ca_ok$25$next[0:0]$9475 - attribute \src "libresoc.v:169192.3-169210.6" - wire width 2 $1\xer_ov$26$next[1:0]$9480 - attribute \src "libresoc.v:169192.3-169210.6" - wire $1\xer_ov_ok$27$next[0:0]$9481 - attribute \src "libresoc.v:169211.3-169229.6" - wire $1\xer_so$28$next[0:0]$9486 - attribute \src "libresoc.v:169211.3-169229.6" - wire $1\xer_so_ok$29$next[0:0]$9487 - attribute \src "libresoc.v:169093.3-169134.6" - wire width 64 $2\alu_op__imm_data__data$4$next[63:0]$9453 - attribute \src "libresoc.v:169093.3-169134.6" - wire $2\alu_op__imm_data__ok$5$next[0:0]$9454 - attribute \src "libresoc.v:169093.3-169134.6" - wire $2\alu_op__oe__oe$8$next[0:0]$9455 - attribute \src "libresoc.v:169093.3-169134.6" - wire $2\alu_op__oe__ok$9$next[0:0]$9456 - attribute \src "libresoc.v:169093.3-169134.6" - wire $2\alu_op__rc__ok$7$next[0:0]$9457 - attribute \src "libresoc.v:169093.3-169134.6" - wire $2\alu_op__rc__rc$6$next[0:0]$9458 - attribute \src "libresoc.v:169154.3-169172.6" - wire $2\cr_a_ok$23$next[0:0]$9470 - attribute \src "libresoc.v:169135.3-169153.6" - wire $2\o_ok$21$next[0:0]$9464 - attribute \src "libresoc.v:169062.3-169079.6" - wire $2\r_busy$next[0:0]$9412 - attribute \src "libresoc.v:169173.3-169191.6" - wire $2\xer_ca_ok$25$next[0:0]$9476 - attribute \src "libresoc.v:169192.3-169210.6" - wire $2\xer_ov_ok$27$next[0:0]$9482 - attribute \src "libresoc.v:169211.3-169229.6" - wire $2\xer_so_ok$29$next[0:0]$9488 - attribute \src "libresoc.v:168937.18-168937.118" - wire $and$libresoc.v:168937$9349_Y + attribute \src "libresoc.v:170481.3-170499.6" + wire width 2 $1\xer_ca$24$next[1:0]$9458 + attribute \src "libresoc.v:170481.3-170499.6" + wire $1\xer_ca_ok$25$next[0:0]$9459 + attribute \src "libresoc.v:170500.3-170518.6" + wire width 2 $1\xer_ov$26$next[1:0]$9464 + attribute \src "libresoc.v:170500.3-170518.6" + wire $1\xer_ov_ok$27$next[0:0]$9465 + attribute \src "libresoc.v:170519.3-170537.6" + wire $1\xer_so$28$next[0:0]$9470 + attribute \src "libresoc.v:170519.3-170537.6" + wire $1\xer_so_ok$29$next[0:0]$9471 + attribute \src "libresoc.v:170401.3-170442.6" + wire width 64 $2\alu_op__imm_data__data$4$next[63:0]$9437 + attribute \src "libresoc.v:170401.3-170442.6" + wire $2\alu_op__imm_data__ok$5$next[0:0]$9438 + attribute \src "libresoc.v:170401.3-170442.6" + wire $2\alu_op__oe__oe$8$next[0:0]$9439 + attribute \src "libresoc.v:170401.3-170442.6" + wire $2\alu_op__oe__ok$9$next[0:0]$9440 + attribute \src "libresoc.v:170401.3-170442.6" + wire $2\alu_op__rc__ok$7$next[0:0]$9441 + attribute \src "libresoc.v:170401.3-170442.6" + wire $2\alu_op__rc__rc$6$next[0:0]$9442 + attribute \src "libresoc.v:170462.3-170480.6" + wire $2\cr_a_ok$23$next[0:0]$9454 + attribute \src "libresoc.v:170443.3-170461.6" + wire $2\o_ok$21$next[0:0]$9448 + attribute \src "libresoc.v:170370.3-170387.6" + wire $2\r_busy$next[0:0]$9396 + attribute \src "libresoc.v:170481.3-170499.6" + wire $2\xer_ca_ok$25$next[0:0]$9460 + attribute \src "libresoc.v:170500.3-170518.6" + wire $2\xer_ov_ok$27$next[0:0]$9466 + attribute \src "libresoc.v:170519.3-170537.6" + wire $2\xer_so_ok$29$next[0:0]$9472 + attribute \src "libresoc.v:170245.18-170245.118" + wire $and$libresoc.v:170245$9333_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$60 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" @@ -343701,9 +315071,9 @@ module \pipe2 wire \alu_op__zero_a$11$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire \alu_op__zero_a$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 64 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 input 25 \cr_a @@ -343723,7 +315093,7 @@ module \pipe2 wire \cr_a_ok$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$84 - attribute \src "libresoc.v:168065.7-168065.15" + attribute \src "libresoc.v:169373.7-169373.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 4 \muxid @@ -344118,7 +315488,7 @@ module \pipe2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$90 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:168937$9349 + cell $and $and$libresoc.v:170245$9333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -344126,16 +315496,16 @@ module \pipe2 parameter \Y_WIDTH 1 connect \A \p_valid_i$59 connect \B \p_ready_o - connect \Y $and$libresoc.v:168937$9349_Y + connect \Y $and$libresoc.v:170245$9333_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:168998.9-169001.4" + attribute \src "libresoc.v:170306.9-170309.4" cell \n$4 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:169002.12-169057.4" + attribute \src "libresoc.v:170310.12-170365.4" cell \output \output connect \alu_op__data_len \output_alu_op__data_len connect \alu_op__data_len$18 \output_alu_op__data_len$47 @@ -344193,478 +315563,478 @@ module \pipe2 connect \xer_so_ok \output_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:169058.9-169061.4" + attribute \src "libresoc.v:170366.9-170369.4" cell \p$3 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:168065.7-168065.20" - process $proc$libresoc.v:168065$9489 + attribute \src "libresoc.v:169373.7-169373.20" + process $proc$libresoc.v:169373$9473 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:168072.13-168072.41" - process $proc$libresoc.v:168072$9490 + attribute \src "libresoc.v:169380.13-169380.41" + process $proc$libresoc.v:169380$9474 assign { } { } - assign $0\alu_op__data_len$18[3:0]$9491 4'0000 + assign $0\alu_op__data_len$18[3:0]$9475 4'0000 sync always sync init - update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9491 + update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9475 end - attribute \src "libresoc.v:168111.14-168111.44" - process $proc$libresoc.v:168111$9492 + attribute \src "libresoc.v:169419.14-169419.44" + process $proc$libresoc.v:169419$9476 assign { } { } - assign $0\alu_op__fn_unit$3[13:0]$9493 14'00000000000000 + assign $0\alu_op__fn_unit$3[13:0]$9477 14'00000000000000 sync always sync init - update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[13:0]$9493 + update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[13:0]$9477 end - attribute \src "libresoc.v:168135.14-168135.63" - process $proc$libresoc.v:168135$9494 + attribute \src "libresoc.v:169443.14-169443.63" + process $proc$libresoc.v:169443$9478 assign { } { } - assign $0\alu_op__imm_data__data$4[63:0]$9495 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\alu_op__imm_data__data$4[63:0]$9479 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9495 + update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9479 end - attribute \src "libresoc.v:168144.7-168144.38" - process $proc$libresoc.v:168144$9496 + attribute \src "libresoc.v:169452.7-169452.38" + process $proc$libresoc.v:169452$9480 assign { } { } - assign $0\alu_op__imm_data__ok$5[0:0]$9497 1'0 + assign $0\alu_op__imm_data__ok$5[0:0]$9481 1'0 sync always sync init - update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9497 + update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9481 end - attribute \src "libresoc.v:168161.13-168161.44" - process $proc$libresoc.v:168161$9498 + attribute \src "libresoc.v:169469.13-169469.44" + process $proc$libresoc.v:169469$9482 assign { } { } - assign $0\alu_op__input_carry$14[1:0]$9499 2'00 + assign $0\alu_op__input_carry$14[1:0]$9483 2'00 sync always sync init - update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9499 + update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9483 end - attribute \src "libresoc.v:168174.14-168174.39" - process $proc$libresoc.v:168174$9500 + attribute \src "libresoc.v:169482.14-169482.39" + process $proc$libresoc.v:169482$9484 assign { } { } - assign $0\alu_op__insn$19[31:0]$9501 0 + assign $0\alu_op__insn$19[31:0]$9485 0 sync always sync init - update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9501 + update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9485 end - attribute \src "libresoc.v:168333.13-168333.42" - process $proc$libresoc.v:168333$9502 + attribute \src "libresoc.v:169641.13-169641.42" + process $proc$libresoc.v:169641$9486 assign { } { } - assign $0\alu_op__insn_type$2[6:0]$9503 7'0000000 + assign $0\alu_op__insn_type$2[6:0]$9487 7'0000000 sync always sync init - update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9503 + update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9487 end - attribute \src "libresoc.v:168417.7-168417.36" - process $proc$libresoc.v:168417$9504 + attribute \src "libresoc.v:169725.7-169725.36" + process $proc$libresoc.v:169725$9488 assign { } { } - assign $0\alu_op__invert_in$10[0:0]$9505 1'0 + assign $0\alu_op__invert_in$10[0:0]$9489 1'0 sync always sync init - update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9505 + update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9489 end - attribute \src "libresoc.v:168426.7-168426.37" - process $proc$libresoc.v:168426$9506 + attribute \src "libresoc.v:169734.7-169734.37" + process $proc$libresoc.v:169734$9490 assign { } { } - assign $0\alu_op__invert_out$12[0:0]$9507 1'0 + assign $0\alu_op__invert_out$12[0:0]$9491 1'0 sync always sync init - update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9507 + update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9491 end - attribute \src "libresoc.v:168435.7-168435.35" - process $proc$libresoc.v:168435$9508 + attribute \src "libresoc.v:169743.7-169743.35" + process $proc$libresoc.v:169743$9492 assign { } { } - assign $0\alu_op__is_32bit$16[0:0]$9509 1'0 + assign $0\alu_op__is_32bit$16[0:0]$9493 1'0 sync always sync init - update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9509 + update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9493 end - attribute \src "libresoc.v:168444.7-168444.36" - process $proc$libresoc.v:168444$9510 + attribute \src "libresoc.v:169752.7-169752.36" + process $proc$libresoc.v:169752$9494 assign { } { } - assign $0\alu_op__is_signed$17[0:0]$9511 1'0 + assign $0\alu_op__is_signed$17[0:0]$9495 1'0 sync always sync init - update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9511 + update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9495 end - attribute \src "libresoc.v:168455.7-168455.32" - process $proc$libresoc.v:168455$9512 + attribute \src "libresoc.v:169763.7-169763.32" + process $proc$libresoc.v:169763$9496 assign { } { } - assign $0\alu_op__oe__oe$8[0:0]$9513 1'0 + assign $0\alu_op__oe__oe$8[0:0]$9497 1'0 sync always sync init - update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9513 + update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9497 end - attribute \src "libresoc.v:168464.7-168464.32" - process $proc$libresoc.v:168464$9514 + attribute \src "libresoc.v:169772.7-169772.32" + process $proc$libresoc.v:169772$9498 assign { } { } - assign $0\alu_op__oe__ok$9[0:0]$9515 1'0 + assign $0\alu_op__oe__ok$9[0:0]$9499 1'0 sync always sync init - update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9515 + update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9499 end - attribute \src "libresoc.v:168471.7-168471.39" - process $proc$libresoc.v:168471$9516 + attribute \src "libresoc.v:169779.7-169779.39" + process $proc$libresoc.v:169779$9500 assign { } { } - assign $0\alu_op__output_carry$15[0:0]$9517 1'0 + assign $0\alu_op__output_carry$15[0:0]$9501 1'0 sync always sync init - update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9517 + update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9501 end - attribute \src "libresoc.v:168482.7-168482.32" - process $proc$libresoc.v:168482$9518 + attribute \src "libresoc.v:169790.7-169790.32" + process $proc$libresoc.v:169790$9502 assign { } { } - assign $0\alu_op__rc__ok$7[0:0]$9519 1'0 + assign $0\alu_op__rc__ok$7[0:0]$9503 1'0 sync always sync init - update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9519 + update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9503 end - attribute \src "libresoc.v:168489.7-168489.32" - process $proc$libresoc.v:168489$9520 + attribute \src "libresoc.v:169797.7-169797.32" + process $proc$libresoc.v:169797$9504 assign { } { } - assign $0\alu_op__rc__rc$6[0:0]$9521 1'0 + assign $0\alu_op__rc__rc$6[0:0]$9505 1'0 sync always sync init - update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9521 + update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9505 end - attribute \src "libresoc.v:168498.7-168498.36" - process $proc$libresoc.v:168498$9522 + attribute \src "libresoc.v:169806.7-169806.36" + process $proc$libresoc.v:169806$9506 assign { } { } - assign $0\alu_op__write_cr0$13[0:0]$9523 1'0 + assign $0\alu_op__write_cr0$13[0:0]$9507 1'0 sync always sync init - update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9523 + update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9507 end - attribute \src "libresoc.v:168507.7-168507.33" - process $proc$libresoc.v:168507$9524 + attribute \src "libresoc.v:169815.7-169815.33" + process $proc$libresoc.v:169815$9508 assign { } { } - assign $0\alu_op__zero_a$11[0:0]$9525 1'0 + assign $0\alu_op__zero_a$11[0:0]$9509 1'0 sync always sync init - update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9525 + update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9509 end - attribute \src "libresoc.v:168520.13-168520.29" - process $proc$libresoc.v:168520$9526 + attribute \src "libresoc.v:169828.13-169828.29" + process $proc$libresoc.v:169828$9510 assign { } { } - assign $0\cr_a$22[3:0]$9527 4'0000 + assign $0\cr_a$22[3:0]$9511 4'0000 sync always sync init - update \cr_a$22 $0\cr_a$22[3:0]$9527 + update \cr_a$22 $0\cr_a$22[3:0]$9511 end - attribute \src "libresoc.v:168529.7-168529.26" - process $proc$libresoc.v:168529$9528 + attribute \src "libresoc.v:169837.7-169837.26" + process $proc$libresoc.v:169837$9512 assign { } { } - assign $0\cr_a_ok$23[0:0]$9529 1'0 + assign $0\cr_a_ok$23[0:0]$9513 1'0 sync always sync init - update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9529 + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9513 end - attribute \src "libresoc.v:168540.13-168540.29" - process $proc$libresoc.v:168540$9530 + attribute \src "libresoc.v:169848.13-169848.29" + process $proc$libresoc.v:169848$9514 assign { } { } - assign $0\muxid$1[1:0]$9531 2'00 + assign $0\muxid$1[1:0]$9515 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$9531 + update \muxid$1 $0\muxid$1[1:0]$9515 end - attribute \src "libresoc.v:168555.14-168555.43" - process $proc$libresoc.v:168555$9532 + attribute \src "libresoc.v:169863.14-169863.43" + process $proc$libresoc.v:169863$9516 assign { } { } - assign $0\o$20[63:0]$9533 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\o$20[63:0]$9517 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \o$20 $0\o$20[63:0]$9533 + update \o$20 $0\o$20[63:0]$9517 end - attribute \src "libresoc.v:168564.7-168564.23" - process $proc$libresoc.v:168564$9534 + attribute \src "libresoc.v:169872.7-169872.23" + process $proc$libresoc.v:169872$9518 assign { } { } - assign $0\o_ok$21[0:0]$9535 1'0 + assign $0\o_ok$21[0:0]$9519 1'0 sync always sync init - update \o_ok$21 $0\o_ok$21[0:0]$9535 + update \o_ok$21 $0\o_ok$21[0:0]$9519 end - attribute \src "libresoc.v:168874.7-168874.20" - process $proc$libresoc.v:168874$9536 + attribute \src "libresoc.v:170182.7-170182.20" + process $proc$libresoc.v:170182$9520 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:168881.13-168881.31" - process $proc$libresoc.v:168881$9537 + attribute \src "libresoc.v:170189.13-170189.31" + process $proc$libresoc.v:170189$9521 assign { } { } - assign $0\xer_ca$24[1:0]$9538 2'00 + assign $0\xer_ca$24[1:0]$9522 2'00 sync always sync init - update \xer_ca$24 $0\xer_ca$24[1:0]$9538 + update \xer_ca$24 $0\xer_ca$24[1:0]$9522 end - attribute \src "libresoc.v:168890.7-168890.28" - process $proc$libresoc.v:168890$9539 + attribute \src "libresoc.v:170198.7-170198.28" + process $proc$libresoc.v:170198$9523 assign { } { } - assign $0\xer_ca_ok$25[0:0]$9540 1'0 + assign $0\xer_ca_ok$25[0:0]$9524 1'0 sync always sync init - update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9540 + update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9524 end - attribute \src "libresoc.v:168901.13-168901.31" - process $proc$libresoc.v:168901$9541 + attribute \src "libresoc.v:170209.13-170209.31" + process $proc$libresoc.v:170209$9525 assign { } { } - assign $0\xer_ov$26[1:0]$9542 2'00 + assign $0\xer_ov$26[1:0]$9526 2'00 sync always sync init - update \xer_ov$26 $0\xer_ov$26[1:0]$9542 + update \xer_ov$26 $0\xer_ov$26[1:0]$9526 end - attribute \src "libresoc.v:168910.7-168910.28" - process $proc$libresoc.v:168910$9543 + attribute \src "libresoc.v:170218.7-170218.28" + process $proc$libresoc.v:170218$9527 assign { } { } - assign $0\xer_ov_ok$27[0:0]$9544 1'0 + assign $0\xer_ov_ok$27[0:0]$9528 1'0 sync always sync init - update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9544 + update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9528 end - attribute \src "libresoc.v:168921.7-168921.25" - process $proc$libresoc.v:168921$9545 + attribute \src "libresoc.v:170229.7-170229.25" + process $proc$libresoc.v:170229$9529 assign { } { } - assign $0\xer_so$28[0:0]$9546 1'0 + assign $0\xer_so$28[0:0]$9530 1'0 sync always sync init - update \xer_so$28 $0\xer_so$28[0:0]$9546 + update \xer_so$28 $0\xer_so$28[0:0]$9530 end - attribute \src "libresoc.v:168930.7-168930.28" - process $proc$libresoc.v:168930$9547 + attribute \src "libresoc.v:170238.7-170238.28" + process $proc$libresoc.v:170238$9531 assign { } { } - assign $0\xer_so_ok$29[0:0]$9548 1'0 + assign $0\xer_so_ok$29[0:0]$9532 1'0 sync always sync init - update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9548 + update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9532 end - attribute \src "libresoc.v:168938.3-168939.37" - process $proc$libresoc.v:168938$9350 + attribute \src "libresoc.v:170246.3-170247.37" + process $proc$libresoc.v:170246$9334 assign { } { } - assign $0\xer_so$28[0:0]$9351 \xer_so$28$next + assign $0\xer_so$28[0:0]$9335 \xer_so$28$next sync posedge \coresync_clk - update \xer_so$28 $0\xer_so$28[0:0]$9351 + update \xer_so$28 $0\xer_so$28[0:0]$9335 end - attribute \src "libresoc.v:168940.3-168941.43" - process $proc$libresoc.v:168940$9352 + attribute \src "libresoc.v:170248.3-170249.43" + process $proc$libresoc.v:170248$9336 assign { } { } - assign $0\xer_so_ok$29[0:0]$9353 \xer_so_ok$29$next + assign $0\xer_so_ok$29[0:0]$9337 \xer_so_ok$29$next sync posedge \coresync_clk - update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9353 + update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$9337 end - attribute \src "libresoc.v:168942.3-168943.37" - process $proc$libresoc.v:168942$9354 + attribute \src "libresoc.v:170250.3-170251.37" + process $proc$libresoc.v:170250$9338 assign { } { } - assign $0\xer_ov$26[1:0]$9355 \xer_ov$26$next + assign $0\xer_ov$26[1:0]$9339 \xer_ov$26$next sync posedge \coresync_clk - update \xer_ov$26 $0\xer_ov$26[1:0]$9355 + update \xer_ov$26 $0\xer_ov$26[1:0]$9339 end - attribute \src "libresoc.v:168944.3-168945.43" - process $proc$libresoc.v:168944$9356 + attribute \src "libresoc.v:170252.3-170253.43" + process $proc$libresoc.v:170252$9340 assign { } { } - assign $0\xer_ov_ok$27[0:0]$9357 \xer_ov_ok$27$next + assign $0\xer_ov_ok$27[0:0]$9341 \xer_ov_ok$27$next sync posedge \coresync_clk - update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9357 + update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$9341 end - attribute \src "libresoc.v:168946.3-168947.37" - process $proc$libresoc.v:168946$9358 + attribute \src "libresoc.v:170254.3-170255.37" + process $proc$libresoc.v:170254$9342 assign { } { } - assign $0\xer_ca$24[1:0]$9359 \xer_ca$24$next + assign $0\xer_ca$24[1:0]$9343 \xer_ca$24$next sync posedge \coresync_clk - update \xer_ca$24 $0\xer_ca$24[1:0]$9359 + update \xer_ca$24 $0\xer_ca$24[1:0]$9343 end - attribute \src "libresoc.v:168948.3-168949.43" - process $proc$libresoc.v:168948$9360 + attribute \src "libresoc.v:170256.3-170257.43" + process $proc$libresoc.v:170256$9344 assign { } { } - assign $0\xer_ca_ok$25[0:0]$9361 \xer_ca_ok$25$next + assign $0\xer_ca_ok$25[0:0]$9345 \xer_ca_ok$25$next sync posedge \coresync_clk - update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9361 + update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$9345 end - attribute \src "libresoc.v:168950.3-168951.33" - process $proc$libresoc.v:168950$9362 + attribute \src "libresoc.v:170258.3-170259.33" + process $proc$libresoc.v:170258$9346 assign { } { } - assign $0\cr_a$22[3:0]$9363 \cr_a$22$next + assign $0\cr_a$22[3:0]$9347 \cr_a$22$next sync posedge \coresync_clk - update \cr_a$22 $0\cr_a$22[3:0]$9363 + update \cr_a$22 $0\cr_a$22[3:0]$9347 end - attribute \src "libresoc.v:168952.3-168953.39" - process $proc$libresoc.v:168952$9364 + attribute \src "libresoc.v:170260.3-170261.39" + process $proc$libresoc.v:170260$9348 assign { } { } - assign $0\cr_a_ok$23[0:0]$9365 \cr_a_ok$23$next + assign $0\cr_a_ok$23[0:0]$9349 \cr_a_ok$23$next sync posedge \coresync_clk - update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9365 + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$9349 end - attribute \src "libresoc.v:168954.3-168955.27" - process $proc$libresoc.v:168954$9366 + attribute \src "libresoc.v:170262.3-170263.27" + process $proc$libresoc.v:170262$9350 assign { } { } - assign $0\o$20[63:0]$9367 \o$20$next + assign $0\o$20[63:0]$9351 \o$20$next sync posedge \coresync_clk - update \o$20 $0\o$20[63:0]$9367 + update \o$20 $0\o$20[63:0]$9351 end - attribute \src "libresoc.v:168956.3-168957.33" - process $proc$libresoc.v:168956$9368 + attribute \src "libresoc.v:170264.3-170265.33" + process $proc$libresoc.v:170264$9352 assign { } { } - assign $0\o_ok$21[0:0]$9369 \o_ok$21$next + assign $0\o_ok$21[0:0]$9353 \o_ok$21$next sync posedge \coresync_clk - update \o_ok$21 $0\o_ok$21[0:0]$9369 + update \o_ok$21 $0\o_ok$21[0:0]$9353 end - attribute \src "libresoc.v:168958.3-168959.57" - process $proc$libresoc.v:168958$9370 + attribute \src "libresoc.v:170266.3-170267.57" + process $proc$libresoc.v:170266$9354 assign { } { } - assign $0\alu_op__insn_type$2[6:0]$9371 \alu_op__insn_type$2$next + assign $0\alu_op__insn_type$2[6:0]$9355 \alu_op__insn_type$2$next sync posedge \coresync_clk - update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9371 + update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$9355 end - attribute \src "libresoc.v:168960.3-168961.53" - process $proc$libresoc.v:168960$9372 + attribute \src "libresoc.v:170268.3-170269.53" + process $proc$libresoc.v:170268$9356 assign { } { } - assign $0\alu_op__fn_unit$3[13:0]$9373 \alu_op__fn_unit$3$next + assign $0\alu_op__fn_unit$3[13:0]$9357 \alu_op__fn_unit$3$next sync posedge \coresync_clk - update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[13:0]$9373 + update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[13:0]$9357 end - attribute \src "libresoc.v:168962.3-168963.67" - process $proc$libresoc.v:168962$9374 + attribute \src "libresoc.v:170270.3-170271.67" + process $proc$libresoc.v:170270$9358 assign { } { } - assign $0\alu_op__imm_data__data$4[63:0]$9375 \alu_op__imm_data__data$4$next + assign $0\alu_op__imm_data__data$4[63:0]$9359 \alu_op__imm_data__data$4$next sync posedge \coresync_clk - update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9375 + update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$9359 end - attribute \src "libresoc.v:168964.3-168965.63" - process $proc$libresoc.v:168964$9376 + attribute \src "libresoc.v:170272.3-170273.63" + process $proc$libresoc.v:170272$9360 assign { } { } - assign $0\alu_op__imm_data__ok$5[0:0]$9377 \alu_op__imm_data__ok$5$next + assign $0\alu_op__imm_data__ok$5[0:0]$9361 \alu_op__imm_data__ok$5$next sync posedge \coresync_clk - update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9377 + update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$9361 end - attribute \src "libresoc.v:168966.3-168967.51" - process $proc$libresoc.v:168966$9378 + attribute \src "libresoc.v:170274.3-170275.51" + process $proc$libresoc.v:170274$9362 assign { } { } - assign $0\alu_op__rc__rc$6[0:0]$9379 \alu_op__rc__rc$6$next + assign $0\alu_op__rc__rc$6[0:0]$9363 \alu_op__rc__rc$6$next sync posedge \coresync_clk - update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9379 + update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$9363 end - attribute \src "libresoc.v:168968.3-168969.51" - process $proc$libresoc.v:168968$9380 + attribute \src "libresoc.v:170276.3-170277.51" + process $proc$libresoc.v:170276$9364 assign { } { } - assign $0\alu_op__rc__ok$7[0:0]$9381 \alu_op__rc__ok$7$next + assign $0\alu_op__rc__ok$7[0:0]$9365 \alu_op__rc__ok$7$next sync posedge \coresync_clk - update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9381 + update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$9365 end - attribute \src "libresoc.v:168970.3-168971.51" - process $proc$libresoc.v:168970$9382 + attribute \src "libresoc.v:170278.3-170279.51" + process $proc$libresoc.v:170278$9366 assign { } { } - assign $0\alu_op__oe__oe$8[0:0]$9383 \alu_op__oe__oe$8$next + assign $0\alu_op__oe__oe$8[0:0]$9367 \alu_op__oe__oe$8$next sync posedge \coresync_clk - update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9383 + update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$9367 end - attribute \src "libresoc.v:168972.3-168973.51" - process $proc$libresoc.v:168972$9384 + attribute \src "libresoc.v:170280.3-170281.51" + process $proc$libresoc.v:170280$9368 assign { } { } - assign $0\alu_op__oe__ok$9[0:0]$9385 \alu_op__oe__ok$9$next + assign $0\alu_op__oe__ok$9[0:0]$9369 \alu_op__oe__ok$9$next sync posedge \coresync_clk - update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9385 + update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$9369 end - attribute \src "libresoc.v:168974.3-168975.59" - process $proc$libresoc.v:168974$9386 + attribute \src "libresoc.v:170282.3-170283.59" + process $proc$libresoc.v:170282$9370 assign { } { } - assign $0\alu_op__invert_in$10[0:0]$9387 \alu_op__invert_in$10$next + assign $0\alu_op__invert_in$10[0:0]$9371 \alu_op__invert_in$10$next sync posedge \coresync_clk - update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9387 + update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$9371 end - attribute \src "libresoc.v:168976.3-168977.53" - process $proc$libresoc.v:168976$9388 + attribute \src "libresoc.v:170284.3-170285.53" + process $proc$libresoc.v:170284$9372 assign { } { } - assign $0\alu_op__zero_a$11[0:0]$9389 \alu_op__zero_a$11$next + assign $0\alu_op__zero_a$11[0:0]$9373 \alu_op__zero_a$11$next sync posedge \coresync_clk - update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9389 + update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$9373 end - attribute \src "libresoc.v:168978.3-168979.61" - process $proc$libresoc.v:168978$9390 + attribute \src "libresoc.v:170286.3-170287.61" + process $proc$libresoc.v:170286$9374 assign { } { } - assign $0\alu_op__invert_out$12[0:0]$9391 \alu_op__invert_out$12$next + assign $0\alu_op__invert_out$12[0:0]$9375 \alu_op__invert_out$12$next sync posedge \coresync_clk - update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9391 + update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$9375 end - attribute \src "libresoc.v:168980.3-168981.59" - process $proc$libresoc.v:168980$9392 + attribute \src "libresoc.v:170288.3-170289.59" + process $proc$libresoc.v:170288$9376 assign { } { } - assign $0\alu_op__write_cr0$13[0:0]$9393 \alu_op__write_cr0$13$next + assign $0\alu_op__write_cr0$13[0:0]$9377 \alu_op__write_cr0$13$next sync posedge \coresync_clk - update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9393 + update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$9377 end - attribute \src "libresoc.v:168982.3-168983.63" - process $proc$libresoc.v:168982$9394 + attribute \src "libresoc.v:170290.3-170291.63" + process $proc$libresoc.v:170290$9378 assign { } { } - assign $0\alu_op__input_carry$14[1:0]$9395 \alu_op__input_carry$14$next + assign $0\alu_op__input_carry$14[1:0]$9379 \alu_op__input_carry$14$next sync posedge \coresync_clk - update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9395 + update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$9379 end - attribute \src "libresoc.v:168984.3-168985.65" - process $proc$libresoc.v:168984$9396 + attribute \src "libresoc.v:170292.3-170293.65" + process $proc$libresoc.v:170292$9380 assign { } { } - assign $0\alu_op__output_carry$15[0:0]$9397 \alu_op__output_carry$15$next + assign $0\alu_op__output_carry$15[0:0]$9381 \alu_op__output_carry$15$next sync posedge \coresync_clk - update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9397 + update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$9381 end - attribute \src "libresoc.v:168986.3-168987.57" - process $proc$libresoc.v:168986$9398 + attribute \src "libresoc.v:170294.3-170295.57" + process $proc$libresoc.v:170294$9382 assign { } { } - assign $0\alu_op__is_32bit$16[0:0]$9399 \alu_op__is_32bit$16$next + assign $0\alu_op__is_32bit$16[0:0]$9383 \alu_op__is_32bit$16$next sync posedge \coresync_clk - update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9399 + update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$9383 end - attribute \src "libresoc.v:168988.3-168989.59" - process $proc$libresoc.v:168988$9400 + attribute \src "libresoc.v:170296.3-170297.59" + process $proc$libresoc.v:170296$9384 assign { } { } - assign $0\alu_op__is_signed$17[0:0]$9401 \alu_op__is_signed$17$next + assign $0\alu_op__is_signed$17[0:0]$9385 \alu_op__is_signed$17$next sync posedge \coresync_clk - update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9401 + update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$9385 end - attribute \src "libresoc.v:168990.3-168991.57" - process $proc$libresoc.v:168990$9402 + attribute \src "libresoc.v:170298.3-170299.57" + process $proc$libresoc.v:170298$9386 assign { } { } - assign $0\alu_op__data_len$18[3:0]$9403 \alu_op__data_len$18$next + assign $0\alu_op__data_len$18[3:0]$9387 \alu_op__data_len$18$next sync posedge \coresync_clk - update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9403 + update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$9387 end - attribute \src "libresoc.v:168992.3-168993.49" - process $proc$libresoc.v:168992$9404 + attribute \src "libresoc.v:170300.3-170301.49" + process $proc$libresoc.v:170300$9388 assign { } { } - assign $0\alu_op__insn$19[31:0]$9405 \alu_op__insn$19$next + assign $0\alu_op__insn$19[31:0]$9389 \alu_op__insn$19$next sync posedge \coresync_clk - update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9405 + update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$9389 end - attribute \src "libresoc.v:168994.3-168995.33" - process $proc$libresoc.v:168994$9406 + attribute \src "libresoc.v:170302.3-170303.33" + process $proc$libresoc.v:170302$9390 assign { } { } - assign $0\muxid$1[1:0]$9407 \muxid$1$next + assign $0\muxid$1[1:0]$9391 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$9407 + update \muxid$1 $0\muxid$1[1:0]$9391 end - attribute \src "libresoc.v:168996.3-168997.29" - process $proc$libresoc.v:168996$9408 + attribute \src "libresoc.v:170304.3-170305.29" + process $proc$libresoc.v:170304$9392 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:169062.3-169079.6" - process $proc$libresoc.v:169062$9409 + attribute \src "libresoc.v:170370.3-170387.6" + process $proc$libresoc.v:170370$9393 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9410 $2\r_busy$next[0:0]$9412 - attribute \src "libresoc.v:169063.5-169063.29" + assign $0\r_busy$next[0:0]$9394 $2\r_busy$next[0:0]$9396 + attribute \src "libresoc.v:170371.5-170371.29" switch \initial - attribute \src "libresoc.v:169063.9-169063.17" + attribute \src "libresoc.v:170371.9-170371.17" case 1'1 case end @@ -344673,34 +316043,34 @@ module \pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9411 1'1 + assign $1\r_busy$next[0:0]$9395 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9411 1'0 + assign $1\r_busy$next[0:0]$9395 1'0 case - assign $1\r_busy$next[0:0]$9411 \r_busy + assign $1\r_busy$next[0:0]$9395 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9412 1'0 + assign $2\r_busy$next[0:0]$9396 1'0 case - assign $2\r_busy$next[0:0]$9412 $1\r_busy$next[0:0]$9411 + assign $2\r_busy$next[0:0]$9396 $1\r_busy$next[0:0]$9395 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9410 + update \r_busy$next $0\r_busy$next[0:0]$9394 end - attribute \src "libresoc.v:169080.3-169092.6" - process $proc$libresoc.v:169080$9413 + attribute \src "libresoc.v:170388.3-170400.6" + process $proc$libresoc.v:170388$9397 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$9414 $1\muxid$1$next[1:0]$9415 - attribute \src "libresoc.v:169081.5-169081.29" + assign $0\muxid$1$next[1:0]$9398 $1\muxid$1$next[1:0]$9399 + attribute \src "libresoc.v:170389.5-170389.29" switch \initial - attribute \src "libresoc.v:169081.9-169081.17" + attribute \src "libresoc.v:170389.9-170389.17" case 1'1 case end @@ -344709,19 +316079,19 @@ module \pipe2 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$9415 \muxid$62 + assign $1\muxid$1$next[1:0]$9399 \muxid$62 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$9415 \muxid$62 + assign $1\muxid$1$next[1:0]$9399 \muxid$62 case - assign $1\muxid$1$next[1:0]$9415 \muxid$1 + assign $1\muxid$1$next[1:0]$9399 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$9414 + update \muxid$1$next $0\muxid$1$next[1:0]$9398 end - attribute \src "libresoc.v:169093.3-169134.6" - process $proc$libresoc.v:169093$9416 + attribute \src "libresoc.v:170401.3-170442.6" + process $proc$libresoc.v:170401$9400 assign { } { } assign { } { } assign { } { } @@ -344758,33 +316128,33 @@ module \pipe2 assign { } { } assign { } { } assign { } { } - assign $0\alu_op__data_len$18$next[3:0]$9417 $1\alu_op__data_len$18$next[3:0]$9435 - assign $0\alu_op__fn_unit$3$next[13:0]$9418 $1\alu_op__fn_unit$3$next[13:0]$9436 + assign $0\alu_op__data_len$18$next[3:0]$9401 $1\alu_op__data_len$18$next[3:0]$9419 + assign $0\alu_op__fn_unit$3$next[13:0]$9402 $1\alu_op__fn_unit$3$next[13:0]$9420 assign { } { } assign { } { } - assign $0\alu_op__input_carry$14$next[1:0]$9421 $1\alu_op__input_carry$14$next[1:0]$9439 - assign $0\alu_op__insn$19$next[31:0]$9422 $1\alu_op__insn$19$next[31:0]$9440 - assign $0\alu_op__insn_type$2$next[6:0]$9423 $1\alu_op__insn_type$2$next[6:0]$9441 - assign $0\alu_op__invert_in$10$next[0:0]$9424 $1\alu_op__invert_in$10$next[0:0]$9442 - assign $0\alu_op__invert_out$12$next[0:0]$9425 $1\alu_op__invert_out$12$next[0:0]$9443 - assign $0\alu_op__is_32bit$16$next[0:0]$9426 $1\alu_op__is_32bit$16$next[0:0]$9444 - assign $0\alu_op__is_signed$17$next[0:0]$9427 $1\alu_op__is_signed$17$next[0:0]$9445 + assign $0\alu_op__input_carry$14$next[1:0]$9405 $1\alu_op__input_carry$14$next[1:0]$9423 + assign $0\alu_op__insn$19$next[31:0]$9406 $1\alu_op__insn$19$next[31:0]$9424 + assign $0\alu_op__insn_type$2$next[6:0]$9407 $1\alu_op__insn_type$2$next[6:0]$9425 + assign $0\alu_op__invert_in$10$next[0:0]$9408 $1\alu_op__invert_in$10$next[0:0]$9426 + assign $0\alu_op__invert_out$12$next[0:0]$9409 $1\alu_op__invert_out$12$next[0:0]$9427 + assign $0\alu_op__is_32bit$16$next[0:0]$9410 $1\alu_op__is_32bit$16$next[0:0]$9428 + assign $0\alu_op__is_signed$17$next[0:0]$9411 $1\alu_op__is_signed$17$next[0:0]$9429 assign { } { } assign { } { } - assign $0\alu_op__output_carry$15$next[0:0]$9430 $1\alu_op__output_carry$15$next[0:0]$9448 + assign $0\alu_op__output_carry$15$next[0:0]$9414 $1\alu_op__output_carry$15$next[0:0]$9432 assign { } { } assign { } { } - assign $0\alu_op__write_cr0$13$next[0:0]$9433 $1\alu_op__write_cr0$13$next[0:0]$9451 - assign $0\alu_op__zero_a$11$next[0:0]$9434 $1\alu_op__zero_a$11$next[0:0]$9452 - assign $0\alu_op__imm_data__data$4$next[63:0]$9419 $2\alu_op__imm_data__data$4$next[63:0]$9453 - assign $0\alu_op__imm_data__ok$5$next[0:0]$9420 $2\alu_op__imm_data__ok$5$next[0:0]$9454 - assign $0\alu_op__oe__oe$8$next[0:0]$9428 $2\alu_op__oe__oe$8$next[0:0]$9455 - assign $0\alu_op__oe__ok$9$next[0:0]$9429 $2\alu_op__oe__ok$9$next[0:0]$9456 - assign $0\alu_op__rc__ok$7$next[0:0]$9431 $2\alu_op__rc__ok$7$next[0:0]$9457 - assign $0\alu_op__rc__rc$6$next[0:0]$9432 $2\alu_op__rc__rc$6$next[0:0]$9458 - attribute \src "libresoc.v:169094.5-169094.29" + assign $0\alu_op__write_cr0$13$next[0:0]$9417 $1\alu_op__write_cr0$13$next[0:0]$9435 + assign $0\alu_op__zero_a$11$next[0:0]$9418 $1\alu_op__zero_a$11$next[0:0]$9436 + assign $0\alu_op__imm_data__data$4$next[63:0]$9403 $2\alu_op__imm_data__data$4$next[63:0]$9437 + assign $0\alu_op__imm_data__ok$5$next[0:0]$9404 $2\alu_op__imm_data__ok$5$next[0:0]$9438 + assign $0\alu_op__oe__oe$8$next[0:0]$9412 $2\alu_op__oe__oe$8$next[0:0]$9439 + assign $0\alu_op__oe__ok$9$next[0:0]$9413 $2\alu_op__oe__ok$9$next[0:0]$9440 + assign $0\alu_op__rc__ok$7$next[0:0]$9415 $2\alu_op__rc__ok$7$next[0:0]$9441 + assign $0\alu_op__rc__rc$6$next[0:0]$9416 $2\alu_op__rc__rc$6$next[0:0]$9442 + attribute \src "libresoc.v:170402.5-170402.29" switch \initial - attribute \src "libresoc.v:169094.9-169094.17" + attribute \src "libresoc.v:170402.9-170402.17" case 1'1 case end @@ -344810,7 +316180,7 @@ module \pipe2 assign { } { } assign { } { } assign { } { } - assign { $1\alu_op__insn$19$next[31:0]$9440 $1\alu_op__data_len$18$next[3:0]$9435 $1\alu_op__is_signed$17$next[0:0]$9445 $1\alu_op__is_32bit$16$next[0:0]$9444 $1\alu_op__output_carry$15$next[0:0]$9448 $1\alu_op__input_carry$14$next[1:0]$9439 $1\alu_op__write_cr0$13$next[0:0]$9451 $1\alu_op__invert_out$12$next[0:0]$9443 $1\alu_op__zero_a$11$next[0:0]$9452 $1\alu_op__invert_in$10$next[0:0]$9442 $1\alu_op__oe__ok$9$next[0:0]$9447 $1\alu_op__oe__oe$8$next[0:0]$9446 $1\alu_op__rc__ok$7$next[0:0]$9449 $1\alu_op__rc__rc$6$next[0:0]$9450 $1\alu_op__imm_data__ok$5$next[0:0]$9438 $1\alu_op__imm_data__data$4$next[63:0]$9437 $1\alu_op__fn_unit$3$next[13:0]$9436 $1\alu_op__insn_type$2$next[6:0]$9441 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } + assign { $1\alu_op__insn$19$next[31:0]$9424 $1\alu_op__data_len$18$next[3:0]$9419 $1\alu_op__is_signed$17$next[0:0]$9429 $1\alu_op__is_32bit$16$next[0:0]$9428 $1\alu_op__output_carry$15$next[0:0]$9432 $1\alu_op__input_carry$14$next[1:0]$9423 $1\alu_op__write_cr0$13$next[0:0]$9435 $1\alu_op__invert_out$12$next[0:0]$9427 $1\alu_op__zero_a$11$next[0:0]$9436 $1\alu_op__invert_in$10$next[0:0]$9426 $1\alu_op__oe__ok$9$next[0:0]$9431 $1\alu_op__oe__oe$8$next[0:0]$9430 $1\alu_op__rc__ok$7$next[0:0]$9433 $1\alu_op__rc__rc$6$next[0:0]$9434 $1\alu_op__imm_data__ok$5$next[0:0]$9422 $1\alu_op__imm_data__data$4$next[63:0]$9421 $1\alu_op__fn_unit$3$next[13:0]$9420 $1\alu_op__insn_type$2$next[6:0]$9425 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -344831,26 +316201,26 @@ module \pipe2 assign { } { } assign { } { } assign { } { } - assign { $1\alu_op__insn$19$next[31:0]$9440 $1\alu_op__data_len$18$next[3:0]$9435 $1\alu_op__is_signed$17$next[0:0]$9445 $1\alu_op__is_32bit$16$next[0:0]$9444 $1\alu_op__output_carry$15$next[0:0]$9448 $1\alu_op__input_carry$14$next[1:0]$9439 $1\alu_op__write_cr0$13$next[0:0]$9451 $1\alu_op__invert_out$12$next[0:0]$9443 $1\alu_op__zero_a$11$next[0:0]$9452 $1\alu_op__invert_in$10$next[0:0]$9442 $1\alu_op__oe__ok$9$next[0:0]$9447 $1\alu_op__oe__oe$8$next[0:0]$9446 $1\alu_op__rc__ok$7$next[0:0]$9449 $1\alu_op__rc__rc$6$next[0:0]$9450 $1\alu_op__imm_data__ok$5$next[0:0]$9438 $1\alu_op__imm_data__data$4$next[63:0]$9437 $1\alu_op__fn_unit$3$next[13:0]$9436 $1\alu_op__insn_type$2$next[6:0]$9441 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } + assign { $1\alu_op__insn$19$next[31:0]$9424 $1\alu_op__data_len$18$next[3:0]$9419 $1\alu_op__is_signed$17$next[0:0]$9429 $1\alu_op__is_32bit$16$next[0:0]$9428 $1\alu_op__output_carry$15$next[0:0]$9432 $1\alu_op__input_carry$14$next[1:0]$9423 $1\alu_op__write_cr0$13$next[0:0]$9435 $1\alu_op__invert_out$12$next[0:0]$9427 $1\alu_op__zero_a$11$next[0:0]$9436 $1\alu_op__invert_in$10$next[0:0]$9426 $1\alu_op__oe__ok$9$next[0:0]$9431 $1\alu_op__oe__oe$8$next[0:0]$9430 $1\alu_op__rc__ok$7$next[0:0]$9433 $1\alu_op__rc__rc$6$next[0:0]$9434 $1\alu_op__imm_data__ok$5$next[0:0]$9422 $1\alu_op__imm_data__data$4$next[63:0]$9421 $1\alu_op__fn_unit$3$next[13:0]$9420 $1\alu_op__insn_type$2$next[6:0]$9425 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } case - assign $1\alu_op__data_len$18$next[3:0]$9435 \alu_op__data_len$18 - assign $1\alu_op__fn_unit$3$next[13:0]$9436 \alu_op__fn_unit$3 - assign $1\alu_op__imm_data__data$4$next[63:0]$9437 \alu_op__imm_data__data$4 - assign $1\alu_op__imm_data__ok$5$next[0:0]$9438 \alu_op__imm_data__ok$5 - assign $1\alu_op__input_carry$14$next[1:0]$9439 \alu_op__input_carry$14 - assign $1\alu_op__insn$19$next[31:0]$9440 \alu_op__insn$19 - assign $1\alu_op__insn_type$2$next[6:0]$9441 \alu_op__insn_type$2 - assign $1\alu_op__invert_in$10$next[0:0]$9442 \alu_op__invert_in$10 - assign $1\alu_op__invert_out$12$next[0:0]$9443 \alu_op__invert_out$12 - assign $1\alu_op__is_32bit$16$next[0:0]$9444 \alu_op__is_32bit$16 - assign $1\alu_op__is_signed$17$next[0:0]$9445 \alu_op__is_signed$17 - assign $1\alu_op__oe__oe$8$next[0:0]$9446 \alu_op__oe__oe$8 - assign $1\alu_op__oe__ok$9$next[0:0]$9447 \alu_op__oe__ok$9 - assign $1\alu_op__output_carry$15$next[0:0]$9448 \alu_op__output_carry$15 - assign $1\alu_op__rc__ok$7$next[0:0]$9449 \alu_op__rc__ok$7 - assign $1\alu_op__rc__rc$6$next[0:0]$9450 \alu_op__rc__rc$6 - assign $1\alu_op__write_cr0$13$next[0:0]$9451 \alu_op__write_cr0$13 - assign $1\alu_op__zero_a$11$next[0:0]$9452 \alu_op__zero_a$11 + assign $1\alu_op__data_len$18$next[3:0]$9419 \alu_op__data_len$18 + assign $1\alu_op__fn_unit$3$next[13:0]$9420 \alu_op__fn_unit$3 + assign $1\alu_op__imm_data__data$4$next[63:0]$9421 \alu_op__imm_data__data$4 + assign $1\alu_op__imm_data__ok$5$next[0:0]$9422 \alu_op__imm_data__ok$5 + assign $1\alu_op__input_carry$14$next[1:0]$9423 \alu_op__input_carry$14 + assign $1\alu_op__insn$19$next[31:0]$9424 \alu_op__insn$19 + assign $1\alu_op__insn_type$2$next[6:0]$9425 \alu_op__insn_type$2 + assign $1\alu_op__invert_in$10$next[0:0]$9426 \alu_op__invert_in$10 + assign $1\alu_op__invert_out$12$next[0:0]$9427 \alu_op__invert_out$12 + assign $1\alu_op__is_32bit$16$next[0:0]$9428 \alu_op__is_32bit$16 + assign $1\alu_op__is_signed$17$next[0:0]$9429 \alu_op__is_signed$17 + assign $1\alu_op__oe__oe$8$next[0:0]$9430 \alu_op__oe__oe$8 + assign $1\alu_op__oe__ok$9$next[0:0]$9431 \alu_op__oe__ok$9 + assign $1\alu_op__output_carry$15$next[0:0]$9432 \alu_op__output_carry$15 + assign $1\alu_op__rc__ok$7$next[0:0]$9433 \alu_op__rc__ok$7 + assign $1\alu_op__rc__rc$6$next[0:0]$9434 \alu_op__rc__rc$6 + assign $1\alu_op__write_cr0$13$next[0:0]$9435 \alu_op__write_cr0$13 + assign $1\alu_op__zero_a$11$next[0:0]$9436 \alu_op__zero_a$11 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -344862,52 +316232,52 @@ module \pipe2 assign { } { } assign { } { } assign { } { } - assign $2\alu_op__imm_data__data$4$next[63:0]$9453 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_op__imm_data__ok$5$next[0:0]$9454 1'0 - assign $2\alu_op__rc__rc$6$next[0:0]$9458 1'0 - assign $2\alu_op__rc__ok$7$next[0:0]$9457 1'0 - assign $2\alu_op__oe__oe$8$next[0:0]$9455 1'0 - assign $2\alu_op__oe__ok$9$next[0:0]$9456 1'0 + assign $2\alu_op__imm_data__data$4$next[63:0]$9437 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_op__imm_data__ok$5$next[0:0]$9438 1'0 + assign $2\alu_op__rc__rc$6$next[0:0]$9442 1'0 + assign $2\alu_op__rc__ok$7$next[0:0]$9441 1'0 + assign $2\alu_op__oe__oe$8$next[0:0]$9439 1'0 + assign $2\alu_op__oe__ok$9$next[0:0]$9440 1'0 case - assign $2\alu_op__imm_data__data$4$next[63:0]$9453 $1\alu_op__imm_data__data$4$next[63:0]$9437 - assign $2\alu_op__imm_data__ok$5$next[0:0]$9454 $1\alu_op__imm_data__ok$5$next[0:0]$9438 - assign $2\alu_op__oe__oe$8$next[0:0]$9455 $1\alu_op__oe__oe$8$next[0:0]$9446 - assign $2\alu_op__oe__ok$9$next[0:0]$9456 $1\alu_op__oe__ok$9$next[0:0]$9447 - assign $2\alu_op__rc__ok$7$next[0:0]$9457 $1\alu_op__rc__ok$7$next[0:0]$9449 - assign $2\alu_op__rc__rc$6$next[0:0]$9458 $1\alu_op__rc__rc$6$next[0:0]$9450 + assign $2\alu_op__imm_data__data$4$next[63:0]$9437 $1\alu_op__imm_data__data$4$next[63:0]$9421 + assign $2\alu_op__imm_data__ok$5$next[0:0]$9438 $1\alu_op__imm_data__ok$5$next[0:0]$9422 + assign $2\alu_op__oe__oe$8$next[0:0]$9439 $1\alu_op__oe__oe$8$next[0:0]$9430 + assign $2\alu_op__oe__ok$9$next[0:0]$9440 $1\alu_op__oe__ok$9$next[0:0]$9431 + assign $2\alu_op__rc__ok$7$next[0:0]$9441 $1\alu_op__rc__ok$7$next[0:0]$9433 + assign $2\alu_op__rc__rc$6$next[0:0]$9442 $1\alu_op__rc__rc$6$next[0:0]$9434 end sync always - update \alu_op__data_len$18$next $0\alu_op__data_len$18$next[3:0]$9417 - update \alu_op__fn_unit$3$next $0\alu_op__fn_unit$3$next[13:0]$9418 - update \alu_op__imm_data__data$4$next $0\alu_op__imm_data__data$4$next[63:0]$9419 - update \alu_op__imm_data__ok$5$next $0\alu_op__imm_data__ok$5$next[0:0]$9420 - update \alu_op__input_carry$14$next $0\alu_op__input_carry$14$next[1:0]$9421 - update \alu_op__insn$19$next $0\alu_op__insn$19$next[31:0]$9422 - update \alu_op__insn_type$2$next $0\alu_op__insn_type$2$next[6:0]$9423 - update \alu_op__invert_in$10$next $0\alu_op__invert_in$10$next[0:0]$9424 - update \alu_op__invert_out$12$next $0\alu_op__invert_out$12$next[0:0]$9425 - update \alu_op__is_32bit$16$next $0\alu_op__is_32bit$16$next[0:0]$9426 - update \alu_op__is_signed$17$next $0\alu_op__is_signed$17$next[0:0]$9427 - update \alu_op__oe__oe$8$next $0\alu_op__oe__oe$8$next[0:0]$9428 - update \alu_op__oe__ok$9$next $0\alu_op__oe__ok$9$next[0:0]$9429 - update \alu_op__output_carry$15$next $0\alu_op__output_carry$15$next[0:0]$9430 - update \alu_op__rc__ok$7$next $0\alu_op__rc__ok$7$next[0:0]$9431 - update \alu_op__rc__rc$6$next $0\alu_op__rc__rc$6$next[0:0]$9432 - update \alu_op__write_cr0$13$next $0\alu_op__write_cr0$13$next[0:0]$9433 - update \alu_op__zero_a$11$next $0\alu_op__zero_a$11$next[0:0]$9434 + update \alu_op__data_len$18$next $0\alu_op__data_len$18$next[3:0]$9401 + update \alu_op__fn_unit$3$next $0\alu_op__fn_unit$3$next[13:0]$9402 + update \alu_op__imm_data__data$4$next $0\alu_op__imm_data__data$4$next[63:0]$9403 + update \alu_op__imm_data__ok$5$next $0\alu_op__imm_data__ok$5$next[0:0]$9404 + update \alu_op__input_carry$14$next $0\alu_op__input_carry$14$next[1:0]$9405 + update \alu_op__insn$19$next $0\alu_op__insn$19$next[31:0]$9406 + update \alu_op__insn_type$2$next $0\alu_op__insn_type$2$next[6:0]$9407 + update \alu_op__invert_in$10$next $0\alu_op__invert_in$10$next[0:0]$9408 + update \alu_op__invert_out$12$next $0\alu_op__invert_out$12$next[0:0]$9409 + update \alu_op__is_32bit$16$next $0\alu_op__is_32bit$16$next[0:0]$9410 + update \alu_op__is_signed$17$next $0\alu_op__is_signed$17$next[0:0]$9411 + update \alu_op__oe__oe$8$next $0\alu_op__oe__oe$8$next[0:0]$9412 + update \alu_op__oe__ok$9$next $0\alu_op__oe__ok$9$next[0:0]$9413 + update \alu_op__output_carry$15$next $0\alu_op__output_carry$15$next[0:0]$9414 + update \alu_op__rc__ok$7$next $0\alu_op__rc__ok$7$next[0:0]$9415 + update \alu_op__rc__rc$6$next $0\alu_op__rc__rc$6$next[0:0]$9416 + update \alu_op__write_cr0$13$next $0\alu_op__write_cr0$13$next[0:0]$9417 + update \alu_op__zero_a$11$next $0\alu_op__zero_a$11$next[0:0]$9418 end - attribute \src "libresoc.v:169135.3-169153.6" - process $proc$libresoc.v:169135$9459 + attribute \src "libresoc.v:170443.3-170461.6" + process $proc$libresoc.v:170443$9443 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$20$next[63:0]$9460 $1\o$20$next[63:0]$9462 + assign $0\o$20$next[63:0]$9444 $1\o$20$next[63:0]$9446 assign { } { } - assign $0\o_ok$21$next[0:0]$9461 $2\o_ok$21$next[0:0]$9464 - attribute \src "libresoc.v:169136.5-169136.29" + assign $0\o_ok$21$next[0:0]$9445 $2\o_ok$21$next[0:0]$9448 + attribute \src "libresoc.v:170444.5-170444.29" switch \initial - attribute \src "libresoc.v:169136.9-169136.17" + attribute \src "libresoc.v:170444.9-170444.17" case 1'1 case end @@ -344917,41 +316287,41 @@ module \pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$21$next[0:0]$9463 $1\o$20$next[63:0]$9462 } { \o_ok$82 \o$81 } + assign { $1\o_ok$21$next[0:0]$9447 $1\o$20$next[63:0]$9446 } { \o_ok$82 \o$81 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$21$next[0:0]$9463 $1\o$20$next[63:0]$9462 } { \o_ok$82 \o$81 } + assign { $1\o_ok$21$next[0:0]$9447 $1\o$20$next[63:0]$9446 } { \o_ok$82 \o$81 } case - assign $1\o$20$next[63:0]$9462 \o$20 - assign $1\o_ok$21$next[0:0]$9463 \o_ok$21 + assign $1\o$20$next[63:0]$9446 \o$20 + assign $1\o_ok$21$next[0:0]$9447 \o_ok$21 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$21$next[0:0]$9464 1'0 + assign $2\o_ok$21$next[0:0]$9448 1'0 case - assign $2\o_ok$21$next[0:0]$9464 $1\o_ok$21$next[0:0]$9463 + assign $2\o_ok$21$next[0:0]$9448 $1\o_ok$21$next[0:0]$9447 end sync always - update \o$20$next $0\o$20$next[63:0]$9460 - update \o_ok$21$next $0\o_ok$21$next[0:0]$9461 + update \o$20$next $0\o$20$next[63:0]$9444 + update \o_ok$21$next $0\o_ok$21$next[0:0]$9445 end - attribute \src "libresoc.v:169154.3-169172.6" - process $proc$libresoc.v:169154$9465 + attribute \src "libresoc.v:170462.3-170480.6" + process $proc$libresoc.v:170462$9449 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$22$next[3:0]$9466 $1\cr_a$22$next[3:0]$9468 + assign $0\cr_a$22$next[3:0]$9450 $1\cr_a$22$next[3:0]$9452 assign { } { } - assign $0\cr_a_ok$23$next[0:0]$9467 $2\cr_a_ok$23$next[0:0]$9470 - attribute \src "libresoc.v:169155.5-169155.29" + assign $0\cr_a_ok$23$next[0:0]$9451 $2\cr_a_ok$23$next[0:0]$9454 + attribute \src "libresoc.v:170463.5-170463.29" switch \initial - attribute \src "libresoc.v:169155.9-169155.17" + attribute \src "libresoc.v:170463.9-170463.17" case 1'1 case end @@ -344961,41 +316331,41 @@ module \pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$23$next[0:0]$9469 $1\cr_a$22$next[3:0]$9468 } { \cr_a_ok$84 \cr_a$83 } + assign { $1\cr_a_ok$23$next[0:0]$9453 $1\cr_a$22$next[3:0]$9452 } { \cr_a_ok$84 \cr_a$83 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$23$next[0:0]$9469 $1\cr_a$22$next[3:0]$9468 } { \cr_a_ok$84 \cr_a$83 } + assign { $1\cr_a_ok$23$next[0:0]$9453 $1\cr_a$22$next[3:0]$9452 } { \cr_a_ok$84 \cr_a$83 } case - assign $1\cr_a$22$next[3:0]$9468 \cr_a$22 - assign $1\cr_a_ok$23$next[0:0]$9469 \cr_a_ok$23 + assign $1\cr_a$22$next[3:0]$9452 \cr_a$22 + assign $1\cr_a_ok$23$next[0:0]$9453 \cr_a_ok$23 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$23$next[0:0]$9470 1'0 + assign $2\cr_a_ok$23$next[0:0]$9454 1'0 case - assign $2\cr_a_ok$23$next[0:0]$9470 $1\cr_a_ok$23$next[0:0]$9469 + assign $2\cr_a_ok$23$next[0:0]$9454 $1\cr_a_ok$23$next[0:0]$9453 end sync always - update \cr_a$22$next $0\cr_a$22$next[3:0]$9466 - update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$9467 + update \cr_a$22$next $0\cr_a$22$next[3:0]$9450 + update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$9451 end - attribute \src "libresoc.v:169173.3-169191.6" - process $proc$libresoc.v:169173$9471 + attribute \src "libresoc.v:170481.3-170499.6" + process $proc$libresoc.v:170481$9455 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ca$24$next[1:0]$9472 $1\xer_ca$24$next[1:0]$9474 + assign $0\xer_ca$24$next[1:0]$9456 $1\xer_ca$24$next[1:0]$9458 assign { } { } - assign $0\xer_ca_ok$25$next[0:0]$9473 $2\xer_ca_ok$25$next[0:0]$9476 - attribute \src "libresoc.v:169174.5-169174.29" + assign $0\xer_ca_ok$25$next[0:0]$9457 $2\xer_ca_ok$25$next[0:0]$9460 + attribute \src "libresoc.v:170482.5-170482.29" switch \initial - attribute \src "libresoc.v:169174.9-169174.17" + attribute \src "libresoc.v:170482.9-170482.17" case 1'1 case end @@ -345005,41 +316375,41 @@ module \pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ca_ok$25$next[0:0]$9475 $1\xer_ca$24$next[1:0]$9474 } { \xer_ca_ok$86 \xer_ca$85 } + assign { $1\xer_ca_ok$25$next[0:0]$9459 $1\xer_ca$24$next[1:0]$9458 } { \xer_ca_ok$86 \xer_ca$85 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ca_ok$25$next[0:0]$9475 $1\xer_ca$24$next[1:0]$9474 } { \xer_ca_ok$86 \xer_ca$85 } + assign { $1\xer_ca_ok$25$next[0:0]$9459 $1\xer_ca$24$next[1:0]$9458 } { \xer_ca_ok$86 \xer_ca$85 } case - assign $1\xer_ca$24$next[1:0]$9474 \xer_ca$24 - assign $1\xer_ca_ok$25$next[0:0]$9475 \xer_ca_ok$25 + assign $1\xer_ca$24$next[1:0]$9458 \xer_ca$24 + assign $1\xer_ca_ok$25$next[0:0]$9459 \xer_ca_ok$25 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ca_ok$25$next[0:0]$9476 1'0 + assign $2\xer_ca_ok$25$next[0:0]$9460 1'0 case - assign $2\xer_ca_ok$25$next[0:0]$9476 $1\xer_ca_ok$25$next[0:0]$9475 + assign $2\xer_ca_ok$25$next[0:0]$9460 $1\xer_ca_ok$25$next[0:0]$9459 end sync always - update \xer_ca$24$next $0\xer_ca$24$next[1:0]$9472 - update \xer_ca_ok$25$next $0\xer_ca_ok$25$next[0:0]$9473 + update \xer_ca$24$next $0\xer_ca$24$next[1:0]$9456 + update \xer_ca_ok$25$next $0\xer_ca_ok$25$next[0:0]$9457 end - attribute \src "libresoc.v:169192.3-169210.6" - process $proc$libresoc.v:169192$9477 + attribute \src "libresoc.v:170500.3-170518.6" + process $proc$libresoc.v:170500$9461 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ov$26$next[1:0]$9478 $1\xer_ov$26$next[1:0]$9480 + assign $0\xer_ov$26$next[1:0]$9462 $1\xer_ov$26$next[1:0]$9464 assign { } { } - assign $0\xer_ov_ok$27$next[0:0]$9479 $2\xer_ov_ok$27$next[0:0]$9482 - attribute \src "libresoc.v:169193.5-169193.29" + assign $0\xer_ov_ok$27$next[0:0]$9463 $2\xer_ov_ok$27$next[0:0]$9466 + attribute \src "libresoc.v:170501.5-170501.29" switch \initial - attribute \src "libresoc.v:169193.9-169193.17" + attribute \src "libresoc.v:170501.9-170501.17" case 1'1 case end @@ -345049,41 +316419,41 @@ module \pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ov_ok$27$next[0:0]$9481 $1\xer_ov$26$next[1:0]$9480 } { \xer_ov_ok$88 \xer_ov$87 } + assign { $1\xer_ov_ok$27$next[0:0]$9465 $1\xer_ov$26$next[1:0]$9464 } { \xer_ov_ok$88 \xer_ov$87 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ov_ok$27$next[0:0]$9481 $1\xer_ov$26$next[1:0]$9480 } { \xer_ov_ok$88 \xer_ov$87 } + assign { $1\xer_ov_ok$27$next[0:0]$9465 $1\xer_ov$26$next[1:0]$9464 } { \xer_ov_ok$88 \xer_ov$87 } case - assign $1\xer_ov$26$next[1:0]$9480 \xer_ov$26 - assign $1\xer_ov_ok$27$next[0:0]$9481 \xer_ov_ok$27 + assign $1\xer_ov$26$next[1:0]$9464 \xer_ov$26 + assign $1\xer_ov_ok$27$next[0:0]$9465 \xer_ov_ok$27 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ov_ok$27$next[0:0]$9482 1'0 + assign $2\xer_ov_ok$27$next[0:0]$9466 1'0 case - assign $2\xer_ov_ok$27$next[0:0]$9482 $1\xer_ov_ok$27$next[0:0]$9481 + assign $2\xer_ov_ok$27$next[0:0]$9466 $1\xer_ov_ok$27$next[0:0]$9465 end sync always - update \xer_ov$26$next $0\xer_ov$26$next[1:0]$9478 - update \xer_ov_ok$27$next $0\xer_ov_ok$27$next[0:0]$9479 + update \xer_ov$26$next $0\xer_ov$26$next[1:0]$9462 + update \xer_ov_ok$27$next $0\xer_ov_ok$27$next[0:0]$9463 end - attribute \src "libresoc.v:169211.3-169229.6" - process $proc$libresoc.v:169211$9483 + attribute \src "libresoc.v:170519.3-170537.6" + process $proc$libresoc.v:170519$9467 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$28$next[0:0]$9484 $1\xer_so$28$next[0:0]$9486 + assign $0\xer_so$28$next[0:0]$9468 $1\xer_so$28$next[0:0]$9470 assign { } { } - assign $0\xer_so_ok$29$next[0:0]$9485 $2\xer_so_ok$29$next[0:0]$9488 - attribute \src "libresoc.v:169212.5-169212.29" + assign $0\xer_so_ok$29$next[0:0]$9469 $2\xer_so_ok$29$next[0:0]$9472 + attribute \src "libresoc.v:170520.5-170520.29" switch \initial - attribute \src "libresoc.v:169212.9-169212.17" + attribute \src "libresoc.v:170520.9-170520.17" case 1'1 case end @@ -345093,30 +316463,30 @@ module \pipe2 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$29$next[0:0]$9487 $1\xer_so$28$next[0:0]$9486 } { \xer_so_ok$90 \xer_so$89 } + assign { $1\xer_so_ok$29$next[0:0]$9471 $1\xer_so$28$next[0:0]$9470 } { \xer_so_ok$90 \xer_so$89 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$29$next[0:0]$9487 $1\xer_so$28$next[0:0]$9486 } { \xer_so_ok$90 \xer_so$89 } + assign { $1\xer_so_ok$29$next[0:0]$9471 $1\xer_so$28$next[0:0]$9470 } { \xer_so_ok$90 \xer_so$89 } case - assign $1\xer_so$28$next[0:0]$9486 \xer_so$28 - assign $1\xer_so_ok$29$next[0:0]$9487 \xer_so_ok$29 + assign $1\xer_so$28$next[0:0]$9470 \xer_so$28 + assign $1\xer_so_ok$29$next[0:0]$9471 \xer_so_ok$29 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$29$next[0:0]$9488 1'0 + assign $2\xer_so_ok$29$next[0:0]$9472 1'0 case - assign $2\xer_so_ok$29$next[0:0]$9488 $1\xer_so_ok$29$next[0:0]$9487 + assign $2\xer_so_ok$29$next[0:0]$9472 $1\xer_so_ok$29$next[0:0]$9471 end sync always - update \xer_so$28$next $0\xer_so$28$next[0:0]$9484 - update \xer_so_ok$29$next $0\xer_so_ok$29$next[0:0]$9485 + update \xer_so$28$next $0\xer_so$28$next[0:0]$9468 + update \xer_so_ok$29$next $0\xer_so_ok$29$next[0:0]$9469 end - connect \$60 $and$libresoc.v:168937$9349_Y + connect \$60 $and$libresoc.v:170245$9333_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \xer_so_ok$90 \xer_so$89 } { \output_xer_so_ok \output_xer_so$54 } @@ -345137,240 +316507,240 @@ module \pipe2 connect { \output_alu_op__insn \output_alu_op__data_len \output_alu_op__is_signed \output_alu_op__is_32bit \output_alu_op__output_carry \output_alu_op__input_carry \output_alu_op__write_cr0 \output_alu_op__invert_out \output_alu_op__zero_a \output_alu_op__invert_in \output_alu_op__oe__ok \output_alu_op__oe__oe \output_alu_op__rc__ok \output_alu_op__rc__rc \output_alu_op__imm_data__ok \output_alu_op__imm_data__data \output_alu_op__fn_unit \output_alu_op__insn_type } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } connect \output_muxid \muxid end -attribute \src "libresoc.v:169253.1-170322.10" +attribute \src "libresoc.v:170561.1-171630.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe2" attribute \generator "nMigen" module \pipe2$115 - attribute \src "libresoc.v:170268.3-170286.6" - wire width 4 $0\cr_a$21$next[3:0]$9654 - attribute \src "libresoc.v:170074.3-170075.33" - wire width 4 $0\cr_a$21[3:0]$9555 - attribute \src "libresoc.v:169265.13-169265.29" - wire width 4 $0\cr_a$21[3:0]$9667 - attribute \src "libresoc.v:170268.3-170286.6" - wire $0\cr_a_ok$22$next[0:0]$9655 - attribute \src "libresoc.v:170076.3-170077.39" - wire $0\cr_a_ok$22[0:0]$9557 - attribute \src "libresoc.v:169274.7-169274.26" - wire $0\cr_a_ok$22[0:0]$9669 - attribute \src "libresoc.v:169254.7-169254.20" + attribute \src "libresoc.v:171576.3-171594.6" + wire width 4 $0\cr_a$21$next[3:0]$9638 + attribute \src "libresoc.v:171382.3-171383.33" + wire width 4 $0\cr_a$21[3:0]$9539 + attribute \src "libresoc.v:170573.13-170573.29" + wire width 4 $0\cr_a$21[3:0]$9651 + attribute \src "libresoc.v:171576.3-171594.6" + wire $0\cr_a_ok$22$next[0:0]$9639 + attribute \src "libresoc.v:171384.3-171385.39" + wire $0\cr_a_ok$22[0:0]$9541 + attribute \src "libresoc.v:170582.7-170582.26" + wire $0\cr_a_ok$22[0:0]$9653 + attribute \src "libresoc.v:170562.7-170562.20" wire $0\initial[0:0] - attribute \src "libresoc.v:170195.3-170207.6" - wire width 2 $0\muxid$1$next[1:0]$9604 - attribute \src "libresoc.v:170116.3-170117.33" - wire width 2 $0\muxid$1[1:0]$9597 - attribute \src "libresoc.v:169285.13-169285.29" - wire width 2 $0\muxid$1[1:0]$9671 - attribute \src "libresoc.v:170249.3-170267.6" - wire width 64 $0\o$19$next[63:0]$9648 - attribute \src "libresoc.v:170078.3-170079.27" - wire width 64 $0\o$19[63:0]$9559 - attribute \src "libresoc.v:169300.14-169300.43" - wire width 64 $0\o$19[63:0]$9673 - attribute \src "libresoc.v:170249.3-170267.6" - wire $0\o_ok$20$next[0:0]$9649 - attribute \src "libresoc.v:170080.3-170081.33" - wire $0\o_ok$20[0:0]$9561 - attribute \src "libresoc.v:169309.7-169309.23" - wire $0\o_ok$20[0:0]$9675 - attribute \src "libresoc.v:170177.3-170194.6" - wire $0\r_busy$next[0:0]$9600 - attribute \src "libresoc.v:170118.3-170119.29" + attribute \src "libresoc.v:171503.3-171515.6" + wire width 2 $0\muxid$1$next[1:0]$9588 + attribute \src "libresoc.v:171424.3-171425.33" + wire width 2 $0\muxid$1[1:0]$9581 + attribute \src "libresoc.v:170593.13-170593.29" + wire width 2 $0\muxid$1[1:0]$9655 + attribute \src "libresoc.v:171557.3-171575.6" + wire width 64 $0\o$19$next[63:0]$9632 + attribute \src "libresoc.v:171386.3-171387.27" + wire width 64 $0\o$19[63:0]$9543 + attribute \src "libresoc.v:170608.14-170608.43" + wire width 64 $0\o$19[63:0]$9657 + attribute \src "libresoc.v:171557.3-171575.6" + wire $0\o_ok$20$next[0:0]$9633 + attribute \src "libresoc.v:171388.3-171389.33" + wire $0\o_ok$20[0:0]$9545 + attribute \src "libresoc.v:170617.7-170617.23" + wire $0\o_ok$20[0:0]$9659 + attribute \src "libresoc.v:171485.3-171502.6" + wire $0\r_busy$next[0:0]$9584 + attribute \src "libresoc.v:171426.3-171427.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:170208.3-170248.6" - wire width 14 $0\sr_op__fn_unit$3$next[13:0]$9607 - attribute \src "libresoc.v:170084.3-170085.51" - wire width 14 $0\sr_op__fn_unit$3[13:0]$9565 - attribute \src "libresoc.v:169642.14-169642.43" - wire width 14 $0\sr_op__fn_unit$3[13:0]$9678 - attribute \src "libresoc.v:170208.3-170248.6" - wire width 64 $0\sr_op__imm_data__data$4$next[63:0]$9608 - attribute \src "libresoc.v:170086.3-170087.65" - wire width 64 $0\sr_op__imm_data__data$4[63:0]$9567 - attribute \src "libresoc.v:169666.14-169666.62" - wire width 64 $0\sr_op__imm_data__data$4[63:0]$9680 - attribute \src "libresoc.v:170208.3-170248.6" - wire $0\sr_op__imm_data__ok$5$next[0:0]$9609 - attribute \src "libresoc.v:170088.3-170089.61" - wire $0\sr_op__imm_data__ok$5[0:0]$9569 - attribute \src "libresoc.v:169675.7-169675.37" - wire $0\sr_op__imm_data__ok$5[0:0]$9682 - attribute \src "libresoc.v:170208.3-170248.6" - wire width 2 $0\sr_op__input_carry$12$next[1:0]$9610 - attribute \src "libresoc.v:170102.3-170103.61" - wire width 2 $0\sr_op__input_carry$12[1:0]$9583 - attribute \src "libresoc.v:169692.13-169692.43" - wire width 2 $0\sr_op__input_carry$12[1:0]$9684 - attribute \src "libresoc.v:170208.3-170248.6" - wire $0\sr_op__input_cr$14$next[0:0]$9611 - attribute \src "libresoc.v:170106.3-170107.55" - wire $0\sr_op__input_cr$14[0:0]$9587 - attribute \src "libresoc.v:169705.7-169705.34" - wire $0\sr_op__input_cr$14[0:0]$9686 - attribute \src "libresoc.v:170208.3-170248.6" - wire width 32 $0\sr_op__insn$18$next[31:0]$9612 - attribute \src "libresoc.v:170114.3-170115.47" - wire width 32 $0\sr_op__insn$18[31:0]$9595 - attribute \src "libresoc.v:169714.14-169714.38" - wire width 32 $0\sr_op__insn$18[31:0]$9688 - attribute \src "libresoc.v:170208.3-170248.6" - wire width 7 $0\sr_op__insn_type$2$next[6:0]$9613 - attribute \src "libresoc.v:170082.3-170083.55" - wire width 7 $0\sr_op__insn_type$2[6:0]$9563 - attribute \src "libresoc.v:169873.13-169873.41" - wire width 7 $0\sr_op__insn_type$2[6:0]$9690 - attribute \src "libresoc.v:170208.3-170248.6" - wire $0\sr_op__invert_in$11$next[0:0]$9614 - attribute \src "libresoc.v:170100.3-170101.57" - wire $0\sr_op__invert_in$11[0:0]$9581 - attribute \src "libresoc.v:169957.7-169957.35" - wire $0\sr_op__invert_in$11[0:0]$9692 - attribute \src "libresoc.v:170208.3-170248.6" - wire $0\sr_op__is_32bit$16$next[0:0]$9615 - attribute \src "libresoc.v:170110.3-170111.55" - wire $0\sr_op__is_32bit$16[0:0]$9591 - attribute \src "libresoc.v:169966.7-169966.34" - wire $0\sr_op__is_32bit$16[0:0]$9694 - attribute \src "libresoc.v:170208.3-170248.6" - wire $0\sr_op__is_signed$17$next[0:0]$9616 - attribute \src "libresoc.v:170112.3-170113.57" - wire $0\sr_op__is_signed$17[0:0]$9593 - attribute \src "libresoc.v:169975.7-169975.35" - wire $0\sr_op__is_signed$17[0:0]$9696 - attribute \src "libresoc.v:170208.3-170248.6" - wire $0\sr_op__oe__oe$8$next[0:0]$9617 - attribute \src "libresoc.v:170094.3-170095.49" - wire $0\sr_op__oe__oe$8[0:0]$9575 - attribute \src "libresoc.v:169986.7-169986.31" - wire $0\sr_op__oe__oe$8[0:0]$9698 - attribute \src "libresoc.v:170208.3-170248.6" - wire $0\sr_op__oe__ok$9$next[0:0]$9618 - attribute \src "libresoc.v:170096.3-170097.49" - wire $0\sr_op__oe__ok$9[0:0]$9577 - attribute \src "libresoc.v:169995.7-169995.31" - wire $0\sr_op__oe__ok$9[0:0]$9700 - attribute \src "libresoc.v:170208.3-170248.6" - wire $0\sr_op__output_carry$13$next[0:0]$9619 - attribute \src "libresoc.v:170104.3-170105.63" - wire $0\sr_op__output_carry$13[0:0]$9585 - attribute \src "libresoc.v:170002.7-170002.38" - wire $0\sr_op__output_carry$13[0:0]$9702 - attribute \src "libresoc.v:170208.3-170248.6" - wire $0\sr_op__output_cr$15$next[0:0]$9620 - attribute \src "libresoc.v:170108.3-170109.57" - wire $0\sr_op__output_cr$15[0:0]$9589 - attribute \src "libresoc.v:170011.7-170011.35" - wire $0\sr_op__output_cr$15[0:0]$9704 - attribute \src "libresoc.v:170208.3-170248.6" - wire $0\sr_op__rc__ok$7$next[0:0]$9621 - attribute \src "libresoc.v:170092.3-170093.49" - wire $0\sr_op__rc__ok$7[0:0]$9573 - attribute \src "libresoc.v:170022.7-170022.31" - wire $0\sr_op__rc__ok$7[0:0]$9706 - attribute \src "libresoc.v:170208.3-170248.6" - wire $0\sr_op__rc__rc$6$next[0:0]$9622 - attribute \src "libresoc.v:170090.3-170091.49" - wire $0\sr_op__rc__rc$6[0:0]$9571 - attribute \src "libresoc.v:170031.7-170031.31" - wire $0\sr_op__rc__rc$6[0:0]$9708 - attribute \src "libresoc.v:170208.3-170248.6" - wire $0\sr_op__write_cr0$10$next[0:0]$9623 - attribute \src "libresoc.v:170098.3-170099.57" - wire $0\sr_op__write_cr0$10[0:0]$9579 - attribute \src "libresoc.v:170038.7-170038.35" - wire $0\sr_op__write_cr0$10[0:0]$9710 - attribute \src "libresoc.v:170287.3-170305.6" - wire width 2 $0\xer_ca$23$next[1:0]$9660 - attribute \src "libresoc.v:170070.3-170071.37" - wire width 2 $0\xer_ca$23[1:0]$9551 - attribute \src "libresoc.v:170047.13-170047.31" - wire width 2 $0\xer_ca$23[1:0]$9712 - attribute \src "libresoc.v:170287.3-170305.6" - wire $0\xer_ca_ok$24$next[0:0]$9661 - attribute \src "libresoc.v:170072.3-170073.43" - wire $0\xer_ca_ok$24[0:0]$9553 - attribute \src "libresoc.v:170056.7-170056.28" - wire $0\xer_ca_ok$24[0:0]$9714 - attribute \src "libresoc.v:170268.3-170286.6" - wire width 4 $1\cr_a$21$next[3:0]$9656 - attribute \src "libresoc.v:170268.3-170286.6" - wire $1\cr_a_ok$22$next[0:0]$9657 - attribute \src "libresoc.v:170195.3-170207.6" - wire width 2 $1\muxid$1$next[1:0]$9605 - attribute \src "libresoc.v:170249.3-170267.6" - wire width 64 $1\o$19$next[63:0]$9650 - attribute \src "libresoc.v:170249.3-170267.6" - wire $1\o_ok$20$next[0:0]$9651 - attribute \src "libresoc.v:170177.3-170194.6" - wire $1\r_busy$next[0:0]$9601 - attribute \src "libresoc.v:169605.7-169605.20" + attribute \src "libresoc.v:171516.3-171556.6" + wire width 14 $0\sr_op__fn_unit$3$next[13:0]$9591 + attribute \src "libresoc.v:171392.3-171393.51" + wire width 14 $0\sr_op__fn_unit$3[13:0]$9549 + attribute \src "libresoc.v:170950.14-170950.43" + wire width 14 $0\sr_op__fn_unit$3[13:0]$9662 + attribute \src "libresoc.v:171516.3-171556.6" + wire width 64 $0\sr_op__imm_data__data$4$next[63:0]$9592 + attribute \src "libresoc.v:171394.3-171395.65" + wire width 64 $0\sr_op__imm_data__data$4[63:0]$9551 + attribute \src "libresoc.v:170974.14-170974.62" + wire width 64 $0\sr_op__imm_data__data$4[63:0]$9664 + attribute \src "libresoc.v:171516.3-171556.6" + wire $0\sr_op__imm_data__ok$5$next[0:0]$9593 + attribute \src "libresoc.v:171396.3-171397.61" + wire $0\sr_op__imm_data__ok$5[0:0]$9553 + attribute \src "libresoc.v:170983.7-170983.37" + wire $0\sr_op__imm_data__ok$5[0:0]$9666 + attribute \src "libresoc.v:171516.3-171556.6" + wire width 2 $0\sr_op__input_carry$12$next[1:0]$9594 + attribute \src "libresoc.v:171410.3-171411.61" + wire width 2 $0\sr_op__input_carry$12[1:0]$9567 + attribute \src "libresoc.v:171000.13-171000.43" + wire width 2 $0\sr_op__input_carry$12[1:0]$9668 + attribute \src "libresoc.v:171516.3-171556.6" + wire $0\sr_op__input_cr$14$next[0:0]$9595 + attribute \src "libresoc.v:171414.3-171415.55" + wire $0\sr_op__input_cr$14[0:0]$9571 + attribute \src "libresoc.v:171013.7-171013.34" + wire $0\sr_op__input_cr$14[0:0]$9670 + attribute \src "libresoc.v:171516.3-171556.6" + wire width 32 $0\sr_op__insn$18$next[31:0]$9596 + attribute \src "libresoc.v:171422.3-171423.47" + wire width 32 $0\sr_op__insn$18[31:0]$9579 + attribute \src "libresoc.v:171022.14-171022.38" + wire width 32 $0\sr_op__insn$18[31:0]$9672 + attribute \src "libresoc.v:171516.3-171556.6" + wire width 7 $0\sr_op__insn_type$2$next[6:0]$9597 + attribute \src "libresoc.v:171390.3-171391.55" + wire width 7 $0\sr_op__insn_type$2[6:0]$9547 + attribute \src "libresoc.v:171181.13-171181.41" + wire width 7 $0\sr_op__insn_type$2[6:0]$9674 + attribute \src "libresoc.v:171516.3-171556.6" + wire $0\sr_op__invert_in$11$next[0:0]$9598 + attribute \src "libresoc.v:171408.3-171409.57" + wire $0\sr_op__invert_in$11[0:0]$9565 + attribute \src "libresoc.v:171265.7-171265.35" + wire $0\sr_op__invert_in$11[0:0]$9676 + attribute \src "libresoc.v:171516.3-171556.6" + wire $0\sr_op__is_32bit$16$next[0:0]$9599 + attribute \src "libresoc.v:171418.3-171419.55" + wire $0\sr_op__is_32bit$16[0:0]$9575 + attribute \src "libresoc.v:171274.7-171274.34" + wire $0\sr_op__is_32bit$16[0:0]$9678 + attribute \src "libresoc.v:171516.3-171556.6" + wire $0\sr_op__is_signed$17$next[0:0]$9600 + attribute \src "libresoc.v:171420.3-171421.57" + wire $0\sr_op__is_signed$17[0:0]$9577 + attribute \src "libresoc.v:171283.7-171283.35" + wire $0\sr_op__is_signed$17[0:0]$9680 + attribute \src "libresoc.v:171516.3-171556.6" + wire $0\sr_op__oe__oe$8$next[0:0]$9601 + attribute \src "libresoc.v:171402.3-171403.49" + wire $0\sr_op__oe__oe$8[0:0]$9559 + attribute \src "libresoc.v:171294.7-171294.31" + wire $0\sr_op__oe__oe$8[0:0]$9682 + attribute \src "libresoc.v:171516.3-171556.6" + wire $0\sr_op__oe__ok$9$next[0:0]$9602 + attribute \src "libresoc.v:171404.3-171405.49" + wire $0\sr_op__oe__ok$9[0:0]$9561 + attribute \src "libresoc.v:171303.7-171303.31" + wire $0\sr_op__oe__ok$9[0:0]$9684 + attribute \src "libresoc.v:171516.3-171556.6" + wire $0\sr_op__output_carry$13$next[0:0]$9603 + attribute \src "libresoc.v:171412.3-171413.63" + wire $0\sr_op__output_carry$13[0:0]$9569 + attribute \src "libresoc.v:171310.7-171310.38" + wire $0\sr_op__output_carry$13[0:0]$9686 + attribute \src "libresoc.v:171516.3-171556.6" + wire $0\sr_op__output_cr$15$next[0:0]$9604 + attribute \src "libresoc.v:171416.3-171417.57" + wire $0\sr_op__output_cr$15[0:0]$9573 + attribute \src "libresoc.v:171319.7-171319.35" + wire $0\sr_op__output_cr$15[0:0]$9688 + attribute \src "libresoc.v:171516.3-171556.6" + wire $0\sr_op__rc__ok$7$next[0:0]$9605 + attribute \src "libresoc.v:171400.3-171401.49" + wire $0\sr_op__rc__ok$7[0:0]$9557 + attribute \src "libresoc.v:171330.7-171330.31" + wire $0\sr_op__rc__ok$7[0:0]$9690 + attribute \src "libresoc.v:171516.3-171556.6" + wire $0\sr_op__rc__rc$6$next[0:0]$9606 + attribute \src "libresoc.v:171398.3-171399.49" + wire $0\sr_op__rc__rc$6[0:0]$9555 + attribute \src "libresoc.v:171339.7-171339.31" + wire $0\sr_op__rc__rc$6[0:0]$9692 + attribute \src "libresoc.v:171516.3-171556.6" + wire $0\sr_op__write_cr0$10$next[0:0]$9607 + attribute \src "libresoc.v:171406.3-171407.57" + wire $0\sr_op__write_cr0$10[0:0]$9563 + attribute \src "libresoc.v:171346.7-171346.35" + wire $0\sr_op__write_cr0$10[0:0]$9694 + attribute \src "libresoc.v:171595.3-171613.6" + wire width 2 $0\xer_ca$23$next[1:0]$9644 + attribute \src "libresoc.v:171378.3-171379.37" + wire width 2 $0\xer_ca$23[1:0]$9535 + attribute \src "libresoc.v:171355.13-171355.31" + wire width 2 $0\xer_ca$23[1:0]$9696 + attribute \src "libresoc.v:171595.3-171613.6" + wire $0\xer_ca_ok$24$next[0:0]$9645 + attribute \src "libresoc.v:171380.3-171381.43" + wire $0\xer_ca_ok$24[0:0]$9537 + attribute \src "libresoc.v:171364.7-171364.28" + wire $0\xer_ca_ok$24[0:0]$9698 + attribute \src "libresoc.v:171576.3-171594.6" + wire width 4 $1\cr_a$21$next[3:0]$9640 + attribute \src "libresoc.v:171576.3-171594.6" + wire $1\cr_a_ok$22$next[0:0]$9641 + attribute \src "libresoc.v:171503.3-171515.6" + wire width 2 $1\muxid$1$next[1:0]$9589 + attribute \src "libresoc.v:171557.3-171575.6" + wire width 64 $1\o$19$next[63:0]$9634 + attribute \src "libresoc.v:171557.3-171575.6" + wire $1\o_ok$20$next[0:0]$9635 + attribute \src "libresoc.v:171485.3-171502.6" + wire $1\r_busy$next[0:0]$9585 + attribute \src "libresoc.v:170913.7-170913.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:170208.3-170248.6" - wire width 14 $1\sr_op__fn_unit$3$next[13:0]$9624 - attribute \src "libresoc.v:170208.3-170248.6" - wire width 64 $1\sr_op__imm_data__data$4$next[63:0]$9625 - attribute \src "libresoc.v:170208.3-170248.6" - wire $1\sr_op__imm_data__ok$5$next[0:0]$9626 - attribute \src "libresoc.v:170208.3-170248.6" - wire width 2 $1\sr_op__input_carry$12$next[1:0]$9627 - attribute \src "libresoc.v:170208.3-170248.6" - wire $1\sr_op__input_cr$14$next[0:0]$9628 - attribute \src "libresoc.v:170208.3-170248.6" - wire width 32 $1\sr_op__insn$18$next[31:0]$9629 - attribute \src "libresoc.v:170208.3-170248.6" - wire width 7 $1\sr_op__insn_type$2$next[6:0]$9630 - attribute \src "libresoc.v:170208.3-170248.6" - wire $1\sr_op__invert_in$11$next[0:0]$9631 - attribute \src "libresoc.v:170208.3-170248.6" - wire $1\sr_op__is_32bit$16$next[0:0]$9632 - attribute \src "libresoc.v:170208.3-170248.6" - wire $1\sr_op__is_signed$17$next[0:0]$9633 - attribute \src "libresoc.v:170208.3-170248.6" - wire $1\sr_op__oe__oe$8$next[0:0]$9634 - attribute \src "libresoc.v:170208.3-170248.6" - wire $1\sr_op__oe__ok$9$next[0:0]$9635 - attribute \src "libresoc.v:170208.3-170248.6" - wire $1\sr_op__output_carry$13$next[0:0]$9636 - attribute \src "libresoc.v:170208.3-170248.6" - wire $1\sr_op__output_cr$15$next[0:0]$9637 - attribute \src "libresoc.v:170208.3-170248.6" - wire $1\sr_op__rc__ok$7$next[0:0]$9638 - attribute \src "libresoc.v:170208.3-170248.6" - wire $1\sr_op__rc__rc$6$next[0:0]$9639 - attribute \src "libresoc.v:170208.3-170248.6" - wire $1\sr_op__write_cr0$10$next[0:0]$9640 - attribute \src "libresoc.v:170287.3-170305.6" - wire width 2 $1\xer_ca$23$next[1:0]$9662 - attribute \src "libresoc.v:170287.3-170305.6" - wire $1\xer_ca_ok$24$next[0:0]$9663 - attribute \src "libresoc.v:170268.3-170286.6" - wire $2\cr_a_ok$22$next[0:0]$9658 - attribute \src "libresoc.v:170249.3-170267.6" - wire $2\o_ok$20$next[0:0]$9652 - attribute \src "libresoc.v:170177.3-170194.6" - wire $2\r_busy$next[0:0]$9602 - attribute \src "libresoc.v:170208.3-170248.6" - wire width 64 $2\sr_op__imm_data__data$4$next[63:0]$9641 - attribute \src "libresoc.v:170208.3-170248.6" - wire $2\sr_op__imm_data__ok$5$next[0:0]$9642 - attribute \src "libresoc.v:170208.3-170248.6" - wire $2\sr_op__oe__oe$8$next[0:0]$9643 - attribute \src "libresoc.v:170208.3-170248.6" - wire $2\sr_op__oe__ok$9$next[0:0]$9644 - attribute \src "libresoc.v:170208.3-170248.6" - wire $2\sr_op__rc__ok$7$next[0:0]$9645 - attribute \src "libresoc.v:170208.3-170248.6" - wire $2\sr_op__rc__rc$6$next[0:0]$9646 - attribute \src "libresoc.v:170287.3-170305.6" - wire $2\xer_ca_ok$24$next[0:0]$9664 - attribute \src "libresoc.v:170069.18-170069.118" - wire $and$libresoc.v:170069$9549_Y + attribute \src "libresoc.v:171516.3-171556.6" + wire width 14 $1\sr_op__fn_unit$3$next[13:0]$9608 + attribute \src "libresoc.v:171516.3-171556.6" + wire width 64 $1\sr_op__imm_data__data$4$next[63:0]$9609 + attribute \src "libresoc.v:171516.3-171556.6" + wire $1\sr_op__imm_data__ok$5$next[0:0]$9610 + attribute \src "libresoc.v:171516.3-171556.6" + wire width 2 $1\sr_op__input_carry$12$next[1:0]$9611 + attribute \src "libresoc.v:171516.3-171556.6" + wire $1\sr_op__input_cr$14$next[0:0]$9612 + attribute \src "libresoc.v:171516.3-171556.6" + wire width 32 $1\sr_op__insn$18$next[31:0]$9613 + attribute \src "libresoc.v:171516.3-171556.6" + wire width 7 $1\sr_op__insn_type$2$next[6:0]$9614 + attribute \src "libresoc.v:171516.3-171556.6" + wire $1\sr_op__invert_in$11$next[0:0]$9615 + attribute \src "libresoc.v:171516.3-171556.6" + wire $1\sr_op__is_32bit$16$next[0:0]$9616 + attribute \src "libresoc.v:171516.3-171556.6" + wire $1\sr_op__is_signed$17$next[0:0]$9617 + attribute \src "libresoc.v:171516.3-171556.6" + wire $1\sr_op__oe__oe$8$next[0:0]$9618 + attribute \src "libresoc.v:171516.3-171556.6" + wire $1\sr_op__oe__ok$9$next[0:0]$9619 + attribute \src "libresoc.v:171516.3-171556.6" + wire $1\sr_op__output_carry$13$next[0:0]$9620 + attribute \src "libresoc.v:171516.3-171556.6" + wire $1\sr_op__output_cr$15$next[0:0]$9621 + attribute \src "libresoc.v:171516.3-171556.6" + wire $1\sr_op__rc__ok$7$next[0:0]$9622 + attribute \src "libresoc.v:171516.3-171556.6" + wire $1\sr_op__rc__rc$6$next[0:0]$9623 + attribute \src "libresoc.v:171516.3-171556.6" + wire $1\sr_op__write_cr0$10$next[0:0]$9624 + attribute \src "libresoc.v:171595.3-171613.6" + wire width 2 $1\xer_ca$23$next[1:0]$9646 + attribute \src "libresoc.v:171595.3-171613.6" + wire $1\xer_ca_ok$24$next[0:0]$9647 + attribute \src "libresoc.v:171576.3-171594.6" + wire $2\cr_a_ok$22$next[0:0]$9642 + attribute \src "libresoc.v:171557.3-171575.6" + wire $2\o_ok$20$next[0:0]$9636 + attribute \src "libresoc.v:171485.3-171502.6" + wire $2\r_busy$next[0:0]$9586 + attribute \src "libresoc.v:171516.3-171556.6" + wire width 64 $2\sr_op__imm_data__data$4$next[63:0]$9625 + attribute \src "libresoc.v:171516.3-171556.6" + wire $2\sr_op__imm_data__ok$5$next[0:0]$9626 + attribute \src "libresoc.v:171516.3-171556.6" + wire $2\sr_op__oe__oe$8$next[0:0]$9627 + attribute \src "libresoc.v:171516.3-171556.6" + wire $2\sr_op__oe__ok$9$next[0:0]$9628 + attribute \src "libresoc.v:171516.3-171556.6" + wire $2\sr_op__rc__ok$7$next[0:0]$9629 + attribute \src "libresoc.v:171516.3-171556.6" + wire $2\sr_op__rc__rc$6$next[0:0]$9630 + attribute \src "libresoc.v:171595.3-171613.6" + wire $2\xer_ca_ok$24$next[0:0]$9648 + attribute \src "libresoc.v:171377.18-171377.118" + wire $and$libresoc.v:171377$9533_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 56 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 input 24 \cr_a @@ -345390,7 +316760,7 @@ module \pipe2$115 wire \cr_a_ok$47 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \cr_a_ok$74 - attribute \src "libresoc.v:169254.7-169254.15" + attribute \src "libresoc.v:170562.7-170562.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 4 \muxid @@ -346159,7 +317529,7 @@ module \pipe2$115 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$48 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:170069$9549 + cell $and $and$libresoc.v:171377$9533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -346167,16 +317537,16 @@ module \pipe2$115 parameter \Y_WIDTH 1 connect \A \p_valid_i$50 connect \B \p_ready_o - connect \Y $and$libresoc.v:170069$9549_Y + connect \Y $and$libresoc.v:171377$9533_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:170120.11-170123.4" + attribute \src "libresoc.v:171428.11-171431.4" cell \n$117 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:170124.16-170172.4" + attribute \src "libresoc.v:171432.16-171480.4" cell \output$118 \output connect \cr_a \output_cr_a connect \cr_a$21 \output_cr_a$45 @@ -346227,403 +317597,403 @@ module \pipe2$115 connect \xer_so \output_xer_so end attribute \module_not_derived 1 - attribute \src "libresoc.v:170173.11-170176.4" + attribute \src "libresoc.v:171481.11-171484.4" cell \p$116 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:169254.7-169254.20" - process $proc$libresoc.v:169254$9665 + attribute \src "libresoc.v:170562.7-170562.20" + process $proc$libresoc.v:170562$9649 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:169265.13-169265.29" - process $proc$libresoc.v:169265$9666 + attribute \src "libresoc.v:170573.13-170573.29" + process $proc$libresoc.v:170573$9650 assign { } { } - assign $0\cr_a$21[3:0]$9667 4'0000 + assign $0\cr_a$21[3:0]$9651 4'0000 sync always sync init - update \cr_a$21 $0\cr_a$21[3:0]$9667 + update \cr_a$21 $0\cr_a$21[3:0]$9651 end - attribute \src "libresoc.v:169274.7-169274.26" - process $proc$libresoc.v:169274$9668 + attribute \src "libresoc.v:170582.7-170582.26" + process $proc$libresoc.v:170582$9652 assign { } { } - assign $0\cr_a_ok$22[0:0]$9669 1'0 + assign $0\cr_a_ok$22[0:0]$9653 1'0 sync always sync init - update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9669 + update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9653 end - attribute \src "libresoc.v:169285.13-169285.29" - process $proc$libresoc.v:169285$9670 + attribute \src "libresoc.v:170593.13-170593.29" + process $proc$libresoc.v:170593$9654 assign { } { } - assign $0\muxid$1[1:0]$9671 2'00 + assign $0\muxid$1[1:0]$9655 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$9671 + update \muxid$1 $0\muxid$1[1:0]$9655 end - attribute \src "libresoc.v:169300.14-169300.43" - process $proc$libresoc.v:169300$9672 + attribute \src "libresoc.v:170608.14-170608.43" + process $proc$libresoc.v:170608$9656 assign { } { } - assign $0\o$19[63:0]$9673 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\o$19[63:0]$9657 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \o$19 $0\o$19[63:0]$9673 + update \o$19 $0\o$19[63:0]$9657 end - attribute \src "libresoc.v:169309.7-169309.23" - process $proc$libresoc.v:169309$9674 + attribute \src "libresoc.v:170617.7-170617.23" + process $proc$libresoc.v:170617$9658 assign { } { } - assign $0\o_ok$20[0:0]$9675 1'0 + assign $0\o_ok$20[0:0]$9659 1'0 sync always sync init - update \o_ok$20 $0\o_ok$20[0:0]$9675 + update \o_ok$20 $0\o_ok$20[0:0]$9659 end - attribute \src "libresoc.v:169605.7-169605.20" - process $proc$libresoc.v:169605$9676 + attribute \src "libresoc.v:170913.7-170913.20" + process $proc$libresoc.v:170913$9660 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:169642.14-169642.43" - process $proc$libresoc.v:169642$9677 + attribute \src "libresoc.v:170950.14-170950.43" + process $proc$libresoc.v:170950$9661 assign { } { } - assign $0\sr_op__fn_unit$3[13:0]$9678 14'00000000000000 + assign $0\sr_op__fn_unit$3[13:0]$9662 14'00000000000000 sync always sync init - update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[13:0]$9678 + update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[13:0]$9662 end - attribute \src "libresoc.v:169666.14-169666.62" - process $proc$libresoc.v:169666$9679 + attribute \src "libresoc.v:170974.14-170974.62" + process $proc$libresoc.v:170974$9663 assign { } { } - assign $0\sr_op__imm_data__data$4[63:0]$9680 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\sr_op__imm_data__data$4[63:0]$9664 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9680 + update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9664 end - attribute \src "libresoc.v:169675.7-169675.37" - process $proc$libresoc.v:169675$9681 + attribute \src "libresoc.v:170983.7-170983.37" + process $proc$libresoc.v:170983$9665 assign { } { } - assign $0\sr_op__imm_data__ok$5[0:0]$9682 1'0 + assign $0\sr_op__imm_data__ok$5[0:0]$9666 1'0 sync always sync init - update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9682 + update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9666 end - attribute \src "libresoc.v:169692.13-169692.43" - process $proc$libresoc.v:169692$9683 + attribute \src "libresoc.v:171000.13-171000.43" + process $proc$libresoc.v:171000$9667 assign { } { } - assign $0\sr_op__input_carry$12[1:0]$9684 2'00 + assign $0\sr_op__input_carry$12[1:0]$9668 2'00 sync always sync init - update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9684 + update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9668 end - attribute \src "libresoc.v:169705.7-169705.34" - process $proc$libresoc.v:169705$9685 + attribute \src "libresoc.v:171013.7-171013.34" + process $proc$libresoc.v:171013$9669 assign { } { } - assign $0\sr_op__input_cr$14[0:0]$9686 1'0 + assign $0\sr_op__input_cr$14[0:0]$9670 1'0 sync always sync init - update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9686 + update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9670 end - attribute \src "libresoc.v:169714.14-169714.38" - process $proc$libresoc.v:169714$9687 + attribute \src "libresoc.v:171022.14-171022.38" + process $proc$libresoc.v:171022$9671 assign { } { } - assign $0\sr_op__insn$18[31:0]$9688 0 + assign $0\sr_op__insn$18[31:0]$9672 0 sync always sync init - update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9688 + update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9672 end - attribute \src "libresoc.v:169873.13-169873.41" - process $proc$libresoc.v:169873$9689 + attribute \src "libresoc.v:171181.13-171181.41" + process $proc$libresoc.v:171181$9673 assign { } { } - assign $0\sr_op__insn_type$2[6:0]$9690 7'0000000 + assign $0\sr_op__insn_type$2[6:0]$9674 7'0000000 sync always sync init - update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9690 + update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9674 end - attribute \src "libresoc.v:169957.7-169957.35" - process $proc$libresoc.v:169957$9691 + attribute \src "libresoc.v:171265.7-171265.35" + process $proc$libresoc.v:171265$9675 assign { } { } - assign $0\sr_op__invert_in$11[0:0]$9692 1'0 + assign $0\sr_op__invert_in$11[0:0]$9676 1'0 sync always sync init - update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9692 + update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9676 end - attribute \src "libresoc.v:169966.7-169966.34" - process $proc$libresoc.v:169966$9693 + attribute \src "libresoc.v:171274.7-171274.34" + process $proc$libresoc.v:171274$9677 assign { } { } - assign $0\sr_op__is_32bit$16[0:0]$9694 1'0 + assign $0\sr_op__is_32bit$16[0:0]$9678 1'0 sync always sync init - update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9694 + update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9678 end - attribute \src "libresoc.v:169975.7-169975.35" - process $proc$libresoc.v:169975$9695 + attribute \src "libresoc.v:171283.7-171283.35" + process $proc$libresoc.v:171283$9679 assign { } { } - assign $0\sr_op__is_signed$17[0:0]$9696 1'0 + assign $0\sr_op__is_signed$17[0:0]$9680 1'0 sync always sync init - update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9696 + update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9680 end - attribute \src "libresoc.v:169986.7-169986.31" - process $proc$libresoc.v:169986$9697 + attribute \src "libresoc.v:171294.7-171294.31" + process $proc$libresoc.v:171294$9681 assign { } { } - assign $0\sr_op__oe__oe$8[0:0]$9698 1'0 + assign $0\sr_op__oe__oe$8[0:0]$9682 1'0 sync always sync init - update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9698 + update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9682 end - attribute \src "libresoc.v:169995.7-169995.31" - process $proc$libresoc.v:169995$9699 + attribute \src "libresoc.v:171303.7-171303.31" + process $proc$libresoc.v:171303$9683 assign { } { } - assign $0\sr_op__oe__ok$9[0:0]$9700 1'0 + assign $0\sr_op__oe__ok$9[0:0]$9684 1'0 sync always sync init - update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9700 + update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9684 end - attribute \src "libresoc.v:170002.7-170002.38" - process $proc$libresoc.v:170002$9701 + attribute \src "libresoc.v:171310.7-171310.38" + process $proc$libresoc.v:171310$9685 assign { } { } - assign $0\sr_op__output_carry$13[0:0]$9702 1'0 + assign $0\sr_op__output_carry$13[0:0]$9686 1'0 sync always sync init - update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9702 + update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9686 end - attribute \src "libresoc.v:170011.7-170011.35" - process $proc$libresoc.v:170011$9703 + attribute \src "libresoc.v:171319.7-171319.35" + process $proc$libresoc.v:171319$9687 assign { } { } - assign $0\sr_op__output_cr$15[0:0]$9704 1'0 + assign $0\sr_op__output_cr$15[0:0]$9688 1'0 sync always sync init - update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9704 + update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9688 end - attribute \src "libresoc.v:170022.7-170022.31" - process $proc$libresoc.v:170022$9705 + attribute \src "libresoc.v:171330.7-171330.31" + process $proc$libresoc.v:171330$9689 assign { } { } - assign $0\sr_op__rc__ok$7[0:0]$9706 1'0 + assign $0\sr_op__rc__ok$7[0:0]$9690 1'0 sync always sync init - update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9706 + update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9690 end - attribute \src "libresoc.v:170031.7-170031.31" - process $proc$libresoc.v:170031$9707 + attribute \src "libresoc.v:171339.7-171339.31" + process $proc$libresoc.v:171339$9691 assign { } { } - assign $0\sr_op__rc__rc$6[0:0]$9708 1'0 + assign $0\sr_op__rc__rc$6[0:0]$9692 1'0 sync always sync init - update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9708 + update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9692 end - attribute \src "libresoc.v:170038.7-170038.35" - process $proc$libresoc.v:170038$9709 + attribute \src "libresoc.v:171346.7-171346.35" + process $proc$libresoc.v:171346$9693 assign { } { } - assign $0\sr_op__write_cr0$10[0:0]$9710 1'0 + assign $0\sr_op__write_cr0$10[0:0]$9694 1'0 sync always sync init - update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9710 + update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9694 end - attribute \src "libresoc.v:170047.13-170047.31" - process $proc$libresoc.v:170047$9711 + attribute \src "libresoc.v:171355.13-171355.31" + process $proc$libresoc.v:171355$9695 assign { } { } - assign $0\xer_ca$23[1:0]$9712 2'00 + assign $0\xer_ca$23[1:0]$9696 2'00 sync always sync init - update \xer_ca$23 $0\xer_ca$23[1:0]$9712 + update \xer_ca$23 $0\xer_ca$23[1:0]$9696 end - attribute \src "libresoc.v:170056.7-170056.28" - process $proc$libresoc.v:170056$9713 + attribute \src "libresoc.v:171364.7-171364.28" + process $proc$libresoc.v:171364$9697 assign { } { } - assign $0\xer_ca_ok$24[0:0]$9714 1'0 + assign $0\xer_ca_ok$24[0:0]$9698 1'0 sync always sync init - update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9714 + update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9698 end - attribute \src "libresoc.v:170070.3-170071.37" - process $proc$libresoc.v:170070$9550 + attribute \src "libresoc.v:171378.3-171379.37" + process $proc$libresoc.v:171378$9534 assign { } { } - assign $0\xer_ca$23[1:0]$9551 \xer_ca$23$next + assign $0\xer_ca$23[1:0]$9535 \xer_ca$23$next sync posedge \coresync_clk - update \xer_ca$23 $0\xer_ca$23[1:0]$9551 + update \xer_ca$23 $0\xer_ca$23[1:0]$9535 end - attribute \src "libresoc.v:170072.3-170073.43" - process $proc$libresoc.v:170072$9552 + attribute \src "libresoc.v:171380.3-171381.43" + process $proc$libresoc.v:171380$9536 assign { } { } - assign $0\xer_ca_ok$24[0:0]$9553 \xer_ca_ok$24$next + assign $0\xer_ca_ok$24[0:0]$9537 \xer_ca_ok$24$next sync posedge \coresync_clk - update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9553 + update \xer_ca_ok$24 $0\xer_ca_ok$24[0:0]$9537 end - attribute \src "libresoc.v:170074.3-170075.33" - process $proc$libresoc.v:170074$9554 + attribute \src "libresoc.v:171382.3-171383.33" + process $proc$libresoc.v:171382$9538 assign { } { } - assign $0\cr_a$21[3:0]$9555 \cr_a$21$next + assign $0\cr_a$21[3:0]$9539 \cr_a$21$next sync posedge \coresync_clk - update \cr_a$21 $0\cr_a$21[3:0]$9555 + update \cr_a$21 $0\cr_a$21[3:0]$9539 end - attribute \src "libresoc.v:170076.3-170077.39" - process $proc$libresoc.v:170076$9556 + attribute \src "libresoc.v:171384.3-171385.39" + process $proc$libresoc.v:171384$9540 assign { } { } - assign $0\cr_a_ok$22[0:0]$9557 \cr_a_ok$22$next + assign $0\cr_a_ok$22[0:0]$9541 \cr_a_ok$22$next sync posedge \coresync_clk - update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9557 + update \cr_a_ok$22 $0\cr_a_ok$22[0:0]$9541 end - attribute \src "libresoc.v:170078.3-170079.27" - process $proc$libresoc.v:170078$9558 + attribute \src "libresoc.v:171386.3-171387.27" + process $proc$libresoc.v:171386$9542 assign { } { } - assign $0\o$19[63:0]$9559 \o$19$next + assign $0\o$19[63:0]$9543 \o$19$next sync posedge \coresync_clk - update \o$19 $0\o$19[63:0]$9559 + update \o$19 $0\o$19[63:0]$9543 end - attribute \src "libresoc.v:170080.3-170081.33" - process $proc$libresoc.v:170080$9560 + attribute \src "libresoc.v:171388.3-171389.33" + process $proc$libresoc.v:171388$9544 assign { } { } - assign $0\o_ok$20[0:0]$9561 \o_ok$20$next + assign $0\o_ok$20[0:0]$9545 \o_ok$20$next sync posedge \coresync_clk - update \o_ok$20 $0\o_ok$20[0:0]$9561 + update \o_ok$20 $0\o_ok$20[0:0]$9545 end - attribute \src "libresoc.v:170082.3-170083.55" - process $proc$libresoc.v:170082$9562 + attribute \src "libresoc.v:171390.3-171391.55" + process $proc$libresoc.v:171390$9546 assign { } { } - assign $0\sr_op__insn_type$2[6:0]$9563 \sr_op__insn_type$2$next + assign $0\sr_op__insn_type$2[6:0]$9547 \sr_op__insn_type$2$next sync posedge \coresync_clk - update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9563 + update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$9547 end - attribute \src "libresoc.v:170084.3-170085.51" - process $proc$libresoc.v:170084$9564 + attribute \src "libresoc.v:171392.3-171393.51" + process $proc$libresoc.v:171392$9548 assign { } { } - assign $0\sr_op__fn_unit$3[13:0]$9565 \sr_op__fn_unit$3$next + assign $0\sr_op__fn_unit$3[13:0]$9549 \sr_op__fn_unit$3$next sync posedge \coresync_clk - update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[13:0]$9565 + update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[13:0]$9549 end - attribute \src "libresoc.v:170086.3-170087.65" - process $proc$libresoc.v:170086$9566 + attribute \src "libresoc.v:171394.3-171395.65" + process $proc$libresoc.v:171394$9550 assign { } { } - assign $0\sr_op__imm_data__data$4[63:0]$9567 \sr_op__imm_data__data$4$next + assign $0\sr_op__imm_data__data$4[63:0]$9551 \sr_op__imm_data__data$4$next sync posedge \coresync_clk - update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9567 + update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$9551 end - attribute \src "libresoc.v:170088.3-170089.61" - process $proc$libresoc.v:170088$9568 + attribute \src "libresoc.v:171396.3-171397.61" + process $proc$libresoc.v:171396$9552 assign { } { } - assign $0\sr_op__imm_data__ok$5[0:0]$9569 \sr_op__imm_data__ok$5$next + assign $0\sr_op__imm_data__ok$5[0:0]$9553 \sr_op__imm_data__ok$5$next sync posedge \coresync_clk - update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9569 + update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$9553 end - attribute \src "libresoc.v:170090.3-170091.49" - process $proc$libresoc.v:170090$9570 + attribute \src "libresoc.v:171398.3-171399.49" + process $proc$libresoc.v:171398$9554 assign { } { } - assign $0\sr_op__rc__rc$6[0:0]$9571 \sr_op__rc__rc$6$next + assign $0\sr_op__rc__rc$6[0:0]$9555 \sr_op__rc__rc$6$next sync posedge \coresync_clk - update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9571 + update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$9555 end - attribute \src "libresoc.v:170092.3-170093.49" - process $proc$libresoc.v:170092$9572 + attribute \src "libresoc.v:171400.3-171401.49" + process $proc$libresoc.v:171400$9556 assign { } { } - assign $0\sr_op__rc__ok$7[0:0]$9573 \sr_op__rc__ok$7$next + assign $0\sr_op__rc__ok$7[0:0]$9557 \sr_op__rc__ok$7$next sync posedge \coresync_clk - update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9573 + update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$9557 end - attribute \src "libresoc.v:170094.3-170095.49" - process $proc$libresoc.v:170094$9574 + attribute \src "libresoc.v:171402.3-171403.49" + process $proc$libresoc.v:171402$9558 assign { } { } - assign $0\sr_op__oe__oe$8[0:0]$9575 \sr_op__oe__oe$8$next + assign $0\sr_op__oe__oe$8[0:0]$9559 \sr_op__oe__oe$8$next sync posedge \coresync_clk - update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9575 + update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$9559 end - attribute \src "libresoc.v:170096.3-170097.49" - process $proc$libresoc.v:170096$9576 + attribute \src "libresoc.v:171404.3-171405.49" + process $proc$libresoc.v:171404$9560 assign { } { } - assign $0\sr_op__oe__ok$9[0:0]$9577 \sr_op__oe__ok$9$next + assign $0\sr_op__oe__ok$9[0:0]$9561 \sr_op__oe__ok$9$next sync posedge \coresync_clk - update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9577 + update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$9561 end - attribute \src "libresoc.v:170098.3-170099.57" - process $proc$libresoc.v:170098$9578 + attribute \src "libresoc.v:171406.3-171407.57" + process $proc$libresoc.v:171406$9562 assign { } { } - assign $0\sr_op__write_cr0$10[0:0]$9579 \sr_op__write_cr0$10$next + assign $0\sr_op__write_cr0$10[0:0]$9563 \sr_op__write_cr0$10$next sync posedge \coresync_clk - update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9579 + update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$9563 end - attribute \src "libresoc.v:170100.3-170101.57" - process $proc$libresoc.v:170100$9580 + attribute \src "libresoc.v:171408.3-171409.57" + process $proc$libresoc.v:171408$9564 assign { } { } - assign $0\sr_op__invert_in$11[0:0]$9581 \sr_op__invert_in$11$next + assign $0\sr_op__invert_in$11[0:0]$9565 \sr_op__invert_in$11$next sync posedge \coresync_clk - update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9581 + update \sr_op__invert_in$11 $0\sr_op__invert_in$11[0:0]$9565 end - attribute \src "libresoc.v:170102.3-170103.61" - process $proc$libresoc.v:170102$9582 + attribute \src "libresoc.v:171410.3-171411.61" + process $proc$libresoc.v:171410$9566 assign { } { } - assign $0\sr_op__input_carry$12[1:0]$9583 \sr_op__input_carry$12$next + assign $0\sr_op__input_carry$12[1:0]$9567 \sr_op__input_carry$12$next sync posedge \coresync_clk - update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9583 + update \sr_op__input_carry$12 $0\sr_op__input_carry$12[1:0]$9567 end - attribute \src "libresoc.v:170104.3-170105.63" - process $proc$libresoc.v:170104$9584 + attribute \src "libresoc.v:171412.3-171413.63" + process $proc$libresoc.v:171412$9568 assign { } { } - assign $0\sr_op__output_carry$13[0:0]$9585 \sr_op__output_carry$13$next + assign $0\sr_op__output_carry$13[0:0]$9569 \sr_op__output_carry$13$next sync posedge \coresync_clk - update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9585 + update \sr_op__output_carry$13 $0\sr_op__output_carry$13[0:0]$9569 end - attribute \src "libresoc.v:170106.3-170107.55" - process $proc$libresoc.v:170106$9586 + attribute \src "libresoc.v:171414.3-171415.55" + process $proc$libresoc.v:171414$9570 assign { } { } - assign $0\sr_op__input_cr$14[0:0]$9587 \sr_op__input_cr$14$next + assign $0\sr_op__input_cr$14[0:0]$9571 \sr_op__input_cr$14$next sync posedge \coresync_clk - update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9587 + update \sr_op__input_cr$14 $0\sr_op__input_cr$14[0:0]$9571 end - attribute \src "libresoc.v:170108.3-170109.57" - process $proc$libresoc.v:170108$9588 + attribute \src "libresoc.v:171416.3-171417.57" + process $proc$libresoc.v:171416$9572 assign { } { } - assign $0\sr_op__output_cr$15[0:0]$9589 \sr_op__output_cr$15$next + assign $0\sr_op__output_cr$15[0:0]$9573 \sr_op__output_cr$15$next sync posedge \coresync_clk - update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9589 + update \sr_op__output_cr$15 $0\sr_op__output_cr$15[0:0]$9573 end - attribute \src "libresoc.v:170110.3-170111.55" - process $proc$libresoc.v:170110$9590 + attribute \src "libresoc.v:171418.3-171419.55" + process $proc$libresoc.v:171418$9574 assign { } { } - assign $0\sr_op__is_32bit$16[0:0]$9591 \sr_op__is_32bit$16$next + assign $0\sr_op__is_32bit$16[0:0]$9575 \sr_op__is_32bit$16$next sync posedge \coresync_clk - update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9591 + update \sr_op__is_32bit$16 $0\sr_op__is_32bit$16[0:0]$9575 end - attribute \src "libresoc.v:170112.3-170113.57" - process $proc$libresoc.v:170112$9592 + attribute \src "libresoc.v:171420.3-171421.57" + process $proc$libresoc.v:171420$9576 assign { } { } - assign $0\sr_op__is_signed$17[0:0]$9593 \sr_op__is_signed$17$next + assign $0\sr_op__is_signed$17[0:0]$9577 \sr_op__is_signed$17$next sync posedge \coresync_clk - update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9593 + update \sr_op__is_signed$17 $0\sr_op__is_signed$17[0:0]$9577 end - attribute \src "libresoc.v:170114.3-170115.47" - process $proc$libresoc.v:170114$9594 + attribute \src "libresoc.v:171422.3-171423.47" + process $proc$libresoc.v:171422$9578 assign { } { } - assign $0\sr_op__insn$18[31:0]$9595 \sr_op__insn$18$next + assign $0\sr_op__insn$18[31:0]$9579 \sr_op__insn$18$next sync posedge \coresync_clk - update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9595 + update \sr_op__insn$18 $0\sr_op__insn$18[31:0]$9579 end - attribute \src "libresoc.v:170116.3-170117.33" - process $proc$libresoc.v:170116$9596 + attribute \src "libresoc.v:171424.3-171425.33" + process $proc$libresoc.v:171424$9580 assign { } { } - assign $0\muxid$1[1:0]$9597 \muxid$1$next + assign $0\muxid$1[1:0]$9581 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$9597 + update \muxid$1 $0\muxid$1[1:0]$9581 end - attribute \src "libresoc.v:170118.3-170119.29" - process $proc$libresoc.v:170118$9598 + attribute \src "libresoc.v:171426.3-171427.29" + process $proc$libresoc.v:171426$9582 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:170177.3-170194.6" - process $proc$libresoc.v:170177$9599 + attribute \src "libresoc.v:171485.3-171502.6" + process $proc$libresoc.v:171485$9583 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9600 $2\r_busy$next[0:0]$9602 - attribute \src "libresoc.v:170178.5-170178.29" + assign $0\r_busy$next[0:0]$9584 $2\r_busy$next[0:0]$9586 + attribute \src "libresoc.v:171486.5-171486.29" switch \initial - attribute \src "libresoc.v:170178.9-170178.17" + attribute \src "libresoc.v:171486.9-171486.17" case 1'1 case end @@ -346632,34 +318002,34 @@ module \pipe2$115 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9601 1'1 + assign $1\r_busy$next[0:0]$9585 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9601 1'0 + assign $1\r_busy$next[0:0]$9585 1'0 case - assign $1\r_busy$next[0:0]$9601 \r_busy + assign $1\r_busy$next[0:0]$9585 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9602 1'0 + assign $2\r_busy$next[0:0]$9586 1'0 case - assign $2\r_busy$next[0:0]$9602 $1\r_busy$next[0:0]$9601 + assign $2\r_busy$next[0:0]$9586 $1\r_busy$next[0:0]$9585 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9600 + update \r_busy$next $0\r_busy$next[0:0]$9584 end - attribute \src "libresoc.v:170195.3-170207.6" - process $proc$libresoc.v:170195$9603 + attribute \src "libresoc.v:171503.3-171515.6" + process $proc$libresoc.v:171503$9587 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$9604 $1\muxid$1$next[1:0]$9605 - attribute \src "libresoc.v:170196.5-170196.29" + assign $0\muxid$1$next[1:0]$9588 $1\muxid$1$next[1:0]$9589 + attribute \src "libresoc.v:171504.5-171504.29" switch \initial - attribute \src "libresoc.v:170196.9-170196.17" + attribute \src "libresoc.v:171504.9-171504.17" case 1'1 case end @@ -346668,19 +318038,19 @@ module \pipe2$115 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$9605 \muxid$53 + assign $1\muxid$1$next[1:0]$9589 \muxid$53 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$9605 \muxid$53 + assign $1\muxid$1$next[1:0]$9589 \muxid$53 case - assign $1\muxid$1$next[1:0]$9605 \muxid$1 + assign $1\muxid$1$next[1:0]$9589 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$9604 + update \muxid$1$next $0\muxid$1$next[1:0]$9588 end - attribute \src "libresoc.v:170208.3-170248.6" - process $proc$libresoc.v:170208$9606 + attribute \src "libresoc.v:171516.3-171556.6" + process $proc$libresoc.v:171516$9590 assign { } { } assign { } { } assign { } { } @@ -346715,32 +318085,32 @@ module \pipe2$115 assign { } { } assign { } { } assign { } { } - assign $0\sr_op__fn_unit$3$next[13:0]$9607 $1\sr_op__fn_unit$3$next[13:0]$9624 + assign $0\sr_op__fn_unit$3$next[13:0]$9591 $1\sr_op__fn_unit$3$next[13:0]$9608 assign { } { } assign { } { } - assign $0\sr_op__input_carry$12$next[1:0]$9610 $1\sr_op__input_carry$12$next[1:0]$9627 - assign $0\sr_op__input_cr$14$next[0:0]$9611 $1\sr_op__input_cr$14$next[0:0]$9628 - assign $0\sr_op__insn$18$next[31:0]$9612 $1\sr_op__insn$18$next[31:0]$9629 - assign $0\sr_op__insn_type$2$next[6:0]$9613 $1\sr_op__insn_type$2$next[6:0]$9630 - assign $0\sr_op__invert_in$11$next[0:0]$9614 $1\sr_op__invert_in$11$next[0:0]$9631 - assign $0\sr_op__is_32bit$16$next[0:0]$9615 $1\sr_op__is_32bit$16$next[0:0]$9632 - assign $0\sr_op__is_signed$17$next[0:0]$9616 $1\sr_op__is_signed$17$next[0:0]$9633 + assign $0\sr_op__input_carry$12$next[1:0]$9594 $1\sr_op__input_carry$12$next[1:0]$9611 + assign $0\sr_op__input_cr$14$next[0:0]$9595 $1\sr_op__input_cr$14$next[0:0]$9612 + assign $0\sr_op__insn$18$next[31:0]$9596 $1\sr_op__insn$18$next[31:0]$9613 + assign $0\sr_op__insn_type$2$next[6:0]$9597 $1\sr_op__insn_type$2$next[6:0]$9614 + assign $0\sr_op__invert_in$11$next[0:0]$9598 $1\sr_op__invert_in$11$next[0:0]$9615 + assign $0\sr_op__is_32bit$16$next[0:0]$9599 $1\sr_op__is_32bit$16$next[0:0]$9616 + assign $0\sr_op__is_signed$17$next[0:0]$9600 $1\sr_op__is_signed$17$next[0:0]$9617 assign { } { } assign { } { } - assign $0\sr_op__output_carry$13$next[0:0]$9619 $1\sr_op__output_carry$13$next[0:0]$9636 - assign $0\sr_op__output_cr$15$next[0:0]$9620 $1\sr_op__output_cr$15$next[0:0]$9637 + assign $0\sr_op__output_carry$13$next[0:0]$9603 $1\sr_op__output_carry$13$next[0:0]$9620 + assign $0\sr_op__output_cr$15$next[0:0]$9604 $1\sr_op__output_cr$15$next[0:0]$9621 assign { } { } assign { } { } - assign $0\sr_op__write_cr0$10$next[0:0]$9623 $1\sr_op__write_cr0$10$next[0:0]$9640 - assign $0\sr_op__imm_data__data$4$next[63:0]$9608 $2\sr_op__imm_data__data$4$next[63:0]$9641 - assign $0\sr_op__imm_data__ok$5$next[0:0]$9609 $2\sr_op__imm_data__ok$5$next[0:0]$9642 - assign $0\sr_op__oe__oe$8$next[0:0]$9617 $2\sr_op__oe__oe$8$next[0:0]$9643 - assign $0\sr_op__oe__ok$9$next[0:0]$9618 $2\sr_op__oe__ok$9$next[0:0]$9644 - assign $0\sr_op__rc__ok$7$next[0:0]$9621 $2\sr_op__rc__ok$7$next[0:0]$9645 - assign $0\sr_op__rc__rc$6$next[0:0]$9622 $2\sr_op__rc__rc$6$next[0:0]$9646 - attribute \src "libresoc.v:170209.5-170209.29" + assign $0\sr_op__write_cr0$10$next[0:0]$9607 $1\sr_op__write_cr0$10$next[0:0]$9624 + assign $0\sr_op__imm_data__data$4$next[63:0]$9592 $2\sr_op__imm_data__data$4$next[63:0]$9625 + assign $0\sr_op__imm_data__ok$5$next[0:0]$9593 $2\sr_op__imm_data__ok$5$next[0:0]$9626 + assign $0\sr_op__oe__oe$8$next[0:0]$9601 $2\sr_op__oe__oe$8$next[0:0]$9627 + assign $0\sr_op__oe__ok$9$next[0:0]$9602 $2\sr_op__oe__ok$9$next[0:0]$9628 + assign $0\sr_op__rc__ok$7$next[0:0]$9605 $2\sr_op__rc__ok$7$next[0:0]$9629 + assign $0\sr_op__rc__rc$6$next[0:0]$9606 $2\sr_op__rc__rc$6$next[0:0]$9630 + attribute \src "libresoc.v:171517.5-171517.29" switch \initial - attribute \src "libresoc.v:170209.9-170209.17" + attribute \src "libresoc.v:171517.9-171517.17" case 1'1 case end @@ -346765,7 +318135,7 @@ module \pipe2$115 assign { } { } assign { } { } assign { } { } - assign { $1\sr_op__insn$18$next[31:0]$9629 $1\sr_op__is_signed$17$next[0:0]$9633 $1\sr_op__is_32bit$16$next[0:0]$9632 $1\sr_op__output_cr$15$next[0:0]$9637 $1\sr_op__input_cr$14$next[0:0]$9628 $1\sr_op__output_carry$13$next[0:0]$9636 $1\sr_op__input_carry$12$next[1:0]$9627 $1\sr_op__invert_in$11$next[0:0]$9631 $1\sr_op__write_cr0$10$next[0:0]$9640 $1\sr_op__oe__ok$9$next[0:0]$9635 $1\sr_op__oe__oe$8$next[0:0]$9634 $1\sr_op__rc__ok$7$next[0:0]$9638 $1\sr_op__rc__rc$6$next[0:0]$9639 $1\sr_op__imm_data__ok$5$next[0:0]$9626 $1\sr_op__imm_data__data$4$next[63:0]$9625 $1\sr_op__fn_unit$3$next[13:0]$9624 $1\sr_op__insn_type$2$next[6:0]$9630 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } + assign { $1\sr_op__insn$18$next[31:0]$9613 $1\sr_op__is_signed$17$next[0:0]$9617 $1\sr_op__is_32bit$16$next[0:0]$9616 $1\sr_op__output_cr$15$next[0:0]$9621 $1\sr_op__input_cr$14$next[0:0]$9612 $1\sr_op__output_carry$13$next[0:0]$9620 $1\sr_op__input_carry$12$next[1:0]$9611 $1\sr_op__invert_in$11$next[0:0]$9615 $1\sr_op__write_cr0$10$next[0:0]$9624 $1\sr_op__oe__ok$9$next[0:0]$9619 $1\sr_op__oe__oe$8$next[0:0]$9618 $1\sr_op__rc__ok$7$next[0:0]$9622 $1\sr_op__rc__rc$6$next[0:0]$9623 $1\sr_op__imm_data__ok$5$next[0:0]$9610 $1\sr_op__imm_data__data$4$next[63:0]$9609 $1\sr_op__fn_unit$3$next[13:0]$9608 $1\sr_op__insn_type$2$next[6:0]$9614 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -346785,25 +318155,25 @@ module \pipe2$115 assign { } { } assign { } { } assign { } { } - assign { $1\sr_op__insn$18$next[31:0]$9629 $1\sr_op__is_signed$17$next[0:0]$9633 $1\sr_op__is_32bit$16$next[0:0]$9632 $1\sr_op__output_cr$15$next[0:0]$9637 $1\sr_op__input_cr$14$next[0:0]$9628 $1\sr_op__output_carry$13$next[0:0]$9636 $1\sr_op__input_carry$12$next[1:0]$9627 $1\sr_op__invert_in$11$next[0:0]$9631 $1\sr_op__write_cr0$10$next[0:0]$9640 $1\sr_op__oe__ok$9$next[0:0]$9635 $1\sr_op__oe__oe$8$next[0:0]$9634 $1\sr_op__rc__ok$7$next[0:0]$9638 $1\sr_op__rc__rc$6$next[0:0]$9639 $1\sr_op__imm_data__ok$5$next[0:0]$9626 $1\sr_op__imm_data__data$4$next[63:0]$9625 $1\sr_op__fn_unit$3$next[13:0]$9624 $1\sr_op__insn_type$2$next[6:0]$9630 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } + assign { $1\sr_op__insn$18$next[31:0]$9613 $1\sr_op__is_signed$17$next[0:0]$9617 $1\sr_op__is_32bit$16$next[0:0]$9616 $1\sr_op__output_cr$15$next[0:0]$9621 $1\sr_op__input_cr$14$next[0:0]$9612 $1\sr_op__output_carry$13$next[0:0]$9620 $1\sr_op__input_carry$12$next[1:0]$9611 $1\sr_op__invert_in$11$next[0:0]$9615 $1\sr_op__write_cr0$10$next[0:0]$9624 $1\sr_op__oe__ok$9$next[0:0]$9619 $1\sr_op__oe__oe$8$next[0:0]$9618 $1\sr_op__rc__ok$7$next[0:0]$9622 $1\sr_op__rc__rc$6$next[0:0]$9623 $1\sr_op__imm_data__ok$5$next[0:0]$9610 $1\sr_op__imm_data__data$4$next[63:0]$9609 $1\sr_op__fn_unit$3$next[13:0]$9608 $1\sr_op__insn_type$2$next[6:0]$9614 } { \sr_op__insn$70 \sr_op__is_signed$69 \sr_op__is_32bit$68 \sr_op__output_cr$67 \sr_op__input_cr$66 \sr_op__output_carry$65 \sr_op__input_carry$64 \sr_op__invert_in$63 \sr_op__write_cr0$62 \sr_op__oe__ok$61 \sr_op__oe__oe$60 \sr_op__rc__ok$59 \sr_op__rc__rc$58 \sr_op__imm_data__ok$57 \sr_op__imm_data__data$56 \sr_op__fn_unit$55 \sr_op__insn_type$54 } case - assign $1\sr_op__fn_unit$3$next[13:0]$9624 \sr_op__fn_unit$3 - assign $1\sr_op__imm_data__data$4$next[63:0]$9625 \sr_op__imm_data__data$4 - assign $1\sr_op__imm_data__ok$5$next[0:0]$9626 \sr_op__imm_data__ok$5 - assign $1\sr_op__input_carry$12$next[1:0]$9627 \sr_op__input_carry$12 - assign $1\sr_op__input_cr$14$next[0:0]$9628 \sr_op__input_cr$14 - assign $1\sr_op__insn$18$next[31:0]$9629 \sr_op__insn$18 - assign $1\sr_op__insn_type$2$next[6:0]$9630 \sr_op__insn_type$2 - assign $1\sr_op__invert_in$11$next[0:0]$9631 \sr_op__invert_in$11 - assign $1\sr_op__is_32bit$16$next[0:0]$9632 \sr_op__is_32bit$16 - assign $1\sr_op__is_signed$17$next[0:0]$9633 \sr_op__is_signed$17 - assign $1\sr_op__oe__oe$8$next[0:0]$9634 \sr_op__oe__oe$8 - assign $1\sr_op__oe__ok$9$next[0:0]$9635 \sr_op__oe__ok$9 - assign $1\sr_op__output_carry$13$next[0:0]$9636 \sr_op__output_carry$13 - assign $1\sr_op__output_cr$15$next[0:0]$9637 \sr_op__output_cr$15 - assign $1\sr_op__rc__ok$7$next[0:0]$9638 \sr_op__rc__ok$7 - assign $1\sr_op__rc__rc$6$next[0:0]$9639 \sr_op__rc__rc$6 - assign $1\sr_op__write_cr0$10$next[0:0]$9640 \sr_op__write_cr0$10 + assign $1\sr_op__fn_unit$3$next[13:0]$9608 \sr_op__fn_unit$3 + assign $1\sr_op__imm_data__data$4$next[63:0]$9609 \sr_op__imm_data__data$4 + assign $1\sr_op__imm_data__ok$5$next[0:0]$9610 \sr_op__imm_data__ok$5 + assign $1\sr_op__input_carry$12$next[1:0]$9611 \sr_op__input_carry$12 + assign $1\sr_op__input_cr$14$next[0:0]$9612 \sr_op__input_cr$14 + assign $1\sr_op__insn$18$next[31:0]$9613 \sr_op__insn$18 + assign $1\sr_op__insn_type$2$next[6:0]$9614 \sr_op__insn_type$2 + assign $1\sr_op__invert_in$11$next[0:0]$9615 \sr_op__invert_in$11 + assign $1\sr_op__is_32bit$16$next[0:0]$9616 \sr_op__is_32bit$16 + assign $1\sr_op__is_signed$17$next[0:0]$9617 \sr_op__is_signed$17 + assign $1\sr_op__oe__oe$8$next[0:0]$9618 \sr_op__oe__oe$8 + assign $1\sr_op__oe__ok$9$next[0:0]$9619 \sr_op__oe__ok$9 + assign $1\sr_op__output_carry$13$next[0:0]$9620 \sr_op__output_carry$13 + assign $1\sr_op__output_cr$15$next[0:0]$9621 \sr_op__output_cr$15 + assign $1\sr_op__rc__ok$7$next[0:0]$9622 \sr_op__rc__ok$7 + assign $1\sr_op__rc__rc$6$next[0:0]$9623 \sr_op__rc__rc$6 + assign $1\sr_op__write_cr0$10$next[0:0]$9624 \sr_op__write_cr0$10 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -346815,51 +318185,51 @@ module \pipe2$115 assign { } { } assign { } { } assign { } { } - assign $2\sr_op__imm_data__data$4$next[63:0]$9641 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\sr_op__imm_data__ok$5$next[0:0]$9642 1'0 - assign $2\sr_op__rc__rc$6$next[0:0]$9646 1'0 - assign $2\sr_op__rc__ok$7$next[0:0]$9645 1'0 - assign $2\sr_op__oe__oe$8$next[0:0]$9643 1'0 - assign $2\sr_op__oe__ok$9$next[0:0]$9644 1'0 + assign $2\sr_op__imm_data__data$4$next[63:0]$9625 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sr_op__imm_data__ok$5$next[0:0]$9626 1'0 + assign $2\sr_op__rc__rc$6$next[0:0]$9630 1'0 + assign $2\sr_op__rc__ok$7$next[0:0]$9629 1'0 + assign $2\sr_op__oe__oe$8$next[0:0]$9627 1'0 + assign $2\sr_op__oe__ok$9$next[0:0]$9628 1'0 case - assign $2\sr_op__imm_data__data$4$next[63:0]$9641 $1\sr_op__imm_data__data$4$next[63:0]$9625 - assign $2\sr_op__imm_data__ok$5$next[0:0]$9642 $1\sr_op__imm_data__ok$5$next[0:0]$9626 - assign $2\sr_op__oe__oe$8$next[0:0]$9643 $1\sr_op__oe__oe$8$next[0:0]$9634 - assign $2\sr_op__oe__ok$9$next[0:0]$9644 $1\sr_op__oe__ok$9$next[0:0]$9635 - assign $2\sr_op__rc__ok$7$next[0:0]$9645 $1\sr_op__rc__ok$7$next[0:0]$9638 - assign $2\sr_op__rc__rc$6$next[0:0]$9646 $1\sr_op__rc__rc$6$next[0:0]$9639 + assign $2\sr_op__imm_data__data$4$next[63:0]$9625 $1\sr_op__imm_data__data$4$next[63:0]$9609 + assign $2\sr_op__imm_data__ok$5$next[0:0]$9626 $1\sr_op__imm_data__ok$5$next[0:0]$9610 + assign $2\sr_op__oe__oe$8$next[0:0]$9627 $1\sr_op__oe__oe$8$next[0:0]$9618 + assign $2\sr_op__oe__ok$9$next[0:0]$9628 $1\sr_op__oe__ok$9$next[0:0]$9619 + assign $2\sr_op__rc__ok$7$next[0:0]$9629 $1\sr_op__rc__ok$7$next[0:0]$9622 + assign $2\sr_op__rc__rc$6$next[0:0]$9630 $1\sr_op__rc__rc$6$next[0:0]$9623 end sync always - update \sr_op__fn_unit$3$next $0\sr_op__fn_unit$3$next[13:0]$9607 - update \sr_op__imm_data__data$4$next $0\sr_op__imm_data__data$4$next[63:0]$9608 - update \sr_op__imm_data__ok$5$next $0\sr_op__imm_data__ok$5$next[0:0]$9609 - update \sr_op__input_carry$12$next $0\sr_op__input_carry$12$next[1:0]$9610 - update \sr_op__input_cr$14$next $0\sr_op__input_cr$14$next[0:0]$9611 - update \sr_op__insn$18$next $0\sr_op__insn$18$next[31:0]$9612 - update \sr_op__insn_type$2$next $0\sr_op__insn_type$2$next[6:0]$9613 - update \sr_op__invert_in$11$next $0\sr_op__invert_in$11$next[0:0]$9614 - update \sr_op__is_32bit$16$next $0\sr_op__is_32bit$16$next[0:0]$9615 - update \sr_op__is_signed$17$next $0\sr_op__is_signed$17$next[0:0]$9616 - update \sr_op__oe__oe$8$next $0\sr_op__oe__oe$8$next[0:0]$9617 - update \sr_op__oe__ok$9$next $0\sr_op__oe__ok$9$next[0:0]$9618 - update \sr_op__output_carry$13$next $0\sr_op__output_carry$13$next[0:0]$9619 - update \sr_op__output_cr$15$next $0\sr_op__output_cr$15$next[0:0]$9620 - update \sr_op__rc__ok$7$next $0\sr_op__rc__ok$7$next[0:0]$9621 - update \sr_op__rc__rc$6$next $0\sr_op__rc__rc$6$next[0:0]$9622 - update \sr_op__write_cr0$10$next $0\sr_op__write_cr0$10$next[0:0]$9623 + update \sr_op__fn_unit$3$next $0\sr_op__fn_unit$3$next[13:0]$9591 + update \sr_op__imm_data__data$4$next $0\sr_op__imm_data__data$4$next[63:0]$9592 + update \sr_op__imm_data__ok$5$next $0\sr_op__imm_data__ok$5$next[0:0]$9593 + update \sr_op__input_carry$12$next $0\sr_op__input_carry$12$next[1:0]$9594 + update \sr_op__input_cr$14$next $0\sr_op__input_cr$14$next[0:0]$9595 + update \sr_op__insn$18$next $0\sr_op__insn$18$next[31:0]$9596 + update \sr_op__insn_type$2$next $0\sr_op__insn_type$2$next[6:0]$9597 + update \sr_op__invert_in$11$next $0\sr_op__invert_in$11$next[0:0]$9598 + update \sr_op__is_32bit$16$next $0\sr_op__is_32bit$16$next[0:0]$9599 + update \sr_op__is_signed$17$next $0\sr_op__is_signed$17$next[0:0]$9600 + update \sr_op__oe__oe$8$next $0\sr_op__oe__oe$8$next[0:0]$9601 + update \sr_op__oe__ok$9$next $0\sr_op__oe__ok$9$next[0:0]$9602 + update \sr_op__output_carry$13$next $0\sr_op__output_carry$13$next[0:0]$9603 + update \sr_op__output_cr$15$next $0\sr_op__output_cr$15$next[0:0]$9604 + update \sr_op__rc__ok$7$next $0\sr_op__rc__ok$7$next[0:0]$9605 + update \sr_op__rc__rc$6$next $0\sr_op__rc__rc$6$next[0:0]$9606 + update \sr_op__write_cr0$10$next $0\sr_op__write_cr0$10$next[0:0]$9607 end - attribute \src "libresoc.v:170249.3-170267.6" - process $proc$libresoc.v:170249$9647 + attribute \src "libresoc.v:171557.3-171575.6" + process $proc$libresoc.v:171557$9631 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$19$next[63:0]$9648 $1\o$19$next[63:0]$9650 + assign $0\o$19$next[63:0]$9632 $1\o$19$next[63:0]$9634 assign { } { } - assign $0\o_ok$20$next[0:0]$9649 $2\o_ok$20$next[0:0]$9652 - attribute \src "libresoc.v:170250.5-170250.29" + assign $0\o_ok$20$next[0:0]$9633 $2\o_ok$20$next[0:0]$9636 + attribute \src "libresoc.v:171558.5-171558.29" switch \initial - attribute \src "libresoc.v:170250.9-170250.17" + attribute \src "libresoc.v:171558.9-171558.17" case 1'1 case end @@ -346869,41 +318239,41 @@ module \pipe2$115 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$20$next[0:0]$9651 $1\o$19$next[63:0]$9650 } { \o_ok$72 \o$71 } + assign { $1\o_ok$20$next[0:0]$9635 $1\o$19$next[63:0]$9634 } { \o_ok$72 \o$71 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$20$next[0:0]$9651 $1\o$19$next[63:0]$9650 } { \o_ok$72 \o$71 } + assign { $1\o_ok$20$next[0:0]$9635 $1\o$19$next[63:0]$9634 } { \o_ok$72 \o$71 } case - assign $1\o$19$next[63:0]$9650 \o$19 - assign $1\o_ok$20$next[0:0]$9651 \o_ok$20 + assign $1\o$19$next[63:0]$9634 \o$19 + assign $1\o_ok$20$next[0:0]$9635 \o_ok$20 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$20$next[0:0]$9652 1'0 + assign $2\o_ok$20$next[0:0]$9636 1'0 case - assign $2\o_ok$20$next[0:0]$9652 $1\o_ok$20$next[0:0]$9651 + assign $2\o_ok$20$next[0:0]$9636 $1\o_ok$20$next[0:0]$9635 end sync always - update \o$19$next $0\o$19$next[63:0]$9648 - update \o_ok$20$next $0\o_ok$20$next[0:0]$9649 + update \o$19$next $0\o$19$next[63:0]$9632 + update \o_ok$20$next $0\o_ok$20$next[0:0]$9633 end - attribute \src "libresoc.v:170268.3-170286.6" - process $proc$libresoc.v:170268$9653 + attribute \src "libresoc.v:171576.3-171594.6" + process $proc$libresoc.v:171576$9637 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$21$next[3:0]$9654 $1\cr_a$21$next[3:0]$9656 + assign $0\cr_a$21$next[3:0]$9638 $1\cr_a$21$next[3:0]$9640 assign { } { } - assign $0\cr_a_ok$22$next[0:0]$9655 $2\cr_a_ok$22$next[0:0]$9658 - attribute \src "libresoc.v:170269.5-170269.29" + assign $0\cr_a_ok$22$next[0:0]$9639 $2\cr_a_ok$22$next[0:0]$9642 + attribute \src "libresoc.v:171577.5-171577.29" switch \initial - attribute \src "libresoc.v:170269.9-170269.17" + attribute \src "libresoc.v:171577.9-171577.17" case 1'1 case end @@ -346913,41 +318283,41 @@ module \pipe2$115 case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$22$next[0:0]$9657 $1\cr_a$21$next[3:0]$9656 } { \cr_a_ok$74 \cr_a$73 } + assign { $1\cr_a_ok$22$next[0:0]$9641 $1\cr_a$21$next[3:0]$9640 } { \cr_a_ok$74 \cr_a$73 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$22$next[0:0]$9657 $1\cr_a$21$next[3:0]$9656 } { \cr_a_ok$74 \cr_a$73 } + assign { $1\cr_a_ok$22$next[0:0]$9641 $1\cr_a$21$next[3:0]$9640 } { \cr_a_ok$74 \cr_a$73 } case - assign $1\cr_a$21$next[3:0]$9656 \cr_a$21 - assign $1\cr_a_ok$22$next[0:0]$9657 \cr_a_ok$22 + assign $1\cr_a$21$next[3:0]$9640 \cr_a$21 + assign $1\cr_a_ok$22$next[0:0]$9641 \cr_a_ok$22 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$22$next[0:0]$9658 1'0 + assign $2\cr_a_ok$22$next[0:0]$9642 1'0 case - assign $2\cr_a_ok$22$next[0:0]$9658 $1\cr_a_ok$22$next[0:0]$9657 + assign $2\cr_a_ok$22$next[0:0]$9642 $1\cr_a_ok$22$next[0:0]$9641 end sync always - update \cr_a$21$next $0\cr_a$21$next[3:0]$9654 - update \cr_a_ok$22$next $0\cr_a_ok$22$next[0:0]$9655 + update \cr_a$21$next $0\cr_a$21$next[3:0]$9638 + update \cr_a_ok$22$next $0\cr_a_ok$22$next[0:0]$9639 end - attribute \src "libresoc.v:170287.3-170305.6" - process $proc$libresoc.v:170287$9659 + attribute \src "libresoc.v:171595.3-171613.6" + process $proc$libresoc.v:171595$9643 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ca$23$next[1:0]$9660 $1\xer_ca$23$next[1:0]$9662 + assign $0\xer_ca$23$next[1:0]$9644 $1\xer_ca$23$next[1:0]$9646 assign { } { } - assign $0\xer_ca_ok$24$next[0:0]$9661 $2\xer_ca_ok$24$next[0:0]$9664 - attribute \src "libresoc.v:170288.5-170288.29" + assign $0\xer_ca_ok$24$next[0:0]$9645 $2\xer_ca_ok$24$next[0:0]$9648 + attribute \src "libresoc.v:171596.5-171596.29" switch \initial - attribute \src "libresoc.v:170288.9-170288.17" + attribute \src "libresoc.v:171596.9-171596.17" case 1'1 case end @@ -346957,30 +318327,30 @@ module \pipe2$115 case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ca_ok$24$next[0:0]$9663 $1\xer_ca$23$next[1:0]$9662 } { \xer_ca_ok$76 \xer_ca$75 } + assign { $1\xer_ca_ok$24$next[0:0]$9647 $1\xer_ca$23$next[1:0]$9646 } { \xer_ca_ok$76 \xer_ca$75 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ca_ok$24$next[0:0]$9663 $1\xer_ca$23$next[1:0]$9662 } { \xer_ca_ok$76 \xer_ca$75 } + assign { $1\xer_ca_ok$24$next[0:0]$9647 $1\xer_ca$23$next[1:0]$9646 } { \xer_ca_ok$76 \xer_ca$75 } case - assign $1\xer_ca$23$next[1:0]$9662 \xer_ca$23 - assign $1\xer_ca_ok$24$next[0:0]$9663 \xer_ca_ok$24 + assign $1\xer_ca$23$next[1:0]$9646 \xer_ca$23 + assign $1\xer_ca_ok$24$next[0:0]$9647 \xer_ca_ok$24 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ca_ok$24$next[0:0]$9664 1'0 + assign $2\xer_ca_ok$24$next[0:0]$9648 1'0 case - assign $2\xer_ca_ok$24$next[0:0]$9664 $1\xer_ca_ok$24$next[0:0]$9663 + assign $2\xer_ca_ok$24$next[0:0]$9648 $1\xer_ca_ok$24$next[0:0]$9647 end sync always - update \xer_ca$23$next $0\xer_ca$23$next[1:0]$9660 - update \xer_ca_ok$24$next $0\xer_ca_ok$24$next[0:0]$9661 + update \xer_ca$23$next $0\xer_ca$23$next[1:0]$9644 + update \xer_ca_ok$24$next $0\xer_ca_ok$24$next[0:0]$9645 end - connect \$51 $and$libresoc.v:170069$9549_Y + connect \$51 $and$libresoc.v:171377$9533_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \xer_ca_ok$76 \xer_ca$75 } { \output_xer_ca_ok \output_xer_ca$46 } @@ -346998,200 +318368,200 @@ module \pipe2$115 connect { \output_sr_op__insn \output_sr_op__is_signed \output_sr_op__is_32bit \output_sr_op__output_cr \output_sr_op__input_cr \output_sr_op__output_carry \output_sr_op__input_carry \output_sr_op__invert_in \output_sr_op__write_cr0 \output_sr_op__oe__ok \output_sr_op__oe__oe \output_sr_op__rc__ok \output_sr_op__rc__rc \output_sr_op__imm_data__ok \output_sr_op__imm_data__data \output_sr_op__fn_unit \output_sr_op__insn_type } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__invert_in \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } connect \output_muxid \muxid end -attribute \src "libresoc.v:170326.1-171290.10" +attribute \src "libresoc.v:171634.1-172598.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.alu_trap0.pipe2" attribute \generator "nMigen" module \pipe2$35 - attribute \src "libresoc.v:171196.3-171214.6" - wire width 64 $0\fast1$11$next[63:0]$9783 - attribute \src "libresoc.v:171051.3-171052.35" - wire width 64 $0\fast1$11[63:0]$9724 - attribute \src "libresoc.v:170338.14-170338.47" - wire width 64 $0\fast1$11[63:0]$9807 - attribute \src "libresoc.v:171196.3-171214.6" - wire $0\fast1_ok$next[0:0]$9782 - attribute \src "libresoc.v:171053.3-171054.33" + attribute \src "libresoc.v:172504.3-172522.6" + wire width 64 $0\fast1$11$next[63:0]$9767 + attribute \src "libresoc.v:172359.3-172360.35" + wire width 64 $0\fast1$11[63:0]$9708 + attribute \src "libresoc.v:171646.14-171646.47" + wire width 64 $0\fast1$11[63:0]$9791 + attribute \src "libresoc.v:172504.3-172522.6" + wire $0\fast1_ok$next[0:0]$9766 + attribute \src "libresoc.v:172361.3-172362.33" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:171215.3-171233.6" - wire width 64 $0\fast2$12$next[63:0]$9789 - attribute \src "libresoc.v:171047.3-171048.35" - wire width 64 $0\fast2$12[63:0]$9721 - attribute \src "libresoc.v:170354.14-170354.47" - wire width 64 $0\fast2$12[63:0]$9810 - attribute \src "libresoc.v:171215.3-171233.6" - wire $0\fast2_ok$next[0:0]$9788 - attribute \src "libresoc.v:171049.3-171050.33" + attribute \src "libresoc.v:172523.3-172541.6" + wire width 64 $0\fast2$12$next[63:0]$9773 + attribute \src "libresoc.v:172355.3-172356.35" + wire width 64 $0\fast2$12[63:0]$9705 + attribute \src "libresoc.v:171662.14-171662.47" + wire width 64 $0\fast2$12[63:0]$9794 + attribute \src "libresoc.v:172523.3-172541.6" + wire $0\fast2_ok$next[0:0]$9772 + attribute \src "libresoc.v:172357.3-172358.33" wire $0\fast2_ok[0:0] - attribute \src "libresoc.v:170327.7-170327.20" + attribute \src "libresoc.v:171635.7-171635.20" wire $0\initial[0:0] - attribute \src "libresoc.v:171253.3-171271.6" - wire width 64 $0\msr$next[63:0]$9800 - attribute \src "libresoc.v:171039.3-171040.23" + attribute \src "libresoc.v:172561.3-172579.6" + wire width 64 $0\msr$next[63:0]$9784 + attribute \src "libresoc.v:172347.3-172348.23" wire width 64 $0\msr[63:0] - attribute \src "libresoc.v:171253.3-171271.6" - wire $0\msr_ok$next[0:0]$9801 - attribute \src "libresoc.v:171041.3-171042.29" + attribute \src "libresoc.v:172561.3-172579.6" + wire $0\msr_ok$next[0:0]$9785 + attribute \src "libresoc.v:172349.3-172350.29" wire $0\msr_ok[0:0] - attribute \src "libresoc.v:171143.3-171155.6" - wire width 2 $0\muxid$1$next[1:0]$9754 - attribute \src "libresoc.v:171077.3-171078.33" - wire width 2 $0\muxid$1[1:0]$9747 - attribute \src "libresoc.v:170632.13-170632.29" - wire width 2 $0\muxid$1[1:0]$9815 - attribute \src "libresoc.v:171234.3-171252.6" - wire width 64 $0\nia$next[63:0]$9794 - attribute \src "libresoc.v:171043.3-171044.23" + attribute \src "libresoc.v:172451.3-172463.6" + wire width 2 $0\muxid$1$next[1:0]$9738 + attribute \src "libresoc.v:172385.3-172386.33" + wire width 2 $0\muxid$1[1:0]$9731 + attribute \src "libresoc.v:171940.13-171940.29" + wire width 2 $0\muxid$1[1:0]$9799 + attribute \src "libresoc.v:172542.3-172560.6" + wire width 64 $0\nia$next[63:0]$9778 + attribute \src "libresoc.v:172351.3-172352.23" wire width 64 $0\nia[63:0] - attribute \src "libresoc.v:171234.3-171252.6" - wire $0\nia_ok$next[0:0]$9795 - attribute \src "libresoc.v:171045.3-171046.29" + attribute \src "libresoc.v:172542.3-172560.6" + wire $0\nia_ok$next[0:0]$9779 + attribute \src "libresoc.v:172353.3-172354.29" wire $0\nia_ok[0:0] - attribute \src "libresoc.v:171177.3-171195.6" - wire width 64 $0\o$next[63:0]$9776 - attribute \src "libresoc.v:171055.3-171056.19" + attribute \src "libresoc.v:172485.3-172503.6" + wire width 64 $0\o$next[63:0]$9760 + attribute \src "libresoc.v:172363.3-172364.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:171177.3-171195.6" - wire $0\o_ok$next[0:0]$9777 - attribute \src "libresoc.v:171057.3-171058.25" + attribute \src "libresoc.v:172485.3-172503.6" + wire $0\o_ok$next[0:0]$9761 + attribute \src "libresoc.v:172365.3-172366.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:171125.3-171142.6" - wire $0\r_busy$next[0:0]$9750 - attribute \src "libresoc.v:171079.3-171080.29" + attribute \src "libresoc.v:172433.3-172450.6" + wire $0\r_busy$next[0:0]$9734 + attribute \src "libresoc.v:172387.3-172388.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:171156.3-171176.6" - wire width 64 $0\trap_op__cia$6$next[63:0]$9757 - attribute \src "libresoc.v:171067.3-171068.47" - wire width 64 $0\trap_op__cia$6[63:0]$9737 - attribute \src "libresoc.v:170693.14-170693.53" - wire width 64 $0\trap_op__cia$6[63:0]$9822 - attribute \src "libresoc.v:171156.3-171176.6" - wire width 14 $0\trap_op__fn_unit$3$next[13:0]$9758 - attribute \src "libresoc.v:171061.3-171062.55" - wire width 14 $0\trap_op__fn_unit$3[13:0]$9731 - attribute \src "libresoc.v:170730.14-170730.45" - wire width 14 $0\trap_op__fn_unit$3[13:0]$9824 - attribute \src "libresoc.v:171156.3-171176.6" - wire width 32 $0\trap_op__insn$4$next[31:0]$9759 - attribute \src "libresoc.v:171063.3-171064.49" - wire width 32 $0\trap_op__insn$4[31:0]$9733 - attribute \src "libresoc.v:170756.14-170756.39" - wire width 32 $0\trap_op__insn$4[31:0]$9826 - attribute \src "libresoc.v:171156.3-171176.6" - wire width 7 $0\trap_op__insn_type$2$next[6:0]$9760 - attribute \src "libresoc.v:171059.3-171060.59" - wire width 7 $0\trap_op__insn_type$2[6:0]$9729 - attribute \src "libresoc.v:170913.13-170913.43" - wire width 7 $0\trap_op__insn_type$2[6:0]$9828 - attribute \src "libresoc.v:171156.3-171176.6" - wire $0\trap_op__is_32bit$7$next[0:0]$9761 - attribute \src "libresoc.v:171069.3-171070.57" - wire $0\trap_op__is_32bit$7[0:0]$9739 - attribute \src "libresoc.v:170999.7-170999.35" - wire $0\trap_op__is_32bit$7[0:0]$9830 - attribute \src "libresoc.v:171156.3-171176.6" - wire width 8 $0\trap_op__ldst_exc$10$next[7:0]$9762 - attribute \src "libresoc.v:171075.3-171076.59" - wire width 8 $0\trap_op__ldst_exc$10[7:0]$9745 - attribute \src "libresoc.v:171006.13-171006.43" - wire width 8 $0\trap_op__ldst_exc$10[7:0]$9832 - attribute \src "libresoc.v:171156.3-171176.6" - wire width 64 $0\trap_op__msr$5$next[63:0]$9763 - attribute \src "libresoc.v:171065.3-171066.47" - wire width 64 $0\trap_op__msr$5[63:0]$9735 - attribute \src "libresoc.v:171017.14-171017.53" - wire width 64 $0\trap_op__msr$5[63:0]$9834 - attribute \src "libresoc.v:171156.3-171176.6" - wire width 13 $0\trap_op__trapaddr$9$next[12:0]$9764 - attribute \src "libresoc.v:171073.3-171074.57" - wire width 13 $0\trap_op__trapaddr$9[12:0]$9743 - attribute \src "libresoc.v:171026.14-171026.46" - wire width 13 $0\trap_op__trapaddr$9[12:0]$9836 - attribute \src "libresoc.v:171156.3-171176.6" - wire width 8 $0\trap_op__traptype$8$next[7:0]$9765 - attribute \src "libresoc.v:171071.3-171072.57" - wire width 8 $0\trap_op__traptype$8[7:0]$9741 - attribute \src "libresoc.v:171035.13-171035.42" - wire width 8 $0\trap_op__traptype$8[7:0]$9838 - attribute \src "libresoc.v:171196.3-171214.6" - wire width 64 $1\fast1$11$next[63:0]$9785 - attribute \src "libresoc.v:171196.3-171214.6" - wire $1\fast1_ok$next[0:0]$9784 - attribute \src "libresoc.v:170345.7-170345.22" + attribute \src "libresoc.v:172464.3-172484.6" + wire width 64 $0\trap_op__cia$6$next[63:0]$9741 + attribute \src "libresoc.v:172375.3-172376.47" + wire width 64 $0\trap_op__cia$6[63:0]$9721 + attribute \src "libresoc.v:172001.14-172001.53" + wire width 64 $0\trap_op__cia$6[63:0]$9806 + attribute \src "libresoc.v:172464.3-172484.6" + wire width 14 $0\trap_op__fn_unit$3$next[13:0]$9742 + attribute \src "libresoc.v:172369.3-172370.55" + wire width 14 $0\trap_op__fn_unit$3[13:0]$9715 + attribute \src "libresoc.v:172038.14-172038.45" + wire width 14 $0\trap_op__fn_unit$3[13:0]$9808 + attribute \src "libresoc.v:172464.3-172484.6" + wire width 32 $0\trap_op__insn$4$next[31:0]$9743 + attribute \src "libresoc.v:172371.3-172372.49" + wire width 32 $0\trap_op__insn$4[31:0]$9717 + attribute \src "libresoc.v:172064.14-172064.39" + wire width 32 $0\trap_op__insn$4[31:0]$9810 + attribute \src "libresoc.v:172464.3-172484.6" + wire width 7 $0\trap_op__insn_type$2$next[6:0]$9744 + attribute \src "libresoc.v:172367.3-172368.59" + wire width 7 $0\trap_op__insn_type$2[6:0]$9713 + attribute \src "libresoc.v:172221.13-172221.43" + wire width 7 $0\trap_op__insn_type$2[6:0]$9812 + attribute \src "libresoc.v:172464.3-172484.6" + wire $0\trap_op__is_32bit$7$next[0:0]$9745 + attribute \src "libresoc.v:172377.3-172378.57" + wire $0\trap_op__is_32bit$7[0:0]$9723 + attribute \src "libresoc.v:172307.7-172307.35" + wire $0\trap_op__is_32bit$7[0:0]$9814 + attribute \src "libresoc.v:172464.3-172484.6" + wire width 8 $0\trap_op__ldst_exc$10$next[7:0]$9746 + attribute \src "libresoc.v:172383.3-172384.59" + wire width 8 $0\trap_op__ldst_exc$10[7:0]$9729 + attribute \src "libresoc.v:172314.13-172314.43" + wire width 8 $0\trap_op__ldst_exc$10[7:0]$9816 + attribute \src "libresoc.v:172464.3-172484.6" + wire width 64 $0\trap_op__msr$5$next[63:0]$9747 + attribute \src "libresoc.v:172373.3-172374.47" + wire width 64 $0\trap_op__msr$5[63:0]$9719 + attribute \src "libresoc.v:172325.14-172325.53" + wire width 64 $0\trap_op__msr$5[63:0]$9818 + attribute \src "libresoc.v:172464.3-172484.6" + wire width 13 $0\trap_op__trapaddr$9$next[12:0]$9748 + attribute \src "libresoc.v:172381.3-172382.57" + wire width 13 $0\trap_op__trapaddr$9[12:0]$9727 + attribute \src "libresoc.v:172334.14-172334.46" + wire width 13 $0\trap_op__trapaddr$9[12:0]$9820 + attribute \src "libresoc.v:172464.3-172484.6" + wire width 8 $0\trap_op__traptype$8$next[7:0]$9749 + attribute \src "libresoc.v:172379.3-172380.57" + wire width 8 $0\trap_op__traptype$8[7:0]$9725 + attribute \src "libresoc.v:172343.13-172343.42" + wire width 8 $0\trap_op__traptype$8[7:0]$9822 + attribute \src "libresoc.v:172504.3-172522.6" + wire width 64 $1\fast1$11$next[63:0]$9769 + attribute \src "libresoc.v:172504.3-172522.6" + wire $1\fast1_ok$next[0:0]$9768 + attribute \src "libresoc.v:171653.7-171653.22" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:171215.3-171233.6" - wire width 64 $1\fast2$12$next[63:0]$9791 - attribute \src "libresoc.v:171215.3-171233.6" - wire $1\fast2_ok$next[0:0]$9790 - attribute \src "libresoc.v:170361.7-170361.22" + attribute \src "libresoc.v:172523.3-172541.6" + wire width 64 $1\fast2$12$next[63:0]$9775 + attribute \src "libresoc.v:172523.3-172541.6" + wire $1\fast2_ok$next[0:0]$9774 + attribute \src "libresoc.v:171669.7-171669.22" wire $1\fast2_ok[0:0] - attribute \src "libresoc.v:171253.3-171271.6" - wire width 64 $1\msr$next[63:0]$9802 - attribute \src "libresoc.v:170616.14-170616.40" + attribute \src "libresoc.v:172561.3-172579.6" + wire width 64 $1\msr$next[63:0]$9786 + attribute \src "libresoc.v:171924.14-171924.40" wire width 64 $1\msr[63:0] - attribute \src "libresoc.v:171253.3-171271.6" - wire $1\msr_ok$next[0:0]$9803 - attribute \src "libresoc.v:170623.7-170623.20" + attribute \src "libresoc.v:172561.3-172579.6" + wire $1\msr_ok$next[0:0]$9787 + attribute \src "libresoc.v:171931.7-171931.20" wire $1\msr_ok[0:0] - attribute \src "libresoc.v:171143.3-171155.6" - wire width 2 $1\muxid$1$next[1:0]$9755 - attribute \src "libresoc.v:171234.3-171252.6" - wire width 64 $1\nia$next[63:0]$9796 - attribute \src "libresoc.v:170645.14-170645.40" + attribute \src "libresoc.v:172451.3-172463.6" + wire width 2 $1\muxid$1$next[1:0]$9739 + attribute \src "libresoc.v:172542.3-172560.6" + wire width 64 $1\nia$next[63:0]$9780 + attribute \src "libresoc.v:171953.14-171953.40" wire width 64 $1\nia[63:0] - attribute \src "libresoc.v:171234.3-171252.6" - wire $1\nia_ok$next[0:0]$9797 - attribute \src "libresoc.v:170652.7-170652.20" + attribute \src "libresoc.v:172542.3-172560.6" + wire $1\nia_ok$next[0:0]$9781 + attribute \src "libresoc.v:171960.7-171960.20" wire $1\nia_ok[0:0] - attribute \src "libresoc.v:171177.3-171195.6" - wire width 64 $1\o$next[63:0]$9778 - attribute \src "libresoc.v:170659.14-170659.38" + attribute \src "libresoc.v:172485.3-172503.6" + wire width 64 $1\o$next[63:0]$9762 + attribute \src "libresoc.v:171967.14-171967.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:171177.3-171195.6" - wire $1\o_ok$next[0:0]$9779 - attribute \src "libresoc.v:170666.7-170666.18" + attribute \src "libresoc.v:172485.3-172503.6" + wire $1\o_ok$next[0:0]$9763 + attribute \src "libresoc.v:171974.7-171974.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:171125.3-171142.6" - wire $1\r_busy$next[0:0]$9751 - attribute \src "libresoc.v:170680.7-170680.20" + attribute \src "libresoc.v:172433.3-172450.6" + wire $1\r_busy$next[0:0]$9735 + attribute \src "libresoc.v:171988.7-171988.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:171156.3-171176.6" - wire width 64 $1\trap_op__cia$6$next[63:0]$9766 - attribute \src "libresoc.v:171156.3-171176.6" - wire width 14 $1\trap_op__fn_unit$3$next[13:0]$9767 - attribute \src "libresoc.v:171156.3-171176.6" - wire width 32 $1\trap_op__insn$4$next[31:0]$9768 - attribute \src "libresoc.v:171156.3-171176.6" - wire width 7 $1\trap_op__insn_type$2$next[6:0]$9769 - attribute \src "libresoc.v:171156.3-171176.6" - wire $1\trap_op__is_32bit$7$next[0:0]$9770 - attribute \src "libresoc.v:171156.3-171176.6" - wire width 8 $1\trap_op__ldst_exc$10$next[7:0]$9771 - attribute \src "libresoc.v:171156.3-171176.6" - wire width 64 $1\trap_op__msr$5$next[63:0]$9772 - attribute \src "libresoc.v:171156.3-171176.6" - wire width 13 $1\trap_op__trapaddr$9$next[12:0]$9773 - attribute \src "libresoc.v:171156.3-171176.6" - wire width 8 $1\trap_op__traptype$8$next[7:0]$9774 - attribute \src "libresoc.v:171196.3-171214.6" - wire $2\fast1_ok$next[0:0]$9786 - attribute \src "libresoc.v:171215.3-171233.6" - wire $2\fast2_ok$next[0:0]$9792 - attribute \src "libresoc.v:171253.3-171271.6" - wire $2\msr_ok$next[0:0]$9804 - attribute \src "libresoc.v:171234.3-171252.6" - wire $2\nia_ok$next[0:0]$9798 - attribute \src "libresoc.v:171177.3-171195.6" - wire $2\o_ok$next[0:0]$9780 - attribute \src "libresoc.v:171125.3-171142.6" - wire $2\r_busy$next[0:0]$9752 - attribute \src "libresoc.v:171038.18-171038.118" - wire $and$libresoc.v:171038$9715_Y + attribute \src "libresoc.v:172464.3-172484.6" + wire width 64 $1\trap_op__cia$6$next[63:0]$9750 + attribute \src "libresoc.v:172464.3-172484.6" + wire width 14 $1\trap_op__fn_unit$3$next[13:0]$9751 + attribute \src "libresoc.v:172464.3-172484.6" + wire width 32 $1\trap_op__insn$4$next[31:0]$9752 + attribute \src "libresoc.v:172464.3-172484.6" + wire width 7 $1\trap_op__insn_type$2$next[6:0]$9753 + attribute \src "libresoc.v:172464.3-172484.6" + wire $1\trap_op__is_32bit$7$next[0:0]$9754 + attribute \src "libresoc.v:172464.3-172484.6" + wire width 8 $1\trap_op__ldst_exc$10$next[7:0]$9755 + attribute \src "libresoc.v:172464.3-172484.6" + wire width 64 $1\trap_op__msr$5$next[63:0]$9756 + attribute \src "libresoc.v:172464.3-172484.6" + wire width 13 $1\trap_op__trapaddr$9$next[12:0]$9757 + attribute \src "libresoc.v:172464.3-172484.6" + wire width 8 $1\trap_op__traptype$8$next[7:0]$9758 + attribute \src "libresoc.v:172504.3-172522.6" + wire $2\fast1_ok$next[0:0]$9770 + attribute \src "libresoc.v:172523.3-172541.6" + wire $2\fast2_ok$next[0:0]$9776 + attribute \src "libresoc.v:172561.3-172579.6" + wire $2\msr_ok$next[0:0]$9788 + attribute \src "libresoc.v:172542.3-172560.6" + wire $2\nia_ok$next[0:0]$9782 + attribute \src "libresoc.v:172485.3-172503.6" + wire $2\o_ok$next[0:0]$9764 + attribute \src "libresoc.v:172433.3-172450.6" + wire $2\r_busy$next[0:0]$9736 + attribute \src "libresoc.v:172346.18-172346.118" + wire $and$libresoc.v:172346$9699_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 40 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 input 16 \fast1 @@ -347221,7 +318591,7 @@ module \pipe2$35 wire \fast2_ok$43 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \fast2_ok$next - attribute \src "libresoc.v:170327.7-170327.15" + attribute \src "libresoc.v:171635.7-171635.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire width 64 \main_fast1 @@ -347880,7 +319250,7 @@ module \pipe2$35 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 8 \trap_op__traptype$8$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:171038$9715 + cell $and $and$libresoc.v:172346$9699 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -347888,10 +319258,10 @@ module \pipe2$35 parameter \Y_WIDTH 1 connect \A \p_valid_i$25 connect \B \p_ready_o - connect \Y $and$libresoc.v:171038$9715_Y + connect \Y $and$libresoc.v:172346$9699_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:171081.13-171116.4" + attribute \src "libresoc.v:172389.13-172424.4" cell \main$38 \main connect \fast1 \main_fast1 connect \fast1$11 \main_fast1$23 @@ -347929,349 +319299,349 @@ module \pipe2$35 connect \trap_op__traptype$8 \main_trap_op__traptype$20 end attribute \module_not_derived 1 - attribute \src "libresoc.v:171117.10-171120.4" + attribute \src "libresoc.v:172425.10-172428.4" cell \n$37 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:171121.10-171124.4" + attribute \src "libresoc.v:172429.10-172432.4" cell \p$36 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:170327.7-170327.20" - process $proc$libresoc.v:170327$9805 + attribute \src "libresoc.v:171635.7-171635.20" + process $proc$libresoc.v:171635$9789 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:170338.14-170338.47" - process $proc$libresoc.v:170338$9806 + attribute \src "libresoc.v:171646.14-171646.47" + process $proc$libresoc.v:171646$9790 assign { } { } - assign $0\fast1$11[63:0]$9807 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\fast1$11[63:0]$9791 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \fast1$11 $0\fast1$11[63:0]$9807 + update \fast1$11 $0\fast1$11[63:0]$9791 end - attribute \src "libresoc.v:170345.7-170345.22" - process $proc$libresoc.v:170345$9808 + attribute \src "libresoc.v:171653.7-171653.22" + process $proc$libresoc.v:171653$9792 assign { } { } assign $1\fast1_ok[0:0] 1'0 sync always sync init update \fast1_ok $1\fast1_ok[0:0] end - attribute \src "libresoc.v:170354.14-170354.47" - process $proc$libresoc.v:170354$9809 + attribute \src "libresoc.v:171662.14-171662.47" + process $proc$libresoc.v:171662$9793 assign { } { } - assign $0\fast2$12[63:0]$9810 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\fast2$12[63:0]$9794 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \fast2$12 $0\fast2$12[63:0]$9810 + update \fast2$12 $0\fast2$12[63:0]$9794 end - attribute \src "libresoc.v:170361.7-170361.22" - process $proc$libresoc.v:170361$9811 + attribute \src "libresoc.v:171669.7-171669.22" + process $proc$libresoc.v:171669$9795 assign { } { } assign $1\fast2_ok[0:0] 1'0 sync always sync init update \fast2_ok $1\fast2_ok[0:0] end - attribute \src "libresoc.v:170616.14-170616.40" - process $proc$libresoc.v:170616$9812 + attribute \src "libresoc.v:171924.14-171924.40" + process $proc$libresoc.v:171924$9796 assign { } { } assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \msr $1\msr[63:0] end - attribute \src "libresoc.v:170623.7-170623.20" - process $proc$libresoc.v:170623$9813 + attribute \src "libresoc.v:171931.7-171931.20" + process $proc$libresoc.v:171931$9797 assign { } { } assign $1\msr_ok[0:0] 1'0 sync always sync init update \msr_ok $1\msr_ok[0:0] end - attribute \src "libresoc.v:170632.13-170632.29" - process $proc$libresoc.v:170632$9814 + attribute \src "libresoc.v:171940.13-171940.29" + process $proc$libresoc.v:171940$9798 assign { } { } - assign $0\muxid$1[1:0]$9815 2'00 + assign $0\muxid$1[1:0]$9799 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$9815 + update \muxid$1 $0\muxid$1[1:0]$9799 end - attribute \src "libresoc.v:170645.14-170645.40" - process $proc$libresoc.v:170645$9816 + attribute \src "libresoc.v:171953.14-171953.40" + process $proc$libresoc.v:171953$9800 assign { } { } assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \nia $1\nia[63:0] end - attribute \src "libresoc.v:170652.7-170652.20" - process $proc$libresoc.v:170652$9817 + attribute \src "libresoc.v:171960.7-171960.20" + process $proc$libresoc.v:171960$9801 assign { } { } assign $1\nia_ok[0:0] 1'0 sync always sync init update \nia_ok $1\nia_ok[0:0] end - attribute \src "libresoc.v:170659.14-170659.38" - process $proc$libresoc.v:170659$9818 + attribute \src "libresoc.v:171967.14-171967.38" + process $proc$libresoc.v:171967$9802 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:170666.7-170666.18" - process $proc$libresoc.v:170666$9819 + attribute \src "libresoc.v:171974.7-171974.18" + process $proc$libresoc.v:171974$9803 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:170680.7-170680.20" - process $proc$libresoc.v:170680$9820 + attribute \src "libresoc.v:171988.7-171988.20" + process $proc$libresoc.v:171988$9804 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:170693.14-170693.53" - process $proc$libresoc.v:170693$9821 + attribute \src "libresoc.v:172001.14-172001.53" + process $proc$libresoc.v:172001$9805 assign { } { } - assign $0\trap_op__cia$6[63:0]$9822 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\trap_op__cia$6[63:0]$9806 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9822 + update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9806 end - attribute \src "libresoc.v:170730.14-170730.45" - process $proc$libresoc.v:170730$9823 + attribute \src "libresoc.v:172038.14-172038.45" + process $proc$libresoc.v:172038$9807 assign { } { } - assign $0\trap_op__fn_unit$3[13:0]$9824 14'00000000000000 + assign $0\trap_op__fn_unit$3[13:0]$9808 14'00000000000000 sync always sync init - update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[13:0]$9824 + update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[13:0]$9808 end - attribute \src "libresoc.v:170756.14-170756.39" - process $proc$libresoc.v:170756$9825 + attribute \src "libresoc.v:172064.14-172064.39" + process $proc$libresoc.v:172064$9809 assign { } { } - assign $0\trap_op__insn$4[31:0]$9826 0 + assign $0\trap_op__insn$4[31:0]$9810 0 sync always sync init - update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9826 + update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9810 end - attribute \src "libresoc.v:170913.13-170913.43" - process $proc$libresoc.v:170913$9827 + attribute \src "libresoc.v:172221.13-172221.43" + process $proc$libresoc.v:172221$9811 assign { } { } - assign $0\trap_op__insn_type$2[6:0]$9828 7'0000000 + assign $0\trap_op__insn_type$2[6:0]$9812 7'0000000 sync always sync init - update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9828 + update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9812 end - attribute \src "libresoc.v:170999.7-170999.35" - process $proc$libresoc.v:170999$9829 + attribute \src "libresoc.v:172307.7-172307.35" + process $proc$libresoc.v:172307$9813 assign { } { } - assign $0\trap_op__is_32bit$7[0:0]$9830 1'0 + assign $0\trap_op__is_32bit$7[0:0]$9814 1'0 sync always sync init - update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9830 + update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9814 end - attribute \src "libresoc.v:171006.13-171006.43" - process $proc$libresoc.v:171006$9831 + attribute \src "libresoc.v:172314.13-172314.43" + process $proc$libresoc.v:172314$9815 assign { } { } - assign $0\trap_op__ldst_exc$10[7:0]$9832 8'00000000 + assign $0\trap_op__ldst_exc$10[7:0]$9816 8'00000000 sync always sync init - update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9832 + update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9816 end - attribute \src "libresoc.v:171017.14-171017.53" - process $proc$libresoc.v:171017$9833 + attribute \src "libresoc.v:172325.14-172325.53" + process $proc$libresoc.v:172325$9817 assign { } { } - assign $0\trap_op__msr$5[63:0]$9834 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\trap_op__msr$5[63:0]$9818 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9834 + update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9818 end - attribute \src "libresoc.v:171026.14-171026.46" - process $proc$libresoc.v:171026$9835 + attribute \src "libresoc.v:172334.14-172334.46" + process $proc$libresoc.v:172334$9819 assign { } { } - assign $0\trap_op__trapaddr$9[12:0]$9836 13'0000000000000 + assign $0\trap_op__trapaddr$9[12:0]$9820 13'0000000000000 sync always sync init - update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9836 + update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9820 end - attribute \src "libresoc.v:171035.13-171035.42" - process $proc$libresoc.v:171035$9837 + attribute \src "libresoc.v:172343.13-172343.42" + process $proc$libresoc.v:172343$9821 assign { } { } - assign $0\trap_op__traptype$8[7:0]$9838 8'00000000 + assign $0\trap_op__traptype$8[7:0]$9822 8'00000000 sync always sync init - update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9838 + update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9822 end - attribute \src "libresoc.v:171039.3-171040.23" - process $proc$libresoc.v:171039$9716 + attribute \src "libresoc.v:172347.3-172348.23" + process $proc$libresoc.v:172347$9700 assign { } { } assign $0\msr[63:0] \msr$next sync posedge \coresync_clk update \msr $0\msr[63:0] end - attribute \src "libresoc.v:171041.3-171042.29" - process $proc$libresoc.v:171041$9717 + attribute \src "libresoc.v:172349.3-172350.29" + process $proc$libresoc.v:172349$9701 assign { } { } assign $0\msr_ok[0:0] \msr_ok$next sync posedge \coresync_clk update \msr_ok $0\msr_ok[0:0] end - attribute \src "libresoc.v:171043.3-171044.23" - process $proc$libresoc.v:171043$9718 + attribute \src "libresoc.v:172351.3-172352.23" + process $proc$libresoc.v:172351$9702 assign { } { } assign $0\nia[63:0] \nia$next sync posedge \coresync_clk update \nia $0\nia[63:0] end - attribute \src "libresoc.v:171045.3-171046.29" - process $proc$libresoc.v:171045$9719 + attribute \src "libresoc.v:172353.3-172354.29" + process $proc$libresoc.v:172353$9703 assign { } { } assign $0\nia_ok[0:0] \nia_ok$next sync posedge \coresync_clk update \nia_ok $0\nia_ok[0:0] end - attribute \src "libresoc.v:171047.3-171048.35" - process $proc$libresoc.v:171047$9720 + attribute \src "libresoc.v:172355.3-172356.35" + process $proc$libresoc.v:172355$9704 assign { } { } - assign $0\fast2$12[63:0]$9721 \fast2$12$next + assign $0\fast2$12[63:0]$9705 \fast2$12$next sync posedge \coresync_clk - update \fast2$12 $0\fast2$12[63:0]$9721 + update \fast2$12 $0\fast2$12[63:0]$9705 end - attribute \src "libresoc.v:171049.3-171050.33" - process $proc$libresoc.v:171049$9722 + attribute \src "libresoc.v:172357.3-172358.33" + process $proc$libresoc.v:172357$9706 assign { } { } assign $0\fast2_ok[0:0] \fast2_ok$next sync posedge \coresync_clk update \fast2_ok $0\fast2_ok[0:0] end - attribute \src "libresoc.v:171051.3-171052.35" - process $proc$libresoc.v:171051$9723 + attribute \src "libresoc.v:172359.3-172360.35" + process $proc$libresoc.v:172359$9707 assign { } { } - assign $0\fast1$11[63:0]$9724 \fast1$11$next + assign $0\fast1$11[63:0]$9708 \fast1$11$next sync posedge \coresync_clk - update \fast1$11 $0\fast1$11[63:0]$9724 + update \fast1$11 $0\fast1$11[63:0]$9708 end - attribute \src "libresoc.v:171053.3-171054.33" - process $proc$libresoc.v:171053$9725 + attribute \src "libresoc.v:172361.3-172362.33" + process $proc$libresoc.v:172361$9709 assign { } { } assign $0\fast1_ok[0:0] \fast1_ok$next sync posedge \coresync_clk update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:171055.3-171056.19" - process $proc$libresoc.v:171055$9726 + attribute \src "libresoc.v:172363.3-172364.19" + process $proc$libresoc.v:172363$9710 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:171057.3-171058.25" - process $proc$libresoc.v:171057$9727 + attribute \src "libresoc.v:172365.3-172366.25" + process $proc$libresoc.v:172365$9711 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:171059.3-171060.59" - process $proc$libresoc.v:171059$9728 + attribute \src "libresoc.v:172367.3-172368.59" + process $proc$libresoc.v:172367$9712 assign { } { } - assign $0\trap_op__insn_type$2[6:0]$9729 \trap_op__insn_type$2$next + assign $0\trap_op__insn_type$2[6:0]$9713 \trap_op__insn_type$2$next sync posedge \coresync_clk - update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9729 + update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$9713 end - attribute \src "libresoc.v:171061.3-171062.55" - process $proc$libresoc.v:171061$9730 + attribute \src "libresoc.v:172369.3-172370.55" + process $proc$libresoc.v:172369$9714 assign { } { } - assign $0\trap_op__fn_unit$3[13:0]$9731 \trap_op__fn_unit$3$next + assign $0\trap_op__fn_unit$3[13:0]$9715 \trap_op__fn_unit$3$next sync posedge \coresync_clk - update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[13:0]$9731 + update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[13:0]$9715 end - attribute \src "libresoc.v:171063.3-171064.49" - process $proc$libresoc.v:171063$9732 + attribute \src "libresoc.v:172371.3-172372.49" + process $proc$libresoc.v:172371$9716 assign { } { } - assign $0\trap_op__insn$4[31:0]$9733 \trap_op__insn$4$next + assign $0\trap_op__insn$4[31:0]$9717 \trap_op__insn$4$next sync posedge \coresync_clk - update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9733 + update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$9717 end - attribute \src "libresoc.v:171065.3-171066.47" - process $proc$libresoc.v:171065$9734 + attribute \src "libresoc.v:172373.3-172374.47" + process $proc$libresoc.v:172373$9718 assign { } { } - assign $0\trap_op__msr$5[63:0]$9735 \trap_op__msr$5$next + assign $0\trap_op__msr$5[63:0]$9719 \trap_op__msr$5$next sync posedge \coresync_clk - update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9735 + update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$9719 end - attribute \src "libresoc.v:171067.3-171068.47" - process $proc$libresoc.v:171067$9736 + attribute \src "libresoc.v:172375.3-172376.47" + process $proc$libresoc.v:172375$9720 assign { } { } - assign $0\trap_op__cia$6[63:0]$9737 \trap_op__cia$6$next + assign $0\trap_op__cia$6[63:0]$9721 \trap_op__cia$6$next sync posedge \coresync_clk - update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9737 + update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$9721 end - attribute \src "libresoc.v:171069.3-171070.57" - process $proc$libresoc.v:171069$9738 + attribute \src "libresoc.v:172377.3-172378.57" + process $proc$libresoc.v:172377$9722 assign { } { } - assign $0\trap_op__is_32bit$7[0:0]$9739 \trap_op__is_32bit$7$next + assign $0\trap_op__is_32bit$7[0:0]$9723 \trap_op__is_32bit$7$next sync posedge \coresync_clk - update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9739 + update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$9723 end - attribute \src "libresoc.v:171071.3-171072.57" - process $proc$libresoc.v:171071$9740 + attribute \src "libresoc.v:172379.3-172380.57" + process $proc$libresoc.v:172379$9724 assign { } { } - assign $0\trap_op__traptype$8[7:0]$9741 \trap_op__traptype$8$next + assign $0\trap_op__traptype$8[7:0]$9725 \trap_op__traptype$8$next sync posedge \coresync_clk - update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9741 + update \trap_op__traptype$8 $0\trap_op__traptype$8[7:0]$9725 end - attribute \src "libresoc.v:171073.3-171074.57" - process $proc$libresoc.v:171073$9742 + attribute \src "libresoc.v:172381.3-172382.57" + process $proc$libresoc.v:172381$9726 assign { } { } - assign $0\trap_op__trapaddr$9[12:0]$9743 \trap_op__trapaddr$9$next + assign $0\trap_op__trapaddr$9[12:0]$9727 \trap_op__trapaddr$9$next sync posedge \coresync_clk - update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9743 + update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$9727 end - attribute \src "libresoc.v:171075.3-171076.59" - process $proc$libresoc.v:171075$9744 + attribute \src "libresoc.v:172383.3-172384.59" + process $proc$libresoc.v:172383$9728 assign { } { } - assign $0\trap_op__ldst_exc$10[7:0]$9745 \trap_op__ldst_exc$10$next + assign $0\trap_op__ldst_exc$10[7:0]$9729 \trap_op__ldst_exc$10$next sync posedge \coresync_clk - update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9745 + update \trap_op__ldst_exc$10 $0\trap_op__ldst_exc$10[7:0]$9729 end - attribute \src "libresoc.v:171077.3-171078.33" - process $proc$libresoc.v:171077$9746 + attribute \src "libresoc.v:172385.3-172386.33" + process $proc$libresoc.v:172385$9730 assign { } { } - assign $0\muxid$1[1:0]$9747 \muxid$1$next + assign $0\muxid$1[1:0]$9731 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$9747 + update \muxid$1 $0\muxid$1[1:0]$9731 end - attribute \src "libresoc.v:171079.3-171080.29" - process $proc$libresoc.v:171079$9748 + attribute \src "libresoc.v:172387.3-172388.29" + process $proc$libresoc.v:172387$9732 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:171125.3-171142.6" - process $proc$libresoc.v:171125$9749 + attribute \src "libresoc.v:172433.3-172450.6" + process $proc$libresoc.v:172433$9733 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9750 $2\r_busy$next[0:0]$9752 - attribute \src "libresoc.v:171126.5-171126.29" + assign $0\r_busy$next[0:0]$9734 $2\r_busy$next[0:0]$9736 + attribute \src "libresoc.v:172434.5-172434.29" switch \initial - attribute \src "libresoc.v:171126.9-171126.17" + attribute \src "libresoc.v:172434.9-172434.17" case 1'1 case end @@ -348280,34 +319650,34 @@ module \pipe2$35 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9751 1'1 + assign $1\r_busy$next[0:0]$9735 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9751 1'0 + assign $1\r_busy$next[0:0]$9735 1'0 case - assign $1\r_busy$next[0:0]$9751 \r_busy + assign $1\r_busy$next[0:0]$9735 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9752 1'0 + assign $2\r_busy$next[0:0]$9736 1'0 case - assign $2\r_busy$next[0:0]$9752 $1\r_busy$next[0:0]$9751 + assign $2\r_busy$next[0:0]$9736 $1\r_busy$next[0:0]$9735 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9750 + update \r_busy$next $0\r_busy$next[0:0]$9734 end - attribute \src "libresoc.v:171143.3-171155.6" - process $proc$libresoc.v:171143$9753 + attribute \src "libresoc.v:172451.3-172463.6" + process $proc$libresoc.v:172451$9737 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$9754 $1\muxid$1$next[1:0]$9755 - attribute \src "libresoc.v:171144.5-171144.29" + assign $0\muxid$1$next[1:0]$9738 $1\muxid$1$next[1:0]$9739 + attribute \src "libresoc.v:172452.5-172452.29" switch \initial - attribute \src "libresoc.v:171144.9-171144.17" + attribute \src "libresoc.v:172452.9-172452.17" case 1'1 case end @@ -348316,19 +319686,19 @@ module \pipe2$35 attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$9755 \muxid$28 + assign $1\muxid$1$next[1:0]$9739 \muxid$28 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$9755 \muxid$28 + assign $1\muxid$1$next[1:0]$9739 \muxid$28 case - assign $1\muxid$1$next[1:0]$9755 \muxid$1 + assign $1\muxid$1$next[1:0]$9739 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$9754 + update \muxid$1$next $0\muxid$1$next[1:0]$9738 end - attribute \src "libresoc.v:171156.3-171176.6" - process $proc$libresoc.v:171156$9756 + attribute \src "libresoc.v:172464.3-172484.6" + process $proc$libresoc.v:172464$9740 assign { } { } assign { } { } assign { } { } @@ -348347,18 +319717,18 @@ module \pipe2$35 assign { } { } assign { } { } assign { } { } - assign $0\trap_op__cia$6$next[63:0]$9757 $1\trap_op__cia$6$next[63:0]$9766 - assign $0\trap_op__fn_unit$3$next[13:0]$9758 $1\trap_op__fn_unit$3$next[13:0]$9767 - assign $0\trap_op__insn$4$next[31:0]$9759 $1\trap_op__insn$4$next[31:0]$9768 - assign $0\trap_op__insn_type$2$next[6:0]$9760 $1\trap_op__insn_type$2$next[6:0]$9769 - assign $0\trap_op__is_32bit$7$next[0:0]$9761 $1\trap_op__is_32bit$7$next[0:0]$9770 - assign $0\trap_op__ldst_exc$10$next[7:0]$9762 $1\trap_op__ldst_exc$10$next[7:0]$9771 - assign $0\trap_op__msr$5$next[63:0]$9763 $1\trap_op__msr$5$next[63:0]$9772 - assign $0\trap_op__trapaddr$9$next[12:0]$9764 $1\trap_op__trapaddr$9$next[12:0]$9773 - assign $0\trap_op__traptype$8$next[7:0]$9765 $1\trap_op__traptype$8$next[7:0]$9774 - attribute \src "libresoc.v:171157.5-171157.29" + assign $0\trap_op__cia$6$next[63:0]$9741 $1\trap_op__cia$6$next[63:0]$9750 + assign $0\trap_op__fn_unit$3$next[13:0]$9742 $1\trap_op__fn_unit$3$next[13:0]$9751 + assign $0\trap_op__insn$4$next[31:0]$9743 $1\trap_op__insn$4$next[31:0]$9752 + assign $0\trap_op__insn_type$2$next[6:0]$9744 $1\trap_op__insn_type$2$next[6:0]$9753 + assign $0\trap_op__is_32bit$7$next[0:0]$9745 $1\trap_op__is_32bit$7$next[0:0]$9754 + assign $0\trap_op__ldst_exc$10$next[7:0]$9746 $1\trap_op__ldst_exc$10$next[7:0]$9755 + assign $0\trap_op__msr$5$next[63:0]$9747 $1\trap_op__msr$5$next[63:0]$9756 + assign $0\trap_op__trapaddr$9$next[12:0]$9748 $1\trap_op__trapaddr$9$next[12:0]$9757 + assign $0\trap_op__traptype$8$next[7:0]$9749 $1\trap_op__traptype$8$next[7:0]$9758 + attribute \src "libresoc.v:172465.5-172465.29" switch \initial - attribute \src "libresoc.v:171157.9-171157.17" + attribute \src "libresoc.v:172465.9-172465.17" case 1'1 case end @@ -348375,7 +319745,7 @@ module \pipe2$35 assign { } { } assign { } { } assign { } { } - assign { $1\trap_op__ldst_exc$10$next[7:0]$9771 $1\trap_op__trapaddr$9$next[12:0]$9773 $1\trap_op__traptype$8$next[7:0]$9774 $1\trap_op__is_32bit$7$next[0:0]$9770 $1\trap_op__cia$6$next[63:0]$9766 $1\trap_op__msr$5$next[63:0]$9772 $1\trap_op__insn$4$next[31:0]$9768 $1\trap_op__fn_unit$3$next[13:0]$9767 $1\trap_op__insn_type$2$next[6:0]$9769 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } + assign { $1\trap_op__ldst_exc$10$next[7:0]$9755 $1\trap_op__trapaddr$9$next[12:0]$9757 $1\trap_op__traptype$8$next[7:0]$9758 $1\trap_op__is_32bit$7$next[0:0]$9754 $1\trap_op__cia$6$next[63:0]$9750 $1\trap_op__msr$5$next[63:0]$9756 $1\trap_op__insn$4$next[31:0]$9752 $1\trap_op__fn_unit$3$next[13:0]$9751 $1\trap_op__insn_type$2$next[6:0]$9753 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -348387,41 +319757,41 @@ module \pipe2$35 assign { } { } assign { } { } assign { } { } - assign { $1\trap_op__ldst_exc$10$next[7:0]$9771 $1\trap_op__trapaddr$9$next[12:0]$9773 $1\trap_op__traptype$8$next[7:0]$9774 $1\trap_op__is_32bit$7$next[0:0]$9770 $1\trap_op__cia$6$next[63:0]$9766 $1\trap_op__msr$5$next[63:0]$9772 $1\trap_op__insn$4$next[31:0]$9768 $1\trap_op__fn_unit$3$next[13:0]$9767 $1\trap_op__insn_type$2$next[6:0]$9769 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } + assign { $1\trap_op__ldst_exc$10$next[7:0]$9755 $1\trap_op__trapaddr$9$next[12:0]$9757 $1\trap_op__traptype$8$next[7:0]$9758 $1\trap_op__is_32bit$7$next[0:0]$9754 $1\trap_op__cia$6$next[63:0]$9750 $1\trap_op__msr$5$next[63:0]$9756 $1\trap_op__insn$4$next[31:0]$9752 $1\trap_op__fn_unit$3$next[13:0]$9751 $1\trap_op__insn_type$2$next[6:0]$9753 } { \trap_op__ldst_exc$37 \trap_op__trapaddr$36 \trap_op__traptype$35 \trap_op__is_32bit$34 \trap_op__cia$33 \trap_op__msr$32 \trap_op__insn$31 \trap_op__fn_unit$30 \trap_op__insn_type$29 } case - assign $1\trap_op__cia$6$next[63:0]$9766 \trap_op__cia$6 - assign $1\trap_op__fn_unit$3$next[13:0]$9767 \trap_op__fn_unit$3 - assign $1\trap_op__insn$4$next[31:0]$9768 \trap_op__insn$4 - assign $1\trap_op__insn_type$2$next[6:0]$9769 \trap_op__insn_type$2 - assign $1\trap_op__is_32bit$7$next[0:0]$9770 \trap_op__is_32bit$7 - assign $1\trap_op__ldst_exc$10$next[7:0]$9771 \trap_op__ldst_exc$10 - assign $1\trap_op__msr$5$next[63:0]$9772 \trap_op__msr$5 - assign $1\trap_op__trapaddr$9$next[12:0]$9773 \trap_op__trapaddr$9 - assign $1\trap_op__traptype$8$next[7:0]$9774 \trap_op__traptype$8 + assign $1\trap_op__cia$6$next[63:0]$9750 \trap_op__cia$6 + assign $1\trap_op__fn_unit$3$next[13:0]$9751 \trap_op__fn_unit$3 + assign $1\trap_op__insn$4$next[31:0]$9752 \trap_op__insn$4 + assign $1\trap_op__insn_type$2$next[6:0]$9753 \trap_op__insn_type$2 + assign $1\trap_op__is_32bit$7$next[0:0]$9754 \trap_op__is_32bit$7 + assign $1\trap_op__ldst_exc$10$next[7:0]$9755 \trap_op__ldst_exc$10 + assign $1\trap_op__msr$5$next[63:0]$9756 \trap_op__msr$5 + assign $1\trap_op__trapaddr$9$next[12:0]$9757 \trap_op__trapaddr$9 + assign $1\trap_op__traptype$8$next[7:0]$9758 \trap_op__traptype$8 end sync always - update \trap_op__cia$6$next $0\trap_op__cia$6$next[63:0]$9757 - update \trap_op__fn_unit$3$next $0\trap_op__fn_unit$3$next[13:0]$9758 - update \trap_op__insn$4$next $0\trap_op__insn$4$next[31:0]$9759 - update \trap_op__insn_type$2$next $0\trap_op__insn_type$2$next[6:0]$9760 - update \trap_op__is_32bit$7$next $0\trap_op__is_32bit$7$next[0:0]$9761 - update \trap_op__ldst_exc$10$next $0\trap_op__ldst_exc$10$next[7:0]$9762 - update \trap_op__msr$5$next $0\trap_op__msr$5$next[63:0]$9763 - update \trap_op__trapaddr$9$next $0\trap_op__trapaddr$9$next[12:0]$9764 - update \trap_op__traptype$8$next $0\trap_op__traptype$8$next[7:0]$9765 + update \trap_op__cia$6$next $0\trap_op__cia$6$next[63:0]$9741 + update \trap_op__fn_unit$3$next $0\trap_op__fn_unit$3$next[13:0]$9742 + update \trap_op__insn$4$next $0\trap_op__insn$4$next[31:0]$9743 + update \trap_op__insn_type$2$next $0\trap_op__insn_type$2$next[6:0]$9744 + update \trap_op__is_32bit$7$next $0\trap_op__is_32bit$7$next[0:0]$9745 + update \trap_op__ldst_exc$10$next $0\trap_op__ldst_exc$10$next[7:0]$9746 + update \trap_op__msr$5$next $0\trap_op__msr$5$next[63:0]$9747 + update \trap_op__trapaddr$9$next $0\trap_op__trapaddr$9$next[12:0]$9748 + update \trap_op__traptype$8$next $0\trap_op__traptype$8$next[7:0]$9749 end - attribute \src "libresoc.v:171177.3-171195.6" - process $proc$libresoc.v:171177$9775 + attribute \src "libresoc.v:172485.3-172503.6" + process $proc$libresoc.v:172485$9759 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$9776 $1\o$next[63:0]$9778 + assign $0\o$next[63:0]$9760 $1\o$next[63:0]$9762 assign { } { } - assign $0\o_ok$next[0:0]$9777 $2\o_ok$next[0:0]$9780 - attribute \src "libresoc.v:171178.5-171178.29" + assign $0\o_ok$next[0:0]$9761 $2\o_ok$next[0:0]$9764 + attribute \src "libresoc.v:172486.5-172486.29" switch \initial - attribute \src "libresoc.v:171178.9-171178.17" + attribute \src "libresoc.v:172486.9-172486.17" case 1'1 case end @@ -348431,41 +319801,41 @@ module \pipe2$35 case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9779 $1\o$next[63:0]$9778 } { \o_ok$39 \o$38 } + assign { $1\o_ok$next[0:0]$9763 $1\o$next[63:0]$9762 } { \o_ok$39 \o$38 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9779 $1\o$next[63:0]$9778 } { \o_ok$39 \o$38 } + assign { $1\o_ok$next[0:0]$9763 $1\o$next[63:0]$9762 } { \o_ok$39 \o$38 } case - assign $1\o$next[63:0]$9778 \o - assign $1\o_ok$next[0:0]$9779 \o_ok + assign $1\o$next[63:0]$9762 \o + assign $1\o_ok$next[0:0]$9763 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$9780 1'0 + assign $2\o_ok$next[0:0]$9764 1'0 case - assign $2\o_ok$next[0:0]$9780 $1\o_ok$next[0:0]$9779 + assign $2\o_ok$next[0:0]$9764 $1\o_ok$next[0:0]$9763 end sync always - update \o$next $0\o$next[63:0]$9776 - update \o_ok$next $0\o_ok$next[0:0]$9777 + update \o$next $0\o$next[63:0]$9760 + update \o_ok$next $0\o_ok$next[0:0]$9761 end - attribute \src "libresoc.v:171196.3-171214.6" - process $proc$libresoc.v:171196$9781 + attribute \src "libresoc.v:172504.3-172522.6" + process $proc$libresoc.v:172504$9765 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\fast1$11$next[63:0]$9783 $1\fast1$11$next[63:0]$9785 - assign $0\fast1_ok$next[0:0]$9782 $2\fast1_ok$next[0:0]$9786 - attribute \src "libresoc.v:171197.5-171197.29" + assign $0\fast1$11$next[63:0]$9767 $1\fast1$11$next[63:0]$9769 + assign $0\fast1_ok$next[0:0]$9766 $2\fast1_ok$next[0:0]$9770 + attribute \src "libresoc.v:172505.5-172505.29" switch \initial - attribute \src "libresoc.v:171197.9-171197.17" + attribute \src "libresoc.v:172505.9-172505.17" case 1'1 case end @@ -348475,41 +319845,41 @@ module \pipe2$35 case 2'-1 assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$9784 $1\fast1$11$next[63:0]$9785 } { \fast1_ok$41 \fast1$40 } + assign { $1\fast1_ok$next[0:0]$9768 $1\fast1$11$next[63:0]$9769 } { \fast1_ok$41 \fast1$40 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\fast1_ok$next[0:0]$9784 $1\fast1$11$next[63:0]$9785 } { \fast1_ok$41 \fast1$40 } + assign { $1\fast1_ok$next[0:0]$9768 $1\fast1$11$next[63:0]$9769 } { \fast1_ok$41 \fast1$40 } case - assign $1\fast1_ok$next[0:0]$9784 \fast1_ok - assign $1\fast1$11$next[63:0]$9785 \fast1$11 + assign $1\fast1_ok$next[0:0]$9768 \fast1_ok + assign $1\fast1$11$next[63:0]$9769 \fast1$11 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast1_ok$next[0:0]$9786 1'0 + assign $2\fast1_ok$next[0:0]$9770 1'0 case - assign $2\fast1_ok$next[0:0]$9786 $1\fast1_ok$next[0:0]$9784 + assign $2\fast1_ok$next[0:0]$9770 $1\fast1_ok$next[0:0]$9768 end sync always - update \fast1_ok$next $0\fast1_ok$next[0:0]$9782 - update \fast1$11$next $0\fast1$11$next[63:0]$9783 + update \fast1_ok$next $0\fast1_ok$next[0:0]$9766 + update \fast1$11$next $0\fast1$11$next[63:0]$9767 end - attribute \src "libresoc.v:171215.3-171233.6" - process $proc$libresoc.v:171215$9787 + attribute \src "libresoc.v:172523.3-172541.6" + process $proc$libresoc.v:172523$9771 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\fast2$12$next[63:0]$9789 $1\fast2$12$next[63:0]$9791 - assign $0\fast2_ok$next[0:0]$9788 $2\fast2_ok$next[0:0]$9792 - attribute \src "libresoc.v:171216.5-171216.29" + assign $0\fast2$12$next[63:0]$9773 $1\fast2$12$next[63:0]$9775 + assign $0\fast2_ok$next[0:0]$9772 $2\fast2_ok$next[0:0]$9776 + attribute \src "libresoc.v:172524.5-172524.29" switch \initial - attribute \src "libresoc.v:171216.9-171216.17" + attribute \src "libresoc.v:172524.9-172524.17" case 1'1 case end @@ -348519,41 +319889,41 @@ module \pipe2$35 case 2'-1 assign { } { } assign { } { } - assign { $1\fast2_ok$next[0:0]$9790 $1\fast2$12$next[63:0]$9791 } { \fast2_ok$43 \fast2$42 } + assign { $1\fast2_ok$next[0:0]$9774 $1\fast2$12$next[63:0]$9775 } { \fast2_ok$43 \fast2$42 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\fast2_ok$next[0:0]$9790 $1\fast2$12$next[63:0]$9791 } { \fast2_ok$43 \fast2$42 } + assign { $1\fast2_ok$next[0:0]$9774 $1\fast2$12$next[63:0]$9775 } { \fast2_ok$43 \fast2$42 } case - assign $1\fast2_ok$next[0:0]$9790 \fast2_ok - assign $1\fast2$12$next[63:0]$9791 \fast2$12 + assign $1\fast2_ok$next[0:0]$9774 \fast2_ok + assign $1\fast2$12$next[63:0]$9775 \fast2$12 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fast2_ok$next[0:0]$9792 1'0 + assign $2\fast2_ok$next[0:0]$9776 1'0 case - assign $2\fast2_ok$next[0:0]$9792 $1\fast2_ok$next[0:0]$9790 + assign $2\fast2_ok$next[0:0]$9776 $1\fast2_ok$next[0:0]$9774 end sync always - update \fast2_ok$next $0\fast2_ok$next[0:0]$9788 - update \fast2$12$next $0\fast2$12$next[63:0]$9789 + update \fast2_ok$next $0\fast2_ok$next[0:0]$9772 + update \fast2$12$next $0\fast2$12$next[63:0]$9773 end - attribute \src "libresoc.v:171234.3-171252.6" - process $proc$libresoc.v:171234$9793 + attribute \src "libresoc.v:172542.3-172560.6" + process $proc$libresoc.v:172542$9777 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\nia$next[63:0]$9794 $1\nia$next[63:0]$9796 + assign $0\nia$next[63:0]$9778 $1\nia$next[63:0]$9780 assign { } { } - assign $0\nia_ok$next[0:0]$9795 $2\nia_ok$next[0:0]$9798 - attribute \src "libresoc.v:171235.5-171235.29" + assign $0\nia_ok$next[0:0]$9779 $2\nia_ok$next[0:0]$9782 + attribute \src "libresoc.v:172543.5-172543.29" switch \initial - attribute \src "libresoc.v:171235.9-171235.17" + attribute \src "libresoc.v:172543.9-172543.17" case 1'1 case end @@ -348563,41 +319933,41 @@ module \pipe2$35 case 2'-1 assign { } { } assign { } { } - assign { $1\nia_ok$next[0:0]$9797 $1\nia$next[63:0]$9796 } { \nia_ok$45 \nia$44 } + assign { $1\nia_ok$next[0:0]$9781 $1\nia$next[63:0]$9780 } { \nia_ok$45 \nia$44 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\nia_ok$next[0:0]$9797 $1\nia$next[63:0]$9796 } { \nia_ok$45 \nia$44 } + assign { $1\nia_ok$next[0:0]$9781 $1\nia$next[63:0]$9780 } { \nia_ok$45 \nia$44 } case - assign $1\nia$next[63:0]$9796 \nia - assign $1\nia_ok$next[0:0]$9797 \nia_ok + assign $1\nia$next[63:0]$9780 \nia + assign $1\nia_ok$next[0:0]$9781 \nia_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\nia_ok$next[0:0]$9798 1'0 + assign $2\nia_ok$next[0:0]$9782 1'0 case - assign $2\nia_ok$next[0:0]$9798 $1\nia_ok$next[0:0]$9797 + assign $2\nia_ok$next[0:0]$9782 $1\nia_ok$next[0:0]$9781 end sync always - update \nia$next $0\nia$next[63:0]$9794 - update \nia_ok$next $0\nia_ok$next[0:0]$9795 + update \nia$next $0\nia$next[63:0]$9778 + update \nia_ok$next $0\nia_ok$next[0:0]$9779 end - attribute \src "libresoc.v:171253.3-171271.6" - process $proc$libresoc.v:171253$9799 + attribute \src "libresoc.v:172561.3-172579.6" + process $proc$libresoc.v:172561$9783 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\msr$next[63:0]$9800 $1\msr$next[63:0]$9802 + assign $0\msr$next[63:0]$9784 $1\msr$next[63:0]$9786 assign { } { } - assign $0\msr_ok$next[0:0]$9801 $2\msr_ok$next[0:0]$9804 - attribute \src "libresoc.v:171254.5-171254.29" + assign $0\msr_ok$next[0:0]$9785 $2\msr_ok$next[0:0]$9788 + attribute \src "libresoc.v:172562.5-172562.29" switch \initial - attribute \src "libresoc.v:171254.9-171254.17" + attribute \src "libresoc.v:172562.9-172562.17" case 1'1 case end @@ -348607,30 +319977,30 @@ module \pipe2$35 case 2'-1 assign { } { } assign { } { } - assign { $1\msr_ok$next[0:0]$9803 $1\msr$next[63:0]$9802 } { \msr_ok$47 \msr$46 } + assign { $1\msr_ok$next[0:0]$9787 $1\msr$next[63:0]$9786 } { \msr_ok$47 \msr$46 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\msr_ok$next[0:0]$9803 $1\msr$next[63:0]$9802 } { \msr_ok$47 \msr$46 } + assign { $1\msr_ok$next[0:0]$9787 $1\msr$next[63:0]$9786 } { \msr_ok$47 \msr$46 } case - assign $1\msr$next[63:0]$9802 \msr - assign $1\msr_ok$next[0:0]$9803 \msr_ok + assign $1\msr$next[63:0]$9786 \msr + assign $1\msr_ok$next[0:0]$9787 \msr_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr_ok$next[0:0]$9804 1'0 + assign $2\msr_ok$next[0:0]$9788 1'0 case - assign $2\msr_ok$next[0:0]$9804 $1\msr_ok$next[0:0]$9803 + assign $2\msr_ok$next[0:0]$9788 $1\msr_ok$next[0:0]$9787 end sync always - update \msr$next $0\msr$next[63:0]$9800 - update \msr_ok$next $0\msr_ok$next[0:0]$9801 + update \msr$next $0\msr$next[63:0]$9784 + update \msr_ok$next $0\msr_ok$next[0:0]$9785 end - connect \$26 $and$libresoc.v:171038$9715_Y + connect \$26 $and$libresoc.v:172346$9699_Y connect \p_ready_o \n_i_rdy_data connect \n_valid_o \r_busy connect { \msr_ok$47 \msr$46 } { \main_msr_ok \main_msr } @@ -348650,266 +320020,266 @@ module \pipe2$35 connect { \main_trap_op__ldst_exc \main_trap_op__trapaddr \main_trap_op__traptype \main_trap_op__is_32bit \main_trap_op__cia \main_trap_op__msr \main_trap_op__insn \main_trap_op__fn_unit \main_trap_op__insn_type } { \trap_op__ldst_exc \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } connect \main_muxid \muxid end -attribute \src "libresoc.v:171294.1-172797.10" +attribute \src "libresoc.v:172602.1-174105.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_end" attribute \generator "nMigen" module \pipe_end - attribute \src "libresoc.v:172635.3-172653.6" - wire width 4 $0\cr_a$next[3:0]$9895 - attribute \src "libresoc.v:172454.3-172455.25" + attribute \src "libresoc.v:173943.3-173961.6" + wire width 4 $0\cr_a$next[3:0]$9879 + attribute \src "libresoc.v:173762.3-173763.25" wire width 4 $0\cr_a[3:0] - attribute \src "libresoc.v:172635.3-172653.6" - wire $0\cr_a_ok$next[0:0]$9896 - attribute \src "libresoc.v:172456.3-172457.31" + attribute \src "libresoc.v:173943.3-173961.6" + wire $0\cr_a_ok$next[0:0]$9880 + attribute \src "libresoc.v:173764.3-173765.31" wire $0\cr_a_ok[0:0] - attribute \src "libresoc.v:171295.7-171295.20" + attribute \src "libresoc.v:172603.7-172603.20" wire $0\initial[0:0] - attribute \src "libresoc.v:172723.3-172764.6" - wire width 4 $0\logical_op__data_len$18$next[3:0]$9920 - attribute \src "libresoc.v:172494.3-172495.65" - wire width 4 $0\logical_op__data_len$18[3:0]$9882 - attribute \src "libresoc.v:171336.13-171336.45" - wire width 4 $0\logical_op__data_len$18[3:0]$9966 - attribute \src "libresoc.v:172723.3-172764.6" - wire width 14 $0\logical_op__fn_unit$3$next[13:0]$9921 - attribute \src "libresoc.v:172464.3-172465.61" - wire width 14 $0\logical_op__fn_unit$3[13:0]$9852 - attribute \src "libresoc.v:171375.14-171375.48" - wire width 14 $0\logical_op__fn_unit$3[13:0]$9968 - attribute \src "libresoc.v:172723.3-172764.6" - wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$9922 - attribute \src "libresoc.v:172466.3-172467.75" - wire width 64 $0\logical_op__imm_data__data$4[63:0]$9854 - attribute \src "libresoc.v:171399.14-171399.67" - wire width 64 $0\logical_op__imm_data__data$4[63:0]$9970 - attribute \src "libresoc.v:172723.3-172764.6" - wire $0\logical_op__imm_data__ok$5$next[0:0]$9923 - attribute \src "libresoc.v:172468.3-172469.71" - wire $0\logical_op__imm_data__ok$5[0:0]$9856 - attribute \src "libresoc.v:171408.7-171408.42" - wire $0\logical_op__imm_data__ok$5[0:0]$9972 - attribute \src "libresoc.v:172723.3-172764.6" - wire width 2 $0\logical_op__input_carry$12$next[1:0]$9924 - attribute \src "libresoc.v:172482.3-172483.71" - wire width 2 $0\logical_op__input_carry$12[1:0]$9870 - attribute \src "libresoc.v:171425.13-171425.48" - wire width 2 $0\logical_op__input_carry$12[1:0]$9974 - attribute \src "libresoc.v:172723.3-172764.6" - wire width 32 $0\logical_op__insn$19$next[31:0]$9925 - attribute \src "libresoc.v:172496.3-172497.57" - wire width 32 $0\logical_op__insn$19[31:0]$9884 - attribute \src "libresoc.v:171438.14-171438.43" - wire width 32 $0\logical_op__insn$19[31:0]$9976 - attribute \src "libresoc.v:172723.3-172764.6" - wire width 7 $0\logical_op__insn_type$2$next[6:0]$9926 - attribute \src "libresoc.v:172462.3-172463.65" - wire width 7 $0\logical_op__insn_type$2[6:0]$9850 - attribute \src "libresoc.v:171597.13-171597.46" - wire width 7 $0\logical_op__insn_type$2[6:0]$9978 - attribute \src "libresoc.v:172723.3-172764.6" - wire $0\logical_op__invert_in$10$next[0:0]$9927 - attribute \src "libresoc.v:172478.3-172479.67" - wire $0\logical_op__invert_in$10[0:0]$9866 - attribute \src "libresoc.v:171681.7-171681.40" - wire $0\logical_op__invert_in$10[0:0]$9980 - attribute \src "libresoc.v:172723.3-172764.6" - wire $0\logical_op__invert_out$13$next[0:0]$9928 - attribute \src "libresoc.v:172484.3-172485.69" - wire $0\logical_op__invert_out$13[0:0]$9872 - attribute \src "libresoc.v:171690.7-171690.41" - wire $0\logical_op__invert_out$13[0:0]$9982 - attribute \src "libresoc.v:172723.3-172764.6" - wire $0\logical_op__is_32bit$16$next[0:0]$9929 - attribute \src "libresoc.v:172490.3-172491.65" - wire $0\logical_op__is_32bit$16[0:0]$9878 - attribute \src "libresoc.v:171699.7-171699.39" - wire $0\logical_op__is_32bit$16[0:0]$9984 - attribute \src "libresoc.v:172723.3-172764.6" - wire $0\logical_op__is_signed$17$next[0:0]$9930 - attribute \src "libresoc.v:172492.3-172493.67" - wire $0\logical_op__is_signed$17[0:0]$9880 - attribute \src "libresoc.v:171708.7-171708.40" - wire $0\logical_op__is_signed$17[0:0]$9986 - attribute \src "libresoc.v:172723.3-172764.6" - wire $0\logical_op__oe__oe$8$next[0:0]$9931 - attribute \src "libresoc.v:172474.3-172475.59" - wire $0\logical_op__oe__oe$8[0:0]$9862 - attribute \src "libresoc.v:171717.7-171717.36" - wire $0\logical_op__oe__oe$8[0:0]$9988 - attribute \src "libresoc.v:172723.3-172764.6" - wire $0\logical_op__oe__ok$9$next[0:0]$9932 - attribute \src "libresoc.v:172476.3-172477.59" - wire $0\logical_op__oe__ok$9[0:0]$9864 - attribute \src "libresoc.v:171728.7-171728.36" - wire $0\logical_op__oe__ok$9[0:0]$9990 - attribute \src "libresoc.v:172723.3-172764.6" - wire $0\logical_op__output_carry$15$next[0:0]$9933 - attribute \src "libresoc.v:172488.3-172489.73" - wire $0\logical_op__output_carry$15[0:0]$9876 - attribute \src "libresoc.v:171735.7-171735.43" - wire $0\logical_op__output_carry$15[0:0]$9992 - attribute \src "libresoc.v:172723.3-172764.6" - wire $0\logical_op__rc__ok$7$next[0:0]$9934 - attribute \src "libresoc.v:172472.3-172473.59" - wire $0\logical_op__rc__ok$7[0:0]$9860 - attribute \src "libresoc.v:171744.7-171744.36" - wire $0\logical_op__rc__ok$7[0:0]$9994 - attribute \src "libresoc.v:172723.3-172764.6" - wire $0\logical_op__rc__rc$6$next[0:0]$9935 - attribute \src "libresoc.v:172470.3-172471.59" - wire $0\logical_op__rc__rc$6[0:0]$9858 - attribute \src "libresoc.v:171753.7-171753.36" - wire $0\logical_op__rc__rc$6[0:0]$9996 - attribute \src "libresoc.v:172723.3-172764.6" - wire $0\logical_op__write_cr0$14$next[0:0]$9936 - attribute \src "libresoc.v:172486.3-172487.67" - wire $0\logical_op__write_cr0$14[0:0]$9874 - attribute \src "libresoc.v:171762.7-171762.40" - wire $0\logical_op__write_cr0$14[0:0]$9998 - attribute \src "libresoc.v:172723.3-172764.6" - wire $0\logical_op__zero_a$11$next[0:0]$9937 - attribute \src "libresoc.v:171771.7-171771.37" - wire $0\logical_op__zero_a$11[0:0]$10000 - attribute \src "libresoc.v:172480.3-172481.61" - wire $0\logical_op__zero_a$11[0:0]$9868 - attribute \src "libresoc.v:172710.3-172722.6" - wire width 2 $0\muxid$1$next[1:0]$9917 - attribute \src "libresoc.v:171780.13-171780.29" - wire width 2 $0\muxid$1[1:0]$10002 - attribute \src "libresoc.v:172498.3-172499.33" - wire width 2 $0\muxid$1[1:0]$9886 - attribute \src "libresoc.v:172616.3-172634.6" - wire width 64 $0\o$next[63:0]$9889 - attribute \src "libresoc.v:172458.3-172459.19" + attribute \src "libresoc.v:174031.3-174072.6" + wire width 4 $0\logical_op__data_len$18$next[3:0]$9904 + attribute \src "libresoc.v:173802.3-173803.65" + wire width 4 $0\logical_op__data_len$18[3:0]$9866 + attribute \src "libresoc.v:172644.13-172644.45" + wire width 4 $0\logical_op__data_len$18[3:0]$9950 + attribute \src "libresoc.v:174031.3-174072.6" + wire width 14 $0\logical_op__fn_unit$3$next[13:0]$9905 + attribute \src "libresoc.v:173772.3-173773.61" + wire width 14 $0\logical_op__fn_unit$3[13:0]$9836 + attribute \src "libresoc.v:172683.14-172683.48" + wire width 14 $0\logical_op__fn_unit$3[13:0]$9952 + attribute \src "libresoc.v:174031.3-174072.6" + wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$9906 + attribute \src "libresoc.v:173774.3-173775.75" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$9838 + attribute \src "libresoc.v:172707.14-172707.67" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$9954 + attribute \src "libresoc.v:174031.3-174072.6" + wire $0\logical_op__imm_data__ok$5$next[0:0]$9907 + attribute \src "libresoc.v:173776.3-173777.71" + wire $0\logical_op__imm_data__ok$5[0:0]$9840 + attribute \src "libresoc.v:172716.7-172716.42" + wire $0\logical_op__imm_data__ok$5[0:0]$9956 + attribute \src "libresoc.v:174031.3-174072.6" + wire width 2 $0\logical_op__input_carry$12$next[1:0]$9908 + attribute \src "libresoc.v:173790.3-173791.71" + wire width 2 $0\logical_op__input_carry$12[1:0]$9854 + attribute \src "libresoc.v:172733.13-172733.48" + wire width 2 $0\logical_op__input_carry$12[1:0]$9958 + attribute \src "libresoc.v:174031.3-174072.6" + wire width 32 $0\logical_op__insn$19$next[31:0]$9909 + attribute \src "libresoc.v:173804.3-173805.57" + wire width 32 $0\logical_op__insn$19[31:0]$9868 + attribute \src "libresoc.v:172746.14-172746.43" + wire width 32 $0\logical_op__insn$19[31:0]$9960 + attribute \src "libresoc.v:174031.3-174072.6" + wire width 7 $0\logical_op__insn_type$2$next[6:0]$9910 + attribute \src "libresoc.v:173770.3-173771.65" + wire width 7 $0\logical_op__insn_type$2[6:0]$9834 + attribute \src "libresoc.v:172905.13-172905.46" + wire width 7 $0\logical_op__insn_type$2[6:0]$9962 + attribute \src "libresoc.v:174031.3-174072.6" + wire $0\logical_op__invert_in$10$next[0:0]$9911 + attribute \src "libresoc.v:173786.3-173787.67" + wire $0\logical_op__invert_in$10[0:0]$9850 + attribute \src "libresoc.v:172989.7-172989.40" + wire $0\logical_op__invert_in$10[0:0]$9964 + attribute \src "libresoc.v:174031.3-174072.6" + wire $0\logical_op__invert_out$13$next[0:0]$9912 + attribute \src "libresoc.v:173792.3-173793.69" + wire $0\logical_op__invert_out$13[0:0]$9856 + attribute \src "libresoc.v:172998.7-172998.41" + wire $0\logical_op__invert_out$13[0:0]$9966 + attribute \src "libresoc.v:174031.3-174072.6" + wire $0\logical_op__is_32bit$16$next[0:0]$9913 + attribute \src "libresoc.v:173798.3-173799.65" + wire $0\logical_op__is_32bit$16[0:0]$9862 + attribute \src "libresoc.v:173007.7-173007.39" + wire $0\logical_op__is_32bit$16[0:0]$9968 + attribute \src "libresoc.v:174031.3-174072.6" + wire $0\logical_op__is_signed$17$next[0:0]$9914 + attribute \src "libresoc.v:173800.3-173801.67" + wire $0\logical_op__is_signed$17[0:0]$9864 + attribute \src "libresoc.v:173016.7-173016.40" + wire $0\logical_op__is_signed$17[0:0]$9970 + attribute \src "libresoc.v:174031.3-174072.6" + wire $0\logical_op__oe__oe$8$next[0:0]$9915 + attribute \src "libresoc.v:173782.3-173783.59" + wire $0\logical_op__oe__oe$8[0:0]$9846 + attribute \src "libresoc.v:173025.7-173025.36" + wire $0\logical_op__oe__oe$8[0:0]$9972 + attribute \src "libresoc.v:174031.3-174072.6" + wire $0\logical_op__oe__ok$9$next[0:0]$9916 + attribute \src "libresoc.v:173784.3-173785.59" + wire $0\logical_op__oe__ok$9[0:0]$9848 + attribute \src "libresoc.v:173036.7-173036.36" + wire $0\logical_op__oe__ok$9[0:0]$9974 + attribute \src "libresoc.v:174031.3-174072.6" + wire $0\logical_op__output_carry$15$next[0:0]$9917 + attribute \src "libresoc.v:173796.3-173797.73" + wire $0\logical_op__output_carry$15[0:0]$9860 + attribute \src "libresoc.v:173043.7-173043.43" + wire $0\logical_op__output_carry$15[0:0]$9976 + attribute \src "libresoc.v:174031.3-174072.6" + wire $0\logical_op__rc__ok$7$next[0:0]$9918 + attribute \src "libresoc.v:173780.3-173781.59" + wire $0\logical_op__rc__ok$7[0:0]$9844 + attribute \src "libresoc.v:173052.7-173052.36" + wire $0\logical_op__rc__ok$7[0:0]$9978 + attribute \src "libresoc.v:174031.3-174072.6" + wire $0\logical_op__rc__rc$6$next[0:0]$9919 + attribute \src "libresoc.v:173778.3-173779.59" + wire $0\logical_op__rc__rc$6[0:0]$9842 + attribute \src "libresoc.v:173061.7-173061.36" + wire $0\logical_op__rc__rc$6[0:0]$9980 + attribute \src "libresoc.v:174031.3-174072.6" + wire $0\logical_op__write_cr0$14$next[0:0]$9920 + attribute \src "libresoc.v:173794.3-173795.67" + wire $0\logical_op__write_cr0$14[0:0]$9858 + attribute \src "libresoc.v:173070.7-173070.40" + wire $0\logical_op__write_cr0$14[0:0]$9982 + attribute \src "libresoc.v:174031.3-174072.6" + wire $0\logical_op__zero_a$11$next[0:0]$9921 + attribute \src "libresoc.v:173788.3-173789.61" + wire $0\logical_op__zero_a$11[0:0]$9852 + attribute \src "libresoc.v:173079.7-173079.37" + wire $0\logical_op__zero_a$11[0:0]$9984 + attribute \src "libresoc.v:174018.3-174030.6" + wire width 2 $0\muxid$1$next[1:0]$9901 + attribute \src "libresoc.v:173806.3-173807.33" + wire width 2 $0\muxid$1[1:0]$9870 + attribute \src "libresoc.v:173088.13-173088.29" + wire width 2 $0\muxid$1[1:0]$9986 + attribute \src "libresoc.v:173924.3-173942.6" + wire width 64 $0\o$next[63:0]$9873 + attribute \src "libresoc.v:173766.3-173767.19" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:172616.3-172634.6" - wire $0\o_ok$next[0:0]$9890 - attribute \src "libresoc.v:172460.3-172461.25" + attribute \src "libresoc.v:173924.3-173942.6" + wire $0\o_ok$next[0:0]$9874 + attribute \src "libresoc.v:173768.3-173769.25" wire $0\o_ok[0:0] - attribute \src "libresoc.v:172692.3-172709.6" - wire $0\r_busy$next[0:0]$9913 - attribute \src "libresoc.v:172500.3-172501.29" + attribute \src "libresoc.v:174000.3-174017.6" + wire $0\r_busy$next[0:0]$9897 + attribute \src "libresoc.v:173808.3-173809.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:172654.3-172672.6" - wire width 2 $0\xer_ov$next[1:0]$9901 - attribute \src "libresoc.v:172450.3-172451.29" + attribute \src "libresoc.v:173962.3-173980.6" + wire width 2 $0\xer_ov$next[1:0]$9885 + attribute \src "libresoc.v:173758.3-173759.29" wire width 2 $0\xer_ov[1:0] - attribute \src "libresoc.v:172654.3-172672.6" - wire $0\xer_ov_ok$next[0:0]$9902 - attribute \src "libresoc.v:172452.3-172453.35" + attribute \src "libresoc.v:173962.3-173980.6" + wire $0\xer_ov_ok$next[0:0]$9886 + attribute \src "libresoc.v:173760.3-173761.35" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:172673.3-172691.6" - wire $0\xer_so$20$next[0:0]$9908 - attribute \src "libresoc.v:172431.7-172431.25" - wire $0\xer_so$20[0:0]$10009 - attribute \src "libresoc.v:172446.3-172447.37" - wire $0\xer_so$20[0:0]$9841 - attribute \src "libresoc.v:172673.3-172691.6" - wire $0\xer_so_ok$next[0:0]$9907 - attribute \src "libresoc.v:172448.3-172449.35" + attribute \src "libresoc.v:173981.3-173999.6" + wire $0\xer_so$20$next[0:0]$9892 + attribute \src "libresoc.v:173754.3-173755.37" + wire $0\xer_so$20[0:0]$9825 + attribute \src "libresoc.v:173739.7-173739.25" + wire $0\xer_so$20[0:0]$9993 + attribute \src "libresoc.v:173981.3-173999.6" + wire $0\xer_so_ok$next[0:0]$9891 + attribute \src "libresoc.v:173756.3-173757.35" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:172635.3-172653.6" - wire width 4 $1\cr_a$next[3:0]$9897 - attribute \src "libresoc.v:171304.13-171304.24" + attribute \src "libresoc.v:173943.3-173961.6" + wire width 4 $1\cr_a$next[3:0]$9881 + attribute \src "libresoc.v:172612.13-172612.24" wire width 4 $1\cr_a[3:0] - attribute \src "libresoc.v:172635.3-172653.6" - wire $1\cr_a_ok$next[0:0]$9898 - attribute \src "libresoc.v:171313.7-171313.21" + attribute \src "libresoc.v:173943.3-173961.6" + wire $1\cr_a_ok$next[0:0]$9882 + attribute \src "libresoc.v:172621.7-172621.21" wire $1\cr_a_ok[0:0] - attribute \src "libresoc.v:172723.3-172764.6" - wire width 4 $1\logical_op__data_len$18$next[3:0]$9938 - attribute \src "libresoc.v:172723.3-172764.6" - wire width 14 $1\logical_op__fn_unit$3$next[13:0]$9939 - attribute \src "libresoc.v:172723.3-172764.6" - wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$9940 - attribute \src "libresoc.v:172723.3-172764.6" - wire $1\logical_op__imm_data__ok$5$next[0:0]$9941 - attribute \src "libresoc.v:172723.3-172764.6" - wire width 2 $1\logical_op__input_carry$12$next[1:0]$9942 - attribute \src "libresoc.v:172723.3-172764.6" - wire width 32 $1\logical_op__insn$19$next[31:0]$9943 - attribute \src "libresoc.v:172723.3-172764.6" - wire width 7 $1\logical_op__insn_type$2$next[6:0]$9944 - attribute \src "libresoc.v:172723.3-172764.6" - wire $1\logical_op__invert_in$10$next[0:0]$9945 - attribute \src "libresoc.v:172723.3-172764.6" - wire $1\logical_op__invert_out$13$next[0:0]$9946 - attribute \src "libresoc.v:172723.3-172764.6" - wire $1\logical_op__is_32bit$16$next[0:0]$9947 - attribute \src "libresoc.v:172723.3-172764.6" - wire $1\logical_op__is_signed$17$next[0:0]$9948 - attribute \src "libresoc.v:172723.3-172764.6" - wire $1\logical_op__oe__oe$8$next[0:0]$9949 - attribute \src "libresoc.v:172723.3-172764.6" - wire $1\logical_op__oe__ok$9$next[0:0]$9950 - attribute \src "libresoc.v:172723.3-172764.6" - wire $1\logical_op__output_carry$15$next[0:0]$9951 - attribute \src "libresoc.v:172723.3-172764.6" - wire $1\logical_op__rc__ok$7$next[0:0]$9952 - attribute \src "libresoc.v:172723.3-172764.6" - wire $1\logical_op__rc__rc$6$next[0:0]$9953 - attribute \src "libresoc.v:172723.3-172764.6" - wire $1\logical_op__write_cr0$14$next[0:0]$9954 - attribute \src "libresoc.v:172723.3-172764.6" - wire $1\logical_op__zero_a$11$next[0:0]$9955 - attribute \src "libresoc.v:172710.3-172722.6" - wire width 2 $1\muxid$1$next[1:0]$9918 - attribute \src "libresoc.v:172616.3-172634.6" - wire width 64 $1\o$next[63:0]$9891 - attribute \src "libresoc.v:171793.14-171793.38" + attribute \src "libresoc.v:174031.3-174072.6" + wire width 4 $1\logical_op__data_len$18$next[3:0]$9922 + attribute \src "libresoc.v:174031.3-174072.6" + wire width 14 $1\logical_op__fn_unit$3$next[13:0]$9923 + attribute \src "libresoc.v:174031.3-174072.6" + wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$9924 + attribute \src "libresoc.v:174031.3-174072.6" + wire $1\logical_op__imm_data__ok$5$next[0:0]$9925 + attribute \src "libresoc.v:174031.3-174072.6" + wire width 2 $1\logical_op__input_carry$12$next[1:0]$9926 + attribute \src "libresoc.v:174031.3-174072.6" + wire width 32 $1\logical_op__insn$19$next[31:0]$9927 + attribute \src "libresoc.v:174031.3-174072.6" + wire width 7 $1\logical_op__insn_type$2$next[6:0]$9928 + attribute \src "libresoc.v:174031.3-174072.6" + wire $1\logical_op__invert_in$10$next[0:0]$9929 + attribute \src "libresoc.v:174031.3-174072.6" + wire $1\logical_op__invert_out$13$next[0:0]$9930 + attribute \src "libresoc.v:174031.3-174072.6" + wire $1\logical_op__is_32bit$16$next[0:0]$9931 + attribute \src "libresoc.v:174031.3-174072.6" + wire $1\logical_op__is_signed$17$next[0:0]$9932 + attribute \src "libresoc.v:174031.3-174072.6" + wire $1\logical_op__oe__oe$8$next[0:0]$9933 + attribute \src "libresoc.v:174031.3-174072.6" + wire $1\logical_op__oe__ok$9$next[0:0]$9934 + attribute \src "libresoc.v:174031.3-174072.6" + wire $1\logical_op__output_carry$15$next[0:0]$9935 + attribute \src "libresoc.v:174031.3-174072.6" + wire $1\logical_op__rc__ok$7$next[0:0]$9936 + attribute \src "libresoc.v:174031.3-174072.6" + wire $1\logical_op__rc__rc$6$next[0:0]$9937 + attribute \src "libresoc.v:174031.3-174072.6" + wire $1\logical_op__write_cr0$14$next[0:0]$9938 + attribute \src "libresoc.v:174031.3-174072.6" + wire $1\logical_op__zero_a$11$next[0:0]$9939 + attribute \src "libresoc.v:174018.3-174030.6" + wire width 2 $1\muxid$1$next[1:0]$9902 + attribute \src "libresoc.v:173924.3-173942.6" + wire width 64 $1\o$next[63:0]$9875 + attribute \src "libresoc.v:173101.14-173101.38" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:172616.3-172634.6" - wire $1\o_ok$next[0:0]$9892 - attribute \src "libresoc.v:171800.7-171800.18" + attribute \src "libresoc.v:173924.3-173942.6" + wire $1\o_ok$next[0:0]$9876 + attribute \src "libresoc.v:173108.7-173108.18" wire $1\o_ok[0:0] - attribute \src "libresoc.v:172692.3-172709.6" - wire $1\r_busy$next[0:0]$9914 - attribute \src "libresoc.v:172396.7-172396.20" + attribute \src "libresoc.v:174000.3-174017.6" + wire $1\r_busy$next[0:0]$9898 + attribute \src "libresoc.v:173704.7-173704.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:172654.3-172672.6" - wire width 2 $1\xer_ov$next[1:0]$9903 - attribute \src "libresoc.v:172411.13-172411.26" + attribute \src "libresoc.v:173962.3-173980.6" + wire width 2 $1\xer_ov$next[1:0]$9887 + attribute \src "libresoc.v:173719.13-173719.26" wire width 2 $1\xer_ov[1:0] - attribute \src "libresoc.v:172654.3-172672.6" - wire $1\xer_ov_ok$next[0:0]$9904 - attribute \src "libresoc.v:172418.7-172418.23" + attribute \src "libresoc.v:173962.3-173980.6" + wire $1\xer_ov_ok$next[0:0]$9888 + attribute \src "libresoc.v:173726.7-173726.23" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:172673.3-172691.6" - wire $1\xer_so$20$next[0:0]$9910 - attribute \src "libresoc.v:172673.3-172691.6" - wire $1\xer_so_ok$next[0:0]$9909 - attribute \src "libresoc.v:172436.7-172436.23" + attribute \src "libresoc.v:173981.3-173999.6" + wire $1\xer_so$20$next[0:0]$9894 + attribute \src "libresoc.v:173981.3-173999.6" + wire $1\xer_so_ok$next[0:0]$9893 + attribute \src "libresoc.v:173744.7-173744.23" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:172635.3-172653.6" - wire $2\cr_a_ok$next[0:0]$9899 - attribute \src "libresoc.v:172723.3-172764.6" - wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$9956 - attribute \src "libresoc.v:172723.3-172764.6" - wire $2\logical_op__imm_data__ok$5$next[0:0]$9957 - attribute \src "libresoc.v:172723.3-172764.6" - wire $2\logical_op__oe__oe$8$next[0:0]$9958 - attribute \src "libresoc.v:172723.3-172764.6" - wire $2\logical_op__oe__ok$9$next[0:0]$9959 - attribute \src "libresoc.v:172723.3-172764.6" - wire $2\logical_op__rc__ok$7$next[0:0]$9960 - attribute \src "libresoc.v:172723.3-172764.6" - wire $2\logical_op__rc__rc$6$next[0:0]$9961 - attribute \src "libresoc.v:172616.3-172634.6" - wire $2\o_ok$next[0:0]$9893 - attribute \src "libresoc.v:172692.3-172709.6" - wire $2\r_busy$next[0:0]$9915 - attribute \src "libresoc.v:172654.3-172672.6" - wire $2\xer_ov_ok$next[0:0]$9905 - attribute \src "libresoc.v:172673.3-172691.6" - wire $2\xer_so_ok$next[0:0]$9911 - attribute \src "libresoc.v:172445.18-172445.118" - wire $and$libresoc.v:172445$9839_Y + attribute \src "libresoc.v:173943.3-173961.6" + wire $2\cr_a_ok$next[0:0]$9883 + attribute \src "libresoc.v:174031.3-174072.6" + wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$9940 + attribute \src "libresoc.v:174031.3-174072.6" + wire $2\logical_op__imm_data__ok$5$next[0:0]$9941 + attribute \src "libresoc.v:174031.3-174072.6" + wire $2\logical_op__oe__oe$8$next[0:0]$9942 + attribute \src "libresoc.v:174031.3-174072.6" + wire $2\logical_op__oe__ok$9$next[0:0]$9943 + attribute \src "libresoc.v:174031.3-174072.6" + wire $2\logical_op__rc__ok$7$next[0:0]$9944 + attribute \src "libresoc.v:174031.3-174072.6" + wire $2\logical_op__rc__rc$6$next[0:0]$9945 + attribute \src "libresoc.v:173924.3-173942.6" + wire $2\o_ok$next[0:0]$9877 + attribute \src "libresoc.v:174000.3-174017.6" + wire $2\r_busy$next[0:0]$9899 + attribute \src "libresoc.v:173962.3-173980.6" + wire $2\xer_ov_ok$next[0:0]$9889 + attribute \src "libresoc.v:173981.3-173999.6" + wire $2\xer_so_ok$next[0:0]$9895 + attribute \src "libresoc.v:173753.18-173753.118" + wire $and$libresoc.v:173753$9823_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 62 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 4 output 56 \cr_a @@ -348939,7 +320309,7 @@ module \pipe_end wire input 27 \dividend_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" wire input 26 \divisor_neg - attribute \src "libresoc.v:171295.7-171295.15" + attribute \src "libresoc.v:172603.7-172603.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 21 \logical_op__data_len @@ -350030,7 +321400,7 @@ module \pipe_end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \xer_so_ok$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:172445$9839 + cell $and $and$libresoc.v:173753$9823 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -350038,16 +321408,16 @@ module \pipe_end parameter \Y_WIDTH 1 connect \A \p_valid_i$73 connect \B \p_ready_o - connect \Y $and$libresoc.v:172445$9839_Y + connect \Y $and$libresoc.v:173753$9823_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:172502.10-172505.4" + attribute \src "libresoc.v:173810.10-173813.4" cell \n$82 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:172506.15-172558.4" + attribute \src "libresoc.v:173814.15-173866.4" cell \output$83 \output connect \cr_a \output_cr_a connect \cr_a$22 \output_cr_a$62 @@ -350102,7 +321472,7 @@ module \pipe_end connect \xer_so_ok \output_xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:172559.16-172611.4" + attribute \src "libresoc.v:173867.16-173919.4" cell \output_stage \output_stage connect \div_by_zero \output_stage_div_by_zero connect \dive_abs_ov32 \output_stage_dive_abs_ov32 @@ -350157,451 +321527,451 @@ module \pipe_end connect \xer_so$20 \output_stage_xer_so$40 end attribute \module_not_derived 1 - attribute \src "libresoc.v:172612.10-172615.4" + attribute \src "libresoc.v:173920.10-173923.4" cell \p$81 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:171295.7-171295.20" - process $proc$libresoc.v:171295$9962 + attribute \src "libresoc.v:172603.7-172603.20" + process $proc$libresoc.v:172603$9946 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:171304.13-171304.24" - process $proc$libresoc.v:171304$9963 + attribute \src "libresoc.v:172612.13-172612.24" + process $proc$libresoc.v:172612$9947 assign { } { } assign $1\cr_a[3:0] 4'0000 sync always sync init update \cr_a $1\cr_a[3:0] end - attribute \src "libresoc.v:171313.7-171313.21" - process $proc$libresoc.v:171313$9964 + attribute \src "libresoc.v:172621.7-172621.21" + process $proc$libresoc.v:172621$9948 assign { } { } assign $1\cr_a_ok[0:0] 1'0 sync always sync init update \cr_a_ok $1\cr_a_ok[0:0] end - attribute \src "libresoc.v:171336.13-171336.45" - process $proc$libresoc.v:171336$9965 + attribute \src "libresoc.v:172644.13-172644.45" + process $proc$libresoc.v:172644$9949 assign { } { } - assign $0\logical_op__data_len$18[3:0]$9966 4'0000 + assign $0\logical_op__data_len$18[3:0]$9950 4'0000 sync always sync init - update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9966 + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9950 end - attribute \src "libresoc.v:171375.14-171375.48" - process $proc$libresoc.v:171375$9967 + attribute \src "libresoc.v:172683.14-172683.48" + process $proc$libresoc.v:172683$9951 assign { } { } - assign $0\logical_op__fn_unit$3[13:0]$9968 14'00000000000000 + assign $0\logical_op__fn_unit$3[13:0]$9952 14'00000000000000 sync always sync init - update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$9968 + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$9952 end - attribute \src "libresoc.v:171399.14-171399.67" - process $proc$libresoc.v:171399$9969 + attribute \src "libresoc.v:172707.14-172707.67" + process $proc$libresoc.v:172707$9953 assign { } { } - assign $0\logical_op__imm_data__data$4[63:0]$9970 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\logical_op__imm_data__data$4[63:0]$9954 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9970 + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9954 end - attribute \src "libresoc.v:171408.7-171408.42" - process $proc$libresoc.v:171408$9971 + attribute \src "libresoc.v:172716.7-172716.42" + process $proc$libresoc.v:172716$9955 assign { } { } - assign $0\logical_op__imm_data__ok$5[0:0]$9972 1'0 + assign $0\logical_op__imm_data__ok$5[0:0]$9956 1'0 sync always sync init - update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9972 + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9956 end - attribute \src "libresoc.v:171425.13-171425.48" - process $proc$libresoc.v:171425$9973 + attribute \src "libresoc.v:172733.13-172733.48" + process $proc$libresoc.v:172733$9957 assign { } { } - assign $0\logical_op__input_carry$12[1:0]$9974 2'00 + assign $0\logical_op__input_carry$12[1:0]$9958 2'00 sync always sync init - update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9974 + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9958 end - attribute \src "libresoc.v:171438.14-171438.43" - process $proc$libresoc.v:171438$9975 + attribute \src "libresoc.v:172746.14-172746.43" + process $proc$libresoc.v:172746$9959 assign { } { } - assign $0\logical_op__insn$19[31:0]$9976 0 + assign $0\logical_op__insn$19[31:0]$9960 0 sync always sync init - update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9976 + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9960 end - attribute \src "libresoc.v:171597.13-171597.46" - process $proc$libresoc.v:171597$9977 + attribute \src "libresoc.v:172905.13-172905.46" + process $proc$libresoc.v:172905$9961 assign { } { } - assign $0\logical_op__insn_type$2[6:0]$9978 7'0000000 + assign $0\logical_op__insn_type$2[6:0]$9962 7'0000000 sync always sync init - update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9978 + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9962 end - attribute \src "libresoc.v:171681.7-171681.40" - process $proc$libresoc.v:171681$9979 + attribute \src "libresoc.v:172989.7-172989.40" + process $proc$libresoc.v:172989$9963 assign { } { } - assign $0\logical_op__invert_in$10[0:0]$9980 1'0 + assign $0\logical_op__invert_in$10[0:0]$9964 1'0 sync always sync init - update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9980 + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9964 end - attribute \src "libresoc.v:171690.7-171690.41" - process $proc$libresoc.v:171690$9981 + attribute \src "libresoc.v:172998.7-172998.41" + process $proc$libresoc.v:172998$9965 assign { } { } - assign $0\logical_op__invert_out$13[0:0]$9982 1'0 + assign $0\logical_op__invert_out$13[0:0]$9966 1'0 sync always sync init - update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9982 + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9966 end - attribute \src "libresoc.v:171699.7-171699.39" - process $proc$libresoc.v:171699$9983 + attribute \src "libresoc.v:173007.7-173007.39" + process $proc$libresoc.v:173007$9967 assign { } { } - assign $0\logical_op__is_32bit$16[0:0]$9984 1'0 + assign $0\logical_op__is_32bit$16[0:0]$9968 1'0 sync always sync init - update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9984 + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9968 end - attribute \src "libresoc.v:171708.7-171708.40" - process $proc$libresoc.v:171708$9985 + attribute \src "libresoc.v:173016.7-173016.40" + process $proc$libresoc.v:173016$9969 assign { } { } - assign $0\logical_op__is_signed$17[0:0]$9986 1'0 + assign $0\logical_op__is_signed$17[0:0]$9970 1'0 sync always sync init - update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9986 + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9970 end - attribute \src "libresoc.v:171717.7-171717.36" - process $proc$libresoc.v:171717$9987 + attribute \src "libresoc.v:173025.7-173025.36" + process $proc$libresoc.v:173025$9971 assign { } { } - assign $0\logical_op__oe__oe$8[0:0]$9988 1'0 + assign $0\logical_op__oe__oe$8[0:0]$9972 1'0 sync always sync init - update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9988 + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9972 end - attribute \src "libresoc.v:171728.7-171728.36" - process $proc$libresoc.v:171728$9989 + attribute \src "libresoc.v:173036.7-173036.36" + process $proc$libresoc.v:173036$9973 assign { } { } - assign $0\logical_op__oe__ok$9[0:0]$9990 1'0 + assign $0\logical_op__oe__ok$9[0:0]$9974 1'0 sync always sync init - update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9990 + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9974 end - attribute \src "libresoc.v:171735.7-171735.43" - process $proc$libresoc.v:171735$9991 + attribute \src "libresoc.v:173043.7-173043.43" + process $proc$libresoc.v:173043$9975 assign { } { } - assign $0\logical_op__output_carry$15[0:0]$9992 1'0 + assign $0\logical_op__output_carry$15[0:0]$9976 1'0 sync always sync init - update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9992 + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9976 end - attribute \src "libresoc.v:171744.7-171744.36" - process $proc$libresoc.v:171744$9993 + attribute \src "libresoc.v:173052.7-173052.36" + process $proc$libresoc.v:173052$9977 assign { } { } - assign $0\logical_op__rc__ok$7[0:0]$9994 1'0 + assign $0\logical_op__rc__ok$7[0:0]$9978 1'0 sync always sync init - update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9994 + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9978 end - attribute \src "libresoc.v:171753.7-171753.36" - process $proc$libresoc.v:171753$9995 + attribute \src "libresoc.v:173061.7-173061.36" + process $proc$libresoc.v:173061$9979 assign { } { } - assign $0\logical_op__rc__rc$6[0:0]$9996 1'0 + assign $0\logical_op__rc__rc$6[0:0]$9980 1'0 sync always sync init - update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9996 + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9980 end - attribute \src "libresoc.v:171762.7-171762.40" - process $proc$libresoc.v:171762$9997 + attribute \src "libresoc.v:173070.7-173070.40" + process $proc$libresoc.v:173070$9981 assign { } { } - assign $0\logical_op__write_cr0$14[0:0]$9998 1'0 + assign $0\logical_op__write_cr0$14[0:0]$9982 1'0 sync always sync init - update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9998 + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9982 end - attribute \src "libresoc.v:171771.7-171771.37" - process $proc$libresoc.v:171771$9999 + attribute \src "libresoc.v:173079.7-173079.37" + process $proc$libresoc.v:173079$9983 assign { } { } - assign $0\logical_op__zero_a$11[0:0]$10000 1'0 + assign $0\logical_op__zero_a$11[0:0]$9984 1'0 sync always sync init - update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$10000 + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9984 end - attribute \src "libresoc.v:171780.13-171780.29" - process $proc$libresoc.v:171780$10001 + attribute \src "libresoc.v:173088.13-173088.29" + process $proc$libresoc.v:173088$9985 assign { } { } - assign $0\muxid$1[1:0]$10002 2'00 + assign $0\muxid$1[1:0]$9986 2'00 sync always sync init - update \muxid$1 $0\muxid$1[1:0]$10002 + update \muxid$1 $0\muxid$1[1:0]$9986 end - attribute \src "libresoc.v:171793.14-171793.38" - process $proc$libresoc.v:171793$10003 + attribute \src "libresoc.v:173101.14-173101.38" + process $proc$libresoc.v:173101$9987 assign { } { } assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \o $1\o[63:0] end - attribute \src "libresoc.v:171800.7-171800.18" - process $proc$libresoc.v:171800$10004 + attribute \src "libresoc.v:173108.7-173108.18" + process $proc$libresoc.v:173108$9988 assign { } { } assign $1\o_ok[0:0] 1'0 sync always sync init update \o_ok $1\o_ok[0:0] end - attribute \src "libresoc.v:172396.7-172396.20" - process $proc$libresoc.v:172396$10005 + attribute \src "libresoc.v:173704.7-173704.20" + process $proc$libresoc.v:173704$9989 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:172411.13-172411.26" - process $proc$libresoc.v:172411$10006 + attribute \src "libresoc.v:173719.13-173719.26" + process $proc$libresoc.v:173719$9990 assign { } { } assign $1\xer_ov[1:0] 2'00 sync always sync init update \xer_ov $1\xer_ov[1:0] end - attribute \src "libresoc.v:172418.7-172418.23" - process $proc$libresoc.v:172418$10007 + attribute \src "libresoc.v:173726.7-173726.23" + process $proc$libresoc.v:173726$9991 assign { } { } assign $1\xer_ov_ok[0:0] 1'0 sync always sync init update \xer_ov_ok $1\xer_ov_ok[0:0] end - attribute \src "libresoc.v:172431.7-172431.25" - process $proc$libresoc.v:172431$10008 + attribute \src "libresoc.v:173739.7-173739.25" + process $proc$libresoc.v:173739$9992 assign { } { } - assign $0\xer_so$20[0:0]$10009 1'0 + assign $0\xer_so$20[0:0]$9993 1'0 sync always sync init - update \xer_so$20 $0\xer_so$20[0:0]$10009 + update \xer_so$20 $0\xer_so$20[0:0]$9993 end - attribute \src "libresoc.v:172436.7-172436.23" - process $proc$libresoc.v:172436$10010 + attribute \src "libresoc.v:173744.7-173744.23" + process $proc$libresoc.v:173744$9994 assign { } { } assign $1\xer_so_ok[0:0] 1'0 sync always sync init update \xer_so_ok $1\xer_so_ok[0:0] end - attribute \src "libresoc.v:172446.3-172447.37" - process $proc$libresoc.v:172446$9840 + attribute \src "libresoc.v:173754.3-173755.37" + process $proc$libresoc.v:173754$9824 assign { } { } - assign $0\xer_so$20[0:0]$9841 \xer_so$20$next + assign $0\xer_so$20[0:0]$9825 \xer_so$20$next sync posedge \coresync_clk - update \xer_so$20 $0\xer_so$20[0:0]$9841 + update \xer_so$20 $0\xer_so$20[0:0]$9825 end - attribute \src "libresoc.v:172448.3-172449.35" - process $proc$libresoc.v:172448$9842 + attribute \src "libresoc.v:173756.3-173757.35" + process $proc$libresoc.v:173756$9826 assign { } { } assign $0\xer_so_ok[0:0] \xer_so_ok$next sync posedge \coresync_clk update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:172450.3-172451.29" - process $proc$libresoc.v:172450$9843 + attribute \src "libresoc.v:173758.3-173759.29" + process $proc$libresoc.v:173758$9827 assign { } { } assign $0\xer_ov[1:0] \xer_ov$next sync posedge \coresync_clk update \xer_ov $0\xer_ov[1:0] end - attribute \src "libresoc.v:172452.3-172453.35" - process $proc$libresoc.v:172452$9844 + attribute \src "libresoc.v:173760.3-173761.35" + process $proc$libresoc.v:173760$9828 assign { } { } assign $0\xer_ov_ok[0:0] \xer_ov_ok$next sync posedge \coresync_clk update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:172454.3-172455.25" - process $proc$libresoc.v:172454$9845 + attribute \src "libresoc.v:173762.3-173763.25" + process $proc$libresoc.v:173762$9829 assign { } { } assign $0\cr_a[3:0] \cr_a$next sync posedge \coresync_clk update \cr_a $0\cr_a[3:0] end - attribute \src "libresoc.v:172456.3-172457.31" - process $proc$libresoc.v:172456$9846 + attribute \src "libresoc.v:173764.3-173765.31" + process $proc$libresoc.v:173764$9830 assign { } { } assign $0\cr_a_ok[0:0] \cr_a_ok$next sync posedge \coresync_clk update \cr_a_ok $0\cr_a_ok[0:0] end - attribute \src "libresoc.v:172458.3-172459.19" - process $proc$libresoc.v:172458$9847 + attribute \src "libresoc.v:173766.3-173767.19" + process $proc$libresoc.v:173766$9831 assign { } { } assign $0\o[63:0] \o$next sync posedge \coresync_clk update \o $0\o[63:0] end - attribute \src "libresoc.v:172460.3-172461.25" - process $proc$libresoc.v:172460$9848 + attribute \src "libresoc.v:173768.3-173769.25" + process $proc$libresoc.v:173768$9832 assign { } { } assign $0\o_ok[0:0] \o_ok$next sync posedge \coresync_clk update \o_ok $0\o_ok[0:0] end - attribute \src "libresoc.v:172462.3-172463.65" - process $proc$libresoc.v:172462$9849 + attribute \src "libresoc.v:173770.3-173771.65" + process $proc$libresoc.v:173770$9833 assign { } { } - assign $0\logical_op__insn_type$2[6:0]$9850 \logical_op__insn_type$2$next + assign $0\logical_op__insn_type$2[6:0]$9834 \logical_op__insn_type$2$next sync posedge \coresync_clk - update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9850 + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$9834 end - attribute \src "libresoc.v:172464.3-172465.61" - process $proc$libresoc.v:172464$9851 + attribute \src "libresoc.v:173772.3-173773.61" + process $proc$libresoc.v:173772$9835 assign { } { } - assign $0\logical_op__fn_unit$3[13:0]$9852 \logical_op__fn_unit$3$next + assign $0\logical_op__fn_unit$3[13:0]$9836 \logical_op__fn_unit$3$next sync posedge \coresync_clk - update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$9852 + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[13:0]$9836 end - attribute \src "libresoc.v:172466.3-172467.75" - process $proc$libresoc.v:172466$9853 + attribute \src "libresoc.v:173774.3-173775.75" + process $proc$libresoc.v:173774$9837 assign { } { } - assign $0\logical_op__imm_data__data$4[63:0]$9854 \logical_op__imm_data__data$4$next + assign $0\logical_op__imm_data__data$4[63:0]$9838 \logical_op__imm_data__data$4$next sync posedge \coresync_clk - update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9854 + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$9838 end - attribute \src "libresoc.v:172468.3-172469.71" - process $proc$libresoc.v:172468$9855 + attribute \src "libresoc.v:173776.3-173777.71" + process $proc$libresoc.v:173776$9839 assign { } { } - assign $0\logical_op__imm_data__ok$5[0:0]$9856 \logical_op__imm_data__ok$5$next + assign $0\logical_op__imm_data__ok$5[0:0]$9840 \logical_op__imm_data__ok$5$next sync posedge \coresync_clk - update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9856 + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$9840 end - attribute \src "libresoc.v:172470.3-172471.59" - process $proc$libresoc.v:172470$9857 + attribute \src "libresoc.v:173778.3-173779.59" + process $proc$libresoc.v:173778$9841 assign { } { } - assign $0\logical_op__rc__rc$6[0:0]$9858 \logical_op__rc__rc$6$next + assign $0\logical_op__rc__rc$6[0:0]$9842 \logical_op__rc__rc$6$next sync posedge \coresync_clk - update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9858 + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$9842 end - attribute \src "libresoc.v:172472.3-172473.59" - process $proc$libresoc.v:172472$9859 + attribute \src "libresoc.v:173780.3-173781.59" + process $proc$libresoc.v:173780$9843 assign { } { } - assign $0\logical_op__rc__ok$7[0:0]$9860 \logical_op__rc__ok$7$next + assign $0\logical_op__rc__ok$7[0:0]$9844 \logical_op__rc__ok$7$next sync posedge \coresync_clk - update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9860 + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$9844 end - attribute \src "libresoc.v:172474.3-172475.59" - process $proc$libresoc.v:172474$9861 + attribute \src "libresoc.v:173782.3-173783.59" + process $proc$libresoc.v:173782$9845 assign { } { } - assign $0\logical_op__oe__oe$8[0:0]$9862 \logical_op__oe__oe$8$next + assign $0\logical_op__oe__oe$8[0:0]$9846 \logical_op__oe__oe$8$next sync posedge \coresync_clk - update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9862 + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$9846 end - attribute \src "libresoc.v:172476.3-172477.59" - process $proc$libresoc.v:172476$9863 + attribute \src "libresoc.v:173784.3-173785.59" + process $proc$libresoc.v:173784$9847 assign { } { } - assign $0\logical_op__oe__ok$9[0:0]$9864 \logical_op__oe__ok$9$next + assign $0\logical_op__oe__ok$9[0:0]$9848 \logical_op__oe__ok$9$next sync posedge \coresync_clk - update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9864 + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$9848 end - attribute \src "libresoc.v:172478.3-172479.67" - process $proc$libresoc.v:172478$9865 + attribute \src "libresoc.v:173786.3-173787.67" + process $proc$libresoc.v:173786$9849 assign { } { } - assign $0\logical_op__invert_in$10[0:0]$9866 \logical_op__invert_in$10$next + assign $0\logical_op__invert_in$10[0:0]$9850 \logical_op__invert_in$10$next sync posedge \coresync_clk - update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9866 + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$9850 end - attribute \src "libresoc.v:172480.3-172481.61" - process $proc$libresoc.v:172480$9867 + attribute \src "libresoc.v:173788.3-173789.61" + process $proc$libresoc.v:173788$9851 assign { } { } - assign $0\logical_op__zero_a$11[0:0]$9868 \logical_op__zero_a$11$next + assign $0\logical_op__zero_a$11[0:0]$9852 \logical_op__zero_a$11$next sync posedge \coresync_clk - update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9868 + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$9852 end - attribute \src "libresoc.v:172482.3-172483.71" - process $proc$libresoc.v:172482$9869 + attribute \src "libresoc.v:173790.3-173791.71" + process $proc$libresoc.v:173790$9853 assign { } { } - assign $0\logical_op__input_carry$12[1:0]$9870 \logical_op__input_carry$12$next + assign $0\logical_op__input_carry$12[1:0]$9854 \logical_op__input_carry$12$next sync posedge \coresync_clk - update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9870 + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$9854 end - attribute \src "libresoc.v:172484.3-172485.69" - process $proc$libresoc.v:172484$9871 + attribute \src "libresoc.v:173792.3-173793.69" + process $proc$libresoc.v:173792$9855 assign { } { } - assign $0\logical_op__invert_out$13[0:0]$9872 \logical_op__invert_out$13$next + assign $0\logical_op__invert_out$13[0:0]$9856 \logical_op__invert_out$13$next sync posedge \coresync_clk - update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9872 + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$9856 end - attribute \src "libresoc.v:172486.3-172487.67" - process $proc$libresoc.v:172486$9873 + attribute \src "libresoc.v:173794.3-173795.67" + process $proc$libresoc.v:173794$9857 assign { } { } - assign $0\logical_op__write_cr0$14[0:0]$9874 \logical_op__write_cr0$14$next + assign $0\logical_op__write_cr0$14[0:0]$9858 \logical_op__write_cr0$14$next sync posedge \coresync_clk - update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9874 + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$9858 end - attribute \src "libresoc.v:172488.3-172489.73" - process $proc$libresoc.v:172488$9875 + attribute \src "libresoc.v:173796.3-173797.73" + process $proc$libresoc.v:173796$9859 assign { } { } - assign $0\logical_op__output_carry$15[0:0]$9876 \logical_op__output_carry$15$next + assign $0\logical_op__output_carry$15[0:0]$9860 \logical_op__output_carry$15$next sync posedge \coresync_clk - update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9876 + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$9860 end - attribute \src "libresoc.v:172490.3-172491.65" - process $proc$libresoc.v:172490$9877 + attribute \src "libresoc.v:173798.3-173799.65" + process $proc$libresoc.v:173798$9861 assign { } { } - assign $0\logical_op__is_32bit$16[0:0]$9878 \logical_op__is_32bit$16$next + assign $0\logical_op__is_32bit$16[0:0]$9862 \logical_op__is_32bit$16$next sync posedge \coresync_clk - update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9878 + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$9862 end - attribute \src "libresoc.v:172492.3-172493.67" - process $proc$libresoc.v:172492$9879 + attribute \src "libresoc.v:173800.3-173801.67" + process $proc$libresoc.v:173800$9863 assign { } { } - assign $0\logical_op__is_signed$17[0:0]$9880 \logical_op__is_signed$17$next + assign $0\logical_op__is_signed$17[0:0]$9864 \logical_op__is_signed$17$next sync posedge \coresync_clk - update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9880 + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$9864 end - attribute \src "libresoc.v:172494.3-172495.65" - process $proc$libresoc.v:172494$9881 + attribute \src "libresoc.v:173802.3-173803.65" + process $proc$libresoc.v:173802$9865 assign { } { } - assign $0\logical_op__data_len$18[3:0]$9882 \logical_op__data_len$18$next + assign $0\logical_op__data_len$18[3:0]$9866 \logical_op__data_len$18$next sync posedge \coresync_clk - update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9882 + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$9866 end - attribute \src "libresoc.v:172496.3-172497.57" - process $proc$libresoc.v:172496$9883 + attribute \src "libresoc.v:173804.3-173805.57" + process $proc$libresoc.v:173804$9867 assign { } { } - assign $0\logical_op__insn$19[31:0]$9884 \logical_op__insn$19$next + assign $0\logical_op__insn$19[31:0]$9868 \logical_op__insn$19$next sync posedge \coresync_clk - update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9884 + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$9868 end - attribute \src "libresoc.v:172498.3-172499.33" - process $proc$libresoc.v:172498$9885 + attribute \src "libresoc.v:173806.3-173807.33" + process $proc$libresoc.v:173806$9869 assign { } { } - assign $0\muxid$1[1:0]$9886 \muxid$1$next + assign $0\muxid$1[1:0]$9870 \muxid$1$next sync posedge \coresync_clk - update \muxid$1 $0\muxid$1[1:0]$9886 + update \muxid$1 $0\muxid$1[1:0]$9870 end - attribute \src "libresoc.v:172500.3-172501.29" - process $proc$libresoc.v:172500$9887 + attribute \src "libresoc.v:173808.3-173809.29" + process $proc$libresoc.v:173808$9871 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:172616.3-172634.6" - process $proc$libresoc.v:172616$9888 + attribute \src "libresoc.v:173924.3-173942.6" + process $proc$libresoc.v:173924$9872 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\o$next[63:0]$9889 $1\o$next[63:0]$9891 + assign $0\o$next[63:0]$9873 $1\o$next[63:0]$9875 assign { } { } - assign $0\o_ok$next[0:0]$9890 $2\o_ok$next[0:0]$9893 - attribute \src "libresoc.v:172617.5-172617.29" + assign $0\o_ok$next[0:0]$9874 $2\o_ok$next[0:0]$9877 + attribute \src "libresoc.v:173925.5-173925.29" switch \initial - attribute \src "libresoc.v:172617.9-172617.17" + attribute \src "libresoc.v:173925.9-173925.17" case 1'1 case end @@ -350611,41 +321981,41 @@ module \pipe_end case 2'-1 assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9892 $1\o$next[63:0]$9891 } { \o_ok$96 \o$95 } + assign { $1\o_ok$next[0:0]$9876 $1\o$next[63:0]$9875 } { \o_ok$96 \o$95 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\o_ok$next[0:0]$9892 $1\o$next[63:0]$9891 } { \o_ok$96 \o$95 } + assign { $1\o_ok$next[0:0]$9876 $1\o$next[63:0]$9875 } { \o_ok$96 \o$95 } case - assign $1\o$next[63:0]$9891 \o - assign $1\o_ok$next[0:0]$9892 \o_ok + assign $1\o$next[63:0]$9875 \o + assign $1\o_ok$next[0:0]$9876 \o_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\o_ok$next[0:0]$9893 1'0 + assign $2\o_ok$next[0:0]$9877 1'0 case - assign $2\o_ok$next[0:0]$9893 $1\o_ok$next[0:0]$9892 + assign $2\o_ok$next[0:0]$9877 $1\o_ok$next[0:0]$9876 end sync always - update \o$next $0\o$next[63:0]$9889 - update \o_ok$next $0\o_ok$next[0:0]$9890 + update \o$next $0\o$next[63:0]$9873 + update \o_ok$next $0\o_ok$next[0:0]$9874 end - attribute \src "libresoc.v:172635.3-172653.6" - process $proc$libresoc.v:172635$9894 + attribute \src "libresoc.v:173943.3-173961.6" + process $proc$libresoc.v:173943$9878 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\cr_a$next[3:0]$9895 $1\cr_a$next[3:0]$9897 + assign $0\cr_a$next[3:0]$9879 $1\cr_a$next[3:0]$9881 assign { } { } - assign $0\cr_a_ok$next[0:0]$9896 $2\cr_a_ok$next[0:0]$9899 - attribute \src "libresoc.v:172636.5-172636.29" + assign $0\cr_a_ok$next[0:0]$9880 $2\cr_a_ok$next[0:0]$9883 + attribute \src "libresoc.v:173944.5-173944.29" switch \initial - attribute \src "libresoc.v:172636.9-172636.17" + attribute \src "libresoc.v:173944.9-173944.17" case 1'1 case end @@ -350655,41 +322025,41 @@ module \pipe_end case 2'-1 assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$9898 $1\cr_a$next[3:0]$9897 } { \cr_a_ok$98 \cr_a$97 } + assign { $1\cr_a_ok$next[0:0]$9882 $1\cr_a$next[3:0]$9881 } { \cr_a_ok$98 \cr_a$97 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\cr_a_ok$next[0:0]$9898 $1\cr_a$next[3:0]$9897 } { \cr_a_ok$98 \cr_a$97 } + assign { $1\cr_a_ok$next[0:0]$9882 $1\cr_a$next[3:0]$9881 } { \cr_a_ok$98 \cr_a$97 } case - assign $1\cr_a$next[3:0]$9897 \cr_a - assign $1\cr_a_ok$next[0:0]$9898 \cr_a_ok + assign $1\cr_a$next[3:0]$9881 \cr_a + assign $1\cr_a_ok$next[0:0]$9882 \cr_a_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_a_ok$next[0:0]$9899 1'0 + assign $2\cr_a_ok$next[0:0]$9883 1'0 case - assign $2\cr_a_ok$next[0:0]$9899 $1\cr_a_ok$next[0:0]$9898 + assign $2\cr_a_ok$next[0:0]$9883 $1\cr_a_ok$next[0:0]$9882 end sync always - update \cr_a$next $0\cr_a$next[3:0]$9895 - update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9896 + update \cr_a$next $0\cr_a$next[3:0]$9879 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$9880 end - attribute \src "libresoc.v:172654.3-172672.6" - process $proc$libresoc.v:172654$9900 + attribute \src "libresoc.v:173962.3-173980.6" + process $proc$libresoc.v:173962$9884 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_ov$next[1:0]$9901 $1\xer_ov$next[1:0]$9903 + assign $0\xer_ov$next[1:0]$9885 $1\xer_ov$next[1:0]$9887 assign { } { } - assign $0\xer_ov_ok$next[0:0]$9902 $2\xer_ov_ok$next[0:0]$9905 - attribute \src "libresoc.v:172655.5-172655.29" + assign $0\xer_ov_ok$next[0:0]$9886 $2\xer_ov_ok$next[0:0]$9889 + attribute \src "libresoc.v:173963.5-173963.29" switch \initial - attribute \src "libresoc.v:172655.9-172655.17" + attribute \src "libresoc.v:173963.9-173963.17" case 1'1 case end @@ -350699,41 +322069,41 @@ module \pipe_end case 2'-1 assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$9904 $1\xer_ov$next[1:0]$9903 } { \xer_ov_ok$100 \xer_ov$99 } + assign { $1\xer_ov_ok$next[0:0]$9888 $1\xer_ov$next[1:0]$9887 } { \xer_ov_ok$100 \xer_ov$99 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_ov_ok$next[0:0]$9904 $1\xer_ov$next[1:0]$9903 } { \xer_ov_ok$100 \xer_ov$99 } + assign { $1\xer_ov_ok$next[0:0]$9888 $1\xer_ov$next[1:0]$9887 } { \xer_ov_ok$100 \xer_ov$99 } case - assign $1\xer_ov$next[1:0]$9903 \xer_ov - assign $1\xer_ov_ok$next[0:0]$9904 \xer_ov_ok + assign $1\xer_ov$next[1:0]$9887 \xer_ov + assign $1\xer_ov_ok$next[0:0]$9888 \xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_ov_ok$next[0:0]$9905 1'0 + assign $2\xer_ov_ok$next[0:0]$9889 1'0 case - assign $2\xer_ov_ok$next[0:0]$9905 $1\xer_ov_ok$next[0:0]$9904 + assign $2\xer_ov_ok$next[0:0]$9889 $1\xer_ov_ok$next[0:0]$9888 end sync always - update \xer_ov$next $0\xer_ov$next[1:0]$9901 - update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9902 + update \xer_ov$next $0\xer_ov$next[1:0]$9885 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$9886 end - attribute \src "libresoc.v:172673.3-172691.6" - process $proc$libresoc.v:172673$9906 + attribute \src "libresoc.v:173981.3-173999.6" + process $proc$libresoc.v:173981$9890 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\xer_so$20$next[0:0]$9908 $1\xer_so$20$next[0:0]$9910 - assign $0\xer_so_ok$next[0:0]$9907 $2\xer_so_ok$next[0:0]$9911 - attribute \src "libresoc.v:172674.5-172674.29" + assign $0\xer_so$20$next[0:0]$9892 $1\xer_so$20$next[0:0]$9894 + assign $0\xer_so_ok$next[0:0]$9891 $2\xer_so_ok$next[0:0]$9895 + attribute \src "libresoc.v:173982.5-173982.29" switch \initial - attribute \src "libresoc.v:172674.9-172674.17" + attribute \src "libresoc.v:173982.9-173982.17" case 1'1 case end @@ -350743,38 +322113,38 @@ module \pipe_end case 2'-1 assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$9909 $1\xer_so$20$next[0:0]$9910 } { \xer_so_ok$102 \xer_so$101 } + assign { $1\xer_so_ok$next[0:0]$9893 $1\xer_so$20$next[0:0]$9894 } { \xer_so_ok$102 \xer_so$101 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } assign { } { } - assign { $1\xer_so_ok$next[0:0]$9909 $1\xer_so$20$next[0:0]$9910 } { \xer_so_ok$102 \xer_so$101 } + assign { $1\xer_so_ok$next[0:0]$9893 $1\xer_so$20$next[0:0]$9894 } { \xer_so_ok$102 \xer_so$101 } case - assign $1\xer_so_ok$next[0:0]$9909 \xer_so_ok - assign $1\xer_so$20$next[0:0]$9910 \xer_so$20 + assign $1\xer_so_ok$next[0:0]$9893 \xer_so_ok + assign $1\xer_so$20$next[0:0]$9894 \xer_so$20 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so_ok$next[0:0]$9911 1'0 + assign $2\xer_so_ok$next[0:0]$9895 1'0 case - assign $2\xer_so_ok$next[0:0]$9911 $1\xer_so_ok$next[0:0]$9909 + assign $2\xer_so_ok$next[0:0]$9895 $1\xer_so_ok$next[0:0]$9893 end sync always - update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9907 - update \xer_so$20$next $0\xer_so$20$next[0:0]$9908 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$9891 + update \xer_so$20$next $0\xer_so$20$next[0:0]$9892 end - attribute \src "libresoc.v:172692.3-172709.6" - process $proc$libresoc.v:172692$9912 + attribute \src "libresoc.v:174000.3-174017.6" + process $proc$libresoc.v:174000$9896 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$9913 $2\r_busy$next[0:0]$9915 - attribute \src "libresoc.v:172693.5-172693.29" + assign $0\r_busy$next[0:0]$9897 $2\r_busy$next[0:0]$9899 + attribute \src "libresoc.v:174001.5-174001.29" switch \initial - attribute \src "libresoc.v:172693.9-172693.17" + attribute \src "libresoc.v:174001.9-174001.17" case 1'1 case end @@ -350783,34 +322153,34 @@ module \pipe_end attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$9914 1'1 + assign $1\r_busy$next[0:0]$9898 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$9914 1'0 + assign $1\r_busy$next[0:0]$9898 1'0 case - assign $1\r_busy$next[0:0]$9914 \r_busy + assign $1\r_busy$next[0:0]$9898 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$9915 1'0 + assign $2\r_busy$next[0:0]$9899 1'0 case - assign $2\r_busy$next[0:0]$9915 $1\r_busy$next[0:0]$9914 + assign $2\r_busy$next[0:0]$9899 $1\r_busy$next[0:0]$9898 end sync always - update \r_busy$next $0\r_busy$next[0:0]$9913 + update \r_busy$next $0\r_busy$next[0:0]$9897 end - attribute \src "libresoc.v:172710.3-172722.6" - process $proc$libresoc.v:172710$9916 + attribute \src "libresoc.v:174018.3-174030.6" + process $proc$libresoc.v:174018$9900 assign { } { } assign { } { } - assign $0\muxid$1$next[1:0]$9917 $1\muxid$1$next[1:0]$9918 - attribute \src "libresoc.v:172711.5-172711.29" + assign $0\muxid$1$next[1:0]$9901 $1\muxid$1$next[1:0]$9902 + attribute \src "libresoc.v:174019.5-174019.29" switch \initial - attribute \src "libresoc.v:172711.9-172711.17" + attribute \src "libresoc.v:174019.9-174019.17" case 1'1 case end @@ -350819,19 +322189,19 @@ module \pipe_end attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$1$next[1:0]$9918 \muxid$76 + assign $1\muxid$1$next[1:0]$9902 \muxid$76 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$1$next[1:0]$9918 \muxid$76 + assign $1\muxid$1$next[1:0]$9902 \muxid$76 case - assign $1\muxid$1$next[1:0]$9918 \muxid$1 + assign $1\muxid$1$next[1:0]$9902 \muxid$1 end sync always - update \muxid$1$next $0\muxid$1$next[1:0]$9917 + update \muxid$1$next $0\muxid$1$next[1:0]$9901 end - attribute \src "libresoc.v:172723.3-172764.6" - process $proc$libresoc.v:172723$9919 + attribute \src "libresoc.v:174031.3-174072.6" + process $proc$libresoc.v:174031$9903 assign { } { } assign { } { } assign { } { } @@ -350868,33 +322238,33 @@ module \pipe_end assign { } { } assign { } { } assign { } { } - assign $0\logical_op__data_len$18$next[3:0]$9920 $1\logical_op__data_len$18$next[3:0]$9938 - assign $0\logical_op__fn_unit$3$next[13:0]$9921 $1\logical_op__fn_unit$3$next[13:0]$9939 + assign $0\logical_op__data_len$18$next[3:0]$9904 $1\logical_op__data_len$18$next[3:0]$9922 + assign $0\logical_op__fn_unit$3$next[13:0]$9905 $1\logical_op__fn_unit$3$next[13:0]$9923 assign { } { } assign { } { } - assign $0\logical_op__input_carry$12$next[1:0]$9924 $1\logical_op__input_carry$12$next[1:0]$9942 - assign $0\logical_op__insn$19$next[31:0]$9925 $1\logical_op__insn$19$next[31:0]$9943 - assign $0\logical_op__insn_type$2$next[6:0]$9926 $1\logical_op__insn_type$2$next[6:0]$9944 - assign $0\logical_op__invert_in$10$next[0:0]$9927 $1\logical_op__invert_in$10$next[0:0]$9945 - assign $0\logical_op__invert_out$13$next[0:0]$9928 $1\logical_op__invert_out$13$next[0:0]$9946 - assign $0\logical_op__is_32bit$16$next[0:0]$9929 $1\logical_op__is_32bit$16$next[0:0]$9947 - assign $0\logical_op__is_signed$17$next[0:0]$9930 $1\logical_op__is_signed$17$next[0:0]$9948 + assign $0\logical_op__input_carry$12$next[1:0]$9908 $1\logical_op__input_carry$12$next[1:0]$9926 + assign $0\logical_op__insn$19$next[31:0]$9909 $1\logical_op__insn$19$next[31:0]$9927 + assign $0\logical_op__insn_type$2$next[6:0]$9910 $1\logical_op__insn_type$2$next[6:0]$9928 + assign $0\logical_op__invert_in$10$next[0:0]$9911 $1\logical_op__invert_in$10$next[0:0]$9929 + assign $0\logical_op__invert_out$13$next[0:0]$9912 $1\logical_op__invert_out$13$next[0:0]$9930 + assign $0\logical_op__is_32bit$16$next[0:0]$9913 $1\logical_op__is_32bit$16$next[0:0]$9931 + assign $0\logical_op__is_signed$17$next[0:0]$9914 $1\logical_op__is_signed$17$next[0:0]$9932 assign { } { } assign { } { } - assign $0\logical_op__output_carry$15$next[0:0]$9933 $1\logical_op__output_carry$15$next[0:0]$9951 + assign $0\logical_op__output_carry$15$next[0:0]$9917 $1\logical_op__output_carry$15$next[0:0]$9935 assign { } { } assign { } { } - assign $0\logical_op__write_cr0$14$next[0:0]$9936 $1\logical_op__write_cr0$14$next[0:0]$9954 - assign $0\logical_op__zero_a$11$next[0:0]$9937 $1\logical_op__zero_a$11$next[0:0]$9955 - assign $0\logical_op__imm_data__data$4$next[63:0]$9922 $2\logical_op__imm_data__data$4$next[63:0]$9956 - assign $0\logical_op__imm_data__ok$5$next[0:0]$9923 $2\logical_op__imm_data__ok$5$next[0:0]$9957 - assign $0\logical_op__oe__oe$8$next[0:0]$9931 $2\logical_op__oe__oe$8$next[0:0]$9958 - assign $0\logical_op__oe__ok$9$next[0:0]$9932 $2\logical_op__oe__ok$9$next[0:0]$9959 - assign $0\logical_op__rc__ok$7$next[0:0]$9934 $2\logical_op__rc__ok$7$next[0:0]$9960 - assign $0\logical_op__rc__rc$6$next[0:0]$9935 $2\logical_op__rc__rc$6$next[0:0]$9961 - attribute \src "libresoc.v:172724.5-172724.29" + assign $0\logical_op__write_cr0$14$next[0:0]$9920 $1\logical_op__write_cr0$14$next[0:0]$9938 + assign $0\logical_op__zero_a$11$next[0:0]$9921 $1\logical_op__zero_a$11$next[0:0]$9939 + assign $0\logical_op__imm_data__data$4$next[63:0]$9906 $2\logical_op__imm_data__data$4$next[63:0]$9940 + assign $0\logical_op__imm_data__ok$5$next[0:0]$9907 $2\logical_op__imm_data__ok$5$next[0:0]$9941 + assign $0\logical_op__oe__oe$8$next[0:0]$9915 $2\logical_op__oe__oe$8$next[0:0]$9942 + assign $0\logical_op__oe__ok$9$next[0:0]$9916 $2\logical_op__oe__ok$9$next[0:0]$9943 + assign $0\logical_op__rc__ok$7$next[0:0]$9918 $2\logical_op__rc__ok$7$next[0:0]$9944 + assign $0\logical_op__rc__rc$6$next[0:0]$9919 $2\logical_op__rc__rc$6$next[0:0]$9945 + attribute \src "libresoc.v:174032.5-174032.29" switch \initial - attribute \src "libresoc.v:172724.9-172724.17" + attribute \src "libresoc.v:174032.9-174032.17" case 1'1 case end @@ -350920,7 +322290,7 @@ module \pipe_end assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$19$next[31:0]$9943 $1\logical_op__data_len$18$next[3:0]$9938 $1\logical_op__is_signed$17$next[0:0]$9948 $1\logical_op__is_32bit$16$next[0:0]$9947 $1\logical_op__output_carry$15$next[0:0]$9951 $1\logical_op__write_cr0$14$next[0:0]$9954 $1\logical_op__invert_out$13$next[0:0]$9946 $1\logical_op__input_carry$12$next[1:0]$9942 $1\logical_op__zero_a$11$next[0:0]$9955 $1\logical_op__invert_in$10$next[0:0]$9945 $1\logical_op__oe__ok$9$next[0:0]$9950 $1\logical_op__oe__oe$8$next[0:0]$9949 $1\logical_op__rc__ok$7$next[0:0]$9952 $1\logical_op__rc__rc$6$next[0:0]$9953 $1\logical_op__imm_data__ok$5$next[0:0]$9941 $1\logical_op__imm_data__data$4$next[63:0]$9940 $1\logical_op__fn_unit$3$next[13:0]$9939 $1\logical_op__insn_type$2$next[6:0]$9944 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } + assign { $1\logical_op__insn$19$next[31:0]$9927 $1\logical_op__data_len$18$next[3:0]$9922 $1\logical_op__is_signed$17$next[0:0]$9932 $1\logical_op__is_32bit$16$next[0:0]$9931 $1\logical_op__output_carry$15$next[0:0]$9935 $1\logical_op__write_cr0$14$next[0:0]$9938 $1\logical_op__invert_out$13$next[0:0]$9930 $1\logical_op__input_carry$12$next[1:0]$9926 $1\logical_op__zero_a$11$next[0:0]$9939 $1\logical_op__invert_in$10$next[0:0]$9929 $1\logical_op__oe__ok$9$next[0:0]$9934 $1\logical_op__oe__oe$8$next[0:0]$9933 $1\logical_op__rc__ok$7$next[0:0]$9936 $1\logical_op__rc__rc$6$next[0:0]$9937 $1\logical_op__imm_data__ok$5$next[0:0]$9925 $1\logical_op__imm_data__data$4$next[63:0]$9924 $1\logical_op__fn_unit$3$next[13:0]$9923 $1\logical_op__insn_type$2$next[6:0]$9928 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -350941,26 +322311,26 @@ module \pipe_end assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$19$next[31:0]$9943 $1\logical_op__data_len$18$next[3:0]$9938 $1\logical_op__is_signed$17$next[0:0]$9948 $1\logical_op__is_32bit$16$next[0:0]$9947 $1\logical_op__output_carry$15$next[0:0]$9951 $1\logical_op__write_cr0$14$next[0:0]$9954 $1\logical_op__invert_out$13$next[0:0]$9946 $1\logical_op__input_carry$12$next[1:0]$9942 $1\logical_op__zero_a$11$next[0:0]$9955 $1\logical_op__invert_in$10$next[0:0]$9945 $1\logical_op__oe__ok$9$next[0:0]$9950 $1\logical_op__oe__oe$8$next[0:0]$9949 $1\logical_op__rc__ok$7$next[0:0]$9952 $1\logical_op__rc__rc$6$next[0:0]$9953 $1\logical_op__imm_data__ok$5$next[0:0]$9941 $1\logical_op__imm_data__data$4$next[63:0]$9940 $1\logical_op__fn_unit$3$next[13:0]$9939 $1\logical_op__insn_type$2$next[6:0]$9944 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } + assign { $1\logical_op__insn$19$next[31:0]$9927 $1\logical_op__data_len$18$next[3:0]$9922 $1\logical_op__is_signed$17$next[0:0]$9932 $1\logical_op__is_32bit$16$next[0:0]$9931 $1\logical_op__output_carry$15$next[0:0]$9935 $1\logical_op__write_cr0$14$next[0:0]$9938 $1\logical_op__invert_out$13$next[0:0]$9930 $1\logical_op__input_carry$12$next[1:0]$9926 $1\logical_op__zero_a$11$next[0:0]$9939 $1\logical_op__invert_in$10$next[0:0]$9929 $1\logical_op__oe__ok$9$next[0:0]$9934 $1\logical_op__oe__oe$8$next[0:0]$9933 $1\logical_op__rc__ok$7$next[0:0]$9936 $1\logical_op__rc__rc$6$next[0:0]$9937 $1\logical_op__imm_data__ok$5$next[0:0]$9925 $1\logical_op__imm_data__data$4$next[63:0]$9924 $1\logical_op__fn_unit$3$next[13:0]$9923 $1\logical_op__insn_type$2$next[6:0]$9928 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } case - assign $1\logical_op__data_len$18$next[3:0]$9938 \logical_op__data_len$18 - assign $1\logical_op__fn_unit$3$next[13:0]$9939 \logical_op__fn_unit$3 - assign $1\logical_op__imm_data__data$4$next[63:0]$9940 \logical_op__imm_data__data$4 - assign $1\logical_op__imm_data__ok$5$next[0:0]$9941 \logical_op__imm_data__ok$5 - assign $1\logical_op__input_carry$12$next[1:0]$9942 \logical_op__input_carry$12 - assign $1\logical_op__insn$19$next[31:0]$9943 \logical_op__insn$19 - assign $1\logical_op__insn_type$2$next[6:0]$9944 \logical_op__insn_type$2 - assign $1\logical_op__invert_in$10$next[0:0]$9945 \logical_op__invert_in$10 - assign $1\logical_op__invert_out$13$next[0:0]$9946 \logical_op__invert_out$13 - assign $1\logical_op__is_32bit$16$next[0:0]$9947 \logical_op__is_32bit$16 - assign $1\logical_op__is_signed$17$next[0:0]$9948 \logical_op__is_signed$17 - assign $1\logical_op__oe__oe$8$next[0:0]$9949 \logical_op__oe__oe$8 - assign $1\logical_op__oe__ok$9$next[0:0]$9950 \logical_op__oe__ok$9 - assign $1\logical_op__output_carry$15$next[0:0]$9951 \logical_op__output_carry$15 - assign $1\logical_op__rc__ok$7$next[0:0]$9952 \logical_op__rc__ok$7 - assign $1\logical_op__rc__rc$6$next[0:0]$9953 \logical_op__rc__rc$6 - assign $1\logical_op__write_cr0$14$next[0:0]$9954 \logical_op__write_cr0$14 - assign $1\logical_op__zero_a$11$next[0:0]$9955 \logical_op__zero_a$11 + assign $1\logical_op__data_len$18$next[3:0]$9922 \logical_op__data_len$18 + assign $1\logical_op__fn_unit$3$next[13:0]$9923 \logical_op__fn_unit$3 + assign $1\logical_op__imm_data__data$4$next[63:0]$9924 \logical_op__imm_data__data$4 + assign $1\logical_op__imm_data__ok$5$next[0:0]$9925 \logical_op__imm_data__ok$5 + assign $1\logical_op__input_carry$12$next[1:0]$9926 \logical_op__input_carry$12 + assign $1\logical_op__insn$19$next[31:0]$9927 \logical_op__insn$19 + assign $1\logical_op__insn_type$2$next[6:0]$9928 \logical_op__insn_type$2 + assign $1\logical_op__invert_in$10$next[0:0]$9929 \logical_op__invert_in$10 + assign $1\logical_op__invert_out$13$next[0:0]$9930 \logical_op__invert_out$13 + assign $1\logical_op__is_32bit$16$next[0:0]$9931 \logical_op__is_32bit$16 + assign $1\logical_op__is_signed$17$next[0:0]$9932 \logical_op__is_signed$17 + assign $1\logical_op__oe__oe$8$next[0:0]$9933 \logical_op__oe__oe$8 + assign $1\logical_op__oe__ok$9$next[0:0]$9934 \logical_op__oe__ok$9 + assign $1\logical_op__output_carry$15$next[0:0]$9935 \logical_op__output_carry$15 + assign $1\logical_op__rc__ok$7$next[0:0]$9936 \logical_op__rc__ok$7 + assign $1\logical_op__rc__rc$6$next[0:0]$9937 \logical_op__rc__rc$6 + assign $1\logical_op__write_cr0$14$next[0:0]$9938 \logical_op__write_cr0$14 + assign $1\logical_op__zero_a$11$next[0:0]$9939 \logical_op__zero_a$11 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -350972,41 +322342,41 @@ module \pipe_end assign { } { } assign { } { } assign { } { } - assign $2\logical_op__imm_data__data$4$next[63:0]$9956 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\logical_op__imm_data__ok$5$next[0:0]$9957 1'0 - assign $2\logical_op__rc__rc$6$next[0:0]$9961 1'0 - assign $2\logical_op__rc__ok$7$next[0:0]$9960 1'0 - assign $2\logical_op__oe__oe$8$next[0:0]$9958 1'0 - assign $2\logical_op__oe__ok$9$next[0:0]$9959 1'0 + assign $2\logical_op__imm_data__data$4$next[63:0]$9940 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$5$next[0:0]$9941 1'0 + assign $2\logical_op__rc__rc$6$next[0:0]$9945 1'0 + assign $2\logical_op__rc__ok$7$next[0:0]$9944 1'0 + assign $2\logical_op__oe__oe$8$next[0:0]$9942 1'0 + assign $2\logical_op__oe__ok$9$next[0:0]$9943 1'0 case - assign $2\logical_op__imm_data__data$4$next[63:0]$9956 $1\logical_op__imm_data__data$4$next[63:0]$9940 - assign $2\logical_op__imm_data__ok$5$next[0:0]$9957 $1\logical_op__imm_data__ok$5$next[0:0]$9941 - assign $2\logical_op__oe__oe$8$next[0:0]$9958 $1\logical_op__oe__oe$8$next[0:0]$9949 - assign $2\logical_op__oe__ok$9$next[0:0]$9959 $1\logical_op__oe__ok$9$next[0:0]$9950 - assign $2\logical_op__rc__ok$7$next[0:0]$9960 $1\logical_op__rc__ok$7$next[0:0]$9952 - assign $2\logical_op__rc__rc$6$next[0:0]$9961 $1\logical_op__rc__rc$6$next[0:0]$9953 + assign $2\logical_op__imm_data__data$4$next[63:0]$9940 $1\logical_op__imm_data__data$4$next[63:0]$9924 + assign $2\logical_op__imm_data__ok$5$next[0:0]$9941 $1\logical_op__imm_data__ok$5$next[0:0]$9925 + assign $2\logical_op__oe__oe$8$next[0:0]$9942 $1\logical_op__oe__oe$8$next[0:0]$9933 + assign $2\logical_op__oe__ok$9$next[0:0]$9943 $1\logical_op__oe__ok$9$next[0:0]$9934 + assign $2\logical_op__rc__ok$7$next[0:0]$9944 $1\logical_op__rc__ok$7$next[0:0]$9936 + assign $2\logical_op__rc__rc$6$next[0:0]$9945 $1\logical_op__rc__rc$6$next[0:0]$9937 end sync always - update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$9920 - update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[13:0]$9921 - update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$9922 - update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$9923 - update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$9924 - update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$9925 - update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$9926 - update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$9927 - update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$9928 - update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$9929 - update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$9930 - update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$9931 - update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$9932 - update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$9933 - update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$9934 - update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$9935 - update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$9936 - update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$9937 + update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$9904 + update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[13:0]$9905 + update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$9906 + update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$9907 + update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$9908 + update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$9909 + update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$9910 + update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$9911 + update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$9912 + update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$9913 + update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$9914 + update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$9915 + update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$9916 + update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$9917 + update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$9918 + update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$9919 + update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$9920 + update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$9921 end - connect \$74 $and$libresoc.v:172445$9839_Y + connect \$74 $and$libresoc.v:173753$9823_Y connect \cr_a$68 4'0000 connect \cr_a_ok$69 1'0 connect \xer_so_ok$72 1'0 @@ -351040,381 +322410,381 @@ module \pipe_end connect { \output_stage_logical_op__insn \output_stage_logical_op__data_len \output_stage_logical_op__is_signed \output_stage_logical_op__is_32bit \output_stage_logical_op__output_carry \output_stage_logical_op__write_cr0 \output_stage_logical_op__invert_out \output_stage_logical_op__input_carry \output_stage_logical_op__zero_a \output_stage_logical_op__invert_in \output_stage_logical_op__oe__ok \output_stage_logical_op__oe__oe \output_stage_logical_op__rc__ok \output_stage_logical_op__rc__rc \output_stage_logical_op__imm_data__ok \output_stage_logical_op__imm_data__data \output_stage_logical_op__fn_unit \output_stage_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } connect \output_stage_muxid \muxid end -attribute \src "libresoc.v:172801.1-173788.10" +attribute \src "libresoc.v:174109.1-175096.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_middle_0" attribute \generator "nMigen" module \pipe_middle_0 - attribute \src "libresoc.v:173713.3-173727.6" - wire $0\div_by_zero$54$next[0:0]$10190 - attribute \src "libresoc.v:173387.3-173388.47" - wire $0\div_by_zero$54[0:0]$10025 - attribute \src "libresoc.v:172824.7-172824.30" - wire $0\div_by_zero$54[0:0]$10207 - attribute \src "libresoc.v:173509.3-173520.6" + attribute \src "libresoc.v:175021.3-175035.6" + wire $0\div_by_zero$54$next[0:0]$10174 + attribute \src "libresoc.v:174695.3-174696.47" + wire $0\div_by_zero$54[0:0]$10009 + attribute \src "libresoc.v:174132.7-174132.30" + wire $0\div_by_zero$54[0:0]$10191 + attribute \src "libresoc.v:174817.3-174828.6" wire width 64 $0\div_state_next_divisor[63:0] - attribute \src "libresoc.v:173497.3-173508.6" + attribute \src "libresoc.v:174805.3-174816.6" wire width 128 $0\div_state_next_i_dividend_quotient[127:0] - attribute \src "libresoc.v:173485.3-173496.6" + attribute \src "libresoc.v:174793.3-174804.6" wire width 7 $0\div_state_next_i_q_bits_known[6:0] - attribute \src "libresoc.v:173683.3-173697.6" - wire $0\dive_abs_ov32$52$next[0:0]$10182 - attribute \src "libresoc.v:173391.3-173392.51" - wire $0\dive_abs_ov32$52[0:0]$10029 - attribute \src "libresoc.v:172848.7-172848.32" - wire $0\dive_abs_ov32$52[0:0]$10209 - attribute \src "libresoc.v:173698.3-173712.6" - wire $0\dive_abs_ov64$53$next[0:0]$10186 - attribute \src "libresoc.v:173389.3-173390.51" - wire $0\dive_abs_ov64$53[0:0]$10027 - attribute \src "libresoc.v:172856.7-172856.32" - wire $0\dive_abs_ov64$53[0:0]$10211 - attribute \src "libresoc.v:173728.3-173742.6" - wire width 128 $0\dividend$68$next[127:0]$10194 - attribute \src "libresoc.v:173385.3-173386.41" - wire width 128 $0\dividend$68[127:0]$10023 - attribute \src "libresoc.v:172862.15-172862.68" - wire width 128 $0\dividend$68[127:0]$10213 - attribute \src "libresoc.v:173668.3-173682.6" - wire $0\dividend_neg$51$next[0:0]$10178 - attribute \src "libresoc.v:173393.3-173394.49" - wire $0\dividend_neg$51[0:0]$10031 - attribute \src "libresoc.v:172870.7-172870.31" - wire $0\dividend_neg$51[0:0]$10215 - attribute \src "libresoc.v:173653.3-173667.6" - wire $0\divisor_neg$50$next[0:0]$10174 - attribute \src "libresoc.v:173395.3-173396.47" - wire $0\divisor_neg$50[0:0]$10033 - attribute \src "libresoc.v:172878.7-172878.30" - wire $0\divisor_neg$50[0:0]$10217 - attribute \src "libresoc.v:173743.3-173757.6" - wire width 64 $0\divisor_radicand$65$next[63:0]$10198 - attribute \src "libresoc.v:173383.3-173384.57" - wire width 64 $0\divisor_radicand$65[63:0]$10021 - attribute \src "libresoc.v:172884.14-172884.58" - wire width 64 $0\divisor_radicand$65[63:0]$10219 - attribute \src "libresoc.v:173521.3-173548.6" - wire $0\empty$next[0:0]$10091 - attribute \src "libresoc.v:173441.3-173442.27" + attribute \src "libresoc.v:174991.3-175005.6" + wire $0\dive_abs_ov32$52$next[0:0]$10166 + attribute \src "libresoc.v:174699.3-174700.51" + wire $0\dive_abs_ov32$52[0:0]$10013 + attribute \src "libresoc.v:174156.7-174156.32" + wire $0\dive_abs_ov32$52[0:0]$10193 + attribute \src "libresoc.v:175006.3-175020.6" + wire $0\dive_abs_ov64$53$next[0:0]$10170 + attribute \src "libresoc.v:174697.3-174698.51" + wire $0\dive_abs_ov64$53[0:0]$10011 + attribute \src "libresoc.v:174164.7-174164.32" + wire $0\dive_abs_ov64$53[0:0]$10195 + attribute \src "libresoc.v:175036.3-175050.6" + wire width 128 $0\dividend$68$next[127:0]$10178 + attribute \src "libresoc.v:174693.3-174694.41" + wire width 128 $0\dividend$68[127:0]$10007 + attribute \src "libresoc.v:174170.15-174170.68" + wire width 128 $0\dividend$68[127:0]$10197 + attribute \src "libresoc.v:174976.3-174990.6" + wire $0\dividend_neg$51$next[0:0]$10162 + attribute \src "libresoc.v:174701.3-174702.49" + wire $0\dividend_neg$51[0:0]$10015 + attribute \src "libresoc.v:174178.7-174178.31" + wire $0\dividend_neg$51[0:0]$10199 + attribute \src "libresoc.v:174961.3-174975.6" + wire $0\divisor_neg$50$next[0:0]$10158 + attribute \src "libresoc.v:174703.3-174704.47" + wire $0\divisor_neg$50[0:0]$10017 + attribute \src "libresoc.v:174186.7-174186.30" + wire $0\divisor_neg$50[0:0]$10201 + attribute \src "libresoc.v:175051.3-175065.6" + wire width 64 $0\divisor_radicand$65$next[63:0]$10182 + attribute \src "libresoc.v:174691.3-174692.57" + wire width 64 $0\divisor_radicand$65[63:0]$10005 + attribute \src "libresoc.v:174192.14-174192.58" + wire width 64 $0\divisor_radicand$65[63:0]$10203 + attribute \src "libresoc.v:174829.3-174856.6" + wire $0\empty$next[0:0]$10075 + attribute \src "libresoc.v:174749.3-174750.27" wire $0\empty[0:0] - attribute \src "libresoc.v:172802.7-172802.20" + attribute \src "libresoc.v:174110.7-174110.20" wire $0\initial[0:0] - attribute \src "libresoc.v:173564.3-173607.6" - wire width 4 $0\logical_op__data_len$45$next[3:0]$10101 - attribute \src "libresoc.v:173435.3-173436.65" - wire width 4 $0\logical_op__data_len$45[3:0]$10073 - attribute \src "libresoc.v:172896.13-172896.45" - wire width 4 $0\logical_op__data_len$45[3:0]$10222 - attribute \src "libresoc.v:173564.3-173607.6" - wire width 14 $0\logical_op__fn_unit$30$next[13:0]$10102 - attribute \src "libresoc.v:173405.3-173406.63" - wire width 14 $0\logical_op__fn_unit$30[13:0]$10043 - attribute \src "libresoc.v:172949.14-172949.49" - wire width 14 $0\logical_op__fn_unit$30[13:0]$10224 - attribute \src "libresoc.v:173564.3-173607.6" - wire width 64 $0\logical_op__imm_data__data$31$next[63:0]$10103 - attribute \src "libresoc.v:173407.3-173408.77" - wire width 64 $0\logical_op__imm_data__data$31[63:0]$10045 - attribute \src "libresoc.v:172955.14-172955.68" - wire width 64 $0\logical_op__imm_data__data$31[63:0]$10226 - attribute \src "libresoc.v:173564.3-173607.6" - wire $0\logical_op__imm_data__ok$32$next[0:0]$10104 - attribute \src "libresoc.v:173409.3-173410.73" - wire $0\logical_op__imm_data__ok$32[0:0]$10047 - attribute \src "libresoc.v:172963.7-172963.43" - wire $0\logical_op__imm_data__ok$32[0:0]$10228 - attribute \src "libresoc.v:173564.3-173607.6" - wire width 2 $0\logical_op__input_carry$39$next[1:0]$10105 - attribute \src "libresoc.v:173423.3-173424.71" - wire width 2 $0\logical_op__input_carry$39[1:0]$10061 - attribute \src "libresoc.v:172985.13-172985.48" - wire width 2 $0\logical_op__input_carry$39[1:0]$10230 - attribute \src "libresoc.v:173564.3-173607.6" - wire width 32 $0\logical_op__insn$46$next[31:0]$10106 - attribute \src "libresoc.v:173437.3-173438.57" - wire width 32 $0\logical_op__insn$46[31:0]$10075 - attribute \src "libresoc.v:172993.14-172993.43" - wire width 32 $0\logical_op__insn$46[31:0]$10232 - attribute \src "libresoc.v:173564.3-173607.6" - wire width 7 $0\logical_op__insn_type$29$next[6:0]$10107 - attribute \src "libresoc.v:173403.3-173404.67" - wire width 7 $0\logical_op__insn_type$29[6:0]$10041 - attribute \src "libresoc.v:173226.13-173226.47" - wire width 7 $0\logical_op__insn_type$29[6:0]$10234 - attribute \src "libresoc.v:173564.3-173607.6" - wire $0\logical_op__invert_in$37$next[0:0]$10108 - attribute \src "libresoc.v:173419.3-173420.67" - wire $0\logical_op__invert_in$37[0:0]$10057 - attribute \src "libresoc.v:173234.7-173234.40" - wire $0\logical_op__invert_in$37[0:0]$10236 - attribute \src "libresoc.v:173564.3-173607.6" - wire $0\logical_op__invert_out$40$next[0:0]$10109 - attribute \src "libresoc.v:173425.3-173426.69" - wire $0\logical_op__invert_out$40[0:0]$10063 - attribute \src "libresoc.v:173242.7-173242.41" - wire $0\logical_op__invert_out$40[0:0]$10238 - attribute \src "libresoc.v:173564.3-173607.6" - wire $0\logical_op__is_32bit$43$next[0:0]$10110 - attribute \src "libresoc.v:173431.3-173432.65" - wire $0\logical_op__is_32bit$43[0:0]$10069 - attribute \src "libresoc.v:173250.7-173250.39" - wire $0\logical_op__is_32bit$43[0:0]$10240 - attribute \src "libresoc.v:173564.3-173607.6" - wire $0\logical_op__is_signed$44$next[0:0]$10111 - attribute \src "libresoc.v:173433.3-173434.67" - wire $0\logical_op__is_signed$44[0:0]$10071 - attribute \src "libresoc.v:173258.7-173258.40" - wire $0\logical_op__is_signed$44[0:0]$10242 - attribute \src "libresoc.v:173564.3-173607.6" - wire $0\logical_op__oe__oe$35$next[0:0]$10112 - attribute \src "libresoc.v:173415.3-173416.61" - wire $0\logical_op__oe__oe$35[0:0]$10053 - attribute \src "libresoc.v:173264.7-173264.37" - wire $0\logical_op__oe__oe$35[0:0]$10244 - attribute \src "libresoc.v:173564.3-173607.6" - wire $0\logical_op__oe__ok$36$next[0:0]$10113 - attribute \src "libresoc.v:173417.3-173418.61" - wire $0\logical_op__oe__ok$36[0:0]$10055 - attribute \src "libresoc.v:173272.7-173272.37" - wire $0\logical_op__oe__ok$36[0:0]$10246 - attribute \src "libresoc.v:173564.3-173607.6" - wire $0\logical_op__output_carry$42$next[0:0]$10114 - attribute \src "libresoc.v:173429.3-173430.73" - wire $0\logical_op__output_carry$42[0:0]$10067 - attribute \src "libresoc.v:173282.7-173282.43" - wire $0\logical_op__output_carry$42[0:0]$10248 - attribute \src "libresoc.v:173564.3-173607.6" - wire $0\logical_op__rc__ok$34$next[0:0]$10115 - attribute \src "libresoc.v:173413.3-173414.61" - wire $0\logical_op__rc__ok$34[0:0]$10051 - attribute \src "libresoc.v:173288.7-173288.37" - wire $0\logical_op__rc__ok$34[0:0]$10250 - attribute \src "libresoc.v:173564.3-173607.6" - wire $0\logical_op__rc__rc$33$next[0:0]$10116 - attribute \src "libresoc.v:173411.3-173412.61" - wire $0\logical_op__rc__rc$33[0:0]$10049 - attribute \src "libresoc.v:173296.7-173296.37" - wire $0\logical_op__rc__rc$33[0:0]$10252 - attribute \src "libresoc.v:173564.3-173607.6" - wire $0\logical_op__write_cr0$41$next[0:0]$10117 - attribute \src "libresoc.v:173427.3-173428.67" - wire $0\logical_op__write_cr0$41[0:0]$10065 - attribute \src "libresoc.v:173306.7-173306.40" - wire $0\logical_op__write_cr0$41[0:0]$10254 - attribute \src "libresoc.v:173564.3-173607.6" - wire $0\logical_op__zero_a$38$next[0:0]$10118 - attribute \src "libresoc.v:173421.3-173422.61" - wire $0\logical_op__zero_a$38[0:0]$10059 - attribute \src "libresoc.v:173314.7-173314.37" - wire $0\logical_op__zero_a$38[0:0]$10256 - attribute \src "libresoc.v:173549.3-173563.6" - wire width 2 $0\muxid$28$next[1:0]$10097 - attribute \src "libresoc.v:173439.3-173440.35" - wire width 2 $0\muxid$28[1:0]$10077 - attribute \src "libresoc.v:173322.13-173322.30" - wire width 2 $0\muxid$28[1:0]$10258 - attribute \src "libresoc.v:173758.3-173772.6" - wire width 2 $0\operation$69$next[1:0]$10202 - attribute \src "libresoc.v:173381.3-173382.43" - wire width 2 $0\operation$69[1:0]$10019 - attribute \src "libresoc.v:173332.13-173332.34" - wire width 2 $0\operation$69[1:0]$10260 - attribute \src "libresoc.v:173608.3-173622.6" - wire width 64 $0\ra$47$next[63:0]$10162 - attribute \src "libresoc.v:173401.3-173402.29" - wire width 64 $0\ra$47[63:0]$10039 - attribute \src "libresoc.v:173346.14-173346.44" - wire width 64 $0\ra$47[63:0]$10262 - attribute \src "libresoc.v:173623.3-173637.6" - wire width 64 $0\rb$48$next[63:0]$10166 - attribute \src "libresoc.v:173399.3-173400.29" - wire width 64 $0\rb$48[63:0]$10037 - attribute \src "libresoc.v:173354.14-173354.44" - wire width 64 $0\rb$48[63:0]$10264 - attribute \src "libresoc.v:173476.3-173484.6" - wire width 128 $0\saved_state_dividend_quotient$next[127:0]$10085 - attribute \src "libresoc.v:173443.3-173444.75" + attribute \src "libresoc.v:174872.3-174915.6" + wire width 4 $0\logical_op__data_len$45$next[3:0]$10085 + attribute \src "libresoc.v:174743.3-174744.65" + wire width 4 $0\logical_op__data_len$45[3:0]$10057 + attribute \src "libresoc.v:174204.13-174204.45" + wire width 4 $0\logical_op__data_len$45[3:0]$10206 + attribute \src "libresoc.v:174872.3-174915.6" + wire width 14 $0\logical_op__fn_unit$30$next[13:0]$10086 + attribute \src "libresoc.v:174713.3-174714.63" + wire width 14 $0\logical_op__fn_unit$30[13:0]$10027 + attribute \src "libresoc.v:174257.14-174257.49" + wire width 14 $0\logical_op__fn_unit$30[13:0]$10208 + attribute \src "libresoc.v:174872.3-174915.6" + wire width 64 $0\logical_op__imm_data__data$31$next[63:0]$10087 + attribute \src "libresoc.v:174715.3-174716.77" + wire width 64 $0\logical_op__imm_data__data$31[63:0]$10029 + attribute \src "libresoc.v:174263.14-174263.68" + wire width 64 $0\logical_op__imm_data__data$31[63:0]$10210 + attribute \src "libresoc.v:174872.3-174915.6" + wire $0\logical_op__imm_data__ok$32$next[0:0]$10088 + attribute \src "libresoc.v:174717.3-174718.73" + wire $0\logical_op__imm_data__ok$32[0:0]$10031 + attribute \src "libresoc.v:174271.7-174271.43" + wire $0\logical_op__imm_data__ok$32[0:0]$10212 + attribute \src "libresoc.v:174872.3-174915.6" + wire width 2 $0\logical_op__input_carry$39$next[1:0]$10089 + attribute \src "libresoc.v:174731.3-174732.71" + wire width 2 $0\logical_op__input_carry$39[1:0]$10045 + attribute \src "libresoc.v:174293.13-174293.48" + wire width 2 $0\logical_op__input_carry$39[1:0]$10214 + attribute \src "libresoc.v:174872.3-174915.6" + wire width 32 $0\logical_op__insn$46$next[31:0]$10090 + attribute \src "libresoc.v:174745.3-174746.57" + wire width 32 $0\logical_op__insn$46[31:0]$10059 + attribute \src "libresoc.v:174301.14-174301.43" + wire width 32 $0\logical_op__insn$46[31:0]$10216 + attribute \src "libresoc.v:174872.3-174915.6" + wire width 7 $0\logical_op__insn_type$29$next[6:0]$10091 + attribute \src "libresoc.v:174711.3-174712.67" + wire width 7 $0\logical_op__insn_type$29[6:0]$10025 + attribute \src "libresoc.v:174534.13-174534.47" + wire width 7 $0\logical_op__insn_type$29[6:0]$10218 + attribute \src "libresoc.v:174872.3-174915.6" + wire $0\logical_op__invert_in$37$next[0:0]$10092 + attribute \src "libresoc.v:174727.3-174728.67" + wire $0\logical_op__invert_in$37[0:0]$10041 + attribute \src "libresoc.v:174542.7-174542.40" + wire $0\logical_op__invert_in$37[0:0]$10220 + attribute \src "libresoc.v:174872.3-174915.6" + wire $0\logical_op__invert_out$40$next[0:0]$10093 + attribute \src "libresoc.v:174733.3-174734.69" + wire $0\logical_op__invert_out$40[0:0]$10047 + attribute \src "libresoc.v:174550.7-174550.41" + wire $0\logical_op__invert_out$40[0:0]$10222 + attribute \src "libresoc.v:174872.3-174915.6" + wire $0\logical_op__is_32bit$43$next[0:0]$10094 + attribute \src "libresoc.v:174739.3-174740.65" + wire $0\logical_op__is_32bit$43[0:0]$10053 + attribute \src "libresoc.v:174558.7-174558.39" + wire $0\logical_op__is_32bit$43[0:0]$10224 + attribute \src "libresoc.v:174872.3-174915.6" + wire $0\logical_op__is_signed$44$next[0:0]$10095 + attribute \src "libresoc.v:174741.3-174742.67" + wire $0\logical_op__is_signed$44[0:0]$10055 + attribute \src "libresoc.v:174566.7-174566.40" + wire $0\logical_op__is_signed$44[0:0]$10226 + attribute \src "libresoc.v:174872.3-174915.6" + wire $0\logical_op__oe__oe$35$next[0:0]$10096 + attribute \src "libresoc.v:174723.3-174724.61" + wire $0\logical_op__oe__oe$35[0:0]$10037 + attribute \src "libresoc.v:174572.7-174572.37" + wire $0\logical_op__oe__oe$35[0:0]$10228 + attribute \src "libresoc.v:174872.3-174915.6" + wire $0\logical_op__oe__ok$36$next[0:0]$10097 + attribute \src "libresoc.v:174725.3-174726.61" + wire $0\logical_op__oe__ok$36[0:0]$10039 + attribute \src "libresoc.v:174580.7-174580.37" + wire $0\logical_op__oe__ok$36[0:0]$10230 + attribute \src "libresoc.v:174872.3-174915.6" + wire $0\logical_op__output_carry$42$next[0:0]$10098 + attribute \src "libresoc.v:174737.3-174738.73" + wire $0\logical_op__output_carry$42[0:0]$10051 + attribute \src "libresoc.v:174590.7-174590.43" + wire $0\logical_op__output_carry$42[0:0]$10232 + attribute \src "libresoc.v:174872.3-174915.6" + wire $0\logical_op__rc__ok$34$next[0:0]$10099 + attribute \src "libresoc.v:174721.3-174722.61" + wire $0\logical_op__rc__ok$34[0:0]$10035 + attribute \src "libresoc.v:174596.7-174596.37" + wire $0\logical_op__rc__ok$34[0:0]$10234 + attribute \src "libresoc.v:174872.3-174915.6" + wire $0\logical_op__rc__rc$33$next[0:0]$10100 + attribute \src "libresoc.v:174719.3-174720.61" + wire $0\logical_op__rc__rc$33[0:0]$10033 + attribute \src "libresoc.v:174604.7-174604.37" + wire $0\logical_op__rc__rc$33[0:0]$10236 + attribute \src "libresoc.v:174872.3-174915.6" + wire $0\logical_op__write_cr0$41$next[0:0]$10101 + attribute \src "libresoc.v:174735.3-174736.67" + wire $0\logical_op__write_cr0$41[0:0]$10049 + attribute \src "libresoc.v:174614.7-174614.40" + wire $0\logical_op__write_cr0$41[0:0]$10238 + attribute \src "libresoc.v:174872.3-174915.6" + wire $0\logical_op__zero_a$38$next[0:0]$10102 + attribute \src "libresoc.v:174729.3-174730.61" + wire $0\logical_op__zero_a$38[0:0]$10043 + attribute \src "libresoc.v:174622.7-174622.37" + wire $0\logical_op__zero_a$38[0:0]$10240 + attribute \src "libresoc.v:174857.3-174871.6" + wire width 2 $0\muxid$28$next[1:0]$10081 + attribute \src "libresoc.v:174747.3-174748.35" + wire width 2 $0\muxid$28[1:0]$10061 + attribute \src "libresoc.v:174630.13-174630.30" + wire width 2 $0\muxid$28[1:0]$10242 + attribute \src "libresoc.v:175066.3-175080.6" + wire width 2 $0\operation$69$next[1:0]$10186 + attribute \src "libresoc.v:174689.3-174690.43" + wire width 2 $0\operation$69[1:0]$10003 + attribute \src "libresoc.v:174640.13-174640.34" + wire width 2 $0\operation$69[1:0]$10244 + attribute \src "libresoc.v:174916.3-174930.6" + wire width 64 $0\ra$47$next[63:0]$10146 + attribute \src "libresoc.v:174709.3-174710.29" + wire width 64 $0\ra$47[63:0]$10023 + attribute \src "libresoc.v:174654.14-174654.44" + wire width 64 $0\ra$47[63:0]$10246 + attribute \src "libresoc.v:174931.3-174945.6" + wire width 64 $0\rb$48$next[63:0]$10150 + attribute \src "libresoc.v:174707.3-174708.29" + wire width 64 $0\rb$48[63:0]$10021 + attribute \src "libresoc.v:174662.14-174662.44" + wire width 64 $0\rb$48[63:0]$10248 + attribute \src "libresoc.v:174784.3-174792.6" + wire width 128 $0\saved_state_dividend_quotient$next[127:0]$10069 + attribute \src "libresoc.v:174751.3-174752.75" wire width 128 $0\saved_state_dividend_quotient[127:0] - attribute \src "libresoc.v:173467.3-173475.6" - wire width 7 $0\saved_state_q_bits_known$next[6:0]$10082 - attribute \src "libresoc.v:173445.3-173446.65" + attribute \src "libresoc.v:174775.3-174783.6" + wire width 7 $0\saved_state_q_bits_known$next[6:0]$10066 + attribute \src "libresoc.v:174753.3-174754.65" wire width 7 $0\saved_state_q_bits_known[6:0] - attribute \src "libresoc.v:173638.3-173652.6" - wire $0\xer_so$49$next[0:0]$10170 - attribute \src "libresoc.v:173397.3-173398.37" - wire $0\xer_so$49[0:0]$10035 - attribute \src "libresoc.v:173372.7-173372.25" - wire $0\xer_so$49[0:0]$10268 - attribute \src "libresoc.v:173713.3-173727.6" - wire $1\div_by_zero$54$next[0:0]$10191 - attribute \src "libresoc.v:173509.3-173520.6" + attribute \src "libresoc.v:174946.3-174960.6" + wire $0\xer_so$49$next[0:0]$10154 + attribute \src "libresoc.v:174705.3-174706.37" + wire $0\xer_so$49[0:0]$10019 + attribute \src "libresoc.v:174680.7-174680.25" + wire $0\xer_so$49[0:0]$10252 + attribute \src "libresoc.v:175021.3-175035.6" + wire $1\div_by_zero$54$next[0:0]$10175 + attribute \src "libresoc.v:174817.3-174828.6" wire width 64 $1\div_state_next_divisor[63:0] - attribute \src "libresoc.v:173497.3-173508.6" + attribute \src "libresoc.v:174805.3-174816.6" wire width 128 $1\div_state_next_i_dividend_quotient[127:0] - attribute \src "libresoc.v:173485.3-173496.6" + attribute \src "libresoc.v:174793.3-174804.6" wire width 7 $1\div_state_next_i_q_bits_known[6:0] - attribute \src "libresoc.v:173683.3-173697.6" - wire $1\dive_abs_ov32$52$next[0:0]$10183 - attribute \src "libresoc.v:173698.3-173712.6" - wire $1\dive_abs_ov64$53$next[0:0]$10187 - attribute \src "libresoc.v:173728.3-173742.6" - wire width 128 $1\dividend$68$next[127:0]$10195 - attribute \src "libresoc.v:173668.3-173682.6" - wire $1\dividend_neg$51$next[0:0]$10179 - attribute \src "libresoc.v:173653.3-173667.6" - wire $1\divisor_neg$50$next[0:0]$10175 - attribute \src "libresoc.v:173743.3-173757.6" - wire width 64 $1\divisor_radicand$65$next[63:0]$10199 - attribute \src "libresoc.v:173521.3-173548.6" - wire $1\empty$next[0:0]$10092 - attribute \src "libresoc.v:172888.7-172888.19" + attribute \src "libresoc.v:174991.3-175005.6" + wire $1\dive_abs_ov32$52$next[0:0]$10167 + attribute \src "libresoc.v:175006.3-175020.6" + wire $1\dive_abs_ov64$53$next[0:0]$10171 + attribute \src "libresoc.v:175036.3-175050.6" + wire width 128 $1\dividend$68$next[127:0]$10179 + attribute \src "libresoc.v:174976.3-174990.6" + wire $1\dividend_neg$51$next[0:0]$10163 + attribute \src "libresoc.v:174961.3-174975.6" + wire $1\divisor_neg$50$next[0:0]$10159 + attribute \src "libresoc.v:175051.3-175065.6" + wire width 64 $1\divisor_radicand$65$next[63:0]$10183 + attribute \src "libresoc.v:174829.3-174856.6" + wire $1\empty$next[0:0]$10076 + attribute \src "libresoc.v:174196.7-174196.19" wire $1\empty[0:0] - attribute \src "libresoc.v:173564.3-173607.6" - wire width 4 $1\logical_op__data_len$45$next[3:0]$10119 - attribute \src "libresoc.v:173564.3-173607.6" - wire width 14 $1\logical_op__fn_unit$30$next[13:0]$10120 - attribute \src "libresoc.v:173564.3-173607.6" - wire width 64 $1\logical_op__imm_data__data$31$next[63:0]$10121 - attribute \src "libresoc.v:173564.3-173607.6" - wire $1\logical_op__imm_data__ok$32$next[0:0]$10122 - attribute \src "libresoc.v:173564.3-173607.6" - wire width 2 $1\logical_op__input_carry$39$next[1:0]$10123 - attribute \src "libresoc.v:173564.3-173607.6" - wire width 32 $1\logical_op__insn$46$next[31:0]$10124 - attribute \src "libresoc.v:173564.3-173607.6" - wire width 7 $1\logical_op__insn_type$29$next[6:0]$10125 - attribute \src "libresoc.v:173564.3-173607.6" - wire $1\logical_op__invert_in$37$next[0:0]$10126 - attribute \src "libresoc.v:173564.3-173607.6" - wire $1\logical_op__invert_out$40$next[0:0]$10127 - attribute \src "libresoc.v:173564.3-173607.6" - wire $1\logical_op__is_32bit$43$next[0:0]$10128 - attribute \src "libresoc.v:173564.3-173607.6" - wire $1\logical_op__is_signed$44$next[0:0]$10129 - attribute \src "libresoc.v:173564.3-173607.6" - wire $1\logical_op__oe__oe$35$next[0:0]$10130 - attribute \src "libresoc.v:173564.3-173607.6" - wire $1\logical_op__oe__ok$36$next[0:0]$10131 - attribute \src "libresoc.v:173564.3-173607.6" - wire $1\logical_op__output_carry$42$next[0:0]$10132 - attribute \src "libresoc.v:173564.3-173607.6" - wire $1\logical_op__rc__ok$34$next[0:0]$10133 - attribute \src "libresoc.v:173564.3-173607.6" - wire $1\logical_op__rc__rc$33$next[0:0]$10134 - attribute \src "libresoc.v:173564.3-173607.6" - wire $1\logical_op__write_cr0$41$next[0:0]$10135 - attribute \src "libresoc.v:173564.3-173607.6" - wire $1\logical_op__zero_a$38$next[0:0]$10136 - attribute \src "libresoc.v:173549.3-173563.6" - wire width 2 $1\muxid$28$next[1:0]$10098 - attribute \src "libresoc.v:173758.3-173772.6" - wire width 2 $1\operation$69$next[1:0]$10203 - attribute \src "libresoc.v:173608.3-173622.6" - wire width 64 $1\ra$47$next[63:0]$10163 - attribute \src "libresoc.v:173623.3-173637.6" - wire width 64 $1\rb$48$next[63:0]$10167 - attribute \src "libresoc.v:173476.3-173484.6" - wire width 128 $1\saved_state_dividend_quotient$next[127:0]$10086 - attribute \src "libresoc.v:173360.15-173360.84" + attribute \src "libresoc.v:174872.3-174915.6" + wire width 4 $1\logical_op__data_len$45$next[3:0]$10103 + attribute \src "libresoc.v:174872.3-174915.6" + wire width 14 $1\logical_op__fn_unit$30$next[13:0]$10104 + attribute \src "libresoc.v:174872.3-174915.6" + wire width 64 $1\logical_op__imm_data__data$31$next[63:0]$10105 + attribute \src "libresoc.v:174872.3-174915.6" + wire $1\logical_op__imm_data__ok$32$next[0:0]$10106 + attribute \src "libresoc.v:174872.3-174915.6" + wire width 2 $1\logical_op__input_carry$39$next[1:0]$10107 + attribute \src "libresoc.v:174872.3-174915.6" + wire width 32 $1\logical_op__insn$46$next[31:0]$10108 + attribute \src "libresoc.v:174872.3-174915.6" + wire width 7 $1\logical_op__insn_type$29$next[6:0]$10109 + attribute \src "libresoc.v:174872.3-174915.6" + wire $1\logical_op__invert_in$37$next[0:0]$10110 + attribute \src "libresoc.v:174872.3-174915.6" + wire $1\logical_op__invert_out$40$next[0:0]$10111 + attribute \src "libresoc.v:174872.3-174915.6" + wire $1\logical_op__is_32bit$43$next[0:0]$10112 + attribute \src "libresoc.v:174872.3-174915.6" + wire $1\logical_op__is_signed$44$next[0:0]$10113 + attribute \src "libresoc.v:174872.3-174915.6" + wire $1\logical_op__oe__oe$35$next[0:0]$10114 + attribute \src "libresoc.v:174872.3-174915.6" + wire $1\logical_op__oe__ok$36$next[0:0]$10115 + attribute \src "libresoc.v:174872.3-174915.6" + wire $1\logical_op__output_carry$42$next[0:0]$10116 + attribute \src "libresoc.v:174872.3-174915.6" + wire $1\logical_op__rc__ok$34$next[0:0]$10117 + attribute \src "libresoc.v:174872.3-174915.6" + wire $1\logical_op__rc__rc$33$next[0:0]$10118 + attribute \src "libresoc.v:174872.3-174915.6" + wire $1\logical_op__write_cr0$41$next[0:0]$10119 + attribute \src "libresoc.v:174872.3-174915.6" + wire $1\logical_op__zero_a$38$next[0:0]$10120 + attribute \src "libresoc.v:174857.3-174871.6" + wire width 2 $1\muxid$28$next[1:0]$10082 + attribute \src "libresoc.v:175066.3-175080.6" + wire width 2 $1\operation$69$next[1:0]$10187 + attribute \src "libresoc.v:174916.3-174930.6" + wire width 64 $1\ra$47$next[63:0]$10147 + attribute \src "libresoc.v:174931.3-174945.6" + wire width 64 $1\rb$48$next[63:0]$10151 + attribute \src "libresoc.v:174784.3-174792.6" + wire width 128 $1\saved_state_dividend_quotient$next[127:0]$10070 + attribute \src "libresoc.v:174668.15-174668.84" wire width 128 $1\saved_state_dividend_quotient[127:0] - attribute \src "libresoc.v:173467.3-173475.6" - wire width 7 $1\saved_state_q_bits_known$next[6:0]$10083 - attribute \src "libresoc.v:173364.13-173364.45" + attribute \src "libresoc.v:174775.3-174783.6" + wire width 7 $1\saved_state_q_bits_known$next[6:0]$10067 + attribute \src "libresoc.v:174672.13-174672.45" wire width 7 $1\saved_state_q_bits_known[6:0] - attribute \src "libresoc.v:173638.3-173652.6" - wire $1\xer_so$49$next[0:0]$10171 - attribute \src "libresoc.v:173713.3-173727.6" - wire $2\div_by_zero$54$next[0:0]$10192 - attribute \src "libresoc.v:173683.3-173697.6" - wire $2\dive_abs_ov32$52$next[0:0]$10184 - attribute \src "libresoc.v:173698.3-173712.6" - wire $2\dive_abs_ov64$53$next[0:0]$10188 - attribute \src "libresoc.v:173728.3-173742.6" - wire width 128 $2\dividend$68$next[127:0]$10196 - attribute \src "libresoc.v:173668.3-173682.6" - wire $2\dividend_neg$51$next[0:0]$10180 - attribute \src "libresoc.v:173653.3-173667.6" - wire $2\divisor_neg$50$next[0:0]$10176 - attribute \src "libresoc.v:173743.3-173757.6" - wire width 64 $2\divisor_radicand$65$next[63:0]$10200 - attribute \src "libresoc.v:173521.3-173548.6" - wire $2\empty$next[0:0]$10093 - attribute \src "libresoc.v:173564.3-173607.6" - wire width 4 $2\logical_op__data_len$45$next[3:0]$10137 - attribute \src "libresoc.v:173564.3-173607.6" - wire width 14 $2\logical_op__fn_unit$30$next[13:0]$10138 - attribute \src "libresoc.v:173564.3-173607.6" - wire width 64 $2\logical_op__imm_data__data$31$next[63:0]$10139 - attribute \src "libresoc.v:173564.3-173607.6" - wire $2\logical_op__imm_data__ok$32$next[0:0]$10140 - attribute \src "libresoc.v:173564.3-173607.6" - wire width 2 $2\logical_op__input_carry$39$next[1:0]$10141 - attribute \src "libresoc.v:173564.3-173607.6" - wire width 32 $2\logical_op__insn$46$next[31:0]$10142 - attribute \src "libresoc.v:173564.3-173607.6" - wire width 7 $2\logical_op__insn_type$29$next[6:0]$10143 - attribute \src "libresoc.v:173564.3-173607.6" - wire $2\logical_op__invert_in$37$next[0:0]$10144 - attribute \src "libresoc.v:173564.3-173607.6" - wire $2\logical_op__invert_out$40$next[0:0]$10145 - attribute \src "libresoc.v:173564.3-173607.6" - wire $2\logical_op__is_32bit$43$next[0:0]$10146 - attribute \src "libresoc.v:173564.3-173607.6" - wire $2\logical_op__is_signed$44$next[0:0]$10147 - attribute \src "libresoc.v:173564.3-173607.6" - wire $2\logical_op__oe__oe$35$next[0:0]$10148 - attribute \src "libresoc.v:173564.3-173607.6" - wire $2\logical_op__oe__ok$36$next[0:0]$10149 - attribute \src "libresoc.v:173564.3-173607.6" - wire $2\logical_op__output_carry$42$next[0:0]$10150 - attribute \src "libresoc.v:173564.3-173607.6" - wire $2\logical_op__rc__ok$34$next[0:0]$10151 - attribute \src "libresoc.v:173564.3-173607.6" - wire $2\logical_op__rc__rc$33$next[0:0]$10152 - attribute \src "libresoc.v:173564.3-173607.6" - wire $2\logical_op__write_cr0$41$next[0:0]$10153 - attribute \src "libresoc.v:173564.3-173607.6" - wire $2\logical_op__zero_a$38$next[0:0]$10154 - attribute \src "libresoc.v:173549.3-173563.6" - wire width 2 $2\muxid$28$next[1:0]$10099 - attribute \src "libresoc.v:173758.3-173772.6" - wire width 2 $2\operation$69$next[1:0]$10204 - attribute \src "libresoc.v:173608.3-173622.6" - wire width 64 $2\ra$47$next[63:0]$10164 - attribute \src "libresoc.v:173623.3-173637.6" - wire width 64 $2\rb$48$next[63:0]$10168 - attribute \src "libresoc.v:173638.3-173652.6" - wire $2\xer_so$49$next[0:0]$10172 - attribute \src "libresoc.v:173521.3-173548.6" - wire $3\empty$next[0:0]$10094 - attribute \src "libresoc.v:173564.3-173607.6" - wire width 64 $3\logical_op__imm_data__data$31$next[63:0]$10155 - attribute \src "libresoc.v:173564.3-173607.6" - wire $3\logical_op__imm_data__ok$32$next[0:0]$10156 - attribute \src "libresoc.v:173564.3-173607.6" - wire $3\logical_op__oe__oe$35$next[0:0]$10157 - attribute \src "libresoc.v:173564.3-173607.6" - wire $3\logical_op__oe__ok$36$next[0:0]$10158 - attribute \src "libresoc.v:173564.3-173607.6" - wire $3\logical_op__rc__ok$34$next[0:0]$10159 - attribute \src "libresoc.v:173564.3-173607.6" - wire $3\logical_op__rc__rc$33$next[0:0]$10160 - attribute \src "libresoc.v:173521.3-173548.6" - wire $4\empty$next[0:0]$10095 - attribute \src "libresoc.v:173379.18-173379.98" - wire $and$libresoc.v:173379$10016_Y - attribute \src "libresoc.v:173380.18-173380.107" - wire $and$libresoc.v:173380$10017_Y - attribute \src "libresoc.v:173376.18-173376.92" - wire width 192 $extend$libresoc.v:173376$10012_Y - attribute \src "libresoc.v:173378.18-173378.119" - wire $ge$libresoc.v:173378$10015_Y - attribute \src "libresoc.v:173377.18-173377.93" - wire $not$libresoc.v:173377$10014_Y - attribute \src "libresoc.v:173376.18-173376.92" - wire width 192 $pos$libresoc.v:173376$10013_Y - attribute \src "libresoc.v:173375.18-173375.138" - wire width 191 $sshl$libresoc.v:173375$10011_Y + attribute \src "libresoc.v:174946.3-174960.6" + wire $1\xer_so$49$next[0:0]$10155 + attribute \src "libresoc.v:175021.3-175035.6" + wire $2\div_by_zero$54$next[0:0]$10176 + attribute \src "libresoc.v:174991.3-175005.6" + wire $2\dive_abs_ov32$52$next[0:0]$10168 + attribute \src "libresoc.v:175006.3-175020.6" + wire $2\dive_abs_ov64$53$next[0:0]$10172 + attribute \src "libresoc.v:175036.3-175050.6" + wire width 128 $2\dividend$68$next[127:0]$10180 + attribute \src "libresoc.v:174976.3-174990.6" + wire $2\dividend_neg$51$next[0:0]$10164 + attribute \src "libresoc.v:174961.3-174975.6" + wire $2\divisor_neg$50$next[0:0]$10160 + attribute \src "libresoc.v:175051.3-175065.6" + wire width 64 $2\divisor_radicand$65$next[63:0]$10184 + attribute \src "libresoc.v:174829.3-174856.6" + wire $2\empty$next[0:0]$10077 + attribute \src "libresoc.v:174872.3-174915.6" + wire width 4 $2\logical_op__data_len$45$next[3:0]$10121 + attribute \src "libresoc.v:174872.3-174915.6" + wire width 14 $2\logical_op__fn_unit$30$next[13:0]$10122 + attribute \src "libresoc.v:174872.3-174915.6" + wire width 64 $2\logical_op__imm_data__data$31$next[63:0]$10123 + attribute \src "libresoc.v:174872.3-174915.6" + wire $2\logical_op__imm_data__ok$32$next[0:0]$10124 + attribute \src "libresoc.v:174872.3-174915.6" + wire width 2 $2\logical_op__input_carry$39$next[1:0]$10125 + attribute \src "libresoc.v:174872.3-174915.6" + wire width 32 $2\logical_op__insn$46$next[31:0]$10126 + attribute \src "libresoc.v:174872.3-174915.6" + wire width 7 $2\logical_op__insn_type$29$next[6:0]$10127 + attribute \src "libresoc.v:174872.3-174915.6" + wire $2\logical_op__invert_in$37$next[0:0]$10128 + attribute \src "libresoc.v:174872.3-174915.6" + wire $2\logical_op__invert_out$40$next[0:0]$10129 + attribute \src "libresoc.v:174872.3-174915.6" + wire $2\logical_op__is_32bit$43$next[0:0]$10130 + attribute \src "libresoc.v:174872.3-174915.6" + wire $2\logical_op__is_signed$44$next[0:0]$10131 + attribute \src "libresoc.v:174872.3-174915.6" + wire $2\logical_op__oe__oe$35$next[0:0]$10132 + attribute \src "libresoc.v:174872.3-174915.6" + wire $2\logical_op__oe__ok$36$next[0:0]$10133 + attribute \src "libresoc.v:174872.3-174915.6" + wire $2\logical_op__output_carry$42$next[0:0]$10134 + attribute \src "libresoc.v:174872.3-174915.6" + wire $2\logical_op__rc__ok$34$next[0:0]$10135 + attribute \src "libresoc.v:174872.3-174915.6" + wire $2\logical_op__rc__rc$33$next[0:0]$10136 + attribute \src "libresoc.v:174872.3-174915.6" + wire $2\logical_op__write_cr0$41$next[0:0]$10137 + attribute \src "libresoc.v:174872.3-174915.6" + wire $2\logical_op__zero_a$38$next[0:0]$10138 + attribute \src "libresoc.v:174857.3-174871.6" + wire width 2 $2\muxid$28$next[1:0]$10083 + attribute \src "libresoc.v:175066.3-175080.6" + wire width 2 $2\operation$69$next[1:0]$10188 + attribute \src "libresoc.v:174916.3-174930.6" + wire width 64 $2\ra$47$next[63:0]$10148 + attribute \src "libresoc.v:174931.3-174945.6" + wire width 64 $2\rb$48$next[63:0]$10152 + attribute \src "libresoc.v:174946.3-174960.6" + wire $2\xer_so$49$next[0:0]$10156 + attribute \src "libresoc.v:174829.3-174856.6" + wire $3\empty$next[0:0]$10078 + attribute \src "libresoc.v:174872.3-174915.6" + wire width 64 $3\logical_op__imm_data__data$31$next[63:0]$10139 + attribute \src "libresoc.v:174872.3-174915.6" + wire $3\logical_op__imm_data__ok$32$next[0:0]$10140 + attribute \src "libresoc.v:174872.3-174915.6" + wire $3\logical_op__oe__oe$35$next[0:0]$10141 + attribute \src "libresoc.v:174872.3-174915.6" + wire $3\logical_op__oe__ok$36$next[0:0]$10142 + attribute \src "libresoc.v:174872.3-174915.6" + wire $3\logical_op__rc__ok$34$next[0:0]$10143 + attribute \src "libresoc.v:174872.3-174915.6" + wire $3\logical_op__rc__rc$33$next[0:0]$10144 + attribute \src "libresoc.v:174829.3-174856.6" + wire $4\empty$next[0:0]$10079 + attribute \src "libresoc.v:174687.18-174687.98" + wire $and$libresoc.v:174687$10000_Y + attribute \src "libresoc.v:174688.18-174688.107" + wire $and$libresoc.v:174688$10001_Y + attribute \src "libresoc.v:174684.18-174684.92" + wire width 192 $extend$libresoc.v:174684$9996_Y + attribute \src "libresoc.v:174686.18-174686.119" + wire $ge$libresoc.v:174686$9999_Y + attribute \src "libresoc.v:174685.18-174685.93" + wire $not$libresoc.v:174685$9998_Y + attribute \src "libresoc.v:174684.18-174684.92" + wire width 192 $pos$libresoc.v:174684$9997_Y + attribute \src "libresoc.v:174683.18-174683.138" + wire width 191 $sshl$libresoc.v:174683$9995_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" wire width 192 \$55 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" @@ -351427,9 +322797,9 @@ module \pipe_middle_0 wire \$63 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" wire \$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 65 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire input 30 \div_by_zero @@ -351503,7 +322873,7 @@ module \pipe_middle_0 wire \empty attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:140" wire \empty$next - attribute \src "libresoc.v:172802.7-172802.15" + attribute \src "libresoc.v:174110.7-174110.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 21 \logical_op__data_len @@ -351990,7 +323360,7 @@ module \pipe_middle_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \xer_so$49$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" - cell $and $and$libresoc.v:173379$10016 + cell $and $and$libresoc.v:174687$10000 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -351998,10 +323368,10 @@ module \pipe_middle_0 parameter \Y_WIDTH 1 connect \A \$59 connect \B \$61 - connect \Y $and$libresoc.v:173379$10016_Y + connect \Y $and$libresoc.v:174687$10000_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - cell $and $and$libresoc.v:173380$10017 + cell $and $and$libresoc.v:174688$10001 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -352009,18 +323379,18 @@ module \pipe_middle_0 parameter \Y_WIDTH 1 connect \A \n_ready_i connect \B \n_valid_o - connect \Y $and$libresoc.v:173380$10017_Y + connect \Y $and$libresoc.v:174688$10001_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" - cell $pos $extend$libresoc.v:173376$10012 + cell $pos $extend$libresoc.v:174684$9996 parameter \A_SIGNED 0 parameter \A_WIDTH 191 parameter \Y_WIDTH 192 connect \A \$56 - connect \Y $extend$libresoc.v:173376$10012_Y + connect \Y $extend$libresoc.v:174684$9996_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:116" - cell $ge $ge$libresoc.v:173378$10015 + cell $ge $ge$libresoc.v:174686$9999 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -352028,26 +323398,26 @@ module \pipe_middle_0 parameter \Y_WIDTH 1 connect \A \saved_state_q_bits_known connect \B 6'111111 - connect \Y $ge$libresoc.v:173378$10015_Y + connect \Y $ge$libresoc.v:174686$9999_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:171" - cell $not $not$libresoc.v:173377$10014 + cell $not $not$libresoc.v:174685$9998 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \empty - connect \Y $not$libresoc.v:173377$10014_Y + connect \Y $not$libresoc.v:174685$9998_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" - cell $pos $pos$libresoc.v:173376$10013 + cell $pos $pos$libresoc.v:174684$9997 parameter \A_SIGNED 0 parameter \A_WIDTH 192 parameter \Y_WIDTH 192 - connect \A $extend$libresoc.v:173376$10012_Y - connect \Y $pos$libresoc.v:173376$10013_Y + connect \A $extend$libresoc.v:174684$9996_Y + connect \Y $pos$libresoc.v:174684$9997_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:169" - cell $sshl $sshl$libresoc.v:173375$10011 + cell $sshl $sshl$libresoc.v:174683$9995 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -352055,17 +323425,17 @@ module \pipe_middle_0 parameter \Y_WIDTH 191 connect \A \div_state_next_o_dividend_quotient [127:64] connect \B 7'1000000 - connect \Y $sshl$libresoc.v:173375$10011_Y + connect \Y $sshl$libresoc.v:174683$9995_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:173447.18-173451.4" + attribute \src "libresoc.v:174755.18-174759.4" cell \div_state_init \div_state_init connect \dividend \div_state_init_dividend connect \o_dividend_quotient \div_state_init_o_dividend_quotient connect \o_q_bits_known \div_state_init_o_q_bits_known end attribute \module_not_derived 1 - attribute \src "libresoc.v:173452.18-173458.4" + attribute \src "libresoc.v:174760.18-174766.4" cell \div_state_next \div_state_next connect \divisor \div_state_next_divisor connect \i_dividend_quotient \div_state_next_i_dividend_quotient @@ -352074,528 +323444,528 @@ module \pipe_middle_0 connect \o_q_bits_known \div_state_next_o_q_bits_known end attribute \module_not_derived 1 - attribute \src "libresoc.v:173459.10-173462.4" + attribute \src "libresoc.v:174767.10-174770.4" cell \n$80 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:173463.10-173466.4" + attribute \src "libresoc.v:174771.10-174774.4" cell \p$79 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end - attribute \src "libresoc.v:172802.7-172802.20" - process $proc$libresoc.v:172802$10205 + attribute \src "libresoc.v:174110.7-174110.20" + process $proc$libresoc.v:174110$10189 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:172824.7-172824.30" - process $proc$libresoc.v:172824$10206 + attribute \src "libresoc.v:174132.7-174132.30" + process $proc$libresoc.v:174132$10190 assign { } { } - assign $0\div_by_zero$54[0:0]$10207 1'0 + assign $0\div_by_zero$54[0:0]$10191 1'0 sync always sync init - update \div_by_zero$54 $0\div_by_zero$54[0:0]$10207 + update \div_by_zero$54 $0\div_by_zero$54[0:0]$10191 end - attribute \src "libresoc.v:172848.7-172848.32" - process $proc$libresoc.v:172848$10208 + attribute \src "libresoc.v:174156.7-174156.32" + process $proc$libresoc.v:174156$10192 assign { } { } - assign $0\dive_abs_ov32$52[0:0]$10209 1'0 + assign $0\dive_abs_ov32$52[0:0]$10193 1'0 sync always sync init - update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$10209 + update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$10193 end - attribute \src "libresoc.v:172856.7-172856.32" - process $proc$libresoc.v:172856$10210 + attribute \src "libresoc.v:174164.7-174164.32" + process $proc$libresoc.v:174164$10194 assign { } { } - assign $0\dive_abs_ov64$53[0:0]$10211 1'0 + assign $0\dive_abs_ov64$53[0:0]$10195 1'0 sync always sync init - update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$10211 + update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$10195 end - attribute \src "libresoc.v:172862.15-172862.68" - process $proc$libresoc.v:172862$10212 + attribute \src "libresoc.v:174170.15-174170.68" + process $proc$libresoc.v:174170$10196 assign { } { } - assign $0\dividend$68[127:0]$10213 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $0\dividend$68[127:0]$10197 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \dividend$68 $0\dividend$68[127:0]$10213 + update \dividend$68 $0\dividend$68[127:0]$10197 end - attribute \src "libresoc.v:172870.7-172870.31" - process $proc$libresoc.v:172870$10214 + attribute \src "libresoc.v:174178.7-174178.31" + process $proc$libresoc.v:174178$10198 assign { } { } - assign $0\dividend_neg$51[0:0]$10215 1'0 + assign $0\dividend_neg$51[0:0]$10199 1'0 sync always sync init - update \dividend_neg$51 $0\dividend_neg$51[0:0]$10215 + update \dividend_neg$51 $0\dividend_neg$51[0:0]$10199 end - attribute \src "libresoc.v:172878.7-172878.30" - process $proc$libresoc.v:172878$10216 + attribute \src "libresoc.v:174186.7-174186.30" + process $proc$libresoc.v:174186$10200 assign { } { } - assign $0\divisor_neg$50[0:0]$10217 1'0 + assign $0\divisor_neg$50[0:0]$10201 1'0 sync always sync init - update \divisor_neg$50 $0\divisor_neg$50[0:0]$10217 + update \divisor_neg$50 $0\divisor_neg$50[0:0]$10201 end - attribute \src "libresoc.v:172884.14-172884.58" - process $proc$libresoc.v:172884$10218 + attribute \src "libresoc.v:174192.14-174192.58" + process $proc$libresoc.v:174192$10202 assign { } { } - assign $0\divisor_radicand$65[63:0]$10219 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\divisor_radicand$65[63:0]$10203 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$10219 + update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$10203 end - attribute \src "libresoc.v:172888.7-172888.19" - process $proc$libresoc.v:172888$10220 + attribute \src "libresoc.v:174196.7-174196.19" + process $proc$libresoc.v:174196$10204 assign { } { } assign $1\empty[0:0] 1'1 sync always sync init update \empty $1\empty[0:0] end - attribute \src "libresoc.v:172896.13-172896.45" - process $proc$libresoc.v:172896$10221 + attribute \src "libresoc.v:174204.13-174204.45" + process $proc$libresoc.v:174204$10205 assign { } { } - assign $0\logical_op__data_len$45[3:0]$10222 4'0000 + assign $0\logical_op__data_len$45[3:0]$10206 4'0000 sync always sync init - update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$10222 + update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$10206 end - attribute \src "libresoc.v:172949.14-172949.49" - process $proc$libresoc.v:172949$10223 + attribute \src "libresoc.v:174257.14-174257.49" + process $proc$libresoc.v:174257$10207 assign { } { } - assign $0\logical_op__fn_unit$30[13:0]$10224 14'00000000000000 + assign $0\logical_op__fn_unit$30[13:0]$10208 14'00000000000000 sync always sync init - update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[13:0]$10224 + update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[13:0]$10208 end - attribute \src "libresoc.v:172955.14-172955.68" - process $proc$libresoc.v:172955$10225 + attribute \src "libresoc.v:174263.14-174263.68" + process $proc$libresoc.v:174263$10209 assign { } { } - assign $0\logical_op__imm_data__data$31[63:0]$10226 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\logical_op__imm_data__data$31[63:0]$10210 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$10226 + update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$10210 end - attribute \src "libresoc.v:172963.7-172963.43" - process $proc$libresoc.v:172963$10227 + attribute \src "libresoc.v:174271.7-174271.43" + process $proc$libresoc.v:174271$10211 assign { } { } - assign $0\logical_op__imm_data__ok$32[0:0]$10228 1'0 + assign $0\logical_op__imm_data__ok$32[0:0]$10212 1'0 sync always sync init - update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$10228 + update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$10212 end - attribute \src "libresoc.v:172985.13-172985.48" - process $proc$libresoc.v:172985$10229 + attribute \src "libresoc.v:174293.13-174293.48" + process $proc$libresoc.v:174293$10213 assign { } { } - assign $0\logical_op__input_carry$39[1:0]$10230 2'00 + assign $0\logical_op__input_carry$39[1:0]$10214 2'00 sync always sync init - update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$10230 + update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$10214 end - attribute \src "libresoc.v:172993.14-172993.43" - process $proc$libresoc.v:172993$10231 + attribute \src "libresoc.v:174301.14-174301.43" + process $proc$libresoc.v:174301$10215 assign { } { } - assign $0\logical_op__insn$46[31:0]$10232 0 + assign $0\logical_op__insn$46[31:0]$10216 0 sync always sync init - update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$10232 + update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$10216 end - attribute \src "libresoc.v:173226.13-173226.47" - process $proc$libresoc.v:173226$10233 + attribute \src "libresoc.v:174534.13-174534.47" + process $proc$libresoc.v:174534$10217 assign { } { } - assign $0\logical_op__insn_type$29[6:0]$10234 7'0000000 + assign $0\logical_op__insn_type$29[6:0]$10218 7'0000000 sync always sync init - update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$10234 + update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$10218 end - attribute \src "libresoc.v:173234.7-173234.40" - process $proc$libresoc.v:173234$10235 + attribute \src "libresoc.v:174542.7-174542.40" + process $proc$libresoc.v:174542$10219 assign { } { } - assign $0\logical_op__invert_in$37[0:0]$10236 1'0 + assign $0\logical_op__invert_in$37[0:0]$10220 1'0 sync always sync init - update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$10236 + update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$10220 end - attribute \src "libresoc.v:173242.7-173242.41" - process $proc$libresoc.v:173242$10237 + attribute \src "libresoc.v:174550.7-174550.41" + process $proc$libresoc.v:174550$10221 assign { } { } - assign $0\logical_op__invert_out$40[0:0]$10238 1'0 + assign $0\logical_op__invert_out$40[0:0]$10222 1'0 sync always sync init - update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$10238 + update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$10222 end - attribute \src "libresoc.v:173250.7-173250.39" - process $proc$libresoc.v:173250$10239 + attribute \src "libresoc.v:174558.7-174558.39" + process $proc$libresoc.v:174558$10223 assign { } { } - assign $0\logical_op__is_32bit$43[0:0]$10240 1'0 + assign $0\logical_op__is_32bit$43[0:0]$10224 1'0 sync always sync init - update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$10240 + update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$10224 end - attribute \src "libresoc.v:173258.7-173258.40" - process $proc$libresoc.v:173258$10241 + attribute \src "libresoc.v:174566.7-174566.40" + process $proc$libresoc.v:174566$10225 assign { } { } - assign $0\logical_op__is_signed$44[0:0]$10242 1'0 + assign $0\logical_op__is_signed$44[0:0]$10226 1'0 sync always sync init - update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$10242 + update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$10226 end - attribute \src "libresoc.v:173264.7-173264.37" - process $proc$libresoc.v:173264$10243 + attribute \src "libresoc.v:174572.7-174572.37" + process $proc$libresoc.v:174572$10227 assign { } { } - assign $0\logical_op__oe__oe$35[0:0]$10244 1'0 + assign $0\logical_op__oe__oe$35[0:0]$10228 1'0 sync always sync init - update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$10244 + update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$10228 end - attribute \src "libresoc.v:173272.7-173272.37" - process $proc$libresoc.v:173272$10245 + attribute \src "libresoc.v:174580.7-174580.37" + process $proc$libresoc.v:174580$10229 assign { } { } - assign $0\logical_op__oe__ok$36[0:0]$10246 1'0 + assign $0\logical_op__oe__ok$36[0:0]$10230 1'0 sync always sync init - update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$10246 + update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$10230 end - attribute \src "libresoc.v:173282.7-173282.43" - process $proc$libresoc.v:173282$10247 + attribute \src "libresoc.v:174590.7-174590.43" + process $proc$libresoc.v:174590$10231 assign { } { } - assign $0\logical_op__output_carry$42[0:0]$10248 1'0 + assign $0\logical_op__output_carry$42[0:0]$10232 1'0 sync always sync init - update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$10248 + update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$10232 end - attribute \src "libresoc.v:173288.7-173288.37" - process $proc$libresoc.v:173288$10249 + attribute \src "libresoc.v:174596.7-174596.37" + process $proc$libresoc.v:174596$10233 assign { } { } - assign $0\logical_op__rc__ok$34[0:0]$10250 1'0 + assign $0\logical_op__rc__ok$34[0:0]$10234 1'0 sync always sync init - update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$10250 + update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$10234 end - attribute \src "libresoc.v:173296.7-173296.37" - process $proc$libresoc.v:173296$10251 + attribute \src "libresoc.v:174604.7-174604.37" + process $proc$libresoc.v:174604$10235 assign { } { } - assign $0\logical_op__rc__rc$33[0:0]$10252 1'0 + assign $0\logical_op__rc__rc$33[0:0]$10236 1'0 sync always sync init - update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$10252 + update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$10236 end - attribute \src "libresoc.v:173306.7-173306.40" - process $proc$libresoc.v:173306$10253 + attribute \src "libresoc.v:174614.7-174614.40" + process $proc$libresoc.v:174614$10237 assign { } { } - assign $0\logical_op__write_cr0$41[0:0]$10254 1'0 + assign $0\logical_op__write_cr0$41[0:0]$10238 1'0 sync always sync init - update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$10254 + update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$10238 end - attribute \src "libresoc.v:173314.7-173314.37" - process $proc$libresoc.v:173314$10255 + attribute \src "libresoc.v:174622.7-174622.37" + process $proc$libresoc.v:174622$10239 assign { } { } - assign $0\logical_op__zero_a$38[0:0]$10256 1'0 + assign $0\logical_op__zero_a$38[0:0]$10240 1'0 sync always sync init - update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$10256 + update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$10240 end - attribute \src "libresoc.v:173322.13-173322.30" - process $proc$libresoc.v:173322$10257 + attribute \src "libresoc.v:174630.13-174630.30" + process $proc$libresoc.v:174630$10241 assign { } { } - assign $0\muxid$28[1:0]$10258 2'00 + assign $0\muxid$28[1:0]$10242 2'00 sync always sync init - update \muxid$28 $0\muxid$28[1:0]$10258 + update \muxid$28 $0\muxid$28[1:0]$10242 end - attribute \src "libresoc.v:173332.13-173332.34" - process $proc$libresoc.v:173332$10259 + attribute \src "libresoc.v:174640.13-174640.34" + process $proc$libresoc.v:174640$10243 assign { } { } - assign $0\operation$69[1:0]$10260 2'00 + assign $0\operation$69[1:0]$10244 2'00 sync always sync init - update \operation$69 $0\operation$69[1:0]$10260 + update \operation$69 $0\operation$69[1:0]$10244 end - attribute \src "libresoc.v:173346.14-173346.44" - process $proc$libresoc.v:173346$10261 + attribute \src "libresoc.v:174654.14-174654.44" + process $proc$libresoc.v:174654$10245 assign { } { } - assign $0\ra$47[63:0]$10262 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\ra$47[63:0]$10246 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \ra$47 $0\ra$47[63:0]$10262 + update \ra$47 $0\ra$47[63:0]$10246 end - attribute \src "libresoc.v:173354.14-173354.44" - process $proc$libresoc.v:173354$10263 + attribute \src "libresoc.v:174662.14-174662.44" + process $proc$libresoc.v:174662$10247 assign { } { } - assign $0\rb$48[63:0]$10264 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\rb$48[63:0]$10248 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init - update \rb$48 $0\rb$48[63:0]$10264 + update \rb$48 $0\rb$48[63:0]$10248 end - attribute \src "libresoc.v:173360.15-173360.84" - process $proc$libresoc.v:173360$10265 + attribute \src "libresoc.v:174668.15-174668.84" + process $proc$libresoc.v:174668$10249 assign { } { } assign $1\saved_state_dividend_quotient[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \saved_state_dividend_quotient $1\saved_state_dividend_quotient[127:0] end - attribute \src "libresoc.v:173364.13-173364.45" - process $proc$libresoc.v:173364$10266 + attribute \src "libresoc.v:174672.13-174672.45" + process $proc$libresoc.v:174672$10250 assign { } { } assign $1\saved_state_q_bits_known[6:0] 7'0000000 sync always sync init update \saved_state_q_bits_known $1\saved_state_q_bits_known[6:0] end - attribute \src "libresoc.v:173372.7-173372.25" - process $proc$libresoc.v:173372$10267 + attribute \src "libresoc.v:174680.7-174680.25" + process $proc$libresoc.v:174680$10251 assign { } { } - assign $0\xer_so$49[0:0]$10268 1'0 + assign $0\xer_so$49[0:0]$10252 1'0 sync always sync init - update \xer_so$49 $0\xer_so$49[0:0]$10268 + update \xer_so$49 $0\xer_so$49[0:0]$10252 end - attribute \src "libresoc.v:173381.3-173382.43" - process $proc$libresoc.v:173381$10018 + attribute \src "libresoc.v:174689.3-174690.43" + process $proc$libresoc.v:174689$10002 assign { } { } - assign $0\operation$69[1:0]$10019 \operation$69$next + assign $0\operation$69[1:0]$10003 \operation$69$next sync posedge \coresync_clk - update \operation$69 $0\operation$69[1:0]$10019 + update \operation$69 $0\operation$69[1:0]$10003 end - attribute \src "libresoc.v:173383.3-173384.57" - process $proc$libresoc.v:173383$10020 + attribute \src "libresoc.v:174691.3-174692.57" + process $proc$libresoc.v:174691$10004 assign { } { } - assign $0\divisor_radicand$65[63:0]$10021 \divisor_radicand$65$next + assign $0\divisor_radicand$65[63:0]$10005 \divisor_radicand$65$next sync posedge \coresync_clk - update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$10021 + update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$10005 end - attribute \src "libresoc.v:173385.3-173386.41" - process $proc$libresoc.v:173385$10022 + attribute \src "libresoc.v:174693.3-174694.41" + process $proc$libresoc.v:174693$10006 assign { } { } - assign $0\dividend$68[127:0]$10023 \dividend$68$next + assign $0\dividend$68[127:0]$10007 \dividend$68$next sync posedge \coresync_clk - update \dividend$68 $0\dividend$68[127:0]$10023 + update \dividend$68 $0\dividend$68[127:0]$10007 end - attribute \src "libresoc.v:173387.3-173388.47" - process $proc$libresoc.v:173387$10024 + attribute \src "libresoc.v:174695.3-174696.47" + process $proc$libresoc.v:174695$10008 assign { } { } - assign $0\div_by_zero$54[0:0]$10025 \div_by_zero$54$next + assign $0\div_by_zero$54[0:0]$10009 \div_by_zero$54$next sync posedge \coresync_clk - update \div_by_zero$54 $0\div_by_zero$54[0:0]$10025 + update \div_by_zero$54 $0\div_by_zero$54[0:0]$10009 end - attribute \src "libresoc.v:173389.3-173390.51" - process $proc$libresoc.v:173389$10026 + attribute \src "libresoc.v:174697.3-174698.51" + process $proc$libresoc.v:174697$10010 assign { } { } - assign $0\dive_abs_ov64$53[0:0]$10027 \dive_abs_ov64$53$next + assign $0\dive_abs_ov64$53[0:0]$10011 \dive_abs_ov64$53$next sync posedge \coresync_clk - update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$10027 + update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$10011 end - attribute \src "libresoc.v:173391.3-173392.51" - process $proc$libresoc.v:173391$10028 + attribute \src "libresoc.v:174699.3-174700.51" + process $proc$libresoc.v:174699$10012 assign { } { } - assign $0\dive_abs_ov32$52[0:0]$10029 \dive_abs_ov32$52$next + assign $0\dive_abs_ov32$52[0:0]$10013 \dive_abs_ov32$52$next sync posedge \coresync_clk - update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$10029 + update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$10013 end - attribute \src "libresoc.v:173393.3-173394.49" - process $proc$libresoc.v:173393$10030 + attribute \src "libresoc.v:174701.3-174702.49" + process $proc$libresoc.v:174701$10014 assign { } { } - assign $0\dividend_neg$51[0:0]$10031 \dividend_neg$51$next + assign $0\dividend_neg$51[0:0]$10015 \dividend_neg$51$next sync posedge \coresync_clk - update \dividend_neg$51 $0\dividend_neg$51[0:0]$10031 + update \dividend_neg$51 $0\dividend_neg$51[0:0]$10015 end - attribute \src "libresoc.v:173395.3-173396.47" - process $proc$libresoc.v:173395$10032 + attribute \src "libresoc.v:174703.3-174704.47" + process $proc$libresoc.v:174703$10016 assign { } { } - assign $0\divisor_neg$50[0:0]$10033 \divisor_neg$50$next + assign $0\divisor_neg$50[0:0]$10017 \divisor_neg$50$next sync posedge \coresync_clk - update \divisor_neg$50 $0\divisor_neg$50[0:0]$10033 + update \divisor_neg$50 $0\divisor_neg$50[0:0]$10017 end - attribute \src "libresoc.v:173397.3-173398.37" - process $proc$libresoc.v:173397$10034 + attribute \src "libresoc.v:174705.3-174706.37" + process $proc$libresoc.v:174705$10018 assign { } { } - assign $0\xer_so$49[0:0]$10035 \xer_so$49$next + assign $0\xer_so$49[0:0]$10019 \xer_so$49$next sync posedge \coresync_clk - update \xer_so$49 $0\xer_so$49[0:0]$10035 + update \xer_so$49 $0\xer_so$49[0:0]$10019 end - attribute \src "libresoc.v:173399.3-173400.29" - process $proc$libresoc.v:173399$10036 + attribute \src "libresoc.v:174707.3-174708.29" + process $proc$libresoc.v:174707$10020 assign { } { } - assign $0\rb$48[63:0]$10037 \rb$48$next + assign $0\rb$48[63:0]$10021 \rb$48$next sync posedge \coresync_clk - update \rb$48 $0\rb$48[63:0]$10037 + update \rb$48 $0\rb$48[63:0]$10021 end - attribute \src "libresoc.v:173401.3-173402.29" - process $proc$libresoc.v:173401$10038 + attribute \src "libresoc.v:174709.3-174710.29" + process $proc$libresoc.v:174709$10022 assign { } { } - assign $0\ra$47[63:0]$10039 \ra$47$next + assign $0\ra$47[63:0]$10023 \ra$47$next sync posedge \coresync_clk - update \ra$47 $0\ra$47[63:0]$10039 + update \ra$47 $0\ra$47[63:0]$10023 end - attribute \src "libresoc.v:173403.3-173404.67" - process $proc$libresoc.v:173403$10040 + attribute \src "libresoc.v:174711.3-174712.67" + process $proc$libresoc.v:174711$10024 assign { } { } - assign $0\logical_op__insn_type$29[6:0]$10041 \logical_op__insn_type$29$next + assign $0\logical_op__insn_type$29[6:0]$10025 \logical_op__insn_type$29$next sync posedge \coresync_clk - update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$10041 + update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$10025 end - attribute \src "libresoc.v:173405.3-173406.63" - process $proc$libresoc.v:173405$10042 + attribute \src "libresoc.v:174713.3-174714.63" + process $proc$libresoc.v:174713$10026 assign { } { } - assign $0\logical_op__fn_unit$30[13:0]$10043 \logical_op__fn_unit$30$next + assign $0\logical_op__fn_unit$30[13:0]$10027 \logical_op__fn_unit$30$next sync posedge \coresync_clk - update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[13:0]$10043 + update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[13:0]$10027 end - attribute \src "libresoc.v:173407.3-173408.77" - process $proc$libresoc.v:173407$10044 + attribute \src "libresoc.v:174715.3-174716.77" + process $proc$libresoc.v:174715$10028 assign { } { } - assign $0\logical_op__imm_data__data$31[63:0]$10045 \logical_op__imm_data__data$31$next + assign $0\logical_op__imm_data__data$31[63:0]$10029 \logical_op__imm_data__data$31$next sync posedge \coresync_clk - update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$10045 + update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$10029 end - attribute \src "libresoc.v:173409.3-173410.73" - process $proc$libresoc.v:173409$10046 + attribute \src "libresoc.v:174717.3-174718.73" + process $proc$libresoc.v:174717$10030 assign { } { } - assign $0\logical_op__imm_data__ok$32[0:0]$10047 \logical_op__imm_data__ok$32$next + assign $0\logical_op__imm_data__ok$32[0:0]$10031 \logical_op__imm_data__ok$32$next sync posedge \coresync_clk - update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$10047 + update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$10031 end - attribute \src "libresoc.v:173411.3-173412.61" - process $proc$libresoc.v:173411$10048 + attribute \src "libresoc.v:174719.3-174720.61" + process $proc$libresoc.v:174719$10032 assign { } { } - assign $0\logical_op__rc__rc$33[0:0]$10049 \logical_op__rc__rc$33$next + assign $0\logical_op__rc__rc$33[0:0]$10033 \logical_op__rc__rc$33$next sync posedge \coresync_clk - update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$10049 + update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$10033 end - attribute \src "libresoc.v:173413.3-173414.61" - process $proc$libresoc.v:173413$10050 + attribute \src "libresoc.v:174721.3-174722.61" + process $proc$libresoc.v:174721$10034 assign { } { } - assign $0\logical_op__rc__ok$34[0:0]$10051 \logical_op__rc__ok$34$next + assign $0\logical_op__rc__ok$34[0:0]$10035 \logical_op__rc__ok$34$next sync posedge \coresync_clk - update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$10051 + update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$10035 end - attribute \src "libresoc.v:173415.3-173416.61" - process $proc$libresoc.v:173415$10052 + attribute \src "libresoc.v:174723.3-174724.61" + process $proc$libresoc.v:174723$10036 assign { } { } - assign $0\logical_op__oe__oe$35[0:0]$10053 \logical_op__oe__oe$35$next + assign $0\logical_op__oe__oe$35[0:0]$10037 \logical_op__oe__oe$35$next sync posedge \coresync_clk - update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$10053 + update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$10037 end - attribute \src "libresoc.v:173417.3-173418.61" - process $proc$libresoc.v:173417$10054 + attribute \src "libresoc.v:174725.3-174726.61" + process $proc$libresoc.v:174725$10038 assign { } { } - assign $0\logical_op__oe__ok$36[0:0]$10055 \logical_op__oe__ok$36$next + assign $0\logical_op__oe__ok$36[0:0]$10039 \logical_op__oe__ok$36$next sync posedge \coresync_clk - update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$10055 + update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$10039 end - attribute \src "libresoc.v:173419.3-173420.67" - process $proc$libresoc.v:173419$10056 + attribute \src "libresoc.v:174727.3-174728.67" + process $proc$libresoc.v:174727$10040 assign { } { } - assign $0\logical_op__invert_in$37[0:0]$10057 \logical_op__invert_in$37$next + assign $0\logical_op__invert_in$37[0:0]$10041 \logical_op__invert_in$37$next sync posedge \coresync_clk - update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$10057 + update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$10041 end - attribute \src "libresoc.v:173421.3-173422.61" - process $proc$libresoc.v:173421$10058 + attribute \src "libresoc.v:174729.3-174730.61" + process $proc$libresoc.v:174729$10042 assign { } { } - assign $0\logical_op__zero_a$38[0:0]$10059 \logical_op__zero_a$38$next + assign $0\logical_op__zero_a$38[0:0]$10043 \logical_op__zero_a$38$next sync posedge \coresync_clk - update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$10059 + update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$10043 end - attribute \src "libresoc.v:173423.3-173424.71" - process $proc$libresoc.v:173423$10060 + attribute \src "libresoc.v:174731.3-174732.71" + process $proc$libresoc.v:174731$10044 assign { } { } - assign $0\logical_op__input_carry$39[1:0]$10061 \logical_op__input_carry$39$next + assign $0\logical_op__input_carry$39[1:0]$10045 \logical_op__input_carry$39$next sync posedge \coresync_clk - update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$10061 + update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$10045 end - attribute \src "libresoc.v:173425.3-173426.69" - process $proc$libresoc.v:173425$10062 + attribute \src "libresoc.v:174733.3-174734.69" + process $proc$libresoc.v:174733$10046 assign { } { } - assign $0\logical_op__invert_out$40[0:0]$10063 \logical_op__invert_out$40$next + assign $0\logical_op__invert_out$40[0:0]$10047 \logical_op__invert_out$40$next sync posedge \coresync_clk - update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$10063 + update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$10047 end - attribute \src "libresoc.v:173427.3-173428.67" - process $proc$libresoc.v:173427$10064 + attribute \src "libresoc.v:174735.3-174736.67" + process $proc$libresoc.v:174735$10048 assign { } { } - assign $0\logical_op__write_cr0$41[0:0]$10065 \logical_op__write_cr0$41$next + assign $0\logical_op__write_cr0$41[0:0]$10049 \logical_op__write_cr0$41$next sync posedge \coresync_clk - update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$10065 + update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$10049 end - attribute \src "libresoc.v:173429.3-173430.73" - process $proc$libresoc.v:173429$10066 + attribute \src "libresoc.v:174737.3-174738.73" + process $proc$libresoc.v:174737$10050 assign { } { } - assign $0\logical_op__output_carry$42[0:0]$10067 \logical_op__output_carry$42$next + assign $0\logical_op__output_carry$42[0:0]$10051 \logical_op__output_carry$42$next sync posedge \coresync_clk - update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$10067 + update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$10051 end - attribute \src "libresoc.v:173431.3-173432.65" - process $proc$libresoc.v:173431$10068 + attribute \src "libresoc.v:174739.3-174740.65" + process $proc$libresoc.v:174739$10052 assign { } { } - assign $0\logical_op__is_32bit$43[0:0]$10069 \logical_op__is_32bit$43$next + assign $0\logical_op__is_32bit$43[0:0]$10053 \logical_op__is_32bit$43$next sync posedge \coresync_clk - update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$10069 + update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$10053 end - attribute \src "libresoc.v:173433.3-173434.67" - process $proc$libresoc.v:173433$10070 + attribute \src "libresoc.v:174741.3-174742.67" + process $proc$libresoc.v:174741$10054 assign { } { } - assign $0\logical_op__is_signed$44[0:0]$10071 \logical_op__is_signed$44$next + assign $0\logical_op__is_signed$44[0:0]$10055 \logical_op__is_signed$44$next sync posedge \coresync_clk - update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$10071 + update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$10055 end - attribute \src "libresoc.v:173435.3-173436.65" - process $proc$libresoc.v:173435$10072 + attribute \src "libresoc.v:174743.3-174744.65" + process $proc$libresoc.v:174743$10056 assign { } { } - assign $0\logical_op__data_len$45[3:0]$10073 \logical_op__data_len$45$next + assign $0\logical_op__data_len$45[3:0]$10057 \logical_op__data_len$45$next sync posedge \coresync_clk - update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$10073 + update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$10057 end - attribute \src "libresoc.v:173437.3-173438.57" - process $proc$libresoc.v:173437$10074 + attribute \src "libresoc.v:174745.3-174746.57" + process $proc$libresoc.v:174745$10058 assign { } { } - assign $0\logical_op__insn$46[31:0]$10075 \logical_op__insn$46$next + assign $0\logical_op__insn$46[31:0]$10059 \logical_op__insn$46$next sync posedge \coresync_clk - update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$10075 + update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$10059 end - attribute \src "libresoc.v:173439.3-173440.35" - process $proc$libresoc.v:173439$10076 + attribute \src "libresoc.v:174747.3-174748.35" + process $proc$libresoc.v:174747$10060 assign { } { } - assign $0\muxid$28[1:0]$10077 \muxid$28$next + assign $0\muxid$28[1:0]$10061 \muxid$28$next sync posedge \coresync_clk - update \muxid$28 $0\muxid$28[1:0]$10077 + update \muxid$28 $0\muxid$28[1:0]$10061 end - attribute \src "libresoc.v:173441.3-173442.27" - process $proc$libresoc.v:173441$10078 + attribute \src "libresoc.v:174749.3-174750.27" + process $proc$libresoc.v:174749$10062 assign { } { } assign $0\empty[0:0] \empty$next sync posedge \coresync_clk update \empty $0\empty[0:0] end - attribute \src "libresoc.v:173443.3-173444.75" - process $proc$libresoc.v:173443$10079 + attribute \src "libresoc.v:174751.3-174752.75" + process $proc$libresoc.v:174751$10063 assign { } { } assign $0\saved_state_dividend_quotient[127:0] \saved_state_dividend_quotient$next sync posedge \coresync_clk update \saved_state_dividend_quotient $0\saved_state_dividend_quotient[127:0] end - attribute \src "libresoc.v:173445.3-173446.65" - process $proc$libresoc.v:173445$10080 + attribute \src "libresoc.v:174753.3-174754.65" + process $proc$libresoc.v:174753$10064 assign { } { } assign $0\saved_state_q_bits_known[6:0] \saved_state_q_bits_known$next sync posedge \coresync_clk update \saved_state_q_bits_known $0\saved_state_q_bits_known[6:0] end - attribute \src "libresoc.v:173467.3-173475.6" - process $proc$libresoc.v:173467$10081 + attribute \src "libresoc.v:174775.3-174783.6" + process $proc$libresoc.v:174775$10065 assign { } { } assign { } { } - assign $0\saved_state_q_bits_known$next[6:0]$10082 $1\saved_state_q_bits_known$next[6:0]$10083 - attribute \src "libresoc.v:173468.5-173468.29" + assign $0\saved_state_q_bits_known$next[6:0]$10066 $1\saved_state_q_bits_known$next[6:0]$10067 + attribute \src "libresoc.v:174776.5-174776.29" switch \initial - attribute \src "libresoc.v:173468.9-173468.17" + attribute \src "libresoc.v:174776.9-174776.17" case 1'1 case end @@ -352604,21 +323974,21 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\saved_state_q_bits_known$next[6:0]$10083 7'0000000 + assign $1\saved_state_q_bits_known$next[6:0]$10067 7'0000000 case - assign $1\saved_state_q_bits_known$next[6:0]$10083 \div_state_next_o_q_bits_known + assign $1\saved_state_q_bits_known$next[6:0]$10067 \div_state_next_o_q_bits_known end sync always - update \saved_state_q_bits_known$next $0\saved_state_q_bits_known$next[6:0]$10082 + update \saved_state_q_bits_known$next $0\saved_state_q_bits_known$next[6:0]$10066 end - attribute \src "libresoc.v:173476.3-173484.6" - process $proc$libresoc.v:173476$10084 + attribute \src "libresoc.v:174784.3-174792.6" + process $proc$libresoc.v:174784$10068 assign { } { } assign { } { } - assign $0\saved_state_dividend_quotient$next[127:0]$10085 $1\saved_state_dividend_quotient$next[127:0]$10086 - attribute \src "libresoc.v:173477.5-173477.29" + assign $0\saved_state_dividend_quotient$next[127:0]$10069 $1\saved_state_dividend_quotient$next[127:0]$10070 + attribute \src "libresoc.v:174785.5-174785.29" switch \initial - attribute \src "libresoc.v:173477.9-173477.17" + attribute \src "libresoc.v:174785.9-174785.17" case 1'1 case end @@ -352627,20 +323997,20 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\saved_state_dividend_quotient$next[127:0]$10086 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\saved_state_dividend_quotient$next[127:0]$10070 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 case - assign $1\saved_state_dividend_quotient$next[127:0]$10086 \div_state_next_o_dividend_quotient + assign $1\saved_state_dividend_quotient$next[127:0]$10070 \div_state_next_o_dividend_quotient end sync always - update \saved_state_dividend_quotient$next $0\saved_state_dividend_quotient$next[127:0]$10085 + update \saved_state_dividend_quotient$next $0\saved_state_dividend_quotient$next[127:0]$10069 end - attribute \src "libresoc.v:173485.3-173496.6" - process $proc$libresoc.v:173485$10087 + attribute \src "libresoc.v:174793.3-174804.6" + process $proc$libresoc.v:174793$10071 assign { } { } assign $0\div_state_next_i_q_bits_known[6:0] $1\div_state_next_i_q_bits_known[6:0] - attribute \src "libresoc.v:173486.5-173486.29" + attribute \src "libresoc.v:174794.5-174794.29" switch \initial - attribute \src "libresoc.v:173486.9-173486.17" + attribute \src "libresoc.v:174794.9-174794.17" case 1'1 case end @@ -352658,13 +324028,13 @@ module \pipe_middle_0 sync always update \div_state_next_i_q_bits_known $0\div_state_next_i_q_bits_known[6:0] end - attribute \src "libresoc.v:173497.3-173508.6" - process $proc$libresoc.v:173497$10088 + attribute \src "libresoc.v:174805.3-174816.6" + process $proc$libresoc.v:174805$10072 assign { } { } assign $0\div_state_next_i_dividend_quotient[127:0] $1\div_state_next_i_dividend_quotient[127:0] - attribute \src "libresoc.v:173498.5-173498.29" + attribute \src "libresoc.v:174806.5-174806.29" switch \initial - attribute \src "libresoc.v:173498.9-173498.17" + attribute \src "libresoc.v:174806.9-174806.17" case 1'1 case end @@ -352682,13 +324052,13 @@ module \pipe_middle_0 sync always update \div_state_next_i_dividend_quotient $0\div_state_next_i_dividend_quotient[127:0] end - attribute \src "libresoc.v:173509.3-173520.6" - process $proc$libresoc.v:173509$10089 + attribute \src "libresoc.v:174817.3-174828.6" + process $proc$libresoc.v:174817$10073 assign { } { } assign $0\div_state_next_divisor[63:0] $1\div_state_next_divisor[63:0] - attribute \src "libresoc.v:173510.5-173510.29" + attribute \src "libresoc.v:174818.5-174818.29" switch \initial - attribute \src "libresoc.v:173510.9-173510.17" + attribute \src "libresoc.v:174818.9-174818.17" case 1'1 case end @@ -352706,15 +324076,15 @@ module \pipe_middle_0 sync always update \div_state_next_divisor $0\div_state_next_divisor[63:0] end - attribute \src "libresoc.v:173521.3-173548.6" - process $proc$libresoc.v:173521$10090 + attribute \src "libresoc.v:174829.3-174856.6" + process $proc$libresoc.v:174829$10074 assign { } { } assign { } { } assign { } { } - assign $0\empty$next[0:0]$10091 $4\empty$next[0:0]$10095 - attribute \src "libresoc.v:173522.5-173522.29" + assign $0\empty$next[0:0]$10075 $4\empty$next[0:0]$10079 + attribute \src "libresoc.v:174830.5-174830.29" switch \initial - attribute \src "libresoc.v:173522.9-173522.17" + attribute \src "libresoc.v:174830.9-174830.17" case 1'1 case end @@ -352723,28 +324093,28 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\empty$next[0:0]$10092 $2\empty$next[0:0]$10093 + assign $1\empty$next[0:0]$10076 $2\empty$next[0:0]$10077 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\empty$next[0:0]$10093 1'0 + assign $2\empty$next[0:0]$10077 1'0 case - assign $2\empty$next[0:0]$10093 \empty + assign $2\empty$next[0:0]$10077 \empty end attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\empty$next[0:0]$10092 $3\empty$next[0:0]$10094 + assign $1\empty$next[0:0]$10076 $3\empty$next[0:0]$10078 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" switch \$66 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\empty$next[0:0]$10094 1'1 + assign $3\empty$next[0:0]$10078 1'1 case - assign $3\empty$next[0:0]$10094 \empty + assign $3\empty$next[0:0]$10078 \empty end end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" @@ -352752,21 +324122,21 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\empty$next[0:0]$10095 1'1 + assign $4\empty$next[0:0]$10079 1'1 case - assign $4\empty$next[0:0]$10095 $1\empty$next[0:0]$10092 + assign $4\empty$next[0:0]$10079 $1\empty$next[0:0]$10076 end sync always - update \empty$next $0\empty$next[0:0]$10091 + update \empty$next $0\empty$next[0:0]$10075 end - attribute \src "libresoc.v:173549.3-173563.6" - process $proc$libresoc.v:173549$10096 + attribute \src "libresoc.v:174857.3-174871.6" + process $proc$libresoc.v:174857$10080 assign { } { } assign { } { } - assign $0\muxid$28$next[1:0]$10097 $1\muxid$28$next[1:0]$10098 - attribute \src "libresoc.v:173550.5-173550.29" + assign $0\muxid$28$next[1:0]$10081 $1\muxid$28$next[1:0]$10082 + attribute \src "libresoc.v:174858.5-174858.29" switch \initial - attribute \src "libresoc.v:173550.9-173550.17" + attribute \src "libresoc.v:174858.9-174858.17" case 1'1 case end @@ -352775,24 +324145,24 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\muxid$28$next[1:0]$10098 $2\muxid$28$next[1:0]$10099 + assign $1\muxid$28$next[1:0]$10082 $2\muxid$28$next[1:0]$10083 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\muxid$28$next[1:0]$10099 \muxid + assign $2\muxid$28$next[1:0]$10083 \muxid case - assign $2\muxid$28$next[1:0]$10099 \muxid$28 + assign $2\muxid$28$next[1:0]$10083 \muxid$28 end case - assign $1\muxid$28$next[1:0]$10098 \muxid$28 + assign $1\muxid$28$next[1:0]$10082 \muxid$28 end sync always - update \muxid$28$next $0\muxid$28$next[1:0]$10097 + update \muxid$28$next $0\muxid$28$next[1:0]$10081 end - attribute \src "libresoc.v:173564.3-173607.6" - process $proc$libresoc.v:173564$10100 + attribute \src "libresoc.v:174872.3-174915.6" + process $proc$libresoc.v:174872$10084 assign { } { } assign { } { } assign { } { } @@ -352829,33 +324199,33 @@ module \pipe_middle_0 assign { } { } assign { } { } assign { } { } - assign $0\logical_op__data_len$45$next[3:0]$10101 $1\logical_op__data_len$45$next[3:0]$10119 - assign $0\logical_op__fn_unit$30$next[13:0]$10102 $1\logical_op__fn_unit$30$next[13:0]$10120 + assign $0\logical_op__data_len$45$next[3:0]$10085 $1\logical_op__data_len$45$next[3:0]$10103 + assign $0\logical_op__fn_unit$30$next[13:0]$10086 $1\logical_op__fn_unit$30$next[13:0]$10104 assign { } { } assign { } { } - assign $0\logical_op__input_carry$39$next[1:0]$10105 $1\logical_op__input_carry$39$next[1:0]$10123 - assign $0\logical_op__insn$46$next[31:0]$10106 $1\logical_op__insn$46$next[31:0]$10124 - assign $0\logical_op__insn_type$29$next[6:0]$10107 $1\logical_op__insn_type$29$next[6:0]$10125 - assign $0\logical_op__invert_in$37$next[0:0]$10108 $1\logical_op__invert_in$37$next[0:0]$10126 - assign $0\logical_op__invert_out$40$next[0:0]$10109 $1\logical_op__invert_out$40$next[0:0]$10127 - assign $0\logical_op__is_32bit$43$next[0:0]$10110 $1\logical_op__is_32bit$43$next[0:0]$10128 - assign $0\logical_op__is_signed$44$next[0:0]$10111 $1\logical_op__is_signed$44$next[0:0]$10129 + assign $0\logical_op__input_carry$39$next[1:0]$10089 $1\logical_op__input_carry$39$next[1:0]$10107 + assign $0\logical_op__insn$46$next[31:0]$10090 $1\logical_op__insn$46$next[31:0]$10108 + assign $0\logical_op__insn_type$29$next[6:0]$10091 $1\logical_op__insn_type$29$next[6:0]$10109 + assign $0\logical_op__invert_in$37$next[0:0]$10092 $1\logical_op__invert_in$37$next[0:0]$10110 + assign $0\logical_op__invert_out$40$next[0:0]$10093 $1\logical_op__invert_out$40$next[0:0]$10111 + assign $0\logical_op__is_32bit$43$next[0:0]$10094 $1\logical_op__is_32bit$43$next[0:0]$10112 + assign $0\logical_op__is_signed$44$next[0:0]$10095 $1\logical_op__is_signed$44$next[0:0]$10113 assign { } { } assign { } { } - assign $0\logical_op__output_carry$42$next[0:0]$10114 $1\logical_op__output_carry$42$next[0:0]$10132 + assign $0\logical_op__output_carry$42$next[0:0]$10098 $1\logical_op__output_carry$42$next[0:0]$10116 assign { } { } assign { } { } - assign $0\logical_op__write_cr0$41$next[0:0]$10117 $1\logical_op__write_cr0$41$next[0:0]$10135 - assign $0\logical_op__zero_a$38$next[0:0]$10118 $1\logical_op__zero_a$38$next[0:0]$10136 - assign $0\logical_op__imm_data__data$31$next[63:0]$10103 $3\logical_op__imm_data__data$31$next[63:0]$10155 - assign $0\logical_op__imm_data__ok$32$next[0:0]$10104 $3\logical_op__imm_data__ok$32$next[0:0]$10156 - assign $0\logical_op__oe__oe$35$next[0:0]$10112 $3\logical_op__oe__oe$35$next[0:0]$10157 - assign $0\logical_op__oe__ok$36$next[0:0]$10113 $3\logical_op__oe__ok$36$next[0:0]$10158 - assign $0\logical_op__rc__ok$34$next[0:0]$10115 $3\logical_op__rc__ok$34$next[0:0]$10159 - assign $0\logical_op__rc__rc$33$next[0:0]$10116 $3\logical_op__rc__rc$33$next[0:0]$10160 - attribute \src "libresoc.v:173565.5-173565.29" + assign $0\logical_op__write_cr0$41$next[0:0]$10101 $1\logical_op__write_cr0$41$next[0:0]$10119 + assign $0\logical_op__zero_a$38$next[0:0]$10102 $1\logical_op__zero_a$38$next[0:0]$10120 + assign $0\logical_op__imm_data__data$31$next[63:0]$10087 $3\logical_op__imm_data__data$31$next[63:0]$10139 + assign $0\logical_op__imm_data__ok$32$next[0:0]$10088 $3\logical_op__imm_data__ok$32$next[0:0]$10140 + assign $0\logical_op__oe__oe$35$next[0:0]$10096 $3\logical_op__oe__oe$35$next[0:0]$10141 + assign $0\logical_op__oe__ok$36$next[0:0]$10097 $3\logical_op__oe__ok$36$next[0:0]$10142 + assign $0\logical_op__rc__ok$34$next[0:0]$10099 $3\logical_op__rc__ok$34$next[0:0]$10143 + assign $0\logical_op__rc__rc$33$next[0:0]$10100 $3\logical_op__rc__rc$33$next[0:0]$10144 + attribute \src "libresoc.v:174873.5-174873.29" switch \initial - attribute \src "libresoc.v:173565.9-173565.17" + attribute \src "libresoc.v:174873.9-174873.17" case 1'1 case end @@ -352881,24 +324251,24 @@ module \pipe_middle_0 assign { } { } assign { } { } assign { } { } - assign $1\logical_op__data_len$45$next[3:0]$10119 $2\logical_op__data_len$45$next[3:0]$10137 - assign $1\logical_op__fn_unit$30$next[13:0]$10120 $2\logical_op__fn_unit$30$next[13:0]$10138 - assign $1\logical_op__imm_data__data$31$next[63:0]$10121 $2\logical_op__imm_data__data$31$next[63:0]$10139 - assign $1\logical_op__imm_data__ok$32$next[0:0]$10122 $2\logical_op__imm_data__ok$32$next[0:0]$10140 - assign $1\logical_op__input_carry$39$next[1:0]$10123 $2\logical_op__input_carry$39$next[1:0]$10141 - assign $1\logical_op__insn$46$next[31:0]$10124 $2\logical_op__insn$46$next[31:0]$10142 - assign $1\logical_op__insn_type$29$next[6:0]$10125 $2\logical_op__insn_type$29$next[6:0]$10143 - assign $1\logical_op__invert_in$37$next[0:0]$10126 $2\logical_op__invert_in$37$next[0:0]$10144 - assign $1\logical_op__invert_out$40$next[0:0]$10127 $2\logical_op__invert_out$40$next[0:0]$10145 - assign $1\logical_op__is_32bit$43$next[0:0]$10128 $2\logical_op__is_32bit$43$next[0:0]$10146 - assign $1\logical_op__is_signed$44$next[0:0]$10129 $2\logical_op__is_signed$44$next[0:0]$10147 - assign $1\logical_op__oe__oe$35$next[0:0]$10130 $2\logical_op__oe__oe$35$next[0:0]$10148 - assign $1\logical_op__oe__ok$36$next[0:0]$10131 $2\logical_op__oe__ok$36$next[0:0]$10149 - assign $1\logical_op__output_carry$42$next[0:0]$10132 $2\logical_op__output_carry$42$next[0:0]$10150 - assign $1\logical_op__rc__ok$34$next[0:0]$10133 $2\logical_op__rc__ok$34$next[0:0]$10151 - assign $1\logical_op__rc__rc$33$next[0:0]$10134 $2\logical_op__rc__rc$33$next[0:0]$10152 - assign $1\logical_op__write_cr0$41$next[0:0]$10135 $2\logical_op__write_cr0$41$next[0:0]$10153 - assign $1\logical_op__zero_a$38$next[0:0]$10136 $2\logical_op__zero_a$38$next[0:0]$10154 + assign $1\logical_op__data_len$45$next[3:0]$10103 $2\logical_op__data_len$45$next[3:0]$10121 + assign $1\logical_op__fn_unit$30$next[13:0]$10104 $2\logical_op__fn_unit$30$next[13:0]$10122 + assign $1\logical_op__imm_data__data$31$next[63:0]$10105 $2\logical_op__imm_data__data$31$next[63:0]$10123 + assign $1\logical_op__imm_data__ok$32$next[0:0]$10106 $2\logical_op__imm_data__ok$32$next[0:0]$10124 + assign $1\logical_op__input_carry$39$next[1:0]$10107 $2\logical_op__input_carry$39$next[1:0]$10125 + assign $1\logical_op__insn$46$next[31:0]$10108 $2\logical_op__insn$46$next[31:0]$10126 + assign $1\logical_op__insn_type$29$next[6:0]$10109 $2\logical_op__insn_type$29$next[6:0]$10127 + assign $1\logical_op__invert_in$37$next[0:0]$10110 $2\logical_op__invert_in$37$next[0:0]$10128 + assign $1\logical_op__invert_out$40$next[0:0]$10111 $2\logical_op__invert_out$40$next[0:0]$10129 + assign $1\logical_op__is_32bit$43$next[0:0]$10112 $2\logical_op__is_32bit$43$next[0:0]$10130 + assign $1\logical_op__is_signed$44$next[0:0]$10113 $2\logical_op__is_signed$44$next[0:0]$10131 + assign $1\logical_op__oe__oe$35$next[0:0]$10114 $2\logical_op__oe__oe$35$next[0:0]$10132 + assign $1\logical_op__oe__ok$36$next[0:0]$10115 $2\logical_op__oe__ok$36$next[0:0]$10133 + assign $1\logical_op__output_carry$42$next[0:0]$10116 $2\logical_op__output_carry$42$next[0:0]$10134 + assign $1\logical_op__rc__ok$34$next[0:0]$10117 $2\logical_op__rc__ok$34$next[0:0]$10135 + assign $1\logical_op__rc__rc$33$next[0:0]$10118 $2\logical_op__rc__rc$33$next[0:0]$10136 + assign $1\logical_op__write_cr0$41$next[0:0]$10119 $2\logical_op__write_cr0$41$next[0:0]$10137 + assign $1\logical_op__zero_a$38$next[0:0]$10120 $2\logical_op__zero_a$38$next[0:0]$10138 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" @@ -352921,46 +324291,46 @@ module \pipe_middle_0 assign { } { } assign { } { } assign { } { } - assign { $2\logical_op__insn$46$next[31:0]$10142 $2\logical_op__data_len$45$next[3:0]$10137 $2\logical_op__is_signed$44$next[0:0]$10147 $2\logical_op__is_32bit$43$next[0:0]$10146 $2\logical_op__output_carry$42$next[0:0]$10150 $2\logical_op__write_cr0$41$next[0:0]$10153 $2\logical_op__invert_out$40$next[0:0]$10145 $2\logical_op__input_carry$39$next[1:0]$10141 $2\logical_op__zero_a$38$next[0:0]$10154 $2\logical_op__invert_in$37$next[0:0]$10144 $2\logical_op__oe__ok$36$next[0:0]$10149 $2\logical_op__oe__oe$35$next[0:0]$10148 $2\logical_op__rc__ok$34$next[0:0]$10151 $2\logical_op__rc__rc$33$next[0:0]$10152 $2\logical_op__imm_data__ok$32$next[0:0]$10140 $2\logical_op__imm_data__data$31$next[63:0]$10139 $2\logical_op__fn_unit$30$next[13:0]$10138 $2\logical_op__insn_type$29$next[6:0]$10143 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + assign { $2\logical_op__insn$46$next[31:0]$10126 $2\logical_op__data_len$45$next[3:0]$10121 $2\logical_op__is_signed$44$next[0:0]$10131 $2\logical_op__is_32bit$43$next[0:0]$10130 $2\logical_op__output_carry$42$next[0:0]$10134 $2\logical_op__write_cr0$41$next[0:0]$10137 $2\logical_op__invert_out$40$next[0:0]$10129 $2\logical_op__input_carry$39$next[1:0]$10125 $2\logical_op__zero_a$38$next[0:0]$10138 $2\logical_op__invert_in$37$next[0:0]$10128 $2\logical_op__oe__ok$36$next[0:0]$10133 $2\logical_op__oe__oe$35$next[0:0]$10132 $2\logical_op__rc__ok$34$next[0:0]$10135 $2\logical_op__rc__rc$33$next[0:0]$10136 $2\logical_op__imm_data__ok$32$next[0:0]$10124 $2\logical_op__imm_data__data$31$next[63:0]$10123 $2\logical_op__fn_unit$30$next[13:0]$10122 $2\logical_op__insn_type$29$next[6:0]$10127 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } case - assign $2\logical_op__data_len$45$next[3:0]$10137 \logical_op__data_len$45 - assign $2\logical_op__fn_unit$30$next[13:0]$10138 \logical_op__fn_unit$30 - assign $2\logical_op__imm_data__data$31$next[63:0]$10139 \logical_op__imm_data__data$31 - assign $2\logical_op__imm_data__ok$32$next[0:0]$10140 \logical_op__imm_data__ok$32 - assign $2\logical_op__input_carry$39$next[1:0]$10141 \logical_op__input_carry$39 - assign $2\logical_op__insn$46$next[31:0]$10142 \logical_op__insn$46 - assign $2\logical_op__insn_type$29$next[6:0]$10143 \logical_op__insn_type$29 - assign $2\logical_op__invert_in$37$next[0:0]$10144 \logical_op__invert_in$37 - assign $2\logical_op__invert_out$40$next[0:0]$10145 \logical_op__invert_out$40 - assign $2\logical_op__is_32bit$43$next[0:0]$10146 \logical_op__is_32bit$43 - assign $2\logical_op__is_signed$44$next[0:0]$10147 \logical_op__is_signed$44 - assign $2\logical_op__oe__oe$35$next[0:0]$10148 \logical_op__oe__oe$35 - assign $2\logical_op__oe__ok$36$next[0:0]$10149 \logical_op__oe__ok$36 - assign $2\logical_op__output_carry$42$next[0:0]$10150 \logical_op__output_carry$42 - assign $2\logical_op__rc__ok$34$next[0:0]$10151 \logical_op__rc__ok$34 - assign $2\logical_op__rc__rc$33$next[0:0]$10152 \logical_op__rc__rc$33 - assign $2\logical_op__write_cr0$41$next[0:0]$10153 \logical_op__write_cr0$41 - assign $2\logical_op__zero_a$38$next[0:0]$10154 \logical_op__zero_a$38 + assign $2\logical_op__data_len$45$next[3:0]$10121 \logical_op__data_len$45 + assign $2\logical_op__fn_unit$30$next[13:0]$10122 \logical_op__fn_unit$30 + assign $2\logical_op__imm_data__data$31$next[63:0]$10123 \logical_op__imm_data__data$31 + assign $2\logical_op__imm_data__ok$32$next[0:0]$10124 \logical_op__imm_data__ok$32 + assign $2\logical_op__input_carry$39$next[1:0]$10125 \logical_op__input_carry$39 + assign $2\logical_op__insn$46$next[31:0]$10126 \logical_op__insn$46 + assign $2\logical_op__insn_type$29$next[6:0]$10127 \logical_op__insn_type$29 + assign $2\logical_op__invert_in$37$next[0:0]$10128 \logical_op__invert_in$37 + assign $2\logical_op__invert_out$40$next[0:0]$10129 \logical_op__invert_out$40 + assign $2\logical_op__is_32bit$43$next[0:0]$10130 \logical_op__is_32bit$43 + assign $2\logical_op__is_signed$44$next[0:0]$10131 \logical_op__is_signed$44 + assign $2\logical_op__oe__oe$35$next[0:0]$10132 \logical_op__oe__oe$35 + assign $2\logical_op__oe__ok$36$next[0:0]$10133 \logical_op__oe__ok$36 + assign $2\logical_op__output_carry$42$next[0:0]$10134 \logical_op__output_carry$42 + assign $2\logical_op__rc__ok$34$next[0:0]$10135 \logical_op__rc__ok$34 + assign $2\logical_op__rc__rc$33$next[0:0]$10136 \logical_op__rc__rc$33 + assign $2\logical_op__write_cr0$41$next[0:0]$10137 \logical_op__write_cr0$41 + assign $2\logical_op__zero_a$38$next[0:0]$10138 \logical_op__zero_a$38 end case - assign $1\logical_op__data_len$45$next[3:0]$10119 \logical_op__data_len$45 - assign $1\logical_op__fn_unit$30$next[13:0]$10120 \logical_op__fn_unit$30 - assign $1\logical_op__imm_data__data$31$next[63:0]$10121 \logical_op__imm_data__data$31 - assign $1\logical_op__imm_data__ok$32$next[0:0]$10122 \logical_op__imm_data__ok$32 - assign $1\logical_op__input_carry$39$next[1:0]$10123 \logical_op__input_carry$39 - assign $1\logical_op__insn$46$next[31:0]$10124 \logical_op__insn$46 - assign $1\logical_op__insn_type$29$next[6:0]$10125 \logical_op__insn_type$29 - assign $1\logical_op__invert_in$37$next[0:0]$10126 \logical_op__invert_in$37 - assign $1\logical_op__invert_out$40$next[0:0]$10127 \logical_op__invert_out$40 - assign $1\logical_op__is_32bit$43$next[0:0]$10128 \logical_op__is_32bit$43 - assign $1\logical_op__is_signed$44$next[0:0]$10129 \logical_op__is_signed$44 - assign $1\logical_op__oe__oe$35$next[0:0]$10130 \logical_op__oe__oe$35 - assign $1\logical_op__oe__ok$36$next[0:0]$10131 \logical_op__oe__ok$36 - assign $1\logical_op__output_carry$42$next[0:0]$10132 \logical_op__output_carry$42 - assign $1\logical_op__rc__ok$34$next[0:0]$10133 \logical_op__rc__ok$34 - assign $1\logical_op__rc__rc$33$next[0:0]$10134 \logical_op__rc__rc$33 - assign $1\logical_op__write_cr0$41$next[0:0]$10135 \logical_op__write_cr0$41 - assign $1\logical_op__zero_a$38$next[0:0]$10136 \logical_op__zero_a$38 + assign $1\logical_op__data_len$45$next[3:0]$10103 \logical_op__data_len$45 + assign $1\logical_op__fn_unit$30$next[13:0]$10104 \logical_op__fn_unit$30 + assign $1\logical_op__imm_data__data$31$next[63:0]$10105 \logical_op__imm_data__data$31 + assign $1\logical_op__imm_data__ok$32$next[0:0]$10106 \logical_op__imm_data__ok$32 + assign $1\logical_op__input_carry$39$next[1:0]$10107 \logical_op__input_carry$39 + assign $1\logical_op__insn$46$next[31:0]$10108 \logical_op__insn$46 + assign $1\logical_op__insn_type$29$next[6:0]$10109 \logical_op__insn_type$29 + assign $1\logical_op__invert_in$37$next[0:0]$10110 \logical_op__invert_in$37 + assign $1\logical_op__invert_out$40$next[0:0]$10111 \logical_op__invert_out$40 + assign $1\logical_op__is_32bit$43$next[0:0]$10112 \logical_op__is_32bit$43 + assign $1\logical_op__is_signed$44$next[0:0]$10113 \logical_op__is_signed$44 + assign $1\logical_op__oe__oe$35$next[0:0]$10114 \logical_op__oe__oe$35 + assign $1\logical_op__oe__ok$36$next[0:0]$10115 \logical_op__oe__ok$36 + assign $1\logical_op__output_carry$42$next[0:0]$10116 \logical_op__output_carry$42 + assign $1\logical_op__rc__ok$34$next[0:0]$10117 \logical_op__rc__ok$34 + assign $1\logical_op__rc__rc$33$next[0:0]$10118 \logical_op__rc__rc$33 + assign $1\logical_op__write_cr0$41$next[0:0]$10119 \logical_op__write_cr0$41 + assign $1\logical_op__zero_a$38$next[0:0]$10120 \logical_op__zero_a$38 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -352972,48 +324342,48 @@ module \pipe_middle_0 assign { } { } assign { } { } assign { } { } - assign $3\logical_op__imm_data__data$31$next[63:0]$10155 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\logical_op__imm_data__ok$32$next[0:0]$10156 1'0 - assign $3\logical_op__rc__rc$33$next[0:0]$10160 1'0 - assign $3\logical_op__rc__ok$34$next[0:0]$10159 1'0 - assign $3\logical_op__oe__oe$35$next[0:0]$10157 1'0 - assign $3\logical_op__oe__ok$36$next[0:0]$10158 1'0 + assign $3\logical_op__imm_data__data$31$next[63:0]$10139 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\logical_op__imm_data__ok$32$next[0:0]$10140 1'0 + assign $3\logical_op__rc__rc$33$next[0:0]$10144 1'0 + assign $3\logical_op__rc__ok$34$next[0:0]$10143 1'0 + assign $3\logical_op__oe__oe$35$next[0:0]$10141 1'0 + assign $3\logical_op__oe__ok$36$next[0:0]$10142 1'0 case - assign $3\logical_op__imm_data__data$31$next[63:0]$10155 $1\logical_op__imm_data__data$31$next[63:0]$10121 - assign $3\logical_op__imm_data__ok$32$next[0:0]$10156 $1\logical_op__imm_data__ok$32$next[0:0]$10122 - assign $3\logical_op__oe__oe$35$next[0:0]$10157 $1\logical_op__oe__oe$35$next[0:0]$10130 - assign $3\logical_op__oe__ok$36$next[0:0]$10158 $1\logical_op__oe__ok$36$next[0:0]$10131 - assign $3\logical_op__rc__ok$34$next[0:0]$10159 $1\logical_op__rc__ok$34$next[0:0]$10133 - assign $3\logical_op__rc__rc$33$next[0:0]$10160 $1\logical_op__rc__rc$33$next[0:0]$10134 + assign $3\logical_op__imm_data__data$31$next[63:0]$10139 $1\logical_op__imm_data__data$31$next[63:0]$10105 + assign $3\logical_op__imm_data__ok$32$next[0:0]$10140 $1\logical_op__imm_data__ok$32$next[0:0]$10106 + assign $3\logical_op__oe__oe$35$next[0:0]$10141 $1\logical_op__oe__oe$35$next[0:0]$10114 + assign $3\logical_op__oe__ok$36$next[0:0]$10142 $1\logical_op__oe__ok$36$next[0:0]$10115 + assign $3\logical_op__rc__ok$34$next[0:0]$10143 $1\logical_op__rc__ok$34$next[0:0]$10117 + assign $3\logical_op__rc__rc$33$next[0:0]$10144 $1\logical_op__rc__rc$33$next[0:0]$10118 end sync always - update \logical_op__data_len$45$next $0\logical_op__data_len$45$next[3:0]$10101 - update \logical_op__fn_unit$30$next $0\logical_op__fn_unit$30$next[13:0]$10102 - update \logical_op__imm_data__data$31$next $0\logical_op__imm_data__data$31$next[63:0]$10103 - update \logical_op__imm_data__ok$32$next $0\logical_op__imm_data__ok$32$next[0:0]$10104 - update \logical_op__input_carry$39$next $0\logical_op__input_carry$39$next[1:0]$10105 - update \logical_op__insn$46$next $0\logical_op__insn$46$next[31:0]$10106 - update \logical_op__insn_type$29$next $0\logical_op__insn_type$29$next[6:0]$10107 - update \logical_op__invert_in$37$next $0\logical_op__invert_in$37$next[0:0]$10108 - update \logical_op__invert_out$40$next $0\logical_op__invert_out$40$next[0:0]$10109 - update \logical_op__is_32bit$43$next $0\logical_op__is_32bit$43$next[0:0]$10110 - update \logical_op__is_signed$44$next $0\logical_op__is_signed$44$next[0:0]$10111 - update \logical_op__oe__oe$35$next $0\logical_op__oe__oe$35$next[0:0]$10112 - update \logical_op__oe__ok$36$next $0\logical_op__oe__ok$36$next[0:0]$10113 - update \logical_op__output_carry$42$next $0\logical_op__output_carry$42$next[0:0]$10114 - update \logical_op__rc__ok$34$next $0\logical_op__rc__ok$34$next[0:0]$10115 - update \logical_op__rc__rc$33$next $0\logical_op__rc__rc$33$next[0:0]$10116 - update \logical_op__write_cr0$41$next $0\logical_op__write_cr0$41$next[0:0]$10117 - update \logical_op__zero_a$38$next $0\logical_op__zero_a$38$next[0:0]$10118 + update \logical_op__data_len$45$next $0\logical_op__data_len$45$next[3:0]$10085 + update \logical_op__fn_unit$30$next $0\logical_op__fn_unit$30$next[13:0]$10086 + update \logical_op__imm_data__data$31$next $0\logical_op__imm_data__data$31$next[63:0]$10087 + update \logical_op__imm_data__ok$32$next $0\logical_op__imm_data__ok$32$next[0:0]$10088 + update \logical_op__input_carry$39$next $0\logical_op__input_carry$39$next[1:0]$10089 + update \logical_op__insn$46$next $0\logical_op__insn$46$next[31:0]$10090 + update \logical_op__insn_type$29$next $0\logical_op__insn_type$29$next[6:0]$10091 + update \logical_op__invert_in$37$next $0\logical_op__invert_in$37$next[0:0]$10092 + update \logical_op__invert_out$40$next $0\logical_op__invert_out$40$next[0:0]$10093 + update \logical_op__is_32bit$43$next $0\logical_op__is_32bit$43$next[0:0]$10094 + update \logical_op__is_signed$44$next $0\logical_op__is_signed$44$next[0:0]$10095 + update \logical_op__oe__oe$35$next $0\logical_op__oe__oe$35$next[0:0]$10096 + update \logical_op__oe__ok$36$next $0\logical_op__oe__ok$36$next[0:0]$10097 + update \logical_op__output_carry$42$next $0\logical_op__output_carry$42$next[0:0]$10098 + update \logical_op__rc__ok$34$next $0\logical_op__rc__ok$34$next[0:0]$10099 + update \logical_op__rc__rc$33$next $0\logical_op__rc__rc$33$next[0:0]$10100 + update \logical_op__write_cr0$41$next $0\logical_op__write_cr0$41$next[0:0]$10101 + update \logical_op__zero_a$38$next $0\logical_op__zero_a$38$next[0:0]$10102 end - attribute \src "libresoc.v:173608.3-173622.6" - process $proc$libresoc.v:173608$10161 + attribute \src "libresoc.v:174916.3-174930.6" + process $proc$libresoc.v:174916$10145 assign { } { } assign { } { } - assign $0\ra$47$next[63:0]$10162 $1\ra$47$next[63:0]$10163 - attribute \src "libresoc.v:173609.5-173609.29" + assign $0\ra$47$next[63:0]$10146 $1\ra$47$next[63:0]$10147 + attribute \src "libresoc.v:174917.5-174917.29" switch \initial - attribute \src "libresoc.v:173609.9-173609.17" + attribute \src "libresoc.v:174917.9-174917.17" case 1'1 case end @@ -353022,30 +324392,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ra$47$next[63:0]$10163 $2\ra$47$next[63:0]$10164 + assign $1\ra$47$next[63:0]$10147 $2\ra$47$next[63:0]$10148 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\ra$47$next[63:0]$10164 \ra + assign $2\ra$47$next[63:0]$10148 \ra case - assign $2\ra$47$next[63:0]$10164 \ra$47 + assign $2\ra$47$next[63:0]$10148 \ra$47 end case - assign $1\ra$47$next[63:0]$10163 \ra$47 + assign $1\ra$47$next[63:0]$10147 \ra$47 end sync always - update \ra$47$next $0\ra$47$next[63:0]$10162 + update \ra$47$next $0\ra$47$next[63:0]$10146 end - attribute \src "libresoc.v:173623.3-173637.6" - process $proc$libresoc.v:173623$10165 + attribute \src "libresoc.v:174931.3-174945.6" + process $proc$libresoc.v:174931$10149 assign { } { } assign { } { } - assign $0\rb$48$next[63:0]$10166 $1\rb$48$next[63:0]$10167 - attribute \src "libresoc.v:173624.5-173624.29" + assign $0\rb$48$next[63:0]$10150 $1\rb$48$next[63:0]$10151 + attribute \src "libresoc.v:174932.5-174932.29" switch \initial - attribute \src "libresoc.v:173624.9-173624.17" + attribute \src "libresoc.v:174932.9-174932.17" case 1'1 case end @@ -353054,30 +324424,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rb$48$next[63:0]$10167 $2\rb$48$next[63:0]$10168 + assign $1\rb$48$next[63:0]$10151 $2\rb$48$next[63:0]$10152 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\rb$48$next[63:0]$10168 \rb + assign $2\rb$48$next[63:0]$10152 \rb case - assign $2\rb$48$next[63:0]$10168 \rb$48 + assign $2\rb$48$next[63:0]$10152 \rb$48 end case - assign $1\rb$48$next[63:0]$10167 \rb$48 + assign $1\rb$48$next[63:0]$10151 \rb$48 end sync always - update \rb$48$next $0\rb$48$next[63:0]$10166 + update \rb$48$next $0\rb$48$next[63:0]$10150 end - attribute \src "libresoc.v:173638.3-173652.6" - process $proc$libresoc.v:173638$10169 + attribute \src "libresoc.v:174946.3-174960.6" + process $proc$libresoc.v:174946$10153 assign { } { } assign { } { } - assign $0\xer_so$49$next[0:0]$10170 $1\xer_so$49$next[0:0]$10171 - attribute \src "libresoc.v:173639.5-173639.29" + assign $0\xer_so$49$next[0:0]$10154 $1\xer_so$49$next[0:0]$10155 + attribute \src "libresoc.v:174947.5-174947.29" switch \initial - attribute \src "libresoc.v:173639.9-173639.17" + attribute \src "libresoc.v:174947.9-174947.17" case 1'1 case end @@ -353086,30 +324456,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xer_so$49$next[0:0]$10171 $2\xer_so$49$next[0:0]$10172 + assign $1\xer_so$49$next[0:0]$10155 $2\xer_so$49$next[0:0]$10156 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xer_so$49$next[0:0]$10172 \xer_so + assign $2\xer_so$49$next[0:0]$10156 \xer_so case - assign $2\xer_so$49$next[0:0]$10172 \xer_so$49 + assign $2\xer_so$49$next[0:0]$10156 \xer_so$49 end case - assign $1\xer_so$49$next[0:0]$10171 \xer_so$49 + assign $1\xer_so$49$next[0:0]$10155 \xer_so$49 end sync always - update \xer_so$49$next $0\xer_so$49$next[0:0]$10170 + update \xer_so$49$next $0\xer_so$49$next[0:0]$10154 end - attribute \src "libresoc.v:173653.3-173667.6" - process $proc$libresoc.v:173653$10173 + attribute \src "libresoc.v:174961.3-174975.6" + process $proc$libresoc.v:174961$10157 assign { } { } assign { } { } - assign $0\divisor_neg$50$next[0:0]$10174 $1\divisor_neg$50$next[0:0]$10175 - attribute \src "libresoc.v:173654.5-173654.29" + assign $0\divisor_neg$50$next[0:0]$10158 $1\divisor_neg$50$next[0:0]$10159 + attribute \src "libresoc.v:174962.5-174962.29" switch \initial - attribute \src "libresoc.v:173654.9-173654.17" + attribute \src "libresoc.v:174962.9-174962.17" case 1'1 case end @@ -353118,30 +324488,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\divisor_neg$50$next[0:0]$10175 $2\divisor_neg$50$next[0:0]$10176 + assign $1\divisor_neg$50$next[0:0]$10159 $2\divisor_neg$50$next[0:0]$10160 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\divisor_neg$50$next[0:0]$10176 \divisor_neg + assign $2\divisor_neg$50$next[0:0]$10160 \divisor_neg case - assign $2\divisor_neg$50$next[0:0]$10176 \divisor_neg$50 + assign $2\divisor_neg$50$next[0:0]$10160 \divisor_neg$50 end case - assign $1\divisor_neg$50$next[0:0]$10175 \divisor_neg$50 + assign $1\divisor_neg$50$next[0:0]$10159 \divisor_neg$50 end sync always - update \divisor_neg$50$next $0\divisor_neg$50$next[0:0]$10174 + update \divisor_neg$50$next $0\divisor_neg$50$next[0:0]$10158 end - attribute \src "libresoc.v:173668.3-173682.6" - process $proc$libresoc.v:173668$10177 + attribute \src "libresoc.v:174976.3-174990.6" + process $proc$libresoc.v:174976$10161 assign { } { } assign { } { } - assign $0\dividend_neg$51$next[0:0]$10178 $1\dividend_neg$51$next[0:0]$10179 - attribute \src "libresoc.v:173669.5-173669.29" + assign $0\dividend_neg$51$next[0:0]$10162 $1\dividend_neg$51$next[0:0]$10163 + attribute \src "libresoc.v:174977.5-174977.29" switch \initial - attribute \src "libresoc.v:173669.9-173669.17" + attribute \src "libresoc.v:174977.9-174977.17" case 1'1 case end @@ -353150,30 +324520,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dividend_neg$51$next[0:0]$10179 $2\dividend_neg$51$next[0:0]$10180 + assign $1\dividend_neg$51$next[0:0]$10163 $2\dividend_neg$51$next[0:0]$10164 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dividend_neg$51$next[0:0]$10180 \dividend_neg + assign $2\dividend_neg$51$next[0:0]$10164 \dividend_neg case - assign $2\dividend_neg$51$next[0:0]$10180 \dividend_neg$51 + assign $2\dividend_neg$51$next[0:0]$10164 \dividend_neg$51 end case - assign $1\dividend_neg$51$next[0:0]$10179 \dividend_neg$51 + assign $1\dividend_neg$51$next[0:0]$10163 \dividend_neg$51 end sync always - update \dividend_neg$51$next $0\dividend_neg$51$next[0:0]$10178 + update \dividend_neg$51$next $0\dividend_neg$51$next[0:0]$10162 end - attribute \src "libresoc.v:173683.3-173697.6" - process $proc$libresoc.v:173683$10181 + attribute \src "libresoc.v:174991.3-175005.6" + process $proc$libresoc.v:174991$10165 assign { } { } assign { } { } - assign $0\dive_abs_ov32$52$next[0:0]$10182 $1\dive_abs_ov32$52$next[0:0]$10183 - attribute \src "libresoc.v:173684.5-173684.29" + assign $0\dive_abs_ov32$52$next[0:0]$10166 $1\dive_abs_ov32$52$next[0:0]$10167 + attribute \src "libresoc.v:174992.5-174992.29" switch \initial - attribute \src "libresoc.v:173684.9-173684.17" + attribute \src "libresoc.v:174992.9-174992.17" case 1'1 case end @@ -353182,30 +324552,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dive_abs_ov32$52$next[0:0]$10183 $2\dive_abs_ov32$52$next[0:0]$10184 + assign $1\dive_abs_ov32$52$next[0:0]$10167 $2\dive_abs_ov32$52$next[0:0]$10168 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dive_abs_ov32$52$next[0:0]$10184 \dive_abs_ov32 + assign $2\dive_abs_ov32$52$next[0:0]$10168 \dive_abs_ov32 case - assign $2\dive_abs_ov32$52$next[0:0]$10184 \dive_abs_ov32$52 + assign $2\dive_abs_ov32$52$next[0:0]$10168 \dive_abs_ov32$52 end case - assign $1\dive_abs_ov32$52$next[0:0]$10183 \dive_abs_ov32$52 + assign $1\dive_abs_ov32$52$next[0:0]$10167 \dive_abs_ov32$52 end sync always - update \dive_abs_ov32$52$next $0\dive_abs_ov32$52$next[0:0]$10182 + update \dive_abs_ov32$52$next $0\dive_abs_ov32$52$next[0:0]$10166 end - attribute \src "libresoc.v:173698.3-173712.6" - process $proc$libresoc.v:173698$10185 + attribute \src "libresoc.v:175006.3-175020.6" + process $proc$libresoc.v:175006$10169 assign { } { } assign { } { } - assign $0\dive_abs_ov64$53$next[0:0]$10186 $1\dive_abs_ov64$53$next[0:0]$10187 - attribute \src "libresoc.v:173699.5-173699.29" + assign $0\dive_abs_ov64$53$next[0:0]$10170 $1\dive_abs_ov64$53$next[0:0]$10171 + attribute \src "libresoc.v:175007.5-175007.29" switch \initial - attribute \src "libresoc.v:173699.9-173699.17" + attribute \src "libresoc.v:175007.9-175007.17" case 1'1 case end @@ -353214,30 +324584,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dive_abs_ov64$53$next[0:0]$10187 $2\dive_abs_ov64$53$next[0:0]$10188 + assign $1\dive_abs_ov64$53$next[0:0]$10171 $2\dive_abs_ov64$53$next[0:0]$10172 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dive_abs_ov64$53$next[0:0]$10188 \dive_abs_ov64 + assign $2\dive_abs_ov64$53$next[0:0]$10172 \dive_abs_ov64 case - assign $2\dive_abs_ov64$53$next[0:0]$10188 \dive_abs_ov64$53 + assign $2\dive_abs_ov64$53$next[0:0]$10172 \dive_abs_ov64$53 end case - assign $1\dive_abs_ov64$53$next[0:0]$10187 \dive_abs_ov64$53 + assign $1\dive_abs_ov64$53$next[0:0]$10171 \dive_abs_ov64$53 end sync always - update \dive_abs_ov64$53$next $0\dive_abs_ov64$53$next[0:0]$10186 + update \dive_abs_ov64$53$next $0\dive_abs_ov64$53$next[0:0]$10170 end - attribute \src "libresoc.v:173713.3-173727.6" - process $proc$libresoc.v:173713$10189 + attribute \src "libresoc.v:175021.3-175035.6" + process $proc$libresoc.v:175021$10173 assign { } { } assign { } { } - assign $0\div_by_zero$54$next[0:0]$10190 $1\div_by_zero$54$next[0:0]$10191 - attribute \src "libresoc.v:173714.5-173714.29" + assign $0\div_by_zero$54$next[0:0]$10174 $1\div_by_zero$54$next[0:0]$10175 + attribute \src "libresoc.v:175022.5-175022.29" switch \initial - attribute \src "libresoc.v:173714.9-173714.17" + attribute \src "libresoc.v:175022.9-175022.17" case 1'1 case end @@ -353246,30 +324616,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\div_by_zero$54$next[0:0]$10191 $2\div_by_zero$54$next[0:0]$10192 + assign $1\div_by_zero$54$next[0:0]$10175 $2\div_by_zero$54$next[0:0]$10176 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\div_by_zero$54$next[0:0]$10192 \div_by_zero + assign $2\div_by_zero$54$next[0:0]$10176 \div_by_zero case - assign $2\div_by_zero$54$next[0:0]$10192 \div_by_zero$54 + assign $2\div_by_zero$54$next[0:0]$10176 \div_by_zero$54 end case - assign $1\div_by_zero$54$next[0:0]$10191 \div_by_zero$54 + assign $1\div_by_zero$54$next[0:0]$10175 \div_by_zero$54 end sync always - update \div_by_zero$54$next $0\div_by_zero$54$next[0:0]$10190 + update \div_by_zero$54$next $0\div_by_zero$54$next[0:0]$10174 end - attribute \src "libresoc.v:173728.3-173742.6" - process $proc$libresoc.v:173728$10193 + attribute \src "libresoc.v:175036.3-175050.6" + process $proc$libresoc.v:175036$10177 assign { } { } assign { } { } - assign $0\dividend$68$next[127:0]$10194 $1\dividend$68$next[127:0]$10195 - attribute \src "libresoc.v:173729.5-173729.29" + assign $0\dividend$68$next[127:0]$10178 $1\dividend$68$next[127:0]$10179 + attribute \src "libresoc.v:175037.5-175037.29" switch \initial - attribute \src "libresoc.v:173729.9-173729.17" + attribute \src "libresoc.v:175037.9-175037.17" case 1'1 case end @@ -353278,30 +324648,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dividend$68$next[127:0]$10195 $2\dividend$68$next[127:0]$10196 + assign $1\dividend$68$next[127:0]$10179 $2\dividend$68$next[127:0]$10180 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dividend$68$next[127:0]$10196 \dividend + assign $2\dividend$68$next[127:0]$10180 \dividend case - assign $2\dividend$68$next[127:0]$10196 \dividend$68 + assign $2\dividend$68$next[127:0]$10180 \dividend$68 end case - assign $1\dividend$68$next[127:0]$10195 \dividend$68 + assign $1\dividend$68$next[127:0]$10179 \dividend$68 end sync always - update \dividend$68$next $0\dividend$68$next[127:0]$10194 + update \dividend$68$next $0\dividend$68$next[127:0]$10178 end - attribute \src "libresoc.v:173743.3-173757.6" - process $proc$libresoc.v:173743$10197 + attribute \src "libresoc.v:175051.3-175065.6" + process $proc$libresoc.v:175051$10181 assign { } { } assign { } { } - assign $0\divisor_radicand$65$next[63:0]$10198 $1\divisor_radicand$65$next[63:0]$10199 - attribute \src "libresoc.v:173744.5-173744.29" + assign $0\divisor_radicand$65$next[63:0]$10182 $1\divisor_radicand$65$next[63:0]$10183 + attribute \src "libresoc.v:175052.5-175052.29" switch \initial - attribute \src "libresoc.v:173744.9-173744.17" + attribute \src "libresoc.v:175052.9-175052.17" case 1'1 case end @@ -353310,30 +324680,30 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\divisor_radicand$65$next[63:0]$10199 $2\divisor_radicand$65$next[63:0]$10200 + assign $1\divisor_radicand$65$next[63:0]$10183 $2\divisor_radicand$65$next[63:0]$10184 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\divisor_radicand$65$next[63:0]$10200 \divisor_radicand + assign $2\divisor_radicand$65$next[63:0]$10184 \divisor_radicand case - assign $2\divisor_radicand$65$next[63:0]$10200 \divisor_radicand$65 + assign $2\divisor_radicand$65$next[63:0]$10184 \divisor_radicand$65 end case - assign $1\divisor_radicand$65$next[63:0]$10199 \divisor_radicand$65 + assign $1\divisor_radicand$65$next[63:0]$10183 \divisor_radicand$65 end sync always - update \divisor_radicand$65$next $0\divisor_radicand$65$next[63:0]$10198 + update \divisor_radicand$65$next $0\divisor_radicand$65$next[63:0]$10182 end - attribute \src "libresoc.v:173758.3-173772.6" - process $proc$libresoc.v:173758$10201 + attribute \src "libresoc.v:175066.3-175080.6" + process $proc$libresoc.v:175066$10185 assign { } { } assign { } { } - assign $0\operation$69$next[1:0]$10202 $1\operation$69$next[1:0]$10203 - attribute \src "libresoc.v:173759.5-173759.29" + assign $0\operation$69$next[1:0]$10186 $1\operation$69$next[1:0]$10187 + attribute \src "libresoc.v:175067.5-175067.29" switch \initial - attribute \src "libresoc.v:173759.9-173759.17" + attribute \src "libresoc.v:175067.9-175067.17" case 1'1 case end @@ -353342,28 +324712,28 @@ module \pipe_middle_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\operation$69$next[1:0]$10203 $2\operation$69$next[1:0]$10204 + assign $1\operation$69$next[1:0]$10187 $2\operation$69$next[1:0]$10188 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:178" switch \p_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\operation$69$next[1:0]$10204 \operation + assign $2\operation$69$next[1:0]$10188 \operation case - assign $2\operation$69$next[1:0]$10204 \operation$69 + assign $2\operation$69$next[1:0]$10188 \operation$69 end case - assign $1\operation$69$next[1:0]$10203 \operation$69 + assign $1\operation$69$next[1:0]$10187 \operation$69 end sync always - update \operation$69$next $0\operation$69$next[1:0]$10202 + update \operation$69$next $0\operation$69$next[1:0]$10186 end - connect \$56 $sshl$libresoc.v:173375$10011_Y - connect \$55 $pos$libresoc.v:173376$10013_Y - connect \$59 $not$libresoc.v:173377$10014_Y - connect \$61 $ge$libresoc.v:173378$10015_Y - connect \$63 $and$libresoc.v:173379$10016_Y - connect \$66 $and$libresoc.v:173380$10017_Y + connect \$56 $sshl$libresoc.v:174683$9995_Y + connect \$55 $pos$libresoc.v:174684$9997_Y + connect \$59 $not$libresoc.v:174685$9998_Y + connect \$61 $ge$libresoc.v:174686$9999_Y + connect \$63 $and$libresoc.v:174687$10000_Y + connect \$66 $and$libresoc.v:174688$10001_Y connect \p_ready_o \empty connect \n_valid_o \$63 connect \remainder \$55 @@ -353380,282 +324750,282 @@ module \pipe_middle_0 connect \muxid$1 \muxid$28 connect \div_state_init_dividend \dividend end -attribute \src "libresoc.v:173792.1-175337.10" +attribute \src "libresoc.v:175100.1-176645.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start" attribute \generator "nMigen" module \pipe_start - attribute \src "libresoc.v:175143.3-175155.6" - wire $0\div_by_zero$next[0:0]$10314 - attribute \src "libresoc.v:174929.3-174930.39" + attribute \src "libresoc.v:176451.3-176463.6" + wire $0\div_by_zero$next[0:0]$10298 + attribute \src "libresoc.v:176237.3-176238.39" wire $0\div_by_zero[0:0] - attribute \src "libresoc.v:175117.3-175129.6" - wire $0\dive_abs_ov32$next[0:0]$10308 - attribute \src "libresoc.v:174933.3-174934.43" + attribute \src "libresoc.v:176425.3-176437.6" + wire $0\dive_abs_ov32$next[0:0]$10292 + attribute \src "libresoc.v:176241.3-176242.43" wire $0\dive_abs_ov32[0:0] - attribute \src "libresoc.v:175130.3-175142.6" - wire $0\dive_abs_ov64$next[0:0]$10311 - attribute \src "libresoc.v:174931.3-174932.43" + attribute \src "libresoc.v:176438.3-176450.6" + wire $0\dive_abs_ov64$next[0:0]$10295 + attribute \src "libresoc.v:176239.3-176240.43" wire $0\dive_abs_ov64[0:0] - attribute \src "libresoc.v:175156.3-175168.6" - wire width 128 $0\dividend$next[127:0]$10317 - attribute \src "libresoc.v:174927.3-174928.33" + attribute \src "libresoc.v:176464.3-176476.6" + wire width 128 $0\dividend$next[127:0]$10301 + attribute \src "libresoc.v:176235.3-176236.33" wire width 128 $0\dividend[127:0] - attribute \src "libresoc.v:175104.3-175116.6" - wire $0\dividend_neg$next[0:0]$10305 - attribute \src "libresoc.v:174935.3-174936.41" + attribute \src "libresoc.v:176412.3-176424.6" + wire $0\dividend_neg$next[0:0]$10289 + attribute \src "libresoc.v:176243.3-176244.41" wire $0\dividend_neg[0:0] - attribute \src "libresoc.v:175091.3-175103.6" - wire $0\divisor_neg$next[0:0]$10302 - attribute \src "libresoc.v:174937.3-174938.39" + attribute \src "libresoc.v:176399.3-176411.6" + wire $0\divisor_neg$next[0:0]$10286 + attribute \src "libresoc.v:176245.3-176246.39" wire $0\divisor_neg[0:0] - attribute \src "libresoc.v:175169.3-175181.6" - wire width 64 $0\divisor_radicand$next[63:0]$10320 - attribute \src "libresoc.v:174925.3-174926.49" + attribute \src "libresoc.v:176477.3-176489.6" + wire width 64 $0\divisor_radicand$next[63:0]$10304 + attribute \src "libresoc.v:176233.3-176234.49" wire width 64 $0\divisor_radicand[63:0] - attribute \src "libresoc.v:173793.7-173793.20" + attribute \src "libresoc.v:175101.7-175101.20" wire $0\initial[0:0] - attribute \src "libresoc.v:175226.3-175267.6" - wire width 4 $0\logical_op__data_len$next[3:0]$10333 - attribute \src "libresoc.v:174977.3-174978.57" + attribute \src "libresoc.v:176534.3-176575.6" + wire width 4 $0\logical_op__data_len$next[3:0]$10317 + attribute \src "libresoc.v:176285.3-176286.57" wire width 4 $0\logical_op__data_len[3:0] - attribute \src "libresoc.v:175226.3-175267.6" - wire width 14 $0\logical_op__fn_unit$next[13:0]$10334 - attribute \src "libresoc.v:174947.3-174948.55" + attribute \src "libresoc.v:176534.3-176575.6" + wire width 14 $0\logical_op__fn_unit$next[13:0]$10318 + attribute \src "libresoc.v:176255.3-176256.55" wire width 14 $0\logical_op__fn_unit[13:0] - attribute \src "libresoc.v:175226.3-175267.6" - wire width 64 $0\logical_op__imm_data__data$next[63:0]$10335 - attribute \src "libresoc.v:174949.3-174950.69" + attribute \src "libresoc.v:176534.3-176575.6" + wire width 64 $0\logical_op__imm_data__data$next[63:0]$10319 + attribute \src "libresoc.v:176257.3-176258.69" wire width 64 $0\logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:175226.3-175267.6" - wire $0\logical_op__imm_data__ok$next[0:0]$10336 - attribute \src "libresoc.v:174951.3-174952.65" + attribute \src "libresoc.v:176534.3-176575.6" + wire $0\logical_op__imm_data__ok$next[0:0]$10320 + attribute \src "libresoc.v:176259.3-176260.65" wire $0\logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:175226.3-175267.6" - wire width 2 $0\logical_op__input_carry$next[1:0]$10337 - attribute \src "libresoc.v:174965.3-174966.63" + attribute \src "libresoc.v:176534.3-176575.6" + wire width 2 $0\logical_op__input_carry$next[1:0]$10321 + attribute \src "libresoc.v:176273.3-176274.63" wire width 2 $0\logical_op__input_carry[1:0] - attribute \src "libresoc.v:175226.3-175267.6" - wire width 32 $0\logical_op__insn$next[31:0]$10338 - attribute \src "libresoc.v:174979.3-174980.49" + attribute \src "libresoc.v:176534.3-176575.6" + wire width 32 $0\logical_op__insn$next[31:0]$10322 + attribute \src "libresoc.v:176287.3-176288.49" wire width 32 $0\logical_op__insn[31:0] - attribute \src "libresoc.v:175226.3-175267.6" - wire width 7 $0\logical_op__insn_type$next[6:0]$10339 - attribute \src "libresoc.v:174945.3-174946.59" + attribute \src "libresoc.v:176534.3-176575.6" + wire width 7 $0\logical_op__insn_type$next[6:0]$10323 + attribute \src "libresoc.v:176253.3-176254.59" wire width 7 $0\logical_op__insn_type[6:0] - attribute \src "libresoc.v:175226.3-175267.6" - wire $0\logical_op__invert_in$next[0:0]$10340 - attribute \src "libresoc.v:174961.3-174962.59" + attribute \src "libresoc.v:176534.3-176575.6" + wire $0\logical_op__invert_in$next[0:0]$10324 + attribute \src "libresoc.v:176269.3-176270.59" wire $0\logical_op__invert_in[0:0] - attribute \src "libresoc.v:175226.3-175267.6" - wire $0\logical_op__invert_out$next[0:0]$10341 - attribute \src "libresoc.v:174967.3-174968.61" + attribute \src "libresoc.v:176534.3-176575.6" + wire $0\logical_op__invert_out$next[0:0]$10325 + attribute \src "libresoc.v:176275.3-176276.61" wire $0\logical_op__invert_out[0:0] - attribute \src "libresoc.v:175226.3-175267.6" - wire $0\logical_op__is_32bit$next[0:0]$10342 - attribute \src "libresoc.v:174973.3-174974.57" + attribute \src "libresoc.v:176534.3-176575.6" + wire $0\logical_op__is_32bit$next[0:0]$10326 + attribute \src "libresoc.v:176281.3-176282.57" wire $0\logical_op__is_32bit[0:0] - attribute \src "libresoc.v:175226.3-175267.6" - wire $0\logical_op__is_signed$next[0:0]$10343 - attribute \src "libresoc.v:174975.3-174976.59" + attribute \src "libresoc.v:176534.3-176575.6" + wire $0\logical_op__is_signed$next[0:0]$10327 + attribute \src "libresoc.v:176283.3-176284.59" wire $0\logical_op__is_signed[0:0] - attribute \src "libresoc.v:175226.3-175267.6" - wire $0\logical_op__oe__oe$next[0:0]$10344 - attribute \src "libresoc.v:174957.3-174958.53" + attribute \src "libresoc.v:176534.3-176575.6" + wire $0\logical_op__oe__oe$next[0:0]$10328 + attribute \src "libresoc.v:176265.3-176266.53" wire $0\logical_op__oe__oe[0:0] - attribute \src "libresoc.v:175226.3-175267.6" - wire $0\logical_op__oe__ok$next[0:0]$10345 - attribute \src "libresoc.v:174959.3-174960.53" + attribute \src "libresoc.v:176534.3-176575.6" + wire $0\logical_op__oe__ok$next[0:0]$10329 + attribute \src "libresoc.v:176267.3-176268.53" wire $0\logical_op__oe__ok[0:0] - attribute \src "libresoc.v:175226.3-175267.6" - wire $0\logical_op__output_carry$next[0:0]$10346 - attribute \src "libresoc.v:174971.3-174972.65" + attribute \src "libresoc.v:176534.3-176575.6" + wire $0\logical_op__output_carry$next[0:0]$10330 + attribute \src "libresoc.v:176279.3-176280.65" wire $0\logical_op__output_carry[0:0] - attribute \src "libresoc.v:175226.3-175267.6" - wire $0\logical_op__rc__ok$next[0:0]$10347 - attribute \src "libresoc.v:174955.3-174956.53" + attribute \src "libresoc.v:176534.3-176575.6" + wire $0\logical_op__rc__ok$next[0:0]$10331 + attribute \src "libresoc.v:176263.3-176264.53" wire $0\logical_op__rc__ok[0:0] - attribute \src "libresoc.v:175226.3-175267.6" - wire $0\logical_op__rc__rc$next[0:0]$10348 - attribute \src "libresoc.v:174953.3-174954.53" + attribute \src "libresoc.v:176534.3-176575.6" + wire $0\logical_op__rc__rc$next[0:0]$10332 + attribute \src "libresoc.v:176261.3-176262.53" wire $0\logical_op__rc__rc[0:0] - attribute \src "libresoc.v:175226.3-175267.6" - wire $0\logical_op__write_cr0$next[0:0]$10349 - attribute \src "libresoc.v:174969.3-174970.59" + attribute \src "libresoc.v:176534.3-176575.6" + wire $0\logical_op__write_cr0$next[0:0]$10333 + attribute \src "libresoc.v:176277.3-176278.59" wire $0\logical_op__write_cr0[0:0] - attribute \src "libresoc.v:175226.3-175267.6" - wire $0\logical_op__zero_a$next[0:0]$10350 - attribute \src "libresoc.v:174963.3-174964.53" + attribute \src "libresoc.v:176534.3-176575.6" + wire $0\logical_op__zero_a$next[0:0]$10334 + attribute \src "libresoc.v:176271.3-176272.53" wire $0\logical_op__zero_a[0:0] - attribute \src "libresoc.v:175213.3-175225.6" - wire width 2 $0\muxid$next[1:0]$10330 - attribute \src "libresoc.v:174981.3-174982.27" + attribute \src "libresoc.v:176521.3-176533.6" + wire width 2 $0\muxid$next[1:0]$10314 + attribute \src "libresoc.v:176289.3-176290.27" wire width 2 $0\muxid[1:0] - attribute \src "libresoc.v:175182.3-175194.6" - wire width 2 $0\operation$next[1:0]$10323 - attribute \src "libresoc.v:174923.3-174924.35" + attribute \src "libresoc.v:176490.3-176502.6" + wire width 2 $0\operation$next[1:0]$10307 + attribute \src "libresoc.v:176231.3-176232.35" wire width 2 $0\operation[1:0] - attribute \src "libresoc.v:175195.3-175212.6" - wire $0\r_busy$next[0:0]$10326 - attribute \src "libresoc.v:174983.3-174984.29" + attribute \src "libresoc.v:176503.3-176520.6" + wire $0\r_busy$next[0:0]$10310 + attribute \src "libresoc.v:176291.3-176292.29" wire $0\r_busy[0:0] - attribute \src "libresoc.v:175268.3-175280.6" - wire width 64 $0\ra$next[63:0]$10376 - attribute \src "libresoc.v:174943.3-174944.21" + attribute \src "libresoc.v:176576.3-176588.6" + wire width 64 $0\ra$next[63:0]$10360 + attribute \src "libresoc.v:176251.3-176252.21" wire width 64 $0\ra[63:0] - attribute \src "libresoc.v:175281.3-175293.6" - wire width 64 $0\rb$next[63:0]$10379 - attribute \src "libresoc.v:174941.3-174942.21" + attribute \src "libresoc.v:176589.3-176601.6" + wire width 64 $0\rb$next[63:0]$10363 + attribute \src "libresoc.v:176249.3-176250.21" wire width 64 $0\rb[63:0] - attribute \src "libresoc.v:175294.3-175306.6" - wire $0\xer_so$next[0:0]$10382 - attribute \src "libresoc.v:174939.3-174940.29" + attribute \src "libresoc.v:176602.3-176614.6" + wire $0\xer_so$next[0:0]$10366 + attribute \src "libresoc.v:176247.3-176248.29" wire $0\xer_so[0:0] - attribute \src "libresoc.v:175143.3-175155.6" - wire $1\div_by_zero$next[0:0]$10315 - attribute \src "libresoc.v:173802.7-173802.25" + attribute \src "libresoc.v:176451.3-176463.6" + wire $1\div_by_zero$next[0:0]$10299 + attribute \src "libresoc.v:175110.7-175110.25" wire $1\div_by_zero[0:0] - attribute \src "libresoc.v:175117.3-175129.6" - wire $1\dive_abs_ov32$next[0:0]$10309 - attribute \src "libresoc.v:173809.7-173809.27" + attribute \src "libresoc.v:176425.3-176437.6" + wire $1\dive_abs_ov32$next[0:0]$10293 + attribute \src "libresoc.v:175117.7-175117.27" wire $1\dive_abs_ov32[0:0] - attribute \src "libresoc.v:175130.3-175142.6" - wire $1\dive_abs_ov64$next[0:0]$10312 - attribute \src "libresoc.v:173816.7-173816.27" + attribute \src "libresoc.v:176438.3-176450.6" + wire $1\dive_abs_ov64$next[0:0]$10296 + attribute \src "libresoc.v:175124.7-175124.27" wire $1\dive_abs_ov64[0:0] - attribute \src "libresoc.v:175156.3-175168.6" - wire width 128 $1\dividend$next[127:0]$10318 - attribute \src "libresoc.v:173823.15-173823.63" + attribute \src "libresoc.v:176464.3-176476.6" + wire width 128 $1\dividend$next[127:0]$10302 + attribute \src "libresoc.v:175131.15-175131.63" wire width 128 $1\dividend[127:0] - attribute \src "libresoc.v:175104.3-175116.6" - wire $1\dividend_neg$next[0:0]$10306 - attribute \src "libresoc.v:173830.7-173830.26" + attribute \src "libresoc.v:176412.3-176424.6" + wire $1\dividend_neg$next[0:0]$10290 + attribute \src "libresoc.v:175138.7-175138.26" wire $1\dividend_neg[0:0] - attribute \src "libresoc.v:175091.3-175103.6" - wire $1\divisor_neg$next[0:0]$10303 - attribute \src "libresoc.v:173837.7-173837.25" + attribute \src "libresoc.v:176399.3-176411.6" + wire $1\divisor_neg$next[0:0]$10287 + attribute \src "libresoc.v:175145.7-175145.25" wire $1\divisor_neg[0:0] - attribute \src "libresoc.v:175169.3-175181.6" - wire width 64 $1\divisor_radicand$next[63:0]$10321 - attribute \src "libresoc.v:173844.14-173844.53" + attribute \src "libresoc.v:176477.3-176489.6" + wire width 64 $1\divisor_radicand$next[63:0]$10305 + attribute \src "libresoc.v:175152.14-175152.53" wire width 64 $1\divisor_radicand[63:0] - attribute \src "libresoc.v:175226.3-175267.6" - wire width 4 $1\logical_op__data_len$next[3:0]$10351 - attribute \src "libresoc.v:174127.13-174127.40" + attribute \src "libresoc.v:176534.3-176575.6" + wire width 4 $1\logical_op__data_len$next[3:0]$10335 + attribute \src "libresoc.v:175435.13-175435.40" wire width 4 $1\logical_op__data_len[3:0] - attribute \src "libresoc.v:175226.3-175267.6" - wire width 14 $1\logical_op__fn_unit$next[13:0]$10352 - attribute \src "libresoc.v:174151.14-174151.44" + attribute \src "libresoc.v:176534.3-176575.6" + wire width 14 $1\logical_op__fn_unit$next[13:0]$10336 + attribute \src "libresoc.v:175459.14-175459.44" wire width 14 $1\logical_op__fn_unit[13:0] - attribute \src "libresoc.v:175226.3-175267.6" - wire width 64 $1\logical_op__imm_data__data$next[63:0]$10353 - attribute \src "libresoc.v:174190.14-174190.63" + attribute \src "libresoc.v:176534.3-176575.6" + wire width 64 $1\logical_op__imm_data__data$next[63:0]$10337 + attribute \src "libresoc.v:175498.14-175498.63" wire width 64 $1\logical_op__imm_data__data[63:0] - attribute \src "libresoc.v:175226.3-175267.6" - wire $1\logical_op__imm_data__ok$next[0:0]$10354 - attribute \src "libresoc.v:174199.7-174199.38" + attribute \src "libresoc.v:176534.3-176575.6" + wire $1\logical_op__imm_data__ok$next[0:0]$10338 + attribute \src "libresoc.v:175507.7-175507.38" wire $1\logical_op__imm_data__ok[0:0] - attribute \src "libresoc.v:175226.3-175267.6" - wire width 2 $1\logical_op__input_carry$next[1:0]$10355 - attribute \src "libresoc.v:174212.13-174212.43" + attribute \src "libresoc.v:176534.3-176575.6" + wire width 2 $1\logical_op__input_carry$next[1:0]$10339 + attribute \src "libresoc.v:175520.13-175520.43" wire width 2 $1\logical_op__input_carry[1:0] - attribute \src "libresoc.v:175226.3-175267.6" - wire width 32 $1\logical_op__insn$next[31:0]$10356 - attribute \src "libresoc.v:174229.14-174229.38" + attribute \src "libresoc.v:176534.3-176575.6" + wire width 32 $1\logical_op__insn$next[31:0]$10340 + attribute \src "libresoc.v:175537.14-175537.38" wire width 32 $1\logical_op__insn[31:0] - attribute \src "libresoc.v:175226.3-175267.6" - wire width 7 $1\logical_op__insn_type$next[6:0]$10357 - attribute \src "libresoc.v:174313.13-174313.42" + attribute \src "libresoc.v:176534.3-176575.6" + wire width 7 $1\logical_op__insn_type$next[6:0]$10341 + attribute \src "libresoc.v:175621.13-175621.42" wire width 7 $1\logical_op__insn_type[6:0] - attribute \src "libresoc.v:175226.3-175267.6" - wire $1\logical_op__invert_in$next[0:0]$10358 - attribute \src "libresoc.v:174472.7-174472.35" + attribute \src "libresoc.v:176534.3-176575.6" + wire $1\logical_op__invert_in$next[0:0]$10342 + attribute \src "libresoc.v:175780.7-175780.35" wire $1\logical_op__invert_in[0:0] - attribute \src "libresoc.v:175226.3-175267.6" - wire $1\logical_op__invert_out$next[0:0]$10359 - attribute \src "libresoc.v:174481.7-174481.36" + attribute \src "libresoc.v:176534.3-176575.6" + wire $1\logical_op__invert_out$next[0:0]$10343 + attribute \src "libresoc.v:175789.7-175789.36" wire $1\logical_op__invert_out[0:0] - attribute \src "libresoc.v:175226.3-175267.6" - wire $1\logical_op__is_32bit$next[0:0]$10360 - attribute \src "libresoc.v:174490.7-174490.34" + attribute \src "libresoc.v:176534.3-176575.6" + wire $1\logical_op__is_32bit$next[0:0]$10344 + attribute \src "libresoc.v:175798.7-175798.34" wire $1\logical_op__is_32bit[0:0] - attribute \src "libresoc.v:175226.3-175267.6" - wire $1\logical_op__is_signed$next[0:0]$10361 - attribute \src "libresoc.v:174499.7-174499.35" + attribute \src "libresoc.v:176534.3-176575.6" + wire $1\logical_op__is_signed$next[0:0]$10345 + attribute \src "libresoc.v:175807.7-175807.35" wire $1\logical_op__is_signed[0:0] - attribute \src "libresoc.v:175226.3-175267.6" - wire $1\logical_op__oe__oe$next[0:0]$10362 - attribute \src "libresoc.v:174508.7-174508.32" + attribute \src "libresoc.v:176534.3-176575.6" + wire $1\logical_op__oe__oe$next[0:0]$10346 + attribute \src "libresoc.v:175816.7-175816.32" wire $1\logical_op__oe__oe[0:0] - attribute \src "libresoc.v:175226.3-175267.6" - wire $1\logical_op__oe__ok$next[0:0]$10363 - attribute \src "libresoc.v:174517.7-174517.32" + attribute \src "libresoc.v:176534.3-176575.6" + wire $1\logical_op__oe__ok$next[0:0]$10347 + attribute \src "libresoc.v:175825.7-175825.32" wire $1\logical_op__oe__ok[0:0] - attribute \src "libresoc.v:175226.3-175267.6" - wire $1\logical_op__output_carry$next[0:0]$10364 - attribute \src "libresoc.v:174526.7-174526.38" + attribute \src "libresoc.v:176534.3-176575.6" + wire $1\logical_op__output_carry$next[0:0]$10348 + attribute \src "libresoc.v:175834.7-175834.38" wire $1\logical_op__output_carry[0:0] - attribute \src "libresoc.v:175226.3-175267.6" - wire $1\logical_op__rc__ok$next[0:0]$10365 - attribute \src "libresoc.v:174535.7-174535.32" + attribute \src "libresoc.v:176534.3-176575.6" + wire $1\logical_op__rc__ok$next[0:0]$10349 + attribute \src "libresoc.v:175843.7-175843.32" wire $1\logical_op__rc__ok[0:0] - attribute \src "libresoc.v:175226.3-175267.6" - wire $1\logical_op__rc__rc$next[0:0]$10366 - attribute \src "libresoc.v:174544.7-174544.32" + attribute \src "libresoc.v:176534.3-176575.6" + wire $1\logical_op__rc__rc$next[0:0]$10350 + attribute \src "libresoc.v:175852.7-175852.32" wire $1\logical_op__rc__rc[0:0] - attribute \src "libresoc.v:175226.3-175267.6" - wire $1\logical_op__write_cr0$next[0:0]$10367 - attribute \src "libresoc.v:174553.7-174553.35" + attribute \src "libresoc.v:176534.3-176575.6" + wire $1\logical_op__write_cr0$next[0:0]$10351 + attribute \src "libresoc.v:175861.7-175861.35" wire $1\logical_op__write_cr0[0:0] - attribute \src "libresoc.v:175226.3-175267.6" - wire $1\logical_op__zero_a$next[0:0]$10368 - attribute \src "libresoc.v:174562.7-174562.32" + attribute \src "libresoc.v:176534.3-176575.6" + wire $1\logical_op__zero_a$next[0:0]$10352 + attribute \src "libresoc.v:175870.7-175870.32" wire $1\logical_op__zero_a[0:0] - attribute \src "libresoc.v:175213.3-175225.6" - wire width 2 $1\muxid$next[1:0]$10331 - attribute \src "libresoc.v:174571.13-174571.25" + attribute \src "libresoc.v:176521.3-176533.6" + wire width 2 $1\muxid$next[1:0]$10315 + attribute \src "libresoc.v:175879.13-175879.25" wire width 2 $1\muxid[1:0] - attribute \src "libresoc.v:175182.3-175194.6" - wire width 2 $1\operation$next[1:0]$10324 - attribute \src "libresoc.v:174586.13-174586.29" + attribute \src "libresoc.v:176490.3-176502.6" + wire width 2 $1\operation$next[1:0]$10308 + attribute \src "libresoc.v:175894.13-175894.29" wire width 2 $1\operation[1:0] - attribute \src "libresoc.v:175195.3-175212.6" - wire $1\r_busy$next[0:0]$10327 - attribute \src "libresoc.v:174600.7-174600.20" + attribute \src "libresoc.v:176503.3-176520.6" + wire $1\r_busy$next[0:0]$10311 + attribute \src "libresoc.v:175908.7-175908.20" wire $1\r_busy[0:0] - attribute \src "libresoc.v:175268.3-175280.6" - wire width 64 $1\ra$next[63:0]$10377 - attribute \src "libresoc.v:174605.14-174605.39" + attribute \src "libresoc.v:176576.3-176588.6" + wire width 64 $1\ra$next[63:0]$10361 + attribute \src "libresoc.v:175913.14-175913.39" wire width 64 $1\ra[63:0] - attribute \src "libresoc.v:175281.3-175293.6" - wire width 64 $1\rb$next[63:0]$10380 - attribute \src "libresoc.v:174616.14-174616.39" + attribute \src "libresoc.v:176589.3-176601.6" + wire width 64 $1\rb$next[63:0]$10364 + attribute \src "libresoc.v:175924.14-175924.39" wire width 64 $1\rb[63:0] - attribute \src "libresoc.v:175294.3-175306.6" - wire $1\xer_so$next[0:0]$10383 - attribute \src "libresoc.v:174915.7-174915.20" + attribute \src "libresoc.v:176602.3-176614.6" + wire $1\xer_so$next[0:0]$10367 + attribute \src "libresoc.v:176223.7-176223.20" wire $1\xer_so[0:0] - attribute \src "libresoc.v:175226.3-175267.6" - wire width 64 $2\logical_op__imm_data__data$next[63:0]$10369 - attribute \src "libresoc.v:175226.3-175267.6" - wire $2\logical_op__imm_data__ok$next[0:0]$10370 - attribute \src "libresoc.v:175226.3-175267.6" - wire $2\logical_op__oe__oe$next[0:0]$10371 - attribute \src "libresoc.v:175226.3-175267.6" - wire $2\logical_op__oe__ok$next[0:0]$10372 - attribute \src "libresoc.v:175226.3-175267.6" - wire $2\logical_op__rc__ok$next[0:0]$10373 - attribute \src "libresoc.v:175226.3-175267.6" - wire $2\logical_op__rc__rc$next[0:0]$10374 - attribute \src "libresoc.v:175195.3-175212.6" - wire $2\r_busy$next[0:0]$10328 - attribute \src "libresoc.v:174922.18-174922.118" - wire $and$libresoc.v:174922$10269_Y + attribute \src "libresoc.v:176534.3-176575.6" + wire width 64 $2\logical_op__imm_data__data$next[63:0]$10353 + attribute \src "libresoc.v:176534.3-176575.6" + wire $2\logical_op__imm_data__ok$next[0:0]$10354 + attribute \src "libresoc.v:176534.3-176575.6" + wire $2\logical_op__oe__oe$next[0:0]$10355 + attribute \src "libresoc.v:176534.3-176575.6" + wire $2\logical_op__oe__ok$next[0:0]$10356 + attribute \src "libresoc.v:176534.3-176575.6" + wire $2\logical_op__rc__ok$next[0:0]$10357 + attribute \src "libresoc.v:176534.3-176575.6" + wire $2\logical_op__rc__rc$next[0:0]$10358 + attribute \src "libresoc.v:176503.3-176520.6" + wire $2\r_busy$next[0:0]$10312 + attribute \src "libresoc.v:176230.18-176230.118" + wire $and$libresoc.v:176230$10253_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" wire \$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 58 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" wire output 30 \div_by_zero @@ -353699,7 +325069,7 @@ module \pipe_start wire width 64 \divisor_radicand$98 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" wire width 64 \divisor_radicand$next - attribute \src "libresoc.v:173793.7-173793.15" + attribute \src "libresoc.v:175101.7-175101.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 \input_logical_op__data_len @@ -354752,7 +326122,7 @@ module \pipe_start attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire \xer_so$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:629" - cell $and $and$libresoc.v:174922$10269 + cell $and $and$libresoc.v:176230$10253 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -354760,10 +326130,10 @@ module \pipe_start parameter \Y_WIDTH 1 connect \A \p_valid_i$65 connect \B \p_ready_o - connect \Y $and$libresoc.v:174922$10269_Y + connect \Y $and$libresoc.v:176230$10253_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:174985.14-175030.4" + attribute \src "libresoc.v:176293.14-176338.4" cell \input$78 \input connect \logical_op__data_len \input_logical_op__data_len connect \logical_op__data_len$18 \input_logical_op__data_len$40 @@ -354811,19 +326181,19 @@ module \pipe_start connect \xer_so$22 \input_xer_so$44 end attribute \module_not_derived 1 - attribute \src "libresoc.v:175031.10-175034.4" + attribute \src "libresoc.v:176339.10-176342.4" cell \n$77 \n connect \n_ready_i \n_ready_i connect \n_valid_o \n_valid_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:175035.10-175038.4" + attribute \src "libresoc.v:176343.10-176346.4" cell \p$76 \p connect \p_ready_o \p_ready_o connect \p_valid_i \p_valid_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:175039.15-175090.4" + attribute \src "libresoc.v:176347.15-176398.4" cell \setup_stage \setup_stage connect \div_by_zero \setup_stage_div_by_zero connect \dive_abs_ov32 \setup_stage_dive_abs_ov32 @@ -354876,487 +326246,487 @@ module \pipe_start connect \xer_so \setup_stage_xer_so connect \xer_so$20 \setup_stage_xer_so$64 end - attribute \src "libresoc.v:173793.7-173793.20" - process $proc$libresoc.v:173793$10384 + attribute \src "libresoc.v:175101.7-175101.20" + process $proc$libresoc.v:175101$10368 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:173802.7-173802.25" - process $proc$libresoc.v:173802$10385 + attribute \src "libresoc.v:175110.7-175110.25" + process $proc$libresoc.v:175110$10369 assign { } { } assign $1\div_by_zero[0:0] 1'0 sync always sync init update \div_by_zero $1\div_by_zero[0:0] end - attribute \src "libresoc.v:173809.7-173809.27" - process $proc$libresoc.v:173809$10386 + attribute \src "libresoc.v:175117.7-175117.27" + process $proc$libresoc.v:175117$10370 assign { } { } assign $1\dive_abs_ov32[0:0] 1'0 sync always sync init update \dive_abs_ov32 $1\dive_abs_ov32[0:0] end - attribute \src "libresoc.v:173816.7-173816.27" - process $proc$libresoc.v:173816$10387 + attribute \src "libresoc.v:175124.7-175124.27" + process $proc$libresoc.v:175124$10371 assign { } { } assign $1\dive_abs_ov64[0:0] 1'0 sync always sync init update \dive_abs_ov64 $1\dive_abs_ov64[0:0] end - attribute \src "libresoc.v:173823.15-173823.63" - process $proc$libresoc.v:173823$10388 + attribute \src "libresoc.v:175131.15-175131.63" + process $proc$libresoc.v:175131$10372 assign { } { } assign $1\dividend[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dividend $1\dividend[127:0] end - attribute \src "libresoc.v:173830.7-173830.26" - process $proc$libresoc.v:173830$10389 + attribute \src "libresoc.v:175138.7-175138.26" + process $proc$libresoc.v:175138$10373 assign { } { } assign $1\dividend_neg[0:0] 1'0 sync always sync init update \dividend_neg $1\dividend_neg[0:0] end - attribute \src "libresoc.v:173837.7-173837.25" - process $proc$libresoc.v:173837$10390 + attribute \src "libresoc.v:175145.7-175145.25" + process $proc$libresoc.v:175145$10374 assign { } { } assign $1\divisor_neg[0:0] 1'0 sync always sync init update \divisor_neg $1\divisor_neg[0:0] end - attribute \src "libresoc.v:173844.14-173844.53" - process $proc$libresoc.v:173844$10391 + attribute \src "libresoc.v:175152.14-175152.53" + process $proc$libresoc.v:175152$10375 assign { } { } assign $1\divisor_radicand[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \divisor_radicand $1\divisor_radicand[63:0] end - attribute \src "libresoc.v:174127.13-174127.40" - process $proc$libresoc.v:174127$10392 + attribute \src "libresoc.v:175435.13-175435.40" + process $proc$libresoc.v:175435$10376 assign { } { } assign $1\logical_op__data_len[3:0] 4'0000 sync always sync init update \logical_op__data_len $1\logical_op__data_len[3:0] end - attribute \src "libresoc.v:174151.14-174151.44" - process $proc$libresoc.v:174151$10393 + attribute \src "libresoc.v:175459.14-175459.44" + process $proc$libresoc.v:175459$10377 assign { } { } assign $1\logical_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \logical_op__fn_unit $1\logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:174190.14-174190.63" - process $proc$libresoc.v:174190$10394 + attribute \src "libresoc.v:175498.14-175498.63" + process $proc$libresoc.v:175498$10378 assign { } { } assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:174199.7-174199.38" - process $proc$libresoc.v:174199$10395 + attribute \src "libresoc.v:175507.7-175507.38" + process $proc$libresoc.v:175507$10379 assign { } { } assign $1\logical_op__imm_data__ok[0:0] 1'0 sync always sync init update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:174212.13-174212.43" - process $proc$libresoc.v:174212$10396 + attribute \src "libresoc.v:175520.13-175520.43" + process $proc$libresoc.v:175520$10380 assign { } { } assign $1\logical_op__input_carry[1:0] 2'00 sync always sync init update \logical_op__input_carry $1\logical_op__input_carry[1:0] end - attribute \src "libresoc.v:174229.14-174229.38" - process $proc$libresoc.v:174229$10397 + attribute \src "libresoc.v:175537.14-175537.38" + process $proc$libresoc.v:175537$10381 assign { } { } assign $1\logical_op__insn[31:0] 0 sync always sync init update \logical_op__insn $1\logical_op__insn[31:0] end - attribute \src "libresoc.v:174313.13-174313.42" - process $proc$libresoc.v:174313$10398 + attribute \src "libresoc.v:175621.13-175621.42" + process $proc$libresoc.v:175621$10382 assign { } { } assign $1\logical_op__insn_type[6:0] 7'0000000 sync always sync init update \logical_op__insn_type $1\logical_op__insn_type[6:0] end - attribute \src "libresoc.v:174472.7-174472.35" - process $proc$libresoc.v:174472$10399 + attribute \src "libresoc.v:175780.7-175780.35" + process $proc$libresoc.v:175780$10383 assign { } { } assign $1\logical_op__invert_in[0:0] 1'0 sync always sync init update \logical_op__invert_in $1\logical_op__invert_in[0:0] end - attribute \src "libresoc.v:174481.7-174481.36" - process $proc$libresoc.v:174481$10400 + attribute \src "libresoc.v:175789.7-175789.36" + process $proc$libresoc.v:175789$10384 assign { } { } assign $1\logical_op__invert_out[0:0] 1'0 sync always sync init update \logical_op__invert_out $1\logical_op__invert_out[0:0] end - attribute \src "libresoc.v:174490.7-174490.34" - process $proc$libresoc.v:174490$10401 + attribute \src "libresoc.v:175798.7-175798.34" + process $proc$libresoc.v:175798$10385 assign { } { } assign $1\logical_op__is_32bit[0:0] 1'0 sync always sync init update \logical_op__is_32bit $1\logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:174499.7-174499.35" - process $proc$libresoc.v:174499$10402 + attribute \src "libresoc.v:175807.7-175807.35" + process $proc$libresoc.v:175807$10386 assign { } { } assign $1\logical_op__is_signed[0:0] 1'0 sync always sync init update \logical_op__is_signed $1\logical_op__is_signed[0:0] end - attribute \src "libresoc.v:174508.7-174508.32" - process $proc$libresoc.v:174508$10403 + attribute \src "libresoc.v:175816.7-175816.32" + process $proc$libresoc.v:175816$10387 assign { } { } assign $1\logical_op__oe__oe[0:0] 1'0 sync always sync init update \logical_op__oe__oe $1\logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:174517.7-174517.32" - process $proc$libresoc.v:174517$10404 + attribute \src "libresoc.v:175825.7-175825.32" + process $proc$libresoc.v:175825$10388 assign { } { } assign $1\logical_op__oe__ok[0:0] 1'0 sync always sync init update \logical_op__oe__ok $1\logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:174526.7-174526.38" - process $proc$libresoc.v:174526$10405 + attribute \src "libresoc.v:175834.7-175834.38" + process $proc$libresoc.v:175834$10389 assign { } { } assign $1\logical_op__output_carry[0:0] 1'0 sync always sync init update \logical_op__output_carry $1\logical_op__output_carry[0:0] end - attribute \src "libresoc.v:174535.7-174535.32" - process $proc$libresoc.v:174535$10406 + attribute \src "libresoc.v:175843.7-175843.32" + process $proc$libresoc.v:175843$10390 assign { } { } assign $1\logical_op__rc__ok[0:0] 1'0 sync always sync init update \logical_op__rc__ok $1\logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:174544.7-174544.32" - process $proc$libresoc.v:174544$10407 + attribute \src "libresoc.v:175852.7-175852.32" + process $proc$libresoc.v:175852$10391 assign { } { } assign $1\logical_op__rc__rc[0:0] 1'0 sync always sync init update \logical_op__rc__rc $1\logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:174553.7-174553.35" - process $proc$libresoc.v:174553$10408 + attribute \src "libresoc.v:175861.7-175861.35" + process $proc$libresoc.v:175861$10392 assign { } { } assign $1\logical_op__write_cr0[0:0] 1'0 sync always sync init update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:174562.7-174562.32" - process $proc$libresoc.v:174562$10409 + attribute \src "libresoc.v:175870.7-175870.32" + process $proc$libresoc.v:175870$10393 assign { } { } assign $1\logical_op__zero_a[0:0] 1'0 sync always sync init update \logical_op__zero_a $1\logical_op__zero_a[0:0] end - attribute \src "libresoc.v:174571.13-174571.25" - process $proc$libresoc.v:174571$10410 + attribute \src "libresoc.v:175879.13-175879.25" + process $proc$libresoc.v:175879$10394 assign { } { } assign $1\muxid[1:0] 2'00 sync always sync init update \muxid $1\muxid[1:0] end - attribute \src "libresoc.v:174586.13-174586.29" - process $proc$libresoc.v:174586$10411 + attribute \src "libresoc.v:175894.13-175894.29" + process $proc$libresoc.v:175894$10395 assign { } { } assign $1\operation[1:0] 2'00 sync always sync init update \operation $1\operation[1:0] end - attribute \src "libresoc.v:174600.7-174600.20" - process $proc$libresoc.v:174600$10412 + attribute \src "libresoc.v:175908.7-175908.20" + process $proc$libresoc.v:175908$10396 assign { } { } assign $1\r_busy[0:0] 1'0 sync always sync init update \r_busy $1\r_busy[0:0] end - attribute \src "libresoc.v:174605.14-174605.39" - process $proc$libresoc.v:174605$10413 + attribute \src "libresoc.v:175913.14-175913.39" + process $proc$libresoc.v:175913$10397 assign { } { } assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \ra $1\ra[63:0] end - attribute \src "libresoc.v:174616.14-174616.39" - process $proc$libresoc.v:174616$10414 + attribute \src "libresoc.v:175924.14-175924.39" + process $proc$libresoc.v:175924$10398 assign { } { } assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \rb $1\rb[63:0] end - attribute \src "libresoc.v:174915.7-174915.20" - process $proc$libresoc.v:174915$10415 + attribute \src "libresoc.v:176223.7-176223.20" + process $proc$libresoc.v:176223$10399 assign { } { } assign $1\xer_so[0:0] 1'0 sync always sync init update \xer_so $1\xer_so[0:0] end - attribute \src "libresoc.v:174923.3-174924.35" - process $proc$libresoc.v:174923$10270 + attribute \src "libresoc.v:176231.3-176232.35" + process $proc$libresoc.v:176231$10254 assign { } { } assign $0\operation[1:0] \operation$next sync posedge \coresync_clk update \operation $0\operation[1:0] end - attribute \src "libresoc.v:174925.3-174926.49" - process $proc$libresoc.v:174925$10271 + attribute \src "libresoc.v:176233.3-176234.49" + process $proc$libresoc.v:176233$10255 assign { } { } assign $0\divisor_radicand[63:0] \divisor_radicand$next sync posedge \coresync_clk update \divisor_radicand $0\divisor_radicand[63:0] end - attribute \src "libresoc.v:174927.3-174928.33" - process $proc$libresoc.v:174927$10272 + attribute \src "libresoc.v:176235.3-176236.33" + process $proc$libresoc.v:176235$10256 assign { } { } assign $0\dividend[127:0] \dividend$next sync posedge \coresync_clk update \dividend $0\dividend[127:0] end - attribute \src "libresoc.v:174929.3-174930.39" - process $proc$libresoc.v:174929$10273 + attribute \src "libresoc.v:176237.3-176238.39" + process $proc$libresoc.v:176237$10257 assign { } { } assign $0\div_by_zero[0:0] \div_by_zero$next sync posedge \coresync_clk update \div_by_zero $0\div_by_zero[0:0] end - attribute \src "libresoc.v:174931.3-174932.43" - process $proc$libresoc.v:174931$10274 + attribute \src "libresoc.v:176239.3-176240.43" + process $proc$libresoc.v:176239$10258 assign { } { } assign $0\dive_abs_ov64[0:0] \dive_abs_ov64$next sync posedge \coresync_clk update \dive_abs_ov64 $0\dive_abs_ov64[0:0] end - attribute \src "libresoc.v:174933.3-174934.43" - process $proc$libresoc.v:174933$10275 + attribute \src "libresoc.v:176241.3-176242.43" + process $proc$libresoc.v:176241$10259 assign { } { } assign $0\dive_abs_ov32[0:0] \dive_abs_ov32$next sync posedge \coresync_clk update \dive_abs_ov32 $0\dive_abs_ov32[0:0] end - attribute \src "libresoc.v:174935.3-174936.41" - process $proc$libresoc.v:174935$10276 + attribute \src "libresoc.v:176243.3-176244.41" + process $proc$libresoc.v:176243$10260 assign { } { } assign $0\dividend_neg[0:0] \dividend_neg$next sync posedge \coresync_clk update \dividend_neg $0\dividend_neg[0:0] end - attribute \src "libresoc.v:174937.3-174938.39" - process $proc$libresoc.v:174937$10277 + attribute \src "libresoc.v:176245.3-176246.39" + process $proc$libresoc.v:176245$10261 assign { } { } assign $0\divisor_neg[0:0] \divisor_neg$next sync posedge \coresync_clk update \divisor_neg $0\divisor_neg[0:0] end - attribute \src "libresoc.v:174939.3-174940.29" - process $proc$libresoc.v:174939$10278 + attribute \src "libresoc.v:176247.3-176248.29" + process $proc$libresoc.v:176247$10262 assign { } { } assign $0\xer_so[0:0] \xer_so$next sync posedge \coresync_clk update \xer_so $0\xer_so[0:0] end - attribute \src "libresoc.v:174941.3-174942.21" - process $proc$libresoc.v:174941$10279 + attribute \src "libresoc.v:176249.3-176250.21" + process $proc$libresoc.v:176249$10263 assign { } { } assign $0\rb[63:0] \rb$next sync posedge \coresync_clk update \rb $0\rb[63:0] end - attribute \src "libresoc.v:174943.3-174944.21" - process $proc$libresoc.v:174943$10280 + attribute \src "libresoc.v:176251.3-176252.21" + process $proc$libresoc.v:176251$10264 assign { } { } assign $0\ra[63:0] \ra$next sync posedge \coresync_clk update \ra $0\ra[63:0] end - attribute \src "libresoc.v:174945.3-174946.59" - process $proc$libresoc.v:174945$10281 + attribute \src "libresoc.v:176253.3-176254.59" + process $proc$libresoc.v:176253$10265 assign { } { } assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next sync posedge \coresync_clk update \logical_op__insn_type $0\logical_op__insn_type[6:0] end - attribute \src "libresoc.v:174947.3-174948.55" - process $proc$libresoc.v:174947$10282 + attribute \src "libresoc.v:176255.3-176256.55" + process $proc$libresoc.v:176255$10266 assign { } { } assign $0\logical_op__fn_unit[13:0] \logical_op__fn_unit$next sync posedge \coresync_clk update \logical_op__fn_unit $0\logical_op__fn_unit[13:0] end - attribute \src "libresoc.v:174949.3-174950.69" - process $proc$libresoc.v:174949$10283 + attribute \src "libresoc.v:176257.3-176258.69" + process $proc$libresoc.v:176257$10267 assign { } { } assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next sync posedge \coresync_clk update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0] end - attribute \src "libresoc.v:174951.3-174952.65" - process $proc$libresoc.v:174951$10284 + attribute \src "libresoc.v:176259.3-176260.65" + process $proc$libresoc.v:176259$10268 assign { } { } assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next sync posedge \coresync_clk update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:174953.3-174954.53" - process $proc$libresoc.v:174953$10285 + attribute \src "libresoc.v:176261.3-176262.53" + process $proc$libresoc.v:176261$10269 assign { } { } assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next sync posedge \coresync_clk update \logical_op__rc__rc $0\logical_op__rc__rc[0:0] end - attribute \src "libresoc.v:174955.3-174956.53" - process $proc$libresoc.v:174955$10286 + attribute \src "libresoc.v:176263.3-176264.53" + process $proc$libresoc.v:176263$10270 assign { } { } assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next sync posedge \coresync_clk update \logical_op__rc__ok $0\logical_op__rc__ok[0:0] end - attribute \src "libresoc.v:174957.3-174958.53" - process $proc$libresoc.v:174957$10287 + attribute \src "libresoc.v:176265.3-176266.53" + process $proc$libresoc.v:176265$10271 assign { } { } assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next sync posedge \coresync_clk update \logical_op__oe__oe $0\logical_op__oe__oe[0:0] end - attribute \src "libresoc.v:174959.3-174960.53" - process $proc$libresoc.v:174959$10288 + attribute \src "libresoc.v:176267.3-176268.53" + process $proc$libresoc.v:176267$10272 assign { } { } assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next sync posedge \coresync_clk update \logical_op__oe__ok $0\logical_op__oe__ok[0:0] end - attribute \src "libresoc.v:174961.3-174962.59" - process $proc$libresoc.v:174961$10289 + attribute \src "libresoc.v:176269.3-176270.59" + process $proc$libresoc.v:176269$10273 assign { } { } assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next sync posedge \coresync_clk update \logical_op__invert_in $0\logical_op__invert_in[0:0] end - attribute \src "libresoc.v:174963.3-174964.53" - process $proc$libresoc.v:174963$10290 + attribute \src "libresoc.v:176271.3-176272.53" + process $proc$libresoc.v:176271$10274 assign { } { } assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next sync posedge \coresync_clk update \logical_op__zero_a $0\logical_op__zero_a[0:0] end - attribute \src "libresoc.v:174965.3-174966.63" - process $proc$libresoc.v:174965$10291 + attribute \src "libresoc.v:176273.3-176274.63" + process $proc$libresoc.v:176273$10275 assign { } { } assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next sync posedge \coresync_clk update \logical_op__input_carry $0\logical_op__input_carry[1:0] end - attribute \src "libresoc.v:174967.3-174968.61" - process $proc$libresoc.v:174967$10292 + attribute \src "libresoc.v:176275.3-176276.61" + process $proc$libresoc.v:176275$10276 assign { } { } assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next sync posedge \coresync_clk update \logical_op__invert_out $0\logical_op__invert_out[0:0] end - attribute \src "libresoc.v:174969.3-174970.59" - process $proc$libresoc.v:174969$10293 + attribute \src "libresoc.v:176277.3-176278.59" + process $proc$libresoc.v:176277$10277 assign { } { } assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next sync posedge \coresync_clk update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0] end - attribute \src "libresoc.v:174971.3-174972.65" - process $proc$libresoc.v:174971$10294 + attribute \src "libresoc.v:176279.3-176280.65" + process $proc$libresoc.v:176279$10278 assign { } { } assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next sync posedge \coresync_clk update \logical_op__output_carry $0\logical_op__output_carry[0:0] end - attribute \src "libresoc.v:174973.3-174974.57" - process $proc$libresoc.v:174973$10295 + attribute \src "libresoc.v:176281.3-176282.57" + process $proc$libresoc.v:176281$10279 assign { } { } assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next sync posedge \coresync_clk update \logical_op__is_32bit $0\logical_op__is_32bit[0:0] end - attribute \src "libresoc.v:174975.3-174976.59" - process $proc$libresoc.v:174975$10296 + attribute \src "libresoc.v:176283.3-176284.59" + process $proc$libresoc.v:176283$10280 assign { } { } assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next sync posedge \coresync_clk update \logical_op__is_signed $0\logical_op__is_signed[0:0] end - attribute \src "libresoc.v:174977.3-174978.57" - process $proc$libresoc.v:174977$10297 + attribute \src "libresoc.v:176285.3-176286.57" + process $proc$libresoc.v:176285$10281 assign { } { } assign $0\logical_op__data_len[3:0] \logical_op__data_len$next sync posedge \coresync_clk update \logical_op__data_len $0\logical_op__data_len[3:0] end - attribute \src "libresoc.v:174979.3-174980.49" - process $proc$libresoc.v:174979$10298 + attribute \src "libresoc.v:176287.3-176288.49" + process $proc$libresoc.v:176287$10282 assign { } { } assign $0\logical_op__insn[31:0] \logical_op__insn$next sync posedge \coresync_clk update \logical_op__insn $0\logical_op__insn[31:0] end - attribute \src "libresoc.v:174981.3-174982.27" - process $proc$libresoc.v:174981$10299 + attribute \src "libresoc.v:176289.3-176290.27" + process $proc$libresoc.v:176289$10283 assign { } { } assign $0\muxid[1:0] \muxid$next sync posedge \coresync_clk update \muxid $0\muxid[1:0] end - attribute \src "libresoc.v:174983.3-174984.29" - process $proc$libresoc.v:174983$10300 + attribute \src "libresoc.v:176291.3-176292.29" + process $proc$libresoc.v:176291$10284 assign { } { } assign $0\r_busy[0:0] \r_busy$next sync posedge \coresync_clk update \r_busy $0\r_busy[0:0] end - attribute \src "libresoc.v:175091.3-175103.6" - process $proc$libresoc.v:175091$10301 + attribute \src "libresoc.v:176399.3-176411.6" + process $proc$libresoc.v:176399$10285 assign { } { } assign { } { } - assign $0\divisor_neg$next[0:0]$10302 $1\divisor_neg$next[0:0]$10303 - attribute \src "libresoc.v:175092.5-175092.29" + assign $0\divisor_neg$next[0:0]$10286 $1\divisor_neg$next[0:0]$10287 + attribute \src "libresoc.v:176400.5-176400.29" switch \initial - attribute \src "libresoc.v:175092.9-175092.17" + attribute \src "libresoc.v:176400.9-176400.17" case 1'1 case end @@ -355365,25 +326735,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\divisor_neg$next[0:0]$10303 \divisor_neg$92 + assign $1\divisor_neg$next[0:0]$10287 \divisor_neg$92 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\divisor_neg$next[0:0]$10303 \divisor_neg$92 + assign $1\divisor_neg$next[0:0]$10287 \divisor_neg$92 case - assign $1\divisor_neg$next[0:0]$10303 \divisor_neg + assign $1\divisor_neg$next[0:0]$10287 \divisor_neg end sync always - update \divisor_neg$next $0\divisor_neg$next[0:0]$10302 + update \divisor_neg$next $0\divisor_neg$next[0:0]$10286 end - attribute \src "libresoc.v:175104.3-175116.6" - process $proc$libresoc.v:175104$10304 + attribute \src "libresoc.v:176412.3-176424.6" + process $proc$libresoc.v:176412$10288 assign { } { } assign { } { } - assign $0\dividend_neg$next[0:0]$10305 $1\dividend_neg$next[0:0]$10306 - attribute \src "libresoc.v:175105.5-175105.29" + assign $0\dividend_neg$next[0:0]$10289 $1\dividend_neg$next[0:0]$10290 + attribute \src "libresoc.v:176413.5-176413.29" switch \initial - attribute \src "libresoc.v:175105.9-175105.17" + attribute \src "libresoc.v:176413.9-176413.17" case 1'1 case end @@ -355392,25 +326762,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\dividend_neg$next[0:0]$10306 \dividend_neg$93 + assign $1\dividend_neg$next[0:0]$10290 \dividend_neg$93 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\dividend_neg$next[0:0]$10306 \dividend_neg$93 + assign $1\dividend_neg$next[0:0]$10290 \dividend_neg$93 case - assign $1\dividend_neg$next[0:0]$10306 \dividend_neg + assign $1\dividend_neg$next[0:0]$10290 \dividend_neg end sync always - update \dividend_neg$next $0\dividend_neg$next[0:0]$10305 + update \dividend_neg$next $0\dividend_neg$next[0:0]$10289 end - attribute \src "libresoc.v:175117.3-175129.6" - process $proc$libresoc.v:175117$10307 + attribute \src "libresoc.v:176425.3-176437.6" + process $proc$libresoc.v:176425$10291 assign { } { } assign { } { } - assign $0\dive_abs_ov32$next[0:0]$10308 $1\dive_abs_ov32$next[0:0]$10309 - attribute \src "libresoc.v:175118.5-175118.29" + assign $0\dive_abs_ov32$next[0:0]$10292 $1\dive_abs_ov32$next[0:0]$10293 + attribute \src "libresoc.v:176426.5-176426.29" switch \initial - attribute \src "libresoc.v:175118.9-175118.17" + attribute \src "libresoc.v:176426.9-176426.17" case 1'1 case end @@ -355419,25 +326789,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\dive_abs_ov32$next[0:0]$10309 \dive_abs_ov32$94 + assign $1\dive_abs_ov32$next[0:0]$10293 \dive_abs_ov32$94 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\dive_abs_ov32$next[0:0]$10309 \dive_abs_ov32$94 + assign $1\dive_abs_ov32$next[0:0]$10293 \dive_abs_ov32$94 case - assign $1\dive_abs_ov32$next[0:0]$10309 \dive_abs_ov32 + assign $1\dive_abs_ov32$next[0:0]$10293 \dive_abs_ov32 end sync always - update \dive_abs_ov32$next $0\dive_abs_ov32$next[0:0]$10308 + update \dive_abs_ov32$next $0\dive_abs_ov32$next[0:0]$10292 end - attribute \src "libresoc.v:175130.3-175142.6" - process $proc$libresoc.v:175130$10310 + attribute \src "libresoc.v:176438.3-176450.6" + process $proc$libresoc.v:176438$10294 assign { } { } assign { } { } - assign $0\dive_abs_ov64$next[0:0]$10311 $1\dive_abs_ov64$next[0:0]$10312 - attribute \src "libresoc.v:175131.5-175131.29" + assign $0\dive_abs_ov64$next[0:0]$10295 $1\dive_abs_ov64$next[0:0]$10296 + attribute \src "libresoc.v:176439.5-176439.29" switch \initial - attribute \src "libresoc.v:175131.9-175131.17" + attribute \src "libresoc.v:176439.9-176439.17" case 1'1 case end @@ -355446,25 +326816,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\dive_abs_ov64$next[0:0]$10312 \dive_abs_ov64$95 + assign $1\dive_abs_ov64$next[0:0]$10296 \dive_abs_ov64$95 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\dive_abs_ov64$next[0:0]$10312 \dive_abs_ov64$95 + assign $1\dive_abs_ov64$next[0:0]$10296 \dive_abs_ov64$95 case - assign $1\dive_abs_ov64$next[0:0]$10312 \dive_abs_ov64 + assign $1\dive_abs_ov64$next[0:0]$10296 \dive_abs_ov64 end sync always - update \dive_abs_ov64$next $0\dive_abs_ov64$next[0:0]$10311 + update \dive_abs_ov64$next $0\dive_abs_ov64$next[0:0]$10295 end - attribute \src "libresoc.v:175143.3-175155.6" - process $proc$libresoc.v:175143$10313 + attribute \src "libresoc.v:176451.3-176463.6" + process $proc$libresoc.v:176451$10297 assign { } { } assign { } { } - assign $0\div_by_zero$next[0:0]$10314 $1\div_by_zero$next[0:0]$10315 - attribute \src "libresoc.v:175144.5-175144.29" + assign $0\div_by_zero$next[0:0]$10298 $1\div_by_zero$next[0:0]$10299 + attribute \src "libresoc.v:176452.5-176452.29" switch \initial - attribute \src "libresoc.v:175144.9-175144.17" + attribute \src "libresoc.v:176452.9-176452.17" case 1'1 case end @@ -355473,25 +326843,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\div_by_zero$next[0:0]$10315 \div_by_zero$96 + assign $1\div_by_zero$next[0:0]$10299 \div_by_zero$96 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\div_by_zero$next[0:0]$10315 \div_by_zero$96 + assign $1\div_by_zero$next[0:0]$10299 \div_by_zero$96 case - assign $1\div_by_zero$next[0:0]$10315 \div_by_zero + assign $1\div_by_zero$next[0:0]$10299 \div_by_zero end sync always - update \div_by_zero$next $0\div_by_zero$next[0:0]$10314 + update \div_by_zero$next $0\div_by_zero$next[0:0]$10298 end - attribute \src "libresoc.v:175156.3-175168.6" - process $proc$libresoc.v:175156$10316 + attribute \src "libresoc.v:176464.3-176476.6" + process $proc$libresoc.v:176464$10300 assign { } { } assign { } { } - assign $0\dividend$next[127:0]$10317 $1\dividend$next[127:0]$10318 - attribute \src "libresoc.v:175157.5-175157.29" + assign $0\dividend$next[127:0]$10301 $1\dividend$next[127:0]$10302 + attribute \src "libresoc.v:176465.5-176465.29" switch \initial - attribute \src "libresoc.v:175157.9-175157.17" + attribute \src "libresoc.v:176465.9-176465.17" case 1'1 case end @@ -355500,25 +326870,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\dividend$next[127:0]$10318 \dividend$97 + assign $1\dividend$next[127:0]$10302 \dividend$97 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\dividend$next[127:0]$10318 \dividend$97 + assign $1\dividend$next[127:0]$10302 \dividend$97 case - assign $1\dividend$next[127:0]$10318 \dividend + assign $1\dividend$next[127:0]$10302 \dividend end sync always - update \dividend$next $0\dividend$next[127:0]$10317 + update \dividend$next $0\dividend$next[127:0]$10301 end - attribute \src "libresoc.v:175169.3-175181.6" - process $proc$libresoc.v:175169$10319 + attribute \src "libresoc.v:176477.3-176489.6" + process $proc$libresoc.v:176477$10303 assign { } { } assign { } { } - assign $0\divisor_radicand$next[63:0]$10320 $1\divisor_radicand$next[63:0]$10321 - attribute \src "libresoc.v:175170.5-175170.29" + assign $0\divisor_radicand$next[63:0]$10304 $1\divisor_radicand$next[63:0]$10305 + attribute \src "libresoc.v:176478.5-176478.29" switch \initial - attribute \src "libresoc.v:175170.9-175170.17" + attribute \src "libresoc.v:176478.9-176478.17" case 1'1 case end @@ -355527,25 +326897,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\divisor_radicand$next[63:0]$10321 \divisor_radicand$98 + assign $1\divisor_radicand$next[63:0]$10305 \divisor_radicand$98 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\divisor_radicand$next[63:0]$10321 \divisor_radicand$98 + assign $1\divisor_radicand$next[63:0]$10305 \divisor_radicand$98 case - assign $1\divisor_radicand$next[63:0]$10321 \divisor_radicand + assign $1\divisor_radicand$next[63:0]$10305 \divisor_radicand end sync always - update \divisor_radicand$next $0\divisor_radicand$next[63:0]$10320 + update \divisor_radicand$next $0\divisor_radicand$next[63:0]$10304 end - attribute \src "libresoc.v:175182.3-175194.6" - process $proc$libresoc.v:175182$10322 + attribute \src "libresoc.v:176490.3-176502.6" + process $proc$libresoc.v:176490$10306 assign { } { } assign { } { } - assign $0\operation$next[1:0]$10323 $1\operation$next[1:0]$10324 - attribute \src "libresoc.v:175183.5-175183.29" + assign $0\operation$next[1:0]$10307 $1\operation$next[1:0]$10308 + attribute \src "libresoc.v:176491.5-176491.29" switch \initial - attribute \src "libresoc.v:175183.9-175183.17" + attribute \src "libresoc.v:176491.9-176491.17" case 1'1 case end @@ -355554,26 +326924,26 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\operation$next[1:0]$10324 \operation$99 + assign $1\operation$next[1:0]$10308 \operation$99 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\operation$next[1:0]$10324 \operation$99 + assign $1\operation$next[1:0]$10308 \operation$99 case - assign $1\operation$next[1:0]$10324 \operation + assign $1\operation$next[1:0]$10308 \operation end sync always - update \operation$next $0\operation$next[1:0]$10323 + update \operation$next $0\operation$next[1:0]$10307 end - attribute \src "libresoc.v:175195.3-175212.6" - process $proc$libresoc.v:175195$10325 + attribute \src "libresoc.v:176503.3-176520.6" + process $proc$libresoc.v:176503$10309 assign { } { } assign { } { } assign { } { } - assign $0\r_busy$next[0:0]$10326 $2\r_busy$next[0:0]$10328 - attribute \src "libresoc.v:175196.5-175196.29" + assign $0\r_busy$next[0:0]$10310 $2\r_busy$next[0:0]$10312 + attribute \src "libresoc.v:176504.5-176504.29" switch \initial - attribute \src "libresoc.v:175196.9-175196.17" + attribute \src "libresoc.v:176504.9-176504.17" case 1'1 case end @@ -355582,34 +326952,34 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\r_busy$next[0:0]$10327 1'1 + assign $1\r_busy$next[0:0]$10311 1'1 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\r_busy$next[0:0]$10327 1'0 + assign $1\r_busy$next[0:0]$10311 1'0 case - assign $1\r_busy$next[0:0]$10327 \r_busy + assign $1\r_busy$next[0:0]$10311 \r_busy end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r_busy$next[0:0]$10328 1'0 + assign $2\r_busy$next[0:0]$10312 1'0 case - assign $2\r_busy$next[0:0]$10328 $1\r_busy$next[0:0]$10327 + assign $2\r_busy$next[0:0]$10312 $1\r_busy$next[0:0]$10311 end sync always - update \r_busy$next $0\r_busy$next[0:0]$10326 + update \r_busy$next $0\r_busy$next[0:0]$10310 end - attribute \src "libresoc.v:175213.3-175225.6" - process $proc$libresoc.v:175213$10329 + attribute \src "libresoc.v:176521.3-176533.6" + process $proc$libresoc.v:176521$10313 assign { } { } assign { } { } - assign $0\muxid$next[1:0]$10330 $1\muxid$next[1:0]$10331 - attribute \src "libresoc.v:175214.5-175214.29" + assign $0\muxid$next[1:0]$10314 $1\muxid$next[1:0]$10315 + attribute \src "libresoc.v:176522.5-176522.29" switch \initial - attribute \src "libresoc.v:175214.9-175214.17" + attribute \src "libresoc.v:176522.9-176522.17" case 1'1 case end @@ -355618,19 +326988,19 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\muxid$next[1:0]$10331 \muxid$68 + assign $1\muxid$next[1:0]$10315 \muxid$68 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\muxid$next[1:0]$10331 \muxid$68 + assign $1\muxid$next[1:0]$10315 \muxid$68 case - assign $1\muxid$next[1:0]$10331 \muxid + assign $1\muxid$next[1:0]$10315 \muxid end sync always - update \muxid$next $0\muxid$next[1:0]$10330 + update \muxid$next $0\muxid$next[1:0]$10314 end - attribute \src "libresoc.v:175226.3-175267.6" - process $proc$libresoc.v:175226$10332 + attribute \src "libresoc.v:176534.3-176575.6" + process $proc$libresoc.v:176534$10316 assign { } { } assign { } { } assign { } { } @@ -355667,33 +327037,33 @@ module \pipe_start assign { } { } assign { } { } assign { } { } - assign $0\logical_op__data_len$next[3:0]$10333 $1\logical_op__data_len$next[3:0]$10351 - assign $0\logical_op__fn_unit$next[13:0]$10334 $1\logical_op__fn_unit$next[13:0]$10352 + assign $0\logical_op__data_len$next[3:0]$10317 $1\logical_op__data_len$next[3:0]$10335 + assign $0\logical_op__fn_unit$next[13:0]$10318 $1\logical_op__fn_unit$next[13:0]$10336 assign { } { } assign { } { } - assign $0\logical_op__input_carry$next[1:0]$10337 $1\logical_op__input_carry$next[1:0]$10355 - assign $0\logical_op__insn$next[31:0]$10338 $1\logical_op__insn$next[31:0]$10356 - assign $0\logical_op__insn_type$next[6:0]$10339 $1\logical_op__insn_type$next[6:0]$10357 - assign $0\logical_op__invert_in$next[0:0]$10340 $1\logical_op__invert_in$next[0:0]$10358 - assign $0\logical_op__invert_out$next[0:0]$10341 $1\logical_op__invert_out$next[0:0]$10359 - assign $0\logical_op__is_32bit$next[0:0]$10342 $1\logical_op__is_32bit$next[0:0]$10360 - assign $0\logical_op__is_signed$next[0:0]$10343 $1\logical_op__is_signed$next[0:0]$10361 + assign $0\logical_op__input_carry$next[1:0]$10321 $1\logical_op__input_carry$next[1:0]$10339 + assign $0\logical_op__insn$next[31:0]$10322 $1\logical_op__insn$next[31:0]$10340 + assign $0\logical_op__insn_type$next[6:0]$10323 $1\logical_op__insn_type$next[6:0]$10341 + assign $0\logical_op__invert_in$next[0:0]$10324 $1\logical_op__invert_in$next[0:0]$10342 + assign $0\logical_op__invert_out$next[0:0]$10325 $1\logical_op__invert_out$next[0:0]$10343 + assign $0\logical_op__is_32bit$next[0:0]$10326 $1\logical_op__is_32bit$next[0:0]$10344 + assign $0\logical_op__is_signed$next[0:0]$10327 $1\logical_op__is_signed$next[0:0]$10345 assign { } { } assign { } { } - assign $0\logical_op__output_carry$next[0:0]$10346 $1\logical_op__output_carry$next[0:0]$10364 + assign $0\logical_op__output_carry$next[0:0]$10330 $1\logical_op__output_carry$next[0:0]$10348 assign { } { } assign { } { } - assign $0\logical_op__write_cr0$next[0:0]$10349 $1\logical_op__write_cr0$next[0:0]$10367 - assign $0\logical_op__zero_a$next[0:0]$10350 $1\logical_op__zero_a$next[0:0]$10368 - assign $0\logical_op__imm_data__data$next[63:0]$10335 $2\logical_op__imm_data__data$next[63:0]$10369 - assign $0\logical_op__imm_data__ok$next[0:0]$10336 $2\logical_op__imm_data__ok$next[0:0]$10370 - assign $0\logical_op__oe__oe$next[0:0]$10344 $2\logical_op__oe__oe$next[0:0]$10371 - assign $0\logical_op__oe__ok$next[0:0]$10345 $2\logical_op__oe__ok$next[0:0]$10372 - assign $0\logical_op__rc__ok$next[0:0]$10347 $2\logical_op__rc__ok$next[0:0]$10373 - assign $0\logical_op__rc__rc$next[0:0]$10348 $2\logical_op__rc__rc$next[0:0]$10374 - attribute \src "libresoc.v:175227.5-175227.29" + assign $0\logical_op__write_cr0$next[0:0]$10333 $1\logical_op__write_cr0$next[0:0]$10351 + assign $0\logical_op__zero_a$next[0:0]$10334 $1\logical_op__zero_a$next[0:0]$10352 + assign $0\logical_op__imm_data__data$next[63:0]$10319 $2\logical_op__imm_data__data$next[63:0]$10353 + assign $0\logical_op__imm_data__ok$next[0:0]$10320 $2\logical_op__imm_data__ok$next[0:0]$10354 + assign $0\logical_op__oe__oe$next[0:0]$10328 $2\logical_op__oe__oe$next[0:0]$10355 + assign $0\logical_op__oe__ok$next[0:0]$10329 $2\logical_op__oe__ok$next[0:0]$10356 + assign $0\logical_op__rc__ok$next[0:0]$10331 $2\logical_op__rc__ok$next[0:0]$10357 + assign $0\logical_op__rc__rc$next[0:0]$10332 $2\logical_op__rc__rc$next[0:0]$10358 + attribute \src "libresoc.v:176535.5-176535.29" switch \initial - attribute \src "libresoc.v:175227.9-175227.17" + attribute \src "libresoc.v:176535.9-176535.17" case 1'1 case end @@ -355719,7 +327089,7 @@ module \pipe_start assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$next[31:0]$10356 $1\logical_op__data_len$next[3:0]$10351 $1\logical_op__is_signed$next[0:0]$10361 $1\logical_op__is_32bit$next[0:0]$10360 $1\logical_op__output_carry$next[0:0]$10364 $1\logical_op__write_cr0$next[0:0]$10367 $1\logical_op__invert_out$next[0:0]$10359 $1\logical_op__input_carry$next[1:0]$10355 $1\logical_op__zero_a$next[0:0]$10368 $1\logical_op__invert_in$next[0:0]$10358 $1\logical_op__oe__ok$next[0:0]$10363 $1\logical_op__oe__oe$next[0:0]$10362 $1\logical_op__rc__ok$next[0:0]$10365 $1\logical_op__rc__rc$next[0:0]$10366 $1\logical_op__imm_data__ok$next[0:0]$10354 $1\logical_op__imm_data__data$next[63:0]$10353 $1\logical_op__fn_unit$next[13:0]$10352 $1\logical_op__insn_type$next[6:0]$10357 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } + assign { $1\logical_op__insn$next[31:0]$10340 $1\logical_op__data_len$next[3:0]$10335 $1\logical_op__is_signed$next[0:0]$10345 $1\logical_op__is_32bit$next[0:0]$10344 $1\logical_op__output_carry$next[0:0]$10348 $1\logical_op__write_cr0$next[0:0]$10351 $1\logical_op__invert_out$next[0:0]$10343 $1\logical_op__input_carry$next[1:0]$10339 $1\logical_op__zero_a$next[0:0]$10352 $1\logical_op__invert_in$next[0:0]$10342 $1\logical_op__oe__ok$next[0:0]$10347 $1\logical_op__oe__oe$next[0:0]$10346 $1\logical_op__rc__ok$next[0:0]$10349 $1\logical_op__rc__rc$next[0:0]$10350 $1\logical_op__imm_data__ok$next[0:0]$10338 $1\logical_op__imm_data__data$next[63:0]$10337 $1\logical_op__fn_unit$next[13:0]$10336 $1\logical_op__insn_type$next[6:0]$10341 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } @@ -355740,26 +327110,26 @@ module \pipe_start assign { } { } assign { } { } assign { } { } - assign { $1\logical_op__insn$next[31:0]$10356 $1\logical_op__data_len$next[3:0]$10351 $1\logical_op__is_signed$next[0:0]$10361 $1\logical_op__is_32bit$next[0:0]$10360 $1\logical_op__output_carry$next[0:0]$10364 $1\logical_op__write_cr0$next[0:0]$10367 $1\logical_op__invert_out$next[0:0]$10359 $1\logical_op__input_carry$next[1:0]$10355 $1\logical_op__zero_a$next[0:0]$10368 $1\logical_op__invert_in$next[0:0]$10358 $1\logical_op__oe__ok$next[0:0]$10363 $1\logical_op__oe__oe$next[0:0]$10362 $1\logical_op__rc__ok$next[0:0]$10365 $1\logical_op__rc__rc$next[0:0]$10366 $1\logical_op__imm_data__ok$next[0:0]$10354 $1\logical_op__imm_data__data$next[63:0]$10353 $1\logical_op__fn_unit$next[13:0]$10352 $1\logical_op__insn_type$next[6:0]$10357 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } + assign { $1\logical_op__insn$next[31:0]$10340 $1\logical_op__data_len$next[3:0]$10335 $1\logical_op__is_signed$next[0:0]$10345 $1\logical_op__is_32bit$next[0:0]$10344 $1\logical_op__output_carry$next[0:0]$10348 $1\logical_op__write_cr0$next[0:0]$10351 $1\logical_op__invert_out$next[0:0]$10343 $1\logical_op__input_carry$next[1:0]$10339 $1\logical_op__zero_a$next[0:0]$10352 $1\logical_op__invert_in$next[0:0]$10342 $1\logical_op__oe__ok$next[0:0]$10347 $1\logical_op__oe__oe$next[0:0]$10346 $1\logical_op__rc__ok$next[0:0]$10349 $1\logical_op__rc__rc$next[0:0]$10350 $1\logical_op__imm_data__ok$next[0:0]$10338 $1\logical_op__imm_data__data$next[63:0]$10337 $1\logical_op__fn_unit$next[13:0]$10336 $1\logical_op__insn_type$next[6:0]$10341 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } case - assign $1\logical_op__data_len$next[3:0]$10351 \logical_op__data_len - assign $1\logical_op__fn_unit$next[13:0]$10352 \logical_op__fn_unit - assign $1\logical_op__imm_data__data$next[63:0]$10353 \logical_op__imm_data__data - assign $1\logical_op__imm_data__ok$next[0:0]$10354 \logical_op__imm_data__ok - assign $1\logical_op__input_carry$next[1:0]$10355 \logical_op__input_carry - assign $1\logical_op__insn$next[31:0]$10356 \logical_op__insn - assign $1\logical_op__insn_type$next[6:0]$10357 \logical_op__insn_type - assign $1\logical_op__invert_in$next[0:0]$10358 \logical_op__invert_in - assign $1\logical_op__invert_out$next[0:0]$10359 \logical_op__invert_out - assign $1\logical_op__is_32bit$next[0:0]$10360 \logical_op__is_32bit - assign $1\logical_op__is_signed$next[0:0]$10361 \logical_op__is_signed - assign $1\logical_op__oe__oe$next[0:0]$10362 \logical_op__oe__oe - assign $1\logical_op__oe__ok$next[0:0]$10363 \logical_op__oe__ok - assign $1\logical_op__output_carry$next[0:0]$10364 \logical_op__output_carry - assign $1\logical_op__rc__ok$next[0:0]$10365 \logical_op__rc__ok - assign $1\logical_op__rc__rc$next[0:0]$10366 \logical_op__rc__rc - assign $1\logical_op__write_cr0$next[0:0]$10367 \logical_op__write_cr0 - assign $1\logical_op__zero_a$next[0:0]$10368 \logical_op__zero_a + assign $1\logical_op__data_len$next[3:0]$10335 \logical_op__data_len + assign $1\logical_op__fn_unit$next[13:0]$10336 \logical_op__fn_unit + assign $1\logical_op__imm_data__data$next[63:0]$10337 \logical_op__imm_data__data + assign $1\logical_op__imm_data__ok$next[0:0]$10338 \logical_op__imm_data__ok + assign $1\logical_op__input_carry$next[1:0]$10339 \logical_op__input_carry + assign $1\logical_op__insn$next[31:0]$10340 \logical_op__insn + assign $1\logical_op__insn_type$next[6:0]$10341 \logical_op__insn_type + assign $1\logical_op__invert_in$next[0:0]$10342 \logical_op__invert_in + assign $1\logical_op__invert_out$next[0:0]$10343 \logical_op__invert_out + assign $1\logical_op__is_32bit$next[0:0]$10344 \logical_op__is_32bit + assign $1\logical_op__is_signed$next[0:0]$10345 \logical_op__is_signed + assign $1\logical_op__oe__oe$next[0:0]$10346 \logical_op__oe__oe + assign $1\logical_op__oe__ok$next[0:0]$10347 \logical_op__oe__ok + assign $1\logical_op__output_carry$next[0:0]$10348 \logical_op__output_carry + assign $1\logical_op__rc__ok$next[0:0]$10349 \logical_op__rc__ok + assign $1\logical_op__rc__rc$next[0:0]$10350 \logical_op__rc__rc + assign $1\logical_op__write_cr0$next[0:0]$10351 \logical_op__write_cr0 + assign $1\logical_op__zero_a$next[0:0]$10352 \logical_op__zero_a end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -355771,48 +327141,48 @@ module \pipe_start assign { } { } assign { } { } assign { } { } - assign $2\logical_op__imm_data__data$next[63:0]$10369 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\logical_op__imm_data__ok$next[0:0]$10370 1'0 - assign $2\logical_op__rc__rc$next[0:0]$10374 1'0 - assign $2\logical_op__rc__ok$next[0:0]$10373 1'0 - assign $2\logical_op__oe__oe$next[0:0]$10371 1'0 - assign $2\logical_op__oe__ok$next[0:0]$10372 1'0 + assign $2\logical_op__imm_data__data$next[63:0]$10353 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$next[0:0]$10354 1'0 + assign $2\logical_op__rc__rc$next[0:0]$10358 1'0 + assign $2\logical_op__rc__ok$next[0:0]$10357 1'0 + assign $2\logical_op__oe__oe$next[0:0]$10355 1'0 + assign $2\logical_op__oe__ok$next[0:0]$10356 1'0 case - assign $2\logical_op__imm_data__data$next[63:0]$10369 $1\logical_op__imm_data__data$next[63:0]$10353 - assign $2\logical_op__imm_data__ok$next[0:0]$10370 $1\logical_op__imm_data__ok$next[0:0]$10354 - assign $2\logical_op__oe__oe$next[0:0]$10371 $1\logical_op__oe__oe$next[0:0]$10362 - assign $2\logical_op__oe__ok$next[0:0]$10372 $1\logical_op__oe__ok$next[0:0]$10363 - assign $2\logical_op__rc__ok$next[0:0]$10373 $1\logical_op__rc__ok$next[0:0]$10365 - assign $2\logical_op__rc__rc$next[0:0]$10374 $1\logical_op__rc__rc$next[0:0]$10366 + assign $2\logical_op__imm_data__data$next[63:0]$10353 $1\logical_op__imm_data__data$next[63:0]$10337 + assign $2\logical_op__imm_data__ok$next[0:0]$10354 $1\logical_op__imm_data__ok$next[0:0]$10338 + assign $2\logical_op__oe__oe$next[0:0]$10355 $1\logical_op__oe__oe$next[0:0]$10346 + assign $2\logical_op__oe__ok$next[0:0]$10356 $1\logical_op__oe__ok$next[0:0]$10347 + assign $2\logical_op__rc__ok$next[0:0]$10357 $1\logical_op__rc__ok$next[0:0]$10349 + assign $2\logical_op__rc__rc$next[0:0]$10358 $1\logical_op__rc__rc$next[0:0]$10350 end sync always - update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$10333 - update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[13:0]$10334 - update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$10335 - update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$10336 - update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$10337 - update \logical_op__insn$next $0\logical_op__insn$next[31:0]$10338 - update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$10339 - update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$10340 - update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$10341 - update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$10342 - update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$10343 - update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$10344 - update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$10345 - update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$10346 - update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$10347 - update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$10348 - update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$10349 - update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$10350 + update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$10317 + update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[13:0]$10318 + update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$10319 + update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$10320 + update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$10321 + update \logical_op__insn$next $0\logical_op__insn$next[31:0]$10322 + update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$10323 + update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$10324 + update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$10325 + update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$10326 + update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$10327 + update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$10328 + update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$10329 + update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$10330 + update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$10331 + update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$10332 + update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$10333 + update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$10334 end - attribute \src "libresoc.v:175268.3-175280.6" - process $proc$libresoc.v:175268$10375 + attribute \src "libresoc.v:176576.3-176588.6" + process $proc$libresoc.v:176576$10359 assign { } { } assign { } { } - assign $0\ra$next[63:0]$10376 $1\ra$next[63:0]$10377 - attribute \src "libresoc.v:175269.5-175269.29" + assign $0\ra$next[63:0]$10360 $1\ra$next[63:0]$10361 + attribute \src "libresoc.v:176577.5-176577.29" switch \initial - attribute \src "libresoc.v:175269.9-175269.17" + attribute \src "libresoc.v:176577.9-176577.17" case 1'1 case end @@ -355821,25 +327191,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\ra$next[63:0]$10377 \ra$87 + assign $1\ra$next[63:0]$10361 \ra$87 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\ra$next[63:0]$10377 \ra$87 + assign $1\ra$next[63:0]$10361 \ra$87 case - assign $1\ra$next[63:0]$10377 \ra + assign $1\ra$next[63:0]$10361 \ra end sync always - update \ra$next $0\ra$next[63:0]$10376 + update \ra$next $0\ra$next[63:0]$10360 end - attribute \src "libresoc.v:175281.3-175293.6" - process $proc$libresoc.v:175281$10378 + attribute \src "libresoc.v:176589.3-176601.6" + process $proc$libresoc.v:176589$10362 assign { } { } assign { } { } - assign $0\rb$next[63:0]$10379 $1\rb$next[63:0]$10380 - attribute \src "libresoc.v:175282.5-175282.29" + assign $0\rb$next[63:0]$10363 $1\rb$next[63:0]$10364 + attribute \src "libresoc.v:176590.5-176590.29" switch \initial - attribute \src "libresoc.v:175282.9-175282.17" + attribute \src "libresoc.v:176590.9-176590.17" case 1'1 case end @@ -355848,25 +327218,25 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\rb$next[63:0]$10380 \rb$89 + assign $1\rb$next[63:0]$10364 \rb$89 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\rb$next[63:0]$10380 \rb$89 + assign $1\rb$next[63:0]$10364 \rb$89 case - assign $1\rb$next[63:0]$10380 \rb + assign $1\rb$next[63:0]$10364 \rb end sync always - update \rb$next $0\rb$next[63:0]$10379 + update \rb$next $0\rb$next[63:0]$10363 end - attribute \src "libresoc.v:175294.3-175306.6" - process $proc$libresoc.v:175294$10381 + attribute \src "libresoc.v:176602.3-176614.6" + process $proc$libresoc.v:176602$10365 assign { } { } assign { } { } - assign $0\xer_so$next[0:0]$10382 $1\xer_so$next[0:0]$10383 - attribute \src "libresoc.v:175295.5-175295.29" + assign $0\xer_so$next[0:0]$10366 $1\xer_so$next[0:0]$10367 + attribute \src "libresoc.v:176603.5-176603.29" switch \initial - attribute \src "libresoc.v:175295.9-175295.17" + attribute \src "libresoc.v:176603.9-176603.17" case 1'1 case end @@ -355875,18 +327245,18 @@ module \pipe_start attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\xer_so$next[0:0]$10383 \xer_so$91 + assign $1\xer_so$next[0:0]$10367 \xer_so$91 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\xer_so$next[0:0]$10383 \xer_so$91 + assign $1\xer_so$next[0:0]$10367 \xer_so$91 case - assign $1\xer_so$next[0:0]$10383 \xer_so + assign $1\xer_so$next[0:0]$10367 \xer_so end sync always - update \xer_so$next $0\xer_so$next[0:0]$10382 + update \xer_so$next $0\xer_so$next[0:0]$10366 end - connect \$66 $and$libresoc.v:174922$10269_Y + connect \$66 $and$libresoc.v:176230$10253_Y connect \ra$88 64'0000000000000000000000000000000000000000000000000000000000000000 connect \rb$90 64'0000000000000000000000000000000000000000000000000000000000000000 connect \p_ready_o \n_i_rdy_data @@ -355918,27 +327288,27 @@ module \pipe_start connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } connect \input_muxid \muxid$1 end -attribute \src "libresoc.v:175341.1-175385.10" +attribute \src "libresoc.v:176649.1-176693.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.pll" attribute \generator "nMigen" module \pll - attribute \src "libresoc.v:175342.7-175342.20" + attribute \src "libresoc.v:176650.7-176650.20" wire $0\initial[0:0] - attribute \src "libresoc.v:175374.3-175383.6" + attribute \src "libresoc.v:176682.3-176691.6" wire $0\pll_18_o[0:0] - attribute \src "libresoc.v:175364.3-175373.6" + attribute \src "libresoc.v:176672.3-176681.6" wire $0\pll_lck_o[0:0] - attribute \src "libresoc.v:175374.3-175383.6" + attribute \src "libresoc.v:176682.3-176691.6" wire $1\pll_18_o[0:0] - attribute \src "libresoc.v:175364.3-175373.6" + attribute \src "libresoc.v:176672.3-176681.6" wire $1\pll_lck_o[0:0] - attribute \src "libresoc.v:175361.17-175361.105" - wire $eq$libresoc.v:175361$10416_Y - attribute \src "libresoc.v:175362.17-175362.105" - wire $eq$libresoc.v:175362$10417_Y - attribute \src "libresoc.v:175363.17-175363.98" - wire $not$libresoc.v:175363$10418_Y + attribute \src "libresoc.v:176669.17-176669.105" + wire $eq$libresoc.v:176669$10400_Y + attribute \src "libresoc.v:176670.17-176670.105" + wire $eq$libresoc.v:176670$10401_Y + attribute \src "libresoc.v:176671.17-176671.98" + wire $not$libresoc.v:176671$10402_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" @@ -355951,14 +327321,14 @@ module \pll wire output 5 \clk_pll_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" wire width 2 input 3 \clk_sel_i - attribute \src "libresoc.v:175342.7-175342.15" + attribute \src "libresoc.v:176650.7-176650.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" wire output 2 \pll_18_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" wire output 4 \pll_lck_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" - cell $eq $eq$libresoc.v:175361$10416 + cell $eq $eq$libresoc.v:176669$10400 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -355966,10 +327336,10 @@ module \pll parameter \Y_WIDTH 1 connect \A \clk_sel_i connect \B 2'00 - connect \Y $eq$libresoc.v:175361$10416_Y + connect \Y $eq$libresoc.v:176669$10400_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:19" - cell $eq $eq$libresoc.v:175362$10417 + cell $eq $eq$libresoc.v:176670$10401 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -355977,32 +327347,32 @@ module \pll parameter \Y_WIDTH 1 connect \A \clk_sel_i connect \B 2'00 - connect \Y $eq$libresoc.v:175362$10417_Y + connect \Y $eq$libresoc.v:176670$10401_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:21" - cell $not $not$libresoc.v:175363$10418 + cell $not $not$libresoc.v:176671$10402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \clk_24_i - connect \Y $not$libresoc.v:175363$10418_Y + connect \Y $not$libresoc.v:176671$10402_Y end - attribute \src "libresoc.v:175342.7-175342.20" - process $proc$libresoc.v:175342$10421 + attribute \src "libresoc.v:176650.7-176650.20" + process $proc$libresoc.v:176650$10405 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:175364.3-175373.6" - process $proc$libresoc.v:175364$10419 + attribute \src "libresoc.v:176672.3-176681.6" + process $proc$libresoc.v:176672$10403 assign { } { } assign { } { } assign $0\pll_lck_o[0:0] $1\pll_lck_o[0:0] - attribute \src "libresoc.v:175365.5-175365.29" + attribute \src "libresoc.v:176673.5-176673.29" switch \initial - attribute \src "libresoc.v:175365.9-175365.17" + attribute \src "libresoc.v:176673.9-176673.17" case 1'1 case end @@ -356018,14 +327388,14 @@ module \pll sync always update \pll_lck_o $0\pll_lck_o[0:0] end - attribute \src "libresoc.v:175374.3-175383.6" - process $proc$libresoc.v:175374$10420 + attribute \src "libresoc.v:176682.3-176691.6" + process $proc$libresoc.v:176682$10404 assign { } { } assign { } { } assign $0\pll_18_o[0:0] $1\pll_18_o[0:0] - attribute \src "libresoc.v:175375.5-175375.29" + attribute \src "libresoc.v:176683.5-176683.29" switch \initial - attribute \src "libresoc.v:175375.9-175375.17" + attribute \src "libresoc.v:176683.9-176683.17" case 1'1 case end @@ -356041,196 +327411,196 @@ module \pll sync always update \pll_18_o $0\pll_18_o[0:0] end - connect \$1 $eq$libresoc.v:175361$10416_Y - connect \$3 $eq$libresoc.v:175362$10417_Y - connect \$5 $not$libresoc.v:175363$10418_Y + connect \$1 $eq$libresoc.v:176669$10400_Y + connect \$3 $eq$libresoc.v:176670$10401_Y + connect \$5 $not$libresoc.v:176671$10402_Y connect \clk_pll_o \clk_24_i end -attribute \src "libresoc.v:175389.1-176031.10" +attribute \src "libresoc.v:176697.1-177339.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.alu_logical0.logical_pipe1.main.popcount" attribute \generator "nMigen" module \popcount - attribute \src "libresoc.v:175390.7-175390.20" + attribute \src "libresoc.v:176698.7-176698.20" wire $0\initial[0:0] - attribute \src "libresoc.v:175878.3-175904.6" + attribute \src "libresoc.v:177186.3-177212.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:175878.3-175904.6" + attribute \src "libresoc.v:177186.3-177212.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:175802.19-175802.132" - wire width 4 $add$libresoc.v:175802$10422_Y - attribute \src "libresoc.v:175803.19-175803.132" - wire width 4 $add$libresoc.v:175803$10423_Y - attribute \src "libresoc.v:175804.19-175804.132" - wire width 4 $add$libresoc.v:175804$10424_Y - attribute \src "libresoc.v:175805.19-175805.132" - wire width 4 $add$libresoc.v:175805$10425_Y - attribute \src "libresoc.v:175806.19-175806.134" - wire width 4 $add$libresoc.v:175806$10426_Y - attribute \src "libresoc.v:175807.19-175807.134" - wire width 4 $add$libresoc.v:175807$10427_Y - attribute \src "libresoc.v:175808.18-175808.125" - wire width 3 $add$libresoc.v:175808$10428_Y - attribute \src "libresoc.v:175809.19-175809.134" - wire width 4 $add$libresoc.v:175809$10429_Y - attribute \src "libresoc.v:175810.19-175810.134" - wire width 4 $add$libresoc.v:175810$10430_Y - attribute \src "libresoc.v:175811.19-175811.134" - wire width 4 $add$libresoc.v:175811$10431_Y - attribute \src "libresoc.v:175812.19-175812.134" - wire width 4 $add$libresoc.v:175812$10432_Y - attribute \src "libresoc.v:175813.19-175813.134" - wire width 4 $add$libresoc.v:175813$10433_Y - attribute \src "libresoc.v:175814.19-175814.134" - wire width 4 $add$libresoc.v:175814$10434_Y - attribute \src "libresoc.v:175815.19-175815.134" - wire width 4 $add$libresoc.v:175815$10435_Y - attribute \src "libresoc.v:175816.19-175816.134" - wire width 4 $add$libresoc.v:175816$10436_Y - attribute \src "libresoc.v:175817.19-175817.134" - wire width 4 $add$libresoc.v:175817$10437_Y - attribute \src "libresoc.v:175818.19-175818.132" - wire width 5 $add$libresoc.v:175818$10438_Y - attribute \src "libresoc.v:175819.18-175819.125" - wire width 3 $add$libresoc.v:175819$10439_Y - attribute \src "libresoc.v:175820.19-175820.132" - wire width 5 $add$libresoc.v:175820$10440_Y - attribute \src "libresoc.v:175821.19-175821.132" - wire width 5 $add$libresoc.v:175821$10441_Y - attribute \src "libresoc.v:175822.19-175822.132" - wire width 5 $add$libresoc.v:175822$10442_Y - attribute \src "libresoc.v:175823.19-175823.132" - wire width 5 $add$libresoc.v:175823$10443_Y - attribute \src "libresoc.v:175824.19-175824.134" - wire width 5 $add$libresoc.v:175824$10444_Y - attribute \src "libresoc.v:175825.19-175825.134" - wire width 5 $add$libresoc.v:175825$10445_Y - attribute \src "libresoc.v:175826.19-175826.134" - wire width 5 $add$libresoc.v:175826$10446_Y - attribute \src "libresoc.v:175827.19-175827.132" - wire width 6 $add$libresoc.v:175827$10447_Y - attribute \src "libresoc.v:175828.19-175828.132" - wire width 6 $add$libresoc.v:175828$10448_Y - attribute \src "libresoc.v:175829.19-175829.132" - wire width 6 $add$libresoc.v:175829$10449_Y - attribute \src "libresoc.v:175830.18-175830.127" - wire width 3 $add$libresoc.v:175830$10450_Y - attribute \src "libresoc.v:175831.19-175831.132" - wire width 6 $add$libresoc.v:175831$10451_Y - attribute \src "libresoc.v:175832.19-175832.132" - wire width 7 $add$libresoc.v:175832$10452_Y - attribute \src "libresoc.v:175833.19-175833.132" - wire width 7 $add$libresoc.v:175833$10453_Y - attribute \src "libresoc.v:175834.19-175834.132" - wire width 8 $add$libresoc.v:175834$10454_Y - attribute \src "libresoc.v:175845.18-175845.127" - wire width 3 $add$libresoc.v:175845$10473_Y - attribute \src "libresoc.v:175849.18-175849.127" - wire width 3 $add$libresoc.v:175849$10480_Y - attribute \src "libresoc.v:175850.18-175850.127" - wire width 3 $add$libresoc.v:175850$10481_Y - attribute \src "libresoc.v:175851.17-175851.124" - wire width 3 $add$libresoc.v:175851$10482_Y - attribute \src "libresoc.v:175852.18-175852.127" - wire width 3 $add$libresoc.v:175852$10483_Y - attribute \src "libresoc.v:175853.18-175853.127" - wire width 3 $add$libresoc.v:175853$10484_Y - attribute \src "libresoc.v:175854.18-175854.127" - wire width 3 $add$libresoc.v:175854$10485_Y - attribute \src "libresoc.v:175855.18-175855.127" - wire width 3 $add$libresoc.v:175855$10486_Y - attribute \src "libresoc.v:175856.18-175856.127" - wire width 3 $add$libresoc.v:175856$10487_Y - attribute \src "libresoc.v:175857.18-175857.127" - wire width 3 $add$libresoc.v:175857$10488_Y - attribute \src "libresoc.v:175858.18-175858.127" - wire width 3 $add$libresoc.v:175858$10489_Y - attribute \src "libresoc.v:175859.18-175859.127" - wire width 3 $add$libresoc.v:175859$10490_Y - attribute \src "libresoc.v:175860.18-175860.127" - wire width 3 $add$libresoc.v:175860$10491_Y - attribute \src "libresoc.v:175861.18-175861.127" - wire width 3 $add$libresoc.v:175861$10492_Y - attribute \src "libresoc.v:175862.17-175862.124" - wire width 3 $add$libresoc.v:175862$10493_Y - attribute \src "libresoc.v:175863.18-175863.127" - wire width 3 $add$libresoc.v:175863$10494_Y - attribute \src "libresoc.v:175864.18-175864.127" - wire width 3 $add$libresoc.v:175864$10495_Y - attribute \src "libresoc.v:175865.18-175865.127" - wire width 3 $add$libresoc.v:175865$10496_Y - attribute \src "libresoc.v:175866.18-175866.127" - wire width 3 $add$libresoc.v:175866$10497_Y - attribute \src "libresoc.v:175867.18-175867.127" - wire width 3 $add$libresoc.v:175867$10498_Y - attribute \src "libresoc.v:175868.18-175868.127" - wire width 3 $add$libresoc.v:175868$10499_Y - attribute \src "libresoc.v:175869.18-175869.127" - wire width 3 $add$libresoc.v:175869$10500_Y - attribute \src "libresoc.v:175870.18-175870.127" - wire width 3 $add$libresoc.v:175870$10501_Y - attribute \src "libresoc.v:175871.18-175871.127" - wire width 3 $add$libresoc.v:175871$10502_Y - attribute \src "libresoc.v:175872.18-175872.127" - wire width 3 $add$libresoc.v:175872$10503_Y - attribute \src "libresoc.v:175873.17-175873.124" - wire width 3 $add$libresoc.v:175873$10504_Y - attribute \src "libresoc.v:175874.18-175874.127" - wire width 3 $add$libresoc.v:175874$10505_Y - attribute \src "libresoc.v:175875.18-175875.127" - wire width 3 $add$libresoc.v:175875$10506_Y - attribute \src "libresoc.v:175876.18-175876.127" - wire width 3 $add$libresoc.v:175876$10507_Y - attribute \src "libresoc.v:175877.18-175877.131" - wire width 4 $add$libresoc.v:175877$10508_Y - attribute \src "libresoc.v:175835.19-175835.111" - wire $eq$libresoc.v:175835$10455_Y - attribute \src "libresoc.v:175836.19-175836.111" - wire $eq$libresoc.v:175836$10456_Y - attribute \src "libresoc.v:175837.19-175837.104" - wire width 8 $extend$libresoc.v:175837$10457_Y - attribute \src "libresoc.v:175838.19-175838.104" - wire width 8 $extend$libresoc.v:175838$10459_Y - attribute \src "libresoc.v:175839.19-175839.104" - wire width 8 $extend$libresoc.v:175839$10461_Y - attribute \src "libresoc.v:175840.19-175840.104" - wire width 8 $extend$libresoc.v:175840$10463_Y - attribute \src "libresoc.v:175841.19-175841.104" - wire width 8 $extend$libresoc.v:175841$10465_Y - attribute \src "libresoc.v:175842.19-175842.104" - wire width 8 $extend$libresoc.v:175842$10467_Y - attribute \src "libresoc.v:175843.19-175843.104" - wire width 8 $extend$libresoc.v:175843$10469_Y - attribute \src "libresoc.v:175844.19-175844.104" - wire width 8 $extend$libresoc.v:175844$10471_Y - attribute \src "libresoc.v:175846.19-175846.104" - wire width 32 $extend$libresoc.v:175846$10474_Y - attribute \src "libresoc.v:175847.19-175847.104" - wire width 32 $extend$libresoc.v:175847$10476_Y - attribute \src "libresoc.v:175848.19-175848.104" - wire width 64 $extend$libresoc.v:175848$10478_Y - attribute \src "libresoc.v:175837.19-175837.104" - wire width 8 $pos$libresoc.v:175837$10458_Y - attribute \src "libresoc.v:175838.19-175838.104" - wire width 8 $pos$libresoc.v:175838$10460_Y - attribute \src "libresoc.v:175839.19-175839.104" - wire width 8 $pos$libresoc.v:175839$10462_Y - attribute \src "libresoc.v:175840.19-175840.104" - wire width 8 $pos$libresoc.v:175840$10464_Y - attribute \src "libresoc.v:175841.19-175841.104" - wire width 8 $pos$libresoc.v:175841$10466_Y - attribute \src "libresoc.v:175842.19-175842.104" - wire width 8 $pos$libresoc.v:175842$10468_Y - attribute \src "libresoc.v:175843.19-175843.104" - wire width 8 $pos$libresoc.v:175843$10470_Y - attribute \src "libresoc.v:175844.19-175844.104" - wire width 8 $pos$libresoc.v:175844$10472_Y - attribute \src "libresoc.v:175846.19-175846.104" - wire width 32 $pos$libresoc.v:175846$10475_Y - attribute \src "libresoc.v:175847.19-175847.104" - wire width 32 $pos$libresoc.v:175847$10477_Y - attribute \src "libresoc.v:175848.19-175848.104" - wire width 64 $pos$libresoc.v:175848$10479_Y + attribute \src "libresoc.v:177110.19-177110.132" + wire width 4 $add$libresoc.v:177110$10406_Y + attribute \src "libresoc.v:177111.19-177111.132" + wire width 4 $add$libresoc.v:177111$10407_Y + attribute \src "libresoc.v:177112.19-177112.132" + wire width 4 $add$libresoc.v:177112$10408_Y + attribute \src "libresoc.v:177113.19-177113.132" + wire width 4 $add$libresoc.v:177113$10409_Y + attribute \src "libresoc.v:177114.19-177114.134" + wire width 4 $add$libresoc.v:177114$10410_Y + attribute \src "libresoc.v:177115.19-177115.134" + wire width 4 $add$libresoc.v:177115$10411_Y + attribute \src "libresoc.v:177116.18-177116.125" + wire width 3 $add$libresoc.v:177116$10412_Y + attribute \src "libresoc.v:177117.19-177117.134" + wire width 4 $add$libresoc.v:177117$10413_Y + attribute \src "libresoc.v:177118.19-177118.134" + wire width 4 $add$libresoc.v:177118$10414_Y + attribute \src "libresoc.v:177119.19-177119.134" + wire width 4 $add$libresoc.v:177119$10415_Y + attribute \src "libresoc.v:177120.19-177120.134" + wire width 4 $add$libresoc.v:177120$10416_Y + attribute \src "libresoc.v:177121.19-177121.134" + wire width 4 $add$libresoc.v:177121$10417_Y + attribute \src "libresoc.v:177122.19-177122.134" + wire width 4 $add$libresoc.v:177122$10418_Y + attribute \src "libresoc.v:177123.19-177123.134" + wire width 4 $add$libresoc.v:177123$10419_Y + attribute \src "libresoc.v:177124.19-177124.134" + wire width 4 $add$libresoc.v:177124$10420_Y + attribute \src "libresoc.v:177125.19-177125.134" + wire width 4 $add$libresoc.v:177125$10421_Y + attribute \src "libresoc.v:177126.19-177126.132" + wire width 5 $add$libresoc.v:177126$10422_Y + attribute \src "libresoc.v:177127.18-177127.125" + wire width 3 $add$libresoc.v:177127$10423_Y + attribute \src "libresoc.v:177128.19-177128.132" + wire width 5 $add$libresoc.v:177128$10424_Y + attribute \src "libresoc.v:177129.19-177129.132" + wire width 5 $add$libresoc.v:177129$10425_Y + attribute \src "libresoc.v:177130.19-177130.132" + wire width 5 $add$libresoc.v:177130$10426_Y + attribute \src "libresoc.v:177131.19-177131.132" + wire width 5 $add$libresoc.v:177131$10427_Y + attribute \src "libresoc.v:177132.19-177132.134" + wire width 5 $add$libresoc.v:177132$10428_Y + attribute \src "libresoc.v:177133.19-177133.134" + wire width 5 $add$libresoc.v:177133$10429_Y + attribute \src "libresoc.v:177134.19-177134.134" + wire width 5 $add$libresoc.v:177134$10430_Y + attribute \src "libresoc.v:177135.19-177135.132" + wire width 6 $add$libresoc.v:177135$10431_Y + attribute \src "libresoc.v:177136.19-177136.132" + wire width 6 $add$libresoc.v:177136$10432_Y + attribute \src "libresoc.v:177137.19-177137.132" + wire width 6 $add$libresoc.v:177137$10433_Y + attribute \src "libresoc.v:177138.18-177138.127" + wire width 3 $add$libresoc.v:177138$10434_Y + attribute \src "libresoc.v:177139.19-177139.132" + wire width 6 $add$libresoc.v:177139$10435_Y + attribute \src "libresoc.v:177140.19-177140.132" + wire width 7 $add$libresoc.v:177140$10436_Y + attribute \src "libresoc.v:177141.19-177141.132" + wire width 7 $add$libresoc.v:177141$10437_Y + attribute \src "libresoc.v:177142.19-177142.132" + wire width 8 $add$libresoc.v:177142$10438_Y + attribute \src "libresoc.v:177153.18-177153.127" + wire width 3 $add$libresoc.v:177153$10457_Y + attribute \src "libresoc.v:177157.18-177157.127" + wire width 3 $add$libresoc.v:177157$10464_Y + attribute \src "libresoc.v:177158.18-177158.127" + wire width 3 $add$libresoc.v:177158$10465_Y + attribute \src "libresoc.v:177159.17-177159.124" + wire width 3 $add$libresoc.v:177159$10466_Y + attribute \src "libresoc.v:177160.18-177160.127" + wire width 3 $add$libresoc.v:177160$10467_Y + attribute \src "libresoc.v:177161.18-177161.127" + wire width 3 $add$libresoc.v:177161$10468_Y + attribute \src "libresoc.v:177162.18-177162.127" + wire width 3 $add$libresoc.v:177162$10469_Y + attribute \src "libresoc.v:177163.18-177163.127" + wire width 3 $add$libresoc.v:177163$10470_Y + attribute \src "libresoc.v:177164.18-177164.127" + wire width 3 $add$libresoc.v:177164$10471_Y + attribute \src "libresoc.v:177165.18-177165.127" + wire width 3 $add$libresoc.v:177165$10472_Y + attribute \src "libresoc.v:177166.18-177166.127" + wire width 3 $add$libresoc.v:177166$10473_Y + attribute \src "libresoc.v:177167.18-177167.127" + wire width 3 $add$libresoc.v:177167$10474_Y + attribute \src "libresoc.v:177168.18-177168.127" + wire width 3 $add$libresoc.v:177168$10475_Y + attribute \src "libresoc.v:177169.18-177169.127" + wire width 3 $add$libresoc.v:177169$10476_Y + attribute \src "libresoc.v:177170.17-177170.124" + wire width 3 $add$libresoc.v:177170$10477_Y + attribute \src "libresoc.v:177171.18-177171.127" + wire width 3 $add$libresoc.v:177171$10478_Y + attribute \src "libresoc.v:177172.18-177172.127" + wire width 3 $add$libresoc.v:177172$10479_Y + attribute \src "libresoc.v:177173.18-177173.127" + wire width 3 $add$libresoc.v:177173$10480_Y + attribute \src "libresoc.v:177174.18-177174.127" + wire width 3 $add$libresoc.v:177174$10481_Y + attribute \src "libresoc.v:177175.18-177175.127" + wire width 3 $add$libresoc.v:177175$10482_Y + attribute \src "libresoc.v:177176.18-177176.127" + wire width 3 $add$libresoc.v:177176$10483_Y + attribute \src "libresoc.v:177177.18-177177.127" + wire width 3 $add$libresoc.v:177177$10484_Y + attribute \src "libresoc.v:177178.18-177178.127" + wire width 3 $add$libresoc.v:177178$10485_Y + attribute \src "libresoc.v:177179.18-177179.127" + wire width 3 $add$libresoc.v:177179$10486_Y + attribute \src "libresoc.v:177180.18-177180.127" + wire width 3 $add$libresoc.v:177180$10487_Y + attribute \src "libresoc.v:177181.17-177181.124" + wire width 3 $add$libresoc.v:177181$10488_Y + attribute \src "libresoc.v:177182.18-177182.127" + wire width 3 $add$libresoc.v:177182$10489_Y + attribute \src "libresoc.v:177183.18-177183.127" + wire width 3 $add$libresoc.v:177183$10490_Y + attribute \src "libresoc.v:177184.18-177184.127" + wire width 3 $add$libresoc.v:177184$10491_Y + attribute \src "libresoc.v:177185.18-177185.131" + wire width 4 $add$libresoc.v:177185$10492_Y + attribute \src "libresoc.v:177143.19-177143.111" + wire $eq$libresoc.v:177143$10439_Y + attribute \src "libresoc.v:177144.19-177144.111" + wire $eq$libresoc.v:177144$10440_Y + attribute \src "libresoc.v:177145.19-177145.104" + wire width 8 $extend$libresoc.v:177145$10441_Y + attribute \src "libresoc.v:177146.19-177146.104" + wire width 8 $extend$libresoc.v:177146$10443_Y + attribute \src "libresoc.v:177147.19-177147.104" + wire width 8 $extend$libresoc.v:177147$10445_Y + attribute \src "libresoc.v:177148.19-177148.104" + wire width 8 $extend$libresoc.v:177148$10447_Y + attribute \src "libresoc.v:177149.19-177149.104" + wire width 8 $extend$libresoc.v:177149$10449_Y + attribute \src "libresoc.v:177150.19-177150.104" + wire width 8 $extend$libresoc.v:177150$10451_Y + attribute \src "libresoc.v:177151.19-177151.104" + wire width 8 $extend$libresoc.v:177151$10453_Y + attribute \src "libresoc.v:177152.19-177152.104" + wire width 8 $extend$libresoc.v:177152$10455_Y + attribute \src "libresoc.v:177154.19-177154.104" + wire width 32 $extend$libresoc.v:177154$10458_Y + attribute \src "libresoc.v:177155.19-177155.104" + wire width 32 $extend$libresoc.v:177155$10460_Y + attribute \src "libresoc.v:177156.19-177156.104" + wire width 64 $extend$libresoc.v:177156$10462_Y + attribute \src "libresoc.v:177145.19-177145.104" + wire width 8 $pos$libresoc.v:177145$10442_Y + attribute \src "libresoc.v:177146.19-177146.104" + wire width 8 $pos$libresoc.v:177146$10444_Y + attribute \src "libresoc.v:177147.19-177147.104" + wire width 8 $pos$libresoc.v:177147$10446_Y + attribute \src "libresoc.v:177148.19-177148.104" + wire width 8 $pos$libresoc.v:177148$10448_Y + attribute \src "libresoc.v:177149.19-177149.104" + wire width 8 $pos$libresoc.v:177149$10450_Y + attribute \src "libresoc.v:177150.19-177150.104" + wire width 8 $pos$libresoc.v:177150$10452_Y + attribute \src "libresoc.v:177151.19-177151.104" + wire width 8 $pos$libresoc.v:177151$10454_Y + attribute \src "libresoc.v:177152.19-177152.104" + wire width 8 $pos$libresoc.v:177152$10456_Y + attribute \src "libresoc.v:177154.19-177154.104" + wire width 32 $pos$libresoc.v:177154$10459_Y + attribute \src "libresoc.v:177155.19-177155.104" + wire width 32 $pos$libresoc.v:177155$10461_Y + attribute \src "libresoc.v:177156.19-177156.104" + wire width 64 $pos$libresoc.v:177156$10463_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" @@ -356513,7 +327883,7 @@ module \popcount wire width 64 input 3 \a attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:29" wire width 64 input 1 \data_len - attribute \src "libresoc.v:175390.7-175390.15" + attribute \src "libresoc.v:176698.7-176698.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:30" wire width 64 output 2 \o @@ -356644,7 +328014,7 @@ module \popcount attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" wire width 7 \pop_7_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175802$10422 + cell $add $add$libresoc.v:177110$10406 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -356652,10 +328022,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_2 } connect \B { 2'00 \pop_2_3 } - connect \Y $add$libresoc.v:175802$10422_Y + connect \Y $add$libresoc.v:177110$10406_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175803$10423 + cell $add $add$libresoc.v:177111$10407 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -356663,10 +328033,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_4 } connect \B { 2'00 \pop_2_5 } - connect \Y $add$libresoc.v:175803$10423_Y + connect \Y $add$libresoc.v:177111$10407_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175804$10424 + cell $add $add$libresoc.v:177112$10408 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -356674,10 +328044,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_6 } connect \B { 2'00 \pop_2_7 } - connect \Y $add$libresoc.v:175804$10424_Y + connect \Y $add$libresoc.v:177112$10408_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175805$10425 + cell $add $add$libresoc.v:177113$10409 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -356685,10 +328055,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_8 } connect \B { 2'00 \pop_2_9 } - connect \Y $add$libresoc.v:175805$10425_Y + connect \Y $add$libresoc.v:177113$10409_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175806$10426 + cell $add $add$libresoc.v:177114$10410 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -356696,10 +328066,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_10 } connect \B { 2'00 \pop_2_11 } - connect \Y $add$libresoc.v:175806$10426_Y + connect \Y $add$libresoc.v:177114$10410_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175807$10427 + cell $add $add$libresoc.v:177115$10411 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -356707,10 +328077,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_12 } connect \B { 2'00 \pop_2_13 } - connect \Y $add$libresoc.v:175807$10427_Y + connect \Y $add$libresoc.v:177115$10411_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175808$10428 + cell $add $add$libresoc.v:177116$10412 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -356718,10 +328088,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [6] } connect \B { 2'00 \a [7] } - connect \Y $add$libresoc.v:175808$10428_Y + connect \Y $add$libresoc.v:177116$10412_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175809$10429 + cell $add $add$libresoc.v:177117$10413 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -356729,10 +328099,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_14 } connect \B { 2'00 \pop_2_15 } - connect \Y $add$libresoc.v:175809$10429_Y + connect \Y $add$libresoc.v:177117$10413_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175810$10430 + cell $add $add$libresoc.v:177118$10414 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -356740,10 +328110,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_16 } connect \B { 2'00 \pop_2_17 } - connect \Y $add$libresoc.v:175810$10430_Y + connect \Y $add$libresoc.v:177118$10414_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175811$10431 + cell $add $add$libresoc.v:177119$10415 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -356751,10 +328121,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_18 } connect \B { 2'00 \pop_2_19 } - connect \Y $add$libresoc.v:175811$10431_Y + connect \Y $add$libresoc.v:177119$10415_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175812$10432 + cell $add $add$libresoc.v:177120$10416 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -356762,10 +328132,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_20 } connect \B { 2'00 \pop_2_21 } - connect \Y $add$libresoc.v:175812$10432_Y + connect \Y $add$libresoc.v:177120$10416_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175813$10433 + cell $add $add$libresoc.v:177121$10417 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -356773,10 +328143,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_22 } connect \B { 2'00 \pop_2_23 } - connect \Y $add$libresoc.v:175813$10433_Y + connect \Y $add$libresoc.v:177121$10417_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175814$10434 + cell $add $add$libresoc.v:177122$10418 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -356784,10 +328154,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_24 } connect \B { 2'00 \pop_2_25 } - connect \Y $add$libresoc.v:175814$10434_Y + connect \Y $add$libresoc.v:177122$10418_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175815$10435 + cell $add $add$libresoc.v:177123$10419 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -356795,10 +328165,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_26 } connect \B { 2'00 \pop_2_27 } - connect \Y $add$libresoc.v:175815$10435_Y + connect \Y $add$libresoc.v:177123$10419_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175816$10436 + cell $add $add$libresoc.v:177124$10420 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -356806,10 +328176,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_28 } connect \B { 2'00 \pop_2_29 } - connect \Y $add$libresoc.v:175816$10436_Y + connect \Y $add$libresoc.v:177124$10420_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175817$10437 + cell $add $add$libresoc.v:177125$10421 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -356817,10 +328187,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_30 } connect \B { 2'00 \pop_2_31 } - connect \Y $add$libresoc.v:175817$10437_Y + connect \Y $add$libresoc.v:177125$10421_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175818$10438 + cell $add $add$libresoc.v:177126$10422 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -356828,10 +328198,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_0 } connect \B { 2'00 \pop_3_1 } - connect \Y $add$libresoc.v:175818$10438_Y + connect \Y $add$libresoc.v:177126$10422_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175819$10439 + cell $add $add$libresoc.v:177127$10423 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -356839,10 +328209,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [8] } connect \B { 2'00 \a [9] } - connect \Y $add$libresoc.v:175819$10439_Y + connect \Y $add$libresoc.v:177127$10423_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175820$10440 + cell $add $add$libresoc.v:177128$10424 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -356850,10 +328220,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_2 } connect \B { 2'00 \pop_3_3 } - connect \Y $add$libresoc.v:175820$10440_Y + connect \Y $add$libresoc.v:177128$10424_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175821$10441 + cell $add $add$libresoc.v:177129$10425 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -356861,10 +328231,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_4 } connect \B { 2'00 \pop_3_5 } - connect \Y $add$libresoc.v:175821$10441_Y + connect \Y $add$libresoc.v:177129$10425_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175822$10442 + cell $add $add$libresoc.v:177130$10426 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -356872,10 +328242,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_6 } connect \B { 2'00 \pop_3_7 } - connect \Y $add$libresoc.v:175822$10442_Y + connect \Y $add$libresoc.v:177130$10426_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175823$10443 + cell $add $add$libresoc.v:177131$10427 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -356883,10 +328253,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_8 } connect \B { 2'00 \pop_3_9 } - connect \Y $add$libresoc.v:175823$10443_Y + connect \Y $add$libresoc.v:177131$10427_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175824$10444 + cell $add $add$libresoc.v:177132$10428 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -356894,10 +328264,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_10 } connect \B { 2'00 \pop_3_11 } - connect \Y $add$libresoc.v:175824$10444_Y + connect \Y $add$libresoc.v:177132$10428_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175825$10445 + cell $add $add$libresoc.v:177133$10429 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -356905,10 +328275,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_12 } connect \B { 2'00 \pop_3_13 } - connect \Y $add$libresoc.v:175825$10445_Y + connect \Y $add$libresoc.v:177133$10429_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175826$10446 + cell $add $add$libresoc.v:177134$10430 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -356916,10 +328286,10 @@ module \popcount parameter \Y_WIDTH 5 connect \A { 2'00 \pop_3_14 } connect \B { 2'00 \pop_3_15 } - connect \Y $add$libresoc.v:175826$10446_Y + connect \Y $add$libresoc.v:177134$10430_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175827$10447 + cell $add $add$libresoc.v:177135$10431 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -356927,10 +328297,10 @@ module \popcount parameter \Y_WIDTH 6 connect \A { 2'00 \pop_4_0 } connect \B { 2'00 \pop_4_1 } - connect \Y $add$libresoc.v:175827$10447_Y + connect \Y $add$libresoc.v:177135$10431_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175828$10448 + cell $add $add$libresoc.v:177136$10432 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -356938,10 +328308,10 @@ module \popcount parameter \Y_WIDTH 6 connect \A { 2'00 \pop_4_2 } connect \B { 2'00 \pop_4_3 } - connect \Y $add$libresoc.v:175828$10448_Y + connect \Y $add$libresoc.v:177136$10432_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175829$10449 + cell $add $add$libresoc.v:177137$10433 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -356949,10 +328319,10 @@ module \popcount parameter \Y_WIDTH 6 connect \A { 2'00 \pop_4_4 } connect \B { 2'00 \pop_4_5 } - connect \Y $add$libresoc.v:175829$10449_Y + connect \Y $add$libresoc.v:177137$10433_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175830$10450 + cell $add $add$libresoc.v:177138$10434 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -356960,10 +328330,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [10] } connect \B { 2'00 \a [11] } - connect \Y $add$libresoc.v:175830$10450_Y + connect \Y $add$libresoc.v:177138$10434_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175831$10451 + cell $add $add$libresoc.v:177139$10435 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -356971,10 +328341,10 @@ module \popcount parameter \Y_WIDTH 6 connect \A { 2'00 \pop_4_6 } connect \B { 2'00 \pop_4_7 } - connect \Y $add$libresoc.v:175831$10451_Y + connect \Y $add$libresoc.v:177139$10435_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175832$10452 + cell $add $add$libresoc.v:177140$10436 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -356982,10 +328352,10 @@ module \popcount parameter \Y_WIDTH 7 connect \A { 2'00 \pop_5_0 } connect \B { 2'00 \pop_5_1 } - connect \Y $add$libresoc.v:175832$10452_Y + connect \Y $add$libresoc.v:177140$10436_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175833$10453 + cell $add $add$libresoc.v:177141$10437 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -356993,10 +328363,10 @@ module \popcount parameter \Y_WIDTH 7 connect \A { 2'00 \pop_5_2 } connect \B { 2'00 \pop_5_3 } - connect \Y $add$libresoc.v:175833$10453_Y + connect \Y $add$libresoc.v:177141$10437_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175834$10454 + cell $add $add$libresoc.v:177142$10438 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -357004,10 +328374,10 @@ module \popcount parameter \Y_WIDTH 8 connect \A { 2'00 \pop_6_0 } connect \B { 2'00 \pop_6_1 } - connect \Y $add$libresoc.v:175834$10454_Y + connect \Y $add$libresoc.v:177142$10438_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175845$10473 + cell $add $add$libresoc.v:177153$10457 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357015,10 +328385,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [12] } connect \B { 2'00 \a [13] } - connect \Y $add$libresoc.v:175845$10473_Y + connect \Y $add$libresoc.v:177153$10457_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175849$10480 + cell $add $add$libresoc.v:177157$10464 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357026,10 +328396,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [14] } connect \B { 2'00 \a [15] } - connect \Y $add$libresoc.v:175849$10480_Y + connect \Y $add$libresoc.v:177157$10464_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175850$10481 + cell $add $add$libresoc.v:177158$10465 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357037,10 +328407,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [16] } connect \B { 2'00 \a [17] } - connect \Y $add$libresoc.v:175850$10481_Y + connect \Y $add$libresoc.v:177158$10465_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175851$10482 + cell $add $add$libresoc.v:177159$10466 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357048,10 +328418,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [0] } connect \B { 2'00 \a [1] } - connect \Y $add$libresoc.v:175851$10482_Y + connect \Y $add$libresoc.v:177159$10466_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175852$10483 + cell $add $add$libresoc.v:177160$10467 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357059,10 +328429,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [18] } connect \B { 2'00 \a [19] } - connect \Y $add$libresoc.v:175852$10483_Y + connect \Y $add$libresoc.v:177160$10467_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175853$10484 + cell $add $add$libresoc.v:177161$10468 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357070,10 +328440,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [20] } connect \B { 2'00 \a [21] } - connect \Y $add$libresoc.v:175853$10484_Y + connect \Y $add$libresoc.v:177161$10468_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175854$10485 + cell $add $add$libresoc.v:177162$10469 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357081,10 +328451,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [22] } connect \B { 2'00 \a [23] } - connect \Y $add$libresoc.v:175854$10485_Y + connect \Y $add$libresoc.v:177162$10469_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175855$10486 + cell $add $add$libresoc.v:177163$10470 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357092,10 +328462,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [24] } connect \B { 2'00 \a [25] } - connect \Y $add$libresoc.v:175855$10486_Y + connect \Y $add$libresoc.v:177163$10470_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175856$10487 + cell $add $add$libresoc.v:177164$10471 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357103,10 +328473,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [26] } connect \B { 2'00 \a [27] } - connect \Y $add$libresoc.v:175856$10487_Y + connect \Y $add$libresoc.v:177164$10471_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175857$10488 + cell $add $add$libresoc.v:177165$10472 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357114,10 +328484,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [28] } connect \B { 2'00 \a [29] } - connect \Y $add$libresoc.v:175857$10488_Y + connect \Y $add$libresoc.v:177165$10472_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175858$10489 + cell $add $add$libresoc.v:177166$10473 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357125,10 +328495,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [30] } connect \B { 2'00 \a [31] } - connect \Y $add$libresoc.v:175858$10489_Y + connect \Y $add$libresoc.v:177166$10473_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175859$10490 + cell $add $add$libresoc.v:177167$10474 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357136,10 +328506,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [32] } connect \B { 2'00 \a [33] } - connect \Y $add$libresoc.v:175859$10490_Y + connect \Y $add$libresoc.v:177167$10474_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175860$10491 + cell $add $add$libresoc.v:177168$10475 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357147,10 +328517,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [34] } connect \B { 2'00 \a [35] } - connect \Y $add$libresoc.v:175860$10491_Y + connect \Y $add$libresoc.v:177168$10475_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175861$10492 + cell $add $add$libresoc.v:177169$10476 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357158,10 +328528,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [36] } connect \B { 2'00 \a [37] } - connect \Y $add$libresoc.v:175861$10492_Y + connect \Y $add$libresoc.v:177169$10476_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175862$10493 + cell $add $add$libresoc.v:177170$10477 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357169,10 +328539,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [2] } connect \B { 2'00 \a [3] } - connect \Y $add$libresoc.v:175862$10493_Y + connect \Y $add$libresoc.v:177170$10477_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175863$10494 + cell $add $add$libresoc.v:177171$10478 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357180,10 +328550,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [38] } connect \B { 2'00 \a [39] } - connect \Y $add$libresoc.v:175863$10494_Y + connect \Y $add$libresoc.v:177171$10478_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175864$10495 + cell $add $add$libresoc.v:177172$10479 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357191,10 +328561,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [40] } connect \B { 2'00 \a [41] } - connect \Y $add$libresoc.v:175864$10495_Y + connect \Y $add$libresoc.v:177172$10479_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175865$10496 + cell $add $add$libresoc.v:177173$10480 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357202,10 +328572,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [42] } connect \B { 2'00 \a [43] } - connect \Y $add$libresoc.v:175865$10496_Y + connect \Y $add$libresoc.v:177173$10480_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175866$10497 + cell $add $add$libresoc.v:177174$10481 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357213,10 +328583,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [44] } connect \B { 2'00 \a [45] } - connect \Y $add$libresoc.v:175866$10497_Y + connect \Y $add$libresoc.v:177174$10481_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175867$10498 + cell $add $add$libresoc.v:177175$10482 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357224,10 +328594,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [46] } connect \B { 2'00 \a [47] } - connect \Y $add$libresoc.v:175867$10498_Y + connect \Y $add$libresoc.v:177175$10482_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175868$10499 + cell $add $add$libresoc.v:177176$10483 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357235,10 +328605,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [48] } connect \B { 2'00 \a [49] } - connect \Y $add$libresoc.v:175868$10499_Y + connect \Y $add$libresoc.v:177176$10483_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175869$10500 + cell $add $add$libresoc.v:177177$10484 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357246,10 +328616,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [50] } connect \B { 2'00 \a [51] } - connect \Y $add$libresoc.v:175869$10500_Y + connect \Y $add$libresoc.v:177177$10484_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175870$10501 + cell $add $add$libresoc.v:177178$10485 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357257,10 +328627,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [52] } connect \B { 2'00 \a [53] } - connect \Y $add$libresoc.v:175870$10501_Y + connect \Y $add$libresoc.v:177178$10485_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175871$10502 + cell $add $add$libresoc.v:177179$10486 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357268,10 +328638,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [54] } connect \B { 2'00 \a [55] } - connect \Y $add$libresoc.v:175871$10502_Y + connect \Y $add$libresoc.v:177179$10486_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175872$10503 + cell $add $add$libresoc.v:177180$10487 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357279,10 +328649,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [56] } connect \B { 2'00 \a [57] } - connect \Y $add$libresoc.v:175872$10503_Y + connect \Y $add$libresoc.v:177180$10487_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175873$10504 + cell $add $add$libresoc.v:177181$10488 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357290,10 +328660,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [4] } connect \B { 2'00 \a [5] } - connect \Y $add$libresoc.v:175873$10504_Y + connect \Y $add$libresoc.v:177181$10488_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175874$10505 + cell $add $add$libresoc.v:177182$10489 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357301,10 +328671,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [58] } connect \B { 2'00 \a [59] } - connect \Y $add$libresoc.v:175874$10505_Y + connect \Y $add$libresoc.v:177182$10489_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175875$10506 + cell $add $add$libresoc.v:177183$10490 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357312,10 +328682,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [60] } connect \B { 2'00 \a [61] } - connect \Y $add$libresoc.v:175875$10506_Y + connect \Y $add$libresoc.v:177183$10490_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175876$10507 + cell $add $add$libresoc.v:177184$10491 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -357323,10 +328693,10 @@ module \popcount parameter \Y_WIDTH 3 connect \A { 2'00 \a [62] } connect \B { 2'00 \a [63] } - connect \Y $add$libresoc.v:175876$10507_Y + connect \Y $add$libresoc.v:177184$10491_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $add$libresoc.v:175877$10508 + cell $add $add$libresoc.v:177185$10492 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -357334,10 +328704,10 @@ module \popcount parameter \Y_WIDTH 4 connect \A { 2'00 \pop_2_0 } connect \B { 2'00 \pop_2_1 } - connect \Y $add$libresoc.v:175877$10508_Y + connect \Y $add$libresoc.v:177185$10492_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" - cell $eq $eq$libresoc.v:175835$10455 + cell $eq $eq$libresoc.v:177143$10439 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -357345,10 +328715,10 @@ module \popcount parameter \Y_WIDTH 1 connect \A \data_len connect \B 1'1 - connect \Y $eq$libresoc.v:175835$10455_Y + connect \Y $eq$libresoc.v:177143$10439_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:59" - cell $eq $eq$libresoc.v:175836$10456 + cell $eq $eq$libresoc.v:177144$10440 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -357356,199 +328726,199 @@ module \popcount parameter \Y_WIDTH 1 connect \A \data_len connect \B 3'100 - connect \Y $eq$libresoc.v:175836$10456_Y + connect \Y $eq$libresoc.v:177144$10440_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:175837$10457 + cell $pos $extend$libresoc.v:177145$10441 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_0 - connect \Y $extend$libresoc.v:175837$10457_Y + connect \Y $extend$libresoc.v:177145$10441_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:175838$10459 + cell $pos $extend$libresoc.v:177146$10443 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_1 - connect \Y $extend$libresoc.v:175838$10459_Y + connect \Y $extend$libresoc.v:177146$10443_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:175839$10461 + cell $pos $extend$libresoc.v:177147$10445 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_2 - connect \Y $extend$libresoc.v:175839$10461_Y + connect \Y $extend$libresoc.v:177147$10445_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:175840$10463 + cell $pos $extend$libresoc.v:177148$10447 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_3 - connect \Y $extend$libresoc.v:175840$10463_Y + connect \Y $extend$libresoc.v:177148$10447_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:175841$10465 + cell $pos $extend$libresoc.v:177149$10449 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_4 - connect \Y $extend$libresoc.v:175841$10465_Y + connect \Y $extend$libresoc.v:177149$10449_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:175842$10467 + cell $pos $extend$libresoc.v:177150$10451 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_5 - connect \Y $extend$libresoc.v:175842$10467_Y + connect \Y $extend$libresoc.v:177150$10451_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:175843$10469 + cell $pos $extend$libresoc.v:177151$10453 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_6 - connect \Y $extend$libresoc.v:175843$10469_Y + connect \Y $extend$libresoc.v:177151$10453_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:175844$10471 + cell $pos $extend$libresoc.v:177152$10455 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 8 connect \A \pop_4_7 - connect \Y $extend$libresoc.v:175844$10471_Y + connect \Y $extend$libresoc.v:177152$10455_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:175846$10474 + cell $pos $extend$libresoc.v:177154$10458 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 32 connect \A \pop_6_0 - connect \Y $extend$libresoc.v:175846$10474_Y + connect \Y $extend$libresoc.v:177154$10458_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:175847$10476 + cell $pos $extend$libresoc.v:177155$10460 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 32 connect \A \pop_6_1 - connect \Y $extend$libresoc.v:175847$10476_Y + connect \Y $extend$libresoc.v:177155$10460_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $extend$libresoc.v:175848$10478 + cell $pos $extend$libresoc.v:177156$10462 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 64 connect \A \pop_7_0 - connect \Y $extend$libresoc.v:175848$10478_Y + connect \Y $extend$libresoc.v:177156$10462_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:175837$10458 + cell $pos $pos$libresoc.v:177145$10442 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:175837$10457_Y - connect \Y $pos$libresoc.v:175837$10458_Y + connect \A $extend$libresoc.v:177145$10441_Y + connect \Y $pos$libresoc.v:177145$10442_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:175838$10460 + cell $pos $pos$libresoc.v:177146$10444 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:175838$10459_Y - connect \Y $pos$libresoc.v:175838$10460_Y + connect \A $extend$libresoc.v:177146$10443_Y + connect \Y $pos$libresoc.v:177146$10444_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:175839$10462 + cell $pos $pos$libresoc.v:177147$10446 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:175839$10461_Y - connect \Y $pos$libresoc.v:175839$10462_Y + connect \A $extend$libresoc.v:177147$10445_Y + connect \Y $pos$libresoc.v:177147$10446_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:175840$10464 + cell $pos $pos$libresoc.v:177148$10448 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:175840$10463_Y - connect \Y $pos$libresoc.v:175840$10464_Y + connect \A $extend$libresoc.v:177148$10447_Y + connect \Y $pos$libresoc.v:177148$10448_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:175841$10466 + cell $pos $pos$libresoc.v:177149$10450 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:175841$10465_Y - connect \Y $pos$libresoc.v:175841$10466_Y + connect \A $extend$libresoc.v:177149$10449_Y + connect \Y $pos$libresoc.v:177149$10450_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:175842$10468 + cell $pos $pos$libresoc.v:177150$10452 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:175842$10467_Y - connect \Y $pos$libresoc.v:175842$10468_Y + connect \A $extend$libresoc.v:177150$10451_Y + connect \Y $pos$libresoc.v:177150$10452_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:175843$10470 + cell $pos $pos$libresoc.v:177151$10454 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:175843$10469_Y - connect \Y $pos$libresoc.v:175843$10470_Y + connect \A $extend$libresoc.v:177151$10453_Y + connect \Y $pos$libresoc.v:177151$10454_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:175844$10472 + cell $pos $pos$libresoc.v:177152$10456 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 - connect \A $extend$libresoc.v:175844$10471_Y - connect \Y $pos$libresoc.v:175844$10472_Y + connect \A $extend$libresoc.v:177152$10455_Y + connect \Y $pos$libresoc.v:177152$10456_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:175846$10475 + cell $pos $pos$libresoc.v:177154$10459 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 32 - connect \A $extend$libresoc.v:175846$10474_Y - connect \Y $pos$libresoc.v:175846$10475_Y + connect \A $extend$libresoc.v:177154$10458_Y + connect \Y $pos$libresoc.v:177154$10459_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:175847$10477 + cell $pos $pos$libresoc.v:177155$10461 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 32 - connect \A $extend$libresoc.v:175847$10476_Y - connect \Y $pos$libresoc.v:175847$10477_Y + connect \A $extend$libresoc.v:177155$10460_Y + connect \Y $pos$libresoc.v:177155$10461_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $pos$libresoc.v:175848$10479 + cell $pos $pos$libresoc.v:177156$10463 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:175848$10478_Y - connect \Y $pos$libresoc.v:175848$10479_Y + connect \A $extend$libresoc.v:177156$10462_Y + connect \Y $pos$libresoc.v:177156$10463_Y end - attribute \src "libresoc.v:175390.7-175390.20" - process $proc$libresoc.v:175390$10510 + attribute \src "libresoc.v:176698.7-176698.20" + process $proc$libresoc.v:176698$10494 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:175878.3-175904.6" - process $proc$libresoc.v:175878$10509 + attribute \src "libresoc.v:177186.3-177212.6" + process $proc$libresoc.v:177186$10493 assign { } { } assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:175879.5-175879.29" + attribute \src "libresoc.v:177187.5-177187.29" switch \initial - attribute \src "libresoc.v:175879.9-175879.17" + attribute \src "libresoc.v:177187.9-177187.17" case 1'1 case end @@ -357578,82 +328948,82 @@ module \popcount sync always update \o $0\o[63:0] end - connect \$101 $add$libresoc.v:175802$10422_Y - connect \$104 $add$libresoc.v:175803$10423_Y - connect \$107 $add$libresoc.v:175804$10424_Y - connect \$110 $add$libresoc.v:175805$10425_Y - connect \$113 $add$libresoc.v:175806$10426_Y - connect \$116 $add$libresoc.v:175807$10427_Y - connect \$11 $add$libresoc.v:175808$10428_Y - connect \$119 $add$libresoc.v:175809$10429_Y - connect \$122 $add$libresoc.v:175810$10430_Y - connect \$125 $add$libresoc.v:175811$10431_Y - connect \$128 $add$libresoc.v:175812$10432_Y - connect \$131 $add$libresoc.v:175813$10433_Y - connect \$134 $add$libresoc.v:175814$10434_Y - connect \$137 $add$libresoc.v:175815$10435_Y - connect \$140 $add$libresoc.v:175816$10436_Y - connect \$143 $add$libresoc.v:175817$10437_Y - connect \$146 $add$libresoc.v:175818$10438_Y - connect \$14 $add$libresoc.v:175819$10439_Y - connect \$149 $add$libresoc.v:175820$10440_Y - connect \$152 $add$libresoc.v:175821$10441_Y - connect \$155 $add$libresoc.v:175822$10442_Y - connect \$158 $add$libresoc.v:175823$10443_Y - connect \$161 $add$libresoc.v:175824$10444_Y - connect \$164 $add$libresoc.v:175825$10445_Y - connect \$167 $add$libresoc.v:175826$10446_Y - connect \$170 $add$libresoc.v:175827$10447_Y - connect \$173 $add$libresoc.v:175828$10448_Y - connect \$176 $add$libresoc.v:175829$10449_Y - connect \$17 $add$libresoc.v:175830$10450_Y - connect \$179 $add$libresoc.v:175831$10451_Y - connect \$182 $add$libresoc.v:175832$10452_Y - connect \$185 $add$libresoc.v:175833$10453_Y - connect \$188 $add$libresoc.v:175834$10454_Y - connect \$190 $eq$libresoc.v:175835$10455_Y - connect \$192 $eq$libresoc.v:175836$10456_Y - connect \$194 $pos$libresoc.v:175837$10458_Y - connect \$196 $pos$libresoc.v:175838$10460_Y - connect \$198 $pos$libresoc.v:175839$10462_Y - connect \$200 $pos$libresoc.v:175840$10464_Y - connect \$202 $pos$libresoc.v:175841$10466_Y - connect \$204 $pos$libresoc.v:175842$10468_Y - connect \$206 $pos$libresoc.v:175843$10470_Y - connect \$208 $pos$libresoc.v:175844$10472_Y - connect \$20 $add$libresoc.v:175845$10473_Y - connect \$210 $pos$libresoc.v:175846$10475_Y - connect \$212 $pos$libresoc.v:175847$10477_Y - connect \$214 $pos$libresoc.v:175848$10479_Y - connect \$23 $add$libresoc.v:175849$10480_Y - connect \$26 $add$libresoc.v:175850$10481_Y - connect \$2 $add$libresoc.v:175851$10482_Y - connect \$29 $add$libresoc.v:175852$10483_Y - connect \$32 $add$libresoc.v:175853$10484_Y - connect \$35 $add$libresoc.v:175854$10485_Y - connect \$38 $add$libresoc.v:175855$10486_Y - connect \$41 $add$libresoc.v:175856$10487_Y - connect \$44 $add$libresoc.v:175857$10488_Y - connect \$47 $add$libresoc.v:175858$10489_Y - connect \$50 $add$libresoc.v:175859$10490_Y - connect \$53 $add$libresoc.v:175860$10491_Y - connect \$56 $add$libresoc.v:175861$10492_Y - connect \$5 $add$libresoc.v:175862$10493_Y - connect \$59 $add$libresoc.v:175863$10494_Y - connect \$62 $add$libresoc.v:175864$10495_Y - connect \$65 $add$libresoc.v:175865$10496_Y - connect \$68 $add$libresoc.v:175866$10497_Y - connect \$71 $add$libresoc.v:175867$10498_Y - connect \$74 $add$libresoc.v:175868$10499_Y - connect \$77 $add$libresoc.v:175869$10500_Y - connect \$80 $add$libresoc.v:175870$10501_Y - connect \$83 $add$libresoc.v:175871$10502_Y - connect \$86 $add$libresoc.v:175872$10503_Y - connect \$8 $add$libresoc.v:175873$10504_Y - connect \$89 $add$libresoc.v:175874$10505_Y - connect \$92 $add$libresoc.v:175875$10506_Y - connect \$95 $add$libresoc.v:175876$10507_Y - connect \$98 $add$libresoc.v:175877$10508_Y + connect \$101 $add$libresoc.v:177110$10406_Y + connect \$104 $add$libresoc.v:177111$10407_Y + connect \$107 $add$libresoc.v:177112$10408_Y + connect \$110 $add$libresoc.v:177113$10409_Y + connect \$113 $add$libresoc.v:177114$10410_Y + connect \$116 $add$libresoc.v:177115$10411_Y + connect \$11 $add$libresoc.v:177116$10412_Y + connect \$119 $add$libresoc.v:177117$10413_Y + connect \$122 $add$libresoc.v:177118$10414_Y + connect \$125 $add$libresoc.v:177119$10415_Y + connect \$128 $add$libresoc.v:177120$10416_Y + connect \$131 $add$libresoc.v:177121$10417_Y + connect \$134 $add$libresoc.v:177122$10418_Y + connect \$137 $add$libresoc.v:177123$10419_Y + connect \$140 $add$libresoc.v:177124$10420_Y + connect \$143 $add$libresoc.v:177125$10421_Y + connect \$146 $add$libresoc.v:177126$10422_Y + connect \$14 $add$libresoc.v:177127$10423_Y + connect \$149 $add$libresoc.v:177128$10424_Y + connect \$152 $add$libresoc.v:177129$10425_Y + connect \$155 $add$libresoc.v:177130$10426_Y + connect \$158 $add$libresoc.v:177131$10427_Y + connect \$161 $add$libresoc.v:177132$10428_Y + connect \$164 $add$libresoc.v:177133$10429_Y + connect \$167 $add$libresoc.v:177134$10430_Y + connect \$170 $add$libresoc.v:177135$10431_Y + connect \$173 $add$libresoc.v:177136$10432_Y + connect \$176 $add$libresoc.v:177137$10433_Y + connect \$17 $add$libresoc.v:177138$10434_Y + connect \$179 $add$libresoc.v:177139$10435_Y + connect \$182 $add$libresoc.v:177140$10436_Y + connect \$185 $add$libresoc.v:177141$10437_Y + connect \$188 $add$libresoc.v:177142$10438_Y + connect \$190 $eq$libresoc.v:177143$10439_Y + connect \$192 $eq$libresoc.v:177144$10440_Y + connect \$194 $pos$libresoc.v:177145$10442_Y + connect \$196 $pos$libresoc.v:177146$10444_Y + connect \$198 $pos$libresoc.v:177147$10446_Y + connect \$200 $pos$libresoc.v:177148$10448_Y + connect \$202 $pos$libresoc.v:177149$10450_Y + connect \$204 $pos$libresoc.v:177150$10452_Y + connect \$206 $pos$libresoc.v:177151$10454_Y + connect \$208 $pos$libresoc.v:177152$10456_Y + connect \$20 $add$libresoc.v:177153$10457_Y + connect \$210 $pos$libresoc.v:177154$10459_Y + connect \$212 $pos$libresoc.v:177155$10461_Y + connect \$214 $pos$libresoc.v:177156$10463_Y + connect \$23 $add$libresoc.v:177157$10464_Y + connect \$26 $add$libresoc.v:177158$10465_Y + connect \$2 $add$libresoc.v:177159$10466_Y + connect \$29 $add$libresoc.v:177160$10467_Y + connect \$32 $add$libresoc.v:177161$10468_Y + connect \$35 $add$libresoc.v:177162$10469_Y + connect \$38 $add$libresoc.v:177163$10470_Y + connect \$41 $add$libresoc.v:177164$10471_Y + connect \$44 $add$libresoc.v:177165$10472_Y + connect \$47 $add$libresoc.v:177166$10473_Y + connect \$50 $add$libresoc.v:177167$10474_Y + connect \$53 $add$libresoc.v:177168$10475_Y + connect \$56 $add$libresoc.v:177169$10476_Y + connect \$5 $add$libresoc.v:177170$10477_Y + connect \$59 $add$libresoc.v:177171$10478_Y + connect \$62 $add$libresoc.v:177172$10479_Y + connect \$65 $add$libresoc.v:177173$10480_Y + connect \$68 $add$libresoc.v:177174$10481_Y + connect \$71 $add$libresoc.v:177175$10482_Y + connect \$74 $add$libresoc.v:177176$10483_Y + connect \$77 $add$libresoc.v:177177$10484_Y + connect \$80 $add$libresoc.v:177178$10485_Y + connect \$83 $add$libresoc.v:177179$10486_Y + connect \$86 $add$libresoc.v:177180$10487_Y + connect \$8 $add$libresoc.v:177181$10488_Y + connect \$89 $add$libresoc.v:177182$10489_Y + connect \$92 $add$libresoc.v:177183$10490_Y + connect \$95 $add$libresoc.v:177184$10491_Y + connect \$98 $add$libresoc.v:177185$10492_Y connect \$1 \$2 connect \$4 \$5 connect \$7 \$8 @@ -357781,43 +329151,43 @@ module \popcount connect \pop_2_1 \$5 [1:0] connect \pop_2_0 \$2 [1:0] end -attribute \src "libresoc.v:176035.1-176119.10" +attribute \src "libresoc.v:177343.1-177427.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_in.ppick" attribute \generator "nMigen" module \ppick - attribute \src "libresoc.v:176092.17-176092.91" - wire $not$libresoc.v:176092$10511_Y - attribute \src "libresoc.v:176094.18-176094.93" - wire $not$libresoc.v:176094$10513_Y - attribute \src "libresoc.v:176096.18-176096.93" - wire $not$libresoc.v:176096$10515_Y - attribute \src "libresoc.v:176097.17-176097.138" - wire width 8 $not$libresoc.v:176097$10516_Y - attribute \src "libresoc.v:176099.18-176099.93" - wire $not$libresoc.v:176099$10518_Y - attribute \src "libresoc.v:176101.18-176101.93" - wire $not$libresoc.v:176101$10520_Y - attribute \src "libresoc.v:176103.18-176103.93" - wire $not$libresoc.v:176103$10522_Y - attribute \src "libresoc.v:176106.17-176106.91" - wire $not$libresoc.v:176106$10525_Y - attribute \src "libresoc.v:176093.18-176093.116" - wire $reduce_or$libresoc.v:176093$10512_Y - attribute \src "libresoc.v:176095.18-176095.122" - wire $reduce_or$libresoc.v:176095$10514_Y - attribute \src "libresoc.v:176098.18-176098.128" - wire $reduce_or$libresoc.v:176098$10517_Y - attribute \src "libresoc.v:176100.18-176100.134" - wire $reduce_or$libresoc.v:176100$10519_Y - attribute \src "libresoc.v:176102.18-176102.140" - wire $reduce_or$libresoc.v:176102$10521_Y - attribute \src "libresoc.v:176104.18-176104.90" - wire $reduce_or$libresoc.v:176104$10523_Y - attribute \src "libresoc.v:176105.17-176105.103" - wire $reduce_or$libresoc.v:176105$10524_Y - attribute \src "libresoc.v:176107.17-176107.109" - wire $reduce_or$libresoc.v:176107$10526_Y + attribute \src "libresoc.v:177400.17-177400.91" + wire $not$libresoc.v:177400$10495_Y + attribute \src "libresoc.v:177402.18-177402.93" + wire $not$libresoc.v:177402$10497_Y + attribute \src "libresoc.v:177404.18-177404.93" + wire $not$libresoc.v:177404$10499_Y + attribute \src "libresoc.v:177405.17-177405.138" + wire width 8 $not$libresoc.v:177405$10500_Y + attribute \src "libresoc.v:177407.18-177407.93" + wire $not$libresoc.v:177407$10502_Y + attribute \src "libresoc.v:177409.18-177409.93" + wire $not$libresoc.v:177409$10504_Y + attribute \src "libresoc.v:177411.18-177411.93" + wire $not$libresoc.v:177411$10506_Y + attribute \src "libresoc.v:177414.17-177414.91" + wire $not$libresoc.v:177414$10509_Y + attribute \src "libresoc.v:177401.18-177401.116" + wire $reduce_or$libresoc.v:177401$10496_Y + attribute \src "libresoc.v:177403.18-177403.122" + wire $reduce_or$libresoc.v:177403$10498_Y + attribute \src "libresoc.v:177406.18-177406.128" + wire $reduce_or$libresoc.v:177406$10501_Y + attribute \src "libresoc.v:177408.18-177408.134" + wire $reduce_or$libresoc.v:177408$10503_Y + attribute \src "libresoc.v:177410.18-177410.140" + wire $reduce_or$libresoc.v:177410$10505_Y + attribute \src "libresoc.v:177412.18-177412.90" + wire $reduce_or$libresoc.v:177412$10507_Y + attribute \src "libresoc.v:177413.17-177413.103" + wire $reduce_or$libresoc.v:177413$10508_Y + attribute \src "libresoc.v:177415.17-177415.109" + wire $reduce_or$libresoc.v:177415$10510_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -357875,149 +329245,149 @@ module \ppick attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176092$10511 + cell $not $not$libresoc.v:177400$10495 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:176092$10511_Y + connect \Y $not$libresoc.v:177400$10495_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176094$10513 + cell $not $not$libresoc.v:177402$10497 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:176094$10513_Y + connect \Y $not$libresoc.v:177402$10497_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176096$10515 + cell $not $not$libresoc.v:177404$10499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:176096$10515_Y + connect \Y $not$libresoc.v:177404$10499_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176097$10516 + cell $not $not$libresoc.v:177405$10500 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:176097$10516_Y + connect \Y $not$libresoc.v:177405$10500_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176099$10518 + cell $not $not$libresoc.v:177407$10502 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:176099$10518_Y + connect \Y $not$libresoc.v:177407$10502_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176101$10520 + cell $not $not$libresoc.v:177409$10504 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:176101$10520_Y + connect \Y $not$libresoc.v:177409$10504_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176103$10522 + cell $not $not$libresoc.v:177411$10506 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:176103$10522_Y + connect \Y $not$libresoc.v:177411$10506_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176106$10525 + cell $not $not$libresoc.v:177414$10509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:176106$10525_Y + connect \Y $not$libresoc.v:177414$10509_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176093$10512 + cell $reduce_or $reduce_or$libresoc.v:177401$10496 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:176093$10512_Y + connect \Y $reduce_or$libresoc.v:177401$10496_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176095$10514 + cell $reduce_or $reduce_or$libresoc.v:177403$10498 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:176095$10514_Y + connect \Y $reduce_or$libresoc.v:177403$10498_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176098$10517 + cell $reduce_or $reduce_or$libresoc.v:177406$10501 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:176098$10517_Y + connect \Y $reduce_or$libresoc.v:177406$10501_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176100$10519 + cell $reduce_or $reduce_or$libresoc.v:177408$10503 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:176100$10519_Y + connect \Y $reduce_or$libresoc.v:177408$10503_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176102$10521 + cell $reduce_or $reduce_or$libresoc.v:177410$10505 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:176102$10521_Y + connect \Y $reduce_or$libresoc.v:177410$10505_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176104$10523 + cell $reduce_or $reduce_or$libresoc.v:177412$10507 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:176104$10523_Y + connect \Y $reduce_or$libresoc.v:177412$10507_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176105$10524 + cell $reduce_or $reduce_or$libresoc.v:177413$10508 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:176105$10524_Y + connect \Y $reduce_or$libresoc.v:177413$10508_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176107$10526 + cell $reduce_or $reduce_or$libresoc.v:177415$10510 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:176107$10526_Y - end - connect \$7 $not$libresoc.v:176092$10511_Y - connect \$12 $reduce_or$libresoc.v:176093$10512_Y - connect \$11 $not$libresoc.v:176094$10513_Y - connect \$16 $reduce_or$libresoc.v:176095$10514_Y - connect \$15 $not$libresoc.v:176096$10515_Y - connect \$1 $not$libresoc.v:176097$10516_Y - connect \$20 $reduce_or$libresoc.v:176098$10517_Y - connect \$19 $not$libresoc.v:176099$10518_Y - connect \$24 $reduce_or$libresoc.v:176100$10519_Y - connect \$23 $not$libresoc.v:176101$10520_Y - connect \$28 $reduce_or$libresoc.v:176102$10521_Y - connect \$27 $not$libresoc.v:176103$10522_Y - connect \$31 $reduce_or$libresoc.v:176104$10523_Y - connect \$4 $reduce_or$libresoc.v:176105$10524_Y - connect \$3 $not$libresoc.v:176106$10525_Y - connect \$8 $reduce_or$libresoc.v:176107$10526_Y + connect \Y $reduce_or$libresoc.v:177415$10510_Y + end + connect \$7 $not$libresoc.v:177400$10495_Y + connect \$12 $reduce_or$libresoc.v:177401$10496_Y + connect \$11 $not$libresoc.v:177402$10497_Y + connect \$16 $reduce_or$libresoc.v:177403$10498_Y + connect \$15 $not$libresoc.v:177404$10499_Y + connect \$1 $not$libresoc.v:177405$10500_Y + connect \$20 $reduce_or$libresoc.v:177406$10501_Y + connect \$19 $not$libresoc.v:177407$10502_Y + connect \$24 $reduce_or$libresoc.v:177408$10503_Y + connect \$23 $not$libresoc.v:177409$10504_Y + connect \$28 $reduce_or$libresoc.v:177410$10505_Y + connect \$27 $not$libresoc.v:177411$10506_Y + connect \$31 $reduce_or$libresoc.v:177412$10507_Y + connect \$4 $reduce_or$libresoc.v:177413$10508_Y + connect \$3 $not$libresoc.v:177414$10509_Y + connect \$8 $reduce_or$libresoc.v:177415$10510_Y connect \en_o \$31 connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } connect \t7 \$27 @@ -358030,43 +329400,43 @@ module \ppick connect \t0 \i [7] connect \ni \$1 end -attribute \src "libresoc.v:176123.1-176207.10" +attribute \src "libresoc.v:177431.1-177515.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_cr_out.ppick" attribute \generator "nMigen" module \ppick$175 - attribute \src "libresoc.v:176180.17-176180.91" - wire $not$libresoc.v:176180$10527_Y - attribute \src "libresoc.v:176182.18-176182.93" - wire $not$libresoc.v:176182$10529_Y - attribute \src "libresoc.v:176184.18-176184.93" - wire $not$libresoc.v:176184$10531_Y - attribute \src "libresoc.v:176185.17-176185.138" - wire width 8 $not$libresoc.v:176185$10532_Y - attribute \src "libresoc.v:176187.18-176187.93" - wire $not$libresoc.v:176187$10534_Y - attribute \src "libresoc.v:176189.18-176189.93" - wire $not$libresoc.v:176189$10536_Y - attribute \src "libresoc.v:176191.18-176191.93" - wire $not$libresoc.v:176191$10538_Y - attribute \src "libresoc.v:176194.17-176194.91" - wire $not$libresoc.v:176194$10541_Y - attribute \src "libresoc.v:176181.18-176181.116" - wire $reduce_or$libresoc.v:176181$10528_Y - attribute \src "libresoc.v:176183.18-176183.122" - wire $reduce_or$libresoc.v:176183$10530_Y - attribute \src "libresoc.v:176186.18-176186.128" - wire $reduce_or$libresoc.v:176186$10533_Y - attribute \src "libresoc.v:176188.18-176188.134" - wire $reduce_or$libresoc.v:176188$10535_Y - attribute \src "libresoc.v:176190.18-176190.140" - wire $reduce_or$libresoc.v:176190$10537_Y - attribute \src "libresoc.v:176192.18-176192.90" - wire $reduce_or$libresoc.v:176192$10539_Y - attribute \src "libresoc.v:176193.17-176193.103" - wire $reduce_or$libresoc.v:176193$10540_Y - attribute \src "libresoc.v:176195.17-176195.109" - wire $reduce_or$libresoc.v:176195$10542_Y + attribute \src "libresoc.v:177488.17-177488.91" + wire $not$libresoc.v:177488$10511_Y + attribute \src "libresoc.v:177490.18-177490.93" + wire $not$libresoc.v:177490$10513_Y + attribute \src "libresoc.v:177492.18-177492.93" + wire $not$libresoc.v:177492$10515_Y + attribute \src "libresoc.v:177493.17-177493.138" + wire width 8 $not$libresoc.v:177493$10516_Y + attribute \src "libresoc.v:177495.18-177495.93" + wire $not$libresoc.v:177495$10518_Y + attribute \src "libresoc.v:177497.18-177497.93" + wire $not$libresoc.v:177497$10520_Y + attribute \src "libresoc.v:177499.18-177499.93" + wire $not$libresoc.v:177499$10522_Y + attribute \src "libresoc.v:177502.17-177502.91" + wire $not$libresoc.v:177502$10525_Y + attribute \src "libresoc.v:177489.18-177489.116" + wire $reduce_or$libresoc.v:177489$10512_Y + attribute \src "libresoc.v:177491.18-177491.122" + wire $reduce_or$libresoc.v:177491$10514_Y + attribute \src "libresoc.v:177494.18-177494.128" + wire $reduce_or$libresoc.v:177494$10517_Y + attribute \src "libresoc.v:177496.18-177496.134" + wire $reduce_or$libresoc.v:177496$10519_Y + attribute \src "libresoc.v:177498.18-177498.140" + wire $reduce_or$libresoc.v:177498$10521_Y + attribute \src "libresoc.v:177500.18-177500.90" + wire $reduce_or$libresoc.v:177500$10523_Y + attribute \src "libresoc.v:177501.17-177501.103" + wire $reduce_or$libresoc.v:177501$10524_Y + attribute \src "libresoc.v:177503.17-177503.109" + wire $reduce_or$libresoc.v:177503$10526_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -358124,149 +329494,149 @@ module \ppick$175 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176180$10527 + cell $not $not$libresoc.v:177488$10511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:176180$10527_Y + connect \Y $not$libresoc.v:177488$10511_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176182$10529 + cell $not $not$libresoc.v:177490$10513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:176182$10529_Y + connect \Y $not$libresoc.v:177490$10513_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176184$10531 + cell $not $not$libresoc.v:177492$10515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:176184$10531_Y + connect \Y $not$libresoc.v:177492$10515_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176185$10532 + cell $not $not$libresoc.v:177493$10516 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $not$libresoc.v:176185$10532_Y + connect \Y $not$libresoc.v:177493$10516_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176187$10534 + cell $not $not$libresoc.v:177495$10518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:176187$10534_Y + connect \Y $not$libresoc.v:177495$10518_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176189$10536 + cell $not $not$libresoc.v:177497$10520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:176189$10536_Y + connect \Y $not$libresoc.v:177497$10520_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176191$10538 + cell $not $not$libresoc.v:177499$10522 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:176191$10538_Y + connect \Y $not$libresoc.v:177499$10522_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176194$10541 + cell $not $not$libresoc.v:177502$10525 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:176194$10541_Y + connect \Y $not$libresoc.v:177502$10525_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176181$10528 + cell $reduce_or $reduce_or$libresoc.v:177489$10512 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $reduce_or$libresoc.v:176181$10528_Y + connect \Y $reduce_or$libresoc.v:177489$10512_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176183$10530 + cell $reduce_or $reduce_or$libresoc.v:177491$10514 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $reduce_or$libresoc.v:176183$10530_Y + connect \Y $reduce_or$libresoc.v:177491$10514_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176186$10533 + cell $reduce_or $reduce_or$libresoc.v:177494$10517 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $reduce_or$libresoc.v:176186$10533_Y + connect \Y $reduce_or$libresoc.v:177494$10517_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176188$10535 + cell $reduce_or $reduce_or$libresoc.v:177496$10519 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $reduce_or$libresoc.v:176188$10535_Y + connect \Y $reduce_or$libresoc.v:177496$10519_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176190$10537 + cell $reduce_or $reduce_or$libresoc.v:177498$10521 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $reduce_or$libresoc.v:176190$10537_Y + connect \Y $reduce_or$libresoc.v:177498$10521_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176192$10539 + cell $reduce_or $reduce_or$libresoc.v:177500$10523 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:176192$10539_Y + connect \Y $reduce_or$libresoc.v:177500$10523_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176193$10540 + cell $reduce_or $reduce_or$libresoc.v:177501$10524 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [7] \ni [1] } - connect \Y $reduce_or$libresoc.v:176193$10540_Y + connect \Y $reduce_or$libresoc.v:177501$10524_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176195$10542 + cell $reduce_or $reduce_or$libresoc.v:177503$10526 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [6] \i [7] \ni [2] } - connect \Y $reduce_or$libresoc.v:176195$10542_Y - end - connect \$7 $not$libresoc.v:176180$10527_Y - connect \$12 $reduce_or$libresoc.v:176181$10528_Y - connect \$11 $not$libresoc.v:176182$10529_Y - connect \$16 $reduce_or$libresoc.v:176183$10530_Y - connect \$15 $not$libresoc.v:176184$10531_Y - connect \$1 $not$libresoc.v:176185$10532_Y - connect \$20 $reduce_or$libresoc.v:176186$10533_Y - connect \$19 $not$libresoc.v:176187$10534_Y - connect \$24 $reduce_or$libresoc.v:176188$10535_Y - connect \$23 $not$libresoc.v:176189$10536_Y - connect \$28 $reduce_or$libresoc.v:176190$10537_Y - connect \$27 $not$libresoc.v:176191$10538_Y - connect \$31 $reduce_or$libresoc.v:176192$10539_Y - connect \$4 $reduce_or$libresoc.v:176193$10540_Y - connect \$3 $not$libresoc.v:176194$10541_Y - connect \$8 $reduce_or$libresoc.v:176195$10542_Y + connect \Y $reduce_or$libresoc.v:177503$10526_Y + end + connect \$7 $not$libresoc.v:177488$10511_Y + connect \$12 $reduce_or$libresoc.v:177489$10512_Y + connect \$11 $not$libresoc.v:177490$10513_Y + connect \$16 $reduce_or$libresoc.v:177491$10514_Y + connect \$15 $not$libresoc.v:177492$10515_Y + connect \$1 $not$libresoc.v:177493$10516_Y + connect \$20 $reduce_or$libresoc.v:177494$10517_Y + connect \$19 $not$libresoc.v:177495$10518_Y + connect \$24 $reduce_or$libresoc.v:177496$10519_Y + connect \$23 $not$libresoc.v:177497$10520_Y + connect \$28 $reduce_or$libresoc.v:177498$10521_Y + connect \$27 $not$libresoc.v:177499$10522_Y + connect \$31 $reduce_or$libresoc.v:177500$10523_Y + connect \$4 $reduce_or$libresoc.v:177501$10524_Y + connect \$3 $not$libresoc.v:177502$10525_Y + connect \$8 $reduce_or$libresoc.v:177503$10526_Y connect \en_o \$31 connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } connect \t7 \$27 @@ -358279,19 +329649,19 @@ module \ppick$175 connect \t0 \i [7] connect \ni \$1 end -attribute \src "libresoc.v:176211.1-176241.10" +attribute \src "libresoc.v:177519.1-177549.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_a" attribute \generator "nMigen" module \rdpick_CR_cr_a - attribute \src "libresoc.v:176232.17-176232.89" - wire width 2 $not$libresoc.v:176232$10543_Y - attribute \src "libresoc.v:176234.17-176234.91" - wire $not$libresoc.v:176234$10545_Y - attribute \src "libresoc.v:176233.17-176233.103" - wire $reduce_or$libresoc.v:176233$10544_Y - attribute \src "libresoc.v:176235.17-176235.89" - wire $reduce_or$libresoc.v:176235$10546_Y + attribute \src "libresoc.v:177540.17-177540.89" + wire width 2 $not$libresoc.v:177540$10527_Y + attribute \src "libresoc.v:177542.17-177542.91" + wire $not$libresoc.v:177542$10529_Y + attribute \src "libresoc.v:177541.17-177541.103" + wire $reduce_or$libresoc.v:177541$10528_Y + attribute \src "libresoc.v:177543.17-177543.89" + wire $reduce_or$libresoc.v:177543$10530_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -358313,56 +329683,56 @@ module \rdpick_CR_cr_a attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176232$10543 + cell $not $not$libresoc.v:177540$10527 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \i - connect \Y $not$libresoc.v:176232$10543_Y + connect \Y $not$libresoc.v:177540$10527_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176234$10545 + cell $not $not$libresoc.v:177542$10529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:176234$10545_Y + connect \Y $not$libresoc.v:177542$10529_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176233$10544 + cell $reduce_or $reduce_or$libresoc.v:177541$10528 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:176233$10544_Y + connect \Y $reduce_or$libresoc.v:177541$10528_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176235$10546 + cell $reduce_or $reduce_or$libresoc.v:177543$10530 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:176235$10546_Y + connect \Y $reduce_or$libresoc.v:177543$10530_Y end - connect \$1 $not$libresoc.v:176232$10543_Y - connect \$4 $reduce_or$libresoc.v:176233$10544_Y - connect \$3 $not$libresoc.v:176234$10545_Y - connect \$7 $reduce_or$libresoc.v:176235$10546_Y + connect \$1 $not$libresoc.v:177540$10527_Y + connect \$4 $reduce_or$libresoc.v:177541$10528_Y + connect \$3 $not$libresoc.v:177542$10529_Y + connect \$7 $reduce_or$libresoc.v:177543$10530_Y connect \en_o \$7 connect \o { \t1 \t0 } connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:176245.1-176266.10" +attribute \src "libresoc.v:177553.1-177574.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_b" attribute \generator "nMigen" module \rdpick_CR_cr_b - attribute \src "libresoc.v:176260.17-176260.89" - wire $not$libresoc.v:176260$10547_Y - attribute \src "libresoc.v:176261.17-176261.89" - wire $reduce_or$libresoc.v:176261$10548_Y + attribute \src "libresoc.v:177568.17-177568.89" + wire $not$libresoc.v:177568$10531_Y + attribute \src "libresoc.v:177569.17-177569.89" + wire $reduce_or$libresoc.v:177569$10532_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -358378,37 +329748,37 @@ module \rdpick_CR_cr_b attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176260$10547 + cell $not $not$libresoc.v:177568$10531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:176260$10547_Y + connect \Y $not$libresoc.v:177568$10531_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176261$10548 + cell $reduce_or $reduce_or$libresoc.v:177569$10532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:176261$10548_Y + connect \Y $reduce_or$libresoc.v:177569$10532_Y end - connect \$1 $not$libresoc.v:176260$10547_Y - connect \$3 $reduce_or$libresoc.v:176261$10548_Y + connect \$1 $not$libresoc.v:177568$10531_Y + connect \$3 $reduce_or$libresoc.v:177569$10532_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:176270.1-176291.10" +attribute \src "libresoc.v:177578.1-177599.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_cr_c" attribute \generator "nMigen" module \rdpick_CR_cr_c - attribute \src "libresoc.v:176285.17-176285.89" - wire $not$libresoc.v:176285$10549_Y - attribute \src "libresoc.v:176286.17-176286.89" - wire $reduce_or$libresoc.v:176286$10550_Y + attribute \src "libresoc.v:177593.17-177593.89" + wire $not$libresoc.v:177593$10533_Y + attribute \src "libresoc.v:177594.17-177594.89" + wire $reduce_or$libresoc.v:177594$10534_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -358424,37 +329794,37 @@ module \rdpick_CR_cr_c attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176285$10549 + cell $not $not$libresoc.v:177593$10533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:176285$10549_Y + connect \Y $not$libresoc.v:177593$10533_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176286$10550 + cell $reduce_or $reduce_or$libresoc.v:177594$10534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:176286$10550_Y + connect \Y $reduce_or$libresoc.v:177594$10534_Y end - connect \$1 $not$libresoc.v:176285$10549_Y - connect \$3 $reduce_or$libresoc.v:176286$10550_Y + connect \$1 $not$libresoc.v:177593$10533_Y + connect \$3 $reduce_or$libresoc.v:177594$10534_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:176295.1-176316.10" +attribute \src "libresoc.v:177603.1-177624.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_CR_full_cr" attribute \generator "nMigen" module \rdpick_CR_full_cr - attribute \src "libresoc.v:176310.17-176310.89" - wire $not$libresoc.v:176310$10551_Y - attribute \src "libresoc.v:176311.17-176311.89" - wire $reduce_or$libresoc.v:176311$10552_Y + attribute \src "libresoc.v:177618.17-177618.89" + wire $not$libresoc.v:177618$10535_Y + attribute \src "libresoc.v:177619.17-177619.89" + wire $reduce_or$libresoc.v:177619$10536_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -358470,45 +329840,45 @@ module \rdpick_CR_full_cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176310$10551 + cell $not $not$libresoc.v:177618$10535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:176310$10551_Y + connect \Y $not$libresoc.v:177618$10535_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176311$10552 + cell $reduce_or $reduce_or$libresoc.v:177619$10536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:176311$10552_Y + connect \Y $reduce_or$libresoc.v:177619$10536_Y end - connect \$1 $not$libresoc.v:176310$10551_Y - connect \$3 $reduce_or$libresoc.v:176311$10552_Y + connect \$1 $not$libresoc.v:177618$10535_Y + connect \$3 $reduce_or$libresoc.v:177619$10536_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:176320.1-176359.10" +attribute \src "libresoc.v:177628.1-177667.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_FAST_fast1" attribute \generator "nMigen" module \rdpick_FAST_fast1 - attribute \src "libresoc.v:176347.17-176347.91" - wire $not$libresoc.v:176347$10553_Y - attribute \src "libresoc.v:176349.17-176349.89" - wire width 3 $not$libresoc.v:176349$10555_Y - attribute \src "libresoc.v:176351.17-176351.91" - wire $not$libresoc.v:176351$10557_Y - attribute \src "libresoc.v:176348.18-176348.90" - wire $reduce_or$libresoc.v:176348$10554_Y - attribute \src "libresoc.v:176350.17-176350.103" - wire $reduce_or$libresoc.v:176350$10556_Y - attribute \src "libresoc.v:176352.17-176352.105" - wire $reduce_or$libresoc.v:176352$10558_Y + attribute \src "libresoc.v:177655.17-177655.91" + wire $not$libresoc.v:177655$10537_Y + attribute \src "libresoc.v:177657.17-177657.89" + wire width 3 $not$libresoc.v:177657$10539_Y + attribute \src "libresoc.v:177659.17-177659.91" + wire $not$libresoc.v:177659$10541_Y + attribute \src "libresoc.v:177656.18-177656.90" + wire $reduce_or$libresoc.v:177656$10538_Y + attribute \src "libresoc.v:177658.17-177658.103" + wire $reduce_or$libresoc.v:177658$10540_Y + attribute \src "libresoc.v:177660.17-177660.105" + wire $reduce_or$libresoc.v:177660$10542_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -358536,59 +329906,59 @@ module \rdpick_FAST_fast1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176347$10553 + cell $not $not$libresoc.v:177655$10537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:176347$10553_Y + connect \Y $not$libresoc.v:177655$10537_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176349$10555 + cell $not $not$libresoc.v:177657$10539 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \i - connect \Y $not$libresoc.v:176349$10555_Y + connect \Y $not$libresoc.v:177657$10539_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176351$10557 + cell $not $not$libresoc.v:177659$10541 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:176351$10557_Y + connect \Y $not$libresoc.v:177659$10541_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176348$10554 + cell $reduce_or $reduce_or$libresoc.v:177656$10538 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:176348$10554_Y + connect \Y $reduce_or$libresoc.v:177656$10538_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176350$10556 + cell $reduce_or $reduce_or$libresoc.v:177658$10540 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:176350$10556_Y + connect \Y $reduce_or$libresoc.v:177658$10540_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176352$10558 + cell $reduce_or $reduce_or$libresoc.v:177660$10542 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:176352$10558_Y - end - connect \$7 $not$libresoc.v:176347$10553_Y - connect \$11 $reduce_or$libresoc.v:176348$10554_Y - connect \$1 $not$libresoc.v:176349$10555_Y - connect \$4 $reduce_or$libresoc.v:176350$10556_Y - connect \$3 $not$libresoc.v:176351$10557_Y - connect \$8 $reduce_or$libresoc.v:176352$10558_Y + connect \Y $reduce_or$libresoc.v:177660$10542_Y + end + connect \$7 $not$libresoc.v:177655$10537_Y + connect \$11 $reduce_or$libresoc.v:177656$10538_Y + connect \$1 $not$libresoc.v:177657$10539_Y + connect \$4 $reduce_or$libresoc.v:177658$10540_Y + connect \$3 $not$libresoc.v:177659$10541_Y + connect \$8 $reduce_or$libresoc.v:177660$10542_Y connect \en_o \$11 connect \o { \t2 \t1 \t0 } connect \t2 \$7 @@ -358596,19 +329966,19 @@ module \rdpick_FAST_fast1 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:176363.1-176393.10" +attribute \src "libresoc.v:177671.1-177701.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_FAST_fast2" attribute \generator "nMigen" module \rdpick_FAST_fast2 - attribute \src "libresoc.v:176384.17-176384.89" - wire width 2 $not$libresoc.v:176384$10559_Y - attribute \src "libresoc.v:176386.17-176386.91" - wire $not$libresoc.v:176386$10561_Y - attribute \src "libresoc.v:176385.17-176385.103" - wire $reduce_or$libresoc.v:176385$10560_Y - attribute \src "libresoc.v:176387.17-176387.89" - wire $reduce_or$libresoc.v:176387$10562_Y + attribute \src "libresoc.v:177692.17-177692.89" + wire width 2 $not$libresoc.v:177692$10543_Y + attribute \src "libresoc.v:177694.17-177694.91" + wire $not$libresoc.v:177694$10545_Y + attribute \src "libresoc.v:177693.17-177693.103" + wire $reduce_or$libresoc.v:177693$10544_Y + attribute \src "libresoc.v:177695.17-177695.89" + wire $reduce_or$libresoc.v:177695$10546_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -358630,88 +330000,88 @@ module \rdpick_FAST_fast2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176384$10559 + cell $not $not$libresoc.v:177692$10543 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \i - connect \Y $not$libresoc.v:176384$10559_Y + connect \Y $not$libresoc.v:177692$10543_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176386$10561 + cell $not $not$libresoc.v:177694$10545 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:176386$10561_Y + connect \Y $not$libresoc.v:177694$10545_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176385$10560 + cell $reduce_or $reduce_or$libresoc.v:177693$10544 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:176385$10560_Y + connect \Y $reduce_or$libresoc.v:177693$10544_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176387$10562 + cell $reduce_or $reduce_or$libresoc.v:177695$10546 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:176387$10562_Y + connect \Y $reduce_or$libresoc.v:177695$10546_Y end - connect \$1 $not$libresoc.v:176384$10559_Y - connect \$4 $reduce_or$libresoc.v:176385$10560_Y - connect \$3 $not$libresoc.v:176386$10561_Y - connect \$7 $reduce_or$libresoc.v:176387$10562_Y + connect \$1 $not$libresoc.v:177692$10543_Y + connect \$4 $reduce_or$libresoc.v:177693$10544_Y + connect \$3 $not$libresoc.v:177694$10545_Y + connect \$7 $reduce_or$libresoc.v:177695$10546_Y connect \en_o \$7 connect \o { \t1 \t0 } connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:176397.1-176490.10" +attribute \src "libresoc.v:177705.1-177798.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_ra" attribute \generator "nMigen" module \rdpick_INT_ra - attribute \src "libresoc.v:176460.17-176460.91" - wire $not$libresoc.v:176460$10563_Y - attribute \src "libresoc.v:176462.18-176462.93" - wire $not$libresoc.v:176462$10565_Y - attribute \src "libresoc.v:176464.18-176464.93" - wire $not$libresoc.v:176464$10567_Y - attribute \src "libresoc.v:176465.17-176465.89" - wire width 9 $not$libresoc.v:176465$10568_Y - attribute \src "libresoc.v:176467.18-176467.93" - wire $not$libresoc.v:176467$10570_Y - attribute \src "libresoc.v:176469.18-176469.93" - wire $not$libresoc.v:176469$10572_Y - attribute \src "libresoc.v:176471.18-176471.93" - wire $not$libresoc.v:176471$10574_Y - attribute \src "libresoc.v:176473.18-176473.93" - wire $not$libresoc.v:176473$10576_Y - attribute \src "libresoc.v:176476.17-176476.91" - wire $not$libresoc.v:176476$10579_Y - attribute \src "libresoc.v:176461.18-176461.106" - wire $reduce_or$libresoc.v:176461$10564_Y - attribute \src "libresoc.v:176463.18-176463.106" - wire $reduce_or$libresoc.v:176463$10566_Y - attribute \src "libresoc.v:176466.18-176466.106" - wire $reduce_or$libresoc.v:176466$10569_Y - attribute \src "libresoc.v:176468.18-176468.106" - wire $reduce_or$libresoc.v:176468$10571_Y - attribute \src "libresoc.v:176470.18-176470.106" - wire $reduce_or$libresoc.v:176470$10573_Y - attribute \src "libresoc.v:176472.18-176472.106" - wire $reduce_or$libresoc.v:176472$10575_Y - attribute \src "libresoc.v:176474.18-176474.90" - wire $reduce_or$libresoc.v:176474$10577_Y - attribute \src "libresoc.v:176475.17-176475.103" - wire $reduce_or$libresoc.v:176475$10578_Y - attribute \src "libresoc.v:176477.17-176477.105" - wire $reduce_or$libresoc.v:176477$10580_Y + attribute \src "libresoc.v:177768.17-177768.91" + wire $not$libresoc.v:177768$10547_Y + attribute \src "libresoc.v:177770.18-177770.93" + wire $not$libresoc.v:177770$10549_Y + attribute \src "libresoc.v:177772.18-177772.93" + wire $not$libresoc.v:177772$10551_Y + attribute \src "libresoc.v:177773.17-177773.89" + wire width 9 $not$libresoc.v:177773$10552_Y + attribute \src "libresoc.v:177775.18-177775.93" + wire $not$libresoc.v:177775$10554_Y + attribute \src "libresoc.v:177777.18-177777.93" + wire $not$libresoc.v:177777$10556_Y + attribute \src "libresoc.v:177779.18-177779.93" + wire $not$libresoc.v:177779$10558_Y + attribute \src "libresoc.v:177781.18-177781.93" + wire $not$libresoc.v:177781$10560_Y + attribute \src "libresoc.v:177784.17-177784.91" + wire $not$libresoc.v:177784$10563_Y + attribute \src "libresoc.v:177769.18-177769.106" + wire $reduce_or$libresoc.v:177769$10548_Y + attribute \src "libresoc.v:177771.18-177771.106" + wire $reduce_or$libresoc.v:177771$10550_Y + attribute \src "libresoc.v:177774.18-177774.106" + wire $reduce_or$libresoc.v:177774$10553_Y + attribute \src "libresoc.v:177776.18-177776.106" + wire $reduce_or$libresoc.v:177776$10555_Y + attribute \src "libresoc.v:177778.18-177778.106" + wire $reduce_or$libresoc.v:177778$10557_Y + attribute \src "libresoc.v:177780.18-177780.106" + wire $reduce_or$libresoc.v:177780$10559_Y + attribute \src "libresoc.v:177782.18-177782.90" + wire $reduce_or$libresoc.v:177782$10561_Y + attribute \src "libresoc.v:177783.17-177783.103" + wire $reduce_or$libresoc.v:177783$10562_Y + attribute \src "libresoc.v:177785.17-177785.105" + wire $reduce_or$libresoc.v:177785$10564_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 9 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -358775,167 +330145,167 @@ module \rdpick_INT_ra attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t8 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176460$10563 + cell $not $not$libresoc.v:177768$10547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:176460$10563_Y + connect \Y $not$libresoc.v:177768$10547_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176462$10565 + cell $not $not$libresoc.v:177770$10549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:176462$10565_Y + connect \Y $not$libresoc.v:177770$10549_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176464$10567 + cell $not $not$libresoc.v:177772$10551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:176464$10567_Y + connect \Y $not$libresoc.v:177772$10551_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176465$10568 + cell $not $not$libresoc.v:177773$10552 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 9 connect \A \i - connect \Y $not$libresoc.v:176465$10568_Y + connect \Y $not$libresoc.v:177773$10552_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176467$10570 + cell $not $not$libresoc.v:177775$10554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:176467$10570_Y + connect \Y $not$libresoc.v:177775$10554_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176469$10572 + cell $not $not$libresoc.v:177777$10556 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:176469$10572_Y + connect \Y $not$libresoc.v:177777$10556_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176471$10574 + cell $not $not$libresoc.v:177779$10558 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:176471$10574_Y + connect \Y $not$libresoc.v:177779$10558_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176473$10576 + cell $not $not$libresoc.v:177781$10560 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$32 - connect \Y $not$libresoc.v:176473$10576_Y + connect \Y $not$libresoc.v:177781$10560_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176476$10579 + cell $not $not$libresoc.v:177784$10563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:176476$10579_Y + connect \Y $not$libresoc.v:177784$10563_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176461$10564 + cell $reduce_or $reduce_or$libresoc.v:177769$10548 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:176461$10564_Y + connect \Y $reduce_or$libresoc.v:177769$10548_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176463$10566 + cell $reduce_or $reduce_or$libresoc.v:177771$10550 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:176463$10566_Y + connect \Y $reduce_or$libresoc.v:177771$10550_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176466$10569 + cell $reduce_or $reduce_or$libresoc.v:177774$10553 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:176466$10569_Y + connect \Y $reduce_or$libresoc.v:177774$10553_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176468$10571 + cell $reduce_or $reduce_or$libresoc.v:177776$10555 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [5:0] \ni [6] } - connect \Y $reduce_or$libresoc.v:176468$10571_Y + connect \Y $reduce_or$libresoc.v:177776$10555_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176470$10573 + cell $reduce_or $reduce_or$libresoc.v:177778$10557 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [6:0] \ni [7] } - connect \Y $reduce_or$libresoc.v:176470$10573_Y + connect \Y $reduce_or$libresoc.v:177778$10557_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176472$10575 + cell $reduce_or $reduce_or$libresoc.v:177780$10559 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 1 connect \A { \i [7:0] \ni [8] } - connect \Y $reduce_or$libresoc.v:176472$10575_Y + connect \Y $reduce_or$libresoc.v:177780$10559_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176474$10577 + cell $reduce_or $reduce_or$libresoc.v:177782$10561 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:176474$10577_Y + connect \Y $reduce_or$libresoc.v:177782$10561_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176475$10578 + cell $reduce_or $reduce_or$libresoc.v:177783$10562 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:176475$10578_Y + connect \Y $reduce_or$libresoc.v:177783$10562_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176477$10580 + cell $reduce_or $reduce_or$libresoc.v:177785$10564 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:176477$10580_Y - end - connect \$7 $not$libresoc.v:176460$10563_Y - connect \$12 $reduce_or$libresoc.v:176461$10564_Y - connect \$11 $not$libresoc.v:176462$10565_Y - connect \$16 $reduce_or$libresoc.v:176463$10566_Y - connect \$15 $not$libresoc.v:176464$10567_Y - connect \$1 $not$libresoc.v:176465$10568_Y - connect \$20 $reduce_or$libresoc.v:176466$10569_Y - connect \$19 $not$libresoc.v:176467$10570_Y - connect \$24 $reduce_or$libresoc.v:176468$10571_Y - connect \$23 $not$libresoc.v:176469$10572_Y - connect \$28 $reduce_or$libresoc.v:176470$10573_Y - connect \$27 $not$libresoc.v:176471$10574_Y - connect \$32 $reduce_or$libresoc.v:176472$10575_Y - connect \$31 $not$libresoc.v:176473$10576_Y - connect \$35 $reduce_or$libresoc.v:176474$10577_Y - connect \$4 $reduce_or$libresoc.v:176475$10578_Y - connect \$3 $not$libresoc.v:176476$10579_Y - connect \$8 $reduce_or$libresoc.v:176477$10580_Y + connect \Y $reduce_or$libresoc.v:177785$10564_Y + end + connect \$7 $not$libresoc.v:177768$10547_Y + connect \$12 $reduce_or$libresoc.v:177769$10548_Y + connect \$11 $not$libresoc.v:177770$10549_Y + connect \$16 $reduce_or$libresoc.v:177771$10550_Y + connect \$15 $not$libresoc.v:177772$10551_Y + connect \$1 $not$libresoc.v:177773$10552_Y + connect \$20 $reduce_or$libresoc.v:177774$10553_Y + connect \$19 $not$libresoc.v:177775$10554_Y + connect \$24 $reduce_or$libresoc.v:177776$10555_Y + connect \$23 $not$libresoc.v:177777$10556_Y + connect \$28 $reduce_or$libresoc.v:177778$10557_Y + connect \$27 $not$libresoc.v:177779$10558_Y + connect \$32 $reduce_or$libresoc.v:177780$10559_Y + connect \$31 $not$libresoc.v:177781$10560_Y + connect \$35 $reduce_or$libresoc.v:177782$10561_Y + connect \$4 $reduce_or$libresoc.v:177783$10562_Y + connect \$3 $not$libresoc.v:177784$10563_Y + connect \$8 $reduce_or$libresoc.v:177785$10564_Y connect \en_o \$35 connect \o { \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } connect \t8 \$31 @@ -358949,43 +330319,43 @@ module \rdpick_INT_ra connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:176494.1-176578.10" +attribute \src "libresoc.v:177802.1-177886.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_rb" attribute \generator "nMigen" module \rdpick_INT_rb - attribute \src "libresoc.v:176551.17-176551.91" - wire $not$libresoc.v:176551$10581_Y - attribute \src "libresoc.v:176553.18-176553.93" - wire $not$libresoc.v:176553$10583_Y - attribute \src "libresoc.v:176555.18-176555.93" - wire $not$libresoc.v:176555$10585_Y - attribute \src "libresoc.v:176556.17-176556.89" - wire width 8 $not$libresoc.v:176556$10586_Y - attribute \src "libresoc.v:176558.18-176558.93" - wire $not$libresoc.v:176558$10588_Y - attribute \src "libresoc.v:176560.18-176560.93" - wire $not$libresoc.v:176560$10590_Y - attribute \src "libresoc.v:176562.18-176562.93" - wire $not$libresoc.v:176562$10592_Y - attribute \src "libresoc.v:176565.17-176565.91" - wire $not$libresoc.v:176565$10595_Y - attribute \src "libresoc.v:176552.18-176552.106" - wire $reduce_or$libresoc.v:176552$10582_Y - attribute \src "libresoc.v:176554.18-176554.106" - wire $reduce_or$libresoc.v:176554$10584_Y - attribute \src "libresoc.v:176557.18-176557.106" - wire $reduce_or$libresoc.v:176557$10587_Y - attribute \src "libresoc.v:176559.18-176559.106" - wire $reduce_or$libresoc.v:176559$10589_Y - attribute \src "libresoc.v:176561.18-176561.106" - wire $reduce_or$libresoc.v:176561$10591_Y - attribute \src "libresoc.v:176563.18-176563.90" - wire $reduce_or$libresoc.v:176563$10593_Y - attribute \src "libresoc.v:176564.17-176564.103" - wire $reduce_or$libresoc.v:176564$10594_Y - attribute \src "libresoc.v:176566.17-176566.105" - wire $reduce_or$libresoc.v:176566$10596_Y + attribute \src "libresoc.v:177859.17-177859.91" + wire $not$libresoc.v:177859$10565_Y + attribute \src "libresoc.v:177861.18-177861.93" + wire $not$libresoc.v:177861$10567_Y + attribute \src "libresoc.v:177863.18-177863.93" + wire $not$libresoc.v:177863$10569_Y + attribute \src "libresoc.v:177864.17-177864.89" + wire width 8 $not$libresoc.v:177864$10570_Y + attribute \src "libresoc.v:177866.18-177866.93" + wire $not$libresoc.v:177866$10572_Y + attribute \src "libresoc.v:177868.18-177868.93" + wire $not$libresoc.v:177868$10574_Y + attribute \src "libresoc.v:177870.18-177870.93" + wire $not$libresoc.v:177870$10576_Y + attribute \src "libresoc.v:177873.17-177873.91" + wire $not$libresoc.v:177873$10579_Y + attribute \src "libresoc.v:177860.18-177860.106" + wire $reduce_or$libresoc.v:177860$10566_Y + attribute \src "libresoc.v:177862.18-177862.106" + wire $reduce_or$libresoc.v:177862$10568_Y + attribute \src "libresoc.v:177865.18-177865.106" + wire $reduce_or$libresoc.v:177865$10571_Y + attribute \src "libresoc.v:177867.18-177867.106" + wire $reduce_or$libresoc.v:177867$10573_Y + attribute \src "libresoc.v:177869.18-177869.106" + wire $reduce_or$libresoc.v:177869$10575_Y + attribute \src "libresoc.v:177871.18-177871.90" + wire $reduce_or$libresoc.v:177871$10577_Y + attribute \src "libresoc.v:177872.17-177872.103" + wire $reduce_or$libresoc.v:177872$10578_Y + attribute \src "libresoc.v:177874.17-177874.105" + wire $reduce_or$libresoc.v:177874$10580_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 8 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -359043,149 +330413,149 @@ module \rdpick_INT_rb attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176551$10581 + cell $not $not$libresoc.v:177859$10565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:176551$10581_Y + connect \Y $not$libresoc.v:177859$10565_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176553$10583 + cell $not $not$libresoc.v:177861$10567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:176553$10583_Y + connect \Y $not$libresoc.v:177861$10567_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176555$10585 + cell $not $not$libresoc.v:177863$10569 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:176555$10585_Y + connect \Y $not$libresoc.v:177863$10569_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176556$10586 + cell $not $not$libresoc.v:177864$10570 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 8 connect \A \i - connect \Y $not$libresoc.v:176556$10586_Y + connect \Y $not$libresoc.v:177864$10570_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176558$10588 + cell $not $not$libresoc.v:177866$10572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:176558$10588_Y + connect \Y $not$libresoc.v:177866$10572_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176560$10590 + cell $not $not$libresoc.v:177868$10574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:176560$10590_Y + connect \Y $not$libresoc.v:177868$10574_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176562$10592 + cell $not $not$libresoc.v:177870$10576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:176562$10592_Y + connect \Y $not$libresoc.v:177870$10576_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176565$10595 + cell $not $not$libresoc.v:177873$10579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:176565$10595_Y + connect \Y $not$libresoc.v:177873$10579_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176552$10582 + cell $reduce_or $reduce_or$libresoc.v:177860$10566 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:176552$10582_Y + connect \Y $reduce_or$libresoc.v:177860$10566_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176554$10584 + cell $reduce_or $reduce_or$libresoc.v:177862$10568 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:176554$10584_Y + connect \Y $reduce_or$libresoc.v:177862$10568_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176557$10587 + cell $reduce_or $reduce_or$libresoc.v:177865$10571 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:176557$10587_Y + connect \Y $reduce_or$libresoc.v:177865$10571_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176559$10589 + cell $reduce_or $reduce_or$libresoc.v:177867$10573 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [5:0] \ni [6] } - connect \Y $reduce_or$libresoc.v:176559$10589_Y + connect \Y $reduce_or$libresoc.v:177867$10573_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176561$10591 + cell $reduce_or $reduce_or$libresoc.v:177869$10575 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [6:0] \ni [7] } - connect \Y $reduce_or$libresoc.v:176561$10591_Y + connect \Y $reduce_or$libresoc.v:177869$10575_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176563$10593 + cell $reduce_or $reduce_or$libresoc.v:177871$10577 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:176563$10593_Y + connect \Y $reduce_or$libresoc.v:177871$10577_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176564$10594 + cell $reduce_or $reduce_or$libresoc.v:177872$10578 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:176564$10594_Y + connect \Y $reduce_or$libresoc.v:177872$10578_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176566$10596 + cell $reduce_or $reduce_or$libresoc.v:177874$10580 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:176566$10596_Y - end - connect \$7 $not$libresoc.v:176551$10581_Y - connect \$12 $reduce_or$libresoc.v:176552$10582_Y - connect \$11 $not$libresoc.v:176553$10583_Y - connect \$16 $reduce_or$libresoc.v:176554$10584_Y - connect \$15 $not$libresoc.v:176555$10585_Y - connect \$1 $not$libresoc.v:176556$10586_Y - connect \$20 $reduce_or$libresoc.v:176557$10587_Y - connect \$19 $not$libresoc.v:176558$10588_Y - connect \$24 $reduce_or$libresoc.v:176559$10589_Y - connect \$23 $not$libresoc.v:176560$10590_Y - connect \$28 $reduce_or$libresoc.v:176561$10591_Y - connect \$27 $not$libresoc.v:176562$10592_Y - connect \$31 $reduce_or$libresoc.v:176563$10593_Y - connect \$4 $reduce_or$libresoc.v:176564$10594_Y - connect \$3 $not$libresoc.v:176565$10595_Y - connect \$8 $reduce_or$libresoc.v:176566$10596_Y + connect \Y $reduce_or$libresoc.v:177874$10580_Y + end + connect \$7 $not$libresoc.v:177859$10565_Y + connect \$12 $reduce_or$libresoc.v:177860$10566_Y + connect \$11 $not$libresoc.v:177861$10567_Y + connect \$16 $reduce_or$libresoc.v:177862$10568_Y + connect \$15 $not$libresoc.v:177863$10569_Y + connect \$1 $not$libresoc.v:177864$10570_Y + connect \$20 $reduce_or$libresoc.v:177865$10571_Y + connect \$19 $not$libresoc.v:177866$10572_Y + connect \$24 $reduce_or$libresoc.v:177867$10573_Y + connect \$23 $not$libresoc.v:177868$10574_Y + connect \$28 $reduce_or$libresoc.v:177869$10575_Y + connect \$27 $not$libresoc.v:177870$10576_Y + connect \$31 $reduce_or$libresoc.v:177871$10577_Y + connect \$4 $reduce_or$libresoc.v:177872$10578_Y + connect \$3 $not$libresoc.v:177873$10579_Y + connect \$8 $reduce_or$libresoc.v:177874$10580_Y connect \en_o \$31 connect \o { \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } connect \t7 \$27 @@ -359198,19 +330568,19 @@ module \rdpick_INT_rb connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:176582.1-176612.10" +attribute \src "libresoc.v:177890.1-177920.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_INT_rc" attribute \generator "nMigen" module \rdpick_INT_rc - attribute \src "libresoc.v:176603.17-176603.89" - wire width 2 $not$libresoc.v:176603$10597_Y - attribute \src "libresoc.v:176605.17-176605.91" - wire $not$libresoc.v:176605$10599_Y - attribute \src "libresoc.v:176604.17-176604.103" - wire $reduce_or$libresoc.v:176604$10598_Y - attribute \src "libresoc.v:176606.17-176606.89" - wire $reduce_or$libresoc.v:176606$10600_Y + attribute \src "libresoc.v:177911.17-177911.89" + wire width 2 $not$libresoc.v:177911$10581_Y + attribute \src "libresoc.v:177913.17-177913.91" + wire $not$libresoc.v:177913$10583_Y + attribute \src "libresoc.v:177912.17-177912.103" + wire $reduce_or$libresoc.v:177912$10582_Y + attribute \src "libresoc.v:177914.17-177914.89" + wire $reduce_or$libresoc.v:177914$10584_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -359232,56 +330602,56 @@ module \rdpick_INT_rc attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176603$10597 + cell $not $not$libresoc.v:177911$10581 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \i - connect \Y $not$libresoc.v:176603$10597_Y + connect \Y $not$libresoc.v:177911$10581_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176605$10599 + cell $not $not$libresoc.v:177913$10583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:176605$10599_Y + connect \Y $not$libresoc.v:177913$10583_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176604$10598 + cell $reduce_or $reduce_or$libresoc.v:177912$10582 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:176604$10598_Y + connect \Y $reduce_or$libresoc.v:177912$10582_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176606$10600 + cell $reduce_or $reduce_or$libresoc.v:177914$10584 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:176606$10600_Y + connect \Y $reduce_or$libresoc.v:177914$10584_Y end - connect \$1 $not$libresoc.v:176603$10597_Y - connect \$4 $reduce_or$libresoc.v:176604$10598_Y - connect \$3 $not$libresoc.v:176605$10599_Y - connect \$7 $reduce_or$libresoc.v:176606$10600_Y + connect \$1 $not$libresoc.v:177911$10581_Y + connect \$4 $reduce_or$libresoc.v:177912$10582_Y + connect \$3 $not$libresoc.v:177913$10583_Y + connect \$7 $reduce_or$libresoc.v:177914$10584_Y connect \en_o \$7 connect \o { \t1 \t0 } connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:176616.1-176637.10" +attribute \src "libresoc.v:177924.1-177945.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_SPR_spr1" attribute \generator "nMigen" module \rdpick_SPR_spr1 - attribute \src "libresoc.v:176631.17-176631.89" - wire $not$libresoc.v:176631$10601_Y - attribute \src "libresoc.v:176632.17-176632.89" - wire $reduce_or$libresoc.v:176632$10602_Y + attribute \src "libresoc.v:177939.17-177939.89" + wire $not$libresoc.v:177939$10585_Y + attribute \src "libresoc.v:177940.17-177940.89" + wire $reduce_or$libresoc.v:177940$10586_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -359297,45 +330667,45 @@ module \rdpick_SPR_spr1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176631$10601 + cell $not $not$libresoc.v:177939$10585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:176631$10601_Y + connect \Y $not$libresoc.v:177939$10585_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176632$10602 + cell $reduce_or $reduce_or$libresoc.v:177940$10586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:176632$10602_Y + connect \Y $reduce_or$libresoc.v:177940$10586_Y end - connect \$1 $not$libresoc.v:176631$10601_Y - connect \$3 $reduce_or$libresoc.v:176632$10602_Y + connect \$1 $not$libresoc.v:177939$10585_Y + connect \$3 $reduce_or$libresoc.v:177940$10586_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:176641.1-176680.10" +attribute \src "libresoc.v:177949.1-177988.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_ca" attribute \generator "nMigen" module \rdpick_XER_xer_ca - attribute \src "libresoc.v:176668.17-176668.91" - wire $not$libresoc.v:176668$10603_Y - attribute \src "libresoc.v:176670.17-176670.89" - wire width 3 $not$libresoc.v:176670$10605_Y - attribute \src "libresoc.v:176672.17-176672.91" - wire $not$libresoc.v:176672$10607_Y - attribute \src "libresoc.v:176669.18-176669.90" - wire $reduce_or$libresoc.v:176669$10604_Y - attribute \src "libresoc.v:176671.17-176671.103" - wire $reduce_or$libresoc.v:176671$10606_Y - attribute \src "libresoc.v:176673.17-176673.105" - wire $reduce_or$libresoc.v:176673$10608_Y + attribute \src "libresoc.v:177976.17-177976.91" + wire $not$libresoc.v:177976$10587_Y + attribute \src "libresoc.v:177978.17-177978.89" + wire width 3 $not$libresoc.v:177978$10589_Y + attribute \src "libresoc.v:177980.17-177980.91" + wire $not$libresoc.v:177980$10591_Y + attribute \src "libresoc.v:177977.18-177977.90" + wire $reduce_or$libresoc.v:177977$10588_Y + attribute \src "libresoc.v:177979.17-177979.103" + wire $reduce_or$libresoc.v:177979$10590_Y + attribute \src "libresoc.v:177981.17-177981.105" + wire $reduce_or$libresoc.v:177981$10592_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -359363,59 +330733,59 @@ module \rdpick_XER_xer_ca attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176668$10603 + cell $not $not$libresoc.v:177976$10587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:176668$10603_Y + connect \Y $not$libresoc.v:177976$10587_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176670$10605 + cell $not $not$libresoc.v:177978$10589 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \i - connect \Y $not$libresoc.v:176670$10605_Y + connect \Y $not$libresoc.v:177978$10589_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176672$10607 + cell $not $not$libresoc.v:177980$10591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:176672$10607_Y + connect \Y $not$libresoc.v:177980$10591_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176669$10604 + cell $reduce_or $reduce_or$libresoc.v:177977$10588 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:176669$10604_Y + connect \Y $reduce_or$libresoc.v:177977$10588_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176671$10606 + cell $reduce_or $reduce_or$libresoc.v:177979$10590 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:176671$10606_Y + connect \Y $reduce_or$libresoc.v:177979$10590_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176673$10608 + cell $reduce_or $reduce_or$libresoc.v:177981$10592 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:176673$10608_Y - end - connect \$7 $not$libresoc.v:176668$10603_Y - connect \$11 $reduce_or$libresoc.v:176669$10604_Y - connect \$1 $not$libresoc.v:176670$10605_Y - connect \$4 $reduce_or$libresoc.v:176671$10606_Y - connect \$3 $not$libresoc.v:176672$10607_Y - connect \$8 $reduce_or$libresoc.v:176673$10608_Y + connect \Y $reduce_or$libresoc.v:177981$10592_Y + end + connect \$7 $not$libresoc.v:177976$10587_Y + connect \$11 $reduce_or$libresoc.v:177977$10588_Y + connect \$1 $not$libresoc.v:177978$10589_Y + connect \$4 $reduce_or$libresoc.v:177979$10590_Y + connect \$3 $not$libresoc.v:177980$10591_Y + connect \$8 $reduce_or$libresoc.v:177981$10592_Y connect \en_o \$11 connect \o { \t2 \t1 \t0 } connect \t2 \$7 @@ -359423,15 +330793,15 @@ module \rdpick_XER_xer_ca connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:176684.1-176705.10" +attribute \src "libresoc.v:177992.1-178013.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_ov" attribute \generator "nMigen" module \rdpick_XER_xer_ov - attribute \src "libresoc.v:176699.17-176699.89" - wire $not$libresoc.v:176699$10609_Y - attribute \src "libresoc.v:176700.17-176700.89" - wire $reduce_or$libresoc.v:176700$10610_Y + attribute \src "libresoc.v:178007.17-178007.89" + wire $not$libresoc.v:178007$10593_Y + attribute \src "libresoc.v:178008.17-178008.89" + wire $reduce_or$libresoc.v:178008$10594_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -359447,57 +330817,57 @@ module \rdpick_XER_xer_ov attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176699$10609 + cell $not $not$libresoc.v:178007$10593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:176699$10609_Y + connect \Y $not$libresoc.v:178007$10593_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176700$10610 + cell $reduce_or $reduce_or$libresoc.v:178008$10594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:176700$10610_Y + connect \Y $reduce_or$libresoc.v:178008$10594_Y end - connect \$1 $not$libresoc.v:176699$10609_Y - connect \$3 $reduce_or$libresoc.v:176700$10610_Y + connect \$1 $not$libresoc.v:178007$10593_Y + connect \$3 $reduce_or$libresoc.v:178008$10594_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:176709.1-176775.10" +attribute \src "libresoc.v:178017.1-178083.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.rdpick_XER_xer_so" attribute \generator "nMigen" module \rdpick_XER_xer_so - attribute \src "libresoc.v:176754.17-176754.91" - wire $not$libresoc.v:176754$10611_Y - attribute \src "libresoc.v:176756.18-176756.93" - wire $not$libresoc.v:176756$10613_Y - attribute \src "libresoc.v:176758.18-176758.93" - wire $not$libresoc.v:176758$10615_Y - attribute \src "libresoc.v:176759.17-176759.89" - wire width 6 $not$libresoc.v:176759$10616_Y - attribute \src "libresoc.v:176761.18-176761.93" - wire $not$libresoc.v:176761$10618_Y - attribute \src "libresoc.v:176764.17-176764.91" - wire $not$libresoc.v:176764$10621_Y - attribute \src "libresoc.v:176755.18-176755.106" - wire $reduce_or$libresoc.v:176755$10612_Y - attribute \src "libresoc.v:176757.18-176757.106" - wire $reduce_or$libresoc.v:176757$10614_Y - attribute \src "libresoc.v:176760.18-176760.106" - wire $reduce_or$libresoc.v:176760$10617_Y - attribute \src "libresoc.v:176762.18-176762.90" - wire $reduce_or$libresoc.v:176762$10619_Y - attribute \src "libresoc.v:176763.17-176763.103" - wire $reduce_or$libresoc.v:176763$10620_Y - attribute \src "libresoc.v:176765.17-176765.105" - wire $reduce_or$libresoc.v:176765$10622_Y + attribute \src "libresoc.v:178062.17-178062.91" + wire $not$libresoc.v:178062$10595_Y + attribute \src "libresoc.v:178064.18-178064.93" + wire $not$libresoc.v:178064$10597_Y + attribute \src "libresoc.v:178066.18-178066.93" + wire $not$libresoc.v:178066$10599_Y + attribute \src "libresoc.v:178067.17-178067.89" + wire width 6 $not$libresoc.v:178067$10600_Y + attribute \src "libresoc.v:178069.18-178069.93" + wire $not$libresoc.v:178069$10602_Y + attribute \src "libresoc.v:178072.17-178072.91" + wire $not$libresoc.v:178072$10605_Y + attribute \src "libresoc.v:178063.18-178063.106" + wire $reduce_or$libresoc.v:178063$10596_Y + attribute \src "libresoc.v:178065.18-178065.106" + wire $reduce_or$libresoc.v:178065$10598_Y + attribute \src "libresoc.v:178068.18-178068.106" + wire $reduce_or$libresoc.v:178068$10601_Y + attribute \src "libresoc.v:178070.18-178070.90" + wire $reduce_or$libresoc.v:178070$10603_Y + attribute \src "libresoc.v:178071.17-178071.103" + wire $reduce_or$libresoc.v:178071$10604_Y + attribute \src "libresoc.v:178073.17-178073.105" + wire $reduce_or$libresoc.v:178073$10606_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -359543,113 +330913,113 @@ module \rdpick_XER_xer_so attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176754$10611 + cell $not $not$libresoc.v:178062$10595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:176754$10611_Y + connect \Y $not$libresoc.v:178062$10595_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176756$10613 + cell $not $not$libresoc.v:178064$10597 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:176756$10613_Y + connect \Y $not$libresoc.v:178064$10597_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176758$10615 + cell $not $not$libresoc.v:178066$10599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:176758$10615_Y + connect \Y $not$libresoc.v:178066$10599_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:176759$10616 + cell $not $not$libresoc.v:178067$10600 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \i - connect \Y $not$libresoc.v:176759$10616_Y + connect \Y $not$libresoc.v:178067$10600_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176761$10618 + cell $not $not$libresoc.v:178069$10602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:176761$10618_Y + connect \Y $not$libresoc.v:178069$10602_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:176764$10621 + cell $not $not$libresoc.v:178072$10605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:176764$10621_Y + connect \Y $not$libresoc.v:178072$10605_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176755$10612 + cell $reduce_or $reduce_or$libresoc.v:178063$10596 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:176755$10612_Y + connect \Y $reduce_or$libresoc.v:178063$10596_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176757$10614 + cell $reduce_or $reduce_or$libresoc.v:178065$10598 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:176757$10614_Y + connect \Y $reduce_or$libresoc.v:178065$10598_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176760$10617 + cell $reduce_or $reduce_or$libresoc.v:178068$10601 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:176760$10617_Y + connect \Y $reduce_or$libresoc.v:178068$10601_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:176762$10619 + cell $reduce_or $reduce_or$libresoc.v:178070$10603 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:176762$10619_Y + connect \Y $reduce_or$libresoc.v:178070$10603_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176763$10620 + cell $reduce_or $reduce_or$libresoc.v:178071$10604 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:176763$10620_Y + connect \Y $reduce_or$libresoc.v:178071$10604_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:176765$10622 + cell $reduce_or $reduce_or$libresoc.v:178073$10606 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:176765$10622_Y - end - connect \$7 $not$libresoc.v:176754$10611_Y - connect \$12 $reduce_or$libresoc.v:176755$10612_Y - connect \$11 $not$libresoc.v:176756$10613_Y - connect \$16 $reduce_or$libresoc.v:176757$10614_Y - connect \$15 $not$libresoc.v:176758$10615_Y - connect \$1 $not$libresoc.v:176759$10616_Y - connect \$20 $reduce_or$libresoc.v:176760$10617_Y - connect \$19 $not$libresoc.v:176761$10618_Y - connect \$23 $reduce_or$libresoc.v:176762$10619_Y - connect \$4 $reduce_or$libresoc.v:176763$10620_Y - connect \$3 $not$libresoc.v:176764$10621_Y - connect \$8 $reduce_or$libresoc.v:176765$10622_Y + connect \Y $reduce_or$libresoc.v:178073$10606_Y + end + connect \$7 $not$libresoc.v:178062$10595_Y + connect \$12 $reduce_or$libresoc.v:178063$10596_Y + connect \$11 $not$libresoc.v:178064$10597_Y + connect \$16 $reduce_or$libresoc.v:178065$10598_Y + connect \$15 $not$libresoc.v:178066$10599_Y + connect \$1 $not$libresoc.v:178067$10600_Y + connect \$20 $reduce_or$libresoc.v:178068$10601_Y + connect \$19 $not$libresoc.v:178069$10602_Y + connect \$23 $reduce_or$libresoc.v:178070$10603_Y + connect \$4 $reduce_or$libresoc.v:178071$10604_Y + connect \$3 $not$libresoc.v:178072$10605_Y + connect \$8 $reduce_or$libresoc.v:178073$10606_Y connect \en_o \$23 connect \o { \t5 \t4 \t3 \t2 \t1 \t0 } connect \t5 \$19 @@ -359660,207 +331030,207 @@ module \rdpick_XER_xer_so connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:176779.1-177334.10" +attribute \src "libresoc.v:178087.1-178642.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_0" attribute \generator "nMigen" module \reg_0 - attribute \src "libresoc.v:176887.3-176926.6" - wire width 4 $0\cr_pred0__data_o$next[3:0]$10637 - attribute \src "libresoc.v:176885.3-176886.49" + attribute \src "libresoc.v:178195.3-178234.6" + wire width 4 $0\cr_pred0__data_o$next[3:0]$10621 + attribute \src "libresoc.v:178193.3-178194.49" wire width 4 $0\cr_pred0__data_o[3:0] - attribute \src "libresoc.v:176780.7-176780.20" + attribute \src "libresoc.v:178088.7-178088.20" wire $0\initial[0:0] - attribute \src "libresoc.v:177264.3-177303.6" - wire width 4 $0\r0__data_o$next[3:0]$10708 - attribute \src "libresoc.v:176877.3-176878.37" + attribute \src "libresoc.v:178572.3-178611.6" + wire width 4 $0\r0__data_o$next[3:0]$10692 + attribute \src "libresoc.v:178185.3-178186.37" wire width 4 $0\r0__data_o[3:0] - attribute \src "libresoc.v:176957.3-176996.6" - wire width 4 $0\r20__data_o$next[3:0]$10646 - attribute \src "libresoc.v:176875.3-176876.39" + attribute \src "libresoc.v:178265.3-178304.6" + wire width 4 $0\r20__data_o$next[3:0]$10630 + attribute \src "libresoc.v:178183.3-178184.39" wire width 4 $0\r20__data_o[3:0] - attribute \src "libresoc.v:177027.3-177053.6" - wire width 4 $0\reg$next[3:0]$10660 - attribute \src "libresoc.v:176873.3-176874.25" + attribute \src "libresoc.v:178335.3-178361.6" + wire width 4 $0\reg$next[3:0]$10644 + attribute \src "libresoc.v:178181.3-178182.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:177054.3-177093.6" - wire width 4 $0\src10__data_o$next[3:0]$10666 - attribute \src "libresoc.v:176883.3-176884.43" + attribute \src "libresoc.v:178362.3-178401.6" + wire width 4 $0\src10__data_o$next[3:0]$10650 + attribute \src "libresoc.v:178191.3-178192.43" wire width 4 $0\src10__data_o[3:0] - attribute \src "libresoc.v:177124.3-177163.6" - wire width 4 $0\src20__data_o$next[3:0]$10680 - attribute \src "libresoc.v:176881.3-176882.43" + attribute \src "libresoc.v:178432.3-178471.6" + wire width 4 $0\src20__data_o$next[3:0]$10664 + attribute \src "libresoc.v:178189.3-178190.43" wire width 4 $0\src20__data_o[3:0] - attribute \src "libresoc.v:177194.3-177233.6" - wire width 4 $0\src30__data_o$next[3:0]$10694 - attribute \src "libresoc.v:176879.3-176880.43" + attribute \src "libresoc.v:178502.3-178541.6" + wire width 4 $0\src30__data_o$next[3:0]$10678 + attribute \src "libresoc.v:178187.3-178188.43" wire width 4 $0\src30__data_o[3:0] - attribute \src "libresoc.v:177234.3-177263.6" - wire $0\wr_detect$10[0:0]$10702 - attribute \src "libresoc.v:177304.3-177333.6" - wire $0\wr_detect$13[0:0]$10716 - attribute \src "libresoc.v:176997.3-177026.6" - wire $0\wr_detect$16[0:0]$10654 - attribute \src "libresoc.v:177094.3-177123.6" - wire $0\wr_detect$4[0:0]$10674 - attribute \src "libresoc.v:177164.3-177193.6" - wire $0\wr_detect$7[0:0]$10688 - attribute \src "libresoc.v:176927.3-176956.6" + attribute \src "libresoc.v:178542.3-178571.6" + wire $0\wr_detect$10[0:0]$10686 + attribute \src "libresoc.v:178612.3-178641.6" + wire $0\wr_detect$13[0:0]$10700 + attribute \src "libresoc.v:178305.3-178334.6" + wire $0\wr_detect$16[0:0]$10638 + attribute \src "libresoc.v:178402.3-178431.6" + wire $0\wr_detect$4[0:0]$10658 + attribute \src "libresoc.v:178472.3-178501.6" + wire $0\wr_detect$7[0:0]$10672 + attribute \src "libresoc.v:178235.3-178264.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:176887.3-176926.6" - wire width 4 $1\cr_pred0__data_o$next[3:0]$10638 - attribute \src "libresoc.v:176799.13-176799.36" + attribute \src "libresoc.v:178195.3-178234.6" + wire width 4 $1\cr_pred0__data_o$next[3:0]$10622 + attribute \src "libresoc.v:178107.13-178107.36" wire width 4 $1\cr_pred0__data_o[3:0] - attribute \src "libresoc.v:177264.3-177303.6" - wire width 4 $1\r0__data_o$next[3:0]$10709 - attribute \src "libresoc.v:176814.13-176814.30" + attribute \src "libresoc.v:178572.3-178611.6" + wire width 4 $1\r0__data_o$next[3:0]$10693 + attribute \src "libresoc.v:178122.13-178122.30" wire width 4 $1\r0__data_o[3:0] - attribute \src "libresoc.v:176957.3-176996.6" - wire width 4 $1\r20__data_o$next[3:0]$10647 - attribute \src "libresoc.v:176821.13-176821.31" + attribute \src "libresoc.v:178265.3-178304.6" + wire width 4 $1\r20__data_o$next[3:0]$10631 + attribute \src "libresoc.v:178129.13-178129.31" wire width 4 $1\r20__data_o[3:0] - attribute \src "libresoc.v:177027.3-177053.6" - wire width 4 $1\reg$next[3:0]$10661 - attribute \src "libresoc.v:176827.13-176827.25" + attribute \src "libresoc.v:178335.3-178361.6" + wire width 4 $1\reg$next[3:0]$10645 + attribute \src "libresoc.v:178135.13-178135.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:177054.3-177093.6" - wire width 4 $1\src10__data_o$next[3:0]$10667 - attribute \src "libresoc.v:176832.13-176832.33" + attribute \src "libresoc.v:178362.3-178401.6" + wire width 4 $1\src10__data_o$next[3:0]$10651 + attribute \src "libresoc.v:178140.13-178140.33" wire width 4 $1\src10__data_o[3:0] - attribute \src "libresoc.v:177124.3-177163.6" - wire width 4 $1\src20__data_o$next[3:0]$10681 - attribute \src "libresoc.v:176839.13-176839.33" + attribute \src "libresoc.v:178432.3-178471.6" + wire width 4 $1\src20__data_o$next[3:0]$10665 + attribute \src "libresoc.v:178147.13-178147.33" wire width 4 $1\src20__data_o[3:0] - attribute \src "libresoc.v:177194.3-177233.6" - wire width 4 $1\src30__data_o$next[3:0]$10695 - attribute \src "libresoc.v:176846.13-176846.33" + attribute \src "libresoc.v:178502.3-178541.6" + wire width 4 $1\src30__data_o$next[3:0]$10679 + attribute \src "libresoc.v:178154.13-178154.33" wire width 4 $1\src30__data_o[3:0] - attribute \src "libresoc.v:177234.3-177263.6" - wire $1\wr_detect$10[0:0]$10703 - attribute \src "libresoc.v:177304.3-177333.6" - wire $1\wr_detect$13[0:0]$10717 - attribute \src "libresoc.v:176997.3-177026.6" - wire $1\wr_detect$16[0:0]$10655 - attribute \src "libresoc.v:177094.3-177123.6" - wire $1\wr_detect$4[0:0]$10675 - attribute \src "libresoc.v:177164.3-177193.6" - wire $1\wr_detect$7[0:0]$10689 - attribute \src "libresoc.v:176927.3-176956.6" + attribute \src "libresoc.v:178542.3-178571.6" + wire $1\wr_detect$10[0:0]$10687 + attribute \src "libresoc.v:178612.3-178641.6" + wire $1\wr_detect$13[0:0]$10701 + attribute \src "libresoc.v:178305.3-178334.6" + wire $1\wr_detect$16[0:0]$10639 + attribute \src "libresoc.v:178402.3-178431.6" + wire $1\wr_detect$4[0:0]$10659 + attribute \src "libresoc.v:178472.3-178501.6" + wire $1\wr_detect$7[0:0]$10673 + attribute \src "libresoc.v:178235.3-178264.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:176887.3-176926.6" - wire width 4 $2\cr_pred0__data_o$next[3:0]$10639 - attribute \src "libresoc.v:177264.3-177303.6" - wire width 4 $2\r0__data_o$next[3:0]$10710 - attribute \src "libresoc.v:176957.3-176996.6" - wire width 4 $2\r20__data_o$next[3:0]$10648 - attribute \src "libresoc.v:177027.3-177053.6" - wire width 4 $2\reg$next[3:0]$10662 - attribute \src "libresoc.v:177054.3-177093.6" - wire width 4 $2\src10__data_o$next[3:0]$10668 - attribute \src "libresoc.v:177124.3-177163.6" - wire width 4 $2\src20__data_o$next[3:0]$10682 - attribute \src "libresoc.v:177194.3-177233.6" - wire width 4 $2\src30__data_o$next[3:0]$10696 - attribute \src "libresoc.v:177234.3-177263.6" - wire $2\wr_detect$10[0:0]$10704 - attribute \src "libresoc.v:177304.3-177333.6" - wire $2\wr_detect$13[0:0]$10718 - attribute \src "libresoc.v:176997.3-177026.6" - wire $2\wr_detect$16[0:0]$10656 - attribute \src "libresoc.v:177094.3-177123.6" - wire $2\wr_detect$4[0:0]$10676 - attribute \src "libresoc.v:177164.3-177193.6" - wire $2\wr_detect$7[0:0]$10690 - attribute \src "libresoc.v:176927.3-176956.6" + attribute \src "libresoc.v:178195.3-178234.6" + wire width 4 $2\cr_pred0__data_o$next[3:0]$10623 + attribute \src "libresoc.v:178572.3-178611.6" + wire width 4 $2\r0__data_o$next[3:0]$10694 + attribute \src "libresoc.v:178265.3-178304.6" + wire width 4 $2\r20__data_o$next[3:0]$10632 + attribute \src "libresoc.v:178335.3-178361.6" + wire width 4 $2\reg$next[3:0]$10646 + attribute \src "libresoc.v:178362.3-178401.6" + wire width 4 $2\src10__data_o$next[3:0]$10652 + attribute \src "libresoc.v:178432.3-178471.6" + wire width 4 $2\src20__data_o$next[3:0]$10666 + attribute \src "libresoc.v:178502.3-178541.6" + wire width 4 $2\src30__data_o$next[3:0]$10680 + attribute \src "libresoc.v:178542.3-178571.6" + wire $2\wr_detect$10[0:0]$10688 + attribute \src "libresoc.v:178612.3-178641.6" + wire $2\wr_detect$13[0:0]$10702 + attribute \src "libresoc.v:178305.3-178334.6" + wire $2\wr_detect$16[0:0]$10640 + attribute \src "libresoc.v:178402.3-178431.6" + wire $2\wr_detect$4[0:0]$10660 + attribute \src "libresoc.v:178472.3-178501.6" + wire $2\wr_detect$7[0:0]$10674 + attribute \src "libresoc.v:178235.3-178264.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:176887.3-176926.6" - wire width 4 $3\cr_pred0__data_o$next[3:0]$10640 - attribute \src "libresoc.v:177264.3-177303.6" - wire width 4 $3\r0__data_o$next[3:0]$10711 - attribute \src "libresoc.v:176957.3-176996.6" - wire width 4 $3\r20__data_o$next[3:0]$10649 - attribute \src "libresoc.v:177027.3-177053.6" - wire width 4 $3\reg$next[3:0]$10663 - attribute \src "libresoc.v:177054.3-177093.6" - wire width 4 $3\src10__data_o$next[3:0]$10669 - attribute \src "libresoc.v:177124.3-177163.6" - wire width 4 $3\src20__data_o$next[3:0]$10683 - attribute \src "libresoc.v:177194.3-177233.6" - wire width 4 $3\src30__data_o$next[3:0]$10697 - attribute \src "libresoc.v:177234.3-177263.6" - wire $3\wr_detect$10[0:0]$10705 - attribute \src "libresoc.v:177304.3-177333.6" - wire $3\wr_detect$13[0:0]$10719 - attribute \src "libresoc.v:176997.3-177026.6" - wire $3\wr_detect$16[0:0]$10657 - attribute \src "libresoc.v:177094.3-177123.6" - wire $3\wr_detect$4[0:0]$10677 - attribute \src "libresoc.v:177164.3-177193.6" - wire $3\wr_detect$7[0:0]$10691 - attribute \src "libresoc.v:176927.3-176956.6" + attribute \src "libresoc.v:178195.3-178234.6" + wire width 4 $3\cr_pred0__data_o$next[3:0]$10624 + attribute \src "libresoc.v:178572.3-178611.6" + wire width 4 $3\r0__data_o$next[3:0]$10695 + attribute \src "libresoc.v:178265.3-178304.6" + wire width 4 $3\r20__data_o$next[3:0]$10633 + attribute \src "libresoc.v:178335.3-178361.6" + wire width 4 $3\reg$next[3:0]$10647 + attribute \src "libresoc.v:178362.3-178401.6" + wire width 4 $3\src10__data_o$next[3:0]$10653 + attribute \src "libresoc.v:178432.3-178471.6" + wire width 4 $3\src20__data_o$next[3:0]$10667 + attribute \src "libresoc.v:178502.3-178541.6" + wire width 4 $3\src30__data_o$next[3:0]$10681 + attribute \src "libresoc.v:178542.3-178571.6" + wire $3\wr_detect$10[0:0]$10689 + attribute \src "libresoc.v:178612.3-178641.6" + wire $3\wr_detect$13[0:0]$10703 + attribute \src "libresoc.v:178305.3-178334.6" + wire $3\wr_detect$16[0:0]$10641 + attribute \src "libresoc.v:178402.3-178431.6" + wire $3\wr_detect$4[0:0]$10661 + attribute \src "libresoc.v:178472.3-178501.6" + wire $3\wr_detect$7[0:0]$10675 + attribute \src "libresoc.v:178235.3-178264.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:176887.3-176926.6" - wire width 4 $4\cr_pred0__data_o$next[3:0]$10641 - attribute \src "libresoc.v:177264.3-177303.6" - wire width 4 $4\r0__data_o$next[3:0]$10712 - attribute \src "libresoc.v:176957.3-176996.6" - wire width 4 $4\r20__data_o$next[3:0]$10650 - attribute \src "libresoc.v:177027.3-177053.6" - wire width 4 $4\reg$next[3:0]$10664 - attribute \src "libresoc.v:177054.3-177093.6" - wire width 4 $4\src10__data_o$next[3:0]$10670 - attribute \src "libresoc.v:177124.3-177163.6" - wire width 4 $4\src20__data_o$next[3:0]$10684 - attribute \src "libresoc.v:177194.3-177233.6" - wire width 4 $4\src30__data_o$next[3:0]$10698 - attribute \src "libresoc.v:177234.3-177263.6" - wire $4\wr_detect$10[0:0]$10706 - attribute \src "libresoc.v:177304.3-177333.6" - wire $4\wr_detect$13[0:0]$10720 - attribute \src "libresoc.v:176997.3-177026.6" - wire $4\wr_detect$16[0:0]$10658 - attribute \src "libresoc.v:177094.3-177123.6" - wire $4\wr_detect$4[0:0]$10678 - attribute \src "libresoc.v:177164.3-177193.6" - wire $4\wr_detect$7[0:0]$10692 - attribute \src "libresoc.v:176927.3-176956.6" + attribute \src "libresoc.v:178195.3-178234.6" + wire width 4 $4\cr_pred0__data_o$next[3:0]$10625 + attribute \src "libresoc.v:178572.3-178611.6" + wire width 4 $4\r0__data_o$next[3:0]$10696 + attribute \src "libresoc.v:178265.3-178304.6" + wire width 4 $4\r20__data_o$next[3:0]$10634 + attribute \src "libresoc.v:178335.3-178361.6" + wire width 4 $4\reg$next[3:0]$10648 + attribute \src "libresoc.v:178362.3-178401.6" + wire width 4 $4\src10__data_o$next[3:0]$10654 + attribute \src "libresoc.v:178432.3-178471.6" + wire width 4 $4\src20__data_o$next[3:0]$10668 + attribute \src "libresoc.v:178502.3-178541.6" + wire width 4 $4\src30__data_o$next[3:0]$10682 + attribute \src "libresoc.v:178542.3-178571.6" + wire $4\wr_detect$10[0:0]$10690 + attribute \src "libresoc.v:178612.3-178641.6" + wire $4\wr_detect$13[0:0]$10704 + attribute \src "libresoc.v:178305.3-178334.6" + wire $4\wr_detect$16[0:0]$10642 + attribute \src "libresoc.v:178402.3-178431.6" + wire $4\wr_detect$4[0:0]$10662 + attribute \src "libresoc.v:178472.3-178501.6" + wire $4\wr_detect$7[0:0]$10676 + attribute \src "libresoc.v:178235.3-178264.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:176887.3-176926.6" - wire width 4 $5\cr_pred0__data_o$next[3:0]$10642 - attribute \src "libresoc.v:177264.3-177303.6" - wire width 4 $5\r0__data_o$next[3:0]$10713 - attribute \src "libresoc.v:176957.3-176996.6" - wire width 4 $5\r20__data_o$next[3:0]$10651 - attribute \src "libresoc.v:177054.3-177093.6" - wire width 4 $5\src10__data_o$next[3:0]$10671 - attribute \src "libresoc.v:177124.3-177163.6" - wire width 4 $5\src20__data_o$next[3:0]$10685 - attribute \src "libresoc.v:177194.3-177233.6" - wire width 4 $5\src30__data_o$next[3:0]$10699 - attribute \src "libresoc.v:176887.3-176926.6" - wire width 4 $6\cr_pred0__data_o$next[3:0]$10643 - attribute \src "libresoc.v:177264.3-177303.6" - wire width 4 $6\r0__data_o$next[3:0]$10714 - attribute \src "libresoc.v:176957.3-176996.6" - wire width 4 $6\r20__data_o$next[3:0]$10652 - attribute \src "libresoc.v:177054.3-177093.6" - wire width 4 $6\src10__data_o$next[3:0]$10672 - attribute \src "libresoc.v:177124.3-177163.6" - wire width 4 $6\src20__data_o$next[3:0]$10686 - attribute \src "libresoc.v:177194.3-177233.6" - wire width 4 $6\src30__data_o$next[3:0]$10700 - attribute \src "libresoc.v:176867.17-176867.104" - wire $not$libresoc.v:176867$10623_Y - attribute \src "libresoc.v:176868.18-176868.105" - wire $not$libresoc.v:176868$10624_Y - attribute \src "libresoc.v:176869.18-176869.105" - wire $not$libresoc.v:176869$10625_Y - attribute \src "libresoc.v:176870.17-176870.100" - wire $not$libresoc.v:176870$10626_Y - attribute \src "libresoc.v:176871.17-176871.103" - wire $not$libresoc.v:176871$10627_Y - attribute \src "libresoc.v:176872.17-176872.103" - wire $not$libresoc.v:176872$10628_Y + attribute \src "libresoc.v:178195.3-178234.6" + wire width 4 $5\cr_pred0__data_o$next[3:0]$10626 + attribute \src "libresoc.v:178572.3-178611.6" + wire width 4 $5\r0__data_o$next[3:0]$10697 + attribute \src "libresoc.v:178265.3-178304.6" + wire width 4 $5\r20__data_o$next[3:0]$10635 + attribute \src "libresoc.v:178362.3-178401.6" + wire width 4 $5\src10__data_o$next[3:0]$10655 + attribute \src "libresoc.v:178432.3-178471.6" + wire width 4 $5\src20__data_o$next[3:0]$10669 + attribute \src "libresoc.v:178502.3-178541.6" + wire width 4 $5\src30__data_o$next[3:0]$10683 + attribute \src "libresoc.v:178195.3-178234.6" + wire width 4 $6\cr_pred0__data_o$next[3:0]$10627 + attribute \src "libresoc.v:178572.3-178611.6" + wire width 4 $6\r0__data_o$next[3:0]$10698 + attribute \src "libresoc.v:178265.3-178304.6" + wire width 4 $6\r20__data_o$next[3:0]$10636 + attribute \src "libresoc.v:178362.3-178401.6" + wire width 4 $6\src10__data_o$next[3:0]$10656 + attribute \src "libresoc.v:178432.3-178471.6" + wire width 4 $6\src20__data_o$next[3:0]$10670 + attribute \src "libresoc.v:178502.3-178541.6" + wire width 4 $6\src30__data_o$next[3:0]$10684 + attribute \src "libresoc.v:178175.17-178175.104" + wire $not$libresoc.v:178175$10607_Y + attribute \src "libresoc.v:178176.18-178176.105" + wire $not$libresoc.v:178176$10608_Y + attribute \src "libresoc.v:178177.18-178177.105" + wire $not$libresoc.v:178177$10609_Y + attribute \src "libresoc.v:178178.17-178178.100" + wire $not$libresoc.v:178178$10610_Y + attribute \src "libresoc.v:178179.17-178179.103" + wire $not$libresoc.v:178179$10611_Y + attribute \src "libresoc.v:178180.17-178180.103" + wire $not$libresoc.v:178180$10612_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -359873,9 +331243,9 @@ module \reg_0 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 20 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 3 \cr_pred0__data_o @@ -359891,7 +331261,7 @@ module \reg_0 wire width 4 input 13 \dest20__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest20__wen - attribute \src "libresoc.v:176780.7-176780.15" + attribute \src "libresoc.v:178088.7-178088.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 14 \r0__data_o @@ -359944,175 +331314,175 @@ module \reg_0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176867$10623 + cell $not $not$libresoc.v:178175$10607 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:176867$10623_Y + connect \Y $not$libresoc.v:178175$10607_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176868$10624 + cell $not $not$libresoc.v:178176$10608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:176868$10624_Y + connect \Y $not$libresoc.v:178176$10608_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176869$10625 + cell $not $not$libresoc.v:178177$10609 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$16 - connect \Y $not$libresoc.v:176869$10625_Y + connect \Y $not$libresoc.v:178177$10609_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176870$10626 + cell $not $not$libresoc.v:178178$10610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:176870$10626_Y + connect \Y $not$libresoc.v:178178$10610_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176871$10627 + cell $not $not$libresoc.v:178179$10611 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:176871$10627_Y + connect \Y $not$libresoc.v:178179$10611_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:176872$10628 + cell $not $not$libresoc.v:178180$10612 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:176872$10628_Y + connect \Y $not$libresoc.v:178180$10612_Y end - attribute \src "libresoc.v:176780.7-176780.20" - process $proc$libresoc.v:176780$10721 + attribute \src "libresoc.v:178088.7-178088.20" + process $proc$libresoc.v:178088$10705 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:176799.13-176799.36" - process $proc$libresoc.v:176799$10722 + attribute \src "libresoc.v:178107.13-178107.36" + process $proc$libresoc.v:178107$10706 assign { } { } assign $1\cr_pred0__data_o[3:0] 4'0000 sync always sync init update \cr_pred0__data_o $1\cr_pred0__data_o[3:0] end - attribute \src "libresoc.v:176814.13-176814.30" - process $proc$libresoc.v:176814$10723 + attribute \src "libresoc.v:178122.13-178122.30" + process $proc$libresoc.v:178122$10707 assign { } { } assign $1\r0__data_o[3:0] 4'0000 sync always sync init update \r0__data_o $1\r0__data_o[3:0] end - attribute \src "libresoc.v:176821.13-176821.31" - process $proc$libresoc.v:176821$10724 + attribute \src "libresoc.v:178129.13-178129.31" + process $proc$libresoc.v:178129$10708 assign { } { } assign $1\r20__data_o[3:0] 4'0000 sync always sync init update \r20__data_o $1\r20__data_o[3:0] end - attribute \src "libresoc.v:176827.13-176827.25" - process $proc$libresoc.v:176827$10725 + attribute \src "libresoc.v:178135.13-178135.25" + process $proc$libresoc.v:178135$10709 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:176832.13-176832.33" - process $proc$libresoc.v:176832$10726 + attribute \src "libresoc.v:178140.13-178140.33" + process $proc$libresoc.v:178140$10710 assign { } { } assign $1\src10__data_o[3:0] 4'0000 sync always sync init update \src10__data_o $1\src10__data_o[3:0] end - attribute \src "libresoc.v:176839.13-176839.33" - process $proc$libresoc.v:176839$10727 + attribute \src "libresoc.v:178147.13-178147.33" + process $proc$libresoc.v:178147$10711 assign { } { } assign $1\src20__data_o[3:0] 4'0000 sync always sync init update \src20__data_o $1\src20__data_o[3:0] end - attribute \src "libresoc.v:176846.13-176846.33" - process $proc$libresoc.v:176846$10728 + attribute \src "libresoc.v:178154.13-178154.33" + process $proc$libresoc.v:178154$10712 assign { } { } assign $1\src30__data_o[3:0] 4'0000 sync always sync init update \src30__data_o $1\src30__data_o[3:0] end - attribute \src "libresoc.v:176873.3-176874.25" - process $proc$libresoc.v:176873$10629 + attribute \src "libresoc.v:178181.3-178182.25" + process $proc$libresoc.v:178181$10613 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:176875.3-176876.39" - process $proc$libresoc.v:176875$10630 + attribute \src "libresoc.v:178183.3-178184.39" + process $proc$libresoc.v:178183$10614 assign { } { } assign $0\r20__data_o[3:0] \r20__data_o$next sync posedge \coresync_clk update \r20__data_o $0\r20__data_o[3:0] end - attribute \src "libresoc.v:176877.3-176878.37" - process $proc$libresoc.v:176877$10631 + attribute \src "libresoc.v:178185.3-178186.37" + process $proc$libresoc.v:178185$10615 assign { } { } assign $0\r0__data_o[3:0] \r0__data_o$next sync posedge \coresync_clk update \r0__data_o $0\r0__data_o[3:0] end - attribute \src "libresoc.v:176879.3-176880.43" - process $proc$libresoc.v:176879$10632 + attribute \src "libresoc.v:178187.3-178188.43" + process $proc$libresoc.v:178187$10616 assign { } { } assign $0\src30__data_o[3:0] \src30__data_o$next sync posedge \coresync_clk update \src30__data_o $0\src30__data_o[3:0] end - attribute \src "libresoc.v:176881.3-176882.43" - process $proc$libresoc.v:176881$10633 + attribute \src "libresoc.v:178189.3-178190.43" + process $proc$libresoc.v:178189$10617 assign { } { } assign $0\src20__data_o[3:0] \src20__data_o$next sync posedge \coresync_clk update \src20__data_o $0\src20__data_o[3:0] end - attribute \src "libresoc.v:176883.3-176884.43" - process $proc$libresoc.v:176883$10634 + attribute \src "libresoc.v:178191.3-178192.43" + process $proc$libresoc.v:178191$10618 assign { } { } assign $0\src10__data_o[3:0] \src10__data_o$next sync posedge \coresync_clk update \src10__data_o $0\src10__data_o[3:0] end - attribute \src "libresoc.v:176885.3-176886.49" - process $proc$libresoc.v:176885$10635 + attribute \src "libresoc.v:178193.3-178194.49" + process $proc$libresoc.v:178193$10619 assign { } { } assign $0\cr_pred0__data_o[3:0] \cr_pred0__data_o$next sync posedge \coresync_clk update \cr_pred0__data_o $0\cr_pred0__data_o[3:0] end - attribute \src "libresoc.v:176887.3-176926.6" - process $proc$libresoc.v:176887$10636 + attribute \src "libresoc.v:178195.3-178234.6" + process $proc$libresoc.v:178195$10620 assign { } { } assign { } { } assign { } { } - assign $0\cr_pred0__data_o$next[3:0]$10637 $6\cr_pred0__data_o$next[3:0]$10643 - attribute \src "libresoc.v:176888.5-176888.29" + assign $0\cr_pred0__data_o$next[3:0]$10621 $6\cr_pred0__data_o$next[3:0]$10627 + attribute \src "libresoc.v:178196.5-178196.29" switch \initial - attribute \src "libresoc.v:176888.9-176888.17" + attribute \src "libresoc.v:178196.9-178196.17" case 1'1 case end @@ -360124,66 +331494,66 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\cr_pred0__data_o$next[3:0]$10638 $5\cr_pred0__data_o$next[3:0]$10642 + assign $1\cr_pred0__data_o$next[3:0]$10622 $5\cr_pred0__data_o$next[3:0]$10626 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_pred0__data_o$next[3:0]$10639 \dest10__data_i + assign $2\cr_pred0__data_o$next[3:0]$10623 \dest10__data_i case - assign $2\cr_pred0__data_o$next[3:0]$10639 4'0000 + assign $2\cr_pred0__data_o$next[3:0]$10623 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\cr_pred0__data_o$next[3:0]$10640 \dest20__data_i + assign $3\cr_pred0__data_o$next[3:0]$10624 \dest20__data_i case - assign $3\cr_pred0__data_o$next[3:0]$10640 $2\cr_pred0__data_o$next[3:0]$10639 + assign $3\cr_pred0__data_o$next[3:0]$10624 $2\cr_pred0__data_o$next[3:0]$10623 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cr_pred0__data_o$next[3:0]$10641 \w0__data_i + assign $4\cr_pred0__data_o$next[3:0]$10625 \w0__data_i case - assign $4\cr_pred0__data_o$next[3:0]$10641 $3\cr_pred0__data_o$next[3:0]$10640 + assign $4\cr_pred0__data_o$next[3:0]$10625 $3\cr_pred0__data_o$next[3:0]$10624 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\cr_pred0__data_o$next[3:0]$10642 \reg + assign $5\cr_pred0__data_o$next[3:0]$10626 \reg case - assign $5\cr_pred0__data_o$next[3:0]$10642 $4\cr_pred0__data_o$next[3:0]$10641 + assign $5\cr_pred0__data_o$next[3:0]$10626 $4\cr_pred0__data_o$next[3:0]$10625 end case - assign $1\cr_pred0__data_o$next[3:0]$10638 4'0000 + assign $1\cr_pred0__data_o$next[3:0]$10622 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cr_pred0__data_o$next[3:0]$10643 4'0000 + assign $6\cr_pred0__data_o$next[3:0]$10627 4'0000 case - assign $6\cr_pred0__data_o$next[3:0]$10643 $1\cr_pred0__data_o$next[3:0]$10638 + assign $6\cr_pred0__data_o$next[3:0]$10627 $1\cr_pred0__data_o$next[3:0]$10622 end sync always - update \cr_pred0__data_o$next $0\cr_pred0__data_o$next[3:0]$10637 + update \cr_pred0__data_o$next $0\cr_pred0__data_o$next[3:0]$10621 end - attribute \src "libresoc.v:176927.3-176956.6" - process $proc$libresoc.v:176927$10644 + attribute \src "libresoc.v:178235.3-178264.6" + process $proc$libresoc.v:178235$10628 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:176928.5-176928.29" + attribute \src "libresoc.v:178236.5-178236.29" switch \initial - attribute \src "libresoc.v:176928.9-176928.17" + attribute \src "libresoc.v:178236.9-178236.17" case 1'1 case end @@ -360229,15 +331599,15 @@ module \reg_0 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:176957.3-176996.6" - process $proc$libresoc.v:176957$10645 + attribute \src "libresoc.v:178265.3-178304.6" + process $proc$libresoc.v:178265$10629 assign { } { } assign { } { } assign { } { } - assign $0\r20__data_o$next[3:0]$10646 $6\r20__data_o$next[3:0]$10652 - attribute \src "libresoc.v:176958.5-176958.29" + assign $0\r20__data_o$next[3:0]$10630 $6\r20__data_o$next[3:0]$10636 + attribute \src "libresoc.v:178266.5-178266.29" switch \initial - attribute \src "libresoc.v:176958.9-176958.17" + attribute \src "libresoc.v:178266.9-178266.17" case 1'1 case end @@ -360249,66 +331619,66 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\r20__data_o$next[3:0]$10647 $5\r20__data_o$next[3:0]$10651 + assign $1\r20__data_o$next[3:0]$10631 $5\r20__data_o$next[3:0]$10635 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r20__data_o$next[3:0]$10648 \dest10__data_i + assign $2\r20__data_o$next[3:0]$10632 \dest10__data_i case - assign $2\r20__data_o$next[3:0]$10648 4'0000 + assign $2\r20__data_o$next[3:0]$10632 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r20__data_o$next[3:0]$10649 \dest20__data_i + assign $3\r20__data_o$next[3:0]$10633 \dest20__data_i case - assign $3\r20__data_o$next[3:0]$10649 $2\r20__data_o$next[3:0]$10648 + assign $3\r20__data_o$next[3:0]$10633 $2\r20__data_o$next[3:0]$10632 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r20__data_o$next[3:0]$10650 \w0__data_i + assign $4\r20__data_o$next[3:0]$10634 \w0__data_i case - assign $4\r20__data_o$next[3:0]$10650 $3\r20__data_o$next[3:0]$10649 + assign $4\r20__data_o$next[3:0]$10634 $3\r20__data_o$next[3:0]$10633 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$15 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r20__data_o$next[3:0]$10651 \reg + assign $5\r20__data_o$next[3:0]$10635 \reg case - assign $5\r20__data_o$next[3:0]$10651 $4\r20__data_o$next[3:0]$10650 + assign $5\r20__data_o$next[3:0]$10635 $4\r20__data_o$next[3:0]$10634 end case - assign $1\r20__data_o$next[3:0]$10647 4'0000 + assign $1\r20__data_o$next[3:0]$10631 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r20__data_o$next[3:0]$10652 4'0000 + assign $6\r20__data_o$next[3:0]$10636 4'0000 case - assign $6\r20__data_o$next[3:0]$10652 $1\r20__data_o$next[3:0]$10647 + assign $6\r20__data_o$next[3:0]$10636 $1\r20__data_o$next[3:0]$10631 end sync always - update \r20__data_o$next $0\r20__data_o$next[3:0]$10646 + update \r20__data_o$next $0\r20__data_o$next[3:0]$10630 end - attribute \src "libresoc.v:176997.3-177026.6" - process $proc$libresoc.v:176997$10653 + attribute \src "libresoc.v:178305.3-178334.6" + process $proc$libresoc.v:178305$10637 assign { } { } assign { } { } - assign $0\wr_detect$16[0:0]$10654 $1\wr_detect$16[0:0]$10655 - attribute \src "libresoc.v:176998.5-176998.29" + assign $0\wr_detect$16[0:0]$10638 $1\wr_detect$16[0:0]$10639 + attribute \src "libresoc.v:178306.5-178306.29" switch \initial - attribute \src "libresoc.v:176998.9-176998.17" + attribute \src "libresoc.v:178306.9-178306.17" case 1'1 case end @@ -360320,51 +331690,51 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$16[0:0]$10655 $4\wr_detect$16[0:0]$10658 + assign $1\wr_detect$16[0:0]$10639 $4\wr_detect$16[0:0]$10642 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$16[0:0]$10656 1'1 + assign $2\wr_detect$16[0:0]$10640 1'1 case - assign $2\wr_detect$16[0:0]$10656 1'0 + assign $2\wr_detect$16[0:0]$10640 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$16[0:0]$10657 1'1 + assign $3\wr_detect$16[0:0]$10641 1'1 case - assign $3\wr_detect$16[0:0]$10657 $2\wr_detect$16[0:0]$10656 + assign $3\wr_detect$16[0:0]$10641 $2\wr_detect$16[0:0]$10640 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$16[0:0]$10658 1'1 + assign $4\wr_detect$16[0:0]$10642 1'1 case - assign $4\wr_detect$16[0:0]$10658 $3\wr_detect$16[0:0]$10657 + assign $4\wr_detect$16[0:0]$10642 $3\wr_detect$16[0:0]$10641 end case - assign $1\wr_detect$16[0:0]$10655 1'0 + assign $1\wr_detect$16[0:0]$10639 1'0 end sync always - update \wr_detect$16 $0\wr_detect$16[0:0]$10654 + update \wr_detect$16 $0\wr_detect$16[0:0]$10638 end - attribute \src "libresoc.v:177027.3-177053.6" - process $proc$libresoc.v:177027$10659 + attribute \src "libresoc.v:178335.3-178361.6" + process $proc$libresoc.v:178335$10643 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$10660 $4\reg$next[3:0]$10664 - attribute \src "libresoc.v:177028.5-177028.29" + assign $0\reg$next[3:0]$10644 $4\reg$next[3:0]$10648 + attribute \src "libresoc.v:178336.5-178336.29" switch \initial - attribute \src "libresoc.v:177028.9-177028.17" + attribute \src "libresoc.v:178336.9-178336.17" case 1'1 case end @@ -360373,49 +331743,49 @@ module \reg_0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$10661 \dest10__data_i + assign $1\reg$next[3:0]$10645 \dest10__data_i case - assign $1\reg$next[3:0]$10661 \reg + assign $1\reg$next[3:0]$10645 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$10662 \dest20__data_i + assign $2\reg$next[3:0]$10646 \dest20__data_i case - assign $2\reg$next[3:0]$10662 $1\reg$next[3:0]$10661 + assign $2\reg$next[3:0]$10646 $1\reg$next[3:0]$10645 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$10663 \w0__data_i + assign $3\reg$next[3:0]$10647 \w0__data_i case - assign $3\reg$next[3:0]$10663 $2\reg$next[3:0]$10662 + assign $3\reg$next[3:0]$10647 $2\reg$next[3:0]$10646 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$10664 4'0000 + assign $4\reg$next[3:0]$10648 4'0000 case - assign $4\reg$next[3:0]$10664 $3\reg$next[3:0]$10663 + assign $4\reg$next[3:0]$10648 $3\reg$next[3:0]$10647 end sync always - update \reg$next $0\reg$next[3:0]$10660 + update \reg$next $0\reg$next[3:0]$10644 end - attribute \src "libresoc.v:177054.3-177093.6" - process $proc$libresoc.v:177054$10665 + attribute \src "libresoc.v:178362.3-178401.6" + process $proc$libresoc.v:178362$10649 assign { } { } assign { } { } assign { } { } - assign $0\src10__data_o$next[3:0]$10666 $6\src10__data_o$next[3:0]$10672 - attribute \src "libresoc.v:177055.5-177055.29" + assign $0\src10__data_o$next[3:0]$10650 $6\src10__data_o$next[3:0]$10656 + attribute \src "libresoc.v:178363.5-178363.29" switch \initial - attribute \src "libresoc.v:177055.9-177055.17" + attribute \src "libresoc.v:178363.9-178363.17" case 1'1 case end @@ -360427,66 +331797,66 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\src10__data_o$next[3:0]$10667 $5\src10__data_o$next[3:0]$10671 + assign $1\src10__data_o$next[3:0]$10651 $5\src10__data_o$next[3:0]$10655 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src10__data_o$next[3:0]$10668 \dest10__data_i + assign $2\src10__data_o$next[3:0]$10652 \dest10__data_i case - assign $2\src10__data_o$next[3:0]$10668 4'0000 + assign $2\src10__data_o$next[3:0]$10652 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src10__data_o$next[3:0]$10669 \dest20__data_i + assign $3\src10__data_o$next[3:0]$10653 \dest20__data_i case - assign $3\src10__data_o$next[3:0]$10669 $2\src10__data_o$next[3:0]$10668 + assign $3\src10__data_o$next[3:0]$10653 $2\src10__data_o$next[3:0]$10652 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src10__data_o$next[3:0]$10670 \w0__data_i + assign $4\src10__data_o$next[3:0]$10654 \w0__data_i case - assign $4\src10__data_o$next[3:0]$10670 $3\src10__data_o$next[3:0]$10669 + assign $4\src10__data_o$next[3:0]$10654 $3\src10__data_o$next[3:0]$10653 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src10__data_o$next[3:0]$10671 \reg + assign $5\src10__data_o$next[3:0]$10655 \reg case - assign $5\src10__data_o$next[3:0]$10671 $4\src10__data_o$next[3:0]$10670 + assign $5\src10__data_o$next[3:0]$10655 $4\src10__data_o$next[3:0]$10654 end case - assign $1\src10__data_o$next[3:0]$10667 4'0000 + assign $1\src10__data_o$next[3:0]$10651 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src10__data_o$next[3:0]$10672 4'0000 + assign $6\src10__data_o$next[3:0]$10656 4'0000 case - assign $6\src10__data_o$next[3:0]$10672 $1\src10__data_o$next[3:0]$10667 + assign $6\src10__data_o$next[3:0]$10656 $1\src10__data_o$next[3:0]$10651 end sync always - update \src10__data_o$next $0\src10__data_o$next[3:0]$10666 + update \src10__data_o$next $0\src10__data_o$next[3:0]$10650 end - attribute \src "libresoc.v:177094.3-177123.6" - process $proc$libresoc.v:177094$10673 + attribute \src "libresoc.v:178402.3-178431.6" + process $proc$libresoc.v:178402$10657 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10674 $1\wr_detect$4[0:0]$10675 - attribute \src "libresoc.v:177095.5-177095.29" + assign $0\wr_detect$4[0:0]$10658 $1\wr_detect$4[0:0]$10659 + attribute \src "libresoc.v:178403.5-178403.29" switch \initial - attribute \src "libresoc.v:177095.9-177095.17" + attribute \src "libresoc.v:178403.9-178403.17" case 1'1 case end @@ -360498,49 +331868,49 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10675 $4\wr_detect$4[0:0]$10678 + assign $1\wr_detect$4[0:0]$10659 $4\wr_detect$4[0:0]$10662 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10676 1'1 + assign $2\wr_detect$4[0:0]$10660 1'1 case - assign $2\wr_detect$4[0:0]$10676 1'0 + assign $2\wr_detect$4[0:0]$10660 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10677 1'1 + assign $3\wr_detect$4[0:0]$10661 1'1 case - assign $3\wr_detect$4[0:0]$10677 $2\wr_detect$4[0:0]$10676 + assign $3\wr_detect$4[0:0]$10661 $2\wr_detect$4[0:0]$10660 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10678 1'1 + assign $4\wr_detect$4[0:0]$10662 1'1 case - assign $4\wr_detect$4[0:0]$10678 $3\wr_detect$4[0:0]$10677 + assign $4\wr_detect$4[0:0]$10662 $3\wr_detect$4[0:0]$10661 end case - assign $1\wr_detect$4[0:0]$10675 1'0 + assign $1\wr_detect$4[0:0]$10659 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10674 + update \wr_detect$4 $0\wr_detect$4[0:0]$10658 end - attribute \src "libresoc.v:177124.3-177163.6" - process $proc$libresoc.v:177124$10679 + attribute \src "libresoc.v:178432.3-178471.6" + process $proc$libresoc.v:178432$10663 assign { } { } assign { } { } assign { } { } - assign $0\src20__data_o$next[3:0]$10680 $6\src20__data_o$next[3:0]$10686 - attribute \src "libresoc.v:177125.5-177125.29" + assign $0\src20__data_o$next[3:0]$10664 $6\src20__data_o$next[3:0]$10670 + attribute \src "libresoc.v:178433.5-178433.29" switch \initial - attribute \src "libresoc.v:177125.9-177125.17" + attribute \src "libresoc.v:178433.9-178433.17" case 1'1 case end @@ -360552,66 +331922,66 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\src20__data_o$next[3:0]$10681 $5\src20__data_o$next[3:0]$10685 + assign $1\src20__data_o$next[3:0]$10665 $5\src20__data_o$next[3:0]$10669 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src20__data_o$next[3:0]$10682 \dest10__data_i + assign $2\src20__data_o$next[3:0]$10666 \dest10__data_i case - assign $2\src20__data_o$next[3:0]$10682 4'0000 + assign $2\src20__data_o$next[3:0]$10666 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src20__data_o$next[3:0]$10683 \dest20__data_i + assign $3\src20__data_o$next[3:0]$10667 \dest20__data_i case - assign $3\src20__data_o$next[3:0]$10683 $2\src20__data_o$next[3:0]$10682 + assign $3\src20__data_o$next[3:0]$10667 $2\src20__data_o$next[3:0]$10666 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src20__data_o$next[3:0]$10684 \w0__data_i + assign $4\src20__data_o$next[3:0]$10668 \w0__data_i case - assign $4\src20__data_o$next[3:0]$10684 $3\src20__data_o$next[3:0]$10683 + assign $4\src20__data_o$next[3:0]$10668 $3\src20__data_o$next[3:0]$10667 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src20__data_o$next[3:0]$10685 \reg + assign $5\src20__data_o$next[3:0]$10669 \reg case - assign $5\src20__data_o$next[3:0]$10685 $4\src20__data_o$next[3:0]$10684 + assign $5\src20__data_o$next[3:0]$10669 $4\src20__data_o$next[3:0]$10668 end case - assign $1\src20__data_o$next[3:0]$10681 4'0000 + assign $1\src20__data_o$next[3:0]$10665 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src20__data_o$next[3:0]$10686 4'0000 + assign $6\src20__data_o$next[3:0]$10670 4'0000 case - assign $6\src20__data_o$next[3:0]$10686 $1\src20__data_o$next[3:0]$10681 + assign $6\src20__data_o$next[3:0]$10670 $1\src20__data_o$next[3:0]$10665 end sync always - update \src20__data_o$next $0\src20__data_o$next[3:0]$10680 + update \src20__data_o$next $0\src20__data_o$next[3:0]$10664 end - attribute \src "libresoc.v:177164.3-177193.6" - process $proc$libresoc.v:177164$10687 + attribute \src "libresoc.v:178472.3-178501.6" + process $proc$libresoc.v:178472$10671 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10688 $1\wr_detect$7[0:0]$10689 - attribute \src "libresoc.v:177165.5-177165.29" + assign $0\wr_detect$7[0:0]$10672 $1\wr_detect$7[0:0]$10673 + attribute \src "libresoc.v:178473.5-178473.29" switch \initial - attribute \src "libresoc.v:177165.9-177165.17" + attribute \src "libresoc.v:178473.9-178473.17" case 1'1 case end @@ -360623,49 +331993,49 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10689 $4\wr_detect$7[0:0]$10692 + assign $1\wr_detect$7[0:0]$10673 $4\wr_detect$7[0:0]$10676 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10690 1'1 + assign $2\wr_detect$7[0:0]$10674 1'1 case - assign $2\wr_detect$7[0:0]$10690 1'0 + assign $2\wr_detect$7[0:0]$10674 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$10691 1'1 + assign $3\wr_detect$7[0:0]$10675 1'1 case - assign $3\wr_detect$7[0:0]$10691 $2\wr_detect$7[0:0]$10690 + assign $3\wr_detect$7[0:0]$10675 $2\wr_detect$7[0:0]$10674 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$10692 1'1 + assign $4\wr_detect$7[0:0]$10676 1'1 case - assign $4\wr_detect$7[0:0]$10692 $3\wr_detect$7[0:0]$10691 + assign $4\wr_detect$7[0:0]$10676 $3\wr_detect$7[0:0]$10675 end case - assign $1\wr_detect$7[0:0]$10689 1'0 + assign $1\wr_detect$7[0:0]$10673 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10688 + update \wr_detect$7 $0\wr_detect$7[0:0]$10672 end - attribute \src "libresoc.v:177194.3-177233.6" - process $proc$libresoc.v:177194$10693 + attribute \src "libresoc.v:178502.3-178541.6" + process $proc$libresoc.v:178502$10677 assign { } { } assign { } { } assign { } { } - assign $0\src30__data_o$next[3:0]$10694 $6\src30__data_o$next[3:0]$10700 - attribute \src "libresoc.v:177195.5-177195.29" + assign $0\src30__data_o$next[3:0]$10678 $6\src30__data_o$next[3:0]$10684 + attribute \src "libresoc.v:178503.5-178503.29" switch \initial - attribute \src "libresoc.v:177195.9-177195.17" + attribute \src "libresoc.v:178503.9-178503.17" case 1'1 case end @@ -360677,66 +332047,66 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\src30__data_o$next[3:0]$10695 $5\src30__data_o$next[3:0]$10699 + assign $1\src30__data_o$next[3:0]$10679 $5\src30__data_o$next[3:0]$10683 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src30__data_o$next[3:0]$10696 \dest10__data_i + assign $2\src30__data_o$next[3:0]$10680 \dest10__data_i case - assign $2\src30__data_o$next[3:0]$10696 4'0000 + assign $2\src30__data_o$next[3:0]$10680 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src30__data_o$next[3:0]$10697 \dest20__data_i + assign $3\src30__data_o$next[3:0]$10681 \dest20__data_i case - assign $3\src30__data_o$next[3:0]$10697 $2\src30__data_o$next[3:0]$10696 + assign $3\src30__data_o$next[3:0]$10681 $2\src30__data_o$next[3:0]$10680 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src30__data_o$next[3:0]$10698 \w0__data_i + assign $4\src30__data_o$next[3:0]$10682 \w0__data_i case - assign $4\src30__data_o$next[3:0]$10698 $3\src30__data_o$next[3:0]$10697 + assign $4\src30__data_o$next[3:0]$10682 $3\src30__data_o$next[3:0]$10681 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src30__data_o$next[3:0]$10699 \reg + assign $5\src30__data_o$next[3:0]$10683 \reg case - assign $5\src30__data_o$next[3:0]$10699 $4\src30__data_o$next[3:0]$10698 + assign $5\src30__data_o$next[3:0]$10683 $4\src30__data_o$next[3:0]$10682 end case - assign $1\src30__data_o$next[3:0]$10695 4'0000 + assign $1\src30__data_o$next[3:0]$10679 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src30__data_o$next[3:0]$10700 4'0000 + assign $6\src30__data_o$next[3:0]$10684 4'0000 case - assign $6\src30__data_o$next[3:0]$10700 $1\src30__data_o$next[3:0]$10695 + assign $6\src30__data_o$next[3:0]$10684 $1\src30__data_o$next[3:0]$10679 end sync always - update \src30__data_o$next $0\src30__data_o$next[3:0]$10694 + update \src30__data_o$next $0\src30__data_o$next[3:0]$10678 end - attribute \src "libresoc.v:177234.3-177263.6" - process $proc$libresoc.v:177234$10701 + attribute \src "libresoc.v:178542.3-178571.6" + process $proc$libresoc.v:178542$10685 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$10702 $1\wr_detect$10[0:0]$10703 - attribute \src "libresoc.v:177235.5-177235.29" + assign $0\wr_detect$10[0:0]$10686 $1\wr_detect$10[0:0]$10687 + attribute \src "libresoc.v:178543.5-178543.29" switch \initial - attribute \src "libresoc.v:177235.9-177235.17" + attribute \src "libresoc.v:178543.9-178543.17" case 1'1 case end @@ -360748,49 +332118,49 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$10703 $4\wr_detect$10[0:0]$10706 + assign $1\wr_detect$10[0:0]$10687 $4\wr_detect$10[0:0]$10690 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$10704 1'1 + assign $2\wr_detect$10[0:0]$10688 1'1 case - assign $2\wr_detect$10[0:0]$10704 1'0 + assign $2\wr_detect$10[0:0]$10688 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$10705 1'1 + assign $3\wr_detect$10[0:0]$10689 1'1 case - assign $3\wr_detect$10[0:0]$10705 $2\wr_detect$10[0:0]$10704 + assign $3\wr_detect$10[0:0]$10689 $2\wr_detect$10[0:0]$10688 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$10706 1'1 + assign $4\wr_detect$10[0:0]$10690 1'1 case - assign $4\wr_detect$10[0:0]$10706 $3\wr_detect$10[0:0]$10705 + assign $4\wr_detect$10[0:0]$10690 $3\wr_detect$10[0:0]$10689 end case - assign $1\wr_detect$10[0:0]$10703 1'0 + assign $1\wr_detect$10[0:0]$10687 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10702 + update \wr_detect$10 $0\wr_detect$10[0:0]$10686 end - attribute \src "libresoc.v:177264.3-177303.6" - process $proc$libresoc.v:177264$10707 + attribute \src "libresoc.v:178572.3-178611.6" + process $proc$libresoc.v:178572$10691 assign { } { } assign { } { } assign { } { } - assign $0\r0__data_o$next[3:0]$10708 $6\r0__data_o$next[3:0]$10714 - attribute \src "libresoc.v:177265.5-177265.29" + assign $0\r0__data_o$next[3:0]$10692 $6\r0__data_o$next[3:0]$10698 + attribute \src "libresoc.v:178573.5-178573.29" switch \initial - attribute \src "libresoc.v:177265.9-177265.17" + attribute \src "libresoc.v:178573.9-178573.17" case 1'1 case end @@ -360802,66 +332172,66 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\r0__data_o$next[3:0]$10709 $5\r0__data_o$next[3:0]$10713 + assign $1\r0__data_o$next[3:0]$10693 $5\r0__data_o$next[3:0]$10697 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r0__data_o$next[3:0]$10710 \dest10__data_i + assign $2\r0__data_o$next[3:0]$10694 \dest10__data_i case - assign $2\r0__data_o$next[3:0]$10710 4'0000 + assign $2\r0__data_o$next[3:0]$10694 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r0__data_o$next[3:0]$10711 \dest20__data_i + assign $3\r0__data_o$next[3:0]$10695 \dest20__data_i case - assign $3\r0__data_o$next[3:0]$10711 $2\r0__data_o$next[3:0]$10710 + assign $3\r0__data_o$next[3:0]$10695 $2\r0__data_o$next[3:0]$10694 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r0__data_o$next[3:0]$10712 \w0__data_i + assign $4\r0__data_o$next[3:0]$10696 \w0__data_i case - assign $4\r0__data_o$next[3:0]$10712 $3\r0__data_o$next[3:0]$10711 + assign $4\r0__data_o$next[3:0]$10696 $3\r0__data_o$next[3:0]$10695 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r0__data_o$next[3:0]$10713 \reg + assign $5\r0__data_o$next[3:0]$10697 \reg case - assign $5\r0__data_o$next[3:0]$10713 $4\r0__data_o$next[3:0]$10712 + assign $5\r0__data_o$next[3:0]$10697 $4\r0__data_o$next[3:0]$10696 end case - assign $1\r0__data_o$next[3:0]$10709 4'0000 + assign $1\r0__data_o$next[3:0]$10693 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r0__data_o$next[3:0]$10714 4'0000 + assign $6\r0__data_o$next[3:0]$10698 4'0000 case - assign $6\r0__data_o$next[3:0]$10714 $1\r0__data_o$next[3:0]$10709 + assign $6\r0__data_o$next[3:0]$10698 $1\r0__data_o$next[3:0]$10693 end sync always - update \r0__data_o$next $0\r0__data_o$next[3:0]$10708 + update \r0__data_o$next $0\r0__data_o$next[3:0]$10692 end - attribute \src "libresoc.v:177304.3-177333.6" - process $proc$libresoc.v:177304$10715 + attribute \src "libresoc.v:178612.3-178641.6" + process $proc$libresoc.v:178612$10699 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$10716 $1\wr_detect$13[0:0]$10717 - attribute \src "libresoc.v:177305.5-177305.29" + assign $0\wr_detect$13[0:0]$10700 $1\wr_detect$13[0:0]$10701 + attribute \src "libresoc.v:178613.5-178613.29" switch \initial - attribute \src "libresoc.v:177305.9-177305.17" + attribute \src "libresoc.v:178613.9-178613.17" case 1'1 case end @@ -360873,206 +332243,206 @@ module \reg_0 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$10717 $4\wr_detect$13[0:0]$10720 + assign $1\wr_detect$13[0:0]$10701 $4\wr_detect$13[0:0]$10704 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$10718 1'1 + assign $2\wr_detect$13[0:0]$10702 1'1 case - assign $2\wr_detect$13[0:0]$10718 1'0 + assign $2\wr_detect$13[0:0]$10702 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$10719 1'1 + assign $3\wr_detect$13[0:0]$10703 1'1 case - assign $3\wr_detect$13[0:0]$10719 $2\wr_detect$13[0:0]$10718 + assign $3\wr_detect$13[0:0]$10703 $2\wr_detect$13[0:0]$10702 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$10720 1'1 + assign $4\wr_detect$13[0:0]$10704 1'1 case - assign $4\wr_detect$13[0:0]$10720 $3\wr_detect$13[0:0]$10719 + assign $4\wr_detect$13[0:0]$10704 $3\wr_detect$13[0:0]$10703 end case - assign $1\wr_detect$13[0:0]$10717 1'0 + assign $1\wr_detect$13[0:0]$10701 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$10716 + update \wr_detect$13 $0\wr_detect$13[0:0]$10700 end - connect \$9 $not$libresoc.v:176867$10623_Y - connect \$12 $not$libresoc.v:176868$10624_Y - connect \$15 $not$libresoc.v:176869$10625_Y - connect \$1 $not$libresoc.v:176870$10626_Y - connect \$3 $not$libresoc.v:176871$10627_Y - connect \$6 $not$libresoc.v:176872$10628_Y + connect \$9 $not$libresoc.v:178175$10607_Y + connect \$12 $not$libresoc.v:178176$10608_Y + connect \$15 $not$libresoc.v:178177$10609_Y + connect \$1 $not$libresoc.v:178178$10610_Y + connect \$3 $not$libresoc.v:178179$10611_Y + connect \$6 $not$libresoc.v:178180$10612_Y end -attribute \src "libresoc.v:177338.1-177783.10" +attribute \src "libresoc.v:178646.1-179091.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_0" attribute \generator "nMigen" module \reg_0$132 - attribute \src "libresoc.v:177339.7-177339.20" + attribute \src "libresoc.v:178647.7-178647.20" wire $0\initial[0:0] - attribute \src "libresoc.v:177668.3-177713.6" - wire width 2 $0\r0__data_o$next[1:0]$10781 - attribute \src "libresoc.v:177414.3-177415.37" + attribute \src "libresoc.v:178976.3-179021.6" + wire width 2 $0\r0__data_o$next[1:0]$10765 + attribute \src "libresoc.v:178722.3-178723.37" wire width 2 $0\r0__data_o[1:0] - attribute \src "libresoc.v:177750.3-177782.6" - wire width 2 $0\reg$next[1:0]$10797 - attribute \src "libresoc.v:177412.3-177413.25" + attribute \src "libresoc.v:179058.3-179090.6" + wire width 2 $0\reg$next[1:0]$10781 + attribute \src "libresoc.v:178720.3-178721.25" wire width 2 $0\reg[1:0] - attribute \src "libresoc.v:177422.3-177467.6" - wire width 2 $0\src10__data_o$next[1:0]$10739 - attribute \src "libresoc.v:177420.3-177421.43" + attribute \src "libresoc.v:178730.3-178775.6" + wire width 2 $0\src10__data_o$next[1:0]$10723 + attribute \src "libresoc.v:178728.3-178729.43" wire width 2 $0\src10__data_o[1:0] - attribute \src "libresoc.v:177504.3-177549.6" - wire width 2 $0\src20__data_o$next[1:0]$10749 - attribute \src "libresoc.v:177418.3-177419.43" + attribute \src "libresoc.v:178812.3-178857.6" + wire width 2 $0\src20__data_o$next[1:0]$10733 + attribute \src "libresoc.v:178726.3-178727.43" wire width 2 $0\src20__data_o[1:0] - attribute \src "libresoc.v:177586.3-177631.6" - wire width 2 $0\src30__data_o$next[1:0]$10765 - attribute \src "libresoc.v:177416.3-177417.43" + attribute \src "libresoc.v:178894.3-178939.6" + wire width 2 $0\src30__data_o$next[1:0]$10749 + attribute \src "libresoc.v:178724.3-178725.43" wire width 2 $0\src30__data_o[1:0] - attribute \src "libresoc.v:177714.3-177749.6" - wire $0\wr_detect$10[0:0]$10790 - attribute \src "libresoc.v:177550.3-177585.6" - wire $0\wr_detect$4[0:0]$10758 - attribute \src "libresoc.v:177632.3-177667.6" - wire $0\wr_detect$7[0:0]$10774 - attribute \src "libresoc.v:177468.3-177503.6" + attribute \src "libresoc.v:179022.3-179057.6" + wire $0\wr_detect$10[0:0]$10774 + attribute \src "libresoc.v:178858.3-178893.6" + wire $0\wr_detect$4[0:0]$10742 + attribute \src "libresoc.v:178940.3-178975.6" + wire $0\wr_detect$7[0:0]$10758 + attribute \src "libresoc.v:178776.3-178811.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:177668.3-177713.6" - wire width 2 $1\r0__data_o$next[1:0]$10782 - attribute \src "libresoc.v:177366.13-177366.30" + attribute \src "libresoc.v:178976.3-179021.6" + wire width 2 $1\r0__data_o$next[1:0]$10766 + attribute \src "libresoc.v:178674.13-178674.30" wire width 2 $1\r0__data_o[1:0] - attribute \src "libresoc.v:177750.3-177782.6" - wire width 2 $1\reg$next[1:0]$10798 - attribute \src "libresoc.v:177372.13-177372.25" + attribute \src "libresoc.v:179058.3-179090.6" + wire width 2 $1\reg$next[1:0]$10782 + attribute \src "libresoc.v:178680.13-178680.25" wire width 2 $1\reg[1:0] - attribute \src "libresoc.v:177422.3-177467.6" - wire width 2 $1\src10__data_o$next[1:0]$10740 - attribute \src "libresoc.v:177377.13-177377.33" + attribute \src "libresoc.v:178730.3-178775.6" + wire width 2 $1\src10__data_o$next[1:0]$10724 + attribute \src "libresoc.v:178685.13-178685.33" wire width 2 $1\src10__data_o[1:0] - attribute \src "libresoc.v:177504.3-177549.6" - wire width 2 $1\src20__data_o$next[1:0]$10750 - attribute \src "libresoc.v:177384.13-177384.33" + attribute \src "libresoc.v:178812.3-178857.6" + wire width 2 $1\src20__data_o$next[1:0]$10734 + attribute \src "libresoc.v:178692.13-178692.33" wire width 2 $1\src20__data_o[1:0] - attribute \src "libresoc.v:177586.3-177631.6" - wire width 2 $1\src30__data_o$next[1:0]$10766 - attribute \src "libresoc.v:177391.13-177391.33" + attribute \src "libresoc.v:178894.3-178939.6" + wire width 2 $1\src30__data_o$next[1:0]$10750 + attribute \src "libresoc.v:178699.13-178699.33" wire width 2 $1\src30__data_o[1:0] - attribute \src "libresoc.v:177714.3-177749.6" - wire $1\wr_detect$10[0:0]$10791 - attribute \src "libresoc.v:177550.3-177585.6" - wire $1\wr_detect$4[0:0]$10759 - attribute \src "libresoc.v:177632.3-177667.6" - wire $1\wr_detect$7[0:0]$10775 - attribute \src "libresoc.v:177468.3-177503.6" + attribute \src "libresoc.v:179022.3-179057.6" + wire $1\wr_detect$10[0:0]$10775 + attribute \src "libresoc.v:178858.3-178893.6" + wire $1\wr_detect$4[0:0]$10743 + attribute \src "libresoc.v:178940.3-178975.6" + wire $1\wr_detect$7[0:0]$10759 + attribute \src "libresoc.v:178776.3-178811.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:177668.3-177713.6" - wire width 2 $2\r0__data_o$next[1:0]$10783 - attribute \src "libresoc.v:177750.3-177782.6" - wire width 2 $2\reg$next[1:0]$10799 - attribute \src "libresoc.v:177422.3-177467.6" - wire width 2 $2\src10__data_o$next[1:0]$10741 - attribute \src "libresoc.v:177504.3-177549.6" - wire width 2 $2\src20__data_o$next[1:0]$10751 - attribute \src "libresoc.v:177586.3-177631.6" - wire width 2 $2\src30__data_o$next[1:0]$10767 - attribute \src "libresoc.v:177714.3-177749.6" - wire $2\wr_detect$10[0:0]$10792 - attribute \src "libresoc.v:177550.3-177585.6" - wire $2\wr_detect$4[0:0]$10760 - attribute \src "libresoc.v:177632.3-177667.6" - wire $2\wr_detect$7[0:0]$10776 - attribute \src "libresoc.v:177468.3-177503.6" + attribute \src "libresoc.v:178976.3-179021.6" + wire width 2 $2\r0__data_o$next[1:0]$10767 + attribute \src "libresoc.v:179058.3-179090.6" + wire width 2 $2\reg$next[1:0]$10783 + attribute \src "libresoc.v:178730.3-178775.6" + wire width 2 $2\src10__data_o$next[1:0]$10725 + attribute \src "libresoc.v:178812.3-178857.6" + wire width 2 $2\src20__data_o$next[1:0]$10735 + attribute \src "libresoc.v:178894.3-178939.6" + wire width 2 $2\src30__data_o$next[1:0]$10751 + attribute \src "libresoc.v:179022.3-179057.6" + wire $2\wr_detect$10[0:0]$10776 + attribute \src "libresoc.v:178858.3-178893.6" + wire $2\wr_detect$4[0:0]$10744 + attribute \src "libresoc.v:178940.3-178975.6" + wire $2\wr_detect$7[0:0]$10760 + attribute \src "libresoc.v:178776.3-178811.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:177668.3-177713.6" - wire width 2 $3\r0__data_o$next[1:0]$10784 - attribute \src "libresoc.v:177750.3-177782.6" - wire width 2 $3\reg$next[1:0]$10800 - attribute \src "libresoc.v:177422.3-177467.6" - wire width 2 $3\src10__data_o$next[1:0]$10742 - attribute \src "libresoc.v:177504.3-177549.6" - wire width 2 $3\src20__data_o$next[1:0]$10752 - attribute \src "libresoc.v:177586.3-177631.6" - wire width 2 $3\src30__data_o$next[1:0]$10768 - attribute \src "libresoc.v:177714.3-177749.6" - wire $3\wr_detect$10[0:0]$10793 - attribute \src "libresoc.v:177550.3-177585.6" - wire $3\wr_detect$4[0:0]$10761 - attribute \src "libresoc.v:177632.3-177667.6" - wire $3\wr_detect$7[0:0]$10777 - attribute \src "libresoc.v:177468.3-177503.6" + attribute \src "libresoc.v:178976.3-179021.6" + wire width 2 $3\r0__data_o$next[1:0]$10768 + attribute \src "libresoc.v:179058.3-179090.6" + wire width 2 $3\reg$next[1:0]$10784 + attribute \src "libresoc.v:178730.3-178775.6" + wire width 2 $3\src10__data_o$next[1:0]$10726 + attribute \src "libresoc.v:178812.3-178857.6" + wire width 2 $3\src20__data_o$next[1:0]$10736 + attribute \src "libresoc.v:178894.3-178939.6" + wire width 2 $3\src30__data_o$next[1:0]$10752 + attribute \src "libresoc.v:179022.3-179057.6" + wire $3\wr_detect$10[0:0]$10777 + attribute \src "libresoc.v:178858.3-178893.6" + wire $3\wr_detect$4[0:0]$10745 + attribute \src "libresoc.v:178940.3-178975.6" + wire $3\wr_detect$7[0:0]$10761 + attribute \src "libresoc.v:178776.3-178811.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:177668.3-177713.6" - wire width 2 $4\r0__data_o$next[1:0]$10785 - attribute \src "libresoc.v:177750.3-177782.6" - wire width 2 $4\reg$next[1:0]$10801 - attribute \src "libresoc.v:177422.3-177467.6" - wire width 2 $4\src10__data_o$next[1:0]$10743 - attribute \src "libresoc.v:177504.3-177549.6" - wire width 2 $4\src20__data_o$next[1:0]$10753 - attribute \src "libresoc.v:177586.3-177631.6" - wire width 2 $4\src30__data_o$next[1:0]$10769 - attribute \src "libresoc.v:177714.3-177749.6" - wire $4\wr_detect$10[0:0]$10794 - attribute \src "libresoc.v:177550.3-177585.6" - wire $4\wr_detect$4[0:0]$10762 - attribute \src "libresoc.v:177632.3-177667.6" - wire $4\wr_detect$7[0:0]$10778 - attribute \src "libresoc.v:177468.3-177503.6" + attribute \src "libresoc.v:178976.3-179021.6" + wire width 2 $4\r0__data_o$next[1:0]$10769 + attribute \src "libresoc.v:179058.3-179090.6" + wire width 2 $4\reg$next[1:0]$10785 + attribute \src "libresoc.v:178730.3-178775.6" + wire width 2 $4\src10__data_o$next[1:0]$10727 + attribute \src "libresoc.v:178812.3-178857.6" + wire width 2 $4\src20__data_o$next[1:0]$10737 + attribute \src "libresoc.v:178894.3-178939.6" + wire width 2 $4\src30__data_o$next[1:0]$10753 + attribute \src "libresoc.v:179022.3-179057.6" + wire $4\wr_detect$10[0:0]$10778 + attribute \src "libresoc.v:178858.3-178893.6" + wire $4\wr_detect$4[0:0]$10746 + attribute \src "libresoc.v:178940.3-178975.6" + wire $4\wr_detect$7[0:0]$10762 + attribute \src "libresoc.v:178776.3-178811.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:177668.3-177713.6" - wire width 2 $5\r0__data_o$next[1:0]$10786 - attribute \src "libresoc.v:177750.3-177782.6" - wire width 2 $5\reg$next[1:0]$10802 - attribute \src "libresoc.v:177422.3-177467.6" - wire width 2 $5\src10__data_o$next[1:0]$10744 - attribute \src "libresoc.v:177504.3-177549.6" - wire width 2 $5\src20__data_o$next[1:0]$10754 - attribute \src "libresoc.v:177586.3-177631.6" - wire width 2 $5\src30__data_o$next[1:0]$10770 - attribute \src "libresoc.v:177714.3-177749.6" - wire $5\wr_detect$10[0:0]$10795 - attribute \src "libresoc.v:177550.3-177585.6" - wire $5\wr_detect$4[0:0]$10763 - attribute \src "libresoc.v:177632.3-177667.6" - wire $5\wr_detect$7[0:0]$10779 - attribute \src "libresoc.v:177468.3-177503.6" + attribute \src "libresoc.v:178976.3-179021.6" + wire width 2 $5\r0__data_o$next[1:0]$10770 + attribute \src "libresoc.v:179058.3-179090.6" + wire width 2 $5\reg$next[1:0]$10786 + attribute \src "libresoc.v:178730.3-178775.6" + wire width 2 $5\src10__data_o$next[1:0]$10728 + attribute \src "libresoc.v:178812.3-178857.6" + wire width 2 $5\src20__data_o$next[1:0]$10738 + attribute \src "libresoc.v:178894.3-178939.6" + wire width 2 $5\src30__data_o$next[1:0]$10754 + attribute \src "libresoc.v:179022.3-179057.6" + wire $5\wr_detect$10[0:0]$10779 + attribute \src "libresoc.v:178858.3-178893.6" + wire $5\wr_detect$4[0:0]$10747 + attribute \src "libresoc.v:178940.3-178975.6" + wire $5\wr_detect$7[0:0]$10763 + attribute \src "libresoc.v:178776.3-178811.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:177668.3-177713.6" - wire width 2 $6\r0__data_o$next[1:0]$10787 - attribute \src "libresoc.v:177422.3-177467.6" - wire width 2 $6\src10__data_o$next[1:0]$10745 - attribute \src "libresoc.v:177504.3-177549.6" - wire width 2 $6\src20__data_o$next[1:0]$10755 - attribute \src "libresoc.v:177586.3-177631.6" - wire width 2 $6\src30__data_o$next[1:0]$10771 - attribute \src "libresoc.v:177668.3-177713.6" - wire width 2 $7\r0__data_o$next[1:0]$10788 - attribute \src "libresoc.v:177422.3-177467.6" - wire width 2 $7\src10__data_o$next[1:0]$10746 - attribute \src "libresoc.v:177504.3-177549.6" - wire width 2 $7\src20__data_o$next[1:0]$10756 - attribute \src "libresoc.v:177586.3-177631.6" - wire width 2 $7\src30__data_o$next[1:0]$10772 - attribute \src "libresoc.v:177408.17-177408.104" - wire $not$libresoc.v:177408$10729_Y - attribute \src "libresoc.v:177409.17-177409.100" - wire $not$libresoc.v:177409$10730_Y - attribute \src "libresoc.v:177410.17-177410.103" - wire $not$libresoc.v:177410$10731_Y - attribute \src "libresoc.v:177411.17-177411.103" - wire $not$libresoc.v:177411$10732_Y + attribute \src "libresoc.v:178976.3-179021.6" + wire width 2 $6\r0__data_o$next[1:0]$10771 + attribute \src "libresoc.v:178730.3-178775.6" + wire width 2 $6\src10__data_o$next[1:0]$10729 + attribute \src "libresoc.v:178812.3-178857.6" + wire width 2 $6\src20__data_o$next[1:0]$10739 + attribute \src "libresoc.v:178894.3-178939.6" + wire width 2 $6\src30__data_o$next[1:0]$10755 + attribute \src "libresoc.v:178976.3-179021.6" + wire width 2 $7\r0__data_o$next[1:0]$10772 + attribute \src "libresoc.v:178730.3-178775.6" + wire width 2 $7\src10__data_o$next[1:0]$10730 + attribute \src "libresoc.v:178812.3-178857.6" + wire width 2 $7\src20__data_o$next[1:0]$10740 + attribute \src "libresoc.v:178894.3-178939.6" + wire width 2 $7\src30__data_o$next[1:0]$10756 + attribute \src "libresoc.v:178716.17-178716.104" + wire $not$libresoc.v:178716$10713_Y + attribute \src "libresoc.v:178717.17-178717.100" + wire $not$libresoc.v:178717$10714_Y + attribute \src "libresoc.v:178718.17-178718.103" + wire $not$libresoc.v:178718$10715_Y + attribute \src "libresoc.v:178719.17-178719.103" + wire $not$libresoc.v:178719$10716_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -361081,9 +332451,9 @@ module \reg_0$132 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 9 \dest10__data_i @@ -361097,7 +332467,7 @@ module \reg_0$132 wire width 2 input 13 \dest30__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest30__wen - attribute \src "libresoc.v:177339.7-177339.15" + attribute \src "libresoc.v:178647.7-178647.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 14 \r0__data_o @@ -361140,129 +332510,129 @@ module \reg_0$132 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177408$10729 + cell $not $not$libresoc.v:178716$10713 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:177408$10729_Y + connect \Y $not$libresoc.v:178716$10713_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177409$10730 + cell $not $not$libresoc.v:178717$10714 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:177409$10730_Y + connect \Y $not$libresoc.v:178717$10714_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177410$10731 + cell $not $not$libresoc.v:178718$10715 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:177410$10731_Y + connect \Y $not$libresoc.v:178718$10715_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177411$10732 + cell $not $not$libresoc.v:178719$10716 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:177411$10732_Y + connect \Y $not$libresoc.v:178719$10716_Y end - attribute \src "libresoc.v:177339.7-177339.20" - process $proc$libresoc.v:177339$10803 + attribute \src "libresoc.v:178647.7-178647.20" + process $proc$libresoc.v:178647$10787 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:177366.13-177366.30" - process $proc$libresoc.v:177366$10804 + attribute \src "libresoc.v:178674.13-178674.30" + process $proc$libresoc.v:178674$10788 assign { } { } assign $1\r0__data_o[1:0] 2'00 sync always sync init update \r0__data_o $1\r0__data_o[1:0] end - attribute \src "libresoc.v:177372.13-177372.25" - process $proc$libresoc.v:177372$10805 + attribute \src "libresoc.v:178680.13-178680.25" + process $proc$libresoc.v:178680$10789 assign { } { } assign $1\reg[1:0] 2'00 sync always sync init update \reg $1\reg[1:0] end - attribute \src "libresoc.v:177377.13-177377.33" - process $proc$libresoc.v:177377$10806 + attribute \src "libresoc.v:178685.13-178685.33" + process $proc$libresoc.v:178685$10790 assign { } { } assign $1\src10__data_o[1:0] 2'00 sync always sync init update \src10__data_o $1\src10__data_o[1:0] end - attribute \src "libresoc.v:177384.13-177384.33" - process $proc$libresoc.v:177384$10807 + attribute \src "libresoc.v:178692.13-178692.33" + process $proc$libresoc.v:178692$10791 assign { } { } assign $1\src20__data_o[1:0] 2'00 sync always sync init update \src20__data_o $1\src20__data_o[1:0] end - attribute \src "libresoc.v:177391.13-177391.33" - process $proc$libresoc.v:177391$10808 + attribute \src "libresoc.v:178699.13-178699.33" + process $proc$libresoc.v:178699$10792 assign { } { } assign $1\src30__data_o[1:0] 2'00 sync always sync init update \src30__data_o $1\src30__data_o[1:0] end - attribute \src "libresoc.v:177412.3-177413.25" - process $proc$libresoc.v:177412$10733 + attribute \src "libresoc.v:178720.3-178721.25" + process $proc$libresoc.v:178720$10717 assign { } { } assign $0\reg[1:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[1:0] end - attribute \src "libresoc.v:177414.3-177415.37" - process $proc$libresoc.v:177414$10734 + attribute \src "libresoc.v:178722.3-178723.37" + process $proc$libresoc.v:178722$10718 assign { } { } assign $0\r0__data_o[1:0] \r0__data_o$next sync posedge \coresync_clk update \r0__data_o $0\r0__data_o[1:0] end - attribute \src "libresoc.v:177416.3-177417.43" - process $proc$libresoc.v:177416$10735 + attribute \src "libresoc.v:178724.3-178725.43" + process $proc$libresoc.v:178724$10719 assign { } { } assign $0\src30__data_o[1:0] \src30__data_o$next sync posedge \coresync_clk update \src30__data_o $0\src30__data_o[1:0] end - attribute \src "libresoc.v:177418.3-177419.43" - process $proc$libresoc.v:177418$10736 + attribute \src "libresoc.v:178726.3-178727.43" + process $proc$libresoc.v:178726$10720 assign { } { } assign $0\src20__data_o[1:0] \src20__data_o$next sync posedge \coresync_clk update \src20__data_o $0\src20__data_o[1:0] end - attribute \src "libresoc.v:177420.3-177421.43" - process $proc$libresoc.v:177420$10737 + attribute \src "libresoc.v:178728.3-178729.43" + process $proc$libresoc.v:178728$10721 assign { } { } assign $0\src10__data_o[1:0] \src10__data_o$next sync posedge \coresync_clk update \src10__data_o $0\src10__data_o[1:0] end - attribute \src "libresoc.v:177422.3-177467.6" - process $proc$libresoc.v:177422$10738 + attribute \src "libresoc.v:178730.3-178775.6" + process $proc$libresoc.v:178730$10722 assign { } { } assign { } { } assign { } { } - assign $0\src10__data_o$next[1:0]$10739 $7\src10__data_o$next[1:0]$10746 - attribute \src "libresoc.v:177423.5-177423.29" + assign $0\src10__data_o$next[1:0]$10723 $7\src10__data_o$next[1:0]$10730 + attribute \src "libresoc.v:178731.5-178731.29" switch \initial - attribute \src "libresoc.v:177423.9-177423.17" + attribute \src "libresoc.v:178731.9-178731.17" case 1'1 case end @@ -361275,75 +332645,75 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\src10__data_o$next[1:0]$10740 $6\src10__data_o$next[1:0]$10745 + assign $1\src10__data_o$next[1:0]$10724 $6\src10__data_o$next[1:0]$10729 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src10__data_o$next[1:0]$10741 \dest10__data_i + assign $2\src10__data_o$next[1:0]$10725 \dest10__data_i case - assign $2\src10__data_o$next[1:0]$10741 2'00 + assign $2\src10__data_o$next[1:0]$10725 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src10__data_o$next[1:0]$10742 \dest20__data_i + assign $3\src10__data_o$next[1:0]$10726 \dest20__data_i case - assign $3\src10__data_o$next[1:0]$10742 $2\src10__data_o$next[1:0]$10741 + assign $3\src10__data_o$next[1:0]$10726 $2\src10__data_o$next[1:0]$10725 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src10__data_o$next[1:0]$10743 \dest30__data_i + assign $4\src10__data_o$next[1:0]$10727 \dest30__data_i case - assign $4\src10__data_o$next[1:0]$10743 $3\src10__data_o$next[1:0]$10742 + assign $4\src10__data_o$next[1:0]$10727 $3\src10__data_o$next[1:0]$10726 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src10__data_o$next[1:0]$10744 \w0__data_i + assign $5\src10__data_o$next[1:0]$10728 \w0__data_i case - assign $5\src10__data_o$next[1:0]$10744 $4\src10__data_o$next[1:0]$10743 + assign $5\src10__data_o$next[1:0]$10728 $4\src10__data_o$next[1:0]$10727 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src10__data_o$next[1:0]$10745 \reg + assign $6\src10__data_o$next[1:0]$10729 \reg case - assign $6\src10__data_o$next[1:0]$10745 $5\src10__data_o$next[1:0]$10744 + assign $6\src10__data_o$next[1:0]$10729 $5\src10__data_o$next[1:0]$10728 end case - assign $1\src10__data_o$next[1:0]$10740 2'00 + assign $1\src10__data_o$next[1:0]$10724 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src10__data_o$next[1:0]$10746 2'00 + assign $7\src10__data_o$next[1:0]$10730 2'00 case - assign $7\src10__data_o$next[1:0]$10746 $1\src10__data_o$next[1:0]$10740 + assign $7\src10__data_o$next[1:0]$10730 $1\src10__data_o$next[1:0]$10724 end sync always - update \src10__data_o$next $0\src10__data_o$next[1:0]$10739 + update \src10__data_o$next $0\src10__data_o$next[1:0]$10723 end - attribute \src "libresoc.v:177468.3-177503.6" - process $proc$libresoc.v:177468$10747 + attribute \src "libresoc.v:178776.3-178811.6" + process $proc$libresoc.v:178776$10731 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:177469.5-177469.29" + attribute \src "libresoc.v:178777.5-178777.29" switch \initial - attribute \src "libresoc.v:177469.9-177469.17" + attribute \src "libresoc.v:178777.9-178777.17" case 1'1 case end @@ -361399,15 +332769,15 @@ module \reg_0$132 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:177504.3-177549.6" - process $proc$libresoc.v:177504$10748 + attribute \src "libresoc.v:178812.3-178857.6" + process $proc$libresoc.v:178812$10732 assign { } { } assign { } { } assign { } { } - assign $0\src20__data_o$next[1:0]$10749 $7\src20__data_o$next[1:0]$10756 - attribute \src "libresoc.v:177505.5-177505.29" + assign $0\src20__data_o$next[1:0]$10733 $7\src20__data_o$next[1:0]$10740 + attribute \src "libresoc.v:178813.5-178813.29" switch \initial - attribute \src "libresoc.v:177505.9-177505.17" + attribute \src "libresoc.v:178813.9-178813.17" case 1'1 case end @@ -361420,75 +332790,75 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\src20__data_o$next[1:0]$10750 $6\src20__data_o$next[1:0]$10755 + assign $1\src20__data_o$next[1:0]$10734 $6\src20__data_o$next[1:0]$10739 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src20__data_o$next[1:0]$10751 \dest10__data_i + assign $2\src20__data_o$next[1:0]$10735 \dest10__data_i case - assign $2\src20__data_o$next[1:0]$10751 2'00 + assign $2\src20__data_o$next[1:0]$10735 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src20__data_o$next[1:0]$10752 \dest20__data_i + assign $3\src20__data_o$next[1:0]$10736 \dest20__data_i case - assign $3\src20__data_o$next[1:0]$10752 $2\src20__data_o$next[1:0]$10751 + assign $3\src20__data_o$next[1:0]$10736 $2\src20__data_o$next[1:0]$10735 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src20__data_o$next[1:0]$10753 \dest30__data_i + assign $4\src20__data_o$next[1:0]$10737 \dest30__data_i case - assign $4\src20__data_o$next[1:0]$10753 $3\src20__data_o$next[1:0]$10752 + assign $4\src20__data_o$next[1:0]$10737 $3\src20__data_o$next[1:0]$10736 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src20__data_o$next[1:0]$10754 \w0__data_i + assign $5\src20__data_o$next[1:0]$10738 \w0__data_i case - assign $5\src20__data_o$next[1:0]$10754 $4\src20__data_o$next[1:0]$10753 + assign $5\src20__data_o$next[1:0]$10738 $4\src20__data_o$next[1:0]$10737 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src20__data_o$next[1:0]$10755 \reg + assign $6\src20__data_o$next[1:0]$10739 \reg case - assign $6\src20__data_o$next[1:0]$10755 $5\src20__data_o$next[1:0]$10754 + assign $6\src20__data_o$next[1:0]$10739 $5\src20__data_o$next[1:0]$10738 end case - assign $1\src20__data_o$next[1:0]$10750 2'00 + assign $1\src20__data_o$next[1:0]$10734 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src20__data_o$next[1:0]$10756 2'00 + assign $7\src20__data_o$next[1:0]$10740 2'00 case - assign $7\src20__data_o$next[1:0]$10756 $1\src20__data_o$next[1:0]$10750 + assign $7\src20__data_o$next[1:0]$10740 $1\src20__data_o$next[1:0]$10734 end sync always - update \src20__data_o$next $0\src20__data_o$next[1:0]$10749 + update \src20__data_o$next $0\src20__data_o$next[1:0]$10733 end - attribute \src "libresoc.v:177550.3-177585.6" - process $proc$libresoc.v:177550$10757 + attribute \src "libresoc.v:178858.3-178893.6" + process $proc$libresoc.v:178858$10741 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10758 $1\wr_detect$4[0:0]$10759 - attribute \src "libresoc.v:177551.5-177551.29" + assign $0\wr_detect$4[0:0]$10742 $1\wr_detect$4[0:0]$10743 + attribute \src "libresoc.v:178859.5-178859.29" switch \initial - attribute \src "libresoc.v:177551.9-177551.17" + attribute \src "libresoc.v:178859.9-178859.17" case 1'1 case end @@ -361501,58 +332871,58 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10759 $5\wr_detect$4[0:0]$10763 + assign $1\wr_detect$4[0:0]$10743 $5\wr_detect$4[0:0]$10747 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10760 1'1 + assign $2\wr_detect$4[0:0]$10744 1'1 case - assign $2\wr_detect$4[0:0]$10760 1'0 + assign $2\wr_detect$4[0:0]$10744 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10761 1'1 + assign $3\wr_detect$4[0:0]$10745 1'1 case - assign $3\wr_detect$4[0:0]$10761 $2\wr_detect$4[0:0]$10760 + assign $3\wr_detect$4[0:0]$10745 $2\wr_detect$4[0:0]$10744 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10762 1'1 + assign $4\wr_detect$4[0:0]$10746 1'1 case - assign $4\wr_detect$4[0:0]$10762 $3\wr_detect$4[0:0]$10761 + assign $4\wr_detect$4[0:0]$10746 $3\wr_detect$4[0:0]$10745 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$10763 1'1 + assign $5\wr_detect$4[0:0]$10747 1'1 case - assign $5\wr_detect$4[0:0]$10763 $4\wr_detect$4[0:0]$10762 + assign $5\wr_detect$4[0:0]$10747 $4\wr_detect$4[0:0]$10746 end case - assign $1\wr_detect$4[0:0]$10759 1'0 + assign $1\wr_detect$4[0:0]$10743 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10758 + update \wr_detect$4 $0\wr_detect$4[0:0]$10742 end - attribute \src "libresoc.v:177586.3-177631.6" - process $proc$libresoc.v:177586$10764 + attribute \src "libresoc.v:178894.3-178939.6" + process $proc$libresoc.v:178894$10748 assign { } { } assign { } { } assign { } { } - assign $0\src30__data_o$next[1:0]$10765 $7\src30__data_o$next[1:0]$10772 - attribute \src "libresoc.v:177587.5-177587.29" + assign $0\src30__data_o$next[1:0]$10749 $7\src30__data_o$next[1:0]$10756 + attribute \src "libresoc.v:178895.5-178895.29" switch \initial - attribute \src "libresoc.v:177587.9-177587.17" + attribute \src "libresoc.v:178895.9-178895.17" case 1'1 case end @@ -361565,75 +332935,75 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\src30__data_o$next[1:0]$10766 $6\src30__data_o$next[1:0]$10771 + assign $1\src30__data_o$next[1:0]$10750 $6\src30__data_o$next[1:0]$10755 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src30__data_o$next[1:0]$10767 \dest10__data_i + assign $2\src30__data_o$next[1:0]$10751 \dest10__data_i case - assign $2\src30__data_o$next[1:0]$10767 2'00 + assign $2\src30__data_o$next[1:0]$10751 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src30__data_o$next[1:0]$10768 \dest20__data_i + assign $3\src30__data_o$next[1:0]$10752 \dest20__data_i case - assign $3\src30__data_o$next[1:0]$10768 $2\src30__data_o$next[1:0]$10767 + assign $3\src30__data_o$next[1:0]$10752 $2\src30__data_o$next[1:0]$10751 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src30__data_o$next[1:0]$10769 \dest30__data_i + assign $4\src30__data_o$next[1:0]$10753 \dest30__data_i case - assign $4\src30__data_o$next[1:0]$10769 $3\src30__data_o$next[1:0]$10768 + assign $4\src30__data_o$next[1:0]$10753 $3\src30__data_o$next[1:0]$10752 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src30__data_o$next[1:0]$10770 \w0__data_i + assign $5\src30__data_o$next[1:0]$10754 \w0__data_i case - assign $5\src30__data_o$next[1:0]$10770 $4\src30__data_o$next[1:0]$10769 + assign $5\src30__data_o$next[1:0]$10754 $4\src30__data_o$next[1:0]$10753 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src30__data_o$next[1:0]$10771 \reg + assign $6\src30__data_o$next[1:0]$10755 \reg case - assign $6\src30__data_o$next[1:0]$10771 $5\src30__data_o$next[1:0]$10770 + assign $6\src30__data_o$next[1:0]$10755 $5\src30__data_o$next[1:0]$10754 end case - assign $1\src30__data_o$next[1:0]$10766 2'00 + assign $1\src30__data_o$next[1:0]$10750 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src30__data_o$next[1:0]$10772 2'00 + assign $7\src30__data_o$next[1:0]$10756 2'00 case - assign $7\src30__data_o$next[1:0]$10772 $1\src30__data_o$next[1:0]$10766 + assign $7\src30__data_o$next[1:0]$10756 $1\src30__data_o$next[1:0]$10750 end sync always - update \src30__data_o$next $0\src30__data_o$next[1:0]$10765 + update \src30__data_o$next $0\src30__data_o$next[1:0]$10749 end - attribute \src "libresoc.v:177632.3-177667.6" - process $proc$libresoc.v:177632$10773 + attribute \src "libresoc.v:178940.3-178975.6" + process $proc$libresoc.v:178940$10757 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10774 $1\wr_detect$7[0:0]$10775 - attribute \src "libresoc.v:177633.5-177633.29" + assign $0\wr_detect$7[0:0]$10758 $1\wr_detect$7[0:0]$10759 + attribute \src "libresoc.v:178941.5-178941.29" switch \initial - attribute \src "libresoc.v:177633.9-177633.17" + attribute \src "libresoc.v:178941.9-178941.17" case 1'1 case end @@ -361646,58 +333016,58 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10775 $5\wr_detect$7[0:0]$10779 + assign $1\wr_detect$7[0:0]$10759 $5\wr_detect$7[0:0]$10763 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10776 1'1 + assign $2\wr_detect$7[0:0]$10760 1'1 case - assign $2\wr_detect$7[0:0]$10776 1'0 + assign $2\wr_detect$7[0:0]$10760 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$10777 1'1 + assign $3\wr_detect$7[0:0]$10761 1'1 case - assign $3\wr_detect$7[0:0]$10777 $2\wr_detect$7[0:0]$10776 + assign $3\wr_detect$7[0:0]$10761 $2\wr_detect$7[0:0]$10760 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$10778 1'1 + assign $4\wr_detect$7[0:0]$10762 1'1 case - assign $4\wr_detect$7[0:0]$10778 $3\wr_detect$7[0:0]$10777 + assign $4\wr_detect$7[0:0]$10762 $3\wr_detect$7[0:0]$10761 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$10779 1'1 + assign $5\wr_detect$7[0:0]$10763 1'1 case - assign $5\wr_detect$7[0:0]$10779 $4\wr_detect$7[0:0]$10778 + assign $5\wr_detect$7[0:0]$10763 $4\wr_detect$7[0:0]$10762 end case - assign $1\wr_detect$7[0:0]$10775 1'0 + assign $1\wr_detect$7[0:0]$10759 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10774 + update \wr_detect$7 $0\wr_detect$7[0:0]$10758 end - attribute \src "libresoc.v:177668.3-177713.6" - process $proc$libresoc.v:177668$10780 + attribute \src "libresoc.v:178976.3-179021.6" + process $proc$libresoc.v:178976$10764 assign { } { } assign { } { } assign { } { } - assign $0\r0__data_o$next[1:0]$10781 $7\r0__data_o$next[1:0]$10788 - attribute \src "libresoc.v:177669.5-177669.29" + assign $0\r0__data_o$next[1:0]$10765 $7\r0__data_o$next[1:0]$10772 + attribute \src "libresoc.v:178977.5-178977.29" switch \initial - attribute \src "libresoc.v:177669.9-177669.17" + attribute \src "libresoc.v:178977.9-178977.17" case 1'1 case end @@ -361710,75 +333080,75 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\r0__data_o$next[1:0]$10782 $6\r0__data_o$next[1:0]$10787 + assign $1\r0__data_o$next[1:0]$10766 $6\r0__data_o$next[1:0]$10771 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r0__data_o$next[1:0]$10783 \dest10__data_i + assign $2\r0__data_o$next[1:0]$10767 \dest10__data_i case - assign $2\r0__data_o$next[1:0]$10783 2'00 + assign $2\r0__data_o$next[1:0]$10767 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r0__data_o$next[1:0]$10784 \dest20__data_i + assign $3\r0__data_o$next[1:0]$10768 \dest20__data_i case - assign $3\r0__data_o$next[1:0]$10784 $2\r0__data_o$next[1:0]$10783 + assign $3\r0__data_o$next[1:0]$10768 $2\r0__data_o$next[1:0]$10767 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r0__data_o$next[1:0]$10785 \dest30__data_i + assign $4\r0__data_o$next[1:0]$10769 \dest30__data_i case - assign $4\r0__data_o$next[1:0]$10785 $3\r0__data_o$next[1:0]$10784 + assign $4\r0__data_o$next[1:0]$10769 $3\r0__data_o$next[1:0]$10768 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r0__data_o$next[1:0]$10786 \w0__data_i + assign $5\r0__data_o$next[1:0]$10770 \w0__data_i case - assign $5\r0__data_o$next[1:0]$10786 $4\r0__data_o$next[1:0]$10785 + assign $5\r0__data_o$next[1:0]$10770 $4\r0__data_o$next[1:0]$10769 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r0__data_o$next[1:0]$10787 \reg + assign $6\r0__data_o$next[1:0]$10771 \reg case - assign $6\r0__data_o$next[1:0]$10787 $5\r0__data_o$next[1:0]$10786 + assign $6\r0__data_o$next[1:0]$10771 $5\r0__data_o$next[1:0]$10770 end case - assign $1\r0__data_o$next[1:0]$10782 2'00 + assign $1\r0__data_o$next[1:0]$10766 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\r0__data_o$next[1:0]$10788 2'00 + assign $7\r0__data_o$next[1:0]$10772 2'00 case - assign $7\r0__data_o$next[1:0]$10788 $1\r0__data_o$next[1:0]$10782 + assign $7\r0__data_o$next[1:0]$10772 $1\r0__data_o$next[1:0]$10766 end sync always - update \r0__data_o$next $0\r0__data_o$next[1:0]$10781 + update \r0__data_o$next $0\r0__data_o$next[1:0]$10765 end - attribute \src "libresoc.v:177714.3-177749.6" - process $proc$libresoc.v:177714$10789 + attribute \src "libresoc.v:179022.3-179057.6" + process $proc$libresoc.v:179022$10773 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$10790 $1\wr_detect$10[0:0]$10791 - attribute \src "libresoc.v:177715.5-177715.29" + assign $0\wr_detect$10[0:0]$10774 $1\wr_detect$10[0:0]$10775 + attribute \src "libresoc.v:179023.5-179023.29" switch \initial - attribute \src "libresoc.v:177715.9-177715.17" + attribute \src "libresoc.v:179023.9-179023.17" case 1'1 case end @@ -361791,61 +333161,61 @@ module \reg_0$132 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$10791 $5\wr_detect$10[0:0]$10795 + assign $1\wr_detect$10[0:0]$10775 $5\wr_detect$10[0:0]$10779 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$10792 1'1 + assign $2\wr_detect$10[0:0]$10776 1'1 case - assign $2\wr_detect$10[0:0]$10792 1'0 + assign $2\wr_detect$10[0:0]$10776 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$10793 1'1 + assign $3\wr_detect$10[0:0]$10777 1'1 case - assign $3\wr_detect$10[0:0]$10793 $2\wr_detect$10[0:0]$10792 + assign $3\wr_detect$10[0:0]$10777 $2\wr_detect$10[0:0]$10776 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$10794 1'1 + assign $4\wr_detect$10[0:0]$10778 1'1 case - assign $4\wr_detect$10[0:0]$10794 $3\wr_detect$10[0:0]$10793 + assign $4\wr_detect$10[0:0]$10778 $3\wr_detect$10[0:0]$10777 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$10[0:0]$10795 1'1 + assign $5\wr_detect$10[0:0]$10779 1'1 case - assign $5\wr_detect$10[0:0]$10795 $4\wr_detect$10[0:0]$10794 + assign $5\wr_detect$10[0:0]$10779 $4\wr_detect$10[0:0]$10778 end case - assign $1\wr_detect$10[0:0]$10791 1'0 + assign $1\wr_detect$10[0:0]$10775 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10790 + update \wr_detect$10 $0\wr_detect$10[0:0]$10774 end - attribute \src "libresoc.v:177750.3-177782.6" - process $proc$libresoc.v:177750$10796 + attribute \src "libresoc.v:179058.3-179090.6" + process $proc$libresoc.v:179058$10780 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[1:0]$10797 $5\reg$next[1:0]$10802 - attribute \src "libresoc.v:177751.5-177751.29" + assign $0\reg$next[1:0]$10781 $5\reg$next[1:0]$10786 + attribute \src "libresoc.v:179059.5-179059.29" switch \initial - attribute \src "libresoc.v:177751.9-177751.17" + attribute \src "libresoc.v:179059.9-179059.17" case 1'1 case end @@ -361854,179 +333224,179 @@ module \reg_0$132 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[1:0]$10798 \dest10__data_i + assign $1\reg$next[1:0]$10782 \dest10__data_i case - assign $1\reg$next[1:0]$10798 \reg + assign $1\reg$next[1:0]$10782 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest20__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[1:0]$10799 \dest20__data_i + assign $2\reg$next[1:0]$10783 \dest20__data_i case - assign $2\reg$next[1:0]$10799 $1\reg$next[1:0]$10798 + assign $2\reg$next[1:0]$10783 $1\reg$next[1:0]$10782 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest30__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[1:0]$10800 \dest30__data_i + assign $3\reg$next[1:0]$10784 \dest30__data_i case - assign $3\reg$next[1:0]$10800 $2\reg$next[1:0]$10799 + assign $3\reg$next[1:0]$10784 $2\reg$next[1:0]$10783 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[1:0]$10801 \w0__data_i + assign $4\reg$next[1:0]$10785 \w0__data_i case - assign $4\reg$next[1:0]$10801 $3\reg$next[1:0]$10800 + assign $4\reg$next[1:0]$10785 $3\reg$next[1:0]$10784 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[1:0]$10802 2'00 + assign $5\reg$next[1:0]$10786 2'00 case - assign $5\reg$next[1:0]$10802 $4\reg$next[1:0]$10801 + assign $5\reg$next[1:0]$10786 $4\reg$next[1:0]$10785 end sync always - update \reg$next $0\reg$next[1:0]$10797 + update \reg$next $0\reg$next[1:0]$10781 end - connect \$9 $not$libresoc.v:177408$10729_Y - connect \$1 $not$libresoc.v:177409$10730_Y - connect \$3 $not$libresoc.v:177410$10731_Y - connect \$6 $not$libresoc.v:177411$10732_Y + connect \$9 $not$libresoc.v:178716$10713_Y + connect \$1 $not$libresoc.v:178717$10714_Y + connect \$3 $not$libresoc.v:178718$10715_Y + connect \$6 $not$libresoc.v:178719$10716_Y end -attribute \src "libresoc.v:177787.1-178136.10" +attribute \src "libresoc.v:179095.1-179444.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_0" attribute \generator "nMigen" module \reg_0$135 - attribute \src "libresoc.v:177857.3-177902.6" - wire width 64 $0\cia0__data_o$next[63:0]$10817 - attribute \src "libresoc.v:177855.3-177856.41" + attribute \src "libresoc.v:179165.3-179210.6" + wire width 64 $0\cia0__data_o$next[63:0]$10801 + attribute \src "libresoc.v:179163.3-179164.41" wire width 64 $0\cia0__data_o[63:0] - attribute \src "libresoc.v:177788.7-177788.20" + attribute \src "libresoc.v:179096.7-179096.20" wire $0\initial[0:0] - attribute \src "libresoc.v:177939.3-177984.6" - wire width 64 $0\msr0__data_o$next[63:0]$10827 - attribute \src "libresoc.v:177853.3-177854.41" + attribute \src "libresoc.v:179247.3-179292.6" + wire width 64 $0\msr0__data_o$next[63:0]$10811 + attribute \src "libresoc.v:179161.3-179162.41" wire width 64 $0\msr0__data_o[63:0] - attribute \src "libresoc.v:178103.3-178135.6" - wire width 64 $0\reg$next[63:0]$10859 - attribute \src "libresoc.v:177849.3-177850.25" + attribute \src "libresoc.v:179411.3-179443.6" + wire width 64 $0\reg$next[63:0]$10843 + attribute \src "libresoc.v:179157.3-179158.25" wire width 64 $0\reg[63:0] - attribute \src "libresoc.v:178021.3-178066.6" - wire width 64 $0\sv0__data_o$next[63:0]$10843 - attribute \src "libresoc.v:177851.3-177852.39" + attribute \src "libresoc.v:179329.3-179374.6" + wire width 64 $0\sv0__data_o$next[63:0]$10827 + attribute \src "libresoc.v:179159.3-179160.39" wire width 64 $0\sv0__data_o[63:0] - attribute \src "libresoc.v:177985.3-178020.6" - wire $0\wr_detect$4[0:0]$10836 - attribute \src "libresoc.v:178067.3-178102.6" - wire $0\wr_detect$7[0:0]$10852 - attribute \src "libresoc.v:177903.3-177938.6" + attribute \src "libresoc.v:179293.3-179328.6" + wire $0\wr_detect$4[0:0]$10820 + attribute \src "libresoc.v:179375.3-179410.6" + wire $0\wr_detect$7[0:0]$10836 + attribute \src "libresoc.v:179211.3-179246.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:177857.3-177902.6" - wire width 64 $1\cia0__data_o$next[63:0]$10818 - attribute \src "libresoc.v:177797.14-177797.49" + attribute \src "libresoc.v:179165.3-179210.6" + wire width 64 $1\cia0__data_o$next[63:0]$10802 + attribute \src "libresoc.v:179105.14-179105.49" wire width 64 $1\cia0__data_o[63:0] - attribute \src "libresoc.v:177939.3-177984.6" - wire width 64 $1\msr0__data_o$next[63:0]$10828 - attribute \src "libresoc.v:177814.14-177814.49" + attribute \src "libresoc.v:179247.3-179292.6" + wire width 64 $1\msr0__data_o$next[63:0]$10812 + attribute \src "libresoc.v:179122.14-179122.49" wire width 64 $1\msr0__data_o[63:0] - attribute \src "libresoc.v:178103.3-178135.6" - wire width 64 $1\reg$next[63:0]$10860 - attribute \src "libresoc.v:177826.14-177826.42" + attribute \src "libresoc.v:179411.3-179443.6" + wire width 64 $1\reg$next[63:0]$10844 + attribute \src "libresoc.v:179134.14-179134.42" wire width 64 $1\reg[63:0] - attribute \src "libresoc.v:178021.3-178066.6" - wire width 64 $1\sv0__data_o$next[63:0]$10844 - attribute \src "libresoc.v:177833.14-177833.48" + attribute \src "libresoc.v:179329.3-179374.6" + wire width 64 $1\sv0__data_o$next[63:0]$10828 + attribute \src "libresoc.v:179141.14-179141.48" wire width 64 $1\sv0__data_o[63:0] - attribute \src "libresoc.v:177985.3-178020.6" - wire $1\wr_detect$4[0:0]$10837 - attribute \src "libresoc.v:178067.3-178102.6" - wire $1\wr_detect$7[0:0]$10853 - attribute \src "libresoc.v:177903.3-177938.6" + attribute \src "libresoc.v:179293.3-179328.6" + wire $1\wr_detect$4[0:0]$10821 + attribute \src "libresoc.v:179375.3-179410.6" + wire $1\wr_detect$7[0:0]$10837 + attribute \src "libresoc.v:179211.3-179246.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:177857.3-177902.6" - wire width 64 $2\cia0__data_o$next[63:0]$10819 - attribute \src "libresoc.v:177939.3-177984.6" - wire width 64 $2\msr0__data_o$next[63:0]$10829 - attribute \src "libresoc.v:178103.3-178135.6" - wire width 64 $2\reg$next[63:0]$10861 - attribute \src "libresoc.v:178021.3-178066.6" - wire width 64 $2\sv0__data_o$next[63:0]$10845 - attribute \src "libresoc.v:177985.3-178020.6" - wire $2\wr_detect$4[0:0]$10838 - attribute \src "libresoc.v:178067.3-178102.6" - wire $2\wr_detect$7[0:0]$10854 - attribute \src "libresoc.v:177903.3-177938.6" + attribute \src "libresoc.v:179165.3-179210.6" + wire width 64 $2\cia0__data_o$next[63:0]$10803 + attribute \src "libresoc.v:179247.3-179292.6" + wire width 64 $2\msr0__data_o$next[63:0]$10813 + attribute \src "libresoc.v:179411.3-179443.6" + wire width 64 $2\reg$next[63:0]$10845 + attribute \src "libresoc.v:179329.3-179374.6" + wire width 64 $2\sv0__data_o$next[63:0]$10829 + attribute \src "libresoc.v:179293.3-179328.6" + wire $2\wr_detect$4[0:0]$10822 + attribute \src "libresoc.v:179375.3-179410.6" + wire $2\wr_detect$7[0:0]$10838 + attribute \src "libresoc.v:179211.3-179246.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:177857.3-177902.6" - wire width 64 $3\cia0__data_o$next[63:0]$10820 - attribute \src "libresoc.v:177939.3-177984.6" - wire width 64 $3\msr0__data_o$next[63:0]$10830 - attribute \src "libresoc.v:178103.3-178135.6" - wire width 64 $3\reg$next[63:0]$10862 - attribute \src "libresoc.v:178021.3-178066.6" - wire width 64 $3\sv0__data_o$next[63:0]$10846 - attribute \src "libresoc.v:177985.3-178020.6" - wire $3\wr_detect$4[0:0]$10839 - attribute \src "libresoc.v:178067.3-178102.6" - wire $3\wr_detect$7[0:0]$10855 - attribute \src "libresoc.v:177903.3-177938.6" + attribute \src "libresoc.v:179165.3-179210.6" + wire width 64 $3\cia0__data_o$next[63:0]$10804 + attribute \src "libresoc.v:179247.3-179292.6" + wire width 64 $3\msr0__data_o$next[63:0]$10814 + attribute \src "libresoc.v:179411.3-179443.6" + wire width 64 $3\reg$next[63:0]$10846 + attribute \src "libresoc.v:179329.3-179374.6" + wire width 64 $3\sv0__data_o$next[63:0]$10830 + attribute \src "libresoc.v:179293.3-179328.6" + wire $3\wr_detect$4[0:0]$10823 + attribute \src "libresoc.v:179375.3-179410.6" + wire $3\wr_detect$7[0:0]$10839 + attribute \src "libresoc.v:179211.3-179246.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:177857.3-177902.6" - wire width 64 $4\cia0__data_o$next[63:0]$10821 - attribute \src "libresoc.v:177939.3-177984.6" - wire width 64 $4\msr0__data_o$next[63:0]$10831 - attribute \src "libresoc.v:178103.3-178135.6" - wire width 64 $4\reg$next[63:0]$10863 - attribute \src "libresoc.v:178021.3-178066.6" - wire width 64 $4\sv0__data_o$next[63:0]$10847 - attribute \src "libresoc.v:177985.3-178020.6" - wire $4\wr_detect$4[0:0]$10840 - attribute \src "libresoc.v:178067.3-178102.6" - wire $4\wr_detect$7[0:0]$10856 - attribute \src "libresoc.v:177903.3-177938.6" + attribute \src "libresoc.v:179165.3-179210.6" + wire width 64 $4\cia0__data_o$next[63:0]$10805 + attribute \src "libresoc.v:179247.3-179292.6" + wire width 64 $4\msr0__data_o$next[63:0]$10815 + attribute \src "libresoc.v:179411.3-179443.6" + wire width 64 $4\reg$next[63:0]$10847 + attribute \src "libresoc.v:179329.3-179374.6" + wire width 64 $4\sv0__data_o$next[63:0]$10831 + attribute \src "libresoc.v:179293.3-179328.6" + wire $4\wr_detect$4[0:0]$10824 + attribute \src "libresoc.v:179375.3-179410.6" + wire $4\wr_detect$7[0:0]$10840 + attribute \src "libresoc.v:179211.3-179246.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:177857.3-177902.6" - wire width 64 $5\cia0__data_o$next[63:0]$10822 - attribute \src "libresoc.v:177939.3-177984.6" - wire width 64 $5\msr0__data_o$next[63:0]$10832 - attribute \src "libresoc.v:178103.3-178135.6" - wire width 64 $5\reg$next[63:0]$10864 - attribute \src "libresoc.v:178021.3-178066.6" - wire width 64 $5\sv0__data_o$next[63:0]$10848 - attribute \src "libresoc.v:177985.3-178020.6" - wire $5\wr_detect$4[0:0]$10841 - attribute \src "libresoc.v:178067.3-178102.6" - wire $5\wr_detect$7[0:0]$10857 - attribute \src "libresoc.v:177903.3-177938.6" + attribute \src "libresoc.v:179165.3-179210.6" + wire width 64 $5\cia0__data_o$next[63:0]$10806 + attribute \src "libresoc.v:179247.3-179292.6" + wire width 64 $5\msr0__data_o$next[63:0]$10816 + attribute \src "libresoc.v:179411.3-179443.6" + wire width 64 $5\reg$next[63:0]$10848 + attribute \src "libresoc.v:179329.3-179374.6" + wire width 64 $5\sv0__data_o$next[63:0]$10832 + attribute \src "libresoc.v:179293.3-179328.6" + wire $5\wr_detect$4[0:0]$10825 + attribute \src "libresoc.v:179375.3-179410.6" + wire $5\wr_detect$7[0:0]$10841 + attribute \src "libresoc.v:179211.3-179246.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:177857.3-177902.6" - wire width 64 $6\cia0__data_o$next[63:0]$10823 - attribute \src "libresoc.v:177939.3-177984.6" - wire width 64 $6\msr0__data_o$next[63:0]$10833 - attribute \src "libresoc.v:178021.3-178066.6" - wire width 64 $6\sv0__data_o$next[63:0]$10849 - attribute \src "libresoc.v:177857.3-177902.6" - wire width 64 $7\cia0__data_o$next[63:0]$10824 - attribute \src "libresoc.v:177939.3-177984.6" - wire width 64 $7\msr0__data_o$next[63:0]$10834 - attribute \src "libresoc.v:178021.3-178066.6" - wire width 64 $7\sv0__data_o$next[63:0]$10850 - attribute \src "libresoc.v:177846.17-177846.100" - wire $not$libresoc.v:177846$10809_Y - attribute \src "libresoc.v:177847.17-177847.103" - wire $not$libresoc.v:177847$10810_Y - attribute \src "libresoc.v:177848.17-177848.103" - wire $not$libresoc.v:177848$10811_Y + attribute \src "libresoc.v:179165.3-179210.6" + wire width 64 $6\cia0__data_o$next[63:0]$10807 + attribute \src "libresoc.v:179247.3-179292.6" + wire width 64 $6\msr0__data_o$next[63:0]$10817 + attribute \src "libresoc.v:179329.3-179374.6" + wire width 64 $6\sv0__data_o$next[63:0]$10833 + attribute \src "libresoc.v:179165.3-179210.6" + wire width 64 $7\cia0__data_o$next[63:0]$10808 + attribute \src "libresoc.v:179247.3-179292.6" + wire width 64 $7\msr0__data_o$next[63:0]$10818 + attribute \src "libresoc.v:179329.3-179374.6" + wire width 64 $7\sv0__data_o$next[63:0]$10834 + attribute \src "libresoc.v:179154.17-179154.100" + wire $not$libresoc.v:179154$10793_Y + attribute \src "libresoc.v:179155.17-179155.103" + wire $not$libresoc.v:179155$10794_Y + attribute \src "libresoc.v:179156.17-179156.103" + wire $not$libresoc.v:179156$10795_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -362039,15 +333409,15 @@ module \reg_0$135 wire width 64 \cia0__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \cia0__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 15 \d_wr10__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 14 \d_wr10__wen - attribute \src "libresoc.v:177788.7-177788.15" + attribute \src "libresoc.v:179096.7-179096.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 11 \msr0__data_i @@ -362084,106 +333454,106 @@ module \reg_0$135 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177846$10809 + cell $not $not$libresoc.v:179154$10793 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:177846$10809_Y + connect \Y $not$libresoc.v:179154$10793_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177847$10810 + cell $not $not$libresoc.v:179155$10794 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:177847$10810_Y + connect \Y $not$libresoc.v:179155$10794_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:177848$10811 + cell $not $not$libresoc.v:179156$10795 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:177848$10811_Y + connect \Y $not$libresoc.v:179156$10795_Y end - attribute \src "libresoc.v:177788.7-177788.20" - process $proc$libresoc.v:177788$10865 + attribute \src "libresoc.v:179096.7-179096.20" + process $proc$libresoc.v:179096$10849 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:177797.14-177797.49" - process $proc$libresoc.v:177797$10866 + attribute \src "libresoc.v:179105.14-179105.49" + process $proc$libresoc.v:179105$10850 assign { } { } assign $1\cia0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \cia0__data_o $1\cia0__data_o[63:0] end - attribute \src "libresoc.v:177814.14-177814.49" - process $proc$libresoc.v:177814$10867 + attribute \src "libresoc.v:179122.14-179122.49" + process $proc$libresoc.v:179122$10851 assign { } { } assign $1\msr0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \msr0__data_o $1\msr0__data_o[63:0] end - attribute \src "libresoc.v:177826.14-177826.42" - process $proc$libresoc.v:177826$10868 + attribute \src "libresoc.v:179134.14-179134.42" + process $proc$libresoc.v:179134$10852 assign { } { } assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \reg $1\reg[63:0] end - attribute \src "libresoc.v:177833.14-177833.48" - process $proc$libresoc.v:177833$10869 + attribute \src "libresoc.v:179141.14-179141.48" + process $proc$libresoc.v:179141$10853 assign { } { } assign $1\sv0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \sv0__data_o $1\sv0__data_o[63:0] end - attribute \src "libresoc.v:177849.3-177850.25" - process $proc$libresoc.v:177849$10812 + attribute \src "libresoc.v:179157.3-179158.25" + process $proc$libresoc.v:179157$10796 assign { } { } assign $0\reg[63:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[63:0] end - attribute \src "libresoc.v:177851.3-177852.39" - process $proc$libresoc.v:177851$10813 + attribute \src "libresoc.v:179159.3-179160.39" + process $proc$libresoc.v:179159$10797 assign { } { } assign $0\sv0__data_o[63:0] \sv0__data_o$next sync posedge \coresync_clk update \sv0__data_o $0\sv0__data_o[63:0] end - attribute \src "libresoc.v:177853.3-177854.41" - process $proc$libresoc.v:177853$10814 + attribute \src "libresoc.v:179161.3-179162.41" + process $proc$libresoc.v:179161$10798 assign { } { } assign $0\msr0__data_o[63:0] \msr0__data_o$next sync posedge \coresync_clk update \msr0__data_o $0\msr0__data_o[63:0] end - attribute \src "libresoc.v:177855.3-177856.41" - process $proc$libresoc.v:177855$10815 + attribute \src "libresoc.v:179163.3-179164.41" + process $proc$libresoc.v:179163$10799 assign { } { } assign $0\cia0__data_o[63:0] \cia0__data_o$next sync posedge \coresync_clk update \cia0__data_o $0\cia0__data_o[63:0] end - attribute \src "libresoc.v:177857.3-177902.6" - process $proc$libresoc.v:177857$10816 + attribute \src "libresoc.v:179165.3-179210.6" + process $proc$libresoc.v:179165$10800 assign { } { } assign { } { } assign { } { } - assign $0\cia0__data_o$next[63:0]$10817 $7\cia0__data_o$next[63:0]$10824 - attribute \src "libresoc.v:177858.5-177858.29" + assign $0\cia0__data_o$next[63:0]$10801 $7\cia0__data_o$next[63:0]$10808 + attribute \src "libresoc.v:179166.5-179166.29" switch \initial - attribute \src "libresoc.v:177858.9-177858.17" + attribute \src "libresoc.v:179166.9-179166.17" case 1'1 case end @@ -362196,75 +333566,75 @@ module \reg_0$135 assign { } { } assign { } { } assign { } { } - assign $1\cia0__data_o$next[63:0]$10818 $6\cia0__data_o$next[63:0]$10823 + assign $1\cia0__data_o$next[63:0]$10802 $6\cia0__data_o$next[63:0]$10807 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cia0__data_o$next[63:0]$10819 \nia0__data_i + assign $2\cia0__data_o$next[63:0]$10803 \nia0__data_i case - assign $2\cia0__data_o$next[63:0]$10819 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\cia0__data_o$next[63:0]$10803 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\cia0__data_o$next[63:0]$10820 \msr0__data_i + assign $3\cia0__data_o$next[63:0]$10804 \msr0__data_i case - assign $3\cia0__data_o$next[63:0]$10820 $2\cia0__data_o$next[63:0]$10819 + assign $3\cia0__data_o$next[63:0]$10804 $2\cia0__data_o$next[63:0]$10803 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cia0__data_o$next[63:0]$10821 \sv0__data_i + assign $4\cia0__data_o$next[63:0]$10805 \sv0__data_i case - assign $4\cia0__data_o$next[63:0]$10821 $3\cia0__data_o$next[63:0]$10820 + assign $4\cia0__data_o$next[63:0]$10805 $3\cia0__data_o$next[63:0]$10804 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\cia0__data_o$next[63:0]$10822 \d_wr10__data_i + assign $5\cia0__data_o$next[63:0]$10806 \d_wr10__data_i case - assign $5\cia0__data_o$next[63:0]$10822 $4\cia0__data_o$next[63:0]$10821 + assign $5\cia0__data_o$next[63:0]$10806 $4\cia0__data_o$next[63:0]$10805 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cia0__data_o$next[63:0]$10823 \reg + assign $6\cia0__data_o$next[63:0]$10807 \reg case - assign $6\cia0__data_o$next[63:0]$10823 $5\cia0__data_o$next[63:0]$10822 + assign $6\cia0__data_o$next[63:0]$10807 $5\cia0__data_o$next[63:0]$10806 end case - assign $1\cia0__data_o$next[63:0]$10818 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\cia0__data_o$next[63:0]$10802 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\cia0__data_o$next[63:0]$10824 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\cia0__data_o$next[63:0]$10808 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\cia0__data_o$next[63:0]$10824 $1\cia0__data_o$next[63:0]$10818 + assign $7\cia0__data_o$next[63:0]$10808 $1\cia0__data_o$next[63:0]$10802 end sync always - update \cia0__data_o$next $0\cia0__data_o$next[63:0]$10817 + update \cia0__data_o$next $0\cia0__data_o$next[63:0]$10801 end - attribute \src "libresoc.v:177903.3-177938.6" - process $proc$libresoc.v:177903$10825 + attribute \src "libresoc.v:179211.3-179246.6" + process $proc$libresoc.v:179211$10809 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:177904.5-177904.29" + attribute \src "libresoc.v:179212.5-179212.29" switch \initial - attribute \src "libresoc.v:177904.9-177904.17" + attribute \src "libresoc.v:179212.9-179212.17" case 1'1 case end @@ -362320,15 +333690,15 @@ module \reg_0$135 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:177939.3-177984.6" - process $proc$libresoc.v:177939$10826 + attribute \src "libresoc.v:179247.3-179292.6" + process $proc$libresoc.v:179247$10810 assign { } { } assign { } { } assign { } { } - assign $0\msr0__data_o$next[63:0]$10827 $7\msr0__data_o$next[63:0]$10834 - attribute \src "libresoc.v:177940.5-177940.29" + assign $0\msr0__data_o$next[63:0]$10811 $7\msr0__data_o$next[63:0]$10818 + attribute \src "libresoc.v:179248.5-179248.29" switch \initial - attribute \src "libresoc.v:177940.9-177940.17" + attribute \src "libresoc.v:179248.9-179248.17" case 1'1 case end @@ -362341,75 +333711,75 @@ module \reg_0$135 assign { } { } assign { } { } assign { } { } - assign $1\msr0__data_o$next[63:0]$10828 $6\msr0__data_o$next[63:0]$10833 + assign $1\msr0__data_o$next[63:0]$10812 $6\msr0__data_o$next[63:0]$10817 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr0__data_o$next[63:0]$10829 \nia0__data_i + assign $2\msr0__data_o$next[63:0]$10813 \nia0__data_i case - assign $2\msr0__data_o$next[63:0]$10829 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\msr0__data_o$next[63:0]$10813 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\msr0__data_o$next[63:0]$10830 \msr0__data_i + assign $3\msr0__data_o$next[63:0]$10814 \msr0__data_i case - assign $3\msr0__data_o$next[63:0]$10830 $2\msr0__data_o$next[63:0]$10829 + assign $3\msr0__data_o$next[63:0]$10814 $2\msr0__data_o$next[63:0]$10813 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\msr0__data_o$next[63:0]$10831 \sv0__data_i + assign $4\msr0__data_o$next[63:0]$10815 \sv0__data_i case - assign $4\msr0__data_o$next[63:0]$10831 $3\msr0__data_o$next[63:0]$10830 + assign $4\msr0__data_o$next[63:0]$10815 $3\msr0__data_o$next[63:0]$10814 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\msr0__data_o$next[63:0]$10832 \d_wr10__data_i + assign $5\msr0__data_o$next[63:0]$10816 \d_wr10__data_i case - assign $5\msr0__data_o$next[63:0]$10832 $4\msr0__data_o$next[63:0]$10831 + assign $5\msr0__data_o$next[63:0]$10816 $4\msr0__data_o$next[63:0]$10815 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\msr0__data_o$next[63:0]$10833 \reg + assign $6\msr0__data_o$next[63:0]$10817 \reg case - assign $6\msr0__data_o$next[63:0]$10833 $5\msr0__data_o$next[63:0]$10832 + assign $6\msr0__data_o$next[63:0]$10817 $5\msr0__data_o$next[63:0]$10816 end case - assign $1\msr0__data_o$next[63:0]$10828 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\msr0__data_o$next[63:0]$10812 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\msr0__data_o$next[63:0]$10834 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\msr0__data_o$next[63:0]$10818 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\msr0__data_o$next[63:0]$10834 $1\msr0__data_o$next[63:0]$10828 + assign $7\msr0__data_o$next[63:0]$10818 $1\msr0__data_o$next[63:0]$10812 end sync always - update \msr0__data_o$next $0\msr0__data_o$next[63:0]$10827 + update \msr0__data_o$next $0\msr0__data_o$next[63:0]$10811 end - attribute \src "libresoc.v:177985.3-178020.6" - process $proc$libresoc.v:177985$10835 + attribute \src "libresoc.v:179293.3-179328.6" + process $proc$libresoc.v:179293$10819 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10836 $1\wr_detect$4[0:0]$10837 - attribute \src "libresoc.v:177986.5-177986.29" + assign $0\wr_detect$4[0:0]$10820 $1\wr_detect$4[0:0]$10821 + attribute \src "libresoc.v:179294.5-179294.29" switch \initial - attribute \src "libresoc.v:177986.9-177986.17" + attribute \src "libresoc.v:179294.9-179294.17" case 1'1 case end @@ -362422,58 +333792,58 @@ module \reg_0$135 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10837 $5\wr_detect$4[0:0]$10841 + assign $1\wr_detect$4[0:0]$10821 $5\wr_detect$4[0:0]$10825 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10838 1'1 + assign $2\wr_detect$4[0:0]$10822 1'1 case - assign $2\wr_detect$4[0:0]$10838 1'0 + assign $2\wr_detect$4[0:0]$10822 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10839 1'1 + assign $3\wr_detect$4[0:0]$10823 1'1 case - assign $3\wr_detect$4[0:0]$10839 $2\wr_detect$4[0:0]$10838 + assign $3\wr_detect$4[0:0]$10823 $2\wr_detect$4[0:0]$10822 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10840 1'1 + assign $4\wr_detect$4[0:0]$10824 1'1 case - assign $4\wr_detect$4[0:0]$10840 $3\wr_detect$4[0:0]$10839 + assign $4\wr_detect$4[0:0]$10824 $3\wr_detect$4[0:0]$10823 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$10841 1'1 + assign $5\wr_detect$4[0:0]$10825 1'1 case - assign $5\wr_detect$4[0:0]$10841 $4\wr_detect$4[0:0]$10840 + assign $5\wr_detect$4[0:0]$10825 $4\wr_detect$4[0:0]$10824 end case - assign $1\wr_detect$4[0:0]$10837 1'0 + assign $1\wr_detect$4[0:0]$10821 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10836 + update \wr_detect$4 $0\wr_detect$4[0:0]$10820 end - attribute \src "libresoc.v:178021.3-178066.6" - process $proc$libresoc.v:178021$10842 + attribute \src "libresoc.v:179329.3-179374.6" + process $proc$libresoc.v:179329$10826 assign { } { } assign { } { } assign { } { } - assign $0\sv0__data_o$next[63:0]$10843 $7\sv0__data_o$next[63:0]$10850 - attribute \src "libresoc.v:178022.5-178022.29" + assign $0\sv0__data_o$next[63:0]$10827 $7\sv0__data_o$next[63:0]$10834 + attribute \src "libresoc.v:179330.5-179330.29" switch \initial - attribute \src "libresoc.v:178022.9-178022.17" + attribute \src "libresoc.v:179330.9-179330.17" case 1'1 case end @@ -362486,75 +333856,75 @@ module \reg_0$135 assign { } { } assign { } { } assign { } { } - assign $1\sv0__data_o$next[63:0]$10844 $6\sv0__data_o$next[63:0]$10849 + assign $1\sv0__data_o$next[63:0]$10828 $6\sv0__data_o$next[63:0]$10833 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sv0__data_o$next[63:0]$10845 \nia0__data_i + assign $2\sv0__data_o$next[63:0]$10829 \nia0__data_i case - assign $2\sv0__data_o$next[63:0]$10845 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sv0__data_o$next[63:0]$10829 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sv0__data_o$next[63:0]$10846 \msr0__data_i + assign $3\sv0__data_o$next[63:0]$10830 \msr0__data_i case - assign $3\sv0__data_o$next[63:0]$10846 $2\sv0__data_o$next[63:0]$10845 + assign $3\sv0__data_o$next[63:0]$10830 $2\sv0__data_o$next[63:0]$10829 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\sv0__data_o$next[63:0]$10847 \sv0__data_i + assign $4\sv0__data_o$next[63:0]$10831 \sv0__data_i case - assign $4\sv0__data_o$next[63:0]$10847 $3\sv0__data_o$next[63:0]$10846 + assign $4\sv0__data_o$next[63:0]$10831 $3\sv0__data_o$next[63:0]$10830 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\sv0__data_o$next[63:0]$10848 \d_wr10__data_i + assign $5\sv0__data_o$next[63:0]$10832 \d_wr10__data_i case - assign $5\sv0__data_o$next[63:0]$10848 $4\sv0__data_o$next[63:0]$10847 + assign $5\sv0__data_o$next[63:0]$10832 $4\sv0__data_o$next[63:0]$10831 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\sv0__data_o$next[63:0]$10849 \reg + assign $6\sv0__data_o$next[63:0]$10833 \reg case - assign $6\sv0__data_o$next[63:0]$10849 $5\sv0__data_o$next[63:0]$10848 + assign $6\sv0__data_o$next[63:0]$10833 $5\sv0__data_o$next[63:0]$10832 end case - assign $1\sv0__data_o$next[63:0]$10844 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\sv0__data_o$next[63:0]$10828 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\sv0__data_o$next[63:0]$10850 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\sv0__data_o$next[63:0]$10834 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\sv0__data_o$next[63:0]$10850 $1\sv0__data_o$next[63:0]$10844 + assign $7\sv0__data_o$next[63:0]$10834 $1\sv0__data_o$next[63:0]$10828 end sync always - update \sv0__data_o$next $0\sv0__data_o$next[63:0]$10843 + update \sv0__data_o$next $0\sv0__data_o$next[63:0]$10827 end - attribute \src "libresoc.v:178067.3-178102.6" - process $proc$libresoc.v:178067$10851 + attribute \src "libresoc.v:179375.3-179410.6" + process $proc$libresoc.v:179375$10835 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10852 $1\wr_detect$7[0:0]$10853 - attribute \src "libresoc.v:178068.5-178068.29" + assign $0\wr_detect$7[0:0]$10836 $1\wr_detect$7[0:0]$10837 + attribute \src "libresoc.v:179376.5-179376.29" switch \initial - attribute \src "libresoc.v:178068.9-178068.17" + attribute \src "libresoc.v:179376.9-179376.17" case 1'1 case end @@ -362567,61 +333937,61 @@ module \reg_0$135 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10853 $5\wr_detect$7[0:0]$10857 + assign $1\wr_detect$7[0:0]$10837 $5\wr_detect$7[0:0]$10841 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10854 1'1 + assign $2\wr_detect$7[0:0]$10838 1'1 case - assign $2\wr_detect$7[0:0]$10854 1'0 + assign $2\wr_detect$7[0:0]$10838 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$10855 1'1 + assign $3\wr_detect$7[0:0]$10839 1'1 case - assign $3\wr_detect$7[0:0]$10855 $2\wr_detect$7[0:0]$10854 + assign $3\wr_detect$7[0:0]$10839 $2\wr_detect$7[0:0]$10838 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$10856 1'1 + assign $4\wr_detect$7[0:0]$10840 1'1 case - assign $4\wr_detect$7[0:0]$10856 $3\wr_detect$7[0:0]$10855 + assign $4\wr_detect$7[0:0]$10840 $3\wr_detect$7[0:0]$10839 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$10857 1'1 + assign $5\wr_detect$7[0:0]$10841 1'1 case - assign $5\wr_detect$7[0:0]$10857 $4\wr_detect$7[0:0]$10856 + assign $5\wr_detect$7[0:0]$10841 $4\wr_detect$7[0:0]$10840 end case - assign $1\wr_detect$7[0:0]$10853 1'0 + assign $1\wr_detect$7[0:0]$10837 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10852 + update \wr_detect$7 $0\wr_detect$7[0:0]$10836 end - attribute \src "libresoc.v:178103.3-178135.6" - process $proc$libresoc.v:178103$10858 + attribute \src "libresoc.v:179411.3-179443.6" + process $proc$libresoc.v:179411$10842 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[63:0]$10859 $5\reg$next[63:0]$10864 - attribute \src "libresoc.v:178104.5-178104.29" + assign $0\reg$next[63:0]$10843 $5\reg$next[63:0]$10848 + attribute \src "libresoc.v:179412.5-179412.29" switch \initial - attribute \src "libresoc.v:178104.9-178104.17" + attribute \src "libresoc.v:179412.9-179412.17" case 1'1 case end @@ -362630,254 +334000,254 @@ module \reg_0$135 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[63:0]$10860 \nia0__data_i + assign $1\reg$next[63:0]$10844 \nia0__data_i case - assign $1\reg$next[63:0]$10860 \reg + assign $1\reg$next[63:0]$10844 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \msr0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[63:0]$10861 \msr0__data_i + assign $2\reg$next[63:0]$10845 \msr0__data_i case - assign $2\reg$next[63:0]$10861 $1\reg$next[63:0]$10860 + assign $2\reg$next[63:0]$10845 $1\reg$next[63:0]$10844 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \sv0__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[63:0]$10862 \sv0__data_i + assign $3\reg$next[63:0]$10846 \sv0__data_i case - assign $3\reg$next[63:0]$10862 $2\reg$next[63:0]$10861 + assign $3\reg$next[63:0]$10846 $2\reg$next[63:0]$10845 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \d_wr10__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[63:0]$10863 \d_wr10__data_i + assign $4\reg$next[63:0]$10847 \d_wr10__data_i case - assign $4\reg$next[63:0]$10863 $3\reg$next[63:0]$10862 + assign $4\reg$next[63:0]$10847 $3\reg$next[63:0]$10846 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[63:0]$10864 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $5\reg$next[63:0]$10848 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $5\reg$next[63:0]$10864 $4\reg$next[63:0]$10863 + assign $5\reg$next[63:0]$10848 $4\reg$next[63:0]$10847 end sync always - update \reg$next $0\reg$next[63:0]$10859 + update \reg$next $0\reg$next[63:0]$10843 end - connect \$1 $not$libresoc.v:177846$10809_Y - connect \$3 $not$libresoc.v:177847$10810_Y - connect \$6 $not$libresoc.v:177848$10811_Y + connect \$1 $not$libresoc.v:179154$10793_Y + connect \$3 $not$libresoc.v:179155$10794_Y + connect \$6 $not$libresoc.v:179156$10795_Y end -attribute \src "libresoc.v:178140.1-178695.10" +attribute \src "libresoc.v:179448.1-180003.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_1" attribute \generator "nMigen" module \reg_1 - attribute \src "libresoc.v:178248.3-178287.6" - wire width 4 $0\cr_pred1__data_o$next[3:0]$10884 - attribute \src "libresoc.v:178246.3-178247.49" + attribute \src "libresoc.v:179556.3-179595.6" + wire width 4 $0\cr_pred1__data_o$next[3:0]$10868 + attribute \src "libresoc.v:179554.3-179555.49" wire width 4 $0\cr_pred1__data_o[3:0] - attribute \src "libresoc.v:178141.7-178141.20" + attribute \src "libresoc.v:179449.7-179449.20" wire $0\initial[0:0] - attribute \src "libresoc.v:178625.3-178664.6" - wire width 4 $0\r1__data_o$next[3:0]$10955 - attribute \src "libresoc.v:178238.3-178239.37" + attribute \src "libresoc.v:179933.3-179972.6" + wire width 4 $0\r1__data_o$next[3:0]$10939 + attribute \src "libresoc.v:179546.3-179547.37" wire width 4 $0\r1__data_o[3:0] - attribute \src "libresoc.v:178318.3-178357.6" - wire width 4 $0\r21__data_o$next[3:0]$10893 - attribute \src "libresoc.v:178236.3-178237.39" + attribute \src "libresoc.v:179626.3-179665.6" + wire width 4 $0\r21__data_o$next[3:0]$10877 + attribute \src "libresoc.v:179544.3-179545.39" wire width 4 $0\r21__data_o[3:0] - attribute \src "libresoc.v:178388.3-178414.6" - wire width 4 $0\reg$next[3:0]$10907 - attribute \src "libresoc.v:178234.3-178235.25" + attribute \src "libresoc.v:179696.3-179722.6" + wire width 4 $0\reg$next[3:0]$10891 + attribute \src "libresoc.v:179542.3-179543.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:178415.3-178454.6" - wire width 4 $0\src11__data_o$next[3:0]$10913 - attribute \src "libresoc.v:178244.3-178245.43" + attribute \src "libresoc.v:179723.3-179762.6" + wire width 4 $0\src11__data_o$next[3:0]$10897 + attribute \src "libresoc.v:179552.3-179553.43" wire width 4 $0\src11__data_o[3:0] - attribute \src "libresoc.v:178485.3-178524.6" - wire width 4 $0\src21__data_o$next[3:0]$10927 - attribute \src "libresoc.v:178242.3-178243.43" + attribute \src "libresoc.v:179793.3-179832.6" + wire width 4 $0\src21__data_o$next[3:0]$10911 + attribute \src "libresoc.v:179550.3-179551.43" wire width 4 $0\src21__data_o[3:0] - attribute \src "libresoc.v:178555.3-178594.6" - wire width 4 $0\src31__data_o$next[3:0]$10941 - attribute \src "libresoc.v:178240.3-178241.43" + attribute \src "libresoc.v:179863.3-179902.6" + wire width 4 $0\src31__data_o$next[3:0]$10925 + attribute \src "libresoc.v:179548.3-179549.43" wire width 4 $0\src31__data_o[3:0] - attribute \src "libresoc.v:178595.3-178624.6" - wire $0\wr_detect$10[0:0]$10949 - attribute \src "libresoc.v:178665.3-178694.6" - wire $0\wr_detect$13[0:0]$10963 - attribute \src "libresoc.v:178358.3-178387.6" - wire $0\wr_detect$16[0:0]$10901 - attribute \src "libresoc.v:178455.3-178484.6" - wire $0\wr_detect$4[0:0]$10921 - attribute \src "libresoc.v:178525.3-178554.6" - wire $0\wr_detect$7[0:0]$10935 - attribute \src "libresoc.v:178288.3-178317.6" + attribute \src "libresoc.v:179903.3-179932.6" + wire $0\wr_detect$10[0:0]$10933 + attribute \src "libresoc.v:179973.3-180002.6" + wire $0\wr_detect$13[0:0]$10947 + attribute \src "libresoc.v:179666.3-179695.6" + wire $0\wr_detect$16[0:0]$10885 + attribute \src "libresoc.v:179763.3-179792.6" + wire $0\wr_detect$4[0:0]$10905 + attribute \src "libresoc.v:179833.3-179862.6" + wire $0\wr_detect$7[0:0]$10919 + attribute \src "libresoc.v:179596.3-179625.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:178248.3-178287.6" - wire width 4 $1\cr_pred1__data_o$next[3:0]$10885 - attribute \src "libresoc.v:178160.13-178160.36" + attribute \src "libresoc.v:179556.3-179595.6" + wire width 4 $1\cr_pred1__data_o$next[3:0]$10869 + attribute \src "libresoc.v:179468.13-179468.36" wire width 4 $1\cr_pred1__data_o[3:0] - attribute \src "libresoc.v:178625.3-178664.6" - wire width 4 $1\r1__data_o$next[3:0]$10956 - attribute \src "libresoc.v:178175.13-178175.30" + attribute \src "libresoc.v:179933.3-179972.6" + wire width 4 $1\r1__data_o$next[3:0]$10940 + attribute \src "libresoc.v:179483.13-179483.30" wire width 4 $1\r1__data_o[3:0] - attribute \src "libresoc.v:178318.3-178357.6" - wire width 4 $1\r21__data_o$next[3:0]$10894 - attribute \src "libresoc.v:178182.13-178182.31" + attribute \src "libresoc.v:179626.3-179665.6" + wire width 4 $1\r21__data_o$next[3:0]$10878 + attribute \src "libresoc.v:179490.13-179490.31" wire width 4 $1\r21__data_o[3:0] - attribute \src "libresoc.v:178388.3-178414.6" - wire width 4 $1\reg$next[3:0]$10908 - attribute \src "libresoc.v:178188.13-178188.25" + attribute \src "libresoc.v:179696.3-179722.6" + wire width 4 $1\reg$next[3:0]$10892 + attribute \src "libresoc.v:179496.13-179496.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:178415.3-178454.6" - wire width 4 $1\src11__data_o$next[3:0]$10914 - attribute \src "libresoc.v:178193.13-178193.33" + attribute \src "libresoc.v:179723.3-179762.6" + wire width 4 $1\src11__data_o$next[3:0]$10898 + attribute \src "libresoc.v:179501.13-179501.33" wire width 4 $1\src11__data_o[3:0] - attribute \src "libresoc.v:178485.3-178524.6" - wire width 4 $1\src21__data_o$next[3:0]$10928 - attribute \src "libresoc.v:178200.13-178200.33" + attribute \src "libresoc.v:179793.3-179832.6" + wire width 4 $1\src21__data_o$next[3:0]$10912 + attribute \src "libresoc.v:179508.13-179508.33" wire width 4 $1\src21__data_o[3:0] - attribute \src "libresoc.v:178555.3-178594.6" - wire width 4 $1\src31__data_o$next[3:0]$10942 - attribute \src "libresoc.v:178207.13-178207.33" + attribute \src "libresoc.v:179863.3-179902.6" + wire width 4 $1\src31__data_o$next[3:0]$10926 + attribute \src "libresoc.v:179515.13-179515.33" wire width 4 $1\src31__data_o[3:0] - attribute \src "libresoc.v:178595.3-178624.6" - wire $1\wr_detect$10[0:0]$10950 - attribute \src "libresoc.v:178665.3-178694.6" - wire $1\wr_detect$13[0:0]$10964 - attribute \src "libresoc.v:178358.3-178387.6" - wire $1\wr_detect$16[0:0]$10902 - attribute \src "libresoc.v:178455.3-178484.6" - wire $1\wr_detect$4[0:0]$10922 - attribute \src "libresoc.v:178525.3-178554.6" - wire $1\wr_detect$7[0:0]$10936 - attribute \src "libresoc.v:178288.3-178317.6" + attribute \src "libresoc.v:179903.3-179932.6" + wire $1\wr_detect$10[0:0]$10934 + attribute \src "libresoc.v:179973.3-180002.6" + wire $1\wr_detect$13[0:0]$10948 + attribute \src "libresoc.v:179666.3-179695.6" + wire $1\wr_detect$16[0:0]$10886 + attribute \src "libresoc.v:179763.3-179792.6" + wire $1\wr_detect$4[0:0]$10906 + attribute \src "libresoc.v:179833.3-179862.6" + wire $1\wr_detect$7[0:0]$10920 + attribute \src "libresoc.v:179596.3-179625.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:178248.3-178287.6" - wire width 4 $2\cr_pred1__data_o$next[3:0]$10886 - attribute \src "libresoc.v:178625.3-178664.6" - wire width 4 $2\r1__data_o$next[3:0]$10957 - attribute \src "libresoc.v:178318.3-178357.6" - wire width 4 $2\r21__data_o$next[3:0]$10895 - attribute \src "libresoc.v:178388.3-178414.6" - wire width 4 $2\reg$next[3:0]$10909 - attribute \src "libresoc.v:178415.3-178454.6" - wire width 4 $2\src11__data_o$next[3:0]$10915 - attribute \src "libresoc.v:178485.3-178524.6" - wire width 4 $2\src21__data_o$next[3:0]$10929 - attribute \src "libresoc.v:178555.3-178594.6" - wire width 4 $2\src31__data_o$next[3:0]$10943 - attribute \src "libresoc.v:178595.3-178624.6" - wire $2\wr_detect$10[0:0]$10951 - attribute \src "libresoc.v:178665.3-178694.6" - wire $2\wr_detect$13[0:0]$10965 - attribute \src "libresoc.v:178358.3-178387.6" - wire $2\wr_detect$16[0:0]$10903 - attribute \src "libresoc.v:178455.3-178484.6" - wire $2\wr_detect$4[0:0]$10923 - attribute \src "libresoc.v:178525.3-178554.6" - wire $2\wr_detect$7[0:0]$10937 - attribute \src "libresoc.v:178288.3-178317.6" + attribute \src "libresoc.v:179556.3-179595.6" + wire width 4 $2\cr_pred1__data_o$next[3:0]$10870 + attribute \src "libresoc.v:179933.3-179972.6" + wire width 4 $2\r1__data_o$next[3:0]$10941 + attribute \src "libresoc.v:179626.3-179665.6" + wire width 4 $2\r21__data_o$next[3:0]$10879 + attribute \src "libresoc.v:179696.3-179722.6" + wire width 4 $2\reg$next[3:0]$10893 + attribute \src "libresoc.v:179723.3-179762.6" + wire width 4 $2\src11__data_o$next[3:0]$10899 + attribute \src "libresoc.v:179793.3-179832.6" + wire width 4 $2\src21__data_o$next[3:0]$10913 + attribute \src "libresoc.v:179863.3-179902.6" + wire width 4 $2\src31__data_o$next[3:0]$10927 + attribute \src "libresoc.v:179903.3-179932.6" + wire $2\wr_detect$10[0:0]$10935 + attribute \src "libresoc.v:179973.3-180002.6" + wire $2\wr_detect$13[0:0]$10949 + attribute \src "libresoc.v:179666.3-179695.6" + wire $2\wr_detect$16[0:0]$10887 + attribute \src "libresoc.v:179763.3-179792.6" + wire $2\wr_detect$4[0:0]$10907 + attribute \src "libresoc.v:179833.3-179862.6" + wire $2\wr_detect$7[0:0]$10921 + attribute \src "libresoc.v:179596.3-179625.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:178248.3-178287.6" - wire width 4 $3\cr_pred1__data_o$next[3:0]$10887 - attribute \src "libresoc.v:178625.3-178664.6" - wire width 4 $3\r1__data_o$next[3:0]$10958 - attribute \src "libresoc.v:178318.3-178357.6" - wire width 4 $3\r21__data_o$next[3:0]$10896 - attribute \src "libresoc.v:178388.3-178414.6" - wire width 4 $3\reg$next[3:0]$10910 - attribute \src "libresoc.v:178415.3-178454.6" - wire width 4 $3\src11__data_o$next[3:0]$10916 - attribute \src "libresoc.v:178485.3-178524.6" - wire width 4 $3\src21__data_o$next[3:0]$10930 - attribute \src "libresoc.v:178555.3-178594.6" - wire width 4 $3\src31__data_o$next[3:0]$10944 - attribute \src "libresoc.v:178595.3-178624.6" - wire $3\wr_detect$10[0:0]$10952 - attribute \src "libresoc.v:178665.3-178694.6" - wire $3\wr_detect$13[0:0]$10966 - attribute \src "libresoc.v:178358.3-178387.6" - wire $3\wr_detect$16[0:0]$10904 - attribute \src "libresoc.v:178455.3-178484.6" - wire $3\wr_detect$4[0:0]$10924 - attribute \src "libresoc.v:178525.3-178554.6" - wire $3\wr_detect$7[0:0]$10938 - attribute \src "libresoc.v:178288.3-178317.6" + attribute \src "libresoc.v:179556.3-179595.6" + wire width 4 $3\cr_pred1__data_o$next[3:0]$10871 + attribute \src "libresoc.v:179933.3-179972.6" + wire width 4 $3\r1__data_o$next[3:0]$10942 + attribute \src "libresoc.v:179626.3-179665.6" + wire width 4 $3\r21__data_o$next[3:0]$10880 + attribute \src "libresoc.v:179696.3-179722.6" + wire width 4 $3\reg$next[3:0]$10894 + attribute \src "libresoc.v:179723.3-179762.6" + wire width 4 $3\src11__data_o$next[3:0]$10900 + attribute \src "libresoc.v:179793.3-179832.6" + wire width 4 $3\src21__data_o$next[3:0]$10914 + attribute \src "libresoc.v:179863.3-179902.6" + wire width 4 $3\src31__data_o$next[3:0]$10928 + attribute \src "libresoc.v:179903.3-179932.6" + wire $3\wr_detect$10[0:0]$10936 + attribute \src "libresoc.v:179973.3-180002.6" + wire $3\wr_detect$13[0:0]$10950 + attribute \src "libresoc.v:179666.3-179695.6" + wire $3\wr_detect$16[0:0]$10888 + attribute \src "libresoc.v:179763.3-179792.6" + wire $3\wr_detect$4[0:0]$10908 + attribute \src "libresoc.v:179833.3-179862.6" + wire $3\wr_detect$7[0:0]$10922 + attribute \src "libresoc.v:179596.3-179625.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:178248.3-178287.6" - wire width 4 $4\cr_pred1__data_o$next[3:0]$10888 - attribute \src "libresoc.v:178625.3-178664.6" - wire width 4 $4\r1__data_o$next[3:0]$10959 - attribute \src "libresoc.v:178318.3-178357.6" - wire width 4 $4\r21__data_o$next[3:0]$10897 - attribute \src "libresoc.v:178388.3-178414.6" - wire width 4 $4\reg$next[3:0]$10911 - attribute \src "libresoc.v:178415.3-178454.6" - wire width 4 $4\src11__data_o$next[3:0]$10917 - attribute \src "libresoc.v:178485.3-178524.6" - wire width 4 $4\src21__data_o$next[3:0]$10931 - attribute \src "libresoc.v:178555.3-178594.6" - wire width 4 $4\src31__data_o$next[3:0]$10945 - attribute \src "libresoc.v:178595.3-178624.6" - wire $4\wr_detect$10[0:0]$10953 - attribute \src "libresoc.v:178665.3-178694.6" - wire $4\wr_detect$13[0:0]$10967 - attribute \src "libresoc.v:178358.3-178387.6" - wire $4\wr_detect$16[0:0]$10905 - attribute \src "libresoc.v:178455.3-178484.6" - wire $4\wr_detect$4[0:0]$10925 - attribute \src "libresoc.v:178525.3-178554.6" - wire $4\wr_detect$7[0:0]$10939 - attribute \src "libresoc.v:178288.3-178317.6" + attribute \src "libresoc.v:179556.3-179595.6" + wire width 4 $4\cr_pred1__data_o$next[3:0]$10872 + attribute \src "libresoc.v:179933.3-179972.6" + wire width 4 $4\r1__data_o$next[3:0]$10943 + attribute \src "libresoc.v:179626.3-179665.6" + wire width 4 $4\r21__data_o$next[3:0]$10881 + attribute \src "libresoc.v:179696.3-179722.6" + wire width 4 $4\reg$next[3:0]$10895 + attribute \src "libresoc.v:179723.3-179762.6" + wire width 4 $4\src11__data_o$next[3:0]$10901 + attribute \src "libresoc.v:179793.3-179832.6" + wire width 4 $4\src21__data_o$next[3:0]$10915 + attribute \src "libresoc.v:179863.3-179902.6" + wire width 4 $4\src31__data_o$next[3:0]$10929 + attribute \src "libresoc.v:179903.3-179932.6" + wire $4\wr_detect$10[0:0]$10937 + attribute \src "libresoc.v:179973.3-180002.6" + wire $4\wr_detect$13[0:0]$10951 + attribute \src "libresoc.v:179666.3-179695.6" + wire $4\wr_detect$16[0:0]$10889 + attribute \src "libresoc.v:179763.3-179792.6" + wire $4\wr_detect$4[0:0]$10909 + attribute \src "libresoc.v:179833.3-179862.6" + wire $4\wr_detect$7[0:0]$10923 + attribute \src "libresoc.v:179596.3-179625.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:178248.3-178287.6" - wire width 4 $5\cr_pred1__data_o$next[3:0]$10889 - attribute \src "libresoc.v:178625.3-178664.6" - wire width 4 $5\r1__data_o$next[3:0]$10960 - attribute \src "libresoc.v:178318.3-178357.6" - wire width 4 $5\r21__data_o$next[3:0]$10898 - attribute \src "libresoc.v:178415.3-178454.6" - wire width 4 $5\src11__data_o$next[3:0]$10918 - attribute \src "libresoc.v:178485.3-178524.6" - wire width 4 $5\src21__data_o$next[3:0]$10932 - attribute \src "libresoc.v:178555.3-178594.6" - wire width 4 $5\src31__data_o$next[3:0]$10946 - attribute \src "libresoc.v:178248.3-178287.6" - wire width 4 $6\cr_pred1__data_o$next[3:0]$10890 - attribute \src "libresoc.v:178625.3-178664.6" - wire width 4 $6\r1__data_o$next[3:0]$10961 - attribute \src "libresoc.v:178318.3-178357.6" - wire width 4 $6\r21__data_o$next[3:0]$10899 - attribute \src "libresoc.v:178415.3-178454.6" - wire width 4 $6\src11__data_o$next[3:0]$10919 - attribute \src "libresoc.v:178485.3-178524.6" - wire width 4 $6\src21__data_o$next[3:0]$10933 - attribute \src "libresoc.v:178555.3-178594.6" - wire width 4 $6\src31__data_o$next[3:0]$10947 - attribute \src "libresoc.v:178228.17-178228.104" - wire $not$libresoc.v:178228$10870_Y - attribute \src "libresoc.v:178229.18-178229.105" - wire $not$libresoc.v:178229$10871_Y - attribute \src "libresoc.v:178230.18-178230.105" - wire $not$libresoc.v:178230$10872_Y - attribute \src "libresoc.v:178231.17-178231.100" - wire $not$libresoc.v:178231$10873_Y - attribute \src "libresoc.v:178232.17-178232.103" - wire $not$libresoc.v:178232$10874_Y - attribute \src "libresoc.v:178233.17-178233.103" - wire $not$libresoc.v:178233$10875_Y + attribute \src "libresoc.v:179556.3-179595.6" + wire width 4 $5\cr_pred1__data_o$next[3:0]$10873 + attribute \src "libresoc.v:179933.3-179972.6" + wire width 4 $5\r1__data_o$next[3:0]$10944 + attribute \src "libresoc.v:179626.3-179665.6" + wire width 4 $5\r21__data_o$next[3:0]$10882 + attribute \src "libresoc.v:179723.3-179762.6" + wire width 4 $5\src11__data_o$next[3:0]$10902 + attribute \src "libresoc.v:179793.3-179832.6" + wire width 4 $5\src21__data_o$next[3:0]$10916 + attribute \src "libresoc.v:179863.3-179902.6" + wire width 4 $5\src31__data_o$next[3:0]$10930 + attribute \src "libresoc.v:179556.3-179595.6" + wire width 4 $6\cr_pred1__data_o$next[3:0]$10874 + attribute \src "libresoc.v:179933.3-179972.6" + wire width 4 $6\r1__data_o$next[3:0]$10945 + attribute \src "libresoc.v:179626.3-179665.6" + wire width 4 $6\r21__data_o$next[3:0]$10883 + attribute \src "libresoc.v:179723.3-179762.6" + wire width 4 $6\src11__data_o$next[3:0]$10903 + attribute \src "libresoc.v:179793.3-179832.6" + wire width 4 $6\src21__data_o$next[3:0]$10917 + attribute \src "libresoc.v:179863.3-179902.6" + wire width 4 $6\src31__data_o$next[3:0]$10931 + attribute \src "libresoc.v:179536.17-179536.104" + wire $not$libresoc.v:179536$10854_Y + attribute \src "libresoc.v:179537.18-179537.105" + wire $not$libresoc.v:179537$10855_Y + attribute \src "libresoc.v:179538.18-179538.105" + wire $not$libresoc.v:179538$10856_Y + attribute \src "libresoc.v:179539.17-179539.100" + wire $not$libresoc.v:179539$10857_Y + attribute \src "libresoc.v:179540.17-179540.103" + wire $not$libresoc.v:179540$10858_Y + attribute \src "libresoc.v:179541.17-179541.103" + wire $not$libresoc.v:179541$10859_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -362890,9 +334260,9 @@ module \reg_1 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 20 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 3 \cr_pred1__data_o @@ -362908,7 +334278,7 @@ module \reg_1 wire width 4 input 13 \dest21__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest21__wen - attribute \src "libresoc.v:178141.7-178141.15" + attribute \src "libresoc.v:179449.7-179449.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 14 \r1__data_o @@ -362961,175 +334331,175 @@ module \reg_1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178228$10870 + cell $not $not$libresoc.v:179536$10854 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:178228$10870_Y + connect \Y $not$libresoc.v:179536$10854_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178229$10871 + cell $not $not$libresoc.v:179537$10855 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:178229$10871_Y + connect \Y $not$libresoc.v:179537$10855_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178230$10872 + cell $not $not$libresoc.v:179538$10856 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$16 - connect \Y $not$libresoc.v:178230$10872_Y + connect \Y $not$libresoc.v:179538$10856_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178231$10873 + cell $not $not$libresoc.v:179539$10857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:178231$10873_Y + connect \Y $not$libresoc.v:179539$10857_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178232$10874 + cell $not $not$libresoc.v:179540$10858 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:178232$10874_Y + connect \Y $not$libresoc.v:179540$10858_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178233$10875 + cell $not $not$libresoc.v:179541$10859 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:178233$10875_Y + connect \Y $not$libresoc.v:179541$10859_Y end - attribute \src "libresoc.v:178141.7-178141.20" - process $proc$libresoc.v:178141$10968 + attribute \src "libresoc.v:179449.7-179449.20" + process $proc$libresoc.v:179449$10952 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:178160.13-178160.36" - process $proc$libresoc.v:178160$10969 + attribute \src "libresoc.v:179468.13-179468.36" + process $proc$libresoc.v:179468$10953 assign { } { } assign $1\cr_pred1__data_o[3:0] 4'0000 sync always sync init update \cr_pred1__data_o $1\cr_pred1__data_o[3:0] end - attribute \src "libresoc.v:178175.13-178175.30" - process $proc$libresoc.v:178175$10970 + attribute \src "libresoc.v:179483.13-179483.30" + process $proc$libresoc.v:179483$10954 assign { } { } assign $1\r1__data_o[3:0] 4'0000 sync always sync init update \r1__data_o $1\r1__data_o[3:0] end - attribute \src "libresoc.v:178182.13-178182.31" - process $proc$libresoc.v:178182$10971 + attribute \src "libresoc.v:179490.13-179490.31" + process $proc$libresoc.v:179490$10955 assign { } { } assign $1\r21__data_o[3:0] 4'0000 sync always sync init update \r21__data_o $1\r21__data_o[3:0] end - attribute \src "libresoc.v:178188.13-178188.25" - process $proc$libresoc.v:178188$10972 + attribute \src "libresoc.v:179496.13-179496.25" + process $proc$libresoc.v:179496$10956 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:178193.13-178193.33" - process $proc$libresoc.v:178193$10973 + attribute \src "libresoc.v:179501.13-179501.33" + process $proc$libresoc.v:179501$10957 assign { } { } assign $1\src11__data_o[3:0] 4'0000 sync always sync init update \src11__data_o $1\src11__data_o[3:0] end - attribute \src "libresoc.v:178200.13-178200.33" - process $proc$libresoc.v:178200$10974 + attribute \src "libresoc.v:179508.13-179508.33" + process $proc$libresoc.v:179508$10958 assign { } { } assign $1\src21__data_o[3:0] 4'0000 sync always sync init update \src21__data_o $1\src21__data_o[3:0] end - attribute \src "libresoc.v:178207.13-178207.33" - process $proc$libresoc.v:178207$10975 + attribute \src "libresoc.v:179515.13-179515.33" + process $proc$libresoc.v:179515$10959 assign { } { } assign $1\src31__data_o[3:0] 4'0000 sync always sync init update \src31__data_o $1\src31__data_o[3:0] end - attribute \src "libresoc.v:178234.3-178235.25" - process $proc$libresoc.v:178234$10876 + attribute \src "libresoc.v:179542.3-179543.25" + process $proc$libresoc.v:179542$10860 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:178236.3-178237.39" - process $proc$libresoc.v:178236$10877 + attribute \src "libresoc.v:179544.3-179545.39" + process $proc$libresoc.v:179544$10861 assign { } { } assign $0\r21__data_o[3:0] \r21__data_o$next sync posedge \coresync_clk update \r21__data_o $0\r21__data_o[3:0] end - attribute \src "libresoc.v:178238.3-178239.37" - process $proc$libresoc.v:178238$10878 + attribute \src "libresoc.v:179546.3-179547.37" + process $proc$libresoc.v:179546$10862 assign { } { } assign $0\r1__data_o[3:0] \r1__data_o$next sync posedge \coresync_clk update \r1__data_o $0\r1__data_o[3:0] end - attribute \src "libresoc.v:178240.3-178241.43" - process $proc$libresoc.v:178240$10879 + attribute \src "libresoc.v:179548.3-179549.43" + process $proc$libresoc.v:179548$10863 assign { } { } assign $0\src31__data_o[3:0] \src31__data_o$next sync posedge \coresync_clk update \src31__data_o $0\src31__data_o[3:0] end - attribute \src "libresoc.v:178242.3-178243.43" - process $proc$libresoc.v:178242$10880 + attribute \src "libresoc.v:179550.3-179551.43" + process $proc$libresoc.v:179550$10864 assign { } { } assign $0\src21__data_o[3:0] \src21__data_o$next sync posedge \coresync_clk update \src21__data_o $0\src21__data_o[3:0] end - attribute \src "libresoc.v:178244.3-178245.43" - process $proc$libresoc.v:178244$10881 + attribute \src "libresoc.v:179552.3-179553.43" + process $proc$libresoc.v:179552$10865 assign { } { } assign $0\src11__data_o[3:0] \src11__data_o$next sync posedge \coresync_clk update \src11__data_o $0\src11__data_o[3:0] end - attribute \src "libresoc.v:178246.3-178247.49" - process $proc$libresoc.v:178246$10882 + attribute \src "libresoc.v:179554.3-179555.49" + process $proc$libresoc.v:179554$10866 assign { } { } assign $0\cr_pred1__data_o[3:0] \cr_pred1__data_o$next sync posedge \coresync_clk update \cr_pred1__data_o $0\cr_pred1__data_o[3:0] end - attribute \src "libresoc.v:178248.3-178287.6" - process $proc$libresoc.v:178248$10883 + attribute \src "libresoc.v:179556.3-179595.6" + process $proc$libresoc.v:179556$10867 assign { } { } assign { } { } assign { } { } - assign $0\cr_pred1__data_o$next[3:0]$10884 $6\cr_pred1__data_o$next[3:0]$10890 - attribute \src "libresoc.v:178249.5-178249.29" + assign $0\cr_pred1__data_o$next[3:0]$10868 $6\cr_pred1__data_o$next[3:0]$10874 + attribute \src "libresoc.v:179557.5-179557.29" switch \initial - attribute \src "libresoc.v:178249.9-178249.17" + attribute \src "libresoc.v:179557.9-179557.17" case 1'1 case end @@ -363141,66 +334511,66 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\cr_pred1__data_o$next[3:0]$10885 $5\cr_pred1__data_o$next[3:0]$10889 + assign $1\cr_pred1__data_o$next[3:0]$10869 $5\cr_pred1__data_o$next[3:0]$10873 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_pred1__data_o$next[3:0]$10886 \dest11__data_i + assign $2\cr_pred1__data_o$next[3:0]$10870 \dest11__data_i case - assign $2\cr_pred1__data_o$next[3:0]$10886 4'0000 + assign $2\cr_pred1__data_o$next[3:0]$10870 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\cr_pred1__data_o$next[3:0]$10887 \dest21__data_i + assign $3\cr_pred1__data_o$next[3:0]$10871 \dest21__data_i case - assign $3\cr_pred1__data_o$next[3:0]$10887 $2\cr_pred1__data_o$next[3:0]$10886 + assign $3\cr_pred1__data_o$next[3:0]$10871 $2\cr_pred1__data_o$next[3:0]$10870 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cr_pred1__data_o$next[3:0]$10888 \w1__data_i + assign $4\cr_pred1__data_o$next[3:0]$10872 \w1__data_i case - assign $4\cr_pred1__data_o$next[3:0]$10888 $3\cr_pred1__data_o$next[3:0]$10887 + assign $4\cr_pred1__data_o$next[3:0]$10872 $3\cr_pred1__data_o$next[3:0]$10871 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\cr_pred1__data_o$next[3:0]$10889 \reg + assign $5\cr_pred1__data_o$next[3:0]$10873 \reg case - assign $5\cr_pred1__data_o$next[3:0]$10889 $4\cr_pred1__data_o$next[3:0]$10888 + assign $5\cr_pred1__data_o$next[3:0]$10873 $4\cr_pred1__data_o$next[3:0]$10872 end case - assign $1\cr_pred1__data_o$next[3:0]$10885 4'0000 + assign $1\cr_pred1__data_o$next[3:0]$10869 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cr_pred1__data_o$next[3:0]$10890 4'0000 + assign $6\cr_pred1__data_o$next[3:0]$10874 4'0000 case - assign $6\cr_pred1__data_o$next[3:0]$10890 $1\cr_pred1__data_o$next[3:0]$10885 + assign $6\cr_pred1__data_o$next[3:0]$10874 $1\cr_pred1__data_o$next[3:0]$10869 end sync always - update \cr_pred1__data_o$next $0\cr_pred1__data_o$next[3:0]$10884 + update \cr_pred1__data_o$next $0\cr_pred1__data_o$next[3:0]$10868 end - attribute \src "libresoc.v:178288.3-178317.6" - process $proc$libresoc.v:178288$10891 + attribute \src "libresoc.v:179596.3-179625.6" + process $proc$libresoc.v:179596$10875 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:178289.5-178289.29" + attribute \src "libresoc.v:179597.5-179597.29" switch \initial - attribute \src "libresoc.v:178289.9-178289.17" + attribute \src "libresoc.v:179597.9-179597.17" case 1'1 case end @@ -363246,15 +334616,15 @@ module \reg_1 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:178318.3-178357.6" - process $proc$libresoc.v:178318$10892 + attribute \src "libresoc.v:179626.3-179665.6" + process $proc$libresoc.v:179626$10876 assign { } { } assign { } { } assign { } { } - assign $0\r21__data_o$next[3:0]$10893 $6\r21__data_o$next[3:0]$10899 - attribute \src "libresoc.v:178319.5-178319.29" + assign $0\r21__data_o$next[3:0]$10877 $6\r21__data_o$next[3:0]$10883 + attribute \src "libresoc.v:179627.5-179627.29" switch \initial - attribute \src "libresoc.v:178319.9-178319.17" + attribute \src "libresoc.v:179627.9-179627.17" case 1'1 case end @@ -363266,66 +334636,66 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\r21__data_o$next[3:0]$10894 $5\r21__data_o$next[3:0]$10898 + assign $1\r21__data_o$next[3:0]$10878 $5\r21__data_o$next[3:0]$10882 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r21__data_o$next[3:0]$10895 \dest11__data_i + assign $2\r21__data_o$next[3:0]$10879 \dest11__data_i case - assign $2\r21__data_o$next[3:0]$10895 4'0000 + assign $2\r21__data_o$next[3:0]$10879 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r21__data_o$next[3:0]$10896 \dest21__data_i + assign $3\r21__data_o$next[3:0]$10880 \dest21__data_i case - assign $3\r21__data_o$next[3:0]$10896 $2\r21__data_o$next[3:0]$10895 + assign $3\r21__data_o$next[3:0]$10880 $2\r21__data_o$next[3:0]$10879 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r21__data_o$next[3:0]$10897 \w1__data_i + assign $4\r21__data_o$next[3:0]$10881 \w1__data_i case - assign $4\r21__data_o$next[3:0]$10897 $3\r21__data_o$next[3:0]$10896 + assign $4\r21__data_o$next[3:0]$10881 $3\r21__data_o$next[3:0]$10880 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$15 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r21__data_o$next[3:0]$10898 \reg + assign $5\r21__data_o$next[3:0]$10882 \reg case - assign $5\r21__data_o$next[3:0]$10898 $4\r21__data_o$next[3:0]$10897 + assign $5\r21__data_o$next[3:0]$10882 $4\r21__data_o$next[3:0]$10881 end case - assign $1\r21__data_o$next[3:0]$10894 4'0000 + assign $1\r21__data_o$next[3:0]$10878 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r21__data_o$next[3:0]$10899 4'0000 + assign $6\r21__data_o$next[3:0]$10883 4'0000 case - assign $6\r21__data_o$next[3:0]$10899 $1\r21__data_o$next[3:0]$10894 + assign $6\r21__data_o$next[3:0]$10883 $1\r21__data_o$next[3:0]$10878 end sync always - update \r21__data_o$next $0\r21__data_o$next[3:0]$10893 + update \r21__data_o$next $0\r21__data_o$next[3:0]$10877 end - attribute \src "libresoc.v:178358.3-178387.6" - process $proc$libresoc.v:178358$10900 + attribute \src "libresoc.v:179666.3-179695.6" + process $proc$libresoc.v:179666$10884 assign { } { } assign { } { } - assign $0\wr_detect$16[0:0]$10901 $1\wr_detect$16[0:0]$10902 - attribute \src "libresoc.v:178359.5-178359.29" + assign $0\wr_detect$16[0:0]$10885 $1\wr_detect$16[0:0]$10886 + attribute \src "libresoc.v:179667.5-179667.29" switch \initial - attribute \src "libresoc.v:178359.9-178359.17" + attribute \src "libresoc.v:179667.9-179667.17" case 1'1 case end @@ -363337,51 +334707,51 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$16[0:0]$10902 $4\wr_detect$16[0:0]$10905 + assign $1\wr_detect$16[0:0]$10886 $4\wr_detect$16[0:0]$10889 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$16[0:0]$10903 1'1 + assign $2\wr_detect$16[0:0]$10887 1'1 case - assign $2\wr_detect$16[0:0]$10903 1'0 + assign $2\wr_detect$16[0:0]$10887 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$16[0:0]$10904 1'1 + assign $3\wr_detect$16[0:0]$10888 1'1 case - assign $3\wr_detect$16[0:0]$10904 $2\wr_detect$16[0:0]$10903 + assign $3\wr_detect$16[0:0]$10888 $2\wr_detect$16[0:0]$10887 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$16[0:0]$10905 1'1 + assign $4\wr_detect$16[0:0]$10889 1'1 case - assign $4\wr_detect$16[0:0]$10905 $3\wr_detect$16[0:0]$10904 + assign $4\wr_detect$16[0:0]$10889 $3\wr_detect$16[0:0]$10888 end case - assign $1\wr_detect$16[0:0]$10902 1'0 + assign $1\wr_detect$16[0:0]$10886 1'0 end sync always - update \wr_detect$16 $0\wr_detect$16[0:0]$10901 + update \wr_detect$16 $0\wr_detect$16[0:0]$10885 end - attribute \src "libresoc.v:178388.3-178414.6" - process $proc$libresoc.v:178388$10906 + attribute \src "libresoc.v:179696.3-179722.6" + process $proc$libresoc.v:179696$10890 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$10907 $4\reg$next[3:0]$10911 - attribute \src "libresoc.v:178389.5-178389.29" + assign $0\reg$next[3:0]$10891 $4\reg$next[3:0]$10895 + attribute \src "libresoc.v:179697.5-179697.29" switch \initial - attribute \src "libresoc.v:178389.9-178389.17" + attribute \src "libresoc.v:179697.9-179697.17" case 1'1 case end @@ -363390,49 +334760,49 @@ module \reg_1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$10908 \dest11__data_i + assign $1\reg$next[3:0]$10892 \dest11__data_i case - assign $1\reg$next[3:0]$10908 \reg + assign $1\reg$next[3:0]$10892 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$10909 \dest21__data_i + assign $2\reg$next[3:0]$10893 \dest21__data_i case - assign $2\reg$next[3:0]$10909 $1\reg$next[3:0]$10908 + assign $2\reg$next[3:0]$10893 $1\reg$next[3:0]$10892 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$10910 \w1__data_i + assign $3\reg$next[3:0]$10894 \w1__data_i case - assign $3\reg$next[3:0]$10910 $2\reg$next[3:0]$10909 + assign $3\reg$next[3:0]$10894 $2\reg$next[3:0]$10893 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$10911 4'0000 + assign $4\reg$next[3:0]$10895 4'0000 case - assign $4\reg$next[3:0]$10911 $3\reg$next[3:0]$10910 + assign $4\reg$next[3:0]$10895 $3\reg$next[3:0]$10894 end sync always - update \reg$next $0\reg$next[3:0]$10907 + update \reg$next $0\reg$next[3:0]$10891 end - attribute \src "libresoc.v:178415.3-178454.6" - process $proc$libresoc.v:178415$10912 + attribute \src "libresoc.v:179723.3-179762.6" + process $proc$libresoc.v:179723$10896 assign { } { } assign { } { } assign { } { } - assign $0\src11__data_o$next[3:0]$10913 $6\src11__data_o$next[3:0]$10919 - attribute \src "libresoc.v:178416.5-178416.29" + assign $0\src11__data_o$next[3:0]$10897 $6\src11__data_o$next[3:0]$10903 + attribute \src "libresoc.v:179724.5-179724.29" switch \initial - attribute \src "libresoc.v:178416.9-178416.17" + attribute \src "libresoc.v:179724.9-179724.17" case 1'1 case end @@ -363444,66 +334814,66 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\src11__data_o$next[3:0]$10914 $5\src11__data_o$next[3:0]$10918 + assign $1\src11__data_o$next[3:0]$10898 $5\src11__data_o$next[3:0]$10902 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src11__data_o$next[3:0]$10915 \dest11__data_i + assign $2\src11__data_o$next[3:0]$10899 \dest11__data_i case - assign $2\src11__data_o$next[3:0]$10915 4'0000 + assign $2\src11__data_o$next[3:0]$10899 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src11__data_o$next[3:0]$10916 \dest21__data_i + assign $3\src11__data_o$next[3:0]$10900 \dest21__data_i case - assign $3\src11__data_o$next[3:0]$10916 $2\src11__data_o$next[3:0]$10915 + assign $3\src11__data_o$next[3:0]$10900 $2\src11__data_o$next[3:0]$10899 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src11__data_o$next[3:0]$10917 \w1__data_i + assign $4\src11__data_o$next[3:0]$10901 \w1__data_i case - assign $4\src11__data_o$next[3:0]$10917 $3\src11__data_o$next[3:0]$10916 + assign $4\src11__data_o$next[3:0]$10901 $3\src11__data_o$next[3:0]$10900 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src11__data_o$next[3:0]$10918 \reg + assign $5\src11__data_o$next[3:0]$10902 \reg case - assign $5\src11__data_o$next[3:0]$10918 $4\src11__data_o$next[3:0]$10917 + assign $5\src11__data_o$next[3:0]$10902 $4\src11__data_o$next[3:0]$10901 end case - assign $1\src11__data_o$next[3:0]$10914 4'0000 + assign $1\src11__data_o$next[3:0]$10898 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src11__data_o$next[3:0]$10919 4'0000 + assign $6\src11__data_o$next[3:0]$10903 4'0000 case - assign $6\src11__data_o$next[3:0]$10919 $1\src11__data_o$next[3:0]$10914 + assign $6\src11__data_o$next[3:0]$10903 $1\src11__data_o$next[3:0]$10898 end sync always - update \src11__data_o$next $0\src11__data_o$next[3:0]$10913 + update \src11__data_o$next $0\src11__data_o$next[3:0]$10897 end - attribute \src "libresoc.v:178455.3-178484.6" - process $proc$libresoc.v:178455$10920 + attribute \src "libresoc.v:179763.3-179792.6" + process $proc$libresoc.v:179763$10904 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$10921 $1\wr_detect$4[0:0]$10922 - attribute \src "libresoc.v:178456.5-178456.29" + assign $0\wr_detect$4[0:0]$10905 $1\wr_detect$4[0:0]$10906 + attribute \src "libresoc.v:179764.5-179764.29" switch \initial - attribute \src "libresoc.v:178456.9-178456.17" + attribute \src "libresoc.v:179764.9-179764.17" case 1'1 case end @@ -363515,49 +334885,49 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$10922 $4\wr_detect$4[0:0]$10925 + assign $1\wr_detect$4[0:0]$10906 $4\wr_detect$4[0:0]$10909 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$10923 1'1 + assign $2\wr_detect$4[0:0]$10907 1'1 case - assign $2\wr_detect$4[0:0]$10923 1'0 + assign $2\wr_detect$4[0:0]$10907 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$10924 1'1 + assign $3\wr_detect$4[0:0]$10908 1'1 case - assign $3\wr_detect$4[0:0]$10924 $2\wr_detect$4[0:0]$10923 + assign $3\wr_detect$4[0:0]$10908 $2\wr_detect$4[0:0]$10907 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$10925 1'1 + assign $4\wr_detect$4[0:0]$10909 1'1 case - assign $4\wr_detect$4[0:0]$10925 $3\wr_detect$4[0:0]$10924 + assign $4\wr_detect$4[0:0]$10909 $3\wr_detect$4[0:0]$10908 end case - assign $1\wr_detect$4[0:0]$10922 1'0 + assign $1\wr_detect$4[0:0]$10906 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$10921 + update \wr_detect$4 $0\wr_detect$4[0:0]$10905 end - attribute \src "libresoc.v:178485.3-178524.6" - process $proc$libresoc.v:178485$10926 + attribute \src "libresoc.v:179793.3-179832.6" + process $proc$libresoc.v:179793$10910 assign { } { } assign { } { } assign { } { } - assign $0\src21__data_o$next[3:0]$10927 $6\src21__data_o$next[3:0]$10933 - attribute \src "libresoc.v:178486.5-178486.29" + assign $0\src21__data_o$next[3:0]$10911 $6\src21__data_o$next[3:0]$10917 + attribute \src "libresoc.v:179794.5-179794.29" switch \initial - attribute \src "libresoc.v:178486.9-178486.17" + attribute \src "libresoc.v:179794.9-179794.17" case 1'1 case end @@ -363569,66 +334939,66 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\src21__data_o$next[3:0]$10928 $5\src21__data_o$next[3:0]$10932 + assign $1\src21__data_o$next[3:0]$10912 $5\src21__data_o$next[3:0]$10916 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src21__data_o$next[3:0]$10929 \dest11__data_i + assign $2\src21__data_o$next[3:0]$10913 \dest11__data_i case - assign $2\src21__data_o$next[3:0]$10929 4'0000 + assign $2\src21__data_o$next[3:0]$10913 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src21__data_o$next[3:0]$10930 \dest21__data_i + assign $3\src21__data_o$next[3:0]$10914 \dest21__data_i case - assign $3\src21__data_o$next[3:0]$10930 $2\src21__data_o$next[3:0]$10929 + assign $3\src21__data_o$next[3:0]$10914 $2\src21__data_o$next[3:0]$10913 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src21__data_o$next[3:0]$10931 \w1__data_i + assign $4\src21__data_o$next[3:0]$10915 \w1__data_i case - assign $4\src21__data_o$next[3:0]$10931 $3\src21__data_o$next[3:0]$10930 + assign $4\src21__data_o$next[3:0]$10915 $3\src21__data_o$next[3:0]$10914 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src21__data_o$next[3:0]$10932 \reg + assign $5\src21__data_o$next[3:0]$10916 \reg case - assign $5\src21__data_o$next[3:0]$10932 $4\src21__data_o$next[3:0]$10931 + assign $5\src21__data_o$next[3:0]$10916 $4\src21__data_o$next[3:0]$10915 end case - assign $1\src21__data_o$next[3:0]$10928 4'0000 + assign $1\src21__data_o$next[3:0]$10912 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src21__data_o$next[3:0]$10933 4'0000 + assign $6\src21__data_o$next[3:0]$10917 4'0000 case - assign $6\src21__data_o$next[3:0]$10933 $1\src21__data_o$next[3:0]$10928 + assign $6\src21__data_o$next[3:0]$10917 $1\src21__data_o$next[3:0]$10912 end sync always - update \src21__data_o$next $0\src21__data_o$next[3:0]$10927 + update \src21__data_o$next $0\src21__data_o$next[3:0]$10911 end - attribute \src "libresoc.v:178525.3-178554.6" - process $proc$libresoc.v:178525$10934 + attribute \src "libresoc.v:179833.3-179862.6" + process $proc$libresoc.v:179833$10918 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$10935 $1\wr_detect$7[0:0]$10936 - attribute \src "libresoc.v:178526.5-178526.29" + assign $0\wr_detect$7[0:0]$10919 $1\wr_detect$7[0:0]$10920 + attribute \src "libresoc.v:179834.5-179834.29" switch \initial - attribute \src "libresoc.v:178526.9-178526.17" + attribute \src "libresoc.v:179834.9-179834.17" case 1'1 case end @@ -363640,49 +335010,49 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$10936 $4\wr_detect$7[0:0]$10939 + assign $1\wr_detect$7[0:0]$10920 $4\wr_detect$7[0:0]$10923 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$10937 1'1 + assign $2\wr_detect$7[0:0]$10921 1'1 case - assign $2\wr_detect$7[0:0]$10937 1'0 + assign $2\wr_detect$7[0:0]$10921 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$10938 1'1 + assign $3\wr_detect$7[0:0]$10922 1'1 case - assign $3\wr_detect$7[0:0]$10938 $2\wr_detect$7[0:0]$10937 + assign $3\wr_detect$7[0:0]$10922 $2\wr_detect$7[0:0]$10921 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$10939 1'1 + assign $4\wr_detect$7[0:0]$10923 1'1 case - assign $4\wr_detect$7[0:0]$10939 $3\wr_detect$7[0:0]$10938 + assign $4\wr_detect$7[0:0]$10923 $3\wr_detect$7[0:0]$10922 end case - assign $1\wr_detect$7[0:0]$10936 1'0 + assign $1\wr_detect$7[0:0]$10920 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$10935 + update \wr_detect$7 $0\wr_detect$7[0:0]$10919 end - attribute \src "libresoc.v:178555.3-178594.6" - process $proc$libresoc.v:178555$10940 + attribute \src "libresoc.v:179863.3-179902.6" + process $proc$libresoc.v:179863$10924 assign { } { } assign { } { } assign { } { } - assign $0\src31__data_o$next[3:0]$10941 $6\src31__data_o$next[3:0]$10947 - attribute \src "libresoc.v:178556.5-178556.29" + assign $0\src31__data_o$next[3:0]$10925 $6\src31__data_o$next[3:0]$10931 + attribute \src "libresoc.v:179864.5-179864.29" switch \initial - attribute \src "libresoc.v:178556.9-178556.17" + attribute \src "libresoc.v:179864.9-179864.17" case 1'1 case end @@ -363694,66 +335064,66 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\src31__data_o$next[3:0]$10942 $5\src31__data_o$next[3:0]$10946 + assign $1\src31__data_o$next[3:0]$10926 $5\src31__data_o$next[3:0]$10930 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src31__data_o$next[3:0]$10943 \dest11__data_i + assign $2\src31__data_o$next[3:0]$10927 \dest11__data_i case - assign $2\src31__data_o$next[3:0]$10943 4'0000 + assign $2\src31__data_o$next[3:0]$10927 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src31__data_o$next[3:0]$10944 \dest21__data_i + assign $3\src31__data_o$next[3:0]$10928 \dest21__data_i case - assign $3\src31__data_o$next[3:0]$10944 $2\src31__data_o$next[3:0]$10943 + assign $3\src31__data_o$next[3:0]$10928 $2\src31__data_o$next[3:0]$10927 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src31__data_o$next[3:0]$10945 \w1__data_i + assign $4\src31__data_o$next[3:0]$10929 \w1__data_i case - assign $4\src31__data_o$next[3:0]$10945 $3\src31__data_o$next[3:0]$10944 + assign $4\src31__data_o$next[3:0]$10929 $3\src31__data_o$next[3:0]$10928 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src31__data_o$next[3:0]$10946 \reg + assign $5\src31__data_o$next[3:0]$10930 \reg case - assign $5\src31__data_o$next[3:0]$10946 $4\src31__data_o$next[3:0]$10945 + assign $5\src31__data_o$next[3:0]$10930 $4\src31__data_o$next[3:0]$10929 end case - assign $1\src31__data_o$next[3:0]$10942 4'0000 + assign $1\src31__data_o$next[3:0]$10926 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src31__data_o$next[3:0]$10947 4'0000 + assign $6\src31__data_o$next[3:0]$10931 4'0000 case - assign $6\src31__data_o$next[3:0]$10947 $1\src31__data_o$next[3:0]$10942 + assign $6\src31__data_o$next[3:0]$10931 $1\src31__data_o$next[3:0]$10926 end sync always - update \src31__data_o$next $0\src31__data_o$next[3:0]$10941 + update \src31__data_o$next $0\src31__data_o$next[3:0]$10925 end - attribute \src "libresoc.v:178595.3-178624.6" - process $proc$libresoc.v:178595$10948 + attribute \src "libresoc.v:179903.3-179932.6" + process $proc$libresoc.v:179903$10932 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$10949 $1\wr_detect$10[0:0]$10950 - attribute \src "libresoc.v:178596.5-178596.29" + assign $0\wr_detect$10[0:0]$10933 $1\wr_detect$10[0:0]$10934 + attribute \src "libresoc.v:179904.5-179904.29" switch \initial - attribute \src "libresoc.v:178596.9-178596.17" + attribute \src "libresoc.v:179904.9-179904.17" case 1'1 case end @@ -363765,49 +335135,49 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$10950 $4\wr_detect$10[0:0]$10953 + assign $1\wr_detect$10[0:0]$10934 $4\wr_detect$10[0:0]$10937 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$10951 1'1 + assign $2\wr_detect$10[0:0]$10935 1'1 case - assign $2\wr_detect$10[0:0]$10951 1'0 + assign $2\wr_detect$10[0:0]$10935 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$10952 1'1 + assign $3\wr_detect$10[0:0]$10936 1'1 case - assign $3\wr_detect$10[0:0]$10952 $2\wr_detect$10[0:0]$10951 + assign $3\wr_detect$10[0:0]$10936 $2\wr_detect$10[0:0]$10935 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$10953 1'1 + assign $4\wr_detect$10[0:0]$10937 1'1 case - assign $4\wr_detect$10[0:0]$10953 $3\wr_detect$10[0:0]$10952 + assign $4\wr_detect$10[0:0]$10937 $3\wr_detect$10[0:0]$10936 end case - assign $1\wr_detect$10[0:0]$10950 1'0 + assign $1\wr_detect$10[0:0]$10934 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$10949 + update \wr_detect$10 $0\wr_detect$10[0:0]$10933 end - attribute \src "libresoc.v:178625.3-178664.6" - process $proc$libresoc.v:178625$10954 + attribute \src "libresoc.v:179933.3-179972.6" + process $proc$libresoc.v:179933$10938 assign { } { } assign { } { } assign { } { } - assign $0\r1__data_o$next[3:0]$10955 $6\r1__data_o$next[3:0]$10961 - attribute \src "libresoc.v:178626.5-178626.29" + assign $0\r1__data_o$next[3:0]$10939 $6\r1__data_o$next[3:0]$10945 + attribute \src "libresoc.v:179934.5-179934.29" switch \initial - attribute \src "libresoc.v:178626.9-178626.17" + attribute \src "libresoc.v:179934.9-179934.17" case 1'1 case end @@ -363819,66 +335189,66 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\r1__data_o$next[3:0]$10956 $5\r1__data_o$next[3:0]$10960 + assign $1\r1__data_o$next[3:0]$10940 $5\r1__data_o$next[3:0]$10944 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r1__data_o$next[3:0]$10957 \dest11__data_i + assign $2\r1__data_o$next[3:0]$10941 \dest11__data_i case - assign $2\r1__data_o$next[3:0]$10957 4'0000 + assign $2\r1__data_o$next[3:0]$10941 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r1__data_o$next[3:0]$10958 \dest21__data_i + assign $3\r1__data_o$next[3:0]$10942 \dest21__data_i case - assign $3\r1__data_o$next[3:0]$10958 $2\r1__data_o$next[3:0]$10957 + assign $3\r1__data_o$next[3:0]$10942 $2\r1__data_o$next[3:0]$10941 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r1__data_o$next[3:0]$10959 \w1__data_i + assign $4\r1__data_o$next[3:0]$10943 \w1__data_i case - assign $4\r1__data_o$next[3:0]$10959 $3\r1__data_o$next[3:0]$10958 + assign $4\r1__data_o$next[3:0]$10943 $3\r1__data_o$next[3:0]$10942 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r1__data_o$next[3:0]$10960 \reg + assign $5\r1__data_o$next[3:0]$10944 \reg case - assign $5\r1__data_o$next[3:0]$10960 $4\r1__data_o$next[3:0]$10959 + assign $5\r1__data_o$next[3:0]$10944 $4\r1__data_o$next[3:0]$10943 end case - assign $1\r1__data_o$next[3:0]$10956 4'0000 + assign $1\r1__data_o$next[3:0]$10940 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r1__data_o$next[3:0]$10961 4'0000 + assign $6\r1__data_o$next[3:0]$10945 4'0000 case - assign $6\r1__data_o$next[3:0]$10961 $1\r1__data_o$next[3:0]$10956 + assign $6\r1__data_o$next[3:0]$10945 $1\r1__data_o$next[3:0]$10940 end sync always - update \r1__data_o$next $0\r1__data_o$next[3:0]$10955 + update \r1__data_o$next $0\r1__data_o$next[3:0]$10939 end - attribute \src "libresoc.v:178665.3-178694.6" - process $proc$libresoc.v:178665$10962 + attribute \src "libresoc.v:179973.3-180002.6" + process $proc$libresoc.v:179973$10946 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$10963 $1\wr_detect$13[0:0]$10964 - attribute \src "libresoc.v:178666.5-178666.29" + assign $0\wr_detect$13[0:0]$10947 $1\wr_detect$13[0:0]$10948 + attribute \src "libresoc.v:179974.5-179974.29" switch \initial - attribute \src "libresoc.v:178666.9-178666.17" + attribute \src "libresoc.v:179974.9-179974.17" case 1'1 case end @@ -363890,206 +335260,206 @@ module \reg_1 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$10964 $4\wr_detect$13[0:0]$10967 + assign $1\wr_detect$13[0:0]$10948 $4\wr_detect$13[0:0]$10951 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$10965 1'1 + assign $2\wr_detect$13[0:0]$10949 1'1 case - assign $2\wr_detect$13[0:0]$10965 1'0 + assign $2\wr_detect$13[0:0]$10949 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$10966 1'1 + assign $3\wr_detect$13[0:0]$10950 1'1 case - assign $3\wr_detect$13[0:0]$10966 $2\wr_detect$13[0:0]$10965 + assign $3\wr_detect$13[0:0]$10950 $2\wr_detect$13[0:0]$10949 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$10967 1'1 + assign $4\wr_detect$13[0:0]$10951 1'1 case - assign $4\wr_detect$13[0:0]$10967 $3\wr_detect$13[0:0]$10966 + assign $4\wr_detect$13[0:0]$10951 $3\wr_detect$13[0:0]$10950 end case - assign $1\wr_detect$13[0:0]$10964 1'0 + assign $1\wr_detect$13[0:0]$10948 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$10963 + update \wr_detect$13 $0\wr_detect$13[0:0]$10947 end - connect \$9 $not$libresoc.v:178228$10870_Y - connect \$12 $not$libresoc.v:178229$10871_Y - connect \$15 $not$libresoc.v:178230$10872_Y - connect \$1 $not$libresoc.v:178231$10873_Y - connect \$3 $not$libresoc.v:178232$10874_Y - connect \$6 $not$libresoc.v:178233$10875_Y + connect \$9 $not$libresoc.v:179536$10854_Y + connect \$12 $not$libresoc.v:179537$10855_Y + connect \$15 $not$libresoc.v:179538$10856_Y + connect \$1 $not$libresoc.v:179539$10857_Y + connect \$3 $not$libresoc.v:179540$10858_Y + connect \$6 $not$libresoc.v:179541$10859_Y end -attribute \src "libresoc.v:178699.1-179144.10" +attribute \src "libresoc.v:180007.1-180452.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_1" attribute \generator "nMigen" module \reg_1$133 - attribute \src "libresoc.v:178700.7-178700.20" + attribute \src "libresoc.v:180008.7-180008.20" wire $0\initial[0:0] - attribute \src "libresoc.v:179029.3-179074.6" - wire width 2 $0\r1__data_o$next[1:0]$11028 - attribute \src "libresoc.v:178775.3-178776.37" + attribute \src "libresoc.v:180337.3-180382.6" + wire width 2 $0\r1__data_o$next[1:0]$11012 + attribute \src "libresoc.v:180083.3-180084.37" wire width 2 $0\r1__data_o[1:0] - attribute \src "libresoc.v:179111.3-179143.6" - wire width 2 $0\reg$next[1:0]$11044 - attribute \src "libresoc.v:178773.3-178774.25" + attribute \src "libresoc.v:180419.3-180451.6" + wire width 2 $0\reg$next[1:0]$11028 + attribute \src "libresoc.v:180081.3-180082.25" wire width 2 $0\reg[1:0] - attribute \src "libresoc.v:178783.3-178828.6" - wire width 2 $0\src11__data_o$next[1:0]$10986 - attribute \src "libresoc.v:178781.3-178782.43" + attribute \src "libresoc.v:180091.3-180136.6" + wire width 2 $0\src11__data_o$next[1:0]$10970 + attribute \src "libresoc.v:180089.3-180090.43" wire width 2 $0\src11__data_o[1:0] - attribute \src "libresoc.v:178865.3-178910.6" - wire width 2 $0\src21__data_o$next[1:0]$10996 - attribute \src "libresoc.v:178779.3-178780.43" + attribute \src "libresoc.v:180173.3-180218.6" + wire width 2 $0\src21__data_o$next[1:0]$10980 + attribute \src "libresoc.v:180087.3-180088.43" wire width 2 $0\src21__data_o[1:0] - attribute \src "libresoc.v:178947.3-178992.6" - wire width 2 $0\src31__data_o$next[1:0]$11012 - attribute \src "libresoc.v:178777.3-178778.43" + attribute \src "libresoc.v:180255.3-180300.6" + wire width 2 $0\src31__data_o$next[1:0]$10996 + attribute \src "libresoc.v:180085.3-180086.43" wire width 2 $0\src31__data_o[1:0] - attribute \src "libresoc.v:179075.3-179110.6" - wire $0\wr_detect$10[0:0]$11037 - attribute \src "libresoc.v:178911.3-178946.6" - wire $0\wr_detect$4[0:0]$11005 - attribute \src "libresoc.v:178993.3-179028.6" - wire $0\wr_detect$7[0:0]$11021 - attribute \src "libresoc.v:178829.3-178864.6" + attribute \src "libresoc.v:180383.3-180418.6" + wire $0\wr_detect$10[0:0]$11021 + attribute \src "libresoc.v:180219.3-180254.6" + wire $0\wr_detect$4[0:0]$10989 + attribute \src "libresoc.v:180301.3-180336.6" + wire $0\wr_detect$7[0:0]$11005 + attribute \src "libresoc.v:180137.3-180172.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:179029.3-179074.6" - wire width 2 $1\r1__data_o$next[1:0]$11029 - attribute \src "libresoc.v:178727.13-178727.30" + attribute \src "libresoc.v:180337.3-180382.6" + wire width 2 $1\r1__data_o$next[1:0]$11013 + attribute \src "libresoc.v:180035.13-180035.30" wire width 2 $1\r1__data_o[1:0] - attribute \src "libresoc.v:179111.3-179143.6" - wire width 2 $1\reg$next[1:0]$11045 - attribute \src "libresoc.v:178733.13-178733.25" + attribute \src "libresoc.v:180419.3-180451.6" + wire width 2 $1\reg$next[1:0]$11029 + attribute \src "libresoc.v:180041.13-180041.25" wire width 2 $1\reg[1:0] - attribute \src "libresoc.v:178783.3-178828.6" - wire width 2 $1\src11__data_o$next[1:0]$10987 - attribute \src "libresoc.v:178738.13-178738.33" + attribute \src "libresoc.v:180091.3-180136.6" + wire width 2 $1\src11__data_o$next[1:0]$10971 + attribute \src "libresoc.v:180046.13-180046.33" wire width 2 $1\src11__data_o[1:0] - attribute \src "libresoc.v:178865.3-178910.6" - wire width 2 $1\src21__data_o$next[1:0]$10997 - attribute \src "libresoc.v:178745.13-178745.33" + attribute \src "libresoc.v:180173.3-180218.6" + wire width 2 $1\src21__data_o$next[1:0]$10981 + attribute \src "libresoc.v:180053.13-180053.33" wire width 2 $1\src21__data_o[1:0] - attribute \src "libresoc.v:178947.3-178992.6" - wire width 2 $1\src31__data_o$next[1:0]$11013 - attribute \src "libresoc.v:178752.13-178752.33" + attribute \src "libresoc.v:180255.3-180300.6" + wire width 2 $1\src31__data_o$next[1:0]$10997 + attribute \src "libresoc.v:180060.13-180060.33" wire width 2 $1\src31__data_o[1:0] - attribute \src "libresoc.v:179075.3-179110.6" - wire $1\wr_detect$10[0:0]$11038 - attribute \src "libresoc.v:178911.3-178946.6" - wire $1\wr_detect$4[0:0]$11006 - attribute \src "libresoc.v:178993.3-179028.6" - wire $1\wr_detect$7[0:0]$11022 - attribute \src "libresoc.v:178829.3-178864.6" + attribute \src "libresoc.v:180383.3-180418.6" + wire $1\wr_detect$10[0:0]$11022 + attribute \src "libresoc.v:180219.3-180254.6" + wire $1\wr_detect$4[0:0]$10990 + attribute \src "libresoc.v:180301.3-180336.6" + wire $1\wr_detect$7[0:0]$11006 + attribute \src "libresoc.v:180137.3-180172.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:179029.3-179074.6" - wire width 2 $2\r1__data_o$next[1:0]$11030 - attribute \src "libresoc.v:179111.3-179143.6" - wire width 2 $2\reg$next[1:0]$11046 - attribute \src "libresoc.v:178783.3-178828.6" - wire width 2 $2\src11__data_o$next[1:0]$10988 - attribute \src "libresoc.v:178865.3-178910.6" - wire width 2 $2\src21__data_o$next[1:0]$10998 - attribute \src "libresoc.v:178947.3-178992.6" - wire width 2 $2\src31__data_o$next[1:0]$11014 - attribute \src "libresoc.v:179075.3-179110.6" - wire $2\wr_detect$10[0:0]$11039 - attribute \src "libresoc.v:178911.3-178946.6" - wire $2\wr_detect$4[0:0]$11007 - attribute \src "libresoc.v:178993.3-179028.6" - wire $2\wr_detect$7[0:0]$11023 - attribute \src "libresoc.v:178829.3-178864.6" + attribute \src "libresoc.v:180337.3-180382.6" + wire width 2 $2\r1__data_o$next[1:0]$11014 + attribute \src "libresoc.v:180419.3-180451.6" + wire width 2 $2\reg$next[1:0]$11030 + attribute \src "libresoc.v:180091.3-180136.6" + wire width 2 $2\src11__data_o$next[1:0]$10972 + attribute \src "libresoc.v:180173.3-180218.6" + wire width 2 $2\src21__data_o$next[1:0]$10982 + attribute \src "libresoc.v:180255.3-180300.6" + wire width 2 $2\src31__data_o$next[1:0]$10998 + attribute \src "libresoc.v:180383.3-180418.6" + wire $2\wr_detect$10[0:0]$11023 + attribute \src "libresoc.v:180219.3-180254.6" + wire $2\wr_detect$4[0:0]$10991 + attribute \src "libresoc.v:180301.3-180336.6" + wire $2\wr_detect$7[0:0]$11007 + attribute \src "libresoc.v:180137.3-180172.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:179029.3-179074.6" - wire width 2 $3\r1__data_o$next[1:0]$11031 - attribute \src "libresoc.v:179111.3-179143.6" - wire width 2 $3\reg$next[1:0]$11047 - attribute \src "libresoc.v:178783.3-178828.6" - wire width 2 $3\src11__data_o$next[1:0]$10989 - attribute \src "libresoc.v:178865.3-178910.6" - wire width 2 $3\src21__data_o$next[1:0]$10999 - attribute \src "libresoc.v:178947.3-178992.6" - wire width 2 $3\src31__data_o$next[1:0]$11015 - attribute \src "libresoc.v:179075.3-179110.6" - wire $3\wr_detect$10[0:0]$11040 - attribute \src "libresoc.v:178911.3-178946.6" - wire $3\wr_detect$4[0:0]$11008 - attribute \src "libresoc.v:178993.3-179028.6" - wire $3\wr_detect$7[0:0]$11024 - attribute \src "libresoc.v:178829.3-178864.6" + attribute \src "libresoc.v:180337.3-180382.6" + wire width 2 $3\r1__data_o$next[1:0]$11015 + attribute \src "libresoc.v:180419.3-180451.6" + wire width 2 $3\reg$next[1:0]$11031 + attribute \src "libresoc.v:180091.3-180136.6" + wire width 2 $3\src11__data_o$next[1:0]$10973 + attribute \src "libresoc.v:180173.3-180218.6" + wire width 2 $3\src21__data_o$next[1:0]$10983 + attribute \src "libresoc.v:180255.3-180300.6" + wire width 2 $3\src31__data_o$next[1:0]$10999 + attribute \src "libresoc.v:180383.3-180418.6" + wire $3\wr_detect$10[0:0]$11024 + attribute \src "libresoc.v:180219.3-180254.6" + wire $3\wr_detect$4[0:0]$10992 + attribute \src "libresoc.v:180301.3-180336.6" + wire $3\wr_detect$7[0:0]$11008 + attribute \src "libresoc.v:180137.3-180172.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:179029.3-179074.6" - wire width 2 $4\r1__data_o$next[1:0]$11032 - attribute \src "libresoc.v:179111.3-179143.6" - wire width 2 $4\reg$next[1:0]$11048 - attribute \src "libresoc.v:178783.3-178828.6" - wire width 2 $4\src11__data_o$next[1:0]$10990 - attribute \src "libresoc.v:178865.3-178910.6" - wire width 2 $4\src21__data_o$next[1:0]$11000 - attribute \src "libresoc.v:178947.3-178992.6" - wire width 2 $4\src31__data_o$next[1:0]$11016 - attribute \src "libresoc.v:179075.3-179110.6" - wire $4\wr_detect$10[0:0]$11041 - attribute \src "libresoc.v:178911.3-178946.6" - wire $4\wr_detect$4[0:0]$11009 - attribute \src "libresoc.v:178993.3-179028.6" - wire $4\wr_detect$7[0:0]$11025 - attribute \src "libresoc.v:178829.3-178864.6" + attribute \src "libresoc.v:180337.3-180382.6" + wire width 2 $4\r1__data_o$next[1:0]$11016 + attribute \src "libresoc.v:180419.3-180451.6" + wire width 2 $4\reg$next[1:0]$11032 + attribute \src "libresoc.v:180091.3-180136.6" + wire width 2 $4\src11__data_o$next[1:0]$10974 + attribute \src "libresoc.v:180173.3-180218.6" + wire width 2 $4\src21__data_o$next[1:0]$10984 + attribute \src "libresoc.v:180255.3-180300.6" + wire width 2 $4\src31__data_o$next[1:0]$11000 + attribute \src "libresoc.v:180383.3-180418.6" + wire $4\wr_detect$10[0:0]$11025 + attribute \src "libresoc.v:180219.3-180254.6" + wire $4\wr_detect$4[0:0]$10993 + attribute \src "libresoc.v:180301.3-180336.6" + wire $4\wr_detect$7[0:0]$11009 + attribute \src "libresoc.v:180137.3-180172.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:179029.3-179074.6" - wire width 2 $5\r1__data_o$next[1:0]$11033 - attribute \src "libresoc.v:179111.3-179143.6" - wire width 2 $5\reg$next[1:0]$11049 - attribute \src "libresoc.v:178783.3-178828.6" - wire width 2 $5\src11__data_o$next[1:0]$10991 - attribute \src "libresoc.v:178865.3-178910.6" - wire width 2 $5\src21__data_o$next[1:0]$11001 - attribute \src "libresoc.v:178947.3-178992.6" - wire width 2 $5\src31__data_o$next[1:0]$11017 - attribute \src "libresoc.v:179075.3-179110.6" - wire $5\wr_detect$10[0:0]$11042 - attribute \src "libresoc.v:178911.3-178946.6" - wire $5\wr_detect$4[0:0]$11010 - attribute \src "libresoc.v:178993.3-179028.6" - wire $5\wr_detect$7[0:0]$11026 - attribute \src "libresoc.v:178829.3-178864.6" + attribute \src "libresoc.v:180337.3-180382.6" + wire width 2 $5\r1__data_o$next[1:0]$11017 + attribute \src "libresoc.v:180419.3-180451.6" + wire width 2 $5\reg$next[1:0]$11033 + attribute \src "libresoc.v:180091.3-180136.6" + wire width 2 $5\src11__data_o$next[1:0]$10975 + attribute \src "libresoc.v:180173.3-180218.6" + wire width 2 $5\src21__data_o$next[1:0]$10985 + attribute \src "libresoc.v:180255.3-180300.6" + wire width 2 $5\src31__data_o$next[1:0]$11001 + attribute \src "libresoc.v:180383.3-180418.6" + wire $5\wr_detect$10[0:0]$11026 + attribute \src "libresoc.v:180219.3-180254.6" + wire $5\wr_detect$4[0:0]$10994 + attribute \src "libresoc.v:180301.3-180336.6" + wire $5\wr_detect$7[0:0]$11010 + attribute \src "libresoc.v:180137.3-180172.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:179029.3-179074.6" - wire width 2 $6\r1__data_o$next[1:0]$11034 - attribute \src "libresoc.v:178783.3-178828.6" - wire width 2 $6\src11__data_o$next[1:0]$10992 - attribute \src "libresoc.v:178865.3-178910.6" - wire width 2 $6\src21__data_o$next[1:0]$11002 - attribute \src "libresoc.v:178947.3-178992.6" - wire width 2 $6\src31__data_o$next[1:0]$11018 - attribute \src "libresoc.v:179029.3-179074.6" - wire width 2 $7\r1__data_o$next[1:0]$11035 - attribute \src "libresoc.v:178783.3-178828.6" - wire width 2 $7\src11__data_o$next[1:0]$10993 - attribute \src "libresoc.v:178865.3-178910.6" - wire width 2 $7\src21__data_o$next[1:0]$11003 - attribute \src "libresoc.v:178947.3-178992.6" - wire width 2 $7\src31__data_o$next[1:0]$11019 - attribute \src "libresoc.v:178769.17-178769.104" - wire $not$libresoc.v:178769$10976_Y - attribute \src "libresoc.v:178770.17-178770.100" - wire $not$libresoc.v:178770$10977_Y - attribute \src "libresoc.v:178771.17-178771.103" - wire $not$libresoc.v:178771$10978_Y - attribute \src "libresoc.v:178772.17-178772.103" - wire $not$libresoc.v:178772$10979_Y + attribute \src "libresoc.v:180337.3-180382.6" + wire width 2 $6\r1__data_o$next[1:0]$11018 + attribute \src "libresoc.v:180091.3-180136.6" + wire width 2 $6\src11__data_o$next[1:0]$10976 + attribute \src "libresoc.v:180173.3-180218.6" + wire width 2 $6\src21__data_o$next[1:0]$10986 + attribute \src "libresoc.v:180255.3-180300.6" + wire width 2 $6\src31__data_o$next[1:0]$11002 + attribute \src "libresoc.v:180337.3-180382.6" + wire width 2 $7\r1__data_o$next[1:0]$11019 + attribute \src "libresoc.v:180091.3-180136.6" + wire width 2 $7\src11__data_o$next[1:0]$10977 + attribute \src "libresoc.v:180173.3-180218.6" + wire width 2 $7\src21__data_o$next[1:0]$10987 + attribute \src "libresoc.v:180255.3-180300.6" + wire width 2 $7\src31__data_o$next[1:0]$11003 + attribute \src "libresoc.v:180077.17-180077.104" + wire $not$libresoc.v:180077$10960_Y + attribute \src "libresoc.v:180078.17-180078.100" + wire $not$libresoc.v:180078$10961_Y + attribute \src "libresoc.v:180079.17-180079.103" + wire $not$libresoc.v:180079$10962_Y + attribute \src "libresoc.v:180080.17-180080.103" + wire $not$libresoc.v:180080$10963_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -364098,9 +335468,9 @@ module \reg_1$133 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 9 \dest11__data_i @@ -364114,7 +335484,7 @@ module \reg_1$133 wire width 2 input 13 \dest31__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest31__wen - attribute \src "libresoc.v:178700.7-178700.15" + attribute \src "libresoc.v:180008.7-180008.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 14 \r1__data_o @@ -364157,129 +335527,129 @@ module \reg_1$133 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178769$10976 + cell $not $not$libresoc.v:180077$10960 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:178769$10976_Y + connect \Y $not$libresoc.v:180077$10960_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178770$10977 + cell $not $not$libresoc.v:180078$10961 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:178770$10977_Y + connect \Y $not$libresoc.v:180078$10961_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178771$10978 + cell $not $not$libresoc.v:180079$10962 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:178771$10978_Y + connect \Y $not$libresoc.v:180079$10962_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:178772$10979 + cell $not $not$libresoc.v:180080$10963 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:178772$10979_Y + connect \Y $not$libresoc.v:180080$10963_Y end - attribute \src "libresoc.v:178700.7-178700.20" - process $proc$libresoc.v:178700$11050 + attribute \src "libresoc.v:180008.7-180008.20" + process $proc$libresoc.v:180008$11034 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:178727.13-178727.30" - process $proc$libresoc.v:178727$11051 + attribute \src "libresoc.v:180035.13-180035.30" + process $proc$libresoc.v:180035$11035 assign { } { } assign $1\r1__data_o[1:0] 2'00 sync always sync init update \r1__data_o $1\r1__data_o[1:0] end - attribute \src "libresoc.v:178733.13-178733.25" - process $proc$libresoc.v:178733$11052 + attribute \src "libresoc.v:180041.13-180041.25" + process $proc$libresoc.v:180041$11036 assign { } { } assign $1\reg[1:0] 2'00 sync always sync init update \reg $1\reg[1:0] end - attribute \src "libresoc.v:178738.13-178738.33" - process $proc$libresoc.v:178738$11053 + attribute \src "libresoc.v:180046.13-180046.33" + process $proc$libresoc.v:180046$11037 assign { } { } assign $1\src11__data_o[1:0] 2'00 sync always sync init update \src11__data_o $1\src11__data_o[1:0] end - attribute \src "libresoc.v:178745.13-178745.33" - process $proc$libresoc.v:178745$11054 + attribute \src "libresoc.v:180053.13-180053.33" + process $proc$libresoc.v:180053$11038 assign { } { } assign $1\src21__data_o[1:0] 2'00 sync always sync init update \src21__data_o $1\src21__data_o[1:0] end - attribute \src "libresoc.v:178752.13-178752.33" - process $proc$libresoc.v:178752$11055 + attribute \src "libresoc.v:180060.13-180060.33" + process $proc$libresoc.v:180060$11039 assign { } { } assign $1\src31__data_o[1:0] 2'00 sync always sync init update \src31__data_o $1\src31__data_o[1:0] end - attribute \src "libresoc.v:178773.3-178774.25" - process $proc$libresoc.v:178773$10980 + attribute \src "libresoc.v:180081.3-180082.25" + process $proc$libresoc.v:180081$10964 assign { } { } assign $0\reg[1:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[1:0] end - attribute \src "libresoc.v:178775.3-178776.37" - process $proc$libresoc.v:178775$10981 + attribute \src "libresoc.v:180083.3-180084.37" + process $proc$libresoc.v:180083$10965 assign { } { } assign $0\r1__data_o[1:0] \r1__data_o$next sync posedge \coresync_clk update \r1__data_o $0\r1__data_o[1:0] end - attribute \src "libresoc.v:178777.3-178778.43" - process $proc$libresoc.v:178777$10982 + attribute \src "libresoc.v:180085.3-180086.43" + process $proc$libresoc.v:180085$10966 assign { } { } assign $0\src31__data_o[1:0] \src31__data_o$next sync posedge \coresync_clk update \src31__data_o $0\src31__data_o[1:0] end - attribute \src "libresoc.v:178779.3-178780.43" - process $proc$libresoc.v:178779$10983 + attribute \src "libresoc.v:180087.3-180088.43" + process $proc$libresoc.v:180087$10967 assign { } { } assign $0\src21__data_o[1:0] \src21__data_o$next sync posedge \coresync_clk update \src21__data_o $0\src21__data_o[1:0] end - attribute \src "libresoc.v:178781.3-178782.43" - process $proc$libresoc.v:178781$10984 + attribute \src "libresoc.v:180089.3-180090.43" + process $proc$libresoc.v:180089$10968 assign { } { } assign $0\src11__data_o[1:0] \src11__data_o$next sync posedge \coresync_clk update \src11__data_o $0\src11__data_o[1:0] end - attribute \src "libresoc.v:178783.3-178828.6" - process $proc$libresoc.v:178783$10985 + attribute \src "libresoc.v:180091.3-180136.6" + process $proc$libresoc.v:180091$10969 assign { } { } assign { } { } assign { } { } - assign $0\src11__data_o$next[1:0]$10986 $7\src11__data_o$next[1:0]$10993 - attribute \src "libresoc.v:178784.5-178784.29" + assign $0\src11__data_o$next[1:0]$10970 $7\src11__data_o$next[1:0]$10977 + attribute \src "libresoc.v:180092.5-180092.29" switch \initial - attribute \src "libresoc.v:178784.9-178784.17" + attribute \src "libresoc.v:180092.9-180092.17" case 1'1 case end @@ -364292,75 +335662,75 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\src11__data_o$next[1:0]$10987 $6\src11__data_o$next[1:0]$10992 + assign $1\src11__data_o$next[1:0]$10971 $6\src11__data_o$next[1:0]$10976 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src11__data_o$next[1:0]$10988 \dest11__data_i + assign $2\src11__data_o$next[1:0]$10972 \dest11__data_i case - assign $2\src11__data_o$next[1:0]$10988 2'00 + assign $2\src11__data_o$next[1:0]$10972 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src11__data_o$next[1:0]$10989 \dest21__data_i + assign $3\src11__data_o$next[1:0]$10973 \dest21__data_i case - assign $3\src11__data_o$next[1:0]$10989 $2\src11__data_o$next[1:0]$10988 + assign $3\src11__data_o$next[1:0]$10973 $2\src11__data_o$next[1:0]$10972 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src11__data_o$next[1:0]$10990 \dest31__data_i + assign $4\src11__data_o$next[1:0]$10974 \dest31__data_i case - assign $4\src11__data_o$next[1:0]$10990 $3\src11__data_o$next[1:0]$10989 + assign $4\src11__data_o$next[1:0]$10974 $3\src11__data_o$next[1:0]$10973 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src11__data_o$next[1:0]$10991 \w1__data_i + assign $5\src11__data_o$next[1:0]$10975 \w1__data_i case - assign $5\src11__data_o$next[1:0]$10991 $4\src11__data_o$next[1:0]$10990 + assign $5\src11__data_o$next[1:0]$10975 $4\src11__data_o$next[1:0]$10974 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src11__data_o$next[1:0]$10992 \reg + assign $6\src11__data_o$next[1:0]$10976 \reg case - assign $6\src11__data_o$next[1:0]$10992 $5\src11__data_o$next[1:0]$10991 + assign $6\src11__data_o$next[1:0]$10976 $5\src11__data_o$next[1:0]$10975 end case - assign $1\src11__data_o$next[1:0]$10987 2'00 + assign $1\src11__data_o$next[1:0]$10971 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src11__data_o$next[1:0]$10993 2'00 + assign $7\src11__data_o$next[1:0]$10977 2'00 case - assign $7\src11__data_o$next[1:0]$10993 $1\src11__data_o$next[1:0]$10987 + assign $7\src11__data_o$next[1:0]$10977 $1\src11__data_o$next[1:0]$10971 end sync always - update \src11__data_o$next $0\src11__data_o$next[1:0]$10986 + update \src11__data_o$next $0\src11__data_o$next[1:0]$10970 end - attribute \src "libresoc.v:178829.3-178864.6" - process $proc$libresoc.v:178829$10994 + attribute \src "libresoc.v:180137.3-180172.6" + process $proc$libresoc.v:180137$10978 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:178830.5-178830.29" + attribute \src "libresoc.v:180138.5-180138.29" switch \initial - attribute \src "libresoc.v:178830.9-178830.17" + attribute \src "libresoc.v:180138.9-180138.17" case 1'1 case end @@ -364416,15 +335786,15 @@ module \reg_1$133 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:178865.3-178910.6" - process $proc$libresoc.v:178865$10995 + attribute \src "libresoc.v:180173.3-180218.6" + process $proc$libresoc.v:180173$10979 assign { } { } assign { } { } assign { } { } - assign $0\src21__data_o$next[1:0]$10996 $7\src21__data_o$next[1:0]$11003 - attribute \src "libresoc.v:178866.5-178866.29" + assign $0\src21__data_o$next[1:0]$10980 $7\src21__data_o$next[1:0]$10987 + attribute \src "libresoc.v:180174.5-180174.29" switch \initial - attribute \src "libresoc.v:178866.9-178866.17" + attribute \src "libresoc.v:180174.9-180174.17" case 1'1 case end @@ -364437,75 +335807,75 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\src21__data_o$next[1:0]$10997 $6\src21__data_o$next[1:0]$11002 + assign $1\src21__data_o$next[1:0]$10981 $6\src21__data_o$next[1:0]$10986 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src21__data_o$next[1:0]$10998 \dest11__data_i + assign $2\src21__data_o$next[1:0]$10982 \dest11__data_i case - assign $2\src21__data_o$next[1:0]$10998 2'00 + assign $2\src21__data_o$next[1:0]$10982 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src21__data_o$next[1:0]$10999 \dest21__data_i + assign $3\src21__data_o$next[1:0]$10983 \dest21__data_i case - assign $3\src21__data_o$next[1:0]$10999 $2\src21__data_o$next[1:0]$10998 + assign $3\src21__data_o$next[1:0]$10983 $2\src21__data_o$next[1:0]$10982 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src21__data_o$next[1:0]$11000 \dest31__data_i + assign $4\src21__data_o$next[1:0]$10984 \dest31__data_i case - assign $4\src21__data_o$next[1:0]$11000 $3\src21__data_o$next[1:0]$10999 + assign $4\src21__data_o$next[1:0]$10984 $3\src21__data_o$next[1:0]$10983 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src21__data_o$next[1:0]$11001 \w1__data_i + assign $5\src21__data_o$next[1:0]$10985 \w1__data_i case - assign $5\src21__data_o$next[1:0]$11001 $4\src21__data_o$next[1:0]$11000 + assign $5\src21__data_o$next[1:0]$10985 $4\src21__data_o$next[1:0]$10984 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src21__data_o$next[1:0]$11002 \reg + assign $6\src21__data_o$next[1:0]$10986 \reg case - assign $6\src21__data_o$next[1:0]$11002 $5\src21__data_o$next[1:0]$11001 + assign $6\src21__data_o$next[1:0]$10986 $5\src21__data_o$next[1:0]$10985 end case - assign $1\src21__data_o$next[1:0]$10997 2'00 + assign $1\src21__data_o$next[1:0]$10981 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src21__data_o$next[1:0]$11003 2'00 + assign $7\src21__data_o$next[1:0]$10987 2'00 case - assign $7\src21__data_o$next[1:0]$11003 $1\src21__data_o$next[1:0]$10997 + assign $7\src21__data_o$next[1:0]$10987 $1\src21__data_o$next[1:0]$10981 end sync always - update \src21__data_o$next $0\src21__data_o$next[1:0]$10996 + update \src21__data_o$next $0\src21__data_o$next[1:0]$10980 end - attribute \src "libresoc.v:178911.3-178946.6" - process $proc$libresoc.v:178911$11004 + attribute \src "libresoc.v:180219.3-180254.6" + process $proc$libresoc.v:180219$10988 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11005 $1\wr_detect$4[0:0]$11006 - attribute \src "libresoc.v:178912.5-178912.29" + assign $0\wr_detect$4[0:0]$10989 $1\wr_detect$4[0:0]$10990 + attribute \src "libresoc.v:180220.5-180220.29" switch \initial - attribute \src "libresoc.v:178912.9-178912.17" + attribute \src "libresoc.v:180220.9-180220.17" case 1'1 case end @@ -364518,58 +335888,58 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11006 $5\wr_detect$4[0:0]$11010 + assign $1\wr_detect$4[0:0]$10990 $5\wr_detect$4[0:0]$10994 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11007 1'1 + assign $2\wr_detect$4[0:0]$10991 1'1 case - assign $2\wr_detect$4[0:0]$11007 1'0 + assign $2\wr_detect$4[0:0]$10991 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11008 1'1 + assign $3\wr_detect$4[0:0]$10992 1'1 case - assign $3\wr_detect$4[0:0]$11008 $2\wr_detect$4[0:0]$11007 + assign $3\wr_detect$4[0:0]$10992 $2\wr_detect$4[0:0]$10991 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11009 1'1 + assign $4\wr_detect$4[0:0]$10993 1'1 case - assign $4\wr_detect$4[0:0]$11009 $3\wr_detect$4[0:0]$11008 + assign $4\wr_detect$4[0:0]$10993 $3\wr_detect$4[0:0]$10992 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$11010 1'1 + assign $5\wr_detect$4[0:0]$10994 1'1 case - assign $5\wr_detect$4[0:0]$11010 $4\wr_detect$4[0:0]$11009 + assign $5\wr_detect$4[0:0]$10994 $4\wr_detect$4[0:0]$10993 end case - assign $1\wr_detect$4[0:0]$11006 1'0 + assign $1\wr_detect$4[0:0]$10990 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11005 + update \wr_detect$4 $0\wr_detect$4[0:0]$10989 end - attribute \src "libresoc.v:178947.3-178992.6" - process $proc$libresoc.v:178947$11011 + attribute \src "libresoc.v:180255.3-180300.6" + process $proc$libresoc.v:180255$10995 assign { } { } assign { } { } assign { } { } - assign $0\src31__data_o$next[1:0]$11012 $7\src31__data_o$next[1:0]$11019 - attribute \src "libresoc.v:178948.5-178948.29" + assign $0\src31__data_o$next[1:0]$10996 $7\src31__data_o$next[1:0]$11003 + attribute \src "libresoc.v:180256.5-180256.29" switch \initial - attribute \src "libresoc.v:178948.9-178948.17" + attribute \src "libresoc.v:180256.9-180256.17" case 1'1 case end @@ -364582,75 +335952,75 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\src31__data_o$next[1:0]$11013 $6\src31__data_o$next[1:0]$11018 + assign $1\src31__data_o$next[1:0]$10997 $6\src31__data_o$next[1:0]$11002 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src31__data_o$next[1:0]$11014 \dest11__data_i + assign $2\src31__data_o$next[1:0]$10998 \dest11__data_i case - assign $2\src31__data_o$next[1:0]$11014 2'00 + assign $2\src31__data_o$next[1:0]$10998 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src31__data_o$next[1:0]$11015 \dest21__data_i + assign $3\src31__data_o$next[1:0]$10999 \dest21__data_i case - assign $3\src31__data_o$next[1:0]$11015 $2\src31__data_o$next[1:0]$11014 + assign $3\src31__data_o$next[1:0]$10999 $2\src31__data_o$next[1:0]$10998 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src31__data_o$next[1:0]$11016 \dest31__data_i + assign $4\src31__data_o$next[1:0]$11000 \dest31__data_i case - assign $4\src31__data_o$next[1:0]$11016 $3\src31__data_o$next[1:0]$11015 + assign $4\src31__data_o$next[1:0]$11000 $3\src31__data_o$next[1:0]$10999 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src31__data_o$next[1:0]$11017 \w1__data_i + assign $5\src31__data_o$next[1:0]$11001 \w1__data_i case - assign $5\src31__data_o$next[1:0]$11017 $4\src31__data_o$next[1:0]$11016 + assign $5\src31__data_o$next[1:0]$11001 $4\src31__data_o$next[1:0]$11000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src31__data_o$next[1:0]$11018 \reg + assign $6\src31__data_o$next[1:0]$11002 \reg case - assign $6\src31__data_o$next[1:0]$11018 $5\src31__data_o$next[1:0]$11017 + assign $6\src31__data_o$next[1:0]$11002 $5\src31__data_o$next[1:0]$11001 end case - assign $1\src31__data_o$next[1:0]$11013 2'00 + assign $1\src31__data_o$next[1:0]$10997 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src31__data_o$next[1:0]$11019 2'00 + assign $7\src31__data_o$next[1:0]$11003 2'00 case - assign $7\src31__data_o$next[1:0]$11019 $1\src31__data_o$next[1:0]$11013 + assign $7\src31__data_o$next[1:0]$11003 $1\src31__data_o$next[1:0]$10997 end sync always - update \src31__data_o$next $0\src31__data_o$next[1:0]$11012 + update \src31__data_o$next $0\src31__data_o$next[1:0]$10996 end - attribute \src "libresoc.v:178993.3-179028.6" - process $proc$libresoc.v:178993$11020 + attribute \src "libresoc.v:180301.3-180336.6" + process $proc$libresoc.v:180301$11004 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11021 $1\wr_detect$7[0:0]$11022 - attribute \src "libresoc.v:178994.5-178994.29" + assign $0\wr_detect$7[0:0]$11005 $1\wr_detect$7[0:0]$11006 + attribute \src "libresoc.v:180302.5-180302.29" switch \initial - attribute \src "libresoc.v:178994.9-178994.17" + attribute \src "libresoc.v:180302.9-180302.17" case 1'1 case end @@ -364663,58 +336033,58 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11022 $5\wr_detect$7[0:0]$11026 + assign $1\wr_detect$7[0:0]$11006 $5\wr_detect$7[0:0]$11010 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11023 1'1 + assign $2\wr_detect$7[0:0]$11007 1'1 case - assign $2\wr_detect$7[0:0]$11023 1'0 + assign $2\wr_detect$7[0:0]$11007 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11024 1'1 + assign $3\wr_detect$7[0:0]$11008 1'1 case - assign $3\wr_detect$7[0:0]$11024 $2\wr_detect$7[0:0]$11023 + assign $3\wr_detect$7[0:0]$11008 $2\wr_detect$7[0:0]$11007 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11025 1'1 + assign $4\wr_detect$7[0:0]$11009 1'1 case - assign $4\wr_detect$7[0:0]$11025 $3\wr_detect$7[0:0]$11024 + assign $4\wr_detect$7[0:0]$11009 $3\wr_detect$7[0:0]$11008 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$11026 1'1 + assign $5\wr_detect$7[0:0]$11010 1'1 case - assign $5\wr_detect$7[0:0]$11026 $4\wr_detect$7[0:0]$11025 + assign $5\wr_detect$7[0:0]$11010 $4\wr_detect$7[0:0]$11009 end case - assign $1\wr_detect$7[0:0]$11022 1'0 + assign $1\wr_detect$7[0:0]$11006 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11021 + update \wr_detect$7 $0\wr_detect$7[0:0]$11005 end - attribute \src "libresoc.v:179029.3-179074.6" - process $proc$libresoc.v:179029$11027 + attribute \src "libresoc.v:180337.3-180382.6" + process $proc$libresoc.v:180337$11011 assign { } { } assign { } { } assign { } { } - assign $0\r1__data_o$next[1:0]$11028 $7\r1__data_o$next[1:0]$11035 - attribute \src "libresoc.v:179030.5-179030.29" + assign $0\r1__data_o$next[1:0]$11012 $7\r1__data_o$next[1:0]$11019 + attribute \src "libresoc.v:180338.5-180338.29" switch \initial - attribute \src "libresoc.v:179030.9-179030.17" + attribute \src "libresoc.v:180338.9-180338.17" case 1'1 case end @@ -364727,75 +336097,75 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\r1__data_o$next[1:0]$11029 $6\r1__data_o$next[1:0]$11034 + assign $1\r1__data_o$next[1:0]$11013 $6\r1__data_o$next[1:0]$11018 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r1__data_o$next[1:0]$11030 \dest11__data_i + assign $2\r1__data_o$next[1:0]$11014 \dest11__data_i case - assign $2\r1__data_o$next[1:0]$11030 2'00 + assign $2\r1__data_o$next[1:0]$11014 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r1__data_o$next[1:0]$11031 \dest21__data_i + assign $3\r1__data_o$next[1:0]$11015 \dest21__data_i case - assign $3\r1__data_o$next[1:0]$11031 $2\r1__data_o$next[1:0]$11030 + assign $3\r1__data_o$next[1:0]$11015 $2\r1__data_o$next[1:0]$11014 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r1__data_o$next[1:0]$11032 \dest31__data_i + assign $4\r1__data_o$next[1:0]$11016 \dest31__data_i case - assign $4\r1__data_o$next[1:0]$11032 $3\r1__data_o$next[1:0]$11031 + assign $4\r1__data_o$next[1:0]$11016 $3\r1__data_o$next[1:0]$11015 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r1__data_o$next[1:0]$11033 \w1__data_i + assign $5\r1__data_o$next[1:0]$11017 \w1__data_i case - assign $5\r1__data_o$next[1:0]$11033 $4\r1__data_o$next[1:0]$11032 + assign $5\r1__data_o$next[1:0]$11017 $4\r1__data_o$next[1:0]$11016 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r1__data_o$next[1:0]$11034 \reg + assign $6\r1__data_o$next[1:0]$11018 \reg case - assign $6\r1__data_o$next[1:0]$11034 $5\r1__data_o$next[1:0]$11033 + assign $6\r1__data_o$next[1:0]$11018 $5\r1__data_o$next[1:0]$11017 end case - assign $1\r1__data_o$next[1:0]$11029 2'00 + assign $1\r1__data_o$next[1:0]$11013 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\r1__data_o$next[1:0]$11035 2'00 + assign $7\r1__data_o$next[1:0]$11019 2'00 case - assign $7\r1__data_o$next[1:0]$11035 $1\r1__data_o$next[1:0]$11029 + assign $7\r1__data_o$next[1:0]$11019 $1\r1__data_o$next[1:0]$11013 end sync always - update \r1__data_o$next $0\r1__data_o$next[1:0]$11028 + update \r1__data_o$next $0\r1__data_o$next[1:0]$11012 end - attribute \src "libresoc.v:179075.3-179110.6" - process $proc$libresoc.v:179075$11036 + attribute \src "libresoc.v:180383.3-180418.6" + process $proc$libresoc.v:180383$11020 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11037 $1\wr_detect$10[0:0]$11038 - attribute \src "libresoc.v:179076.5-179076.29" + assign $0\wr_detect$10[0:0]$11021 $1\wr_detect$10[0:0]$11022 + attribute \src "libresoc.v:180384.5-180384.29" switch \initial - attribute \src "libresoc.v:179076.9-179076.17" + attribute \src "libresoc.v:180384.9-180384.17" case 1'1 case end @@ -364808,61 +336178,61 @@ module \reg_1$133 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11038 $5\wr_detect$10[0:0]$11042 + assign $1\wr_detect$10[0:0]$11022 $5\wr_detect$10[0:0]$11026 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11039 1'1 + assign $2\wr_detect$10[0:0]$11023 1'1 case - assign $2\wr_detect$10[0:0]$11039 1'0 + assign $2\wr_detect$10[0:0]$11023 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11040 1'1 + assign $3\wr_detect$10[0:0]$11024 1'1 case - assign $3\wr_detect$10[0:0]$11040 $2\wr_detect$10[0:0]$11039 + assign $3\wr_detect$10[0:0]$11024 $2\wr_detect$10[0:0]$11023 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11041 1'1 + assign $4\wr_detect$10[0:0]$11025 1'1 case - assign $4\wr_detect$10[0:0]$11041 $3\wr_detect$10[0:0]$11040 + assign $4\wr_detect$10[0:0]$11025 $3\wr_detect$10[0:0]$11024 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$10[0:0]$11042 1'1 + assign $5\wr_detect$10[0:0]$11026 1'1 case - assign $5\wr_detect$10[0:0]$11042 $4\wr_detect$10[0:0]$11041 + assign $5\wr_detect$10[0:0]$11026 $4\wr_detect$10[0:0]$11025 end case - assign $1\wr_detect$10[0:0]$11038 1'0 + assign $1\wr_detect$10[0:0]$11022 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11037 + update \wr_detect$10 $0\wr_detect$10[0:0]$11021 end - attribute \src "libresoc.v:179111.3-179143.6" - process $proc$libresoc.v:179111$11043 + attribute \src "libresoc.v:180419.3-180451.6" + process $proc$libresoc.v:180419$11027 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[1:0]$11044 $5\reg$next[1:0]$11049 - attribute \src "libresoc.v:179112.5-179112.29" + assign $0\reg$next[1:0]$11028 $5\reg$next[1:0]$11033 + attribute \src "libresoc.v:180420.5-180420.29" switch \initial - attribute \src "libresoc.v:179112.9-179112.17" + attribute \src "libresoc.v:180420.9-180420.17" case 1'1 case end @@ -364871,179 +336241,179 @@ module \reg_1$133 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[1:0]$11045 \dest11__data_i + assign $1\reg$next[1:0]$11029 \dest11__data_i case - assign $1\reg$next[1:0]$11045 \reg + assign $1\reg$next[1:0]$11029 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest21__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[1:0]$11046 \dest21__data_i + assign $2\reg$next[1:0]$11030 \dest21__data_i case - assign $2\reg$next[1:0]$11046 $1\reg$next[1:0]$11045 + assign $2\reg$next[1:0]$11030 $1\reg$next[1:0]$11029 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest31__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[1:0]$11047 \dest31__data_i + assign $3\reg$next[1:0]$11031 \dest31__data_i case - assign $3\reg$next[1:0]$11047 $2\reg$next[1:0]$11046 + assign $3\reg$next[1:0]$11031 $2\reg$next[1:0]$11030 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[1:0]$11048 \w1__data_i + assign $4\reg$next[1:0]$11032 \w1__data_i case - assign $4\reg$next[1:0]$11048 $3\reg$next[1:0]$11047 + assign $4\reg$next[1:0]$11032 $3\reg$next[1:0]$11031 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[1:0]$11049 2'00 + assign $5\reg$next[1:0]$11033 2'00 case - assign $5\reg$next[1:0]$11049 $4\reg$next[1:0]$11048 + assign $5\reg$next[1:0]$11033 $4\reg$next[1:0]$11032 end sync always - update \reg$next $0\reg$next[1:0]$11044 + update \reg$next $0\reg$next[1:0]$11028 end - connect \$9 $not$libresoc.v:178769$10976_Y - connect \$1 $not$libresoc.v:178770$10977_Y - connect \$3 $not$libresoc.v:178771$10978_Y - connect \$6 $not$libresoc.v:178772$10979_Y + connect \$9 $not$libresoc.v:180077$10960_Y + connect \$1 $not$libresoc.v:180078$10961_Y + connect \$3 $not$libresoc.v:180079$10962_Y + connect \$6 $not$libresoc.v:180080$10963_Y end -attribute \src "libresoc.v:179148.1-179497.10" +attribute \src "libresoc.v:180456.1-180805.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_1" attribute \generator "nMigen" module \reg_1$136 - attribute \src "libresoc.v:179218.3-179263.6" - wire width 64 $0\cia1__data_o$next[63:0]$11064 - attribute \src "libresoc.v:179216.3-179217.41" + attribute \src "libresoc.v:180526.3-180571.6" + wire width 64 $0\cia1__data_o$next[63:0]$11048 + attribute \src "libresoc.v:180524.3-180525.41" wire width 64 $0\cia1__data_o[63:0] - attribute \src "libresoc.v:179149.7-179149.20" + attribute \src "libresoc.v:180457.7-180457.20" wire $0\initial[0:0] - attribute \src "libresoc.v:179300.3-179345.6" - wire width 64 $0\msr1__data_o$next[63:0]$11074 - attribute \src "libresoc.v:179214.3-179215.41" + attribute \src "libresoc.v:180608.3-180653.6" + wire width 64 $0\msr1__data_o$next[63:0]$11058 + attribute \src "libresoc.v:180522.3-180523.41" wire width 64 $0\msr1__data_o[63:0] - attribute \src "libresoc.v:179464.3-179496.6" - wire width 64 $0\reg$next[63:0]$11106 - attribute \src "libresoc.v:179210.3-179211.25" + attribute \src "libresoc.v:180772.3-180804.6" + wire width 64 $0\reg$next[63:0]$11090 + attribute \src "libresoc.v:180518.3-180519.25" wire width 64 $0\reg[63:0] - attribute \src "libresoc.v:179382.3-179427.6" - wire width 64 $0\sv1__data_o$next[63:0]$11090 - attribute \src "libresoc.v:179212.3-179213.39" + attribute \src "libresoc.v:180690.3-180735.6" + wire width 64 $0\sv1__data_o$next[63:0]$11074 + attribute \src "libresoc.v:180520.3-180521.39" wire width 64 $0\sv1__data_o[63:0] - attribute \src "libresoc.v:179346.3-179381.6" - wire $0\wr_detect$4[0:0]$11083 - attribute \src "libresoc.v:179428.3-179463.6" - wire $0\wr_detect$7[0:0]$11099 - attribute \src "libresoc.v:179264.3-179299.6" + attribute \src "libresoc.v:180654.3-180689.6" + wire $0\wr_detect$4[0:0]$11067 + attribute \src "libresoc.v:180736.3-180771.6" + wire $0\wr_detect$7[0:0]$11083 + attribute \src "libresoc.v:180572.3-180607.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:179218.3-179263.6" - wire width 64 $1\cia1__data_o$next[63:0]$11065 - attribute \src "libresoc.v:179158.14-179158.49" + attribute \src "libresoc.v:180526.3-180571.6" + wire width 64 $1\cia1__data_o$next[63:0]$11049 + attribute \src "libresoc.v:180466.14-180466.49" wire width 64 $1\cia1__data_o[63:0] - attribute \src "libresoc.v:179300.3-179345.6" - wire width 64 $1\msr1__data_o$next[63:0]$11075 - attribute \src "libresoc.v:179175.14-179175.49" + attribute \src "libresoc.v:180608.3-180653.6" + wire width 64 $1\msr1__data_o$next[63:0]$11059 + attribute \src "libresoc.v:180483.14-180483.49" wire width 64 $1\msr1__data_o[63:0] - attribute \src "libresoc.v:179464.3-179496.6" - wire width 64 $1\reg$next[63:0]$11107 - attribute \src "libresoc.v:179187.14-179187.42" + attribute \src "libresoc.v:180772.3-180804.6" + wire width 64 $1\reg$next[63:0]$11091 + attribute \src "libresoc.v:180495.14-180495.42" wire width 64 $1\reg[63:0] - attribute \src "libresoc.v:179382.3-179427.6" - wire width 64 $1\sv1__data_o$next[63:0]$11091 - attribute \src "libresoc.v:179194.14-179194.48" + attribute \src "libresoc.v:180690.3-180735.6" + wire width 64 $1\sv1__data_o$next[63:0]$11075 + attribute \src "libresoc.v:180502.14-180502.48" wire width 64 $1\sv1__data_o[63:0] - attribute \src "libresoc.v:179346.3-179381.6" - wire $1\wr_detect$4[0:0]$11084 - attribute \src "libresoc.v:179428.3-179463.6" - wire $1\wr_detect$7[0:0]$11100 - attribute \src "libresoc.v:179264.3-179299.6" + attribute \src "libresoc.v:180654.3-180689.6" + wire $1\wr_detect$4[0:0]$11068 + attribute \src "libresoc.v:180736.3-180771.6" + wire $1\wr_detect$7[0:0]$11084 + attribute \src "libresoc.v:180572.3-180607.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:179218.3-179263.6" - wire width 64 $2\cia1__data_o$next[63:0]$11066 - attribute \src "libresoc.v:179300.3-179345.6" - wire width 64 $2\msr1__data_o$next[63:0]$11076 - attribute \src "libresoc.v:179464.3-179496.6" - wire width 64 $2\reg$next[63:0]$11108 - attribute \src "libresoc.v:179382.3-179427.6" - wire width 64 $2\sv1__data_o$next[63:0]$11092 - attribute \src "libresoc.v:179346.3-179381.6" - wire $2\wr_detect$4[0:0]$11085 - attribute \src "libresoc.v:179428.3-179463.6" - wire $2\wr_detect$7[0:0]$11101 - attribute \src "libresoc.v:179264.3-179299.6" + attribute \src "libresoc.v:180526.3-180571.6" + wire width 64 $2\cia1__data_o$next[63:0]$11050 + attribute \src "libresoc.v:180608.3-180653.6" + wire width 64 $2\msr1__data_o$next[63:0]$11060 + attribute \src "libresoc.v:180772.3-180804.6" + wire width 64 $2\reg$next[63:0]$11092 + attribute \src "libresoc.v:180690.3-180735.6" + wire width 64 $2\sv1__data_o$next[63:0]$11076 + attribute \src "libresoc.v:180654.3-180689.6" + wire $2\wr_detect$4[0:0]$11069 + attribute \src "libresoc.v:180736.3-180771.6" + wire $2\wr_detect$7[0:0]$11085 + attribute \src "libresoc.v:180572.3-180607.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:179218.3-179263.6" - wire width 64 $3\cia1__data_o$next[63:0]$11067 - attribute \src "libresoc.v:179300.3-179345.6" - wire width 64 $3\msr1__data_o$next[63:0]$11077 - attribute \src "libresoc.v:179464.3-179496.6" - wire width 64 $3\reg$next[63:0]$11109 - attribute \src "libresoc.v:179382.3-179427.6" - wire width 64 $3\sv1__data_o$next[63:0]$11093 - attribute \src "libresoc.v:179346.3-179381.6" - wire $3\wr_detect$4[0:0]$11086 - attribute \src "libresoc.v:179428.3-179463.6" - wire $3\wr_detect$7[0:0]$11102 - attribute \src "libresoc.v:179264.3-179299.6" + attribute \src "libresoc.v:180526.3-180571.6" + wire width 64 $3\cia1__data_o$next[63:0]$11051 + attribute \src "libresoc.v:180608.3-180653.6" + wire width 64 $3\msr1__data_o$next[63:0]$11061 + attribute \src "libresoc.v:180772.3-180804.6" + wire width 64 $3\reg$next[63:0]$11093 + attribute \src "libresoc.v:180690.3-180735.6" + wire width 64 $3\sv1__data_o$next[63:0]$11077 + attribute \src "libresoc.v:180654.3-180689.6" + wire $3\wr_detect$4[0:0]$11070 + attribute \src "libresoc.v:180736.3-180771.6" + wire $3\wr_detect$7[0:0]$11086 + attribute \src "libresoc.v:180572.3-180607.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:179218.3-179263.6" - wire width 64 $4\cia1__data_o$next[63:0]$11068 - attribute \src "libresoc.v:179300.3-179345.6" - wire width 64 $4\msr1__data_o$next[63:0]$11078 - attribute \src "libresoc.v:179464.3-179496.6" - wire width 64 $4\reg$next[63:0]$11110 - attribute \src "libresoc.v:179382.3-179427.6" - wire width 64 $4\sv1__data_o$next[63:0]$11094 - attribute \src "libresoc.v:179346.3-179381.6" - wire $4\wr_detect$4[0:0]$11087 - attribute \src "libresoc.v:179428.3-179463.6" - wire $4\wr_detect$7[0:0]$11103 - attribute \src "libresoc.v:179264.3-179299.6" + attribute \src "libresoc.v:180526.3-180571.6" + wire width 64 $4\cia1__data_o$next[63:0]$11052 + attribute \src "libresoc.v:180608.3-180653.6" + wire width 64 $4\msr1__data_o$next[63:0]$11062 + attribute \src "libresoc.v:180772.3-180804.6" + wire width 64 $4\reg$next[63:0]$11094 + attribute \src "libresoc.v:180690.3-180735.6" + wire width 64 $4\sv1__data_o$next[63:0]$11078 + attribute \src "libresoc.v:180654.3-180689.6" + wire $4\wr_detect$4[0:0]$11071 + attribute \src "libresoc.v:180736.3-180771.6" + wire $4\wr_detect$7[0:0]$11087 + attribute \src "libresoc.v:180572.3-180607.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:179218.3-179263.6" - wire width 64 $5\cia1__data_o$next[63:0]$11069 - attribute \src "libresoc.v:179300.3-179345.6" - wire width 64 $5\msr1__data_o$next[63:0]$11079 - attribute \src "libresoc.v:179464.3-179496.6" - wire width 64 $5\reg$next[63:0]$11111 - attribute \src "libresoc.v:179382.3-179427.6" - wire width 64 $5\sv1__data_o$next[63:0]$11095 - attribute \src "libresoc.v:179346.3-179381.6" - wire $5\wr_detect$4[0:0]$11088 - attribute \src "libresoc.v:179428.3-179463.6" - wire $5\wr_detect$7[0:0]$11104 - attribute \src "libresoc.v:179264.3-179299.6" + attribute \src "libresoc.v:180526.3-180571.6" + wire width 64 $5\cia1__data_o$next[63:0]$11053 + attribute \src "libresoc.v:180608.3-180653.6" + wire width 64 $5\msr1__data_o$next[63:0]$11063 + attribute \src "libresoc.v:180772.3-180804.6" + wire width 64 $5\reg$next[63:0]$11095 + attribute \src "libresoc.v:180690.3-180735.6" + wire width 64 $5\sv1__data_o$next[63:0]$11079 + attribute \src "libresoc.v:180654.3-180689.6" + wire $5\wr_detect$4[0:0]$11072 + attribute \src "libresoc.v:180736.3-180771.6" + wire $5\wr_detect$7[0:0]$11088 + attribute \src "libresoc.v:180572.3-180607.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:179218.3-179263.6" - wire width 64 $6\cia1__data_o$next[63:0]$11070 - attribute \src "libresoc.v:179300.3-179345.6" - wire width 64 $6\msr1__data_o$next[63:0]$11080 - attribute \src "libresoc.v:179382.3-179427.6" - wire width 64 $6\sv1__data_o$next[63:0]$11096 - attribute \src "libresoc.v:179218.3-179263.6" - wire width 64 $7\cia1__data_o$next[63:0]$11071 - attribute \src "libresoc.v:179300.3-179345.6" - wire width 64 $7\msr1__data_o$next[63:0]$11081 - attribute \src "libresoc.v:179382.3-179427.6" - wire width 64 $7\sv1__data_o$next[63:0]$11097 - attribute \src "libresoc.v:179207.17-179207.100" - wire $not$libresoc.v:179207$11056_Y - attribute \src "libresoc.v:179208.17-179208.103" - wire $not$libresoc.v:179208$11057_Y - attribute \src "libresoc.v:179209.17-179209.103" - wire $not$libresoc.v:179209$11058_Y + attribute \src "libresoc.v:180526.3-180571.6" + wire width 64 $6\cia1__data_o$next[63:0]$11054 + attribute \src "libresoc.v:180608.3-180653.6" + wire width 64 $6\msr1__data_o$next[63:0]$11064 + attribute \src "libresoc.v:180690.3-180735.6" + wire width 64 $6\sv1__data_o$next[63:0]$11080 + attribute \src "libresoc.v:180526.3-180571.6" + wire width 64 $7\cia1__data_o$next[63:0]$11055 + attribute \src "libresoc.v:180608.3-180653.6" + wire width 64 $7\msr1__data_o$next[63:0]$11065 + attribute \src "libresoc.v:180690.3-180735.6" + wire width 64 $7\sv1__data_o$next[63:0]$11081 + attribute \src "libresoc.v:180515.17-180515.100" + wire $not$libresoc.v:180515$11040_Y + attribute \src "libresoc.v:180516.17-180516.103" + wire $not$libresoc.v:180516$11041_Y + attribute \src "libresoc.v:180517.17-180517.103" + wire $not$libresoc.v:180517$11042_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -365056,15 +336426,15 @@ module \reg_1$136 wire width 64 \cia1__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \cia1__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 15 \d_wr11__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 14 \d_wr11__wen - attribute \src "libresoc.v:179149.7-179149.15" + attribute \src "libresoc.v:180457.7-180457.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 11 \msr1__data_i @@ -365101,106 +336471,106 @@ module \reg_1$136 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179207$11056 + cell $not $not$libresoc.v:180515$11040 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:179207$11056_Y + connect \Y $not$libresoc.v:180515$11040_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179208$11057 + cell $not $not$libresoc.v:180516$11041 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:179208$11057_Y + connect \Y $not$libresoc.v:180516$11041_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179209$11058 + cell $not $not$libresoc.v:180517$11042 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:179209$11058_Y + connect \Y $not$libresoc.v:180517$11042_Y end - attribute \src "libresoc.v:179149.7-179149.20" - process $proc$libresoc.v:179149$11112 + attribute \src "libresoc.v:180457.7-180457.20" + process $proc$libresoc.v:180457$11096 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:179158.14-179158.49" - process $proc$libresoc.v:179158$11113 + attribute \src "libresoc.v:180466.14-180466.49" + process $proc$libresoc.v:180466$11097 assign { } { } assign $1\cia1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \cia1__data_o $1\cia1__data_o[63:0] end - attribute \src "libresoc.v:179175.14-179175.49" - process $proc$libresoc.v:179175$11114 + attribute \src "libresoc.v:180483.14-180483.49" + process $proc$libresoc.v:180483$11098 assign { } { } assign $1\msr1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \msr1__data_o $1\msr1__data_o[63:0] end - attribute \src "libresoc.v:179187.14-179187.42" - process $proc$libresoc.v:179187$11115 + attribute \src "libresoc.v:180495.14-180495.42" + process $proc$libresoc.v:180495$11099 assign { } { } assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \reg $1\reg[63:0] end - attribute \src "libresoc.v:179194.14-179194.48" - process $proc$libresoc.v:179194$11116 + attribute \src "libresoc.v:180502.14-180502.48" + process $proc$libresoc.v:180502$11100 assign { } { } assign $1\sv1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \sv1__data_o $1\sv1__data_o[63:0] end - attribute \src "libresoc.v:179210.3-179211.25" - process $proc$libresoc.v:179210$11059 + attribute \src "libresoc.v:180518.3-180519.25" + process $proc$libresoc.v:180518$11043 assign { } { } assign $0\reg[63:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[63:0] end - attribute \src "libresoc.v:179212.3-179213.39" - process $proc$libresoc.v:179212$11060 + attribute \src "libresoc.v:180520.3-180521.39" + process $proc$libresoc.v:180520$11044 assign { } { } assign $0\sv1__data_o[63:0] \sv1__data_o$next sync posedge \coresync_clk update \sv1__data_o $0\sv1__data_o[63:0] end - attribute \src "libresoc.v:179214.3-179215.41" - process $proc$libresoc.v:179214$11061 + attribute \src "libresoc.v:180522.3-180523.41" + process $proc$libresoc.v:180522$11045 assign { } { } assign $0\msr1__data_o[63:0] \msr1__data_o$next sync posedge \coresync_clk update \msr1__data_o $0\msr1__data_o[63:0] end - attribute \src "libresoc.v:179216.3-179217.41" - process $proc$libresoc.v:179216$11062 + attribute \src "libresoc.v:180524.3-180525.41" + process $proc$libresoc.v:180524$11046 assign { } { } assign $0\cia1__data_o[63:0] \cia1__data_o$next sync posedge \coresync_clk update \cia1__data_o $0\cia1__data_o[63:0] end - attribute \src "libresoc.v:179218.3-179263.6" - process $proc$libresoc.v:179218$11063 + attribute \src "libresoc.v:180526.3-180571.6" + process $proc$libresoc.v:180526$11047 assign { } { } assign { } { } assign { } { } - assign $0\cia1__data_o$next[63:0]$11064 $7\cia1__data_o$next[63:0]$11071 - attribute \src "libresoc.v:179219.5-179219.29" + assign $0\cia1__data_o$next[63:0]$11048 $7\cia1__data_o$next[63:0]$11055 + attribute \src "libresoc.v:180527.5-180527.29" switch \initial - attribute \src "libresoc.v:179219.9-179219.17" + attribute \src "libresoc.v:180527.9-180527.17" case 1'1 case end @@ -365213,75 +336583,75 @@ module \reg_1$136 assign { } { } assign { } { } assign { } { } - assign $1\cia1__data_o$next[63:0]$11065 $6\cia1__data_o$next[63:0]$11070 + assign $1\cia1__data_o$next[63:0]$11049 $6\cia1__data_o$next[63:0]$11054 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cia1__data_o$next[63:0]$11066 \nia1__data_i + assign $2\cia1__data_o$next[63:0]$11050 \nia1__data_i case - assign $2\cia1__data_o$next[63:0]$11066 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\cia1__data_o$next[63:0]$11050 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\cia1__data_o$next[63:0]$11067 \msr1__data_i + assign $3\cia1__data_o$next[63:0]$11051 \msr1__data_i case - assign $3\cia1__data_o$next[63:0]$11067 $2\cia1__data_o$next[63:0]$11066 + assign $3\cia1__data_o$next[63:0]$11051 $2\cia1__data_o$next[63:0]$11050 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cia1__data_o$next[63:0]$11068 \sv1__data_i + assign $4\cia1__data_o$next[63:0]$11052 \sv1__data_i case - assign $4\cia1__data_o$next[63:0]$11068 $3\cia1__data_o$next[63:0]$11067 + assign $4\cia1__data_o$next[63:0]$11052 $3\cia1__data_o$next[63:0]$11051 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\cia1__data_o$next[63:0]$11069 \d_wr11__data_i + assign $5\cia1__data_o$next[63:0]$11053 \d_wr11__data_i case - assign $5\cia1__data_o$next[63:0]$11069 $4\cia1__data_o$next[63:0]$11068 + assign $5\cia1__data_o$next[63:0]$11053 $4\cia1__data_o$next[63:0]$11052 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cia1__data_o$next[63:0]$11070 \reg + assign $6\cia1__data_o$next[63:0]$11054 \reg case - assign $6\cia1__data_o$next[63:0]$11070 $5\cia1__data_o$next[63:0]$11069 + assign $6\cia1__data_o$next[63:0]$11054 $5\cia1__data_o$next[63:0]$11053 end case - assign $1\cia1__data_o$next[63:0]$11065 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\cia1__data_o$next[63:0]$11049 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\cia1__data_o$next[63:0]$11071 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\cia1__data_o$next[63:0]$11055 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\cia1__data_o$next[63:0]$11071 $1\cia1__data_o$next[63:0]$11065 + assign $7\cia1__data_o$next[63:0]$11055 $1\cia1__data_o$next[63:0]$11049 end sync always - update \cia1__data_o$next $0\cia1__data_o$next[63:0]$11064 + update \cia1__data_o$next $0\cia1__data_o$next[63:0]$11048 end - attribute \src "libresoc.v:179264.3-179299.6" - process $proc$libresoc.v:179264$11072 + attribute \src "libresoc.v:180572.3-180607.6" + process $proc$libresoc.v:180572$11056 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:179265.5-179265.29" + attribute \src "libresoc.v:180573.5-180573.29" switch \initial - attribute \src "libresoc.v:179265.9-179265.17" + attribute \src "libresoc.v:180573.9-180573.17" case 1'1 case end @@ -365337,15 +336707,15 @@ module \reg_1$136 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:179300.3-179345.6" - process $proc$libresoc.v:179300$11073 + attribute \src "libresoc.v:180608.3-180653.6" + process $proc$libresoc.v:180608$11057 assign { } { } assign { } { } assign { } { } - assign $0\msr1__data_o$next[63:0]$11074 $7\msr1__data_o$next[63:0]$11081 - attribute \src "libresoc.v:179301.5-179301.29" + assign $0\msr1__data_o$next[63:0]$11058 $7\msr1__data_o$next[63:0]$11065 + attribute \src "libresoc.v:180609.5-180609.29" switch \initial - attribute \src "libresoc.v:179301.9-179301.17" + attribute \src "libresoc.v:180609.9-180609.17" case 1'1 case end @@ -365358,75 +336728,75 @@ module \reg_1$136 assign { } { } assign { } { } assign { } { } - assign $1\msr1__data_o$next[63:0]$11075 $6\msr1__data_o$next[63:0]$11080 + assign $1\msr1__data_o$next[63:0]$11059 $6\msr1__data_o$next[63:0]$11064 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr1__data_o$next[63:0]$11076 \nia1__data_i + assign $2\msr1__data_o$next[63:0]$11060 \nia1__data_i case - assign $2\msr1__data_o$next[63:0]$11076 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\msr1__data_o$next[63:0]$11060 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\msr1__data_o$next[63:0]$11077 \msr1__data_i + assign $3\msr1__data_o$next[63:0]$11061 \msr1__data_i case - assign $3\msr1__data_o$next[63:0]$11077 $2\msr1__data_o$next[63:0]$11076 + assign $3\msr1__data_o$next[63:0]$11061 $2\msr1__data_o$next[63:0]$11060 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\msr1__data_o$next[63:0]$11078 \sv1__data_i + assign $4\msr1__data_o$next[63:0]$11062 \sv1__data_i case - assign $4\msr1__data_o$next[63:0]$11078 $3\msr1__data_o$next[63:0]$11077 + assign $4\msr1__data_o$next[63:0]$11062 $3\msr1__data_o$next[63:0]$11061 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\msr1__data_o$next[63:0]$11079 \d_wr11__data_i + assign $5\msr1__data_o$next[63:0]$11063 \d_wr11__data_i case - assign $5\msr1__data_o$next[63:0]$11079 $4\msr1__data_o$next[63:0]$11078 + assign $5\msr1__data_o$next[63:0]$11063 $4\msr1__data_o$next[63:0]$11062 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\msr1__data_o$next[63:0]$11080 \reg + assign $6\msr1__data_o$next[63:0]$11064 \reg case - assign $6\msr1__data_o$next[63:0]$11080 $5\msr1__data_o$next[63:0]$11079 + assign $6\msr1__data_o$next[63:0]$11064 $5\msr1__data_o$next[63:0]$11063 end case - assign $1\msr1__data_o$next[63:0]$11075 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\msr1__data_o$next[63:0]$11059 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\msr1__data_o$next[63:0]$11081 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\msr1__data_o$next[63:0]$11065 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\msr1__data_o$next[63:0]$11081 $1\msr1__data_o$next[63:0]$11075 + assign $7\msr1__data_o$next[63:0]$11065 $1\msr1__data_o$next[63:0]$11059 end sync always - update \msr1__data_o$next $0\msr1__data_o$next[63:0]$11074 + update \msr1__data_o$next $0\msr1__data_o$next[63:0]$11058 end - attribute \src "libresoc.v:179346.3-179381.6" - process $proc$libresoc.v:179346$11082 + attribute \src "libresoc.v:180654.3-180689.6" + process $proc$libresoc.v:180654$11066 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11083 $1\wr_detect$4[0:0]$11084 - attribute \src "libresoc.v:179347.5-179347.29" + assign $0\wr_detect$4[0:0]$11067 $1\wr_detect$4[0:0]$11068 + attribute \src "libresoc.v:180655.5-180655.29" switch \initial - attribute \src "libresoc.v:179347.9-179347.17" + attribute \src "libresoc.v:180655.9-180655.17" case 1'1 case end @@ -365439,58 +336809,58 @@ module \reg_1$136 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11084 $5\wr_detect$4[0:0]$11088 + assign $1\wr_detect$4[0:0]$11068 $5\wr_detect$4[0:0]$11072 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11085 1'1 + assign $2\wr_detect$4[0:0]$11069 1'1 case - assign $2\wr_detect$4[0:0]$11085 1'0 + assign $2\wr_detect$4[0:0]$11069 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11086 1'1 + assign $3\wr_detect$4[0:0]$11070 1'1 case - assign $3\wr_detect$4[0:0]$11086 $2\wr_detect$4[0:0]$11085 + assign $3\wr_detect$4[0:0]$11070 $2\wr_detect$4[0:0]$11069 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11087 1'1 + assign $4\wr_detect$4[0:0]$11071 1'1 case - assign $4\wr_detect$4[0:0]$11087 $3\wr_detect$4[0:0]$11086 + assign $4\wr_detect$4[0:0]$11071 $3\wr_detect$4[0:0]$11070 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$11088 1'1 + assign $5\wr_detect$4[0:0]$11072 1'1 case - assign $5\wr_detect$4[0:0]$11088 $4\wr_detect$4[0:0]$11087 + assign $5\wr_detect$4[0:0]$11072 $4\wr_detect$4[0:0]$11071 end case - assign $1\wr_detect$4[0:0]$11084 1'0 + assign $1\wr_detect$4[0:0]$11068 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11083 + update \wr_detect$4 $0\wr_detect$4[0:0]$11067 end - attribute \src "libresoc.v:179382.3-179427.6" - process $proc$libresoc.v:179382$11089 + attribute \src "libresoc.v:180690.3-180735.6" + process $proc$libresoc.v:180690$11073 assign { } { } assign { } { } assign { } { } - assign $0\sv1__data_o$next[63:0]$11090 $7\sv1__data_o$next[63:0]$11097 - attribute \src "libresoc.v:179383.5-179383.29" + assign $0\sv1__data_o$next[63:0]$11074 $7\sv1__data_o$next[63:0]$11081 + attribute \src "libresoc.v:180691.5-180691.29" switch \initial - attribute \src "libresoc.v:179383.9-179383.17" + attribute \src "libresoc.v:180691.9-180691.17" case 1'1 case end @@ -365503,75 +336873,75 @@ module \reg_1$136 assign { } { } assign { } { } assign { } { } - assign $1\sv1__data_o$next[63:0]$11091 $6\sv1__data_o$next[63:0]$11096 + assign $1\sv1__data_o$next[63:0]$11075 $6\sv1__data_o$next[63:0]$11080 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sv1__data_o$next[63:0]$11092 \nia1__data_i + assign $2\sv1__data_o$next[63:0]$11076 \nia1__data_i case - assign $2\sv1__data_o$next[63:0]$11092 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sv1__data_o$next[63:0]$11076 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sv1__data_o$next[63:0]$11093 \msr1__data_i + assign $3\sv1__data_o$next[63:0]$11077 \msr1__data_i case - assign $3\sv1__data_o$next[63:0]$11093 $2\sv1__data_o$next[63:0]$11092 + assign $3\sv1__data_o$next[63:0]$11077 $2\sv1__data_o$next[63:0]$11076 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\sv1__data_o$next[63:0]$11094 \sv1__data_i + assign $4\sv1__data_o$next[63:0]$11078 \sv1__data_i case - assign $4\sv1__data_o$next[63:0]$11094 $3\sv1__data_o$next[63:0]$11093 + assign $4\sv1__data_o$next[63:0]$11078 $3\sv1__data_o$next[63:0]$11077 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\sv1__data_o$next[63:0]$11095 \d_wr11__data_i + assign $5\sv1__data_o$next[63:0]$11079 \d_wr11__data_i case - assign $5\sv1__data_o$next[63:0]$11095 $4\sv1__data_o$next[63:0]$11094 + assign $5\sv1__data_o$next[63:0]$11079 $4\sv1__data_o$next[63:0]$11078 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\sv1__data_o$next[63:0]$11096 \reg + assign $6\sv1__data_o$next[63:0]$11080 \reg case - assign $6\sv1__data_o$next[63:0]$11096 $5\sv1__data_o$next[63:0]$11095 + assign $6\sv1__data_o$next[63:0]$11080 $5\sv1__data_o$next[63:0]$11079 end case - assign $1\sv1__data_o$next[63:0]$11091 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\sv1__data_o$next[63:0]$11075 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\sv1__data_o$next[63:0]$11097 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\sv1__data_o$next[63:0]$11081 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\sv1__data_o$next[63:0]$11097 $1\sv1__data_o$next[63:0]$11091 + assign $7\sv1__data_o$next[63:0]$11081 $1\sv1__data_o$next[63:0]$11075 end sync always - update \sv1__data_o$next $0\sv1__data_o$next[63:0]$11090 + update \sv1__data_o$next $0\sv1__data_o$next[63:0]$11074 end - attribute \src "libresoc.v:179428.3-179463.6" - process $proc$libresoc.v:179428$11098 + attribute \src "libresoc.v:180736.3-180771.6" + process $proc$libresoc.v:180736$11082 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11099 $1\wr_detect$7[0:0]$11100 - attribute \src "libresoc.v:179429.5-179429.29" + assign $0\wr_detect$7[0:0]$11083 $1\wr_detect$7[0:0]$11084 + attribute \src "libresoc.v:180737.5-180737.29" switch \initial - attribute \src "libresoc.v:179429.9-179429.17" + attribute \src "libresoc.v:180737.9-180737.17" case 1'1 case end @@ -365584,61 +336954,61 @@ module \reg_1$136 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11100 $5\wr_detect$7[0:0]$11104 + assign $1\wr_detect$7[0:0]$11084 $5\wr_detect$7[0:0]$11088 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11101 1'1 + assign $2\wr_detect$7[0:0]$11085 1'1 case - assign $2\wr_detect$7[0:0]$11101 1'0 + assign $2\wr_detect$7[0:0]$11085 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11102 1'1 + assign $3\wr_detect$7[0:0]$11086 1'1 case - assign $3\wr_detect$7[0:0]$11102 $2\wr_detect$7[0:0]$11101 + assign $3\wr_detect$7[0:0]$11086 $2\wr_detect$7[0:0]$11085 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11103 1'1 + assign $4\wr_detect$7[0:0]$11087 1'1 case - assign $4\wr_detect$7[0:0]$11103 $3\wr_detect$7[0:0]$11102 + assign $4\wr_detect$7[0:0]$11087 $3\wr_detect$7[0:0]$11086 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$11104 1'1 + assign $5\wr_detect$7[0:0]$11088 1'1 case - assign $5\wr_detect$7[0:0]$11104 $4\wr_detect$7[0:0]$11103 + assign $5\wr_detect$7[0:0]$11088 $4\wr_detect$7[0:0]$11087 end case - assign $1\wr_detect$7[0:0]$11100 1'0 + assign $1\wr_detect$7[0:0]$11084 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11099 + update \wr_detect$7 $0\wr_detect$7[0:0]$11083 end - attribute \src "libresoc.v:179464.3-179496.6" - process $proc$libresoc.v:179464$11105 + attribute \src "libresoc.v:180772.3-180804.6" + process $proc$libresoc.v:180772$11089 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[63:0]$11106 $5\reg$next[63:0]$11111 - attribute \src "libresoc.v:179465.5-179465.29" + assign $0\reg$next[63:0]$11090 $5\reg$next[63:0]$11095 + attribute \src "libresoc.v:180773.5-180773.29" switch \initial - attribute \src "libresoc.v:179465.9-179465.17" + attribute \src "libresoc.v:180773.9-180773.17" case 1'1 case end @@ -365647,254 +337017,254 @@ module \reg_1$136 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[63:0]$11107 \nia1__data_i + assign $1\reg$next[63:0]$11091 \nia1__data_i case - assign $1\reg$next[63:0]$11107 \reg + assign $1\reg$next[63:0]$11091 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \msr1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[63:0]$11108 \msr1__data_i + assign $2\reg$next[63:0]$11092 \msr1__data_i case - assign $2\reg$next[63:0]$11108 $1\reg$next[63:0]$11107 + assign $2\reg$next[63:0]$11092 $1\reg$next[63:0]$11091 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \sv1__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[63:0]$11109 \sv1__data_i + assign $3\reg$next[63:0]$11093 \sv1__data_i case - assign $3\reg$next[63:0]$11109 $2\reg$next[63:0]$11108 + assign $3\reg$next[63:0]$11093 $2\reg$next[63:0]$11092 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \d_wr11__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[63:0]$11110 \d_wr11__data_i + assign $4\reg$next[63:0]$11094 \d_wr11__data_i case - assign $4\reg$next[63:0]$11110 $3\reg$next[63:0]$11109 + assign $4\reg$next[63:0]$11094 $3\reg$next[63:0]$11093 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[63:0]$11111 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $5\reg$next[63:0]$11095 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $5\reg$next[63:0]$11111 $4\reg$next[63:0]$11110 + assign $5\reg$next[63:0]$11095 $4\reg$next[63:0]$11094 end sync always - update \reg$next $0\reg$next[63:0]$11106 + update \reg$next $0\reg$next[63:0]$11090 end - connect \$1 $not$libresoc.v:179207$11056_Y - connect \$3 $not$libresoc.v:179208$11057_Y - connect \$6 $not$libresoc.v:179209$11058_Y + connect \$1 $not$libresoc.v:180515$11040_Y + connect \$3 $not$libresoc.v:180516$11041_Y + connect \$6 $not$libresoc.v:180517$11042_Y end -attribute \src "libresoc.v:179501.1-180056.10" +attribute \src "libresoc.v:180809.1-181364.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_2" attribute \generator "nMigen" module \reg_2 - attribute \src "libresoc.v:179609.3-179648.6" - wire width 4 $0\cr_pred2__data_o$next[3:0]$11131 - attribute \src "libresoc.v:179607.3-179608.49" + attribute \src "libresoc.v:180917.3-180956.6" + wire width 4 $0\cr_pred2__data_o$next[3:0]$11115 + attribute \src "libresoc.v:180915.3-180916.49" wire width 4 $0\cr_pred2__data_o[3:0] - attribute \src "libresoc.v:179502.7-179502.20" + attribute \src "libresoc.v:180810.7-180810.20" wire $0\initial[0:0] - attribute \src "libresoc.v:179679.3-179718.6" - wire width 4 $0\r22__data_o$next[3:0]$11140 - attribute \src "libresoc.v:179597.3-179598.39" + attribute \src "libresoc.v:180987.3-181026.6" + wire width 4 $0\r22__data_o$next[3:0]$11124 + attribute \src "libresoc.v:180905.3-180906.39" wire width 4 $0\r22__data_o[3:0] - attribute \src "libresoc.v:179986.3-180025.6" - wire width 4 $0\r2__data_o$next[3:0]$11202 - attribute \src "libresoc.v:179599.3-179600.37" + attribute \src "libresoc.v:181294.3-181333.6" + wire width 4 $0\r2__data_o$next[3:0]$11186 + attribute \src "libresoc.v:180907.3-180908.37" wire width 4 $0\r2__data_o[3:0] - attribute \src "libresoc.v:179749.3-179775.6" - wire width 4 $0\reg$next[3:0]$11154 - attribute \src "libresoc.v:179595.3-179596.25" + attribute \src "libresoc.v:181057.3-181083.6" + wire width 4 $0\reg$next[3:0]$11138 + attribute \src "libresoc.v:180903.3-180904.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:179776.3-179815.6" - wire width 4 $0\src12__data_o$next[3:0]$11160 - attribute \src "libresoc.v:179605.3-179606.43" + attribute \src "libresoc.v:181084.3-181123.6" + wire width 4 $0\src12__data_o$next[3:0]$11144 + attribute \src "libresoc.v:180913.3-180914.43" wire width 4 $0\src12__data_o[3:0] - attribute \src "libresoc.v:179846.3-179885.6" - wire width 4 $0\src22__data_o$next[3:0]$11174 - attribute \src "libresoc.v:179603.3-179604.43" + attribute \src "libresoc.v:181154.3-181193.6" + wire width 4 $0\src22__data_o$next[3:0]$11158 + attribute \src "libresoc.v:180911.3-180912.43" wire width 4 $0\src22__data_o[3:0] - attribute \src "libresoc.v:179916.3-179955.6" - wire width 4 $0\src32__data_o$next[3:0]$11188 - attribute \src "libresoc.v:179601.3-179602.43" + attribute \src "libresoc.v:181224.3-181263.6" + wire width 4 $0\src32__data_o$next[3:0]$11172 + attribute \src "libresoc.v:180909.3-180910.43" wire width 4 $0\src32__data_o[3:0] - attribute \src "libresoc.v:179956.3-179985.6" - wire $0\wr_detect$10[0:0]$11196 - attribute \src "libresoc.v:180026.3-180055.6" - wire $0\wr_detect$13[0:0]$11210 - attribute \src "libresoc.v:179719.3-179748.6" - wire $0\wr_detect$16[0:0]$11148 - attribute \src "libresoc.v:179816.3-179845.6" - wire $0\wr_detect$4[0:0]$11168 - attribute \src "libresoc.v:179886.3-179915.6" - wire $0\wr_detect$7[0:0]$11182 - attribute \src "libresoc.v:179649.3-179678.6" + attribute \src "libresoc.v:181264.3-181293.6" + wire $0\wr_detect$10[0:0]$11180 + attribute \src "libresoc.v:181334.3-181363.6" + wire $0\wr_detect$13[0:0]$11194 + attribute \src "libresoc.v:181027.3-181056.6" + wire $0\wr_detect$16[0:0]$11132 + attribute \src "libresoc.v:181124.3-181153.6" + wire $0\wr_detect$4[0:0]$11152 + attribute \src "libresoc.v:181194.3-181223.6" + wire $0\wr_detect$7[0:0]$11166 + attribute \src "libresoc.v:180957.3-180986.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:179609.3-179648.6" - wire width 4 $1\cr_pred2__data_o$next[3:0]$11132 - attribute \src "libresoc.v:179521.13-179521.36" + attribute \src "libresoc.v:180917.3-180956.6" + wire width 4 $1\cr_pred2__data_o$next[3:0]$11116 + attribute \src "libresoc.v:180829.13-180829.36" wire width 4 $1\cr_pred2__data_o[3:0] - attribute \src "libresoc.v:179679.3-179718.6" - wire width 4 $1\r22__data_o$next[3:0]$11141 - attribute \src "libresoc.v:179536.13-179536.31" + attribute \src "libresoc.v:180987.3-181026.6" + wire width 4 $1\r22__data_o$next[3:0]$11125 + attribute \src "libresoc.v:180844.13-180844.31" wire width 4 $1\r22__data_o[3:0] - attribute \src "libresoc.v:179986.3-180025.6" - wire width 4 $1\r2__data_o$next[3:0]$11203 - attribute \src "libresoc.v:179543.13-179543.30" + attribute \src "libresoc.v:181294.3-181333.6" + wire width 4 $1\r2__data_o$next[3:0]$11187 + attribute \src "libresoc.v:180851.13-180851.30" wire width 4 $1\r2__data_o[3:0] - attribute \src "libresoc.v:179749.3-179775.6" - wire width 4 $1\reg$next[3:0]$11155 - attribute \src "libresoc.v:179549.13-179549.25" + attribute \src "libresoc.v:181057.3-181083.6" + wire width 4 $1\reg$next[3:0]$11139 + attribute \src "libresoc.v:180857.13-180857.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:179776.3-179815.6" - wire width 4 $1\src12__data_o$next[3:0]$11161 - attribute \src "libresoc.v:179554.13-179554.33" + attribute \src "libresoc.v:181084.3-181123.6" + wire width 4 $1\src12__data_o$next[3:0]$11145 + attribute \src "libresoc.v:180862.13-180862.33" wire width 4 $1\src12__data_o[3:0] - attribute \src "libresoc.v:179846.3-179885.6" - wire width 4 $1\src22__data_o$next[3:0]$11175 - attribute \src "libresoc.v:179561.13-179561.33" + attribute \src "libresoc.v:181154.3-181193.6" + wire width 4 $1\src22__data_o$next[3:0]$11159 + attribute \src "libresoc.v:180869.13-180869.33" wire width 4 $1\src22__data_o[3:0] - attribute \src "libresoc.v:179916.3-179955.6" - wire width 4 $1\src32__data_o$next[3:0]$11189 - attribute \src "libresoc.v:179568.13-179568.33" + attribute \src "libresoc.v:181224.3-181263.6" + wire width 4 $1\src32__data_o$next[3:0]$11173 + attribute \src "libresoc.v:180876.13-180876.33" wire width 4 $1\src32__data_o[3:0] - attribute \src "libresoc.v:179956.3-179985.6" - wire $1\wr_detect$10[0:0]$11197 - attribute \src "libresoc.v:180026.3-180055.6" - wire $1\wr_detect$13[0:0]$11211 - attribute \src "libresoc.v:179719.3-179748.6" - wire $1\wr_detect$16[0:0]$11149 - attribute \src "libresoc.v:179816.3-179845.6" - wire $1\wr_detect$4[0:0]$11169 - attribute \src "libresoc.v:179886.3-179915.6" - wire $1\wr_detect$7[0:0]$11183 - attribute \src "libresoc.v:179649.3-179678.6" + attribute \src "libresoc.v:181264.3-181293.6" + wire $1\wr_detect$10[0:0]$11181 + attribute \src "libresoc.v:181334.3-181363.6" + wire $1\wr_detect$13[0:0]$11195 + attribute \src "libresoc.v:181027.3-181056.6" + wire $1\wr_detect$16[0:0]$11133 + attribute \src "libresoc.v:181124.3-181153.6" + wire $1\wr_detect$4[0:0]$11153 + attribute \src "libresoc.v:181194.3-181223.6" + wire $1\wr_detect$7[0:0]$11167 + attribute \src "libresoc.v:180957.3-180986.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:179609.3-179648.6" - wire width 4 $2\cr_pred2__data_o$next[3:0]$11133 - attribute \src "libresoc.v:179679.3-179718.6" - wire width 4 $2\r22__data_o$next[3:0]$11142 - attribute \src "libresoc.v:179986.3-180025.6" - wire width 4 $2\r2__data_o$next[3:0]$11204 - attribute \src "libresoc.v:179749.3-179775.6" - wire width 4 $2\reg$next[3:0]$11156 - attribute \src "libresoc.v:179776.3-179815.6" - wire width 4 $2\src12__data_o$next[3:0]$11162 - attribute \src "libresoc.v:179846.3-179885.6" - wire width 4 $2\src22__data_o$next[3:0]$11176 - attribute \src "libresoc.v:179916.3-179955.6" - wire width 4 $2\src32__data_o$next[3:0]$11190 - attribute \src "libresoc.v:179956.3-179985.6" - wire $2\wr_detect$10[0:0]$11198 - attribute \src "libresoc.v:180026.3-180055.6" - wire $2\wr_detect$13[0:0]$11212 - attribute \src "libresoc.v:179719.3-179748.6" - wire $2\wr_detect$16[0:0]$11150 - attribute \src "libresoc.v:179816.3-179845.6" - wire $2\wr_detect$4[0:0]$11170 - attribute \src "libresoc.v:179886.3-179915.6" - wire $2\wr_detect$7[0:0]$11184 - attribute \src "libresoc.v:179649.3-179678.6" + attribute \src "libresoc.v:180917.3-180956.6" + wire width 4 $2\cr_pred2__data_o$next[3:0]$11117 + attribute \src "libresoc.v:180987.3-181026.6" + wire width 4 $2\r22__data_o$next[3:0]$11126 + attribute \src "libresoc.v:181294.3-181333.6" + wire width 4 $2\r2__data_o$next[3:0]$11188 + attribute \src "libresoc.v:181057.3-181083.6" + wire width 4 $2\reg$next[3:0]$11140 + attribute \src "libresoc.v:181084.3-181123.6" + wire width 4 $2\src12__data_o$next[3:0]$11146 + attribute \src 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attribute \src "libresoc.v:180987.3-181026.6" + wire width 4 $5\r22__data_o$next[3:0]$11129 + attribute \src "libresoc.v:181294.3-181333.6" + wire width 4 $5\r2__data_o$next[3:0]$11191 + attribute \src "libresoc.v:181084.3-181123.6" + wire width 4 $5\src12__data_o$next[3:0]$11149 + attribute \src "libresoc.v:181154.3-181193.6" + wire width 4 $5\src22__data_o$next[3:0]$11163 + attribute \src "libresoc.v:181224.3-181263.6" + wire width 4 $5\src32__data_o$next[3:0]$11177 + attribute \src "libresoc.v:180917.3-180956.6" + wire width 4 $6\cr_pred2__data_o$next[3:0]$11121 + attribute \src "libresoc.v:180987.3-181026.6" + wire width 4 $6\r22__data_o$next[3:0]$11130 + attribute \src "libresoc.v:181294.3-181333.6" + wire width 4 $6\r2__data_o$next[3:0]$11192 + attribute \src "libresoc.v:181084.3-181123.6" + wire width 4 $6\src12__data_o$next[3:0]$11150 + attribute \src "libresoc.v:181154.3-181193.6" + wire width 4 $6\src22__data_o$next[3:0]$11164 + attribute \src "libresoc.v:181224.3-181263.6" + wire width 4 $6\src32__data_o$next[3:0]$11178 + attribute \src "libresoc.v:180897.17-180897.104" + wire $not$libresoc.v:180897$11101_Y + attribute \src "libresoc.v:180898.18-180898.105" + wire $not$libresoc.v:180898$11102_Y + attribute \src "libresoc.v:180899.18-180899.105" + wire $not$libresoc.v:180899$11103_Y + attribute \src "libresoc.v:180900.17-180900.100" + wire $not$libresoc.v:180900$11104_Y + attribute \src "libresoc.v:180901.17-180901.103" + wire $not$libresoc.v:180901$11105_Y + attribute \src "libresoc.v:180902.17-180902.103" + wire $not$libresoc.v:180902$11106_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -365907,9 +337277,9 @@ module \reg_2 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 20 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 3 \cr_pred2__data_o @@ -365925,7 +337295,7 @@ module \reg_2 wire width 4 input 13 \dest22__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest22__wen - attribute \src "libresoc.v:179502.7-179502.15" + attribute \src "libresoc.v:180810.7-180810.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 16 \r22__data_o @@ -365978,175 +337348,175 @@ module \reg_2 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179589$11117 + cell $not $not$libresoc.v:180897$11101 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:179589$11117_Y + connect \Y $not$libresoc.v:180897$11101_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179590$11118 + cell $not $not$libresoc.v:180898$11102 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:179590$11118_Y + connect \Y $not$libresoc.v:180898$11102_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179591$11119 + cell $not $not$libresoc.v:180899$11103 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$16 - connect \Y $not$libresoc.v:179591$11119_Y + connect \Y $not$libresoc.v:180899$11103_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179592$11120 + cell $not $not$libresoc.v:180900$11104 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:179592$11120_Y + connect \Y $not$libresoc.v:180900$11104_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179593$11121 + cell $not $not$libresoc.v:180901$11105 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:179593$11121_Y + connect \Y $not$libresoc.v:180901$11105_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:179594$11122 + cell $not $not$libresoc.v:180902$11106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:179594$11122_Y + connect \Y $not$libresoc.v:180902$11106_Y end - attribute \src "libresoc.v:179502.7-179502.20" - process $proc$libresoc.v:179502$11215 + attribute \src "libresoc.v:180810.7-180810.20" + process $proc$libresoc.v:180810$11199 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:179521.13-179521.36" - process $proc$libresoc.v:179521$11216 + attribute \src "libresoc.v:180829.13-180829.36" + process $proc$libresoc.v:180829$11200 assign { } { } assign $1\cr_pred2__data_o[3:0] 4'0000 sync always sync init update \cr_pred2__data_o $1\cr_pred2__data_o[3:0] end - attribute \src "libresoc.v:179536.13-179536.31" - process $proc$libresoc.v:179536$11217 + attribute \src "libresoc.v:180844.13-180844.31" + process $proc$libresoc.v:180844$11201 assign { } { } assign $1\r22__data_o[3:0] 4'0000 sync always sync init update \r22__data_o $1\r22__data_o[3:0] end - attribute \src "libresoc.v:179543.13-179543.30" - process $proc$libresoc.v:179543$11218 + attribute \src "libresoc.v:180851.13-180851.30" + process $proc$libresoc.v:180851$11202 assign { } { } assign $1\r2__data_o[3:0] 4'0000 sync always sync init update \r2__data_o $1\r2__data_o[3:0] end - attribute \src "libresoc.v:179549.13-179549.25" - process $proc$libresoc.v:179549$11219 + attribute \src "libresoc.v:180857.13-180857.25" + process $proc$libresoc.v:180857$11203 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:179554.13-179554.33" - process $proc$libresoc.v:179554$11220 + attribute \src "libresoc.v:180862.13-180862.33" + process $proc$libresoc.v:180862$11204 assign { } { } assign $1\src12__data_o[3:0] 4'0000 sync always sync init update \src12__data_o $1\src12__data_o[3:0] end - attribute \src "libresoc.v:179561.13-179561.33" - process $proc$libresoc.v:179561$11221 + attribute \src "libresoc.v:180869.13-180869.33" + process $proc$libresoc.v:180869$11205 assign { } { } assign $1\src22__data_o[3:0] 4'0000 sync always sync init update \src22__data_o $1\src22__data_o[3:0] end - attribute \src "libresoc.v:179568.13-179568.33" - process $proc$libresoc.v:179568$11222 + attribute \src "libresoc.v:180876.13-180876.33" + process $proc$libresoc.v:180876$11206 assign { } { } assign $1\src32__data_o[3:0] 4'0000 sync always sync init update \src32__data_o $1\src32__data_o[3:0] end - attribute \src "libresoc.v:179595.3-179596.25" - process $proc$libresoc.v:179595$11123 + attribute \src "libresoc.v:180903.3-180904.25" + process $proc$libresoc.v:180903$11107 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:179597.3-179598.39" - process $proc$libresoc.v:179597$11124 + attribute \src "libresoc.v:180905.3-180906.39" + process $proc$libresoc.v:180905$11108 assign { } { } assign $0\r22__data_o[3:0] \r22__data_o$next sync posedge \coresync_clk update \r22__data_o $0\r22__data_o[3:0] end - attribute \src "libresoc.v:179599.3-179600.37" - process $proc$libresoc.v:179599$11125 + attribute \src "libresoc.v:180907.3-180908.37" + process $proc$libresoc.v:180907$11109 assign { } { } assign $0\r2__data_o[3:0] \r2__data_o$next sync posedge \coresync_clk update \r2__data_o $0\r2__data_o[3:0] end - attribute \src "libresoc.v:179601.3-179602.43" - process $proc$libresoc.v:179601$11126 + attribute \src "libresoc.v:180909.3-180910.43" + process $proc$libresoc.v:180909$11110 assign { } { } assign $0\src32__data_o[3:0] \src32__data_o$next sync posedge \coresync_clk update \src32__data_o $0\src32__data_o[3:0] end - attribute \src "libresoc.v:179603.3-179604.43" - process $proc$libresoc.v:179603$11127 + attribute \src "libresoc.v:180911.3-180912.43" + process $proc$libresoc.v:180911$11111 assign { } { } assign $0\src22__data_o[3:0] \src22__data_o$next sync posedge \coresync_clk update \src22__data_o $0\src22__data_o[3:0] end - attribute \src "libresoc.v:179605.3-179606.43" - process $proc$libresoc.v:179605$11128 + attribute \src "libresoc.v:180913.3-180914.43" + process $proc$libresoc.v:180913$11112 assign { } { } assign $0\src12__data_o[3:0] \src12__data_o$next sync posedge \coresync_clk update \src12__data_o $0\src12__data_o[3:0] end - attribute \src "libresoc.v:179607.3-179608.49" - process $proc$libresoc.v:179607$11129 + attribute \src "libresoc.v:180915.3-180916.49" + process $proc$libresoc.v:180915$11113 assign { } { } assign $0\cr_pred2__data_o[3:0] \cr_pred2__data_o$next sync posedge \coresync_clk update \cr_pred2__data_o $0\cr_pred2__data_o[3:0] end - attribute \src "libresoc.v:179609.3-179648.6" - process $proc$libresoc.v:179609$11130 + attribute \src "libresoc.v:180917.3-180956.6" + process $proc$libresoc.v:180917$11114 assign { } { } assign { } { } assign { } { } - assign $0\cr_pred2__data_o$next[3:0]$11131 $6\cr_pred2__data_o$next[3:0]$11137 - attribute \src "libresoc.v:179610.5-179610.29" + assign $0\cr_pred2__data_o$next[3:0]$11115 $6\cr_pred2__data_o$next[3:0]$11121 + attribute \src "libresoc.v:180918.5-180918.29" switch \initial - attribute \src "libresoc.v:179610.9-179610.17" + attribute \src "libresoc.v:180918.9-180918.17" case 1'1 case end @@ -366158,66 +337528,66 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\cr_pred2__data_o$next[3:0]$11132 $5\cr_pred2__data_o$next[3:0]$11136 + assign $1\cr_pred2__data_o$next[3:0]$11116 $5\cr_pred2__data_o$next[3:0]$11120 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_pred2__data_o$next[3:0]$11133 \dest12__data_i + assign $2\cr_pred2__data_o$next[3:0]$11117 \dest12__data_i case - assign $2\cr_pred2__data_o$next[3:0]$11133 4'0000 + assign $2\cr_pred2__data_o$next[3:0]$11117 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\cr_pred2__data_o$next[3:0]$11134 \dest22__data_i + assign $3\cr_pred2__data_o$next[3:0]$11118 \dest22__data_i case - assign $3\cr_pred2__data_o$next[3:0]$11134 $2\cr_pred2__data_o$next[3:0]$11133 + assign $3\cr_pred2__data_o$next[3:0]$11118 $2\cr_pred2__data_o$next[3:0]$11117 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cr_pred2__data_o$next[3:0]$11135 \w2__data_i + assign $4\cr_pred2__data_o$next[3:0]$11119 \w2__data_i case - assign $4\cr_pred2__data_o$next[3:0]$11135 $3\cr_pred2__data_o$next[3:0]$11134 + assign $4\cr_pred2__data_o$next[3:0]$11119 $3\cr_pred2__data_o$next[3:0]$11118 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\cr_pred2__data_o$next[3:0]$11136 \reg + assign $5\cr_pred2__data_o$next[3:0]$11120 \reg case - assign $5\cr_pred2__data_o$next[3:0]$11136 $4\cr_pred2__data_o$next[3:0]$11135 + assign $5\cr_pred2__data_o$next[3:0]$11120 $4\cr_pred2__data_o$next[3:0]$11119 end case - assign $1\cr_pred2__data_o$next[3:0]$11132 4'0000 + assign $1\cr_pred2__data_o$next[3:0]$11116 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cr_pred2__data_o$next[3:0]$11137 4'0000 + assign $6\cr_pred2__data_o$next[3:0]$11121 4'0000 case - assign $6\cr_pred2__data_o$next[3:0]$11137 $1\cr_pred2__data_o$next[3:0]$11132 + assign $6\cr_pred2__data_o$next[3:0]$11121 $1\cr_pred2__data_o$next[3:0]$11116 end sync always - update \cr_pred2__data_o$next $0\cr_pred2__data_o$next[3:0]$11131 + update \cr_pred2__data_o$next $0\cr_pred2__data_o$next[3:0]$11115 end - attribute \src "libresoc.v:179649.3-179678.6" - process $proc$libresoc.v:179649$11138 + attribute \src "libresoc.v:180957.3-180986.6" + process $proc$libresoc.v:180957$11122 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:179650.5-179650.29" + attribute \src "libresoc.v:180958.5-180958.29" switch \initial - attribute \src "libresoc.v:179650.9-179650.17" + attribute \src "libresoc.v:180958.9-180958.17" case 1'1 case end @@ -366263,15 +337633,15 @@ module \reg_2 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:179679.3-179718.6" - process $proc$libresoc.v:179679$11139 + attribute \src "libresoc.v:180987.3-181026.6" + process $proc$libresoc.v:180987$11123 assign { } { } assign { } { } assign { } { } - assign $0\r22__data_o$next[3:0]$11140 $6\r22__data_o$next[3:0]$11146 - attribute \src "libresoc.v:179680.5-179680.29" + assign $0\r22__data_o$next[3:0]$11124 $6\r22__data_o$next[3:0]$11130 + attribute \src "libresoc.v:180988.5-180988.29" switch \initial - attribute \src "libresoc.v:179680.9-179680.17" + attribute \src "libresoc.v:180988.9-180988.17" case 1'1 case end @@ -366283,66 +337653,66 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\r22__data_o$next[3:0]$11141 $5\r22__data_o$next[3:0]$11145 + assign $1\r22__data_o$next[3:0]$11125 $5\r22__data_o$next[3:0]$11129 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r22__data_o$next[3:0]$11142 \dest12__data_i + assign $2\r22__data_o$next[3:0]$11126 \dest12__data_i case - assign $2\r22__data_o$next[3:0]$11142 4'0000 + assign $2\r22__data_o$next[3:0]$11126 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r22__data_o$next[3:0]$11143 \dest22__data_i + assign $3\r22__data_o$next[3:0]$11127 \dest22__data_i case - assign $3\r22__data_o$next[3:0]$11143 $2\r22__data_o$next[3:0]$11142 + assign $3\r22__data_o$next[3:0]$11127 $2\r22__data_o$next[3:0]$11126 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r22__data_o$next[3:0]$11144 \w2__data_i + assign $4\r22__data_o$next[3:0]$11128 \w2__data_i case - assign $4\r22__data_o$next[3:0]$11144 $3\r22__data_o$next[3:0]$11143 + assign $4\r22__data_o$next[3:0]$11128 $3\r22__data_o$next[3:0]$11127 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$15 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r22__data_o$next[3:0]$11145 \reg + assign $5\r22__data_o$next[3:0]$11129 \reg case - assign $5\r22__data_o$next[3:0]$11145 $4\r22__data_o$next[3:0]$11144 + assign $5\r22__data_o$next[3:0]$11129 $4\r22__data_o$next[3:0]$11128 end case - assign $1\r22__data_o$next[3:0]$11141 4'0000 + assign $1\r22__data_o$next[3:0]$11125 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r22__data_o$next[3:0]$11146 4'0000 + assign $6\r22__data_o$next[3:0]$11130 4'0000 case - assign $6\r22__data_o$next[3:0]$11146 $1\r22__data_o$next[3:0]$11141 + assign $6\r22__data_o$next[3:0]$11130 $1\r22__data_o$next[3:0]$11125 end sync always - update \r22__data_o$next $0\r22__data_o$next[3:0]$11140 + update \r22__data_o$next $0\r22__data_o$next[3:0]$11124 end - attribute \src "libresoc.v:179719.3-179748.6" - process $proc$libresoc.v:179719$11147 + attribute \src "libresoc.v:181027.3-181056.6" + process $proc$libresoc.v:181027$11131 assign { } { } assign { } { } - assign $0\wr_detect$16[0:0]$11148 $1\wr_detect$16[0:0]$11149 - attribute \src "libresoc.v:179720.5-179720.29" + assign $0\wr_detect$16[0:0]$11132 $1\wr_detect$16[0:0]$11133 + attribute \src "libresoc.v:181028.5-181028.29" switch \initial - attribute \src "libresoc.v:179720.9-179720.17" + attribute \src "libresoc.v:181028.9-181028.17" case 1'1 case end @@ -366354,51 +337724,51 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$16[0:0]$11149 $4\wr_detect$16[0:0]$11152 + assign $1\wr_detect$16[0:0]$11133 $4\wr_detect$16[0:0]$11136 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$16[0:0]$11150 1'1 + assign $2\wr_detect$16[0:0]$11134 1'1 case - assign $2\wr_detect$16[0:0]$11150 1'0 + assign $2\wr_detect$16[0:0]$11134 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$16[0:0]$11151 1'1 + assign $3\wr_detect$16[0:0]$11135 1'1 case - assign $3\wr_detect$16[0:0]$11151 $2\wr_detect$16[0:0]$11150 + assign $3\wr_detect$16[0:0]$11135 $2\wr_detect$16[0:0]$11134 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$16[0:0]$11152 1'1 + assign $4\wr_detect$16[0:0]$11136 1'1 case - assign $4\wr_detect$16[0:0]$11152 $3\wr_detect$16[0:0]$11151 + assign $4\wr_detect$16[0:0]$11136 $3\wr_detect$16[0:0]$11135 end case - assign $1\wr_detect$16[0:0]$11149 1'0 + assign $1\wr_detect$16[0:0]$11133 1'0 end sync always - update \wr_detect$16 $0\wr_detect$16[0:0]$11148 + update \wr_detect$16 $0\wr_detect$16[0:0]$11132 end - attribute \src "libresoc.v:179749.3-179775.6" - process $proc$libresoc.v:179749$11153 + attribute \src "libresoc.v:181057.3-181083.6" + process $proc$libresoc.v:181057$11137 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11154 $4\reg$next[3:0]$11158 - attribute \src "libresoc.v:179750.5-179750.29" + assign $0\reg$next[3:0]$11138 $4\reg$next[3:0]$11142 + attribute \src "libresoc.v:181058.5-181058.29" switch \initial - attribute \src "libresoc.v:179750.9-179750.17" + attribute \src "libresoc.v:181058.9-181058.17" case 1'1 case end @@ -366407,49 +337777,49 @@ module \reg_2 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11155 \dest12__data_i + assign $1\reg$next[3:0]$11139 \dest12__data_i case - assign $1\reg$next[3:0]$11155 \reg + assign $1\reg$next[3:0]$11139 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11156 \dest22__data_i + assign $2\reg$next[3:0]$11140 \dest22__data_i case - assign $2\reg$next[3:0]$11156 $1\reg$next[3:0]$11155 + assign $2\reg$next[3:0]$11140 $1\reg$next[3:0]$11139 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11157 \w2__data_i + assign $3\reg$next[3:0]$11141 \w2__data_i case - assign $3\reg$next[3:0]$11157 $2\reg$next[3:0]$11156 + assign $3\reg$next[3:0]$11141 $2\reg$next[3:0]$11140 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11158 4'0000 + assign $4\reg$next[3:0]$11142 4'0000 case - assign $4\reg$next[3:0]$11158 $3\reg$next[3:0]$11157 + assign $4\reg$next[3:0]$11142 $3\reg$next[3:0]$11141 end sync always - update \reg$next $0\reg$next[3:0]$11154 + update \reg$next $0\reg$next[3:0]$11138 end - attribute \src "libresoc.v:179776.3-179815.6" - process $proc$libresoc.v:179776$11159 + attribute \src "libresoc.v:181084.3-181123.6" + process $proc$libresoc.v:181084$11143 assign { } { } assign { } { } assign { } { } - assign $0\src12__data_o$next[3:0]$11160 $6\src12__data_o$next[3:0]$11166 - attribute \src "libresoc.v:179777.5-179777.29" + assign $0\src12__data_o$next[3:0]$11144 $6\src12__data_o$next[3:0]$11150 + attribute \src "libresoc.v:181085.5-181085.29" switch \initial - attribute \src "libresoc.v:179777.9-179777.17" + attribute \src "libresoc.v:181085.9-181085.17" case 1'1 case end @@ -366461,66 +337831,66 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\src12__data_o$next[3:0]$11161 $5\src12__data_o$next[3:0]$11165 + assign $1\src12__data_o$next[3:0]$11145 $5\src12__data_o$next[3:0]$11149 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src12__data_o$next[3:0]$11162 \dest12__data_i + assign $2\src12__data_o$next[3:0]$11146 \dest12__data_i case - assign $2\src12__data_o$next[3:0]$11162 4'0000 + assign $2\src12__data_o$next[3:0]$11146 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src12__data_o$next[3:0]$11163 \dest22__data_i + assign $3\src12__data_o$next[3:0]$11147 \dest22__data_i case - assign $3\src12__data_o$next[3:0]$11163 $2\src12__data_o$next[3:0]$11162 + assign $3\src12__data_o$next[3:0]$11147 $2\src12__data_o$next[3:0]$11146 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src12__data_o$next[3:0]$11164 \w2__data_i + assign $4\src12__data_o$next[3:0]$11148 \w2__data_i case - assign $4\src12__data_o$next[3:0]$11164 $3\src12__data_o$next[3:0]$11163 + assign $4\src12__data_o$next[3:0]$11148 $3\src12__data_o$next[3:0]$11147 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src12__data_o$next[3:0]$11165 \reg + assign $5\src12__data_o$next[3:0]$11149 \reg case - assign $5\src12__data_o$next[3:0]$11165 $4\src12__data_o$next[3:0]$11164 + assign $5\src12__data_o$next[3:0]$11149 $4\src12__data_o$next[3:0]$11148 end case - assign $1\src12__data_o$next[3:0]$11161 4'0000 + assign $1\src12__data_o$next[3:0]$11145 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src12__data_o$next[3:0]$11166 4'0000 + assign $6\src12__data_o$next[3:0]$11150 4'0000 case - assign $6\src12__data_o$next[3:0]$11166 $1\src12__data_o$next[3:0]$11161 + assign $6\src12__data_o$next[3:0]$11150 $1\src12__data_o$next[3:0]$11145 end sync always - update \src12__data_o$next $0\src12__data_o$next[3:0]$11160 + update \src12__data_o$next $0\src12__data_o$next[3:0]$11144 end - attribute \src "libresoc.v:179816.3-179845.6" - process $proc$libresoc.v:179816$11167 + attribute \src "libresoc.v:181124.3-181153.6" + process $proc$libresoc.v:181124$11151 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11168 $1\wr_detect$4[0:0]$11169 - attribute \src "libresoc.v:179817.5-179817.29" + assign $0\wr_detect$4[0:0]$11152 $1\wr_detect$4[0:0]$11153 + attribute \src "libresoc.v:181125.5-181125.29" switch \initial - attribute \src "libresoc.v:179817.9-179817.17" + attribute \src "libresoc.v:181125.9-181125.17" case 1'1 case end @@ -366532,49 +337902,49 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11169 $4\wr_detect$4[0:0]$11172 + assign $1\wr_detect$4[0:0]$11153 $4\wr_detect$4[0:0]$11156 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11170 1'1 + assign $2\wr_detect$4[0:0]$11154 1'1 case - assign $2\wr_detect$4[0:0]$11170 1'0 + assign $2\wr_detect$4[0:0]$11154 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11171 1'1 + assign $3\wr_detect$4[0:0]$11155 1'1 case - assign $3\wr_detect$4[0:0]$11171 $2\wr_detect$4[0:0]$11170 + assign $3\wr_detect$4[0:0]$11155 $2\wr_detect$4[0:0]$11154 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11172 1'1 + assign $4\wr_detect$4[0:0]$11156 1'1 case - assign $4\wr_detect$4[0:0]$11172 $3\wr_detect$4[0:0]$11171 + assign $4\wr_detect$4[0:0]$11156 $3\wr_detect$4[0:0]$11155 end case - assign $1\wr_detect$4[0:0]$11169 1'0 + assign $1\wr_detect$4[0:0]$11153 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11168 + update \wr_detect$4 $0\wr_detect$4[0:0]$11152 end - attribute \src "libresoc.v:179846.3-179885.6" - process $proc$libresoc.v:179846$11173 + attribute \src "libresoc.v:181154.3-181193.6" + process $proc$libresoc.v:181154$11157 assign { } { } assign { } { } assign { } { } - assign $0\src22__data_o$next[3:0]$11174 $6\src22__data_o$next[3:0]$11180 - attribute \src "libresoc.v:179847.5-179847.29" + assign $0\src22__data_o$next[3:0]$11158 $6\src22__data_o$next[3:0]$11164 + attribute \src "libresoc.v:181155.5-181155.29" switch \initial - attribute \src "libresoc.v:179847.9-179847.17" + attribute \src "libresoc.v:181155.9-181155.17" case 1'1 case end @@ -366586,66 +337956,66 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\src22__data_o$next[3:0]$11175 $5\src22__data_o$next[3:0]$11179 + assign $1\src22__data_o$next[3:0]$11159 $5\src22__data_o$next[3:0]$11163 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src22__data_o$next[3:0]$11176 \dest12__data_i + assign $2\src22__data_o$next[3:0]$11160 \dest12__data_i case - assign $2\src22__data_o$next[3:0]$11176 4'0000 + assign $2\src22__data_o$next[3:0]$11160 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src22__data_o$next[3:0]$11177 \dest22__data_i + assign $3\src22__data_o$next[3:0]$11161 \dest22__data_i case - assign $3\src22__data_o$next[3:0]$11177 $2\src22__data_o$next[3:0]$11176 + assign $3\src22__data_o$next[3:0]$11161 $2\src22__data_o$next[3:0]$11160 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src22__data_o$next[3:0]$11178 \w2__data_i + assign $4\src22__data_o$next[3:0]$11162 \w2__data_i case - assign $4\src22__data_o$next[3:0]$11178 $3\src22__data_o$next[3:0]$11177 + assign $4\src22__data_o$next[3:0]$11162 $3\src22__data_o$next[3:0]$11161 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src22__data_o$next[3:0]$11179 \reg + assign $5\src22__data_o$next[3:0]$11163 \reg case - assign $5\src22__data_o$next[3:0]$11179 $4\src22__data_o$next[3:0]$11178 + assign $5\src22__data_o$next[3:0]$11163 $4\src22__data_o$next[3:0]$11162 end case - assign $1\src22__data_o$next[3:0]$11175 4'0000 + assign $1\src22__data_o$next[3:0]$11159 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src22__data_o$next[3:0]$11180 4'0000 + assign $6\src22__data_o$next[3:0]$11164 4'0000 case - assign $6\src22__data_o$next[3:0]$11180 $1\src22__data_o$next[3:0]$11175 + assign $6\src22__data_o$next[3:0]$11164 $1\src22__data_o$next[3:0]$11159 end sync always - update \src22__data_o$next $0\src22__data_o$next[3:0]$11174 + update \src22__data_o$next $0\src22__data_o$next[3:0]$11158 end - attribute \src "libresoc.v:179886.3-179915.6" - process $proc$libresoc.v:179886$11181 + attribute \src "libresoc.v:181194.3-181223.6" + process $proc$libresoc.v:181194$11165 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11182 $1\wr_detect$7[0:0]$11183 - attribute \src "libresoc.v:179887.5-179887.29" + assign $0\wr_detect$7[0:0]$11166 $1\wr_detect$7[0:0]$11167 + attribute \src "libresoc.v:181195.5-181195.29" switch \initial - attribute \src "libresoc.v:179887.9-179887.17" + attribute \src "libresoc.v:181195.9-181195.17" case 1'1 case end @@ -366657,49 +338027,49 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11183 $4\wr_detect$7[0:0]$11186 + assign $1\wr_detect$7[0:0]$11167 $4\wr_detect$7[0:0]$11170 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11184 1'1 + assign $2\wr_detect$7[0:0]$11168 1'1 case - assign $2\wr_detect$7[0:0]$11184 1'0 + assign $2\wr_detect$7[0:0]$11168 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11185 1'1 + assign $3\wr_detect$7[0:0]$11169 1'1 case - assign $3\wr_detect$7[0:0]$11185 $2\wr_detect$7[0:0]$11184 + assign $3\wr_detect$7[0:0]$11169 $2\wr_detect$7[0:0]$11168 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11186 1'1 + assign $4\wr_detect$7[0:0]$11170 1'1 case - assign $4\wr_detect$7[0:0]$11186 $3\wr_detect$7[0:0]$11185 + assign $4\wr_detect$7[0:0]$11170 $3\wr_detect$7[0:0]$11169 end case - assign $1\wr_detect$7[0:0]$11183 1'0 + assign $1\wr_detect$7[0:0]$11167 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11182 + update \wr_detect$7 $0\wr_detect$7[0:0]$11166 end - attribute \src "libresoc.v:179916.3-179955.6" - process $proc$libresoc.v:179916$11187 + attribute \src "libresoc.v:181224.3-181263.6" + process $proc$libresoc.v:181224$11171 assign { } { } assign { } { } assign { } { } - assign $0\src32__data_o$next[3:0]$11188 $6\src32__data_o$next[3:0]$11194 - attribute \src "libresoc.v:179917.5-179917.29" + assign $0\src32__data_o$next[3:0]$11172 $6\src32__data_o$next[3:0]$11178 + attribute \src "libresoc.v:181225.5-181225.29" switch \initial - attribute \src "libresoc.v:179917.9-179917.17" + attribute \src "libresoc.v:181225.9-181225.17" case 1'1 case end @@ -366711,66 +338081,66 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\src32__data_o$next[3:0]$11189 $5\src32__data_o$next[3:0]$11193 + assign $1\src32__data_o$next[3:0]$11173 $5\src32__data_o$next[3:0]$11177 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src32__data_o$next[3:0]$11190 \dest12__data_i + assign $2\src32__data_o$next[3:0]$11174 \dest12__data_i case - assign $2\src32__data_o$next[3:0]$11190 4'0000 + assign $2\src32__data_o$next[3:0]$11174 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src32__data_o$next[3:0]$11191 \dest22__data_i + assign $3\src32__data_o$next[3:0]$11175 \dest22__data_i case - assign $3\src32__data_o$next[3:0]$11191 $2\src32__data_o$next[3:0]$11190 + assign $3\src32__data_o$next[3:0]$11175 $2\src32__data_o$next[3:0]$11174 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src32__data_o$next[3:0]$11192 \w2__data_i + assign $4\src32__data_o$next[3:0]$11176 \w2__data_i case - assign $4\src32__data_o$next[3:0]$11192 $3\src32__data_o$next[3:0]$11191 + assign $4\src32__data_o$next[3:0]$11176 $3\src32__data_o$next[3:0]$11175 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src32__data_o$next[3:0]$11193 \reg + assign $5\src32__data_o$next[3:0]$11177 \reg case - assign $5\src32__data_o$next[3:0]$11193 $4\src32__data_o$next[3:0]$11192 + assign $5\src32__data_o$next[3:0]$11177 $4\src32__data_o$next[3:0]$11176 end case - assign $1\src32__data_o$next[3:0]$11189 4'0000 + assign $1\src32__data_o$next[3:0]$11173 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src32__data_o$next[3:0]$11194 4'0000 + assign $6\src32__data_o$next[3:0]$11178 4'0000 case - assign $6\src32__data_o$next[3:0]$11194 $1\src32__data_o$next[3:0]$11189 + assign $6\src32__data_o$next[3:0]$11178 $1\src32__data_o$next[3:0]$11173 end sync always - update \src32__data_o$next $0\src32__data_o$next[3:0]$11188 + update \src32__data_o$next $0\src32__data_o$next[3:0]$11172 end - attribute \src "libresoc.v:179956.3-179985.6" - process $proc$libresoc.v:179956$11195 + attribute \src "libresoc.v:181264.3-181293.6" + process $proc$libresoc.v:181264$11179 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11196 $1\wr_detect$10[0:0]$11197 - attribute \src "libresoc.v:179957.5-179957.29" + assign $0\wr_detect$10[0:0]$11180 $1\wr_detect$10[0:0]$11181 + attribute \src "libresoc.v:181265.5-181265.29" switch \initial - attribute \src "libresoc.v:179957.9-179957.17" + attribute \src "libresoc.v:181265.9-181265.17" case 1'1 case end @@ -366782,49 +338152,49 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11197 $4\wr_detect$10[0:0]$11200 + assign $1\wr_detect$10[0:0]$11181 $4\wr_detect$10[0:0]$11184 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11198 1'1 + assign $2\wr_detect$10[0:0]$11182 1'1 case - assign $2\wr_detect$10[0:0]$11198 1'0 + assign $2\wr_detect$10[0:0]$11182 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11199 1'1 + assign $3\wr_detect$10[0:0]$11183 1'1 case - assign $3\wr_detect$10[0:0]$11199 $2\wr_detect$10[0:0]$11198 + assign $3\wr_detect$10[0:0]$11183 $2\wr_detect$10[0:0]$11182 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11200 1'1 + assign $4\wr_detect$10[0:0]$11184 1'1 case - assign $4\wr_detect$10[0:0]$11200 $3\wr_detect$10[0:0]$11199 + assign $4\wr_detect$10[0:0]$11184 $3\wr_detect$10[0:0]$11183 end case - assign $1\wr_detect$10[0:0]$11197 1'0 + assign $1\wr_detect$10[0:0]$11181 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11196 + update \wr_detect$10 $0\wr_detect$10[0:0]$11180 end - attribute \src "libresoc.v:179986.3-180025.6" - process $proc$libresoc.v:179986$11201 + attribute \src "libresoc.v:181294.3-181333.6" + process $proc$libresoc.v:181294$11185 assign { } { } assign { } { } assign { } { } - assign $0\r2__data_o$next[3:0]$11202 $6\r2__data_o$next[3:0]$11208 - attribute \src "libresoc.v:179987.5-179987.29" + assign $0\r2__data_o$next[3:0]$11186 $6\r2__data_o$next[3:0]$11192 + attribute \src "libresoc.v:181295.5-181295.29" switch \initial - attribute \src "libresoc.v:179987.9-179987.17" + attribute \src "libresoc.v:181295.9-181295.17" case 1'1 case end @@ -366836,66 +338206,66 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\r2__data_o$next[3:0]$11203 $5\r2__data_o$next[3:0]$11207 + assign $1\r2__data_o$next[3:0]$11187 $5\r2__data_o$next[3:0]$11191 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r2__data_o$next[3:0]$11204 \dest12__data_i + assign $2\r2__data_o$next[3:0]$11188 \dest12__data_i case - assign $2\r2__data_o$next[3:0]$11204 4'0000 + assign $2\r2__data_o$next[3:0]$11188 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r2__data_o$next[3:0]$11205 \dest22__data_i + assign $3\r2__data_o$next[3:0]$11189 \dest22__data_i case - assign $3\r2__data_o$next[3:0]$11205 $2\r2__data_o$next[3:0]$11204 + assign $3\r2__data_o$next[3:0]$11189 $2\r2__data_o$next[3:0]$11188 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r2__data_o$next[3:0]$11206 \w2__data_i + assign $4\r2__data_o$next[3:0]$11190 \w2__data_i case - assign $4\r2__data_o$next[3:0]$11206 $3\r2__data_o$next[3:0]$11205 + assign $4\r2__data_o$next[3:0]$11190 $3\r2__data_o$next[3:0]$11189 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r2__data_o$next[3:0]$11207 \reg + assign $5\r2__data_o$next[3:0]$11191 \reg case - assign $5\r2__data_o$next[3:0]$11207 $4\r2__data_o$next[3:0]$11206 + assign $5\r2__data_o$next[3:0]$11191 $4\r2__data_o$next[3:0]$11190 end case - assign $1\r2__data_o$next[3:0]$11203 4'0000 + assign $1\r2__data_o$next[3:0]$11187 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r2__data_o$next[3:0]$11208 4'0000 + assign $6\r2__data_o$next[3:0]$11192 4'0000 case - assign $6\r2__data_o$next[3:0]$11208 $1\r2__data_o$next[3:0]$11203 + assign $6\r2__data_o$next[3:0]$11192 $1\r2__data_o$next[3:0]$11187 end sync always - update \r2__data_o$next $0\r2__data_o$next[3:0]$11202 + update \r2__data_o$next $0\r2__data_o$next[3:0]$11186 end - attribute \src "libresoc.v:180026.3-180055.6" - process $proc$libresoc.v:180026$11209 + attribute \src "libresoc.v:181334.3-181363.6" + process $proc$libresoc.v:181334$11193 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11210 $1\wr_detect$13[0:0]$11211 - attribute \src "libresoc.v:180027.5-180027.29" + assign $0\wr_detect$13[0:0]$11194 $1\wr_detect$13[0:0]$11195 + attribute \src "libresoc.v:181335.5-181335.29" switch \initial - attribute \src "libresoc.v:180027.9-180027.17" + attribute \src "libresoc.v:181335.9-181335.17" case 1'1 case end @@ -366907,206 +338277,206 @@ module \reg_2 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11211 $4\wr_detect$13[0:0]$11214 + assign $1\wr_detect$13[0:0]$11195 $4\wr_detect$13[0:0]$11198 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11212 1'1 + assign $2\wr_detect$13[0:0]$11196 1'1 case - assign $2\wr_detect$13[0:0]$11212 1'0 + assign $2\wr_detect$13[0:0]$11196 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11213 1'1 + assign $3\wr_detect$13[0:0]$11197 1'1 case - assign $3\wr_detect$13[0:0]$11213 $2\wr_detect$13[0:0]$11212 + assign $3\wr_detect$13[0:0]$11197 $2\wr_detect$13[0:0]$11196 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11214 1'1 + assign $4\wr_detect$13[0:0]$11198 1'1 case - assign $4\wr_detect$13[0:0]$11214 $3\wr_detect$13[0:0]$11213 + assign $4\wr_detect$13[0:0]$11198 $3\wr_detect$13[0:0]$11197 end case - assign $1\wr_detect$13[0:0]$11211 1'0 + assign $1\wr_detect$13[0:0]$11195 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11210 + update \wr_detect$13 $0\wr_detect$13[0:0]$11194 end - connect \$9 $not$libresoc.v:179589$11117_Y - connect \$12 $not$libresoc.v:179590$11118_Y - connect \$15 $not$libresoc.v:179591$11119_Y - connect \$1 $not$libresoc.v:179592$11120_Y - connect \$3 $not$libresoc.v:179593$11121_Y - connect \$6 $not$libresoc.v:179594$11122_Y + connect \$9 $not$libresoc.v:180897$11101_Y + connect \$12 $not$libresoc.v:180898$11102_Y + connect \$15 $not$libresoc.v:180899$11103_Y + connect \$1 $not$libresoc.v:180900$11104_Y + connect \$3 $not$libresoc.v:180901$11105_Y + connect \$6 $not$libresoc.v:180902$11106_Y end -attribute \src "libresoc.v:180060.1-180505.10" +attribute \src "libresoc.v:181368.1-181813.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.xer.reg_2" attribute \generator "nMigen" module \reg_2$134 - attribute \src "libresoc.v:180061.7-180061.20" + attribute \src "libresoc.v:181369.7-181369.20" wire $0\initial[0:0] - attribute \src "libresoc.v:180390.3-180435.6" - wire width 2 $0\r2__data_o$next[1:0]$11275 - attribute \src "libresoc.v:180136.3-180137.37" + attribute \src "libresoc.v:181698.3-181743.6" + wire width 2 $0\r2__data_o$next[1:0]$11259 + attribute \src "libresoc.v:181444.3-181445.37" wire width 2 $0\r2__data_o[1:0] - attribute \src "libresoc.v:180472.3-180504.6" - wire width 2 $0\reg$next[1:0]$11291 - attribute \src "libresoc.v:180134.3-180135.25" + attribute \src "libresoc.v:181780.3-181812.6" + wire width 2 $0\reg$next[1:0]$11275 + attribute \src "libresoc.v:181442.3-181443.25" wire width 2 $0\reg[1:0] - attribute \src "libresoc.v:180144.3-180189.6" - wire width 2 $0\src12__data_o$next[1:0]$11233 - attribute \src "libresoc.v:180142.3-180143.43" + attribute \src "libresoc.v:181452.3-181497.6" + wire width 2 $0\src12__data_o$next[1:0]$11217 + attribute \src "libresoc.v:181450.3-181451.43" wire width 2 $0\src12__data_o[1:0] - attribute \src "libresoc.v:180226.3-180271.6" - wire width 2 $0\src22__data_o$next[1:0]$11243 - attribute \src "libresoc.v:180140.3-180141.43" + attribute \src "libresoc.v:181534.3-181579.6" + wire width 2 $0\src22__data_o$next[1:0]$11227 + attribute \src "libresoc.v:181448.3-181449.43" wire width 2 $0\src22__data_o[1:0] - attribute \src "libresoc.v:180308.3-180353.6" - wire width 2 $0\src32__data_o$next[1:0]$11259 - attribute \src "libresoc.v:180138.3-180139.43" + attribute \src "libresoc.v:181616.3-181661.6" + wire width 2 $0\src32__data_o$next[1:0]$11243 + attribute \src "libresoc.v:181446.3-181447.43" wire width 2 $0\src32__data_o[1:0] - attribute \src "libresoc.v:180436.3-180471.6" - wire $0\wr_detect$10[0:0]$11284 - attribute \src "libresoc.v:180272.3-180307.6" - wire $0\wr_detect$4[0:0]$11252 - attribute \src "libresoc.v:180354.3-180389.6" - wire $0\wr_detect$7[0:0]$11268 - attribute \src "libresoc.v:180190.3-180225.6" + attribute \src "libresoc.v:181744.3-181779.6" + wire $0\wr_detect$10[0:0]$11268 + attribute \src "libresoc.v:181580.3-181615.6" + wire $0\wr_detect$4[0:0]$11236 + attribute \src "libresoc.v:181662.3-181697.6" + wire $0\wr_detect$7[0:0]$11252 + attribute \src "libresoc.v:181498.3-181533.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:180390.3-180435.6" - wire width 2 $1\r2__data_o$next[1:0]$11276 - attribute \src "libresoc.v:180088.13-180088.30" + attribute \src "libresoc.v:181698.3-181743.6" + wire width 2 $1\r2__data_o$next[1:0]$11260 + attribute \src "libresoc.v:181396.13-181396.30" wire width 2 $1\r2__data_o[1:0] - attribute \src "libresoc.v:180472.3-180504.6" - wire width 2 $1\reg$next[1:0]$11292 - attribute \src "libresoc.v:180094.13-180094.25" + attribute \src "libresoc.v:181780.3-181812.6" + wire width 2 $1\reg$next[1:0]$11276 + attribute \src "libresoc.v:181402.13-181402.25" wire width 2 $1\reg[1:0] - attribute \src "libresoc.v:180144.3-180189.6" - wire width 2 $1\src12__data_o$next[1:0]$11234 - attribute \src "libresoc.v:180099.13-180099.33" + attribute \src "libresoc.v:181452.3-181497.6" + wire width 2 $1\src12__data_o$next[1:0]$11218 + attribute \src "libresoc.v:181407.13-181407.33" wire width 2 $1\src12__data_o[1:0] - attribute \src "libresoc.v:180226.3-180271.6" - wire width 2 $1\src22__data_o$next[1:0]$11244 - attribute \src "libresoc.v:180106.13-180106.33" + attribute \src "libresoc.v:181534.3-181579.6" + wire width 2 $1\src22__data_o$next[1:0]$11228 + attribute \src "libresoc.v:181414.13-181414.33" wire width 2 $1\src22__data_o[1:0] - attribute \src "libresoc.v:180308.3-180353.6" - wire width 2 $1\src32__data_o$next[1:0]$11260 - attribute \src "libresoc.v:180113.13-180113.33" + attribute \src "libresoc.v:181616.3-181661.6" + wire width 2 $1\src32__data_o$next[1:0]$11244 + attribute \src "libresoc.v:181421.13-181421.33" wire width 2 $1\src32__data_o[1:0] - attribute \src "libresoc.v:180436.3-180471.6" - wire $1\wr_detect$10[0:0]$11285 - attribute \src "libresoc.v:180272.3-180307.6" - wire $1\wr_detect$4[0:0]$11253 - attribute \src "libresoc.v:180354.3-180389.6" - wire $1\wr_detect$7[0:0]$11269 - attribute \src "libresoc.v:180190.3-180225.6" + attribute \src "libresoc.v:181744.3-181779.6" + wire $1\wr_detect$10[0:0]$11269 + attribute \src "libresoc.v:181580.3-181615.6" + wire $1\wr_detect$4[0:0]$11237 + attribute \src "libresoc.v:181662.3-181697.6" + wire $1\wr_detect$7[0:0]$11253 + attribute \src "libresoc.v:181498.3-181533.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:180390.3-180435.6" - wire width 2 $2\r2__data_o$next[1:0]$11277 - attribute \src "libresoc.v:180472.3-180504.6" - wire width 2 $2\reg$next[1:0]$11293 - attribute \src "libresoc.v:180144.3-180189.6" - wire width 2 $2\src12__data_o$next[1:0]$11235 - attribute \src "libresoc.v:180226.3-180271.6" - wire width 2 $2\src22__data_o$next[1:0]$11245 - attribute \src "libresoc.v:180308.3-180353.6" - wire width 2 $2\src32__data_o$next[1:0]$11261 - attribute \src "libresoc.v:180436.3-180471.6" - wire $2\wr_detect$10[0:0]$11286 - attribute \src "libresoc.v:180272.3-180307.6" - wire $2\wr_detect$4[0:0]$11254 - attribute \src "libresoc.v:180354.3-180389.6" - wire $2\wr_detect$7[0:0]$11270 - attribute \src "libresoc.v:180190.3-180225.6" + attribute \src "libresoc.v:181698.3-181743.6" + wire width 2 $2\r2__data_o$next[1:0]$11261 + attribute \src "libresoc.v:181780.3-181812.6" + wire width 2 $2\reg$next[1:0]$11277 + attribute \src "libresoc.v:181452.3-181497.6" + wire width 2 $2\src12__data_o$next[1:0]$11219 + attribute \src "libresoc.v:181534.3-181579.6" + wire width 2 $2\src22__data_o$next[1:0]$11229 + attribute \src "libresoc.v:181616.3-181661.6" + wire width 2 $2\src32__data_o$next[1:0]$11245 + attribute \src "libresoc.v:181744.3-181779.6" + wire $2\wr_detect$10[0:0]$11270 + attribute \src "libresoc.v:181580.3-181615.6" + wire $2\wr_detect$4[0:0]$11238 + attribute \src "libresoc.v:181662.3-181697.6" + wire $2\wr_detect$7[0:0]$11254 + attribute \src "libresoc.v:181498.3-181533.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:180390.3-180435.6" - wire width 2 $3\r2__data_o$next[1:0]$11278 - attribute \src "libresoc.v:180472.3-180504.6" - wire width 2 $3\reg$next[1:0]$11294 - attribute \src "libresoc.v:180144.3-180189.6" - wire width 2 $3\src12__data_o$next[1:0]$11236 - attribute \src "libresoc.v:180226.3-180271.6" - wire width 2 $3\src22__data_o$next[1:0]$11246 - attribute \src "libresoc.v:180308.3-180353.6" - wire width 2 $3\src32__data_o$next[1:0]$11262 - attribute \src "libresoc.v:180436.3-180471.6" - wire $3\wr_detect$10[0:0]$11287 - attribute \src "libresoc.v:180272.3-180307.6" - wire $3\wr_detect$4[0:0]$11255 - attribute \src "libresoc.v:180354.3-180389.6" - wire $3\wr_detect$7[0:0]$11271 - attribute \src "libresoc.v:180190.3-180225.6" + attribute \src "libresoc.v:181698.3-181743.6" + wire width 2 $3\r2__data_o$next[1:0]$11262 + attribute \src "libresoc.v:181780.3-181812.6" + wire width 2 $3\reg$next[1:0]$11278 + attribute \src "libresoc.v:181452.3-181497.6" + wire width 2 $3\src12__data_o$next[1:0]$11220 + attribute \src "libresoc.v:181534.3-181579.6" + wire width 2 $3\src22__data_o$next[1:0]$11230 + attribute \src "libresoc.v:181616.3-181661.6" + wire width 2 $3\src32__data_o$next[1:0]$11246 + attribute \src "libresoc.v:181744.3-181779.6" + wire $3\wr_detect$10[0:0]$11271 + attribute \src "libresoc.v:181580.3-181615.6" + wire $3\wr_detect$4[0:0]$11239 + attribute \src "libresoc.v:181662.3-181697.6" + wire $3\wr_detect$7[0:0]$11255 + attribute \src "libresoc.v:181498.3-181533.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:180390.3-180435.6" - wire width 2 $4\r2__data_o$next[1:0]$11279 - attribute \src "libresoc.v:180472.3-180504.6" - wire width 2 $4\reg$next[1:0]$11295 - attribute \src "libresoc.v:180144.3-180189.6" - wire width 2 $4\src12__data_o$next[1:0]$11237 - attribute \src "libresoc.v:180226.3-180271.6" - wire width 2 $4\src22__data_o$next[1:0]$11247 - attribute \src "libresoc.v:180308.3-180353.6" - wire width 2 $4\src32__data_o$next[1:0]$11263 - attribute \src "libresoc.v:180436.3-180471.6" - wire $4\wr_detect$10[0:0]$11288 - attribute \src "libresoc.v:180272.3-180307.6" - wire $4\wr_detect$4[0:0]$11256 - attribute \src "libresoc.v:180354.3-180389.6" - wire $4\wr_detect$7[0:0]$11272 - attribute \src "libresoc.v:180190.3-180225.6" + attribute \src "libresoc.v:181698.3-181743.6" + wire width 2 $4\r2__data_o$next[1:0]$11263 + attribute \src "libresoc.v:181780.3-181812.6" + wire width 2 $4\reg$next[1:0]$11279 + attribute \src "libresoc.v:181452.3-181497.6" + wire width 2 $4\src12__data_o$next[1:0]$11221 + attribute \src "libresoc.v:181534.3-181579.6" + wire width 2 $4\src22__data_o$next[1:0]$11231 + attribute \src "libresoc.v:181616.3-181661.6" + wire width 2 $4\src32__data_o$next[1:0]$11247 + attribute \src "libresoc.v:181744.3-181779.6" + wire $4\wr_detect$10[0:0]$11272 + attribute \src "libresoc.v:181580.3-181615.6" + wire $4\wr_detect$4[0:0]$11240 + attribute \src "libresoc.v:181662.3-181697.6" + wire $4\wr_detect$7[0:0]$11256 + attribute \src "libresoc.v:181498.3-181533.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:180390.3-180435.6" - wire width 2 $5\r2__data_o$next[1:0]$11280 - attribute \src "libresoc.v:180472.3-180504.6" - wire width 2 $5\reg$next[1:0]$11296 - attribute \src "libresoc.v:180144.3-180189.6" - wire width 2 $5\src12__data_o$next[1:0]$11238 - attribute \src "libresoc.v:180226.3-180271.6" - wire width 2 $5\src22__data_o$next[1:0]$11248 - attribute \src "libresoc.v:180308.3-180353.6" - wire width 2 $5\src32__data_o$next[1:0]$11264 - attribute \src "libresoc.v:180436.3-180471.6" - wire $5\wr_detect$10[0:0]$11289 - attribute \src "libresoc.v:180272.3-180307.6" - wire $5\wr_detect$4[0:0]$11257 - attribute \src "libresoc.v:180354.3-180389.6" - wire $5\wr_detect$7[0:0]$11273 - attribute \src "libresoc.v:180190.3-180225.6" + attribute \src "libresoc.v:181698.3-181743.6" + wire width 2 $5\r2__data_o$next[1:0]$11264 + attribute \src "libresoc.v:181780.3-181812.6" + wire width 2 $5\reg$next[1:0]$11280 + attribute \src "libresoc.v:181452.3-181497.6" + wire width 2 $5\src12__data_o$next[1:0]$11222 + attribute \src "libresoc.v:181534.3-181579.6" + wire width 2 $5\src22__data_o$next[1:0]$11232 + attribute \src "libresoc.v:181616.3-181661.6" + wire width 2 $5\src32__data_o$next[1:0]$11248 + attribute \src "libresoc.v:181744.3-181779.6" + wire $5\wr_detect$10[0:0]$11273 + attribute \src "libresoc.v:181580.3-181615.6" + wire $5\wr_detect$4[0:0]$11241 + attribute \src "libresoc.v:181662.3-181697.6" + wire $5\wr_detect$7[0:0]$11257 + attribute \src "libresoc.v:181498.3-181533.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:180390.3-180435.6" - wire width 2 $6\r2__data_o$next[1:0]$11281 - attribute \src "libresoc.v:180144.3-180189.6" - wire width 2 $6\src12__data_o$next[1:0]$11239 - attribute \src "libresoc.v:180226.3-180271.6" - wire width 2 $6\src22__data_o$next[1:0]$11249 - attribute \src "libresoc.v:180308.3-180353.6" - wire width 2 $6\src32__data_o$next[1:0]$11265 - attribute \src "libresoc.v:180390.3-180435.6" - wire width 2 $7\r2__data_o$next[1:0]$11282 - attribute \src "libresoc.v:180144.3-180189.6" - wire width 2 $7\src12__data_o$next[1:0]$11240 - attribute \src "libresoc.v:180226.3-180271.6" - wire width 2 $7\src22__data_o$next[1:0]$11250 - attribute \src "libresoc.v:180308.3-180353.6" - wire width 2 $7\src32__data_o$next[1:0]$11266 - attribute \src "libresoc.v:180130.17-180130.104" - wire $not$libresoc.v:180130$11223_Y - attribute \src "libresoc.v:180131.17-180131.100" - wire $not$libresoc.v:180131$11224_Y - attribute \src "libresoc.v:180132.17-180132.103" - wire $not$libresoc.v:180132$11225_Y - attribute \src "libresoc.v:180133.17-180133.103" - wire $not$libresoc.v:180133$11226_Y + attribute \src "libresoc.v:181698.3-181743.6" + wire width 2 $6\r2__data_o$next[1:0]$11265 + attribute \src "libresoc.v:181452.3-181497.6" + wire width 2 $6\src12__data_o$next[1:0]$11223 + attribute \src "libresoc.v:181534.3-181579.6" + wire width 2 $6\src22__data_o$next[1:0]$11233 + attribute \src "libresoc.v:181616.3-181661.6" + wire width 2 $6\src32__data_o$next[1:0]$11249 + attribute \src "libresoc.v:181698.3-181743.6" + wire width 2 $7\r2__data_o$next[1:0]$11266 + attribute \src "libresoc.v:181452.3-181497.6" + wire width 2 $7\src12__data_o$next[1:0]$11224 + attribute \src "libresoc.v:181534.3-181579.6" + wire width 2 $7\src22__data_o$next[1:0]$11234 + attribute \src "libresoc.v:181616.3-181661.6" + wire width 2 $7\src32__data_o$next[1:0]$11250 + attribute \src "libresoc.v:181438.17-181438.104" + wire $not$libresoc.v:181438$11207_Y + attribute \src "libresoc.v:181439.17-181439.100" + wire $not$libresoc.v:181439$11208_Y + attribute \src "libresoc.v:181440.17-181440.103" + wire $not$libresoc.v:181440$11209_Y + attribute \src "libresoc.v:181441.17-181441.103" + wire $not$libresoc.v:181441$11210_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -367115,9 +338485,9 @@ module \reg_2$134 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 18 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 9 \dest12__data_i @@ -367131,7 +338501,7 @@ module \reg_2$134 wire width 2 input 13 \dest32__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest32__wen - attribute \src "libresoc.v:180061.7-180061.15" + attribute \src "libresoc.v:181369.7-181369.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 output 14 \r2__data_o @@ -367174,129 +338544,129 @@ module \reg_2$134 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180130$11223 + cell $not $not$libresoc.v:181438$11207 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:180130$11223_Y + connect \Y $not$libresoc.v:181438$11207_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180131$11224 + cell $not $not$libresoc.v:181439$11208 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:180131$11224_Y + connect \Y $not$libresoc.v:181439$11208_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180132$11225 + cell $not $not$libresoc.v:181440$11209 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:180132$11225_Y + connect \Y $not$libresoc.v:181440$11209_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180133$11226 + cell $not $not$libresoc.v:181441$11210 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:180133$11226_Y + connect \Y $not$libresoc.v:181441$11210_Y end - attribute \src "libresoc.v:180061.7-180061.20" - process $proc$libresoc.v:180061$11297 + attribute \src "libresoc.v:181369.7-181369.20" + process $proc$libresoc.v:181369$11281 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:180088.13-180088.30" - process $proc$libresoc.v:180088$11298 + attribute \src "libresoc.v:181396.13-181396.30" + process $proc$libresoc.v:181396$11282 assign { } { } assign $1\r2__data_o[1:0] 2'00 sync always sync init update \r2__data_o $1\r2__data_o[1:0] end - attribute \src "libresoc.v:180094.13-180094.25" - process $proc$libresoc.v:180094$11299 + attribute \src "libresoc.v:181402.13-181402.25" + process $proc$libresoc.v:181402$11283 assign { } { } assign $1\reg[1:0] 2'00 sync always sync init update \reg $1\reg[1:0] end - attribute \src "libresoc.v:180099.13-180099.33" - process $proc$libresoc.v:180099$11300 + attribute \src "libresoc.v:181407.13-181407.33" + process $proc$libresoc.v:181407$11284 assign { } { } assign $1\src12__data_o[1:0] 2'00 sync always sync init update \src12__data_o $1\src12__data_o[1:0] end - attribute \src "libresoc.v:180106.13-180106.33" - process $proc$libresoc.v:180106$11301 + attribute \src "libresoc.v:181414.13-181414.33" + process $proc$libresoc.v:181414$11285 assign { } { } assign $1\src22__data_o[1:0] 2'00 sync always sync init update \src22__data_o $1\src22__data_o[1:0] end - attribute \src "libresoc.v:180113.13-180113.33" - process $proc$libresoc.v:180113$11302 + attribute \src "libresoc.v:181421.13-181421.33" + process $proc$libresoc.v:181421$11286 assign { } { } assign $1\src32__data_o[1:0] 2'00 sync always sync init update \src32__data_o $1\src32__data_o[1:0] end - attribute \src "libresoc.v:180134.3-180135.25" - process $proc$libresoc.v:180134$11227 + attribute \src "libresoc.v:181442.3-181443.25" + process $proc$libresoc.v:181442$11211 assign { } { } assign $0\reg[1:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[1:0] end - attribute \src "libresoc.v:180136.3-180137.37" - process $proc$libresoc.v:180136$11228 + attribute \src "libresoc.v:181444.3-181445.37" + process $proc$libresoc.v:181444$11212 assign { } { } assign $0\r2__data_o[1:0] \r2__data_o$next sync posedge \coresync_clk update \r2__data_o $0\r2__data_o[1:0] end - attribute \src "libresoc.v:180138.3-180139.43" - process $proc$libresoc.v:180138$11229 + attribute \src "libresoc.v:181446.3-181447.43" + process $proc$libresoc.v:181446$11213 assign { } { } assign $0\src32__data_o[1:0] \src32__data_o$next sync posedge \coresync_clk update \src32__data_o $0\src32__data_o[1:0] end - attribute \src "libresoc.v:180140.3-180141.43" - process $proc$libresoc.v:180140$11230 + attribute \src "libresoc.v:181448.3-181449.43" + process $proc$libresoc.v:181448$11214 assign { } { } assign $0\src22__data_o[1:0] \src22__data_o$next sync posedge \coresync_clk update \src22__data_o $0\src22__data_o[1:0] end - attribute \src "libresoc.v:180142.3-180143.43" - process $proc$libresoc.v:180142$11231 + attribute \src "libresoc.v:181450.3-181451.43" + process $proc$libresoc.v:181450$11215 assign { } { } assign $0\src12__data_o[1:0] \src12__data_o$next sync posedge \coresync_clk update \src12__data_o $0\src12__data_o[1:0] end - attribute \src "libresoc.v:180144.3-180189.6" - process $proc$libresoc.v:180144$11232 + attribute \src "libresoc.v:181452.3-181497.6" + process $proc$libresoc.v:181452$11216 assign { } { } assign { } { } assign { } { } - assign $0\src12__data_o$next[1:0]$11233 $7\src12__data_o$next[1:0]$11240 - attribute \src "libresoc.v:180145.5-180145.29" + assign $0\src12__data_o$next[1:0]$11217 $7\src12__data_o$next[1:0]$11224 + attribute \src "libresoc.v:181453.5-181453.29" switch \initial - attribute \src "libresoc.v:180145.9-180145.17" + attribute \src "libresoc.v:181453.9-181453.17" case 1'1 case end @@ -367309,75 +338679,75 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\src12__data_o$next[1:0]$11234 $6\src12__data_o$next[1:0]$11239 + assign $1\src12__data_o$next[1:0]$11218 $6\src12__data_o$next[1:0]$11223 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src12__data_o$next[1:0]$11235 \dest12__data_i + assign $2\src12__data_o$next[1:0]$11219 \dest12__data_i case - assign $2\src12__data_o$next[1:0]$11235 2'00 + assign $2\src12__data_o$next[1:0]$11219 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src12__data_o$next[1:0]$11236 \dest22__data_i + assign $3\src12__data_o$next[1:0]$11220 \dest22__data_i case - assign $3\src12__data_o$next[1:0]$11236 $2\src12__data_o$next[1:0]$11235 + assign $3\src12__data_o$next[1:0]$11220 $2\src12__data_o$next[1:0]$11219 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src12__data_o$next[1:0]$11237 \dest32__data_i + assign $4\src12__data_o$next[1:0]$11221 \dest32__data_i case - assign $4\src12__data_o$next[1:0]$11237 $3\src12__data_o$next[1:0]$11236 + assign $4\src12__data_o$next[1:0]$11221 $3\src12__data_o$next[1:0]$11220 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src12__data_o$next[1:0]$11238 \w2__data_i + assign $5\src12__data_o$next[1:0]$11222 \w2__data_i case - assign $5\src12__data_o$next[1:0]$11238 $4\src12__data_o$next[1:0]$11237 + assign $5\src12__data_o$next[1:0]$11222 $4\src12__data_o$next[1:0]$11221 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src12__data_o$next[1:0]$11239 \reg + assign $6\src12__data_o$next[1:0]$11223 \reg case - assign $6\src12__data_o$next[1:0]$11239 $5\src12__data_o$next[1:0]$11238 + assign $6\src12__data_o$next[1:0]$11223 $5\src12__data_o$next[1:0]$11222 end case - assign $1\src12__data_o$next[1:0]$11234 2'00 + assign $1\src12__data_o$next[1:0]$11218 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src12__data_o$next[1:0]$11240 2'00 + assign $7\src12__data_o$next[1:0]$11224 2'00 case - assign $7\src12__data_o$next[1:0]$11240 $1\src12__data_o$next[1:0]$11234 + assign $7\src12__data_o$next[1:0]$11224 $1\src12__data_o$next[1:0]$11218 end sync always - update \src12__data_o$next $0\src12__data_o$next[1:0]$11233 + update \src12__data_o$next $0\src12__data_o$next[1:0]$11217 end - attribute \src "libresoc.v:180190.3-180225.6" - process $proc$libresoc.v:180190$11241 + attribute \src "libresoc.v:181498.3-181533.6" + process $proc$libresoc.v:181498$11225 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:180191.5-180191.29" + attribute \src "libresoc.v:181499.5-181499.29" switch \initial - attribute \src "libresoc.v:180191.9-180191.17" + attribute \src "libresoc.v:181499.9-181499.17" case 1'1 case end @@ -367433,15 +338803,15 @@ module \reg_2$134 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:180226.3-180271.6" - process $proc$libresoc.v:180226$11242 + attribute \src "libresoc.v:181534.3-181579.6" + process $proc$libresoc.v:181534$11226 assign { } { } assign { } { } assign { } { } - assign $0\src22__data_o$next[1:0]$11243 $7\src22__data_o$next[1:0]$11250 - attribute \src "libresoc.v:180227.5-180227.29" + assign $0\src22__data_o$next[1:0]$11227 $7\src22__data_o$next[1:0]$11234 + attribute \src "libresoc.v:181535.5-181535.29" switch \initial - attribute \src "libresoc.v:180227.9-180227.17" + attribute \src "libresoc.v:181535.9-181535.17" case 1'1 case end @@ -367454,75 +338824,75 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\src22__data_o$next[1:0]$11244 $6\src22__data_o$next[1:0]$11249 + assign $1\src22__data_o$next[1:0]$11228 $6\src22__data_o$next[1:0]$11233 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src22__data_o$next[1:0]$11245 \dest12__data_i + assign $2\src22__data_o$next[1:0]$11229 \dest12__data_i case - assign $2\src22__data_o$next[1:0]$11245 2'00 + assign $2\src22__data_o$next[1:0]$11229 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src22__data_o$next[1:0]$11246 \dest22__data_i + assign $3\src22__data_o$next[1:0]$11230 \dest22__data_i case - assign $3\src22__data_o$next[1:0]$11246 $2\src22__data_o$next[1:0]$11245 + assign $3\src22__data_o$next[1:0]$11230 $2\src22__data_o$next[1:0]$11229 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src22__data_o$next[1:0]$11247 \dest32__data_i + assign $4\src22__data_o$next[1:0]$11231 \dest32__data_i case - assign $4\src22__data_o$next[1:0]$11247 $3\src22__data_o$next[1:0]$11246 + assign $4\src22__data_o$next[1:0]$11231 $3\src22__data_o$next[1:0]$11230 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src22__data_o$next[1:0]$11248 \w2__data_i + assign $5\src22__data_o$next[1:0]$11232 \w2__data_i case - assign $5\src22__data_o$next[1:0]$11248 $4\src22__data_o$next[1:0]$11247 + assign $5\src22__data_o$next[1:0]$11232 $4\src22__data_o$next[1:0]$11231 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src22__data_o$next[1:0]$11249 \reg + assign $6\src22__data_o$next[1:0]$11233 \reg case - assign $6\src22__data_o$next[1:0]$11249 $5\src22__data_o$next[1:0]$11248 + assign $6\src22__data_o$next[1:0]$11233 $5\src22__data_o$next[1:0]$11232 end case - assign $1\src22__data_o$next[1:0]$11244 2'00 + assign $1\src22__data_o$next[1:0]$11228 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src22__data_o$next[1:0]$11250 2'00 + assign $7\src22__data_o$next[1:0]$11234 2'00 case - assign $7\src22__data_o$next[1:0]$11250 $1\src22__data_o$next[1:0]$11244 + assign $7\src22__data_o$next[1:0]$11234 $1\src22__data_o$next[1:0]$11228 end sync always - update \src22__data_o$next $0\src22__data_o$next[1:0]$11243 + update \src22__data_o$next $0\src22__data_o$next[1:0]$11227 end - attribute \src "libresoc.v:180272.3-180307.6" - process $proc$libresoc.v:180272$11251 + attribute \src "libresoc.v:181580.3-181615.6" + process $proc$libresoc.v:181580$11235 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11252 $1\wr_detect$4[0:0]$11253 - attribute \src "libresoc.v:180273.5-180273.29" + assign $0\wr_detect$4[0:0]$11236 $1\wr_detect$4[0:0]$11237 + attribute \src "libresoc.v:181581.5-181581.29" switch \initial - attribute \src "libresoc.v:180273.9-180273.17" + attribute \src "libresoc.v:181581.9-181581.17" case 1'1 case end @@ -367535,58 +338905,58 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11253 $5\wr_detect$4[0:0]$11257 + assign $1\wr_detect$4[0:0]$11237 $5\wr_detect$4[0:0]$11241 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11254 1'1 + assign $2\wr_detect$4[0:0]$11238 1'1 case - assign $2\wr_detect$4[0:0]$11254 1'0 + assign $2\wr_detect$4[0:0]$11238 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11255 1'1 + assign $3\wr_detect$4[0:0]$11239 1'1 case - assign $3\wr_detect$4[0:0]$11255 $2\wr_detect$4[0:0]$11254 + assign $3\wr_detect$4[0:0]$11239 $2\wr_detect$4[0:0]$11238 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11256 1'1 + assign $4\wr_detect$4[0:0]$11240 1'1 case - assign $4\wr_detect$4[0:0]$11256 $3\wr_detect$4[0:0]$11255 + assign $4\wr_detect$4[0:0]$11240 $3\wr_detect$4[0:0]$11239 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$11257 1'1 + assign $5\wr_detect$4[0:0]$11241 1'1 case - assign $5\wr_detect$4[0:0]$11257 $4\wr_detect$4[0:0]$11256 + assign $5\wr_detect$4[0:0]$11241 $4\wr_detect$4[0:0]$11240 end case - assign $1\wr_detect$4[0:0]$11253 1'0 + assign $1\wr_detect$4[0:0]$11237 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11252 + update \wr_detect$4 $0\wr_detect$4[0:0]$11236 end - attribute \src "libresoc.v:180308.3-180353.6" - process $proc$libresoc.v:180308$11258 + attribute \src "libresoc.v:181616.3-181661.6" + process $proc$libresoc.v:181616$11242 assign { } { } assign { } { } assign { } { } - assign $0\src32__data_o$next[1:0]$11259 $7\src32__data_o$next[1:0]$11266 - attribute \src "libresoc.v:180309.5-180309.29" + assign $0\src32__data_o$next[1:0]$11243 $7\src32__data_o$next[1:0]$11250 + attribute \src "libresoc.v:181617.5-181617.29" switch \initial - attribute \src "libresoc.v:180309.9-180309.17" + attribute \src "libresoc.v:181617.9-181617.17" case 1'1 case end @@ -367599,75 +338969,75 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\src32__data_o$next[1:0]$11260 $6\src32__data_o$next[1:0]$11265 + assign $1\src32__data_o$next[1:0]$11244 $6\src32__data_o$next[1:0]$11249 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src32__data_o$next[1:0]$11261 \dest12__data_i + assign $2\src32__data_o$next[1:0]$11245 \dest12__data_i case - assign $2\src32__data_o$next[1:0]$11261 2'00 + assign $2\src32__data_o$next[1:0]$11245 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src32__data_o$next[1:0]$11262 \dest22__data_i + assign $3\src32__data_o$next[1:0]$11246 \dest22__data_i case - assign $3\src32__data_o$next[1:0]$11262 $2\src32__data_o$next[1:0]$11261 + assign $3\src32__data_o$next[1:0]$11246 $2\src32__data_o$next[1:0]$11245 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src32__data_o$next[1:0]$11263 \dest32__data_i + assign $4\src32__data_o$next[1:0]$11247 \dest32__data_i case - assign $4\src32__data_o$next[1:0]$11263 $3\src32__data_o$next[1:0]$11262 + assign $4\src32__data_o$next[1:0]$11247 $3\src32__data_o$next[1:0]$11246 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src32__data_o$next[1:0]$11264 \w2__data_i + assign $5\src32__data_o$next[1:0]$11248 \w2__data_i case - assign $5\src32__data_o$next[1:0]$11264 $4\src32__data_o$next[1:0]$11263 + assign $5\src32__data_o$next[1:0]$11248 $4\src32__data_o$next[1:0]$11247 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src32__data_o$next[1:0]$11265 \reg + assign $6\src32__data_o$next[1:0]$11249 \reg case - assign $6\src32__data_o$next[1:0]$11265 $5\src32__data_o$next[1:0]$11264 + assign $6\src32__data_o$next[1:0]$11249 $5\src32__data_o$next[1:0]$11248 end case - assign $1\src32__data_o$next[1:0]$11260 2'00 + assign $1\src32__data_o$next[1:0]$11244 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\src32__data_o$next[1:0]$11266 2'00 + assign $7\src32__data_o$next[1:0]$11250 2'00 case - assign $7\src32__data_o$next[1:0]$11266 $1\src32__data_o$next[1:0]$11260 + assign $7\src32__data_o$next[1:0]$11250 $1\src32__data_o$next[1:0]$11244 end sync always - update \src32__data_o$next $0\src32__data_o$next[1:0]$11259 + update \src32__data_o$next $0\src32__data_o$next[1:0]$11243 end - attribute \src "libresoc.v:180354.3-180389.6" - process $proc$libresoc.v:180354$11267 + attribute \src "libresoc.v:181662.3-181697.6" + process $proc$libresoc.v:181662$11251 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11268 $1\wr_detect$7[0:0]$11269 - attribute \src "libresoc.v:180355.5-180355.29" + assign $0\wr_detect$7[0:0]$11252 $1\wr_detect$7[0:0]$11253 + attribute \src "libresoc.v:181663.5-181663.29" switch \initial - attribute \src "libresoc.v:180355.9-180355.17" + attribute \src "libresoc.v:181663.9-181663.17" case 1'1 case end @@ -367680,58 +339050,58 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11269 $5\wr_detect$7[0:0]$11273 + assign $1\wr_detect$7[0:0]$11253 $5\wr_detect$7[0:0]$11257 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11270 1'1 + assign $2\wr_detect$7[0:0]$11254 1'1 case - assign $2\wr_detect$7[0:0]$11270 1'0 + assign $2\wr_detect$7[0:0]$11254 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11271 1'1 + assign $3\wr_detect$7[0:0]$11255 1'1 case - assign $3\wr_detect$7[0:0]$11271 $2\wr_detect$7[0:0]$11270 + assign $3\wr_detect$7[0:0]$11255 $2\wr_detect$7[0:0]$11254 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11272 1'1 + assign $4\wr_detect$7[0:0]$11256 1'1 case - assign $4\wr_detect$7[0:0]$11272 $3\wr_detect$7[0:0]$11271 + assign $4\wr_detect$7[0:0]$11256 $3\wr_detect$7[0:0]$11255 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$11273 1'1 + assign $5\wr_detect$7[0:0]$11257 1'1 case - assign $5\wr_detect$7[0:0]$11273 $4\wr_detect$7[0:0]$11272 + assign $5\wr_detect$7[0:0]$11257 $4\wr_detect$7[0:0]$11256 end case - assign $1\wr_detect$7[0:0]$11269 1'0 + assign $1\wr_detect$7[0:0]$11253 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11268 + update \wr_detect$7 $0\wr_detect$7[0:0]$11252 end - attribute \src "libresoc.v:180390.3-180435.6" - process $proc$libresoc.v:180390$11274 + attribute \src "libresoc.v:181698.3-181743.6" + process $proc$libresoc.v:181698$11258 assign { } { } assign { } { } assign { } { } - assign $0\r2__data_o$next[1:0]$11275 $7\r2__data_o$next[1:0]$11282 - attribute \src "libresoc.v:180391.5-180391.29" + assign $0\r2__data_o$next[1:0]$11259 $7\r2__data_o$next[1:0]$11266 + attribute \src "libresoc.v:181699.5-181699.29" switch \initial - attribute \src "libresoc.v:180391.9-180391.17" + attribute \src "libresoc.v:181699.9-181699.17" case 1'1 case end @@ -367744,75 +339114,75 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\r2__data_o$next[1:0]$11276 $6\r2__data_o$next[1:0]$11281 + assign $1\r2__data_o$next[1:0]$11260 $6\r2__data_o$next[1:0]$11265 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r2__data_o$next[1:0]$11277 \dest12__data_i + assign $2\r2__data_o$next[1:0]$11261 \dest12__data_i case - assign $2\r2__data_o$next[1:0]$11277 2'00 + assign $2\r2__data_o$next[1:0]$11261 2'00 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r2__data_o$next[1:0]$11278 \dest22__data_i + assign $3\r2__data_o$next[1:0]$11262 \dest22__data_i case - assign $3\r2__data_o$next[1:0]$11278 $2\r2__data_o$next[1:0]$11277 + assign $3\r2__data_o$next[1:0]$11262 $2\r2__data_o$next[1:0]$11261 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r2__data_o$next[1:0]$11279 \dest32__data_i + assign $4\r2__data_o$next[1:0]$11263 \dest32__data_i case - assign $4\r2__data_o$next[1:0]$11279 $3\r2__data_o$next[1:0]$11278 + assign $4\r2__data_o$next[1:0]$11263 $3\r2__data_o$next[1:0]$11262 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r2__data_o$next[1:0]$11280 \w2__data_i + assign $5\r2__data_o$next[1:0]$11264 \w2__data_i case - assign $5\r2__data_o$next[1:0]$11280 $4\r2__data_o$next[1:0]$11279 + assign $5\r2__data_o$next[1:0]$11264 $4\r2__data_o$next[1:0]$11263 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r2__data_o$next[1:0]$11281 \reg + assign $6\r2__data_o$next[1:0]$11265 \reg case - assign $6\r2__data_o$next[1:0]$11281 $5\r2__data_o$next[1:0]$11280 + assign $6\r2__data_o$next[1:0]$11265 $5\r2__data_o$next[1:0]$11264 end case - assign $1\r2__data_o$next[1:0]$11276 2'00 + assign $1\r2__data_o$next[1:0]$11260 2'00 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\r2__data_o$next[1:0]$11282 2'00 + assign $7\r2__data_o$next[1:0]$11266 2'00 case - assign $7\r2__data_o$next[1:0]$11282 $1\r2__data_o$next[1:0]$11276 + assign $7\r2__data_o$next[1:0]$11266 $1\r2__data_o$next[1:0]$11260 end sync always - update \r2__data_o$next $0\r2__data_o$next[1:0]$11275 + update \r2__data_o$next $0\r2__data_o$next[1:0]$11259 end - attribute \src "libresoc.v:180436.3-180471.6" - process $proc$libresoc.v:180436$11283 + attribute \src "libresoc.v:181744.3-181779.6" + process $proc$libresoc.v:181744$11267 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11284 $1\wr_detect$10[0:0]$11285 - attribute \src "libresoc.v:180437.5-180437.29" + assign $0\wr_detect$10[0:0]$11268 $1\wr_detect$10[0:0]$11269 + attribute \src "libresoc.v:181745.5-181745.29" switch \initial - attribute \src "libresoc.v:180437.9-180437.17" + attribute \src "libresoc.v:181745.9-181745.17" case 1'1 case end @@ -367825,61 +339195,61 @@ module \reg_2$134 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11285 $5\wr_detect$10[0:0]$11289 + assign $1\wr_detect$10[0:0]$11269 $5\wr_detect$10[0:0]$11273 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11286 1'1 + assign $2\wr_detect$10[0:0]$11270 1'1 case - assign $2\wr_detect$10[0:0]$11286 1'0 + assign $2\wr_detect$10[0:0]$11270 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11287 1'1 + assign $3\wr_detect$10[0:0]$11271 1'1 case - assign $3\wr_detect$10[0:0]$11287 $2\wr_detect$10[0:0]$11286 + assign $3\wr_detect$10[0:0]$11271 $2\wr_detect$10[0:0]$11270 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11288 1'1 + assign $4\wr_detect$10[0:0]$11272 1'1 case - assign $4\wr_detect$10[0:0]$11288 $3\wr_detect$10[0:0]$11287 + assign $4\wr_detect$10[0:0]$11272 $3\wr_detect$10[0:0]$11271 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$10[0:0]$11289 1'1 + assign $5\wr_detect$10[0:0]$11273 1'1 case - assign $5\wr_detect$10[0:0]$11289 $4\wr_detect$10[0:0]$11288 + assign $5\wr_detect$10[0:0]$11273 $4\wr_detect$10[0:0]$11272 end case - assign $1\wr_detect$10[0:0]$11285 1'0 + assign $1\wr_detect$10[0:0]$11269 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11284 + update \wr_detect$10 $0\wr_detect$10[0:0]$11268 end - attribute \src "libresoc.v:180472.3-180504.6" - process $proc$libresoc.v:180472$11290 + attribute \src "libresoc.v:181780.3-181812.6" + process $proc$libresoc.v:181780$11274 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[1:0]$11291 $5\reg$next[1:0]$11296 - attribute \src "libresoc.v:180473.5-180473.29" + assign $0\reg$next[1:0]$11275 $5\reg$next[1:0]$11280 + attribute \src "libresoc.v:181781.5-181781.29" switch \initial - attribute \src "libresoc.v:180473.9-180473.17" + attribute \src "libresoc.v:181781.9-181781.17" case 1'1 case end @@ -367888,179 +339258,179 @@ module \reg_2$134 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[1:0]$11292 \dest12__data_i + assign $1\reg$next[1:0]$11276 \dest12__data_i case - assign $1\reg$next[1:0]$11292 \reg + assign $1\reg$next[1:0]$11276 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest22__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[1:0]$11293 \dest22__data_i + assign $2\reg$next[1:0]$11277 \dest22__data_i case - assign $2\reg$next[1:0]$11293 $1\reg$next[1:0]$11292 + assign $2\reg$next[1:0]$11277 $1\reg$next[1:0]$11276 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest32__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[1:0]$11294 \dest32__data_i + assign $3\reg$next[1:0]$11278 \dest32__data_i case - assign $3\reg$next[1:0]$11294 $2\reg$next[1:0]$11293 + assign $3\reg$next[1:0]$11278 $2\reg$next[1:0]$11277 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[1:0]$11295 \w2__data_i + assign $4\reg$next[1:0]$11279 \w2__data_i case - assign $4\reg$next[1:0]$11295 $3\reg$next[1:0]$11294 + assign $4\reg$next[1:0]$11279 $3\reg$next[1:0]$11278 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[1:0]$11296 2'00 + assign $5\reg$next[1:0]$11280 2'00 case - assign $5\reg$next[1:0]$11296 $4\reg$next[1:0]$11295 + assign $5\reg$next[1:0]$11280 $4\reg$next[1:0]$11279 end sync always - update \reg$next $0\reg$next[1:0]$11291 + update \reg$next $0\reg$next[1:0]$11275 end - connect \$9 $not$libresoc.v:180130$11223_Y - connect \$1 $not$libresoc.v:180131$11224_Y - connect \$3 $not$libresoc.v:180132$11225_Y - connect \$6 $not$libresoc.v:180133$11226_Y + connect \$9 $not$libresoc.v:181438$11207_Y + connect \$1 $not$libresoc.v:181439$11208_Y + connect \$3 $not$libresoc.v:181440$11209_Y + connect \$6 $not$libresoc.v:181441$11210_Y end -attribute \src "libresoc.v:180509.1-180858.10" +attribute \src "libresoc.v:181817.1-182166.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.state.reg_2" attribute \generator "nMigen" module \reg_2$137 - attribute \src "libresoc.v:180579.3-180624.6" - wire width 64 $0\cia2__data_o$next[63:0]$11311 - attribute \src "libresoc.v:180577.3-180578.41" + attribute \src "libresoc.v:181887.3-181932.6" + wire width 64 $0\cia2__data_o$next[63:0]$11295 + attribute \src "libresoc.v:181885.3-181886.41" wire width 64 $0\cia2__data_o[63:0] - attribute \src "libresoc.v:180510.7-180510.20" + attribute \src "libresoc.v:181818.7-181818.20" wire $0\initial[0:0] - attribute \src "libresoc.v:180661.3-180706.6" - wire width 64 $0\msr2__data_o$next[63:0]$11321 - attribute \src "libresoc.v:180575.3-180576.41" + attribute \src "libresoc.v:181969.3-182014.6" + wire width 64 $0\msr2__data_o$next[63:0]$11305 + attribute \src "libresoc.v:181883.3-181884.41" wire width 64 $0\msr2__data_o[63:0] - attribute \src "libresoc.v:180825.3-180857.6" - wire width 64 $0\reg$next[63:0]$11353 - attribute \src "libresoc.v:180571.3-180572.25" + attribute \src "libresoc.v:182133.3-182165.6" + wire width 64 $0\reg$next[63:0]$11337 + attribute \src "libresoc.v:181879.3-181880.25" wire width 64 $0\reg[63:0] - attribute \src "libresoc.v:180743.3-180788.6" - wire width 64 $0\sv2__data_o$next[63:0]$11337 - attribute \src "libresoc.v:180573.3-180574.39" + attribute \src "libresoc.v:182051.3-182096.6" + wire width 64 $0\sv2__data_o$next[63:0]$11321 + attribute \src "libresoc.v:181881.3-181882.39" wire width 64 $0\sv2__data_o[63:0] - attribute \src "libresoc.v:180707.3-180742.6" - wire $0\wr_detect$4[0:0]$11330 - attribute \src "libresoc.v:180789.3-180824.6" - wire $0\wr_detect$7[0:0]$11346 - attribute \src "libresoc.v:180625.3-180660.6" + attribute \src "libresoc.v:182015.3-182050.6" + wire $0\wr_detect$4[0:0]$11314 + attribute \src "libresoc.v:182097.3-182132.6" + wire $0\wr_detect$7[0:0]$11330 + attribute \src "libresoc.v:181933.3-181968.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:180579.3-180624.6" - wire width 64 $1\cia2__data_o$next[63:0]$11312 - attribute \src "libresoc.v:180519.14-180519.49" + attribute \src "libresoc.v:181887.3-181932.6" + wire width 64 $1\cia2__data_o$next[63:0]$11296 + attribute \src "libresoc.v:181827.14-181827.49" wire width 64 $1\cia2__data_o[63:0] - attribute \src "libresoc.v:180661.3-180706.6" - wire width 64 $1\msr2__data_o$next[63:0]$11322 - attribute \src "libresoc.v:180536.14-180536.49" + attribute \src "libresoc.v:181969.3-182014.6" + wire width 64 $1\msr2__data_o$next[63:0]$11306 + attribute \src "libresoc.v:181844.14-181844.49" wire width 64 $1\msr2__data_o[63:0] - attribute \src "libresoc.v:180825.3-180857.6" - wire width 64 $1\reg$next[63:0]$11354 - attribute \src "libresoc.v:180548.14-180548.42" + attribute \src "libresoc.v:182133.3-182165.6" + wire width 64 $1\reg$next[63:0]$11338 + attribute \src "libresoc.v:181856.14-181856.42" wire width 64 $1\reg[63:0] - attribute \src "libresoc.v:180743.3-180788.6" - wire width 64 $1\sv2__data_o$next[63:0]$11338 - attribute \src "libresoc.v:180555.14-180555.48" + attribute \src "libresoc.v:182051.3-182096.6" + wire width 64 $1\sv2__data_o$next[63:0]$11322 + attribute \src "libresoc.v:181863.14-181863.48" wire width 64 $1\sv2__data_o[63:0] - attribute \src "libresoc.v:180707.3-180742.6" - wire $1\wr_detect$4[0:0]$11331 - attribute \src "libresoc.v:180789.3-180824.6" - wire $1\wr_detect$7[0:0]$11347 - attribute \src "libresoc.v:180625.3-180660.6" + attribute \src "libresoc.v:182015.3-182050.6" + wire $1\wr_detect$4[0:0]$11315 + attribute \src "libresoc.v:182097.3-182132.6" + wire $1\wr_detect$7[0:0]$11331 + attribute \src "libresoc.v:181933.3-181968.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:180579.3-180624.6" - wire width 64 $2\cia2__data_o$next[63:0]$11313 - attribute \src "libresoc.v:180661.3-180706.6" - wire width 64 $2\msr2__data_o$next[63:0]$11323 - attribute \src "libresoc.v:180825.3-180857.6" - wire width 64 $2\reg$next[63:0]$11355 - attribute \src "libresoc.v:180743.3-180788.6" - wire width 64 $2\sv2__data_o$next[63:0]$11339 - attribute \src "libresoc.v:180707.3-180742.6" - wire $2\wr_detect$4[0:0]$11332 - attribute \src "libresoc.v:180789.3-180824.6" - wire $2\wr_detect$7[0:0]$11348 - attribute \src "libresoc.v:180625.3-180660.6" + attribute \src "libresoc.v:181887.3-181932.6" + wire width 64 $2\cia2__data_o$next[63:0]$11297 + attribute \src "libresoc.v:181969.3-182014.6" + wire width 64 $2\msr2__data_o$next[63:0]$11307 + attribute \src "libresoc.v:182133.3-182165.6" + wire width 64 $2\reg$next[63:0]$11339 + attribute \src "libresoc.v:182051.3-182096.6" + wire width 64 $2\sv2__data_o$next[63:0]$11323 + attribute \src "libresoc.v:182015.3-182050.6" + wire $2\wr_detect$4[0:0]$11316 + attribute \src "libresoc.v:182097.3-182132.6" + wire $2\wr_detect$7[0:0]$11332 + attribute \src "libresoc.v:181933.3-181968.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:180579.3-180624.6" - wire width 64 $3\cia2__data_o$next[63:0]$11314 - attribute \src "libresoc.v:180661.3-180706.6" - wire width 64 $3\msr2__data_o$next[63:0]$11324 - attribute \src "libresoc.v:180825.3-180857.6" - wire width 64 $3\reg$next[63:0]$11356 - attribute \src "libresoc.v:180743.3-180788.6" - wire width 64 $3\sv2__data_o$next[63:0]$11340 - attribute \src "libresoc.v:180707.3-180742.6" - wire $3\wr_detect$4[0:0]$11333 - attribute \src "libresoc.v:180789.3-180824.6" - wire $3\wr_detect$7[0:0]$11349 - attribute \src "libresoc.v:180625.3-180660.6" + attribute \src "libresoc.v:181887.3-181932.6" + wire width 64 $3\cia2__data_o$next[63:0]$11298 + attribute \src "libresoc.v:181969.3-182014.6" + wire width 64 $3\msr2__data_o$next[63:0]$11308 + attribute \src "libresoc.v:182133.3-182165.6" + wire width 64 $3\reg$next[63:0]$11340 + attribute \src "libresoc.v:182051.3-182096.6" + wire width 64 $3\sv2__data_o$next[63:0]$11324 + attribute \src "libresoc.v:182015.3-182050.6" + wire $3\wr_detect$4[0:0]$11317 + attribute \src "libresoc.v:182097.3-182132.6" + wire $3\wr_detect$7[0:0]$11333 + attribute \src "libresoc.v:181933.3-181968.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:180579.3-180624.6" - wire width 64 $4\cia2__data_o$next[63:0]$11315 - attribute \src "libresoc.v:180661.3-180706.6" - wire width 64 $4\msr2__data_o$next[63:0]$11325 - attribute \src "libresoc.v:180825.3-180857.6" - wire width 64 $4\reg$next[63:0]$11357 - attribute \src "libresoc.v:180743.3-180788.6" - wire width 64 $4\sv2__data_o$next[63:0]$11341 - attribute \src "libresoc.v:180707.3-180742.6" - wire $4\wr_detect$4[0:0]$11334 - attribute \src "libresoc.v:180789.3-180824.6" - wire $4\wr_detect$7[0:0]$11350 - attribute \src "libresoc.v:180625.3-180660.6" + attribute \src "libresoc.v:181887.3-181932.6" + wire width 64 $4\cia2__data_o$next[63:0]$11299 + attribute \src "libresoc.v:181969.3-182014.6" + wire width 64 $4\msr2__data_o$next[63:0]$11309 + attribute \src "libresoc.v:182133.3-182165.6" + wire width 64 $4\reg$next[63:0]$11341 + attribute \src "libresoc.v:182051.3-182096.6" + wire width 64 $4\sv2__data_o$next[63:0]$11325 + attribute \src "libresoc.v:182015.3-182050.6" + wire $4\wr_detect$4[0:0]$11318 + attribute \src "libresoc.v:182097.3-182132.6" + wire $4\wr_detect$7[0:0]$11334 + attribute \src "libresoc.v:181933.3-181968.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:180579.3-180624.6" - wire width 64 $5\cia2__data_o$next[63:0]$11316 - attribute \src "libresoc.v:180661.3-180706.6" - wire width 64 $5\msr2__data_o$next[63:0]$11326 - attribute \src "libresoc.v:180825.3-180857.6" - wire width 64 $5\reg$next[63:0]$11358 - attribute \src "libresoc.v:180743.3-180788.6" - wire width 64 $5\sv2__data_o$next[63:0]$11342 - attribute \src "libresoc.v:180707.3-180742.6" - wire $5\wr_detect$4[0:0]$11335 - attribute \src "libresoc.v:180789.3-180824.6" - wire $5\wr_detect$7[0:0]$11351 - attribute \src "libresoc.v:180625.3-180660.6" + attribute \src "libresoc.v:181887.3-181932.6" + wire width 64 $5\cia2__data_o$next[63:0]$11300 + attribute \src "libresoc.v:181969.3-182014.6" + wire width 64 $5\msr2__data_o$next[63:0]$11310 + attribute \src "libresoc.v:182133.3-182165.6" + wire width 64 $5\reg$next[63:0]$11342 + attribute \src "libresoc.v:182051.3-182096.6" + wire width 64 $5\sv2__data_o$next[63:0]$11326 + attribute \src "libresoc.v:182015.3-182050.6" + wire $5\wr_detect$4[0:0]$11319 + attribute \src "libresoc.v:182097.3-182132.6" + wire $5\wr_detect$7[0:0]$11335 + attribute \src "libresoc.v:181933.3-181968.6" wire $5\wr_detect[0:0] - attribute \src "libresoc.v:180579.3-180624.6" - wire width 64 $6\cia2__data_o$next[63:0]$11317 - attribute \src "libresoc.v:180661.3-180706.6" - wire width 64 $6\msr2__data_o$next[63:0]$11327 - attribute \src "libresoc.v:180743.3-180788.6" - wire width 64 $6\sv2__data_o$next[63:0]$11343 - attribute \src "libresoc.v:180579.3-180624.6" - wire width 64 $7\cia2__data_o$next[63:0]$11318 - attribute \src "libresoc.v:180661.3-180706.6" - wire width 64 $7\msr2__data_o$next[63:0]$11328 - attribute \src "libresoc.v:180743.3-180788.6" - wire width 64 $7\sv2__data_o$next[63:0]$11344 - attribute \src "libresoc.v:180568.17-180568.100" - wire $not$libresoc.v:180568$11303_Y - attribute \src "libresoc.v:180569.17-180569.103" - wire $not$libresoc.v:180569$11304_Y - attribute \src "libresoc.v:180570.17-180570.103" - wire $not$libresoc.v:180570$11305_Y + attribute \src "libresoc.v:181887.3-181932.6" + wire width 64 $6\cia2__data_o$next[63:0]$11301 + attribute \src "libresoc.v:181969.3-182014.6" + wire width 64 $6\msr2__data_o$next[63:0]$11311 + attribute \src "libresoc.v:182051.3-182096.6" + wire width 64 $6\sv2__data_o$next[63:0]$11327 + attribute \src "libresoc.v:181887.3-181932.6" + wire width 64 $7\cia2__data_o$next[63:0]$11302 + attribute \src "libresoc.v:181969.3-182014.6" + wire width 64 $7\msr2__data_o$next[63:0]$11312 + attribute \src "libresoc.v:182051.3-182096.6" + wire width 64 $7\sv2__data_o$next[63:0]$11328 + attribute \src "libresoc.v:181876.17-181876.100" + wire $not$libresoc.v:181876$11287_Y + attribute \src "libresoc.v:181877.17-181877.103" + wire $not$libresoc.v:181877$11288_Y + attribute \src "libresoc.v:181878.17-181878.103" + wire $not$libresoc.v:181878$11289_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -368073,15 +339443,15 @@ module \reg_2$137 wire width 64 \cia2__data_o$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 2 \cia2__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 15 \d_wr12__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 14 \d_wr12__wen - attribute \src "libresoc.v:180510.7-180510.15" + attribute \src "libresoc.v:181818.7-181818.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 11 \msr2__data_i @@ -368118,106 +339488,106 @@ module \reg_2$137 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180568$11303 + cell $not $not$libresoc.v:181876$11287 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:180568$11303_Y + connect \Y $not$libresoc.v:181876$11287_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180569$11304 + cell $not $not$libresoc.v:181877$11288 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:180569$11304_Y + connect \Y $not$libresoc.v:181877$11288_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180570$11305 + cell $not $not$libresoc.v:181878$11289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:180570$11305_Y + connect \Y $not$libresoc.v:181878$11289_Y end - attribute \src "libresoc.v:180510.7-180510.20" - process $proc$libresoc.v:180510$11359 + attribute \src "libresoc.v:181818.7-181818.20" + process $proc$libresoc.v:181818$11343 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:180519.14-180519.49" - process $proc$libresoc.v:180519$11360 + attribute \src "libresoc.v:181827.14-181827.49" + process $proc$libresoc.v:181827$11344 assign { } { } assign $1\cia2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \cia2__data_o $1\cia2__data_o[63:0] end - attribute \src "libresoc.v:180536.14-180536.49" - process $proc$libresoc.v:180536$11361 + attribute \src "libresoc.v:181844.14-181844.49" + process $proc$libresoc.v:181844$11345 assign { } { } assign $1\msr2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \msr2__data_o $1\msr2__data_o[63:0] end - attribute \src "libresoc.v:180548.14-180548.42" - process $proc$libresoc.v:180548$11362 + attribute \src "libresoc.v:181856.14-181856.42" + process $proc$libresoc.v:181856$11346 assign { } { } assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \reg $1\reg[63:0] end - attribute \src "libresoc.v:180555.14-180555.48" - process $proc$libresoc.v:180555$11363 + attribute \src "libresoc.v:181863.14-181863.48" + process $proc$libresoc.v:181863$11347 assign { } { } assign $1\sv2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \sv2__data_o $1\sv2__data_o[63:0] end - attribute \src "libresoc.v:180571.3-180572.25" - process $proc$libresoc.v:180571$11306 + attribute \src "libresoc.v:181879.3-181880.25" + process $proc$libresoc.v:181879$11290 assign { } { } assign $0\reg[63:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[63:0] end - attribute \src "libresoc.v:180573.3-180574.39" - process $proc$libresoc.v:180573$11307 + attribute \src "libresoc.v:181881.3-181882.39" + process $proc$libresoc.v:181881$11291 assign { } { } assign $0\sv2__data_o[63:0] \sv2__data_o$next sync posedge \coresync_clk update \sv2__data_o $0\sv2__data_o[63:0] end - attribute \src "libresoc.v:180575.3-180576.41" - process $proc$libresoc.v:180575$11308 + attribute \src "libresoc.v:181883.3-181884.41" + process $proc$libresoc.v:181883$11292 assign { } { } assign $0\msr2__data_o[63:0] \msr2__data_o$next sync posedge \coresync_clk update \msr2__data_o $0\msr2__data_o[63:0] end - attribute \src "libresoc.v:180577.3-180578.41" - process $proc$libresoc.v:180577$11309 + attribute \src "libresoc.v:181885.3-181886.41" + process $proc$libresoc.v:181885$11293 assign { } { } assign $0\cia2__data_o[63:0] \cia2__data_o$next sync posedge \coresync_clk update \cia2__data_o $0\cia2__data_o[63:0] end - attribute \src "libresoc.v:180579.3-180624.6" - process $proc$libresoc.v:180579$11310 + attribute \src "libresoc.v:181887.3-181932.6" + process $proc$libresoc.v:181887$11294 assign { } { } assign { } { } assign { } { } - assign $0\cia2__data_o$next[63:0]$11311 $7\cia2__data_o$next[63:0]$11318 - attribute \src "libresoc.v:180580.5-180580.29" + assign $0\cia2__data_o$next[63:0]$11295 $7\cia2__data_o$next[63:0]$11302 + attribute \src "libresoc.v:181888.5-181888.29" switch \initial - attribute \src "libresoc.v:180580.9-180580.17" + attribute \src "libresoc.v:181888.9-181888.17" case 1'1 case end @@ -368230,75 +339600,75 @@ module \reg_2$137 assign { } { } assign { } { } assign { } { } - assign $1\cia2__data_o$next[63:0]$11312 $6\cia2__data_o$next[63:0]$11317 + assign $1\cia2__data_o$next[63:0]$11296 $6\cia2__data_o$next[63:0]$11301 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cia2__data_o$next[63:0]$11313 \nia2__data_i + assign $2\cia2__data_o$next[63:0]$11297 \nia2__data_i case - assign $2\cia2__data_o$next[63:0]$11313 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\cia2__data_o$next[63:0]$11297 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\cia2__data_o$next[63:0]$11314 \msr2__data_i + assign $3\cia2__data_o$next[63:0]$11298 \msr2__data_i case - assign $3\cia2__data_o$next[63:0]$11314 $2\cia2__data_o$next[63:0]$11313 + assign $3\cia2__data_o$next[63:0]$11298 $2\cia2__data_o$next[63:0]$11297 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cia2__data_o$next[63:0]$11315 \sv2__data_i + assign $4\cia2__data_o$next[63:0]$11299 \sv2__data_i case - assign $4\cia2__data_o$next[63:0]$11315 $3\cia2__data_o$next[63:0]$11314 + assign $4\cia2__data_o$next[63:0]$11299 $3\cia2__data_o$next[63:0]$11298 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\cia2__data_o$next[63:0]$11316 \d_wr12__data_i + assign $5\cia2__data_o$next[63:0]$11300 \d_wr12__data_i case - assign $5\cia2__data_o$next[63:0]$11316 $4\cia2__data_o$next[63:0]$11315 + assign $5\cia2__data_o$next[63:0]$11300 $4\cia2__data_o$next[63:0]$11299 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cia2__data_o$next[63:0]$11317 \reg + assign $6\cia2__data_o$next[63:0]$11301 \reg case - assign $6\cia2__data_o$next[63:0]$11317 $5\cia2__data_o$next[63:0]$11316 + assign $6\cia2__data_o$next[63:0]$11301 $5\cia2__data_o$next[63:0]$11300 end case - assign $1\cia2__data_o$next[63:0]$11312 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\cia2__data_o$next[63:0]$11296 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\cia2__data_o$next[63:0]$11318 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\cia2__data_o$next[63:0]$11302 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\cia2__data_o$next[63:0]$11318 $1\cia2__data_o$next[63:0]$11312 + assign $7\cia2__data_o$next[63:0]$11302 $1\cia2__data_o$next[63:0]$11296 end sync always - update \cia2__data_o$next $0\cia2__data_o$next[63:0]$11311 + update \cia2__data_o$next $0\cia2__data_o$next[63:0]$11295 end - attribute \src "libresoc.v:180625.3-180660.6" - process $proc$libresoc.v:180625$11319 + attribute \src "libresoc.v:181933.3-181968.6" + process $proc$libresoc.v:181933$11303 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:180626.5-180626.29" + attribute \src "libresoc.v:181934.5-181934.29" switch \initial - attribute \src "libresoc.v:180626.9-180626.17" + attribute \src "libresoc.v:181934.9-181934.17" case 1'1 case end @@ -368354,15 +339724,15 @@ module \reg_2$137 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:180661.3-180706.6" - process $proc$libresoc.v:180661$11320 + attribute \src "libresoc.v:181969.3-182014.6" + process $proc$libresoc.v:181969$11304 assign { } { } assign { } { } assign { } { } - assign $0\msr2__data_o$next[63:0]$11321 $7\msr2__data_o$next[63:0]$11328 - attribute \src "libresoc.v:180662.5-180662.29" + assign $0\msr2__data_o$next[63:0]$11305 $7\msr2__data_o$next[63:0]$11312 + attribute \src "libresoc.v:181970.5-181970.29" switch \initial - attribute \src "libresoc.v:180662.9-180662.17" + attribute \src "libresoc.v:181970.9-181970.17" case 1'1 case end @@ -368375,75 +339745,75 @@ module \reg_2$137 assign { } { } assign { } { } assign { } { } - assign $1\msr2__data_o$next[63:0]$11322 $6\msr2__data_o$next[63:0]$11327 + assign $1\msr2__data_o$next[63:0]$11306 $6\msr2__data_o$next[63:0]$11311 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr2__data_o$next[63:0]$11323 \nia2__data_i + assign $2\msr2__data_o$next[63:0]$11307 \nia2__data_i case - assign $2\msr2__data_o$next[63:0]$11323 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\msr2__data_o$next[63:0]$11307 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\msr2__data_o$next[63:0]$11324 \msr2__data_i + assign $3\msr2__data_o$next[63:0]$11308 \msr2__data_i case - assign $3\msr2__data_o$next[63:0]$11324 $2\msr2__data_o$next[63:0]$11323 + assign $3\msr2__data_o$next[63:0]$11308 $2\msr2__data_o$next[63:0]$11307 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\msr2__data_o$next[63:0]$11325 \sv2__data_i + assign $4\msr2__data_o$next[63:0]$11309 \sv2__data_i case - assign $4\msr2__data_o$next[63:0]$11325 $3\msr2__data_o$next[63:0]$11324 + assign $4\msr2__data_o$next[63:0]$11309 $3\msr2__data_o$next[63:0]$11308 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\msr2__data_o$next[63:0]$11326 \d_wr12__data_i + assign $5\msr2__data_o$next[63:0]$11310 \d_wr12__data_i case - assign $5\msr2__data_o$next[63:0]$11326 $4\msr2__data_o$next[63:0]$11325 + assign $5\msr2__data_o$next[63:0]$11310 $4\msr2__data_o$next[63:0]$11309 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\msr2__data_o$next[63:0]$11327 \reg + assign $6\msr2__data_o$next[63:0]$11311 \reg case - assign $6\msr2__data_o$next[63:0]$11327 $5\msr2__data_o$next[63:0]$11326 + assign $6\msr2__data_o$next[63:0]$11311 $5\msr2__data_o$next[63:0]$11310 end case - assign $1\msr2__data_o$next[63:0]$11322 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\msr2__data_o$next[63:0]$11306 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\msr2__data_o$next[63:0]$11328 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\msr2__data_o$next[63:0]$11312 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\msr2__data_o$next[63:0]$11328 $1\msr2__data_o$next[63:0]$11322 + assign $7\msr2__data_o$next[63:0]$11312 $1\msr2__data_o$next[63:0]$11306 end sync always - update \msr2__data_o$next $0\msr2__data_o$next[63:0]$11321 + update \msr2__data_o$next $0\msr2__data_o$next[63:0]$11305 end - attribute \src "libresoc.v:180707.3-180742.6" - process $proc$libresoc.v:180707$11329 + attribute \src "libresoc.v:182015.3-182050.6" + process $proc$libresoc.v:182015$11313 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11330 $1\wr_detect$4[0:0]$11331 - attribute \src "libresoc.v:180708.5-180708.29" + assign $0\wr_detect$4[0:0]$11314 $1\wr_detect$4[0:0]$11315 + attribute \src "libresoc.v:182016.5-182016.29" switch \initial - attribute \src "libresoc.v:180708.9-180708.17" + attribute \src "libresoc.v:182016.9-182016.17" case 1'1 case end @@ -368456,58 +339826,58 @@ module \reg_2$137 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11331 $5\wr_detect$4[0:0]$11335 + assign $1\wr_detect$4[0:0]$11315 $5\wr_detect$4[0:0]$11319 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11332 1'1 + assign $2\wr_detect$4[0:0]$11316 1'1 case - assign $2\wr_detect$4[0:0]$11332 1'0 + assign $2\wr_detect$4[0:0]$11316 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11333 1'1 + assign $3\wr_detect$4[0:0]$11317 1'1 case - assign $3\wr_detect$4[0:0]$11333 $2\wr_detect$4[0:0]$11332 + assign $3\wr_detect$4[0:0]$11317 $2\wr_detect$4[0:0]$11316 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11334 1'1 + assign $4\wr_detect$4[0:0]$11318 1'1 case - assign $4\wr_detect$4[0:0]$11334 $3\wr_detect$4[0:0]$11333 + assign $4\wr_detect$4[0:0]$11318 $3\wr_detect$4[0:0]$11317 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$4[0:0]$11335 1'1 + assign $5\wr_detect$4[0:0]$11319 1'1 case - assign $5\wr_detect$4[0:0]$11335 $4\wr_detect$4[0:0]$11334 + assign $5\wr_detect$4[0:0]$11319 $4\wr_detect$4[0:0]$11318 end case - assign $1\wr_detect$4[0:0]$11331 1'0 + assign $1\wr_detect$4[0:0]$11315 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11330 + update \wr_detect$4 $0\wr_detect$4[0:0]$11314 end - attribute \src "libresoc.v:180743.3-180788.6" - process $proc$libresoc.v:180743$11336 + attribute \src "libresoc.v:182051.3-182096.6" + process $proc$libresoc.v:182051$11320 assign { } { } assign { } { } assign { } { } - assign $0\sv2__data_o$next[63:0]$11337 $7\sv2__data_o$next[63:0]$11344 - attribute \src "libresoc.v:180744.5-180744.29" + assign $0\sv2__data_o$next[63:0]$11321 $7\sv2__data_o$next[63:0]$11328 + attribute \src "libresoc.v:182052.5-182052.29" switch \initial - attribute \src "libresoc.v:180744.9-180744.17" + attribute \src "libresoc.v:182052.9-182052.17" case 1'1 case end @@ -368520,75 +339890,75 @@ module \reg_2$137 assign { } { } assign { } { } assign { } { } - assign $1\sv2__data_o$next[63:0]$11338 $6\sv2__data_o$next[63:0]$11343 + assign $1\sv2__data_o$next[63:0]$11322 $6\sv2__data_o$next[63:0]$11327 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\sv2__data_o$next[63:0]$11339 \nia2__data_i + assign $2\sv2__data_o$next[63:0]$11323 \nia2__data_i case - assign $2\sv2__data_o$next[63:0]$11339 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sv2__data_o$next[63:0]$11323 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sv2__data_o$next[63:0]$11340 \msr2__data_i + assign $3\sv2__data_o$next[63:0]$11324 \msr2__data_i case - assign $3\sv2__data_o$next[63:0]$11340 $2\sv2__data_o$next[63:0]$11339 + assign $3\sv2__data_o$next[63:0]$11324 $2\sv2__data_o$next[63:0]$11323 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\sv2__data_o$next[63:0]$11341 \sv2__data_i + assign $4\sv2__data_o$next[63:0]$11325 \sv2__data_i case - assign $4\sv2__data_o$next[63:0]$11341 $3\sv2__data_o$next[63:0]$11340 + assign $4\sv2__data_o$next[63:0]$11325 $3\sv2__data_o$next[63:0]$11324 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\sv2__data_o$next[63:0]$11342 \d_wr12__data_i + assign $5\sv2__data_o$next[63:0]$11326 \d_wr12__data_i case - assign $5\sv2__data_o$next[63:0]$11342 $4\sv2__data_o$next[63:0]$11341 + assign $5\sv2__data_o$next[63:0]$11326 $4\sv2__data_o$next[63:0]$11325 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\sv2__data_o$next[63:0]$11343 \reg + assign $6\sv2__data_o$next[63:0]$11327 \reg case - assign $6\sv2__data_o$next[63:0]$11343 $5\sv2__data_o$next[63:0]$11342 + assign $6\sv2__data_o$next[63:0]$11327 $5\sv2__data_o$next[63:0]$11326 end case - assign $1\sv2__data_o$next[63:0]$11338 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\sv2__data_o$next[63:0]$11322 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\sv2__data_o$next[63:0]$11344 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $7\sv2__data_o$next[63:0]$11328 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $7\sv2__data_o$next[63:0]$11344 $1\sv2__data_o$next[63:0]$11338 + assign $7\sv2__data_o$next[63:0]$11328 $1\sv2__data_o$next[63:0]$11322 end sync always - update \sv2__data_o$next $0\sv2__data_o$next[63:0]$11337 + update \sv2__data_o$next $0\sv2__data_o$next[63:0]$11321 end - attribute \src "libresoc.v:180789.3-180824.6" - process $proc$libresoc.v:180789$11345 + attribute \src "libresoc.v:182097.3-182132.6" + process $proc$libresoc.v:182097$11329 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11346 $1\wr_detect$7[0:0]$11347 - attribute \src "libresoc.v:180790.5-180790.29" + assign $0\wr_detect$7[0:0]$11330 $1\wr_detect$7[0:0]$11331 + attribute \src "libresoc.v:182098.5-182098.29" switch \initial - attribute \src "libresoc.v:180790.9-180790.17" + attribute \src "libresoc.v:182098.9-182098.17" case 1'1 case end @@ -368601,61 +339971,61 @@ module \reg_2$137 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11347 $5\wr_detect$7[0:0]$11351 + assign $1\wr_detect$7[0:0]$11331 $5\wr_detect$7[0:0]$11335 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \nia2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11348 1'1 + assign $2\wr_detect$7[0:0]$11332 1'1 case - assign $2\wr_detect$7[0:0]$11348 1'0 + assign $2\wr_detect$7[0:0]$11332 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11349 1'1 + assign $3\wr_detect$7[0:0]$11333 1'1 case - assign $3\wr_detect$7[0:0]$11349 $2\wr_detect$7[0:0]$11348 + assign $3\wr_detect$7[0:0]$11333 $2\wr_detect$7[0:0]$11332 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11350 1'1 + assign $4\wr_detect$7[0:0]$11334 1'1 case - assign $4\wr_detect$7[0:0]$11350 $3\wr_detect$7[0:0]$11349 + assign $4\wr_detect$7[0:0]$11334 $3\wr_detect$7[0:0]$11333 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\wr_detect$7[0:0]$11351 1'1 + assign $5\wr_detect$7[0:0]$11335 1'1 case - assign $5\wr_detect$7[0:0]$11351 $4\wr_detect$7[0:0]$11350 + assign $5\wr_detect$7[0:0]$11335 $4\wr_detect$7[0:0]$11334 end case - assign $1\wr_detect$7[0:0]$11347 1'0 + assign $1\wr_detect$7[0:0]$11331 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11346 + update \wr_detect$7 $0\wr_detect$7[0:0]$11330 end - attribute \src "libresoc.v:180825.3-180857.6" - process $proc$libresoc.v:180825$11352 + attribute \src "libresoc.v:182133.3-182165.6" + process $proc$libresoc.v:182133$11336 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[63:0]$11353 $5\reg$next[63:0]$11358 - attribute \src "libresoc.v:180826.5-180826.29" + assign $0\reg$next[63:0]$11337 $5\reg$next[63:0]$11342 + attribute \src "libresoc.v:182134.5-182134.29" switch \initial - attribute \src "libresoc.v:180826.9-180826.17" + attribute \src "libresoc.v:182134.9-182134.17" case 1'1 case end @@ -368664,254 +340034,254 @@ module \reg_2$137 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[63:0]$11354 \nia2__data_i + assign $1\reg$next[63:0]$11338 \nia2__data_i case - assign $1\reg$next[63:0]$11354 \reg + assign $1\reg$next[63:0]$11338 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \msr2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[63:0]$11355 \msr2__data_i + assign $2\reg$next[63:0]$11339 \msr2__data_i case - assign $2\reg$next[63:0]$11355 $1\reg$next[63:0]$11354 + assign $2\reg$next[63:0]$11339 $1\reg$next[63:0]$11338 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \sv2__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[63:0]$11356 \sv2__data_i + assign $3\reg$next[63:0]$11340 \sv2__data_i case - assign $3\reg$next[63:0]$11356 $2\reg$next[63:0]$11355 + assign $3\reg$next[63:0]$11340 $2\reg$next[63:0]$11339 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \d_wr12__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[63:0]$11357 \d_wr12__data_i + assign $4\reg$next[63:0]$11341 \d_wr12__data_i case - assign $4\reg$next[63:0]$11357 $3\reg$next[63:0]$11356 + assign $4\reg$next[63:0]$11341 $3\reg$next[63:0]$11340 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\reg$next[63:0]$11358 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $5\reg$next[63:0]$11342 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $5\reg$next[63:0]$11358 $4\reg$next[63:0]$11357 + assign $5\reg$next[63:0]$11342 $4\reg$next[63:0]$11341 end sync always - update \reg$next $0\reg$next[63:0]$11353 + update \reg$next $0\reg$next[63:0]$11337 end - connect \$1 $not$libresoc.v:180568$11303_Y - connect \$3 $not$libresoc.v:180569$11304_Y - connect \$6 $not$libresoc.v:180570$11305_Y + connect \$1 $not$libresoc.v:181876$11287_Y + connect \$3 $not$libresoc.v:181877$11288_Y + connect \$6 $not$libresoc.v:181878$11289_Y end -attribute \src "libresoc.v:180862.1-181417.10" +attribute \src "libresoc.v:182170.1-182725.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_3" attribute \generator "nMigen" module \reg_3 - attribute \src "libresoc.v:180970.3-181009.6" - wire width 4 $0\cr_pred3__data_o$next[3:0]$11378 - attribute \src "libresoc.v:180968.3-180969.49" + attribute \src "libresoc.v:182278.3-182317.6" + wire width 4 $0\cr_pred3__data_o$next[3:0]$11362 + attribute \src "libresoc.v:182276.3-182277.49" wire width 4 $0\cr_pred3__data_o[3:0] - attribute \src "libresoc.v:180863.7-180863.20" + attribute \src "libresoc.v:182171.7-182171.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181040.3-181079.6" - wire width 4 $0\r23__data_o$next[3:0]$11387 - attribute \src "libresoc.v:180958.3-180959.39" + attribute \src "libresoc.v:182348.3-182387.6" + wire width 4 $0\r23__data_o$next[3:0]$11371 + attribute \src "libresoc.v:182266.3-182267.39" wire width 4 $0\r23__data_o[3:0] - attribute \src "libresoc.v:181347.3-181386.6" - wire width 4 $0\r3__data_o$next[3:0]$11449 - attribute \src "libresoc.v:180960.3-180961.37" + attribute \src "libresoc.v:182655.3-182694.6" + wire width 4 $0\r3__data_o$next[3:0]$11433 + attribute \src "libresoc.v:182268.3-182269.37" wire width 4 $0\r3__data_o[3:0] - attribute \src "libresoc.v:181110.3-181136.6" - wire width 4 $0\reg$next[3:0]$11401 - attribute \src "libresoc.v:180956.3-180957.25" + attribute \src "libresoc.v:182418.3-182444.6" + wire width 4 $0\reg$next[3:0]$11385 + attribute \src "libresoc.v:182264.3-182265.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:181137.3-181176.6" - wire width 4 $0\src13__data_o$next[3:0]$11407 - attribute \src "libresoc.v:180966.3-180967.43" + attribute \src "libresoc.v:182445.3-182484.6" + wire width 4 $0\src13__data_o$next[3:0]$11391 + attribute \src "libresoc.v:182274.3-182275.43" wire width 4 $0\src13__data_o[3:0] - attribute \src "libresoc.v:181207.3-181246.6" - wire width 4 $0\src23__data_o$next[3:0]$11421 - attribute \src "libresoc.v:180964.3-180965.43" + attribute \src "libresoc.v:182515.3-182554.6" + wire width 4 $0\src23__data_o$next[3:0]$11405 + attribute \src "libresoc.v:182272.3-182273.43" wire width 4 $0\src23__data_o[3:0] - attribute \src "libresoc.v:181277.3-181316.6" - wire width 4 $0\src33__data_o$next[3:0]$11435 - attribute \src "libresoc.v:180962.3-180963.43" + attribute \src "libresoc.v:182585.3-182624.6" + wire width 4 $0\src33__data_o$next[3:0]$11419 + attribute \src "libresoc.v:182270.3-182271.43" wire width 4 $0\src33__data_o[3:0] - attribute \src "libresoc.v:181317.3-181346.6" - wire $0\wr_detect$10[0:0]$11443 - attribute \src "libresoc.v:181387.3-181416.6" - wire $0\wr_detect$13[0:0]$11457 - attribute \src "libresoc.v:181080.3-181109.6" - wire $0\wr_detect$16[0:0]$11395 - attribute \src "libresoc.v:181177.3-181206.6" - wire $0\wr_detect$4[0:0]$11415 - attribute \src "libresoc.v:181247.3-181276.6" - wire $0\wr_detect$7[0:0]$11429 - attribute \src "libresoc.v:181010.3-181039.6" + attribute \src "libresoc.v:182625.3-182654.6" + wire $0\wr_detect$10[0:0]$11427 + attribute \src "libresoc.v:182695.3-182724.6" + wire $0\wr_detect$13[0:0]$11441 + attribute \src "libresoc.v:182388.3-182417.6" + wire $0\wr_detect$16[0:0]$11379 + attribute \src "libresoc.v:182485.3-182514.6" + wire $0\wr_detect$4[0:0]$11399 + attribute \src "libresoc.v:182555.3-182584.6" + wire $0\wr_detect$7[0:0]$11413 + attribute \src "libresoc.v:182318.3-182347.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:180970.3-181009.6" - wire width 4 $1\cr_pred3__data_o$next[3:0]$11379 - attribute \src "libresoc.v:180882.13-180882.36" + attribute \src "libresoc.v:182278.3-182317.6" + wire width 4 $1\cr_pred3__data_o$next[3:0]$11363 + attribute \src "libresoc.v:182190.13-182190.36" wire width 4 $1\cr_pred3__data_o[3:0] - attribute \src "libresoc.v:181040.3-181079.6" - wire width 4 $1\r23__data_o$next[3:0]$11388 - attribute \src "libresoc.v:180897.13-180897.31" + attribute \src "libresoc.v:182348.3-182387.6" + wire width 4 $1\r23__data_o$next[3:0]$11372 + attribute \src "libresoc.v:182205.13-182205.31" wire width 4 $1\r23__data_o[3:0] - attribute \src "libresoc.v:181347.3-181386.6" - wire width 4 $1\r3__data_o$next[3:0]$11450 - attribute \src "libresoc.v:180904.13-180904.30" + attribute \src "libresoc.v:182655.3-182694.6" + wire width 4 $1\r3__data_o$next[3:0]$11434 + attribute \src "libresoc.v:182212.13-182212.30" wire width 4 $1\r3__data_o[3:0] - attribute \src "libresoc.v:181110.3-181136.6" - wire width 4 $1\reg$next[3:0]$11402 - attribute \src "libresoc.v:180910.13-180910.25" + attribute \src "libresoc.v:182418.3-182444.6" + wire width 4 $1\reg$next[3:0]$11386 + attribute \src "libresoc.v:182218.13-182218.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:181137.3-181176.6" - wire width 4 $1\src13__data_o$next[3:0]$11408 - attribute \src "libresoc.v:180915.13-180915.33" + attribute \src "libresoc.v:182445.3-182484.6" + wire width 4 $1\src13__data_o$next[3:0]$11392 + attribute \src "libresoc.v:182223.13-182223.33" wire width 4 $1\src13__data_o[3:0] - attribute \src "libresoc.v:181207.3-181246.6" - wire width 4 $1\src23__data_o$next[3:0]$11422 - attribute \src "libresoc.v:180922.13-180922.33" + attribute \src "libresoc.v:182515.3-182554.6" + wire width 4 $1\src23__data_o$next[3:0]$11406 + attribute \src "libresoc.v:182230.13-182230.33" wire width 4 $1\src23__data_o[3:0] - attribute \src "libresoc.v:181277.3-181316.6" - wire width 4 $1\src33__data_o$next[3:0]$11436 - attribute \src "libresoc.v:180929.13-180929.33" + attribute \src "libresoc.v:182585.3-182624.6" + wire width 4 $1\src33__data_o$next[3:0]$11420 + attribute \src "libresoc.v:182237.13-182237.33" wire width 4 $1\src33__data_o[3:0] - attribute \src "libresoc.v:181317.3-181346.6" - wire $1\wr_detect$10[0:0]$11444 - attribute \src "libresoc.v:181387.3-181416.6" - wire $1\wr_detect$13[0:0]$11458 - attribute \src "libresoc.v:181080.3-181109.6" - wire $1\wr_detect$16[0:0]$11396 - attribute \src "libresoc.v:181177.3-181206.6" - wire $1\wr_detect$4[0:0]$11416 - attribute \src "libresoc.v:181247.3-181276.6" - wire $1\wr_detect$7[0:0]$11430 - attribute \src "libresoc.v:181010.3-181039.6" + attribute \src "libresoc.v:182625.3-182654.6" + wire $1\wr_detect$10[0:0]$11428 + attribute \src "libresoc.v:182695.3-182724.6" + wire $1\wr_detect$13[0:0]$11442 + attribute \src "libresoc.v:182388.3-182417.6" + wire $1\wr_detect$16[0:0]$11380 + attribute \src "libresoc.v:182485.3-182514.6" + wire $1\wr_detect$4[0:0]$11400 + attribute \src "libresoc.v:182555.3-182584.6" + wire $1\wr_detect$7[0:0]$11414 + attribute \src "libresoc.v:182318.3-182347.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:180970.3-181009.6" - wire width 4 $2\cr_pred3__data_o$next[3:0]$11380 - attribute \src "libresoc.v:181040.3-181079.6" - wire width 4 $2\r23__data_o$next[3:0]$11389 - attribute \src "libresoc.v:181347.3-181386.6" - wire width 4 $2\r3__data_o$next[3:0]$11451 - attribute \src "libresoc.v:181110.3-181136.6" - wire width 4 $2\reg$next[3:0]$11403 - attribute \src "libresoc.v:181137.3-181176.6" - wire width 4 $2\src13__data_o$next[3:0]$11409 - attribute \src "libresoc.v:181207.3-181246.6" - wire width 4 $2\src23__data_o$next[3:0]$11423 - attribute \src "libresoc.v:181277.3-181316.6" - wire width 4 $2\src33__data_o$next[3:0]$11437 - attribute \src "libresoc.v:181317.3-181346.6" - wire $2\wr_detect$10[0:0]$11445 - attribute \src "libresoc.v:181387.3-181416.6" - wire $2\wr_detect$13[0:0]$11459 - attribute \src "libresoc.v:181080.3-181109.6" - wire $2\wr_detect$16[0:0]$11397 - attribute \src "libresoc.v:181177.3-181206.6" - wire $2\wr_detect$4[0:0]$11417 - attribute \src "libresoc.v:181247.3-181276.6" - wire $2\wr_detect$7[0:0]$11431 - attribute \src "libresoc.v:181010.3-181039.6" + attribute \src "libresoc.v:182278.3-182317.6" + wire width 4 $2\cr_pred3__data_o$next[3:0]$11364 + attribute \src "libresoc.v:182348.3-182387.6" + wire width 4 $2\r23__data_o$next[3:0]$11373 + attribute \src "libresoc.v:182655.3-182694.6" + wire width 4 $2\r3__data_o$next[3:0]$11435 + attribute \src "libresoc.v:182418.3-182444.6" + wire width 4 $2\reg$next[3:0]$11387 + attribute \src "libresoc.v:182445.3-182484.6" + wire width 4 $2\src13__data_o$next[3:0]$11393 + attribute \src "libresoc.v:182515.3-182554.6" + wire width 4 $2\src23__data_o$next[3:0]$11407 + attribute \src "libresoc.v:182585.3-182624.6" + wire width 4 $2\src33__data_o$next[3:0]$11421 + attribute \src "libresoc.v:182625.3-182654.6" + wire $2\wr_detect$10[0:0]$11429 + attribute \src "libresoc.v:182695.3-182724.6" + wire $2\wr_detect$13[0:0]$11443 + attribute \src "libresoc.v:182388.3-182417.6" + wire $2\wr_detect$16[0:0]$11381 + attribute \src "libresoc.v:182485.3-182514.6" + wire $2\wr_detect$4[0:0]$11401 + attribute \src "libresoc.v:182555.3-182584.6" + wire $2\wr_detect$7[0:0]$11415 + attribute \src "libresoc.v:182318.3-182347.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:180970.3-181009.6" - wire width 4 $3\cr_pred3__data_o$next[3:0]$11381 - attribute \src "libresoc.v:181040.3-181079.6" - wire width 4 $3\r23__data_o$next[3:0]$11390 - attribute \src "libresoc.v:181347.3-181386.6" - wire width 4 $3\r3__data_o$next[3:0]$11452 - attribute \src "libresoc.v:181110.3-181136.6" - wire width 4 $3\reg$next[3:0]$11404 - attribute \src "libresoc.v:181137.3-181176.6" - wire width 4 $3\src13__data_o$next[3:0]$11410 - attribute \src "libresoc.v:181207.3-181246.6" - wire width 4 $3\src23__data_o$next[3:0]$11424 - attribute \src "libresoc.v:181277.3-181316.6" - wire width 4 $3\src33__data_o$next[3:0]$11438 - attribute \src "libresoc.v:181317.3-181346.6" - wire $3\wr_detect$10[0:0]$11446 - attribute \src "libresoc.v:181387.3-181416.6" - wire $3\wr_detect$13[0:0]$11460 - attribute \src "libresoc.v:181080.3-181109.6" - wire $3\wr_detect$16[0:0]$11398 - attribute \src "libresoc.v:181177.3-181206.6" - wire $3\wr_detect$4[0:0]$11418 - attribute \src "libresoc.v:181247.3-181276.6" - wire $3\wr_detect$7[0:0]$11432 - attribute \src "libresoc.v:181010.3-181039.6" + attribute \src "libresoc.v:182278.3-182317.6" + wire width 4 $3\cr_pred3__data_o$next[3:0]$11365 + attribute \src "libresoc.v:182348.3-182387.6" + wire width 4 $3\r23__data_o$next[3:0]$11374 + attribute \src "libresoc.v:182655.3-182694.6" + wire width 4 $3\r3__data_o$next[3:0]$11436 + attribute \src "libresoc.v:182418.3-182444.6" + wire width 4 $3\reg$next[3:0]$11388 + attribute \src "libresoc.v:182445.3-182484.6" + wire width 4 $3\src13__data_o$next[3:0]$11394 + attribute \src "libresoc.v:182515.3-182554.6" + wire width 4 $3\src23__data_o$next[3:0]$11408 + attribute \src "libresoc.v:182585.3-182624.6" + wire width 4 $3\src33__data_o$next[3:0]$11422 + attribute \src "libresoc.v:182625.3-182654.6" + wire $3\wr_detect$10[0:0]$11430 + attribute \src "libresoc.v:182695.3-182724.6" + wire $3\wr_detect$13[0:0]$11444 + attribute \src "libresoc.v:182388.3-182417.6" + wire $3\wr_detect$16[0:0]$11382 + attribute \src "libresoc.v:182485.3-182514.6" + wire $3\wr_detect$4[0:0]$11402 + attribute \src "libresoc.v:182555.3-182584.6" + wire $3\wr_detect$7[0:0]$11416 + attribute \src "libresoc.v:182318.3-182347.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:180970.3-181009.6" - wire width 4 $4\cr_pred3__data_o$next[3:0]$11382 - attribute \src "libresoc.v:181040.3-181079.6" - wire width 4 $4\r23__data_o$next[3:0]$11391 - attribute \src "libresoc.v:181347.3-181386.6" - wire width 4 $4\r3__data_o$next[3:0]$11453 - attribute \src "libresoc.v:181110.3-181136.6" - wire width 4 $4\reg$next[3:0]$11405 - attribute \src "libresoc.v:181137.3-181176.6" - wire width 4 $4\src13__data_o$next[3:0]$11411 - attribute \src "libresoc.v:181207.3-181246.6" - wire width 4 $4\src23__data_o$next[3:0]$11425 - attribute \src "libresoc.v:181277.3-181316.6" - wire width 4 $4\src33__data_o$next[3:0]$11439 - attribute \src "libresoc.v:181317.3-181346.6" - wire $4\wr_detect$10[0:0]$11447 - attribute \src "libresoc.v:181387.3-181416.6" - wire $4\wr_detect$13[0:0]$11461 - attribute \src "libresoc.v:181080.3-181109.6" - wire $4\wr_detect$16[0:0]$11399 - attribute \src "libresoc.v:181177.3-181206.6" - wire $4\wr_detect$4[0:0]$11419 - attribute \src "libresoc.v:181247.3-181276.6" - wire $4\wr_detect$7[0:0]$11433 - attribute \src "libresoc.v:181010.3-181039.6" + attribute \src "libresoc.v:182278.3-182317.6" + wire width 4 $4\cr_pred3__data_o$next[3:0]$11366 + attribute \src "libresoc.v:182348.3-182387.6" + wire width 4 $4\r23__data_o$next[3:0]$11375 + attribute \src "libresoc.v:182655.3-182694.6" + wire width 4 $4\r3__data_o$next[3:0]$11437 + attribute \src "libresoc.v:182418.3-182444.6" + wire width 4 $4\reg$next[3:0]$11389 + attribute \src "libresoc.v:182445.3-182484.6" + wire width 4 $4\src13__data_o$next[3:0]$11395 + attribute \src "libresoc.v:182515.3-182554.6" + wire width 4 $4\src23__data_o$next[3:0]$11409 + attribute \src "libresoc.v:182585.3-182624.6" + wire width 4 $4\src33__data_o$next[3:0]$11423 + attribute \src "libresoc.v:182625.3-182654.6" + wire $4\wr_detect$10[0:0]$11431 + attribute \src "libresoc.v:182695.3-182724.6" + wire $4\wr_detect$13[0:0]$11445 + attribute \src "libresoc.v:182388.3-182417.6" + wire $4\wr_detect$16[0:0]$11383 + attribute \src "libresoc.v:182485.3-182514.6" + wire $4\wr_detect$4[0:0]$11403 + attribute \src "libresoc.v:182555.3-182584.6" + wire $4\wr_detect$7[0:0]$11417 + attribute \src "libresoc.v:182318.3-182347.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:180970.3-181009.6" - wire width 4 $5\cr_pred3__data_o$next[3:0]$11383 - attribute \src "libresoc.v:181040.3-181079.6" - wire width 4 $5\r23__data_o$next[3:0]$11392 - attribute \src "libresoc.v:181347.3-181386.6" - wire width 4 $5\r3__data_o$next[3:0]$11454 - attribute \src "libresoc.v:181137.3-181176.6" - wire width 4 $5\src13__data_o$next[3:0]$11412 - attribute \src "libresoc.v:181207.3-181246.6" - wire width 4 $5\src23__data_o$next[3:0]$11426 - attribute \src "libresoc.v:181277.3-181316.6" - wire width 4 $5\src33__data_o$next[3:0]$11440 - attribute \src "libresoc.v:180970.3-181009.6" - wire width 4 $6\cr_pred3__data_o$next[3:0]$11384 - attribute \src "libresoc.v:181040.3-181079.6" - wire width 4 $6\r23__data_o$next[3:0]$11393 - attribute \src "libresoc.v:181347.3-181386.6" - wire width 4 $6\r3__data_o$next[3:0]$11455 - attribute \src "libresoc.v:181137.3-181176.6" - wire width 4 $6\src13__data_o$next[3:0]$11413 - attribute \src "libresoc.v:181207.3-181246.6" - wire width 4 $6\src23__data_o$next[3:0]$11427 - attribute \src "libresoc.v:181277.3-181316.6" - wire width 4 $6\src33__data_o$next[3:0]$11441 - attribute \src "libresoc.v:180950.17-180950.104" - wire $not$libresoc.v:180950$11364_Y - attribute \src "libresoc.v:180951.18-180951.105" - wire $not$libresoc.v:180951$11365_Y - attribute \src "libresoc.v:180952.18-180952.105" - wire $not$libresoc.v:180952$11366_Y - attribute \src "libresoc.v:180953.17-180953.100" - wire $not$libresoc.v:180953$11367_Y - attribute \src "libresoc.v:180954.17-180954.103" - wire $not$libresoc.v:180954$11368_Y - attribute \src "libresoc.v:180955.17-180955.103" - wire $not$libresoc.v:180955$11369_Y + attribute \src "libresoc.v:182278.3-182317.6" + wire width 4 $5\cr_pred3__data_o$next[3:0]$11367 + attribute \src "libresoc.v:182348.3-182387.6" + wire width 4 $5\r23__data_o$next[3:0]$11376 + attribute \src "libresoc.v:182655.3-182694.6" + wire width 4 $5\r3__data_o$next[3:0]$11438 + attribute \src "libresoc.v:182445.3-182484.6" + wire width 4 $5\src13__data_o$next[3:0]$11396 + attribute \src "libresoc.v:182515.3-182554.6" + wire width 4 $5\src23__data_o$next[3:0]$11410 + attribute \src "libresoc.v:182585.3-182624.6" + wire width 4 $5\src33__data_o$next[3:0]$11424 + attribute \src "libresoc.v:182278.3-182317.6" + wire width 4 $6\cr_pred3__data_o$next[3:0]$11368 + attribute \src "libresoc.v:182348.3-182387.6" + wire width 4 $6\r23__data_o$next[3:0]$11377 + attribute \src "libresoc.v:182655.3-182694.6" + wire width 4 $6\r3__data_o$next[3:0]$11439 + attribute \src "libresoc.v:182445.3-182484.6" + wire width 4 $6\src13__data_o$next[3:0]$11397 + attribute \src "libresoc.v:182515.3-182554.6" + wire width 4 $6\src23__data_o$next[3:0]$11411 + attribute \src "libresoc.v:182585.3-182624.6" + wire width 4 $6\src33__data_o$next[3:0]$11425 + attribute \src "libresoc.v:182258.17-182258.104" + wire $not$libresoc.v:182258$11348_Y + attribute \src "libresoc.v:182259.18-182259.105" + wire $not$libresoc.v:182259$11349_Y + attribute \src "libresoc.v:182260.18-182260.105" + wire $not$libresoc.v:182260$11350_Y + attribute \src "libresoc.v:182261.17-182261.100" + wire $not$libresoc.v:182261$11351_Y + attribute \src "libresoc.v:182262.17-182262.103" + wire $not$libresoc.v:182262$11352_Y + attribute \src "libresoc.v:182263.17-182263.103" + wire $not$libresoc.v:182263$11353_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -368924,9 +340294,9 @@ module \reg_3 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 20 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 3 \cr_pred3__data_o @@ -368942,7 +340312,7 @@ module \reg_3 wire width 4 input 13 \dest23__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest23__wen - attribute \src "libresoc.v:180863.7-180863.15" + attribute \src "libresoc.v:182171.7-182171.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 16 \r23__data_o @@ -368995,175 +340365,175 @@ module \reg_3 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180950$11364 + cell $not $not$libresoc.v:182258$11348 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:180950$11364_Y + connect \Y $not$libresoc.v:182258$11348_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180951$11365 + cell $not $not$libresoc.v:182259$11349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:180951$11365_Y + connect \Y $not$libresoc.v:182259$11349_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180952$11366 + cell $not $not$libresoc.v:182260$11350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$16 - connect \Y $not$libresoc.v:180952$11366_Y + connect \Y $not$libresoc.v:182260$11350_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180953$11367 + cell $not $not$libresoc.v:182261$11351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:180953$11367_Y + connect \Y $not$libresoc.v:182261$11351_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180954$11368 + cell $not $not$libresoc.v:182262$11352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:180954$11368_Y + connect \Y $not$libresoc.v:182262$11352_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:180955$11369 + cell $not $not$libresoc.v:182263$11353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:180955$11369_Y + connect \Y $not$libresoc.v:182263$11353_Y end - attribute \src "libresoc.v:180863.7-180863.20" - process $proc$libresoc.v:180863$11462 + attribute \src "libresoc.v:182171.7-182171.20" + process $proc$libresoc.v:182171$11446 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:180882.13-180882.36" - process $proc$libresoc.v:180882$11463 + attribute \src "libresoc.v:182190.13-182190.36" + process $proc$libresoc.v:182190$11447 assign { } { } assign $1\cr_pred3__data_o[3:0] 4'0000 sync always sync init update \cr_pred3__data_o $1\cr_pred3__data_o[3:0] end - attribute \src "libresoc.v:180897.13-180897.31" - process $proc$libresoc.v:180897$11464 + attribute \src "libresoc.v:182205.13-182205.31" + process $proc$libresoc.v:182205$11448 assign { } { } assign $1\r23__data_o[3:0] 4'0000 sync always sync init update \r23__data_o $1\r23__data_o[3:0] end - attribute \src "libresoc.v:180904.13-180904.30" - process $proc$libresoc.v:180904$11465 + attribute \src "libresoc.v:182212.13-182212.30" + process $proc$libresoc.v:182212$11449 assign { } { } assign $1\r3__data_o[3:0] 4'0000 sync always sync init update \r3__data_o $1\r3__data_o[3:0] end - attribute \src "libresoc.v:180910.13-180910.25" - process $proc$libresoc.v:180910$11466 + attribute \src "libresoc.v:182218.13-182218.25" + process $proc$libresoc.v:182218$11450 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:180915.13-180915.33" - process $proc$libresoc.v:180915$11467 + attribute \src "libresoc.v:182223.13-182223.33" + process $proc$libresoc.v:182223$11451 assign { } { } assign $1\src13__data_o[3:0] 4'0000 sync always sync init update \src13__data_o $1\src13__data_o[3:0] end - attribute \src "libresoc.v:180922.13-180922.33" - process $proc$libresoc.v:180922$11468 + attribute \src "libresoc.v:182230.13-182230.33" + process $proc$libresoc.v:182230$11452 assign { } { } assign $1\src23__data_o[3:0] 4'0000 sync always sync init update \src23__data_o $1\src23__data_o[3:0] end - attribute \src "libresoc.v:180929.13-180929.33" - process $proc$libresoc.v:180929$11469 + attribute \src "libresoc.v:182237.13-182237.33" + process $proc$libresoc.v:182237$11453 assign { } { } assign $1\src33__data_o[3:0] 4'0000 sync always sync init update \src33__data_o $1\src33__data_o[3:0] end - attribute \src "libresoc.v:180956.3-180957.25" - process $proc$libresoc.v:180956$11370 + attribute \src "libresoc.v:182264.3-182265.25" + process $proc$libresoc.v:182264$11354 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:180958.3-180959.39" - process $proc$libresoc.v:180958$11371 + attribute \src "libresoc.v:182266.3-182267.39" + process $proc$libresoc.v:182266$11355 assign { } { } assign $0\r23__data_o[3:0] \r23__data_o$next sync posedge \coresync_clk update \r23__data_o $0\r23__data_o[3:0] end - attribute \src "libresoc.v:180960.3-180961.37" - process $proc$libresoc.v:180960$11372 + attribute \src "libresoc.v:182268.3-182269.37" + process $proc$libresoc.v:182268$11356 assign { } { } assign $0\r3__data_o[3:0] \r3__data_o$next sync posedge \coresync_clk update \r3__data_o $0\r3__data_o[3:0] end - attribute \src "libresoc.v:180962.3-180963.43" - process $proc$libresoc.v:180962$11373 + attribute \src "libresoc.v:182270.3-182271.43" + process $proc$libresoc.v:182270$11357 assign { } { } assign $0\src33__data_o[3:0] \src33__data_o$next sync posedge \coresync_clk update \src33__data_o $0\src33__data_o[3:0] end - attribute \src "libresoc.v:180964.3-180965.43" - process $proc$libresoc.v:180964$11374 + attribute \src "libresoc.v:182272.3-182273.43" + process $proc$libresoc.v:182272$11358 assign { } { } assign $0\src23__data_o[3:0] \src23__data_o$next sync posedge \coresync_clk update \src23__data_o $0\src23__data_o[3:0] end - attribute \src "libresoc.v:180966.3-180967.43" - process $proc$libresoc.v:180966$11375 + attribute \src "libresoc.v:182274.3-182275.43" + process $proc$libresoc.v:182274$11359 assign { } { } assign $0\src13__data_o[3:0] \src13__data_o$next sync posedge \coresync_clk update \src13__data_o $0\src13__data_o[3:0] end - attribute \src "libresoc.v:180968.3-180969.49" - process $proc$libresoc.v:180968$11376 + attribute \src "libresoc.v:182276.3-182277.49" + process $proc$libresoc.v:182276$11360 assign { } { } assign $0\cr_pred3__data_o[3:0] \cr_pred3__data_o$next sync posedge \coresync_clk update \cr_pred3__data_o $0\cr_pred3__data_o[3:0] end - attribute \src "libresoc.v:180970.3-181009.6" - process $proc$libresoc.v:180970$11377 + attribute \src "libresoc.v:182278.3-182317.6" + process $proc$libresoc.v:182278$11361 assign { } { } assign { } { } assign { } { } - assign $0\cr_pred3__data_o$next[3:0]$11378 $6\cr_pred3__data_o$next[3:0]$11384 - attribute \src "libresoc.v:180971.5-180971.29" + assign $0\cr_pred3__data_o$next[3:0]$11362 $6\cr_pred3__data_o$next[3:0]$11368 + attribute \src "libresoc.v:182279.5-182279.29" switch \initial - attribute \src "libresoc.v:180971.9-180971.17" + attribute \src "libresoc.v:182279.9-182279.17" case 1'1 case end @@ -369175,66 +340545,66 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\cr_pred3__data_o$next[3:0]$11379 $5\cr_pred3__data_o$next[3:0]$11383 + assign $1\cr_pred3__data_o$next[3:0]$11363 $5\cr_pred3__data_o$next[3:0]$11367 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_pred3__data_o$next[3:0]$11380 \dest13__data_i + assign $2\cr_pred3__data_o$next[3:0]$11364 \dest13__data_i case - assign $2\cr_pred3__data_o$next[3:0]$11380 4'0000 + assign $2\cr_pred3__data_o$next[3:0]$11364 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\cr_pred3__data_o$next[3:0]$11381 \dest23__data_i + assign $3\cr_pred3__data_o$next[3:0]$11365 \dest23__data_i case - assign $3\cr_pred3__data_o$next[3:0]$11381 $2\cr_pred3__data_o$next[3:0]$11380 + assign $3\cr_pred3__data_o$next[3:0]$11365 $2\cr_pred3__data_o$next[3:0]$11364 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cr_pred3__data_o$next[3:0]$11382 \w3__data_i + assign $4\cr_pred3__data_o$next[3:0]$11366 \w3__data_i case - assign $4\cr_pred3__data_o$next[3:0]$11382 $3\cr_pred3__data_o$next[3:0]$11381 + assign $4\cr_pred3__data_o$next[3:0]$11366 $3\cr_pred3__data_o$next[3:0]$11365 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\cr_pred3__data_o$next[3:0]$11383 \reg + assign $5\cr_pred3__data_o$next[3:0]$11367 \reg case - assign $5\cr_pred3__data_o$next[3:0]$11383 $4\cr_pred3__data_o$next[3:0]$11382 + assign $5\cr_pred3__data_o$next[3:0]$11367 $4\cr_pred3__data_o$next[3:0]$11366 end case - assign $1\cr_pred3__data_o$next[3:0]$11379 4'0000 + assign $1\cr_pred3__data_o$next[3:0]$11363 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cr_pred3__data_o$next[3:0]$11384 4'0000 + assign $6\cr_pred3__data_o$next[3:0]$11368 4'0000 case - assign $6\cr_pred3__data_o$next[3:0]$11384 $1\cr_pred3__data_o$next[3:0]$11379 + assign $6\cr_pred3__data_o$next[3:0]$11368 $1\cr_pred3__data_o$next[3:0]$11363 end sync always - update \cr_pred3__data_o$next $0\cr_pred3__data_o$next[3:0]$11378 + update \cr_pred3__data_o$next $0\cr_pred3__data_o$next[3:0]$11362 end - attribute \src "libresoc.v:181010.3-181039.6" - process $proc$libresoc.v:181010$11385 + attribute \src "libresoc.v:182318.3-182347.6" + process $proc$libresoc.v:182318$11369 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:181011.5-181011.29" + attribute \src "libresoc.v:182319.5-182319.29" switch \initial - attribute \src "libresoc.v:181011.9-181011.17" + attribute \src "libresoc.v:182319.9-182319.17" case 1'1 case end @@ -369280,15 +340650,15 @@ module \reg_3 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:181040.3-181079.6" - process $proc$libresoc.v:181040$11386 + attribute \src "libresoc.v:182348.3-182387.6" + process $proc$libresoc.v:182348$11370 assign { } { } assign { } { } assign { } { } - assign $0\r23__data_o$next[3:0]$11387 $6\r23__data_o$next[3:0]$11393 - attribute \src "libresoc.v:181041.5-181041.29" + assign $0\r23__data_o$next[3:0]$11371 $6\r23__data_o$next[3:0]$11377 + attribute \src "libresoc.v:182349.5-182349.29" switch \initial - attribute \src "libresoc.v:181041.9-181041.17" + attribute \src "libresoc.v:182349.9-182349.17" case 1'1 case end @@ -369300,66 +340670,66 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\r23__data_o$next[3:0]$11388 $5\r23__data_o$next[3:0]$11392 + assign $1\r23__data_o$next[3:0]$11372 $5\r23__data_o$next[3:0]$11376 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r23__data_o$next[3:0]$11389 \dest13__data_i + assign $2\r23__data_o$next[3:0]$11373 \dest13__data_i case - assign $2\r23__data_o$next[3:0]$11389 4'0000 + assign $2\r23__data_o$next[3:0]$11373 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r23__data_o$next[3:0]$11390 \dest23__data_i + assign $3\r23__data_o$next[3:0]$11374 \dest23__data_i case - assign $3\r23__data_o$next[3:0]$11390 $2\r23__data_o$next[3:0]$11389 + assign $3\r23__data_o$next[3:0]$11374 $2\r23__data_o$next[3:0]$11373 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r23__data_o$next[3:0]$11391 \w3__data_i + assign $4\r23__data_o$next[3:0]$11375 \w3__data_i case - assign $4\r23__data_o$next[3:0]$11391 $3\r23__data_o$next[3:0]$11390 + assign $4\r23__data_o$next[3:0]$11375 $3\r23__data_o$next[3:0]$11374 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$15 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r23__data_o$next[3:0]$11392 \reg + assign $5\r23__data_o$next[3:0]$11376 \reg case - assign $5\r23__data_o$next[3:0]$11392 $4\r23__data_o$next[3:0]$11391 + assign $5\r23__data_o$next[3:0]$11376 $4\r23__data_o$next[3:0]$11375 end case - assign $1\r23__data_o$next[3:0]$11388 4'0000 + assign $1\r23__data_o$next[3:0]$11372 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r23__data_o$next[3:0]$11393 4'0000 + assign $6\r23__data_o$next[3:0]$11377 4'0000 case - assign $6\r23__data_o$next[3:0]$11393 $1\r23__data_o$next[3:0]$11388 + assign $6\r23__data_o$next[3:0]$11377 $1\r23__data_o$next[3:0]$11372 end sync always - update \r23__data_o$next $0\r23__data_o$next[3:0]$11387 + update \r23__data_o$next $0\r23__data_o$next[3:0]$11371 end - attribute \src "libresoc.v:181080.3-181109.6" - process $proc$libresoc.v:181080$11394 + attribute \src "libresoc.v:182388.3-182417.6" + process $proc$libresoc.v:182388$11378 assign { } { } assign { } { } - assign $0\wr_detect$16[0:0]$11395 $1\wr_detect$16[0:0]$11396 - attribute \src "libresoc.v:181081.5-181081.29" + assign $0\wr_detect$16[0:0]$11379 $1\wr_detect$16[0:0]$11380 + attribute \src "libresoc.v:182389.5-182389.29" switch \initial - attribute \src "libresoc.v:181081.9-181081.17" + attribute \src "libresoc.v:182389.9-182389.17" case 1'1 case end @@ -369371,51 +340741,51 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$16[0:0]$11396 $4\wr_detect$16[0:0]$11399 + assign $1\wr_detect$16[0:0]$11380 $4\wr_detect$16[0:0]$11383 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$16[0:0]$11397 1'1 + assign $2\wr_detect$16[0:0]$11381 1'1 case - assign $2\wr_detect$16[0:0]$11397 1'0 + assign $2\wr_detect$16[0:0]$11381 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$16[0:0]$11398 1'1 + assign $3\wr_detect$16[0:0]$11382 1'1 case - assign $3\wr_detect$16[0:0]$11398 $2\wr_detect$16[0:0]$11397 + assign $3\wr_detect$16[0:0]$11382 $2\wr_detect$16[0:0]$11381 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$16[0:0]$11399 1'1 + assign $4\wr_detect$16[0:0]$11383 1'1 case - assign $4\wr_detect$16[0:0]$11399 $3\wr_detect$16[0:0]$11398 + assign $4\wr_detect$16[0:0]$11383 $3\wr_detect$16[0:0]$11382 end case - assign $1\wr_detect$16[0:0]$11396 1'0 + assign $1\wr_detect$16[0:0]$11380 1'0 end sync always - update \wr_detect$16 $0\wr_detect$16[0:0]$11395 + update \wr_detect$16 $0\wr_detect$16[0:0]$11379 end - attribute \src "libresoc.v:181110.3-181136.6" - process $proc$libresoc.v:181110$11400 + attribute \src "libresoc.v:182418.3-182444.6" + process $proc$libresoc.v:182418$11384 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11401 $4\reg$next[3:0]$11405 - attribute \src "libresoc.v:181111.5-181111.29" + assign $0\reg$next[3:0]$11385 $4\reg$next[3:0]$11389 + attribute \src "libresoc.v:182419.5-182419.29" switch \initial - attribute \src "libresoc.v:181111.9-181111.17" + attribute \src "libresoc.v:182419.9-182419.17" case 1'1 case end @@ -369424,49 +340794,49 @@ module \reg_3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11402 \dest13__data_i + assign $1\reg$next[3:0]$11386 \dest13__data_i case - assign $1\reg$next[3:0]$11402 \reg + assign $1\reg$next[3:0]$11386 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11403 \dest23__data_i + assign $2\reg$next[3:0]$11387 \dest23__data_i case - assign $2\reg$next[3:0]$11403 $1\reg$next[3:0]$11402 + assign $2\reg$next[3:0]$11387 $1\reg$next[3:0]$11386 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11404 \w3__data_i + assign $3\reg$next[3:0]$11388 \w3__data_i case - assign $3\reg$next[3:0]$11404 $2\reg$next[3:0]$11403 + assign $3\reg$next[3:0]$11388 $2\reg$next[3:0]$11387 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11405 4'0000 + assign $4\reg$next[3:0]$11389 4'0000 case - assign $4\reg$next[3:0]$11405 $3\reg$next[3:0]$11404 + assign $4\reg$next[3:0]$11389 $3\reg$next[3:0]$11388 end sync always - update \reg$next $0\reg$next[3:0]$11401 + update \reg$next $0\reg$next[3:0]$11385 end - attribute \src "libresoc.v:181137.3-181176.6" - process $proc$libresoc.v:181137$11406 + attribute \src "libresoc.v:182445.3-182484.6" + process $proc$libresoc.v:182445$11390 assign { } { } assign { } { } assign { } { } - assign $0\src13__data_o$next[3:0]$11407 $6\src13__data_o$next[3:0]$11413 - attribute \src "libresoc.v:181138.5-181138.29" + assign $0\src13__data_o$next[3:0]$11391 $6\src13__data_o$next[3:0]$11397 + attribute \src "libresoc.v:182446.5-182446.29" switch \initial - attribute \src "libresoc.v:181138.9-181138.17" + attribute \src "libresoc.v:182446.9-182446.17" case 1'1 case end @@ -369478,66 +340848,66 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\src13__data_o$next[3:0]$11408 $5\src13__data_o$next[3:0]$11412 + assign $1\src13__data_o$next[3:0]$11392 $5\src13__data_o$next[3:0]$11396 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src13__data_o$next[3:0]$11409 \dest13__data_i + assign $2\src13__data_o$next[3:0]$11393 \dest13__data_i case - assign $2\src13__data_o$next[3:0]$11409 4'0000 + assign $2\src13__data_o$next[3:0]$11393 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src13__data_o$next[3:0]$11410 \dest23__data_i + assign $3\src13__data_o$next[3:0]$11394 \dest23__data_i case - assign $3\src13__data_o$next[3:0]$11410 $2\src13__data_o$next[3:0]$11409 + assign $3\src13__data_o$next[3:0]$11394 $2\src13__data_o$next[3:0]$11393 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src13__data_o$next[3:0]$11411 \w3__data_i + assign $4\src13__data_o$next[3:0]$11395 \w3__data_i case - assign $4\src13__data_o$next[3:0]$11411 $3\src13__data_o$next[3:0]$11410 + assign $4\src13__data_o$next[3:0]$11395 $3\src13__data_o$next[3:0]$11394 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src13__data_o$next[3:0]$11412 \reg + assign $5\src13__data_o$next[3:0]$11396 \reg case - assign $5\src13__data_o$next[3:0]$11412 $4\src13__data_o$next[3:0]$11411 + assign $5\src13__data_o$next[3:0]$11396 $4\src13__data_o$next[3:0]$11395 end case - assign $1\src13__data_o$next[3:0]$11408 4'0000 + assign $1\src13__data_o$next[3:0]$11392 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src13__data_o$next[3:0]$11413 4'0000 + assign $6\src13__data_o$next[3:0]$11397 4'0000 case - assign $6\src13__data_o$next[3:0]$11413 $1\src13__data_o$next[3:0]$11408 + assign $6\src13__data_o$next[3:0]$11397 $1\src13__data_o$next[3:0]$11392 end sync always - update \src13__data_o$next $0\src13__data_o$next[3:0]$11407 + update \src13__data_o$next $0\src13__data_o$next[3:0]$11391 end - attribute \src "libresoc.v:181177.3-181206.6" - process $proc$libresoc.v:181177$11414 + attribute \src "libresoc.v:182485.3-182514.6" + process $proc$libresoc.v:182485$11398 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11415 $1\wr_detect$4[0:0]$11416 - attribute \src "libresoc.v:181178.5-181178.29" + assign $0\wr_detect$4[0:0]$11399 $1\wr_detect$4[0:0]$11400 + attribute \src "libresoc.v:182486.5-182486.29" switch \initial - attribute \src "libresoc.v:181178.9-181178.17" + attribute \src "libresoc.v:182486.9-182486.17" case 1'1 case end @@ -369549,49 +340919,49 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11416 $4\wr_detect$4[0:0]$11419 + assign $1\wr_detect$4[0:0]$11400 $4\wr_detect$4[0:0]$11403 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11417 1'1 + assign $2\wr_detect$4[0:0]$11401 1'1 case - assign $2\wr_detect$4[0:0]$11417 1'0 + assign $2\wr_detect$4[0:0]$11401 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11418 1'1 + assign $3\wr_detect$4[0:0]$11402 1'1 case - assign $3\wr_detect$4[0:0]$11418 $2\wr_detect$4[0:0]$11417 + assign $3\wr_detect$4[0:0]$11402 $2\wr_detect$4[0:0]$11401 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11419 1'1 + assign $4\wr_detect$4[0:0]$11403 1'1 case - assign $4\wr_detect$4[0:0]$11419 $3\wr_detect$4[0:0]$11418 + assign $4\wr_detect$4[0:0]$11403 $3\wr_detect$4[0:0]$11402 end case - assign $1\wr_detect$4[0:0]$11416 1'0 + assign $1\wr_detect$4[0:0]$11400 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11415 + update \wr_detect$4 $0\wr_detect$4[0:0]$11399 end - attribute \src "libresoc.v:181207.3-181246.6" - process $proc$libresoc.v:181207$11420 + attribute \src "libresoc.v:182515.3-182554.6" + process $proc$libresoc.v:182515$11404 assign { } { } assign { } { } assign { } { } - assign $0\src23__data_o$next[3:0]$11421 $6\src23__data_o$next[3:0]$11427 - attribute \src "libresoc.v:181208.5-181208.29" + assign $0\src23__data_o$next[3:0]$11405 $6\src23__data_o$next[3:0]$11411 + attribute \src "libresoc.v:182516.5-182516.29" switch \initial - attribute \src "libresoc.v:181208.9-181208.17" + attribute \src "libresoc.v:182516.9-182516.17" case 1'1 case end @@ -369603,66 +340973,66 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\src23__data_o$next[3:0]$11422 $5\src23__data_o$next[3:0]$11426 + assign $1\src23__data_o$next[3:0]$11406 $5\src23__data_o$next[3:0]$11410 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src23__data_o$next[3:0]$11423 \dest13__data_i + assign $2\src23__data_o$next[3:0]$11407 \dest13__data_i case - assign $2\src23__data_o$next[3:0]$11423 4'0000 + assign $2\src23__data_o$next[3:0]$11407 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src23__data_o$next[3:0]$11424 \dest23__data_i + assign $3\src23__data_o$next[3:0]$11408 \dest23__data_i case - assign $3\src23__data_o$next[3:0]$11424 $2\src23__data_o$next[3:0]$11423 + assign $3\src23__data_o$next[3:0]$11408 $2\src23__data_o$next[3:0]$11407 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src23__data_o$next[3:0]$11425 \w3__data_i + assign $4\src23__data_o$next[3:0]$11409 \w3__data_i case - assign $4\src23__data_o$next[3:0]$11425 $3\src23__data_o$next[3:0]$11424 + assign $4\src23__data_o$next[3:0]$11409 $3\src23__data_o$next[3:0]$11408 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src23__data_o$next[3:0]$11426 \reg + assign $5\src23__data_o$next[3:0]$11410 \reg case - assign $5\src23__data_o$next[3:0]$11426 $4\src23__data_o$next[3:0]$11425 + assign $5\src23__data_o$next[3:0]$11410 $4\src23__data_o$next[3:0]$11409 end case - assign $1\src23__data_o$next[3:0]$11422 4'0000 + assign $1\src23__data_o$next[3:0]$11406 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src23__data_o$next[3:0]$11427 4'0000 + assign $6\src23__data_o$next[3:0]$11411 4'0000 case - assign $6\src23__data_o$next[3:0]$11427 $1\src23__data_o$next[3:0]$11422 + assign $6\src23__data_o$next[3:0]$11411 $1\src23__data_o$next[3:0]$11406 end sync always - update \src23__data_o$next $0\src23__data_o$next[3:0]$11421 + update \src23__data_o$next $0\src23__data_o$next[3:0]$11405 end - attribute \src "libresoc.v:181247.3-181276.6" - process $proc$libresoc.v:181247$11428 + attribute \src "libresoc.v:182555.3-182584.6" + process $proc$libresoc.v:182555$11412 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11429 $1\wr_detect$7[0:0]$11430 - attribute \src "libresoc.v:181248.5-181248.29" + assign $0\wr_detect$7[0:0]$11413 $1\wr_detect$7[0:0]$11414 + attribute \src "libresoc.v:182556.5-182556.29" switch \initial - attribute \src "libresoc.v:181248.9-181248.17" + attribute \src "libresoc.v:182556.9-182556.17" case 1'1 case end @@ -369674,49 +341044,49 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11430 $4\wr_detect$7[0:0]$11433 + assign $1\wr_detect$7[0:0]$11414 $4\wr_detect$7[0:0]$11417 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11431 1'1 + assign $2\wr_detect$7[0:0]$11415 1'1 case - assign $2\wr_detect$7[0:0]$11431 1'0 + assign $2\wr_detect$7[0:0]$11415 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11432 1'1 + assign $3\wr_detect$7[0:0]$11416 1'1 case - assign $3\wr_detect$7[0:0]$11432 $2\wr_detect$7[0:0]$11431 + assign $3\wr_detect$7[0:0]$11416 $2\wr_detect$7[0:0]$11415 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11433 1'1 + assign $4\wr_detect$7[0:0]$11417 1'1 case - assign $4\wr_detect$7[0:0]$11433 $3\wr_detect$7[0:0]$11432 + assign $4\wr_detect$7[0:0]$11417 $3\wr_detect$7[0:0]$11416 end case - assign $1\wr_detect$7[0:0]$11430 1'0 + assign $1\wr_detect$7[0:0]$11414 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11429 + update \wr_detect$7 $0\wr_detect$7[0:0]$11413 end - attribute \src "libresoc.v:181277.3-181316.6" - process $proc$libresoc.v:181277$11434 + attribute \src "libresoc.v:182585.3-182624.6" + process $proc$libresoc.v:182585$11418 assign { } { } assign { } { } assign { } { } - assign $0\src33__data_o$next[3:0]$11435 $6\src33__data_o$next[3:0]$11441 - attribute \src "libresoc.v:181278.5-181278.29" + assign $0\src33__data_o$next[3:0]$11419 $6\src33__data_o$next[3:0]$11425 + attribute \src "libresoc.v:182586.5-182586.29" switch \initial - attribute \src "libresoc.v:181278.9-181278.17" + attribute \src "libresoc.v:182586.9-182586.17" case 1'1 case end @@ -369728,66 +341098,66 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\src33__data_o$next[3:0]$11436 $5\src33__data_o$next[3:0]$11440 + assign $1\src33__data_o$next[3:0]$11420 $5\src33__data_o$next[3:0]$11424 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src33__data_o$next[3:0]$11437 \dest13__data_i + assign $2\src33__data_o$next[3:0]$11421 \dest13__data_i case - assign $2\src33__data_o$next[3:0]$11437 4'0000 + assign $2\src33__data_o$next[3:0]$11421 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src33__data_o$next[3:0]$11438 \dest23__data_i + assign $3\src33__data_o$next[3:0]$11422 \dest23__data_i case - assign $3\src33__data_o$next[3:0]$11438 $2\src33__data_o$next[3:0]$11437 + assign $3\src33__data_o$next[3:0]$11422 $2\src33__data_o$next[3:0]$11421 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src33__data_o$next[3:0]$11439 \w3__data_i + assign $4\src33__data_o$next[3:0]$11423 \w3__data_i case - assign $4\src33__data_o$next[3:0]$11439 $3\src33__data_o$next[3:0]$11438 + assign $4\src33__data_o$next[3:0]$11423 $3\src33__data_o$next[3:0]$11422 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src33__data_o$next[3:0]$11440 \reg + assign $5\src33__data_o$next[3:0]$11424 \reg case - assign $5\src33__data_o$next[3:0]$11440 $4\src33__data_o$next[3:0]$11439 + assign $5\src33__data_o$next[3:0]$11424 $4\src33__data_o$next[3:0]$11423 end case - assign $1\src33__data_o$next[3:0]$11436 4'0000 + assign $1\src33__data_o$next[3:0]$11420 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src33__data_o$next[3:0]$11441 4'0000 + assign $6\src33__data_o$next[3:0]$11425 4'0000 case - assign $6\src33__data_o$next[3:0]$11441 $1\src33__data_o$next[3:0]$11436 + assign $6\src33__data_o$next[3:0]$11425 $1\src33__data_o$next[3:0]$11420 end sync always - update \src33__data_o$next $0\src33__data_o$next[3:0]$11435 + update \src33__data_o$next $0\src33__data_o$next[3:0]$11419 end - attribute \src "libresoc.v:181317.3-181346.6" - process $proc$libresoc.v:181317$11442 + attribute \src "libresoc.v:182625.3-182654.6" + process $proc$libresoc.v:182625$11426 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11443 $1\wr_detect$10[0:0]$11444 - attribute \src "libresoc.v:181318.5-181318.29" + assign $0\wr_detect$10[0:0]$11427 $1\wr_detect$10[0:0]$11428 + attribute \src "libresoc.v:182626.5-182626.29" switch \initial - attribute \src "libresoc.v:181318.9-181318.17" + attribute \src "libresoc.v:182626.9-182626.17" case 1'1 case end @@ -369799,49 +341169,49 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11444 $4\wr_detect$10[0:0]$11447 + assign $1\wr_detect$10[0:0]$11428 $4\wr_detect$10[0:0]$11431 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11445 1'1 + assign $2\wr_detect$10[0:0]$11429 1'1 case - assign $2\wr_detect$10[0:0]$11445 1'0 + assign $2\wr_detect$10[0:0]$11429 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11446 1'1 + assign $3\wr_detect$10[0:0]$11430 1'1 case - assign $3\wr_detect$10[0:0]$11446 $2\wr_detect$10[0:0]$11445 + assign $3\wr_detect$10[0:0]$11430 $2\wr_detect$10[0:0]$11429 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11447 1'1 + assign $4\wr_detect$10[0:0]$11431 1'1 case - assign $4\wr_detect$10[0:0]$11447 $3\wr_detect$10[0:0]$11446 + assign $4\wr_detect$10[0:0]$11431 $3\wr_detect$10[0:0]$11430 end case - assign $1\wr_detect$10[0:0]$11444 1'0 + assign $1\wr_detect$10[0:0]$11428 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11443 + update \wr_detect$10 $0\wr_detect$10[0:0]$11427 end - attribute \src "libresoc.v:181347.3-181386.6" - process $proc$libresoc.v:181347$11448 + attribute \src "libresoc.v:182655.3-182694.6" + process $proc$libresoc.v:182655$11432 assign { } { } assign { } { } assign { } { } - assign $0\r3__data_o$next[3:0]$11449 $6\r3__data_o$next[3:0]$11455 - attribute \src "libresoc.v:181348.5-181348.29" + assign $0\r3__data_o$next[3:0]$11433 $6\r3__data_o$next[3:0]$11439 + attribute \src "libresoc.v:182656.5-182656.29" switch \initial - attribute \src "libresoc.v:181348.9-181348.17" + attribute \src "libresoc.v:182656.9-182656.17" case 1'1 case end @@ -369853,66 +341223,66 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\r3__data_o$next[3:0]$11450 $5\r3__data_o$next[3:0]$11454 + assign $1\r3__data_o$next[3:0]$11434 $5\r3__data_o$next[3:0]$11438 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r3__data_o$next[3:0]$11451 \dest13__data_i + assign $2\r3__data_o$next[3:0]$11435 \dest13__data_i case - assign $2\r3__data_o$next[3:0]$11451 4'0000 + assign $2\r3__data_o$next[3:0]$11435 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r3__data_o$next[3:0]$11452 \dest23__data_i + assign $3\r3__data_o$next[3:0]$11436 \dest23__data_i case - assign $3\r3__data_o$next[3:0]$11452 $2\r3__data_o$next[3:0]$11451 + assign $3\r3__data_o$next[3:0]$11436 $2\r3__data_o$next[3:0]$11435 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r3__data_o$next[3:0]$11453 \w3__data_i + assign $4\r3__data_o$next[3:0]$11437 \w3__data_i case - assign $4\r3__data_o$next[3:0]$11453 $3\r3__data_o$next[3:0]$11452 + assign $4\r3__data_o$next[3:0]$11437 $3\r3__data_o$next[3:0]$11436 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r3__data_o$next[3:0]$11454 \reg + assign $5\r3__data_o$next[3:0]$11438 \reg case - assign $5\r3__data_o$next[3:0]$11454 $4\r3__data_o$next[3:0]$11453 + assign $5\r3__data_o$next[3:0]$11438 $4\r3__data_o$next[3:0]$11437 end case - assign $1\r3__data_o$next[3:0]$11450 4'0000 + assign $1\r3__data_o$next[3:0]$11434 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r3__data_o$next[3:0]$11455 4'0000 + assign $6\r3__data_o$next[3:0]$11439 4'0000 case - assign $6\r3__data_o$next[3:0]$11455 $1\r3__data_o$next[3:0]$11450 + assign $6\r3__data_o$next[3:0]$11439 $1\r3__data_o$next[3:0]$11434 end sync always - update \r3__data_o$next $0\r3__data_o$next[3:0]$11449 + update \r3__data_o$next $0\r3__data_o$next[3:0]$11433 end - attribute \src "libresoc.v:181387.3-181416.6" - process $proc$libresoc.v:181387$11456 + attribute \src "libresoc.v:182695.3-182724.6" + process $proc$libresoc.v:182695$11440 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11457 $1\wr_detect$13[0:0]$11458 - attribute \src "libresoc.v:181388.5-181388.29" + assign $0\wr_detect$13[0:0]$11441 $1\wr_detect$13[0:0]$11442 + attribute \src "libresoc.v:182696.5-182696.29" switch \initial - attribute \src "libresoc.v:181388.9-181388.17" + attribute \src "libresoc.v:182696.9-182696.17" case 1'1 case end @@ -369924,248 +341294,248 @@ module \reg_3 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11458 $4\wr_detect$13[0:0]$11461 + assign $1\wr_detect$13[0:0]$11442 $4\wr_detect$13[0:0]$11445 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest13__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11459 1'1 + assign $2\wr_detect$13[0:0]$11443 1'1 case - assign $2\wr_detect$13[0:0]$11459 1'0 + assign $2\wr_detect$13[0:0]$11443 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest23__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11460 1'1 + assign $3\wr_detect$13[0:0]$11444 1'1 case - assign $3\wr_detect$13[0:0]$11460 $2\wr_detect$13[0:0]$11459 + assign $3\wr_detect$13[0:0]$11444 $2\wr_detect$13[0:0]$11443 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w3__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11461 1'1 + assign $4\wr_detect$13[0:0]$11445 1'1 case - assign $4\wr_detect$13[0:0]$11461 $3\wr_detect$13[0:0]$11460 + assign $4\wr_detect$13[0:0]$11445 $3\wr_detect$13[0:0]$11444 end case - assign $1\wr_detect$13[0:0]$11458 1'0 + assign $1\wr_detect$13[0:0]$11442 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11457 + update \wr_detect$13 $0\wr_detect$13[0:0]$11441 end - connect \$9 $not$libresoc.v:180950$11364_Y - connect \$12 $not$libresoc.v:180951$11365_Y - connect \$15 $not$libresoc.v:180952$11366_Y - connect \$1 $not$libresoc.v:180953$11367_Y - connect \$3 $not$libresoc.v:180954$11368_Y - connect \$6 $not$libresoc.v:180955$11369_Y + connect \$9 $not$libresoc.v:182258$11348_Y + connect \$12 $not$libresoc.v:182259$11349_Y + connect \$15 $not$libresoc.v:182260$11350_Y + connect \$1 $not$libresoc.v:182261$11351_Y + connect \$3 $not$libresoc.v:182262$11352_Y + connect \$6 $not$libresoc.v:182263$11353_Y end -attribute \src "libresoc.v:181421.1-181976.10" +attribute \src "libresoc.v:182729.1-183284.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_4" attribute \generator "nMigen" module \reg_4 - attribute \src "libresoc.v:181529.3-181568.6" - wire width 4 $0\cr_pred4__data_o$next[3:0]$11484 - attribute \src "libresoc.v:181527.3-181528.49" + attribute \src "libresoc.v:182837.3-182876.6" + wire width 4 $0\cr_pred4__data_o$next[3:0]$11468 + attribute \src "libresoc.v:182835.3-182836.49" wire width 4 $0\cr_pred4__data_o[3:0] - attribute \src "libresoc.v:181422.7-181422.20" + attribute \src "libresoc.v:182730.7-182730.20" wire $0\initial[0:0] - attribute \src "libresoc.v:181599.3-181638.6" - wire width 4 $0\r24__data_o$next[3:0]$11493 - attribute \src "libresoc.v:181517.3-181518.39" + attribute \src "libresoc.v:182907.3-182946.6" + wire width 4 $0\r24__data_o$next[3:0]$11477 + attribute \src "libresoc.v:182825.3-182826.39" wire width 4 $0\r24__data_o[3:0] - attribute \src "libresoc.v:181906.3-181945.6" - wire width 4 $0\r4__data_o$next[3:0]$11555 - attribute \src "libresoc.v:181519.3-181520.37" + attribute \src "libresoc.v:183214.3-183253.6" + wire width 4 $0\r4__data_o$next[3:0]$11539 + attribute \src "libresoc.v:182827.3-182828.37" wire width 4 $0\r4__data_o[3:0] - attribute \src "libresoc.v:181669.3-181695.6" - wire width 4 $0\reg$next[3:0]$11507 - attribute \src "libresoc.v:181515.3-181516.25" + attribute \src "libresoc.v:182977.3-183003.6" + wire width 4 $0\reg$next[3:0]$11491 + attribute \src "libresoc.v:182823.3-182824.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:181696.3-181735.6" - wire width 4 $0\src14__data_o$next[3:0]$11513 - attribute \src "libresoc.v:181525.3-181526.43" + attribute \src "libresoc.v:183004.3-183043.6" + wire width 4 $0\src14__data_o$next[3:0]$11497 + attribute \src "libresoc.v:182833.3-182834.43" wire width 4 $0\src14__data_o[3:0] - attribute \src "libresoc.v:181766.3-181805.6" - wire width 4 $0\src24__data_o$next[3:0]$11527 - attribute \src "libresoc.v:181523.3-181524.43" + attribute \src "libresoc.v:183074.3-183113.6" + wire width 4 $0\src24__data_o$next[3:0]$11511 + attribute \src "libresoc.v:182831.3-182832.43" wire width 4 $0\src24__data_o[3:0] - attribute \src "libresoc.v:181836.3-181875.6" - wire width 4 $0\src34__data_o$next[3:0]$11541 - attribute \src "libresoc.v:181521.3-181522.43" + attribute \src "libresoc.v:183144.3-183183.6" + wire width 4 $0\src34__data_o$next[3:0]$11525 + attribute \src "libresoc.v:182829.3-182830.43" wire width 4 $0\src34__data_o[3:0] - attribute \src "libresoc.v:181876.3-181905.6" - wire $0\wr_detect$10[0:0]$11549 - attribute \src "libresoc.v:181946.3-181975.6" - wire $0\wr_detect$13[0:0]$11563 - attribute \src "libresoc.v:181639.3-181668.6" - wire $0\wr_detect$16[0:0]$11501 - attribute \src "libresoc.v:181736.3-181765.6" - wire $0\wr_detect$4[0:0]$11521 - attribute \src "libresoc.v:181806.3-181835.6" - wire $0\wr_detect$7[0:0]$11535 - attribute \src "libresoc.v:181569.3-181598.6" + attribute \src "libresoc.v:183184.3-183213.6" + wire $0\wr_detect$10[0:0]$11533 + attribute \src "libresoc.v:183254.3-183283.6" + wire $0\wr_detect$13[0:0]$11547 + attribute \src "libresoc.v:182947.3-182976.6" + wire $0\wr_detect$16[0:0]$11485 + attribute \src "libresoc.v:183044.3-183073.6" + wire $0\wr_detect$4[0:0]$11505 + attribute \src "libresoc.v:183114.3-183143.6" + wire $0\wr_detect$7[0:0]$11519 + attribute \src "libresoc.v:182877.3-182906.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:181529.3-181568.6" - wire width 4 $1\cr_pred4__data_o$next[3:0]$11485 - attribute \src "libresoc.v:181441.13-181441.36" + attribute \src "libresoc.v:182837.3-182876.6" + wire width 4 $1\cr_pred4__data_o$next[3:0]$11469 + attribute \src "libresoc.v:182749.13-182749.36" wire width 4 $1\cr_pred4__data_o[3:0] - attribute \src "libresoc.v:181599.3-181638.6" - wire width 4 $1\r24__data_o$next[3:0]$11494 - attribute \src "libresoc.v:181456.13-181456.31" + attribute \src "libresoc.v:182907.3-182946.6" + wire width 4 $1\r24__data_o$next[3:0]$11478 + attribute \src "libresoc.v:182764.13-182764.31" wire width 4 $1\r24__data_o[3:0] - attribute \src "libresoc.v:181906.3-181945.6" - wire width 4 $1\r4__data_o$next[3:0]$11556 - attribute \src "libresoc.v:181463.13-181463.30" + attribute \src "libresoc.v:183214.3-183253.6" + wire width 4 $1\r4__data_o$next[3:0]$11540 + attribute \src "libresoc.v:182771.13-182771.30" wire width 4 $1\r4__data_o[3:0] - attribute \src "libresoc.v:181669.3-181695.6" - wire width 4 $1\reg$next[3:0]$11508 - attribute \src "libresoc.v:181469.13-181469.25" + attribute \src "libresoc.v:182977.3-183003.6" + wire width 4 $1\reg$next[3:0]$11492 + attribute \src "libresoc.v:182777.13-182777.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:181696.3-181735.6" - wire width 4 $1\src14__data_o$next[3:0]$11514 - attribute \src "libresoc.v:181474.13-181474.33" + attribute \src "libresoc.v:183004.3-183043.6" + wire width 4 $1\src14__data_o$next[3:0]$11498 + attribute \src "libresoc.v:182782.13-182782.33" wire width 4 $1\src14__data_o[3:0] - attribute \src "libresoc.v:181766.3-181805.6" - wire width 4 $1\src24__data_o$next[3:0]$11528 - attribute \src "libresoc.v:181481.13-181481.33" + attribute \src "libresoc.v:183074.3-183113.6" + wire width 4 $1\src24__data_o$next[3:0]$11512 + attribute \src "libresoc.v:182789.13-182789.33" wire width 4 $1\src24__data_o[3:0] - attribute \src "libresoc.v:181836.3-181875.6" - wire width 4 $1\src34__data_o$next[3:0]$11542 - attribute \src "libresoc.v:181488.13-181488.33" + attribute \src "libresoc.v:183144.3-183183.6" + wire width 4 $1\src34__data_o$next[3:0]$11526 + attribute \src "libresoc.v:182796.13-182796.33" wire width 4 $1\src34__data_o[3:0] - attribute \src "libresoc.v:181876.3-181905.6" - wire $1\wr_detect$10[0:0]$11550 - attribute \src "libresoc.v:181946.3-181975.6" - wire $1\wr_detect$13[0:0]$11564 - attribute \src "libresoc.v:181639.3-181668.6" - wire $1\wr_detect$16[0:0]$11502 - attribute \src "libresoc.v:181736.3-181765.6" - wire $1\wr_detect$4[0:0]$11522 - attribute \src "libresoc.v:181806.3-181835.6" - wire $1\wr_detect$7[0:0]$11536 - attribute \src "libresoc.v:181569.3-181598.6" + attribute \src "libresoc.v:183184.3-183213.6" + wire $1\wr_detect$10[0:0]$11534 + attribute \src "libresoc.v:183254.3-183283.6" + wire $1\wr_detect$13[0:0]$11548 + attribute \src "libresoc.v:182947.3-182976.6" + wire $1\wr_detect$16[0:0]$11486 + attribute \src "libresoc.v:183044.3-183073.6" + wire $1\wr_detect$4[0:0]$11506 + attribute \src "libresoc.v:183114.3-183143.6" + wire $1\wr_detect$7[0:0]$11520 + attribute \src "libresoc.v:182877.3-182906.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:181529.3-181568.6" - wire width 4 $2\cr_pred4__data_o$next[3:0]$11486 - attribute \src "libresoc.v:181599.3-181638.6" - wire width 4 $2\r24__data_o$next[3:0]$11495 - attribute \src "libresoc.v:181906.3-181945.6" - wire width 4 $2\r4__data_o$next[3:0]$11557 - attribute \src "libresoc.v:181669.3-181695.6" - wire width 4 $2\reg$next[3:0]$11509 - attribute \src "libresoc.v:181696.3-181735.6" - wire width 4 $2\src14__data_o$next[3:0]$11515 - attribute \src "libresoc.v:181766.3-181805.6" - wire width 4 $2\src24__data_o$next[3:0]$11529 - attribute \src "libresoc.v:181836.3-181875.6" - wire width 4 $2\src34__data_o$next[3:0]$11543 - attribute \src "libresoc.v:181876.3-181905.6" - wire $2\wr_detect$10[0:0]$11551 - attribute \src "libresoc.v:181946.3-181975.6" - wire $2\wr_detect$13[0:0]$11565 - attribute \src "libresoc.v:181639.3-181668.6" - wire $2\wr_detect$16[0:0]$11503 - attribute \src "libresoc.v:181736.3-181765.6" - wire $2\wr_detect$4[0:0]$11523 - attribute \src "libresoc.v:181806.3-181835.6" - wire $2\wr_detect$7[0:0]$11537 - attribute \src "libresoc.v:181569.3-181598.6" + attribute \src "libresoc.v:182837.3-182876.6" + wire width 4 $2\cr_pred4__data_o$next[3:0]$11470 + attribute \src "libresoc.v:182907.3-182946.6" + wire width 4 $2\r24__data_o$next[3:0]$11479 + attribute \src "libresoc.v:183214.3-183253.6" + wire width 4 $2\r4__data_o$next[3:0]$11541 + attribute \src "libresoc.v:182977.3-183003.6" + wire width 4 $2\reg$next[3:0]$11493 + attribute \src "libresoc.v:183004.3-183043.6" + wire width 4 $2\src14__data_o$next[3:0]$11499 + attribute \src "libresoc.v:183074.3-183113.6" + wire width 4 $2\src24__data_o$next[3:0]$11513 + attribute \src "libresoc.v:183144.3-183183.6" + wire width 4 $2\src34__data_o$next[3:0]$11527 + attribute \src "libresoc.v:183184.3-183213.6" + wire $2\wr_detect$10[0:0]$11535 + attribute \src "libresoc.v:183254.3-183283.6" + wire $2\wr_detect$13[0:0]$11549 + attribute \src "libresoc.v:182947.3-182976.6" + wire $2\wr_detect$16[0:0]$11487 + attribute \src "libresoc.v:183044.3-183073.6" + wire $2\wr_detect$4[0:0]$11507 + attribute \src "libresoc.v:183114.3-183143.6" + wire $2\wr_detect$7[0:0]$11521 + attribute \src "libresoc.v:182877.3-182906.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:181529.3-181568.6" - wire width 4 $3\cr_pred4__data_o$next[3:0]$11487 - attribute \src "libresoc.v:181599.3-181638.6" - wire width 4 $3\r24__data_o$next[3:0]$11496 - attribute \src "libresoc.v:181906.3-181945.6" - wire width 4 $3\r4__data_o$next[3:0]$11558 - attribute \src "libresoc.v:181669.3-181695.6" - wire width 4 $3\reg$next[3:0]$11510 - attribute \src "libresoc.v:181696.3-181735.6" - wire width 4 $3\src14__data_o$next[3:0]$11516 - attribute \src "libresoc.v:181766.3-181805.6" - wire width 4 $3\src24__data_o$next[3:0]$11530 - attribute \src "libresoc.v:181836.3-181875.6" - wire width 4 $3\src34__data_o$next[3:0]$11544 - attribute \src "libresoc.v:181876.3-181905.6" - wire $3\wr_detect$10[0:0]$11552 - attribute \src "libresoc.v:181946.3-181975.6" - wire $3\wr_detect$13[0:0]$11566 - attribute \src "libresoc.v:181639.3-181668.6" - wire $3\wr_detect$16[0:0]$11504 - attribute \src "libresoc.v:181736.3-181765.6" - wire $3\wr_detect$4[0:0]$11524 - attribute \src "libresoc.v:181806.3-181835.6" - wire $3\wr_detect$7[0:0]$11538 - attribute \src "libresoc.v:181569.3-181598.6" + attribute \src "libresoc.v:182837.3-182876.6" + wire width 4 $3\cr_pred4__data_o$next[3:0]$11471 + attribute \src "libresoc.v:182907.3-182946.6" + wire width 4 $3\r24__data_o$next[3:0]$11480 + attribute \src "libresoc.v:183214.3-183253.6" + wire width 4 $3\r4__data_o$next[3:0]$11542 + attribute \src "libresoc.v:182977.3-183003.6" + wire width 4 $3\reg$next[3:0]$11494 + attribute \src "libresoc.v:183004.3-183043.6" + wire width 4 $3\src14__data_o$next[3:0]$11500 + attribute \src "libresoc.v:183074.3-183113.6" + wire width 4 $3\src24__data_o$next[3:0]$11514 + attribute \src "libresoc.v:183144.3-183183.6" + wire width 4 $3\src34__data_o$next[3:0]$11528 + attribute \src "libresoc.v:183184.3-183213.6" + wire $3\wr_detect$10[0:0]$11536 + attribute \src "libresoc.v:183254.3-183283.6" + wire $3\wr_detect$13[0:0]$11550 + attribute \src "libresoc.v:182947.3-182976.6" + wire $3\wr_detect$16[0:0]$11488 + attribute \src "libresoc.v:183044.3-183073.6" + wire $3\wr_detect$4[0:0]$11508 + attribute \src "libresoc.v:183114.3-183143.6" + wire $3\wr_detect$7[0:0]$11522 + attribute \src "libresoc.v:182877.3-182906.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:181529.3-181568.6" - wire width 4 $4\cr_pred4__data_o$next[3:0]$11488 - attribute \src "libresoc.v:181599.3-181638.6" - wire width 4 $4\r24__data_o$next[3:0]$11497 - attribute \src "libresoc.v:181906.3-181945.6" - wire width 4 $4\r4__data_o$next[3:0]$11559 - attribute \src "libresoc.v:181669.3-181695.6" - wire width 4 $4\reg$next[3:0]$11511 - attribute \src "libresoc.v:181696.3-181735.6" - wire width 4 $4\src14__data_o$next[3:0]$11517 - attribute \src "libresoc.v:181766.3-181805.6" - wire width 4 $4\src24__data_o$next[3:0]$11531 - attribute \src "libresoc.v:181836.3-181875.6" - wire width 4 $4\src34__data_o$next[3:0]$11545 - attribute \src "libresoc.v:181876.3-181905.6" - wire $4\wr_detect$10[0:0]$11553 - attribute \src "libresoc.v:181946.3-181975.6" - wire $4\wr_detect$13[0:0]$11567 - attribute \src "libresoc.v:181639.3-181668.6" - wire $4\wr_detect$16[0:0]$11505 - attribute \src "libresoc.v:181736.3-181765.6" - wire $4\wr_detect$4[0:0]$11525 - attribute \src "libresoc.v:181806.3-181835.6" - wire $4\wr_detect$7[0:0]$11539 - attribute \src "libresoc.v:181569.3-181598.6" + attribute \src "libresoc.v:182837.3-182876.6" + wire width 4 $4\cr_pred4__data_o$next[3:0]$11472 + attribute \src "libresoc.v:182907.3-182946.6" + wire width 4 $4\r24__data_o$next[3:0]$11481 + attribute \src "libresoc.v:183214.3-183253.6" + wire width 4 $4\r4__data_o$next[3:0]$11543 + attribute \src "libresoc.v:182977.3-183003.6" + wire width 4 $4\reg$next[3:0]$11495 + attribute \src "libresoc.v:183004.3-183043.6" + wire width 4 $4\src14__data_o$next[3:0]$11501 + attribute \src "libresoc.v:183074.3-183113.6" + wire width 4 $4\src24__data_o$next[3:0]$11515 + attribute \src "libresoc.v:183144.3-183183.6" + wire width 4 $4\src34__data_o$next[3:0]$11529 + attribute \src "libresoc.v:183184.3-183213.6" + wire $4\wr_detect$10[0:0]$11537 + attribute \src "libresoc.v:183254.3-183283.6" + wire $4\wr_detect$13[0:0]$11551 + attribute \src "libresoc.v:182947.3-182976.6" + wire $4\wr_detect$16[0:0]$11489 + attribute \src "libresoc.v:183044.3-183073.6" + wire $4\wr_detect$4[0:0]$11509 + attribute \src "libresoc.v:183114.3-183143.6" + wire $4\wr_detect$7[0:0]$11523 + attribute \src "libresoc.v:182877.3-182906.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:181529.3-181568.6" - wire width 4 $5\cr_pred4__data_o$next[3:0]$11489 - attribute \src "libresoc.v:181599.3-181638.6" - wire width 4 $5\r24__data_o$next[3:0]$11498 - attribute \src "libresoc.v:181906.3-181945.6" - wire width 4 $5\r4__data_o$next[3:0]$11560 - attribute \src "libresoc.v:181696.3-181735.6" - wire width 4 $5\src14__data_o$next[3:0]$11518 - attribute \src "libresoc.v:181766.3-181805.6" - wire width 4 $5\src24__data_o$next[3:0]$11532 - attribute \src "libresoc.v:181836.3-181875.6" - wire width 4 $5\src34__data_o$next[3:0]$11546 - attribute \src "libresoc.v:181529.3-181568.6" - wire width 4 $6\cr_pred4__data_o$next[3:0]$11490 - attribute \src "libresoc.v:181599.3-181638.6" - wire width 4 $6\r24__data_o$next[3:0]$11499 - attribute \src "libresoc.v:181906.3-181945.6" - wire width 4 $6\r4__data_o$next[3:0]$11561 - attribute \src "libresoc.v:181696.3-181735.6" - wire width 4 $6\src14__data_o$next[3:0]$11519 - attribute \src "libresoc.v:181766.3-181805.6" - wire width 4 $6\src24__data_o$next[3:0]$11533 - attribute \src "libresoc.v:181836.3-181875.6" - wire width 4 $6\src34__data_o$next[3:0]$11547 - attribute \src "libresoc.v:181509.17-181509.104" - wire $not$libresoc.v:181509$11470_Y - attribute \src "libresoc.v:181510.18-181510.105" - wire $not$libresoc.v:181510$11471_Y - attribute \src "libresoc.v:181511.18-181511.105" - wire $not$libresoc.v:181511$11472_Y - attribute \src "libresoc.v:181512.17-181512.100" - wire $not$libresoc.v:181512$11473_Y - attribute \src "libresoc.v:181513.17-181513.103" - wire $not$libresoc.v:181513$11474_Y - attribute \src "libresoc.v:181514.17-181514.103" - wire $not$libresoc.v:181514$11475_Y + attribute \src "libresoc.v:182837.3-182876.6" + wire width 4 $5\cr_pred4__data_o$next[3:0]$11473 + attribute \src "libresoc.v:182907.3-182946.6" + wire width 4 $5\r24__data_o$next[3:0]$11482 + attribute \src "libresoc.v:183214.3-183253.6" + wire width 4 $5\r4__data_o$next[3:0]$11544 + attribute \src "libresoc.v:183004.3-183043.6" + wire width 4 $5\src14__data_o$next[3:0]$11502 + attribute \src "libresoc.v:183074.3-183113.6" + wire width 4 $5\src24__data_o$next[3:0]$11516 + attribute \src "libresoc.v:183144.3-183183.6" + wire width 4 $5\src34__data_o$next[3:0]$11530 + attribute \src "libresoc.v:182837.3-182876.6" + wire width 4 $6\cr_pred4__data_o$next[3:0]$11474 + attribute \src "libresoc.v:182907.3-182946.6" + wire width 4 $6\r24__data_o$next[3:0]$11483 + attribute \src "libresoc.v:183214.3-183253.6" + wire width 4 $6\r4__data_o$next[3:0]$11545 + attribute \src "libresoc.v:183004.3-183043.6" + wire width 4 $6\src14__data_o$next[3:0]$11503 + attribute \src "libresoc.v:183074.3-183113.6" + wire width 4 $6\src24__data_o$next[3:0]$11517 + attribute \src "libresoc.v:183144.3-183183.6" + wire width 4 $6\src34__data_o$next[3:0]$11531 + attribute \src "libresoc.v:182817.17-182817.104" + wire $not$libresoc.v:182817$11454_Y + attribute \src "libresoc.v:182818.18-182818.105" + wire $not$libresoc.v:182818$11455_Y + attribute \src "libresoc.v:182819.18-182819.105" + wire $not$libresoc.v:182819$11456_Y + attribute \src "libresoc.v:182820.17-182820.100" + wire $not$libresoc.v:182820$11457_Y + attribute \src "libresoc.v:182821.17-182821.103" + wire $not$libresoc.v:182821$11458_Y + attribute \src "libresoc.v:182822.17-182822.103" + wire $not$libresoc.v:182822$11459_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -370178,9 +341548,9 @@ module \reg_4 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 20 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 3 \cr_pred4__data_o @@ -370196,7 +341566,7 @@ module \reg_4 wire width 4 input 13 \dest24__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest24__wen - attribute \src "libresoc.v:181422.7-181422.15" + attribute \src "libresoc.v:182730.7-182730.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 16 \r24__data_o @@ -370249,175 +341619,175 @@ module \reg_4 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:181509$11470 + cell $not $not$libresoc.v:182817$11454 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:181509$11470_Y + connect \Y $not$libresoc.v:182817$11454_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:181510$11471 + cell $not $not$libresoc.v:182818$11455 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:181510$11471_Y + connect \Y $not$libresoc.v:182818$11455_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:181511$11472 + cell $not $not$libresoc.v:182819$11456 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$16 - connect \Y $not$libresoc.v:181511$11472_Y + connect \Y $not$libresoc.v:182819$11456_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:181512$11473 + cell $not $not$libresoc.v:182820$11457 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:181512$11473_Y + connect \Y $not$libresoc.v:182820$11457_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:181513$11474 + cell $not $not$libresoc.v:182821$11458 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:181513$11474_Y + connect \Y $not$libresoc.v:182821$11458_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:181514$11475 + cell $not $not$libresoc.v:182822$11459 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:181514$11475_Y + connect \Y $not$libresoc.v:182822$11459_Y end - attribute \src "libresoc.v:181422.7-181422.20" - process $proc$libresoc.v:181422$11568 + attribute \src "libresoc.v:182730.7-182730.20" + process $proc$libresoc.v:182730$11552 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:181441.13-181441.36" - process $proc$libresoc.v:181441$11569 + attribute \src "libresoc.v:182749.13-182749.36" + process $proc$libresoc.v:182749$11553 assign { } { } assign $1\cr_pred4__data_o[3:0] 4'0000 sync always sync init update \cr_pred4__data_o $1\cr_pred4__data_o[3:0] end - attribute \src "libresoc.v:181456.13-181456.31" - process $proc$libresoc.v:181456$11570 + attribute \src "libresoc.v:182764.13-182764.31" + process $proc$libresoc.v:182764$11554 assign { } { } assign $1\r24__data_o[3:0] 4'0000 sync always sync init update \r24__data_o $1\r24__data_o[3:0] end - attribute \src "libresoc.v:181463.13-181463.30" - process $proc$libresoc.v:181463$11571 + attribute \src "libresoc.v:182771.13-182771.30" + process $proc$libresoc.v:182771$11555 assign { } { } assign $1\r4__data_o[3:0] 4'0000 sync always sync init update \r4__data_o $1\r4__data_o[3:0] end - attribute \src "libresoc.v:181469.13-181469.25" - process $proc$libresoc.v:181469$11572 + attribute \src "libresoc.v:182777.13-182777.25" + process $proc$libresoc.v:182777$11556 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:181474.13-181474.33" - process $proc$libresoc.v:181474$11573 + attribute \src "libresoc.v:182782.13-182782.33" + process $proc$libresoc.v:182782$11557 assign { } { } assign $1\src14__data_o[3:0] 4'0000 sync always sync init update \src14__data_o $1\src14__data_o[3:0] end - attribute \src "libresoc.v:181481.13-181481.33" - process $proc$libresoc.v:181481$11574 + attribute \src "libresoc.v:182789.13-182789.33" + process $proc$libresoc.v:182789$11558 assign { } { } assign $1\src24__data_o[3:0] 4'0000 sync always sync init update \src24__data_o $1\src24__data_o[3:0] end - attribute \src "libresoc.v:181488.13-181488.33" - process $proc$libresoc.v:181488$11575 + attribute \src "libresoc.v:182796.13-182796.33" + process $proc$libresoc.v:182796$11559 assign { } { } assign $1\src34__data_o[3:0] 4'0000 sync always sync init update \src34__data_o $1\src34__data_o[3:0] end - attribute \src "libresoc.v:181515.3-181516.25" - process $proc$libresoc.v:181515$11476 + attribute \src "libresoc.v:182823.3-182824.25" + process $proc$libresoc.v:182823$11460 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:181517.3-181518.39" - process $proc$libresoc.v:181517$11477 + attribute \src "libresoc.v:182825.3-182826.39" + process $proc$libresoc.v:182825$11461 assign { } { } assign $0\r24__data_o[3:0] \r24__data_o$next sync posedge \coresync_clk update \r24__data_o $0\r24__data_o[3:0] end - attribute \src "libresoc.v:181519.3-181520.37" - process $proc$libresoc.v:181519$11478 + attribute \src "libresoc.v:182827.3-182828.37" + process $proc$libresoc.v:182827$11462 assign { } { } assign $0\r4__data_o[3:0] \r4__data_o$next sync posedge \coresync_clk update \r4__data_o $0\r4__data_o[3:0] end - attribute \src "libresoc.v:181521.3-181522.43" - process $proc$libresoc.v:181521$11479 + attribute \src "libresoc.v:182829.3-182830.43" + process $proc$libresoc.v:182829$11463 assign { } { } assign $0\src34__data_o[3:0] \src34__data_o$next sync posedge \coresync_clk update \src34__data_o $0\src34__data_o[3:0] end - attribute \src "libresoc.v:181523.3-181524.43" - process $proc$libresoc.v:181523$11480 + attribute \src "libresoc.v:182831.3-182832.43" + process $proc$libresoc.v:182831$11464 assign { } { } assign $0\src24__data_o[3:0] \src24__data_o$next sync posedge \coresync_clk update \src24__data_o $0\src24__data_o[3:0] end - attribute \src "libresoc.v:181525.3-181526.43" - process $proc$libresoc.v:181525$11481 + attribute \src "libresoc.v:182833.3-182834.43" + process $proc$libresoc.v:182833$11465 assign { } { } assign $0\src14__data_o[3:0] \src14__data_o$next sync posedge \coresync_clk update \src14__data_o $0\src14__data_o[3:0] end - attribute \src "libresoc.v:181527.3-181528.49" - process $proc$libresoc.v:181527$11482 + attribute \src "libresoc.v:182835.3-182836.49" + process $proc$libresoc.v:182835$11466 assign { } { } assign $0\cr_pred4__data_o[3:0] \cr_pred4__data_o$next sync posedge \coresync_clk update \cr_pred4__data_o $0\cr_pred4__data_o[3:0] end - attribute \src "libresoc.v:181529.3-181568.6" - process $proc$libresoc.v:181529$11483 + attribute \src "libresoc.v:182837.3-182876.6" + process $proc$libresoc.v:182837$11467 assign { } { } assign { } { } assign { } { } - assign $0\cr_pred4__data_o$next[3:0]$11484 $6\cr_pred4__data_o$next[3:0]$11490 - attribute \src "libresoc.v:181530.5-181530.29" + assign $0\cr_pred4__data_o$next[3:0]$11468 $6\cr_pred4__data_o$next[3:0]$11474 + attribute \src "libresoc.v:182838.5-182838.29" switch \initial - attribute \src "libresoc.v:181530.9-181530.17" + attribute \src "libresoc.v:182838.9-182838.17" case 1'1 case end @@ -370429,66 +341799,66 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\cr_pred4__data_o$next[3:0]$11485 $5\cr_pred4__data_o$next[3:0]$11489 + assign $1\cr_pred4__data_o$next[3:0]$11469 $5\cr_pred4__data_o$next[3:0]$11473 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_pred4__data_o$next[3:0]$11486 \dest14__data_i + assign $2\cr_pred4__data_o$next[3:0]$11470 \dest14__data_i case - assign $2\cr_pred4__data_o$next[3:0]$11486 4'0000 + assign $2\cr_pred4__data_o$next[3:0]$11470 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\cr_pred4__data_o$next[3:0]$11487 \dest24__data_i + assign $3\cr_pred4__data_o$next[3:0]$11471 \dest24__data_i case - assign $3\cr_pred4__data_o$next[3:0]$11487 $2\cr_pred4__data_o$next[3:0]$11486 + assign $3\cr_pred4__data_o$next[3:0]$11471 $2\cr_pred4__data_o$next[3:0]$11470 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cr_pred4__data_o$next[3:0]$11488 \w4__data_i + assign $4\cr_pred4__data_o$next[3:0]$11472 \w4__data_i case - assign $4\cr_pred4__data_o$next[3:0]$11488 $3\cr_pred4__data_o$next[3:0]$11487 + assign $4\cr_pred4__data_o$next[3:0]$11472 $3\cr_pred4__data_o$next[3:0]$11471 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\cr_pred4__data_o$next[3:0]$11489 \reg + assign $5\cr_pred4__data_o$next[3:0]$11473 \reg case - assign $5\cr_pred4__data_o$next[3:0]$11489 $4\cr_pred4__data_o$next[3:0]$11488 + assign $5\cr_pred4__data_o$next[3:0]$11473 $4\cr_pred4__data_o$next[3:0]$11472 end case - assign $1\cr_pred4__data_o$next[3:0]$11485 4'0000 + assign $1\cr_pred4__data_o$next[3:0]$11469 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cr_pred4__data_o$next[3:0]$11490 4'0000 + assign $6\cr_pred4__data_o$next[3:0]$11474 4'0000 case - assign $6\cr_pred4__data_o$next[3:0]$11490 $1\cr_pred4__data_o$next[3:0]$11485 + assign $6\cr_pred4__data_o$next[3:0]$11474 $1\cr_pred4__data_o$next[3:0]$11469 end sync always - update \cr_pred4__data_o$next $0\cr_pred4__data_o$next[3:0]$11484 + update \cr_pred4__data_o$next $0\cr_pred4__data_o$next[3:0]$11468 end - attribute \src "libresoc.v:181569.3-181598.6" - process $proc$libresoc.v:181569$11491 + attribute \src "libresoc.v:182877.3-182906.6" + process $proc$libresoc.v:182877$11475 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:181570.5-181570.29" + attribute \src "libresoc.v:182878.5-182878.29" switch \initial - attribute \src "libresoc.v:181570.9-181570.17" + attribute \src "libresoc.v:182878.9-182878.17" case 1'1 case end @@ -370534,15 +341904,15 @@ module \reg_4 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:181599.3-181638.6" - process $proc$libresoc.v:181599$11492 + attribute \src "libresoc.v:182907.3-182946.6" + process $proc$libresoc.v:182907$11476 assign { } { } assign { } { } assign { } { } - assign $0\r24__data_o$next[3:0]$11493 $6\r24__data_o$next[3:0]$11499 - attribute \src "libresoc.v:181600.5-181600.29" + assign $0\r24__data_o$next[3:0]$11477 $6\r24__data_o$next[3:0]$11483 + attribute \src "libresoc.v:182908.5-182908.29" switch \initial - attribute \src "libresoc.v:181600.9-181600.17" + attribute \src "libresoc.v:182908.9-182908.17" case 1'1 case end @@ -370554,66 +341924,66 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\r24__data_o$next[3:0]$11494 $5\r24__data_o$next[3:0]$11498 + assign $1\r24__data_o$next[3:0]$11478 $5\r24__data_o$next[3:0]$11482 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r24__data_o$next[3:0]$11495 \dest14__data_i + assign $2\r24__data_o$next[3:0]$11479 \dest14__data_i case - assign $2\r24__data_o$next[3:0]$11495 4'0000 + assign $2\r24__data_o$next[3:0]$11479 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r24__data_o$next[3:0]$11496 \dest24__data_i + assign $3\r24__data_o$next[3:0]$11480 \dest24__data_i case - assign $3\r24__data_o$next[3:0]$11496 $2\r24__data_o$next[3:0]$11495 + assign $3\r24__data_o$next[3:0]$11480 $2\r24__data_o$next[3:0]$11479 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r24__data_o$next[3:0]$11497 \w4__data_i + assign $4\r24__data_o$next[3:0]$11481 \w4__data_i case - assign $4\r24__data_o$next[3:0]$11497 $3\r24__data_o$next[3:0]$11496 + assign $4\r24__data_o$next[3:0]$11481 $3\r24__data_o$next[3:0]$11480 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$15 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r24__data_o$next[3:0]$11498 \reg + assign $5\r24__data_o$next[3:0]$11482 \reg case - assign $5\r24__data_o$next[3:0]$11498 $4\r24__data_o$next[3:0]$11497 + assign $5\r24__data_o$next[3:0]$11482 $4\r24__data_o$next[3:0]$11481 end case - assign $1\r24__data_o$next[3:0]$11494 4'0000 + assign $1\r24__data_o$next[3:0]$11478 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r24__data_o$next[3:0]$11499 4'0000 + assign $6\r24__data_o$next[3:0]$11483 4'0000 case - assign $6\r24__data_o$next[3:0]$11499 $1\r24__data_o$next[3:0]$11494 + assign $6\r24__data_o$next[3:0]$11483 $1\r24__data_o$next[3:0]$11478 end sync always - update \r24__data_o$next $0\r24__data_o$next[3:0]$11493 + update \r24__data_o$next $0\r24__data_o$next[3:0]$11477 end - attribute \src "libresoc.v:181639.3-181668.6" - process $proc$libresoc.v:181639$11500 + attribute \src "libresoc.v:182947.3-182976.6" + process $proc$libresoc.v:182947$11484 assign { } { } assign { } { } - assign $0\wr_detect$16[0:0]$11501 $1\wr_detect$16[0:0]$11502 - attribute \src "libresoc.v:181640.5-181640.29" + assign $0\wr_detect$16[0:0]$11485 $1\wr_detect$16[0:0]$11486 + attribute \src "libresoc.v:182948.5-182948.29" switch \initial - attribute \src "libresoc.v:181640.9-181640.17" + attribute \src "libresoc.v:182948.9-182948.17" case 1'1 case end @@ -370625,51 +341995,51 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$16[0:0]$11502 $4\wr_detect$16[0:0]$11505 + assign $1\wr_detect$16[0:0]$11486 $4\wr_detect$16[0:0]$11489 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$16[0:0]$11503 1'1 + assign $2\wr_detect$16[0:0]$11487 1'1 case - assign $2\wr_detect$16[0:0]$11503 1'0 + assign $2\wr_detect$16[0:0]$11487 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$16[0:0]$11504 1'1 + assign $3\wr_detect$16[0:0]$11488 1'1 case - assign $3\wr_detect$16[0:0]$11504 $2\wr_detect$16[0:0]$11503 + assign $3\wr_detect$16[0:0]$11488 $2\wr_detect$16[0:0]$11487 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$16[0:0]$11505 1'1 + assign $4\wr_detect$16[0:0]$11489 1'1 case - assign $4\wr_detect$16[0:0]$11505 $3\wr_detect$16[0:0]$11504 + assign $4\wr_detect$16[0:0]$11489 $3\wr_detect$16[0:0]$11488 end case - assign $1\wr_detect$16[0:0]$11502 1'0 + assign $1\wr_detect$16[0:0]$11486 1'0 end sync always - update \wr_detect$16 $0\wr_detect$16[0:0]$11501 + update \wr_detect$16 $0\wr_detect$16[0:0]$11485 end - attribute \src "libresoc.v:181669.3-181695.6" - process $proc$libresoc.v:181669$11506 + attribute \src "libresoc.v:182977.3-183003.6" + process $proc$libresoc.v:182977$11490 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11507 $4\reg$next[3:0]$11511 - attribute \src "libresoc.v:181670.5-181670.29" + assign $0\reg$next[3:0]$11491 $4\reg$next[3:0]$11495 + attribute \src "libresoc.v:182978.5-182978.29" switch \initial - attribute \src "libresoc.v:181670.9-181670.17" + attribute \src "libresoc.v:182978.9-182978.17" case 1'1 case end @@ -370678,49 +342048,49 @@ module \reg_4 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11508 \dest14__data_i + assign $1\reg$next[3:0]$11492 \dest14__data_i case - assign $1\reg$next[3:0]$11508 \reg + assign $1\reg$next[3:0]$11492 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11509 \dest24__data_i + assign $2\reg$next[3:0]$11493 \dest24__data_i case - assign $2\reg$next[3:0]$11509 $1\reg$next[3:0]$11508 + assign $2\reg$next[3:0]$11493 $1\reg$next[3:0]$11492 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11510 \w4__data_i + assign $3\reg$next[3:0]$11494 \w4__data_i case - assign $3\reg$next[3:0]$11510 $2\reg$next[3:0]$11509 + assign $3\reg$next[3:0]$11494 $2\reg$next[3:0]$11493 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11511 4'0000 + assign $4\reg$next[3:0]$11495 4'0000 case - assign $4\reg$next[3:0]$11511 $3\reg$next[3:0]$11510 + assign $4\reg$next[3:0]$11495 $3\reg$next[3:0]$11494 end sync always - update \reg$next $0\reg$next[3:0]$11507 + update \reg$next $0\reg$next[3:0]$11491 end - attribute \src "libresoc.v:181696.3-181735.6" - process $proc$libresoc.v:181696$11512 + attribute \src "libresoc.v:183004.3-183043.6" + process $proc$libresoc.v:183004$11496 assign { } { } assign { } { } assign { } { } - assign $0\src14__data_o$next[3:0]$11513 $6\src14__data_o$next[3:0]$11519 - attribute \src "libresoc.v:181697.5-181697.29" + assign $0\src14__data_o$next[3:0]$11497 $6\src14__data_o$next[3:0]$11503 + attribute \src "libresoc.v:183005.5-183005.29" switch \initial - attribute \src "libresoc.v:181697.9-181697.17" + attribute \src "libresoc.v:183005.9-183005.17" case 1'1 case end @@ -370732,66 +342102,66 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\src14__data_o$next[3:0]$11514 $5\src14__data_o$next[3:0]$11518 + assign $1\src14__data_o$next[3:0]$11498 $5\src14__data_o$next[3:0]$11502 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src14__data_o$next[3:0]$11515 \dest14__data_i + assign $2\src14__data_o$next[3:0]$11499 \dest14__data_i case - assign $2\src14__data_o$next[3:0]$11515 4'0000 + assign $2\src14__data_o$next[3:0]$11499 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src14__data_o$next[3:0]$11516 \dest24__data_i + assign $3\src14__data_o$next[3:0]$11500 \dest24__data_i case - assign $3\src14__data_o$next[3:0]$11516 $2\src14__data_o$next[3:0]$11515 + assign $3\src14__data_o$next[3:0]$11500 $2\src14__data_o$next[3:0]$11499 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src14__data_o$next[3:0]$11517 \w4__data_i + assign $4\src14__data_o$next[3:0]$11501 \w4__data_i case - assign $4\src14__data_o$next[3:0]$11517 $3\src14__data_o$next[3:0]$11516 + assign $4\src14__data_o$next[3:0]$11501 $3\src14__data_o$next[3:0]$11500 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src14__data_o$next[3:0]$11518 \reg + assign $5\src14__data_o$next[3:0]$11502 \reg case - assign $5\src14__data_o$next[3:0]$11518 $4\src14__data_o$next[3:0]$11517 + assign $5\src14__data_o$next[3:0]$11502 $4\src14__data_o$next[3:0]$11501 end case - assign $1\src14__data_o$next[3:0]$11514 4'0000 + assign $1\src14__data_o$next[3:0]$11498 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src14__data_o$next[3:0]$11519 4'0000 + assign $6\src14__data_o$next[3:0]$11503 4'0000 case - assign $6\src14__data_o$next[3:0]$11519 $1\src14__data_o$next[3:0]$11514 + assign $6\src14__data_o$next[3:0]$11503 $1\src14__data_o$next[3:0]$11498 end sync always - update \src14__data_o$next $0\src14__data_o$next[3:0]$11513 + update \src14__data_o$next $0\src14__data_o$next[3:0]$11497 end - attribute \src "libresoc.v:181736.3-181765.6" - process $proc$libresoc.v:181736$11520 + attribute \src "libresoc.v:183044.3-183073.6" + process $proc$libresoc.v:183044$11504 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11521 $1\wr_detect$4[0:0]$11522 - attribute \src "libresoc.v:181737.5-181737.29" + assign $0\wr_detect$4[0:0]$11505 $1\wr_detect$4[0:0]$11506 + attribute \src "libresoc.v:183045.5-183045.29" switch \initial - attribute \src "libresoc.v:181737.9-181737.17" + attribute \src "libresoc.v:183045.9-183045.17" case 1'1 case end @@ -370803,49 +342173,49 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11522 $4\wr_detect$4[0:0]$11525 + assign $1\wr_detect$4[0:0]$11506 $4\wr_detect$4[0:0]$11509 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11523 1'1 + assign $2\wr_detect$4[0:0]$11507 1'1 case - assign $2\wr_detect$4[0:0]$11523 1'0 + assign $2\wr_detect$4[0:0]$11507 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11524 1'1 + assign $3\wr_detect$4[0:0]$11508 1'1 case - assign $3\wr_detect$4[0:0]$11524 $2\wr_detect$4[0:0]$11523 + assign $3\wr_detect$4[0:0]$11508 $2\wr_detect$4[0:0]$11507 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11525 1'1 + assign $4\wr_detect$4[0:0]$11509 1'1 case - assign $4\wr_detect$4[0:0]$11525 $3\wr_detect$4[0:0]$11524 + assign $4\wr_detect$4[0:0]$11509 $3\wr_detect$4[0:0]$11508 end case - assign $1\wr_detect$4[0:0]$11522 1'0 + assign $1\wr_detect$4[0:0]$11506 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11521 + update \wr_detect$4 $0\wr_detect$4[0:0]$11505 end - attribute \src "libresoc.v:181766.3-181805.6" - process $proc$libresoc.v:181766$11526 + attribute \src "libresoc.v:183074.3-183113.6" + process $proc$libresoc.v:183074$11510 assign { } { } assign { } { } assign { } { } - assign $0\src24__data_o$next[3:0]$11527 $6\src24__data_o$next[3:0]$11533 - attribute \src "libresoc.v:181767.5-181767.29" + assign $0\src24__data_o$next[3:0]$11511 $6\src24__data_o$next[3:0]$11517 + attribute \src "libresoc.v:183075.5-183075.29" switch \initial - attribute \src "libresoc.v:181767.9-181767.17" + attribute \src "libresoc.v:183075.9-183075.17" case 1'1 case end @@ -370857,66 +342227,66 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\src24__data_o$next[3:0]$11528 $5\src24__data_o$next[3:0]$11532 + assign $1\src24__data_o$next[3:0]$11512 $5\src24__data_o$next[3:0]$11516 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src24__data_o$next[3:0]$11529 \dest14__data_i + assign $2\src24__data_o$next[3:0]$11513 \dest14__data_i case - assign $2\src24__data_o$next[3:0]$11529 4'0000 + assign $2\src24__data_o$next[3:0]$11513 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src24__data_o$next[3:0]$11530 \dest24__data_i + assign $3\src24__data_o$next[3:0]$11514 \dest24__data_i case - assign $3\src24__data_o$next[3:0]$11530 $2\src24__data_o$next[3:0]$11529 + assign $3\src24__data_o$next[3:0]$11514 $2\src24__data_o$next[3:0]$11513 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src24__data_o$next[3:0]$11531 \w4__data_i + assign $4\src24__data_o$next[3:0]$11515 \w4__data_i case - assign $4\src24__data_o$next[3:0]$11531 $3\src24__data_o$next[3:0]$11530 + assign $4\src24__data_o$next[3:0]$11515 $3\src24__data_o$next[3:0]$11514 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src24__data_o$next[3:0]$11532 \reg + assign $5\src24__data_o$next[3:0]$11516 \reg case - assign $5\src24__data_o$next[3:0]$11532 $4\src24__data_o$next[3:0]$11531 + assign $5\src24__data_o$next[3:0]$11516 $4\src24__data_o$next[3:0]$11515 end case - assign $1\src24__data_o$next[3:0]$11528 4'0000 + assign $1\src24__data_o$next[3:0]$11512 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src24__data_o$next[3:0]$11533 4'0000 + assign $6\src24__data_o$next[3:0]$11517 4'0000 case - assign $6\src24__data_o$next[3:0]$11533 $1\src24__data_o$next[3:0]$11528 + assign $6\src24__data_o$next[3:0]$11517 $1\src24__data_o$next[3:0]$11512 end sync always - update \src24__data_o$next $0\src24__data_o$next[3:0]$11527 + update \src24__data_o$next $0\src24__data_o$next[3:0]$11511 end - attribute \src "libresoc.v:181806.3-181835.6" - process $proc$libresoc.v:181806$11534 + attribute \src "libresoc.v:183114.3-183143.6" + process $proc$libresoc.v:183114$11518 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11535 $1\wr_detect$7[0:0]$11536 - attribute \src "libresoc.v:181807.5-181807.29" + assign $0\wr_detect$7[0:0]$11519 $1\wr_detect$7[0:0]$11520 + attribute \src "libresoc.v:183115.5-183115.29" switch \initial - attribute \src "libresoc.v:181807.9-181807.17" + attribute \src "libresoc.v:183115.9-183115.17" case 1'1 case end @@ -370928,49 +342298,49 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11536 $4\wr_detect$7[0:0]$11539 + assign $1\wr_detect$7[0:0]$11520 $4\wr_detect$7[0:0]$11523 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11537 1'1 + assign $2\wr_detect$7[0:0]$11521 1'1 case - assign $2\wr_detect$7[0:0]$11537 1'0 + assign $2\wr_detect$7[0:0]$11521 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11538 1'1 + assign $3\wr_detect$7[0:0]$11522 1'1 case - assign $3\wr_detect$7[0:0]$11538 $2\wr_detect$7[0:0]$11537 + assign $3\wr_detect$7[0:0]$11522 $2\wr_detect$7[0:0]$11521 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11539 1'1 + assign $4\wr_detect$7[0:0]$11523 1'1 case - assign $4\wr_detect$7[0:0]$11539 $3\wr_detect$7[0:0]$11538 + assign $4\wr_detect$7[0:0]$11523 $3\wr_detect$7[0:0]$11522 end case - assign $1\wr_detect$7[0:0]$11536 1'0 + assign $1\wr_detect$7[0:0]$11520 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11535 + update \wr_detect$7 $0\wr_detect$7[0:0]$11519 end - attribute \src "libresoc.v:181836.3-181875.6" - process $proc$libresoc.v:181836$11540 + attribute \src "libresoc.v:183144.3-183183.6" + process $proc$libresoc.v:183144$11524 assign { } { } assign { } { } assign { } { } - assign $0\src34__data_o$next[3:0]$11541 $6\src34__data_o$next[3:0]$11547 - attribute \src "libresoc.v:181837.5-181837.29" + assign $0\src34__data_o$next[3:0]$11525 $6\src34__data_o$next[3:0]$11531 + attribute \src "libresoc.v:183145.5-183145.29" switch \initial - attribute \src "libresoc.v:181837.9-181837.17" + attribute \src "libresoc.v:183145.9-183145.17" case 1'1 case end @@ -370982,66 +342352,66 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\src34__data_o$next[3:0]$11542 $5\src34__data_o$next[3:0]$11546 + assign $1\src34__data_o$next[3:0]$11526 $5\src34__data_o$next[3:0]$11530 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src34__data_o$next[3:0]$11543 \dest14__data_i + assign $2\src34__data_o$next[3:0]$11527 \dest14__data_i case - assign $2\src34__data_o$next[3:0]$11543 4'0000 + assign $2\src34__data_o$next[3:0]$11527 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src34__data_o$next[3:0]$11544 \dest24__data_i + assign $3\src34__data_o$next[3:0]$11528 \dest24__data_i case - assign $3\src34__data_o$next[3:0]$11544 $2\src34__data_o$next[3:0]$11543 + assign $3\src34__data_o$next[3:0]$11528 $2\src34__data_o$next[3:0]$11527 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src34__data_o$next[3:0]$11545 \w4__data_i + assign $4\src34__data_o$next[3:0]$11529 \w4__data_i case - assign $4\src34__data_o$next[3:0]$11545 $3\src34__data_o$next[3:0]$11544 + assign $4\src34__data_o$next[3:0]$11529 $3\src34__data_o$next[3:0]$11528 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src34__data_o$next[3:0]$11546 \reg + assign $5\src34__data_o$next[3:0]$11530 \reg case - assign $5\src34__data_o$next[3:0]$11546 $4\src34__data_o$next[3:0]$11545 + assign $5\src34__data_o$next[3:0]$11530 $4\src34__data_o$next[3:0]$11529 end case - assign $1\src34__data_o$next[3:0]$11542 4'0000 + assign $1\src34__data_o$next[3:0]$11526 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src34__data_o$next[3:0]$11547 4'0000 + assign $6\src34__data_o$next[3:0]$11531 4'0000 case - assign $6\src34__data_o$next[3:0]$11547 $1\src34__data_o$next[3:0]$11542 + assign $6\src34__data_o$next[3:0]$11531 $1\src34__data_o$next[3:0]$11526 end sync always - update \src34__data_o$next $0\src34__data_o$next[3:0]$11541 + update \src34__data_o$next $0\src34__data_o$next[3:0]$11525 end - attribute \src "libresoc.v:181876.3-181905.6" - process $proc$libresoc.v:181876$11548 + attribute \src "libresoc.v:183184.3-183213.6" + process $proc$libresoc.v:183184$11532 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11549 $1\wr_detect$10[0:0]$11550 - attribute \src "libresoc.v:181877.5-181877.29" + assign $0\wr_detect$10[0:0]$11533 $1\wr_detect$10[0:0]$11534 + attribute \src "libresoc.v:183185.5-183185.29" switch \initial - attribute \src "libresoc.v:181877.9-181877.17" + attribute \src "libresoc.v:183185.9-183185.17" case 1'1 case end @@ -371053,49 +342423,49 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11550 $4\wr_detect$10[0:0]$11553 + assign $1\wr_detect$10[0:0]$11534 $4\wr_detect$10[0:0]$11537 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11551 1'1 + assign $2\wr_detect$10[0:0]$11535 1'1 case - assign $2\wr_detect$10[0:0]$11551 1'0 + assign $2\wr_detect$10[0:0]$11535 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11552 1'1 + assign $3\wr_detect$10[0:0]$11536 1'1 case - assign $3\wr_detect$10[0:0]$11552 $2\wr_detect$10[0:0]$11551 + assign $3\wr_detect$10[0:0]$11536 $2\wr_detect$10[0:0]$11535 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11553 1'1 + assign $4\wr_detect$10[0:0]$11537 1'1 case - assign $4\wr_detect$10[0:0]$11553 $3\wr_detect$10[0:0]$11552 + assign $4\wr_detect$10[0:0]$11537 $3\wr_detect$10[0:0]$11536 end case - assign $1\wr_detect$10[0:0]$11550 1'0 + assign $1\wr_detect$10[0:0]$11534 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11549 + update \wr_detect$10 $0\wr_detect$10[0:0]$11533 end - attribute \src "libresoc.v:181906.3-181945.6" - process $proc$libresoc.v:181906$11554 + attribute \src "libresoc.v:183214.3-183253.6" + process $proc$libresoc.v:183214$11538 assign { } { } assign { } { } assign { } { } - assign $0\r4__data_o$next[3:0]$11555 $6\r4__data_o$next[3:0]$11561 - attribute \src "libresoc.v:181907.5-181907.29" + assign $0\r4__data_o$next[3:0]$11539 $6\r4__data_o$next[3:0]$11545 + attribute \src "libresoc.v:183215.5-183215.29" switch \initial - attribute \src "libresoc.v:181907.9-181907.17" + attribute \src "libresoc.v:183215.9-183215.17" case 1'1 case end @@ -371107,66 +342477,66 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\r4__data_o$next[3:0]$11556 $5\r4__data_o$next[3:0]$11560 + assign $1\r4__data_o$next[3:0]$11540 $5\r4__data_o$next[3:0]$11544 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r4__data_o$next[3:0]$11557 \dest14__data_i + assign $2\r4__data_o$next[3:0]$11541 \dest14__data_i case - assign $2\r4__data_o$next[3:0]$11557 4'0000 + assign $2\r4__data_o$next[3:0]$11541 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r4__data_o$next[3:0]$11558 \dest24__data_i + assign $3\r4__data_o$next[3:0]$11542 \dest24__data_i case - assign $3\r4__data_o$next[3:0]$11558 $2\r4__data_o$next[3:0]$11557 + assign $3\r4__data_o$next[3:0]$11542 $2\r4__data_o$next[3:0]$11541 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r4__data_o$next[3:0]$11559 \w4__data_i + assign $4\r4__data_o$next[3:0]$11543 \w4__data_i case - assign $4\r4__data_o$next[3:0]$11559 $3\r4__data_o$next[3:0]$11558 + assign $4\r4__data_o$next[3:0]$11543 $3\r4__data_o$next[3:0]$11542 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r4__data_o$next[3:0]$11560 \reg + assign $5\r4__data_o$next[3:0]$11544 \reg case - assign $5\r4__data_o$next[3:0]$11560 $4\r4__data_o$next[3:0]$11559 + assign $5\r4__data_o$next[3:0]$11544 $4\r4__data_o$next[3:0]$11543 end case - assign $1\r4__data_o$next[3:0]$11556 4'0000 + assign $1\r4__data_o$next[3:0]$11540 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r4__data_o$next[3:0]$11561 4'0000 + assign $6\r4__data_o$next[3:0]$11545 4'0000 case - assign $6\r4__data_o$next[3:0]$11561 $1\r4__data_o$next[3:0]$11556 + assign $6\r4__data_o$next[3:0]$11545 $1\r4__data_o$next[3:0]$11540 end sync always - update \r4__data_o$next $0\r4__data_o$next[3:0]$11555 + update \r4__data_o$next $0\r4__data_o$next[3:0]$11539 end - attribute \src "libresoc.v:181946.3-181975.6" - process $proc$libresoc.v:181946$11562 + attribute \src "libresoc.v:183254.3-183283.6" + process $proc$libresoc.v:183254$11546 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11563 $1\wr_detect$13[0:0]$11564 - attribute \src "libresoc.v:181947.5-181947.29" + assign $0\wr_detect$13[0:0]$11547 $1\wr_detect$13[0:0]$11548 + attribute \src "libresoc.v:183255.5-183255.29" switch \initial - attribute \src "libresoc.v:181947.9-181947.17" + attribute \src "libresoc.v:183255.9-183255.17" case 1'1 case end @@ -371178,248 +342548,248 @@ module \reg_4 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11564 $4\wr_detect$13[0:0]$11567 + assign $1\wr_detect$13[0:0]$11548 $4\wr_detect$13[0:0]$11551 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest14__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11565 1'1 + assign $2\wr_detect$13[0:0]$11549 1'1 case - assign $2\wr_detect$13[0:0]$11565 1'0 + assign $2\wr_detect$13[0:0]$11549 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest24__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11566 1'1 + assign $3\wr_detect$13[0:0]$11550 1'1 case - assign $3\wr_detect$13[0:0]$11566 $2\wr_detect$13[0:0]$11565 + assign $3\wr_detect$13[0:0]$11550 $2\wr_detect$13[0:0]$11549 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w4__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11567 1'1 + assign $4\wr_detect$13[0:0]$11551 1'1 case - assign $4\wr_detect$13[0:0]$11567 $3\wr_detect$13[0:0]$11566 + assign $4\wr_detect$13[0:0]$11551 $3\wr_detect$13[0:0]$11550 end case - assign $1\wr_detect$13[0:0]$11564 1'0 + assign $1\wr_detect$13[0:0]$11548 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11563 + update \wr_detect$13 $0\wr_detect$13[0:0]$11547 end - connect \$9 $not$libresoc.v:181509$11470_Y - connect \$12 $not$libresoc.v:181510$11471_Y - connect \$15 $not$libresoc.v:181511$11472_Y - connect \$1 $not$libresoc.v:181512$11473_Y - connect \$3 $not$libresoc.v:181513$11474_Y - connect \$6 $not$libresoc.v:181514$11475_Y + connect \$9 $not$libresoc.v:182817$11454_Y + connect \$12 $not$libresoc.v:182818$11455_Y + connect \$15 $not$libresoc.v:182819$11456_Y + connect \$1 $not$libresoc.v:182820$11457_Y + connect \$3 $not$libresoc.v:182821$11458_Y + connect \$6 $not$libresoc.v:182822$11459_Y end -attribute \src "libresoc.v:181980.1-182535.10" +attribute \src "libresoc.v:183288.1-183843.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_5" attribute \generator "nMigen" module \reg_5 - attribute \src "libresoc.v:182088.3-182127.6" - wire width 4 $0\cr_pred5__data_o$next[3:0]$11590 - attribute \src "libresoc.v:182086.3-182087.49" + attribute \src "libresoc.v:183396.3-183435.6" + wire width 4 $0\cr_pred5__data_o$next[3:0]$11574 + attribute \src "libresoc.v:183394.3-183395.49" wire width 4 $0\cr_pred5__data_o[3:0] - attribute \src "libresoc.v:181981.7-181981.20" + attribute \src "libresoc.v:183289.7-183289.20" wire $0\initial[0:0] - attribute \src "libresoc.v:182158.3-182197.6" - wire width 4 $0\r25__data_o$next[3:0]$11599 - attribute \src "libresoc.v:182076.3-182077.39" + attribute \src "libresoc.v:183466.3-183505.6" + wire width 4 $0\r25__data_o$next[3:0]$11583 + attribute \src "libresoc.v:183384.3-183385.39" wire width 4 $0\r25__data_o[3:0] - attribute \src "libresoc.v:182465.3-182504.6" - wire width 4 $0\r5__data_o$next[3:0]$11661 - attribute \src "libresoc.v:182078.3-182079.37" + attribute \src "libresoc.v:183773.3-183812.6" + wire width 4 $0\r5__data_o$next[3:0]$11645 + attribute \src "libresoc.v:183386.3-183387.37" wire width 4 $0\r5__data_o[3:0] - attribute \src "libresoc.v:182228.3-182254.6" - wire width 4 $0\reg$next[3:0]$11613 - attribute \src "libresoc.v:182074.3-182075.25" + attribute \src "libresoc.v:183536.3-183562.6" + wire width 4 $0\reg$next[3:0]$11597 + attribute \src "libresoc.v:183382.3-183383.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:182255.3-182294.6" - wire width 4 $0\src15__data_o$next[3:0]$11619 - attribute \src "libresoc.v:182084.3-182085.43" + attribute \src "libresoc.v:183563.3-183602.6" + wire width 4 $0\src15__data_o$next[3:0]$11603 + attribute \src "libresoc.v:183392.3-183393.43" wire width 4 $0\src15__data_o[3:0] - attribute \src "libresoc.v:182325.3-182364.6" - wire width 4 $0\src25__data_o$next[3:0]$11633 - attribute \src "libresoc.v:182082.3-182083.43" + attribute \src "libresoc.v:183633.3-183672.6" + wire width 4 $0\src25__data_o$next[3:0]$11617 + attribute \src "libresoc.v:183390.3-183391.43" wire width 4 $0\src25__data_o[3:0] - attribute \src "libresoc.v:182395.3-182434.6" - wire width 4 $0\src35__data_o$next[3:0]$11647 - attribute \src "libresoc.v:182080.3-182081.43" + attribute \src "libresoc.v:183703.3-183742.6" + wire width 4 $0\src35__data_o$next[3:0]$11631 + attribute \src "libresoc.v:183388.3-183389.43" wire width 4 $0\src35__data_o[3:0] - attribute \src "libresoc.v:182435.3-182464.6" - wire $0\wr_detect$10[0:0]$11655 - attribute \src "libresoc.v:182505.3-182534.6" - wire $0\wr_detect$13[0:0]$11669 - attribute \src "libresoc.v:182198.3-182227.6" - wire $0\wr_detect$16[0:0]$11607 - attribute \src "libresoc.v:182295.3-182324.6" - wire $0\wr_detect$4[0:0]$11627 - attribute \src "libresoc.v:182365.3-182394.6" - wire $0\wr_detect$7[0:0]$11641 - attribute \src "libresoc.v:182128.3-182157.6" + attribute \src "libresoc.v:183743.3-183772.6" + wire $0\wr_detect$10[0:0]$11639 + attribute \src "libresoc.v:183813.3-183842.6" + wire $0\wr_detect$13[0:0]$11653 + attribute \src "libresoc.v:183506.3-183535.6" + wire $0\wr_detect$16[0:0]$11591 + attribute \src "libresoc.v:183603.3-183632.6" + wire $0\wr_detect$4[0:0]$11611 + attribute \src "libresoc.v:183673.3-183702.6" + wire $0\wr_detect$7[0:0]$11625 + attribute \src "libresoc.v:183436.3-183465.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:182088.3-182127.6" - wire width 4 $1\cr_pred5__data_o$next[3:0]$11591 - attribute \src "libresoc.v:182000.13-182000.36" + attribute \src "libresoc.v:183396.3-183435.6" + wire width 4 $1\cr_pred5__data_o$next[3:0]$11575 + attribute \src "libresoc.v:183308.13-183308.36" wire width 4 $1\cr_pred5__data_o[3:0] - attribute \src "libresoc.v:182158.3-182197.6" - wire width 4 $1\r25__data_o$next[3:0]$11600 - attribute \src "libresoc.v:182015.13-182015.31" + attribute \src "libresoc.v:183466.3-183505.6" + wire width 4 $1\r25__data_o$next[3:0]$11584 + attribute \src "libresoc.v:183323.13-183323.31" wire width 4 $1\r25__data_o[3:0] - attribute \src "libresoc.v:182465.3-182504.6" - wire width 4 $1\r5__data_o$next[3:0]$11662 - attribute \src "libresoc.v:182022.13-182022.30" + attribute \src "libresoc.v:183773.3-183812.6" + wire width 4 $1\r5__data_o$next[3:0]$11646 + attribute \src "libresoc.v:183330.13-183330.30" wire width 4 $1\r5__data_o[3:0] - attribute \src "libresoc.v:182228.3-182254.6" - wire width 4 $1\reg$next[3:0]$11614 - attribute \src "libresoc.v:182028.13-182028.25" + attribute \src "libresoc.v:183536.3-183562.6" + wire width 4 $1\reg$next[3:0]$11598 + attribute \src "libresoc.v:183336.13-183336.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:182255.3-182294.6" - wire width 4 $1\src15__data_o$next[3:0]$11620 - attribute \src "libresoc.v:182033.13-182033.33" + attribute \src "libresoc.v:183563.3-183602.6" + wire width 4 $1\src15__data_o$next[3:0]$11604 + attribute \src "libresoc.v:183341.13-183341.33" wire width 4 $1\src15__data_o[3:0] - attribute \src "libresoc.v:182325.3-182364.6" - wire width 4 $1\src25__data_o$next[3:0]$11634 - attribute \src "libresoc.v:182040.13-182040.33" + attribute \src "libresoc.v:183633.3-183672.6" + wire width 4 $1\src25__data_o$next[3:0]$11618 + attribute \src "libresoc.v:183348.13-183348.33" wire width 4 $1\src25__data_o[3:0] - attribute \src "libresoc.v:182395.3-182434.6" - wire width 4 $1\src35__data_o$next[3:0]$11648 - attribute \src "libresoc.v:182047.13-182047.33" + attribute \src "libresoc.v:183703.3-183742.6" + wire width 4 $1\src35__data_o$next[3:0]$11632 + attribute \src "libresoc.v:183355.13-183355.33" wire width 4 $1\src35__data_o[3:0] - attribute \src "libresoc.v:182435.3-182464.6" - wire $1\wr_detect$10[0:0]$11656 - attribute \src "libresoc.v:182505.3-182534.6" - wire $1\wr_detect$13[0:0]$11670 - attribute \src "libresoc.v:182198.3-182227.6" - wire $1\wr_detect$16[0:0]$11608 - attribute \src "libresoc.v:182295.3-182324.6" - wire $1\wr_detect$4[0:0]$11628 - attribute \src "libresoc.v:182365.3-182394.6" - wire $1\wr_detect$7[0:0]$11642 - attribute \src "libresoc.v:182128.3-182157.6" + attribute \src "libresoc.v:183743.3-183772.6" + wire $1\wr_detect$10[0:0]$11640 + attribute \src "libresoc.v:183813.3-183842.6" + wire $1\wr_detect$13[0:0]$11654 + attribute \src "libresoc.v:183506.3-183535.6" + wire $1\wr_detect$16[0:0]$11592 + attribute \src "libresoc.v:183603.3-183632.6" + wire $1\wr_detect$4[0:0]$11612 + attribute \src "libresoc.v:183673.3-183702.6" + wire $1\wr_detect$7[0:0]$11626 + attribute \src "libresoc.v:183436.3-183465.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:182088.3-182127.6" - wire width 4 $2\cr_pred5__data_o$next[3:0]$11592 - attribute \src "libresoc.v:182158.3-182197.6" - wire width 4 $2\r25__data_o$next[3:0]$11601 - attribute \src "libresoc.v:182465.3-182504.6" - wire width 4 $2\r5__data_o$next[3:0]$11663 - attribute \src "libresoc.v:182228.3-182254.6" - wire width 4 $2\reg$next[3:0]$11615 - attribute \src "libresoc.v:182255.3-182294.6" - wire width 4 $2\src15__data_o$next[3:0]$11621 - attribute \src "libresoc.v:182325.3-182364.6" - wire width 4 $2\src25__data_o$next[3:0]$11635 - attribute \src "libresoc.v:182395.3-182434.6" - wire width 4 $2\src35__data_o$next[3:0]$11649 - attribute \src "libresoc.v:182435.3-182464.6" - wire $2\wr_detect$10[0:0]$11657 - attribute \src "libresoc.v:182505.3-182534.6" - wire $2\wr_detect$13[0:0]$11671 - attribute \src "libresoc.v:182198.3-182227.6" - wire $2\wr_detect$16[0:0]$11609 - attribute \src "libresoc.v:182295.3-182324.6" - wire $2\wr_detect$4[0:0]$11629 - attribute \src "libresoc.v:182365.3-182394.6" - wire $2\wr_detect$7[0:0]$11643 - attribute \src "libresoc.v:182128.3-182157.6" + attribute \src "libresoc.v:183396.3-183435.6" + wire width 4 $2\cr_pred5__data_o$next[3:0]$11576 + attribute \src "libresoc.v:183466.3-183505.6" + wire width 4 $2\r25__data_o$next[3:0]$11585 + attribute \src "libresoc.v:183773.3-183812.6" + wire width 4 $2\r5__data_o$next[3:0]$11647 + attribute \src "libresoc.v:183536.3-183562.6" + wire width 4 $2\reg$next[3:0]$11599 + attribute \src "libresoc.v:183563.3-183602.6" + wire width 4 $2\src15__data_o$next[3:0]$11605 + attribute \src "libresoc.v:183633.3-183672.6" + wire width 4 $2\src25__data_o$next[3:0]$11619 + attribute \src "libresoc.v:183703.3-183742.6" + wire width 4 $2\src35__data_o$next[3:0]$11633 + attribute \src "libresoc.v:183743.3-183772.6" + wire $2\wr_detect$10[0:0]$11641 + attribute \src "libresoc.v:183813.3-183842.6" + wire $2\wr_detect$13[0:0]$11655 + attribute \src "libresoc.v:183506.3-183535.6" + wire $2\wr_detect$16[0:0]$11593 + attribute \src "libresoc.v:183603.3-183632.6" + wire $2\wr_detect$4[0:0]$11613 + attribute \src "libresoc.v:183673.3-183702.6" + wire $2\wr_detect$7[0:0]$11627 + attribute \src "libresoc.v:183436.3-183465.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:182088.3-182127.6" - wire width 4 $3\cr_pred5__data_o$next[3:0]$11593 - attribute \src "libresoc.v:182158.3-182197.6" - wire width 4 $3\r25__data_o$next[3:0]$11602 - attribute \src "libresoc.v:182465.3-182504.6" - wire width 4 $3\r5__data_o$next[3:0]$11664 - attribute \src "libresoc.v:182228.3-182254.6" - wire width 4 $3\reg$next[3:0]$11616 - attribute \src "libresoc.v:182255.3-182294.6" - wire width 4 $3\src15__data_o$next[3:0]$11622 - attribute \src "libresoc.v:182325.3-182364.6" - wire width 4 $3\src25__data_o$next[3:0]$11636 - attribute \src "libresoc.v:182395.3-182434.6" - wire width 4 $3\src35__data_o$next[3:0]$11650 - attribute \src "libresoc.v:182435.3-182464.6" - wire $3\wr_detect$10[0:0]$11658 - attribute \src "libresoc.v:182505.3-182534.6" - wire $3\wr_detect$13[0:0]$11672 - attribute \src "libresoc.v:182198.3-182227.6" - wire $3\wr_detect$16[0:0]$11610 - attribute \src "libresoc.v:182295.3-182324.6" - wire $3\wr_detect$4[0:0]$11630 - attribute \src "libresoc.v:182365.3-182394.6" - wire $3\wr_detect$7[0:0]$11644 - attribute \src "libresoc.v:182128.3-182157.6" + attribute \src "libresoc.v:183396.3-183435.6" + wire width 4 $3\cr_pred5__data_o$next[3:0]$11577 + attribute \src "libresoc.v:183466.3-183505.6" + wire width 4 $3\r25__data_o$next[3:0]$11586 + attribute \src "libresoc.v:183773.3-183812.6" + wire width 4 $3\r5__data_o$next[3:0]$11648 + attribute \src "libresoc.v:183536.3-183562.6" + wire width 4 $3\reg$next[3:0]$11600 + attribute \src "libresoc.v:183563.3-183602.6" + wire width 4 $3\src15__data_o$next[3:0]$11606 + attribute \src "libresoc.v:183633.3-183672.6" + wire width 4 $3\src25__data_o$next[3:0]$11620 + attribute \src "libresoc.v:183703.3-183742.6" + wire width 4 $3\src35__data_o$next[3:0]$11634 + attribute \src "libresoc.v:183743.3-183772.6" + wire $3\wr_detect$10[0:0]$11642 + attribute \src "libresoc.v:183813.3-183842.6" + wire $3\wr_detect$13[0:0]$11656 + attribute \src "libresoc.v:183506.3-183535.6" + wire $3\wr_detect$16[0:0]$11594 + attribute \src "libresoc.v:183603.3-183632.6" + wire $3\wr_detect$4[0:0]$11614 + attribute \src "libresoc.v:183673.3-183702.6" + wire $3\wr_detect$7[0:0]$11628 + attribute \src "libresoc.v:183436.3-183465.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:182088.3-182127.6" - wire width 4 $4\cr_pred5__data_o$next[3:0]$11594 - attribute \src "libresoc.v:182158.3-182197.6" - wire width 4 $4\r25__data_o$next[3:0]$11603 - attribute \src "libresoc.v:182465.3-182504.6" - wire width 4 $4\r5__data_o$next[3:0]$11665 - attribute \src "libresoc.v:182228.3-182254.6" - wire width 4 $4\reg$next[3:0]$11617 - attribute \src "libresoc.v:182255.3-182294.6" - wire width 4 $4\src15__data_o$next[3:0]$11623 - attribute \src "libresoc.v:182325.3-182364.6" - wire width 4 $4\src25__data_o$next[3:0]$11637 - attribute \src "libresoc.v:182395.3-182434.6" - wire width 4 $4\src35__data_o$next[3:0]$11651 - attribute \src "libresoc.v:182435.3-182464.6" - wire $4\wr_detect$10[0:0]$11659 - attribute \src "libresoc.v:182505.3-182534.6" - wire $4\wr_detect$13[0:0]$11673 - attribute \src "libresoc.v:182198.3-182227.6" - wire $4\wr_detect$16[0:0]$11611 - attribute \src "libresoc.v:182295.3-182324.6" - wire $4\wr_detect$4[0:0]$11631 - attribute \src "libresoc.v:182365.3-182394.6" - wire $4\wr_detect$7[0:0]$11645 - attribute \src "libresoc.v:182128.3-182157.6" + attribute \src "libresoc.v:183396.3-183435.6" + wire width 4 $4\cr_pred5__data_o$next[3:0]$11578 + attribute \src "libresoc.v:183466.3-183505.6" + wire width 4 $4\r25__data_o$next[3:0]$11587 + attribute \src "libresoc.v:183773.3-183812.6" + wire width 4 $4\r5__data_o$next[3:0]$11649 + attribute \src "libresoc.v:183536.3-183562.6" + wire width 4 $4\reg$next[3:0]$11601 + attribute \src "libresoc.v:183563.3-183602.6" + wire width 4 $4\src15__data_o$next[3:0]$11607 + attribute \src "libresoc.v:183633.3-183672.6" + wire width 4 $4\src25__data_o$next[3:0]$11621 + attribute \src "libresoc.v:183703.3-183742.6" + wire width 4 $4\src35__data_o$next[3:0]$11635 + attribute \src "libresoc.v:183743.3-183772.6" + wire $4\wr_detect$10[0:0]$11643 + attribute \src "libresoc.v:183813.3-183842.6" + wire $4\wr_detect$13[0:0]$11657 + attribute \src "libresoc.v:183506.3-183535.6" + wire $4\wr_detect$16[0:0]$11595 + attribute \src "libresoc.v:183603.3-183632.6" + wire $4\wr_detect$4[0:0]$11615 + attribute \src "libresoc.v:183673.3-183702.6" + wire $4\wr_detect$7[0:0]$11629 + attribute \src "libresoc.v:183436.3-183465.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:182088.3-182127.6" - wire width 4 $5\cr_pred5__data_o$next[3:0]$11595 - attribute \src "libresoc.v:182158.3-182197.6" - wire width 4 $5\r25__data_o$next[3:0]$11604 - attribute \src "libresoc.v:182465.3-182504.6" - wire width 4 $5\r5__data_o$next[3:0]$11666 - attribute \src "libresoc.v:182255.3-182294.6" - wire width 4 $5\src15__data_o$next[3:0]$11624 - attribute \src "libresoc.v:182325.3-182364.6" - wire width 4 $5\src25__data_o$next[3:0]$11638 - attribute \src "libresoc.v:182395.3-182434.6" - wire width 4 $5\src35__data_o$next[3:0]$11652 - attribute \src "libresoc.v:182088.3-182127.6" - wire width 4 $6\cr_pred5__data_o$next[3:0]$11596 - attribute \src "libresoc.v:182158.3-182197.6" - wire width 4 $6\r25__data_o$next[3:0]$11605 - attribute \src "libresoc.v:182465.3-182504.6" - wire width 4 $6\r5__data_o$next[3:0]$11667 - attribute \src "libresoc.v:182255.3-182294.6" - wire width 4 $6\src15__data_o$next[3:0]$11625 - attribute \src "libresoc.v:182325.3-182364.6" - wire width 4 $6\src25__data_o$next[3:0]$11639 - attribute \src "libresoc.v:182395.3-182434.6" - wire width 4 $6\src35__data_o$next[3:0]$11653 - attribute \src "libresoc.v:182068.17-182068.104" - wire $not$libresoc.v:182068$11576_Y - attribute \src "libresoc.v:182069.18-182069.105" - wire $not$libresoc.v:182069$11577_Y - attribute \src "libresoc.v:182070.18-182070.105" - wire $not$libresoc.v:182070$11578_Y - attribute \src "libresoc.v:182071.17-182071.100" - wire $not$libresoc.v:182071$11579_Y - attribute \src "libresoc.v:182072.17-182072.103" - wire $not$libresoc.v:182072$11580_Y - attribute \src "libresoc.v:182073.17-182073.103" - wire $not$libresoc.v:182073$11581_Y + attribute \src "libresoc.v:183396.3-183435.6" + wire width 4 $5\cr_pred5__data_o$next[3:0]$11579 + attribute \src "libresoc.v:183466.3-183505.6" + wire width 4 $5\r25__data_o$next[3:0]$11588 + attribute \src "libresoc.v:183773.3-183812.6" + wire width 4 $5\r5__data_o$next[3:0]$11650 + attribute \src "libresoc.v:183563.3-183602.6" + wire width 4 $5\src15__data_o$next[3:0]$11608 + attribute \src "libresoc.v:183633.3-183672.6" + wire width 4 $5\src25__data_o$next[3:0]$11622 + attribute \src "libresoc.v:183703.3-183742.6" + wire width 4 $5\src35__data_o$next[3:0]$11636 + attribute \src "libresoc.v:183396.3-183435.6" + wire width 4 $6\cr_pred5__data_o$next[3:0]$11580 + attribute \src "libresoc.v:183466.3-183505.6" + wire width 4 $6\r25__data_o$next[3:0]$11589 + attribute \src "libresoc.v:183773.3-183812.6" + wire width 4 $6\r5__data_o$next[3:0]$11651 + attribute \src "libresoc.v:183563.3-183602.6" + wire width 4 $6\src15__data_o$next[3:0]$11609 + attribute \src "libresoc.v:183633.3-183672.6" + wire width 4 $6\src25__data_o$next[3:0]$11623 + attribute \src "libresoc.v:183703.3-183742.6" + wire width 4 $6\src35__data_o$next[3:0]$11637 + attribute \src "libresoc.v:183376.17-183376.104" + wire $not$libresoc.v:183376$11560_Y + attribute \src "libresoc.v:183377.18-183377.105" + wire $not$libresoc.v:183377$11561_Y + attribute \src "libresoc.v:183378.18-183378.105" + wire $not$libresoc.v:183378$11562_Y + attribute \src "libresoc.v:183379.17-183379.100" + wire $not$libresoc.v:183379$11563_Y + attribute \src "libresoc.v:183380.17-183380.103" + wire $not$libresoc.v:183380$11564_Y + attribute \src "libresoc.v:183381.17-183381.103" + wire $not$libresoc.v:183381$11565_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -371432,9 +342802,9 @@ module \reg_5 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 20 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 3 \cr_pred5__data_o @@ -371450,7 +342820,7 @@ module \reg_5 wire width 4 input 13 \dest25__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest25__wen - attribute \src "libresoc.v:181981.7-181981.15" + attribute \src "libresoc.v:183289.7-183289.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 16 \r25__data_o @@ -371503,175 +342873,175 @@ module \reg_5 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182068$11576 + cell $not $not$libresoc.v:183376$11560 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:182068$11576_Y + connect \Y $not$libresoc.v:183376$11560_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182069$11577 + cell $not $not$libresoc.v:183377$11561 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:182069$11577_Y + connect \Y $not$libresoc.v:183377$11561_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182070$11578 + cell $not $not$libresoc.v:183378$11562 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$16 - connect \Y $not$libresoc.v:182070$11578_Y + connect \Y $not$libresoc.v:183378$11562_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182071$11579 + cell $not $not$libresoc.v:183379$11563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:182071$11579_Y + connect \Y $not$libresoc.v:183379$11563_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182072$11580 + cell $not $not$libresoc.v:183380$11564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:182072$11580_Y + connect \Y $not$libresoc.v:183380$11564_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182073$11581 + cell $not $not$libresoc.v:183381$11565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:182073$11581_Y + connect \Y $not$libresoc.v:183381$11565_Y end - attribute \src "libresoc.v:181981.7-181981.20" - process $proc$libresoc.v:181981$11674 + attribute \src "libresoc.v:183289.7-183289.20" + process $proc$libresoc.v:183289$11658 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:182000.13-182000.36" - process $proc$libresoc.v:182000$11675 + attribute \src "libresoc.v:183308.13-183308.36" + process $proc$libresoc.v:183308$11659 assign { } { } assign $1\cr_pred5__data_o[3:0] 4'0000 sync always sync init update \cr_pred5__data_o $1\cr_pred5__data_o[3:0] end - attribute \src "libresoc.v:182015.13-182015.31" - process $proc$libresoc.v:182015$11676 + attribute \src "libresoc.v:183323.13-183323.31" + process $proc$libresoc.v:183323$11660 assign { } { } assign $1\r25__data_o[3:0] 4'0000 sync always sync init update \r25__data_o $1\r25__data_o[3:0] end - attribute \src "libresoc.v:182022.13-182022.30" - process $proc$libresoc.v:182022$11677 + attribute \src "libresoc.v:183330.13-183330.30" + process $proc$libresoc.v:183330$11661 assign { } { } assign $1\r5__data_o[3:0] 4'0000 sync always sync init update \r5__data_o $1\r5__data_o[3:0] end - attribute \src "libresoc.v:182028.13-182028.25" - process $proc$libresoc.v:182028$11678 + attribute \src "libresoc.v:183336.13-183336.25" + process $proc$libresoc.v:183336$11662 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:182033.13-182033.33" - process $proc$libresoc.v:182033$11679 + attribute \src "libresoc.v:183341.13-183341.33" + process $proc$libresoc.v:183341$11663 assign { } { } assign $1\src15__data_o[3:0] 4'0000 sync always sync init update \src15__data_o $1\src15__data_o[3:0] end - attribute \src "libresoc.v:182040.13-182040.33" - process $proc$libresoc.v:182040$11680 + attribute \src "libresoc.v:183348.13-183348.33" + process $proc$libresoc.v:183348$11664 assign { } { } assign $1\src25__data_o[3:0] 4'0000 sync always sync init update \src25__data_o $1\src25__data_o[3:0] end - attribute \src "libresoc.v:182047.13-182047.33" - process $proc$libresoc.v:182047$11681 + attribute \src "libresoc.v:183355.13-183355.33" + process $proc$libresoc.v:183355$11665 assign { } { } assign $1\src35__data_o[3:0] 4'0000 sync always sync init update \src35__data_o $1\src35__data_o[3:0] end - attribute \src "libresoc.v:182074.3-182075.25" - process $proc$libresoc.v:182074$11582 + attribute \src "libresoc.v:183382.3-183383.25" + process $proc$libresoc.v:183382$11566 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:182076.3-182077.39" - process $proc$libresoc.v:182076$11583 + attribute \src "libresoc.v:183384.3-183385.39" + process $proc$libresoc.v:183384$11567 assign { } { } assign $0\r25__data_o[3:0] \r25__data_o$next sync posedge \coresync_clk update \r25__data_o $0\r25__data_o[3:0] end - attribute \src "libresoc.v:182078.3-182079.37" - process $proc$libresoc.v:182078$11584 + attribute \src "libresoc.v:183386.3-183387.37" + process $proc$libresoc.v:183386$11568 assign { } { } assign $0\r5__data_o[3:0] \r5__data_o$next sync posedge \coresync_clk update \r5__data_o $0\r5__data_o[3:0] end - attribute \src "libresoc.v:182080.3-182081.43" - process $proc$libresoc.v:182080$11585 + attribute \src "libresoc.v:183388.3-183389.43" + process $proc$libresoc.v:183388$11569 assign { } { } assign $0\src35__data_o[3:0] \src35__data_o$next sync posedge \coresync_clk update \src35__data_o $0\src35__data_o[3:0] end - attribute \src "libresoc.v:182082.3-182083.43" - process $proc$libresoc.v:182082$11586 + attribute \src "libresoc.v:183390.3-183391.43" + process $proc$libresoc.v:183390$11570 assign { } { } assign $0\src25__data_o[3:0] \src25__data_o$next sync posedge \coresync_clk update \src25__data_o $0\src25__data_o[3:0] end - attribute \src "libresoc.v:182084.3-182085.43" - process $proc$libresoc.v:182084$11587 + attribute \src "libresoc.v:183392.3-183393.43" + process $proc$libresoc.v:183392$11571 assign { } { } assign $0\src15__data_o[3:0] \src15__data_o$next sync posedge \coresync_clk update \src15__data_o $0\src15__data_o[3:0] end - attribute \src "libresoc.v:182086.3-182087.49" - process $proc$libresoc.v:182086$11588 + attribute \src "libresoc.v:183394.3-183395.49" + process $proc$libresoc.v:183394$11572 assign { } { } assign $0\cr_pred5__data_o[3:0] \cr_pred5__data_o$next sync posedge \coresync_clk update \cr_pred5__data_o $0\cr_pred5__data_o[3:0] end - attribute \src "libresoc.v:182088.3-182127.6" - process $proc$libresoc.v:182088$11589 + attribute \src "libresoc.v:183396.3-183435.6" + process $proc$libresoc.v:183396$11573 assign { } { } assign { } { } assign { } { } - assign $0\cr_pred5__data_o$next[3:0]$11590 $6\cr_pred5__data_o$next[3:0]$11596 - attribute \src "libresoc.v:182089.5-182089.29" + assign $0\cr_pred5__data_o$next[3:0]$11574 $6\cr_pred5__data_o$next[3:0]$11580 + attribute \src "libresoc.v:183397.5-183397.29" switch \initial - attribute \src "libresoc.v:182089.9-182089.17" + attribute \src "libresoc.v:183397.9-183397.17" case 1'1 case end @@ -371683,66 +343053,66 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\cr_pred5__data_o$next[3:0]$11591 $5\cr_pred5__data_o$next[3:0]$11595 + assign $1\cr_pred5__data_o$next[3:0]$11575 $5\cr_pred5__data_o$next[3:0]$11579 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_pred5__data_o$next[3:0]$11592 \dest15__data_i + assign $2\cr_pred5__data_o$next[3:0]$11576 \dest15__data_i case - assign $2\cr_pred5__data_o$next[3:0]$11592 4'0000 + assign $2\cr_pred5__data_o$next[3:0]$11576 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\cr_pred5__data_o$next[3:0]$11593 \dest25__data_i + assign $3\cr_pred5__data_o$next[3:0]$11577 \dest25__data_i case - assign $3\cr_pred5__data_o$next[3:0]$11593 $2\cr_pred5__data_o$next[3:0]$11592 + assign $3\cr_pred5__data_o$next[3:0]$11577 $2\cr_pred5__data_o$next[3:0]$11576 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cr_pred5__data_o$next[3:0]$11594 \w5__data_i + assign $4\cr_pred5__data_o$next[3:0]$11578 \w5__data_i case - assign $4\cr_pred5__data_o$next[3:0]$11594 $3\cr_pred5__data_o$next[3:0]$11593 + assign $4\cr_pred5__data_o$next[3:0]$11578 $3\cr_pred5__data_o$next[3:0]$11577 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\cr_pred5__data_o$next[3:0]$11595 \reg + assign $5\cr_pred5__data_o$next[3:0]$11579 \reg case - assign $5\cr_pred5__data_o$next[3:0]$11595 $4\cr_pred5__data_o$next[3:0]$11594 + assign $5\cr_pred5__data_o$next[3:0]$11579 $4\cr_pred5__data_o$next[3:0]$11578 end case - assign $1\cr_pred5__data_o$next[3:0]$11591 4'0000 + assign $1\cr_pred5__data_o$next[3:0]$11575 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cr_pred5__data_o$next[3:0]$11596 4'0000 + assign $6\cr_pred5__data_o$next[3:0]$11580 4'0000 case - assign $6\cr_pred5__data_o$next[3:0]$11596 $1\cr_pred5__data_o$next[3:0]$11591 + assign $6\cr_pred5__data_o$next[3:0]$11580 $1\cr_pred5__data_o$next[3:0]$11575 end sync always - update \cr_pred5__data_o$next $0\cr_pred5__data_o$next[3:0]$11590 + update \cr_pred5__data_o$next $0\cr_pred5__data_o$next[3:0]$11574 end - attribute \src "libresoc.v:182128.3-182157.6" - process $proc$libresoc.v:182128$11597 + attribute \src "libresoc.v:183436.3-183465.6" + process $proc$libresoc.v:183436$11581 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:182129.5-182129.29" + attribute \src "libresoc.v:183437.5-183437.29" switch \initial - attribute \src "libresoc.v:182129.9-182129.17" + attribute \src "libresoc.v:183437.9-183437.17" case 1'1 case end @@ -371788,15 +343158,15 @@ module \reg_5 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:182158.3-182197.6" - process $proc$libresoc.v:182158$11598 + attribute \src "libresoc.v:183466.3-183505.6" + process $proc$libresoc.v:183466$11582 assign { } { } assign { } { } assign { } { } - assign $0\r25__data_o$next[3:0]$11599 $6\r25__data_o$next[3:0]$11605 - attribute \src "libresoc.v:182159.5-182159.29" + assign $0\r25__data_o$next[3:0]$11583 $6\r25__data_o$next[3:0]$11589 + attribute \src "libresoc.v:183467.5-183467.29" switch \initial - attribute \src "libresoc.v:182159.9-182159.17" + attribute \src "libresoc.v:183467.9-183467.17" case 1'1 case end @@ -371808,66 +343178,66 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\r25__data_o$next[3:0]$11600 $5\r25__data_o$next[3:0]$11604 + assign $1\r25__data_o$next[3:0]$11584 $5\r25__data_o$next[3:0]$11588 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r25__data_o$next[3:0]$11601 \dest15__data_i + assign $2\r25__data_o$next[3:0]$11585 \dest15__data_i case - assign $2\r25__data_o$next[3:0]$11601 4'0000 + assign $2\r25__data_o$next[3:0]$11585 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r25__data_o$next[3:0]$11602 \dest25__data_i + assign $3\r25__data_o$next[3:0]$11586 \dest25__data_i case - assign $3\r25__data_o$next[3:0]$11602 $2\r25__data_o$next[3:0]$11601 + assign $3\r25__data_o$next[3:0]$11586 $2\r25__data_o$next[3:0]$11585 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r25__data_o$next[3:0]$11603 \w5__data_i + assign $4\r25__data_o$next[3:0]$11587 \w5__data_i case - assign $4\r25__data_o$next[3:0]$11603 $3\r25__data_o$next[3:0]$11602 + assign $4\r25__data_o$next[3:0]$11587 $3\r25__data_o$next[3:0]$11586 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$15 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r25__data_o$next[3:0]$11604 \reg + assign $5\r25__data_o$next[3:0]$11588 \reg case - assign $5\r25__data_o$next[3:0]$11604 $4\r25__data_o$next[3:0]$11603 + assign $5\r25__data_o$next[3:0]$11588 $4\r25__data_o$next[3:0]$11587 end case - assign $1\r25__data_o$next[3:0]$11600 4'0000 + assign $1\r25__data_o$next[3:0]$11584 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r25__data_o$next[3:0]$11605 4'0000 + assign $6\r25__data_o$next[3:0]$11589 4'0000 case - assign $6\r25__data_o$next[3:0]$11605 $1\r25__data_o$next[3:0]$11600 + assign $6\r25__data_o$next[3:0]$11589 $1\r25__data_o$next[3:0]$11584 end sync always - update \r25__data_o$next $0\r25__data_o$next[3:0]$11599 + update \r25__data_o$next $0\r25__data_o$next[3:0]$11583 end - attribute \src "libresoc.v:182198.3-182227.6" - process $proc$libresoc.v:182198$11606 + attribute \src "libresoc.v:183506.3-183535.6" + process $proc$libresoc.v:183506$11590 assign { } { } assign { } { } - assign $0\wr_detect$16[0:0]$11607 $1\wr_detect$16[0:0]$11608 - attribute \src "libresoc.v:182199.5-182199.29" + assign $0\wr_detect$16[0:0]$11591 $1\wr_detect$16[0:0]$11592 + attribute \src "libresoc.v:183507.5-183507.29" switch \initial - attribute \src "libresoc.v:182199.9-182199.17" + attribute \src "libresoc.v:183507.9-183507.17" case 1'1 case end @@ -371879,51 +343249,51 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$16[0:0]$11608 $4\wr_detect$16[0:0]$11611 + assign $1\wr_detect$16[0:0]$11592 $4\wr_detect$16[0:0]$11595 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$16[0:0]$11609 1'1 + assign $2\wr_detect$16[0:0]$11593 1'1 case - assign $2\wr_detect$16[0:0]$11609 1'0 + assign $2\wr_detect$16[0:0]$11593 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$16[0:0]$11610 1'1 + assign $3\wr_detect$16[0:0]$11594 1'1 case - assign $3\wr_detect$16[0:0]$11610 $2\wr_detect$16[0:0]$11609 + assign $3\wr_detect$16[0:0]$11594 $2\wr_detect$16[0:0]$11593 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$16[0:0]$11611 1'1 + assign $4\wr_detect$16[0:0]$11595 1'1 case - assign $4\wr_detect$16[0:0]$11611 $3\wr_detect$16[0:0]$11610 + assign $4\wr_detect$16[0:0]$11595 $3\wr_detect$16[0:0]$11594 end case - assign $1\wr_detect$16[0:0]$11608 1'0 + assign $1\wr_detect$16[0:0]$11592 1'0 end sync always - update \wr_detect$16 $0\wr_detect$16[0:0]$11607 + update \wr_detect$16 $0\wr_detect$16[0:0]$11591 end - attribute \src "libresoc.v:182228.3-182254.6" - process $proc$libresoc.v:182228$11612 + attribute \src "libresoc.v:183536.3-183562.6" + process $proc$libresoc.v:183536$11596 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11613 $4\reg$next[3:0]$11617 - attribute \src "libresoc.v:182229.5-182229.29" + assign $0\reg$next[3:0]$11597 $4\reg$next[3:0]$11601 + attribute \src "libresoc.v:183537.5-183537.29" switch \initial - attribute \src "libresoc.v:182229.9-182229.17" + attribute \src "libresoc.v:183537.9-183537.17" case 1'1 case end @@ -371932,49 +343302,49 @@ module \reg_5 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11614 \dest15__data_i + assign $1\reg$next[3:0]$11598 \dest15__data_i case - assign $1\reg$next[3:0]$11614 \reg + assign $1\reg$next[3:0]$11598 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11615 \dest25__data_i + assign $2\reg$next[3:0]$11599 \dest25__data_i case - assign $2\reg$next[3:0]$11615 $1\reg$next[3:0]$11614 + assign $2\reg$next[3:0]$11599 $1\reg$next[3:0]$11598 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11616 \w5__data_i + assign $3\reg$next[3:0]$11600 \w5__data_i case - assign $3\reg$next[3:0]$11616 $2\reg$next[3:0]$11615 + assign $3\reg$next[3:0]$11600 $2\reg$next[3:0]$11599 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11617 4'0000 + assign $4\reg$next[3:0]$11601 4'0000 case - assign $4\reg$next[3:0]$11617 $3\reg$next[3:0]$11616 + assign $4\reg$next[3:0]$11601 $3\reg$next[3:0]$11600 end sync always - update \reg$next $0\reg$next[3:0]$11613 + update \reg$next $0\reg$next[3:0]$11597 end - attribute \src "libresoc.v:182255.3-182294.6" - process $proc$libresoc.v:182255$11618 + attribute \src "libresoc.v:183563.3-183602.6" + process $proc$libresoc.v:183563$11602 assign { } { } assign { } { } assign { } { } - assign $0\src15__data_o$next[3:0]$11619 $6\src15__data_o$next[3:0]$11625 - attribute \src "libresoc.v:182256.5-182256.29" + assign $0\src15__data_o$next[3:0]$11603 $6\src15__data_o$next[3:0]$11609 + attribute \src "libresoc.v:183564.5-183564.29" switch \initial - attribute \src "libresoc.v:182256.9-182256.17" + attribute \src "libresoc.v:183564.9-183564.17" case 1'1 case end @@ -371986,66 +343356,66 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\src15__data_o$next[3:0]$11620 $5\src15__data_o$next[3:0]$11624 + assign $1\src15__data_o$next[3:0]$11604 $5\src15__data_o$next[3:0]$11608 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src15__data_o$next[3:0]$11621 \dest15__data_i + assign $2\src15__data_o$next[3:0]$11605 \dest15__data_i case - assign $2\src15__data_o$next[3:0]$11621 4'0000 + assign $2\src15__data_o$next[3:0]$11605 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src15__data_o$next[3:0]$11622 \dest25__data_i + assign $3\src15__data_o$next[3:0]$11606 \dest25__data_i case - assign $3\src15__data_o$next[3:0]$11622 $2\src15__data_o$next[3:0]$11621 + assign $3\src15__data_o$next[3:0]$11606 $2\src15__data_o$next[3:0]$11605 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src15__data_o$next[3:0]$11623 \w5__data_i + assign $4\src15__data_o$next[3:0]$11607 \w5__data_i case - assign $4\src15__data_o$next[3:0]$11623 $3\src15__data_o$next[3:0]$11622 + assign $4\src15__data_o$next[3:0]$11607 $3\src15__data_o$next[3:0]$11606 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src15__data_o$next[3:0]$11624 \reg + assign $5\src15__data_o$next[3:0]$11608 \reg case - assign $5\src15__data_o$next[3:0]$11624 $4\src15__data_o$next[3:0]$11623 + assign $5\src15__data_o$next[3:0]$11608 $4\src15__data_o$next[3:0]$11607 end case - assign $1\src15__data_o$next[3:0]$11620 4'0000 + assign $1\src15__data_o$next[3:0]$11604 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src15__data_o$next[3:0]$11625 4'0000 + assign $6\src15__data_o$next[3:0]$11609 4'0000 case - assign $6\src15__data_o$next[3:0]$11625 $1\src15__data_o$next[3:0]$11620 + assign $6\src15__data_o$next[3:0]$11609 $1\src15__data_o$next[3:0]$11604 end sync always - update \src15__data_o$next $0\src15__data_o$next[3:0]$11619 + update \src15__data_o$next $0\src15__data_o$next[3:0]$11603 end - attribute \src "libresoc.v:182295.3-182324.6" - process $proc$libresoc.v:182295$11626 + attribute \src "libresoc.v:183603.3-183632.6" + process $proc$libresoc.v:183603$11610 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11627 $1\wr_detect$4[0:0]$11628 - attribute \src "libresoc.v:182296.5-182296.29" + assign $0\wr_detect$4[0:0]$11611 $1\wr_detect$4[0:0]$11612 + attribute \src "libresoc.v:183604.5-183604.29" switch \initial - attribute \src "libresoc.v:182296.9-182296.17" + attribute \src "libresoc.v:183604.9-183604.17" case 1'1 case end @@ -372057,49 +343427,49 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11628 $4\wr_detect$4[0:0]$11631 + assign $1\wr_detect$4[0:0]$11612 $4\wr_detect$4[0:0]$11615 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11629 1'1 + assign $2\wr_detect$4[0:0]$11613 1'1 case - assign $2\wr_detect$4[0:0]$11629 1'0 + assign $2\wr_detect$4[0:0]$11613 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11630 1'1 + assign $3\wr_detect$4[0:0]$11614 1'1 case - assign $3\wr_detect$4[0:0]$11630 $2\wr_detect$4[0:0]$11629 + assign $3\wr_detect$4[0:0]$11614 $2\wr_detect$4[0:0]$11613 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11631 1'1 + assign $4\wr_detect$4[0:0]$11615 1'1 case - assign $4\wr_detect$4[0:0]$11631 $3\wr_detect$4[0:0]$11630 + assign $4\wr_detect$4[0:0]$11615 $3\wr_detect$4[0:0]$11614 end case - assign $1\wr_detect$4[0:0]$11628 1'0 + assign $1\wr_detect$4[0:0]$11612 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11627 + update \wr_detect$4 $0\wr_detect$4[0:0]$11611 end - attribute \src "libresoc.v:182325.3-182364.6" - process $proc$libresoc.v:182325$11632 + attribute \src "libresoc.v:183633.3-183672.6" + process $proc$libresoc.v:183633$11616 assign { } { } assign { } { } assign { } { } - assign $0\src25__data_o$next[3:0]$11633 $6\src25__data_o$next[3:0]$11639 - attribute \src "libresoc.v:182326.5-182326.29" + assign $0\src25__data_o$next[3:0]$11617 $6\src25__data_o$next[3:0]$11623 + attribute \src "libresoc.v:183634.5-183634.29" switch \initial - attribute \src "libresoc.v:182326.9-182326.17" + attribute \src "libresoc.v:183634.9-183634.17" case 1'1 case end @@ -372111,66 +343481,66 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\src25__data_o$next[3:0]$11634 $5\src25__data_o$next[3:0]$11638 + assign $1\src25__data_o$next[3:0]$11618 $5\src25__data_o$next[3:0]$11622 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src25__data_o$next[3:0]$11635 \dest15__data_i + assign $2\src25__data_o$next[3:0]$11619 \dest15__data_i case - assign $2\src25__data_o$next[3:0]$11635 4'0000 + assign $2\src25__data_o$next[3:0]$11619 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src25__data_o$next[3:0]$11636 \dest25__data_i + assign $3\src25__data_o$next[3:0]$11620 \dest25__data_i case - assign $3\src25__data_o$next[3:0]$11636 $2\src25__data_o$next[3:0]$11635 + assign $3\src25__data_o$next[3:0]$11620 $2\src25__data_o$next[3:0]$11619 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src25__data_o$next[3:0]$11637 \w5__data_i + assign $4\src25__data_o$next[3:0]$11621 \w5__data_i case - assign $4\src25__data_o$next[3:0]$11637 $3\src25__data_o$next[3:0]$11636 + assign $4\src25__data_o$next[3:0]$11621 $3\src25__data_o$next[3:0]$11620 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src25__data_o$next[3:0]$11638 \reg + assign $5\src25__data_o$next[3:0]$11622 \reg case - assign $5\src25__data_o$next[3:0]$11638 $4\src25__data_o$next[3:0]$11637 + assign $5\src25__data_o$next[3:0]$11622 $4\src25__data_o$next[3:0]$11621 end case - assign $1\src25__data_o$next[3:0]$11634 4'0000 + assign $1\src25__data_o$next[3:0]$11618 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src25__data_o$next[3:0]$11639 4'0000 + assign $6\src25__data_o$next[3:0]$11623 4'0000 case - assign $6\src25__data_o$next[3:0]$11639 $1\src25__data_o$next[3:0]$11634 + assign $6\src25__data_o$next[3:0]$11623 $1\src25__data_o$next[3:0]$11618 end sync always - update \src25__data_o$next $0\src25__data_o$next[3:0]$11633 + update \src25__data_o$next $0\src25__data_o$next[3:0]$11617 end - attribute \src "libresoc.v:182365.3-182394.6" - process $proc$libresoc.v:182365$11640 + attribute \src "libresoc.v:183673.3-183702.6" + process $proc$libresoc.v:183673$11624 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11641 $1\wr_detect$7[0:0]$11642 - attribute \src "libresoc.v:182366.5-182366.29" + assign $0\wr_detect$7[0:0]$11625 $1\wr_detect$7[0:0]$11626 + attribute \src "libresoc.v:183674.5-183674.29" switch \initial - attribute \src "libresoc.v:182366.9-182366.17" + attribute \src "libresoc.v:183674.9-183674.17" case 1'1 case end @@ -372182,49 +343552,49 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11642 $4\wr_detect$7[0:0]$11645 + assign $1\wr_detect$7[0:0]$11626 $4\wr_detect$7[0:0]$11629 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11643 1'1 + assign $2\wr_detect$7[0:0]$11627 1'1 case - assign $2\wr_detect$7[0:0]$11643 1'0 + assign $2\wr_detect$7[0:0]$11627 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11644 1'1 + assign $3\wr_detect$7[0:0]$11628 1'1 case - assign $3\wr_detect$7[0:0]$11644 $2\wr_detect$7[0:0]$11643 + assign $3\wr_detect$7[0:0]$11628 $2\wr_detect$7[0:0]$11627 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11645 1'1 + assign $4\wr_detect$7[0:0]$11629 1'1 case - assign $4\wr_detect$7[0:0]$11645 $3\wr_detect$7[0:0]$11644 + assign $4\wr_detect$7[0:0]$11629 $3\wr_detect$7[0:0]$11628 end case - assign $1\wr_detect$7[0:0]$11642 1'0 + assign $1\wr_detect$7[0:0]$11626 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11641 + update \wr_detect$7 $0\wr_detect$7[0:0]$11625 end - attribute \src "libresoc.v:182395.3-182434.6" - process $proc$libresoc.v:182395$11646 + attribute \src "libresoc.v:183703.3-183742.6" + process $proc$libresoc.v:183703$11630 assign { } { } assign { } { } assign { } { } - assign $0\src35__data_o$next[3:0]$11647 $6\src35__data_o$next[3:0]$11653 - attribute \src "libresoc.v:182396.5-182396.29" + assign $0\src35__data_o$next[3:0]$11631 $6\src35__data_o$next[3:0]$11637 + attribute \src "libresoc.v:183704.5-183704.29" switch \initial - attribute \src "libresoc.v:182396.9-182396.17" + attribute \src "libresoc.v:183704.9-183704.17" case 1'1 case end @@ -372236,66 +343606,66 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\src35__data_o$next[3:0]$11648 $5\src35__data_o$next[3:0]$11652 + assign $1\src35__data_o$next[3:0]$11632 $5\src35__data_o$next[3:0]$11636 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src35__data_o$next[3:0]$11649 \dest15__data_i + assign $2\src35__data_o$next[3:0]$11633 \dest15__data_i case - assign $2\src35__data_o$next[3:0]$11649 4'0000 + assign $2\src35__data_o$next[3:0]$11633 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src35__data_o$next[3:0]$11650 \dest25__data_i + assign $3\src35__data_o$next[3:0]$11634 \dest25__data_i case - assign $3\src35__data_o$next[3:0]$11650 $2\src35__data_o$next[3:0]$11649 + assign $3\src35__data_o$next[3:0]$11634 $2\src35__data_o$next[3:0]$11633 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src35__data_o$next[3:0]$11651 \w5__data_i + assign $4\src35__data_o$next[3:0]$11635 \w5__data_i case - assign $4\src35__data_o$next[3:0]$11651 $3\src35__data_o$next[3:0]$11650 + assign $4\src35__data_o$next[3:0]$11635 $3\src35__data_o$next[3:0]$11634 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src35__data_o$next[3:0]$11652 \reg + assign $5\src35__data_o$next[3:0]$11636 \reg case - assign $5\src35__data_o$next[3:0]$11652 $4\src35__data_o$next[3:0]$11651 + assign $5\src35__data_o$next[3:0]$11636 $4\src35__data_o$next[3:0]$11635 end case - assign $1\src35__data_o$next[3:0]$11648 4'0000 + assign $1\src35__data_o$next[3:0]$11632 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src35__data_o$next[3:0]$11653 4'0000 + assign $6\src35__data_o$next[3:0]$11637 4'0000 case - assign $6\src35__data_o$next[3:0]$11653 $1\src35__data_o$next[3:0]$11648 + assign $6\src35__data_o$next[3:0]$11637 $1\src35__data_o$next[3:0]$11632 end sync always - update \src35__data_o$next $0\src35__data_o$next[3:0]$11647 + update \src35__data_o$next $0\src35__data_o$next[3:0]$11631 end - attribute \src "libresoc.v:182435.3-182464.6" - process $proc$libresoc.v:182435$11654 + attribute \src "libresoc.v:183743.3-183772.6" + process $proc$libresoc.v:183743$11638 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11655 $1\wr_detect$10[0:0]$11656 - attribute \src "libresoc.v:182436.5-182436.29" + assign $0\wr_detect$10[0:0]$11639 $1\wr_detect$10[0:0]$11640 + attribute \src "libresoc.v:183744.5-183744.29" switch \initial - attribute \src "libresoc.v:182436.9-182436.17" + attribute \src "libresoc.v:183744.9-183744.17" case 1'1 case end @@ -372307,49 +343677,49 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11656 $4\wr_detect$10[0:0]$11659 + assign $1\wr_detect$10[0:0]$11640 $4\wr_detect$10[0:0]$11643 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11657 1'1 + assign $2\wr_detect$10[0:0]$11641 1'1 case - assign $2\wr_detect$10[0:0]$11657 1'0 + assign $2\wr_detect$10[0:0]$11641 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11658 1'1 + assign $3\wr_detect$10[0:0]$11642 1'1 case - assign $3\wr_detect$10[0:0]$11658 $2\wr_detect$10[0:0]$11657 + assign $3\wr_detect$10[0:0]$11642 $2\wr_detect$10[0:0]$11641 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11659 1'1 + assign $4\wr_detect$10[0:0]$11643 1'1 case - assign $4\wr_detect$10[0:0]$11659 $3\wr_detect$10[0:0]$11658 + assign $4\wr_detect$10[0:0]$11643 $3\wr_detect$10[0:0]$11642 end case - assign $1\wr_detect$10[0:0]$11656 1'0 + assign $1\wr_detect$10[0:0]$11640 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11655 + update \wr_detect$10 $0\wr_detect$10[0:0]$11639 end - attribute \src "libresoc.v:182465.3-182504.6" - process $proc$libresoc.v:182465$11660 + attribute \src "libresoc.v:183773.3-183812.6" + process $proc$libresoc.v:183773$11644 assign { } { } assign { } { } assign { } { } - assign $0\r5__data_o$next[3:0]$11661 $6\r5__data_o$next[3:0]$11667 - attribute \src "libresoc.v:182466.5-182466.29" + assign $0\r5__data_o$next[3:0]$11645 $6\r5__data_o$next[3:0]$11651 + attribute \src "libresoc.v:183774.5-183774.29" switch \initial - attribute \src "libresoc.v:182466.9-182466.17" + attribute \src "libresoc.v:183774.9-183774.17" case 1'1 case end @@ -372361,66 +343731,66 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\r5__data_o$next[3:0]$11662 $5\r5__data_o$next[3:0]$11666 + assign $1\r5__data_o$next[3:0]$11646 $5\r5__data_o$next[3:0]$11650 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r5__data_o$next[3:0]$11663 \dest15__data_i + assign $2\r5__data_o$next[3:0]$11647 \dest15__data_i case - assign $2\r5__data_o$next[3:0]$11663 4'0000 + assign $2\r5__data_o$next[3:0]$11647 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r5__data_o$next[3:0]$11664 \dest25__data_i + assign $3\r5__data_o$next[3:0]$11648 \dest25__data_i case - assign $3\r5__data_o$next[3:0]$11664 $2\r5__data_o$next[3:0]$11663 + assign $3\r5__data_o$next[3:0]$11648 $2\r5__data_o$next[3:0]$11647 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r5__data_o$next[3:0]$11665 \w5__data_i + assign $4\r5__data_o$next[3:0]$11649 \w5__data_i case - assign $4\r5__data_o$next[3:0]$11665 $3\r5__data_o$next[3:0]$11664 + assign $4\r5__data_o$next[3:0]$11649 $3\r5__data_o$next[3:0]$11648 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r5__data_o$next[3:0]$11666 \reg + assign $5\r5__data_o$next[3:0]$11650 \reg case - assign $5\r5__data_o$next[3:0]$11666 $4\r5__data_o$next[3:0]$11665 + assign $5\r5__data_o$next[3:0]$11650 $4\r5__data_o$next[3:0]$11649 end case - assign $1\r5__data_o$next[3:0]$11662 4'0000 + assign $1\r5__data_o$next[3:0]$11646 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r5__data_o$next[3:0]$11667 4'0000 + assign $6\r5__data_o$next[3:0]$11651 4'0000 case - assign $6\r5__data_o$next[3:0]$11667 $1\r5__data_o$next[3:0]$11662 + assign $6\r5__data_o$next[3:0]$11651 $1\r5__data_o$next[3:0]$11646 end sync always - update \r5__data_o$next $0\r5__data_o$next[3:0]$11661 + update \r5__data_o$next $0\r5__data_o$next[3:0]$11645 end - attribute \src "libresoc.v:182505.3-182534.6" - process $proc$libresoc.v:182505$11668 + attribute \src "libresoc.v:183813.3-183842.6" + process $proc$libresoc.v:183813$11652 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11669 $1\wr_detect$13[0:0]$11670 - attribute \src "libresoc.v:182506.5-182506.29" + assign $0\wr_detect$13[0:0]$11653 $1\wr_detect$13[0:0]$11654 + attribute \src "libresoc.v:183814.5-183814.29" switch \initial - attribute \src "libresoc.v:182506.9-182506.17" + attribute \src "libresoc.v:183814.9-183814.17" case 1'1 case end @@ -372432,248 +343802,248 @@ module \reg_5 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11670 $4\wr_detect$13[0:0]$11673 + assign $1\wr_detect$13[0:0]$11654 $4\wr_detect$13[0:0]$11657 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest15__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11671 1'1 + assign $2\wr_detect$13[0:0]$11655 1'1 case - assign $2\wr_detect$13[0:0]$11671 1'0 + assign $2\wr_detect$13[0:0]$11655 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest25__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11672 1'1 + assign $3\wr_detect$13[0:0]$11656 1'1 case - assign $3\wr_detect$13[0:0]$11672 $2\wr_detect$13[0:0]$11671 + assign $3\wr_detect$13[0:0]$11656 $2\wr_detect$13[0:0]$11655 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w5__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11673 1'1 + assign $4\wr_detect$13[0:0]$11657 1'1 case - assign $4\wr_detect$13[0:0]$11673 $3\wr_detect$13[0:0]$11672 + assign $4\wr_detect$13[0:0]$11657 $3\wr_detect$13[0:0]$11656 end case - assign $1\wr_detect$13[0:0]$11670 1'0 + assign $1\wr_detect$13[0:0]$11654 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11669 + update \wr_detect$13 $0\wr_detect$13[0:0]$11653 end - connect \$9 $not$libresoc.v:182068$11576_Y - connect \$12 $not$libresoc.v:182069$11577_Y - connect \$15 $not$libresoc.v:182070$11578_Y - connect \$1 $not$libresoc.v:182071$11579_Y - connect \$3 $not$libresoc.v:182072$11580_Y - connect \$6 $not$libresoc.v:182073$11581_Y + connect \$9 $not$libresoc.v:183376$11560_Y + connect \$12 $not$libresoc.v:183377$11561_Y + connect \$15 $not$libresoc.v:183378$11562_Y + connect \$1 $not$libresoc.v:183379$11563_Y + connect \$3 $not$libresoc.v:183380$11564_Y + connect \$6 $not$libresoc.v:183381$11565_Y end -attribute \src "libresoc.v:182539.1-183094.10" +attribute \src "libresoc.v:183847.1-184402.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_6" attribute \generator "nMigen" module \reg_6 - attribute \src "libresoc.v:182647.3-182686.6" - wire width 4 $0\cr_pred6__data_o$next[3:0]$11696 - attribute \src "libresoc.v:182645.3-182646.49" + attribute \src "libresoc.v:183955.3-183994.6" + wire width 4 $0\cr_pred6__data_o$next[3:0]$11680 + attribute \src "libresoc.v:183953.3-183954.49" wire width 4 $0\cr_pred6__data_o[3:0] - attribute \src "libresoc.v:182540.7-182540.20" + attribute \src "libresoc.v:183848.7-183848.20" wire $0\initial[0:0] - attribute \src "libresoc.v:182717.3-182756.6" - wire width 4 $0\r26__data_o$next[3:0]$11705 - attribute \src "libresoc.v:182635.3-182636.39" + attribute \src "libresoc.v:184025.3-184064.6" + wire width 4 $0\r26__data_o$next[3:0]$11689 + attribute \src "libresoc.v:183943.3-183944.39" wire width 4 $0\r26__data_o[3:0] - attribute \src "libresoc.v:183024.3-183063.6" - wire width 4 $0\r6__data_o$next[3:0]$11767 - attribute \src "libresoc.v:182637.3-182638.37" + attribute \src "libresoc.v:184332.3-184371.6" + wire width 4 $0\r6__data_o$next[3:0]$11751 + attribute \src "libresoc.v:183945.3-183946.37" wire width 4 $0\r6__data_o[3:0] - attribute \src "libresoc.v:182787.3-182813.6" - wire width 4 $0\reg$next[3:0]$11719 - attribute \src "libresoc.v:182633.3-182634.25" + attribute \src "libresoc.v:184095.3-184121.6" + wire width 4 $0\reg$next[3:0]$11703 + attribute \src "libresoc.v:183941.3-183942.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:182814.3-182853.6" - wire width 4 $0\src16__data_o$next[3:0]$11725 - attribute \src "libresoc.v:182643.3-182644.43" + attribute \src "libresoc.v:184122.3-184161.6" + wire width 4 $0\src16__data_o$next[3:0]$11709 + attribute \src "libresoc.v:183951.3-183952.43" wire width 4 $0\src16__data_o[3:0] - attribute \src "libresoc.v:182884.3-182923.6" - wire width 4 $0\src26__data_o$next[3:0]$11739 - attribute \src "libresoc.v:182641.3-182642.43" + attribute \src "libresoc.v:184192.3-184231.6" + wire width 4 $0\src26__data_o$next[3:0]$11723 + attribute \src "libresoc.v:183949.3-183950.43" wire width 4 $0\src26__data_o[3:0] - attribute \src "libresoc.v:182954.3-182993.6" - wire width 4 $0\src36__data_o$next[3:0]$11753 - attribute \src "libresoc.v:182639.3-182640.43" + attribute \src "libresoc.v:184262.3-184301.6" + wire width 4 $0\src36__data_o$next[3:0]$11737 + attribute \src "libresoc.v:183947.3-183948.43" wire width 4 $0\src36__data_o[3:0] - attribute \src "libresoc.v:182994.3-183023.6" - wire $0\wr_detect$10[0:0]$11761 - attribute \src "libresoc.v:183064.3-183093.6" - wire $0\wr_detect$13[0:0]$11775 - attribute \src "libresoc.v:182757.3-182786.6" - wire $0\wr_detect$16[0:0]$11713 - attribute \src "libresoc.v:182854.3-182883.6" - wire $0\wr_detect$4[0:0]$11733 - attribute \src "libresoc.v:182924.3-182953.6" - wire $0\wr_detect$7[0:0]$11747 - attribute \src "libresoc.v:182687.3-182716.6" + attribute \src "libresoc.v:184302.3-184331.6" + wire $0\wr_detect$10[0:0]$11745 + attribute \src "libresoc.v:184372.3-184401.6" + wire $0\wr_detect$13[0:0]$11759 + attribute \src "libresoc.v:184065.3-184094.6" + wire $0\wr_detect$16[0:0]$11697 + attribute \src "libresoc.v:184162.3-184191.6" + wire $0\wr_detect$4[0:0]$11717 + attribute \src "libresoc.v:184232.3-184261.6" + wire $0\wr_detect$7[0:0]$11731 + attribute \src "libresoc.v:183995.3-184024.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:182647.3-182686.6" - wire width 4 $1\cr_pred6__data_o$next[3:0]$11697 - attribute \src "libresoc.v:182559.13-182559.36" + attribute \src "libresoc.v:183955.3-183994.6" + wire width 4 $1\cr_pred6__data_o$next[3:0]$11681 + attribute \src "libresoc.v:183867.13-183867.36" wire width 4 $1\cr_pred6__data_o[3:0] - attribute \src "libresoc.v:182717.3-182756.6" - wire width 4 $1\r26__data_o$next[3:0]$11706 - attribute \src "libresoc.v:182574.13-182574.31" + attribute \src "libresoc.v:184025.3-184064.6" + wire width 4 $1\r26__data_o$next[3:0]$11690 + attribute \src "libresoc.v:183882.13-183882.31" wire width 4 $1\r26__data_o[3:0] - attribute \src "libresoc.v:183024.3-183063.6" - wire width 4 $1\r6__data_o$next[3:0]$11768 - attribute \src "libresoc.v:182581.13-182581.30" + attribute \src "libresoc.v:184332.3-184371.6" + wire width 4 $1\r6__data_o$next[3:0]$11752 + attribute \src "libresoc.v:183889.13-183889.30" wire width 4 $1\r6__data_o[3:0] - attribute \src "libresoc.v:182787.3-182813.6" - wire width 4 $1\reg$next[3:0]$11720 - attribute \src "libresoc.v:182587.13-182587.25" + attribute \src "libresoc.v:184095.3-184121.6" + wire width 4 $1\reg$next[3:0]$11704 + attribute \src "libresoc.v:183895.13-183895.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:182814.3-182853.6" - wire width 4 $1\src16__data_o$next[3:0]$11726 - attribute \src "libresoc.v:182592.13-182592.33" + attribute \src "libresoc.v:184122.3-184161.6" + wire width 4 $1\src16__data_o$next[3:0]$11710 + attribute \src "libresoc.v:183900.13-183900.33" wire width 4 $1\src16__data_o[3:0] - attribute \src "libresoc.v:182884.3-182923.6" - wire width 4 $1\src26__data_o$next[3:0]$11740 - attribute \src "libresoc.v:182599.13-182599.33" + attribute \src "libresoc.v:184192.3-184231.6" + wire width 4 $1\src26__data_o$next[3:0]$11724 + attribute \src "libresoc.v:183907.13-183907.33" wire width 4 $1\src26__data_o[3:0] - attribute \src "libresoc.v:182954.3-182993.6" - wire width 4 $1\src36__data_o$next[3:0]$11754 - attribute \src "libresoc.v:182606.13-182606.33" + attribute \src "libresoc.v:184262.3-184301.6" + wire width 4 $1\src36__data_o$next[3:0]$11738 + attribute \src "libresoc.v:183914.13-183914.33" wire width 4 $1\src36__data_o[3:0] - attribute \src "libresoc.v:182994.3-183023.6" - wire $1\wr_detect$10[0:0]$11762 - attribute \src "libresoc.v:183064.3-183093.6" - wire $1\wr_detect$13[0:0]$11776 - attribute \src "libresoc.v:182757.3-182786.6" - wire $1\wr_detect$16[0:0]$11714 - attribute \src "libresoc.v:182854.3-182883.6" - wire $1\wr_detect$4[0:0]$11734 - attribute \src "libresoc.v:182924.3-182953.6" - wire $1\wr_detect$7[0:0]$11748 - attribute \src "libresoc.v:182687.3-182716.6" + attribute \src "libresoc.v:184302.3-184331.6" + wire $1\wr_detect$10[0:0]$11746 + attribute \src "libresoc.v:184372.3-184401.6" + wire $1\wr_detect$13[0:0]$11760 + attribute \src "libresoc.v:184065.3-184094.6" + wire $1\wr_detect$16[0:0]$11698 + attribute \src "libresoc.v:184162.3-184191.6" + wire $1\wr_detect$4[0:0]$11718 + attribute \src "libresoc.v:184232.3-184261.6" + wire $1\wr_detect$7[0:0]$11732 + attribute \src "libresoc.v:183995.3-184024.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:182647.3-182686.6" - wire width 4 $2\cr_pred6__data_o$next[3:0]$11698 - attribute \src "libresoc.v:182717.3-182756.6" - wire width 4 $2\r26__data_o$next[3:0]$11707 - attribute \src "libresoc.v:183024.3-183063.6" - wire width 4 $2\r6__data_o$next[3:0]$11769 - attribute \src "libresoc.v:182787.3-182813.6" - wire width 4 $2\reg$next[3:0]$11721 - attribute \src "libresoc.v:182814.3-182853.6" - wire width 4 $2\src16__data_o$next[3:0]$11727 - attribute \src "libresoc.v:182884.3-182923.6" - wire width 4 $2\src26__data_o$next[3:0]$11741 - attribute \src "libresoc.v:182954.3-182993.6" - wire width 4 $2\src36__data_o$next[3:0]$11755 - attribute \src "libresoc.v:182994.3-183023.6" - wire $2\wr_detect$10[0:0]$11763 - attribute \src "libresoc.v:183064.3-183093.6" - wire $2\wr_detect$13[0:0]$11777 - attribute \src "libresoc.v:182757.3-182786.6" - wire $2\wr_detect$16[0:0]$11715 - attribute \src "libresoc.v:182854.3-182883.6" - wire $2\wr_detect$4[0:0]$11735 - attribute \src "libresoc.v:182924.3-182953.6" - wire $2\wr_detect$7[0:0]$11749 - attribute \src "libresoc.v:182687.3-182716.6" + attribute \src "libresoc.v:183955.3-183994.6" + wire width 4 $2\cr_pred6__data_o$next[3:0]$11682 + attribute \src "libresoc.v:184025.3-184064.6" + wire width 4 $2\r26__data_o$next[3:0]$11691 + attribute \src "libresoc.v:184332.3-184371.6" + wire width 4 $2\r6__data_o$next[3:0]$11753 + attribute \src "libresoc.v:184095.3-184121.6" + wire width 4 $2\reg$next[3:0]$11705 + attribute \src "libresoc.v:184122.3-184161.6" + wire width 4 $2\src16__data_o$next[3:0]$11711 + attribute \src "libresoc.v:184192.3-184231.6" + wire width 4 $2\src26__data_o$next[3:0]$11725 + attribute \src "libresoc.v:184262.3-184301.6" + wire width 4 $2\src36__data_o$next[3:0]$11739 + attribute \src "libresoc.v:184302.3-184331.6" + wire $2\wr_detect$10[0:0]$11747 + attribute \src "libresoc.v:184372.3-184401.6" + wire $2\wr_detect$13[0:0]$11761 + attribute \src "libresoc.v:184065.3-184094.6" + wire $2\wr_detect$16[0:0]$11699 + attribute \src "libresoc.v:184162.3-184191.6" + wire $2\wr_detect$4[0:0]$11719 + attribute \src "libresoc.v:184232.3-184261.6" + wire $2\wr_detect$7[0:0]$11733 + attribute \src "libresoc.v:183995.3-184024.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:182647.3-182686.6" - wire width 4 $3\cr_pred6__data_o$next[3:0]$11699 - attribute \src "libresoc.v:182717.3-182756.6" - wire width 4 $3\r26__data_o$next[3:0]$11708 - attribute \src "libresoc.v:183024.3-183063.6" - wire width 4 $3\r6__data_o$next[3:0]$11770 - attribute \src "libresoc.v:182787.3-182813.6" - wire width 4 $3\reg$next[3:0]$11722 - attribute \src "libresoc.v:182814.3-182853.6" - wire width 4 $3\src16__data_o$next[3:0]$11728 - attribute \src "libresoc.v:182884.3-182923.6" - wire width 4 $3\src26__data_o$next[3:0]$11742 - attribute \src "libresoc.v:182954.3-182993.6" - wire width 4 $3\src36__data_o$next[3:0]$11756 - attribute \src "libresoc.v:182994.3-183023.6" - wire $3\wr_detect$10[0:0]$11764 - attribute \src "libresoc.v:183064.3-183093.6" - wire $3\wr_detect$13[0:0]$11778 - attribute \src "libresoc.v:182757.3-182786.6" - wire $3\wr_detect$16[0:0]$11716 - attribute \src "libresoc.v:182854.3-182883.6" - wire $3\wr_detect$4[0:0]$11736 - attribute \src "libresoc.v:182924.3-182953.6" - wire $3\wr_detect$7[0:0]$11750 - attribute \src "libresoc.v:182687.3-182716.6" + attribute \src "libresoc.v:183955.3-183994.6" + wire width 4 $3\cr_pred6__data_o$next[3:0]$11683 + attribute \src "libresoc.v:184025.3-184064.6" + wire width 4 $3\r26__data_o$next[3:0]$11692 + attribute \src "libresoc.v:184332.3-184371.6" + wire width 4 $3\r6__data_o$next[3:0]$11754 + attribute \src "libresoc.v:184095.3-184121.6" + wire width 4 $3\reg$next[3:0]$11706 + attribute \src "libresoc.v:184122.3-184161.6" + wire width 4 $3\src16__data_o$next[3:0]$11712 + attribute \src "libresoc.v:184192.3-184231.6" + wire width 4 $3\src26__data_o$next[3:0]$11726 + attribute \src "libresoc.v:184262.3-184301.6" + wire width 4 $3\src36__data_o$next[3:0]$11740 + attribute \src "libresoc.v:184302.3-184331.6" + wire $3\wr_detect$10[0:0]$11748 + attribute \src "libresoc.v:184372.3-184401.6" + wire $3\wr_detect$13[0:0]$11762 + attribute \src "libresoc.v:184065.3-184094.6" + wire $3\wr_detect$16[0:0]$11700 + attribute \src "libresoc.v:184162.3-184191.6" + wire $3\wr_detect$4[0:0]$11720 + attribute \src "libresoc.v:184232.3-184261.6" + wire $3\wr_detect$7[0:0]$11734 + attribute \src "libresoc.v:183995.3-184024.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:182647.3-182686.6" - wire width 4 $4\cr_pred6__data_o$next[3:0]$11700 - attribute \src "libresoc.v:182717.3-182756.6" - wire width 4 $4\r26__data_o$next[3:0]$11709 - attribute \src "libresoc.v:183024.3-183063.6" - wire width 4 $4\r6__data_o$next[3:0]$11771 - attribute \src "libresoc.v:182787.3-182813.6" - wire width 4 $4\reg$next[3:0]$11723 - attribute \src "libresoc.v:182814.3-182853.6" - wire width 4 $4\src16__data_o$next[3:0]$11729 - attribute \src "libresoc.v:182884.3-182923.6" - wire width 4 $4\src26__data_o$next[3:0]$11743 - attribute \src "libresoc.v:182954.3-182993.6" - wire width 4 $4\src36__data_o$next[3:0]$11757 - attribute \src "libresoc.v:182994.3-183023.6" - wire $4\wr_detect$10[0:0]$11765 - attribute \src "libresoc.v:183064.3-183093.6" - wire $4\wr_detect$13[0:0]$11779 - attribute \src "libresoc.v:182757.3-182786.6" - wire $4\wr_detect$16[0:0]$11717 - attribute \src "libresoc.v:182854.3-182883.6" - wire $4\wr_detect$4[0:0]$11737 - attribute \src "libresoc.v:182924.3-182953.6" - wire $4\wr_detect$7[0:0]$11751 - attribute \src "libresoc.v:182687.3-182716.6" + attribute \src "libresoc.v:183955.3-183994.6" + wire width 4 $4\cr_pred6__data_o$next[3:0]$11684 + attribute \src "libresoc.v:184025.3-184064.6" + wire width 4 $4\r26__data_o$next[3:0]$11693 + attribute \src "libresoc.v:184332.3-184371.6" + wire width 4 $4\r6__data_o$next[3:0]$11755 + attribute \src "libresoc.v:184095.3-184121.6" + wire width 4 $4\reg$next[3:0]$11707 + attribute \src "libresoc.v:184122.3-184161.6" + wire width 4 $4\src16__data_o$next[3:0]$11713 + attribute \src "libresoc.v:184192.3-184231.6" + wire width 4 $4\src26__data_o$next[3:0]$11727 + attribute \src "libresoc.v:184262.3-184301.6" + wire width 4 $4\src36__data_o$next[3:0]$11741 + attribute \src "libresoc.v:184302.3-184331.6" + wire $4\wr_detect$10[0:0]$11749 + attribute \src "libresoc.v:184372.3-184401.6" + wire $4\wr_detect$13[0:0]$11763 + attribute \src "libresoc.v:184065.3-184094.6" + wire $4\wr_detect$16[0:0]$11701 + attribute \src "libresoc.v:184162.3-184191.6" + wire $4\wr_detect$4[0:0]$11721 + attribute \src "libresoc.v:184232.3-184261.6" + wire $4\wr_detect$7[0:0]$11735 + attribute \src "libresoc.v:183995.3-184024.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:182647.3-182686.6" - wire width 4 $5\cr_pred6__data_o$next[3:0]$11701 - attribute \src "libresoc.v:182717.3-182756.6" - wire width 4 $5\r26__data_o$next[3:0]$11710 - attribute \src "libresoc.v:183024.3-183063.6" - wire width 4 $5\r6__data_o$next[3:0]$11772 - attribute \src "libresoc.v:182814.3-182853.6" - wire width 4 $5\src16__data_o$next[3:0]$11730 - attribute \src "libresoc.v:182884.3-182923.6" - wire width 4 $5\src26__data_o$next[3:0]$11744 - attribute \src "libresoc.v:182954.3-182993.6" - wire width 4 $5\src36__data_o$next[3:0]$11758 - attribute \src "libresoc.v:182647.3-182686.6" - wire width 4 $6\cr_pred6__data_o$next[3:0]$11702 - attribute \src "libresoc.v:182717.3-182756.6" - wire width 4 $6\r26__data_o$next[3:0]$11711 - attribute \src "libresoc.v:183024.3-183063.6" - wire width 4 $6\r6__data_o$next[3:0]$11773 - attribute \src "libresoc.v:182814.3-182853.6" - wire width 4 $6\src16__data_o$next[3:0]$11731 - attribute \src "libresoc.v:182884.3-182923.6" - wire width 4 $6\src26__data_o$next[3:0]$11745 - attribute \src "libresoc.v:182954.3-182993.6" - wire width 4 $6\src36__data_o$next[3:0]$11759 - attribute \src "libresoc.v:182627.17-182627.104" - wire $not$libresoc.v:182627$11682_Y - attribute \src "libresoc.v:182628.18-182628.105" - wire $not$libresoc.v:182628$11683_Y - attribute \src "libresoc.v:182629.18-182629.105" - wire $not$libresoc.v:182629$11684_Y - attribute \src "libresoc.v:182630.17-182630.100" - wire $not$libresoc.v:182630$11685_Y - attribute \src "libresoc.v:182631.17-182631.103" - wire $not$libresoc.v:182631$11686_Y - attribute \src "libresoc.v:182632.17-182632.103" - wire $not$libresoc.v:182632$11687_Y + attribute \src "libresoc.v:183955.3-183994.6" + wire width 4 $5\cr_pred6__data_o$next[3:0]$11685 + attribute \src "libresoc.v:184025.3-184064.6" + wire width 4 $5\r26__data_o$next[3:0]$11694 + attribute \src "libresoc.v:184332.3-184371.6" + wire width 4 $5\r6__data_o$next[3:0]$11756 + attribute \src "libresoc.v:184122.3-184161.6" + wire width 4 $5\src16__data_o$next[3:0]$11714 + attribute \src "libresoc.v:184192.3-184231.6" + wire width 4 $5\src26__data_o$next[3:0]$11728 + attribute \src "libresoc.v:184262.3-184301.6" + wire width 4 $5\src36__data_o$next[3:0]$11742 + attribute \src "libresoc.v:183955.3-183994.6" + wire width 4 $6\cr_pred6__data_o$next[3:0]$11686 + attribute \src "libresoc.v:184025.3-184064.6" + wire width 4 $6\r26__data_o$next[3:0]$11695 + attribute \src "libresoc.v:184332.3-184371.6" + wire width 4 $6\r6__data_o$next[3:0]$11757 + attribute \src "libresoc.v:184122.3-184161.6" + wire width 4 $6\src16__data_o$next[3:0]$11715 + attribute \src "libresoc.v:184192.3-184231.6" + wire width 4 $6\src26__data_o$next[3:0]$11729 + attribute \src "libresoc.v:184262.3-184301.6" + wire width 4 $6\src36__data_o$next[3:0]$11743 + attribute \src "libresoc.v:183935.17-183935.104" + wire $not$libresoc.v:183935$11666_Y + attribute \src "libresoc.v:183936.18-183936.105" + wire $not$libresoc.v:183936$11667_Y + attribute \src "libresoc.v:183937.18-183937.105" + wire $not$libresoc.v:183937$11668_Y + attribute \src "libresoc.v:183938.17-183938.100" + wire $not$libresoc.v:183938$11669_Y + attribute \src "libresoc.v:183939.17-183939.103" + wire $not$libresoc.v:183939$11670_Y + attribute \src "libresoc.v:183940.17-183940.103" + wire $not$libresoc.v:183940$11671_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -372686,9 +344056,9 @@ module \reg_6 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 20 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 3 \cr_pred6__data_o @@ -372704,7 +344074,7 @@ module \reg_6 wire width 4 input 13 \dest26__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest26__wen - attribute \src "libresoc.v:182540.7-182540.15" + attribute \src "libresoc.v:183848.7-183848.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 16 \r26__data_o @@ -372757,175 +344127,175 @@ module \reg_6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182627$11682 + cell $not $not$libresoc.v:183935$11666 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:182627$11682_Y + connect \Y $not$libresoc.v:183935$11666_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182628$11683 + cell $not $not$libresoc.v:183936$11667 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:182628$11683_Y + connect \Y $not$libresoc.v:183936$11667_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182629$11684 + cell $not $not$libresoc.v:183937$11668 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$16 - connect \Y $not$libresoc.v:182629$11684_Y + connect \Y $not$libresoc.v:183937$11668_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182630$11685 + cell $not $not$libresoc.v:183938$11669 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:182630$11685_Y + connect \Y $not$libresoc.v:183938$11669_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182631$11686 + cell $not $not$libresoc.v:183939$11670 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:182631$11686_Y + connect \Y $not$libresoc.v:183939$11670_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:182632$11687 + cell $not $not$libresoc.v:183940$11671 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:182632$11687_Y + connect \Y $not$libresoc.v:183940$11671_Y end - attribute \src "libresoc.v:182540.7-182540.20" - process $proc$libresoc.v:182540$11780 + attribute \src "libresoc.v:183848.7-183848.20" + process $proc$libresoc.v:183848$11764 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:182559.13-182559.36" - process $proc$libresoc.v:182559$11781 + attribute \src "libresoc.v:183867.13-183867.36" + process $proc$libresoc.v:183867$11765 assign { } { } assign $1\cr_pred6__data_o[3:0] 4'0000 sync always sync init update \cr_pred6__data_o $1\cr_pred6__data_o[3:0] end - attribute \src "libresoc.v:182574.13-182574.31" - process $proc$libresoc.v:182574$11782 + attribute \src "libresoc.v:183882.13-183882.31" + process $proc$libresoc.v:183882$11766 assign { } { } assign $1\r26__data_o[3:0] 4'0000 sync always sync init update \r26__data_o $1\r26__data_o[3:0] end - attribute \src "libresoc.v:182581.13-182581.30" - process $proc$libresoc.v:182581$11783 + attribute \src "libresoc.v:183889.13-183889.30" + process $proc$libresoc.v:183889$11767 assign { } { } assign $1\r6__data_o[3:0] 4'0000 sync always sync init update \r6__data_o $1\r6__data_o[3:0] end - attribute \src "libresoc.v:182587.13-182587.25" - process $proc$libresoc.v:182587$11784 + attribute \src "libresoc.v:183895.13-183895.25" + process $proc$libresoc.v:183895$11768 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:182592.13-182592.33" - process $proc$libresoc.v:182592$11785 + attribute \src "libresoc.v:183900.13-183900.33" + process $proc$libresoc.v:183900$11769 assign { } { } assign $1\src16__data_o[3:0] 4'0000 sync always sync init update \src16__data_o $1\src16__data_o[3:0] end - attribute \src "libresoc.v:182599.13-182599.33" - process $proc$libresoc.v:182599$11786 + attribute \src "libresoc.v:183907.13-183907.33" + process $proc$libresoc.v:183907$11770 assign { } { } assign $1\src26__data_o[3:0] 4'0000 sync always sync init update \src26__data_o $1\src26__data_o[3:0] end - attribute \src "libresoc.v:182606.13-182606.33" - process $proc$libresoc.v:182606$11787 + attribute \src "libresoc.v:183914.13-183914.33" + process $proc$libresoc.v:183914$11771 assign { } { } assign $1\src36__data_o[3:0] 4'0000 sync always sync init update \src36__data_o $1\src36__data_o[3:0] end - attribute \src "libresoc.v:182633.3-182634.25" - process $proc$libresoc.v:182633$11688 + attribute \src "libresoc.v:183941.3-183942.25" + process $proc$libresoc.v:183941$11672 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:182635.3-182636.39" - process $proc$libresoc.v:182635$11689 + attribute \src "libresoc.v:183943.3-183944.39" + process $proc$libresoc.v:183943$11673 assign { } { } assign $0\r26__data_o[3:0] \r26__data_o$next sync posedge \coresync_clk update \r26__data_o $0\r26__data_o[3:0] end - attribute \src "libresoc.v:182637.3-182638.37" - process $proc$libresoc.v:182637$11690 + attribute \src "libresoc.v:183945.3-183946.37" + process $proc$libresoc.v:183945$11674 assign { } { } assign $0\r6__data_o[3:0] \r6__data_o$next sync posedge \coresync_clk update \r6__data_o $0\r6__data_o[3:0] end - attribute \src "libresoc.v:182639.3-182640.43" - process $proc$libresoc.v:182639$11691 + attribute \src "libresoc.v:183947.3-183948.43" + process $proc$libresoc.v:183947$11675 assign { } { } assign $0\src36__data_o[3:0] \src36__data_o$next sync posedge \coresync_clk update \src36__data_o $0\src36__data_o[3:0] end - attribute \src "libresoc.v:182641.3-182642.43" - process $proc$libresoc.v:182641$11692 + attribute \src "libresoc.v:183949.3-183950.43" + process $proc$libresoc.v:183949$11676 assign { } { } assign $0\src26__data_o[3:0] \src26__data_o$next sync posedge \coresync_clk update \src26__data_o $0\src26__data_o[3:0] end - attribute \src "libresoc.v:182643.3-182644.43" - process $proc$libresoc.v:182643$11693 + attribute \src "libresoc.v:183951.3-183952.43" + process $proc$libresoc.v:183951$11677 assign { } { } assign $0\src16__data_o[3:0] \src16__data_o$next sync posedge \coresync_clk update \src16__data_o $0\src16__data_o[3:0] end - attribute \src "libresoc.v:182645.3-182646.49" - process $proc$libresoc.v:182645$11694 + attribute \src "libresoc.v:183953.3-183954.49" + process $proc$libresoc.v:183953$11678 assign { } { } assign $0\cr_pred6__data_o[3:0] \cr_pred6__data_o$next sync posedge \coresync_clk update \cr_pred6__data_o $0\cr_pred6__data_o[3:0] end - attribute \src "libresoc.v:182647.3-182686.6" - process $proc$libresoc.v:182647$11695 + attribute \src "libresoc.v:183955.3-183994.6" + process $proc$libresoc.v:183955$11679 assign { } { } assign { } { } assign { } { } - assign $0\cr_pred6__data_o$next[3:0]$11696 $6\cr_pred6__data_o$next[3:0]$11702 - attribute \src "libresoc.v:182648.5-182648.29" + assign $0\cr_pred6__data_o$next[3:0]$11680 $6\cr_pred6__data_o$next[3:0]$11686 + attribute \src "libresoc.v:183956.5-183956.29" switch \initial - attribute \src "libresoc.v:182648.9-182648.17" + attribute \src "libresoc.v:183956.9-183956.17" case 1'1 case end @@ -372937,66 +344307,66 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\cr_pred6__data_o$next[3:0]$11697 $5\cr_pred6__data_o$next[3:0]$11701 + assign $1\cr_pred6__data_o$next[3:0]$11681 $5\cr_pred6__data_o$next[3:0]$11685 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_pred6__data_o$next[3:0]$11698 \dest16__data_i + assign $2\cr_pred6__data_o$next[3:0]$11682 \dest16__data_i case - assign $2\cr_pred6__data_o$next[3:0]$11698 4'0000 + assign $2\cr_pred6__data_o$next[3:0]$11682 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\cr_pred6__data_o$next[3:0]$11699 \dest26__data_i + assign $3\cr_pred6__data_o$next[3:0]$11683 \dest26__data_i case - assign $3\cr_pred6__data_o$next[3:0]$11699 $2\cr_pred6__data_o$next[3:0]$11698 + assign $3\cr_pred6__data_o$next[3:0]$11683 $2\cr_pred6__data_o$next[3:0]$11682 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cr_pred6__data_o$next[3:0]$11700 \w6__data_i + assign $4\cr_pred6__data_o$next[3:0]$11684 \w6__data_i case - assign $4\cr_pred6__data_o$next[3:0]$11700 $3\cr_pred6__data_o$next[3:0]$11699 + assign $4\cr_pred6__data_o$next[3:0]$11684 $3\cr_pred6__data_o$next[3:0]$11683 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\cr_pred6__data_o$next[3:0]$11701 \reg + assign $5\cr_pred6__data_o$next[3:0]$11685 \reg case - assign $5\cr_pred6__data_o$next[3:0]$11701 $4\cr_pred6__data_o$next[3:0]$11700 + assign $5\cr_pred6__data_o$next[3:0]$11685 $4\cr_pred6__data_o$next[3:0]$11684 end case - assign $1\cr_pred6__data_o$next[3:0]$11697 4'0000 + assign $1\cr_pred6__data_o$next[3:0]$11681 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cr_pred6__data_o$next[3:0]$11702 4'0000 + assign $6\cr_pred6__data_o$next[3:0]$11686 4'0000 case - assign $6\cr_pred6__data_o$next[3:0]$11702 $1\cr_pred6__data_o$next[3:0]$11697 + assign $6\cr_pred6__data_o$next[3:0]$11686 $1\cr_pred6__data_o$next[3:0]$11681 end sync always - update \cr_pred6__data_o$next $0\cr_pred6__data_o$next[3:0]$11696 + update \cr_pred6__data_o$next $0\cr_pred6__data_o$next[3:0]$11680 end - attribute \src "libresoc.v:182687.3-182716.6" - process $proc$libresoc.v:182687$11703 + attribute \src "libresoc.v:183995.3-184024.6" + process $proc$libresoc.v:183995$11687 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:182688.5-182688.29" + attribute \src "libresoc.v:183996.5-183996.29" switch \initial - attribute \src "libresoc.v:182688.9-182688.17" + attribute \src "libresoc.v:183996.9-183996.17" case 1'1 case end @@ -373042,15 +344412,15 @@ module \reg_6 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:182717.3-182756.6" - process $proc$libresoc.v:182717$11704 + attribute \src "libresoc.v:184025.3-184064.6" + process $proc$libresoc.v:184025$11688 assign { } { } assign { } { } assign { } { } - assign $0\r26__data_o$next[3:0]$11705 $6\r26__data_o$next[3:0]$11711 - attribute \src "libresoc.v:182718.5-182718.29" + assign $0\r26__data_o$next[3:0]$11689 $6\r26__data_o$next[3:0]$11695 + attribute \src "libresoc.v:184026.5-184026.29" switch \initial - attribute \src "libresoc.v:182718.9-182718.17" + attribute \src "libresoc.v:184026.9-184026.17" case 1'1 case end @@ -373062,66 +344432,66 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\r26__data_o$next[3:0]$11706 $5\r26__data_o$next[3:0]$11710 + assign $1\r26__data_o$next[3:0]$11690 $5\r26__data_o$next[3:0]$11694 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r26__data_o$next[3:0]$11707 \dest16__data_i + assign $2\r26__data_o$next[3:0]$11691 \dest16__data_i case - assign $2\r26__data_o$next[3:0]$11707 4'0000 + assign $2\r26__data_o$next[3:0]$11691 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r26__data_o$next[3:0]$11708 \dest26__data_i + assign $3\r26__data_o$next[3:0]$11692 \dest26__data_i case - assign $3\r26__data_o$next[3:0]$11708 $2\r26__data_o$next[3:0]$11707 + assign $3\r26__data_o$next[3:0]$11692 $2\r26__data_o$next[3:0]$11691 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r26__data_o$next[3:0]$11709 \w6__data_i + assign $4\r26__data_o$next[3:0]$11693 \w6__data_i case - assign $4\r26__data_o$next[3:0]$11709 $3\r26__data_o$next[3:0]$11708 + assign $4\r26__data_o$next[3:0]$11693 $3\r26__data_o$next[3:0]$11692 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$15 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r26__data_o$next[3:0]$11710 \reg + assign $5\r26__data_o$next[3:0]$11694 \reg case - assign $5\r26__data_o$next[3:0]$11710 $4\r26__data_o$next[3:0]$11709 + assign $5\r26__data_o$next[3:0]$11694 $4\r26__data_o$next[3:0]$11693 end case - assign $1\r26__data_o$next[3:0]$11706 4'0000 + assign $1\r26__data_o$next[3:0]$11690 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r26__data_o$next[3:0]$11711 4'0000 + assign $6\r26__data_o$next[3:0]$11695 4'0000 case - assign $6\r26__data_o$next[3:0]$11711 $1\r26__data_o$next[3:0]$11706 + assign $6\r26__data_o$next[3:0]$11695 $1\r26__data_o$next[3:0]$11690 end sync always - update \r26__data_o$next $0\r26__data_o$next[3:0]$11705 + update \r26__data_o$next $0\r26__data_o$next[3:0]$11689 end - attribute \src "libresoc.v:182757.3-182786.6" - process $proc$libresoc.v:182757$11712 + attribute \src "libresoc.v:184065.3-184094.6" + process $proc$libresoc.v:184065$11696 assign { } { } assign { } { } - assign $0\wr_detect$16[0:0]$11713 $1\wr_detect$16[0:0]$11714 - attribute \src "libresoc.v:182758.5-182758.29" + assign $0\wr_detect$16[0:0]$11697 $1\wr_detect$16[0:0]$11698 + attribute \src "libresoc.v:184066.5-184066.29" switch \initial - attribute \src "libresoc.v:182758.9-182758.17" + attribute \src "libresoc.v:184066.9-184066.17" case 1'1 case end @@ -373133,51 +344503,51 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$16[0:0]$11714 $4\wr_detect$16[0:0]$11717 + assign $1\wr_detect$16[0:0]$11698 $4\wr_detect$16[0:0]$11701 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$16[0:0]$11715 1'1 + assign $2\wr_detect$16[0:0]$11699 1'1 case - assign $2\wr_detect$16[0:0]$11715 1'0 + assign $2\wr_detect$16[0:0]$11699 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$16[0:0]$11716 1'1 + assign $3\wr_detect$16[0:0]$11700 1'1 case - assign $3\wr_detect$16[0:0]$11716 $2\wr_detect$16[0:0]$11715 + assign $3\wr_detect$16[0:0]$11700 $2\wr_detect$16[0:0]$11699 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$16[0:0]$11717 1'1 + assign $4\wr_detect$16[0:0]$11701 1'1 case - assign $4\wr_detect$16[0:0]$11717 $3\wr_detect$16[0:0]$11716 + assign $4\wr_detect$16[0:0]$11701 $3\wr_detect$16[0:0]$11700 end case - assign $1\wr_detect$16[0:0]$11714 1'0 + assign $1\wr_detect$16[0:0]$11698 1'0 end sync always - update \wr_detect$16 $0\wr_detect$16[0:0]$11713 + update \wr_detect$16 $0\wr_detect$16[0:0]$11697 end - attribute \src "libresoc.v:182787.3-182813.6" - process $proc$libresoc.v:182787$11718 + attribute \src "libresoc.v:184095.3-184121.6" + process $proc$libresoc.v:184095$11702 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11719 $4\reg$next[3:0]$11723 - attribute \src "libresoc.v:182788.5-182788.29" + assign $0\reg$next[3:0]$11703 $4\reg$next[3:0]$11707 + attribute \src "libresoc.v:184096.5-184096.29" switch \initial - attribute \src "libresoc.v:182788.9-182788.17" + attribute \src "libresoc.v:184096.9-184096.17" case 1'1 case end @@ -373186,49 +344556,49 @@ module \reg_6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11720 \dest16__data_i + assign $1\reg$next[3:0]$11704 \dest16__data_i case - assign $1\reg$next[3:0]$11720 \reg + assign $1\reg$next[3:0]$11704 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11721 \dest26__data_i + assign $2\reg$next[3:0]$11705 \dest26__data_i case - assign $2\reg$next[3:0]$11721 $1\reg$next[3:0]$11720 + assign $2\reg$next[3:0]$11705 $1\reg$next[3:0]$11704 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11722 \w6__data_i + assign $3\reg$next[3:0]$11706 \w6__data_i case - assign $3\reg$next[3:0]$11722 $2\reg$next[3:0]$11721 + assign $3\reg$next[3:0]$11706 $2\reg$next[3:0]$11705 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11723 4'0000 + assign $4\reg$next[3:0]$11707 4'0000 case - assign $4\reg$next[3:0]$11723 $3\reg$next[3:0]$11722 + assign $4\reg$next[3:0]$11707 $3\reg$next[3:0]$11706 end sync always - update \reg$next $0\reg$next[3:0]$11719 + update \reg$next $0\reg$next[3:0]$11703 end - attribute \src "libresoc.v:182814.3-182853.6" - process $proc$libresoc.v:182814$11724 + attribute \src "libresoc.v:184122.3-184161.6" + process $proc$libresoc.v:184122$11708 assign { } { } assign { } { } assign { } { } - assign $0\src16__data_o$next[3:0]$11725 $6\src16__data_o$next[3:0]$11731 - attribute \src "libresoc.v:182815.5-182815.29" + assign $0\src16__data_o$next[3:0]$11709 $6\src16__data_o$next[3:0]$11715 + attribute \src "libresoc.v:184123.5-184123.29" switch \initial - attribute \src "libresoc.v:182815.9-182815.17" + attribute \src "libresoc.v:184123.9-184123.17" case 1'1 case end @@ -373240,66 +344610,66 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\src16__data_o$next[3:0]$11726 $5\src16__data_o$next[3:0]$11730 + assign $1\src16__data_o$next[3:0]$11710 $5\src16__data_o$next[3:0]$11714 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src16__data_o$next[3:0]$11727 \dest16__data_i + assign $2\src16__data_o$next[3:0]$11711 \dest16__data_i case - assign $2\src16__data_o$next[3:0]$11727 4'0000 + assign $2\src16__data_o$next[3:0]$11711 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src16__data_o$next[3:0]$11728 \dest26__data_i + assign $3\src16__data_o$next[3:0]$11712 \dest26__data_i case - assign $3\src16__data_o$next[3:0]$11728 $2\src16__data_o$next[3:0]$11727 + assign $3\src16__data_o$next[3:0]$11712 $2\src16__data_o$next[3:0]$11711 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src16__data_o$next[3:0]$11729 \w6__data_i + assign $4\src16__data_o$next[3:0]$11713 \w6__data_i case - assign $4\src16__data_o$next[3:0]$11729 $3\src16__data_o$next[3:0]$11728 + assign $4\src16__data_o$next[3:0]$11713 $3\src16__data_o$next[3:0]$11712 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src16__data_o$next[3:0]$11730 \reg + assign $5\src16__data_o$next[3:0]$11714 \reg case - assign $5\src16__data_o$next[3:0]$11730 $4\src16__data_o$next[3:0]$11729 + assign $5\src16__data_o$next[3:0]$11714 $4\src16__data_o$next[3:0]$11713 end case - assign $1\src16__data_o$next[3:0]$11726 4'0000 + assign $1\src16__data_o$next[3:0]$11710 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src16__data_o$next[3:0]$11731 4'0000 + assign $6\src16__data_o$next[3:0]$11715 4'0000 case - assign $6\src16__data_o$next[3:0]$11731 $1\src16__data_o$next[3:0]$11726 + assign $6\src16__data_o$next[3:0]$11715 $1\src16__data_o$next[3:0]$11710 end sync always - update \src16__data_o$next $0\src16__data_o$next[3:0]$11725 + update \src16__data_o$next $0\src16__data_o$next[3:0]$11709 end - attribute \src "libresoc.v:182854.3-182883.6" - process $proc$libresoc.v:182854$11732 + attribute \src "libresoc.v:184162.3-184191.6" + process $proc$libresoc.v:184162$11716 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11733 $1\wr_detect$4[0:0]$11734 - attribute \src "libresoc.v:182855.5-182855.29" + assign $0\wr_detect$4[0:0]$11717 $1\wr_detect$4[0:0]$11718 + attribute \src "libresoc.v:184163.5-184163.29" switch \initial - attribute \src "libresoc.v:182855.9-182855.17" + attribute \src "libresoc.v:184163.9-184163.17" case 1'1 case end @@ -373311,49 +344681,49 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11734 $4\wr_detect$4[0:0]$11737 + assign $1\wr_detect$4[0:0]$11718 $4\wr_detect$4[0:0]$11721 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11735 1'1 + assign $2\wr_detect$4[0:0]$11719 1'1 case - assign $2\wr_detect$4[0:0]$11735 1'0 + assign $2\wr_detect$4[0:0]$11719 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11736 1'1 + assign $3\wr_detect$4[0:0]$11720 1'1 case - assign $3\wr_detect$4[0:0]$11736 $2\wr_detect$4[0:0]$11735 + assign $3\wr_detect$4[0:0]$11720 $2\wr_detect$4[0:0]$11719 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11737 1'1 + assign $4\wr_detect$4[0:0]$11721 1'1 case - assign $4\wr_detect$4[0:0]$11737 $3\wr_detect$4[0:0]$11736 + assign $4\wr_detect$4[0:0]$11721 $3\wr_detect$4[0:0]$11720 end case - assign $1\wr_detect$4[0:0]$11734 1'0 + assign $1\wr_detect$4[0:0]$11718 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11733 + update \wr_detect$4 $0\wr_detect$4[0:0]$11717 end - attribute \src "libresoc.v:182884.3-182923.6" - process $proc$libresoc.v:182884$11738 + attribute \src "libresoc.v:184192.3-184231.6" + process $proc$libresoc.v:184192$11722 assign { } { } assign { } { } assign { } { } - assign $0\src26__data_o$next[3:0]$11739 $6\src26__data_o$next[3:0]$11745 - attribute \src "libresoc.v:182885.5-182885.29" + assign $0\src26__data_o$next[3:0]$11723 $6\src26__data_o$next[3:0]$11729 + attribute \src "libresoc.v:184193.5-184193.29" switch \initial - attribute \src "libresoc.v:182885.9-182885.17" + attribute \src "libresoc.v:184193.9-184193.17" case 1'1 case end @@ -373365,66 +344735,66 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\src26__data_o$next[3:0]$11740 $5\src26__data_o$next[3:0]$11744 + assign $1\src26__data_o$next[3:0]$11724 $5\src26__data_o$next[3:0]$11728 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src26__data_o$next[3:0]$11741 \dest16__data_i + assign $2\src26__data_o$next[3:0]$11725 \dest16__data_i case - assign $2\src26__data_o$next[3:0]$11741 4'0000 + assign $2\src26__data_o$next[3:0]$11725 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src26__data_o$next[3:0]$11742 \dest26__data_i + assign $3\src26__data_o$next[3:0]$11726 \dest26__data_i case - assign $3\src26__data_o$next[3:0]$11742 $2\src26__data_o$next[3:0]$11741 + assign $3\src26__data_o$next[3:0]$11726 $2\src26__data_o$next[3:0]$11725 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src26__data_o$next[3:0]$11743 \w6__data_i + assign $4\src26__data_o$next[3:0]$11727 \w6__data_i case - assign $4\src26__data_o$next[3:0]$11743 $3\src26__data_o$next[3:0]$11742 + assign $4\src26__data_o$next[3:0]$11727 $3\src26__data_o$next[3:0]$11726 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src26__data_o$next[3:0]$11744 \reg + assign $5\src26__data_o$next[3:0]$11728 \reg case - assign $5\src26__data_o$next[3:0]$11744 $4\src26__data_o$next[3:0]$11743 + assign $5\src26__data_o$next[3:0]$11728 $4\src26__data_o$next[3:0]$11727 end case - assign $1\src26__data_o$next[3:0]$11740 4'0000 + assign $1\src26__data_o$next[3:0]$11724 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src26__data_o$next[3:0]$11745 4'0000 + assign $6\src26__data_o$next[3:0]$11729 4'0000 case - assign $6\src26__data_o$next[3:0]$11745 $1\src26__data_o$next[3:0]$11740 + assign $6\src26__data_o$next[3:0]$11729 $1\src26__data_o$next[3:0]$11724 end sync always - update \src26__data_o$next $0\src26__data_o$next[3:0]$11739 + update \src26__data_o$next $0\src26__data_o$next[3:0]$11723 end - attribute \src "libresoc.v:182924.3-182953.6" - process $proc$libresoc.v:182924$11746 + attribute \src "libresoc.v:184232.3-184261.6" + process $proc$libresoc.v:184232$11730 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11747 $1\wr_detect$7[0:0]$11748 - attribute \src "libresoc.v:182925.5-182925.29" + assign $0\wr_detect$7[0:0]$11731 $1\wr_detect$7[0:0]$11732 + attribute \src "libresoc.v:184233.5-184233.29" switch \initial - attribute \src "libresoc.v:182925.9-182925.17" + attribute \src "libresoc.v:184233.9-184233.17" case 1'1 case end @@ -373436,49 +344806,49 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11748 $4\wr_detect$7[0:0]$11751 + assign $1\wr_detect$7[0:0]$11732 $4\wr_detect$7[0:0]$11735 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11749 1'1 + assign $2\wr_detect$7[0:0]$11733 1'1 case - assign $2\wr_detect$7[0:0]$11749 1'0 + assign $2\wr_detect$7[0:0]$11733 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11750 1'1 + assign $3\wr_detect$7[0:0]$11734 1'1 case - assign $3\wr_detect$7[0:0]$11750 $2\wr_detect$7[0:0]$11749 + assign $3\wr_detect$7[0:0]$11734 $2\wr_detect$7[0:0]$11733 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11751 1'1 + assign $4\wr_detect$7[0:0]$11735 1'1 case - assign $4\wr_detect$7[0:0]$11751 $3\wr_detect$7[0:0]$11750 + assign $4\wr_detect$7[0:0]$11735 $3\wr_detect$7[0:0]$11734 end case - assign $1\wr_detect$7[0:0]$11748 1'0 + assign $1\wr_detect$7[0:0]$11732 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11747 + update \wr_detect$7 $0\wr_detect$7[0:0]$11731 end - attribute \src "libresoc.v:182954.3-182993.6" - process $proc$libresoc.v:182954$11752 + attribute \src "libresoc.v:184262.3-184301.6" + process $proc$libresoc.v:184262$11736 assign { } { } assign { } { } assign { } { } - assign $0\src36__data_o$next[3:0]$11753 $6\src36__data_o$next[3:0]$11759 - attribute \src "libresoc.v:182955.5-182955.29" + assign $0\src36__data_o$next[3:0]$11737 $6\src36__data_o$next[3:0]$11743 + attribute \src "libresoc.v:184263.5-184263.29" switch \initial - attribute \src "libresoc.v:182955.9-182955.17" + attribute \src "libresoc.v:184263.9-184263.17" case 1'1 case end @@ -373490,66 +344860,66 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\src36__data_o$next[3:0]$11754 $5\src36__data_o$next[3:0]$11758 + assign $1\src36__data_o$next[3:0]$11738 $5\src36__data_o$next[3:0]$11742 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src36__data_o$next[3:0]$11755 \dest16__data_i + assign $2\src36__data_o$next[3:0]$11739 \dest16__data_i case - assign $2\src36__data_o$next[3:0]$11755 4'0000 + assign $2\src36__data_o$next[3:0]$11739 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src36__data_o$next[3:0]$11756 \dest26__data_i + assign $3\src36__data_o$next[3:0]$11740 \dest26__data_i case - assign $3\src36__data_o$next[3:0]$11756 $2\src36__data_o$next[3:0]$11755 + assign $3\src36__data_o$next[3:0]$11740 $2\src36__data_o$next[3:0]$11739 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src36__data_o$next[3:0]$11757 \w6__data_i + assign $4\src36__data_o$next[3:0]$11741 \w6__data_i case - assign $4\src36__data_o$next[3:0]$11757 $3\src36__data_o$next[3:0]$11756 + assign $4\src36__data_o$next[3:0]$11741 $3\src36__data_o$next[3:0]$11740 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src36__data_o$next[3:0]$11758 \reg + assign $5\src36__data_o$next[3:0]$11742 \reg case - assign $5\src36__data_o$next[3:0]$11758 $4\src36__data_o$next[3:0]$11757 + assign $5\src36__data_o$next[3:0]$11742 $4\src36__data_o$next[3:0]$11741 end case - assign $1\src36__data_o$next[3:0]$11754 4'0000 + assign $1\src36__data_o$next[3:0]$11738 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src36__data_o$next[3:0]$11759 4'0000 + assign $6\src36__data_o$next[3:0]$11743 4'0000 case - assign $6\src36__data_o$next[3:0]$11759 $1\src36__data_o$next[3:0]$11754 + assign $6\src36__data_o$next[3:0]$11743 $1\src36__data_o$next[3:0]$11738 end sync always - update \src36__data_o$next $0\src36__data_o$next[3:0]$11753 + update \src36__data_o$next $0\src36__data_o$next[3:0]$11737 end - attribute \src "libresoc.v:182994.3-183023.6" - process $proc$libresoc.v:182994$11760 + attribute \src "libresoc.v:184302.3-184331.6" + process $proc$libresoc.v:184302$11744 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11761 $1\wr_detect$10[0:0]$11762 - attribute \src "libresoc.v:182995.5-182995.29" + assign $0\wr_detect$10[0:0]$11745 $1\wr_detect$10[0:0]$11746 + attribute \src "libresoc.v:184303.5-184303.29" switch \initial - attribute \src "libresoc.v:182995.9-182995.17" + attribute \src "libresoc.v:184303.9-184303.17" case 1'1 case end @@ -373561,49 +344931,49 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11762 $4\wr_detect$10[0:0]$11765 + assign $1\wr_detect$10[0:0]$11746 $4\wr_detect$10[0:0]$11749 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11763 1'1 + assign $2\wr_detect$10[0:0]$11747 1'1 case - assign $2\wr_detect$10[0:0]$11763 1'0 + assign $2\wr_detect$10[0:0]$11747 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11764 1'1 + assign $3\wr_detect$10[0:0]$11748 1'1 case - assign $3\wr_detect$10[0:0]$11764 $2\wr_detect$10[0:0]$11763 + assign $3\wr_detect$10[0:0]$11748 $2\wr_detect$10[0:0]$11747 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11765 1'1 + assign $4\wr_detect$10[0:0]$11749 1'1 case - assign $4\wr_detect$10[0:0]$11765 $3\wr_detect$10[0:0]$11764 + assign $4\wr_detect$10[0:0]$11749 $3\wr_detect$10[0:0]$11748 end case - assign $1\wr_detect$10[0:0]$11762 1'0 + assign $1\wr_detect$10[0:0]$11746 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11761 + update \wr_detect$10 $0\wr_detect$10[0:0]$11745 end - attribute \src "libresoc.v:183024.3-183063.6" - process $proc$libresoc.v:183024$11766 + attribute \src "libresoc.v:184332.3-184371.6" + process $proc$libresoc.v:184332$11750 assign { } { } assign { } { } assign { } { } - assign $0\r6__data_o$next[3:0]$11767 $6\r6__data_o$next[3:0]$11773 - attribute \src "libresoc.v:183025.5-183025.29" + assign $0\r6__data_o$next[3:0]$11751 $6\r6__data_o$next[3:0]$11757 + attribute \src "libresoc.v:184333.5-184333.29" switch \initial - attribute \src "libresoc.v:183025.9-183025.17" + attribute \src "libresoc.v:184333.9-184333.17" case 1'1 case end @@ -373615,66 +344985,66 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\r6__data_o$next[3:0]$11768 $5\r6__data_o$next[3:0]$11772 + assign $1\r6__data_o$next[3:0]$11752 $5\r6__data_o$next[3:0]$11756 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r6__data_o$next[3:0]$11769 \dest16__data_i + assign $2\r6__data_o$next[3:0]$11753 \dest16__data_i case - assign $2\r6__data_o$next[3:0]$11769 4'0000 + assign $2\r6__data_o$next[3:0]$11753 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r6__data_o$next[3:0]$11770 \dest26__data_i + assign $3\r6__data_o$next[3:0]$11754 \dest26__data_i case - assign $3\r6__data_o$next[3:0]$11770 $2\r6__data_o$next[3:0]$11769 + assign $3\r6__data_o$next[3:0]$11754 $2\r6__data_o$next[3:0]$11753 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r6__data_o$next[3:0]$11771 \w6__data_i + assign $4\r6__data_o$next[3:0]$11755 \w6__data_i case - assign $4\r6__data_o$next[3:0]$11771 $3\r6__data_o$next[3:0]$11770 + assign $4\r6__data_o$next[3:0]$11755 $3\r6__data_o$next[3:0]$11754 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r6__data_o$next[3:0]$11772 \reg + assign $5\r6__data_o$next[3:0]$11756 \reg case - assign $5\r6__data_o$next[3:0]$11772 $4\r6__data_o$next[3:0]$11771 + assign $5\r6__data_o$next[3:0]$11756 $4\r6__data_o$next[3:0]$11755 end case - assign $1\r6__data_o$next[3:0]$11768 4'0000 + assign $1\r6__data_o$next[3:0]$11752 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r6__data_o$next[3:0]$11773 4'0000 + assign $6\r6__data_o$next[3:0]$11757 4'0000 case - assign $6\r6__data_o$next[3:0]$11773 $1\r6__data_o$next[3:0]$11768 + assign $6\r6__data_o$next[3:0]$11757 $1\r6__data_o$next[3:0]$11752 end sync always - update \r6__data_o$next $0\r6__data_o$next[3:0]$11767 + update \r6__data_o$next $0\r6__data_o$next[3:0]$11751 end - attribute \src "libresoc.v:183064.3-183093.6" - process $proc$libresoc.v:183064$11774 + attribute \src "libresoc.v:184372.3-184401.6" + process $proc$libresoc.v:184372$11758 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11775 $1\wr_detect$13[0:0]$11776 - attribute \src "libresoc.v:183065.5-183065.29" + assign $0\wr_detect$13[0:0]$11759 $1\wr_detect$13[0:0]$11760 + attribute \src "libresoc.v:184373.5-184373.29" switch \initial - attribute \src "libresoc.v:183065.9-183065.17" + attribute \src "libresoc.v:184373.9-184373.17" case 1'1 case end @@ -373686,248 +345056,248 @@ module \reg_6 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11776 $4\wr_detect$13[0:0]$11779 + assign $1\wr_detect$13[0:0]$11760 $4\wr_detect$13[0:0]$11763 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest16__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11777 1'1 + assign $2\wr_detect$13[0:0]$11761 1'1 case - assign $2\wr_detect$13[0:0]$11777 1'0 + assign $2\wr_detect$13[0:0]$11761 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest26__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11778 1'1 + assign $3\wr_detect$13[0:0]$11762 1'1 case - assign $3\wr_detect$13[0:0]$11778 $2\wr_detect$13[0:0]$11777 + assign $3\wr_detect$13[0:0]$11762 $2\wr_detect$13[0:0]$11761 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w6__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11779 1'1 + assign $4\wr_detect$13[0:0]$11763 1'1 case - assign $4\wr_detect$13[0:0]$11779 $3\wr_detect$13[0:0]$11778 + assign $4\wr_detect$13[0:0]$11763 $3\wr_detect$13[0:0]$11762 end case - assign $1\wr_detect$13[0:0]$11776 1'0 + assign $1\wr_detect$13[0:0]$11760 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11775 + update \wr_detect$13 $0\wr_detect$13[0:0]$11759 end - connect \$9 $not$libresoc.v:182627$11682_Y - connect \$12 $not$libresoc.v:182628$11683_Y - connect \$15 $not$libresoc.v:182629$11684_Y - connect \$1 $not$libresoc.v:182630$11685_Y - connect \$3 $not$libresoc.v:182631$11686_Y - connect \$6 $not$libresoc.v:182632$11687_Y + connect \$9 $not$libresoc.v:183935$11666_Y + connect \$12 $not$libresoc.v:183936$11667_Y + connect \$15 $not$libresoc.v:183937$11668_Y + connect \$1 $not$libresoc.v:183938$11669_Y + connect \$3 $not$libresoc.v:183939$11670_Y + connect \$6 $not$libresoc.v:183940$11671_Y end -attribute \src "libresoc.v:183098.1-183653.10" +attribute \src "libresoc.v:184406.1-184961.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.cr.reg_7" attribute \generator "nMigen" module \reg_7 - attribute \src "libresoc.v:183206.3-183245.6" - wire width 4 $0\cr_pred7__data_o$next[3:0]$11802 - attribute \src "libresoc.v:183204.3-183205.49" + attribute \src "libresoc.v:184514.3-184553.6" + wire width 4 $0\cr_pred7__data_o$next[3:0]$11786 + attribute \src "libresoc.v:184512.3-184513.49" wire width 4 $0\cr_pred7__data_o[3:0] - attribute \src "libresoc.v:183099.7-183099.20" + attribute \src "libresoc.v:184407.7-184407.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183276.3-183315.6" - wire width 4 $0\r27__data_o$next[3:0]$11811 - attribute \src "libresoc.v:183194.3-183195.39" + attribute \src "libresoc.v:184584.3-184623.6" + wire width 4 $0\r27__data_o$next[3:0]$11795 + attribute \src "libresoc.v:184502.3-184503.39" wire width 4 $0\r27__data_o[3:0] - attribute \src "libresoc.v:183583.3-183622.6" - wire width 4 $0\r7__data_o$next[3:0]$11873 - attribute \src "libresoc.v:183196.3-183197.37" + attribute \src "libresoc.v:184891.3-184930.6" + wire width 4 $0\r7__data_o$next[3:0]$11857 + attribute \src "libresoc.v:184504.3-184505.37" wire width 4 $0\r7__data_o[3:0] - attribute \src "libresoc.v:183346.3-183372.6" - wire width 4 $0\reg$next[3:0]$11825 - attribute \src "libresoc.v:183192.3-183193.25" + attribute \src "libresoc.v:184654.3-184680.6" + wire width 4 $0\reg$next[3:0]$11809 + attribute \src "libresoc.v:184500.3-184501.25" wire width 4 $0\reg[3:0] - attribute \src "libresoc.v:183373.3-183412.6" - wire width 4 $0\src17__data_o$next[3:0]$11831 - attribute \src "libresoc.v:183202.3-183203.43" + attribute \src "libresoc.v:184681.3-184720.6" + wire width 4 $0\src17__data_o$next[3:0]$11815 + attribute \src "libresoc.v:184510.3-184511.43" wire width 4 $0\src17__data_o[3:0] - attribute \src "libresoc.v:183443.3-183482.6" - wire width 4 $0\src27__data_o$next[3:0]$11845 - attribute \src "libresoc.v:183200.3-183201.43" + attribute \src "libresoc.v:184751.3-184790.6" + wire width 4 $0\src27__data_o$next[3:0]$11829 + attribute \src "libresoc.v:184508.3-184509.43" wire width 4 $0\src27__data_o[3:0] - attribute \src "libresoc.v:183513.3-183552.6" - wire width 4 $0\src37__data_o$next[3:0]$11859 - attribute \src "libresoc.v:183198.3-183199.43" + attribute \src "libresoc.v:184821.3-184860.6" + wire width 4 $0\src37__data_o$next[3:0]$11843 + attribute \src "libresoc.v:184506.3-184507.43" wire width 4 $0\src37__data_o[3:0] - attribute \src "libresoc.v:183553.3-183582.6" - wire $0\wr_detect$10[0:0]$11867 - attribute \src "libresoc.v:183623.3-183652.6" - wire $0\wr_detect$13[0:0]$11881 - attribute \src "libresoc.v:183316.3-183345.6" - wire $0\wr_detect$16[0:0]$11819 - attribute \src "libresoc.v:183413.3-183442.6" - wire $0\wr_detect$4[0:0]$11839 - attribute \src "libresoc.v:183483.3-183512.6" - wire $0\wr_detect$7[0:0]$11853 - attribute \src "libresoc.v:183246.3-183275.6" + attribute \src "libresoc.v:184861.3-184890.6" + wire $0\wr_detect$10[0:0]$11851 + attribute \src "libresoc.v:184931.3-184960.6" + wire $0\wr_detect$13[0:0]$11865 + attribute \src "libresoc.v:184624.3-184653.6" + wire $0\wr_detect$16[0:0]$11803 + attribute \src "libresoc.v:184721.3-184750.6" + wire $0\wr_detect$4[0:0]$11823 + attribute \src "libresoc.v:184791.3-184820.6" + wire $0\wr_detect$7[0:0]$11837 + attribute \src "libresoc.v:184554.3-184583.6" wire $0\wr_detect[0:0] - attribute \src "libresoc.v:183206.3-183245.6" - wire width 4 $1\cr_pred7__data_o$next[3:0]$11803 - attribute \src "libresoc.v:183118.13-183118.36" + attribute \src "libresoc.v:184514.3-184553.6" + wire width 4 $1\cr_pred7__data_o$next[3:0]$11787 + attribute \src "libresoc.v:184426.13-184426.36" wire width 4 $1\cr_pred7__data_o[3:0] - attribute \src "libresoc.v:183276.3-183315.6" - wire width 4 $1\r27__data_o$next[3:0]$11812 - attribute \src "libresoc.v:183133.13-183133.31" + attribute \src "libresoc.v:184584.3-184623.6" + wire width 4 $1\r27__data_o$next[3:0]$11796 + attribute \src "libresoc.v:184441.13-184441.31" wire width 4 $1\r27__data_o[3:0] - attribute \src "libresoc.v:183583.3-183622.6" - wire width 4 $1\r7__data_o$next[3:0]$11874 - attribute \src "libresoc.v:183140.13-183140.30" + attribute \src "libresoc.v:184891.3-184930.6" + wire width 4 $1\r7__data_o$next[3:0]$11858 + attribute \src "libresoc.v:184448.13-184448.30" wire width 4 $1\r7__data_o[3:0] - attribute \src "libresoc.v:183346.3-183372.6" - wire width 4 $1\reg$next[3:0]$11826 - attribute \src "libresoc.v:183146.13-183146.25" + attribute \src "libresoc.v:184654.3-184680.6" + wire width 4 $1\reg$next[3:0]$11810 + attribute \src "libresoc.v:184454.13-184454.25" wire width 4 $1\reg[3:0] - attribute \src "libresoc.v:183373.3-183412.6" - wire width 4 $1\src17__data_o$next[3:0]$11832 - attribute \src "libresoc.v:183151.13-183151.33" + attribute \src "libresoc.v:184681.3-184720.6" + wire width 4 $1\src17__data_o$next[3:0]$11816 + attribute \src "libresoc.v:184459.13-184459.33" wire width 4 $1\src17__data_o[3:0] - attribute \src "libresoc.v:183443.3-183482.6" - wire width 4 $1\src27__data_o$next[3:0]$11846 - attribute \src "libresoc.v:183158.13-183158.33" + attribute \src "libresoc.v:184751.3-184790.6" + wire width 4 $1\src27__data_o$next[3:0]$11830 + attribute \src "libresoc.v:184466.13-184466.33" wire width 4 $1\src27__data_o[3:0] - attribute \src "libresoc.v:183513.3-183552.6" - wire width 4 $1\src37__data_o$next[3:0]$11860 - attribute \src "libresoc.v:183165.13-183165.33" + attribute \src "libresoc.v:184821.3-184860.6" + wire width 4 $1\src37__data_o$next[3:0]$11844 + attribute \src "libresoc.v:184473.13-184473.33" wire width 4 $1\src37__data_o[3:0] - attribute \src "libresoc.v:183553.3-183582.6" - wire $1\wr_detect$10[0:0]$11868 - attribute \src "libresoc.v:183623.3-183652.6" - wire $1\wr_detect$13[0:0]$11882 - attribute \src "libresoc.v:183316.3-183345.6" - wire $1\wr_detect$16[0:0]$11820 - attribute \src "libresoc.v:183413.3-183442.6" - wire $1\wr_detect$4[0:0]$11840 - attribute \src "libresoc.v:183483.3-183512.6" - wire $1\wr_detect$7[0:0]$11854 - attribute \src "libresoc.v:183246.3-183275.6" + attribute \src "libresoc.v:184861.3-184890.6" + wire $1\wr_detect$10[0:0]$11852 + attribute \src "libresoc.v:184931.3-184960.6" + wire $1\wr_detect$13[0:0]$11866 + attribute \src "libresoc.v:184624.3-184653.6" + wire $1\wr_detect$16[0:0]$11804 + attribute \src "libresoc.v:184721.3-184750.6" + wire $1\wr_detect$4[0:0]$11824 + attribute \src "libresoc.v:184791.3-184820.6" + wire $1\wr_detect$7[0:0]$11838 + attribute \src "libresoc.v:184554.3-184583.6" wire $1\wr_detect[0:0] - attribute \src "libresoc.v:183206.3-183245.6" - wire width 4 $2\cr_pred7__data_o$next[3:0]$11804 - attribute \src "libresoc.v:183276.3-183315.6" - wire width 4 $2\r27__data_o$next[3:0]$11813 - attribute \src "libresoc.v:183583.3-183622.6" - wire width 4 $2\r7__data_o$next[3:0]$11875 - attribute \src "libresoc.v:183346.3-183372.6" - wire width 4 $2\reg$next[3:0]$11827 - attribute \src "libresoc.v:183373.3-183412.6" - wire width 4 $2\src17__data_o$next[3:0]$11833 - attribute \src "libresoc.v:183443.3-183482.6" - wire width 4 $2\src27__data_o$next[3:0]$11847 - attribute \src "libresoc.v:183513.3-183552.6" - wire width 4 $2\src37__data_o$next[3:0]$11861 - attribute \src "libresoc.v:183553.3-183582.6" - wire $2\wr_detect$10[0:0]$11869 - attribute \src "libresoc.v:183623.3-183652.6" - wire $2\wr_detect$13[0:0]$11883 - attribute \src "libresoc.v:183316.3-183345.6" - wire $2\wr_detect$16[0:0]$11821 - attribute \src "libresoc.v:183413.3-183442.6" - wire $2\wr_detect$4[0:0]$11841 - attribute \src "libresoc.v:183483.3-183512.6" - wire $2\wr_detect$7[0:0]$11855 - attribute \src "libresoc.v:183246.3-183275.6" + attribute \src "libresoc.v:184514.3-184553.6" + wire width 4 $2\cr_pred7__data_o$next[3:0]$11788 + attribute \src "libresoc.v:184584.3-184623.6" + wire width 4 $2\r27__data_o$next[3:0]$11797 + attribute \src "libresoc.v:184891.3-184930.6" + wire width 4 $2\r7__data_o$next[3:0]$11859 + attribute \src "libresoc.v:184654.3-184680.6" + wire width 4 $2\reg$next[3:0]$11811 + attribute \src "libresoc.v:184681.3-184720.6" + wire width 4 $2\src17__data_o$next[3:0]$11817 + attribute \src "libresoc.v:184751.3-184790.6" + wire width 4 $2\src27__data_o$next[3:0]$11831 + attribute \src "libresoc.v:184821.3-184860.6" + wire width 4 $2\src37__data_o$next[3:0]$11845 + attribute \src "libresoc.v:184861.3-184890.6" + wire $2\wr_detect$10[0:0]$11853 + attribute \src "libresoc.v:184931.3-184960.6" + wire $2\wr_detect$13[0:0]$11867 + attribute \src "libresoc.v:184624.3-184653.6" + wire $2\wr_detect$16[0:0]$11805 + attribute \src "libresoc.v:184721.3-184750.6" + wire $2\wr_detect$4[0:0]$11825 + attribute \src "libresoc.v:184791.3-184820.6" + wire $2\wr_detect$7[0:0]$11839 + attribute \src "libresoc.v:184554.3-184583.6" wire $2\wr_detect[0:0] - attribute \src "libresoc.v:183206.3-183245.6" - wire width 4 $3\cr_pred7__data_o$next[3:0]$11805 - attribute \src "libresoc.v:183276.3-183315.6" - wire width 4 $3\r27__data_o$next[3:0]$11814 - attribute \src "libresoc.v:183583.3-183622.6" - wire width 4 $3\r7__data_o$next[3:0]$11876 - attribute \src "libresoc.v:183346.3-183372.6" - wire width 4 $3\reg$next[3:0]$11828 - attribute \src "libresoc.v:183373.3-183412.6" - wire width 4 $3\src17__data_o$next[3:0]$11834 - attribute \src "libresoc.v:183443.3-183482.6" - wire width 4 $3\src27__data_o$next[3:0]$11848 - attribute \src "libresoc.v:183513.3-183552.6" - wire width 4 $3\src37__data_o$next[3:0]$11862 - attribute \src "libresoc.v:183553.3-183582.6" - wire $3\wr_detect$10[0:0]$11870 - attribute \src "libresoc.v:183623.3-183652.6" - wire $3\wr_detect$13[0:0]$11884 - attribute \src "libresoc.v:183316.3-183345.6" - wire $3\wr_detect$16[0:0]$11822 - attribute \src "libresoc.v:183413.3-183442.6" - wire $3\wr_detect$4[0:0]$11842 - attribute \src "libresoc.v:183483.3-183512.6" - wire $3\wr_detect$7[0:0]$11856 - attribute \src "libresoc.v:183246.3-183275.6" + attribute \src "libresoc.v:184514.3-184553.6" + wire width 4 $3\cr_pred7__data_o$next[3:0]$11789 + attribute \src "libresoc.v:184584.3-184623.6" + wire width 4 $3\r27__data_o$next[3:0]$11798 + attribute \src "libresoc.v:184891.3-184930.6" + wire width 4 $3\r7__data_o$next[3:0]$11860 + attribute \src "libresoc.v:184654.3-184680.6" + wire width 4 $3\reg$next[3:0]$11812 + attribute \src "libresoc.v:184681.3-184720.6" + wire width 4 $3\src17__data_o$next[3:0]$11818 + attribute \src "libresoc.v:184751.3-184790.6" + wire width 4 $3\src27__data_o$next[3:0]$11832 + attribute \src "libresoc.v:184821.3-184860.6" + wire width 4 $3\src37__data_o$next[3:0]$11846 + attribute \src "libresoc.v:184861.3-184890.6" + wire $3\wr_detect$10[0:0]$11854 + attribute \src "libresoc.v:184931.3-184960.6" + wire $3\wr_detect$13[0:0]$11868 + attribute \src "libresoc.v:184624.3-184653.6" + wire $3\wr_detect$16[0:0]$11806 + attribute \src "libresoc.v:184721.3-184750.6" + wire $3\wr_detect$4[0:0]$11826 + attribute \src "libresoc.v:184791.3-184820.6" + wire $3\wr_detect$7[0:0]$11840 + attribute \src "libresoc.v:184554.3-184583.6" wire $3\wr_detect[0:0] - attribute \src "libresoc.v:183206.3-183245.6" - wire width 4 $4\cr_pred7__data_o$next[3:0]$11806 - attribute \src "libresoc.v:183276.3-183315.6" - wire width 4 $4\r27__data_o$next[3:0]$11815 - attribute \src "libresoc.v:183583.3-183622.6" - wire width 4 $4\r7__data_o$next[3:0]$11877 - attribute \src "libresoc.v:183346.3-183372.6" - wire width 4 $4\reg$next[3:0]$11829 - attribute \src "libresoc.v:183373.3-183412.6" - wire width 4 $4\src17__data_o$next[3:0]$11835 - attribute \src "libresoc.v:183443.3-183482.6" - wire width 4 $4\src27__data_o$next[3:0]$11849 - attribute \src "libresoc.v:183513.3-183552.6" - wire width 4 $4\src37__data_o$next[3:0]$11863 - attribute \src "libresoc.v:183553.3-183582.6" - wire $4\wr_detect$10[0:0]$11871 - attribute \src "libresoc.v:183623.3-183652.6" - wire $4\wr_detect$13[0:0]$11885 - attribute \src "libresoc.v:183316.3-183345.6" - wire $4\wr_detect$16[0:0]$11823 - attribute \src "libresoc.v:183413.3-183442.6" - wire $4\wr_detect$4[0:0]$11843 - attribute \src "libresoc.v:183483.3-183512.6" - wire $4\wr_detect$7[0:0]$11857 - attribute \src "libresoc.v:183246.3-183275.6" + attribute \src "libresoc.v:184514.3-184553.6" + wire width 4 $4\cr_pred7__data_o$next[3:0]$11790 + attribute \src "libresoc.v:184584.3-184623.6" + wire width 4 $4\r27__data_o$next[3:0]$11799 + attribute \src "libresoc.v:184891.3-184930.6" + wire width 4 $4\r7__data_o$next[3:0]$11861 + attribute \src "libresoc.v:184654.3-184680.6" + wire width 4 $4\reg$next[3:0]$11813 + attribute \src "libresoc.v:184681.3-184720.6" + wire width 4 $4\src17__data_o$next[3:0]$11819 + attribute \src "libresoc.v:184751.3-184790.6" + wire width 4 $4\src27__data_o$next[3:0]$11833 + attribute \src "libresoc.v:184821.3-184860.6" + wire width 4 $4\src37__data_o$next[3:0]$11847 + attribute \src "libresoc.v:184861.3-184890.6" + wire $4\wr_detect$10[0:0]$11855 + attribute \src "libresoc.v:184931.3-184960.6" + wire $4\wr_detect$13[0:0]$11869 + attribute \src "libresoc.v:184624.3-184653.6" + wire $4\wr_detect$16[0:0]$11807 + attribute \src "libresoc.v:184721.3-184750.6" + wire $4\wr_detect$4[0:0]$11827 + attribute \src "libresoc.v:184791.3-184820.6" + wire $4\wr_detect$7[0:0]$11841 + attribute \src "libresoc.v:184554.3-184583.6" wire $4\wr_detect[0:0] - attribute \src "libresoc.v:183206.3-183245.6" - wire width 4 $5\cr_pred7__data_o$next[3:0]$11807 - attribute \src "libresoc.v:183276.3-183315.6" - wire width 4 $5\r27__data_o$next[3:0]$11816 - attribute \src "libresoc.v:183583.3-183622.6" - wire width 4 $5\r7__data_o$next[3:0]$11878 - attribute \src "libresoc.v:183373.3-183412.6" - wire width 4 $5\src17__data_o$next[3:0]$11836 - attribute \src "libresoc.v:183443.3-183482.6" - wire width 4 $5\src27__data_o$next[3:0]$11850 - attribute \src "libresoc.v:183513.3-183552.6" - wire width 4 $5\src37__data_o$next[3:0]$11864 - attribute \src "libresoc.v:183206.3-183245.6" - wire width 4 $6\cr_pred7__data_o$next[3:0]$11808 - attribute \src "libresoc.v:183276.3-183315.6" - wire width 4 $6\r27__data_o$next[3:0]$11817 - attribute \src "libresoc.v:183583.3-183622.6" - wire width 4 $6\r7__data_o$next[3:0]$11879 - attribute \src "libresoc.v:183373.3-183412.6" - wire width 4 $6\src17__data_o$next[3:0]$11837 - attribute \src "libresoc.v:183443.3-183482.6" - wire width 4 $6\src27__data_o$next[3:0]$11851 - attribute \src "libresoc.v:183513.3-183552.6" - wire width 4 $6\src37__data_o$next[3:0]$11865 - attribute \src "libresoc.v:183186.17-183186.104" - wire $not$libresoc.v:183186$11788_Y - attribute \src "libresoc.v:183187.18-183187.105" - wire $not$libresoc.v:183187$11789_Y - attribute \src "libresoc.v:183188.18-183188.105" - wire $not$libresoc.v:183188$11790_Y - attribute \src "libresoc.v:183189.17-183189.100" - wire $not$libresoc.v:183189$11791_Y - attribute \src "libresoc.v:183190.17-183190.103" - wire $not$libresoc.v:183190$11792_Y - attribute \src "libresoc.v:183191.17-183191.103" - wire $not$libresoc.v:183191$11793_Y + attribute \src "libresoc.v:184514.3-184553.6" + wire width 4 $5\cr_pred7__data_o$next[3:0]$11791 + attribute \src "libresoc.v:184584.3-184623.6" + wire width 4 $5\r27__data_o$next[3:0]$11800 + attribute \src "libresoc.v:184891.3-184930.6" + wire width 4 $5\r7__data_o$next[3:0]$11862 + attribute \src "libresoc.v:184681.3-184720.6" + wire width 4 $5\src17__data_o$next[3:0]$11820 + attribute \src "libresoc.v:184751.3-184790.6" + wire width 4 $5\src27__data_o$next[3:0]$11834 + attribute \src "libresoc.v:184821.3-184860.6" + wire width 4 $5\src37__data_o$next[3:0]$11848 + attribute \src "libresoc.v:184514.3-184553.6" + wire width 4 $6\cr_pred7__data_o$next[3:0]$11792 + attribute \src "libresoc.v:184584.3-184623.6" + wire width 4 $6\r27__data_o$next[3:0]$11801 + attribute \src "libresoc.v:184891.3-184930.6" + wire width 4 $6\r7__data_o$next[3:0]$11863 + attribute \src "libresoc.v:184681.3-184720.6" + wire width 4 $6\src17__data_o$next[3:0]$11821 + attribute \src "libresoc.v:184751.3-184790.6" + wire width 4 $6\src27__data_o$next[3:0]$11835 + attribute \src "libresoc.v:184821.3-184860.6" + wire width 4 $6\src37__data_o$next[3:0]$11849 + attribute \src "libresoc.v:184494.17-184494.104" + wire $not$libresoc.v:184494$11772_Y + attribute \src "libresoc.v:184495.18-184495.105" + wire $not$libresoc.v:184495$11773_Y + attribute \src "libresoc.v:184496.18-184496.105" + wire $not$libresoc.v:184496$11774_Y + attribute \src "libresoc.v:184497.17-184497.100" + wire $not$libresoc.v:184497$11775_Y + attribute \src "libresoc.v:184498.17-184498.103" + wire $not$libresoc.v:184498$11776_Y + attribute \src "libresoc.v:184499.17-184499.103" + wire $not$libresoc.v:184499$11777_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" @@ -373940,9 +345310,9 @@ module \reg_7 wire \$6 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 20 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 3 \cr_pred7__data_o @@ -373958,7 +345328,7 @@ module \reg_7 wire width 4 input 13 \dest27__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 12 \dest27__wen - attribute \src "libresoc.v:183099.7-183099.15" + attribute \src "libresoc.v:184407.7-184407.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 4 output 16 \r27__data_o @@ -374011,175 +345381,175 @@ module \reg_7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" wire \wr_detect$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:183186$11788 + cell $not $not$libresoc.v:184494$11772 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$10 - connect \Y $not$libresoc.v:183186$11788_Y + connect \Y $not$libresoc.v:184494$11772_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:183187$11789 + cell $not $not$libresoc.v:184495$11773 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$13 - connect \Y $not$libresoc.v:183187$11789_Y + connect \Y $not$libresoc.v:184495$11773_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:183188$11790 + cell $not $not$libresoc.v:184496$11774 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$16 - connect \Y $not$libresoc.v:183188$11790_Y + connect \Y $not$libresoc.v:184496$11774_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:183189$11791 + cell $not $not$libresoc.v:184497$11775 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect - connect \Y $not$libresoc.v:183189$11791_Y + connect \Y $not$libresoc.v:184497$11775_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:183190$11792 + cell $not $not$libresoc.v:184498$11776 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$4 - connect \Y $not$libresoc.v:183190$11792_Y + connect \Y $not$libresoc.v:184498$11776_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $not$libresoc.v:183191$11793 + cell $not $not$libresoc.v:184499$11777 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \wr_detect$7 - connect \Y $not$libresoc.v:183191$11793_Y + connect \Y $not$libresoc.v:184499$11777_Y end - attribute \src "libresoc.v:183099.7-183099.20" - process $proc$libresoc.v:183099$11886 + attribute \src "libresoc.v:184407.7-184407.20" + process $proc$libresoc.v:184407$11870 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183118.13-183118.36" - process $proc$libresoc.v:183118$11887 + attribute \src "libresoc.v:184426.13-184426.36" + process $proc$libresoc.v:184426$11871 assign { } { } assign $1\cr_pred7__data_o[3:0] 4'0000 sync always sync init update \cr_pred7__data_o $1\cr_pred7__data_o[3:0] end - attribute \src "libresoc.v:183133.13-183133.31" - process $proc$libresoc.v:183133$11888 + attribute \src "libresoc.v:184441.13-184441.31" + process $proc$libresoc.v:184441$11872 assign { } { } assign $1\r27__data_o[3:0] 4'0000 sync always sync init update \r27__data_o $1\r27__data_o[3:0] end - attribute \src "libresoc.v:183140.13-183140.30" - process $proc$libresoc.v:183140$11889 + attribute \src "libresoc.v:184448.13-184448.30" + process $proc$libresoc.v:184448$11873 assign { } { } assign $1\r7__data_o[3:0] 4'0000 sync always sync init update \r7__data_o $1\r7__data_o[3:0] end - attribute \src "libresoc.v:183146.13-183146.25" - process $proc$libresoc.v:183146$11890 + attribute \src "libresoc.v:184454.13-184454.25" + process $proc$libresoc.v:184454$11874 assign { } { } assign $1\reg[3:0] 4'0000 sync always sync init update \reg $1\reg[3:0] end - attribute \src "libresoc.v:183151.13-183151.33" - process $proc$libresoc.v:183151$11891 + attribute \src "libresoc.v:184459.13-184459.33" + process $proc$libresoc.v:184459$11875 assign { } { } assign $1\src17__data_o[3:0] 4'0000 sync always sync init update \src17__data_o $1\src17__data_o[3:0] end - attribute \src "libresoc.v:183158.13-183158.33" - process $proc$libresoc.v:183158$11892 + attribute \src "libresoc.v:184466.13-184466.33" + process $proc$libresoc.v:184466$11876 assign { } { } assign $1\src27__data_o[3:0] 4'0000 sync always sync init update \src27__data_o $1\src27__data_o[3:0] end - attribute \src "libresoc.v:183165.13-183165.33" - process $proc$libresoc.v:183165$11893 + attribute \src "libresoc.v:184473.13-184473.33" + process $proc$libresoc.v:184473$11877 assign { } { } assign $1\src37__data_o[3:0] 4'0000 sync always sync init update \src37__data_o $1\src37__data_o[3:0] end - attribute \src "libresoc.v:183192.3-183193.25" - process $proc$libresoc.v:183192$11794 + attribute \src "libresoc.v:184500.3-184501.25" + process $proc$libresoc.v:184500$11778 assign { } { } assign $0\reg[3:0] \reg$next sync posedge \coresync_clk update \reg $0\reg[3:0] end - attribute \src "libresoc.v:183194.3-183195.39" - process $proc$libresoc.v:183194$11795 + attribute \src "libresoc.v:184502.3-184503.39" + process $proc$libresoc.v:184502$11779 assign { } { } assign $0\r27__data_o[3:0] \r27__data_o$next sync posedge \coresync_clk update \r27__data_o $0\r27__data_o[3:0] end - attribute \src "libresoc.v:183196.3-183197.37" - process $proc$libresoc.v:183196$11796 + attribute \src "libresoc.v:184504.3-184505.37" + process $proc$libresoc.v:184504$11780 assign { } { } assign $0\r7__data_o[3:0] \r7__data_o$next sync posedge \coresync_clk update \r7__data_o $0\r7__data_o[3:0] end - attribute \src "libresoc.v:183198.3-183199.43" - process $proc$libresoc.v:183198$11797 + attribute \src "libresoc.v:184506.3-184507.43" + process $proc$libresoc.v:184506$11781 assign { } { } assign $0\src37__data_o[3:0] \src37__data_o$next sync posedge \coresync_clk update \src37__data_o $0\src37__data_o[3:0] end - attribute \src "libresoc.v:183200.3-183201.43" - process $proc$libresoc.v:183200$11798 + attribute \src "libresoc.v:184508.3-184509.43" + process $proc$libresoc.v:184508$11782 assign { } { } assign $0\src27__data_o[3:0] \src27__data_o$next sync posedge \coresync_clk update \src27__data_o $0\src27__data_o[3:0] end - attribute \src "libresoc.v:183202.3-183203.43" - process $proc$libresoc.v:183202$11799 + attribute \src "libresoc.v:184510.3-184511.43" + process $proc$libresoc.v:184510$11783 assign { } { } assign $0\src17__data_o[3:0] \src17__data_o$next sync posedge \coresync_clk update \src17__data_o $0\src17__data_o[3:0] end - attribute \src "libresoc.v:183204.3-183205.49" - process $proc$libresoc.v:183204$11800 + attribute \src "libresoc.v:184512.3-184513.49" + process $proc$libresoc.v:184512$11784 assign { } { } assign $0\cr_pred7__data_o[3:0] \cr_pred7__data_o$next sync posedge \coresync_clk update \cr_pred7__data_o $0\cr_pred7__data_o[3:0] end - attribute \src "libresoc.v:183206.3-183245.6" - process $proc$libresoc.v:183206$11801 + attribute \src "libresoc.v:184514.3-184553.6" + process $proc$libresoc.v:184514$11785 assign { } { } assign { } { } assign { } { } - assign $0\cr_pred7__data_o$next[3:0]$11802 $6\cr_pred7__data_o$next[3:0]$11808 - attribute \src "libresoc.v:183207.5-183207.29" + assign $0\cr_pred7__data_o$next[3:0]$11786 $6\cr_pred7__data_o$next[3:0]$11792 + attribute \src "libresoc.v:184515.5-184515.29" switch \initial - attribute \src "libresoc.v:183207.9-183207.17" + attribute \src "libresoc.v:184515.9-184515.17" case 1'1 case end @@ -374191,66 +345561,66 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\cr_pred7__data_o$next[3:0]$11803 $5\cr_pred7__data_o$next[3:0]$11807 + assign $1\cr_pred7__data_o$next[3:0]$11787 $5\cr_pred7__data_o$next[3:0]$11791 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\cr_pred7__data_o$next[3:0]$11804 \dest17__data_i + assign $2\cr_pred7__data_o$next[3:0]$11788 \dest17__data_i case - assign $2\cr_pred7__data_o$next[3:0]$11804 4'0000 + assign $2\cr_pred7__data_o$next[3:0]$11788 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\cr_pred7__data_o$next[3:0]$11805 \dest27__data_i + assign $3\cr_pred7__data_o$next[3:0]$11789 \dest27__data_i case - assign $3\cr_pred7__data_o$next[3:0]$11805 $2\cr_pred7__data_o$next[3:0]$11804 + assign $3\cr_pred7__data_o$next[3:0]$11789 $2\cr_pred7__data_o$next[3:0]$11788 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cr_pred7__data_o$next[3:0]$11806 \w7__data_i + assign $4\cr_pred7__data_o$next[3:0]$11790 \w7__data_i case - assign $4\cr_pred7__data_o$next[3:0]$11806 $3\cr_pred7__data_o$next[3:0]$11805 + assign $4\cr_pred7__data_o$next[3:0]$11790 $3\cr_pred7__data_o$next[3:0]$11789 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$1 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\cr_pred7__data_o$next[3:0]$11807 \reg + assign $5\cr_pred7__data_o$next[3:0]$11791 \reg case - assign $5\cr_pred7__data_o$next[3:0]$11807 $4\cr_pred7__data_o$next[3:0]$11806 + assign $5\cr_pred7__data_o$next[3:0]$11791 $4\cr_pred7__data_o$next[3:0]$11790 end case - assign $1\cr_pred7__data_o$next[3:0]$11803 4'0000 + assign $1\cr_pred7__data_o$next[3:0]$11787 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\cr_pred7__data_o$next[3:0]$11808 4'0000 + assign $6\cr_pred7__data_o$next[3:0]$11792 4'0000 case - assign $6\cr_pred7__data_o$next[3:0]$11808 $1\cr_pred7__data_o$next[3:0]$11803 + assign $6\cr_pred7__data_o$next[3:0]$11792 $1\cr_pred7__data_o$next[3:0]$11787 end sync always - update \cr_pred7__data_o$next $0\cr_pred7__data_o$next[3:0]$11802 + update \cr_pred7__data_o$next $0\cr_pred7__data_o$next[3:0]$11786 end - attribute \src "libresoc.v:183246.3-183275.6" - process $proc$libresoc.v:183246$11809 + attribute \src "libresoc.v:184554.3-184583.6" + process $proc$libresoc.v:184554$11793 assign { } { } assign { } { } assign $0\wr_detect[0:0] $1\wr_detect[0:0] - attribute \src "libresoc.v:183247.5-183247.29" + attribute \src "libresoc.v:184555.5-184555.29" switch \initial - attribute \src "libresoc.v:183247.9-183247.17" + attribute \src "libresoc.v:184555.9-184555.17" case 1'1 case end @@ -374296,15 +345666,15 @@ module \reg_7 sync always update \wr_detect $0\wr_detect[0:0] end - attribute \src "libresoc.v:183276.3-183315.6" - process $proc$libresoc.v:183276$11810 + attribute \src "libresoc.v:184584.3-184623.6" + process $proc$libresoc.v:184584$11794 assign { } { } assign { } { } assign { } { } - assign $0\r27__data_o$next[3:0]$11811 $6\r27__data_o$next[3:0]$11817 - attribute \src "libresoc.v:183277.5-183277.29" + assign $0\r27__data_o$next[3:0]$11795 $6\r27__data_o$next[3:0]$11801 + attribute \src "libresoc.v:184585.5-184585.29" switch \initial - attribute \src "libresoc.v:183277.9-183277.17" + attribute \src "libresoc.v:184585.9-184585.17" case 1'1 case end @@ -374316,66 +345686,66 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\r27__data_o$next[3:0]$11812 $5\r27__data_o$next[3:0]$11816 + assign $1\r27__data_o$next[3:0]$11796 $5\r27__data_o$next[3:0]$11800 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r27__data_o$next[3:0]$11813 \dest17__data_i + assign $2\r27__data_o$next[3:0]$11797 \dest17__data_i case - assign $2\r27__data_o$next[3:0]$11813 4'0000 + assign $2\r27__data_o$next[3:0]$11797 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r27__data_o$next[3:0]$11814 \dest27__data_i + assign $3\r27__data_o$next[3:0]$11798 \dest27__data_i case - assign $3\r27__data_o$next[3:0]$11814 $2\r27__data_o$next[3:0]$11813 + assign $3\r27__data_o$next[3:0]$11798 $2\r27__data_o$next[3:0]$11797 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r27__data_o$next[3:0]$11815 \w7__data_i + assign $4\r27__data_o$next[3:0]$11799 \w7__data_i case - assign $4\r27__data_o$next[3:0]$11815 $3\r27__data_o$next[3:0]$11814 + assign $4\r27__data_o$next[3:0]$11799 $3\r27__data_o$next[3:0]$11798 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$15 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r27__data_o$next[3:0]$11816 \reg + assign $5\r27__data_o$next[3:0]$11800 \reg case - assign $5\r27__data_o$next[3:0]$11816 $4\r27__data_o$next[3:0]$11815 + assign $5\r27__data_o$next[3:0]$11800 $4\r27__data_o$next[3:0]$11799 end case - assign $1\r27__data_o$next[3:0]$11812 4'0000 + assign $1\r27__data_o$next[3:0]$11796 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r27__data_o$next[3:0]$11817 4'0000 + assign $6\r27__data_o$next[3:0]$11801 4'0000 case - assign $6\r27__data_o$next[3:0]$11817 $1\r27__data_o$next[3:0]$11812 + assign $6\r27__data_o$next[3:0]$11801 $1\r27__data_o$next[3:0]$11796 end sync always - update \r27__data_o$next $0\r27__data_o$next[3:0]$11811 + update \r27__data_o$next $0\r27__data_o$next[3:0]$11795 end - attribute \src "libresoc.v:183316.3-183345.6" - process $proc$libresoc.v:183316$11818 + attribute \src "libresoc.v:184624.3-184653.6" + process $proc$libresoc.v:184624$11802 assign { } { } assign { } { } - assign $0\wr_detect$16[0:0]$11819 $1\wr_detect$16[0:0]$11820 - attribute \src "libresoc.v:183317.5-183317.29" + assign $0\wr_detect$16[0:0]$11803 $1\wr_detect$16[0:0]$11804 + attribute \src "libresoc.v:184625.5-184625.29" switch \initial - attribute \src "libresoc.v:183317.9-183317.17" + attribute \src "libresoc.v:184625.9-184625.17" case 1'1 case end @@ -374387,51 +345757,51 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$16[0:0]$11820 $4\wr_detect$16[0:0]$11823 + assign $1\wr_detect$16[0:0]$11804 $4\wr_detect$16[0:0]$11807 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$16[0:0]$11821 1'1 + assign $2\wr_detect$16[0:0]$11805 1'1 case - assign $2\wr_detect$16[0:0]$11821 1'0 + assign $2\wr_detect$16[0:0]$11805 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$16[0:0]$11822 1'1 + assign $3\wr_detect$16[0:0]$11806 1'1 case - assign $3\wr_detect$16[0:0]$11822 $2\wr_detect$16[0:0]$11821 + assign $3\wr_detect$16[0:0]$11806 $2\wr_detect$16[0:0]$11805 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$16[0:0]$11823 1'1 + assign $4\wr_detect$16[0:0]$11807 1'1 case - assign $4\wr_detect$16[0:0]$11823 $3\wr_detect$16[0:0]$11822 + assign $4\wr_detect$16[0:0]$11807 $3\wr_detect$16[0:0]$11806 end case - assign $1\wr_detect$16[0:0]$11820 1'0 + assign $1\wr_detect$16[0:0]$11804 1'0 end sync always - update \wr_detect$16 $0\wr_detect$16[0:0]$11819 + update \wr_detect$16 $0\wr_detect$16[0:0]$11803 end - attribute \src "libresoc.v:183346.3-183372.6" - process $proc$libresoc.v:183346$11824 + attribute \src "libresoc.v:184654.3-184680.6" + process $proc$libresoc.v:184654$11808 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\reg$next[3:0]$11825 $4\reg$next[3:0]$11829 - attribute \src "libresoc.v:183347.5-183347.29" + assign $0\reg$next[3:0]$11809 $4\reg$next[3:0]$11813 + attribute \src "libresoc.v:184655.5-184655.29" switch \initial - attribute \src "libresoc.v:183347.9-183347.17" + attribute \src "libresoc.v:184655.9-184655.17" case 1'1 case end @@ -374440,49 +345810,49 @@ module \reg_7 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\reg$next[3:0]$11826 \dest17__data_i + assign $1\reg$next[3:0]$11810 \dest17__data_i case - assign $1\reg$next[3:0]$11826 \reg + assign $1\reg$next[3:0]$11810 \reg end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\reg$next[3:0]$11827 \dest27__data_i + assign $2\reg$next[3:0]$11811 \dest27__data_i case - assign $2\reg$next[3:0]$11827 $1\reg$next[3:0]$11826 + assign $2\reg$next[3:0]$11811 $1\reg$next[3:0]$11810 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\reg$next[3:0]$11828 \w7__data_i + assign $3\reg$next[3:0]$11812 \w7__data_i case - assign $3\reg$next[3:0]$11828 $2\reg$next[3:0]$11827 + assign $3\reg$next[3:0]$11812 $2\reg$next[3:0]$11811 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\reg$next[3:0]$11829 4'0000 + assign $4\reg$next[3:0]$11813 4'0000 case - assign $4\reg$next[3:0]$11829 $3\reg$next[3:0]$11828 + assign $4\reg$next[3:0]$11813 $3\reg$next[3:0]$11812 end sync always - update \reg$next $0\reg$next[3:0]$11825 + update \reg$next $0\reg$next[3:0]$11809 end - attribute \src "libresoc.v:183373.3-183412.6" - process $proc$libresoc.v:183373$11830 + attribute \src "libresoc.v:184681.3-184720.6" + process $proc$libresoc.v:184681$11814 assign { } { } assign { } { } assign { } { } - assign $0\src17__data_o$next[3:0]$11831 $6\src17__data_o$next[3:0]$11837 - attribute \src "libresoc.v:183374.5-183374.29" + assign $0\src17__data_o$next[3:0]$11815 $6\src17__data_o$next[3:0]$11821 + attribute \src "libresoc.v:184682.5-184682.29" switch \initial - attribute \src "libresoc.v:183374.9-183374.17" + attribute \src "libresoc.v:184682.9-184682.17" case 1'1 case end @@ -374494,66 +345864,66 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\src17__data_o$next[3:0]$11832 $5\src17__data_o$next[3:0]$11836 + assign $1\src17__data_o$next[3:0]$11816 $5\src17__data_o$next[3:0]$11820 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src17__data_o$next[3:0]$11833 \dest17__data_i + assign $2\src17__data_o$next[3:0]$11817 \dest17__data_i case - assign $2\src17__data_o$next[3:0]$11833 4'0000 + assign $2\src17__data_o$next[3:0]$11817 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src17__data_o$next[3:0]$11834 \dest27__data_i + assign $3\src17__data_o$next[3:0]$11818 \dest27__data_i case - assign $3\src17__data_o$next[3:0]$11834 $2\src17__data_o$next[3:0]$11833 + assign $3\src17__data_o$next[3:0]$11818 $2\src17__data_o$next[3:0]$11817 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src17__data_o$next[3:0]$11835 \w7__data_i + assign $4\src17__data_o$next[3:0]$11819 \w7__data_i case - assign $4\src17__data_o$next[3:0]$11835 $3\src17__data_o$next[3:0]$11834 + assign $4\src17__data_o$next[3:0]$11819 $3\src17__data_o$next[3:0]$11818 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$3 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src17__data_o$next[3:0]$11836 \reg + assign $5\src17__data_o$next[3:0]$11820 \reg case - assign $5\src17__data_o$next[3:0]$11836 $4\src17__data_o$next[3:0]$11835 + assign $5\src17__data_o$next[3:0]$11820 $4\src17__data_o$next[3:0]$11819 end case - assign $1\src17__data_o$next[3:0]$11832 4'0000 + assign $1\src17__data_o$next[3:0]$11816 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src17__data_o$next[3:0]$11837 4'0000 + assign $6\src17__data_o$next[3:0]$11821 4'0000 case - assign $6\src17__data_o$next[3:0]$11837 $1\src17__data_o$next[3:0]$11832 + assign $6\src17__data_o$next[3:0]$11821 $1\src17__data_o$next[3:0]$11816 end sync always - update \src17__data_o$next $0\src17__data_o$next[3:0]$11831 + update \src17__data_o$next $0\src17__data_o$next[3:0]$11815 end - attribute \src "libresoc.v:183413.3-183442.6" - process $proc$libresoc.v:183413$11838 + attribute \src "libresoc.v:184721.3-184750.6" + process $proc$libresoc.v:184721$11822 assign { } { } assign { } { } - assign $0\wr_detect$4[0:0]$11839 $1\wr_detect$4[0:0]$11840 - attribute \src "libresoc.v:183414.5-183414.29" + assign $0\wr_detect$4[0:0]$11823 $1\wr_detect$4[0:0]$11824 + attribute \src "libresoc.v:184722.5-184722.29" switch \initial - attribute \src "libresoc.v:183414.9-183414.17" + attribute \src "libresoc.v:184722.9-184722.17" case 1'1 case end @@ -374565,49 +345935,49 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$4[0:0]$11840 $4\wr_detect$4[0:0]$11843 + assign $1\wr_detect$4[0:0]$11824 $4\wr_detect$4[0:0]$11827 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$4[0:0]$11841 1'1 + assign $2\wr_detect$4[0:0]$11825 1'1 case - assign $2\wr_detect$4[0:0]$11841 1'0 + assign $2\wr_detect$4[0:0]$11825 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$4[0:0]$11842 1'1 + assign $3\wr_detect$4[0:0]$11826 1'1 case - assign $3\wr_detect$4[0:0]$11842 $2\wr_detect$4[0:0]$11841 + assign $3\wr_detect$4[0:0]$11826 $2\wr_detect$4[0:0]$11825 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$4[0:0]$11843 1'1 + assign $4\wr_detect$4[0:0]$11827 1'1 case - assign $4\wr_detect$4[0:0]$11843 $3\wr_detect$4[0:0]$11842 + assign $4\wr_detect$4[0:0]$11827 $3\wr_detect$4[0:0]$11826 end case - assign $1\wr_detect$4[0:0]$11840 1'0 + assign $1\wr_detect$4[0:0]$11824 1'0 end sync always - update \wr_detect$4 $0\wr_detect$4[0:0]$11839 + update \wr_detect$4 $0\wr_detect$4[0:0]$11823 end - attribute \src "libresoc.v:183443.3-183482.6" - process $proc$libresoc.v:183443$11844 + attribute \src "libresoc.v:184751.3-184790.6" + process $proc$libresoc.v:184751$11828 assign { } { } assign { } { } assign { } { } - assign $0\src27__data_o$next[3:0]$11845 $6\src27__data_o$next[3:0]$11851 - attribute \src "libresoc.v:183444.5-183444.29" + assign $0\src27__data_o$next[3:0]$11829 $6\src27__data_o$next[3:0]$11835 + attribute \src "libresoc.v:184752.5-184752.29" switch \initial - attribute \src "libresoc.v:183444.9-183444.17" + attribute \src "libresoc.v:184752.9-184752.17" case 1'1 case end @@ -374619,66 +345989,66 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\src27__data_o$next[3:0]$11846 $5\src27__data_o$next[3:0]$11850 + assign $1\src27__data_o$next[3:0]$11830 $5\src27__data_o$next[3:0]$11834 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src27__data_o$next[3:0]$11847 \dest17__data_i + assign $2\src27__data_o$next[3:0]$11831 \dest17__data_i case - assign $2\src27__data_o$next[3:0]$11847 4'0000 + assign $2\src27__data_o$next[3:0]$11831 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src27__data_o$next[3:0]$11848 \dest27__data_i + assign $3\src27__data_o$next[3:0]$11832 \dest27__data_i case - assign $3\src27__data_o$next[3:0]$11848 $2\src27__data_o$next[3:0]$11847 + assign $3\src27__data_o$next[3:0]$11832 $2\src27__data_o$next[3:0]$11831 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src27__data_o$next[3:0]$11849 \w7__data_i + assign $4\src27__data_o$next[3:0]$11833 \w7__data_i case - assign $4\src27__data_o$next[3:0]$11849 $3\src27__data_o$next[3:0]$11848 + assign $4\src27__data_o$next[3:0]$11833 $3\src27__data_o$next[3:0]$11832 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$6 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src27__data_o$next[3:0]$11850 \reg + assign $5\src27__data_o$next[3:0]$11834 \reg case - assign $5\src27__data_o$next[3:0]$11850 $4\src27__data_o$next[3:0]$11849 + assign $5\src27__data_o$next[3:0]$11834 $4\src27__data_o$next[3:0]$11833 end case - assign $1\src27__data_o$next[3:0]$11846 4'0000 + assign $1\src27__data_o$next[3:0]$11830 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src27__data_o$next[3:0]$11851 4'0000 + assign $6\src27__data_o$next[3:0]$11835 4'0000 case - assign $6\src27__data_o$next[3:0]$11851 $1\src27__data_o$next[3:0]$11846 + assign $6\src27__data_o$next[3:0]$11835 $1\src27__data_o$next[3:0]$11830 end sync always - update \src27__data_o$next $0\src27__data_o$next[3:0]$11845 + update \src27__data_o$next $0\src27__data_o$next[3:0]$11829 end - attribute \src "libresoc.v:183483.3-183512.6" - process $proc$libresoc.v:183483$11852 + attribute \src "libresoc.v:184791.3-184820.6" + process $proc$libresoc.v:184791$11836 assign { } { } assign { } { } - assign $0\wr_detect$7[0:0]$11853 $1\wr_detect$7[0:0]$11854 - attribute \src "libresoc.v:183484.5-183484.29" + assign $0\wr_detect$7[0:0]$11837 $1\wr_detect$7[0:0]$11838 + attribute \src "libresoc.v:184792.5-184792.29" switch \initial - attribute \src "libresoc.v:183484.9-183484.17" + attribute \src "libresoc.v:184792.9-184792.17" case 1'1 case end @@ -374690,49 +346060,49 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$7[0:0]$11854 $4\wr_detect$7[0:0]$11857 + assign $1\wr_detect$7[0:0]$11838 $4\wr_detect$7[0:0]$11841 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$7[0:0]$11855 1'1 + assign $2\wr_detect$7[0:0]$11839 1'1 case - assign $2\wr_detect$7[0:0]$11855 1'0 + assign $2\wr_detect$7[0:0]$11839 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$7[0:0]$11856 1'1 + assign $3\wr_detect$7[0:0]$11840 1'1 case - assign $3\wr_detect$7[0:0]$11856 $2\wr_detect$7[0:0]$11855 + assign $3\wr_detect$7[0:0]$11840 $2\wr_detect$7[0:0]$11839 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$7[0:0]$11857 1'1 + assign $4\wr_detect$7[0:0]$11841 1'1 case - assign $4\wr_detect$7[0:0]$11857 $3\wr_detect$7[0:0]$11856 + assign $4\wr_detect$7[0:0]$11841 $3\wr_detect$7[0:0]$11840 end case - assign $1\wr_detect$7[0:0]$11854 1'0 + assign $1\wr_detect$7[0:0]$11838 1'0 end sync always - update \wr_detect$7 $0\wr_detect$7[0:0]$11853 + update \wr_detect$7 $0\wr_detect$7[0:0]$11837 end - attribute \src "libresoc.v:183513.3-183552.6" - process $proc$libresoc.v:183513$11858 + attribute \src "libresoc.v:184821.3-184860.6" + process $proc$libresoc.v:184821$11842 assign { } { } assign { } { } assign { } { } - assign $0\src37__data_o$next[3:0]$11859 $6\src37__data_o$next[3:0]$11865 - attribute \src "libresoc.v:183514.5-183514.29" + assign $0\src37__data_o$next[3:0]$11843 $6\src37__data_o$next[3:0]$11849 + attribute \src "libresoc.v:184822.5-184822.29" switch \initial - attribute \src "libresoc.v:183514.9-183514.17" + attribute \src "libresoc.v:184822.9-184822.17" case 1'1 case end @@ -374744,66 +346114,66 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\src37__data_o$next[3:0]$11860 $5\src37__data_o$next[3:0]$11864 + assign $1\src37__data_o$next[3:0]$11844 $5\src37__data_o$next[3:0]$11848 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\src37__data_o$next[3:0]$11861 \dest17__data_i + assign $2\src37__data_o$next[3:0]$11845 \dest17__data_i case - assign $2\src37__data_o$next[3:0]$11861 4'0000 + assign $2\src37__data_o$next[3:0]$11845 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\src37__data_o$next[3:0]$11862 \dest27__data_i + assign $3\src37__data_o$next[3:0]$11846 \dest27__data_i case - assign $3\src37__data_o$next[3:0]$11862 $2\src37__data_o$next[3:0]$11861 + assign $3\src37__data_o$next[3:0]$11846 $2\src37__data_o$next[3:0]$11845 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\src37__data_o$next[3:0]$11863 \w7__data_i + assign $4\src37__data_o$next[3:0]$11847 \w7__data_i case - assign $4\src37__data_o$next[3:0]$11863 $3\src37__data_o$next[3:0]$11862 + assign $4\src37__data_o$next[3:0]$11847 $3\src37__data_o$next[3:0]$11846 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$9 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\src37__data_o$next[3:0]$11864 \reg + assign $5\src37__data_o$next[3:0]$11848 \reg case - assign $5\src37__data_o$next[3:0]$11864 $4\src37__data_o$next[3:0]$11863 + assign $5\src37__data_o$next[3:0]$11848 $4\src37__data_o$next[3:0]$11847 end case - assign $1\src37__data_o$next[3:0]$11860 4'0000 + assign $1\src37__data_o$next[3:0]$11844 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\src37__data_o$next[3:0]$11865 4'0000 + assign $6\src37__data_o$next[3:0]$11849 4'0000 case - assign $6\src37__data_o$next[3:0]$11865 $1\src37__data_o$next[3:0]$11860 + assign $6\src37__data_o$next[3:0]$11849 $1\src37__data_o$next[3:0]$11844 end sync always - update \src37__data_o$next $0\src37__data_o$next[3:0]$11859 + update \src37__data_o$next $0\src37__data_o$next[3:0]$11843 end - attribute \src "libresoc.v:183553.3-183582.6" - process $proc$libresoc.v:183553$11866 + attribute \src "libresoc.v:184861.3-184890.6" + process $proc$libresoc.v:184861$11850 assign { } { } assign { } { } - assign $0\wr_detect$10[0:0]$11867 $1\wr_detect$10[0:0]$11868 - attribute \src "libresoc.v:183554.5-183554.29" + assign $0\wr_detect$10[0:0]$11851 $1\wr_detect$10[0:0]$11852 + attribute \src "libresoc.v:184862.5-184862.29" switch \initial - attribute \src "libresoc.v:183554.9-183554.17" + attribute \src "libresoc.v:184862.9-184862.17" case 1'1 case end @@ -374815,49 +346185,49 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$10[0:0]$11868 $4\wr_detect$10[0:0]$11871 + assign $1\wr_detect$10[0:0]$11852 $4\wr_detect$10[0:0]$11855 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$10[0:0]$11869 1'1 + assign $2\wr_detect$10[0:0]$11853 1'1 case - assign $2\wr_detect$10[0:0]$11869 1'0 + assign $2\wr_detect$10[0:0]$11853 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$10[0:0]$11870 1'1 + assign $3\wr_detect$10[0:0]$11854 1'1 case - assign $3\wr_detect$10[0:0]$11870 $2\wr_detect$10[0:0]$11869 + assign $3\wr_detect$10[0:0]$11854 $2\wr_detect$10[0:0]$11853 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$10[0:0]$11871 1'1 + assign $4\wr_detect$10[0:0]$11855 1'1 case - assign $4\wr_detect$10[0:0]$11871 $3\wr_detect$10[0:0]$11870 + assign $4\wr_detect$10[0:0]$11855 $3\wr_detect$10[0:0]$11854 end case - assign $1\wr_detect$10[0:0]$11868 1'0 + assign $1\wr_detect$10[0:0]$11852 1'0 end sync always - update \wr_detect$10 $0\wr_detect$10[0:0]$11867 + update \wr_detect$10 $0\wr_detect$10[0:0]$11851 end - attribute \src "libresoc.v:183583.3-183622.6" - process $proc$libresoc.v:183583$11872 + attribute \src "libresoc.v:184891.3-184930.6" + process $proc$libresoc.v:184891$11856 assign { } { } assign { } { } assign { } { } - assign $0\r7__data_o$next[3:0]$11873 $6\r7__data_o$next[3:0]$11879 - attribute \src "libresoc.v:183584.5-183584.29" + assign $0\r7__data_o$next[3:0]$11857 $6\r7__data_o$next[3:0]$11863 + attribute \src "libresoc.v:184892.5-184892.29" switch \initial - attribute \src "libresoc.v:183584.9-183584.17" + attribute \src "libresoc.v:184892.9-184892.17" case 1'1 case end @@ -374869,66 +346239,66 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\r7__data_o$next[3:0]$11874 $5\r7__data_o$next[3:0]$11878 + assign $1\r7__data_o$next[3:0]$11858 $5\r7__data_o$next[3:0]$11862 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\r7__data_o$next[3:0]$11875 \dest17__data_i + assign $2\r7__data_o$next[3:0]$11859 \dest17__data_i case - assign $2\r7__data_o$next[3:0]$11875 4'0000 + assign $2\r7__data_o$next[3:0]$11859 4'0000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\r7__data_o$next[3:0]$11876 \dest27__data_i + assign $3\r7__data_o$next[3:0]$11860 \dest27__data_i case - assign $3\r7__data_o$next[3:0]$11876 $2\r7__data_o$next[3:0]$11875 + assign $3\r7__data_o$next[3:0]$11860 $2\r7__data_o$next[3:0]$11859 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\r7__data_o$next[3:0]$11877 \w7__data_i + assign $4\r7__data_o$next[3:0]$11861 \w7__data_i case - assign $4\r7__data_o$next[3:0]$11877 $3\r7__data_o$next[3:0]$11876 + assign $4\r7__data_o$next[3:0]$11861 $3\r7__data_o$next[3:0]$11860 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" switch \$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\r7__data_o$next[3:0]$11878 \reg + assign $5\r7__data_o$next[3:0]$11862 \reg case - assign $5\r7__data_o$next[3:0]$11878 $4\r7__data_o$next[3:0]$11877 + assign $5\r7__data_o$next[3:0]$11862 $4\r7__data_o$next[3:0]$11861 end case - assign $1\r7__data_o$next[3:0]$11874 4'0000 + assign $1\r7__data_o$next[3:0]$11858 4'0000 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\r7__data_o$next[3:0]$11879 4'0000 + assign $6\r7__data_o$next[3:0]$11863 4'0000 case - assign $6\r7__data_o$next[3:0]$11879 $1\r7__data_o$next[3:0]$11874 + assign $6\r7__data_o$next[3:0]$11863 $1\r7__data_o$next[3:0]$11858 end sync always - update \r7__data_o$next $0\r7__data_o$next[3:0]$11873 + update \r7__data_o$next $0\r7__data_o$next[3:0]$11857 end - attribute \src "libresoc.v:183623.3-183652.6" - process $proc$libresoc.v:183623$11880 + attribute \src "libresoc.v:184931.3-184960.6" + process $proc$libresoc.v:184931$11864 assign { } { } assign { } { } - assign $0\wr_detect$13[0:0]$11881 $1\wr_detect$13[0:0]$11882 - attribute \src "libresoc.v:183624.5-183624.29" + assign $0\wr_detect$13[0:0]$11865 $1\wr_detect$13[0:0]$11866 + attribute \src "libresoc.v:184932.5-184932.29" switch \initial - attribute \src "libresoc.v:183624.9-183624.17" + attribute \src "libresoc.v:184932.9-184932.17" case 1'1 case end @@ -374940,78 +346310,78 @@ module \reg_7 assign { } { } assign { } { } assign { } { } - assign $1\wr_detect$13[0:0]$11882 $4\wr_detect$13[0:0]$11885 + assign $1\wr_detect$13[0:0]$11866 $4\wr_detect$13[0:0]$11869 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest17__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\wr_detect$13[0:0]$11883 1'1 + assign $2\wr_detect$13[0:0]$11867 1'1 case - assign $2\wr_detect$13[0:0]$11883 1'0 + assign $2\wr_detect$13[0:0]$11867 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \dest27__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\wr_detect$13[0:0]$11884 1'1 + assign $3\wr_detect$13[0:0]$11868 1'1 case - assign $3\wr_detect$13[0:0]$11884 $2\wr_detect$13[0:0]$11883 + assign $3\wr_detect$13[0:0]$11868 $2\wr_detect$13[0:0]$11867 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" switch \w7__wen attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\wr_detect$13[0:0]$11885 1'1 + assign $4\wr_detect$13[0:0]$11869 1'1 case - assign $4\wr_detect$13[0:0]$11885 $3\wr_detect$13[0:0]$11884 + assign $4\wr_detect$13[0:0]$11869 $3\wr_detect$13[0:0]$11868 end case - assign $1\wr_detect$13[0:0]$11882 1'0 + assign $1\wr_detect$13[0:0]$11866 1'0 end sync always - update \wr_detect$13 $0\wr_detect$13[0:0]$11881 + update \wr_detect$13 $0\wr_detect$13[0:0]$11865 end - connect \$9 $not$libresoc.v:183186$11788_Y - connect \$12 $not$libresoc.v:183187$11789_Y - connect \$15 $not$libresoc.v:183188$11790_Y - connect \$1 $not$libresoc.v:183189$11791_Y - connect \$3 $not$libresoc.v:183190$11792_Y - connect \$6 $not$libresoc.v:183191$11793_Y + connect \$9 $not$libresoc.v:184494$11772_Y + connect \$12 $not$libresoc.v:184495$11773_Y + connect \$15 $not$libresoc.v:184496$11774_Y + connect \$1 $not$libresoc.v:184497$11775_Y + connect \$3 $not$libresoc.v:184498$11776_Y + connect \$6 $not$libresoc.v:184499$11777_Y end -attribute \src "libresoc.v:183657.1-183715.10" +attribute \src "libresoc.v:184965.1-185023.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.req_l" attribute \generator "nMigen" module \req_l - attribute \src "libresoc.v:183658.7-183658.20" + attribute \src "libresoc.v:184966.7-184966.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183703.3-183711.6" - wire width 5 $0\q_int$next[4:0]$11904 - attribute \src "libresoc.v:183701.3-183702.27" + attribute \src "libresoc.v:185011.3-185019.6" + wire width 5 $0\q_int$next[4:0]$11888 + attribute \src "libresoc.v:185009.3-185010.27" wire width 5 $0\q_int[4:0] - attribute \src "libresoc.v:183703.3-183711.6" - wire width 5 $1\q_int$next[4:0]$11905 - attribute \src "libresoc.v:183680.13-183680.26" + attribute \src "libresoc.v:185011.3-185019.6" + wire width 5 $1\q_int$next[4:0]$11889 + attribute \src "libresoc.v:184988.13-184988.26" wire width 5 $1\q_int[4:0] - attribute \src "libresoc.v:183693.17-183693.96" - wire width 5 $and$libresoc.v:183693$11894_Y - attribute \src "libresoc.v:183698.17-183698.96" - wire width 5 $and$libresoc.v:183698$11899_Y - attribute \src "libresoc.v:183695.18-183695.93" - wire width 5 $not$libresoc.v:183695$11896_Y - attribute \src "libresoc.v:183697.17-183697.92" - wire width 5 $not$libresoc.v:183697$11898_Y - attribute \src "libresoc.v:183700.17-183700.92" - wire width 5 $not$libresoc.v:183700$11901_Y - attribute \src "libresoc.v:183694.18-183694.98" - wire width 5 $or$libresoc.v:183694$11895_Y - attribute \src "libresoc.v:183696.18-183696.99" - wire width 5 $or$libresoc.v:183696$11897_Y - attribute \src "libresoc.v:183699.17-183699.97" - wire width 5 $or$libresoc.v:183699$11900_Y + attribute \src "libresoc.v:185001.17-185001.96" + wire width 5 $and$libresoc.v:185001$11878_Y + attribute \src "libresoc.v:185006.17-185006.96" + wire width 5 $and$libresoc.v:185006$11883_Y + attribute \src "libresoc.v:185003.18-185003.93" + wire width 5 $not$libresoc.v:185003$11880_Y + attribute \src "libresoc.v:185005.17-185005.92" + wire width 5 $not$libresoc.v:185005$11882_Y + attribute \src "libresoc.v:185008.17-185008.92" + wire width 5 $not$libresoc.v:185008$11885_Y + attribute \src "libresoc.v:185002.18-185002.98" + wire width 5 $or$libresoc.v:185002$11879_Y + attribute \src "libresoc.v:185004.18-185004.99" + wire width 5 $or$libresoc.v:185004$11881_Y + attribute \src "libresoc.v:185007.17-185007.97" + wire width 5 $or$libresoc.v:185007$11884_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 5 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -375028,11 +346398,11 @@ module \req_l wire width 5 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 5 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:183658.7-183658.15" + attribute \src "libresoc.v:184966.7-184966.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 5 \q_int @@ -375049,7 +346419,7 @@ module \req_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 5 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:183693$11894 + cell $and $and$libresoc.v:185001$11878 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -375057,10 +346427,10 @@ module \req_l parameter \Y_WIDTH 5 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:183693$11894_Y + connect \Y $and$libresoc.v:185001$11878_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:183698$11899 + cell $and $and$libresoc.v:185006$11883 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -375068,34 +346438,34 @@ module \req_l parameter \Y_WIDTH 5 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:183698$11899_Y + connect \Y $and$libresoc.v:185006$11883_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:183695$11896 + cell $not $not$libresoc.v:185003$11880 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \q_req - connect \Y $not$libresoc.v:183695$11896_Y + connect \Y $not$libresoc.v:185003$11880_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:183697$11898 + cell $not $not$libresoc.v:185005$11882 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req - connect \Y $not$libresoc.v:183697$11898_Y + connect \Y $not$libresoc.v:185005$11882_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:183700$11901 + cell $not $not$libresoc.v:185008$11885 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req - connect \Y $not$libresoc.v:183700$11901_Y + connect \Y $not$libresoc.v:185008$11885_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:183694$11895 + cell $or $or$libresoc.v:185002$11879 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -375103,10 +346473,10 @@ module \req_l parameter \Y_WIDTH 5 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:183694$11895_Y + connect \Y $or$libresoc.v:185002$11879_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:183696$11897 + cell $or $or$libresoc.v:185004$11881 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -375114,10 +346484,10 @@ module \req_l parameter \Y_WIDTH 5 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:183696$11897_Y + connect \Y $or$libresoc.v:185004$11881_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:183699$11900 + cell $or $or$libresoc.v:185007$11884 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -375125,39 +346495,39 @@ module \req_l parameter \Y_WIDTH 5 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:183699$11900_Y + connect \Y $or$libresoc.v:185007$11884_Y end - attribute \src "libresoc.v:183658.7-183658.20" - process $proc$libresoc.v:183658$11906 + attribute \src "libresoc.v:184966.7-184966.20" + process $proc$libresoc.v:184966$11890 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183680.13-183680.26" - process $proc$libresoc.v:183680$11907 + attribute \src "libresoc.v:184988.13-184988.26" + process $proc$libresoc.v:184988$11891 assign { } { } assign $1\q_int[4:0] 5'00000 sync always sync init update \q_int $1\q_int[4:0] end - attribute \src "libresoc.v:183701.3-183702.27" - process $proc$libresoc.v:183701$11902 + attribute \src "libresoc.v:185009.3-185010.27" + process $proc$libresoc.v:185009$11886 assign { } { } assign $0\q_int[4:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[4:0] end - attribute \src "libresoc.v:183703.3-183711.6" - process $proc$libresoc.v:183703$11903 + attribute \src "libresoc.v:185011.3-185019.6" + process $proc$libresoc.v:185011$11887 assign { } { } assign { } { } - assign $0\q_int$next[4:0]$11904 $1\q_int$next[4:0]$11905 - attribute \src "libresoc.v:183704.5-183704.29" + assign $0\q_int$next[4:0]$11888 $1\q_int$next[4:0]$11889 + attribute \src "libresoc.v:185012.5-185012.29" switch \initial - attribute \src "libresoc.v:183704.9-183704.17" + attribute \src "libresoc.v:185012.9-185012.17" case 1'1 case end @@ -375166,56 +346536,56 @@ module \req_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[4:0]$11905 5'00000 + assign $1\q_int$next[4:0]$11889 5'00000 case - assign $1\q_int$next[4:0]$11905 \$5 + assign $1\q_int$next[4:0]$11889 \$5 end sync always - update \q_int$next $0\q_int$next[4:0]$11904 + update \q_int$next $0\q_int$next[4:0]$11888 end - connect \$9 $and$libresoc.v:183693$11894_Y - connect \$11 $or$libresoc.v:183694$11895_Y - connect \$13 $not$libresoc.v:183695$11896_Y - connect \$15 $or$libresoc.v:183696$11897_Y - connect \$1 $not$libresoc.v:183697$11898_Y - connect \$3 $and$libresoc.v:183698$11899_Y - connect \$5 $or$libresoc.v:183699$11900_Y - connect \$7 $not$libresoc.v:183700$11901_Y + connect \$9 $and$libresoc.v:185001$11878_Y + connect \$11 $or$libresoc.v:185002$11879_Y + connect \$13 $not$libresoc.v:185003$11880_Y + connect \$15 $or$libresoc.v:185004$11881_Y + connect \$1 $not$libresoc.v:185005$11882_Y + connect \$3 $and$libresoc.v:185006$11883_Y + connect \$5 $or$libresoc.v:185007$11884_Y + connect \$7 $not$libresoc.v:185008$11885_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:183719.1-183777.10" +attribute \src "libresoc.v:185027.1-185085.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.req_l" attribute \generator "nMigen" module \req_l$103 - attribute \src "libresoc.v:183720.7-183720.20" + attribute \src "libresoc.v:185028.7-185028.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183765.3-183773.6" - wire width 4 $0\q_int$next[3:0]$11918 - attribute \src "libresoc.v:183763.3-183764.27" + attribute \src "libresoc.v:185073.3-185081.6" + wire width 4 $0\q_int$next[3:0]$11902 + attribute \src "libresoc.v:185071.3-185072.27" wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:183765.3-183773.6" - wire width 4 $1\q_int$next[3:0]$11919 - attribute \src "libresoc.v:183742.13-183742.25" + attribute \src "libresoc.v:185073.3-185081.6" + wire width 4 $1\q_int$next[3:0]$11903 + attribute \src "libresoc.v:185050.13-185050.25" wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:183755.17-183755.96" - wire width 4 $and$libresoc.v:183755$11908_Y - attribute \src "libresoc.v:183760.17-183760.96" - wire width 4 $and$libresoc.v:183760$11913_Y - attribute \src "libresoc.v:183757.18-183757.93" - wire width 4 $not$libresoc.v:183757$11910_Y - attribute \src "libresoc.v:183759.17-183759.92" - wire width 4 $not$libresoc.v:183759$11912_Y - attribute \src "libresoc.v:183762.17-183762.92" - wire width 4 $not$libresoc.v:183762$11915_Y - attribute \src "libresoc.v:183756.18-183756.98" - wire width 4 $or$libresoc.v:183756$11909_Y - attribute \src "libresoc.v:183758.18-183758.99" - wire width 4 $or$libresoc.v:183758$11911_Y - attribute \src "libresoc.v:183761.17-183761.97" - wire width 4 $or$libresoc.v:183761$11914_Y + attribute \src "libresoc.v:185063.17-185063.96" + wire width 4 $and$libresoc.v:185063$11892_Y + attribute \src "libresoc.v:185068.17-185068.96" + wire width 4 $and$libresoc.v:185068$11897_Y + attribute \src "libresoc.v:185065.18-185065.93" + wire width 4 $not$libresoc.v:185065$11894_Y + attribute \src "libresoc.v:185067.17-185067.92" + wire width 4 $not$libresoc.v:185067$11896_Y + attribute \src "libresoc.v:185070.17-185070.92" + wire width 4 $not$libresoc.v:185070$11899_Y + attribute \src "libresoc.v:185064.18-185064.98" + wire width 4 $or$libresoc.v:185064$11893_Y + attribute \src "libresoc.v:185066.18-185066.99" + wire width 4 $or$libresoc.v:185066$11895_Y + attribute \src "libresoc.v:185069.17-185069.97" + wire width 4 $or$libresoc.v:185069$11898_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -375232,11 +346602,11 @@ module \req_l$103 wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:183720.7-183720.15" + attribute \src "libresoc.v:185028.7-185028.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int @@ -375253,7 +346623,7 @@ module \req_l$103 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:183755$11908 + cell $and $and$libresoc.v:185063$11892 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -375261,10 +346631,10 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:183755$11908_Y + connect \Y $and$libresoc.v:185063$11892_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:183760$11913 + cell $and $and$libresoc.v:185068$11897 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -375272,34 +346642,34 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:183760$11913_Y + connect \Y $and$libresoc.v:185068$11897_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:183757$11910 + cell $not $not$libresoc.v:185065$11894 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_req - connect \Y $not$libresoc.v:183757$11910_Y + connect \Y $not$libresoc.v:185065$11894_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:183759$11912 + cell $not $not$libresoc.v:185067$11896 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req - connect \Y $not$libresoc.v:183759$11912_Y + connect \Y $not$libresoc.v:185067$11896_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:183762$11915 + cell $not $not$libresoc.v:185070$11899 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req - connect \Y $not$libresoc.v:183762$11915_Y + connect \Y $not$libresoc.v:185070$11899_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:183756$11909 + cell $or $or$libresoc.v:185064$11893 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -375307,10 +346677,10 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:183756$11909_Y + connect \Y $or$libresoc.v:185064$11893_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:183758$11911 + cell $or $or$libresoc.v:185066$11895 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -375318,10 +346688,10 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:183758$11911_Y + connect \Y $or$libresoc.v:185066$11895_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:183761$11914 + cell $or $or$libresoc.v:185069$11898 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -375329,39 +346699,39 @@ module \req_l$103 parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:183761$11914_Y + connect \Y $or$libresoc.v:185069$11898_Y end - attribute \src "libresoc.v:183720.7-183720.20" - process $proc$libresoc.v:183720$11920 + attribute \src "libresoc.v:185028.7-185028.20" + process $proc$libresoc.v:185028$11904 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183742.13-183742.25" - process $proc$libresoc.v:183742$11921 + attribute \src "libresoc.v:185050.13-185050.25" + process $proc$libresoc.v:185050$11905 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end - attribute \src "libresoc.v:183763.3-183764.27" - process $proc$libresoc.v:183763$11916 + attribute \src "libresoc.v:185071.3-185072.27" + process $proc$libresoc.v:185071$11900 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end - attribute \src "libresoc.v:183765.3-183773.6" - process $proc$libresoc.v:183765$11917 + attribute \src "libresoc.v:185073.3-185081.6" + process $proc$libresoc.v:185073$11901 assign { } { } assign { } { } - assign $0\q_int$next[3:0]$11918 $1\q_int$next[3:0]$11919 - attribute \src "libresoc.v:183766.5-183766.29" + assign $0\q_int$next[3:0]$11902 $1\q_int$next[3:0]$11903 + attribute \src "libresoc.v:185074.5-185074.29" switch \initial - attribute \src "libresoc.v:183766.9-183766.17" + attribute \src "libresoc.v:185074.9-185074.17" case 1'1 case end @@ -375370,56 +346740,56 @@ module \req_l$103 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[3:0]$11919 4'0000 + assign $1\q_int$next[3:0]$11903 4'0000 case - assign $1\q_int$next[3:0]$11919 \$5 + assign $1\q_int$next[3:0]$11903 \$5 end sync always - update \q_int$next $0\q_int$next[3:0]$11918 + update \q_int$next $0\q_int$next[3:0]$11902 end - connect \$9 $and$libresoc.v:183755$11908_Y - connect \$11 $or$libresoc.v:183756$11909_Y - connect \$13 $not$libresoc.v:183757$11910_Y - connect \$15 $or$libresoc.v:183758$11911_Y - connect \$1 $not$libresoc.v:183759$11912_Y - connect \$3 $and$libresoc.v:183760$11913_Y - connect \$5 $or$libresoc.v:183761$11914_Y - connect \$7 $not$libresoc.v:183762$11915_Y + connect \$9 $and$libresoc.v:185063$11892_Y + connect \$11 $or$libresoc.v:185064$11893_Y + connect \$13 $not$libresoc.v:185065$11894_Y + connect \$15 $or$libresoc.v:185066$11895_Y + connect \$1 $not$libresoc.v:185067$11896_Y + connect \$3 $and$libresoc.v:185068$11897_Y + connect \$5 $or$libresoc.v:185069$11898_Y + connect \$7 $not$libresoc.v:185070$11899_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:183781.1-183839.10" +attribute \src "libresoc.v:185089.1-185147.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.req_l" attribute \generator "nMigen" module \req_l$12 - attribute \src "libresoc.v:183782.7-183782.20" + attribute \src "libresoc.v:185090.7-185090.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183827.3-183835.6" - wire width 3 $0\q_int$next[2:0]$11932 - attribute \src "libresoc.v:183825.3-183826.27" + attribute \src "libresoc.v:185135.3-185143.6" + wire width 3 $0\q_int$next[2:0]$11916 + attribute \src "libresoc.v:185133.3-185134.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:183827.3-183835.6" - wire width 3 $1\q_int$next[2:0]$11933 - attribute \src "libresoc.v:183804.13-183804.25" + attribute \src "libresoc.v:185135.3-185143.6" + wire width 3 $1\q_int$next[2:0]$11917 + attribute \src "libresoc.v:185112.13-185112.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:183817.17-183817.96" - wire width 3 $and$libresoc.v:183817$11922_Y - attribute \src "libresoc.v:183822.17-183822.96" - wire width 3 $and$libresoc.v:183822$11927_Y - attribute \src "libresoc.v:183819.18-183819.93" - wire width 3 $not$libresoc.v:183819$11924_Y - attribute \src "libresoc.v:183821.17-183821.92" - wire width 3 $not$libresoc.v:183821$11926_Y - attribute \src "libresoc.v:183824.17-183824.92" - wire width 3 $not$libresoc.v:183824$11929_Y - attribute \src "libresoc.v:183818.18-183818.98" - wire width 3 $or$libresoc.v:183818$11923_Y - attribute \src "libresoc.v:183820.18-183820.99" - wire width 3 $or$libresoc.v:183820$11925_Y - attribute \src "libresoc.v:183823.17-183823.97" - wire width 3 $or$libresoc.v:183823$11928_Y + attribute \src "libresoc.v:185125.17-185125.96" + wire width 3 $and$libresoc.v:185125$11906_Y + attribute \src "libresoc.v:185130.17-185130.96" + wire width 3 $and$libresoc.v:185130$11911_Y + attribute \src "libresoc.v:185127.18-185127.93" + wire width 3 $not$libresoc.v:185127$11908_Y + attribute \src "libresoc.v:185129.17-185129.92" + wire width 3 $not$libresoc.v:185129$11910_Y + attribute \src "libresoc.v:185132.17-185132.92" + wire width 3 $not$libresoc.v:185132$11913_Y + attribute \src "libresoc.v:185126.18-185126.98" + wire width 3 $or$libresoc.v:185126$11907_Y + attribute \src "libresoc.v:185128.18-185128.99" + wire width 3 $or$libresoc.v:185128$11909_Y + attribute \src "libresoc.v:185131.17-185131.97" + wire width 3 $or$libresoc.v:185131$11912_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -375436,11 +346806,11 @@ module \req_l$12 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:183782.7-183782.15" + attribute \src "libresoc.v:185090.7-185090.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -375457,7 +346827,7 @@ module \req_l$12 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:183817$11922 + cell $and $and$libresoc.v:185125$11906 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -375465,10 +346835,10 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:183817$11922_Y + connect \Y $and$libresoc.v:185125$11906_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:183822$11927 + cell $and $and$libresoc.v:185130$11911 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -375476,34 +346846,34 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:183822$11927_Y + connect \Y $and$libresoc.v:185130$11911_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:183819$11924 + cell $not $not$libresoc.v:185127$11908 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_req - connect \Y $not$libresoc.v:183819$11924_Y + connect \Y $not$libresoc.v:185127$11908_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:183821$11926 + cell $not $not$libresoc.v:185129$11910 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:183821$11926_Y + connect \Y $not$libresoc.v:185129$11910_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:183824$11929 + cell $not $not$libresoc.v:185132$11913 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:183824$11929_Y + connect \Y $not$libresoc.v:185132$11913_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:183818$11923 + cell $or $or$libresoc.v:185126$11907 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -375511,10 +346881,10 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:183818$11923_Y + connect \Y $or$libresoc.v:185126$11907_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:183820$11925 + cell $or $or$libresoc.v:185128$11909 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -375522,10 +346892,10 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:183820$11925_Y + connect \Y $or$libresoc.v:185128$11909_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:183823$11928 + cell $or $or$libresoc.v:185131$11912 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -375533,39 +346903,39 @@ module \req_l$12 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:183823$11928_Y + connect \Y $or$libresoc.v:185131$11912_Y end - attribute \src "libresoc.v:183782.7-183782.20" - process $proc$libresoc.v:183782$11934 + attribute \src "libresoc.v:185090.7-185090.20" + process $proc$libresoc.v:185090$11918 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183804.13-183804.25" - process $proc$libresoc.v:183804$11935 + attribute \src "libresoc.v:185112.13-185112.25" + process $proc$libresoc.v:185112$11919 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:183825.3-183826.27" - process $proc$libresoc.v:183825$11930 + attribute \src "libresoc.v:185133.3-185134.27" + process $proc$libresoc.v:185133$11914 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:183827.3-183835.6" - process $proc$libresoc.v:183827$11931 + attribute \src "libresoc.v:185135.3-185143.6" + process $proc$libresoc.v:185135$11915 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$11932 $1\q_int$next[2:0]$11933 - attribute \src "libresoc.v:183828.5-183828.29" + assign $0\q_int$next[2:0]$11916 $1\q_int$next[2:0]$11917 + attribute \src "libresoc.v:185136.5-185136.29" switch \initial - attribute \src "libresoc.v:183828.9-183828.17" + attribute \src "libresoc.v:185136.9-185136.17" case 1'1 case end @@ -375574,56 +346944,56 @@ module \req_l$12 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$11933 3'000 + assign $1\q_int$next[2:0]$11917 3'000 case - assign $1\q_int$next[2:0]$11933 \$5 + assign $1\q_int$next[2:0]$11917 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$11932 + update \q_int$next $0\q_int$next[2:0]$11916 end - connect \$9 $and$libresoc.v:183817$11922_Y - connect \$11 $or$libresoc.v:183818$11923_Y - connect \$13 $not$libresoc.v:183819$11924_Y - connect \$15 $or$libresoc.v:183820$11925_Y - connect \$1 $not$libresoc.v:183821$11926_Y - connect \$3 $and$libresoc.v:183822$11927_Y - connect \$5 $or$libresoc.v:183823$11928_Y - connect \$7 $not$libresoc.v:183824$11929_Y + connect \$9 $and$libresoc.v:185125$11906_Y + connect \$11 $or$libresoc.v:185126$11907_Y + connect \$13 $not$libresoc.v:185127$11908_Y + connect \$15 $or$libresoc.v:185128$11909_Y + connect \$1 $not$libresoc.v:185129$11910_Y + connect \$3 $and$libresoc.v:185130$11911_Y + connect \$5 $or$libresoc.v:185131$11912_Y + connect \$7 $not$libresoc.v:185132$11913_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:183843.1-183901.10" +attribute \src "libresoc.v:185151.1-185209.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.req_l" attribute \generator "nMigen" module \req_l$121 - attribute \src "libresoc.v:183844.7-183844.20" + attribute \src "libresoc.v:185152.7-185152.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183889.3-183897.6" - wire width 3 $0\q_int$next[2:0]$11946 - attribute \src "libresoc.v:183887.3-183888.27" + attribute \src "libresoc.v:185197.3-185205.6" + wire width 3 $0\q_int$next[2:0]$11930 + attribute \src "libresoc.v:185195.3-185196.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:183889.3-183897.6" - wire width 3 $1\q_int$next[2:0]$11947 - attribute \src "libresoc.v:183866.13-183866.25" + attribute \src "libresoc.v:185197.3-185205.6" + wire width 3 $1\q_int$next[2:0]$11931 + attribute \src "libresoc.v:185174.13-185174.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:183879.17-183879.96" - wire width 3 $and$libresoc.v:183879$11936_Y - attribute \src "libresoc.v:183884.17-183884.96" - wire width 3 $and$libresoc.v:183884$11941_Y - attribute \src "libresoc.v:183881.18-183881.93" - wire width 3 $not$libresoc.v:183881$11938_Y - attribute \src "libresoc.v:183883.17-183883.92" - wire width 3 $not$libresoc.v:183883$11940_Y - attribute \src "libresoc.v:183886.17-183886.92" - wire width 3 $not$libresoc.v:183886$11943_Y - attribute \src "libresoc.v:183880.18-183880.98" - wire width 3 $or$libresoc.v:183880$11937_Y - attribute \src "libresoc.v:183882.18-183882.99" - wire width 3 $or$libresoc.v:183882$11939_Y - attribute \src "libresoc.v:183885.17-183885.97" - wire width 3 $or$libresoc.v:183885$11942_Y + attribute \src "libresoc.v:185187.17-185187.96" + wire width 3 $and$libresoc.v:185187$11920_Y + attribute \src "libresoc.v:185192.17-185192.96" + wire width 3 $and$libresoc.v:185192$11925_Y + attribute \src "libresoc.v:185189.18-185189.93" + wire width 3 $not$libresoc.v:185189$11922_Y + attribute \src "libresoc.v:185191.17-185191.92" + wire width 3 $not$libresoc.v:185191$11924_Y + attribute \src "libresoc.v:185194.17-185194.92" + wire width 3 $not$libresoc.v:185194$11927_Y + attribute \src "libresoc.v:185188.18-185188.98" + wire width 3 $or$libresoc.v:185188$11921_Y + attribute \src "libresoc.v:185190.18-185190.99" + wire width 3 $or$libresoc.v:185190$11923_Y + attribute \src "libresoc.v:185193.17-185193.97" + wire width 3 $or$libresoc.v:185193$11926_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -375640,11 +347010,11 @@ module \req_l$121 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:183844.7-183844.15" + attribute \src "libresoc.v:185152.7-185152.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -375661,7 +347031,7 @@ module \req_l$121 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:183879$11936 + cell $and $and$libresoc.v:185187$11920 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -375669,10 +347039,10 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:183879$11936_Y + connect \Y $and$libresoc.v:185187$11920_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:183884$11941 + cell $and $and$libresoc.v:185192$11925 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -375680,34 +347050,34 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:183884$11941_Y + connect \Y $and$libresoc.v:185192$11925_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:183881$11938 + cell $not $not$libresoc.v:185189$11922 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_req - connect \Y $not$libresoc.v:183881$11938_Y + connect \Y $not$libresoc.v:185189$11922_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:183883$11940 + cell $not $not$libresoc.v:185191$11924 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:183883$11940_Y + connect \Y $not$libresoc.v:185191$11924_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:183886$11943 + cell $not $not$libresoc.v:185194$11927 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:183886$11943_Y + connect \Y $not$libresoc.v:185194$11927_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:183880$11937 + cell $or $or$libresoc.v:185188$11921 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -375715,10 +347085,10 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:183880$11937_Y + connect \Y $or$libresoc.v:185188$11921_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:183882$11939 + cell $or $or$libresoc.v:185190$11923 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -375726,10 +347096,10 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:183882$11939_Y + connect \Y $or$libresoc.v:185190$11923_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:183885$11942 + cell $or $or$libresoc.v:185193$11926 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -375737,39 +347107,39 @@ module \req_l$121 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:183885$11942_Y + connect \Y $or$libresoc.v:185193$11926_Y end - attribute \src "libresoc.v:183844.7-183844.20" - process $proc$libresoc.v:183844$11948 + attribute \src "libresoc.v:185152.7-185152.20" + process $proc$libresoc.v:185152$11932 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183866.13-183866.25" - process $proc$libresoc.v:183866$11949 + attribute \src "libresoc.v:185174.13-185174.25" + process $proc$libresoc.v:185174$11933 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:183887.3-183888.27" - process $proc$libresoc.v:183887$11944 + attribute \src "libresoc.v:185195.3-185196.27" + process $proc$libresoc.v:185195$11928 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:183889.3-183897.6" - process $proc$libresoc.v:183889$11945 + attribute \src "libresoc.v:185197.3-185205.6" + process $proc$libresoc.v:185197$11929 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$11946 $1\q_int$next[2:0]$11947 - attribute \src "libresoc.v:183890.5-183890.29" + assign $0\q_int$next[2:0]$11930 $1\q_int$next[2:0]$11931 + attribute \src "libresoc.v:185198.5-185198.29" switch \initial - attribute \src "libresoc.v:183890.9-183890.17" + attribute \src "libresoc.v:185198.9-185198.17" case 1'1 case end @@ -375778,56 +347148,56 @@ module \req_l$121 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$11947 3'000 + assign $1\q_int$next[2:0]$11931 3'000 case - assign $1\q_int$next[2:0]$11947 \$5 + assign $1\q_int$next[2:0]$11931 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$11946 + update \q_int$next $0\q_int$next[2:0]$11930 end - connect \$9 $and$libresoc.v:183879$11936_Y - connect \$11 $or$libresoc.v:183880$11937_Y - connect \$13 $not$libresoc.v:183881$11938_Y - connect \$15 $or$libresoc.v:183882$11939_Y - connect \$1 $not$libresoc.v:183883$11940_Y - connect \$3 $and$libresoc.v:183884$11941_Y - connect \$5 $or$libresoc.v:183885$11942_Y - connect \$7 $not$libresoc.v:183886$11943_Y + connect \$9 $and$libresoc.v:185187$11920_Y + connect \$11 $or$libresoc.v:185188$11921_Y + connect \$13 $not$libresoc.v:185189$11922_Y + connect \$15 $or$libresoc.v:185190$11923_Y + connect \$1 $not$libresoc.v:185191$11924_Y + connect \$3 $and$libresoc.v:185192$11925_Y + connect \$5 $or$libresoc.v:185193$11926_Y + connect \$7 $not$libresoc.v:185194$11927_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:183905.1-183963.10" +attribute \src "libresoc.v:185213.1-185271.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.req_l" attribute \generator "nMigen" module \req_l$25 - attribute \src "libresoc.v:183906.7-183906.20" + attribute \src "libresoc.v:185214.7-185214.20" wire $0\initial[0:0] - attribute \src "libresoc.v:183951.3-183959.6" - wire width 3 $0\q_int$next[2:0]$11960 - attribute \src "libresoc.v:183949.3-183950.27" + attribute \src "libresoc.v:185259.3-185267.6" + wire width 3 $0\q_int$next[2:0]$11944 + attribute \src "libresoc.v:185257.3-185258.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:183951.3-183959.6" - wire width 3 $1\q_int$next[2:0]$11961 - attribute \src "libresoc.v:183928.13-183928.25" + attribute \src "libresoc.v:185259.3-185267.6" + wire width 3 $1\q_int$next[2:0]$11945 + attribute \src "libresoc.v:185236.13-185236.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:183941.17-183941.96" - wire width 3 $and$libresoc.v:183941$11950_Y - attribute \src "libresoc.v:183946.17-183946.96" - wire width 3 $and$libresoc.v:183946$11955_Y - attribute \src "libresoc.v:183943.18-183943.93" - wire width 3 $not$libresoc.v:183943$11952_Y - attribute \src "libresoc.v:183945.17-183945.92" - wire width 3 $not$libresoc.v:183945$11954_Y - attribute \src "libresoc.v:183948.17-183948.92" - wire width 3 $not$libresoc.v:183948$11957_Y - attribute \src "libresoc.v:183942.18-183942.98" - wire width 3 $or$libresoc.v:183942$11951_Y - attribute \src "libresoc.v:183944.18-183944.99" - wire width 3 $or$libresoc.v:183944$11953_Y - attribute \src "libresoc.v:183947.17-183947.97" - wire width 3 $or$libresoc.v:183947$11956_Y + attribute \src "libresoc.v:185249.17-185249.96" + wire width 3 $and$libresoc.v:185249$11934_Y + attribute \src "libresoc.v:185254.17-185254.96" + wire width 3 $and$libresoc.v:185254$11939_Y + attribute \src "libresoc.v:185251.18-185251.93" + wire width 3 $not$libresoc.v:185251$11936_Y + attribute \src "libresoc.v:185253.17-185253.92" + wire width 3 $not$libresoc.v:185253$11938_Y + attribute \src "libresoc.v:185256.17-185256.92" + wire width 3 $not$libresoc.v:185256$11941_Y + attribute \src "libresoc.v:185250.18-185250.98" + wire width 3 $or$libresoc.v:185250$11935_Y + attribute \src "libresoc.v:185252.18-185252.99" + wire width 3 $or$libresoc.v:185252$11937_Y + attribute \src "libresoc.v:185255.17-185255.97" + wire width 3 $or$libresoc.v:185255$11940_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -375844,11 +347214,11 @@ module \req_l$25 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:183906.7-183906.15" + attribute \src "libresoc.v:185214.7-185214.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -375865,7 +347235,7 @@ module \req_l$25 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:183941$11950 + cell $and $and$libresoc.v:185249$11934 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -375873,10 +347243,10 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:183941$11950_Y + connect \Y $and$libresoc.v:185249$11934_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:183946$11955 + cell $and $and$libresoc.v:185254$11939 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -375884,34 +347254,34 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:183946$11955_Y + connect \Y $and$libresoc.v:185254$11939_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:183943$11952 + cell $not $not$libresoc.v:185251$11936 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_req - connect \Y $not$libresoc.v:183943$11952_Y + connect \Y $not$libresoc.v:185251$11936_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:183945$11954 + cell $not $not$libresoc.v:185253$11938 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:183945$11954_Y + connect \Y $not$libresoc.v:185253$11938_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:183948$11957 + cell $not $not$libresoc.v:185256$11941 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_req - connect \Y $not$libresoc.v:183948$11957_Y + connect \Y $not$libresoc.v:185256$11941_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:183942$11951 + cell $or $or$libresoc.v:185250$11935 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -375919,10 +347289,10 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:183942$11951_Y + connect \Y $or$libresoc.v:185250$11935_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:183944$11953 + cell $or $or$libresoc.v:185252$11937 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -375930,10 +347300,10 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:183944$11953_Y + connect \Y $or$libresoc.v:185252$11937_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:183947$11956 + cell $or $or$libresoc.v:185255$11940 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -375941,39 +347311,39 @@ module \req_l$25 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:183947$11956_Y + connect \Y $or$libresoc.v:185255$11940_Y end - attribute \src "libresoc.v:183906.7-183906.20" - process $proc$libresoc.v:183906$11962 + attribute \src "libresoc.v:185214.7-185214.20" + process $proc$libresoc.v:185214$11946 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183928.13-183928.25" - process $proc$libresoc.v:183928$11963 + attribute \src "libresoc.v:185236.13-185236.25" + process $proc$libresoc.v:185236$11947 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:183949.3-183950.27" - process $proc$libresoc.v:183949$11958 + attribute \src "libresoc.v:185257.3-185258.27" + process $proc$libresoc.v:185257$11942 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:183951.3-183959.6" - process $proc$libresoc.v:183951$11959 + attribute \src "libresoc.v:185259.3-185267.6" + process $proc$libresoc.v:185259$11943 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$11960 $1\q_int$next[2:0]$11961 - attribute \src "libresoc.v:183952.5-183952.29" + assign $0\q_int$next[2:0]$11944 $1\q_int$next[2:0]$11945 + attribute \src "libresoc.v:185260.5-185260.29" switch \initial - attribute \src "libresoc.v:183952.9-183952.17" + attribute \src "libresoc.v:185260.9-185260.17" case 1'1 case end @@ -375982,56 +347352,56 @@ module \req_l$25 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$11961 3'000 + assign $1\q_int$next[2:0]$11945 3'000 case - assign $1\q_int$next[2:0]$11961 \$5 + assign $1\q_int$next[2:0]$11945 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$11960 + update \q_int$next $0\q_int$next[2:0]$11944 end - connect \$9 $and$libresoc.v:183941$11950_Y - connect \$11 $or$libresoc.v:183942$11951_Y - connect \$13 $not$libresoc.v:183943$11952_Y - connect \$15 $or$libresoc.v:183944$11953_Y - connect \$1 $not$libresoc.v:183945$11954_Y - connect \$3 $and$libresoc.v:183946$11955_Y - connect \$5 $or$libresoc.v:183947$11956_Y - connect \$7 $not$libresoc.v:183948$11957_Y + connect \$9 $and$libresoc.v:185249$11934_Y + connect \$11 $or$libresoc.v:185250$11935_Y + connect \$13 $not$libresoc.v:185251$11936_Y + connect \$15 $or$libresoc.v:185252$11937_Y + connect \$1 $not$libresoc.v:185253$11938_Y + connect \$3 $and$libresoc.v:185254$11939_Y + connect \$5 $or$libresoc.v:185255$11940_Y + connect \$7 $not$libresoc.v:185256$11941_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:183967.1-184025.10" +attribute \src "libresoc.v:185275.1-185333.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.req_l" attribute \generator "nMigen" module \req_l$41 - attribute \src "libresoc.v:183968.7-183968.20" + attribute \src "libresoc.v:185276.7-185276.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184013.3-184021.6" - wire width 5 $0\q_int$next[4:0]$11974 - attribute \src "libresoc.v:184011.3-184012.27" + attribute \src "libresoc.v:185321.3-185329.6" + wire width 5 $0\q_int$next[4:0]$11958 + attribute \src "libresoc.v:185319.3-185320.27" wire width 5 $0\q_int[4:0] - attribute \src "libresoc.v:184013.3-184021.6" - wire width 5 $1\q_int$next[4:0]$11975 - attribute \src "libresoc.v:183990.13-183990.26" + attribute \src "libresoc.v:185321.3-185329.6" + wire width 5 $1\q_int$next[4:0]$11959 + attribute \src "libresoc.v:185298.13-185298.26" wire width 5 $1\q_int[4:0] - attribute \src "libresoc.v:184003.17-184003.96" - wire width 5 $and$libresoc.v:184003$11964_Y - attribute \src "libresoc.v:184008.17-184008.96" - wire width 5 $and$libresoc.v:184008$11969_Y - attribute \src "libresoc.v:184005.18-184005.93" - wire width 5 $not$libresoc.v:184005$11966_Y - attribute \src "libresoc.v:184007.17-184007.92" - wire width 5 $not$libresoc.v:184007$11968_Y - attribute \src "libresoc.v:184010.17-184010.92" - wire width 5 $not$libresoc.v:184010$11971_Y - attribute \src "libresoc.v:184004.18-184004.98" - wire width 5 $or$libresoc.v:184004$11965_Y - attribute \src "libresoc.v:184006.18-184006.99" - wire width 5 $or$libresoc.v:184006$11967_Y - attribute \src "libresoc.v:184009.17-184009.97" - wire width 5 $or$libresoc.v:184009$11970_Y + attribute \src "libresoc.v:185311.17-185311.96" + wire width 5 $and$libresoc.v:185311$11948_Y + attribute \src "libresoc.v:185316.17-185316.96" + wire width 5 $and$libresoc.v:185316$11953_Y + attribute \src "libresoc.v:185313.18-185313.93" + wire width 5 $not$libresoc.v:185313$11950_Y + attribute \src "libresoc.v:185315.17-185315.92" + wire width 5 $not$libresoc.v:185315$11952_Y + attribute \src "libresoc.v:185318.17-185318.92" + wire width 5 $not$libresoc.v:185318$11955_Y + attribute \src "libresoc.v:185312.18-185312.98" + wire width 5 $or$libresoc.v:185312$11949_Y + attribute \src "libresoc.v:185314.18-185314.99" + wire width 5 $or$libresoc.v:185314$11951_Y + attribute \src "libresoc.v:185317.17-185317.97" + wire width 5 $or$libresoc.v:185317$11954_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 5 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -376048,11 +347418,11 @@ module \req_l$41 wire width 5 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 5 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:183968.7-183968.15" + attribute \src "libresoc.v:185276.7-185276.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 5 \q_int @@ -376069,7 +347439,7 @@ module \req_l$41 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 5 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:184003$11964 + cell $and $and$libresoc.v:185311$11948 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -376077,10 +347447,10 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:184003$11964_Y + connect \Y $and$libresoc.v:185311$11948_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:184008$11969 + cell $and $and$libresoc.v:185316$11953 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -376088,34 +347458,34 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:184008$11969_Y + connect \Y $and$libresoc.v:185316$11953_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:184005$11966 + cell $not $not$libresoc.v:185313$11950 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \q_req - connect \Y $not$libresoc.v:184005$11966_Y + connect \Y $not$libresoc.v:185313$11950_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:184007$11968 + cell $not $not$libresoc.v:185315$11952 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req - connect \Y $not$libresoc.v:184007$11968_Y + connect \Y $not$libresoc.v:185315$11952_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:184010$11971 + cell $not $not$libresoc.v:185318$11955 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_req - connect \Y $not$libresoc.v:184010$11971_Y + connect \Y $not$libresoc.v:185318$11955_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:184004$11965 + cell $or $or$libresoc.v:185312$11949 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -376123,10 +347493,10 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:184004$11965_Y + connect \Y $or$libresoc.v:185312$11949_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:184006$11967 + cell $or $or$libresoc.v:185314$11951 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -376134,10 +347504,10 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:184006$11967_Y + connect \Y $or$libresoc.v:185314$11951_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:184009$11970 + cell $or $or$libresoc.v:185317$11954 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -376145,39 +347515,39 @@ module \req_l$41 parameter \Y_WIDTH 5 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:184009$11970_Y + connect \Y $or$libresoc.v:185317$11954_Y end - attribute \src "libresoc.v:183968.7-183968.20" - process $proc$libresoc.v:183968$11976 + attribute \src "libresoc.v:185276.7-185276.20" + process $proc$libresoc.v:185276$11960 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:183990.13-183990.26" - process $proc$libresoc.v:183990$11977 + attribute \src "libresoc.v:185298.13-185298.26" + process $proc$libresoc.v:185298$11961 assign { } { } assign $1\q_int[4:0] 5'00000 sync always sync init update \q_int $1\q_int[4:0] end - attribute \src "libresoc.v:184011.3-184012.27" - process $proc$libresoc.v:184011$11972 + attribute \src "libresoc.v:185319.3-185320.27" + process $proc$libresoc.v:185319$11956 assign { } { } assign $0\q_int[4:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[4:0] end - attribute \src "libresoc.v:184013.3-184021.6" - process $proc$libresoc.v:184013$11973 + attribute \src "libresoc.v:185321.3-185329.6" + process $proc$libresoc.v:185321$11957 assign { } { } assign { } { } - assign $0\q_int$next[4:0]$11974 $1\q_int$next[4:0]$11975 - attribute \src "libresoc.v:184014.5-184014.29" + assign $0\q_int$next[4:0]$11958 $1\q_int$next[4:0]$11959 + attribute \src "libresoc.v:185322.5-185322.29" switch \initial - attribute \src "libresoc.v:184014.9-184014.17" + attribute \src "libresoc.v:185322.9-185322.17" case 1'1 case end @@ -376186,56 +347556,56 @@ module \req_l$41 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[4:0]$11975 5'00000 + assign $1\q_int$next[4:0]$11959 5'00000 case - assign $1\q_int$next[4:0]$11975 \$5 + assign $1\q_int$next[4:0]$11959 \$5 end sync always - update \q_int$next $0\q_int$next[4:0]$11974 + update \q_int$next $0\q_int$next[4:0]$11958 end - connect \$9 $and$libresoc.v:184003$11964_Y - connect \$11 $or$libresoc.v:184004$11965_Y - connect \$13 $not$libresoc.v:184005$11966_Y - connect \$15 $or$libresoc.v:184006$11967_Y - connect \$1 $not$libresoc.v:184007$11968_Y - connect \$3 $and$libresoc.v:184008$11969_Y - connect \$5 $or$libresoc.v:184009$11970_Y - connect \$7 $not$libresoc.v:184010$11971_Y + connect \$9 $and$libresoc.v:185311$11948_Y + connect \$11 $or$libresoc.v:185312$11949_Y + connect \$13 $not$libresoc.v:185313$11950_Y + connect \$15 $or$libresoc.v:185314$11951_Y + connect \$1 $not$libresoc.v:185315$11952_Y + connect \$3 $and$libresoc.v:185316$11953_Y + connect \$5 $or$libresoc.v:185317$11954_Y + connect \$7 $not$libresoc.v:185318$11955_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:184029.1-184087.10" +attribute \src "libresoc.v:185337.1-185395.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.req_l" attribute \generator "nMigen" module \req_l$57 - attribute \src "libresoc.v:184030.7-184030.20" + attribute \src "libresoc.v:185338.7-185338.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184075.3-184083.6" - wire width 2 $0\q_int$next[1:0]$11988 - attribute \src "libresoc.v:184073.3-184074.27" + attribute \src "libresoc.v:185383.3-185391.6" + wire width 2 $0\q_int$next[1:0]$11972 + attribute \src "libresoc.v:185381.3-185382.27" wire width 2 $0\q_int[1:0] - attribute \src "libresoc.v:184075.3-184083.6" - wire width 2 $1\q_int$next[1:0]$11989 - attribute \src "libresoc.v:184052.13-184052.25" + attribute \src "libresoc.v:185383.3-185391.6" + wire width 2 $1\q_int$next[1:0]$11973 + attribute \src "libresoc.v:185360.13-185360.25" wire width 2 $1\q_int[1:0] - attribute \src "libresoc.v:184065.17-184065.96" - wire width 2 $and$libresoc.v:184065$11978_Y - attribute \src "libresoc.v:184070.17-184070.96" - wire width 2 $and$libresoc.v:184070$11983_Y - attribute \src "libresoc.v:184067.18-184067.93" - wire width 2 $not$libresoc.v:184067$11980_Y - attribute \src "libresoc.v:184069.17-184069.92" - wire width 2 $not$libresoc.v:184069$11982_Y - attribute \src "libresoc.v:184072.17-184072.92" - wire width 2 $not$libresoc.v:184072$11985_Y - attribute \src "libresoc.v:184066.18-184066.98" - wire width 2 $or$libresoc.v:184066$11979_Y - attribute \src "libresoc.v:184068.18-184068.99" - wire width 2 $or$libresoc.v:184068$11981_Y - attribute \src "libresoc.v:184071.17-184071.97" - wire width 2 $or$libresoc.v:184071$11984_Y + attribute \src "libresoc.v:185373.17-185373.96" + wire width 2 $and$libresoc.v:185373$11962_Y + attribute \src "libresoc.v:185378.17-185378.96" + wire width 2 $and$libresoc.v:185378$11967_Y + attribute \src "libresoc.v:185375.18-185375.93" + wire width 2 $not$libresoc.v:185375$11964_Y + attribute \src "libresoc.v:185377.17-185377.92" + wire width 2 $not$libresoc.v:185377$11966_Y + attribute \src "libresoc.v:185380.17-185380.92" + wire width 2 $not$libresoc.v:185380$11969_Y + attribute \src "libresoc.v:185374.18-185374.98" + wire width 2 $or$libresoc.v:185374$11963_Y + attribute \src "libresoc.v:185376.18-185376.99" + wire width 2 $or$libresoc.v:185376$11965_Y + attribute \src "libresoc.v:185379.17-185379.97" + wire width 2 $or$libresoc.v:185379$11968_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -376252,11 +347622,11 @@ module \req_l$57 wire width 2 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 2 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:184030.7-184030.15" + attribute \src "libresoc.v:185338.7-185338.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 2 \q_int @@ -376273,7 +347643,7 @@ module \req_l$57 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 2 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:184065$11978 + cell $and $and$libresoc.v:185373$11962 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -376281,10 +347651,10 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:184065$11978_Y + connect \Y $and$libresoc.v:185373$11962_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:184070$11983 + cell $and $and$libresoc.v:185378$11967 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -376292,34 +347662,34 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:184070$11983_Y + connect \Y $and$libresoc.v:185378$11967_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:184067$11980 + cell $not $not$libresoc.v:185375$11964 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \q_req - connect \Y $not$libresoc.v:184067$11980_Y + connect \Y $not$libresoc.v:185375$11964_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:184069$11982 + cell $not $not$libresoc.v:185377$11966 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \r_req - connect \Y $not$libresoc.v:184069$11982_Y + connect \Y $not$libresoc.v:185377$11966_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:184072$11985 + cell $not $not$libresoc.v:185380$11969 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \r_req - connect \Y $not$libresoc.v:184072$11985_Y + connect \Y $not$libresoc.v:185380$11969_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:184066$11979 + cell $or $or$libresoc.v:185374$11963 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -376327,10 +347697,10 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:184066$11979_Y + connect \Y $or$libresoc.v:185374$11963_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:184068$11981 + cell $or $or$libresoc.v:185376$11965 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -376338,10 +347708,10 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:184068$11981_Y + connect \Y $or$libresoc.v:185376$11965_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:184071$11984 + cell $or $or$libresoc.v:185379$11968 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -376349,39 +347719,39 @@ module \req_l$57 parameter \Y_WIDTH 2 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:184071$11984_Y + connect \Y $or$libresoc.v:185379$11968_Y end - attribute \src "libresoc.v:184030.7-184030.20" - process $proc$libresoc.v:184030$11990 + attribute \src "libresoc.v:185338.7-185338.20" + process $proc$libresoc.v:185338$11974 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184052.13-184052.25" - process $proc$libresoc.v:184052$11991 + attribute \src "libresoc.v:185360.13-185360.25" + process $proc$libresoc.v:185360$11975 assign { } { } assign $1\q_int[1:0] 2'00 sync always sync init update \q_int $1\q_int[1:0] end - attribute \src "libresoc.v:184073.3-184074.27" - process $proc$libresoc.v:184073$11986 + attribute \src "libresoc.v:185381.3-185382.27" + process $proc$libresoc.v:185381$11970 assign { } { } assign $0\q_int[1:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[1:0] end - attribute \src "libresoc.v:184075.3-184083.6" - process $proc$libresoc.v:184075$11987 + attribute \src "libresoc.v:185383.3-185391.6" + process $proc$libresoc.v:185383$11971 assign { } { } assign { } { } - assign $0\q_int$next[1:0]$11988 $1\q_int$next[1:0]$11989 - attribute \src "libresoc.v:184076.5-184076.29" + assign $0\q_int$next[1:0]$11972 $1\q_int$next[1:0]$11973 + attribute \src "libresoc.v:185384.5-185384.29" switch \initial - attribute \src "libresoc.v:184076.9-184076.17" + attribute \src "libresoc.v:185384.9-185384.17" case 1'1 case end @@ -376390,56 +347760,56 @@ module \req_l$57 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[1:0]$11989 2'00 + assign $1\q_int$next[1:0]$11973 2'00 case - assign $1\q_int$next[1:0]$11989 \$5 + assign $1\q_int$next[1:0]$11973 \$5 end sync always - update \q_int$next $0\q_int$next[1:0]$11988 + update \q_int$next $0\q_int$next[1:0]$11972 end - connect \$9 $and$libresoc.v:184065$11978_Y - connect \$11 $or$libresoc.v:184066$11979_Y - connect \$13 $not$libresoc.v:184067$11980_Y - connect \$15 $or$libresoc.v:184068$11981_Y - connect \$1 $not$libresoc.v:184069$11982_Y - connect \$3 $and$libresoc.v:184070$11983_Y - connect \$5 $or$libresoc.v:184071$11984_Y - connect \$7 $not$libresoc.v:184072$11985_Y + connect \$9 $and$libresoc.v:185373$11962_Y + connect \$11 $or$libresoc.v:185374$11963_Y + connect \$13 $not$libresoc.v:185375$11964_Y + connect \$15 $or$libresoc.v:185376$11965_Y + connect \$1 $not$libresoc.v:185377$11966_Y + connect \$3 $and$libresoc.v:185378$11967_Y + connect \$5 $or$libresoc.v:185379$11968_Y + connect \$7 $not$libresoc.v:185380$11969_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:184091.1-184149.10" +attribute \src "libresoc.v:185399.1-185457.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.req_l" attribute \generator "nMigen" module \req_l$69 - attribute \src "libresoc.v:184092.7-184092.20" + attribute \src "libresoc.v:185400.7-185400.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184137.3-184145.6" - wire width 6 $0\q_int$next[5:0]$12002 - attribute \src "libresoc.v:184135.3-184136.27" + attribute \src "libresoc.v:185445.3-185453.6" + wire width 6 $0\q_int$next[5:0]$11986 + attribute \src "libresoc.v:185443.3-185444.27" wire width 6 $0\q_int[5:0] - attribute \src "libresoc.v:184137.3-184145.6" - wire width 6 $1\q_int$next[5:0]$12003 - attribute \src "libresoc.v:184114.13-184114.26" + attribute \src "libresoc.v:185445.3-185453.6" + wire width 6 $1\q_int$next[5:0]$11987 + attribute \src "libresoc.v:185422.13-185422.26" wire width 6 $1\q_int[5:0] - attribute \src "libresoc.v:184127.17-184127.96" - wire width 6 $and$libresoc.v:184127$11992_Y - attribute \src "libresoc.v:184132.17-184132.96" - wire width 6 $and$libresoc.v:184132$11997_Y - attribute \src "libresoc.v:184129.18-184129.93" - wire width 6 $not$libresoc.v:184129$11994_Y - attribute \src "libresoc.v:184131.17-184131.92" - wire width 6 $not$libresoc.v:184131$11996_Y - attribute \src "libresoc.v:184134.17-184134.92" - wire width 6 $not$libresoc.v:184134$11999_Y - attribute \src "libresoc.v:184128.18-184128.98" - wire width 6 $or$libresoc.v:184128$11993_Y - attribute \src "libresoc.v:184130.18-184130.99" - wire width 6 $or$libresoc.v:184130$11995_Y - attribute \src "libresoc.v:184133.17-184133.97" - wire width 6 $or$libresoc.v:184133$11998_Y + attribute \src "libresoc.v:185435.17-185435.96" + wire width 6 $and$libresoc.v:185435$11976_Y + attribute \src "libresoc.v:185440.17-185440.96" + wire width 6 $and$libresoc.v:185440$11981_Y + attribute \src "libresoc.v:185437.18-185437.93" + wire width 6 $not$libresoc.v:185437$11978_Y + attribute \src "libresoc.v:185439.17-185439.92" + wire width 6 $not$libresoc.v:185439$11980_Y + attribute \src "libresoc.v:185442.17-185442.92" + wire width 6 $not$libresoc.v:185442$11983_Y + attribute \src "libresoc.v:185436.18-185436.98" + wire width 6 $or$libresoc.v:185436$11977_Y + attribute \src "libresoc.v:185438.18-185438.99" + wire width 6 $or$libresoc.v:185438$11979_Y + attribute \src "libresoc.v:185441.17-185441.97" + wire width 6 $or$libresoc.v:185441$11982_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -376456,11 +347826,11 @@ module \req_l$69 wire width 6 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 6 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:184092.7-184092.15" + attribute \src "libresoc.v:185400.7-185400.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 6 \q_int @@ -376477,7 +347847,7 @@ module \req_l$69 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 6 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:184127$11992 + cell $and $and$libresoc.v:185435$11976 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -376485,10 +347855,10 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:184127$11992_Y + connect \Y $and$libresoc.v:185435$11976_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:184132$11997 + cell $and $and$libresoc.v:185440$11981 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -376496,34 +347866,34 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:184132$11997_Y + connect \Y $and$libresoc.v:185440$11981_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:184129$11994 + cell $not $not$libresoc.v:185437$11978 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \q_req - connect \Y $not$libresoc.v:184129$11994_Y + connect \Y $not$libresoc.v:185437$11978_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:184131$11996 + cell $not $not$libresoc.v:185439$11980 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_req - connect \Y $not$libresoc.v:184131$11996_Y + connect \Y $not$libresoc.v:185439$11980_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:184134$11999 + cell $not $not$libresoc.v:185442$11983 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_req - connect \Y $not$libresoc.v:184134$11999_Y + connect \Y $not$libresoc.v:185442$11983_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:184128$11993 + cell $or $or$libresoc.v:185436$11977 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -376531,10 +347901,10 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:184128$11993_Y + connect \Y $or$libresoc.v:185436$11977_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:184130$11995 + cell $or $or$libresoc.v:185438$11979 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -376542,10 +347912,10 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:184130$11995_Y + connect \Y $or$libresoc.v:185438$11979_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:184133$11998 + cell $or $or$libresoc.v:185441$11982 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -376553,39 +347923,39 @@ module \req_l$69 parameter \Y_WIDTH 6 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:184133$11998_Y + connect \Y $or$libresoc.v:185441$11982_Y end - attribute \src "libresoc.v:184092.7-184092.20" - process $proc$libresoc.v:184092$12004 + attribute \src "libresoc.v:185400.7-185400.20" + process $proc$libresoc.v:185400$11988 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184114.13-184114.26" - process $proc$libresoc.v:184114$12005 + attribute \src "libresoc.v:185422.13-185422.26" + process $proc$libresoc.v:185422$11989 assign { } { } assign $1\q_int[5:0] 6'000000 sync always sync init update \q_int $1\q_int[5:0] end - attribute \src "libresoc.v:184135.3-184136.27" - process $proc$libresoc.v:184135$12000 + attribute \src "libresoc.v:185443.3-185444.27" + process $proc$libresoc.v:185443$11984 assign { } { } assign $0\q_int[5:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[5:0] end - attribute \src "libresoc.v:184137.3-184145.6" - process $proc$libresoc.v:184137$12001 + attribute \src "libresoc.v:185445.3-185453.6" + process $proc$libresoc.v:185445$11985 assign { } { } assign { } { } - assign $0\q_int$next[5:0]$12002 $1\q_int$next[5:0]$12003 - attribute \src "libresoc.v:184138.5-184138.29" + assign $0\q_int$next[5:0]$11986 $1\q_int$next[5:0]$11987 + attribute \src "libresoc.v:185446.5-185446.29" switch \initial - attribute \src "libresoc.v:184138.9-184138.17" + attribute \src "libresoc.v:185446.9-185446.17" case 1'1 case end @@ -376594,56 +347964,56 @@ module \req_l$69 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[5:0]$12003 6'000000 + assign $1\q_int$next[5:0]$11987 6'000000 case - assign $1\q_int$next[5:0]$12003 \$5 + assign $1\q_int$next[5:0]$11987 \$5 end sync always - update \q_int$next $0\q_int$next[5:0]$12002 + update \q_int$next $0\q_int$next[5:0]$11986 end - connect \$9 $and$libresoc.v:184127$11992_Y - connect \$11 $or$libresoc.v:184128$11993_Y - connect \$13 $not$libresoc.v:184129$11994_Y - connect \$15 $or$libresoc.v:184130$11995_Y - connect \$1 $not$libresoc.v:184131$11996_Y - connect \$3 $and$libresoc.v:184132$11997_Y - connect \$5 $or$libresoc.v:184133$11998_Y - connect \$7 $not$libresoc.v:184134$11999_Y + connect \$9 $and$libresoc.v:185435$11976_Y + connect \$11 $or$libresoc.v:185436$11977_Y + connect \$13 $not$libresoc.v:185437$11978_Y + connect \$15 $or$libresoc.v:185438$11979_Y + connect \$1 $not$libresoc.v:185439$11980_Y + connect \$3 $and$libresoc.v:185440$11981_Y + connect \$5 $or$libresoc.v:185441$11982_Y + connect \$7 $not$libresoc.v:185442$11983_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:184153.1-184211.10" +attribute \src "libresoc.v:185461.1-185519.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.req_l" attribute \generator "nMigen" module \req_l$86 - attribute \src "libresoc.v:184154.7-184154.20" + attribute \src "libresoc.v:185462.7-185462.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184199.3-184207.6" - wire width 4 $0\q_int$next[3:0]$12016 - attribute \src "libresoc.v:184197.3-184198.27" + attribute \src "libresoc.v:185507.3-185515.6" + wire width 4 $0\q_int$next[3:0]$12000 + attribute \src "libresoc.v:185505.3-185506.27" wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:184199.3-184207.6" - wire width 4 $1\q_int$next[3:0]$12017 - attribute \src "libresoc.v:184176.13-184176.25" + attribute \src "libresoc.v:185507.3-185515.6" + wire width 4 $1\q_int$next[3:0]$12001 + attribute \src "libresoc.v:185484.13-185484.25" wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:184189.17-184189.96" - wire width 4 $and$libresoc.v:184189$12006_Y - attribute \src "libresoc.v:184194.17-184194.96" - wire width 4 $and$libresoc.v:184194$12011_Y - attribute \src "libresoc.v:184191.18-184191.93" - wire width 4 $not$libresoc.v:184191$12008_Y - attribute \src "libresoc.v:184193.17-184193.92" - wire width 4 $not$libresoc.v:184193$12010_Y - attribute \src "libresoc.v:184196.17-184196.92" - wire width 4 $not$libresoc.v:184196$12013_Y - attribute \src "libresoc.v:184190.18-184190.98" - wire width 4 $or$libresoc.v:184190$12007_Y - attribute \src "libresoc.v:184192.18-184192.99" - wire width 4 $or$libresoc.v:184192$12009_Y - attribute \src "libresoc.v:184195.17-184195.97" - wire width 4 $or$libresoc.v:184195$12012_Y + attribute \src "libresoc.v:185497.17-185497.96" + wire width 4 $and$libresoc.v:185497$11990_Y + attribute \src "libresoc.v:185502.17-185502.96" + wire width 4 $and$libresoc.v:185502$11995_Y + attribute \src "libresoc.v:185499.18-185499.93" + wire width 4 $not$libresoc.v:185499$11992_Y + attribute \src "libresoc.v:185501.17-185501.92" + wire width 4 $not$libresoc.v:185501$11994_Y + attribute \src "libresoc.v:185504.17-185504.92" + wire width 4 $not$libresoc.v:185504$11997_Y + attribute \src "libresoc.v:185498.18-185498.98" + wire width 4 $or$libresoc.v:185498$11991_Y + attribute \src "libresoc.v:185500.18-185500.99" + wire width 4 $or$libresoc.v:185500$11993_Y + attribute \src "libresoc.v:185503.17-185503.97" + wire width 4 $or$libresoc.v:185503$11996_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -376660,11 +348030,11 @@ module \req_l$86 wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:184154.7-184154.15" + attribute \src "libresoc.v:185462.7-185462.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int @@ -376681,7 +348051,7 @@ module \req_l$86 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 input 3 \s_req attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:184189$12006 + cell $and $and$libresoc.v:185497$11990 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -376689,10 +348059,10 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:184189$12006_Y + connect \Y $and$libresoc.v:185497$11990_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:184194$12011 + cell $and $and$libresoc.v:185502$11995 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -376700,34 +348070,34 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:184194$12011_Y + connect \Y $and$libresoc.v:185502$11995_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:184191$12008 + cell $not $not$libresoc.v:185499$11992 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_req - connect \Y $not$libresoc.v:184191$12008_Y + connect \Y $not$libresoc.v:185499$11992_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:184193$12010 + cell $not $not$libresoc.v:185501$11994 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req - connect \Y $not$libresoc.v:184193$12010_Y + connect \Y $not$libresoc.v:185501$11994_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:184196$12013 + cell $not $not$libresoc.v:185504$11997 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_req - connect \Y $not$libresoc.v:184196$12013_Y + connect \Y $not$libresoc.v:185504$11997_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:184190$12007 + cell $or $or$libresoc.v:185498$11991 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -376735,10 +348105,10 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_req - connect \Y $or$libresoc.v:184190$12007_Y + connect \Y $or$libresoc.v:185498$11991_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:184192$12009 + cell $or $or$libresoc.v:185500$11993 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -376746,10 +348116,10 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \q_req connect \B \q_int - connect \Y $or$libresoc.v:184192$12009_Y + connect \Y $or$libresoc.v:185500$11993_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:184195$12012 + cell $or $or$libresoc.v:185503$11996 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -376757,39 +348127,39 @@ module \req_l$86 parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_req - connect \Y $or$libresoc.v:184195$12012_Y + connect \Y $or$libresoc.v:185503$11996_Y end - attribute \src "libresoc.v:184154.7-184154.20" - process $proc$libresoc.v:184154$12018 + attribute \src "libresoc.v:185462.7-185462.20" + process $proc$libresoc.v:185462$12002 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184176.13-184176.25" - process $proc$libresoc.v:184176$12019 + attribute \src "libresoc.v:185484.13-185484.25" + process $proc$libresoc.v:185484$12003 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end - attribute \src "libresoc.v:184197.3-184198.27" - process $proc$libresoc.v:184197$12014 + attribute \src "libresoc.v:185505.3-185506.27" + process $proc$libresoc.v:185505$11998 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end - attribute \src "libresoc.v:184199.3-184207.6" - process $proc$libresoc.v:184199$12015 + attribute \src "libresoc.v:185507.3-185515.6" + process $proc$libresoc.v:185507$11999 assign { } { } assign { } { } - assign $0\q_int$next[3:0]$12016 $1\q_int$next[3:0]$12017 - attribute \src "libresoc.v:184200.5-184200.29" + assign $0\q_int$next[3:0]$12000 $1\q_int$next[3:0]$12001 + attribute \src "libresoc.v:185508.5-185508.29" switch \initial - attribute \src "libresoc.v:184200.9-184200.17" + attribute \src "libresoc.v:185508.9-185508.17" case 1'1 case end @@ -376798,50 +348168,50 @@ module \req_l$86 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[3:0]$12017 4'0000 + assign $1\q_int$next[3:0]$12001 4'0000 case - assign $1\q_int$next[3:0]$12017 \$5 + assign $1\q_int$next[3:0]$12001 \$5 end sync always - update \q_int$next $0\q_int$next[3:0]$12016 + update \q_int$next $0\q_int$next[3:0]$12000 end - connect \$9 $and$libresoc.v:184189$12006_Y - connect \$11 $or$libresoc.v:184190$12007_Y - connect \$13 $not$libresoc.v:184191$12008_Y - connect \$15 $or$libresoc.v:184192$12009_Y - connect \$1 $not$libresoc.v:184193$12010_Y - connect \$3 $and$libresoc.v:184194$12011_Y - connect \$5 $or$libresoc.v:184195$12012_Y - connect \$7 $not$libresoc.v:184196$12013_Y + connect \$9 $and$libresoc.v:185497$11990_Y + connect \$11 $or$libresoc.v:185498$11991_Y + connect \$13 $not$libresoc.v:185499$11992_Y + connect \$15 $or$libresoc.v:185500$11993_Y + connect \$1 $not$libresoc.v:185501$11994_Y + connect \$3 $and$libresoc.v:185502$11995_Y + connect \$5 $or$libresoc.v:185503$11996_Y + connect \$7 $not$libresoc.v:185504$11997_Y connect \qlq_req \$15 connect \qn_req \$13 connect \q_req \$11 end -attribute \src "libresoc.v:184215.1-184264.10" +attribute \src "libresoc.v:185523.1-185572.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.reset_l" attribute \generator "nMigen" module \reset_l - attribute \src "libresoc.v:184216.7-184216.20" + attribute \src "libresoc.v:185524.7-185524.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184252.3-184260.6" - wire $0\q_int$next[0:0]$12027 - attribute \src "libresoc.v:184250.3-184251.27" + attribute \src "libresoc.v:185560.3-185568.6" + wire $0\q_int$next[0:0]$12011 + attribute \src "libresoc.v:185558.3-185559.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:184252.3-184260.6" - wire $1\q_int$next[0:0]$12028 - attribute \src "libresoc.v:184232.7-184232.19" + attribute \src "libresoc.v:185560.3-185568.6" + wire $1\q_int$next[0:0]$12012 + attribute \src "libresoc.v:185540.7-185540.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:184247.17-184247.96" - wire $and$libresoc.v:184247$12022_Y - attribute \src "libresoc.v:184246.17-184246.94" - wire $not$libresoc.v:184246$12021_Y - attribute \src "libresoc.v:184249.17-184249.94" - wire $not$libresoc.v:184249$12024_Y - attribute \src "libresoc.v:184245.17-184245.100" - wire $or$libresoc.v:184245$12020_Y - attribute \src "libresoc.v:184248.17-184248.99" - wire $or$libresoc.v:184248$12023_Y + attribute \src "libresoc.v:185555.17-185555.96" + wire $and$libresoc.v:185555$12006_Y + attribute \src "libresoc.v:185554.17-185554.94" + wire $not$libresoc.v:185554$12005_Y + attribute \src "libresoc.v:185557.17-185557.94" + wire $not$libresoc.v:185557$12008_Y + attribute \src "libresoc.v:185553.17-185553.100" + wire $or$libresoc.v:185553$12004_Y + attribute \src "libresoc.v:185556.17-185556.99" + wire $or$libresoc.v:185556$12007_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" @@ -376852,11 +348222,11 @@ module \reset_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:184216.7-184216.15" + attribute \src "libresoc.v:185524.7-185524.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -376873,7 +348243,7 @@ module \reset_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:184247$12022 + cell $and $and$libresoc.v:185555$12006 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -376881,26 +348251,26 @@ module \reset_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:184247$12022_Y + connect \Y $and$libresoc.v:185555$12006_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:184246$12021 + cell $not $not$libresoc.v:185554$12005 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_reset - connect \Y $not$libresoc.v:184246$12021_Y + connect \Y $not$libresoc.v:185554$12005_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:184249$12024 + cell $not $not$libresoc.v:185557$12008 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_reset - connect \Y $not$libresoc.v:184249$12024_Y + connect \Y $not$libresoc.v:185557$12008_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:184245$12020 + cell $or $or$libresoc.v:185553$12004 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -376908,10 +348278,10 @@ module \reset_l parameter \Y_WIDTH 1 connect \A \q_reset connect \B \q_int - connect \Y $or$libresoc.v:184245$12020_Y + connect \Y $or$libresoc.v:185553$12004_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:184248$12023 + cell $or $or$libresoc.v:185556$12007 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -376919,39 +348289,39 @@ module \reset_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_reset - connect \Y $or$libresoc.v:184248$12023_Y + connect \Y $or$libresoc.v:185556$12007_Y end - attribute \src "libresoc.v:184216.7-184216.20" - process $proc$libresoc.v:184216$12029 + attribute \src "libresoc.v:185524.7-185524.20" + process $proc$libresoc.v:185524$12013 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184232.7-184232.19" - process $proc$libresoc.v:184232$12030 + attribute \src "libresoc.v:185540.7-185540.19" + process $proc$libresoc.v:185540$12014 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:184250.3-184251.27" - process $proc$libresoc.v:184250$12025 + attribute \src "libresoc.v:185558.3-185559.27" + process $proc$libresoc.v:185558$12009 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:184252.3-184260.6" - process $proc$libresoc.v:184252$12026 + attribute \src "libresoc.v:185560.3-185568.6" + process $proc$libresoc.v:185560$12010 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12027 $1\q_int$next[0:0]$12028 - attribute \src "libresoc.v:184253.5-184253.29" + assign $0\q_int$next[0:0]$12011 $1\q_int$next[0:0]$12012 + attribute \src "libresoc.v:185561.5-185561.29" switch \initial - attribute \src "libresoc.v:184253.9-184253.17" + attribute \src "libresoc.v:185561.9-185561.17" case 1'1 case end @@ -376960,47 +348330,47 @@ module \reset_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12028 1'0 + assign $1\q_int$next[0:0]$12012 1'0 case - assign $1\q_int$next[0:0]$12028 \$5 + assign $1\q_int$next[0:0]$12012 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12027 + update \q_int$next $0\q_int$next[0:0]$12011 end - connect \$9 $or$libresoc.v:184245$12020_Y - connect \$1 $not$libresoc.v:184246$12021_Y - connect \$3 $and$libresoc.v:184247$12022_Y - connect \$5 $or$libresoc.v:184248$12023_Y - connect \$7 $not$libresoc.v:184249$12024_Y + connect \$9 $or$libresoc.v:185553$12004_Y + connect \$1 $not$libresoc.v:185554$12005_Y + connect \$3 $and$libresoc.v:185555$12006_Y + connect \$5 $or$libresoc.v:185556$12007_Y + connect \$7 $not$libresoc.v:185557$12008_Y connect \qlq_reset \$9 connect \qn_reset \$7 connect \q_reset \q_int end -attribute \src "libresoc.v:184268.1-184317.10" +attribute \src "libresoc.v:185576.1-185625.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.l0.reset_l" attribute \generator "nMigen" module \reset_l$131 - attribute \src "libresoc.v:184269.7-184269.20" + attribute \src "libresoc.v:185577.7-185577.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184305.3-184313.6" - wire $0\q_int$next[0:0]$12038 - attribute \src "libresoc.v:184303.3-184304.27" + attribute \src "libresoc.v:185613.3-185621.6" + wire $0\q_int$next[0:0]$12022 + attribute \src "libresoc.v:185611.3-185612.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:184305.3-184313.6" - wire $1\q_int$next[0:0]$12039 - attribute \src "libresoc.v:184285.7-184285.19" + attribute \src "libresoc.v:185613.3-185621.6" + wire $1\q_int$next[0:0]$12023 + attribute \src "libresoc.v:185593.7-185593.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:184300.17-184300.96" - wire $and$libresoc.v:184300$12033_Y - attribute \src "libresoc.v:184299.17-184299.94" - wire $not$libresoc.v:184299$12032_Y - attribute \src "libresoc.v:184302.17-184302.94" - wire $not$libresoc.v:184302$12035_Y - attribute \src "libresoc.v:184298.17-184298.100" - wire $or$libresoc.v:184298$12031_Y - attribute \src "libresoc.v:184301.17-184301.99" - wire $or$libresoc.v:184301$12034_Y + attribute \src "libresoc.v:185608.17-185608.96" + wire $and$libresoc.v:185608$12017_Y + attribute \src "libresoc.v:185607.17-185607.94" + wire $not$libresoc.v:185607$12016_Y + attribute \src "libresoc.v:185610.17-185610.94" + wire $not$libresoc.v:185610$12019_Y + attribute \src "libresoc.v:185606.17-185606.100" + wire $or$libresoc.v:185606$12015_Y + attribute \src "libresoc.v:185609.17-185609.99" + wire $or$libresoc.v:185609$12018_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" @@ -377011,11 +348381,11 @@ module \reset_l$131 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:184269.7-184269.15" + attribute \src "libresoc.v:185577.7-185577.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -377032,7 +348402,7 @@ module \reset_l$131 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_reset attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:184300$12033 + cell $and $and$libresoc.v:185608$12017 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -377040,26 +348410,26 @@ module \reset_l$131 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:184300$12033_Y + connect \Y $and$libresoc.v:185608$12017_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:184299$12032 + cell $not $not$libresoc.v:185607$12016 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_reset - connect \Y $not$libresoc.v:184299$12032_Y + connect \Y $not$libresoc.v:185607$12016_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:184302$12035 + cell $not $not$libresoc.v:185610$12019 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_reset - connect \Y $not$libresoc.v:184302$12035_Y + connect \Y $not$libresoc.v:185610$12019_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:184298$12031 + cell $or $or$libresoc.v:185606$12015 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -377067,10 +348437,10 @@ module \reset_l$131 parameter \Y_WIDTH 1 connect \A \q_reset connect \B \q_int - connect \Y $or$libresoc.v:184298$12031_Y + connect \Y $or$libresoc.v:185606$12015_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:184301$12034 + cell $or $or$libresoc.v:185609$12018 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -377078,39 +348448,39 @@ module \reset_l$131 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_reset - connect \Y $or$libresoc.v:184301$12034_Y + connect \Y $or$libresoc.v:185609$12018_Y end - attribute \src "libresoc.v:184269.7-184269.20" - process $proc$libresoc.v:184269$12040 + attribute \src "libresoc.v:185577.7-185577.20" + process $proc$libresoc.v:185577$12024 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184285.7-184285.19" - process $proc$libresoc.v:184285$12041 + attribute \src "libresoc.v:185593.7-185593.19" + process $proc$libresoc.v:185593$12025 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:184303.3-184304.27" - process $proc$libresoc.v:184303$12036 + attribute \src "libresoc.v:185611.3-185612.27" + process $proc$libresoc.v:185611$12020 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:184305.3-184313.6" - process $proc$libresoc.v:184305$12037 + attribute \src "libresoc.v:185613.3-185621.6" + process $proc$libresoc.v:185613$12021 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12038 $1\q_int$next[0:0]$12039 - attribute \src "libresoc.v:184306.5-184306.29" + assign $0\q_int$next[0:0]$12022 $1\q_int$next[0:0]$12023 + attribute \src "libresoc.v:185614.5-185614.29" switch \initial - attribute \src "libresoc.v:184306.9-184306.17" + attribute \src "libresoc.v:185614.9-185614.17" case 1'1 case end @@ -377119,287 +348489,287 @@ module \reset_l$131 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12039 1'0 + assign $1\q_int$next[0:0]$12023 1'0 case - assign $1\q_int$next[0:0]$12039 \$5 + assign $1\q_int$next[0:0]$12023 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12038 + update \q_int$next $0\q_int$next[0:0]$12022 end - connect \$9 $or$libresoc.v:184298$12031_Y - connect \$1 $not$libresoc.v:184299$12032_Y - connect \$3 $and$libresoc.v:184300$12033_Y - connect \$5 $or$libresoc.v:184301$12034_Y - connect \$7 $not$libresoc.v:184302$12035_Y + connect \$9 $or$libresoc.v:185606$12015_Y + connect \$1 $not$libresoc.v:185607$12016_Y + connect \$3 $and$libresoc.v:185608$12017_Y + connect \$5 $or$libresoc.v:185609$12018_Y + connect \$7 $not$libresoc.v:185610$12019_Y connect \qlq_reset \$9 connect \qn_reset \$7 connect \q_reset \q_int end -attribute \src "libresoc.v:184321.1-184908.10" +attribute \src "libresoc.v:185629.1-186216.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.right_mask" attribute \generator "nMigen" module \right_mask - attribute \src "libresoc.v:184322.7-184322.20" + attribute \src "libresoc.v:185630.7-185630.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire width 64 $0\mask[63:0] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $10\mask[9:9] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $11\mask[10:10] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $12\mask[11:11] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $13\mask[12:12] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $14\mask[13:13] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $15\mask[14:14] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $16\mask[15:15] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $17\mask[16:16] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $18\mask[17:17] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $19\mask[18:18] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $1\mask[0:0] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $20\mask[19:19] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $21\mask[20:20] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $22\mask[21:21] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $23\mask[22:22] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $24\mask[23:23] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $25\mask[24:24] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $26\mask[25:25] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $27\mask[26:26] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $28\mask[27:27] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $29\mask[28:28] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $2\mask[1:1] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $30\mask[29:29] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $31\mask[30:30] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $32\mask[31:31] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $33\mask[32:32] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $34\mask[33:33] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $35\mask[34:34] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $36\mask[35:35] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $37\mask[36:36] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $38\mask[37:37] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $39\mask[38:38] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $3\mask[2:2] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $40\mask[39:39] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $41\mask[40:40] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $42\mask[41:41] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $43\mask[42:42] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $44\mask[43:43] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $45\mask[44:44] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $46\mask[45:45] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $47\mask[46:46] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $48\mask[47:47] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $49\mask[48:48] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $4\mask[3:3] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $50\mask[49:49] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $51\mask[50:50] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $52\mask[51:51] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $53\mask[52:52] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $54\mask[53:53] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $55\mask[54:54] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $56\mask[55:55] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $57\mask[56:56] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $58\mask[57:57] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $59\mask[58:58] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $5\mask[4:4] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $60\mask[59:59] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $61\mask[60:60] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $62\mask[61:61] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $63\mask[62:62] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $64\mask[63:63] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $6\mask[5:5] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $7\mask[6:6] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $8\mask[7:7] - attribute \src "libresoc.v:184520.3-184907.6" + attribute \src "libresoc.v:185828.3-186215.6" wire $9\mask[8:8] - attribute \src "libresoc.v:184456.17-184456.96" - wire $gt$libresoc.v:184456$12042_Y - attribute \src "libresoc.v:184457.18-184457.98" - wire $gt$libresoc.v:184457$12043_Y - attribute \src "libresoc.v:184458.19-184458.99" - wire $gt$libresoc.v:184458$12044_Y - attribute \src "libresoc.v:184459.19-184459.99" - wire $gt$libresoc.v:184459$12045_Y - attribute \src "libresoc.v:184460.19-184460.99" - wire $gt$libresoc.v:184460$12046_Y - attribute \src "libresoc.v:184461.19-184461.99" - wire $gt$libresoc.v:184461$12047_Y - attribute \src "libresoc.v:184462.19-184462.99" - wire $gt$libresoc.v:184462$12048_Y - attribute \src "libresoc.v:184463.19-184463.99" - wire $gt$libresoc.v:184463$12049_Y - attribute \src "libresoc.v:184464.19-184464.99" - wire $gt$libresoc.v:184464$12050_Y - attribute \src "libresoc.v:184465.19-184465.99" - wire $gt$libresoc.v:184465$12051_Y - attribute \src "libresoc.v:184466.19-184466.99" - wire $gt$libresoc.v:184466$12052_Y - attribute \src "libresoc.v:184467.18-184467.97" - wire $gt$libresoc.v:184467$12053_Y - attribute \src "libresoc.v:184468.19-184468.99" - wire $gt$libresoc.v:184468$12054_Y - attribute \src "libresoc.v:184469.19-184469.99" - wire $gt$libresoc.v:184469$12055_Y - attribute \src "libresoc.v:184470.19-184470.99" - wire $gt$libresoc.v:184470$12056_Y - attribute \src "libresoc.v:184471.19-184471.99" - wire $gt$libresoc.v:184471$12057_Y - attribute \src "libresoc.v:184472.19-184472.99" - wire $gt$libresoc.v:184472$12058_Y - attribute \src "libresoc.v:184473.18-184473.97" - wire $gt$libresoc.v:184473$12059_Y - attribute \src "libresoc.v:184474.18-184474.97" - wire $gt$libresoc.v:184474$12060_Y - attribute \src "libresoc.v:184475.18-184475.97" - wire $gt$libresoc.v:184475$12061_Y - attribute \src "libresoc.v:184476.17-184476.96" - wire $gt$libresoc.v:184476$12062_Y - attribute \src "libresoc.v:184477.18-184477.97" - wire $gt$libresoc.v:184477$12063_Y - attribute \src "libresoc.v:184478.18-184478.97" - wire $gt$libresoc.v:184478$12064_Y - attribute \src "libresoc.v:184479.18-184479.97" - wire $gt$libresoc.v:184479$12065_Y - attribute \src "libresoc.v:184480.18-184480.97" - wire $gt$libresoc.v:184480$12066_Y - attribute \src "libresoc.v:184481.18-184481.97" - wire $gt$libresoc.v:184481$12067_Y - attribute \src "libresoc.v:184482.18-184482.97" - wire $gt$libresoc.v:184482$12068_Y - attribute \src "libresoc.v:184483.18-184483.97" - wire $gt$libresoc.v:184483$12069_Y - attribute \src "libresoc.v:184484.18-184484.98" - wire $gt$libresoc.v:184484$12070_Y - attribute \src "libresoc.v:184485.18-184485.98" - wire $gt$libresoc.v:184485$12071_Y - attribute \src "libresoc.v:184486.18-184486.98" - wire $gt$libresoc.v:184486$12072_Y - attribute \src "libresoc.v:184487.17-184487.96" - wire $gt$libresoc.v:184487$12073_Y - attribute \src "libresoc.v:184488.18-184488.98" - wire $gt$libresoc.v:184488$12074_Y - attribute \src "libresoc.v:184489.18-184489.98" - wire $gt$libresoc.v:184489$12075_Y - attribute \src "libresoc.v:184490.18-184490.98" - wire $gt$libresoc.v:184490$12076_Y - attribute \src "libresoc.v:184491.18-184491.98" - wire $gt$libresoc.v:184491$12077_Y - attribute \src "libresoc.v:184492.18-184492.98" - wire $gt$libresoc.v:184492$12078_Y - attribute \src "libresoc.v:184493.18-184493.98" - wire $gt$libresoc.v:184493$12079_Y - attribute \src "libresoc.v:184494.18-184494.98" - wire $gt$libresoc.v:184494$12080_Y - attribute \src "libresoc.v:184495.18-184495.98" - wire $gt$libresoc.v:184495$12081_Y - attribute \src "libresoc.v:184496.18-184496.98" - wire $gt$libresoc.v:184496$12082_Y - attribute \src "libresoc.v:184497.18-184497.98" - wire $gt$libresoc.v:184497$12083_Y - attribute \src "libresoc.v:184498.17-184498.96" - wire $gt$libresoc.v:184498$12084_Y - attribute \src "libresoc.v:184499.18-184499.98" - wire $gt$libresoc.v:184499$12085_Y - attribute \src "libresoc.v:184500.18-184500.98" - wire $gt$libresoc.v:184500$12086_Y - attribute \src "libresoc.v:184501.18-184501.98" - wire $gt$libresoc.v:184501$12087_Y - attribute \src "libresoc.v:184502.18-184502.98" - wire $gt$libresoc.v:184502$12088_Y - attribute \src "libresoc.v:184503.18-184503.98" - wire $gt$libresoc.v:184503$12089_Y - attribute \src "libresoc.v:184504.18-184504.98" - wire $gt$libresoc.v:184504$12090_Y - attribute \src "libresoc.v:184505.18-184505.98" - wire $gt$libresoc.v:184505$12091_Y - attribute \src "libresoc.v:184506.18-184506.98" - wire $gt$libresoc.v:184506$12092_Y - attribute \src "libresoc.v:184507.18-184507.98" - wire $gt$libresoc.v:184507$12093_Y - attribute \src "libresoc.v:184508.18-184508.98" - wire $gt$libresoc.v:184508$12094_Y - attribute \src "libresoc.v:184509.17-184509.96" - wire $gt$libresoc.v:184509$12095_Y - attribute \src "libresoc.v:184510.18-184510.98" - wire $gt$libresoc.v:184510$12096_Y - attribute \src "libresoc.v:184511.18-184511.98" - wire $gt$libresoc.v:184511$12097_Y - attribute \src "libresoc.v:184512.18-184512.98" - wire $gt$libresoc.v:184512$12098_Y - attribute \src "libresoc.v:184513.18-184513.98" - wire $gt$libresoc.v:184513$12099_Y - attribute \src "libresoc.v:184514.18-184514.98" - wire $gt$libresoc.v:184514$12100_Y - attribute \src "libresoc.v:184515.18-184515.98" - wire $gt$libresoc.v:184515$12101_Y - attribute \src "libresoc.v:184516.18-184516.98" - wire $gt$libresoc.v:184516$12102_Y - attribute \src "libresoc.v:184517.18-184517.98" - wire $gt$libresoc.v:184517$12103_Y - attribute \src "libresoc.v:184518.18-184518.98" - wire $gt$libresoc.v:184518$12104_Y - attribute \src "libresoc.v:184519.18-184519.98" - wire $gt$libresoc.v:184519$12105_Y + attribute \src "libresoc.v:185764.17-185764.96" + wire $gt$libresoc.v:185764$12026_Y + attribute \src "libresoc.v:185765.18-185765.98" + wire $gt$libresoc.v:185765$12027_Y + attribute \src "libresoc.v:185766.19-185766.99" + wire $gt$libresoc.v:185766$12028_Y + attribute \src "libresoc.v:185767.19-185767.99" + wire $gt$libresoc.v:185767$12029_Y + attribute \src "libresoc.v:185768.19-185768.99" + wire $gt$libresoc.v:185768$12030_Y + attribute \src "libresoc.v:185769.19-185769.99" + wire $gt$libresoc.v:185769$12031_Y + attribute \src "libresoc.v:185770.19-185770.99" + wire $gt$libresoc.v:185770$12032_Y + attribute \src "libresoc.v:185771.19-185771.99" + wire $gt$libresoc.v:185771$12033_Y + attribute \src "libresoc.v:185772.19-185772.99" + wire $gt$libresoc.v:185772$12034_Y + attribute \src "libresoc.v:185773.19-185773.99" + wire $gt$libresoc.v:185773$12035_Y + attribute \src "libresoc.v:185774.19-185774.99" + wire $gt$libresoc.v:185774$12036_Y + attribute \src "libresoc.v:185775.18-185775.97" + wire $gt$libresoc.v:185775$12037_Y + attribute \src "libresoc.v:185776.19-185776.99" + wire $gt$libresoc.v:185776$12038_Y + attribute \src "libresoc.v:185777.19-185777.99" + wire $gt$libresoc.v:185777$12039_Y + attribute \src "libresoc.v:185778.19-185778.99" + wire $gt$libresoc.v:185778$12040_Y + attribute \src "libresoc.v:185779.19-185779.99" + wire $gt$libresoc.v:185779$12041_Y + attribute \src "libresoc.v:185780.19-185780.99" + wire $gt$libresoc.v:185780$12042_Y + attribute \src "libresoc.v:185781.18-185781.97" + wire $gt$libresoc.v:185781$12043_Y + attribute \src "libresoc.v:185782.18-185782.97" + wire $gt$libresoc.v:185782$12044_Y + attribute \src "libresoc.v:185783.18-185783.97" + wire $gt$libresoc.v:185783$12045_Y + attribute \src "libresoc.v:185784.17-185784.96" + wire $gt$libresoc.v:185784$12046_Y + attribute \src "libresoc.v:185785.18-185785.97" + wire $gt$libresoc.v:185785$12047_Y + attribute \src "libresoc.v:185786.18-185786.97" + wire $gt$libresoc.v:185786$12048_Y + attribute \src "libresoc.v:185787.18-185787.97" + wire $gt$libresoc.v:185787$12049_Y + attribute \src "libresoc.v:185788.18-185788.97" + wire $gt$libresoc.v:185788$12050_Y + attribute \src "libresoc.v:185789.18-185789.97" + wire $gt$libresoc.v:185789$12051_Y + attribute \src "libresoc.v:185790.18-185790.97" + wire $gt$libresoc.v:185790$12052_Y + attribute \src "libresoc.v:185791.18-185791.97" + wire $gt$libresoc.v:185791$12053_Y + attribute \src "libresoc.v:185792.18-185792.98" + wire $gt$libresoc.v:185792$12054_Y + attribute \src "libresoc.v:185793.18-185793.98" + wire $gt$libresoc.v:185793$12055_Y + attribute \src "libresoc.v:185794.18-185794.98" + wire $gt$libresoc.v:185794$12056_Y + attribute \src "libresoc.v:185795.17-185795.96" + wire $gt$libresoc.v:185795$12057_Y + attribute \src "libresoc.v:185796.18-185796.98" + wire $gt$libresoc.v:185796$12058_Y + attribute \src "libresoc.v:185797.18-185797.98" + wire $gt$libresoc.v:185797$12059_Y + attribute \src "libresoc.v:185798.18-185798.98" + wire $gt$libresoc.v:185798$12060_Y + attribute \src "libresoc.v:185799.18-185799.98" + wire $gt$libresoc.v:185799$12061_Y + attribute \src "libresoc.v:185800.18-185800.98" + wire $gt$libresoc.v:185800$12062_Y + attribute \src "libresoc.v:185801.18-185801.98" + wire $gt$libresoc.v:185801$12063_Y + attribute \src "libresoc.v:185802.18-185802.98" + wire $gt$libresoc.v:185802$12064_Y + attribute \src "libresoc.v:185803.18-185803.98" + wire $gt$libresoc.v:185803$12065_Y + attribute \src "libresoc.v:185804.18-185804.98" + wire $gt$libresoc.v:185804$12066_Y + attribute \src "libresoc.v:185805.18-185805.98" + wire $gt$libresoc.v:185805$12067_Y + attribute \src "libresoc.v:185806.17-185806.96" + wire $gt$libresoc.v:185806$12068_Y + attribute \src "libresoc.v:185807.18-185807.98" + wire $gt$libresoc.v:185807$12069_Y + attribute \src "libresoc.v:185808.18-185808.98" + wire $gt$libresoc.v:185808$12070_Y + attribute \src "libresoc.v:185809.18-185809.98" + wire $gt$libresoc.v:185809$12071_Y + attribute \src "libresoc.v:185810.18-185810.98" + wire $gt$libresoc.v:185810$12072_Y + attribute \src "libresoc.v:185811.18-185811.98" + wire $gt$libresoc.v:185811$12073_Y + attribute \src "libresoc.v:185812.18-185812.98" + wire $gt$libresoc.v:185812$12074_Y + attribute \src "libresoc.v:185813.18-185813.98" + wire $gt$libresoc.v:185813$12075_Y + attribute \src "libresoc.v:185814.18-185814.98" + wire $gt$libresoc.v:185814$12076_Y + attribute \src "libresoc.v:185815.18-185815.98" + wire $gt$libresoc.v:185815$12077_Y + attribute \src "libresoc.v:185816.18-185816.98" + wire $gt$libresoc.v:185816$12078_Y + attribute \src "libresoc.v:185817.17-185817.96" + wire $gt$libresoc.v:185817$12079_Y + attribute \src "libresoc.v:185818.18-185818.98" + wire $gt$libresoc.v:185818$12080_Y + attribute \src "libresoc.v:185819.18-185819.98" + wire $gt$libresoc.v:185819$12081_Y + attribute \src "libresoc.v:185820.18-185820.98" + wire $gt$libresoc.v:185820$12082_Y + attribute \src "libresoc.v:185821.18-185821.98" + wire $gt$libresoc.v:185821$12083_Y + attribute \src "libresoc.v:185822.18-185822.98" + wire $gt$libresoc.v:185822$12084_Y + attribute \src "libresoc.v:185823.18-185823.98" + wire $gt$libresoc.v:185823$12085_Y + attribute \src "libresoc.v:185824.18-185824.98" + wire $gt$libresoc.v:185824$12086_Y + attribute \src "libresoc.v:185825.18-185825.98" + wire $gt$libresoc.v:185825$12087_Y + attribute \src "libresoc.v:185826.18-185826.98" + wire $gt$libresoc.v:185826$12088_Y + attribute \src "libresoc.v:185827.18-185827.98" + wire $gt$libresoc.v:185827$12089_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" @@ -377528,14 +348898,14 @@ module \right_mask wire \$97 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" wire \$99 - attribute \src "libresoc.v:184322.7-184322.15" + attribute \src "libresoc.v:185630.7-185630.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:20" wire width 64 output 1 \mask attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:19" wire width 7 input 2 \shift attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184456$12042 + cell $gt $gt$libresoc.v:185764$12026 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377543,10 +348913,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'100 - connect \Y $gt$libresoc.v:184456$12042_Y + connect \Y $gt$libresoc.v:185764$12026_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184457$12043 + cell $gt $gt$libresoc.v:185765$12027 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377554,10 +348924,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110001 - connect \Y $gt$libresoc.v:184457$12043_Y + connect \Y $gt$libresoc.v:185765$12027_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184458$12044 + cell $gt $gt$libresoc.v:185766$12028 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377565,10 +348935,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110010 - connect \Y $gt$libresoc.v:184458$12044_Y + connect \Y $gt$libresoc.v:185766$12028_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184459$12045 + cell $gt $gt$libresoc.v:185767$12029 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377576,10 +348946,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110011 - connect \Y $gt$libresoc.v:184459$12045_Y + connect \Y $gt$libresoc.v:185767$12029_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184460$12046 + cell $gt $gt$libresoc.v:185768$12030 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377587,10 +348957,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110100 - connect \Y $gt$libresoc.v:184460$12046_Y + connect \Y $gt$libresoc.v:185768$12030_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184461$12047 + cell $gt $gt$libresoc.v:185769$12031 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377598,10 +348968,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110101 - connect \Y $gt$libresoc.v:184461$12047_Y + connect \Y $gt$libresoc.v:185769$12031_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184462$12048 + cell $gt $gt$libresoc.v:185770$12032 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377609,10 +348979,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110110 - connect \Y $gt$libresoc.v:184462$12048_Y + connect \Y $gt$libresoc.v:185770$12032_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184463$12049 + cell $gt $gt$libresoc.v:185771$12033 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377620,10 +348990,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110111 - connect \Y $gt$libresoc.v:184463$12049_Y + connect \Y $gt$libresoc.v:185771$12033_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184464$12050 + cell $gt $gt$libresoc.v:185772$12034 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377631,10 +349001,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111000 - connect \Y $gt$libresoc.v:184464$12050_Y + connect \Y $gt$libresoc.v:185772$12034_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184465$12051 + cell $gt $gt$libresoc.v:185773$12035 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377642,10 +349012,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111001 - connect \Y $gt$libresoc.v:184465$12051_Y + connect \Y $gt$libresoc.v:185773$12035_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184466$12052 + cell $gt $gt$libresoc.v:185774$12036 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377653,10 +349023,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111010 - connect \Y $gt$libresoc.v:184466$12052_Y + connect \Y $gt$libresoc.v:185774$12036_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184467$12053 + cell $gt $gt$libresoc.v:185775$12037 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377664,10 +349034,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'101 - connect \Y $gt$libresoc.v:184467$12053_Y + connect \Y $gt$libresoc.v:185775$12037_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184468$12054 + cell $gt $gt$libresoc.v:185776$12038 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377675,10 +349045,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111011 - connect \Y $gt$libresoc.v:184468$12054_Y + connect \Y $gt$libresoc.v:185776$12038_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184469$12055 + cell $gt $gt$libresoc.v:185777$12039 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377686,10 +349056,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111100 - connect \Y $gt$libresoc.v:184469$12055_Y + connect \Y $gt$libresoc.v:185777$12039_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184470$12056 + cell $gt $gt$libresoc.v:185778$12040 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377697,10 +349067,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111101 - connect \Y $gt$libresoc.v:184470$12056_Y + connect \Y $gt$libresoc.v:185778$12040_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184471$12057 + cell $gt $gt$libresoc.v:185779$12041 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377708,10 +349078,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111110 - connect \Y $gt$libresoc.v:184471$12057_Y + connect \Y $gt$libresoc.v:185779$12041_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184472$12058 + cell $gt $gt$libresoc.v:185780$12042 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377719,10 +349089,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'111111 - connect \Y $gt$libresoc.v:184472$12058_Y + connect \Y $gt$libresoc.v:185780$12042_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184473$12059 + cell $gt $gt$libresoc.v:185781$12043 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377730,10 +349100,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'110 - connect \Y $gt$libresoc.v:184473$12059_Y + connect \Y $gt$libresoc.v:185781$12043_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184474$12060 + cell $gt $gt$libresoc.v:185782$12044 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377741,10 +349111,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 3'111 - connect \Y $gt$libresoc.v:184474$12060_Y + connect \Y $gt$libresoc.v:185782$12044_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184475$12061 + cell $gt $gt$libresoc.v:185783$12045 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377752,10 +349122,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1000 - connect \Y $gt$libresoc.v:184475$12061_Y + connect \Y $gt$libresoc.v:185783$12045_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184476$12062 + cell $gt $gt$libresoc.v:185784$12046 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377763,10 +349133,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 1'0 - connect \Y $gt$libresoc.v:184476$12062_Y + connect \Y $gt$libresoc.v:185784$12046_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184477$12063 + cell $gt $gt$libresoc.v:185785$12047 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377774,10 +349144,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1001 - connect \Y $gt$libresoc.v:184477$12063_Y + connect \Y $gt$libresoc.v:185785$12047_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184478$12064 + cell $gt $gt$libresoc.v:185786$12048 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377785,10 +349155,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1010 - connect \Y $gt$libresoc.v:184478$12064_Y + connect \Y $gt$libresoc.v:185786$12048_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184479$12065 + cell $gt $gt$libresoc.v:185787$12049 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377796,10 +349166,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1011 - connect \Y $gt$libresoc.v:184479$12065_Y + connect \Y $gt$libresoc.v:185787$12049_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184480$12066 + cell $gt $gt$libresoc.v:185788$12050 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377807,10 +349177,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1100 - connect \Y $gt$libresoc.v:184480$12066_Y + connect \Y $gt$libresoc.v:185788$12050_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184481$12067 + cell $gt $gt$libresoc.v:185789$12051 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377818,10 +349188,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1101 - connect \Y $gt$libresoc.v:184481$12067_Y + connect \Y $gt$libresoc.v:185789$12051_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184482$12068 + cell $gt $gt$libresoc.v:185790$12052 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377829,10 +349199,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1110 - connect \Y $gt$libresoc.v:184482$12068_Y + connect \Y $gt$libresoc.v:185790$12052_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184483$12069 + cell $gt $gt$libresoc.v:185791$12053 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377840,10 +349210,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 4'1111 - connect \Y $gt$libresoc.v:184483$12069_Y + connect \Y $gt$libresoc.v:185791$12053_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184484$12070 + cell $gt $gt$libresoc.v:185792$12054 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377851,10 +349221,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10000 - connect \Y $gt$libresoc.v:184484$12070_Y + connect \Y $gt$libresoc.v:185792$12054_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184485$12071 + cell $gt $gt$libresoc.v:185793$12055 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377862,10 +349232,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10001 - connect \Y $gt$libresoc.v:184485$12071_Y + connect \Y $gt$libresoc.v:185793$12055_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184486$12072 + cell $gt $gt$libresoc.v:185794$12056 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377873,10 +349243,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10010 - connect \Y $gt$libresoc.v:184486$12072_Y + connect \Y $gt$libresoc.v:185794$12056_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184487$12073 + cell $gt $gt$libresoc.v:185795$12057 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377884,10 +349254,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 1'1 - connect \Y $gt$libresoc.v:184487$12073_Y + connect \Y $gt$libresoc.v:185795$12057_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184488$12074 + cell $gt $gt$libresoc.v:185796$12058 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377895,10 +349265,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10011 - connect \Y $gt$libresoc.v:184488$12074_Y + connect \Y $gt$libresoc.v:185796$12058_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184489$12075 + cell $gt $gt$libresoc.v:185797$12059 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377906,10 +349276,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10100 - connect \Y $gt$libresoc.v:184489$12075_Y + connect \Y $gt$libresoc.v:185797$12059_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184490$12076 + cell $gt $gt$libresoc.v:185798$12060 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377917,10 +349287,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10101 - connect \Y $gt$libresoc.v:184490$12076_Y + connect \Y $gt$libresoc.v:185798$12060_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184491$12077 + cell $gt $gt$libresoc.v:185799$12061 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377928,10 +349298,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10110 - connect \Y $gt$libresoc.v:184491$12077_Y + connect \Y $gt$libresoc.v:185799$12061_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184492$12078 + cell $gt $gt$libresoc.v:185800$12062 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377939,10 +349309,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'10111 - connect \Y $gt$libresoc.v:184492$12078_Y + connect \Y $gt$libresoc.v:185800$12062_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184493$12079 + cell $gt $gt$libresoc.v:185801$12063 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377950,10 +349320,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11000 - connect \Y $gt$libresoc.v:184493$12079_Y + connect \Y $gt$libresoc.v:185801$12063_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184494$12080 + cell $gt $gt$libresoc.v:185802$12064 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377961,10 +349331,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11001 - connect \Y $gt$libresoc.v:184494$12080_Y + connect \Y $gt$libresoc.v:185802$12064_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184495$12081 + cell $gt $gt$libresoc.v:185803$12065 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377972,10 +349342,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11010 - connect \Y $gt$libresoc.v:184495$12081_Y + connect \Y $gt$libresoc.v:185803$12065_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184496$12082 + cell $gt $gt$libresoc.v:185804$12066 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377983,10 +349353,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11011 - connect \Y $gt$libresoc.v:184496$12082_Y + connect \Y $gt$libresoc.v:185804$12066_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184497$12083 + cell $gt $gt$libresoc.v:185805$12067 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -377994,10 +349364,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11100 - connect \Y $gt$libresoc.v:184497$12083_Y + connect \Y $gt$libresoc.v:185805$12067_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184498$12084 + cell $gt $gt$libresoc.v:185806$12068 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -378005,10 +349375,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 2'10 - connect \Y $gt$libresoc.v:184498$12084_Y + connect \Y $gt$libresoc.v:185806$12068_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184499$12085 + cell $gt $gt$libresoc.v:185807$12069 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -378016,10 +349386,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11101 - connect \Y $gt$libresoc.v:184499$12085_Y + connect \Y $gt$libresoc.v:185807$12069_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184500$12086 + cell $gt $gt$libresoc.v:185808$12070 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -378027,10 +349397,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11110 - connect \Y $gt$libresoc.v:184500$12086_Y + connect \Y $gt$libresoc.v:185808$12070_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184501$12087 + cell $gt $gt$libresoc.v:185809$12071 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -378038,10 +349408,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 5'11111 - connect \Y $gt$libresoc.v:184501$12087_Y + connect \Y $gt$libresoc.v:185809$12071_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184502$12088 + cell $gt $gt$libresoc.v:185810$12072 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -378049,10 +349419,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100000 - connect \Y $gt$libresoc.v:184502$12088_Y + connect \Y $gt$libresoc.v:185810$12072_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184503$12089 + cell $gt $gt$libresoc.v:185811$12073 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -378060,10 +349430,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100001 - connect \Y $gt$libresoc.v:184503$12089_Y + connect \Y $gt$libresoc.v:185811$12073_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184504$12090 + cell $gt $gt$libresoc.v:185812$12074 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -378071,10 +349441,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100010 - connect \Y $gt$libresoc.v:184504$12090_Y + connect \Y $gt$libresoc.v:185812$12074_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184505$12091 + cell $gt $gt$libresoc.v:185813$12075 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -378082,10 +349452,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100011 - connect \Y $gt$libresoc.v:184505$12091_Y + connect \Y $gt$libresoc.v:185813$12075_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184506$12092 + cell $gt $gt$libresoc.v:185814$12076 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -378093,10 +349463,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100100 - connect \Y $gt$libresoc.v:184506$12092_Y + connect \Y $gt$libresoc.v:185814$12076_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184507$12093 + cell $gt $gt$libresoc.v:185815$12077 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -378104,10 +349474,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100101 - connect \Y $gt$libresoc.v:184507$12093_Y + connect \Y $gt$libresoc.v:185815$12077_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184508$12094 + cell $gt $gt$libresoc.v:185816$12078 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -378115,10 +349485,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100110 - connect \Y $gt$libresoc.v:184508$12094_Y + connect \Y $gt$libresoc.v:185816$12078_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184509$12095 + cell $gt $gt$libresoc.v:185817$12079 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -378126,10 +349496,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 2'11 - connect \Y $gt$libresoc.v:184509$12095_Y + connect \Y $gt$libresoc.v:185817$12079_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184510$12096 + cell $gt $gt$libresoc.v:185818$12080 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -378137,10 +349507,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'100111 - connect \Y $gt$libresoc.v:184510$12096_Y + connect \Y $gt$libresoc.v:185818$12080_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184511$12097 + cell $gt $gt$libresoc.v:185819$12081 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -378148,10 +349518,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101000 - connect \Y $gt$libresoc.v:184511$12097_Y + connect \Y $gt$libresoc.v:185819$12081_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184512$12098 + cell $gt $gt$libresoc.v:185820$12082 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -378159,10 +349529,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101001 - connect \Y $gt$libresoc.v:184512$12098_Y + connect \Y $gt$libresoc.v:185820$12082_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184513$12099 + cell $gt $gt$libresoc.v:185821$12083 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -378170,10 +349540,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101010 - connect \Y $gt$libresoc.v:184513$12099_Y + connect \Y $gt$libresoc.v:185821$12083_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184514$12100 + cell $gt $gt$libresoc.v:185822$12084 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -378181,10 +349551,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101011 - connect \Y $gt$libresoc.v:184514$12100_Y + connect \Y $gt$libresoc.v:185822$12084_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184515$12101 + cell $gt $gt$libresoc.v:185823$12085 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -378192,10 +349562,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101100 - connect \Y $gt$libresoc.v:184515$12101_Y + connect \Y $gt$libresoc.v:185823$12085_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184516$12102 + cell $gt $gt$libresoc.v:185824$12086 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -378203,10 +349573,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101101 - connect \Y $gt$libresoc.v:184516$12102_Y + connect \Y $gt$libresoc.v:185824$12086_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184517$12103 + cell $gt $gt$libresoc.v:185825$12087 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -378214,10 +349584,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101110 - connect \Y $gt$libresoc.v:184517$12103_Y + connect \Y $gt$libresoc.v:185825$12087_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184518$12104 + cell $gt $gt$libresoc.v:185826$12088 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -378225,10 +349595,10 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'101111 - connect \Y $gt$libresoc.v:184518$12104_Y + connect \Y $gt$libresoc.v:185826$12088_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:26" - cell $gt $gt$libresoc.v:184519$12105 + cell $gt $gt$libresoc.v:185827$12089 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -378236,18 +349606,18 @@ module \right_mask parameter \Y_WIDTH 1 connect \A \shift connect \B 6'110000 - connect \Y $gt$libresoc.v:184519$12105_Y + connect \Y $gt$libresoc.v:185827$12089_Y end - attribute \src "libresoc.v:184322.7-184322.20" - process $proc$libresoc.v:184322$12107 + attribute \src "libresoc.v:185630.7-185630.20" + process $proc$libresoc.v:185630$12091 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184520.3-184907.6" - process $proc$libresoc.v:184520$12106 + attribute \src "libresoc.v:185828.3-186215.6" + process $proc$libresoc.v:185828$12090 assign { } { } assign { } { } assign $0\mask[63:0] [0] $1\mask[0:0] @@ -378314,9 +349684,9 @@ module \right_mask assign $0\mask[63:0] [61] $62\mask[61:61] assign $0\mask[63:0] [62] $63\mask[62:62] assign $0\mask[63:0] [63] $64\mask[63:63] - attribute \src "libresoc.v:184521.5-184521.29" + attribute \src "libresoc.v:185829.5-185829.29" switch \initial - attribute \src "libresoc.v:184521.9-184521.17" + attribute \src "libresoc.v:185829.9-185829.17" case 1'1 case end @@ -378899,102 +350269,102 @@ module \right_mask sync always update \mask $0\mask[63:0] end - connect \$9 $gt$libresoc.v:184456$12042_Y - connect \$99 $gt$libresoc.v:184457$12043_Y - connect \$101 $gt$libresoc.v:184458$12044_Y - connect \$103 $gt$libresoc.v:184459$12045_Y - connect \$105 $gt$libresoc.v:184460$12046_Y - connect \$107 $gt$libresoc.v:184461$12047_Y - connect \$109 $gt$libresoc.v:184462$12048_Y - connect \$111 $gt$libresoc.v:184463$12049_Y - connect \$113 $gt$libresoc.v:184464$12050_Y - connect \$115 $gt$libresoc.v:184465$12051_Y - connect \$117 $gt$libresoc.v:184466$12052_Y - connect \$11 $gt$libresoc.v:184467$12053_Y - connect \$119 $gt$libresoc.v:184468$12054_Y - connect \$121 $gt$libresoc.v:184469$12055_Y - connect \$123 $gt$libresoc.v:184470$12056_Y - connect \$125 $gt$libresoc.v:184471$12057_Y - connect \$127 $gt$libresoc.v:184472$12058_Y - connect \$13 $gt$libresoc.v:184473$12059_Y - connect \$15 $gt$libresoc.v:184474$12060_Y - connect \$17 $gt$libresoc.v:184475$12061_Y - connect \$1 $gt$libresoc.v:184476$12062_Y - connect \$19 $gt$libresoc.v:184477$12063_Y - connect \$21 $gt$libresoc.v:184478$12064_Y - connect \$23 $gt$libresoc.v:184479$12065_Y - connect \$25 $gt$libresoc.v:184480$12066_Y - connect \$27 $gt$libresoc.v:184481$12067_Y - connect \$29 $gt$libresoc.v:184482$12068_Y - connect \$31 $gt$libresoc.v:184483$12069_Y - connect \$33 $gt$libresoc.v:184484$12070_Y - connect \$35 $gt$libresoc.v:184485$12071_Y - connect \$37 $gt$libresoc.v:184486$12072_Y - connect \$3 $gt$libresoc.v:184487$12073_Y - connect \$39 $gt$libresoc.v:184488$12074_Y - connect \$41 $gt$libresoc.v:184489$12075_Y - connect \$43 $gt$libresoc.v:184490$12076_Y - connect \$45 $gt$libresoc.v:184491$12077_Y - connect \$47 $gt$libresoc.v:184492$12078_Y - connect \$49 $gt$libresoc.v:184493$12079_Y - connect \$51 $gt$libresoc.v:184494$12080_Y - connect \$53 $gt$libresoc.v:184495$12081_Y - connect \$55 $gt$libresoc.v:184496$12082_Y - connect \$57 $gt$libresoc.v:184497$12083_Y - connect \$5 $gt$libresoc.v:184498$12084_Y - connect \$59 $gt$libresoc.v:184499$12085_Y - connect \$61 $gt$libresoc.v:184500$12086_Y - connect \$63 $gt$libresoc.v:184501$12087_Y - connect \$65 $gt$libresoc.v:184502$12088_Y - connect \$67 $gt$libresoc.v:184503$12089_Y - connect \$69 $gt$libresoc.v:184504$12090_Y - connect \$71 $gt$libresoc.v:184505$12091_Y - connect \$73 $gt$libresoc.v:184506$12092_Y - connect \$75 $gt$libresoc.v:184507$12093_Y - connect \$77 $gt$libresoc.v:184508$12094_Y - connect \$7 $gt$libresoc.v:184509$12095_Y - connect \$79 $gt$libresoc.v:184510$12096_Y - connect \$81 $gt$libresoc.v:184511$12097_Y - connect \$83 $gt$libresoc.v:184512$12098_Y - connect \$85 $gt$libresoc.v:184513$12099_Y - connect \$87 $gt$libresoc.v:184514$12100_Y - connect \$89 $gt$libresoc.v:184515$12101_Y - connect \$91 $gt$libresoc.v:184516$12102_Y - connect \$93 $gt$libresoc.v:184517$12103_Y - connect \$95 $gt$libresoc.v:184518$12104_Y - connect \$97 $gt$libresoc.v:184519$12105_Y + connect \$9 $gt$libresoc.v:185764$12026_Y + connect \$99 $gt$libresoc.v:185765$12027_Y + connect \$101 $gt$libresoc.v:185766$12028_Y + connect \$103 $gt$libresoc.v:185767$12029_Y + connect \$105 $gt$libresoc.v:185768$12030_Y + connect \$107 $gt$libresoc.v:185769$12031_Y + connect \$109 $gt$libresoc.v:185770$12032_Y + connect \$111 $gt$libresoc.v:185771$12033_Y + connect \$113 $gt$libresoc.v:185772$12034_Y + connect \$115 $gt$libresoc.v:185773$12035_Y + connect \$117 $gt$libresoc.v:185774$12036_Y + connect \$11 $gt$libresoc.v:185775$12037_Y + connect \$119 $gt$libresoc.v:185776$12038_Y + connect \$121 $gt$libresoc.v:185777$12039_Y + connect \$123 $gt$libresoc.v:185778$12040_Y + connect \$125 $gt$libresoc.v:185779$12041_Y + connect \$127 $gt$libresoc.v:185780$12042_Y + connect \$13 $gt$libresoc.v:185781$12043_Y + connect \$15 $gt$libresoc.v:185782$12044_Y + connect \$17 $gt$libresoc.v:185783$12045_Y + connect \$1 $gt$libresoc.v:185784$12046_Y + connect \$19 $gt$libresoc.v:185785$12047_Y + connect \$21 $gt$libresoc.v:185786$12048_Y + connect \$23 $gt$libresoc.v:185787$12049_Y + connect \$25 $gt$libresoc.v:185788$12050_Y + connect \$27 $gt$libresoc.v:185789$12051_Y + connect \$29 $gt$libresoc.v:185790$12052_Y + connect \$31 $gt$libresoc.v:185791$12053_Y + connect \$33 $gt$libresoc.v:185792$12054_Y + connect \$35 $gt$libresoc.v:185793$12055_Y + connect \$37 $gt$libresoc.v:185794$12056_Y + connect \$3 $gt$libresoc.v:185795$12057_Y + connect \$39 $gt$libresoc.v:185796$12058_Y + connect \$41 $gt$libresoc.v:185797$12059_Y + connect \$43 $gt$libresoc.v:185798$12060_Y + connect \$45 $gt$libresoc.v:185799$12061_Y + connect \$47 $gt$libresoc.v:185800$12062_Y + connect \$49 $gt$libresoc.v:185801$12063_Y + connect \$51 $gt$libresoc.v:185802$12064_Y + connect \$53 $gt$libresoc.v:185803$12065_Y + connect \$55 $gt$libresoc.v:185804$12066_Y + connect \$57 $gt$libresoc.v:185805$12067_Y + connect \$5 $gt$libresoc.v:185806$12068_Y + connect \$59 $gt$libresoc.v:185807$12069_Y + connect \$61 $gt$libresoc.v:185808$12070_Y + connect \$63 $gt$libresoc.v:185809$12071_Y + connect \$65 $gt$libresoc.v:185810$12072_Y + connect \$67 $gt$libresoc.v:185811$12073_Y + connect \$69 $gt$libresoc.v:185812$12074_Y + connect \$71 $gt$libresoc.v:185813$12075_Y + connect \$73 $gt$libresoc.v:185814$12076_Y + connect \$75 $gt$libresoc.v:185815$12077_Y + connect \$77 $gt$libresoc.v:185816$12078_Y + connect \$7 $gt$libresoc.v:185817$12079_Y + connect \$79 $gt$libresoc.v:185818$12080_Y + connect \$81 $gt$libresoc.v:185819$12081_Y + connect \$83 $gt$libresoc.v:185820$12082_Y + connect \$85 $gt$libresoc.v:185821$12083_Y + connect \$87 $gt$libresoc.v:185822$12084_Y + connect \$89 $gt$libresoc.v:185823$12085_Y + connect \$91 $gt$libresoc.v:185824$12086_Y + connect \$93 $gt$libresoc.v:185825$12087_Y + connect \$95 $gt$libresoc.v:185826$12088_Y + connect \$97 $gt$libresoc.v:185827$12089_Y end -attribute \src "libresoc.v:184912.1-184970.10" +attribute \src "libresoc.v:186220.1-186278.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.rok_l" attribute \generator "nMigen" module \rok_l - attribute \src "libresoc.v:184913.7-184913.20" + attribute \src "libresoc.v:186221.7-186221.20" wire $0\initial[0:0] - attribute \src "libresoc.v:184958.3-184966.6" - wire $0\q_int$next[0:0]$12118 - attribute \src "libresoc.v:184956.3-184957.27" + attribute \src "libresoc.v:186266.3-186274.6" + wire $0\q_int$next[0:0]$12102 + attribute \src "libresoc.v:186264.3-186265.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:184958.3-184966.6" - wire $1\q_int$next[0:0]$12119 - attribute \src "libresoc.v:184935.7-184935.19" + attribute \src "libresoc.v:186266.3-186274.6" + wire $1\q_int$next[0:0]$12103 + attribute \src "libresoc.v:186243.7-186243.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:184948.17-184948.96" - wire $and$libresoc.v:184948$12108_Y - attribute \src "libresoc.v:184953.17-184953.96" - wire $and$libresoc.v:184953$12113_Y - attribute \src "libresoc.v:184950.18-184950.94" - wire $not$libresoc.v:184950$12110_Y - attribute \src "libresoc.v:184952.17-184952.93" - wire $not$libresoc.v:184952$12112_Y - attribute \src "libresoc.v:184955.17-184955.93" - wire $not$libresoc.v:184955$12115_Y - attribute \src "libresoc.v:184949.18-184949.99" - wire $or$libresoc.v:184949$12109_Y - attribute \src "libresoc.v:184951.18-184951.100" - wire $or$libresoc.v:184951$12111_Y - attribute \src "libresoc.v:184954.17-184954.98" - wire $or$libresoc.v:184954$12114_Y + attribute \src "libresoc.v:186256.17-186256.96" + wire $and$libresoc.v:186256$12092_Y + attribute \src "libresoc.v:186261.17-186261.96" + wire $and$libresoc.v:186261$12097_Y + attribute \src "libresoc.v:186258.18-186258.94" + wire $not$libresoc.v:186258$12094_Y + attribute \src "libresoc.v:186260.17-186260.93" + wire $not$libresoc.v:186260$12096_Y + attribute \src "libresoc.v:186263.17-186263.93" + wire $not$libresoc.v:186263$12099_Y + attribute \src "libresoc.v:186257.18-186257.99" + wire $or$libresoc.v:186257$12093_Y + attribute \src "libresoc.v:186259.18-186259.100" + wire $or$libresoc.v:186259$12095_Y + attribute \src "libresoc.v:186262.17-186262.98" + wire $or$libresoc.v:186262$12098_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -379011,11 +350381,11 @@ module \rok_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:184913.7-184913.15" + attribute \src "libresoc.v:186221.7-186221.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -379032,7 +350402,7 @@ module \rok_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:184948$12108 + cell $and $and$libresoc.v:186256$12092 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379040,10 +350410,10 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:184948$12108_Y + connect \Y $and$libresoc.v:186256$12092_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:184953$12113 + cell $and $and$libresoc.v:186261$12097 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379051,34 +350421,34 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:184953$12113_Y + connect \Y $and$libresoc.v:186261$12097_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:184950$12110 + cell $not $not$libresoc.v:186258$12094 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:184950$12110_Y + connect \Y $not$libresoc.v:186258$12094_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:184952$12112 + cell $not $not$libresoc.v:186260$12096 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:184952$12112_Y + connect \Y $not$libresoc.v:186260$12096_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:184955$12115 + cell $not $not$libresoc.v:186263$12099 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:184955$12115_Y + connect \Y $not$libresoc.v:186263$12099_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:184949$12109 + cell $or $or$libresoc.v:186257$12093 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379086,10 +350456,10 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:184949$12109_Y + connect \Y $or$libresoc.v:186257$12093_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:184951$12111 + cell $or $or$libresoc.v:186259$12095 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379097,10 +350467,10 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:184951$12111_Y + connect \Y $or$libresoc.v:186259$12095_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:184954$12114 + cell $or $or$libresoc.v:186262$12098 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379108,39 +350478,39 @@ module \rok_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:184954$12114_Y + connect \Y $or$libresoc.v:186262$12098_Y end - attribute \src "libresoc.v:184913.7-184913.20" - process $proc$libresoc.v:184913$12120 + attribute \src "libresoc.v:186221.7-186221.20" + process $proc$libresoc.v:186221$12104 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184935.7-184935.19" - process $proc$libresoc.v:184935$12121 + attribute \src "libresoc.v:186243.7-186243.19" + process $proc$libresoc.v:186243$12105 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:184956.3-184957.27" - process $proc$libresoc.v:184956$12116 + attribute \src "libresoc.v:186264.3-186265.27" + process $proc$libresoc.v:186264$12100 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:184958.3-184966.6" - process $proc$libresoc.v:184958$12117 + attribute \src "libresoc.v:186266.3-186274.6" + process $proc$libresoc.v:186266$12101 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12118 $1\q_int$next[0:0]$12119 - attribute \src "libresoc.v:184959.5-184959.29" + assign $0\q_int$next[0:0]$12102 $1\q_int$next[0:0]$12103 + attribute \src "libresoc.v:186267.5-186267.29" switch \initial - attribute \src "libresoc.v:184959.9-184959.17" + attribute \src "libresoc.v:186267.9-186267.17" case 1'1 case end @@ -379149,56 +350519,56 @@ module \rok_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12119 1'0 + assign $1\q_int$next[0:0]$12103 1'0 case - assign $1\q_int$next[0:0]$12119 \$5 + assign $1\q_int$next[0:0]$12103 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12118 + update \q_int$next $0\q_int$next[0:0]$12102 end - connect \$9 $and$libresoc.v:184948$12108_Y - connect \$11 $or$libresoc.v:184949$12109_Y - connect \$13 $not$libresoc.v:184950$12110_Y - connect \$15 $or$libresoc.v:184951$12111_Y - connect \$1 $not$libresoc.v:184952$12112_Y - connect \$3 $and$libresoc.v:184953$12113_Y - connect \$5 $or$libresoc.v:184954$12114_Y - connect \$7 $not$libresoc.v:184955$12115_Y + connect \$9 $and$libresoc.v:186256$12092_Y + connect \$11 $or$libresoc.v:186257$12093_Y + connect \$13 $not$libresoc.v:186258$12094_Y + connect \$15 $or$libresoc.v:186259$12095_Y + connect \$1 $not$libresoc.v:186260$12096_Y + connect \$3 $and$libresoc.v:186261$12097_Y + connect \$5 $or$libresoc.v:186262$12098_Y + connect \$7 $not$libresoc.v:186263$12099_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:184974.1-185032.10" +attribute \src "libresoc.v:186282.1-186340.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.rok_l" attribute \generator "nMigen" module \rok_l$105 - attribute \src "libresoc.v:184975.7-184975.20" + attribute \src "libresoc.v:186283.7-186283.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185020.3-185028.6" - wire $0\q_int$next[0:0]$12132 - attribute \src "libresoc.v:185018.3-185019.27" + attribute \src "libresoc.v:186328.3-186336.6" + wire $0\q_int$next[0:0]$12116 + attribute \src "libresoc.v:186326.3-186327.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:185020.3-185028.6" - wire $1\q_int$next[0:0]$12133 - attribute \src "libresoc.v:184997.7-184997.19" + attribute \src "libresoc.v:186328.3-186336.6" + wire $1\q_int$next[0:0]$12117 + attribute \src "libresoc.v:186305.7-186305.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:185010.17-185010.96" - wire $and$libresoc.v:185010$12122_Y - attribute \src "libresoc.v:185015.17-185015.96" - wire $and$libresoc.v:185015$12127_Y - attribute \src "libresoc.v:185012.18-185012.94" - wire $not$libresoc.v:185012$12124_Y - attribute \src "libresoc.v:185014.17-185014.93" - wire $not$libresoc.v:185014$12126_Y - attribute \src "libresoc.v:185017.17-185017.93" - wire $not$libresoc.v:185017$12129_Y - attribute \src "libresoc.v:185011.18-185011.99" - wire $or$libresoc.v:185011$12123_Y - attribute \src "libresoc.v:185013.18-185013.100" - wire $or$libresoc.v:185013$12125_Y - attribute \src "libresoc.v:185016.17-185016.98" - wire $or$libresoc.v:185016$12128_Y + attribute \src "libresoc.v:186318.17-186318.96" + wire $and$libresoc.v:186318$12106_Y + attribute \src "libresoc.v:186323.17-186323.96" + wire $and$libresoc.v:186323$12111_Y + attribute \src "libresoc.v:186320.18-186320.94" + wire $not$libresoc.v:186320$12108_Y + attribute \src "libresoc.v:186322.17-186322.93" + wire $not$libresoc.v:186322$12110_Y + attribute \src "libresoc.v:186325.17-186325.93" + wire $not$libresoc.v:186325$12113_Y + attribute \src "libresoc.v:186319.18-186319.99" + wire $or$libresoc.v:186319$12107_Y + attribute \src "libresoc.v:186321.18-186321.100" + wire $or$libresoc.v:186321$12109_Y + attribute \src "libresoc.v:186324.17-186324.98" + wire $or$libresoc.v:186324$12112_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -379215,11 +350585,11 @@ module \rok_l$105 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:184975.7-184975.15" + attribute \src "libresoc.v:186283.7-186283.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -379236,7 +350606,7 @@ module \rok_l$105 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:185010$12122 + cell $and $and$libresoc.v:186318$12106 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379244,10 +350614,10 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:185010$12122_Y + connect \Y $and$libresoc.v:186318$12106_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:185015$12127 + cell $and $and$libresoc.v:186323$12111 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379255,34 +350625,34 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:185015$12127_Y + connect \Y $and$libresoc.v:186323$12111_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:185012$12124 + cell $not $not$libresoc.v:186320$12108 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:185012$12124_Y + connect \Y $not$libresoc.v:186320$12108_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:185014$12126 + cell $not $not$libresoc.v:186322$12110 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185014$12126_Y + connect \Y $not$libresoc.v:186322$12110_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:185017$12129 + cell $not $not$libresoc.v:186325$12113 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185017$12129_Y + connect \Y $not$libresoc.v:186325$12113_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:185011$12123 + cell $or $or$libresoc.v:186319$12107 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379290,10 +350660,10 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:185011$12123_Y + connect \Y $or$libresoc.v:186319$12107_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:185013$12125 + cell $or $or$libresoc.v:186321$12109 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379301,10 +350671,10 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:185013$12125_Y + connect \Y $or$libresoc.v:186321$12109_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:185016$12128 + cell $or $or$libresoc.v:186324$12112 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379312,39 +350682,39 @@ module \rok_l$105 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:185016$12128_Y + connect \Y $or$libresoc.v:186324$12112_Y end - attribute \src "libresoc.v:184975.7-184975.20" - process $proc$libresoc.v:184975$12134 + attribute \src "libresoc.v:186283.7-186283.20" + process $proc$libresoc.v:186283$12118 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:184997.7-184997.19" - process $proc$libresoc.v:184997$12135 + attribute \src "libresoc.v:186305.7-186305.19" + process $proc$libresoc.v:186305$12119 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:185018.3-185019.27" - process $proc$libresoc.v:185018$12130 + attribute \src "libresoc.v:186326.3-186327.27" + process $proc$libresoc.v:186326$12114 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:185020.3-185028.6" - process $proc$libresoc.v:185020$12131 + attribute \src "libresoc.v:186328.3-186336.6" + process $proc$libresoc.v:186328$12115 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12132 $1\q_int$next[0:0]$12133 - attribute \src "libresoc.v:185021.5-185021.29" + assign $0\q_int$next[0:0]$12116 $1\q_int$next[0:0]$12117 + attribute \src "libresoc.v:186329.5-186329.29" switch \initial - attribute \src "libresoc.v:185021.9-185021.17" + attribute \src "libresoc.v:186329.9-186329.17" case 1'1 case end @@ -379353,56 +350723,56 @@ module \rok_l$105 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12133 1'0 + assign $1\q_int$next[0:0]$12117 1'0 case - assign $1\q_int$next[0:0]$12133 \$5 + assign $1\q_int$next[0:0]$12117 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12132 + update \q_int$next $0\q_int$next[0:0]$12116 end - connect \$9 $and$libresoc.v:185010$12122_Y - connect \$11 $or$libresoc.v:185011$12123_Y - connect \$13 $not$libresoc.v:185012$12124_Y - connect \$15 $or$libresoc.v:185013$12125_Y - connect \$1 $not$libresoc.v:185014$12126_Y - connect \$3 $and$libresoc.v:185015$12127_Y - connect \$5 $or$libresoc.v:185016$12128_Y - connect \$7 $not$libresoc.v:185017$12129_Y + connect \$9 $and$libresoc.v:186318$12106_Y + connect \$11 $or$libresoc.v:186319$12107_Y + connect \$13 $not$libresoc.v:186320$12108_Y + connect \$15 $or$libresoc.v:186321$12109_Y + connect \$1 $not$libresoc.v:186322$12110_Y + connect \$3 $and$libresoc.v:186323$12111_Y + connect \$5 $or$libresoc.v:186324$12112_Y + connect \$7 $not$libresoc.v:186325$12113_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:185036.1-185094.10" +attribute \src "libresoc.v:186344.1-186402.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.rok_l" attribute \generator "nMigen" module \rok_l$123 - attribute \src "libresoc.v:185037.7-185037.20" + attribute \src "libresoc.v:186345.7-186345.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185082.3-185090.6" - wire $0\q_int$next[0:0]$12146 - attribute \src "libresoc.v:185080.3-185081.27" + attribute \src "libresoc.v:186390.3-186398.6" + wire $0\q_int$next[0:0]$12130 + attribute \src "libresoc.v:186388.3-186389.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:185082.3-185090.6" - wire $1\q_int$next[0:0]$12147 - attribute \src "libresoc.v:185059.7-185059.19" + attribute \src "libresoc.v:186390.3-186398.6" + wire $1\q_int$next[0:0]$12131 + attribute \src "libresoc.v:186367.7-186367.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:185072.17-185072.96" - wire $and$libresoc.v:185072$12136_Y - attribute \src "libresoc.v:185077.17-185077.96" - wire $and$libresoc.v:185077$12141_Y - attribute \src "libresoc.v:185074.18-185074.94" - wire $not$libresoc.v:185074$12138_Y - attribute \src "libresoc.v:185076.17-185076.93" - wire $not$libresoc.v:185076$12140_Y - attribute \src "libresoc.v:185079.17-185079.93" - wire $not$libresoc.v:185079$12143_Y - attribute \src "libresoc.v:185073.18-185073.99" - wire $or$libresoc.v:185073$12137_Y - attribute \src "libresoc.v:185075.18-185075.100" - wire $or$libresoc.v:185075$12139_Y - attribute \src "libresoc.v:185078.17-185078.98" - wire $or$libresoc.v:185078$12142_Y + attribute \src "libresoc.v:186380.17-186380.96" + wire $and$libresoc.v:186380$12120_Y + attribute \src "libresoc.v:186385.17-186385.96" + wire $and$libresoc.v:186385$12125_Y + attribute \src "libresoc.v:186382.18-186382.94" + wire $not$libresoc.v:186382$12122_Y + attribute \src "libresoc.v:186384.17-186384.93" + wire $not$libresoc.v:186384$12124_Y + attribute \src "libresoc.v:186387.17-186387.93" + wire $not$libresoc.v:186387$12127_Y + attribute \src "libresoc.v:186381.18-186381.99" + wire $or$libresoc.v:186381$12121_Y + attribute \src "libresoc.v:186383.18-186383.100" + wire $or$libresoc.v:186383$12123_Y + attribute \src "libresoc.v:186386.17-186386.98" + wire $or$libresoc.v:186386$12126_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -379419,11 +350789,11 @@ module \rok_l$123 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:185037.7-185037.15" + attribute \src "libresoc.v:186345.7-186345.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -379440,7 +350810,7 @@ module \rok_l$123 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:185072$12136 + cell $and $and$libresoc.v:186380$12120 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379448,10 +350818,10 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:185072$12136_Y + connect \Y $and$libresoc.v:186380$12120_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:185077$12141 + cell $and $and$libresoc.v:186385$12125 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379459,34 +350829,34 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:185077$12141_Y + connect \Y $and$libresoc.v:186385$12125_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:185074$12138 + cell $not $not$libresoc.v:186382$12122 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:185074$12138_Y + connect \Y $not$libresoc.v:186382$12122_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:185076$12140 + cell $not $not$libresoc.v:186384$12124 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185076$12140_Y + connect \Y $not$libresoc.v:186384$12124_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:185079$12143 + cell $not $not$libresoc.v:186387$12127 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185079$12143_Y + connect \Y $not$libresoc.v:186387$12127_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:185073$12137 + cell $or $or$libresoc.v:186381$12121 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379494,10 +350864,10 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:185073$12137_Y + connect \Y $or$libresoc.v:186381$12121_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:185075$12139 + cell $or $or$libresoc.v:186383$12123 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379505,10 +350875,10 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:185075$12139_Y + connect \Y $or$libresoc.v:186383$12123_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:185078$12142 + cell $or $or$libresoc.v:186386$12126 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379516,39 +350886,39 @@ module \rok_l$123 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:185078$12142_Y + connect \Y $or$libresoc.v:186386$12126_Y end - attribute \src "libresoc.v:185037.7-185037.20" - process $proc$libresoc.v:185037$12148 + attribute \src "libresoc.v:186345.7-186345.20" + process $proc$libresoc.v:186345$12132 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185059.7-185059.19" - process $proc$libresoc.v:185059$12149 + attribute \src "libresoc.v:186367.7-186367.19" + process $proc$libresoc.v:186367$12133 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:185080.3-185081.27" - process $proc$libresoc.v:185080$12144 + attribute \src "libresoc.v:186388.3-186389.27" + process $proc$libresoc.v:186388$12128 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:185082.3-185090.6" - process $proc$libresoc.v:185082$12145 + attribute \src "libresoc.v:186390.3-186398.6" + process $proc$libresoc.v:186390$12129 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12146 $1\q_int$next[0:0]$12147 - attribute \src "libresoc.v:185083.5-185083.29" + assign $0\q_int$next[0:0]$12130 $1\q_int$next[0:0]$12131 + attribute \src "libresoc.v:186391.5-186391.29" switch \initial - attribute \src "libresoc.v:185083.9-185083.17" + attribute \src "libresoc.v:186391.9-186391.17" case 1'1 case end @@ -379557,56 +350927,56 @@ module \rok_l$123 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12147 1'0 + assign $1\q_int$next[0:0]$12131 1'0 case - assign $1\q_int$next[0:0]$12147 \$5 + assign $1\q_int$next[0:0]$12131 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12146 + update \q_int$next $0\q_int$next[0:0]$12130 end - connect \$9 $and$libresoc.v:185072$12136_Y - connect \$11 $or$libresoc.v:185073$12137_Y - connect \$13 $not$libresoc.v:185074$12138_Y - connect \$15 $or$libresoc.v:185075$12139_Y - connect \$1 $not$libresoc.v:185076$12140_Y - connect \$3 $and$libresoc.v:185077$12141_Y - connect \$5 $or$libresoc.v:185078$12142_Y - connect \$7 $not$libresoc.v:185079$12143_Y + connect \$9 $and$libresoc.v:186380$12120_Y + connect \$11 $or$libresoc.v:186381$12121_Y + connect \$13 $not$libresoc.v:186382$12122_Y + connect \$15 $or$libresoc.v:186383$12123_Y + connect \$1 $not$libresoc.v:186384$12124_Y + connect \$3 $and$libresoc.v:186385$12125_Y + connect \$5 $or$libresoc.v:186386$12126_Y + connect \$7 $not$libresoc.v:186387$12127_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:185098.1-185156.10" +attribute \src "libresoc.v:186406.1-186464.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.rok_l" attribute \generator "nMigen" module \rok_l$14 - attribute \src "libresoc.v:185099.7-185099.20" + attribute \src "libresoc.v:186407.7-186407.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185144.3-185152.6" - wire $0\q_int$next[0:0]$12160 - attribute \src "libresoc.v:185142.3-185143.27" + attribute \src "libresoc.v:186452.3-186460.6" + wire $0\q_int$next[0:0]$12144 + attribute \src "libresoc.v:186450.3-186451.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:185144.3-185152.6" - wire $1\q_int$next[0:0]$12161 - attribute \src "libresoc.v:185121.7-185121.19" + attribute \src "libresoc.v:186452.3-186460.6" + wire $1\q_int$next[0:0]$12145 + attribute \src "libresoc.v:186429.7-186429.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:185134.17-185134.96" - wire $and$libresoc.v:185134$12150_Y - attribute \src "libresoc.v:185139.17-185139.96" - wire $and$libresoc.v:185139$12155_Y - attribute \src "libresoc.v:185136.18-185136.94" - wire $not$libresoc.v:185136$12152_Y - attribute \src "libresoc.v:185138.17-185138.93" - wire $not$libresoc.v:185138$12154_Y - attribute \src "libresoc.v:185141.17-185141.93" - wire $not$libresoc.v:185141$12157_Y - attribute \src "libresoc.v:185135.18-185135.99" - wire $or$libresoc.v:185135$12151_Y - attribute \src "libresoc.v:185137.18-185137.100" - wire $or$libresoc.v:185137$12153_Y - attribute \src "libresoc.v:185140.17-185140.98" - wire $or$libresoc.v:185140$12156_Y + attribute \src "libresoc.v:186442.17-186442.96" + wire $and$libresoc.v:186442$12134_Y + attribute \src "libresoc.v:186447.17-186447.96" + wire $and$libresoc.v:186447$12139_Y + attribute \src "libresoc.v:186444.18-186444.94" + wire $not$libresoc.v:186444$12136_Y + attribute \src "libresoc.v:186446.17-186446.93" + wire $not$libresoc.v:186446$12138_Y + attribute \src "libresoc.v:186449.17-186449.93" + wire $not$libresoc.v:186449$12141_Y + attribute \src "libresoc.v:186443.18-186443.99" + wire $or$libresoc.v:186443$12135_Y + attribute \src "libresoc.v:186445.18-186445.100" + wire $or$libresoc.v:186445$12137_Y + attribute \src "libresoc.v:186448.17-186448.98" + wire $or$libresoc.v:186448$12140_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -379623,11 +350993,11 @@ module \rok_l$14 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:185099.7-185099.15" + attribute \src "libresoc.v:186407.7-186407.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -379644,7 +351014,7 @@ module \rok_l$14 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:185134$12150 + cell $and $and$libresoc.v:186442$12134 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379652,10 +351022,10 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:185134$12150_Y + connect \Y $and$libresoc.v:186442$12134_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:185139$12155 + cell $and $and$libresoc.v:186447$12139 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379663,34 +351033,34 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:185139$12155_Y + connect \Y $and$libresoc.v:186447$12139_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:185136$12152 + cell $not $not$libresoc.v:186444$12136 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:185136$12152_Y + connect \Y $not$libresoc.v:186444$12136_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:185138$12154 + cell $not $not$libresoc.v:186446$12138 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185138$12154_Y + connect \Y $not$libresoc.v:186446$12138_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:185141$12157 + cell $not $not$libresoc.v:186449$12141 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185141$12157_Y + connect \Y $not$libresoc.v:186449$12141_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:185135$12151 + cell $or $or$libresoc.v:186443$12135 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379698,10 +351068,10 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:185135$12151_Y + connect \Y $or$libresoc.v:186443$12135_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:185137$12153 + cell $or $or$libresoc.v:186445$12137 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379709,10 +351079,10 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:185137$12153_Y + connect \Y $or$libresoc.v:186445$12137_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:185140$12156 + cell $or $or$libresoc.v:186448$12140 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379720,39 +351090,39 @@ module \rok_l$14 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:185140$12156_Y + connect \Y $or$libresoc.v:186448$12140_Y end - attribute \src "libresoc.v:185099.7-185099.20" - process $proc$libresoc.v:185099$12162 + attribute \src "libresoc.v:186407.7-186407.20" + process $proc$libresoc.v:186407$12146 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185121.7-185121.19" - process $proc$libresoc.v:185121$12163 + attribute \src "libresoc.v:186429.7-186429.19" + process $proc$libresoc.v:186429$12147 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:185142.3-185143.27" - process $proc$libresoc.v:185142$12158 + attribute \src "libresoc.v:186450.3-186451.27" + process $proc$libresoc.v:186450$12142 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:185144.3-185152.6" - process $proc$libresoc.v:185144$12159 + attribute \src "libresoc.v:186452.3-186460.6" + process $proc$libresoc.v:186452$12143 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12160 $1\q_int$next[0:0]$12161 - attribute \src "libresoc.v:185145.5-185145.29" + assign $0\q_int$next[0:0]$12144 $1\q_int$next[0:0]$12145 + attribute \src "libresoc.v:186453.5-186453.29" switch \initial - attribute \src "libresoc.v:185145.9-185145.17" + attribute \src "libresoc.v:186453.9-186453.17" case 1'1 case end @@ -379761,56 +351131,56 @@ module \rok_l$14 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12161 1'0 + assign $1\q_int$next[0:0]$12145 1'0 case - assign $1\q_int$next[0:0]$12161 \$5 + assign $1\q_int$next[0:0]$12145 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12160 + update \q_int$next $0\q_int$next[0:0]$12144 end - connect \$9 $and$libresoc.v:185134$12150_Y - connect \$11 $or$libresoc.v:185135$12151_Y - connect \$13 $not$libresoc.v:185136$12152_Y - connect \$15 $or$libresoc.v:185137$12153_Y - connect \$1 $not$libresoc.v:185138$12154_Y - connect \$3 $and$libresoc.v:185139$12155_Y - connect \$5 $or$libresoc.v:185140$12156_Y - connect \$7 $not$libresoc.v:185141$12157_Y + connect \$9 $and$libresoc.v:186442$12134_Y + connect \$11 $or$libresoc.v:186443$12135_Y + connect \$13 $not$libresoc.v:186444$12136_Y + connect \$15 $or$libresoc.v:186445$12137_Y + connect \$1 $not$libresoc.v:186446$12138_Y + connect \$3 $and$libresoc.v:186447$12139_Y + connect \$5 $or$libresoc.v:186448$12140_Y + connect \$7 $not$libresoc.v:186449$12141_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:185160.1-185218.10" +attribute \src "libresoc.v:186468.1-186526.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.rok_l" attribute \generator "nMigen" module \rok_l$27 - attribute \src "libresoc.v:185161.7-185161.20" + attribute \src "libresoc.v:186469.7-186469.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185206.3-185214.6" - wire $0\q_int$next[0:0]$12174 - attribute \src "libresoc.v:185204.3-185205.27" + attribute \src "libresoc.v:186514.3-186522.6" + wire $0\q_int$next[0:0]$12158 + attribute \src "libresoc.v:186512.3-186513.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:185206.3-185214.6" - wire $1\q_int$next[0:0]$12175 - attribute \src "libresoc.v:185183.7-185183.19" + attribute \src "libresoc.v:186514.3-186522.6" + wire $1\q_int$next[0:0]$12159 + attribute \src "libresoc.v:186491.7-186491.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:185196.17-185196.96" - wire $and$libresoc.v:185196$12164_Y - attribute \src "libresoc.v:185201.17-185201.96" - wire $and$libresoc.v:185201$12169_Y - attribute \src "libresoc.v:185198.18-185198.94" - wire $not$libresoc.v:185198$12166_Y - attribute \src "libresoc.v:185200.17-185200.93" - wire $not$libresoc.v:185200$12168_Y - attribute \src "libresoc.v:185203.17-185203.93" - wire $not$libresoc.v:185203$12171_Y - attribute \src "libresoc.v:185197.18-185197.99" - wire $or$libresoc.v:185197$12165_Y - attribute \src "libresoc.v:185199.18-185199.100" - wire $or$libresoc.v:185199$12167_Y - attribute \src "libresoc.v:185202.17-185202.98" - wire $or$libresoc.v:185202$12170_Y + attribute \src "libresoc.v:186504.17-186504.96" + wire $and$libresoc.v:186504$12148_Y + attribute \src "libresoc.v:186509.17-186509.96" + wire $and$libresoc.v:186509$12153_Y + attribute \src "libresoc.v:186506.18-186506.94" + wire $not$libresoc.v:186506$12150_Y + attribute \src "libresoc.v:186508.17-186508.93" + wire $not$libresoc.v:186508$12152_Y + attribute \src "libresoc.v:186511.17-186511.93" + wire $not$libresoc.v:186511$12155_Y + attribute \src "libresoc.v:186505.18-186505.99" + wire $or$libresoc.v:186505$12149_Y + attribute \src "libresoc.v:186507.18-186507.100" + wire $or$libresoc.v:186507$12151_Y + attribute \src "libresoc.v:186510.17-186510.98" + wire $or$libresoc.v:186510$12154_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -379827,11 +351197,11 @@ module \rok_l$27 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:185161.7-185161.15" + attribute \src "libresoc.v:186469.7-186469.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -379848,7 +351218,7 @@ module \rok_l$27 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:185196$12164 + cell $and $and$libresoc.v:186504$12148 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379856,10 +351226,10 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:185196$12164_Y + connect \Y $and$libresoc.v:186504$12148_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:185201$12169 + cell $and $and$libresoc.v:186509$12153 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379867,34 +351237,34 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:185201$12169_Y + connect \Y $and$libresoc.v:186509$12153_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:185198$12166 + cell $not $not$libresoc.v:186506$12150 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:185198$12166_Y + connect \Y $not$libresoc.v:186506$12150_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:185200$12168 + cell $not $not$libresoc.v:186508$12152 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185200$12168_Y + connect \Y $not$libresoc.v:186508$12152_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:185203$12171 + cell $not $not$libresoc.v:186511$12155 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185203$12171_Y + connect \Y $not$libresoc.v:186511$12155_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:185197$12165 + cell $or $or$libresoc.v:186505$12149 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379902,10 +351272,10 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:185197$12165_Y + connect \Y $or$libresoc.v:186505$12149_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:185199$12167 + cell $or $or$libresoc.v:186507$12151 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379913,10 +351283,10 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:185199$12167_Y + connect \Y $or$libresoc.v:186507$12151_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:185202$12170 + cell $or $or$libresoc.v:186510$12154 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -379924,39 +351294,39 @@ module \rok_l$27 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:185202$12170_Y + connect \Y $or$libresoc.v:186510$12154_Y end - attribute \src "libresoc.v:185161.7-185161.20" - process $proc$libresoc.v:185161$12176 + attribute \src "libresoc.v:186469.7-186469.20" + process $proc$libresoc.v:186469$12160 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185183.7-185183.19" - process $proc$libresoc.v:185183$12177 + attribute \src "libresoc.v:186491.7-186491.19" + process $proc$libresoc.v:186491$12161 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:185204.3-185205.27" - process $proc$libresoc.v:185204$12172 + attribute \src "libresoc.v:186512.3-186513.27" + process $proc$libresoc.v:186512$12156 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:185206.3-185214.6" - process $proc$libresoc.v:185206$12173 + attribute \src "libresoc.v:186514.3-186522.6" + process $proc$libresoc.v:186514$12157 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12174 $1\q_int$next[0:0]$12175 - attribute \src "libresoc.v:185207.5-185207.29" + assign $0\q_int$next[0:0]$12158 $1\q_int$next[0:0]$12159 + attribute \src "libresoc.v:186515.5-186515.29" switch \initial - attribute \src "libresoc.v:185207.9-185207.17" + attribute \src "libresoc.v:186515.9-186515.17" case 1'1 case end @@ -379965,56 +351335,56 @@ module \rok_l$27 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12175 1'0 + assign $1\q_int$next[0:0]$12159 1'0 case - assign $1\q_int$next[0:0]$12175 \$5 + assign $1\q_int$next[0:0]$12159 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12174 + update \q_int$next $0\q_int$next[0:0]$12158 end - connect \$9 $and$libresoc.v:185196$12164_Y - connect \$11 $or$libresoc.v:185197$12165_Y - connect \$13 $not$libresoc.v:185198$12166_Y - connect \$15 $or$libresoc.v:185199$12167_Y - connect \$1 $not$libresoc.v:185200$12168_Y - connect \$3 $and$libresoc.v:185201$12169_Y - connect \$5 $or$libresoc.v:185202$12170_Y - connect \$7 $not$libresoc.v:185203$12171_Y + connect \$9 $and$libresoc.v:186504$12148_Y + connect \$11 $or$libresoc.v:186505$12149_Y + connect \$13 $not$libresoc.v:186506$12150_Y + connect \$15 $or$libresoc.v:186507$12151_Y + connect \$1 $not$libresoc.v:186508$12152_Y + connect \$3 $and$libresoc.v:186509$12153_Y + connect \$5 $or$libresoc.v:186510$12154_Y + connect \$7 $not$libresoc.v:186511$12155_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:185222.1-185280.10" +attribute \src "libresoc.v:186530.1-186588.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.rok_l" attribute \generator "nMigen" module \rok_l$43 - attribute \src "libresoc.v:185223.7-185223.20" + attribute \src "libresoc.v:186531.7-186531.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185268.3-185276.6" - wire $0\q_int$next[0:0]$12188 - attribute \src "libresoc.v:185266.3-185267.27" + attribute \src "libresoc.v:186576.3-186584.6" + wire $0\q_int$next[0:0]$12172 + attribute \src "libresoc.v:186574.3-186575.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:185268.3-185276.6" - wire $1\q_int$next[0:0]$12189 - attribute \src "libresoc.v:185245.7-185245.19" + attribute \src "libresoc.v:186576.3-186584.6" + wire $1\q_int$next[0:0]$12173 + attribute \src "libresoc.v:186553.7-186553.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:185258.17-185258.96" - wire $and$libresoc.v:185258$12178_Y - attribute \src "libresoc.v:185263.17-185263.96" - wire $and$libresoc.v:185263$12183_Y - attribute \src "libresoc.v:185260.18-185260.94" - wire $not$libresoc.v:185260$12180_Y - attribute \src "libresoc.v:185262.17-185262.93" - wire $not$libresoc.v:185262$12182_Y - attribute \src "libresoc.v:185265.17-185265.93" - wire $not$libresoc.v:185265$12185_Y - attribute \src "libresoc.v:185259.18-185259.99" - wire $or$libresoc.v:185259$12179_Y - attribute \src "libresoc.v:185261.18-185261.100" - wire $or$libresoc.v:185261$12181_Y - attribute \src "libresoc.v:185264.17-185264.98" - wire $or$libresoc.v:185264$12184_Y + attribute \src "libresoc.v:186566.17-186566.96" + wire $and$libresoc.v:186566$12162_Y + attribute \src "libresoc.v:186571.17-186571.96" + wire $and$libresoc.v:186571$12167_Y + attribute \src "libresoc.v:186568.18-186568.94" + wire $not$libresoc.v:186568$12164_Y + attribute \src "libresoc.v:186570.17-186570.93" + wire $not$libresoc.v:186570$12166_Y + attribute \src "libresoc.v:186573.17-186573.93" + wire $not$libresoc.v:186573$12169_Y + attribute \src "libresoc.v:186567.18-186567.99" + wire $or$libresoc.v:186567$12163_Y + attribute \src "libresoc.v:186569.18-186569.100" + wire $or$libresoc.v:186569$12165_Y + attribute \src "libresoc.v:186572.17-186572.98" + wire $or$libresoc.v:186572$12168_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -380031,11 +351401,11 @@ module \rok_l$43 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:185223.7-185223.15" + attribute \src "libresoc.v:186531.7-186531.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -380052,7 +351422,7 @@ module \rok_l$43 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:185258$12178 + cell $and $and$libresoc.v:186566$12162 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380060,10 +351430,10 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:185258$12178_Y + connect \Y $and$libresoc.v:186566$12162_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:185263$12183 + cell $and $and$libresoc.v:186571$12167 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380071,34 +351441,34 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:185263$12183_Y + connect \Y $and$libresoc.v:186571$12167_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:185260$12180 + cell $not $not$libresoc.v:186568$12164 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:185260$12180_Y + connect \Y $not$libresoc.v:186568$12164_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:185262$12182 + cell $not $not$libresoc.v:186570$12166 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185262$12182_Y + connect \Y $not$libresoc.v:186570$12166_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:185265$12185 + cell $not $not$libresoc.v:186573$12169 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185265$12185_Y + connect \Y $not$libresoc.v:186573$12169_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:185259$12179 + cell $or $or$libresoc.v:186567$12163 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380106,10 +351476,10 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:185259$12179_Y + connect \Y $or$libresoc.v:186567$12163_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:185261$12181 + cell $or $or$libresoc.v:186569$12165 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380117,10 +351487,10 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:185261$12181_Y + connect \Y $or$libresoc.v:186569$12165_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:185264$12184 + cell $or $or$libresoc.v:186572$12168 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380128,39 +351498,39 @@ module \rok_l$43 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:185264$12184_Y + connect \Y $or$libresoc.v:186572$12168_Y end - attribute \src "libresoc.v:185223.7-185223.20" - process $proc$libresoc.v:185223$12190 + attribute \src "libresoc.v:186531.7-186531.20" + process $proc$libresoc.v:186531$12174 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185245.7-185245.19" - process $proc$libresoc.v:185245$12191 + attribute \src "libresoc.v:186553.7-186553.19" + process $proc$libresoc.v:186553$12175 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:185266.3-185267.27" - process $proc$libresoc.v:185266$12186 + attribute \src "libresoc.v:186574.3-186575.27" + process $proc$libresoc.v:186574$12170 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:185268.3-185276.6" - process $proc$libresoc.v:185268$12187 + attribute \src "libresoc.v:186576.3-186584.6" + process $proc$libresoc.v:186576$12171 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12188 $1\q_int$next[0:0]$12189 - attribute \src "libresoc.v:185269.5-185269.29" + assign $0\q_int$next[0:0]$12172 $1\q_int$next[0:0]$12173 + attribute \src "libresoc.v:186577.5-186577.29" switch \initial - attribute \src "libresoc.v:185269.9-185269.17" + attribute \src "libresoc.v:186577.9-186577.17" case 1'1 case end @@ -380169,56 +351539,56 @@ module \rok_l$43 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12189 1'0 + assign $1\q_int$next[0:0]$12173 1'0 case - assign $1\q_int$next[0:0]$12189 \$5 + assign $1\q_int$next[0:0]$12173 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12188 + update \q_int$next $0\q_int$next[0:0]$12172 end - connect \$9 $and$libresoc.v:185258$12178_Y - connect \$11 $or$libresoc.v:185259$12179_Y - connect \$13 $not$libresoc.v:185260$12180_Y - connect \$15 $or$libresoc.v:185261$12181_Y - connect \$1 $not$libresoc.v:185262$12182_Y - connect \$3 $and$libresoc.v:185263$12183_Y - connect \$5 $or$libresoc.v:185264$12184_Y - connect \$7 $not$libresoc.v:185265$12185_Y + connect \$9 $and$libresoc.v:186566$12162_Y + connect \$11 $or$libresoc.v:186567$12163_Y + connect \$13 $not$libresoc.v:186568$12164_Y + connect \$15 $or$libresoc.v:186569$12165_Y + connect \$1 $not$libresoc.v:186570$12166_Y + connect \$3 $and$libresoc.v:186571$12167_Y + connect \$5 $or$libresoc.v:186572$12168_Y + connect \$7 $not$libresoc.v:186573$12169_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:185284.1-185342.10" +attribute \src "libresoc.v:186592.1-186650.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.rok_l" attribute \generator "nMigen" module \rok_l$59 - attribute \src "libresoc.v:185285.7-185285.20" + attribute \src "libresoc.v:186593.7-186593.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185330.3-185338.6" - wire $0\q_int$next[0:0]$12202 - attribute \src "libresoc.v:185328.3-185329.27" + attribute \src "libresoc.v:186638.3-186646.6" + wire $0\q_int$next[0:0]$12186 + attribute \src "libresoc.v:186636.3-186637.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:185330.3-185338.6" - wire $1\q_int$next[0:0]$12203 - attribute \src "libresoc.v:185307.7-185307.19" + attribute \src "libresoc.v:186638.3-186646.6" + wire $1\q_int$next[0:0]$12187 + attribute \src "libresoc.v:186615.7-186615.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:185320.17-185320.96" - wire $and$libresoc.v:185320$12192_Y - attribute \src "libresoc.v:185325.17-185325.96" - wire $and$libresoc.v:185325$12197_Y - attribute \src "libresoc.v:185322.18-185322.94" - wire $not$libresoc.v:185322$12194_Y - attribute \src "libresoc.v:185324.17-185324.93" - wire $not$libresoc.v:185324$12196_Y - attribute \src "libresoc.v:185327.17-185327.93" - wire $not$libresoc.v:185327$12199_Y - attribute \src "libresoc.v:185321.18-185321.99" - wire $or$libresoc.v:185321$12193_Y - attribute \src "libresoc.v:185323.18-185323.100" - wire $or$libresoc.v:185323$12195_Y - attribute \src "libresoc.v:185326.17-185326.98" - wire $or$libresoc.v:185326$12198_Y + attribute \src "libresoc.v:186628.17-186628.96" + wire $and$libresoc.v:186628$12176_Y + attribute \src "libresoc.v:186633.17-186633.96" + wire $and$libresoc.v:186633$12181_Y + attribute \src "libresoc.v:186630.18-186630.94" + wire $not$libresoc.v:186630$12178_Y + attribute \src "libresoc.v:186632.17-186632.93" + wire $not$libresoc.v:186632$12180_Y + attribute \src "libresoc.v:186635.17-186635.93" + wire $not$libresoc.v:186635$12183_Y + attribute \src "libresoc.v:186629.18-186629.99" + wire $or$libresoc.v:186629$12177_Y + attribute \src "libresoc.v:186631.18-186631.100" + wire $or$libresoc.v:186631$12179_Y + attribute \src "libresoc.v:186634.17-186634.98" + wire $or$libresoc.v:186634$12182_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -380235,11 +351605,11 @@ module \rok_l$59 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:185285.7-185285.15" + attribute \src "libresoc.v:186593.7-186593.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -380256,7 +351626,7 @@ module \rok_l$59 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:185320$12192 + cell $and $and$libresoc.v:186628$12176 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380264,10 +351634,10 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:185320$12192_Y + connect \Y $and$libresoc.v:186628$12176_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:185325$12197 + cell $and $and$libresoc.v:186633$12181 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380275,34 +351645,34 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:185325$12197_Y + connect \Y $and$libresoc.v:186633$12181_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:185322$12194 + cell $not $not$libresoc.v:186630$12178 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:185322$12194_Y + connect \Y $not$libresoc.v:186630$12178_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:185324$12196 + cell $not $not$libresoc.v:186632$12180 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185324$12196_Y + connect \Y $not$libresoc.v:186632$12180_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:185327$12199 + cell $not $not$libresoc.v:186635$12183 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185327$12199_Y + connect \Y $not$libresoc.v:186635$12183_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:185321$12193 + cell $or $or$libresoc.v:186629$12177 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380310,10 +351680,10 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:185321$12193_Y + connect \Y $or$libresoc.v:186629$12177_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:185323$12195 + cell $or $or$libresoc.v:186631$12179 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380321,10 +351691,10 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:185323$12195_Y + connect \Y $or$libresoc.v:186631$12179_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:185326$12198 + cell $or $or$libresoc.v:186634$12182 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380332,39 +351702,39 @@ module \rok_l$59 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:185326$12198_Y + connect \Y $or$libresoc.v:186634$12182_Y end - attribute \src "libresoc.v:185285.7-185285.20" - process $proc$libresoc.v:185285$12204 + attribute \src "libresoc.v:186593.7-186593.20" + process $proc$libresoc.v:186593$12188 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185307.7-185307.19" - process $proc$libresoc.v:185307$12205 + attribute \src "libresoc.v:186615.7-186615.19" + process $proc$libresoc.v:186615$12189 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:185328.3-185329.27" - process $proc$libresoc.v:185328$12200 + attribute \src "libresoc.v:186636.3-186637.27" + process $proc$libresoc.v:186636$12184 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:185330.3-185338.6" - process $proc$libresoc.v:185330$12201 + attribute \src "libresoc.v:186638.3-186646.6" + process $proc$libresoc.v:186638$12185 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12202 $1\q_int$next[0:0]$12203 - attribute \src "libresoc.v:185331.5-185331.29" + assign $0\q_int$next[0:0]$12186 $1\q_int$next[0:0]$12187 + attribute \src "libresoc.v:186639.5-186639.29" switch \initial - attribute \src "libresoc.v:185331.9-185331.17" + attribute \src "libresoc.v:186639.9-186639.17" case 1'1 case end @@ -380373,56 +351743,56 @@ module \rok_l$59 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12203 1'0 + assign $1\q_int$next[0:0]$12187 1'0 case - assign $1\q_int$next[0:0]$12203 \$5 + assign $1\q_int$next[0:0]$12187 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12202 + update \q_int$next $0\q_int$next[0:0]$12186 end - connect \$9 $and$libresoc.v:185320$12192_Y - connect \$11 $or$libresoc.v:185321$12193_Y - connect \$13 $not$libresoc.v:185322$12194_Y - connect \$15 $or$libresoc.v:185323$12195_Y - connect \$1 $not$libresoc.v:185324$12196_Y - connect \$3 $and$libresoc.v:185325$12197_Y - connect \$5 $or$libresoc.v:185326$12198_Y - connect \$7 $not$libresoc.v:185327$12199_Y + connect \$9 $and$libresoc.v:186628$12176_Y + connect \$11 $or$libresoc.v:186629$12177_Y + connect \$13 $not$libresoc.v:186630$12178_Y + connect \$15 $or$libresoc.v:186631$12179_Y + connect \$1 $not$libresoc.v:186632$12180_Y + connect \$3 $and$libresoc.v:186633$12181_Y + connect \$5 $or$libresoc.v:186634$12182_Y + connect \$7 $not$libresoc.v:186635$12183_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:185346.1-185404.10" +attribute \src "libresoc.v:186654.1-186712.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.rok_l" attribute \generator "nMigen" module \rok_l$71 - attribute \src "libresoc.v:185347.7-185347.20" + attribute \src "libresoc.v:186655.7-186655.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185392.3-185400.6" - wire $0\q_int$next[0:0]$12216 - attribute \src "libresoc.v:185390.3-185391.27" + attribute \src "libresoc.v:186700.3-186708.6" + wire $0\q_int$next[0:0]$12200 + attribute \src "libresoc.v:186698.3-186699.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:185392.3-185400.6" - wire $1\q_int$next[0:0]$12217 - attribute \src "libresoc.v:185369.7-185369.19" + attribute \src "libresoc.v:186700.3-186708.6" + wire $1\q_int$next[0:0]$12201 + attribute \src "libresoc.v:186677.7-186677.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:185382.17-185382.96" - wire $and$libresoc.v:185382$12206_Y - attribute \src "libresoc.v:185387.17-185387.96" - wire $and$libresoc.v:185387$12211_Y - attribute \src "libresoc.v:185384.18-185384.94" - wire $not$libresoc.v:185384$12208_Y - attribute \src "libresoc.v:185386.17-185386.93" - wire $not$libresoc.v:185386$12210_Y - attribute \src "libresoc.v:185389.17-185389.93" - wire $not$libresoc.v:185389$12213_Y - attribute \src "libresoc.v:185383.18-185383.99" - wire $or$libresoc.v:185383$12207_Y - attribute \src "libresoc.v:185385.18-185385.100" - wire $or$libresoc.v:185385$12209_Y - attribute \src "libresoc.v:185388.17-185388.98" - wire $or$libresoc.v:185388$12212_Y + attribute \src "libresoc.v:186690.17-186690.96" + wire $and$libresoc.v:186690$12190_Y + attribute \src "libresoc.v:186695.17-186695.96" + wire $and$libresoc.v:186695$12195_Y + attribute \src "libresoc.v:186692.18-186692.94" + wire $not$libresoc.v:186692$12192_Y + attribute \src "libresoc.v:186694.17-186694.93" + wire $not$libresoc.v:186694$12194_Y + attribute \src "libresoc.v:186697.17-186697.93" + wire $not$libresoc.v:186697$12197_Y + attribute \src "libresoc.v:186691.18-186691.99" + wire $or$libresoc.v:186691$12191_Y + attribute \src "libresoc.v:186693.18-186693.100" + wire $or$libresoc.v:186693$12193_Y + attribute \src "libresoc.v:186696.17-186696.98" + wire $or$libresoc.v:186696$12196_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -380439,11 +351809,11 @@ module \rok_l$71 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:185347.7-185347.15" + attribute \src "libresoc.v:186655.7-186655.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -380460,7 +351830,7 @@ module \rok_l$71 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:185382$12206 + cell $and $and$libresoc.v:186690$12190 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380468,10 +351838,10 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:185382$12206_Y + connect \Y $and$libresoc.v:186690$12190_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:185387$12211 + cell $and $and$libresoc.v:186695$12195 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380479,34 +351849,34 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:185387$12211_Y + connect \Y $and$libresoc.v:186695$12195_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:185384$12208 + cell $not $not$libresoc.v:186692$12192 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:185384$12208_Y + connect \Y $not$libresoc.v:186692$12192_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:185386$12210 + cell $not $not$libresoc.v:186694$12194 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185386$12210_Y + connect \Y $not$libresoc.v:186694$12194_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:185389$12213 + cell $not $not$libresoc.v:186697$12197 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185389$12213_Y + connect \Y $not$libresoc.v:186697$12197_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:185383$12207 + cell $or $or$libresoc.v:186691$12191 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380514,10 +351884,10 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:185383$12207_Y + connect \Y $or$libresoc.v:186691$12191_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:185385$12209 + cell $or $or$libresoc.v:186693$12193 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380525,10 +351895,10 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:185385$12209_Y + connect \Y $or$libresoc.v:186693$12193_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:185388$12212 + cell $or $or$libresoc.v:186696$12196 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380536,39 +351906,39 @@ module \rok_l$71 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:185388$12212_Y + connect \Y $or$libresoc.v:186696$12196_Y end - attribute \src "libresoc.v:185347.7-185347.20" - process $proc$libresoc.v:185347$12218 + attribute \src "libresoc.v:186655.7-186655.20" + process $proc$libresoc.v:186655$12202 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185369.7-185369.19" - process $proc$libresoc.v:185369$12219 + attribute \src "libresoc.v:186677.7-186677.19" + process $proc$libresoc.v:186677$12203 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:185390.3-185391.27" - process $proc$libresoc.v:185390$12214 + attribute \src "libresoc.v:186698.3-186699.27" + process $proc$libresoc.v:186698$12198 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:185392.3-185400.6" - process $proc$libresoc.v:185392$12215 + attribute \src "libresoc.v:186700.3-186708.6" + process $proc$libresoc.v:186700$12199 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12216 $1\q_int$next[0:0]$12217 - attribute \src "libresoc.v:185393.5-185393.29" + assign $0\q_int$next[0:0]$12200 $1\q_int$next[0:0]$12201 + attribute \src "libresoc.v:186701.5-186701.29" switch \initial - attribute \src "libresoc.v:185393.9-185393.17" + attribute \src "libresoc.v:186701.9-186701.17" case 1'1 case end @@ -380577,56 +351947,56 @@ module \rok_l$71 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12217 1'0 + assign $1\q_int$next[0:0]$12201 1'0 case - assign $1\q_int$next[0:0]$12217 \$5 + assign $1\q_int$next[0:0]$12201 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12216 + update \q_int$next $0\q_int$next[0:0]$12200 end - connect \$9 $and$libresoc.v:185382$12206_Y - connect \$11 $or$libresoc.v:185383$12207_Y - connect \$13 $not$libresoc.v:185384$12208_Y - connect \$15 $or$libresoc.v:185385$12209_Y - connect \$1 $not$libresoc.v:185386$12210_Y - connect \$3 $and$libresoc.v:185387$12211_Y - connect \$5 $or$libresoc.v:185388$12212_Y - connect \$7 $not$libresoc.v:185389$12213_Y + connect \$9 $and$libresoc.v:186690$12190_Y + connect \$11 $or$libresoc.v:186691$12191_Y + connect \$13 $not$libresoc.v:186692$12192_Y + connect \$15 $or$libresoc.v:186693$12193_Y + connect \$1 $not$libresoc.v:186694$12194_Y + connect \$3 $and$libresoc.v:186695$12195_Y + connect \$5 $or$libresoc.v:186696$12196_Y + connect \$7 $not$libresoc.v:186697$12197_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:185408.1-185466.10" +attribute \src "libresoc.v:186716.1-186774.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.rok_l" attribute \generator "nMigen" module \rok_l$88 - attribute \src "libresoc.v:185409.7-185409.20" + attribute \src "libresoc.v:186717.7-186717.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185454.3-185462.6" - wire $0\q_int$next[0:0]$12230 - attribute \src "libresoc.v:185452.3-185453.27" + attribute \src "libresoc.v:186762.3-186770.6" + wire $0\q_int$next[0:0]$12214 + attribute \src "libresoc.v:186760.3-186761.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:185454.3-185462.6" - wire $1\q_int$next[0:0]$12231 - attribute \src "libresoc.v:185431.7-185431.19" + attribute \src "libresoc.v:186762.3-186770.6" + wire $1\q_int$next[0:0]$12215 + attribute \src "libresoc.v:186739.7-186739.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:185444.17-185444.96" - wire $and$libresoc.v:185444$12220_Y - attribute \src "libresoc.v:185449.17-185449.96" - wire $and$libresoc.v:185449$12225_Y - attribute \src "libresoc.v:185446.18-185446.94" - wire $not$libresoc.v:185446$12222_Y - attribute \src "libresoc.v:185448.17-185448.93" - wire $not$libresoc.v:185448$12224_Y - attribute \src "libresoc.v:185451.17-185451.93" - wire $not$libresoc.v:185451$12227_Y - attribute \src "libresoc.v:185445.18-185445.99" - wire $or$libresoc.v:185445$12221_Y - attribute \src "libresoc.v:185447.18-185447.100" - wire $or$libresoc.v:185447$12223_Y - attribute \src "libresoc.v:185450.17-185450.98" - wire $or$libresoc.v:185450$12226_Y + attribute \src "libresoc.v:186752.17-186752.96" + wire $and$libresoc.v:186752$12204_Y + attribute \src "libresoc.v:186757.17-186757.96" + wire $and$libresoc.v:186757$12209_Y + attribute \src "libresoc.v:186754.18-186754.94" + wire $not$libresoc.v:186754$12206_Y + attribute \src "libresoc.v:186756.17-186756.93" + wire $not$libresoc.v:186756$12208_Y + attribute \src "libresoc.v:186759.17-186759.93" + wire $not$libresoc.v:186759$12211_Y + attribute \src "libresoc.v:186753.18-186753.99" + wire $or$libresoc.v:186753$12205_Y + attribute \src "libresoc.v:186755.18-186755.100" + wire $or$libresoc.v:186755$12207_Y + attribute \src "libresoc.v:186758.17-186758.98" + wire $or$libresoc.v:186758$12210_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -380643,11 +352013,11 @@ module \rok_l$88 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:185409.7-185409.15" + attribute \src "libresoc.v:186717.7-186717.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -380664,7 +352034,7 @@ module \rok_l$88 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_rdok attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:185444$12220 + cell $and $and$libresoc.v:186752$12204 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380672,10 +352042,10 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:185444$12220_Y + connect \Y $and$libresoc.v:186752$12204_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:185449$12225 + cell $and $and$libresoc.v:186757$12209 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380683,34 +352053,34 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:185449$12225_Y + connect \Y $and$libresoc.v:186757$12209_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:185446$12222 + cell $not $not$libresoc.v:186754$12206 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rdok - connect \Y $not$libresoc.v:185446$12222_Y + connect \Y $not$libresoc.v:186754$12206_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:185448$12224 + cell $not $not$libresoc.v:186756$12208 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185448$12224_Y + connect \Y $not$libresoc.v:186756$12208_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:185451$12227 + cell $not $not$libresoc.v:186759$12211 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rdok - connect \Y $not$libresoc.v:185451$12227_Y + connect \Y $not$libresoc.v:186759$12211_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:185445$12221 + cell $or $or$libresoc.v:186753$12205 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380718,10 +352088,10 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rdok - connect \Y $or$libresoc.v:185445$12221_Y + connect \Y $or$libresoc.v:186753$12205_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:185447$12223 + cell $or $or$libresoc.v:186755$12207 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380729,10 +352099,10 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \q_rdok connect \B \q_int - connect \Y $or$libresoc.v:185447$12223_Y + connect \Y $or$libresoc.v:186755$12207_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:185450$12226 + cell $or $or$libresoc.v:186758$12210 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -380740,39 +352110,39 @@ module \rok_l$88 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rdok - connect \Y $or$libresoc.v:185450$12226_Y + connect \Y $or$libresoc.v:186758$12210_Y end - attribute \src "libresoc.v:185409.7-185409.20" - process $proc$libresoc.v:185409$12232 + attribute \src "libresoc.v:186717.7-186717.20" + process $proc$libresoc.v:186717$12216 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185431.7-185431.19" - process $proc$libresoc.v:185431$12233 + attribute \src "libresoc.v:186739.7-186739.19" + process $proc$libresoc.v:186739$12217 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:185452.3-185453.27" - process $proc$libresoc.v:185452$12228 + attribute \src "libresoc.v:186760.3-186761.27" + process $proc$libresoc.v:186760$12212 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:185454.3-185462.6" - process $proc$libresoc.v:185454$12229 + attribute \src "libresoc.v:186762.3-186770.6" + process $proc$libresoc.v:186762$12213 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12230 $1\q_int$next[0:0]$12231 - attribute \src "libresoc.v:185455.5-185455.29" + assign $0\q_int$next[0:0]$12214 $1\q_int$next[0:0]$12215 + attribute \src "libresoc.v:186763.5-186763.29" switch \initial - attribute \src "libresoc.v:185455.9-185455.17" + attribute \src "libresoc.v:186763.9-186763.17" case 1'1 case end @@ -380781,150 +352151,150 @@ module \rok_l$88 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12231 1'0 + assign $1\q_int$next[0:0]$12215 1'0 case - assign $1\q_int$next[0:0]$12231 \$5 + assign $1\q_int$next[0:0]$12215 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12230 + update \q_int$next $0\q_int$next[0:0]$12214 end - connect \$9 $and$libresoc.v:185444$12220_Y - connect \$11 $or$libresoc.v:185445$12221_Y - connect \$13 $not$libresoc.v:185446$12222_Y - connect \$15 $or$libresoc.v:185447$12223_Y - connect \$1 $not$libresoc.v:185448$12224_Y - connect \$3 $and$libresoc.v:185449$12225_Y - connect \$5 $or$libresoc.v:185450$12226_Y - connect \$7 $not$libresoc.v:185451$12227_Y + connect \$9 $and$libresoc.v:186752$12204_Y + connect \$11 $or$libresoc.v:186753$12205_Y + connect \$13 $not$libresoc.v:186754$12206_Y + connect \$15 $or$libresoc.v:186755$12207_Y + connect \$1 $not$libresoc.v:186756$12208_Y + connect \$3 $and$libresoc.v:186757$12209_Y + connect \$5 $or$libresoc.v:186758$12210_Y + connect \$7 $not$libresoc.v:186759$12211_Y connect \qlq_rdok \$15 connect \qn_rdok \$13 connect \q_rdok \$11 end -attribute \src "libresoc.v:185470.1-185821.10" +attribute \src "libresoc.v:186778.1-187138.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator" attribute \generator "nMigen" module \rotator - attribute \src "libresoc.v:185739.3-185748.6" + attribute \src "libresoc.v:187047.3-187065.6" wire $0\carry_out_o[0:0] - attribute \src "libresoc.v:185671.3-185685.6" + attribute \src "libresoc.v:186979.3-186993.6" wire width 32 $0\hi32[31:0] - attribute \src "libresoc.v:185471.7-185471.20" + attribute \src "libresoc.v:186779.7-186779.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185761.3-185794.6" - wire width 7 $0\mb$8[6:0]$12281 - attribute \src "libresoc.v:185795.3-185809.6" - wire width 7 $0\me$13[6:0]$12286 - attribute \src "libresoc.v:185696.3-185707.6" + attribute \src "libresoc.v:187078.3-187111.6" + wire width 7 $0\mb$8[6:0]$12265 + attribute \src "libresoc.v:187112.3-187126.6" + wire width 7 $0\me$13[6:0]$12270 + attribute \src "libresoc.v:187004.3-187015.6" wire width 64 $0\mr[63:0] - attribute \src "libresoc.v:185708.3-185719.6" + attribute \src "libresoc.v:187016.3-187027.6" wire width 2 $0\output_mode[1:0] - attribute \src "libresoc.v:185720.3-185738.6" + attribute \src "libresoc.v:187028.3-187046.6" wire width 64 $0\result_o[63:0] - attribute \src "libresoc.v:185686.3-185695.6" + attribute \src "libresoc.v:186994.3-187003.6" wire width 7 $0\right_mask_shift[6:0] - attribute \src "libresoc.v:185749.3-185760.6" + attribute \src "libresoc.v:187066.3-187077.6" wire width 6 $0\rot_count[5:0] - attribute \src "libresoc.v:185739.3-185748.6" + attribute \src "libresoc.v:187047.3-187065.6" wire $1\carry_out_o[0:0] - attribute \src "libresoc.v:185671.3-185685.6" + attribute \src "libresoc.v:186979.3-186993.6" wire width 32 $1\hi32[31:0] - attribute \src "libresoc.v:185761.3-185794.6" - wire width 7 $1\mb$8[6:0]$12282 - attribute \src "libresoc.v:185795.3-185809.6" - wire width 7 $1\me$13[6:0]$12287 - attribute \src "libresoc.v:185696.3-185707.6" + attribute \src "libresoc.v:187078.3-187111.6" + wire width 7 $1\mb$8[6:0]$12266 + attribute \src "libresoc.v:187112.3-187126.6" + wire width 7 $1\me$13[6:0]$12271 + attribute \src "libresoc.v:187004.3-187015.6" wire width 64 $1\mr[63:0] - attribute \src "libresoc.v:185708.3-185719.6" + attribute \src "libresoc.v:187016.3-187027.6" wire width 2 $1\output_mode[1:0] - attribute \src "libresoc.v:185720.3-185738.6" + attribute \src "libresoc.v:187028.3-187046.6" wire width 64 $1\result_o[63:0] - attribute \src "libresoc.v:185686.3-185695.6" + attribute \src "libresoc.v:186994.3-187003.6" wire width 7 $1\right_mask_shift[6:0] - attribute \src "libresoc.v:185749.3-185760.6" + attribute \src "libresoc.v:187066.3-187077.6" wire width 6 $1\rot_count[5:0] - attribute \src "libresoc.v:185761.3-185794.6" - wire width 2 $2\mb$8[6:5]$12283 - attribute \src "libresoc.v:185761.3-185794.6" - wire width 2 $3\mb$8[6:5]$12284 - attribute \src "libresoc.v:185622.18-185622.118" - wire $and$libresoc.v:185622$12237_Y - attribute \src "libresoc.v:185624.18-185624.114" - wire $and$libresoc.v:185624$12239_Y - attribute \src "libresoc.v:185633.18-185633.113" - wire $and$libresoc.v:185633$12248_Y - attribute \src "libresoc.v:185635.18-185635.114" - wire $and$libresoc.v:185635$12250_Y - attribute \src "libresoc.v:185637.18-185637.114" - wire $and$libresoc.v:185637$12252_Y - attribute \src "libresoc.v:185638.18-185638.103" - wire width 64 $and$libresoc.v:185638$12253_Y - attribute \src "libresoc.v:185639.18-185639.106" - wire width 64 $and$libresoc.v:185639$12254_Y - attribute \src "libresoc.v:185641.18-185641.103" - wire width 64 $and$libresoc.v:185641$12256_Y - attribute \src "libresoc.v:185643.18-185643.105" - wire width 64 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$not$libresoc.v:186931$12222_Y + attribute \src "libresoc.v:186933.18-186933.105" + wire width 6 $not$libresoc.v:186933$12224_Y + attribute \src "libresoc.v:186939.18-186939.112" + wire width 64 $not$libresoc.v:186939$12230_Y + attribute \src "libresoc.v:186940.18-186940.109" + wire $not$libresoc.v:186940$12231_Y + attribute \src "libresoc.v:186948.17-186948.105" + wire $not$libresoc.v:186948$12239_Y + attribute \src "libresoc.v:186950.18-186950.102" + wire width 64 $not$libresoc.v:186950$12241_Y + attribute \src "libresoc.v:186956.18-186956.102" + wire width 64 $not$libresoc.v:186956$12247_Y + attribute \src "libresoc.v:186961.18-186961.100" + wire width 64 $not$libresoc.v:186961$12252_Y + attribute \src "libresoc.v:186963.18-186963.100" + wire width 64 $not$libresoc.v:186963$12254_Y + attribute \src "libresoc.v:186942.18-186942.115" + wire $or$libresoc.v:186942$12233_Y + attribute \src "libresoc.v:186952.18-186952.108" + wire width 64 $or$libresoc.v:186952$12243_Y + attribute \src "libresoc.v:186953.18-186953.103" + wire width 64 $or$libresoc.v:186953$12244_Y + attribute \src "libresoc.v:186955.18-186955.103" + wire width 64 $or$libresoc.v:186955$12246_Y + attribute \src "libresoc.v:186958.18-186958.108" + wire width 64 $or$libresoc.v:186958$12249_Y + attribute \src "libresoc.v:186962.18-186962.106" + wire width 64 $or$libresoc.v:186962$12253_Y + attribute \src "libresoc.v:186928.17-186928.98" + wire width 7 $pos$libresoc.v:186928$12219_Y + attribute \src "libresoc.v:186965.18-186965.102" + wire $reduce_or$libresoc.v:186965$12256_Y + attribute \src "libresoc.v:186935.18-186935.109" + wire width 8 $sub$libresoc.v:186935$12226_Y + attribute \src "libresoc.v:186938.18-186938.110" + wire width 8 $sub$libresoc.v:186938$12229_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99" wire width 7 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126" @@ -381017,7 +352387,7 @@ module \rotator wire input 10 \clear_right attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:81" wire width 32 \hi32 - attribute \src "libresoc.v:185471.7-185471.15" + attribute \src "libresoc.v:186779.7-186779.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:57" wire input 6 \is_32bit @@ -381074,7 +352444,7 @@ module \rotator attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:62" wire input 11 \sign_ext_rs attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" - cell $and $and$libresoc.v:185622$12237 + cell $and $and$libresoc.v:186930$12221 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381082,10 +352452,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \clear_right connect \B \is_32bit - connect \Y $and$libresoc.v:185622$12237_Y + connect \Y $and$libresoc.v:186930$12221_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" - cell $and $and$libresoc.v:185624$12239 + cell $and $and$libresoc.v:186932$12223 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381093,10 +352463,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \clear_right connect \B \$16 - connect \Y $and$libresoc.v:185624$12239_Y + connect \Y $and$libresoc.v:186932$12223_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - cell $and $and$libresoc.v:185633$12248 + cell $and $and$libresoc.v:186941$12232 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381104,10 +352474,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \clear_left connect \B \$34 - connect \Y $and$libresoc.v:185633$12248_Y + connect \Y $and$libresoc.v:186941$12232_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:162" - cell $and $and$libresoc.v:185635$12250 + cell $and $and$libresoc.v:186943$12234 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381115,10 +352485,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \arith connect \B \repl32 [63] - connect \Y $and$libresoc.v:185635$12250_Y + connect \Y $and$libresoc.v:186943$12234_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" - cell $and $and$libresoc.v:185637$12252 + cell $and $and$libresoc.v:186945$12236 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381126,10 +352496,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \clear_right connect \B \$42 - connect \Y $and$libresoc.v:185637$12252_Y + connect \Y $and$libresoc.v:186945$12236_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$libresoc.v:185638$12253 + cell $and $and$libresoc.v:186946$12237 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -381137,10 +352507,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \mr connect \B \ml - connect \Y $and$libresoc.v:185638$12253_Y + connect \Y $and$libresoc.v:186946$12237_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$libresoc.v:185639$12254 + cell $and $and$libresoc.v:186947$12238 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -381148,10 +352518,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rot connect \B \$46 - connect \Y $and$libresoc.v:185639$12254_Y + connect \Y $and$libresoc.v:186947$12238_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$libresoc.v:185641$12256 + cell $and $and$libresoc.v:186949$12240 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -381159,10 +352529,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \mr connect \B \ml - connect \Y $and$libresoc.v:185641$12256_Y + connect \Y $and$libresoc.v:186949$12240_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $and $and$libresoc.v:185643$12258 + cell $and $and$libresoc.v:186951$12242 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -381170,10 +352540,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \ra connect \B \$50 - connect \Y $and$libresoc.v:185643$12258_Y + connect \Y $and$libresoc.v:186951$12242_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $and $and$libresoc.v:185646$12261 + cell $and $and$libresoc.v:186954$12245 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -381181,10 +352551,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rot connect \B \$58 - connect \Y $and$libresoc.v:185646$12261_Y + connect \Y $and$libresoc.v:186954$12245_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $and $and$libresoc.v:185649$12264 + cell $and $and$libresoc.v:186957$12248 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -381192,10 +352562,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \ra connect \B \$62 - connect \Y $and$libresoc.v:185649$12264_Y + connect \Y $and$libresoc.v:186957$12248_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" - cell $and $and$libresoc.v:185651$12266 + cell $and $and$libresoc.v:186959$12250 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381203,10 +352573,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \shift [6] connect \B \$4 - connect \Y $and$libresoc.v:185651$12266_Y + connect \Y $and$libresoc.v:186959$12250_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:174" - cell $and $and$libresoc.v:185652$12267 + cell $and $and$libresoc.v:186960$12251 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -381214,10 +352584,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rot connect \B \mr - connect \Y $and$libresoc.v:185652$12267_Y + connect \Y $and$libresoc.v:186960$12251_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" - cell $and $and$libresoc.v:185656$12271 + cell $and $and$libresoc.v:186964$12255 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -381225,18 +352595,18 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rs connect \B \$77 - connect \Y $and$libresoc.v:185656$12271_Y + connect \Y $and$libresoc.v:186964$12255_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" - cell $pos $extend$libresoc.v:185620$12234 + cell $pos $extend$libresoc.v:186928$12218 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 7 connect \A \mb - connect \Y $extend$libresoc.v:185620$12234_Y + connect \Y $extend$libresoc.v:186928$12218_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" - cell $gt $gt$libresoc.v:185636$12251 + cell $gt $gt$libresoc.v:186944$12235 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -381244,10 +352614,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \mb$8 [5:0] connect \B \me$13 [5:0] - connect \Y $gt$libresoc.v:185636$12251_Y + connect \Y $gt$libresoc.v:186944$12235_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" - cell $le $le$libresoc.v:185626$12241 + cell $le $le$libresoc.v:186934$12225 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381255,10 +352625,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \mb$8 connect \B 7'1000000 - connect \Y $le$libresoc.v:185626$12241_Y + connect \Y $le$libresoc.v:186934$12225_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" - cell $le $le$libresoc.v:185628$12243 + cell $le $le$libresoc.v:186936$12227 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381266,98 +352636,98 @@ module \rotator parameter \Y_WIDTH 1 connect \A \mb$8 connect \B 7'1000000 - connect \Y $le$libresoc.v:185628$12243_Y + connect \Y $le$libresoc.v:186936$12227_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99" - cell $neg $neg$libresoc.v:185629$12244 + cell $neg $neg$libresoc.v:186937$12228 parameter \A_SIGNED 1 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 connect \A { \shift_signed [5] \shift_signed } - connect \Y $neg$libresoc.v:185629$12244_Y + connect \Y $neg$libresoc.v:186937$12228_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126" - cell $not $not$libresoc.v:185621$12236 + cell $not $not$libresoc.v:186929$12220 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \sh [5] - connect \Y $not$libresoc.v:185621$12236_Y + connect \Y $not$libresoc.v:186929$12220_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" - cell $not $not$libresoc.v:185623$12238 + cell $not $not$libresoc.v:186931$12222 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \clear_left - connect \Y $not$libresoc.v:185623$12238_Y + connect \Y $not$libresoc.v:186931$12222_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:139" - cell $not $not$libresoc.v:185625$12240 + cell $not $not$libresoc.v:186933$12224 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \sh [5:0] - connect \Y $not$libresoc.v:185625$12240_Y + connect \Y $not$libresoc.v:186933$12224_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:152" - cell $not $not$libresoc.v:185631$12246 + cell $not $not$libresoc.v:186939$12230 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \left_mask_mask - connect \Y $not$libresoc.v:185631$12246_Y + connect \Y $not$libresoc.v:186939$12230_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - cell $not $not$libresoc.v:185632$12247 + cell $not $not$libresoc.v:186940$12231 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \clear_right - connect \Y $not$libresoc.v:185632$12247_Y + connect \Y $not$libresoc.v:186940$12231_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" - cell $not $not$libresoc.v:185640$12255 + cell $not $not$libresoc.v:186948$12239 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \is_32bit - connect \Y $not$libresoc.v:185640$12255_Y + connect \Y $not$libresoc.v:186948$12239_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $not $not$libresoc.v:185642$12257 + cell $not $not$libresoc.v:186950$12241 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \$51 - connect \Y $not$libresoc.v:185642$12257_Y + connect \Y $not$libresoc.v:186950$12241_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $not $not$libresoc.v:185648$12263 + cell $not $not$libresoc.v:186956$12247 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \$63 - connect \Y $not$libresoc.v:185648$12263_Y + connect \Y $not$libresoc.v:186956$12247_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" - cell $not $not$libresoc.v:185653$12268 + cell $not $not$libresoc.v:186961$12252 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \mr - connect \Y $not$libresoc.v:185653$12268_Y + connect \Y $not$libresoc.v:186961$12252_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" - cell $not $not$libresoc.v:185655$12270 + cell $not $not$libresoc.v:186963$12254 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A \ml - connect \Y $not$libresoc.v:185655$12270_Y + connect \Y $not$libresoc.v:186963$12254_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - cell $or $or$libresoc.v:185634$12249 + cell $or $or$libresoc.v:186942$12233 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381365,10 +352735,10 @@ module \rotator parameter \Y_WIDTH 1 connect \A \$36 connect \B \right_shift - connect \Y $or$libresoc.v:185634$12249_Y + connect \Y $or$libresoc.v:186942$12233_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" - cell $or $or$libresoc.v:185644$12259 + cell $or $or$libresoc.v:186952$12243 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -381376,10 +352746,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \$48 connect \B \$54 - connect \Y $or$libresoc.v:185644$12259_Y + connect \Y $or$libresoc.v:186952$12243_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $or $or$libresoc.v:185645$12260 + cell $or $or$libresoc.v:186953$12244 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -381387,10 +352757,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \mr connect \B \ml - connect \Y $or$libresoc.v:185645$12260_Y + connect \Y $or$libresoc.v:186953$12244_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $or $or$libresoc.v:185647$12262 + cell $or $or$libresoc.v:186955$12246 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -381398,10 +352768,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \mr connect \B \ml - connect \Y $or$libresoc.v:185647$12262_Y + connect \Y $or$libresoc.v:186955$12246_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" - cell $or $or$libresoc.v:185650$12265 + cell $or $or$libresoc.v:186958$12249 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -381409,10 +352779,10 @@ module \rotator parameter \Y_WIDTH 64 connect \A \$60 connect \B \$66 - connect \Y $or$libresoc.v:185650$12265_Y + connect \Y $or$libresoc.v:186958$12249_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" - cell $or $or$libresoc.v:185654$12269 + cell $or $or$libresoc.v:186962$12253 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -381420,26 +352790,26 @@ module \rotator parameter \Y_WIDTH 64 connect \A \rot connect \B \$72 - connect \Y $or$libresoc.v:185654$12269_Y + connect \Y $or$libresoc.v:186962$12253_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" - cell $pos $pos$libresoc.v:185620$12235 + cell $pos $pos$libresoc.v:186928$12219 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 7 - connect \A $extend$libresoc.v:185620$12234_Y - connect \Y $pos$libresoc.v:185620$12235_Y + connect \A $extend$libresoc.v:186928$12218_Y + connect \Y $pos$libresoc.v:186928$12219_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" - cell $reduce_or $reduce_or$libresoc.v:185657$12272 + cell $reduce_or $reduce_or$libresoc.v:186965$12256 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 1 connect \A \$79 - connect \Y $reduce_or$libresoc.v:185657$12272_Y + connect \Y $reduce_or$libresoc.v:186965$12256_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144" - cell $sub $sub$libresoc.v:185627$12242 + cell $sub $sub$libresoc.v:186935$12226 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381447,10 +352817,10 @@ module \rotator parameter \Y_WIDTH 8 connect \A 7'1000000 connect \B \mb$8 - connect \Y $sub$libresoc.v:185627$12242_Y + connect \Y $sub$libresoc.v:186935$12226_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151" - cell $sub $sub$libresoc.v:185630$12245 + cell $sub $sub$libresoc.v:186938$12229 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -381458,42 +352828,42 @@ module \rotator parameter \Y_WIDTH 8 connect \A 6'111111 connect \B \me$13 - connect \Y $sub$libresoc.v:185630$12245_Y + connect \Y $sub$libresoc.v:186938$12229_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:185658.13-185661.4" + attribute \src "libresoc.v:186966.13-186969.4" cell \left_mask \left_mask connect \mask \left_mask_mask connect \shift \left_mask_shift end attribute \module_not_derived 1 - attribute \src "libresoc.v:185662.14-185665.4" + attribute \src "libresoc.v:186970.14-186973.4" cell \right_mask \right_mask connect \mask \right_mask_mask connect \shift \right_mask_shift end attribute \module_not_derived 1 - attribute \src "libresoc.v:185666.8-185670.4" + attribute \src "libresoc.v:186974.8-186978.4" cell \rotl \rotl connect \a \rotl_a connect \b \rotl_b connect \o \rotl_o end - attribute \src "libresoc.v:185471.7-185471.20" - process $proc$libresoc.v:185471$12288 + attribute \src "libresoc.v:186779.7-186779.20" + process $proc$libresoc.v:186779$12272 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185671.3-185685.6" - process $proc$libresoc.v:185671$12273 + attribute \src "libresoc.v:186979.3-186993.6" + process $proc$libresoc.v:186979$12257 assign { } { } assign $0\hi32[31:0] $1\hi32[31:0] - attribute \src "libresoc.v:185672.5-185672.29" + attribute \src "libresoc.v:186980.5-186980.29" switch \initial - attribute \src "libresoc.v:185672.9-185672.17" + attribute \src "libresoc.v:186980.9-186980.17" case 1'1 case end @@ -381515,14 +352885,14 @@ module \rotator sync always update \hi32 $0\hi32[31:0] end - attribute \src "libresoc.v:185686.3-185695.6" - process $proc$libresoc.v:185686$12274 + attribute \src "libresoc.v:186994.3-187003.6" + process $proc$libresoc.v:186994$12258 assign { } { } assign { } { } assign $0\right_mask_shift[6:0] $1\right_mask_shift[6:0] - attribute \src "libresoc.v:185687.5-185687.29" + attribute \src "libresoc.v:186995.5-186995.29" switch \initial - attribute \src "libresoc.v:185687.9-185687.17" + attribute \src "libresoc.v:186995.9-186995.17" case 1'1 case end @@ -381538,13 +352908,13 @@ module \rotator sync always update \right_mask_shift $0\right_mask_shift[6:0] end - attribute \src "libresoc.v:185696.3-185707.6" - process $proc$libresoc.v:185696$12275 + attribute \src "libresoc.v:187004.3-187015.6" + process $proc$libresoc.v:187004$12259 assign { } { } assign $0\mr[63:0] $1\mr[63:0] - attribute \src "libresoc.v:185697.5-185697.29" + attribute \src "libresoc.v:187005.5-187005.29" switch \initial - attribute \src "libresoc.v:185697.9-185697.17" + attribute \src "libresoc.v:187005.9-187005.17" case 1'1 case end @@ -381562,13 +352932,13 @@ module \rotator sync always update \mr $0\mr[63:0] end - attribute \src "libresoc.v:185708.3-185719.6" - process $proc$libresoc.v:185708$12276 + attribute \src "libresoc.v:187016.3-187027.6" + process $proc$libresoc.v:187016$12260 assign { } { } assign $0\output_mode[1:0] $1\output_mode[1:0] - attribute \src "libresoc.v:185709.5-185709.29" + attribute \src "libresoc.v:187017.5-187017.29" switch \initial - attribute \src "libresoc.v:185709.9-185709.17" + attribute \src "libresoc.v:187017.9-187017.17" case 1'1 case end @@ -381586,14 +352956,14 @@ module \rotator sync always update \output_mode $0\output_mode[1:0] end - attribute \src "libresoc.v:185720.3-185738.6" - process $proc$libresoc.v:185720$12277 + attribute \src "libresoc.v:187028.3-187046.6" + process $proc$libresoc.v:187028$12261 assign { } { } assign { } { } assign $0\result_o[63:0] $1\result_o[63:0] - attribute \src "libresoc.v:185721.5-185721.29" + attribute \src "libresoc.v:187029.5-187029.29" switch \initial - attribute \src "libresoc.v:185721.9-185721.17" + attribute \src "libresoc.v:187029.9-187029.17" case 1'1 case end @@ -381621,20 +352991,29 @@ module \rotator sync always update \result_o $0\result_o[63:0] end - attribute \src "libresoc.v:185739.3-185748.6" - process $proc$libresoc.v:185739$12278 + attribute \src "libresoc.v:187047.3-187065.6" + process $proc$libresoc.v:187047$12262 assign { } { } assign { } { } assign $0\carry_out_o[0:0] $1\carry_out_o[0:0] - attribute \src "libresoc.v:185740.5-185740.29" + attribute \src "libresoc.v:187048.5-187048.29" switch \initial - attribute \src "libresoc.v:185740.9-185740.17" + attribute \src "libresoc.v:187048.9-187048.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:168" switch \output_mode attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign $1\carry_out_o[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign $1\carry_out_o[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign $1\carry_out_o[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } assign $1\carry_out_o[0:0] \$76 @@ -381644,13 +353023,13 @@ module \rotator sync always update \carry_out_o $0\carry_out_o[0:0] end - attribute \src "libresoc.v:185749.3-185760.6" - process $proc$libresoc.v:185749$12279 + attribute \src "libresoc.v:187066.3-187077.6" + process $proc$libresoc.v:187066$12263 assign { } { } assign $0\rot_count[5:0] $1\rot_count[5:0] - attribute \src "libresoc.v:185750.5-185750.29" + attribute \src "libresoc.v:187067.5-187067.29" switch \initial - attribute \src "libresoc.v:185750.9-185750.17" + attribute \src "libresoc.v:187067.9-187067.17" case 1'1 case end @@ -381668,13 +353047,13 @@ module \rotator sync always update \rot_count $0\rot_count[5:0] end - attribute \src "libresoc.v:185761.3-185794.6" - process $proc$libresoc.v:185761$12280 + attribute \src "libresoc.v:187078.3-187111.6" + process $proc$libresoc.v:187078$12264 assign { } { } - assign $0\mb$8[6:0]$12281 $1\mb$8[6:0]$12282 - attribute \src "libresoc.v:185762.5-185762.29" + assign $0\mb$8[6:0]$12265 $1\mb$8[6:0]$12266 + attribute \src "libresoc.v:187079.5-187079.29" switch \initial - attribute \src "libresoc.v:185762.9-185762.17" + attribute \src "libresoc.v:187079.9-187079.17" case 1'1 case end @@ -381683,48 +353062,48 @@ module \rotator attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\mb$8[6:0]$12282 [4:0] \$9 [4:0] - assign $1\mb$8[6:0]$12282 [6:5] $2\mb$8[6:5]$12283 + assign $1\mb$8[6:0]$12266 [4:0] \$9 [4:0] + assign $1\mb$8[6:0]$12266 [6:5] $2\mb$8[6:5]$12267 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:118" switch \is_32bit attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\mb$8[6:5]$12283 2'01 + assign $2\mb$8[6:5]$12267 2'01 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\mb$8[6:5]$12283 { 1'0 \mb_extra } + assign $2\mb$8[6:5]$12267 { 1'0 \mb_extra } end attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\mb$8[6:0]$12282 [4:0] \sh [4:0] - assign $1\mb$8[6:0]$12282 [6:5] $3\mb$8[6:5]$12284 + assign $1\mb$8[6:0]$12266 [4:0] \sh [4:0] + assign $1\mb$8[6:0]$12266 [6:5] $3\mb$8[6:5]$12268 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:125" switch \is_32bit attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\mb$8[6:5]$12284 { \sh [5] \$11 } + assign $3\mb$8[6:5]$12268 { \sh [5] \$11 } case - assign $3\mb$8[6:5]$12284 \sh [6:5] + assign $3\mb$8[6:5]$12268 \sh [6:5] end attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $1\mb$8[6:0]$12282 { 1'0 \is_32bit 5'00000 } + assign $1\mb$8[6:0]$12266 { 1'0 \is_32bit 5'00000 } end sync always - update \mb$8 $0\mb$8[6:0]$12281 + update \mb$8 $0\mb$8[6:0]$12265 end - attribute \src "libresoc.v:185795.3-185809.6" - process $proc$libresoc.v:185795$12285 + attribute \src "libresoc.v:187112.3-187126.6" + process $proc$libresoc.v:187112$12269 assign { } { } - assign $0\me$13[6:0]$12286 $1\me$13[6:0]$12287 - attribute \src "libresoc.v:185796.5-185796.29" + assign $0\me$13[6:0]$12270 $1\me$13[6:0]$12271 + attribute \src "libresoc.v:187113.5-187113.29" switch \initial - attribute \src "libresoc.v:185796.9-185796.17" + attribute \src "libresoc.v:187113.9-187113.17" case 1'1 case end @@ -381733,57 +353112,57 @@ module \rotator attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\me$13[6:0]$12287 { 2'01 \me } + assign $1\me$13[6:0]$12271 { 2'01 \me } attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $1\me$13[6:0]$12287 { 1'0 \mb_extra \mb } - attribute \src "libresoc.v:0.0-0.0" - case - assign { } { } - assign $1\me$13[6:0]$12287 { \sh [6] \$20 } - end - sync always - update \me$13 $0\me$13[6:0]$12286 - end - connect \$9 $pos$libresoc.v:185620$12235_Y - connect \$11 $not$libresoc.v:185621$12236_Y - connect \$14 $and$libresoc.v:185622$12237_Y - connect \$16 $not$libresoc.v:185623$12238_Y - connect \$18 $and$libresoc.v:185624$12239_Y - connect \$20 $not$libresoc.v:185625$12240_Y - connect \$22 $le$libresoc.v:185626$12241_Y - connect \$25 $sub$libresoc.v:185627$12242_Y - connect \$27 $le$libresoc.v:185628$12243_Y - connect \$2 $neg$libresoc.v:185629$12244_Y - connect \$30 $sub$libresoc.v:185630$12245_Y - connect \$32 $not$libresoc.v:185631$12246_Y - connect \$34 $not$libresoc.v:185632$12247_Y - connect \$36 $and$libresoc.v:185633$12248_Y - connect \$38 $or$libresoc.v:185634$12249_Y - connect \$40 $and$libresoc.v:185635$12250_Y - connect \$42 $gt$libresoc.v:185636$12251_Y - connect \$44 $and$libresoc.v:185637$12252_Y - connect \$46 $and$libresoc.v:185638$12253_Y - connect \$48 $and$libresoc.v:185639$12254_Y - connect \$4 $not$libresoc.v:185640$12255_Y - connect \$51 $and$libresoc.v:185641$12256_Y - connect \$50 $not$libresoc.v:185642$12257_Y - connect \$54 $and$libresoc.v:185643$12258_Y - connect \$56 $or$libresoc.v:185644$12259_Y - connect \$58 $or$libresoc.v:185645$12260_Y - connect \$60 $and$libresoc.v:185646$12261_Y - connect \$63 $or$libresoc.v:185647$12262_Y - connect \$62 $not$libresoc.v:185648$12263_Y - connect \$66 $and$libresoc.v:185649$12264_Y - connect \$68 $or$libresoc.v:185650$12265_Y - connect \$6 $and$libresoc.v:185651$12266_Y - connect \$70 $and$libresoc.v:185652$12267_Y - connect \$72 $not$libresoc.v:185653$12268_Y - connect \$74 $or$libresoc.v:185654$12269_Y - connect \$77 $not$libresoc.v:185655$12270_Y - connect \$79 $and$libresoc.v:185656$12271_Y - connect \$76 $reduce_or$libresoc.v:185657$12272_Y + assign $1\me$13[6:0]$12271 { 1'0 \mb_extra \mb } + attribute \src "libresoc.v:0.0-0.0" + case + assign { } { } + assign $1\me$13[6:0]$12271 { \sh [6] \$20 } + end + sync always + update \me$13 $0\me$13[6:0]$12270 + end + connect \$9 $pos$libresoc.v:186928$12219_Y + connect \$11 $not$libresoc.v:186929$12220_Y + connect \$14 $and$libresoc.v:186930$12221_Y + connect \$16 $not$libresoc.v:186931$12222_Y + connect \$18 $and$libresoc.v:186932$12223_Y + connect \$20 $not$libresoc.v:186933$12224_Y + connect \$22 $le$libresoc.v:186934$12225_Y + connect \$25 $sub$libresoc.v:186935$12226_Y + connect \$27 $le$libresoc.v:186936$12227_Y + connect \$2 $neg$libresoc.v:186937$12228_Y + connect \$30 $sub$libresoc.v:186938$12229_Y + connect \$32 $not$libresoc.v:186939$12230_Y + connect \$34 $not$libresoc.v:186940$12231_Y + connect \$36 $and$libresoc.v:186941$12232_Y + connect \$38 $or$libresoc.v:186942$12233_Y + connect \$40 $and$libresoc.v:186943$12234_Y + connect \$42 $gt$libresoc.v:186944$12235_Y + connect \$44 $and$libresoc.v:186945$12236_Y + connect \$46 $and$libresoc.v:186946$12237_Y + connect \$48 $and$libresoc.v:186947$12238_Y + connect \$4 $not$libresoc.v:186948$12239_Y + connect \$51 $and$libresoc.v:186949$12240_Y + connect \$50 $not$libresoc.v:186950$12241_Y + connect \$54 $and$libresoc.v:186951$12242_Y + connect \$56 $or$libresoc.v:186952$12243_Y + connect \$58 $or$libresoc.v:186953$12244_Y + connect \$60 $and$libresoc.v:186954$12245_Y + connect \$63 $or$libresoc.v:186955$12246_Y + connect \$62 $not$libresoc.v:186956$12247_Y + connect \$66 $and$libresoc.v:186957$12248_Y + connect \$68 $or$libresoc.v:186958$12249_Y + connect \$6 $and$libresoc.v:186959$12250_Y + connect \$70 $and$libresoc.v:186960$12251_Y + connect \$72 $not$libresoc.v:186961$12252_Y + connect \$74 $or$libresoc.v:186962$12253_Y + connect \$77 $not$libresoc.v:186963$12254_Y + connect \$79 $and$libresoc.v:186964$12255_Y + connect \$76 $reduce_or$libresoc.v:186965$12256_Y connect \$1 \$2 connect \$24 \$25 connect \$29 \$30 @@ -381796,15 +353175,15 @@ module \rotator connect \shift_signed \shift [5:0] connect \repl32 { \hi32 \rs [31:0] } end -attribute \src "libresoc.v:185825.1-185839.10" +attribute \src "libresoc.v:187142.1-187156.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.rotl" attribute \generator "nMigen" module \rotl - attribute \src "libresoc.v:185837.17-185837.32" - wire width 128 $shr$libresoc.v:185837$12290_Y - attribute \src "libresoc.v:185836.17-185836.100" - wire width 8 $sub$libresoc.v:185836$12289_Y + attribute \src "libresoc.v:187154.17-187154.32" + wire width 128 $shr$libresoc.v:187154$12274_Y + attribute \src "libresoc.v:187153.17-187153.100" + wire width 8 $sub$libresoc.v:187153$12273_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:19" wire width 64 \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" @@ -381815,8 +353194,8 @@ module \rotl wire width 6 input 1 \b attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:11" wire width 64 output 2 \o - attribute \src "libresoc.v:185837.17-185837.32" - cell $shr $shr$libresoc.v:185837$12290 + attribute \src "libresoc.v:187154.17-187154.32" + cell $shr $shr$libresoc.v:187154$12274 parameter \A_SIGNED 0 parameter \A_WIDTH 128 parameter \B_SIGNED 0 @@ -381824,10 +353203,10 @@ module \rotl parameter \Y_WIDTH 128 connect \A { \a \a } connect \B \$2 - connect \Y $shr$libresoc.v:185837$12290_Y + connect \Y $shr$libresoc.v:187154$12274_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" - cell $sub $sub$libresoc.v:185836$12289 + cell $sub $sub$libresoc.v:187153$12273 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -381835,43 +353214,43 @@ module \rotl parameter \Y_WIDTH 8 connect \A 7'1000000 connect \B \b - connect \Y $sub$libresoc.v:185836$12289_Y + connect \Y $sub$libresoc.v:187153$12273_Y end - connect \$2 $sub$libresoc.v:185836$12289_Y - connect \$1 $shr$libresoc.v:185837$12290_Y [63:0] + connect \$2 $sub$libresoc.v:187153$12273_Y + connect \$1 $shr$libresoc.v:187154$12274_Y [63:0] connect \o \$1 end -attribute \src "libresoc.v:185843.1-185901.10" +attribute \src "libresoc.v:187160.1-187218.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.rst_l" attribute \generator "nMigen" module \rst_l - attribute \src "libresoc.v:185844.7-185844.20" + attribute \src "libresoc.v:187161.7-187161.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185889.3-185897.6" - wire $0\q_int$next[0:0]$12301 - attribute \src "libresoc.v:185887.3-185888.27" + attribute \src "libresoc.v:187206.3-187214.6" + wire $0\q_int$next[0:0]$12285 + attribute \src "libresoc.v:187204.3-187205.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:185889.3-185897.6" - wire $1\q_int$next[0:0]$12302 - attribute \src "libresoc.v:185866.7-185866.19" + attribute \src "libresoc.v:187206.3-187214.6" + wire $1\q_int$next[0:0]$12286 + attribute \src "libresoc.v:187183.7-187183.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:185879.17-185879.96" - wire $and$libresoc.v:185879$12291_Y - attribute \src "libresoc.v:185884.17-185884.96" - wire $and$libresoc.v:185884$12296_Y - attribute \src "libresoc.v:185881.18-185881.93" - wire $not$libresoc.v:185881$12293_Y - attribute \src "libresoc.v:185883.17-185883.92" - wire $not$libresoc.v:185883$12295_Y - attribute \src "libresoc.v:185886.17-185886.92" - wire $not$libresoc.v:185886$12298_Y - attribute \src "libresoc.v:185880.18-185880.98" - wire $or$libresoc.v:185880$12292_Y - attribute \src "libresoc.v:185882.18-185882.99" - wire $or$libresoc.v:185882$12294_Y - attribute \src "libresoc.v:185885.17-185885.97" - wire $or$libresoc.v:185885$12297_Y + attribute \src "libresoc.v:187196.17-187196.96" + wire $and$libresoc.v:187196$12275_Y + attribute \src "libresoc.v:187201.17-187201.96" + wire $and$libresoc.v:187201$12280_Y + attribute \src "libresoc.v:187198.18-187198.93" + wire $not$libresoc.v:187198$12277_Y + attribute \src "libresoc.v:187200.17-187200.92" + wire $not$libresoc.v:187200$12279_Y + attribute \src "libresoc.v:187203.17-187203.92" + wire $not$libresoc.v:187203$12282_Y + attribute \src "libresoc.v:187197.18-187197.98" + wire $or$libresoc.v:187197$12276_Y + attribute \src "libresoc.v:187199.18-187199.99" + wire $or$libresoc.v:187199$12278_Y + attribute \src "libresoc.v:187202.17-187202.97" + wire $or$libresoc.v:187202$12281_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -381888,11 +353267,11 @@ module \rst_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:185844.7-185844.15" + attribute \src "libresoc.v:187161.7-187161.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -381909,7 +353288,7 @@ module \rst_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:185879$12291 + cell $and $and$libresoc.v:187196$12275 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381917,10 +353296,10 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:185879$12291_Y + connect \Y $and$libresoc.v:187196$12275_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:185884$12296 + cell $and $and$libresoc.v:187201$12280 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381928,34 +353307,34 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:185884$12296_Y + connect \Y $and$libresoc.v:187201$12280_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:185881$12293 + cell $not $not$libresoc.v:187198$12277 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:185881$12293_Y + connect \Y $not$libresoc.v:187198$12277_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:185883$12295 + cell $not $not$libresoc.v:187200$12279 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:185883$12295_Y + connect \Y $not$libresoc.v:187200$12279_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:185886$12298 + cell $not $not$libresoc.v:187203$12282 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:185886$12298_Y + connect \Y $not$libresoc.v:187203$12282_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:185880$12292 + cell $or $or$libresoc.v:187197$12276 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381963,10 +353342,10 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:185880$12292_Y + connect \Y $or$libresoc.v:187197$12276_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:185882$12294 + cell $or $or$libresoc.v:187199$12278 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381974,10 +353353,10 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:185882$12294_Y + connect \Y $or$libresoc.v:187199$12278_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:185885$12297 + cell $or $or$libresoc.v:187202$12281 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -381985,39 +353364,39 @@ module \rst_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:185885$12297_Y + connect \Y $or$libresoc.v:187202$12281_Y end - attribute \src "libresoc.v:185844.7-185844.20" - process $proc$libresoc.v:185844$12303 + attribute \src "libresoc.v:187161.7-187161.20" + process $proc$libresoc.v:187161$12287 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185866.7-185866.19" - process $proc$libresoc.v:185866$12304 + attribute \src "libresoc.v:187183.7-187183.19" + process $proc$libresoc.v:187183$12288 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:185887.3-185888.27" - process $proc$libresoc.v:185887$12299 + attribute \src "libresoc.v:187204.3-187205.27" + process $proc$libresoc.v:187204$12283 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:185889.3-185897.6" - process $proc$libresoc.v:185889$12300 + attribute \src "libresoc.v:187206.3-187214.6" + process $proc$libresoc.v:187206$12284 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12301 $1\q_int$next[0:0]$12302 - attribute \src "libresoc.v:185890.5-185890.29" + assign $0\q_int$next[0:0]$12285 $1\q_int$next[0:0]$12286 + attribute \src "libresoc.v:187207.5-187207.29" switch \initial - attribute \src "libresoc.v:185890.9-185890.17" + attribute \src "libresoc.v:187207.9-187207.17" case 1'1 case end @@ -382026,56 +353405,56 @@ module \rst_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12302 1'0 + assign $1\q_int$next[0:0]$12286 1'0 case - assign $1\q_int$next[0:0]$12302 \$5 + assign $1\q_int$next[0:0]$12286 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12301 + update \q_int$next $0\q_int$next[0:0]$12285 end - connect \$9 $and$libresoc.v:185879$12291_Y - connect \$11 $or$libresoc.v:185880$12292_Y - connect \$13 $not$libresoc.v:185881$12293_Y - connect \$15 $or$libresoc.v:185882$12294_Y - connect \$1 $not$libresoc.v:185883$12295_Y - connect \$3 $and$libresoc.v:185884$12296_Y - connect \$5 $or$libresoc.v:185885$12297_Y - connect \$7 $not$libresoc.v:185886$12298_Y + connect \$9 $and$libresoc.v:187196$12275_Y + connect \$11 $or$libresoc.v:187197$12276_Y + connect \$13 $not$libresoc.v:187198$12277_Y + connect \$15 $or$libresoc.v:187199$12278_Y + connect \$1 $not$libresoc.v:187200$12279_Y + connect \$3 $and$libresoc.v:187201$12280_Y + connect \$5 $or$libresoc.v:187202$12281_Y + connect \$7 $not$libresoc.v:187203$12282_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:185905.1-185963.10" +attribute \src "libresoc.v:187222.1-187280.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.rst_l" attribute \generator "nMigen" module \rst_l$104 - attribute \src "libresoc.v:185906.7-185906.20" + attribute \src "libresoc.v:187223.7-187223.20" wire $0\initial[0:0] - attribute \src "libresoc.v:185951.3-185959.6" - wire $0\q_int$next[0:0]$12315 - attribute \src "libresoc.v:185949.3-185950.27" + attribute \src "libresoc.v:187268.3-187276.6" + wire $0\q_int$next[0:0]$12299 + attribute \src "libresoc.v:187266.3-187267.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:185951.3-185959.6" - wire $1\q_int$next[0:0]$12316 - attribute \src "libresoc.v:185928.7-185928.19" + attribute \src "libresoc.v:187268.3-187276.6" + wire $1\q_int$next[0:0]$12300 + attribute \src "libresoc.v:187245.7-187245.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:185941.17-185941.96" - wire $and$libresoc.v:185941$12305_Y - attribute \src "libresoc.v:185946.17-185946.96" - wire $and$libresoc.v:185946$12310_Y - attribute \src "libresoc.v:185943.18-185943.93" - wire $not$libresoc.v:185943$12307_Y - attribute \src "libresoc.v:185945.17-185945.92" - wire $not$libresoc.v:185945$12309_Y - attribute \src "libresoc.v:185948.17-185948.92" - wire $not$libresoc.v:185948$12312_Y - attribute \src "libresoc.v:185942.18-185942.98" - wire $or$libresoc.v:185942$12306_Y - attribute \src "libresoc.v:185944.18-185944.99" - wire $or$libresoc.v:185944$12308_Y - attribute \src "libresoc.v:185947.17-185947.97" - wire $or$libresoc.v:185947$12311_Y + attribute \src "libresoc.v:187258.17-187258.96" + wire $and$libresoc.v:187258$12289_Y + attribute \src "libresoc.v:187263.17-187263.96" + wire $and$libresoc.v:187263$12294_Y + attribute \src "libresoc.v:187260.18-187260.93" + wire $not$libresoc.v:187260$12291_Y + attribute \src "libresoc.v:187262.17-187262.92" + wire $not$libresoc.v:187262$12293_Y + attribute \src "libresoc.v:187265.17-187265.92" + wire $not$libresoc.v:187265$12296_Y + attribute \src "libresoc.v:187259.18-187259.98" + wire $or$libresoc.v:187259$12290_Y + attribute \src "libresoc.v:187261.18-187261.99" + wire $or$libresoc.v:187261$12292_Y + attribute \src "libresoc.v:187264.17-187264.97" + wire $or$libresoc.v:187264$12295_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -382092,11 +353471,11 @@ module \rst_l$104 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:185906.7-185906.15" + attribute \src "libresoc.v:187223.7-187223.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -382113,7 +353492,7 @@ module \rst_l$104 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:185941$12305 + cell $and $and$libresoc.v:187258$12289 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382121,10 +353500,10 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:185941$12305_Y + connect \Y $and$libresoc.v:187258$12289_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:185946$12310 + cell $and $and$libresoc.v:187263$12294 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382132,34 +353511,34 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:185946$12310_Y + connect \Y $and$libresoc.v:187263$12294_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:185943$12307 + cell $not $not$libresoc.v:187260$12291 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:185943$12307_Y + connect \Y $not$libresoc.v:187260$12291_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:185945$12309 + cell $not $not$libresoc.v:187262$12293 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:185945$12309_Y + connect \Y $not$libresoc.v:187262$12293_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:185948$12312 + cell $not $not$libresoc.v:187265$12296 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:185948$12312_Y + connect \Y $not$libresoc.v:187265$12296_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:185942$12306 + cell $or $or$libresoc.v:187259$12290 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382167,10 +353546,10 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:185942$12306_Y + connect \Y $or$libresoc.v:187259$12290_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:185944$12308 + cell $or $or$libresoc.v:187261$12292 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382178,10 +353557,10 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:185944$12308_Y + connect \Y $or$libresoc.v:187261$12292_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:185947$12311 + cell $or $or$libresoc.v:187264$12295 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382189,39 +353568,39 @@ module \rst_l$104 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:185947$12311_Y + connect \Y $or$libresoc.v:187264$12295_Y end - attribute \src "libresoc.v:185906.7-185906.20" - process $proc$libresoc.v:185906$12317 + attribute \src "libresoc.v:187223.7-187223.20" + process $proc$libresoc.v:187223$12301 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185928.7-185928.19" - process $proc$libresoc.v:185928$12318 + attribute \src "libresoc.v:187245.7-187245.19" + process $proc$libresoc.v:187245$12302 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:185949.3-185950.27" - process $proc$libresoc.v:185949$12313 + attribute \src "libresoc.v:187266.3-187267.27" + process $proc$libresoc.v:187266$12297 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:185951.3-185959.6" - process $proc$libresoc.v:185951$12314 + attribute \src "libresoc.v:187268.3-187276.6" + process $proc$libresoc.v:187268$12298 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12315 $1\q_int$next[0:0]$12316 - attribute \src "libresoc.v:185952.5-185952.29" + assign $0\q_int$next[0:0]$12299 $1\q_int$next[0:0]$12300 + attribute \src "libresoc.v:187269.5-187269.29" switch \initial - attribute \src "libresoc.v:185952.9-185952.17" + attribute \src "libresoc.v:187269.9-187269.17" case 1'1 case end @@ -382230,56 +353609,56 @@ module \rst_l$104 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12316 1'0 + assign $1\q_int$next[0:0]$12300 1'0 case - assign $1\q_int$next[0:0]$12316 \$5 + assign $1\q_int$next[0:0]$12300 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12315 + update \q_int$next $0\q_int$next[0:0]$12299 end - connect \$9 $and$libresoc.v:185941$12305_Y - connect \$11 $or$libresoc.v:185942$12306_Y - connect \$13 $not$libresoc.v:185943$12307_Y - connect \$15 $or$libresoc.v:185944$12308_Y - connect \$1 $not$libresoc.v:185945$12309_Y - connect \$3 $and$libresoc.v:185946$12310_Y - connect \$5 $or$libresoc.v:185947$12311_Y - connect \$7 $not$libresoc.v:185948$12312_Y + connect \$9 $and$libresoc.v:187258$12289_Y + connect \$11 $or$libresoc.v:187259$12290_Y + connect \$13 $not$libresoc.v:187260$12291_Y + connect \$15 $or$libresoc.v:187261$12292_Y + connect \$1 $not$libresoc.v:187262$12293_Y + connect \$3 $and$libresoc.v:187263$12294_Y + connect \$5 $or$libresoc.v:187264$12295_Y + connect \$7 $not$libresoc.v:187265$12296_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:185967.1-186025.10" +attribute \src "libresoc.v:187284.1-187342.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.rst_l" attribute \generator "nMigen" module \rst_l$122 - attribute \src "libresoc.v:185968.7-185968.20" + attribute \src "libresoc.v:187285.7-187285.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186013.3-186021.6" - wire $0\q_int$next[0:0]$12329 - attribute \src "libresoc.v:186011.3-186012.27" + attribute \src "libresoc.v:187330.3-187338.6" + wire $0\q_int$next[0:0]$12313 + attribute \src "libresoc.v:187328.3-187329.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:186013.3-186021.6" - wire $1\q_int$next[0:0]$12330 - attribute \src "libresoc.v:185990.7-185990.19" + attribute \src "libresoc.v:187330.3-187338.6" + wire $1\q_int$next[0:0]$12314 + attribute \src "libresoc.v:187307.7-187307.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:186003.17-186003.96" - wire $and$libresoc.v:186003$12319_Y - attribute \src "libresoc.v:186008.17-186008.96" - wire $and$libresoc.v:186008$12324_Y - attribute \src "libresoc.v:186005.18-186005.93" - wire $not$libresoc.v:186005$12321_Y - attribute \src "libresoc.v:186007.17-186007.92" - wire $not$libresoc.v:186007$12323_Y - attribute \src "libresoc.v:186010.17-186010.92" - wire $not$libresoc.v:186010$12326_Y - attribute \src "libresoc.v:186004.18-186004.98" - wire $or$libresoc.v:186004$12320_Y - attribute \src "libresoc.v:186006.18-186006.99" - wire $or$libresoc.v:186006$12322_Y - attribute \src "libresoc.v:186009.17-186009.97" - wire $or$libresoc.v:186009$12325_Y + attribute \src "libresoc.v:187320.17-187320.96" + wire $and$libresoc.v:187320$12303_Y + attribute \src "libresoc.v:187325.17-187325.96" + wire $and$libresoc.v:187325$12308_Y + attribute \src "libresoc.v:187322.18-187322.93" + wire $not$libresoc.v:187322$12305_Y + attribute \src "libresoc.v:187324.17-187324.92" + wire $not$libresoc.v:187324$12307_Y + attribute \src "libresoc.v:187327.17-187327.92" + wire $not$libresoc.v:187327$12310_Y + attribute \src "libresoc.v:187321.18-187321.98" + wire $or$libresoc.v:187321$12304_Y + attribute \src "libresoc.v:187323.18-187323.99" + wire $or$libresoc.v:187323$12306_Y + attribute \src "libresoc.v:187326.17-187326.97" + wire $or$libresoc.v:187326$12309_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -382296,11 +353675,11 @@ module \rst_l$122 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:185968.7-185968.15" + attribute \src "libresoc.v:187285.7-187285.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -382317,7 +353696,7 @@ module \rst_l$122 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:186003$12319 + cell $and $and$libresoc.v:187320$12303 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382325,10 +353704,10 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:186003$12319_Y + connect \Y $and$libresoc.v:187320$12303_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:186008$12324 + cell $and $and$libresoc.v:187325$12308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382336,34 +353715,34 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:186008$12324_Y + connect \Y $and$libresoc.v:187325$12308_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:186005$12321 + cell $not $not$libresoc.v:187322$12305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:186005$12321_Y + connect \Y $not$libresoc.v:187322$12305_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:186007$12323 + cell $not $not$libresoc.v:187324$12307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186007$12323_Y + connect \Y $not$libresoc.v:187324$12307_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:186010$12326 + cell $not $not$libresoc.v:187327$12310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186010$12326_Y + connect \Y $not$libresoc.v:187327$12310_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:186004$12320 + cell $or $or$libresoc.v:187321$12304 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382371,10 +353750,10 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:186004$12320_Y + connect \Y $or$libresoc.v:187321$12304_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:186006$12322 + cell $or $or$libresoc.v:187323$12306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382382,10 +353761,10 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:186006$12322_Y + connect \Y $or$libresoc.v:187323$12306_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:186009$12325 + cell $or $or$libresoc.v:187326$12309 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382393,39 +353772,39 @@ module \rst_l$122 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:186009$12325_Y + connect \Y $or$libresoc.v:187326$12309_Y end - attribute \src "libresoc.v:185968.7-185968.20" - process $proc$libresoc.v:185968$12331 + attribute \src "libresoc.v:187285.7-187285.20" + process $proc$libresoc.v:187285$12315 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:185990.7-185990.19" - process $proc$libresoc.v:185990$12332 + attribute \src "libresoc.v:187307.7-187307.19" + process $proc$libresoc.v:187307$12316 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:186011.3-186012.27" - process $proc$libresoc.v:186011$12327 + attribute \src "libresoc.v:187328.3-187329.27" + process $proc$libresoc.v:187328$12311 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:186013.3-186021.6" - process $proc$libresoc.v:186013$12328 + attribute \src "libresoc.v:187330.3-187338.6" + process $proc$libresoc.v:187330$12312 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12329 $1\q_int$next[0:0]$12330 - attribute \src "libresoc.v:186014.5-186014.29" + assign $0\q_int$next[0:0]$12313 $1\q_int$next[0:0]$12314 + attribute \src "libresoc.v:187331.5-187331.29" switch \initial - attribute \src "libresoc.v:186014.9-186014.17" + attribute \src "libresoc.v:187331.9-187331.17" case 1'1 case end @@ -382434,56 +353813,56 @@ module \rst_l$122 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12330 1'0 + assign $1\q_int$next[0:0]$12314 1'0 case - assign $1\q_int$next[0:0]$12330 \$5 + assign $1\q_int$next[0:0]$12314 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12329 + update \q_int$next $0\q_int$next[0:0]$12313 end - connect \$9 $and$libresoc.v:186003$12319_Y - connect \$11 $or$libresoc.v:186004$12320_Y - connect \$13 $not$libresoc.v:186005$12321_Y - connect \$15 $or$libresoc.v:186006$12322_Y - connect \$1 $not$libresoc.v:186007$12323_Y - connect \$3 $and$libresoc.v:186008$12324_Y - connect \$5 $or$libresoc.v:186009$12325_Y - connect \$7 $not$libresoc.v:186010$12326_Y + connect \$9 $and$libresoc.v:187320$12303_Y + connect \$11 $or$libresoc.v:187321$12304_Y + connect \$13 $not$libresoc.v:187322$12305_Y + connect \$15 $or$libresoc.v:187323$12306_Y + connect \$1 $not$libresoc.v:187324$12307_Y + connect \$3 $and$libresoc.v:187325$12308_Y + connect \$5 $or$libresoc.v:187326$12309_Y + connect \$7 $not$libresoc.v:187327$12310_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:186029.1-186087.10" +attribute \src "libresoc.v:187346.1-187404.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.rst_l" attribute \generator "nMigen" module \rst_l$129 - attribute \src "libresoc.v:186030.7-186030.20" + attribute \src "libresoc.v:187347.7-187347.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186075.3-186083.6" - wire $0\q_int$next[0:0]$12343 - attribute \src "libresoc.v:186073.3-186074.27" + attribute \src "libresoc.v:187392.3-187400.6" + wire $0\q_int$next[0:0]$12327 + attribute \src "libresoc.v:187390.3-187391.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:186075.3-186083.6" - wire $1\q_int$next[0:0]$12344 - attribute \src "libresoc.v:186052.7-186052.19" + attribute \src "libresoc.v:187392.3-187400.6" + wire $1\q_int$next[0:0]$12328 + attribute \src "libresoc.v:187369.7-187369.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:186065.17-186065.96" - wire $and$libresoc.v:186065$12333_Y - attribute \src "libresoc.v:186070.17-186070.96" - wire $and$libresoc.v:186070$12338_Y - attribute \src "libresoc.v:186067.18-186067.93" - wire $not$libresoc.v:186067$12335_Y - attribute \src "libresoc.v:186069.17-186069.92" - wire $not$libresoc.v:186069$12337_Y - attribute \src "libresoc.v:186072.17-186072.92" - wire $not$libresoc.v:186072$12340_Y - attribute \src "libresoc.v:186066.18-186066.98" - wire $or$libresoc.v:186066$12334_Y - attribute \src "libresoc.v:186068.18-186068.99" - wire $or$libresoc.v:186068$12336_Y - attribute \src "libresoc.v:186071.17-186071.97" - wire $or$libresoc.v:186071$12339_Y + attribute \src "libresoc.v:187382.17-187382.96" + wire $and$libresoc.v:187382$12317_Y + attribute \src "libresoc.v:187387.17-187387.96" + wire $and$libresoc.v:187387$12322_Y + attribute \src "libresoc.v:187384.18-187384.93" + wire $not$libresoc.v:187384$12319_Y + attribute \src "libresoc.v:187386.17-187386.92" + wire $not$libresoc.v:187386$12321_Y + attribute \src "libresoc.v:187389.17-187389.92" + wire $not$libresoc.v:187389$12324_Y + attribute \src "libresoc.v:187383.18-187383.98" + wire $or$libresoc.v:187383$12318_Y + attribute \src "libresoc.v:187385.18-187385.99" + wire $or$libresoc.v:187385$12320_Y + attribute \src "libresoc.v:187388.17-187388.97" + wire $or$libresoc.v:187388$12323_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -382500,11 +353879,11 @@ module \rst_l$129 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:186030.7-186030.15" + attribute \src "libresoc.v:187347.7-187347.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -382521,7 +353900,7 @@ module \rst_l$129 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:186065$12333 + cell $and $and$libresoc.v:187382$12317 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382529,10 +353908,10 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:186065$12333_Y + connect \Y $and$libresoc.v:187382$12317_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:186070$12338 + cell $and $and$libresoc.v:187387$12322 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382540,34 +353919,34 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:186070$12338_Y + connect \Y $and$libresoc.v:187387$12322_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:186067$12335 + cell $not $not$libresoc.v:187384$12319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:186067$12335_Y + connect \Y $not$libresoc.v:187384$12319_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:186069$12337 + cell $not $not$libresoc.v:187386$12321 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186069$12337_Y + connect \Y $not$libresoc.v:187386$12321_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:186072$12340 + cell $not $not$libresoc.v:187389$12324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186072$12340_Y + connect \Y $not$libresoc.v:187389$12324_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:186066$12334 + cell $or $or$libresoc.v:187383$12318 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382575,10 +353954,10 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:186066$12334_Y + connect \Y $or$libresoc.v:187383$12318_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:186068$12336 + cell $or $or$libresoc.v:187385$12320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382586,10 +353965,10 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:186068$12336_Y + connect \Y $or$libresoc.v:187385$12320_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:186071$12339 + cell $or $or$libresoc.v:187388$12323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382597,39 +353976,39 @@ module \rst_l$129 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:186071$12339_Y + connect \Y $or$libresoc.v:187388$12323_Y end - attribute \src "libresoc.v:186030.7-186030.20" - process $proc$libresoc.v:186030$12345 + attribute \src "libresoc.v:187347.7-187347.20" + process $proc$libresoc.v:187347$12329 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:186052.7-186052.19" - process $proc$libresoc.v:186052$12346 + attribute \src "libresoc.v:187369.7-187369.19" + process $proc$libresoc.v:187369$12330 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:186073.3-186074.27" - process $proc$libresoc.v:186073$12341 + attribute \src "libresoc.v:187390.3-187391.27" + process $proc$libresoc.v:187390$12325 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:186075.3-186083.6" - process $proc$libresoc.v:186075$12342 + attribute \src "libresoc.v:187392.3-187400.6" + process $proc$libresoc.v:187392$12326 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12343 $1\q_int$next[0:0]$12344 - attribute \src "libresoc.v:186076.5-186076.29" + assign $0\q_int$next[0:0]$12327 $1\q_int$next[0:0]$12328 + attribute \src "libresoc.v:187393.5-187393.29" switch \initial - attribute \src "libresoc.v:186076.9-186076.17" + attribute \src "libresoc.v:187393.9-187393.17" case 1'1 case end @@ -382638,56 +354017,56 @@ module \rst_l$129 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12344 1'0 + assign $1\q_int$next[0:0]$12328 1'0 case - assign $1\q_int$next[0:0]$12344 \$5 + assign $1\q_int$next[0:0]$12328 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12343 + update \q_int$next $0\q_int$next[0:0]$12327 end - connect \$9 $and$libresoc.v:186065$12333_Y - connect \$11 $or$libresoc.v:186066$12334_Y - connect \$13 $not$libresoc.v:186067$12335_Y - connect \$15 $or$libresoc.v:186068$12336_Y - connect \$1 $not$libresoc.v:186069$12337_Y - connect \$3 $and$libresoc.v:186070$12338_Y - connect \$5 $or$libresoc.v:186071$12339_Y - connect \$7 $not$libresoc.v:186072$12340_Y + connect \$9 $and$libresoc.v:187382$12317_Y + connect \$11 $or$libresoc.v:187383$12318_Y + connect \$13 $not$libresoc.v:187384$12319_Y + connect \$15 $or$libresoc.v:187385$12320_Y + connect \$1 $not$libresoc.v:187386$12321_Y + connect \$3 $and$libresoc.v:187387$12322_Y + connect \$5 $or$libresoc.v:187388$12323_Y + connect \$7 $not$libresoc.v:187389$12324_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:186091.1-186149.10" +attribute \src "libresoc.v:187408.1-187466.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.rst_l" attribute \generator "nMigen" module \rst_l$13 - attribute \src "libresoc.v:186092.7-186092.20" + attribute \src "libresoc.v:187409.7-187409.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186137.3-186145.6" - wire $0\q_int$next[0:0]$12357 - attribute \src "libresoc.v:186135.3-186136.27" + attribute \src "libresoc.v:187454.3-187462.6" + wire $0\q_int$next[0:0]$12341 + attribute \src "libresoc.v:187452.3-187453.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:186137.3-186145.6" - wire $1\q_int$next[0:0]$12358 - attribute \src "libresoc.v:186114.7-186114.19" + attribute \src "libresoc.v:187454.3-187462.6" + wire $1\q_int$next[0:0]$12342 + attribute \src "libresoc.v:187431.7-187431.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:186127.17-186127.96" - wire $and$libresoc.v:186127$12347_Y - attribute \src "libresoc.v:186132.17-186132.96" - wire $and$libresoc.v:186132$12352_Y - attribute \src "libresoc.v:186129.18-186129.93" - wire $not$libresoc.v:186129$12349_Y - attribute \src "libresoc.v:186131.17-186131.92" - wire $not$libresoc.v:186131$12351_Y - attribute \src "libresoc.v:186134.17-186134.92" - wire $not$libresoc.v:186134$12354_Y - attribute \src "libresoc.v:186128.18-186128.98" - wire $or$libresoc.v:186128$12348_Y - attribute \src "libresoc.v:186130.18-186130.99" - wire $or$libresoc.v:186130$12350_Y - attribute \src "libresoc.v:186133.17-186133.97" - wire $or$libresoc.v:186133$12353_Y + attribute \src "libresoc.v:187444.17-187444.96" + wire $and$libresoc.v:187444$12331_Y + attribute \src "libresoc.v:187449.17-187449.96" + wire $and$libresoc.v:187449$12336_Y + attribute \src "libresoc.v:187446.18-187446.93" + wire $not$libresoc.v:187446$12333_Y + attribute \src "libresoc.v:187448.17-187448.92" + wire $not$libresoc.v:187448$12335_Y + attribute \src "libresoc.v:187451.17-187451.92" + wire $not$libresoc.v:187451$12338_Y + attribute \src "libresoc.v:187445.18-187445.98" + wire $or$libresoc.v:187445$12332_Y + attribute \src "libresoc.v:187447.18-187447.99" + wire $or$libresoc.v:187447$12334_Y + attribute \src "libresoc.v:187450.17-187450.97" + wire $or$libresoc.v:187450$12337_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -382704,11 +354083,11 @@ module \rst_l$13 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:186092.7-186092.15" + attribute \src "libresoc.v:187409.7-187409.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -382725,7 +354104,7 @@ module \rst_l$13 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:186127$12347 + cell $and $and$libresoc.v:187444$12331 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382733,10 +354112,10 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:186127$12347_Y + connect \Y $and$libresoc.v:187444$12331_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:186132$12352 + cell $and $and$libresoc.v:187449$12336 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382744,34 +354123,34 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:186132$12352_Y + connect \Y $and$libresoc.v:187449$12336_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:186129$12349 + cell $not $not$libresoc.v:187446$12333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:186129$12349_Y + connect \Y $not$libresoc.v:187446$12333_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:186131$12351 + cell $not $not$libresoc.v:187448$12335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186131$12351_Y + connect \Y $not$libresoc.v:187448$12335_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:186134$12354 + cell $not $not$libresoc.v:187451$12338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186134$12354_Y + connect \Y $not$libresoc.v:187451$12338_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:186128$12348 + cell $or $or$libresoc.v:187445$12332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382779,10 +354158,10 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:186128$12348_Y + connect \Y $or$libresoc.v:187445$12332_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:186130$12350 + cell $or $or$libresoc.v:187447$12334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382790,10 +354169,10 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:186130$12350_Y + connect \Y $or$libresoc.v:187447$12334_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:186133$12353 + cell $or $or$libresoc.v:187450$12337 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382801,39 +354180,39 @@ module \rst_l$13 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:186133$12353_Y + connect \Y $or$libresoc.v:187450$12337_Y end - attribute \src "libresoc.v:186092.7-186092.20" - process $proc$libresoc.v:186092$12359 + attribute \src "libresoc.v:187409.7-187409.20" + process $proc$libresoc.v:187409$12343 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:186114.7-186114.19" - process $proc$libresoc.v:186114$12360 + attribute \src "libresoc.v:187431.7-187431.19" + process $proc$libresoc.v:187431$12344 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:186135.3-186136.27" - process $proc$libresoc.v:186135$12355 + attribute \src "libresoc.v:187452.3-187453.27" + process $proc$libresoc.v:187452$12339 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:186137.3-186145.6" - process $proc$libresoc.v:186137$12356 + attribute \src "libresoc.v:187454.3-187462.6" + process $proc$libresoc.v:187454$12340 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12357 $1\q_int$next[0:0]$12358 - attribute \src "libresoc.v:186138.5-186138.29" + assign $0\q_int$next[0:0]$12341 $1\q_int$next[0:0]$12342 + attribute \src "libresoc.v:187455.5-187455.29" switch \initial - attribute \src "libresoc.v:186138.9-186138.17" + attribute \src "libresoc.v:187455.9-187455.17" case 1'1 case end @@ -382842,56 +354221,56 @@ module \rst_l$13 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12358 1'0 + assign $1\q_int$next[0:0]$12342 1'0 case - assign $1\q_int$next[0:0]$12358 \$5 + assign $1\q_int$next[0:0]$12342 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12357 + update \q_int$next $0\q_int$next[0:0]$12341 end - connect \$9 $and$libresoc.v:186127$12347_Y - connect \$11 $or$libresoc.v:186128$12348_Y - connect \$13 $not$libresoc.v:186129$12349_Y - connect \$15 $or$libresoc.v:186130$12350_Y - connect \$1 $not$libresoc.v:186131$12351_Y - connect \$3 $and$libresoc.v:186132$12352_Y - connect \$5 $or$libresoc.v:186133$12353_Y - connect \$7 $not$libresoc.v:186134$12354_Y + connect \$9 $and$libresoc.v:187444$12331_Y + connect \$11 $or$libresoc.v:187445$12332_Y + connect \$13 $not$libresoc.v:187446$12333_Y + connect \$15 $or$libresoc.v:187447$12334_Y + connect \$1 $not$libresoc.v:187448$12335_Y + connect \$3 $and$libresoc.v:187449$12336_Y + connect \$5 $or$libresoc.v:187450$12337_Y + connect \$7 $not$libresoc.v:187451$12338_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:186153.1-186211.10" +attribute \src "libresoc.v:187470.1-187528.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.rst_l" attribute \generator "nMigen" module \rst_l$26 - attribute \src "libresoc.v:186154.7-186154.20" + attribute \src "libresoc.v:187471.7-187471.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186199.3-186207.6" - wire $0\q_int$next[0:0]$12371 - attribute \src "libresoc.v:186197.3-186198.27" + attribute \src "libresoc.v:187516.3-187524.6" + wire $0\q_int$next[0:0]$12355 + attribute \src "libresoc.v:187514.3-187515.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:186199.3-186207.6" - wire $1\q_int$next[0:0]$12372 - attribute \src "libresoc.v:186176.7-186176.19" + attribute \src "libresoc.v:187516.3-187524.6" + wire $1\q_int$next[0:0]$12356 + attribute \src "libresoc.v:187493.7-187493.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:186189.17-186189.96" - wire $and$libresoc.v:186189$12361_Y - attribute \src "libresoc.v:186194.17-186194.96" - wire $and$libresoc.v:186194$12366_Y - attribute \src "libresoc.v:186191.18-186191.93" - wire $not$libresoc.v:186191$12363_Y - attribute \src "libresoc.v:186193.17-186193.92" - wire $not$libresoc.v:186193$12365_Y - attribute \src "libresoc.v:186196.17-186196.92" - wire $not$libresoc.v:186196$12368_Y - attribute \src "libresoc.v:186190.18-186190.98" - wire $or$libresoc.v:186190$12362_Y - attribute \src "libresoc.v:186192.18-186192.99" - wire $or$libresoc.v:186192$12364_Y - attribute \src "libresoc.v:186195.17-186195.97" - wire $or$libresoc.v:186195$12367_Y + attribute \src "libresoc.v:187506.17-187506.96" + wire $and$libresoc.v:187506$12345_Y + attribute \src "libresoc.v:187511.17-187511.96" + wire $and$libresoc.v:187511$12350_Y + attribute \src "libresoc.v:187508.18-187508.93" + wire $not$libresoc.v:187508$12347_Y + attribute \src "libresoc.v:187510.17-187510.92" + wire $not$libresoc.v:187510$12349_Y + attribute \src "libresoc.v:187513.17-187513.92" + wire $not$libresoc.v:187513$12352_Y + attribute \src "libresoc.v:187507.18-187507.98" + wire $or$libresoc.v:187507$12346_Y + attribute \src "libresoc.v:187509.18-187509.99" + wire $or$libresoc.v:187509$12348_Y + attribute \src "libresoc.v:187512.17-187512.97" + wire $or$libresoc.v:187512$12351_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -382908,11 +354287,11 @@ module \rst_l$26 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:186154.7-186154.15" + attribute \src "libresoc.v:187471.7-187471.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -382929,7 +354308,7 @@ module \rst_l$26 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:186189$12361 + cell $and $and$libresoc.v:187506$12345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382937,10 +354316,10 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:186189$12361_Y + connect \Y $and$libresoc.v:187506$12345_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:186194$12366 + cell $and $and$libresoc.v:187511$12350 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382948,34 +354327,34 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:186194$12366_Y + connect \Y $and$libresoc.v:187511$12350_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:186191$12363 + cell $not $not$libresoc.v:187508$12347 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:186191$12363_Y + connect \Y $not$libresoc.v:187508$12347_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:186193$12365 + cell $not $not$libresoc.v:187510$12349 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186193$12365_Y + connect \Y $not$libresoc.v:187510$12349_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:186196$12368 + cell $not $not$libresoc.v:187513$12352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186196$12368_Y + connect \Y $not$libresoc.v:187513$12352_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:186190$12362 + cell $or $or$libresoc.v:187507$12346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382983,10 +354362,10 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:186190$12362_Y + connect \Y $or$libresoc.v:187507$12346_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:186192$12364 + cell $or $or$libresoc.v:187509$12348 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -382994,10 +354373,10 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:186192$12364_Y + connect \Y $or$libresoc.v:187509$12348_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:186195$12367 + cell $or $or$libresoc.v:187512$12351 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383005,39 +354384,39 @@ module \rst_l$26 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:186195$12367_Y + connect \Y $or$libresoc.v:187512$12351_Y end - attribute \src "libresoc.v:186154.7-186154.20" - process $proc$libresoc.v:186154$12373 + attribute \src "libresoc.v:187471.7-187471.20" + process $proc$libresoc.v:187471$12357 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:186176.7-186176.19" - process $proc$libresoc.v:186176$12374 + attribute \src "libresoc.v:187493.7-187493.19" + process $proc$libresoc.v:187493$12358 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:186197.3-186198.27" - process $proc$libresoc.v:186197$12369 + attribute \src "libresoc.v:187514.3-187515.27" + process $proc$libresoc.v:187514$12353 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:186199.3-186207.6" - process $proc$libresoc.v:186199$12370 + attribute \src "libresoc.v:187516.3-187524.6" + process $proc$libresoc.v:187516$12354 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12371 $1\q_int$next[0:0]$12372 - attribute \src "libresoc.v:186200.5-186200.29" + assign $0\q_int$next[0:0]$12355 $1\q_int$next[0:0]$12356 + attribute \src "libresoc.v:187517.5-187517.29" switch \initial - attribute \src "libresoc.v:186200.9-186200.17" + attribute \src "libresoc.v:187517.9-187517.17" case 1'1 case end @@ -383046,56 +354425,56 @@ module \rst_l$26 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12372 1'0 + assign $1\q_int$next[0:0]$12356 1'0 case - assign $1\q_int$next[0:0]$12372 \$5 + assign $1\q_int$next[0:0]$12356 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12371 + update \q_int$next $0\q_int$next[0:0]$12355 end - connect \$9 $and$libresoc.v:186189$12361_Y - connect \$11 $or$libresoc.v:186190$12362_Y - connect \$13 $not$libresoc.v:186191$12363_Y - connect \$15 $or$libresoc.v:186192$12364_Y - connect \$1 $not$libresoc.v:186193$12365_Y - connect \$3 $and$libresoc.v:186194$12366_Y - connect \$5 $or$libresoc.v:186195$12367_Y - connect \$7 $not$libresoc.v:186196$12368_Y + connect \$9 $and$libresoc.v:187506$12345_Y + connect \$11 $or$libresoc.v:187507$12346_Y + connect \$13 $not$libresoc.v:187508$12347_Y + connect \$15 $or$libresoc.v:187509$12348_Y + connect \$1 $not$libresoc.v:187510$12349_Y + connect \$3 $and$libresoc.v:187511$12350_Y + connect \$5 $or$libresoc.v:187512$12351_Y + connect \$7 $not$libresoc.v:187513$12352_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:186215.1-186273.10" +attribute \src "libresoc.v:187532.1-187590.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.rst_l" attribute \generator "nMigen" module \rst_l$42 - attribute \src "libresoc.v:186216.7-186216.20" + attribute \src "libresoc.v:187533.7-187533.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186261.3-186269.6" - wire $0\q_int$next[0:0]$12385 - attribute \src "libresoc.v:186259.3-186260.27" + attribute \src "libresoc.v:187578.3-187586.6" + wire $0\q_int$next[0:0]$12369 + attribute \src "libresoc.v:187576.3-187577.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:186261.3-186269.6" - wire $1\q_int$next[0:0]$12386 - attribute \src "libresoc.v:186238.7-186238.19" + attribute \src "libresoc.v:187578.3-187586.6" + wire $1\q_int$next[0:0]$12370 + attribute \src "libresoc.v:187555.7-187555.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:186251.17-186251.96" - wire $and$libresoc.v:186251$12375_Y - attribute \src "libresoc.v:186256.17-186256.96" - wire $and$libresoc.v:186256$12380_Y - attribute \src "libresoc.v:186253.18-186253.93" - wire $not$libresoc.v:186253$12377_Y - attribute \src "libresoc.v:186255.17-186255.92" - wire $not$libresoc.v:186255$12379_Y - attribute \src "libresoc.v:186258.17-186258.92" - wire $not$libresoc.v:186258$12382_Y - attribute \src "libresoc.v:186252.18-186252.98" - wire $or$libresoc.v:186252$12376_Y - attribute \src "libresoc.v:186254.18-186254.99" - wire $or$libresoc.v:186254$12378_Y - attribute \src "libresoc.v:186257.17-186257.97" - wire $or$libresoc.v:186257$12381_Y + attribute \src "libresoc.v:187568.17-187568.96" + wire $and$libresoc.v:187568$12359_Y + attribute \src "libresoc.v:187573.17-187573.96" + wire $and$libresoc.v:187573$12364_Y + attribute \src "libresoc.v:187570.18-187570.93" + wire $not$libresoc.v:187570$12361_Y + attribute \src "libresoc.v:187572.17-187572.92" + wire $not$libresoc.v:187572$12363_Y + attribute \src "libresoc.v:187575.17-187575.92" + wire $not$libresoc.v:187575$12366_Y + attribute \src "libresoc.v:187569.18-187569.98" + wire $or$libresoc.v:187569$12360_Y + attribute \src "libresoc.v:187571.18-187571.99" + wire $or$libresoc.v:187571$12362_Y + attribute \src "libresoc.v:187574.17-187574.97" + wire $or$libresoc.v:187574$12365_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -383112,11 +354491,11 @@ module \rst_l$42 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:186216.7-186216.15" + attribute \src "libresoc.v:187533.7-187533.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -383133,7 +354512,7 @@ module \rst_l$42 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:186251$12375 + cell $and $and$libresoc.v:187568$12359 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383141,10 +354520,10 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:186251$12375_Y + connect \Y $and$libresoc.v:187568$12359_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:186256$12380 + cell $and $and$libresoc.v:187573$12364 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383152,34 +354531,34 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:186256$12380_Y + connect \Y $and$libresoc.v:187573$12364_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:186253$12377 + cell $not $not$libresoc.v:187570$12361 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:186253$12377_Y + connect \Y $not$libresoc.v:187570$12361_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:186255$12379 + cell $not $not$libresoc.v:187572$12363 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186255$12379_Y + connect \Y $not$libresoc.v:187572$12363_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:186258$12382 + cell $not $not$libresoc.v:187575$12366 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186258$12382_Y + connect \Y $not$libresoc.v:187575$12366_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:186252$12376 + cell $or $or$libresoc.v:187569$12360 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383187,10 +354566,10 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:186252$12376_Y + connect \Y $or$libresoc.v:187569$12360_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:186254$12378 + cell $or $or$libresoc.v:187571$12362 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383198,10 +354577,10 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:186254$12378_Y + connect \Y $or$libresoc.v:187571$12362_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:186257$12381 + cell $or $or$libresoc.v:187574$12365 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383209,39 +354588,39 @@ module \rst_l$42 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:186257$12381_Y + connect \Y $or$libresoc.v:187574$12365_Y end - attribute \src "libresoc.v:186216.7-186216.20" - process $proc$libresoc.v:186216$12387 + attribute \src "libresoc.v:187533.7-187533.20" + process $proc$libresoc.v:187533$12371 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:186238.7-186238.19" - process $proc$libresoc.v:186238$12388 + attribute \src "libresoc.v:187555.7-187555.19" + process $proc$libresoc.v:187555$12372 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:186259.3-186260.27" - process $proc$libresoc.v:186259$12383 + attribute \src "libresoc.v:187576.3-187577.27" + process $proc$libresoc.v:187576$12367 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:186261.3-186269.6" - process $proc$libresoc.v:186261$12384 + attribute \src "libresoc.v:187578.3-187586.6" + process $proc$libresoc.v:187578$12368 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12385 $1\q_int$next[0:0]$12386 - attribute \src "libresoc.v:186262.5-186262.29" + assign $0\q_int$next[0:0]$12369 $1\q_int$next[0:0]$12370 + attribute \src "libresoc.v:187579.5-187579.29" switch \initial - attribute \src "libresoc.v:186262.9-186262.17" + attribute \src "libresoc.v:187579.9-187579.17" case 1'1 case end @@ -383250,56 +354629,56 @@ module \rst_l$42 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12386 1'0 + assign $1\q_int$next[0:0]$12370 1'0 case - assign $1\q_int$next[0:0]$12386 \$5 + assign $1\q_int$next[0:0]$12370 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12385 + update \q_int$next $0\q_int$next[0:0]$12369 end - connect \$9 $and$libresoc.v:186251$12375_Y - connect \$11 $or$libresoc.v:186252$12376_Y - connect \$13 $not$libresoc.v:186253$12377_Y - connect \$15 $or$libresoc.v:186254$12378_Y - connect \$1 $not$libresoc.v:186255$12379_Y - connect \$3 $and$libresoc.v:186256$12380_Y - connect \$5 $or$libresoc.v:186257$12381_Y - connect \$7 $not$libresoc.v:186258$12382_Y + connect \$9 $and$libresoc.v:187568$12359_Y + connect \$11 $or$libresoc.v:187569$12360_Y + connect \$13 $not$libresoc.v:187570$12361_Y + connect \$15 $or$libresoc.v:187571$12362_Y + connect \$1 $not$libresoc.v:187572$12363_Y + connect \$3 $and$libresoc.v:187573$12364_Y + connect \$5 $or$libresoc.v:187574$12365_Y + connect \$7 $not$libresoc.v:187575$12366_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:186277.1-186335.10" +attribute \src "libresoc.v:187594.1-187652.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.rst_l" attribute \generator "nMigen" module \rst_l$58 - attribute \src "libresoc.v:186278.7-186278.20" + attribute \src "libresoc.v:187595.7-187595.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186323.3-186331.6" - wire $0\q_int$next[0:0]$12399 - attribute \src "libresoc.v:186321.3-186322.27" + attribute \src "libresoc.v:187640.3-187648.6" + wire $0\q_int$next[0:0]$12383 + attribute \src "libresoc.v:187638.3-187639.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:186323.3-186331.6" - wire $1\q_int$next[0:0]$12400 - attribute \src "libresoc.v:186300.7-186300.19" + attribute \src "libresoc.v:187640.3-187648.6" + wire $1\q_int$next[0:0]$12384 + attribute \src "libresoc.v:187617.7-187617.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:186313.17-186313.96" - wire $and$libresoc.v:186313$12389_Y - attribute \src "libresoc.v:186318.17-186318.96" - wire $and$libresoc.v:186318$12394_Y - attribute \src "libresoc.v:186315.18-186315.93" - wire $not$libresoc.v:186315$12391_Y - attribute \src "libresoc.v:186317.17-186317.92" - wire $not$libresoc.v:186317$12393_Y - attribute \src "libresoc.v:186320.17-186320.92" - wire $not$libresoc.v:186320$12396_Y - attribute \src "libresoc.v:186314.18-186314.98" - wire $or$libresoc.v:186314$12390_Y - attribute \src "libresoc.v:186316.18-186316.99" - wire $or$libresoc.v:186316$12392_Y - attribute \src "libresoc.v:186319.17-186319.97" - wire $or$libresoc.v:186319$12395_Y + attribute \src "libresoc.v:187630.17-187630.96" + wire $and$libresoc.v:187630$12373_Y + attribute \src "libresoc.v:187635.17-187635.96" + wire $and$libresoc.v:187635$12378_Y + attribute \src "libresoc.v:187632.18-187632.93" + wire $not$libresoc.v:187632$12375_Y + attribute \src "libresoc.v:187634.17-187634.92" + wire $not$libresoc.v:187634$12377_Y + attribute \src "libresoc.v:187637.17-187637.92" + wire $not$libresoc.v:187637$12380_Y + attribute \src "libresoc.v:187631.18-187631.98" + wire $or$libresoc.v:187631$12374_Y + attribute \src "libresoc.v:187633.18-187633.99" + wire $or$libresoc.v:187633$12376_Y + attribute \src "libresoc.v:187636.17-187636.97" + wire $or$libresoc.v:187636$12379_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -383316,11 +354695,11 @@ module \rst_l$58 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:186278.7-186278.15" + attribute \src "libresoc.v:187595.7-187595.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -383337,7 +354716,7 @@ module \rst_l$58 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:186313$12389 + cell $and $and$libresoc.v:187630$12373 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383345,10 +354724,10 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:186313$12389_Y + connect \Y $and$libresoc.v:187630$12373_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:186318$12394 + cell $and $and$libresoc.v:187635$12378 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383356,34 +354735,34 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:186318$12394_Y + connect \Y $and$libresoc.v:187635$12378_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:186315$12391 + cell $not $not$libresoc.v:187632$12375 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:186315$12391_Y + connect \Y $not$libresoc.v:187632$12375_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:186317$12393 + cell $not $not$libresoc.v:187634$12377 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186317$12393_Y + connect \Y $not$libresoc.v:187634$12377_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:186320$12396 + cell $not $not$libresoc.v:187637$12380 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186320$12396_Y + connect \Y $not$libresoc.v:187637$12380_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:186314$12390 + cell $or $or$libresoc.v:187631$12374 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383391,10 +354770,10 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:186314$12390_Y + connect \Y $or$libresoc.v:187631$12374_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:186316$12392 + cell $or $or$libresoc.v:187633$12376 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383402,10 +354781,10 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:186316$12392_Y + connect \Y $or$libresoc.v:187633$12376_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:186319$12395 + cell $or $or$libresoc.v:187636$12379 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383413,39 +354792,39 @@ module \rst_l$58 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:186319$12395_Y + connect \Y $or$libresoc.v:187636$12379_Y end - attribute \src "libresoc.v:186278.7-186278.20" - process $proc$libresoc.v:186278$12401 + attribute \src "libresoc.v:187595.7-187595.20" + process $proc$libresoc.v:187595$12385 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:186300.7-186300.19" - process $proc$libresoc.v:186300$12402 + attribute \src "libresoc.v:187617.7-187617.19" + process $proc$libresoc.v:187617$12386 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:186321.3-186322.27" - process $proc$libresoc.v:186321$12397 + attribute \src "libresoc.v:187638.3-187639.27" + process $proc$libresoc.v:187638$12381 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:186323.3-186331.6" - process $proc$libresoc.v:186323$12398 + attribute \src "libresoc.v:187640.3-187648.6" + process $proc$libresoc.v:187640$12382 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12399 $1\q_int$next[0:0]$12400 - attribute \src "libresoc.v:186324.5-186324.29" + assign $0\q_int$next[0:0]$12383 $1\q_int$next[0:0]$12384 + attribute \src "libresoc.v:187641.5-187641.29" switch \initial - attribute \src "libresoc.v:186324.9-186324.17" + attribute \src "libresoc.v:187641.9-187641.17" case 1'1 case end @@ -383454,56 +354833,56 @@ module \rst_l$58 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12400 1'0 + assign $1\q_int$next[0:0]$12384 1'0 case - assign $1\q_int$next[0:0]$12400 \$5 + assign $1\q_int$next[0:0]$12384 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12399 + update \q_int$next $0\q_int$next[0:0]$12383 end - connect \$9 $and$libresoc.v:186313$12389_Y - connect \$11 $or$libresoc.v:186314$12390_Y - connect \$13 $not$libresoc.v:186315$12391_Y - connect \$15 $or$libresoc.v:186316$12392_Y - connect \$1 $not$libresoc.v:186317$12393_Y - connect \$3 $and$libresoc.v:186318$12394_Y - connect \$5 $or$libresoc.v:186319$12395_Y - connect \$7 $not$libresoc.v:186320$12396_Y + connect \$9 $and$libresoc.v:187630$12373_Y + connect \$11 $or$libresoc.v:187631$12374_Y + connect \$13 $not$libresoc.v:187632$12375_Y + connect \$15 $or$libresoc.v:187633$12376_Y + connect \$1 $not$libresoc.v:187634$12377_Y + connect \$3 $and$libresoc.v:187635$12378_Y + connect \$5 $or$libresoc.v:187636$12379_Y + connect \$7 $not$libresoc.v:187637$12380_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:186339.1-186397.10" +attribute \src "libresoc.v:187656.1-187714.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.rst_l" attribute \generator "nMigen" module \rst_l$70 - attribute \src "libresoc.v:186340.7-186340.20" + attribute \src "libresoc.v:187657.7-187657.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186385.3-186393.6" - wire $0\q_int$next[0:0]$12413 - attribute \src "libresoc.v:186383.3-186384.27" + attribute \src "libresoc.v:187702.3-187710.6" + wire $0\q_int$next[0:0]$12397 + attribute \src "libresoc.v:187700.3-187701.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:186385.3-186393.6" - wire $1\q_int$next[0:0]$12414 - attribute \src "libresoc.v:186362.7-186362.19" + attribute \src "libresoc.v:187702.3-187710.6" + wire $1\q_int$next[0:0]$12398 + attribute \src "libresoc.v:187679.7-187679.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:186375.17-186375.96" - wire $and$libresoc.v:186375$12403_Y - attribute \src "libresoc.v:186380.17-186380.96" - wire $and$libresoc.v:186380$12408_Y - attribute \src "libresoc.v:186377.18-186377.93" - wire $not$libresoc.v:186377$12405_Y - attribute \src "libresoc.v:186379.17-186379.92" - wire $not$libresoc.v:186379$12407_Y - attribute \src "libresoc.v:186382.17-186382.92" - wire $not$libresoc.v:186382$12410_Y - attribute \src "libresoc.v:186376.18-186376.98" - wire $or$libresoc.v:186376$12404_Y - attribute \src "libresoc.v:186378.18-186378.99" - wire $or$libresoc.v:186378$12406_Y - attribute \src "libresoc.v:186381.17-186381.97" - wire $or$libresoc.v:186381$12409_Y + attribute \src "libresoc.v:187692.17-187692.96" + wire $and$libresoc.v:187692$12387_Y + attribute \src "libresoc.v:187697.17-187697.96" + wire $and$libresoc.v:187697$12392_Y + attribute \src "libresoc.v:187694.18-187694.93" + wire $not$libresoc.v:187694$12389_Y + attribute \src "libresoc.v:187696.17-187696.92" + wire $not$libresoc.v:187696$12391_Y + attribute \src "libresoc.v:187699.17-187699.92" + wire $not$libresoc.v:187699$12394_Y + attribute \src "libresoc.v:187693.18-187693.98" + wire $or$libresoc.v:187693$12388_Y + attribute \src "libresoc.v:187695.18-187695.99" + wire $or$libresoc.v:187695$12390_Y + attribute \src "libresoc.v:187698.17-187698.97" + wire $or$libresoc.v:187698$12393_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -383520,11 +354899,11 @@ module \rst_l$70 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:186340.7-186340.15" + attribute \src "libresoc.v:187657.7-187657.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -383541,7 +354920,7 @@ module \rst_l$70 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:186375$12403 + cell $and $and$libresoc.v:187692$12387 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383549,10 +354928,10 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:186375$12403_Y + connect \Y $and$libresoc.v:187692$12387_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:186380$12408 + cell $and $and$libresoc.v:187697$12392 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383560,34 +354939,34 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:186380$12408_Y + connect \Y $and$libresoc.v:187697$12392_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:186377$12405 + cell $not $not$libresoc.v:187694$12389 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:186377$12405_Y + connect \Y $not$libresoc.v:187694$12389_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:186379$12407 + cell $not $not$libresoc.v:187696$12391 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186379$12407_Y + connect \Y $not$libresoc.v:187696$12391_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:186382$12410 + cell $not $not$libresoc.v:187699$12394 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186382$12410_Y + connect \Y $not$libresoc.v:187699$12394_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:186376$12404 + cell $or $or$libresoc.v:187693$12388 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383595,10 +354974,10 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:186376$12404_Y + connect \Y $or$libresoc.v:187693$12388_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:186378$12406 + cell $or $or$libresoc.v:187695$12390 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383606,10 +354985,10 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:186378$12406_Y + connect \Y $or$libresoc.v:187695$12390_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:186381$12409 + cell $or $or$libresoc.v:187698$12393 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383617,39 +354996,39 @@ module \rst_l$70 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:186381$12409_Y + connect \Y $or$libresoc.v:187698$12393_Y end - attribute \src "libresoc.v:186340.7-186340.20" - process $proc$libresoc.v:186340$12415 + attribute \src "libresoc.v:187657.7-187657.20" + process $proc$libresoc.v:187657$12399 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:186362.7-186362.19" - process $proc$libresoc.v:186362$12416 + attribute \src "libresoc.v:187679.7-187679.19" + process $proc$libresoc.v:187679$12400 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:186383.3-186384.27" - process $proc$libresoc.v:186383$12411 + attribute \src "libresoc.v:187700.3-187701.27" + process $proc$libresoc.v:187700$12395 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:186385.3-186393.6" - process $proc$libresoc.v:186385$12412 + attribute \src "libresoc.v:187702.3-187710.6" + process $proc$libresoc.v:187702$12396 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12413 $1\q_int$next[0:0]$12414 - attribute \src "libresoc.v:186386.5-186386.29" + assign $0\q_int$next[0:0]$12397 $1\q_int$next[0:0]$12398 + attribute \src "libresoc.v:187703.5-187703.29" switch \initial - attribute \src "libresoc.v:186386.9-186386.17" + attribute \src "libresoc.v:187703.9-187703.17" case 1'1 case end @@ -383658,56 +355037,56 @@ module \rst_l$70 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12414 1'0 + assign $1\q_int$next[0:0]$12398 1'0 case - assign $1\q_int$next[0:0]$12414 \$5 + assign $1\q_int$next[0:0]$12398 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12413 + update \q_int$next $0\q_int$next[0:0]$12397 end - connect \$9 $and$libresoc.v:186375$12403_Y - connect \$11 $or$libresoc.v:186376$12404_Y - connect \$13 $not$libresoc.v:186377$12405_Y - connect \$15 $or$libresoc.v:186378$12406_Y - connect \$1 $not$libresoc.v:186379$12407_Y - connect \$3 $and$libresoc.v:186380$12408_Y - connect \$5 $or$libresoc.v:186381$12409_Y - connect \$7 $not$libresoc.v:186382$12410_Y + connect \$9 $and$libresoc.v:187692$12387_Y + connect \$11 $or$libresoc.v:187693$12388_Y + connect \$13 $not$libresoc.v:187694$12389_Y + connect \$15 $or$libresoc.v:187695$12390_Y + connect \$1 $not$libresoc.v:187696$12391_Y + connect \$3 $and$libresoc.v:187697$12392_Y + connect \$5 $or$libresoc.v:187698$12393_Y + connect \$7 $not$libresoc.v:187699$12394_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:186401.1-186459.10" +attribute \src "libresoc.v:187718.1-187776.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.rst_l" attribute \generator "nMigen" module \rst_l$87 - attribute \src "libresoc.v:186402.7-186402.20" + attribute \src "libresoc.v:187719.7-187719.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186447.3-186455.6" - wire $0\q_int$next[0:0]$12427 - attribute \src "libresoc.v:186445.3-186446.27" + attribute \src "libresoc.v:187764.3-187772.6" + wire $0\q_int$next[0:0]$12411 + attribute \src "libresoc.v:187762.3-187763.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:186447.3-186455.6" - wire $1\q_int$next[0:0]$12428 - attribute \src "libresoc.v:186424.7-186424.19" + attribute \src "libresoc.v:187764.3-187772.6" + wire $1\q_int$next[0:0]$12412 + attribute \src "libresoc.v:187741.7-187741.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:186437.17-186437.96" - wire $and$libresoc.v:186437$12417_Y - attribute \src "libresoc.v:186442.17-186442.96" - wire $and$libresoc.v:186442$12422_Y - attribute \src "libresoc.v:186439.18-186439.93" - wire $not$libresoc.v:186439$12419_Y - attribute \src "libresoc.v:186441.17-186441.92" - wire $not$libresoc.v:186441$12421_Y - attribute \src "libresoc.v:186444.17-186444.92" - wire $not$libresoc.v:186444$12424_Y - attribute \src "libresoc.v:186438.18-186438.98" - wire $or$libresoc.v:186438$12418_Y - attribute \src "libresoc.v:186440.18-186440.99" - wire $or$libresoc.v:186440$12420_Y - attribute \src "libresoc.v:186443.17-186443.97" - wire $or$libresoc.v:186443$12423_Y + attribute \src "libresoc.v:187754.17-187754.96" + wire $and$libresoc.v:187754$12401_Y + attribute \src "libresoc.v:187759.17-187759.96" + wire $and$libresoc.v:187759$12406_Y + attribute \src "libresoc.v:187756.18-187756.93" + wire $not$libresoc.v:187756$12403_Y + attribute \src "libresoc.v:187758.17-187758.92" + wire $not$libresoc.v:187758$12405_Y + attribute \src "libresoc.v:187761.17-187761.92" + wire $not$libresoc.v:187761$12408_Y + attribute \src "libresoc.v:187755.18-187755.98" + wire $or$libresoc.v:187755$12402_Y + attribute \src "libresoc.v:187757.18-187757.99" + wire $or$libresoc.v:187757$12404_Y + attribute \src "libresoc.v:187760.17-187760.97" + wire $or$libresoc.v:187760$12407_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -383724,11 +355103,11 @@ module \rst_l$87 wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 4 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:186402.7-186402.15" + attribute \src "libresoc.v:187719.7-187719.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -383745,7 +355124,7 @@ module \rst_l$87 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:186437$12417 + cell $and $and$libresoc.v:187754$12401 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383753,10 +355132,10 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:186437$12417_Y + connect \Y $and$libresoc.v:187754$12401_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:186442$12422 + cell $and $and$libresoc.v:187759$12406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383764,34 +355143,34 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:186442$12422_Y + connect \Y $and$libresoc.v:187759$12406_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:186439$12419 + cell $not $not$libresoc.v:187756$12403 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_rst - connect \Y $not$libresoc.v:186439$12419_Y + connect \Y $not$libresoc.v:187756$12403_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:186441$12421 + cell $not $not$libresoc.v:187758$12405 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186441$12421_Y + connect \Y $not$libresoc.v:187758$12405_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:186444$12424 + cell $not $not$libresoc.v:187761$12408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_rst - connect \Y $not$libresoc.v:186444$12424_Y + connect \Y $not$libresoc.v:187761$12408_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:186438$12418 + cell $or $or$libresoc.v:187755$12402 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383799,10 +355178,10 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_rst - connect \Y $or$libresoc.v:186438$12418_Y + connect \Y $or$libresoc.v:187755$12402_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:186440$12420 + cell $or $or$libresoc.v:187757$12404 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383810,10 +355189,10 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \q_rst connect \B \q_int - connect \Y $or$libresoc.v:186440$12420_Y + connect \Y $or$libresoc.v:187757$12404_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:186443$12423 + cell $or $or$libresoc.v:187760$12407 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -383821,39 +355200,39 @@ module \rst_l$87 parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_rst - connect \Y $or$libresoc.v:186443$12423_Y + connect \Y $or$libresoc.v:187760$12407_Y end - attribute \src "libresoc.v:186402.7-186402.20" - process $proc$libresoc.v:186402$12429 + attribute \src "libresoc.v:187719.7-187719.20" + process $proc$libresoc.v:187719$12413 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:186424.7-186424.19" - process $proc$libresoc.v:186424$12430 + attribute \src "libresoc.v:187741.7-187741.19" + process $proc$libresoc.v:187741$12414 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:186445.3-186446.27" - process $proc$libresoc.v:186445$12425 + attribute \src "libresoc.v:187762.3-187763.27" + process $proc$libresoc.v:187762$12409 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:186447.3-186455.6" - process $proc$libresoc.v:186447$12426 + attribute \src "libresoc.v:187764.3-187772.6" + process $proc$libresoc.v:187764$12410 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$12427 $1\q_int$next[0:0]$12428 - attribute \src "libresoc.v:186448.5-186448.29" + assign $0\q_int$next[0:0]$12411 $1\q_int$next[0:0]$12412 + attribute \src "libresoc.v:187765.5-187765.29" switch \initial - attribute \src "libresoc.v:186448.9-186448.17" + attribute \src "libresoc.v:187765.9-187765.17" case 1'1 case end @@ -383862,92 +355241,92 @@ module \rst_l$87 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$12428 1'0 + assign $1\q_int$next[0:0]$12412 1'0 case - assign $1\q_int$next[0:0]$12428 \$5 + assign $1\q_int$next[0:0]$12412 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$12427 + update \q_int$next $0\q_int$next[0:0]$12411 end - connect \$9 $and$libresoc.v:186437$12417_Y - connect \$11 $or$libresoc.v:186438$12418_Y - connect \$13 $not$libresoc.v:186439$12419_Y - connect \$15 $or$libresoc.v:186440$12420_Y - connect \$1 $not$libresoc.v:186441$12421_Y - connect \$3 $and$libresoc.v:186442$12422_Y - connect \$5 $or$libresoc.v:186443$12423_Y - connect \$7 $not$libresoc.v:186444$12424_Y + connect \$9 $and$libresoc.v:187754$12401_Y + connect \$11 $or$libresoc.v:187755$12402_Y + connect \$13 $not$libresoc.v:187756$12403_Y + connect \$15 $or$libresoc.v:187757$12404_Y + connect \$1 $not$libresoc.v:187758$12405_Y + connect \$3 $and$libresoc.v:187759$12406_Y + connect \$5 $or$libresoc.v:187760$12407_Y + connect \$7 $not$libresoc.v:187761$12408_Y connect \qlq_rst \$15 connect \qn_rst \$13 connect \q_rst \$11 end -attribute \src "libresoc.v:186463.1-186872.10" +attribute \src "libresoc.v:187780.1-188189.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.alu_div0.pipe_start.setup_stage" attribute \generator "nMigen" module \setup_stage - attribute \src "libresoc.v:186830.3-186855.6" + attribute \src "libresoc.v:188147.3-188172.6" wire width 128 $0\dividend[127:0] - attribute \src "libresoc.v:186464.7-186464.20" + attribute \src "libresoc.v:187781.7-187781.20" wire $0\initial[0:0] - attribute \src "libresoc.v:186830.3-186855.6" + attribute \src "libresoc.v:188147.3-188172.6" wire width 128 $1\dividend[127:0] - attribute \src "libresoc.v:186830.3-186855.6" + attribute \src "libresoc.v:188147.3-188172.6" wire width 128 $2\dividend[127:0] - attribute \src "libresoc.v:186809.18-186809.122" - wire $and$libresoc.v:186809$12432_Y - attribute \src "libresoc.v:186811.18-186811.122" - wire $and$libresoc.v:186811$12434_Y - attribute \src "libresoc.v:186820.18-186820.105" - wire $and$libresoc.v:186820$12447_Y - attribute \src "libresoc.v:186823.18-186823.105" - wire $and$libresoc.v:186823$12450_Y - attribute \src "libresoc.v:186819.18-186819.123" - wire $eq$libresoc.v:186819$12446_Y - attribute \src "libresoc.v:186822.18-186822.123" - wire $eq$libresoc.v:186822$12449_Y - attribute \src "libresoc.v:186825.18-186825.117" - wire $eq$libresoc.v:186825$12452_Y - attribute \src "libresoc.v:186812.18-186812.97" - wire width 65 $extend$libresoc.v:186812$12435_Y - attribute \src "libresoc.v:186813.18-186813.91" - wire width 65 $extend$libresoc.v:186813$12437_Y - attribute \src "libresoc.v:186815.18-186815.97" - wire width 65 $extend$libresoc.v:186815$12440_Y - attribute \src "libresoc.v:186816.18-186816.91" - wire width 65 $extend$libresoc.v:186816$12442_Y - attribute \src "libresoc.v:186828.18-186828.99" - wire width 128 $extend$libresoc.v:186828$12455_Y - attribute \src "libresoc.v:186818.18-186818.112" - wire $ge$libresoc.v:186818$12445_Y - attribute \src "libresoc.v:186821.18-186821.124" - wire $ge$libresoc.v:186821$12448_Y - attribute \src "libresoc.v:186812.18-186812.97" - wire width 65 $neg$libresoc.v:186812$12436_Y - attribute \src "libresoc.v:186815.18-186815.97" - wire width 65 $neg$libresoc.v:186815$12441_Y - attribute \src "libresoc.v:186813.18-186813.91" - wire width 65 $pos$libresoc.v:186813$12438_Y - attribute \src "libresoc.v:186816.18-186816.91" - wire width 65 $pos$libresoc.v:186816$12443_Y - attribute \src "libresoc.v:186828.18-186828.99" - wire width 128 $pos$libresoc.v:186828$12456_Y - attribute \src "libresoc.v:186827.18-186827.117" - wire width 95 $sshl$libresoc.v:186827$12454_Y - attribute \src "libresoc.v:186829.18-186829.111" - wire width 191 $sshl$libresoc.v:186829$12457_Y - attribute \src "libresoc.v:186808.18-186808.131" - wire $ternary$libresoc.v:186808$12431_Y - attribute \src "libresoc.v:186810.18-186810.131" - wire $ternary$libresoc.v:186810$12433_Y - attribute \src "libresoc.v:186814.18-186814.119" - wire width 65 $ternary$libresoc.v:186814$12439_Y - attribute \src "libresoc.v:186817.18-186817.120" - wire width 65 $ternary$libresoc.v:186817$12444_Y - attribute \src "libresoc.v:186824.18-186824.130" - wire width 32 $ternary$libresoc.v:186824$12451_Y - attribute \src "libresoc.v:186826.18-186826.131" - wire width 32 $ternary$libresoc.v:186826$12453_Y + attribute \src "libresoc.v:188126.18-188126.122" + wire $and$libresoc.v:188126$12416_Y + attribute \src "libresoc.v:188128.18-188128.122" + wire $and$libresoc.v:188128$12418_Y + attribute \src "libresoc.v:188137.18-188137.105" + wire $and$libresoc.v:188137$12431_Y + attribute \src "libresoc.v:188140.18-188140.105" + wire $and$libresoc.v:188140$12434_Y + attribute \src "libresoc.v:188136.18-188136.123" + wire $eq$libresoc.v:188136$12430_Y + attribute \src "libresoc.v:188139.18-188139.123" + wire $eq$libresoc.v:188139$12433_Y + attribute \src "libresoc.v:188142.18-188142.117" + wire $eq$libresoc.v:188142$12436_Y + attribute \src "libresoc.v:188129.18-188129.97" + wire width 65 $extend$libresoc.v:188129$12419_Y + attribute \src "libresoc.v:188130.18-188130.91" + wire width 65 $extend$libresoc.v:188130$12421_Y + attribute \src "libresoc.v:188132.18-188132.97" + wire width 65 $extend$libresoc.v:188132$12424_Y + attribute \src "libresoc.v:188133.18-188133.91" + wire width 65 $extend$libresoc.v:188133$12426_Y + attribute \src "libresoc.v:188145.18-188145.99" + wire width 128 $extend$libresoc.v:188145$12439_Y + attribute \src "libresoc.v:188135.18-188135.112" + wire $ge$libresoc.v:188135$12429_Y + attribute \src "libresoc.v:188138.18-188138.124" + wire $ge$libresoc.v:188138$12432_Y + attribute \src "libresoc.v:188129.18-188129.97" + wire width 65 $neg$libresoc.v:188129$12420_Y + attribute \src "libresoc.v:188132.18-188132.97" + wire width 65 $neg$libresoc.v:188132$12425_Y + attribute \src "libresoc.v:188130.18-188130.91" + wire width 65 $pos$libresoc.v:188130$12422_Y + attribute \src "libresoc.v:188133.18-188133.91" + wire width 65 $pos$libresoc.v:188133$12427_Y + attribute \src "libresoc.v:188145.18-188145.99" + wire width 128 $pos$libresoc.v:188145$12440_Y + attribute \src "libresoc.v:188144.18-188144.117" + wire width 95 $sshl$libresoc.v:188144$12438_Y + attribute \src "libresoc.v:188146.18-188146.111" + wire width 191 $sshl$libresoc.v:188146$12441_Y + attribute \src "libresoc.v:188125.18-188125.131" + wire $ternary$libresoc.v:188125$12415_Y + attribute \src "libresoc.v:188127.18-188127.131" + wire $ternary$libresoc.v:188127$12417_Y + attribute \src "libresoc.v:188131.18-188131.119" + wire width 65 $ternary$libresoc.v:188131$12423_Y + attribute \src "libresoc.v:188134.18-188134.120" + wire width 65 $ternary$libresoc.v:188134$12428_Y + attribute \src "libresoc.v:188141.18-188141.130" + wire width 32 $ternary$libresoc.v:188141$12435_Y + attribute \src "libresoc.v:188143.18-188143.131" + wire width 32 $ternary$libresoc.v:188143$12437_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" wire \$21 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" @@ -384016,7 +355395,7 @@ module \setup_stage wire output 42 \divisor_neg attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" wire width 64 output 48 \divisor_radicand - attribute \src "libresoc.v:186464.7-186464.15" + attribute \src "libresoc.v:187781.7-187781.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" wire width 4 input 17 \logical_op__data_len @@ -384293,7 +355672,7 @@ module \setup_stage attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" wire output 41 \xer_so$20 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" - cell $and $and$libresoc.v:186809$12432 + cell $and $and$libresoc.v:188126$12416 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -384301,10 +355680,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \$21 connect \B \logical_op__is_signed - connect \Y $and$libresoc.v:186809$12432_Y + connect \Y $and$libresoc.v:188126$12416_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" - cell $and $and$libresoc.v:186811$12434 + cell $and $and$libresoc.v:188128$12418 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -384312,10 +355691,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \$25 connect \B \logical_op__is_signed - connect \Y $and$libresoc.v:186811$12434_Y + connect \Y $and$libresoc.v:188128$12418_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" - cell $and $and$libresoc.v:186820$12447 + cell $and $and$libresoc.v:188137$12431 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -384323,10 +355702,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \$43 connect \B \$45 - connect \Y $and$libresoc.v:186820$12447_Y + connect \Y $and$libresoc.v:188137$12431_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" - cell $and $and$libresoc.v:186823$12450 + cell $and $and$libresoc.v:188140$12434 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -384334,10 +355713,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \$49 connect \B \$51 - connect \Y $and$libresoc.v:186823$12450_Y + connect \Y $and$libresoc.v:188140$12434_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" - cell $eq $eq$libresoc.v:186819$12446 + cell $eq $eq$libresoc.v:188136$12430 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -384345,10 +355724,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0011110 - connect \Y $eq$libresoc.v:186819$12446_Y + connect \Y $eq$libresoc.v:188136$12430_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" - cell $eq $eq$libresoc.v:186822$12449 + cell $eq $eq$libresoc.v:188139$12433 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -384356,10 +355735,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \logical_op__insn_type connect \B 7'0011110 - connect \Y $eq$libresoc.v:186822$12449_Y + connect \Y $eq$libresoc.v:188139$12433_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67" - cell $eq $eq$libresoc.v:186825$12452 + cell $eq $eq$libresoc.v:188142$12436 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -384367,50 +355746,50 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \divisor_radicand connect \B 1'0 - connect \Y $eq$libresoc.v:186825$12452_Y + connect \Y $eq$libresoc.v:188142$12436_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - cell $pos $extend$libresoc.v:186812$12435 + cell $pos $extend$libresoc.v:188129$12419 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \rb - connect \Y $extend$libresoc.v:186812$12435_Y + connect \Y $extend$libresoc.v:188129$12419_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:186813$12437 + cell $pos $extend$libresoc.v:188130$12421 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \rb - connect \Y $extend$libresoc.v:186813$12437_Y + connect \Y $extend$libresoc.v:188130$12421_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - cell $pos $extend$libresoc.v:186815$12440 + cell $pos $extend$libresoc.v:188132$12424 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \ra - connect \Y $extend$libresoc.v:186815$12440_Y + connect \Y $extend$libresoc.v:188132$12424_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $extend$libresoc.v:186816$12442 + cell $pos $extend$libresoc.v:188133$12426 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 65 connect \A \ra - connect \Y $extend$libresoc.v:186816$12442_Y + connect \Y $extend$libresoc.v:188133$12426_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - cell $pos $extend$libresoc.v:186828$12455 + cell $pos $extend$libresoc.v:188145$12439 parameter \A_SIGNED 0 parameter \A_WIDTH 95 parameter \Y_WIDTH 128 connect \A \$62 - connect \Y $extend$libresoc.v:186828$12455_Y + connect \Y $extend$libresoc.v:188145$12439_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" - cell $ge $ge$libresoc.v:186818$12445 + cell $ge $ge$libresoc.v:188135$12429 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -384418,10 +355797,10 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \abs_dend connect \B \abs_dor - connect \Y $ge$libresoc.v:186818$12445_Y + connect \Y $ge$libresoc.v:188135$12429_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60" - cell $ge $ge$libresoc.v:186821$12448 + cell $ge $ge$libresoc.v:188138$12432 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -384429,50 +355808,50 @@ module \setup_stage parameter \Y_WIDTH 1 connect \A \abs_dend [31:0] connect \B \abs_dor [31:0] - connect \Y $ge$libresoc.v:186821$12448_Y + connect \Y $ge$libresoc.v:188138$12432_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - cell $neg $neg$libresoc.v:186812$12436 + cell $neg $neg$libresoc.v:188129$12420 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:186812$12435_Y - connect \Y $neg$libresoc.v:186812$12436_Y + connect \A $extend$libresoc.v:188129$12419_Y + connect \Y $neg$libresoc.v:188129$12420_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - cell $neg $neg$libresoc.v:186815$12441 + cell $neg $neg$libresoc.v:188132$12425 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:186815$12440_Y - connect \Y $neg$libresoc.v:186815$12441_Y + connect \A $extend$libresoc.v:188132$12424_Y + connect \Y $neg$libresoc.v:188132$12425_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:186813$12438 + cell $pos $pos$libresoc.v:188130$12422 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:186813$12437_Y - connect \Y $pos$libresoc.v:186813$12438_Y + connect \A $extend$libresoc.v:188130$12421_Y + connect \Y $pos$libresoc.v:188130$12422_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $pos$libresoc.v:186816$12443 + cell $pos $pos$libresoc.v:188133$12427 parameter \A_SIGNED 0 parameter \A_WIDTH 65 parameter \Y_WIDTH 65 - connect \A $extend$libresoc.v:186816$12442_Y - connect \Y $pos$libresoc.v:186816$12443_Y + connect \A $extend$libresoc.v:188133$12426_Y + connect \Y $pos$libresoc.v:188133$12427_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - cell $pos $pos$libresoc.v:186828$12456 + cell $pos $pos$libresoc.v:188145$12440 parameter \A_SIGNED 0 parameter \A_WIDTH 128 parameter \Y_WIDTH 128 - connect \A $extend$libresoc.v:186828$12455_Y - connect \Y $pos$libresoc.v:186828$12456_Y + connect \A $extend$libresoc.v:188145$12439_Y + connect \Y $pos$libresoc.v:188145$12440_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - cell $sshl $sshl$libresoc.v:186827$12454 + cell $sshl $sshl$libresoc.v:188144$12438 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \B_SIGNED 0 @@ -384480,10 +355859,10 @@ module \setup_stage parameter \Y_WIDTH 95 connect \A \abs_dend [31:0] connect \B 6'100000 - connect \Y $sshl$libresoc.v:186827$12454_Y + connect \Y $sshl$libresoc.v:188144$12438_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" - cell $sshl $sshl$libresoc.v:186829$12457 + cell $sshl $sshl$libresoc.v:188146$12441 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -384491,72 +355870,72 @@ module \setup_stage parameter \Y_WIDTH 191 connect \A \abs_dend connect \B 7'1000000 - connect \Y $sshl$libresoc.v:186829$12457_Y + connect \Y $sshl$libresoc.v:188146$12441_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" - cell $mux $ternary$libresoc.v:186808$12431 + cell $mux $ternary$libresoc.v:188125$12415 parameter \WIDTH 1 connect \A \ra [63] connect \B \ra [31] connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:186808$12431_Y + connect \Y $ternary$libresoc.v:188125$12415_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" - cell $mux $ternary$libresoc.v:186810$12433 + cell $mux $ternary$libresoc.v:188127$12417 parameter \WIDTH 1 connect \A \rb [63] connect \B \rb [31] connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:186810$12433_Y + connect \Y $ternary$libresoc.v:188127$12417_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - cell $mux $ternary$libresoc.v:186814$12439 + cell $mux $ternary$libresoc.v:188131$12423 parameter \WIDTH 65 connect \A \$32 connect \B \$30 connect \S \divisor_neg - connect \Y $ternary$libresoc.v:186814$12439_Y + connect \Y $ternary$libresoc.v:188131$12423_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - cell $mux $ternary$libresoc.v:186817$12444 + cell $mux $ternary$libresoc.v:188134$12428 parameter \WIDTH 65 connect \A \$39 connect \B \$37 connect \S \dividend_neg - connect \Y $ternary$libresoc.v:186817$12444_Y + connect \Y $ternary$libresoc.v:188134$12428_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" - cell $mux $ternary$libresoc.v:186824$12451 + cell $mux $ternary$libresoc.v:188141$12435 parameter \WIDTH 32 connect \A \abs_dor [63:32] connect \B 0 connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:186824$12451_Y + connect \Y $ternary$libresoc.v:188141$12435_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:41" - cell $mux $ternary$libresoc.v:186826$12453 + cell $mux $ternary$libresoc.v:188143$12437 parameter \WIDTH 32 connect \A \abs_dend [63:32] connect \B 0 connect \S \logical_op__is_32bit - connect \Y $ternary$libresoc.v:186826$12453_Y + connect \Y $ternary$libresoc.v:188143$12437_Y end - attribute \src "libresoc.v:186464.7-186464.20" - process $proc$libresoc.v:186464$12459 + attribute \src "libresoc.v:187781.7-187781.20" + process $proc$libresoc.v:187781$12443 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:186830.3-186855.6" - process $proc$libresoc.v:186830$12458 + attribute \src "libresoc.v:188147.3-188172.6" + process $proc$libresoc.v:188147$12442 assign { } { } assign { } { } assign $0\dividend[127:0] $1\dividend[127:0] - attribute \src "libresoc.v:186831.5-186831.29" + attribute \src "libresoc.v:188148.5-188148.29" switch \initial - attribute \src "libresoc.v:186831.9-186831.17" + attribute \src "libresoc.v:188148.9-188148.17" case 1'1 case end @@ -384588,28 +355967,28 @@ module \setup_stage sync always update \dividend $0\dividend[127:0] end - connect \$21 $ternary$libresoc.v:186808$12431_Y - connect \$23 $and$libresoc.v:186809$12432_Y - connect \$25 $ternary$libresoc.v:186810$12433_Y - connect \$27 $and$libresoc.v:186811$12434_Y - connect \$30 $neg$libresoc.v:186812$12436_Y - connect \$32 $pos$libresoc.v:186813$12438_Y - connect \$34 $ternary$libresoc.v:186814$12439_Y - connect \$37 $neg$libresoc.v:186815$12441_Y - connect \$39 $pos$libresoc.v:186816$12443_Y - connect \$41 $ternary$libresoc.v:186817$12444_Y - connect \$43 $ge$libresoc.v:186818$12445_Y - connect \$45 $eq$libresoc.v:186819$12446_Y - connect \$47 $and$libresoc.v:186820$12447_Y - connect \$49 $ge$libresoc.v:186821$12448_Y - connect \$51 $eq$libresoc.v:186822$12449_Y - connect \$53 $and$libresoc.v:186823$12450_Y - connect \$55 $ternary$libresoc.v:186824$12451_Y - connect \$57 $eq$libresoc.v:186825$12452_Y - connect \$59 $ternary$libresoc.v:186826$12453_Y - connect \$62 $sshl$libresoc.v:186827$12454_Y - connect \$61 $pos$libresoc.v:186828$12456_Y - connect \$66 $sshl$libresoc.v:186829$12457_Y + connect \$21 $ternary$libresoc.v:188125$12415_Y + connect \$23 $and$libresoc.v:188126$12416_Y + connect \$25 $ternary$libresoc.v:188127$12417_Y + connect \$27 $and$libresoc.v:188128$12418_Y + connect \$30 $neg$libresoc.v:188129$12420_Y + connect \$32 $pos$libresoc.v:188130$12422_Y + connect \$34 $ternary$libresoc.v:188131$12423_Y + connect \$37 $neg$libresoc.v:188132$12425_Y + connect \$39 $pos$libresoc.v:188133$12427_Y + connect \$41 $ternary$libresoc.v:188134$12428_Y + connect \$43 $ge$libresoc.v:188135$12429_Y + connect \$45 $eq$libresoc.v:188136$12430_Y + connect \$47 $and$libresoc.v:188137$12431_Y + connect \$49 $ge$libresoc.v:188138$12432_Y + connect \$51 $eq$libresoc.v:188139$12433_Y + connect \$53 $and$libresoc.v:188140$12434_Y + connect \$55 $ternary$libresoc.v:188141$12435_Y + connect \$57 $eq$libresoc.v:188142$12436_Y + connect \$59 $ternary$libresoc.v:188143$12437_Y + connect \$62 $sshl$libresoc.v:188144$12438_Y + connect \$61 $pos$libresoc.v:188145$12440_Y + connect \$66 $sshl$libresoc.v:188146$12441_Y connect \$29 \$34 connect \$36 \$41 connect \$65 \$66 @@ -384627,513 +356006,513 @@ module \setup_stage connect \dividend_neg \$23 connect \operation 2'01 end -attribute \src "libresoc.v:186876.1-188083.10" +attribute \src "libresoc.v:188193.1-189400.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0" attribute \generator "nMigen" module \shiftrot0 - attribute \src "libresoc.v:187654.3-187655.25" + attribute \src "libresoc.v:188971.3-188972.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:187652.3-187653.46" + attribute \src "libresoc.v:188969.3-188970.46" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:188003.3-188011.6" - wire $0\alu_l_r_alu$next[0:0]$12677 - attribute \src "libresoc.v:187570.3-187571.39" + attribute \src "libresoc.v:189320.3-189328.6" + wire $0\alu_l_r_alu$next[0:0]$12661 + attribute \src "libresoc.v:188887.3-188888.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:187840.3-187877.6" - wire width 14 $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12594 - attribute \src "libresoc.v:187598.3-187599.75" + attribute \src "libresoc.v:189157.3-189194.6" + wire width 14 $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12578 + attribute \src "libresoc.v:188915.3-188916.75" wire width 14 $0\alu_shift_rot0_sr_op__fn_unit[13:0] - attribute \src "libresoc.v:187840.3-187877.6" - wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12595 - attribute \src "libresoc.v:187600.3-187601.89" + attribute \src "libresoc.v:189157.3-189194.6" + wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12579 + attribute \src "libresoc.v:188917.3-188918.89" wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:187840.3-187877.6" - wire $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12596 - attribute \src "libresoc.v:187602.3-187603.85" + attribute \src "libresoc.v:189157.3-189194.6" + wire $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12580 + attribute \src "libresoc.v:188919.3-188920.85" wire $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:187840.3-187877.6" - wire width 2 $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12597 - attribute \src "libresoc.v:187616.3-187617.83" + attribute \src "libresoc.v:189157.3-189194.6" + wire width 2 $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12581 + attribute \src "libresoc.v:188933.3-188934.83" wire width 2 $0\alu_shift_rot0_sr_op__input_carry[1:0] - attribute \src "libresoc.v:187840.3-187877.6" - wire $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12598 - attribute \src "libresoc.v:187620.3-187621.77" + attribute \src "libresoc.v:189157.3-189194.6" + wire $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12582 + attribute \src "libresoc.v:188937.3-188938.77" wire $0\alu_shift_rot0_sr_op__input_cr[0:0] - attribute \src "libresoc.v:187840.3-187877.6" - wire width 32 $0\alu_shift_rot0_sr_op__insn$next[31:0]$12599 - attribute \src "libresoc.v:187628.3-187629.69" + attribute \src "libresoc.v:189157.3-189194.6" + wire width 32 $0\alu_shift_rot0_sr_op__insn$next[31:0]$12583 + attribute \src "libresoc.v:188945.3-188946.69" wire width 32 $0\alu_shift_rot0_sr_op__insn[31:0] - attribute \src "libresoc.v:187840.3-187877.6" - wire width 7 $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12600 - attribute \src "libresoc.v:187596.3-187597.79" + attribute \src "libresoc.v:189157.3-189194.6" + wire width 7 $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12584 + attribute \src "libresoc.v:188913.3-188914.79" wire width 7 $0\alu_shift_rot0_sr_op__insn_type[6:0] - attribute \src "libresoc.v:187840.3-187877.6" - wire $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12601 - attribute \src "libresoc.v:187614.3-187615.79" + attribute \src "libresoc.v:189157.3-189194.6" + wire $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12585 + attribute \src "libresoc.v:188931.3-188932.79" wire $0\alu_shift_rot0_sr_op__invert_in[0:0] - attribute \src "libresoc.v:187840.3-187877.6" - wire $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12602 - attribute \src "libresoc.v:187624.3-187625.77" + attribute \src "libresoc.v:189157.3-189194.6" + wire $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12586 + attribute \src "libresoc.v:188941.3-188942.77" wire $0\alu_shift_rot0_sr_op__is_32bit[0:0] - attribute \src "libresoc.v:187840.3-187877.6" - wire $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12603 - attribute \src "libresoc.v:187626.3-187627.79" + attribute \src "libresoc.v:189157.3-189194.6" + wire $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12587 + attribute \src "libresoc.v:188943.3-188944.79" wire $0\alu_shift_rot0_sr_op__is_signed[0:0] - attribute \src "libresoc.v:187840.3-187877.6" - wire $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12604 - attribute \src "libresoc.v:187608.3-187609.73" + attribute \src "libresoc.v:189157.3-189194.6" + wire $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12588 + attribute \src "libresoc.v:188925.3-188926.73" wire $0\alu_shift_rot0_sr_op__oe__oe[0:0] - attribute \src "libresoc.v:187840.3-187877.6" - wire $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12605 - attribute \src "libresoc.v:187610.3-187611.73" + attribute \src "libresoc.v:189157.3-189194.6" + wire $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12589 + attribute \src "libresoc.v:188927.3-188928.73" wire $0\alu_shift_rot0_sr_op__oe__ok[0:0] - attribute \src "libresoc.v:187840.3-187877.6" - wire $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12606 - attribute \src "libresoc.v:187618.3-187619.85" + attribute \src "libresoc.v:189157.3-189194.6" + wire $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12590 + attribute \src "libresoc.v:188935.3-188936.85" wire $0\alu_shift_rot0_sr_op__output_carry[0:0] - attribute \src "libresoc.v:187840.3-187877.6" - wire $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12607 - attribute \src "libresoc.v:187622.3-187623.79" + attribute \src "libresoc.v:189157.3-189194.6" + wire $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12591 + attribute \src "libresoc.v:188939.3-188940.79" wire $0\alu_shift_rot0_sr_op__output_cr[0:0] - attribute \src "libresoc.v:187840.3-187877.6" - wire $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12608 - attribute \src "libresoc.v:187606.3-187607.73" + attribute \src "libresoc.v:189157.3-189194.6" + wire $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12592 + attribute \src "libresoc.v:188923.3-188924.73" wire $0\alu_shift_rot0_sr_op__rc__ok[0:0] - attribute \src "libresoc.v:187840.3-187877.6" - wire $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12609 - attribute \src "libresoc.v:187604.3-187605.73" + attribute \src "libresoc.v:189157.3-189194.6" + wire $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12593 + attribute \src "libresoc.v:188921.3-188922.73" wire $0\alu_shift_rot0_sr_op__rc__rc[0:0] - attribute \src "libresoc.v:187840.3-187877.6" - wire $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12610 - attribute \src "libresoc.v:187612.3-187613.79" + attribute \src "libresoc.v:189157.3-189194.6" + wire $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12594 + attribute \src "libresoc.v:188929.3-188930.79" wire $0\alu_shift_rot0_sr_op__write_cr0[0:0] - attribute \src "libresoc.v:187994.3-188002.6" - wire $0\alui_l_r_alui$next[0:0]$12674 - attribute \src "libresoc.v:187572.3-187573.43" + attribute \src "libresoc.v:189311.3-189319.6" + wire $0\alui_l_r_alui$next[0:0]$12658 + attribute \src "libresoc.v:188889.3-188890.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:187878.3-187899.6" - wire width 64 $0\data_r0__o$next[63:0]$12635 - attribute \src "libresoc.v:187592.3-187593.37" + attribute \src "libresoc.v:189195.3-189216.6" + wire width 64 $0\data_r0__o$next[63:0]$12619 + attribute \src "libresoc.v:188909.3-188910.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:187878.3-187899.6" - wire $0\data_r0__o_ok$next[0:0]$12636 - attribute \src "libresoc.v:187594.3-187595.43" + attribute \src "libresoc.v:189195.3-189216.6" + wire $0\data_r0__o_ok$next[0:0]$12620 + attribute \src "libresoc.v:188911.3-188912.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:187900.3-187921.6" - wire width 4 $0\data_r1__cr_a$next[3:0]$12643 - attribute \src "libresoc.v:187588.3-187589.43" + attribute \src "libresoc.v:189217.3-189238.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$12627 + attribute \src "libresoc.v:188905.3-188906.43" wire width 4 $0\data_r1__cr_a[3:0] - attribute \src "libresoc.v:187900.3-187921.6" - wire $0\data_r1__cr_a_ok$next[0:0]$12644 - attribute \src "libresoc.v:187590.3-187591.49" + attribute \src "libresoc.v:189217.3-189238.6" + wire $0\data_r1__cr_a_ok$next[0:0]$12628 + attribute \src "libresoc.v:188907.3-188908.49" wire $0\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:187922.3-187943.6" - wire width 2 $0\data_r2__xer_ca$next[1:0]$12651 - attribute \src "libresoc.v:187584.3-187585.47" + attribute \src "libresoc.v:189239.3-189260.6" + wire width 2 $0\data_r2__xer_ca$next[1:0]$12635 + attribute \src "libresoc.v:188901.3-188902.47" wire width 2 $0\data_r2__xer_ca[1:0] - attribute \src "libresoc.v:187922.3-187943.6" - wire $0\data_r2__xer_ca_ok$next[0:0]$12652 - attribute \src "libresoc.v:187586.3-187587.53" + attribute \src "libresoc.v:189239.3-189260.6" + wire $0\data_r2__xer_ca_ok$next[0:0]$12636 + attribute \src "libresoc.v:188903.3-188904.53" wire $0\data_r2__xer_ca_ok[0:0] - attribute \src "libresoc.v:188012.3-188021.6" + attribute \src "libresoc.v:189329.3-189338.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:188022.3-188031.6" + attribute \src "libresoc.v:189339.3-189348.6" wire width 4 $0\dest2_o[3:0] - attribute \src "libresoc.v:188032.3-188041.6" + attribute \src "libresoc.v:189349.3-189358.6" wire width 2 $0\dest3_o[1:0] - attribute \src "libresoc.v:186877.7-186877.20" + attribute \src "libresoc.v:188194.7-188194.20" wire $0\initial[0:0] - attribute \src "libresoc.v:187795.3-187803.6" - wire $0\opc_l_r_opc$next[0:0]$12579 - attribute \src "libresoc.v:187638.3-187639.39" + attribute \src "libresoc.v:189112.3-189120.6" + wire $0\opc_l_r_opc$next[0:0]$12563 + attribute \src "libresoc.v:188955.3-188956.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:187786.3-187794.6" - wire $0\opc_l_s_opc$next[0:0]$12576 - attribute \src "libresoc.v:187640.3-187641.39" + attribute \src "libresoc.v:189103.3-189111.6" + wire $0\opc_l_s_opc$next[0:0]$12560 + attribute \src "libresoc.v:188957.3-188958.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:188042.3-188050.6" - wire width 3 $0\prev_wr_go$next[2:0]$12683 - attribute \src "libresoc.v:187650.3-187651.37" + attribute \src "libresoc.v:189359.3-189367.6" + wire width 3 $0\prev_wr_go$next[2:0]$12667 + attribute \src "libresoc.v:188967.3-188968.37" wire width 3 $0\prev_wr_go[2:0] - attribute \src "libresoc.v:187740.3-187749.6" + attribute \src "libresoc.v:189057.3-189066.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:187831.3-187839.6" - wire width 3 $0\req_l_r_req$next[2:0]$12591 - attribute \src "libresoc.v:187630.3-187631.39" + attribute \src "libresoc.v:189148.3-189156.6" + wire width 3 $0\req_l_r_req$next[2:0]$12575 + attribute \src "libresoc.v:188947.3-188948.39" wire width 3 $0\req_l_r_req[2:0] - attribute \src "libresoc.v:187822.3-187830.6" - wire width 3 $0\req_l_s_req$next[2:0]$12588 - attribute \src "libresoc.v:187632.3-187633.39" + attribute \src "libresoc.v:189139.3-189147.6" + wire width 3 $0\req_l_s_req$next[2:0]$12572 + attribute \src "libresoc.v:188949.3-188950.39" wire width 3 $0\req_l_s_req[2:0] - attribute \src "libresoc.v:187759.3-187767.6" - wire $0\rok_l_r_rdok$next[0:0]$12567 - attribute \src "libresoc.v:187646.3-187647.41" + attribute \src "libresoc.v:189076.3-189084.6" + wire $0\rok_l_r_rdok$next[0:0]$12551 + attribute \src "libresoc.v:188963.3-188964.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:187750.3-187758.6" - wire $0\rok_l_s_rdok$next[0:0]$12564 - attribute \src "libresoc.v:187648.3-187649.41" + attribute \src "libresoc.v:189067.3-189075.6" + wire $0\rok_l_s_rdok$next[0:0]$12548 + attribute \src "libresoc.v:188965.3-188966.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:187777.3-187785.6" - wire $0\rst_l_r_rst$next[0:0]$12573 - attribute \src "libresoc.v:187642.3-187643.39" + attribute \src "libresoc.v:189094.3-189102.6" + wire $0\rst_l_r_rst$next[0:0]$12557 + attribute \src "libresoc.v:188959.3-188960.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:187768.3-187776.6" - wire $0\rst_l_s_rst$next[0:0]$12570 - attribute \src "libresoc.v:187644.3-187645.39" + attribute \src "libresoc.v:189085.3-189093.6" + wire $0\rst_l_s_rst$next[0:0]$12554 + attribute \src "libresoc.v:188961.3-188962.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:187813.3-187821.6" - wire width 5 $0\src_l_r_src$next[4:0]$12585 - attribute \src "libresoc.v:187634.3-187635.39" + attribute \src "libresoc.v:189130.3-189138.6" + wire width 5 $0\src_l_r_src$next[4:0]$12569 + attribute \src "libresoc.v:188951.3-188952.39" wire width 5 $0\src_l_r_src[4:0] - attribute \src "libresoc.v:187804.3-187812.6" - wire width 5 $0\src_l_s_src$next[4:0]$12582 - attribute \src "libresoc.v:187636.3-187637.39" + attribute \src "libresoc.v:189121.3-189129.6" + wire width 5 $0\src_l_s_src$next[4:0]$12566 + attribute \src "libresoc.v:188953.3-188954.39" wire width 5 $0\src_l_s_src[4:0] - attribute \src "libresoc.v:187944.3-187953.6" - wire width 64 $0\src_r0$next[63:0]$12659 - attribute \src "libresoc.v:187582.3-187583.29" + attribute \src "libresoc.v:189261.3-189270.6" + wire width 64 $0\src_r0$next[63:0]$12643 + attribute \src "libresoc.v:188899.3-188900.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:187954.3-187963.6" - wire width 64 $0\src_r1$next[63:0]$12662 - attribute \src "libresoc.v:187580.3-187581.29" + attribute \src "libresoc.v:189271.3-189280.6" + wire width 64 $0\src_r1$next[63:0]$12646 + attribute \src "libresoc.v:188897.3-188898.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:187964.3-187973.6" - wire width 64 $0\src_r2$next[63:0]$12665 - attribute \src "libresoc.v:187578.3-187579.29" + attribute \src "libresoc.v:189281.3-189290.6" + wire width 64 $0\src_r2$next[63:0]$12649 + attribute \src "libresoc.v:188895.3-188896.29" wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:187974.3-187983.6" - wire $0\src_r3$next[0:0]$12668 - attribute \src "libresoc.v:187576.3-187577.29" + attribute \src "libresoc.v:189291.3-189300.6" + wire $0\src_r3$next[0:0]$12652 + attribute \src "libresoc.v:188893.3-188894.29" wire $0\src_r3[0:0] - attribute \src "libresoc.v:187984.3-187993.6" - wire width 2 $0\src_r4$next[1:0]$12671 - attribute \src "libresoc.v:187574.3-187575.29" + attribute \src "libresoc.v:189301.3-189310.6" + wire width 2 $0\src_r4$next[1:0]$12655 + attribute \src "libresoc.v:188891.3-188892.29" wire width 2 $0\src_r4[1:0] - attribute \src "libresoc.v:186999.7-186999.24" + attribute \src "libresoc.v:188316.7-188316.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:187009.7-187009.26" + attribute \src "libresoc.v:188326.7-188326.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:188003.3-188011.6" - wire $1\alu_l_r_alu$next[0:0]$12678 - attribute \src "libresoc.v:187017.7-187017.25" + attribute \src "libresoc.v:189320.3-189328.6" + wire $1\alu_l_r_alu$next[0:0]$12662 + attribute \src "libresoc.v:188334.7-188334.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:187840.3-187877.6" - wire width 14 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12611 - attribute \src "libresoc.v:187060.14-187060.54" + attribute \src "libresoc.v:189157.3-189194.6" + wire width 14 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12595 + attribute \src "libresoc.v:188377.14-188377.54" wire width 14 $1\alu_shift_rot0_sr_op__fn_unit[13:0] - attribute \src "libresoc.v:187840.3-187877.6" - wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12612 - attribute \src "libresoc.v:187064.14-187064.73" + attribute \src "libresoc.v:189157.3-189194.6" + wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12596 + attribute \src "libresoc.v:188381.14-188381.73" wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data[63:0] - attribute \src "libresoc.v:187840.3-187877.6" - wire $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12613 - attribute \src "libresoc.v:187068.7-187068.48" + attribute \src "libresoc.v:189157.3-189194.6" + wire $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12597 + attribute \src "libresoc.v:188385.7-188385.48" wire $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] - attribute \src "libresoc.v:187840.3-187877.6" - wire width 2 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12614 - attribute \src "libresoc.v:187076.13-187076.53" + attribute \src "libresoc.v:189157.3-189194.6" + wire width 2 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12598 + attribute \src "libresoc.v:188393.13-188393.53" wire width 2 $1\alu_shift_rot0_sr_op__input_carry[1:0] - attribute \src "libresoc.v:187840.3-187877.6" - wire $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12615 - attribute \src "libresoc.v:187080.7-187080.44" + attribute \src "libresoc.v:189157.3-189194.6" + wire $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12599 + attribute \src "libresoc.v:188397.7-188397.44" wire $1\alu_shift_rot0_sr_op__input_cr[0:0] - attribute \src "libresoc.v:187840.3-187877.6" - wire width 32 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12616 - attribute \src "libresoc.v:187084.14-187084.48" + attribute \src "libresoc.v:189157.3-189194.6" + wire width 32 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12600 + attribute \src "libresoc.v:188401.14-188401.48" wire width 32 $1\alu_shift_rot0_sr_op__insn[31:0] - attribute \src "libresoc.v:187840.3-187877.6" - wire width 7 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12617 - attribute \src "libresoc.v:187163.13-187163.52" + attribute \src "libresoc.v:189157.3-189194.6" + wire width 7 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12601 + attribute \src "libresoc.v:188480.13-188480.52" wire width 7 $1\alu_shift_rot0_sr_op__insn_type[6:0] - attribute \src "libresoc.v:187840.3-187877.6" - wire $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12618 - attribute \src "libresoc.v:187167.7-187167.45" + attribute \src "libresoc.v:189157.3-189194.6" + wire $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12602 + attribute \src "libresoc.v:188484.7-188484.45" wire $1\alu_shift_rot0_sr_op__invert_in[0:0] - attribute \src "libresoc.v:187840.3-187877.6" - wire $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12619 - attribute \src "libresoc.v:187171.7-187171.44" + attribute \src "libresoc.v:189157.3-189194.6" + wire $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12603 + attribute \src "libresoc.v:188488.7-188488.44" wire $1\alu_shift_rot0_sr_op__is_32bit[0:0] - attribute \src "libresoc.v:187840.3-187877.6" - wire $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12620 - attribute \src "libresoc.v:187175.7-187175.45" + attribute \src "libresoc.v:189157.3-189194.6" + wire $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12604 + attribute \src "libresoc.v:188492.7-188492.45" wire $1\alu_shift_rot0_sr_op__is_signed[0:0] - attribute \src "libresoc.v:187840.3-187877.6" - wire $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12621 - attribute \src "libresoc.v:187179.7-187179.42" + attribute \src "libresoc.v:189157.3-189194.6" + wire $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12605 + attribute \src "libresoc.v:188496.7-188496.42" wire $1\alu_shift_rot0_sr_op__oe__oe[0:0] - attribute \src "libresoc.v:187840.3-187877.6" - wire $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12622 - attribute \src "libresoc.v:187183.7-187183.42" + attribute \src "libresoc.v:189157.3-189194.6" + wire $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12606 + attribute \src "libresoc.v:188500.7-188500.42" wire $1\alu_shift_rot0_sr_op__oe__ok[0:0] - attribute \src "libresoc.v:187840.3-187877.6" - wire $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12623 - attribute \src "libresoc.v:187187.7-187187.48" + attribute \src "libresoc.v:189157.3-189194.6" + wire $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12607 + attribute \src "libresoc.v:188504.7-188504.48" wire $1\alu_shift_rot0_sr_op__output_carry[0:0] - attribute \src "libresoc.v:187840.3-187877.6" - wire $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12624 - attribute \src "libresoc.v:187191.7-187191.45" + attribute \src "libresoc.v:189157.3-189194.6" + wire $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12608 + attribute \src "libresoc.v:188508.7-188508.45" wire $1\alu_shift_rot0_sr_op__output_cr[0:0] - attribute \src "libresoc.v:187840.3-187877.6" - wire $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12625 - attribute \src "libresoc.v:187195.7-187195.42" + attribute \src "libresoc.v:189157.3-189194.6" + wire $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12609 + attribute \src "libresoc.v:188512.7-188512.42" wire $1\alu_shift_rot0_sr_op__rc__ok[0:0] - attribute \src "libresoc.v:187840.3-187877.6" - wire $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12626 - attribute \src "libresoc.v:187199.7-187199.42" + attribute \src "libresoc.v:189157.3-189194.6" + wire $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12610 + attribute \src "libresoc.v:188516.7-188516.42" wire $1\alu_shift_rot0_sr_op__rc__rc[0:0] - attribute \src "libresoc.v:187840.3-187877.6" - wire $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12627 - attribute \src "libresoc.v:187203.7-187203.45" + attribute \src "libresoc.v:189157.3-189194.6" + wire $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12611 + attribute \src "libresoc.v:188520.7-188520.45" wire $1\alu_shift_rot0_sr_op__write_cr0[0:0] - attribute \src "libresoc.v:187994.3-188002.6" - wire $1\alui_l_r_alui$next[0:0]$12675 - attribute \src "libresoc.v:187215.7-187215.27" + attribute \src "libresoc.v:189311.3-189319.6" + wire $1\alui_l_r_alui$next[0:0]$12659 + attribute \src "libresoc.v:188532.7-188532.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:187878.3-187899.6" - wire width 64 $1\data_r0__o$next[63:0]$12637 - attribute \src "libresoc.v:187249.14-187249.47" + attribute \src "libresoc.v:189195.3-189216.6" + wire width 64 $1\data_r0__o$next[63:0]$12621 + attribute \src "libresoc.v:188566.14-188566.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:187878.3-187899.6" - wire $1\data_r0__o_ok$next[0:0]$12638 - attribute \src "libresoc.v:187253.7-187253.27" + attribute \src "libresoc.v:189195.3-189216.6" + wire $1\data_r0__o_ok$next[0:0]$12622 + attribute \src "libresoc.v:188570.7-188570.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:187900.3-187921.6" - wire width 4 $1\data_r1__cr_a$next[3:0]$12645 - attribute \src "libresoc.v:187257.13-187257.33" + attribute \src "libresoc.v:189217.3-189238.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$12629 + attribute \src "libresoc.v:188574.13-188574.33" wire width 4 $1\data_r1__cr_a[3:0] - attribute \src "libresoc.v:187900.3-187921.6" - wire $1\data_r1__cr_a_ok$next[0:0]$12646 - attribute \src "libresoc.v:187261.7-187261.30" + attribute \src "libresoc.v:189217.3-189238.6" + wire $1\data_r1__cr_a_ok$next[0:0]$12630 + attribute \src "libresoc.v:188578.7-188578.30" wire $1\data_r1__cr_a_ok[0:0] - attribute \src "libresoc.v:187922.3-187943.6" - wire width 2 $1\data_r2__xer_ca$next[1:0]$12653 - attribute \src "libresoc.v:187265.13-187265.35" + attribute \src "libresoc.v:189239.3-189260.6" + wire width 2 $1\data_r2__xer_ca$next[1:0]$12637 + attribute \src "libresoc.v:188582.13-188582.35" wire width 2 $1\data_r2__xer_ca[1:0] - attribute \src "libresoc.v:187922.3-187943.6" - wire $1\data_r2__xer_ca_ok$next[0:0]$12654 - attribute \src "libresoc.v:187269.7-187269.32" + attribute \src "libresoc.v:189239.3-189260.6" + wire $1\data_r2__xer_ca_ok$next[0:0]$12638 + attribute \src "libresoc.v:188586.7-188586.32" wire $1\data_r2__xer_ca_ok[0:0] - attribute \src "libresoc.v:188012.3-188021.6" + attribute \src "libresoc.v:189329.3-189338.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:188022.3-188031.6" + attribute \src "libresoc.v:189339.3-189348.6" wire width 4 $1\dest2_o[3:0] - attribute \src "libresoc.v:188032.3-188041.6" + attribute \src "libresoc.v:189349.3-189358.6" wire width 2 $1\dest3_o[1:0] - attribute \src "libresoc.v:187795.3-187803.6" - wire $1\opc_l_r_opc$next[0:0]$12580 - attribute \src "libresoc.v:187286.7-187286.25" + attribute \src "libresoc.v:189112.3-189120.6" + wire $1\opc_l_r_opc$next[0:0]$12564 + attribute \src "libresoc.v:188603.7-188603.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:187786.3-187794.6" - wire $1\opc_l_s_opc$next[0:0]$12577 - attribute \src "libresoc.v:187290.7-187290.25" + attribute \src "libresoc.v:189103.3-189111.6" + wire $1\opc_l_s_opc$next[0:0]$12561 + attribute \src "libresoc.v:188607.7-188607.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:188042.3-188050.6" - wire width 3 $1\prev_wr_go$next[2:0]$12684 - attribute \src "libresoc.v:187422.13-187422.30" + attribute \src "libresoc.v:189359.3-189367.6" + wire width 3 $1\prev_wr_go$next[2:0]$12668 + attribute \src "libresoc.v:188739.13-188739.30" wire width 3 $1\prev_wr_go[2:0] - attribute \src "libresoc.v:187740.3-187749.6" + attribute \src "libresoc.v:189057.3-189066.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:187831.3-187839.6" - wire width 3 $1\req_l_r_req$next[2:0]$12592 - attribute \src "libresoc.v:187430.13-187430.31" + attribute \src "libresoc.v:189148.3-189156.6" + wire width 3 $1\req_l_r_req$next[2:0]$12576 + attribute \src "libresoc.v:188747.13-188747.31" wire width 3 $1\req_l_r_req[2:0] - attribute \src "libresoc.v:187822.3-187830.6" - wire width 3 $1\req_l_s_req$next[2:0]$12589 - attribute \src "libresoc.v:187434.13-187434.31" + attribute \src "libresoc.v:189139.3-189147.6" + wire width 3 $1\req_l_s_req$next[2:0]$12573 + attribute \src "libresoc.v:188751.13-188751.31" wire width 3 $1\req_l_s_req[2:0] - attribute \src "libresoc.v:187759.3-187767.6" - wire $1\rok_l_r_rdok$next[0:0]$12568 - attribute \src "libresoc.v:187446.7-187446.26" + attribute \src "libresoc.v:189076.3-189084.6" + wire $1\rok_l_r_rdok$next[0:0]$12552 + attribute \src "libresoc.v:188763.7-188763.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:187750.3-187758.6" - wire $1\rok_l_s_rdok$next[0:0]$12565 - attribute \src "libresoc.v:187450.7-187450.26" + attribute \src "libresoc.v:189067.3-189075.6" + wire $1\rok_l_s_rdok$next[0:0]$12549 + attribute \src "libresoc.v:188767.7-188767.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:187777.3-187785.6" - wire $1\rst_l_r_rst$next[0:0]$12574 - attribute \src "libresoc.v:187454.7-187454.25" + attribute \src "libresoc.v:189094.3-189102.6" + wire $1\rst_l_r_rst$next[0:0]$12558 + attribute \src "libresoc.v:188771.7-188771.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:187768.3-187776.6" - wire $1\rst_l_s_rst$next[0:0]$12571 - attribute \src "libresoc.v:187458.7-187458.25" + attribute \src "libresoc.v:189085.3-189093.6" + wire $1\rst_l_s_rst$next[0:0]$12555 + attribute \src "libresoc.v:188775.7-188775.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:187813.3-187821.6" - wire width 5 $1\src_l_r_src$next[4:0]$12586 - attribute \src "libresoc.v:187476.13-187476.32" + attribute \src "libresoc.v:189130.3-189138.6" + wire width 5 $1\src_l_r_src$next[4:0]$12570 + attribute \src "libresoc.v:188793.13-188793.32" wire width 5 $1\src_l_r_src[4:0] - attribute \src "libresoc.v:187804.3-187812.6" - wire width 5 $1\src_l_s_src$next[4:0]$12583 - attribute \src "libresoc.v:187480.13-187480.32" + attribute \src "libresoc.v:189121.3-189129.6" + wire width 5 $1\src_l_s_src$next[4:0]$12567 + attribute \src "libresoc.v:188797.13-188797.32" wire width 5 $1\src_l_s_src[4:0] - attribute \src "libresoc.v:187944.3-187953.6" - wire width 64 $1\src_r0$next[63:0]$12660 - attribute \src "libresoc.v:187486.14-187486.43" + attribute \src "libresoc.v:189261.3-189270.6" + wire width 64 $1\src_r0$next[63:0]$12644 + attribute \src "libresoc.v:188803.14-188803.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:187954.3-187963.6" - wire width 64 $1\src_r1$next[63:0]$12663 - attribute \src "libresoc.v:187490.14-187490.43" + attribute \src "libresoc.v:189271.3-189280.6" + wire width 64 $1\src_r1$next[63:0]$12647 + attribute \src "libresoc.v:188807.14-188807.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:187964.3-187973.6" - wire width 64 $1\src_r2$next[63:0]$12666 - attribute \src "libresoc.v:187494.14-187494.43" + attribute \src "libresoc.v:189281.3-189290.6" + wire width 64 $1\src_r2$next[63:0]$12650 + attribute \src "libresoc.v:188811.14-188811.43" wire width 64 $1\src_r2[63:0] - attribute \src "libresoc.v:187974.3-187983.6" - wire $1\src_r3$next[0:0]$12669 - attribute \src "libresoc.v:187498.7-187498.20" + attribute \src "libresoc.v:189291.3-189300.6" + wire $1\src_r3$next[0:0]$12653 + attribute \src "libresoc.v:188815.7-188815.20" wire $1\src_r3[0:0] - attribute \src "libresoc.v:187984.3-187993.6" - wire width 2 $1\src_r4$next[1:0]$12672 - attribute \src "libresoc.v:187502.13-187502.26" + attribute \src "libresoc.v:189301.3-189310.6" + wire width 2 $1\src_r4$next[1:0]$12656 + attribute \src "libresoc.v:188819.13-188819.26" wire width 2 $1\src_r4[1:0] - attribute \src "libresoc.v:187840.3-187877.6" - wire width 64 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12628 - attribute \src "libresoc.v:187840.3-187877.6" - wire $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12629 - attribute \src "libresoc.v:187840.3-187877.6" - wire $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12630 - attribute \src "libresoc.v:187840.3-187877.6" - wire $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12631 - attribute \src "libresoc.v:187840.3-187877.6" - wire $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12632 - attribute \src "libresoc.v:187840.3-187877.6" - wire $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12633 - attribute \src "libresoc.v:187878.3-187899.6" - wire width 64 $2\data_r0__o$next[63:0]$12639 - attribute \src "libresoc.v:187878.3-187899.6" - wire $2\data_r0__o_ok$next[0:0]$12640 - attribute \src "libresoc.v:187900.3-187921.6" - wire width 4 $2\data_r1__cr_a$next[3:0]$12647 - attribute \src "libresoc.v:187900.3-187921.6" - wire $2\data_r1__cr_a_ok$next[0:0]$12648 - attribute \src "libresoc.v:187922.3-187943.6" - wire width 2 $2\data_r2__xer_ca$next[1:0]$12655 - attribute \src "libresoc.v:187922.3-187943.6" - wire $2\data_r2__xer_ca_ok$next[0:0]$12656 - attribute \src "libresoc.v:187878.3-187899.6" - wire $3\data_r0__o_ok$next[0:0]$12641 - attribute \src "libresoc.v:187900.3-187921.6" - wire $3\data_r1__cr_a_ok$next[0:0]$12649 - attribute \src "libresoc.v:187922.3-187943.6" - wire $3\data_r2__xer_ca_ok$next[0:0]$12657 - attribute \src "libresoc.v:187512.19-187512.114" - wire width 5 $and$libresoc.v:187512$12461_Y - attribute \src "libresoc.v:187513.19-187513.125" - wire $and$libresoc.v:187513$12462_Y - attribute \src "libresoc.v:187514.19-187514.125" - wire $and$libresoc.v:187514$12463_Y - attribute \src "libresoc.v:187515.19-187515.125" - wire $and$libresoc.v:187515$12464_Y - attribute \src "libresoc.v:187516.18-187516.110" - wire $and$libresoc.v:187516$12465_Y - attribute \src "libresoc.v:187517.19-187517.141" - wire width 3 $and$libresoc.v:187517$12466_Y - attribute \src "libresoc.v:187518.19-187518.121" - wire width 3 $and$libresoc.v:187518$12467_Y - attribute \src "libresoc.v:187519.19-187519.127" - wire $and$libresoc.v:187519$12468_Y - attribute \src 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"libresoc.v:189157.3-189194.6" + wire $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12614 + attribute \src "libresoc.v:189157.3-189194.6" + wire $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12615 + attribute \src "libresoc.v:189157.3-189194.6" + wire $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12616 + attribute \src "libresoc.v:189157.3-189194.6" + wire $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12617 + attribute \src "libresoc.v:189195.3-189216.6" + wire width 64 $2\data_r0__o$next[63:0]$12623 + attribute \src "libresoc.v:189195.3-189216.6" + wire $2\data_r0__o_ok$next[0:0]$12624 + attribute \src "libresoc.v:189217.3-189238.6" + wire width 4 $2\data_r1__cr_a$next[3:0]$12631 + attribute \src "libresoc.v:189217.3-189238.6" + wire $2\data_r1__cr_a_ok$next[0:0]$12632 + attribute \src "libresoc.v:189239.3-189260.6" + wire width 2 $2\data_r2__xer_ca$next[1:0]$12639 + attribute \src "libresoc.v:189239.3-189260.6" + wire $2\data_r2__xer_ca_ok$next[0:0]$12640 + attribute \src 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+ attribute \src "libresoc.v:188859.18-188859.132" + wire $and$libresoc.v:188859$12475_Y + attribute \src "libresoc.v:188860.18-188860.132" + wire $and$libresoc.v:188860$12476_Y + attribute \src "libresoc.v:188861.18-188861.117" + wire $and$libresoc.v:188861$12477_Y + attribute \src "libresoc.v:188867.18-188867.136" + wire $and$libresoc.v:188867$12483_Y + attribute \src "libresoc.v:188868.18-188868.124" + wire width 3 $and$libresoc.v:188868$12484_Y + attribute \src "libresoc.v:188870.18-188870.116" + wire $and$libresoc.v:188870$12486_Y + attribute \src "libresoc.v:188871.18-188871.119" + wire $and$libresoc.v:188871$12487_Y + attribute \src "libresoc.v:188872.18-188872.121" + wire $and$libresoc.v:188872$12488_Y + attribute \src "libresoc.v:188882.18-188882.140" + wire $and$libresoc.v:188882$12498_Y + attribute \src "libresoc.v:188883.18-188883.138" + wire $and$libresoc.v:188883$12499_Y + attribute \src "libresoc.v:188884.18-188884.171" + wire width 5 $and$libresoc.v:188884$12500_Y + attribute \src "libresoc.v:188886.18-188886.129" + wire width 5 $and$libresoc.v:188886$12502_Y + attribute \src "libresoc.v:188856.18-188856.113" + wire $eq$libresoc.v:188856$12472_Y + attribute \src "libresoc.v:188858.18-188858.119" + wire $eq$libresoc.v:188858$12474_Y + attribute \src "libresoc.v:188828.19-188828.115" + wire width 5 $not$libresoc.v:188828$12444_Y + attribute \src "libresoc.v:188839.18-188839.97" + wire $not$libresoc.v:188839$12455_Y + attribute \src "libresoc.v:188841.18-188841.99" + wire $not$libresoc.v:188841$12457_Y + attribute \src "libresoc.v:188844.18-188844.113" + wire width 3 $not$libresoc.v:188844$12460_Y + attribute \src "libresoc.v:188847.18-188847.106" + wire $not$libresoc.v:188847$12463_Y + attribute \src "libresoc.v:188853.18-188853.126" + wire $not$libresoc.v:188853$12469_Y + attribute \src "libresoc.v:188864.17-188864.113" + wire width 5 $not$libresoc.v:188864$12480_Y + attribute \src "libresoc.v:188885.18-188885.136" + wire $not$libresoc.v:188885$12501_Y + attribute \src "libresoc.v:188852.18-188852.112" + wire $or$libresoc.v:188852$12468_Y + attribute \src "libresoc.v:188862.18-188862.122" + wire $or$libresoc.v:188862$12478_Y + attribute \src "libresoc.v:188863.18-188863.124" + wire $or$libresoc.v:188863$12479_Y + attribute \src "libresoc.v:188865.18-188865.155" + wire width 3 $or$libresoc.v:188865$12481_Y + attribute \src "libresoc.v:188866.18-188866.181" + wire width 5 $or$libresoc.v:188866$12482_Y + attribute \src "libresoc.v:188869.18-188869.120" + wire width 3 $or$libresoc.v:188869$12485_Y + attribute \src "libresoc.v:188875.17-188875.117" + wire width 5 $or$libresoc.v:188875$12491_Y + attribute \src "libresoc.v:188881.17-188881.104" + wire $reduce_and$libresoc.v:188881$12497_Y + attribute \src "libresoc.v:188846.18-188846.106" + wire $reduce_or$libresoc.v:188846$12462_Y + attribute \src "libresoc.v:188850.18-188850.113" + wire $reduce_or$libresoc.v:188850$12466_Y + attribute \src "libresoc.v:188851.18-188851.112" + wire $reduce_or$libresoc.v:188851$12467_Y + attribute \src "libresoc.v:188873.18-188873.165" + wire $ternary$libresoc.v:188873$12489_Y + attribute \src "libresoc.v:188874.18-188874.182" + wire width 64 $ternary$libresoc.v:188874$12490_Y + attribute \src "libresoc.v:188876.18-188876.118" + wire width 64 $ternary$libresoc.v:188876$12492_Y + attribute \src "libresoc.v:188877.18-188877.115" + wire width 64 $ternary$libresoc.v:188877$12493_Y + attribute \src "libresoc.v:188878.18-188878.118" + wire width 64 $ternary$libresoc.v:188878$12494_Y + attribute \src "libresoc.v:188879.18-188879.118" + wire $ternary$libresoc.v:188879$12495_Y + attribute \src "libresoc.v:188880.18-188880.118" + wire width 2 $ternary$libresoc.v:188880$12496_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" wire \$10 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -385476,9 +356855,9 @@ module \shiftrot0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 37 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 33 \cr_a_ok @@ -385534,7 +356913,7 @@ module \shiftrot0 wire width 4 output 34 \dest2_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" wire width 2 output 36 \dest3_o - attribute \src "libresoc.v:186877.7-186877.15" + attribute \src "libresoc.v:188194.7-188194.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 29 \o_ok @@ -385767,7 +357146,7 @@ module \shiftrot0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 35 \xer_ca_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:187512$12461 + cell $and $and$libresoc.v:188829$12445 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -385775,10 +357154,10 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \$98 connect \B \$100 - connect \Y $and$libresoc.v:187512$12461_Y + connect \Y $and$libresoc.v:188829$12445_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:187513$12462 + cell $and $and$libresoc.v:188830$12446 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385786,10 +357165,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:187513$12462_Y + connect \Y $and$libresoc.v:188830$12446_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:187514$12463 + cell $and $and$libresoc.v:188831$12447 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385797,10 +357176,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:187514$12463_Y + connect \Y $and$libresoc.v:188831$12447_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:187515$12464 + cell $and $and$libresoc.v:188832$12448 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385808,10 +357187,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:187515$12464_Y + connect \Y $and$libresoc.v:188832$12448_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:187516$12465 + cell $and $and$libresoc.v:188833$12449 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385819,10 +357198,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$2 connect \B \$4 - connect \Y $and$libresoc.v:187516$12465_Y + connect \Y $and$libresoc.v:188833$12449_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:187517$12466 + cell $and $and$libresoc.v:188834$12450 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -385830,10 +357209,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B { \$104 \$106 \$108 } - connect \Y $and$libresoc.v:187517$12466_Y + connect \Y $and$libresoc.v:188834$12450_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:187518$12467 + cell $and $and$libresoc.v:188835$12451 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -385841,10 +357220,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \$110 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:187518$12467_Y + connect \Y $and$libresoc.v:188835$12451_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:187519$12468 + cell $and $and$libresoc.v:188836$12452 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385852,10 +357231,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:187519$12468_Y + connect \Y $and$libresoc.v:188836$12452_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:187520$12469 + cell $and $and$libresoc.v:188837$12453 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385863,10 +357242,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:187520$12469_Y + connect \Y $and$libresoc.v:188837$12453_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:187521$12470 + cell $and $and$libresoc.v:188838$12454 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385874,10 +357253,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:187521$12470_Y + connect \Y $and$libresoc.v:188838$12454_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:187523$12472 + cell $and $and$libresoc.v:188840$12456 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385885,10 +357264,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$12 - connect \Y $and$libresoc.v:187523$12472_Y + connect \Y $and$libresoc.v:188840$12456_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:187525$12474 + cell $and $and$libresoc.v:188842$12458 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385896,10 +357275,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$16 - connect \Y $and$libresoc.v:187525$12474_Y + connect \Y $and$libresoc.v:188842$12458_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:187526$12475 + cell $and $and$libresoc.v:188843$12459 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -385907,10 +357286,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:187526$12475_Y + connect \Y $and$libresoc.v:188843$12459_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:187528$12477 + cell $and $and$libresoc.v:188845$12461 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -385918,10 +357297,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \cu_wr__rel_o connect \B \$24 - connect \Y $and$libresoc.v:187528$12477_Y + connect \Y $and$libresoc.v:188845$12461_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:187531$12480 + cell $and $and$libresoc.v:188848$12464 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385929,10 +357308,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:187531$12480_Y + connect \Y $and$libresoc.v:188848$12464_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:187532$12481 + cell $and $and$libresoc.v:188849$12465 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385940,10 +357319,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$22 - connect \Y $and$libresoc.v:187532$12481_Y + connect \Y $and$libresoc.v:188849$12465_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:187537$12486 + cell $and $and$libresoc.v:188854$12470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385951,10 +357330,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$38 - connect \Y $and$libresoc.v:187537$12486_Y + connect \Y $and$libresoc.v:188854$12470_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:187538$12487 + cell $and $and$libresoc.v:188855$12471 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -385962,10 +357341,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:187538$12487_Y + connect \Y $and$libresoc.v:188855$12471_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:187540$12489 + cell $and $and$libresoc.v:188857$12473 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385973,10 +357352,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$40 connect \B \$44 - connect \Y $and$libresoc.v:187540$12489_Y + connect \Y $and$libresoc.v:188857$12473_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:187542$12491 + cell $and $and$libresoc.v:188859$12475 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385984,10 +357363,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$48 connect \B \alu_shift_rot0_n_ready_i - connect \Y $and$libresoc.v:187542$12491_Y + connect \Y $and$libresoc.v:188859$12475_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:187543$12492 + cell $and $and$libresoc.v:188860$12476 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -385995,10 +357374,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$50 connect \B \alu_shift_rot0_n_valid_o - connect \Y $and$libresoc.v:187543$12492_Y + connect \Y $and$libresoc.v:188860$12476_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:187544$12493 + cell $and $and$libresoc.v:188861$12477 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386006,10 +357385,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$52 connect \B \cu_busy_o - connect \Y $and$libresoc.v:187544$12493_Y + connect \Y $and$libresoc.v:188861$12477_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:187550$12499 + cell $and $and$libresoc.v:188867$12483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386017,10 +357396,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:187550$12499_Y + connect \Y $and$libresoc.v:188867$12483_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:187551$12500 + cell $and $and$libresoc.v:188868$12484 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -386028,10 +357407,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:187551$12500_Y + connect \Y $and$libresoc.v:188868$12484_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:187553$12502 + cell $and $and$libresoc.v:188870$12486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386039,10 +357418,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:187553$12502_Y + connect \Y $and$libresoc.v:188870$12486_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:187554$12503 + cell $and $and$libresoc.v:188871$12487 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386050,10 +357429,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cr_a_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:187554$12503_Y + connect \Y $and$libresoc.v:188871$12487_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:187555$12504 + cell $and $and$libresoc.v:188872$12488 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386061,10 +357440,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \xer_ca_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:187555$12504_Y + connect \Y $and$libresoc.v:188872$12488_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:187565$12514 + cell $and $and$libresoc.v:188882$12498 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386072,10 +357451,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:187565$12514_Y + connect \Y $and$libresoc.v:188882$12498_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:187566$12515 + cell $and $and$libresoc.v:188883$12499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386083,10 +357462,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:187566$12515_Y + connect \Y $and$libresoc.v:188883$12499_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:187567$12516 + cell $and $and$libresoc.v:188884$12500 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -386094,10 +357473,10 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:187567$12516_Y + connect \Y $and$libresoc.v:188884$12500_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:187569$12518 + cell $and $and$libresoc.v:188886$12502 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -386105,10 +357484,10 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \$94 connect \B { 3'111 \$96 1'1 } - connect \Y $and$libresoc.v:187569$12518_Y + connect \Y $and$libresoc.v:188886$12502_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:187539$12488 + cell $eq $eq$libresoc.v:188856$12472 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -386116,10 +357495,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$42 connect \B 1'0 - connect \Y $eq$libresoc.v:187539$12488_Y + connect \Y $eq$libresoc.v:188856$12472_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:187541$12490 + cell $eq $eq$libresoc.v:188858$12474 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -386127,74 +357506,74 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:187541$12490_Y + connect \Y $eq$libresoc.v:188858$12474_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:187511$12460 + cell $not $not$libresoc.v:188828$12444 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:187511$12460_Y + connect \Y $not$libresoc.v:188828$12444_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:187522$12471 + cell $not $not$libresoc.v:188839$12455 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:187522$12471_Y + connect \Y $not$libresoc.v:188839$12455_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:187524$12473 + cell $not $not$libresoc.v:188841$12457 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:187524$12473_Y + connect \Y $not$libresoc.v:188841$12457_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:187527$12476 + cell $not $not$libresoc.v:188844$12460 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:187527$12476_Y + connect \Y $not$libresoc.v:188844$12460_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:187530$12479 + cell $not $not$libresoc.v:188847$12463 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$23 - connect \Y $not$libresoc.v:187530$12479_Y + connect \Y $not$libresoc.v:188847$12463_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:187536$12485 + cell $not $not$libresoc.v:188853$12469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_n_ready_i - connect \Y $not$libresoc.v:187536$12485_Y + connect \Y $not$libresoc.v:188853$12469_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:187547$12496 + cell $not $not$libresoc.v:188864$12480 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:187547$12496_Y + connect \Y $not$libresoc.v:188864$12480_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $not$libresoc.v:187568$12517 + cell $not $not$libresoc.v:188885$12501 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_shift_rot0_sr_op__imm_data__ok - connect \Y $not$libresoc.v:187568$12517_Y + connect \Y $not$libresoc.v:188885$12501_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:187535$12484 + cell $or $or$libresoc.v:188852$12468 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386202,10 +357581,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \$32 connect \B \$34 - connect \Y $or$libresoc.v:187535$12484_Y + connect \Y $or$libresoc.v:188852$12468_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:187545$12494 + cell $or $or$libresoc.v:188862$12478 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386213,10 +357592,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:187545$12494_Y + connect \Y $or$libresoc.v:188862$12478_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:187546$12495 + cell $or $or$libresoc.v:188863$12479 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -386224,10 +357603,10 @@ module \shiftrot0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:187546$12495_Y + connect \Y $or$libresoc.v:188863$12479_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:187548$12497 + cell $or $or$libresoc.v:188865$12481 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -386235,10 +357614,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:187548$12497_Y + connect \Y $or$libresoc.v:188865$12481_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:187549$12498 + cell $or $or$libresoc.v:188866$12482 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -386246,10 +357625,10 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:187549$12498_Y + connect \Y $or$libresoc.v:188866$12482_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:187552$12501 + cell $or $or$libresoc.v:188869$12485 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -386257,10 +357636,10 @@ module \shiftrot0 parameter \Y_WIDTH 3 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:187552$12501_Y + connect \Y $or$libresoc.v:188869$12485_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:187558$12507 + cell $or $or$libresoc.v:188875$12491 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -386268,98 +357647,98 @@ module \shiftrot0 parameter \Y_WIDTH 5 connect \A \$5 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:187558$12507_Y + connect \Y $or$libresoc.v:188875$12491_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:187564$12513 + cell $reduce_and $reduce_and$libresoc.v:188881$12497 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \$7 - connect \Y $reduce_and$libresoc.v:187564$12513_Y + connect \Y $reduce_and$libresoc.v:188881$12497_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:187529$12478 + cell $reduce_or $reduce_or$libresoc.v:188846$12462 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$26 - connect \Y $reduce_or$libresoc.v:187529$12478_Y + connect \Y $reduce_or$libresoc.v:188846$12462_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:187533$12482 + cell $reduce_or $reduce_or$libresoc.v:188850$12466 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:187533$12482_Y + connect \Y $reduce_or$libresoc.v:188850$12466_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:187534$12483 + cell $reduce_or $reduce_or$libresoc.v:188851$12467 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:187534$12483_Y + connect \Y $reduce_or$libresoc.v:188851$12467_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $ternary$libresoc.v:187556$12505 + cell $mux $ternary$libresoc.v:188873$12489 parameter \WIDTH 1 connect \A \src_l_q_src [1] connect \B \opc_l_q_opc connect \S \alu_shift_rot0_sr_op__imm_data__ok - connect \Y $ternary$libresoc.v:187556$12505_Y + connect \Y $ternary$libresoc.v:188873$12489_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $ternary$libresoc.v:187557$12506 + cell $mux $ternary$libresoc.v:188874$12490 parameter \WIDTH 64 connect \A \src2_i connect \B \alu_shift_rot0_sr_op__imm_data__data connect \S \alu_shift_rot0_sr_op__imm_data__ok - connect \Y $ternary$libresoc.v:187557$12506_Y + connect \Y $ternary$libresoc.v:188874$12490_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:187559$12508 + cell $mux $ternary$libresoc.v:188876$12492 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:187559$12508_Y + connect \Y $ternary$libresoc.v:188876$12492_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:187560$12509 + cell $mux $ternary$libresoc.v:188877$12493 parameter \WIDTH 64 connect \A \src_r1 connect \B \src_or_imm connect \S \src_sel - connect \Y $ternary$libresoc.v:187560$12509_Y + connect \Y $ternary$libresoc.v:188877$12493_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:187561$12510 + cell $mux $ternary$libresoc.v:188878$12494 parameter \WIDTH 64 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:187561$12510_Y + connect \Y $ternary$libresoc.v:188878$12494_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:187562$12511 + cell $mux $ternary$libresoc.v:188879$12495 parameter \WIDTH 1 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:187562$12511_Y + connect \Y $ternary$libresoc.v:188879$12495_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:187563$12512 + cell $mux $ternary$libresoc.v:188880$12496 parameter \WIDTH 2 connect \A \src_r4 connect \B \src5_i connect \S \src_l_q_src [4] - connect \Y $ternary$libresoc.v:187563$12512_Y + connect \Y $ternary$libresoc.v:188880$12496_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:187656.15-187662.4" + attribute \src "libresoc.v:188973.15-188979.4" cell \alu_l$125 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -386368,7 +357747,7 @@ module \shiftrot0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:187663.18-187698.4" + attribute \src "libresoc.v:188980.18-189015.4" cell \alu_shift_rot0 \alu_shift_rot0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -386406,7 +357785,7 @@ module \shiftrot0 connect \xer_so \alu_shift_rot0_xer_so end attribute \module_not_derived 1 - attribute \src "libresoc.v:187699.16-187705.4" + attribute \src "libresoc.v:189016.16-189022.4" cell \alui_l$124 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -386415,7 +357794,7 @@ module \shiftrot0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:187706.15-187712.4" + attribute \src "libresoc.v:189023.15-189029.4" cell \opc_l$120 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -386424,7 +357803,7 @@ module \shiftrot0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:187713.15-187719.4" + attribute \src "libresoc.v:189030.15-189036.4" cell \req_l$121 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -386433,7 +357812,7 @@ module \shiftrot0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:187720.15-187726.4" + attribute \src "libresoc.v:189037.15-189043.4" cell \rok_l$123 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -386442,7 +357821,7 @@ module \shiftrot0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:187727.15-187732.4" + attribute \src "libresoc.v:189044.15-189049.4" cell \rst_l$122 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -386450,7 +357829,7 @@ module \shiftrot0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:187733.15-187739.4" + attribute \src "libresoc.v:189050.15-189056.4" cell \src_l$119 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -386458,667 +357837,667 @@ module \shiftrot0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:186877.7-186877.20" - process $proc$libresoc.v:186877$12685 + attribute \src "libresoc.v:188194.7-188194.20" + process $proc$libresoc.v:188194$12669 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:186999.7-186999.24" - process $proc$libresoc.v:186999$12686 + attribute \src "libresoc.v:188316.7-188316.24" + process $proc$libresoc.v:188316$12670 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:187009.7-187009.26" - process $proc$libresoc.v:187009$12687 + attribute \src "libresoc.v:188326.7-188326.26" + process $proc$libresoc.v:188326$12671 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:187017.7-187017.25" - process $proc$libresoc.v:187017$12688 + attribute \src "libresoc.v:188334.7-188334.25" + process $proc$libresoc.v:188334$12672 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:187060.14-187060.54" - process $proc$libresoc.v:187060$12689 + attribute \src "libresoc.v:188377.14-188377.54" + process $proc$libresoc.v:188377$12673 assign { } { } assign $1\alu_shift_rot0_sr_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_shift_rot0_sr_op__fn_unit $1\alu_shift_rot0_sr_op__fn_unit[13:0] end - attribute \src "libresoc.v:187064.14-187064.73" - process $proc$libresoc.v:187064$12690 + attribute \src "libresoc.v:188381.14-188381.73" + process $proc$libresoc.v:188381$12674 assign { } { } assign $1\alu_shift_rot0_sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_shift_rot0_sr_op__imm_data__data $1\alu_shift_rot0_sr_op__imm_data__data[63:0] end - attribute \src "libresoc.v:187068.7-187068.48" - process $proc$libresoc.v:187068$12691 + attribute \src "libresoc.v:188385.7-188385.48" + process $proc$libresoc.v:188385$12675 assign { } { } assign $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__imm_data__ok $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:187076.13-187076.53" - process $proc$libresoc.v:187076$12692 + attribute \src "libresoc.v:188393.13-188393.53" + process $proc$libresoc.v:188393$12676 assign { } { } assign $1\alu_shift_rot0_sr_op__input_carry[1:0] 2'00 sync always sync init update \alu_shift_rot0_sr_op__input_carry $1\alu_shift_rot0_sr_op__input_carry[1:0] end - attribute \src "libresoc.v:187080.7-187080.44" - process $proc$libresoc.v:187080$12693 + attribute \src "libresoc.v:188397.7-188397.44" + process $proc$libresoc.v:188397$12677 assign { } { } assign $1\alu_shift_rot0_sr_op__input_cr[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__input_cr $1\alu_shift_rot0_sr_op__input_cr[0:0] end - attribute \src "libresoc.v:187084.14-187084.48" - process $proc$libresoc.v:187084$12694 + attribute \src "libresoc.v:188401.14-188401.48" + process $proc$libresoc.v:188401$12678 assign { } { } assign $1\alu_shift_rot0_sr_op__insn[31:0] 0 sync always sync init update \alu_shift_rot0_sr_op__insn $1\alu_shift_rot0_sr_op__insn[31:0] end - attribute \src "libresoc.v:187163.13-187163.52" - process $proc$libresoc.v:187163$12695 + attribute \src "libresoc.v:188480.13-188480.52" + process $proc$libresoc.v:188480$12679 assign { } { } assign $1\alu_shift_rot0_sr_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_shift_rot0_sr_op__insn_type $1\alu_shift_rot0_sr_op__insn_type[6:0] end - attribute \src "libresoc.v:187167.7-187167.45" - process $proc$libresoc.v:187167$12696 + attribute \src "libresoc.v:188484.7-188484.45" + process $proc$libresoc.v:188484$12680 assign { } { } assign $1\alu_shift_rot0_sr_op__invert_in[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__invert_in $1\alu_shift_rot0_sr_op__invert_in[0:0] end - attribute \src "libresoc.v:187171.7-187171.44" - process $proc$libresoc.v:187171$12697 + attribute \src "libresoc.v:188488.7-188488.44" + process $proc$libresoc.v:188488$12681 assign { } { } assign $1\alu_shift_rot0_sr_op__is_32bit[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__is_32bit $1\alu_shift_rot0_sr_op__is_32bit[0:0] end - attribute \src "libresoc.v:187175.7-187175.45" - process $proc$libresoc.v:187175$12698 + attribute \src "libresoc.v:188492.7-188492.45" + process $proc$libresoc.v:188492$12682 assign { } { } assign $1\alu_shift_rot0_sr_op__is_signed[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__is_signed $1\alu_shift_rot0_sr_op__is_signed[0:0] end - attribute \src "libresoc.v:187179.7-187179.42" - process $proc$libresoc.v:187179$12699 + attribute \src "libresoc.v:188496.7-188496.42" + process $proc$libresoc.v:188496$12683 assign { } { } assign $1\alu_shift_rot0_sr_op__oe__oe[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__oe__oe $1\alu_shift_rot0_sr_op__oe__oe[0:0] end - attribute \src "libresoc.v:187183.7-187183.42" - process $proc$libresoc.v:187183$12700 + attribute \src "libresoc.v:188500.7-188500.42" + process $proc$libresoc.v:188500$12684 assign { } { } assign $1\alu_shift_rot0_sr_op__oe__ok[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__oe__ok $1\alu_shift_rot0_sr_op__oe__ok[0:0] end - attribute \src "libresoc.v:187187.7-187187.48" - process $proc$libresoc.v:187187$12701 + attribute \src "libresoc.v:188504.7-188504.48" + process $proc$libresoc.v:188504$12685 assign { } { } assign $1\alu_shift_rot0_sr_op__output_carry[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__output_carry $1\alu_shift_rot0_sr_op__output_carry[0:0] end - attribute \src "libresoc.v:187191.7-187191.45" - process $proc$libresoc.v:187191$12702 + attribute \src "libresoc.v:188508.7-188508.45" + process $proc$libresoc.v:188508$12686 assign { } { } assign $1\alu_shift_rot0_sr_op__output_cr[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__output_cr $1\alu_shift_rot0_sr_op__output_cr[0:0] end - attribute \src "libresoc.v:187195.7-187195.42" - process $proc$libresoc.v:187195$12703 + attribute \src "libresoc.v:188512.7-188512.42" + process $proc$libresoc.v:188512$12687 assign { } { } assign $1\alu_shift_rot0_sr_op__rc__ok[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__rc__ok $1\alu_shift_rot0_sr_op__rc__ok[0:0] end - attribute \src "libresoc.v:187199.7-187199.42" - process $proc$libresoc.v:187199$12704 + attribute \src "libresoc.v:188516.7-188516.42" + process $proc$libresoc.v:188516$12688 assign { } { } assign $1\alu_shift_rot0_sr_op__rc__rc[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__rc__rc $1\alu_shift_rot0_sr_op__rc__rc[0:0] end - attribute \src "libresoc.v:187203.7-187203.45" - process $proc$libresoc.v:187203$12705 + attribute \src "libresoc.v:188520.7-188520.45" + process $proc$libresoc.v:188520$12689 assign { } { } assign $1\alu_shift_rot0_sr_op__write_cr0[0:0] 1'0 sync always sync init update \alu_shift_rot0_sr_op__write_cr0 $1\alu_shift_rot0_sr_op__write_cr0[0:0] end - attribute \src "libresoc.v:187215.7-187215.27" - process $proc$libresoc.v:187215$12706 + attribute \src "libresoc.v:188532.7-188532.27" + process $proc$libresoc.v:188532$12690 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:187249.14-187249.47" - process $proc$libresoc.v:187249$12707 + attribute \src "libresoc.v:188566.14-188566.47" + process $proc$libresoc.v:188566$12691 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:187253.7-187253.27" - process $proc$libresoc.v:187253$12708 + attribute \src "libresoc.v:188570.7-188570.27" + process $proc$libresoc.v:188570$12692 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:187257.13-187257.33" - process $proc$libresoc.v:187257$12709 + attribute \src "libresoc.v:188574.13-188574.33" + process $proc$libresoc.v:188574$12693 assign { } { } assign $1\data_r1__cr_a[3:0] 4'0000 sync always sync init update \data_r1__cr_a $1\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:187261.7-187261.30" - process $proc$libresoc.v:187261$12710 + attribute \src "libresoc.v:188578.7-188578.30" + process $proc$libresoc.v:188578$12694 assign { } { } assign $1\data_r1__cr_a_ok[0:0] 1'0 sync always sync init update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:187265.13-187265.35" - process $proc$libresoc.v:187265$12711 + attribute \src "libresoc.v:188582.13-188582.35" + process $proc$libresoc.v:188582$12695 assign { } { } assign $1\data_r2__xer_ca[1:0] 2'00 sync always sync init update \data_r2__xer_ca $1\data_r2__xer_ca[1:0] end - attribute \src "libresoc.v:187269.7-187269.32" - process $proc$libresoc.v:187269$12712 + attribute \src "libresoc.v:188586.7-188586.32" + process $proc$libresoc.v:188586$12696 assign { } { } assign $1\data_r2__xer_ca_ok[0:0] 1'0 sync always sync init update \data_r2__xer_ca_ok $1\data_r2__xer_ca_ok[0:0] end - attribute \src "libresoc.v:187286.7-187286.25" - process $proc$libresoc.v:187286$12713 + attribute \src "libresoc.v:188603.7-188603.25" + process $proc$libresoc.v:188603$12697 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:187290.7-187290.25" - process $proc$libresoc.v:187290$12714 + attribute \src "libresoc.v:188607.7-188607.25" + process $proc$libresoc.v:188607$12698 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:187422.13-187422.30" - process $proc$libresoc.v:187422$12715 + attribute \src "libresoc.v:188739.13-188739.30" + process $proc$libresoc.v:188739$12699 assign { } { } assign $1\prev_wr_go[2:0] 3'000 sync always sync init update \prev_wr_go $1\prev_wr_go[2:0] end - attribute \src "libresoc.v:187430.13-187430.31" - process $proc$libresoc.v:187430$12716 + attribute \src "libresoc.v:188747.13-188747.31" + process $proc$libresoc.v:188747$12700 assign { } { } assign $1\req_l_r_req[2:0] 3'111 sync always sync init update \req_l_r_req $1\req_l_r_req[2:0] end - attribute \src "libresoc.v:187434.13-187434.31" - process $proc$libresoc.v:187434$12717 + attribute \src "libresoc.v:188751.13-188751.31" + process $proc$libresoc.v:188751$12701 assign { } { } assign $1\req_l_s_req[2:0] 3'000 sync always sync init update \req_l_s_req $1\req_l_s_req[2:0] end - attribute \src "libresoc.v:187446.7-187446.26" - process $proc$libresoc.v:187446$12718 + attribute \src "libresoc.v:188763.7-188763.26" + process $proc$libresoc.v:188763$12702 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:187450.7-187450.26" - process $proc$libresoc.v:187450$12719 + attribute \src "libresoc.v:188767.7-188767.26" + process $proc$libresoc.v:188767$12703 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:187454.7-187454.25" - process $proc$libresoc.v:187454$12720 + attribute \src "libresoc.v:188771.7-188771.25" + process $proc$libresoc.v:188771$12704 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:187458.7-187458.25" - process $proc$libresoc.v:187458$12721 + attribute \src "libresoc.v:188775.7-188775.25" + process $proc$libresoc.v:188775$12705 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:187476.13-187476.32" - process $proc$libresoc.v:187476$12722 + attribute \src "libresoc.v:188793.13-188793.32" + process $proc$libresoc.v:188793$12706 assign { } { } assign $1\src_l_r_src[4:0] 5'11111 sync always sync init update \src_l_r_src $1\src_l_r_src[4:0] end - attribute \src "libresoc.v:187480.13-187480.32" - process $proc$libresoc.v:187480$12723 + attribute \src "libresoc.v:188797.13-188797.32" + process $proc$libresoc.v:188797$12707 assign { } { } assign $1\src_l_s_src[4:0] 5'00000 sync always sync init update \src_l_s_src $1\src_l_s_src[4:0] end - attribute \src "libresoc.v:187486.14-187486.43" - process $proc$libresoc.v:187486$12724 + attribute \src "libresoc.v:188803.14-188803.43" + process $proc$libresoc.v:188803$12708 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:187490.14-187490.43" - process $proc$libresoc.v:187490$12725 + attribute \src "libresoc.v:188807.14-188807.43" + process $proc$libresoc.v:188807$12709 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:187494.14-187494.43" - process $proc$libresoc.v:187494$12726 + attribute \src "libresoc.v:188811.14-188811.43" + process $proc$libresoc.v:188811$12710 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end - attribute \src "libresoc.v:187498.7-187498.20" - process $proc$libresoc.v:187498$12727 + attribute \src "libresoc.v:188815.7-188815.20" + process $proc$libresoc.v:188815$12711 assign { } { } assign $1\src_r3[0:0] 1'0 sync always sync init update \src_r3 $1\src_r3[0:0] end - attribute \src "libresoc.v:187502.13-187502.26" - process $proc$libresoc.v:187502$12728 + attribute \src "libresoc.v:188819.13-188819.26" + process $proc$libresoc.v:188819$12712 assign { } { } assign $1\src_r4[1:0] 2'00 sync always sync init update \src_r4 $1\src_r4[1:0] end - attribute \src "libresoc.v:187570.3-187571.39" - process $proc$libresoc.v:187570$12519 + attribute \src "libresoc.v:188887.3-188888.39" + process $proc$libresoc.v:188887$12503 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:187572.3-187573.43" - process $proc$libresoc.v:187572$12520 + attribute \src "libresoc.v:188889.3-188890.43" + process $proc$libresoc.v:188889$12504 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:187574.3-187575.29" - process $proc$libresoc.v:187574$12521 + attribute \src "libresoc.v:188891.3-188892.29" + process $proc$libresoc.v:188891$12505 assign { } { } assign $0\src_r4[1:0] \src_r4$next sync posedge \coresync_clk update \src_r4 $0\src_r4[1:0] end - attribute \src "libresoc.v:187576.3-187577.29" - process $proc$libresoc.v:187576$12522 + attribute \src "libresoc.v:188893.3-188894.29" + process $proc$libresoc.v:188893$12506 assign { } { } assign $0\src_r3[0:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[0:0] end - attribute \src "libresoc.v:187578.3-187579.29" - process $proc$libresoc.v:187578$12523 + attribute \src "libresoc.v:188895.3-188896.29" + process $proc$libresoc.v:188895$12507 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end - attribute \src "libresoc.v:187580.3-187581.29" - process $proc$libresoc.v:187580$12524 + attribute \src "libresoc.v:188897.3-188898.29" + process $proc$libresoc.v:188897$12508 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:187582.3-187583.29" - process $proc$libresoc.v:187582$12525 + attribute \src "libresoc.v:188899.3-188900.29" + process $proc$libresoc.v:188899$12509 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:187584.3-187585.47" - process $proc$libresoc.v:187584$12526 + attribute \src "libresoc.v:188901.3-188902.47" + process $proc$libresoc.v:188901$12510 assign { } { } assign $0\data_r2__xer_ca[1:0] \data_r2__xer_ca$next sync posedge \coresync_clk update \data_r2__xer_ca $0\data_r2__xer_ca[1:0] end - attribute \src "libresoc.v:187586.3-187587.53" - process $proc$libresoc.v:187586$12527 + attribute \src "libresoc.v:188903.3-188904.53" + process $proc$libresoc.v:188903$12511 assign { } { } assign $0\data_r2__xer_ca_ok[0:0] \data_r2__xer_ca_ok$next sync posedge \coresync_clk update \data_r2__xer_ca_ok $0\data_r2__xer_ca_ok[0:0] end - attribute \src "libresoc.v:187588.3-187589.43" - process $proc$libresoc.v:187588$12528 + attribute \src "libresoc.v:188905.3-188906.43" + process $proc$libresoc.v:188905$12512 assign { } { } assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next sync posedge \coresync_clk update \data_r1__cr_a $0\data_r1__cr_a[3:0] end - attribute \src "libresoc.v:187590.3-187591.49" - process $proc$libresoc.v:187590$12529 + attribute \src "libresoc.v:188907.3-188908.49" + process $proc$libresoc.v:188907$12513 assign { } { } assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next sync posedge \coresync_clk update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] end - attribute \src "libresoc.v:187592.3-187593.37" - process $proc$libresoc.v:187592$12530 + attribute \src "libresoc.v:188909.3-188910.37" + process $proc$libresoc.v:188909$12514 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:187594.3-187595.43" - process $proc$libresoc.v:187594$12531 + attribute \src "libresoc.v:188911.3-188912.43" + process $proc$libresoc.v:188911$12515 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:187596.3-187597.79" - process $proc$libresoc.v:187596$12532 + attribute \src "libresoc.v:188913.3-188914.79" + process $proc$libresoc.v:188913$12516 assign { } { } assign $0\alu_shift_rot0_sr_op__insn_type[6:0] \alu_shift_rot0_sr_op__insn_type$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__insn_type $0\alu_shift_rot0_sr_op__insn_type[6:0] end - attribute \src "libresoc.v:187598.3-187599.75" - process $proc$libresoc.v:187598$12533 + attribute \src "libresoc.v:188915.3-188916.75" + process $proc$libresoc.v:188915$12517 assign { } { } assign $0\alu_shift_rot0_sr_op__fn_unit[13:0] \alu_shift_rot0_sr_op__fn_unit$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__fn_unit $0\alu_shift_rot0_sr_op__fn_unit[13:0] end - attribute \src "libresoc.v:187600.3-187601.89" - process $proc$libresoc.v:187600$12534 + attribute \src "libresoc.v:188917.3-188918.89" + process $proc$libresoc.v:188917$12518 assign { } { } assign $0\alu_shift_rot0_sr_op__imm_data__data[63:0] \alu_shift_rot0_sr_op__imm_data__data$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__imm_data__data $0\alu_shift_rot0_sr_op__imm_data__data[63:0] end - attribute \src "libresoc.v:187602.3-187603.85" - process $proc$libresoc.v:187602$12535 + attribute \src "libresoc.v:188919.3-188920.85" + process $proc$libresoc.v:188919$12519 assign { } { } assign $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] \alu_shift_rot0_sr_op__imm_data__ok$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__imm_data__ok $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] end - attribute \src "libresoc.v:187604.3-187605.73" - process $proc$libresoc.v:187604$12536 + attribute \src "libresoc.v:188921.3-188922.73" + process $proc$libresoc.v:188921$12520 assign { } { } assign $0\alu_shift_rot0_sr_op__rc__rc[0:0] \alu_shift_rot0_sr_op__rc__rc$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__rc__rc $0\alu_shift_rot0_sr_op__rc__rc[0:0] end - attribute \src "libresoc.v:187606.3-187607.73" - process $proc$libresoc.v:187606$12537 + attribute \src "libresoc.v:188923.3-188924.73" + process $proc$libresoc.v:188923$12521 assign { } { } assign $0\alu_shift_rot0_sr_op__rc__ok[0:0] \alu_shift_rot0_sr_op__rc__ok$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__rc__ok $0\alu_shift_rot0_sr_op__rc__ok[0:0] end - attribute \src "libresoc.v:187608.3-187609.73" - process $proc$libresoc.v:187608$12538 + attribute \src "libresoc.v:188925.3-188926.73" + process $proc$libresoc.v:188925$12522 assign { } { } assign $0\alu_shift_rot0_sr_op__oe__oe[0:0] \alu_shift_rot0_sr_op__oe__oe$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__oe__oe $0\alu_shift_rot0_sr_op__oe__oe[0:0] end - attribute \src "libresoc.v:187610.3-187611.73" - process $proc$libresoc.v:187610$12539 + attribute \src "libresoc.v:188927.3-188928.73" + process $proc$libresoc.v:188927$12523 assign { } { } assign $0\alu_shift_rot0_sr_op__oe__ok[0:0] \alu_shift_rot0_sr_op__oe__ok$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__oe__ok $0\alu_shift_rot0_sr_op__oe__ok[0:0] end - attribute \src "libresoc.v:187612.3-187613.79" - process $proc$libresoc.v:187612$12540 + attribute \src "libresoc.v:188929.3-188930.79" + process $proc$libresoc.v:188929$12524 assign { } { } assign $0\alu_shift_rot0_sr_op__write_cr0[0:0] \alu_shift_rot0_sr_op__write_cr0$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__write_cr0 $0\alu_shift_rot0_sr_op__write_cr0[0:0] end - attribute \src "libresoc.v:187614.3-187615.79" - process $proc$libresoc.v:187614$12541 + attribute \src "libresoc.v:188931.3-188932.79" + process $proc$libresoc.v:188931$12525 assign { } { } assign $0\alu_shift_rot0_sr_op__invert_in[0:0] \alu_shift_rot0_sr_op__invert_in$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__invert_in $0\alu_shift_rot0_sr_op__invert_in[0:0] end - attribute \src "libresoc.v:187616.3-187617.83" - process $proc$libresoc.v:187616$12542 + attribute \src "libresoc.v:188933.3-188934.83" + process $proc$libresoc.v:188933$12526 assign { } { } assign $0\alu_shift_rot0_sr_op__input_carry[1:0] \alu_shift_rot0_sr_op__input_carry$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__input_carry $0\alu_shift_rot0_sr_op__input_carry[1:0] end - attribute \src "libresoc.v:187618.3-187619.85" - process $proc$libresoc.v:187618$12543 + attribute \src "libresoc.v:188935.3-188936.85" + process $proc$libresoc.v:188935$12527 assign { } { } assign $0\alu_shift_rot0_sr_op__output_carry[0:0] \alu_shift_rot0_sr_op__output_carry$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__output_carry $0\alu_shift_rot0_sr_op__output_carry[0:0] end - attribute \src "libresoc.v:187620.3-187621.77" - process $proc$libresoc.v:187620$12544 + attribute \src "libresoc.v:188937.3-188938.77" + process $proc$libresoc.v:188937$12528 assign { } { } assign $0\alu_shift_rot0_sr_op__input_cr[0:0] \alu_shift_rot0_sr_op__input_cr$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__input_cr $0\alu_shift_rot0_sr_op__input_cr[0:0] end - attribute \src "libresoc.v:187622.3-187623.79" - process $proc$libresoc.v:187622$12545 + attribute \src "libresoc.v:188939.3-188940.79" + process $proc$libresoc.v:188939$12529 assign { } { } assign $0\alu_shift_rot0_sr_op__output_cr[0:0] \alu_shift_rot0_sr_op__output_cr$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__output_cr $0\alu_shift_rot0_sr_op__output_cr[0:0] end - attribute \src "libresoc.v:187624.3-187625.77" - process $proc$libresoc.v:187624$12546 + attribute \src "libresoc.v:188941.3-188942.77" + process $proc$libresoc.v:188941$12530 assign { } { } assign $0\alu_shift_rot0_sr_op__is_32bit[0:0] \alu_shift_rot0_sr_op__is_32bit$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__is_32bit $0\alu_shift_rot0_sr_op__is_32bit[0:0] end - attribute \src "libresoc.v:187626.3-187627.79" - process $proc$libresoc.v:187626$12547 + attribute \src "libresoc.v:188943.3-188944.79" + process $proc$libresoc.v:188943$12531 assign { } { } assign $0\alu_shift_rot0_sr_op__is_signed[0:0] \alu_shift_rot0_sr_op__is_signed$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__is_signed $0\alu_shift_rot0_sr_op__is_signed[0:0] end - attribute \src "libresoc.v:187628.3-187629.69" - process $proc$libresoc.v:187628$12548 + attribute \src "libresoc.v:188945.3-188946.69" + process $proc$libresoc.v:188945$12532 assign { } { } assign $0\alu_shift_rot0_sr_op__insn[31:0] \alu_shift_rot0_sr_op__insn$next sync posedge \coresync_clk update \alu_shift_rot0_sr_op__insn $0\alu_shift_rot0_sr_op__insn[31:0] end - attribute \src "libresoc.v:187630.3-187631.39" - process $proc$libresoc.v:187630$12549 + attribute \src "libresoc.v:188947.3-188948.39" + process $proc$libresoc.v:188947$12533 assign { } { } assign $0\req_l_r_req[2:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[2:0] end - attribute \src "libresoc.v:187632.3-187633.39" - process $proc$libresoc.v:187632$12550 + attribute \src "libresoc.v:188949.3-188950.39" + process $proc$libresoc.v:188949$12534 assign { } { } assign $0\req_l_s_req[2:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[2:0] end - attribute \src "libresoc.v:187634.3-187635.39" - process $proc$libresoc.v:187634$12551 + attribute \src "libresoc.v:188951.3-188952.39" + process $proc$libresoc.v:188951$12535 assign { } { } assign $0\src_l_r_src[4:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[4:0] end - attribute \src "libresoc.v:187636.3-187637.39" - process $proc$libresoc.v:187636$12552 + attribute \src "libresoc.v:188953.3-188954.39" + process $proc$libresoc.v:188953$12536 assign { } { } assign $0\src_l_s_src[4:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[4:0] end - attribute \src "libresoc.v:187638.3-187639.39" - process $proc$libresoc.v:187638$12553 + attribute \src "libresoc.v:188955.3-188956.39" + process $proc$libresoc.v:188955$12537 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:187640.3-187641.39" - process $proc$libresoc.v:187640$12554 + attribute \src "libresoc.v:188957.3-188958.39" + process $proc$libresoc.v:188957$12538 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:187642.3-187643.39" - process $proc$libresoc.v:187642$12555 + attribute \src "libresoc.v:188959.3-188960.39" + process $proc$libresoc.v:188959$12539 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:187644.3-187645.39" - process $proc$libresoc.v:187644$12556 + attribute \src "libresoc.v:188961.3-188962.39" + process $proc$libresoc.v:188961$12540 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:187646.3-187647.41" - process $proc$libresoc.v:187646$12557 + attribute \src "libresoc.v:188963.3-188964.41" + process $proc$libresoc.v:188963$12541 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:187648.3-187649.41" - process $proc$libresoc.v:187648$12558 + attribute \src "libresoc.v:188965.3-188966.41" + process $proc$libresoc.v:188965$12542 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:187650.3-187651.37" - process $proc$libresoc.v:187650$12559 + attribute \src "libresoc.v:188967.3-188968.37" + process $proc$libresoc.v:188967$12543 assign { } { } assign $0\prev_wr_go[2:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[2:0] end - attribute \src "libresoc.v:187652.3-187653.46" - process $proc$libresoc.v:187652$12560 + attribute \src "libresoc.v:188969.3-188970.46" + process $proc$libresoc.v:188969$12544 assign { } { } assign $0\alu_done_dly[0:0] \alu_shift_rot0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:187654.3-187655.25" - process $proc$libresoc.v:187654$12561 + attribute \src "libresoc.v:188971.3-188972.25" + process $proc$libresoc.v:188971$12545 assign { } { } assign $0\all_rd_dly[0:0] \$10 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:187740.3-187749.6" - process $proc$libresoc.v:187740$12562 + attribute \src "libresoc.v:189057.3-189066.6" + process $proc$libresoc.v:189057$12546 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:187741.5-187741.29" + attribute \src "libresoc.v:189058.5-189058.29" switch \initial - attribute \src "libresoc.v:187741.9-187741.17" + attribute \src "libresoc.v:189058.9-189058.17" case 1'1 case end @@ -387134,14 +358513,14 @@ module \shiftrot0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:187750.3-187758.6" - process $proc$libresoc.v:187750$12563 + attribute \src "libresoc.v:189067.3-189075.6" + process $proc$libresoc.v:189067$12547 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$12564 $1\rok_l_s_rdok$next[0:0]$12565 - attribute \src "libresoc.v:187751.5-187751.29" + assign $0\rok_l_s_rdok$next[0:0]$12548 $1\rok_l_s_rdok$next[0:0]$12549 + attribute \src "libresoc.v:189068.5-189068.29" switch \initial - attribute \src "libresoc.v:187751.9-187751.17" + attribute \src "libresoc.v:189068.9-189068.17" case 1'1 case end @@ -387150,21 +358529,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$12565 1'0 + assign $1\rok_l_s_rdok$next[0:0]$12549 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$12565 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$12549 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12564 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12548 end - attribute \src "libresoc.v:187759.3-187767.6" - process $proc$libresoc.v:187759$12566 + attribute \src "libresoc.v:189076.3-189084.6" + process $proc$libresoc.v:189076$12550 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$12567 $1\rok_l_r_rdok$next[0:0]$12568 - attribute \src "libresoc.v:187760.5-187760.29" + assign $0\rok_l_r_rdok$next[0:0]$12551 $1\rok_l_r_rdok$next[0:0]$12552 + attribute \src "libresoc.v:189077.5-189077.29" switch \initial - attribute \src "libresoc.v:187760.9-187760.17" + attribute \src "libresoc.v:189077.9-189077.17" case 1'1 case end @@ -387173,21 +358552,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$12568 1'1 + assign $1\rok_l_r_rdok$next[0:0]$12552 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$12568 \$64 + assign $1\rok_l_r_rdok$next[0:0]$12552 \$64 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12567 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12551 end - attribute \src "libresoc.v:187768.3-187776.6" - process $proc$libresoc.v:187768$12569 + attribute \src "libresoc.v:189085.3-189093.6" + process $proc$libresoc.v:189085$12553 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$12570 $1\rst_l_s_rst$next[0:0]$12571 - attribute \src "libresoc.v:187769.5-187769.29" + assign $0\rst_l_s_rst$next[0:0]$12554 $1\rst_l_s_rst$next[0:0]$12555 + attribute \src "libresoc.v:189086.5-189086.29" switch \initial - attribute \src "libresoc.v:187769.9-187769.17" + attribute \src "libresoc.v:189086.9-189086.17" case 1'1 case end @@ -387196,21 +358575,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$12571 1'0 + assign $1\rst_l_s_rst$next[0:0]$12555 1'0 case - assign $1\rst_l_s_rst$next[0:0]$12571 \all_rd + assign $1\rst_l_s_rst$next[0:0]$12555 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12570 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12554 end - attribute \src "libresoc.v:187777.3-187785.6" - process $proc$libresoc.v:187777$12572 + attribute \src "libresoc.v:189094.3-189102.6" + process $proc$libresoc.v:189094$12556 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$12573 $1\rst_l_r_rst$next[0:0]$12574 - attribute \src "libresoc.v:187778.5-187778.29" + assign $0\rst_l_r_rst$next[0:0]$12557 $1\rst_l_r_rst$next[0:0]$12558 + attribute \src "libresoc.v:189095.5-189095.29" switch \initial - attribute \src "libresoc.v:187778.9-187778.17" + attribute \src "libresoc.v:189095.9-189095.17" case 1'1 case end @@ -387219,21 +358598,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$12574 1'1 + assign $1\rst_l_r_rst$next[0:0]$12558 1'1 case - assign $1\rst_l_r_rst$next[0:0]$12574 \rst_r + assign $1\rst_l_r_rst$next[0:0]$12558 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12573 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12557 end - attribute \src "libresoc.v:187786.3-187794.6" - process $proc$libresoc.v:187786$12575 + attribute \src "libresoc.v:189103.3-189111.6" + process $proc$libresoc.v:189103$12559 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$12576 $1\opc_l_s_opc$next[0:0]$12577 - attribute \src "libresoc.v:187787.5-187787.29" + assign $0\opc_l_s_opc$next[0:0]$12560 $1\opc_l_s_opc$next[0:0]$12561 + attribute \src "libresoc.v:189104.5-189104.29" switch \initial - attribute \src "libresoc.v:187787.9-187787.17" + attribute \src "libresoc.v:189104.9-189104.17" case 1'1 case end @@ -387242,21 +358621,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$12577 1'0 + assign $1\opc_l_s_opc$next[0:0]$12561 1'0 case - assign $1\opc_l_s_opc$next[0:0]$12577 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$12561 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12576 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12560 end - attribute \src "libresoc.v:187795.3-187803.6" - process $proc$libresoc.v:187795$12578 + attribute \src "libresoc.v:189112.3-189120.6" + process $proc$libresoc.v:189112$12562 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$12579 $1\opc_l_r_opc$next[0:0]$12580 - attribute \src "libresoc.v:187796.5-187796.29" + assign $0\opc_l_r_opc$next[0:0]$12563 $1\opc_l_r_opc$next[0:0]$12564 + attribute \src "libresoc.v:189113.5-189113.29" switch \initial - attribute \src "libresoc.v:187796.9-187796.17" + attribute \src "libresoc.v:189113.9-189113.17" case 1'1 case end @@ -387265,21 +358644,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$12580 1'1 + assign $1\opc_l_r_opc$next[0:0]$12564 1'1 case - assign $1\opc_l_r_opc$next[0:0]$12580 \req_done + assign $1\opc_l_r_opc$next[0:0]$12564 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12579 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12563 end - attribute \src "libresoc.v:187804.3-187812.6" - process $proc$libresoc.v:187804$12581 + attribute \src "libresoc.v:189121.3-189129.6" + process $proc$libresoc.v:189121$12565 assign { } { } assign { } { } - assign $0\src_l_s_src$next[4:0]$12582 $1\src_l_s_src$next[4:0]$12583 - attribute \src "libresoc.v:187805.5-187805.29" + assign $0\src_l_s_src$next[4:0]$12566 $1\src_l_s_src$next[4:0]$12567 + attribute \src "libresoc.v:189122.5-189122.29" switch \initial - attribute \src "libresoc.v:187805.9-187805.17" + attribute \src "libresoc.v:189122.9-189122.17" case 1'1 case end @@ -387288,21 +358667,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[4:0]$12583 5'00000 + assign $1\src_l_s_src$next[4:0]$12567 5'00000 case - assign $1\src_l_s_src$next[4:0]$12583 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[4:0]$12567 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[4:0]$12582 + update \src_l_s_src$next $0\src_l_s_src$next[4:0]$12566 end - attribute \src "libresoc.v:187813.3-187821.6" - process $proc$libresoc.v:187813$12584 + attribute \src "libresoc.v:189130.3-189138.6" + process $proc$libresoc.v:189130$12568 assign { } { } assign { } { } - assign $0\src_l_r_src$next[4:0]$12585 $1\src_l_r_src$next[4:0]$12586 - attribute \src "libresoc.v:187814.5-187814.29" + assign $0\src_l_r_src$next[4:0]$12569 $1\src_l_r_src$next[4:0]$12570 + attribute \src "libresoc.v:189131.5-189131.29" switch \initial - attribute \src "libresoc.v:187814.9-187814.17" + attribute \src "libresoc.v:189131.9-189131.17" case 1'1 case end @@ -387311,21 +358690,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[4:0]$12586 5'11111 + assign $1\src_l_r_src$next[4:0]$12570 5'11111 case - assign $1\src_l_r_src$next[4:0]$12586 \reset_r + assign $1\src_l_r_src$next[4:0]$12570 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[4:0]$12585 + update \src_l_r_src$next $0\src_l_r_src$next[4:0]$12569 end - attribute \src "libresoc.v:187822.3-187830.6" - process $proc$libresoc.v:187822$12587 + attribute \src "libresoc.v:189139.3-189147.6" + process $proc$libresoc.v:189139$12571 assign { } { } assign { } { } - assign $0\req_l_s_req$next[2:0]$12588 $1\req_l_s_req$next[2:0]$12589 - attribute \src "libresoc.v:187823.5-187823.29" + assign $0\req_l_s_req$next[2:0]$12572 $1\req_l_s_req$next[2:0]$12573 + attribute \src "libresoc.v:189140.5-189140.29" switch \initial - attribute \src "libresoc.v:187823.9-187823.17" + attribute \src "libresoc.v:189140.9-189140.17" case 1'1 case end @@ -387334,21 +358713,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[2:0]$12589 3'000 + assign $1\req_l_s_req$next[2:0]$12573 3'000 case - assign $1\req_l_s_req$next[2:0]$12589 \$66 + assign $1\req_l_s_req$next[2:0]$12573 \$66 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[2:0]$12588 + update \req_l_s_req$next $0\req_l_s_req$next[2:0]$12572 end - attribute \src "libresoc.v:187831.3-187839.6" - process $proc$libresoc.v:187831$12590 + attribute \src "libresoc.v:189148.3-189156.6" + process $proc$libresoc.v:189148$12574 assign { } { } assign { } { } - assign $0\req_l_r_req$next[2:0]$12591 $1\req_l_r_req$next[2:0]$12592 - attribute \src "libresoc.v:187832.5-187832.29" + assign $0\req_l_r_req$next[2:0]$12575 $1\req_l_r_req$next[2:0]$12576 + attribute \src "libresoc.v:189149.5-189149.29" switch \initial - attribute \src "libresoc.v:187832.9-187832.17" + attribute \src "libresoc.v:189149.9-189149.17" case 1'1 case end @@ -387357,15 +358736,15 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[2:0]$12592 3'111 + assign $1\req_l_r_req$next[2:0]$12576 3'111 case - assign $1\req_l_r_req$next[2:0]$12592 \$68 + assign $1\req_l_r_req$next[2:0]$12576 \$68 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[2:0]$12591 + update \req_l_r_req$next $0\req_l_r_req$next[2:0]$12575 end - attribute \src "libresoc.v:187840.3-187877.6" - process $proc$libresoc.v:187840$12593 + attribute \src "libresoc.v:189157.3-189194.6" + process $proc$libresoc.v:189157$12577 assign { } { } assign { } { } assign { } { } @@ -387400,32 +358779,32 @@ module \shiftrot0 assign { } { } assign { } { } assign { } { } - assign $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12594 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12611 + assign $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12578 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12595 assign { } { } assign { } { } - assign $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12597 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12614 - assign $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12598 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12615 - assign $0\alu_shift_rot0_sr_op__insn$next[31:0]$12599 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12616 - assign $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12600 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12617 - assign $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12601 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12618 - assign $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12602 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12619 - assign $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12603 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12620 + assign $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12581 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12598 + assign $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12582 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12599 + assign $0\alu_shift_rot0_sr_op__insn$next[31:0]$12583 $1\alu_shift_rot0_sr_op__insn$next[31:0]$12600 + assign $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12584 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12601 + assign $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12585 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12602 + assign $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12586 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12603 + assign $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12587 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12604 assign { } { } assign { } { } - assign $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12606 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12623 - assign $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12607 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12624 + assign $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12590 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12607 + assign $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12591 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12608 assign { } { } assign { } { } - assign $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12610 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12627 - assign $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12595 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12628 - assign $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12596 $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12629 - assign $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12604 $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12630 - assign $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12605 $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12631 - assign $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12608 $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12632 - assign $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12609 $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12633 - attribute \src "libresoc.v:187841.5-187841.29" + assign $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12594 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12611 + assign $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12579 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12612 + assign $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12580 $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12613 + assign $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12588 $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12614 + assign $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12589 $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12615 + assign $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12592 $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12616 + assign $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12593 $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12617 + attribute \src "libresoc.v:189158.5-189158.29" switch \initial - attribute \src "libresoc.v:187841.9-187841.17" + attribute \src "libresoc.v:189158.9-189158.17" case 1'1 case end @@ -387450,25 +358829,25 @@ module \shiftrot0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_shift_rot0_sr_op__insn$next[31:0]$12616 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12620 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12619 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12624 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12615 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12623 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12614 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12618 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12627 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12622 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12621 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12625 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12626 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12613 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12612 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12611 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12617 } { \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__invert_in \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__data \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__insn_type } + assign { $1\alu_shift_rot0_sr_op__insn$next[31:0]$12600 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12604 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12603 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12608 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12599 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12607 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12598 $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12602 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12611 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12606 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12605 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12609 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12610 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12597 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12596 $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12595 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12601 } { \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__invert_in \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__data \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__insn_type } case - assign $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12611 \alu_shift_rot0_sr_op__fn_unit - assign $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12612 \alu_shift_rot0_sr_op__imm_data__data - assign $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12613 \alu_shift_rot0_sr_op__imm_data__ok - assign $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12614 \alu_shift_rot0_sr_op__input_carry - assign $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12615 \alu_shift_rot0_sr_op__input_cr - assign $1\alu_shift_rot0_sr_op__insn$next[31:0]$12616 \alu_shift_rot0_sr_op__insn - assign $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12617 \alu_shift_rot0_sr_op__insn_type - assign $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12618 \alu_shift_rot0_sr_op__invert_in - assign $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12619 \alu_shift_rot0_sr_op__is_32bit - assign $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12620 \alu_shift_rot0_sr_op__is_signed - assign $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12621 \alu_shift_rot0_sr_op__oe__oe - assign $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12622 \alu_shift_rot0_sr_op__oe__ok - assign $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12623 \alu_shift_rot0_sr_op__output_carry - assign $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12624 \alu_shift_rot0_sr_op__output_cr - assign $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12625 \alu_shift_rot0_sr_op__rc__ok - assign $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12626 \alu_shift_rot0_sr_op__rc__rc - assign $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12627 \alu_shift_rot0_sr_op__write_cr0 + assign $1\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12595 \alu_shift_rot0_sr_op__fn_unit + assign $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12596 \alu_shift_rot0_sr_op__imm_data__data + assign $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12597 \alu_shift_rot0_sr_op__imm_data__ok + assign $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$12598 \alu_shift_rot0_sr_op__input_carry + assign $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$12599 \alu_shift_rot0_sr_op__input_cr + assign $1\alu_shift_rot0_sr_op__insn$next[31:0]$12600 \alu_shift_rot0_sr_op__insn + assign $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$12601 \alu_shift_rot0_sr_op__insn_type + assign $1\alu_shift_rot0_sr_op__invert_in$next[0:0]$12602 \alu_shift_rot0_sr_op__invert_in + assign $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12603 \alu_shift_rot0_sr_op__is_32bit + assign $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$12604 \alu_shift_rot0_sr_op__is_signed + assign $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12605 \alu_shift_rot0_sr_op__oe__oe + assign $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12606 \alu_shift_rot0_sr_op__oe__ok + assign $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$12607 \alu_shift_rot0_sr_op__output_carry + assign $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$12608 \alu_shift_rot0_sr_op__output_cr + assign $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12609 \alu_shift_rot0_sr_op__rc__ok + assign $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12610 \alu_shift_rot0_sr_op__rc__rc + assign $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12611 \alu_shift_rot0_sr_op__write_cr0 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst @@ -387480,53 +358859,53 @@ module \shiftrot0 assign { } { } assign { } { } assign { } { } - assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12628 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12629 1'0 - assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12633 1'0 - assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12632 1'0 - assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12630 1'0 - assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12631 1'0 + assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12612 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12613 1'0 + assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12617 1'0 + assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12616 1'0 + assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12614 1'0 + assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12615 1'0 case - assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12628 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12612 - assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12629 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12613 - assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12630 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12621 - assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12631 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12622 - assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12632 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12625 - assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12633 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12626 + assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12612 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12596 + assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12613 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12597 + assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12614 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12605 + assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12615 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12606 + assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12616 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12609 + assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12617 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12610 end sync always - update \alu_shift_rot0_sr_op__fn_unit$next $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12594 - update \alu_shift_rot0_sr_op__imm_data__data$next $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12595 - update \alu_shift_rot0_sr_op__imm_data__ok$next $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12596 - update \alu_shift_rot0_sr_op__input_carry$next $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12597 - update \alu_shift_rot0_sr_op__input_cr$next $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12598 - update \alu_shift_rot0_sr_op__insn$next $0\alu_shift_rot0_sr_op__insn$next[31:0]$12599 - update \alu_shift_rot0_sr_op__insn_type$next $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12600 - update \alu_shift_rot0_sr_op__invert_in$next $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12601 - update \alu_shift_rot0_sr_op__is_32bit$next $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12602 - update \alu_shift_rot0_sr_op__is_signed$next $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12603 - update \alu_shift_rot0_sr_op__oe__oe$next $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12604 - update \alu_shift_rot0_sr_op__oe__ok$next $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12605 - update \alu_shift_rot0_sr_op__output_carry$next $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12606 - update \alu_shift_rot0_sr_op__output_cr$next $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12607 - update \alu_shift_rot0_sr_op__rc__ok$next $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12608 - update \alu_shift_rot0_sr_op__rc__rc$next $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12609 - update \alu_shift_rot0_sr_op__write_cr0$next $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12610 + update \alu_shift_rot0_sr_op__fn_unit$next $0\alu_shift_rot0_sr_op__fn_unit$next[13:0]$12578 + update \alu_shift_rot0_sr_op__imm_data__data$next $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$12579 + update \alu_shift_rot0_sr_op__imm_data__ok$next $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$12580 + update \alu_shift_rot0_sr_op__input_carry$next $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$12581 + update \alu_shift_rot0_sr_op__input_cr$next $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$12582 + update \alu_shift_rot0_sr_op__insn$next $0\alu_shift_rot0_sr_op__insn$next[31:0]$12583 + update \alu_shift_rot0_sr_op__insn_type$next $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$12584 + update \alu_shift_rot0_sr_op__invert_in$next $0\alu_shift_rot0_sr_op__invert_in$next[0:0]$12585 + update \alu_shift_rot0_sr_op__is_32bit$next $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$12586 + update \alu_shift_rot0_sr_op__is_signed$next $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$12587 + update \alu_shift_rot0_sr_op__oe__oe$next $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$12588 + update \alu_shift_rot0_sr_op__oe__ok$next $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$12589 + update \alu_shift_rot0_sr_op__output_carry$next $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$12590 + update \alu_shift_rot0_sr_op__output_cr$next $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$12591 + update \alu_shift_rot0_sr_op__rc__ok$next $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$12592 + update \alu_shift_rot0_sr_op__rc__rc$next $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$12593 + update \alu_shift_rot0_sr_op__write_cr0$next $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$12594 end - attribute \src "libresoc.v:187878.3-187899.6" - process $proc$libresoc.v:187878$12634 + attribute \src "libresoc.v:189195.3-189216.6" + process $proc$libresoc.v:189195$12618 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$12635 $2\data_r0__o$next[63:0]$12639 + assign $0\data_r0__o$next[63:0]$12619 $2\data_r0__o$next[63:0]$12623 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$12636 $3\data_r0__o_ok$next[0:0]$12641 - attribute \src "libresoc.v:187879.5-187879.29" + assign $0\data_r0__o_ok$next[0:0]$12620 $3\data_r0__o_ok$next[0:0]$12625 + attribute \src "libresoc.v:189196.5-189196.29" switch \initial - attribute \src "libresoc.v:187879.9-187879.17" + attribute \src "libresoc.v:189196.9-189196.17" case 1'1 case end @@ -387536,10 +358915,10 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$12638 $1\data_r0__o$next[63:0]$12637 } { \o_ok \alu_shift_rot0_o } + assign { $1\data_r0__o_ok$next[0:0]$12622 $1\data_r0__o$next[63:0]$12621 } { \o_ok \alu_shift_rot0_o } case - assign $1\data_r0__o$next[63:0]$12637 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$12638 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$12621 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$12622 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -387547,38 +358926,38 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$12640 $2\data_r0__o$next[63:0]$12639 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$12624 $2\data_r0__o$next[63:0]$12623 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$12639 $1\data_r0__o$next[63:0]$12637 - assign $2\data_r0__o_ok$next[0:0]$12640 $1\data_r0__o_ok$next[0:0]$12638 + assign $2\data_r0__o$next[63:0]$12623 $1\data_r0__o$next[63:0]$12621 + assign $2\data_r0__o_ok$next[0:0]$12624 $1\data_r0__o_ok$next[0:0]$12622 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$12641 1'0 + assign $3\data_r0__o_ok$next[0:0]$12625 1'0 case - assign $3\data_r0__o_ok$next[0:0]$12641 $2\data_r0__o_ok$next[0:0]$12640 + assign $3\data_r0__o_ok$next[0:0]$12625 $2\data_r0__o_ok$next[0:0]$12624 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$12635 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12636 + update \data_r0__o$next $0\data_r0__o$next[63:0]$12619 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12620 end - attribute \src "libresoc.v:187900.3-187921.6" - process $proc$libresoc.v:187900$12642 + attribute \src "libresoc.v:189217.3-189238.6" + process $proc$libresoc.v:189217$12626 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__cr_a$next[3:0]$12643 $2\data_r1__cr_a$next[3:0]$12647 + assign $0\data_r1__cr_a$next[3:0]$12627 $2\data_r1__cr_a$next[3:0]$12631 assign { } { } - assign $0\data_r1__cr_a_ok$next[0:0]$12644 $3\data_r1__cr_a_ok$next[0:0]$12649 - attribute \src "libresoc.v:187901.5-187901.29" + assign $0\data_r1__cr_a_ok$next[0:0]$12628 $3\data_r1__cr_a_ok$next[0:0]$12633 + attribute \src "libresoc.v:189218.5-189218.29" switch \initial - attribute \src "libresoc.v:187901.9-187901.17" + attribute \src "libresoc.v:189218.9-189218.17" case 1'1 case end @@ -387588,10 +358967,10 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__cr_a_ok$next[0:0]$12646 $1\data_r1__cr_a$next[3:0]$12645 } { \cr_a_ok \alu_shift_rot0_cr_a } + assign { $1\data_r1__cr_a_ok$next[0:0]$12630 $1\data_r1__cr_a$next[3:0]$12629 } { \cr_a_ok \alu_shift_rot0_cr_a } case - assign $1\data_r1__cr_a$next[3:0]$12645 \data_r1__cr_a - assign $1\data_r1__cr_a_ok$next[0:0]$12646 \data_r1__cr_a_ok + assign $1\data_r1__cr_a$next[3:0]$12629 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$12630 \data_r1__cr_a_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -387599,38 +358978,38 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__cr_a_ok$next[0:0]$12648 $2\data_r1__cr_a$next[3:0]$12647 } 5'00000 + assign { $2\data_r1__cr_a_ok$next[0:0]$12632 $2\data_r1__cr_a$next[3:0]$12631 } 5'00000 case - assign $2\data_r1__cr_a$next[3:0]$12647 $1\data_r1__cr_a$next[3:0]$12645 - assign $2\data_r1__cr_a_ok$next[0:0]$12648 $1\data_r1__cr_a_ok$next[0:0]$12646 + assign $2\data_r1__cr_a$next[3:0]$12631 $1\data_r1__cr_a$next[3:0]$12629 + assign $2\data_r1__cr_a_ok$next[0:0]$12632 $1\data_r1__cr_a_ok$next[0:0]$12630 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__cr_a_ok$next[0:0]$12649 1'0 + assign $3\data_r1__cr_a_ok$next[0:0]$12633 1'0 case - assign $3\data_r1__cr_a_ok$next[0:0]$12649 $2\data_r1__cr_a_ok$next[0:0]$12648 + assign $3\data_r1__cr_a_ok$next[0:0]$12633 $2\data_r1__cr_a_ok$next[0:0]$12632 end sync always - update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$12643 - update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$12644 + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$12627 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$12628 end - attribute \src "libresoc.v:187922.3-187943.6" - process $proc$libresoc.v:187922$12650 + attribute \src "libresoc.v:189239.3-189260.6" + process $proc$libresoc.v:189239$12634 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__xer_ca$next[1:0]$12651 $2\data_r2__xer_ca$next[1:0]$12655 + assign $0\data_r2__xer_ca$next[1:0]$12635 $2\data_r2__xer_ca$next[1:0]$12639 assign { } { } - assign $0\data_r2__xer_ca_ok$next[0:0]$12652 $3\data_r2__xer_ca_ok$next[0:0]$12657 - attribute \src "libresoc.v:187923.5-187923.29" + assign $0\data_r2__xer_ca_ok$next[0:0]$12636 $3\data_r2__xer_ca_ok$next[0:0]$12641 + attribute \src "libresoc.v:189240.5-189240.29" switch \initial - attribute \src "libresoc.v:187923.9-187923.17" + attribute \src "libresoc.v:189240.9-189240.17" case 1'1 case end @@ -387640,10 +359019,10 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__xer_ca_ok$next[0:0]$12654 $1\data_r2__xer_ca$next[1:0]$12653 } { \xer_ca_ok \alu_shift_rot0_xer_ca } + assign { $1\data_r2__xer_ca_ok$next[0:0]$12638 $1\data_r2__xer_ca$next[1:0]$12637 } { \xer_ca_ok \alu_shift_rot0_xer_ca } case - assign $1\data_r2__xer_ca$next[1:0]$12653 \data_r2__xer_ca - assign $1\data_r2__xer_ca_ok$next[0:0]$12654 \data_r2__xer_ca_ok + assign $1\data_r2__xer_ca$next[1:0]$12637 \data_r2__xer_ca + assign $1\data_r2__xer_ca_ok$next[0:0]$12638 \data_r2__xer_ca_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -387651,32 +359030,32 @@ module \shiftrot0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__xer_ca_ok$next[0:0]$12656 $2\data_r2__xer_ca$next[1:0]$12655 } 3'000 + assign { $2\data_r2__xer_ca_ok$next[0:0]$12640 $2\data_r2__xer_ca$next[1:0]$12639 } 3'000 case - assign $2\data_r2__xer_ca$next[1:0]$12655 $1\data_r2__xer_ca$next[1:0]$12653 - assign $2\data_r2__xer_ca_ok$next[0:0]$12656 $1\data_r2__xer_ca_ok$next[0:0]$12654 + assign $2\data_r2__xer_ca$next[1:0]$12639 $1\data_r2__xer_ca$next[1:0]$12637 + assign $2\data_r2__xer_ca_ok$next[0:0]$12640 $1\data_r2__xer_ca_ok$next[0:0]$12638 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__xer_ca_ok$next[0:0]$12657 1'0 + assign $3\data_r2__xer_ca_ok$next[0:0]$12641 1'0 case - assign $3\data_r2__xer_ca_ok$next[0:0]$12657 $2\data_r2__xer_ca_ok$next[0:0]$12656 + assign $3\data_r2__xer_ca_ok$next[0:0]$12641 $2\data_r2__xer_ca_ok$next[0:0]$12640 end sync always - update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$12651 - update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$12652 + update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$12635 + update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$12636 end - attribute \src "libresoc.v:187944.3-187953.6" - process $proc$libresoc.v:187944$12658 + attribute \src "libresoc.v:189261.3-189270.6" + process $proc$libresoc.v:189261$12642 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$12659 $1\src_r0$next[63:0]$12660 - attribute \src "libresoc.v:187945.5-187945.29" + assign $0\src_r0$next[63:0]$12643 $1\src_r0$next[63:0]$12644 + attribute \src "libresoc.v:189262.5-189262.29" switch \initial - attribute \src "libresoc.v:187945.9-187945.17" + attribute \src "libresoc.v:189262.9-189262.17" case 1'1 case end @@ -387685,21 +359064,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$12660 \src1_i + assign $1\src_r0$next[63:0]$12644 \src1_i case - assign $1\src_r0$next[63:0]$12660 \src_r0 + assign $1\src_r0$next[63:0]$12644 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$12659 + update \src_r0$next $0\src_r0$next[63:0]$12643 end - attribute \src "libresoc.v:187954.3-187963.6" - process $proc$libresoc.v:187954$12661 + attribute \src "libresoc.v:189271.3-189280.6" + process $proc$libresoc.v:189271$12645 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$12662 $1\src_r1$next[63:0]$12663 - attribute \src "libresoc.v:187955.5-187955.29" + assign $0\src_r1$next[63:0]$12646 $1\src_r1$next[63:0]$12647 + attribute \src "libresoc.v:189272.5-189272.29" switch \initial - attribute \src "libresoc.v:187955.9-187955.17" + attribute \src "libresoc.v:189272.9-189272.17" case 1'1 case end @@ -387708,21 +359087,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$12663 \src_or_imm + assign $1\src_r1$next[63:0]$12647 \src_or_imm case - assign $1\src_r1$next[63:0]$12663 \src_r1 + assign $1\src_r1$next[63:0]$12647 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$12662 + update \src_r1$next $0\src_r1$next[63:0]$12646 end - attribute \src "libresoc.v:187964.3-187973.6" - process $proc$libresoc.v:187964$12664 + attribute \src "libresoc.v:189281.3-189290.6" + process $proc$libresoc.v:189281$12648 assign { } { } assign { } { } - assign $0\src_r2$next[63:0]$12665 $1\src_r2$next[63:0]$12666 - attribute \src "libresoc.v:187965.5-187965.29" + assign $0\src_r2$next[63:0]$12649 $1\src_r2$next[63:0]$12650 + attribute \src "libresoc.v:189282.5-189282.29" switch \initial - attribute \src "libresoc.v:187965.9-187965.17" + attribute \src "libresoc.v:189282.9-189282.17" case 1'1 case end @@ -387731,21 +359110,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[63:0]$12666 \src3_i + assign $1\src_r2$next[63:0]$12650 \src3_i case - assign $1\src_r2$next[63:0]$12666 \src_r2 + assign $1\src_r2$next[63:0]$12650 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[63:0]$12665 + update \src_r2$next $0\src_r2$next[63:0]$12649 end - attribute \src "libresoc.v:187974.3-187983.6" - process $proc$libresoc.v:187974$12667 + attribute \src "libresoc.v:189291.3-189300.6" + process $proc$libresoc.v:189291$12651 assign { } { } assign { } { } - assign $0\src_r3$next[0:0]$12668 $1\src_r3$next[0:0]$12669 - attribute \src "libresoc.v:187975.5-187975.29" + assign $0\src_r3$next[0:0]$12652 $1\src_r3$next[0:0]$12653 + attribute \src "libresoc.v:189292.5-189292.29" switch \initial - attribute \src "libresoc.v:187975.9-187975.17" + attribute \src "libresoc.v:189292.9-189292.17" case 1'1 case end @@ -387754,21 +359133,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r3$next[0:0]$12669 \src4_i + assign $1\src_r3$next[0:0]$12653 \src4_i case - assign $1\src_r3$next[0:0]$12669 \src_r3 + assign $1\src_r3$next[0:0]$12653 \src_r3 end sync always - update \src_r3$next $0\src_r3$next[0:0]$12668 + update \src_r3$next $0\src_r3$next[0:0]$12652 end - attribute \src "libresoc.v:187984.3-187993.6" - process $proc$libresoc.v:187984$12670 + attribute \src "libresoc.v:189301.3-189310.6" + process $proc$libresoc.v:189301$12654 assign { } { } assign { } { } - assign $0\src_r4$next[1:0]$12671 $1\src_r4$next[1:0]$12672 - attribute \src "libresoc.v:187985.5-187985.29" + assign $0\src_r4$next[1:0]$12655 $1\src_r4$next[1:0]$12656 + attribute \src "libresoc.v:189302.5-189302.29" switch \initial - attribute \src "libresoc.v:187985.9-187985.17" + attribute \src "libresoc.v:189302.9-189302.17" case 1'1 case end @@ -387777,21 +359156,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r4$next[1:0]$12672 \src5_i + assign $1\src_r4$next[1:0]$12656 \src5_i case - assign $1\src_r4$next[1:0]$12672 \src_r4 + assign $1\src_r4$next[1:0]$12656 \src_r4 end sync always - update \src_r4$next $0\src_r4$next[1:0]$12671 + update \src_r4$next $0\src_r4$next[1:0]$12655 end - attribute \src "libresoc.v:187994.3-188002.6" - process $proc$libresoc.v:187994$12673 + attribute \src "libresoc.v:189311.3-189319.6" + process $proc$libresoc.v:189311$12657 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$12674 $1\alui_l_r_alui$next[0:0]$12675 - attribute \src "libresoc.v:187995.5-187995.29" + assign $0\alui_l_r_alui$next[0:0]$12658 $1\alui_l_r_alui$next[0:0]$12659 + attribute \src "libresoc.v:189312.5-189312.29" switch \initial - attribute \src "libresoc.v:187995.9-187995.17" + attribute \src "libresoc.v:189312.9-189312.17" case 1'1 case end @@ -387800,21 +359179,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$12675 1'1 + assign $1\alui_l_r_alui$next[0:0]$12659 1'1 case - assign $1\alui_l_r_alui$next[0:0]$12675 \$90 + assign $1\alui_l_r_alui$next[0:0]$12659 \$90 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12674 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12658 end - attribute \src "libresoc.v:188003.3-188011.6" - process $proc$libresoc.v:188003$12676 + attribute \src "libresoc.v:189320.3-189328.6" + process $proc$libresoc.v:189320$12660 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$12677 $1\alu_l_r_alu$next[0:0]$12678 - attribute \src "libresoc.v:188004.5-188004.29" + assign $0\alu_l_r_alu$next[0:0]$12661 $1\alu_l_r_alu$next[0:0]$12662 + attribute \src "libresoc.v:189321.5-189321.29" switch \initial - attribute \src "libresoc.v:188004.9-188004.17" + attribute \src "libresoc.v:189321.9-189321.17" case 1'1 case end @@ -387823,21 +359202,21 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$12678 1'1 + assign $1\alu_l_r_alu$next[0:0]$12662 1'1 case - assign $1\alu_l_r_alu$next[0:0]$12678 \$92 + assign $1\alu_l_r_alu$next[0:0]$12662 \$92 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12677 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12661 end - attribute \src "libresoc.v:188012.3-188021.6" - process $proc$libresoc.v:188012$12679 + attribute \src "libresoc.v:189329.3-189338.6" + process $proc$libresoc.v:189329$12663 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:188013.5-188013.29" + attribute \src "libresoc.v:189330.5-189330.29" switch \initial - attribute \src "libresoc.v:188013.9-188013.17" + attribute \src "libresoc.v:189330.9-189330.17" case 1'1 case end @@ -387853,14 +359232,14 @@ module \shiftrot0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:188022.3-188031.6" - process $proc$libresoc.v:188022$12680 + attribute \src "libresoc.v:189339.3-189348.6" + process $proc$libresoc.v:189339$12664 assign { } { } assign { } { } assign $0\dest2_o[3:0] $1\dest2_o[3:0] - attribute \src "libresoc.v:188023.5-188023.29" + attribute \src "libresoc.v:189340.5-189340.29" switch \initial - attribute \src "libresoc.v:188023.9-188023.17" + attribute \src "libresoc.v:189340.9-189340.17" case 1'1 case end @@ -387876,14 +359255,14 @@ module \shiftrot0 sync always update \dest2_o $0\dest2_o[3:0] end - attribute \src "libresoc.v:188032.3-188041.6" - process $proc$libresoc.v:188032$12681 + attribute \src "libresoc.v:189349.3-189358.6" + process $proc$libresoc.v:189349$12665 assign { } { } assign { } { } assign $0\dest3_o[1:0] $1\dest3_o[1:0] - attribute \src "libresoc.v:188033.5-188033.29" + attribute \src "libresoc.v:189350.5-189350.29" switch \initial - attribute \src "libresoc.v:188033.9-188033.17" + attribute \src "libresoc.v:189350.9-189350.17" case 1'1 case end @@ -387899,14 +359278,14 @@ module \shiftrot0 sync always update \dest3_o $0\dest3_o[1:0] end - attribute \src "libresoc.v:188042.3-188050.6" - process $proc$libresoc.v:188042$12682 + attribute \src "libresoc.v:189359.3-189367.6" + process $proc$libresoc.v:189359$12666 assign { } { } assign { } { } - assign $0\prev_wr_go$next[2:0]$12683 $1\prev_wr_go$next[2:0]$12684 - attribute \src "libresoc.v:188043.5-188043.29" + assign $0\prev_wr_go$next[2:0]$12667 $1\prev_wr_go$next[2:0]$12668 + attribute \src "libresoc.v:189360.5-189360.29" switch \initial - attribute \src "libresoc.v:188043.9-188043.17" + attribute \src "libresoc.v:189360.9-189360.17" case 1'1 case end @@ -387915,72 +359294,72 @@ module \shiftrot0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[2:0]$12684 3'000 - case - assign $1\prev_wr_go$next[2:0]$12684 \$20 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[2:0]$12683 - end - connect \$100 $not$libresoc.v:187511$12460_Y - connect \$102 $and$libresoc.v:187512$12461_Y - connect \$104 $and$libresoc.v:187513$12462_Y - connect \$106 $and$libresoc.v:187514$12463_Y - connect \$108 $and$libresoc.v:187515$12464_Y - connect \$10 $and$libresoc.v:187516$12465_Y - connect \$110 $and$libresoc.v:187517$12466_Y - connect \$112 $and$libresoc.v:187518$12467_Y - connect \$114 $and$libresoc.v:187519$12468_Y - connect \$116 $and$libresoc.v:187520$12469_Y - connect \$118 $and$libresoc.v:187521$12470_Y - connect \$12 $not$libresoc.v:187522$12471_Y - connect \$14 $and$libresoc.v:187523$12472_Y - connect \$16 $not$libresoc.v:187524$12473_Y - connect \$18 $and$libresoc.v:187525$12474_Y - connect \$20 $and$libresoc.v:187526$12475_Y - connect \$24 $not$libresoc.v:187527$12476_Y - connect \$26 $and$libresoc.v:187528$12477_Y - connect \$23 $reduce_or$libresoc.v:187529$12478_Y - connect \$22 $not$libresoc.v:187530$12479_Y - connect \$2 $and$libresoc.v:187531$12480_Y - connect \$30 $and$libresoc.v:187532$12481_Y - connect \$32 $reduce_or$libresoc.v:187533$12482_Y - connect \$34 $reduce_or$libresoc.v:187534$12483_Y - connect \$36 $or$libresoc.v:187535$12484_Y - connect \$38 $not$libresoc.v:187536$12485_Y - connect \$40 $and$libresoc.v:187537$12486_Y - connect \$42 $and$libresoc.v:187538$12487_Y - connect \$44 $eq$libresoc.v:187539$12488_Y - connect \$46 $and$libresoc.v:187540$12489_Y - connect \$48 $eq$libresoc.v:187541$12490_Y - connect \$50 $and$libresoc.v:187542$12491_Y - connect \$52 $and$libresoc.v:187543$12492_Y - connect \$54 $and$libresoc.v:187544$12493_Y - connect \$56 $or$libresoc.v:187545$12494_Y - connect \$58 $or$libresoc.v:187546$12495_Y - connect \$5 $not$libresoc.v:187547$12496_Y - connect \$60 $or$libresoc.v:187548$12497_Y - connect \$62 $or$libresoc.v:187549$12498_Y - connect \$64 $and$libresoc.v:187550$12499_Y - connect \$66 $and$libresoc.v:187551$12500_Y - connect \$68 $or$libresoc.v:187552$12501_Y - connect \$70 $and$libresoc.v:187553$12502_Y - connect \$72 $and$libresoc.v:187554$12503_Y - connect \$74 $and$libresoc.v:187555$12504_Y - connect \$76 $ternary$libresoc.v:187556$12505_Y - connect \$78 $ternary$libresoc.v:187557$12506_Y - connect \$7 $or$libresoc.v:187558$12507_Y - connect \$80 $ternary$libresoc.v:187559$12508_Y - connect \$82 $ternary$libresoc.v:187560$12509_Y - connect \$84 $ternary$libresoc.v:187561$12510_Y - connect \$86 $ternary$libresoc.v:187562$12511_Y - connect \$88 $ternary$libresoc.v:187563$12512_Y - connect \$4 $reduce_and$libresoc.v:187564$12513_Y - connect \$90 $and$libresoc.v:187565$12514_Y - connect \$92 $and$libresoc.v:187566$12515_Y - connect \$94 $and$libresoc.v:187567$12516_Y - connect \$96 $not$libresoc.v:187568$12517_Y - connect \$98 $and$libresoc.v:187569$12518_Y + assign $1\prev_wr_go$next[2:0]$12668 3'000 + case + assign $1\prev_wr_go$next[2:0]$12668 \$20 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[2:0]$12667 + end + connect \$100 $not$libresoc.v:188828$12444_Y + connect \$102 $and$libresoc.v:188829$12445_Y + connect \$104 $and$libresoc.v:188830$12446_Y + connect \$106 $and$libresoc.v:188831$12447_Y + connect \$108 $and$libresoc.v:188832$12448_Y + connect \$10 $and$libresoc.v:188833$12449_Y + connect \$110 $and$libresoc.v:188834$12450_Y + connect \$112 $and$libresoc.v:188835$12451_Y + connect \$114 $and$libresoc.v:188836$12452_Y + connect \$116 $and$libresoc.v:188837$12453_Y + connect \$118 $and$libresoc.v:188838$12454_Y + connect \$12 $not$libresoc.v:188839$12455_Y + connect \$14 $and$libresoc.v:188840$12456_Y + connect \$16 $not$libresoc.v:188841$12457_Y + connect \$18 $and$libresoc.v:188842$12458_Y + connect \$20 $and$libresoc.v:188843$12459_Y + connect \$24 $not$libresoc.v:188844$12460_Y + connect \$26 $and$libresoc.v:188845$12461_Y + connect \$23 $reduce_or$libresoc.v:188846$12462_Y + connect \$22 $not$libresoc.v:188847$12463_Y + connect \$2 $and$libresoc.v:188848$12464_Y + connect \$30 $and$libresoc.v:188849$12465_Y + connect \$32 $reduce_or$libresoc.v:188850$12466_Y + connect \$34 $reduce_or$libresoc.v:188851$12467_Y + connect \$36 $or$libresoc.v:188852$12468_Y + connect \$38 $not$libresoc.v:188853$12469_Y + connect \$40 $and$libresoc.v:188854$12470_Y + connect \$42 $and$libresoc.v:188855$12471_Y + connect \$44 $eq$libresoc.v:188856$12472_Y + connect \$46 $and$libresoc.v:188857$12473_Y + connect \$48 $eq$libresoc.v:188858$12474_Y + connect \$50 $and$libresoc.v:188859$12475_Y + connect \$52 $and$libresoc.v:188860$12476_Y + connect \$54 $and$libresoc.v:188861$12477_Y + connect \$56 $or$libresoc.v:188862$12478_Y + connect \$58 $or$libresoc.v:188863$12479_Y + connect \$5 $not$libresoc.v:188864$12480_Y + connect \$60 $or$libresoc.v:188865$12481_Y + connect \$62 $or$libresoc.v:188866$12482_Y + connect \$64 $and$libresoc.v:188867$12483_Y + connect \$66 $and$libresoc.v:188868$12484_Y + connect \$68 $or$libresoc.v:188869$12485_Y + connect \$70 $and$libresoc.v:188870$12486_Y + connect \$72 $and$libresoc.v:188871$12487_Y + connect \$74 $and$libresoc.v:188872$12488_Y + connect \$76 $ternary$libresoc.v:188873$12489_Y + connect \$78 $ternary$libresoc.v:188874$12490_Y + connect \$7 $or$libresoc.v:188875$12491_Y + connect \$80 $ternary$libresoc.v:188876$12492_Y + connect \$82 $ternary$libresoc.v:188877$12493_Y + connect \$84 $ternary$libresoc.v:188878$12494_Y + connect \$86 $ternary$libresoc.v:188879$12495_Y + connect \$88 $ternary$libresoc.v:188880$12496_Y + connect \$4 $reduce_and$libresoc.v:188881$12497_Y + connect \$90 $and$libresoc.v:188882$12498_Y + connect \$92 $and$libresoc.v:188883$12499_Y + connect \$94 $and$libresoc.v:188884$12500_Y + connect \$96 $not$libresoc.v:188885$12501_Y + connect \$98 $and$libresoc.v:188886$12502_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$112 @@ -388014,48 +359393,54 @@ module \shiftrot0 connect \all_rd_dly$next \all_rd connect \all_rd \$10 end -attribute \src "libresoc.v:188087.1-188267.10" +attribute \src "libresoc.v:189404.1-189584.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.spr" attribute \generator "nMigen" module \spr - attribute \src "libresoc.v:188239.3-188242.6" - wire width 7 $0$memwr$\memory$libresoc.v:188241$12842_ADDR[6:0]$12845 - attribute \src "libresoc.v:188239.3-188242.6" - wire width 64 $0$memwr$\memory$libresoc.v:188241$12842_DATA[63:0]$12846 - attribute \src "libresoc.v:188239.3-188242.6" - wire width 64 $0$memwr$\memory$libresoc.v:188241$12842_EN[63:0]$12847 - attribute \src "libresoc.v:188239.3-188242.6" + attribute \src "libresoc.v:189554.3-189557.6" + wire width 7 $0$memwr$\memory$libresoc.v:189556$12826_ADDR[6:0]$12828 + attribute \src "libresoc.v:189554.3-189557.6" + wire width 64 $0$memwr$\memory$libresoc.v:189556$12826_DATA[63:0]$12829 + attribute \src "libresoc.v:189554.3-189557.6" + wire width 64 $0$memwr$\memory$libresoc.v:189556$12826_EN[63:0]$12830 + attribute \src "libresoc.v:189554.3-189557.6" wire width 7 $0\_0_[6:0] - attribute \src "libresoc.v:188088.7-188088.20" + attribute \src "libresoc.v:189405.7-189405.20" wire $0\initial[0:0] - attribute \src "libresoc.v:188244.3-188252.6" - wire $0\ren_delay$next[0:0]$12850 - attribute \src "libresoc.v:188120.3-188121.35" + attribute \src "libresoc.v:189561.3-189569.6" + wire $0\ren_delay$next[0:0]$12837 + attribute \src "libresoc.v:189559.3-189560.35" wire $0\ren_delay[0:0] - attribute \src "libresoc.v:188253.3-188262.6" + attribute \src "libresoc.v:189570.3-189579.6" wire width 64 $0\spr1__data_o[63:0] - attribute \src "libresoc.v:188244.3-188252.6" - wire $1\ren_delay$next[0:0]$12851 - attribute \src "libresoc.v:188104.7-188104.23" + attribute \src "libresoc.v:189554.3-189557.6" + wire width 7 $1$memwr$\memory$libresoc.v:189556$12826_ADDR[6:0]$12831 + attribute \src "libresoc.v:189554.3-189557.6" + wire width 64 $1$memwr$\memory$libresoc.v:189556$12826_DATA[63:0]$12832 + attribute \src "libresoc.v:189554.3-189557.6" + wire width 64 $1$memwr$\memory$libresoc.v:189556$12826_EN[63:0]$12833 + attribute \src "libresoc.v:189561.3-189569.6" + wire $1\ren_delay$next[0:0]$12838 + attribute \src "libresoc.v:189421.7-189421.23" wire $1\ren_delay[0:0] - attribute \src "libresoc.v:188253.3-188262.6" + attribute \src "libresoc.v:189570.3-189579.6" wire width 64 $1\spr1__data_o[63:0] - attribute \src "libresoc.v:188243.26-188243.32" - wire width 64 $memrd$\memory$libresoc.v:188243$12848_DATA + attribute \src "libresoc.v:189558.26-189558.32" + wire width 64 $memrd$\memory$libresoc.v:189558$12834_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 7 $memwr$\memory$libresoc.v:188241$12842_ADDR + wire width 7 $memwr$\memory$libresoc.v:189556$12826_ADDR attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:188241$12842_DATA + wire width 64 $memwr$\memory$libresoc.v:189556$12826_DATA attribute \src "libresoc.v:0.0-0.0" - wire width 64 $memwr$\memory$libresoc.v:188241$12842_EN - attribute \src "libresoc.v:188238.13-188238.16" + wire width 64 $memwr$\memory$libresoc.v:189556$12826_EN + attribute \src "libresoc.v:189553.13-189553.16" wire width 7 \_0_ - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 8 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:188088.7-188088.15" + attribute \src "libresoc.v:189405.7-189405.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" wire width 7 \memory_r_addr @@ -388083,1140 +359468,1140 @@ module \spr wire input 4 \spr1__ren attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire input 7 \spr1__wen - attribute \src "libresoc.v:188122.14-188122.20" + attribute \src "libresoc.v:189437.14-189437.20" memory width 64 size 113 \memory - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12853 + attribute \src "libresoc.v:189439.5-189439.37" + cell $meminit $meminit$\memory$libresoc.v:189439$12840 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12853 + parameter \PRIORITY 12840 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 0 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12854 + attribute \src "libresoc.v:189440.5-189440.37" + cell $meminit $meminit$\memory$libresoc.v:189440$12841 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12854 + parameter \PRIORITY 12841 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 1 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12855 + attribute \src "libresoc.v:189441.5-189441.37" + cell $meminit $meminit$\memory$libresoc.v:189441$12842 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12855 + parameter \PRIORITY 12842 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 2 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12856 + attribute \src "libresoc.v:189442.5-189442.37" + cell $meminit $meminit$\memory$libresoc.v:189442$12843 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12856 + parameter \PRIORITY 12843 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 3 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12857 + attribute \src "libresoc.v:189443.5-189443.37" + cell $meminit $meminit$\memory$libresoc.v:189443$12844 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12857 + parameter \PRIORITY 12844 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 4 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12858 + attribute \src "libresoc.v:189444.5-189444.37" + cell $meminit $meminit$\memory$libresoc.v:189444$12845 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12858 + parameter \PRIORITY 12845 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 5 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12859 + attribute \src "libresoc.v:189445.5-189445.37" + cell $meminit $meminit$\memory$libresoc.v:189445$12846 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12859 + parameter \PRIORITY 12846 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 6 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12860 + attribute \src "libresoc.v:189446.5-189446.37" + cell $meminit $meminit$\memory$libresoc.v:189446$12847 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12860 + parameter \PRIORITY 12847 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 7 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12861 + attribute \src "libresoc.v:189447.5-189447.37" + cell $meminit $meminit$\memory$libresoc.v:189447$12848 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12861 + parameter \PRIORITY 12848 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 8 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12862 + attribute \src "libresoc.v:189448.5-189448.37" + cell $meminit $meminit$\memory$libresoc.v:189448$12849 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12862 + parameter \PRIORITY 12849 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 9 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12863 + attribute \src "libresoc.v:189449.5-189449.38" + cell $meminit $meminit$\memory$libresoc.v:189449$12850 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12863 + parameter \PRIORITY 12850 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 10 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12864 + attribute \src "libresoc.v:189450.5-189450.38" + cell $meminit $meminit$\memory$libresoc.v:189450$12851 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12864 + parameter \PRIORITY 12851 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 11 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12865 + attribute \src "libresoc.v:189451.5-189451.38" + cell $meminit $meminit$\memory$libresoc.v:189451$12852 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12865 + parameter \PRIORITY 12852 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 12 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12866 + attribute \src "libresoc.v:189452.5-189452.38" + cell $meminit $meminit$\memory$libresoc.v:189452$12853 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12866 + parameter \PRIORITY 12853 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 13 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12867 + attribute \src "libresoc.v:189453.5-189453.38" + cell $meminit $meminit$\memory$libresoc.v:189453$12854 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12867 + parameter \PRIORITY 12854 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 14 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12868 + attribute \src "libresoc.v:189454.5-189454.38" + cell $meminit $meminit$\memory$libresoc.v:189454$12855 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12868 + parameter \PRIORITY 12855 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 15 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12869 + attribute \src "libresoc.v:189455.5-189455.38" + cell $meminit $meminit$\memory$libresoc.v:189455$12856 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12869 + parameter \PRIORITY 12856 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 16 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12870 + attribute \src "libresoc.v:189456.5-189456.38" + cell $meminit $meminit$\memory$libresoc.v:189456$12857 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12870 + parameter \PRIORITY 12857 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 17 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12871 + attribute \src "libresoc.v:189457.5-189457.38" + cell $meminit $meminit$\memory$libresoc.v:189457$12858 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12871 + parameter \PRIORITY 12858 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 18 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12872 + attribute \src "libresoc.v:189458.5-189458.38" + cell $meminit $meminit$\memory$libresoc.v:189458$12859 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12872 + parameter \PRIORITY 12859 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 19 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12873 + attribute \src "libresoc.v:189459.5-189459.38" + cell $meminit $meminit$\memory$libresoc.v:189459$12860 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12873 + parameter \PRIORITY 12860 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 20 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12874 + attribute \src "libresoc.v:189460.5-189460.38" + cell $meminit $meminit$\memory$libresoc.v:189460$12861 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12874 + parameter \PRIORITY 12861 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 21 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12875 + attribute \src "libresoc.v:189461.5-189461.38" + cell $meminit $meminit$\memory$libresoc.v:189461$12862 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12875 + parameter \PRIORITY 12862 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 22 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12876 + attribute \src "libresoc.v:189462.5-189462.38" + cell $meminit $meminit$\memory$libresoc.v:189462$12863 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12876 + parameter \PRIORITY 12863 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 23 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12877 + attribute \src "libresoc.v:189463.5-189463.38" + cell $meminit $meminit$\memory$libresoc.v:189463$12864 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12877 + parameter \PRIORITY 12864 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 24 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12878 + attribute \src "libresoc.v:189464.5-189464.38" + cell $meminit $meminit$\memory$libresoc.v:189464$12865 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12878 + parameter \PRIORITY 12865 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 25 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12879 + attribute \src "libresoc.v:189465.5-189465.38" + cell $meminit $meminit$\memory$libresoc.v:189465$12866 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12879 + parameter \PRIORITY 12866 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 26 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12880 + attribute \src "libresoc.v:189466.5-189466.38" + cell $meminit $meminit$\memory$libresoc.v:189466$12867 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12880 + parameter \PRIORITY 12867 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 27 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12881 + attribute \src "libresoc.v:189467.5-189467.38" + cell $meminit $meminit$\memory$libresoc.v:189467$12868 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12881 + parameter \PRIORITY 12868 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 28 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12882 + attribute \src "libresoc.v:189468.5-189468.38" + cell $meminit $meminit$\memory$libresoc.v:189468$12869 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12882 + parameter \PRIORITY 12869 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 29 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12883 + attribute \src "libresoc.v:189469.5-189469.38" + cell $meminit $meminit$\memory$libresoc.v:189469$12870 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12883 + parameter \PRIORITY 12870 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 30 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12884 + attribute \src "libresoc.v:189470.5-189470.38" + cell $meminit $meminit$\memory$libresoc.v:189470$12871 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12884 + parameter \PRIORITY 12871 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 31 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12885 + attribute \src "libresoc.v:189471.5-189471.38" + cell $meminit $meminit$\memory$libresoc.v:189471$12872 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12885 + parameter \PRIORITY 12872 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 32 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12886 + attribute \src "libresoc.v:189472.5-189472.38" + cell $meminit $meminit$\memory$libresoc.v:189472$12873 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12886 + parameter \PRIORITY 12873 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 33 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12887 + attribute \src "libresoc.v:189473.5-189473.38" + cell $meminit $meminit$\memory$libresoc.v:189473$12874 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12887 + parameter \PRIORITY 12874 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 34 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12888 + attribute \src "libresoc.v:189474.5-189474.38" + cell $meminit $meminit$\memory$libresoc.v:189474$12875 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12888 + parameter \PRIORITY 12875 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 35 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12889 + attribute \src "libresoc.v:189475.5-189475.38" + cell $meminit $meminit$\memory$libresoc.v:189475$12876 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12889 + parameter \PRIORITY 12876 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 36 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12890 + attribute \src "libresoc.v:189476.5-189476.38" + cell $meminit $meminit$\memory$libresoc.v:189476$12877 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12890 + parameter \PRIORITY 12877 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 37 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12891 + attribute \src "libresoc.v:189477.5-189477.38" + cell $meminit $meminit$\memory$libresoc.v:189477$12878 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12891 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64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12894 + attribute \src "libresoc.v:189480.5-189480.38" + cell $meminit $meminit$\memory$libresoc.v:189480$12881 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12894 + parameter \PRIORITY 12881 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 41 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12895 + attribute \src "libresoc.v:189481.5-189481.38" + cell $meminit $meminit$\memory$libresoc.v:189481$12882 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12895 + parameter \PRIORITY 12882 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 42 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell 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$meminit$\memory$libresoc.v:189484$12885 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12898 + parameter \PRIORITY 12885 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 45 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12899 + attribute \src "libresoc.v:189485.5-189485.38" + cell $meminit $meminit$\memory$libresoc.v:189485$12886 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12899 + parameter \PRIORITY 12886 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 46 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12900 + attribute \src "libresoc.v:189486.5-189486.38" + cell $meminit $meminit$\memory$libresoc.v:189486$12887 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12900 + parameter \PRIORITY 12887 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 47 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12901 + attribute \src "libresoc.v:189487.5-189487.38" + cell $meminit $meminit$\memory$libresoc.v:189487$12888 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12901 + parameter \PRIORITY 12888 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 48 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12902 + attribute \src "libresoc.v:189488.5-189488.38" + cell $meminit $meminit$\memory$libresoc.v:189488$12889 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12902 + parameter \PRIORITY 12889 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 49 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12903 + attribute \src "libresoc.v:189489.5-189489.38" + cell $meminit $meminit$\memory$libresoc.v:189489$12890 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12903 + parameter \PRIORITY 12890 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 50 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12904 + attribute \src "libresoc.v:189490.5-189490.38" + cell $meminit $meminit$\memory$libresoc.v:189490$12891 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12904 + parameter \PRIORITY 12891 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 51 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12905 + attribute \src "libresoc.v:189491.5-189491.38" + cell $meminit $meminit$\memory$libresoc.v:189491$12892 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12905 + parameter \PRIORITY 12892 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 52 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12906 + attribute \src "libresoc.v:189492.5-189492.38" + cell $meminit $meminit$\memory$libresoc.v:189492$12893 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12906 + parameter \PRIORITY 12893 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 53 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12907 + attribute \src "libresoc.v:189493.5-189493.38" + cell $meminit $meminit$\memory$libresoc.v:189493$12894 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12907 + parameter \PRIORITY 12894 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 54 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12908 + attribute \src "libresoc.v:189494.5-189494.38" + cell $meminit $meminit$\memory$libresoc.v:189494$12895 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12908 + parameter \PRIORITY 12895 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 55 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12909 + attribute \src "libresoc.v:189495.5-189495.38" + cell $meminit $meminit$\memory$libresoc.v:189495$12896 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12909 + parameter \PRIORITY 12896 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 56 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12910 + attribute \src "libresoc.v:189496.5-189496.38" + cell $meminit $meminit$\memory$libresoc.v:189496$12897 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12910 + parameter \PRIORITY 12897 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 57 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12911 + attribute \src "libresoc.v:189497.5-189497.38" + cell $meminit $meminit$\memory$libresoc.v:189497$12898 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12911 + parameter \PRIORITY 12898 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 58 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12912 + attribute \src "libresoc.v:189498.5-189498.38" + cell $meminit $meminit$\memory$libresoc.v:189498$12899 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12912 + parameter \PRIORITY 12899 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 59 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12913 + attribute \src "libresoc.v:189499.5-189499.38" + cell $meminit $meminit$\memory$libresoc.v:189499$12900 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12913 + parameter \PRIORITY 12900 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 60 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12914 + attribute \src "libresoc.v:189500.5-189500.38" + cell $meminit $meminit$\memory$libresoc.v:189500$12901 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12914 + parameter \PRIORITY 12901 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 61 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12915 + attribute \src "libresoc.v:189501.5-189501.38" + cell $meminit $meminit$\memory$libresoc.v:189501$12902 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12915 + parameter \PRIORITY 12902 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 62 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12916 + attribute \src "libresoc.v:189502.5-189502.38" + cell $meminit $meminit$\memory$libresoc.v:189502$12903 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12916 + parameter \PRIORITY 12903 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 63 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12917 + attribute \src "libresoc.v:189503.5-189503.38" + cell $meminit $meminit$\memory$libresoc.v:189503$12904 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12917 + parameter \PRIORITY 12904 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 64 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12918 + attribute \src "libresoc.v:189504.5-189504.38" + cell $meminit $meminit$\memory$libresoc.v:189504$12905 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12918 + parameter \PRIORITY 12905 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 65 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12919 + attribute \src "libresoc.v:189505.5-189505.38" + cell $meminit $meminit$\memory$libresoc.v:189505$12906 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12919 + parameter \PRIORITY 12906 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 66 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12920 + attribute \src "libresoc.v:189506.5-189506.38" + cell $meminit $meminit$\memory$libresoc.v:189506$12907 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12920 + parameter \PRIORITY 12907 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 67 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12921 + attribute \src "libresoc.v:189507.5-189507.38" + cell $meminit $meminit$\memory$libresoc.v:189507$12908 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12921 + parameter \PRIORITY 12908 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 68 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12922 + attribute \src "libresoc.v:189508.5-189508.38" + cell $meminit $meminit$\memory$libresoc.v:189508$12909 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12922 + parameter \PRIORITY 12909 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 69 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12923 + attribute \src "libresoc.v:189509.5-189509.38" + cell $meminit $meminit$\memory$libresoc.v:189509$12910 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12923 + parameter \PRIORITY 12910 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 70 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12924 + attribute \src "libresoc.v:189510.5-189510.38" + cell $meminit $meminit$\memory$libresoc.v:189510$12911 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12924 + parameter \PRIORITY 12911 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 71 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12925 + attribute \src "libresoc.v:189511.5-189511.38" + cell $meminit $meminit$\memory$libresoc.v:189511$12912 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12925 + parameter \PRIORITY 12912 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 72 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12926 + attribute \src "libresoc.v:189512.5-189512.38" + cell $meminit $meminit$\memory$libresoc.v:189512$12913 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12926 + parameter \PRIORITY 12913 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 73 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12927 + attribute \src "libresoc.v:189513.5-189513.38" + cell $meminit $meminit$\memory$libresoc.v:189513$12914 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12927 + parameter \PRIORITY 12914 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 74 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12928 + attribute \src "libresoc.v:189514.5-189514.38" + cell $meminit $meminit$\memory$libresoc.v:189514$12915 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12928 + parameter \PRIORITY 12915 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 75 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12929 + attribute \src "libresoc.v:189515.5-189515.38" + cell $meminit $meminit$\memory$libresoc.v:189515$12916 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12929 + parameter \PRIORITY 12916 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 76 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12930 + attribute \src "libresoc.v:189516.5-189516.38" + cell $meminit $meminit$\memory$libresoc.v:189516$12917 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12930 + parameter \PRIORITY 12917 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 77 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12931 + attribute \src "libresoc.v:189517.5-189517.38" + cell $meminit $meminit$\memory$libresoc.v:189517$12918 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12931 + parameter \PRIORITY 12918 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 78 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12932 + attribute \src "libresoc.v:189518.5-189518.38" + cell $meminit $meminit$\memory$libresoc.v:189518$12919 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12932 + parameter \PRIORITY 12919 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 79 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12933 + attribute \src "libresoc.v:189519.5-189519.38" + cell $meminit $meminit$\memory$libresoc.v:189519$12920 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12933 + parameter \PRIORITY 12920 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 80 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12934 + attribute \src "libresoc.v:189520.5-189520.38" + cell $meminit $meminit$\memory$libresoc.v:189520$12921 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12934 + parameter \PRIORITY 12921 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 81 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12935 + attribute \src "libresoc.v:189521.5-189521.38" + cell $meminit $meminit$\memory$libresoc.v:189521$12922 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12935 + parameter \PRIORITY 12922 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 82 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12936 + attribute \src "libresoc.v:189522.5-189522.38" + cell $meminit $meminit$\memory$libresoc.v:189522$12923 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12936 + parameter \PRIORITY 12923 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 83 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12937 + attribute \src "libresoc.v:189523.5-189523.38" + cell $meminit $meminit$\memory$libresoc.v:189523$12924 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12937 + parameter \PRIORITY 12924 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 84 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12938 + attribute \src "libresoc.v:189524.5-189524.38" + cell $meminit $meminit$\memory$libresoc.v:189524$12925 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12938 + parameter \PRIORITY 12925 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 85 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12939 + attribute \src "libresoc.v:189525.5-189525.38" + cell $meminit $meminit$\memory$libresoc.v:189525$12926 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12939 + parameter \PRIORITY 12926 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 86 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12940 + attribute \src "libresoc.v:189526.5-189526.38" + cell $meminit $meminit$\memory$libresoc.v:189526$12927 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12940 + parameter \PRIORITY 12927 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 87 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12941 + attribute \src "libresoc.v:189527.5-189527.38" + cell $meminit $meminit$\memory$libresoc.v:189527$12928 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12941 + parameter \PRIORITY 12928 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 88 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12942 + attribute \src "libresoc.v:189528.5-189528.38" + cell $meminit $meminit$\memory$libresoc.v:189528$12929 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12942 + parameter \PRIORITY 12929 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 89 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12943 + attribute \src "libresoc.v:189529.5-189529.38" + cell $meminit $meminit$\memory$libresoc.v:189529$12930 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12943 + parameter \PRIORITY 12930 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 90 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12944 + attribute \src "libresoc.v:189530.5-189530.38" + cell $meminit $meminit$\memory$libresoc.v:189530$12931 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12944 + parameter \PRIORITY 12931 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 91 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12945 + attribute \src "libresoc.v:189531.5-189531.38" + cell $meminit $meminit$\memory$libresoc.v:189531$12932 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12945 + parameter \PRIORITY 12932 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 92 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12946 + attribute \src "libresoc.v:189532.5-189532.38" + cell $meminit $meminit$\memory$libresoc.v:189532$12933 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12946 + parameter \PRIORITY 12933 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 93 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12947 + attribute \src "libresoc.v:189533.5-189533.38" + cell $meminit $meminit$\memory$libresoc.v:189533$12934 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12947 + parameter \PRIORITY 12934 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 94 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12948 + attribute \src "libresoc.v:189534.5-189534.38" + cell $meminit $meminit$\memory$libresoc.v:189534$12935 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12948 + parameter \PRIORITY 12935 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 95 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12949 + attribute \src "libresoc.v:189535.5-189535.38" + cell $meminit $meminit$\memory$libresoc.v:189535$12936 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12949 + parameter \PRIORITY 12936 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 96 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12950 + attribute \src "libresoc.v:189536.5-189536.38" + cell $meminit $meminit$\memory$libresoc.v:189536$12937 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12950 + parameter \PRIORITY 12937 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 97 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12951 + attribute \src "libresoc.v:189537.5-189537.38" + cell $meminit $meminit$\memory$libresoc.v:189537$12938 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12951 + parameter \PRIORITY 12938 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 98 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12952 + attribute \src "libresoc.v:189538.5-189538.38" + cell $meminit $meminit$\memory$libresoc.v:189538$12939 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12952 + parameter \PRIORITY 12939 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 99 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12953 + attribute \src "libresoc.v:189539.5-189539.39" + cell $meminit $meminit$\memory$libresoc.v:189539$12940 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12953 + parameter \PRIORITY 12940 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 100 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12954 + attribute \src "libresoc.v:189540.5-189540.39" + cell $meminit $meminit$\memory$libresoc.v:189540$12941 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12954 + parameter \PRIORITY 12941 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 101 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12955 + attribute \src "libresoc.v:189541.5-189541.39" + cell $meminit $meminit$\memory$libresoc.v:189541$12942 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12955 + parameter \PRIORITY 12942 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 102 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12956 + attribute \src "libresoc.v:189542.5-189542.39" + cell $meminit $meminit$\memory$libresoc.v:189542$12943 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12956 + parameter \PRIORITY 12943 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 103 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12957 + attribute \src "libresoc.v:189543.5-189543.39" + cell $meminit $meminit$\memory$libresoc.v:189543$12944 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12957 + parameter \PRIORITY 12944 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 104 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12958 + attribute \src "libresoc.v:189544.5-189544.39" + cell $meminit $meminit$\memory$libresoc.v:189544$12945 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12958 + parameter \PRIORITY 12945 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 105 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12959 + attribute \src "libresoc.v:189545.5-189545.39" + cell $meminit $meminit$\memory$libresoc.v:189545$12946 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12959 + parameter \PRIORITY 12946 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 106 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12960 + attribute \src "libresoc.v:189546.5-189546.39" + cell $meminit $meminit$\memory$libresoc.v:189546$12947 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12960 + parameter \PRIORITY 12947 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 107 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12961 + attribute \src "libresoc.v:189547.5-189547.39" + cell $meminit $meminit$\memory$libresoc.v:189547$12948 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12961 + parameter \PRIORITY 12948 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 108 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12962 + attribute \src "libresoc.v:189548.5-189548.39" + cell $meminit $meminit$\memory$libresoc.v:189548$12949 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12962 + parameter \PRIORITY 12949 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 109 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12963 + attribute \src "libresoc.v:189549.5-189549.39" + cell $meminit $meminit$\memory$libresoc.v:189549$12950 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12963 + parameter \PRIORITY 12950 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 110 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12964 + attribute \src "libresoc.v:189550.5-189550.39" + cell $meminit $meminit$\memory$libresoc.v:189550$12951 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12964 + parameter \PRIORITY 12951 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 111 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:0.0-0.0" - cell $meminit $meminit$\memory$libresoc.v:0$12965 + attribute \src "libresoc.v:189551.5-189551.39" + cell $meminit $meminit$\memory$libresoc.v:189551$12952 parameter \ABITS 32 parameter \MEMID "\\memory" - parameter \PRIORITY 12965 + parameter \PRIORITY 12952 parameter \WIDTH 64 parameter \WORDS 1 connect \ADDR 112 connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 end - attribute \src "libresoc.v:188243.26-188243.32" - cell $memrd $memrd$\memory$libresoc.v:188243$12848 + attribute \src "libresoc.v:189558.26-189558.32" + cell $memrd $memrd$\memory$libresoc.v:189558$12834 parameter \ABITS 7 parameter \CLK_ENABLE 0 parameter \CLK_POLARITY 0 @@ -389225,83 +360610,81 @@ module \spr parameter \WIDTH 64 connect \ADDR \_0_ connect \CLK 1'x - connect \DATA $memrd$\memory$libresoc.v:188243$12848_DATA + connect \DATA $memrd$\memory$libresoc.v:189558$12834_DATA connect \EN 1'x end attribute \src "libresoc.v:0.0-0.0" - cell $memwr $memwr$\memory$libresoc.v:0$12966 - parameter \ABITS 7 - parameter \CLK_ENABLE 0 - parameter \CLK_POLARITY 0 - parameter \MEMID "\\memory" - parameter \PRIORITY 12966 - parameter \WIDTH 64 - connect \ADDR $memwr$\memory$libresoc.v:188241$12842_ADDR - connect \CLK 1'x - connect \DATA $memwr$\memory$libresoc.v:188241$12842_DATA - connect \EN $memwr$\memory$libresoc.v:188241$12842_EN - end - attribute \src "libresoc.v:0.0-0.0" - process $proc$libresoc.v:0$12969 + process $proc$libresoc.v:0$12955 sync always sync init end - attribute \src "libresoc.v:188088.7-188088.20" - process $proc$libresoc.v:188088$12967 + attribute \src "libresoc.v:189405.7-189405.20" + process $proc$libresoc.v:189405$12953 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:188104.7-188104.23" - process $proc$libresoc.v:188104$12968 + attribute \src "libresoc.v:189421.7-189421.23" + process $proc$libresoc.v:189421$12954 assign { } { } assign $1\ren_delay[0:0] 1'0 sync always sync init update \ren_delay $1\ren_delay[0:0] end - attribute \src "libresoc.v:188120.3-188121.35" - process $proc$libresoc.v:188120$12843 + attribute \src "libresoc.v:189554.3-189557.6" + process $proc$libresoc.v:189554$12827 + assign { } { } assign { } { } - assign $0\ren_delay[0:0] \ren_delay$next - sync posedge \coresync_clk - update \ren_delay $0\ren_delay[0:0] - end - attribute \src "libresoc.v:188239.3-188242.6" - process $proc$libresoc.v:188239$12844 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0$memwr$\memory$libresoc.v:188241$12842_ADDR[6:0]$12845 7'xxxxxxx - assign $0$memwr$\memory$libresoc.v:188241$12842_DATA[63:0]$12846 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - assign $0$memwr$\memory$libresoc.v:188241$12842_EN[63:0]$12847 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $0\_0_[6:0] \spr1__addr - attribute \src "libresoc.v:188241.5-188241.59" - switch \spr1__wen - attribute \src "libresoc.v:188241.9-188241.18" + assign { } { } + assign $0\_0_[6:0] \memory_r_addr + assign $0$memwr$\memory$libresoc.v:189556$12826_ADDR[6:0]$12828 $1$memwr$\memory$libresoc.v:189556$12826_ADDR[6:0]$12831 + assign $0$memwr$\memory$libresoc.v:189556$12826_DATA[63:0]$12829 $1$memwr$\memory$libresoc.v:189556$12826_DATA[63:0]$12832 + assign $0$memwr$\memory$libresoc.v:189556$12826_EN[63:0]$12830 $1$memwr$\memory$libresoc.v:189556$12826_EN[63:0]$12833 + attribute \src "libresoc.v:189556.5-189556.61" + switch \memory_w_en + attribute \src "libresoc.v:189556.9-189556.20" case 1'1 - assign $0$memwr$\memory$libresoc.v:188241$12842_ADDR[6:0]$12845 \spr1__addr$1 - assign $0$memwr$\memory$libresoc.v:188241$12842_DATA[63:0]$12846 \spr1__data_i - assign $0$memwr$\memory$libresoc.v:188241$12842_EN[63:0]$12847 64'1111111111111111111111111111111111111111111111111111111111111111 + assign { } { } + assign { } { } + assign { } { } + assign $1$memwr$\memory$libresoc.v:189556$12826_ADDR[6:0]$12831 \memory_w_addr + assign $1$memwr$\memory$libresoc.v:189556$12826_DATA[63:0]$12832 \memory_w_data + assign $1$memwr$\memory$libresoc.v:189556$12826_EN[63:0]$12833 64'1111111111111111111111111111111111111111111111111111111111111111 case + assign $1$memwr$\memory$libresoc.v:189556$12826_ADDR[6:0]$12831 7'xxxxxxx + assign $1$memwr$\memory$libresoc.v:189556$12826_DATA[63:0]$12832 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $1$memwr$\memory$libresoc.v:189556$12826_EN[63:0]$12833 64'0000000000000000000000000000000000000000000000000000000000000000 end sync posedge \coresync_clk update \_0_ $0\_0_[6:0] - update $memwr$\memory$libresoc.v:188241$12842_ADDR $0$memwr$\memory$libresoc.v:188241$12842_ADDR[6:0]$12845 - update $memwr$\memory$libresoc.v:188241$12842_DATA $0$memwr$\memory$libresoc.v:188241$12842_DATA[63:0]$12846 - update $memwr$\memory$libresoc.v:188241$12842_EN $0$memwr$\memory$libresoc.v:188241$12842_EN[63:0]$12847 + update $memwr$\memory$libresoc.v:189556$12826_ADDR $0$memwr$\memory$libresoc.v:189556$12826_ADDR[6:0]$12828 + update $memwr$\memory$libresoc.v:189556$12826_DATA $0$memwr$\memory$libresoc.v:189556$12826_DATA[63:0]$12829 + update $memwr$\memory$libresoc.v:189556$12826_EN $0$memwr$\memory$libresoc.v:189556$12826_EN[63:0]$12830 + attribute \src "libresoc.v:189556.22-189556.60" + memwr \memory $1$memwr$\memory$libresoc.v:189556$12826_ADDR[6:0]$12831 $1$memwr$\memory$libresoc.v:189556$12826_DATA[63:0]$12832 $1$memwr$\memory$libresoc.v:189556$12826_EN[63:0]$12833 0' + end + attribute \src "libresoc.v:189559.3-189560.35" + process $proc$libresoc.v:189559$12835 + assign { } { } + assign $0\ren_delay[0:0] \ren_delay$next + sync posedge \coresync_clk + update \ren_delay $0\ren_delay[0:0] end - attribute \src "libresoc.v:188244.3-188252.6" - process $proc$libresoc.v:188244$12849 + attribute \src "libresoc.v:189561.3-189569.6" + process $proc$libresoc.v:189561$12836 assign { } { } assign { } { } - assign $0\ren_delay$next[0:0]$12850 $1\ren_delay$next[0:0]$12851 - attribute \src "libresoc.v:188245.5-188245.29" + assign $0\ren_delay$next[0:0]$12837 $1\ren_delay$next[0:0]$12838 + attribute \src "libresoc.v:189562.5-189562.29" switch \initial - attribute \src "libresoc.v:188245.9-188245.17" + attribute \src "libresoc.v:189562.9-189562.17" case 1'1 case end @@ -389310,21 +360693,21 @@ module \spr attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[0:0]$12851 1'0 + assign $1\ren_delay$next[0:0]$12838 1'0 case - assign $1\ren_delay$next[0:0]$12851 \spr1__ren + assign $1\ren_delay$next[0:0]$12838 \spr1__ren end sync always - update \ren_delay$next $0\ren_delay$next[0:0]$12850 + update \ren_delay$next $0\ren_delay$next[0:0]$12837 end - attribute \src "libresoc.v:188253.3-188262.6" - process $proc$libresoc.v:188253$12852 + attribute \src "libresoc.v:189570.3-189579.6" + process $proc$libresoc.v:189570$12839 assign { } { } assign { } { } assign $0\spr1__data_o[63:0] $1\spr1__data_o[63:0] - attribute \src "libresoc.v:188254.5-188254.29" + attribute \src "libresoc.v:189571.5-189571.29" switch \initial - attribute \src "libresoc.v:188254.9-188254.17" + attribute \src "libresoc.v:189571.9-189571.17" case 1'1 case end @@ -389340,503 +360723,503 @@ module \spr sync always update \spr1__data_o $0\spr1__data_o[63:0] end - connect \memory_r_data $memrd$\memory$libresoc.v:188243$12848_DATA + connect \memory_r_data $memrd$\memory$libresoc.v:189558$12834_DATA connect \memory_w_data \spr1__data_i connect \memory_w_en \spr1__wen connect \memory_w_addr \spr1__addr$1 connect \memory_r_addr \spr1__addr end -attribute \src "libresoc.v:188271.1-189524.10" +attribute \src "libresoc.v:189588.1-190841.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0" attribute \generator "nMigen" module \spr0 - attribute \src "libresoc.v:189021.3-189022.25" + attribute \src "libresoc.v:190338.3-190339.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:189019.3-189020.40" + attribute \src "libresoc.v:190336.3-190337.40" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:189415.3-189423.6" - wire $0\alu_l_r_alu$next[0:0]$13183 - attribute \src "libresoc.v:188949.3-188950.39" + attribute \src "libresoc.v:190732.3-190740.6" + wire $0\alu_l_r_alu$next[0:0]$13169 + attribute \src "libresoc.v:190266.3-190267.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:189201.3-189213.6" - wire width 14 $0\alu_spr0_spr_op__fn_unit$next[13:0]$13105 - attribute \src "libresoc.v:188991.3-188992.65" + attribute \src "libresoc.v:190518.3-190530.6" + wire width 14 $0\alu_spr0_spr_op__fn_unit$next[13:0]$13091 + attribute \src "libresoc.v:190308.3-190309.65" wire width 14 $0\alu_spr0_spr_op__fn_unit[13:0] - attribute \src "libresoc.v:189201.3-189213.6" - wire width 32 $0\alu_spr0_spr_op__insn$next[31:0]$13106 - attribute \src "libresoc.v:188993.3-188994.59" + attribute \src "libresoc.v:190518.3-190530.6" + wire width 32 $0\alu_spr0_spr_op__insn$next[31:0]$13092 + attribute \src "libresoc.v:190310.3-190311.59" wire width 32 $0\alu_spr0_spr_op__insn[31:0] - attribute \src "libresoc.v:189201.3-189213.6" - wire width 7 $0\alu_spr0_spr_op__insn_type$next[6:0]$13107 - attribute \src "libresoc.v:188989.3-188990.69" + attribute \src "libresoc.v:190518.3-190530.6" + wire width 7 $0\alu_spr0_spr_op__insn_type$next[6:0]$13093 + attribute \src "libresoc.v:190306.3-190307.69" wire width 7 $0\alu_spr0_spr_op__insn_type[6:0] - attribute \src "libresoc.v:189201.3-189213.6" - wire $0\alu_spr0_spr_op__is_32bit$next[0:0]$13108 - attribute \src "libresoc.v:188995.3-188996.67" + attribute \src "libresoc.v:190518.3-190530.6" + wire $0\alu_spr0_spr_op__is_32bit$next[0:0]$13094 + attribute \src "libresoc.v:190312.3-190313.67" wire $0\alu_spr0_spr_op__is_32bit[0:0] - attribute \src "libresoc.v:189406.3-189414.6" - wire $0\alui_l_r_alui$next[0:0]$13180 - attribute \src "libresoc.v:188951.3-188952.43" + attribute \src "libresoc.v:190723.3-190731.6" + wire $0\alui_l_r_alui$next[0:0]$13166 + attribute \src "libresoc.v:190268.3-190269.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:189214.3-189235.6" - wire width 64 $0\data_r0__o$next[63:0]$13114 - attribute \src "libresoc.v:188985.3-188986.37" + attribute \src "libresoc.v:190531.3-190552.6" + wire width 64 $0\data_r0__o$next[63:0]$13100 + attribute \src "libresoc.v:190302.3-190303.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:189214.3-189235.6" - wire $0\data_r0__o_ok$next[0:0]$13115 - attribute \src "libresoc.v:188987.3-188988.43" + attribute \src "libresoc.v:190531.3-190552.6" + wire $0\data_r0__o_ok$next[0:0]$13101 + attribute \src "libresoc.v:190304.3-190305.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:189236.3-189257.6" - wire width 64 $0\data_r1__spr1$next[63:0]$13122 - attribute \src "libresoc.v:188981.3-188982.43" + attribute \src "libresoc.v:190553.3-190574.6" + wire width 64 $0\data_r1__spr1$next[63:0]$13108 + attribute \src "libresoc.v:190298.3-190299.43" wire width 64 $0\data_r1__spr1[63:0] - attribute \src "libresoc.v:189236.3-189257.6" - wire $0\data_r1__spr1_ok$next[0:0]$13123 - attribute \src "libresoc.v:188983.3-188984.49" + attribute \src "libresoc.v:190553.3-190574.6" + wire $0\data_r1__spr1_ok$next[0:0]$13109 + attribute \src "libresoc.v:190300.3-190301.49" wire $0\data_r1__spr1_ok[0:0] - attribute \src "libresoc.v:189258.3-189279.6" - wire width 64 $0\data_r2__fast1$next[63:0]$13130 - attribute \src "libresoc.v:188977.3-188978.45" + attribute \src "libresoc.v:190575.3-190596.6" + wire width 64 $0\data_r2__fast1$next[63:0]$13116 + attribute \src "libresoc.v:190294.3-190295.45" wire width 64 $0\data_r2__fast1[63:0] - attribute \src "libresoc.v:189258.3-189279.6" - wire $0\data_r2__fast1_ok$next[0:0]$13131 - attribute \src "libresoc.v:188979.3-188980.51" + attribute \src "libresoc.v:190575.3-190596.6" + wire $0\data_r2__fast1_ok$next[0:0]$13117 + attribute \src "libresoc.v:190296.3-190297.51" wire $0\data_r2__fast1_ok[0:0] - attribute \src "libresoc.v:189280.3-189301.6" - wire $0\data_r3__xer_so$next[0:0]$13138 - attribute \src "libresoc.v:188973.3-188974.47" + attribute \src "libresoc.v:190597.3-190618.6" + wire $0\data_r3__xer_so$next[0:0]$13124 + attribute \src "libresoc.v:190290.3-190291.47" wire $0\data_r3__xer_so[0:0] - attribute \src "libresoc.v:189280.3-189301.6" - wire $0\data_r3__xer_so_ok$next[0:0]$13139 - attribute \src "libresoc.v:188975.3-188976.53" + attribute \src "libresoc.v:190597.3-190618.6" + wire $0\data_r3__xer_so_ok$next[0:0]$13125 + attribute \src "libresoc.v:190292.3-190293.53" wire $0\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:189302.3-189323.6" - wire width 2 $0\data_r4__xer_ov$next[1:0]$13146 - attribute \src "libresoc.v:188969.3-188970.47" + attribute \src "libresoc.v:190619.3-190640.6" + wire width 2 $0\data_r4__xer_ov$next[1:0]$13132 + attribute \src "libresoc.v:190286.3-190287.47" wire width 2 $0\data_r4__xer_ov[1:0] - attribute \src "libresoc.v:189302.3-189323.6" - wire $0\data_r4__xer_ov_ok$next[0:0]$13147 - attribute \src "libresoc.v:188971.3-188972.53" + attribute \src "libresoc.v:190619.3-190640.6" + wire $0\data_r4__xer_ov_ok$next[0:0]$13133 + attribute \src "libresoc.v:190288.3-190289.53" wire $0\data_r4__xer_ov_ok[0:0] - attribute \src "libresoc.v:189324.3-189345.6" - wire width 2 $0\data_r5__xer_ca$next[1:0]$13154 - attribute \src "libresoc.v:188965.3-188966.47" + attribute \src "libresoc.v:190641.3-190662.6" + wire width 2 $0\data_r5__xer_ca$next[1:0]$13140 + attribute \src "libresoc.v:190282.3-190283.47" wire width 2 $0\data_r5__xer_ca[1:0] - attribute \src "libresoc.v:189324.3-189345.6" - wire $0\data_r5__xer_ca_ok$next[0:0]$13155 - attribute \src "libresoc.v:188967.3-188968.53" + attribute \src "libresoc.v:190641.3-190662.6" + wire $0\data_r5__xer_ca_ok$next[0:0]$13141 + attribute \src "libresoc.v:190284.3-190285.53" wire $0\data_r5__xer_ca_ok[0:0] - attribute \src "libresoc.v:189424.3-189433.6" + attribute \src "libresoc.v:190741.3-190750.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:189434.3-189443.6" + attribute \src "libresoc.v:190751.3-190760.6" wire width 64 $0\dest2_o[63:0] - attribute \src "libresoc.v:189444.3-189453.6" + attribute \src "libresoc.v:190761.3-190770.6" wire width 64 $0\dest3_o[63:0] - attribute \src "libresoc.v:189454.3-189463.6" + attribute \src "libresoc.v:190771.3-190780.6" wire $0\dest4_o[0:0] - attribute \src "libresoc.v:189464.3-189473.6" + attribute \src "libresoc.v:190781.3-190790.6" wire width 2 $0\dest5_o[1:0] - attribute \src "libresoc.v:189474.3-189483.6" + attribute \src "libresoc.v:190791.3-190800.6" wire width 2 $0\dest6_o[1:0] - attribute \src "libresoc.v:188272.7-188272.20" + attribute \src "libresoc.v:189589.7-189589.20" wire $0\initial[0:0] - attribute \src "libresoc.v:189156.3-189164.6" - wire $0\opc_l_r_opc$next[0:0]$13090 - attribute \src "libresoc.v:189005.3-189006.39" + attribute \src "libresoc.v:190473.3-190481.6" + wire $0\opc_l_r_opc$next[0:0]$13076 + attribute \src "libresoc.v:190322.3-190323.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:189147.3-189155.6" - wire $0\opc_l_s_opc$next[0:0]$13087 - attribute \src "libresoc.v:189007.3-189008.39" + attribute \src "libresoc.v:190464.3-190472.6" + wire $0\opc_l_s_opc$next[0:0]$13073 + attribute \src "libresoc.v:190324.3-190325.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:189484.3-189492.6" - wire width 6 $0\prev_wr_go$next[5:0]$13192 - attribute \src "libresoc.v:189017.3-189018.37" + attribute \src "libresoc.v:190801.3-190809.6" + wire width 6 $0\prev_wr_go$next[5:0]$13178 + attribute \src "libresoc.v:190334.3-190335.37" wire width 6 $0\prev_wr_go[5:0] - attribute \src "libresoc.v:189101.3-189110.6" + attribute \src "libresoc.v:190418.3-190427.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:189192.3-189200.6" - wire width 6 $0\req_l_r_req$next[5:0]$13102 - attribute \src "libresoc.v:188997.3-188998.39" + attribute \src "libresoc.v:190509.3-190517.6" + wire width 6 $0\req_l_r_req$next[5:0]$13088 + attribute \src "libresoc.v:190314.3-190315.39" wire width 6 $0\req_l_r_req[5:0] - attribute \src "libresoc.v:189183.3-189191.6" - wire width 6 $0\req_l_s_req$next[5:0]$13099 - attribute \src "libresoc.v:188999.3-189000.39" + attribute \src "libresoc.v:190500.3-190508.6" + wire width 6 $0\req_l_s_req$next[5:0]$13085 + attribute \src "libresoc.v:190316.3-190317.39" wire width 6 $0\req_l_s_req[5:0] - attribute \src "libresoc.v:189120.3-189128.6" - wire $0\rok_l_r_rdok$next[0:0]$13078 - attribute \src "libresoc.v:189013.3-189014.41" + attribute \src "libresoc.v:190437.3-190445.6" + wire $0\rok_l_r_rdok$next[0:0]$13064 + attribute \src "libresoc.v:190330.3-190331.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:189111.3-189119.6" - wire $0\rok_l_s_rdok$next[0:0]$13075 - attribute \src "libresoc.v:189015.3-189016.41" + attribute \src "libresoc.v:190428.3-190436.6" + wire $0\rok_l_s_rdok$next[0:0]$13061 + attribute \src "libresoc.v:190332.3-190333.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:189138.3-189146.6" - wire $0\rst_l_r_rst$next[0:0]$13084 - attribute \src "libresoc.v:189009.3-189010.39" + attribute \src "libresoc.v:190455.3-190463.6" + wire $0\rst_l_r_rst$next[0:0]$13070 + attribute \src "libresoc.v:190326.3-190327.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:189129.3-189137.6" - wire $0\rst_l_s_rst$next[0:0]$13081 - attribute \src "libresoc.v:189011.3-189012.39" + attribute \src "libresoc.v:190446.3-190454.6" + wire $0\rst_l_s_rst$next[0:0]$13067 + attribute \src "libresoc.v:190328.3-190329.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:189174.3-189182.6" - wire width 6 $0\src_l_r_src$next[5:0]$13096 - attribute \src "libresoc.v:189001.3-189002.39" + attribute \src "libresoc.v:190491.3-190499.6" + wire width 6 $0\src_l_r_src$next[5:0]$13082 + attribute \src "libresoc.v:190318.3-190319.39" wire width 6 $0\src_l_r_src[5:0] - attribute \src "libresoc.v:189165.3-189173.6" - wire width 6 $0\src_l_s_src$next[5:0]$13093 - attribute \src "libresoc.v:189003.3-189004.39" + attribute \src "libresoc.v:190482.3-190490.6" + wire width 6 $0\src_l_s_src$next[5:0]$13079 + attribute \src "libresoc.v:190320.3-190321.39" wire width 6 $0\src_l_s_src[5:0] - attribute \src "libresoc.v:189346.3-189355.6" - wire width 64 $0\src_r0$next[63:0]$13162 - attribute \src "libresoc.v:188963.3-188964.29" + attribute \src "libresoc.v:190663.3-190672.6" + wire width 64 $0\src_r0$next[63:0]$13148 + attribute \src "libresoc.v:190280.3-190281.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:189356.3-189365.6" - wire width 64 $0\src_r1$next[63:0]$13165 - attribute \src "libresoc.v:188961.3-188962.29" + attribute \src "libresoc.v:190673.3-190682.6" + wire width 64 $0\src_r1$next[63:0]$13151 + attribute \src "libresoc.v:190278.3-190279.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:189366.3-189375.6" - wire width 64 $0\src_r2$next[63:0]$13168 - attribute \src "libresoc.v:188959.3-188960.29" + attribute \src "libresoc.v:190683.3-190692.6" + wire width 64 $0\src_r2$next[63:0]$13154 + attribute \src "libresoc.v:190276.3-190277.29" wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:189376.3-189385.6" - wire $0\src_r3$next[0:0]$13171 - attribute \src "libresoc.v:188957.3-188958.29" + attribute \src "libresoc.v:190693.3-190702.6" + wire $0\src_r3$next[0:0]$13157 + attribute \src "libresoc.v:190274.3-190275.29" wire $0\src_r3[0:0] - attribute \src "libresoc.v:189386.3-189395.6" - wire width 2 $0\src_r4$next[1:0]$13174 - attribute \src "libresoc.v:188955.3-188956.29" + attribute \src "libresoc.v:190703.3-190712.6" + wire width 2 $0\src_r4$next[1:0]$13160 + attribute \src "libresoc.v:190272.3-190273.29" wire width 2 $0\src_r4[1:0] - attribute \src "libresoc.v:189396.3-189405.6" - wire width 2 $0\src_r5$next[1:0]$13177 - attribute \src "libresoc.v:188953.3-188954.29" + attribute \src "libresoc.v:190713.3-190722.6" + wire width 2 $0\src_r5$next[1:0]$13163 + attribute \src "libresoc.v:190270.3-190271.29" wire width 2 $0\src_r5[1:0] - attribute \src "libresoc.v:188408.7-188408.24" + attribute \src "libresoc.v:189725.7-189725.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:188418.7-188418.26" + attribute \src "libresoc.v:189735.7-189735.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:189415.3-189423.6" - wire $1\alu_l_r_alu$next[0:0]$13184 - attribute \src "libresoc.v:188426.7-188426.25" + attribute \src "libresoc.v:190732.3-190740.6" + wire $1\alu_l_r_alu$next[0:0]$13170 + attribute \src "libresoc.v:189743.7-189743.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:189201.3-189213.6" - wire width 14 $1\alu_spr0_spr_op__fn_unit$next[13:0]$13109 - attribute \src "libresoc.v:188471.14-188471.49" + attribute \src "libresoc.v:190518.3-190530.6" + wire width 14 $1\alu_spr0_spr_op__fn_unit$next[13:0]$13095 + attribute \src "libresoc.v:189788.14-189788.49" wire width 14 $1\alu_spr0_spr_op__fn_unit[13:0] - attribute \src "libresoc.v:189201.3-189213.6" - wire width 32 $1\alu_spr0_spr_op__insn$next[31:0]$13110 - attribute \src "libresoc.v:188475.14-188475.43" + attribute \src "libresoc.v:190518.3-190530.6" + wire width 32 $1\alu_spr0_spr_op__insn$next[31:0]$13096 + attribute \src "libresoc.v:189792.14-189792.43" wire width 32 $1\alu_spr0_spr_op__insn[31:0] - attribute \src "libresoc.v:189201.3-189213.6" - wire width 7 $1\alu_spr0_spr_op__insn_type$next[6:0]$13111 - attribute \src "libresoc.v:188554.13-188554.47" + attribute \src "libresoc.v:190518.3-190530.6" + wire width 7 $1\alu_spr0_spr_op__insn_type$next[6:0]$13097 + attribute \src "libresoc.v:189871.13-189871.47" wire width 7 $1\alu_spr0_spr_op__insn_type[6:0] - attribute \src "libresoc.v:189201.3-189213.6" - wire $1\alu_spr0_spr_op__is_32bit$next[0:0]$13112 - attribute \src "libresoc.v:188558.7-188558.39" + attribute \src "libresoc.v:190518.3-190530.6" + wire $1\alu_spr0_spr_op__is_32bit$next[0:0]$13098 + attribute \src "libresoc.v:189875.7-189875.39" wire $1\alu_spr0_spr_op__is_32bit[0:0] - attribute \src "libresoc.v:189406.3-189414.6" - wire $1\alui_l_r_alui$next[0:0]$13181 - attribute \src "libresoc.v:188576.7-188576.27" + attribute \src "libresoc.v:190723.3-190731.6" + wire $1\alui_l_r_alui$next[0:0]$13167 + attribute \src "libresoc.v:189893.7-189893.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:189214.3-189235.6" - wire width 64 $1\data_r0__o$next[63:0]$13116 - attribute \src "libresoc.v:188608.14-188608.47" + attribute \src "libresoc.v:190531.3-190552.6" + wire width 64 $1\data_r0__o$next[63:0]$13102 + attribute \src "libresoc.v:189925.14-189925.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:189214.3-189235.6" - wire $1\data_r0__o_ok$next[0:0]$13117 - attribute \src "libresoc.v:188612.7-188612.27" + attribute \src "libresoc.v:190531.3-190552.6" + wire $1\data_r0__o_ok$next[0:0]$13103 + attribute \src "libresoc.v:189929.7-189929.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:189236.3-189257.6" - wire width 64 $1\data_r1__spr1$next[63:0]$13124 - attribute \src "libresoc.v:188616.14-188616.50" + attribute \src "libresoc.v:190553.3-190574.6" + wire width 64 $1\data_r1__spr1$next[63:0]$13110 + attribute \src "libresoc.v:189933.14-189933.50" wire width 64 $1\data_r1__spr1[63:0] - attribute \src "libresoc.v:189236.3-189257.6" - wire $1\data_r1__spr1_ok$next[0:0]$13125 - attribute \src "libresoc.v:188620.7-188620.30" + attribute \src "libresoc.v:190553.3-190574.6" + wire $1\data_r1__spr1_ok$next[0:0]$13111 + attribute \src "libresoc.v:189937.7-189937.30" wire $1\data_r1__spr1_ok[0:0] - attribute \src "libresoc.v:189258.3-189279.6" - wire width 64 $1\data_r2__fast1$next[63:0]$13132 - attribute \src "libresoc.v:188624.14-188624.51" + attribute \src "libresoc.v:190575.3-190596.6" + wire width 64 $1\data_r2__fast1$next[63:0]$13118 + attribute \src "libresoc.v:189941.14-189941.51" wire width 64 $1\data_r2__fast1[63:0] - attribute \src "libresoc.v:189258.3-189279.6" - wire $1\data_r2__fast1_ok$next[0:0]$13133 - attribute \src "libresoc.v:188628.7-188628.31" + attribute \src "libresoc.v:190575.3-190596.6" + wire $1\data_r2__fast1_ok$next[0:0]$13119 + attribute \src "libresoc.v:189945.7-189945.31" wire $1\data_r2__fast1_ok[0:0] - attribute \src "libresoc.v:189280.3-189301.6" - wire $1\data_r3__xer_so$next[0:0]$13140 - attribute \src "libresoc.v:188632.7-188632.29" + attribute \src "libresoc.v:190597.3-190618.6" + wire $1\data_r3__xer_so$next[0:0]$13126 + attribute \src "libresoc.v:189949.7-189949.29" wire $1\data_r3__xer_so[0:0] - attribute \src "libresoc.v:189280.3-189301.6" - wire $1\data_r3__xer_so_ok$next[0:0]$13141 - attribute \src "libresoc.v:188636.7-188636.32" + attribute \src "libresoc.v:190597.3-190618.6" + wire $1\data_r3__xer_so_ok$next[0:0]$13127 + attribute \src "libresoc.v:189953.7-189953.32" wire $1\data_r3__xer_so_ok[0:0] - attribute \src "libresoc.v:189302.3-189323.6" - wire width 2 $1\data_r4__xer_ov$next[1:0]$13148 - attribute \src "libresoc.v:188640.13-188640.35" + attribute \src "libresoc.v:190619.3-190640.6" + wire width 2 $1\data_r4__xer_ov$next[1:0]$13134 + attribute \src "libresoc.v:189957.13-189957.35" wire width 2 $1\data_r4__xer_ov[1:0] - attribute \src "libresoc.v:189302.3-189323.6" - wire $1\data_r4__xer_ov_ok$next[0:0]$13149 - attribute \src "libresoc.v:188644.7-188644.32" + attribute \src "libresoc.v:190619.3-190640.6" + wire $1\data_r4__xer_ov_ok$next[0:0]$13135 + attribute \src "libresoc.v:189961.7-189961.32" wire $1\data_r4__xer_ov_ok[0:0] - attribute \src "libresoc.v:189324.3-189345.6" - wire width 2 $1\data_r5__xer_ca$next[1:0]$13156 - attribute \src "libresoc.v:188648.13-188648.35" + attribute \src "libresoc.v:190641.3-190662.6" + wire width 2 $1\data_r5__xer_ca$next[1:0]$13142 + attribute \src "libresoc.v:189965.13-189965.35" wire width 2 $1\data_r5__xer_ca[1:0] - attribute \src "libresoc.v:189324.3-189345.6" - wire $1\data_r5__xer_ca_ok$next[0:0]$13157 - attribute \src "libresoc.v:188652.7-188652.32" + attribute \src "libresoc.v:190641.3-190662.6" + wire $1\data_r5__xer_ca_ok$next[0:0]$13143 + attribute \src "libresoc.v:189969.7-189969.32" wire $1\data_r5__xer_ca_ok[0:0] - attribute \src "libresoc.v:189424.3-189433.6" + attribute \src "libresoc.v:190741.3-190750.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:189434.3-189443.6" + attribute \src "libresoc.v:190751.3-190760.6" wire width 64 $1\dest2_o[63:0] - attribute \src "libresoc.v:189444.3-189453.6" + attribute \src "libresoc.v:190761.3-190770.6" wire width 64 $1\dest3_o[63:0] - attribute \src "libresoc.v:189454.3-189463.6" + attribute \src "libresoc.v:190771.3-190780.6" wire $1\dest4_o[0:0] - attribute \src "libresoc.v:189464.3-189473.6" + attribute \src "libresoc.v:190781.3-190790.6" wire width 2 $1\dest5_o[1:0] - attribute \src "libresoc.v:189474.3-189483.6" + attribute \src "libresoc.v:190791.3-190800.6" wire width 2 $1\dest6_o[1:0] - attribute \src "libresoc.v:189156.3-189164.6" - wire $1\opc_l_r_opc$next[0:0]$13091 - attribute \src "libresoc.v:188680.7-188680.25" + attribute \src "libresoc.v:190473.3-190481.6" + wire $1\opc_l_r_opc$next[0:0]$13077 + attribute \src "libresoc.v:189997.7-189997.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:189147.3-189155.6" - wire $1\opc_l_s_opc$next[0:0]$13088 - attribute \src "libresoc.v:188684.7-188684.25" + attribute \src "libresoc.v:190464.3-190472.6" + wire $1\opc_l_s_opc$next[0:0]$13074 + attribute \src "libresoc.v:190001.7-190001.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:189484.3-189492.6" - wire width 6 $1\prev_wr_go$next[5:0]$13193 - attribute \src "libresoc.v:188786.13-188786.31" + attribute \src "libresoc.v:190801.3-190809.6" + wire width 6 $1\prev_wr_go$next[5:0]$13179 + attribute \src "libresoc.v:190103.13-190103.31" wire width 6 $1\prev_wr_go[5:0] - attribute \src "libresoc.v:189101.3-189110.6" + attribute \src "libresoc.v:190418.3-190427.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:189192.3-189200.6" - wire width 6 $1\req_l_r_req$next[5:0]$13103 - attribute \src "libresoc.v:188794.13-188794.32" + attribute \src "libresoc.v:190509.3-190517.6" + wire width 6 $1\req_l_r_req$next[5:0]$13089 + attribute \src "libresoc.v:190111.13-190111.32" wire width 6 $1\req_l_r_req[5:0] - attribute \src "libresoc.v:189183.3-189191.6" - wire width 6 $1\req_l_s_req$next[5:0]$13100 - attribute \src "libresoc.v:188798.13-188798.32" + attribute \src "libresoc.v:190500.3-190508.6" + wire width 6 $1\req_l_s_req$next[5:0]$13086 + attribute \src "libresoc.v:190115.13-190115.32" wire width 6 $1\req_l_s_req[5:0] - attribute \src "libresoc.v:189120.3-189128.6" - wire $1\rok_l_r_rdok$next[0:0]$13079 - attribute \src "libresoc.v:188810.7-188810.26" + attribute \src "libresoc.v:190437.3-190445.6" + wire $1\rok_l_r_rdok$next[0:0]$13065 + attribute \src "libresoc.v:190127.7-190127.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:189111.3-189119.6" - wire $1\rok_l_s_rdok$next[0:0]$13076 - attribute \src "libresoc.v:188814.7-188814.26" + attribute \src "libresoc.v:190428.3-190436.6" + wire $1\rok_l_s_rdok$next[0:0]$13062 + attribute \src "libresoc.v:190131.7-190131.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:189138.3-189146.6" - wire $1\rst_l_r_rst$next[0:0]$13085 - attribute \src "libresoc.v:188818.7-188818.25" + attribute \src "libresoc.v:190455.3-190463.6" + wire $1\rst_l_r_rst$next[0:0]$13071 + attribute \src "libresoc.v:190135.7-190135.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:189129.3-189137.6" - wire $1\rst_l_s_rst$next[0:0]$13082 - attribute \src "libresoc.v:188822.7-188822.25" + attribute \src "libresoc.v:190446.3-190454.6" + wire $1\rst_l_s_rst$next[0:0]$13068 + attribute \src "libresoc.v:190139.7-190139.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:189174.3-189182.6" - wire width 6 $1\src_l_r_src$next[5:0]$13097 - attribute \src "libresoc.v:188844.13-188844.32" + attribute \src "libresoc.v:190491.3-190499.6" + wire width 6 $1\src_l_r_src$next[5:0]$13083 + attribute \src "libresoc.v:190161.13-190161.32" wire width 6 $1\src_l_r_src[5:0] - attribute \src "libresoc.v:189165.3-189173.6" - wire width 6 $1\src_l_s_src$next[5:0]$13094 - attribute \src "libresoc.v:188848.13-188848.32" + attribute \src "libresoc.v:190482.3-190490.6" + wire width 6 $1\src_l_s_src$next[5:0]$13080 + attribute \src "libresoc.v:190165.13-190165.32" wire width 6 $1\src_l_s_src[5:0] - attribute \src "libresoc.v:189346.3-189355.6" - wire width 64 $1\src_r0$next[63:0]$13163 - attribute \src "libresoc.v:188852.14-188852.43" + attribute \src "libresoc.v:190663.3-190672.6" + wire width 64 $1\src_r0$next[63:0]$13149 + attribute \src "libresoc.v:190169.14-190169.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:189356.3-189365.6" - wire width 64 $1\src_r1$next[63:0]$13166 - attribute \src "libresoc.v:188856.14-188856.43" + attribute \src "libresoc.v:190673.3-190682.6" + wire width 64 $1\src_r1$next[63:0]$13152 + attribute \src "libresoc.v:190173.14-190173.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:189366.3-189375.6" - wire width 64 $1\src_r2$next[63:0]$13169 - attribute \src "libresoc.v:188860.14-188860.43" + attribute \src "libresoc.v:190683.3-190692.6" + wire width 64 $1\src_r2$next[63:0]$13155 + attribute \src "libresoc.v:190177.14-190177.43" wire width 64 $1\src_r2[63:0] - attribute \src "libresoc.v:189376.3-189385.6" - wire $1\src_r3$next[0:0]$13172 - attribute \src "libresoc.v:188864.7-188864.20" + attribute \src "libresoc.v:190693.3-190702.6" + wire $1\src_r3$next[0:0]$13158 + attribute \src "libresoc.v:190181.7-190181.20" wire $1\src_r3[0:0] - attribute \src "libresoc.v:189386.3-189395.6" - wire width 2 $1\src_r4$next[1:0]$13175 - attribute \src "libresoc.v:188868.13-188868.26" + attribute \src "libresoc.v:190703.3-190712.6" + wire width 2 $1\src_r4$next[1:0]$13161 + attribute \src "libresoc.v:190185.13-190185.26" wire width 2 $1\src_r4[1:0] - attribute \src "libresoc.v:189396.3-189405.6" - wire width 2 $1\src_r5$next[1:0]$13178 - attribute \src "libresoc.v:188872.13-188872.26" + attribute \src "libresoc.v:190713.3-190722.6" + wire width 2 $1\src_r5$next[1:0]$13164 + attribute \src "libresoc.v:190189.13-190189.26" wire width 2 $1\src_r5[1:0] - attribute \src "libresoc.v:189214.3-189235.6" - wire width 64 $2\data_r0__o$next[63:0]$13118 - attribute \src "libresoc.v:189214.3-189235.6" - wire $2\data_r0__o_ok$next[0:0]$13119 - attribute \src "libresoc.v:189236.3-189257.6" - wire width 64 $2\data_r1__spr1$next[63:0]$13126 - attribute \src "libresoc.v:189236.3-189257.6" - wire $2\data_r1__spr1_ok$next[0:0]$13127 - attribute \src "libresoc.v:189258.3-189279.6" - wire width 64 $2\data_r2__fast1$next[63:0]$13134 - attribute \src "libresoc.v:189258.3-189279.6" - wire $2\data_r2__fast1_ok$next[0:0]$13135 - attribute \src "libresoc.v:189280.3-189301.6" - wire $2\data_r3__xer_so$next[0:0]$13142 - attribute \src "libresoc.v:189280.3-189301.6" - wire $2\data_r3__xer_so_ok$next[0:0]$13143 - attribute \src "libresoc.v:189302.3-189323.6" - wire width 2 $2\data_r4__xer_ov$next[1:0]$13150 - attribute \src "libresoc.v:189302.3-189323.6" - wire $2\data_r4__xer_ov_ok$next[0:0]$13151 - attribute \src "libresoc.v:189324.3-189345.6" - wire width 2 $2\data_r5__xer_ca$next[1:0]$13158 - attribute \src "libresoc.v:189324.3-189345.6" - wire $2\data_r5__xer_ca_ok$next[0:0]$13159 - attribute \src "libresoc.v:189214.3-189235.6" - wire $3\data_r0__o_ok$next[0:0]$13120 - attribute \src "libresoc.v:189236.3-189257.6" - wire $3\data_r1__spr1_ok$next[0:0]$13128 - attribute \src "libresoc.v:189258.3-189279.6" - wire $3\data_r2__fast1_ok$next[0:0]$13136 - attribute \src "libresoc.v:189280.3-189301.6" - wire $3\data_r3__xer_so_ok$next[0:0]$13144 - attribute \src "libresoc.v:189302.3-189323.6" - wire $3\data_r4__xer_ov_ok$next[0:0]$13152 - attribute \src "libresoc.v:189324.3-189345.6" - wire $3\data_r5__xer_ca_ok$next[0:0]$13160 - attribute \src "libresoc.v:188884.19-188884.133" - wire $and$libresoc.v:188884$12971_Y - attribute \src "libresoc.v:188885.19-188885.183" - wire width 6 $and$libresoc.v:188885$12972_Y - attribute \src "libresoc.v:188886.19-188886.115" - wire width 6 $and$libresoc.v:188886$12973_Y - attribute \src "libresoc.v:188888.19-188888.115" - wire width 6 $and$libresoc.v:188888$12975_Y - attribute \src "libresoc.v:188889.19-188889.125" - wire $and$libresoc.v:188889$12976_Y - attribute \src "libresoc.v:188890.19-188890.125" - wire $and$libresoc.v:188890$12977_Y - attribute \src "libresoc.v:188891.19-188891.125" - wire $and$libresoc.v:188891$12978_Y - attribute \src "libresoc.v:188892.19-188892.125" - wire $and$libresoc.v:188892$12979_Y - attribute \src "libresoc.v:188893.19-188893.125" - wire $and$libresoc.v:188893$12980_Y - attribute \src "libresoc.v:188895.19-188895.125" - wire $and$libresoc.v:188895$12982_Y - attribute \src "libresoc.v:188896.19-188896.165" - wire width 6 $and$libresoc.v:188896$12983_Y - attribute \src "libresoc.v:188897.19-188897.121" - wire width 6 $and$libresoc.v:188897$12984_Y - attribute \src "libresoc.v:188898.19-188898.127" - wire $and$libresoc.v:188898$12985_Y - attribute \src "libresoc.v:188899.19-188899.127" - wire $and$libresoc.v:188899$12986_Y - attribute \src "libresoc.v:188901.19-188901.127" - wire $and$libresoc.v:188901$12988_Y - attribute \src "libresoc.v:188902.19-188902.127" - wire $and$libresoc.v:188902$12989_Y - attribute \src "libresoc.v:188903.19-188903.127" - wire $and$libresoc.v:188903$12990_Y - attribute \src "libresoc.v:188904.19-188904.127" - wire $and$libresoc.v:188904$12991_Y - attribute \src "libresoc.v:188905.18-188905.110" - wire $and$libresoc.v:188905$12992_Y - attribute \src "libresoc.v:188907.18-188907.98" - wire $and$libresoc.v:188907$12994_Y - attribute \src "libresoc.v:188909.18-188909.100" - wire $and$libresoc.v:188909$12996_Y - attribute \src "libresoc.v:188910.18-188910.182" - wire width 6 $and$libresoc.v:188910$12997_Y - attribute \src "libresoc.v:188912.18-188912.119" - wire width 6 $and$libresoc.v:188912$12999_Y - attribute \src "libresoc.v:188915.18-188915.116" - wire $and$libresoc.v:188915$13002_Y - attribute \src "libresoc.v:188920.18-188920.113" - wire $and$libresoc.v:188920$13007_Y - attribute \src "libresoc.v:188921.18-188921.125" - wire width 6 $and$libresoc.v:188921$13008_Y - attribute \src "libresoc.v:188923.18-188923.112" - wire $and$libresoc.v:188923$13010_Y - attribute \src "libresoc.v:188925.18-188925.126" - wire $and$libresoc.v:188925$13012_Y - attribute \src "libresoc.v:188926.18-188926.126" - wire $and$libresoc.v:188926$13013_Y - attribute \src "libresoc.v:188927.18-188927.117" - wire $and$libresoc.v:188927$13014_Y - attribute \src "libresoc.v:188932.18-188932.130" - wire $and$libresoc.v:188932$13019_Y - attribute \src "libresoc.v:188933.17-188933.123" - wire $and$libresoc.v:188933$13020_Y - attribute \src "libresoc.v:188934.18-188934.124" - wire width 6 $and$libresoc.v:188934$13021_Y - attribute \src "libresoc.v:188936.18-188936.116" - wire $and$libresoc.v:188936$13023_Y - attribute \src "libresoc.v:188937.18-188937.119" - wire $and$libresoc.v:188937$13024_Y - attribute \src "libresoc.v:188938.18-188938.120" - wire $and$libresoc.v:188938$13025_Y - attribute \src "libresoc.v:188939.18-188939.121" - wire $and$libresoc.v:188939$13026_Y - attribute \src "libresoc.v:188940.18-188940.121" - wire $and$libresoc.v:188940$13027_Y - attribute \src "libresoc.v:188941.18-188941.121" - wire $and$libresoc.v:188941$13028_Y - attribute \src "libresoc.v:188948.18-188948.134" - wire $and$libresoc.v:188948$13035_Y - attribute \src "libresoc.v:188922.18-188922.113" - wire $eq$libresoc.v:188922$13009_Y - attribute \src "libresoc.v:188924.18-188924.119" - wire $eq$libresoc.v:188924$13011_Y - attribute \src "libresoc.v:188883.17-188883.113" - wire width 6 $not$libresoc.v:188883$12970_Y - attribute \src "libresoc.v:188887.19-188887.115" - wire width 6 $not$libresoc.v:188887$12974_Y - attribute \src "libresoc.v:188906.18-188906.97" - wire $not$libresoc.v:188906$12993_Y - attribute \src "libresoc.v:188908.18-188908.99" - wire $not$libresoc.v:188908$12995_Y - attribute \src "libresoc.v:188911.18-188911.113" - wire width 6 $not$libresoc.v:188911$12998_Y - attribute \src "libresoc.v:188914.18-188914.106" - wire $not$libresoc.v:188914$13001_Y - attribute \src "libresoc.v:188919.18-188919.120" - wire $not$libresoc.v:188919$13006_Y - attribute \src "libresoc.v:188894.18-188894.118" - wire width 6 $or$libresoc.v:188894$12981_Y - attribute \src "libresoc.v:188918.18-188918.112" - wire $or$libresoc.v:188918$13005_Y - attribute \src "libresoc.v:188928.18-188928.122" - wire $or$libresoc.v:188928$13015_Y - attribute \src "libresoc.v:188929.18-188929.124" - wire $or$libresoc.v:188929$13016_Y - attribute \src "libresoc.v:188930.18-188930.194" - wire width 6 $or$libresoc.v:188930$13017_Y - attribute \src "libresoc.v:188931.18-188931.194" - wire width 6 $or$libresoc.v:188931$13018_Y - attribute \src "libresoc.v:188935.18-188935.120" - wire width 6 $or$libresoc.v:188935$13022_Y - attribute \src "libresoc.v:188900.17-188900.105" - wire $reduce_and$libresoc.v:188900$12987_Y - attribute \src "libresoc.v:188913.18-188913.106" - wire $reduce_or$libresoc.v:188913$13000_Y - attribute \src "libresoc.v:188916.18-188916.113" - wire $reduce_or$libresoc.v:188916$13003_Y - attribute \src "libresoc.v:188917.18-188917.112" - wire $reduce_or$libresoc.v:188917$13004_Y - attribute \src "libresoc.v:188942.18-188942.118" - wire width 64 $ternary$libresoc.v:188942$13029_Y - attribute \src "libresoc.v:188943.18-188943.118" - wire width 64 $ternary$libresoc.v:188943$13030_Y - attribute \src "libresoc.v:188944.18-188944.118" - wire width 64 $ternary$libresoc.v:188944$13031_Y - attribute \src "libresoc.v:188945.18-188945.118" - wire $ternary$libresoc.v:188945$13032_Y - attribute \src "libresoc.v:188946.18-188946.118" - wire width 2 $ternary$libresoc.v:188946$13033_Y - attribute \src "libresoc.v:188947.18-188947.118" - wire width 2 $ternary$libresoc.v:188947$13034_Y + attribute \src "libresoc.v:190531.3-190552.6" + wire width 64 $2\data_r0__o$next[63:0]$13104 + attribute \src "libresoc.v:190531.3-190552.6" + wire $2\data_r0__o_ok$next[0:0]$13105 + attribute \src "libresoc.v:190553.3-190574.6" + wire width 64 $2\data_r1__spr1$next[63:0]$13112 + attribute \src "libresoc.v:190553.3-190574.6" + wire $2\data_r1__spr1_ok$next[0:0]$13113 + attribute \src "libresoc.v:190575.3-190596.6" + wire width 64 $2\data_r2__fast1$next[63:0]$13120 + attribute \src "libresoc.v:190575.3-190596.6" + wire $2\data_r2__fast1_ok$next[0:0]$13121 + attribute \src "libresoc.v:190597.3-190618.6" + wire $2\data_r3__xer_so$next[0:0]$13128 + attribute \src "libresoc.v:190597.3-190618.6" + wire $2\data_r3__xer_so_ok$next[0:0]$13129 + attribute \src "libresoc.v:190619.3-190640.6" + wire width 2 $2\data_r4__xer_ov$next[1:0]$13136 + attribute \src "libresoc.v:190619.3-190640.6" + wire $2\data_r4__xer_ov_ok$next[0:0]$13137 + attribute \src "libresoc.v:190641.3-190662.6" + wire width 2 $2\data_r5__xer_ca$next[1:0]$13144 + attribute \src "libresoc.v:190641.3-190662.6" + wire $2\data_r5__xer_ca_ok$next[0:0]$13145 + attribute \src "libresoc.v:190531.3-190552.6" + wire $3\data_r0__o_ok$next[0:0]$13106 + attribute \src "libresoc.v:190553.3-190574.6" + wire $3\data_r1__spr1_ok$next[0:0]$13114 + attribute \src "libresoc.v:190575.3-190596.6" + wire $3\data_r2__fast1_ok$next[0:0]$13122 + attribute \src "libresoc.v:190597.3-190618.6" + wire $3\data_r3__xer_so_ok$next[0:0]$13130 + attribute \src "libresoc.v:190619.3-190640.6" + wire $3\data_r4__xer_ov_ok$next[0:0]$13138 + attribute \src "libresoc.v:190641.3-190662.6" + wire $3\data_r5__xer_ca_ok$next[0:0]$13146 + attribute \src "libresoc.v:190201.19-190201.133" + wire $and$libresoc.v:190201$12957_Y + attribute \src "libresoc.v:190202.19-190202.183" + wire width 6 $and$libresoc.v:190202$12958_Y + attribute \src "libresoc.v:190203.19-190203.115" + wire width 6 $and$libresoc.v:190203$12959_Y + attribute \src "libresoc.v:190205.19-190205.115" + wire width 6 $and$libresoc.v:190205$12961_Y + attribute \src "libresoc.v:190206.19-190206.125" + wire $and$libresoc.v:190206$12962_Y + attribute \src "libresoc.v:190207.19-190207.125" + wire $and$libresoc.v:190207$12963_Y + attribute \src "libresoc.v:190208.19-190208.125" + wire $and$libresoc.v:190208$12964_Y + attribute \src "libresoc.v:190209.19-190209.125" + wire $and$libresoc.v:190209$12965_Y + attribute \src "libresoc.v:190210.19-190210.125" + wire $and$libresoc.v:190210$12966_Y + attribute \src "libresoc.v:190212.19-190212.125" + wire $and$libresoc.v:190212$12968_Y + attribute \src "libresoc.v:190213.19-190213.165" + wire width 6 $and$libresoc.v:190213$12969_Y + attribute \src "libresoc.v:190214.19-190214.121" + wire width 6 $and$libresoc.v:190214$12970_Y + attribute \src "libresoc.v:190215.19-190215.127" + wire $and$libresoc.v:190215$12971_Y + attribute \src "libresoc.v:190216.19-190216.127" + wire $and$libresoc.v:190216$12972_Y + attribute \src "libresoc.v:190218.19-190218.127" + wire $and$libresoc.v:190218$12974_Y + attribute \src "libresoc.v:190219.19-190219.127" + wire $and$libresoc.v:190219$12975_Y + attribute \src "libresoc.v:190220.19-190220.127" + wire $and$libresoc.v:190220$12976_Y + attribute \src "libresoc.v:190221.19-190221.127" + wire $and$libresoc.v:190221$12977_Y + attribute \src "libresoc.v:190222.18-190222.110" + wire $and$libresoc.v:190222$12978_Y + attribute \src "libresoc.v:190224.18-190224.98" + wire $and$libresoc.v:190224$12980_Y + attribute \src "libresoc.v:190226.18-190226.100" + wire $and$libresoc.v:190226$12982_Y + attribute \src "libresoc.v:190227.18-190227.182" + wire width 6 $and$libresoc.v:190227$12983_Y + attribute \src "libresoc.v:190229.18-190229.119" + wire width 6 $and$libresoc.v:190229$12985_Y + attribute \src "libresoc.v:190232.18-190232.116" + wire $and$libresoc.v:190232$12988_Y + attribute \src "libresoc.v:190237.18-190237.113" + wire $and$libresoc.v:190237$12993_Y + attribute \src "libresoc.v:190238.18-190238.125" + wire width 6 $and$libresoc.v:190238$12994_Y + attribute \src "libresoc.v:190240.18-190240.112" + wire $and$libresoc.v:190240$12996_Y + attribute \src "libresoc.v:190242.18-190242.126" + wire $and$libresoc.v:190242$12998_Y + attribute \src "libresoc.v:190243.18-190243.126" + wire $and$libresoc.v:190243$12999_Y + attribute \src "libresoc.v:190244.18-190244.117" + wire $and$libresoc.v:190244$13000_Y + attribute \src "libresoc.v:190249.18-190249.130" + wire $and$libresoc.v:190249$13005_Y + attribute \src "libresoc.v:190250.17-190250.123" + wire $and$libresoc.v:190250$13006_Y + attribute \src "libresoc.v:190251.18-190251.124" + wire width 6 $and$libresoc.v:190251$13007_Y + attribute \src "libresoc.v:190253.18-190253.116" + wire $and$libresoc.v:190253$13009_Y + attribute \src "libresoc.v:190254.18-190254.119" + wire $and$libresoc.v:190254$13010_Y + attribute \src "libresoc.v:190255.18-190255.120" + wire $and$libresoc.v:190255$13011_Y + attribute \src "libresoc.v:190256.18-190256.121" + wire $and$libresoc.v:190256$13012_Y + attribute \src "libresoc.v:190257.18-190257.121" + wire $and$libresoc.v:190257$13013_Y + attribute \src "libresoc.v:190258.18-190258.121" + wire $and$libresoc.v:190258$13014_Y + attribute \src "libresoc.v:190265.18-190265.134" + wire $and$libresoc.v:190265$13021_Y + attribute \src "libresoc.v:190239.18-190239.113" + wire $eq$libresoc.v:190239$12995_Y + attribute \src "libresoc.v:190241.18-190241.119" + wire $eq$libresoc.v:190241$12997_Y + attribute \src "libresoc.v:190200.17-190200.113" + wire width 6 $not$libresoc.v:190200$12956_Y + attribute \src "libresoc.v:190204.19-190204.115" + wire width 6 $not$libresoc.v:190204$12960_Y + attribute \src "libresoc.v:190223.18-190223.97" + wire $not$libresoc.v:190223$12979_Y + attribute \src "libresoc.v:190225.18-190225.99" + wire $not$libresoc.v:190225$12981_Y + attribute \src "libresoc.v:190228.18-190228.113" + wire width 6 $not$libresoc.v:190228$12984_Y + attribute \src "libresoc.v:190231.18-190231.106" + wire $not$libresoc.v:190231$12987_Y + attribute \src "libresoc.v:190236.18-190236.120" + wire $not$libresoc.v:190236$12992_Y + attribute \src "libresoc.v:190211.18-190211.118" + wire width 6 $or$libresoc.v:190211$12967_Y + attribute \src "libresoc.v:190235.18-190235.112" + wire $or$libresoc.v:190235$12991_Y + attribute \src "libresoc.v:190245.18-190245.122" + wire $or$libresoc.v:190245$13001_Y + attribute \src "libresoc.v:190246.18-190246.124" + wire $or$libresoc.v:190246$13002_Y + attribute \src "libresoc.v:190247.18-190247.194" + wire width 6 $or$libresoc.v:190247$13003_Y + attribute \src "libresoc.v:190248.18-190248.194" + wire width 6 $or$libresoc.v:190248$13004_Y + attribute \src "libresoc.v:190252.18-190252.120" + wire width 6 $or$libresoc.v:190252$13008_Y + attribute \src "libresoc.v:190217.17-190217.105" + wire $reduce_and$libresoc.v:190217$12973_Y + attribute \src "libresoc.v:190230.18-190230.106" + wire $reduce_or$libresoc.v:190230$12986_Y + attribute \src "libresoc.v:190233.18-190233.113" + wire $reduce_or$libresoc.v:190233$12989_Y + attribute \src "libresoc.v:190234.18-190234.112" + wire $reduce_or$libresoc.v:190234$12990_Y + attribute \src "libresoc.v:190259.18-190259.118" + wire width 64 $ternary$libresoc.v:190259$13015_Y + attribute \src "libresoc.v:190260.18-190260.118" + wire width 64 $ternary$libresoc.v:190260$13016_Y + attribute \src "libresoc.v:190261.18-190261.118" + wire width 64 $ternary$libresoc.v:190261$13017_Y + attribute \src "libresoc.v:190262.18-190262.118" + wire $ternary$libresoc.v:190262$13018_Y + attribute \src "libresoc.v:190263.18-190263.118" + wire width 2 $ternary$libresoc.v:190263$13019_Y + attribute \src "libresoc.v:190264.18-190264.118" + wire width 2 $ternary$libresoc.v:190264$13020_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" wire \$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" @@ -390145,9 +361528,9 @@ module \spr0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 31 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 7 \cu_busy_o @@ -390233,7 +361616,7 @@ module \spr0 wire width 2 output 22 \dest6_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 27 \fast1_ok - attribute \src "libresoc.v:188272.7-188272.15" + attribute \src "libresoc.v:189589.7-189589.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 17 \o_ok @@ -390444,7 +361827,7 @@ module \spr0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 25 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:188884$12971 + cell $and $and$libresoc.v:190201$12957 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390452,10 +361835,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \alu_spr0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:188884$12971_Y + connect \Y $and$libresoc.v:190201$12957_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:188885$12972 + cell $and $and$libresoc.v:190202$12958 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -390463,10 +361846,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:188885$12972_Y + connect \Y $and$libresoc.v:190202$12958_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:188886$12973 + cell $and $and$libresoc.v:190203$12959 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -390474,10 +361857,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \$102 connect \B 6'111111 - connect \Y $and$libresoc.v:188886$12973_Y + connect \Y $and$libresoc.v:190203$12959_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:188888$12975 + cell $and $and$libresoc.v:190205$12961 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -390485,10 +361868,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \$104 connect \B \$106 - connect \Y $and$libresoc.v:188888$12975_Y + connect \Y $and$libresoc.v:190205$12961_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:188889$12976 + cell $and $and$libresoc.v:190206$12962 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390496,10 +361879,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:188889$12976_Y + connect \Y $and$libresoc.v:190206$12962_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:188890$12977 + cell $and $and$libresoc.v:190207$12963 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390507,10 +361890,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:188890$12977_Y + connect \Y $and$libresoc.v:190207$12963_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:188891$12978 + cell $and $and$libresoc.v:190208$12964 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390518,10 +361901,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:188891$12978_Y + connect \Y $and$libresoc.v:190208$12964_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:188892$12979 + cell $and $and$libresoc.v:190209$12965 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390529,10 +361912,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:188892$12979_Y + connect \Y $and$libresoc.v:190209$12965_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:188893$12980 + cell $and $and$libresoc.v:190210$12966 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390540,10 +361923,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:188893$12980_Y + connect \Y $and$libresoc.v:190210$12966_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:188895$12982 + cell $and $and$libresoc.v:190212$12968 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390551,10 +361934,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:188895$12982_Y + connect \Y $and$libresoc.v:190212$12968_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:188896$12983 + cell $and $and$libresoc.v:190213$12969 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -390562,10 +361945,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \req_l_q_req connect \B { \$110 \$112 \$114 \$116 \$118 \$120 } - connect \Y $and$libresoc.v:188896$12983_Y + connect \Y $and$libresoc.v:190213$12969_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:188897$12984 + cell $and $and$libresoc.v:190214$12970 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -390573,10 +361956,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \$122 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:188897$12984_Y + connect \Y $and$libresoc.v:190214$12970_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:188898$12985 + cell $and $and$libresoc.v:190215$12971 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390584,10 +361967,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:188898$12985_Y + connect \Y $and$libresoc.v:190215$12971_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:188899$12986 + cell $and $and$libresoc.v:190216$12972 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390595,10 +361978,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:188899$12986_Y + connect \Y $and$libresoc.v:190216$12972_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:188901$12988 + cell $and $and$libresoc.v:190218$12974 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390606,10 +361989,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:188901$12988_Y + connect \Y $and$libresoc.v:190218$12974_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:188902$12989 + cell $and $and$libresoc.v:190219$12975 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390617,10 +362000,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o - connect \Y $and$libresoc.v:188902$12989_Y + connect \Y $and$libresoc.v:190219$12975_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:188903$12990 + cell $and $and$libresoc.v:190220$12976 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390628,10 +362011,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [4] connect \B \cu_busy_o - connect \Y $and$libresoc.v:188903$12990_Y + connect \Y $and$libresoc.v:190220$12976_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:188904$12991 + cell $and $and$libresoc.v:190221$12977 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390639,10 +362022,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [5] connect \B \cu_busy_o - connect \Y $and$libresoc.v:188904$12991_Y + connect \Y $and$libresoc.v:190221$12977_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:188905$12992 + cell $and $and$libresoc.v:190222$12978 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390650,10 +362033,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$6 connect \B \$8 - connect \Y $and$libresoc.v:188905$12992_Y + connect \Y $and$libresoc.v:190222$12978_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:188907$12994 + cell $and $and$libresoc.v:190224$12980 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390661,10 +362044,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$16 - connect \Y $and$libresoc.v:188907$12994_Y + connect \Y $and$libresoc.v:190224$12980_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:188909$12996 + cell $and $and$libresoc.v:190226$12982 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390672,10 +362055,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$20 - connect \Y $and$libresoc.v:188909$12996_Y + connect \Y $and$libresoc.v:190226$12982_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:188910$12997 + cell $and $and$libresoc.v:190227$12983 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -390683,10 +362066,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:188910$12997_Y + connect \Y $and$libresoc.v:190227$12983_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:188912$12999 + cell $and $and$libresoc.v:190229$12985 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -390694,10 +362077,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \cu_wr__rel_o connect \B \$28 - connect \Y $and$libresoc.v:188912$12999_Y + connect \Y $and$libresoc.v:190229$12985_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:188915$13002 + cell $and $and$libresoc.v:190232$12988 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390705,10 +362088,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$26 - connect \Y $and$libresoc.v:188915$13002_Y + connect \Y $and$libresoc.v:190232$12988_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:188920$13007 + cell $and $and$libresoc.v:190237$12993 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390716,10 +362099,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$42 - connect \Y $and$libresoc.v:188920$13007_Y + connect \Y $and$libresoc.v:190237$12993_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:188921$13008 + cell $and $and$libresoc.v:190238$12994 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -390727,10 +362110,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:188921$13008_Y + connect \Y $and$libresoc.v:190238$12994_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:188923$13010 + cell $and $and$libresoc.v:190240$12996 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390738,10 +362121,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$44 connect \B \$48 - connect \Y $and$libresoc.v:188923$13010_Y + connect \Y $and$libresoc.v:190240$12996_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:188925$13012 + cell $and $and$libresoc.v:190242$12998 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390749,10 +362132,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$52 connect \B \alu_spr0_n_ready_i - connect \Y $and$libresoc.v:188925$13012_Y + connect \Y $and$libresoc.v:190242$12998_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:188926$13013 + cell $and $and$libresoc.v:190243$12999 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390760,10 +362143,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$54 connect \B \alu_spr0_n_valid_o - connect \Y $and$libresoc.v:188926$13013_Y + connect \Y $and$libresoc.v:190243$12999_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:188927$13014 + cell $and $and$libresoc.v:190244$13000 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390771,10 +362154,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$56 connect \B \cu_busy_o - connect \Y $and$libresoc.v:188927$13014_Y + connect \Y $and$libresoc.v:190244$13000_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:188932$13019 + cell $and $and$libresoc.v:190249$13005 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390782,10 +362165,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \alu_spr0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:188932$13019_Y + connect \Y $and$libresoc.v:190249$13005_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:188933$13020 + cell $and $and$libresoc.v:190250$13006 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390793,10 +362176,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:188933$13020_Y + connect \Y $and$libresoc.v:190250$13006_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:188934$13021 + cell $and $and$libresoc.v:190251$13007 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -390804,10 +362187,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:188934$13021_Y + connect \Y $and$libresoc.v:190251$13007_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:188936$13023 + cell $and $and$libresoc.v:190253$13009 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390815,10 +362198,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:188936$13023_Y + connect \Y $and$libresoc.v:190253$13009_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:188937$13024 + cell $and $and$libresoc.v:190254$13010 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390826,10 +362209,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \spr1_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:188937$13024_Y + connect \Y $and$libresoc.v:190254$13010_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:188938$13025 + cell $and $and$libresoc.v:190255$13011 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390837,10 +362220,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \fast1_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:188938$13025_Y + connect \Y $and$libresoc.v:190255$13011_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:188939$13026 + cell $and $and$libresoc.v:190256$13012 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390848,10 +362231,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \xer_so_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:188939$13026_Y + connect \Y $and$libresoc.v:190256$13012_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:188940$13027 + cell $and $and$libresoc.v:190257$13013 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390859,10 +362242,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \xer_ov_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:188940$13027_Y + connect \Y $and$libresoc.v:190257$13013_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:188941$13028 + cell $and $and$libresoc.v:190258$13014 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390870,10 +362253,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \xer_ca_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:188941$13028_Y + connect \Y $and$libresoc.v:190258$13014_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:188948$13035 + cell $and $and$libresoc.v:190265$13021 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390881,10 +362264,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \alu_spr0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:188948$13035_Y + connect \Y $and$libresoc.v:190265$13021_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:188922$13009 + cell $eq $eq$libresoc.v:190239$12995 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -390892,10 +362275,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$46 connect \B 1'0 - connect \Y $eq$libresoc.v:188922$13009_Y + connect \Y $eq$libresoc.v:190239$12995_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:188924$13011 + cell $eq $eq$libresoc.v:190241$12997 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -390903,66 +362286,66 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:188924$13011_Y + connect \Y $eq$libresoc.v:190241$12997_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:188883$12970 + cell $not $not$libresoc.v:190200$12956 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:188883$12970_Y + connect \Y $not$libresoc.v:190200$12956_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:188887$12974 + cell $not $not$libresoc.v:190204$12960 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:188887$12974_Y + connect \Y $not$libresoc.v:190204$12960_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:188906$12993 + cell $not $not$libresoc.v:190223$12979 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:188906$12993_Y + connect \Y $not$libresoc.v:190223$12979_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:188908$12995 + cell $not $not$libresoc.v:190225$12981 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:188908$12995_Y + connect \Y $not$libresoc.v:190225$12981_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:188911$12998 + cell $not $not$libresoc.v:190228$12984 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:188911$12998_Y + connect \Y $not$libresoc.v:190228$12984_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:188914$13001 + cell $not $not$libresoc.v:190231$12987 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$27 - connect \Y $not$libresoc.v:188914$13001_Y + connect \Y $not$libresoc.v:190231$12987_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:188919$13006 + cell $not $not$libresoc.v:190236$12992 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_spr0_n_ready_i - connect \Y $not$libresoc.v:188919$13006_Y + connect \Y $not$libresoc.v:190236$12992_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:188894$12981 + cell $or $or$libresoc.v:190211$12967 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -390970,10 +362353,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \$9 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:188894$12981_Y + connect \Y $or$libresoc.v:190211$12967_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:188918$13005 + cell $or $or$libresoc.v:190235$12991 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390981,10 +362364,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \$36 connect \B \$38 - connect \Y $or$libresoc.v:188918$13005_Y + connect \Y $or$libresoc.v:190235$12991_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:188928$13015 + cell $or $or$libresoc.v:190245$13001 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -390992,10 +362375,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:188928$13015_Y + connect \Y $or$libresoc.v:190245$13001_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:188929$13016 + cell $or $or$libresoc.v:190246$13002 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -391003,10 +362386,10 @@ module \spr0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:188929$13016_Y + connect \Y $or$libresoc.v:190246$13002_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:188930$13017 + cell $or $or$libresoc.v:190247$13003 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -391014,10 +362397,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:188930$13017_Y + connect \Y $or$libresoc.v:190247$13003_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:188931$13018 + cell $or $or$libresoc.v:190248$13004 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -391025,10 +362408,10 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:188931$13018_Y + connect \Y $or$libresoc.v:190248$13004_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:188935$13022 + cell $or $or$libresoc.v:190252$13008 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -391036,90 +362419,90 @@ module \spr0 parameter \Y_WIDTH 6 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:188935$13022_Y + connect \Y $or$libresoc.v:190252$13008_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:188900$12987 + cell $reduce_and $reduce_and$libresoc.v:190217$12973 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \$11 - connect \Y $reduce_and$libresoc.v:188900$12987_Y + connect \Y $reduce_and$libresoc.v:190217$12973_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:188913$13000 + cell $reduce_or $reduce_or$libresoc.v:190230$12986 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \$30 - connect \Y $reduce_or$libresoc.v:188913$13000_Y + connect \Y $reduce_or$libresoc.v:190230$12986_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:188916$13003 + cell $reduce_or $reduce_or$libresoc.v:190233$12989 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:188916$13003_Y + connect \Y $reduce_or$libresoc.v:190233$12989_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:188917$13004 + cell $reduce_or $reduce_or$libresoc.v:190234$12990 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:188917$13004_Y + connect \Y $reduce_or$libresoc.v:190234$12990_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:188942$13029 + cell $mux $ternary$libresoc.v:190259$13015 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:188942$13029_Y + connect \Y $ternary$libresoc.v:190259$13015_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:188943$13030 + cell $mux $ternary$libresoc.v:190260$13016 parameter \WIDTH 64 connect \A \src_r1 connect \B \src2_i connect \S \src_l_q_src [1] - connect \Y $ternary$libresoc.v:188943$13030_Y + connect \Y $ternary$libresoc.v:190260$13016_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:188944$13031 + cell $mux $ternary$libresoc.v:190261$13017 parameter \WIDTH 64 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:188944$13031_Y + connect \Y $ternary$libresoc.v:190261$13017_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:188945$13032 + cell $mux $ternary$libresoc.v:190262$13018 parameter \WIDTH 1 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:188945$13032_Y + connect \Y $ternary$libresoc.v:190262$13018_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:188946$13033 + cell $mux $ternary$libresoc.v:190263$13019 parameter \WIDTH 2 connect \A \src_r4 connect \B \src5_i connect \S \src_l_q_src [4] - connect \Y $ternary$libresoc.v:188946$13033_Y + connect \Y $ternary$libresoc.v:190263$13019_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:188947$13034 + cell $mux $ternary$libresoc.v:190264$13020 parameter \WIDTH 2 connect \A \src_r5 connect \B \src6_i connect \S \src_l_q_src [5] - connect \Y $ternary$libresoc.v:188947$13034_Y + connect \Y $ternary$libresoc.v:190264$13020_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:189023.14-189029.4" + attribute \src "libresoc.v:190340.14-190346.4" cell \alu_l$73 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -391128,7 +362511,7 @@ module \spr0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:189030.12-189059.4" + attribute \src "libresoc.v:190347.12-190376.4" cell \alu_spr0 \alu_spr0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -391160,7 +362543,7 @@ module \spr0 connect \xer_so_ok \xer_so_ok end attribute \module_not_derived 1 - attribute \src "libresoc.v:189060.15-189066.4" + attribute \src "libresoc.v:190377.15-190383.4" cell \alui_l$72 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -391169,7 +362552,7 @@ module \spr0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:189067.14-189073.4" + attribute \src "libresoc.v:190384.14-190390.4" cell \opc_l$68 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -391178,7 +362561,7 @@ module \spr0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:189074.14-189080.4" + attribute \src "libresoc.v:190391.14-190397.4" cell \req_l$69 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -391187,7 +362570,7 @@ module \spr0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:189081.14-189087.4" + attribute \src "libresoc.v:190398.14-190404.4" cell \rok_l$71 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -391196,7 +362579,7 @@ module \spr0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:189088.14-189093.4" + attribute \src "libresoc.v:190405.14-190410.4" cell \rst_l$70 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -391204,7 +362587,7 @@ module \spr0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:189094.14-189100.4" + attribute \src "libresoc.v:190411.14-190417.4" cell \src_l$67 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -391212,577 +362595,577 @@ module \spr0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:188272.7-188272.20" - process $proc$libresoc.v:188272$13194 + attribute \src "libresoc.v:189589.7-189589.20" + process $proc$libresoc.v:189589$13180 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:188408.7-188408.24" - process $proc$libresoc.v:188408$13195 + attribute \src "libresoc.v:189725.7-189725.24" + process $proc$libresoc.v:189725$13181 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:188418.7-188418.26" - process $proc$libresoc.v:188418$13196 + attribute \src "libresoc.v:189735.7-189735.26" + process $proc$libresoc.v:189735$13182 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:188426.7-188426.25" - process $proc$libresoc.v:188426$13197 + attribute \src "libresoc.v:189743.7-189743.25" + process $proc$libresoc.v:189743$13183 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:188471.14-188471.49" - process $proc$libresoc.v:188471$13198 + attribute \src "libresoc.v:189788.14-189788.49" + process $proc$libresoc.v:189788$13184 assign { } { } assign $1\alu_spr0_spr_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_spr0_spr_op__fn_unit $1\alu_spr0_spr_op__fn_unit[13:0] end - attribute \src "libresoc.v:188475.14-188475.43" - process $proc$libresoc.v:188475$13199 + attribute \src "libresoc.v:189792.14-189792.43" + process $proc$libresoc.v:189792$13185 assign { } { } assign $1\alu_spr0_spr_op__insn[31:0] 0 sync always sync init update \alu_spr0_spr_op__insn $1\alu_spr0_spr_op__insn[31:0] end - attribute \src "libresoc.v:188554.13-188554.47" - process $proc$libresoc.v:188554$13200 + attribute \src "libresoc.v:189871.13-189871.47" + process $proc$libresoc.v:189871$13186 assign { } { } assign $1\alu_spr0_spr_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_spr0_spr_op__insn_type $1\alu_spr0_spr_op__insn_type[6:0] end - attribute \src "libresoc.v:188558.7-188558.39" - process $proc$libresoc.v:188558$13201 + attribute \src "libresoc.v:189875.7-189875.39" + process $proc$libresoc.v:189875$13187 assign { } { } assign $1\alu_spr0_spr_op__is_32bit[0:0] 1'0 sync always sync init update \alu_spr0_spr_op__is_32bit $1\alu_spr0_spr_op__is_32bit[0:0] end - attribute \src "libresoc.v:188576.7-188576.27" - process $proc$libresoc.v:188576$13202 + attribute \src "libresoc.v:189893.7-189893.27" + process $proc$libresoc.v:189893$13188 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:188608.14-188608.47" - process $proc$libresoc.v:188608$13203 + attribute \src "libresoc.v:189925.14-189925.47" + process $proc$libresoc.v:189925$13189 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:188612.7-188612.27" - process $proc$libresoc.v:188612$13204 + attribute \src "libresoc.v:189929.7-189929.27" + process $proc$libresoc.v:189929$13190 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:188616.14-188616.50" - process $proc$libresoc.v:188616$13205 + attribute \src "libresoc.v:189933.14-189933.50" + process $proc$libresoc.v:189933$13191 assign { } { } assign $1\data_r1__spr1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r1__spr1 $1\data_r1__spr1[63:0] end - attribute \src "libresoc.v:188620.7-188620.30" - process $proc$libresoc.v:188620$13206 + attribute \src "libresoc.v:189937.7-189937.30" + process $proc$libresoc.v:189937$13192 assign { } { } assign $1\data_r1__spr1_ok[0:0] 1'0 sync always sync init update \data_r1__spr1_ok $1\data_r1__spr1_ok[0:0] end - attribute \src "libresoc.v:188624.14-188624.51" - process $proc$libresoc.v:188624$13207 + attribute \src "libresoc.v:189941.14-189941.51" + process $proc$libresoc.v:189941$13193 assign { } { } assign $1\data_r2__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r2__fast1 $1\data_r2__fast1[63:0] end - attribute \src "libresoc.v:188628.7-188628.31" - process $proc$libresoc.v:188628$13208 + attribute \src "libresoc.v:189945.7-189945.31" + process $proc$libresoc.v:189945$13194 assign { } { } assign $1\data_r2__fast1_ok[0:0] 1'0 sync always sync init update \data_r2__fast1_ok $1\data_r2__fast1_ok[0:0] end - attribute \src "libresoc.v:188632.7-188632.29" - process $proc$libresoc.v:188632$13209 + attribute \src "libresoc.v:189949.7-189949.29" + process $proc$libresoc.v:189949$13195 assign { } { } assign $1\data_r3__xer_so[0:0] 1'0 sync always sync init update \data_r3__xer_so $1\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:188636.7-188636.32" - process $proc$libresoc.v:188636$13210 + attribute \src "libresoc.v:189953.7-189953.32" + process $proc$libresoc.v:189953$13196 assign { } { } assign $1\data_r3__xer_so_ok[0:0] 1'0 sync always sync init update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:188640.13-188640.35" - process $proc$libresoc.v:188640$13211 + attribute \src "libresoc.v:189957.13-189957.35" + process $proc$libresoc.v:189957$13197 assign { } { } assign $1\data_r4__xer_ov[1:0] 2'00 sync always sync init update \data_r4__xer_ov $1\data_r4__xer_ov[1:0] end - attribute \src "libresoc.v:188644.7-188644.32" - process $proc$libresoc.v:188644$13212 + attribute \src "libresoc.v:189961.7-189961.32" + process $proc$libresoc.v:189961$13198 assign { } { } assign $1\data_r4__xer_ov_ok[0:0] 1'0 sync always sync init update \data_r4__xer_ov_ok $1\data_r4__xer_ov_ok[0:0] end - attribute \src "libresoc.v:188648.13-188648.35" - process $proc$libresoc.v:188648$13213 + attribute \src "libresoc.v:189965.13-189965.35" + process $proc$libresoc.v:189965$13199 assign { } { } assign $1\data_r5__xer_ca[1:0] 2'00 sync always sync init update \data_r5__xer_ca $1\data_r5__xer_ca[1:0] end - attribute \src "libresoc.v:188652.7-188652.32" - process $proc$libresoc.v:188652$13214 + attribute \src "libresoc.v:189969.7-189969.32" + process $proc$libresoc.v:189969$13200 assign { } { } assign $1\data_r5__xer_ca_ok[0:0] 1'0 sync always sync init update \data_r5__xer_ca_ok $1\data_r5__xer_ca_ok[0:0] end - attribute \src "libresoc.v:188680.7-188680.25" - process $proc$libresoc.v:188680$13215 + attribute \src "libresoc.v:189997.7-189997.25" + process $proc$libresoc.v:189997$13201 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:188684.7-188684.25" - process $proc$libresoc.v:188684$13216 + attribute \src "libresoc.v:190001.7-190001.25" + process $proc$libresoc.v:190001$13202 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:188786.13-188786.31" - process $proc$libresoc.v:188786$13217 + attribute \src "libresoc.v:190103.13-190103.31" + process $proc$libresoc.v:190103$13203 assign { } { } assign $1\prev_wr_go[5:0] 6'000000 sync always sync init update \prev_wr_go $1\prev_wr_go[5:0] end - attribute \src "libresoc.v:188794.13-188794.32" - process $proc$libresoc.v:188794$13218 + attribute \src "libresoc.v:190111.13-190111.32" + process $proc$libresoc.v:190111$13204 assign { } { } assign $1\req_l_r_req[5:0] 6'111111 sync always sync init update \req_l_r_req $1\req_l_r_req[5:0] end - attribute \src "libresoc.v:188798.13-188798.32" - process $proc$libresoc.v:188798$13219 + attribute \src "libresoc.v:190115.13-190115.32" + process $proc$libresoc.v:190115$13205 assign { } { } assign $1\req_l_s_req[5:0] 6'000000 sync always sync init update \req_l_s_req $1\req_l_s_req[5:0] end - attribute \src "libresoc.v:188810.7-188810.26" - process $proc$libresoc.v:188810$13220 + attribute \src "libresoc.v:190127.7-190127.26" + process $proc$libresoc.v:190127$13206 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:188814.7-188814.26" - process $proc$libresoc.v:188814$13221 + attribute \src "libresoc.v:190131.7-190131.26" + process $proc$libresoc.v:190131$13207 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:188818.7-188818.25" - process $proc$libresoc.v:188818$13222 + attribute \src "libresoc.v:190135.7-190135.25" + process $proc$libresoc.v:190135$13208 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:188822.7-188822.25" - process $proc$libresoc.v:188822$13223 + attribute \src "libresoc.v:190139.7-190139.25" + process $proc$libresoc.v:190139$13209 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:188844.13-188844.32" - process $proc$libresoc.v:188844$13224 + attribute \src "libresoc.v:190161.13-190161.32" + process $proc$libresoc.v:190161$13210 assign { } { } assign $1\src_l_r_src[5:0] 6'111111 sync always sync init update \src_l_r_src $1\src_l_r_src[5:0] end - attribute \src "libresoc.v:188848.13-188848.32" - process $proc$libresoc.v:188848$13225 + attribute \src "libresoc.v:190165.13-190165.32" + process $proc$libresoc.v:190165$13211 assign { } { } assign $1\src_l_s_src[5:0] 6'000000 sync always sync init update \src_l_s_src $1\src_l_s_src[5:0] end - attribute \src "libresoc.v:188852.14-188852.43" - process $proc$libresoc.v:188852$13226 + attribute \src "libresoc.v:190169.14-190169.43" + process $proc$libresoc.v:190169$13212 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:188856.14-188856.43" - process $proc$libresoc.v:188856$13227 + attribute \src "libresoc.v:190173.14-190173.43" + process $proc$libresoc.v:190173$13213 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:188860.14-188860.43" - process $proc$libresoc.v:188860$13228 + attribute \src "libresoc.v:190177.14-190177.43" + process $proc$libresoc.v:190177$13214 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end - attribute \src "libresoc.v:188864.7-188864.20" - process $proc$libresoc.v:188864$13229 + attribute \src "libresoc.v:190181.7-190181.20" + process $proc$libresoc.v:190181$13215 assign { } { } assign $1\src_r3[0:0] 1'0 sync always sync init update \src_r3 $1\src_r3[0:0] end - attribute \src "libresoc.v:188868.13-188868.26" - process $proc$libresoc.v:188868$13230 + attribute \src "libresoc.v:190185.13-190185.26" + process $proc$libresoc.v:190185$13216 assign { } { } assign $1\src_r4[1:0] 2'00 sync always sync init update \src_r4 $1\src_r4[1:0] end - attribute \src "libresoc.v:188872.13-188872.26" - process $proc$libresoc.v:188872$13231 + attribute \src "libresoc.v:190189.13-190189.26" + process $proc$libresoc.v:190189$13217 assign { } { } assign $1\src_r5[1:0] 2'00 sync always sync init update \src_r5 $1\src_r5[1:0] end - attribute \src "libresoc.v:188949.3-188950.39" - process $proc$libresoc.v:188949$13036 + attribute \src "libresoc.v:190266.3-190267.39" + process $proc$libresoc.v:190266$13022 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:188951.3-188952.43" - process $proc$libresoc.v:188951$13037 + attribute \src "libresoc.v:190268.3-190269.43" + process $proc$libresoc.v:190268$13023 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:188953.3-188954.29" - process $proc$libresoc.v:188953$13038 + attribute \src "libresoc.v:190270.3-190271.29" + process $proc$libresoc.v:190270$13024 assign { } { } assign $0\src_r5[1:0] \src_r5$next sync posedge \coresync_clk update \src_r5 $0\src_r5[1:0] end - attribute \src "libresoc.v:188955.3-188956.29" - process $proc$libresoc.v:188955$13039 + attribute \src "libresoc.v:190272.3-190273.29" + process $proc$libresoc.v:190272$13025 assign { } { } assign $0\src_r4[1:0] \src_r4$next sync posedge \coresync_clk update \src_r4 $0\src_r4[1:0] end - attribute \src "libresoc.v:188957.3-188958.29" - process $proc$libresoc.v:188957$13040 + attribute \src "libresoc.v:190274.3-190275.29" + process $proc$libresoc.v:190274$13026 assign { } { } assign $0\src_r3[0:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[0:0] end - attribute \src "libresoc.v:188959.3-188960.29" - process $proc$libresoc.v:188959$13041 + attribute \src "libresoc.v:190276.3-190277.29" + process $proc$libresoc.v:190276$13027 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end - attribute \src "libresoc.v:188961.3-188962.29" - process $proc$libresoc.v:188961$13042 + attribute \src "libresoc.v:190278.3-190279.29" + process $proc$libresoc.v:190278$13028 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:188963.3-188964.29" - process $proc$libresoc.v:188963$13043 + attribute \src "libresoc.v:190280.3-190281.29" + process $proc$libresoc.v:190280$13029 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:188965.3-188966.47" - process $proc$libresoc.v:188965$13044 + attribute \src "libresoc.v:190282.3-190283.47" + process $proc$libresoc.v:190282$13030 assign { } { } assign $0\data_r5__xer_ca[1:0] \data_r5__xer_ca$next sync posedge \coresync_clk update \data_r5__xer_ca $0\data_r5__xer_ca[1:0] end - attribute \src "libresoc.v:188967.3-188968.53" - process $proc$libresoc.v:188967$13045 + attribute \src "libresoc.v:190284.3-190285.53" + process $proc$libresoc.v:190284$13031 assign { } { } assign $0\data_r5__xer_ca_ok[0:0] \data_r5__xer_ca_ok$next sync posedge \coresync_clk update \data_r5__xer_ca_ok $0\data_r5__xer_ca_ok[0:0] end - attribute \src "libresoc.v:188969.3-188970.47" - process $proc$libresoc.v:188969$13046 + attribute \src "libresoc.v:190286.3-190287.47" + process $proc$libresoc.v:190286$13032 assign { } { } assign $0\data_r4__xer_ov[1:0] \data_r4__xer_ov$next sync posedge \coresync_clk update \data_r4__xer_ov $0\data_r4__xer_ov[1:0] end - attribute \src "libresoc.v:188971.3-188972.53" - process $proc$libresoc.v:188971$13047 + attribute \src "libresoc.v:190288.3-190289.53" + process $proc$libresoc.v:190288$13033 assign { } { } assign $0\data_r4__xer_ov_ok[0:0] \data_r4__xer_ov_ok$next sync posedge \coresync_clk update \data_r4__xer_ov_ok $0\data_r4__xer_ov_ok[0:0] end - attribute \src "libresoc.v:188973.3-188974.47" - process $proc$libresoc.v:188973$13048 + attribute \src "libresoc.v:190290.3-190291.47" + process $proc$libresoc.v:190290$13034 assign { } { } assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next sync posedge \coresync_clk update \data_r3__xer_so $0\data_r3__xer_so[0:0] end - attribute \src "libresoc.v:188975.3-188976.53" - process $proc$libresoc.v:188975$13049 + attribute \src "libresoc.v:190292.3-190293.53" + process $proc$libresoc.v:190292$13035 assign { } { } assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next sync posedge \coresync_clk update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] end - attribute \src "libresoc.v:188977.3-188978.45" - process $proc$libresoc.v:188977$13050 + attribute \src "libresoc.v:190294.3-190295.45" + process $proc$libresoc.v:190294$13036 assign { } { } assign $0\data_r2__fast1[63:0] \data_r2__fast1$next sync posedge \coresync_clk update \data_r2__fast1 $0\data_r2__fast1[63:0] end - attribute \src "libresoc.v:188979.3-188980.51" - process $proc$libresoc.v:188979$13051 + attribute \src "libresoc.v:190296.3-190297.51" + process $proc$libresoc.v:190296$13037 assign { } { } assign $0\data_r2__fast1_ok[0:0] \data_r2__fast1_ok$next sync posedge \coresync_clk update \data_r2__fast1_ok $0\data_r2__fast1_ok[0:0] end - attribute \src "libresoc.v:188981.3-188982.43" - process $proc$libresoc.v:188981$13052 + attribute \src "libresoc.v:190298.3-190299.43" + process $proc$libresoc.v:190298$13038 assign { } { } assign $0\data_r1__spr1[63:0] \data_r1__spr1$next sync posedge \coresync_clk update \data_r1__spr1 $0\data_r1__spr1[63:0] end - attribute \src "libresoc.v:188983.3-188984.49" - process $proc$libresoc.v:188983$13053 + attribute \src "libresoc.v:190300.3-190301.49" + process $proc$libresoc.v:190300$13039 assign { } { } assign $0\data_r1__spr1_ok[0:0] \data_r1__spr1_ok$next sync posedge \coresync_clk update \data_r1__spr1_ok $0\data_r1__spr1_ok[0:0] end - attribute \src "libresoc.v:188985.3-188986.37" - process $proc$libresoc.v:188985$13054 + attribute \src "libresoc.v:190302.3-190303.37" + process $proc$libresoc.v:190302$13040 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:188987.3-188988.43" - process $proc$libresoc.v:188987$13055 + attribute \src "libresoc.v:190304.3-190305.43" + process $proc$libresoc.v:190304$13041 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:188989.3-188990.69" - process $proc$libresoc.v:188989$13056 + attribute \src "libresoc.v:190306.3-190307.69" + process $proc$libresoc.v:190306$13042 assign { } { } assign $0\alu_spr0_spr_op__insn_type[6:0] \alu_spr0_spr_op__insn_type$next sync posedge \coresync_clk update \alu_spr0_spr_op__insn_type $0\alu_spr0_spr_op__insn_type[6:0] end - attribute \src "libresoc.v:188991.3-188992.65" - process $proc$libresoc.v:188991$13057 + attribute \src "libresoc.v:190308.3-190309.65" + process $proc$libresoc.v:190308$13043 assign { } { } assign $0\alu_spr0_spr_op__fn_unit[13:0] \alu_spr0_spr_op__fn_unit$next sync posedge \coresync_clk update \alu_spr0_spr_op__fn_unit $0\alu_spr0_spr_op__fn_unit[13:0] end - attribute \src "libresoc.v:188993.3-188994.59" - process $proc$libresoc.v:188993$13058 + attribute \src "libresoc.v:190310.3-190311.59" + process $proc$libresoc.v:190310$13044 assign { } { } assign $0\alu_spr0_spr_op__insn[31:0] \alu_spr0_spr_op__insn$next sync posedge \coresync_clk update \alu_spr0_spr_op__insn $0\alu_spr0_spr_op__insn[31:0] end - attribute \src "libresoc.v:188995.3-188996.67" - process $proc$libresoc.v:188995$13059 + attribute \src "libresoc.v:190312.3-190313.67" + process $proc$libresoc.v:190312$13045 assign { } { } assign $0\alu_spr0_spr_op__is_32bit[0:0] \alu_spr0_spr_op__is_32bit$next sync posedge \coresync_clk update \alu_spr0_spr_op__is_32bit $0\alu_spr0_spr_op__is_32bit[0:0] end - attribute \src "libresoc.v:188997.3-188998.39" - process $proc$libresoc.v:188997$13060 + attribute \src "libresoc.v:190314.3-190315.39" + process $proc$libresoc.v:190314$13046 assign { } { } assign $0\req_l_r_req[5:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[5:0] end - attribute \src "libresoc.v:188999.3-189000.39" - process $proc$libresoc.v:188999$13061 + attribute \src "libresoc.v:190316.3-190317.39" + process $proc$libresoc.v:190316$13047 assign { } { } assign $0\req_l_s_req[5:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[5:0] end - attribute \src "libresoc.v:189001.3-189002.39" - process $proc$libresoc.v:189001$13062 + attribute \src "libresoc.v:190318.3-190319.39" + process $proc$libresoc.v:190318$13048 assign { } { } assign $0\src_l_r_src[5:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[5:0] end - attribute \src "libresoc.v:189003.3-189004.39" - process $proc$libresoc.v:189003$13063 + attribute \src "libresoc.v:190320.3-190321.39" + process $proc$libresoc.v:190320$13049 assign { } { } assign $0\src_l_s_src[5:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[5:0] end - attribute \src "libresoc.v:189005.3-189006.39" - process $proc$libresoc.v:189005$13064 + attribute \src "libresoc.v:190322.3-190323.39" + process $proc$libresoc.v:190322$13050 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:189007.3-189008.39" - process $proc$libresoc.v:189007$13065 + attribute \src "libresoc.v:190324.3-190325.39" + process $proc$libresoc.v:190324$13051 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:189009.3-189010.39" - process $proc$libresoc.v:189009$13066 + attribute \src "libresoc.v:190326.3-190327.39" + process $proc$libresoc.v:190326$13052 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:189011.3-189012.39" - process $proc$libresoc.v:189011$13067 + attribute \src "libresoc.v:190328.3-190329.39" + process $proc$libresoc.v:190328$13053 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:189013.3-189014.41" - process $proc$libresoc.v:189013$13068 + attribute \src "libresoc.v:190330.3-190331.41" + process $proc$libresoc.v:190330$13054 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:189015.3-189016.41" - process $proc$libresoc.v:189015$13069 + attribute \src "libresoc.v:190332.3-190333.41" + process $proc$libresoc.v:190332$13055 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:189017.3-189018.37" - process $proc$libresoc.v:189017$13070 + attribute \src "libresoc.v:190334.3-190335.37" + process $proc$libresoc.v:190334$13056 assign { } { } assign $0\prev_wr_go[5:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[5:0] end - attribute \src "libresoc.v:189019.3-189020.40" - process $proc$libresoc.v:189019$13071 + attribute \src "libresoc.v:190336.3-190337.40" + process $proc$libresoc.v:190336$13057 assign { } { } assign $0\alu_done_dly[0:0] \alu_spr0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:189021.3-189022.25" - process $proc$libresoc.v:189021$13072 + attribute \src "libresoc.v:190338.3-190339.25" + process $proc$libresoc.v:190338$13058 assign { } { } assign $0\all_rd_dly[0:0] \$14 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:189101.3-189110.6" - process $proc$libresoc.v:189101$13073 + attribute \src "libresoc.v:190418.3-190427.6" + process $proc$libresoc.v:190418$13059 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:189102.5-189102.29" + attribute \src "libresoc.v:190419.5-190419.29" switch \initial - attribute \src "libresoc.v:189102.9-189102.17" + attribute \src "libresoc.v:190419.9-190419.17" case 1'1 case end @@ -391798,14 +363181,14 @@ module \spr0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:189111.3-189119.6" - process $proc$libresoc.v:189111$13074 + attribute \src "libresoc.v:190428.3-190436.6" + process $proc$libresoc.v:190428$13060 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$13075 $1\rok_l_s_rdok$next[0:0]$13076 - attribute \src "libresoc.v:189112.5-189112.29" + assign $0\rok_l_s_rdok$next[0:0]$13061 $1\rok_l_s_rdok$next[0:0]$13062 + attribute \src "libresoc.v:190429.5-190429.29" switch \initial - attribute \src "libresoc.v:189112.9-189112.17" + attribute \src "libresoc.v:190429.9-190429.17" case 1'1 case end @@ -391814,21 +363197,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$13076 1'0 + assign $1\rok_l_s_rdok$next[0:0]$13062 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$13076 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$13062 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$13075 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$13061 end - attribute \src "libresoc.v:189120.3-189128.6" - process $proc$libresoc.v:189120$13077 + attribute \src "libresoc.v:190437.3-190445.6" + process $proc$libresoc.v:190437$13063 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$13078 $1\rok_l_r_rdok$next[0:0]$13079 - attribute \src "libresoc.v:189121.5-189121.29" + assign $0\rok_l_r_rdok$next[0:0]$13064 $1\rok_l_r_rdok$next[0:0]$13065 + attribute \src "libresoc.v:190438.5-190438.29" switch \initial - attribute \src "libresoc.v:189121.9-189121.17" + attribute \src "libresoc.v:190438.9-190438.17" case 1'1 case end @@ -391837,21 +363220,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$13079 1'1 + assign $1\rok_l_r_rdok$next[0:0]$13065 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$13079 \$68 + assign $1\rok_l_r_rdok$next[0:0]$13065 \$68 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$13078 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$13064 end - attribute \src "libresoc.v:189129.3-189137.6" - process $proc$libresoc.v:189129$13080 + attribute \src "libresoc.v:190446.3-190454.6" + process $proc$libresoc.v:190446$13066 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$13081 $1\rst_l_s_rst$next[0:0]$13082 - attribute \src "libresoc.v:189130.5-189130.29" + assign $0\rst_l_s_rst$next[0:0]$13067 $1\rst_l_s_rst$next[0:0]$13068 + attribute \src "libresoc.v:190447.5-190447.29" switch \initial - attribute \src "libresoc.v:189130.9-189130.17" + attribute \src "libresoc.v:190447.9-190447.17" case 1'1 case end @@ -391860,21 +363243,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$13082 1'0 + assign $1\rst_l_s_rst$next[0:0]$13068 1'0 case - assign $1\rst_l_s_rst$next[0:0]$13082 \all_rd + assign $1\rst_l_s_rst$next[0:0]$13068 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$13081 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$13067 end - attribute \src "libresoc.v:189138.3-189146.6" - process $proc$libresoc.v:189138$13083 + attribute \src "libresoc.v:190455.3-190463.6" + process $proc$libresoc.v:190455$13069 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$13084 $1\rst_l_r_rst$next[0:0]$13085 - attribute \src "libresoc.v:189139.5-189139.29" + assign $0\rst_l_r_rst$next[0:0]$13070 $1\rst_l_r_rst$next[0:0]$13071 + attribute \src "libresoc.v:190456.5-190456.29" switch \initial - attribute \src "libresoc.v:189139.9-189139.17" + attribute \src "libresoc.v:190456.9-190456.17" case 1'1 case end @@ -391883,21 +363266,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$13085 1'1 + assign $1\rst_l_r_rst$next[0:0]$13071 1'1 case - assign $1\rst_l_r_rst$next[0:0]$13085 \rst_r + assign $1\rst_l_r_rst$next[0:0]$13071 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$13084 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$13070 end - attribute \src "libresoc.v:189147.3-189155.6" - process $proc$libresoc.v:189147$13086 + attribute \src "libresoc.v:190464.3-190472.6" + process $proc$libresoc.v:190464$13072 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$13087 $1\opc_l_s_opc$next[0:0]$13088 - attribute \src "libresoc.v:189148.5-189148.29" + assign $0\opc_l_s_opc$next[0:0]$13073 $1\opc_l_s_opc$next[0:0]$13074 + attribute \src "libresoc.v:190465.5-190465.29" switch \initial - attribute \src "libresoc.v:189148.9-189148.17" + attribute \src "libresoc.v:190465.9-190465.17" case 1'1 case end @@ -391906,21 +363289,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$13088 1'0 + assign $1\opc_l_s_opc$next[0:0]$13074 1'0 case - assign $1\opc_l_s_opc$next[0:0]$13088 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$13074 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$13087 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$13073 end - attribute \src "libresoc.v:189156.3-189164.6" - process $proc$libresoc.v:189156$13089 + attribute \src "libresoc.v:190473.3-190481.6" + process $proc$libresoc.v:190473$13075 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$13090 $1\opc_l_r_opc$next[0:0]$13091 - attribute \src "libresoc.v:189157.5-189157.29" + assign $0\opc_l_r_opc$next[0:0]$13076 $1\opc_l_r_opc$next[0:0]$13077 + attribute \src "libresoc.v:190474.5-190474.29" switch \initial - attribute \src "libresoc.v:189157.9-189157.17" + attribute \src "libresoc.v:190474.9-190474.17" case 1'1 case end @@ -391929,21 +363312,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$13091 1'1 + assign $1\opc_l_r_opc$next[0:0]$13077 1'1 case - assign $1\opc_l_r_opc$next[0:0]$13091 \req_done + assign $1\opc_l_r_opc$next[0:0]$13077 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$13090 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$13076 end - attribute \src "libresoc.v:189165.3-189173.6" - process $proc$libresoc.v:189165$13092 + attribute \src "libresoc.v:190482.3-190490.6" + process $proc$libresoc.v:190482$13078 assign { } { } assign { } { } - assign $0\src_l_s_src$next[5:0]$13093 $1\src_l_s_src$next[5:0]$13094 - attribute \src "libresoc.v:189166.5-189166.29" + assign $0\src_l_s_src$next[5:0]$13079 $1\src_l_s_src$next[5:0]$13080 + attribute \src "libresoc.v:190483.5-190483.29" switch \initial - attribute \src "libresoc.v:189166.9-189166.17" + attribute \src "libresoc.v:190483.9-190483.17" case 1'1 case end @@ -391952,21 +363335,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[5:0]$13094 6'000000 + assign $1\src_l_s_src$next[5:0]$13080 6'000000 case - assign $1\src_l_s_src$next[5:0]$13094 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[5:0]$13080 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[5:0]$13093 + update \src_l_s_src$next $0\src_l_s_src$next[5:0]$13079 end - attribute \src "libresoc.v:189174.3-189182.6" - process $proc$libresoc.v:189174$13095 + attribute \src "libresoc.v:190491.3-190499.6" + process $proc$libresoc.v:190491$13081 assign { } { } assign { } { } - assign $0\src_l_r_src$next[5:0]$13096 $1\src_l_r_src$next[5:0]$13097 - attribute \src "libresoc.v:189175.5-189175.29" + assign $0\src_l_r_src$next[5:0]$13082 $1\src_l_r_src$next[5:0]$13083 + attribute \src "libresoc.v:190492.5-190492.29" switch \initial - attribute \src "libresoc.v:189175.9-189175.17" + attribute \src "libresoc.v:190492.9-190492.17" case 1'1 case end @@ -391975,21 +363358,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[5:0]$13097 6'111111 + assign $1\src_l_r_src$next[5:0]$13083 6'111111 case - assign $1\src_l_r_src$next[5:0]$13097 \reset_r + assign $1\src_l_r_src$next[5:0]$13083 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[5:0]$13096 + update \src_l_r_src$next $0\src_l_r_src$next[5:0]$13082 end - attribute \src "libresoc.v:189183.3-189191.6" - process $proc$libresoc.v:189183$13098 + attribute \src "libresoc.v:190500.3-190508.6" + process $proc$libresoc.v:190500$13084 assign { } { } assign { } { } - assign $0\req_l_s_req$next[5:0]$13099 $1\req_l_s_req$next[5:0]$13100 - attribute \src "libresoc.v:189184.5-189184.29" + assign $0\req_l_s_req$next[5:0]$13085 $1\req_l_s_req$next[5:0]$13086 + attribute \src "libresoc.v:190501.5-190501.29" switch \initial - attribute \src "libresoc.v:189184.9-189184.17" + attribute \src "libresoc.v:190501.9-190501.17" case 1'1 case end @@ -391998,21 +363381,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[5:0]$13100 6'000000 + assign $1\req_l_s_req$next[5:0]$13086 6'000000 case - assign $1\req_l_s_req$next[5:0]$13100 \$70 + assign $1\req_l_s_req$next[5:0]$13086 \$70 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[5:0]$13099 + update \req_l_s_req$next $0\req_l_s_req$next[5:0]$13085 end - attribute \src "libresoc.v:189192.3-189200.6" - process $proc$libresoc.v:189192$13101 + attribute \src "libresoc.v:190509.3-190517.6" + process $proc$libresoc.v:190509$13087 assign { } { } assign { } { } - assign $0\req_l_r_req$next[5:0]$13102 $1\req_l_r_req$next[5:0]$13103 - attribute \src "libresoc.v:189193.5-189193.29" + assign $0\req_l_r_req$next[5:0]$13088 $1\req_l_r_req$next[5:0]$13089 + attribute \src "libresoc.v:190510.5-190510.29" switch \initial - attribute \src "libresoc.v:189193.9-189193.17" + attribute \src "libresoc.v:190510.9-190510.17" case 1'1 case end @@ -392021,15 +363404,15 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[5:0]$13103 6'111111 + assign $1\req_l_r_req$next[5:0]$13089 6'111111 case - assign $1\req_l_r_req$next[5:0]$13103 \$72 + assign $1\req_l_r_req$next[5:0]$13089 \$72 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[5:0]$13102 + update \req_l_r_req$next $0\req_l_r_req$next[5:0]$13088 end - attribute \src "libresoc.v:189201.3-189213.6" - process $proc$libresoc.v:189201$13104 + attribute \src "libresoc.v:190518.3-190530.6" + process $proc$libresoc.v:190518$13090 assign { } { } assign { } { } assign { } { } @@ -392038,13 +363421,13 @@ module \spr0 assign { } { } assign { } { } assign { } { } - assign $0\alu_spr0_spr_op__fn_unit$next[13:0]$13105 $1\alu_spr0_spr_op__fn_unit$next[13:0]$13109 - assign $0\alu_spr0_spr_op__insn$next[31:0]$13106 $1\alu_spr0_spr_op__insn$next[31:0]$13110 - assign $0\alu_spr0_spr_op__insn_type$next[6:0]$13107 $1\alu_spr0_spr_op__insn_type$next[6:0]$13111 - assign $0\alu_spr0_spr_op__is_32bit$next[0:0]$13108 $1\alu_spr0_spr_op__is_32bit$next[0:0]$13112 - attribute \src "libresoc.v:189202.5-189202.29" + assign $0\alu_spr0_spr_op__fn_unit$next[13:0]$13091 $1\alu_spr0_spr_op__fn_unit$next[13:0]$13095 + assign $0\alu_spr0_spr_op__insn$next[31:0]$13092 $1\alu_spr0_spr_op__insn$next[31:0]$13096 + assign $0\alu_spr0_spr_op__insn_type$next[6:0]$13093 $1\alu_spr0_spr_op__insn_type$next[6:0]$13097 + assign $0\alu_spr0_spr_op__is_32bit$next[0:0]$13094 $1\alu_spr0_spr_op__is_32bit$next[0:0]$13098 + attribute \src "libresoc.v:190519.5-190519.29" switch \initial - attribute \src "libresoc.v:189202.9-189202.17" + attribute \src "libresoc.v:190519.9-190519.17" case 1'1 case end @@ -392056,33 +363439,33 @@ module \spr0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_spr0_spr_op__is_32bit$next[0:0]$13112 $1\alu_spr0_spr_op__insn$next[31:0]$13110 $1\alu_spr0_spr_op__fn_unit$next[13:0]$13109 $1\alu_spr0_spr_op__insn_type$next[6:0]$13111 } { \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__insn \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__insn_type } + assign { $1\alu_spr0_spr_op__is_32bit$next[0:0]$13098 $1\alu_spr0_spr_op__insn$next[31:0]$13096 $1\alu_spr0_spr_op__fn_unit$next[13:0]$13095 $1\alu_spr0_spr_op__insn_type$next[6:0]$13097 } { \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__insn \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__insn_type } case - assign $1\alu_spr0_spr_op__fn_unit$next[13:0]$13109 \alu_spr0_spr_op__fn_unit - assign $1\alu_spr0_spr_op__insn$next[31:0]$13110 \alu_spr0_spr_op__insn - assign $1\alu_spr0_spr_op__insn_type$next[6:0]$13111 \alu_spr0_spr_op__insn_type - assign $1\alu_spr0_spr_op__is_32bit$next[0:0]$13112 \alu_spr0_spr_op__is_32bit + assign $1\alu_spr0_spr_op__fn_unit$next[13:0]$13095 \alu_spr0_spr_op__fn_unit + assign $1\alu_spr0_spr_op__insn$next[31:0]$13096 \alu_spr0_spr_op__insn + assign $1\alu_spr0_spr_op__insn_type$next[6:0]$13097 \alu_spr0_spr_op__insn_type + assign $1\alu_spr0_spr_op__is_32bit$next[0:0]$13098 \alu_spr0_spr_op__is_32bit end sync always - update \alu_spr0_spr_op__fn_unit$next $0\alu_spr0_spr_op__fn_unit$next[13:0]$13105 - update \alu_spr0_spr_op__insn$next $0\alu_spr0_spr_op__insn$next[31:0]$13106 - update \alu_spr0_spr_op__insn_type$next $0\alu_spr0_spr_op__insn_type$next[6:0]$13107 - update \alu_spr0_spr_op__is_32bit$next $0\alu_spr0_spr_op__is_32bit$next[0:0]$13108 + update \alu_spr0_spr_op__fn_unit$next $0\alu_spr0_spr_op__fn_unit$next[13:0]$13091 + update \alu_spr0_spr_op__insn$next $0\alu_spr0_spr_op__insn$next[31:0]$13092 + update \alu_spr0_spr_op__insn_type$next $0\alu_spr0_spr_op__insn_type$next[6:0]$13093 + update \alu_spr0_spr_op__is_32bit$next $0\alu_spr0_spr_op__is_32bit$next[0:0]$13094 end - attribute \src "libresoc.v:189214.3-189235.6" - process $proc$libresoc.v:189214$13113 + attribute \src "libresoc.v:190531.3-190552.6" + process $proc$libresoc.v:190531$13099 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$13114 $2\data_r0__o$next[63:0]$13118 + assign $0\data_r0__o$next[63:0]$13100 $2\data_r0__o$next[63:0]$13104 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$13115 $3\data_r0__o_ok$next[0:0]$13120 - attribute \src "libresoc.v:189215.5-189215.29" + assign $0\data_r0__o_ok$next[0:0]$13101 $3\data_r0__o_ok$next[0:0]$13106 + attribute \src "libresoc.v:190532.5-190532.29" switch \initial - attribute \src "libresoc.v:189215.9-189215.17" + attribute \src "libresoc.v:190532.9-190532.17" case 1'1 case end @@ -392092,10 +363475,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$13117 $1\data_r0__o$next[63:0]$13116 } { \o_ok \alu_spr0_o } + assign { $1\data_r0__o_ok$next[0:0]$13103 $1\data_r0__o$next[63:0]$13102 } { \o_ok \alu_spr0_o } case - assign $1\data_r0__o$next[63:0]$13116 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$13117 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$13102 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$13103 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -392103,38 +363486,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$13119 $2\data_r0__o$next[63:0]$13118 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$13105 $2\data_r0__o$next[63:0]$13104 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$13118 $1\data_r0__o$next[63:0]$13116 - assign $2\data_r0__o_ok$next[0:0]$13119 $1\data_r0__o_ok$next[0:0]$13117 + assign $2\data_r0__o$next[63:0]$13104 $1\data_r0__o$next[63:0]$13102 + assign $2\data_r0__o_ok$next[0:0]$13105 $1\data_r0__o_ok$next[0:0]$13103 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$13120 1'0 + assign $3\data_r0__o_ok$next[0:0]$13106 1'0 case - assign $3\data_r0__o_ok$next[0:0]$13120 $2\data_r0__o_ok$next[0:0]$13119 + assign $3\data_r0__o_ok$next[0:0]$13106 $2\data_r0__o_ok$next[0:0]$13105 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$13114 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$13115 + update \data_r0__o$next $0\data_r0__o$next[63:0]$13100 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$13101 end - attribute \src "libresoc.v:189236.3-189257.6" - process $proc$libresoc.v:189236$13121 + attribute \src "libresoc.v:190553.3-190574.6" + process $proc$libresoc.v:190553$13107 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__spr1$next[63:0]$13122 $2\data_r1__spr1$next[63:0]$13126 + assign $0\data_r1__spr1$next[63:0]$13108 $2\data_r1__spr1$next[63:0]$13112 assign { } { } - assign $0\data_r1__spr1_ok$next[0:0]$13123 $3\data_r1__spr1_ok$next[0:0]$13128 - attribute \src "libresoc.v:189237.5-189237.29" + assign $0\data_r1__spr1_ok$next[0:0]$13109 $3\data_r1__spr1_ok$next[0:0]$13114 + attribute \src "libresoc.v:190554.5-190554.29" switch \initial - attribute \src "libresoc.v:189237.9-189237.17" + attribute \src "libresoc.v:190554.9-190554.17" case 1'1 case end @@ -392144,10 +363527,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__spr1_ok$next[0:0]$13125 $1\data_r1__spr1$next[63:0]$13124 } { \spr1_ok \alu_spr0_spr1 } + assign { $1\data_r1__spr1_ok$next[0:0]$13111 $1\data_r1__spr1$next[63:0]$13110 } { \spr1_ok \alu_spr0_spr1 } case - assign $1\data_r1__spr1$next[63:0]$13124 \data_r1__spr1 - assign $1\data_r1__spr1_ok$next[0:0]$13125 \data_r1__spr1_ok + assign $1\data_r1__spr1$next[63:0]$13110 \data_r1__spr1 + assign $1\data_r1__spr1_ok$next[0:0]$13111 \data_r1__spr1_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -392155,38 +363538,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__spr1_ok$next[0:0]$13127 $2\data_r1__spr1$next[63:0]$13126 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r1__spr1_ok$next[0:0]$13113 $2\data_r1__spr1$next[63:0]$13112 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r1__spr1$next[63:0]$13126 $1\data_r1__spr1$next[63:0]$13124 - assign $2\data_r1__spr1_ok$next[0:0]$13127 $1\data_r1__spr1_ok$next[0:0]$13125 + assign $2\data_r1__spr1$next[63:0]$13112 $1\data_r1__spr1$next[63:0]$13110 + assign $2\data_r1__spr1_ok$next[0:0]$13113 $1\data_r1__spr1_ok$next[0:0]$13111 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__spr1_ok$next[0:0]$13128 1'0 + assign $3\data_r1__spr1_ok$next[0:0]$13114 1'0 case - assign $3\data_r1__spr1_ok$next[0:0]$13128 $2\data_r1__spr1_ok$next[0:0]$13127 + assign $3\data_r1__spr1_ok$next[0:0]$13114 $2\data_r1__spr1_ok$next[0:0]$13113 end sync always - update \data_r1__spr1$next $0\data_r1__spr1$next[63:0]$13122 - update \data_r1__spr1_ok$next $0\data_r1__spr1_ok$next[0:0]$13123 + update \data_r1__spr1$next $0\data_r1__spr1$next[63:0]$13108 + update \data_r1__spr1_ok$next $0\data_r1__spr1_ok$next[0:0]$13109 end - attribute \src "libresoc.v:189258.3-189279.6" - process $proc$libresoc.v:189258$13129 + attribute \src "libresoc.v:190575.3-190596.6" + process $proc$libresoc.v:190575$13115 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__fast1$next[63:0]$13130 $2\data_r2__fast1$next[63:0]$13134 + assign $0\data_r2__fast1$next[63:0]$13116 $2\data_r2__fast1$next[63:0]$13120 assign { } { } - assign $0\data_r2__fast1_ok$next[0:0]$13131 $3\data_r2__fast1_ok$next[0:0]$13136 - attribute \src "libresoc.v:189259.5-189259.29" + assign $0\data_r2__fast1_ok$next[0:0]$13117 $3\data_r2__fast1_ok$next[0:0]$13122 + attribute \src "libresoc.v:190576.5-190576.29" switch \initial - attribute \src "libresoc.v:189259.9-189259.17" + attribute \src "libresoc.v:190576.9-190576.17" case 1'1 case end @@ -392196,10 +363579,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__fast1_ok$next[0:0]$13133 $1\data_r2__fast1$next[63:0]$13132 } { \fast1_ok \alu_spr0_fast1 } + assign { $1\data_r2__fast1_ok$next[0:0]$13119 $1\data_r2__fast1$next[63:0]$13118 } { \fast1_ok \alu_spr0_fast1 } case - assign $1\data_r2__fast1$next[63:0]$13132 \data_r2__fast1 - assign $1\data_r2__fast1_ok$next[0:0]$13133 \data_r2__fast1_ok + assign $1\data_r2__fast1$next[63:0]$13118 \data_r2__fast1 + assign $1\data_r2__fast1_ok$next[0:0]$13119 \data_r2__fast1_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -392207,38 +363590,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__fast1_ok$next[0:0]$13135 $2\data_r2__fast1$next[63:0]$13134 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r2__fast1_ok$next[0:0]$13121 $2\data_r2__fast1$next[63:0]$13120 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r2__fast1$next[63:0]$13134 $1\data_r2__fast1$next[63:0]$13132 - assign $2\data_r2__fast1_ok$next[0:0]$13135 $1\data_r2__fast1_ok$next[0:0]$13133 + assign $2\data_r2__fast1$next[63:0]$13120 $1\data_r2__fast1$next[63:0]$13118 + assign $2\data_r2__fast1_ok$next[0:0]$13121 $1\data_r2__fast1_ok$next[0:0]$13119 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__fast1_ok$next[0:0]$13136 1'0 + assign $3\data_r2__fast1_ok$next[0:0]$13122 1'0 case - assign $3\data_r2__fast1_ok$next[0:0]$13136 $2\data_r2__fast1_ok$next[0:0]$13135 + assign $3\data_r2__fast1_ok$next[0:0]$13122 $2\data_r2__fast1_ok$next[0:0]$13121 end sync always - update \data_r2__fast1$next $0\data_r2__fast1$next[63:0]$13130 - update \data_r2__fast1_ok$next $0\data_r2__fast1_ok$next[0:0]$13131 + update \data_r2__fast1$next $0\data_r2__fast1$next[63:0]$13116 + update \data_r2__fast1_ok$next $0\data_r2__fast1_ok$next[0:0]$13117 end - attribute \src "libresoc.v:189280.3-189301.6" - process $proc$libresoc.v:189280$13137 + attribute \src "libresoc.v:190597.3-190618.6" + process $proc$libresoc.v:190597$13123 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r3__xer_so$next[0:0]$13138 $2\data_r3__xer_so$next[0:0]$13142 + assign $0\data_r3__xer_so$next[0:0]$13124 $2\data_r3__xer_so$next[0:0]$13128 assign { } { } - assign $0\data_r3__xer_so_ok$next[0:0]$13139 $3\data_r3__xer_so_ok$next[0:0]$13144 - attribute \src "libresoc.v:189281.5-189281.29" + assign $0\data_r3__xer_so_ok$next[0:0]$13125 $3\data_r3__xer_so_ok$next[0:0]$13130 + attribute \src "libresoc.v:190598.5-190598.29" switch \initial - attribute \src "libresoc.v:189281.9-189281.17" + attribute \src "libresoc.v:190598.9-190598.17" case 1'1 case end @@ -392248,10 +363631,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r3__xer_so_ok$next[0:0]$13141 $1\data_r3__xer_so$next[0:0]$13140 } { \xer_so_ok \alu_spr0_xer_so } + assign { $1\data_r3__xer_so_ok$next[0:0]$13127 $1\data_r3__xer_so$next[0:0]$13126 } { \xer_so_ok \alu_spr0_xer_so } case - assign $1\data_r3__xer_so$next[0:0]$13140 \data_r3__xer_so - assign $1\data_r3__xer_so_ok$next[0:0]$13141 \data_r3__xer_so_ok + assign $1\data_r3__xer_so$next[0:0]$13126 \data_r3__xer_so + assign $1\data_r3__xer_so_ok$next[0:0]$13127 \data_r3__xer_so_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -392259,38 +363642,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r3__xer_so_ok$next[0:0]$13143 $2\data_r3__xer_so$next[0:0]$13142 } 2'00 + assign { $2\data_r3__xer_so_ok$next[0:0]$13129 $2\data_r3__xer_so$next[0:0]$13128 } 2'00 case - assign $2\data_r3__xer_so$next[0:0]$13142 $1\data_r3__xer_so$next[0:0]$13140 - assign $2\data_r3__xer_so_ok$next[0:0]$13143 $1\data_r3__xer_so_ok$next[0:0]$13141 + assign $2\data_r3__xer_so$next[0:0]$13128 $1\data_r3__xer_so$next[0:0]$13126 + assign $2\data_r3__xer_so_ok$next[0:0]$13129 $1\data_r3__xer_so_ok$next[0:0]$13127 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r3__xer_so_ok$next[0:0]$13144 1'0 + assign $3\data_r3__xer_so_ok$next[0:0]$13130 1'0 case - assign $3\data_r3__xer_so_ok$next[0:0]$13144 $2\data_r3__xer_so_ok$next[0:0]$13143 + assign $3\data_r3__xer_so_ok$next[0:0]$13130 $2\data_r3__xer_so_ok$next[0:0]$13129 end sync always - update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$13138 - update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$13139 + update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$13124 + update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$13125 end - attribute \src "libresoc.v:189302.3-189323.6" - process $proc$libresoc.v:189302$13145 + attribute \src "libresoc.v:190619.3-190640.6" + process $proc$libresoc.v:190619$13131 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r4__xer_ov$next[1:0]$13146 $2\data_r4__xer_ov$next[1:0]$13150 + assign $0\data_r4__xer_ov$next[1:0]$13132 $2\data_r4__xer_ov$next[1:0]$13136 assign { } { } - assign $0\data_r4__xer_ov_ok$next[0:0]$13147 $3\data_r4__xer_ov_ok$next[0:0]$13152 - attribute \src "libresoc.v:189303.5-189303.29" + assign $0\data_r4__xer_ov_ok$next[0:0]$13133 $3\data_r4__xer_ov_ok$next[0:0]$13138 + attribute \src "libresoc.v:190620.5-190620.29" switch \initial - attribute \src "libresoc.v:189303.9-189303.17" + attribute \src "libresoc.v:190620.9-190620.17" case 1'1 case end @@ -392300,10 +363683,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r4__xer_ov_ok$next[0:0]$13149 $1\data_r4__xer_ov$next[1:0]$13148 } { \xer_ov_ok \alu_spr0_xer_ov } + assign { $1\data_r4__xer_ov_ok$next[0:0]$13135 $1\data_r4__xer_ov$next[1:0]$13134 } { \xer_ov_ok \alu_spr0_xer_ov } case - assign $1\data_r4__xer_ov$next[1:0]$13148 \data_r4__xer_ov - assign $1\data_r4__xer_ov_ok$next[0:0]$13149 \data_r4__xer_ov_ok + assign $1\data_r4__xer_ov$next[1:0]$13134 \data_r4__xer_ov + assign $1\data_r4__xer_ov_ok$next[0:0]$13135 \data_r4__xer_ov_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -392311,38 +363694,38 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r4__xer_ov_ok$next[0:0]$13151 $2\data_r4__xer_ov$next[1:0]$13150 } 3'000 + assign { $2\data_r4__xer_ov_ok$next[0:0]$13137 $2\data_r4__xer_ov$next[1:0]$13136 } 3'000 case - assign $2\data_r4__xer_ov$next[1:0]$13150 $1\data_r4__xer_ov$next[1:0]$13148 - assign $2\data_r4__xer_ov_ok$next[0:0]$13151 $1\data_r4__xer_ov_ok$next[0:0]$13149 + assign $2\data_r4__xer_ov$next[1:0]$13136 $1\data_r4__xer_ov$next[1:0]$13134 + assign $2\data_r4__xer_ov_ok$next[0:0]$13137 $1\data_r4__xer_ov_ok$next[0:0]$13135 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r4__xer_ov_ok$next[0:0]$13152 1'0 + assign $3\data_r4__xer_ov_ok$next[0:0]$13138 1'0 case - assign $3\data_r4__xer_ov_ok$next[0:0]$13152 $2\data_r4__xer_ov_ok$next[0:0]$13151 + assign $3\data_r4__xer_ov_ok$next[0:0]$13138 $2\data_r4__xer_ov_ok$next[0:0]$13137 end sync always - update \data_r4__xer_ov$next $0\data_r4__xer_ov$next[1:0]$13146 - update \data_r4__xer_ov_ok$next $0\data_r4__xer_ov_ok$next[0:0]$13147 + update \data_r4__xer_ov$next $0\data_r4__xer_ov$next[1:0]$13132 + update \data_r4__xer_ov_ok$next $0\data_r4__xer_ov_ok$next[0:0]$13133 end - attribute \src "libresoc.v:189324.3-189345.6" - process $proc$libresoc.v:189324$13153 + attribute \src "libresoc.v:190641.3-190662.6" + process $proc$libresoc.v:190641$13139 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r5__xer_ca$next[1:0]$13154 $2\data_r5__xer_ca$next[1:0]$13158 + assign $0\data_r5__xer_ca$next[1:0]$13140 $2\data_r5__xer_ca$next[1:0]$13144 assign { } { } - assign $0\data_r5__xer_ca_ok$next[0:0]$13155 $3\data_r5__xer_ca_ok$next[0:0]$13160 - attribute \src "libresoc.v:189325.5-189325.29" + assign $0\data_r5__xer_ca_ok$next[0:0]$13141 $3\data_r5__xer_ca_ok$next[0:0]$13146 + attribute \src "libresoc.v:190642.5-190642.29" switch \initial - attribute \src "libresoc.v:189325.9-189325.17" + attribute \src "libresoc.v:190642.9-190642.17" case 1'1 case end @@ -392352,10 +363735,10 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r5__xer_ca_ok$next[0:0]$13157 $1\data_r5__xer_ca$next[1:0]$13156 } { \xer_ca_ok \alu_spr0_xer_ca } + assign { $1\data_r5__xer_ca_ok$next[0:0]$13143 $1\data_r5__xer_ca$next[1:0]$13142 } { \xer_ca_ok \alu_spr0_xer_ca } case - assign $1\data_r5__xer_ca$next[1:0]$13156 \data_r5__xer_ca - assign $1\data_r5__xer_ca_ok$next[0:0]$13157 \data_r5__xer_ca_ok + assign $1\data_r5__xer_ca$next[1:0]$13142 \data_r5__xer_ca + assign $1\data_r5__xer_ca_ok$next[0:0]$13143 \data_r5__xer_ca_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -392363,32 +363746,32 @@ module \spr0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r5__xer_ca_ok$next[0:0]$13159 $2\data_r5__xer_ca$next[1:0]$13158 } 3'000 + assign { $2\data_r5__xer_ca_ok$next[0:0]$13145 $2\data_r5__xer_ca$next[1:0]$13144 } 3'000 case - assign $2\data_r5__xer_ca$next[1:0]$13158 $1\data_r5__xer_ca$next[1:0]$13156 - assign $2\data_r5__xer_ca_ok$next[0:0]$13159 $1\data_r5__xer_ca_ok$next[0:0]$13157 + assign $2\data_r5__xer_ca$next[1:0]$13144 $1\data_r5__xer_ca$next[1:0]$13142 + assign $2\data_r5__xer_ca_ok$next[0:0]$13145 $1\data_r5__xer_ca_ok$next[0:0]$13143 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r5__xer_ca_ok$next[0:0]$13160 1'0 + assign $3\data_r5__xer_ca_ok$next[0:0]$13146 1'0 case - assign $3\data_r5__xer_ca_ok$next[0:0]$13160 $2\data_r5__xer_ca_ok$next[0:0]$13159 + assign $3\data_r5__xer_ca_ok$next[0:0]$13146 $2\data_r5__xer_ca_ok$next[0:0]$13145 end sync always - update \data_r5__xer_ca$next $0\data_r5__xer_ca$next[1:0]$13154 - update \data_r5__xer_ca_ok$next $0\data_r5__xer_ca_ok$next[0:0]$13155 + update \data_r5__xer_ca$next $0\data_r5__xer_ca$next[1:0]$13140 + update \data_r5__xer_ca_ok$next $0\data_r5__xer_ca_ok$next[0:0]$13141 end - attribute \src "libresoc.v:189346.3-189355.6" - process $proc$libresoc.v:189346$13161 + attribute \src "libresoc.v:190663.3-190672.6" + process $proc$libresoc.v:190663$13147 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$13162 $1\src_r0$next[63:0]$13163 - attribute \src "libresoc.v:189347.5-189347.29" + assign $0\src_r0$next[63:0]$13148 $1\src_r0$next[63:0]$13149 + attribute \src "libresoc.v:190664.5-190664.29" switch \initial - attribute \src "libresoc.v:189347.9-189347.17" + attribute \src "libresoc.v:190664.9-190664.17" case 1'1 case end @@ -392397,21 +363780,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$13163 \src1_i + assign $1\src_r0$next[63:0]$13149 \src1_i case - assign $1\src_r0$next[63:0]$13163 \src_r0 + assign $1\src_r0$next[63:0]$13149 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$13162 + update \src_r0$next $0\src_r0$next[63:0]$13148 end - attribute \src "libresoc.v:189356.3-189365.6" - process $proc$libresoc.v:189356$13164 + attribute \src "libresoc.v:190673.3-190682.6" + process $proc$libresoc.v:190673$13150 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$13165 $1\src_r1$next[63:0]$13166 - attribute \src "libresoc.v:189357.5-189357.29" + assign $0\src_r1$next[63:0]$13151 $1\src_r1$next[63:0]$13152 + attribute \src "libresoc.v:190674.5-190674.29" switch \initial - attribute \src "libresoc.v:189357.9-189357.17" + attribute \src "libresoc.v:190674.9-190674.17" case 1'1 case end @@ -392420,21 +363803,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$13166 \src2_i + assign $1\src_r1$next[63:0]$13152 \src2_i case - assign $1\src_r1$next[63:0]$13166 \src_r1 + assign $1\src_r1$next[63:0]$13152 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$13165 + update \src_r1$next $0\src_r1$next[63:0]$13151 end - attribute \src "libresoc.v:189366.3-189375.6" - process $proc$libresoc.v:189366$13167 + attribute \src "libresoc.v:190683.3-190692.6" + process $proc$libresoc.v:190683$13153 assign { } { } assign { } { } - assign $0\src_r2$next[63:0]$13168 $1\src_r2$next[63:0]$13169 - attribute \src "libresoc.v:189367.5-189367.29" + assign $0\src_r2$next[63:0]$13154 $1\src_r2$next[63:0]$13155 + attribute \src "libresoc.v:190684.5-190684.29" switch \initial - attribute \src "libresoc.v:189367.9-189367.17" + attribute \src "libresoc.v:190684.9-190684.17" case 1'1 case end @@ -392443,21 +363826,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[63:0]$13169 \src3_i + assign $1\src_r2$next[63:0]$13155 \src3_i case - assign $1\src_r2$next[63:0]$13169 \src_r2 + assign $1\src_r2$next[63:0]$13155 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[63:0]$13168 + update \src_r2$next $0\src_r2$next[63:0]$13154 end - attribute \src "libresoc.v:189376.3-189385.6" - process $proc$libresoc.v:189376$13170 + attribute \src "libresoc.v:190693.3-190702.6" + process $proc$libresoc.v:190693$13156 assign { } { } assign { } { } - assign $0\src_r3$next[0:0]$13171 $1\src_r3$next[0:0]$13172 - attribute \src "libresoc.v:189377.5-189377.29" + assign $0\src_r3$next[0:0]$13157 $1\src_r3$next[0:0]$13158 + attribute \src "libresoc.v:190694.5-190694.29" switch \initial - attribute \src "libresoc.v:189377.9-189377.17" + attribute \src "libresoc.v:190694.9-190694.17" case 1'1 case end @@ -392466,21 +363849,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r3$next[0:0]$13172 \src4_i + assign $1\src_r3$next[0:0]$13158 \src4_i case - assign $1\src_r3$next[0:0]$13172 \src_r3 + assign $1\src_r3$next[0:0]$13158 \src_r3 end sync always - update \src_r3$next $0\src_r3$next[0:0]$13171 + update \src_r3$next $0\src_r3$next[0:0]$13157 end - attribute \src "libresoc.v:189386.3-189395.6" - process $proc$libresoc.v:189386$13173 + attribute \src "libresoc.v:190703.3-190712.6" + process $proc$libresoc.v:190703$13159 assign { } { } assign { } { } - assign $0\src_r4$next[1:0]$13174 $1\src_r4$next[1:0]$13175 - attribute \src "libresoc.v:189387.5-189387.29" + assign $0\src_r4$next[1:0]$13160 $1\src_r4$next[1:0]$13161 + attribute \src "libresoc.v:190704.5-190704.29" switch \initial - attribute \src "libresoc.v:189387.9-189387.17" + attribute \src "libresoc.v:190704.9-190704.17" case 1'1 case end @@ -392489,21 +363872,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r4$next[1:0]$13175 \src5_i + assign $1\src_r4$next[1:0]$13161 \src5_i case - assign $1\src_r4$next[1:0]$13175 \src_r4 + assign $1\src_r4$next[1:0]$13161 \src_r4 end sync always - update \src_r4$next $0\src_r4$next[1:0]$13174 + update \src_r4$next $0\src_r4$next[1:0]$13160 end - attribute \src "libresoc.v:189396.3-189405.6" - process $proc$libresoc.v:189396$13176 + attribute \src "libresoc.v:190713.3-190722.6" + process $proc$libresoc.v:190713$13162 assign { } { } assign { } { } - assign $0\src_r5$next[1:0]$13177 $1\src_r5$next[1:0]$13178 - attribute \src "libresoc.v:189397.5-189397.29" + assign $0\src_r5$next[1:0]$13163 $1\src_r5$next[1:0]$13164 + attribute \src "libresoc.v:190714.5-190714.29" switch \initial - attribute \src "libresoc.v:189397.9-189397.17" + attribute \src "libresoc.v:190714.9-190714.17" case 1'1 case end @@ -392512,21 +363895,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r5$next[1:0]$13178 \src6_i + assign $1\src_r5$next[1:0]$13164 \src6_i case - assign $1\src_r5$next[1:0]$13178 \src_r5 + assign $1\src_r5$next[1:0]$13164 \src_r5 end sync always - update \src_r5$next $0\src_r5$next[1:0]$13177 + update \src_r5$next $0\src_r5$next[1:0]$13163 end - attribute \src "libresoc.v:189406.3-189414.6" - process $proc$libresoc.v:189406$13179 + attribute \src "libresoc.v:190723.3-190731.6" + process $proc$libresoc.v:190723$13165 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$13180 $1\alui_l_r_alui$next[0:0]$13181 - attribute \src "libresoc.v:189407.5-189407.29" + assign $0\alui_l_r_alui$next[0:0]$13166 $1\alui_l_r_alui$next[0:0]$13167 + attribute \src "libresoc.v:190724.5-190724.29" switch \initial - attribute \src "libresoc.v:189407.9-189407.17" + attribute \src "libresoc.v:190724.9-190724.17" case 1'1 case end @@ -392535,21 +363918,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$13181 1'1 + assign $1\alui_l_r_alui$next[0:0]$13167 1'1 case - assign $1\alui_l_r_alui$next[0:0]$13181 \$98 + assign $1\alui_l_r_alui$next[0:0]$13167 \$98 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$13180 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$13166 end - attribute \src "libresoc.v:189415.3-189423.6" - process $proc$libresoc.v:189415$13182 + attribute \src "libresoc.v:190732.3-190740.6" + process $proc$libresoc.v:190732$13168 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$13183 $1\alu_l_r_alu$next[0:0]$13184 - attribute \src "libresoc.v:189416.5-189416.29" + assign $0\alu_l_r_alu$next[0:0]$13169 $1\alu_l_r_alu$next[0:0]$13170 + attribute \src "libresoc.v:190733.5-190733.29" switch \initial - attribute \src "libresoc.v:189416.9-189416.17" + attribute \src "libresoc.v:190733.9-190733.17" case 1'1 case end @@ -392558,21 +363941,21 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$13184 1'1 + assign $1\alu_l_r_alu$next[0:0]$13170 1'1 case - assign $1\alu_l_r_alu$next[0:0]$13184 \$100 + assign $1\alu_l_r_alu$next[0:0]$13170 \$100 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$13183 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$13169 end - attribute \src "libresoc.v:189424.3-189433.6" - process $proc$libresoc.v:189424$13185 + attribute \src "libresoc.v:190741.3-190750.6" + process $proc$libresoc.v:190741$13171 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:189425.5-189425.29" + attribute \src "libresoc.v:190742.5-190742.29" switch \initial - attribute \src "libresoc.v:189425.9-189425.17" + attribute \src "libresoc.v:190742.9-190742.17" case 1'1 case end @@ -392588,14 +363971,14 @@ module \spr0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:189434.3-189443.6" - process $proc$libresoc.v:189434$13186 + attribute \src "libresoc.v:190751.3-190760.6" + process $proc$libresoc.v:190751$13172 assign { } { } assign { } { } assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "libresoc.v:189435.5-189435.29" + attribute \src "libresoc.v:190752.5-190752.29" switch \initial - attribute \src "libresoc.v:189435.9-189435.17" + attribute \src "libresoc.v:190752.9-190752.17" case 1'1 case end @@ -392611,14 +363994,14 @@ module \spr0 sync always update \dest2_o $0\dest2_o[63:0] end - attribute \src "libresoc.v:189444.3-189453.6" - process $proc$libresoc.v:189444$13187 + attribute \src "libresoc.v:190761.3-190770.6" + process $proc$libresoc.v:190761$13173 assign { } { } assign { } { } assign $0\dest3_o[63:0] $1\dest3_o[63:0] - attribute \src "libresoc.v:189445.5-189445.29" + attribute \src "libresoc.v:190762.5-190762.29" switch \initial - attribute \src "libresoc.v:189445.9-189445.17" + attribute \src "libresoc.v:190762.9-190762.17" case 1'1 case end @@ -392634,14 +364017,14 @@ module \spr0 sync always update \dest3_o $0\dest3_o[63:0] end - attribute \src "libresoc.v:189454.3-189463.6" - process $proc$libresoc.v:189454$13188 + attribute \src "libresoc.v:190771.3-190780.6" + process $proc$libresoc.v:190771$13174 assign { } { } assign { } { } assign $0\dest4_o[0:0] $1\dest4_o[0:0] - attribute \src "libresoc.v:189455.5-189455.29" + attribute \src "libresoc.v:190772.5-190772.29" switch \initial - attribute \src "libresoc.v:189455.9-189455.17" + attribute \src "libresoc.v:190772.9-190772.17" case 1'1 case end @@ -392657,14 +364040,14 @@ module \spr0 sync always update \dest4_o $0\dest4_o[0:0] end - attribute \src "libresoc.v:189464.3-189473.6" - process $proc$libresoc.v:189464$13189 + attribute \src "libresoc.v:190781.3-190790.6" + process $proc$libresoc.v:190781$13175 assign { } { } assign { } { } assign $0\dest5_o[1:0] $1\dest5_o[1:0] - attribute \src "libresoc.v:189465.5-189465.29" + attribute \src "libresoc.v:190782.5-190782.29" switch \initial - attribute \src "libresoc.v:189465.9-189465.17" + attribute \src "libresoc.v:190782.9-190782.17" case 1'1 case end @@ -392680,14 +364063,14 @@ module \spr0 sync always update \dest5_o $0\dest5_o[1:0] end - attribute \src "libresoc.v:189474.3-189483.6" - process $proc$libresoc.v:189474$13190 + attribute \src "libresoc.v:190791.3-190800.6" + process $proc$libresoc.v:190791$13176 assign { } { } assign { } { } assign $0\dest6_o[1:0] $1\dest6_o[1:0] - attribute \src "libresoc.v:189475.5-189475.29" + attribute \src "libresoc.v:190792.5-190792.29" switch \initial - attribute \src "libresoc.v:189475.9-189475.17" + attribute \src "libresoc.v:190792.9-190792.17" case 1'1 case end @@ -392703,14 +364086,14 @@ module \spr0 sync always update \dest6_o $0\dest6_o[1:0] end - attribute \src "libresoc.v:189484.3-189492.6" - process $proc$libresoc.v:189484$13191 + attribute \src "libresoc.v:190801.3-190809.6" + process $proc$libresoc.v:190801$13177 assign { } { } assign { } { } - assign $0\prev_wr_go$next[5:0]$13192 $1\prev_wr_go$next[5:0]$13193 - attribute \src "libresoc.v:189485.5-189485.29" + assign $0\prev_wr_go$next[5:0]$13178 $1\prev_wr_go$next[5:0]$13179 + attribute \src "libresoc.v:190802.5-190802.29" switch \initial - attribute \src "libresoc.v:189485.9-189485.17" + attribute \src "libresoc.v:190802.9-190802.17" case 1'1 case end @@ -392719,79 +364102,79 @@ module \spr0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[5:0]$13193 6'000000 - case - assign $1\prev_wr_go$next[5:0]$13193 \$24 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[5:0]$13192 - end - connect \$9 $not$libresoc.v:188883$12970_Y - connect \$100 $and$libresoc.v:188884$12971_Y - connect \$102 $and$libresoc.v:188885$12972_Y - connect \$104 $and$libresoc.v:188886$12973_Y - connect \$106 $not$libresoc.v:188887$12974_Y - connect \$108 $and$libresoc.v:188888$12975_Y - connect \$110 $and$libresoc.v:188889$12976_Y - connect \$112 $and$libresoc.v:188890$12977_Y - connect \$114 $and$libresoc.v:188891$12978_Y - connect \$116 $and$libresoc.v:188892$12979_Y - connect \$118 $and$libresoc.v:188893$12980_Y - connect \$11 $or$libresoc.v:188894$12981_Y - connect \$120 $and$libresoc.v:188895$12982_Y - connect \$122 $and$libresoc.v:188896$12983_Y - connect \$124 $and$libresoc.v:188897$12984_Y - connect \$126 $and$libresoc.v:188898$12985_Y - connect \$128 $and$libresoc.v:188899$12986_Y - connect \$8 $reduce_and$libresoc.v:188900$12987_Y - connect \$130 $and$libresoc.v:188901$12988_Y - connect \$132 $and$libresoc.v:188902$12989_Y - connect \$134 $and$libresoc.v:188903$12990_Y - connect \$136 $and$libresoc.v:188904$12991_Y - connect \$14 $and$libresoc.v:188905$12992_Y - connect \$16 $not$libresoc.v:188906$12993_Y - connect \$18 $and$libresoc.v:188907$12994_Y - connect \$20 $not$libresoc.v:188908$12995_Y - connect \$22 $and$libresoc.v:188909$12996_Y - connect \$24 $and$libresoc.v:188910$12997_Y - connect \$28 $not$libresoc.v:188911$12998_Y - connect \$30 $and$libresoc.v:188912$12999_Y - connect \$27 $reduce_or$libresoc.v:188913$13000_Y - connect \$26 $not$libresoc.v:188914$13001_Y - connect \$34 $and$libresoc.v:188915$13002_Y - connect \$36 $reduce_or$libresoc.v:188916$13003_Y - connect \$38 $reduce_or$libresoc.v:188917$13004_Y - connect \$40 $or$libresoc.v:188918$13005_Y - connect \$42 $not$libresoc.v:188919$13006_Y - connect \$44 $and$libresoc.v:188920$13007_Y - connect \$46 $and$libresoc.v:188921$13008_Y - connect \$48 $eq$libresoc.v:188922$13009_Y - connect \$50 $and$libresoc.v:188923$13010_Y - connect \$52 $eq$libresoc.v:188924$13011_Y - connect \$54 $and$libresoc.v:188925$13012_Y - connect \$56 $and$libresoc.v:188926$13013_Y - connect \$58 $and$libresoc.v:188927$13014_Y - connect \$60 $or$libresoc.v:188928$13015_Y - connect \$62 $or$libresoc.v:188929$13016_Y - connect \$64 $or$libresoc.v:188930$13017_Y - connect \$66 $or$libresoc.v:188931$13018_Y - connect \$68 $and$libresoc.v:188932$13019_Y - connect \$6 $and$libresoc.v:188933$13020_Y - connect \$70 $and$libresoc.v:188934$13021_Y - connect \$72 $or$libresoc.v:188935$13022_Y - connect \$74 $and$libresoc.v:188936$13023_Y - connect \$76 $and$libresoc.v:188937$13024_Y - connect \$78 $and$libresoc.v:188938$13025_Y - connect \$80 $and$libresoc.v:188939$13026_Y - connect \$82 $and$libresoc.v:188940$13027_Y - connect \$84 $and$libresoc.v:188941$13028_Y - connect \$86 $ternary$libresoc.v:188942$13029_Y - connect \$88 $ternary$libresoc.v:188943$13030_Y - connect \$90 $ternary$libresoc.v:188944$13031_Y - connect \$92 $ternary$libresoc.v:188945$13032_Y - connect \$94 $ternary$libresoc.v:188946$13033_Y - connect \$96 $ternary$libresoc.v:188947$13034_Y - connect \$98 $and$libresoc.v:188948$13035_Y + assign $1\prev_wr_go$next[5:0]$13179 6'000000 + case + assign $1\prev_wr_go$next[5:0]$13179 \$24 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[5:0]$13178 + end + connect \$9 $not$libresoc.v:190200$12956_Y + connect \$100 $and$libresoc.v:190201$12957_Y + connect \$102 $and$libresoc.v:190202$12958_Y + connect \$104 $and$libresoc.v:190203$12959_Y + connect \$106 $not$libresoc.v:190204$12960_Y + connect \$108 $and$libresoc.v:190205$12961_Y + connect \$110 $and$libresoc.v:190206$12962_Y + connect \$112 $and$libresoc.v:190207$12963_Y + connect \$114 $and$libresoc.v:190208$12964_Y + connect \$116 $and$libresoc.v:190209$12965_Y + connect \$118 $and$libresoc.v:190210$12966_Y + connect \$11 $or$libresoc.v:190211$12967_Y + connect \$120 $and$libresoc.v:190212$12968_Y + connect \$122 $and$libresoc.v:190213$12969_Y + connect \$124 $and$libresoc.v:190214$12970_Y + connect \$126 $and$libresoc.v:190215$12971_Y + connect \$128 $and$libresoc.v:190216$12972_Y + connect \$8 $reduce_and$libresoc.v:190217$12973_Y + connect \$130 $and$libresoc.v:190218$12974_Y + connect \$132 $and$libresoc.v:190219$12975_Y + connect \$134 $and$libresoc.v:190220$12976_Y + connect \$136 $and$libresoc.v:190221$12977_Y + connect \$14 $and$libresoc.v:190222$12978_Y + connect \$16 $not$libresoc.v:190223$12979_Y + connect \$18 $and$libresoc.v:190224$12980_Y + connect \$20 $not$libresoc.v:190225$12981_Y + connect \$22 $and$libresoc.v:190226$12982_Y + connect \$24 $and$libresoc.v:190227$12983_Y + connect \$28 $not$libresoc.v:190228$12984_Y + connect \$30 $and$libresoc.v:190229$12985_Y + connect \$27 $reduce_or$libresoc.v:190230$12986_Y + connect \$26 $not$libresoc.v:190231$12987_Y + connect \$34 $and$libresoc.v:190232$12988_Y + connect \$36 $reduce_or$libresoc.v:190233$12989_Y + connect \$38 $reduce_or$libresoc.v:190234$12990_Y + connect \$40 $or$libresoc.v:190235$12991_Y + connect \$42 $not$libresoc.v:190236$12992_Y + connect \$44 $and$libresoc.v:190237$12993_Y + connect \$46 $and$libresoc.v:190238$12994_Y + connect \$48 $eq$libresoc.v:190239$12995_Y + connect \$50 $and$libresoc.v:190240$12996_Y + connect \$52 $eq$libresoc.v:190241$12997_Y + connect \$54 $and$libresoc.v:190242$12998_Y + connect \$56 $and$libresoc.v:190243$12999_Y + connect \$58 $and$libresoc.v:190244$13000_Y + connect \$60 $or$libresoc.v:190245$13001_Y + connect \$62 $or$libresoc.v:190246$13002_Y + connect \$64 $or$libresoc.v:190247$13003_Y + connect \$66 $or$libresoc.v:190248$13004_Y + connect \$68 $and$libresoc.v:190249$13005_Y + connect \$6 $and$libresoc.v:190250$13006_Y + connect \$70 $and$libresoc.v:190251$13007_Y + connect \$72 $or$libresoc.v:190252$13008_Y + connect \$74 $and$libresoc.v:190253$13009_Y + connect \$76 $and$libresoc.v:190254$13010_Y + connect \$78 $and$libresoc.v:190255$13011_Y + connect \$80 $and$libresoc.v:190256$13012_Y + connect \$82 $and$libresoc.v:190257$13013_Y + connect \$84 $and$libresoc.v:190258$13014_Y + connect \$86 $ternary$libresoc.v:190259$13015_Y + connect \$88 $ternary$libresoc.v:190260$13016_Y + connect \$90 $ternary$libresoc.v:190261$13017_Y + connect \$92 $ternary$libresoc.v:190262$13018_Y + connect \$94 $ternary$libresoc.v:190263$13019_Y + connect \$96 $ternary$libresoc.v:190264$13020_Y + connect \$98 $and$libresoc.v:190265$13021_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$124 @@ -392824,111 +364207,111 @@ module \spr0 connect \all_rd_dly$next \all_rd connect \all_rd \$14 end -attribute \src "libresoc.v:189528.1-190048.10" +attribute \src "libresoc.v:190845.1-191369.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.alu_spr0.pipe.spr_main" attribute \generator "nMigen" module \spr_main - attribute \src "libresoc.v:189801.3-189816.6" - wire width 64 $0\fast1$7[63:0]$13240 - attribute \src "libresoc.v:189878.3-189893.6" + attribute \src "libresoc.v:191118.3-191133.6" + wire width 64 $0\fast1$7[63:0]$13226 + attribute \src "libresoc.v:191199.3-191214.6" wire $0\fast1_ok[0:0] - attribute \src "libresoc.v:189529.7-189529.20" + attribute \src "libresoc.v:190846.7-190846.20" wire $0\initial[0:0] - attribute \src "libresoc.v:189836.3-189877.6" + attribute \src "libresoc.v:191153.3-191198.6" wire width 64 $0\o[63:0] - attribute \src "libresoc.v:189836.3-189877.6" + attribute \src "libresoc.v:191153.3-191198.6" wire $0\o_ok[0:0] - attribute \src "libresoc.v:190026.3-190044.6" - wire width 64 $0\spr1$6[63:0]$13265 - attribute \src "libresoc.v:189817.3-189835.6" + attribute \src "libresoc.v:191347.3-191365.6" + wire width 64 $0\spr1$6[63:0]$13251 + attribute \src "libresoc.v:191134.3-191152.6" wire $0\spr1_ok[0:0] - attribute \src "libresoc.v:189981.3-190004.6" - wire width 2 $0\xer_ca$10[1:0]$13259 - attribute \src "libresoc.v:190005.3-190025.6" + attribute \src "libresoc.v:191302.3-191325.6" + wire width 2 $0\xer_ca$10[1:0]$13245 + attribute \src "libresoc.v:191326.3-191346.6" wire $0\xer_ca_ok[0:0] - attribute \src "libresoc.v:189936.3-189959.6" - wire width 2 $0\xer_ov$9[1:0]$13253 - attribute \src "libresoc.v:189960.3-189980.6" + attribute \src "libresoc.v:191257.3-191280.6" + wire width 2 $0\xer_ov$9[1:0]$13239 + attribute \src "libresoc.v:191281.3-191301.6" wire $0\xer_ov_ok[0:0] - attribute \src "libresoc.v:189894.3-189914.6" - wire $0\xer_so$8[0:0]$13247 - attribute \src "libresoc.v:189915.3-189935.6" + attribute \src "libresoc.v:191215.3-191235.6" + wire $0\xer_so$8[0:0]$13233 + attribute \src "libresoc.v:191236.3-191256.6" wire $0\xer_so_ok[0:0] - attribute \src "libresoc.v:189801.3-189816.6" - wire width 64 $1\fast1$7[63:0]$13241 - attribute \src "libresoc.v:189878.3-189893.6" + attribute \src "libresoc.v:191118.3-191133.6" + wire width 64 $1\fast1$7[63:0]$13227 + attribute \src "libresoc.v:191199.3-191214.6" wire $1\fast1_ok[0:0] - attribute \src "libresoc.v:189836.3-189877.6" + attribute \src "libresoc.v:191153.3-191198.6" wire width 64 $1\o[63:0] - attribute \src "libresoc.v:189836.3-189877.6" + attribute \src "libresoc.v:191153.3-191198.6" wire $1\o_ok[0:0] - attribute \src "libresoc.v:190026.3-190044.6" - wire width 64 $1\spr1$6[63:0]$13266 - attribute \src "libresoc.v:189817.3-189835.6" + attribute \src "libresoc.v:191347.3-191365.6" + wire width 64 $1\spr1$6[63:0]$13252 + attribute \src "libresoc.v:191134.3-191152.6" wire $1\spr1_ok[0:0] - attribute \src "libresoc.v:189981.3-190004.6" - wire width 2 $1\xer_ca$10[1:0]$13260 - attribute \src "libresoc.v:190005.3-190025.6" + attribute \src "libresoc.v:191302.3-191325.6" + wire width 2 $1\xer_ca$10[1:0]$13246 + attribute \src "libresoc.v:191326.3-191346.6" wire $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:189936.3-189959.6" - wire width 2 $1\xer_ov$9[1:0]$13254 - attribute \src "libresoc.v:189960.3-189980.6" + attribute \src "libresoc.v:191257.3-191280.6" + wire width 2 $1\xer_ov$9[1:0]$13240 + attribute \src "libresoc.v:191281.3-191301.6" wire $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:189894.3-189914.6" - wire $1\xer_so$8[0:0]$13248 - attribute \src "libresoc.v:189915.3-189935.6" + attribute \src "libresoc.v:191215.3-191235.6" + wire $1\xer_so$8[0:0]$13234 + attribute \src "libresoc.v:191236.3-191256.6" wire $1\xer_so_ok[0:0] - attribute \src "libresoc.v:189801.3-189816.6" - wire width 64 $2\fast1$7[63:0]$13242 - attribute \src "libresoc.v:189878.3-189893.6" + attribute \src "libresoc.v:191118.3-191133.6" + wire width 64 $2\fast1$7[63:0]$13228 + attribute \src "libresoc.v:191199.3-191214.6" wire $2\fast1_ok[0:0] - attribute \src "libresoc.v:189836.3-189877.6" + attribute \src "libresoc.v:191153.3-191198.6" wire width 64 $2\o[63:0] - attribute \src "libresoc.v:190026.3-190044.6" - wire width 64 $2\spr1$6[63:0]$13267 - attribute \src "libresoc.v:189817.3-189835.6" + attribute \src "libresoc.v:191347.3-191365.6" + wire width 64 $2\spr1$6[63:0]$13253 + attribute \src "libresoc.v:191134.3-191152.6" wire $2\spr1_ok[0:0] - attribute \src "libresoc.v:189981.3-190004.6" - wire width 2 $2\xer_ca$10[1:0]$13261 - attribute \src "libresoc.v:190005.3-190025.6" + attribute \src "libresoc.v:191302.3-191325.6" + wire width 2 $2\xer_ca$10[1:0]$13247 + attribute \src "libresoc.v:191326.3-191346.6" wire $2\xer_ca_ok[0:0] - attribute \src "libresoc.v:189936.3-189959.6" - wire width 2 $2\xer_ov$9[1:0]$13255 - attribute \src "libresoc.v:189960.3-189980.6" + attribute \src "libresoc.v:191257.3-191280.6" + wire width 2 $2\xer_ov$9[1:0]$13241 + attribute \src "libresoc.v:191281.3-191301.6" wire $2\xer_ov_ok[0:0] - attribute \src "libresoc.v:189894.3-189914.6" - wire $2\xer_so$8[0:0]$13249 - attribute \src "libresoc.v:189915.3-189935.6" + attribute \src "libresoc.v:191215.3-191235.6" + wire $2\xer_so$8[0:0]$13235 + attribute \src "libresoc.v:191236.3-191256.6" wire $2\xer_so_ok[0:0] - attribute \src "libresoc.v:189836.3-189877.6" + attribute \src "libresoc.v:191153.3-191198.6" wire width 46 $3\o[63:18] - attribute \src "libresoc.v:189981.3-190004.6" - wire width 2 $3\xer_ca$10[1:0]$13262 - attribute \src "libresoc.v:190005.3-190025.6" + attribute \src "libresoc.v:191302.3-191325.6" + wire width 2 $3\xer_ca$10[1:0]$13248 + attribute \src "libresoc.v:191326.3-191346.6" wire $3\xer_ca_ok[0:0] - attribute \src "libresoc.v:189936.3-189959.6" - wire width 2 $3\xer_ov$9[1:0]$13256 - attribute \src "libresoc.v:189960.3-189980.6" + attribute \src "libresoc.v:191257.3-191280.6" + wire width 2 $3\xer_ov$9[1:0]$13242 + attribute \src "libresoc.v:191281.3-191301.6" wire $3\xer_ov_ok[0:0] - attribute \src "libresoc.v:189894.3-189914.6" - wire $3\xer_so$8[0:0]$13250 - attribute \src "libresoc.v:189915.3-189935.6" + attribute \src "libresoc.v:191215.3-191235.6" + wire $3\xer_so$8[0:0]$13236 + attribute \src "libresoc.v:191236.3-191256.6" wire $3\xer_so_ok[0:0] - attribute \src "libresoc.v:189794.18-189794.106" - wire $eq$libresoc.v:189794$13232_Y - attribute \src "libresoc.v:189795.18-189795.106" - wire $eq$libresoc.v:189795$13233_Y - attribute \src "libresoc.v:189796.18-189796.106" - wire $eq$libresoc.v:189796$13234_Y - attribute \src "libresoc.v:189797.18-189797.106" - wire $eq$libresoc.v:189797$13235_Y - attribute \src "libresoc.v:189798.18-189798.106" - wire $eq$libresoc.v:189798$13236_Y - attribute \src "libresoc.v:189799.18-189799.106" - wire $eq$libresoc.v:189799$13237_Y - attribute \src "libresoc.v:189800.18-189800.106" - wire $eq$libresoc.v:189800$13238_Y + attribute \src "libresoc.v:191111.18-191111.106" + wire $eq$libresoc.v:191111$13218_Y + attribute \src "libresoc.v:191112.18-191112.106" + wire $eq$libresoc.v:191112$13219_Y + attribute \src "libresoc.v:191113.18-191113.106" + wire $eq$libresoc.v:191113$13220_Y + attribute \src "libresoc.v:191114.18-191114.106" + wire $eq$libresoc.v:191114$13221_Y + attribute \src "libresoc.v:191115.18-191115.106" + wire $eq$libresoc.v:191115$13222_Y + attribute \src "libresoc.v:191116.18-191116.106" + wire $eq$libresoc.v:191116$13223_Y + attribute \src "libresoc.v:191117.18-191117.106" + wire $eq$libresoc.v:191117$13224_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" wire \$11 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" @@ -392949,7 +364332,7 @@ module \spr_main wire width 64 output 20 \fast1$7 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 21 \fast1_ok - attribute \src "libresoc.v:189529.7-189529.15" + attribute \src "libresoc.v:190846.7-190846.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:45" wire width 2 input 28 \muxid @@ -393184,7 +364567,7 @@ module \spr_main attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 23 \xer_so_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:189794$13232 + cell $eq $eq$libresoc.v:191111$13218 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -393192,10 +364575,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:189794$13232_Y + connect \Y $eq$libresoc.v:191111$13218_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:189795$13233 + cell $eq $eq$libresoc.v:191112$13219 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -393203,10 +364586,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:189795$13233_Y + connect \Y $eq$libresoc.v:191112$13219_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:189796$13234 + cell $eq $eq$libresoc.v:191113$13220 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -393214,10 +364597,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:189796$13234_Y + connect \Y $eq$libresoc.v:191113$13220_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:189797$13235 + cell $eq $eq$libresoc.v:191114$13221 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -393225,10 +364608,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:189797$13235_Y + connect \Y $eq$libresoc.v:191114$13221_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:189798$13236 + cell $eq $eq$libresoc.v:191115$13222 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -393236,10 +364619,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:189798$13236_Y + connect \Y $eq$libresoc.v:191115$13222_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $eq$libresoc.v:189799$13237 + cell $eq $eq$libresoc.v:191116$13223 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -393247,10 +364630,10 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:189799$13237_Y + connect \Y $eq$libresoc.v:191116$13223_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82" - cell $eq $eq$libresoc.v:189800$13238 + cell $eq $eq$libresoc.v:191117$13224 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -393258,24 +364641,24 @@ module \spr_main parameter \Y_WIDTH 1 connect \A \spr connect \B 10'0000000001 - connect \Y $eq$libresoc.v:189800$13238_Y + connect \Y $eq$libresoc.v:191117$13224_Y end - attribute \src "libresoc.v:189529.7-189529.20" - process $proc$libresoc.v:189529$13268 + attribute \src "libresoc.v:190846.7-190846.20" + process $proc$libresoc.v:190846$13254 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:189801.3-189816.6" - process $proc$libresoc.v:189801$13239 + attribute \src "libresoc.v:191118.3-191133.6" + process $proc$libresoc.v:191118$13225 assign { } { } assign { } { } - assign $0\fast1$7[63:0]$13240 $1\fast1$7[63:0]$13241 - attribute \src "libresoc.v:189802.5-189802.29" + assign $0\fast1$7[63:0]$13226 $1\fast1$7[63:0]$13227 + attribute \src "libresoc.v:191119.5-191119.29" switch \initial - attribute \src "libresoc.v:189802.9-189802.17" + attribute \src "libresoc.v:191119.9-191119.17" case 1'1 case end @@ -393284,30 +364667,30 @@ module \spr_main attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\fast1$7[63:0]$13241 $2\fast1$7[63:0]$13242 + assign $1\fast1$7[63:0]$13227 $2\fast1$7[63:0]$13228 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } - assign $2\fast1$7[63:0]$13242 \ra + assign $2\fast1$7[63:0]$13228 \ra case - assign $2\fast1$7[63:0]$13242 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fast1$7[63:0]$13228 64'0000000000000000000000000000000000000000000000000000000000000000 end case - assign $1\fast1$7[63:0]$13241 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fast1$7[63:0]$13227 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \fast1$7 $0\fast1$7[63:0]$13240 + update \fast1$7 $0\fast1$7[63:0]$13226 end - attribute \src "libresoc.v:189817.3-189835.6" - process $proc$libresoc.v:189817$13243 + attribute \src "libresoc.v:191134.3-191152.6" + process $proc$libresoc.v:191134$13229 assign { } { } assign { } { } assign $0\spr1_ok[0:0] $1\spr1_ok[0:0] - attribute \src "libresoc.v:189818.5-189818.29" + attribute \src "libresoc.v:191135.5-191135.29" switch \initial - attribute \src "libresoc.v:189818.9-189818.17" + attribute \src "libresoc.v:191135.9-191135.17" case 1'1 case end @@ -393333,23 +364716,27 @@ module \spr_main sync always update \spr1_ok $0\spr1_ok[0:0] end - attribute \src "libresoc.v:189836.3-189877.6" - process $proc$libresoc.v:189836$13244 + attribute \src "libresoc.v:191153.3-191198.6" + process $proc$libresoc.v:191153$13230 assign { } { } assign { } { } assign { } { } assign { } { } assign $0\o_ok[0:0] $1\o_ok[0:0] assign $0\o[63:0] $1\o[63:0] - attribute \src "libresoc.v:189837.5-189837.29" + attribute \src "libresoc.v:191154.5-191154.29" switch \initial - attribute \src "libresoc.v:189837.9-189837.17" + attribute \src "libresoc.v:191154.9-191154.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" switch \spr_op__insn_type attribute \src "libresoc.v:0.0-0.0" + case 7'0110001 + assign $1\o_ok[0:0] 1'0 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 7'0101110 assign { } { } assign { } { } @@ -393394,14 +364781,14 @@ module \spr_main update \o_ok $0\o_ok[0:0] update \o $0\o[63:0] end - attribute \src "libresoc.v:189878.3-189893.6" - process $proc$libresoc.v:189878$13245 + attribute \src "libresoc.v:191199.3-191214.6" + process $proc$libresoc.v:191199$13231 assign { } { } assign { } { } assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] - attribute \src "libresoc.v:189879.5-189879.29" + attribute \src "libresoc.v:191200.5-191200.29" switch \initial - attribute \src "libresoc.v:189879.9-189879.17" + attribute \src "libresoc.v:191200.9-191200.17" case 1'1 case end @@ -393426,14 +364813,14 @@ module \spr_main sync always update \fast1_ok $0\fast1_ok[0:0] end - attribute \src "libresoc.v:189894.3-189914.6" - process $proc$libresoc.v:189894$13246 + attribute \src "libresoc.v:191215.3-191235.6" + process $proc$libresoc.v:191215$13232 assign { } { } assign { } { } - assign $0\xer_so$8[0:0]$13247 $1\xer_so$8[0:0]$13248 - attribute \src "libresoc.v:189895.5-189895.29" + assign $0\xer_so$8[0:0]$13233 $1\xer_so$8[0:0]$13234 + attribute \src "libresoc.v:191216.5-191216.29" switch \initial - attribute \src "libresoc.v:189895.9-189895.17" + attribute \src "libresoc.v:191216.9-191216.17" case 1'1 case end @@ -393442,39 +364829,39 @@ module \spr_main attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\xer_so$8[0:0]$13248 $2\xer_so$8[0:0]$13249 + assign $1\xer_so$8[0:0]$13234 $2\xer_so$8[0:0]$13235 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } - assign $2\xer_so$8[0:0]$13249 $3\xer_so$8[0:0]$13250 + assign $2\xer_so$8[0:0]$13235 $3\xer_so$8[0:0]$13236 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" switch \$11 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\xer_so$8[0:0]$13250 \ra [31] + assign $3\xer_so$8[0:0]$13236 \ra [31] case - assign $3\xer_so$8[0:0]$13250 1'0 + assign $3\xer_so$8[0:0]$13236 1'0 end case - assign $2\xer_so$8[0:0]$13249 1'0 + assign $2\xer_so$8[0:0]$13235 1'0 end case - assign $1\xer_so$8[0:0]$13248 1'0 + assign $1\xer_so$8[0:0]$13234 1'0 end sync always - update \xer_so$8 $0\xer_so$8[0:0]$13247 + update \xer_so$8 $0\xer_so$8[0:0]$13233 end - attribute \src "libresoc.v:189915.3-189935.6" - process $proc$libresoc.v:189915$13251 + attribute \src "libresoc.v:191236.3-191256.6" + process $proc$libresoc.v:191236$13237 assign { } { } assign { } { } assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] - attribute \src "libresoc.v:189916.5-189916.29" + attribute \src "libresoc.v:191237.5-191237.29" switch \initial - attribute \src "libresoc.v:189916.9-189916.17" + attribute \src "libresoc.v:191237.9-191237.17" case 1'1 case end @@ -393508,14 +364895,14 @@ module \spr_main sync always update \xer_so_ok $0\xer_so_ok[0:0] end - attribute \src "libresoc.v:189936.3-189959.6" - process $proc$libresoc.v:189936$13252 + attribute \src "libresoc.v:191257.3-191280.6" + process $proc$libresoc.v:191257$13238 assign { } { } assign { } { } - assign $0\xer_ov$9[1:0]$13253 $1\xer_ov$9[1:0]$13254 - attribute \src "libresoc.v:189937.5-189937.29" + assign $0\xer_ov$9[1:0]$13239 $1\xer_ov$9[1:0]$13240 + attribute \src "libresoc.v:191258.5-191258.29" switch \initial - attribute \src "libresoc.v:189937.9-189937.17" + attribute \src "libresoc.v:191258.9-191258.17" case 1'1 case end @@ -393524,40 +364911,40 @@ module \spr_main attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\xer_ov$9[1:0]$13254 $2\xer_ov$9[1:0]$13255 + assign $1\xer_ov$9[1:0]$13240 $2\xer_ov$9[1:0]$13241 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } - assign $2\xer_ov$9[1:0]$13255 $3\xer_ov$9[1:0]$13256 + assign $2\xer_ov$9[1:0]$13241 $3\xer_ov$9[1:0]$13242 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" switch \$15 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\xer_ov$9[1:0]$13256 [0] \ra [30] - assign $3\xer_ov$9[1:0]$13256 [1] \ra [19] + assign $3\xer_ov$9[1:0]$13242 [0] \ra [30] + assign $3\xer_ov$9[1:0]$13242 [1] \ra [19] case - assign $3\xer_ov$9[1:0]$13256 2'00 + assign $3\xer_ov$9[1:0]$13242 2'00 end case - assign $2\xer_ov$9[1:0]$13255 2'00 + assign $2\xer_ov$9[1:0]$13241 2'00 end case - assign $1\xer_ov$9[1:0]$13254 2'00 + assign $1\xer_ov$9[1:0]$13240 2'00 end sync always - update \xer_ov$9 $0\xer_ov$9[1:0]$13253 + update \xer_ov$9 $0\xer_ov$9[1:0]$13239 end - attribute \src "libresoc.v:189960.3-189980.6" - process $proc$libresoc.v:189960$13257 + attribute \src "libresoc.v:191281.3-191301.6" + process $proc$libresoc.v:191281$13243 assign { } { } assign { } { } assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] - attribute \src "libresoc.v:189961.5-189961.29" + attribute \src "libresoc.v:191282.5-191282.29" switch \initial - attribute \src "libresoc.v:189961.9-189961.17" + attribute \src "libresoc.v:191282.9-191282.17" case 1'1 case end @@ -393591,14 +364978,14 @@ module \spr_main sync always update \xer_ov_ok $0\xer_ov_ok[0:0] end - attribute \src "libresoc.v:189981.3-190004.6" - process $proc$libresoc.v:189981$13258 + attribute \src "libresoc.v:191302.3-191325.6" + process $proc$libresoc.v:191302$13244 assign { } { } assign { } { } - assign $0\xer_ca$10[1:0]$13259 $1\xer_ca$10[1:0]$13260 - attribute \src "libresoc.v:189982.5-189982.29" + assign $0\xer_ca$10[1:0]$13245 $1\xer_ca$10[1:0]$13246 + attribute \src "libresoc.v:191303.5-191303.29" switch \initial - attribute \src "libresoc.v:189982.9-189982.17" + attribute \src "libresoc.v:191303.9-191303.17" case 1'1 case end @@ -393607,40 +364994,40 @@ module \spr_main attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\xer_ca$10[1:0]$13260 $2\xer_ca$10[1:0]$13261 + assign $1\xer_ca$10[1:0]$13246 $2\xer_ca$10[1:0]$13247 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 assign { } { } - assign $2\xer_ca$10[1:0]$13261 $3\xer_ca$10[1:0]$13262 + assign $2\xer_ca$10[1:0]$13247 $3\xer_ca$10[1:0]$13248 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" switch \$19 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\xer_ca$10[1:0]$13262 [0] \ra [29] - assign $3\xer_ca$10[1:0]$13262 [1] \ra [18] + assign $3\xer_ca$10[1:0]$13248 [0] \ra [29] + assign $3\xer_ca$10[1:0]$13248 [1] \ra [18] case - assign $3\xer_ca$10[1:0]$13262 2'00 + assign $3\xer_ca$10[1:0]$13248 2'00 end case - assign $2\xer_ca$10[1:0]$13261 2'00 + assign $2\xer_ca$10[1:0]$13247 2'00 end case - assign $1\xer_ca$10[1:0]$13260 2'00 + assign $1\xer_ca$10[1:0]$13246 2'00 end sync always - update \xer_ca$10 $0\xer_ca$10[1:0]$13259 + update \xer_ca$10 $0\xer_ca$10[1:0]$13245 end - attribute \src "libresoc.v:190005.3-190025.6" - process $proc$libresoc.v:190005$13263 + attribute \src "libresoc.v:191326.3-191346.6" + process $proc$libresoc.v:191326$13249 assign { } { } assign { } { } assign $0\xer_ca_ok[0:0] $1\xer_ca_ok[0:0] - attribute \src "libresoc.v:190006.5-190006.29" + attribute \src "libresoc.v:191327.5-191327.29" switch \initial - attribute \src "libresoc.v:190006.9-190006.17" + attribute \src "libresoc.v:191327.9-191327.17" case 1'1 case end @@ -393674,14 +365061,14 @@ module \spr_main sync always update \xer_ca_ok $0\xer_ca_ok[0:0] end - attribute \src "libresoc.v:190026.3-190044.6" - process $proc$libresoc.v:190026$13264 + attribute \src "libresoc.v:191347.3-191365.6" + process $proc$libresoc.v:191347$13250 assign { } { } assign { } { } - assign $0\spr1$6[63:0]$13265 $1\spr1$6[63:0]$13266 - attribute \src "libresoc.v:190027.5-190027.29" + assign $0\spr1$6[63:0]$13251 $1\spr1$6[63:0]$13252 + attribute \src "libresoc.v:191348.5-191348.29" switch \initial - attribute \src "libresoc.v:190027.9-190027.17" + attribute \src "libresoc.v:191348.9-191348.17" case 1'1 case end @@ -393690,62 +365077,62 @@ module \spr_main attribute \src "libresoc.v:0.0-0.0" case 7'0110001 assign { } { } - assign $1\spr1$6[63:0]$13266 $2\spr1$6[63:0]$13267 + assign $1\spr1$6[63:0]$13252 $2\spr1$6[63:0]$13253 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" switch \spr attribute \src "libresoc.v:0.0-0.0" case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 - assign $2\spr1$6[63:0]$13267 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\spr1$6[63:0]$13253 64'0000000000000000000000000000000000000000000000000000000000000000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\spr1$6[63:0]$13267 \ra + assign $2\spr1$6[63:0]$13253 \ra end case - assign $1\spr1$6[63:0]$13266 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\spr1$6[63:0]$13252 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \spr1$6 $0\spr1$6[63:0]$13265 + update \spr1$6 $0\spr1$6[63:0]$13251 end - connect \$11 $eq$libresoc.v:189794$13232_Y - connect \$13 $eq$libresoc.v:189795$13233_Y - connect \$15 $eq$libresoc.v:189796$13234_Y - connect \$17 $eq$libresoc.v:189797$13235_Y - connect \$19 $eq$libresoc.v:189798$13236_Y - connect \$21 $eq$libresoc.v:189799$13237_Y - connect \$23 $eq$libresoc.v:189800$13238_Y + connect \$11 $eq$libresoc.v:191111$13218_Y + connect \$13 $eq$libresoc.v:191112$13219_Y + connect \$15 $eq$libresoc.v:191113$13220_Y + connect \$17 $eq$libresoc.v:191114$13221_Y + connect \$19 $eq$libresoc.v:191115$13222_Y + connect \$21 $eq$libresoc.v:191116$13223_Y + connect \$23 $eq$libresoc.v:191117$13224_Y connect { \spr_op__is_32bit$5 \spr_op__insn$4 \spr_op__fn_unit$3 \spr_op__insn_type$2 } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } connect \muxid$1 \muxid connect \spr { \spr_op__insn [15:11] \spr_op__insn [20:16] } end -attribute \src "libresoc.v:190052.1-190888.10" +attribute \src "libresoc.v:191373.1-192839.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_a.sprmap" attribute \generator "nMigen" module \sprmap - attribute \src "libresoc.v:190182.3-190212.6" + attribute \src "libresoc.v:191503.3-191824.6" wire width 3 $0\fast_o[2:0] - attribute \src "libresoc.v:190213.3-190243.6" + attribute \src "libresoc.v:191825.3-192146.6" wire $0\fast_o_ok[0:0] - attribute \src "libresoc.v:190053.7-190053.20" + attribute \src "libresoc.v:191374.7-191374.20" wire $0\initial[0:0] - attribute \src "libresoc.v:190244.3-190565.6" + attribute \src "libresoc.v:192147.3-192492.6" wire width 10 $0\spr_o[9:0] - attribute \src "libresoc.v:190566.3-190887.6" + attribute \src "libresoc.v:192493.3-192838.6" wire $0\spr_o_ok[0:0] - attribute \src "libresoc.v:190182.3-190212.6" + attribute \src "libresoc.v:191503.3-191824.6" wire width 3 $1\fast_o[2:0] - attribute \src "libresoc.v:190213.3-190243.6" + attribute \src "libresoc.v:191825.3-192146.6" wire $1\fast_o_ok[0:0] - attribute \src "libresoc.v:190244.3-190565.6" + attribute \src "libresoc.v:192147.3-192492.6" wire width 10 $1\spr_o[9:0] - attribute \src "libresoc.v:190566.3-190887.6" + attribute \src "libresoc.v:192493.3-192838.6" wire $1\spr_o_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 3 \fast_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 4 \fast_o_ok - attribute \src "libresoc.v:190053.7-190053.15" + attribute \src "libresoc.v:191374.7-191374.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:69" wire width 10 input 5 \spr_i @@ -393867,55 +365254,346 @@ module \sprmap wire width 10 output 1 \spr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \spr_o_ok - attribute \src "libresoc.v:190053.7-190053.20" - process $proc$libresoc.v:190053$13273 + attribute \src "libresoc.v:191374.7-191374.20" + process $proc$libresoc.v:191374$13259 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:190182.3-190212.6" - process $proc$libresoc.v:190182$13269 + attribute \src "libresoc.v:191503.3-191824.6" + process $proc$libresoc.v:191503$13255 assign { } { } assign { } { } assign $0\fast_o[2:0] $1\fast_o[2:0] - attribute \src "libresoc.v:190183.5-190183.29" + attribute \src "libresoc.v:191504.5-191504.29" switch \initial - attribute \src "libresoc.v:190183.9-190183.17" + attribute \src "libresoc.v:191504.9-191504.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75" switch \spr_i attribute \src "libresoc.v:0.0-0.0" - case 10'0000000001 - assign { } { } - assign $1\fast_o[2:0] 3'101 + case 10'0000000001 + assign { } { } + assign $1\fast_o[2:0] 3'101 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000000011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001000 + assign { } { } + assign $1\fast_o[2:0] 3'001 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 + assign { } { } + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010110 + assign { } { } + assign $1\fast_o[2:0] 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011010 + assign { } { } + assign $1\fast_o[2:0] 3'011 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011011 + assign { } { } + assign $1\fast_o[2:0] 3'100 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011100 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000110000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000111101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010001000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011111 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110100 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111100 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001100 + assign { } { } + assign $1\fast_o[2:0] 3'111 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011100 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011111 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110100 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111111 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101011101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110111110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111010000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011000000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011010000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011010001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000100 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000111 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001100 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010000 + assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 10'0000001000 - assign { } { } - assign $1\fast_o[2:0] 3'001 + case 10'1100010001 + assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 10'0000001001 - assign { } { } + case 10'1100010010 assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 10'0000010110 - assign { } { } - assign $1\fast_o[2:0] 3'110 + case 10'1100010011 + assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 10'0000011010 - assign { } { } - assign $1\fast_o[2:0] 3'011 + case 10'1100010100 + assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 10'0000011011 - assign { } { } - assign $1\fast_o[2:0] 3'100 + case 10'1100010101 + assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" - case 10'0100001100 - assign { } { } - assign $1\fast_o[2:0] 3'111 + case 10'1100010110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010111 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011100 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100100 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101011 + assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" case 10'1100101111 assign { } { } @@ -393926,14 +365604,14 @@ module \sprmap sync always update \fast_o $0\fast_o[2:0] end - attribute \src "libresoc.v:190213.3-190243.6" - process $proc$libresoc.v:190213$13270 + attribute \src "libresoc.v:191825.3-192146.6" + process $proc$libresoc.v:191825$13256 assign { } { } assign { } { } assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] - attribute \src "libresoc.v:190214.5-190214.29" + attribute \src "libresoc.v:191826.5-191826.29" switch \initial - attribute \src "libresoc.v:190214.9-190214.17" + attribute \src "libresoc.v:191826.9-191826.17" case 1'1 case end @@ -393944,6 +365622,9 @@ module \sprmap assign { } { } assign $1\fast_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 10'0000000011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 10'0000001000 assign { } { } assign $1\fast_o_ok[0:0] 1'1 @@ -393952,6 +365633,18 @@ module \sprmap assign { } { } assign $1\fast_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 10'0000001101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 10'0000010110 assign { } { } assign $1\fast_o_ok[0:0] 1'1 @@ -393964,10 +365657,286 @@ module \sprmap assign { } { } assign $1\fast_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 10'0000011100 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000110000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000111101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010001000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011111 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110100 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111100 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 10'0100001100 assign { } { } assign $1\fast_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011100 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011111 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110100 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111111 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101011101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110111110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111010000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011000000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011010000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011010001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000100 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000111 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001100 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010100 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010111 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011100 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100100 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 10'1100101111 assign { } { } assign $1\fast_o_ok[0:0] 1'1 @@ -393977,24 +365946,33 @@ module \sprmap sync always update \fast_o_ok $0\fast_o_ok[0:0] end - attribute \src "libresoc.v:190244.3-190565.6" - process $proc$libresoc.v:190244$13271 + attribute \src "libresoc.v:192147.3-192492.6" + process $proc$libresoc.v:192147$13257 assign { } { } assign { } { } assign $0\spr_o[9:0] $1\spr_o[9:0] - attribute \src "libresoc.v:190245.5-190245.29" + attribute \src "libresoc.v:192148.5-192148.29" switch \initial - attribute \src "libresoc.v:190245.9-190245.17" + attribute \src "libresoc.v:192148.9-192148.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75" switch \spr_i attribute \src "libresoc.v:0.0-0.0" + case 10'0000000001 + assign $1\spr_o[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" case 10'0000000011 assign { } { } assign $1\spr_o[9:0] 10'0000000001 attribute \src "libresoc.v:0.0-0.0" + case 10'0000001000 + assign $1\spr_o[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 + assign $1\spr_o[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" case 10'0000001101 assign { } { } assign $1\spr_o[9:0] 10'0000000100 @@ -394011,6 +365989,15 @@ module \sprmap assign { } { } assign $1\spr_o[9:0] 10'0000000111 attribute \src "libresoc.v:0.0-0.0" + case 10'0000010110 + assign $1\spr_o[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011010 + assign $1\spr_o[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011011 + assign $1\spr_o[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" case 10'0000011100 assign { } { } assign $1\spr_o[9:0] 10'0000001011 @@ -394103,6 +366090,9 @@ module \sprmap assign { } { } assign $1\spr_o[9:0] 10'0000100001 attribute \src "libresoc.v:0.0-0.0" + case 10'0100001100 + assign $1\spr_o[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" case 10'0100001101 assign { } { } assign $1\spr_o[9:0] 10'0000100011 @@ -394379,6 +366369,9 @@ module \sprmap assign { } { } assign $1\spr_o[9:0] 10'0001100111 attribute \src "libresoc.v:0.0-0.0" + case 10'1100101111 + assign $1\spr_o[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" case 10'1100110000 assign { } { } assign $1\spr_o[9:0] 10'0001101001 @@ -394416,24 +366409,33 @@ module \sprmap sync always update \spr_o $0\spr_o[9:0] end - attribute \src "libresoc.v:190566.3-190887.6" - process $proc$libresoc.v:190566$13272 + attribute \src "libresoc.v:192493.3-192838.6" + process $proc$libresoc.v:192493$13258 assign { } { } assign { } { } assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] - attribute \src "libresoc.v:190567.5-190567.29" + attribute \src "libresoc.v:192494.5-192494.29" switch \initial - attribute \src "libresoc.v:190567.9-190567.17" + attribute \src "libresoc.v:192494.9-192494.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75" switch \spr_i attribute \src "libresoc.v:0.0-0.0" + case 10'0000000001 + assign $1\spr_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 10'0000000011 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 10'0000001000 + assign $1\spr_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 + assign $1\spr_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 10'0000001101 assign { } { } assign $1\spr_o_ok[0:0] 1'1 @@ -394450,6 +366452,15 @@ module \sprmap assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 10'0000010110 + assign $1\spr_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011010 + assign $1\spr_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011011 + assign $1\spr_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 10'0000011100 assign { } { } assign $1\spr_o_ok[0:0] 1'1 @@ -394542,6 +366553,9 @@ module \sprmap assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 10'0100001100 + assign $1\spr_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 10'0100001101 assign { } { } assign $1\spr_o_ok[0:0] 1'1 @@ -394818,6 +366832,9 @@ module \sprmap assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 10'1100101111 + assign $1\spr_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 10'1100110000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 @@ -394856,34 +366873,34 @@ module \sprmap update \spr_o_ok $0\spr_o_ok[0:0] end end -attribute \src "libresoc.v:190892.1-191728.10" +attribute \src "libresoc.v:192843.1-194309.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.dec2.dec_o.sprmap" attribute \generator "nMigen" module \sprmap$174 - attribute \src "libresoc.v:191022.3-191052.6" + attribute \src "libresoc.v:192973.3-193294.6" wire width 3 $0\fast_o[2:0] - attribute \src "libresoc.v:191053.3-191083.6" + attribute \src "libresoc.v:193295.3-193616.6" wire $0\fast_o_ok[0:0] - attribute \src "libresoc.v:190893.7-190893.20" + attribute \src "libresoc.v:192844.7-192844.20" wire $0\initial[0:0] - attribute \src "libresoc.v:191084.3-191405.6" + attribute \src "libresoc.v:193617.3-193962.6" wire width 10 $0\spr_o[9:0] - attribute \src "libresoc.v:191406.3-191727.6" + attribute \src "libresoc.v:193963.3-194308.6" wire $0\spr_o_ok[0:0] - attribute \src "libresoc.v:191022.3-191052.6" + attribute \src "libresoc.v:192973.3-193294.6" wire width 3 $1\fast_o[2:0] - attribute \src "libresoc.v:191053.3-191083.6" + attribute \src "libresoc.v:193295.3-193616.6" wire $1\fast_o_ok[0:0] - attribute \src "libresoc.v:191084.3-191405.6" + attribute \src "libresoc.v:193617.3-193962.6" wire width 10 $1\spr_o[9:0] - attribute \src "libresoc.v:191406.3-191727.6" + attribute \src "libresoc.v:193963.3-194308.6" wire $1\spr_o_ok[0:0] attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 3 output 3 \fast_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 4 \fast_o_ok - attribute \src "libresoc.v:190893.7-190893.15" + attribute \src "libresoc.v:192844.7-192844.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:69" wire width 10 input 5 \spr_i @@ -395005,22 +367022,22 @@ module \sprmap$174 wire width 10 output 1 \spr_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 2 \spr_o_ok - attribute \src "libresoc.v:190893.7-190893.20" - process $proc$libresoc.v:190893$13278 + attribute \src "libresoc.v:192844.7-192844.20" + process $proc$libresoc.v:192844$13264 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:191022.3-191052.6" - process $proc$libresoc.v:191022$13274 + attribute \src "libresoc.v:192973.3-193294.6" + process $proc$libresoc.v:192973$13260 assign { } { } assign { } { } assign $0\fast_o[2:0] $1\fast_o[2:0] - attribute \src "libresoc.v:191023.5-191023.29" + attribute \src "libresoc.v:192974.5-192974.29" switch \initial - attribute \src "libresoc.v:191023.9-191023.17" + attribute \src "libresoc.v:192974.9-192974.17" case 1'1 case end @@ -395031,6 +367048,9 @@ module \sprmap$174 assign { } { } assign $1\fast_o[2:0] 3'101 attribute \src "libresoc.v:0.0-0.0" + case 10'0000000011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" case 10'0000001000 assign { } { } assign $1\fast_o[2:0] 3'001 @@ -395039,6 +367059,18 @@ module \sprmap$174 assign { } { } assign $1\fast_o[2:0] 3'000 attribute \src "libresoc.v:0.0-0.0" + case 10'0000001101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" case 10'0000010110 assign { } { } assign $1\fast_o[2:0] 3'110 @@ -395051,10 +367083,286 @@ module \sprmap$174 assign { } { } assign $1\fast_o[2:0] 3'100 attribute \src "libresoc.v:0.0-0.0" + case 10'0000011100 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000110000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000111101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010001000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011111 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110100 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111100 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" case 10'0100001100 assign { } { } assign $1\fast_o[2:0] 3'111 attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011100 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011111 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110100 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111111 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101011101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110111110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111010000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011000000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011010000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011010001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000100 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000111 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001100 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010100 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010111 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011100 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100100 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100101 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100110 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101000 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101001 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101010 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101011 + assign $1\fast_o[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" case 10'1100101111 assign { } { } assign $1\fast_o[2:0] 3'010 @@ -395064,14 +367372,14 @@ module \sprmap$174 sync always update \fast_o $0\fast_o[2:0] end - attribute \src "libresoc.v:191053.3-191083.6" - process $proc$libresoc.v:191053$13275 + attribute \src "libresoc.v:193295.3-193616.6" + process $proc$libresoc.v:193295$13261 assign { } { } assign { } { } assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] - attribute \src "libresoc.v:191054.5-191054.29" + attribute \src "libresoc.v:193296.5-193296.29" switch \initial - attribute \src "libresoc.v:191054.9-191054.17" + attribute \src "libresoc.v:193296.9-193296.17" case 1'1 case end @@ -395082,6 +367390,9 @@ module \sprmap$174 assign { } { } assign $1\fast_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 10'0000000011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 10'0000001000 assign { } { } assign $1\fast_o_ok[0:0] 1'1 @@ -395090,6 +367401,18 @@ module \sprmap$174 assign { } { } assign $1\fast_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 10'0000001101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000010011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 10'0000010110 assign { } { } assign $1\fast_o_ok[0:0] 1'1 @@ -395102,10 +367425,286 @@ module \sprmap$174 assign { } { } assign $1\fast_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 10'0000011100 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000110000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000111101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010000011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010001000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010010000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010011111 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010110100 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111100 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0010111110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100000011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 10'0100001100 assign { } { } assign $1\fast_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 10'0100001101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100010011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011100 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100011111 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110100 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100110110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0100111111 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101010011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0101011101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0110111110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0111010000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011000000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011010000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1011010001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000100 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100000111 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001100 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100001110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010100 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100010111 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011100 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100011110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100100 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100101 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100100110 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101000 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101001 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101010 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'1100101011 + assign $1\fast_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 10'1100101111 assign { } { } assign $1\fast_o_ok[0:0] 1'1 @@ -395115,24 +367714,33 @@ module \sprmap$174 sync always update \fast_o_ok $0\fast_o_ok[0:0] end - attribute \src "libresoc.v:191084.3-191405.6" - process $proc$libresoc.v:191084$13276 + attribute \src "libresoc.v:193617.3-193962.6" + process $proc$libresoc.v:193617$13262 assign { } { } assign { } { } assign $0\spr_o[9:0] $1\spr_o[9:0] - attribute \src "libresoc.v:191085.5-191085.29" + attribute \src "libresoc.v:193618.5-193618.29" switch \initial - attribute \src "libresoc.v:191085.9-191085.17" + attribute \src "libresoc.v:193618.9-193618.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75" switch \spr_i attribute \src "libresoc.v:0.0-0.0" + case 10'0000000001 + assign $1\spr_o[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" case 10'0000000011 assign { } { } assign $1\spr_o[9:0] 10'0000000001 attribute \src "libresoc.v:0.0-0.0" + case 10'0000001000 + assign $1\spr_o[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 + assign $1\spr_o[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" case 10'0000001101 assign { } { } assign $1\spr_o[9:0] 10'0000000100 @@ -395149,6 +367757,15 @@ module \sprmap$174 assign { } { } assign $1\spr_o[9:0] 10'0000000111 attribute \src "libresoc.v:0.0-0.0" + case 10'0000010110 + assign $1\spr_o[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011010 + assign $1\spr_o[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011011 + assign $1\spr_o[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" case 10'0000011100 assign { } { } assign $1\spr_o[9:0] 10'0000001011 @@ -395241,6 +367858,9 @@ module \sprmap$174 assign { } { } assign $1\spr_o[9:0] 10'0000100001 attribute \src "libresoc.v:0.0-0.0" + case 10'0100001100 + assign $1\spr_o[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" case 10'0100001101 assign { } { } assign $1\spr_o[9:0] 10'0000100011 @@ -395517,6 +368137,9 @@ module \sprmap$174 assign { } { } assign $1\spr_o[9:0] 10'0001100111 attribute \src "libresoc.v:0.0-0.0" + case 10'1100101111 + assign $1\spr_o[9:0] 10'0000000000 + attribute \src "libresoc.v:0.0-0.0" case 10'1100110000 assign { } { } assign $1\spr_o[9:0] 10'0001101001 @@ -395554,24 +368177,33 @@ module \sprmap$174 sync always update \spr_o $0\spr_o[9:0] end - attribute \src "libresoc.v:191406.3-191727.6" - process $proc$libresoc.v:191406$13277 + attribute \src "libresoc.v:193963.3-194308.6" + process $proc$libresoc.v:193963$13263 assign { } { } assign { } { } assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] - attribute \src "libresoc.v:191407.5-191407.29" + attribute \src "libresoc.v:193964.5-193964.29" switch \initial - attribute \src "libresoc.v:191407.9-191407.17" + attribute \src "libresoc.v:193964.9-193964.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75" switch \spr_i attribute \src "libresoc.v:0.0-0.0" + case 10'0000000001 + assign $1\spr_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 10'0000000011 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 10'0000001000 + assign $1\spr_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000001001 + assign $1\spr_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 10'0000001101 assign { } { } assign $1\spr_o_ok[0:0] 1'1 @@ -395588,6 +368220,15 @@ module \sprmap$174 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 10'0000010110 + assign $1\spr_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011010 + assign $1\spr_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 10'0000011011 + assign $1\spr_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 10'0000011100 assign { } { } assign $1\spr_o_ok[0:0] 1'1 @@ -395680,6 +368321,9 @@ module \sprmap$174 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 10'0100001100 + assign $1\spr_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 10'0100001101 assign { } { } assign $1\spr_o_ok[0:0] 1'1 @@ -395956,6 +368600,9 @@ module \sprmap$174 assign { } { } assign $1\spr_o_ok[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 10'1100101111 + assign $1\spr_o_ok[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 10'1100110000 assign { } { } assign $1\spr_o_ok[0:0] 1'1 @@ -395994,37 +368641,37 @@ module \sprmap$174 update \spr_o_ok $0\spr_o_ok[0:0] end end -attribute \src "libresoc.v:191732.1-191790.10" +attribute \src "libresoc.v:194313.1-194371.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.alu0.src_l" attribute \generator "nMigen" module \src_l - attribute \src "libresoc.v:191733.7-191733.20" + attribute \src "libresoc.v:194314.7-194314.20" wire $0\initial[0:0] - attribute \src "libresoc.v:191778.3-191786.6" - wire width 4 $0\q_int$next[3:0]$13289 - attribute \src "libresoc.v:191776.3-191777.27" + attribute \src "libresoc.v:194359.3-194367.6" + wire width 4 $0\q_int$next[3:0]$13275 + attribute \src "libresoc.v:194357.3-194358.27" wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:191778.3-191786.6" - wire width 4 $1\q_int$next[3:0]$13290 - attribute \src "libresoc.v:191755.13-191755.25" + attribute \src "libresoc.v:194359.3-194367.6" + wire width 4 $1\q_int$next[3:0]$13276 + attribute \src "libresoc.v:194336.13-194336.25" wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:191768.17-191768.96" - wire width 4 $and$libresoc.v:191768$13279_Y - attribute \src "libresoc.v:191773.17-191773.96" - wire width 4 $and$libresoc.v:191773$13284_Y - attribute \src "libresoc.v:191770.18-191770.93" - wire width 4 $not$libresoc.v:191770$13281_Y - attribute \src "libresoc.v:191772.17-191772.92" - wire width 4 $not$libresoc.v:191772$13283_Y - attribute \src "libresoc.v:191775.17-191775.92" - wire width 4 $not$libresoc.v:191775$13286_Y - attribute \src "libresoc.v:191769.18-191769.98" - wire width 4 $or$libresoc.v:191769$13280_Y - attribute \src "libresoc.v:191771.18-191771.99" - wire width 4 $or$libresoc.v:191771$13282_Y - attribute \src "libresoc.v:191774.17-191774.97" - wire width 4 $or$libresoc.v:191774$13285_Y + attribute \src "libresoc.v:194349.17-194349.96" + wire width 4 $and$libresoc.v:194349$13265_Y + attribute \src "libresoc.v:194354.17-194354.96" + wire width 4 $and$libresoc.v:194354$13270_Y + attribute \src "libresoc.v:194351.18-194351.93" + wire width 4 $not$libresoc.v:194351$13267_Y + attribute \src "libresoc.v:194353.17-194353.92" + wire width 4 $not$libresoc.v:194353$13269_Y + attribute \src "libresoc.v:194356.17-194356.92" + wire width 4 $not$libresoc.v:194356$13272_Y + attribute \src "libresoc.v:194350.18-194350.98" + wire width 4 $or$libresoc.v:194350$13266_Y + attribute \src "libresoc.v:194352.18-194352.99" + wire width 4 $or$libresoc.v:194352$13268_Y + attribute \src "libresoc.v:194355.17-194355.97" + wire width 4 $or$libresoc.v:194355$13271_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -396041,11 +368688,11 @@ module \src_l wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:191733.7-191733.15" + attribute \src "libresoc.v:194314.7-194314.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int @@ -396062,7 +368709,7 @@ module \src_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:191768$13279 + cell $and $and$libresoc.v:194349$13265 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -396070,10 +368717,10 @@ module \src_l parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:191768$13279_Y + connect \Y $and$libresoc.v:194349$13265_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:191773$13284 + cell $and $and$libresoc.v:194354$13270 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -396081,34 +368728,34 @@ module \src_l parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:191773$13284_Y + connect \Y $and$libresoc.v:194354$13270_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:191770$13281 + cell $not $not$libresoc.v:194351$13267 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_src - connect \Y $not$libresoc.v:191770$13281_Y + connect \Y $not$libresoc.v:194351$13267_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:191772$13283 + cell $not $not$libresoc.v:194353$13269 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src - connect \Y $not$libresoc.v:191772$13283_Y + connect \Y $not$libresoc.v:194353$13269_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:191775$13286 + cell $not $not$libresoc.v:194356$13272 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src - connect \Y $not$libresoc.v:191775$13286_Y + connect \Y $not$libresoc.v:194356$13272_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:191769$13280 + cell $or $or$libresoc.v:194350$13266 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -396116,10 +368763,10 @@ module \src_l parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:191769$13280_Y + connect \Y $or$libresoc.v:194350$13266_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:191771$13282 + cell $or $or$libresoc.v:194352$13268 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -396127,10 +368774,10 @@ module \src_l parameter \Y_WIDTH 4 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:191771$13282_Y + connect \Y $or$libresoc.v:194352$13268_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:191774$13285 + cell $or $or$libresoc.v:194355$13271 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -396138,39 +368785,39 @@ module \src_l parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:191774$13285_Y + connect \Y $or$libresoc.v:194355$13271_Y end - attribute \src "libresoc.v:191733.7-191733.20" - process $proc$libresoc.v:191733$13291 + attribute \src "libresoc.v:194314.7-194314.20" + process $proc$libresoc.v:194314$13277 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:191755.13-191755.25" - process $proc$libresoc.v:191755$13292 + attribute \src "libresoc.v:194336.13-194336.25" + process $proc$libresoc.v:194336$13278 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end - attribute \src "libresoc.v:191776.3-191777.27" - process $proc$libresoc.v:191776$13287 + attribute \src "libresoc.v:194357.3-194358.27" + process $proc$libresoc.v:194357$13273 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end - attribute \src "libresoc.v:191778.3-191786.6" - process $proc$libresoc.v:191778$13288 + attribute \src "libresoc.v:194359.3-194367.6" + process $proc$libresoc.v:194359$13274 assign { } { } assign { } { } - assign $0\q_int$next[3:0]$13289 $1\q_int$next[3:0]$13290 - attribute \src "libresoc.v:191779.5-191779.29" + assign $0\q_int$next[3:0]$13275 $1\q_int$next[3:0]$13276 + attribute \src "libresoc.v:194360.5-194360.29" switch \initial - attribute \src "libresoc.v:191779.9-191779.17" + attribute \src "libresoc.v:194360.9-194360.17" case 1'1 case end @@ -396179,56 +368826,56 @@ module \src_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[3:0]$13290 4'0000 + assign $1\q_int$next[3:0]$13276 4'0000 case - assign $1\q_int$next[3:0]$13290 \$5 + assign $1\q_int$next[3:0]$13276 \$5 end sync always - update \q_int$next $0\q_int$next[3:0]$13289 + update \q_int$next $0\q_int$next[3:0]$13275 end - connect \$9 $and$libresoc.v:191768$13279_Y - connect \$11 $or$libresoc.v:191769$13280_Y - connect \$13 $not$libresoc.v:191770$13281_Y - connect \$15 $or$libresoc.v:191771$13282_Y - connect \$1 $not$libresoc.v:191772$13283_Y - connect \$3 $and$libresoc.v:191773$13284_Y - connect \$5 $or$libresoc.v:191774$13285_Y - connect \$7 $not$libresoc.v:191775$13286_Y + connect \$9 $and$libresoc.v:194349$13265_Y + connect \$11 $or$libresoc.v:194350$13266_Y + connect \$13 $not$libresoc.v:194351$13267_Y + connect \$15 $or$libresoc.v:194352$13268_Y + connect \$1 $not$libresoc.v:194353$13269_Y + connect \$3 $and$libresoc.v:194354$13270_Y + connect \$5 $or$libresoc.v:194355$13271_Y + connect \$7 $not$libresoc.v:194356$13272_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:191794.1-191852.10" +attribute \src "libresoc.v:194375.1-194433.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.cr0.src_l" attribute \generator "nMigen" module \src_l$10 - attribute \src "libresoc.v:191795.7-191795.20" + attribute \src "libresoc.v:194376.7-194376.20" wire $0\initial[0:0] - attribute \src "libresoc.v:191840.3-191848.6" - wire width 6 $0\q_int$next[5:0]$13303 - attribute \src "libresoc.v:191838.3-191839.27" + attribute \src "libresoc.v:194421.3-194429.6" + wire width 6 $0\q_int$next[5:0]$13289 + attribute \src "libresoc.v:194419.3-194420.27" wire width 6 $0\q_int[5:0] - attribute \src "libresoc.v:191840.3-191848.6" - wire width 6 $1\q_int$next[5:0]$13304 - attribute \src "libresoc.v:191817.13-191817.26" + attribute \src "libresoc.v:194421.3-194429.6" + wire width 6 $1\q_int$next[5:0]$13290 + attribute \src "libresoc.v:194398.13-194398.26" wire width 6 $1\q_int[5:0] - attribute \src "libresoc.v:191830.17-191830.96" - wire width 6 $and$libresoc.v:191830$13293_Y - attribute \src "libresoc.v:191835.17-191835.96" - wire width 6 $and$libresoc.v:191835$13298_Y - attribute \src "libresoc.v:191832.18-191832.93" - wire width 6 $not$libresoc.v:191832$13295_Y - attribute \src "libresoc.v:191834.17-191834.92" - wire width 6 $not$libresoc.v:191834$13297_Y - attribute \src "libresoc.v:191837.17-191837.92" - wire width 6 $not$libresoc.v:191837$13300_Y - attribute \src "libresoc.v:191831.18-191831.98" - wire width 6 $or$libresoc.v:191831$13294_Y - attribute \src "libresoc.v:191833.18-191833.99" - wire width 6 $or$libresoc.v:191833$13296_Y - attribute \src "libresoc.v:191836.17-191836.97" - wire width 6 $or$libresoc.v:191836$13299_Y + attribute \src "libresoc.v:194411.17-194411.96" + wire width 6 $and$libresoc.v:194411$13279_Y + attribute \src "libresoc.v:194416.17-194416.96" + wire width 6 $and$libresoc.v:194416$13284_Y + attribute \src "libresoc.v:194413.18-194413.93" + wire width 6 $not$libresoc.v:194413$13281_Y + attribute \src "libresoc.v:194415.17-194415.92" + wire width 6 $not$libresoc.v:194415$13283_Y + attribute \src "libresoc.v:194418.17-194418.92" + wire width 6 $not$libresoc.v:194418$13286_Y + attribute \src "libresoc.v:194412.18-194412.98" + wire width 6 $or$libresoc.v:194412$13280_Y + attribute \src "libresoc.v:194414.18-194414.99" + wire width 6 $or$libresoc.v:194414$13282_Y + attribute \src "libresoc.v:194417.17-194417.97" + wire width 6 $or$libresoc.v:194417$13285_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -396245,11 +368892,11 @@ module \src_l$10 wire width 6 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 6 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:191795.7-191795.15" + attribute \src "libresoc.v:194376.7-194376.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 6 \q_int @@ -396266,7 +368913,7 @@ module \src_l$10 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 6 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:191830$13293 + cell $and $and$libresoc.v:194411$13279 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -396274,10 +368921,10 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:191830$13293_Y + connect \Y $and$libresoc.v:194411$13279_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:191835$13298 + cell $and $and$libresoc.v:194416$13284 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -396285,34 +368932,34 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:191835$13298_Y + connect \Y $and$libresoc.v:194416$13284_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:191832$13295 + cell $not $not$libresoc.v:194413$13281 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \q_src - connect \Y $not$libresoc.v:191832$13295_Y + connect \Y $not$libresoc.v:194413$13281_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:191834$13297 + cell $not $not$libresoc.v:194415$13283 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_src - connect \Y $not$libresoc.v:191834$13297_Y + connect \Y $not$libresoc.v:194415$13283_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:191837$13300 + cell $not $not$libresoc.v:194418$13286 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_src - connect \Y $not$libresoc.v:191837$13300_Y + connect \Y $not$libresoc.v:194418$13286_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:191831$13294 + cell $or $or$libresoc.v:194412$13280 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -396320,10 +368967,10 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:191831$13294_Y + connect \Y $or$libresoc.v:194412$13280_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:191833$13296 + cell $or $or$libresoc.v:194414$13282 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -396331,10 +368978,10 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:191833$13296_Y + connect \Y $or$libresoc.v:194414$13282_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:191836$13299 + cell $or $or$libresoc.v:194417$13285 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -396342,39 +368989,39 @@ module \src_l$10 parameter \Y_WIDTH 6 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:191836$13299_Y + connect \Y $or$libresoc.v:194417$13285_Y end - attribute \src "libresoc.v:191795.7-191795.20" - process $proc$libresoc.v:191795$13305 + attribute \src "libresoc.v:194376.7-194376.20" + process $proc$libresoc.v:194376$13291 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:191817.13-191817.26" - process $proc$libresoc.v:191817$13306 + attribute \src "libresoc.v:194398.13-194398.26" + process $proc$libresoc.v:194398$13292 assign { } { } assign $1\q_int[5:0] 6'000000 sync always sync init update \q_int $1\q_int[5:0] end - attribute \src "libresoc.v:191838.3-191839.27" - process $proc$libresoc.v:191838$13301 + attribute \src "libresoc.v:194419.3-194420.27" + process $proc$libresoc.v:194419$13287 assign { } { } assign $0\q_int[5:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[5:0] end - attribute \src "libresoc.v:191840.3-191848.6" - process $proc$libresoc.v:191840$13302 + attribute \src "libresoc.v:194421.3-194429.6" + process $proc$libresoc.v:194421$13288 assign { } { } assign { } { } - assign $0\q_int$next[5:0]$13303 $1\q_int$next[5:0]$13304 - attribute \src "libresoc.v:191841.5-191841.29" + assign $0\q_int$next[5:0]$13289 $1\q_int$next[5:0]$13290 + attribute \src "libresoc.v:194422.5-194422.29" switch \initial - attribute \src "libresoc.v:191841.9-191841.17" + attribute \src "libresoc.v:194422.9-194422.17" case 1'1 case end @@ -396383,56 +369030,56 @@ module \src_l$10 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[5:0]$13304 6'000000 + assign $1\q_int$next[5:0]$13290 6'000000 case - assign $1\q_int$next[5:0]$13304 \$5 + assign $1\q_int$next[5:0]$13290 \$5 end sync always - update \q_int$next $0\q_int$next[5:0]$13303 + update \q_int$next $0\q_int$next[5:0]$13289 end - connect \$9 $and$libresoc.v:191830$13293_Y - connect \$11 $or$libresoc.v:191831$13294_Y - connect \$13 $not$libresoc.v:191832$13295_Y - connect \$15 $or$libresoc.v:191833$13296_Y - connect \$1 $not$libresoc.v:191834$13297_Y - connect \$3 $and$libresoc.v:191835$13298_Y - connect \$5 $or$libresoc.v:191836$13299_Y - connect \$7 $not$libresoc.v:191837$13300_Y + connect \$9 $and$libresoc.v:194411$13279_Y + connect \$11 $or$libresoc.v:194412$13280_Y + connect \$13 $not$libresoc.v:194413$13281_Y + connect \$15 $or$libresoc.v:194414$13282_Y + connect \$1 $not$libresoc.v:194415$13283_Y + connect \$3 $and$libresoc.v:194416$13284_Y + connect \$5 $or$libresoc.v:194417$13285_Y + connect \$7 $not$libresoc.v:194418$13286_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:191856.1-191914.10" +attribute \src "libresoc.v:194437.1-194495.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.mul0.src_l" attribute \generator "nMigen" module \src_l$101 - attribute \src "libresoc.v:191857.7-191857.20" + attribute \src "libresoc.v:194438.7-194438.20" wire $0\initial[0:0] - attribute \src "libresoc.v:191902.3-191910.6" - wire width 3 $0\q_int$next[2:0]$13317 - attribute \src "libresoc.v:191900.3-191901.27" + attribute \src "libresoc.v:194483.3-194491.6" + wire width 3 $0\q_int$next[2:0]$13303 + attribute \src "libresoc.v:194481.3-194482.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:191902.3-191910.6" - wire width 3 $1\q_int$next[2:0]$13318 - attribute \src "libresoc.v:191879.13-191879.25" + attribute \src "libresoc.v:194483.3-194491.6" + wire width 3 $1\q_int$next[2:0]$13304 + attribute \src "libresoc.v:194460.13-194460.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:191892.17-191892.96" - wire width 3 $and$libresoc.v:191892$13307_Y - attribute \src "libresoc.v:191897.17-191897.96" - wire width 3 $and$libresoc.v:191897$13312_Y - attribute \src "libresoc.v:191894.18-191894.93" - wire width 3 $not$libresoc.v:191894$13309_Y - attribute \src "libresoc.v:191896.17-191896.92" - wire width 3 $not$libresoc.v:191896$13311_Y - attribute \src "libresoc.v:191899.17-191899.92" - wire width 3 $not$libresoc.v:191899$13314_Y - attribute \src "libresoc.v:191893.18-191893.98" - wire width 3 $or$libresoc.v:191893$13308_Y - attribute \src "libresoc.v:191895.18-191895.99" - wire width 3 $or$libresoc.v:191895$13310_Y - attribute \src "libresoc.v:191898.17-191898.97" - wire width 3 $or$libresoc.v:191898$13313_Y + attribute \src "libresoc.v:194473.17-194473.96" + wire width 3 $and$libresoc.v:194473$13293_Y + attribute \src "libresoc.v:194478.17-194478.96" + wire width 3 $and$libresoc.v:194478$13298_Y + attribute \src "libresoc.v:194475.18-194475.93" + wire width 3 $not$libresoc.v:194475$13295_Y + attribute \src "libresoc.v:194477.17-194477.92" + wire width 3 $not$libresoc.v:194477$13297_Y + attribute \src "libresoc.v:194480.17-194480.92" + wire width 3 $not$libresoc.v:194480$13300_Y + attribute \src "libresoc.v:194474.18-194474.98" + wire width 3 $or$libresoc.v:194474$13294_Y + attribute \src "libresoc.v:194476.18-194476.99" + wire width 3 $or$libresoc.v:194476$13296_Y + attribute \src "libresoc.v:194479.17-194479.97" + wire width 3 $or$libresoc.v:194479$13299_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -396449,11 +369096,11 @@ module \src_l$101 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:191857.7-191857.15" + attribute \src "libresoc.v:194438.7-194438.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -396470,7 +369117,7 @@ module \src_l$101 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:191892$13307 + cell $and $and$libresoc.v:194473$13293 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -396478,10 +369125,10 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:191892$13307_Y + connect \Y $and$libresoc.v:194473$13293_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:191897$13312 + cell $and $and$libresoc.v:194478$13298 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -396489,34 +369136,34 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:191897$13312_Y + connect \Y $and$libresoc.v:194478$13298_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:191894$13309 + cell $not $not$libresoc.v:194475$13295 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:191894$13309_Y + connect \Y $not$libresoc.v:194475$13295_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:191896$13311 + cell $not $not$libresoc.v:194477$13297 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:191896$13311_Y + connect \Y $not$libresoc.v:194477$13297_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:191899$13314 + cell $not $not$libresoc.v:194480$13300 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:191899$13314_Y + connect \Y $not$libresoc.v:194480$13300_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:191893$13308 + cell $or $or$libresoc.v:194474$13294 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -396524,10 +369171,10 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:191893$13308_Y + connect \Y $or$libresoc.v:194474$13294_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:191895$13310 + cell $or $or$libresoc.v:194476$13296 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -396535,10 +369182,10 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:191895$13310_Y + connect \Y $or$libresoc.v:194476$13296_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:191898$13313 + cell $or $or$libresoc.v:194479$13299 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -396546,39 +369193,39 @@ module \src_l$101 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:191898$13313_Y + connect \Y $or$libresoc.v:194479$13299_Y end - attribute \src "libresoc.v:191857.7-191857.20" - process $proc$libresoc.v:191857$13319 + attribute \src "libresoc.v:194438.7-194438.20" + process $proc$libresoc.v:194438$13305 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:191879.13-191879.25" - process $proc$libresoc.v:191879$13320 + attribute \src "libresoc.v:194460.13-194460.25" + process $proc$libresoc.v:194460$13306 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:191900.3-191901.27" - process $proc$libresoc.v:191900$13315 + attribute \src "libresoc.v:194481.3-194482.27" + process $proc$libresoc.v:194481$13301 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:191902.3-191910.6" - process $proc$libresoc.v:191902$13316 + attribute \src "libresoc.v:194483.3-194491.6" + process $proc$libresoc.v:194483$13302 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13317 $1\q_int$next[2:0]$13318 - attribute \src "libresoc.v:191903.5-191903.29" + assign $0\q_int$next[2:0]$13303 $1\q_int$next[2:0]$13304 + attribute \src "libresoc.v:194484.5-194484.29" switch \initial - attribute \src "libresoc.v:191903.9-191903.17" + attribute \src "libresoc.v:194484.9-194484.17" case 1'1 case end @@ -396587,56 +369234,56 @@ module \src_l$101 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$13318 3'000 + assign $1\q_int$next[2:0]$13304 3'000 case - assign $1\q_int$next[2:0]$13318 \$5 + assign $1\q_int$next[2:0]$13304 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$13317 + update \q_int$next $0\q_int$next[2:0]$13303 end - connect \$9 $and$libresoc.v:191892$13307_Y - connect \$11 $or$libresoc.v:191893$13308_Y - connect \$13 $not$libresoc.v:191894$13309_Y - connect \$15 $or$libresoc.v:191895$13310_Y - connect \$1 $not$libresoc.v:191896$13311_Y - connect \$3 $and$libresoc.v:191897$13312_Y - connect \$5 $or$libresoc.v:191898$13313_Y - connect \$7 $not$libresoc.v:191899$13314_Y + connect \$9 $and$libresoc.v:194473$13293_Y + connect \$11 $or$libresoc.v:194474$13294_Y + connect \$13 $not$libresoc.v:194475$13295_Y + connect \$15 $or$libresoc.v:194476$13296_Y + connect \$1 $not$libresoc.v:194477$13297_Y + connect \$3 $and$libresoc.v:194478$13298_Y + connect \$5 $or$libresoc.v:194479$13299_Y + connect \$7 $not$libresoc.v:194480$13300_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:191918.1-191976.10" +attribute \src "libresoc.v:194499.1-194557.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.shiftrot0.src_l" attribute \generator "nMigen" module \src_l$119 - attribute \src "libresoc.v:191919.7-191919.20" + attribute \src "libresoc.v:194500.7-194500.20" wire $0\initial[0:0] - attribute \src "libresoc.v:191964.3-191972.6" - wire width 5 $0\q_int$next[4:0]$13331 - attribute \src "libresoc.v:191962.3-191963.27" + attribute \src "libresoc.v:194545.3-194553.6" + wire width 5 $0\q_int$next[4:0]$13317 + attribute \src "libresoc.v:194543.3-194544.27" wire width 5 $0\q_int[4:0] - attribute \src "libresoc.v:191964.3-191972.6" - wire width 5 $1\q_int$next[4:0]$13332 - attribute \src "libresoc.v:191941.13-191941.26" + attribute \src "libresoc.v:194545.3-194553.6" + wire width 5 $1\q_int$next[4:0]$13318 + attribute \src "libresoc.v:194522.13-194522.26" wire width 5 $1\q_int[4:0] - attribute \src "libresoc.v:191954.17-191954.96" - wire width 5 $and$libresoc.v:191954$13321_Y - attribute \src "libresoc.v:191959.17-191959.96" - wire width 5 $and$libresoc.v:191959$13326_Y - attribute \src "libresoc.v:191956.18-191956.93" - wire width 5 $not$libresoc.v:191956$13323_Y - attribute \src "libresoc.v:191958.17-191958.92" - wire width 5 $not$libresoc.v:191958$13325_Y - attribute \src "libresoc.v:191961.17-191961.92" - wire width 5 $not$libresoc.v:191961$13328_Y - attribute \src "libresoc.v:191955.18-191955.98" - wire width 5 $or$libresoc.v:191955$13322_Y - attribute \src "libresoc.v:191957.18-191957.99" - wire width 5 $or$libresoc.v:191957$13324_Y - attribute \src "libresoc.v:191960.17-191960.97" - wire width 5 $or$libresoc.v:191960$13327_Y + attribute \src "libresoc.v:194535.17-194535.96" + wire width 5 $and$libresoc.v:194535$13307_Y + attribute \src "libresoc.v:194540.17-194540.96" + wire width 5 $and$libresoc.v:194540$13312_Y + attribute \src "libresoc.v:194537.18-194537.93" + wire width 5 $not$libresoc.v:194537$13309_Y + attribute \src "libresoc.v:194539.17-194539.92" + wire width 5 $not$libresoc.v:194539$13311_Y + attribute \src "libresoc.v:194542.17-194542.92" + wire width 5 $not$libresoc.v:194542$13314_Y + attribute \src "libresoc.v:194536.18-194536.98" + wire width 5 $or$libresoc.v:194536$13308_Y + attribute \src "libresoc.v:194538.18-194538.99" + wire width 5 $or$libresoc.v:194538$13310_Y + attribute \src "libresoc.v:194541.17-194541.97" + wire width 5 $or$libresoc.v:194541$13313_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 5 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -396653,11 +369300,11 @@ module \src_l$119 wire width 5 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 5 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:191919.7-191919.15" + attribute \src "libresoc.v:194500.7-194500.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 5 \q_int @@ -396674,7 +369321,7 @@ module \src_l$119 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 5 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:191954$13321 + cell $and $and$libresoc.v:194535$13307 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -396682,10 +369329,10 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:191954$13321_Y + connect \Y $and$libresoc.v:194535$13307_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:191959$13326 + cell $and $and$libresoc.v:194540$13312 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -396693,34 +369340,34 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:191959$13326_Y + connect \Y $and$libresoc.v:194540$13312_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:191956$13323 + cell $not $not$libresoc.v:194537$13309 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \q_src - connect \Y $not$libresoc.v:191956$13323_Y + connect \Y $not$libresoc.v:194537$13309_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:191958$13325 + cell $not $not$libresoc.v:194539$13311 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_src - connect \Y $not$libresoc.v:191958$13325_Y + connect \Y $not$libresoc.v:194539$13311_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:191961$13328 + cell $not $not$libresoc.v:194542$13314 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \r_src - connect \Y $not$libresoc.v:191961$13328_Y + connect \Y $not$libresoc.v:194542$13314_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:191955$13322 + cell $or $or$libresoc.v:194536$13308 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -396728,10 +369375,10 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:191955$13322_Y + connect \Y $or$libresoc.v:194536$13308_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:191957$13324 + cell $or $or$libresoc.v:194538$13310 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -396739,10 +369386,10 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:191957$13324_Y + connect \Y $or$libresoc.v:194538$13310_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:191960$13327 + cell $or $or$libresoc.v:194541$13313 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -396750,39 +369397,39 @@ module \src_l$119 parameter \Y_WIDTH 5 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:191960$13327_Y + connect \Y $or$libresoc.v:194541$13313_Y end - attribute \src "libresoc.v:191919.7-191919.20" - process $proc$libresoc.v:191919$13333 + attribute \src "libresoc.v:194500.7-194500.20" + process $proc$libresoc.v:194500$13319 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:191941.13-191941.26" - process $proc$libresoc.v:191941$13334 + attribute \src "libresoc.v:194522.13-194522.26" + process $proc$libresoc.v:194522$13320 assign { } { } assign $1\q_int[4:0] 5'00000 sync always sync init update \q_int $1\q_int[4:0] end - attribute \src "libresoc.v:191962.3-191963.27" - process $proc$libresoc.v:191962$13329 + attribute \src "libresoc.v:194543.3-194544.27" + process $proc$libresoc.v:194543$13315 assign { } { } assign $0\q_int[4:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[4:0] end - attribute \src "libresoc.v:191964.3-191972.6" - process $proc$libresoc.v:191964$13330 + attribute \src "libresoc.v:194545.3-194553.6" + process $proc$libresoc.v:194545$13316 assign { } { } assign { } { } - assign $0\q_int$next[4:0]$13331 $1\q_int$next[4:0]$13332 - attribute \src "libresoc.v:191965.5-191965.29" + assign $0\q_int$next[4:0]$13317 $1\q_int$next[4:0]$13318 + attribute \src "libresoc.v:194546.5-194546.29" switch \initial - attribute \src "libresoc.v:191965.9-191965.17" + attribute \src "libresoc.v:194546.9-194546.17" case 1'1 case end @@ -396791,56 +369438,56 @@ module \src_l$119 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[4:0]$13332 5'00000 + assign $1\q_int$next[4:0]$13318 5'00000 case - assign $1\q_int$next[4:0]$13332 \$5 + assign $1\q_int$next[4:0]$13318 \$5 end sync always - update \q_int$next $0\q_int$next[4:0]$13331 + update \q_int$next $0\q_int$next[4:0]$13317 end - connect \$9 $and$libresoc.v:191954$13321_Y - connect \$11 $or$libresoc.v:191955$13322_Y - connect \$13 $not$libresoc.v:191956$13323_Y - connect \$15 $or$libresoc.v:191957$13324_Y - connect \$1 $not$libresoc.v:191958$13325_Y - connect \$3 $and$libresoc.v:191959$13326_Y - connect \$5 $or$libresoc.v:191960$13327_Y - connect \$7 $not$libresoc.v:191961$13328_Y + connect \$9 $and$libresoc.v:194535$13307_Y + connect \$11 $or$libresoc.v:194536$13308_Y + connect \$13 $not$libresoc.v:194537$13309_Y + connect \$15 $or$libresoc.v:194538$13310_Y + connect \$1 $not$libresoc.v:194539$13311_Y + connect \$3 $and$libresoc.v:194540$13312_Y + connect \$5 $or$libresoc.v:194541$13313_Y + connect \$7 $not$libresoc.v:194542$13314_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:191980.1-192038.10" +attribute \src "libresoc.v:194561.1-194619.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.src_l" attribute \generator "nMigen" module \src_l$127 - attribute \src "libresoc.v:191981.7-191981.20" + attribute \src "libresoc.v:194562.7-194562.20" wire $0\initial[0:0] - attribute \src "libresoc.v:192026.3-192034.6" - wire width 3 $0\q_int$next[2:0]$13345 - attribute \src "libresoc.v:192024.3-192025.27" + attribute \src "libresoc.v:194607.3-194615.6" + wire width 3 $0\q_int$next[2:0]$13331 + attribute \src "libresoc.v:194605.3-194606.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:192026.3-192034.6" - wire width 3 $1\q_int$next[2:0]$13346 - attribute \src "libresoc.v:192003.13-192003.25" + attribute \src "libresoc.v:194607.3-194615.6" + wire width 3 $1\q_int$next[2:0]$13332 + attribute \src "libresoc.v:194584.13-194584.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:192016.17-192016.96" - wire width 3 $and$libresoc.v:192016$13335_Y - attribute \src "libresoc.v:192021.17-192021.96" - wire width 3 $and$libresoc.v:192021$13340_Y - attribute \src "libresoc.v:192018.18-192018.93" - wire width 3 $not$libresoc.v:192018$13337_Y - attribute \src "libresoc.v:192020.17-192020.92" - wire width 3 $not$libresoc.v:192020$13339_Y - attribute \src "libresoc.v:192023.17-192023.92" - wire width 3 $not$libresoc.v:192023$13342_Y - attribute \src "libresoc.v:192017.18-192017.98" - wire width 3 $or$libresoc.v:192017$13336_Y - attribute \src "libresoc.v:192019.18-192019.99" - wire width 3 $or$libresoc.v:192019$13338_Y - attribute \src "libresoc.v:192022.17-192022.97" - wire width 3 $or$libresoc.v:192022$13341_Y + attribute \src "libresoc.v:194597.17-194597.96" + wire width 3 $and$libresoc.v:194597$13321_Y + attribute \src "libresoc.v:194602.17-194602.96" + wire width 3 $and$libresoc.v:194602$13326_Y + attribute \src "libresoc.v:194599.18-194599.93" + wire width 3 $not$libresoc.v:194599$13323_Y + attribute \src "libresoc.v:194601.17-194601.92" + wire width 3 $not$libresoc.v:194601$13325_Y + attribute \src "libresoc.v:194604.17-194604.92" + wire width 3 $not$libresoc.v:194604$13328_Y + attribute \src "libresoc.v:194598.18-194598.98" + wire width 3 $or$libresoc.v:194598$13322_Y + attribute \src "libresoc.v:194600.18-194600.99" + wire width 3 $or$libresoc.v:194600$13324_Y + attribute \src "libresoc.v:194603.17-194603.97" + wire width 3 $or$libresoc.v:194603$13327_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -396857,11 +369504,11 @@ module \src_l$127 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:191981.7-191981.15" + attribute \src "libresoc.v:194562.7-194562.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -396878,7 +369525,7 @@ module \src_l$127 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:192016$13335 + cell $and $and$libresoc.v:194597$13321 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -396886,10 +369533,10 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:192016$13335_Y + connect \Y $and$libresoc.v:194597$13321_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:192021$13340 + cell $and $and$libresoc.v:194602$13326 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -396897,34 +369544,34 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:192021$13340_Y + connect \Y $and$libresoc.v:194602$13326_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:192018$13337 + cell $not $not$libresoc.v:194599$13323 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:192018$13337_Y + connect \Y $not$libresoc.v:194599$13323_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:192020$13339 + cell $not $not$libresoc.v:194601$13325 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:192020$13339_Y + connect \Y $not$libresoc.v:194601$13325_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:192023$13342 + cell $not $not$libresoc.v:194604$13328 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:192023$13342_Y + connect \Y $not$libresoc.v:194604$13328_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:192017$13336 + cell $or $or$libresoc.v:194598$13322 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -396932,10 +369579,10 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:192017$13336_Y + connect \Y $or$libresoc.v:194598$13322_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:192019$13338 + cell $or $or$libresoc.v:194600$13324 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -396943,10 +369590,10 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:192019$13338_Y + connect \Y $or$libresoc.v:194600$13324_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:192022$13341 + cell $or $or$libresoc.v:194603$13327 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -396954,39 +369601,39 @@ module \src_l$127 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:192022$13341_Y + connect \Y $or$libresoc.v:194603$13327_Y end - attribute \src "libresoc.v:191981.7-191981.20" - process $proc$libresoc.v:191981$13347 + attribute \src "libresoc.v:194562.7-194562.20" + process $proc$libresoc.v:194562$13333 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:192003.13-192003.25" - process $proc$libresoc.v:192003$13348 + attribute \src "libresoc.v:194584.13-194584.25" + process $proc$libresoc.v:194584$13334 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:192024.3-192025.27" - process $proc$libresoc.v:192024$13343 + attribute \src "libresoc.v:194605.3-194606.27" + process $proc$libresoc.v:194605$13329 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:192026.3-192034.6" - process $proc$libresoc.v:192026$13344 + attribute \src "libresoc.v:194607.3-194615.6" + process $proc$libresoc.v:194607$13330 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13345 $1\q_int$next[2:0]$13346 - attribute \src "libresoc.v:192027.5-192027.29" + assign $0\q_int$next[2:0]$13331 $1\q_int$next[2:0]$13332 + attribute \src "libresoc.v:194608.5-194608.29" switch \initial - attribute \src "libresoc.v:192027.9-192027.17" + attribute \src "libresoc.v:194608.9-194608.17" case 1'1 case end @@ -396995,56 +369642,56 @@ module \src_l$127 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$13346 3'000 + assign $1\q_int$next[2:0]$13332 3'000 case - assign $1\q_int$next[2:0]$13346 \$5 + assign $1\q_int$next[2:0]$13332 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$13345 + update \q_int$next $0\q_int$next[2:0]$13331 end - connect \$9 $and$libresoc.v:192016$13335_Y - connect \$11 $or$libresoc.v:192017$13336_Y - connect \$13 $not$libresoc.v:192018$13337_Y - connect \$15 $or$libresoc.v:192019$13338_Y - connect \$1 $not$libresoc.v:192020$13339_Y - connect \$3 $and$libresoc.v:192021$13340_Y - connect \$5 $or$libresoc.v:192022$13341_Y - connect \$7 $not$libresoc.v:192023$13342_Y + connect \$9 $and$libresoc.v:194597$13321_Y + connect \$11 $or$libresoc.v:194598$13322_Y + connect \$13 $not$libresoc.v:194599$13323_Y + connect \$15 $or$libresoc.v:194600$13324_Y + connect \$1 $not$libresoc.v:194601$13325_Y + connect \$3 $and$libresoc.v:194602$13326_Y + connect \$5 $or$libresoc.v:194603$13327_Y + connect \$7 $not$libresoc.v:194604$13328_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:192042.1-192100.10" +attribute \src "libresoc.v:194623.1-194681.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.branch0.src_l" attribute \generator "nMigen" module \src_l$23 - attribute \src "libresoc.v:192043.7-192043.20" + attribute \src "libresoc.v:194624.7-194624.20" wire $0\initial[0:0] - attribute \src "libresoc.v:192088.3-192096.6" - wire width 3 $0\q_int$next[2:0]$13359 - attribute \src "libresoc.v:192086.3-192087.27" + attribute \src "libresoc.v:194669.3-194677.6" + wire width 3 $0\q_int$next[2:0]$13345 + attribute \src "libresoc.v:194667.3-194668.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:192088.3-192096.6" - wire width 3 $1\q_int$next[2:0]$13360 - attribute \src "libresoc.v:192065.13-192065.25" + attribute \src "libresoc.v:194669.3-194677.6" + wire width 3 $1\q_int$next[2:0]$13346 + attribute \src "libresoc.v:194646.13-194646.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:192078.17-192078.96" - wire width 3 $and$libresoc.v:192078$13349_Y - attribute \src "libresoc.v:192083.17-192083.96" - wire width 3 $and$libresoc.v:192083$13354_Y - attribute \src "libresoc.v:192080.18-192080.93" - wire width 3 $not$libresoc.v:192080$13351_Y - attribute \src "libresoc.v:192082.17-192082.92" - wire width 3 $not$libresoc.v:192082$13353_Y - attribute \src "libresoc.v:192085.17-192085.92" - wire width 3 $not$libresoc.v:192085$13356_Y - attribute \src "libresoc.v:192079.18-192079.98" - wire width 3 $or$libresoc.v:192079$13350_Y - attribute \src "libresoc.v:192081.18-192081.99" - wire width 3 $or$libresoc.v:192081$13352_Y - attribute \src "libresoc.v:192084.17-192084.97" - wire width 3 $or$libresoc.v:192084$13355_Y + attribute \src "libresoc.v:194659.17-194659.96" + wire width 3 $and$libresoc.v:194659$13335_Y + attribute \src "libresoc.v:194664.17-194664.96" + wire width 3 $and$libresoc.v:194664$13340_Y + attribute \src "libresoc.v:194661.18-194661.93" + wire width 3 $not$libresoc.v:194661$13337_Y + attribute \src "libresoc.v:194663.17-194663.92" + wire width 3 $not$libresoc.v:194663$13339_Y + attribute \src "libresoc.v:194666.17-194666.92" + wire width 3 $not$libresoc.v:194666$13342_Y + attribute \src "libresoc.v:194660.18-194660.98" + wire width 3 $or$libresoc.v:194660$13336_Y + attribute \src "libresoc.v:194662.18-194662.99" + wire width 3 $or$libresoc.v:194662$13338_Y + attribute \src "libresoc.v:194665.17-194665.97" + wire width 3 $or$libresoc.v:194665$13341_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -397061,11 +369708,11 @@ module \src_l$23 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:192043.7-192043.15" + attribute \src "libresoc.v:194624.7-194624.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -397082,7 +369729,7 @@ module \src_l$23 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:192078$13349 + cell $and $and$libresoc.v:194659$13335 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397090,10 +369737,10 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:192078$13349_Y + connect \Y $and$libresoc.v:194659$13335_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:192083$13354 + cell $and $and$libresoc.v:194664$13340 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397101,34 +369748,34 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:192083$13354_Y + connect \Y $and$libresoc.v:194664$13340_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:192080$13351 + cell $not $not$libresoc.v:194661$13337 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:192080$13351_Y + connect \Y $not$libresoc.v:194661$13337_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:192082$13353 + cell $not $not$libresoc.v:194663$13339 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:192082$13353_Y + connect \Y $not$libresoc.v:194663$13339_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:192085$13356 + cell $not $not$libresoc.v:194666$13342 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:192085$13356_Y + connect \Y $not$libresoc.v:194666$13342_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:192079$13350 + cell $or $or$libresoc.v:194660$13336 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397136,10 +369783,10 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:192079$13350_Y + connect \Y $or$libresoc.v:194660$13336_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:192081$13352 + cell $or $or$libresoc.v:194662$13338 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397147,10 +369794,10 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:192081$13352_Y + connect \Y $or$libresoc.v:194662$13338_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:192084$13355 + cell $or $or$libresoc.v:194665$13341 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397158,39 +369805,39 @@ module \src_l$23 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:192084$13355_Y + connect \Y $or$libresoc.v:194665$13341_Y end - attribute \src "libresoc.v:192043.7-192043.20" - process $proc$libresoc.v:192043$13361 + attribute \src "libresoc.v:194624.7-194624.20" + process $proc$libresoc.v:194624$13347 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:192065.13-192065.25" - process $proc$libresoc.v:192065$13362 + attribute \src "libresoc.v:194646.13-194646.25" + process $proc$libresoc.v:194646$13348 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:192086.3-192087.27" - process $proc$libresoc.v:192086$13357 + attribute \src "libresoc.v:194667.3-194668.27" + process $proc$libresoc.v:194667$13343 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:192088.3-192096.6" - process $proc$libresoc.v:192088$13358 + attribute \src "libresoc.v:194669.3-194677.6" + process $proc$libresoc.v:194669$13344 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13359 $1\q_int$next[2:0]$13360 - attribute \src "libresoc.v:192089.5-192089.29" + assign $0\q_int$next[2:0]$13345 $1\q_int$next[2:0]$13346 + attribute \src "libresoc.v:194670.5-194670.29" switch \initial - attribute \src "libresoc.v:192089.9-192089.17" + attribute \src "libresoc.v:194670.9-194670.17" case 1'1 case end @@ -397199,56 +369846,56 @@ module \src_l$23 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$13360 3'000 + assign $1\q_int$next[2:0]$13346 3'000 case - assign $1\q_int$next[2:0]$13360 \$5 + assign $1\q_int$next[2:0]$13346 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$13359 + update \q_int$next $0\q_int$next[2:0]$13345 end - connect \$9 $and$libresoc.v:192078$13349_Y - connect \$11 $or$libresoc.v:192079$13350_Y - connect \$13 $not$libresoc.v:192080$13351_Y - connect \$15 $or$libresoc.v:192081$13352_Y - connect \$1 $not$libresoc.v:192082$13353_Y - connect \$3 $and$libresoc.v:192083$13354_Y - connect \$5 $or$libresoc.v:192084$13355_Y - connect \$7 $not$libresoc.v:192085$13356_Y + connect \$9 $and$libresoc.v:194659$13335_Y + connect \$11 $or$libresoc.v:194660$13336_Y + connect \$13 $not$libresoc.v:194661$13337_Y + connect \$15 $or$libresoc.v:194662$13338_Y + connect \$1 $not$libresoc.v:194663$13339_Y + connect \$3 $and$libresoc.v:194664$13340_Y + connect \$5 $or$libresoc.v:194665$13341_Y + connect \$7 $not$libresoc.v:194666$13342_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:192104.1-192162.10" +attribute \src "libresoc.v:194685.1-194743.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0.src_l" attribute \generator "nMigen" module \src_l$39 - attribute \src "libresoc.v:192105.7-192105.20" + attribute \src "libresoc.v:194686.7-194686.20" wire $0\initial[0:0] - attribute \src "libresoc.v:192150.3-192158.6" - wire width 4 $0\q_int$next[3:0]$13373 - attribute \src "libresoc.v:192148.3-192149.27" + attribute \src "libresoc.v:194731.3-194739.6" + wire width 4 $0\q_int$next[3:0]$13359 + attribute \src "libresoc.v:194729.3-194730.27" wire width 4 $0\q_int[3:0] - attribute \src "libresoc.v:192150.3-192158.6" - wire width 4 $1\q_int$next[3:0]$13374 - attribute \src "libresoc.v:192127.13-192127.25" + attribute \src "libresoc.v:194731.3-194739.6" + wire width 4 $1\q_int$next[3:0]$13360 + attribute \src "libresoc.v:194708.13-194708.25" wire width 4 $1\q_int[3:0] - attribute \src "libresoc.v:192140.17-192140.96" - wire width 4 $and$libresoc.v:192140$13363_Y - attribute \src "libresoc.v:192145.17-192145.96" - wire width 4 $and$libresoc.v:192145$13368_Y - attribute \src "libresoc.v:192142.18-192142.93" - wire width 4 $not$libresoc.v:192142$13365_Y - attribute \src "libresoc.v:192144.17-192144.92" - wire width 4 $not$libresoc.v:192144$13367_Y - attribute \src "libresoc.v:192147.17-192147.92" - wire width 4 $not$libresoc.v:192147$13370_Y - attribute \src "libresoc.v:192141.18-192141.98" - wire width 4 $or$libresoc.v:192141$13364_Y - attribute \src "libresoc.v:192143.18-192143.99" - wire width 4 $or$libresoc.v:192143$13366_Y - attribute \src "libresoc.v:192146.17-192146.97" - wire width 4 $or$libresoc.v:192146$13369_Y + attribute \src "libresoc.v:194721.17-194721.96" + wire width 4 $and$libresoc.v:194721$13349_Y + attribute \src "libresoc.v:194726.17-194726.96" + wire width 4 $and$libresoc.v:194726$13354_Y + attribute \src "libresoc.v:194723.18-194723.93" + wire width 4 $not$libresoc.v:194723$13351_Y + attribute \src "libresoc.v:194725.17-194725.92" + wire width 4 $not$libresoc.v:194725$13353_Y + attribute \src "libresoc.v:194728.17-194728.92" + wire width 4 $not$libresoc.v:194728$13356_Y + attribute \src "libresoc.v:194722.18-194722.98" + wire width 4 $or$libresoc.v:194722$13350_Y + attribute \src "libresoc.v:194724.18-194724.99" + wire width 4 $or$libresoc.v:194724$13352_Y + attribute \src "libresoc.v:194727.17-194727.97" + wire width 4 $or$libresoc.v:194727$13355_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -397265,11 +369912,11 @@ module \src_l$39 wire width 4 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 4 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:192105.7-192105.15" + attribute \src "libresoc.v:194686.7-194686.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 4 \q_int @@ -397286,7 +369933,7 @@ module \src_l$39 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 4 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:192140$13363 + cell $and $and$libresoc.v:194721$13349 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -397294,10 +369941,10 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:192140$13363_Y + connect \Y $and$libresoc.v:194721$13349_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:192145$13368 + cell $and $and$libresoc.v:194726$13354 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -397305,34 +369952,34 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:192145$13368_Y + connect \Y $and$libresoc.v:194726$13354_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:192142$13365 + cell $not $not$libresoc.v:194723$13351 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \q_src - connect \Y $not$libresoc.v:192142$13365_Y + connect \Y $not$libresoc.v:194723$13351_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:192144$13367 + cell $not $not$libresoc.v:194725$13353 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src - connect \Y $not$libresoc.v:192144$13367_Y + connect \Y $not$libresoc.v:194725$13353_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:192147$13370 + cell $not $not$libresoc.v:194728$13356 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \r_src - connect \Y $not$libresoc.v:192147$13370_Y + connect \Y $not$libresoc.v:194728$13356_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:192141$13364 + cell $or $or$libresoc.v:194722$13350 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -397340,10 +369987,10 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:192141$13364_Y + connect \Y $or$libresoc.v:194722$13350_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:192143$13366 + cell $or $or$libresoc.v:194724$13352 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -397351,10 +369998,10 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:192143$13366_Y + connect \Y $or$libresoc.v:194724$13352_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:192146$13369 + cell $or $or$libresoc.v:194727$13355 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -397362,39 +370009,39 @@ module \src_l$39 parameter \Y_WIDTH 4 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:192146$13369_Y + connect \Y $or$libresoc.v:194727$13355_Y end - attribute \src "libresoc.v:192105.7-192105.20" - process $proc$libresoc.v:192105$13375 + attribute \src "libresoc.v:194686.7-194686.20" + process $proc$libresoc.v:194686$13361 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:192127.13-192127.25" - process $proc$libresoc.v:192127$13376 + attribute \src "libresoc.v:194708.13-194708.25" + process $proc$libresoc.v:194708$13362 assign { } { } assign $1\q_int[3:0] 4'0000 sync always sync init update \q_int $1\q_int[3:0] end - attribute \src "libresoc.v:192148.3-192149.27" - process $proc$libresoc.v:192148$13371 + attribute \src "libresoc.v:194729.3-194730.27" + process $proc$libresoc.v:194729$13357 assign { } { } assign $0\q_int[3:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[3:0] end - attribute \src "libresoc.v:192150.3-192158.6" - process $proc$libresoc.v:192150$13372 + attribute \src "libresoc.v:194731.3-194739.6" + process $proc$libresoc.v:194731$13358 assign { } { } assign { } { } - assign $0\q_int$next[3:0]$13373 $1\q_int$next[3:0]$13374 - attribute \src "libresoc.v:192151.5-192151.29" + assign $0\q_int$next[3:0]$13359 $1\q_int$next[3:0]$13360 + attribute \src "libresoc.v:194732.5-194732.29" switch \initial - attribute \src "libresoc.v:192151.9-192151.17" + attribute \src "libresoc.v:194732.9-194732.17" case 1'1 case end @@ -397403,56 +370050,56 @@ module \src_l$39 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[3:0]$13374 4'0000 + assign $1\q_int$next[3:0]$13360 4'0000 case - assign $1\q_int$next[3:0]$13374 \$5 + assign $1\q_int$next[3:0]$13360 \$5 end sync always - update \q_int$next $0\q_int$next[3:0]$13373 + update \q_int$next $0\q_int$next[3:0]$13359 end - connect \$9 $and$libresoc.v:192140$13363_Y - connect \$11 $or$libresoc.v:192141$13364_Y - connect \$13 $not$libresoc.v:192142$13365_Y - connect \$15 $or$libresoc.v:192143$13366_Y - connect \$1 $not$libresoc.v:192144$13367_Y - connect \$3 $and$libresoc.v:192145$13368_Y - connect \$5 $or$libresoc.v:192146$13369_Y - connect \$7 $not$libresoc.v:192147$13370_Y + connect \$9 $and$libresoc.v:194721$13349_Y + connect \$11 $or$libresoc.v:194722$13350_Y + connect \$13 $not$libresoc.v:194723$13351_Y + connect \$15 $or$libresoc.v:194724$13352_Y + connect \$1 $not$libresoc.v:194725$13353_Y + connect \$3 $and$libresoc.v:194726$13354_Y + connect \$5 $or$libresoc.v:194727$13355_Y + connect \$7 $not$libresoc.v:194728$13356_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:192166.1-192224.10" +attribute \src "libresoc.v:194747.1-194805.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.logical0.src_l" attribute \generator "nMigen" module \src_l$55 - attribute \src "libresoc.v:192167.7-192167.20" + attribute \src "libresoc.v:194748.7-194748.20" wire $0\initial[0:0] - attribute \src "libresoc.v:192212.3-192220.6" - wire width 3 $0\q_int$next[2:0]$13387 - attribute \src "libresoc.v:192210.3-192211.27" + attribute \src "libresoc.v:194793.3-194801.6" + wire width 3 $0\q_int$next[2:0]$13373 + attribute \src "libresoc.v:194791.3-194792.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:192212.3-192220.6" - wire width 3 $1\q_int$next[2:0]$13388 - attribute \src "libresoc.v:192189.13-192189.25" + attribute \src "libresoc.v:194793.3-194801.6" + wire width 3 $1\q_int$next[2:0]$13374 + attribute \src "libresoc.v:194770.13-194770.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:192202.17-192202.96" - wire width 3 $and$libresoc.v:192202$13377_Y - attribute \src "libresoc.v:192207.17-192207.96" - wire width 3 $and$libresoc.v:192207$13382_Y - attribute \src "libresoc.v:192204.18-192204.93" - wire width 3 $not$libresoc.v:192204$13379_Y - attribute \src "libresoc.v:192206.17-192206.92" - wire width 3 $not$libresoc.v:192206$13381_Y - attribute \src "libresoc.v:192209.17-192209.92" - wire width 3 $not$libresoc.v:192209$13384_Y - attribute \src "libresoc.v:192203.18-192203.98" - wire width 3 $or$libresoc.v:192203$13378_Y - attribute \src "libresoc.v:192205.18-192205.99" - wire width 3 $or$libresoc.v:192205$13380_Y - attribute \src "libresoc.v:192208.17-192208.97" - wire width 3 $or$libresoc.v:192208$13383_Y + attribute \src "libresoc.v:194783.17-194783.96" + wire width 3 $and$libresoc.v:194783$13363_Y + attribute \src "libresoc.v:194788.17-194788.96" + wire width 3 $and$libresoc.v:194788$13368_Y + attribute \src "libresoc.v:194785.18-194785.93" + wire width 3 $not$libresoc.v:194785$13365_Y + attribute \src "libresoc.v:194787.17-194787.92" + wire width 3 $not$libresoc.v:194787$13367_Y + attribute \src "libresoc.v:194790.17-194790.92" + wire width 3 $not$libresoc.v:194790$13370_Y + attribute \src "libresoc.v:194784.18-194784.98" + wire width 3 $or$libresoc.v:194784$13364_Y + attribute \src "libresoc.v:194786.18-194786.99" + wire width 3 $or$libresoc.v:194786$13366_Y + attribute \src "libresoc.v:194789.17-194789.97" + wire width 3 $or$libresoc.v:194789$13369_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -397469,11 +370116,11 @@ module \src_l$55 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:192167.7-192167.15" + attribute \src "libresoc.v:194748.7-194748.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -397490,7 +370137,7 @@ module \src_l$55 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:192202$13377 + cell $and $and$libresoc.v:194783$13363 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397498,10 +370145,10 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:192202$13377_Y + connect \Y $and$libresoc.v:194783$13363_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:192207$13382 + cell $and $and$libresoc.v:194788$13368 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397509,34 +370156,34 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:192207$13382_Y + connect \Y $and$libresoc.v:194788$13368_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:192204$13379 + cell $not $not$libresoc.v:194785$13365 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:192204$13379_Y + connect \Y $not$libresoc.v:194785$13365_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:192206$13381 + cell $not $not$libresoc.v:194787$13367 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:192206$13381_Y + connect \Y $not$libresoc.v:194787$13367_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:192209$13384 + cell $not $not$libresoc.v:194790$13370 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:192209$13384_Y + connect \Y $not$libresoc.v:194790$13370_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:192203$13378 + cell $or $or$libresoc.v:194784$13364 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397544,10 +370191,10 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:192203$13378_Y + connect \Y $or$libresoc.v:194784$13364_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:192205$13380 + cell $or $or$libresoc.v:194786$13366 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397555,10 +370202,10 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:192205$13380_Y + connect \Y $or$libresoc.v:194786$13366_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:192208$13383 + cell $or $or$libresoc.v:194789$13369 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397566,39 +370213,39 @@ module \src_l$55 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:192208$13383_Y + connect \Y $or$libresoc.v:194789$13369_Y end - attribute \src "libresoc.v:192167.7-192167.20" - process $proc$libresoc.v:192167$13389 + attribute \src "libresoc.v:194748.7-194748.20" + process $proc$libresoc.v:194748$13375 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:192189.13-192189.25" - process $proc$libresoc.v:192189$13390 + attribute \src "libresoc.v:194770.13-194770.25" + process $proc$libresoc.v:194770$13376 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:192210.3-192211.27" - process $proc$libresoc.v:192210$13385 + attribute \src "libresoc.v:194791.3-194792.27" + process $proc$libresoc.v:194791$13371 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:192212.3-192220.6" - process $proc$libresoc.v:192212$13386 + attribute \src "libresoc.v:194793.3-194801.6" + process $proc$libresoc.v:194793$13372 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13387 $1\q_int$next[2:0]$13388 - attribute \src "libresoc.v:192213.5-192213.29" + assign $0\q_int$next[2:0]$13373 $1\q_int$next[2:0]$13374 + attribute \src "libresoc.v:194794.5-194794.29" switch \initial - attribute \src "libresoc.v:192213.9-192213.17" + attribute \src "libresoc.v:194794.9-194794.17" case 1'1 case end @@ -397607,56 +370254,56 @@ module \src_l$55 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$13388 3'000 + assign $1\q_int$next[2:0]$13374 3'000 case - assign $1\q_int$next[2:0]$13388 \$5 + assign $1\q_int$next[2:0]$13374 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$13387 + update \q_int$next $0\q_int$next[2:0]$13373 end - connect \$9 $and$libresoc.v:192202$13377_Y - connect \$11 $or$libresoc.v:192203$13378_Y - connect \$13 $not$libresoc.v:192204$13379_Y - connect \$15 $or$libresoc.v:192205$13380_Y - connect \$1 $not$libresoc.v:192206$13381_Y - connect \$3 $and$libresoc.v:192207$13382_Y - connect \$5 $or$libresoc.v:192208$13383_Y - connect \$7 $not$libresoc.v:192209$13384_Y + connect \$9 $and$libresoc.v:194783$13363_Y + connect \$11 $or$libresoc.v:194784$13364_Y + connect \$13 $not$libresoc.v:194785$13365_Y + connect \$15 $or$libresoc.v:194786$13366_Y + connect \$1 $not$libresoc.v:194787$13367_Y + connect \$3 $and$libresoc.v:194788$13368_Y + connect \$5 $or$libresoc.v:194789$13369_Y + connect \$7 $not$libresoc.v:194790$13370_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:192228.1-192286.10" +attribute \src "libresoc.v:194809.1-194867.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.spr0.src_l" attribute \generator "nMigen" module \src_l$67 - attribute \src "libresoc.v:192229.7-192229.20" + attribute \src "libresoc.v:194810.7-194810.20" wire $0\initial[0:0] - attribute \src "libresoc.v:192274.3-192282.6" - wire width 6 $0\q_int$next[5:0]$13401 - attribute \src "libresoc.v:192272.3-192273.27" + attribute \src "libresoc.v:194855.3-194863.6" + wire width 6 $0\q_int$next[5:0]$13387 + attribute \src "libresoc.v:194853.3-194854.27" wire width 6 $0\q_int[5:0] - attribute \src "libresoc.v:192274.3-192282.6" - wire width 6 $1\q_int$next[5:0]$13402 - attribute \src "libresoc.v:192251.13-192251.26" + attribute \src "libresoc.v:194855.3-194863.6" + wire width 6 $1\q_int$next[5:0]$13388 + attribute \src "libresoc.v:194832.13-194832.26" wire width 6 $1\q_int[5:0] - attribute \src "libresoc.v:192264.17-192264.96" - wire width 6 $and$libresoc.v:192264$13391_Y - attribute \src "libresoc.v:192269.17-192269.96" - wire width 6 $and$libresoc.v:192269$13396_Y - attribute \src "libresoc.v:192266.18-192266.93" - wire width 6 $not$libresoc.v:192266$13393_Y - attribute \src "libresoc.v:192268.17-192268.92" - wire width 6 $not$libresoc.v:192268$13395_Y - attribute \src "libresoc.v:192271.17-192271.92" - wire width 6 $not$libresoc.v:192271$13398_Y - attribute \src "libresoc.v:192265.18-192265.98" - wire width 6 $or$libresoc.v:192265$13392_Y - attribute \src "libresoc.v:192267.18-192267.99" - wire width 6 $or$libresoc.v:192267$13394_Y - attribute \src "libresoc.v:192270.17-192270.97" - wire width 6 $or$libresoc.v:192270$13397_Y + attribute \src "libresoc.v:194845.17-194845.96" + wire width 6 $and$libresoc.v:194845$13377_Y + attribute \src "libresoc.v:194850.17-194850.96" + wire width 6 $and$libresoc.v:194850$13382_Y + attribute \src "libresoc.v:194847.18-194847.93" + wire width 6 $not$libresoc.v:194847$13379_Y + attribute \src "libresoc.v:194849.17-194849.92" + wire width 6 $not$libresoc.v:194849$13381_Y + attribute \src "libresoc.v:194852.17-194852.92" + wire width 6 $not$libresoc.v:194852$13384_Y + attribute \src "libresoc.v:194846.18-194846.98" + wire width 6 $or$libresoc.v:194846$13378_Y + attribute \src "libresoc.v:194848.18-194848.99" + wire width 6 $or$libresoc.v:194848$13380_Y + attribute \src "libresoc.v:194851.17-194851.97" + wire width 6 $or$libresoc.v:194851$13383_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -397673,11 +370320,11 @@ module \src_l$67 wire width 6 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 6 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:192229.7-192229.15" + attribute \src "libresoc.v:194810.7-194810.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 6 \q_int @@ -397694,7 +370341,7 @@ module \src_l$67 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 6 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:192264$13391 + cell $and $and$libresoc.v:194845$13377 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -397702,10 +370349,10 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:192264$13391_Y + connect \Y $and$libresoc.v:194845$13377_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:192269$13396 + cell $and $and$libresoc.v:194850$13382 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -397713,34 +370360,34 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:192269$13396_Y + connect \Y $and$libresoc.v:194850$13382_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:192266$13393 + cell $not $not$libresoc.v:194847$13379 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \q_src - connect \Y $not$libresoc.v:192266$13393_Y + connect \Y $not$libresoc.v:194847$13379_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:192268$13395 + cell $not $not$libresoc.v:194849$13381 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_src - connect \Y $not$libresoc.v:192268$13395_Y + connect \Y $not$libresoc.v:194849$13381_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:192271$13398 + cell $not $not$libresoc.v:194852$13384 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \r_src - connect \Y $not$libresoc.v:192271$13398_Y + connect \Y $not$libresoc.v:194852$13384_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:192265$13392 + cell $or $or$libresoc.v:194846$13378 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -397748,10 +370395,10 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:192265$13392_Y + connect \Y $or$libresoc.v:194846$13378_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:192267$13394 + cell $or $or$libresoc.v:194848$13380 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -397759,10 +370406,10 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:192267$13394_Y + connect \Y $or$libresoc.v:194848$13380_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:192270$13397 + cell $or $or$libresoc.v:194851$13383 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \B_SIGNED 0 @@ -397770,39 +370417,39 @@ module \src_l$67 parameter \Y_WIDTH 6 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:192270$13397_Y + connect \Y $or$libresoc.v:194851$13383_Y end - attribute \src "libresoc.v:192229.7-192229.20" - process $proc$libresoc.v:192229$13403 + attribute \src "libresoc.v:194810.7-194810.20" + process $proc$libresoc.v:194810$13389 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:192251.13-192251.26" - process $proc$libresoc.v:192251$13404 + attribute \src "libresoc.v:194832.13-194832.26" + process $proc$libresoc.v:194832$13390 assign { } { } assign $1\q_int[5:0] 6'000000 sync always sync init update \q_int $1\q_int[5:0] end - attribute \src "libresoc.v:192272.3-192273.27" - process $proc$libresoc.v:192272$13399 + attribute \src "libresoc.v:194853.3-194854.27" + process $proc$libresoc.v:194853$13385 assign { } { } assign $0\q_int[5:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[5:0] end - attribute \src "libresoc.v:192274.3-192282.6" - process $proc$libresoc.v:192274$13400 + attribute \src "libresoc.v:194855.3-194863.6" + process $proc$libresoc.v:194855$13386 assign { } { } assign { } { } - assign $0\q_int$next[5:0]$13401 $1\q_int$next[5:0]$13402 - attribute \src "libresoc.v:192275.5-192275.29" + assign $0\q_int$next[5:0]$13387 $1\q_int$next[5:0]$13388 + attribute \src "libresoc.v:194856.5-194856.29" switch \initial - attribute \src "libresoc.v:192275.9-192275.17" + attribute \src "libresoc.v:194856.9-194856.17" case 1'1 case end @@ -397811,56 +370458,56 @@ module \src_l$67 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[5:0]$13402 6'000000 + assign $1\q_int$next[5:0]$13388 6'000000 case - assign $1\q_int$next[5:0]$13402 \$5 + assign $1\q_int$next[5:0]$13388 \$5 end sync always - update \q_int$next $0\q_int$next[5:0]$13401 + update \q_int$next $0\q_int$next[5:0]$13387 end - connect \$9 $and$libresoc.v:192264$13391_Y - connect \$11 $or$libresoc.v:192265$13392_Y - connect \$13 $not$libresoc.v:192266$13393_Y - connect \$15 $or$libresoc.v:192267$13394_Y - connect \$1 $not$libresoc.v:192268$13395_Y - connect \$3 $and$libresoc.v:192269$13396_Y - connect \$5 $or$libresoc.v:192270$13397_Y - connect \$7 $not$libresoc.v:192271$13398_Y + connect \$9 $and$libresoc.v:194845$13377_Y + connect \$11 $or$libresoc.v:194846$13378_Y + connect \$13 $not$libresoc.v:194847$13379_Y + connect \$15 $or$libresoc.v:194848$13380_Y + connect \$1 $not$libresoc.v:194849$13381_Y + connect \$3 $and$libresoc.v:194850$13382_Y + connect \$5 $or$libresoc.v:194851$13383_Y + connect \$7 $not$libresoc.v:194852$13384_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:192290.1-192348.10" +attribute \src "libresoc.v:194871.1-194929.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.div0.src_l" attribute \generator "nMigen" module \src_l$84 - attribute \src "libresoc.v:192291.7-192291.20" + attribute \src "libresoc.v:194872.7-194872.20" wire $0\initial[0:0] - attribute \src "libresoc.v:192336.3-192344.6" - wire width 3 $0\q_int$next[2:0]$13415 - attribute \src "libresoc.v:192334.3-192335.27" + attribute \src "libresoc.v:194917.3-194925.6" + wire width 3 $0\q_int$next[2:0]$13401 + attribute \src "libresoc.v:194915.3-194916.27" wire width 3 $0\q_int[2:0] - attribute \src "libresoc.v:192336.3-192344.6" - wire width 3 $1\q_int$next[2:0]$13416 - attribute \src "libresoc.v:192313.13-192313.25" + attribute \src "libresoc.v:194917.3-194925.6" + wire width 3 $1\q_int$next[2:0]$13402 + attribute \src "libresoc.v:194894.13-194894.25" wire width 3 $1\q_int[2:0] - attribute \src "libresoc.v:192326.17-192326.96" - wire width 3 $and$libresoc.v:192326$13405_Y - attribute \src "libresoc.v:192331.17-192331.96" - wire width 3 $and$libresoc.v:192331$13410_Y - attribute \src "libresoc.v:192328.18-192328.93" - wire width 3 $not$libresoc.v:192328$13407_Y - attribute \src "libresoc.v:192330.17-192330.92" - wire width 3 $not$libresoc.v:192330$13409_Y - attribute \src "libresoc.v:192333.17-192333.92" - wire width 3 $not$libresoc.v:192333$13412_Y - attribute \src "libresoc.v:192327.18-192327.98" - wire width 3 $or$libresoc.v:192327$13406_Y - attribute \src "libresoc.v:192329.18-192329.99" - wire width 3 $or$libresoc.v:192329$13408_Y - attribute \src "libresoc.v:192332.17-192332.97" - wire width 3 $or$libresoc.v:192332$13411_Y + attribute \src "libresoc.v:194907.17-194907.96" + wire width 3 $and$libresoc.v:194907$13391_Y + attribute \src "libresoc.v:194912.17-194912.96" + wire width 3 $and$libresoc.v:194912$13396_Y + attribute \src "libresoc.v:194909.18-194909.93" + wire width 3 $not$libresoc.v:194909$13393_Y + attribute \src "libresoc.v:194911.17-194911.92" + wire width 3 $not$libresoc.v:194911$13395_Y + attribute \src "libresoc.v:194914.17-194914.92" + wire width 3 $not$libresoc.v:194914$13398_Y + attribute \src "libresoc.v:194908.18-194908.98" + wire width 3 $or$libresoc.v:194908$13392_Y + attribute \src "libresoc.v:194910.18-194910.99" + wire width 3 $or$libresoc.v:194910$13394_Y + attribute \src "libresoc.v:194913.17-194913.97" + wire width 3 $or$libresoc.v:194913$13397_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -397877,11 +370524,11 @@ module \src_l$84 wire width 3 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire width 3 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:192291.7-192291.15" + attribute \src "libresoc.v:194872.7-194872.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire width 3 \q_int @@ -397898,7 +370545,7 @@ module \src_l$84 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire width 3 input 2 \s_src attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:192326$13405 + cell $and $and$libresoc.v:194907$13391 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397906,10 +370553,10 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:192326$13405_Y + connect \Y $and$libresoc.v:194907$13391_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:192331$13410 + cell $and $and$libresoc.v:194912$13396 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397917,34 +370564,34 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:192331$13410_Y + connect \Y $and$libresoc.v:194912$13396_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:192328$13407 + cell $not $not$libresoc.v:194909$13393 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \q_src - connect \Y $not$libresoc.v:192328$13407_Y + connect \Y $not$libresoc.v:194909$13393_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:192330$13409 + cell $not $not$libresoc.v:194911$13395 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:192330$13409_Y + connect \Y $not$libresoc.v:194911$13395_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:192333$13412 + cell $not $not$libresoc.v:194914$13398 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \r_src - connect \Y $not$libresoc.v:192333$13412_Y + connect \Y $not$libresoc.v:194914$13398_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:192327$13406 + cell $or $or$libresoc.v:194908$13392 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397952,10 +370599,10 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \$9 connect \B \s_src - connect \Y $or$libresoc.v:192327$13406_Y + connect \Y $or$libresoc.v:194908$13392_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:192329$13408 + cell $or $or$libresoc.v:194910$13394 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397963,10 +370610,10 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \q_src connect \B \q_int - connect \Y $or$libresoc.v:192329$13408_Y + connect \Y $or$libresoc.v:194910$13394_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:192332$13411 + cell $or $or$libresoc.v:194913$13397 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -397974,39 +370621,39 @@ module \src_l$84 parameter \Y_WIDTH 3 connect \A \$3 connect \B \s_src - connect \Y $or$libresoc.v:192332$13411_Y + connect \Y $or$libresoc.v:194913$13397_Y end - attribute \src "libresoc.v:192291.7-192291.20" - process $proc$libresoc.v:192291$13417 + attribute \src "libresoc.v:194872.7-194872.20" + process $proc$libresoc.v:194872$13403 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:192313.13-192313.25" - process $proc$libresoc.v:192313$13418 + attribute \src "libresoc.v:194894.13-194894.25" + process $proc$libresoc.v:194894$13404 assign { } { } assign $1\q_int[2:0] 3'000 sync always sync init update \q_int $1\q_int[2:0] end - attribute \src "libresoc.v:192334.3-192335.27" - process $proc$libresoc.v:192334$13413 + attribute \src "libresoc.v:194915.3-194916.27" + process $proc$libresoc.v:194915$13399 assign { } { } assign $0\q_int[2:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[2:0] end - attribute \src "libresoc.v:192336.3-192344.6" - process $proc$libresoc.v:192336$13414 + attribute \src "libresoc.v:194917.3-194925.6" + process $proc$libresoc.v:194917$13400 assign { } { } assign { } { } - assign $0\q_int$next[2:0]$13415 $1\q_int$next[2:0]$13416 - attribute \src "libresoc.v:192337.5-192337.29" + assign $0\q_int$next[2:0]$13401 $1\q_int$next[2:0]$13402 + attribute \src "libresoc.v:194918.5-194918.29" switch \initial - attribute \src "libresoc.v:192337.9-192337.17" + attribute \src "libresoc.v:194918.9-194918.17" case 1'1 case end @@ -398015,56 +370662,56 @@ module \src_l$84 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[2:0]$13416 3'000 + assign $1\q_int$next[2:0]$13402 3'000 case - assign $1\q_int$next[2:0]$13416 \$5 + assign $1\q_int$next[2:0]$13402 \$5 end sync always - update \q_int$next $0\q_int$next[2:0]$13415 + update \q_int$next $0\q_int$next[2:0]$13401 end - connect \$9 $and$libresoc.v:192326$13405_Y - connect \$11 $or$libresoc.v:192327$13406_Y - connect \$13 $not$libresoc.v:192328$13407_Y - connect \$15 $or$libresoc.v:192329$13408_Y - connect \$1 $not$libresoc.v:192330$13409_Y - connect \$3 $and$libresoc.v:192331$13410_Y - connect \$5 $or$libresoc.v:192332$13411_Y - connect \$7 $not$libresoc.v:192333$13412_Y + connect \$9 $and$libresoc.v:194907$13391_Y + connect \$11 $or$libresoc.v:194908$13392_Y + connect \$13 $not$libresoc.v:194909$13393_Y + connect \$15 $or$libresoc.v:194910$13394_Y + connect \$1 $not$libresoc.v:194911$13395_Y + connect \$3 $and$libresoc.v:194912$13396_Y + connect \$5 $or$libresoc.v:194913$13397_Y + connect \$7 $not$libresoc.v:194914$13398_Y connect \qlq_src \$15 connect \qn_src \$13 connect \q_src \$11 end -attribute \src "libresoc.v:192352.1-192410.10" +attribute \src "libresoc.v:194933.1-194991.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.st_active" attribute \generator "nMigen" module \st_active - attribute \src "libresoc.v:192353.7-192353.20" + attribute \src "libresoc.v:194934.7-194934.20" wire $0\initial[0:0] - attribute \src "libresoc.v:192398.3-192406.6" - wire $0\q_int$next[0:0]$13429 - attribute \src "libresoc.v:192396.3-192397.27" + attribute \src "libresoc.v:194979.3-194987.6" + wire $0\q_int$next[0:0]$13415 + attribute \src "libresoc.v:194977.3-194978.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:192398.3-192406.6" - wire $1\q_int$next[0:0]$13430 - attribute \src "libresoc.v:192375.7-192375.19" + attribute \src "libresoc.v:194979.3-194987.6" + wire $1\q_int$next[0:0]$13416 + attribute \src "libresoc.v:194956.7-194956.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:192388.17-192388.96" - wire $and$libresoc.v:192388$13419_Y - attribute \src "libresoc.v:192393.17-192393.96" - wire $and$libresoc.v:192393$13424_Y - attribute \src "libresoc.v:192390.18-192390.99" - wire $not$libresoc.v:192390$13421_Y - attribute \src "libresoc.v:192392.17-192392.98" - wire $not$libresoc.v:192392$13423_Y - attribute \src "libresoc.v:192395.17-192395.98" - wire $not$libresoc.v:192395$13426_Y - attribute \src "libresoc.v:192389.18-192389.104" - wire $or$libresoc.v:192389$13420_Y - attribute \src "libresoc.v:192391.18-192391.105" - wire $or$libresoc.v:192391$13422_Y - attribute \src "libresoc.v:192394.17-192394.103" - wire $or$libresoc.v:192394$13425_Y + attribute \src "libresoc.v:194969.17-194969.96" + wire $and$libresoc.v:194969$13405_Y + attribute \src "libresoc.v:194974.17-194974.96" + wire $and$libresoc.v:194974$13410_Y + attribute \src "libresoc.v:194971.18-194971.99" + wire $not$libresoc.v:194971$13407_Y + attribute \src "libresoc.v:194973.17-194973.98" + wire $not$libresoc.v:194973$13409_Y + attribute \src "libresoc.v:194976.17-194976.98" + wire $not$libresoc.v:194976$13412_Y + attribute \src "libresoc.v:194970.18-194970.104" + wire $or$libresoc.v:194970$13406_Y + attribute \src "libresoc.v:194972.18-194972.105" + wire $or$libresoc.v:194972$13408_Y + attribute \src "libresoc.v:194975.17-194975.103" + wire $or$libresoc.v:194975$13411_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -398081,11 +370728,11 @@ module \st_active wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:192353.7-192353.15" + attribute \src "libresoc.v:194934.7-194934.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -398102,7 +370749,7 @@ module \st_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 3 \s_st_active attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:192388$13419 + cell $and $and$libresoc.v:194969$13405 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -398110,10 +370757,10 @@ module \st_active parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:192388$13419_Y + connect \Y $and$libresoc.v:194969$13405_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:192393$13424 + cell $and $and$libresoc.v:194974$13410 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -398121,34 +370768,34 @@ module \st_active parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:192393$13424_Y + connect \Y $and$libresoc.v:194974$13410_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:192390$13421 + cell $not $not$libresoc.v:194971$13407 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_st_active - connect \Y $not$libresoc.v:192390$13421_Y + connect \Y $not$libresoc.v:194971$13407_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:192392$13423 + cell $not $not$libresoc.v:194973$13409 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_active - connect \Y $not$libresoc.v:192392$13423_Y + connect \Y $not$libresoc.v:194973$13409_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:192395$13426 + cell $not $not$libresoc.v:194976$13412 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_active - connect \Y $not$libresoc.v:192395$13426_Y + connect \Y $not$libresoc.v:194976$13412_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:192389$13420 + cell $or $or$libresoc.v:194970$13406 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -398156,10 +370803,10 @@ module \st_active parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_st_active - connect \Y $or$libresoc.v:192389$13420_Y + connect \Y $or$libresoc.v:194970$13406_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:192391$13422 + cell $or $or$libresoc.v:194972$13408 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -398167,10 +370814,10 @@ module \st_active parameter \Y_WIDTH 1 connect \A \q_st_active connect \B \q_int - connect \Y $or$libresoc.v:192391$13422_Y + connect \Y $or$libresoc.v:194972$13408_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:192394$13425 + cell $or $or$libresoc.v:194975$13411 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -398178,39 +370825,39 @@ module \st_active parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_st_active - connect \Y $or$libresoc.v:192394$13425_Y + connect \Y $or$libresoc.v:194975$13411_Y end - attribute \src "libresoc.v:192353.7-192353.20" - process $proc$libresoc.v:192353$13431 + attribute \src "libresoc.v:194934.7-194934.20" + process $proc$libresoc.v:194934$13417 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:192375.7-192375.19" - process $proc$libresoc.v:192375$13432 + attribute \src "libresoc.v:194956.7-194956.19" + process $proc$libresoc.v:194956$13418 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:192396.3-192397.27" - process $proc$libresoc.v:192396$13427 + attribute \src "libresoc.v:194977.3-194978.27" + process $proc$libresoc.v:194977$13413 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:192398.3-192406.6" - process $proc$libresoc.v:192398$13428 + attribute \src "libresoc.v:194979.3-194987.6" + process $proc$libresoc.v:194979$13414 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$13429 $1\q_int$next[0:0]$13430 - attribute \src "libresoc.v:192399.5-192399.29" + assign $0\q_int$next[0:0]$13415 $1\q_int$next[0:0]$13416 + attribute \src "libresoc.v:194980.5-194980.29" switch \initial - attribute \src "libresoc.v:192399.9-192399.17" + attribute \src "libresoc.v:194980.9-194980.17" case 1'1 case end @@ -398219,56 +370866,56 @@ module \st_active attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$13430 1'0 + assign $1\q_int$next[0:0]$13416 1'0 case - assign $1\q_int$next[0:0]$13430 \$5 + assign $1\q_int$next[0:0]$13416 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$13429 + update \q_int$next $0\q_int$next[0:0]$13415 end - connect \$9 $and$libresoc.v:192388$13419_Y - connect \$11 $or$libresoc.v:192389$13420_Y - connect \$13 $not$libresoc.v:192390$13421_Y - connect \$15 $or$libresoc.v:192391$13422_Y - connect \$1 $not$libresoc.v:192392$13423_Y - connect \$3 $and$libresoc.v:192393$13424_Y - connect \$5 $or$libresoc.v:192394$13425_Y - connect \$7 $not$libresoc.v:192395$13426_Y + connect \$9 $and$libresoc.v:194969$13405_Y + connect \$11 $or$libresoc.v:194970$13406_Y + connect \$13 $not$libresoc.v:194971$13407_Y + connect \$15 $or$libresoc.v:194972$13408_Y + connect \$1 $not$libresoc.v:194973$13409_Y + connect \$3 $and$libresoc.v:194974$13410_Y + connect \$5 $or$libresoc.v:194975$13411_Y + connect \$7 $not$libresoc.v:194976$13412_Y connect \qlq_st_active \$15 connect \qn_st_active \$13 connect \q_st_active \$11 end -attribute \src "libresoc.v:192414.1-192472.10" +attribute \src "libresoc.v:194995.1-195053.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.st_done" attribute \generator "nMigen" module \st_done - attribute \src "libresoc.v:192415.7-192415.20" + attribute \src "libresoc.v:194996.7-194996.20" wire $0\initial[0:0] - attribute \src "libresoc.v:192460.3-192468.6" - wire $0\q_int$next[0:0]$13443 - attribute \src "libresoc.v:192458.3-192459.27" + attribute \src "libresoc.v:195041.3-195049.6" + wire $0\q_int$next[0:0]$13429 + attribute \src "libresoc.v:195039.3-195040.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:192460.3-192468.6" - wire $1\q_int$next[0:0]$13444 - attribute \src "libresoc.v:192437.7-192437.19" + attribute \src "libresoc.v:195041.3-195049.6" + wire $1\q_int$next[0:0]$13430 + attribute \src "libresoc.v:195018.7-195018.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:192450.17-192450.96" - wire $and$libresoc.v:192450$13433_Y - attribute \src "libresoc.v:192455.17-192455.96" - wire $and$libresoc.v:192455$13438_Y - attribute \src "libresoc.v:192452.18-192452.97" - wire $not$libresoc.v:192452$13435_Y - attribute \src "libresoc.v:192454.17-192454.96" - wire $not$libresoc.v:192454$13437_Y - attribute \src "libresoc.v:192457.17-192457.96" - wire $not$libresoc.v:192457$13440_Y - attribute \src "libresoc.v:192451.18-192451.102" - wire $or$libresoc.v:192451$13434_Y - attribute \src "libresoc.v:192453.18-192453.103" - wire $or$libresoc.v:192453$13436_Y - attribute \src "libresoc.v:192456.17-192456.101" - wire $or$libresoc.v:192456$13439_Y + attribute \src "libresoc.v:195031.17-195031.96" + wire $and$libresoc.v:195031$13419_Y + attribute \src "libresoc.v:195036.17-195036.96" + wire $and$libresoc.v:195036$13424_Y + attribute \src "libresoc.v:195033.18-195033.97" + wire $not$libresoc.v:195033$13421_Y + attribute \src "libresoc.v:195035.17-195035.96" + wire $not$libresoc.v:195035$13423_Y + attribute \src "libresoc.v:195038.17-195038.96" + wire $not$libresoc.v:195038$13426_Y + attribute \src "libresoc.v:195032.18-195032.102" + wire $or$libresoc.v:195032$13420_Y + attribute \src "libresoc.v:195034.18-195034.103" + wire $or$libresoc.v:195034$13422_Y + attribute \src "libresoc.v:195037.17-195037.101" + wire $or$libresoc.v:195037$13425_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -398285,11 +370932,11 @@ module \st_done wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:192415.7-192415.15" + attribute \src "libresoc.v:194996.7-194996.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -398306,7 +370953,7 @@ module \st_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_st_done attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:192450$13433 + cell $and $and$libresoc.v:195031$13419 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -398314,10 +370961,10 @@ module \st_done parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:192450$13433_Y + connect \Y $and$libresoc.v:195031$13419_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:192455$13438 + cell $and $and$libresoc.v:195036$13424 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -398325,34 +370972,34 @@ module \st_done parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:192455$13438_Y + connect \Y $and$libresoc.v:195036$13424_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:192452$13435 + cell $not $not$libresoc.v:195033$13421 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_st_done - connect \Y $not$libresoc.v:192452$13435_Y + connect \Y $not$libresoc.v:195033$13421_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:192454$13437 + cell $not $not$libresoc.v:195035$13423 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_done - connect \Y $not$libresoc.v:192454$13437_Y + connect \Y $not$libresoc.v:195035$13423_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:192457$13440 + cell $not $not$libresoc.v:195038$13426 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_st_done - connect \Y $not$libresoc.v:192457$13440_Y + connect \Y $not$libresoc.v:195038$13426_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:192451$13434 + cell $or $or$libresoc.v:195032$13420 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -398360,10 +371007,10 @@ module \st_done parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_st_done - connect \Y $or$libresoc.v:192451$13434_Y + connect \Y $or$libresoc.v:195032$13420_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:192453$13436 + cell $or $or$libresoc.v:195034$13422 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -398371,10 +371018,10 @@ module \st_done parameter \Y_WIDTH 1 connect \A \q_st_done connect \B \q_int - connect \Y $or$libresoc.v:192453$13436_Y + connect \Y $or$libresoc.v:195034$13422_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:192456$13439 + cell $or $or$libresoc.v:195037$13425 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -398382,39 +371029,39 @@ module \st_done parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_st_done - connect \Y $or$libresoc.v:192456$13439_Y + connect \Y $or$libresoc.v:195037$13425_Y end - attribute \src "libresoc.v:192415.7-192415.20" - process $proc$libresoc.v:192415$13445 + attribute \src "libresoc.v:194996.7-194996.20" + process $proc$libresoc.v:194996$13431 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:192437.7-192437.19" - process $proc$libresoc.v:192437$13446 + attribute \src "libresoc.v:195018.7-195018.19" + process $proc$libresoc.v:195018$13432 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:192458.3-192459.27" - process $proc$libresoc.v:192458$13441 + attribute \src "libresoc.v:195039.3-195040.27" + process $proc$libresoc.v:195039$13427 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:192460.3-192468.6" - process $proc$libresoc.v:192460$13442 + attribute \src "libresoc.v:195041.3-195049.6" + process $proc$libresoc.v:195041$13428 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$13443 $1\q_int$next[0:0]$13444 - attribute \src "libresoc.v:192461.5-192461.29" + assign $0\q_int$next[0:0]$13429 $1\q_int$next[0:0]$13430 + attribute \src "libresoc.v:195042.5-195042.29" switch \initial - attribute \src "libresoc.v:192461.9-192461.17" + attribute \src "libresoc.v:195042.9-195042.17" case 1'1 case end @@ -398423,86 +371070,86 @@ module \st_done attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$13444 1'0 + assign $1\q_int$next[0:0]$13430 1'0 case - assign $1\q_int$next[0:0]$13444 \$5 + assign $1\q_int$next[0:0]$13430 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$13443 + update \q_int$next $0\q_int$next[0:0]$13429 end - connect \$9 $and$libresoc.v:192450$13433_Y - connect \$11 $or$libresoc.v:192451$13434_Y - connect \$13 $not$libresoc.v:192452$13435_Y - connect \$15 $or$libresoc.v:192453$13436_Y - connect \$1 $not$libresoc.v:192454$13437_Y - connect \$3 $and$libresoc.v:192455$13438_Y - connect \$5 $or$libresoc.v:192456$13439_Y - connect \$7 $not$libresoc.v:192457$13440_Y + connect \$9 $and$libresoc.v:195031$13419_Y + connect \$11 $or$libresoc.v:195032$13420_Y + connect \$13 $not$libresoc.v:195033$13421_Y + connect \$15 $or$libresoc.v:195034$13422_Y + connect \$1 $not$libresoc.v:195035$13423_Y + connect \$3 $and$libresoc.v:195036$13424_Y + connect \$5 $or$libresoc.v:195037$13425_Y + connect \$7 $not$libresoc.v:195038$13426_Y connect \qlq_st_done \$15 connect \qn_st_done \$13 connect \q_st_done \$11 end -attribute \src "libresoc.v:192476.1-192772.10" +attribute \src "libresoc.v:195057.1-195353.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.state" attribute \generator "nMigen" module \state - attribute \src "libresoc.v:192724.3-192733.6" + attribute \src "libresoc.v:195305.3-195314.6" wire width 64 $0\cia__data_o[63:0] - attribute \src "libresoc.v:192477.7-192477.20" + attribute \src "libresoc.v:195058.7-195058.20" wire $0\initial[0:0] - attribute \src "libresoc.v:192743.3-192752.6" + attribute \src "libresoc.v:195324.3-195333.6" wire width 64 $0\msr__data_o[63:0] - attribute \src "libresoc.v:192734.3-192742.6" - wire width 3 $0\ren_delay$12$next[2:0]$13470 - attribute \src "libresoc.v:192638.3-192639.43" - wire width 3 $0\ren_delay$12[2:0]$13459 - attribute \src "libresoc.v:192605.13-192605.34" - wire width 3 $0\ren_delay$12[2:0]$13476 - attribute \src "libresoc.v:192696.3-192704.6" - wire width 3 $0\ren_delay$19$next[2:0]$13462 - attribute \src "libresoc.v:192636.3-192637.43" - wire width 3 $0\ren_delay$19[2:0]$13457 - attribute \src "libresoc.v:192609.13-192609.34" - wire width 3 $0\ren_delay$19[2:0]$13478 - attribute \src "libresoc.v:192715.3-192723.6" - wire width 3 $0\ren_delay$next[2:0]$13466 - attribute \src "libresoc.v:192640.3-192641.35" + attribute \src "libresoc.v:195315.3-195323.6" + wire width 3 $0\ren_delay$12$next[2:0]$13456 + attribute \src "libresoc.v:195219.3-195220.43" + wire width 3 $0\ren_delay$12[2:0]$13445 + attribute \src "libresoc.v:195186.13-195186.34" + wire width 3 $0\ren_delay$12[2:0]$13462 + attribute \src "libresoc.v:195277.3-195285.6" + wire width 3 $0\ren_delay$19$next[2:0]$13448 + attribute \src "libresoc.v:195217.3-195218.43" + wire width 3 $0\ren_delay$19[2:0]$13443 + attribute \src "libresoc.v:195190.13-195190.34" + wire width 3 $0\ren_delay$19[2:0]$13464 + attribute \src "libresoc.v:195296.3-195304.6" + wire width 3 $0\ren_delay$next[2:0]$13452 + attribute \src "libresoc.v:195221.3-195222.35" wire width 3 $0\ren_delay[2:0] - attribute \src "libresoc.v:192705.3-192714.6" + attribute \src "libresoc.v:195286.3-195295.6" wire width 64 $0\sv__data_o[63:0] - attribute \src "libresoc.v:192724.3-192733.6" + attribute \src "libresoc.v:195305.3-195314.6" wire width 64 $1\cia__data_o[63:0] - attribute \src "libresoc.v:192743.3-192752.6" + attribute \src "libresoc.v:195324.3-195333.6" wire width 64 $1\msr__data_o[63:0] - attribute \src "libresoc.v:192734.3-192742.6" - wire width 3 $1\ren_delay$12$next[2:0]$13471 - attribute \src "libresoc.v:192696.3-192704.6" - wire width 3 $1\ren_delay$19$next[2:0]$13463 - attribute \src "libresoc.v:192715.3-192723.6" - wire width 3 $1\ren_delay$next[2:0]$13467 - attribute \src "libresoc.v:192603.13-192603.29" + attribute \src "libresoc.v:195315.3-195323.6" + wire width 3 $1\ren_delay$12$next[2:0]$13457 + attribute \src "libresoc.v:195277.3-195285.6" + wire width 3 $1\ren_delay$19$next[2:0]$13449 + attribute \src "libresoc.v:195296.3-195304.6" + wire width 3 $1\ren_delay$next[2:0]$13453 + attribute \src "libresoc.v:195184.13-195184.29" wire width 3 $1\ren_delay[2:0] - attribute \src "libresoc.v:192705.3-192714.6" + attribute \src "libresoc.v:195286.3-195295.6" wire width 64 $1\sv__data_o[63:0] - attribute \src "libresoc.v:192627.18-192627.109" - wire width 64 $or$libresoc.v:192627$13447_Y - attribute \src "libresoc.v:192629.18-192629.124" - wire width 64 $or$libresoc.v:192629$13449_Y - attribute \src "libresoc.v:192630.18-192630.110" - wire width 64 $or$libresoc.v:192630$13450_Y - attribute \src "libresoc.v:192632.18-192632.122" - wire width 64 $or$libresoc.v:192632$13452_Y - attribute \src "libresoc.v:192633.18-192633.109" - wire width 64 $or$libresoc.v:192633$13453_Y - attribute \src "libresoc.v:192635.17-192635.123" - wire width 64 $or$libresoc.v:192635$13455_Y - attribute \src "libresoc.v:192628.18-192628.100" - wire $reduce_or$libresoc.v:192628$13448_Y - attribute \src "libresoc.v:192631.18-192631.100" - wire $reduce_or$libresoc.v:192631$13451_Y - attribute \src "libresoc.v:192634.17-192634.95" - wire $reduce_or$libresoc.v:192634$13454_Y + attribute \src "libresoc.v:195208.18-195208.109" + wire width 64 $or$libresoc.v:195208$13433_Y + attribute \src "libresoc.v:195210.18-195210.124" + wire width 64 $or$libresoc.v:195210$13435_Y + attribute \src "libresoc.v:195211.18-195211.110" + wire width 64 $or$libresoc.v:195211$13436_Y + attribute \src "libresoc.v:195213.18-195213.122" + wire width 64 $or$libresoc.v:195213$13438_Y + attribute \src "libresoc.v:195214.18-195214.109" + wire width 64 $or$libresoc.v:195214$13439_Y + attribute \src "libresoc.v:195216.17-195216.123" + wire width 64 $or$libresoc.v:195216$13441_Y + attribute \src "libresoc.v:195209.18-195209.100" + wire $reduce_or$libresoc.v:195209$13434_Y + attribute \src "libresoc.v:195212.18-195212.100" + wire $reduce_or$libresoc.v:195212$13437_Y + attribute \src "libresoc.v:195215.17-195215.95" + wire $reduce_or$libresoc.v:195215$13440_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 64 \$10 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" @@ -398525,9 +371172,9 @@ module \state wire width 64 output 3 \cia__data_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 2 \cia__ren - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 7 \data_i @@ -398537,7 +371184,7 @@ module \state wire width 64 input 13 \data_i$3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 input 14 \data_i$4 - attribute \src "libresoc.v:192477.7-192477.15" + attribute \src "libresoc.v:195058.7-195058.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 output 9 \msr__data_o @@ -398652,7 +371299,7 @@ module \state attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 15 \wen$5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:192627$13447 + cell $or $or$libresoc.v:195208$13433 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -398660,10 +371307,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_0_cia0__data_o connect \B \$8 - connect \Y $or$libresoc.v:192627$13447_Y + connect \Y $or$libresoc.v:195208$13433_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:192629$13449 + cell $or $or$libresoc.v:195210$13435 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -398671,10 +371318,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_1_msr1__data_o connect \B \reg_2_msr2__data_o - connect \Y $or$libresoc.v:192629$13449_Y + connect \Y $or$libresoc.v:195210$13435_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:192630$13450 + cell $or $or$libresoc.v:195211$13436 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -398682,10 +371329,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_0_msr0__data_o connect \B \$15 - connect \Y $or$libresoc.v:192630$13450_Y + connect \Y $or$libresoc.v:195211$13436_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:192632$13452 + cell $or $or$libresoc.v:195213$13438 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -398693,10 +371340,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_1_sv1__data_o connect \B \reg_2_sv2__data_o - connect \Y $or$libresoc.v:192632$13452_Y + connect \Y $or$libresoc.v:195213$13438_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:192633$13453 + cell $or $or$libresoc.v:195214$13439 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -398704,10 +371351,10 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_0_sv0__data_o connect \B \$22 - connect \Y $or$libresoc.v:192633$13453_Y + connect \Y $or$libresoc.v:195214$13439_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:192635$13455 + cell $or $or$libresoc.v:195216$13441 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -398715,34 +371362,34 @@ module \state parameter \Y_WIDTH 64 connect \A \reg_1_cia1__data_o connect \B \reg_2_cia2__data_o - connect \Y $or$libresoc.v:192635$13455_Y + connect \Y $or$libresoc.v:195216$13441_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:192628$13448 + cell $reduce_or $reduce_or$libresoc.v:195209$13434 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay$12 - connect \Y $reduce_or$libresoc.v:192628$13448_Y + connect \Y $reduce_or$libresoc.v:195209$13434_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:192631$13451 + cell $reduce_or $reduce_or$libresoc.v:195212$13437 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay$19 - connect \Y $reduce_or$libresoc.v:192631$13451_Y + connect \Y $reduce_or$libresoc.v:195212$13437_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:192634$13454 + cell $reduce_or $reduce_or$libresoc.v:195215$13440 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay - connect \Y $reduce_or$libresoc.v:192634$13454_Y + connect \Y $reduce_or$libresoc.v:195215$13440_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:192642.15-192659.4" + attribute \src "libresoc.v:195223.15-195240.4" cell \reg_0$135 \reg_0 connect \cia0__data_o \reg_0_cia0__data_o connect \cia0__ren \reg_0_cia0__ren @@ -398762,7 +371409,7 @@ module \state connect \sv0__wen \reg_0_sv0__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:192660.15-192677.4" + attribute \src "libresoc.v:195241.15-195258.4" cell \reg_1$136 \reg_1 connect \cia1__data_o \reg_1_cia1__data_o connect \cia1__ren \reg_1_cia1__ren @@ -398782,7 +371429,7 @@ module \state connect \sv1__wen \reg_1_sv1__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:192678.15-192695.4" + attribute \src "libresoc.v:195259.15-195276.4" cell \reg_2$137 \reg_2 connect \cia2__data_o \reg_2_cia2__data_o connect \cia2__ren \reg_2_cia2__ren @@ -398801,67 +371448,67 @@ module \state connect \sv2__ren \reg_2_sv2__ren connect \sv2__wen \reg_2_sv2__wen end - attribute \src "libresoc.v:192477.7-192477.20" - process $proc$libresoc.v:192477$13473 + attribute \src "libresoc.v:195058.7-195058.20" + process $proc$libresoc.v:195058$13459 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:192603.13-192603.29" - process $proc$libresoc.v:192603$13474 + attribute \src "libresoc.v:195184.13-195184.29" + process $proc$libresoc.v:195184$13460 assign { } { } assign $1\ren_delay[2:0] 3'000 sync always sync init update \ren_delay $1\ren_delay[2:0] end - attribute \src "libresoc.v:192605.13-192605.34" - process $proc$libresoc.v:192605$13475 + attribute \src "libresoc.v:195186.13-195186.34" + process $proc$libresoc.v:195186$13461 assign { } { } - assign $0\ren_delay$12[2:0]$13476 3'000 + assign $0\ren_delay$12[2:0]$13462 3'000 sync always sync init - update \ren_delay$12 $0\ren_delay$12[2:0]$13476 + update \ren_delay$12 $0\ren_delay$12[2:0]$13462 end - attribute \src "libresoc.v:192609.13-192609.34" - process $proc$libresoc.v:192609$13477 + attribute \src "libresoc.v:195190.13-195190.34" + process $proc$libresoc.v:195190$13463 assign { } { } - assign $0\ren_delay$19[2:0]$13478 3'000 + assign $0\ren_delay$19[2:0]$13464 3'000 sync always sync init - update \ren_delay$19 $0\ren_delay$19[2:0]$13478 + update \ren_delay$19 $0\ren_delay$19[2:0]$13464 end - attribute \src "libresoc.v:192636.3-192637.43" - process $proc$libresoc.v:192636$13456 + attribute \src "libresoc.v:195217.3-195218.43" + process $proc$libresoc.v:195217$13442 assign { } { } - assign $0\ren_delay$19[2:0]$13457 \ren_delay$19$next + assign $0\ren_delay$19[2:0]$13443 \ren_delay$19$next sync posedge \coresync_clk - update \ren_delay$19 $0\ren_delay$19[2:0]$13457 + update \ren_delay$19 $0\ren_delay$19[2:0]$13443 end - attribute \src "libresoc.v:192638.3-192639.43" - process $proc$libresoc.v:192638$13458 + attribute \src "libresoc.v:195219.3-195220.43" + process $proc$libresoc.v:195219$13444 assign { } { } - assign $0\ren_delay$12[2:0]$13459 \ren_delay$12$next + assign $0\ren_delay$12[2:0]$13445 \ren_delay$12$next sync posedge \coresync_clk - update \ren_delay$12 $0\ren_delay$12[2:0]$13459 + update \ren_delay$12 $0\ren_delay$12[2:0]$13445 end - attribute \src "libresoc.v:192640.3-192641.35" - process $proc$libresoc.v:192640$13460 + attribute \src "libresoc.v:195221.3-195222.35" + process $proc$libresoc.v:195221$13446 assign { } { } assign $0\ren_delay[2:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[2:0] end - attribute \src "libresoc.v:192696.3-192704.6" - process $proc$libresoc.v:192696$13461 + attribute \src "libresoc.v:195277.3-195285.6" + process $proc$libresoc.v:195277$13447 assign { } { } assign { } { } - assign $0\ren_delay$19$next[2:0]$13462 $1\ren_delay$19$next[2:0]$13463 - attribute \src "libresoc.v:192697.5-192697.29" + assign $0\ren_delay$19$next[2:0]$13448 $1\ren_delay$19$next[2:0]$13449 + attribute \src "libresoc.v:195278.5-195278.29" switch \initial - attribute \src "libresoc.v:192697.9-192697.17" + attribute \src "libresoc.v:195278.9-195278.17" case 1'1 case end @@ -398870,21 +371517,21 @@ module \state attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$19$next[2:0]$13463 3'000 + assign $1\ren_delay$19$next[2:0]$13449 3'000 case - assign $1\ren_delay$19$next[2:0]$13463 \sv__ren + assign $1\ren_delay$19$next[2:0]$13449 \sv__ren end sync always - update \ren_delay$19$next $0\ren_delay$19$next[2:0]$13462 + update \ren_delay$19$next $0\ren_delay$19$next[2:0]$13448 end - attribute \src "libresoc.v:192705.3-192714.6" - process $proc$libresoc.v:192705$13464 + attribute \src "libresoc.v:195286.3-195295.6" + process $proc$libresoc.v:195286$13450 assign { } { } assign { } { } assign $0\sv__data_o[63:0] $1\sv__data_o[63:0] - attribute \src "libresoc.v:192706.5-192706.29" + attribute \src "libresoc.v:195287.5-195287.29" switch \initial - attribute \src "libresoc.v:192706.9-192706.17" + attribute \src "libresoc.v:195287.9-195287.17" case 1'1 case end @@ -398900,14 +371547,14 @@ module \state sync always update \sv__data_o $0\sv__data_o[63:0] end - attribute \src "libresoc.v:192715.3-192723.6" - process $proc$libresoc.v:192715$13465 + attribute \src "libresoc.v:195296.3-195304.6" + process $proc$libresoc.v:195296$13451 assign { } { } assign { } { } - assign $0\ren_delay$next[2:0]$13466 $1\ren_delay$next[2:0]$13467 - attribute \src "libresoc.v:192716.5-192716.29" + assign $0\ren_delay$next[2:0]$13452 $1\ren_delay$next[2:0]$13453 + attribute \src "libresoc.v:195297.5-195297.29" switch \initial - attribute \src "libresoc.v:192716.9-192716.17" + attribute \src "libresoc.v:195297.9-195297.17" case 1'1 case end @@ -398916,21 +371563,21 @@ module \state attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[2:0]$13467 3'000 + assign $1\ren_delay$next[2:0]$13453 3'000 case - assign $1\ren_delay$next[2:0]$13467 \cia__ren + assign $1\ren_delay$next[2:0]$13453 \cia__ren end sync always - update \ren_delay$next $0\ren_delay$next[2:0]$13466 + update \ren_delay$next $0\ren_delay$next[2:0]$13452 end - attribute \src "libresoc.v:192724.3-192733.6" - process $proc$libresoc.v:192724$13468 + attribute \src "libresoc.v:195305.3-195314.6" + process $proc$libresoc.v:195305$13454 assign { } { } assign { } { } assign $0\cia__data_o[63:0] $1\cia__data_o[63:0] - attribute \src "libresoc.v:192725.5-192725.29" + attribute \src "libresoc.v:195306.5-195306.29" switch \initial - attribute \src "libresoc.v:192725.9-192725.17" + attribute \src "libresoc.v:195306.9-195306.17" case 1'1 case end @@ -398946,14 +371593,14 @@ module \state sync always update \cia__data_o $0\cia__data_o[63:0] end - attribute \src "libresoc.v:192734.3-192742.6" - process $proc$libresoc.v:192734$13469 + attribute \src "libresoc.v:195315.3-195323.6" + process $proc$libresoc.v:195315$13455 assign { } { } assign { } { } - assign $0\ren_delay$12$next[2:0]$13470 $1\ren_delay$12$next[2:0]$13471 - attribute \src "libresoc.v:192735.5-192735.29" + assign $0\ren_delay$12$next[2:0]$13456 $1\ren_delay$12$next[2:0]$13457 + attribute \src "libresoc.v:195316.5-195316.29" switch \initial - attribute \src "libresoc.v:192735.9-192735.17" + attribute \src "libresoc.v:195316.9-195316.17" case 1'1 case end @@ -398962,21 +371609,21 @@ module \state attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$12$next[2:0]$13471 3'000 + assign $1\ren_delay$12$next[2:0]$13457 3'000 case - assign $1\ren_delay$12$next[2:0]$13471 \msr__ren + assign $1\ren_delay$12$next[2:0]$13457 \msr__ren end sync always - update \ren_delay$12$next $0\ren_delay$12$next[2:0]$13470 + update \ren_delay$12$next $0\ren_delay$12$next[2:0]$13456 end - attribute \src "libresoc.v:192743.3-192752.6" - process $proc$libresoc.v:192743$13472 + attribute \src "libresoc.v:195324.3-195333.6" + process $proc$libresoc.v:195324$13458 assign { } { } assign { } { } assign $0\msr__data_o[63:0] $1\msr__data_o[63:0] - attribute \src "libresoc.v:192744.5-192744.29" + attribute \src "libresoc.v:195325.5-195325.29" switch \initial - attribute \src "libresoc.v:192744.9-192744.17" + attribute \src "libresoc.v:195325.9-195325.17" case 1'1 case end @@ -398992,15 +371639,15 @@ module \state sync always update \msr__data_o $0\msr__data_o[63:0] end - connect \$10 $or$libresoc.v:192627$13447_Y - connect \$13 $reduce_or$libresoc.v:192628$13448_Y - connect \$15 $or$libresoc.v:192629$13449_Y - connect \$17 $or$libresoc.v:192630$13450_Y - connect \$20 $reduce_or$libresoc.v:192631$13451_Y - connect \$22 $or$libresoc.v:192632$13452_Y - connect \$24 $or$libresoc.v:192633$13453_Y - connect \$6 $reduce_or$libresoc.v:192634$13454_Y - connect \$8 $or$libresoc.v:192635$13455_Y + connect \$10 $or$libresoc.v:195208$13433_Y + connect \$13 $reduce_or$libresoc.v:195209$13434_Y + connect \$15 $or$libresoc.v:195210$13435_Y + connect \$17 $or$libresoc.v:195211$13436_Y + connect \$20 $reduce_or$libresoc.v:195212$13437_Y + connect \$22 $or$libresoc.v:195213$13438_Y + connect \$24 $or$libresoc.v:195214$13439_Y + connect \$6 $reduce_or$libresoc.v:195215$13440_Y + connect \$8 $or$libresoc.v:195216$13441_Y connect \reg_2_d_wr12__data_i \data_i connect \reg_1_d_wr11__data_i \data_i connect \reg_0_d_wr10__data_i \data_i @@ -399021,37 +371668,37 @@ module \state connect { \reg_2_msr2__ren \reg_1_msr1__ren \reg_0_msr0__ren } \msr__ren connect { \reg_2_cia2__ren \reg_1_cia1__ren \reg_0_cia0__ren } \cia__ren end -attribute \src "libresoc.v:192776.1-192834.10" +attribute \src "libresoc.v:195357.1-195415.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.sto_l" attribute \generator "nMigen" module \sto_l - attribute \src "libresoc.v:192777.7-192777.20" + attribute \src "libresoc.v:195358.7-195358.20" wire $0\initial[0:0] - attribute \src "libresoc.v:192822.3-192830.6" - wire $0\q_int$next[0:0]$13489 - attribute \src "libresoc.v:192820.3-192821.27" + attribute \src "libresoc.v:195403.3-195411.6" + wire $0\q_int$next[0:0]$13475 + attribute \src "libresoc.v:195401.3-195402.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:192822.3-192830.6" - wire $1\q_int$next[0:0]$13490 - attribute \src "libresoc.v:192799.7-192799.19" + attribute \src "libresoc.v:195403.3-195411.6" + wire $1\q_int$next[0:0]$13476 + attribute \src "libresoc.v:195380.7-195380.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:192812.17-192812.96" - wire $and$libresoc.v:192812$13479_Y - attribute \src "libresoc.v:192817.17-192817.96" - wire $and$libresoc.v:192817$13484_Y - attribute \src "libresoc.v:192814.18-192814.93" - wire $not$libresoc.v:192814$13481_Y - attribute \src "libresoc.v:192816.17-192816.92" - wire $not$libresoc.v:192816$13483_Y - attribute \src "libresoc.v:192819.17-192819.92" - wire $not$libresoc.v:192819$13486_Y - attribute \src "libresoc.v:192813.18-192813.98" - wire $or$libresoc.v:192813$13480_Y - attribute \src "libresoc.v:192815.18-192815.99" - wire $or$libresoc.v:192815$13482_Y - attribute \src "libresoc.v:192818.17-192818.97" - wire $or$libresoc.v:192818$13485_Y + attribute \src "libresoc.v:195393.17-195393.96" + wire $and$libresoc.v:195393$13465_Y + attribute \src "libresoc.v:195398.17-195398.96" + wire $and$libresoc.v:195398$13470_Y + attribute \src "libresoc.v:195395.18-195395.93" + wire $not$libresoc.v:195395$13467_Y + attribute \src "libresoc.v:195397.17-195397.92" + wire $not$libresoc.v:195397$13469_Y + attribute \src "libresoc.v:195400.17-195400.92" + wire $not$libresoc.v:195400$13472_Y + attribute \src "libresoc.v:195394.18-195394.98" + wire $or$libresoc.v:195394$13466_Y + attribute \src "libresoc.v:195396.18-195396.99" + wire $or$libresoc.v:195396$13468_Y + attribute \src "libresoc.v:195399.17-195399.97" + wire $or$libresoc.v:195399$13471_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -399068,11 +371715,11 @@ module \sto_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:192777.7-192777.15" + attribute \src "libresoc.v:195358.7-195358.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -399089,7 +371736,7 @@ module \sto_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_sto attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:192812$13479 + cell $and $and$libresoc.v:195393$13465 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399097,10 +371744,10 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:192812$13479_Y + connect \Y $and$libresoc.v:195393$13465_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:192817$13484 + cell $and $and$libresoc.v:195398$13470 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399108,34 +371755,34 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:192817$13484_Y + connect \Y $and$libresoc.v:195398$13470_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:192814$13481 + cell $not $not$libresoc.v:195395$13467 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_sto - connect \Y $not$libresoc.v:192814$13481_Y + connect \Y $not$libresoc.v:195395$13467_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:192816$13483 + cell $not $not$libresoc.v:195397$13469 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_sto - connect \Y $not$libresoc.v:192816$13483_Y + connect \Y $not$libresoc.v:195397$13469_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:192819$13486 + cell $not $not$libresoc.v:195400$13472 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_sto - connect \Y $not$libresoc.v:192819$13486_Y + connect \Y $not$libresoc.v:195400$13472_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:192813$13480 + cell $or $or$libresoc.v:195394$13466 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399143,10 +371790,10 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_sto - connect \Y $or$libresoc.v:192813$13480_Y + connect \Y $or$libresoc.v:195394$13466_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:192815$13482 + cell $or $or$libresoc.v:195396$13468 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399154,10 +371801,10 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \q_sto connect \B \q_int - connect \Y $or$libresoc.v:192815$13482_Y + connect \Y $or$libresoc.v:195396$13468_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:192818$13485 + cell $or $or$libresoc.v:195399$13471 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -399165,39 +371812,39 @@ module \sto_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_sto - connect \Y $or$libresoc.v:192818$13485_Y + connect \Y $or$libresoc.v:195399$13471_Y end - attribute \src "libresoc.v:192777.7-192777.20" - process $proc$libresoc.v:192777$13491 + attribute \src "libresoc.v:195358.7-195358.20" + process $proc$libresoc.v:195358$13477 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:192799.7-192799.19" - process $proc$libresoc.v:192799$13492 + attribute \src "libresoc.v:195380.7-195380.19" + process $proc$libresoc.v:195380$13478 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:192820.3-192821.27" - process $proc$libresoc.v:192820$13487 + attribute \src "libresoc.v:195401.3-195402.27" + process $proc$libresoc.v:195401$13473 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:192822.3-192830.6" - process $proc$libresoc.v:192822$13488 + attribute \src "libresoc.v:195403.3-195411.6" + process $proc$libresoc.v:195403$13474 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$13489 $1\q_int$next[0:0]$13490 - attribute \src "libresoc.v:192823.5-192823.29" + assign $0\q_int$next[0:0]$13475 $1\q_int$next[0:0]$13476 + attribute \src "libresoc.v:195404.5-195404.29" switch \initial - attribute \src "libresoc.v:192823.9-192823.17" + attribute \src "libresoc.v:195404.9-195404.17" case 1'1 case end @@ -399206,26 +371853,26 @@ module \sto_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$13490 1'0 + assign $1\q_int$next[0:0]$13476 1'0 case - assign $1\q_int$next[0:0]$13490 \$5 + assign $1\q_int$next[0:0]$13476 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$13489 + update \q_int$next $0\q_int$next[0:0]$13475 end - connect \$9 $and$libresoc.v:192812$13479_Y - connect \$11 $or$libresoc.v:192813$13480_Y - connect \$13 $not$libresoc.v:192814$13481_Y - connect \$15 $or$libresoc.v:192815$13482_Y - connect \$1 $not$libresoc.v:192816$13483_Y - connect \$3 $and$libresoc.v:192817$13484_Y - connect \$5 $or$libresoc.v:192818$13485_Y - connect \$7 $not$libresoc.v:192819$13486_Y + connect \$9 $and$libresoc.v:195393$13465_Y + connect \$11 $or$libresoc.v:195394$13466_Y + connect \$13 $not$libresoc.v:195395$13467_Y + connect \$15 $or$libresoc.v:195396$13468_Y + connect \$1 $not$libresoc.v:195397$13469_Y + connect \$3 $and$libresoc.v:195398$13470_Y + connect \$5 $or$libresoc.v:195399$13471_Y + connect \$7 $not$libresoc.v:195400$13472_Y connect \qlq_sto \$15 connect \qn_sto \$13 connect \q_sto \$11 end -attribute \src "libresoc.v:192839.1-193960.10" +attribute \src "libresoc.v:195420.1-196409.10" attribute \cells_not_processed 1 attribute \top 1 attribute \nmigen.hierarchy "test_issuer" @@ -399241,34 +371888,34 @@ module \test_issuer wire input 8 \TAP_bus__tms attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" wire output 5 \busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" - wire input 364 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 320 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:10" - wire width 2 input 366 \clk_sel_i + wire width 2 input 322 \clk_sel_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:224" wire input 4 \core_bigendian_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 340 \dbus__ack + wire input 296 \dbus__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 45 output 334 \dbus__adr + wire width 45 output 290 \dbus__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 2 input 344 \dbus__bte + wire width 2 input 300 \dbus__bte attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 3 input 343 \dbus__cti + wire width 3 input 299 \dbus__cti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 338 \dbus__cyc + wire output 294 \dbus__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 input 336 \dbus__dat_r + wire width 64 input 292 \dbus__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 output 335 \dbus__dat_w + wire width 64 output 291 \dbus__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire input 342 \dbus__err + wire input 298 \dbus__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 8 output 337 \dbus__sel + wire width 8 output 293 \dbus__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 339 \dbus__stb + wire output 295 \dbus__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire output 341 \dbus__we + wire output 297 \dbus__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 19 \eint_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -399474,65 +372121,65 @@ module \test_issuer attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 120 \gpio_s7__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire input 329 \ibus__ack + wire input 285 \ibus__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 45 output 323 \ibus__adr + wire width 45 output 279 \ibus__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 2 input 333 \ibus__bte + wire width 2 input 289 \ibus__bte attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 3 input 332 \ibus__cti + wire width 3 input 288 \ibus__cti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire output 327 \ibus__cyc + wire output 283 \ibus__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 64 input 325 \ibus__dat_r + wire width 64 input 281 \ibus__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 64 input 324 \ibus__dat_w + wire width 64 input 280 \ibus__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire input 331 \ibus__err + wire input 287 \ibus__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 8 output 326 \ibus__sel + wire width 8 output 282 \ibus__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire output 328 \ibus__stb + wire output 284 \ibus__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire input 330 \ibus__we + wire input 286 \ibus__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire output 351 \icp_wb__ack + wire output 307 \icp_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 28 input 345 \icp_wb__adr + wire width 28 input 301 \icp_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 349 \icp_wb__cyc + wire input 305 \icp_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 output 347 \icp_wb__dat_r + wire width 32 output 303 \icp_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 input 346 \icp_wb__dat_w + wire width 32 input 302 \icp_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 353 \icp_wb__err + wire input 309 \icp_wb__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 4 input 348 \icp_wb__sel + wire width 4 input 304 \icp_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 350 \icp_wb__stb + wire input 306 \icp_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 352 \icp_wb__we + wire input 308 \icp_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire output 360 \ics_wb__ack + wire output 316 \ics_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 28 input 354 \ics_wb__adr + wire width 28 input 310 \ics_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 358 \ics_wb__cyc + wire input 314 \ics_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 output 356 \ics_wb__dat_r + wire width 32 output 312 \ics_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 input 355 \ics_wb__dat_w + wire width 32 input 311 \ics_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 362 \ics_wb__err + wire input 318 \ics_wb__err attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 4 input 357 \ics_wb__sel + wire width 4 input 313 \ics_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 359 \ics_wb__stb + wire input 315 \ics_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 361 \ics_wb__we + wire input 317 \ics_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" - wire width 16 input 363 \int_level_i + wire width 16 input 319 \int_level_i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" wire input 17 \jtag_wb__ack attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" @@ -399570,419 +372217,331 @@ module \test_issuer attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire output 126 \mspi0_mosi__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 129 \mspi1_clk__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 130 \mspi1_clk__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 131 \mspi1_cs_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 132 \mspi1_cs_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 135 \mspi1_miso__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 136 \mspi1_miso__pad__i + wire input 135 \mtwi_scl__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 133 \mspi1_mosi__core__o + wire output 136 \mtwi_scl__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 134 \mspi1_mosi__pad__o + wire output 129 \mtwi_sda__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 143 \mtwi_scl__core__o + wire input 130 \mtwi_sda__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 144 \mtwi_scl__pad__o + wire input 131 \mtwi_sda__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 137 \mtwi_sda__core__i + wire input 132 \mtwi_sda__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 138 \mtwi_sda__core__o + wire output 133 \mtwi_sda__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 139 \mtwi_sda__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 140 \mtwi_sda__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 141 \mtwi_sda__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 142 \mtwi_sda__pad__oe + wire output 134 \mtwi_sda__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - wire width 64 input 369 \pc_i + wire width 64 input 325 \pc_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire input 1 \pc_i_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:221" wire width 64 output 2 \pc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1079" - wire output 367 \pll_18_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1080" + wire output 323 \pll_18_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:9" wire \pll_clk_24_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:11" wire \pll_clk_pll_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:13" - wire output 368 \pll_lck_o + wire output 324 \pll_lck_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/clock/dummypll.py:12" wire \pll_pll_18_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1094" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1095" wire \pllclk_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1094" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1095" wire \pllclk_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 321 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 145 \pwm_0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 146 \pwm_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 147 \pwm_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 148 \pwm_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" - wire input 365 \rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 155 \sd0_clk__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 156 \sd0_clk__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 149 \sd0_cmd__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 150 \sd0_cmd__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 151 \sd0_cmd__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 152 \sd0_cmd__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 153 \sd0_cmd__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 154 \sd0_cmd__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 157 \sd0_data0__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 158 \sd0_data0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 159 \sd0_data0__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 160 \sd0_data0__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 161 \sd0_data0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 162 \sd0_data0__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 163 \sd0_data1__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 164 \sd0_data1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 165 \sd0_data1__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 166 \sd0_data1__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 167 \sd0_data1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 168 \sd0_data1__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 169 \sd0_data2__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 170 \sd0_data2__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 171 \sd0_data2__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 172 \sd0_data2__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 173 \sd0_data2__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 174 \sd0_data2__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 175 \sd0_data3__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 176 \sd0_data3__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 177 \sd0_data3__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 178 \sd0_data3__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 179 \sd0_data3__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 180 \sd0_data3__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 231 \sdr_a_0__core__o + wire input 187 \sdr_a_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 232 \sdr_a_0__pad__o + wire output 188 \sdr_a_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 267 \sdr_a_10__core__o + wire input 223 \sdr_a_10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 268 \sdr_a_10__pad__o + wire output 224 \sdr_a_10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 269 \sdr_a_11__core__o + wire input 225 \sdr_a_11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 270 \sdr_a_11__pad__o + wire output 226 \sdr_a_11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 271 \sdr_a_12__core__o + wire input 227 \sdr_a_12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 272 \sdr_a_12__pad__o + wire output 228 \sdr_a_12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 233 \sdr_a_1__core__o + wire input 189 \sdr_a_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 234 \sdr_a_1__pad__o + wire output 190 \sdr_a_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 235 \sdr_a_2__core__o + wire input 191 \sdr_a_2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 236 \sdr_a_2__pad__o + wire output 192 \sdr_a_2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 237 \sdr_a_3__core__o + wire input 193 \sdr_a_3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 238 \sdr_a_3__pad__o + wire output 194 \sdr_a_3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 239 \sdr_a_4__core__o + wire input 195 \sdr_a_4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 240 \sdr_a_4__pad__o + wire output 196 \sdr_a_4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 241 \sdr_a_5__core__o + wire input 197 \sdr_a_5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 242 \sdr_a_5__pad__o + wire output 198 \sdr_a_5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 243 \sdr_a_6__core__o + wire input 199 \sdr_a_6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 244 \sdr_a_6__pad__o + wire output 200 \sdr_a_6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 245 \sdr_a_7__core__o + wire input 201 \sdr_a_7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 246 \sdr_a_7__pad__o + wire output 202 \sdr_a_7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 247 \sdr_a_8__core__o + wire input 203 \sdr_a_8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 248 \sdr_a_8__pad__o + wire output 204 \sdr_a_8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 249 \sdr_a_9__core__o + wire input 205 \sdr_a_9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 250 \sdr_a_9__pad__o + wire output 206 \sdr_a_9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 251 \sdr_ba_0__core__o + wire input 207 \sdr_ba_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 252 \sdr_ba_0__pad__o + wire output 208 \sdr_ba_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 253 \sdr_ba_1__core__o + wire input 209 \sdr_ba_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 254 \sdr_ba_1__pad__o + wire output 210 \sdr_ba_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 261 \sdr_cas_n__core__o + wire input 217 \sdr_cas_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 262 \sdr_cas_n__pad__o + wire output 218 \sdr_cas_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 257 \sdr_cke__core__o + wire input 213 \sdr_cke__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 258 \sdr_cke__pad__o + wire output 214 \sdr_cke__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 255 \sdr_clock__core__o + wire input 211 \sdr_clock__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 256 \sdr_clock__pad__o + wire output 212 \sdr_clock__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 265 \sdr_cs_n__core__o + wire input 221 \sdr_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 266 \sdr_cs_n__pad__o + wire output 222 \sdr_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 181 \sdr_dm_0__core__o + wire input 137 \sdr_dm_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 182 \sdr_dm_0__pad__o + wire output 138 \sdr_dm_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 273 \sdr_dm_1__core__o + wire input 229 \sdr_dm_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 274 \sdr_dm_1__pad__o + wire output 230 \sdr_dm_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 183 \sdr_dq_0__core__i + wire output 139 \sdr_dq_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 184 \sdr_dq_0__core__o + wire input 140 \sdr_dq_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 185 \sdr_dq_0__core__oe + wire input 141 \sdr_dq_0__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 186 \sdr_dq_0__pad__i + wire input 142 \sdr_dq_0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 187 \sdr_dq_0__pad__o + wire output 143 \sdr_dq_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 188 \sdr_dq_0__pad__oe + wire output 144 \sdr_dq_0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 287 \sdr_dq_10__core__i + wire output 243 \sdr_dq_10__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 288 \sdr_dq_10__core__o + wire input 244 \sdr_dq_10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 289 \sdr_dq_10__core__oe + wire input 245 \sdr_dq_10__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 290 \sdr_dq_10__pad__i + wire input 246 \sdr_dq_10__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 291 \sdr_dq_10__pad__o + wire output 247 \sdr_dq_10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 292 \sdr_dq_10__pad__oe + wire output 248 \sdr_dq_10__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 293 \sdr_dq_11__core__i + wire output 249 \sdr_dq_11__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 294 \sdr_dq_11__core__o + wire input 250 \sdr_dq_11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 295 \sdr_dq_11__core__oe + wire input 251 \sdr_dq_11__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 296 \sdr_dq_11__pad__i + wire input 252 \sdr_dq_11__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 297 \sdr_dq_11__pad__o + wire output 253 \sdr_dq_11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 298 \sdr_dq_11__pad__oe + wire output 254 \sdr_dq_11__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 299 \sdr_dq_12__core__i + wire output 255 \sdr_dq_12__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 300 \sdr_dq_12__core__o + wire input 256 \sdr_dq_12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 301 \sdr_dq_12__core__oe + wire input 257 \sdr_dq_12__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 302 \sdr_dq_12__pad__i + wire input 258 \sdr_dq_12__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 303 \sdr_dq_12__pad__o + wire output 259 \sdr_dq_12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 304 \sdr_dq_12__pad__oe + wire output 260 \sdr_dq_12__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 305 \sdr_dq_13__core__i + wire output 261 \sdr_dq_13__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 306 \sdr_dq_13__core__o + wire input 262 \sdr_dq_13__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 307 \sdr_dq_13__core__oe + wire input 263 \sdr_dq_13__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 308 \sdr_dq_13__pad__i + wire input 264 \sdr_dq_13__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 309 \sdr_dq_13__pad__o + wire output 265 \sdr_dq_13__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 310 \sdr_dq_13__pad__oe + wire output 266 \sdr_dq_13__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 311 \sdr_dq_14__core__i + wire output 267 \sdr_dq_14__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 312 \sdr_dq_14__core__o + wire input 268 \sdr_dq_14__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 313 \sdr_dq_14__core__oe + wire input 269 \sdr_dq_14__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 314 \sdr_dq_14__pad__i + wire input 270 \sdr_dq_14__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 315 \sdr_dq_14__pad__o + wire output 271 \sdr_dq_14__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 316 \sdr_dq_14__pad__oe + wire output 272 \sdr_dq_14__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 317 \sdr_dq_15__core__i + wire output 273 \sdr_dq_15__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 318 \sdr_dq_15__core__o + wire input 274 \sdr_dq_15__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 319 \sdr_dq_15__core__oe + wire input 275 \sdr_dq_15__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 320 \sdr_dq_15__pad__i + wire input 276 \sdr_dq_15__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 321 \sdr_dq_15__pad__o + wire output 277 \sdr_dq_15__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 322 \sdr_dq_15__pad__oe + wire output 278 \sdr_dq_15__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 189 \sdr_dq_1__core__i + wire output 145 \sdr_dq_1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 190 \sdr_dq_1__core__o + wire input 146 \sdr_dq_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 191 \sdr_dq_1__core__oe + wire input 147 \sdr_dq_1__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 192 \sdr_dq_1__pad__i + wire input 148 \sdr_dq_1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 193 \sdr_dq_1__pad__o + wire output 149 \sdr_dq_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 194 \sdr_dq_1__pad__oe + wire output 150 \sdr_dq_1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 195 \sdr_dq_2__core__i + wire output 151 \sdr_dq_2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 196 \sdr_dq_2__core__o + wire input 152 \sdr_dq_2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 197 \sdr_dq_2__core__oe + wire input 153 \sdr_dq_2__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 198 \sdr_dq_2__pad__i + wire input 154 \sdr_dq_2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 199 \sdr_dq_2__pad__o + wire output 155 \sdr_dq_2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 200 \sdr_dq_2__pad__oe + wire output 156 \sdr_dq_2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 201 \sdr_dq_3__core__i + wire output 157 \sdr_dq_3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 202 \sdr_dq_3__core__o + wire input 158 \sdr_dq_3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 203 \sdr_dq_3__core__oe + wire input 159 \sdr_dq_3__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 204 \sdr_dq_3__pad__i + wire input 160 \sdr_dq_3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 205 \sdr_dq_3__pad__o + wire output 161 \sdr_dq_3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 206 \sdr_dq_3__pad__oe + wire output 162 \sdr_dq_3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 207 \sdr_dq_4__core__i + wire output 163 \sdr_dq_4__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 208 \sdr_dq_4__core__o + wire input 164 \sdr_dq_4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 209 \sdr_dq_4__core__oe + wire input 165 \sdr_dq_4__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 210 \sdr_dq_4__pad__i + wire input 166 \sdr_dq_4__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 211 \sdr_dq_4__pad__o + wire output 167 \sdr_dq_4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 212 \sdr_dq_4__pad__oe + wire output 168 \sdr_dq_4__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 213 \sdr_dq_5__core__i + wire output 169 \sdr_dq_5__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 214 \sdr_dq_5__core__o + wire input 170 \sdr_dq_5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 215 \sdr_dq_5__core__oe + wire input 171 \sdr_dq_5__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 216 \sdr_dq_5__pad__i + wire input 172 \sdr_dq_5__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 217 \sdr_dq_5__pad__o + wire output 173 \sdr_dq_5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 218 \sdr_dq_5__pad__oe + wire output 174 \sdr_dq_5__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 219 \sdr_dq_6__core__i + wire output 175 \sdr_dq_6__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 220 \sdr_dq_6__core__o + wire input 176 \sdr_dq_6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 221 \sdr_dq_6__core__oe + wire input 177 \sdr_dq_6__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 222 \sdr_dq_6__pad__i + wire input 178 \sdr_dq_6__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 223 \sdr_dq_6__pad__o + wire output 179 \sdr_dq_6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 224 \sdr_dq_6__pad__oe + wire output 180 \sdr_dq_6__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 225 \sdr_dq_7__core__i + wire output 181 \sdr_dq_7__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 226 \sdr_dq_7__core__o + wire input 182 \sdr_dq_7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 227 \sdr_dq_7__core__oe + wire input 183 \sdr_dq_7__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 228 \sdr_dq_7__pad__i + wire input 184 \sdr_dq_7__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 229 \sdr_dq_7__pad__o + wire output 185 \sdr_dq_7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 230 \sdr_dq_7__pad__oe + wire output 186 \sdr_dq_7__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 275 \sdr_dq_8__core__i + wire output 231 \sdr_dq_8__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 276 \sdr_dq_8__core__o + wire input 232 \sdr_dq_8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 277 \sdr_dq_8__core__oe + wire input 233 \sdr_dq_8__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 278 \sdr_dq_8__pad__i + wire input 234 \sdr_dq_8__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 279 \sdr_dq_8__pad__o + wire output 235 \sdr_dq_8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 280 \sdr_dq_8__pad__oe + wire output 236 \sdr_dq_8__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 281 \sdr_dq_9__core__i + wire output 237 \sdr_dq_9__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 282 \sdr_dq_9__core__o + wire input 238 \sdr_dq_9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 283 \sdr_dq_9__core__oe + wire input 239 \sdr_dq_9__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 284 \sdr_dq_9__pad__i + wire input 240 \sdr_dq_9__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 285 \sdr_dq_9__pad__o + wire output 241 \sdr_dq_9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 286 \sdr_dq_9__pad__oe + wire output 242 \sdr_dq_9__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 259 \sdr_ras_n__core__o + wire input 215 \sdr_ras_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 260 \sdr_ras_n__pad__o + wire output 216 \sdr_ras_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 263 \sdr_we_n__core__o + wire input 219 \sdr_we_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 264 \sdr_we_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire output 220 \sdr_we_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire \ti_coresync_clk attribute \module_not_derived 1 - attribute \src "libresoc.v:193590.7-193596.4" + attribute \src "libresoc.v:196083.7-196089.4" cell \pll \pll connect \clk_24_i \pll_clk_24_i connect \clk_pll_o \pll_clk_pll_o @@ -399991,7 +372550,7 @@ module \test_issuer connect \pll_lck_o \pll_lck_o end attribute \module_not_derived 1 - attribute \src "libresoc.v:193597.6-193954.4" + attribute \src "libresoc.v:196090.6-196403.4" cell \ti \ti connect \TAP_bus__tck \TAP_bus__tck connect \TAP_bus__tdi \TAP_bus__tdi @@ -400151,14 +372710,6 @@ module \test_issuer connect \mspi0_miso__pad__i \mspi0_miso__pad__i connect \mspi0_mosi__core__o \mspi0_mosi__core__o connect \mspi0_mosi__pad__o \mspi0_mosi__pad__o - connect \mspi1_clk__core__o \mspi1_clk__core__o - connect \mspi1_clk__pad__o \mspi1_clk__pad__o - connect \mspi1_cs_n__core__o \mspi1_cs_n__core__o - connect \mspi1_cs_n__pad__o \mspi1_cs_n__pad__o - connect \mspi1_miso__core__i \mspi1_miso__core__i - connect \mspi1_miso__pad__i \mspi1_miso__pad__i - connect \mspi1_mosi__core__o \mspi1_mosi__core__o - connect \mspi1_mosi__pad__o \mspi1_mosi__pad__o connect \mtwi_scl__core__o \mtwi_scl__core__o connect \mtwi_scl__pad__o \mtwi_scl__pad__o connect \mtwi_sda__core__i \mtwi_sda__core__i @@ -400170,43 +372721,7 @@ module \test_issuer connect \pc_i \pc_i connect \pc_i_ok \pc_i_ok connect \pc_o \pc_o - connect \pwm_0__core__o \pwm_0__core__o - connect \pwm_0__pad__o \pwm_0__pad__o - connect \pwm_1__core__o \pwm_1__core__o - connect \pwm_1__pad__o \pwm_1__pad__o connect \rst \rst - connect \sd0_clk__core__o \sd0_clk__core__o - connect \sd0_clk__pad__o \sd0_clk__pad__o - connect \sd0_cmd__core__i \sd0_cmd__core__i - connect \sd0_cmd__core__o \sd0_cmd__core__o - connect \sd0_cmd__core__oe \sd0_cmd__core__oe - connect \sd0_cmd__pad__i \sd0_cmd__pad__i - connect \sd0_cmd__pad__o \sd0_cmd__pad__o - connect \sd0_cmd__pad__oe \sd0_cmd__pad__oe - connect \sd0_data0__core__i \sd0_data0__core__i - connect \sd0_data0__core__o \sd0_data0__core__o - connect \sd0_data0__core__oe \sd0_data0__core__oe - connect \sd0_data0__pad__i \sd0_data0__pad__i - connect \sd0_data0__pad__o \sd0_data0__pad__o - connect \sd0_data0__pad__oe \sd0_data0__pad__oe - connect \sd0_data1__core__i \sd0_data1__core__i - connect \sd0_data1__core__o \sd0_data1__core__o - connect \sd0_data1__core__oe \sd0_data1__core__oe - connect \sd0_data1__pad__i \sd0_data1__pad__i - connect \sd0_data1__pad__o \sd0_data1__pad__o - connect \sd0_data1__pad__oe \sd0_data1__pad__oe - connect \sd0_data2__core__i \sd0_data2__core__i - connect \sd0_data2__core__o \sd0_data2__core__o - connect \sd0_data2__core__oe \sd0_data2__core__oe - connect \sd0_data2__pad__i \sd0_data2__pad__i - connect \sd0_data2__pad__o \sd0_data2__pad__o - connect \sd0_data2__pad__oe \sd0_data2__pad__oe - connect \sd0_data3__core__i \sd0_data3__core__i - connect \sd0_data3__core__o \sd0_data3__core__o - connect \sd0_data3__core__oe \sd0_data3__core__oe - connect \sd0_data3__pad__i \sd0_data3__pad__i - connect \sd0_data3__pad__o \sd0_data3__pad__o - connect \sd0_data3__pad__oe \sd0_data3__pad__oe connect \sdr_a_0__core__o \sdr_a_0__core__o connect \sdr_a_0__pad__o \sdr_a_0__pad__o connect \sdr_a_10__core__o \sdr_a_10__core__o @@ -400356,1795 +372871,1795 @@ module \test_issuer connect \pll_clk_24_i \clk connect \pllclk_clk \pll_clk_pll_o end -attribute \src "libresoc.v:193964.1-199046.10" +attribute \src "libresoc.v:196413.1-201735.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti" attribute \generator "nMigen" module \ti - attribute \src "libresoc.v:198886.3-198996.6" - wire width 8 $0\core_asmcode$next[7:0]$13984 - attribute \src "libresoc.v:196482.3-196483.41" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 8 $0\core_asmcode$next[7:0]$13970 + attribute \src "libresoc.v:198843.3-198844.41" wire width 8 $0\core_asmcode[7:0] - attribute \src "libresoc.v:197313.3-197337.6" - wire $0\core_bigendian_i$10$next[0:0]$13779 - attribute \src "libresoc.v:196612.3-196613.57" - wire $0\core_bigendian_i$10[0:0]$13704 - attribute \src "libresoc.v:194239.7-194239.35" - wire $0\core_bigendian_i$10[0:0]$14197 - attribute \src "libresoc.v:197896.3-197908.6" + attribute \src "libresoc.v:199654.3-199698.6" + wire $0\core_bigendian_i$10$next[0:0]$13765 + attribute \src "libresoc.v:198973.3-198974.57" + wire $0\core_bigendian_i$10[0:0]$13690 + attribute \src "libresoc.v:196688.7-196688.35" + wire $0\core_bigendian_i$10[0:0]$14183 + attribute \src "libresoc.v:200417.3-200429.6" wire width 3 $0\core_cia__ren[2:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 64 $0\core_core_core_cia$next[63:0]$13985 - attribute \src "libresoc.v:196556.3-196557.53" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 64 $0\core_core_core_cia$next[63:0]$13971 + attribute \src "libresoc.v:198917.3-198918.53" wire width 64 $0\core_core_core_cia[63:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 8 $0\core_core_core_cr_rd$next[7:0]$13986 - attribute \src "libresoc.v:196600.3-196601.57" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 8 $0\core_core_core_cr_rd$next[7:0]$13972 + attribute \src "libresoc.v:198961.3-198962.57" wire width 8 $0\core_core_core_cr_rd[7:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $0\core_core_core_cr_rd_ok$next[0:0]$13987 - attribute \src "libresoc.v:196602.3-196603.63" + attribute \src "libresoc.v:201555.3-201685.6" + wire $0\core_core_core_cr_rd_ok$next[0:0]$13973 + attribute \src "libresoc.v:198963.3-198964.63" wire $0\core_core_core_cr_rd_ok[0:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 8 $0\core_core_core_cr_wr$next[7:0]$13988 - attribute \src "libresoc.v:196604.3-196605.57" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 8 $0\core_core_core_cr_wr$next[7:0]$13974 + attribute \src "libresoc.v:198965.3-198966.57" wire width 8 $0\core_core_core_cr_wr[7:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $0\core_core_core_exc_$signal$3$next[0:0]$13989 - attribute \src "libresoc.v:196582.3-196583.75" - wire $0\core_core_core_exc_$signal$3[0:0]$13682 - attribute \src "libresoc.v:194265.7-194265.44" - wire $0\core_core_core_exc_$signal$3[0:0]$14205 - attribute \src "libresoc.v:198886.3-198996.6" - wire $0\core_core_core_exc_$signal$4$next[0:0]$13990 - attribute \src "libresoc.v:196584.3-196585.75" - wire $0\core_core_core_exc_$signal$4[0:0]$13684 - attribute \src "libresoc.v:194269.7-194269.44" - wire $0\core_core_core_exc_$signal$4[0:0]$14207 - attribute \src "libresoc.v:198886.3-198996.6" - wire $0\core_core_core_exc_$signal$5$next[0:0]$13991 - attribute \src "libresoc.v:196586.3-196587.75" - wire $0\core_core_core_exc_$signal$5[0:0]$13686 - attribute \src "libresoc.v:194273.7-194273.44" - wire $0\core_core_core_exc_$signal$5[0:0]$14209 - attribute \src "libresoc.v:198886.3-198996.6" - wire $0\core_core_core_exc_$signal$6$next[0:0]$13992 - attribute \src "libresoc.v:196588.3-196589.75" - wire $0\core_core_core_exc_$signal$6[0:0]$13688 - attribute \src "libresoc.v:194277.7-194277.44" - wire $0\core_core_core_exc_$signal$6[0:0]$14211 - attribute \src "libresoc.v:198886.3-198996.6" - wire $0\core_core_core_exc_$signal$7$next[0:0]$13993 - attribute \src "libresoc.v:196592.3-196593.75" - wire $0\core_core_core_exc_$signal$7[0:0]$13691 - attribute \src "libresoc.v:194281.7-194281.44" - wire $0\core_core_core_exc_$signal$7[0:0]$14213 - attribute \src "libresoc.v:198886.3-198996.6" - wire $0\core_core_core_exc_$signal$8$next[0:0]$13994 - attribute \src "libresoc.v:196594.3-196595.75" - wire $0\core_core_core_exc_$signal$8[0:0]$13693 - attribute \src "libresoc.v:194285.7-194285.44" - wire $0\core_core_core_exc_$signal$8[0:0]$14215 - attribute \src "libresoc.v:198886.3-198996.6" - wire $0\core_core_core_exc_$signal$9$next[0:0]$13995 - attribute \src "libresoc.v:196596.3-196597.75" - wire $0\core_core_core_exc_$signal$9[0:0]$13695 - attribute \src "libresoc.v:194289.7-194289.44" - wire $0\core_core_core_exc_$signal$9[0:0]$14217 - attribute \src "libresoc.v:198886.3-198996.6" - wire $0\core_core_core_exc_$signal$next[0:0]$13996 - attribute \src "libresoc.v:196580.3-196581.71" - wire $0\core_core_core_exc_$signal[0:0]$13680 - attribute \src "libresoc.v:194263.7-194263.42" - wire $0\core_core_core_exc_$signal[0:0]$14203 - attribute \src "libresoc.v:198886.3-198996.6" - wire width 14 $0\core_core_core_fn_unit$next[13:0]$13997 - attribute \src "libresoc.v:196562.3-196563.61" + attribute \src "libresoc.v:201555.3-201685.6" + wire $0\core_core_core_exc_$signal$3$next[0:0]$13975 + attribute \src "libresoc.v:198943.3-198944.75" + wire $0\core_core_core_exc_$signal$3[0:0]$13668 + attribute \src "libresoc.v:196714.7-196714.44" + wire $0\core_core_core_exc_$signal$3[0:0]$14191 + attribute \src "libresoc.v:201555.3-201685.6" + wire $0\core_core_core_exc_$signal$4$next[0:0]$13976 + attribute \src "libresoc.v:198945.3-198946.75" + wire $0\core_core_core_exc_$signal$4[0:0]$13670 + attribute \src "libresoc.v:196718.7-196718.44" + wire $0\core_core_core_exc_$signal$4[0:0]$14193 + attribute \src "libresoc.v:201555.3-201685.6" + wire $0\core_core_core_exc_$signal$5$next[0:0]$13977 + attribute \src "libresoc.v:198947.3-198948.75" + wire $0\core_core_core_exc_$signal$5[0:0]$13672 + attribute \src "libresoc.v:196722.7-196722.44" + wire $0\core_core_core_exc_$signal$5[0:0]$14195 + attribute \src "libresoc.v:201555.3-201685.6" + wire $0\core_core_core_exc_$signal$6$next[0:0]$13978 + attribute \src "libresoc.v:198949.3-198950.75" + wire $0\core_core_core_exc_$signal$6[0:0]$13674 + attribute \src "libresoc.v:196726.7-196726.44" + wire $0\core_core_core_exc_$signal$6[0:0]$14197 + attribute \src "libresoc.v:201555.3-201685.6" + wire $0\core_core_core_exc_$signal$7$next[0:0]$13979 + attribute \src "libresoc.v:198953.3-198954.75" + wire $0\core_core_core_exc_$signal$7[0:0]$13677 + attribute \src "libresoc.v:196730.7-196730.44" + wire $0\core_core_core_exc_$signal$7[0:0]$14199 + attribute \src "libresoc.v:201555.3-201685.6" + wire $0\core_core_core_exc_$signal$8$next[0:0]$13980 + attribute \src "libresoc.v:198955.3-198956.75" + wire $0\core_core_core_exc_$signal$8[0:0]$13679 + attribute \src "libresoc.v:196734.7-196734.44" + wire $0\core_core_core_exc_$signal$8[0:0]$14201 + attribute \src "libresoc.v:201555.3-201685.6" + wire $0\core_core_core_exc_$signal$9$next[0:0]$13981 + attribute \src "libresoc.v:198957.3-198958.75" + wire $0\core_core_core_exc_$signal$9[0:0]$13681 + attribute \src "libresoc.v:196738.7-196738.44" + wire $0\core_core_core_exc_$signal$9[0:0]$14203 + attribute \src "libresoc.v:201555.3-201685.6" + wire $0\core_core_core_exc_$signal$next[0:0]$13982 + attribute \src "libresoc.v:198941.3-198942.71" + wire $0\core_core_core_exc_$signal[0:0]$13666 + attribute \src "libresoc.v:196712.7-196712.42" + wire $0\core_core_core_exc_$signal[0:0]$14189 + attribute \src "libresoc.v:201555.3-201685.6" + wire width 14 $0\core_core_core_fn_unit$next[13:0]$13983 + attribute \src "libresoc.v:198923.3-198924.61" wire width 14 $0\core_core_core_fn_unit[13:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 2 $0\core_core_core_input_carry$next[1:0]$13998 - attribute \src "libresoc.v:196576.3-196577.69" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 2 $0\core_core_core_input_carry$next[1:0]$13984 + attribute \src "libresoc.v:198937.3-198938.69" wire width 2 $0\core_core_core_input_carry[1:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 32 $0\core_core_core_insn$next[31:0]$13999 - attribute \src "libresoc.v:196558.3-196559.55" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 32 $0\core_core_core_insn$next[31:0]$13985 + attribute \src "libresoc.v:198919.3-198920.55" wire width 32 $0\core_core_core_insn[31:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 7 $0\core_core_core_insn_type$next[6:0]$14000 - attribute \src "libresoc.v:196560.3-196561.65" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 7 $0\core_core_core_insn_type$next[6:0]$13986 + attribute \src "libresoc.v:198921.3-198922.65" wire width 7 $0\core_core_core_insn_type[6:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $0\core_core_core_is_32bit$next[0:0]$14001 - attribute \src "libresoc.v:196608.3-196609.63" + attribute \src "libresoc.v:201555.3-201685.6" + wire $0\core_core_core_is_32bit$next[0:0]$13987 + attribute \src "libresoc.v:198969.3-198970.63" wire $0\core_core_core_is_32bit[0:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 64 $0\core_core_core_msr$next[63:0]$14002 - attribute \src "libresoc.v:196554.3-196555.53" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 64 $0\core_core_core_msr$next[63:0]$13988 + attribute \src "libresoc.v:198915.3-198916.53" wire width 64 $0\core_core_core_msr[63:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $0\core_core_core_oe$next[0:0]$14003 - attribute \src "libresoc.v:196572.3-196573.51" + attribute \src "libresoc.v:201555.3-201685.6" + wire $0\core_core_core_oe$next[0:0]$13989 + attribute \src "libresoc.v:198933.3-198934.51" wire $0\core_core_core_oe[0:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $0\core_core_core_oe_ok$next[0:0]$14004 - attribute \src "libresoc.v:196574.3-196575.57" + attribute \src "libresoc.v:201555.3-201685.6" + wire $0\core_core_core_oe_ok$next[0:0]$13990 + attribute \src "libresoc.v:198935.3-198936.57" wire $0\core_core_core_oe_ok[0:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $0\core_core_core_rc$next[0:0]$14005 - attribute \src "libresoc.v:196566.3-196567.51" + attribute \src "libresoc.v:201555.3-201685.6" + wire $0\core_core_core_rc$next[0:0]$13991 + attribute \src "libresoc.v:198927.3-198928.51" wire $0\core_core_core_rc[0:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $0\core_core_core_rc_ok$next[0:0]$14006 - attribute \src "libresoc.v:196570.3-196571.57" + attribute \src "libresoc.v:201555.3-201685.6" + wire $0\core_core_core_rc_ok$next[0:0]$13992 + attribute \src "libresoc.v:198931.3-198932.57" wire $0\core_core_core_rc_ok[0:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 13 $0\core_core_core_trapaddr$next[12:0]$14007 - attribute \src "libresoc.v:196598.3-196599.63" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 13 $0\core_core_core_trapaddr$next[12:0]$13993 + attribute \src "libresoc.v:198959.3-198960.63" wire width 13 $0\core_core_core_trapaddr[12:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 8 $0\core_core_core_traptype$next[7:0]$14008 - attribute \src "libresoc.v:196578.3-196579.63" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 8 $0\core_core_core_traptype$next[7:0]$13994 + attribute \src "libresoc.v:198939.3-198940.63" wire width 8 $0\core_core_core_traptype[7:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 7 $0\core_core_cr_in1$next[6:0]$14009 - attribute \src "libresoc.v:196536.3-196537.49" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 7 $0\core_core_cr_in1$next[6:0]$13995 + attribute \src "libresoc.v:198897.3-198898.49" wire width 7 $0\core_core_cr_in1[6:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $0\core_core_cr_in1_ok$next[0:0]$14010 - attribute \src "libresoc.v:196538.3-196539.55" + attribute \src "libresoc.v:201555.3-201685.6" + wire $0\core_core_cr_in1_ok$next[0:0]$13996 + attribute \src "libresoc.v:198899.3-198900.55" wire $0\core_core_cr_in1_ok[0:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 7 $0\core_core_cr_in2$1$next[6:0]$14011 - attribute \src "libresoc.v:196544.3-196545.55" - wire width 7 $0\core_core_cr_in2$1[6:0]$13660 - attribute \src "libresoc.v:194447.13-194447.41" - wire width 7 $0\core_core_cr_in2$1[6:0]$14234 - attribute \src "libresoc.v:198886.3-198996.6" - wire width 7 $0\core_core_cr_in2$next[6:0]$14012 - attribute \src "libresoc.v:196540.3-196541.49" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 7 $0\core_core_cr_in2$1$next[6:0]$13997 + attribute \src "libresoc.v:198905.3-198906.55" + wire width 7 $0\core_core_cr_in2$1[6:0]$13646 + attribute \src "libresoc.v:196896.13-196896.41" + wire width 7 $0\core_core_cr_in2$1[6:0]$14220 + attribute \src "libresoc.v:201555.3-201685.6" + wire width 7 $0\core_core_cr_in2$next[6:0]$13998 + attribute \src "libresoc.v:198901.3-198902.49" wire width 7 $0\core_core_cr_in2[6:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $0\core_core_cr_in2_ok$2$next[0:0]$14013 - attribute \src "libresoc.v:196548.3-196549.61" - wire $0\core_core_cr_in2_ok$2[0:0]$13663 - attribute \src "libresoc.v:194455.7-194455.37" - wire $0\core_core_cr_in2_ok$2[0:0]$14237 - attribute \src "libresoc.v:198886.3-198996.6" - wire $0\core_core_cr_in2_ok$next[0:0]$14014 - attribute \src "libresoc.v:196542.3-196543.55" + attribute \src "libresoc.v:201555.3-201685.6" + wire $0\core_core_cr_in2_ok$2$next[0:0]$13999 + attribute \src "libresoc.v:198909.3-198910.61" + wire $0\core_core_cr_in2_ok$2[0:0]$13649 + attribute \src "libresoc.v:196904.7-196904.37" + wire $0\core_core_cr_in2_ok$2[0:0]$14223 + attribute \src "libresoc.v:201555.3-201685.6" + wire $0\core_core_cr_in2_ok$next[0:0]$14000 + attribute \src "libresoc.v:198903.3-198904.55" wire $0\core_core_cr_in2_ok[0:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 7 $0\core_core_cr_out$next[6:0]$14015 - attribute \src "libresoc.v:196550.3-196551.49" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 7 $0\core_core_cr_out$next[6:0]$14001 + attribute \src "libresoc.v:198911.3-198912.49" wire width 7 $0\core_core_cr_out[6:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $0\core_core_cr_wr_ok$next[0:0]$14016 - attribute \src "libresoc.v:196606.3-196607.53" + attribute \src "libresoc.v:201555.3-201685.6" + wire $0\core_core_cr_wr_ok$next[0:0]$14002 + attribute \src "libresoc.v:198967.3-198968.53" wire $0\core_core_cr_wr_ok[0:0] - attribute \src "libresoc.v:197247.3-197291.6" - wire width 7 $0\core_core_dststep$next[6:0]$13733 - attribute \src "libresoc.v:196472.3-196473.51" + attribute \src "libresoc.v:199564.3-199628.6" + wire width 7 $0\core_core_dststep$next[6:0]$13719 + attribute \src "libresoc.v:198833.3-198834.51" wire width 7 $0\core_core_dststep[6:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 7 $0\core_core_ea$next[6:0]$14017 - attribute \src "libresoc.v:196488.3-196489.41" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 7 $0\core_core_ea$next[6:0]$14003 + attribute \src "libresoc.v:198849.3-198850.41" wire width 7 $0\core_core_ea[6:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 3 $0\core_core_fast1$next[2:0]$14018 - attribute \src "libresoc.v:196518.3-196519.47" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 3 $0\core_core_fast1$next[2:0]$14004 + attribute \src "libresoc.v:198879.3-198880.47" wire width 3 $0\core_core_fast1[2:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $0\core_core_fast1_ok$next[0:0]$14019 - attribute \src "libresoc.v:196520.3-196521.53" + attribute \src "libresoc.v:201555.3-201685.6" + wire $0\core_core_fast1_ok$next[0:0]$14005 + attribute \src "libresoc.v:198881.3-198882.53" wire $0\core_core_fast1_ok[0:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 3 $0\core_core_fast2$next[2:0]$14020 - attribute \src "libresoc.v:196522.3-196523.47" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 3 $0\core_core_fast2$next[2:0]$14006 + attribute \src "libresoc.v:198883.3-198884.47" wire width 3 $0\core_core_fast2[2:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $0\core_core_fast2_ok$next[0:0]$14021 - attribute \src "libresoc.v:196526.3-196527.53" + attribute \src "libresoc.v:201555.3-201685.6" + wire $0\core_core_fast2_ok$next[0:0]$14007 + attribute \src "libresoc.v:198887.3-198888.53" wire $0\core_core_fast2_ok[0:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 3 $0\core_core_fasto1$next[2:0]$14022 - attribute \src "libresoc.v:196528.3-196529.49" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 3 $0\core_core_fasto1$next[2:0]$14008 + attribute \src "libresoc.v:198889.3-198890.49" wire width 3 $0\core_core_fasto1[2:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 3 $0\core_core_fasto2$next[2:0]$14023 - attribute \src "libresoc.v:196532.3-196533.49" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 3 $0\core_core_fasto2$next[2:0]$14009 + attribute \src "libresoc.v:198893.3-198894.49" wire width 3 $0\core_core_fasto2[2:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $0\core_core_lk$next[0:0]$14024 - attribute \src "libresoc.v:196564.3-196565.41" + attribute \src "libresoc.v:201555.3-201685.6" + wire $0\core_core_lk$next[0:0]$14010 + attribute \src "libresoc.v:198925.3-198926.41" wire $0\core_core_lk[0:0] - attribute \src "libresoc.v:197247.3-197291.6" - wire width 7 $0\core_core_maxvl$next[6:0]$13734 - attribute \src "libresoc.v:196478.3-196479.47" + attribute \src "libresoc.v:199564.3-199628.6" + wire width 7 $0\core_core_maxvl$next[6:0]$13720 + attribute \src "libresoc.v:198839.3-198840.47" wire width 7 $0\core_core_maxvl[6:0] - attribute \src "libresoc.v:197247.3-197291.6" - wire width 64 $0\core_core_pc$next[63:0]$13735 - attribute \src "libresoc.v:196450.3-196451.41" + attribute \src "libresoc.v:199564.3-199628.6" + wire width 64 $0\core_core_pc$next[63:0]$13721 + attribute \src "libresoc.v:198811.3-198812.41" wire width 64 $0\core_core_pc[63:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 7 $0\core_core_reg1$next[6:0]$14025 - attribute \src "libresoc.v:196492.3-196493.45" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 7 $0\core_core_reg1$next[6:0]$14011 + attribute \src "libresoc.v:198853.3-198854.45" wire width 7 $0\core_core_reg1[6:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $0\core_core_reg1_ok$next[0:0]$14026 - attribute \src "libresoc.v:196494.3-196495.51" + attribute \src "libresoc.v:201555.3-201685.6" + wire $0\core_core_reg1_ok$next[0:0]$14012 + attribute \src "libresoc.v:198855.3-198856.51" wire $0\core_core_reg1_ok[0:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 7 $0\core_core_reg2$next[6:0]$14027 - attribute \src "libresoc.v:196496.3-196497.45" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 7 $0\core_core_reg2$next[6:0]$14013 + attribute \src "libresoc.v:198857.3-198858.45" wire width 7 $0\core_core_reg2[6:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $0\core_core_reg2_ok$next[0:0]$14028 - attribute \src "libresoc.v:196498.3-196499.51" + attribute \src "libresoc.v:201555.3-201685.6" + wire $0\core_core_reg2_ok$next[0:0]$14014 + attribute \src "libresoc.v:198859.3-198860.51" wire $0\core_core_reg2_ok[0:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 7 $0\core_core_reg3$next[6:0]$14029 - attribute \src "libresoc.v:196500.3-196501.45" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 7 $0\core_core_reg3$next[6:0]$14015 + attribute \src "libresoc.v:198861.3-198862.45" wire width 7 $0\core_core_reg3[6:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $0\core_core_reg3_ok$next[0:0]$14030 - attribute \src "libresoc.v:196504.3-196505.51" + attribute \src "libresoc.v:201555.3-201685.6" + wire $0\core_core_reg3_ok$next[0:0]$14016 + attribute \src "libresoc.v:198865.3-198866.51" wire $0\core_core_reg3_ok[0:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 7 $0\core_core_rego$next[6:0]$14031 - attribute \src "libresoc.v:196484.3-196485.45" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 7 $0\core_core_rego$next[6:0]$14017 + attribute \src "libresoc.v:198845.3-198846.45" wire width 7 $0\core_core_rego[6:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 10 $0\core_core_spr1$next[9:0]$14032 - attribute \src "libresoc.v:196510.3-196511.45" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 10 $0\core_core_spr1$next[9:0]$14018 + attribute \src "libresoc.v:198871.3-198872.45" wire width 10 $0\core_core_spr1[9:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $0\core_core_spr1_ok$next[0:0]$14033 - attribute \src "libresoc.v:196512.3-196513.51" + attribute \src "libresoc.v:201555.3-201685.6" + wire $0\core_core_spr1_ok$next[0:0]$14019 + attribute \src "libresoc.v:198873.3-198874.51" wire $0\core_core_spr1_ok[0:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 10 $0\core_core_spro$next[9:0]$14034 - attribute \src "libresoc.v:196506.3-196507.45" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 10 $0\core_core_spro$next[9:0]$14020 + attribute \src "libresoc.v:198867.3-198868.45" wire width 10 $0\core_core_spro[9:0] - attribute \src "libresoc.v:197247.3-197291.6" - wire width 7 $0\core_core_srcstep$next[6:0]$13736 - attribute \src "libresoc.v:196474.3-196475.51" + attribute \src "libresoc.v:199564.3-199628.6" + wire width 7 $0\core_core_srcstep$next[6:0]$13722 + attribute \src "libresoc.v:198835.3-198836.51" wire width 7 $0\core_core_srcstep[6:0] - attribute \src "libresoc.v:197247.3-197291.6" - wire width 2 $0\core_core_subvl$next[1:0]$13737 - attribute \src "libresoc.v:196470.3-196471.47" + attribute \src "libresoc.v:199564.3-199628.6" + wire width 2 $0\core_core_subvl$next[1:0]$13723 + attribute \src "libresoc.v:198831.3-198832.47" wire width 2 $0\core_core_subvl[1:0] - attribute \src "libresoc.v:197247.3-197291.6" - wire width 2 $0\core_core_svstep$next[1:0]$13738 - attribute \src "libresoc.v:196468.3-196469.49" + attribute \src "libresoc.v:199564.3-199628.6" + wire width 2 $0\core_core_svstep$next[1:0]$13724 + attribute \src "libresoc.v:198829.3-198830.49" wire width 2 $0\core_core_svstep[1:0] - attribute \src "libresoc.v:197247.3-197291.6" - wire width 7 $0\core_core_vl$next[6:0]$13739 - attribute \src "libresoc.v:196476.3-196477.41" + attribute \src "libresoc.v:199564.3-199628.6" + wire width 7 $0\core_core_vl$next[6:0]$13725 + attribute \src "libresoc.v:198837.3-198838.41" wire width 7 $0\core_core_vl[6:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 3 $0\core_core_xer_in$next[2:0]$14035 - attribute \src "libresoc.v:196514.3-196515.49" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 3 $0\core_core_xer_in$next[2:0]$14021 + attribute \src "libresoc.v:198875.3-198876.49" wire width 3 $0\core_core_xer_in[2:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $0\core_cr_out_ok$next[0:0]$14036 - attribute \src "libresoc.v:196552.3-196553.45" + attribute \src "libresoc.v:201555.3-201685.6" + wire $0\core_cr_out_ok$next[0:0]$14022 + attribute \src "libresoc.v:198913.3-198914.45" wire $0\core_cr_out_ok[0:0] - attribute \src "libresoc.v:197481.3-197490.6" - wire width 64 $0\core_data_i$12[63:0]$13798 - attribute \src "libresoc.v:198015.3-198082.6" + attribute \src "libresoc.v:199946.3-199955.6" + wire width 64 $0\core_data_i$12[63:0]$13784 + attribute \src "libresoc.v:200548.3-200627.6" wire width 64 $0\core_data_i[63:0] - attribute \src "libresoc.v:197247.3-197291.6" - wire width 64 $0\core_dec$next[63:0]$13740 - attribute \src "libresoc.v:196466.3-196467.33" + attribute \src "libresoc.v:199564.3-199628.6" + wire width 64 $0\core_dec$next[63:0]$13726 + attribute \src "libresoc.v:198827.3-198828.33" wire width 64 $0\core_dec[63:0] - attribute \src "libresoc.v:197594.3-197603.6" + attribute \src "libresoc.v:200063.3-200072.6" wire width 5 $0\core_dmi__addr[4:0] - attribute \src "libresoc.v:197604.3-197613.6" + attribute \src "libresoc.v:200073.3-200082.6" wire $0\core_dmi__ren[0:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $0\core_ea_ok$next[0:0]$14037 - attribute \src "libresoc.v:196490.3-196491.37" + attribute \src "libresoc.v:201555.3-201685.6" + wire $0\core_ea_ok$next[0:0]$14023 + attribute \src "libresoc.v:198851.3-198852.37" wire $0\core_ea_ok[0:0] - attribute \src "libresoc.v:197247.3-197291.6" - wire $0\core_eint$next[0:0]$13741 - attribute \src "libresoc.v:196464.3-196465.35" + attribute \src "libresoc.v:199564.3-199628.6" + wire $0\core_eint$next[0:0]$13727 + attribute \src "libresoc.v:198825.3-198826.35" wire $0\core_eint[0:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $0\core_fasto1_ok$next[0:0]$14038 - attribute \src "libresoc.v:196530.3-196531.45" + attribute \src "libresoc.v:201555.3-201685.6" + wire $0\core_fasto1_ok$next[0:0]$14024 + attribute \src "libresoc.v:198891.3-198892.45" wire $0\core_fasto1_ok[0:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $0\core_fasto2_ok$next[0:0]$14039 - attribute \src "libresoc.v:196534.3-196535.45" + attribute \src "libresoc.v:201555.3-201685.6" + wire $0\core_fasto2_ok$next[0:0]$14025 + attribute \src "libresoc.v:198895.3-198896.45" wire $0\core_fasto2_ok[0:0] - attribute \src "libresoc.v:197643.3-197652.6" + attribute \src "libresoc.v:200112.3-200121.6" wire width 8 $0\core_full_rd2__ren[7:0] - attribute \src "libresoc.v:197682.3-197691.6" + attribute \src "libresoc.v:200151.3-200160.6" wire width 3 $0\core_full_rd__ren[2:0] - attribute \src "libresoc.v:197790.3-197804.6" - wire width 3 $0\core_issue__addr$13[2:0]$13838 - attribute \src "libresoc.v:197721.3-197735.6" + attribute \src "libresoc.v:200271.3-200293.6" + wire width 3 $0\core_issue__addr$13[2:0]$13824 + attribute \src "libresoc.v:200190.3-200208.6" wire width 3 $0\core_issue__addr[2:0] - attribute \src "libresoc.v:197820.3-197834.6" + attribute \src "libresoc.v:200317.3-200339.6" wire width 64 $0\core_issue__data_i[63:0] - attribute \src "libresoc.v:197736.3-197750.6" + attribute \src "libresoc.v:200209.3-200227.6" wire $0\core_issue__ren[0:0] - attribute \src "libresoc.v:197805.3-197819.6" + attribute \src "libresoc.v:200294.3-200316.6" wire $0\core_issue__wen[0:0] - attribute \src "libresoc.v:197527.3-197542.6" + attribute \src "libresoc.v:199992.3-200007.6" wire $0\core_issue_i[0:0] - attribute \src "libresoc.v:197502.3-197526.6" + attribute \src "libresoc.v:199967.3-199991.6" wire $0\core_ivalid_i[0:0] - attribute \src "libresoc.v:197247.3-197291.6" - wire width 64 $0\core_msr$next[63:0]$13742 - attribute \src "libresoc.v:196462.3-196463.33" + attribute \src "libresoc.v:199564.3-199628.6" + wire width 64 $0\core_msr$next[63:0]$13728 + attribute \src "libresoc.v:198823.3-198824.33" wire width 64 $0\core_msr[63:0] - attribute \src "libresoc.v:198083.3-198098.6" + attribute \src "libresoc.v:200628.3-200643.6" wire width 3 $0\core_msr__ren[2:0] - attribute \src "libresoc.v:197292.3-197312.6" - wire width 32 $0\core_raw_insn_i$next[31:0]$13774 - attribute \src "libresoc.v:196634.3-196635.47" + attribute \src "libresoc.v:199629.3-199653.6" + wire width 32 $0\core_raw_insn_i$next[31:0]$13760 + attribute \src "libresoc.v:198995.3-198996.47" wire width 32 $0\core_raw_insn_i[31:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $0\core_rego_ok$next[0:0]$14040 - attribute \src "libresoc.v:196486.3-196487.41" + attribute \src "libresoc.v:201555.3-201685.6" + wire $0\core_rego_ok$next[0:0]$14026 + attribute \src "libresoc.v:198847.3-198848.41" wire $0\core_rego_ok[0:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $0\core_spro_ok$next[0:0]$14041 - attribute \src "libresoc.v:196508.3-196509.41" + attribute \src "libresoc.v:201555.3-201685.6" + wire $0\core_spro_ok$next[0:0]$14027 + attribute \src "libresoc.v:198869.3-198870.41" wire $0\core_spro_ok[0:0] - attribute \src "libresoc.v:198622.3-198652.6" + attribute \src "libresoc.v:201207.3-201253.6" wire $0\core_stopped_i[0:0] - attribute \src "libresoc.v:197934.3-197946.6" + attribute \src "libresoc.v:200455.3-200467.6" wire width 3 $0\core_sv__ren[2:0] - attribute \src "libresoc.v:197338.3-197362.6" - wire $0\core_sv_a_nz$next[0:0]$13784 - attribute \src "libresoc.v:196590.3-196591.41" + attribute \src "libresoc.v:199699.3-199743.6" + wire $0\core_sv_a_nz$next[0:0]$13770 + attribute \src "libresoc.v:198951.3-198952.41" wire $0\core_sv_a_nz[0:0] - attribute \src "libresoc.v:197471.3-197480.6" - wire width 3 $0\core_wen$11[2:0]$13795 - attribute \src "libresoc.v:197947.3-198014.6" + attribute \src "libresoc.v:199936.3-199945.6" + wire width 3 $0\core_wen$11[2:0]$13781 + attribute \src "libresoc.v:200468.3-200547.6" wire width 3 $0\core_wen[2:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $0\core_xer_out$next[0:0]$14042 - attribute \src "libresoc.v:196516.3-196517.41" + attribute \src "libresoc.v:201555.3-201685.6" + wire $0\core_xer_out$next[0:0]$14028 + attribute \src "libresoc.v:198877.3-198878.41" wire $0\core_xer_out[0:0] - attribute \src "libresoc.v:196648.3-196649.43" + attribute \src "libresoc.v:199009.3-199010.43" wire $0\cu_st__rel_o_dly[0:0] - attribute \src "libresoc.v:198233.3-198271.6" - wire width 7 $0\cur_cur_dststep$next[6:0]$13879 - attribute \src "libresoc.v:196632.3-196633.47" + attribute \src "libresoc.v:200778.3-200816.6" + wire width 7 $0\cur_cur_dststep$next[6:0]$13865 + attribute \src "libresoc.v:198993.3-198994.47" wire width 7 $0\cur_cur_dststep[6:0] - attribute \src "libresoc.v:198233.3-198271.6" - wire width 7 $0\cur_cur_maxvl$next[6:0]$13880 - attribute \src "libresoc.v:196640.3-196641.43" + attribute \src "libresoc.v:200778.3-200816.6" + wire width 7 $0\cur_cur_maxvl$next[6:0]$13866 + attribute \src "libresoc.v:199001.3-199002.43" wire width 7 $0\cur_cur_maxvl[6:0] - attribute \src "libresoc.v:198233.3-198271.6" - wire width 7 $0\cur_cur_srcstep$next[6:0]$13881 - attribute \src "libresoc.v:196636.3-196637.47" + attribute \src "libresoc.v:200778.3-200816.6" + wire width 7 $0\cur_cur_srcstep$next[6:0]$13867 + attribute \src "libresoc.v:198997.3-198998.47" wire width 7 $0\cur_cur_srcstep[6:0] - attribute \src "libresoc.v:198233.3-198271.6" - wire width 2 $0\cur_cur_subvl$next[1:0]$13882 - attribute \src "libresoc.v:196630.3-196631.43" + attribute \src "libresoc.v:200778.3-200816.6" + wire width 2 $0\cur_cur_subvl$next[1:0]$13868 + attribute \src "libresoc.v:198991.3-198992.43" wire width 2 $0\cur_cur_subvl[1:0] - attribute \src "libresoc.v:198233.3-198271.6" - wire width 2 $0\cur_cur_svstep$next[1:0]$13883 - attribute \src "libresoc.v:196628.3-196629.45" + attribute \src "libresoc.v:200778.3-200816.6" + wire width 2 $0\cur_cur_svstep$next[1:0]$13869 + attribute \src "libresoc.v:198989.3-198990.45" wire width 2 $0\cur_cur_svstep[1:0] - attribute \src "libresoc.v:198233.3-198271.6" - wire width 7 $0\cur_cur_vl$next[6:0]$13884 - attribute \src "libresoc.v:196638.3-196639.37" + attribute \src "libresoc.v:200778.3-200816.6" + wire width 7 $0\cur_cur_vl$next[6:0]$13870 + attribute \src "libresoc.v:198999.3-199000.37" wire width 7 $0\cur_cur_vl[6:0] - attribute \src "libresoc.v:197653.3-197661.6" - wire $0\d_cr_delay$next[0:0]$13820 - attribute \src "libresoc.v:196524.3-196525.37" + attribute \src "libresoc.v:200122.3-200130.6" + wire $0\d_cr_delay$next[0:0]$13806 + attribute \src "libresoc.v:198885.3-198886.37" wire $0\d_cr_delay[0:0] - attribute \src "libresoc.v:197614.3-197622.6" - wire $0\d_reg_delay$next[0:0]$13814 - attribute \src "libresoc.v:196546.3-196547.39" + attribute \src "libresoc.v:200083.3-200091.6" + wire $0\d_reg_delay$next[0:0]$13800 + attribute \src "libresoc.v:198907.3-198908.39" wire $0\d_reg_delay[0:0] - attribute \src "libresoc.v:197692.3-197700.6" - wire $0\d_xer_delay$next[0:0]$13826 - attribute \src "libresoc.v:196502.3-196503.39" + attribute \src "libresoc.v:200161.3-200169.6" + wire $0\d_xer_delay$next[0:0]$13812 + attribute \src "libresoc.v:198863.3-198864.39" wire $0\d_xer_delay[0:0] - attribute \src "libresoc.v:198653.3-198683.6" + attribute \src "libresoc.v:201254.3-201300.6" wire $0\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:197672.3-197681.6" + attribute \src "libresoc.v:200141.3-200150.6" wire $0\dbg_d_cr_ack[0:0] - attribute \src "libresoc.v:197662.3-197671.6" + attribute \src "libresoc.v:200131.3-200140.6" wire width 64 $0\dbg_d_cr_data[63:0] - attribute \src "libresoc.v:197633.3-197642.6" + attribute \src "libresoc.v:200102.3-200111.6" wire $0\dbg_d_gpr_ack[0:0] - attribute \src "libresoc.v:197623.3-197632.6" + attribute \src "libresoc.v:200092.3-200101.6" wire width 64 $0\dbg_d_gpr_data[63:0] - attribute \src "libresoc.v:197711.3-197720.6" + attribute \src "libresoc.v:200180.3-200189.6" wire $0\dbg_d_xer_ack[0:0] - attribute \src "libresoc.v:197701.3-197710.6" + attribute \src "libresoc.v:200170.3-200179.6" wire width 64 $0\dbg_d_xer_data[63:0] - attribute \src "libresoc.v:197229.3-197237.6" - wire width 4 $0\dbg_dmi_addr_i$next[3:0]$13727 - attribute \src "libresoc.v:196460.3-196461.45" + attribute \src "libresoc.v:199546.3-199554.6" + wire width 4 $0\dbg_dmi_addr_i$next[3:0]$13713 + attribute \src "libresoc.v:198821.3-198822.45" wire width 4 $0\dbg_dmi_addr_i[3:0] - attribute \src "libresoc.v:198099.3-198107.6" - wire width 64 $0\dbg_dmi_din$next[63:0]$13864 - attribute \src "libresoc.v:196454.3-196455.39" + attribute \src "libresoc.v:200644.3-200652.6" + wire width 64 $0\dbg_dmi_din$next[63:0]$13850 + attribute \src "libresoc.v:198815.3-198816.39" wire width 64 $0\dbg_dmi_din[63:0] - attribute \src "libresoc.v:197238.3-197246.6" - wire $0\dbg_dmi_req_i$next[0:0]$13730 - attribute \src "libresoc.v:196458.3-196459.43" + attribute \src "libresoc.v:199555.3-199563.6" + wire $0\dbg_dmi_req_i$next[0:0]$13716 + attribute \src "libresoc.v:198819.3-198820.43" wire $0\dbg_dmi_req_i[0:0] - attribute \src "libresoc.v:197862.3-197870.6" - wire $0\dbg_dmi_we_i$next[0:0]$13848 - attribute \src "libresoc.v:196456.3-196457.41" + attribute \src "libresoc.v:200383.3-200391.6" + wire $0\dbg_dmi_we_i$next[0:0]$13834 + attribute \src "libresoc.v:198817.3-198818.41" wire $0\dbg_dmi_we_i[0:0] - attribute \src "libresoc.v:197835.3-197850.6" - wire width 64 $0\dec2_cur_dec$next[63:0]$13843 - attribute \src "libresoc.v:196448.3-196449.41" + attribute \src "libresoc.v:200340.3-200359.6" + wire width 64 $0\dec2_cur_dec$next[63:0]$13829 + attribute \src "libresoc.v:198809.3-198810.41" wire width 64 $0\dec2_cur_dec[63:0] - attribute \src "libresoc.v:198997.3-199005.6" - wire $0\dec2_cur_eint$next[0:0]$14189 - attribute \src "libresoc.v:196652.3-196653.43" + attribute \src "libresoc.v:201686.3-201694.6" + wire $0\dec2_cur_eint$next[0:0]$14175 + attribute \src "libresoc.v:199013.3-199014.43" wire $0\dec2_cur_eint[0:0] - attribute \src "libresoc.v:198365.3-198385.6" - wire width 64 $0\dec2_cur_msr$next[63:0]$13927 - attribute \src "libresoc.v:196622.3-196623.41" + attribute \src "libresoc.v:200910.3-200934.6" + wire width 64 $0\dec2_cur_msr$next[63:0]$13913 + attribute \src "libresoc.v:198983.3-198984.41" wire width 64 $0\dec2_cur_msr[63:0] - attribute \src "libresoc.v:198212.3-198232.6" - wire width 64 $0\dec2_cur_pc$next[63:0]$13874 - attribute \src "libresoc.v:196642.3-196643.39" + attribute \src "libresoc.v:200757.3-200777.6" + wire width 64 $0\dec2_cur_pc$next[63:0]$13860 + attribute \src "libresoc.v:199003.3-199004.39" wire width 64 $0\dec2_cur_pc[63:0] - attribute \src "libresoc.v:198405.3-198435.6" - wire width 32 $0\dec2_raw_opcode_in$next[31:0]$13936 - attribute \src "libresoc.v:196618.3-196619.53" + attribute \src "libresoc.v:200958.3-200992.6" + wire width 32 $0\dec2_raw_opcode_in$next[31:0]$13922 + attribute \src "libresoc.v:198979.3-198980.53" wire width 32 $0\dec2_raw_opcode_in[31:0] - attribute \src "libresoc.v:199006.3-199015.6" - wire width 2 $0\delay$next[1:0]$14192 - attribute \src "libresoc.v:196650.3-196651.27" + attribute \src "libresoc.v:201695.3-201704.6" + wire width 2 $0\delay$next[1:0]$14178 + attribute \src "libresoc.v:199011.3-199012.27" wire width 2 $0\delay[1:0] - attribute \src "libresoc.v:197543.3-197577.6" - wire $0\exec_fsm_state$next[0:0]$13804 - attribute \src "libresoc.v:196568.3-196569.45" + attribute \src "libresoc.v:200008.3-200042.6" + wire $0\exec_fsm_state$next[0:0]$13790 + attribute \src "libresoc.v:198929.3-198930.45" wire $0\exec_fsm_state[0:0] - attribute \src "libresoc.v:197491.3-197501.6" + attribute \src "libresoc.v:199956.3-199966.6" wire $0\exec_insn_ready_o[0:0] - attribute \src "libresoc.v:197423.3-197433.6" + attribute \src "libresoc.v:199832.3-199858.6" wire $0\exec_insn_valid_i[0:0] - attribute \src "libresoc.v:197434.3-197449.6" + attribute \src "libresoc.v:199859.3-199894.6" wire $0\exec_pc_ready_i[0:0] - attribute \src "libresoc.v:197578.3-197593.6" + attribute \src "libresoc.v:200043.3-200062.6" wire $0\exec_pc_valid_o[0:0] - attribute \src "libresoc.v:198311.3-198364.6" - wire width 2 $0\fetch_fsm_state$next[1:0]$13919 - attribute \src "libresoc.v:196624.3-196625.47" + attribute \src "libresoc.v:200856.3-200909.6" + wire width 2 $0\fetch_fsm_state$next[1:0]$13905 + attribute \src "libresoc.v:198985.3-198986.47" wire width 2 $0\fetch_fsm_state[1:0] - attribute \src "libresoc.v:198875.3-198885.6" + attribute \src "libresoc.v:201540.3-201554.6" wire $0\fetch_insn_ready_i[0:0] - attribute \src "libresoc.v:198436.3-198446.6" + attribute \src "libresoc.v:200993.3-201015.6" wire $0\fetch_insn_valid_o[0:0] - attribute \src "libresoc.v:198108.3-198118.6" + attribute \src "libresoc.v:200653.3-200663.6" wire $0\fetch_pc_ready_o[0:0] - attribute \src "libresoc.v:198507.3-198522.6" + attribute \src "libresoc.v:201092.3-201107.6" wire $0\fetch_pc_valid_i[0:0] - attribute \src "libresoc.v:197751.3-197778.6" - wire width 2 $0\fsm_state$next[1:0]$13833 - attribute \src "libresoc.v:196480.3-196481.35" + attribute \src "libresoc.v:200228.3-200255.6" + wire width 2 $0\fsm_state$next[1:0]$13819 + attribute \src "libresoc.v:198841.3-198842.35" wire width 2 $0\fsm_state[1:0] - attribute \src "libresoc.v:198119.3-198134.6" + attribute \src "libresoc.v:200664.3-200679.6" wire width 48 $0\imem_a_pc_i[47:0] - attribute \src "libresoc.v:198144.3-198177.6" + attribute \src "libresoc.v:200689.3-200722.6" wire $0\imem_a_valid_i[0:0] - attribute \src "libresoc.v:198178.3-198211.6" + attribute \src "libresoc.v:200723.3-200756.6" wire $0\imem_f_valid_i[0:0] - attribute \src "libresoc.v:193965.7-193965.20" + attribute \src "libresoc.v:196414.7-196414.20" wire $0\initial[0:0] - attribute \src "libresoc.v:197363.3-197400.6" + attribute \src "libresoc.v:199744.3-199789.6" wire $0\insn_done[0:0] - attribute \src "libresoc.v:197450.3-197470.6" + attribute \src "libresoc.v:199895.3-199935.6" wire $0\is_last[0:0] - attribute \src "libresoc.v:198523.3-198621.6" - wire width 3 $0\issue_fsm_state$next[2:0]$13944 - attribute \src "libresoc.v:196616.3-196617.47" + attribute \src "libresoc.v:201108.3-201206.6" + wire width 3 $0\issue_fsm_state$next[2:0]$13930 + attribute \src "libresoc.v:198977.3-198978.47" wire width 3 $0\issue_fsm_state[2:0] - attribute \src "libresoc.v:198135.3-198143.6" - wire $0\jtag_dmi0__ack_o$next[0:0]$13869 - attribute \src "libresoc.v:196452.3-196453.49" + attribute \src "libresoc.v:200680.3-200688.6" + wire $0\jtag_dmi0__ack_o$next[0:0]$13855 + attribute \src "libresoc.v:198813.3-198814.49" wire $0\jtag_dmi0__ack_o[0:0] - attribute \src "libresoc.v:198302.3-198310.6" - wire width 64 $0\jtag_dmi0__dout$next[63:0]$13916 - attribute \src "libresoc.v:196654.3-196655.47" + attribute \src "libresoc.v:200847.3-200855.6" + wire width 64 $0\jtag_dmi0__dout$next[63:0]$13902 + attribute \src "libresoc.v:199015.3-199016.47" wire width 64 $0\jtag_dmi0__dout[63:0] - attribute \src "libresoc.v:198272.3-198301.6" - wire $0\msr_read$next[0:0]$13910 - attribute \src "libresoc.v:196626.3-196627.33" + attribute \src "libresoc.v:200817.3-200846.6" + wire $0\msr_read$next[0:0]$13896 + attribute \src "libresoc.v:198987.3-198988.33" wire $0\msr_read[0:0] - attribute \src "libresoc.v:197779.3-197789.6" + attribute \src "libresoc.v:200256.3-200270.6" wire width 64 $0\new_dec[63:0] - attribute \src "libresoc.v:198447.3-198506.6" + attribute \src "libresoc.v:201016.3-201091.6" wire width 7 $0\new_svstate_dststep[6:0] - attribute \src "libresoc.v:198447.3-198506.6" + attribute \src "libresoc.v:201016.3-201091.6" wire width 7 $0\new_svstate_maxvl[6:0] - attribute \src "libresoc.v:198447.3-198506.6" + attribute \src "libresoc.v:201016.3-201091.6" wire width 7 $0\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:198447.3-198506.6" + attribute \src "libresoc.v:201016.3-201091.6" wire width 2 $0\new_svstate_subvl[1:0] - attribute \src "libresoc.v:198447.3-198506.6" + attribute \src "libresoc.v:201016.3-201091.6" wire width 2 $0\new_svstate_svstep[1:0] - attribute \src "libresoc.v:198447.3-198506.6" + attribute \src "libresoc.v:201016.3-201091.6" wire width 7 $0\new_svstate_vl[6:0] - attribute \src "libresoc.v:197851.3-197861.6" + attribute \src "libresoc.v:200360.3-200382.6" wire width 64 $0\new_tb[63:0] - attribute \src "libresoc.v:198386.3-198404.6" - wire width 64 $0\nia$next[63:0]$13932 - attribute \src "libresoc.v:196620.3-196621.23" + attribute \src "libresoc.v:200935.3-200957.6" + wire width 64 $0\nia$next[63:0]$13918 + attribute \src "libresoc.v:198981.3-198982.23" wire width 64 $0\nia[63:0] - attribute \src "libresoc.v:197880.3-197895.6" + attribute \src "libresoc.v:200401.3-200416.6" wire width 64 $0\pc[63:0] - attribute \src "libresoc.v:198684.3-198750.6" - wire $0\pc_changed$next[0:0]$13960 - attribute \src "libresoc.v:196614.3-196615.37" + attribute \src "libresoc.v:201301.3-201383.6" + wire $0\pc_changed$next[0:0]$13946 + attribute \src "libresoc.v:198975.3-198976.37" wire $0\pc_changed[0:0] - attribute \src "libresoc.v:197871.3-197879.6" - wire $0\pc_ok_delay$next[0:0]$13851 - attribute \src "libresoc.v:196646.3-196647.39" + attribute \src "libresoc.v:200392.3-200400.6" + wire $0\pc_ok_delay$next[0:0]$13837 + attribute \src "libresoc.v:199007.3-199008.39" wire $0\pc_ok_delay[0:0] - attribute \src "libresoc.v:197401.3-197411.6" + attribute \src "libresoc.v:199790.3-199808.6" wire $0\pred_insn_valid_i[0:0] - attribute \src "libresoc.v:197412.3-197422.6" + attribute \src "libresoc.v:199809.3-199831.6" wire $0\pred_mask_ready_i[0:0] - attribute \src "libresoc.v:198808.3-198874.6" - wire $0\sv_changed$next[0:0]$13972 - attribute \src "libresoc.v:196610.3-196611.37" + attribute \src "libresoc.v:201457.3-201539.6" + wire $0\sv_changed$next[0:0]$13958 + attribute \src "libresoc.v:198971.3-198972.37" wire $0\sv_changed[0:0] - attribute \src "libresoc.v:197918.3-197933.6" + attribute \src "libresoc.v:200439.3-200454.6" wire width 64 $0\svstate[63:0] - attribute \src "libresoc.v:197909.3-197917.6" - wire $0\svstate_ok_delay$next[0:0]$13856 - attribute \src "libresoc.v:196644.3-196645.49" + attribute \src "libresoc.v:200430.3-200438.6" + wire $0\svstate_ok_delay$next[0:0]$13842 + attribute \src "libresoc.v:199005.3-199006.49" wire $0\svstate_ok_delay[0:0] - attribute \src "libresoc.v:198751.3-198807.6" + attribute \src "libresoc.v:201384.3-201456.6" wire $0\update_svstate[0:0] - attribute \src "libresoc.v:198523.3-198621.6" - wire width 3 $10\issue_fsm_state$next[2:0]$13954 - attribute \src "libresoc.v:198523.3-198621.6" - wire width 3 $11\issue_fsm_state$next[2:0]$13955 - attribute \src "libresoc.v:198523.3-198621.6" - wire width 3 $12\issue_fsm_state$next[2:0]$13956 - attribute \src "libresoc.v:198886.3-198996.6" - wire width 8 $1\core_asmcode$next[7:0]$14043 - attribute \src "libresoc.v:194233.13-194233.33" + attribute \src "libresoc.v:201108.3-201206.6" + wire width 3 $10\issue_fsm_state$next[2:0]$13940 + attribute \src "libresoc.v:201108.3-201206.6" + wire width 3 $11\issue_fsm_state$next[2:0]$13941 + attribute \src "libresoc.v:201108.3-201206.6" + wire width 3 $12\issue_fsm_state$next[2:0]$13942 + attribute \src "libresoc.v:201555.3-201685.6" + wire width 8 $1\core_asmcode$next[7:0]$14029 + attribute \src "libresoc.v:196682.13-196682.33" wire width 8 $1\core_asmcode[7:0] - attribute \src "libresoc.v:197313.3-197337.6" - wire $1\core_bigendian_i$10$next[0:0]$13780 - attribute \src "libresoc.v:197896.3-197908.6" + attribute \src "libresoc.v:199654.3-199698.6" + wire $1\core_bigendian_i$10$next[0:0]$13766 + attribute \src "libresoc.v:200417.3-200429.6" wire width 3 $1\core_cia__ren[2:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 64 $1\core_core_core_cia$next[63:0]$14044 - attribute \src "libresoc.v:194247.14-194247.55" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 64 $1\core_core_core_cia$next[63:0]$14030 + attribute \src "libresoc.v:196696.14-196696.55" wire width 64 $1\core_core_core_cia[63:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 8 $1\core_core_core_cr_rd$next[7:0]$14045 - attribute \src "libresoc.v:194251.13-194251.41" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 8 $1\core_core_core_cr_rd$next[7:0]$14031 + attribute \src "libresoc.v:196700.13-196700.41" wire width 8 $1\core_core_core_cr_rd[7:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $1\core_core_core_cr_rd_ok$next[0:0]$14046 - attribute \src "libresoc.v:194255.7-194255.37" + attribute \src "libresoc.v:201555.3-201685.6" + wire $1\core_core_core_cr_rd_ok$next[0:0]$14032 + attribute \src "libresoc.v:196704.7-196704.37" wire $1\core_core_core_cr_rd_ok[0:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 8 $1\core_core_core_cr_wr$next[7:0]$14047 - attribute \src "libresoc.v:194259.13-194259.41" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 8 $1\core_core_core_cr_wr$next[7:0]$14033 + attribute \src "libresoc.v:196708.13-196708.41" wire width 8 $1\core_core_core_cr_wr[7:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $1\core_core_core_exc_$signal$3$next[0:0]$14048 - attribute \src "libresoc.v:198886.3-198996.6" - wire $1\core_core_core_exc_$signal$4$next[0:0]$14049 - attribute \src "libresoc.v:198886.3-198996.6" - wire $1\core_core_core_exc_$signal$5$next[0:0]$14050 - attribute \src "libresoc.v:198886.3-198996.6" - wire $1\core_core_core_exc_$signal$6$next[0:0]$14051 - attribute \src "libresoc.v:198886.3-198996.6" - wire $1\core_core_core_exc_$signal$7$next[0:0]$14052 - attribute \src "libresoc.v:198886.3-198996.6" - wire $1\core_core_core_exc_$signal$8$next[0:0]$14053 - attribute \src "libresoc.v:198886.3-198996.6" - wire $1\core_core_core_exc_$signal$9$next[0:0]$14054 - attribute \src "libresoc.v:198886.3-198996.6" - wire $1\core_core_core_exc_$signal$next[0:0]$14055 - attribute \src "libresoc.v:198886.3-198996.6" - wire width 14 $1\core_core_core_fn_unit$next[13:0]$14056 - attribute \src "libresoc.v:194310.14-194310.47" + attribute \src "libresoc.v:201555.3-201685.6" + wire $1\core_core_core_exc_$signal$3$next[0:0]$14034 + attribute \src "libresoc.v:201555.3-201685.6" + wire $1\core_core_core_exc_$signal$4$next[0:0]$14035 + attribute \src "libresoc.v:201555.3-201685.6" + wire $1\core_core_core_exc_$signal$5$next[0:0]$14036 + attribute \src "libresoc.v:201555.3-201685.6" + wire $1\core_core_core_exc_$signal$6$next[0:0]$14037 + attribute \src "libresoc.v:201555.3-201685.6" + wire $1\core_core_core_exc_$signal$7$next[0:0]$14038 + attribute \src "libresoc.v:201555.3-201685.6" + wire $1\core_core_core_exc_$signal$8$next[0:0]$14039 + attribute \src "libresoc.v:201555.3-201685.6" + wire $1\core_core_core_exc_$signal$9$next[0:0]$14040 + attribute \src "libresoc.v:201555.3-201685.6" + wire $1\core_core_core_exc_$signal$next[0:0]$14041 + attribute \src "libresoc.v:201555.3-201685.6" + wire width 14 $1\core_core_core_fn_unit$next[13:0]$14042 + attribute \src "libresoc.v:196759.14-196759.47" wire width 14 $1\core_core_core_fn_unit[13:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 2 $1\core_core_core_input_carry$next[1:0]$14057 - attribute \src "libresoc.v:194318.13-194318.46" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 2 $1\core_core_core_input_carry$next[1:0]$14043 + attribute \src "libresoc.v:196767.13-196767.46" wire width 2 $1\core_core_core_input_carry[1:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 32 $1\core_core_core_insn$next[31:0]$14058 - attribute \src "libresoc.v:194322.14-194322.41" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 32 $1\core_core_core_insn$next[31:0]$14044 + attribute \src "libresoc.v:196771.14-196771.41" wire width 32 $1\core_core_core_insn[31:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 7 $1\core_core_core_insn_type$next[6:0]$14059 - attribute \src "libresoc.v:194401.13-194401.45" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 7 $1\core_core_core_insn_type$next[6:0]$14045 + attribute \src "libresoc.v:196850.13-196850.45" wire width 7 $1\core_core_core_insn_type[6:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $1\core_core_core_is_32bit$next[0:0]$14060 - attribute \src "libresoc.v:194405.7-194405.37" + attribute \src "libresoc.v:201555.3-201685.6" + wire $1\core_core_core_is_32bit$next[0:0]$14046 + attribute \src "libresoc.v:196854.7-196854.37" wire $1\core_core_core_is_32bit[0:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 64 $1\core_core_core_msr$next[63:0]$14061 - attribute \src "libresoc.v:194409.14-194409.55" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 64 $1\core_core_core_msr$next[63:0]$14047 + attribute \src "libresoc.v:196858.14-196858.55" wire width 64 $1\core_core_core_msr[63:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $1\core_core_core_oe$next[0:0]$14062 - attribute \src "libresoc.v:194413.7-194413.31" + attribute \src "libresoc.v:201555.3-201685.6" + wire $1\core_core_core_oe$next[0:0]$14048 + attribute \src "libresoc.v:196862.7-196862.31" wire $1\core_core_core_oe[0:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $1\core_core_core_oe_ok$next[0:0]$14063 - attribute \src "libresoc.v:194417.7-194417.34" + attribute \src "libresoc.v:201555.3-201685.6" + wire $1\core_core_core_oe_ok$next[0:0]$14049 + attribute \src "libresoc.v:196866.7-196866.34" wire $1\core_core_core_oe_ok[0:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $1\core_core_core_rc$next[0:0]$14064 - attribute \src "libresoc.v:194421.7-194421.31" + attribute \src "libresoc.v:201555.3-201685.6" + wire $1\core_core_core_rc$next[0:0]$14050 + attribute \src "libresoc.v:196870.7-196870.31" wire $1\core_core_core_rc[0:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $1\core_core_core_rc_ok$next[0:0]$14065 - attribute \src "libresoc.v:194425.7-194425.34" + attribute \src "libresoc.v:201555.3-201685.6" + wire $1\core_core_core_rc_ok$next[0:0]$14051 + attribute \src "libresoc.v:196874.7-196874.34" wire $1\core_core_core_rc_ok[0:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 13 $1\core_core_core_trapaddr$next[12:0]$14066 - attribute \src "libresoc.v:194429.14-194429.48" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 13 $1\core_core_core_trapaddr$next[12:0]$14052 + attribute \src "libresoc.v:196878.14-196878.48" wire width 13 $1\core_core_core_trapaddr[12:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 8 $1\core_core_core_traptype$next[7:0]$14067 - attribute \src "libresoc.v:194433.13-194433.44" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 8 $1\core_core_core_traptype$next[7:0]$14053 + attribute \src "libresoc.v:196882.13-196882.44" wire width 8 $1\core_core_core_traptype[7:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 7 $1\core_core_cr_in1$next[6:0]$14068 - attribute \src "libresoc.v:194437.13-194437.37" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 7 $1\core_core_cr_in1$next[6:0]$14054 + attribute \src "libresoc.v:196886.13-196886.37" wire width 7 $1\core_core_cr_in1[6:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $1\core_core_cr_in1_ok$next[0:0]$14069 - attribute \src "libresoc.v:194441.7-194441.33" + attribute \src "libresoc.v:201555.3-201685.6" + wire $1\core_core_cr_in1_ok$next[0:0]$14055 + attribute \src "libresoc.v:196890.7-196890.33" wire $1\core_core_cr_in1_ok[0:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 7 $1\core_core_cr_in2$1$next[6:0]$14070 - attribute \src "libresoc.v:198886.3-198996.6" - wire width 7 $1\core_core_cr_in2$next[6:0]$14071 - attribute \src "libresoc.v:194445.13-194445.37" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 7 $1\core_core_cr_in2$1$next[6:0]$14056 + attribute \src "libresoc.v:201555.3-201685.6" + wire width 7 $1\core_core_cr_in2$next[6:0]$14057 + attribute \src "libresoc.v:196894.13-196894.37" wire width 7 $1\core_core_cr_in2[6:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $1\core_core_cr_in2_ok$2$next[0:0]$14072 - attribute \src "libresoc.v:198886.3-198996.6" - wire $1\core_core_cr_in2_ok$next[0:0]$14073 - attribute \src "libresoc.v:194453.7-194453.33" + attribute \src "libresoc.v:201555.3-201685.6" + wire $1\core_core_cr_in2_ok$2$next[0:0]$14058 + attribute \src "libresoc.v:201555.3-201685.6" + wire $1\core_core_cr_in2_ok$next[0:0]$14059 + attribute \src "libresoc.v:196902.7-196902.33" wire $1\core_core_cr_in2_ok[0:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 7 $1\core_core_cr_out$next[6:0]$14074 - attribute \src "libresoc.v:194461.13-194461.37" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 7 $1\core_core_cr_out$next[6:0]$14060 + attribute \src "libresoc.v:196910.13-196910.37" wire width 7 $1\core_core_cr_out[6:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $1\core_core_cr_wr_ok$next[0:0]$14075 - attribute \src "libresoc.v:194465.7-194465.32" + attribute \src "libresoc.v:201555.3-201685.6" + wire $1\core_core_cr_wr_ok$next[0:0]$14061 + attribute \src "libresoc.v:196914.7-196914.32" wire $1\core_core_cr_wr_ok[0:0] - attribute \src "libresoc.v:197247.3-197291.6" - wire width 7 $1\core_core_dststep$next[6:0]$13743 - attribute \src "libresoc.v:194469.13-194469.38" + attribute \src "libresoc.v:199564.3-199628.6" + wire width 7 $1\core_core_dststep$next[6:0]$13729 + attribute \src "libresoc.v:196918.13-196918.38" wire width 7 $1\core_core_dststep[6:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 7 $1\core_core_ea$next[6:0]$14076 - attribute \src "libresoc.v:194473.13-194473.33" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 7 $1\core_core_ea$next[6:0]$14062 + attribute \src "libresoc.v:196922.13-196922.33" wire width 7 $1\core_core_ea[6:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 3 $1\core_core_fast1$next[2:0]$14077 - attribute \src "libresoc.v:194477.13-194477.35" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 3 $1\core_core_fast1$next[2:0]$14063 + attribute \src "libresoc.v:196926.13-196926.35" wire width 3 $1\core_core_fast1[2:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $1\core_core_fast1_ok$next[0:0]$14078 - attribute \src "libresoc.v:194481.7-194481.32" + attribute \src "libresoc.v:201555.3-201685.6" + wire $1\core_core_fast1_ok$next[0:0]$14064 + attribute \src "libresoc.v:196930.7-196930.32" wire $1\core_core_fast1_ok[0:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 3 $1\core_core_fast2$next[2:0]$14079 - attribute \src "libresoc.v:194485.13-194485.35" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 3 $1\core_core_fast2$next[2:0]$14065 + attribute \src "libresoc.v:196934.13-196934.35" wire width 3 $1\core_core_fast2[2:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $1\core_core_fast2_ok$next[0:0]$14080 - attribute \src "libresoc.v:194489.7-194489.32" + attribute \src "libresoc.v:201555.3-201685.6" + wire $1\core_core_fast2_ok$next[0:0]$14066 + attribute \src "libresoc.v:196938.7-196938.32" wire $1\core_core_fast2_ok[0:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 3 $1\core_core_fasto1$next[2:0]$14081 - attribute \src "libresoc.v:194493.13-194493.36" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 3 $1\core_core_fasto1$next[2:0]$14067 + attribute \src "libresoc.v:196942.13-196942.36" wire width 3 $1\core_core_fasto1[2:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 3 $1\core_core_fasto2$next[2:0]$14082 - attribute \src "libresoc.v:194497.13-194497.36" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 3 $1\core_core_fasto2$next[2:0]$14068 + attribute \src "libresoc.v:196946.13-196946.36" wire width 3 $1\core_core_fasto2[2:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $1\core_core_lk$next[0:0]$14083 - attribute \src "libresoc.v:194501.7-194501.26" + attribute \src "libresoc.v:201555.3-201685.6" + wire $1\core_core_lk$next[0:0]$14069 + attribute \src "libresoc.v:196950.7-196950.26" wire $1\core_core_lk[0:0] - attribute \src "libresoc.v:197247.3-197291.6" - wire width 7 $1\core_core_maxvl$next[6:0]$13744 - attribute \src "libresoc.v:194505.13-194505.36" + attribute \src "libresoc.v:199564.3-199628.6" + wire width 7 $1\core_core_maxvl$next[6:0]$13730 + attribute \src "libresoc.v:196954.13-196954.36" wire width 7 $1\core_core_maxvl[6:0] - attribute \src "libresoc.v:197247.3-197291.6" - wire width 64 $1\core_core_pc$next[63:0]$13745 - attribute \src "libresoc.v:194509.14-194509.49" + attribute \src "libresoc.v:199564.3-199628.6" + wire width 64 $1\core_core_pc$next[63:0]$13731 + attribute \src "libresoc.v:196958.14-196958.49" wire width 64 $1\core_core_pc[63:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 7 $1\core_core_reg1$next[6:0]$14084 - attribute \src "libresoc.v:194513.13-194513.35" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 7 $1\core_core_reg1$next[6:0]$14070 + attribute \src "libresoc.v:196962.13-196962.35" wire width 7 $1\core_core_reg1[6:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $1\core_core_reg1_ok$next[0:0]$14085 - attribute \src "libresoc.v:194517.7-194517.31" + attribute \src "libresoc.v:201555.3-201685.6" + wire $1\core_core_reg1_ok$next[0:0]$14071 + attribute \src "libresoc.v:196966.7-196966.31" wire $1\core_core_reg1_ok[0:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 7 $1\core_core_reg2$next[6:0]$14086 - attribute \src "libresoc.v:194521.13-194521.35" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 7 $1\core_core_reg2$next[6:0]$14072 + attribute \src "libresoc.v:196970.13-196970.35" wire width 7 $1\core_core_reg2[6:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $1\core_core_reg2_ok$next[0:0]$14087 - attribute \src "libresoc.v:194525.7-194525.31" + attribute \src "libresoc.v:201555.3-201685.6" + wire $1\core_core_reg2_ok$next[0:0]$14073 + attribute \src "libresoc.v:196974.7-196974.31" wire $1\core_core_reg2_ok[0:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 7 $1\core_core_reg3$next[6:0]$14088 - attribute \src "libresoc.v:194529.13-194529.35" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 7 $1\core_core_reg3$next[6:0]$14074 + attribute \src "libresoc.v:196978.13-196978.35" wire width 7 $1\core_core_reg3[6:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $1\core_core_reg3_ok$next[0:0]$14089 - attribute \src "libresoc.v:194533.7-194533.31" + attribute \src "libresoc.v:201555.3-201685.6" + wire $1\core_core_reg3_ok$next[0:0]$14075 + attribute \src "libresoc.v:196982.7-196982.31" wire $1\core_core_reg3_ok[0:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 7 $1\core_core_rego$next[6:0]$14090 - attribute \src "libresoc.v:194537.13-194537.35" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 7 $1\core_core_rego$next[6:0]$14076 + attribute \src "libresoc.v:196986.13-196986.35" wire width 7 $1\core_core_rego[6:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 10 $1\core_core_spr1$next[9:0]$14091 - attribute \src "libresoc.v:194655.13-194655.37" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 10 $1\core_core_spr1$next[9:0]$14077 + attribute \src "libresoc.v:197104.13-197104.37" wire width 10 $1\core_core_spr1[9:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $1\core_core_spr1_ok$next[0:0]$14092 - attribute \src "libresoc.v:194659.7-194659.31" + attribute \src "libresoc.v:201555.3-201685.6" + wire $1\core_core_spr1_ok$next[0:0]$14078 + attribute \src "libresoc.v:197108.7-197108.31" wire $1\core_core_spr1_ok[0:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 10 $1\core_core_spro$next[9:0]$14093 - attribute \src "libresoc.v:194777.13-194777.37" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 10 $1\core_core_spro$next[9:0]$14079 + attribute \src "libresoc.v:197226.13-197226.37" wire width 10 $1\core_core_spro[9:0] - attribute \src "libresoc.v:197247.3-197291.6" - wire width 7 $1\core_core_srcstep$next[6:0]$13746 - attribute \src "libresoc.v:194781.13-194781.38" + attribute \src "libresoc.v:199564.3-199628.6" + wire width 7 $1\core_core_srcstep$next[6:0]$13732 + attribute \src "libresoc.v:197230.13-197230.38" wire width 7 $1\core_core_srcstep[6:0] - attribute \src "libresoc.v:197247.3-197291.6" - wire width 2 $1\core_core_subvl$next[1:0]$13747 - attribute \src "libresoc.v:194785.13-194785.35" + attribute \src "libresoc.v:199564.3-199628.6" + wire width 2 $1\core_core_subvl$next[1:0]$13733 + attribute \src "libresoc.v:197234.13-197234.35" wire width 2 $1\core_core_subvl[1:0] - attribute \src "libresoc.v:197247.3-197291.6" - wire width 2 $1\core_core_svstep$next[1:0]$13748 - attribute \src "libresoc.v:194789.13-194789.36" + attribute \src "libresoc.v:199564.3-199628.6" + wire width 2 $1\core_core_svstep$next[1:0]$13734 + attribute \src "libresoc.v:197238.13-197238.36" wire width 2 $1\core_core_svstep[1:0] - attribute \src "libresoc.v:197247.3-197291.6" - wire width 7 $1\core_core_vl$next[6:0]$13749 - attribute \src "libresoc.v:194795.13-194795.33" + attribute \src "libresoc.v:199564.3-199628.6" + wire width 7 $1\core_core_vl$next[6:0]$13735 + attribute \src "libresoc.v:197244.13-197244.33" wire width 7 $1\core_core_vl[6:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 3 $1\core_core_xer_in$next[2:0]$14094 - attribute \src "libresoc.v:194799.13-194799.36" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 3 $1\core_core_xer_in$next[2:0]$14080 + attribute \src "libresoc.v:197248.13-197248.36" wire width 3 $1\core_core_xer_in[2:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $1\core_cr_out_ok$next[0:0]$14095 - attribute \src "libresoc.v:194807.7-194807.28" + attribute \src "libresoc.v:201555.3-201685.6" + wire $1\core_cr_out_ok$next[0:0]$14081 + attribute \src "libresoc.v:197256.7-197256.28" wire $1\core_cr_out_ok[0:0] - attribute \src "libresoc.v:197481.3-197490.6" - wire width 64 $1\core_data_i$12[63:0]$13799 - attribute \src "libresoc.v:198015.3-198082.6" + attribute \src "libresoc.v:199946.3-199955.6" + wire width 64 $1\core_data_i$12[63:0]$13785 + attribute \src "libresoc.v:200548.3-200627.6" wire width 64 $1\core_data_i[63:0] - attribute \src "libresoc.v:197247.3-197291.6" - wire width 64 $1\core_dec$next[63:0]$13750 - attribute \src "libresoc.v:194823.14-194823.45" + attribute \src "libresoc.v:199564.3-199628.6" + wire width 64 $1\core_dec$next[63:0]$13736 + attribute \src "libresoc.v:197272.14-197272.45" wire width 64 $1\core_dec[63:0] - attribute \src "libresoc.v:197594.3-197603.6" + attribute \src "libresoc.v:200063.3-200072.6" wire width 5 $1\core_dmi__addr[4:0] - attribute \src "libresoc.v:197604.3-197613.6" + attribute \src "libresoc.v:200073.3-200082.6" wire $1\core_dmi__ren[0:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $1\core_ea_ok$next[0:0]$14096 - attribute \src "libresoc.v:194833.7-194833.24" + attribute \src "libresoc.v:201555.3-201685.6" + wire $1\core_ea_ok$next[0:0]$14082 + attribute \src "libresoc.v:197282.7-197282.24" wire $1\core_ea_ok[0:0] - attribute \src "libresoc.v:197247.3-197291.6" - wire $1\core_eint$next[0:0]$13751 - attribute \src "libresoc.v:194837.7-194837.23" + attribute \src "libresoc.v:199564.3-199628.6" + wire $1\core_eint$next[0:0]$13737 + attribute \src "libresoc.v:197286.7-197286.23" wire $1\core_eint[0:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $1\core_fasto1_ok$next[0:0]$14097 - attribute \src "libresoc.v:194841.7-194841.28" + attribute \src "libresoc.v:201555.3-201685.6" + wire $1\core_fasto1_ok$next[0:0]$14083 + attribute \src "libresoc.v:197290.7-197290.28" wire $1\core_fasto1_ok[0:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $1\core_fasto2_ok$next[0:0]$14098 - attribute \src "libresoc.v:194845.7-194845.28" + attribute \src "libresoc.v:201555.3-201685.6" + wire $1\core_fasto2_ok$next[0:0]$14084 + attribute \src "libresoc.v:197294.7-197294.28" wire $1\core_fasto2_ok[0:0] - attribute \src "libresoc.v:197643.3-197652.6" + attribute \src "libresoc.v:200112.3-200121.6" wire width 8 $1\core_full_rd2__ren[7:0] - attribute \src "libresoc.v:197682.3-197691.6" + attribute \src "libresoc.v:200151.3-200160.6" wire width 3 $1\core_full_rd__ren[2:0] - attribute \src "libresoc.v:197790.3-197804.6" - wire width 3 $1\core_issue__addr$13[2:0]$13839 - attribute \src "libresoc.v:197721.3-197735.6" + attribute \src "libresoc.v:200271.3-200293.6" + wire width 3 $1\core_issue__addr$13[2:0]$13825 + attribute \src "libresoc.v:200190.3-200208.6" wire width 3 $1\core_issue__addr[2:0] - attribute \src "libresoc.v:197820.3-197834.6" + attribute \src "libresoc.v:200317.3-200339.6" wire width 64 $1\core_issue__data_i[63:0] - attribute \src "libresoc.v:197736.3-197750.6" + attribute \src "libresoc.v:200209.3-200227.6" wire $1\core_issue__ren[0:0] - attribute \src "libresoc.v:197805.3-197819.6" + attribute \src "libresoc.v:200294.3-200316.6" wire $1\core_issue__wen[0:0] - attribute \src "libresoc.v:197527.3-197542.6" + attribute \src "libresoc.v:199992.3-200007.6" wire $1\core_issue_i[0:0] - attribute \src "libresoc.v:197502.3-197526.6" + attribute \src "libresoc.v:199967.3-199991.6" wire $1\core_ivalid_i[0:0] - attribute \src "libresoc.v:197247.3-197291.6" - wire width 64 $1\core_msr$next[63:0]$13752 - attribute \src "libresoc.v:194873.14-194873.45" + attribute \src "libresoc.v:199564.3-199628.6" + wire width 64 $1\core_msr$next[63:0]$13738 + attribute \src "libresoc.v:197322.14-197322.45" wire width 64 $1\core_msr[63:0] - attribute \src "libresoc.v:198083.3-198098.6" + attribute \src "libresoc.v:200628.3-200643.6" wire width 3 $1\core_msr__ren[2:0] - attribute \src "libresoc.v:197292.3-197312.6" - wire width 32 $1\core_raw_insn_i$next[31:0]$13775 - attribute \src "libresoc.v:194881.14-194881.37" + attribute \src "libresoc.v:199629.3-199653.6" + wire width 32 $1\core_raw_insn_i$next[31:0]$13761 + attribute \src "libresoc.v:197330.14-197330.37" wire width 32 $1\core_raw_insn_i[31:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $1\core_rego_ok$next[0:0]$14099 - attribute \src "libresoc.v:194885.7-194885.26" + attribute \src "libresoc.v:201555.3-201685.6" + wire $1\core_rego_ok$next[0:0]$14085 + attribute \src "libresoc.v:197334.7-197334.26" wire $1\core_rego_ok[0:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $1\core_spro_ok$next[0:0]$14100 - attribute \src "libresoc.v:194889.7-194889.26" + attribute \src "libresoc.v:201555.3-201685.6" + wire $1\core_spro_ok$next[0:0]$14086 + attribute \src "libresoc.v:197338.7-197338.26" wire $1\core_spro_ok[0:0] - attribute \src "libresoc.v:198622.3-198652.6" + attribute \src "libresoc.v:201207.3-201253.6" wire $1\core_stopped_i[0:0] - attribute \src "libresoc.v:197934.3-197946.6" + attribute \src "libresoc.v:200455.3-200467.6" wire width 3 $1\core_sv__ren[2:0] - attribute \src "libresoc.v:197338.3-197362.6" - wire $1\core_sv_a_nz$next[0:0]$13785 - attribute \src "libresoc.v:194901.7-194901.26" + attribute \src "libresoc.v:199699.3-199743.6" + wire $1\core_sv_a_nz$next[0:0]$13771 + attribute \src "libresoc.v:197350.7-197350.26" wire $1\core_sv_a_nz[0:0] - attribute \src "libresoc.v:197471.3-197480.6" - wire width 3 $1\core_wen$11[2:0]$13796 - attribute \src "libresoc.v:197947.3-198014.6" + attribute \src "libresoc.v:199936.3-199945.6" + wire width 3 $1\core_wen$11[2:0]$13782 + attribute \src "libresoc.v:200468.3-200547.6" wire width 3 $1\core_wen[2:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $1\core_xer_out$next[0:0]$14101 - attribute \src "libresoc.v:194911.7-194911.26" + attribute \src "libresoc.v:201555.3-201685.6" + wire $1\core_xer_out$next[0:0]$14087 + attribute \src "libresoc.v:197360.7-197360.26" wire $1\core_xer_out[0:0] - attribute \src "libresoc.v:194917.7-194917.30" + attribute \src "libresoc.v:197366.7-197366.30" wire $1\cu_st__rel_o_dly[0:0] - attribute \src "libresoc.v:198233.3-198271.6" - wire width 7 $1\cur_cur_dststep$next[6:0]$13885 - attribute \src "libresoc.v:194923.13-194923.36" + attribute \src "libresoc.v:200778.3-200816.6" + wire width 7 $1\cur_cur_dststep$next[6:0]$13871 + attribute \src "libresoc.v:197372.13-197372.36" wire width 7 $1\cur_cur_dststep[6:0] - attribute \src "libresoc.v:198233.3-198271.6" - wire width 7 $1\cur_cur_maxvl$next[6:0]$13886 - attribute \src "libresoc.v:194927.13-194927.34" + attribute \src "libresoc.v:200778.3-200816.6" + wire width 7 $1\cur_cur_maxvl$next[6:0]$13872 + attribute \src "libresoc.v:197376.13-197376.34" wire width 7 $1\cur_cur_maxvl[6:0] - attribute \src "libresoc.v:198233.3-198271.6" - wire width 7 $1\cur_cur_srcstep$next[6:0]$13887 - attribute \src "libresoc.v:194931.13-194931.36" + attribute \src "libresoc.v:200778.3-200816.6" + wire width 7 $1\cur_cur_srcstep$next[6:0]$13873 + attribute \src "libresoc.v:197380.13-197380.36" wire width 7 $1\cur_cur_srcstep[6:0] - attribute \src "libresoc.v:198233.3-198271.6" - wire width 2 $1\cur_cur_subvl$next[1:0]$13888 - attribute \src "libresoc.v:194935.13-194935.33" + attribute \src "libresoc.v:200778.3-200816.6" + wire width 2 $1\cur_cur_subvl$next[1:0]$13874 + attribute \src "libresoc.v:197384.13-197384.33" wire width 2 $1\cur_cur_subvl[1:0] - attribute \src "libresoc.v:198233.3-198271.6" - wire width 2 $1\cur_cur_svstep$next[1:0]$13889 - attribute \src "libresoc.v:194939.13-194939.34" + attribute \src "libresoc.v:200778.3-200816.6" + wire width 2 $1\cur_cur_svstep$next[1:0]$13875 + attribute \src "libresoc.v:197388.13-197388.34" wire width 2 $1\cur_cur_svstep[1:0] - attribute \src "libresoc.v:198233.3-198271.6" - wire width 7 $1\cur_cur_vl$next[6:0]$13890 - attribute \src "libresoc.v:194943.13-194943.31" + attribute \src "libresoc.v:200778.3-200816.6" + wire width 7 $1\cur_cur_vl$next[6:0]$13876 + attribute \src "libresoc.v:197392.13-197392.31" wire width 7 $1\cur_cur_vl[6:0] - attribute \src "libresoc.v:197653.3-197661.6" - wire $1\d_cr_delay$next[0:0]$13821 - attribute \src "libresoc.v:194947.7-194947.24" + attribute \src "libresoc.v:200122.3-200130.6" + wire $1\d_cr_delay$next[0:0]$13807 + attribute \src "libresoc.v:197396.7-197396.24" wire $1\d_cr_delay[0:0] - attribute \src "libresoc.v:197614.3-197622.6" - wire $1\d_reg_delay$next[0:0]$13815 - attribute \src "libresoc.v:194951.7-194951.25" + attribute \src "libresoc.v:200083.3-200091.6" + wire $1\d_reg_delay$next[0:0]$13801 + attribute \src "libresoc.v:197400.7-197400.25" wire $1\d_reg_delay[0:0] - attribute \src "libresoc.v:197692.3-197700.6" - wire $1\d_xer_delay$next[0:0]$13827 - attribute \src "libresoc.v:194955.7-194955.25" + attribute \src "libresoc.v:200161.3-200169.6" + wire $1\d_xer_delay$next[0:0]$13813 + attribute \src "libresoc.v:197404.7-197404.25" wire $1\d_xer_delay[0:0] - attribute \src "libresoc.v:198653.3-198683.6" + attribute \src "libresoc.v:201254.3-201300.6" wire $1\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:197672.3-197681.6" + attribute \src "libresoc.v:200141.3-200150.6" wire $1\dbg_d_cr_ack[0:0] - attribute \src "libresoc.v:197662.3-197671.6" + attribute \src "libresoc.v:200131.3-200140.6" wire width 64 $1\dbg_d_cr_data[63:0] - attribute \src "libresoc.v:197633.3-197642.6" + attribute \src "libresoc.v:200102.3-200111.6" wire $1\dbg_d_gpr_ack[0:0] - attribute \src "libresoc.v:197623.3-197632.6" + attribute \src "libresoc.v:200092.3-200101.6" wire width 64 $1\dbg_d_gpr_data[63:0] - attribute \src "libresoc.v:197711.3-197720.6" + attribute \src "libresoc.v:200180.3-200189.6" wire $1\dbg_d_xer_ack[0:0] - attribute \src "libresoc.v:197701.3-197710.6" + attribute \src "libresoc.v:200170.3-200179.6" wire width 64 $1\dbg_d_xer_data[63:0] - attribute \src "libresoc.v:197229.3-197237.6" - wire width 4 $1\dbg_dmi_addr_i$next[3:0]$13728 - attribute \src "libresoc.v:195003.13-195003.34" + attribute \src "libresoc.v:199546.3-199554.6" + wire width 4 $1\dbg_dmi_addr_i$next[3:0]$13714 + attribute \src "libresoc.v:197452.13-197452.34" wire width 4 $1\dbg_dmi_addr_i[3:0] - attribute \src "libresoc.v:198099.3-198107.6" - wire width 64 $1\dbg_dmi_din$next[63:0]$13865 - attribute \src "libresoc.v:195007.14-195007.48" + attribute \src "libresoc.v:200644.3-200652.6" + wire width 64 $1\dbg_dmi_din$next[63:0]$13851 + attribute \src "libresoc.v:197456.14-197456.48" wire width 64 $1\dbg_dmi_din[63:0] - attribute \src "libresoc.v:197238.3-197246.6" - wire $1\dbg_dmi_req_i$next[0:0]$13731 - attribute \src "libresoc.v:195013.7-195013.27" + attribute \src "libresoc.v:199555.3-199563.6" + wire $1\dbg_dmi_req_i$next[0:0]$13717 + attribute \src "libresoc.v:197462.7-197462.27" wire $1\dbg_dmi_req_i[0:0] - attribute \src "libresoc.v:197862.3-197870.6" - wire $1\dbg_dmi_we_i$next[0:0]$13849 - attribute \src "libresoc.v:195017.7-195017.26" + attribute \src "libresoc.v:200383.3-200391.6" + wire $1\dbg_dmi_we_i$next[0:0]$13835 + attribute \src "libresoc.v:197466.7-197466.26" wire $1\dbg_dmi_we_i[0:0] - attribute \src "libresoc.v:197835.3-197850.6" - wire width 64 $1\dec2_cur_dec$next[63:0]$13844 - attribute \src "libresoc.v:195071.14-195071.49" + attribute \src "libresoc.v:200340.3-200359.6" + wire width 64 $1\dec2_cur_dec$next[63:0]$13830 + attribute \src "libresoc.v:197520.14-197520.49" wire width 64 $1\dec2_cur_dec[63:0] - attribute \src "libresoc.v:198997.3-199005.6" - wire $1\dec2_cur_eint$next[0:0]$14190 - attribute \src "libresoc.v:195075.7-195075.27" + attribute \src "libresoc.v:201686.3-201694.6" + wire $1\dec2_cur_eint$next[0:0]$14176 + attribute \src "libresoc.v:197524.7-197524.27" wire $1\dec2_cur_eint[0:0] - attribute \src "libresoc.v:198365.3-198385.6" - wire width 64 $1\dec2_cur_msr$next[63:0]$13928 - attribute \src "libresoc.v:195079.14-195079.49" + attribute \src "libresoc.v:200910.3-200934.6" + wire width 64 $1\dec2_cur_msr$next[63:0]$13914 + attribute \src "libresoc.v:197528.14-197528.49" wire width 64 $1\dec2_cur_msr[63:0] - attribute \src "libresoc.v:198212.3-198232.6" - wire width 64 $1\dec2_cur_pc$next[63:0]$13875 - attribute \src "libresoc.v:195083.14-195083.48" + attribute \src "libresoc.v:200757.3-200777.6" + wire width 64 $1\dec2_cur_pc$next[63:0]$13861 + attribute \src "libresoc.v:197532.14-197532.48" wire width 64 $1\dec2_cur_pc[63:0] - attribute \src "libresoc.v:198405.3-198435.6" - wire width 32 $1\dec2_raw_opcode_in$next[31:0]$13937 - attribute \src "libresoc.v:195235.14-195235.40" + attribute \src "libresoc.v:200958.3-200992.6" + wire width 32 $1\dec2_raw_opcode_in$next[31:0]$13923 + attribute \src "libresoc.v:197684.14-197684.40" wire width 32 $1\dec2_raw_opcode_in[31:0] - attribute \src "libresoc.v:199006.3-199015.6" - wire width 2 $1\delay$next[1:0]$14193 - attribute \src "libresoc.v:195505.13-195505.25" + attribute \src "libresoc.v:201695.3-201704.6" + wire width 2 $1\delay$next[1:0]$14179 + attribute \src "libresoc.v:197954.13-197954.25" wire width 2 $1\delay[1:0] - attribute \src "libresoc.v:197543.3-197577.6" - wire $1\exec_fsm_state$next[0:0]$13805 - attribute \src "libresoc.v:195521.7-195521.28" + attribute \src "libresoc.v:200008.3-200042.6" + wire $1\exec_fsm_state$next[0:0]$13791 + attribute \src "libresoc.v:197970.7-197970.28" wire $1\exec_fsm_state[0:0] - attribute \src "libresoc.v:197491.3-197501.6" + attribute \src "libresoc.v:199956.3-199966.6" wire $1\exec_insn_ready_o[0:0] - attribute \src "libresoc.v:197423.3-197433.6" + attribute \src "libresoc.v:199832.3-199858.6" wire $1\exec_insn_valid_i[0:0] - attribute \src "libresoc.v:197434.3-197449.6" + attribute \src "libresoc.v:199859.3-199894.6" wire $1\exec_pc_ready_i[0:0] - attribute \src "libresoc.v:197578.3-197593.6" + attribute \src "libresoc.v:200043.3-200062.6" wire $1\exec_pc_valid_o[0:0] - attribute \src "libresoc.v:198311.3-198364.6" - wire width 2 $1\fetch_fsm_state$next[1:0]$13920 - attribute \src "libresoc.v:195533.13-195533.35" + attribute \src "libresoc.v:200856.3-200909.6" + wire width 2 $1\fetch_fsm_state$next[1:0]$13906 + attribute \src "libresoc.v:197982.13-197982.35" wire width 2 $1\fetch_fsm_state[1:0] - attribute \src "libresoc.v:198875.3-198885.6" + attribute \src "libresoc.v:201540.3-201554.6" wire $1\fetch_insn_ready_i[0:0] - attribute \src "libresoc.v:198436.3-198446.6" + attribute \src "libresoc.v:200993.3-201015.6" wire $1\fetch_insn_valid_o[0:0] - attribute \src "libresoc.v:198108.3-198118.6" + attribute \src "libresoc.v:200653.3-200663.6" wire $1\fetch_pc_ready_o[0:0] - attribute \src "libresoc.v:198507.3-198522.6" + attribute \src "libresoc.v:201092.3-201107.6" wire $1\fetch_pc_valid_i[0:0] - attribute \src "libresoc.v:197751.3-197778.6" - wire width 2 $1\fsm_state$next[1:0]$13834 - attribute \src "libresoc.v:195545.13-195545.29" + attribute \src "libresoc.v:200228.3-200255.6" + wire width 2 $1\fsm_state$next[1:0]$13820 + attribute \src "libresoc.v:197994.13-197994.29" wire width 2 $1\fsm_state[1:0] - attribute \src "libresoc.v:198119.3-198134.6" + attribute \src "libresoc.v:200664.3-200679.6" wire width 48 $1\imem_a_pc_i[47:0] - attribute \src "libresoc.v:198144.3-198177.6" + attribute \src "libresoc.v:200689.3-200722.6" wire $1\imem_a_valid_i[0:0] - attribute \src "libresoc.v:198178.3-198211.6" + attribute \src "libresoc.v:200723.3-200756.6" wire $1\imem_f_valid_i[0:0] - attribute \src "libresoc.v:197363.3-197400.6" + attribute \src "libresoc.v:199744.3-199789.6" wire $1\insn_done[0:0] - attribute \src "libresoc.v:197450.3-197470.6" + attribute \src "libresoc.v:199895.3-199935.6" wire $1\is_last[0:0] - attribute \src "libresoc.v:198523.3-198621.6" - wire width 3 $1\issue_fsm_state$next[2:0]$13945 - attribute \src "libresoc.v:195805.13-195805.35" + attribute \src "libresoc.v:201108.3-201206.6" + wire width 3 $1\issue_fsm_state$next[2:0]$13931 + attribute \src "libresoc.v:198254.13-198254.35" wire width 3 $1\issue_fsm_state[2:0] - attribute \src "libresoc.v:198135.3-198143.6" - wire $1\jtag_dmi0__ack_o$next[0:0]$13870 - attribute \src "libresoc.v:195809.7-195809.30" + attribute \src "libresoc.v:200680.3-200688.6" + wire $1\jtag_dmi0__ack_o$next[0:0]$13856 + attribute \src "libresoc.v:198258.7-198258.30" wire $1\jtag_dmi0__ack_o[0:0] - attribute \src "libresoc.v:198302.3-198310.6" - wire width 64 $1\jtag_dmi0__dout$next[63:0]$13917 - attribute \src "libresoc.v:195817.14-195817.52" + attribute \src "libresoc.v:200847.3-200855.6" + wire width 64 $1\jtag_dmi0__dout$next[63:0]$13903 + attribute \src "libresoc.v:198266.14-198266.52" wire width 64 $1\jtag_dmi0__dout[63:0] - attribute \src "libresoc.v:198272.3-198301.6" - wire $1\msr_read$next[0:0]$13911 - attribute \src "libresoc.v:195873.7-195873.22" + attribute \src "libresoc.v:200817.3-200846.6" + wire $1\msr_read$next[0:0]$13897 + attribute \src "libresoc.v:198306.7-198306.22" wire $1\msr_read[0:0] - attribute \src "libresoc.v:197779.3-197789.6" + attribute \src "libresoc.v:200256.3-200270.6" wire width 64 $1\new_dec[63:0] - attribute \src "libresoc.v:198447.3-198506.6" + attribute \src "libresoc.v:201016.3-201091.6" wire width 7 $1\new_svstate_dststep[6:0] - attribute \src "libresoc.v:198447.3-198506.6" + attribute \src "libresoc.v:201016.3-201091.6" wire width 7 $1\new_svstate_maxvl[6:0] - attribute \src "libresoc.v:198447.3-198506.6" + attribute \src "libresoc.v:201016.3-201091.6" wire width 7 $1\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:198447.3-198506.6" + attribute \src "libresoc.v:201016.3-201091.6" wire width 2 $1\new_svstate_subvl[1:0] - attribute \src "libresoc.v:198447.3-198506.6" + attribute \src "libresoc.v:201016.3-201091.6" wire width 2 $1\new_svstate_svstep[1:0] - attribute \src "libresoc.v:198447.3-198506.6" + attribute \src "libresoc.v:201016.3-201091.6" wire width 7 $1\new_svstate_vl[6:0] - attribute \src "libresoc.v:197851.3-197861.6" + attribute \src "libresoc.v:200360.3-200382.6" wire width 64 $1\new_tb[63:0] - attribute \src "libresoc.v:198386.3-198404.6" - wire width 64 $1\nia$next[63:0]$13933 - attribute \src "libresoc.v:195913.14-195913.40" + attribute \src "libresoc.v:200935.3-200957.6" + wire width 64 $1\nia$next[63:0]$13919 + attribute \src "libresoc.v:198346.14-198346.40" wire width 64 $1\nia[63:0] - attribute \src "libresoc.v:197880.3-197895.6" + attribute \src "libresoc.v:200401.3-200416.6" wire width 64 $1\pc[63:0] - attribute \src "libresoc.v:198684.3-198750.6" - wire $1\pc_changed$next[0:0]$13961 - attribute \src "libresoc.v:195919.7-195919.24" + attribute \src "libresoc.v:201301.3-201383.6" + wire $1\pc_changed$next[0:0]$13947 + attribute \src "libresoc.v:198352.7-198352.24" wire $1\pc_changed[0:0] - attribute \src "libresoc.v:197871.3-197879.6" - wire $1\pc_ok_delay$next[0:0]$13852 - attribute \src "libresoc.v:195929.7-195929.25" + attribute \src "libresoc.v:200392.3-200400.6" + wire $1\pc_ok_delay$next[0:0]$13838 + attribute \src "libresoc.v:198362.7-198362.25" wire $1\pc_ok_delay[0:0] - attribute \src "libresoc.v:197401.3-197411.6" + attribute \src "libresoc.v:199790.3-199808.6" wire $1\pred_insn_valid_i[0:0] - attribute \src "libresoc.v:197412.3-197422.6" + attribute \src "libresoc.v:199809.3-199831.6" wire $1\pred_mask_ready_i[0:0] - attribute \src "libresoc.v:198808.3-198874.6" - wire $1\sv_changed$next[0:0]$13973 - attribute \src "libresoc.v:196301.7-196301.24" + attribute \src "libresoc.v:201457.3-201539.6" + wire $1\sv_changed$next[0:0]$13959 + attribute \src "libresoc.v:198662.7-198662.24" wire $1\sv_changed[0:0] - attribute \src "libresoc.v:197918.3-197933.6" + attribute \src "libresoc.v:200439.3-200454.6" wire width 64 $1\svstate[63:0] - attribute \src "libresoc.v:197909.3-197917.6" - wire $1\svstate_ok_delay$next[0:0]$13857 - attribute \src "libresoc.v:196311.7-196311.30" + attribute \src "libresoc.v:200430.3-200438.6" + wire $1\svstate_ok_delay$next[0:0]$13843 + attribute \src "libresoc.v:198672.7-198672.30" wire $1\svstate_ok_delay[0:0] - attribute \src "libresoc.v:198751.3-198807.6" + attribute \src "libresoc.v:201384.3-201456.6" wire $1\update_svstate[0:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire width 8 $2\core_asmcode$next[7:0]$14102 - attribute \src "libresoc.v:197313.3-197337.6" - wire $2\core_bigendian_i$10$next[0:0]$13781 - attribute \src "libresoc.v:198886.3-198996.6" - wire width 64 $2\core_core_core_cia$next[63:0]$14103 - attribute \src "libresoc.v:198886.3-198996.6" - wire width 8 $2\core_core_core_cr_rd$next[7:0]$14104 - attribute \src "libresoc.v:198886.3-198996.6" - wire $2\core_core_core_cr_rd_ok$next[0:0]$14105 - attribute \src "libresoc.v:198886.3-198996.6" - wire width 8 $2\core_core_core_cr_wr$next[7:0]$14106 - attribute \src "libresoc.v:198886.3-198996.6" - wire $2\core_core_core_exc_$signal$3$next[0:0]$14107 - attribute \src "libresoc.v:198886.3-198996.6" - wire $2\core_core_core_exc_$signal$4$next[0:0]$14108 - attribute \src "libresoc.v:198886.3-198996.6" - wire $2\core_core_core_exc_$signal$5$next[0:0]$14109 - attribute \src "libresoc.v:198886.3-198996.6" - wire $2\core_core_core_exc_$signal$6$next[0:0]$14110 - attribute \src "libresoc.v:198886.3-198996.6" - wire $2\core_core_core_exc_$signal$7$next[0:0]$14111 - attribute \src "libresoc.v:198886.3-198996.6" - wire $2\core_core_core_exc_$signal$8$next[0:0]$14112 - attribute \src "libresoc.v:198886.3-198996.6" - wire $2\core_core_core_exc_$signal$9$next[0:0]$14113 - attribute \src "libresoc.v:198886.3-198996.6" - wire $2\core_core_core_exc_$signal$next[0:0]$14114 - attribute \src "libresoc.v:198886.3-198996.6" - wire width 14 $2\core_core_core_fn_unit$next[13:0]$14115 - attribute \src "libresoc.v:198886.3-198996.6" - wire width 2 $2\core_core_core_input_carry$next[1:0]$14116 - attribute \src "libresoc.v:198886.3-198996.6" - wire width 32 $2\core_core_core_insn$next[31:0]$14117 - attribute \src "libresoc.v:198886.3-198996.6" - wire width 7 $2\core_core_core_insn_type$next[6:0]$14118 - attribute \src "libresoc.v:198886.3-198996.6" - wire $2\core_core_core_is_32bit$next[0:0]$14119 - attribute \src "libresoc.v:198886.3-198996.6" - wire width 64 $2\core_core_core_msr$next[63:0]$14120 - attribute \src "libresoc.v:198886.3-198996.6" - wire $2\core_core_core_oe$next[0:0]$14121 - attribute \src "libresoc.v:198886.3-198996.6" - wire $2\core_core_core_oe_ok$next[0:0]$14122 - attribute \src "libresoc.v:198886.3-198996.6" - wire $2\core_core_core_rc$next[0:0]$14123 - attribute \src "libresoc.v:198886.3-198996.6" - wire $2\core_core_core_rc_ok$next[0:0]$14124 - attribute \src "libresoc.v:198886.3-198996.6" - wire width 13 $2\core_core_core_trapaddr$next[12:0]$14125 - attribute \src "libresoc.v:198886.3-198996.6" - wire width 8 $2\core_core_core_traptype$next[7:0]$14126 - attribute \src "libresoc.v:198886.3-198996.6" - wire width 7 $2\core_core_cr_in1$next[6:0]$14127 - attribute \src "libresoc.v:198886.3-198996.6" - wire $2\core_core_cr_in1_ok$next[0:0]$14128 - attribute \src "libresoc.v:198886.3-198996.6" - wire width 7 $2\core_core_cr_in2$1$next[6:0]$14129 - attribute \src "libresoc.v:198886.3-198996.6" - wire width 7 $2\core_core_cr_in2$next[6:0]$14130 - attribute \src "libresoc.v:198886.3-198996.6" - wire $2\core_core_cr_in2_ok$2$next[0:0]$14131 - attribute \src "libresoc.v:198886.3-198996.6" - wire $2\core_core_cr_in2_ok$next[0:0]$14132 - attribute \src "libresoc.v:198886.3-198996.6" - wire width 7 $2\core_core_cr_out$next[6:0]$14133 - attribute \src "libresoc.v:198886.3-198996.6" - wire $2\core_core_cr_wr_ok$next[0:0]$14134 - attribute \src "libresoc.v:197247.3-197291.6" - wire width 7 $2\core_core_dststep$next[6:0]$13753 - attribute \src "libresoc.v:198886.3-198996.6" - wire width 7 $2\core_core_ea$next[6:0]$14135 - attribute \src "libresoc.v:198886.3-198996.6" - wire width 3 $2\core_core_fast1$next[2:0]$14136 - attribute \src "libresoc.v:198886.3-198996.6" - wire $2\core_core_fast1_ok$next[0:0]$14137 - attribute \src "libresoc.v:198886.3-198996.6" - wire width 3 $2\core_core_fast2$next[2:0]$14138 - attribute \src "libresoc.v:198886.3-198996.6" - wire $2\core_core_fast2_ok$next[0:0]$14139 - attribute \src "libresoc.v:198886.3-198996.6" - wire width 3 $2\core_core_fasto1$next[2:0]$14140 - attribute \src "libresoc.v:198886.3-198996.6" - wire width 3 $2\core_core_fasto2$next[2:0]$14141 - attribute \src "libresoc.v:198886.3-198996.6" - wire $2\core_core_lk$next[0:0]$14142 - attribute \src "libresoc.v:197247.3-197291.6" - wire width 7 $2\core_core_maxvl$next[6:0]$13754 - attribute \src "libresoc.v:197247.3-197291.6" - wire width 64 $2\core_core_pc$next[63:0]$13755 - attribute \src "libresoc.v:198886.3-198996.6" - wire width 7 $2\core_core_reg1$next[6:0]$14143 - attribute \src "libresoc.v:198886.3-198996.6" - wire $2\core_core_reg1_ok$next[0:0]$14144 - attribute \src "libresoc.v:198886.3-198996.6" - wire width 7 $2\core_core_reg2$next[6:0]$14145 - attribute \src "libresoc.v:198886.3-198996.6" - wire $2\core_core_reg2_ok$next[0:0]$14146 - attribute \src "libresoc.v:198886.3-198996.6" - wire width 7 $2\core_core_reg3$next[6:0]$14147 - attribute \src "libresoc.v:198886.3-198996.6" - wire $2\core_core_reg3_ok$next[0:0]$14148 - attribute \src "libresoc.v:198886.3-198996.6" - wire width 7 $2\core_core_rego$next[6:0]$14149 - attribute \src "libresoc.v:198886.3-198996.6" - wire width 10 $2\core_core_spr1$next[9:0]$14150 - attribute \src "libresoc.v:198886.3-198996.6" - wire $2\core_core_spr1_ok$next[0:0]$14151 - attribute \src "libresoc.v:198886.3-198996.6" - wire width 10 $2\core_core_spro$next[9:0]$14152 - attribute \src "libresoc.v:197247.3-197291.6" - wire width 7 $2\core_core_srcstep$next[6:0]$13756 - attribute \src "libresoc.v:197247.3-197291.6" - wire width 2 $2\core_core_subvl$next[1:0]$13757 - attribute \src "libresoc.v:197247.3-197291.6" - wire width 2 $2\core_core_svstep$next[1:0]$13758 - attribute \src "libresoc.v:197247.3-197291.6" - wire width 7 $2\core_core_vl$next[6:0]$13759 - attribute \src "libresoc.v:198886.3-198996.6" - wire width 3 $2\core_core_xer_in$next[2:0]$14153 - attribute \src "libresoc.v:198886.3-198996.6" - wire $2\core_cr_out_ok$next[0:0]$14154 - attribute \src "libresoc.v:198015.3-198082.6" + attribute \src "libresoc.v:201555.3-201685.6" + wire width 8 $2\core_asmcode$next[7:0]$14088 + attribute \src "libresoc.v:199654.3-199698.6" + wire $2\core_bigendian_i$10$next[0:0]$13767 + attribute \src "libresoc.v:201555.3-201685.6" + wire width 64 $2\core_core_core_cia$next[63:0]$14089 + attribute \src "libresoc.v:201555.3-201685.6" + wire width 8 $2\core_core_core_cr_rd$next[7:0]$14090 + attribute \src "libresoc.v:201555.3-201685.6" + wire $2\core_core_core_cr_rd_ok$next[0:0]$14091 + attribute \src "libresoc.v:201555.3-201685.6" + wire width 8 $2\core_core_core_cr_wr$next[7:0]$14092 + attribute \src "libresoc.v:201555.3-201685.6" + wire $2\core_core_core_exc_$signal$3$next[0:0]$14093 + attribute \src "libresoc.v:201555.3-201685.6" + wire $2\core_core_core_exc_$signal$4$next[0:0]$14094 + attribute \src "libresoc.v:201555.3-201685.6" + wire $2\core_core_core_exc_$signal$5$next[0:0]$14095 + attribute \src "libresoc.v:201555.3-201685.6" + wire $2\core_core_core_exc_$signal$6$next[0:0]$14096 + attribute \src "libresoc.v:201555.3-201685.6" + wire $2\core_core_core_exc_$signal$7$next[0:0]$14097 + attribute \src "libresoc.v:201555.3-201685.6" + wire $2\core_core_core_exc_$signal$8$next[0:0]$14098 + attribute \src "libresoc.v:201555.3-201685.6" + wire $2\core_core_core_exc_$signal$9$next[0:0]$14099 + attribute \src "libresoc.v:201555.3-201685.6" + wire $2\core_core_core_exc_$signal$next[0:0]$14100 + attribute \src "libresoc.v:201555.3-201685.6" + wire width 14 $2\core_core_core_fn_unit$next[13:0]$14101 + attribute \src "libresoc.v:201555.3-201685.6" + wire width 2 $2\core_core_core_input_carry$next[1:0]$14102 + attribute \src "libresoc.v:201555.3-201685.6" + wire width 32 $2\core_core_core_insn$next[31:0]$14103 + attribute \src "libresoc.v:201555.3-201685.6" + wire width 7 $2\core_core_core_insn_type$next[6:0]$14104 + attribute \src "libresoc.v:201555.3-201685.6" + wire $2\core_core_core_is_32bit$next[0:0]$14105 + attribute \src "libresoc.v:201555.3-201685.6" + wire width 64 $2\core_core_core_msr$next[63:0]$14106 + attribute \src "libresoc.v:201555.3-201685.6" + wire $2\core_core_core_oe$next[0:0]$14107 + attribute \src "libresoc.v:201555.3-201685.6" + wire $2\core_core_core_oe_ok$next[0:0]$14108 + attribute \src "libresoc.v:201555.3-201685.6" + wire $2\core_core_core_rc$next[0:0]$14109 + attribute \src "libresoc.v:201555.3-201685.6" + wire $2\core_core_core_rc_ok$next[0:0]$14110 + attribute \src "libresoc.v:201555.3-201685.6" + wire width 13 $2\core_core_core_trapaddr$next[12:0]$14111 + attribute \src "libresoc.v:201555.3-201685.6" + wire width 8 $2\core_core_core_traptype$next[7:0]$14112 + attribute \src "libresoc.v:201555.3-201685.6" + wire width 7 $2\core_core_cr_in1$next[6:0]$14113 + attribute \src "libresoc.v:201555.3-201685.6" + wire $2\core_core_cr_in1_ok$next[0:0]$14114 + attribute \src "libresoc.v:201555.3-201685.6" + wire width 7 $2\core_core_cr_in2$1$next[6:0]$14115 + attribute \src "libresoc.v:201555.3-201685.6" + wire width 7 $2\core_core_cr_in2$next[6:0]$14116 + attribute \src "libresoc.v:201555.3-201685.6" + wire $2\core_core_cr_in2_ok$2$next[0:0]$14117 + attribute \src "libresoc.v:201555.3-201685.6" + wire $2\core_core_cr_in2_ok$next[0:0]$14118 + attribute \src "libresoc.v:201555.3-201685.6" + wire width 7 $2\core_core_cr_out$next[6:0]$14119 + attribute \src "libresoc.v:201555.3-201685.6" + wire $2\core_core_cr_wr_ok$next[0:0]$14120 + attribute \src "libresoc.v:199564.3-199628.6" + wire width 7 $2\core_core_dststep$next[6:0]$13739 + attribute \src "libresoc.v:201555.3-201685.6" + wire width 7 $2\core_core_ea$next[6:0]$14121 + attribute \src "libresoc.v:201555.3-201685.6" + wire width 3 $2\core_core_fast1$next[2:0]$14122 + attribute \src "libresoc.v:201555.3-201685.6" + wire $2\core_core_fast1_ok$next[0:0]$14123 + attribute \src "libresoc.v:201555.3-201685.6" + wire width 3 $2\core_core_fast2$next[2:0]$14124 + attribute \src "libresoc.v:201555.3-201685.6" + wire $2\core_core_fast2_ok$next[0:0]$14125 + attribute \src "libresoc.v:201555.3-201685.6" + wire width 3 $2\core_core_fasto1$next[2:0]$14126 + attribute \src "libresoc.v:201555.3-201685.6" + wire width 3 $2\core_core_fasto2$next[2:0]$14127 + attribute \src "libresoc.v:201555.3-201685.6" + wire $2\core_core_lk$next[0:0]$14128 + attribute \src "libresoc.v:199564.3-199628.6" + wire width 7 $2\core_core_maxvl$next[6:0]$13740 + attribute \src "libresoc.v:199564.3-199628.6" + wire width 64 $2\core_core_pc$next[63:0]$13741 + attribute \src "libresoc.v:201555.3-201685.6" + wire width 7 $2\core_core_reg1$next[6:0]$14129 + attribute \src "libresoc.v:201555.3-201685.6" + wire $2\core_core_reg1_ok$next[0:0]$14130 + attribute \src "libresoc.v:201555.3-201685.6" + wire width 7 $2\core_core_reg2$next[6:0]$14131 + attribute \src "libresoc.v:201555.3-201685.6" + wire $2\core_core_reg2_ok$next[0:0]$14132 + attribute \src "libresoc.v:201555.3-201685.6" + wire width 7 $2\core_core_reg3$next[6:0]$14133 + attribute \src "libresoc.v:201555.3-201685.6" + wire $2\core_core_reg3_ok$next[0:0]$14134 + attribute \src "libresoc.v:201555.3-201685.6" + wire width 7 $2\core_core_rego$next[6:0]$14135 + attribute \src "libresoc.v:201555.3-201685.6" + wire width 10 $2\core_core_spr1$next[9:0]$14136 + attribute \src "libresoc.v:201555.3-201685.6" + wire $2\core_core_spr1_ok$next[0:0]$14137 + attribute \src "libresoc.v:201555.3-201685.6" + wire width 10 $2\core_core_spro$next[9:0]$14138 + attribute \src "libresoc.v:199564.3-199628.6" + wire width 7 $2\core_core_srcstep$next[6:0]$13742 + attribute \src "libresoc.v:199564.3-199628.6" + wire width 2 $2\core_core_subvl$next[1:0]$13743 + attribute \src "libresoc.v:199564.3-199628.6" + wire width 2 $2\core_core_svstep$next[1:0]$13744 + attribute \src "libresoc.v:199564.3-199628.6" + wire width 7 $2\core_core_vl$next[6:0]$13745 + attribute \src "libresoc.v:201555.3-201685.6" + wire width 3 $2\core_core_xer_in$next[2:0]$14139 + attribute \src "libresoc.v:201555.3-201685.6" + wire $2\core_cr_out_ok$next[0:0]$14140 + attribute \src "libresoc.v:200548.3-200627.6" wire width 64 $2\core_data_i[63:0] - attribute \src "libresoc.v:197247.3-197291.6" - wire width 64 $2\core_dec$next[63:0]$13760 - attribute \src "libresoc.v:198886.3-198996.6" - wire $2\core_ea_ok$next[0:0]$14155 - attribute \src "libresoc.v:197247.3-197291.6" - wire $2\core_eint$next[0:0]$13761 - attribute \src "libresoc.v:198886.3-198996.6" - wire $2\core_fasto1_ok$next[0:0]$14156 - attribute \src "libresoc.v:198886.3-198996.6" - wire $2\core_fasto2_ok$next[0:0]$14157 - attribute \src "libresoc.v:197527.3-197542.6" + attribute \src "libresoc.v:199564.3-199628.6" + wire width 64 $2\core_dec$next[63:0]$13746 + attribute \src "libresoc.v:201555.3-201685.6" + wire $2\core_ea_ok$next[0:0]$14141 + attribute \src "libresoc.v:199564.3-199628.6" + wire $2\core_eint$next[0:0]$13747 + attribute \src "libresoc.v:201555.3-201685.6" + wire $2\core_fasto1_ok$next[0:0]$14142 + attribute \src "libresoc.v:201555.3-201685.6" + wire $2\core_fasto2_ok$next[0:0]$14143 + attribute \src "libresoc.v:199992.3-200007.6" wire $2\core_issue_i[0:0] - attribute \src "libresoc.v:197502.3-197526.6" + attribute \src "libresoc.v:199967.3-199991.6" wire $2\core_ivalid_i[0:0] - attribute \src "libresoc.v:197247.3-197291.6" - wire width 64 $2\core_msr$next[63:0]$13762 - attribute \src "libresoc.v:198083.3-198098.6" + attribute \src "libresoc.v:199564.3-199628.6" + wire width 64 $2\core_msr$next[63:0]$13748 + attribute \src "libresoc.v:200628.3-200643.6" wire width 3 $2\core_msr__ren[2:0] - attribute \src "libresoc.v:197292.3-197312.6" - wire width 32 $2\core_raw_insn_i$next[31:0]$13776 - attribute \src "libresoc.v:198886.3-198996.6" - wire $2\core_rego_ok$next[0:0]$14158 - attribute \src "libresoc.v:198886.3-198996.6" - wire $2\core_spro_ok$next[0:0]$14159 - attribute \src "libresoc.v:198622.3-198652.6" + attribute \src "libresoc.v:199629.3-199653.6" + wire width 32 $2\core_raw_insn_i$next[31:0]$13762 + attribute \src "libresoc.v:201555.3-201685.6" + wire $2\core_rego_ok$next[0:0]$14144 + attribute \src "libresoc.v:201555.3-201685.6" + wire $2\core_spro_ok$next[0:0]$14145 + attribute \src "libresoc.v:201207.3-201253.6" wire $2\core_stopped_i[0:0] - attribute \src "libresoc.v:197338.3-197362.6" - wire $2\core_sv_a_nz$next[0:0]$13786 - attribute \src "libresoc.v:197947.3-198014.6" + attribute \src "libresoc.v:199699.3-199743.6" + wire $2\core_sv_a_nz$next[0:0]$13772 + attribute \src "libresoc.v:200468.3-200547.6" wire width 3 $2\core_wen[2:0] - attribute \src "libresoc.v:198886.3-198996.6" - wire $2\core_xer_out$next[0:0]$14160 - attribute \src "libresoc.v:198233.3-198271.6" - wire width 7 $2\cur_cur_dststep$next[6:0]$13891 - attribute \src "libresoc.v:198233.3-198271.6" - wire width 7 $2\cur_cur_maxvl$next[6:0]$13892 - attribute \src "libresoc.v:198233.3-198271.6" - wire width 7 $2\cur_cur_srcstep$next[6:0]$13893 - attribute \src "libresoc.v:198233.3-198271.6" - wire width 2 $2\cur_cur_subvl$next[1:0]$13894 - attribute \src "libresoc.v:198233.3-198271.6" - wire width 2 $2\cur_cur_svstep$next[1:0]$13895 - attribute \src "libresoc.v:198233.3-198271.6" - wire width 7 $2\cur_cur_vl$next[6:0]$13896 - attribute \src "libresoc.v:198653.3-198683.6" + attribute \src "libresoc.v:201555.3-201685.6" + wire $2\core_xer_out$next[0:0]$14146 + attribute \src "libresoc.v:200778.3-200816.6" + wire width 7 $2\cur_cur_dststep$next[6:0]$13877 + attribute \src "libresoc.v:200778.3-200816.6" + wire width 7 $2\cur_cur_maxvl$next[6:0]$13878 + attribute \src "libresoc.v:200778.3-200816.6" + wire width 7 $2\cur_cur_srcstep$next[6:0]$13879 + attribute \src "libresoc.v:200778.3-200816.6" + wire width 2 $2\cur_cur_subvl$next[1:0]$13880 + attribute \src "libresoc.v:200778.3-200816.6" + wire width 2 $2\cur_cur_svstep$next[1:0]$13881 + attribute \src "libresoc.v:200778.3-200816.6" + wire width 7 $2\cur_cur_vl$next[6:0]$13882 + attribute \src "libresoc.v:201254.3-201300.6" wire $2\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:197835.3-197850.6" - wire width 64 $2\dec2_cur_dec$next[63:0]$13845 - attribute \src "libresoc.v:198365.3-198385.6" - wire width 64 $2\dec2_cur_msr$next[63:0]$13929 - attribute \src "libresoc.v:198212.3-198232.6" - wire width 64 $2\dec2_cur_pc$next[63:0]$13876 - attribute \src "libresoc.v:198405.3-198435.6" - wire width 32 $2\dec2_raw_opcode_in$next[31:0]$13938 - attribute \src "libresoc.v:197543.3-197577.6" - wire $2\exec_fsm_state$next[0:0]$13806 - attribute \src "libresoc.v:197434.3-197449.6" + attribute \src "libresoc.v:200340.3-200359.6" + wire width 64 $2\dec2_cur_dec$next[63:0]$13831 + attribute \src "libresoc.v:200910.3-200934.6" + wire width 64 $2\dec2_cur_msr$next[63:0]$13915 + attribute \src "libresoc.v:200757.3-200777.6" + wire width 64 $2\dec2_cur_pc$next[63:0]$13862 + attribute \src "libresoc.v:200958.3-200992.6" + wire width 32 $2\dec2_raw_opcode_in$next[31:0]$13924 + attribute \src "libresoc.v:200008.3-200042.6" + wire $2\exec_fsm_state$next[0:0]$13792 + attribute \src "libresoc.v:199859.3-199894.6" wire $2\exec_pc_ready_i[0:0] - attribute \src "libresoc.v:197578.3-197593.6" + attribute \src "libresoc.v:200043.3-200062.6" wire $2\exec_pc_valid_o[0:0] - attribute \src "libresoc.v:198311.3-198364.6" - wire width 2 $2\fetch_fsm_state$next[1:0]$13921 - attribute \src "libresoc.v:198507.3-198522.6" + attribute \src "libresoc.v:200856.3-200909.6" + wire width 2 $2\fetch_fsm_state$next[1:0]$13907 + attribute \src "libresoc.v:201092.3-201107.6" wire $2\fetch_pc_valid_i[0:0] - attribute \src "libresoc.v:197751.3-197778.6" - wire width 2 $2\fsm_state$next[1:0]$13835 - attribute \src "libresoc.v:198119.3-198134.6" + attribute \src "libresoc.v:200228.3-200255.6" + wire width 2 $2\fsm_state$next[1:0]$13821 + attribute \src "libresoc.v:200664.3-200679.6" wire width 48 $2\imem_a_pc_i[47:0] - attribute \src "libresoc.v:198144.3-198177.6" + attribute \src "libresoc.v:200689.3-200722.6" wire $2\imem_a_valid_i[0:0] - attribute \src "libresoc.v:198178.3-198211.6" + attribute \src "libresoc.v:200723.3-200756.6" wire $2\imem_f_valid_i[0:0] - attribute \src "libresoc.v:197363.3-197400.6" + attribute \src "libresoc.v:199744.3-199789.6" wire $2\insn_done[0:0] - attribute \src "libresoc.v:197450.3-197470.6" + attribute \src "libresoc.v:199895.3-199935.6" wire $2\is_last[0:0] - attribute \src "libresoc.v:198523.3-198621.6" - wire width 3 $2\issue_fsm_state$next[2:0]$13946 - attribute \src "libresoc.v:198272.3-198301.6" - wire $2\msr_read$next[0:0]$13912 - attribute \src "libresoc.v:198447.3-198506.6" + attribute \src "libresoc.v:201108.3-201206.6" + wire width 3 $2\issue_fsm_state$next[2:0]$13932 + attribute \src "libresoc.v:200817.3-200846.6" + wire $2\msr_read$next[0:0]$13898 + attribute \src "libresoc.v:201016.3-201091.6" wire width 7 $2\new_svstate_dststep[6:0] - attribute \src "libresoc.v:198447.3-198506.6" + attribute \src "libresoc.v:201016.3-201091.6" wire width 7 $2\new_svstate_maxvl[6:0] - attribute \src "libresoc.v:198447.3-198506.6" + attribute \src "libresoc.v:201016.3-201091.6" wire width 7 $2\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:198447.3-198506.6" + attribute \src "libresoc.v:201016.3-201091.6" wire width 2 $2\new_svstate_subvl[1:0] - attribute \src "libresoc.v:198447.3-198506.6" + attribute \src "libresoc.v:201016.3-201091.6" wire width 2 $2\new_svstate_svstep[1:0] - attribute \src "libresoc.v:198447.3-198506.6" + attribute \src "libresoc.v:201016.3-201091.6" wire width 7 $2\new_svstate_vl[6:0] - attribute \src "libresoc.v:198386.3-198404.6" - wire width 64 $2\nia$next[63:0]$13934 - attribute \src "libresoc.v:197880.3-197895.6" + attribute \src "libresoc.v:200935.3-200957.6" + wire width 64 $2\nia$next[63:0]$13920 + attribute \src "libresoc.v:200401.3-200416.6" wire width 64 $2\pc[63:0] - attribute \src "libresoc.v:198684.3-198750.6" - wire $2\pc_changed$next[0:0]$13962 - attribute \src "libresoc.v:198808.3-198874.6" - wire $2\sv_changed$next[0:0]$13974 - attribute \src "libresoc.v:197918.3-197933.6" + attribute \src "libresoc.v:201301.3-201383.6" + wire $2\pc_changed$next[0:0]$13948 + attribute \src "libresoc.v:201457.3-201539.6" + wire $2\sv_changed$next[0:0]$13960 + attribute \src "libresoc.v:200439.3-200454.6" wire width 64 $2\svstate[63:0] - attribute \src "libresoc.v:198751.3-198807.6" + attribute \src "libresoc.v:201384.3-201456.6" wire $2\update_svstate[0:0] - attribute \src "libresoc.v:197313.3-197337.6" - wire $3\core_bigendian_i$10$next[0:0]$13782 - attribute \src "libresoc.v:198886.3-198996.6" - wire $3\core_core_core_cr_rd_ok$next[0:0]$14161 - attribute \src "libresoc.v:198886.3-198996.6" - wire $3\core_core_core_exc_$signal$3$next[0:0]$14162 - attribute \src "libresoc.v:198886.3-198996.6" - wire $3\core_core_core_exc_$signal$4$next[0:0]$14163 - attribute \src "libresoc.v:198886.3-198996.6" - wire $3\core_core_core_exc_$signal$5$next[0:0]$14164 - attribute \src "libresoc.v:198886.3-198996.6" - wire $3\core_core_core_exc_$signal$6$next[0:0]$14165 - attribute \src "libresoc.v:198886.3-198996.6" - wire $3\core_core_core_exc_$signal$7$next[0:0]$14166 - attribute \src "libresoc.v:198886.3-198996.6" - wire $3\core_core_core_exc_$signal$8$next[0:0]$14167 - attribute \src "libresoc.v:198886.3-198996.6" - wire $3\core_core_core_exc_$signal$9$next[0:0]$14168 - attribute \src "libresoc.v:198886.3-198996.6" - wire $3\core_core_core_exc_$signal$next[0:0]$14169 - attribute \src "libresoc.v:198886.3-198996.6" - wire $3\core_core_core_oe_ok$next[0:0]$14170 - attribute \src "libresoc.v:198886.3-198996.6" - wire $3\core_core_core_rc_ok$next[0:0]$14171 - attribute \src "libresoc.v:198886.3-198996.6" - wire $3\core_core_cr_in1_ok$next[0:0]$14172 - attribute \src "libresoc.v:198886.3-198996.6" - wire $3\core_core_cr_in2_ok$2$next[0:0]$14173 - attribute \src "libresoc.v:198886.3-198996.6" - wire $3\core_core_cr_in2_ok$next[0:0]$14174 - attribute \src "libresoc.v:198886.3-198996.6" - wire $3\core_core_cr_wr_ok$next[0:0]$14175 - attribute \src "libresoc.v:197247.3-197291.6" - wire width 7 $3\core_core_dststep$next[6:0]$13763 - attribute \src "libresoc.v:198886.3-198996.6" - wire $3\core_core_fast1_ok$next[0:0]$14176 - attribute \src "libresoc.v:198886.3-198996.6" - wire $3\core_core_fast2_ok$next[0:0]$14177 - attribute \src "libresoc.v:197247.3-197291.6" - wire width 7 $3\core_core_maxvl$next[6:0]$13764 - attribute \src "libresoc.v:197247.3-197291.6" - wire width 64 $3\core_core_pc$next[63:0]$13765 - attribute \src "libresoc.v:198886.3-198996.6" - wire $3\core_core_reg1_ok$next[0:0]$14178 - attribute \src "libresoc.v:198886.3-198996.6" - wire $3\core_core_reg2_ok$next[0:0]$14179 - attribute \src "libresoc.v:198886.3-198996.6" - wire $3\core_core_reg3_ok$next[0:0]$14180 - attribute \src "libresoc.v:198886.3-198996.6" - wire $3\core_core_spr1_ok$next[0:0]$14181 - attribute \src "libresoc.v:197247.3-197291.6" - wire width 7 $3\core_core_srcstep$next[6:0]$13766 - attribute \src "libresoc.v:197247.3-197291.6" - wire width 2 $3\core_core_subvl$next[1:0]$13767 - attribute \src "libresoc.v:197247.3-197291.6" - wire width 2 $3\core_core_svstep$next[1:0]$13768 - attribute \src "libresoc.v:197247.3-197291.6" - wire width 7 $3\core_core_vl$next[6:0]$13769 - attribute \src "libresoc.v:198886.3-198996.6" - wire $3\core_cr_out_ok$next[0:0]$14182 - attribute \src "libresoc.v:198015.3-198082.6" + attribute \src "libresoc.v:199654.3-199698.6" + wire $3\core_bigendian_i$10$next[0:0]$13768 + attribute \src "libresoc.v:201555.3-201685.6" + wire $3\core_core_core_cr_rd_ok$next[0:0]$14147 + attribute \src "libresoc.v:201555.3-201685.6" + wire $3\core_core_core_exc_$signal$3$next[0:0]$14148 + attribute \src "libresoc.v:201555.3-201685.6" + wire $3\core_core_core_exc_$signal$4$next[0:0]$14149 + attribute \src "libresoc.v:201555.3-201685.6" + wire $3\core_core_core_exc_$signal$5$next[0:0]$14150 + attribute \src "libresoc.v:201555.3-201685.6" + wire $3\core_core_core_exc_$signal$6$next[0:0]$14151 + attribute \src "libresoc.v:201555.3-201685.6" + wire $3\core_core_core_exc_$signal$7$next[0:0]$14152 + attribute \src "libresoc.v:201555.3-201685.6" + wire $3\core_core_core_exc_$signal$8$next[0:0]$14153 + attribute \src "libresoc.v:201555.3-201685.6" + wire $3\core_core_core_exc_$signal$9$next[0:0]$14154 + attribute \src "libresoc.v:201555.3-201685.6" + wire $3\core_core_core_exc_$signal$next[0:0]$14155 + attribute \src "libresoc.v:201555.3-201685.6" + wire $3\core_core_core_oe_ok$next[0:0]$14156 + attribute \src "libresoc.v:201555.3-201685.6" + wire $3\core_core_core_rc_ok$next[0:0]$14157 + attribute \src "libresoc.v:201555.3-201685.6" + wire $3\core_core_cr_in1_ok$next[0:0]$14158 + attribute \src "libresoc.v:201555.3-201685.6" + wire $3\core_core_cr_in2_ok$2$next[0:0]$14159 + attribute \src "libresoc.v:201555.3-201685.6" + wire $3\core_core_cr_in2_ok$next[0:0]$14160 + attribute \src "libresoc.v:201555.3-201685.6" + wire $3\core_core_cr_wr_ok$next[0:0]$14161 + attribute \src "libresoc.v:199564.3-199628.6" + wire width 7 $3\core_core_dststep$next[6:0]$13749 + attribute \src "libresoc.v:201555.3-201685.6" + wire $3\core_core_fast1_ok$next[0:0]$14162 + attribute \src "libresoc.v:201555.3-201685.6" + wire $3\core_core_fast2_ok$next[0:0]$14163 + attribute \src "libresoc.v:199564.3-199628.6" + wire width 7 $3\core_core_maxvl$next[6:0]$13750 + attribute \src "libresoc.v:199564.3-199628.6" + wire width 64 $3\core_core_pc$next[63:0]$13751 + attribute \src "libresoc.v:201555.3-201685.6" + wire $3\core_core_reg1_ok$next[0:0]$14164 + attribute \src "libresoc.v:201555.3-201685.6" + wire $3\core_core_reg2_ok$next[0:0]$14165 + attribute \src "libresoc.v:201555.3-201685.6" + wire $3\core_core_reg3_ok$next[0:0]$14166 + attribute \src "libresoc.v:201555.3-201685.6" + wire $3\core_core_spr1_ok$next[0:0]$14167 + attribute \src "libresoc.v:199564.3-199628.6" + wire width 7 $3\core_core_srcstep$next[6:0]$13752 + attribute \src "libresoc.v:199564.3-199628.6" + wire width 2 $3\core_core_subvl$next[1:0]$13753 + attribute \src "libresoc.v:199564.3-199628.6" + wire width 2 $3\core_core_svstep$next[1:0]$13754 + attribute \src "libresoc.v:199564.3-199628.6" + wire width 7 $3\core_core_vl$next[6:0]$13755 + attribute \src "libresoc.v:201555.3-201685.6" + wire $3\core_cr_out_ok$next[0:0]$14168 + attribute \src "libresoc.v:200548.3-200627.6" wire width 64 $3\core_data_i[63:0] - attribute \src "libresoc.v:197247.3-197291.6" - wire width 64 $3\core_dec$next[63:0]$13770 - attribute \src "libresoc.v:198886.3-198996.6" - wire $3\core_ea_ok$next[0:0]$14183 - attribute \src "libresoc.v:197247.3-197291.6" - wire $3\core_eint$next[0:0]$13771 - attribute \src "libresoc.v:198886.3-198996.6" - wire $3\core_fasto1_ok$next[0:0]$14184 - attribute \src "libresoc.v:198886.3-198996.6" - wire $3\core_fasto2_ok$next[0:0]$14185 - attribute \src "libresoc.v:197502.3-197526.6" + attribute \src "libresoc.v:199564.3-199628.6" + wire width 64 $3\core_dec$next[63:0]$13756 + attribute \src "libresoc.v:201555.3-201685.6" + wire $3\core_ea_ok$next[0:0]$14169 + attribute \src "libresoc.v:199564.3-199628.6" + wire $3\core_eint$next[0:0]$13757 + attribute \src "libresoc.v:201555.3-201685.6" + wire $3\core_fasto1_ok$next[0:0]$14170 + attribute \src "libresoc.v:201555.3-201685.6" + wire $3\core_fasto2_ok$next[0:0]$14171 + attribute \src "libresoc.v:199967.3-199991.6" wire $3\core_ivalid_i[0:0] - attribute \src "libresoc.v:197247.3-197291.6" - wire width 64 $3\core_msr$next[63:0]$13772 - attribute \src "libresoc.v:197292.3-197312.6" - wire width 32 $3\core_raw_insn_i$next[31:0]$13777 - attribute \src "libresoc.v:198886.3-198996.6" - wire $3\core_rego_ok$next[0:0]$14186 - attribute \src "libresoc.v:198886.3-198996.6" - wire $3\core_spro_ok$next[0:0]$14187 - attribute \src "libresoc.v:198622.3-198652.6" + attribute \src "libresoc.v:199564.3-199628.6" + wire width 64 $3\core_msr$next[63:0]$13758 + attribute \src "libresoc.v:199629.3-199653.6" + wire width 32 $3\core_raw_insn_i$next[31:0]$13763 + attribute \src "libresoc.v:201555.3-201685.6" + wire $3\core_rego_ok$next[0:0]$14172 + attribute \src "libresoc.v:201555.3-201685.6" + wire $3\core_spro_ok$next[0:0]$14173 + attribute \src "libresoc.v:201207.3-201253.6" wire $3\core_stopped_i[0:0] - attribute \src "libresoc.v:197338.3-197362.6" - wire $3\core_sv_a_nz$next[0:0]$13787 - attribute \src "libresoc.v:197947.3-198014.6" + attribute \src "libresoc.v:199699.3-199743.6" + wire $3\core_sv_a_nz$next[0:0]$13773 + attribute \src "libresoc.v:200468.3-200547.6" wire width 3 $3\core_wen[2:0] - attribute \src "libresoc.v:198233.3-198271.6" - wire width 7 $3\cur_cur_dststep$next[6:0]$13897 - attribute \src "libresoc.v:198233.3-198271.6" - wire width 7 $3\cur_cur_maxvl$next[6:0]$13898 - attribute \src "libresoc.v:198233.3-198271.6" - wire width 7 $3\cur_cur_srcstep$next[6:0]$13899 - attribute \src "libresoc.v:198233.3-198271.6" - wire width 2 $3\cur_cur_subvl$next[1:0]$13900 - attribute \src "libresoc.v:198233.3-198271.6" - wire width 2 $3\cur_cur_svstep$next[1:0]$13901 - attribute \src "libresoc.v:198233.3-198271.6" - wire width 7 $3\cur_cur_vl$next[6:0]$13902 - attribute \src "libresoc.v:198653.3-198683.6" + attribute \src "libresoc.v:200778.3-200816.6" + wire width 7 $3\cur_cur_dststep$next[6:0]$13883 + attribute \src "libresoc.v:200778.3-200816.6" + wire width 7 $3\cur_cur_maxvl$next[6:0]$13884 + attribute \src "libresoc.v:200778.3-200816.6" + wire width 7 $3\cur_cur_srcstep$next[6:0]$13885 + attribute \src "libresoc.v:200778.3-200816.6" + wire width 2 $3\cur_cur_subvl$next[1:0]$13886 + attribute \src "libresoc.v:200778.3-200816.6" + wire width 2 $3\cur_cur_svstep$next[1:0]$13887 + attribute \src "libresoc.v:200778.3-200816.6" + wire width 7 $3\cur_cur_vl$next[6:0]$13888 + attribute \src "libresoc.v:201254.3-201300.6" wire $3\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:198365.3-198385.6" - wire width 64 $3\dec2_cur_msr$next[63:0]$13930 - attribute \src "libresoc.v:198212.3-198232.6" - wire width 64 $3\dec2_cur_pc$next[63:0]$13877 - attribute \src "libresoc.v:198405.3-198435.6" - wire width 32 $3\dec2_raw_opcode_in$next[31:0]$13939 - attribute \src "libresoc.v:197543.3-197577.6" - wire $3\exec_fsm_state$next[0:0]$13807 - attribute \src "libresoc.v:198311.3-198364.6" - wire width 2 $3\fetch_fsm_state$next[1:0]$13922 - attribute \src "libresoc.v:198144.3-198177.6" + attribute \src "libresoc.v:200910.3-200934.6" + wire width 64 $3\dec2_cur_msr$next[63:0]$13916 + attribute \src "libresoc.v:200757.3-200777.6" + wire width 64 $3\dec2_cur_pc$next[63:0]$13863 + attribute \src "libresoc.v:200958.3-200992.6" + wire width 32 $3\dec2_raw_opcode_in$next[31:0]$13925 + attribute \src "libresoc.v:200008.3-200042.6" + wire $3\exec_fsm_state$next[0:0]$13793 + attribute \src "libresoc.v:200856.3-200909.6" + wire width 2 $3\fetch_fsm_state$next[1:0]$13908 + attribute \src "libresoc.v:200689.3-200722.6" wire $3\imem_a_valid_i[0:0] - attribute \src "libresoc.v:198178.3-198211.6" + attribute \src "libresoc.v:200723.3-200756.6" wire $3\imem_f_valid_i[0:0] - attribute \src "libresoc.v:197363.3-197400.6" + attribute \src "libresoc.v:199744.3-199789.6" wire $3\insn_done[0:0] - attribute \src "libresoc.v:197450.3-197470.6" + attribute \src "libresoc.v:199895.3-199935.6" wire $3\is_last[0:0] - attribute \src "libresoc.v:198523.3-198621.6" - wire width 3 $3\issue_fsm_state$next[2:0]$13947 - attribute \src "libresoc.v:198272.3-198301.6" - wire $3\msr_read$next[0:0]$13913 - attribute \src "libresoc.v:198447.3-198506.6" + attribute \src "libresoc.v:201108.3-201206.6" + wire width 3 $3\issue_fsm_state$next[2:0]$13933 + attribute \src "libresoc.v:200817.3-200846.6" + wire $3\msr_read$next[0:0]$13899 + attribute \src "libresoc.v:201016.3-201091.6" wire width 7 $3\new_svstate_dststep[6:0] - attribute \src "libresoc.v:198447.3-198506.6" + attribute \src "libresoc.v:201016.3-201091.6" wire width 7 $3\new_svstate_maxvl[6:0] - attribute \src "libresoc.v:198447.3-198506.6" + attribute \src "libresoc.v:201016.3-201091.6" wire width 7 $3\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:198447.3-198506.6" + attribute \src "libresoc.v:201016.3-201091.6" wire width 2 $3\new_svstate_subvl[1:0] - attribute \src "libresoc.v:198447.3-198506.6" + attribute \src "libresoc.v:201016.3-201091.6" wire width 2 $3\new_svstate_svstep[1:0] - attribute \src "libresoc.v:198447.3-198506.6" + attribute \src "libresoc.v:201016.3-201091.6" wire width 7 $3\new_svstate_vl[6:0] - attribute \src "libresoc.v:198684.3-198750.6" - wire $3\pc_changed$next[0:0]$13963 - attribute \src "libresoc.v:198808.3-198874.6" - wire $3\sv_changed$next[0:0]$13975 - attribute \src "libresoc.v:198751.3-198807.6" + attribute \src "libresoc.v:201301.3-201383.6" + wire $3\pc_changed$next[0:0]$13949 + attribute \src "libresoc.v:201457.3-201539.6" + wire $3\sv_changed$next[0:0]$13961 + attribute \src "libresoc.v:201384.3-201456.6" wire $3\update_svstate[0:0] - attribute \src "libresoc.v:198015.3-198082.6" + attribute \src "libresoc.v:200548.3-200627.6" wire width 64 $4\core_data_i[63:0] - attribute \src "libresoc.v:197947.3-198014.6" + attribute \src "libresoc.v:200468.3-200547.6" wire width 3 $4\core_wen[2:0] - attribute \src "libresoc.v:198233.3-198271.6" - wire width 7 $4\cur_cur_dststep$next[6:0]$13903 - attribute \src "libresoc.v:198233.3-198271.6" - wire width 7 $4\cur_cur_maxvl$next[6:0]$13904 - attribute \src "libresoc.v:198233.3-198271.6" - wire width 7 $4\cur_cur_srcstep$next[6:0]$13905 - attribute \src "libresoc.v:198233.3-198271.6" - wire width 2 $4\cur_cur_subvl$next[1:0]$13906 - attribute \src "libresoc.v:198233.3-198271.6" - wire width 2 $4\cur_cur_svstep$next[1:0]$13907 - attribute \src "libresoc.v:198233.3-198271.6" - wire width 7 $4\cur_cur_vl$next[6:0]$13908 - attribute \src "libresoc.v:197543.3-197577.6" - wire $4\exec_fsm_state$next[0:0]$13808 - attribute \src "libresoc.v:198311.3-198364.6" - wire width 2 $4\fetch_fsm_state$next[1:0]$13923 - attribute \src "libresoc.v:198144.3-198177.6" + attribute \src "libresoc.v:200778.3-200816.6" + wire width 7 $4\cur_cur_dststep$next[6:0]$13889 + attribute \src "libresoc.v:200778.3-200816.6" + wire width 7 $4\cur_cur_maxvl$next[6:0]$13890 + attribute \src "libresoc.v:200778.3-200816.6" + wire width 7 $4\cur_cur_srcstep$next[6:0]$13891 + attribute \src "libresoc.v:200778.3-200816.6" + wire width 2 $4\cur_cur_subvl$next[1:0]$13892 + attribute \src "libresoc.v:200778.3-200816.6" + wire width 2 $4\cur_cur_svstep$next[1:0]$13893 + attribute \src "libresoc.v:200778.3-200816.6" + wire width 7 $4\cur_cur_vl$next[6:0]$13894 + attribute \src "libresoc.v:200008.3-200042.6" + wire $4\exec_fsm_state$next[0:0]$13794 + attribute \src "libresoc.v:200856.3-200909.6" + wire width 2 $4\fetch_fsm_state$next[1:0]$13909 + attribute \src "libresoc.v:200689.3-200722.6" wire $4\imem_a_valid_i[0:0] - attribute \src "libresoc.v:198178.3-198211.6" + attribute \src "libresoc.v:200723.3-200756.6" wire $4\imem_f_valid_i[0:0] - attribute \src "libresoc.v:197363.3-197400.6" + attribute \src "libresoc.v:199744.3-199789.6" wire $4\insn_done[0:0] - attribute \src "libresoc.v:198523.3-198621.6" - wire width 3 $4\issue_fsm_state$next[2:0]$13948 - attribute \src "libresoc.v:198272.3-198301.6" - wire $4\msr_read$next[0:0]$13914 - attribute \src "libresoc.v:198447.3-198506.6" + attribute \src "libresoc.v:201108.3-201206.6" + wire width 3 $4\issue_fsm_state$next[2:0]$13934 + attribute \src "libresoc.v:200817.3-200846.6" + wire $4\msr_read$next[0:0]$13900 + attribute \src "libresoc.v:201016.3-201091.6" wire width 7 $4\new_svstate_dststep[6:0] - attribute \src "libresoc.v:198447.3-198506.6" + attribute \src "libresoc.v:201016.3-201091.6" wire width 7 $4\new_svstate_maxvl[6:0] - attribute \src "libresoc.v:198447.3-198506.6" + attribute \src "libresoc.v:201016.3-201091.6" wire width 7 $4\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:198447.3-198506.6" + attribute \src "libresoc.v:201016.3-201091.6" wire width 2 $4\new_svstate_subvl[1:0] - attribute \src "libresoc.v:198447.3-198506.6" + attribute \src "libresoc.v:201016.3-201091.6" wire width 2 $4\new_svstate_svstep[1:0] - attribute \src "libresoc.v:198447.3-198506.6" + attribute \src "libresoc.v:201016.3-201091.6" wire width 7 $4\new_svstate_vl[6:0] - attribute \src "libresoc.v:198684.3-198750.6" - wire $4\pc_changed$next[0:0]$13964 - attribute \src "libresoc.v:198808.3-198874.6" - wire $4\sv_changed$next[0:0]$13976 - attribute \src "libresoc.v:198751.3-198807.6" + attribute \src "libresoc.v:201301.3-201383.6" + wire $4\pc_changed$next[0:0]$13950 + attribute \src "libresoc.v:201457.3-201539.6" + wire $4\sv_changed$next[0:0]$13962 + attribute \src "libresoc.v:201384.3-201456.6" wire $4\update_svstate[0:0] - attribute \src "libresoc.v:198015.3-198082.6" + attribute \src "libresoc.v:200548.3-200627.6" wire width 64 $5\core_data_i[63:0] - attribute \src "libresoc.v:197947.3-198014.6" + attribute \src "libresoc.v:200468.3-200547.6" wire width 3 $5\core_wen[2:0] - attribute \src "libresoc.v:197543.3-197577.6" - wire $5\exec_fsm_state$next[0:0]$13809 - attribute \src "libresoc.v:198311.3-198364.6" - wire width 2 $5\fetch_fsm_state$next[1:0]$13924 - attribute \src "libresoc.v:197363.3-197400.6" + attribute \src "libresoc.v:200008.3-200042.6" + wire $5\exec_fsm_state$next[0:0]$13795 + attribute \src "libresoc.v:200856.3-200909.6" + wire width 2 $5\fetch_fsm_state$next[1:0]$13910 + attribute \src "libresoc.v:199744.3-199789.6" wire $5\insn_done[0:0] - attribute \src "libresoc.v:198523.3-198621.6" - wire width 3 $5\issue_fsm_state$next[2:0]$13949 - attribute \src "libresoc.v:198447.3-198506.6" + attribute \src "libresoc.v:201108.3-201206.6" + wire width 3 $5\issue_fsm_state$next[2:0]$13935 + attribute \src "libresoc.v:201016.3-201091.6" wire width 7 $5\new_svstate_dststep[6:0] - attribute \src "libresoc.v:198447.3-198506.6" + attribute \src "libresoc.v:201016.3-201091.6" wire width 7 $5\new_svstate_maxvl[6:0] - attribute \src "libresoc.v:198447.3-198506.6" + attribute \src "libresoc.v:201016.3-201091.6" wire width 7 $5\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:198447.3-198506.6" + attribute \src "libresoc.v:201016.3-201091.6" wire width 2 $5\new_svstate_subvl[1:0] - attribute \src "libresoc.v:198447.3-198506.6" + attribute \src "libresoc.v:201016.3-201091.6" wire width 2 $5\new_svstate_svstep[1:0] - attribute \src "libresoc.v:198447.3-198506.6" + attribute \src "libresoc.v:201016.3-201091.6" wire width 7 $5\new_svstate_vl[6:0] - attribute \src "libresoc.v:198684.3-198750.6" - wire $5\pc_changed$next[0:0]$13965 - attribute \src "libresoc.v:198808.3-198874.6" - wire $5\sv_changed$next[0:0]$13977 - attribute \src "libresoc.v:198751.3-198807.6" + attribute \src "libresoc.v:201301.3-201383.6" + wire $5\pc_changed$next[0:0]$13951 + attribute \src "libresoc.v:201457.3-201539.6" + wire $5\sv_changed$next[0:0]$13963 + attribute \src "libresoc.v:201384.3-201456.6" wire $5\update_svstate[0:0] - attribute \src "libresoc.v:198015.3-198082.6" + attribute \src "libresoc.v:200548.3-200627.6" wire width 64 $6\core_data_i[63:0] - attribute \src "libresoc.v:197947.3-198014.6" + attribute \src "libresoc.v:200468.3-200547.6" wire width 3 $6\core_wen[2:0] - attribute \src "libresoc.v:198311.3-198364.6" - wire width 2 $6\fetch_fsm_state$next[1:0]$13925 - attribute \src "libresoc.v:197363.3-197400.6" + attribute \src "libresoc.v:200856.3-200909.6" + wire width 2 $6\fetch_fsm_state$next[1:0]$13911 + attribute \src "libresoc.v:199744.3-199789.6" wire $6\insn_done[0:0] - attribute \src "libresoc.v:198523.3-198621.6" - wire width 3 $6\issue_fsm_state$next[2:0]$13950 - attribute \src "libresoc.v:198447.3-198506.6" + attribute \src "libresoc.v:201108.3-201206.6" + wire width 3 $6\issue_fsm_state$next[2:0]$13936 + attribute \src "libresoc.v:201016.3-201091.6" wire width 7 $6\new_svstate_dststep[6:0] - attribute \src "libresoc.v:198447.3-198506.6" + attribute \src "libresoc.v:201016.3-201091.6" wire width 7 $6\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:198684.3-198750.6" - wire $6\pc_changed$next[0:0]$13966 - attribute \src "libresoc.v:198808.3-198874.6" - wire $6\sv_changed$next[0:0]$13978 - attribute \src "libresoc.v:198751.3-198807.6" + attribute \src "libresoc.v:201301.3-201383.6" + wire $6\pc_changed$next[0:0]$13952 + attribute \src "libresoc.v:201457.3-201539.6" + wire $6\sv_changed$next[0:0]$13964 + attribute \src "libresoc.v:201384.3-201456.6" wire $6\update_svstate[0:0] - attribute \src "libresoc.v:198015.3-198082.6" + attribute \src "libresoc.v:200548.3-200627.6" wire width 64 $7\core_data_i[63:0] - attribute \src "libresoc.v:197947.3-198014.6" + attribute \src "libresoc.v:200468.3-200547.6" wire width 3 $7\core_wen[2:0] - attribute \src "libresoc.v:198523.3-198621.6" - wire width 3 $7\issue_fsm_state$next[2:0]$13951 - attribute \src "libresoc.v:198447.3-198506.6" + attribute \src "libresoc.v:201108.3-201206.6" + wire width 3 $7\issue_fsm_state$next[2:0]$13937 + attribute \src "libresoc.v:201016.3-201091.6" wire width 7 $7\new_svstate_dststep[6:0] - attribute \src "libresoc.v:198447.3-198506.6" + attribute \src "libresoc.v:201016.3-201091.6" wire width 7 $7\new_svstate_srcstep[6:0] - attribute \src "libresoc.v:198684.3-198750.6" - wire $7\pc_changed$next[0:0]$13967 - attribute \src "libresoc.v:198808.3-198874.6" - wire $7\sv_changed$next[0:0]$13979 - attribute \src "libresoc.v:198751.3-198807.6" + attribute \src "libresoc.v:201301.3-201383.6" + wire $7\pc_changed$next[0:0]$13953 + attribute \src "libresoc.v:201457.3-201539.6" + wire $7\sv_changed$next[0:0]$13965 + attribute \src "libresoc.v:201384.3-201456.6" wire $7\update_svstate[0:0] - attribute \src "libresoc.v:198015.3-198082.6" + attribute \src "libresoc.v:200548.3-200627.6" wire width 64 $8\core_data_i[63:0] - attribute \src "libresoc.v:197947.3-198014.6" + attribute \src "libresoc.v:200468.3-200547.6" wire width 3 $8\core_wen[2:0] - attribute \src "libresoc.v:198523.3-198621.6" - wire width 3 $8\issue_fsm_state$next[2:0]$13952 - attribute \src "libresoc.v:198684.3-198750.6" - wire $8\pc_changed$next[0:0]$13968 - attribute \src "libresoc.v:198808.3-198874.6" - wire $8\sv_changed$next[0:0]$13980 - attribute \src "libresoc.v:198015.3-198082.6" + attribute \src "libresoc.v:201108.3-201206.6" + wire width 3 $8\issue_fsm_state$next[2:0]$13938 + attribute \src "libresoc.v:201301.3-201383.6" + wire $8\pc_changed$next[0:0]$13954 + attribute \src "libresoc.v:201457.3-201539.6" + wire $8\sv_changed$next[0:0]$13966 + attribute \src "libresoc.v:200548.3-200627.6" wire width 64 $9\core_data_i[63:0] - attribute \src "libresoc.v:197947.3-198014.6" + attribute \src "libresoc.v:200468.3-200547.6" wire width 3 $9\core_wen[2:0] - attribute \src "libresoc.v:198523.3-198621.6" - wire width 3 $9\issue_fsm_state$next[2:0]$13953 - attribute \src "libresoc.v:198684.3-198750.6" - wire $9\pc_changed$next[0:0]$13969 - attribute \src "libresoc.v:198808.3-198874.6" - wire $9\sv_changed$next[0:0]$13981 - attribute \src "libresoc.v:196328.19-196328.108" - wire width 65 $add$libresoc.v:196328$13493_Y - attribute \src "libresoc.v:196340.19-196340.112" - wire width 8 $add$libresoc.v:196340$13504_Y - attribute \src "libresoc.v:196341.19-196341.112" - wire width 8 $add$libresoc.v:196341$13505_Y - attribute \src "libresoc.v:196411.19-196411.116" - wire width 65 $add$libresoc.v:196411$13575_Y - attribute \src "libresoc.v:196445.18-196445.107" - wire width 65 $add$libresoc.v:196445$13608_Y - attribute \src "libresoc.v:196333.19-196333.104" - wire $and$libresoc.v:196333$13498_Y - attribute \src "libresoc.v:196336.19-196336.104" - wire $and$libresoc.v:196336$13501_Y - attribute \src "libresoc.v:196344.19-196344.104" - wire $and$libresoc.v:196344$13508_Y - attribute \src "libresoc.v:196347.19-196347.104" - wire $and$libresoc.v:196347$13511_Y - attribute \src "libresoc.v:196349.19-196349.111" - wire $and$libresoc.v:196349$13513_Y - attribute \src "libresoc.v:196352.19-196352.104" - wire $and$libresoc.v:196352$13516_Y - attribute \src "libresoc.v:196358.19-196358.104" - wire $and$libresoc.v:196358$13521_Y - attribute \src "libresoc.v:196361.19-196361.104" - wire $and$libresoc.v:196361$13524_Y - attribute \src "libresoc.v:196364.19-196364.104" - wire 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attribute \src "libresoc.v:196375.19-196375.93" - wire $reduce_or$libresoc.v:196375$13538_Y - attribute \src "libresoc.v:196392.19-196392.93" - wire $reduce_or$libresoc.v:196392$13554_Y - attribute \src "libresoc.v:196330.18-196330.41" - wire width 64 $shr$libresoc.v:196330$13495_Y - attribute \src "libresoc.v:196447.18-196447.40" - wire width 64 $shr$libresoc.v:196447$13610_Y - attribute \src "libresoc.v:196410.19-196410.116" - wire width 65 $sub$libresoc.v:196410$13574_Y - attribute \src "libresoc.v:196412.18-196412.101" - wire width 3 $sub$libresoc.v:196412$13576_Y + attribute \src "libresoc.v:201108.3-201206.6" + wire width 3 $9\issue_fsm_state$next[2:0]$13939 + attribute \src "libresoc.v:201301.3-201383.6" + wire $9\pc_changed$next[0:0]$13955 + attribute \src "libresoc.v:201457.3-201539.6" + wire $9\sv_changed$next[0:0]$13967 + attribute \src "libresoc.v:198689.19-198689.108" + wire width 65 $add$libresoc.v:198689$13479_Y + attribute \src "libresoc.v:198701.19-198701.112" + wire width 8 $add$libresoc.v:198701$13490_Y + attribute \src "libresoc.v:198702.19-198702.112" + wire width 8 $add$libresoc.v:198702$13491_Y + attribute \src "libresoc.v:198772.19-198772.116" + wire width 65 $add$libresoc.v:198772$13561_Y + attribute \src "libresoc.v:198806.18-198806.107" + wire width 65 $add$libresoc.v:198806$13594_Y + attribute \src "libresoc.v:198694.19-198694.104" + wire $and$libresoc.v:198694$13484_Y + attribute \src "libresoc.v:198697.19-198697.104" + wire $and$libresoc.v:198697$13487_Y + attribute \src "libresoc.v:198705.19-198705.104" + wire $and$libresoc.v:198705$13494_Y + attribute \src "libresoc.v:198708.19-198708.104" + wire $and$libresoc.v:198708$13497_Y + attribute \src "libresoc.v:198710.19-198710.111" + wire $and$libresoc.v:198710$13499_Y + attribute \src "libresoc.v:198713.19-198713.104" + wire $and$libresoc.v:198713$13502_Y + attribute \src "libresoc.v:198719.19-198719.104" + wire $and$libresoc.v:198719$13507_Y + attribute \src "libresoc.v:198722.19-198722.104" + wire $and$libresoc.v:198722$13510_Y + attribute \src "libresoc.v:198725.19-198725.104" + wire $and$libresoc.v:198725$13513_Y + attribute \src "libresoc.v:198728.19-198728.104" + wire $and$libresoc.v:198728$13516_Y + attribute \src "libresoc.v:198731.19-198731.104" + wire $and$libresoc.v:198731$13519_Y + attribute \src "libresoc.v:198734.19-198734.104" + wire $and$libresoc.v:198734$13522_Y + attribute \src "libresoc.v:198735.19-198735.115" + wire width 3 $and$libresoc.v:198735$13523_Y + attribute \src "libresoc.v:198739.19-198739.104" + wire $and$libresoc.v:198739$13527_Y + attribute \src "libresoc.v:198742.19-198742.104" + wire $and$libresoc.v:198742$13530_Y + attribute \src "libresoc.v:198748.19-198748.104" + wire $and$libresoc.v:198748$13535_Y + attribute \src "libresoc.v:198751.19-198751.104" + wire $and$libresoc.v:198751$13538_Y + attribute \src "libresoc.v:198752.19-198752.115" + wire width 3 $and$libresoc.v:198752$13539_Y + attribute \src "libresoc.v:198755.19-198755.111" + wire $and$libresoc.v:198755$13542_Y + attribute \src "libresoc.v:198760.19-198760.104" + wire $and$libresoc.v:198760$13547_Y + attribute \src "libresoc.v:198763.19-198763.104" + wire $and$libresoc.v:198763$13550_Y + attribute \src "libresoc.v:198778.18-198778.109" + wire $and$libresoc.v:198778$13567_Y + attribute \src "libresoc.v:198784.18-198784.101" + wire $and$libresoc.v:198784$13574_Y + attribute \src "libresoc.v:198786.18-198786.109" + wire $and$libresoc.v:198786$13576_Y + attribute \src "libresoc.v:198789.18-198789.101" + wire $and$libresoc.v:198789$13579_Y + attribute \src "libresoc.v:198795.18-198795.101" + wire $and$libresoc.v:198795$13584_Y + attribute \src "libresoc.v:198797.18-198797.109" + wire $and$libresoc.v:198797$13586_Y + attribute \src "libresoc.v:198800.18-198800.101" + wire $and$libresoc.v:198800$13589_Y + attribute \src "libresoc.v:198709.19-198709.108" + wire $eq$libresoc.v:198709$13498_Y + attribute \src "libresoc.v:198754.19-198754.108" + wire $eq$libresoc.v:198754$13541_Y + attribute \src "libresoc.v:198764.19-198764.116" + wire $eq$libresoc.v:198764$13551_Y + attribute \src "libresoc.v:198785.18-198785.107" + wire $eq$libresoc.v:198785$13575_Y + attribute \src "libresoc.v:198796.18-198796.107" + wire $eq$libresoc.v:198796$13585_Y + attribute \src "libresoc.v:198769.19-198769.114" + wire width 64 $extend$libresoc.v:198769$13556_Y + attribute \src "libresoc.v:198770.19-198770.113" + wire width 64 $extend$libresoc.v:198770$13558_Y + attribute \src "libresoc.v:198781.18-198781.109" + wire width 64 $extend$libresoc.v:198781$13570_Y + attribute \src "libresoc.v:198690.19-198690.106" + wire width 7 $mul$libresoc.v:198690$13480_Y + attribute \src "libresoc.v:198807.18-198807.110" + wire width 7 $mul$libresoc.v:198807$13595_Y + attribute \src "libresoc.v:198758.18-198758.102" + wire $ne$libresoc.v:198758$13545_Y + attribute \src "libresoc.v:198766.19-198766.123" + wire $ne$libresoc.v:198766$13553_Y + attribute \src "libresoc.v:198776.18-198776.102" + wire $ne$libresoc.v:198776$13565_Y + attribute \src "libresoc.v:198692.19-198692.107" + wire $not$libresoc.v:198692$13482_Y + attribute \src "libresoc.v:198693.19-198693.109" + wire $not$libresoc.v:198693$13483_Y + attribute \src "libresoc.v:198695.19-198695.107" + wire $not$libresoc.v:198695$13485_Y + attribute \src "libresoc.v:198696.19-198696.109" + wire $not$libresoc.v:198696$13486_Y + attribute \src "libresoc.v:198703.19-198703.107" + wire $not$libresoc.v:198703$13492_Y + attribute \src "libresoc.v:198704.19-198704.109" + wire $not$libresoc.v:198704$13493_Y + attribute \src "libresoc.v:198706.19-198706.107" + wire $not$libresoc.v:198706$13495_Y + attribute \src "libresoc.v:198707.19-198707.109" + wire $not$libresoc.v:198707$13496_Y + attribute \src "libresoc.v:198711.19-198711.107" + wire $not$libresoc.v:198711$13500_Y + attribute \src "libresoc.v:198712.19-198712.109" + wire $not$libresoc.v:198712$13501_Y + attribute \src "libresoc.v:198717.19-198717.107" + wire $not$libresoc.v:198717$13505_Y + attribute \src "libresoc.v:198718.19-198718.109" + wire $not$libresoc.v:198718$13506_Y + attribute \src "libresoc.v:198720.19-198720.107" + wire $not$libresoc.v:198720$13508_Y + attribute \src "libresoc.v:198721.19-198721.109" + wire $not$libresoc.v:198721$13509_Y + attribute \src "libresoc.v:198723.19-198723.107" + wire $not$libresoc.v:198723$13511_Y + attribute \src "libresoc.v:198724.19-198724.109" + wire $not$libresoc.v:198724$13512_Y + attribute \src "libresoc.v:198726.19-198726.107" + wire $not$libresoc.v:198726$13514_Y + attribute \src "libresoc.v:198727.19-198727.109" + wire $not$libresoc.v:198727$13515_Y + attribute \src "libresoc.v:198729.19-198729.107" + wire $not$libresoc.v:198729$13517_Y + attribute \src "libresoc.v:198730.19-198730.109" + wire $not$libresoc.v:198730$13518_Y + attribute \src "libresoc.v:198732.19-198732.107" + wire $not$libresoc.v:198732$13520_Y + attribute \src "libresoc.v:198733.19-198733.109" + wire $not$libresoc.v:198733$13521_Y + attribute \src "libresoc.v:198737.19-198737.107" + wire $not$libresoc.v:198737$13525_Y + attribute \src "libresoc.v:198738.19-198738.109" + wire $not$libresoc.v:198738$13526_Y + attribute \src "libresoc.v:198740.19-198740.107" + wire $not$libresoc.v:198740$13528_Y + attribute \src "libresoc.v:198741.19-198741.109" + wire $not$libresoc.v:198741$13529_Y + attribute \src "libresoc.v:198746.19-198746.107" + wire $not$libresoc.v:198746$13533_Y + attribute \src "libresoc.v:198747.19-198747.109" + wire $not$libresoc.v:198747$13534_Y + attribute \src "libresoc.v:198749.19-198749.107" + wire $not$libresoc.v:198749$13536_Y + attribute \src "libresoc.v:198750.19-198750.109" + wire $not$libresoc.v:198750$13537_Y + attribute \src "libresoc.v:198756.19-198756.107" + wire $not$libresoc.v:198756$13543_Y + attribute \src "libresoc.v:198757.19-198757.107" + wire $not$libresoc.v:198757$13544_Y + attribute \src "libresoc.v:198759.19-198759.109" + wire $not$libresoc.v:198759$13546_Y + attribute \src "libresoc.v:198761.19-198761.107" + wire $not$libresoc.v:198761$13548_Y + attribute \src "libresoc.v:198762.19-198762.109" + wire $not$libresoc.v:198762$13549_Y + attribute \src "libresoc.v:198767.19-198767.107" + wire $not$libresoc.v:198767$13554_Y + attribute \src "libresoc.v:198768.19-198768.107" + wire $not$libresoc.v:198768$13555_Y + attribute \src "libresoc.v:198777.18-198777.103" + wire $not$libresoc.v:198777$13566_Y + attribute \src "libresoc.v:198779.18-198779.97" + wire $not$libresoc.v:198779$13568_Y + attribute \src "libresoc.v:198780.18-198780.102" + wire $not$libresoc.v:198780$13569_Y + attribute \src "libresoc.v:198782.18-198782.106" + wire $not$libresoc.v:198782$13572_Y + attribute \src "libresoc.v:198783.18-198783.108" + wire $not$libresoc.v:198783$13573_Y + attribute \src "libresoc.v:198787.18-198787.106" + wire $not$libresoc.v:198787$13577_Y + attribute \src "libresoc.v:198788.18-198788.108" + wire $not$libresoc.v:198788$13578_Y + attribute \src "libresoc.v:198793.18-198793.106" + wire $not$libresoc.v:198793$13582_Y + attribute \src "libresoc.v:198794.18-198794.108" + wire $not$libresoc.v:198794$13583_Y + attribute \src "libresoc.v:198798.18-198798.106" + wire $not$libresoc.v:198798$13587_Y + attribute \src "libresoc.v:198799.18-198799.108" + wire $not$libresoc.v:198799$13588_Y + attribute \src "libresoc.v:198804.18-198804.99" + wire $not$libresoc.v:198804$13592_Y + attribute \src "libresoc.v:198805.18-198805.99" + wire $not$libresoc.v:198805$13593_Y + attribute \src "libresoc.v:198698.19-198698.113" + wire $or$libresoc.v:198698$13488_Y + attribute \src "libresoc.v:198700.19-198700.106" + wire $or$libresoc.v:198700$13489_Y + attribute \src "libresoc.v:198714.19-198714.113" + wire $or$libresoc.v:198714$13503_Y + attribute \src "libresoc.v:198716.19-198716.106" + wire $or$libresoc.v:198716$13504_Y + attribute \src "libresoc.v:198743.19-198743.113" + wire $or$libresoc.v:198743$13531_Y + attribute \src "libresoc.v:198745.19-198745.106" + wire $or$libresoc.v:198745$13532_Y + attribute \src "libresoc.v:198774.18-198774.110" + wire $or$libresoc.v:198774$13563_Y + attribute \src "libresoc.v:198775.18-198775.100" + wire $or$libresoc.v:198775$13564_Y + attribute \src "libresoc.v:198790.18-198790.112" + wire $or$libresoc.v:198790$13580_Y + attribute \src "libresoc.v:198792.18-198792.104" + wire $or$libresoc.v:198792$13581_Y + attribute \src "libresoc.v:198801.18-198801.112" + wire $or$libresoc.v:198801$13590_Y + attribute \src "libresoc.v:198803.18-198803.104" + wire $or$libresoc.v:198803$13591_Y + attribute \src "libresoc.v:198765.19-198765.211" + wire width 64 $pos$libresoc.v:198765$13552_Y + attribute \src "libresoc.v:198769.19-198769.114" + wire width 64 $pos$libresoc.v:198769$13557_Y + attribute \src "libresoc.v:198770.19-198770.113" + wire width 64 $pos$libresoc.v:198770$13559_Y + attribute \src "libresoc.v:198781.18-198781.109" + wire width 64 $pos$libresoc.v:198781$13571_Y + attribute \src "libresoc.v:198736.19-198736.93" + wire $reduce_or$libresoc.v:198736$13524_Y + attribute \src "libresoc.v:198753.19-198753.93" + wire $reduce_or$libresoc.v:198753$13540_Y + attribute \src "libresoc.v:198691.18-198691.41" + wire width 64 $shr$libresoc.v:198691$13481_Y + attribute \src "libresoc.v:198808.18-198808.40" + wire width 64 $shr$libresoc.v:198808$13596_Y + attribute \src "libresoc.v:198771.19-198771.116" + wire width 65 $sub$libresoc.v:198771$13560_Y + attribute \src "libresoc.v:198773.18-198773.101" + wire width 3 $sub$libresoc.v:198773$13562_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:349" wire width 65 \$100 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:349" @@ -402157,17 +374672,17 @@ module \ti wire \$108 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" wire \$112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" wire \$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" wire \$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" wire \$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637" wire \$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637" wire \$122 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:507" wire width 8 \$124 @@ -402193,17 +374708,17 @@ module \ti wire \$142 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" wire \$144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" wire \$146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" wire \$148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" wire \$150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" wire \$152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637" wire \$154 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637" wire \$156 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$158 @@ -402211,11 +374726,11 @@ module \ti wire \$160 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$162 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" wire \$164 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" wire \$166 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" wire \$168 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$170 @@ -402223,11 +374738,11 @@ module \ti wire \$172 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$174 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" wire \$176 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" wire \$178 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" wire \$180 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$182 @@ -402235,15 +374750,15 @@ module \ti wire \$184 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$186 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" wire \$188 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" wire \$190 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" wire \$192 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$194 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:728" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:729" wire width 3 \$195 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$198 @@ -402251,17 +374766,17 @@ module \ti wire \$200 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$202 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" wire \$204 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" wire \$206 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" wire \$208 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" wire \$210 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637" wire \$212 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637" wire \$214 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$216 @@ -402269,67 +374784,67 @@ module \ti wire \$218 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$220 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" wire \$222 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" wire \$224 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" wire \$226 attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$228 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:726" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:727" wire width 3 \$229 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:791" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" wire \$23 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" wire \$232 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" wire \$234 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:731" wire \$236 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" wire \$238 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" wire \$240 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" wire \$242 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" wire \$244 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" wire \$246 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" wire \$248 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:793" wire width 3 \$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:625" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626" wire \$250 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \$252 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:723" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:724" wire \$254 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:731" wire \$256 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:731" wire \$258 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:793" wire width 3 \$26 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \$260 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 64 \$262 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1001" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1002" wire width 65 \$264 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1001" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1002" wire width 65 \$265 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1017" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1018" wire width 65 \$267 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1017" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1018" wire width 65 \$268 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:797" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" wire \$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:797" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" wire \$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:797" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" wire \$32 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" wire \$34 @@ -402351,17 +374866,17 @@ module \ti wire \$50 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" wire \$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" wire \$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" wire \$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" wire \$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" wire \$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637" wire \$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637" wire \$64 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" wire \$66 @@ -402373,17 +374888,17 @@ module \ti wire \$72 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" wire \$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" wire \$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" wire \$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" wire \$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" wire \$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637" wire \$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637" wire \$86 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:302" wire \$88 @@ -402400,17 +374915,17 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:54" wire width 32 \$99 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 338 \TAP_bus__tck + wire input 294 \TAP_bus__tck attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 176 \TAP_bus__tdi + wire input 154 \TAP_bus__tdi attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire output 329 \TAP_bus__tdo + wire output 285 \TAP_bus__tdo attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:66" - wire input 339 \TAP_bus__tms + wire input 295 \TAP_bus__tms attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:225" wire output 3 \busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" - wire input 356 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + wire input 312 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" wire width 8 \core_asmcode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:94" @@ -402983,7 +375498,7 @@ module \ti wire width 3 \core_core_xer_in$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:99" wire \core_corebusy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire \core_coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire \core_cr_out_ok @@ -403093,7 +375608,7 @@ module \ti wire \core_xer_out attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" wire \core_xer_out$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 2 \coresync_clk attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:60" wire \cu_st__rel_o_dly @@ -403125,17 +375640,17 @@ module \ti wire width 7 \cur_cur_vl attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" wire width 7 \cur_cur_vl$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:956" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:957" wire \d_cr_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:956" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:957" wire \d_cr_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:946" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:947" wire \d_reg_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:946" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:947" wire \d_reg_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:966" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:967" wire \d_xer_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:966" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:967" wire \d_xer_delay$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" wire width 7 \dbg_core_dbg_core_dbg_dststep @@ -403683,52 +376198,52 @@ module \ti wire width 3 \dec2_xer_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:105" wire \dec2_xer_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:791" wire width 2 \delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:791" wire width 2 \delay$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 177 \eint_0__core__i + wire output 155 \eint_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 24 \eint_0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 178 \eint_1__core__i + wire output 156 \eint_1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 25 \eint_1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 179 \eint_2__core__i + wire output 157 \eint_2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 26 \eint_2__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" wire \exec_fsm_state - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" wire \exec_fsm_state$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:880" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:881" wire \exec_insn_ready_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:879" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:880" wire \exec_insn_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:884" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:885" wire \exec_pc_ready_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:883" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:884" wire \exec_pc_valid_o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" wire width 2 \fetch_fsm_state attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" wire width 2 \fetch_fsm_state$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:869" wire \fetch_insn_ready_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:867" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:868" wire \fetch_insn_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:864" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:865" wire \fetch_pc_ready_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:863" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:864" wire \fetch_pc_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:990" wire width 2 \fsm_state - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:990" wire width 2 \fsm_state$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 186 \gpio_e10__core__i + wire output 164 \gpio_e10__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 34 \gpio_e10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -403736,11 +376251,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 33 \gpio_e10__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 187 \gpio_e10__pad__o + wire output 165 \gpio_e10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 188 \gpio_e10__pad__oe + wire output 166 \gpio_e10__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 189 \gpio_e11__core__i + wire output 167 \gpio_e11__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 37 \gpio_e11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -403748,11 +376263,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 36 \gpio_e11__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 190 \gpio_e11__pad__o + wire output 168 \gpio_e11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 191 \gpio_e11__pad__oe + wire output 169 \gpio_e11__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 192 \gpio_e12__core__i + wire output 170 \gpio_e12__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 40 \gpio_e12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -403760,11 +376275,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 39 \gpio_e12__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 193 \gpio_e12__pad__o + wire output 171 \gpio_e12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 194 \gpio_e12__pad__oe + wire output 172 \gpio_e12__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 195 \gpio_e13__core__i + wire output 173 \gpio_e13__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 43 \gpio_e13__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -403772,11 +376287,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 42 \gpio_e13__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 196 \gpio_e13__pad__o + wire output 174 \gpio_e13__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 197 \gpio_e13__pad__oe + wire output 175 \gpio_e13__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 198 \gpio_e14__core__i + wire output 176 \gpio_e14__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 46 \gpio_e14__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -403784,11 +376299,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 45 \gpio_e14__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 199 \gpio_e14__pad__o + wire output 177 \gpio_e14__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 200 \gpio_e14__pad__oe + wire output 178 \gpio_e14__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 201 \gpio_e15__core__i + wire output 179 \gpio_e15__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 49 \gpio_e15__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -403796,11 +376311,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 48 \gpio_e15__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 202 \gpio_e15__pad__o + wire output 180 \gpio_e15__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 203 \gpio_e15__pad__oe + wire output 181 \gpio_e15__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 180 \gpio_e8__core__i + wire output 158 \gpio_e8__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 28 \gpio_e8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -403808,11 +376323,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 27 \gpio_e8__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 181 \gpio_e8__pad__o + wire output 159 \gpio_e8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 182 \gpio_e8__pad__oe + wire output 160 \gpio_e8__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 183 \gpio_e9__core__i + wire output 161 \gpio_e9__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 31 \gpio_e9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -403820,11 +376335,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 30 \gpio_e9__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 184 \gpio_e9__pad__o + wire output 162 \gpio_e9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 185 \gpio_e9__pad__oe + wire output 163 \gpio_e9__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 204 \gpio_s0__core__i + wire output 182 \gpio_s0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 52 \gpio_s0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -403832,11 +376347,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 51 \gpio_s0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 205 \gpio_s0__pad__o + wire output 183 \gpio_s0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 206 \gpio_s0__pad__oe + wire output 184 \gpio_s0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 207 \gpio_s1__core__i + wire output 185 \gpio_s1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 55 \gpio_s1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -403844,11 +376359,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 54 \gpio_s1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 208 \gpio_s1__pad__o + wire output 186 \gpio_s1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 209 \gpio_s1__pad__oe + wire output 187 \gpio_s1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 210 \gpio_s2__core__i + wire output 188 \gpio_s2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 58 \gpio_s2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -403856,11 +376371,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 57 \gpio_s2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 211 \gpio_s2__pad__o + wire output 189 \gpio_s2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 212 \gpio_s2__pad__oe + wire output 190 \gpio_s2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 213 \gpio_s3__core__i + wire output 191 \gpio_s3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 61 \gpio_s3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -403868,11 +376383,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 60 \gpio_s3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 214 \gpio_s3__pad__o + wire output 192 \gpio_s3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 215 \gpio_s3__pad__oe + wire output 193 \gpio_s3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 216 \gpio_s4__core__i + wire output 194 \gpio_s4__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 64 \gpio_s4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -403880,11 +376395,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 63 \gpio_s4__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 217 \gpio_s4__pad__o + wire output 195 \gpio_s4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 218 \gpio_s4__pad__oe + wire output 196 \gpio_s4__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 219 \gpio_s5__core__i + wire output 197 \gpio_s5__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 67 \gpio_s5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -403892,11 +376407,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 66 \gpio_s5__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 220 \gpio_s5__pad__o + wire output 198 \gpio_s5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 221 \gpio_s5__pad__oe + wire output 199 \gpio_s5__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 222 \gpio_s6__core__i + wire output 200 \gpio_s6__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 70 \gpio_s6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -403904,11 +376419,11 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 69 \gpio_s6__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 223 \gpio_s6__pad__o + wire output 201 \gpio_s6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 224 \gpio_s6__pad__oe + wire output 202 \gpio_s6__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 225 \gpio_s7__core__i + wire output 203 \gpio_s7__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 73 \gpio_s7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" @@ -403916,9 +376431,9 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 72 \gpio_s7__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 226 \gpio_s7__pad__o + wire output 204 \gpio_s7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 227 \gpio_s7__pad__oe + wire output 205 \gpio_s7__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire input 18 \ibus__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" @@ -403934,35 +376449,35 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" wire output 20 \ibus__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire output 340 \icp_wb__ack + wire output 296 \icp_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 28 input 346 \icp_wb__adr + wire width 28 input 302 \icp_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 341 \icp_wb__cyc + wire input 297 \icp_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 output 342 \icp_wb__dat_r + wire width 32 output 298 \icp_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 32 input 343 \icp_wb__dat_w + wire width 32 input 299 \icp_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire width 4 input 347 \icp_wb__sel + wire width 4 input 303 \icp_wb__sel attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 344 \icp_wb__stb + wire input 300 \icp_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" - wire input 345 \icp_wb__we + wire input 301 \icp_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire output 353 \ics_wb__ack + wire output 309 \ics_wb__ack attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 28 input 348 \ics_wb__adr + wire width 28 input 304 \ics_wb__adr attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 350 \ics_wb__cyc + wire input 306 \ics_wb__cyc attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 output 352 \ics_wb__dat_r + wire width 32 output 308 \ics_wb__dat_r attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire width 32 input 354 \ics_wb__dat_w + wire width 32 input 310 \ics_wb__dat_w attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 351 \ics_wb__stb + wire input 307 \ics_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" - wire input 355 \ics_wb__we + wire input 311 \ics_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" wire width 48 \imem_a_pc_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" @@ -403975,15 +376490,15 @@ module \ti wire \imem_f_valid_i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:93" wire \imem_wb_icache_en - attribute \src "libresoc.v:193965.7-193965.15" + attribute \src "libresoc.v:196414.7-196414.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:253" wire \insn_done attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" - wire width 16 input 349 \int_level_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:623" + wire width 16 input 305 \int_level_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:624" wire \is_last - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:857" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:858" wire \is_svp64_mode attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" wire width 3 \issue_fsm_state @@ -404006,74 +376521,58 @@ module \ti attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/bus.py:15" wire \jtag_dmi0__we_i attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire input 336 \jtag_wb__ack + wire input 292 \jtag_wb__ack attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 29 output 330 \jtag_wb__adr + wire width 29 output 286 \jtag_wb__adr attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 332 \jtag_wb__cyc + wire output 288 \jtag_wb__cyc attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 64 input 337 \jtag_wb__dat_r + wire width 64 input 293 \jtag_wb__dat_r attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire width 64 output 335 \jtag_wb__dat_w + wire width 64 output 291 \jtag_wb__dat_w attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 331 \jtag_wb__sel + wire output 287 \jtag_wb__sel attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 333 \jtag_wb__stb + wire output 289 \jtag_wb__stb attribute \src "/home/lkcl/src/libresoc/c4m-jtag/c4m/nmigen/jtag/tap.py:740" - wire output 334 \jtag_wb__we + wire output 290 \jtag_wb__we attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 75 \mspi0_clk__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 228 \mspi0_clk__pad__o + wire output 206 \mspi0_clk__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 76 \mspi0_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 229 \mspi0_cs_n__pad__o + wire output 207 \mspi0_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 231 \mspi0_miso__core__i + wire output 209 \mspi0_miso__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 78 \mspi0_miso__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" wire input 77 \mspi0_mosi__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 230 \mspi0_mosi__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 79 \mspi1_clk__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 232 \mspi1_clk__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 80 \mspi1_cs_n__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 233 \mspi1_cs_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 235 \mspi1_miso__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 82 \mspi1_miso__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 81 \mspi1_mosi__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 234 \mspi1_mosi__pad__o + wire output 208 \mspi0_mosi__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275" wire \msr_read attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:275" wire \msr_read$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 86 \mtwi_scl__core__o + wire input 82 \mtwi_scl__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 239 \mtwi_scl__pad__o + wire output 213 \mtwi_scl__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 236 \mtwi_sda__core__i + wire output 210 \mtwi_sda__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 84 \mtwi_sda__core__o + wire input 80 \mtwi_sda__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 85 \mtwi_sda__core__oe + wire input 81 \mtwi_sda__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 83 \mtwi_sda__pad__i + wire input 79 \mtwi_sda__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 237 \mtwi_sda__pad__o + wire output 211 \mtwi_sda__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 238 \mtwi_sda__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:999" + wire output 212 \mtwi_sda__pad__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1000" wire width 64 \new_dec attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:28" wire width 7 \new_svstate_dststep @@ -404087,21 +376586,21 @@ module \ti wire width 2 \new_svstate_svstep attribute \src "/home/lkcl/src/libresoc/soc/src/soc/sv/svstate.py:30" wire width 7 \new_svstate_vl - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1016" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1017" wire width 64 \new_tb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:506" wire width 7 \next_dststep attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:505" wire width 7 \next_srcstep - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:846" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:847" wire width 64 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:846" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:847" wire width 64 \nia$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:61" wire width 64 \pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:827" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" wire \pc_changed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:827" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" wire \pc_changed$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire width 64 input 7 \pc_i @@ -404113,377 +376612,305 @@ module \ti wire \pc_ok_delay attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:62" wire \pc_ok_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:784" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" wire \por_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:872" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:873" wire \pred_insn_ready_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:871" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:872" wire \pred_insn_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:877" wire \pred_mask_ready_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:875" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:876" wire \pred_mask_valid_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 87 \pwm_0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 240 \pwm_0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 88 \pwm_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 241 \pwm_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 92 \sd0_clk__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 245 \sd0_clk__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 242 \sd0_cmd__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 90 \sd0_cmd__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 91 \sd0_cmd__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 89 \sd0_cmd__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 243 \sd0_cmd__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 244 \sd0_cmd__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 246 \sd0_data0__core__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 94 \sd0_data0__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 95 \sd0_data0__core__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 93 \sd0_data0__pad__i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 247 \sd0_data0__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 248 \sd0_data0__pad__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 249 \sd0_data1__core__i + wire input 108 \sdr_a_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 97 \sd0_data1__core__o + wire output 239 \sdr_a_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 98 \sd0_data1__core__oe + wire input 126 \sdr_a_10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 96 \sd0_data1__pad__i + wire output 257 \sdr_a_10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 250 \sd0_data1__pad__o + wire input 127 \sdr_a_11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 251 \sd0_data1__pad__oe + wire output 258 \sdr_a_11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 252 \sd0_data2__core__i + wire input 128 \sdr_a_12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 100 \sd0_data2__core__o + wire output 259 \sdr_a_12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 101 \sd0_data2__core__oe + wire input 109 \sdr_a_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 99 \sd0_data2__pad__i + wire output 240 \sdr_a_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 253 \sd0_data2__pad__o + wire input 110 \sdr_a_2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 254 \sd0_data2__pad__oe + wire output 241 \sdr_a_2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 255 \sd0_data3__core__i + wire input 111 \sdr_a_3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 103 \sd0_data3__core__o + wire output 242 \sdr_a_3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 104 \sd0_data3__core__oe + wire input 112 \sdr_a_4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 102 \sd0_data3__pad__i + wire output 243 \sdr_a_4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 256 \sd0_data3__pad__o + wire input 113 \sdr_a_5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 257 \sd0_data3__pad__oe + wire output 244 \sdr_a_5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 130 \sdr_a_0__core__o + wire input 114 \sdr_a_6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 283 \sdr_a_0__pad__o + wire output 245 \sdr_a_6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 148 \sdr_a_10__core__o + wire input 115 \sdr_a_7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 301 \sdr_a_10__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 149 \sdr_a_11__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 302 \sdr_a_11__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 150 \sdr_a_12__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 303 \sdr_a_12__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 131 \sdr_a_1__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 284 \sdr_a_1__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 132 \sdr_a_2__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 285 \sdr_a_2__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 133 \sdr_a_3__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 286 \sdr_a_3__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 134 \sdr_a_4__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 287 \sdr_a_4__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 135 \sdr_a_5__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 288 \sdr_a_5__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 136 \sdr_a_6__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 289 \sdr_a_6__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 137 \sdr_a_7__core__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 290 \sdr_a_7__pad__o + wire output 246 \sdr_a_7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 138 \sdr_a_8__core__o + wire input 116 \sdr_a_8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 291 \sdr_a_8__pad__o + wire output 247 \sdr_a_8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 139 \sdr_a_9__core__o + wire input 117 \sdr_a_9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 292 \sdr_a_9__pad__o + wire output 248 \sdr_a_9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 140 \sdr_ba_0__core__o + wire input 118 \sdr_ba_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 293 \sdr_ba_0__pad__o + wire output 249 \sdr_ba_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 141 \sdr_ba_1__core__o + wire input 119 \sdr_ba_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 294 \sdr_ba_1__pad__o + wire output 250 \sdr_ba_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 145 \sdr_cas_n__core__o + wire input 123 \sdr_cas_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 298 \sdr_cas_n__pad__o + wire output 254 \sdr_cas_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 143 \sdr_cke__core__o + wire input 121 \sdr_cke__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 296 \sdr_cke__pad__o + wire output 252 \sdr_cke__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 142 \sdr_clock__core__o + wire input 120 \sdr_clock__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 295 \sdr_clock__pad__o + wire output 251 \sdr_clock__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 147 \sdr_cs_n__core__o + wire input 125 \sdr_cs_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 300 \sdr_cs_n__pad__o + wire output 256 \sdr_cs_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 105 \sdr_dm_0__core__o + wire input 83 \sdr_dm_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 258 \sdr_dm_0__pad__o + wire output 214 \sdr_dm_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 151 \sdr_dm_1__core__o + wire input 129 \sdr_dm_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 304 \sdr_dm_1__pad__o + wire output 260 \sdr_dm_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 259 \sdr_dq_0__core__i + wire output 215 \sdr_dq_0__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 107 \sdr_dq_0__core__o + wire input 85 \sdr_dq_0__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 108 \sdr_dq_0__core__oe + wire input 86 \sdr_dq_0__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 106 \sdr_dq_0__pad__i + wire input 84 \sdr_dq_0__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 260 \sdr_dq_0__pad__o + wire output 216 \sdr_dq_0__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 261 \sdr_dq_0__pad__oe + wire output 217 \sdr_dq_0__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 311 \sdr_dq_10__core__i + wire output 267 \sdr_dq_10__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 159 \sdr_dq_10__core__o + wire input 137 \sdr_dq_10__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 160 \sdr_dq_10__core__oe + wire input 138 \sdr_dq_10__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 158 \sdr_dq_10__pad__i + wire input 136 \sdr_dq_10__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 312 \sdr_dq_10__pad__o + wire output 268 \sdr_dq_10__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 313 \sdr_dq_10__pad__oe + wire output 269 \sdr_dq_10__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 314 \sdr_dq_11__core__i + wire output 270 \sdr_dq_11__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 162 \sdr_dq_11__core__o + wire input 140 \sdr_dq_11__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 163 \sdr_dq_11__core__oe + wire input 141 \sdr_dq_11__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 161 \sdr_dq_11__pad__i + wire input 139 \sdr_dq_11__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 315 \sdr_dq_11__pad__o + wire output 271 \sdr_dq_11__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 316 \sdr_dq_11__pad__oe + wire output 272 \sdr_dq_11__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 317 \sdr_dq_12__core__i + wire output 273 \sdr_dq_12__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 165 \sdr_dq_12__core__o + wire input 143 \sdr_dq_12__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 166 \sdr_dq_12__core__oe + wire input 144 \sdr_dq_12__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 164 \sdr_dq_12__pad__i + wire input 142 \sdr_dq_12__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 318 \sdr_dq_12__pad__o + wire output 274 \sdr_dq_12__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 319 \sdr_dq_12__pad__oe + wire output 275 \sdr_dq_12__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 320 \sdr_dq_13__core__i + wire output 276 \sdr_dq_13__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 168 \sdr_dq_13__core__o + wire input 146 \sdr_dq_13__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 169 \sdr_dq_13__core__oe + wire input 147 \sdr_dq_13__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 167 \sdr_dq_13__pad__i + wire input 145 \sdr_dq_13__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 321 \sdr_dq_13__pad__o + wire output 277 \sdr_dq_13__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 322 \sdr_dq_13__pad__oe + wire output 278 \sdr_dq_13__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 323 \sdr_dq_14__core__i + wire output 279 \sdr_dq_14__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 171 \sdr_dq_14__core__o + wire input 149 \sdr_dq_14__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 172 \sdr_dq_14__core__oe + wire input 150 \sdr_dq_14__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 170 \sdr_dq_14__pad__i + wire input 148 \sdr_dq_14__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 324 \sdr_dq_14__pad__o + wire output 280 \sdr_dq_14__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 325 \sdr_dq_14__pad__oe + wire output 281 \sdr_dq_14__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 326 \sdr_dq_15__core__i + wire output 282 \sdr_dq_15__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 174 \sdr_dq_15__core__o + wire input 152 \sdr_dq_15__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 175 \sdr_dq_15__core__oe + wire input 153 \sdr_dq_15__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 173 \sdr_dq_15__pad__i + wire input 151 \sdr_dq_15__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 327 \sdr_dq_15__pad__o + wire output 283 \sdr_dq_15__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 328 \sdr_dq_15__pad__oe + wire output 284 \sdr_dq_15__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 262 \sdr_dq_1__core__i + wire output 218 \sdr_dq_1__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 110 \sdr_dq_1__core__o + wire input 88 \sdr_dq_1__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 111 \sdr_dq_1__core__oe + wire input 89 \sdr_dq_1__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 109 \sdr_dq_1__pad__i + wire input 87 \sdr_dq_1__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 263 \sdr_dq_1__pad__o + wire output 219 \sdr_dq_1__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 264 \sdr_dq_1__pad__oe + wire output 220 \sdr_dq_1__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 265 \sdr_dq_2__core__i + wire output 221 \sdr_dq_2__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 113 \sdr_dq_2__core__o + wire input 91 \sdr_dq_2__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 114 \sdr_dq_2__core__oe + wire input 92 \sdr_dq_2__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 112 \sdr_dq_2__pad__i + wire input 90 \sdr_dq_2__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 266 \sdr_dq_2__pad__o + wire output 222 \sdr_dq_2__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 267 \sdr_dq_2__pad__oe + wire output 223 \sdr_dq_2__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 268 \sdr_dq_3__core__i + wire output 224 \sdr_dq_3__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 116 \sdr_dq_3__core__o + wire input 94 \sdr_dq_3__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 117 \sdr_dq_3__core__oe + wire input 95 \sdr_dq_3__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 115 \sdr_dq_3__pad__i + wire input 93 \sdr_dq_3__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 269 \sdr_dq_3__pad__o + wire output 225 \sdr_dq_3__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 270 \sdr_dq_3__pad__oe + wire output 226 \sdr_dq_3__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 271 \sdr_dq_4__core__i + wire output 227 \sdr_dq_4__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 119 \sdr_dq_4__core__o + wire input 97 \sdr_dq_4__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 120 \sdr_dq_4__core__oe + wire input 98 \sdr_dq_4__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 118 \sdr_dq_4__pad__i + wire input 96 \sdr_dq_4__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 272 \sdr_dq_4__pad__o + wire output 228 \sdr_dq_4__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 273 \sdr_dq_4__pad__oe + wire output 229 \sdr_dq_4__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 274 \sdr_dq_5__core__i + wire output 230 \sdr_dq_5__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 122 \sdr_dq_5__core__o + wire input 100 \sdr_dq_5__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 123 \sdr_dq_5__core__oe + wire input 101 \sdr_dq_5__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 121 \sdr_dq_5__pad__i + wire input 99 \sdr_dq_5__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 275 \sdr_dq_5__pad__o + wire output 231 \sdr_dq_5__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 276 \sdr_dq_5__pad__oe + wire output 232 \sdr_dq_5__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 277 \sdr_dq_6__core__i + wire output 233 \sdr_dq_6__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 125 \sdr_dq_6__core__o + wire input 103 \sdr_dq_6__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 126 \sdr_dq_6__core__oe + wire input 104 \sdr_dq_6__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 124 \sdr_dq_6__pad__i + wire input 102 \sdr_dq_6__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 278 \sdr_dq_6__pad__o + wire output 234 \sdr_dq_6__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 279 \sdr_dq_6__pad__oe + wire output 235 \sdr_dq_6__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 280 \sdr_dq_7__core__i + wire output 236 \sdr_dq_7__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 128 \sdr_dq_7__core__o + wire input 106 \sdr_dq_7__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 129 \sdr_dq_7__core__oe + wire input 107 \sdr_dq_7__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 127 \sdr_dq_7__pad__i + wire input 105 \sdr_dq_7__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 281 \sdr_dq_7__pad__o + wire output 237 \sdr_dq_7__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 282 \sdr_dq_7__pad__oe + wire output 238 \sdr_dq_7__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 305 \sdr_dq_8__core__i + wire output 261 \sdr_dq_8__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 153 \sdr_dq_8__core__o + wire input 131 \sdr_dq_8__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 154 \sdr_dq_8__core__oe + wire input 132 \sdr_dq_8__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 152 \sdr_dq_8__pad__i + wire input 130 \sdr_dq_8__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 306 \sdr_dq_8__pad__o + wire output 262 \sdr_dq_8__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 307 \sdr_dq_8__pad__oe + wire output 263 \sdr_dq_8__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 308 \sdr_dq_9__core__i + wire output 264 \sdr_dq_9__core__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 156 \sdr_dq_9__core__o + wire input 134 \sdr_dq_9__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 157 \sdr_dq_9__core__oe + wire input 135 \sdr_dq_9__core__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 155 \sdr_dq_9__pad__i + wire input 133 \sdr_dq_9__pad__i attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 309 \sdr_dq_9__pad__o + wire output 265 \sdr_dq_9__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 310 \sdr_dq_9__pad__oe + wire output 266 \sdr_dq_9__pad__oe attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 144 \sdr_ras_n__core__o + wire input 122 \sdr_ras_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 297 \sdr_ras_n__pad__o + wire output 253 \sdr_ras_n__pad__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire input 146 \sdr_we_n__core__o + wire input 124 \sdr_we_n__core__o attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/jtag.py:74" - wire output 299 \sdr_we_n__pad__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" + wire output 255 \sdr_we_n__pad__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:829" wire \sv_changed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:828" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:829" wire \sv_changed$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:61" wire width 64 \svstate @@ -404495,7 +376922,7 @@ module \ti wire \svstate_ok_delay attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:62" wire \svstate_ok_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:789" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:790" wire \ti_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:498" wire \update_svstate @@ -404510,7 +376937,7 @@ module \ti attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" wire width 4 \xics_ics_icp_o_src attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:349" - cell $add $add$libresoc.v:196328$13493 + cell $add $add$libresoc.v:198689$13479 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -404518,10 +376945,10 @@ module \ti parameter \Y_WIDTH 65 connect \A \dec2_cur_pc connect \B 3'100 - connect \Y $add$libresoc.v:196328$13493_Y + connect \Y $add$libresoc.v:198689$13479_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:507" - cell $add $add$libresoc.v:196340$13504 + cell $add $add$libresoc.v:198701$13490 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -404529,10 +376956,10 @@ module \ti parameter \Y_WIDTH 8 connect \A \cur_cur_srcstep connect \B 1'1 - connect \Y $add$libresoc.v:196340$13504_Y + connect \Y $add$libresoc.v:198701$13490_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:508" - cell $add $add$libresoc.v:196341$13505 + cell $add $add$libresoc.v:198702$13491 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -404540,10 +376967,10 @@ module \ti parameter \Y_WIDTH 8 connect \A \cur_cur_dststep connect \B 1'1 - connect \Y $add$libresoc.v:196341$13505_Y + connect \Y $add$libresoc.v:198702$13491_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1017" - cell $add $add$libresoc.v:196411$13575 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1018" + cell $add $add$libresoc.v:198772$13561 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -404551,10 +376978,10 @@ module \ti parameter \Y_WIDTH 65 connect \A \core_issue__data_o connect \B 1'1 - connect \Y $add$libresoc.v:196411$13575_Y + connect \Y $add$libresoc.v:198772$13561_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:338" - cell $add $add$libresoc.v:196445$13608 + cell $add $add$libresoc.v:198806$13594 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -404562,10 +376989,10 @@ module \ti parameter \Y_WIDTH 65 connect \A \dec2_cur_pc connect \B 3'100 - connect \Y $add$libresoc.v:196445$13608_Y + connect \Y $add$libresoc.v:198806$13594_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $and $and$libresoc.v:196333$13498 + cell $and $and$libresoc.v:198694$13484 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -404573,10 +377000,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$106 connect \B \$108 - connect \Y $and$libresoc.v:196333$13498_Y + connect \Y $and$libresoc.v:198694$13484_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $and $and$libresoc.v:196336$13501 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" + cell $and $and$libresoc.v:198697$13487 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -404584,10 +377011,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$112 connect \B \$114 - connect \Y $and$libresoc.v:196336$13501_Y + connect \Y $and$libresoc.v:198697$13487_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $and $and$libresoc.v:196344$13508 + cell $and $and$libresoc.v:198705$13494 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -404595,10 +377022,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$130 connect \B \$132 - connect \Y $and$libresoc.v:196344$13508_Y + connect \Y $and$libresoc.v:198705$13494_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $and $and$libresoc.v:196347$13511 + cell $and $and$libresoc.v:198708$13497 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -404606,10 +377033,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$136 connect \B \$138 - connect \Y $and$libresoc.v:196347$13511_Y + connect \Y $and$libresoc.v:198708$13497_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" - cell $and $and$libresoc.v:196349$13513 + cell $and $and$libresoc.v:198710$13499 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -404617,10 +377044,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \is_svp64_mode connect \B \$142 - connect \Y $and$libresoc.v:196349$13513_Y + connect \Y $and$libresoc.v:198710$13499_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $and $and$libresoc.v:196352$13516 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" + cell $and $and$libresoc.v:198713$13502 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -404628,10 +377055,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$146 connect \B \$148 - connect \Y $and$libresoc.v:196352$13516_Y + connect \Y $and$libresoc.v:198713$13502_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $and $and$libresoc.v:196358$13521 + cell $and $and$libresoc.v:198719$13507 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -404639,10 +377066,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$158 connect \B \$160 - connect \Y $and$libresoc.v:196358$13521_Y + connect \Y $and$libresoc.v:198719$13507_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $and $and$libresoc.v:196361$13524 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" + cell $and $and$libresoc.v:198722$13510 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -404650,10 +377077,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$164 connect \B \$166 - connect \Y $and$libresoc.v:196361$13524_Y + connect \Y $and$libresoc.v:198722$13510_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $and $and$libresoc.v:196364$13527 + cell $and $and$libresoc.v:198725$13513 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -404661,10 +377088,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$170 connect \B \$172 - connect \Y $and$libresoc.v:196364$13527_Y + connect \Y $and$libresoc.v:198725$13513_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $and $and$libresoc.v:196367$13530 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" + cell $and $and$libresoc.v:198728$13516 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -404672,10 +377099,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$176 connect \B \$178 - connect \Y $and$libresoc.v:196367$13530_Y + connect \Y $and$libresoc.v:198728$13516_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $and $and$libresoc.v:196370$13533 + cell $and $and$libresoc.v:198731$13519 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -404683,10 +377110,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$182 connect \B \$184 - connect \Y $and$libresoc.v:196370$13533_Y + connect \Y $and$libresoc.v:198731$13519_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $and $and$libresoc.v:196373$13536 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" + cell $and $and$libresoc.v:198734$13522 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -404694,10 +377121,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$188 connect \B \$190 - connect \Y $and$libresoc.v:196373$13536_Y + connect \Y $and$libresoc.v:198734$13522_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:728" - cell $and $and$libresoc.v:196374$13537 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:729" + cell $and $and$libresoc.v:198735$13523 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -404705,10 +377132,10 @@ module \ti parameter \Y_WIDTH 3 connect \A \core_state_nia_wen connect \B 1'1 - connect \Y $and$libresoc.v:196374$13537_Y + connect \Y $and$libresoc.v:198735$13523_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $and $and$libresoc.v:196378$13541 + cell $and $and$libresoc.v:198739$13527 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -404716,10 +377143,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$198 connect \B \$200 - connect \Y $and$libresoc.v:196378$13541_Y + connect \Y $and$libresoc.v:198739$13527_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $and $and$libresoc.v:196381$13544 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" + cell $and $and$libresoc.v:198742$13530 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -404727,10 +377154,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$204 connect \B \$206 - connect \Y $and$libresoc.v:196381$13544_Y + connect \Y $and$libresoc.v:198742$13530_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $and $and$libresoc.v:196387$13549 + cell $and $and$libresoc.v:198748$13535 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -404738,10 +377165,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$216 connect \B \$218 - connect \Y $and$libresoc.v:196387$13549_Y + connect \Y $and$libresoc.v:198748$13535_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $and $and$libresoc.v:196390$13552 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" + cell $and $and$libresoc.v:198751$13538 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -404749,10 +377176,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$222 connect \B \$224 - connect \Y $and$libresoc.v:196390$13552_Y + connect \Y $and$libresoc.v:198751$13538_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:726" - cell $and $and$libresoc.v:196391$13553 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:727" + cell $and $and$libresoc.v:198752$13539 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \B_SIGNED 0 @@ -404760,10 +377187,10 @@ module \ti parameter \Y_WIDTH 3 connect \A \core_state_nia_wen connect \B 3'100 - connect \Y $and$libresoc.v:196391$13553_Y + connect \Y $and$libresoc.v:198752$13539_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" - cell $and $and$libresoc.v:196394$13556 + cell $and $and$libresoc.v:198755$13542 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -404771,10 +377198,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \is_svp64_mode connect \B \$232 - connect \Y $and$libresoc.v:196394$13556_Y + connect \Y $and$libresoc.v:198755$13542_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $and $and$libresoc.v:196399$13561 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" + cell $and $and$libresoc.v:198760$13547 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -404782,10 +377209,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$238 connect \B \$240 - connect \Y $and$libresoc.v:196399$13561_Y + connect \Y $and$libresoc.v:198760$13547_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $and $and$libresoc.v:196402$13564 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" + cell $and $and$libresoc.v:198763$13550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -404793,10 +377220,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$244 connect \B \$246 - connect \Y $and$libresoc.v:196402$13564_Y + connect \Y $and$libresoc.v:198763$13550_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:196417$13581 + cell $and $and$libresoc.v:198778$13567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -404804,10 +377231,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \core_cu_st__rel_o connect \B \$34 - connect \Y $and$libresoc.v:196417$13581_Y + connect \Y $and$libresoc.v:198778$13567_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $and $and$libresoc.v:196423$13588 + cell $and $and$libresoc.v:198784$13574 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -404815,10 +377242,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$44 connect \B \$46 - connect \Y $and$libresoc.v:196423$13588_Y + connect \Y $and$libresoc.v:198784$13574_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" - cell $and $and$libresoc.v:196425$13590 + cell $and $and$libresoc.v:198786$13576 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -404826,10 +377253,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \is_svp64_mode connect \B \$50 - connect \Y $and$libresoc.v:196425$13590_Y + connect \Y $and$libresoc.v:198786$13576_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $and $and$libresoc.v:196428$13593 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" + cell $and $and$libresoc.v:198789$13579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -404837,10 +377264,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$54 connect \B \$56 - connect \Y $and$libresoc.v:196428$13593_Y + connect \Y $and$libresoc.v:198789$13579_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $and $and$libresoc.v:196434$13598 + cell $and $and$libresoc.v:198795$13584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -404848,10 +377275,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$66 connect \B \$68 - connect \Y $and$libresoc.v:196434$13598_Y + connect \Y $and$libresoc.v:198795$13584_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" - cell $and $and$libresoc.v:196436$13600 + cell $and $and$libresoc.v:198797$13586 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -404859,10 +377286,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \is_svp64_mode connect \B \$72 - connect \Y $and$libresoc.v:196436$13600_Y + connect \Y $and$libresoc.v:198797$13586_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $and $and$libresoc.v:196439$13603 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" + cell $and $and$libresoc.v:198800$13589 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -404870,10 +377297,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$76 connect \B \$78 - connect \Y $and$libresoc.v:196439$13603_Y + connect \Y $and$libresoc.v:198800$13589_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" - cell $eq $eq$libresoc.v:196348$13512 + cell $eq $eq$libresoc.v:198709$13498 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -404881,10 +377308,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \cur_cur_vl connect \B 1'0 - connect \Y $eq$libresoc.v:196348$13512_Y + connect \Y $eq$libresoc.v:198709$13498_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" - cell $eq $eq$libresoc.v:196393$13555 + cell $eq $eq$libresoc.v:198754$13541 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -404892,10 +377319,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \cur_cur_vl connect \B 1'0 - connect \Y $eq$libresoc.v:196393$13555_Y + connect \Y $eq$libresoc.v:198754$13541_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:625" - cell $eq $eq$libresoc.v:196403$13565 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:626" + cell $eq $eq$libresoc.v:198764$13551 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -404903,10 +377330,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \next_srcstep connect \B \cur_cur_vl - connect \Y $eq$libresoc.v:196403$13565_Y + connect \Y $eq$libresoc.v:198764$13551_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" - cell $eq $eq$libresoc.v:196424$13589 + cell $eq $eq$libresoc.v:198785$13575 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -404914,10 +377341,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \cur_cur_vl connect \B 1'0 - connect \Y $eq$libresoc.v:196424$13589_Y + connect \Y $eq$libresoc.v:198785$13575_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" - cell $eq $eq$libresoc.v:196435$13599 + cell $eq $eq$libresoc.v:198796$13585 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -404925,34 +377352,34 @@ module \ti parameter \Y_WIDTH 1 connect \A \cur_cur_vl connect \B 1'0 - connect \Y $eq$libresoc.v:196435$13599_Y + connect \Y $eq$libresoc.v:198796$13585_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $extend$libresoc.v:196408$13570 + cell $pos $extend$libresoc.v:198769$13556 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \core_full_rd2__data_o - connect \Y $extend$libresoc.v:196408$13570_Y + connect \Y $extend$libresoc.v:198769$13556_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $extend$libresoc.v:196409$13572 + cell $pos $extend$libresoc.v:198770$13558 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 64 connect \A \core_full_rd__data_o - connect \Y $extend$libresoc.v:196409$13572_Y + connect \Y $extend$libresoc.v:198770$13558_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $extend$libresoc.v:196420$13584 + cell $pos $extend$libresoc.v:198781$13570 parameter \A_SIGNED 0 parameter \A_WIDTH 32 parameter \Y_WIDTH 64 connect \A \svstate_i - connect \Y $extend$libresoc.v:196420$13584_Y + connect \Y $extend$libresoc.v:198781$13570_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - cell $mul $mul$libresoc.v:196329$13494 + cell $mul $mul$libresoc.v:198690$13480 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -404960,10 +377387,10 @@ module \ti parameter \Y_WIDTH 7 connect \A \$100 [2] connect \B 6'100000 - connect \Y $mul$libresoc.v:196329$13494_Y + connect \Y $mul$libresoc.v:198690$13480_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - cell $mul $mul$libresoc.v:196446$13609 + cell $mul $mul$libresoc.v:198807$13595 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -404971,10 +377398,10 @@ module \ti parameter \Y_WIDTH 7 connect \A \dec2_cur_pc [2] connect \B 6'100000 - connect \Y $mul$libresoc.v:196446$13609_Y + connect \Y $mul$libresoc.v:198807$13595_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:791" - cell $ne $ne$libresoc.v:196397$13559 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" + cell $ne $ne$libresoc.v:198758$13545 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -404982,10 +377409,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \delay connect \B 1'0 - connect \Y $ne$libresoc.v:196397$13559_Y + connect \Y $ne$libresoc.v:198758$13545_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:723" - cell $ne $ne$libresoc.v:196405$13567 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:724" + cell $ne $ne$libresoc.v:198766$13553 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \B_SIGNED 0 @@ -404993,10 +377420,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \core_core_core_insn_type connect \B 7'0000001 - connect \Y $ne$libresoc.v:196405$13567_Y + connect \Y $ne$libresoc.v:198766$13553_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:797" - cell $ne $ne$libresoc.v:196415$13579 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" + cell $ne $ne$libresoc.v:198776$13565 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -405004,410 +377431,410 @@ module \ti parameter \Y_WIDTH 1 connect \A \delay connect \B \$30 - connect \Y $ne$libresoc.v:196415$13579_Y + connect \Y $ne$libresoc.v:198776$13565_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:196331$13496 + cell $not $not$libresoc.v:198692$13482 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:196331$13496_Y + connect \Y $not$libresoc.v:198692$13482_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:196332$13497 + cell $not $not$libresoc.v:198693$13483 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:196332$13497_Y + connect \Y $not$libresoc.v:198693$13483_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:196334$13499 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" + cell $not $not$libresoc.v:198695$13485 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:196334$13499_Y + connect \Y $not$libresoc.v:198695$13485_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:196335$13500 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" + cell $not $not$libresoc.v:198696$13486 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:196335$13500_Y + connect \Y $not$libresoc.v:198696$13486_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:196342$13506 + cell $not $not$libresoc.v:198703$13492 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:196342$13506_Y + connect \Y $not$libresoc.v:198703$13492_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:196343$13507 + cell $not $not$libresoc.v:198704$13493 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:196343$13507_Y + connect \Y $not$libresoc.v:198704$13493_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:196345$13509 + cell $not $not$libresoc.v:198706$13495 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:196345$13509_Y + connect \Y $not$libresoc.v:198706$13495_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:196346$13510 + cell $not $not$libresoc.v:198707$13496 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:196346$13510_Y + connect \Y $not$libresoc.v:198707$13496_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:196350$13514 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" + cell $not $not$libresoc.v:198711$13500 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:196350$13514_Y + connect \Y $not$libresoc.v:198711$13500_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:196351$13515 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" + cell $not $not$libresoc.v:198712$13501 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:196351$13515_Y + connect \Y $not$libresoc.v:198712$13501_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:196356$13519 + cell $not $not$libresoc.v:198717$13505 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:196356$13519_Y + connect \Y $not$libresoc.v:198717$13505_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:196357$13520 + cell $not $not$libresoc.v:198718$13506 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:196357$13520_Y + connect \Y $not$libresoc.v:198718$13506_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:196359$13522 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" + cell $not $not$libresoc.v:198720$13508 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:196359$13522_Y + connect \Y $not$libresoc.v:198720$13508_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:196360$13523 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" + cell $not $not$libresoc.v:198721$13509 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:196360$13523_Y + connect \Y $not$libresoc.v:198721$13509_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:196362$13525 + cell $not $not$libresoc.v:198723$13511 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:196362$13525_Y + connect \Y $not$libresoc.v:198723$13511_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:196363$13526 + cell $not $not$libresoc.v:198724$13512 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:196363$13526_Y + connect \Y $not$libresoc.v:198724$13512_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:196365$13528 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" + cell $not $not$libresoc.v:198726$13514 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:196365$13528_Y + connect \Y $not$libresoc.v:198726$13514_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:196366$13529 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" + cell $not $not$libresoc.v:198727$13515 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:196366$13529_Y + connect \Y $not$libresoc.v:198727$13515_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:196368$13531 + cell $not $not$libresoc.v:198729$13517 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:196368$13531_Y + connect \Y $not$libresoc.v:198729$13517_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:196369$13532 + cell $not $not$libresoc.v:198730$13518 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:196369$13532_Y + connect \Y $not$libresoc.v:198730$13518_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:196371$13534 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" + cell $not $not$libresoc.v:198732$13520 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:196371$13534_Y + connect \Y $not$libresoc.v:198732$13520_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:196372$13535 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" + cell $not $not$libresoc.v:198733$13521 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:196372$13535_Y + connect \Y $not$libresoc.v:198733$13521_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:196376$13539 + cell $not $not$libresoc.v:198737$13525 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:196376$13539_Y + connect \Y $not$libresoc.v:198737$13525_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:196377$13540 + cell $not $not$libresoc.v:198738$13526 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:196377$13540_Y + connect \Y $not$libresoc.v:198738$13526_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:196379$13542 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" + cell $not $not$libresoc.v:198740$13528 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:196379$13542_Y + connect \Y $not$libresoc.v:198740$13528_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:196380$13543 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" + cell $not $not$libresoc.v:198741$13529 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:196380$13543_Y + connect \Y $not$libresoc.v:198741$13529_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:196385$13547 + cell $not $not$libresoc.v:198746$13533 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:196385$13547_Y + connect \Y $not$libresoc.v:198746$13533_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:196386$13548 + cell $not $not$libresoc.v:198747$13534 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:196386$13548_Y + connect \Y $not$libresoc.v:198747$13534_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:196388$13550 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" + cell $not $not$libresoc.v:198749$13536 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:196388$13550_Y + connect \Y $not$libresoc.v:198749$13536_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:196389$13551 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" + cell $not $not$libresoc.v:198750$13537 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:196389$13551_Y + connect \Y $not$libresoc.v:198750$13537_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" - cell $not $not$libresoc.v:196395$13557 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:731" + cell $not $not$libresoc.v:198756$13543 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_corebusy_o - connect \Y $not$libresoc.v:196395$13557_Y + connect \Y $not$libresoc.v:198756$13543_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:196396$13558 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" + cell $not $not$libresoc.v:198757$13544 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:196396$13558_Y + connect \Y $not$libresoc.v:198757$13544_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:196398$13560 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" + cell $not $not$libresoc.v:198759$13546 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:196398$13560_Y + connect \Y $not$libresoc.v:198759$13546_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:196400$13562 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" + cell $not $not$libresoc.v:198761$13548 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:196400$13562_Y + connect \Y $not$libresoc.v:198761$13548_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:196401$13563 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" + cell $not $not$libresoc.v:198762$13549 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:196401$13563_Y + connect \Y $not$libresoc.v:198762$13549_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" - cell $not $not$libresoc.v:196406$13568 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:731" + cell $not $not$libresoc.v:198767$13554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_corebusy_o - connect \Y $not$libresoc.v:196406$13568_Y + connect \Y $not$libresoc.v:198767$13554_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" - cell $not $not$libresoc.v:196407$13569 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:731" + cell $not $not$libresoc.v:198768$13555 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_corebusy_o - connect \Y $not$libresoc.v:196407$13569_Y + connect \Y $not$libresoc.v:198768$13555_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:196416$13580 + cell $not $not$libresoc.v:198777$13566 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \cu_st__rel_o_dly - connect \Y $not$libresoc.v:196416$13580_Y + connect \Y $not$libresoc.v:198777$13566_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:63" - cell $not $not$libresoc.v:196418$13582 + cell $not $not$libresoc.v:198779$13568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \pc_i_ok - connect \Y $not$libresoc.v:196418$13582_Y + connect \Y $not$libresoc.v:198779$13568_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:63" - cell $not $not$libresoc.v:196419$13583 + cell $not $not$libresoc.v:198780$13569 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \svstate_i_ok - connect \Y $not$libresoc.v:196419$13583_Y + connect \Y $not$libresoc.v:198780$13569_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:196421$13586 + cell $not $not$libresoc.v:198782$13572 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:196421$13586_Y + connect \Y $not$libresoc.v:198782$13572_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:196422$13587 + cell $not $not$libresoc.v:198783$13573 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:196422$13587_Y + connect \Y $not$libresoc.v:198783$13573_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:196426$13591 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" + cell $not $not$libresoc.v:198787$13577 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:196426$13591_Y + connect \Y $not$libresoc.v:198787$13577_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:196427$13592 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" + cell $not $not$libresoc.v:198788$13578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:196427$13592_Y + connect \Y $not$libresoc.v:198788$13578_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:196432$13596 + cell $not $not$libresoc.v:198793$13582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:196432$13596_Y + connect \Y $not$libresoc.v:198793$13582_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" - cell $not $not$libresoc.v:196433$13597 + cell $not $not$libresoc.v:198794$13583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:196433$13597_Y + connect \Y $not$libresoc.v:198794$13583_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:196437$13601 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" + cell $not $not$libresoc.v:198798$13587 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \dbg_core_stop_o - connect \Y $not$libresoc.v:196437$13601_Y + connect \Y $not$libresoc.v:198798$13587_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" - cell $not $not$libresoc.v:196438$13602 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" + cell $not $not$libresoc.v:198799$13588 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \core_coresync_rst - connect \Y $not$libresoc.v:196438$13602_Y + connect \Y $not$libresoc.v:198799$13588_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:302" - cell $not $not$libresoc.v:196443$13606 + cell $not $not$libresoc.v:198804$13592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msr_read - connect \Y $not$libresoc.v:196443$13606_Y + connect \Y $not$libresoc.v:198804$13592_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:302" - cell $not $not$libresoc.v:196444$13607 + cell $not $not$libresoc.v:198805$13593 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \msr_read - connect \Y $not$libresoc.v:196444$13607_Y + connect \Y $not$libresoc.v:198805$13593_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" - cell $or $or$libresoc.v:196337$13502 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" + cell $or $or$libresoc.v:198698$13488 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405415,10 +377842,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \pc_changed connect \B \sv_changed - connect \Y $or$libresoc.v:196337$13502_Y + connect \Y $or$libresoc.v:198698$13488_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" - cell $or $or$libresoc.v:196339$13503 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637" + cell $or $or$libresoc.v:198700$13489 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405426,10 +377853,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$120 connect \B \is_last - connect \Y $or$libresoc.v:196339$13503_Y + connect \Y $or$libresoc.v:198700$13489_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" - cell $or $or$libresoc.v:196353$13517 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" + cell $or $or$libresoc.v:198714$13503 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405437,10 +377864,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \pc_changed connect \B \sv_changed - connect \Y $or$libresoc.v:196353$13517_Y + connect \Y $or$libresoc.v:198714$13503_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" - cell $or $or$libresoc.v:196355$13518 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637" + cell $or $or$libresoc.v:198716$13504 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405448,10 +377875,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$154 connect \B \is_last - connect \Y $or$libresoc.v:196355$13518_Y + connect \Y $or$libresoc.v:198716$13504_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" - cell $or $or$libresoc.v:196382$13545 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" + cell $or $or$libresoc.v:198743$13531 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405459,10 +377886,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \pc_changed connect \B \sv_changed - connect \Y $or$libresoc.v:196382$13545_Y + connect \Y $or$libresoc.v:198743$13531_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" - cell $or $or$libresoc.v:196384$13546 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637" + cell $or $or$libresoc.v:198745$13532 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405470,10 +377897,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$212 connect \B \is_last - connect \Y $or$libresoc.v:196384$13546_Y + connect \Y $or$libresoc.v:198745$13532_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:797" - cell $or $or$libresoc.v:196413$13577 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" + cell $or $or$libresoc.v:198774$13563 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405481,10 +377908,10 @@ module \ti parameter \Y_WIDTH 1 connect \A 1'0 connect \B \dbg_core_rst_o - connect \Y $or$libresoc.v:196413$13577_Y + connect \Y $or$libresoc.v:198774$13563_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:797" - cell $or $or$libresoc.v:196414$13578 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:798" + cell $or $or$libresoc.v:198775$13564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405492,10 +377919,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$28 connect \B \rst - connect \Y $or$libresoc.v:196414$13578_Y + connect \Y $or$libresoc.v:198775$13564_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" - cell $or $or$libresoc.v:196429$13594 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" + cell $or $or$libresoc.v:198790$13580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405503,10 +377930,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \pc_changed connect \B \sv_changed - connect \Y $or$libresoc.v:196429$13594_Y + connect \Y $or$libresoc.v:198790$13580_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" - cell $or $or$libresoc.v:196431$13595 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637" + cell $or $or$libresoc.v:198792$13581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405514,10 +377941,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \$62 connect \B \is_last - connect \Y $or$libresoc.v:196431$13595_Y + connect \Y $or$libresoc.v:198792$13581_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" - cell $or $or$libresoc.v:196440$13604 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" + cell $or $or$libresoc.v:198801$13590 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405525,10 +377952,10 @@ module \ti parameter \Y_WIDTH 1 connect \A \pc_changed connect \B \sv_changed - connect \Y $or$libresoc.v:196440$13604_Y + connect \Y $or$libresoc.v:198801$13590_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:636" - cell $or $or$libresoc.v:196442$13605 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:637" + cell $or $or$libresoc.v:198803$13591 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -405536,58 +377963,58 @@ module \ti parameter \Y_WIDTH 1 connect \A \$84 connect \B \is_last - connect \Y $or$libresoc.v:196442$13605_Y + connect \Y $or$libresoc.v:198803$13591_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $pos$libresoc.v:196404$13566 + cell $pos $pos$libresoc.v:198765$13552 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 connect \A { 32'00000000000000000000000000000000 \new_svstate_maxvl \new_svstate_vl \new_svstate_srcstep \new_svstate_dststep \new_svstate_subvl \new_svstate_svstep } - connect \Y $pos$libresoc.v:196404$13566_Y + connect \Y $pos$libresoc.v:198765$13552_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $pos$libresoc.v:196408$13571 + cell $pos $pos$libresoc.v:198769$13557 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:196408$13570_Y - connect \Y $pos$libresoc.v:196408$13571_Y + connect \A $extend$libresoc.v:198769$13556_Y + connect \Y $pos$libresoc.v:198769$13557_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" - cell $pos $pos$libresoc.v:196409$13573 + cell $pos $pos$libresoc.v:198770$13559 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:196409$13572_Y - connect \Y $pos$libresoc.v:196409$13573_Y + connect \A $extend$libresoc.v:198770$13558_Y + connect \Y $pos$libresoc.v:198770$13559_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" - cell $pos $pos$libresoc.v:196420$13585 + cell $pos $pos$libresoc.v:198781$13571 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \Y_WIDTH 64 - connect \A $extend$libresoc.v:196420$13584_Y - connect \Y $pos$libresoc.v:196420$13585_Y + connect \A $extend$libresoc.v:198781$13570_Y + connect \Y $pos$libresoc.v:198781$13571_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:196375$13538 + cell $reduce_or $reduce_or$libresoc.v:198736$13524 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$195 - connect \Y $reduce_or$libresoc.v:196375$13538_Y + connect \Y $reduce_or$libresoc.v:198736$13524_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:196392$13554 + cell $reduce_or $reduce_or$libresoc.v:198753$13540 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \$229 - connect \Y $reduce_or$libresoc.v:196392$13554_Y + connect \Y $reduce_or$libresoc.v:198753$13540_Y end - attribute \src "libresoc.v:196330.18-196330.41" - cell $shr $shr$libresoc.v:196330$13495 + attribute \src "libresoc.v:198691.18-198691.41" + cell $shr $shr$libresoc.v:198691$13481 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -405595,10 +378022,10 @@ module \ti parameter \Y_WIDTH 64 connect \A \imem_f_instr_o connect \B \$103 - connect \Y $shr$libresoc.v:196330$13495_Y + connect \Y $shr$libresoc.v:198691$13481_Y end - attribute \src "libresoc.v:196447.18-196447.40" - cell $shr $shr$libresoc.v:196447$13610 + attribute \src "libresoc.v:198808.18-198808.40" + cell $shr $shr$libresoc.v:198808$13596 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -405606,10 +378033,10 @@ module \ti parameter \Y_WIDTH 64 connect \A \imem_f_instr_o connect \B \$96 - connect \Y $shr$libresoc.v:196447$13610_Y + connect \Y $shr$libresoc.v:198808$13596_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1001" - cell $sub $sub$libresoc.v:196410$13574 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:1002" + cell $sub $sub$libresoc.v:198771$13560 parameter \A_SIGNED 0 parameter \A_WIDTH 64 parameter \B_SIGNED 0 @@ -405617,10 +378044,10 @@ module \ti parameter \Y_WIDTH 65 connect \A \core_issue__data_o connect \B 1'1 - connect \Y $sub$libresoc.v:196410$13574_Y + connect \Y $sub$libresoc.v:198771$13560_Y end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" - cell $sub $sub$libresoc.v:196412$13576 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:793" + cell $sub $sub$libresoc.v:198773$13562 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -405628,10 +378055,10 @@ module \ti parameter \Y_WIDTH 3 connect \A \delay connect \B 1'1 - connect \Y $sub$libresoc.v:196412$13576_Y + connect \Y $sub$libresoc.v:198773$13562_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:196656.8-196754.4" + attribute \src "libresoc.v:199017.8-199115.4" cell \core \core connect \bigendian_i \core_bigendian_i$10 connect \cia__data_o \core_cia__data_o @@ -405732,7 +378159,7 @@ module \ti connect \wen$10 \core_wen$11 end attribute \module_not_derived 1 - attribute \src "libresoc.v:196755.7-196786.4" + attribute \src "libresoc.v:199116.7-199147.4" cell \dbg \dbg connect \clk \clk connect \core_dbg_core_dbg_dststep \dbg_core_dbg_core_dbg_dststep @@ -405766,7 +378193,7 @@ module \ti connect \terminate_i \dbg_terminate_i end attribute \module_not_derived 1 - attribute \src "libresoc.v:196787.8-196854.4" + attribute \src "libresoc.v:199148.8-199215.4" cell \dec2 \dec2 connect \asmcode \dec2_asmcode connect \bigendian \dec2_bigendian @@ -405836,7 +378263,7 @@ module \ti connect \xer_out \dec2_xer_out end attribute \module_not_derived 1 - attribute \src "libresoc.v:196855.8-196871.4" + attribute \src "libresoc.v:199216.8-199232.4" cell \imem \imem connect \a_pc_i \imem_a_pc_i connect \a_valid_i \imem_a_valid_i @@ -405855,7 +378282,7 @@ module \ti connect \wb_icache_en \imem_wb_icache_en end attribute \module_not_derived 1 - attribute \src "libresoc.v:196872.8-197199.4" + attribute \src "libresoc.v:199233.8-199516.4" cell \jtag \jtag connect \TAP_bus__tck \TAP_bus__tck connect \TAP_bus__tdi \TAP_bus__tdi @@ -405986,14 +378413,6 @@ module \ti connect \mspi0_miso__pad__i \mspi0_miso__pad__i connect \mspi0_mosi__core__o \mspi0_mosi__core__o connect \mspi0_mosi__pad__o \mspi0_mosi__pad__o - connect \mspi1_clk__core__o \mspi1_clk__core__o - connect \mspi1_clk__pad__o \mspi1_clk__pad__o - connect \mspi1_cs_n__core__o \mspi1_cs_n__core__o - connect \mspi1_cs_n__pad__o \mspi1_cs_n__pad__o - connect \mspi1_miso__core__i \mspi1_miso__core__i - connect \mspi1_miso__pad__i \mspi1_miso__pad__i - connect \mspi1_mosi__core__o \mspi1_mosi__core__o - connect \mspi1_mosi__pad__o \mspi1_mosi__pad__o connect \mtwi_scl__core__o \mtwi_scl__core__o connect \mtwi_scl__pad__o \mtwi_scl__pad__o connect \mtwi_sda__core__i \mtwi_sda__core__i @@ -406002,43 +378421,7 @@ module \ti connect \mtwi_sda__pad__i \mtwi_sda__pad__i connect \mtwi_sda__pad__o \mtwi_sda__pad__o connect \mtwi_sda__pad__oe \mtwi_sda__pad__oe - connect \pwm_0__core__o \pwm_0__core__o - connect \pwm_0__pad__o \pwm_0__pad__o - connect \pwm_1__core__o \pwm_1__core__o - connect \pwm_1__pad__o \pwm_1__pad__o connect \rst \rst - connect \sd0_clk__core__o \sd0_clk__core__o - connect \sd0_clk__pad__o \sd0_clk__pad__o - connect \sd0_cmd__core__i \sd0_cmd__core__i - connect \sd0_cmd__core__o \sd0_cmd__core__o - connect \sd0_cmd__core__oe \sd0_cmd__core__oe - connect \sd0_cmd__pad__i \sd0_cmd__pad__i - connect \sd0_cmd__pad__o \sd0_cmd__pad__o - connect \sd0_cmd__pad__oe \sd0_cmd__pad__oe - connect \sd0_data0__core__i \sd0_data0__core__i - connect \sd0_data0__core__o \sd0_data0__core__o - connect \sd0_data0__core__oe \sd0_data0__core__oe - connect \sd0_data0__pad__i \sd0_data0__pad__i - connect \sd0_data0__pad__o \sd0_data0__pad__o - connect \sd0_data0__pad__oe \sd0_data0__pad__oe - connect \sd0_data1__core__i \sd0_data1__core__i - connect \sd0_data1__core__o \sd0_data1__core__o - connect \sd0_data1__core__oe \sd0_data1__core__oe - connect \sd0_data1__pad__i \sd0_data1__pad__i - connect \sd0_data1__pad__o \sd0_data1__pad__o - connect \sd0_data1__pad__oe \sd0_data1__pad__oe - connect \sd0_data2__core__i \sd0_data2__core__i - connect \sd0_data2__core__o \sd0_data2__core__o - connect \sd0_data2__core__oe \sd0_data2__core__oe - connect \sd0_data2__pad__i \sd0_data2__pad__i - connect \sd0_data2__pad__o \sd0_data2__pad__o - connect \sd0_data2__pad__oe \sd0_data2__pad__oe - connect \sd0_data3__core__i \sd0_data3__core__i - connect \sd0_data3__core__o \sd0_data3__core__o - connect \sd0_data3__core__oe \sd0_data3__core__oe - connect \sd0_data3__pad__i \sd0_data3__pad__i - connect \sd0_data3__pad__o \sd0_data3__pad__o - connect \sd0_data3__pad__oe \sd0_data3__pad__oe connect \sdr_a_0__core__o \sdr_a_0__core__o connect \sdr_a_0__pad__o \sdr_a_0__pad__o connect \sdr_a_10__core__o \sdr_a_10__core__o @@ -406185,7 +378568,7 @@ module \ti connect \wb_icache_en \imem_wb_icache_en end attribute \module_not_derived 1 - attribute \src "libresoc.v:197200.12-197214.4" + attribute \src "libresoc.v:199517.12-199531.4" cell \xics_icp \xics_icp connect \clk \clk connect \core_irq_o \xics_icp_core_irq_o @@ -406202,7 +378585,7 @@ module \ti connect \rst \rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:197215.12-197228.4" + attribute \src "libresoc.v:199532.12-199545.4" cell \xics_ics \xics_ics connect \clk \clk connect \icp_o_pri \xics_ics_icp_o_pri @@ -406217,1582 +378600,1582 @@ module \ti connect \int_level_i \int_level_i connect \rst \rst end - attribute \src "libresoc.v:193965.7-193965.20" - process $proc$libresoc.v:193965$14194 + attribute \src "libresoc.v:196414.7-196414.20" + process $proc$libresoc.v:196414$14180 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:194233.13-194233.33" - process $proc$libresoc.v:194233$14195 + attribute \src "libresoc.v:196682.13-196682.33" + process $proc$libresoc.v:196682$14181 assign { } { } assign $1\core_asmcode[7:0] 8'00000000 sync always sync init update \core_asmcode $1\core_asmcode[7:0] end - attribute \src "libresoc.v:194239.7-194239.35" - process $proc$libresoc.v:194239$14196 + attribute \src "libresoc.v:196688.7-196688.35" + process $proc$libresoc.v:196688$14182 assign { } { } - assign $0\core_bigendian_i$10[0:0]$14197 1'0 + assign $0\core_bigendian_i$10[0:0]$14183 1'0 sync always sync init - update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$14197 + update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$14183 end - attribute \src "libresoc.v:194247.14-194247.55" - process $proc$libresoc.v:194247$14198 + attribute \src "libresoc.v:196696.14-196696.55" + process $proc$libresoc.v:196696$14184 assign { } { } assign $1\core_core_core_cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_core_core_cia $1\core_core_core_cia[63:0] end - attribute \src "libresoc.v:194251.13-194251.41" - process $proc$libresoc.v:194251$14199 + attribute \src "libresoc.v:196700.13-196700.41" + process $proc$libresoc.v:196700$14185 assign { } { } assign $1\core_core_core_cr_rd[7:0] 8'00000000 sync always sync init update \core_core_core_cr_rd $1\core_core_core_cr_rd[7:0] end - attribute \src "libresoc.v:194255.7-194255.37" - process $proc$libresoc.v:194255$14200 + attribute \src "libresoc.v:196704.7-196704.37" + process $proc$libresoc.v:196704$14186 assign { } { } assign $1\core_core_core_cr_rd_ok[0:0] 1'0 sync always sync init update \core_core_core_cr_rd_ok $1\core_core_core_cr_rd_ok[0:0] end - attribute \src "libresoc.v:194259.13-194259.41" - process $proc$libresoc.v:194259$14201 + attribute \src "libresoc.v:196708.13-196708.41" + process $proc$libresoc.v:196708$14187 assign { } { } assign $1\core_core_core_cr_wr[7:0] 8'00000000 sync always sync init update \core_core_core_cr_wr $1\core_core_core_cr_wr[7:0] end - attribute \src "libresoc.v:194263.7-194263.42" - process $proc$libresoc.v:194263$14202 + attribute \src "libresoc.v:196712.7-196712.42" + process $proc$libresoc.v:196712$14188 assign { } { } - assign $0\core_core_core_exc_$signal[0:0]$14203 1'0 + assign $0\core_core_core_exc_$signal[0:0]$14189 1'0 sync always sync init - update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$14203 + update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$14189 end - attribute \src "libresoc.v:194265.7-194265.44" - process $proc$libresoc.v:194265$14204 + attribute \src "libresoc.v:196714.7-196714.44" + process $proc$libresoc.v:196714$14190 assign { } { } - assign $0\core_core_core_exc_$signal$3[0:0]$14205 1'0 + assign $0\core_core_core_exc_$signal$3[0:0]$14191 1'0 sync always sync init - update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$14205 + update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$14191 end - attribute \src "libresoc.v:194269.7-194269.44" - process $proc$libresoc.v:194269$14206 + attribute \src "libresoc.v:196718.7-196718.44" + process $proc$libresoc.v:196718$14192 assign { } { } - assign $0\core_core_core_exc_$signal$4[0:0]$14207 1'0 + assign $0\core_core_core_exc_$signal$4[0:0]$14193 1'0 sync always sync init - update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$14207 + update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$14193 end - attribute \src "libresoc.v:194273.7-194273.44" - process $proc$libresoc.v:194273$14208 + attribute \src "libresoc.v:196722.7-196722.44" + process $proc$libresoc.v:196722$14194 assign { } { } - assign $0\core_core_core_exc_$signal$5[0:0]$14209 1'0 + assign $0\core_core_core_exc_$signal$5[0:0]$14195 1'0 sync always sync init - update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$14209 + update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$14195 end - attribute \src "libresoc.v:194277.7-194277.44" - process $proc$libresoc.v:194277$14210 + attribute \src "libresoc.v:196726.7-196726.44" + process $proc$libresoc.v:196726$14196 assign { } { } - assign $0\core_core_core_exc_$signal$6[0:0]$14211 1'0 + assign $0\core_core_core_exc_$signal$6[0:0]$14197 1'0 sync always sync init - update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$14211 + update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$14197 end - attribute \src "libresoc.v:194281.7-194281.44" - process $proc$libresoc.v:194281$14212 + attribute \src "libresoc.v:196730.7-196730.44" + process $proc$libresoc.v:196730$14198 assign { } { } - assign $0\core_core_core_exc_$signal$7[0:0]$14213 1'0 + assign $0\core_core_core_exc_$signal$7[0:0]$14199 1'0 sync always sync init - update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$14213 + update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$14199 end - attribute \src "libresoc.v:194285.7-194285.44" - process $proc$libresoc.v:194285$14214 + attribute \src "libresoc.v:196734.7-196734.44" + process $proc$libresoc.v:196734$14200 assign { } { } - assign $0\core_core_core_exc_$signal$8[0:0]$14215 1'0 + assign $0\core_core_core_exc_$signal$8[0:0]$14201 1'0 sync always sync init - update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$14215 + update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$14201 end - attribute \src "libresoc.v:194289.7-194289.44" - process $proc$libresoc.v:194289$14216 + attribute \src "libresoc.v:196738.7-196738.44" + process $proc$libresoc.v:196738$14202 assign { } { } - assign $0\core_core_core_exc_$signal$9[0:0]$14217 1'0 + assign $0\core_core_core_exc_$signal$9[0:0]$14203 1'0 sync always sync init - update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$14217 + update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$14203 end - attribute \src "libresoc.v:194310.14-194310.47" - process $proc$libresoc.v:194310$14218 + attribute \src "libresoc.v:196759.14-196759.47" + process $proc$libresoc.v:196759$14204 assign { } { } assign $1\core_core_core_fn_unit[13:0] 14'00000000000000 sync always sync init update \core_core_core_fn_unit $1\core_core_core_fn_unit[13:0] end - attribute \src "libresoc.v:194318.13-194318.46" - process $proc$libresoc.v:194318$14219 + attribute \src "libresoc.v:196767.13-196767.46" + process $proc$libresoc.v:196767$14205 assign { } { } assign $1\core_core_core_input_carry[1:0] 2'00 sync always sync init update \core_core_core_input_carry $1\core_core_core_input_carry[1:0] end - attribute \src "libresoc.v:194322.14-194322.41" - process $proc$libresoc.v:194322$14220 + attribute \src "libresoc.v:196771.14-196771.41" + process $proc$libresoc.v:196771$14206 assign { } { } assign $1\core_core_core_insn[31:0] 0 sync always sync init update \core_core_core_insn $1\core_core_core_insn[31:0] end - attribute \src "libresoc.v:194401.13-194401.45" - process $proc$libresoc.v:194401$14221 + attribute \src "libresoc.v:196850.13-196850.45" + process $proc$libresoc.v:196850$14207 assign { } { } assign $1\core_core_core_insn_type[6:0] 7'0000000 sync always sync init update \core_core_core_insn_type $1\core_core_core_insn_type[6:0] end - attribute \src "libresoc.v:194405.7-194405.37" - process $proc$libresoc.v:194405$14222 + attribute \src "libresoc.v:196854.7-196854.37" + process $proc$libresoc.v:196854$14208 assign { } { } assign $1\core_core_core_is_32bit[0:0] 1'0 sync always sync init update \core_core_core_is_32bit $1\core_core_core_is_32bit[0:0] end - attribute \src "libresoc.v:194409.14-194409.55" - process $proc$libresoc.v:194409$14223 + attribute \src "libresoc.v:196858.14-196858.55" + process $proc$libresoc.v:196858$14209 assign { } { } assign $1\core_core_core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_core_core_msr $1\core_core_core_msr[63:0] end - attribute \src "libresoc.v:194413.7-194413.31" - process $proc$libresoc.v:194413$14224 + attribute \src "libresoc.v:196862.7-196862.31" + process $proc$libresoc.v:196862$14210 assign { } { } assign $1\core_core_core_oe[0:0] 1'0 sync always sync init update \core_core_core_oe $1\core_core_core_oe[0:0] end - attribute \src "libresoc.v:194417.7-194417.34" - process $proc$libresoc.v:194417$14225 + attribute \src "libresoc.v:196866.7-196866.34" + process $proc$libresoc.v:196866$14211 assign { } { } assign $1\core_core_core_oe_ok[0:0] 1'0 sync always sync init update \core_core_core_oe_ok $1\core_core_core_oe_ok[0:0] end - attribute \src "libresoc.v:194421.7-194421.31" - process $proc$libresoc.v:194421$14226 + attribute \src "libresoc.v:196870.7-196870.31" + process $proc$libresoc.v:196870$14212 assign { } { } assign $1\core_core_core_rc[0:0] 1'0 sync always sync init update \core_core_core_rc $1\core_core_core_rc[0:0] end - attribute \src "libresoc.v:194425.7-194425.34" - process $proc$libresoc.v:194425$14227 + attribute \src "libresoc.v:196874.7-196874.34" + process $proc$libresoc.v:196874$14213 assign { } { } assign $1\core_core_core_rc_ok[0:0] 1'0 sync always sync init update \core_core_core_rc_ok $1\core_core_core_rc_ok[0:0] end - attribute \src "libresoc.v:194429.14-194429.48" - process $proc$libresoc.v:194429$14228 + attribute \src "libresoc.v:196878.14-196878.48" + process $proc$libresoc.v:196878$14214 assign { } { } assign $1\core_core_core_trapaddr[12:0] 13'0000000000000 sync always sync init update \core_core_core_trapaddr $1\core_core_core_trapaddr[12:0] end - attribute \src "libresoc.v:194433.13-194433.44" - process $proc$libresoc.v:194433$14229 + attribute \src "libresoc.v:196882.13-196882.44" + process $proc$libresoc.v:196882$14215 assign { } { } assign $1\core_core_core_traptype[7:0] 8'00000000 sync always sync init update \core_core_core_traptype $1\core_core_core_traptype[7:0] end - attribute \src "libresoc.v:194437.13-194437.37" - process $proc$libresoc.v:194437$14230 + attribute \src "libresoc.v:196886.13-196886.37" + process $proc$libresoc.v:196886$14216 assign { } { } assign $1\core_core_cr_in1[6:0] 7'0000000 sync always sync init update \core_core_cr_in1 $1\core_core_cr_in1[6:0] end - attribute \src "libresoc.v:194441.7-194441.33" - process $proc$libresoc.v:194441$14231 + attribute \src "libresoc.v:196890.7-196890.33" + process $proc$libresoc.v:196890$14217 assign { } { } assign $1\core_core_cr_in1_ok[0:0] 1'0 sync always sync init update \core_core_cr_in1_ok $1\core_core_cr_in1_ok[0:0] end - attribute \src "libresoc.v:194445.13-194445.37" - process $proc$libresoc.v:194445$14232 + attribute \src "libresoc.v:196894.13-196894.37" + process $proc$libresoc.v:196894$14218 assign { } { } assign $1\core_core_cr_in2[6:0] 7'0000000 sync always sync init update \core_core_cr_in2 $1\core_core_cr_in2[6:0] end - attribute \src "libresoc.v:194447.13-194447.41" - process $proc$libresoc.v:194447$14233 + attribute \src "libresoc.v:196896.13-196896.41" + process $proc$libresoc.v:196896$14219 assign { } { } - assign $0\core_core_cr_in2$1[6:0]$14234 7'0000000 + assign $0\core_core_cr_in2$1[6:0]$14220 7'0000000 sync always sync init - update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$14234 + update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$14220 end - attribute \src "libresoc.v:194453.7-194453.33" - process $proc$libresoc.v:194453$14235 + attribute \src "libresoc.v:196902.7-196902.33" + process $proc$libresoc.v:196902$14221 assign { } { } assign $1\core_core_cr_in2_ok[0:0] 1'0 sync always sync init update \core_core_cr_in2_ok $1\core_core_cr_in2_ok[0:0] end - attribute \src "libresoc.v:194455.7-194455.37" - process $proc$libresoc.v:194455$14236 + attribute \src "libresoc.v:196904.7-196904.37" + process $proc$libresoc.v:196904$14222 assign { } { } - assign $0\core_core_cr_in2_ok$2[0:0]$14237 1'0 + assign $0\core_core_cr_in2_ok$2[0:0]$14223 1'0 sync always sync init - update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$14237 + update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$14223 end - attribute \src "libresoc.v:194461.13-194461.37" - process $proc$libresoc.v:194461$14238 + attribute \src "libresoc.v:196910.13-196910.37" + process $proc$libresoc.v:196910$14224 assign { } { } assign $1\core_core_cr_out[6:0] 7'0000000 sync always sync init update \core_core_cr_out $1\core_core_cr_out[6:0] end - attribute \src "libresoc.v:194465.7-194465.32" - process $proc$libresoc.v:194465$14239 + attribute \src "libresoc.v:196914.7-196914.32" + process $proc$libresoc.v:196914$14225 assign { } { } assign $1\core_core_cr_wr_ok[0:0] 1'0 sync always sync init update \core_core_cr_wr_ok $1\core_core_cr_wr_ok[0:0] end - attribute \src "libresoc.v:194469.13-194469.38" - process $proc$libresoc.v:194469$14240 + attribute \src "libresoc.v:196918.13-196918.38" + process $proc$libresoc.v:196918$14226 assign { } { } assign $1\core_core_dststep[6:0] 7'0000000 sync always sync init update \core_core_dststep $1\core_core_dststep[6:0] end - attribute \src "libresoc.v:194473.13-194473.33" - process $proc$libresoc.v:194473$14241 + attribute \src "libresoc.v:196922.13-196922.33" + process $proc$libresoc.v:196922$14227 assign { } { } assign $1\core_core_ea[6:0] 7'0000000 sync always sync init update \core_core_ea $1\core_core_ea[6:0] end - attribute \src "libresoc.v:194477.13-194477.35" - process $proc$libresoc.v:194477$14242 + attribute \src "libresoc.v:196926.13-196926.35" + process $proc$libresoc.v:196926$14228 assign { } { } assign $1\core_core_fast1[2:0] 3'000 sync always sync init update \core_core_fast1 $1\core_core_fast1[2:0] end - attribute \src "libresoc.v:194481.7-194481.32" - process $proc$libresoc.v:194481$14243 + attribute \src "libresoc.v:196930.7-196930.32" + process $proc$libresoc.v:196930$14229 assign { } { } assign $1\core_core_fast1_ok[0:0] 1'0 sync always sync init update \core_core_fast1_ok $1\core_core_fast1_ok[0:0] end - attribute \src "libresoc.v:194485.13-194485.35" - process $proc$libresoc.v:194485$14244 + attribute \src "libresoc.v:196934.13-196934.35" + process $proc$libresoc.v:196934$14230 assign { } { } assign $1\core_core_fast2[2:0] 3'000 sync always sync init update \core_core_fast2 $1\core_core_fast2[2:0] end - attribute \src "libresoc.v:194489.7-194489.32" - process $proc$libresoc.v:194489$14245 + attribute \src "libresoc.v:196938.7-196938.32" + process $proc$libresoc.v:196938$14231 assign { } { } assign $1\core_core_fast2_ok[0:0] 1'0 sync always sync init update \core_core_fast2_ok $1\core_core_fast2_ok[0:0] end - attribute \src "libresoc.v:194493.13-194493.36" - process $proc$libresoc.v:194493$14246 + attribute \src "libresoc.v:196942.13-196942.36" + process $proc$libresoc.v:196942$14232 assign { } { } assign $1\core_core_fasto1[2:0] 3'000 sync always sync init update \core_core_fasto1 $1\core_core_fasto1[2:0] end - attribute \src "libresoc.v:194497.13-194497.36" - process $proc$libresoc.v:194497$14247 + attribute \src "libresoc.v:196946.13-196946.36" + process $proc$libresoc.v:196946$14233 assign { } { } assign $1\core_core_fasto2[2:0] 3'000 sync always sync init update \core_core_fasto2 $1\core_core_fasto2[2:0] end - attribute \src "libresoc.v:194501.7-194501.26" - process $proc$libresoc.v:194501$14248 + attribute \src "libresoc.v:196950.7-196950.26" + process $proc$libresoc.v:196950$14234 assign { } { } assign $1\core_core_lk[0:0] 1'0 sync always sync init update \core_core_lk $1\core_core_lk[0:0] end - attribute \src "libresoc.v:194505.13-194505.36" - process $proc$libresoc.v:194505$14249 + attribute \src "libresoc.v:196954.13-196954.36" + process $proc$libresoc.v:196954$14235 assign { } { } assign $1\core_core_maxvl[6:0] 7'0000000 sync always sync init update \core_core_maxvl $1\core_core_maxvl[6:0] end - attribute \src "libresoc.v:194509.14-194509.49" - process $proc$libresoc.v:194509$14250 + attribute \src "libresoc.v:196958.14-196958.49" + process $proc$libresoc.v:196958$14236 assign { } { } assign $1\core_core_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_core_pc $1\core_core_pc[63:0] end - attribute \src "libresoc.v:194513.13-194513.35" - process $proc$libresoc.v:194513$14251 + attribute \src "libresoc.v:196962.13-196962.35" + process $proc$libresoc.v:196962$14237 assign { } { } assign $1\core_core_reg1[6:0] 7'0000000 sync always sync init update \core_core_reg1 $1\core_core_reg1[6:0] end - attribute \src "libresoc.v:194517.7-194517.31" - process $proc$libresoc.v:194517$14252 + attribute \src "libresoc.v:196966.7-196966.31" + process $proc$libresoc.v:196966$14238 assign { } { } assign $1\core_core_reg1_ok[0:0] 1'0 sync always sync init update \core_core_reg1_ok $1\core_core_reg1_ok[0:0] end - attribute \src "libresoc.v:194521.13-194521.35" - process $proc$libresoc.v:194521$14253 + attribute \src "libresoc.v:196970.13-196970.35" + process $proc$libresoc.v:196970$14239 assign { } { } assign $1\core_core_reg2[6:0] 7'0000000 sync always sync init update \core_core_reg2 $1\core_core_reg2[6:0] end - attribute \src "libresoc.v:194525.7-194525.31" - process $proc$libresoc.v:194525$14254 + attribute \src "libresoc.v:196974.7-196974.31" + process $proc$libresoc.v:196974$14240 assign { } { } assign $1\core_core_reg2_ok[0:0] 1'0 sync always sync init update \core_core_reg2_ok $1\core_core_reg2_ok[0:0] end - attribute \src "libresoc.v:194529.13-194529.35" - process $proc$libresoc.v:194529$14255 + attribute \src "libresoc.v:196978.13-196978.35" + process $proc$libresoc.v:196978$14241 assign { } { } assign $1\core_core_reg3[6:0] 7'0000000 sync always sync init update \core_core_reg3 $1\core_core_reg3[6:0] end - attribute \src "libresoc.v:194533.7-194533.31" - process $proc$libresoc.v:194533$14256 + attribute \src "libresoc.v:196982.7-196982.31" + process $proc$libresoc.v:196982$14242 assign { } { } assign $1\core_core_reg3_ok[0:0] 1'0 sync always sync init update \core_core_reg3_ok $1\core_core_reg3_ok[0:0] end - attribute \src "libresoc.v:194537.13-194537.35" - process $proc$libresoc.v:194537$14257 + attribute \src "libresoc.v:196986.13-196986.35" + process $proc$libresoc.v:196986$14243 assign { } { } assign $1\core_core_rego[6:0] 7'0000000 sync always sync init update \core_core_rego $1\core_core_rego[6:0] end - attribute \src "libresoc.v:194655.13-194655.37" - process $proc$libresoc.v:194655$14258 + attribute \src "libresoc.v:197104.13-197104.37" + process $proc$libresoc.v:197104$14244 assign { } { } assign $1\core_core_spr1[9:0] 10'0000000000 sync always sync init update \core_core_spr1 $1\core_core_spr1[9:0] end - attribute \src "libresoc.v:194659.7-194659.31" - process $proc$libresoc.v:194659$14259 + attribute \src "libresoc.v:197108.7-197108.31" + process $proc$libresoc.v:197108$14245 assign { } { } assign $1\core_core_spr1_ok[0:0] 1'0 sync always sync init update \core_core_spr1_ok $1\core_core_spr1_ok[0:0] end - attribute \src "libresoc.v:194777.13-194777.37" - process $proc$libresoc.v:194777$14260 + attribute \src "libresoc.v:197226.13-197226.37" + process $proc$libresoc.v:197226$14246 assign { } { } assign $1\core_core_spro[9:0] 10'0000000000 sync always sync init update \core_core_spro $1\core_core_spro[9:0] end - attribute \src "libresoc.v:194781.13-194781.38" - process $proc$libresoc.v:194781$14261 + attribute \src "libresoc.v:197230.13-197230.38" + process $proc$libresoc.v:197230$14247 assign { } { } assign $1\core_core_srcstep[6:0] 7'0000000 sync always sync init update \core_core_srcstep $1\core_core_srcstep[6:0] end - attribute \src "libresoc.v:194785.13-194785.35" - process $proc$libresoc.v:194785$14262 + attribute \src "libresoc.v:197234.13-197234.35" + process $proc$libresoc.v:197234$14248 assign { } { } assign $1\core_core_subvl[1:0] 2'00 sync always sync init update \core_core_subvl $1\core_core_subvl[1:0] end - attribute \src "libresoc.v:194789.13-194789.36" - process $proc$libresoc.v:194789$14263 + attribute \src "libresoc.v:197238.13-197238.36" + process $proc$libresoc.v:197238$14249 assign { } { } assign $1\core_core_svstep[1:0] 2'00 sync always sync init update \core_core_svstep $1\core_core_svstep[1:0] end - attribute \src "libresoc.v:194795.13-194795.33" - process $proc$libresoc.v:194795$14264 + attribute \src "libresoc.v:197244.13-197244.33" + process $proc$libresoc.v:197244$14250 assign { } { } assign $1\core_core_vl[6:0] 7'0000000 sync always sync init update \core_core_vl $1\core_core_vl[6:0] end - attribute \src "libresoc.v:194799.13-194799.36" - process $proc$libresoc.v:194799$14265 + attribute \src "libresoc.v:197248.13-197248.36" + process $proc$libresoc.v:197248$14251 assign { } { } assign $1\core_core_xer_in[2:0] 3'000 sync always sync init update \core_core_xer_in $1\core_core_xer_in[2:0] end - attribute \src "libresoc.v:194807.7-194807.28" - process $proc$libresoc.v:194807$14266 + attribute \src "libresoc.v:197256.7-197256.28" + process $proc$libresoc.v:197256$14252 assign { } { } assign $1\core_cr_out_ok[0:0] 1'0 sync always sync init update \core_cr_out_ok $1\core_cr_out_ok[0:0] end - attribute \src "libresoc.v:194823.14-194823.45" - process $proc$libresoc.v:194823$14267 + attribute \src "libresoc.v:197272.14-197272.45" + process $proc$libresoc.v:197272$14253 assign { } { } assign $1\core_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_dec $1\core_dec[63:0] end - attribute \src "libresoc.v:194833.7-194833.24" - process $proc$libresoc.v:194833$14268 + attribute \src "libresoc.v:197282.7-197282.24" + process $proc$libresoc.v:197282$14254 assign { } { } assign $1\core_ea_ok[0:0] 1'0 sync always sync init update \core_ea_ok $1\core_ea_ok[0:0] end - attribute \src "libresoc.v:194837.7-194837.23" - process $proc$libresoc.v:194837$14269 + attribute \src "libresoc.v:197286.7-197286.23" + process $proc$libresoc.v:197286$14255 assign { } { } assign $1\core_eint[0:0] 1'0 sync always sync init update \core_eint $1\core_eint[0:0] end - attribute \src "libresoc.v:194841.7-194841.28" - process $proc$libresoc.v:194841$14270 + attribute \src "libresoc.v:197290.7-197290.28" + process $proc$libresoc.v:197290$14256 assign { } { } assign $1\core_fasto1_ok[0:0] 1'0 sync always sync init update \core_fasto1_ok $1\core_fasto1_ok[0:0] end - attribute \src "libresoc.v:194845.7-194845.28" - process $proc$libresoc.v:194845$14271 + attribute \src "libresoc.v:197294.7-197294.28" + process $proc$libresoc.v:197294$14257 assign { } { } assign $1\core_fasto2_ok[0:0] 1'0 sync always sync init update \core_fasto2_ok $1\core_fasto2_ok[0:0] end - attribute \src "libresoc.v:194873.14-194873.45" - process $proc$libresoc.v:194873$14272 + attribute \src "libresoc.v:197322.14-197322.45" + process $proc$libresoc.v:197322$14258 assign { } { } assign $1\core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \core_msr $1\core_msr[63:0] end - attribute \src "libresoc.v:194881.14-194881.37" - process $proc$libresoc.v:194881$14273 + attribute \src "libresoc.v:197330.14-197330.37" + process $proc$libresoc.v:197330$14259 assign { } { } assign $1\core_raw_insn_i[31:0] 0 sync always sync init update \core_raw_insn_i $1\core_raw_insn_i[31:0] end - attribute \src "libresoc.v:194885.7-194885.26" - process $proc$libresoc.v:194885$14274 + attribute \src "libresoc.v:197334.7-197334.26" + process $proc$libresoc.v:197334$14260 assign { } { } assign $1\core_rego_ok[0:0] 1'0 sync always sync init update \core_rego_ok $1\core_rego_ok[0:0] end - attribute \src "libresoc.v:194889.7-194889.26" - process $proc$libresoc.v:194889$14275 + attribute \src "libresoc.v:197338.7-197338.26" + process $proc$libresoc.v:197338$14261 assign { } { } assign $1\core_spro_ok[0:0] 1'0 sync always sync init update \core_spro_ok $1\core_spro_ok[0:0] end - attribute \src "libresoc.v:194901.7-194901.26" - process $proc$libresoc.v:194901$14276 + attribute \src "libresoc.v:197350.7-197350.26" + process $proc$libresoc.v:197350$14262 assign { } { } assign $1\core_sv_a_nz[0:0] 1'0 sync always sync init update \core_sv_a_nz $1\core_sv_a_nz[0:0] end - attribute \src "libresoc.v:194911.7-194911.26" - process $proc$libresoc.v:194911$14277 + attribute \src "libresoc.v:197360.7-197360.26" + process $proc$libresoc.v:197360$14263 assign { } { } assign $1\core_xer_out[0:0] 1'0 sync always sync init update \core_xer_out $1\core_xer_out[0:0] end - attribute \src "libresoc.v:194917.7-194917.30" - process $proc$libresoc.v:194917$14278 + attribute \src "libresoc.v:197366.7-197366.30" + process $proc$libresoc.v:197366$14264 assign { } { } assign $1\cu_st__rel_o_dly[0:0] 1'0 sync always sync init update \cu_st__rel_o_dly $1\cu_st__rel_o_dly[0:0] end - attribute \src "libresoc.v:194923.13-194923.36" - process $proc$libresoc.v:194923$14279 + attribute \src "libresoc.v:197372.13-197372.36" + process $proc$libresoc.v:197372$14265 assign { } { } assign $1\cur_cur_dststep[6:0] 7'0000000 sync always sync init update \cur_cur_dststep $1\cur_cur_dststep[6:0] end - attribute \src "libresoc.v:194927.13-194927.34" - process $proc$libresoc.v:194927$14280 + attribute \src "libresoc.v:197376.13-197376.34" + process $proc$libresoc.v:197376$14266 assign { } { } assign $1\cur_cur_maxvl[6:0] 7'0000000 sync always sync init update \cur_cur_maxvl $1\cur_cur_maxvl[6:0] end - attribute \src "libresoc.v:194931.13-194931.36" - process $proc$libresoc.v:194931$14281 + attribute \src "libresoc.v:197380.13-197380.36" + process $proc$libresoc.v:197380$14267 assign { } { } assign $1\cur_cur_srcstep[6:0] 7'0000000 sync always sync init update \cur_cur_srcstep $1\cur_cur_srcstep[6:0] end - attribute \src "libresoc.v:194935.13-194935.33" - process $proc$libresoc.v:194935$14282 + attribute \src "libresoc.v:197384.13-197384.33" + process $proc$libresoc.v:197384$14268 assign { } { } assign $1\cur_cur_subvl[1:0] 2'00 sync always sync init update \cur_cur_subvl $1\cur_cur_subvl[1:0] end - attribute \src "libresoc.v:194939.13-194939.34" - process $proc$libresoc.v:194939$14283 + attribute \src "libresoc.v:197388.13-197388.34" + process $proc$libresoc.v:197388$14269 assign { } { } assign $1\cur_cur_svstep[1:0] 2'00 sync always sync init update \cur_cur_svstep $1\cur_cur_svstep[1:0] end - attribute \src "libresoc.v:194943.13-194943.31" - process $proc$libresoc.v:194943$14284 + attribute \src "libresoc.v:197392.13-197392.31" + process $proc$libresoc.v:197392$14270 assign { } { } assign $1\cur_cur_vl[6:0] 7'0000000 sync always sync init update \cur_cur_vl $1\cur_cur_vl[6:0] end - attribute \src "libresoc.v:194947.7-194947.24" - process $proc$libresoc.v:194947$14285 + attribute \src "libresoc.v:197396.7-197396.24" + process $proc$libresoc.v:197396$14271 assign { } { } assign $1\d_cr_delay[0:0] 1'0 sync always sync init update \d_cr_delay $1\d_cr_delay[0:0] end - attribute \src "libresoc.v:194951.7-194951.25" - process $proc$libresoc.v:194951$14286 + attribute \src "libresoc.v:197400.7-197400.25" + process $proc$libresoc.v:197400$14272 assign { } { } assign $1\d_reg_delay[0:0] 1'0 sync always sync init update \d_reg_delay $1\d_reg_delay[0:0] end - attribute \src "libresoc.v:194955.7-194955.25" - process $proc$libresoc.v:194955$14287 + attribute \src "libresoc.v:197404.7-197404.25" + process $proc$libresoc.v:197404$14273 assign { } { } assign $1\d_xer_delay[0:0] 1'0 sync always sync init update \d_xer_delay $1\d_xer_delay[0:0] end - attribute \src "libresoc.v:195003.13-195003.34" - process $proc$libresoc.v:195003$14288 + attribute \src "libresoc.v:197452.13-197452.34" + process $proc$libresoc.v:197452$14274 assign { } { } assign $1\dbg_dmi_addr_i[3:0] 4'0000 sync always sync init update \dbg_dmi_addr_i $1\dbg_dmi_addr_i[3:0] end - attribute \src "libresoc.v:195007.14-195007.48" - process $proc$libresoc.v:195007$14289 + attribute \src "libresoc.v:197456.14-197456.48" + process $proc$libresoc.v:197456$14275 assign { } { } assign $1\dbg_dmi_din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dbg_dmi_din $1\dbg_dmi_din[63:0] end - attribute \src "libresoc.v:195013.7-195013.27" - process $proc$libresoc.v:195013$14290 + attribute \src "libresoc.v:197462.7-197462.27" + process $proc$libresoc.v:197462$14276 assign { } { } assign $1\dbg_dmi_req_i[0:0] 1'0 sync always sync init update \dbg_dmi_req_i $1\dbg_dmi_req_i[0:0] end - attribute \src "libresoc.v:195017.7-195017.26" - process $proc$libresoc.v:195017$14291 + attribute \src "libresoc.v:197466.7-197466.26" + process $proc$libresoc.v:197466$14277 assign { } { } assign $1\dbg_dmi_we_i[0:0] 1'0 sync always sync init update \dbg_dmi_we_i $1\dbg_dmi_we_i[0:0] end - attribute \src "libresoc.v:195071.14-195071.49" - process $proc$libresoc.v:195071$14292 + attribute \src "libresoc.v:197520.14-197520.49" + process $proc$libresoc.v:197520$14278 assign { } { } assign $1\dec2_cur_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dec2_cur_dec $1\dec2_cur_dec[63:0] end - attribute \src "libresoc.v:195075.7-195075.27" - process $proc$libresoc.v:195075$14293 + attribute \src "libresoc.v:197524.7-197524.27" + process $proc$libresoc.v:197524$14279 assign { } { } assign $1\dec2_cur_eint[0:0] 1'0 sync always sync init update \dec2_cur_eint $1\dec2_cur_eint[0:0] end - attribute \src "libresoc.v:195079.14-195079.49" - process $proc$libresoc.v:195079$14294 + attribute \src "libresoc.v:197528.14-197528.49" + process $proc$libresoc.v:197528$14280 assign { } { } assign $1\dec2_cur_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dec2_cur_msr $1\dec2_cur_msr[63:0] end - attribute \src "libresoc.v:195083.14-195083.48" - process $proc$libresoc.v:195083$14295 + attribute \src "libresoc.v:197532.14-197532.48" + process $proc$libresoc.v:197532$14281 assign { } { } assign $1\dec2_cur_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \dec2_cur_pc $1\dec2_cur_pc[63:0] end - attribute \src "libresoc.v:195235.14-195235.40" - process $proc$libresoc.v:195235$14296 + attribute \src "libresoc.v:197684.14-197684.40" + process $proc$libresoc.v:197684$14282 assign { } { } assign $1\dec2_raw_opcode_in[31:0] 0 sync always sync init update \dec2_raw_opcode_in $1\dec2_raw_opcode_in[31:0] end - attribute \src "libresoc.v:195505.13-195505.25" - process $proc$libresoc.v:195505$14297 + attribute \src "libresoc.v:197954.13-197954.25" + process $proc$libresoc.v:197954$14283 assign { } { } assign $1\delay[1:0] 2'11 sync always sync init update \delay $1\delay[1:0] end - attribute \src "libresoc.v:195521.7-195521.28" - process $proc$libresoc.v:195521$14298 + attribute \src "libresoc.v:197970.7-197970.28" + process $proc$libresoc.v:197970$14284 assign { } { } assign $1\exec_fsm_state[0:0] 1'0 sync always sync init update \exec_fsm_state $1\exec_fsm_state[0:0] end - attribute \src "libresoc.v:195533.13-195533.35" - process $proc$libresoc.v:195533$14299 + attribute \src "libresoc.v:197982.13-197982.35" + process $proc$libresoc.v:197982$14285 assign { } { } assign $1\fetch_fsm_state[1:0] 2'00 sync always sync init update \fetch_fsm_state $1\fetch_fsm_state[1:0] end - attribute \src "libresoc.v:195545.13-195545.29" - process $proc$libresoc.v:195545$14300 + attribute \src "libresoc.v:197994.13-197994.29" + process $proc$libresoc.v:197994$14286 assign { } { } assign $1\fsm_state[1:0] 2'00 sync always sync init update \fsm_state $1\fsm_state[1:0] end - attribute \src "libresoc.v:195805.13-195805.35" - process $proc$libresoc.v:195805$14301 + attribute \src "libresoc.v:198254.13-198254.35" + process $proc$libresoc.v:198254$14287 assign { } { } assign $1\issue_fsm_state[2:0] 3'000 sync always sync init update \issue_fsm_state $1\issue_fsm_state[2:0] end - attribute \src "libresoc.v:195809.7-195809.30" - process $proc$libresoc.v:195809$14302 + attribute \src "libresoc.v:198258.7-198258.30" + process $proc$libresoc.v:198258$14288 assign { } { } assign $1\jtag_dmi0__ack_o[0:0] 1'0 sync always sync init update \jtag_dmi0__ack_o $1\jtag_dmi0__ack_o[0:0] end - attribute \src "libresoc.v:195817.14-195817.52" - process $proc$libresoc.v:195817$14303 + attribute \src "libresoc.v:198266.14-198266.52" + process $proc$libresoc.v:198266$14289 assign { } { } assign $1\jtag_dmi0__dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \jtag_dmi0__dout $1\jtag_dmi0__dout[63:0] end - attribute \src "libresoc.v:195873.7-195873.22" - process $proc$libresoc.v:195873$14304 + attribute \src "libresoc.v:198306.7-198306.22" + process $proc$libresoc.v:198306$14290 assign { } { } assign $1\msr_read[0:0] 1'1 sync always sync init update \msr_read $1\msr_read[0:0] end - attribute \src "libresoc.v:195913.14-195913.40" - process $proc$libresoc.v:195913$14305 + attribute \src "libresoc.v:198346.14-198346.40" + process $proc$libresoc.v:198346$14291 assign { } { } assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \nia $1\nia[63:0] end - attribute \src "libresoc.v:195919.7-195919.24" - process $proc$libresoc.v:195919$14306 + attribute \src "libresoc.v:198352.7-198352.24" + process $proc$libresoc.v:198352$14292 assign { } { } assign $1\pc_changed[0:0] 1'0 sync always sync init update \pc_changed $1\pc_changed[0:0] end - attribute \src "libresoc.v:195929.7-195929.25" - process $proc$libresoc.v:195929$14307 + attribute \src "libresoc.v:198362.7-198362.25" + process $proc$libresoc.v:198362$14293 assign { } { } assign $1\pc_ok_delay[0:0] 1'0 sync always sync init update \pc_ok_delay $1\pc_ok_delay[0:0] end - attribute \src "libresoc.v:196301.7-196301.24" - process $proc$libresoc.v:196301$14308 + attribute \src "libresoc.v:198662.7-198662.24" + process $proc$libresoc.v:198662$14294 assign { } { } assign $1\sv_changed[0:0] 1'0 sync always sync init update \sv_changed $1\sv_changed[0:0] end - attribute \src "libresoc.v:196311.7-196311.30" - process $proc$libresoc.v:196311$14309 + attribute \src "libresoc.v:198672.7-198672.30" + process $proc$libresoc.v:198672$14295 assign { } { } assign $1\svstate_ok_delay[0:0] 1'0 sync always sync init update \svstate_ok_delay $1\svstate_ok_delay[0:0] end - attribute \src "libresoc.v:196448.3-196449.41" - process $proc$libresoc.v:196448$13611 + attribute \src "libresoc.v:198809.3-198810.41" + process $proc$libresoc.v:198809$13597 assign { } { } assign $0\dec2_cur_dec[63:0] \dec2_cur_dec$next sync posedge \clk update \dec2_cur_dec $0\dec2_cur_dec[63:0] end - attribute \src "libresoc.v:196450.3-196451.41" - process $proc$libresoc.v:196450$13612 + attribute \src "libresoc.v:198811.3-198812.41" + process $proc$libresoc.v:198811$13598 assign { } { } assign $0\core_core_pc[63:0] \core_core_pc$next sync posedge \clk update \core_core_pc $0\core_core_pc[63:0] end - attribute \src "libresoc.v:196452.3-196453.49" - process $proc$libresoc.v:196452$13613 + attribute \src "libresoc.v:198813.3-198814.49" + process $proc$libresoc.v:198813$13599 assign { } { } assign $0\jtag_dmi0__ack_o[0:0] \jtag_dmi0__ack_o$next sync posedge \clk update \jtag_dmi0__ack_o $0\jtag_dmi0__ack_o[0:0] end - attribute \src "libresoc.v:196454.3-196455.39" - process $proc$libresoc.v:196454$13614 + attribute \src "libresoc.v:198815.3-198816.39" + process $proc$libresoc.v:198815$13600 assign { } { } assign $0\dbg_dmi_din[63:0] \dbg_dmi_din$next sync posedge \clk update \dbg_dmi_din $0\dbg_dmi_din[63:0] end - attribute \src "libresoc.v:196456.3-196457.41" - process $proc$libresoc.v:196456$13615 + attribute \src "libresoc.v:198817.3-198818.41" + process $proc$libresoc.v:198817$13601 assign { } { } assign $0\dbg_dmi_we_i[0:0] \dbg_dmi_we_i$next sync posedge \clk update \dbg_dmi_we_i $0\dbg_dmi_we_i[0:0] end - attribute \src "libresoc.v:196458.3-196459.43" - process $proc$libresoc.v:196458$13616 + attribute \src "libresoc.v:198819.3-198820.43" + process $proc$libresoc.v:198819$13602 assign { } { } assign $0\dbg_dmi_req_i[0:0] \dbg_dmi_req_i$next sync posedge \clk update \dbg_dmi_req_i $0\dbg_dmi_req_i[0:0] end - attribute \src "libresoc.v:196460.3-196461.45" - process $proc$libresoc.v:196460$13617 + attribute \src "libresoc.v:198821.3-198822.45" + process $proc$libresoc.v:198821$13603 assign { } { } assign $0\dbg_dmi_addr_i[3:0] \dbg_dmi_addr_i$next sync posedge \clk update \dbg_dmi_addr_i $0\dbg_dmi_addr_i[3:0] end - attribute \src "libresoc.v:196462.3-196463.33" - process $proc$libresoc.v:196462$13618 + attribute \src "libresoc.v:198823.3-198824.33" + process $proc$libresoc.v:198823$13604 assign { } { } assign $0\core_msr[63:0] \core_msr$next sync posedge \clk update \core_msr $0\core_msr[63:0] end - attribute \src "libresoc.v:196464.3-196465.35" - process $proc$libresoc.v:196464$13619 + attribute \src "libresoc.v:198825.3-198826.35" + process $proc$libresoc.v:198825$13605 assign { } { } assign $0\core_eint[0:0] \core_eint$next sync posedge \clk update \core_eint $0\core_eint[0:0] end - attribute \src "libresoc.v:196466.3-196467.33" - process $proc$libresoc.v:196466$13620 + attribute \src "libresoc.v:198827.3-198828.33" + process $proc$libresoc.v:198827$13606 assign { } { } assign $0\core_dec[63:0] \core_dec$next sync posedge \clk update \core_dec $0\core_dec[63:0] end - attribute \src "libresoc.v:196468.3-196469.49" - process $proc$libresoc.v:196468$13621 + attribute \src "libresoc.v:198829.3-198830.49" + process $proc$libresoc.v:198829$13607 assign { } { } assign $0\core_core_svstep[1:0] \core_core_svstep$next sync posedge \clk update \core_core_svstep $0\core_core_svstep[1:0] end - attribute \src "libresoc.v:196470.3-196471.47" - process $proc$libresoc.v:196470$13622 + attribute \src "libresoc.v:198831.3-198832.47" + process $proc$libresoc.v:198831$13608 assign { } { } assign $0\core_core_subvl[1:0] \core_core_subvl$next sync posedge \clk update \core_core_subvl $0\core_core_subvl[1:0] end - attribute \src "libresoc.v:196472.3-196473.51" - process $proc$libresoc.v:196472$13623 + attribute \src "libresoc.v:198833.3-198834.51" + process $proc$libresoc.v:198833$13609 assign { } { } assign $0\core_core_dststep[6:0] \core_core_dststep$next sync posedge \clk update \core_core_dststep $0\core_core_dststep[6:0] end - attribute \src "libresoc.v:196474.3-196475.51" - process $proc$libresoc.v:196474$13624 + attribute \src "libresoc.v:198835.3-198836.51" + process $proc$libresoc.v:198835$13610 assign { } { } assign $0\core_core_srcstep[6:0] \core_core_srcstep$next sync posedge \clk update \core_core_srcstep $0\core_core_srcstep[6:0] end - attribute \src "libresoc.v:196476.3-196477.41" - process $proc$libresoc.v:196476$13625 + attribute \src "libresoc.v:198837.3-198838.41" + process $proc$libresoc.v:198837$13611 assign { } { } assign $0\core_core_vl[6:0] \core_core_vl$next sync posedge \clk update \core_core_vl $0\core_core_vl[6:0] end - attribute \src "libresoc.v:196478.3-196479.47" - process $proc$libresoc.v:196478$13626 + attribute \src "libresoc.v:198839.3-198840.47" + process $proc$libresoc.v:198839$13612 assign { } { } assign $0\core_core_maxvl[6:0] \core_core_maxvl$next sync posedge \clk update \core_core_maxvl $0\core_core_maxvl[6:0] end - attribute \src "libresoc.v:196480.3-196481.35" - process $proc$libresoc.v:196480$13627 + attribute \src "libresoc.v:198841.3-198842.35" + process $proc$libresoc.v:198841$13613 assign { } { } assign $0\fsm_state[1:0] \fsm_state$next sync posedge \clk update \fsm_state $0\fsm_state[1:0] end - attribute \src "libresoc.v:196482.3-196483.41" - process $proc$libresoc.v:196482$13628 + attribute \src "libresoc.v:198843.3-198844.41" + process $proc$libresoc.v:198843$13614 assign { } { } assign $0\core_asmcode[7:0] \core_asmcode$next sync posedge \clk update \core_asmcode $0\core_asmcode[7:0] end - attribute \src "libresoc.v:196484.3-196485.45" - process $proc$libresoc.v:196484$13629 + attribute \src "libresoc.v:198845.3-198846.45" + process $proc$libresoc.v:198845$13615 assign { } { } assign $0\core_core_rego[6:0] \core_core_rego$next sync posedge \clk update \core_core_rego $0\core_core_rego[6:0] end - attribute \src "libresoc.v:196486.3-196487.41" - process $proc$libresoc.v:196486$13630 + attribute \src "libresoc.v:198847.3-198848.41" + process $proc$libresoc.v:198847$13616 assign { } { } assign $0\core_rego_ok[0:0] \core_rego_ok$next sync posedge \clk update \core_rego_ok $0\core_rego_ok[0:0] end - attribute \src "libresoc.v:196488.3-196489.41" - process $proc$libresoc.v:196488$13631 + attribute \src "libresoc.v:198849.3-198850.41" + process $proc$libresoc.v:198849$13617 assign { } { } assign $0\core_core_ea[6:0] \core_core_ea$next sync posedge \clk update \core_core_ea $0\core_core_ea[6:0] end - attribute \src "libresoc.v:196490.3-196491.37" - process $proc$libresoc.v:196490$13632 + attribute \src "libresoc.v:198851.3-198852.37" + process $proc$libresoc.v:198851$13618 assign { } { } assign $0\core_ea_ok[0:0] \core_ea_ok$next sync posedge \clk update \core_ea_ok $0\core_ea_ok[0:0] end - attribute \src "libresoc.v:196492.3-196493.45" - process $proc$libresoc.v:196492$13633 + attribute \src "libresoc.v:198853.3-198854.45" + process $proc$libresoc.v:198853$13619 assign { } { } assign $0\core_core_reg1[6:0] \core_core_reg1$next sync posedge \clk update \core_core_reg1 $0\core_core_reg1[6:0] end - attribute \src "libresoc.v:196494.3-196495.51" - process $proc$libresoc.v:196494$13634 + attribute \src "libresoc.v:198855.3-198856.51" + process $proc$libresoc.v:198855$13620 assign { } { } assign $0\core_core_reg1_ok[0:0] \core_core_reg1_ok$next sync posedge \clk update \core_core_reg1_ok $0\core_core_reg1_ok[0:0] end - attribute \src "libresoc.v:196496.3-196497.45" - process $proc$libresoc.v:196496$13635 + attribute \src "libresoc.v:198857.3-198858.45" + process $proc$libresoc.v:198857$13621 assign { } { } assign $0\core_core_reg2[6:0] \core_core_reg2$next sync posedge \clk update \core_core_reg2 $0\core_core_reg2[6:0] end - attribute \src "libresoc.v:196498.3-196499.51" - process $proc$libresoc.v:196498$13636 + attribute \src "libresoc.v:198859.3-198860.51" + process $proc$libresoc.v:198859$13622 assign { } { } assign $0\core_core_reg2_ok[0:0] \core_core_reg2_ok$next sync posedge \clk update \core_core_reg2_ok $0\core_core_reg2_ok[0:0] end - attribute \src "libresoc.v:196500.3-196501.45" - process $proc$libresoc.v:196500$13637 + attribute \src "libresoc.v:198861.3-198862.45" + process $proc$libresoc.v:198861$13623 assign { } { } assign $0\core_core_reg3[6:0] \core_core_reg3$next sync posedge \clk update \core_core_reg3 $0\core_core_reg3[6:0] end - attribute \src "libresoc.v:196502.3-196503.39" - process $proc$libresoc.v:196502$13638 + attribute \src "libresoc.v:198863.3-198864.39" + process $proc$libresoc.v:198863$13624 assign { } { } assign $0\d_xer_delay[0:0] \d_xer_delay$next sync posedge \clk update \d_xer_delay $0\d_xer_delay[0:0] end - attribute \src "libresoc.v:196504.3-196505.51" - process $proc$libresoc.v:196504$13639 + attribute \src "libresoc.v:198865.3-198866.51" + process $proc$libresoc.v:198865$13625 assign { } { } assign $0\core_core_reg3_ok[0:0] \core_core_reg3_ok$next sync posedge \clk update \core_core_reg3_ok $0\core_core_reg3_ok[0:0] end - attribute \src "libresoc.v:196506.3-196507.45" - process $proc$libresoc.v:196506$13640 + attribute \src "libresoc.v:198867.3-198868.45" + process $proc$libresoc.v:198867$13626 assign { } { } assign $0\core_core_spro[9:0] \core_core_spro$next sync posedge \clk update \core_core_spro $0\core_core_spro[9:0] end - attribute \src "libresoc.v:196508.3-196509.41" - process $proc$libresoc.v:196508$13641 + attribute \src "libresoc.v:198869.3-198870.41" + process $proc$libresoc.v:198869$13627 assign { } { } assign $0\core_spro_ok[0:0] \core_spro_ok$next sync posedge \clk update \core_spro_ok $0\core_spro_ok[0:0] end - attribute \src "libresoc.v:196510.3-196511.45" - process $proc$libresoc.v:196510$13642 + attribute \src "libresoc.v:198871.3-198872.45" + process $proc$libresoc.v:198871$13628 assign { } { } assign $0\core_core_spr1[9:0] \core_core_spr1$next sync posedge \clk update \core_core_spr1 $0\core_core_spr1[9:0] end - attribute \src "libresoc.v:196512.3-196513.51" - process $proc$libresoc.v:196512$13643 + attribute \src "libresoc.v:198873.3-198874.51" + process $proc$libresoc.v:198873$13629 assign { } { } assign $0\core_core_spr1_ok[0:0] \core_core_spr1_ok$next sync posedge \clk update \core_core_spr1_ok $0\core_core_spr1_ok[0:0] end - attribute \src "libresoc.v:196514.3-196515.49" - process $proc$libresoc.v:196514$13644 + attribute \src "libresoc.v:198875.3-198876.49" + process $proc$libresoc.v:198875$13630 assign { } { } assign $0\core_core_xer_in[2:0] \core_core_xer_in$next sync posedge \clk update \core_core_xer_in $0\core_core_xer_in[2:0] end - attribute \src "libresoc.v:196516.3-196517.41" - process $proc$libresoc.v:196516$13645 + attribute \src "libresoc.v:198877.3-198878.41" + process $proc$libresoc.v:198877$13631 assign { } { } assign $0\core_xer_out[0:0] \core_xer_out$next sync posedge \clk update \core_xer_out $0\core_xer_out[0:0] end - attribute \src "libresoc.v:196518.3-196519.47" - process $proc$libresoc.v:196518$13646 + attribute \src "libresoc.v:198879.3-198880.47" + process $proc$libresoc.v:198879$13632 assign { } { } assign $0\core_core_fast1[2:0] \core_core_fast1$next sync posedge \clk update \core_core_fast1 $0\core_core_fast1[2:0] end - attribute \src "libresoc.v:196520.3-196521.53" - process $proc$libresoc.v:196520$13647 + attribute \src "libresoc.v:198881.3-198882.53" + process $proc$libresoc.v:198881$13633 assign { } { } assign $0\core_core_fast1_ok[0:0] \core_core_fast1_ok$next sync posedge \clk update \core_core_fast1_ok $0\core_core_fast1_ok[0:0] end - attribute \src "libresoc.v:196522.3-196523.47" - process $proc$libresoc.v:196522$13648 + attribute \src "libresoc.v:198883.3-198884.47" + process $proc$libresoc.v:198883$13634 assign { } { } assign $0\core_core_fast2[2:0] \core_core_fast2$next sync posedge \clk update \core_core_fast2 $0\core_core_fast2[2:0] end - attribute \src "libresoc.v:196524.3-196525.37" - process $proc$libresoc.v:196524$13649 + attribute \src "libresoc.v:198885.3-198886.37" + process $proc$libresoc.v:198885$13635 assign { } { } assign $0\d_cr_delay[0:0] \d_cr_delay$next sync posedge \clk update \d_cr_delay $0\d_cr_delay[0:0] end - attribute \src "libresoc.v:196526.3-196527.53" - process $proc$libresoc.v:196526$13650 + attribute \src "libresoc.v:198887.3-198888.53" + process $proc$libresoc.v:198887$13636 assign { } { } assign $0\core_core_fast2_ok[0:0] \core_core_fast2_ok$next sync posedge \clk update \core_core_fast2_ok $0\core_core_fast2_ok[0:0] end - attribute \src "libresoc.v:196528.3-196529.49" - process $proc$libresoc.v:196528$13651 + attribute \src "libresoc.v:198889.3-198890.49" + process $proc$libresoc.v:198889$13637 assign { } { } assign $0\core_core_fasto1[2:0] \core_core_fasto1$next sync posedge \clk update \core_core_fasto1 $0\core_core_fasto1[2:0] end - attribute \src "libresoc.v:196530.3-196531.45" - process $proc$libresoc.v:196530$13652 + attribute \src "libresoc.v:198891.3-198892.45" + process $proc$libresoc.v:198891$13638 assign { } { } assign $0\core_fasto1_ok[0:0] \core_fasto1_ok$next sync posedge \clk update \core_fasto1_ok $0\core_fasto1_ok[0:0] end - attribute \src "libresoc.v:196532.3-196533.49" - process $proc$libresoc.v:196532$13653 + attribute \src "libresoc.v:198893.3-198894.49" + process $proc$libresoc.v:198893$13639 assign { } { } assign $0\core_core_fasto2[2:0] \core_core_fasto2$next sync posedge \clk update \core_core_fasto2 $0\core_core_fasto2[2:0] end - attribute \src "libresoc.v:196534.3-196535.45" - process $proc$libresoc.v:196534$13654 + attribute \src "libresoc.v:198895.3-198896.45" + process $proc$libresoc.v:198895$13640 assign { } { } assign $0\core_fasto2_ok[0:0] \core_fasto2_ok$next sync posedge \clk update \core_fasto2_ok $0\core_fasto2_ok[0:0] end - attribute \src "libresoc.v:196536.3-196537.49" - process $proc$libresoc.v:196536$13655 + attribute \src "libresoc.v:198897.3-198898.49" + process $proc$libresoc.v:198897$13641 assign { } { } assign $0\core_core_cr_in1[6:0] \core_core_cr_in1$next sync posedge \clk update \core_core_cr_in1 $0\core_core_cr_in1[6:0] end - attribute \src "libresoc.v:196538.3-196539.55" - process $proc$libresoc.v:196538$13656 + attribute \src "libresoc.v:198899.3-198900.55" + process $proc$libresoc.v:198899$13642 assign { } { } assign $0\core_core_cr_in1_ok[0:0] \core_core_cr_in1_ok$next sync posedge \clk update \core_core_cr_in1_ok $0\core_core_cr_in1_ok[0:0] end - attribute \src "libresoc.v:196540.3-196541.49" - process $proc$libresoc.v:196540$13657 + attribute \src "libresoc.v:198901.3-198902.49" + process $proc$libresoc.v:198901$13643 assign { } { } assign $0\core_core_cr_in2[6:0] \core_core_cr_in2$next sync posedge \clk update \core_core_cr_in2 $0\core_core_cr_in2[6:0] end - attribute \src "libresoc.v:196542.3-196543.55" - process $proc$libresoc.v:196542$13658 + attribute \src "libresoc.v:198903.3-198904.55" + process $proc$libresoc.v:198903$13644 assign { } { } assign $0\core_core_cr_in2_ok[0:0] \core_core_cr_in2_ok$next sync posedge \clk update \core_core_cr_in2_ok $0\core_core_cr_in2_ok[0:0] end - attribute \src "libresoc.v:196544.3-196545.55" - process $proc$libresoc.v:196544$13659 + attribute \src "libresoc.v:198905.3-198906.55" + process $proc$libresoc.v:198905$13645 assign { } { } - assign $0\core_core_cr_in2$1[6:0]$13660 \core_core_cr_in2$1$next + assign $0\core_core_cr_in2$1[6:0]$13646 \core_core_cr_in2$1$next sync posedge \clk - update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$13660 + update \core_core_cr_in2$1 $0\core_core_cr_in2$1[6:0]$13646 end - attribute \src "libresoc.v:196546.3-196547.39" - process $proc$libresoc.v:196546$13661 + attribute \src "libresoc.v:198907.3-198908.39" + process $proc$libresoc.v:198907$13647 assign { } { } assign $0\d_reg_delay[0:0] \d_reg_delay$next sync posedge \clk update \d_reg_delay $0\d_reg_delay[0:0] end - attribute \src "libresoc.v:196548.3-196549.61" - process $proc$libresoc.v:196548$13662 + attribute \src "libresoc.v:198909.3-198910.61" + process $proc$libresoc.v:198909$13648 assign { } { } - assign $0\core_core_cr_in2_ok$2[0:0]$13663 \core_core_cr_in2_ok$2$next + assign $0\core_core_cr_in2_ok$2[0:0]$13649 \core_core_cr_in2_ok$2$next sync posedge \clk - update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13663 + update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$13649 end - attribute \src "libresoc.v:196550.3-196551.49" - process $proc$libresoc.v:196550$13664 + attribute \src "libresoc.v:198911.3-198912.49" + process $proc$libresoc.v:198911$13650 assign { } { } assign $0\core_core_cr_out[6:0] \core_core_cr_out$next sync posedge \clk update \core_core_cr_out $0\core_core_cr_out[6:0] end - attribute \src "libresoc.v:196552.3-196553.45" - process $proc$libresoc.v:196552$13665 + attribute \src "libresoc.v:198913.3-198914.45" + process $proc$libresoc.v:198913$13651 assign { } { } assign $0\core_cr_out_ok[0:0] \core_cr_out_ok$next sync posedge \clk update \core_cr_out_ok $0\core_cr_out_ok[0:0] end - attribute \src "libresoc.v:196554.3-196555.53" - process $proc$libresoc.v:196554$13666 + attribute \src "libresoc.v:198915.3-198916.53" + process $proc$libresoc.v:198915$13652 assign { } { } assign $0\core_core_core_msr[63:0] \core_core_core_msr$next sync posedge \clk update \core_core_core_msr $0\core_core_core_msr[63:0] end - attribute \src "libresoc.v:196556.3-196557.53" - process $proc$libresoc.v:196556$13667 + attribute \src "libresoc.v:198917.3-198918.53" + process $proc$libresoc.v:198917$13653 assign { } { } assign $0\core_core_core_cia[63:0] \core_core_core_cia$next sync posedge \clk update \core_core_core_cia $0\core_core_core_cia[63:0] end - attribute \src "libresoc.v:196558.3-196559.55" - process $proc$libresoc.v:196558$13668 + attribute \src "libresoc.v:198919.3-198920.55" + process $proc$libresoc.v:198919$13654 assign { } { } assign $0\core_core_core_insn[31:0] \core_core_core_insn$next sync posedge \clk update \core_core_core_insn $0\core_core_core_insn[31:0] end - attribute \src "libresoc.v:196560.3-196561.65" - process $proc$libresoc.v:196560$13669 + attribute \src "libresoc.v:198921.3-198922.65" + process $proc$libresoc.v:198921$13655 assign { } { } assign $0\core_core_core_insn_type[6:0] \core_core_core_insn_type$next sync posedge \clk update \core_core_core_insn_type $0\core_core_core_insn_type[6:0] end - attribute \src "libresoc.v:196562.3-196563.61" - process $proc$libresoc.v:196562$13670 + attribute \src "libresoc.v:198923.3-198924.61" + process $proc$libresoc.v:198923$13656 assign { } { } assign $0\core_core_core_fn_unit[13:0] \core_core_core_fn_unit$next sync posedge \clk update \core_core_core_fn_unit $0\core_core_core_fn_unit[13:0] end - attribute \src "libresoc.v:196564.3-196565.41" - process $proc$libresoc.v:196564$13671 + attribute \src "libresoc.v:198925.3-198926.41" + process $proc$libresoc.v:198925$13657 assign { } { } assign $0\core_core_lk[0:0] \core_core_lk$next sync posedge \clk update \core_core_lk $0\core_core_lk[0:0] end - attribute \src "libresoc.v:196566.3-196567.51" - process $proc$libresoc.v:196566$13672 + attribute \src "libresoc.v:198927.3-198928.51" + process $proc$libresoc.v:198927$13658 assign { } { } assign $0\core_core_core_rc[0:0] \core_core_core_rc$next sync posedge \clk update \core_core_core_rc $0\core_core_core_rc[0:0] end - attribute \src "libresoc.v:196568.3-196569.45" - process $proc$libresoc.v:196568$13673 + attribute \src "libresoc.v:198929.3-198930.45" + process $proc$libresoc.v:198929$13659 assign { } { } assign $0\exec_fsm_state[0:0] \exec_fsm_state$next sync posedge \clk update \exec_fsm_state $0\exec_fsm_state[0:0] end - attribute \src "libresoc.v:196570.3-196571.57" - process $proc$libresoc.v:196570$13674 + attribute \src "libresoc.v:198931.3-198932.57" + process $proc$libresoc.v:198931$13660 assign { } { } assign $0\core_core_core_rc_ok[0:0] \core_core_core_rc_ok$next sync posedge \clk update \core_core_core_rc_ok $0\core_core_core_rc_ok[0:0] end - attribute \src "libresoc.v:196572.3-196573.51" - process $proc$libresoc.v:196572$13675 + attribute \src "libresoc.v:198933.3-198934.51" + process $proc$libresoc.v:198933$13661 assign { } { } assign $0\core_core_core_oe[0:0] \core_core_core_oe$next sync posedge \clk update \core_core_core_oe $0\core_core_core_oe[0:0] end - attribute \src "libresoc.v:196574.3-196575.57" - process $proc$libresoc.v:196574$13676 + attribute \src "libresoc.v:198935.3-198936.57" + process $proc$libresoc.v:198935$13662 assign { } { } assign $0\core_core_core_oe_ok[0:0] \core_core_core_oe_ok$next sync posedge \clk update \core_core_core_oe_ok $0\core_core_core_oe_ok[0:0] end - attribute \src "libresoc.v:196576.3-196577.69" - process $proc$libresoc.v:196576$13677 + attribute \src "libresoc.v:198937.3-198938.69" + process $proc$libresoc.v:198937$13663 assign { } { } assign $0\core_core_core_input_carry[1:0] \core_core_core_input_carry$next sync posedge \clk update \core_core_core_input_carry $0\core_core_core_input_carry[1:0] end - attribute \src "libresoc.v:196578.3-196579.63" - process $proc$libresoc.v:196578$13678 + attribute \src "libresoc.v:198939.3-198940.63" + process $proc$libresoc.v:198939$13664 assign { } { } assign $0\core_core_core_traptype[7:0] \core_core_core_traptype$next sync posedge \clk update \core_core_core_traptype $0\core_core_core_traptype[7:0] end - attribute \src "libresoc.v:196580.3-196581.71" - process $proc$libresoc.v:196580$13679 + attribute \src "libresoc.v:198941.3-198942.71" + process $proc$libresoc.v:198941$13665 assign { } { } - assign $0\core_core_core_exc_$signal[0:0]$13680 \core_core_core_exc_$signal$next + assign $0\core_core_core_exc_$signal[0:0]$13666 \core_core_core_exc_$signal$next sync posedge \clk - update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$13680 + update \core_core_core_exc_$signal $0\core_core_core_exc_$signal[0:0]$13666 end - attribute \src "libresoc.v:196582.3-196583.75" - process $proc$libresoc.v:196582$13681 + attribute \src "libresoc.v:198943.3-198944.75" + process $proc$libresoc.v:198943$13667 assign { } { } - assign $0\core_core_core_exc_$signal$3[0:0]$13682 \core_core_core_exc_$signal$3$next + assign $0\core_core_core_exc_$signal$3[0:0]$13668 \core_core_core_exc_$signal$3$next sync posedge \clk - update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$13682 + update \core_core_core_exc_$signal$3 $0\core_core_core_exc_$signal$3[0:0]$13668 end - attribute \src "libresoc.v:196584.3-196585.75" - process $proc$libresoc.v:196584$13683 + attribute \src "libresoc.v:198945.3-198946.75" + process $proc$libresoc.v:198945$13669 assign { } { } - assign $0\core_core_core_exc_$signal$4[0:0]$13684 \core_core_core_exc_$signal$4$next + assign $0\core_core_core_exc_$signal$4[0:0]$13670 \core_core_core_exc_$signal$4$next sync posedge \clk - update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$13684 + update \core_core_core_exc_$signal$4 $0\core_core_core_exc_$signal$4[0:0]$13670 end - attribute \src "libresoc.v:196586.3-196587.75" - process $proc$libresoc.v:196586$13685 + attribute \src "libresoc.v:198947.3-198948.75" + process $proc$libresoc.v:198947$13671 assign { } { } - assign $0\core_core_core_exc_$signal$5[0:0]$13686 \core_core_core_exc_$signal$5$next + assign $0\core_core_core_exc_$signal$5[0:0]$13672 \core_core_core_exc_$signal$5$next sync posedge \clk - update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$13686 + update \core_core_core_exc_$signal$5 $0\core_core_core_exc_$signal$5[0:0]$13672 end - attribute \src "libresoc.v:196588.3-196589.75" - process $proc$libresoc.v:196588$13687 + attribute \src "libresoc.v:198949.3-198950.75" + process $proc$libresoc.v:198949$13673 assign { } { } - assign $0\core_core_core_exc_$signal$6[0:0]$13688 \core_core_core_exc_$signal$6$next + assign $0\core_core_core_exc_$signal$6[0:0]$13674 \core_core_core_exc_$signal$6$next sync posedge \clk - update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$13688 + update \core_core_core_exc_$signal$6 $0\core_core_core_exc_$signal$6[0:0]$13674 end - attribute \src "libresoc.v:196590.3-196591.41" - process $proc$libresoc.v:196590$13689 + attribute \src "libresoc.v:198951.3-198952.41" + process $proc$libresoc.v:198951$13675 assign { } { } assign $0\core_sv_a_nz[0:0] \core_sv_a_nz$next sync posedge \clk update \core_sv_a_nz $0\core_sv_a_nz[0:0] end - attribute \src "libresoc.v:196592.3-196593.75" - process $proc$libresoc.v:196592$13690 + attribute \src "libresoc.v:198953.3-198954.75" + process $proc$libresoc.v:198953$13676 assign { } { } - assign $0\core_core_core_exc_$signal$7[0:0]$13691 \core_core_core_exc_$signal$7$next + assign $0\core_core_core_exc_$signal$7[0:0]$13677 \core_core_core_exc_$signal$7$next sync posedge \clk - update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$13691 + update \core_core_core_exc_$signal$7 $0\core_core_core_exc_$signal$7[0:0]$13677 end - attribute \src "libresoc.v:196594.3-196595.75" - process $proc$libresoc.v:196594$13692 + attribute \src "libresoc.v:198955.3-198956.75" + process $proc$libresoc.v:198955$13678 assign { } { } - assign $0\core_core_core_exc_$signal$8[0:0]$13693 \core_core_core_exc_$signal$8$next + assign $0\core_core_core_exc_$signal$8[0:0]$13679 \core_core_core_exc_$signal$8$next sync posedge \clk - update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$13693 + update \core_core_core_exc_$signal$8 $0\core_core_core_exc_$signal$8[0:0]$13679 end - attribute \src "libresoc.v:196596.3-196597.75" - process $proc$libresoc.v:196596$13694 + attribute \src "libresoc.v:198957.3-198958.75" + process $proc$libresoc.v:198957$13680 assign { } { } - assign $0\core_core_core_exc_$signal$9[0:0]$13695 \core_core_core_exc_$signal$9$next + assign $0\core_core_core_exc_$signal$9[0:0]$13681 \core_core_core_exc_$signal$9$next sync posedge \clk - update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$13695 + update \core_core_core_exc_$signal$9 $0\core_core_core_exc_$signal$9[0:0]$13681 end - attribute \src "libresoc.v:196598.3-196599.63" - process $proc$libresoc.v:196598$13696 + attribute \src "libresoc.v:198959.3-198960.63" + process $proc$libresoc.v:198959$13682 assign { } { } assign $0\core_core_core_trapaddr[12:0] \core_core_core_trapaddr$next sync posedge \clk update \core_core_core_trapaddr $0\core_core_core_trapaddr[12:0] end - attribute \src "libresoc.v:196600.3-196601.57" - process $proc$libresoc.v:196600$13697 + attribute \src "libresoc.v:198961.3-198962.57" + process $proc$libresoc.v:198961$13683 assign { } { } assign $0\core_core_core_cr_rd[7:0] \core_core_core_cr_rd$next sync posedge \clk update \core_core_core_cr_rd $0\core_core_core_cr_rd[7:0] end - attribute \src "libresoc.v:196602.3-196603.63" - process $proc$libresoc.v:196602$13698 + attribute \src "libresoc.v:198963.3-198964.63" + process $proc$libresoc.v:198963$13684 assign { } { } assign $0\core_core_core_cr_rd_ok[0:0] \core_core_core_cr_rd_ok$next sync posedge \clk update \core_core_core_cr_rd_ok $0\core_core_core_cr_rd_ok[0:0] end - attribute \src "libresoc.v:196604.3-196605.57" - process $proc$libresoc.v:196604$13699 + attribute \src "libresoc.v:198965.3-198966.57" + process $proc$libresoc.v:198965$13685 assign { } { } assign $0\core_core_core_cr_wr[7:0] \core_core_core_cr_wr$next sync posedge \clk update \core_core_core_cr_wr $0\core_core_core_cr_wr[7:0] end - attribute \src "libresoc.v:196606.3-196607.53" - process $proc$libresoc.v:196606$13700 + attribute \src "libresoc.v:198967.3-198968.53" + process $proc$libresoc.v:198967$13686 assign { } { } assign $0\core_core_cr_wr_ok[0:0] \core_core_cr_wr_ok$next sync posedge \clk update \core_core_cr_wr_ok $0\core_core_cr_wr_ok[0:0] end - attribute \src "libresoc.v:196608.3-196609.63" - process $proc$libresoc.v:196608$13701 + attribute \src "libresoc.v:198969.3-198970.63" + process $proc$libresoc.v:198969$13687 assign { } { } assign $0\core_core_core_is_32bit[0:0] \core_core_core_is_32bit$next sync posedge \clk update \core_core_core_is_32bit $0\core_core_core_is_32bit[0:0] end - attribute \src "libresoc.v:196610.3-196611.37" - process $proc$libresoc.v:196610$13702 + attribute \src "libresoc.v:198971.3-198972.37" + process $proc$libresoc.v:198971$13688 assign { } { } assign $0\sv_changed[0:0] \sv_changed$next sync posedge \clk update \sv_changed $0\sv_changed[0:0] end - attribute \src "libresoc.v:196612.3-196613.57" - process $proc$libresoc.v:196612$13703 + attribute \src "libresoc.v:198973.3-198974.57" + process $proc$libresoc.v:198973$13689 assign { } { } - assign $0\core_bigendian_i$10[0:0]$13704 \core_bigendian_i$10$next + assign $0\core_bigendian_i$10[0:0]$13690 \core_bigendian_i$10$next sync posedge \clk - update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13704 + update \core_bigendian_i$10 $0\core_bigendian_i$10[0:0]$13690 end - attribute \src "libresoc.v:196614.3-196615.37" - process $proc$libresoc.v:196614$13705 + attribute \src "libresoc.v:198975.3-198976.37" + process $proc$libresoc.v:198975$13691 assign { } { } assign $0\pc_changed[0:0] \pc_changed$next sync posedge \clk update \pc_changed $0\pc_changed[0:0] end - attribute \src "libresoc.v:196616.3-196617.47" - process $proc$libresoc.v:196616$13706 + attribute \src "libresoc.v:198977.3-198978.47" + process $proc$libresoc.v:198977$13692 assign { } { } assign $0\issue_fsm_state[2:0] \issue_fsm_state$next sync posedge \clk update \issue_fsm_state $0\issue_fsm_state[2:0] end - attribute \src "libresoc.v:196618.3-196619.53" - process $proc$libresoc.v:196618$13707 + attribute \src "libresoc.v:198979.3-198980.53" + process $proc$libresoc.v:198979$13693 assign { } { } assign $0\dec2_raw_opcode_in[31:0] \dec2_raw_opcode_in$next sync posedge \clk update \dec2_raw_opcode_in $0\dec2_raw_opcode_in[31:0] end - attribute \src "libresoc.v:196620.3-196621.23" - process $proc$libresoc.v:196620$13708 + attribute \src "libresoc.v:198981.3-198982.23" + process $proc$libresoc.v:198981$13694 assign { } { } assign $0\nia[63:0] \nia$next sync posedge \clk update \nia $0\nia[63:0] end - attribute \src "libresoc.v:196622.3-196623.41" - process $proc$libresoc.v:196622$13709 + attribute \src "libresoc.v:198983.3-198984.41" + process $proc$libresoc.v:198983$13695 assign { } { } assign $0\dec2_cur_msr[63:0] \dec2_cur_msr$next sync posedge \clk update \dec2_cur_msr $0\dec2_cur_msr[63:0] end - attribute \src "libresoc.v:196624.3-196625.47" - process $proc$libresoc.v:196624$13710 + attribute \src "libresoc.v:198985.3-198986.47" + process $proc$libresoc.v:198985$13696 assign { } { } assign $0\fetch_fsm_state[1:0] \fetch_fsm_state$next sync posedge \clk update \fetch_fsm_state $0\fetch_fsm_state[1:0] end - attribute \src "libresoc.v:196626.3-196627.33" - process $proc$libresoc.v:196626$13711 + attribute \src "libresoc.v:198987.3-198988.33" + process $proc$libresoc.v:198987$13697 assign { } { } assign $0\msr_read[0:0] \msr_read$next sync posedge \clk update \msr_read $0\msr_read[0:0] end - attribute \src "libresoc.v:196628.3-196629.45" - process $proc$libresoc.v:196628$13712 + attribute \src "libresoc.v:198989.3-198990.45" + process $proc$libresoc.v:198989$13698 assign { } { } assign $0\cur_cur_svstep[1:0] \cur_cur_svstep$next sync posedge \clk update \cur_cur_svstep $0\cur_cur_svstep[1:0] end - attribute \src "libresoc.v:196630.3-196631.43" - process $proc$libresoc.v:196630$13713 + attribute \src "libresoc.v:198991.3-198992.43" + process $proc$libresoc.v:198991$13699 assign { } { } assign $0\cur_cur_subvl[1:0] \cur_cur_subvl$next sync posedge \clk update \cur_cur_subvl $0\cur_cur_subvl[1:0] end - attribute \src "libresoc.v:196632.3-196633.47" - process $proc$libresoc.v:196632$13714 + attribute \src "libresoc.v:198993.3-198994.47" + process $proc$libresoc.v:198993$13700 assign { } { } assign $0\cur_cur_dststep[6:0] \cur_cur_dststep$next sync posedge \clk update \cur_cur_dststep $0\cur_cur_dststep[6:0] end - attribute \src "libresoc.v:196634.3-196635.47" - process $proc$libresoc.v:196634$13715 + attribute \src "libresoc.v:198995.3-198996.47" + process $proc$libresoc.v:198995$13701 assign { } { } assign $0\core_raw_insn_i[31:0] \core_raw_insn_i$next sync posedge \clk update \core_raw_insn_i $0\core_raw_insn_i[31:0] end - attribute \src "libresoc.v:196636.3-196637.47" - process $proc$libresoc.v:196636$13716 + attribute \src "libresoc.v:198997.3-198998.47" + process $proc$libresoc.v:198997$13702 assign { } { } assign $0\cur_cur_srcstep[6:0] \cur_cur_srcstep$next sync posedge \clk update \cur_cur_srcstep $0\cur_cur_srcstep[6:0] end - attribute \src "libresoc.v:196638.3-196639.37" - process $proc$libresoc.v:196638$13717 + attribute \src "libresoc.v:198999.3-199000.37" + process $proc$libresoc.v:198999$13703 assign { } { } assign $0\cur_cur_vl[6:0] \cur_cur_vl$next sync posedge \clk update \cur_cur_vl $0\cur_cur_vl[6:0] end - attribute \src "libresoc.v:196640.3-196641.43" - process $proc$libresoc.v:196640$13718 + attribute \src "libresoc.v:199001.3-199002.43" + process $proc$libresoc.v:199001$13704 assign { } { } assign $0\cur_cur_maxvl[6:0] \cur_cur_maxvl$next sync posedge \clk update \cur_cur_maxvl $0\cur_cur_maxvl[6:0] end - attribute \src "libresoc.v:196642.3-196643.39" - process $proc$libresoc.v:196642$13719 + attribute \src "libresoc.v:199003.3-199004.39" + process $proc$libresoc.v:199003$13705 assign { } { } assign $0\dec2_cur_pc[63:0] \dec2_cur_pc$next sync posedge \clk update \dec2_cur_pc $0\dec2_cur_pc[63:0] end - attribute \src "libresoc.v:196644.3-196645.49" - process $proc$libresoc.v:196644$13720 + attribute \src "libresoc.v:199005.3-199006.49" + process $proc$libresoc.v:199005$13706 assign { } { } assign $0\svstate_ok_delay[0:0] \svstate_ok_delay$next sync posedge \clk update \svstate_ok_delay $0\svstate_ok_delay[0:0] end - attribute \src "libresoc.v:196646.3-196647.39" - process $proc$libresoc.v:196646$13721 + attribute \src "libresoc.v:199007.3-199008.39" + process $proc$libresoc.v:199007$13707 assign { } { } assign $0\pc_ok_delay[0:0] \pc_ok_delay$next sync posedge \clk update \pc_ok_delay $0\pc_ok_delay[0:0] end - attribute \src "libresoc.v:196648.3-196649.43" - process $proc$libresoc.v:196648$13722 + attribute \src "libresoc.v:199009.3-199010.43" + process $proc$libresoc.v:199009$13708 assign { } { } assign $0\cu_st__rel_o_dly[0:0] \core_cu_st__rel_o sync posedge \clk update \cu_st__rel_o_dly $0\cu_st__rel_o_dly[0:0] end - attribute \src "libresoc.v:196650.3-196651.27" - process $proc$libresoc.v:196650$13723 + attribute \src "libresoc.v:199011.3-199012.27" + process $proc$libresoc.v:199011$13709 assign { } { } assign $0\delay[1:0] \delay$next sync posedge \por_clk update \delay $0\delay[1:0] end - attribute \src "libresoc.v:196652.3-196653.43" - process $proc$libresoc.v:196652$13724 + attribute \src "libresoc.v:199013.3-199014.43" + process $proc$libresoc.v:199013$13710 assign { } { } assign $0\dec2_cur_eint[0:0] \dec2_cur_eint$next sync posedge \clk update \dec2_cur_eint $0\dec2_cur_eint[0:0] end - attribute \src "libresoc.v:196654.3-196655.47" - process $proc$libresoc.v:196654$13725 + attribute \src "libresoc.v:199015.3-199016.47" + process $proc$libresoc.v:199015$13711 assign { } { } assign $0\jtag_dmi0__dout[63:0] \jtag_dmi0__dout$next sync posedge \clk update \jtag_dmi0__dout $0\jtag_dmi0__dout[63:0] end - attribute \src "libresoc.v:197229.3-197237.6" - process $proc$libresoc.v:197229$13726 + attribute \src "libresoc.v:199546.3-199554.6" + process $proc$libresoc.v:199546$13712 assign { } { } assign { } { } - assign $0\dbg_dmi_addr_i$next[3:0]$13727 $1\dbg_dmi_addr_i$next[3:0]$13728 - attribute \src "libresoc.v:197230.5-197230.29" + assign $0\dbg_dmi_addr_i$next[3:0]$13713 $1\dbg_dmi_addr_i$next[3:0]$13714 + attribute \src "libresoc.v:199547.5-199547.29" switch \initial - attribute \src "libresoc.v:197230.9-197230.17" + attribute \src "libresoc.v:199547.9-199547.17" case 1'1 case end @@ -407801,21 +380184,21 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_dmi_addr_i$next[3:0]$13728 4'0000 + assign $1\dbg_dmi_addr_i$next[3:0]$13714 4'0000 case - assign $1\dbg_dmi_addr_i$next[3:0]$13728 \jtag_dmi0__addr_i + assign $1\dbg_dmi_addr_i$next[3:0]$13714 \jtag_dmi0__addr_i end sync always - update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$13727 + update \dbg_dmi_addr_i$next $0\dbg_dmi_addr_i$next[3:0]$13713 end - attribute \src "libresoc.v:197238.3-197246.6" - process $proc$libresoc.v:197238$13729 + attribute \src "libresoc.v:199555.3-199563.6" + process $proc$libresoc.v:199555$13715 assign { } { } assign { } { } - assign $0\dbg_dmi_req_i$next[0:0]$13730 $1\dbg_dmi_req_i$next[0:0]$13731 - attribute \src "libresoc.v:197239.5-197239.29" + assign $0\dbg_dmi_req_i$next[0:0]$13716 $1\dbg_dmi_req_i$next[0:0]$13717 + attribute \src "libresoc.v:199556.5-199556.29" switch \initial - attribute \src "libresoc.v:197239.9-197239.17" + attribute \src "libresoc.v:199556.9-199556.17" case 1'1 case end @@ -407824,15 +380207,15 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_dmi_req_i$next[0:0]$13731 1'0 + assign $1\dbg_dmi_req_i$next[0:0]$13717 1'0 case - assign $1\dbg_dmi_req_i$next[0:0]$13731 \jtag_dmi0__req_i + assign $1\dbg_dmi_req_i$next[0:0]$13717 \jtag_dmi0__req_i end sync always - update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$13730 + update \dbg_dmi_req_i$next $0\dbg_dmi_req_i$next[0:0]$13716 end - attribute \src "libresoc.v:197247.3-197291.6" - process $proc$libresoc.v:197247$13732 + attribute \src "libresoc.v:199564.3-199628.6" + process $proc$libresoc.v:199564$13718 assign { } { } assign { } { } assign { } { } @@ -407863,25 +380246,37 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $0\core_core_dststep$next[6:0]$13733 $3\core_core_dststep$next[6:0]$13763 - assign $0\core_core_maxvl$next[6:0]$13734 $3\core_core_maxvl$next[6:0]$13764 - assign $0\core_core_pc$next[63:0]$13735 $3\core_core_pc$next[63:0]$13765 - assign $0\core_core_srcstep$next[6:0]$13736 $3\core_core_srcstep$next[6:0]$13766 - assign $0\core_core_subvl$next[1:0]$13737 $3\core_core_subvl$next[1:0]$13767 - assign $0\core_core_svstep$next[1:0]$13738 $3\core_core_svstep$next[1:0]$13768 - assign $0\core_core_vl$next[6:0]$13739 $3\core_core_vl$next[6:0]$13769 - assign $0\core_dec$next[63:0]$13740 $3\core_dec$next[63:0]$13770 - assign $0\core_eint$next[0:0]$13741 $3\core_eint$next[0:0]$13771 - assign $0\core_msr$next[63:0]$13742 $3\core_msr$next[63:0]$13772 - attribute \src "libresoc.v:197248.5-197248.29" + assign $0\core_core_dststep$next[6:0]$13719 $3\core_core_dststep$next[6:0]$13749 + assign $0\core_core_maxvl$next[6:0]$13720 $3\core_core_maxvl$next[6:0]$13750 + assign $0\core_core_pc$next[63:0]$13721 $3\core_core_pc$next[63:0]$13751 + assign $0\core_core_srcstep$next[6:0]$13722 $3\core_core_srcstep$next[6:0]$13752 + assign $0\core_core_subvl$next[1:0]$13723 $3\core_core_subvl$next[1:0]$13753 + assign $0\core_core_svstep$next[1:0]$13724 $3\core_core_svstep$next[1:0]$13754 + assign $0\core_core_vl$next[6:0]$13725 $3\core_core_vl$next[6:0]$13755 + assign $0\core_dec$next[63:0]$13726 $3\core_dec$next[63:0]$13756 + assign $0\core_eint$next[0:0]$13727 $3\core_eint$next[0:0]$13757 + assign $0\core_msr$next[63:0]$13728 $3\core_msr$next[63:0]$13758 + attribute \src "libresoc.v:199565.5-199565.29" switch \initial - attribute \src "libresoc.v:197248.9-197248.17" + attribute \src "libresoc.v:199565.9-199565.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\core_core_dststep$next[6:0]$13729 \core_core_dststep + assign $1\core_core_maxvl$next[6:0]$13730 \core_core_maxvl + assign $1\core_core_pc$next[63:0]$13731 \core_core_pc + assign $1\core_core_srcstep$next[6:0]$13732 \core_core_srcstep + assign $1\core_core_subvl$next[1:0]$13733 \core_core_subvl + assign $1\core_core_svstep$next[1:0]$13734 \core_core_svstep + assign $1\core_core_vl$next[6:0]$13735 \core_core_vl + assign $1\core_dec$next[63:0]$13736 \core_dec + assign $1\core_eint$next[0:0]$13737 \core_eint + assign $1\core_msr$next[63:0]$13738 \core_msr + attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } assign { } { } @@ -407893,16 +380288,16 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $1\core_core_dststep$next[6:0]$13743 $2\core_core_dststep$next[6:0]$13753 - assign $1\core_core_maxvl$next[6:0]$13744 $2\core_core_maxvl$next[6:0]$13754 - assign $1\core_core_pc$next[63:0]$13745 $2\core_core_pc$next[63:0]$13755 - assign $1\core_core_srcstep$next[6:0]$13746 $2\core_core_srcstep$next[6:0]$13756 - assign $1\core_core_subvl$next[1:0]$13747 $2\core_core_subvl$next[1:0]$13757 - assign $1\core_core_svstep$next[1:0]$13748 $2\core_core_svstep$next[1:0]$13758 - assign $1\core_core_vl$next[6:0]$13749 $2\core_core_vl$next[6:0]$13759 - assign $1\core_dec$next[63:0]$13750 $2\core_dec$next[63:0]$13760 - assign $1\core_eint$next[0:0]$13751 $2\core_eint$next[0:0]$13761 - assign $1\core_msr$next[63:0]$13752 $2\core_msr$next[63:0]$13762 + assign $1\core_core_dststep$next[6:0]$13729 $2\core_core_dststep$next[6:0]$13739 + assign $1\core_core_maxvl$next[6:0]$13730 $2\core_core_maxvl$next[6:0]$13740 + assign $1\core_core_pc$next[63:0]$13731 $2\core_core_pc$next[63:0]$13741 + assign $1\core_core_srcstep$next[6:0]$13732 $2\core_core_srcstep$next[6:0]$13742 + assign $1\core_core_subvl$next[1:0]$13733 $2\core_core_subvl$next[1:0]$13743 + assign $1\core_core_svstep$next[1:0]$13734 $2\core_core_svstep$next[1:0]$13744 + assign $1\core_core_vl$next[6:0]$13735 $2\core_core_vl$next[6:0]$13745 + assign $1\core_dec$next[63:0]$13736 $2\core_dec$next[63:0]$13746 + assign $1\core_eint$next[0:0]$13737 $2\core_eint$next[0:0]$13747 + assign $1\core_msr$next[63:0]$13738 $2\core_msr$next[63:0]$13748 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" @@ -407917,20 +380312,68 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $2\core_core_maxvl$next[6:0]$13754 $2\core_core_vl$next[6:0]$13759 $2\core_core_srcstep$next[6:0]$13756 $2\core_core_dststep$next[6:0]$13753 $2\core_core_subvl$next[1:0]$13757 $2\core_core_svstep$next[1:0]$13758 $2\core_dec$next[63:0]$13760 $2\core_eint$next[0:0]$13761 $2\core_msr$next[63:0]$13762 $2\core_core_pc$next[63:0]$13755 } { \cur_cur_maxvl \cur_cur_vl \cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } + assign { $2\core_core_maxvl$next[6:0]$13740 $2\core_core_vl$next[6:0]$13745 $2\core_core_srcstep$next[6:0]$13742 $2\core_core_dststep$next[6:0]$13739 $2\core_core_subvl$next[1:0]$13743 $2\core_core_svstep$next[1:0]$13744 $2\core_dec$next[63:0]$13746 $2\core_eint$next[0:0]$13747 $2\core_msr$next[63:0]$13748 $2\core_core_pc$next[63:0]$13741 } { \cur_cur_maxvl \cur_cur_vl \cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } case - assign $2\core_core_dststep$next[6:0]$13753 \core_core_dststep - assign $2\core_core_maxvl$next[6:0]$13754 \core_core_maxvl - assign $2\core_core_pc$next[63:0]$13755 \core_core_pc - assign $2\core_core_srcstep$next[6:0]$13756 \core_core_srcstep - assign $2\core_core_subvl$next[1:0]$13757 \core_core_subvl - assign $2\core_core_svstep$next[1:0]$13758 \core_core_svstep - assign $2\core_core_vl$next[6:0]$13759 \core_core_vl - assign $2\core_dec$next[63:0]$13760 \core_dec - assign $2\core_eint$next[0:0]$13761 \core_eint - assign $2\core_msr$next[63:0]$13762 \core_msr + assign $2\core_core_dststep$next[6:0]$13739 \core_core_dststep + assign $2\core_core_maxvl$next[6:0]$13740 \core_core_maxvl + assign $2\core_core_pc$next[63:0]$13741 \core_core_pc + assign $2\core_core_srcstep$next[6:0]$13742 \core_core_srcstep + assign $2\core_core_subvl$next[1:0]$13743 \core_core_subvl + assign $2\core_core_svstep$next[1:0]$13744 \core_core_svstep + assign $2\core_core_vl$next[6:0]$13745 \core_core_vl + assign $2\core_dec$next[63:0]$13746 \core_dec + assign $2\core_eint$next[0:0]$13747 \core_eint + assign $2\core_msr$next[63:0]$13748 \core_msr end attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\core_core_dststep$next[6:0]$13729 \core_core_dststep + assign $1\core_core_maxvl$next[6:0]$13730 \core_core_maxvl + assign $1\core_core_pc$next[63:0]$13731 \core_core_pc + assign $1\core_core_srcstep$next[6:0]$13732 \core_core_srcstep + assign $1\core_core_subvl$next[1:0]$13733 \core_core_subvl + assign $1\core_core_svstep$next[1:0]$13734 \core_core_svstep + assign $1\core_core_vl$next[6:0]$13735 \core_core_vl + assign $1\core_dec$next[63:0]$13736 \core_dec + assign $1\core_eint$next[0:0]$13737 \core_eint + assign $1\core_msr$next[63:0]$13738 \core_msr + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign $1\core_core_dststep$next[6:0]$13729 \core_core_dststep + assign $1\core_core_maxvl$next[6:0]$13730 \core_core_maxvl + assign $1\core_core_pc$next[63:0]$13731 \core_core_pc + assign $1\core_core_srcstep$next[6:0]$13732 \core_core_srcstep + assign $1\core_core_subvl$next[1:0]$13733 \core_core_subvl + assign $1\core_core_svstep$next[1:0]$13734 \core_core_svstep + assign $1\core_core_vl$next[6:0]$13735 \core_core_vl + assign $1\core_dec$next[63:0]$13736 \core_dec + assign $1\core_eint$next[0:0]$13737 \core_eint + assign $1\core_msr$next[63:0]$13738 \core_msr + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\core_core_dststep$next[6:0]$13729 \core_core_dststep + assign $1\core_core_maxvl$next[6:0]$13730 \core_core_maxvl + assign $1\core_core_pc$next[63:0]$13731 \core_core_pc + assign $1\core_core_srcstep$next[6:0]$13732 \core_core_srcstep + assign $1\core_core_subvl$next[1:0]$13733 \core_core_subvl + assign $1\core_core_svstep$next[1:0]$13734 \core_core_svstep + assign $1\core_core_vl$next[6:0]$13735 \core_core_vl + assign $1\core_dec$next[63:0]$13736 \core_dec + assign $1\core_eint$next[0:0]$13737 \core_eint + assign $1\core_msr$next[63:0]$13738 \core_msr + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign $1\core_core_dststep$next[6:0]$13729 \core_core_dststep + assign $1\core_core_maxvl$next[6:0]$13730 \core_core_maxvl + assign $1\core_core_pc$next[63:0]$13731 \core_core_pc + assign $1\core_core_srcstep$next[6:0]$13732 \core_core_srcstep + assign $1\core_core_subvl$next[1:0]$13733 \core_core_subvl + assign $1\core_core_svstep$next[1:0]$13734 \core_core_svstep + assign $1\core_core_vl$next[6:0]$13735 \core_core_vl + assign $1\core_dec$next[63:0]$13736 \core_dec + assign $1\core_eint$next[0:0]$13737 \core_eint + assign $1\core_msr$next[63:0]$13738 \core_msr + attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign { } { } @@ -407942,18 +380385,18 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $1\core_core_maxvl$next[6:0]$13744 $1\core_core_vl$next[6:0]$13749 $1\core_core_srcstep$next[6:0]$13746 $1\core_core_dststep$next[6:0]$13743 $1\core_core_subvl$next[1:0]$13747 $1\core_core_svstep$next[1:0]$13748 $1\core_dec$next[63:0]$13750 $1\core_eint$next[0:0]$13751 $1\core_msr$next[63:0]$13752 $1\core_core_pc$next[63:0]$13745 } { \cur_cur_maxvl \cur_cur_vl \cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } + assign { $1\core_core_maxvl$next[6:0]$13730 $1\core_core_vl$next[6:0]$13735 $1\core_core_srcstep$next[6:0]$13732 $1\core_core_dststep$next[6:0]$13729 $1\core_core_subvl$next[1:0]$13733 $1\core_core_svstep$next[1:0]$13734 $1\core_dec$next[63:0]$13736 $1\core_eint$next[0:0]$13737 $1\core_msr$next[63:0]$13738 $1\core_core_pc$next[63:0]$13731 } { \cur_cur_maxvl \cur_cur_vl \cur_cur_srcstep \cur_cur_dststep \cur_cur_subvl \cur_cur_svstep \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } case - assign $1\core_core_dststep$next[6:0]$13743 \core_core_dststep - assign $1\core_core_maxvl$next[6:0]$13744 \core_core_maxvl - assign $1\core_core_pc$next[63:0]$13745 \core_core_pc - assign $1\core_core_srcstep$next[6:0]$13746 \core_core_srcstep - assign $1\core_core_subvl$next[1:0]$13747 \core_core_subvl - assign $1\core_core_svstep$next[1:0]$13748 \core_core_svstep - assign $1\core_core_vl$next[6:0]$13749 \core_core_vl - assign $1\core_dec$next[63:0]$13750 \core_dec - assign $1\core_eint$next[0:0]$13751 \core_eint - assign $1\core_msr$next[63:0]$13752 \core_msr + assign $1\core_core_dststep$next[6:0]$13729 \core_core_dststep + assign $1\core_core_maxvl$next[6:0]$13730 \core_core_maxvl + assign $1\core_core_pc$next[63:0]$13731 \core_core_pc + assign $1\core_core_srcstep$next[6:0]$13732 \core_core_srcstep + assign $1\core_core_subvl$next[1:0]$13733 \core_core_subvl + assign $1\core_core_svstep$next[1:0]$13734 \core_core_svstep + assign $1\core_core_vl$next[6:0]$13735 \core_core_vl + assign $1\core_dec$next[63:0]$13736 \core_dec + assign $1\core_eint$next[0:0]$13737 \core_eint + assign $1\core_msr$next[63:0]$13738 \core_msr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -407969,189 +380412,225 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $3\core_core_pc$next[63:0]$13765 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\core_msr$next[63:0]$13772 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\core_eint$next[0:0]$13771 1'0 - assign $3\core_dec$next[63:0]$13770 64'0000000000000000000000000000000000000000000000000000000000000000 - assign $3\core_core_svstep$next[1:0]$13768 2'00 - assign $3\core_core_subvl$next[1:0]$13767 2'00 - assign $3\core_core_dststep$next[6:0]$13763 7'0000000 - assign $3\core_core_srcstep$next[6:0]$13766 7'0000000 - assign $3\core_core_vl$next[6:0]$13769 7'0000000 - assign $3\core_core_maxvl$next[6:0]$13764 7'0000000 + assign $3\core_core_pc$next[63:0]$13751 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_msr$next[63:0]$13758 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_eint$next[0:0]$13757 1'0 + assign $3\core_dec$next[63:0]$13756 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_core_svstep$next[1:0]$13754 2'00 + assign $3\core_core_subvl$next[1:0]$13753 2'00 + assign $3\core_core_dststep$next[6:0]$13749 7'0000000 + assign $3\core_core_srcstep$next[6:0]$13752 7'0000000 + assign $3\core_core_vl$next[6:0]$13755 7'0000000 + assign $3\core_core_maxvl$next[6:0]$13750 7'0000000 case - assign $3\core_core_dststep$next[6:0]$13763 $1\core_core_dststep$next[6:0]$13743 - assign $3\core_core_maxvl$next[6:0]$13764 $1\core_core_maxvl$next[6:0]$13744 - assign $3\core_core_pc$next[63:0]$13765 $1\core_core_pc$next[63:0]$13745 - assign $3\core_core_srcstep$next[6:0]$13766 $1\core_core_srcstep$next[6:0]$13746 - assign $3\core_core_subvl$next[1:0]$13767 $1\core_core_subvl$next[1:0]$13747 - assign $3\core_core_svstep$next[1:0]$13768 $1\core_core_svstep$next[1:0]$13748 - assign $3\core_core_vl$next[6:0]$13769 $1\core_core_vl$next[6:0]$13749 - assign $3\core_dec$next[63:0]$13770 $1\core_dec$next[63:0]$13750 - assign $3\core_eint$next[0:0]$13771 $1\core_eint$next[0:0]$13751 - assign $3\core_msr$next[63:0]$13772 $1\core_msr$next[63:0]$13752 + assign $3\core_core_dststep$next[6:0]$13749 $1\core_core_dststep$next[6:0]$13729 + assign $3\core_core_maxvl$next[6:0]$13750 $1\core_core_maxvl$next[6:0]$13730 + assign $3\core_core_pc$next[63:0]$13751 $1\core_core_pc$next[63:0]$13731 + assign $3\core_core_srcstep$next[6:0]$13752 $1\core_core_srcstep$next[6:0]$13732 + assign $3\core_core_subvl$next[1:0]$13753 $1\core_core_subvl$next[1:0]$13733 + assign $3\core_core_svstep$next[1:0]$13754 $1\core_core_svstep$next[1:0]$13734 + assign $3\core_core_vl$next[6:0]$13755 $1\core_core_vl$next[6:0]$13735 + assign $3\core_dec$next[63:0]$13756 $1\core_dec$next[63:0]$13736 + assign $3\core_eint$next[0:0]$13757 $1\core_eint$next[0:0]$13737 + assign $3\core_msr$next[63:0]$13758 $1\core_msr$next[63:0]$13738 end sync always - update \core_core_dststep$next $0\core_core_dststep$next[6:0]$13733 - update \core_core_maxvl$next $0\core_core_maxvl$next[6:0]$13734 - update \core_core_pc$next $0\core_core_pc$next[63:0]$13735 - update \core_core_srcstep$next $0\core_core_srcstep$next[6:0]$13736 - update \core_core_subvl$next $0\core_core_subvl$next[1:0]$13737 - update \core_core_svstep$next $0\core_core_svstep$next[1:0]$13738 - update \core_core_vl$next $0\core_core_vl$next[6:0]$13739 - update \core_dec$next $0\core_dec$next[63:0]$13740 - update \core_eint$next $0\core_eint$next[0:0]$13741 - update \core_msr$next $0\core_msr$next[63:0]$13742 + update \core_core_dststep$next $0\core_core_dststep$next[6:0]$13719 + update \core_core_maxvl$next $0\core_core_maxvl$next[6:0]$13720 + update \core_core_pc$next $0\core_core_pc$next[63:0]$13721 + update \core_core_srcstep$next $0\core_core_srcstep$next[6:0]$13722 + update \core_core_subvl$next $0\core_core_subvl$next[1:0]$13723 + update \core_core_svstep$next $0\core_core_svstep$next[1:0]$13724 + update \core_core_vl$next $0\core_core_vl$next[6:0]$13725 + update \core_dec$next $0\core_dec$next[63:0]$13726 + update \core_eint$next $0\core_eint$next[0:0]$13727 + update \core_msr$next $0\core_msr$next[63:0]$13728 end - attribute \src "libresoc.v:197292.3-197312.6" - process $proc$libresoc.v:197292$13773 + attribute \src "libresoc.v:199629.3-199653.6" + process $proc$libresoc.v:199629$13759 assign { } { } assign { } { } assign { } { } - assign $0\core_raw_insn_i$next[31:0]$13774 $3\core_raw_insn_i$next[31:0]$13777 - attribute \src "libresoc.v:197293.5-197293.29" + assign $0\core_raw_insn_i$next[31:0]$13760 $3\core_raw_insn_i$next[31:0]$13763 + attribute \src "libresoc.v:199630.5-199630.29" switch \initial - attribute \src "libresoc.v:197293.9-197293.17" + attribute \src "libresoc.v:199630.9-199630.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\core_raw_insn_i$next[31:0]$13761 \core_raw_insn_i + attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } - assign $1\core_raw_insn_i$next[31:0]$13775 $2\core_raw_insn_i$next[31:0]$13776 + assign $1\core_raw_insn_i$next[31:0]$13761 $2\core_raw_insn_i$next[31:0]$13762 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\core_raw_insn_i$next[31:0]$13776 \dec2_raw_opcode_in + assign $2\core_raw_insn_i$next[31:0]$13762 \dec2_raw_opcode_in case - assign $2\core_raw_insn_i$next[31:0]$13776 \core_raw_insn_i + assign $2\core_raw_insn_i$next[31:0]$13762 \core_raw_insn_i end case - assign $1\core_raw_insn_i$next[31:0]$13775 \core_raw_insn_i + assign $1\core_raw_insn_i$next[31:0]$13761 \core_raw_insn_i end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\core_raw_insn_i$next[31:0]$13777 0 + assign $3\core_raw_insn_i$next[31:0]$13763 0 case - assign $3\core_raw_insn_i$next[31:0]$13777 $1\core_raw_insn_i$next[31:0]$13775 + assign $3\core_raw_insn_i$next[31:0]$13763 $1\core_raw_insn_i$next[31:0]$13761 end sync always - update \core_raw_insn_i$next $0\core_raw_insn_i$next[31:0]$13774 + update \core_raw_insn_i$next $0\core_raw_insn_i$next[31:0]$13760 end - attribute \src "libresoc.v:197313.3-197337.6" - process $proc$libresoc.v:197313$13778 + attribute \src "libresoc.v:199654.3-199698.6" + process $proc$libresoc.v:199654$13764 assign { } { } assign { } { } assign { } { } - assign $0\core_bigendian_i$10$next[0:0]$13779 $3\core_bigendian_i$10$next[0:0]$13782 - attribute \src "libresoc.v:197314.5-197314.29" + assign $0\core_bigendian_i$10$next[0:0]$13765 $3\core_bigendian_i$10$next[0:0]$13768 + attribute \src "libresoc.v:199655.5-199655.29" switch \initial - attribute \src "libresoc.v:197314.9-197314.17" + attribute \src "libresoc.v:199655.9-199655.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\core_bigendian_i$10$next[0:0]$13766 \core_bigendian_i$10 + attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } - assign $1\core_bigendian_i$10$next[0:0]$13780 $2\core_bigendian_i$10$next[0:0]$13781 + assign $1\core_bigendian_i$10$next[0:0]$13766 $2\core_bigendian_i$10$next[0:0]$13767 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\core_bigendian_i$10$next[0:0]$13781 \core_bigendian_i + assign $2\core_bigendian_i$10$next[0:0]$13767 \core_bigendian_i case - assign $2\core_bigendian_i$10$next[0:0]$13781 \core_bigendian_i$10 + assign $2\core_bigendian_i$10$next[0:0]$13767 \core_bigendian_i$10 end attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\core_bigendian_i$10$next[0:0]$13766 \core_bigendian_i$10 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign $1\core_bigendian_i$10$next[0:0]$13766 \core_bigendian_i$10 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\core_bigendian_i$10$next[0:0]$13766 \core_bigendian_i$10 + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign $1\core_bigendian_i$10$next[0:0]$13766 \core_bigendian_i$10 + attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } - assign $1\core_bigendian_i$10$next[0:0]$13780 \core_bigendian_i + assign $1\core_bigendian_i$10$next[0:0]$13766 \core_bigendian_i case - assign $1\core_bigendian_i$10$next[0:0]$13780 \core_bigendian_i$10 + assign $1\core_bigendian_i$10$next[0:0]$13766 \core_bigendian_i$10 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\core_bigendian_i$10$next[0:0]$13782 1'0 + assign $3\core_bigendian_i$10$next[0:0]$13768 1'0 case - assign $3\core_bigendian_i$10$next[0:0]$13782 $1\core_bigendian_i$10$next[0:0]$13780 + assign $3\core_bigendian_i$10$next[0:0]$13768 $1\core_bigendian_i$10$next[0:0]$13766 end sync always - update \core_bigendian_i$10$next $0\core_bigendian_i$10$next[0:0]$13779 + update \core_bigendian_i$10$next $0\core_bigendian_i$10$next[0:0]$13765 end - attribute \src "libresoc.v:197338.3-197362.6" - process $proc$libresoc.v:197338$13783 + attribute \src "libresoc.v:199699.3-199743.6" + process $proc$libresoc.v:199699$13769 assign { } { } assign { } { } assign { } { } - assign $0\core_sv_a_nz$next[0:0]$13784 $3\core_sv_a_nz$next[0:0]$13787 - attribute \src "libresoc.v:197339.5-197339.29" + assign $0\core_sv_a_nz$next[0:0]$13770 $3\core_sv_a_nz$next[0:0]$13773 + attribute \src "libresoc.v:199700.5-199700.29" switch \initial - attribute \src "libresoc.v:197339.9-197339.17" + attribute \src "libresoc.v:199700.9-199700.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\core_sv_a_nz$next[0:0]$13771 \core_sv_a_nz + attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } - assign $1\core_sv_a_nz$next[0:0]$13785 $2\core_sv_a_nz$next[0:0]$13786 + assign $1\core_sv_a_nz$next[0:0]$13771 $2\core_sv_a_nz$next[0:0]$13772 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\core_sv_a_nz$next[0:0]$13786 \dec2_sv_a_nz + assign $2\core_sv_a_nz$next[0:0]$13772 \dec2_sv_a_nz case - assign $2\core_sv_a_nz$next[0:0]$13786 \core_sv_a_nz + assign $2\core_sv_a_nz$next[0:0]$13772 \core_sv_a_nz end attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\core_sv_a_nz$next[0:0]$13771 \core_sv_a_nz + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign $1\core_sv_a_nz$next[0:0]$13771 \core_sv_a_nz + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\core_sv_a_nz$next[0:0]$13771 \core_sv_a_nz + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign $1\core_sv_a_nz$next[0:0]$13771 \core_sv_a_nz + attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } - assign $1\core_sv_a_nz$next[0:0]$13785 \dec2_sv_a_nz + assign $1\core_sv_a_nz$next[0:0]$13771 \dec2_sv_a_nz case - assign $1\core_sv_a_nz$next[0:0]$13785 \core_sv_a_nz + assign $1\core_sv_a_nz$next[0:0]$13771 \core_sv_a_nz end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\core_sv_a_nz$next[0:0]$13787 1'0 + assign $3\core_sv_a_nz$next[0:0]$13773 1'0 case - assign $3\core_sv_a_nz$next[0:0]$13787 $1\core_sv_a_nz$next[0:0]$13785 + assign $3\core_sv_a_nz$next[0:0]$13773 $1\core_sv_a_nz$next[0:0]$13771 end sync always - update \core_sv_a_nz$next $0\core_sv_a_nz$next[0:0]$13784 + update \core_sv_a_nz$next $0\core_sv_a_nz$next[0:0]$13770 end - attribute \src "libresoc.v:197363.3-197400.6" - process $proc$libresoc.v:197363$13788 + attribute \src "libresoc.v:199744.3-199789.6" + process $proc$libresoc.v:199744$13774 assign { } { } assign { } { } assign { } { } assign $0\insn_done[0:0] $4\insn_done[0:0] - attribute \src "libresoc.v:197364.5-197364.29" + attribute \src "libresoc.v:199745.5-199745.29" switch \initial - attribute \src "libresoc.v:197364.9-197364.17" + attribute \src "libresoc.v:199745.9-199745.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\insn_done[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } assign $1\insn_done[0:0] $2\insn_done[0:0] @@ -408176,19 +380655,22 @@ module \ti case assign $1\insn_done[0:0] 1'0 end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" + case 1'0 + assign $4\insn_done[0:0] $1\insn_done[0:0] + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\insn_done[0:0] $5\insn_done[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:731" switch \$236 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\insn_done[0:0] $6\insn_done[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" switch \exec_pc_ready_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -408206,20 +380688,26 @@ module \ti sync always update \insn_done $0\insn_done[0:0] end - attribute \src "libresoc.v:197401.3-197411.6" - process $proc$libresoc.v:197401$13789 + attribute \src "libresoc.v:199790.3-199808.6" + process $proc$libresoc.v:199790$13775 assign { } { } assign { } { } assign $0\pred_insn_valid_i[0:0] $1\pred_insn_valid_i[0:0] - attribute \src "libresoc.v:197402.5-197402.29" + attribute \src "libresoc.v:199791.5-199791.29" switch \initial - attribute \src "libresoc.v:197402.9-197402.17" + attribute \src "libresoc.v:199791.9-199791.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\pred_insn_valid_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\pred_insn_valid_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } assign $1\pred_insn_valid_i[0:0] 1'1 @@ -408229,20 +380717,29 @@ module \ti sync always update \pred_insn_valid_i $0\pred_insn_valid_i[0:0] end - attribute \src "libresoc.v:197412.3-197422.6" - process $proc$libresoc.v:197412$13790 + attribute \src "libresoc.v:199809.3-199831.6" + process $proc$libresoc.v:199809$13776 assign { } { } assign { } { } assign $0\pred_mask_ready_i[0:0] $1\pred_mask_ready_i[0:0] - attribute \src "libresoc.v:197413.5-197413.29" + attribute \src "libresoc.v:199810.5-199810.29" switch \initial - attribute \src "libresoc.v:197413.9-197413.17" + attribute \src "libresoc.v:199810.9-199810.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\pred_mask_ready_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\pred_mask_ready_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\pred_mask_ready_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } assign $1\pred_mask_ready_i[0:0] 1'1 @@ -408252,20 +380749,32 @@ module \ti sync always update \pred_mask_ready_i $0\pred_mask_ready_i[0:0] end - attribute \src "libresoc.v:197423.3-197433.6" - process $proc$libresoc.v:197423$13791 + attribute \src "libresoc.v:199832.3-199858.6" + process $proc$libresoc.v:199832$13777 assign { } { } assign { } { } assign $0\exec_insn_valid_i[0:0] $1\exec_insn_valid_i[0:0] - attribute \src "libresoc.v:197424.5-197424.29" + attribute \src "libresoc.v:199833.5-199833.29" switch \initial - attribute \src "libresoc.v:197424.9-197424.17" + attribute \src "libresoc.v:199833.9-199833.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\exec_insn_valid_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\exec_insn_valid_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\exec_insn_valid_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign $1\exec_insn_valid_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } assign $1\exec_insn_valid_i[0:0] 1'1 @@ -408275,24 +380784,39 @@ module \ti sync always update \exec_insn_valid_i $0\exec_insn_valid_i[0:0] end - attribute \src "libresoc.v:197434.3-197449.6" - process $proc$libresoc.v:197434$13792 + attribute \src "libresoc.v:199859.3-199894.6" + process $proc$libresoc.v:199859$13778 assign { } { } assign { } { } assign $0\exec_pc_ready_i[0:0] $1\exec_pc_ready_i[0:0] - attribute \src "libresoc.v:197435.5-197435.29" + attribute \src "libresoc.v:199860.5-199860.29" switch \initial - attribute \src "libresoc.v:197435.9-197435.17" + attribute \src "libresoc.v:199860.9-199860.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\exec_pc_ready_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\exec_pc_ready_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\exec_pc_ready_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign $1\exec_pc_ready_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\exec_pc_ready_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 3'101 assign { } { } assign $1\exec_pc_ready_i[0:0] $2\exec_pc_ready_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" switch \$242 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -408307,30 +380831,45 @@ module \ti sync always update \exec_pc_ready_i $0\exec_pc_ready_i[0:0] end - attribute \src "libresoc.v:197450.3-197470.6" - process $proc$libresoc.v:197450$13793 + attribute \src "libresoc.v:199895.3-199935.6" + process $proc$libresoc.v:199895$13779 assign { } { } assign { } { } assign $0\is_last[0:0] $1\is_last[0:0] - attribute \src "libresoc.v:197451.5-197451.29" + attribute \src "libresoc.v:199896.5-199896.29" switch \initial - attribute \src "libresoc.v:197451.9-197451.17" + attribute \src "libresoc.v:199896.9-199896.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\is_last[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\is_last[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\is_last[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign $1\is_last[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\is_last[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 3'101 assign { } { } assign $1\is_last[0:0] $2\is_last[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" switch \$248 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $2\is_last[0:0] $3\is_last[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:620" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:621" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -408348,64 +380887,64 @@ module \ti sync always update \is_last $0\is_last[0:0] end - attribute \src "libresoc.v:197471.3-197480.6" - process $proc$libresoc.v:197471$13794 + attribute \src "libresoc.v:199936.3-199945.6" + process $proc$libresoc.v:199936$13780 assign { } { } assign { } { } - assign $0\core_wen$11[2:0]$13795 $1\core_wen$11[2:0]$13796 - attribute \src "libresoc.v:197472.5-197472.29" + assign $0\core_wen$11[2:0]$13781 $1\core_wen$11[2:0]$13782 + attribute \src "libresoc.v:199937.5-199937.29" switch \initial - attribute \src "libresoc.v:197472.9-197472.17" + attribute \src "libresoc.v:199937.9-199937.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:683" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:684" switch \update_svstate attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\core_wen$11[2:0]$13796 3'100 + assign $1\core_wen$11[2:0]$13782 3'100 case - assign $1\core_wen$11[2:0]$13796 3'000 + assign $1\core_wen$11[2:0]$13782 3'000 end sync always - update \core_wen$11 $0\core_wen$11[2:0]$13795 + update \core_wen$11 $0\core_wen$11[2:0]$13781 end - attribute \src "libresoc.v:197481.3-197490.6" - process $proc$libresoc.v:197481$13797 + attribute \src "libresoc.v:199946.3-199955.6" + process $proc$libresoc.v:199946$13783 assign { } { } assign { } { } - assign $0\core_data_i$12[63:0]$13798 $1\core_data_i$12[63:0]$13799 - attribute \src "libresoc.v:197482.5-197482.29" + assign $0\core_data_i$12[63:0]$13784 $1\core_data_i$12[63:0]$13785 + attribute \src "libresoc.v:199947.5-199947.29" switch \initial - attribute \src "libresoc.v:197482.9-197482.17" + attribute \src "libresoc.v:199947.9-199947.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:683" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:684" switch \update_svstate attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\core_data_i$12[63:0]$13799 \$252 + assign $1\core_data_i$12[63:0]$13785 \$252 case - assign $1\core_data_i$12[63:0]$13799 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\core_data_i$12[63:0]$13785 64'0000000000000000000000000000000000000000000000000000000000000000 end sync always - update \core_data_i$12 $0\core_data_i$12[63:0]$13798 + update \core_data_i$12 $0\core_data_i$12[63:0]$13784 end - attribute \src "libresoc.v:197491.3-197501.6" - process $proc$libresoc.v:197491$13800 + attribute \src "libresoc.v:199956.3-199966.6" + process $proc$libresoc.v:199956$13786 assign { } { } assign { } { } assign $0\exec_insn_ready_o[0:0] $1\exec_insn_ready_o[0:0] - attribute \src "libresoc.v:197492.5-197492.29" + attribute \src "libresoc.v:199957.5-199957.29" switch \initial - attribute \src "libresoc.v:197492.9-197492.17" + attribute \src "libresoc.v:199957.9-199957.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 @@ -408417,24 +380956,24 @@ module \ti sync always update \exec_insn_ready_o $0\exec_insn_ready_o[0:0] end - attribute \src "libresoc.v:197502.3-197526.6" - process $proc$libresoc.v:197502$13801 + attribute \src "libresoc.v:199967.3-199991.6" + process $proc$libresoc.v:199967$13787 assign { } { } assign { } { } assign $0\core_ivalid_i[0:0] $1\core_ivalid_i[0:0] - attribute \src "libresoc.v:197503.5-197503.29" + attribute \src "libresoc.v:199968.5-199968.29" switch \initial - attribute \src "libresoc.v:197503.9-197503.17" + attribute \src "libresoc.v:199968.9-199968.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 assign { } { } assign $1\core_ivalid_i[0:0] $2\core_ivalid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:714" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:715" switch \exec_insn_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -408447,7 +380986,7 @@ module \ti case 1'1 assign { } { } assign $1\core_ivalid_i[0:0] $3\core_ivalid_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:723" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:724" switch \$254 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -408462,24 +381001,24 @@ module \ti sync always update \core_ivalid_i $0\core_ivalid_i[0:0] end - attribute \src "libresoc.v:197527.3-197542.6" - process $proc$libresoc.v:197527$13802 + attribute \src "libresoc.v:199992.3-200007.6" + process $proc$libresoc.v:199992$13788 assign { } { } assign { } { } assign $0\core_issue_i[0:0] $1\core_issue_i[0:0] - attribute \src "libresoc.v:197528.5-197528.29" + attribute \src "libresoc.v:199993.5-199993.29" switch \initial - attribute \src "libresoc.v:197528.9-197528.17" + attribute \src "libresoc.v:199993.9-199993.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 assign { } { } assign $1\core_issue_i[0:0] $2\core_issue_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:714" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:715" switch \exec_insn_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -408494,88 +381033,91 @@ module \ti sync always update \core_issue_i $0\core_issue_i[0:0] end - attribute \src "libresoc.v:197543.3-197577.6" - process $proc$libresoc.v:197543$13803 + attribute \src "libresoc.v:200008.3-200042.6" + process $proc$libresoc.v:200008$13789 assign { } { } assign { } { } assign { } { } - assign $0\exec_fsm_state$next[0:0]$13804 $5\exec_fsm_state$next[0:0]$13809 - attribute \src "libresoc.v:197544.5-197544.29" + assign $0\exec_fsm_state$next[0:0]$13790 $5\exec_fsm_state$next[0:0]$13795 + attribute \src "libresoc.v:200009.5-200009.29" switch \initial - attribute \src "libresoc.v:197544.9-197544.17" + attribute \src "libresoc.v:200009.9-200009.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 assign { } { } - assign $1\exec_fsm_state$next[0:0]$13805 $2\exec_fsm_state$next[0:0]$13806 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:714" + assign $1\exec_fsm_state$next[0:0]$13791 $2\exec_fsm_state$next[0:0]$13792 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:715" switch \exec_insn_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\exec_fsm_state$next[0:0]$13806 1'1 + assign $2\exec_fsm_state$next[0:0]$13792 1'1 case - assign $2\exec_fsm_state$next[0:0]$13806 \exec_fsm_state + assign $2\exec_fsm_state$next[0:0]$13792 \exec_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\exec_fsm_state$next[0:0]$13805 $3\exec_fsm_state$next[0:0]$13807 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" + assign $1\exec_fsm_state$next[0:0]$13791 $3\exec_fsm_state$next[0:0]$13793 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:731" switch \$256 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\exec_fsm_state$next[0:0]$13807 $4\exec_fsm_state$next[0:0]$13808 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:732" + assign $3\exec_fsm_state$next[0:0]$13793 $4\exec_fsm_state$next[0:0]$13794 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:733" switch \exec_pc_ready_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\exec_fsm_state$next[0:0]$13808 1'0 + assign $4\exec_fsm_state$next[0:0]$13794 1'0 case - assign $4\exec_fsm_state$next[0:0]$13808 \exec_fsm_state + assign $4\exec_fsm_state$next[0:0]$13794 \exec_fsm_state end case - assign $3\exec_fsm_state$next[0:0]$13807 \exec_fsm_state + assign $3\exec_fsm_state$next[0:0]$13793 \exec_fsm_state end case - assign $1\exec_fsm_state$next[0:0]$13805 \exec_fsm_state + assign $1\exec_fsm_state$next[0:0]$13791 \exec_fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\exec_fsm_state$next[0:0]$13809 1'0 + assign $5\exec_fsm_state$next[0:0]$13795 1'0 case - assign $5\exec_fsm_state$next[0:0]$13809 $1\exec_fsm_state$next[0:0]$13805 + assign $5\exec_fsm_state$next[0:0]$13795 $1\exec_fsm_state$next[0:0]$13791 end sync always - update \exec_fsm_state$next $0\exec_fsm_state$next[0:0]$13804 + update \exec_fsm_state$next $0\exec_fsm_state$next[0:0]$13790 end - attribute \src "libresoc.v:197578.3-197593.6" - process $proc$libresoc.v:197578$13810 + attribute \src "libresoc.v:200043.3-200062.6" + process $proc$libresoc.v:200043$13796 assign { } { } assign { } { } assign $0\exec_pc_valid_o[0:0] $1\exec_pc_valid_o[0:0] - attribute \src "libresoc.v:197579.5-197579.29" + attribute \src "libresoc.v:200044.5-200044.29" switch \initial - attribute \src "libresoc.v:197579.9-197579.17" + attribute \src "libresoc.v:200044.9-200044.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" + case 1'0 + assign $1\exec_pc_valid_o[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $1\exec_pc_valid_o[0:0] $2\exec_pc_valid_o[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:730" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:731" switch \$258 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -408590,18 +381132,18 @@ module \ti sync always update \exec_pc_valid_o $0\exec_pc_valid_o[0:0] end - attribute \src "libresoc.v:197594.3-197603.6" - process $proc$libresoc.v:197594$13811 + attribute \src "libresoc.v:200063.3-200072.6" + process $proc$libresoc.v:200063$13797 assign { } { } assign { } { } assign $0\core_dmi__addr[4:0] $1\core_dmi__addr[4:0] - attribute \src "libresoc.v:197595.5-197595.29" + attribute \src "libresoc.v:200064.5-200064.29" switch \initial - attribute \src "libresoc.v:197595.9-197595.17" + attribute \src "libresoc.v:200064.9-200064.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:938" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:939" switch \dbg_d_gpr_req attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -408613,18 +381155,18 @@ module \ti sync always update \core_dmi__addr $0\core_dmi__addr[4:0] end - attribute \src "libresoc.v:197604.3-197613.6" - process $proc$libresoc.v:197604$13812 + attribute \src "libresoc.v:200073.3-200082.6" + process $proc$libresoc.v:200073$13798 assign { } { } assign { } { } assign $0\core_dmi__ren[0:0] $1\core_dmi__ren[0:0] - attribute \src "libresoc.v:197605.5-197605.29" + attribute \src "libresoc.v:200074.5-200074.29" switch \initial - attribute \src "libresoc.v:197605.9-197605.17" + attribute \src "libresoc.v:200074.9-200074.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:938" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:939" switch \dbg_d_gpr_req attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -408636,14 +381178,14 @@ module \ti sync always update \core_dmi__ren $0\core_dmi__ren[0:0] end - attribute \src "libresoc.v:197614.3-197622.6" - process $proc$libresoc.v:197614$13813 + attribute \src "libresoc.v:200083.3-200091.6" + process $proc$libresoc.v:200083$13799 assign { } { } assign { } { } - assign $0\d_reg_delay$next[0:0]$13814 $1\d_reg_delay$next[0:0]$13815 - attribute \src "libresoc.v:197615.5-197615.29" + assign $0\d_reg_delay$next[0:0]$13800 $1\d_reg_delay$next[0:0]$13801 + attribute \src "libresoc.v:200084.5-200084.29" switch \initial - attribute \src "libresoc.v:197615.9-197615.17" + attribute \src "libresoc.v:200084.9-200084.17" case 1'1 case end @@ -408652,25 +381194,25 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\d_reg_delay$next[0:0]$13815 1'0 + assign $1\d_reg_delay$next[0:0]$13801 1'0 case - assign $1\d_reg_delay$next[0:0]$13815 \dbg_d_gpr_req + assign $1\d_reg_delay$next[0:0]$13801 \dbg_d_gpr_req end sync always - update \d_reg_delay$next $0\d_reg_delay$next[0:0]$13814 + update \d_reg_delay$next $0\d_reg_delay$next[0:0]$13800 end - attribute \src "libresoc.v:197623.3-197632.6" - process $proc$libresoc.v:197623$13816 + attribute \src "libresoc.v:200092.3-200101.6" + process $proc$libresoc.v:200092$13802 assign { } { } assign { } { } assign $0\dbg_d_gpr_data[63:0] $1\dbg_d_gpr_data[63:0] - attribute \src "libresoc.v:197624.5-197624.29" + attribute \src "libresoc.v:200093.5-200093.29" switch \initial - attribute \src "libresoc.v:197624.9-197624.17" + attribute \src "libresoc.v:200093.9-200093.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:948" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:949" switch \d_reg_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -408682,18 +381224,18 @@ module \ti sync always update \dbg_d_gpr_data $0\dbg_d_gpr_data[63:0] end - attribute \src "libresoc.v:197633.3-197642.6" - process $proc$libresoc.v:197633$13817 + attribute \src "libresoc.v:200102.3-200111.6" + process $proc$libresoc.v:200102$13803 assign { } { } assign { } { } assign $0\dbg_d_gpr_ack[0:0] $1\dbg_d_gpr_ack[0:0] - attribute \src "libresoc.v:197634.5-197634.29" + attribute \src "libresoc.v:200103.5-200103.29" switch \initial - attribute \src "libresoc.v:197634.9-197634.17" + attribute \src "libresoc.v:200103.9-200103.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:948" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:949" switch \d_reg_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -408705,18 +381247,18 @@ module \ti sync always update \dbg_d_gpr_ack $0\dbg_d_gpr_ack[0:0] end - attribute \src "libresoc.v:197643.3-197652.6" - process $proc$libresoc.v:197643$13818 + attribute \src "libresoc.v:200112.3-200121.6" + process $proc$libresoc.v:200112$13804 assign { } { } assign { } { } assign $0\core_full_rd2__ren[7:0] $1\core_full_rd2__ren[7:0] - attribute \src "libresoc.v:197644.5-197644.29" + attribute \src "libresoc.v:200113.5-200113.29" switch \initial - attribute \src "libresoc.v:197644.9-197644.17" + attribute \src "libresoc.v:200113.9-200113.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:954" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:955" switch \dbg_d_cr_req attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -408728,14 +381270,14 @@ module \ti sync always update \core_full_rd2__ren $0\core_full_rd2__ren[7:0] end - attribute \src "libresoc.v:197653.3-197661.6" - process $proc$libresoc.v:197653$13819 + attribute \src "libresoc.v:200122.3-200130.6" + process $proc$libresoc.v:200122$13805 assign { } { } assign { } { } - assign $0\d_cr_delay$next[0:0]$13820 $1\d_cr_delay$next[0:0]$13821 - attribute \src "libresoc.v:197654.5-197654.29" + assign $0\d_cr_delay$next[0:0]$13806 $1\d_cr_delay$next[0:0]$13807 + attribute \src "libresoc.v:200123.5-200123.29" switch \initial - attribute \src "libresoc.v:197654.9-197654.17" + attribute \src "libresoc.v:200123.9-200123.17" case 1'1 case end @@ -408744,25 +381286,25 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\d_cr_delay$next[0:0]$13821 1'0 + assign $1\d_cr_delay$next[0:0]$13807 1'0 case - assign $1\d_cr_delay$next[0:0]$13821 \dbg_d_cr_req + assign $1\d_cr_delay$next[0:0]$13807 \dbg_d_cr_req end sync always - update \d_cr_delay$next $0\d_cr_delay$next[0:0]$13820 + update \d_cr_delay$next $0\d_cr_delay$next[0:0]$13806 end - attribute \src "libresoc.v:197662.3-197671.6" - process $proc$libresoc.v:197662$13822 + attribute \src "libresoc.v:200131.3-200140.6" + process $proc$libresoc.v:200131$13808 assign { } { } assign { } { } assign $0\dbg_d_cr_data[63:0] $1\dbg_d_cr_data[63:0] - attribute \src "libresoc.v:197663.5-197663.29" + attribute \src "libresoc.v:200132.5-200132.29" switch \initial - attribute \src "libresoc.v:197663.9-197663.17" + attribute \src "libresoc.v:200132.9-200132.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:958" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:959" switch \d_cr_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -408774,18 +381316,18 @@ module \ti sync always update \dbg_d_cr_data $0\dbg_d_cr_data[63:0] end - attribute \src "libresoc.v:197672.3-197681.6" - process $proc$libresoc.v:197672$13823 + attribute \src "libresoc.v:200141.3-200150.6" + process $proc$libresoc.v:200141$13809 assign { } { } assign { } { } assign $0\dbg_d_cr_ack[0:0] $1\dbg_d_cr_ack[0:0] - attribute \src "libresoc.v:197673.5-197673.29" + attribute \src "libresoc.v:200142.5-200142.29" switch \initial - attribute \src "libresoc.v:197673.9-197673.17" + attribute \src "libresoc.v:200142.9-200142.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:958" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:959" switch \d_cr_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -408797,18 +381339,18 @@ module \ti sync always update \dbg_d_cr_ack $0\dbg_d_cr_ack[0:0] end - attribute \src "libresoc.v:197682.3-197691.6" - process $proc$libresoc.v:197682$13824 + attribute \src "libresoc.v:200151.3-200160.6" + process $proc$libresoc.v:200151$13810 assign { } { } assign { } { } assign $0\core_full_rd__ren[2:0] $1\core_full_rd__ren[2:0] - attribute \src "libresoc.v:197683.5-197683.29" + attribute \src "libresoc.v:200152.5-200152.29" switch \initial - attribute \src "libresoc.v:197683.9-197683.17" + attribute \src "libresoc.v:200152.9-200152.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:964" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:965" switch \dbg_d_xer_req attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -408820,14 +381362,14 @@ module \ti sync always update \core_full_rd__ren $0\core_full_rd__ren[2:0] end - attribute \src "libresoc.v:197692.3-197700.6" - process $proc$libresoc.v:197692$13825 + attribute \src "libresoc.v:200161.3-200169.6" + process $proc$libresoc.v:200161$13811 assign { } { } assign { } { } - assign $0\d_xer_delay$next[0:0]$13826 $1\d_xer_delay$next[0:0]$13827 - attribute \src "libresoc.v:197693.5-197693.29" + assign $0\d_xer_delay$next[0:0]$13812 $1\d_xer_delay$next[0:0]$13813 + attribute \src "libresoc.v:200162.5-200162.29" switch \initial - attribute \src "libresoc.v:197693.9-197693.17" + attribute \src "libresoc.v:200162.9-200162.17" case 1'1 case end @@ -408836,25 +381378,25 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\d_xer_delay$next[0:0]$13827 1'0 + assign $1\d_xer_delay$next[0:0]$13813 1'0 case - assign $1\d_xer_delay$next[0:0]$13827 \dbg_d_xer_req + assign $1\d_xer_delay$next[0:0]$13813 \dbg_d_xer_req end sync always - update \d_xer_delay$next $0\d_xer_delay$next[0:0]$13826 + update \d_xer_delay$next $0\d_xer_delay$next[0:0]$13812 end - attribute \src "libresoc.v:197701.3-197710.6" - process $proc$libresoc.v:197701$13828 + attribute \src "libresoc.v:200170.3-200179.6" + process $proc$libresoc.v:200170$13814 assign { } { } assign { } { } assign $0\dbg_d_xer_data[63:0] $1\dbg_d_xer_data[63:0] - attribute \src "libresoc.v:197702.5-197702.29" + attribute \src "libresoc.v:200171.5-200171.29" switch \initial - attribute \src "libresoc.v:197702.9-197702.17" + attribute \src "libresoc.v:200171.9-200171.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:968" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:969" switch \d_xer_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -408866,18 +381408,18 @@ module \ti sync always update \dbg_d_xer_data $0\dbg_d_xer_data[63:0] end - attribute \src "libresoc.v:197711.3-197720.6" - process $proc$libresoc.v:197711$13829 + attribute \src "libresoc.v:200180.3-200189.6" + process $proc$libresoc.v:200180$13815 assign { } { } assign { } { } assign $0\dbg_d_xer_ack[0:0] $1\dbg_d_xer_ack[0:0] - attribute \src "libresoc.v:197712.5-197712.29" + attribute \src "libresoc.v:200181.5-200181.29" switch \initial - attribute \src "libresoc.v:197712.9-197712.17" + attribute \src "libresoc.v:200181.9-200181.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:968" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:969" switch \d_xer_delay attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -408889,24 +381431,27 @@ module \ti sync always update \dbg_d_xer_ack $0\dbg_d_xer_ack[0:0] end - attribute \src "libresoc.v:197721.3-197735.6" - process $proc$libresoc.v:197721$13830 + attribute \src "libresoc.v:200190.3-200208.6" + process $proc$libresoc.v:200190$13816 assign { } { } assign { } { } assign $0\core_issue__addr[2:0] $1\core_issue__addr[2:0] - attribute \src "libresoc.v:197722.5-197722.29" + attribute \src "libresoc.v:200191.5-200191.29" switch \initial - attribute \src "libresoc.v:197722.9-197722.17" + attribute \src "libresoc.v:200191.9-200191.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:990" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\core_issue__addr[2:0] 3'110 attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign $1\core_issue__addr[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\core_issue__addr[2:0] 3'111 @@ -408916,24 +381461,27 @@ module \ti sync always update \core_issue__addr $0\core_issue__addr[2:0] end - attribute \src "libresoc.v:197736.3-197750.6" - process $proc$libresoc.v:197736$13831 + attribute \src "libresoc.v:200209.3-200227.6" + process $proc$libresoc.v:200209$13817 assign { } { } assign { } { } assign $0\core_issue__ren[0:0] $1\core_issue__ren[0:0] - attribute \src "libresoc.v:197737.5-197737.29" + attribute \src "libresoc.v:200210.5-200210.29" switch \initial - attribute \src "libresoc.v:197737.9-197737.17" + attribute \src "libresoc.v:200210.9-200210.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:990" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } assign $1\core_issue__ren[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign $1\core_issue__ren[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\core_issue__ren[0:0] 1'1 @@ -408943,65 +381491,68 @@ module \ti sync always update \core_issue__ren $0\core_issue__ren[0:0] end - attribute \src "libresoc.v:197751.3-197778.6" - process $proc$libresoc.v:197751$13832 + attribute \src "libresoc.v:200228.3-200255.6" + process $proc$libresoc.v:200228$13818 assign { } { } assign { } { } assign { } { } - assign $0\fsm_state$next[1:0]$13833 $2\fsm_state$next[1:0]$13835 - attribute \src "libresoc.v:197752.5-197752.29" + assign $0\fsm_state$next[1:0]$13819 $2\fsm_state$next[1:0]$13821 + attribute \src "libresoc.v:200229.5-200229.29" switch \initial - attribute \src "libresoc.v:197752.9-197752.17" + attribute \src "libresoc.v:200229.9-200229.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:990" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\fsm_state$next[1:0]$13834 2'01 + assign $1\fsm_state$next[1:0]$13820 2'01 attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\fsm_state$next[1:0]$13834 2'10 + assign $1\fsm_state$next[1:0]$13820 2'10 attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\fsm_state$next[1:0]$13834 2'11 + assign $1\fsm_state$next[1:0]$13820 2'11 attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\fsm_state$next[1:0]$13834 2'00 + assign $1\fsm_state$next[1:0]$13820 2'00 case - assign $1\fsm_state$next[1:0]$13834 \fsm_state + assign $1\fsm_state$next[1:0]$13820 \fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fsm_state$next[1:0]$13835 2'00 + assign $2\fsm_state$next[1:0]$13821 2'00 case - assign $2\fsm_state$next[1:0]$13835 $1\fsm_state$next[1:0]$13834 + assign $2\fsm_state$next[1:0]$13821 $1\fsm_state$next[1:0]$13820 end sync always - update \fsm_state$next $0\fsm_state$next[1:0]$13833 + update \fsm_state$next $0\fsm_state$next[1:0]$13819 end - attribute \src "libresoc.v:197779.3-197789.6" - process $proc$libresoc.v:197779$13836 + attribute \src "libresoc.v:200256.3-200270.6" + process $proc$libresoc.v:200256$13822 assign { } { } assign { } { } assign $0\new_dec[63:0] $1\new_dec[63:0] - attribute \src "libresoc.v:197780.5-197780.29" + attribute \src "libresoc.v:200257.5-200257.29" switch \initial - attribute \src "libresoc.v:197780.9-197780.17" + attribute \src "libresoc.v:200257.9-200257.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:990" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign $1\new_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\new_dec[63:0] \$264 [63:0] @@ -409011,51 +381562,63 @@ module \ti sync always update \new_dec $0\new_dec[63:0] end - attribute \src "libresoc.v:197790.3-197804.6" - process $proc$libresoc.v:197790$13837 + attribute \src "libresoc.v:200271.3-200293.6" + process $proc$libresoc.v:200271$13823 assign { } { } assign { } { } - assign $0\core_issue__addr$13[2:0]$13838 $1\core_issue__addr$13[2:0]$13839 - attribute \src "libresoc.v:197791.5-197791.29" + assign $0\core_issue__addr$13[2:0]$13824 $1\core_issue__addr$13[2:0]$13825 + attribute \src "libresoc.v:200272.5-200272.29" switch \initial - attribute \src "libresoc.v:197791.9-197791.17" + attribute \src "libresoc.v:200272.9-200272.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:990" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign $1\core_issue__addr$13[2:0]$13825 3'000 + attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\core_issue__addr$13[2:0]$13839 3'110 + assign $1\core_issue__addr$13[2:0]$13825 3'110 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign $1\core_issue__addr$13[2:0]$13825 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\core_issue__addr$13[2:0]$13839 3'111 + assign $1\core_issue__addr$13[2:0]$13825 3'111 case - assign $1\core_issue__addr$13[2:0]$13839 3'000 + assign $1\core_issue__addr$13[2:0]$13825 3'000 end sync always - update \core_issue__addr$13 $0\core_issue__addr$13[2:0]$13838 + update \core_issue__addr$13 $0\core_issue__addr$13[2:0]$13824 end - attribute \src "libresoc.v:197805.3-197819.6" - process $proc$libresoc.v:197805$13840 + attribute \src "libresoc.v:200294.3-200316.6" + process $proc$libresoc.v:200294$13826 assign { } { } assign { } { } assign $0\core_issue__wen[0:0] $1\core_issue__wen[0:0] - attribute \src "libresoc.v:197806.5-197806.29" + attribute \src "libresoc.v:200295.5-200295.29" switch \initial - attribute \src "libresoc.v:197806.9-197806.17" + attribute \src "libresoc.v:200295.9-200295.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:990" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign $1\core_issue__wen[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\core_issue__wen[0:0] 1'1 attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign $1\core_issue__wen[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } assign $1\core_issue__wen[0:0] 1'1 @@ -409065,24 +381628,30 @@ module \ti sync always update \core_issue__wen $0\core_issue__wen[0:0] end - attribute \src "libresoc.v:197820.3-197834.6" - process $proc$libresoc.v:197820$13841 + attribute \src "libresoc.v:200317.3-200339.6" + process $proc$libresoc.v:200317$13827 assign { } { } assign { } { } assign $0\core_issue__data_i[63:0] $1\core_issue__data_i[63:0] - attribute \src "libresoc.v:197821.5-197821.29" + attribute \src "libresoc.v:200318.5-200318.29" switch \initial - attribute \src "libresoc.v:197821.9-197821.17" + attribute \src "libresoc.v:200318.9-200318.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:990" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign $1\core_issue__data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } assign $1\core_issue__data_i[63:0] \new_dec attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign $1\core_issue__data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } assign $1\core_issue__data_i[63:0] \new_tb @@ -409092,53 +381661,65 @@ module \ti sync always update \core_issue__data_i $0\core_issue__data_i[63:0] end - attribute \src "libresoc.v:197835.3-197850.6" - process $proc$libresoc.v:197835$13842 + attribute \src "libresoc.v:200340.3-200359.6" + process $proc$libresoc.v:200340$13828 assign { } { } assign { } { } assign { } { } - assign $0\dec2_cur_dec$next[63:0]$13843 $2\dec2_cur_dec$next[63:0]$13845 - attribute \src "libresoc.v:197836.5-197836.29" + assign $0\dec2_cur_dec$next[63:0]$13829 $2\dec2_cur_dec$next[63:0]$13831 + attribute \src "libresoc.v:200341.5-200341.29" switch \initial - attribute \src "libresoc.v:197836.9-197836.17" + attribute \src "libresoc.v:200341.9-200341.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:990" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign $1\dec2_cur_dec$next[63:0]$13830 \dec2_cur_dec + attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec2_cur_dec$next[63:0]$13844 \new_dec + assign $1\dec2_cur_dec$next[63:0]$13830 \new_dec case - assign $1\dec2_cur_dec$next[63:0]$13844 \dec2_cur_dec + assign $1\dec2_cur_dec$next[63:0]$13830 \dec2_cur_dec end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dec2_cur_dec$next[63:0]$13845 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\dec2_cur_dec$next[63:0]$13831 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $2\dec2_cur_dec$next[63:0]$13845 $1\dec2_cur_dec$next[63:0]$13844 + assign $2\dec2_cur_dec$next[63:0]$13831 $1\dec2_cur_dec$next[63:0]$13830 end sync always - update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$13843 + update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$13829 end - attribute \src "libresoc.v:197851.3-197861.6" - process $proc$libresoc.v:197851$13846 + attribute \src "libresoc.v:200360.3-200382.6" + process $proc$libresoc.v:200360$13832 assign { } { } assign { } { } assign $0\new_tb[63:0] $1\new_tb[63:0] - attribute \src "libresoc.v:197852.5-197852.29" + attribute \src "libresoc.v:200361.5-200361.29" switch \initial - attribute \src "libresoc.v:197852.9-197852.17" + attribute \src "libresoc.v:200361.9-200361.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:989" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:990" switch \fsm_state attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign $1\new_tb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign $1\new_tb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 2'10 + assign $1\new_tb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } assign $1\new_tb[63:0] \$267 [63:0] @@ -409148,14 +381729,14 @@ module \ti sync always update \new_tb $0\new_tb[63:0] end - attribute \src "libresoc.v:197862.3-197870.6" - process $proc$libresoc.v:197862$13847 + attribute \src "libresoc.v:200383.3-200391.6" + process $proc$libresoc.v:200383$13833 assign { } { } assign { } { } - assign $0\dbg_dmi_we_i$next[0:0]$13848 $1\dbg_dmi_we_i$next[0:0]$13849 - attribute \src "libresoc.v:197863.5-197863.29" + assign $0\dbg_dmi_we_i$next[0:0]$13834 $1\dbg_dmi_we_i$next[0:0]$13835 + attribute \src "libresoc.v:200384.5-200384.29" switch \initial - attribute \src "libresoc.v:197863.9-197863.17" + attribute \src "libresoc.v:200384.9-200384.17" case 1'1 case end @@ -409164,21 +381745,21 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_dmi_we_i$next[0:0]$13849 1'0 + assign $1\dbg_dmi_we_i$next[0:0]$13835 1'0 case - assign $1\dbg_dmi_we_i$next[0:0]$13849 \jtag_dmi0__we_i + assign $1\dbg_dmi_we_i$next[0:0]$13835 \jtag_dmi0__we_i end sync always - update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$13848 + update \dbg_dmi_we_i$next $0\dbg_dmi_we_i$next[0:0]$13834 end - attribute \src "libresoc.v:197871.3-197879.6" - process $proc$libresoc.v:197871$13850 + attribute \src "libresoc.v:200392.3-200400.6" + process $proc$libresoc.v:200392$13836 assign { } { } assign { } { } - assign $0\pc_ok_delay$next[0:0]$13851 $1\pc_ok_delay$next[0:0]$13852 - attribute \src "libresoc.v:197872.5-197872.29" + assign $0\pc_ok_delay$next[0:0]$13837 $1\pc_ok_delay$next[0:0]$13838 + attribute \src "libresoc.v:200393.5-200393.29" switch \initial - attribute \src "libresoc.v:197872.9-197872.17" + attribute \src "libresoc.v:200393.9-200393.17" case 1'1 case end @@ -409187,22 +381768,22 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\pc_ok_delay$next[0:0]$13852 1'0 + assign $1\pc_ok_delay$next[0:0]$13838 1'0 case - assign $1\pc_ok_delay$next[0:0]$13852 \$38 + assign $1\pc_ok_delay$next[0:0]$13838 \$38 end sync always - update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$13851 + update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$13837 end - attribute \src "libresoc.v:197880.3-197895.6" - process $proc$libresoc.v:197880$13853 + attribute \src "libresoc.v:200401.3-200416.6" + process $proc$libresoc.v:200401$13839 assign { } { } assign { } { } assign { } { } assign $0\pc[63:0] $2\pc[63:0] - attribute \src "libresoc.v:197881.5-197881.29" + attribute \src "libresoc.v:200402.5-200402.29" switch \initial - attribute \src "libresoc.v:197881.9-197881.17" + attribute \src "libresoc.v:200402.9-200402.17" case 1'1 case end @@ -409227,14 +381808,14 @@ module \ti sync always update \pc $0\pc[63:0] end - attribute \src "libresoc.v:197896.3-197908.6" - process $proc$libresoc.v:197896$13854 + attribute \src "libresoc.v:200417.3-200429.6" + process $proc$libresoc.v:200417$13840 assign { } { } assign { } { } assign $0\core_cia__ren[2:0] $1\core_cia__ren[2:0] - attribute \src "libresoc.v:197897.5-197897.29" + attribute \src "libresoc.v:200418.5-200418.29" switch \initial - attribute \src "libresoc.v:197897.9-197897.17" + attribute \src "libresoc.v:200418.9-200418.17" case 1'1 case end @@ -409251,14 +381832,14 @@ module \ti sync always update \core_cia__ren $0\core_cia__ren[2:0] end - attribute \src "libresoc.v:197909.3-197917.6" - process $proc$libresoc.v:197909$13855 + attribute \src "libresoc.v:200430.3-200438.6" + process $proc$libresoc.v:200430$13841 assign { } { } assign { } { } - assign $0\svstate_ok_delay$next[0:0]$13856 $1\svstate_ok_delay$next[0:0]$13857 - attribute \src "libresoc.v:197910.5-197910.29" + assign $0\svstate_ok_delay$next[0:0]$13842 $1\svstate_ok_delay$next[0:0]$13843 + attribute \src "libresoc.v:200431.5-200431.29" switch \initial - attribute \src "libresoc.v:197910.9-197910.17" + attribute \src "libresoc.v:200431.9-200431.17" case 1'1 case end @@ -409267,22 +381848,22 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\svstate_ok_delay$next[0:0]$13857 1'0 + assign $1\svstate_ok_delay$next[0:0]$13843 1'0 case - assign $1\svstate_ok_delay$next[0:0]$13857 \$40 + assign $1\svstate_ok_delay$next[0:0]$13843 \$40 end sync always - update \svstate_ok_delay$next $0\svstate_ok_delay$next[0:0]$13856 + update \svstate_ok_delay$next $0\svstate_ok_delay$next[0:0]$13842 end - attribute \src "libresoc.v:197918.3-197933.6" - process $proc$libresoc.v:197918$13858 + attribute \src "libresoc.v:200439.3-200454.6" + process $proc$libresoc.v:200439$13844 assign { } { } assign { } { } assign { } { } assign $0\svstate[63:0] $2\svstate[63:0] - attribute \src "libresoc.v:197919.5-197919.29" + attribute \src "libresoc.v:200440.5-200440.29" switch \initial - attribute \src "libresoc.v:197919.9-197919.17" + attribute \src "libresoc.v:200440.9-200440.17" case 1'1 case end @@ -409307,14 +381888,14 @@ module \ti sync always update \svstate $0\svstate[63:0] end - attribute \src "libresoc.v:197934.3-197946.6" - process $proc$libresoc.v:197934$13859 + attribute \src "libresoc.v:200455.3-200467.6" + process $proc$libresoc.v:200455$13845 assign { } { } assign { } { } assign $0\core_sv__ren[2:0] $1\core_sv__ren[2:0] - attribute \src "libresoc.v:197935.5-197935.29" + attribute \src "libresoc.v:200456.5-200456.29" switch \initial - attribute \src "libresoc.v:197935.9-197935.17" + attribute \src "libresoc.v:200456.9-200456.17" case 1'1 case end @@ -409331,14 +381912,14 @@ module \ti sync always update \core_sv__ren $0\core_sv__ren[2:0] end - attribute \src "libresoc.v:197947.3-198014.6" - process $proc$libresoc.v:197947$13860 + attribute \src "libresoc.v:200468.3-200547.6" + process $proc$libresoc.v:200468$13846 assign { } { } assign { } { } assign $0\core_wen[2:0] $1\core_wen[2:0] - attribute \src "libresoc.v:197948.5-197948.29" + attribute \src "libresoc.v:200469.5-200469.29" switch \initial - attribute \src "libresoc.v:197948.9-197948.17" + attribute \src "libresoc.v:200469.9-200469.17" case 1'1 case end @@ -409390,22 +381971,31 @@ module \ti assign $4\core_wen[2:0] 3'000 end attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\core_wen[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign $1\core_wen[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\core_wen[2:0] 3'000 + attribute \src "libresoc.v:0.0-0.0" case 3'101 assign { } { } assign $1\core_wen[2:0] $6\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" switch \$58 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\core_wen[2:0] $7\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:620" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:621" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\core_wen[2:0] $8\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" switch { \$64 \$60 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -409424,7 +382014,7 @@ module \ti case assign { } { } assign $6\core_wen[2:0] $9\core_wen[2:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:663" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -409440,14 +382030,14 @@ module \ti sync always update \core_wen $0\core_wen[2:0] end - attribute \src "libresoc.v:198015.3-198082.6" - process $proc$libresoc.v:198015$13861 + attribute \src "libresoc.v:200548.3-200627.6" + process $proc$libresoc.v:200548$13847 assign { } { } assign { } { } assign $0\core_data_i[63:0] $1\core_data_i[63:0] - attribute \src "libresoc.v:198016.5-198016.29" + attribute \src "libresoc.v:200549.5-200549.29" switch \initial - attribute \src "libresoc.v:198016.9-198016.17" + attribute \src "libresoc.v:200549.9-200549.17" case 1'1 case end @@ -409499,22 +382089,31 @@ module \ti assign $4\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 end attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign $1\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "libresoc.v:0.0-0.0" case 3'101 assign { } { } assign $1\core_data_i[63:0] $6\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" switch \$80 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $6\core_data_i[63:0] $7\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:620" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:621" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $7\core_data_i[63:0] $8\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" switch { \$86 \$82 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -409533,7 +382132,7 @@ module \ti case assign { } { } assign $6\core_data_i[63:0] $9\core_data_i[63:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:663" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -409549,14 +382148,14 @@ module \ti sync always update \core_data_i $0\core_data_i[63:0] end - attribute \src "libresoc.v:198083.3-198098.6" - process $proc$libresoc.v:198083$13862 + attribute \src "libresoc.v:200628.3-200643.6" + process $proc$libresoc.v:200628$13848 assign { } { } assign { } { } assign $0\core_msr__ren[2:0] $1\core_msr__ren[2:0] - attribute \src "libresoc.v:198084.5-198084.29" + attribute \src "libresoc.v:200629.5-200629.29" switch \initial - attribute \src "libresoc.v:198084.9-198084.17" + attribute \src "libresoc.v:200629.9-200629.17" case 1'1 case end @@ -409581,14 +382180,14 @@ module \ti sync always update \core_msr__ren $0\core_msr__ren[2:0] end - attribute \src "libresoc.v:198099.3-198107.6" - process $proc$libresoc.v:198099$13863 + attribute \src "libresoc.v:200644.3-200652.6" + process $proc$libresoc.v:200644$13849 assign { } { } assign { } { } - assign $0\dbg_dmi_din$next[63:0]$13864 $1\dbg_dmi_din$next[63:0]$13865 - attribute \src "libresoc.v:198100.5-198100.29" + assign $0\dbg_dmi_din$next[63:0]$13850 $1\dbg_dmi_din$next[63:0]$13851 + attribute \src "libresoc.v:200645.5-200645.29" switch \initial - attribute \src "libresoc.v:198100.9-198100.17" + attribute \src "libresoc.v:200645.9-200645.17" case 1'1 case end @@ -409597,21 +382196,21 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dbg_dmi_din$next[63:0]$13865 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\dbg_dmi_din$next[63:0]$13851 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $1\dbg_dmi_din$next[63:0]$13865 \jtag_dmi0__din + assign $1\dbg_dmi_din$next[63:0]$13851 \jtag_dmi0__din end sync always - update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$13864 + update \dbg_dmi_din$next $0\dbg_dmi_din$next[63:0]$13850 end - attribute \src "libresoc.v:198108.3-198118.6" - process $proc$libresoc.v:198108$13866 + attribute \src "libresoc.v:200653.3-200663.6" + process $proc$libresoc.v:200653$13852 assign { } { } assign { } { } assign $0\fetch_pc_ready_o[0:0] $1\fetch_pc_ready_o[0:0] - attribute \src "libresoc.v:198109.5-198109.29" + attribute \src "libresoc.v:200654.5-200654.29" switch \initial - attribute \src "libresoc.v:198109.9-198109.17" + attribute \src "libresoc.v:200654.9-200654.17" case 1'1 case end @@ -409627,14 +382226,14 @@ module \ti sync always update \fetch_pc_ready_o $0\fetch_pc_ready_o[0:0] end - attribute \src "libresoc.v:198119.3-198134.6" - process $proc$libresoc.v:198119$13867 + attribute \src "libresoc.v:200664.3-200679.6" + process $proc$libresoc.v:200664$13853 assign { } { } assign { } { } assign $0\imem_a_pc_i[47:0] $1\imem_a_pc_i[47:0] - attribute \src "libresoc.v:198120.5-198120.29" + attribute \src "libresoc.v:200665.5-200665.29" switch \initial - attribute \src "libresoc.v:198120.9-198120.17" + attribute \src "libresoc.v:200665.9-200665.17" case 1'1 case end @@ -409659,14 +382258,14 @@ module \ti sync always update \imem_a_pc_i $0\imem_a_pc_i[47:0] end - attribute \src "libresoc.v:198135.3-198143.6" - process $proc$libresoc.v:198135$13868 + attribute \src "libresoc.v:200680.3-200688.6" + process $proc$libresoc.v:200680$13854 assign { } { } assign { } { } - assign $0\jtag_dmi0__ack_o$next[0:0]$13869 $1\jtag_dmi0__ack_o$next[0:0]$13870 - attribute \src "libresoc.v:198136.5-198136.29" + assign $0\jtag_dmi0__ack_o$next[0:0]$13855 $1\jtag_dmi0__ack_o$next[0:0]$13856 + attribute \src "libresoc.v:200681.5-200681.29" switch \initial - attribute \src "libresoc.v:198136.9-198136.17" + attribute \src "libresoc.v:200681.9-200681.17" case 1'1 case end @@ -409675,21 +382274,21 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_dmi0__ack_o$next[0:0]$13870 1'0 + assign $1\jtag_dmi0__ack_o$next[0:0]$13856 1'0 case - assign $1\jtag_dmi0__ack_o$next[0:0]$13870 \dbg_dmi_ack_o + assign $1\jtag_dmi0__ack_o$next[0:0]$13856 \dbg_dmi_ack_o end sync always - update \jtag_dmi0__ack_o$next $0\jtag_dmi0__ack_o$next[0:0]$13869 + update \jtag_dmi0__ack_o$next $0\jtag_dmi0__ack_o$next[0:0]$13855 end - attribute \src "libresoc.v:198144.3-198177.6" - process $proc$libresoc.v:198144$13871 + attribute \src "libresoc.v:200689.3-200722.6" + process $proc$libresoc.v:200689$13857 assign { } { } assign { } { } assign $0\imem_a_valid_i[0:0] $1\imem_a_valid_i[0:0] - attribute \src "libresoc.v:198145.5-198145.29" + attribute \src "libresoc.v:200690.5-200690.29" switch \initial - attribute \src "libresoc.v:198145.9-198145.17" + attribute \src "libresoc.v:200690.9-200690.17" case 1'1 case end @@ -409740,14 +382339,14 @@ module \ti sync always update \imem_a_valid_i $0\imem_a_valid_i[0:0] end - attribute \src "libresoc.v:198178.3-198211.6" - process $proc$libresoc.v:198178$13872 + attribute \src "libresoc.v:200723.3-200756.6" + process $proc$libresoc.v:200723$13858 assign { } { } assign { } { } assign $0\imem_f_valid_i[0:0] $1\imem_f_valid_i[0:0] - attribute \src "libresoc.v:198179.5-198179.29" + attribute \src "libresoc.v:200724.5-200724.29" switch \initial - attribute \src "libresoc.v:198179.9-198179.17" + attribute \src "libresoc.v:200724.9-200724.17" case 1'1 case end @@ -409798,15 +382397,15 @@ module \ti sync always update \imem_f_valid_i $0\imem_f_valid_i[0:0] end - attribute \src "libresoc.v:198212.3-198232.6" - process $proc$libresoc.v:198212$13873 + attribute \src "libresoc.v:200757.3-200777.6" + process $proc$libresoc.v:200757$13859 assign { } { } assign { } { } assign { } { } - assign $0\dec2_cur_pc$next[63:0]$13874 $3\dec2_cur_pc$next[63:0]$13877 - attribute \src "libresoc.v:198213.5-198213.29" + assign $0\dec2_cur_pc$next[63:0]$13860 $3\dec2_cur_pc$next[63:0]$13863 + attribute \src "libresoc.v:200758.5-200758.29" switch \initial - attribute \src "libresoc.v:198213.9-198213.17" + attribute \src "libresoc.v:200758.9-200758.17" case 1'1 case end @@ -409815,33 +382414,33 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\dec2_cur_pc$next[63:0]$13875 $2\dec2_cur_pc$next[63:0]$13876 + assign $1\dec2_cur_pc$next[63:0]$13861 $2\dec2_cur_pc$next[63:0]$13862 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dec2_cur_pc$next[63:0]$13876 \pc + assign $2\dec2_cur_pc$next[63:0]$13862 \pc case - assign $2\dec2_cur_pc$next[63:0]$13876 \dec2_cur_pc + assign $2\dec2_cur_pc$next[63:0]$13862 \dec2_cur_pc end case - assign $1\dec2_cur_pc$next[63:0]$13875 \dec2_cur_pc + assign $1\dec2_cur_pc$next[63:0]$13861 \dec2_cur_pc end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dec2_cur_pc$next[63:0]$13877 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dec2_cur_pc$next[63:0]$13863 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\dec2_cur_pc$next[63:0]$13877 $1\dec2_cur_pc$next[63:0]$13875 + assign $3\dec2_cur_pc$next[63:0]$13863 $1\dec2_cur_pc$next[63:0]$13861 end sync always - update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$13874 + update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$13860 end - attribute \src "libresoc.v:198233.3-198271.6" - process $proc$libresoc.v:198233$13878 + attribute \src "libresoc.v:200778.3-200816.6" + process $proc$libresoc.v:200778$13864 assign { } { } assign { } { } assign { } { } @@ -409866,15 +382465,15 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $0\cur_cur_dststep$next[6:0]$13879 $4\cur_cur_dststep$next[6:0]$13903 - assign $0\cur_cur_maxvl$next[6:0]$13880 $4\cur_cur_maxvl$next[6:0]$13904 - assign $0\cur_cur_srcstep$next[6:0]$13881 $4\cur_cur_srcstep$next[6:0]$13905 - assign $0\cur_cur_subvl$next[1:0]$13882 $4\cur_cur_subvl$next[1:0]$13906 - assign $0\cur_cur_svstep$next[1:0]$13883 $4\cur_cur_svstep$next[1:0]$13907 - assign $0\cur_cur_vl$next[6:0]$13884 $4\cur_cur_vl$next[6:0]$13908 - attribute \src "libresoc.v:198234.5-198234.29" + assign $0\cur_cur_dststep$next[6:0]$13865 $4\cur_cur_dststep$next[6:0]$13889 + assign $0\cur_cur_maxvl$next[6:0]$13866 $4\cur_cur_maxvl$next[6:0]$13890 + assign $0\cur_cur_srcstep$next[6:0]$13867 $4\cur_cur_srcstep$next[6:0]$13891 + assign $0\cur_cur_subvl$next[1:0]$13868 $4\cur_cur_subvl$next[1:0]$13892 + assign $0\cur_cur_svstep$next[1:0]$13869 $4\cur_cur_svstep$next[1:0]$13893 + assign $0\cur_cur_vl$next[6:0]$13870 $4\cur_cur_vl$next[6:0]$13894 + attribute \src "libresoc.v:200779.5-200779.29" switch \initial - attribute \src "libresoc.v:198234.9-198234.17" + attribute \src "libresoc.v:200779.9-200779.17" case 1'1 case end @@ -409888,12 +382487,12 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $1\cur_cur_dststep$next[6:0]$13885 $2\cur_cur_dststep$next[6:0]$13891 - assign $1\cur_cur_maxvl$next[6:0]$13886 $2\cur_cur_maxvl$next[6:0]$13892 - assign $1\cur_cur_srcstep$next[6:0]$13887 $2\cur_cur_srcstep$next[6:0]$13893 - assign $1\cur_cur_subvl$next[1:0]$13888 $2\cur_cur_subvl$next[1:0]$13894 - assign $1\cur_cur_svstep$next[1:0]$13889 $2\cur_cur_svstep$next[1:0]$13895 - assign $1\cur_cur_vl$next[6:0]$13890 $2\cur_cur_vl$next[6:0]$13896 + assign $1\cur_cur_dststep$next[6:0]$13871 $2\cur_cur_dststep$next[6:0]$13877 + assign $1\cur_cur_maxvl$next[6:0]$13872 $2\cur_cur_maxvl$next[6:0]$13878 + assign $1\cur_cur_srcstep$next[6:0]$13873 $2\cur_cur_srcstep$next[6:0]$13879 + assign $1\cur_cur_subvl$next[1:0]$13874 $2\cur_cur_subvl$next[1:0]$13880 + assign $1\cur_cur_svstep$next[1:0]$13875 $2\cur_cur_svstep$next[1:0]$13881 + assign $1\cur_cur_vl$next[6:0]$13876 $2\cur_cur_vl$next[6:0]$13882 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" @@ -409904,24 +382503,24 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $2\cur_cur_maxvl$next[6:0]$13892 $2\cur_cur_vl$next[6:0]$13896 $2\cur_cur_srcstep$next[6:0]$13893 $2\cur_cur_dststep$next[6:0]$13891 $2\cur_cur_subvl$next[1:0]$13894 $2\cur_cur_svstep$next[1:0]$13895 } \svstate [31:0] + assign { $2\cur_cur_maxvl$next[6:0]$13878 $2\cur_cur_vl$next[6:0]$13882 $2\cur_cur_srcstep$next[6:0]$13879 $2\cur_cur_dststep$next[6:0]$13877 $2\cur_cur_subvl$next[1:0]$13880 $2\cur_cur_svstep$next[1:0]$13881 } \svstate [31:0] case - assign $2\cur_cur_dststep$next[6:0]$13891 \cur_cur_dststep - assign $2\cur_cur_maxvl$next[6:0]$13892 \cur_cur_maxvl - assign $2\cur_cur_srcstep$next[6:0]$13893 \cur_cur_srcstep - assign $2\cur_cur_subvl$next[1:0]$13894 \cur_cur_subvl - assign $2\cur_cur_svstep$next[1:0]$13895 \cur_cur_svstep - assign $2\cur_cur_vl$next[6:0]$13896 \cur_cur_vl + assign $2\cur_cur_dststep$next[6:0]$13877 \cur_cur_dststep + assign $2\cur_cur_maxvl$next[6:0]$13878 \cur_cur_maxvl + assign $2\cur_cur_srcstep$next[6:0]$13879 \cur_cur_srcstep + assign $2\cur_cur_subvl$next[1:0]$13880 \cur_cur_subvl + assign $2\cur_cur_svstep$next[1:0]$13881 \cur_cur_svstep + assign $2\cur_cur_vl$next[6:0]$13882 \cur_cur_vl end case - assign $1\cur_cur_dststep$next[6:0]$13885 \cur_cur_dststep - assign $1\cur_cur_maxvl$next[6:0]$13886 \cur_cur_maxvl - assign $1\cur_cur_srcstep$next[6:0]$13887 \cur_cur_srcstep - assign $1\cur_cur_subvl$next[1:0]$13888 \cur_cur_subvl - assign $1\cur_cur_svstep$next[1:0]$13889 \cur_cur_svstep - assign $1\cur_cur_vl$next[6:0]$13890 \cur_cur_vl + assign $1\cur_cur_dststep$next[6:0]$13871 \cur_cur_dststep + assign $1\cur_cur_maxvl$next[6:0]$13872 \cur_cur_maxvl + assign $1\cur_cur_srcstep$next[6:0]$13873 \cur_cur_srcstep + assign $1\cur_cur_subvl$next[1:0]$13874 \cur_cur_subvl + assign $1\cur_cur_svstep$next[1:0]$13875 \cur_cur_svstep + assign $1\cur_cur_vl$next[6:0]$13876 \cur_cur_vl end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:683" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:684" switch \update_svstate attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -409931,14 +382530,14 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $3\cur_cur_maxvl$next[6:0]$13898 $3\cur_cur_vl$next[6:0]$13902 $3\cur_cur_srcstep$next[6:0]$13899 $3\cur_cur_dststep$next[6:0]$13897 $3\cur_cur_subvl$next[1:0]$13900 $3\cur_cur_svstep$next[1:0]$13901 } { \new_svstate_maxvl \new_svstate_vl \new_svstate_srcstep \new_svstate_dststep \new_svstate_subvl \new_svstate_svstep } + assign { $3\cur_cur_maxvl$next[6:0]$13884 $3\cur_cur_vl$next[6:0]$13888 $3\cur_cur_srcstep$next[6:0]$13885 $3\cur_cur_dststep$next[6:0]$13883 $3\cur_cur_subvl$next[1:0]$13886 $3\cur_cur_svstep$next[1:0]$13887 } { \new_svstate_maxvl \new_svstate_vl \new_svstate_srcstep \new_svstate_dststep \new_svstate_subvl \new_svstate_svstep } case - assign $3\cur_cur_dststep$next[6:0]$13897 $1\cur_cur_dststep$next[6:0]$13885 - assign $3\cur_cur_maxvl$next[6:0]$13898 $1\cur_cur_maxvl$next[6:0]$13886 - assign $3\cur_cur_srcstep$next[6:0]$13899 $1\cur_cur_srcstep$next[6:0]$13887 - assign $3\cur_cur_subvl$next[1:0]$13900 $1\cur_cur_subvl$next[1:0]$13888 - assign $3\cur_cur_svstep$next[1:0]$13901 $1\cur_cur_svstep$next[1:0]$13889 - assign $3\cur_cur_vl$next[6:0]$13902 $1\cur_cur_vl$next[6:0]$13890 + assign $3\cur_cur_dststep$next[6:0]$13883 $1\cur_cur_dststep$next[6:0]$13871 + assign $3\cur_cur_maxvl$next[6:0]$13884 $1\cur_cur_maxvl$next[6:0]$13872 + assign $3\cur_cur_srcstep$next[6:0]$13885 $1\cur_cur_srcstep$next[6:0]$13873 + assign $3\cur_cur_subvl$next[1:0]$13886 $1\cur_cur_subvl$next[1:0]$13874 + assign $3\cur_cur_svstep$next[1:0]$13887 $1\cur_cur_svstep$next[1:0]$13875 + assign $3\cur_cur_vl$next[6:0]$13888 $1\cur_cur_vl$next[6:0]$13876 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -409950,37 +382549,37 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $4\cur_cur_svstep$next[1:0]$13907 2'00 - assign $4\cur_cur_subvl$next[1:0]$13906 2'00 - assign $4\cur_cur_dststep$next[6:0]$13903 7'0000000 - assign $4\cur_cur_srcstep$next[6:0]$13905 7'0000000 - assign $4\cur_cur_vl$next[6:0]$13908 7'0000000 - assign $4\cur_cur_maxvl$next[6:0]$13904 7'0000000 + assign $4\cur_cur_svstep$next[1:0]$13893 2'00 + assign $4\cur_cur_subvl$next[1:0]$13892 2'00 + assign $4\cur_cur_dststep$next[6:0]$13889 7'0000000 + assign $4\cur_cur_srcstep$next[6:0]$13891 7'0000000 + assign $4\cur_cur_vl$next[6:0]$13894 7'0000000 + assign $4\cur_cur_maxvl$next[6:0]$13890 7'0000000 case - assign $4\cur_cur_dststep$next[6:0]$13903 $3\cur_cur_dststep$next[6:0]$13897 - assign $4\cur_cur_maxvl$next[6:0]$13904 $3\cur_cur_maxvl$next[6:0]$13898 - assign $4\cur_cur_srcstep$next[6:0]$13905 $3\cur_cur_srcstep$next[6:0]$13899 - assign $4\cur_cur_subvl$next[1:0]$13906 $3\cur_cur_subvl$next[1:0]$13900 - assign $4\cur_cur_svstep$next[1:0]$13907 $3\cur_cur_svstep$next[1:0]$13901 - assign $4\cur_cur_vl$next[6:0]$13908 $3\cur_cur_vl$next[6:0]$13902 + assign $4\cur_cur_dststep$next[6:0]$13889 $3\cur_cur_dststep$next[6:0]$13883 + assign $4\cur_cur_maxvl$next[6:0]$13890 $3\cur_cur_maxvl$next[6:0]$13884 + assign $4\cur_cur_srcstep$next[6:0]$13891 $3\cur_cur_srcstep$next[6:0]$13885 + assign $4\cur_cur_subvl$next[1:0]$13892 $3\cur_cur_subvl$next[1:0]$13886 + assign $4\cur_cur_svstep$next[1:0]$13893 $3\cur_cur_svstep$next[1:0]$13887 + assign $4\cur_cur_vl$next[6:0]$13894 $3\cur_cur_vl$next[6:0]$13888 end sync always - update \cur_cur_dststep$next $0\cur_cur_dststep$next[6:0]$13879 - update \cur_cur_maxvl$next $0\cur_cur_maxvl$next[6:0]$13880 - update \cur_cur_srcstep$next $0\cur_cur_srcstep$next[6:0]$13881 - update \cur_cur_subvl$next $0\cur_cur_subvl$next[1:0]$13882 - update \cur_cur_svstep$next $0\cur_cur_svstep$next[1:0]$13883 - update \cur_cur_vl$next $0\cur_cur_vl$next[6:0]$13884 + update \cur_cur_dststep$next $0\cur_cur_dststep$next[6:0]$13865 + update \cur_cur_maxvl$next $0\cur_cur_maxvl$next[6:0]$13866 + update \cur_cur_srcstep$next $0\cur_cur_srcstep$next[6:0]$13867 + update \cur_cur_subvl$next $0\cur_cur_subvl$next[1:0]$13868 + update \cur_cur_svstep$next $0\cur_cur_svstep$next[1:0]$13869 + update \cur_cur_vl$next $0\cur_cur_vl$next[6:0]$13870 end - attribute \src "libresoc.v:198272.3-198301.6" - process $proc$libresoc.v:198272$13909 + attribute \src "libresoc.v:200817.3-200846.6" + process $proc$libresoc.v:200817$13895 assign { } { } assign { } { } assign { } { } - assign $0\msr_read$next[0:0]$13910 $4\msr_read$next[0:0]$13914 - attribute \src "libresoc.v:198273.5-198273.29" + assign $0\msr_read$next[0:0]$13896 $4\msr_read$next[0:0]$13900 + attribute \src "libresoc.v:200818.5-200818.29" switch \initial - attribute \src "libresoc.v:198273.9-198273.17" + attribute \src "libresoc.v:200818.9-200818.17" case 1'1 case end @@ -409989,52 +382588,52 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\msr_read$next[0:0]$13911 $2\msr_read$next[0:0]$13912 + assign $1\msr_read$next[0:0]$13897 $2\msr_read$next[0:0]$13898 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\msr_read$next[0:0]$13912 1'0 + assign $2\msr_read$next[0:0]$13898 1'0 case - assign $2\msr_read$next[0:0]$13912 \msr_read + assign $2\msr_read$next[0:0]$13898 \msr_read end attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\msr_read$next[0:0]$13911 $3\msr_read$next[0:0]$13913 + assign $1\msr_read$next[0:0]$13897 $3\msr_read$next[0:0]$13899 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:302" switch \$88 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\msr_read$next[0:0]$13913 1'1 + assign $3\msr_read$next[0:0]$13899 1'1 case - assign $3\msr_read$next[0:0]$13913 \msr_read + assign $3\msr_read$next[0:0]$13899 \msr_read end case - assign $1\msr_read$next[0:0]$13911 \msr_read + assign $1\msr_read$next[0:0]$13897 \msr_read end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\msr_read$next[0:0]$13914 1'1 + assign $4\msr_read$next[0:0]$13900 1'1 case - assign $4\msr_read$next[0:0]$13914 $1\msr_read$next[0:0]$13911 + assign $4\msr_read$next[0:0]$13900 $1\msr_read$next[0:0]$13897 end sync always - update \msr_read$next $0\msr_read$next[0:0]$13910 + update \msr_read$next $0\msr_read$next[0:0]$13896 end - attribute \src "libresoc.v:198302.3-198310.6" - process $proc$libresoc.v:198302$13915 + attribute \src "libresoc.v:200847.3-200855.6" + process $proc$libresoc.v:200847$13901 assign { } { } assign { } { } - assign $0\jtag_dmi0__dout$next[63:0]$13916 $1\jtag_dmi0__dout$next[63:0]$13917 - attribute \src "libresoc.v:198303.5-198303.29" + assign $0\jtag_dmi0__dout$next[63:0]$13902 $1\jtag_dmi0__dout$next[63:0]$13903 + attribute \src "libresoc.v:200848.5-200848.29" switch \initial - attribute \src "libresoc.v:198303.9-198303.17" + attribute \src "libresoc.v:200848.9-200848.17" case 1'1 case end @@ -410043,22 +382642,22 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\jtag_dmi0__dout$next[63:0]$13917 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\jtag_dmi0__dout$next[63:0]$13903 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $1\jtag_dmi0__dout$next[63:0]$13917 \dbg_dmi_dout + assign $1\jtag_dmi0__dout$next[63:0]$13903 \dbg_dmi_dout end sync always - update \jtag_dmi0__dout$next $0\jtag_dmi0__dout$next[63:0]$13916 + update \jtag_dmi0__dout$next $0\jtag_dmi0__dout$next[63:0]$13902 end - attribute \src "libresoc.v:198311.3-198364.6" - process $proc$libresoc.v:198311$13918 + attribute \src "libresoc.v:200856.3-200909.6" + process $proc$libresoc.v:200856$13904 assign { } { } assign { } { } assign { } { } - assign $0\fetch_fsm_state$next[1:0]$13919 $6\fetch_fsm_state$next[1:0]$13925 - attribute \src "libresoc.v:198312.5-198312.29" + assign $0\fetch_fsm_state$next[1:0]$13905 $6\fetch_fsm_state$next[1:0]$13911 + attribute \src "libresoc.v:200857.5-200857.29" switch \initial - attribute \src "libresoc.v:198312.9-198312.17" + attribute \src "libresoc.v:200857.9-200857.17" case 1'1 case end @@ -410067,208 +382666,226 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 2'00 assign { } { } - assign $1\fetch_fsm_state$next[1:0]$13920 $2\fetch_fsm_state$next[1:0]$13921 + assign $1\fetch_fsm_state$next[1:0]$13906 $2\fetch_fsm_state$next[1:0]$13907 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:282" switch \fetch_pc_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\fetch_fsm_state$next[1:0]$13921 2'01 + assign $2\fetch_fsm_state$next[1:0]$13907 2'01 case - assign $2\fetch_fsm_state$next[1:0]$13921 \fetch_fsm_state + assign $2\fetch_fsm_state$next[1:0]$13907 \fetch_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\fetch_fsm_state$next[1:0]$13920 $3\fetch_fsm_state$next[1:0]$13922 + assign $1\fetch_fsm_state$next[1:0]$13906 $3\fetch_fsm_state$next[1:0]$13908 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:305" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $3\fetch_fsm_state$next[1:0]$13922 \fetch_fsm_state + assign $3\fetch_fsm_state$next[1:0]$13908 \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $3\fetch_fsm_state$next[1:0]$13922 2'10 + assign $3\fetch_fsm_state$next[1:0]$13908 2'10 end attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\fetch_fsm_state$next[1:0]$13920 $4\fetch_fsm_state$next[1:0]$13923 + assign $1\fetch_fsm_state$next[1:0]$13906 $4\fetch_fsm_state$next[1:0]$13909 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:343" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $4\fetch_fsm_state$next[1:0]$13923 \fetch_fsm_state + assign $4\fetch_fsm_state$next[1:0]$13909 \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $4\fetch_fsm_state$next[1:0]$13923 2'10 + assign $4\fetch_fsm_state$next[1:0]$13909 2'10 end attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } - assign $1\fetch_fsm_state$next[1:0]$13920 $5\fetch_fsm_state$next[1:0]$13924 + assign $1\fetch_fsm_state$next[1:0]$13906 $5\fetch_fsm_state$next[1:0]$13910 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:371" switch \fetch_insn_ready_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\fetch_fsm_state$next[1:0]$13924 2'00 + assign $5\fetch_fsm_state$next[1:0]$13910 2'00 case - assign $5\fetch_fsm_state$next[1:0]$13924 \fetch_fsm_state + assign $5\fetch_fsm_state$next[1:0]$13910 \fetch_fsm_state end case - assign $1\fetch_fsm_state$next[1:0]$13920 \fetch_fsm_state + assign $1\fetch_fsm_state$next[1:0]$13906 \fetch_fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\fetch_fsm_state$next[1:0]$13925 2'00 + assign $6\fetch_fsm_state$next[1:0]$13911 2'00 case - assign $6\fetch_fsm_state$next[1:0]$13925 $1\fetch_fsm_state$next[1:0]$13920 + assign $6\fetch_fsm_state$next[1:0]$13911 $1\fetch_fsm_state$next[1:0]$13906 end sync always - update \fetch_fsm_state$next $0\fetch_fsm_state$next[1:0]$13919 + update \fetch_fsm_state$next $0\fetch_fsm_state$next[1:0]$13905 end - attribute \src "libresoc.v:198365.3-198385.6" - process $proc$libresoc.v:198365$13926 + attribute \src "libresoc.v:200910.3-200934.6" + process $proc$libresoc.v:200910$13912 assign { } { } assign { } { } assign { } { } - assign $0\dec2_cur_msr$next[63:0]$13927 $3\dec2_cur_msr$next[63:0]$13930 - attribute \src "libresoc.v:198366.5-198366.29" + assign $0\dec2_cur_msr$next[63:0]$13913 $3\dec2_cur_msr$next[63:0]$13916 + attribute \src "libresoc.v:200911.5-200911.29" switch \initial - attribute \src "libresoc.v:198366.9-198366.17" + attribute \src "libresoc.v:200911.9-200911.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign $1\dec2_cur_msr$next[63:0]$13914 \dec2_cur_msr + attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec2_cur_msr$next[63:0]$13928 $2\dec2_cur_msr$next[63:0]$13929 + assign $1\dec2_cur_msr$next[63:0]$13914 $2\dec2_cur_msr$next[63:0]$13915 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:302" switch \$90 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\dec2_cur_msr$next[63:0]$13929 \core_msr__data_o + assign $2\dec2_cur_msr$next[63:0]$13915 \core_msr__data_o case - assign $2\dec2_cur_msr$next[63:0]$13929 \dec2_cur_msr + assign $2\dec2_cur_msr$next[63:0]$13915 \dec2_cur_msr end case - assign $1\dec2_cur_msr$next[63:0]$13928 \dec2_cur_msr + assign $1\dec2_cur_msr$next[63:0]$13914 \dec2_cur_msr end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\dec2_cur_msr$next[63:0]$13930 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\dec2_cur_msr$next[63:0]$13916 64'0000000000000000000000000000000000000000000000000000000000000000 case - assign $3\dec2_cur_msr$next[63:0]$13930 $1\dec2_cur_msr$next[63:0]$13928 + assign $3\dec2_cur_msr$next[63:0]$13916 $1\dec2_cur_msr$next[63:0]$13914 end sync always - update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$13927 + update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$13913 end - attribute \src "libresoc.v:198386.3-198404.6" - process $proc$libresoc.v:198386$13931 + attribute \src "libresoc.v:200935.3-200957.6" + process $proc$libresoc.v:200935$13917 assign { } { } assign { } { } - assign $0\nia$next[63:0]$13932 $1\nia$next[63:0]$13933 - attribute \src "libresoc.v:198387.5-198387.29" + assign $0\nia$next[63:0]$13918 $1\nia$next[63:0]$13919 + attribute \src "libresoc.v:200936.5-200936.29" switch \initial - attribute \src "libresoc.v:198387.9-198387.17" + attribute \src "libresoc.v:200936.9-200936.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign $1\nia$next[63:0]$13919 \nia + attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\nia$next[63:0]$13933 $2\nia$next[63:0]$13934 + assign $1\nia$next[63:0]$13919 $2\nia$next[63:0]$13920 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:305" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $2\nia$next[63:0]$13934 \nia + assign $2\nia$next[63:0]$13920 \nia attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\nia$next[63:0]$13934 \$92 [63:0] + assign $2\nia$next[63:0]$13920 \$92 [63:0] end case - assign $1\nia$next[63:0]$13933 \nia + assign $1\nia$next[63:0]$13919 \nia end sync always - update \nia$next $0\nia$next[63:0]$13932 + update \nia$next $0\nia$next[63:0]$13918 end - attribute \src "libresoc.v:198405.3-198435.6" - process $proc$libresoc.v:198405$13935 + attribute \src "libresoc.v:200958.3-200992.6" + process $proc$libresoc.v:200958$13921 assign { } { } assign { } { } - assign $0\dec2_raw_opcode_in$next[31:0]$13936 $1\dec2_raw_opcode_in$next[31:0]$13937 - attribute \src "libresoc.v:198406.5-198406.29" + assign $0\dec2_raw_opcode_in$next[31:0]$13922 $1\dec2_raw_opcode_in$next[31:0]$13923 + attribute \src "libresoc.v:200959.5-200959.29" switch \initial - attribute \src "libresoc.v:198406.9-198406.17" + attribute \src "libresoc.v:200959.9-200959.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign $1\dec2_raw_opcode_in$next[31:0]$13923 \dec2_raw_opcode_in + attribute \src "libresoc.v:0.0-0.0" case 2'01 assign { } { } - assign $1\dec2_raw_opcode_in$next[31:0]$13937 $2\dec2_raw_opcode_in$next[31:0]$13938 + assign $1\dec2_raw_opcode_in$next[31:0]$13923 $2\dec2_raw_opcode_in$next[31:0]$13924 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:305" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $2\dec2_raw_opcode_in$next[31:0]$13938 \dec2_raw_opcode_in + assign $2\dec2_raw_opcode_in$next[31:0]$13924 \dec2_raw_opcode_in attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\dec2_raw_opcode_in$next[31:0]$13938 \$95 + assign $2\dec2_raw_opcode_in$next[31:0]$13924 \$95 end attribute \src "libresoc.v:0.0-0.0" case 2'11 assign { } { } - assign $1\dec2_raw_opcode_in$next[31:0]$13937 $3\dec2_raw_opcode_in$next[31:0]$13939 + assign $1\dec2_raw_opcode_in$next[31:0]$13923 $3\dec2_raw_opcode_in$next[31:0]$13925 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:343" switch \imem_f_busy_o attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $3\dec2_raw_opcode_in$next[31:0]$13939 \dec2_raw_opcode_in + assign $3\dec2_raw_opcode_in$next[31:0]$13925 \dec2_raw_opcode_in attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $3\dec2_raw_opcode_in$next[31:0]$13939 \$99 + assign $3\dec2_raw_opcode_in$next[31:0]$13925 \$99 end case - assign $1\dec2_raw_opcode_in$next[31:0]$13937 \dec2_raw_opcode_in + assign $1\dec2_raw_opcode_in$next[31:0]$13923 \dec2_raw_opcode_in end sync always - update \dec2_raw_opcode_in$next $0\dec2_raw_opcode_in$next[31:0]$13936 + update \dec2_raw_opcode_in$next $0\dec2_raw_opcode_in$next[31:0]$13922 end - attribute \src "libresoc.v:198436.3-198446.6" - process $proc$libresoc.v:198436$13940 + attribute \src "libresoc.v:200993.3-201015.6" + process $proc$libresoc.v:200993$13926 assign { } { } assign { } { } assign $0\fetch_insn_valid_o[0:0] $1\fetch_insn_valid_o[0:0] - attribute \src "libresoc.v:198437.5-198437.29" + attribute \src "libresoc.v:200994.5-200994.29" switch \initial - attribute \src "libresoc.v:198437.9-198437.17" + attribute \src "libresoc.v:200994.9-200994.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:277" switch \fetch_fsm_state attribute \src "libresoc.v:0.0-0.0" + case 2'00 + assign $1\fetch_insn_valid_o[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'01 + assign $1\fetch_insn_valid_o[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 2'11 + assign $1\fetch_insn_valid_o[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 2'10 assign { } { } assign $1\fetch_insn_valid_o[0:0] 1'1 @@ -410278,8 +382895,8 @@ module \ti sync always update \fetch_insn_valid_o $0\fetch_insn_valid_o[0:0] end - attribute \src "libresoc.v:198447.3-198506.6" - process $proc$libresoc.v:198447$13941 + attribute \src "libresoc.v:201016.3-201091.6" + process $proc$libresoc.v:201016$13927 assign { } { } assign { } { } assign { } { } @@ -410293,9 +382910,9 @@ module \ti assign $0\new_svstate_subvl[1:0] $1\new_svstate_subvl[1:0] assign $0\new_svstate_svstep[1:0] $1\new_svstate_svstep[1:0] assign $0\new_svstate_vl[6:0] $1\new_svstate_vl[6:0] - attribute \src "libresoc.v:198448.5-198448.29" + attribute \src "libresoc.v:201017.5-201017.29" switch \initial - attribute \src "libresoc.v:198448.9-198448.17" + attribute \src "libresoc.v:201017.9-201017.17" case 1'1 case end @@ -410360,6 +382977,38 @@ module \ti end end attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\new_svstate_dststep[6:0] \cur_cur_dststep + assign $1\new_svstate_maxvl[6:0] \cur_cur_maxvl + assign $1\new_svstate_srcstep[6:0] \cur_cur_srcstep + assign $1\new_svstate_subvl[1:0] \cur_cur_subvl + assign $1\new_svstate_svstep[1:0] \cur_cur_svstep + assign $1\new_svstate_vl[6:0] \cur_cur_vl + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\new_svstate_dststep[6:0] \cur_cur_dststep + assign $1\new_svstate_maxvl[6:0] \cur_cur_maxvl + assign $1\new_svstate_srcstep[6:0] \cur_cur_srcstep + assign $1\new_svstate_subvl[1:0] \cur_cur_subvl + assign $1\new_svstate_svstep[1:0] \cur_cur_svstep + assign $1\new_svstate_vl[6:0] \cur_cur_vl + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign $1\new_svstate_dststep[6:0] \cur_cur_dststep + assign $1\new_svstate_maxvl[6:0] \cur_cur_maxvl + assign $1\new_svstate_srcstep[6:0] \cur_cur_srcstep + assign $1\new_svstate_subvl[1:0] \cur_cur_subvl + assign $1\new_svstate_svstep[1:0] \cur_cur_svstep + assign $1\new_svstate_vl[6:0] \cur_cur_vl + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\new_svstate_dststep[6:0] \cur_cur_dststep + assign $1\new_svstate_maxvl[6:0] \cur_cur_maxvl + assign $1\new_svstate_srcstep[6:0] \cur_cur_srcstep + assign $1\new_svstate_subvl[1:0] \cur_cur_subvl + assign $1\new_svstate_svstep[1:0] \cur_cur_svstep + assign $1\new_svstate_vl[6:0] \cur_cur_vl + attribute \src "libresoc.v:0.0-0.0" case 3'101 assign { } { } assign { } { } @@ -410373,7 +383022,7 @@ module \ti assign $1\new_svstate_subvl[1:0] $4\new_svstate_subvl[1:0] assign $1\new_svstate_svstep[1:0] $4\new_svstate_svstep[1:0] assign $1\new_svstate_vl[6:0] $4\new_svstate_vl[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" switch \$116 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410385,7 +383034,7 @@ module \ti assign $4\new_svstate_vl[6:0] \cur_cur_vl assign $4\new_svstate_dststep[6:0] $5\new_svstate_dststep[6:0] assign $4\new_svstate_srcstep[6:0] $5\new_svstate_srcstep[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:620" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:621" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410393,7 +383042,7 @@ module \ti assign { } { } assign $5\new_svstate_dststep[6:0] $6\new_svstate_dststep[6:0] assign $5\new_svstate_srcstep[6:0] $6\new_svstate_srcstep[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" switch { \$122 \$118 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -410428,7 +383077,7 @@ module \ti assign $4\new_svstate_subvl[1:0] $5\new_svstate_subvl[1:0] assign $4\new_svstate_svstep[1:0] $5\new_svstate_svstep[1:0] assign $4\new_svstate_vl[6:0] $5\new_svstate_vl[6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:666" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:667" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410464,14 +383113,14 @@ module \ti update \new_svstate_svstep $0\new_svstate_svstep[1:0] update \new_svstate_vl $0\new_svstate_vl[6:0] end - attribute \src "libresoc.v:198507.3-198522.6" - process $proc$libresoc.v:198507$13942 + attribute \src "libresoc.v:201092.3-201107.6" + process $proc$libresoc.v:201092$13928 assign { } { } assign { } { } assign $0\fetch_pc_valid_i[0:0] $1\fetch_pc_valid_i[0:0] - attribute \src "libresoc.v:198508.5-198508.29" + attribute \src "libresoc.v:201093.5-201093.29" switch \initial - attribute \src "libresoc.v:198508.9-198508.17" + attribute \src "libresoc.v:201093.9-201093.17" case 1'1 case end @@ -410496,15 +383145,15 @@ module \ti sync always update \fetch_pc_valid_i $0\fetch_pc_valid_i[0:0] end - attribute \src "libresoc.v:198523.3-198621.6" - process $proc$libresoc.v:198523$13943 + attribute \src "libresoc.v:201108.3-201206.6" + process $proc$libresoc.v:201108$13929 assign { } { } assign { } { } assign { } { } - assign $0\issue_fsm_state$next[2:0]$13944 $12\issue_fsm_state$next[2:0]$13956 - attribute \src "libresoc.v:198524.5-198524.29" + assign $0\issue_fsm_state$next[2:0]$13930 $12\issue_fsm_state$next[2:0]$13942 + attribute \src "libresoc.v:201109.5-201109.29" switch \initial - attribute \src "libresoc.v:198524.9-198524.17" + attribute \src "libresoc.v:201109.9-201109.17" case 1'1 case end @@ -410513,152 +383162,152 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\issue_fsm_state$next[2:0]$13945 $2\issue_fsm_state$next[2:0]$13946 + assign $1\issue_fsm_state$next[2:0]$13931 $2\issue_fsm_state$next[2:0]$13932 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" switch \$140 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\issue_fsm_state$next[2:0]$13946 $3\issue_fsm_state$next[2:0]$13947 + assign $2\issue_fsm_state$next[2:0]$13932 $3\issue_fsm_state$next[2:0]$13933 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:520" switch \fetch_pc_ready_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\issue_fsm_state$next[2:0]$13947 3'001 + assign $3\issue_fsm_state$next[2:0]$13933 3'001 case - assign $3\issue_fsm_state$next[2:0]$13947 \issue_fsm_state + assign $3\issue_fsm_state$next[2:0]$13933 \issue_fsm_state end case - assign $2\issue_fsm_state$next[2:0]$13946 \issue_fsm_state + assign $2\issue_fsm_state$next[2:0]$13932 \issue_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } - assign $1\issue_fsm_state$next[2:0]$13945 $4\issue_fsm_state$next[2:0]$13948 + assign $1\issue_fsm_state$next[2:0]$13931 $4\issue_fsm_state$next[2:0]$13934 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\issue_fsm_state$next[2:0]$13948 $5\issue_fsm_state$next[2:0]$13949 + assign $4\issue_fsm_state$next[2:0]$13934 $5\issue_fsm_state$next[2:0]$13935 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:551" switch \$144 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\issue_fsm_state$next[2:0]$13949 3'000 + assign $5\issue_fsm_state$next[2:0]$13935 3'000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $5\issue_fsm_state$next[2:0]$13949 3'010 + assign $5\issue_fsm_state$next[2:0]$13935 3'010 end case - assign $4\issue_fsm_state$next[2:0]$13948 \issue_fsm_state + assign $4\issue_fsm_state$next[2:0]$13934 \issue_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'011 assign { } { } - assign $1\issue_fsm_state$next[2:0]$13945 $6\issue_fsm_state$next[2:0]$13950 + assign $1\issue_fsm_state$next[2:0]$13931 $6\issue_fsm_state$next[2:0]$13936 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:567" switch \pred_insn_ready_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\issue_fsm_state$next[2:0]$13950 3'100 + assign $6\issue_fsm_state$next[2:0]$13936 3'100 case - assign $6\issue_fsm_state$next[2:0]$13950 \issue_fsm_state + assign $6\issue_fsm_state$next[2:0]$13936 \issue_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'100 assign { } { } - assign $1\issue_fsm_state$next[2:0]$13945 $7\issue_fsm_state$next[2:0]$13951 + assign $1\issue_fsm_state$next[2:0]$13931 $7\issue_fsm_state$next[2:0]$13937 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:572" switch \pred_mask_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\issue_fsm_state$next[2:0]$13951 3'010 + assign $7\issue_fsm_state$next[2:0]$13937 3'010 case - assign $7\issue_fsm_state$next[2:0]$13951 \issue_fsm_state + assign $7\issue_fsm_state$next[2:0]$13937 \issue_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'010 assign { } { } - assign $1\issue_fsm_state$next[2:0]$13945 $8\issue_fsm_state$next[2:0]$13952 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:612" + assign $1\issue_fsm_state$next[2:0]$13931 $8\issue_fsm_state$next[2:0]$13938 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:613" switch \exec_insn_ready_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $8\issue_fsm_state$next[2:0]$13952 3'101 + assign $8\issue_fsm_state$next[2:0]$13938 3'101 case - assign $8\issue_fsm_state$next[2:0]$13952 \issue_fsm_state + assign $8\issue_fsm_state$next[2:0]$13938 \issue_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'101 assign { } { } - assign $1\issue_fsm_state$next[2:0]$13945 $9\issue_fsm_state$next[2:0]$13953 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + assign $1\issue_fsm_state$next[2:0]$13931 $9\issue_fsm_state$next[2:0]$13939 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" switch \$150 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $9\issue_fsm_state$next[2:0]$13953 $10\issue_fsm_state$next[2:0]$13954 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:620" + assign $9\issue_fsm_state$next[2:0]$13939 $10\issue_fsm_state$next[2:0]$13940 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:621" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $10\issue_fsm_state$next[2:0]$13954 $11\issue_fsm_state$next[2:0]$13955 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" + assign $10\issue_fsm_state$next[2:0]$13940 $11\issue_fsm_state$next[2:0]$13941 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" switch { \$156 \$152 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $11\issue_fsm_state$next[2:0]$13955 3'000 + assign $11\issue_fsm_state$next[2:0]$13941 3'000 attribute \src "libresoc.v:0.0-0.0" case 2'1- assign { } { } - assign $11\issue_fsm_state$next[2:0]$13955 3'000 + assign $11\issue_fsm_state$next[2:0]$13941 3'000 attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $11\issue_fsm_state$next[2:0]$13955 3'110 + assign $11\issue_fsm_state$next[2:0]$13941 3'110 end case - assign $10\issue_fsm_state$next[2:0]$13954 \issue_fsm_state + assign $10\issue_fsm_state$next[2:0]$13940 \issue_fsm_state end case - assign $9\issue_fsm_state$next[2:0]$13953 \issue_fsm_state + assign $9\issue_fsm_state$next[2:0]$13939 \issue_fsm_state end attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } - assign $1\issue_fsm_state$next[2:0]$13945 3'010 + assign $1\issue_fsm_state$next[2:0]$13931 3'010 case - assign $1\issue_fsm_state$next[2:0]$13945 \issue_fsm_state + assign $1\issue_fsm_state$next[2:0]$13931 \issue_fsm_state end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $12\issue_fsm_state$next[2:0]$13956 3'000 + assign $12\issue_fsm_state$next[2:0]$13942 3'000 case - assign $12\issue_fsm_state$next[2:0]$13956 $1\issue_fsm_state$next[2:0]$13945 + assign $12\issue_fsm_state$next[2:0]$13942 $1\issue_fsm_state$next[2:0]$13931 end sync always - update \issue_fsm_state$next $0\issue_fsm_state$next[2:0]$13944 + update \issue_fsm_state$next $0\issue_fsm_state$next[2:0]$13930 end - attribute \src "libresoc.v:198622.3-198652.6" - process $proc$libresoc.v:198622$13957 + attribute \src "libresoc.v:201207.3-201253.6" + process $proc$libresoc.v:201207$13943 assign { } { } assign { } { } assign $0\core_stopped_i[0:0] $1\core_stopped_i[0:0] - attribute \src "libresoc.v:198623.5-198623.29" + attribute \src "libresoc.v:201208.5-201208.29" switch \initial - attribute \src "libresoc.v:198623.9-198623.17" + attribute \src "libresoc.v:201208.9-201208.17" case 1'1 case end @@ -410679,10 +383328,22 @@ module \ti assign $2\core_stopped_i[0:0] 1'1 end attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign $1\core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 3'101 assign { } { } assign $1\core_stopped_i[0:0] $3\core_stopped_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" switch \$168 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410698,14 +383359,14 @@ module \ti sync always update \core_stopped_i $0\core_stopped_i[0:0] end - attribute \src "libresoc.v:198653.3-198683.6" - process $proc$libresoc.v:198653$13958 + attribute \src "libresoc.v:201254.3-201300.6" + process $proc$libresoc.v:201254$13944 assign { } { } assign { } { } assign $0\dbg_core_stopped_i[0:0] $1\dbg_core_stopped_i[0:0] - attribute \src "libresoc.v:198654.5-198654.29" + attribute \src "libresoc.v:201255.5-201255.29" switch \initial - attribute \src "libresoc.v:198654.9-198654.17" + attribute \src "libresoc.v:201255.9-201255.17" case 1'1 case end @@ -410726,10 +383387,22 @@ module \ti assign $2\dbg_core_stopped_i[0:0] 1'1 end attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\dbg_core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\dbg_core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign $1\dbg_core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\dbg_core_stopped_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 3'101 assign { } { } assign $1\dbg_core_stopped_i[0:0] $3\dbg_core_stopped_i[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" switch \$180 attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410745,16 +383418,16 @@ module \ti sync always update \dbg_core_stopped_i $0\dbg_core_stopped_i[0:0] end - attribute \src "libresoc.v:198684.3-198750.6" - process $proc$libresoc.v:198684$13959 + attribute \src "libresoc.v:201301.3-201383.6" + process $proc$libresoc.v:201301$13945 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\pc_changed$next[0:0]$13960 $9\pc_changed$next[0:0]$13969 - attribute \src "libresoc.v:198685.5-198685.29" + assign $0\pc_changed$next[0:0]$13946 $9\pc_changed$next[0:0]$13955 + attribute \src "libresoc.v:201302.5-201302.29" switch \initial - attribute \src "libresoc.v:198685.9-198685.17" + attribute \src "libresoc.v:201302.9-201302.17" case 1'1 case end @@ -410763,103 +383436,115 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\pc_changed$next[0:0]$13961 $2\pc_changed$next[0:0]$13962 + assign $1\pc_changed$next[0:0]$13947 $2\pc_changed$next[0:0]$13948 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" switch \$186 attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $2\pc_changed$next[0:0]$13962 \pc_changed + assign $2\pc_changed$next[0:0]$13948 \pc_changed attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\pc_changed$next[0:0]$13962 $3\pc_changed$next[0:0]$13963 + assign $2\pc_changed$next[0:0]$13948 $3\pc_changed$next[0:0]$13949 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:527" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\pc_changed$next[0:0]$13963 1'1 + assign $3\pc_changed$next[0:0]$13949 1'1 case - assign $3\pc_changed$next[0:0]$13963 \pc_changed + assign $3\pc_changed$next[0:0]$13949 \pc_changed end end attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\pc_changed$next[0:0]$13947 \pc_changed + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\pc_changed$next[0:0]$13947 \pc_changed + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign $1\pc_changed$next[0:0]$13947 \pc_changed + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\pc_changed$next[0:0]$13947 \pc_changed + attribute \src "libresoc.v:0.0-0.0" case 3'101 assign { } { } - assign $1\pc_changed$next[0:0]$13961 $4\pc_changed$next[0:0]$13964 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + assign $1\pc_changed$next[0:0]$13947 $4\pc_changed$next[0:0]$13950 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" switch \$192 attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $4\pc_changed$next[0:0]$13964 \pc_changed + assign $4\pc_changed$next[0:0]$13950 \pc_changed attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $4\pc_changed$next[0:0]$13964 $5\pc_changed$next[0:0]$13965 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:662" + assign $4\pc_changed$next[0:0]$13950 $5\pc_changed$next[0:0]$13951 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:663" switch \pc_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\pc_changed$next[0:0]$13965 1'1 + assign $5\pc_changed$next[0:0]$13951 1'1 case - assign $5\pc_changed$next[0:0]$13965 \pc_changed + assign $5\pc_changed$next[0:0]$13951 \pc_changed end end case - assign $1\pc_changed$next[0:0]$13961 \pc_changed + assign $1\pc_changed$next[0:0]$13947 \pc_changed end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 assign { } { } - assign $6\pc_changed$next[0:0]$13966 $7\pc_changed$next[0:0]$13967 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:714" + assign $6\pc_changed$next[0:0]$13952 $7\pc_changed$next[0:0]$13953 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:715" switch \exec_insn_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\pc_changed$next[0:0]$13967 1'0 + assign $7\pc_changed$next[0:0]$13953 1'0 case - assign $7\pc_changed$next[0:0]$13967 $1\pc_changed$next[0:0]$13961 + assign $7\pc_changed$next[0:0]$13953 $1\pc_changed$next[0:0]$13947 end attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\pc_changed$next[0:0]$13966 $8\pc_changed$next[0:0]$13968 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:728" + assign $6\pc_changed$next[0:0]$13952 $8\pc_changed$next[0:0]$13954 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:729" switch \$194 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $8\pc_changed$next[0:0]$13968 1'1 + assign $8\pc_changed$next[0:0]$13954 1'1 case - assign $8\pc_changed$next[0:0]$13968 $1\pc_changed$next[0:0]$13961 + assign $8\pc_changed$next[0:0]$13954 $1\pc_changed$next[0:0]$13947 end case - assign $6\pc_changed$next[0:0]$13966 $1\pc_changed$next[0:0]$13961 + assign $6\pc_changed$next[0:0]$13952 $1\pc_changed$next[0:0]$13947 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $9\pc_changed$next[0:0]$13969 1'0 + assign $9\pc_changed$next[0:0]$13955 1'0 case - assign $9\pc_changed$next[0:0]$13969 $6\pc_changed$next[0:0]$13966 + assign $9\pc_changed$next[0:0]$13955 $6\pc_changed$next[0:0]$13952 end sync always - update \pc_changed$next $0\pc_changed$next[0:0]$13960 + update \pc_changed$next $0\pc_changed$next[0:0]$13946 end - attribute \src "libresoc.v:198751.3-198807.6" - process $proc$libresoc.v:198751$13970 + attribute \src "libresoc.v:201384.3-201456.6" + process $proc$libresoc.v:201384$13956 assign { } { } assign { } { } assign $0\update_svstate[0:0] $1\update_svstate[0:0] - attribute \src "libresoc.v:198752.5-198752.29" + attribute \src "libresoc.v:201385.5-201385.29" switch \initial - attribute \src "libresoc.v:198752.9-198752.17" + attribute \src "libresoc.v:201385.9-201385.17" case 1'1 case end @@ -410889,22 +383574,34 @@ module \ti end end attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\update_svstate[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\update_svstate[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign $1\update_svstate[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\update_svstate[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 3'101 assign { } { } assign $1\update_svstate[0:0] $4\update_svstate[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" switch \$208 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $4\update_svstate[0:0] $5\update_svstate[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:620" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:621" switch \exec_pc_valid_o attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign $5\update_svstate[0:0] $6\update_svstate[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:630" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:631" switch { \$214 \$210 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 @@ -410924,7 +383621,7 @@ module \ti case assign { } { } assign $4\update_svstate[0:0] $7\update_svstate[0:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:666" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:667" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 @@ -410940,16 +383637,16 @@ module \ti sync always update \update_svstate $0\update_svstate[0:0] end - attribute \src "libresoc.v:198808.3-198874.6" - process $proc$libresoc.v:198808$13971 + attribute \src "libresoc.v:201457.3-201539.6" + process $proc$libresoc.v:201457$13957 assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\sv_changed$next[0:0]$13972 $9\sv_changed$next[0:0]$13981 - attribute \src "libresoc.v:198809.5-198809.29" + assign $0\sv_changed$next[0:0]$13958 $9\sv_changed$next[0:0]$13967 + attribute \src "libresoc.v:201458.5-201458.29" switch \initial - attribute \src "libresoc.v:198809.9-198809.17" + attribute \src "libresoc.v:201458.9-201458.17" case 1'1 case end @@ -410958,109 +383655,124 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 3'000 assign { } { } - assign $1\sv_changed$next[0:0]$13973 $2\sv_changed$next[0:0]$13974 + assign $1\sv_changed$next[0:0]$13959 $2\sv_changed$next[0:0]$13960 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:518" switch \$220 attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $2\sv_changed$next[0:0]$13974 \sv_changed + assign $2\sv_changed$next[0:0]$13960 \sv_changed attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $2\sv_changed$next[0:0]$13974 $3\sv_changed$next[0:0]$13975 + assign $2\sv_changed$next[0:0]$13960 $3\sv_changed$next[0:0]$13961 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:531" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\sv_changed$next[0:0]$13975 1'1 + assign $3\sv_changed$next[0:0]$13961 1'1 case - assign $3\sv_changed$next[0:0]$13975 \sv_changed + assign $3\sv_changed$next[0:0]$13961 \sv_changed end end attribute \src "libresoc.v:0.0-0.0" + case 3'001 + assign $1\sv_changed$next[0:0]$13959 \sv_changed + attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\sv_changed$next[0:0]$13959 \sv_changed + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign $1\sv_changed$next[0:0]$13959 \sv_changed + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\sv_changed$next[0:0]$13959 \sv_changed + attribute \src "libresoc.v:0.0-0.0" case 3'101 assign { } { } - assign $1\sv_changed$next[0:0]$13973 $4\sv_changed$next[0:0]$13976 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:618" + assign $1\sv_changed$next[0:0]$13959 $4\sv_changed$next[0:0]$13962 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:619" switch \$226 attribute \src "libresoc.v:0.0-0.0" case 1'1 - assign $4\sv_changed$next[0:0]$13976 \sv_changed + assign $4\sv_changed$next[0:0]$13962 \sv_changed attribute \src "libresoc.v:0.0-0.0" case assign { } { } - assign $4\sv_changed$next[0:0]$13976 $5\sv_changed$next[0:0]$13977 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:666" + assign $4\sv_changed$next[0:0]$13962 $5\sv_changed$next[0:0]$13963 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:667" switch \svstate_i_ok attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $5\sv_changed$next[0:0]$13977 1'1 + assign $5\sv_changed$next[0:0]$13963 1'1 case - assign $5\sv_changed$next[0:0]$13977 \sv_changed + assign $5\sv_changed$next[0:0]$13963 \sv_changed end end case - assign $1\sv_changed$next[0:0]$13973 \sv_changed + assign $1\sv_changed$next[0:0]$13959 \sv_changed end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:709" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:710" switch \exec_fsm_state attribute \src "libresoc.v:0.0-0.0" case 1'0 assign { } { } - assign $6\sv_changed$next[0:0]$13978 $7\sv_changed$next[0:0]$13979 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:714" + assign $6\sv_changed$next[0:0]$13964 $7\sv_changed$next[0:0]$13965 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:715" switch \exec_insn_valid_i attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $7\sv_changed$next[0:0]$13979 1'0 + assign $7\sv_changed$next[0:0]$13965 1'0 case - assign $7\sv_changed$next[0:0]$13979 $1\sv_changed$next[0:0]$13973 + assign $7\sv_changed$next[0:0]$13965 $1\sv_changed$next[0:0]$13959 end attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $6\sv_changed$next[0:0]$13978 $8\sv_changed$next[0:0]$13980 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:726" + assign $6\sv_changed$next[0:0]$13964 $8\sv_changed$next[0:0]$13966 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:727" switch \$228 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $8\sv_changed$next[0:0]$13980 1'1 + assign $8\sv_changed$next[0:0]$13966 1'1 case - assign $8\sv_changed$next[0:0]$13980 $1\sv_changed$next[0:0]$13973 + assign $8\sv_changed$next[0:0]$13966 $1\sv_changed$next[0:0]$13959 end case - assign $6\sv_changed$next[0:0]$13978 $1\sv_changed$next[0:0]$13973 + assign $6\sv_changed$next[0:0]$13964 $1\sv_changed$next[0:0]$13959 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $9\sv_changed$next[0:0]$13981 1'0 + assign $9\sv_changed$next[0:0]$13967 1'0 case - assign $9\sv_changed$next[0:0]$13981 $6\sv_changed$next[0:0]$13978 + assign $9\sv_changed$next[0:0]$13967 $6\sv_changed$next[0:0]$13964 end sync always - update \sv_changed$next $0\sv_changed$next[0:0]$13972 + update \sv_changed$next $0\sv_changed$next[0:0]$13958 end - attribute \src "libresoc.v:198875.3-198885.6" - process $proc$libresoc.v:198875$13982 + attribute \src "libresoc.v:201540.3-201554.6" + process $proc$libresoc.v:201540$13968 assign { } { } assign { } { } assign $0\fetch_insn_ready_i[0:0] $1\fetch_insn_ready_i[0:0] - attribute \src "libresoc.v:198876.5-198876.29" + attribute \src "libresoc.v:201541.5-201541.29" switch \initial - attribute \src "libresoc.v:198876.9-198876.17" + attribute \src "libresoc.v:201541.9-201541.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\fetch_insn_ready_i[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } assign $1\fetch_insn_ready_i[0:0] 1'1 @@ -411070,8 +383782,8 @@ module \ti sync always update \fetch_insn_ready_i $0\fetch_insn_ready_i[0:0] end - attribute \src "libresoc.v:198886.3-198996.6" - process $proc$libresoc.v:198886$13983 + attribute \src "libresoc.v:201555.3-201685.6" + process $proc$libresoc.v:201555$13969 assign { } { } assign { } { } assign { } { } @@ -411190,11 +383902,11 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $0\core_asmcode$next[7:0]$13984 $1\core_asmcode$next[7:0]$14043 - assign $0\core_core_core_cia$next[63:0]$13985 $1\core_core_core_cia$next[63:0]$14044 - assign $0\core_core_core_cr_rd$next[7:0]$13986 $1\core_core_core_cr_rd$next[7:0]$14045 + assign $0\core_asmcode$next[7:0]$13970 $1\core_asmcode$next[7:0]$14029 + assign $0\core_core_core_cia$next[63:0]$13971 $1\core_core_core_cia$next[63:0]$14030 + assign $0\core_core_core_cr_rd$next[7:0]$13972 $1\core_core_core_cr_rd$next[7:0]$14031 assign { } { } - assign $0\core_core_core_cr_wr$next[7:0]$13988 $1\core_core_core_cr_wr$next[7:0]$14047 + assign $0\core_core_core_cr_wr$next[7:0]$13974 $1\core_core_core_cr_wr$next[7:0]$14033 assign { } { } assign { } { } assign { } { } @@ -411203,88 +383915,149 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $0\core_core_core_fn_unit$next[13:0]$13997 $1\core_core_core_fn_unit$next[13:0]$14056 - assign $0\core_core_core_input_carry$next[1:0]$13998 $1\core_core_core_input_carry$next[1:0]$14057 - assign $0\core_core_core_insn$next[31:0]$13999 $1\core_core_core_insn$next[31:0]$14058 - assign $0\core_core_core_insn_type$next[6:0]$14000 $1\core_core_core_insn_type$next[6:0]$14059 - assign $0\core_core_core_is_32bit$next[0:0]$14001 $1\core_core_core_is_32bit$next[0:0]$14060 - assign $0\core_core_core_msr$next[63:0]$14002 $1\core_core_core_msr$next[63:0]$14061 - assign $0\core_core_core_oe$next[0:0]$14003 $1\core_core_core_oe$next[0:0]$14062 + assign $0\core_core_core_fn_unit$next[13:0]$13983 $1\core_core_core_fn_unit$next[13:0]$14042 + assign $0\core_core_core_input_carry$next[1:0]$13984 $1\core_core_core_input_carry$next[1:0]$14043 + assign $0\core_core_core_insn$next[31:0]$13985 $1\core_core_core_insn$next[31:0]$14044 + assign $0\core_core_core_insn_type$next[6:0]$13986 $1\core_core_core_insn_type$next[6:0]$14045 + assign $0\core_core_core_is_32bit$next[0:0]$13987 $1\core_core_core_is_32bit$next[0:0]$14046 + assign $0\core_core_core_msr$next[63:0]$13988 $1\core_core_core_msr$next[63:0]$14047 + assign $0\core_core_core_oe$next[0:0]$13989 $1\core_core_core_oe$next[0:0]$14048 assign { } { } - assign $0\core_core_core_rc$next[0:0]$14005 $1\core_core_core_rc$next[0:0]$14064 + assign $0\core_core_core_rc$next[0:0]$13991 $1\core_core_core_rc$next[0:0]$14050 assign { } { } - assign $0\core_core_core_trapaddr$next[12:0]$14007 $1\core_core_core_trapaddr$next[12:0]$14066 - assign $0\core_core_core_traptype$next[7:0]$14008 $1\core_core_core_traptype$next[7:0]$14067 - assign $0\core_core_cr_in1$next[6:0]$14009 $1\core_core_cr_in1$next[6:0]$14068 + assign $0\core_core_core_trapaddr$next[12:0]$13993 $1\core_core_core_trapaddr$next[12:0]$14052 + assign $0\core_core_core_traptype$next[7:0]$13994 $1\core_core_core_traptype$next[7:0]$14053 + assign $0\core_core_cr_in1$next[6:0]$13995 $1\core_core_cr_in1$next[6:0]$14054 assign { } { } - assign $0\core_core_cr_in2$1$next[6:0]$14011 $1\core_core_cr_in2$1$next[6:0]$14070 - assign $0\core_core_cr_in2$next[6:0]$14012 $1\core_core_cr_in2$next[6:0]$14071 + assign $0\core_core_cr_in2$1$next[6:0]$13997 $1\core_core_cr_in2$1$next[6:0]$14056 + assign $0\core_core_cr_in2$next[6:0]$13998 $1\core_core_cr_in2$next[6:0]$14057 assign { } { } assign { } { } - assign $0\core_core_cr_out$next[6:0]$14015 $1\core_core_cr_out$next[6:0]$14074 + assign $0\core_core_cr_out$next[6:0]$14001 $1\core_core_cr_out$next[6:0]$14060 assign { } { } - assign $0\core_core_ea$next[6:0]$14017 $1\core_core_ea$next[6:0]$14076 - assign $0\core_core_fast1$next[2:0]$14018 $1\core_core_fast1$next[2:0]$14077 + assign $0\core_core_ea$next[6:0]$14003 $1\core_core_ea$next[6:0]$14062 + assign $0\core_core_fast1$next[2:0]$14004 $1\core_core_fast1$next[2:0]$14063 assign { } { } - assign $0\core_core_fast2$next[2:0]$14020 $1\core_core_fast2$next[2:0]$14079 + assign $0\core_core_fast2$next[2:0]$14006 $1\core_core_fast2$next[2:0]$14065 assign { } { } - assign $0\core_core_fasto1$next[2:0]$14022 $1\core_core_fasto1$next[2:0]$14081 - assign $0\core_core_fasto2$next[2:0]$14023 $1\core_core_fasto2$next[2:0]$14082 - assign $0\core_core_lk$next[0:0]$14024 $1\core_core_lk$next[0:0]$14083 - assign $0\core_core_reg1$next[6:0]$14025 $1\core_core_reg1$next[6:0]$14084 + assign $0\core_core_fasto1$next[2:0]$14008 $1\core_core_fasto1$next[2:0]$14067 + assign $0\core_core_fasto2$next[2:0]$14009 $1\core_core_fasto2$next[2:0]$14068 + assign $0\core_core_lk$next[0:0]$14010 $1\core_core_lk$next[0:0]$14069 + assign $0\core_core_reg1$next[6:0]$14011 $1\core_core_reg1$next[6:0]$14070 assign { } { } - assign $0\core_core_reg2$next[6:0]$14027 $1\core_core_reg2$next[6:0]$14086 + assign $0\core_core_reg2$next[6:0]$14013 $1\core_core_reg2$next[6:0]$14072 assign { } { } - assign $0\core_core_reg3$next[6:0]$14029 $1\core_core_reg3$next[6:0]$14088 + assign $0\core_core_reg3$next[6:0]$14015 $1\core_core_reg3$next[6:0]$14074 assign { } { } - assign $0\core_core_rego$next[6:0]$14031 $1\core_core_rego$next[6:0]$14090 - assign $0\core_core_spr1$next[9:0]$14032 $1\core_core_spr1$next[9:0]$14091 + assign $0\core_core_rego$next[6:0]$14017 $1\core_core_rego$next[6:0]$14076 + assign $0\core_core_spr1$next[9:0]$14018 $1\core_core_spr1$next[9:0]$14077 assign { } { } - assign $0\core_core_spro$next[9:0]$14034 $1\core_core_spro$next[9:0]$14093 - assign $0\core_core_xer_in$next[2:0]$14035 $1\core_core_xer_in$next[2:0]$14094 + assign $0\core_core_spro$next[9:0]$14020 $1\core_core_spro$next[9:0]$14079 + assign $0\core_core_xer_in$next[2:0]$14021 $1\core_core_xer_in$next[2:0]$14080 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\core_xer_out$next[0:0]$14042 $1\core_xer_out$next[0:0]$14101 - assign $0\core_core_core_cr_rd_ok$next[0:0]$13987 $3\core_core_core_cr_rd_ok$next[0:0]$14161 - assign $0\core_core_core_exc_$signal$3$next[0:0]$13989 $3\core_core_core_exc_$signal$3$next[0:0]$14162 - assign $0\core_core_core_exc_$signal$4$next[0:0]$13990 $3\core_core_core_exc_$signal$4$next[0:0]$14163 - assign $0\core_core_core_exc_$signal$5$next[0:0]$13991 $3\core_core_core_exc_$signal$5$next[0:0]$14164 - assign $0\core_core_core_exc_$signal$6$next[0:0]$13992 $3\core_core_core_exc_$signal$6$next[0:0]$14165 - assign $0\core_core_core_exc_$signal$7$next[0:0]$13993 $3\core_core_core_exc_$signal$7$next[0:0]$14166 - assign $0\core_core_core_exc_$signal$8$next[0:0]$13994 $3\core_core_core_exc_$signal$8$next[0:0]$14167 - assign $0\core_core_core_exc_$signal$9$next[0:0]$13995 $3\core_core_core_exc_$signal$9$next[0:0]$14168 - assign $0\core_core_core_exc_$signal$next[0:0]$13996 $3\core_core_core_exc_$signal$next[0:0]$14169 - assign $0\core_core_core_oe_ok$next[0:0]$14004 $3\core_core_core_oe_ok$next[0:0]$14170 - assign $0\core_core_core_rc_ok$next[0:0]$14006 $3\core_core_core_rc_ok$next[0:0]$14171 - assign $0\core_core_cr_in1_ok$next[0:0]$14010 $3\core_core_cr_in1_ok$next[0:0]$14172 - assign $0\core_core_cr_in2_ok$2$next[0:0]$14013 $3\core_core_cr_in2_ok$2$next[0:0]$14173 - assign $0\core_core_cr_in2_ok$next[0:0]$14014 $3\core_core_cr_in2_ok$next[0:0]$14174 - assign $0\core_core_cr_wr_ok$next[0:0]$14016 $3\core_core_cr_wr_ok$next[0:0]$14175 - assign $0\core_core_fast1_ok$next[0:0]$14019 $3\core_core_fast1_ok$next[0:0]$14176 - assign $0\core_core_fast2_ok$next[0:0]$14021 $3\core_core_fast2_ok$next[0:0]$14177 - assign $0\core_core_reg1_ok$next[0:0]$14026 $3\core_core_reg1_ok$next[0:0]$14178 - assign $0\core_core_reg2_ok$next[0:0]$14028 $3\core_core_reg2_ok$next[0:0]$14179 - assign $0\core_core_reg3_ok$next[0:0]$14030 $3\core_core_reg3_ok$next[0:0]$14180 - assign $0\core_core_spr1_ok$next[0:0]$14033 $3\core_core_spr1_ok$next[0:0]$14181 - assign $0\core_cr_out_ok$next[0:0]$14036 $3\core_cr_out_ok$next[0:0]$14182 - assign $0\core_ea_ok$next[0:0]$14037 $3\core_ea_ok$next[0:0]$14183 - assign $0\core_fasto1_ok$next[0:0]$14038 $3\core_fasto1_ok$next[0:0]$14184 - assign $0\core_fasto2_ok$next[0:0]$14039 $3\core_fasto2_ok$next[0:0]$14185 - assign $0\core_rego_ok$next[0:0]$14040 $3\core_rego_ok$next[0:0]$14186 - assign $0\core_spro_ok$next[0:0]$14041 $3\core_spro_ok$next[0:0]$14187 - attribute \src "libresoc.v:198887.5-198887.29" + assign $0\core_xer_out$next[0:0]$14028 $1\core_xer_out$next[0:0]$14087 + assign $0\core_core_core_cr_rd_ok$next[0:0]$13973 $3\core_core_core_cr_rd_ok$next[0:0]$14147 + assign $0\core_core_core_exc_$signal$3$next[0:0]$13975 $3\core_core_core_exc_$signal$3$next[0:0]$14148 + assign $0\core_core_core_exc_$signal$4$next[0:0]$13976 $3\core_core_core_exc_$signal$4$next[0:0]$14149 + assign $0\core_core_core_exc_$signal$5$next[0:0]$13977 $3\core_core_core_exc_$signal$5$next[0:0]$14150 + assign $0\core_core_core_exc_$signal$6$next[0:0]$13978 $3\core_core_core_exc_$signal$6$next[0:0]$14151 + assign $0\core_core_core_exc_$signal$7$next[0:0]$13979 $3\core_core_core_exc_$signal$7$next[0:0]$14152 + assign $0\core_core_core_exc_$signal$8$next[0:0]$13980 $3\core_core_core_exc_$signal$8$next[0:0]$14153 + assign $0\core_core_core_exc_$signal$9$next[0:0]$13981 $3\core_core_core_exc_$signal$9$next[0:0]$14154 + assign $0\core_core_core_exc_$signal$next[0:0]$13982 $3\core_core_core_exc_$signal$next[0:0]$14155 + assign $0\core_core_core_oe_ok$next[0:0]$13990 $3\core_core_core_oe_ok$next[0:0]$14156 + assign $0\core_core_core_rc_ok$next[0:0]$13992 $3\core_core_core_rc_ok$next[0:0]$14157 + assign $0\core_core_cr_in1_ok$next[0:0]$13996 $3\core_core_cr_in1_ok$next[0:0]$14158 + assign $0\core_core_cr_in2_ok$2$next[0:0]$13999 $3\core_core_cr_in2_ok$2$next[0:0]$14159 + assign $0\core_core_cr_in2_ok$next[0:0]$14000 $3\core_core_cr_in2_ok$next[0:0]$14160 + assign $0\core_core_cr_wr_ok$next[0:0]$14002 $3\core_core_cr_wr_ok$next[0:0]$14161 + assign $0\core_core_fast1_ok$next[0:0]$14005 $3\core_core_fast1_ok$next[0:0]$14162 + assign $0\core_core_fast2_ok$next[0:0]$14007 $3\core_core_fast2_ok$next[0:0]$14163 + assign $0\core_core_reg1_ok$next[0:0]$14012 $3\core_core_reg1_ok$next[0:0]$14164 + assign $0\core_core_reg2_ok$next[0:0]$14014 $3\core_core_reg2_ok$next[0:0]$14165 + assign $0\core_core_reg3_ok$next[0:0]$14016 $3\core_core_reg3_ok$next[0:0]$14166 + assign $0\core_core_spr1_ok$next[0:0]$14019 $3\core_core_spr1_ok$next[0:0]$14167 + assign $0\core_cr_out_ok$next[0:0]$14022 $3\core_cr_out_ok$next[0:0]$14168 + assign $0\core_ea_ok$next[0:0]$14023 $3\core_ea_ok$next[0:0]$14169 + assign $0\core_fasto1_ok$next[0:0]$14024 $3\core_fasto1_ok$next[0:0]$14170 + assign $0\core_fasto2_ok$next[0:0]$14025 $3\core_fasto2_ok$next[0:0]$14171 + assign $0\core_rego_ok$next[0:0]$14026 $3\core_rego_ok$next[0:0]$14172 + assign $0\core_spro_ok$next[0:0]$14027 $3\core_spro_ok$next[0:0]$14173 + attribute \src "libresoc.v:201556.5-201556.29" switch \initial - attribute \src "libresoc.v:198887.9-198887.17" + attribute \src "libresoc.v:201556.9-201556.17" case 1'1 case end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:510" switch \issue_fsm_state attribute \src "libresoc.v:0.0-0.0" + case 3'000 + assign $1\core_asmcode$next[7:0]$14029 \core_asmcode + assign $1\core_core_core_cia$next[63:0]$14030 \core_core_core_cia + assign $1\core_core_core_cr_rd$next[7:0]$14031 \core_core_core_cr_rd + assign $1\core_core_core_cr_rd_ok$next[0:0]$14032 \core_core_core_cr_rd_ok + assign $1\core_core_core_cr_wr$next[7:0]$14033 \core_core_core_cr_wr + assign $1\core_core_core_exc_$signal$3$next[0:0]$14034 \core_core_core_exc_$signal$3 + assign $1\core_core_core_exc_$signal$4$next[0:0]$14035 \core_core_core_exc_$signal$4 + assign $1\core_core_core_exc_$signal$5$next[0:0]$14036 \core_core_core_exc_$signal$5 + assign $1\core_core_core_exc_$signal$6$next[0:0]$14037 \core_core_core_exc_$signal$6 + assign $1\core_core_core_exc_$signal$7$next[0:0]$14038 \core_core_core_exc_$signal$7 + assign $1\core_core_core_exc_$signal$8$next[0:0]$14039 \core_core_core_exc_$signal$8 + assign $1\core_core_core_exc_$signal$9$next[0:0]$14040 \core_core_core_exc_$signal$9 + assign $1\core_core_core_exc_$signal$next[0:0]$14041 \core_core_core_exc_$signal + assign $1\core_core_core_fn_unit$next[13:0]$14042 \core_core_core_fn_unit + assign $1\core_core_core_input_carry$next[1:0]$14043 \core_core_core_input_carry + assign $1\core_core_core_insn$next[31:0]$14044 \core_core_core_insn + assign $1\core_core_core_insn_type$next[6:0]$14045 \core_core_core_insn_type + assign $1\core_core_core_is_32bit$next[0:0]$14046 \core_core_core_is_32bit + assign $1\core_core_core_msr$next[63:0]$14047 \core_core_core_msr + assign $1\core_core_core_oe$next[0:0]$14048 \core_core_core_oe + assign $1\core_core_core_oe_ok$next[0:0]$14049 \core_core_core_oe_ok + assign $1\core_core_core_rc$next[0:0]$14050 \core_core_core_rc + assign $1\core_core_core_rc_ok$next[0:0]$14051 \core_core_core_rc_ok + assign $1\core_core_core_trapaddr$next[12:0]$14052 \core_core_core_trapaddr + assign $1\core_core_core_traptype$next[7:0]$14053 \core_core_core_traptype + assign $1\core_core_cr_in1$next[6:0]$14054 \core_core_cr_in1 + assign $1\core_core_cr_in1_ok$next[0:0]$14055 \core_core_cr_in1_ok + assign $1\core_core_cr_in2$1$next[6:0]$14056 \core_core_cr_in2$1 + assign $1\core_core_cr_in2$next[6:0]$14057 \core_core_cr_in2 + assign $1\core_core_cr_in2_ok$2$next[0:0]$14058 \core_core_cr_in2_ok$2 + assign $1\core_core_cr_in2_ok$next[0:0]$14059 \core_core_cr_in2_ok + assign $1\core_core_cr_out$next[6:0]$14060 \core_core_cr_out + assign $1\core_core_cr_wr_ok$next[0:0]$14061 \core_core_cr_wr_ok + assign $1\core_core_ea$next[6:0]$14062 \core_core_ea + assign $1\core_core_fast1$next[2:0]$14063 \core_core_fast1 + assign $1\core_core_fast1_ok$next[0:0]$14064 \core_core_fast1_ok + assign $1\core_core_fast2$next[2:0]$14065 \core_core_fast2 + assign $1\core_core_fast2_ok$next[0:0]$14066 \core_core_fast2_ok + assign $1\core_core_fasto1$next[2:0]$14067 \core_core_fasto1 + assign $1\core_core_fasto2$next[2:0]$14068 \core_core_fasto2 + assign $1\core_core_lk$next[0:0]$14069 \core_core_lk + assign $1\core_core_reg1$next[6:0]$14070 \core_core_reg1 + assign $1\core_core_reg1_ok$next[0:0]$14071 \core_core_reg1_ok + assign $1\core_core_reg2$next[6:0]$14072 \core_core_reg2 + assign $1\core_core_reg2_ok$next[0:0]$14073 \core_core_reg2_ok + assign $1\core_core_reg3$next[6:0]$14074 \core_core_reg3 + assign $1\core_core_reg3_ok$next[0:0]$14075 \core_core_reg3_ok + assign $1\core_core_rego$next[6:0]$14076 \core_core_rego + assign $1\core_core_spr1$next[9:0]$14077 \core_core_spr1 + assign $1\core_core_spr1_ok$next[0:0]$14078 \core_core_spr1_ok + assign $1\core_core_spro$next[9:0]$14079 \core_core_spro + assign $1\core_core_xer_in$next[2:0]$14080 \core_core_xer_in + assign $1\core_cr_out_ok$next[0:0]$14081 \core_cr_out_ok + assign $1\core_ea_ok$next[0:0]$14082 \core_ea_ok + assign $1\core_fasto1_ok$next[0:0]$14083 \core_fasto1_ok + assign $1\core_fasto2_ok$next[0:0]$14084 \core_fasto2_ok + assign $1\core_rego_ok$next[0:0]$14085 \core_rego_ok + assign $1\core_spro_ok$next[0:0]$14086 \core_spro_ok + assign $1\core_xer_out$next[0:0]$14087 \core_xer_out + attribute \src "libresoc.v:0.0-0.0" case 3'001 assign { } { } assign { } { } @@ -411345,65 +384118,65 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $1\core_asmcode$next[7:0]$14043 $2\core_asmcode$next[7:0]$14102 - assign $1\core_core_core_cia$next[63:0]$14044 $2\core_core_core_cia$next[63:0]$14103 - assign $1\core_core_core_cr_rd$next[7:0]$14045 $2\core_core_core_cr_rd$next[7:0]$14104 - assign $1\core_core_core_cr_rd_ok$next[0:0]$14046 $2\core_core_core_cr_rd_ok$next[0:0]$14105 - assign $1\core_core_core_cr_wr$next[7:0]$14047 $2\core_core_core_cr_wr$next[7:0]$14106 - assign $1\core_core_core_exc_$signal$3$next[0:0]$14048 $2\core_core_core_exc_$signal$3$next[0:0]$14107 - assign $1\core_core_core_exc_$signal$4$next[0:0]$14049 $2\core_core_core_exc_$signal$4$next[0:0]$14108 - assign $1\core_core_core_exc_$signal$5$next[0:0]$14050 $2\core_core_core_exc_$signal$5$next[0:0]$14109 - assign $1\core_core_core_exc_$signal$6$next[0:0]$14051 $2\core_core_core_exc_$signal$6$next[0:0]$14110 - assign $1\core_core_core_exc_$signal$7$next[0:0]$14052 $2\core_core_core_exc_$signal$7$next[0:0]$14111 - assign $1\core_core_core_exc_$signal$8$next[0:0]$14053 $2\core_core_core_exc_$signal$8$next[0:0]$14112 - assign $1\core_core_core_exc_$signal$9$next[0:0]$14054 $2\core_core_core_exc_$signal$9$next[0:0]$14113 - assign $1\core_core_core_exc_$signal$next[0:0]$14055 $2\core_core_core_exc_$signal$next[0:0]$14114 - assign $1\core_core_core_fn_unit$next[13:0]$14056 $2\core_core_core_fn_unit$next[13:0]$14115 - assign $1\core_core_core_input_carry$next[1:0]$14057 $2\core_core_core_input_carry$next[1:0]$14116 - assign $1\core_core_core_insn$next[31:0]$14058 $2\core_core_core_insn$next[31:0]$14117 - assign $1\core_core_core_insn_type$next[6:0]$14059 $2\core_core_core_insn_type$next[6:0]$14118 - assign $1\core_core_core_is_32bit$next[0:0]$14060 $2\core_core_core_is_32bit$next[0:0]$14119 - assign $1\core_core_core_msr$next[63:0]$14061 $2\core_core_core_msr$next[63:0]$14120 - assign $1\core_core_core_oe$next[0:0]$14062 $2\core_core_core_oe$next[0:0]$14121 - assign $1\core_core_core_oe_ok$next[0:0]$14063 $2\core_core_core_oe_ok$next[0:0]$14122 - assign $1\core_core_core_rc$next[0:0]$14064 $2\core_core_core_rc$next[0:0]$14123 - assign $1\core_core_core_rc_ok$next[0:0]$14065 $2\core_core_core_rc_ok$next[0:0]$14124 - assign $1\core_core_core_trapaddr$next[12:0]$14066 $2\core_core_core_trapaddr$next[12:0]$14125 - assign $1\core_core_core_traptype$next[7:0]$14067 $2\core_core_core_traptype$next[7:0]$14126 - assign $1\core_core_cr_in1$next[6:0]$14068 $2\core_core_cr_in1$next[6:0]$14127 - assign $1\core_core_cr_in1_ok$next[0:0]$14069 $2\core_core_cr_in1_ok$next[0:0]$14128 - assign $1\core_core_cr_in2$1$next[6:0]$14070 $2\core_core_cr_in2$1$next[6:0]$14129 - assign $1\core_core_cr_in2$next[6:0]$14071 $2\core_core_cr_in2$next[6:0]$14130 - assign $1\core_core_cr_in2_ok$2$next[0:0]$14072 $2\core_core_cr_in2_ok$2$next[0:0]$14131 - assign $1\core_core_cr_in2_ok$next[0:0]$14073 $2\core_core_cr_in2_ok$next[0:0]$14132 - assign $1\core_core_cr_out$next[6:0]$14074 $2\core_core_cr_out$next[6:0]$14133 - assign $1\core_core_cr_wr_ok$next[0:0]$14075 $2\core_core_cr_wr_ok$next[0:0]$14134 - assign $1\core_core_ea$next[6:0]$14076 $2\core_core_ea$next[6:0]$14135 - assign $1\core_core_fast1$next[2:0]$14077 $2\core_core_fast1$next[2:0]$14136 - assign $1\core_core_fast1_ok$next[0:0]$14078 $2\core_core_fast1_ok$next[0:0]$14137 - assign $1\core_core_fast2$next[2:0]$14079 $2\core_core_fast2$next[2:0]$14138 - assign $1\core_core_fast2_ok$next[0:0]$14080 $2\core_core_fast2_ok$next[0:0]$14139 - assign $1\core_core_fasto1$next[2:0]$14081 $2\core_core_fasto1$next[2:0]$14140 - assign $1\core_core_fasto2$next[2:0]$14082 $2\core_core_fasto2$next[2:0]$14141 - assign $1\core_core_lk$next[0:0]$14083 $2\core_core_lk$next[0:0]$14142 - assign $1\core_core_reg1$next[6:0]$14084 $2\core_core_reg1$next[6:0]$14143 - assign $1\core_core_reg1_ok$next[0:0]$14085 $2\core_core_reg1_ok$next[0:0]$14144 - assign $1\core_core_reg2$next[6:0]$14086 $2\core_core_reg2$next[6:0]$14145 - assign $1\core_core_reg2_ok$next[0:0]$14087 $2\core_core_reg2_ok$next[0:0]$14146 - assign $1\core_core_reg3$next[6:0]$14088 $2\core_core_reg3$next[6:0]$14147 - assign $1\core_core_reg3_ok$next[0:0]$14089 $2\core_core_reg3_ok$next[0:0]$14148 - assign $1\core_core_rego$next[6:0]$14090 $2\core_core_rego$next[6:0]$14149 - assign $1\core_core_spr1$next[9:0]$14091 $2\core_core_spr1$next[9:0]$14150 - assign $1\core_core_spr1_ok$next[0:0]$14092 $2\core_core_spr1_ok$next[0:0]$14151 - assign $1\core_core_spro$next[9:0]$14093 $2\core_core_spro$next[9:0]$14152 - assign $1\core_core_xer_in$next[2:0]$14094 $2\core_core_xer_in$next[2:0]$14153 - assign $1\core_cr_out_ok$next[0:0]$14095 $2\core_cr_out_ok$next[0:0]$14154 - assign $1\core_ea_ok$next[0:0]$14096 $2\core_ea_ok$next[0:0]$14155 - assign $1\core_fasto1_ok$next[0:0]$14097 $2\core_fasto1_ok$next[0:0]$14156 - assign $1\core_fasto2_ok$next[0:0]$14098 $2\core_fasto2_ok$next[0:0]$14157 - assign $1\core_rego_ok$next[0:0]$14099 $2\core_rego_ok$next[0:0]$14158 - assign $1\core_spro_ok$next[0:0]$14100 $2\core_spro_ok$next[0:0]$14159 - assign $1\core_xer_out$next[0:0]$14101 $2\core_xer_out$next[0:0]$14160 + assign $1\core_asmcode$next[7:0]$14029 $2\core_asmcode$next[7:0]$14088 + assign $1\core_core_core_cia$next[63:0]$14030 $2\core_core_core_cia$next[63:0]$14089 + assign $1\core_core_core_cr_rd$next[7:0]$14031 $2\core_core_core_cr_rd$next[7:0]$14090 + assign $1\core_core_core_cr_rd_ok$next[0:0]$14032 $2\core_core_core_cr_rd_ok$next[0:0]$14091 + assign $1\core_core_core_cr_wr$next[7:0]$14033 $2\core_core_core_cr_wr$next[7:0]$14092 + assign $1\core_core_core_exc_$signal$3$next[0:0]$14034 $2\core_core_core_exc_$signal$3$next[0:0]$14093 + assign $1\core_core_core_exc_$signal$4$next[0:0]$14035 $2\core_core_core_exc_$signal$4$next[0:0]$14094 + assign $1\core_core_core_exc_$signal$5$next[0:0]$14036 $2\core_core_core_exc_$signal$5$next[0:0]$14095 + assign $1\core_core_core_exc_$signal$6$next[0:0]$14037 $2\core_core_core_exc_$signal$6$next[0:0]$14096 + assign $1\core_core_core_exc_$signal$7$next[0:0]$14038 $2\core_core_core_exc_$signal$7$next[0:0]$14097 + assign $1\core_core_core_exc_$signal$8$next[0:0]$14039 $2\core_core_core_exc_$signal$8$next[0:0]$14098 + assign $1\core_core_core_exc_$signal$9$next[0:0]$14040 $2\core_core_core_exc_$signal$9$next[0:0]$14099 + assign $1\core_core_core_exc_$signal$next[0:0]$14041 $2\core_core_core_exc_$signal$next[0:0]$14100 + assign $1\core_core_core_fn_unit$next[13:0]$14042 $2\core_core_core_fn_unit$next[13:0]$14101 + assign $1\core_core_core_input_carry$next[1:0]$14043 $2\core_core_core_input_carry$next[1:0]$14102 + assign $1\core_core_core_insn$next[31:0]$14044 $2\core_core_core_insn$next[31:0]$14103 + assign $1\core_core_core_insn_type$next[6:0]$14045 $2\core_core_core_insn_type$next[6:0]$14104 + assign $1\core_core_core_is_32bit$next[0:0]$14046 $2\core_core_core_is_32bit$next[0:0]$14105 + assign $1\core_core_core_msr$next[63:0]$14047 $2\core_core_core_msr$next[63:0]$14106 + assign $1\core_core_core_oe$next[0:0]$14048 $2\core_core_core_oe$next[0:0]$14107 + assign $1\core_core_core_oe_ok$next[0:0]$14049 $2\core_core_core_oe_ok$next[0:0]$14108 + assign $1\core_core_core_rc$next[0:0]$14050 $2\core_core_core_rc$next[0:0]$14109 + assign $1\core_core_core_rc_ok$next[0:0]$14051 $2\core_core_core_rc_ok$next[0:0]$14110 + assign $1\core_core_core_trapaddr$next[12:0]$14052 $2\core_core_core_trapaddr$next[12:0]$14111 + assign $1\core_core_core_traptype$next[7:0]$14053 $2\core_core_core_traptype$next[7:0]$14112 + assign $1\core_core_cr_in1$next[6:0]$14054 $2\core_core_cr_in1$next[6:0]$14113 + assign $1\core_core_cr_in1_ok$next[0:0]$14055 $2\core_core_cr_in1_ok$next[0:0]$14114 + assign $1\core_core_cr_in2$1$next[6:0]$14056 $2\core_core_cr_in2$1$next[6:0]$14115 + assign $1\core_core_cr_in2$next[6:0]$14057 $2\core_core_cr_in2$next[6:0]$14116 + assign $1\core_core_cr_in2_ok$2$next[0:0]$14058 $2\core_core_cr_in2_ok$2$next[0:0]$14117 + assign $1\core_core_cr_in2_ok$next[0:0]$14059 $2\core_core_cr_in2_ok$next[0:0]$14118 + assign $1\core_core_cr_out$next[6:0]$14060 $2\core_core_cr_out$next[6:0]$14119 + assign $1\core_core_cr_wr_ok$next[0:0]$14061 $2\core_core_cr_wr_ok$next[0:0]$14120 + assign $1\core_core_ea$next[6:0]$14062 $2\core_core_ea$next[6:0]$14121 + assign $1\core_core_fast1$next[2:0]$14063 $2\core_core_fast1$next[2:0]$14122 + assign $1\core_core_fast1_ok$next[0:0]$14064 $2\core_core_fast1_ok$next[0:0]$14123 + assign $1\core_core_fast2$next[2:0]$14065 $2\core_core_fast2$next[2:0]$14124 + assign $1\core_core_fast2_ok$next[0:0]$14066 $2\core_core_fast2_ok$next[0:0]$14125 + assign $1\core_core_fasto1$next[2:0]$14067 $2\core_core_fasto1$next[2:0]$14126 + assign $1\core_core_fasto2$next[2:0]$14068 $2\core_core_fasto2$next[2:0]$14127 + assign $1\core_core_lk$next[0:0]$14069 $2\core_core_lk$next[0:0]$14128 + assign $1\core_core_reg1$next[6:0]$14070 $2\core_core_reg1$next[6:0]$14129 + assign $1\core_core_reg1_ok$next[0:0]$14071 $2\core_core_reg1_ok$next[0:0]$14130 + assign $1\core_core_reg2$next[6:0]$14072 $2\core_core_reg2$next[6:0]$14131 + assign $1\core_core_reg2_ok$next[0:0]$14073 $2\core_core_reg2_ok$next[0:0]$14132 + assign $1\core_core_reg3$next[6:0]$14074 $2\core_core_reg3$next[6:0]$14133 + assign $1\core_core_reg3_ok$next[0:0]$14075 $2\core_core_reg3_ok$next[0:0]$14134 + assign $1\core_core_rego$next[6:0]$14076 $2\core_core_rego$next[6:0]$14135 + assign $1\core_core_spr1$next[9:0]$14077 $2\core_core_spr1$next[9:0]$14136 + assign $1\core_core_spr1_ok$next[0:0]$14078 $2\core_core_spr1_ok$next[0:0]$14137 + assign $1\core_core_spro$next[9:0]$14079 $2\core_core_spro$next[9:0]$14138 + assign $1\core_core_xer_in$next[2:0]$14080 $2\core_core_xer_in$next[2:0]$14139 + assign $1\core_cr_out_ok$next[0:0]$14081 $2\core_cr_out_ok$next[0:0]$14140 + assign $1\core_ea_ok$next[0:0]$14082 $2\core_ea_ok$next[0:0]$14141 + assign $1\core_fasto1_ok$next[0:0]$14083 $2\core_fasto1_ok$next[0:0]$14142 + assign $1\core_fasto2_ok$next[0:0]$14084 $2\core_fasto2_ok$next[0:0]$14143 + assign $1\core_rego_ok$next[0:0]$14085 $2\core_rego_ok$next[0:0]$14144 + assign $1\core_spro_ok$next[0:0]$14086 $2\core_spro_ok$next[0:0]$14145 + assign $1\core_xer_out$next[0:0]$14087 $2\core_xer_out$next[0:0]$14146 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:539" switch \fetch_insn_valid_o attribute \src "libresoc.v:0.0-0.0" @@ -411467,69 +384240,313 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $2\core_core_core_is_32bit$next[0:0]$14119 $2\core_core_cr_wr_ok$next[0:0]$14134 $2\core_core_core_cr_wr$next[7:0]$14106 $2\core_core_core_cr_rd_ok$next[0:0]$14105 $2\core_core_core_cr_rd$next[7:0]$14104 $2\core_core_core_trapaddr$next[12:0]$14125 $2\core_core_core_exc_$signal$9$next[0:0]$14113 $2\core_core_core_exc_$signal$8$next[0:0]$14112 $2\core_core_core_exc_$signal$7$next[0:0]$14111 $2\core_core_core_exc_$signal$6$next[0:0]$14110 $2\core_core_core_exc_$signal$5$next[0:0]$14109 $2\core_core_core_exc_$signal$4$next[0:0]$14108 $2\core_core_core_exc_$signal$3$next[0:0]$14107 $2\core_core_core_exc_$signal$next[0:0]$14114 $2\core_core_core_traptype$next[7:0]$14126 $2\core_core_core_input_carry$next[1:0]$14116 $2\core_core_core_oe_ok$next[0:0]$14122 $2\core_core_core_oe$next[0:0]$14121 $2\core_core_core_rc_ok$next[0:0]$14124 $2\core_core_core_rc$next[0:0]$14123 $2\core_core_lk$next[0:0]$14142 $2\core_core_core_fn_unit$next[13:0]$14115 $2\core_core_core_insn_type$next[6:0]$14118 $2\core_core_core_insn$next[31:0]$14117 $2\core_core_core_cia$next[63:0]$14103 $2\core_core_core_msr$next[63:0]$14120 $2\core_cr_out_ok$next[0:0]$14154 $2\core_core_cr_out$next[6:0]$14133 $2\core_core_cr_in2_ok$2$next[0:0]$14131 $2\core_core_cr_in2$1$next[6:0]$14129 $2\core_core_cr_in2_ok$next[0:0]$14132 $2\core_core_cr_in2$next[6:0]$14130 $2\core_core_cr_in1_ok$next[0:0]$14128 $2\core_core_cr_in1$next[6:0]$14127 $2\core_fasto2_ok$next[0:0]$14157 $2\core_core_fasto2$next[2:0]$14141 $2\core_fasto1_ok$next[0:0]$14156 $2\core_core_fasto1$next[2:0]$14140 $2\core_core_fast2_ok$next[0:0]$14139 $2\core_core_fast2$next[2:0]$14138 $2\core_core_fast1_ok$next[0:0]$14137 $2\core_core_fast1$next[2:0]$14136 $2\core_xer_out$next[0:0]$14160 $2\core_core_xer_in$next[2:0]$14153 $2\core_core_spr1_ok$next[0:0]$14151 $2\core_core_spr1$next[9:0]$14150 $2\core_spro_ok$next[0:0]$14159 $2\core_core_spro$next[9:0]$14152 $2\core_core_reg3_ok$next[0:0]$14148 $2\core_core_reg3$next[6:0]$14147 $2\core_core_reg2_ok$next[0:0]$14146 $2\core_core_reg2$next[6:0]$14145 $2\core_core_reg1_ok$next[0:0]$14144 $2\core_core_reg1$next[6:0]$14143 $2\core_ea_ok$next[0:0]$14155 $2\core_core_ea$next[6:0]$14135 $2\core_rego_ok$next[0:0]$14158 $2\core_core_rego$next[6:0]$14149 $2\core_asmcode$next[7:0]$14102 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } + assign { $2\core_core_core_is_32bit$next[0:0]$14105 $2\core_core_cr_wr_ok$next[0:0]$14120 $2\core_core_core_cr_wr$next[7:0]$14092 $2\core_core_core_cr_rd_ok$next[0:0]$14091 $2\core_core_core_cr_rd$next[7:0]$14090 $2\core_core_core_trapaddr$next[12:0]$14111 $2\core_core_core_exc_$signal$9$next[0:0]$14099 $2\core_core_core_exc_$signal$8$next[0:0]$14098 $2\core_core_core_exc_$signal$7$next[0:0]$14097 $2\core_core_core_exc_$signal$6$next[0:0]$14096 $2\core_core_core_exc_$signal$5$next[0:0]$14095 $2\core_core_core_exc_$signal$4$next[0:0]$14094 $2\core_core_core_exc_$signal$3$next[0:0]$14093 $2\core_core_core_exc_$signal$next[0:0]$14100 $2\core_core_core_traptype$next[7:0]$14112 $2\core_core_core_input_carry$next[1:0]$14102 $2\core_core_core_oe_ok$next[0:0]$14108 $2\core_core_core_oe$next[0:0]$14107 $2\core_core_core_rc_ok$next[0:0]$14110 $2\core_core_core_rc$next[0:0]$14109 $2\core_core_lk$next[0:0]$14128 $2\core_core_core_fn_unit$next[13:0]$14101 $2\core_core_core_insn_type$next[6:0]$14104 $2\core_core_core_insn$next[31:0]$14103 $2\core_core_core_cia$next[63:0]$14089 $2\core_core_core_msr$next[63:0]$14106 $2\core_cr_out_ok$next[0:0]$14140 $2\core_core_cr_out$next[6:0]$14119 $2\core_core_cr_in2_ok$2$next[0:0]$14117 $2\core_core_cr_in2$1$next[6:0]$14115 $2\core_core_cr_in2_ok$next[0:0]$14118 $2\core_core_cr_in2$next[6:0]$14116 $2\core_core_cr_in1_ok$next[0:0]$14114 $2\core_core_cr_in1$next[6:0]$14113 $2\core_fasto2_ok$next[0:0]$14143 $2\core_core_fasto2$next[2:0]$14127 $2\core_fasto1_ok$next[0:0]$14142 $2\core_core_fasto1$next[2:0]$14126 $2\core_core_fast2_ok$next[0:0]$14125 $2\core_core_fast2$next[2:0]$14124 $2\core_core_fast1_ok$next[0:0]$14123 $2\core_core_fast1$next[2:0]$14122 $2\core_xer_out$next[0:0]$14146 $2\core_core_xer_in$next[2:0]$14139 $2\core_core_spr1_ok$next[0:0]$14137 $2\core_core_spr1$next[9:0]$14136 $2\core_spro_ok$next[0:0]$14145 $2\core_core_spro$next[9:0]$14138 $2\core_core_reg3_ok$next[0:0]$14134 $2\core_core_reg3$next[6:0]$14133 $2\core_core_reg2_ok$next[0:0]$14132 $2\core_core_reg2$next[6:0]$14131 $2\core_core_reg1_ok$next[0:0]$14130 $2\core_core_reg1$next[6:0]$14129 $2\core_ea_ok$next[0:0]$14141 $2\core_core_ea$next[6:0]$14121 $2\core_rego_ok$next[0:0]$14144 $2\core_core_rego$next[6:0]$14135 $2\core_asmcode$next[7:0]$14088 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } case - assign $2\core_asmcode$next[7:0]$14102 \core_asmcode - assign $2\core_core_core_cia$next[63:0]$14103 \core_core_core_cia - assign $2\core_core_core_cr_rd$next[7:0]$14104 \core_core_core_cr_rd - assign $2\core_core_core_cr_rd_ok$next[0:0]$14105 \core_core_core_cr_rd_ok - assign $2\core_core_core_cr_wr$next[7:0]$14106 \core_core_core_cr_wr - assign $2\core_core_core_exc_$signal$3$next[0:0]$14107 \core_core_core_exc_$signal$3 - assign $2\core_core_core_exc_$signal$4$next[0:0]$14108 \core_core_core_exc_$signal$4 - assign $2\core_core_core_exc_$signal$5$next[0:0]$14109 \core_core_core_exc_$signal$5 - assign $2\core_core_core_exc_$signal$6$next[0:0]$14110 \core_core_core_exc_$signal$6 - assign $2\core_core_core_exc_$signal$7$next[0:0]$14111 \core_core_core_exc_$signal$7 - assign $2\core_core_core_exc_$signal$8$next[0:0]$14112 \core_core_core_exc_$signal$8 - assign $2\core_core_core_exc_$signal$9$next[0:0]$14113 \core_core_core_exc_$signal$9 - assign $2\core_core_core_exc_$signal$next[0:0]$14114 \core_core_core_exc_$signal - assign $2\core_core_core_fn_unit$next[13:0]$14115 \core_core_core_fn_unit - assign $2\core_core_core_input_carry$next[1:0]$14116 \core_core_core_input_carry - assign $2\core_core_core_insn$next[31:0]$14117 \core_core_core_insn - assign $2\core_core_core_insn_type$next[6:0]$14118 \core_core_core_insn_type - assign $2\core_core_core_is_32bit$next[0:0]$14119 \core_core_core_is_32bit - assign $2\core_core_core_msr$next[63:0]$14120 \core_core_core_msr - assign $2\core_core_core_oe$next[0:0]$14121 \core_core_core_oe - assign $2\core_core_core_oe_ok$next[0:0]$14122 \core_core_core_oe_ok - assign $2\core_core_core_rc$next[0:0]$14123 \core_core_core_rc - assign $2\core_core_core_rc_ok$next[0:0]$14124 \core_core_core_rc_ok - assign $2\core_core_core_trapaddr$next[12:0]$14125 \core_core_core_trapaddr - assign $2\core_core_core_traptype$next[7:0]$14126 \core_core_core_traptype - assign $2\core_core_cr_in1$next[6:0]$14127 \core_core_cr_in1 - assign $2\core_core_cr_in1_ok$next[0:0]$14128 \core_core_cr_in1_ok - assign $2\core_core_cr_in2$1$next[6:0]$14129 \core_core_cr_in2$1 - assign $2\core_core_cr_in2$next[6:0]$14130 \core_core_cr_in2 - assign $2\core_core_cr_in2_ok$2$next[0:0]$14131 \core_core_cr_in2_ok$2 - assign $2\core_core_cr_in2_ok$next[0:0]$14132 \core_core_cr_in2_ok - assign $2\core_core_cr_out$next[6:0]$14133 \core_core_cr_out - assign $2\core_core_cr_wr_ok$next[0:0]$14134 \core_core_cr_wr_ok - assign $2\core_core_ea$next[6:0]$14135 \core_core_ea - assign $2\core_core_fast1$next[2:0]$14136 \core_core_fast1 - assign $2\core_core_fast1_ok$next[0:0]$14137 \core_core_fast1_ok - assign $2\core_core_fast2$next[2:0]$14138 \core_core_fast2 - assign $2\core_core_fast2_ok$next[0:0]$14139 \core_core_fast2_ok - assign $2\core_core_fasto1$next[2:0]$14140 \core_core_fasto1 - assign $2\core_core_fasto2$next[2:0]$14141 \core_core_fasto2 - assign $2\core_core_lk$next[0:0]$14142 \core_core_lk - assign $2\core_core_reg1$next[6:0]$14143 \core_core_reg1 - assign $2\core_core_reg1_ok$next[0:0]$14144 \core_core_reg1_ok - assign $2\core_core_reg2$next[6:0]$14145 \core_core_reg2 - assign $2\core_core_reg2_ok$next[0:0]$14146 \core_core_reg2_ok - assign $2\core_core_reg3$next[6:0]$14147 \core_core_reg3 - assign $2\core_core_reg3_ok$next[0:0]$14148 \core_core_reg3_ok - assign $2\core_core_rego$next[6:0]$14149 \core_core_rego - assign $2\core_core_spr1$next[9:0]$14150 \core_core_spr1 - assign $2\core_core_spr1_ok$next[0:0]$14151 \core_core_spr1_ok - assign $2\core_core_spro$next[9:0]$14152 \core_core_spro - assign $2\core_core_xer_in$next[2:0]$14153 \core_core_xer_in - assign $2\core_cr_out_ok$next[0:0]$14154 \core_cr_out_ok - assign $2\core_ea_ok$next[0:0]$14155 \core_ea_ok - assign $2\core_fasto1_ok$next[0:0]$14156 \core_fasto1_ok - assign $2\core_fasto2_ok$next[0:0]$14157 \core_fasto2_ok - assign $2\core_rego_ok$next[0:0]$14158 \core_rego_ok - assign $2\core_spro_ok$next[0:0]$14159 \core_spro_ok - assign $2\core_xer_out$next[0:0]$14160 \core_xer_out + assign $2\core_asmcode$next[7:0]$14088 \core_asmcode + assign $2\core_core_core_cia$next[63:0]$14089 \core_core_core_cia + assign $2\core_core_core_cr_rd$next[7:0]$14090 \core_core_core_cr_rd + assign $2\core_core_core_cr_rd_ok$next[0:0]$14091 \core_core_core_cr_rd_ok + assign $2\core_core_core_cr_wr$next[7:0]$14092 \core_core_core_cr_wr + assign $2\core_core_core_exc_$signal$3$next[0:0]$14093 \core_core_core_exc_$signal$3 + assign $2\core_core_core_exc_$signal$4$next[0:0]$14094 \core_core_core_exc_$signal$4 + assign $2\core_core_core_exc_$signal$5$next[0:0]$14095 \core_core_core_exc_$signal$5 + assign $2\core_core_core_exc_$signal$6$next[0:0]$14096 \core_core_core_exc_$signal$6 + assign $2\core_core_core_exc_$signal$7$next[0:0]$14097 \core_core_core_exc_$signal$7 + assign $2\core_core_core_exc_$signal$8$next[0:0]$14098 \core_core_core_exc_$signal$8 + assign $2\core_core_core_exc_$signal$9$next[0:0]$14099 \core_core_core_exc_$signal$9 + assign $2\core_core_core_exc_$signal$next[0:0]$14100 \core_core_core_exc_$signal + assign $2\core_core_core_fn_unit$next[13:0]$14101 \core_core_core_fn_unit + assign $2\core_core_core_input_carry$next[1:0]$14102 \core_core_core_input_carry + assign $2\core_core_core_insn$next[31:0]$14103 \core_core_core_insn + assign $2\core_core_core_insn_type$next[6:0]$14104 \core_core_core_insn_type + assign $2\core_core_core_is_32bit$next[0:0]$14105 \core_core_core_is_32bit + assign $2\core_core_core_msr$next[63:0]$14106 \core_core_core_msr + assign $2\core_core_core_oe$next[0:0]$14107 \core_core_core_oe + assign $2\core_core_core_oe_ok$next[0:0]$14108 \core_core_core_oe_ok + assign $2\core_core_core_rc$next[0:0]$14109 \core_core_core_rc + assign $2\core_core_core_rc_ok$next[0:0]$14110 \core_core_core_rc_ok + assign $2\core_core_core_trapaddr$next[12:0]$14111 \core_core_core_trapaddr + assign $2\core_core_core_traptype$next[7:0]$14112 \core_core_core_traptype + assign $2\core_core_cr_in1$next[6:0]$14113 \core_core_cr_in1 + assign $2\core_core_cr_in1_ok$next[0:0]$14114 \core_core_cr_in1_ok + assign $2\core_core_cr_in2$1$next[6:0]$14115 \core_core_cr_in2$1 + assign $2\core_core_cr_in2$next[6:0]$14116 \core_core_cr_in2 + assign $2\core_core_cr_in2_ok$2$next[0:0]$14117 \core_core_cr_in2_ok$2 + assign $2\core_core_cr_in2_ok$next[0:0]$14118 \core_core_cr_in2_ok + assign $2\core_core_cr_out$next[6:0]$14119 \core_core_cr_out + assign $2\core_core_cr_wr_ok$next[0:0]$14120 \core_core_cr_wr_ok + assign $2\core_core_ea$next[6:0]$14121 \core_core_ea + assign $2\core_core_fast1$next[2:0]$14122 \core_core_fast1 + assign $2\core_core_fast1_ok$next[0:0]$14123 \core_core_fast1_ok + assign $2\core_core_fast2$next[2:0]$14124 \core_core_fast2 + assign $2\core_core_fast2_ok$next[0:0]$14125 \core_core_fast2_ok + assign $2\core_core_fasto1$next[2:0]$14126 \core_core_fasto1 + assign $2\core_core_fasto2$next[2:0]$14127 \core_core_fasto2 + assign $2\core_core_lk$next[0:0]$14128 \core_core_lk + assign $2\core_core_reg1$next[6:0]$14129 \core_core_reg1 + assign $2\core_core_reg1_ok$next[0:0]$14130 \core_core_reg1_ok + assign $2\core_core_reg2$next[6:0]$14131 \core_core_reg2 + assign $2\core_core_reg2_ok$next[0:0]$14132 \core_core_reg2_ok + assign $2\core_core_reg3$next[6:0]$14133 \core_core_reg3 + assign $2\core_core_reg3_ok$next[0:0]$14134 \core_core_reg3_ok + assign $2\core_core_rego$next[6:0]$14135 \core_core_rego + assign $2\core_core_spr1$next[9:0]$14136 \core_core_spr1 + assign $2\core_core_spr1_ok$next[0:0]$14137 \core_core_spr1_ok + assign $2\core_core_spro$next[9:0]$14138 \core_core_spro + assign $2\core_core_xer_in$next[2:0]$14139 \core_core_xer_in + assign $2\core_cr_out_ok$next[0:0]$14140 \core_cr_out_ok + assign $2\core_ea_ok$next[0:0]$14141 \core_ea_ok + assign $2\core_fasto1_ok$next[0:0]$14142 \core_fasto1_ok + assign $2\core_fasto2_ok$next[0:0]$14143 \core_fasto2_ok + assign $2\core_rego_ok$next[0:0]$14144 \core_rego_ok + assign $2\core_spro_ok$next[0:0]$14145 \core_spro_ok + assign $2\core_xer_out$next[0:0]$14146 \core_xer_out end attribute \src "libresoc.v:0.0-0.0" + case 3'011 + assign $1\core_asmcode$next[7:0]$14029 \core_asmcode + assign $1\core_core_core_cia$next[63:0]$14030 \core_core_core_cia + assign $1\core_core_core_cr_rd$next[7:0]$14031 \core_core_core_cr_rd + assign $1\core_core_core_cr_rd_ok$next[0:0]$14032 \core_core_core_cr_rd_ok + assign $1\core_core_core_cr_wr$next[7:0]$14033 \core_core_core_cr_wr + assign $1\core_core_core_exc_$signal$3$next[0:0]$14034 \core_core_core_exc_$signal$3 + assign $1\core_core_core_exc_$signal$4$next[0:0]$14035 \core_core_core_exc_$signal$4 + assign $1\core_core_core_exc_$signal$5$next[0:0]$14036 \core_core_core_exc_$signal$5 + assign $1\core_core_core_exc_$signal$6$next[0:0]$14037 \core_core_core_exc_$signal$6 + assign $1\core_core_core_exc_$signal$7$next[0:0]$14038 \core_core_core_exc_$signal$7 + assign $1\core_core_core_exc_$signal$8$next[0:0]$14039 \core_core_core_exc_$signal$8 + assign $1\core_core_core_exc_$signal$9$next[0:0]$14040 \core_core_core_exc_$signal$9 + assign $1\core_core_core_exc_$signal$next[0:0]$14041 \core_core_core_exc_$signal + assign $1\core_core_core_fn_unit$next[13:0]$14042 \core_core_core_fn_unit + assign $1\core_core_core_input_carry$next[1:0]$14043 \core_core_core_input_carry + assign $1\core_core_core_insn$next[31:0]$14044 \core_core_core_insn + assign $1\core_core_core_insn_type$next[6:0]$14045 \core_core_core_insn_type + assign $1\core_core_core_is_32bit$next[0:0]$14046 \core_core_core_is_32bit + assign $1\core_core_core_msr$next[63:0]$14047 \core_core_core_msr + assign $1\core_core_core_oe$next[0:0]$14048 \core_core_core_oe + assign $1\core_core_core_oe_ok$next[0:0]$14049 \core_core_core_oe_ok + assign $1\core_core_core_rc$next[0:0]$14050 \core_core_core_rc + assign $1\core_core_core_rc_ok$next[0:0]$14051 \core_core_core_rc_ok + assign $1\core_core_core_trapaddr$next[12:0]$14052 \core_core_core_trapaddr + assign $1\core_core_core_traptype$next[7:0]$14053 \core_core_core_traptype + assign $1\core_core_cr_in1$next[6:0]$14054 \core_core_cr_in1 + assign $1\core_core_cr_in1_ok$next[0:0]$14055 \core_core_cr_in1_ok + assign $1\core_core_cr_in2$1$next[6:0]$14056 \core_core_cr_in2$1 + assign $1\core_core_cr_in2$next[6:0]$14057 \core_core_cr_in2 + assign $1\core_core_cr_in2_ok$2$next[0:0]$14058 \core_core_cr_in2_ok$2 + assign $1\core_core_cr_in2_ok$next[0:0]$14059 \core_core_cr_in2_ok + assign $1\core_core_cr_out$next[6:0]$14060 \core_core_cr_out + assign $1\core_core_cr_wr_ok$next[0:0]$14061 \core_core_cr_wr_ok + assign $1\core_core_ea$next[6:0]$14062 \core_core_ea + assign $1\core_core_fast1$next[2:0]$14063 \core_core_fast1 + assign $1\core_core_fast1_ok$next[0:0]$14064 \core_core_fast1_ok + assign $1\core_core_fast2$next[2:0]$14065 \core_core_fast2 + assign $1\core_core_fast2_ok$next[0:0]$14066 \core_core_fast2_ok + assign $1\core_core_fasto1$next[2:0]$14067 \core_core_fasto1 + assign $1\core_core_fasto2$next[2:0]$14068 \core_core_fasto2 + assign $1\core_core_lk$next[0:0]$14069 \core_core_lk + assign $1\core_core_reg1$next[6:0]$14070 \core_core_reg1 + assign $1\core_core_reg1_ok$next[0:0]$14071 \core_core_reg1_ok + assign $1\core_core_reg2$next[6:0]$14072 \core_core_reg2 + assign $1\core_core_reg2_ok$next[0:0]$14073 \core_core_reg2_ok + assign $1\core_core_reg3$next[6:0]$14074 \core_core_reg3 + assign $1\core_core_reg3_ok$next[0:0]$14075 \core_core_reg3_ok + assign $1\core_core_rego$next[6:0]$14076 \core_core_rego + assign $1\core_core_spr1$next[9:0]$14077 \core_core_spr1 + assign $1\core_core_spr1_ok$next[0:0]$14078 \core_core_spr1_ok + assign $1\core_core_spro$next[9:0]$14079 \core_core_spro + assign $1\core_core_xer_in$next[2:0]$14080 \core_core_xer_in + assign $1\core_cr_out_ok$next[0:0]$14081 \core_cr_out_ok + assign $1\core_ea_ok$next[0:0]$14082 \core_ea_ok + assign $1\core_fasto1_ok$next[0:0]$14083 \core_fasto1_ok + assign $1\core_fasto2_ok$next[0:0]$14084 \core_fasto2_ok + assign $1\core_rego_ok$next[0:0]$14085 \core_rego_ok + assign $1\core_spro_ok$next[0:0]$14086 \core_spro_ok + assign $1\core_xer_out$next[0:0]$14087 \core_xer_out + attribute \src "libresoc.v:0.0-0.0" + case 3'100 + assign $1\core_asmcode$next[7:0]$14029 \core_asmcode + assign $1\core_core_core_cia$next[63:0]$14030 \core_core_core_cia + assign $1\core_core_core_cr_rd$next[7:0]$14031 \core_core_core_cr_rd + assign $1\core_core_core_cr_rd_ok$next[0:0]$14032 \core_core_core_cr_rd_ok + assign $1\core_core_core_cr_wr$next[7:0]$14033 \core_core_core_cr_wr + assign $1\core_core_core_exc_$signal$3$next[0:0]$14034 \core_core_core_exc_$signal$3 + assign $1\core_core_core_exc_$signal$4$next[0:0]$14035 \core_core_core_exc_$signal$4 + assign $1\core_core_core_exc_$signal$5$next[0:0]$14036 \core_core_core_exc_$signal$5 + assign $1\core_core_core_exc_$signal$6$next[0:0]$14037 \core_core_core_exc_$signal$6 + assign $1\core_core_core_exc_$signal$7$next[0:0]$14038 \core_core_core_exc_$signal$7 + assign $1\core_core_core_exc_$signal$8$next[0:0]$14039 \core_core_core_exc_$signal$8 + assign $1\core_core_core_exc_$signal$9$next[0:0]$14040 \core_core_core_exc_$signal$9 + assign $1\core_core_core_exc_$signal$next[0:0]$14041 \core_core_core_exc_$signal + assign $1\core_core_core_fn_unit$next[13:0]$14042 \core_core_core_fn_unit + assign $1\core_core_core_input_carry$next[1:0]$14043 \core_core_core_input_carry + assign $1\core_core_core_insn$next[31:0]$14044 \core_core_core_insn + assign $1\core_core_core_insn_type$next[6:0]$14045 \core_core_core_insn_type + assign $1\core_core_core_is_32bit$next[0:0]$14046 \core_core_core_is_32bit + assign $1\core_core_core_msr$next[63:0]$14047 \core_core_core_msr + assign $1\core_core_core_oe$next[0:0]$14048 \core_core_core_oe + assign $1\core_core_core_oe_ok$next[0:0]$14049 \core_core_core_oe_ok + assign $1\core_core_core_rc$next[0:0]$14050 \core_core_core_rc + assign $1\core_core_core_rc_ok$next[0:0]$14051 \core_core_core_rc_ok + assign $1\core_core_core_trapaddr$next[12:0]$14052 \core_core_core_trapaddr + assign $1\core_core_core_traptype$next[7:0]$14053 \core_core_core_traptype + assign $1\core_core_cr_in1$next[6:0]$14054 \core_core_cr_in1 + assign $1\core_core_cr_in1_ok$next[0:0]$14055 \core_core_cr_in1_ok + assign $1\core_core_cr_in2$1$next[6:0]$14056 \core_core_cr_in2$1 + assign $1\core_core_cr_in2$next[6:0]$14057 \core_core_cr_in2 + assign $1\core_core_cr_in2_ok$2$next[0:0]$14058 \core_core_cr_in2_ok$2 + assign $1\core_core_cr_in2_ok$next[0:0]$14059 \core_core_cr_in2_ok + assign $1\core_core_cr_out$next[6:0]$14060 \core_core_cr_out + assign $1\core_core_cr_wr_ok$next[0:0]$14061 \core_core_cr_wr_ok + assign $1\core_core_ea$next[6:0]$14062 \core_core_ea + assign $1\core_core_fast1$next[2:0]$14063 \core_core_fast1 + assign $1\core_core_fast1_ok$next[0:0]$14064 \core_core_fast1_ok + assign $1\core_core_fast2$next[2:0]$14065 \core_core_fast2 + assign $1\core_core_fast2_ok$next[0:0]$14066 \core_core_fast2_ok + assign $1\core_core_fasto1$next[2:0]$14067 \core_core_fasto1 + assign $1\core_core_fasto2$next[2:0]$14068 \core_core_fasto2 + assign $1\core_core_lk$next[0:0]$14069 \core_core_lk + assign $1\core_core_reg1$next[6:0]$14070 \core_core_reg1 + assign $1\core_core_reg1_ok$next[0:0]$14071 \core_core_reg1_ok + assign $1\core_core_reg2$next[6:0]$14072 \core_core_reg2 + assign $1\core_core_reg2_ok$next[0:0]$14073 \core_core_reg2_ok + assign $1\core_core_reg3$next[6:0]$14074 \core_core_reg3 + assign $1\core_core_reg3_ok$next[0:0]$14075 \core_core_reg3_ok + assign $1\core_core_rego$next[6:0]$14076 \core_core_rego + assign $1\core_core_spr1$next[9:0]$14077 \core_core_spr1 + assign $1\core_core_spr1_ok$next[0:0]$14078 \core_core_spr1_ok + assign $1\core_core_spro$next[9:0]$14079 \core_core_spro + assign $1\core_core_xer_in$next[2:0]$14080 \core_core_xer_in + assign $1\core_cr_out_ok$next[0:0]$14081 \core_cr_out_ok + assign $1\core_ea_ok$next[0:0]$14082 \core_ea_ok + assign $1\core_fasto1_ok$next[0:0]$14083 \core_fasto1_ok + assign $1\core_fasto2_ok$next[0:0]$14084 \core_fasto2_ok + assign $1\core_rego_ok$next[0:0]$14085 \core_rego_ok + assign $1\core_spro_ok$next[0:0]$14086 \core_spro_ok + assign $1\core_xer_out$next[0:0]$14087 \core_xer_out + attribute \src "libresoc.v:0.0-0.0" + case 3'010 + assign $1\core_asmcode$next[7:0]$14029 \core_asmcode + assign $1\core_core_core_cia$next[63:0]$14030 \core_core_core_cia + assign $1\core_core_core_cr_rd$next[7:0]$14031 \core_core_core_cr_rd + assign $1\core_core_core_cr_rd_ok$next[0:0]$14032 \core_core_core_cr_rd_ok + assign $1\core_core_core_cr_wr$next[7:0]$14033 \core_core_core_cr_wr + assign $1\core_core_core_exc_$signal$3$next[0:0]$14034 \core_core_core_exc_$signal$3 + assign $1\core_core_core_exc_$signal$4$next[0:0]$14035 \core_core_core_exc_$signal$4 + assign $1\core_core_core_exc_$signal$5$next[0:0]$14036 \core_core_core_exc_$signal$5 + assign $1\core_core_core_exc_$signal$6$next[0:0]$14037 \core_core_core_exc_$signal$6 + assign $1\core_core_core_exc_$signal$7$next[0:0]$14038 \core_core_core_exc_$signal$7 + assign $1\core_core_core_exc_$signal$8$next[0:0]$14039 \core_core_core_exc_$signal$8 + assign $1\core_core_core_exc_$signal$9$next[0:0]$14040 \core_core_core_exc_$signal$9 + assign $1\core_core_core_exc_$signal$next[0:0]$14041 \core_core_core_exc_$signal + assign $1\core_core_core_fn_unit$next[13:0]$14042 \core_core_core_fn_unit + assign $1\core_core_core_input_carry$next[1:0]$14043 \core_core_core_input_carry + assign $1\core_core_core_insn$next[31:0]$14044 \core_core_core_insn + assign $1\core_core_core_insn_type$next[6:0]$14045 \core_core_core_insn_type + assign $1\core_core_core_is_32bit$next[0:0]$14046 \core_core_core_is_32bit + assign $1\core_core_core_msr$next[63:0]$14047 \core_core_core_msr + assign $1\core_core_core_oe$next[0:0]$14048 \core_core_core_oe + assign $1\core_core_core_oe_ok$next[0:0]$14049 \core_core_core_oe_ok + assign $1\core_core_core_rc$next[0:0]$14050 \core_core_core_rc + assign $1\core_core_core_rc_ok$next[0:0]$14051 \core_core_core_rc_ok + assign $1\core_core_core_trapaddr$next[12:0]$14052 \core_core_core_trapaddr + assign $1\core_core_core_traptype$next[7:0]$14053 \core_core_core_traptype + assign $1\core_core_cr_in1$next[6:0]$14054 \core_core_cr_in1 + assign $1\core_core_cr_in1_ok$next[0:0]$14055 \core_core_cr_in1_ok + assign $1\core_core_cr_in2$1$next[6:0]$14056 \core_core_cr_in2$1 + assign $1\core_core_cr_in2$next[6:0]$14057 \core_core_cr_in2 + assign $1\core_core_cr_in2_ok$2$next[0:0]$14058 \core_core_cr_in2_ok$2 + assign $1\core_core_cr_in2_ok$next[0:0]$14059 \core_core_cr_in2_ok + assign $1\core_core_cr_out$next[6:0]$14060 \core_core_cr_out + assign $1\core_core_cr_wr_ok$next[0:0]$14061 \core_core_cr_wr_ok + assign $1\core_core_ea$next[6:0]$14062 \core_core_ea + assign $1\core_core_fast1$next[2:0]$14063 \core_core_fast1 + assign $1\core_core_fast1_ok$next[0:0]$14064 \core_core_fast1_ok + assign $1\core_core_fast2$next[2:0]$14065 \core_core_fast2 + assign $1\core_core_fast2_ok$next[0:0]$14066 \core_core_fast2_ok + assign $1\core_core_fasto1$next[2:0]$14067 \core_core_fasto1 + assign $1\core_core_fasto2$next[2:0]$14068 \core_core_fasto2 + assign $1\core_core_lk$next[0:0]$14069 \core_core_lk + assign $1\core_core_reg1$next[6:0]$14070 \core_core_reg1 + assign $1\core_core_reg1_ok$next[0:0]$14071 \core_core_reg1_ok + assign $1\core_core_reg2$next[6:0]$14072 \core_core_reg2 + assign $1\core_core_reg2_ok$next[0:0]$14073 \core_core_reg2_ok + assign $1\core_core_reg3$next[6:0]$14074 \core_core_reg3 + assign $1\core_core_reg3_ok$next[0:0]$14075 \core_core_reg3_ok + assign $1\core_core_rego$next[6:0]$14076 \core_core_rego + assign $1\core_core_spr1$next[9:0]$14077 \core_core_spr1 + assign $1\core_core_spr1_ok$next[0:0]$14078 \core_core_spr1_ok + assign $1\core_core_spro$next[9:0]$14079 \core_core_spro + assign $1\core_core_xer_in$next[2:0]$14080 \core_core_xer_in + assign $1\core_cr_out_ok$next[0:0]$14081 \core_cr_out_ok + assign $1\core_ea_ok$next[0:0]$14082 \core_ea_ok + assign $1\core_fasto1_ok$next[0:0]$14083 \core_fasto1_ok + assign $1\core_fasto2_ok$next[0:0]$14084 \core_fasto2_ok + assign $1\core_rego_ok$next[0:0]$14085 \core_rego_ok + assign $1\core_spro_ok$next[0:0]$14086 \core_spro_ok + assign $1\core_xer_out$next[0:0]$14087 \core_xer_out + attribute \src "libresoc.v:0.0-0.0" + case 3'101 + assign $1\core_asmcode$next[7:0]$14029 \core_asmcode + assign $1\core_core_core_cia$next[63:0]$14030 \core_core_core_cia + assign $1\core_core_core_cr_rd$next[7:0]$14031 \core_core_core_cr_rd + assign $1\core_core_core_cr_rd_ok$next[0:0]$14032 \core_core_core_cr_rd_ok + assign $1\core_core_core_cr_wr$next[7:0]$14033 \core_core_core_cr_wr + assign $1\core_core_core_exc_$signal$3$next[0:0]$14034 \core_core_core_exc_$signal$3 + assign $1\core_core_core_exc_$signal$4$next[0:0]$14035 \core_core_core_exc_$signal$4 + assign $1\core_core_core_exc_$signal$5$next[0:0]$14036 \core_core_core_exc_$signal$5 + assign $1\core_core_core_exc_$signal$6$next[0:0]$14037 \core_core_core_exc_$signal$6 + assign $1\core_core_core_exc_$signal$7$next[0:0]$14038 \core_core_core_exc_$signal$7 + assign $1\core_core_core_exc_$signal$8$next[0:0]$14039 \core_core_core_exc_$signal$8 + assign $1\core_core_core_exc_$signal$9$next[0:0]$14040 \core_core_core_exc_$signal$9 + assign $1\core_core_core_exc_$signal$next[0:0]$14041 \core_core_core_exc_$signal + assign $1\core_core_core_fn_unit$next[13:0]$14042 \core_core_core_fn_unit + assign $1\core_core_core_input_carry$next[1:0]$14043 \core_core_core_input_carry + assign $1\core_core_core_insn$next[31:0]$14044 \core_core_core_insn + assign $1\core_core_core_insn_type$next[6:0]$14045 \core_core_core_insn_type + assign $1\core_core_core_is_32bit$next[0:0]$14046 \core_core_core_is_32bit + assign $1\core_core_core_msr$next[63:0]$14047 \core_core_core_msr + assign $1\core_core_core_oe$next[0:0]$14048 \core_core_core_oe + assign $1\core_core_core_oe_ok$next[0:0]$14049 \core_core_core_oe_ok + assign $1\core_core_core_rc$next[0:0]$14050 \core_core_core_rc + assign $1\core_core_core_rc_ok$next[0:0]$14051 \core_core_core_rc_ok + assign $1\core_core_core_trapaddr$next[12:0]$14052 \core_core_core_trapaddr + assign $1\core_core_core_traptype$next[7:0]$14053 \core_core_core_traptype + assign $1\core_core_cr_in1$next[6:0]$14054 \core_core_cr_in1 + assign $1\core_core_cr_in1_ok$next[0:0]$14055 \core_core_cr_in1_ok + assign $1\core_core_cr_in2$1$next[6:0]$14056 \core_core_cr_in2$1 + assign $1\core_core_cr_in2$next[6:0]$14057 \core_core_cr_in2 + assign $1\core_core_cr_in2_ok$2$next[0:0]$14058 \core_core_cr_in2_ok$2 + assign $1\core_core_cr_in2_ok$next[0:0]$14059 \core_core_cr_in2_ok + assign $1\core_core_cr_out$next[6:0]$14060 \core_core_cr_out + assign $1\core_core_cr_wr_ok$next[0:0]$14061 \core_core_cr_wr_ok + assign $1\core_core_ea$next[6:0]$14062 \core_core_ea + assign $1\core_core_fast1$next[2:0]$14063 \core_core_fast1 + assign $1\core_core_fast1_ok$next[0:0]$14064 \core_core_fast1_ok + assign $1\core_core_fast2$next[2:0]$14065 \core_core_fast2 + assign $1\core_core_fast2_ok$next[0:0]$14066 \core_core_fast2_ok + assign $1\core_core_fasto1$next[2:0]$14067 \core_core_fasto1 + assign $1\core_core_fasto2$next[2:0]$14068 \core_core_fasto2 + assign $1\core_core_lk$next[0:0]$14069 \core_core_lk + assign $1\core_core_reg1$next[6:0]$14070 \core_core_reg1 + assign $1\core_core_reg1_ok$next[0:0]$14071 \core_core_reg1_ok + assign $1\core_core_reg2$next[6:0]$14072 \core_core_reg2 + assign $1\core_core_reg2_ok$next[0:0]$14073 \core_core_reg2_ok + assign $1\core_core_reg3$next[6:0]$14074 \core_core_reg3 + assign $1\core_core_reg3_ok$next[0:0]$14075 \core_core_reg3_ok + assign $1\core_core_rego$next[6:0]$14076 \core_core_rego + assign $1\core_core_spr1$next[9:0]$14077 \core_core_spr1 + assign $1\core_core_spr1_ok$next[0:0]$14078 \core_core_spr1_ok + assign $1\core_core_spro$next[9:0]$14079 \core_core_spro + assign $1\core_core_xer_in$next[2:0]$14080 \core_core_xer_in + assign $1\core_cr_out_ok$next[0:0]$14081 \core_cr_out_ok + assign $1\core_ea_ok$next[0:0]$14082 \core_ea_ok + assign $1\core_fasto1_ok$next[0:0]$14083 \core_fasto1_ok + assign $1\core_fasto2_ok$next[0:0]$14084 \core_fasto2_ok + assign $1\core_rego_ok$next[0:0]$14085 \core_rego_ok + assign $1\core_spro_ok$next[0:0]$14086 \core_spro_ok + assign $1\core_xer_out$next[0:0]$14087 \core_xer_out + attribute \src "libresoc.v:0.0-0.0" case 3'110 assign { } { } assign { } { } @@ -411590,67 +384607,67 @@ module \ti assign { } { } assign { } { } assign { } { } - assign { $1\core_core_core_is_32bit$next[0:0]$14060 $1\core_core_cr_wr_ok$next[0:0]$14075 $1\core_core_core_cr_wr$next[7:0]$14047 $1\core_core_core_cr_rd_ok$next[0:0]$14046 $1\core_core_core_cr_rd$next[7:0]$14045 $1\core_core_core_trapaddr$next[12:0]$14066 $1\core_core_core_exc_$signal$9$next[0:0]$14054 $1\core_core_core_exc_$signal$8$next[0:0]$14053 $1\core_core_core_exc_$signal$7$next[0:0]$14052 $1\core_core_core_exc_$signal$6$next[0:0]$14051 $1\core_core_core_exc_$signal$5$next[0:0]$14050 $1\core_core_core_exc_$signal$4$next[0:0]$14049 $1\core_core_core_exc_$signal$3$next[0:0]$14048 $1\core_core_core_exc_$signal$next[0:0]$14055 $1\core_core_core_traptype$next[7:0]$14067 $1\core_core_core_input_carry$next[1:0]$14057 $1\core_core_core_oe_ok$next[0:0]$14063 $1\core_core_core_oe$next[0:0]$14062 $1\core_core_core_rc_ok$next[0:0]$14065 $1\core_core_core_rc$next[0:0]$14064 $1\core_core_lk$next[0:0]$14083 $1\core_core_core_fn_unit$next[13:0]$14056 $1\core_core_core_insn_type$next[6:0]$14059 $1\core_core_core_insn$next[31:0]$14058 $1\core_core_core_cia$next[63:0]$14044 $1\core_core_core_msr$next[63:0]$14061 $1\core_cr_out_ok$next[0:0]$14095 $1\core_core_cr_out$next[6:0]$14074 $1\core_core_cr_in2_ok$2$next[0:0]$14072 $1\core_core_cr_in2$1$next[6:0]$14070 $1\core_core_cr_in2_ok$next[0:0]$14073 $1\core_core_cr_in2$next[6:0]$14071 $1\core_core_cr_in1_ok$next[0:0]$14069 $1\core_core_cr_in1$next[6:0]$14068 $1\core_fasto2_ok$next[0:0]$14098 $1\core_core_fasto2$next[2:0]$14082 $1\core_fasto1_ok$next[0:0]$14097 $1\core_core_fasto1$next[2:0]$14081 $1\core_core_fast2_ok$next[0:0]$14080 $1\core_core_fast2$next[2:0]$14079 $1\core_core_fast1_ok$next[0:0]$14078 $1\core_core_fast1$next[2:0]$14077 $1\core_xer_out$next[0:0]$14101 $1\core_core_xer_in$next[2:0]$14094 $1\core_core_spr1_ok$next[0:0]$14092 $1\core_core_spr1$next[9:0]$14091 $1\core_spro_ok$next[0:0]$14100 $1\core_core_spro$next[9:0]$14093 $1\core_core_reg3_ok$next[0:0]$14089 $1\core_core_reg3$next[6:0]$14088 $1\core_core_reg2_ok$next[0:0]$14087 $1\core_core_reg2$next[6:0]$14086 $1\core_core_reg1_ok$next[0:0]$14085 $1\core_core_reg1$next[6:0]$14084 $1\core_ea_ok$next[0:0]$14096 $1\core_core_ea$next[6:0]$14076 $1\core_rego_ok$next[0:0]$14099 $1\core_core_rego$next[6:0]$14090 $1\core_asmcode$next[7:0]$14043 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } + assign { $1\core_core_core_is_32bit$next[0:0]$14046 $1\core_core_cr_wr_ok$next[0:0]$14061 $1\core_core_core_cr_wr$next[7:0]$14033 $1\core_core_core_cr_rd_ok$next[0:0]$14032 $1\core_core_core_cr_rd$next[7:0]$14031 $1\core_core_core_trapaddr$next[12:0]$14052 $1\core_core_core_exc_$signal$9$next[0:0]$14040 $1\core_core_core_exc_$signal$8$next[0:0]$14039 $1\core_core_core_exc_$signal$7$next[0:0]$14038 $1\core_core_core_exc_$signal$6$next[0:0]$14037 $1\core_core_core_exc_$signal$5$next[0:0]$14036 $1\core_core_core_exc_$signal$4$next[0:0]$14035 $1\core_core_core_exc_$signal$3$next[0:0]$14034 $1\core_core_core_exc_$signal$next[0:0]$14041 $1\core_core_core_traptype$next[7:0]$14053 $1\core_core_core_input_carry$next[1:0]$14043 $1\core_core_core_oe_ok$next[0:0]$14049 $1\core_core_core_oe$next[0:0]$14048 $1\core_core_core_rc_ok$next[0:0]$14051 $1\core_core_core_rc$next[0:0]$14050 $1\core_core_lk$next[0:0]$14069 $1\core_core_core_fn_unit$next[13:0]$14042 $1\core_core_core_insn_type$next[6:0]$14045 $1\core_core_core_insn$next[31:0]$14044 $1\core_core_core_cia$next[63:0]$14030 $1\core_core_core_msr$next[63:0]$14047 $1\core_cr_out_ok$next[0:0]$14081 $1\core_core_cr_out$next[6:0]$14060 $1\core_core_cr_in2_ok$2$next[0:0]$14058 $1\core_core_cr_in2$1$next[6:0]$14056 $1\core_core_cr_in2_ok$next[0:0]$14059 $1\core_core_cr_in2$next[6:0]$14057 $1\core_core_cr_in1_ok$next[0:0]$14055 $1\core_core_cr_in1$next[6:0]$14054 $1\core_fasto2_ok$next[0:0]$14084 $1\core_core_fasto2$next[2:0]$14068 $1\core_fasto1_ok$next[0:0]$14083 $1\core_core_fasto1$next[2:0]$14067 $1\core_core_fast2_ok$next[0:0]$14066 $1\core_core_fast2$next[2:0]$14065 $1\core_core_fast1_ok$next[0:0]$14064 $1\core_core_fast1$next[2:0]$14063 $1\core_xer_out$next[0:0]$14087 $1\core_core_xer_in$next[2:0]$14080 $1\core_core_spr1_ok$next[0:0]$14078 $1\core_core_spr1$next[9:0]$14077 $1\core_spro_ok$next[0:0]$14086 $1\core_core_spro$next[9:0]$14079 $1\core_core_reg3_ok$next[0:0]$14075 $1\core_core_reg3$next[6:0]$14074 $1\core_core_reg2_ok$next[0:0]$14073 $1\core_core_reg2$next[6:0]$14072 $1\core_core_reg1_ok$next[0:0]$14071 $1\core_core_reg1$next[6:0]$14070 $1\core_ea_ok$next[0:0]$14082 $1\core_core_ea$next[6:0]$14062 $1\core_rego_ok$next[0:0]$14085 $1\core_core_rego$next[6:0]$14076 $1\core_asmcode$next[7:0]$14029 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_exc_$signal$22 \dec2_exc_$signal$21 \dec2_exc_$signal$20 \dec2_exc_$signal$19 \dec2_exc_$signal$18 \dec2_exc_$signal$17 \dec2_exc_$signal$16 \dec2_exc_$signal \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$15 \dec2_cr_in2$14 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } case - assign $1\core_asmcode$next[7:0]$14043 \core_asmcode - assign $1\core_core_core_cia$next[63:0]$14044 \core_core_core_cia - assign $1\core_core_core_cr_rd$next[7:0]$14045 \core_core_core_cr_rd - assign $1\core_core_core_cr_rd_ok$next[0:0]$14046 \core_core_core_cr_rd_ok - assign $1\core_core_core_cr_wr$next[7:0]$14047 \core_core_core_cr_wr - assign $1\core_core_core_exc_$signal$3$next[0:0]$14048 \core_core_core_exc_$signal$3 - assign $1\core_core_core_exc_$signal$4$next[0:0]$14049 \core_core_core_exc_$signal$4 - assign $1\core_core_core_exc_$signal$5$next[0:0]$14050 \core_core_core_exc_$signal$5 - assign $1\core_core_core_exc_$signal$6$next[0:0]$14051 \core_core_core_exc_$signal$6 - assign $1\core_core_core_exc_$signal$7$next[0:0]$14052 \core_core_core_exc_$signal$7 - assign $1\core_core_core_exc_$signal$8$next[0:0]$14053 \core_core_core_exc_$signal$8 - assign $1\core_core_core_exc_$signal$9$next[0:0]$14054 \core_core_core_exc_$signal$9 - assign $1\core_core_core_exc_$signal$next[0:0]$14055 \core_core_core_exc_$signal - assign $1\core_core_core_fn_unit$next[13:0]$14056 \core_core_core_fn_unit - assign $1\core_core_core_input_carry$next[1:0]$14057 \core_core_core_input_carry - assign $1\core_core_core_insn$next[31:0]$14058 \core_core_core_insn - assign $1\core_core_core_insn_type$next[6:0]$14059 \core_core_core_insn_type - assign $1\core_core_core_is_32bit$next[0:0]$14060 \core_core_core_is_32bit - assign $1\core_core_core_msr$next[63:0]$14061 \core_core_core_msr - assign $1\core_core_core_oe$next[0:0]$14062 \core_core_core_oe - assign $1\core_core_core_oe_ok$next[0:0]$14063 \core_core_core_oe_ok - assign $1\core_core_core_rc$next[0:0]$14064 \core_core_core_rc - assign $1\core_core_core_rc_ok$next[0:0]$14065 \core_core_core_rc_ok - assign $1\core_core_core_trapaddr$next[12:0]$14066 \core_core_core_trapaddr - assign $1\core_core_core_traptype$next[7:0]$14067 \core_core_core_traptype - assign $1\core_core_cr_in1$next[6:0]$14068 \core_core_cr_in1 - assign $1\core_core_cr_in1_ok$next[0:0]$14069 \core_core_cr_in1_ok - assign $1\core_core_cr_in2$1$next[6:0]$14070 \core_core_cr_in2$1 - assign $1\core_core_cr_in2$next[6:0]$14071 \core_core_cr_in2 - assign $1\core_core_cr_in2_ok$2$next[0:0]$14072 \core_core_cr_in2_ok$2 - assign $1\core_core_cr_in2_ok$next[0:0]$14073 \core_core_cr_in2_ok - assign $1\core_core_cr_out$next[6:0]$14074 \core_core_cr_out - assign $1\core_core_cr_wr_ok$next[0:0]$14075 \core_core_cr_wr_ok - assign $1\core_core_ea$next[6:0]$14076 \core_core_ea - assign $1\core_core_fast1$next[2:0]$14077 \core_core_fast1 - assign $1\core_core_fast1_ok$next[0:0]$14078 \core_core_fast1_ok - assign $1\core_core_fast2$next[2:0]$14079 \core_core_fast2 - assign $1\core_core_fast2_ok$next[0:0]$14080 \core_core_fast2_ok - assign $1\core_core_fasto1$next[2:0]$14081 \core_core_fasto1 - assign $1\core_core_fasto2$next[2:0]$14082 \core_core_fasto2 - assign $1\core_core_lk$next[0:0]$14083 \core_core_lk - assign $1\core_core_reg1$next[6:0]$14084 \core_core_reg1 - assign $1\core_core_reg1_ok$next[0:0]$14085 \core_core_reg1_ok - assign $1\core_core_reg2$next[6:0]$14086 \core_core_reg2 - assign $1\core_core_reg2_ok$next[0:0]$14087 \core_core_reg2_ok - assign $1\core_core_reg3$next[6:0]$14088 \core_core_reg3 - assign $1\core_core_reg3_ok$next[0:0]$14089 \core_core_reg3_ok - assign $1\core_core_rego$next[6:0]$14090 \core_core_rego - assign $1\core_core_spr1$next[9:0]$14091 \core_core_spr1 - assign $1\core_core_spr1_ok$next[0:0]$14092 \core_core_spr1_ok - assign $1\core_core_spro$next[9:0]$14093 \core_core_spro - assign $1\core_core_xer_in$next[2:0]$14094 \core_core_xer_in - assign $1\core_cr_out_ok$next[0:0]$14095 \core_cr_out_ok - assign $1\core_ea_ok$next[0:0]$14096 \core_ea_ok - assign $1\core_fasto1_ok$next[0:0]$14097 \core_fasto1_ok - assign $1\core_fasto2_ok$next[0:0]$14098 \core_fasto2_ok - assign $1\core_rego_ok$next[0:0]$14099 \core_rego_ok - assign $1\core_spro_ok$next[0:0]$14100 \core_spro_ok - assign $1\core_xer_out$next[0:0]$14101 \core_xer_out + assign $1\core_asmcode$next[7:0]$14029 \core_asmcode + assign $1\core_core_core_cia$next[63:0]$14030 \core_core_core_cia + assign $1\core_core_core_cr_rd$next[7:0]$14031 \core_core_core_cr_rd + assign $1\core_core_core_cr_rd_ok$next[0:0]$14032 \core_core_core_cr_rd_ok + assign $1\core_core_core_cr_wr$next[7:0]$14033 \core_core_core_cr_wr + assign $1\core_core_core_exc_$signal$3$next[0:0]$14034 \core_core_core_exc_$signal$3 + assign $1\core_core_core_exc_$signal$4$next[0:0]$14035 \core_core_core_exc_$signal$4 + assign $1\core_core_core_exc_$signal$5$next[0:0]$14036 \core_core_core_exc_$signal$5 + assign $1\core_core_core_exc_$signal$6$next[0:0]$14037 \core_core_core_exc_$signal$6 + assign $1\core_core_core_exc_$signal$7$next[0:0]$14038 \core_core_core_exc_$signal$7 + assign $1\core_core_core_exc_$signal$8$next[0:0]$14039 \core_core_core_exc_$signal$8 + assign $1\core_core_core_exc_$signal$9$next[0:0]$14040 \core_core_core_exc_$signal$9 + assign $1\core_core_core_exc_$signal$next[0:0]$14041 \core_core_core_exc_$signal + assign $1\core_core_core_fn_unit$next[13:0]$14042 \core_core_core_fn_unit + assign $1\core_core_core_input_carry$next[1:0]$14043 \core_core_core_input_carry + assign $1\core_core_core_insn$next[31:0]$14044 \core_core_core_insn + assign $1\core_core_core_insn_type$next[6:0]$14045 \core_core_core_insn_type + assign $1\core_core_core_is_32bit$next[0:0]$14046 \core_core_core_is_32bit + assign $1\core_core_core_msr$next[63:0]$14047 \core_core_core_msr + assign $1\core_core_core_oe$next[0:0]$14048 \core_core_core_oe + assign $1\core_core_core_oe_ok$next[0:0]$14049 \core_core_core_oe_ok + assign $1\core_core_core_rc$next[0:0]$14050 \core_core_core_rc + assign $1\core_core_core_rc_ok$next[0:0]$14051 \core_core_core_rc_ok + assign $1\core_core_core_trapaddr$next[12:0]$14052 \core_core_core_trapaddr + assign $1\core_core_core_traptype$next[7:0]$14053 \core_core_core_traptype + assign $1\core_core_cr_in1$next[6:0]$14054 \core_core_cr_in1 + assign $1\core_core_cr_in1_ok$next[0:0]$14055 \core_core_cr_in1_ok + assign $1\core_core_cr_in2$1$next[6:0]$14056 \core_core_cr_in2$1 + assign $1\core_core_cr_in2$next[6:0]$14057 \core_core_cr_in2 + assign $1\core_core_cr_in2_ok$2$next[0:0]$14058 \core_core_cr_in2_ok$2 + assign $1\core_core_cr_in2_ok$next[0:0]$14059 \core_core_cr_in2_ok + assign $1\core_core_cr_out$next[6:0]$14060 \core_core_cr_out + assign $1\core_core_cr_wr_ok$next[0:0]$14061 \core_core_cr_wr_ok + assign $1\core_core_ea$next[6:0]$14062 \core_core_ea + assign $1\core_core_fast1$next[2:0]$14063 \core_core_fast1 + assign $1\core_core_fast1_ok$next[0:0]$14064 \core_core_fast1_ok + assign $1\core_core_fast2$next[2:0]$14065 \core_core_fast2 + assign $1\core_core_fast2_ok$next[0:0]$14066 \core_core_fast2_ok + assign $1\core_core_fasto1$next[2:0]$14067 \core_core_fasto1 + assign $1\core_core_fasto2$next[2:0]$14068 \core_core_fasto2 + assign $1\core_core_lk$next[0:0]$14069 \core_core_lk + assign $1\core_core_reg1$next[6:0]$14070 \core_core_reg1 + assign $1\core_core_reg1_ok$next[0:0]$14071 \core_core_reg1_ok + assign $1\core_core_reg2$next[6:0]$14072 \core_core_reg2 + assign $1\core_core_reg2_ok$next[0:0]$14073 \core_core_reg2_ok + assign $1\core_core_reg3$next[6:0]$14074 \core_core_reg3 + assign $1\core_core_reg3_ok$next[0:0]$14075 \core_core_reg3_ok + assign $1\core_core_rego$next[6:0]$14076 \core_core_rego + assign $1\core_core_spr1$next[9:0]$14077 \core_core_spr1 + assign $1\core_core_spr1_ok$next[0:0]$14078 \core_core_spr1_ok + assign $1\core_core_spro$next[9:0]$14079 \core_core_spro + assign $1\core_core_xer_in$next[2:0]$14080 \core_core_xer_in + assign $1\core_cr_out_ok$next[0:0]$14081 \core_cr_out_ok + assign $1\core_ea_ok$next[0:0]$14082 \core_ea_ok + assign $1\core_fasto1_ok$next[0:0]$14083 \core_fasto1_ok + assign $1\core_fasto2_ok$next[0:0]$14084 \core_fasto2_ok + assign $1\core_rego_ok$next[0:0]$14085 \core_rego_ok + assign $1\core_spro_ok$next[0:0]$14086 \core_spro_ok + assign $1\core_xer_out$next[0:0]$14087 \core_xer_out end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -411683,131 +384700,131 @@ module \ti assign { } { } assign { } { } assign { } { } - assign $3\core_rego_ok$next[0:0]$14186 1'0 - assign $3\core_ea_ok$next[0:0]$14183 1'0 - assign $3\core_core_reg1_ok$next[0:0]$14178 1'0 - assign $3\core_core_reg2_ok$next[0:0]$14179 1'0 - assign $3\core_core_reg3_ok$next[0:0]$14180 1'0 - assign $3\core_spro_ok$next[0:0]$14187 1'0 - assign $3\core_core_spr1_ok$next[0:0]$14181 1'0 - assign $3\core_core_fast1_ok$next[0:0]$14176 1'0 - assign $3\core_core_fast2_ok$next[0:0]$14177 1'0 - assign $3\core_fasto1_ok$next[0:0]$14184 1'0 - assign $3\core_fasto2_ok$next[0:0]$14185 1'0 - assign $3\core_core_cr_in1_ok$next[0:0]$14172 1'0 - assign $3\core_core_cr_in2_ok$next[0:0]$14174 1'0 - assign $3\core_core_cr_in2_ok$2$next[0:0]$14173 1'0 - assign $3\core_cr_out_ok$next[0:0]$14182 1'0 - assign $3\core_core_core_rc_ok$next[0:0]$14171 1'0 - assign $3\core_core_core_oe_ok$next[0:0]$14170 1'0 - assign $3\core_core_core_exc_$signal$next[0:0]$14169 1'0 - assign $3\core_core_core_exc_$signal$3$next[0:0]$14162 1'0 - assign $3\core_core_core_exc_$signal$4$next[0:0]$14163 1'0 - assign $3\core_core_core_exc_$signal$5$next[0:0]$14164 1'0 - assign $3\core_core_core_exc_$signal$6$next[0:0]$14165 1'0 - assign $3\core_core_core_exc_$signal$7$next[0:0]$14166 1'0 - assign $3\core_core_core_exc_$signal$8$next[0:0]$14167 1'0 - assign $3\core_core_core_exc_$signal$9$next[0:0]$14168 1'0 - assign $3\core_core_core_cr_rd_ok$next[0:0]$14161 1'0 - assign $3\core_core_cr_wr_ok$next[0:0]$14175 1'0 + assign $3\core_rego_ok$next[0:0]$14172 1'0 + assign $3\core_ea_ok$next[0:0]$14169 1'0 + assign $3\core_core_reg1_ok$next[0:0]$14164 1'0 + assign $3\core_core_reg2_ok$next[0:0]$14165 1'0 + assign $3\core_core_reg3_ok$next[0:0]$14166 1'0 + assign $3\core_spro_ok$next[0:0]$14173 1'0 + assign $3\core_core_spr1_ok$next[0:0]$14167 1'0 + assign $3\core_core_fast1_ok$next[0:0]$14162 1'0 + assign $3\core_core_fast2_ok$next[0:0]$14163 1'0 + assign $3\core_fasto1_ok$next[0:0]$14170 1'0 + assign $3\core_fasto2_ok$next[0:0]$14171 1'0 + assign $3\core_core_cr_in1_ok$next[0:0]$14158 1'0 + assign $3\core_core_cr_in2_ok$next[0:0]$14160 1'0 + assign $3\core_core_cr_in2_ok$2$next[0:0]$14159 1'0 + assign $3\core_cr_out_ok$next[0:0]$14168 1'0 + assign $3\core_core_core_rc_ok$next[0:0]$14157 1'0 + assign $3\core_core_core_oe_ok$next[0:0]$14156 1'0 + assign $3\core_core_core_exc_$signal$next[0:0]$14155 1'0 + assign $3\core_core_core_exc_$signal$3$next[0:0]$14148 1'0 + assign $3\core_core_core_exc_$signal$4$next[0:0]$14149 1'0 + assign $3\core_core_core_exc_$signal$5$next[0:0]$14150 1'0 + assign $3\core_core_core_exc_$signal$6$next[0:0]$14151 1'0 + assign $3\core_core_core_exc_$signal$7$next[0:0]$14152 1'0 + assign $3\core_core_core_exc_$signal$8$next[0:0]$14153 1'0 + assign $3\core_core_core_exc_$signal$9$next[0:0]$14154 1'0 + assign $3\core_core_core_cr_rd_ok$next[0:0]$14147 1'0 + assign $3\core_core_cr_wr_ok$next[0:0]$14161 1'0 case - assign $3\core_core_core_cr_rd_ok$next[0:0]$14161 $1\core_core_core_cr_rd_ok$next[0:0]$14046 - assign $3\core_core_core_exc_$signal$3$next[0:0]$14162 $1\core_core_core_exc_$signal$3$next[0:0]$14048 - assign $3\core_core_core_exc_$signal$4$next[0:0]$14163 $1\core_core_core_exc_$signal$4$next[0:0]$14049 - assign $3\core_core_core_exc_$signal$5$next[0:0]$14164 $1\core_core_core_exc_$signal$5$next[0:0]$14050 - assign $3\core_core_core_exc_$signal$6$next[0:0]$14165 $1\core_core_core_exc_$signal$6$next[0:0]$14051 - assign $3\core_core_core_exc_$signal$7$next[0:0]$14166 $1\core_core_core_exc_$signal$7$next[0:0]$14052 - assign $3\core_core_core_exc_$signal$8$next[0:0]$14167 $1\core_core_core_exc_$signal$8$next[0:0]$14053 - assign $3\core_core_core_exc_$signal$9$next[0:0]$14168 $1\core_core_core_exc_$signal$9$next[0:0]$14054 - assign $3\core_core_core_exc_$signal$next[0:0]$14169 $1\core_core_core_exc_$signal$next[0:0]$14055 - assign $3\core_core_core_oe_ok$next[0:0]$14170 $1\core_core_core_oe_ok$next[0:0]$14063 - assign $3\core_core_core_rc_ok$next[0:0]$14171 $1\core_core_core_rc_ok$next[0:0]$14065 - assign $3\core_core_cr_in1_ok$next[0:0]$14172 $1\core_core_cr_in1_ok$next[0:0]$14069 - assign $3\core_core_cr_in2_ok$2$next[0:0]$14173 $1\core_core_cr_in2_ok$2$next[0:0]$14072 - assign $3\core_core_cr_in2_ok$next[0:0]$14174 $1\core_core_cr_in2_ok$next[0:0]$14073 - assign $3\core_core_cr_wr_ok$next[0:0]$14175 $1\core_core_cr_wr_ok$next[0:0]$14075 - assign $3\core_core_fast1_ok$next[0:0]$14176 $1\core_core_fast1_ok$next[0:0]$14078 - assign $3\core_core_fast2_ok$next[0:0]$14177 $1\core_core_fast2_ok$next[0:0]$14080 - assign $3\core_core_reg1_ok$next[0:0]$14178 $1\core_core_reg1_ok$next[0:0]$14085 - assign $3\core_core_reg2_ok$next[0:0]$14179 $1\core_core_reg2_ok$next[0:0]$14087 - assign $3\core_core_reg3_ok$next[0:0]$14180 $1\core_core_reg3_ok$next[0:0]$14089 - assign $3\core_core_spr1_ok$next[0:0]$14181 $1\core_core_spr1_ok$next[0:0]$14092 - assign $3\core_cr_out_ok$next[0:0]$14182 $1\core_cr_out_ok$next[0:0]$14095 - assign $3\core_ea_ok$next[0:0]$14183 $1\core_ea_ok$next[0:0]$14096 - assign $3\core_fasto1_ok$next[0:0]$14184 $1\core_fasto1_ok$next[0:0]$14097 - assign $3\core_fasto2_ok$next[0:0]$14185 $1\core_fasto2_ok$next[0:0]$14098 - assign $3\core_rego_ok$next[0:0]$14186 $1\core_rego_ok$next[0:0]$14099 - assign $3\core_spro_ok$next[0:0]$14187 $1\core_spro_ok$next[0:0]$14100 + assign $3\core_core_core_cr_rd_ok$next[0:0]$14147 $1\core_core_core_cr_rd_ok$next[0:0]$14032 + assign $3\core_core_core_exc_$signal$3$next[0:0]$14148 $1\core_core_core_exc_$signal$3$next[0:0]$14034 + assign $3\core_core_core_exc_$signal$4$next[0:0]$14149 $1\core_core_core_exc_$signal$4$next[0:0]$14035 + assign $3\core_core_core_exc_$signal$5$next[0:0]$14150 $1\core_core_core_exc_$signal$5$next[0:0]$14036 + assign $3\core_core_core_exc_$signal$6$next[0:0]$14151 $1\core_core_core_exc_$signal$6$next[0:0]$14037 + assign $3\core_core_core_exc_$signal$7$next[0:0]$14152 $1\core_core_core_exc_$signal$7$next[0:0]$14038 + assign $3\core_core_core_exc_$signal$8$next[0:0]$14153 $1\core_core_core_exc_$signal$8$next[0:0]$14039 + assign $3\core_core_core_exc_$signal$9$next[0:0]$14154 $1\core_core_core_exc_$signal$9$next[0:0]$14040 + assign $3\core_core_core_exc_$signal$next[0:0]$14155 $1\core_core_core_exc_$signal$next[0:0]$14041 + assign $3\core_core_core_oe_ok$next[0:0]$14156 $1\core_core_core_oe_ok$next[0:0]$14049 + assign $3\core_core_core_rc_ok$next[0:0]$14157 $1\core_core_core_rc_ok$next[0:0]$14051 + assign $3\core_core_cr_in1_ok$next[0:0]$14158 $1\core_core_cr_in1_ok$next[0:0]$14055 + assign $3\core_core_cr_in2_ok$2$next[0:0]$14159 $1\core_core_cr_in2_ok$2$next[0:0]$14058 + assign $3\core_core_cr_in2_ok$next[0:0]$14160 $1\core_core_cr_in2_ok$next[0:0]$14059 + assign $3\core_core_cr_wr_ok$next[0:0]$14161 $1\core_core_cr_wr_ok$next[0:0]$14061 + assign $3\core_core_fast1_ok$next[0:0]$14162 $1\core_core_fast1_ok$next[0:0]$14064 + assign $3\core_core_fast2_ok$next[0:0]$14163 $1\core_core_fast2_ok$next[0:0]$14066 + assign $3\core_core_reg1_ok$next[0:0]$14164 $1\core_core_reg1_ok$next[0:0]$14071 + assign $3\core_core_reg2_ok$next[0:0]$14165 $1\core_core_reg2_ok$next[0:0]$14073 + assign $3\core_core_reg3_ok$next[0:0]$14166 $1\core_core_reg3_ok$next[0:0]$14075 + assign $3\core_core_spr1_ok$next[0:0]$14167 $1\core_core_spr1_ok$next[0:0]$14078 + assign $3\core_cr_out_ok$next[0:0]$14168 $1\core_cr_out_ok$next[0:0]$14081 + assign $3\core_ea_ok$next[0:0]$14169 $1\core_ea_ok$next[0:0]$14082 + assign $3\core_fasto1_ok$next[0:0]$14170 $1\core_fasto1_ok$next[0:0]$14083 + assign $3\core_fasto2_ok$next[0:0]$14171 $1\core_fasto2_ok$next[0:0]$14084 + assign $3\core_rego_ok$next[0:0]$14172 $1\core_rego_ok$next[0:0]$14085 + assign $3\core_spro_ok$next[0:0]$14173 $1\core_spro_ok$next[0:0]$14086 end sync always - update \core_asmcode$next $0\core_asmcode$next[7:0]$13984 - update \core_core_core_cia$next $0\core_core_core_cia$next[63:0]$13985 - update \core_core_core_cr_rd$next $0\core_core_core_cr_rd$next[7:0]$13986 - update \core_core_core_cr_rd_ok$next $0\core_core_core_cr_rd_ok$next[0:0]$13987 - update \core_core_core_cr_wr$next $0\core_core_core_cr_wr$next[7:0]$13988 - update \core_core_core_exc_$signal$3$next $0\core_core_core_exc_$signal$3$next[0:0]$13989 - update \core_core_core_exc_$signal$4$next $0\core_core_core_exc_$signal$4$next[0:0]$13990 - update \core_core_core_exc_$signal$5$next $0\core_core_core_exc_$signal$5$next[0:0]$13991 - update \core_core_core_exc_$signal$6$next $0\core_core_core_exc_$signal$6$next[0:0]$13992 - update \core_core_core_exc_$signal$7$next $0\core_core_core_exc_$signal$7$next[0:0]$13993 - update \core_core_core_exc_$signal$8$next $0\core_core_core_exc_$signal$8$next[0:0]$13994 - update \core_core_core_exc_$signal$9$next $0\core_core_core_exc_$signal$9$next[0:0]$13995 - update \core_core_core_exc_$signal$next $0\core_core_core_exc_$signal$next[0:0]$13996 - update \core_core_core_fn_unit$next $0\core_core_core_fn_unit$next[13:0]$13997 - update \core_core_core_input_carry$next $0\core_core_core_input_carry$next[1:0]$13998 - update \core_core_core_insn$next $0\core_core_core_insn$next[31:0]$13999 - update \core_core_core_insn_type$next $0\core_core_core_insn_type$next[6:0]$14000 - update \core_core_core_is_32bit$next $0\core_core_core_is_32bit$next[0:0]$14001 - update \core_core_core_msr$next $0\core_core_core_msr$next[63:0]$14002 - update \core_core_core_oe$next $0\core_core_core_oe$next[0:0]$14003 - update \core_core_core_oe_ok$next $0\core_core_core_oe_ok$next[0:0]$14004 - update \core_core_core_rc$next $0\core_core_core_rc$next[0:0]$14005 - update \core_core_core_rc_ok$next $0\core_core_core_rc_ok$next[0:0]$14006 - update \core_core_core_trapaddr$next $0\core_core_core_trapaddr$next[12:0]$14007 - update \core_core_core_traptype$next $0\core_core_core_traptype$next[7:0]$14008 - update \core_core_cr_in1$next $0\core_core_cr_in1$next[6:0]$14009 - update \core_core_cr_in1_ok$next $0\core_core_cr_in1_ok$next[0:0]$14010 - update \core_core_cr_in2$1$next $0\core_core_cr_in2$1$next[6:0]$14011 - update \core_core_cr_in2$next $0\core_core_cr_in2$next[6:0]$14012 - update \core_core_cr_in2_ok$2$next $0\core_core_cr_in2_ok$2$next[0:0]$14013 - update \core_core_cr_in2_ok$next $0\core_core_cr_in2_ok$next[0:0]$14014 - update \core_core_cr_out$next $0\core_core_cr_out$next[6:0]$14015 - update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$14016 - update \core_core_ea$next $0\core_core_ea$next[6:0]$14017 - update \core_core_fast1$next $0\core_core_fast1$next[2:0]$14018 - update \core_core_fast1_ok$next $0\core_core_fast1_ok$next[0:0]$14019 - update \core_core_fast2$next $0\core_core_fast2$next[2:0]$14020 - update \core_core_fast2_ok$next $0\core_core_fast2_ok$next[0:0]$14021 - update \core_core_fasto1$next $0\core_core_fasto1$next[2:0]$14022 - update \core_core_fasto2$next $0\core_core_fasto2$next[2:0]$14023 - update \core_core_lk$next $0\core_core_lk$next[0:0]$14024 - update \core_core_reg1$next $0\core_core_reg1$next[6:0]$14025 - update \core_core_reg1_ok$next $0\core_core_reg1_ok$next[0:0]$14026 - update \core_core_reg2$next $0\core_core_reg2$next[6:0]$14027 - update \core_core_reg2_ok$next $0\core_core_reg2_ok$next[0:0]$14028 - update \core_core_reg3$next $0\core_core_reg3$next[6:0]$14029 - update \core_core_reg3_ok$next $0\core_core_reg3_ok$next[0:0]$14030 - update \core_core_rego$next $0\core_core_rego$next[6:0]$14031 - update \core_core_spr1$next $0\core_core_spr1$next[9:0]$14032 - update \core_core_spr1_ok$next $0\core_core_spr1_ok$next[0:0]$14033 - update \core_core_spro$next $0\core_core_spro$next[9:0]$14034 - update \core_core_xer_in$next $0\core_core_xer_in$next[2:0]$14035 - update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$14036 - update \core_ea_ok$next $0\core_ea_ok$next[0:0]$14037 - update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$14038 - update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$14039 - update \core_rego_ok$next $0\core_rego_ok$next[0:0]$14040 - update \core_spro_ok$next $0\core_spro_ok$next[0:0]$14041 - update \core_xer_out$next $0\core_xer_out$next[0:0]$14042 - end - attribute \src "libresoc.v:198997.3-199005.6" - process $proc$libresoc.v:198997$14188 - assign { } { } - assign { } { } - assign $0\dec2_cur_eint$next[0:0]$14189 $1\dec2_cur_eint$next[0:0]$14190 - attribute \src "libresoc.v:198998.5-198998.29" - switch \initial - attribute \src "libresoc.v:198998.9-198998.17" + update \core_asmcode$next $0\core_asmcode$next[7:0]$13970 + update \core_core_core_cia$next $0\core_core_core_cia$next[63:0]$13971 + update \core_core_core_cr_rd$next $0\core_core_core_cr_rd$next[7:0]$13972 + update \core_core_core_cr_rd_ok$next $0\core_core_core_cr_rd_ok$next[0:0]$13973 + update \core_core_core_cr_wr$next $0\core_core_core_cr_wr$next[7:0]$13974 + update \core_core_core_exc_$signal$3$next $0\core_core_core_exc_$signal$3$next[0:0]$13975 + update \core_core_core_exc_$signal$4$next $0\core_core_core_exc_$signal$4$next[0:0]$13976 + update \core_core_core_exc_$signal$5$next $0\core_core_core_exc_$signal$5$next[0:0]$13977 + update \core_core_core_exc_$signal$6$next $0\core_core_core_exc_$signal$6$next[0:0]$13978 + update \core_core_core_exc_$signal$7$next $0\core_core_core_exc_$signal$7$next[0:0]$13979 + update \core_core_core_exc_$signal$8$next $0\core_core_core_exc_$signal$8$next[0:0]$13980 + update \core_core_core_exc_$signal$9$next $0\core_core_core_exc_$signal$9$next[0:0]$13981 + update \core_core_core_exc_$signal$next $0\core_core_core_exc_$signal$next[0:0]$13982 + update \core_core_core_fn_unit$next $0\core_core_core_fn_unit$next[13:0]$13983 + update \core_core_core_input_carry$next $0\core_core_core_input_carry$next[1:0]$13984 + update \core_core_core_insn$next $0\core_core_core_insn$next[31:0]$13985 + update \core_core_core_insn_type$next $0\core_core_core_insn_type$next[6:0]$13986 + update \core_core_core_is_32bit$next $0\core_core_core_is_32bit$next[0:0]$13987 + update \core_core_core_msr$next $0\core_core_core_msr$next[63:0]$13988 + update \core_core_core_oe$next $0\core_core_core_oe$next[0:0]$13989 + update \core_core_core_oe_ok$next $0\core_core_core_oe_ok$next[0:0]$13990 + update \core_core_core_rc$next $0\core_core_core_rc$next[0:0]$13991 + update \core_core_core_rc_ok$next $0\core_core_core_rc_ok$next[0:0]$13992 + update \core_core_core_trapaddr$next $0\core_core_core_trapaddr$next[12:0]$13993 + update \core_core_core_traptype$next $0\core_core_core_traptype$next[7:0]$13994 + update \core_core_cr_in1$next $0\core_core_cr_in1$next[6:0]$13995 + update \core_core_cr_in1_ok$next $0\core_core_cr_in1_ok$next[0:0]$13996 + update \core_core_cr_in2$1$next $0\core_core_cr_in2$1$next[6:0]$13997 + update \core_core_cr_in2$next $0\core_core_cr_in2$next[6:0]$13998 + update \core_core_cr_in2_ok$2$next $0\core_core_cr_in2_ok$2$next[0:0]$13999 + update \core_core_cr_in2_ok$next $0\core_core_cr_in2_ok$next[0:0]$14000 + update \core_core_cr_out$next $0\core_core_cr_out$next[6:0]$14001 + update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$14002 + update \core_core_ea$next $0\core_core_ea$next[6:0]$14003 + update \core_core_fast1$next $0\core_core_fast1$next[2:0]$14004 + update \core_core_fast1_ok$next $0\core_core_fast1_ok$next[0:0]$14005 + update \core_core_fast2$next $0\core_core_fast2$next[2:0]$14006 + update \core_core_fast2_ok$next $0\core_core_fast2_ok$next[0:0]$14007 + update \core_core_fasto1$next $0\core_core_fasto1$next[2:0]$14008 + update \core_core_fasto2$next $0\core_core_fasto2$next[2:0]$14009 + update \core_core_lk$next $0\core_core_lk$next[0:0]$14010 + update \core_core_reg1$next $0\core_core_reg1$next[6:0]$14011 + update \core_core_reg1_ok$next $0\core_core_reg1_ok$next[0:0]$14012 + update \core_core_reg2$next $0\core_core_reg2$next[6:0]$14013 + update \core_core_reg2_ok$next $0\core_core_reg2_ok$next[0:0]$14014 + update \core_core_reg3$next $0\core_core_reg3$next[6:0]$14015 + update \core_core_reg3_ok$next $0\core_core_reg3_ok$next[0:0]$14016 + update \core_core_rego$next $0\core_core_rego$next[6:0]$14017 + update \core_core_spr1$next $0\core_core_spr1$next[9:0]$14018 + update \core_core_spr1_ok$next $0\core_core_spr1_ok$next[0:0]$14019 + update \core_core_spro$next $0\core_core_spro$next[9:0]$14020 + update \core_core_xer_in$next $0\core_core_xer_in$next[2:0]$14021 + update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$14022 + update \core_ea_ok$next $0\core_ea_ok$next[0:0]$14023 + update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$14024 + update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$14025 + update \core_rego_ok$next $0\core_rego_ok$next[0:0]$14026 + update \core_spro_ok$next $0\core_spro_ok$next[0:0]$14027 + update \core_xer_out$next $0\core_xer_out$next[0:0]$14028 + end + attribute \src "libresoc.v:201686.3-201694.6" + process $proc$libresoc.v:201686$14174 + assign { } { } + assign { } { } + assign $0\dec2_cur_eint$next[0:0]$14175 $1\dec2_cur_eint$next[0:0]$14176 + attribute \src "libresoc.v:201687.5-201687.29" + switch \initial + attribute \src "libresoc.v:201687.9-201687.17" case 1'1 case end @@ -411816,156 +384833,156 @@ module \ti attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\dec2_cur_eint$next[0:0]$14190 1'0 + assign $1\dec2_cur_eint$next[0:0]$14176 1'0 case - assign $1\dec2_cur_eint$next[0:0]$14190 \xics_icp_core_irq_o + assign $1\dec2_cur_eint$next[0:0]$14176 \xics_icp_core_irq_o end sync always - update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$14189 + update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$14175 end - attribute \src "libresoc.v:199006.3-199015.6" - process $proc$libresoc.v:199006$14191 + attribute \src "libresoc.v:201695.3-201704.6" + process $proc$libresoc.v:201695$14177 assign { } { } assign { } { } - assign $0\delay$next[1:0]$14192 $1\delay$next[1:0]$14193 - attribute \src "libresoc.v:199007.5-199007.29" + assign $0\delay$next[1:0]$14178 $1\delay$next[1:0]$14179 + attribute \src "libresoc.v:201696.5-201696.29" switch \initial - attribute \src "libresoc.v:199007.9-199007.17" + attribute \src "libresoc.v:201696.9-201696.17" case 1'1 case end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:791" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:792" switch \$23 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\delay$next[1:0]$14193 \$25 [1:0] + assign $1\delay$next[1:0]$14179 \$25 [1:0] case - assign $1\delay$next[1:0]$14193 \delay + assign $1\delay$next[1:0]$14179 \delay end sync always - update \delay$next $0\delay$next[1:0]$14192 + update \delay$next $0\delay$next[1:0]$14178 end - connect \$101 $add$libresoc.v:196328$13493_Y - connect \$103 $mul$libresoc.v:196329$13494_Y - connect \$99 $shr$libresoc.v:196330$13495_Y [31:0] - connect \$106 $not$libresoc.v:196331$13496_Y - connect \$108 $not$libresoc.v:196332$13497_Y - connect \$110 $and$libresoc.v:196333$13498_Y - connect \$112 $not$libresoc.v:196334$13499_Y - connect \$114 $not$libresoc.v:196335$13500_Y - connect \$116 $and$libresoc.v:196336$13501_Y - connect \$118 $or$libresoc.v:196337$13502_Y + connect \$101 $add$libresoc.v:198689$13479_Y + connect \$103 $mul$libresoc.v:198690$13480_Y + connect \$99 $shr$libresoc.v:198691$13481_Y [31:0] + connect \$106 $not$libresoc.v:198692$13482_Y + connect \$108 $not$libresoc.v:198693$13483_Y + connect \$110 $and$libresoc.v:198694$13484_Y + connect \$112 $not$libresoc.v:198695$13485_Y + connect \$114 $not$libresoc.v:198696$13486_Y + connect \$116 $and$libresoc.v:198697$13487_Y + connect \$118 $or$libresoc.v:198698$13488_Y connect \$120 1'1 - connect \$122 $or$libresoc.v:196339$13503_Y - connect \$125 $add$libresoc.v:196340$13504_Y - connect \$128 $add$libresoc.v:196341$13505_Y - connect \$130 $not$libresoc.v:196342$13506_Y - connect \$132 $not$libresoc.v:196343$13507_Y - connect \$134 $and$libresoc.v:196344$13508_Y - connect \$136 $not$libresoc.v:196345$13509_Y - connect \$138 $not$libresoc.v:196346$13510_Y - connect \$140 $and$libresoc.v:196347$13511_Y - connect \$142 $eq$libresoc.v:196348$13512_Y - connect \$144 $and$libresoc.v:196349$13513_Y - connect \$146 $not$libresoc.v:196350$13514_Y - connect \$148 $not$libresoc.v:196351$13515_Y - connect \$150 $and$libresoc.v:196352$13516_Y - connect \$152 $or$libresoc.v:196353$13517_Y + connect \$122 $or$libresoc.v:198700$13489_Y + connect \$125 $add$libresoc.v:198701$13490_Y + connect \$128 $add$libresoc.v:198702$13491_Y + connect \$130 $not$libresoc.v:198703$13492_Y + connect \$132 $not$libresoc.v:198704$13493_Y + connect \$134 $and$libresoc.v:198705$13494_Y + connect \$136 $not$libresoc.v:198706$13495_Y + connect \$138 $not$libresoc.v:198707$13496_Y + connect \$140 $and$libresoc.v:198708$13497_Y + connect \$142 $eq$libresoc.v:198709$13498_Y + connect \$144 $and$libresoc.v:198710$13499_Y + connect \$146 $not$libresoc.v:198711$13500_Y + connect \$148 $not$libresoc.v:198712$13501_Y + connect \$150 $and$libresoc.v:198713$13502_Y + connect \$152 $or$libresoc.v:198714$13503_Y connect \$154 1'1 - connect \$156 $or$libresoc.v:196355$13518_Y - connect \$158 $not$libresoc.v:196356$13519_Y - connect \$160 $not$libresoc.v:196357$13520_Y - connect \$162 $and$libresoc.v:196358$13521_Y - connect \$164 $not$libresoc.v:196359$13522_Y - connect \$166 $not$libresoc.v:196360$13523_Y - connect \$168 $and$libresoc.v:196361$13524_Y - connect \$170 $not$libresoc.v:196362$13525_Y - connect \$172 $not$libresoc.v:196363$13526_Y - connect \$174 $and$libresoc.v:196364$13527_Y - connect \$176 $not$libresoc.v:196365$13528_Y - connect \$178 $not$libresoc.v:196366$13529_Y - connect \$180 $and$libresoc.v:196367$13530_Y - connect \$182 $not$libresoc.v:196368$13531_Y - connect \$184 $not$libresoc.v:196369$13532_Y - connect \$186 $and$libresoc.v:196370$13533_Y - connect \$188 $not$libresoc.v:196371$13534_Y - connect \$190 $not$libresoc.v:196372$13535_Y - connect \$192 $and$libresoc.v:196373$13536_Y - connect \$195 $and$libresoc.v:196374$13537_Y - connect \$194 $reduce_or$libresoc.v:196375$13538_Y - connect \$198 $not$libresoc.v:196376$13539_Y - connect \$200 $not$libresoc.v:196377$13540_Y - connect \$202 $and$libresoc.v:196378$13541_Y - connect \$204 $not$libresoc.v:196379$13542_Y - connect \$206 $not$libresoc.v:196380$13543_Y - connect \$208 $and$libresoc.v:196381$13544_Y - connect \$210 $or$libresoc.v:196382$13545_Y + connect \$156 $or$libresoc.v:198716$13504_Y + connect \$158 $not$libresoc.v:198717$13505_Y + connect \$160 $not$libresoc.v:198718$13506_Y + connect \$162 $and$libresoc.v:198719$13507_Y + connect \$164 $not$libresoc.v:198720$13508_Y + connect \$166 $not$libresoc.v:198721$13509_Y + connect \$168 $and$libresoc.v:198722$13510_Y + connect \$170 $not$libresoc.v:198723$13511_Y + connect \$172 $not$libresoc.v:198724$13512_Y + connect \$174 $and$libresoc.v:198725$13513_Y + connect \$176 $not$libresoc.v:198726$13514_Y + connect \$178 $not$libresoc.v:198727$13515_Y + connect \$180 $and$libresoc.v:198728$13516_Y + connect \$182 $not$libresoc.v:198729$13517_Y + connect \$184 $not$libresoc.v:198730$13518_Y + connect \$186 $and$libresoc.v:198731$13519_Y + connect \$188 $not$libresoc.v:198732$13520_Y + connect \$190 $not$libresoc.v:198733$13521_Y + connect \$192 $and$libresoc.v:198734$13522_Y + connect \$195 $and$libresoc.v:198735$13523_Y + connect \$194 $reduce_or$libresoc.v:198736$13524_Y + connect \$198 $not$libresoc.v:198737$13525_Y + connect \$200 $not$libresoc.v:198738$13526_Y + connect \$202 $and$libresoc.v:198739$13527_Y + connect \$204 $not$libresoc.v:198740$13528_Y + connect \$206 $not$libresoc.v:198741$13529_Y + connect \$208 $and$libresoc.v:198742$13530_Y + connect \$210 $or$libresoc.v:198743$13531_Y connect \$212 1'1 - connect \$214 $or$libresoc.v:196384$13546_Y - connect \$216 $not$libresoc.v:196385$13547_Y - connect \$218 $not$libresoc.v:196386$13548_Y - connect \$220 $and$libresoc.v:196387$13549_Y - connect \$222 $not$libresoc.v:196388$13550_Y - connect \$224 $not$libresoc.v:196389$13551_Y - connect \$226 $and$libresoc.v:196390$13552_Y - connect \$229 $and$libresoc.v:196391$13553_Y - connect \$228 $reduce_or$libresoc.v:196392$13554_Y - connect \$232 $eq$libresoc.v:196393$13555_Y - connect \$234 $and$libresoc.v:196394$13556_Y - connect \$236 $not$libresoc.v:196395$13557_Y - connect \$238 $not$libresoc.v:196396$13558_Y - connect \$23 $ne$libresoc.v:196397$13559_Y - connect \$240 $not$libresoc.v:196398$13560_Y - connect \$242 $and$libresoc.v:196399$13561_Y - connect \$244 $not$libresoc.v:196400$13562_Y - connect \$246 $not$libresoc.v:196401$13563_Y - connect \$248 $and$libresoc.v:196402$13564_Y - connect \$250 $eq$libresoc.v:196403$13565_Y - connect \$252 $pos$libresoc.v:196404$13566_Y - connect \$254 $ne$libresoc.v:196405$13567_Y - connect \$256 $not$libresoc.v:196406$13568_Y - connect \$258 $not$libresoc.v:196407$13569_Y - connect \$260 $pos$libresoc.v:196408$13571_Y - connect \$262 $pos$libresoc.v:196409$13573_Y - connect \$265 $sub$libresoc.v:196410$13574_Y - connect \$268 $add$libresoc.v:196411$13575_Y - connect \$26 $sub$libresoc.v:196412$13576_Y - connect \$28 $or$libresoc.v:196413$13577_Y - connect \$30 $or$libresoc.v:196414$13578_Y - connect \$32 $ne$libresoc.v:196415$13579_Y - connect \$34 $not$libresoc.v:196416$13580_Y - connect \$36 $and$libresoc.v:196417$13581_Y - connect \$38 $not$libresoc.v:196418$13582_Y - connect \$40 $not$libresoc.v:196419$13583_Y - connect \$42 $pos$libresoc.v:196420$13585_Y - connect \$44 $not$libresoc.v:196421$13586_Y - connect \$46 $not$libresoc.v:196422$13587_Y - connect \$48 $and$libresoc.v:196423$13588_Y - connect \$50 $eq$libresoc.v:196424$13589_Y - connect \$52 $and$libresoc.v:196425$13590_Y - connect \$54 $not$libresoc.v:196426$13591_Y - connect \$56 $not$libresoc.v:196427$13592_Y - connect \$58 $and$libresoc.v:196428$13593_Y - connect \$60 $or$libresoc.v:196429$13594_Y + connect \$214 $or$libresoc.v:198745$13532_Y + connect \$216 $not$libresoc.v:198746$13533_Y + connect \$218 $not$libresoc.v:198747$13534_Y + connect \$220 $and$libresoc.v:198748$13535_Y + connect \$222 $not$libresoc.v:198749$13536_Y + connect \$224 $not$libresoc.v:198750$13537_Y + connect \$226 $and$libresoc.v:198751$13538_Y + connect \$229 $and$libresoc.v:198752$13539_Y + connect \$228 $reduce_or$libresoc.v:198753$13540_Y + connect \$232 $eq$libresoc.v:198754$13541_Y + connect \$234 $and$libresoc.v:198755$13542_Y + connect \$236 $not$libresoc.v:198756$13543_Y + connect \$238 $not$libresoc.v:198757$13544_Y + connect \$23 $ne$libresoc.v:198758$13545_Y + connect \$240 $not$libresoc.v:198759$13546_Y + connect \$242 $and$libresoc.v:198760$13547_Y + connect \$244 $not$libresoc.v:198761$13548_Y + connect \$246 $not$libresoc.v:198762$13549_Y + connect \$248 $and$libresoc.v:198763$13550_Y + connect \$250 $eq$libresoc.v:198764$13551_Y + connect \$252 $pos$libresoc.v:198765$13552_Y + connect \$254 $ne$libresoc.v:198766$13553_Y + connect \$256 $not$libresoc.v:198767$13554_Y + connect \$258 $not$libresoc.v:198768$13555_Y + connect \$260 $pos$libresoc.v:198769$13557_Y + connect \$262 $pos$libresoc.v:198770$13559_Y + connect \$265 $sub$libresoc.v:198771$13560_Y + connect \$268 $add$libresoc.v:198772$13561_Y + connect \$26 $sub$libresoc.v:198773$13562_Y + connect \$28 $or$libresoc.v:198774$13563_Y + connect \$30 $or$libresoc.v:198775$13564_Y + connect \$32 $ne$libresoc.v:198776$13565_Y + connect \$34 $not$libresoc.v:198777$13566_Y + connect \$36 $and$libresoc.v:198778$13567_Y + connect \$38 $not$libresoc.v:198779$13568_Y + connect \$40 $not$libresoc.v:198780$13569_Y + connect \$42 $pos$libresoc.v:198781$13571_Y + connect \$44 $not$libresoc.v:198782$13572_Y + connect \$46 $not$libresoc.v:198783$13573_Y + connect \$48 $and$libresoc.v:198784$13574_Y + connect \$50 $eq$libresoc.v:198785$13575_Y + connect \$52 $and$libresoc.v:198786$13576_Y + connect \$54 $not$libresoc.v:198787$13577_Y + connect \$56 $not$libresoc.v:198788$13578_Y + connect \$58 $and$libresoc.v:198789$13579_Y + connect \$60 $or$libresoc.v:198790$13580_Y connect \$62 1'1 - connect \$64 $or$libresoc.v:196431$13595_Y - connect \$66 $not$libresoc.v:196432$13596_Y - connect \$68 $not$libresoc.v:196433$13597_Y - connect \$70 $and$libresoc.v:196434$13598_Y - connect \$72 $eq$libresoc.v:196435$13599_Y - connect \$74 $and$libresoc.v:196436$13600_Y - connect \$76 $not$libresoc.v:196437$13601_Y - connect \$78 $not$libresoc.v:196438$13602_Y - connect \$80 $and$libresoc.v:196439$13603_Y - connect \$82 $or$libresoc.v:196440$13604_Y + connect \$64 $or$libresoc.v:198792$13581_Y + connect \$66 $not$libresoc.v:198793$13582_Y + connect \$68 $not$libresoc.v:198794$13583_Y + connect \$70 $and$libresoc.v:198795$13584_Y + connect \$72 $eq$libresoc.v:198796$13585_Y + connect \$74 $and$libresoc.v:198797$13586_Y + connect \$76 $not$libresoc.v:198798$13587_Y + connect \$78 $not$libresoc.v:198799$13588_Y + connect \$80 $and$libresoc.v:198800$13589_Y + connect \$82 $or$libresoc.v:198801$13590_Y connect \$84 1'1 - connect \$86 $or$libresoc.v:196442$13605_Y - connect \$88 $not$libresoc.v:196443$13606_Y - connect \$90 $not$libresoc.v:196444$13607_Y - connect \$93 $add$libresoc.v:196445$13608_Y - connect \$96 $mul$libresoc.v:196446$13609_Y - connect \$95 $shr$libresoc.v:196447$13610_Y [31:0] + connect \$86 $or$libresoc.v:198803$13591_Y + connect \$88 $not$libresoc.v:198804$13592_Y + connect \$90 $not$libresoc.v:198805$13593_Y + connect \$93 $add$libresoc.v:198806$13594_Y + connect \$96 $mul$libresoc.v:198807$13595_Y + connect \$95 $shr$libresoc.v:198808$13596_Y [31:0] connect \$25 \$26 connect \$92 \$93 connect \$100 \$101 @@ -411997,485 +385014,485 @@ module \ti connect \por_clk \clk connect { \xics_icp_ics_i_pri \xics_icp_ics_i_src } { \xics_ics_icp_o_pri \xics_ics_icp_o_src } end -attribute \src "libresoc.v:199050.1-200241.10" +attribute \src "libresoc.v:201739.1-202930.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.trap0" attribute \generator "nMigen" module \trap0 - attribute \src "libresoc.v:199786.3-199787.25" + attribute \src "libresoc.v:202475.3-202476.25" wire $0\all_rd_dly[0:0] - attribute \src "libresoc.v:199784.3-199785.41" + attribute \src "libresoc.v:202473.3-202474.41" wire $0\alu_done_dly[0:0] - attribute \src "libresoc.v:200144.3-200152.6" - wire $0\alu_l_r_alu$next[0:0]$14515 - attribute \src "libresoc.v:199712.3-199713.39" + attribute \src "libresoc.v:202833.3-202841.6" + wire $0\alu_l_r_alu$next[0:0]$14501 + attribute \src "libresoc.v:202401.3-202402.39" wire $0\alu_l_r_alu[0:0] - attribute \src "libresoc.v:199967.3-199984.6" - wire width 64 $0\alu_trap0_trap_op__cia$next[63:0]$14441 - attribute \src "libresoc.v:199752.3-199753.61" + attribute \src "libresoc.v:202656.3-202673.6" + wire width 64 $0\alu_trap0_trap_op__cia$next[63:0]$14427 + attribute \src "libresoc.v:202441.3-202442.61" wire width 64 $0\alu_trap0_trap_op__cia[63:0] - attribute \src "libresoc.v:199967.3-199984.6" - wire width 14 $0\alu_trap0_trap_op__fn_unit$next[13:0]$14442 - attribute \src "libresoc.v:199746.3-199747.69" + attribute \src "libresoc.v:202656.3-202673.6" + wire width 14 $0\alu_trap0_trap_op__fn_unit$next[13:0]$14428 + attribute \src "libresoc.v:202435.3-202436.69" wire width 14 $0\alu_trap0_trap_op__fn_unit[13:0] - attribute \src "libresoc.v:199967.3-199984.6" - wire width 32 $0\alu_trap0_trap_op__insn$next[31:0]$14443 - attribute \src "libresoc.v:199748.3-199749.63" + attribute \src "libresoc.v:202656.3-202673.6" + wire width 32 $0\alu_trap0_trap_op__insn$next[31:0]$14429 + attribute \src "libresoc.v:202437.3-202438.63" wire width 32 $0\alu_trap0_trap_op__insn[31:0] - attribute \src "libresoc.v:199967.3-199984.6" - wire width 7 $0\alu_trap0_trap_op__insn_type$next[6:0]$14444 - attribute \src "libresoc.v:199744.3-199745.73" + attribute \src "libresoc.v:202656.3-202673.6" + wire width 7 $0\alu_trap0_trap_op__insn_type$next[6:0]$14430 + attribute \src "libresoc.v:202433.3-202434.73" wire width 7 $0\alu_trap0_trap_op__insn_type[6:0] - attribute \src "libresoc.v:199967.3-199984.6" - wire $0\alu_trap0_trap_op__is_32bit$next[0:0]$14445 - attribute \src "libresoc.v:199754.3-199755.71" + attribute \src "libresoc.v:202656.3-202673.6" + wire $0\alu_trap0_trap_op__is_32bit$next[0:0]$14431 + attribute \src "libresoc.v:202443.3-202444.71" wire $0\alu_trap0_trap_op__is_32bit[0:0] - attribute \src "libresoc.v:199967.3-199984.6" - wire width 8 $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14446 - attribute \src "libresoc.v:199760.3-199761.71" + attribute \src "libresoc.v:202656.3-202673.6" + wire width 8 $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14432 + attribute \src "libresoc.v:202449.3-202450.71" wire width 8 $0\alu_trap0_trap_op__ldst_exc[7:0] - attribute \src "libresoc.v:199967.3-199984.6" - wire width 64 $0\alu_trap0_trap_op__msr$next[63:0]$14447 - attribute \src "libresoc.v:199750.3-199751.61" + attribute \src "libresoc.v:202656.3-202673.6" + wire width 64 $0\alu_trap0_trap_op__msr$next[63:0]$14433 + attribute \src "libresoc.v:202439.3-202440.61" wire width 64 $0\alu_trap0_trap_op__msr[63:0] - attribute \src "libresoc.v:199967.3-199984.6" - wire width 13 $0\alu_trap0_trap_op__trapaddr$next[12:0]$14448 - attribute \src "libresoc.v:199758.3-199759.71" + attribute \src "libresoc.v:202656.3-202673.6" + wire width 13 $0\alu_trap0_trap_op__trapaddr$next[12:0]$14434 + attribute \src "libresoc.v:202447.3-202448.71" wire width 13 $0\alu_trap0_trap_op__trapaddr[12:0] - attribute \src "libresoc.v:199967.3-199984.6" - wire width 8 $0\alu_trap0_trap_op__traptype$next[7:0]$14449 - attribute \src "libresoc.v:199756.3-199757.71" + attribute \src "libresoc.v:202656.3-202673.6" + wire width 8 $0\alu_trap0_trap_op__traptype$next[7:0]$14435 + attribute \src "libresoc.v:202445.3-202446.71" wire width 8 $0\alu_trap0_trap_op__traptype[7:0] - attribute \src "libresoc.v:200135.3-200143.6" - wire $0\alui_l_r_alui$next[0:0]$14512 - attribute \src "libresoc.v:199714.3-199715.43" + attribute \src "libresoc.v:202824.3-202832.6" + wire $0\alui_l_r_alui$next[0:0]$14498 + attribute \src "libresoc.v:202403.3-202404.43" wire $0\alui_l_r_alui[0:0] - attribute \src "libresoc.v:199985.3-200006.6" - wire width 64 $0\data_r0__o$next[63:0]$14460 - attribute \src "libresoc.v:199740.3-199741.37" + attribute \src "libresoc.v:202674.3-202695.6" + wire width 64 $0\data_r0__o$next[63:0]$14446 + attribute \src "libresoc.v:202429.3-202430.37" wire width 64 $0\data_r0__o[63:0] - attribute \src "libresoc.v:199985.3-200006.6" - wire $0\data_r0__o_ok$next[0:0]$14461 - attribute \src "libresoc.v:199742.3-199743.43" + attribute \src "libresoc.v:202674.3-202695.6" + wire $0\data_r0__o_ok$next[0:0]$14447 + attribute \src "libresoc.v:202431.3-202432.43" wire $0\data_r0__o_ok[0:0] - attribute \src "libresoc.v:200007.3-200028.6" - wire width 64 $0\data_r1__fast1$next[63:0]$14468 - attribute \src "libresoc.v:199736.3-199737.45" + attribute \src "libresoc.v:202696.3-202717.6" + wire width 64 $0\data_r1__fast1$next[63:0]$14454 + attribute \src "libresoc.v:202425.3-202426.45" wire width 64 $0\data_r1__fast1[63:0] - attribute \src "libresoc.v:200007.3-200028.6" - wire $0\data_r1__fast1_ok$next[0:0]$14469 - attribute \src "libresoc.v:199738.3-199739.51" + attribute \src "libresoc.v:202696.3-202717.6" + wire $0\data_r1__fast1_ok$next[0:0]$14455 + attribute \src "libresoc.v:202427.3-202428.51" wire $0\data_r1__fast1_ok[0:0] - attribute \src "libresoc.v:200029.3-200050.6" - wire width 64 $0\data_r2__fast2$next[63:0]$14476 - attribute \src "libresoc.v:199732.3-199733.45" + attribute \src "libresoc.v:202718.3-202739.6" + wire width 64 $0\data_r2__fast2$next[63:0]$14462 + attribute \src "libresoc.v:202421.3-202422.45" wire width 64 $0\data_r2__fast2[63:0] - attribute \src "libresoc.v:200029.3-200050.6" - wire $0\data_r2__fast2_ok$next[0:0]$14477 - attribute \src "libresoc.v:199734.3-199735.51" + attribute \src "libresoc.v:202718.3-202739.6" + wire $0\data_r2__fast2_ok$next[0:0]$14463 + attribute \src "libresoc.v:202423.3-202424.51" wire $0\data_r2__fast2_ok[0:0] - attribute \src "libresoc.v:200051.3-200072.6" - wire width 64 $0\data_r3__nia$next[63:0]$14484 - attribute \src "libresoc.v:199728.3-199729.41" + attribute \src "libresoc.v:202740.3-202761.6" + wire width 64 $0\data_r3__nia$next[63:0]$14470 + attribute \src "libresoc.v:202417.3-202418.41" wire width 64 $0\data_r3__nia[63:0] - attribute \src "libresoc.v:200051.3-200072.6" - wire $0\data_r3__nia_ok$next[0:0]$14485 - attribute \src "libresoc.v:199730.3-199731.47" + attribute \src "libresoc.v:202740.3-202761.6" + wire $0\data_r3__nia_ok$next[0:0]$14471 + attribute \src "libresoc.v:202419.3-202420.47" wire $0\data_r3__nia_ok[0:0] - attribute \src "libresoc.v:200073.3-200094.6" - wire width 64 $0\data_r4__msr$next[63:0]$14492 - attribute \src "libresoc.v:199724.3-199725.41" + attribute \src "libresoc.v:202762.3-202783.6" + wire width 64 $0\data_r4__msr$next[63:0]$14478 + attribute \src "libresoc.v:202413.3-202414.41" wire width 64 $0\data_r4__msr[63:0] - attribute \src "libresoc.v:200073.3-200094.6" - wire $0\data_r4__msr_ok$next[0:0]$14493 - attribute \src "libresoc.v:199726.3-199727.47" + attribute \src "libresoc.v:202762.3-202783.6" + wire $0\data_r4__msr_ok$next[0:0]$14479 + attribute \src "libresoc.v:202415.3-202416.47" wire $0\data_r4__msr_ok[0:0] - attribute \src "libresoc.v:200153.3-200162.6" + attribute \src "libresoc.v:202842.3-202851.6" wire width 64 $0\dest1_o[63:0] - attribute \src "libresoc.v:200163.3-200172.6" + attribute \src "libresoc.v:202852.3-202861.6" wire width 64 $0\dest2_o[63:0] - attribute \src "libresoc.v:200173.3-200182.6" + attribute \src "libresoc.v:202862.3-202871.6" wire width 64 $0\dest3_o[63:0] - attribute \src "libresoc.v:200183.3-200192.6" + attribute \src "libresoc.v:202872.3-202881.6" wire width 64 $0\dest4_o[63:0] - attribute \src "libresoc.v:200193.3-200202.6" + attribute \src "libresoc.v:202882.3-202891.6" wire width 64 $0\dest5_o[63:0] - attribute \src "libresoc.v:199051.7-199051.20" + attribute \src "libresoc.v:201740.7-201740.20" wire $0\initial[0:0] - attribute \src "libresoc.v:199922.3-199930.6" - wire $0\opc_l_r_opc$next[0:0]$14426 - attribute \src "libresoc.v:199770.3-199771.39" + attribute \src "libresoc.v:202611.3-202619.6" + wire $0\opc_l_r_opc$next[0:0]$14412 + attribute \src "libresoc.v:202459.3-202460.39" wire $0\opc_l_r_opc[0:0] - attribute \src "libresoc.v:199913.3-199921.6" - wire $0\opc_l_s_opc$next[0:0]$14423 - attribute \src "libresoc.v:199772.3-199773.39" + attribute \src "libresoc.v:202602.3-202610.6" + wire $0\opc_l_s_opc$next[0:0]$14409 + attribute \src "libresoc.v:202461.3-202462.39" wire $0\opc_l_s_opc[0:0] - attribute \src "libresoc.v:200203.3-200211.6" - wire width 5 $0\prev_wr_go$next[4:0]$14523 - attribute \src "libresoc.v:199782.3-199783.37" + attribute \src "libresoc.v:202892.3-202900.6" + wire width 5 $0\prev_wr_go$next[4:0]$14509 + attribute \src "libresoc.v:202471.3-202472.37" wire width 5 $0\prev_wr_go[4:0] - attribute \src "libresoc.v:199867.3-199876.6" + attribute \src "libresoc.v:202556.3-202565.6" wire $0\req_done[0:0] - attribute \src "libresoc.v:199958.3-199966.6" - wire width 5 $0\req_l_r_req$next[4:0]$14438 - attribute \src "libresoc.v:199762.3-199763.39" + attribute \src "libresoc.v:202647.3-202655.6" + wire width 5 $0\req_l_r_req$next[4:0]$14424 + attribute \src "libresoc.v:202451.3-202452.39" wire width 5 $0\req_l_r_req[4:0] - attribute \src "libresoc.v:199949.3-199957.6" - wire width 5 $0\req_l_s_req$next[4:0]$14435 - attribute \src "libresoc.v:199764.3-199765.39" + attribute \src "libresoc.v:202638.3-202646.6" + wire width 5 $0\req_l_s_req$next[4:0]$14421 + attribute \src "libresoc.v:202453.3-202454.39" wire width 5 $0\req_l_s_req[4:0] - attribute \src "libresoc.v:199886.3-199894.6" - wire $0\rok_l_r_rdok$next[0:0]$14414 - attribute \src "libresoc.v:199778.3-199779.41" + attribute \src "libresoc.v:202575.3-202583.6" + wire $0\rok_l_r_rdok$next[0:0]$14400 + attribute \src "libresoc.v:202467.3-202468.41" wire $0\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:199877.3-199885.6" - wire $0\rok_l_s_rdok$next[0:0]$14411 - attribute \src "libresoc.v:199780.3-199781.41" + attribute \src "libresoc.v:202566.3-202574.6" + wire $0\rok_l_s_rdok$next[0:0]$14397 + attribute \src "libresoc.v:202469.3-202470.41" wire $0\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:199904.3-199912.6" - wire $0\rst_l_r_rst$next[0:0]$14420 - attribute \src "libresoc.v:199774.3-199775.39" + attribute \src "libresoc.v:202593.3-202601.6" + wire $0\rst_l_r_rst$next[0:0]$14406 + attribute \src "libresoc.v:202463.3-202464.39" wire $0\rst_l_r_rst[0:0] - attribute \src "libresoc.v:199895.3-199903.6" - wire $0\rst_l_s_rst$next[0:0]$14417 - attribute \src "libresoc.v:199776.3-199777.39" + attribute \src "libresoc.v:202584.3-202592.6" + wire $0\rst_l_s_rst$next[0:0]$14403 + attribute \src "libresoc.v:202465.3-202466.39" wire $0\rst_l_s_rst[0:0] - attribute \src "libresoc.v:199940.3-199948.6" - wire width 4 $0\src_l_r_src$next[3:0]$14432 - attribute \src "libresoc.v:199766.3-199767.39" + attribute \src "libresoc.v:202629.3-202637.6" + wire width 4 $0\src_l_r_src$next[3:0]$14418 + attribute \src "libresoc.v:202455.3-202456.39" wire width 4 $0\src_l_r_src[3:0] - attribute \src "libresoc.v:199931.3-199939.6" - wire width 4 $0\src_l_s_src$next[3:0]$14429 - attribute \src "libresoc.v:199768.3-199769.39" + attribute \src "libresoc.v:202620.3-202628.6" + wire width 4 $0\src_l_s_src$next[3:0]$14415 + attribute \src "libresoc.v:202457.3-202458.39" wire width 4 $0\src_l_s_src[3:0] - attribute \src "libresoc.v:200095.3-200104.6" - wire width 64 $0\src_r0$next[63:0]$14500 - attribute \src "libresoc.v:199722.3-199723.29" + attribute \src "libresoc.v:202784.3-202793.6" + wire width 64 $0\src_r0$next[63:0]$14486 + attribute \src "libresoc.v:202411.3-202412.29" wire width 64 $0\src_r0[63:0] - attribute \src "libresoc.v:200105.3-200114.6" - wire width 64 $0\src_r1$next[63:0]$14503 - attribute \src "libresoc.v:199720.3-199721.29" + attribute \src "libresoc.v:202794.3-202803.6" + wire width 64 $0\src_r1$next[63:0]$14489 + attribute \src "libresoc.v:202409.3-202410.29" wire width 64 $0\src_r1[63:0] - attribute \src "libresoc.v:200115.3-200124.6" - wire width 64 $0\src_r2$next[63:0]$14506 - attribute \src "libresoc.v:199718.3-199719.29" + attribute \src "libresoc.v:202804.3-202813.6" + wire width 64 $0\src_r2$next[63:0]$14492 + attribute \src "libresoc.v:202407.3-202408.29" wire width 64 $0\src_r2[63:0] - attribute \src "libresoc.v:200125.3-200134.6" - wire width 64 $0\src_r3$next[63:0]$14509 - attribute \src "libresoc.v:199716.3-199717.29" + attribute \src "libresoc.v:202814.3-202823.6" + wire width 64 $0\src_r3$next[63:0]$14495 + attribute \src "libresoc.v:202405.3-202406.29" wire width 64 $0\src_r3[63:0] - attribute \src "libresoc.v:199177.7-199177.24" + attribute \src "libresoc.v:201866.7-201866.24" wire $1\all_rd_dly[0:0] - attribute \src "libresoc.v:199187.7-199187.26" + attribute \src "libresoc.v:201876.7-201876.26" wire $1\alu_done_dly[0:0] - attribute \src "libresoc.v:200144.3-200152.6" - wire $1\alu_l_r_alu$next[0:0]$14516 - attribute \src "libresoc.v:199195.7-199195.25" + attribute \src "libresoc.v:202833.3-202841.6" + wire $1\alu_l_r_alu$next[0:0]$14502 + attribute \src "libresoc.v:201884.7-201884.25" wire $1\alu_l_r_alu[0:0] - attribute \src "libresoc.v:199967.3-199984.6" - wire width 64 $1\alu_trap0_trap_op__cia$next[63:0]$14450 - attribute \src "libresoc.v:199231.14-199231.59" + attribute \src "libresoc.v:202656.3-202673.6" + wire width 64 $1\alu_trap0_trap_op__cia$next[63:0]$14436 + attribute \src "libresoc.v:201920.14-201920.59" wire width 64 $1\alu_trap0_trap_op__cia[63:0] - attribute \src "libresoc.v:199967.3-199984.6" - wire width 14 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14451 - attribute \src "libresoc.v:199250.14-199250.51" + attribute \src "libresoc.v:202656.3-202673.6" + wire width 14 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14437 + attribute \src "libresoc.v:201939.14-201939.51" wire width 14 $1\alu_trap0_trap_op__fn_unit[13:0] - attribute \src "libresoc.v:199967.3-199984.6" - wire width 32 $1\alu_trap0_trap_op__insn$next[31:0]$14452 - attribute \src "libresoc.v:199254.14-199254.45" + attribute \src "libresoc.v:202656.3-202673.6" + wire width 32 $1\alu_trap0_trap_op__insn$next[31:0]$14438 + attribute \src "libresoc.v:201943.14-201943.45" wire width 32 $1\alu_trap0_trap_op__insn[31:0] - attribute \src "libresoc.v:199967.3-199984.6" - wire width 7 $1\alu_trap0_trap_op__insn_type$next[6:0]$14453 - attribute \src "libresoc.v:199333.13-199333.49" + attribute \src "libresoc.v:202656.3-202673.6" + wire width 7 $1\alu_trap0_trap_op__insn_type$next[6:0]$14439 + attribute \src "libresoc.v:202022.13-202022.49" wire width 7 $1\alu_trap0_trap_op__insn_type[6:0] - attribute \src "libresoc.v:199967.3-199984.6" - wire $1\alu_trap0_trap_op__is_32bit$next[0:0]$14454 - attribute \src "libresoc.v:199337.7-199337.41" + attribute \src "libresoc.v:202656.3-202673.6" + wire $1\alu_trap0_trap_op__is_32bit$next[0:0]$14440 + attribute \src "libresoc.v:202026.7-202026.41" wire $1\alu_trap0_trap_op__is_32bit[0:0] - attribute \src "libresoc.v:199967.3-199984.6" - wire width 8 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14455 - attribute \src "libresoc.v:199341.13-199341.48" + attribute \src "libresoc.v:202656.3-202673.6" + wire width 8 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14441 + attribute \src "libresoc.v:202030.13-202030.48" wire width 8 $1\alu_trap0_trap_op__ldst_exc[7:0] - attribute \src "libresoc.v:199967.3-199984.6" - wire width 64 $1\alu_trap0_trap_op__msr$next[63:0]$14456 - attribute \src "libresoc.v:199345.14-199345.59" + attribute \src "libresoc.v:202656.3-202673.6" + wire width 64 $1\alu_trap0_trap_op__msr$next[63:0]$14442 + attribute \src "libresoc.v:202034.14-202034.59" wire width 64 $1\alu_trap0_trap_op__msr[63:0] - attribute \src "libresoc.v:199967.3-199984.6" - wire width 13 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14457 - attribute \src "libresoc.v:199349.14-199349.52" + attribute \src "libresoc.v:202656.3-202673.6" + wire width 13 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14443 + attribute \src "libresoc.v:202038.14-202038.52" wire width 13 $1\alu_trap0_trap_op__trapaddr[12:0] - attribute \src "libresoc.v:199967.3-199984.6" - wire width 8 $1\alu_trap0_trap_op__traptype$next[7:0]$14458 - attribute \src "libresoc.v:199353.13-199353.48" + attribute \src "libresoc.v:202656.3-202673.6" + wire width 8 $1\alu_trap0_trap_op__traptype$next[7:0]$14444 + attribute \src "libresoc.v:202042.13-202042.48" wire width 8 $1\alu_trap0_trap_op__traptype[7:0] - attribute \src "libresoc.v:200135.3-200143.6" - wire $1\alui_l_r_alui$next[0:0]$14513 - attribute \src "libresoc.v:199359.7-199359.27" + attribute \src "libresoc.v:202824.3-202832.6" + wire $1\alui_l_r_alui$next[0:0]$14499 + attribute \src "libresoc.v:202048.7-202048.27" wire $1\alui_l_r_alui[0:0] - attribute \src "libresoc.v:199985.3-200006.6" - wire width 64 $1\data_r0__o$next[63:0]$14462 - attribute \src "libresoc.v:199391.14-199391.47" + attribute \src "libresoc.v:202674.3-202695.6" + wire width 64 $1\data_r0__o$next[63:0]$14448 + attribute \src "libresoc.v:202080.14-202080.47" wire width 64 $1\data_r0__o[63:0] - attribute \src "libresoc.v:199985.3-200006.6" - wire $1\data_r0__o_ok$next[0:0]$14463 - attribute \src "libresoc.v:199395.7-199395.27" + attribute \src "libresoc.v:202674.3-202695.6" + wire $1\data_r0__o_ok$next[0:0]$14449 + attribute \src "libresoc.v:202084.7-202084.27" wire $1\data_r0__o_ok[0:0] - attribute \src "libresoc.v:200007.3-200028.6" - wire width 64 $1\data_r1__fast1$next[63:0]$14470 - attribute \src "libresoc.v:199399.14-199399.51" + attribute \src "libresoc.v:202696.3-202717.6" + wire width 64 $1\data_r1__fast1$next[63:0]$14456 + attribute \src "libresoc.v:202088.14-202088.51" wire width 64 $1\data_r1__fast1[63:0] - attribute \src "libresoc.v:200007.3-200028.6" - wire $1\data_r1__fast1_ok$next[0:0]$14471 - attribute \src "libresoc.v:199403.7-199403.31" + attribute \src "libresoc.v:202696.3-202717.6" + wire $1\data_r1__fast1_ok$next[0:0]$14457 + attribute \src "libresoc.v:202092.7-202092.31" wire $1\data_r1__fast1_ok[0:0] - attribute \src "libresoc.v:200029.3-200050.6" - wire width 64 $1\data_r2__fast2$next[63:0]$14478 - attribute \src "libresoc.v:199407.14-199407.51" + attribute \src "libresoc.v:202718.3-202739.6" + wire width 64 $1\data_r2__fast2$next[63:0]$14464 + attribute \src "libresoc.v:202096.14-202096.51" wire width 64 $1\data_r2__fast2[63:0] - attribute \src "libresoc.v:200029.3-200050.6" - wire $1\data_r2__fast2_ok$next[0:0]$14479 - attribute \src "libresoc.v:199411.7-199411.31" + attribute \src "libresoc.v:202718.3-202739.6" + wire $1\data_r2__fast2_ok$next[0:0]$14465 + attribute \src "libresoc.v:202100.7-202100.31" wire $1\data_r2__fast2_ok[0:0] - attribute \src "libresoc.v:200051.3-200072.6" - wire width 64 $1\data_r3__nia$next[63:0]$14486 - attribute \src "libresoc.v:199415.14-199415.49" + attribute \src "libresoc.v:202740.3-202761.6" + wire width 64 $1\data_r3__nia$next[63:0]$14472 + attribute \src "libresoc.v:202104.14-202104.49" wire width 64 $1\data_r3__nia[63:0] - attribute \src "libresoc.v:200051.3-200072.6" - wire $1\data_r3__nia_ok$next[0:0]$14487 - attribute \src "libresoc.v:199419.7-199419.29" + attribute \src "libresoc.v:202740.3-202761.6" + wire $1\data_r3__nia_ok$next[0:0]$14473 + attribute \src "libresoc.v:202108.7-202108.29" wire $1\data_r3__nia_ok[0:0] - attribute \src "libresoc.v:200073.3-200094.6" - wire width 64 $1\data_r4__msr$next[63:0]$14494 - attribute \src "libresoc.v:199423.14-199423.49" + attribute \src "libresoc.v:202762.3-202783.6" + wire width 64 $1\data_r4__msr$next[63:0]$14480 + attribute \src "libresoc.v:202112.14-202112.49" wire width 64 $1\data_r4__msr[63:0] - attribute \src "libresoc.v:200073.3-200094.6" - wire $1\data_r4__msr_ok$next[0:0]$14495 - attribute \src "libresoc.v:199427.7-199427.29" + attribute \src "libresoc.v:202762.3-202783.6" + wire $1\data_r4__msr_ok$next[0:0]$14481 + attribute \src "libresoc.v:202116.7-202116.29" wire $1\data_r4__msr_ok[0:0] - attribute \src "libresoc.v:200153.3-200162.6" + attribute \src "libresoc.v:202842.3-202851.6" wire width 64 $1\dest1_o[63:0] - attribute \src "libresoc.v:200163.3-200172.6" + attribute \src "libresoc.v:202852.3-202861.6" wire width 64 $1\dest2_o[63:0] - attribute \src "libresoc.v:200173.3-200182.6" + attribute \src "libresoc.v:202862.3-202871.6" wire width 64 $1\dest3_o[63:0] - attribute \src "libresoc.v:200183.3-200192.6" + attribute \src "libresoc.v:202872.3-202881.6" wire width 64 $1\dest4_o[63:0] - attribute \src "libresoc.v:200193.3-200202.6" + attribute \src "libresoc.v:202882.3-202891.6" wire width 64 $1\dest5_o[63:0] - attribute \src "libresoc.v:199922.3-199930.6" - wire $1\opc_l_r_opc$next[0:0]$14427 - attribute \src "libresoc.v:199458.7-199458.25" + attribute \src "libresoc.v:202611.3-202619.6" + wire $1\opc_l_r_opc$next[0:0]$14413 + attribute \src "libresoc.v:202147.7-202147.25" wire $1\opc_l_r_opc[0:0] - attribute \src "libresoc.v:199913.3-199921.6" - wire $1\opc_l_s_opc$next[0:0]$14424 - attribute \src "libresoc.v:199462.7-199462.25" + attribute \src "libresoc.v:202602.3-202610.6" + wire $1\opc_l_s_opc$next[0:0]$14410 + attribute \src "libresoc.v:202151.7-202151.25" wire $1\opc_l_s_opc[0:0] - attribute \src "libresoc.v:200203.3-200211.6" - wire width 5 $1\prev_wr_go$next[4:0]$14524 - attribute \src "libresoc.v:199574.13-199574.31" + attribute \src "libresoc.v:202892.3-202900.6" + wire width 5 $1\prev_wr_go$next[4:0]$14510 + attribute \src "libresoc.v:202263.13-202263.31" wire width 5 $1\prev_wr_go[4:0] - attribute \src "libresoc.v:199867.3-199876.6" + attribute \src "libresoc.v:202556.3-202565.6" wire $1\req_done[0:0] - attribute \src "libresoc.v:199958.3-199966.6" - wire width 5 $1\req_l_r_req$next[4:0]$14439 - attribute \src "libresoc.v:199582.13-199582.32" + attribute \src "libresoc.v:202647.3-202655.6" + wire width 5 $1\req_l_r_req$next[4:0]$14425 + attribute \src "libresoc.v:202271.13-202271.32" wire width 5 $1\req_l_r_req[4:0] - attribute \src "libresoc.v:199949.3-199957.6" - wire width 5 $1\req_l_s_req$next[4:0]$14436 - attribute \src "libresoc.v:199586.13-199586.32" + attribute \src "libresoc.v:202638.3-202646.6" + wire width 5 $1\req_l_s_req$next[4:0]$14422 + attribute \src "libresoc.v:202275.13-202275.32" wire width 5 $1\req_l_s_req[4:0] - attribute \src "libresoc.v:199886.3-199894.6" - wire $1\rok_l_r_rdok$next[0:0]$14415 - attribute \src "libresoc.v:199598.7-199598.26" + attribute \src "libresoc.v:202575.3-202583.6" + wire $1\rok_l_r_rdok$next[0:0]$14401 + attribute \src "libresoc.v:202287.7-202287.26" wire $1\rok_l_r_rdok[0:0] - attribute \src "libresoc.v:199877.3-199885.6" - wire $1\rok_l_s_rdok$next[0:0]$14412 - attribute \src "libresoc.v:199602.7-199602.26" + attribute \src "libresoc.v:202566.3-202574.6" + wire $1\rok_l_s_rdok$next[0:0]$14398 + attribute \src "libresoc.v:202291.7-202291.26" wire $1\rok_l_s_rdok[0:0] - attribute \src "libresoc.v:199904.3-199912.6" - wire $1\rst_l_r_rst$next[0:0]$14421 - attribute \src "libresoc.v:199606.7-199606.25" + attribute \src "libresoc.v:202593.3-202601.6" + wire $1\rst_l_r_rst$next[0:0]$14407 + attribute \src "libresoc.v:202295.7-202295.25" wire $1\rst_l_r_rst[0:0] - attribute \src "libresoc.v:199895.3-199903.6" - wire $1\rst_l_s_rst$next[0:0]$14418 - attribute \src "libresoc.v:199610.7-199610.25" + attribute \src "libresoc.v:202584.3-202592.6" + wire $1\rst_l_s_rst$next[0:0]$14404 + attribute \src "libresoc.v:202299.7-202299.25" wire $1\rst_l_s_rst[0:0] - attribute \src "libresoc.v:199940.3-199948.6" - wire width 4 $1\src_l_r_src$next[3:0]$14433 - attribute \src "libresoc.v:199626.13-199626.31" + attribute \src "libresoc.v:202629.3-202637.6" + wire width 4 $1\src_l_r_src$next[3:0]$14419 + attribute \src "libresoc.v:202315.13-202315.31" wire width 4 $1\src_l_r_src[3:0] - attribute \src "libresoc.v:199931.3-199939.6" - wire width 4 $1\src_l_s_src$next[3:0]$14430 - attribute \src "libresoc.v:199630.13-199630.31" + attribute \src "libresoc.v:202620.3-202628.6" + wire width 4 $1\src_l_s_src$next[3:0]$14416 + attribute \src "libresoc.v:202319.13-202319.31" wire width 4 $1\src_l_s_src[3:0] - attribute \src "libresoc.v:200095.3-200104.6" - wire width 64 $1\src_r0$next[63:0]$14501 - attribute \src "libresoc.v:199634.14-199634.43" + attribute \src "libresoc.v:202784.3-202793.6" + wire width 64 $1\src_r0$next[63:0]$14487 + attribute \src "libresoc.v:202323.14-202323.43" wire width 64 $1\src_r0[63:0] - attribute \src "libresoc.v:200105.3-200114.6" - wire width 64 $1\src_r1$next[63:0]$14504 - attribute \src "libresoc.v:199638.14-199638.43" + attribute \src "libresoc.v:202794.3-202803.6" + wire width 64 $1\src_r1$next[63:0]$14490 + attribute \src "libresoc.v:202327.14-202327.43" wire width 64 $1\src_r1[63:0] - attribute \src "libresoc.v:200115.3-200124.6" - wire width 64 $1\src_r2$next[63:0]$14507 - attribute \src "libresoc.v:199642.14-199642.43" + attribute \src "libresoc.v:202804.3-202813.6" + wire width 64 $1\src_r2$next[63:0]$14493 + attribute \src "libresoc.v:202331.14-202331.43" wire width 64 $1\src_r2[63:0] - attribute \src "libresoc.v:200125.3-200134.6" - wire width 64 $1\src_r3$next[63:0]$14510 - attribute \src "libresoc.v:199646.14-199646.43" + attribute \src "libresoc.v:202814.3-202823.6" + wire width 64 $1\src_r3$next[63:0]$14496 + attribute \src "libresoc.v:202335.14-202335.43" wire width 64 $1\src_r3[63:0] - attribute \src "libresoc.v:199985.3-200006.6" - wire width 64 $2\data_r0__o$next[63:0]$14464 - attribute \src "libresoc.v:199985.3-200006.6" - wire $2\data_r0__o_ok$next[0:0]$14465 - attribute \src "libresoc.v:200007.3-200028.6" - wire width 64 $2\data_r1__fast1$next[63:0]$14472 - attribute \src "libresoc.v:200007.3-200028.6" - wire $2\data_r1__fast1_ok$next[0:0]$14473 - attribute \src "libresoc.v:200029.3-200050.6" - wire width 64 $2\data_r2__fast2$next[63:0]$14480 - attribute \src "libresoc.v:200029.3-200050.6" - wire $2\data_r2__fast2_ok$next[0:0]$14481 - attribute \src "libresoc.v:200051.3-200072.6" - wire width 64 $2\data_r3__nia$next[63:0]$14488 - attribute \src "libresoc.v:200051.3-200072.6" - wire $2\data_r3__nia_ok$next[0:0]$14489 - attribute \src "libresoc.v:200073.3-200094.6" - wire width 64 $2\data_r4__msr$next[63:0]$14496 - attribute \src "libresoc.v:200073.3-200094.6" - wire $2\data_r4__msr_ok$next[0:0]$14497 - attribute \src "libresoc.v:199985.3-200006.6" - wire $3\data_r0__o_ok$next[0:0]$14466 - attribute \src "libresoc.v:200007.3-200028.6" - wire $3\data_r1__fast1_ok$next[0:0]$14474 - attribute \src "libresoc.v:200029.3-200050.6" - wire $3\data_r2__fast2_ok$next[0:0]$14482 - attribute \src "libresoc.v:200051.3-200072.6" - wire $3\data_r3__nia_ok$next[0:0]$14490 - attribute \src "libresoc.v:200073.3-200094.6" - wire $3\data_r4__msr_ok$next[0:0]$14498 - attribute \src "libresoc.v:199652.18-199652.112" - wire width 4 $and$libresoc.v:199652$14311_Y - attribute \src "libresoc.v:199653.19-199653.125" - wire $and$libresoc.v:199653$14312_Y - attribute \src "libresoc.v:199654.19-199654.125" - wire $and$libresoc.v:199654$14313_Y - attribute \src "libresoc.v:199655.19-199655.125" - wire $and$libresoc.v:199655$14314_Y - attribute \src "libresoc.v:199656.19-199656.125" - wire $and$libresoc.v:199656$14315_Y - attribute \src "libresoc.v:199657.19-199657.125" - wire $and$libresoc.v:199657$14316_Y - attribute \src "libresoc.v:199658.19-199658.157" - wire width 5 $and$libresoc.v:199658$14317_Y - attribute \src "libresoc.v:199659.19-199659.121" - wire width 5 $and$libresoc.v:199659$14318_Y - attribute \src "libresoc.v:199660.19-199660.127" - wire $and$libresoc.v:199660$14319_Y - attribute \src "libresoc.v:199661.19-199661.127" - wire $and$libresoc.v:199661$14320_Y - attribute \src "libresoc.v:199662.18-199662.110" - wire $and$libresoc.v:199662$14321_Y - attribute \src "libresoc.v:199663.19-199663.127" - wire $and$libresoc.v:199663$14322_Y - attribute \src "libresoc.v:199664.19-199664.127" - wire $and$libresoc.v:199664$14323_Y - attribute \src "libresoc.v:199665.19-199665.127" - wire $and$libresoc.v:199665$14324_Y - attribute \src "libresoc.v:199667.18-199667.98" - wire $and$libresoc.v:199667$14326_Y - attribute \src "libresoc.v:199669.18-199669.100" - wire $and$libresoc.v:199669$14328_Y - attribute \src "libresoc.v:199670.18-199670.171" - wire width 5 $and$libresoc.v:199670$14329_Y - attribute \src "libresoc.v:199672.18-199672.119" - wire width 5 $and$libresoc.v:199672$14331_Y - attribute \src "libresoc.v:199675.18-199675.116" - wire $and$libresoc.v:199675$14334_Y - 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$or$libresoc.v:202381$14337_Y + attribute \src "libresoc.v:202385.18-202385.120" + wire width 5 $or$libresoc.v:202385$14341_Y + attribute \src "libresoc.v:202395.17-202395.117" + wire width 4 $or$libresoc.v:202395$14351_Y + attribute \src "libresoc.v:202340.17-202340.104" + wire $reduce_and$libresoc.v:202340$14296_Y + attribute \src "libresoc.v:202362.18-202362.106" + wire $reduce_or$libresoc.v:202362$14318_Y + attribute \src "libresoc.v:202365.18-202365.113" + wire $reduce_or$libresoc.v:202365$14321_Y + attribute \src "libresoc.v:202366.18-202366.112" + wire $reduce_or$libresoc.v:202366$14322_Y + attribute \src "libresoc.v:202391.18-202391.118" + wire width 64 $ternary$libresoc.v:202391$14347_Y + attribute \src "libresoc.v:202392.18-202392.118" + wire width 64 $ternary$libresoc.v:202392$14348_Y + attribute \src "libresoc.v:202393.18-202393.118" + wire width 64 $ternary$libresoc.v:202393$14349_Y + attribute \src "libresoc.v:202394.18-202394.118" + wire width 64 $ternary$libresoc.v:202394$14350_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" wire \$101 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" @@ -412788,9 +385805,9 @@ module \trap0 wire \alui_l_r_alui$next attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire \alui_l_s_alui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 32 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" wire output 12 \cu_busy_o @@ -412868,7 +385885,7 @@ module \trap0 wire output 24 \fast1_ok attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 25 \fast2_ok - attribute \src "libresoc.v:199051.7-199051.15" + attribute \src "libresoc.v:201740.7-201740.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:18" wire output 30 \msr_ok @@ -413073,7 +386090,7 @@ module \trap0 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" wire \wr_any attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:199652$14311 + cell $and $and$libresoc.v:202341$14297 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -413081,10 +386098,10 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \$95 connect \B \$97 - connect \Y $and$libresoc.v:199652$14311_Y + connect \Y $and$libresoc.v:202341$14297_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:199653$14312 + cell $and $and$libresoc.v:202342$14298 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413092,10 +386109,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:199653$14312_Y + connect \Y $and$libresoc.v:202342$14298_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:199654$14313 + cell $and $and$libresoc.v:202343$14299 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413103,10 +386120,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:199654$14313_Y + connect \Y $and$libresoc.v:202343$14299_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:199655$14314 + cell $and $and$libresoc.v:202344$14300 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413114,10 +386131,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:199655$14314_Y + connect \Y $and$libresoc.v:202344$14300_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:199656$14315 + cell $and $and$libresoc.v:202345$14301 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413125,10 +386142,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:199656$14315_Y + connect \Y $and$libresoc.v:202345$14301_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $and$libresoc.v:199657$14316 + cell $and $and$libresoc.v:202346$14302 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413136,10 +386153,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \cu_shadown_i - connect \Y $and$libresoc.v:199657$14316_Y + connect \Y $and$libresoc.v:202346$14302_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:199658$14317 + cell $and $and$libresoc.v:202347$14303 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -413147,10 +386164,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \req_l_q_req connect \B { \$101 \$103 \$105 \$107 \$109 } - connect \Y $and$libresoc.v:199658$14317_Y + connect \Y $and$libresoc.v:202347$14303_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $and$libresoc.v:199659$14318 + cell $and $and$libresoc.v:202348$14304 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -413158,10 +386175,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \$111 connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:199659$14318_Y + connect \Y $and$libresoc.v:202348$14304_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:199660$14319 + cell $and $and$libresoc.v:202349$14305 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413169,10 +386186,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [0] connect \B \cu_busy_o - connect \Y $and$libresoc.v:199660$14319_Y + connect \Y $and$libresoc.v:202349$14305_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:199661$14320 + cell $and $and$libresoc.v:202350$14306 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413180,10 +386197,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [1] connect \B \cu_busy_o - connect \Y $and$libresoc.v:199661$14320_Y + connect \Y $and$libresoc.v:202350$14306_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $and$libresoc.v:199662$14321 + cell $and $and$libresoc.v:202351$14307 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413191,10 +386208,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$3 connect \B \$5 - connect \Y $and$libresoc.v:199662$14321_Y + connect \Y $and$libresoc.v:202351$14307_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:199663$14322 + cell $and $and$libresoc.v:202352$14308 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413202,10 +386219,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [2] connect \B \cu_busy_o - connect \Y $and$libresoc.v:199663$14322_Y + connect \Y $and$libresoc.v:202352$14308_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:199664$14323 + cell $and $and$libresoc.v:202353$14309 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413213,10 +386230,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [3] connect \B \cu_busy_o - connect \Y $and$libresoc.v:199664$14323_Y + connect \Y $and$libresoc.v:202353$14309_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $and$libresoc.v:199665$14324 + cell $and $and$libresoc.v:202354$14310 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413224,10 +386241,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i [4] connect \B \cu_busy_o - connect \Y $and$libresoc.v:199665$14324_Y + connect \Y $and$libresoc.v:202354$14310_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:199667$14326 + cell $and $and$libresoc.v:202356$14312 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413235,10 +386252,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \all_rd connect \B \$13 - connect \Y $and$libresoc.v:199667$14326_Y + connect \Y $and$libresoc.v:202356$14312_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $and $and$libresoc.v:199669$14328 + cell $and $and$libresoc.v:202358$14314 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413246,10 +386263,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \alu_done connect \B \$17 - connect \Y $and$libresoc.v:199669$14328_Y + connect \Y $and$libresoc.v:202358$14314_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $and$libresoc.v:199670$14329 + cell $and $and$libresoc.v:202359$14315 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -413257,10 +386274,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \cu_wr__go_i connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:199670$14329_Y + connect \Y $and$libresoc.v:202359$14315_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:199672$14331 + cell $and $and$libresoc.v:202361$14317 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -413268,10 +386285,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \cu_wr__rel_o connect \B \$25 - connect \Y $and$libresoc.v:199672$14331_Y + connect \Y $and$libresoc.v:202361$14317_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $and$libresoc.v:199675$14334 + cell $and $and$libresoc.v:202364$14320 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413279,10 +386296,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \$23 - connect \Y $and$libresoc.v:199675$14334_Y + connect \Y $and$libresoc.v:202364$14320_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $and$libresoc.v:199679$14338 + cell $and $and$libresoc.v:202368$14324 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413290,10 +386307,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_busy_o connect \B \rok_l_q_rdok - connect \Y $and$libresoc.v:199679$14338_Y + connect \Y $and$libresoc.v:202368$14324_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $and$libresoc.v:199681$14340 + cell $and $and$libresoc.v:202370$14326 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413301,10 +386318,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \wr_any connect \B \$39 - connect \Y $and$libresoc.v:199681$14340_Y + connect \Y $and$libresoc.v:202370$14326_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:199682$14341 + cell $and $and$libresoc.v:202371$14327 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -413312,10 +386329,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \req_l_q_req connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:199682$14341_Y + connect \Y $and$libresoc.v:202371$14327_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $and$libresoc.v:199684$14343 + cell $and $and$libresoc.v:202373$14329 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413323,10 +386340,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$41 connect \B \$45 - connect \Y $and$libresoc.v:199684$14343_Y + connect \Y $and$libresoc.v:202373$14329_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:199686$14345 + cell $and $and$libresoc.v:202375$14331 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413334,10 +386351,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$49 connect \B \alu_trap0_n_ready_i - connect \Y $and$libresoc.v:199686$14345_Y + connect \Y $and$libresoc.v:202375$14331_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:199687$14346 + cell $and $and$libresoc.v:202376$14332 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413345,10 +386362,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$51 connect \B \alu_trap0_n_valid_o - connect \Y $and$libresoc.v:199687$14346_Y + connect \Y $and$libresoc.v:202376$14332_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $and$libresoc.v:199688$14347 + cell $and $and$libresoc.v:202377$14333 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413356,10 +386373,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$53 connect \B \cu_busy_o - connect \Y $and$libresoc.v:199688$14347_Y + connect \Y $and$libresoc.v:202377$14333_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $and$libresoc.v:199693$14352 + cell $and $and$libresoc.v:202382$14338 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413367,10 +386384,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \alu_trap0_n_valid_o connect \B \cu_busy_o - connect \Y $and$libresoc.v:199693$14352_Y + connect \Y $and$libresoc.v:202382$14338_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $and$libresoc.v:199694$14353 + cell $and $and$libresoc.v:202383$14339 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -413378,10 +386395,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \alu_pulsem connect \B \cu_wrmask_o - connect \Y $and$libresoc.v:199694$14353_Y + connect \Y $and$libresoc.v:202383$14339_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:199697$14356 + cell $and $and$libresoc.v:202386$14342 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413389,10 +386406,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \o_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:199697$14356_Y + connect \Y $and$libresoc.v:202386$14342_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:199698$14357 + cell $and $and$libresoc.v:202387$14343 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413400,10 +386417,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \fast1_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:199698$14357_Y + connect \Y $and$libresoc.v:202387$14343_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:199699$14358 + cell $and $and$libresoc.v:202388$14344 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413411,10 +386428,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \fast2_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:199699$14358_Y + connect \Y $and$libresoc.v:202388$14344_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:199700$14359 + cell $and $and$libresoc.v:202389$14345 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413422,10 +386439,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \nia_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:199700$14359_Y + connect \Y $and$libresoc.v:202389$14345_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $and$libresoc.v:199701$14360 + cell $and $and$libresoc.v:202390$14346 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413433,10 +386450,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \msr_ok connect \B \cu_busy_o - connect \Y $and$libresoc.v:199701$14360_Y + connect \Y $and$libresoc.v:202390$14346_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $and$libresoc.v:199707$14366 + cell $and $and$libresoc.v:202396$14352 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413444,10 +386461,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \alu_trap0_p_ready_o connect \B \alui_l_q_alui - connect \Y $and$libresoc.v:199707$14366_Y + connect \Y $and$libresoc.v:202396$14352_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $and$libresoc.v:199708$14367 + cell $and $and$libresoc.v:202397$14353 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413455,10 +386472,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \alu_trap0_n_valid_o connect \B \alu_l_q_alu - connect \Y $and$libresoc.v:199708$14367_Y + connect \Y $and$libresoc.v:202397$14353_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:199709$14368 + cell $and $and$libresoc.v:202398$14354 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -413466,10 +386483,10 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \src_l_q_src connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $and$libresoc.v:199709$14368_Y + connect \Y $and$libresoc.v:202398$14354_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $and$libresoc.v:199710$14369 + cell $and $and$libresoc.v:202399$14355 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -413477,10 +386494,10 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \$93 connect \B 4'1111 - connect \Y $and$libresoc.v:199710$14369_Y + connect \Y $and$libresoc.v:202399$14355_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $eq$libresoc.v:199683$14342 + cell $eq $eq$libresoc.v:202372$14328 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -413488,10 +386505,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$43 connect \B 1'0 - connect \Y $eq$libresoc.v:199683$14342_Y + connect \Y $eq$libresoc.v:202372$14328_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $eq$libresoc.v:199685$14344 + cell $eq $eq$libresoc.v:202374$14330 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -413499,66 +386516,66 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_wrmask_o connect \B 1'0 - connect \Y $eq$libresoc.v:199685$14344_Y + connect \Y $eq$libresoc.v:202374$14330_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:199666$14325 + cell $not $not$libresoc.v:202355$14311 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \all_rd_dly - connect \Y $not$libresoc.v:199666$14325_Y + connect \Y $not$libresoc.v:202355$14311_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:65" - cell $not $not$libresoc.v:199668$14327 + cell $not $not$libresoc.v:202357$14313 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_done_dly - connect \Y $not$libresoc.v:199668$14327_Y + connect \Y $not$libresoc.v:202357$14313_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:199671$14330 + cell $not $not$libresoc.v:202360$14316 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \cu_wrmask_o - connect \Y $not$libresoc.v:199671$14330_Y + connect \Y $not$libresoc.v:202360$14316_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $not$libresoc.v:199674$14333 + cell $not $not$libresoc.v:202363$14319 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:199674$14333_Y + connect \Y $not$libresoc.v:202363$14319_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $not$libresoc.v:199680$14339 + cell $not $not$libresoc.v:202369$14325 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \alu_trap0_n_ready_i - connect \Y $not$libresoc.v:199680$14339_Y + connect \Y $not$libresoc.v:202369$14325_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $not$libresoc.v:199695$14354 + cell $not $not$libresoc.v:202384$14340 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_rd__rel_o - connect \Y $not$libresoc.v:199695$14354_Y + connect \Y $not$libresoc.v:202384$14340_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $not$libresoc.v:199711$14370 + cell $not $not$libresoc.v:202400$14356 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \cu_rdmaskn_i - connect \Y $not$libresoc.v:199711$14370_Y + connect \Y $not$libresoc.v:202400$14356_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $or$libresoc.v:199678$14337 + cell $or $or$libresoc.v:202367$14323 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413566,10 +386583,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \$33 connect \B \$35 - connect \Y $or$libresoc.v:199678$14337_Y + connect \Y $or$libresoc.v:202367$14323_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $or$libresoc.v:199689$14348 + cell $or $or$libresoc.v:202378$14334 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413577,10 +386594,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \req_done connect \B \cu_go_die_i - connect \Y $or$libresoc.v:199689$14348_Y + connect \Y $or$libresoc.v:202378$14334_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $or$libresoc.v:199690$14349 + cell $or $or$libresoc.v:202379$14335 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -413588,10 +386605,10 @@ module \trap0 parameter \Y_WIDTH 1 connect \A \cu_issue_i connect \B \cu_go_die_i - connect \Y $or$libresoc.v:199690$14349_Y + connect \Y $or$libresoc.v:202379$14335_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $or$libresoc.v:199691$14350 + cell $or $or$libresoc.v:202380$14336 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -413599,10 +386616,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \cu_wr__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:199691$14350_Y + connect \Y $or$libresoc.v:202380$14336_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $or$libresoc.v:199692$14351 + cell $or $or$libresoc.v:202381$14337 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -413610,10 +386627,10 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \cu_rd__go_i connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $or$libresoc.v:199692$14351_Y + connect \Y $or$libresoc.v:202381$14337_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $or$libresoc.v:199696$14355 + cell $or $or$libresoc.v:202385$14341 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \B_SIGNED 0 @@ -413621,10 +386638,10 @@ module \trap0 parameter \Y_WIDTH 5 connect \A \reset_w connect \B \prev_wr_go - connect \Y $or$libresoc.v:199696$14355_Y + connect \Y $or$libresoc.v:202385$14341_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $or$libresoc.v:199706$14365 + cell $or $or$libresoc.v:202395$14351 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -413632,74 +386649,74 @@ module \trap0 parameter \Y_WIDTH 4 connect \A \$6 connect \B \cu_rd__go_i - connect \Y $or$libresoc.v:199706$14365_Y + connect \Y $or$libresoc.v:202395$14351_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $reduce_and$libresoc.v:199651$14310 + cell $reduce_and $reduce_and$libresoc.v:202340$14296 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $reduce_and$libresoc.v:199651$14310_Y + connect \Y $reduce_and$libresoc.v:202340$14296_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_or $reduce_or$libresoc.v:199673$14332 + cell $reduce_or $reduce_or$libresoc.v:202362$14318 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \$27 - connect \Y $reduce_or$libresoc.v:199673$14332_Y + connect \Y $reduce_or$libresoc.v:202362$14318_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:199676$14335 + cell $reduce_or $reduce_or$libresoc.v:202365$14321 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \cu_wr__go_i - connect \Y $reduce_or$libresoc.v:199676$14335_Y + connect \Y $reduce_or$libresoc.v:202365$14321_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_or $reduce_or$libresoc.v:199677$14336 + cell $reduce_or $reduce_or$libresoc.v:202366$14322 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \prev_wr_go - connect \Y $reduce_or$libresoc.v:199677$14336_Y + connect \Y $reduce_or$libresoc.v:202366$14322_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:199702$14361 + cell $mux $ternary$libresoc.v:202391$14347 parameter \WIDTH 64 connect \A \src_r0 connect \B \src1_i connect \S \src_l_q_src [0] - connect \Y $ternary$libresoc.v:199702$14361_Y + connect \Y $ternary$libresoc.v:202391$14347_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:199703$14362 + cell $mux $ternary$libresoc.v:202392$14348 parameter \WIDTH 64 connect \A \src_r1 connect \B \src2_i connect \S \src_l_q_src [1] - connect \Y $ternary$libresoc.v:199703$14362_Y + connect \Y $ternary$libresoc.v:202392$14348_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:199704$14363 + cell $mux $ternary$libresoc.v:202393$14349 parameter \WIDTH 64 connect \A \src_r2 connect \B \src3_i connect \S \src_l_q_src [2] - connect \Y $ternary$libresoc.v:199704$14363_Y + connect \Y $ternary$libresoc.v:202393$14349_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:47" - cell $mux $ternary$libresoc.v:199705$14364 + cell $mux $ternary$libresoc.v:202394$14350 parameter \WIDTH 64 connect \A \src_r3 connect \B \src4_i connect \S \src_l_q_src [3] - connect \Y $ternary$libresoc.v:199705$14364_Y + connect \Y $ternary$libresoc.v:202394$14350_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:199788.14-199794.4" + attribute \src "libresoc.v:202477.14-202483.4" cell \alu_l$45 \alu_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -413708,7 +386725,7 @@ module \trap0 connect \s_alu \alu_l_s_alu end attribute \module_not_derived 1 - attribute \src "libresoc.v:199795.13-199825.4" + attribute \src "libresoc.v:202484.13-202514.4" cell \alu_trap0 \alu_trap0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -413741,7 +386758,7 @@ module \trap0 connect \trap_op__traptype \alu_trap0_trap_op__traptype end attribute \module_not_derived 1 - attribute \src "libresoc.v:199826.15-199832.4" + attribute \src "libresoc.v:202515.15-202521.4" cell \alui_l$44 \alui_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -413750,7 +386767,7 @@ module \trap0 connect \s_alui \alui_l_s_alui end attribute \module_not_derived 1 - attribute \src "libresoc.v:199833.14-199839.4" + attribute \src "libresoc.v:202522.14-202528.4" cell \opc_l$40 \opc_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -413759,7 +386776,7 @@ module \trap0 connect \s_opc \opc_l_s_opc end attribute \module_not_derived 1 - attribute \src "libresoc.v:199840.14-199846.4" + attribute \src "libresoc.v:202529.14-202535.4" cell \req_l$41 \req_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -413768,7 +386785,7 @@ module \trap0 connect \s_req \req_l_s_req end attribute \module_not_derived 1 - attribute \src "libresoc.v:199847.14-199853.4" + attribute \src "libresoc.v:202536.14-202542.4" cell \rok_l$43 \rok_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -413777,7 +386794,7 @@ module \trap0 connect \s_rdok \rok_l_s_rdok end attribute \module_not_derived 1 - attribute \src "libresoc.v:199854.14-199859.4" + attribute \src "libresoc.v:202543.14-202548.4" cell \rst_l$42 \rst_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -413785,7 +386802,7 @@ module \trap0 connect \s_rst \rst_l_s_rst end attribute \module_not_derived 1 - attribute \src "libresoc.v:199860.14-199866.4" + attribute \src "libresoc.v:202549.14-202555.4" cell \src_l$39 \src_l connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -413793,592 +386810,592 @@ module \trap0 connect \r_src \src_l_r_src connect \s_src \src_l_s_src end - attribute \src "libresoc.v:199051.7-199051.20" - process $proc$libresoc.v:199051$14525 + attribute \src "libresoc.v:201740.7-201740.20" + process $proc$libresoc.v:201740$14511 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:199177.7-199177.24" - process $proc$libresoc.v:199177$14526 + attribute \src "libresoc.v:201866.7-201866.24" + process $proc$libresoc.v:201866$14512 assign { } { } assign $1\all_rd_dly[0:0] 1'0 sync always sync init update \all_rd_dly $1\all_rd_dly[0:0] end - attribute \src "libresoc.v:199187.7-199187.26" - process $proc$libresoc.v:199187$14527 + attribute \src "libresoc.v:201876.7-201876.26" + process $proc$libresoc.v:201876$14513 assign { } { } assign $1\alu_done_dly[0:0] 1'0 sync always sync init update \alu_done_dly $1\alu_done_dly[0:0] end - attribute \src "libresoc.v:199195.7-199195.25" - process $proc$libresoc.v:199195$14528 + attribute \src "libresoc.v:201884.7-201884.25" + process $proc$libresoc.v:201884$14514 assign { } { } assign $1\alu_l_r_alu[0:0] 1'1 sync always sync init update \alu_l_r_alu $1\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:199231.14-199231.59" - process $proc$libresoc.v:199231$14529 + attribute \src "libresoc.v:201920.14-201920.59" + process $proc$libresoc.v:201920$14515 assign { } { } assign $1\alu_trap0_trap_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_trap0_trap_op__cia $1\alu_trap0_trap_op__cia[63:0] end - attribute \src "libresoc.v:199250.14-199250.51" - process $proc$libresoc.v:199250$14530 + attribute \src "libresoc.v:201939.14-201939.51" + process $proc$libresoc.v:201939$14516 assign { } { } assign $1\alu_trap0_trap_op__fn_unit[13:0] 14'00000000000000 sync always sync init update \alu_trap0_trap_op__fn_unit $1\alu_trap0_trap_op__fn_unit[13:0] end - attribute \src "libresoc.v:199254.14-199254.45" - process $proc$libresoc.v:199254$14531 + attribute \src "libresoc.v:201943.14-201943.45" + process $proc$libresoc.v:201943$14517 assign { } { } assign $1\alu_trap0_trap_op__insn[31:0] 0 sync always sync init update \alu_trap0_trap_op__insn $1\alu_trap0_trap_op__insn[31:0] end - attribute \src "libresoc.v:199333.13-199333.49" - process $proc$libresoc.v:199333$14532 + attribute \src "libresoc.v:202022.13-202022.49" + process $proc$libresoc.v:202022$14518 assign { } { } assign $1\alu_trap0_trap_op__insn_type[6:0] 7'0000000 sync always sync init update \alu_trap0_trap_op__insn_type $1\alu_trap0_trap_op__insn_type[6:0] end - attribute \src "libresoc.v:199337.7-199337.41" - process $proc$libresoc.v:199337$14533 + attribute \src "libresoc.v:202026.7-202026.41" + process $proc$libresoc.v:202026$14519 assign { } { } assign $1\alu_trap0_trap_op__is_32bit[0:0] 1'0 sync always sync init update \alu_trap0_trap_op__is_32bit $1\alu_trap0_trap_op__is_32bit[0:0] end - attribute \src "libresoc.v:199341.13-199341.48" - process $proc$libresoc.v:199341$14534 + attribute \src "libresoc.v:202030.13-202030.48" + process $proc$libresoc.v:202030$14520 assign { } { } assign $1\alu_trap0_trap_op__ldst_exc[7:0] 8'00000000 sync always sync init update \alu_trap0_trap_op__ldst_exc $1\alu_trap0_trap_op__ldst_exc[7:0] end - attribute \src "libresoc.v:199345.14-199345.59" - process $proc$libresoc.v:199345$14535 + attribute \src "libresoc.v:202034.14-202034.59" + process $proc$libresoc.v:202034$14521 assign { } { } assign $1\alu_trap0_trap_op__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \alu_trap0_trap_op__msr $1\alu_trap0_trap_op__msr[63:0] end - attribute \src "libresoc.v:199349.14-199349.52" - process $proc$libresoc.v:199349$14536 + attribute \src "libresoc.v:202038.14-202038.52" + process $proc$libresoc.v:202038$14522 assign { } { } assign $1\alu_trap0_trap_op__trapaddr[12:0] 13'0000000000000 sync always sync init update \alu_trap0_trap_op__trapaddr $1\alu_trap0_trap_op__trapaddr[12:0] end - attribute \src "libresoc.v:199353.13-199353.48" - process $proc$libresoc.v:199353$14537 + attribute \src "libresoc.v:202042.13-202042.48" + process $proc$libresoc.v:202042$14523 assign { } { } assign $1\alu_trap0_trap_op__traptype[7:0] 8'00000000 sync always sync init update \alu_trap0_trap_op__traptype $1\alu_trap0_trap_op__traptype[7:0] end - attribute \src "libresoc.v:199359.7-199359.27" - process $proc$libresoc.v:199359$14538 + attribute \src "libresoc.v:202048.7-202048.27" + process $proc$libresoc.v:202048$14524 assign { } { } assign $1\alui_l_r_alui[0:0] 1'1 sync always sync init update \alui_l_r_alui $1\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:199391.14-199391.47" - process $proc$libresoc.v:199391$14539 + attribute \src "libresoc.v:202080.14-202080.47" + process $proc$libresoc.v:202080$14525 assign { } { } assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r0__o $1\data_r0__o[63:0] end - attribute \src "libresoc.v:199395.7-199395.27" - process $proc$libresoc.v:199395$14540 + attribute \src "libresoc.v:202084.7-202084.27" + process $proc$libresoc.v:202084$14526 assign { } { } assign $1\data_r0__o_ok[0:0] 1'0 sync always sync init update \data_r0__o_ok $1\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:199399.14-199399.51" - process $proc$libresoc.v:199399$14541 + attribute \src "libresoc.v:202088.14-202088.51" + process $proc$libresoc.v:202088$14527 assign { } { } assign $1\data_r1__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r1__fast1 $1\data_r1__fast1[63:0] end - attribute \src "libresoc.v:199403.7-199403.31" - process $proc$libresoc.v:199403$14542 + attribute \src "libresoc.v:202092.7-202092.31" + process $proc$libresoc.v:202092$14528 assign { } { } assign $1\data_r1__fast1_ok[0:0] 1'0 sync always sync init update \data_r1__fast1_ok $1\data_r1__fast1_ok[0:0] end - attribute \src "libresoc.v:199407.14-199407.51" - process $proc$libresoc.v:199407$14543 + attribute \src "libresoc.v:202096.14-202096.51" + process $proc$libresoc.v:202096$14529 assign { } { } assign $1\data_r2__fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r2__fast2 $1\data_r2__fast2[63:0] end - attribute \src "libresoc.v:199411.7-199411.31" - process $proc$libresoc.v:199411$14544 + attribute \src "libresoc.v:202100.7-202100.31" + process $proc$libresoc.v:202100$14530 assign { } { } assign $1\data_r2__fast2_ok[0:0] 1'0 sync always sync init update \data_r2__fast2_ok $1\data_r2__fast2_ok[0:0] end - attribute \src "libresoc.v:199415.14-199415.49" - process $proc$libresoc.v:199415$14545 + attribute \src "libresoc.v:202104.14-202104.49" + process $proc$libresoc.v:202104$14531 assign { } { } assign $1\data_r3__nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r3__nia $1\data_r3__nia[63:0] end - attribute \src "libresoc.v:199419.7-199419.29" - process $proc$libresoc.v:199419$14546 + attribute \src "libresoc.v:202108.7-202108.29" + process $proc$libresoc.v:202108$14532 assign { } { } assign $1\data_r3__nia_ok[0:0] 1'0 sync always sync init update \data_r3__nia_ok $1\data_r3__nia_ok[0:0] end - attribute \src "libresoc.v:199423.14-199423.49" - process $proc$libresoc.v:199423$14547 + attribute \src "libresoc.v:202112.14-202112.49" + process $proc$libresoc.v:202112$14533 assign { } { } assign $1\data_r4__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \data_r4__msr $1\data_r4__msr[63:0] end - attribute \src "libresoc.v:199427.7-199427.29" - process $proc$libresoc.v:199427$14548 + attribute \src "libresoc.v:202116.7-202116.29" + process $proc$libresoc.v:202116$14534 assign { } { } assign $1\data_r4__msr_ok[0:0] 1'0 sync always sync init update \data_r4__msr_ok $1\data_r4__msr_ok[0:0] end - attribute \src "libresoc.v:199458.7-199458.25" - process $proc$libresoc.v:199458$14549 + attribute \src "libresoc.v:202147.7-202147.25" + process $proc$libresoc.v:202147$14535 assign { } { } assign $1\opc_l_r_opc[0:0] 1'1 sync always sync init update \opc_l_r_opc $1\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:199462.7-199462.25" - process $proc$libresoc.v:199462$14550 + attribute \src "libresoc.v:202151.7-202151.25" + process $proc$libresoc.v:202151$14536 assign { } { } assign $1\opc_l_s_opc[0:0] 1'0 sync always sync init update \opc_l_s_opc $1\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:199574.13-199574.31" - process $proc$libresoc.v:199574$14551 + attribute \src "libresoc.v:202263.13-202263.31" + process $proc$libresoc.v:202263$14537 assign { } { } assign $1\prev_wr_go[4:0] 5'00000 sync always sync init update \prev_wr_go $1\prev_wr_go[4:0] end - attribute \src "libresoc.v:199582.13-199582.32" - process $proc$libresoc.v:199582$14552 + attribute \src "libresoc.v:202271.13-202271.32" + process $proc$libresoc.v:202271$14538 assign { } { } assign $1\req_l_r_req[4:0] 5'11111 sync always sync init update \req_l_r_req $1\req_l_r_req[4:0] end - attribute \src "libresoc.v:199586.13-199586.32" - process $proc$libresoc.v:199586$14553 + attribute \src "libresoc.v:202275.13-202275.32" + process $proc$libresoc.v:202275$14539 assign { } { } assign $1\req_l_s_req[4:0] 5'00000 sync always sync init update \req_l_s_req $1\req_l_s_req[4:0] end - attribute \src "libresoc.v:199598.7-199598.26" - process $proc$libresoc.v:199598$14554 + attribute \src "libresoc.v:202287.7-202287.26" + process $proc$libresoc.v:202287$14540 assign { } { } assign $1\rok_l_r_rdok[0:0] 1'1 sync always sync init update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:199602.7-199602.26" - process $proc$libresoc.v:199602$14555 + attribute \src "libresoc.v:202291.7-202291.26" + process $proc$libresoc.v:202291$14541 assign { } { } assign $1\rok_l_s_rdok[0:0] 1'0 sync always sync init update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:199606.7-199606.25" - process $proc$libresoc.v:199606$14556 + attribute \src "libresoc.v:202295.7-202295.25" + process $proc$libresoc.v:202295$14542 assign { } { } assign $1\rst_l_r_rst[0:0] 1'1 sync always sync init update \rst_l_r_rst $1\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:199610.7-199610.25" - process $proc$libresoc.v:199610$14557 + attribute \src "libresoc.v:202299.7-202299.25" + process $proc$libresoc.v:202299$14543 assign { } { } assign $1\rst_l_s_rst[0:0] 1'0 sync always sync init update \rst_l_s_rst $1\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:199626.13-199626.31" - process $proc$libresoc.v:199626$14558 + attribute \src "libresoc.v:202315.13-202315.31" + process $proc$libresoc.v:202315$14544 assign { } { } assign $1\src_l_r_src[3:0] 4'1111 sync always sync init update \src_l_r_src $1\src_l_r_src[3:0] end - attribute \src "libresoc.v:199630.13-199630.31" - process $proc$libresoc.v:199630$14559 + attribute \src "libresoc.v:202319.13-202319.31" + process $proc$libresoc.v:202319$14545 assign { } { } assign $1\src_l_s_src[3:0] 4'0000 sync always sync init update \src_l_s_src $1\src_l_s_src[3:0] end - attribute \src "libresoc.v:199634.14-199634.43" - process $proc$libresoc.v:199634$14560 + attribute \src "libresoc.v:202323.14-202323.43" + process $proc$libresoc.v:202323$14546 assign { } { } assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r0 $1\src_r0[63:0] end - attribute \src "libresoc.v:199638.14-199638.43" - process $proc$libresoc.v:199638$14561 + attribute \src "libresoc.v:202327.14-202327.43" + process $proc$libresoc.v:202327$14547 assign { } { } assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r1 $1\src_r1[63:0] end - attribute \src "libresoc.v:199642.14-199642.43" - process $proc$libresoc.v:199642$14562 + attribute \src "libresoc.v:202331.14-202331.43" + process $proc$libresoc.v:202331$14548 assign { } { } assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r2 $1\src_r2[63:0] end - attribute \src "libresoc.v:199646.14-199646.43" - process $proc$libresoc.v:199646$14563 + attribute \src "libresoc.v:202335.14-202335.43" + process $proc$libresoc.v:202335$14549 assign { } { } assign $1\src_r3[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 sync always sync init update \src_r3 $1\src_r3[63:0] end - attribute \src "libresoc.v:199712.3-199713.39" - process $proc$libresoc.v:199712$14371 + attribute \src "libresoc.v:202401.3-202402.39" + process $proc$libresoc.v:202401$14357 assign { } { } assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next sync posedge \coresync_clk update \alu_l_r_alu $0\alu_l_r_alu[0:0] end - attribute \src "libresoc.v:199714.3-199715.43" - process $proc$libresoc.v:199714$14372 + attribute \src "libresoc.v:202403.3-202404.43" + process $proc$libresoc.v:202403$14358 assign { } { } assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next sync posedge \coresync_clk update \alui_l_r_alui $0\alui_l_r_alui[0:0] end - attribute \src "libresoc.v:199716.3-199717.29" - process $proc$libresoc.v:199716$14373 + attribute \src "libresoc.v:202405.3-202406.29" + process $proc$libresoc.v:202405$14359 assign { } { } assign $0\src_r3[63:0] \src_r3$next sync posedge \coresync_clk update \src_r3 $0\src_r3[63:0] end - attribute \src "libresoc.v:199718.3-199719.29" - process $proc$libresoc.v:199718$14374 + attribute \src "libresoc.v:202407.3-202408.29" + process $proc$libresoc.v:202407$14360 assign { } { } assign $0\src_r2[63:0] \src_r2$next sync posedge \coresync_clk update \src_r2 $0\src_r2[63:0] end - attribute \src "libresoc.v:199720.3-199721.29" - process $proc$libresoc.v:199720$14375 + attribute \src "libresoc.v:202409.3-202410.29" + process $proc$libresoc.v:202409$14361 assign { } { } assign $0\src_r1[63:0] \src_r1$next sync posedge \coresync_clk update \src_r1 $0\src_r1[63:0] end - attribute \src "libresoc.v:199722.3-199723.29" - process $proc$libresoc.v:199722$14376 + attribute \src "libresoc.v:202411.3-202412.29" + process $proc$libresoc.v:202411$14362 assign { } { } assign $0\src_r0[63:0] \src_r0$next sync posedge \coresync_clk update \src_r0 $0\src_r0[63:0] end - attribute \src "libresoc.v:199724.3-199725.41" - process $proc$libresoc.v:199724$14377 + attribute \src "libresoc.v:202413.3-202414.41" + process $proc$libresoc.v:202413$14363 assign { } { } assign $0\data_r4__msr[63:0] \data_r4__msr$next sync posedge \coresync_clk update \data_r4__msr $0\data_r4__msr[63:0] end - attribute \src "libresoc.v:199726.3-199727.47" - process $proc$libresoc.v:199726$14378 + attribute \src "libresoc.v:202415.3-202416.47" + process $proc$libresoc.v:202415$14364 assign { } { } assign $0\data_r4__msr_ok[0:0] \data_r4__msr_ok$next sync posedge \coresync_clk update \data_r4__msr_ok $0\data_r4__msr_ok[0:0] end - attribute \src "libresoc.v:199728.3-199729.41" - process $proc$libresoc.v:199728$14379 + attribute \src "libresoc.v:202417.3-202418.41" + process $proc$libresoc.v:202417$14365 assign { } { } assign $0\data_r3__nia[63:0] \data_r3__nia$next sync posedge \coresync_clk update \data_r3__nia $0\data_r3__nia[63:0] end - attribute \src "libresoc.v:199730.3-199731.47" - process $proc$libresoc.v:199730$14380 + attribute \src "libresoc.v:202419.3-202420.47" + process $proc$libresoc.v:202419$14366 assign { } { } assign $0\data_r3__nia_ok[0:0] \data_r3__nia_ok$next sync posedge \coresync_clk update \data_r3__nia_ok $0\data_r3__nia_ok[0:0] end - attribute \src "libresoc.v:199732.3-199733.45" - process $proc$libresoc.v:199732$14381 + attribute \src "libresoc.v:202421.3-202422.45" + process $proc$libresoc.v:202421$14367 assign { } { } assign $0\data_r2__fast2[63:0] \data_r2__fast2$next sync posedge \coresync_clk update \data_r2__fast2 $0\data_r2__fast2[63:0] end - attribute \src "libresoc.v:199734.3-199735.51" - process $proc$libresoc.v:199734$14382 + attribute \src "libresoc.v:202423.3-202424.51" + process $proc$libresoc.v:202423$14368 assign { } { } assign $0\data_r2__fast2_ok[0:0] \data_r2__fast2_ok$next sync posedge \coresync_clk update \data_r2__fast2_ok $0\data_r2__fast2_ok[0:0] end - attribute \src "libresoc.v:199736.3-199737.45" - process $proc$libresoc.v:199736$14383 + attribute \src "libresoc.v:202425.3-202426.45" + process $proc$libresoc.v:202425$14369 assign { } { } assign $0\data_r1__fast1[63:0] \data_r1__fast1$next sync posedge \coresync_clk update \data_r1__fast1 $0\data_r1__fast1[63:0] end - attribute \src "libresoc.v:199738.3-199739.51" - process $proc$libresoc.v:199738$14384 + attribute \src "libresoc.v:202427.3-202428.51" + process $proc$libresoc.v:202427$14370 assign { } { } assign $0\data_r1__fast1_ok[0:0] \data_r1__fast1_ok$next sync posedge \coresync_clk update \data_r1__fast1_ok $0\data_r1__fast1_ok[0:0] end - attribute \src "libresoc.v:199740.3-199741.37" - process $proc$libresoc.v:199740$14385 + attribute \src "libresoc.v:202429.3-202430.37" + process $proc$libresoc.v:202429$14371 assign { } { } assign $0\data_r0__o[63:0] \data_r0__o$next sync posedge \coresync_clk update \data_r0__o $0\data_r0__o[63:0] end - attribute \src "libresoc.v:199742.3-199743.43" - process $proc$libresoc.v:199742$14386 + attribute \src "libresoc.v:202431.3-202432.43" + process $proc$libresoc.v:202431$14372 assign { } { } assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next sync posedge \coresync_clk update \data_r0__o_ok $0\data_r0__o_ok[0:0] end - attribute \src "libresoc.v:199744.3-199745.73" - process $proc$libresoc.v:199744$14387 + attribute \src "libresoc.v:202433.3-202434.73" + process $proc$libresoc.v:202433$14373 assign { } { } assign $0\alu_trap0_trap_op__insn_type[6:0] \alu_trap0_trap_op__insn_type$next sync posedge \coresync_clk update \alu_trap0_trap_op__insn_type $0\alu_trap0_trap_op__insn_type[6:0] end - attribute \src "libresoc.v:199746.3-199747.69" - process $proc$libresoc.v:199746$14388 + attribute \src "libresoc.v:202435.3-202436.69" + process $proc$libresoc.v:202435$14374 assign { } { } assign $0\alu_trap0_trap_op__fn_unit[13:0] \alu_trap0_trap_op__fn_unit$next sync posedge \coresync_clk update \alu_trap0_trap_op__fn_unit $0\alu_trap0_trap_op__fn_unit[13:0] end - attribute \src "libresoc.v:199748.3-199749.63" - process $proc$libresoc.v:199748$14389 + attribute \src "libresoc.v:202437.3-202438.63" + process $proc$libresoc.v:202437$14375 assign { } { } assign $0\alu_trap0_trap_op__insn[31:0] \alu_trap0_trap_op__insn$next sync posedge \coresync_clk update \alu_trap0_trap_op__insn $0\alu_trap0_trap_op__insn[31:0] end - attribute \src "libresoc.v:199750.3-199751.61" - process $proc$libresoc.v:199750$14390 + attribute \src "libresoc.v:202439.3-202440.61" + process $proc$libresoc.v:202439$14376 assign { } { } assign $0\alu_trap0_trap_op__msr[63:0] \alu_trap0_trap_op__msr$next sync posedge \coresync_clk update \alu_trap0_trap_op__msr $0\alu_trap0_trap_op__msr[63:0] end - attribute \src "libresoc.v:199752.3-199753.61" - process $proc$libresoc.v:199752$14391 + attribute \src "libresoc.v:202441.3-202442.61" + process $proc$libresoc.v:202441$14377 assign { } { } assign $0\alu_trap0_trap_op__cia[63:0] \alu_trap0_trap_op__cia$next sync posedge \coresync_clk update \alu_trap0_trap_op__cia $0\alu_trap0_trap_op__cia[63:0] end - attribute \src "libresoc.v:199754.3-199755.71" - process $proc$libresoc.v:199754$14392 + attribute \src "libresoc.v:202443.3-202444.71" + process $proc$libresoc.v:202443$14378 assign { } { } assign $0\alu_trap0_trap_op__is_32bit[0:0] \alu_trap0_trap_op__is_32bit$next sync posedge \coresync_clk update \alu_trap0_trap_op__is_32bit $0\alu_trap0_trap_op__is_32bit[0:0] end - attribute \src "libresoc.v:199756.3-199757.71" - process $proc$libresoc.v:199756$14393 + attribute \src "libresoc.v:202445.3-202446.71" + process $proc$libresoc.v:202445$14379 assign { } { } assign $0\alu_trap0_trap_op__traptype[7:0] \alu_trap0_trap_op__traptype$next sync posedge \coresync_clk update \alu_trap0_trap_op__traptype $0\alu_trap0_trap_op__traptype[7:0] end - attribute \src "libresoc.v:199758.3-199759.71" - process $proc$libresoc.v:199758$14394 + attribute \src "libresoc.v:202447.3-202448.71" + process $proc$libresoc.v:202447$14380 assign { } { } assign $0\alu_trap0_trap_op__trapaddr[12:0] \alu_trap0_trap_op__trapaddr$next sync posedge \coresync_clk update \alu_trap0_trap_op__trapaddr $0\alu_trap0_trap_op__trapaddr[12:0] end - attribute \src "libresoc.v:199760.3-199761.71" - process $proc$libresoc.v:199760$14395 + attribute \src "libresoc.v:202449.3-202450.71" + process $proc$libresoc.v:202449$14381 assign { } { } assign $0\alu_trap0_trap_op__ldst_exc[7:0] \alu_trap0_trap_op__ldst_exc$next sync posedge \coresync_clk update \alu_trap0_trap_op__ldst_exc $0\alu_trap0_trap_op__ldst_exc[7:0] end - attribute \src "libresoc.v:199762.3-199763.39" - process $proc$libresoc.v:199762$14396 + attribute \src "libresoc.v:202451.3-202452.39" + process $proc$libresoc.v:202451$14382 assign { } { } assign $0\req_l_r_req[4:0] \req_l_r_req$next sync posedge \coresync_clk update \req_l_r_req $0\req_l_r_req[4:0] end - attribute \src "libresoc.v:199764.3-199765.39" - process $proc$libresoc.v:199764$14397 + attribute \src "libresoc.v:202453.3-202454.39" + process $proc$libresoc.v:202453$14383 assign { } { } assign $0\req_l_s_req[4:0] \req_l_s_req$next sync posedge \coresync_clk update \req_l_s_req $0\req_l_s_req[4:0] end - attribute \src "libresoc.v:199766.3-199767.39" - process $proc$libresoc.v:199766$14398 + attribute \src "libresoc.v:202455.3-202456.39" + process $proc$libresoc.v:202455$14384 assign { } { } assign $0\src_l_r_src[3:0] \src_l_r_src$next sync posedge \coresync_clk update \src_l_r_src $0\src_l_r_src[3:0] end - attribute \src "libresoc.v:199768.3-199769.39" - process $proc$libresoc.v:199768$14399 + attribute \src "libresoc.v:202457.3-202458.39" + process $proc$libresoc.v:202457$14385 assign { } { } assign $0\src_l_s_src[3:0] \src_l_s_src$next sync posedge \coresync_clk update \src_l_s_src $0\src_l_s_src[3:0] end - attribute \src "libresoc.v:199770.3-199771.39" - process $proc$libresoc.v:199770$14400 + attribute \src "libresoc.v:202459.3-202460.39" + process $proc$libresoc.v:202459$14386 assign { } { } assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next sync posedge \coresync_clk update \opc_l_r_opc $0\opc_l_r_opc[0:0] end - attribute \src "libresoc.v:199772.3-199773.39" - process $proc$libresoc.v:199772$14401 + attribute \src "libresoc.v:202461.3-202462.39" + process $proc$libresoc.v:202461$14387 assign { } { } assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next sync posedge \coresync_clk update \opc_l_s_opc $0\opc_l_s_opc[0:0] end - attribute \src "libresoc.v:199774.3-199775.39" - process $proc$libresoc.v:199774$14402 + attribute \src "libresoc.v:202463.3-202464.39" + process $proc$libresoc.v:202463$14388 assign { } { } assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next sync posedge \coresync_clk update \rst_l_r_rst $0\rst_l_r_rst[0:0] end - attribute \src "libresoc.v:199776.3-199777.39" - process $proc$libresoc.v:199776$14403 + attribute \src "libresoc.v:202465.3-202466.39" + process $proc$libresoc.v:202465$14389 assign { } { } assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next sync posedge \coresync_clk update \rst_l_s_rst $0\rst_l_s_rst[0:0] end - attribute \src "libresoc.v:199778.3-199779.41" - process $proc$libresoc.v:199778$14404 + attribute \src "libresoc.v:202467.3-202468.41" + process $proc$libresoc.v:202467$14390 assign { } { } assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next sync posedge \coresync_clk update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] end - attribute \src "libresoc.v:199780.3-199781.41" - process $proc$libresoc.v:199780$14405 + attribute \src "libresoc.v:202469.3-202470.41" + process $proc$libresoc.v:202469$14391 assign { } { } assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next sync posedge \coresync_clk update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] end - attribute \src "libresoc.v:199782.3-199783.37" - process $proc$libresoc.v:199782$14406 + attribute \src "libresoc.v:202471.3-202472.37" + process $proc$libresoc.v:202471$14392 assign { } { } assign $0\prev_wr_go[4:0] \prev_wr_go$next sync posedge \coresync_clk update \prev_wr_go $0\prev_wr_go[4:0] end - attribute \src "libresoc.v:199784.3-199785.41" - process $proc$libresoc.v:199784$14407 + attribute \src "libresoc.v:202473.3-202474.41" + process $proc$libresoc.v:202473$14393 assign { } { } assign $0\alu_done_dly[0:0] \alu_trap0_n_valid_o sync posedge \coresync_clk update \alu_done_dly $0\alu_done_dly[0:0] end - attribute \src "libresoc.v:199786.3-199787.25" - process $proc$libresoc.v:199786$14408 + attribute \src "libresoc.v:202475.3-202476.25" + process $proc$libresoc.v:202475$14394 assign { } { } assign $0\all_rd_dly[0:0] \$11 sync posedge \coresync_clk update \all_rd_dly $0\all_rd_dly[0:0] end - attribute \src "libresoc.v:199867.3-199876.6" - process $proc$libresoc.v:199867$14409 + attribute \src "libresoc.v:202556.3-202565.6" + process $proc$libresoc.v:202556$14395 assign { } { } assign { } { } assign $0\req_done[0:0] $1\req_done[0:0] - attribute \src "libresoc.v:199868.5-199868.29" + attribute \src "libresoc.v:202557.5-202557.29" switch \initial - attribute \src "libresoc.v:199868.9-199868.17" + attribute \src "libresoc.v:202557.9-202557.17" case 1'1 case end @@ -414394,14 +387411,14 @@ module \trap0 sync always update \req_done $0\req_done[0:0] end - attribute \src "libresoc.v:199877.3-199885.6" - process $proc$libresoc.v:199877$14410 + attribute \src "libresoc.v:202566.3-202574.6" + process $proc$libresoc.v:202566$14396 assign { } { } assign { } { } - assign $0\rok_l_s_rdok$next[0:0]$14411 $1\rok_l_s_rdok$next[0:0]$14412 - attribute \src "libresoc.v:199878.5-199878.29" + assign $0\rok_l_s_rdok$next[0:0]$14397 $1\rok_l_s_rdok$next[0:0]$14398 + attribute \src "libresoc.v:202567.5-202567.29" switch \initial - attribute \src "libresoc.v:199878.9-199878.17" + attribute \src "libresoc.v:202567.9-202567.17" case 1'1 case end @@ -414410,21 +387427,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_s_rdok$next[0:0]$14412 1'0 + assign $1\rok_l_s_rdok$next[0:0]$14398 1'0 case - assign $1\rok_l_s_rdok$next[0:0]$14412 \cu_issue_i + assign $1\rok_l_s_rdok$next[0:0]$14398 \cu_issue_i end sync always - update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$14411 + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$14397 end - attribute \src "libresoc.v:199886.3-199894.6" - process $proc$libresoc.v:199886$14413 + attribute \src "libresoc.v:202575.3-202583.6" + process $proc$libresoc.v:202575$14399 assign { } { } assign { } { } - assign $0\rok_l_r_rdok$next[0:0]$14414 $1\rok_l_r_rdok$next[0:0]$14415 - attribute \src "libresoc.v:199887.5-199887.29" + assign $0\rok_l_r_rdok$next[0:0]$14400 $1\rok_l_r_rdok$next[0:0]$14401 + attribute \src "libresoc.v:202576.5-202576.29" switch \initial - attribute \src "libresoc.v:199887.9-199887.17" + attribute \src "libresoc.v:202576.9-202576.17" case 1'1 case end @@ -414433,21 +387450,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rok_l_r_rdok$next[0:0]$14415 1'1 + assign $1\rok_l_r_rdok$next[0:0]$14401 1'1 case - assign $1\rok_l_r_rdok$next[0:0]$14415 \$65 + assign $1\rok_l_r_rdok$next[0:0]$14401 \$65 end sync always - update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$14414 + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$14400 end - attribute \src "libresoc.v:199895.3-199903.6" - process $proc$libresoc.v:199895$14416 + attribute \src "libresoc.v:202584.3-202592.6" + process $proc$libresoc.v:202584$14402 assign { } { } assign { } { } - assign $0\rst_l_s_rst$next[0:0]$14417 $1\rst_l_s_rst$next[0:0]$14418 - attribute \src "libresoc.v:199896.5-199896.29" + assign $0\rst_l_s_rst$next[0:0]$14403 $1\rst_l_s_rst$next[0:0]$14404 + attribute \src "libresoc.v:202585.5-202585.29" switch \initial - attribute \src "libresoc.v:199896.9-199896.17" + attribute \src "libresoc.v:202585.9-202585.17" case 1'1 case end @@ -414456,21 +387473,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_s_rst$next[0:0]$14418 1'0 + assign $1\rst_l_s_rst$next[0:0]$14404 1'0 case - assign $1\rst_l_s_rst$next[0:0]$14418 \all_rd + assign $1\rst_l_s_rst$next[0:0]$14404 \all_rd end sync always - update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$14417 + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$14403 end - attribute \src "libresoc.v:199904.3-199912.6" - process $proc$libresoc.v:199904$14419 + attribute \src "libresoc.v:202593.3-202601.6" + process $proc$libresoc.v:202593$14405 assign { } { } assign { } { } - assign $0\rst_l_r_rst$next[0:0]$14420 $1\rst_l_r_rst$next[0:0]$14421 - attribute \src "libresoc.v:199905.5-199905.29" + assign $0\rst_l_r_rst$next[0:0]$14406 $1\rst_l_r_rst$next[0:0]$14407 + attribute \src "libresoc.v:202594.5-202594.29" switch \initial - attribute \src "libresoc.v:199905.9-199905.17" + attribute \src "libresoc.v:202594.9-202594.17" case 1'1 case end @@ -414479,21 +387496,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\rst_l_r_rst$next[0:0]$14421 1'1 + assign $1\rst_l_r_rst$next[0:0]$14407 1'1 case - assign $1\rst_l_r_rst$next[0:0]$14421 \rst_r + assign $1\rst_l_r_rst$next[0:0]$14407 \rst_r end sync always - update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$14420 + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$14406 end - attribute \src "libresoc.v:199913.3-199921.6" - process $proc$libresoc.v:199913$14422 + attribute \src "libresoc.v:202602.3-202610.6" + process $proc$libresoc.v:202602$14408 assign { } { } assign { } { } - assign $0\opc_l_s_opc$next[0:0]$14423 $1\opc_l_s_opc$next[0:0]$14424 - attribute \src "libresoc.v:199914.5-199914.29" + assign $0\opc_l_s_opc$next[0:0]$14409 $1\opc_l_s_opc$next[0:0]$14410 + attribute \src "libresoc.v:202603.5-202603.29" switch \initial - attribute \src "libresoc.v:199914.9-199914.17" + attribute \src "libresoc.v:202603.9-202603.17" case 1'1 case end @@ -414502,21 +387519,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_s_opc$next[0:0]$14424 1'0 + assign $1\opc_l_s_opc$next[0:0]$14410 1'0 case - assign $1\opc_l_s_opc$next[0:0]$14424 \cu_issue_i + assign $1\opc_l_s_opc$next[0:0]$14410 \cu_issue_i end sync always - update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$14423 + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$14409 end - attribute \src "libresoc.v:199922.3-199930.6" - process $proc$libresoc.v:199922$14425 + attribute \src "libresoc.v:202611.3-202619.6" + process $proc$libresoc.v:202611$14411 assign { } { } assign { } { } - assign $0\opc_l_r_opc$next[0:0]$14426 $1\opc_l_r_opc$next[0:0]$14427 - attribute \src "libresoc.v:199923.5-199923.29" + assign $0\opc_l_r_opc$next[0:0]$14412 $1\opc_l_r_opc$next[0:0]$14413 + attribute \src "libresoc.v:202612.5-202612.29" switch \initial - attribute \src "libresoc.v:199923.9-199923.17" + attribute \src "libresoc.v:202612.9-202612.17" case 1'1 case end @@ -414525,21 +387542,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\opc_l_r_opc$next[0:0]$14427 1'1 + assign $1\opc_l_r_opc$next[0:0]$14413 1'1 case - assign $1\opc_l_r_opc$next[0:0]$14427 \req_done + assign $1\opc_l_r_opc$next[0:0]$14413 \req_done end sync always - update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$14426 + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$14412 end - attribute \src "libresoc.v:199931.3-199939.6" - process $proc$libresoc.v:199931$14428 + attribute \src "libresoc.v:202620.3-202628.6" + process $proc$libresoc.v:202620$14414 assign { } { } assign { } { } - assign $0\src_l_s_src$next[3:0]$14429 $1\src_l_s_src$next[3:0]$14430 - attribute \src "libresoc.v:199932.5-199932.29" + assign $0\src_l_s_src$next[3:0]$14415 $1\src_l_s_src$next[3:0]$14416 + attribute \src "libresoc.v:202621.5-202621.29" switch \initial - attribute \src "libresoc.v:199932.9-199932.17" + attribute \src "libresoc.v:202621.9-202621.17" case 1'1 case end @@ -414548,21 +387565,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_s_src$next[3:0]$14430 4'0000 + assign $1\src_l_s_src$next[3:0]$14416 4'0000 case - assign $1\src_l_s_src$next[3:0]$14430 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + assign $1\src_l_s_src$next[3:0]$14416 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } end sync always - update \src_l_s_src$next $0\src_l_s_src$next[3:0]$14429 + update \src_l_s_src$next $0\src_l_s_src$next[3:0]$14415 end - attribute \src "libresoc.v:199940.3-199948.6" - process $proc$libresoc.v:199940$14431 + attribute \src "libresoc.v:202629.3-202637.6" + process $proc$libresoc.v:202629$14417 assign { } { } assign { } { } - assign $0\src_l_r_src$next[3:0]$14432 $1\src_l_r_src$next[3:0]$14433 - attribute \src "libresoc.v:199941.5-199941.29" + assign $0\src_l_r_src$next[3:0]$14418 $1\src_l_r_src$next[3:0]$14419 + attribute \src "libresoc.v:202630.5-202630.29" switch \initial - attribute \src "libresoc.v:199941.9-199941.17" + attribute \src "libresoc.v:202630.9-202630.17" case 1'1 case end @@ -414571,21 +387588,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_l_r_src$next[3:0]$14433 4'1111 + assign $1\src_l_r_src$next[3:0]$14419 4'1111 case - assign $1\src_l_r_src$next[3:0]$14433 \reset_r + assign $1\src_l_r_src$next[3:0]$14419 \reset_r end sync always - update \src_l_r_src$next $0\src_l_r_src$next[3:0]$14432 + update \src_l_r_src$next $0\src_l_r_src$next[3:0]$14418 end - attribute \src "libresoc.v:199949.3-199957.6" - process $proc$libresoc.v:199949$14434 + attribute \src "libresoc.v:202638.3-202646.6" + process $proc$libresoc.v:202638$14420 assign { } { } assign { } { } - assign $0\req_l_s_req$next[4:0]$14435 $1\req_l_s_req$next[4:0]$14436 - attribute \src "libresoc.v:199950.5-199950.29" + assign $0\req_l_s_req$next[4:0]$14421 $1\req_l_s_req$next[4:0]$14422 + attribute \src "libresoc.v:202639.5-202639.29" switch \initial - attribute \src "libresoc.v:199950.9-199950.17" + attribute \src "libresoc.v:202639.9-202639.17" case 1'1 case end @@ -414594,21 +387611,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_s_req$next[4:0]$14436 5'00000 + assign $1\req_l_s_req$next[4:0]$14422 5'00000 case - assign $1\req_l_s_req$next[4:0]$14436 \$67 + assign $1\req_l_s_req$next[4:0]$14422 \$67 end sync always - update \req_l_s_req$next $0\req_l_s_req$next[4:0]$14435 + update \req_l_s_req$next $0\req_l_s_req$next[4:0]$14421 end - attribute \src "libresoc.v:199958.3-199966.6" - process $proc$libresoc.v:199958$14437 + attribute \src "libresoc.v:202647.3-202655.6" + process $proc$libresoc.v:202647$14423 assign { } { } assign { } { } - assign $0\req_l_r_req$next[4:0]$14438 $1\req_l_r_req$next[4:0]$14439 - attribute \src "libresoc.v:199959.5-199959.29" + assign $0\req_l_r_req$next[4:0]$14424 $1\req_l_r_req$next[4:0]$14425 + attribute \src "libresoc.v:202648.5-202648.29" switch \initial - attribute \src "libresoc.v:199959.9-199959.17" + attribute \src "libresoc.v:202648.9-202648.17" case 1'1 case end @@ -414617,15 +387634,15 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\req_l_r_req$next[4:0]$14439 5'11111 + assign $1\req_l_r_req$next[4:0]$14425 5'11111 case - assign $1\req_l_r_req$next[4:0]$14439 \$69 + assign $1\req_l_r_req$next[4:0]$14425 \$69 end sync always - update \req_l_r_req$next $0\req_l_r_req$next[4:0]$14438 + update \req_l_r_req$next $0\req_l_r_req$next[4:0]$14424 end - attribute \src "libresoc.v:199967.3-199984.6" - process $proc$libresoc.v:199967$14440 + attribute \src "libresoc.v:202656.3-202673.6" + process $proc$libresoc.v:202656$14426 assign { } { } assign { } { } assign { } { } @@ -414644,18 +387661,18 @@ module \trap0 assign { } { } assign { } { } assign { } { } - assign $0\alu_trap0_trap_op__cia$next[63:0]$14441 $1\alu_trap0_trap_op__cia$next[63:0]$14450 - assign $0\alu_trap0_trap_op__fn_unit$next[13:0]$14442 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14451 - assign $0\alu_trap0_trap_op__insn$next[31:0]$14443 $1\alu_trap0_trap_op__insn$next[31:0]$14452 - assign $0\alu_trap0_trap_op__insn_type$next[6:0]$14444 $1\alu_trap0_trap_op__insn_type$next[6:0]$14453 - assign $0\alu_trap0_trap_op__is_32bit$next[0:0]$14445 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14454 - assign $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14446 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14455 - assign $0\alu_trap0_trap_op__msr$next[63:0]$14447 $1\alu_trap0_trap_op__msr$next[63:0]$14456 - assign $0\alu_trap0_trap_op__trapaddr$next[12:0]$14448 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14457 - assign $0\alu_trap0_trap_op__traptype$next[7:0]$14449 $1\alu_trap0_trap_op__traptype$next[7:0]$14458 - attribute \src "libresoc.v:199968.5-199968.29" + assign $0\alu_trap0_trap_op__cia$next[63:0]$14427 $1\alu_trap0_trap_op__cia$next[63:0]$14436 + assign $0\alu_trap0_trap_op__fn_unit$next[13:0]$14428 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14437 + assign $0\alu_trap0_trap_op__insn$next[31:0]$14429 $1\alu_trap0_trap_op__insn$next[31:0]$14438 + assign $0\alu_trap0_trap_op__insn_type$next[6:0]$14430 $1\alu_trap0_trap_op__insn_type$next[6:0]$14439 + assign $0\alu_trap0_trap_op__is_32bit$next[0:0]$14431 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14440 + assign $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14432 $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14441 + assign $0\alu_trap0_trap_op__msr$next[63:0]$14433 $1\alu_trap0_trap_op__msr$next[63:0]$14442 + assign $0\alu_trap0_trap_op__trapaddr$next[12:0]$14434 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14443 + assign $0\alu_trap0_trap_op__traptype$next[7:0]$14435 $1\alu_trap0_trap_op__traptype$next[7:0]$14444 + attribute \src "libresoc.v:202657.5-202657.29" switch \initial - attribute \src "libresoc.v:199968.9-199968.17" + attribute \src "libresoc.v:202657.9-202657.17" case 1'1 case end @@ -414672,43 +387689,43 @@ module \trap0 assign { } { } assign { } { } assign { } { } - assign { $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14455 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14457 $1\alu_trap0_trap_op__traptype$next[7:0]$14458 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14454 $1\alu_trap0_trap_op__cia$next[63:0]$14450 $1\alu_trap0_trap_op__msr$next[63:0]$14456 $1\alu_trap0_trap_op__insn$next[31:0]$14452 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14451 $1\alu_trap0_trap_op__insn_type$next[6:0]$14453 } { \oper_i_alu_trap0__ldst_exc \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__traptype \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__cia \oper_i_alu_trap0__msr \oper_i_alu_trap0__insn \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__insn_type } + assign { $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14441 $1\alu_trap0_trap_op__trapaddr$next[12:0]$14443 $1\alu_trap0_trap_op__traptype$next[7:0]$14444 $1\alu_trap0_trap_op__is_32bit$next[0:0]$14440 $1\alu_trap0_trap_op__cia$next[63:0]$14436 $1\alu_trap0_trap_op__msr$next[63:0]$14442 $1\alu_trap0_trap_op__insn$next[31:0]$14438 $1\alu_trap0_trap_op__fn_unit$next[13:0]$14437 $1\alu_trap0_trap_op__insn_type$next[6:0]$14439 } { \oper_i_alu_trap0__ldst_exc \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__traptype \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__cia \oper_i_alu_trap0__msr \oper_i_alu_trap0__insn \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__insn_type } case - assign $1\alu_trap0_trap_op__cia$next[63:0]$14450 \alu_trap0_trap_op__cia - assign $1\alu_trap0_trap_op__fn_unit$next[13:0]$14451 \alu_trap0_trap_op__fn_unit - assign $1\alu_trap0_trap_op__insn$next[31:0]$14452 \alu_trap0_trap_op__insn - assign $1\alu_trap0_trap_op__insn_type$next[6:0]$14453 \alu_trap0_trap_op__insn_type - assign $1\alu_trap0_trap_op__is_32bit$next[0:0]$14454 \alu_trap0_trap_op__is_32bit - assign $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14455 \alu_trap0_trap_op__ldst_exc - assign $1\alu_trap0_trap_op__msr$next[63:0]$14456 \alu_trap0_trap_op__msr - assign $1\alu_trap0_trap_op__trapaddr$next[12:0]$14457 \alu_trap0_trap_op__trapaddr - assign $1\alu_trap0_trap_op__traptype$next[7:0]$14458 \alu_trap0_trap_op__traptype + assign $1\alu_trap0_trap_op__cia$next[63:0]$14436 \alu_trap0_trap_op__cia + assign $1\alu_trap0_trap_op__fn_unit$next[13:0]$14437 \alu_trap0_trap_op__fn_unit + assign $1\alu_trap0_trap_op__insn$next[31:0]$14438 \alu_trap0_trap_op__insn + assign $1\alu_trap0_trap_op__insn_type$next[6:0]$14439 \alu_trap0_trap_op__insn_type + assign $1\alu_trap0_trap_op__is_32bit$next[0:0]$14440 \alu_trap0_trap_op__is_32bit + assign $1\alu_trap0_trap_op__ldst_exc$next[7:0]$14441 \alu_trap0_trap_op__ldst_exc + assign $1\alu_trap0_trap_op__msr$next[63:0]$14442 \alu_trap0_trap_op__msr + assign $1\alu_trap0_trap_op__trapaddr$next[12:0]$14443 \alu_trap0_trap_op__trapaddr + assign $1\alu_trap0_trap_op__traptype$next[7:0]$14444 \alu_trap0_trap_op__traptype end sync always - update \alu_trap0_trap_op__cia$next $0\alu_trap0_trap_op__cia$next[63:0]$14441 - update \alu_trap0_trap_op__fn_unit$next $0\alu_trap0_trap_op__fn_unit$next[13:0]$14442 - update \alu_trap0_trap_op__insn$next $0\alu_trap0_trap_op__insn$next[31:0]$14443 - update \alu_trap0_trap_op__insn_type$next $0\alu_trap0_trap_op__insn_type$next[6:0]$14444 - update \alu_trap0_trap_op__is_32bit$next $0\alu_trap0_trap_op__is_32bit$next[0:0]$14445 - update \alu_trap0_trap_op__ldst_exc$next $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14446 - update \alu_trap0_trap_op__msr$next $0\alu_trap0_trap_op__msr$next[63:0]$14447 - update \alu_trap0_trap_op__trapaddr$next $0\alu_trap0_trap_op__trapaddr$next[12:0]$14448 - update \alu_trap0_trap_op__traptype$next $0\alu_trap0_trap_op__traptype$next[7:0]$14449 + update \alu_trap0_trap_op__cia$next $0\alu_trap0_trap_op__cia$next[63:0]$14427 + update \alu_trap0_trap_op__fn_unit$next $0\alu_trap0_trap_op__fn_unit$next[13:0]$14428 + update \alu_trap0_trap_op__insn$next $0\alu_trap0_trap_op__insn$next[31:0]$14429 + update \alu_trap0_trap_op__insn_type$next $0\alu_trap0_trap_op__insn_type$next[6:0]$14430 + update \alu_trap0_trap_op__is_32bit$next $0\alu_trap0_trap_op__is_32bit$next[0:0]$14431 + update \alu_trap0_trap_op__ldst_exc$next $0\alu_trap0_trap_op__ldst_exc$next[7:0]$14432 + update \alu_trap0_trap_op__msr$next $0\alu_trap0_trap_op__msr$next[63:0]$14433 + update \alu_trap0_trap_op__trapaddr$next $0\alu_trap0_trap_op__trapaddr$next[12:0]$14434 + update \alu_trap0_trap_op__traptype$next $0\alu_trap0_trap_op__traptype$next[7:0]$14435 end - attribute \src "libresoc.v:199985.3-200006.6" - process $proc$libresoc.v:199985$14459 + attribute \src "libresoc.v:202674.3-202695.6" + process $proc$libresoc.v:202674$14445 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r0__o$next[63:0]$14460 $2\data_r0__o$next[63:0]$14464 + assign $0\data_r0__o$next[63:0]$14446 $2\data_r0__o$next[63:0]$14450 assign { } { } - assign $0\data_r0__o_ok$next[0:0]$14461 $3\data_r0__o_ok$next[0:0]$14466 - attribute \src "libresoc.v:199986.5-199986.29" + assign $0\data_r0__o_ok$next[0:0]$14447 $3\data_r0__o_ok$next[0:0]$14452 + attribute \src "libresoc.v:202675.5-202675.29" switch \initial - attribute \src "libresoc.v:199986.9-199986.17" + attribute \src "libresoc.v:202675.9-202675.17" case 1'1 case end @@ -414718,10 +387735,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r0__o_ok$next[0:0]$14463 $1\data_r0__o$next[63:0]$14462 } { \o_ok \alu_trap0_o } + assign { $1\data_r0__o_ok$next[0:0]$14449 $1\data_r0__o$next[63:0]$14448 } { \o_ok \alu_trap0_o } case - assign $1\data_r0__o$next[63:0]$14462 \data_r0__o - assign $1\data_r0__o_ok$next[0:0]$14463 \data_r0__o_ok + assign $1\data_r0__o$next[63:0]$14448 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$14449 \data_r0__o_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -414729,38 +387746,38 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r0__o_ok$next[0:0]$14465 $2\data_r0__o$next[63:0]$14464 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r0__o_ok$next[0:0]$14451 $2\data_r0__o$next[63:0]$14450 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r0__o$next[63:0]$14464 $1\data_r0__o$next[63:0]$14462 - assign $2\data_r0__o_ok$next[0:0]$14465 $1\data_r0__o_ok$next[0:0]$14463 + assign $2\data_r0__o$next[63:0]$14450 $1\data_r0__o$next[63:0]$14448 + assign $2\data_r0__o_ok$next[0:0]$14451 $1\data_r0__o_ok$next[0:0]$14449 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r0__o_ok$next[0:0]$14466 1'0 + assign $3\data_r0__o_ok$next[0:0]$14452 1'0 case - assign $3\data_r0__o_ok$next[0:0]$14466 $2\data_r0__o_ok$next[0:0]$14465 + assign $3\data_r0__o_ok$next[0:0]$14452 $2\data_r0__o_ok$next[0:0]$14451 end sync always - update \data_r0__o$next $0\data_r0__o$next[63:0]$14460 - update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$14461 + update \data_r0__o$next $0\data_r0__o$next[63:0]$14446 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$14447 end - attribute \src "libresoc.v:200007.3-200028.6" - process $proc$libresoc.v:200007$14467 + attribute \src "libresoc.v:202696.3-202717.6" + process $proc$libresoc.v:202696$14453 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r1__fast1$next[63:0]$14468 $2\data_r1__fast1$next[63:0]$14472 + assign $0\data_r1__fast1$next[63:0]$14454 $2\data_r1__fast1$next[63:0]$14458 assign { } { } - assign $0\data_r1__fast1_ok$next[0:0]$14469 $3\data_r1__fast1_ok$next[0:0]$14474 - attribute \src "libresoc.v:200008.5-200008.29" + assign $0\data_r1__fast1_ok$next[0:0]$14455 $3\data_r1__fast1_ok$next[0:0]$14460 + attribute \src "libresoc.v:202697.5-202697.29" switch \initial - attribute \src "libresoc.v:200008.9-200008.17" + attribute \src "libresoc.v:202697.9-202697.17" case 1'1 case end @@ -414770,10 +387787,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r1__fast1_ok$next[0:0]$14471 $1\data_r1__fast1$next[63:0]$14470 } { \fast1_ok \alu_trap0_fast1 } + assign { $1\data_r1__fast1_ok$next[0:0]$14457 $1\data_r1__fast1$next[63:0]$14456 } { \fast1_ok \alu_trap0_fast1 } case - assign $1\data_r1__fast1$next[63:0]$14470 \data_r1__fast1 - assign $1\data_r1__fast1_ok$next[0:0]$14471 \data_r1__fast1_ok + assign $1\data_r1__fast1$next[63:0]$14456 \data_r1__fast1 + assign $1\data_r1__fast1_ok$next[0:0]$14457 \data_r1__fast1_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -414781,38 +387798,38 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r1__fast1_ok$next[0:0]$14473 $2\data_r1__fast1$next[63:0]$14472 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r1__fast1_ok$next[0:0]$14459 $2\data_r1__fast1$next[63:0]$14458 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r1__fast1$next[63:0]$14472 $1\data_r1__fast1$next[63:0]$14470 - assign $2\data_r1__fast1_ok$next[0:0]$14473 $1\data_r1__fast1_ok$next[0:0]$14471 + assign $2\data_r1__fast1$next[63:0]$14458 $1\data_r1__fast1$next[63:0]$14456 + assign $2\data_r1__fast1_ok$next[0:0]$14459 $1\data_r1__fast1_ok$next[0:0]$14457 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r1__fast1_ok$next[0:0]$14474 1'0 + assign $3\data_r1__fast1_ok$next[0:0]$14460 1'0 case - assign $3\data_r1__fast1_ok$next[0:0]$14474 $2\data_r1__fast1_ok$next[0:0]$14473 + assign $3\data_r1__fast1_ok$next[0:0]$14460 $2\data_r1__fast1_ok$next[0:0]$14459 end sync always - update \data_r1__fast1$next $0\data_r1__fast1$next[63:0]$14468 - update \data_r1__fast1_ok$next $0\data_r1__fast1_ok$next[0:0]$14469 + update \data_r1__fast1$next $0\data_r1__fast1$next[63:0]$14454 + update \data_r1__fast1_ok$next $0\data_r1__fast1_ok$next[0:0]$14455 end - attribute \src "libresoc.v:200029.3-200050.6" - process $proc$libresoc.v:200029$14475 + attribute \src "libresoc.v:202718.3-202739.6" + process $proc$libresoc.v:202718$14461 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r2__fast2$next[63:0]$14476 $2\data_r2__fast2$next[63:0]$14480 + assign $0\data_r2__fast2$next[63:0]$14462 $2\data_r2__fast2$next[63:0]$14466 assign { } { } - assign $0\data_r2__fast2_ok$next[0:0]$14477 $3\data_r2__fast2_ok$next[0:0]$14482 - attribute \src "libresoc.v:200030.5-200030.29" + assign $0\data_r2__fast2_ok$next[0:0]$14463 $3\data_r2__fast2_ok$next[0:0]$14468 + attribute \src "libresoc.v:202719.5-202719.29" switch \initial - attribute \src "libresoc.v:200030.9-200030.17" + attribute \src "libresoc.v:202719.9-202719.17" case 1'1 case end @@ -414822,10 +387839,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r2__fast2_ok$next[0:0]$14479 $1\data_r2__fast2$next[63:0]$14478 } { \fast2_ok \alu_trap0_fast2 } + assign { $1\data_r2__fast2_ok$next[0:0]$14465 $1\data_r2__fast2$next[63:0]$14464 } { \fast2_ok \alu_trap0_fast2 } case - assign $1\data_r2__fast2$next[63:0]$14478 \data_r2__fast2 - assign $1\data_r2__fast2_ok$next[0:0]$14479 \data_r2__fast2_ok + assign $1\data_r2__fast2$next[63:0]$14464 \data_r2__fast2 + assign $1\data_r2__fast2_ok$next[0:0]$14465 \data_r2__fast2_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -414833,38 +387850,38 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r2__fast2_ok$next[0:0]$14481 $2\data_r2__fast2$next[63:0]$14480 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r2__fast2_ok$next[0:0]$14467 $2\data_r2__fast2$next[63:0]$14466 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r2__fast2$next[63:0]$14480 $1\data_r2__fast2$next[63:0]$14478 - assign $2\data_r2__fast2_ok$next[0:0]$14481 $1\data_r2__fast2_ok$next[0:0]$14479 + assign $2\data_r2__fast2$next[63:0]$14466 $1\data_r2__fast2$next[63:0]$14464 + assign $2\data_r2__fast2_ok$next[0:0]$14467 $1\data_r2__fast2_ok$next[0:0]$14465 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r2__fast2_ok$next[0:0]$14482 1'0 + assign $3\data_r2__fast2_ok$next[0:0]$14468 1'0 case - assign $3\data_r2__fast2_ok$next[0:0]$14482 $2\data_r2__fast2_ok$next[0:0]$14481 + assign $3\data_r2__fast2_ok$next[0:0]$14468 $2\data_r2__fast2_ok$next[0:0]$14467 end sync always - update \data_r2__fast2$next $0\data_r2__fast2$next[63:0]$14476 - update \data_r2__fast2_ok$next $0\data_r2__fast2_ok$next[0:0]$14477 + update \data_r2__fast2$next $0\data_r2__fast2$next[63:0]$14462 + update \data_r2__fast2_ok$next $0\data_r2__fast2_ok$next[0:0]$14463 end - attribute \src "libresoc.v:200051.3-200072.6" - process $proc$libresoc.v:200051$14483 + attribute \src "libresoc.v:202740.3-202761.6" + process $proc$libresoc.v:202740$14469 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r3__nia$next[63:0]$14484 $2\data_r3__nia$next[63:0]$14488 + assign $0\data_r3__nia$next[63:0]$14470 $2\data_r3__nia$next[63:0]$14474 assign { } { } - assign $0\data_r3__nia_ok$next[0:0]$14485 $3\data_r3__nia_ok$next[0:0]$14490 - attribute \src "libresoc.v:200052.5-200052.29" + assign $0\data_r3__nia_ok$next[0:0]$14471 $3\data_r3__nia_ok$next[0:0]$14476 + attribute \src "libresoc.v:202741.5-202741.29" switch \initial - attribute \src "libresoc.v:200052.9-200052.17" + attribute \src "libresoc.v:202741.9-202741.17" case 1'1 case end @@ -414874,10 +387891,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r3__nia_ok$next[0:0]$14487 $1\data_r3__nia$next[63:0]$14486 } { \nia_ok \alu_trap0_nia } + assign { $1\data_r3__nia_ok$next[0:0]$14473 $1\data_r3__nia$next[63:0]$14472 } { \nia_ok \alu_trap0_nia } case - assign $1\data_r3__nia$next[63:0]$14486 \data_r3__nia - assign $1\data_r3__nia_ok$next[0:0]$14487 \data_r3__nia_ok + assign $1\data_r3__nia$next[63:0]$14472 \data_r3__nia + assign $1\data_r3__nia_ok$next[0:0]$14473 \data_r3__nia_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -414885,38 +387902,38 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r3__nia_ok$next[0:0]$14489 $2\data_r3__nia$next[63:0]$14488 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r3__nia_ok$next[0:0]$14475 $2\data_r3__nia$next[63:0]$14474 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r3__nia$next[63:0]$14488 $1\data_r3__nia$next[63:0]$14486 - assign $2\data_r3__nia_ok$next[0:0]$14489 $1\data_r3__nia_ok$next[0:0]$14487 + assign $2\data_r3__nia$next[63:0]$14474 $1\data_r3__nia$next[63:0]$14472 + assign $2\data_r3__nia_ok$next[0:0]$14475 $1\data_r3__nia_ok$next[0:0]$14473 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r3__nia_ok$next[0:0]$14490 1'0 + assign $3\data_r3__nia_ok$next[0:0]$14476 1'0 case - assign $3\data_r3__nia_ok$next[0:0]$14490 $2\data_r3__nia_ok$next[0:0]$14489 + assign $3\data_r3__nia_ok$next[0:0]$14476 $2\data_r3__nia_ok$next[0:0]$14475 end sync always - update \data_r3__nia$next $0\data_r3__nia$next[63:0]$14484 - update \data_r3__nia_ok$next $0\data_r3__nia_ok$next[0:0]$14485 + update \data_r3__nia$next $0\data_r3__nia$next[63:0]$14470 + update \data_r3__nia_ok$next $0\data_r3__nia_ok$next[0:0]$14471 end - attribute \src "libresoc.v:200073.3-200094.6" - process $proc$libresoc.v:200073$14491 + attribute \src "libresoc.v:202762.3-202783.6" + process $proc$libresoc.v:202762$14477 assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } assign { } { } - assign $0\data_r4__msr$next[63:0]$14492 $2\data_r4__msr$next[63:0]$14496 + assign $0\data_r4__msr$next[63:0]$14478 $2\data_r4__msr$next[63:0]$14482 assign { } { } - assign $0\data_r4__msr_ok$next[0:0]$14493 $3\data_r4__msr_ok$next[0:0]$14498 - attribute \src "libresoc.v:200074.5-200074.29" + assign $0\data_r4__msr_ok$next[0:0]$14479 $3\data_r4__msr_ok$next[0:0]$14484 + attribute \src "libresoc.v:202763.5-202763.29" switch \initial - attribute \src "libresoc.v:200074.9-200074.17" + attribute \src "libresoc.v:202763.9-202763.17" case 1'1 case end @@ -414926,10 +387943,10 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $1\data_r4__msr_ok$next[0:0]$14495 $1\data_r4__msr$next[63:0]$14494 } { \msr_ok \alu_trap0_msr } + assign { $1\data_r4__msr_ok$next[0:0]$14481 $1\data_r4__msr$next[63:0]$14480 } { \msr_ok \alu_trap0_msr } case - assign $1\data_r4__msr$next[63:0]$14494 \data_r4__msr - assign $1\data_r4__msr_ok$next[0:0]$14495 \data_r4__msr_ok + assign $1\data_r4__msr$next[63:0]$14480 \data_r4__msr + assign $1\data_r4__msr_ok$next[0:0]$14481 \data_r4__msr_ok end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" switch \cu_issue_i @@ -414937,32 +387954,32 @@ module \trap0 case 1'1 assign { } { } assign { } { } - assign { $2\data_r4__msr_ok$next[0:0]$14497 $2\data_r4__msr$next[63:0]$14496 } 65'00000000000000000000000000000000000000000000000000000000000000000 + assign { $2\data_r4__msr_ok$next[0:0]$14483 $2\data_r4__msr$next[63:0]$14482 } 65'00000000000000000000000000000000000000000000000000000000000000000 case - assign $2\data_r4__msr$next[63:0]$14496 $1\data_r4__msr$next[63:0]$14494 - assign $2\data_r4__msr_ok$next[0:0]$14497 $1\data_r4__msr_ok$next[0:0]$14495 + assign $2\data_r4__msr$next[63:0]$14482 $1\data_r4__msr$next[63:0]$14480 + assign $2\data_r4__msr_ok$next[0:0]$14483 $1\data_r4__msr_ok$next[0:0]$14481 end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \coresync_rst attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $3\data_r4__msr_ok$next[0:0]$14498 1'0 + assign $3\data_r4__msr_ok$next[0:0]$14484 1'0 case - assign $3\data_r4__msr_ok$next[0:0]$14498 $2\data_r4__msr_ok$next[0:0]$14497 + assign $3\data_r4__msr_ok$next[0:0]$14484 $2\data_r4__msr_ok$next[0:0]$14483 end sync always - update \data_r4__msr$next $0\data_r4__msr$next[63:0]$14492 - update \data_r4__msr_ok$next $0\data_r4__msr_ok$next[0:0]$14493 + update \data_r4__msr$next $0\data_r4__msr$next[63:0]$14478 + update \data_r4__msr_ok$next $0\data_r4__msr_ok$next[0:0]$14479 end - attribute \src "libresoc.v:200095.3-200104.6" - process $proc$libresoc.v:200095$14499 + attribute \src "libresoc.v:202784.3-202793.6" + process $proc$libresoc.v:202784$14485 assign { } { } assign { } { } - assign $0\src_r0$next[63:0]$14500 $1\src_r0$next[63:0]$14501 - attribute \src "libresoc.v:200096.5-200096.29" + assign $0\src_r0$next[63:0]$14486 $1\src_r0$next[63:0]$14487 + attribute \src "libresoc.v:202785.5-202785.29" switch \initial - attribute \src "libresoc.v:200096.9-200096.17" + attribute \src "libresoc.v:202785.9-202785.17" case 1'1 case end @@ -414971,21 +387988,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r0$next[63:0]$14501 \src1_i + assign $1\src_r0$next[63:0]$14487 \src1_i case - assign $1\src_r0$next[63:0]$14501 \src_r0 + assign $1\src_r0$next[63:0]$14487 \src_r0 end sync always - update \src_r0$next $0\src_r0$next[63:0]$14500 + update \src_r0$next $0\src_r0$next[63:0]$14486 end - attribute \src "libresoc.v:200105.3-200114.6" - process $proc$libresoc.v:200105$14502 + attribute \src "libresoc.v:202794.3-202803.6" + process $proc$libresoc.v:202794$14488 assign { } { } assign { } { } - assign $0\src_r1$next[63:0]$14503 $1\src_r1$next[63:0]$14504 - attribute \src "libresoc.v:200106.5-200106.29" + assign $0\src_r1$next[63:0]$14489 $1\src_r1$next[63:0]$14490 + attribute \src "libresoc.v:202795.5-202795.29" switch \initial - attribute \src "libresoc.v:200106.9-200106.17" + attribute \src "libresoc.v:202795.9-202795.17" case 1'1 case end @@ -414994,21 +388011,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r1$next[63:0]$14504 \src2_i + assign $1\src_r1$next[63:0]$14490 \src2_i case - assign $1\src_r1$next[63:0]$14504 \src_r1 + assign $1\src_r1$next[63:0]$14490 \src_r1 end sync always - update \src_r1$next $0\src_r1$next[63:0]$14503 + update \src_r1$next $0\src_r1$next[63:0]$14489 end - attribute \src "libresoc.v:200115.3-200124.6" - process $proc$libresoc.v:200115$14505 + attribute \src "libresoc.v:202804.3-202813.6" + process $proc$libresoc.v:202804$14491 assign { } { } assign { } { } - assign $0\src_r2$next[63:0]$14506 $1\src_r2$next[63:0]$14507 - attribute \src "libresoc.v:200116.5-200116.29" + assign $0\src_r2$next[63:0]$14492 $1\src_r2$next[63:0]$14493 + attribute \src "libresoc.v:202805.5-202805.29" switch \initial - attribute \src "libresoc.v:200116.9-200116.17" + attribute \src "libresoc.v:202805.9-202805.17" case 1'1 case end @@ -415017,21 +388034,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r2$next[63:0]$14507 \src3_i + assign $1\src_r2$next[63:0]$14493 \src3_i case - assign $1\src_r2$next[63:0]$14507 \src_r2 + assign $1\src_r2$next[63:0]$14493 \src_r2 end sync always - update \src_r2$next $0\src_r2$next[63:0]$14506 + update \src_r2$next $0\src_r2$next[63:0]$14492 end - attribute \src "libresoc.v:200125.3-200134.6" - process $proc$libresoc.v:200125$14508 + attribute \src "libresoc.v:202814.3-202823.6" + process $proc$libresoc.v:202814$14494 assign { } { } assign { } { } - assign $0\src_r3$next[63:0]$14509 $1\src_r3$next[63:0]$14510 - attribute \src "libresoc.v:200126.5-200126.29" + assign $0\src_r3$next[63:0]$14495 $1\src_r3$next[63:0]$14496 + attribute \src "libresoc.v:202815.5-202815.29" switch \initial - attribute \src "libresoc.v:200126.9-200126.17" + attribute \src "libresoc.v:202815.9-202815.17" case 1'1 case end @@ -415040,21 +388057,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\src_r3$next[63:0]$14510 \src4_i + assign $1\src_r3$next[63:0]$14496 \src4_i case - assign $1\src_r3$next[63:0]$14510 \src_r3 + assign $1\src_r3$next[63:0]$14496 \src_r3 end sync always - update \src_r3$next $0\src_r3$next[63:0]$14509 + update \src_r3$next $0\src_r3$next[63:0]$14495 end - attribute \src "libresoc.v:200135.3-200143.6" - process $proc$libresoc.v:200135$14511 + attribute \src "libresoc.v:202824.3-202832.6" + process $proc$libresoc.v:202824$14497 assign { } { } assign { } { } - assign $0\alui_l_r_alui$next[0:0]$14512 $1\alui_l_r_alui$next[0:0]$14513 - attribute \src "libresoc.v:200136.5-200136.29" + assign $0\alui_l_r_alui$next[0:0]$14498 $1\alui_l_r_alui$next[0:0]$14499 + attribute \src "libresoc.v:202825.5-202825.29" switch \initial - attribute \src "libresoc.v:200136.9-200136.17" + attribute \src "libresoc.v:202825.9-202825.17" case 1'1 case end @@ -415063,21 +388080,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alui_l_r_alui$next[0:0]$14513 1'1 + assign $1\alui_l_r_alui$next[0:0]$14499 1'1 case - assign $1\alui_l_r_alui$next[0:0]$14513 \$89 + assign $1\alui_l_r_alui$next[0:0]$14499 \$89 end sync always - update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$14512 + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$14498 end - attribute \src "libresoc.v:200144.3-200152.6" - process $proc$libresoc.v:200144$14514 + attribute \src "libresoc.v:202833.3-202841.6" + process $proc$libresoc.v:202833$14500 assign { } { } assign { } { } - assign $0\alu_l_r_alu$next[0:0]$14515 $1\alu_l_r_alu$next[0:0]$14516 - attribute \src "libresoc.v:200145.5-200145.29" + assign $0\alu_l_r_alu$next[0:0]$14501 $1\alu_l_r_alu$next[0:0]$14502 + attribute \src "libresoc.v:202834.5-202834.29" switch \initial - attribute \src "libresoc.v:200145.9-200145.17" + attribute \src "libresoc.v:202834.9-202834.17" case 1'1 case end @@ -415086,21 +388103,21 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\alu_l_r_alu$next[0:0]$14516 1'1 + assign $1\alu_l_r_alu$next[0:0]$14502 1'1 case - assign $1\alu_l_r_alu$next[0:0]$14516 \$91 + assign $1\alu_l_r_alu$next[0:0]$14502 \$91 end sync always - update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$14515 + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$14501 end - attribute \src "libresoc.v:200153.3-200162.6" - process $proc$libresoc.v:200153$14517 + attribute \src "libresoc.v:202842.3-202851.6" + process $proc$libresoc.v:202842$14503 assign { } { } assign { } { } assign $0\dest1_o[63:0] $1\dest1_o[63:0] - attribute \src "libresoc.v:200154.5-200154.29" + attribute \src "libresoc.v:202843.5-202843.29" switch \initial - attribute \src "libresoc.v:200154.9-200154.17" + attribute \src "libresoc.v:202843.9-202843.17" case 1'1 case end @@ -415116,14 +388133,14 @@ module \trap0 sync always update \dest1_o $0\dest1_o[63:0] end - attribute \src "libresoc.v:200163.3-200172.6" - process $proc$libresoc.v:200163$14518 + attribute \src "libresoc.v:202852.3-202861.6" + process $proc$libresoc.v:202852$14504 assign { } { } assign { } { } assign $0\dest2_o[63:0] $1\dest2_o[63:0] - attribute \src "libresoc.v:200164.5-200164.29" + attribute \src "libresoc.v:202853.5-202853.29" switch \initial - attribute \src "libresoc.v:200164.9-200164.17" + attribute \src "libresoc.v:202853.9-202853.17" case 1'1 case end @@ -415139,14 +388156,14 @@ module \trap0 sync always update \dest2_o $0\dest2_o[63:0] end - attribute \src "libresoc.v:200173.3-200182.6" - process $proc$libresoc.v:200173$14519 + attribute \src "libresoc.v:202862.3-202871.6" + process $proc$libresoc.v:202862$14505 assign { } { } assign { } { } assign $0\dest3_o[63:0] $1\dest3_o[63:0] - attribute \src "libresoc.v:200174.5-200174.29" + attribute \src "libresoc.v:202863.5-202863.29" switch \initial - attribute \src "libresoc.v:200174.9-200174.17" + attribute \src "libresoc.v:202863.9-202863.17" case 1'1 case end @@ -415162,14 +388179,14 @@ module \trap0 sync always update \dest3_o $0\dest3_o[63:0] end - attribute \src "libresoc.v:200183.3-200192.6" - process $proc$libresoc.v:200183$14520 + attribute \src "libresoc.v:202872.3-202881.6" + process $proc$libresoc.v:202872$14506 assign { } { } assign { } { } assign $0\dest4_o[63:0] $1\dest4_o[63:0] - attribute \src "libresoc.v:200184.5-200184.29" + attribute \src "libresoc.v:202873.5-202873.29" switch \initial - attribute \src "libresoc.v:200184.9-200184.17" + attribute \src "libresoc.v:202873.9-202873.17" case 1'1 case end @@ -415185,14 +388202,14 @@ module \trap0 sync always update \dest4_o $0\dest4_o[63:0] end - attribute \src "libresoc.v:200193.3-200202.6" - process $proc$libresoc.v:200193$14521 + attribute \src "libresoc.v:202882.3-202891.6" + process $proc$libresoc.v:202882$14507 assign { } { } assign { } { } assign $0\dest5_o[63:0] $1\dest5_o[63:0] - attribute \src "libresoc.v:200194.5-200194.29" + attribute \src "libresoc.v:202883.5-202883.29" switch \initial - attribute \src "libresoc.v:200194.9-200194.17" + attribute \src "libresoc.v:202883.9-202883.17" case 1'1 case end @@ -415208,14 +388225,14 @@ module \trap0 sync always update \dest5_o $0\dest5_o[63:0] end - attribute \src "libresoc.v:200203.3-200211.6" - process $proc$libresoc.v:200203$14522 + attribute \src "libresoc.v:202892.3-202900.6" + process $proc$libresoc.v:202892$14508 assign { } { } assign { } { } - assign $0\prev_wr_go$next[4:0]$14523 $1\prev_wr_go$next[4:0]$14524 - attribute \src "libresoc.v:200204.5-200204.29" + assign $0\prev_wr_go$next[4:0]$14509 $1\prev_wr_go$next[4:0]$14510 + attribute \src "libresoc.v:202893.5-202893.29" switch \initial - attribute \src "libresoc.v:200204.9-200204.17" + attribute \src "libresoc.v:202893.9-202893.17" case 1'1 case end @@ -415224,74 +388241,74 @@ module \trap0 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\prev_wr_go$next[4:0]$14524 5'00000 - case - assign $1\prev_wr_go$next[4:0]$14524 \$21 - end - sync always - update \prev_wr_go$next $0\prev_wr_go$next[4:0]$14523 - end - connect \$5 $reduce_and$libresoc.v:199651$14310_Y - connect \$99 $and$libresoc.v:199652$14311_Y - connect \$101 $and$libresoc.v:199653$14312_Y - connect \$103 $and$libresoc.v:199654$14313_Y - connect \$105 $and$libresoc.v:199655$14314_Y - connect \$107 $and$libresoc.v:199656$14315_Y - connect \$109 $and$libresoc.v:199657$14316_Y - connect \$111 $and$libresoc.v:199658$14317_Y - connect \$113 $and$libresoc.v:199659$14318_Y - connect \$115 $and$libresoc.v:199660$14319_Y - connect \$117 $and$libresoc.v:199661$14320_Y - connect \$11 $and$libresoc.v:199662$14321_Y - connect \$119 $and$libresoc.v:199663$14322_Y - connect \$121 $and$libresoc.v:199664$14323_Y - connect \$123 $and$libresoc.v:199665$14324_Y - connect \$13 $not$libresoc.v:199666$14325_Y - connect \$15 $and$libresoc.v:199667$14326_Y - connect \$17 $not$libresoc.v:199668$14327_Y - connect \$19 $and$libresoc.v:199669$14328_Y - connect \$21 $and$libresoc.v:199670$14329_Y - connect \$25 $not$libresoc.v:199671$14330_Y - connect \$27 $and$libresoc.v:199672$14331_Y - connect \$24 $reduce_or$libresoc.v:199673$14332_Y - connect \$23 $not$libresoc.v:199674$14333_Y - connect \$31 $and$libresoc.v:199675$14334_Y - connect \$33 $reduce_or$libresoc.v:199676$14335_Y - connect \$35 $reduce_or$libresoc.v:199677$14336_Y - connect \$37 $or$libresoc.v:199678$14337_Y - connect \$3 $and$libresoc.v:199679$14338_Y - connect \$39 $not$libresoc.v:199680$14339_Y - connect \$41 $and$libresoc.v:199681$14340_Y - connect \$43 $and$libresoc.v:199682$14341_Y - connect \$45 $eq$libresoc.v:199683$14342_Y - connect \$47 $and$libresoc.v:199684$14343_Y - connect \$49 $eq$libresoc.v:199685$14344_Y - connect \$51 $and$libresoc.v:199686$14345_Y - connect \$53 $and$libresoc.v:199687$14346_Y - connect \$55 $and$libresoc.v:199688$14347_Y - connect \$57 $or$libresoc.v:199689$14348_Y - connect \$59 $or$libresoc.v:199690$14349_Y - connect \$61 $or$libresoc.v:199691$14350_Y - connect \$63 $or$libresoc.v:199692$14351_Y - connect \$65 $and$libresoc.v:199693$14352_Y - connect \$67 $and$libresoc.v:199694$14353_Y - connect \$6 $not$libresoc.v:199695$14354_Y - connect \$69 $or$libresoc.v:199696$14355_Y - connect \$71 $and$libresoc.v:199697$14356_Y - connect \$73 $and$libresoc.v:199698$14357_Y - connect \$75 $and$libresoc.v:199699$14358_Y - connect \$77 $and$libresoc.v:199700$14359_Y - connect \$79 $and$libresoc.v:199701$14360_Y - connect \$81 $ternary$libresoc.v:199702$14361_Y - connect \$83 $ternary$libresoc.v:199703$14362_Y - connect \$85 $ternary$libresoc.v:199704$14363_Y - connect \$87 $ternary$libresoc.v:199705$14364_Y - connect \$8 $or$libresoc.v:199706$14365_Y - connect \$89 $and$libresoc.v:199707$14366_Y - connect \$91 $and$libresoc.v:199708$14367_Y - connect \$93 $and$libresoc.v:199709$14368_Y - connect \$95 $and$libresoc.v:199710$14369_Y - connect \$97 $not$libresoc.v:199711$14370_Y + assign $1\prev_wr_go$next[4:0]$14510 5'00000 + case + assign $1\prev_wr_go$next[4:0]$14510 \$21 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[4:0]$14509 + end + connect \$5 $reduce_and$libresoc.v:202340$14296_Y + connect \$99 $and$libresoc.v:202341$14297_Y + connect \$101 $and$libresoc.v:202342$14298_Y + connect \$103 $and$libresoc.v:202343$14299_Y + connect \$105 $and$libresoc.v:202344$14300_Y + connect \$107 $and$libresoc.v:202345$14301_Y + connect \$109 $and$libresoc.v:202346$14302_Y + connect \$111 $and$libresoc.v:202347$14303_Y + connect \$113 $and$libresoc.v:202348$14304_Y + connect \$115 $and$libresoc.v:202349$14305_Y + connect \$117 $and$libresoc.v:202350$14306_Y + connect \$11 $and$libresoc.v:202351$14307_Y + connect \$119 $and$libresoc.v:202352$14308_Y + connect \$121 $and$libresoc.v:202353$14309_Y + connect \$123 $and$libresoc.v:202354$14310_Y + connect \$13 $not$libresoc.v:202355$14311_Y + connect \$15 $and$libresoc.v:202356$14312_Y + connect \$17 $not$libresoc.v:202357$14313_Y + connect \$19 $and$libresoc.v:202358$14314_Y + connect \$21 $and$libresoc.v:202359$14315_Y + connect \$25 $not$libresoc.v:202360$14316_Y + connect \$27 $and$libresoc.v:202361$14317_Y + connect \$24 $reduce_or$libresoc.v:202362$14318_Y + connect \$23 $not$libresoc.v:202363$14319_Y + connect \$31 $and$libresoc.v:202364$14320_Y + connect \$33 $reduce_or$libresoc.v:202365$14321_Y + connect \$35 $reduce_or$libresoc.v:202366$14322_Y + connect \$37 $or$libresoc.v:202367$14323_Y + connect \$3 $and$libresoc.v:202368$14324_Y + connect \$39 $not$libresoc.v:202369$14325_Y + connect \$41 $and$libresoc.v:202370$14326_Y + connect \$43 $and$libresoc.v:202371$14327_Y + connect \$45 $eq$libresoc.v:202372$14328_Y + connect \$47 $and$libresoc.v:202373$14329_Y + connect \$49 $eq$libresoc.v:202374$14330_Y + connect \$51 $and$libresoc.v:202375$14331_Y + connect \$53 $and$libresoc.v:202376$14332_Y + connect \$55 $and$libresoc.v:202377$14333_Y + connect \$57 $or$libresoc.v:202378$14334_Y + connect \$59 $or$libresoc.v:202379$14335_Y + connect \$61 $or$libresoc.v:202380$14336_Y + connect \$63 $or$libresoc.v:202381$14337_Y + connect \$65 $and$libresoc.v:202382$14338_Y + connect \$67 $and$libresoc.v:202383$14339_Y + connect \$6 $not$libresoc.v:202384$14340_Y + connect \$69 $or$libresoc.v:202385$14341_Y + connect \$71 $and$libresoc.v:202386$14342_Y + connect \$73 $and$libresoc.v:202387$14343_Y + connect \$75 $and$libresoc.v:202388$14344_Y + connect \$77 $and$libresoc.v:202389$14345_Y + connect \$79 $and$libresoc.v:202390$14346_Y + connect \$81 $ternary$libresoc.v:202391$14347_Y + connect \$83 $ternary$libresoc.v:202392$14348_Y + connect \$85 $ternary$libresoc.v:202393$14349_Y + connect \$87 $ternary$libresoc.v:202394$14350_Y + connect \$8 $or$libresoc.v:202395$14351_Y + connect \$89 $and$libresoc.v:202396$14352_Y + connect \$91 $and$libresoc.v:202397$14353_Y + connect \$93 $and$libresoc.v:202398$14354_Y + connect \$95 $and$libresoc.v:202399$14355_Y + connect \$97 $not$libresoc.v:202400$14356_Y connect \cu_go_die_i 1'0 connect \cu_shadown_i 1'1 connect \cu_wr__rel_o \$113 @@ -415322,37 +388339,37 @@ module \trap0 connect \all_rd_dly$next \all_rd connect \all_rd \$11 end -attribute \src "libresoc.v:200245.1-200303.10" +attribute \src "libresoc.v:202934.1-202992.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.upd_l" attribute \generator "nMigen" module \upd_l - attribute \src "libresoc.v:200246.7-200246.20" + attribute \src "libresoc.v:202935.7-202935.20" wire $0\initial[0:0] - attribute \src "libresoc.v:200291.3-200299.6" - wire $0\q_int$next[0:0]$14574 - attribute \src "libresoc.v:200289.3-200290.27" + attribute \src "libresoc.v:202980.3-202988.6" + wire $0\q_int$next[0:0]$14560 + attribute \src "libresoc.v:202978.3-202979.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:200291.3-200299.6" - wire $1\q_int$next[0:0]$14575 - attribute \src "libresoc.v:200268.7-200268.19" + attribute \src "libresoc.v:202980.3-202988.6" + wire $1\q_int$next[0:0]$14561 + attribute \src "libresoc.v:202957.7-202957.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:200281.17-200281.96" - wire $and$libresoc.v:200281$14564_Y - attribute \src "libresoc.v:200286.17-200286.96" - wire $and$libresoc.v:200286$14569_Y - attribute \src "libresoc.v:200283.18-200283.93" - wire $not$libresoc.v:200283$14566_Y - attribute \src "libresoc.v:200285.17-200285.92" - wire $not$libresoc.v:200285$14568_Y - attribute \src "libresoc.v:200288.17-200288.92" - wire $not$libresoc.v:200288$14571_Y - attribute \src "libresoc.v:200282.18-200282.98" - wire $or$libresoc.v:200282$14565_Y - attribute \src "libresoc.v:200284.18-200284.99" - wire $or$libresoc.v:200284$14567_Y - attribute \src "libresoc.v:200287.17-200287.97" - wire $or$libresoc.v:200287$14570_Y + attribute \src "libresoc.v:202970.17-202970.96" + wire $and$libresoc.v:202970$14550_Y + attribute \src "libresoc.v:202975.17-202975.96" + wire $and$libresoc.v:202975$14555_Y + attribute \src "libresoc.v:202972.18-202972.93" + wire $not$libresoc.v:202972$14552_Y + attribute \src "libresoc.v:202974.17-202974.92" + wire $not$libresoc.v:202974$14554_Y + attribute \src "libresoc.v:202977.17-202977.92" + wire $not$libresoc.v:202977$14557_Y + attribute \src "libresoc.v:202971.18-202971.98" + wire $or$libresoc.v:202971$14551_Y + attribute \src "libresoc.v:202973.18-202973.99" + wire $or$libresoc.v:202973$14553_Y + attribute \src "libresoc.v:202976.17-202976.97" + wire $or$libresoc.v:202976$14556_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -415369,11 +388386,11 @@ module \upd_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:200246.7-200246.15" + attribute \src "libresoc.v:202935.7-202935.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -415390,7 +388407,7 @@ module \upd_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_upd attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:200281$14564 + cell $and $and$libresoc.v:202970$14550 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415398,10 +388415,10 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:200281$14564_Y + connect \Y $and$libresoc.v:202970$14550_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:200286$14569 + cell $and $and$libresoc.v:202975$14555 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415409,34 +388426,34 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:200286$14569_Y + connect \Y $and$libresoc.v:202975$14555_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:200283$14566 + cell $not $not$libresoc.v:202972$14552 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_upd - connect \Y $not$libresoc.v:200283$14566_Y + connect \Y $not$libresoc.v:202972$14552_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:200285$14568 + cell $not $not$libresoc.v:202974$14554 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_upd - connect \Y $not$libresoc.v:200285$14568_Y + connect \Y $not$libresoc.v:202974$14554_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:200288$14571 + cell $not $not$libresoc.v:202977$14557 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_upd - connect \Y $not$libresoc.v:200288$14571_Y + connect \Y $not$libresoc.v:202977$14557_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:200282$14565 + cell $or $or$libresoc.v:202971$14551 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415444,10 +388461,10 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_upd - connect \Y $or$libresoc.v:200282$14565_Y + connect \Y $or$libresoc.v:202971$14551_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:200284$14567 + cell $or $or$libresoc.v:202973$14553 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415455,10 +388472,10 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \q_upd connect \B \q_int - connect \Y $or$libresoc.v:200284$14567_Y + connect \Y $or$libresoc.v:202973$14553_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:200287$14570 + cell $or $or$libresoc.v:202976$14556 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415466,39 +388483,39 @@ module \upd_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_upd - connect \Y $or$libresoc.v:200287$14570_Y + connect \Y $or$libresoc.v:202976$14556_Y end - attribute \src "libresoc.v:200246.7-200246.20" - process $proc$libresoc.v:200246$14576 + attribute \src "libresoc.v:202935.7-202935.20" + process $proc$libresoc.v:202935$14562 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:200268.7-200268.19" - process $proc$libresoc.v:200268$14577 + attribute \src "libresoc.v:202957.7-202957.19" + process $proc$libresoc.v:202957$14563 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:200289.3-200290.27" - process $proc$libresoc.v:200289$14572 + attribute \src "libresoc.v:202978.3-202979.27" + process $proc$libresoc.v:202978$14558 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:200291.3-200299.6" - process $proc$libresoc.v:200291$14573 + attribute \src "libresoc.v:202980.3-202988.6" + process $proc$libresoc.v:202980$14559 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$14574 $1\q_int$next[0:0]$14575 - attribute \src "libresoc.v:200292.5-200292.29" + assign $0\q_int$next[0:0]$14560 $1\q_int$next[0:0]$14561 + attribute \src "libresoc.v:202981.5-202981.29" switch \initial - attribute \src "libresoc.v:200292.9-200292.17" + attribute \src "libresoc.v:202981.9-202981.17" case 1'1 case end @@ -415507,56 +388524,56 @@ module \upd_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$14575 1'0 + assign $1\q_int$next[0:0]$14561 1'0 case - assign $1\q_int$next[0:0]$14575 \$5 + assign $1\q_int$next[0:0]$14561 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$14574 + update \q_int$next $0\q_int$next[0:0]$14560 end - connect \$9 $and$libresoc.v:200281$14564_Y - connect \$11 $or$libresoc.v:200282$14565_Y - connect \$13 $not$libresoc.v:200283$14566_Y - connect \$15 $or$libresoc.v:200284$14567_Y - connect \$1 $not$libresoc.v:200285$14568_Y - connect \$3 $and$libresoc.v:200286$14569_Y - connect \$5 $or$libresoc.v:200287$14570_Y - connect \$7 $not$libresoc.v:200288$14571_Y + connect \$9 $and$libresoc.v:202970$14550_Y + connect \$11 $or$libresoc.v:202971$14551_Y + connect \$13 $not$libresoc.v:202972$14552_Y + connect \$15 $or$libresoc.v:202973$14553_Y + connect \$1 $not$libresoc.v:202974$14554_Y + connect \$3 $and$libresoc.v:202975$14555_Y + connect \$5 $or$libresoc.v:202976$14556_Y + connect \$7 $not$libresoc.v:202977$14557_Y connect \qlq_upd \$15 connect \qn_upd \$13 connect \q_upd \$11 end -attribute \src "libresoc.v:200307.1-200365.10" +attribute \src "libresoc.v:202996.1-203054.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.l0.pimem.valid_l" attribute \generator "nMigen" module \valid_l - attribute \src "libresoc.v:200308.7-200308.20" + attribute \src "libresoc.v:202997.7-202997.20" wire $0\initial[0:0] - attribute \src "libresoc.v:200353.3-200361.6" - wire $0\q_int$next[0:0]$14588 - attribute \src "libresoc.v:200351.3-200352.27" + attribute \src "libresoc.v:203042.3-203050.6" + wire $0\q_int$next[0:0]$14574 + attribute \src "libresoc.v:203040.3-203041.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:200353.3-200361.6" - wire $1\q_int$next[0:0]$14589 - attribute \src "libresoc.v:200330.7-200330.19" + attribute \src "libresoc.v:203042.3-203050.6" + wire $1\q_int$next[0:0]$14575 + attribute \src "libresoc.v:203019.7-203019.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:200343.17-200343.96" - wire $and$libresoc.v:200343$14578_Y - attribute \src "libresoc.v:200348.17-200348.96" - wire $and$libresoc.v:200348$14583_Y - attribute \src "libresoc.v:200345.18-200345.95" - wire $not$libresoc.v:200345$14580_Y - attribute \src "libresoc.v:200347.17-200347.94" - wire $not$libresoc.v:200347$14582_Y - attribute \src "libresoc.v:200350.17-200350.94" - wire $not$libresoc.v:200350$14585_Y - attribute \src "libresoc.v:200344.18-200344.100" - wire $or$libresoc.v:200344$14579_Y - attribute \src "libresoc.v:200346.18-200346.101" - wire $or$libresoc.v:200346$14581_Y - attribute \src "libresoc.v:200349.17-200349.99" - wire $or$libresoc.v:200349$14584_Y + attribute \src "libresoc.v:203032.17-203032.96" + wire $and$libresoc.v:203032$14564_Y + attribute \src "libresoc.v:203037.17-203037.96" + wire $and$libresoc.v:203037$14569_Y + attribute \src "libresoc.v:203034.18-203034.95" + wire $not$libresoc.v:203034$14566_Y + attribute \src "libresoc.v:203036.17-203036.94" + wire $not$libresoc.v:203036$14568_Y + attribute \src "libresoc.v:203039.17-203039.94" + wire $not$libresoc.v:203039$14571_Y + attribute \src "libresoc.v:203033.18-203033.100" + wire $or$libresoc.v:203033$14565_Y + attribute \src "libresoc.v:203035.18-203035.101" + wire $or$libresoc.v:203035$14567_Y + attribute \src "libresoc.v:203038.17-203038.99" + wire $or$libresoc.v:203038$14570_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -415573,11 +388590,11 @@ module \valid_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:200308.7-200308.15" + attribute \src "libresoc.v:202997.7-202997.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -415594,7 +388611,7 @@ module \valid_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_valid attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:200343$14578 + cell $and $and$libresoc.v:203032$14564 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415602,10 +388619,10 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:200343$14578_Y + connect \Y $and$libresoc.v:203032$14564_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:200348$14583 + cell $and $and$libresoc.v:203037$14569 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415613,34 +388630,34 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:200348$14583_Y + connect \Y $and$libresoc.v:203037$14569_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:200345$14580 + cell $not $not$libresoc.v:203034$14566 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_valid - connect \Y $not$libresoc.v:200345$14580_Y + connect \Y $not$libresoc.v:203034$14566_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:200347$14582 + cell $not $not$libresoc.v:203036$14568 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_valid - connect \Y $not$libresoc.v:200347$14582_Y + connect \Y $not$libresoc.v:203036$14568_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:200350$14585 + cell $not $not$libresoc.v:203039$14571 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_valid - connect \Y $not$libresoc.v:200350$14585_Y + connect \Y $not$libresoc.v:203039$14571_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:200344$14579 + cell $or $or$libresoc.v:203033$14565 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415648,10 +388665,10 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_valid - connect \Y $or$libresoc.v:200344$14579_Y + connect \Y $or$libresoc.v:203033$14565_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:200346$14581 + cell $or $or$libresoc.v:203035$14567 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415659,10 +388676,10 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \q_valid connect \B \q_int - connect \Y $or$libresoc.v:200346$14581_Y + connect \Y $or$libresoc.v:203035$14567_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:200349$14584 + cell $or $or$libresoc.v:203038$14570 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415670,39 +388687,39 @@ module \valid_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_valid - connect \Y $or$libresoc.v:200349$14584_Y + connect \Y $or$libresoc.v:203038$14570_Y end - attribute \src "libresoc.v:200308.7-200308.20" - process $proc$libresoc.v:200308$14590 + attribute \src "libresoc.v:202997.7-202997.20" + process $proc$libresoc.v:202997$14576 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:200330.7-200330.19" - process $proc$libresoc.v:200330$14591 + attribute \src "libresoc.v:203019.7-203019.19" + process $proc$libresoc.v:203019$14577 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:200351.3-200352.27" - process $proc$libresoc.v:200351$14586 + attribute \src "libresoc.v:203040.3-203041.27" + process $proc$libresoc.v:203040$14572 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:200353.3-200361.6" - process $proc$libresoc.v:200353$14587 + attribute \src "libresoc.v:203042.3-203050.6" + process $proc$libresoc.v:203042$14573 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$14588 $1\q_int$next[0:0]$14589 - attribute \src "libresoc.v:200354.5-200354.29" + assign $0\q_int$next[0:0]$14574 $1\q_int$next[0:0]$14575 + attribute \src "libresoc.v:203043.5-203043.29" switch \initial - attribute \src "libresoc.v:200354.9-200354.17" + attribute \src "libresoc.v:203043.9-203043.17" case 1'1 case end @@ -415711,56 +388728,56 @@ module \valid_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$14589 1'0 + assign $1\q_int$next[0:0]$14575 1'0 case - assign $1\q_int$next[0:0]$14589 \$5 + assign $1\q_int$next[0:0]$14575 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$14588 + update \q_int$next $0\q_int$next[0:0]$14574 end - connect \$9 $and$libresoc.v:200343$14578_Y - connect \$11 $or$libresoc.v:200344$14579_Y - connect \$13 $not$libresoc.v:200345$14580_Y - connect \$15 $or$libresoc.v:200346$14581_Y - connect \$1 $not$libresoc.v:200347$14582_Y - connect \$3 $and$libresoc.v:200348$14583_Y - connect \$5 $or$libresoc.v:200349$14584_Y - connect \$7 $not$libresoc.v:200350$14585_Y + connect \$9 $and$libresoc.v:203032$14564_Y + connect \$11 $or$libresoc.v:203033$14565_Y + connect \$13 $not$libresoc.v:203034$14566_Y + connect \$15 $or$libresoc.v:203035$14567_Y + connect \$1 $not$libresoc.v:203036$14568_Y + connect \$3 $and$libresoc.v:203037$14569_Y + connect \$5 $or$libresoc.v:203038$14570_Y + connect \$7 $not$libresoc.v:203039$14571_Y connect \qlq_valid \$15 connect \qn_valid \$13 connect \q_valid \$11 end -attribute \src "libresoc.v:200369.1-200427.10" +attribute \src "libresoc.v:203058.1-203116.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.fus.ldst0.wri_l" attribute \generator "nMigen" module \wri_l - attribute \src "libresoc.v:200370.7-200370.20" + attribute \src "libresoc.v:203059.7-203059.20" wire $0\initial[0:0] - attribute \src "libresoc.v:200415.3-200423.6" - wire $0\q_int$next[0:0]$14602 - attribute \src "libresoc.v:200413.3-200414.27" + attribute \src "libresoc.v:203104.3-203112.6" + wire $0\q_int$next[0:0]$14588 + attribute \src "libresoc.v:203102.3-203103.27" wire $0\q_int[0:0] - attribute \src "libresoc.v:200415.3-200423.6" - wire $1\q_int$next[0:0]$14603 - attribute \src "libresoc.v:200392.7-200392.19" + attribute \src "libresoc.v:203104.3-203112.6" + wire $1\q_int$next[0:0]$14589 + attribute \src "libresoc.v:203081.7-203081.19" wire $1\q_int[0:0] - attribute \src "libresoc.v:200405.17-200405.96" - wire $and$libresoc.v:200405$14592_Y - attribute \src "libresoc.v:200410.17-200410.96" - wire $and$libresoc.v:200410$14597_Y - attribute \src "libresoc.v:200407.18-200407.93" - wire $not$libresoc.v:200407$14594_Y - attribute \src "libresoc.v:200409.17-200409.92" - wire $not$libresoc.v:200409$14596_Y - attribute \src "libresoc.v:200412.17-200412.92" - wire $not$libresoc.v:200412$14599_Y - attribute \src "libresoc.v:200406.18-200406.98" - wire $or$libresoc.v:200406$14593_Y - attribute \src "libresoc.v:200408.18-200408.99" - wire $or$libresoc.v:200408$14595_Y - attribute \src "libresoc.v:200411.17-200411.97" - wire $or$libresoc.v:200411$14598_Y + attribute \src "libresoc.v:203094.17-203094.96" + wire $and$libresoc.v:203094$14578_Y + attribute \src "libresoc.v:203099.17-203099.96" + wire $and$libresoc.v:203099$14583_Y + attribute \src "libresoc.v:203096.18-203096.93" + wire $not$libresoc.v:203096$14580_Y + attribute \src "libresoc.v:203098.17-203098.92" + wire $not$libresoc.v:203098$14582_Y + attribute \src "libresoc.v:203101.17-203101.92" + wire $not$libresoc.v:203101$14585_Y + attribute \src "libresoc.v:203095.18-203095.98" + wire $or$libresoc.v:203095$14579_Y + attribute \src "libresoc.v:203097.18-203097.99" + wire $or$libresoc.v:203097$14581_Y + attribute \src "libresoc.v:203100.17-203100.97" + wire $or$libresoc.v:203100$14584_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" @@ -415777,11 +388794,11 @@ module \wri_l wire \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" wire \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 5 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst - attribute \src "libresoc.v:200370.7-200370.15" + attribute \src "libresoc.v:203059.7-203059.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" wire \q_int @@ -415798,7 +388815,7 @@ module \wri_l attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:65" wire input 2 \s_wri attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $and $and$libresoc.v:200405$14592 + cell $and $and$libresoc.v:203094$14578 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415806,10 +388823,10 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$7 - connect \Y $and$libresoc.v:200405$14592_Y + connect \Y $and$libresoc.v:203094$14578_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $and $and$libresoc.v:200410$14597 + cell $and $and$libresoc.v:203099$14583 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415817,34 +388834,34 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \q_int connect \B \$1 - connect \Y $and$libresoc.v:200410$14597_Y + connect \Y $and$libresoc.v:203099$14583_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:80" - cell $not $not$libresoc.v:200407$14594 + cell $not $not$libresoc.v:203096$14580 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \q_wri - connect \Y $not$libresoc.v:200407$14594_Y + connect \Y $not$libresoc.v:203096$14580_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $not $not$libresoc.v:200409$14596 + cell $not $not$libresoc.v:203098$14582 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_wri - connect \Y $not$libresoc.v:200409$14596_Y + connect \Y $not$libresoc.v:203098$14582_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $not $not$libresoc.v:200412$14599 + cell $not $not$libresoc.v:203101$14585 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \r_wri - connect \Y $not$libresoc.v:200412$14599_Y + connect \Y $not$libresoc.v:203101$14585_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:79" - cell $or $or$libresoc.v:200406$14593 + cell $or $or$libresoc.v:203095$14579 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415852,10 +388869,10 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \$9 connect \B \s_wri - connect \Y $or$libresoc.v:200406$14593_Y + connect \Y $or$libresoc.v:203095$14579_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:81" - cell $or $or$libresoc.v:200408$14595 + cell $or $or$libresoc.v:203097$14581 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415863,10 +388880,10 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \q_wri connect \B \q_int - connect \Y $or$libresoc.v:200408$14595_Y + connect \Y $or$libresoc.v:203097$14581_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:75" - cell $or $or$libresoc.v:200411$14598 + cell $or $or$libresoc.v:203100$14584 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -415874,39 +388891,39 @@ module \wri_l parameter \Y_WIDTH 1 connect \A \$3 connect \B \s_wri - connect \Y $or$libresoc.v:200411$14598_Y + connect \Y $or$libresoc.v:203100$14584_Y end - attribute \src "libresoc.v:200370.7-200370.20" - process $proc$libresoc.v:200370$14604 + attribute \src "libresoc.v:203059.7-203059.20" + process $proc$libresoc.v:203059$14590 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:200392.7-200392.19" - process $proc$libresoc.v:200392$14605 + attribute \src "libresoc.v:203081.7-203081.19" + process $proc$libresoc.v:203081$14591 assign { } { } assign $1\q_int[0:0] 1'0 sync always sync init update \q_int $1\q_int[0:0] end - attribute \src "libresoc.v:200413.3-200414.27" - process $proc$libresoc.v:200413$14600 + attribute \src "libresoc.v:203102.3-203103.27" + process $proc$libresoc.v:203102$14586 assign { } { } assign $0\q_int[0:0] \q_int$next sync posedge \coresync_clk update \q_int $0\q_int[0:0] end - attribute \src "libresoc.v:200415.3-200423.6" - process $proc$libresoc.v:200415$14601 + attribute \src "libresoc.v:203104.3-203112.6" + process $proc$libresoc.v:203104$14587 assign { } { } assign { } { } - assign $0\q_int$next[0:0]$14602 $1\q_int$next[0:0]$14603 - attribute \src "libresoc.v:200416.5-200416.29" + assign $0\q_int$next[0:0]$14588 $1\q_int$next[0:0]$14589 + attribute \src "libresoc.v:203105.5-203105.29" switch \initial - attribute \src "libresoc.v:200416.9-200416.17" + attribute \src "libresoc.v:203105.9-203105.17" case 1'1 case end @@ -415915,54 +388932,54 @@ module \wri_l attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\q_int$next[0:0]$14603 1'0 + assign $1\q_int$next[0:0]$14589 1'0 case - assign $1\q_int$next[0:0]$14603 \$5 + assign $1\q_int$next[0:0]$14589 \$5 end sync always - update \q_int$next $0\q_int$next[0:0]$14602 + update \q_int$next $0\q_int$next[0:0]$14588 end - connect \$9 $and$libresoc.v:200405$14592_Y - connect \$11 $or$libresoc.v:200406$14593_Y - connect \$13 $not$libresoc.v:200407$14594_Y - connect \$15 $or$libresoc.v:200408$14595_Y - connect \$1 $not$libresoc.v:200409$14596_Y - connect \$3 $and$libresoc.v:200410$14597_Y - connect \$5 $or$libresoc.v:200411$14598_Y - connect \$7 $not$libresoc.v:200412$14599_Y + connect \$9 $and$libresoc.v:203094$14578_Y + connect \$11 $or$libresoc.v:203095$14579_Y + connect \$13 $not$libresoc.v:203096$14580_Y + connect \$15 $or$libresoc.v:203097$14581_Y + connect \$1 $not$libresoc.v:203098$14582_Y + connect \$3 $and$libresoc.v:203099$14583_Y + connect \$5 $or$libresoc.v:203100$14584_Y + connect \$7 $not$libresoc.v:203101$14585_Y connect \qlq_wri \$15 connect \qn_wri \$13 connect \q_wri \$11 end -attribute \src "libresoc.v:200431.1-200497.10" +attribute \src "libresoc.v:203120.1-203186.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_CR_cr_a" attribute \generator "nMigen" module \wrpick_CR_cr_a - attribute \src "libresoc.v:200476.17-200476.91" - wire $not$libresoc.v:200476$14606_Y - attribute \src "libresoc.v:200478.18-200478.93" - wire $not$libresoc.v:200478$14608_Y - attribute \src "libresoc.v:200480.18-200480.93" - wire $not$libresoc.v:200480$14610_Y - attribute \src "libresoc.v:200481.17-200481.89" - wire width 6 $not$libresoc.v:200481$14611_Y - attribute \src "libresoc.v:200483.18-200483.93" - wire $not$libresoc.v:200483$14613_Y - attribute \src "libresoc.v:200486.17-200486.91" - wire $not$libresoc.v:200486$14616_Y - attribute \src "libresoc.v:200477.18-200477.106" - wire $reduce_or$libresoc.v:200477$14607_Y - attribute \src "libresoc.v:200479.18-200479.106" - wire $reduce_or$libresoc.v:200479$14609_Y - attribute \src "libresoc.v:200482.18-200482.106" - wire $reduce_or$libresoc.v:200482$14612_Y - attribute \src "libresoc.v:200484.18-200484.90" - wire $reduce_or$libresoc.v:200484$14614_Y - attribute \src "libresoc.v:200485.17-200485.103" - wire $reduce_or$libresoc.v:200485$14615_Y - attribute \src "libresoc.v:200487.17-200487.105" - wire $reduce_or$libresoc.v:200487$14617_Y + attribute \src "libresoc.v:203165.17-203165.91" + wire $not$libresoc.v:203165$14592_Y + attribute \src "libresoc.v:203167.18-203167.93" + wire $not$libresoc.v:203167$14594_Y + attribute \src "libresoc.v:203169.18-203169.93" + wire $not$libresoc.v:203169$14596_Y + attribute \src "libresoc.v:203170.17-203170.89" + wire width 6 $not$libresoc.v:203170$14597_Y + attribute \src "libresoc.v:203172.18-203172.93" + wire $not$libresoc.v:203172$14599_Y + attribute \src "libresoc.v:203175.17-203175.91" + wire $not$libresoc.v:203175$14602_Y + attribute \src "libresoc.v:203166.18-203166.106" + wire $reduce_or$libresoc.v:203166$14593_Y + attribute \src "libresoc.v:203168.18-203168.106" + wire $reduce_or$libresoc.v:203168$14595_Y + attribute \src "libresoc.v:203171.18-203171.106" + wire $reduce_or$libresoc.v:203171$14598_Y + attribute \src "libresoc.v:203173.18-203173.90" + wire $reduce_or$libresoc.v:203173$14600_Y + attribute \src "libresoc.v:203174.17-203174.103" + wire $reduce_or$libresoc.v:203174$14601_Y + attribute \src "libresoc.v:203176.17-203176.105" + wire $reduce_or$libresoc.v:203176$14603_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 6 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -416008,113 +389025,113 @@ module \wrpick_CR_cr_a attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t5 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:200476$14606 + cell $not $not$libresoc.v:203165$14592 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:200476$14606_Y + connect \Y $not$libresoc.v:203165$14592_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:200478$14608 + cell $not $not$libresoc.v:203167$14594 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:200478$14608_Y + connect \Y $not$libresoc.v:203167$14594_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:200480$14610 + cell $not $not$libresoc.v:203169$14596 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:200480$14610_Y + connect \Y $not$libresoc.v:203169$14596_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:200481$14611 + cell $not $not$libresoc.v:203170$14597 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 6 connect \A \i - connect \Y $not$libresoc.v:200481$14611_Y + connect \Y $not$libresoc.v:203170$14597_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:200483$14613 + cell $not $not$libresoc.v:203172$14599 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:200483$14613_Y + connect \Y $not$libresoc.v:203172$14599_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:200486$14616 + cell $not $not$libresoc.v:203175$14602 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:200486$14616_Y + connect \Y $not$libresoc.v:203175$14602_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:200477$14607 + cell $reduce_or $reduce_or$libresoc.v:203166$14593 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:200477$14607_Y + connect \Y $reduce_or$libresoc.v:203166$14593_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:200479$14609 + cell $reduce_or $reduce_or$libresoc.v:203168$14595 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:200479$14609_Y + connect \Y $reduce_or$libresoc.v:203168$14595_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:200482$14612 + cell $reduce_or $reduce_or$libresoc.v:203171$14598 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:200482$14612_Y + connect \Y $reduce_or$libresoc.v:203171$14598_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:200484$14614 + cell $reduce_or $reduce_or$libresoc.v:203173$14600 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:200484$14614_Y + connect \Y $reduce_or$libresoc.v:203173$14600_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:200485$14615 + cell $reduce_or $reduce_or$libresoc.v:203174$14601 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:200485$14615_Y + connect \Y $reduce_or$libresoc.v:203174$14601_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:200487$14617 + cell $reduce_or $reduce_or$libresoc.v:203176$14603 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:200487$14617_Y - end - connect \$7 $not$libresoc.v:200476$14606_Y - connect \$12 $reduce_or$libresoc.v:200477$14607_Y - connect \$11 $not$libresoc.v:200478$14608_Y - connect \$16 $reduce_or$libresoc.v:200479$14609_Y - connect \$15 $not$libresoc.v:200480$14610_Y - connect \$1 $not$libresoc.v:200481$14611_Y - connect \$20 $reduce_or$libresoc.v:200482$14612_Y - connect \$19 $not$libresoc.v:200483$14613_Y - connect \$23 $reduce_or$libresoc.v:200484$14614_Y - connect \$4 $reduce_or$libresoc.v:200485$14615_Y - connect \$3 $not$libresoc.v:200486$14616_Y - connect \$8 $reduce_or$libresoc.v:200487$14617_Y + connect \Y $reduce_or$libresoc.v:203176$14603_Y + end + connect \$7 $not$libresoc.v:203165$14592_Y + connect \$12 $reduce_or$libresoc.v:203166$14593_Y + connect \$11 $not$libresoc.v:203167$14594_Y + connect \$16 $reduce_or$libresoc.v:203168$14595_Y + connect \$15 $not$libresoc.v:203169$14596_Y + connect \$1 $not$libresoc.v:203170$14597_Y + connect \$20 $reduce_or$libresoc.v:203171$14598_Y + connect \$19 $not$libresoc.v:203172$14599_Y + connect \$23 $reduce_or$libresoc.v:203173$14600_Y + connect \$4 $reduce_or$libresoc.v:203174$14601_Y + connect \$3 $not$libresoc.v:203175$14602_Y + connect \$8 $reduce_or$libresoc.v:203176$14603_Y connect \en_o \$23 connect \o { \t5 \t4 \t3 \t2 \t1 \t0 } connect \t5 \$19 @@ -416125,15 +389142,15 @@ module \wrpick_CR_cr_a connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:200501.1-200522.10" +attribute \src "libresoc.v:203190.1-203211.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_CR_full_cr" attribute \generator "nMigen" module \wrpick_CR_full_cr - attribute \src "libresoc.v:200516.17-200516.89" - wire $not$libresoc.v:200516$14618_Y - attribute \src "libresoc.v:200517.17-200517.89" - wire $reduce_or$libresoc.v:200517$14619_Y + attribute \src "libresoc.v:203205.17-203205.89" + wire $not$libresoc.v:203205$14604_Y + attribute \src "libresoc.v:203206.17-203206.89" + wire $reduce_or$libresoc.v:203206$14605_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -416149,53 +389166,53 @@ module \wrpick_CR_full_cr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:200516$14618 + cell $not $not$libresoc.v:203205$14604 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:200516$14618_Y + connect \Y $not$libresoc.v:203205$14604_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:200517$14619 + cell $reduce_or $reduce_or$libresoc.v:203206$14605 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:200517$14619_Y + connect \Y $reduce_or$libresoc.v:203206$14605_Y end - connect \$1 $not$libresoc.v:200516$14618_Y - connect \$3 $reduce_or$libresoc.v:200517$14619_Y + connect \$1 $not$libresoc.v:203205$14604_Y + connect \$3 $reduce_or$libresoc.v:203206$14605_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:200526.1-200583.10" +attribute \src "libresoc.v:203215.1-203272.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_FAST_fast1" attribute \generator "nMigen" module \wrpick_FAST_fast1 - attribute \src "libresoc.v:200565.17-200565.91" - wire $not$libresoc.v:200565$14620_Y - attribute \src "libresoc.v:200567.18-200567.93" - wire $not$libresoc.v:200567$14622_Y - attribute \src "libresoc.v:200569.18-200569.93" - wire $not$libresoc.v:200569$14624_Y - attribute \src "libresoc.v:200570.17-200570.89" - wire width 5 $not$libresoc.v:200570$14625_Y - attribute \src "libresoc.v:200573.17-200573.91" - wire $not$libresoc.v:200573$14628_Y - attribute \src "libresoc.v:200566.18-200566.106" - wire $reduce_or$libresoc.v:200566$14621_Y - attribute \src "libresoc.v:200568.18-200568.106" - wire $reduce_or$libresoc.v:200568$14623_Y - attribute \src "libresoc.v:200571.18-200571.90" - wire $reduce_or$libresoc.v:200571$14626_Y - attribute \src "libresoc.v:200572.17-200572.103" - wire $reduce_or$libresoc.v:200572$14627_Y - attribute \src "libresoc.v:200574.17-200574.105" - wire $reduce_or$libresoc.v:200574$14629_Y + attribute \src "libresoc.v:203254.17-203254.91" + wire $not$libresoc.v:203254$14606_Y + attribute \src "libresoc.v:203256.18-203256.93" + wire $not$libresoc.v:203256$14608_Y + attribute \src "libresoc.v:203258.18-203258.93" + wire $not$libresoc.v:203258$14610_Y + attribute \src "libresoc.v:203259.17-203259.89" + wire width 5 $not$libresoc.v:203259$14611_Y + attribute \src "libresoc.v:203262.17-203262.91" + wire $not$libresoc.v:203262$14614_Y + attribute \src "libresoc.v:203255.18-203255.106" + wire $reduce_or$libresoc.v:203255$14607_Y + attribute \src "libresoc.v:203257.18-203257.106" + wire $reduce_or$libresoc.v:203257$14609_Y + attribute \src "libresoc.v:203260.18-203260.90" + wire $reduce_or$libresoc.v:203260$14612_Y + attribute \src "libresoc.v:203261.17-203261.103" + wire $reduce_or$libresoc.v:203261$14613_Y + attribute \src "libresoc.v:203263.17-203263.105" + wire $reduce_or$libresoc.v:203263$14615_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 5 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -416235,95 +389252,95 @@ module \wrpick_FAST_fast1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:200565$14620 + cell $not $not$libresoc.v:203254$14606 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:200565$14620_Y + connect \Y $not$libresoc.v:203254$14606_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:200567$14622 + cell $not $not$libresoc.v:203256$14608 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:200567$14622_Y + connect \Y $not$libresoc.v:203256$14608_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:200569$14624 + cell $not $not$libresoc.v:203258$14610 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:200569$14624_Y + connect \Y $not$libresoc.v:203258$14610_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:200570$14625 + cell $not $not$libresoc.v:203259$14611 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 5 connect \A \i - connect \Y $not$libresoc.v:200570$14625_Y + connect \Y $not$libresoc.v:203259$14611_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:200573$14628 + cell $not $not$libresoc.v:203262$14614 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:200573$14628_Y + connect \Y $not$libresoc.v:203262$14614_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:200566$14621 + cell $reduce_or $reduce_or$libresoc.v:203255$14607 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:200566$14621_Y + connect \Y $reduce_or$libresoc.v:203255$14607_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:200568$14623 + cell $reduce_or $reduce_or$libresoc.v:203257$14609 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:200568$14623_Y + connect \Y $reduce_or$libresoc.v:203257$14609_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:200571$14626 + cell $reduce_or $reduce_or$libresoc.v:203260$14612 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:200571$14626_Y + connect \Y $reduce_or$libresoc.v:203260$14612_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:200572$14627 + cell $reduce_or $reduce_or$libresoc.v:203261$14613 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:200572$14627_Y + connect \Y $reduce_or$libresoc.v:203261$14613_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:200574$14629 + cell $reduce_or $reduce_or$libresoc.v:203263$14615 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:200574$14629_Y - end - connect \$7 $not$libresoc.v:200565$14620_Y - connect \$12 $reduce_or$libresoc.v:200566$14621_Y - connect \$11 $not$libresoc.v:200567$14622_Y - connect \$16 $reduce_or$libresoc.v:200568$14623_Y - connect \$15 $not$libresoc.v:200569$14624_Y - connect \$1 $not$libresoc.v:200570$14625_Y - connect \$19 $reduce_or$libresoc.v:200571$14626_Y - connect \$4 $reduce_or$libresoc.v:200572$14627_Y - connect \$3 $not$libresoc.v:200573$14628_Y - connect \$8 $reduce_or$libresoc.v:200574$14629_Y + connect \Y $reduce_or$libresoc.v:203263$14615_Y + end + connect \$7 $not$libresoc.v:203254$14606_Y + connect \$12 $reduce_or$libresoc.v:203255$14607_Y + connect \$11 $not$libresoc.v:203256$14608_Y + connect \$16 $reduce_or$libresoc.v:203257$14609_Y + connect \$15 $not$libresoc.v:203258$14610_Y + connect \$1 $not$libresoc.v:203259$14611_Y + connect \$19 $reduce_or$libresoc.v:203260$14612_Y + connect \$4 $reduce_or$libresoc.v:203261$14613_Y + connect \$3 $not$libresoc.v:203262$14614_Y + connect \$8 $reduce_or$libresoc.v:203263$14615_Y connect \en_o \$19 connect \o { \t4 \t3 \t2 \t1 \t0 } connect \t4 \$15 @@ -416333,51 +389350,51 @@ module \wrpick_FAST_fast1 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:200587.1-200689.10" +attribute \src "libresoc.v:203276.1-203378.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_INT_o" attribute \generator "nMigen" module \wrpick_INT_o - attribute \src "libresoc.v:200656.17-200656.91" - wire $not$libresoc.v:200656$14630_Y - attribute \src "libresoc.v:200658.18-200658.93" - wire $not$libresoc.v:200658$14632_Y - attribute \src "libresoc.v:200660.18-200660.93" - wire $not$libresoc.v:200660$14634_Y - attribute \src "libresoc.v:200661.17-200661.89" - wire width 10 $not$libresoc.v:200661$14635_Y - attribute \src "libresoc.v:200663.18-200663.93" - wire $not$libresoc.v:200663$14637_Y - attribute \src "libresoc.v:200665.18-200665.93" - wire $not$libresoc.v:200665$14639_Y - attribute \src "libresoc.v:200667.18-200667.93" - wire $not$libresoc.v:200667$14641_Y - attribute \src "libresoc.v:200669.18-200669.93" - wire $not$libresoc.v:200669$14643_Y - attribute \src "libresoc.v:200671.18-200671.93" - wire $not$libresoc.v:200671$14645_Y - attribute \src "libresoc.v:200674.17-200674.91" - wire $not$libresoc.v:200674$14648_Y - attribute \src "libresoc.v:200657.18-200657.106" - wire $reduce_or$libresoc.v:200657$14631_Y - attribute \src "libresoc.v:200659.18-200659.106" - wire $reduce_or$libresoc.v:200659$14633_Y - attribute \src "libresoc.v:200662.18-200662.106" - wire $reduce_or$libresoc.v:200662$14636_Y - attribute \src "libresoc.v:200664.18-200664.106" - wire $reduce_or$libresoc.v:200664$14638_Y - attribute \src "libresoc.v:200666.18-200666.106" - wire $reduce_or$libresoc.v:200666$14640_Y - attribute \src "libresoc.v:200668.18-200668.106" - wire $reduce_or$libresoc.v:200668$14642_Y - attribute \src "libresoc.v:200670.18-200670.106" - wire $reduce_or$libresoc.v:200670$14644_Y - attribute \src "libresoc.v:200672.18-200672.90" - wire $reduce_or$libresoc.v:200672$14646_Y - attribute \src "libresoc.v:200673.17-200673.103" - wire $reduce_or$libresoc.v:200673$14647_Y - attribute \src "libresoc.v:200675.17-200675.105" - wire $reduce_or$libresoc.v:200675$14649_Y + attribute \src "libresoc.v:203345.17-203345.91" + wire $not$libresoc.v:203345$14616_Y + attribute \src "libresoc.v:203347.18-203347.93" + wire $not$libresoc.v:203347$14618_Y + attribute \src "libresoc.v:203349.18-203349.93" + wire $not$libresoc.v:203349$14620_Y + attribute \src "libresoc.v:203350.17-203350.89" + wire width 10 $not$libresoc.v:203350$14621_Y + attribute \src "libresoc.v:203352.18-203352.93" + wire $not$libresoc.v:203352$14623_Y + attribute \src "libresoc.v:203354.18-203354.93" + wire $not$libresoc.v:203354$14625_Y + attribute \src "libresoc.v:203356.18-203356.93" + wire $not$libresoc.v:203356$14627_Y + attribute \src "libresoc.v:203358.18-203358.93" + wire $not$libresoc.v:203358$14629_Y + attribute \src "libresoc.v:203360.18-203360.93" + wire $not$libresoc.v:203360$14631_Y + attribute \src "libresoc.v:203363.17-203363.91" + wire $not$libresoc.v:203363$14634_Y + attribute \src "libresoc.v:203346.18-203346.106" + wire $reduce_or$libresoc.v:203346$14617_Y + attribute \src "libresoc.v:203348.18-203348.106" + wire $reduce_or$libresoc.v:203348$14619_Y + attribute \src "libresoc.v:203351.18-203351.106" + wire $reduce_or$libresoc.v:203351$14622_Y + attribute \src "libresoc.v:203353.18-203353.106" + wire $reduce_or$libresoc.v:203353$14624_Y + attribute \src "libresoc.v:203355.18-203355.106" + wire $reduce_or$libresoc.v:203355$14626_Y + attribute \src "libresoc.v:203357.18-203357.106" + wire $reduce_or$libresoc.v:203357$14628_Y + attribute \src "libresoc.v:203359.18-203359.106" + wire $reduce_or$libresoc.v:203359$14630_Y + attribute \src "libresoc.v:203361.18-203361.90" + wire $reduce_or$libresoc.v:203361$14632_Y + attribute \src "libresoc.v:203362.17-203362.103" + wire $reduce_or$libresoc.v:203362$14633_Y + attribute \src "libresoc.v:203364.17-203364.105" + wire $reduce_or$libresoc.v:203364$14635_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 10 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -416447,185 +389464,185 @@ module \wrpick_INT_o attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t9 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:200656$14630 + cell $not $not$libresoc.v:203345$14616 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:200656$14630_Y + connect \Y $not$libresoc.v:203345$14616_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:200658$14632 + cell $not $not$libresoc.v:203347$14618 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:200658$14632_Y + connect \Y $not$libresoc.v:203347$14618_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:200660$14634 + cell $not $not$libresoc.v:203349$14620 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$16 - connect \Y $not$libresoc.v:200660$14634_Y + connect \Y $not$libresoc.v:203349$14620_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:200661$14635 + cell $not $not$libresoc.v:203350$14621 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 10 connect \A \i - connect \Y $not$libresoc.v:200661$14635_Y + connect \Y $not$libresoc.v:203350$14621_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:200663$14637 + cell $not $not$libresoc.v:203352$14623 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$20 - connect \Y $not$libresoc.v:200663$14637_Y + connect \Y $not$libresoc.v:203352$14623_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:200665$14639 + cell $not $not$libresoc.v:203354$14625 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$24 - connect \Y $not$libresoc.v:200665$14639_Y + connect \Y $not$libresoc.v:203354$14625_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:200667$14641 + cell $not $not$libresoc.v:203356$14627 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$28 - connect \Y $not$libresoc.v:200667$14641_Y + connect \Y $not$libresoc.v:203356$14627_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:200669$14643 + cell $not $not$libresoc.v:203358$14629 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$32 - connect \Y $not$libresoc.v:200669$14643_Y + connect \Y $not$libresoc.v:203358$14629_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:200671$14645 + cell $not $not$libresoc.v:203360$14631 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$36 - connect \Y $not$libresoc.v:200671$14645_Y + connect \Y $not$libresoc.v:203360$14631_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:200674$14648 + cell $not $not$libresoc.v:203363$14634 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:200674$14648_Y + connect \Y $not$libresoc.v:203363$14634_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:200657$14631 + cell $reduce_or $reduce_or$libresoc.v:203346$14617 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:200657$14631_Y + connect \Y $reduce_or$libresoc.v:203346$14617_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:200659$14633 + cell $reduce_or $reduce_or$libresoc.v:203348$14619 parameter \A_SIGNED 0 parameter \A_WIDTH 5 parameter \Y_WIDTH 1 connect \A { \i [3:0] \ni [4] } - connect \Y $reduce_or$libresoc.v:200659$14633_Y + connect \Y $reduce_or$libresoc.v:203348$14619_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:200662$14636 + cell $reduce_or $reduce_or$libresoc.v:203351$14622 parameter \A_SIGNED 0 parameter \A_WIDTH 6 parameter \Y_WIDTH 1 connect \A { \i [4:0] \ni [5] } - connect \Y $reduce_or$libresoc.v:200662$14636_Y + connect \Y $reduce_or$libresoc.v:203351$14622_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:200664$14638 + cell $reduce_or $reduce_or$libresoc.v:203353$14624 parameter \A_SIGNED 0 parameter \A_WIDTH 7 parameter \Y_WIDTH 1 connect \A { \i [5:0] \ni [6] } - connect \Y $reduce_or$libresoc.v:200664$14638_Y + connect \Y $reduce_or$libresoc.v:203353$14624_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:200666$14640 + cell $reduce_or $reduce_or$libresoc.v:203355$14626 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \Y_WIDTH 1 connect \A { \i [6:0] \ni [7] } - connect \Y $reduce_or$libresoc.v:200666$14640_Y + connect \Y $reduce_or$libresoc.v:203355$14626_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:200668$14642 + cell $reduce_or $reduce_or$libresoc.v:203357$14628 parameter \A_SIGNED 0 parameter \A_WIDTH 9 parameter \Y_WIDTH 1 connect \A { \i [7:0] \ni [8] } - connect \Y $reduce_or$libresoc.v:200668$14642_Y + connect \Y $reduce_or$libresoc.v:203357$14628_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:200670$14644 + cell $reduce_or $reduce_or$libresoc.v:203359$14630 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 1 connect \A { \i [8:0] \ni [9] } - connect \Y $reduce_or$libresoc.v:200670$14644_Y + connect \Y $reduce_or$libresoc.v:203359$14630_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:200672$14646 + cell $reduce_or $reduce_or$libresoc.v:203361$14632 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:200672$14646_Y + connect \Y $reduce_or$libresoc.v:203361$14632_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:200673$14647 + cell $reduce_or $reduce_or$libresoc.v:203362$14633 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:200673$14647_Y + connect \Y $reduce_or$libresoc.v:203362$14633_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:200675$14649 + cell $reduce_or $reduce_or$libresoc.v:203364$14635 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:200675$14649_Y - end - connect \$7 $not$libresoc.v:200656$14630_Y - connect \$12 $reduce_or$libresoc.v:200657$14631_Y - connect \$11 $not$libresoc.v:200658$14632_Y - connect \$16 $reduce_or$libresoc.v:200659$14633_Y - connect \$15 $not$libresoc.v:200660$14634_Y - connect \$1 $not$libresoc.v:200661$14635_Y - connect \$20 $reduce_or$libresoc.v:200662$14636_Y - connect \$19 $not$libresoc.v:200663$14637_Y - connect \$24 $reduce_or$libresoc.v:200664$14638_Y - connect \$23 $not$libresoc.v:200665$14639_Y - connect \$28 $reduce_or$libresoc.v:200666$14640_Y - connect \$27 $not$libresoc.v:200667$14641_Y - connect \$32 $reduce_or$libresoc.v:200668$14642_Y - connect \$31 $not$libresoc.v:200669$14643_Y - connect \$36 $reduce_or$libresoc.v:200670$14644_Y - connect \$35 $not$libresoc.v:200671$14645_Y - connect \$39 $reduce_or$libresoc.v:200672$14646_Y - connect \$4 $reduce_or$libresoc.v:200673$14647_Y - connect \$3 $not$libresoc.v:200674$14648_Y - connect \$8 $reduce_or$libresoc.v:200675$14649_Y + connect \Y $reduce_or$libresoc.v:203364$14635_Y + end + connect \$7 $not$libresoc.v:203345$14616_Y + connect \$12 $reduce_or$libresoc.v:203346$14617_Y + connect \$11 $not$libresoc.v:203347$14618_Y + connect \$16 $reduce_or$libresoc.v:203348$14619_Y + connect \$15 $not$libresoc.v:203349$14620_Y + connect \$1 $not$libresoc.v:203350$14621_Y + connect \$20 $reduce_or$libresoc.v:203351$14622_Y + connect \$19 $not$libresoc.v:203352$14623_Y + connect \$24 $reduce_or$libresoc.v:203353$14624_Y + connect \$23 $not$libresoc.v:203354$14625_Y + connect \$28 $reduce_or$libresoc.v:203355$14626_Y + connect \$27 $not$libresoc.v:203356$14627_Y + connect \$32 $reduce_or$libresoc.v:203357$14628_Y + connect \$31 $not$libresoc.v:203358$14629_Y + connect \$36 $reduce_or$libresoc.v:203359$14630_Y + connect \$35 $not$libresoc.v:203360$14631_Y + connect \$39 $reduce_or$libresoc.v:203361$14632_Y + connect \$4 $reduce_or$libresoc.v:203362$14633_Y + connect \$3 $not$libresoc.v:203363$14634_Y + connect \$8 $reduce_or$libresoc.v:203364$14635_Y connect \en_o \$39 connect \o { \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } connect \t9 \$35 @@ -416640,15 +389657,15 @@ module \wrpick_INT_o connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:200693.1-200714.10" +attribute \src "libresoc.v:203382.1-203403.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_SPR_spr1" attribute \generator "nMigen" module \wrpick_SPR_spr1 - attribute \src "libresoc.v:200708.17-200708.89" - wire $not$libresoc.v:200708$14650_Y - attribute \src "libresoc.v:200709.17-200709.89" - wire $reduce_or$libresoc.v:200709$14651_Y + attribute \src "libresoc.v:203397.17-203397.89" + wire $not$libresoc.v:203397$14636_Y + attribute \src "libresoc.v:203398.17-203398.89" + wire $reduce_or$libresoc.v:203398$14637_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -416664,37 +389681,37 @@ module \wrpick_SPR_spr1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:200708$14650 + cell $not $not$libresoc.v:203397$14636 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:200708$14650_Y + connect \Y $not$libresoc.v:203397$14636_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:200709$14651 + cell $reduce_or $reduce_or$libresoc.v:203398$14637 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:200709$14651_Y + connect \Y $reduce_or$libresoc.v:203398$14637_Y end - connect \$1 $not$libresoc.v:200708$14650_Y - connect \$3 $reduce_or$libresoc.v:200709$14651_Y + connect \$1 $not$libresoc.v:203397$14636_Y + connect \$3 $reduce_or$libresoc.v:203398$14637_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:200718.1-200739.10" +attribute \src "libresoc.v:203407.1-203428.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_STATE_msr" attribute \generator "nMigen" module \wrpick_STATE_msr - attribute \src "libresoc.v:200733.17-200733.89" - wire $not$libresoc.v:200733$14652_Y - attribute \src "libresoc.v:200734.17-200734.89" - wire $reduce_or$libresoc.v:200734$14653_Y + attribute \src "libresoc.v:203422.17-203422.89" + wire $not$libresoc.v:203422$14638_Y + attribute \src "libresoc.v:203423.17-203423.89" + wire $reduce_or$libresoc.v:203423$14639_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -416710,41 +389727,41 @@ module \wrpick_STATE_msr attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t0 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:200733$14652 + cell $not $not$libresoc.v:203422$14638 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \i - connect \Y $not$libresoc.v:200733$14652_Y + connect \Y $not$libresoc.v:203422$14638_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:200734$14653 + cell $reduce_or $reduce_or$libresoc.v:203423$14639 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:200734$14653_Y + connect \Y $reduce_or$libresoc.v:203423$14639_Y end - connect \$1 $not$libresoc.v:200733$14652_Y - connect \$3 $reduce_or$libresoc.v:200734$14653_Y + connect \$1 $not$libresoc.v:203422$14638_Y + connect \$3 $reduce_or$libresoc.v:203423$14639_Y connect \en_o \$3 connect \o \t0 connect \t0 \i connect \ni \$1 end -attribute \src "libresoc.v:200743.1-200773.10" +attribute \src "libresoc.v:203432.1-203462.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_STATE_nia" attribute \generator "nMigen" module \wrpick_STATE_nia - attribute \src "libresoc.v:200764.17-200764.89" - wire width 2 $not$libresoc.v:200764$14654_Y - attribute \src "libresoc.v:200766.17-200766.91" - wire $not$libresoc.v:200766$14656_Y - attribute \src "libresoc.v:200765.17-200765.103" - wire $reduce_or$libresoc.v:200765$14655_Y - attribute \src "libresoc.v:200767.17-200767.89" - wire $reduce_or$libresoc.v:200767$14657_Y + attribute \src "libresoc.v:203453.17-203453.89" + wire width 2 $not$libresoc.v:203453$14640_Y + attribute \src "libresoc.v:203455.17-203455.91" + wire $not$libresoc.v:203455$14642_Y + attribute \src "libresoc.v:203454.17-203454.103" + wire $reduce_or$libresoc.v:203454$14641_Y + attribute \src "libresoc.v:203456.17-203456.89" + wire $reduce_or$libresoc.v:203456$14643_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 2 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -416766,64 +389783,64 @@ module \wrpick_STATE_nia attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:200764$14654 + cell $not $not$libresoc.v:203453$14640 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 2 connect \A \i - connect \Y $not$libresoc.v:200764$14654_Y + connect \Y $not$libresoc.v:203453$14640_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:200766$14656 + cell $not $not$libresoc.v:203455$14642 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:200766$14656_Y + connect \Y $not$libresoc.v:203455$14642_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:200765$14655 + cell $reduce_or $reduce_or$libresoc.v:203454$14641 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:200765$14655_Y + connect \Y $reduce_or$libresoc.v:203454$14641_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:200767$14657 + cell $reduce_or $reduce_or$libresoc.v:203456$14643 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:200767$14657_Y + connect \Y $reduce_or$libresoc.v:203456$14643_Y end - connect \$1 $not$libresoc.v:200764$14654_Y - connect \$4 $reduce_or$libresoc.v:200765$14655_Y - connect \$3 $not$libresoc.v:200766$14656_Y - connect \$7 $reduce_or$libresoc.v:200767$14657_Y + connect \$1 $not$libresoc.v:203453$14640_Y + connect \$4 $reduce_or$libresoc.v:203454$14641_Y + connect \$3 $not$libresoc.v:203455$14642_Y + connect \$7 $reduce_or$libresoc.v:203456$14643_Y connect \en_o \$7 connect \o { \t1 \t0 } connect \t1 \$3 connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:200777.1-200816.10" +attribute \src "libresoc.v:203466.1-203505.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_ca" attribute \generator "nMigen" module \wrpick_XER_xer_ca - attribute \src "libresoc.v:200804.17-200804.91" - wire $not$libresoc.v:200804$14658_Y - attribute \src "libresoc.v:200806.17-200806.89" - wire width 3 $not$libresoc.v:200806$14660_Y - attribute \src "libresoc.v:200808.17-200808.91" - wire $not$libresoc.v:200808$14662_Y - attribute \src "libresoc.v:200805.18-200805.90" - wire $reduce_or$libresoc.v:200805$14659_Y - attribute \src "libresoc.v:200807.17-200807.103" - wire $reduce_or$libresoc.v:200807$14661_Y - attribute \src "libresoc.v:200809.17-200809.105" - wire $reduce_or$libresoc.v:200809$14663_Y + attribute \src "libresoc.v:203493.17-203493.91" + wire $not$libresoc.v:203493$14644_Y + attribute \src "libresoc.v:203495.17-203495.89" + wire width 3 $not$libresoc.v:203495$14646_Y + attribute \src "libresoc.v:203497.17-203497.91" + wire $not$libresoc.v:203497$14648_Y + attribute \src "libresoc.v:203494.18-203494.90" + wire $reduce_or$libresoc.v:203494$14645_Y + attribute \src "libresoc.v:203496.17-203496.103" + wire $reduce_or$libresoc.v:203496$14647_Y + attribute \src "libresoc.v:203498.17-203498.105" + wire $reduce_or$libresoc.v:203498$14649_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 3 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" @@ -416851,59 +389868,59 @@ module \wrpick_XER_xer_ca attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t2 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:200804$14658 + cell $not $not$libresoc.v:203493$14644 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:200804$14658_Y + connect \Y $not$libresoc.v:203493$14644_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:200806$14660 + cell $not $not$libresoc.v:203495$14646 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 3 connect \A \i - connect \Y $not$libresoc.v:200806$14660_Y + connect \Y $not$libresoc.v:203495$14646_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:200808$14662 + cell $not $not$libresoc.v:203497$14648 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:200808$14662_Y + connect \Y $not$libresoc.v:203497$14648_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:200805$14659 + cell $reduce_or $reduce_or$libresoc.v:203494$14645 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:200805$14659_Y + connect \Y $reduce_or$libresoc.v:203494$14645_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:200807$14661 + cell $reduce_or $reduce_or$libresoc.v:203496$14647 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:200807$14661_Y + connect \Y $reduce_or$libresoc.v:203496$14647_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:200809$14663 + cell $reduce_or $reduce_or$libresoc.v:203498$14649 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:200809$14663_Y - end - connect \$7 $not$libresoc.v:200804$14658_Y - connect \$11 $reduce_or$libresoc.v:200805$14659_Y - connect \$1 $not$libresoc.v:200806$14660_Y - connect \$4 $reduce_or$libresoc.v:200807$14661_Y - connect \$3 $not$libresoc.v:200808$14662_Y - connect \$8 $reduce_or$libresoc.v:200809$14663_Y + connect \Y $reduce_or$libresoc.v:203498$14649_Y + end + connect \$7 $not$libresoc.v:203493$14644_Y + connect \$11 $reduce_or$libresoc.v:203494$14645_Y + connect \$1 $not$libresoc.v:203495$14646_Y + connect \$4 $reduce_or$libresoc.v:203496$14647_Y + connect \$3 $not$libresoc.v:203497$14648_Y + connect \$8 $reduce_or$libresoc.v:203498$14649_Y connect \en_o \$11 connect \o { \t2 \t1 \t0 } connect \t2 \$7 @@ -416911,27 +389928,27 @@ module \wrpick_XER_xer_ca connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:200820.1-200868.10" +attribute \src "libresoc.v:203509.1-203557.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_ov" attribute \generator "nMigen" module \wrpick_XER_xer_ov - attribute \src "libresoc.v:200853.17-200853.91" - wire $not$libresoc.v:200853$14664_Y - attribute \src "libresoc.v:200855.18-200855.93" - wire $not$libresoc.v:200855$14666_Y - attribute \src "libresoc.v:200857.17-200857.89" - wire width 4 $not$libresoc.v:200857$14668_Y - attribute \src "libresoc.v:200859.17-200859.91" - wire $not$libresoc.v:200859$14670_Y - attribute \src "libresoc.v:200854.18-200854.106" - wire $reduce_or$libresoc.v:200854$14665_Y - attribute \src "libresoc.v:200856.18-200856.90" - wire $reduce_or$libresoc.v:200856$14667_Y - attribute \src "libresoc.v:200858.17-200858.103" - wire $reduce_or$libresoc.v:200858$14669_Y - attribute \src "libresoc.v:200860.17-200860.105" - wire $reduce_or$libresoc.v:200860$14671_Y + attribute \src "libresoc.v:203542.17-203542.91" + wire $not$libresoc.v:203542$14650_Y + attribute \src "libresoc.v:203544.18-203544.93" + wire $not$libresoc.v:203544$14652_Y + attribute \src "libresoc.v:203546.17-203546.89" + wire width 4 $not$libresoc.v:203546$14654_Y + attribute \src "libresoc.v:203548.17-203548.91" + wire $not$libresoc.v:203548$14656_Y + attribute \src "libresoc.v:203543.18-203543.106" + wire $reduce_or$libresoc.v:203543$14651_Y + attribute \src "libresoc.v:203545.18-203545.90" + wire $reduce_or$libresoc.v:203545$14653_Y + attribute \src "libresoc.v:203547.17-203547.103" + wire $reduce_or$libresoc.v:203547$14655_Y + attribute \src "libresoc.v:203549.17-203549.105" + wire $reduce_or$libresoc.v:203549$14657_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -416965,77 +389982,77 @@ module \wrpick_XER_xer_ov attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:200853$14664 + cell $not $not$libresoc.v:203542$14650 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:200853$14664_Y + connect \Y $not$libresoc.v:203542$14650_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:200855$14666 + cell $not $not$libresoc.v:203544$14652 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:200855$14666_Y + connect \Y $not$libresoc.v:203544$14652_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:200857$14668 + cell $not $not$libresoc.v:203546$14654 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \i - connect \Y $not$libresoc.v:200857$14668_Y + connect \Y $not$libresoc.v:203546$14654_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:200859$14670 + cell $not $not$libresoc.v:203548$14656 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:200859$14670_Y + connect \Y $not$libresoc.v:203548$14656_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:200854$14665 + cell $reduce_or $reduce_or$libresoc.v:203543$14651 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:200854$14665_Y + connect \Y $reduce_or$libresoc.v:203543$14651_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:200856$14667 + cell $reduce_or $reduce_or$libresoc.v:203545$14653 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:200856$14667_Y + connect \Y $reduce_or$libresoc.v:203545$14653_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:200858$14669 + cell $reduce_or $reduce_or$libresoc.v:203547$14655 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:200858$14669_Y + connect \Y $reduce_or$libresoc.v:203547$14655_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:200860$14671 + cell $reduce_or $reduce_or$libresoc.v:203549$14657 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:200860$14671_Y - end - connect \$7 $not$libresoc.v:200853$14664_Y - connect \$12 $reduce_or$libresoc.v:200854$14665_Y - connect \$11 $not$libresoc.v:200855$14666_Y - connect \$15 $reduce_or$libresoc.v:200856$14667_Y - connect \$1 $not$libresoc.v:200857$14668_Y - connect \$4 $reduce_or$libresoc.v:200858$14669_Y - connect \$3 $not$libresoc.v:200859$14670_Y - connect \$8 $reduce_or$libresoc.v:200860$14671_Y + connect \Y $reduce_or$libresoc.v:203549$14657_Y + end + connect \$7 $not$libresoc.v:203542$14650_Y + connect \$12 $reduce_or$libresoc.v:203543$14651_Y + connect \$11 $not$libresoc.v:203544$14652_Y + connect \$15 $reduce_or$libresoc.v:203545$14653_Y + connect \$1 $not$libresoc.v:203546$14654_Y + connect \$4 $reduce_or$libresoc.v:203547$14655_Y + connect \$3 $not$libresoc.v:203548$14656_Y + connect \$8 $reduce_or$libresoc.v:203549$14657_Y connect \en_o \$15 connect \o { \t3 \t2 \t1 \t0 } connect \t3 \$11 @@ -417044,27 +390061,27 @@ module \wrpick_XER_xer_ov connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:200872.1-200920.10" +attribute \src "libresoc.v:203561.1-203609.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.wrpick_XER_xer_so" attribute \generator "nMigen" module \wrpick_XER_xer_so - attribute \src "libresoc.v:200905.17-200905.91" - wire $not$libresoc.v:200905$14672_Y - attribute \src "libresoc.v:200907.18-200907.93" - wire $not$libresoc.v:200907$14674_Y - attribute \src "libresoc.v:200909.17-200909.89" - wire width 4 $not$libresoc.v:200909$14676_Y - attribute \src "libresoc.v:200911.17-200911.91" - wire $not$libresoc.v:200911$14678_Y - attribute \src "libresoc.v:200906.18-200906.106" - wire $reduce_or$libresoc.v:200906$14673_Y - attribute \src "libresoc.v:200908.18-200908.90" - wire $reduce_or$libresoc.v:200908$14675_Y - attribute \src "libresoc.v:200910.17-200910.103" - wire $reduce_or$libresoc.v:200910$14677_Y - attribute \src "libresoc.v:200912.17-200912.105" - wire $reduce_or$libresoc.v:200912$14679_Y + attribute \src "libresoc.v:203594.17-203594.91" + wire $not$libresoc.v:203594$14658_Y + attribute \src "libresoc.v:203596.18-203596.93" + wire $not$libresoc.v:203596$14660_Y + attribute \src "libresoc.v:203598.17-203598.89" + wire width 4 $not$libresoc.v:203598$14662_Y + attribute \src "libresoc.v:203600.17-203600.91" + wire $not$libresoc.v:203600$14664_Y + attribute \src "libresoc.v:203595.18-203595.106" + wire $reduce_or$libresoc.v:203595$14659_Y + attribute \src "libresoc.v:203597.18-203597.90" + wire $reduce_or$libresoc.v:203597$14661_Y + attribute \src "libresoc.v:203599.17-203599.103" + wire $reduce_or$libresoc.v:203599$14663_Y + attribute \src "libresoc.v:203601.17-203601.105" + wire $reduce_or$libresoc.v:203601$14665_Y attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" wire width 4 \$1 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" @@ -417098,77 +390115,77 @@ module \wrpick_XER_xer_so attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" wire \t3 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:200905$14672 + cell $not $not$libresoc.v:203594$14658 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$8 - connect \Y $not$libresoc.v:200905$14672_Y + connect \Y $not$libresoc.v:203594$14658_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:200907$14674 + cell $not $not$libresoc.v:203596$14660 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$12 - connect \Y $not$libresoc.v:200907$14674_Y + connect \Y $not$libresoc.v:203596$14660_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - cell $not $not$libresoc.v:200909$14676 + cell $not $not$libresoc.v:203598$14662 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 4 connect \A \i - connect \Y $not$libresoc.v:200909$14676_Y + connect \Y $not$libresoc.v:203598$14662_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $not $not$libresoc.v:200911$14678 + cell $not $not$libresoc.v:203600$14664 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \Y_WIDTH 1 connect \A \$4 - connect \Y $not$libresoc.v:200911$14678_Y + connect \Y $not$libresoc.v:203600$14664_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:200906$14673 + cell $reduce_or $reduce_or$libresoc.v:203595$14659 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A { \i [2:0] \ni [3] } - connect \Y $reduce_or$libresoc.v:200906$14673_Y + connect \Y $reduce_or$libresoc.v:203595$14659_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:74" - cell $reduce_or $reduce_or$libresoc.v:200908$14675 + cell $reduce_or $reduce_or$libresoc.v:203597$14661 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \Y_WIDTH 1 connect \A \o - connect \Y $reduce_or$libresoc.v:200908$14675_Y + connect \Y $reduce_or$libresoc.v:203597$14661_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:200910$14677 + cell $reduce_or $reduce_or$libresoc.v:203599$14663 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \Y_WIDTH 1 connect \A { \i [0] \ni [1] } - connect \Y $reduce_or$libresoc.v:200910$14677_Y + connect \Y $reduce_or$libresoc.v:203599$14663_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:68" - cell $reduce_or $reduce_or$libresoc.v:200912$14679 + cell $reduce_or $reduce_or$libresoc.v:203601$14665 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A { \i [1:0] \ni [2] } - connect \Y $reduce_or$libresoc.v:200912$14679_Y - end - connect \$7 $not$libresoc.v:200905$14672_Y - connect \$12 $reduce_or$libresoc.v:200906$14673_Y - connect \$11 $not$libresoc.v:200907$14674_Y - connect \$15 $reduce_or$libresoc.v:200908$14675_Y - connect \$1 $not$libresoc.v:200909$14676_Y - connect \$4 $reduce_or$libresoc.v:200910$14677_Y - connect \$3 $not$libresoc.v:200911$14678_Y - connect \$8 $reduce_or$libresoc.v:200912$14679_Y + connect \Y $reduce_or$libresoc.v:203601$14665_Y + end + connect \$7 $not$libresoc.v:203594$14658_Y + connect \$12 $reduce_or$libresoc.v:203595$14659_Y + connect \$11 $not$libresoc.v:203596$14660_Y + connect \$15 $reduce_or$libresoc.v:203597$14661_Y + connect \$1 $not$libresoc.v:203598$14662_Y + connect \$4 $reduce_or$libresoc.v:203599$14663_Y + connect \$3 $not$libresoc.v:203600$14664_Y + connect \$8 $reduce_or$libresoc.v:203601$14665_Y connect \en_o \$15 connect \o { \t3 \t2 \t1 \t0 } connect \t3 \$11 @@ -417177,67 +390194,67 @@ module \wrpick_XER_xer_so connect \t0 \i [0] connect \ni \$1 end -attribute \src "libresoc.v:200924.1-201244.10" +attribute \src "libresoc.v:203613.1-203933.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.core.xer" attribute \generator "nMigen" module \xer - attribute \src "libresoc.v:200925.7-200925.20" + attribute \src "libresoc.v:203614.7-203614.20" wire $0\initial[0:0] - attribute \src "libresoc.v:201204.3-201212.6" - wire width 3 $0\ren_delay$11$next[2:0]$14703 - attribute \src "libresoc.v:201102.3-201103.43" - wire width 3 $0\ren_delay$11[2:0]$14692 - attribute \src "libresoc.v:201061.13-201061.34" - wire width 3 $0\ren_delay$11[2:0]$14709 - attribute \src "libresoc.v:201166.3-201174.6" - wire width 3 $0\ren_delay$18$next[2:0]$14695 - attribute \src "libresoc.v:201100.3-201101.43" - wire width 3 $0\ren_delay$18[2:0]$14690 - attribute \src "libresoc.v:201065.13-201065.34" - wire width 3 $0\ren_delay$18[2:0]$14711 - attribute \src "libresoc.v:201185.3-201193.6" - wire width 3 $0\ren_delay$next[2:0]$14699 - attribute \src "libresoc.v:201104.3-201105.35" + attribute \src "libresoc.v:203893.3-203901.6" + wire width 3 $0\ren_delay$11$next[2:0]$14689 + attribute \src "libresoc.v:203791.3-203792.43" + wire width 3 $0\ren_delay$11[2:0]$14678 + attribute \src "libresoc.v:203750.13-203750.34" + wire width 3 $0\ren_delay$11[2:0]$14695 + attribute \src "libresoc.v:203855.3-203863.6" + wire width 3 $0\ren_delay$18$next[2:0]$14681 + attribute \src "libresoc.v:203789.3-203790.43" + wire width 3 $0\ren_delay$18[2:0]$14676 + attribute \src "libresoc.v:203754.13-203754.34" + wire width 3 $0\ren_delay$18[2:0]$14697 + attribute \src "libresoc.v:203874.3-203882.6" + wire width 3 $0\ren_delay$next[2:0]$14685 + attribute \src "libresoc.v:203793.3-203794.35" wire width 3 $0\ren_delay[2:0] - attribute \src "libresoc.v:201194.3-201203.6" + attribute \src "libresoc.v:203883.3-203892.6" wire width 2 $0\src1__data_o[1:0] - attribute \src "libresoc.v:201213.3-201222.6" + attribute \src "libresoc.v:203902.3-203911.6" wire width 2 $0\src2__data_o[1:0] - attribute \src "libresoc.v:201175.3-201184.6" + attribute \src "libresoc.v:203864.3-203873.6" wire width 2 $0\src3__data_o[1:0] - attribute \src "libresoc.v:201204.3-201212.6" - wire width 3 $1\ren_delay$11$next[2:0]$14704 - attribute \src "libresoc.v:201166.3-201174.6" - wire width 3 $1\ren_delay$18$next[2:0]$14696 - attribute \src "libresoc.v:201185.3-201193.6" - wire width 3 $1\ren_delay$next[2:0]$14700 - attribute \src "libresoc.v:201059.13-201059.29" + attribute \src "libresoc.v:203893.3-203901.6" + wire width 3 $1\ren_delay$11$next[2:0]$14690 + attribute \src "libresoc.v:203855.3-203863.6" + wire width 3 $1\ren_delay$18$next[2:0]$14682 + attribute \src "libresoc.v:203874.3-203882.6" + wire width 3 $1\ren_delay$next[2:0]$14686 + attribute \src "libresoc.v:203748.13-203748.29" wire width 3 $1\ren_delay[2:0] - attribute \src "libresoc.v:201194.3-201203.6" + attribute \src "libresoc.v:203883.3-203892.6" wire width 2 $1\src1__data_o[1:0] - attribute \src "libresoc.v:201213.3-201222.6" + attribute \src "libresoc.v:203902.3-203911.6" wire width 2 $1\src2__data_o[1:0] - attribute \src "libresoc.v:201175.3-201184.6" + attribute \src "libresoc.v:203864.3-203873.6" wire width 2 $1\src3__data_o[1:0] - attribute \src "libresoc.v:201091.17-201091.109" - wire width 2 $or$libresoc.v:201091$14680_Y - attribute \src "libresoc.v:201093.18-201093.126" - wire width 2 $or$libresoc.v:201093$14682_Y - attribute \src "libresoc.v:201094.18-201094.111" - wire width 2 $or$libresoc.v:201094$14683_Y - attribute \src "libresoc.v:201096.18-201096.126" - wire width 2 $or$libresoc.v:201096$14685_Y - attribute \src "libresoc.v:201097.18-201097.111" - wire width 2 $or$libresoc.v:201097$14686_Y - attribute \src "libresoc.v:201099.17-201099.125" - wire width 2 $or$libresoc.v:201099$14688_Y - attribute \src "libresoc.v:201092.18-201092.100" - wire $reduce_or$libresoc.v:201092$14681_Y - attribute \src "libresoc.v:201095.18-201095.100" - wire $reduce_or$libresoc.v:201095$14684_Y - attribute \src "libresoc.v:201098.17-201098.95" - wire $reduce_or$libresoc.v:201098$14687_Y + attribute \src "libresoc.v:203780.17-203780.109" + wire width 2 $or$libresoc.v:203780$14666_Y + attribute \src "libresoc.v:203782.18-203782.126" + wire width 2 $or$libresoc.v:203782$14668_Y + attribute \src "libresoc.v:203783.18-203783.111" + wire width 2 $or$libresoc.v:203783$14669_Y + attribute \src "libresoc.v:203785.18-203785.126" + wire width 2 $or$libresoc.v:203785$14671_Y + attribute \src "libresoc.v:203786.18-203786.111" + wire width 2 $or$libresoc.v:203786$14672_Y + attribute \src "libresoc.v:203788.17-203788.125" + wire width 2 $or$libresoc.v:203788$14674_Y + attribute \src "libresoc.v:203781.18-203781.100" + wire $reduce_or$libresoc.v:203781$14667_Y + attribute \src "libresoc.v:203784.18-203784.100" + wire $reduce_or$libresoc.v:203784$14670_Y + attribute \src "libresoc.v:203787.17-203787.95" + wire $reduce_or$libresoc.v:203787$14673_Y attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" wire \$12 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" @@ -417256,9 +390273,9 @@ module \xer wire width 2 \$7 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" wire width 2 \$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 16 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:787" wire input 1 \coresync_rst attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 input 10 \data_i @@ -417274,7 +390291,7 @@ module \xer wire width 6 \full_wr__data_i attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 \full_wr__wen - attribute \src "libresoc.v:200925.7-200925.15" + attribute \src "libresoc.v:203614.7-203614.15" wire \initial attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 2 \reg_0_dest10__data_i @@ -417403,7 +390420,7 @@ module \xer attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:97" wire width 3 input 15 \wen$4 attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:201091$14680 + cell $or $or$libresoc.v:203780$14666 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -417411,10 +390428,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_0_src10__data_o connect \B \$7 - connect \Y $or$libresoc.v:201091$14680_Y + connect \Y $or$libresoc.v:203780$14666_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:201093$14682 + cell $or $or$libresoc.v:203782$14668 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -417422,10 +390439,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_1_src21__data_o connect \B \reg_2_src22__data_o - connect \Y $or$libresoc.v:201093$14682_Y + connect \Y $or$libresoc.v:203782$14668_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:201094$14683 + cell $or $or$libresoc.v:203783$14669 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -417433,10 +390450,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_0_src20__data_o connect \B \$14 - connect \Y $or$libresoc.v:201094$14683_Y + connect \Y $or$libresoc.v:203783$14669_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:201096$14685 + cell $or $or$libresoc.v:203785$14671 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -417444,10 +390461,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_1_src31__data_o connect \B \reg_2_src32__data_o - connect \Y $or$libresoc.v:201096$14685_Y + connect \Y $or$libresoc.v:203785$14671_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:36" - cell $or $or$libresoc.v:201097$14686 + cell $or $or$libresoc.v:203786$14672 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -417455,10 +390472,10 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_0_src30__data_o connect \B \$21 - connect \Y $or$libresoc.v:201097$14686_Y + connect \Y $or$libresoc.v:203786$14672_Y end attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:33" - cell $or $or$libresoc.v:201099$14688 + cell $or $or$libresoc.v:203788$14674 parameter \A_SIGNED 0 parameter \A_WIDTH 2 parameter \B_SIGNED 0 @@ -417466,34 +390483,34 @@ module \xer parameter \Y_WIDTH 2 connect \A \reg_1_src11__data_o connect \B \reg_2_src12__data_o - connect \Y $or$libresoc.v:201099$14688_Y + connect \Y $or$libresoc.v:203788$14674_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:201092$14681 + cell $reduce_or $reduce_or$libresoc.v:203781$14667 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay$11 - connect \Y $reduce_or$libresoc.v:201092$14681_Y + connect \Y $reduce_or$libresoc.v:203781$14667_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:201095$14684 + cell $reduce_or $reduce_or$libresoc.v:203784$14670 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay$18 - connect \Y $reduce_or$libresoc.v:201095$14684_Y + connect \Y $reduce_or$libresoc.v:203784$14670_Y end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_or $reduce_or$libresoc.v:201098$14687 + cell $reduce_or $reduce_or$libresoc.v:203787$14673 parameter \A_SIGNED 0 parameter \A_WIDTH 3 parameter \Y_WIDTH 1 connect \A \ren_delay - connect \Y $reduce_or$libresoc.v:201098$14687_Y + connect \Y $reduce_or$libresoc.v:203787$14673_Y end attribute \module_not_derived 1 - attribute \src "libresoc.v:201106.15-201125.4" + attribute \src "libresoc.v:203795.15-203814.4" cell \reg_0$132 \reg_0 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -417515,7 +390532,7 @@ module \xer connect \w0__wen \reg_0_w0__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:201126.15-201145.4" + attribute \src "libresoc.v:203815.15-203834.4" cell \reg_1$133 \reg_1 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -417537,7 +390554,7 @@ module \xer connect \w1__wen \reg_1_w1__wen end attribute \module_not_derived 1 - attribute \src "libresoc.v:201146.15-201165.4" + attribute \src "libresoc.v:203835.15-203854.4" cell \reg_2$134 \reg_2 connect \coresync_clk \coresync_clk connect \coresync_rst \coresync_rst @@ -417558,67 +390575,67 @@ module \xer connect \w2__data_i \reg_2_w2__data_i connect \w2__wen \reg_2_w2__wen end - attribute \src "libresoc.v:200925.7-200925.20" - process $proc$libresoc.v:200925$14706 + attribute \src "libresoc.v:203614.7-203614.20" + process $proc$libresoc.v:203614$14692 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:201059.13-201059.29" - process $proc$libresoc.v:201059$14707 + attribute \src "libresoc.v:203748.13-203748.29" + process $proc$libresoc.v:203748$14693 assign { } { } assign $1\ren_delay[2:0] 3'000 sync always sync init update \ren_delay $1\ren_delay[2:0] end - attribute \src "libresoc.v:201061.13-201061.34" - process $proc$libresoc.v:201061$14708 + attribute \src "libresoc.v:203750.13-203750.34" + process $proc$libresoc.v:203750$14694 assign { } { } - assign $0\ren_delay$11[2:0]$14709 3'000 + assign $0\ren_delay$11[2:0]$14695 3'000 sync always sync init - update \ren_delay$11 $0\ren_delay$11[2:0]$14709 + update \ren_delay$11 $0\ren_delay$11[2:0]$14695 end - attribute \src "libresoc.v:201065.13-201065.34" - process $proc$libresoc.v:201065$14710 + attribute \src "libresoc.v:203754.13-203754.34" + process $proc$libresoc.v:203754$14696 assign { } { } - assign $0\ren_delay$18[2:0]$14711 3'000 + assign $0\ren_delay$18[2:0]$14697 3'000 sync always sync init - update \ren_delay$18 $0\ren_delay$18[2:0]$14711 + update \ren_delay$18 $0\ren_delay$18[2:0]$14697 end - attribute \src "libresoc.v:201100.3-201101.43" - process $proc$libresoc.v:201100$14689 + attribute \src "libresoc.v:203789.3-203790.43" + process $proc$libresoc.v:203789$14675 assign { } { } - assign $0\ren_delay$18[2:0]$14690 \ren_delay$18$next + assign $0\ren_delay$18[2:0]$14676 \ren_delay$18$next sync posedge \coresync_clk - update \ren_delay$18 $0\ren_delay$18[2:0]$14690 + update \ren_delay$18 $0\ren_delay$18[2:0]$14676 end - attribute \src "libresoc.v:201102.3-201103.43" - process $proc$libresoc.v:201102$14691 + attribute \src "libresoc.v:203791.3-203792.43" + process $proc$libresoc.v:203791$14677 assign { } { } - assign $0\ren_delay$11[2:0]$14692 \ren_delay$11$next + assign $0\ren_delay$11[2:0]$14678 \ren_delay$11$next sync posedge \coresync_clk - update \ren_delay$11 $0\ren_delay$11[2:0]$14692 + update \ren_delay$11 $0\ren_delay$11[2:0]$14678 end - attribute \src "libresoc.v:201104.3-201105.35" - process $proc$libresoc.v:201104$14693 + attribute \src "libresoc.v:203793.3-203794.35" + process $proc$libresoc.v:203793$14679 assign { } { } assign $0\ren_delay[2:0] \ren_delay$next sync posedge \coresync_clk update \ren_delay $0\ren_delay[2:0] end - attribute \src "libresoc.v:201166.3-201174.6" - process $proc$libresoc.v:201166$14694 + attribute \src "libresoc.v:203855.3-203863.6" + process $proc$libresoc.v:203855$14680 assign { } { } assign { } { } - assign $0\ren_delay$18$next[2:0]$14695 $1\ren_delay$18$next[2:0]$14696 - attribute \src "libresoc.v:201167.5-201167.29" + assign $0\ren_delay$18$next[2:0]$14681 $1\ren_delay$18$next[2:0]$14682 + attribute \src "libresoc.v:203856.5-203856.29" switch \initial - attribute \src "libresoc.v:201167.9-201167.17" + attribute \src "libresoc.v:203856.9-203856.17" case 1'1 case end @@ -417627,21 +390644,21 @@ module \xer attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$18$next[2:0]$14696 3'000 + assign $1\ren_delay$18$next[2:0]$14682 3'000 case - assign $1\ren_delay$18$next[2:0]$14696 \src3__ren + assign $1\ren_delay$18$next[2:0]$14682 \src3__ren end sync always - update \ren_delay$18$next $0\ren_delay$18$next[2:0]$14695 + update \ren_delay$18$next $0\ren_delay$18$next[2:0]$14681 end - attribute \src "libresoc.v:201175.3-201184.6" - process $proc$libresoc.v:201175$14697 + attribute \src "libresoc.v:203864.3-203873.6" + process $proc$libresoc.v:203864$14683 assign { } { } assign { } { } assign $0\src3__data_o[1:0] $1\src3__data_o[1:0] - attribute \src "libresoc.v:201176.5-201176.29" + attribute \src "libresoc.v:203865.5-203865.29" switch \initial - attribute \src "libresoc.v:201176.9-201176.17" + attribute \src "libresoc.v:203865.9-203865.17" case 1'1 case end @@ -417657,14 +390674,14 @@ module \xer sync always update \src3__data_o $0\src3__data_o[1:0] end - attribute \src "libresoc.v:201185.3-201193.6" - process $proc$libresoc.v:201185$14698 + attribute \src "libresoc.v:203874.3-203882.6" + process $proc$libresoc.v:203874$14684 assign { } { } assign { } { } - assign $0\ren_delay$next[2:0]$14699 $1\ren_delay$next[2:0]$14700 - attribute \src "libresoc.v:201186.5-201186.29" + assign $0\ren_delay$next[2:0]$14685 $1\ren_delay$next[2:0]$14686 + attribute \src "libresoc.v:203875.5-203875.29" switch \initial - attribute \src "libresoc.v:201186.9-201186.17" + attribute \src "libresoc.v:203875.9-203875.17" case 1'1 case end @@ -417673,21 +390690,21 @@ module \xer attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$next[2:0]$14700 3'000 + assign $1\ren_delay$next[2:0]$14686 3'000 case - assign $1\ren_delay$next[2:0]$14700 \src1__ren + assign $1\ren_delay$next[2:0]$14686 \src1__ren end sync always - update \ren_delay$next $0\ren_delay$next[2:0]$14699 + update \ren_delay$next $0\ren_delay$next[2:0]$14685 end - attribute \src "libresoc.v:201194.3-201203.6" - process $proc$libresoc.v:201194$14701 + attribute \src "libresoc.v:203883.3-203892.6" + process $proc$libresoc.v:203883$14687 assign { } { } assign { } { } assign $0\src1__data_o[1:0] $1\src1__data_o[1:0] - attribute \src "libresoc.v:201195.5-201195.29" + attribute \src "libresoc.v:203884.5-203884.29" switch \initial - attribute \src "libresoc.v:201195.9-201195.17" + attribute \src "libresoc.v:203884.9-203884.17" case 1'1 case end @@ -417703,14 +390720,14 @@ module \xer sync always update \src1__data_o $0\src1__data_o[1:0] end - attribute \src "libresoc.v:201204.3-201212.6" - process $proc$libresoc.v:201204$14702 + attribute \src "libresoc.v:203893.3-203901.6" + process $proc$libresoc.v:203893$14688 assign { } { } assign { } { } - assign $0\ren_delay$11$next[2:0]$14703 $1\ren_delay$11$next[2:0]$14704 - attribute \src "libresoc.v:201205.5-201205.29" + assign $0\ren_delay$11$next[2:0]$14689 $1\ren_delay$11$next[2:0]$14690 + attribute \src "libresoc.v:203894.5-203894.29" switch \initial - attribute \src "libresoc.v:201205.9-201205.17" + attribute \src "libresoc.v:203894.9-203894.17" case 1'1 case end @@ -417719,21 +390736,21 @@ module \xer attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ren_delay$11$next[2:0]$14704 3'000 + assign $1\ren_delay$11$next[2:0]$14690 3'000 case - assign $1\ren_delay$11$next[2:0]$14704 \src2__ren + assign $1\ren_delay$11$next[2:0]$14690 \src2__ren end sync always - update \ren_delay$11$next $0\ren_delay$11$next[2:0]$14703 + update \ren_delay$11$next $0\ren_delay$11$next[2:0]$14689 end - attribute \src "libresoc.v:201213.3-201222.6" - process $proc$libresoc.v:201213$14705 + attribute \src "libresoc.v:203902.3-203911.6" + process $proc$libresoc.v:203902$14691 assign { } { } assign { } { } assign $0\src2__data_o[1:0] $1\src2__data_o[1:0] - attribute \src "libresoc.v:201214.5-201214.29" + attribute \src "libresoc.v:203903.5-203903.29" switch \initial - attribute \src "libresoc.v:201214.9-201214.17" + attribute \src "libresoc.v:203903.9-203903.17" case 1'1 case end @@ -417749,15 +390766,15 @@ module \xer sync always update \src2__data_o $0\src2__data_o[1:0] end - connect \$9 $or$libresoc.v:201091$14680_Y - connect \$12 $reduce_or$libresoc.v:201092$14681_Y - connect \$14 $or$libresoc.v:201093$14682_Y - connect \$16 $or$libresoc.v:201094$14683_Y - connect \$19 $reduce_or$libresoc.v:201095$14684_Y - connect \$21 $or$libresoc.v:201096$14685_Y - connect \$23 $or$libresoc.v:201097$14686_Y - connect \$5 $reduce_or$libresoc.v:201098$14687_Y - connect \$7 $or$libresoc.v:201099$14688_Y + connect \$9 $or$libresoc.v:203780$14666_Y + connect \$12 $reduce_or$libresoc.v:203781$14667_Y + connect \$14 $or$libresoc.v:203782$14668_Y + connect \$16 $or$libresoc.v:203783$14669_Y + connect \$19 $reduce_or$libresoc.v:203784$14670_Y + connect \$21 $or$libresoc.v:203785$14671_Y + connect \$23 $or$libresoc.v:203786$14672_Y + connect \$5 $reduce_or$libresoc.v:203787$14673_Y + connect \$7 $or$libresoc.v:203788$14674_Y connect \full_wr__data_i 6'000000 connect \full_wr__wen 3'000 connect { \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } 3'000 @@ -417780,153 +390797,153 @@ module \xer connect { \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren connect { \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren end -attribute \src "libresoc.v:201248.1-201562.10" +attribute \src "libresoc.v:203937.1-204254.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.xics_icp" attribute \generator "nMigen" module \xics_icp - attribute \src "libresoc.v:201426.3-201454.6" + attribute \src "libresoc.v:204118.3-204146.6" wire width 32 $0\be_out[31:0] - attribute \src "libresoc.v:201477.3-201485.6" - wire $0\core_irq_o$next[0:0]$14747 - attribute \src "libresoc.v:201368.3-201369.37" + attribute \src "libresoc.v:204169.3-204177.6" + wire $0\core_irq_o$next[0:0]$14733 + attribute \src "libresoc.v:204057.3-204058.37" wire $0\core_irq_o[0:0] - attribute \src "libresoc.v:201496.3-201558.6" - wire width 8 $0\cppr$10[7:0]$14751 - attribute \src "libresoc.v:201382.3-201397.6" - wire width 8 $0\cppr$next[7:0]$14730 - attribute \src "libresoc.v:201372.3-201373.25" + attribute \src "libresoc.v:204188.3-204250.6" + wire width 8 $0\cppr$10[7:0]$14737 + attribute \src "libresoc.v:204071.3-204086.6" + wire width 8 $0\cppr$next[7:0]$14716 + attribute \src "libresoc.v:204061.3-204062.25" wire width 8 $0\cppr[7:0] - attribute \src "libresoc.v:201486.3-201495.6" + attribute \src "libresoc.v:204178.3-204187.6" wire width 32 $0\icp_wb__dat_r[31:0] - attribute \src "libresoc.v:201249.7-201249.20" + attribute \src "libresoc.v:203938.7-203938.20" wire $0\initial[0:0] - attribute \src "libresoc.v:201496.3-201558.6" - wire $0\irq$12[0:0]$14752 - attribute \src "libresoc.v:201382.3-201397.6" - wire $0\irq$next[0:0]$14731 - attribute \src "libresoc.v:201376.3-201377.23" + attribute \src "libresoc.v:204188.3-204250.6" + wire $0\irq$12[0:0]$14738 + attribute \src "libresoc.v:204071.3-204086.6" + wire $0\irq$next[0:0]$14717 + attribute \src "libresoc.v:204065.3-204066.23" wire $0\irq[0:0] - attribute \src "libresoc.v:201496.3-201558.6" - wire width 8 $0\mfrr$11[7:0]$14753 - attribute \src "libresoc.v:201382.3-201397.6" - wire width 8 $0\mfrr$next[7:0]$14732 - attribute \src "libresoc.v:201374.3-201375.25" + attribute \src "libresoc.v:204188.3-204250.6" + wire width 8 $0\mfrr$11[7:0]$14739 + attribute \src "libresoc.v:204071.3-204086.6" + wire width 8 $0\mfrr$next[7:0]$14718 + attribute \src "libresoc.v:204063.3-204064.25" wire width 8 $0\mfrr[7:0] - attribute \src "libresoc.v:201465.3-201476.6" + attribute \src "libresoc.v:204157.3-204168.6" wire width 8 $0\min_pri[7:0] - attribute \src "libresoc.v:201455.3-201464.6" + attribute \src "libresoc.v:204147.3-204156.6" wire width 8 $0\pending_priority[7:0] - attribute \src "libresoc.v:201496.3-201558.6" - wire $0\wb_ack$14[0:0]$14754 - attribute \src "libresoc.v:201382.3-201397.6" - wire $0\wb_ack$next[0:0]$14733 - attribute \src "libresoc.v:201380.3-201381.29" + attribute \src "libresoc.v:204188.3-204250.6" + wire $0\wb_ack$14[0:0]$14740 + attribute \src "libresoc.v:204071.3-204086.6" + wire $0\wb_ack$next[0:0]$14719 + attribute \src "libresoc.v:204069.3-204070.29" wire $0\wb_ack[0:0] - attribute \src "libresoc.v:201496.3-201558.6" - wire width 32 $0\wb_rd_data$13[31:0]$14755 - attribute \src "libresoc.v:201382.3-201397.6" - wire width 32 $0\wb_rd_data$next[31:0]$14734 - attribute \src "libresoc.v:201378.3-201379.37" + attribute \src "libresoc.v:204188.3-204250.6" + wire width 32 $0\wb_rd_data$13[31:0]$14741 + attribute \src "libresoc.v:204071.3-204086.6" + wire width 32 $0\wb_rd_data$next[31:0]$14720 + attribute \src "libresoc.v:204067.3-204068.37" wire width 32 $0\wb_rd_data[31:0] - attribute \src "libresoc.v:201398.3-201425.6" + attribute \src "libresoc.v:204087.3-204117.6" wire $0\xirr_accept_rd[0:0] - attribute \src "libresoc.v:201496.3-201558.6" - wire width 24 $0\xisr$9[23:0]$14756 - attribute \src "libresoc.v:201382.3-201397.6" - wire width 24 $0\xisr$next[23:0]$14735 - attribute \src "libresoc.v:201370.3-201371.25" + attribute \src "libresoc.v:204188.3-204250.6" + wire width 24 $0\xisr$9[23:0]$14742 + attribute \src "libresoc.v:204071.3-204086.6" + wire width 24 $0\xisr$next[23:0]$14721 + attribute \src "libresoc.v:204059.3-204060.25" wire width 24 $0\xisr[23:0] - attribute \src "libresoc.v:201426.3-201454.6" + attribute \src "libresoc.v:204118.3-204146.6" wire width 32 $1\be_out[31:0] - attribute \src "libresoc.v:201477.3-201485.6" - wire $1\core_irq_o$next[0:0]$14748 - attribute \src "libresoc.v:201278.7-201278.24" + attribute \src "libresoc.v:204169.3-204177.6" + wire $1\core_irq_o$next[0:0]$14734 + attribute \src "libresoc.v:203967.7-203967.24" wire $1\core_irq_o[0:0] - attribute \src "libresoc.v:201496.3-201558.6" - wire width 8 $1\cppr$10[7:0]$14757 - attribute \src "libresoc.v:201382.3-201397.6" - wire width 8 $1\cppr$next[7:0]$14736 - attribute \src "libresoc.v:201282.13-201282.25" + attribute \src "libresoc.v:204188.3-204250.6" + wire width 8 $1\cppr$10[7:0]$14743 + attribute \src "libresoc.v:204071.3-204086.6" + wire width 8 $1\cppr$next[7:0]$14722 + attribute \src "libresoc.v:203971.13-203971.25" wire width 8 $1\cppr[7:0] - attribute \src "libresoc.v:201486.3-201495.6" + attribute \src "libresoc.v:204178.3-204187.6" wire width 32 $1\icp_wb__dat_r[31:0] - attribute \src "libresoc.v:201496.3-201558.6" - wire $1\irq$12[0:0]$14767 - attribute \src "libresoc.v:201382.3-201397.6" - wire $1\irq$next[0:0]$14737 - attribute \src "libresoc.v:201311.7-201311.17" + attribute \src "libresoc.v:204188.3-204250.6" + wire $1\irq$12[0:0]$14753 + attribute \src "libresoc.v:204071.3-204086.6" + wire $1\irq$next[0:0]$14723 + attribute \src "libresoc.v:204000.7-204000.17" wire $1\irq[0:0] - attribute \src "libresoc.v:201496.3-201558.6" - wire width 8 $1\mfrr$11[7:0]$14758 - attribute \src "libresoc.v:201382.3-201397.6" - wire width 8 $1\mfrr$next[7:0]$14738 - attribute \src "libresoc.v:201319.13-201319.25" + attribute \src "libresoc.v:204188.3-204250.6" + wire width 8 $1\mfrr$11[7:0]$14744 + attribute \src "libresoc.v:204071.3-204086.6" + wire width 8 $1\mfrr$next[7:0]$14724 + attribute \src "libresoc.v:204008.13-204008.25" wire width 8 $1\mfrr[7:0] - attribute \src "libresoc.v:201465.3-201476.6" + attribute \src "libresoc.v:204157.3-204168.6" wire width 8 $1\min_pri[7:0] - attribute \src "libresoc.v:201455.3-201464.6" + attribute \src "libresoc.v:204147.3-204156.6" wire width 8 $1\pending_priority[7:0] - attribute \src "libresoc.v:201496.3-201558.6" - wire $1\wb_ack$14[0:0]$14759 - attribute \src "libresoc.v:201382.3-201397.6" - wire $1\wb_ack$next[0:0]$14739 - attribute \src "libresoc.v:201333.7-201333.20" + attribute \src "libresoc.v:204188.3-204250.6" + wire $1\wb_ack$14[0:0]$14745 + attribute \src "libresoc.v:204071.3-204086.6" + wire $1\wb_ack$next[0:0]$14725 + attribute \src "libresoc.v:204022.7-204022.20" wire $1\wb_ack[0:0] - attribute \src "libresoc.v:201382.3-201397.6" - wire width 32 $1\wb_rd_data$next[31:0]$14740 - attribute \src "libresoc.v:201341.14-201341.32" + attribute \src "libresoc.v:204071.3-204086.6" + wire width 32 $1\wb_rd_data$next[31:0]$14726 + attribute \src "libresoc.v:204030.14-204030.32" wire width 32 $1\wb_rd_data[31:0] - attribute \src "libresoc.v:201398.3-201425.6" + attribute \src "libresoc.v:204087.3-204117.6" wire $1\xirr_accept_rd[0:0] - attribute \src "libresoc.v:201496.3-201558.6" - wire width 24 $1\xisr$9[23:0]$14764 - attribute \src "libresoc.v:201382.3-201397.6" - wire width 24 $1\xisr$next[23:0]$14741 - attribute \src "libresoc.v:201351.14-201351.31" + attribute \src "libresoc.v:204188.3-204250.6" + wire width 24 $1\xisr$9[23:0]$14750 + attribute \src "libresoc.v:204071.3-204086.6" + wire width 24 $1\xisr$next[23:0]$14727 + attribute \src "libresoc.v:204040.14-204040.31" wire width 24 $1\xisr[23:0] - attribute \src "libresoc.v:201426.3-201454.6" + attribute \src "libresoc.v:204118.3-204146.6" wire width 32 $2\be_out[31:0] - attribute \src "libresoc.v:201496.3-201558.6" - wire width 8 $2\cppr$10[7:0]$14760 - attribute \src "libresoc.v:201496.3-201558.6" - wire width 8 $2\mfrr$11[7:0]$14761 - attribute \src "libresoc.v:201398.3-201425.6" + attribute \src "libresoc.v:204188.3-204250.6" + wire width 8 $2\cppr$10[7:0]$14746 + attribute \src "libresoc.v:204188.3-204250.6" + wire width 8 $2\mfrr$11[7:0]$14747 + attribute \src "libresoc.v:204087.3-204117.6" wire $2\xirr_accept_rd[0:0] - attribute \src "libresoc.v:201496.3-201558.6" - wire width 24 $2\xisr$9[23:0]$14765 - attribute \src "libresoc.v:201426.3-201454.6" + attribute \src "libresoc.v:204188.3-204250.6" + wire width 24 $2\xisr$9[23:0]$14751 + attribute \src "libresoc.v:204118.3-204146.6" wire width 32 $3\be_out[31:0] - attribute \src "libresoc.v:201496.3-201558.6" - wire width 8 $3\cppr$10[7:0]$14762 - attribute \src "libresoc.v:201496.3-201558.6" - wire width 8 $3\mfrr$11[7:0]$14763 - attribute \src "libresoc.v:201398.3-201425.6" + attribute \src "libresoc.v:204188.3-204250.6" + wire width 8 $3\cppr$10[7:0]$14748 + attribute \src "libresoc.v:204188.3-204250.6" + wire width 8 $3\mfrr$11[7:0]$14749 + attribute \src "libresoc.v:204087.3-204117.6" wire $3\xirr_accept_rd[0:0] - attribute \src "libresoc.v:201496.3-201558.6" - wire width 8 $4\cppr$10[7:0]$14766 - attribute \src "libresoc.v:201398.3-201425.6" + attribute \src "libresoc.v:204188.3-204250.6" + wire width 8 $4\cppr$10[7:0]$14752 + attribute \src "libresoc.v:204087.3-204117.6" wire $4\xirr_accept_rd[0:0] - attribute \src "libresoc.v:201358.18-201358.116" - wire $and$libresoc.v:201358$14712_Y - attribute \src "libresoc.v:201362.18-201362.116" - wire $and$libresoc.v:201362$14716_Y - attribute \src "libresoc.v:201364.18-201364.116" - wire $and$libresoc.v:201364$14718_Y - attribute \src "libresoc.v:201367.17-201367.109" - wire $and$libresoc.v:201367$14721_Y - attribute \src "libresoc.v:201363.18-201363.110" - wire $eq$libresoc.v:201363$14717_Y - attribute \src "libresoc.v:201360.18-201360.114" - wire $lt$libresoc.v:201360$14714_Y - attribute \src "libresoc.v:201361.18-201361.109" - wire $lt$libresoc.v:201361$14715_Y - attribute \src "libresoc.v:201366.18-201366.114" - wire $lt$libresoc.v:201366$14720_Y - attribute \src "libresoc.v:201359.18-201359.109" - wire $ne$libresoc.v:201359$14713_Y - attribute \src "libresoc.v:201365.18-201365.109" - wire $ne$libresoc.v:201365$14719_Y + attribute \src "libresoc.v:204047.18-204047.116" + wire $and$libresoc.v:204047$14698_Y + attribute \src "libresoc.v:204051.18-204051.116" + wire $and$libresoc.v:204051$14702_Y + attribute \src "libresoc.v:204053.18-204053.116" + wire $and$libresoc.v:204053$14704_Y + attribute \src "libresoc.v:204056.17-204056.109" + wire $and$libresoc.v:204056$14707_Y + attribute \src "libresoc.v:204052.18-204052.110" + wire $eq$libresoc.v:204052$14703_Y + attribute \src "libresoc.v:204049.18-204049.114" + wire $lt$libresoc.v:204049$14700_Y + attribute \src "libresoc.v:204050.18-204050.109" + wire $lt$libresoc.v:204050$14701_Y + attribute \src "libresoc.v:204055.18-204055.114" + wire $lt$libresoc.v:204055$14706_Y + attribute \src "libresoc.v:204048.18-204048.109" + wire $ne$libresoc.v:204048$14699_Y + attribute \src "libresoc.v:204054.18-204054.109" + wire $ne$libresoc.v:204054$14705_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" wire \$15 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" @@ -417951,7 +390968,7 @@ module \xics_icp wire width 32 \be_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:104" wire width 32 \be_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 13 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" wire output 4 \core_irq_o @@ -417985,7 +391002,7 @@ module \xics_icp wire width 8 input 3 \ics_i_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" wire width 4 input 2 \ics_i_src - attribute \src "libresoc.v:201249.7-201249.15" + attribute \src "libresoc.v:203938.7-203938.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" wire \irq @@ -418007,7 +391024,7 @@ module \xics_icp wire width 8 \min_pri attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:106" wire width 8 \pending_priority - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" wire \wb_ack @@ -418036,7 +391053,7 @@ module \xics_icp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" wire width 24 \xisr$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - cell $and $and$libresoc.v:201358$14712 + cell $and $and$libresoc.v:204047$14698 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418044,10 +391061,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__cyc connect \B \icp_wb__stb - connect \Y $and$libresoc.v:201358$14712_Y + connect \Y $and$libresoc.v:204047$14698_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - cell $and $and$libresoc.v:201362$14716 + cell $and $and$libresoc.v:204051$14702 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418055,10 +391072,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__cyc connect \B \icp_wb__stb - connect \Y $and$libresoc.v:201362$14716_Y + connect \Y $and$libresoc.v:204051$14702_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" - cell $and $and$libresoc.v:201364$14718 + cell $and $and$libresoc.v:204053$14704 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418066,10 +391083,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__cyc connect \B \icp_wb__stb - connect \Y $and$libresoc.v:201364$14718_Y + connect \Y $and$libresoc.v:204053$14704_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96" - cell $and $and$libresoc.v:201367$14721 + cell $and $and$libresoc.v:204056$14707 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -418077,10 +391094,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \wb_ack connect \B \icp_wb__cyc - connect \Y $and$libresoc.v:201367$14721_Y + connect \Y $and$libresoc.v:204056$14707_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" - cell $eq $eq$libresoc.v:201363$14717 + cell $eq $eq$libresoc.v:204052$14703 parameter \A_SIGNED 0 parameter \A_WIDTH 4 parameter \B_SIGNED 0 @@ -418088,10 +391105,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \icp_wb__sel connect \B 4'1111 - connect \Y $eq$libresoc.v:201363$14717_Y + connect \Y $eq$libresoc.v:204052$14703_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" - cell $lt $lt$libresoc.v:201360$14714 + cell $lt $lt$libresoc.v:204049$14700 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -418099,10 +391116,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \mfrr connect \B \pending_priority - connect \Y $lt$libresoc.v:201360$14714_Y + connect \Y $lt$libresoc.v:204049$14700_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" - cell $lt $lt$libresoc.v:201361$14715 + cell $lt $lt$libresoc.v:204050$14701 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -418110,10 +391127,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \min_pri connect \B \cppr$10 - connect \Y $lt$libresoc.v:201361$14715_Y + connect \Y $lt$libresoc.v:204050$14701_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" - cell $lt $lt$libresoc.v:201366$14720 + cell $lt $lt$libresoc.v:204055$14706 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -418121,10 +391138,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \mfrr connect \B \pending_priority - connect \Y $lt$libresoc.v:201366$14720_Y + connect \Y $lt$libresoc.v:204055$14706_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" - cell $ne $ne$libresoc.v:201359$14713 + cell $ne $ne$libresoc.v:204048$14699 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -418132,10 +391149,10 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \ics_i_pri connect \B 8'11111111 - connect \Y $ne$libresoc.v:201359$14713_Y + connect \Y $ne$libresoc.v:204048$14699_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" - cell $ne $ne$libresoc.v:201365$14719 + cell $ne $ne$libresoc.v:204054$14705 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -418143,123 +391160,123 @@ module \xics_icp parameter \Y_WIDTH 1 connect \A \ics_i_pri connect \B 8'11111111 - connect \Y $ne$libresoc.v:201365$14719_Y + connect \Y $ne$libresoc.v:204054$14705_Y end - attribute \src "libresoc.v:201249.7-201249.20" - process $proc$libresoc.v:201249$14768 + attribute \src "libresoc.v:203938.7-203938.20" + process $proc$libresoc.v:203938$14754 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:201278.7-201278.24" - process $proc$libresoc.v:201278$14769 + attribute \src "libresoc.v:203967.7-203967.24" + process $proc$libresoc.v:203967$14755 assign { } { } assign $1\core_irq_o[0:0] 1'0 sync always sync init update \core_irq_o $1\core_irq_o[0:0] end - attribute \src "libresoc.v:201282.13-201282.25" - process $proc$libresoc.v:201282$14770 + attribute \src "libresoc.v:203971.13-203971.25" + process $proc$libresoc.v:203971$14756 assign { } { } assign $1\cppr[7:0] 8'00000000 sync always sync init update \cppr $1\cppr[7:0] end - attribute \src "libresoc.v:201311.7-201311.17" - process $proc$libresoc.v:201311$14771 + attribute \src "libresoc.v:204000.7-204000.17" + process $proc$libresoc.v:204000$14757 assign { } { } assign $1\irq[0:0] 1'0 sync always sync init update \irq $1\irq[0:0] end - attribute \src "libresoc.v:201319.13-201319.25" - process $proc$libresoc.v:201319$14772 + attribute \src "libresoc.v:204008.13-204008.25" + process $proc$libresoc.v:204008$14758 assign { } { } assign $1\mfrr[7:0] 8'11111111 sync always sync init update \mfrr $1\mfrr[7:0] end - attribute \src "libresoc.v:201333.7-201333.20" - process $proc$libresoc.v:201333$14773 + attribute \src "libresoc.v:204022.7-204022.20" + process $proc$libresoc.v:204022$14759 assign { } { } assign $1\wb_ack[0:0] 1'0 sync always sync init update \wb_ack $1\wb_ack[0:0] end - attribute \src "libresoc.v:201341.14-201341.32" - process $proc$libresoc.v:201341$14774 + attribute \src "libresoc.v:204030.14-204030.32" + process $proc$libresoc.v:204030$14760 assign { } { } assign $1\wb_rd_data[31:0] 0 sync always sync init update \wb_rd_data $1\wb_rd_data[31:0] end - attribute \src "libresoc.v:201351.14-201351.31" - process $proc$libresoc.v:201351$14775 + attribute \src "libresoc.v:204040.14-204040.31" + process $proc$libresoc.v:204040$14761 assign { } { } assign $1\xisr[23:0] 24'000000000000000000000000 sync always sync init update \xisr $1\xisr[23:0] end - attribute \src "libresoc.v:201368.3-201369.37" - process $proc$libresoc.v:201368$14722 + attribute \src "libresoc.v:204057.3-204058.37" + process $proc$libresoc.v:204057$14708 assign { } { } assign $0\core_irq_o[0:0] \core_irq_o$next sync posedge \clk update \core_irq_o $0\core_irq_o[0:0] end - attribute \src "libresoc.v:201370.3-201371.25" - process $proc$libresoc.v:201370$14723 + attribute \src "libresoc.v:204059.3-204060.25" + process $proc$libresoc.v:204059$14709 assign { } { } assign $0\xisr[23:0] \xisr$next sync posedge \clk update \xisr $0\xisr[23:0] end - attribute \src "libresoc.v:201372.3-201373.25" - process $proc$libresoc.v:201372$14724 + attribute \src "libresoc.v:204061.3-204062.25" + process $proc$libresoc.v:204061$14710 assign { } { } assign $0\cppr[7:0] \cppr$next sync posedge \clk update \cppr $0\cppr[7:0] end - attribute \src "libresoc.v:201374.3-201375.25" - process $proc$libresoc.v:201374$14725 + attribute \src "libresoc.v:204063.3-204064.25" + process $proc$libresoc.v:204063$14711 assign { } { } assign $0\mfrr[7:0] \mfrr$next sync posedge \clk update \mfrr $0\mfrr[7:0] end - attribute \src "libresoc.v:201376.3-201377.23" - process $proc$libresoc.v:201376$14726 + attribute \src "libresoc.v:204065.3-204066.23" + process $proc$libresoc.v:204065$14712 assign { } { } assign $0\irq[0:0] \irq$next sync posedge \clk update \irq $0\irq[0:0] end - attribute \src "libresoc.v:201378.3-201379.37" - process $proc$libresoc.v:201378$14727 + attribute \src "libresoc.v:204067.3-204068.37" + process $proc$libresoc.v:204067$14713 assign { } { } assign $0\wb_rd_data[31:0] \wb_rd_data$next sync posedge \clk update \wb_rd_data $0\wb_rd_data[31:0] end - attribute \src "libresoc.v:201380.3-201381.29" - process $proc$libresoc.v:201380$14728 + attribute \src "libresoc.v:204069.3-204070.29" + process $proc$libresoc.v:204069$14714 assign { } { } assign $0\wb_ack[0:0] \wb_ack$next sync posedge \clk update \wb_ack $0\wb_ack[0:0] end - attribute \src "libresoc.v:201382.3-201397.6" - process $proc$libresoc.v:201382$14729 + attribute \src "libresoc.v:204071.3-204086.6" + process $proc$libresoc.v:204071$14715 assign { } { } assign { } { } assign { } { } @@ -418267,15 +391284,15 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $0\cppr$next[7:0]$14730 $1\cppr$next[7:0]$14736 - assign $0\irq$next[0:0]$14731 $1\irq$next[0:0]$14737 - assign $0\mfrr$next[7:0]$14732 $1\mfrr$next[7:0]$14738 - assign $0\wb_ack$next[0:0]$14733 $1\wb_ack$next[0:0]$14739 - assign $0\wb_rd_data$next[31:0]$14734 $1\wb_rd_data$next[31:0]$14740 - assign $0\xisr$next[23:0]$14735 $1\xisr$next[23:0]$14741 - attribute \src "libresoc.v:201383.5-201383.29" + assign $0\cppr$next[7:0]$14716 $1\cppr$next[7:0]$14722 + assign $0\irq$next[0:0]$14717 $1\irq$next[0:0]$14723 + assign $0\mfrr$next[7:0]$14718 $1\mfrr$next[7:0]$14724 + assign $0\wb_ack$next[0:0]$14719 $1\wb_ack$next[0:0]$14725 + assign $0\wb_rd_data$next[31:0]$14720 $1\wb_rd_data$next[31:0]$14726 + assign $0\xisr$next[23:0]$14721 $1\xisr$next[23:0]$14727 + attribute \src "libresoc.v:204072.5-204072.29" switch \initial - attribute \src "libresoc.v:201383.9-201383.17" + attribute \src "libresoc.v:204072.9-204072.17" case 1'1 case end @@ -418289,36 +391306,36 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $1\xisr$next[23:0]$14741 24'000000000000000000000000 - assign $1\cppr$next[7:0]$14736 8'00000000 - assign $1\mfrr$next[7:0]$14738 8'11111111 - assign $1\irq$next[0:0]$14737 1'0 - assign $1\wb_rd_data$next[31:0]$14740 0 - assign $1\wb_ack$next[0:0]$14739 1'0 + assign $1\xisr$next[23:0]$14727 24'000000000000000000000000 + assign $1\cppr$next[7:0]$14722 8'00000000 + assign $1\mfrr$next[7:0]$14724 8'11111111 + assign $1\irq$next[0:0]$14723 1'0 + assign $1\wb_rd_data$next[31:0]$14726 0 + assign $1\wb_ack$next[0:0]$14725 1'0 case - assign $1\cppr$next[7:0]$14736 \cppr$2 - assign $1\irq$next[0:0]$14737 \irq$4 - assign $1\mfrr$next[7:0]$14738 \mfrr$3 - assign $1\wb_ack$next[0:0]$14739 \wb_ack$6 - assign $1\wb_rd_data$next[31:0]$14740 \wb_rd_data$5 - assign $1\xisr$next[23:0]$14741 \xisr$1 + assign $1\cppr$next[7:0]$14722 \cppr$2 + assign $1\irq$next[0:0]$14723 \irq$4 + assign $1\mfrr$next[7:0]$14724 \mfrr$3 + assign $1\wb_ack$next[0:0]$14725 \wb_ack$6 + assign $1\wb_rd_data$next[31:0]$14726 \wb_rd_data$5 + assign $1\xisr$next[23:0]$14727 \xisr$1 end sync always - update \cppr$next $0\cppr$next[7:0]$14730 - update \irq$next $0\irq$next[0:0]$14731 - update \mfrr$next $0\mfrr$next[7:0]$14732 - update \wb_ack$next $0\wb_ack$next[0:0]$14733 - update \wb_rd_data$next $0\wb_rd_data$next[31:0]$14734 - update \xisr$next $0\xisr$next[23:0]$14735 + update \cppr$next $0\cppr$next[7:0]$14716 + update \irq$next $0\irq$next[0:0]$14717 + update \mfrr$next $0\mfrr$next[7:0]$14718 + update \wb_ack$next $0\wb_ack$next[0:0]$14719 + update \wb_rd_data$next $0\wb_rd_data$next[31:0]$14720 + update \xisr$next $0\xisr$next[23:0]$14721 end - attribute \src "libresoc.v:201398.3-201425.6" - process $proc$libresoc.v:201398$14742 + attribute \src "libresoc.v:204087.3-204117.6" + process $proc$libresoc.v:204087$14728 assign { } { } assign { } { } assign $0\xirr_accept_rd[0:0] $1\xirr_accept_rd[0:0] - attribute \src "libresoc.v:201399.5-201399.29" + attribute \src "libresoc.v:204088.5-204088.29" switch \initial - attribute \src "libresoc.v:201399.9-201399.17" + attribute \src "libresoc.v:204088.9-204088.17" case 1'1 case end @@ -418340,6 +391357,9 @@ module \xics_icp attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:155" switch \icp_wb__adr [5:0] attribute \src "libresoc.v:0.0-0.0" + case 6'000000 + assign $3\xirr_accept_rd[0:0] 1'0 + attribute \src "libresoc.v:0.0-0.0" case 6'000001 assign { } { } assign $3\xirr_accept_rd[0:0] $4\xirr_accept_rd[0:0] @@ -418362,14 +391382,14 @@ module \xics_icp sync always update \xirr_accept_rd $0\xirr_accept_rd[0:0] end - attribute \src "libresoc.v:201426.3-201454.6" - process $proc$libresoc.v:201426$14743 + attribute \src "libresoc.v:204118.3-204146.6" + process $proc$libresoc.v:204118$14729 assign { } { } assign { } { } assign $0\be_out[31:0] $1\be_out[31:0] - attribute \src "libresoc.v:201427.5-201427.29" + attribute \src "libresoc.v:204119.5-204119.29" switch \initial - attribute \src "libresoc.v:201427.9-201427.17" + attribute \src "libresoc.v:204119.9-204119.17" case 1'1 case end @@ -418412,14 +391432,14 @@ module \xics_icp sync always update \be_out $0\be_out[31:0] end - attribute \src "libresoc.v:201455.3-201464.6" - process $proc$libresoc.v:201455$14744 + attribute \src "libresoc.v:204147.3-204156.6" + process $proc$libresoc.v:204147$14730 assign { } { } assign { } { } assign $0\pending_priority[7:0] $1\pending_priority[7:0] - attribute \src "libresoc.v:201456.5-201456.29" + attribute \src "libresoc.v:204148.5-204148.29" switch \initial - attribute \src "libresoc.v:201456.9-201456.17" + attribute \src "libresoc.v:204148.9-204148.17" case 1'1 case end @@ -418435,13 +391455,13 @@ module \xics_icp sync always update \pending_priority $0\pending_priority[7:0] end - attribute \src "libresoc.v:201465.3-201476.6" - process $proc$libresoc.v:201465$14745 + attribute \src "libresoc.v:204157.3-204168.6" + process $proc$libresoc.v:204157$14731 assign { } { } assign $0\min_pri[7:0] $1\min_pri[7:0] - attribute \src "libresoc.v:201466.5-201466.29" + attribute \src "libresoc.v:204158.5-204158.29" switch \initial - attribute \src "libresoc.v:201466.9-201466.17" + attribute \src "libresoc.v:204158.9-204158.17" case 1'1 case end @@ -418459,14 +391479,14 @@ module \xics_icp sync always update \min_pri $0\min_pri[7:0] end - attribute \src "libresoc.v:201477.3-201485.6" - process $proc$libresoc.v:201477$14746 + attribute \src "libresoc.v:204169.3-204177.6" + process $proc$libresoc.v:204169$14732 assign { } { } assign { } { } - assign $0\core_irq_o$next[0:0]$14747 $1\core_irq_o$next[0:0]$14748 - attribute \src "libresoc.v:201478.5-201478.29" + assign $0\core_irq_o$next[0:0]$14733 $1\core_irq_o$next[0:0]$14734 + attribute \src "libresoc.v:204170.5-204170.29" switch \initial - attribute \src "libresoc.v:201478.9-201478.17" + attribute \src "libresoc.v:204170.9-204170.17" case 1'1 case end @@ -418475,21 +391495,21 @@ module \xics_icp attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\core_irq_o$next[0:0]$14748 1'0 + assign $1\core_irq_o$next[0:0]$14734 1'0 case - assign $1\core_irq_o$next[0:0]$14748 \irq + assign $1\core_irq_o$next[0:0]$14734 \irq end sync always - update \core_irq_o$next $0\core_irq_o$next[0:0]$14747 + update \core_irq_o$next $0\core_irq_o$next[0:0]$14733 end - attribute \src "libresoc.v:201486.3-201495.6" - process $proc$libresoc.v:201486$14749 + attribute \src "libresoc.v:204178.3-204187.6" + process $proc$libresoc.v:204178$14735 assign { } { } assign { } { } assign $0\icp_wb__dat_r[31:0] $1\icp_wb__dat_r[31:0] - attribute \src "libresoc.v:201487.5-201487.29" + attribute \src "libresoc.v:204179.5-204179.29" switch \initial - attribute \src "libresoc.v:201487.9-201487.17" + attribute \src "libresoc.v:204179.9-204179.17" case 1'1 case end @@ -418505,8 +391525,8 @@ module \xics_icp sync always update \icp_wb__dat_r $0\icp_wb__dat_r[31:0] end - attribute \src "libresoc.v:201496.3-201558.6" - process $proc$libresoc.v:201496$14750 + attribute \src "libresoc.v:204188.3-204250.6" + process $proc$libresoc.v:204188$14736 assign { } { } assign { } { } assign { } { } @@ -418516,18 +391536,18 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $0\mfrr$11[7:0]$14753 $1\mfrr$11[7:0]$14758 - assign $0\wb_ack$14[0:0]$14754 $1\wb_ack$14[0:0]$14759 + assign $0\mfrr$11[7:0]$14739 $1\mfrr$11[7:0]$14744 + assign $0\wb_ack$14[0:0]$14740 $1\wb_ack$14[0:0]$14745 assign { } { } assign { } { } assign { } { } - assign $0\xisr$9[23:0]$14756 $2\xisr$9[23:0]$14765 - assign $0\cppr$10[7:0]$14751 $4\cppr$10[7:0]$14766 - assign $0\wb_rd_data$13[31:0]$14755 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } - assign $0\irq$12[0:0]$14752 $1\irq$12[0:0]$14767 - attribute \src "libresoc.v:201497.5-201497.29" + assign $0\xisr$9[23:0]$14742 $2\xisr$9[23:0]$14751 + assign $0\cppr$10[7:0]$14737 $4\cppr$10[7:0]$14752 + assign $0\wb_rd_data$13[31:0]$14741 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } + assign $0\irq$12[0:0]$14738 $1\irq$12[0:0]$14753 + attribute \src "libresoc.v:204189.5-204189.29" switch \initial - attribute \src "libresoc.v:201497.9-201497.17" + attribute \src "libresoc.v:204189.9-204189.17" case 1'1 case end @@ -418538,712 +391558,712 @@ module \xics_icp assign { } { } assign { } { } assign { } { } - assign $1\wb_ack$14[0:0]$14759 1'1 - assign $1\cppr$10[7:0]$14757 $2\cppr$10[7:0]$14760 - assign $1\mfrr$11[7:0]$14758 $2\mfrr$11[7:0]$14761 + assign $1\wb_ack$14[0:0]$14745 1'1 + assign $1\cppr$10[7:0]$14743 $2\cppr$10[7:0]$14746 + assign $1\mfrr$11[7:0]$14744 $2\mfrr$11[7:0]$14747 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" switch \icp_wb__we attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } assign { } { } - assign $2\cppr$10[7:0]$14760 $3\cppr$10[7:0]$14762 - assign $2\mfrr$11[7:0]$14761 $3\mfrr$11[7:0]$14763 + assign $2\cppr$10[7:0]$14746 $3\cppr$10[7:0]$14748 + assign $2\mfrr$11[7:0]$14747 $3\mfrr$11[7:0]$14749 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:121" switch \icp_wb__adr [5:0] attribute \src "libresoc.v:0.0-0.0" case 6'000000 assign { } { } - assign $3\mfrr$11[7:0]$14763 \mfrr - assign $3\cppr$10[7:0]$14762 \be_in [31:24] + assign $3\mfrr$11[7:0]$14749 \mfrr + assign $3\cppr$10[7:0]$14748 \be_in [31:24] attribute \src "libresoc.v:0.0-0.0" case 6'000001 assign { } { } - assign $3\mfrr$11[7:0]$14763 \mfrr - assign $3\cppr$10[7:0]$14762 \be_in [31:24] + assign $3\mfrr$11[7:0]$14749 \mfrr + assign $3\cppr$10[7:0]$14748 \be_in [31:24] attribute \src "libresoc.v:0.0-0.0" case 6'000011 - assign $3\cppr$10[7:0]$14762 \cppr + assign $3\cppr$10[7:0]$14748 \cppr assign { } { } - assign $3\mfrr$11[7:0]$14763 \be_in [31:24] + assign $3\mfrr$11[7:0]$14749 \be_in [31:24] case - assign $3\cppr$10[7:0]$14762 \cppr - assign $3\mfrr$11[7:0]$14763 \mfrr + assign $3\cppr$10[7:0]$14748 \cppr + assign $3\mfrr$11[7:0]$14749 \mfrr end case - assign $2\cppr$10[7:0]$14760 \cppr - assign $2\mfrr$11[7:0]$14761 \mfrr + assign $2\cppr$10[7:0]$14746 \cppr + assign $2\mfrr$11[7:0]$14747 \mfrr end case - assign $1\cppr$10[7:0]$14757 \cppr - assign $1\mfrr$11[7:0]$14758 \mfrr - assign $1\wb_ack$14[0:0]$14759 1'0 + assign $1\cppr$10[7:0]$14743 \cppr + assign $1\mfrr$11[7:0]$14744 \mfrr + assign $1\wb_ack$14[0:0]$14745 1'0 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" switch \$17 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\xisr$9[23:0]$14764 { 20'00000000000000000001 \ics_i_src } + assign $1\xisr$9[23:0]$14750 { 20'00000000000000000001 \ics_i_src } case - assign $1\xisr$9[23:0]$14764 24'000000000000000000000000 + assign $1\xisr$9[23:0]$14750 24'000000000000000000000000 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" switch \$19 attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $2\xisr$9[23:0]$14765 24'000000000000000000000010 + assign $2\xisr$9[23:0]$14751 24'000000000000000000000010 case - assign $2\xisr$9[23:0]$14765 $1\xisr$9[23:0]$14764 + assign $2\xisr$9[23:0]$14751 $1\xisr$9[23:0]$14750 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:185" switch \xirr_accept_rd attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $4\cppr$10[7:0]$14766 \min_pri + assign $4\cppr$10[7:0]$14752 \min_pri case - assign $4\cppr$10[7:0]$14766 $1\cppr$10[7:0]$14757 + assign $4\cppr$10[7:0]$14752 $1\cppr$10[7:0]$14743 end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" switch { \irq \$21 } attribute \src "libresoc.v:0.0-0.0" case 2'-1 assign { } { } - assign $1\irq$12[0:0]$14767 1'1 + assign $1\irq$12[0:0]$14753 1'1 case - assign $1\irq$12[0:0]$14767 1'0 + assign $1\irq$12[0:0]$14753 1'0 end sync always - update \cppr$10 $0\cppr$10[7:0]$14751 - update \irq$12 $0\irq$12[0:0]$14752 - update \mfrr$11 $0\mfrr$11[7:0]$14753 - update \wb_ack$14 $0\wb_ack$14[0:0]$14754 - update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$14755 - update \xisr$9 $0\xisr$9[23:0]$14756 + update \cppr$10 $0\cppr$10[7:0]$14737 + update \irq$12 $0\irq$12[0:0]$14738 + update \mfrr$11 $0\mfrr$11[7:0]$14739 + update \wb_ack$14 $0\wb_ack$14[0:0]$14740 + update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$14741 + update \xisr$9 $0\xisr$9[23:0]$14742 end - connect \$15 $and$libresoc.v:201358$14712_Y - connect \$17 $ne$libresoc.v:201359$14713_Y - connect \$19 $lt$libresoc.v:201360$14714_Y - connect \$21 $lt$libresoc.v:201361$14715_Y - connect \$23 $and$libresoc.v:201362$14716_Y - connect \$25 $eq$libresoc.v:201363$14717_Y - connect \$27 $and$libresoc.v:201364$14718_Y - connect \$29 $ne$libresoc.v:201365$14719_Y - connect \$31 $lt$libresoc.v:201366$14720_Y - connect \$7 $and$libresoc.v:201367$14721_Y + connect \$15 $and$libresoc.v:204047$14698_Y + connect \$17 $ne$libresoc.v:204048$14699_Y + connect \$19 $lt$libresoc.v:204049$14700_Y + connect \$21 $lt$libresoc.v:204050$14701_Y + connect \$23 $and$libresoc.v:204051$14702_Y + connect \$25 $eq$libresoc.v:204052$14703_Y + connect \$27 $and$libresoc.v:204053$14704_Y + connect \$29 $ne$libresoc.v:204054$14705_Y + connect \$31 $lt$libresoc.v:204055$14706_Y + connect \$7 $and$libresoc.v:204056$14707_Y connect { \wb_ack$6 \wb_rd_data$5 \irq$4 \mfrr$3 \cppr$2 \xisr$1 } { \wb_ack$14 \wb_rd_data$13 \irq$12 \mfrr$11 \cppr$10 \xisr$9 } connect \be_in { \icp_wb__dat_w [7:0] \icp_wb__dat_w [15:8] \icp_wb__dat_w [23:16] \icp_wb__dat_w [31:24] } connect \icp_wb__ack \$7 end -attribute \src "libresoc.v:201566.1-202615.10" +attribute \src "libresoc.v:204258.1-205307.10" attribute \cells_not_processed 1 attribute \nmigen.hierarchy "test_issuer.ti.xics_ics" attribute \generator "nMigen" module \xics_ics - attribute \src "libresoc.v:202496.3-202545.6" + attribute \src "libresoc.v:205188.3-205237.6" wire width 32 $0\be_out[31:0] - attribute \src "libresoc.v:202207.3-202216.6" + attribute \src "libresoc.v:204899.3-204908.6" wire width 4 $0\cur_idx0[3:0] - attribute \src "libresoc.v:202416.3-202425.6" + attribute \src "libresoc.v:205108.3-205117.6" wire width 4 $0\cur_idx10[3:0] - attribute \src "libresoc.v:202436.3-202445.6" + attribute \src "libresoc.v:205128.3-205137.6" wire width 4 $0\cur_idx11[3:0] - attribute \src "libresoc.v:202456.3-202465.6" + attribute \src "libresoc.v:205148.3-205157.6" wire width 4 $0\cur_idx12[3:0] - attribute \src "libresoc.v:202476.3-202485.6" + attribute \src "libresoc.v:205168.3-205177.6" wire width 4 $0\cur_idx13[3:0] - attribute \src "libresoc.v:202546.3-202555.6" + attribute \src "libresoc.v:205238.3-205247.6" wire width 4 $0\cur_idx14[3:0] - attribute \src "libresoc.v:202566.3-202575.6" + attribute \src "libresoc.v:205258.3-205267.6" wire width 4 $0\cur_idx15[3:0] - attribute \src "libresoc.v:202227.3-202236.6" + attribute \src "libresoc.v:204919.3-204928.6" wire width 4 $0\cur_idx1[3:0] - attribute \src "libresoc.v:202247.3-202256.6" + attribute \src "libresoc.v:204939.3-204948.6" wire width 4 $0\cur_idx2[3:0] - attribute \src "libresoc.v:202267.3-202276.6" + attribute \src "libresoc.v:204959.3-204968.6" wire width 4 $0\cur_idx3[3:0] - attribute \src "libresoc.v:202296.3-202305.6" + attribute \src "libresoc.v:204988.3-204997.6" wire width 4 $0\cur_idx4[3:0] - attribute \src "libresoc.v:202316.3-202325.6" + attribute \src "libresoc.v:205008.3-205017.6" wire width 4 $0\cur_idx5[3:0] - attribute \src "libresoc.v:202336.3-202345.6" + attribute \src "libresoc.v:205028.3-205037.6" wire width 4 $0\cur_idx6[3:0] - attribute \src "libresoc.v:202356.3-202365.6" + attribute \src "libresoc.v:205048.3-205057.6" wire width 4 $0\cur_idx7[3:0] - attribute \src "libresoc.v:202376.3-202385.6" + attribute \src "libresoc.v:205068.3-205077.6" wire width 4 $0\cur_idx8[3:0] - attribute \src "libresoc.v:202396.3-202405.6" + attribute \src "libresoc.v:205088.3-205097.6" wire width 4 $0\cur_idx9[3:0] - attribute \src "libresoc.v:202197.3-202206.6" + attribute \src "libresoc.v:204889.3-204898.6" wire width 8 $0\cur_pri0[7:0] - attribute \src "libresoc.v:202406.3-202415.6" + attribute \src "libresoc.v:205098.3-205107.6" wire width 8 $0\cur_pri10[7:0] - attribute \src "libresoc.v:202426.3-202435.6" + attribute \src "libresoc.v:205118.3-205127.6" wire width 8 $0\cur_pri11[7:0] - attribute \src "libresoc.v:202446.3-202455.6" + attribute \src "libresoc.v:205138.3-205147.6" wire width 8 $0\cur_pri12[7:0] - attribute \src "libresoc.v:202466.3-202475.6" + attribute \src "libresoc.v:205158.3-205167.6" wire width 8 $0\cur_pri13[7:0] - attribute \src "libresoc.v:202486.3-202495.6" + attribute \src "libresoc.v:205178.3-205187.6" wire width 8 $0\cur_pri14[7:0] - attribute \src "libresoc.v:202556.3-202565.6" + attribute \src "libresoc.v:205248.3-205257.6" wire width 8 $0\cur_pri15[7:0] - attribute \src "libresoc.v:202217.3-202226.6" + attribute \src "libresoc.v:204909.3-204918.6" wire width 8 $0\cur_pri1[7:0] - attribute \src "libresoc.v:202237.3-202246.6" + attribute \src "libresoc.v:204929.3-204938.6" wire width 8 $0\cur_pri2[7:0] - attribute \src "libresoc.v:202257.3-202266.6" + attribute \src "libresoc.v:204949.3-204958.6" wire width 8 $0\cur_pri3[7:0] - attribute \src "libresoc.v:202277.3-202286.6" + attribute \src "libresoc.v:204969.3-204978.6" wire width 8 $0\cur_pri4[7:0] - attribute \src "libresoc.v:202306.3-202315.6" + attribute \src "libresoc.v:204998.3-205007.6" wire width 8 $0\cur_pri5[7:0] - attribute \src "libresoc.v:202326.3-202335.6" + attribute \src "libresoc.v:205018.3-205027.6" wire width 8 $0\cur_pri6[7:0] - attribute \src "libresoc.v:202346.3-202355.6" + attribute \src "libresoc.v:205038.3-205047.6" wire width 8 $0\cur_pri7[7:0] - attribute \src "libresoc.v:202366.3-202375.6" + attribute \src "libresoc.v:205058.3-205067.6" wire width 8 $0\cur_pri8[7:0] - attribute \src "libresoc.v:202386.3-202395.6" + attribute \src "libresoc.v:205078.3-205087.6" wire width 8 $0\cur_pri9[7:0] - attribute \src "libresoc.v:202576.3-202585.6" + attribute \src "libresoc.v:205268.3-205277.6" wire $0\ibit[0:0] - attribute \src "libresoc.v:202071.3-202072.25" + attribute \src "libresoc.v:204763.3-204764.25" wire width 8 $0\icp_o_pri[7:0] - attribute \src "libresoc.v:202069.3-202070.28" + attribute \src "libresoc.v:204761.3-204762.28" wire width 4 $0\icp_o_src[3:0] - attribute \src "libresoc.v:202595.3-202603.6" - wire $0\ics_wb__ack$next[0:0]$15022 - attribute \src "libresoc.v:202105.3-202106.39" + attribute \src "libresoc.v:205287.3-205295.6" + wire $0\ics_wb__ack$next[0:0]$15008 + attribute \src "libresoc.v:204797.3-204798.39" wire $0\ics_wb__ack[0:0] - attribute \src "libresoc.v:202586.3-202594.6" - wire width 32 $0\ics_wb__dat_r$next[31:0]$15019 - attribute \src "libresoc.v:202107.3-202108.43" + attribute \src "libresoc.v:205278.3-205286.6" + wire width 32 $0\ics_wb__dat_r$next[31:0]$15005 + attribute \src "libresoc.v:204799.3-204800.43" wire width 32 $0\ics_wb__dat_r[31:0] - attribute \src "libresoc.v:201567.7-201567.20" + attribute \src "libresoc.v:204259.7-204259.20" wire $0\initial[0:0] - attribute \src "libresoc.v:202287.3-202295.6" - wire width 16 $0\int_level_l$next[15:0]$14991 - attribute \src "libresoc.v:202109.3-202110.39" + attribute \src "libresoc.v:204979.3-204987.6" + wire width 16 $0\int_level_l$next[15:0]$14977 + attribute \src "libresoc.v:204801.3-204802.39" wire width 16 $0\int_level_l[15:0] - attribute \src "libresoc.v:202111.3-202196.6" - wire width 8 $0\xive0_pri$next[7:0]$14901 - attribute \src "libresoc.v:202073.3-202074.35" + attribute \src "libresoc.v:204803.3-204888.6" + wire width 8 $0\xive0_pri$next[7:0]$14887 + attribute \src "libresoc.v:204765.3-204766.35" wire width 8 $0\xive0_pri[7:0] - attribute \src "libresoc.v:202111.3-202196.6" - wire width 8 $0\xive10_pri$next[7:0]$14902 - attribute \src "libresoc.v:202093.3-202094.37" + attribute \src "libresoc.v:204803.3-204888.6" + wire width 8 $0\xive10_pri$next[7:0]$14888 + attribute \src "libresoc.v:204785.3-204786.37" wire width 8 $0\xive10_pri[7:0] - attribute \src "libresoc.v:202111.3-202196.6" - wire width 8 $0\xive11_pri$next[7:0]$14903 - attribute \src "libresoc.v:202095.3-202096.37" + attribute \src "libresoc.v:204803.3-204888.6" + wire width 8 $0\xive11_pri$next[7:0]$14889 + attribute \src "libresoc.v:204787.3-204788.37" wire width 8 $0\xive11_pri[7:0] - attribute \src "libresoc.v:202111.3-202196.6" - wire width 8 $0\xive12_pri$next[7:0]$14904 - attribute \src "libresoc.v:202097.3-202098.37" + attribute \src "libresoc.v:204803.3-204888.6" + wire width 8 $0\xive12_pri$next[7:0]$14890 + attribute \src "libresoc.v:204789.3-204790.37" wire width 8 $0\xive12_pri[7:0] - attribute \src "libresoc.v:202111.3-202196.6" - wire width 8 $0\xive13_pri$next[7:0]$14905 - attribute \src "libresoc.v:202099.3-202100.37" + attribute \src "libresoc.v:204803.3-204888.6" + wire width 8 $0\xive13_pri$next[7:0]$14891 + attribute \src "libresoc.v:204791.3-204792.37" wire width 8 $0\xive13_pri[7:0] - attribute \src "libresoc.v:202111.3-202196.6" - wire width 8 $0\xive14_pri$next[7:0]$14906 - attribute \src "libresoc.v:202101.3-202102.37" + attribute \src "libresoc.v:204803.3-204888.6" + wire width 8 $0\xive14_pri$next[7:0]$14892 + attribute \src "libresoc.v:204793.3-204794.37" wire width 8 $0\xive14_pri[7:0] - attribute \src "libresoc.v:202111.3-202196.6" - wire width 8 $0\xive15_pri$next[7:0]$14907 - attribute \src "libresoc.v:202103.3-202104.37" + attribute \src "libresoc.v:204803.3-204888.6" + wire width 8 $0\xive15_pri$next[7:0]$14893 + attribute \src "libresoc.v:204795.3-204796.37" wire width 8 $0\xive15_pri[7:0] - attribute \src "libresoc.v:202111.3-202196.6" - wire width 8 $0\xive1_pri$next[7:0]$14908 - attribute \src "libresoc.v:202075.3-202076.35" + attribute \src "libresoc.v:204803.3-204888.6" + wire width 8 $0\xive1_pri$next[7:0]$14894 + attribute \src "libresoc.v:204767.3-204768.35" wire width 8 $0\xive1_pri[7:0] - attribute \src "libresoc.v:202111.3-202196.6" - wire width 8 $0\xive2_pri$next[7:0]$14909 - attribute \src "libresoc.v:202077.3-202078.35" + attribute \src "libresoc.v:204803.3-204888.6" + wire width 8 $0\xive2_pri$next[7:0]$14895 + attribute \src "libresoc.v:204769.3-204770.35" wire width 8 $0\xive2_pri[7:0] - attribute \src "libresoc.v:202111.3-202196.6" - wire width 8 $0\xive3_pri$next[7:0]$14910 - attribute \src "libresoc.v:202079.3-202080.35" + attribute \src "libresoc.v:204803.3-204888.6" + wire width 8 $0\xive3_pri$next[7:0]$14896 + attribute \src "libresoc.v:204771.3-204772.35" wire width 8 $0\xive3_pri[7:0] - attribute \src "libresoc.v:202111.3-202196.6" - wire width 8 $0\xive4_pri$next[7:0]$14911 - attribute \src "libresoc.v:202081.3-202082.35" + attribute \src "libresoc.v:204803.3-204888.6" + wire width 8 $0\xive4_pri$next[7:0]$14897 + attribute \src "libresoc.v:204773.3-204774.35" wire width 8 $0\xive4_pri[7:0] - attribute \src "libresoc.v:202111.3-202196.6" - wire width 8 $0\xive5_pri$next[7:0]$14912 - attribute \src "libresoc.v:202083.3-202084.35" + attribute \src "libresoc.v:204803.3-204888.6" + wire width 8 $0\xive5_pri$next[7:0]$14898 + attribute \src "libresoc.v:204775.3-204776.35" wire width 8 $0\xive5_pri[7:0] - attribute \src "libresoc.v:202111.3-202196.6" - wire width 8 $0\xive6_pri$next[7:0]$14913 - attribute \src "libresoc.v:202085.3-202086.35" + attribute \src "libresoc.v:204803.3-204888.6" + wire width 8 $0\xive6_pri$next[7:0]$14899 + attribute \src "libresoc.v:204777.3-204778.35" wire width 8 $0\xive6_pri[7:0] - attribute \src "libresoc.v:202111.3-202196.6" - wire width 8 $0\xive7_pri$next[7:0]$14914 - attribute \src "libresoc.v:202087.3-202088.35" + attribute \src "libresoc.v:204803.3-204888.6" + wire width 8 $0\xive7_pri$next[7:0]$14900 + attribute \src "libresoc.v:204779.3-204780.35" wire width 8 $0\xive7_pri[7:0] - attribute \src "libresoc.v:202111.3-202196.6" - wire width 8 $0\xive8_pri$next[7:0]$14915 - attribute \src "libresoc.v:202089.3-202090.35" + attribute \src "libresoc.v:204803.3-204888.6" + wire width 8 $0\xive8_pri$next[7:0]$14901 + attribute \src "libresoc.v:204781.3-204782.35" wire width 8 $0\xive8_pri[7:0] - attribute \src "libresoc.v:202111.3-202196.6" - wire width 8 $0\xive9_pri$next[7:0]$14916 - attribute \src "libresoc.v:202091.3-202092.35" + attribute \src "libresoc.v:204803.3-204888.6" + wire width 8 $0\xive9_pri$next[7:0]$14902 + attribute \src "libresoc.v:204783.3-204784.35" wire width 8 $0\xive9_pri[7:0] - attribute \src "libresoc.v:202496.3-202545.6" + attribute \src "libresoc.v:205188.3-205237.6" wire width 32 $1\be_out[31:0] - attribute \src "libresoc.v:202207.3-202216.6" + attribute \src "libresoc.v:204899.3-204908.6" wire width 4 $1\cur_idx0[3:0] - attribute \src "libresoc.v:202416.3-202425.6" + attribute \src "libresoc.v:205108.3-205117.6" wire width 4 $1\cur_idx10[3:0] - attribute \src "libresoc.v:202436.3-202445.6" + attribute \src "libresoc.v:205128.3-205137.6" wire width 4 $1\cur_idx11[3:0] - attribute \src "libresoc.v:202456.3-202465.6" + attribute \src "libresoc.v:205148.3-205157.6" wire width 4 $1\cur_idx12[3:0] - attribute \src "libresoc.v:202476.3-202485.6" + attribute \src "libresoc.v:205168.3-205177.6" wire width 4 $1\cur_idx13[3:0] - attribute \src "libresoc.v:202546.3-202555.6" + attribute \src "libresoc.v:205238.3-205247.6" wire width 4 $1\cur_idx14[3:0] - attribute \src "libresoc.v:202566.3-202575.6" + attribute \src "libresoc.v:205258.3-205267.6" wire width 4 $1\cur_idx15[3:0] - attribute \src "libresoc.v:202227.3-202236.6" + attribute \src "libresoc.v:204919.3-204928.6" wire width 4 $1\cur_idx1[3:0] - attribute \src "libresoc.v:202247.3-202256.6" + attribute \src "libresoc.v:204939.3-204948.6" wire width 4 $1\cur_idx2[3:0] - attribute \src "libresoc.v:202267.3-202276.6" + attribute \src "libresoc.v:204959.3-204968.6" wire width 4 $1\cur_idx3[3:0] - attribute \src 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attribute \src "libresoc.v:202426.3-202435.6" + attribute \src "libresoc.v:205118.3-205127.6" wire width 8 $1\cur_pri11[7:0] - attribute \src "libresoc.v:202446.3-202455.6" + attribute \src "libresoc.v:205138.3-205147.6" wire width 8 $1\cur_pri12[7:0] - attribute \src "libresoc.v:202466.3-202475.6" + attribute \src "libresoc.v:205158.3-205167.6" wire width 8 $1\cur_pri13[7:0] - attribute \src "libresoc.v:202486.3-202495.6" + attribute \src "libresoc.v:205178.3-205187.6" wire width 8 $1\cur_pri14[7:0] - attribute \src "libresoc.v:202556.3-202565.6" + attribute \src "libresoc.v:205248.3-205257.6" wire width 8 $1\cur_pri15[7:0] - attribute \src "libresoc.v:202217.3-202226.6" + attribute \src "libresoc.v:204909.3-204918.6" wire width 8 $1\cur_pri1[7:0] - attribute \src "libresoc.v:202237.3-202246.6" + attribute \src "libresoc.v:204929.3-204938.6" wire width 8 $1\cur_pri2[7:0] - attribute \src "libresoc.v:202257.3-202266.6" + attribute \src "libresoc.v:204949.3-204958.6" wire width 8 $1\cur_pri3[7:0] - attribute \src "libresoc.v:202277.3-202286.6" + attribute \src "libresoc.v:204969.3-204978.6" wire width 8 $1\cur_pri4[7:0] - attribute \src "libresoc.v:202306.3-202315.6" + attribute \src "libresoc.v:204998.3-205007.6" wire width 8 $1\cur_pri5[7:0] - attribute \src "libresoc.v:202326.3-202335.6" + attribute \src "libresoc.v:205018.3-205027.6" wire width 8 $1\cur_pri6[7:0] - attribute \src "libresoc.v:202346.3-202355.6" + attribute \src "libresoc.v:205038.3-205047.6" wire width 8 $1\cur_pri7[7:0] - attribute \src "libresoc.v:202366.3-202375.6" + attribute \src "libresoc.v:205058.3-205067.6" wire width 8 $1\cur_pri8[7:0] - attribute \src "libresoc.v:202386.3-202395.6" + attribute \src "libresoc.v:205078.3-205087.6" wire width 8 $1\cur_pri9[7:0] - attribute \src "libresoc.v:202576.3-202585.6" + attribute \src "libresoc.v:205268.3-205277.6" wire $1\ibit[0:0] - attribute \src "libresoc.v:201848.13-201848.30" + attribute \src "libresoc.v:204540.13-204540.30" wire width 8 $1\icp_o_pri[7:0] - attribute \src "libresoc.v:201853.13-201853.29" + attribute \src "libresoc.v:204545.13-204545.29" wire width 4 $1\icp_o_src[3:0] - attribute \src "libresoc.v:202595.3-202603.6" - wire $1\ics_wb__ack$next[0:0]$15023 - attribute \src "libresoc.v:201862.7-201862.25" + attribute \src "libresoc.v:205287.3-205295.6" + wire $1\ics_wb__ack$next[0:0]$15009 + attribute \src "libresoc.v:204554.7-204554.25" wire $1\ics_wb__ack[0:0] - attribute \src "libresoc.v:202586.3-202594.6" - wire width 32 $1\ics_wb__dat_r$next[31:0]$15020 - attribute \src "libresoc.v:201871.14-201871.35" + attribute \src "libresoc.v:205278.3-205286.6" + wire width 32 $1\ics_wb__dat_r$next[31:0]$15006 + attribute \src "libresoc.v:204563.14-204563.35" wire width 32 $1\ics_wb__dat_r[31:0] - attribute \src "libresoc.v:202287.3-202295.6" - wire width 16 $1\int_level_l$next[15:0]$14992 - attribute \src "libresoc.v:201883.14-201883.36" + attribute \src "libresoc.v:204979.3-204987.6" + wire width 16 $1\int_level_l$next[15:0]$14978 + attribute \src "libresoc.v:204575.14-204575.36" wire width 16 $1\int_level_l[15:0] - attribute \src "libresoc.v:202111.3-202196.6" - wire width 8 $1\xive0_pri$next[7:0]$14917 - attribute \src "libresoc.v:201903.13-201903.30" + attribute \src "libresoc.v:204803.3-204888.6" + wire width 8 $1\xive0_pri$next[7:0]$14903 + attribute \src "libresoc.v:204595.13-204595.30" wire width 8 $1\xive0_pri[7:0] - attribute \src "libresoc.v:202111.3-202196.6" - wire width 8 $1\xive10_pri$next[7:0]$14918 - attribute \src "libresoc.v:201907.13-201907.31" + attribute \src "libresoc.v:204803.3-204888.6" + wire width 8 $1\xive10_pri$next[7:0]$14904 + attribute \src "libresoc.v:204599.13-204599.31" wire width 8 $1\xive10_pri[7:0] - attribute \src "libresoc.v:202111.3-202196.6" - wire width 8 $1\xive11_pri$next[7:0]$14919 - attribute \src "libresoc.v:201911.13-201911.31" + attribute \src "libresoc.v:204803.3-204888.6" + wire width 8 $1\xive11_pri$next[7:0]$14905 + attribute \src "libresoc.v:204603.13-204603.31" wire width 8 $1\xive11_pri[7:0] - attribute \src "libresoc.v:202111.3-202196.6" - wire width 8 $1\xive12_pri$next[7:0]$14920 - attribute \src "libresoc.v:201915.13-201915.31" + attribute \src "libresoc.v:204803.3-204888.6" + wire width 8 $1\xive12_pri$next[7:0]$14906 + attribute \src "libresoc.v:204607.13-204607.31" wire width 8 $1\xive12_pri[7:0] - attribute \src "libresoc.v:202111.3-202196.6" - wire width 8 $1\xive13_pri$next[7:0]$14921 - attribute \src "libresoc.v:201919.13-201919.31" + attribute \src "libresoc.v:204803.3-204888.6" + wire width 8 $1\xive13_pri$next[7:0]$14907 + attribute \src "libresoc.v:204611.13-204611.31" wire width 8 $1\xive13_pri[7:0] - attribute \src "libresoc.v:202111.3-202196.6" - wire width 8 $1\xive14_pri$next[7:0]$14922 - attribute \src "libresoc.v:201923.13-201923.31" + attribute \src "libresoc.v:204803.3-204888.6" + wire width 8 $1\xive14_pri$next[7:0]$14908 + attribute \src "libresoc.v:204615.13-204615.31" wire width 8 $1\xive14_pri[7:0] - attribute \src "libresoc.v:202111.3-202196.6" - wire width 8 $1\xive15_pri$next[7:0]$14923 - attribute \src "libresoc.v:201927.13-201927.31" + attribute \src "libresoc.v:204803.3-204888.6" + wire width 8 $1\xive15_pri$next[7:0]$14909 + attribute \src "libresoc.v:204619.13-204619.31" wire width 8 $1\xive15_pri[7:0] - attribute \src "libresoc.v:202111.3-202196.6" - wire width 8 $1\xive1_pri$next[7:0]$14924 - attribute \src "libresoc.v:201931.13-201931.30" + attribute \src "libresoc.v:204803.3-204888.6" + wire width 8 $1\xive1_pri$next[7:0]$14910 + attribute \src "libresoc.v:204623.13-204623.30" wire width 8 $1\xive1_pri[7:0] - attribute \src "libresoc.v:202111.3-202196.6" - wire width 8 $1\xive2_pri$next[7:0]$14925 - attribute \src "libresoc.v:201935.13-201935.30" + attribute \src "libresoc.v:204803.3-204888.6" + wire width 8 $1\xive2_pri$next[7:0]$14911 + attribute \src "libresoc.v:204627.13-204627.30" wire width 8 $1\xive2_pri[7:0] - attribute \src "libresoc.v:202111.3-202196.6" - wire width 8 $1\xive3_pri$next[7:0]$14926 - attribute \src "libresoc.v:201939.13-201939.30" + attribute \src "libresoc.v:204803.3-204888.6" + wire width 8 $1\xive3_pri$next[7:0]$14912 + attribute \src "libresoc.v:204631.13-204631.30" wire width 8 $1\xive3_pri[7:0] - attribute \src "libresoc.v:202111.3-202196.6" - wire width 8 $1\xive4_pri$next[7:0]$14927 - attribute \src "libresoc.v:201943.13-201943.30" + attribute \src "libresoc.v:204803.3-204888.6" + wire width 8 $1\xive4_pri$next[7:0]$14913 + attribute \src "libresoc.v:204635.13-204635.30" wire width 8 $1\xive4_pri[7:0] - attribute \src "libresoc.v:202111.3-202196.6" - wire width 8 $1\xive5_pri$next[7:0]$14928 - attribute \src "libresoc.v:201947.13-201947.30" + attribute \src "libresoc.v:204803.3-204888.6" + wire width 8 $1\xive5_pri$next[7:0]$14914 + attribute \src "libresoc.v:204639.13-204639.30" wire width 8 $1\xive5_pri[7:0] - attribute \src "libresoc.v:202111.3-202196.6" - wire width 8 $1\xive6_pri$next[7:0]$14929 - attribute \src "libresoc.v:201951.13-201951.30" + attribute \src "libresoc.v:204803.3-204888.6" + wire width 8 $1\xive6_pri$next[7:0]$14915 + attribute \src "libresoc.v:204643.13-204643.30" wire width 8 $1\xive6_pri[7:0] - attribute \src "libresoc.v:202111.3-202196.6" - wire width 8 $1\xive7_pri$next[7:0]$14930 - attribute \src "libresoc.v:201955.13-201955.30" + attribute \src "libresoc.v:204803.3-204888.6" + wire width 8 $1\xive7_pri$next[7:0]$14916 + attribute \src "libresoc.v:204647.13-204647.30" wire width 8 $1\xive7_pri[7:0] - attribute \src "libresoc.v:202111.3-202196.6" - wire width 8 $1\xive8_pri$next[7:0]$14931 - attribute \src "libresoc.v:201959.13-201959.30" + attribute \src "libresoc.v:204803.3-204888.6" + wire width 8 $1\xive8_pri$next[7:0]$14917 + attribute \src "libresoc.v:204651.13-204651.30" wire width 8 $1\xive8_pri[7:0] - attribute \src "libresoc.v:202111.3-202196.6" - wire width 8 $1\xive9_pri$next[7:0]$14932 - attribute \src "libresoc.v:201963.13-201963.30" + attribute \src "libresoc.v:204803.3-204888.6" + wire width 8 $1\xive9_pri$next[7:0]$14918 + attribute \src "libresoc.v:204655.13-204655.30" wire width 8 $1\xive9_pri[7:0] - attribute \src "libresoc.v:202496.3-202545.6" + attribute \src "libresoc.v:205188.3-205237.6" wire width 32 $2\be_out[31:0] - attribute \src "libresoc.v:202111.3-202196.6" - wire width 8 $2\xive0_pri$next[7:0]$14933 - attribute \src "libresoc.v:202111.3-202196.6" - wire width 8 $2\xive10_pri$next[7:0]$14934 - attribute \src "libresoc.v:202111.3-202196.6" - wire width 8 $2\xive11_pri$next[7:0]$14935 - attribute \src "libresoc.v:202111.3-202196.6" - wire width 8 $2\xive12_pri$next[7:0]$14936 - attribute \src "libresoc.v:202111.3-202196.6" - wire width 8 $2\xive13_pri$next[7:0]$14937 - attribute \src "libresoc.v:202111.3-202196.6" - wire width 8 $2\xive14_pri$next[7:0]$14938 - attribute \src "libresoc.v:202111.3-202196.6" - wire width 8 $2\xive15_pri$next[7:0]$14939 - attribute \src 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"libresoc.v:204748.18-204748.110" + wire $lt$libresoc.v:204748$14852_Y + attribute \src "libresoc.v:204750.18-204750.110" + wire $lt$libresoc.v:204750$14854_Y + attribute \src "libresoc.v:204752.18-204752.111" + wire $lt$libresoc.v:204752$14856_Y + attribute \src "libresoc.v:204754.18-204754.111" + wire $lt$libresoc.v:204754$14858_Y + attribute \src "libresoc.v:204757.18-204757.111" + wire $lt$libresoc.v:204757$14861_Y + attribute \src "libresoc.v:204759.18-204759.111" + wire $lt$libresoc.v:204759$14863_Y + attribute \src "libresoc.v:204746.18-204746.40" + wire width 16 $shr$libresoc.v:204746$14850_Y + attribute \src "libresoc.v:204658.17-204658.114" + wire width 8 $ternary$libresoc.v:204658$14762_Y + attribute \src "libresoc.v:204680.18-204680.116" + wire width 8 $ternary$libresoc.v:204680$14784_Y + attribute \src "libresoc.v:204702.18-204702.116" + wire width 8 $ternary$libresoc.v:204702$14806_Y + attribute \src "libresoc.v:204717.19-204717.118" + wire width 8 $ternary$libresoc.v:204717$14821_Y + attribute \src "libresoc.v:204719.18-204719.116" + wire width 8 $ternary$libresoc.v:204719$14823_Y + attribute \src "libresoc.v:204721.18-204721.116" + wire width 8 $ternary$libresoc.v:204721$14825_Y + attribute \src "libresoc.v:204723.18-204723.116" + wire width 8 $ternary$libresoc.v:204723$14827_Y + attribute \src "libresoc.v:204725.18-204725.116" + wire width 8 $ternary$libresoc.v:204725$14829_Y + attribute \src "libresoc.v:204727.18-204727.116" + wire width 8 $ternary$libresoc.v:204727$14831_Y + attribute \src "libresoc.v:204730.18-204730.116" + wire width 8 $ternary$libresoc.v:204730$14834_Y + attribute \src "libresoc.v:204732.18-204732.116" + wire width 8 $ternary$libresoc.v:204732$14836_Y + attribute \src "libresoc.v:204734.18-204734.117" + wire width 8 $ternary$libresoc.v:204734$14838_Y + attribute \src "libresoc.v:204736.18-204736.117" + wire width 8 $ternary$libresoc.v:204736$14840_Y + attribute \src "libresoc.v:204738.18-204738.117" + wire width 8 $ternary$libresoc.v:204738$14842_Y + attribute \src "libresoc.v:204741.18-204741.117" + wire width 8 $ternary$libresoc.v:204741$14845_Y + attribute \src "libresoc.v:204743.18-204743.117" + wire width 8 $ternary$libresoc.v:204743$14847_Y + attribute \src "libresoc.v:204745.18-204745.117" + wire width 8 $ternary$libresoc.v:204745$14849_Y attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293" wire \$1 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" @@ -419454,7 +392474,7 @@ module \xics_ics wire width 32 \be_in attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:308" wire width 32 \be_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 12 \clk attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:365" wire width 4 \cur_idx0 @@ -419552,7 +392572,7 @@ module \xics_ics wire input 7 \ics_wb__stb attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" wire input 11 \ics_wb__we - attribute \src "libresoc.v:201567.7-201567.15" + attribute \src "libresoc.v:204259.7-204259.15" wire \initial attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" wire width 16 input 5 \int_level_i @@ -419572,7 +392592,7 @@ module \xics_ics wire \reg_is_debug attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:286" wire \reg_is_xive - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:785" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:786" wire input 1 \rst attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:260" wire \wb_valid @@ -419641,7 +392661,7 @@ module \xics_ics attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:221" wire width 8 \xive9_pri$next attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:201968$14778 + cell $and $and$libresoc.v:204660$14764 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -419649,10 +392669,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [3] connect \B \$99 - connect \Y $and$libresoc.v:201968$14778_Y + connect \Y $and$libresoc.v:204660$14764_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:201970$14780 + cell $and $and$libresoc.v:204662$14766 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -419660,10 +392680,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [3] connect \B \$103 - connect \Y $and$libresoc.v:201970$14780_Y + connect \Y $and$libresoc.v:204662$14766_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:201972$14782 + cell $and $and$libresoc.v:204664$14768 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -419671,10 +392691,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [4] connect \B \$107 - connect \Y $and$libresoc.v:201972$14782_Y + connect \Y $and$libresoc.v:204664$14768_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:201974$14784 + cell $and $and$libresoc.v:204666$14770 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -419682,10 +392702,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [4] connect \B \$111 - connect \Y $and$libresoc.v:201974$14784_Y + connect \Y $and$libresoc.v:204666$14770_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:201976$14786 + cell $and $and$libresoc.v:204668$14772 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -419693,10 +392713,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [5] connect \B \$115 - connect \Y $and$libresoc.v:201976$14786_Y + connect \Y $and$libresoc.v:204668$14772_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:201978$14788 + cell $and $and$libresoc.v:204670$14774 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -419704,10 +392724,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [5] connect \B \$119 - connect \Y $and$libresoc.v:201978$14788_Y + connect \Y $and$libresoc.v:204670$14774_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:201980$14790 + cell $and $and$libresoc.v:204672$14776 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -419715,10 +392735,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [6] connect \B \$123 - connect \Y $and$libresoc.v:201980$14790_Y + connect \Y $and$libresoc.v:204672$14776_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:201983$14793 + cell $and $and$libresoc.v:204675$14779 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -419726,10 +392746,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [6] connect \B \$127 - connect \Y $and$libresoc.v:201983$14793_Y + connect \Y $and$libresoc.v:204675$14779_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:201985$14795 + cell $and $and$libresoc.v:204677$14781 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -419737,10 +392757,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [7] connect \B \$131 - connect \Y $and$libresoc.v:201985$14795_Y + connect \Y $and$libresoc.v:204677$14781_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:201987$14797 + cell $and $and$libresoc.v:204679$14783 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -419748,10 +392768,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [7] connect \B \$135 - connect \Y $and$libresoc.v:201987$14797_Y + connect \Y $and$libresoc.v:204679$14783_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:201990$14800 + cell $and $and$libresoc.v:204682$14786 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -419759,10 +392779,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [8] connect \B \$139 - connect \Y $and$libresoc.v:201990$14800_Y + connect \Y $and$libresoc.v:204682$14786_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:201992$14802 + cell $and $and$libresoc.v:204684$14788 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -419770,10 +392790,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [8] connect \B \$143 - connect \Y $and$libresoc.v:201992$14802_Y + connect \Y $and$libresoc.v:204684$14788_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:201994$14804 + cell $and $and$libresoc.v:204686$14790 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -419781,10 +392801,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [9] connect \B \$147 - connect \Y $and$libresoc.v:201994$14804_Y + connect \Y $and$libresoc.v:204686$14790_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:201996$14806 + cell $and $and$libresoc.v:204688$14792 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -419792,10 +392812,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [9] connect \B \$151 - connect \Y $and$libresoc.v:201996$14806_Y + connect \Y $and$libresoc.v:204688$14792_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:201998$14808 + cell $and $and$libresoc.v:204690$14794 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -419803,10 +392823,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [10] connect \B \$155 - connect \Y $and$libresoc.v:201998$14808_Y + connect \Y $and$libresoc.v:204690$14794_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202000$14810 + cell $and $and$libresoc.v:204692$14796 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -419814,10 +392834,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [10] connect \B \$159 - connect \Y $and$libresoc.v:202000$14810_Y + connect \Y $and$libresoc.v:204692$14796_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202002$14812 + cell $and $and$libresoc.v:204694$14798 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -419825,10 +392845,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [11] connect \B \$163 - connect \Y $and$libresoc.v:202002$14812_Y + connect \Y $and$libresoc.v:204694$14798_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202005$14815 + cell $and $and$libresoc.v:204697$14801 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -419836,10 +392856,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [11] connect \B \$167 - connect \Y $and$libresoc.v:202005$14815_Y + connect \Y $and$libresoc.v:204697$14801_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202007$14817 + cell $and $and$libresoc.v:204699$14803 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -419847,10 +392867,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [12] connect \B \$171 - connect \Y $and$libresoc.v:202007$14817_Y + connect \Y $and$libresoc.v:204699$14803_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202009$14819 + cell $and $and$libresoc.v:204701$14805 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -419858,10 +392878,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [12] connect \B \$175 - connect \Y $and$libresoc.v:202009$14819_Y + connect \Y $and$libresoc.v:204701$14805_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202012$14822 + cell $and $and$libresoc.v:204704$14808 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -419869,10 +392889,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [13] connect \B \$179 - connect \Y $and$libresoc.v:202012$14822_Y + connect \Y $and$libresoc.v:204704$14808_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202014$14824 + cell $and $and$libresoc.v:204706$14810 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -419880,10 +392900,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [13] connect \B \$183 - connect \Y $and$libresoc.v:202014$14824_Y + connect \Y $and$libresoc.v:204706$14810_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202016$14826 + cell $and $and$libresoc.v:204708$14812 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -419891,10 +392911,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [14] connect \B \$187 - connect \Y $and$libresoc.v:202016$14826_Y + connect \Y $and$libresoc.v:204708$14812_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202018$14828 + cell $and $and$libresoc.v:204710$14814 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -419902,10 +392922,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [14] connect \B \$191 - connect \Y $and$libresoc.v:202018$14828_Y + connect \Y $and$libresoc.v:204710$14814_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202020$14830 + cell $and $and$libresoc.v:204712$14816 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -419913,10 +392933,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [15] connect \B \$195 - connect \Y $and$libresoc.v:202020$14830_Y + connect \Y $and$libresoc.v:204712$14816_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202023$14833 + cell $and $and$libresoc.v:204715$14819 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -419924,10 +392944,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [15] connect \B \$199 - connect \Y $and$libresoc.v:202023$14833_Y + connect \Y $and$libresoc.v:204715$14819_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:304" - cell $and $and$libresoc.v:202047$14857 + cell $and $and$libresoc.v:204739$14843 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -419935,10 +392955,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \ics_wb__cyc connect \B \ics_wb__stb - connect \Y $and$libresoc.v:202047$14857_Y + connect \Y $and$libresoc.v:204739$14843_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341" - cell $and $and$libresoc.v:202055$14865 + cell $and $and$libresoc.v:204747$14851 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -419946,10 +392966,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \wb_valid connect \B \ics_wb__we - connect \Y $and$libresoc.v:202055$14865_Y + connect \Y $and$libresoc.v:204747$14851_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202057$14867 + cell $and $and$libresoc.v:204749$14853 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -419957,10 +392977,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [0] connect \B \$75 - connect \Y $and$libresoc.v:202057$14867_Y + connect \Y $and$libresoc.v:204749$14853_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202059$14869 + cell $and $and$libresoc.v:204751$14855 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -419968,10 +392988,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [0] connect \B \$79 - connect \Y $and$libresoc.v:202059$14869_Y + connect \Y $and$libresoc.v:204751$14855_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202061$14871 + cell $and $and$libresoc.v:204753$14857 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -419979,10 +392999,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [1] connect \B \$83 - connect \Y $and$libresoc.v:202061$14871_Y + connect \Y $and$libresoc.v:204753$14857_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202064$14874 + cell $and $and$libresoc.v:204756$14860 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -419990,10 +393010,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [1] connect \B \$87 - connect \Y $and$libresoc.v:202064$14874_Y + connect \Y $and$libresoc.v:204756$14860_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202066$14876 + cell $and $and$libresoc.v:204758$14862 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420001,10 +393021,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [2] connect \B \$91 - connect \Y $and$libresoc.v:202066$14876_Y + connect \Y $and$libresoc.v:204758$14862_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" - cell $and $and$libresoc.v:202068$14878 + cell $and $and$libresoc.v:204760$14864 parameter \A_SIGNED 0 parameter \A_WIDTH 1 parameter \B_SIGNED 0 @@ -420012,10 +393032,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \int_level_l [2] connect \B \$95 - connect \Y $and$libresoc.v:202068$14878_Y + connect \Y $and$libresoc.v:204760$14864_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:201982$14792 + cell $eq $eq$libresoc.v:204674$14778 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420023,10 +393043,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive1_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:201982$14792_Y + connect \Y $eq$libresoc.v:204674$14778_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202004$14814 + cell $eq $eq$libresoc.v:204696$14800 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420034,10 +393054,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive2_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202004$14814_Y + connect \Y $eq$libresoc.v:204696$14800_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:293" - cell $eq $eq$libresoc.v:202021$14831 + cell $eq $eq$libresoc.v:204713$14817 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -420045,10 +393065,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \ics_wb__adr [9:0] connect \B 1'0 - connect \Y $eq$libresoc.v:202021$14831_Y + connect \Y $eq$libresoc.v:204713$14817_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202024$14834 + cell $eq $eq$libresoc.v:204716$14820 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420056,10 +393076,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \cur_pri15 connect \B 8'11111111 - connect \Y $eq$libresoc.v:202024$14834_Y + connect \Y $eq$libresoc.v:204716$14820_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202026$14836 + cell $eq $eq$libresoc.v:204718$14822 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420067,10 +393087,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive3_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202026$14836_Y + connect \Y $eq$libresoc.v:204718$14822_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202028$14838 + cell $eq $eq$libresoc.v:204720$14824 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420078,10 +393098,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive4_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202028$14838_Y + connect \Y $eq$libresoc.v:204720$14824_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202030$14840 + cell $eq $eq$libresoc.v:204722$14826 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420089,10 +393109,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive5_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202030$14840_Y + connect \Y $eq$libresoc.v:204722$14826_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202032$14842 + cell $eq $eq$libresoc.v:204724$14828 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420100,10 +393120,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive6_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202032$14842_Y + connect \Y $eq$libresoc.v:204724$14828_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202034$14844 + cell $eq $eq$libresoc.v:204726$14830 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420111,10 +393131,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive7_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202034$14844_Y + connect \Y $eq$libresoc.v:204726$14830_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:294" - cell $eq $eq$libresoc.v:202036$14846 + cell $eq $eq$libresoc.v:204728$14832 parameter \A_SIGNED 0 parameter \A_WIDTH 10 parameter \B_SIGNED 0 @@ -420122,10 +393142,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \ics_wb__adr [9:0] connect \B 3'100 - connect \Y $eq$libresoc.v:202036$14846_Y + connect \Y $eq$libresoc.v:204728$14832_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202037$14847 + cell $eq $eq$libresoc.v:204729$14833 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420133,10 +393153,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive8_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202037$14847_Y + connect \Y $eq$libresoc.v:204729$14833_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202039$14849 + cell $eq $eq$libresoc.v:204731$14835 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420144,10 +393164,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive9_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202039$14849_Y + connect \Y $eq$libresoc.v:204731$14835_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202041$14851 + cell $eq $eq$libresoc.v:204733$14837 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420155,10 +393175,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive10_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202041$14851_Y + connect \Y $eq$libresoc.v:204733$14837_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202043$14853 + cell $eq $eq$libresoc.v:204735$14839 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420166,10 +393186,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive11_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202043$14853_Y + connect \Y $eq$libresoc.v:204735$14839_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202045$14855 + cell $eq $eq$libresoc.v:204737$14841 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420177,10 +393197,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive12_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202045$14855_Y + connect \Y $eq$libresoc.v:204737$14841_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202048$14858 + cell $eq $eq$libresoc.v:204740$14844 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420188,10 +393208,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive13_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202048$14858_Y + connect \Y $eq$libresoc.v:204740$14844_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202050$14860 + cell $eq $eq$libresoc.v:204742$14846 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420199,10 +393219,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive14_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202050$14860_Y + connect \Y $eq$libresoc.v:204742$14846_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202052$14862 + cell $eq $eq$libresoc.v:204744$14848 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420210,10 +393230,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive15_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202052$14862_Y + connect \Y $eq$libresoc.v:204744$14848_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $eq $eq$libresoc.v:202063$14873 + cell $eq $eq$libresoc.v:204755$14859 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420221,10 +393241,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive0_pri connect \B 8'11111111 - connect \Y $eq$libresoc.v:202063$14873_Y + connect \Y $eq$libresoc.v:204755$14859_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:201967$14777 + cell $lt $lt$libresoc.v:204659$14763 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420232,10 +393252,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive3_pri connect \B \cur_pri2 - connect \Y $lt$libresoc.v:201967$14777_Y + connect \Y $lt$libresoc.v:204659$14763_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:201969$14779 + cell $lt $lt$libresoc.v:204661$14765 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420243,10 +393263,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive3_pri connect \B \cur_pri2 - connect \Y $lt$libresoc.v:201969$14779_Y + connect \Y $lt$libresoc.v:204661$14765_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:201971$14781 + cell $lt $lt$libresoc.v:204663$14767 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420254,10 +393274,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive4_pri connect \B \cur_pri3 - connect \Y $lt$libresoc.v:201971$14781_Y + connect \Y $lt$libresoc.v:204663$14767_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:201973$14783 + cell $lt $lt$libresoc.v:204665$14769 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420265,10 +393285,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive4_pri connect \B \cur_pri3 - connect \Y $lt$libresoc.v:201973$14783_Y + connect \Y $lt$libresoc.v:204665$14769_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:201975$14785 + cell $lt $lt$libresoc.v:204667$14771 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420276,10 +393296,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive5_pri connect \B \cur_pri4 - connect \Y $lt$libresoc.v:201975$14785_Y + connect \Y $lt$libresoc.v:204667$14771_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:201977$14787 + cell $lt $lt$libresoc.v:204669$14773 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420287,10 +393307,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive5_pri connect \B \cur_pri4 - connect \Y $lt$libresoc.v:201977$14787_Y + connect \Y $lt$libresoc.v:204669$14773_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:201979$14789 + cell $lt $lt$libresoc.v:204671$14775 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420298,10 +393318,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive6_pri connect \B \cur_pri5 - connect \Y $lt$libresoc.v:201979$14789_Y + connect \Y $lt$libresoc.v:204671$14775_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:201981$14791 + cell $lt $lt$libresoc.v:204673$14777 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420309,10 +393329,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive6_pri connect \B \cur_pri5 - connect \Y $lt$libresoc.v:201981$14791_Y + connect \Y $lt$libresoc.v:204673$14777_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:201984$14794 + cell $lt $lt$libresoc.v:204676$14780 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420320,10 +393340,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive7_pri connect \B \cur_pri6 - connect \Y $lt$libresoc.v:201984$14794_Y + connect \Y $lt$libresoc.v:204676$14780_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:201986$14796 + cell $lt $lt$libresoc.v:204678$14782 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420331,10 +393351,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive7_pri connect \B \cur_pri6 - connect \Y $lt$libresoc.v:201986$14796_Y + connect \Y $lt$libresoc.v:204678$14782_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:201989$14799 + cell $lt $lt$libresoc.v:204681$14785 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420342,10 +393362,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive8_pri connect \B \cur_pri7 - connect \Y $lt$libresoc.v:201989$14799_Y + connect \Y $lt$libresoc.v:204681$14785_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:201991$14801 + cell $lt $lt$libresoc.v:204683$14787 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420353,10 +393373,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive8_pri connect \B \cur_pri7 - connect \Y $lt$libresoc.v:201991$14801_Y + connect \Y $lt$libresoc.v:204683$14787_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:201993$14803 + cell $lt $lt$libresoc.v:204685$14789 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420364,10 +393384,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive9_pri connect \B \cur_pri8 - connect \Y $lt$libresoc.v:201993$14803_Y + connect \Y $lt$libresoc.v:204685$14789_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:201995$14805 + cell $lt $lt$libresoc.v:204687$14791 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420375,10 +393395,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive9_pri connect \B \cur_pri8 - connect \Y $lt$libresoc.v:201995$14805_Y + connect \Y $lt$libresoc.v:204687$14791_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:201997$14807 + cell $lt $lt$libresoc.v:204689$14793 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420386,10 +393406,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive10_pri connect \B \cur_pri9 - connect \Y $lt$libresoc.v:201997$14807_Y + connect \Y $lt$libresoc.v:204689$14793_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:201999$14809 + cell $lt $lt$libresoc.v:204691$14795 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420397,10 +393417,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive10_pri connect \B \cur_pri9 - connect \Y $lt$libresoc.v:201999$14809_Y + connect \Y $lt$libresoc.v:204691$14795_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202001$14811 + cell $lt $lt$libresoc.v:204693$14797 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420408,10 +393428,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive11_pri connect \B \cur_pri10 - connect \Y $lt$libresoc.v:202001$14811_Y + connect \Y $lt$libresoc.v:204693$14797_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202003$14813 + cell $lt $lt$libresoc.v:204695$14799 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420419,10 +393439,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive11_pri connect \B \cur_pri10 - connect \Y $lt$libresoc.v:202003$14813_Y + connect \Y $lt$libresoc.v:204695$14799_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202006$14816 + cell $lt $lt$libresoc.v:204698$14802 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420430,10 +393450,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive12_pri connect \B \cur_pri11 - connect \Y $lt$libresoc.v:202006$14816_Y + connect \Y $lt$libresoc.v:204698$14802_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202008$14818 + cell $lt $lt$libresoc.v:204700$14804 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420441,10 +393461,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive12_pri connect \B \cur_pri11 - connect \Y $lt$libresoc.v:202008$14818_Y + connect \Y $lt$libresoc.v:204700$14804_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202011$14821 + cell $lt $lt$libresoc.v:204703$14807 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420452,10 +393472,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive13_pri connect \B \cur_pri12 - connect \Y $lt$libresoc.v:202011$14821_Y + connect \Y $lt$libresoc.v:204703$14807_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202013$14823 + cell $lt $lt$libresoc.v:204705$14809 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420463,10 +393483,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive13_pri connect \B \cur_pri12 - connect \Y $lt$libresoc.v:202013$14823_Y + connect \Y $lt$libresoc.v:204705$14809_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202015$14825 + cell $lt $lt$libresoc.v:204707$14811 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420474,10 +393494,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive14_pri connect \B \cur_pri13 - connect \Y $lt$libresoc.v:202015$14825_Y + connect \Y $lt$libresoc.v:204707$14811_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202017$14827 + cell $lt $lt$libresoc.v:204709$14813 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420485,10 +393505,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive14_pri connect \B \cur_pri13 - connect \Y $lt$libresoc.v:202017$14827_Y + connect \Y $lt$libresoc.v:204709$14813_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202019$14829 + cell $lt $lt$libresoc.v:204711$14815 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420496,10 +393516,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive15_pri connect \B \cur_pri14 - connect \Y $lt$libresoc.v:202019$14829_Y + connect \Y $lt$libresoc.v:204711$14815_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202022$14832 + cell $lt $lt$libresoc.v:204714$14818 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420507,10 +393527,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive15_pri connect \B \cur_pri14 - connect \Y $lt$libresoc.v:202022$14832_Y + connect \Y $lt$libresoc.v:204714$14818_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202056$14866 + cell $lt $lt$libresoc.v:204748$14852 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420518,10 +393538,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive0_pri connect \B \max_pri - connect \Y $lt$libresoc.v:202056$14866_Y + connect \Y $lt$libresoc.v:204748$14852_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202058$14868 + cell $lt $lt$libresoc.v:204750$14854 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420529,10 +393549,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive0_pri connect \B \max_pri - connect \Y $lt$libresoc.v:202058$14868_Y + connect \Y $lt$libresoc.v:204750$14854_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202060$14870 + cell $lt $lt$libresoc.v:204752$14856 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420540,10 +393560,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive1_pri connect \B \cur_pri0 - connect \Y $lt$libresoc.v:202060$14870_Y + connect \Y $lt$libresoc.v:204752$14856_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202062$14872 + cell $lt $lt$libresoc.v:204754$14858 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420551,10 +393571,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive1_pri connect \B \cur_pri0 - connect \Y $lt$libresoc.v:202062$14872_Y + connect \Y $lt$libresoc.v:204754$14858_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202065$14875 + cell $lt $lt$libresoc.v:204757$14861 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420562,10 +393582,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive2_pri connect \B \cur_pri1 - connect \Y $lt$libresoc.v:202065$14875_Y + connect \Y $lt$libresoc.v:204757$14861_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" - cell $lt $lt$libresoc.v:202067$14877 + cell $lt $lt$libresoc.v:204759$14863 parameter \A_SIGNED 0 parameter \A_WIDTH 8 parameter \B_SIGNED 0 @@ -420573,10 +393593,10 @@ module \xics_ics parameter \Y_WIDTH 1 connect \A \xive2_pri connect \B \cur_pri1 - connect \Y $lt$libresoc.v:202067$14877_Y + connect \Y $lt$libresoc.v:204759$14863_Y end - attribute \src "libresoc.v:202054.18-202054.40" - cell $shr $shr$libresoc.v:202054$14864 + attribute \src "libresoc.v:204746.18-204746.40" + cell $shr $shr$libresoc.v:204746$14850 parameter \A_SIGNED 0 parameter \A_WIDTH 16 parameter \B_SIGNED 0 @@ -420584,469 +393604,469 @@ module \xics_ics parameter \Y_WIDTH 16 connect \A \int_level_l connect \B \reg_idx - connect \Y $shr$libresoc.v:202054$14864_Y + connect \Y $shr$libresoc.v:204746$14850_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:201966$14776 + cell $mux $ternary$libresoc.v:204658$14762 parameter \WIDTH 8 connect \A \xive0_pri connect \B 8'11111111 connect \S \$8 - connect \Y $ternary$libresoc.v:201966$14776_Y + connect \Y $ternary$libresoc.v:204658$14762_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:201988$14798 + cell $mux $ternary$libresoc.v:204680$14784 parameter \WIDTH 8 connect \A \xive1_pri connect \B 8'11111111 connect \S \$12 - connect \Y $ternary$libresoc.v:201988$14798_Y + connect \Y $ternary$libresoc.v:204680$14784_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202010$14820 + cell $mux $ternary$libresoc.v:204702$14806 parameter \WIDTH 8 connect \A \xive2_pri connect \B 8'11111111 connect \S \$16 - connect \Y $ternary$libresoc.v:202010$14820_Y + connect \Y $ternary$libresoc.v:204702$14806_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202025$14835 + cell $mux $ternary$libresoc.v:204717$14821 parameter \WIDTH 8 connect \A \cur_pri15 connect \B 8'11111111 connect \S \$204 - connect \Y $ternary$libresoc.v:202025$14835_Y + connect \Y $ternary$libresoc.v:204717$14821_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202027$14837 + cell $mux $ternary$libresoc.v:204719$14823 parameter \WIDTH 8 connect \A \xive3_pri connect \B 8'11111111 connect \S \$20 - connect \Y $ternary$libresoc.v:202027$14837_Y + connect \Y $ternary$libresoc.v:204719$14823_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202029$14839 + cell $mux $ternary$libresoc.v:204721$14825 parameter \WIDTH 8 connect \A \xive4_pri connect \B 8'11111111 connect \S \$24 - connect \Y $ternary$libresoc.v:202029$14839_Y + connect \Y $ternary$libresoc.v:204721$14825_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202031$14841 + cell $mux $ternary$libresoc.v:204723$14827 parameter \WIDTH 8 connect \A \xive5_pri connect \B 8'11111111 connect \S \$28 - connect \Y $ternary$libresoc.v:202031$14841_Y + connect \Y $ternary$libresoc.v:204723$14827_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202033$14843 + cell $mux $ternary$libresoc.v:204725$14829 parameter \WIDTH 8 connect \A \xive6_pri connect \B 8'11111111 connect \S \$32 - connect \Y $ternary$libresoc.v:202033$14843_Y + connect \Y $ternary$libresoc.v:204725$14829_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202035$14845 + cell $mux $ternary$libresoc.v:204727$14831 parameter \WIDTH 8 connect \A \xive7_pri connect \B 8'11111111 connect \S \$36 - connect \Y $ternary$libresoc.v:202035$14845_Y + connect \Y $ternary$libresoc.v:204727$14831_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202038$14848 + cell $mux $ternary$libresoc.v:204730$14834 parameter \WIDTH 8 connect \A \xive8_pri connect \B 8'11111111 connect \S \$40 - connect \Y $ternary$libresoc.v:202038$14848_Y + connect \Y $ternary$libresoc.v:204730$14834_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202040$14850 + cell $mux $ternary$libresoc.v:204732$14836 parameter \WIDTH 8 connect \A \xive9_pri connect \B 8'11111111 connect \S \$44 - connect \Y $ternary$libresoc.v:202040$14850_Y + connect \Y $ternary$libresoc.v:204732$14836_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202042$14852 + cell $mux $ternary$libresoc.v:204734$14838 parameter \WIDTH 8 connect \A \xive10_pri connect \B 8'11111111 connect \S \$48 - connect \Y $ternary$libresoc.v:202042$14852_Y + connect \Y $ternary$libresoc.v:204734$14838_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202044$14854 + cell $mux $ternary$libresoc.v:204736$14840 parameter \WIDTH 8 connect \A \xive11_pri connect \B 8'11111111 connect \S \$52 - connect \Y $ternary$libresoc.v:202044$14854_Y + connect \Y $ternary$libresoc.v:204736$14840_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202046$14856 + cell $mux $ternary$libresoc.v:204738$14842 parameter \WIDTH 8 connect \A \xive12_pri connect \B 8'11111111 connect \S \$56 - connect \Y $ternary$libresoc.v:202046$14856_Y + connect \Y $ternary$libresoc.v:204738$14842_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202049$14859 + cell $mux $ternary$libresoc.v:204741$14845 parameter \WIDTH 8 connect \A \xive13_pri connect \B 8'11111111 connect \S \$60 - connect \Y $ternary$libresoc.v:202049$14859_Y + connect \Y $ternary$libresoc.v:204741$14845_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202051$14861 + cell $mux $ternary$libresoc.v:204743$14847 parameter \WIDTH 8 connect \A \xive14_pri connect \B 8'11111111 connect \S \$64 - connect \Y $ternary$libresoc.v:202051$14861_Y + connect \Y $ternary$libresoc.v:204743$14847_Y end attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" - cell $mux $ternary$libresoc.v:202053$14863 + cell $mux $ternary$libresoc.v:204745$14849 parameter \WIDTH 8 connect \A \xive15_pri connect \B 8'11111111 connect \S \$68 - connect \Y $ternary$libresoc.v:202053$14863_Y + connect \Y $ternary$libresoc.v:204745$14849_Y end - attribute \src "libresoc.v:201567.7-201567.20" - process $proc$libresoc.v:201567$15024 + attribute \src "libresoc.v:204259.7-204259.20" + process $proc$libresoc.v:204259$15010 assign { } { } assign $0\initial[0:0] 1'0 sync always update \initial $0\initial[0:0] sync init end - attribute \src "libresoc.v:201848.13-201848.30" - process $proc$libresoc.v:201848$15025 + attribute \src "libresoc.v:204540.13-204540.30" + process $proc$libresoc.v:204540$15011 assign { } { } assign $1\icp_o_pri[7:0] 8'00000000 sync always sync init update \icp_o_pri $1\icp_o_pri[7:0] end - attribute \src "libresoc.v:201853.13-201853.29" - process $proc$libresoc.v:201853$15026 + attribute \src "libresoc.v:204545.13-204545.29" + process $proc$libresoc.v:204545$15012 assign { } { } assign $1\icp_o_src[3:0] 4'0000 sync always sync init update \icp_o_src $1\icp_o_src[3:0] end - attribute \src "libresoc.v:201862.7-201862.25" - process $proc$libresoc.v:201862$15027 + attribute \src "libresoc.v:204554.7-204554.25" + process $proc$libresoc.v:204554$15013 assign { } { } assign $1\ics_wb__ack[0:0] 1'0 sync always sync init update \ics_wb__ack $1\ics_wb__ack[0:0] end - attribute \src "libresoc.v:201871.14-201871.35" - process $proc$libresoc.v:201871$15028 + attribute \src "libresoc.v:204563.14-204563.35" + process $proc$libresoc.v:204563$15014 assign { } { } assign $1\ics_wb__dat_r[31:0] 0 sync always sync init update \ics_wb__dat_r $1\ics_wb__dat_r[31:0] end - attribute \src "libresoc.v:201883.14-201883.36" - process $proc$libresoc.v:201883$15029 + attribute \src "libresoc.v:204575.14-204575.36" + process $proc$libresoc.v:204575$15015 assign { } { } assign $1\int_level_l[15:0] 16'0000000000000000 sync always sync init update \int_level_l $1\int_level_l[15:0] end - attribute \src "libresoc.v:201903.13-201903.30" - process $proc$libresoc.v:201903$15030 + attribute \src "libresoc.v:204595.13-204595.30" + process $proc$libresoc.v:204595$15016 assign { } { } assign $1\xive0_pri[7:0] 8'11111111 sync always sync init update \xive0_pri $1\xive0_pri[7:0] end - attribute \src "libresoc.v:201907.13-201907.31" - process $proc$libresoc.v:201907$15031 + attribute \src "libresoc.v:204599.13-204599.31" + process $proc$libresoc.v:204599$15017 assign { } { } assign $1\xive10_pri[7:0] 8'11111111 sync always sync init update \xive10_pri $1\xive10_pri[7:0] end - attribute \src "libresoc.v:201911.13-201911.31" - process $proc$libresoc.v:201911$15032 + attribute \src "libresoc.v:204603.13-204603.31" + process $proc$libresoc.v:204603$15018 assign { } { } assign $1\xive11_pri[7:0] 8'11111111 sync always sync init update \xive11_pri $1\xive11_pri[7:0] end - attribute \src "libresoc.v:201915.13-201915.31" - process $proc$libresoc.v:201915$15033 + attribute \src "libresoc.v:204607.13-204607.31" + process $proc$libresoc.v:204607$15019 assign { } { } assign $1\xive12_pri[7:0] 8'11111111 sync always sync init update \xive12_pri $1\xive12_pri[7:0] end - attribute \src "libresoc.v:201919.13-201919.31" - process $proc$libresoc.v:201919$15034 + attribute \src "libresoc.v:204611.13-204611.31" + process $proc$libresoc.v:204611$15020 assign { } { } assign $1\xive13_pri[7:0] 8'11111111 sync always sync init update \xive13_pri $1\xive13_pri[7:0] end - attribute \src "libresoc.v:201923.13-201923.31" - process $proc$libresoc.v:201923$15035 + attribute \src "libresoc.v:204615.13-204615.31" + process $proc$libresoc.v:204615$15021 assign { } { } assign $1\xive14_pri[7:0] 8'11111111 sync always sync init update \xive14_pri $1\xive14_pri[7:0] end - attribute \src "libresoc.v:201927.13-201927.31" - process $proc$libresoc.v:201927$15036 + attribute \src "libresoc.v:204619.13-204619.31" + process $proc$libresoc.v:204619$15022 assign { } { } assign $1\xive15_pri[7:0] 8'11111111 sync always sync init update \xive15_pri $1\xive15_pri[7:0] end - attribute \src "libresoc.v:201931.13-201931.30" - process $proc$libresoc.v:201931$15037 + attribute \src "libresoc.v:204623.13-204623.30" + process $proc$libresoc.v:204623$15023 assign { } { } assign $1\xive1_pri[7:0] 8'11111111 sync always sync init update \xive1_pri $1\xive1_pri[7:0] end - attribute \src "libresoc.v:201935.13-201935.30" - process $proc$libresoc.v:201935$15038 + attribute \src "libresoc.v:204627.13-204627.30" + process $proc$libresoc.v:204627$15024 assign { } { } assign $1\xive2_pri[7:0] 8'11111111 sync always sync init update \xive2_pri $1\xive2_pri[7:0] end - attribute \src "libresoc.v:201939.13-201939.30" - process $proc$libresoc.v:201939$15039 + attribute \src "libresoc.v:204631.13-204631.30" + process $proc$libresoc.v:204631$15025 assign { } { } assign $1\xive3_pri[7:0] 8'11111111 sync always sync init update \xive3_pri $1\xive3_pri[7:0] end - attribute \src "libresoc.v:201943.13-201943.30" - process $proc$libresoc.v:201943$15040 + attribute \src "libresoc.v:204635.13-204635.30" + process $proc$libresoc.v:204635$15026 assign { } { } assign $1\xive4_pri[7:0] 8'11111111 sync always sync init update \xive4_pri $1\xive4_pri[7:0] end - attribute \src "libresoc.v:201947.13-201947.30" - process $proc$libresoc.v:201947$15041 + attribute \src "libresoc.v:204639.13-204639.30" + process $proc$libresoc.v:204639$15027 assign { } { } assign $1\xive5_pri[7:0] 8'11111111 sync always sync init update \xive5_pri $1\xive5_pri[7:0] end - attribute \src "libresoc.v:201951.13-201951.30" - process $proc$libresoc.v:201951$15042 + attribute \src "libresoc.v:204643.13-204643.30" + process $proc$libresoc.v:204643$15028 assign { } { } assign $1\xive6_pri[7:0] 8'11111111 sync always sync init update \xive6_pri $1\xive6_pri[7:0] end - attribute \src "libresoc.v:201955.13-201955.30" - process $proc$libresoc.v:201955$15043 + attribute \src "libresoc.v:204647.13-204647.30" + process $proc$libresoc.v:204647$15029 assign { } { } assign $1\xive7_pri[7:0] 8'11111111 sync always sync init update \xive7_pri $1\xive7_pri[7:0] end - attribute \src "libresoc.v:201959.13-201959.30" - process $proc$libresoc.v:201959$15044 + attribute \src "libresoc.v:204651.13-204651.30" + process $proc$libresoc.v:204651$15030 assign { } { } assign $1\xive8_pri[7:0] 8'11111111 sync always sync init update \xive8_pri $1\xive8_pri[7:0] end - attribute \src "libresoc.v:201963.13-201963.30" - process $proc$libresoc.v:201963$15045 + attribute \src "libresoc.v:204655.13-204655.30" + process $proc$libresoc.v:204655$15031 assign { } { } assign $1\xive9_pri[7:0] 8'11111111 sync always sync init update \xive9_pri $1\xive9_pri[7:0] end - attribute \src "libresoc.v:202069.3-202070.28" - process $proc$libresoc.v:202069$14879 + attribute \src "libresoc.v:204761.3-204762.28" + process $proc$libresoc.v:204761$14865 assign { } { } assign $0\icp_o_src[3:0] \cur_idx15 sync posedge \clk update \icp_o_src $0\icp_o_src[3:0] end - attribute \src "libresoc.v:202071.3-202072.25" - process $proc$libresoc.v:202071$14880 + attribute \src "libresoc.v:204763.3-204764.25" + process $proc$libresoc.v:204763$14866 assign { } { } assign $0\icp_o_pri[7:0] \$203 sync posedge \clk update \icp_o_pri $0\icp_o_pri[7:0] end - attribute \src "libresoc.v:202073.3-202074.35" - process $proc$libresoc.v:202073$14881 + attribute \src "libresoc.v:204765.3-204766.35" + process $proc$libresoc.v:204765$14867 assign { } { } assign $0\xive0_pri[7:0] \xive0_pri$next sync posedge \clk update \xive0_pri $0\xive0_pri[7:0] end - attribute \src "libresoc.v:202075.3-202076.35" - process $proc$libresoc.v:202075$14882 + attribute \src "libresoc.v:204767.3-204768.35" + process $proc$libresoc.v:204767$14868 assign { } { } assign $0\xive1_pri[7:0] \xive1_pri$next sync posedge \clk update \xive1_pri $0\xive1_pri[7:0] end - attribute \src "libresoc.v:202077.3-202078.35" - process $proc$libresoc.v:202077$14883 + attribute \src "libresoc.v:204769.3-204770.35" + process $proc$libresoc.v:204769$14869 assign { } { } assign $0\xive2_pri[7:0] \xive2_pri$next sync posedge \clk update \xive2_pri $0\xive2_pri[7:0] end - attribute \src "libresoc.v:202079.3-202080.35" - process $proc$libresoc.v:202079$14884 + attribute \src "libresoc.v:204771.3-204772.35" + process $proc$libresoc.v:204771$14870 assign { } { } assign $0\xive3_pri[7:0] \xive3_pri$next sync posedge \clk update \xive3_pri $0\xive3_pri[7:0] end - attribute \src "libresoc.v:202081.3-202082.35" - process $proc$libresoc.v:202081$14885 + attribute \src "libresoc.v:204773.3-204774.35" + process $proc$libresoc.v:204773$14871 assign { } { } assign $0\xive4_pri[7:0] \xive4_pri$next sync posedge \clk update \xive4_pri $0\xive4_pri[7:0] end - attribute \src "libresoc.v:202083.3-202084.35" - process $proc$libresoc.v:202083$14886 + attribute \src "libresoc.v:204775.3-204776.35" + process $proc$libresoc.v:204775$14872 assign { } { } assign $0\xive5_pri[7:0] \xive5_pri$next sync posedge \clk update \xive5_pri $0\xive5_pri[7:0] end - attribute \src "libresoc.v:202085.3-202086.35" - process $proc$libresoc.v:202085$14887 + attribute \src "libresoc.v:204777.3-204778.35" + process $proc$libresoc.v:204777$14873 assign { } { } assign $0\xive6_pri[7:0] \xive6_pri$next sync posedge \clk update \xive6_pri $0\xive6_pri[7:0] end - attribute \src "libresoc.v:202087.3-202088.35" - process $proc$libresoc.v:202087$14888 + attribute \src "libresoc.v:204779.3-204780.35" + process $proc$libresoc.v:204779$14874 assign { } { } assign $0\xive7_pri[7:0] \xive7_pri$next sync posedge \clk update \xive7_pri $0\xive7_pri[7:0] end - attribute \src "libresoc.v:202089.3-202090.35" - process $proc$libresoc.v:202089$14889 + attribute \src "libresoc.v:204781.3-204782.35" + process $proc$libresoc.v:204781$14875 assign { } { } assign $0\xive8_pri[7:0] \xive8_pri$next sync posedge \clk update \xive8_pri $0\xive8_pri[7:0] end - attribute \src "libresoc.v:202091.3-202092.35" - process $proc$libresoc.v:202091$14890 + attribute \src "libresoc.v:204783.3-204784.35" + process $proc$libresoc.v:204783$14876 assign { } { } assign $0\xive9_pri[7:0] \xive9_pri$next sync posedge \clk update \xive9_pri $0\xive9_pri[7:0] end - attribute \src "libresoc.v:202093.3-202094.37" - process $proc$libresoc.v:202093$14891 + attribute \src "libresoc.v:204785.3-204786.37" + process $proc$libresoc.v:204785$14877 assign { } { } assign $0\xive10_pri[7:0] \xive10_pri$next sync posedge \clk update \xive10_pri $0\xive10_pri[7:0] end - attribute \src "libresoc.v:202095.3-202096.37" - process $proc$libresoc.v:202095$14892 + attribute \src "libresoc.v:204787.3-204788.37" + process $proc$libresoc.v:204787$14878 assign { } { } assign $0\xive11_pri[7:0] \xive11_pri$next sync posedge \clk update \xive11_pri $0\xive11_pri[7:0] end - attribute \src "libresoc.v:202097.3-202098.37" - process $proc$libresoc.v:202097$14893 + attribute \src "libresoc.v:204789.3-204790.37" + process $proc$libresoc.v:204789$14879 assign { } { } assign $0\xive12_pri[7:0] \xive12_pri$next sync posedge \clk update \xive12_pri $0\xive12_pri[7:0] end - attribute \src "libresoc.v:202099.3-202100.37" - process $proc$libresoc.v:202099$14894 + attribute \src "libresoc.v:204791.3-204792.37" + process $proc$libresoc.v:204791$14880 assign { } { } assign $0\xive13_pri[7:0] \xive13_pri$next sync posedge \clk update \xive13_pri $0\xive13_pri[7:0] end - attribute \src "libresoc.v:202101.3-202102.37" - process $proc$libresoc.v:202101$14895 + attribute \src "libresoc.v:204793.3-204794.37" + process $proc$libresoc.v:204793$14881 assign { } { } assign $0\xive14_pri[7:0] \xive14_pri$next sync posedge \clk update \xive14_pri $0\xive14_pri[7:0] end - attribute \src "libresoc.v:202103.3-202104.37" - process $proc$libresoc.v:202103$14896 + attribute \src "libresoc.v:204795.3-204796.37" + process $proc$libresoc.v:204795$14882 assign { } { } assign $0\xive15_pri[7:0] \xive15_pri$next sync posedge \clk update \xive15_pri $0\xive15_pri[7:0] end - attribute \src "libresoc.v:202105.3-202106.39" - process $proc$libresoc.v:202105$14897 + attribute \src "libresoc.v:204797.3-204798.39" + process $proc$libresoc.v:204797$14883 assign { } { } assign $0\ics_wb__ack[0:0] \ics_wb__ack$next sync posedge \clk update \ics_wb__ack $0\ics_wb__ack[0:0] end - attribute \src "libresoc.v:202107.3-202108.43" - process $proc$libresoc.v:202107$14898 + attribute \src "libresoc.v:204799.3-204800.43" + process $proc$libresoc.v:204799$14884 assign { } { } assign $0\ics_wb__dat_r[31:0] \ics_wb__dat_r$next sync posedge \clk update \ics_wb__dat_r $0\ics_wb__dat_r[31:0] end - attribute \src "libresoc.v:202109.3-202110.39" - process $proc$libresoc.v:202109$14899 + attribute \src "libresoc.v:204801.3-204802.39" + process $proc$libresoc.v:204801$14885 assign { } { } assign $0\int_level_l[15:0] \int_level_l$next sync posedge \clk update \int_level_l $0\int_level_l[15:0] end - attribute \src "libresoc.v:202111.3-202196.6" - process $proc$libresoc.v:202111$14900 + attribute \src "libresoc.v:204803.3-204888.6" + process $proc$libresoc.v:204803$14886 assign { } { } assign { } { } assign { } { } @@ -421095,25 +394115,25 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $0\xive0_pri$next[7:0]$14901 $4\xive0_pri$next[7:0]$14965 - assign $0\xive10_pri$next[7:0]$14902 $4\xive10_pri$next[7:0]$14966 - assign $0\xive11_pri$next[7:0]$14903 $4\xive11_pri$next[7:0]$14967 - assign $0\xive12_pri$next[7:0]$14904 $4\xive12_pri$next[7:0]$14968 - assign $0\xive13_pri$next[7:0]$14905 $4\xive13_pri$next[7:0]$14969 - assign $0\xive14_pri$next[7:0]$14906 $4\xive14_pri$next[7:0]$14970 - assign $0\xive15_pri$next[7:0]$14907 $4\xive15_pri$next[7:0]$14971 - assign $0\xive1_pri$next[7:0]$14908 $4\xive1_pri$next[7:0]$14972 - assign $0\xive2_pri$next[7:0]$14909 $4\xive2_pri$next[7:0]$14973 - assign $0\xive3_pri$next[7:0]$14910 $4\xive3_pri$next[7:0]$14974 - assign $0\xive4_pri$next[7:0]$14911 $4\xive4_pri$next[7:0]$14975 - assign $0\xive5_pri$next[7:0]$14912 $4\xive5_pri$next[7:0]$14976 - assign $0\xive6_pri$next[7:0]$14913 $4\xive6_pri$next[7:0]$14977 - assign $0\xive7_pri$next[7:0]$14914 $4\xive7_pri$next[7:0]$14978 - assign $0\xive8_pri$next[7:0]$14915 $4\xive8_pri$next[7:0]$14979 - assign $0\xive9_pri$next[7:0]$14916 $4\xive9_pri$next[7:0]$14980 - attribute \src "libresoc.v:202112.5-202112.29" + assign $0\xive0_pri$next[7:0]$14887 $4\xive0_pri$next[7:0]$14951 + assign $0\xive10_pri$next[7:0]$14888 $4\xive10_pri$next[7:0]$14952 + assign $0\xive11_pri$next[7:0]$14889 $4\xive11_pri$next[7:0]$14953 + assign $0\xive12_pri$next[7:0]$14890 $4\xive12_pri$next[7:0]$14954 + assign $0\xive13_pri$next[7:0]$14891 $4\xive13_pri$next[7:0]$14955 + assign $0\xive14_pri$next[7:0]$14892 $4\xive14_pri$next[7:0]$14956 + assign $0\xive15_pri$next[7:0]$14893 $4\xive15_pri$next[7:0]$14957 + assign $0\xive1_pri$next[7:0]$14894 $4\xive1_pri$next[7:0]$14958 + assign $0\xive2_pri$next[7:0]$14895 $4\xive2_pri$next[7:0]$14959 + assign $0\xive3_pri$next[7:0]$14896 $4\xive3_pri$next[7:0]$14960 + assign $0\xive4_pri$next[7:0]$14897 $4\xive4_pri$next[7:0]$14961 + assign $0\xive5_pri$next[7:0]$14898 $4\xive5_pri$next[7:0]$14962 + assign $0\xive6_pri$next[7:0]$14899 $4\xive6_pri$next[7:0]$14963 + assign $0\xive7_pri$next[7:0]$14900 $4\xive7_pri$next[7:0]$14964 + assign $0\xive8_pri$next[7:0]$14901 $4\xive8_pri$next[7:0]$14965 + assign $0\xive9_pri$next[7:0]$14902 $4\xive9_pri$next[7:0]$14966 + attribute \src "libresoc.v:204804.5-204804.29" switch \initial - attribute \src "libresoc.v:202112.9-202112.17" + attribute \src "libresoc.v:204804.9-204804.17" case 1'1 case end @@ -421137,22 +394157,22 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $1\xive0_pri$next[7:0]$14917 $2\xive0_pri$next[7:0]$14933 - assign $1\xive10_pri$next[7:0]$14918 $2\xive10_pri$next[7:0]$14934 - assign $1\xive11_pri$next[7:0]$14919 $2\xive11_pri$next[7:0]$14935 - assign $1\xive12_pri$next[7:0]$14920 $2\xive12_pri$next[7:0]$14936 - assign $1\xive13_pri$next[7:0]$14921 $2\xive13_pri$next[7:0]$14937 - assign $1\xive14_pri$next[7:0]$14922 $2\xive14_pri$next[7:0]$14938 - assign $1\xive15_pri$next[7:0]$14923 $2\xive15_pri$next[7:0]$14939 - assign $1\xive1_pri$next[7:0]$14924 $2\xive1_pri$next[7:0]$14940 - assign $1\xive2_pri$next[7:0]$14925 $2\xive2_pri$next[7:0]$14941 - assign $1\xive3_pri$next[7:0]$14926 $2\xive3_pri$next[7:0]$14942 - assign $1\xive4_pri$next[7:0]$14927 $2\xive4_pri$next[7:0]$14943 - assign $1\xive5_pri$next[7:0]$14928 $2\xive5_pri$next[7:0]$14944 - assign $1\xive6_pri$next[7:0]$14929 $2\xive6_pri$next[7:0]$14945 - assign $1\xive7_pri$next[7:0]$14930 $2\xive7_pri$next[7:0]$14946 - assign $1\xive8_pri$next[7:0]$14931 $2\xive8_pri$next[7:0]$14947 - assign $1\xive9_pri$next[7:0]$14932 $2\xive9_pri$next[7:0]$14948 + assign $1\xive0_pri$next[7:0]$14903 $2\xive0_pri$next[7:0]$14919 + assign $1\xive10_pri$next[7:0]$14904 $2\xive10_pri$next[7:0]$14920 + assign $1\xive11_pri$next[7:0]$14905 $2\xive11_pri$next[7:0]$14921 + assign $1\xive12_pri$next[7:0]$14906 $2\xive12_pri$next[7:0]$14922 + assign $1\xive13_pri$next[7:0]$14907 $2\xive13_pri$next[7:0]$14923 + assign $1\xive14_pri$next[7:0]$14908 $2\xive14_pri$next[7:0]$14924 + assign $1\xive15_pri$next[7:0]$14909 $2\xive15_pri$next[7:0]$14925 + assign $1\xive1_pri$next[7:0]$14910 $2\xive1_pri$next[7:0]$14926 + assign $1\xive2_pri$next[7:0]$14911 $2\xive2_pri$next[7:0]$14927 + assign $1\xive3_pri$next[7:0]$14912 $2\xive3_pri$next[7:0]$14928 + assign $1\xive4_pri$next[7:0]$14913 $2\xive4_pri$next[7:0]$14929 + assign $1\xive5_pri$next[7:0]$14914 $2\xive5_pri$next[7:0]$14930 + assign $1\xive6_pri$next[7:0]$14915 $2\xive6_pri$next[7:0]$14931 + assign $1\xive7_pri$next[7:0]$14916 $2\xive7_pri$next[7:0]$14932 + assign $1\xive8_pri$next[7:0]$14917 $2\xive8_pri$next[7:0]$14933 + assign $1\xive9_pri$next[7:0]$14918 $2\xive9_pri$next[7:0]$14934 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:342" switch \reg_is_xive attribute \src "libresoc.v:0.0-0.0" @@ -421173,381 +394193,381 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $2\xive0_pri$next[7:0]$14933 $3\xive0_pri$next[7:0]$14949 - assign $2\xive10_pri$next[7:0]$14934 $3\xive10_pri$next[7:0]$14950 - assign $2\xive11_pri$next[7:0]$14935 $3\xive11_pri$next[7:0]$14951 - assign $2\xive12_pri$next[7:0]$14936 $3\xive12_pri$next[7:0]$14952 - assign $2\xive13_pri$next[7:0]$14937 $3\xive13_pri$next[7:0]$14953 - assign $2\xive14_pri$next[7:0]$14938 $3\xive14_pri$next[7:0]$14954 - assign $2\xive15_pri$next[7:0]$14939 $3\xive15_pri$next[7:0]$14955 - assign $2\xive1_pri$next[7:0]$14940 $3\xive1_pri$next[7:0]$14956 - assign $2\xive2_pri$next[7:0]$14941 $3\xive2_pri$next[7:0]$14957 - assign $2\xive3_pri$next[7:0]$14942 $3\xive3_pri$next[7:0]$14958 - assign $2\xive4_pri$next[7:0]$14943 $3\xive4_pri$next[7:0]$14959 - assign $2\xive5_pri$next[7:0]$14944 $3\xive5_pri$next[7:0]$14960 - assign $2\xive6_pri$next[7:0]$14945 $3\xive6_pri$next[7:0]$14961 - assign $2\xive7_pri$next[7:0]$14946 $3\xive7_pri$next[7:0]$14962 - assign $2\xive8_pri$next[7:0]$14947 $3\xive8_pri$next[7:0]$14963 - assign $2\xive9_pri$next[7:0]$14948 $3\xive9_pri$next[7:0]$14964 + assign $2\xive0_pri$next[7:0]$14919 $3\xive0_pri$next[7:0]$14935 + assign $2\xive10_pri$next[7:0]$14920 $3\xive10_pri$next[7:0]$14936 + assign $2\xive11_pri$next[7:0]$14921 $3\xive11_pri$next[7:0]$14937 + assign $2\xive12_pri$next[7:0]$14922 $3\xive12_pri$next[7:0]$14938 + assign $2\xive13_pri$next[7:0]$14923 $3\xive13_pri$next[7:0]$14939 + assign $2\xive14_pri$next[7:0]$14924 $3\xive14_pri$next[7:0]$14940 + assign $2\xive15_pri$next[7:0]$14925 $3\xive15_pri$next[7:0]$14941 + assign $2\xive1_pri$next[7:0]$14926 $3\xive1_pri$next[7:0]$14942 + assign $2\xive2_pri$next[7:0]$14927 $3\xive2_pri$next[7:0]$14943 + assign $2\xive3_pri$next[7:0]$14928 $3\xive3_pri$next[7:0]$14944 + assign $2\xive4_pri$next[7:0]$14929 $3\xive4_pri$next[7:0]$14945 + assign $2\xive5_pri$next[7:0]$14930 $3\xive5_pri$next[7:0]$14946 + assign $2\xive6_pri$next[7:0]$14931 $3\xive6_pri$next[7:0]$14947 + assign $2\xive7_pri$next[7:0]$14932 $3\xive7_pri$next[7:0]$14948 + assign $2\xive8_pri$next[7:0]$14933 $3\xive8_pri$next[7:0]$14949 + assign $2\xive9_pri$next[7:0]$14934 $3\xive9_pri$next[7:0]$14950 attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:345" switch \reg_idx attribute \src "libresoc.v:0.0-0.0" case 4'0000 assign { } { } - assign $3\xive10_pri$next[7:0]$14950 \xive10_pri - assign $3\xive11_pri$next[7:0]$14951 \xive11_pri - assign $3\xive12_pri$next[7:0]$14952 \xive12_pri - assign $3\xive13_pri$next[7:0]$14953 \xive13_pri - assign $3\xive14_pri$next[7:0]$14954 \xive14_pri - assign $3\xive15_pri$next[7:0]$14955 \xive15_pri - assign $3\xive1_pri$next[7:0]$14956 \xive1_pri - assign $3\xive2_pri$next[7:0]$14957 \xive2_pri - assign $3\xive3_pri$next[7:0]$14958 \xive3_pri - assign $3\xive4_pri$next[7:0]$14959 \xive4_pri - assign $3\xive5_pri$next[7:0]$14960 \xive5_pri - assign $3\xive6_pri$next[7:0]$14961 \xive6_pri - assign $3\xive7_pri$next[7:0]$14962 \xive7_pri - assign $3\xive8_pri$next[7:0]$14963 \xive8_pri - assign $3\xive9_pri$next[7:0]$14964 \xive9_pri - assign $3\xive0_pri$next[7:0]$14949 \be_in [7:0] + assign $3\xive10_pri$next[7:0]$14936 \xive10_pri + assign $3\xive11_pri$next[7:0]$14937 \xive11_pri + assign $3\xive12_pri$next[7:0]$14938 \xive12_pri + assign $3\xive13_pri$next[7:0]$14939 \xive13_pri + assign $3\xive14_pri$next[7:0]$14940 \xive14_pri + assign $3\xive15_pri$next[7:0]$14941 \xive15_pri + assign $3\xive1_pri$next[7:0]$14942 \xive1_pri + assign $3\xive2_pri$next[7:0]$14943 \xive2_pri + assign $3\xive3_pri$next[7:0]$14944 \xive3_pri + assign $3\xive4_pri$next[7:0]$14945 \xive4_pri + assign $3\xive5_pri$next[7:0]$14946 \xive5_pri + assign $3\xive6_pri$next[7:0]$14947 \xive6_pri + assign $3\xive7_pri$next[7:0]$14948 \xive7_pri + assign $3\xive8_pri$next[7:0]$14949 \xive8_pri + assign $3\xive9_pri$next[7:0]$14950 \xive9_pri + assign $3\xive0_pri$next[7:0]$14935 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0001 - assign $3\xive0_pri$next[7:0]$14949 \xive0_pri - assign $3\xive10_pri$next[7:0]$14950 \xive10_pri - assign $3\xive11_pri$next[7:0]$14951 \xive11_pri - assign $3\xive12_pri$next[7:0]$14952 \xive12_pri - assign $3\xive13_pri$next[7:0]$14953 \xive13_pri - assign $3\xive14_pri$next[7:0]$14954 \xive14_pri - assign $3\xive15_pri$next[7:0]$14955 \xive15_pri + assign $3\xive0_pri$next[7:0]$14935 \xive0_pri + assign $3\xive10_pri$next[7:0]$14936 \xive10_pri + assign $3\xive11_pri$next[7:0]$14937 \xive11_pri + assign $3\xive12_pri$next[7:0]$14938 \xive12_pri + assign $3\xive13_pri$next[7:0]$14939 \xive13_pri + assign $3\xive14_pri$next[7:0]$14940 \xive14_pri + assign $3\xive15_pri$next[7:0]$14941 \xive15_pri assign { } { } - assign $3\xive2_pri$next[7:0]$14957 \xive2_pri - assign $3\xive3_pri$next[7:0]$14958 \xive3_pri - assign $3\xive4_pri$next[7:0]$14959 \xive4_pri - assign $3\xive5_pri$next[7:0]$14960 \xive5_pri - assign $3\xive6_pri$next[7:0]$14961 \xive6_pri - assign $3\xive7_pri$next[7:0]$14962 \xive7_pri - assign $3\xive8_pri$next[7:0]$14963 \xive8_pri - assign $3\xive9_pri$next[7:0]$14964 \xive9_pri - assign $3\xive1_pri$next[7:0]$14956 \be_in [7:0] + assign $3\xive2_pri$next[7:0]$14943 \xive2_pri + assign $3\xive3_pri$next[7:0]$14944 \xive3_pri + assign $3\xive4_pri$next[7:0]$14945 \xive4_pri + assign $3\xive5_pri$next[7:0]$14946 \xive5_pri + assign $3\xive6_pri$next[7:0]$14947 \xive6_pri + assign $3\xive7_pri$next[7:0]$14948 \xive7_pri + assign $3\xive8_pri$next[7:0]$14949 \xive8_pri + assign $3\xive9_pri$next[7:0]$14950 \xive9_pri + assign $3\xive1_pri$next[7:0]$14942 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0010 - assign $3\xive0_pri$next[7:0]$14949 \xive0_pri - assign $3\xive10_pri$next[7:0]$14950 \xive10_pri - assign $3\xive11_pri$next[7:0]$14951 \xive11_pri - assign $3\xive12_pri$next[7:0]$14952 \xive12_pri - assign $3\xive13_pri$next[7:0]$14953 \xive13_pri - assign $3\xive14_pri$next[7:0]$14954 \xive14_pri - assign $3\xive15_pri$next[7:0]$14955 \xive15_pri - assign $3\xive1_pri$next[7:0]$14956 \xive1_pri + assign $3\xive0_pri$next[7:0]$14935 \xive0_pri + assign $3\xive10_pri$next[7:0]$14936 \xive10_pri + assign $3\xive11_pri$next[7:0]$14937 \xive11_pri + assign $3\xive12_pri$next[7:0]$14938 \xive12_pri + assign $3\xive13_pri$next[7:0]$14939 \xive13_pri + assign $3\xive14_pri$next[7:0]$14940 \xive14_pri + assign $3\xive15_pri$next[7:0]$14941 \xive15_pri + assign $3\xive1_pri$next[7:0]$14942 \xive1_pri assign { } { } - assign $3\xive3_pri$next[7:0]$14958 \xive3_pri - assign $3\xive4_pri$next[7:0]$14959 \xive4_pri - assign $3\xive5_pri$next[7:0]$14960 \xive5_pri - assign $3\xive6_pri$next[7:0]$14961 \xive6_pri - assign $3\xive7_pri$next[7:0]$14962 \xive7_pri - assign $3\xive8_pri$next[7:0]$14963 \xive8_pri - assign $3\xive9_pri$next[7:0]$14964 \xive9_pri - assign $3\xive2_pri$next[7:0]$14957 \be_in [7:0] + assign $3\xive3_pri$next[7:0]$14944 \xive3_pri + assign $3\xive4_pri$next[7:0]$14945 \xive4_pri + assign $3\xive5_pri$next[7:0]$14946 \xive5_pri + assign $3\xive6_pri$next[7:0]$14947 \xive6_pri + assign $3\xive7_pri$next[7:0]$14948 \xive7_pri + assign $3\xive8_pri$next[7:0]$14949 \xive8_pri + assign $3\xive9_pri$next[7:0]$14950 \xive9_pri + assign $3\xive2_pri$next[7:0]$14943 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0011 - assign $3\xive0_pri$next[7:0]$14949 \xive0_pri - assign $3\xive10_pri$next[7:0]$14950 \xive10_pri - assign $3\xive11_pri$next[7:0]$14951 \xive11_pri - assign $3\xive12_pri$next[7:0]$14952 \xive12_pri - assign $3\xive13_pri$next[7:0]$14953 \xive13_pri - assign $3\xive14_pri$next[7:0]$14954 \xive14_pri - assign $3\xive15_pri$next[7:0]$14955 \xive15_pri - assign $3\xive1_pri$next[7:0]$14956 \xive1_pri - assign $3\xive2_pri$next[7:0]$14957 \xive2_pri + assign $3\xive0_pri$next[7:0]$14935 \xive0_pri + assign $3\xive10_pri$next[7:0]$14936 \xive10_pri + assign $3\xive11_pri$next[7:0]$14937 \xive11_pri + assign $3\xive12_pri$next[7:0]$14938 \xive12_pri + assign $3\xive13_pri$next[7:0]$14939 \xive13_pri + assign $3\xive14_pri$next[7:0]$14940 \xive14_pri + assign $3\xive15_pri$next[7:0]$14941 \xive15_pri + assign $3\xive1_pri$next[7:0]$14942 \xive1_pri + assign $3\xive2_pri$next[7:0]$14943 \xive2_pri assign { } { } - assign $3\xive4_pri$next[7:0]$14959 \xive4_pri - assign $3\xive5_pri$next[7:0]$14960 \xive5_pri - assign $3\xive6_pri$next[7:0]$14961 \xive6_pri - assign $3\xive7_pri$next[7:0]$14962 \xive7_pri - assign $3\xive8_pri$next[7:0]$14963 \xive8_pri - assign $3\xive9_pri$next[7:0]$14964 \xive9_pri - assign $3\xive3_pri$next[7:0]$14958 \be_in [7:0] + assign $3\xive4_pri$next[7:0]$14945 \xive4_pri + assign $3\xive5_pri$next[7:0]$14946 \xive5_pri + assign $3\xive6_pri$next[7:0]$14947 \xive6_pri + assign $3\xive7_pri$next[7:0]$14948 \xive7_pri + assign $3\xive8_pri$next[7:0]$14949 \xive8_pri + assign $3\xive9_pri$next[7:0]$14950 \xive9_pri + assign $3\xive3_pri$next[7:0]$14944 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0100 - assign $3\xive0_pri$next[7:0]$14949 \xive0_pri - assign $3\xive10_pri$next[7:0]$14950 \xive10_pri - assign $3\xive11_pri$next[7:0]$14951 \xive11_pri - assign $3\xive12_pri$next[7:0]$14952 \xive12_pri - assign $3\xive13_pri$next[7:0]$14953 \xive13_pri - assign $3\xive14_pri$next[7:0]$14954 \xive14_pri - assign $3\xive15_pri$next[7:0]$14955 \xive15_pri - assign $3\xive1_pri$next[7:0]$14956 \xive1_pri - assign $3\xive2_pri$next[7:0]$14957 \xive2_pri - assign $3\xive3_pri$next[7:0]$14958 \xive3_pri + assign $3\xive0_pri$next[7:0]$14935 \xive0_pri + assign $3\xive10_pri$next[7:0]$14936 \xive10_pri + assign $3\xive11_pri$next[7:0]$14937 \xive11_pri + assign $3\xive12_pri$next[7:0]$14938 \xive12_pri + assign $3\xive13_pri$next[7:0]$14939 \xive13_pri + assign $3\xive14_pri$next[7:0]$14940 \xive14_pri + assign $3\xive15_pri$next[7:0]$14941 \xive15_pri + assign $3\xive1_pri$next[7:0]$14942 \xive1_pri + assign $3\xive2_pri$next[7:0]$14943 \xive2_pri + assign $3\xive3_pri$next[7:0]$14944 \xive3_pri assign { } { } - assign $3\xive5_pri$next[7:0]$14960 \xive5_pri - assign $3\xive6_pri$next[7:0]$14961 \xive6_pri - assign $3\xive7_pri$next[7:0]$14962 \xive7_pri - assign $3\xive8_pri$next[7:0]$14963 \xive8_pri - assign $3\xive9_pri$next[7:0]$14964 \xive9_pri - assign $3\xive4_pri$next[7:0]$14959 \be_in [7:0] + assign $3\xive5_pri$next[7:0]$14946 \xive5_pri + assign $3\xive6_pri$next[7:0]$14947 \xive6_pri + assign $3\xive7_pri$next[7:0]$14948 \xive7_pri + assign $3\xive8_pri$next[7:0]$14949 \xive8_pri + assign $3\xive9_pri$next[7:0]$14950 \xive9_pri + assign $3\xive4_pri$next[7:0]$14945 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0101 - assign $3\xive0_pri$next[7:0]$14949 \xive0_pri - assign $3\xive10_pri$next[7:0]$14950 \xive10_pri - assign $3\xive11_pri$next[7:0]$14951 \xive11_pri - assign $3\xive12_pri$next[7:0]$14952 \xive12_pri - assign $3\xive13_pri$next[7:0]$14953 \xive13_pri - assign $3\xive14_pri$next[7:0]$14954 \xive14_pri - assign $3\xive15_pri$next[7:0]$14955 \xive15_pri - assign $3\xive1_pri$next[7:0]$14956 \xive1_pri - assign $3\xive2_pri$next[7:0]$14957 \xive2_pri - assign $3\xive3_pri$next[7:0]$14958 \xive3_pri - assign $3\xive4_pri$next[7:0]$14959 \xive4_pri + assign $3\xive0_pri$next[7:0]$14935 \xive0_pri + assign $3\xive10_pri$next[7:0]$14936 \xive10_pri + assign $3\xive11_pri$next[7:0]$14937 \xive11_pri + assign $3\xive12_pri$next[7:0]$14938 \xive12_pri + assign $3\xive13_pri$next[7:0]$14939 \xive13_pri + assign $3\xive14_pri$next[7:0]$14940 \xive14_pri + assign $3\xive15_pri$next[7:0]$14941 \xive15_pri + assign $3\xive1_pri$next[7:0]$14942 \xive1_pri + assign $3\xive2_pri$next[7:0]$14943 \xive2_pri + assign $3\xive3_pri$next[7:0]$14944 \xive3_pri + assign $3\xive4_pri$next[7:0]$14945 \xive4_pri assign { } { } - assign $3\xive6_pri$next[7:0]$14961 \xive6_pri - assign $3\xive7_pri$next[7:0]$14962 \xive7_pri - assign $3\xive8_pri$next[7:0]$14963 \xive8_pri - assign $3\xive9_pri$next[7:0]$14964 \xive9_pri - assign $3\xive5_pri$next[7:0]$14960 \be_in [7:0] + assign $3\xive6_pri$next[7:0]$14947 \xive6_pri + assign $3\xive7_pri$next[7:0]$14948 \xive7_pri + assign $3\xive8_pri$next[7:0]$14949 \xive8_pri + assign $3\xive9_pri$next[7:0]$14950 \xive9_pri + assign $3\xive5_pri$next[7:0]$14946 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0110 - assign $3\xive0_pri$next[7:0]$14949 \xive0_pri - assign $3\xive10_pri$next[7:0]$14950 \xive10_pri - assign $3\xive11_pri$next[7:0]$14951 \xive11_pri - assign $3\xive12_pri$next[7:0]$14952 \xive12_pri - assign $3\xive13_pri$next[7:0]$14953 \xive13_pri - assign $3\xive14_pri$next[7:0]$14954 \xive14_pri - assign $3\xive15_pri$next[7:0]$14955 \xive15_pri - assign $3\xive1_pri$next[7:0]$14956 \xive1_pri - assign $3\xive2_pri$next[7:0]$14957 \xive2_pri - assign $3\xive3_pri$next[7:0]$14958 \xive3_pri - assign $3\xive4_pri$next[7:0]$14959 \xive4_pri - assign $3\xive5_pri$next[7:0]$14960 \xive5_pri + assign $3\xive0_pri$next[7:0]$14935 \xive0_pri + assign $3\xive10_pri$next[7:0]$14936 \xive10_pri + assign $3\xive11_pri$next[7:0]$14937 \xive11_pri + assign $3\xive12_pri$next[7:0]$14938 \xive12_pri + assign $3\xive13_pri$next[7:0]$14939 \xive13_pri + assign $3\xive14_pri$next[7:0]$14940 \xive14_pri + assign $3\xive15_pri$next[7:0]$14941 \xive15_pri + assign $3\xive1_pri$next[7:0]$14942 \xive1_pri + assign $3\xive2_pri$next[7:0]$14943 \xive2_pri + assign $3\xive3_pri$next[7:0]$14944 \xive3_pri + assign $3\xive4_pri$next[7:0]$14945 \xive4_pri + assign $3\xive5_pri$next[7:0]$14946 \xive5_pri assign { } { } - assign $3\xive7_pri$next[7:0]$14962 \xive7_pri - assign $3\xive8_pri$next[7:0]$14963 \xive8_pri - assign $3\xive9_pri$next[7:0]$14964 \xive9_pri - assign $3\xive6_pri$next[7:0]$14961 \be_in [7:0] + assign $3\xive7_pri$next[7:0]$14948 \xive7_pri + assign $3\xive8_pri$next[7:0]$14949 \xive8_pri + assign $3\xive9_pri$next[7:0]$14950 \xive9_pri + assign $3\xive6_pri$next[7:0]$14947 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'0111 - assign $3\xive0_pri$next[7:0]$14949 \xive0_pri - assign $3\xive10_pri$next[7:0]$14950 \xive10_pri - assign $3\xive11_pri$next[7:0]$14951 \xive11_pri - assign $3\xive12_pri$next[7:0]$14952 \xive12_pri - assign $3\xive13_pri$next[7:0]$14953 \xive13_pri - assign $3\xive14_pri$next[7:0]$14954 \xive14_pri - assign $3\xive15_pri$next[7:0]$14955 \xive15_pri - assign $3\xive1_pri$next[7:0]$14956 \xive1_pri - assign $3\xive2_pri$next[7:0]$14957 \xive2_pri - assign $3\xive3_pri$next[7:0]$14958 \xive3_pri - assign $3\xive4_pri$next[7:0]$14959 \xive4_pri - assign $3\xive5_pri$next[7:0]$14960 \xive5_pri - assign $3\xive6_pri$next[7:0]$14961 \xive6_pri + assign $3\xive0_pri$next[7:0]$14935 \xive0_pri + assign $3\xive10_pri$next[7:0]$14936 \xive10_pri + assign $3\xive11_pri$next[7:0]$14937 \xive11_pri + assign $3\xive12_pri$next[7:0]$14938 \xive12_pri + assign $3\xive13_pri$next[7:0]$14939 \xive13_pri + assign $3\xive14_pri$next[7:0]$14940 \xive14_pri + assign $3\xive15_pri$next[7:0]$14941 \xive15_pri + assign $3\xive1_pri$next[7:0]$14942 \xive1_pri + assign $3\xive2_pri$next[7:0]$14943 \xive2_pri + assign $3\xive3_pri$next[7:0]$14944 \xive3_pri + assign $3\xive4_pri$next[7:0]$14945 \xive4_pri + assign $3\xive5_pri$next[7:0]$14946 \xive5_pri + assign $3\xive6_pri$next[7:0]$14947 \xive6_pri assign { } { } - assign $3\xive8_pri$next[7:0]$14963 \xive8_pri - assign $3\xive9_pri$next[7:0]$14964 \xive9_pri - assign $3\xive7_pri$next[7:0]$14962 \be_in [7:0] + assign $3\xive8_pri$next[7:0]$14949 \xive8_pri + assign $3\xive9_pri$next[7:0]$14950 \xive9_pri + assign $3\xive7_pri$next[7:0]$14948 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1000 - assign $3\xive0_pri$next[7:0]$14949 \xive0_pri - assign $3\xive10_pri$next[7:0]$14950 \xive10_pri - assign $3\xive11_pri$next[7:0]$14951 \xive11_pri - assign $3\xive12_pri$next[7:0]$14952 \xive12_pri - assign $3\xive13_pri$next[7:0]$14953 \xive13_pri - assign $3\xive14_pri$next[7:0]$14954 \xive14_pri - assign $3\xive15_pri$next[7:0]$14955 \xive15_pri - assign $3\xive1_pri$next[7:0]$14956 \xive1_pri - assign $3\xive2_pri$next[7:0]$14957 \xive2_pri - assign $3\xive3_pri$next[7:0]$14958 \xive3_pri - assign $3\xive4_pri$next[7:0]$14959 \xive4_pri - assign $3\xive5_pri$next[7:0]$14960 \xive5_pri - assign $3\xive6_pri$next[7:0]$14961 \xive6_pri - assign $3\xive7_pri$next[7:0]$14962 \xive7_pri + assign $3\xive0_pri$next[7:0]$14935 \xive0_pri + assign $3\xive10_pri$next[7:0]$14936 \xive10_pri + assign $3\xive11_pri$next[7:0]$14937 \xive11_pri + assign $3\xive12_pri$next[7:0]$14938 \xive12_pri + assign $3\xive13_pri$next[7:0]$14939 \xive13_pri + assign $3\xive14_pri$next[7:0]$14940 \xive14_pri + assign $3\xive15_pri$next[7:0]$14941 \xive15_pri + assign $3\xive1_pri$next[7:0]$14942 \xive1_pri + assign $3\xive2_pri$next[7:0]$14943 \xive2_pri + assign $3\xive3_pri$next[7:0]$14944 \xive3_pri + assign $3\xive4_pri$next[7:0]$14945 \xive4_pri + assign $3\xive5_pri$next[7:0]$14946 \xive5_pri + assign $3\xive6_pri$next[7:0]$14947 \xive6_pri + assign $3\xive7_pri$next[7:0]$14948 \xive7_pri assign { } { } - assign $3\xive9_pri$next[7:0]$14964 \xive9_pri - assign $3\xive8_pri$next[7:0]$14963 \be_in [7:0] + assign $3\xive9_pri$next[7:0]$14950 \xive9_pri + assign $3\xive8_pri$next[7:0]$14949 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1001 - assign $3\xive0_pri$next[7:0]$14949 \xive0_pri - assign $3\xive10_pri$next[7:0]$14950 \xive10_pri - assign $3\xive11_pri$next[7:0]$14951 \xive11_pri - assign $3\xive12_pri$next[7:0]$14952 \xive12_pri - assign $3\xive13_pri$next[7:0]$14953 \xive13_pri - assign $3\xive14_pri$next[7:0]$14954 \xive14_pri - assign $3\xive15_pri$next[7:0]$14955 \xive15_pri - assign $3\xive1_pri$next[7:0]$14956 \xive1_pri - assign $3\xive2_pri$next[7:0]$14957 \xive2_pri - assign $3\xive3_pri$next[7:0]$14958 \xive3_pri - assign $3\xive4_pri$next[7:0]$14959 \xive4_pri - assign $3\xive5_pri$next[7:0]$14960 \xive5_pri - assign $3\xive6_pri$next[7:0]$14961 \xive6_pri - assign $3\xive7_pri$next[7:0]$14962 \xive7_pri - assign $3\xive8_pri$next[7:0]$14963 \xive8_pri + assign $3\xive0_pri$next[7:0]$14935 \xive0_pri + assign $3\xive10_pri$next[7:0]$14936 \xive10_pri + assign $3\xive11_pri$next[7:0]$14937 \xive11_pri + assign $3\xive12_pri$next[7:0]$14938 \xive12_pri + assign $3\xive13_pri$next[7:0]$14939 \xive13_pri + assign $3\xive14_pri$next[7:0]$14940 \xive14_pri + assign $3\xive15_pri$next[7:0]$14941 \xive15_pri + assign $3\xive1_pri$next[7:0]$14942 \xive1_pri + assign $3\xive2_pri$next[7:0]$14943 \xive2_pri + assign $3\xive3_pri$next[7:0]$14944 \xive3_pri + assign $3\xive4_pri$next[7:0]$14945 \xive4_pri + assign $3\xive5_pri$next[7:0]$14946 \xive5_pri + assign $3\xive6_pri$next[7:0]$14947 \xive6_pri + assign $3\xive7_pri$next[7:0]$14948 \xive7_pri + assign $3\xive8_pri$next[7:0]$14949 \xive8_pri assign { } { } - assign $3\xive9_pri$next[7:0]$14964 \be_in [7:0] + assign $3\xive9_pri$next[7:0]$14950 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1010 - assign $3\xive0_pri$next[7:0]$14949 \xive0_pri + assign $3\xive0_pri$next[7:0]$14935 \xive0_pri assign { } { } - assign $3\xive11_pri$next[7:0]$14951 \xive11_pri - assign $3\xive12_pri$next[7:0]$14952 \xive12_pri - assign $3\xive13_pri$next[7:0]$14953 \xive13_pri - assign $3\xive14_pri$next[7:0]$14954 \xive14_pri - assign $3\xive15_pri$next[7:0]$14955 \xive15_pri - assign $3\xive1_pri$next[7:0]$14956 \xive1_pri - assign $3\xive2_pri$next[7:0]$14957 \xive2_pri - assign $3\xive3_pri$next[7:0]$14958 \xive3_pri - assign $3\xive4_pri$next[7:0]$14959 \xive4_pri - assign $3\xive5_pri$next[7:0]$14960 \xive5_pri - assign $3\xive6_pri$next[7:0]$14961 \xive6_pri - assign $3\xive7_pri$next[7:0]$14962 \xive7_pri - assign $3\xive8_pri$next[7:0]$14963 \xive8_pri - assign $3\xive9_pri$next[7:0]$14964 \xive9_pri - assign $3\xive10_pri$next[7:0]$14950 \be_in [7:0] + assign $3\xive11_pri$next[7:0]$14937 \xive11_pri + assign $3\xive12_pri$next[7:0]$14938 \xive12_pri + assign $3\xive13_pri$next[7:0]$14939 \xive13_pri + assign $3\xive14_pri$next[7:0]$14940 \xive14_pri + assign $3\xive15_pri$next[7:0]$14941 \xive15_pri + assign $3\xive1_pri$next[7:0]$14942 \xive1_pri + assign $3\xive2_pri$next[7:0]$14943 \xive2_pri + assign $3\xive3_pri$next[7:0]$14944 \xive3_pri + assign $3\xive4_pri$next[7:0]$14945 \xive4_pri + assign $3\xive5_pri$next[7:0]$14946 \xive5_pri + assign $3\xive6_pri$next[7:0]$14947 \xive6_pri + assign $3\xive7_pri$next[7:0]$14948 \xive7_pri + assign $3\xive8_pri$next[7:0]$14949 \xive8_pri + assign $3\xive9_pri$next[7:0]$14950 \xive9_pri + assign $3\xive10_pri$next[7:0]$14936 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1011 - assign $3\xive0_pri$next[7:0]$14949 \xive0_pri - assign $3\xive10_pri$next[7:0]$14950 \xive10_pri + assign $3\xive0_pri$next[7:0]$14935 \xive0_pri + assign $3\xive10_pri$next[7:0]$14936 \xive10_pri assign { } { } - assign $3\xive12_pri$next[7:0]$14952 \xive12_pri - assign $3\xive13_pri$next[7:0]$14953 \xive13_pri - assign $3\xive14_pri$next[7:0]$14954 \xive14_pri - assign $3\xive15_pri$next[7:0]$14955 \xive15_pri - assign $3\xive1_pri$next[7:0]$14956 \xive1_pri - assign $3\xive2_pri$next[7:0]$14957 \xive2_pri - assign $3\xive3_pri$next[7:0]$14958 \xive3_pri - assign $3\xive4_pri$next[7:0]$14959 \xive4_pri - assign $3\xive5_pri$next[7:0]$14960 \xive5_pri - assign $3\xive6_pri$next[7:0]$14961 \xive6_pri - assign $3\xive7_pri$next[7:0]$14962 \xive7_pri - assign $3\xive8_pri$next[7:0]$14963 \xive8_pri - assign $3\xive9_pri$next[7:0]$14964 \xive9_pri - assign $3\xive11_pri$next[7:0]$14951 \be_in [7:0] + assign $3\xive12_pri$next[7:0]$14938 \xive12_pri + assign $3\xive13_pri$next[7:0]$14939 \xive13_pri + assign $3\xive14_pri$next[7:0]$14940 \xive14_pri + assign $3\xive15_pri$next[7:0]$14941 \xive15_pri + assign $3\xive1_pri$next[7:0]$14942 \xive1_pri + assign $3\xive2_pri$next[7:0]$14943 \xive2_pri + assign $3\xive3_pri$next[7:0]$14944 \xive3_pri + assign $3\xive4_pri$next[7:0]$14945 \xive4_pri + assign $3\xive5_pri$next[7:0]$14946 \xive5_pri + assign $3\xive6_pri$next[7:0]$14947 \xive6_pri + assign $3\xive7_pri$next[7:0]$14948 \xive7_pri + assign $3\xive8_pri$next[7:0]$14949 \xive8_pri + assign $3\xive9_pri$next[7:0]$14950 \xive9_pri + assign $3\xive11_pri$next[7:0]$14937 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1100 - assign $3\xive0_pri$next[7:0]$14949 \xive0_pri - assign $3\xive10_pri$next[7:0]$14950 \xive10_pri - assign $3\xive11_pri$next[7:0]$14951 \xive11_pri + assign $3\xive0_pri$next[7:0]$14935 \xive0_pri + assign $3\xive10_pri$next[7:0]$14936 \xive10_pri + assign $3\xive11_pri$next[7:0]$14937 \xive11_pri assign { } { } - assign $3\xive13_pri$next[7:0]$14953 \xive13_pri - assign $3\xive14_pri$next[7:0]$14954 \xive14_pri - assign $3\xive15_pri$next[7:0]$14955 \xive15_pri - assign $3\xive1_pri$next[7:0]$14956 \xive1_pri - assign $3\xive2_pri$next[7:0]$14957 \xive2_pri - assign $3\xive3_pri$next[7:0]$14958 \xive3_pri - assign $3\xive4_pri$next[7:0]$14959 \xive4_pri - assign $3\xive5_pri$next[7:0]$14960 \xive5_pri - assign $3\xive6_pri$next[7:0]$14961 \xive6_pri - assign $3\xive7_pri$next[7:0]$14962 \xive7_pri - assign $3\xive8_pri$next[7:0]$14963 \xive8_pri - assign $3\xive9_pri$next[7:0]$14964 \xive9_pri - assign $3\xive12_pri$next[7:0]$14952 \be_in [7:0] + assign $3\xive13_pri$next[7:0]$14939 \xive13_pri + assign $3\xive14_pri$next[7:0]$14940 \xive14_pri + assign $3\xive15_pri$next[7:0]$14941 \xive15_pri + assign $3\xive1_pri$next[7:0]$14942 \xive1_pri + assign $3\xive2_pri$next[7:0]$14943 \xive2_pri + assign $3\xive3_pri$next[7:0]$14944 \xive3_pri + assign $3\xive4_pri$next[7:0]$14945 \xive4_pri + assign $3\xive5_pri$next[7:0]$14946 \xive5_pri + assign $3\xive6_pri$next[7:0]$14947 \xive6_pri + assign $3\xive7_pri$next[7:0]$14948 \xive7_pri + assign $3\xive8_pri$next[7:0]$14949 \xive8_pri + assign $3\xive9_pri$next[7:0]$14950 \xive9_pri + assign $3\xive12_pri$next[7:0]$14938 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1101 - assign $3\xive0_pri$next[7:0]$14949 \xive0_pri - assign $3\xive10_pri$next[7:0]$14950 \xive10_pri - assign $3\xive11_pri$next[7:0]$14951 \xive11_pri - assign $3\xive12_pri$next[7:0]$14952 \xive12_pri + assign $3\xive0_pri$next[7:0]$14935 \xive0_pri + assign $3\xive10_pri$next[7:0]$14936 \xive10_pri + assign $3\xive11_pri$next[7:0]$14937 \xive11_pri + assign $3\xive12_pri$next[7:0]$14938 \xive12_pri assign { } { } - assign $3\xive14_pri$next[7:0]$14954 \xive14_pri - assign $3\xive15_pri$next[7:0]$14955 \xive15_pri - assign $3\xive1_pri$next[7:0]$14956 \xive1_pri - assign $3\xive2_pri$next[7:0]$14957 \xive2_pri - assign $3\xive3_pri$next[7:0]$14958 \xive3_pri - assign $3\xive4_pri$next[7:0]$14959 \xive4_pri - assign $3\xive5_pri$next[7:0]$14960 \xive5_pri - assign $3\xive6_pri$next[7:0]$14961 \xive6_pri - assign $3\xive7_pri$next[7:0]$14962 \xive7_pri - assign $3\xive8_pri$next[7:0]$14963 \xive8_pri - assign $3\xive9_pri$next[7:0]$14964 \xive9_pri - assign $3\xive13_pri$next[7:0]$14953 \be_in [7:0] + assign $3\xive14_pri$next[7:0]$14940 \xive14_pri + assign $3\xive15_pri$next[7:0]$14941 \xive15_pri + assign $3\xive1_pri$next[7:0]$14942 \xive1_pri + assign $3\xive2_pri$next[7:0]$14943 \xive2_pri + assign $3\xive3_pri$next[7:0]$14944 \xive3_pri + assign $3\xive4_pri$next[7:0]$14945 \xive4_pri + assign $3\xive5_pri$next[7:0]$14946 \xive5_pri + assign $3\xive6_pri$next[7:0]$14947 \xive6_pri + assign $3\xive7_pri$next[7:0]$14948 \xive7_pri + assign $3\xive8_pri$next[7:0]$14949 \xive8_pri + assign $3\xive9_pri$next[7:0]$14950 \xive9_pri + assign $3\xive13_pri$next[7:0]$14939 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'1110 - assign $3\xive0_pri$next[7:0]$14949 \xive0_pri - assign $3\xive10_pri$next[7:0]$14950 \xive10_pri - assign $3\xive11_pri$next[7:0]$14951 \xive11_pri - assign $3\xive12_pri$next[7:0]$14952 \xive12_pri - assign $3\xive13_pri$next[7:0]$14953 \xive13_pri + assign $3\xive0_pri$next[7:0]$14935 \xive0_pri + assign $3\xive10_pri$next[7:0]$14936 \xive10_pri + assign $3\xive11_pri$next[7:0]$14937 \xive11_pri + assign $3\xive12_pri$next[7:0]$14938 \xive12_pri + assign $3\xive13_pri$next[7:0]$14939 \xive13_pri assign { } { } - assign $3\xive15_pri$next[7:0]$14955 \xive15_pri - assign $3\xive1_pri$next[7:0]$14956 \xive1_pri - assign $3\xive2_pri$next[7:0]$14957 \xive2_pri - assign $3\xive3_pri$next[7:0]$14958 \xive3_pri - assign $3\xive4_pri$next[7:0]$14959 \xive4_pri - assign $3\xive5_pri$next[7:0]$14960 \xive5_pri - assign $3\xive6_pri$next[7:0]$14961 \xive6_pri - assign $3\xive7_pri$next[7:0]$14962 \xive7_pri - assign $3\xive8_pri$next[7:0]$14963 \xive8_pri - assign $3\xive9_pri$next[7:0]$14964 \xive9_pri - assign $3\xive14_pri$next[7:0]$14954 \be_in [7:0] + assign $3\xive15_pri$next[7:0]$14941 \xive15_pri + assign $3\xive1_pri$next[7:0]$14942 \xive1_pri + assign $3\xive2_pri$next[7:0]$14943 \xive2_pri + assign $3\xive3_pri$next[7:0]$14944 \xive3_pri + assign $3\xive4_pri$next[7:0]$14945 \xive4_pri + assign $3\xive5_pri$next[7:0]$14946 \xive5_pri + assign $3\xive6_pri$next[7:0]$14947 \xive6_pri + assign $3\xive7_pri$next[7:0]$14948 \xive7_pri + assign $3\xive8_pri$next[7:0]$14949 \xive8_pri + assign $3\xive9_pri$next[7:0]$14950 \xive9_pri + assign $3\xive14_pri$next[7:0]$14940 \be_in [7:0] attribute \src "libresoc.v:0.0-0.0" case 4'---- - assign $3\xive0_pri$next[7:0]$14949 \xive0_pri - assign $3\xive10_pri$next[7:0]$14950 \xive10_pri - assign $3\xive11_pri$next[7:0]$14951 \xive11_pri - assign $3\xive12_pri$next[7:0]$14952 \xive12_pri - assign $3\xive13_pri$next[7:0]$14953 \xive13_pri - assign $3\xive14_pri$next[7:0]$14954 \xive14_pri + assign $3\xive0_pri$next[7:0]$14935 \xive0_pri + assign $3\xive10_pri$next[7:0]$14936 \xive10_pri + assign $3\xive11_pri$next[7:0]$14937 \xive11_pri + assign $3\xive12_pri$next[7:0]$14938 \xive12_pri + assign $3\xive13_pri$next[7:0]$14939 \xive13_pri + assign $3\xive14_pri$next[7:0]$14940 \xive14_pri assign { } { } - assign $3\xive1_pri$next[7:0]$14956 \xive1_pri - assign $3\xive2_pri$next[7:0]$14957 \xive2_pri - assign $3\xive3_pri$next[7:0]$14958 \xive3_pri - assign $3\xive4_pri$next[7:0]$14959 \xive4_pri - assign $3\xive5_pri$next[7:0]$14960 \xive5_pri - assign $3\xive6_pri$next[7:0]$14961 \xive6_pri - assign $3\xive7_pri$next[7:0]$14962 \xive7_pri - assign $3\xive8_pri$next[7:0]$14963 \xive8_pri - assign $3\xive9_pri$next[7:0]$14964 \xive9_pri - assign $3\xive15_pri$next[7:0]$14955 \be_in [7:0] + assign $3\xive1_pri$next[7:0]$14942 \xive1_pri + assign $3\xive2_pri$next[7:0]$14943 \xive2_pri + assign $3\xive3_pri$next[7:0]$14944 \xive3_pri + assign $3\xive4_pri$next[7:0]$14945 \xive4_pri + assign $3\xive5_pri$next[7:0]$14946 \xive5_pri + assign $3\xive6_pri$next[7:0]$14947 \xive6_pri + assign $3\xive7_pri$next[7:0]$14948 \xive7_pri + assign $3\xive8_pri$next[7:0]$14949 \xive8_pri + assign $3\xive9_pri$next[7:0]$14950 \xive9_pri + assign $3\xive15_pri$next[7:0]$14941 \be_in [7:0] case - assign $3\xive0_pri$next[7:0]$14949 \xive0_pri - assign $3\xive10_pri$next[7:0]$14950 \xive10_pri - assign $3\xive11_pri$next[7:0]$14951 \xive11_pri - assign $3\xive12_pri$next[7:0]$14952 \xive12_pri - assign $3\xive13_pri$next[7:0]$14953 \xive13_pri - assign $3\xive14_pri$next[7:0]$14954 \xive14_pri - assign $3\xive15_pri$next[7:0]$14955 \xive15_pri - assign $3\xive1_pri$next[7:0]$14956 \xive1_pri - assign $3\xive2_pri$next[7:0]$14957 \xive2_pri - assign $3\xive3_pri$next[7:0]$14958 \xive3_pri - assign $3\xive4_pri$next[7:0]$14959 \xive4_pri - assign $3\xive5_pri$next[7:0]$14960 \xive5_pri - assign $3\xive6_pri$next[7:0]$14961 \xive6_pri - assign $3\xive7_pri$next[7:0]$14962 \xive7_pri - assign $3\xive8_pri$next[7:0]$14963 \xive8_pri - assign $3\xive9_pri$next[7:0]$14964 \xive9_pri + assign $3\xive0_pri$next[7:0]$14935 \xive0_pri + assign $3\xive10_pri$next[7:0]$14936 \xive10_pri + assign $3\xive11_pri$next[7:0]$14937 \xive11_pri + assign $3\xive12_pri$next[7:0]$14938 \xive12_pri + assign $3\xive13_pri$next[7:0]$14939 \xive13_pri + assign $3\xive14_pri$next[7:0]$14940 \xive14_pri + assign $3\xive15_pri$next[7:0]$14941 \xive15_pri + assign $3\xive1_pri$next[7:0]$14942 \xive1_pri + assign $3\xive2_pri$next[7:0]$14943 \xive2_pri + assign $3\xive3_pri$next[7:0]$14944 \xive3_pri + assign $3\xive4_pri$next[7:0]$14945 \xive4_pri + assign $3\xive5_pri$next[7:0]$14946 \xive5_pri + assign $3\xive6_pri$next[7:0]$14947 \xive6_pri + assign $3\xive7_pri$next[7:0]$14948 \xive7_pri + assign $3\xive8_pri$next[7:0]$14949 \xive8_pri + assign $3\xive9_pri$next[7:0]$14950 \xive9_pri end case - assign $2\xive0_pri$next[7:0]$14933 \xive0_pri - assign $2\xive10_pri$next[7:0]$14934 \xive10_pri - assign $2\xive11_pri$next[7:0]$14935 \xive11_pri - assign $2\xive12_pri$next[7:0]$14936 \xive12_pri - assign $2\xive13_pri$next[7:0]$14937 \xive13_pri - assign $2\xive14_pri$next[7:0]$14938 \xive14_pri - assign $2\xive15_pri$next[7:0]$14939 \xive15_pri - assign $2\xive1_pri$next[7:0]$14940 \xive1_pri - assign $2\xive2_pri$next[7:0]$14941 \xive2_pri - assign $2\xive3_pri$next[7:0]$14942 \xive3_pri - assign $2\xive4_pri$next[7:0]$14943 \xive4_pri - assign $2\xive5_pri$next[7:0]$14944 \xive5_pri - assign $2\xive6_pri$next[7:0]$14945 \xive6_pri - assign $2\xive7_pri$next[7:0]$14946 \xive7_pri - assign $2\xive8_pri$next[7:0]$14947 \xive8_pri - assign $2\xive9_pri$next[7:0]$14948 \xive9_pri - end - case - assign $1\xive0_pri$next[7:0]$14917 \xive0_pri - assign $1\xive10_pri$next[7:0]$14918 \xive10_pri - assign $1\xive11_pri$next[7:0]$14919 \xive11_pri - assign $1\xive12_pri$next[7:0]$14920 \xive12_pri - assign $1\xive13_pri$next[7:0]$14921 \xive13_pri - assign $1\xive14_pri$next[7:0]$14922 \xive14_pri - assign $1\xive15_pri$next[7:0]$14923 \xive15_pri - assign $1\xive1_pri$next[7:0]$14924 \xive1_pri - assign $1\xive2_pri$next[7:0]$14925 \xive2_pri - assign $1\xive3_pri$next[7:0]$14926 \xive3_pri - assign $1\xive4_pri$next[7:0]$14927 \xive4_pri - assign $1\xive5_pri$next[7:0]$14928 \xive5_pri - assign $1\xive6_pri$next[7:0]$14929 \xive6_pri - assign $1\xive7_pri$next[7:0]$14930 \xive7_pri - assign $1\xive8_pri$next[7:0]$14931 \xive8_pri - assign $1\xive9_pri$next[7:0]$14932 \xive9_pri + assign $2\xive0_pri$next[7:0]$14919 \xive0_pri + assign $2\xive10_pri$next[7:0]$14920 \xive10_pri + assign $2\xive11_pri$next[7:0]$14921 \xive11_pri + assign $2\xive12_pri$next[7:0]$14922 \xive12_pri + assign $2\xive13_pri$next[7:0]$14923 \xive13_pri + assign $2\xive14_pri$next[7:0]$14924 \xive14_pri + assign $2\xive15_pri$next[7:0]$14925 \xive15_pri + assign $2\xive1_pri$next[7:0]$14926 \xive1_pri + assign $2\xive2_pri$next[7:0]$14927 \xive2_pri + assign $2\xive3_pri$next[7:0]$14928 \xive3_pri + assign $2\xive4_pri$next[7:0]$14929 \xive4_pri + assign $2\xive5_pri$next[7:0]$14930 \xive5_pri + assign $2\xive6_pri$next[7:0]$14931 \xive6_pri + assign $2\xive7_pri$next[7:0]$14932 \xive7_pri + assign $2\xive8_pri$next[7:0]$14933 \xive8_pri + assign $2\xive9_pri$next[7:0]$14934 \xive9_pri + end + case + assign $1\xive0_pri$next[7:0]$14903 \xive0_pri + assign $1\xive10_pri$next[7:0]$14904 \xive10_pri + assign $1\xive11_pri$next[7:0]$14905 \xive11_pri + assign $1\xive12_pri$next[7:0]$14906 \xive12_pri + assign $1\xive13_pri$next[7:0]$14907 \xive13_pri + assign $1\xive14_pri$next[7:0]$14908 \xive14_pri + assign $1\xive15_pri$next[7:0]$14909 \xive15_pri + assign $1\xive1_pri$next[7:0]$14910 \xive1_pri + assign $1\xive2_pri$next[7:0]$14911 \xive2_pri + assign $1\xive3_pri$next[7:0]$14912 \xive3_pri + assign $1\xive4_pri$next[7:0]$14913 \xive4_pri + assign $1\xive5_pri$next[7:0]$14914 \xive5_pri + assign $1\xive6_pri$next[7:0]$14915 \xive6_pri + assign $1\xive7_pri$next[7:0]$14916 \xive7_pri + assign $1\xive8_pri$next[7:0]$14917 \xive8_pri + assign $1\xive9_pri$next[7:0]$14918 \xive9_pri end attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" switch \rst @@ -421569,66 +394589,66 @@ module \xics_ics assign { } { } assign { } { } assign { } { } - assign $4\xive0_pri$next[7:0]$14965 8'11111111 - assign $4\xive1_pri$next[7:0]$14972 8'11111111 - assign $4\xive2_pri$next[7:0]$14973 8'11111111 - assign $4\xive3_pri$next[7:0]$14974 8'11111111 - assign $4\xive4_pri$next[7:0]$14975 8'11111111 - assign $4\xive5_pri$next[7:0]$14976 8'11111111 - assign $4\xive6_pri$next[7:0]$14977 8'11111111 - assign $4\xive7_pri$next[7:0]$14978 8'11111111 - assign $4\xive8_pri$next[7:0]$14979 8'11111111 - assign $4\xive9_pri$next[7:0]$14980 8'11111111 - assign $4\xive10_pri$next[7:0]$14966 8'11111111 - assign $4\xive11_pri$next[7:0]$14967 8'11111111 - assign $4\xive12_pri$next[7:0]$14968 8'11111111 - assign $4\xive13_pri$next[7:0]$14969 8'11111111 - assign $4\xive14_pri$next[7:0]$14970 8'11111111 - assign $4\xive15_pri$next[7:0]$14971 8'11111111 + assign $4\xive0_pri$next[7:0]$14951 8'11111111 + assign $4\xive1_pri$next[7:0]$14958 8'11111111 + assign $4\xive2_pri$next[7:0]$14959 8'11111111 + assign $4\xive3_pri$next[7:0]$14960 8'11111111 + assign $4\xive4_pri$next[7:0]$14961 8'11111111 + assign $4\xive5_pri$next[7:0]$14962 8'11111111 + assign $4\xive6_pri$next[7:0]$14963 8'11111111 + assign $4\xive7_pri$next[7:0]$14964 8'11111111 + assign $4\xive8_pri$next[7:0]$14965 8'11111111 + assign $4\xive9_pri$next[7:0]$14966 8'11111111 + assign $4\xive10_pri$next[7:0]$14952 8'11111111 + assign $4\xive11_pri$next[7:0]$14953 8'11111111 + assign $4\xive12_pri$next[7:0]$14954 8'11111111 + assign $4\xive13_pri$next[7:0]$14955 8'11111111 + assign $4\xive14_pri$next[7:0]$14956 8'11111111 + assign $4\xive15_pri$next[7:0]$14957 8'11111111 case - assign $4\xive0_pri$next[7:0]$14965 $1\xive0_pri$next[7:0]$14917 - assign $4\xive10_pri$next[7:0]$14966 $1\xive10_pri$next[7:0]$14918 - assign $4\xive11_pri$next[7:0]$14967 $1\xive11_pri$next[7:0]$14919 - assign $4\xive12_pri$next[7:0]$14968 $1\xive12_pri$next[7:0]$14920 - assign $4\xive13_pri$next[7:0]$14969 $1\xive13_pri$next[7:0]$14921 - assign $4\xive14_pri$next[7:0]$14970 $1\xive14_pri$next[7:0]$14922 - assign $4\xive15_pri$next[7:0]$14971 $1\xive15_pri$next[7:0]$14923 - assign $4\xive1_pri$next[7:0]$14972 $1\xive1_pri$next[7:0]$14924 - assign $4\xive2_pri$next[7:0]$14973 $1\xive2_pri$next[7:0]$14925 - assign $4\xive3_pri$next[7:0]$14974 $1\xive3_pri$next[7:0]$14926 - assign $4\xive4_pri$next[7:0]$14975 $1\xive4_pri$next[7:0]$14927 - assign $4\xive5_pri$next[7:0]$14976 $1\xive5_pri$next[7:0]$14928 - assign $4\xive6_pri$next[7:0]$14977 $1\xive6_pri$next[7:0]$14929 - assign $4\xive7_pri$next[7:0]$14978 $1\xive7_pri$next[7:0]$14930 - assign $4\xive8_pri$next[7:0]$14979 $1\xive8_pri$next[7:0]$14931 - assign $4\xive9_pri$next[7:0]$14980 $1\xive9_pri$next[7:0]$14932 + assign $4\xive0_pri$next[7:0]$14951 $1\xive0_pri$next[7:0]$14903 + assign $4\xive10_pri$next[7:0]$14952 $1\xive10_pri$next[7:0]$14904 + assign $4\xive11_pri$next[7:0]$14953 $1\xive11_pri$next[7:0]$14905 + assign $4\xive12_pri$next[7:0]$14954 $1\xive12_pri$next[7:0]$14906 + assign $4\xive13_pri$next[7:0]$14955 $1\xive13_pri$next[7:0]$14907 + assign $4\xive14_pri$next[7:0]$14956 $1\xive14_pri$next[7:0]$14908 + assign $4\xive15_pri$next[7:0]$14957 $1\xive15_pri$next[7:0]$14909 + assign $4\xive1_pri$next[7:0]$14958 $1\xive1_pri$next[7:0]$14910 + assign $4\xive2_pri$next[7:0]$14959 $1\xive2_pri$next[7:0]$14911 + assign $4\xive3_pri$next[7:0]$14960 $1\xive3_pri$next[7:0]$14912 + assign $4\xive4_pri$next[7:0]$14961 $1\xive4_pri$next[7:0]$14913 + assign $4\xive5_pri$next[7:0]$14962 $1\xive5_pri$next[7:0]$14914 + assign $4\xive6_pri$next[7:0]$14963 $1\xive6_pri$next[7:0]$14915 + assign $4\xive7_pri$next[7:0]$14964 $1\xive7_pri$next[7:0]$14916 + assign $4\xive8_pri$next[7:0]$14965 $1\xive8_pri$next[7:0]$14917 + assign $4\xive9_pri$next[7:0]$14966 $1\xive9_pri$next[7:0]$14918 end sync always - update \xive0_pri$next $0\xive0_pri$next[7:0]$14901 - update \xive10_pri$next $0\xive10_pri$next[7:0]$14902 - update \xive11_pri$next $0\xive11_pri$next[7:0]$14903 - update \xive12_pri$next $0\xive12_pri$next[7:0]$14904 - update \xive13_pri$next $0\xive13_pri$next[7:0]$14905 - update \xive14_pri$next $0\xive14_pri$next[7:0]$14906 - update \xive15_pri$next $0\xive15_pri$next[7:0]$14907 - update \xive1_pri$next $0\xive1_pri$next[7:0]$14908 - update \xive2_pri$next $0\xive2_pri$next[7:0]$14909 - update \xive3_pri$next $0\xive3_pri$next[7:0]$14910 - update \xive4_pri$next $0\xive4_pri$next[7:0]$14911 - update \xive5_pri$next $0\xive5_pri$next[7:0]$14912 - update \xive6_pri$next $0\xive6_pri$next[7:0]$14913 - update \xive7_pri$next $0\xive7_pri$next[7:0]$14914 - update \xive8_pri$next $0\xive8_pri$next[7:0]$14915 - update \xive9_pri$next $0\xive9_pri$next[7:0]$14916 + update \xive0_pri$next $0\xive0_pri$next[7:0]$14887 + update \xive10_pri$next $0\xive10_pri$next[7:0]$14888 + update \xive11_pri$next $0\xive11_pri$next[7:0]$14889 + update \xive12_pri$next $0\xive12_pri$next[7:0]$14890 + update \xive13_pri$next $0\xive13_pri$next[7:0]$14891 + update \xive14_pri$next $0\xive14_pri$next[7:0]$14892 + update \xive15_pri$next $0\xive15_pri$next[7:0]$14893 + update \xive1_pri$next $0\xive1_pri$next[7:0]$14894 + update \xive2_pri$next $0\xive2_pri$next[7:0]$14895 + update \xive3_pri$next $0\xive3_pri$next[7:0]$14896 + update \xive4_pri$next $0\xive4_pri$next[7:0]$14897 + update \xive5_pri$next $0\xive5_pri$next[7:0]$14898 + update \xive6_pri$next $0\xive6_pri$next[7:0]$14899 + update \xive7_pri$next $0\xive7_pri$next[7:0]$14900 + update \xive8_pri$next $0\xive8_pri$next[7:0]$14901 + update \xive9_pri$next $0\xive9_pri$next[7:0]$14902 end - attribute \src "libresoc.v:202197.3-202206.6" - process $proc$libresoc.v:202197$14981 + attribute \src "libresoc.v:204889.3-204898.6" + process $proc$libresoc.v:204889$14967 assign { } { } assign { } { } assign $0\cur_pri0[7:0] $1\cur_pri0[7:0] - attribute \src "libresoc.v:202198.5-202198.29" + attribute \src "libresoc.v:204890.5-204890.29" switch \initial - attribute \src "libresoc.v:202198.9-202198.17" + attribute \src "libresoc.v:204890.9-204890.17" case 1'1 case end @@ -421644,14 +394664,14 @@ module \xics_ics sync always update \cur_pri0 $0\cur_pri0[7:0] end - attribute \src "libresoc.v:202207.3-202216.6" - process $proc$libresoc.v:202207$14982 + attribute \src "libresoc.v:204899.3-204908.6" + process $proc$libresoc.v:204899$14968 assign { } { } assign { } { } assign $0\cur_idx0[3:0] $1\cur_idx0[3:0] - attribute \src "libresoc.v:202208.5-202208.29" + attribute \src "libresoc.v:204900.5-204900.29" switch \initial - attribute \src "libresoc.v:202208.9-202208.17" + attribute \src "libresoc.v:204900.9-204900.17" case 1'1 case end @@ -421667,14 +394687,14 @@ module \xics_ics sync always update \cur_idx0 $0\cur_idx0[3:0] end - attribute \src "libresoc.v:202217.3-202226.6" - process $proc$libresoc.v:202217$14983 + attribute \src "libresoc.v:204909.3-204918.6" + process $proc$libresoc.v:204909$14969 assign { } { } assign { } { } assign $0\cur_pri1[7:0] $1\cur_pri1[7:0] - attribute \src "libresoc.v:202218.5-202218.29" + attribute \src "libresoc.v:204910.5-204910.29" switch \initial - attribute \src "libresoc.v:202218.9-202218.17" + attribute \src "libresoc.v:204910.9-204910.17" case 1'1 case end @@ -421690,14 +394710,14 @@ module \xics_ics sync always update \cur_pri1 $0\cur_pri1[7:0] end - attribute \src "libresoc.v:202227.3-202236.6" - process $proc$libresoc.v:202227$14984 + attribute \src "libresoc.v:204919.3-204928.6" + process $proc$libresoc.v:204919$14970 assign { } { } assign { } { } assign $0\cur_idx1[3:0] $1\cur_idx1[3:0] - attribute \src "libresoc.v:202228.5-202228.29" + attribute \src "libresoc.v:204920.5-204920.29" switch \initial - attribute \src "libresoc.v:202228.9-202228.17" + attribute \src "libresoc.v:204920.9-204920.17" case 1'1 case end @@ -421713,14 +394733,14 @@ module \xics_ics sync always update \cur_idx1 $0\cur_idx1[3:0] end - attribute \src "libresoc.v:202237.3-202246.6" - process $proc$libresoc.v:202237$14985 + attribute \src "libresoc.v:204929.3-204938.6" + process $proc$libresoc.v:204929$14971 assign { } { } assign { } { } assign $0\cur_pri2[7:0] $1\cur_pri2[7:0] - attribute \src "libresoc.v:202238.5-202238.29" + attribute \src "libresoc.v:204930.5-204930.29" switch \initial - attribute \src "libresoc.v:202238.9-202238.17" + attribute \src "libresoc.v:204930.9-204930.17" case 1'1 case end @@ -421736,14 +394756,14 @@ module \xics_ics sync always update \cur_pri2 $0\cur_pri2[7:0] end - attribute \src "libresoc.v:202247.3-202256.6" - process $proc$libresoc.v:202247$14986 + attribute \src "libresoc.v:204939.3-204948.6" + process $proc$libresoc.v:204939$14972 assign { } { } assign { } { } assign $0\cur_idx2[3:0] $1\cur_idx2[3:0] - attribute \src "libresoc.v:202248.5-202248.29" + attribute \src "libresoc.v:204940.5-204940.29" switch \initial - attribute \src "libresoc.v:202248.9-202248.17" + attribute \src "libresoc.v:204940.9-204940.17" case 1'1 case end @@ -421759,14 +394779,14 @@ module \xics_ics sync always update \cur_idx2 $0\cur_idx2[3:0] end - attribute \src "libresoc.v:202257.3-202266.6" - process $proc$libresoc.v:202257$14987 + attribute \src "libresoc.v:204949.3-204958.6" + process $proc$libresoc.v:204949$14973 assign { } { } assign { } { } assign $0\cur_pri3[7:0] $1\cur_pri3[7:0] - attribute \src "libresoc.v:202258.5-202258.29" + attribute \src "libresoc.v:204950.5-204950.29" switch \initial - attribute \src "libresoc.v:202258.9-202258.17" + attribute \src "libresoc.v:204950.9-204950.17" case 1'1 case end @@ -421782,14 +394802,14 @@ module \xics_ics sync always update \cur_pri3 $0\cur_pri3[7:0] end - attribute \src "libresoc.v:202267.3-202276.6" - process $proc$libresoc.v:202267$14988 + attribute \src "libresoc.v:204959.3-204968.6" + process $proc$libresoc.v:204959$14974 assign { } { } assign { } { } assign $0\cur_idx3[3:0] $1\cur_idx3[3:0] - attribute \src "libresoc.v:202268.5-202268.29" + attribute \src "libresoc.v:204960.5-204960.29" switch \initial - attribute \src "libresoc.v:202268.9-202268.17" + attribute \src "libresoc.v:204960.9-204960.17" case 1'1 case end @@ -421805,14 +394825,14 @@ module \xics_ics sync always update \cur_idx3 $0\cur_idx3[3:0] end - attribute \src "libresoc.v:202277.3-202286.6" - process $proc$libresoc.v:202277$14989 + attribute \src "libresoc.v:204969.3-204978.6" + process $proc$libresoc.v:204969$14975 assign { } { } assign { } { } assign $0\cur_pri4[7:0] $1\cur_pri4[7:0] - attribute \src "libresoc.v:202278.5-202278.29" + attribute \src "libresoc.v:204970.5-204970.29" switch \initial - attribute \src "libresoc.v:202278.9-202278.17" + attribute \src "libresoc.v:204970.9-204970.17" case 1'1 case end @@ -421828,14 +394848,14 @@ module \xics_ics sync always update \cur_pri4 $0\cur_pri4[7:0] end - attribute \src "libresoc.v:202287.3-202295.6" - process $proc$libresoc.v:202287$14990 + attribute \src "libresoc.v:204979.3-204987.6" + process $proc$libresoc.v:204979$14976 assign { } { } assign { } { } - assign $0\int_level_l$next[15:0]$14991 $1\int_level_l$next[15:0]$14992 - attribute \src "libresoc.v:202288.5-202288.29" + assign $0\int_level_l$next[15:0]$14977 $1\int_level_l$next[15:0]$14978 + attribute \src "libresoc.v:204980.5-204980.29" switch \initial - attribute \src "libresoc.v:202288.9-202288.17" + attribute \src "libresoc.v:204980.9-204980.17" case 1'1 case end @@ -421844,21 +394864,21 @@ module \xics_ics attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\int_level_l$next[15:0]$14992 16'0000000000000000 + assign $1\int_level_l$next[15:0]$14978 16'0000000000000000 case - assign $1\int_level_l$next[15:0]$14992 \int_level_i + assign $1\int_level_l$next[15:0]$14978 \int_level_i end sync always - update \int_level_l$next $0\int_level_l$next[15:0]$14991 + update \int_level_l$next $0\int_level_l$next[15:0]$14977 end - attribute \src "libresoc.v:202296.3-202305.6" - process $proc$libresoc.v:202296$14993 + attribute \src "libresoc.v:204988.3-204997.6" + process $proc$libresoc.v:204988$14979 assign { } { } assign { } { } assign $0\cur_idx4[3:0] $1\cur_idx4[3:0] - attribute \src "libresoc.v:202297.5-202297.29" + attribute \src "libresoc.v:204989.5-204989.29" switch \initial - attribute \src "libresoc.v:202297.9-202297.17" + attribute \src "libresoc.v:204989.9-204989.17" case 1'1 case end @@ -421874,14 +394894,14 @@ module \xics_ics sync always update \cur_idx4 $0\cur_idx4[3:0] end - attribute \src "libresoc.v:202306.3-202315.6" - process $proc$libresoc.v:202306$14994 + attribute \src "libresoc.v:204998.3-205007.6" + process $proc$libresoc.v:204998$14980 assign { } { } assign { } { } assign $0\cur_pri5[7:0] $1\cur_pri5[7:0] - attribute \src "libresoc.v:202307.5-202307.29" + attribute \src "libresoc.v:204999.5-204999.29" switch \initial - attribute \src "libresoc.v:202307.9-202307.17" + attribute \src "libresoc.v:204999.9-204999.17" case 1'1 case end @@ -421897,14 +394917,14 @@ module \xics_ics sync always update \cur_pri5 $0\cur_pri5[7:0] end - attribute \src "libresoc.v:202316.3-202325.6" - process $proc$libresoc.v:202316$14995 + attribute \src "libresoc.v:205008.3-205017.6" + process $proc$libresoc.v:205008$14981 assign { } { } assign { } { } assign $0\cur_idx5[3:0] $1\cur_idx5[3:0] - attribute \src "libresoc.v:202317.5-202317.29" + attribute \src "libresoc.v:205009.5-205009.29" switch \initial - attribute \src "libresoc.v:202317.9-202317.17" + attribute \src "libresoc.v:205009.9-205009.17" case 1'1 case end @@ -421920,14 +394940,14 @@ module \xics_ics sync always update \cur_idx5 $0\cur_idx5[3:0] end - attribute \src "libresoc.v:202326.3-202335.6" - process $proc$libresoc.v:202326$14996 + attribute \src "libresoc.v:205018.3-205027.6" + process $proc$libresoc.v:205018$14982 assign { } { } assign { } { } assign $0\cur_pri6[7:0] $1\cur_pri6[7:0] - attribute \src "libresoc.v:202327.5-202327.29" + attribute \src "libresoc.v:205019.5-205019.29" switch \initial - attribute \src "libresoc.v:202327.9-202327.17" + attribute \src "libresoc.v:205019.9-205019.17" case 1'1 case end @@ -421943,14 +394963,14 @@ module \xics_ics sync always update \cur_pri6 $0\cur_pri6[7:0] end - attribute \src "libresoc.v:202336.3-202345.6" - process $proc$libresoc.v:202336$14997 + attribute \src "libresoc.v:205028.3-205037.6" + process $proc$libresoc.v:205028$14983 assign { } { } assign { } { } assign $0\cur_idx6[3:0] $1\cur_idx6[3:0] - attribute \src "libresoc.v:202337.5-202337.29" + attribute \src "libresoc.v:205029.5-205029.29" switch \initial - attribute \src "libresoc.v:202337.9-202337.17" + attribute \src "libresoc.v:205029.9-205029.17" case 1'1 case end @@ -421966,14 +394986,14 @@ module \xics_ics sync always update \cur_idx6 $0\cur_idx6[3:0] end - attribute \src "libresoc.v:202346.3-202355.6" - process $proc$libresoc.v:202346$14998 + attribute \src "libresoc.v:205038.3-205047.6" + process $proc$libresoc.v:205038$14984 assign { } { } assign { } { } assign $0\cur_pri7[7:0] $1\cur_pri7[7:0] - attribute \src "libresoc.v:202347.5-202347.29" + attribute \src "libresoc.v:205039.5-205039.29" switch \initial - attribute \src "libresoc.v:202347.9-202347.17" + attribute \src "libresoc.v:205039.9-205039.17" case 1'1 case end @@ -421989,14 +395009,14 @@ module \xics_ics sync always update \cur_pri7 $0\cur_pri7[7:0] end - attribute \src "libresoc.v:202356.3-202365.6" - process $proc$libresoc.v:202356$14999 + attribute \src "libresoc.v:205048.3-205057.6" + process $proc$libresoc.v:205048$14985 assign { } { } assign { } { } assign $0\cur_idx7[3:0] $1\cur_idx7[3:0] - attribute \src "libresoc.v:202357.5-202357.29" + attribute \src "libresoc.v:205049.5-205049.29" switch \initial - attribute \src "libresoc.v:202357.9-202357.17" + attribute \src "libresoc.v:205049.9-205049.17" case 1'1 case end @@ -422012,14 +395032,14 @@ module \xics_ics sync always update \cur_idx7 $0\cur_idx7[3:0] end - attribute \src "libresoc.v:202366.3-202375.6" - process $proc$libresoc.v:202366$15000 + attribute \src "libresoc.v:205058.3-205067.6" + process $proc$libresoc.v:205058$14986 assign { } { } assign { } { } assign $0\cur_pri8[7:0] $1\cur_pri8[7:0] - attribute \src "libresoc.v:202367.5-202367.29" + attribute \src "libresoc.v:205059.5-205059.29" switch \initial - attribute \src "libresoc.v:202367.9-202367.17" + attribute \src "libresoc.v:205059.9-205059.17" case 1'1 case end @@ -422035,14 +395055,14 @@ module \xics_ics sync always update \cur_pri8 $0\cur_pri8[7:0] end - attribute \src "libresoc.v:202376.3-202385.6" - process $proc$libresoc.v:202376$15001 + attribute \src "libresoc.v:205068.3-205077.6" + process $proc$libresoc.v:205068$14987 assign { } { } assign { } { } assign $0\cur_idx8[3:0] $1\cur_idx8[3:0] - attribute \src "libresoc.v:202377.5-202377.29" + attribute \src "libresoc.v:205069.5-205069.29" switch \initial - attribute \src "libresoc.v:202377.9-202377.17" + attribute \src "libresoc.v:205069.9-205069.17" case 1'1 case end @@ -422058,14 +395078,14 @@ module \xics_ics sync always update \cur_idx8 $0\cur_idx8[3:0] end - attribute \src "libresoc.v:202386.3-202395.6" - process $proc$libresoc.v:202386$15002 + attribute \src "libresoc.v:205078.3-205087.6" + process $proc$libresoc.v:205078$14988 assign { } { } assign { } { } assign $0\cur_pri9[7:0] $1\cur_pri9[7:0] - attribute \src "libresoc.v:202387.5-202387.29" + attribute \src "libresoc.v:205079.5-205079.29" switch \initial - attribute \src "libresoc.v:202387.9-202387.17" + attribute \src "libresoc.v:205079.9-205079.17" case 1'1 case end @@ -422081,14 +395101,14 @@ module \xics_ics sync always update \cur_pri9 $0\cur_pri9[7:0] end - attribute \src "libresoc.v:202396.3-202405.6" - process $proc$libresoc.v:202396$15003 + attribute \src "libresoc.v:205088.3-205097.6" + process $proc$libresoc.v:205088$14989 assign { } { } assign { } { } assign $0\cur_idx9[3:0] $1\cur_idx9[3:0] - attribute \src "libresoc.v:202397.5-202397.29" + attribute \src "libresoc.v:205089.5-205089.29" switch \initial - attribute \src "libresoc.v:202397.9-202397.17" + attribute \src "libresoc.v:205089.9-205089.17" case 1'1 case end @@ -422104,14 +395124,14 @@ module \xics_ics sync always update \cur_idx9 $0\cur_idx9[3:0] end - attribute \src "libresoc.v:202406.3-202415.6" - process $proc$libresoc.v:202406$15004 + attribute \src "libresoc.v:205098.3-205107.6" + process $proc$libresoc.v:205098$14990 assign { } { } assign { } { } assign $0\cur_pri10[7:0] $1\cur_pri10[7:0] - attribute \src "libresoc.v:202407.5-202407.29" + attribute \src "libresoc.v:205099.5-205099.29" switch \initial - attribute \src "libresoc.v:202407.9-202407.17" + attribute \src "libresoc.v:205099.9-205099.17" case 1'1 case end @@ -422127,14 +395147,14 @@ module \xics_ics sync always update \cur_pri10 $0\cur_pri10[7:0] end - attribute \src "libresoc.v:202416.3-202425.6" - process $proc$libresoc.v:202416$15005 + attribute \src "libresoc.v:205108.3-205117.6" + process $proc$libresoc.v:205108$14991 assign { } { } assign { } { } assign $0\cur_idx10[3:0] $1\cur_idx10[3:0] - attribute \src "libresoc.v:202417.5-202417.29" + attribute \src "libresoc.v:205109.5-205109.29" switch \initial - attribute \src "libresoc.v:202417.9-202417.17" + attribute \src "libresoc.v:205109.9-205109.17" case 1'1 case end @@ -422150,14 +395170,14 @@ module \xics_ics sync always update \cur_idx10 $0\cur_idx10[3:0] end - attribute \src "libresoc.v:202426.3-202435.6" - process $proc$libresoc.v:202426$15006 + attribute \src "libresoc.v:205118.3-205127.6" + process $proc$libresoc.v:205118$14992 assign { } { } assign { } { } assign $0\cur_pri11[7:0] $1\cur_pri11[7:0] - attribute \src "libresoc.v:202427.5-202427.29" + attribute \src "libresoc.v:205119.5-205119.29" switch \initial - attribute \src "libresoc.v:202427.9-202427.17" + attribute \src "libresoc.v:205119.9-205119.17" case 1'1 case end @@ -422173,14 +395193,14 @@ module \xics_ics sync always update \cur_pri11 $0\cur_pri11[7:0] end - attribute \src "libresoc.v:202436.3-202445.6" - process $proc$libresoc.v:202436$15007 + attribute \src "libresoc.v:205128.3-205137.6" + process $proc$libresoc.v:205128$14993 assign { } { } assign { } { } assign $0\cur_idx11[3:0] $1\cur_idx11[3:0] - attribute \src "libresoc.v:202437.5-202437.29" + attribute \src "libresoc.v:205129.5-205129.29" switch \initial - attribute \src "libresoc.v:202437.9-202437.17" + attribute \src "libresoc.v:205129.9-205129.17" case 1'1 case end @@ -422196,14 +395216,14 @@ module \xics_ics sync always update \cur_idx11 $0\cur_idx11[3:0] end - attribute \src "libresoc.v:202446.3-202455.6" - process $proc$libresoc.v:202446$15008 + attribute \src "libresoc.v:205138.3-205147.6" + process $proc$libresoc.v:205138$14994 assign { } { } assign { } { } assign $0\cur_pri12[7:0] $1\cur_pri12[7:0] - attribute \src "libresoc.v:202447.5-202447.29" + attribute \src "libresoc.v:205139.5-205139.29" switch \initial - attribute \src "libresoc.v:202447.9-202447.17" + attribute \src "libresoc.v:205139.9-205139.17" case 1'1 case end @@ -422219,14 +395239,14 @@ module \xics_ics sync always update \cur_pri12 $0\cur_pri12[7:0] end - attribute \src "libresoc.v:202456.3-202465.6" - process $proc$libresoc.v:202456$15009 + attribute \src "libresoc.v:205148.3-205157.6" + process $proc$libresoc.v:205148$14995 assign { } { } assign { } { } assign $0\cur_idx12[3:0] $1\cur_idx12[3:0] - attribute \src "libresoc.v:202457.5-202457.29" + attribute \src "libresoc.v:205149.5-205149.29" switch \initial - attribute \src "libresoc.v:202457.9-202457.17" + attribute \src "libresoc.v:205149.9-205149.17" case 1'1 case end @@ -422242,14 +395262,14 @@ module \xics_ics sync always update \cur_idx12 $0\cur_idx12[3:0] end - attribute \src "libresoc.v:202466.3-202475.6" - process $proc$libresoc.v:202466$15010 + attribute \src "libresoc.v:205158.3-205167.6" + process $proc$libresoc.v:205158$14996 assign { } { } assign { } { } assign $0\cur_pri13[7:0] $1\cur_pri13[7:0] - attribute \src "libresoc.v:202467.5-202467.29" + attribute \src "libresoc.v:205159.5-205159.29" switch \initial - attribute \src "libresoc.v:202467.9-202467.17" + attribute \src "libresoc.v:205159.9-205159.17" case 1'1 case end @@ -422265,14 +395285,14 @@ module \xics_ics sync always update \cur_pri13 $0\cur_pri13[7:0] end - attribute \src "libresoc.v:202476.3-202485.6" - process $proc$libresoc.v:202476$15011 + attribute \src "libresoc.v:205168.3-205177.6" + process $proc$libresoc.v:205168$14997 assign { } { } assign { } { } assign $0\cur_idx13[3:0] $1\cur_idx13[3:0] - attribute \src "libresoc.v:202477.5-202477.29" + attribute \src "libresoc.v:205169.5-205169.29" switch \initial - attribute \src "libresoc.v:202477.9-202477.17" + attribute \src "libresoc.v:205169.9-205169.17" case 1'1 case end @@ -422288,14 +395308,14 @@ module \xics_ics sync always update \cur_idx13 $0\cur_idx13[3:0] end - attribute \src "libresoc.v:202486.3-202495.6" - process $proc$libresoc.v:202486$15012 + attribute \src "libresoc.v:205178.3-205187.6" + process $proc$libresoc.v:205178$14998 assign { } { } assign { } { } assign $0\cur_pri14[7:0] $1\cur_pri14[7:0] - attribute \src "libresoc.v:202487.5-202487.29" + attribute \src "libresoc.v:205179.5-205179.29" switch \initial - attribute \src "libresoc.v:202487.9-202487.17" + attribute \src "libresoc.v:205179.9-205179.17" case 1'1 case end @@ -422311,14 +395331,14 @@ module \xics_ics sync always update \cur_pri14 $0\cur_pri14[7:0] end - attribute \src "libresoc.v:202496.3-202545.6" - process $proc$libresoc.v:202496$15013 + attribute \src "libresoc.v:205188.3-205237.6" + process $proc$libresoc.v:205188$14999 assign { } { } assign { } { } assign $0\be_out[31:0] $1\be_out[31:0] - attribute \src "libresoc.v:202497.5-202497.29" + attribute \src "libresoc.v:205189.5-205189.29" switch \initial - attribute \src "libresoc.v:202497.9-202497.17" + attribute \src "libresoc.v:205189.9-205189.17" case 1'1 case end @@ -422411,14 +395431,14 @@ module \xics_ics sync always update \be_out $0\be_out[31:0] end - attribute \src "libresoc.v:202546.3-202555.6" - process $proc$libresoc.v:202546$15014 + attribute \src "libresoc.v:205238.3-205247.6" + process $proc$libresoc.v:205238$15000 assign { } { } assign { } { } assign $0\cur_idx14[3:0] $1\cur_idx14[3:0] - attribute \src "libresoc.v:202547.5-202547.29" + attribute \src "libresoc.v:205239.5-205239.29" switch \initial - attribute \src "libresoc.v:202547.9-202547.17" + attribute \src "libresoc.v:205239.9-205239.17" case 1'1 case end @@ -422434,14 +395454,14 @@ module \xics_ics sync always update \cur_idx14 $0\cur_idx14[3:0] end - attribute \src "libresoc.v:202556.3-202565.6" - process $proc$libresoc.v:202556$15015 + attribute \src "libresoc.v:205248.3-205257.6" + process $proc$libresoc.v:205248$15001 assign { } { } assign { } { } assign $0\cur_pri15[7:0] $1\cur_pri15[7:0] - attribute \src "libresoc.v:202557.5-202557.29" + attribute \src "libresoc.v:205249.5-205249.29" switch \initial - attribute \src "libresoc.v:202557.9-202557.17" + attribute \src "libresoc.v:205249.9-205249.17" case 1'1 case end @@ -422457,14 +395477,14 @@ module \xics_ics sync always update \cur_pri15 $0\cur_pri15[7:0] end - attribute \src "libresoc.v:202566.3-202575.6" - process $proc$libresoc.v:202566$15016 + attribute \src "libresoc.v:205258.3-205267.6" + process $proc$libresoc.v:205258$15002 assign { } { } assign { } { } assign $0\cur_idx15[3:0] $1\cur_idx15[3:0] - attribute \src "libresoc.v:202567.5-202567.29" + attribute \src "libresoc.v:205259.5-205259.29" switch \initial - attribute \src "libresoc.v:202567.9-202567.17" + attribute \src "libresoc.v:205259.9-205259.17" case 1'1 case end @@ -422480,14 +395500,14 @@ module \xics_ics sync always update \cur_idx15 $0\cur_idx15[3:0] end - attribute \src "libresoc.v:202576.3-202585.6" - process $proc$libresoc.v:202576$15017 + attribute \src "libresoc.v:205268.3-205277.6" + process $proc$libresoc.v:205268$15003 assign { } { } assign { } { } assign $0\ibit[0:0] $1\ibit[0:0] - attribute \src "libresoc.v:202577.5-202577.29" + attribute \src "libresoc.v:205269.5-205269.29" switch \initial - attribute \src "libresoc.v:202577.9-202577.17" + attribute \src "libresoc.v:205269.9-205269.17" case 1'1 case end @@ -422503,14 +395523,14 @@ module \xics_ics sync always update \ibit $0\ibit[0:0] end - attribute \src "libresoc.v:202586.3-202594.6" - process $proc$libresoc.v:202586$15018 + attribute \src "libresoc.v:205278.3-205286.6" + process $proc$libresoc.v:205278$15004 assign { } { } assign { } { } - assign $0\ics_wb__dat_r$next[31:0]$15019 $1\ics_wb__dat_r$next[31:0]$15020 - attribute \src "libresoc.v:202587.5-202587.29" + assign $0\ics_wb__dat_r$next[31:0]$15005 $1\ics_wb__dat_r$next[31:0]$15006 + attribute \src "libresoc.v:205279.5-205279.29" switch \initial - attribute \src "libresoc.v:202587.9-202587.17" + attribute \src "libresoc.v:205279.9-205279.17" case 1'1 case end @@ -422519,21 +395539,21 @@ module \xics_ics attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ics_wb__dat_r$next[31:0]$15020 0 + assign $1\ics_wb__dat_r$next[31:0]$15006 0 case - assign $1\ics_wb__dat_r$next[31:0]$15020 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } + assign $1\ics_wb__dat_r$next[31:0]$15006 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } end sync always - update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$15019 + update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$15005 end - attribute \src "libresoc.v:202595.3-202603.6" - process $proc$libresoc.v:202595$15021 + attribute \src "libresoc.v:205287.3-205295.6" + process $proc$libresoc.v:205287$15007 assign { } { } assign { } { } - assign $0\ics_wb__ack$next[0:0]$15022 $1\ics_wb__ack$next[0:0]$15023 - attribute \src "libresoc.v:202596.5-202596.29" + assign $0\ics_wb__ack$next[0:0]$15008 $1\ics_wb__ack$next[0:0]$15009 + attribute \src "libresoc.v:205288.5-205288.29" switch \initial - attribute \src "libresoc.v:202596.9-202596.17" + attribute \src "libresoc.v:205288.9-205288.17" case 1'1 case end @@ -422542,116 +395562,116 @@ module \xics_ics attribute \src "libresoc.v:0.0-0.0" case 1'1 assign { } { } - assign $1\ics_wb__ack$next[0:0]$15023 1'0 - case - assign $1\ics_wb__ack$next[0:0]$15023 \wb_valid - end - sync always - update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$15022 - end - connect \$7 $ternary$libresoc.v:201966$14776_Y - connect \$99 $lt$libresoc.v:201967$14777_Y - connect \$101 $and$libresoc.v:201968$14778_Y - connect \$103 $lt$libresoc.v:201969$14779_Y - connect \$105 $and$libresoc.v:201970$14780_Y - connect \$107 $lt$libresoc.v:201971$14781_Y - connect \$109 $and$libresoc.v:201972$14782_Y - connect \$111 $lt$libresoc.v:201973$14783_Y - connect \$113 $and$libresoc.v:201974$14784_Y - connect \$115 $lt$libresoc.v:201975$14785_Y - connect \$117 $and$libresoc.v:201976$14786_Y - connect \$119 $lt$libresoc.v:201977$14787_Y - connect \$121 $and$libresoc.v:201978$14788_Y - connect \$123 $lt$libresoc.v:201979$14789_Y - connect \$125 $and$libresoc.v:201980$14790_Y - connect \$127 $lt$libresoc.v:201981$14791_Y - connect \$12 $eq$libresoc.v:201982$14792_Y - connect \$129 $and$libresoc.v:201983$14793_Y - connect \$131 $lt$libresoc.v:201984$14794_Y - connect \$133 $and$libresoc.v:201985$14795_Y - connect \$135 $lt$libresoc.v:201986$14796_Y - connect \$137 $and$libresoc.v:201987$14797_Y - connect \$11 $ternary$libresoc.v:201988$14798_Y - connect \$139 $lt$libresoc.v:201989$14799_Y - connect \$141 $and$libresoc.v:201990$14800_Y - connect \$143 $lt$libresoc.v:201991$14801_Y - connect \$145 $and$libresoc.v:201992$14802_Y - connect \$147 $lt$libresoc.v:201993$14803_Y - connect \$149 $and$libresoc.v:201994$14804_Y - connect \$151 $lt$libresoc.v:201995$14805_Y - connect \$153 $and$libresoc.v:201996$14806_Y - connect \$155 $lt$libresoc.v:201997$14807_Y - connect \$157 $and$libresoc.v:201998$14808_Y - connect \$159 $lt$libresoc.v:201999$14809_Y - connect \$161 $and$libresoc.v:202000$14810_Y - connect \$163 $lt$libresoc.v:202001$14811_Y - connect \$165 $and$libresoc.v:202002$14812_Y - connect \$167 $lt$libresoc.v:202003$14813_Y - connect \$16 $eq$libresoc.v:202004$14814_Y - connect \$169 $and$libresoc.v:202005$14815_Y - connect \$171 $lt$libresoc.v:202006$14816_Y - connect \$173 $and$libresoc.v:202007$14817_Y - connect \$175 $lt$libresoc.v:202008$14818_Y - connect \$177 $and$libresoc.v:202009$14819_Y - connect \$15 $ternary$libresoc.v:202010$14820_Y - connect \$179 $lt$libresoc.v:202011$14821_Y - connect \$181 $and$libresoc.v:202012$14822_Y - connect \$183 $lt$libresoc.v:202013$14823_Y - connect \$185 $and$libresoc.v:202014$14824_Y - connect \$187 $lt$libresoc.v:202015$14825_Y - connect \$189 $and$libresoc.v:202016$14826_Y - connect \$191 $lt$libresoc.v:202017$14827_Y - connect \$193 $and$libresoc.v:202018$14828_Y - connect \$195 $lt$libresoc.v:202019$14829_Y - connect \$197 $and$libresoc.v:202020$14830_Y - connect \$1 $eq$libresoc.v:202021$14831_Y - connect \$199 $lt$libresoc.v:202022$14832_Y - connect \$201 $and$libresoc.v:202023$14833_Y - connect \$204 $eq$libresoc.v:202024$14834_Y - connect \$203 $ternary$libresoc.v:202025$14835_Y - connect \$20 $eq$libresoc.v:202026$14836_Y - connect \$19 $ternary$libresoc.v:202027$14837_Y - connect \$24 $eq$libresoc.v:202028$14838_Y - connect \$23 $ternary$libresoc.v:202029$14839_Y - connect \$28 $eq$libresoc.v:202030$14840_Y - connect \$27 $ternary$libresoc.v:202031$14841_Y - connect \$32 $eq$libresoc.v:202032$14842_Y - connect \$31 $ternary$libresoc.v:202033$14843_Y - connect \$36 $eq$libresoc.v:202034$14844_Y - connect \$35 $ternary$libresoc.v:202035$14845_Y - connect \$3 $eq$libresoc.v:202036$14846_Y - connect \$40 $eq$libresoc.v:202037$14847_Y - connect \$39 $ternary$libresoc.v:202038$14848_Y - connect \$44 $eq$libresoc.v:202039$14849_Y - connect \$43 $ternary$libresoc.v:202040$14850_Y - connect \$48 $eq$libresoc.v:202041$14851_Y - connect \$47 $ternary$libresoc.v:202042$14852_Y - connect \$52 $eq$libresoc.v:202043$14853_Y - connect \$51 $ternary$libresoc.v:202044$14854_Y - connect \$56 $eq$libresoc.v:202045$14855_Y - connect \$55 $ternary$libresoc.v:202046$14856_Y - connect \$5 $and$libresoc.v:202047$14857_Y - connect \$60 $eq$libresoc.v:202048$14858_Y - connect \$59 $ternary$libresoc.v:202049$14859_Y - connect \$64 $eq$libresoc.v:202050$14860_Y - connect \$63 $ternary$libresoc.v:202051$14861_Y - connect \$68 $eq$libresoc.v:202052$14862_Y - connect \$67 $ternary$libresoc.v:202053$14863_Y - connect \$71 $shr$libresoc.v:202054$14864_Y [0] - connect \$73 $and$libresoc.v:202055$14865_Y - connect \$75 $lt$libresoc.v:202056$14866_Y - connect \$77 $and$libresoc.v:202057$14867_Y - connect \$79 $lt$libresoc.v:202058$14868_Y - connect \$81 $and$libresoc.v:202059$14869_Y - connect \$83 $lt$libresoc.v:202060$14870_Y - connect \$85 $and$libresoc.v:202061$14871_Y - connect \$87 $lt$libresoc.v:202062$14872_Y - connect \$8 $eq$libresoc.v:202063$14873_Y - connect \$89 $and$libresoc.v:202064$14874_Y - connect \$91 $lt$libresoc.v:202065$14875_Y - connect \$93 $and$libresoc.v:202066$14876_Y - connect \$95 $lt$libresoc.v:202067$14877_Y - connect \$97 $and$libresoc.v:202068$14878_Y + assign $1\ics_wb__ack$next[0:0]$15009 1'0 + case + assign $1\ics_wb__ack$next[0:0]$15009 \wb_valid + end + sync always + update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$15008 + end + connect \$7 $ternary$libresoc.v:204658$14762_Y + connect \$99 $lt$libresoc.v:204659$14763_Y + connect \$101 $and$libresoc.v:204660$14764_Y + connect \$103 $lt$libresoc.v:204661$14765_Y + connect \$105 $and$libresoc.v:204662$14766_Y + connect \$107 $lt$libresoc.v:204663$14767_Y + connect \$109 $and$libresoc.v:204664$14768_Y + connect \$111 $lt$libresoc.v:204665$14769_Y + connect \$113 $and$libresoc.v:204666$14770_Y + connect \$115 $lt$libresoc.v:204667$14771_Y + connect \$117 $and$libresoc.v:204668$14772_Y + connect \$119 $lt$libresoc.v:204669$14773_Y + connect \$121 $and$libresoc.v:204670$14774_Y + connect \$123 $lt$libresoc.v:204671$14775_Y + connect \$125 $and$libresoc.v:204672$14776_Y + connect \$127 $lt$libresoc.v:204673$14777_Y + connect \$12 $eq$libresoc.v:204674$14778_Y + connect \$129 $and$libresoc.v:204675$14779_Y + connect \$131 $lt$libresoc.v:204676$14780_Y + connect \$133 $and$libresoc.v:204677$14781_Y + connect \$135 $lt$libresoc.v:204678$14782_Y + connect \$137 $and$libresoc.v:204679$14783_Y + connect \$11 $ternary$libresoc.v:204680$14784_Y + connect \$139 $lt$libresoc.v:204681$14785_Y + connect \$141 $and$libresoc.v:204682$14786_Y + connect \$143 $lt$libresoc.v:204683$14787_Y + connect \$145 $and$libresoc.v:204684$14788_Y + connect \$147 $lt$libresoc.v:204685$14789_Y + connect \$149 $and$libresoc.v:204686$14790_Y + connect \$151 $lt$libresoc.v:204687$14791_Y + connect \$153 $and$libresoc.v:204688$14792_Y + connect \$155 $lt$libresoc.v:204689$14793_Y + connect \$157 $and$libresoc.v:204690$14794_Y + connect \$159 $lt$libresoc.v:204691$14795_Y + connect \$161 $and$libresoc.v:204692$14796_Y + connect \$163 $lt$libresoc.v:204693$14797_Y + connect \$165 $and$libresoc.v:204694$14798_Y + connect \$167 $lt$libresoc.v:204695$14799_Y + connect \$16 $eq$libresoc.v:204696$14800_Y + connect \$169 $and$libresoc.v:204697$14801_Y + connect \$171 $lt$libresoc.v:204698$14802_Y + connect \$173 $and$libresoc.v:204699$14803_Y + connect \$175 $lt$libresoc.v:204700$14804_Y + connect \$177 $and$libresoc.v:204701$14805_Y + connect \$15 $ternary$libresoc.v:204702$14806_Y + connect \$179 $lt$libresoc.v:204703$14807_Y + connect \$181 $and$libresoc.v:204704$14808_Y + connect \$183 $lt$libresoc.v:204705$14809_Y + connect \$185 $and$libresoc.v:204706$14810_Y + connect \$187 $lt$libresoc.v:204707$14811_Y + connect \$189 $and$libresoc.v:204708$14812_Y + connect \$191 $lt$libresoc.v:204709$14813_Y + connect \$193 $and$libresoc.v:204710$14814_Y + connect \$195 $lt$libresoc.v:204711$14815_Y + connect \$197 $and$libresoc.v:204712$14816_Y + connect \$1 $eq$libresoc.v:204713$14817_Y + connect \$199 $lt$libresoc.v:204714$14818_Y + connect \$201 $and$libresoc.v:204715$14819_Y + connect \$204 $eq$libresoc.v:204716$14820_Y + connect \$203 $ternary$libresoc.v:204717$14821_Y + connect \$20 $eq$libresoc.v:204718$14822_Y + connect \$19 $ternary$libresoc.v:204719$14823_Y + connect \$24 $eq$libresoc.v:204720$14824_Y + connect \$23 $ternary$libresoc.v:204721$14825_Y + connect \$28 $eq$libresoc.v:204722$14826_Y + connect \$27 $ternary$libresoc.v:204723$14827_Y + connect \$32 $eq$libresoc.v:204724$14828_Y + connect \$31 $ternary$libresoc.v:204725$14829_Y + connect \$36 $eq$libresoc.v:204726$14830_Y + connect \$35 $ternary$libresoc.v:204727$14831_Y + connect \$3 $eq$libresoc.v:204728$14832_Y + connect \$40 $eq$libresoc.v:204729$14833_Y + connect \$39 $ternary$libresoc.v:204730$14834_Y + connect \$44 $eq$libresoc.v:204731$14835_Y + connect \$43 $ternary$libresoc.v:204732$14836_Y + connect \$48 $eq$libresoc.v:204733$14837_Y + connect \$47 $ternary$libresoc.v:204734$14838_Y + connect \$52 $eq$libresoc.v:204735$14839_Y + connect \$51 $ternary$libresoc.v:204736$14840_Y + connect \$56 $eq$libresoc.v:204737$14841_Y + connect \$55 $ternary$libresoc.v:204738$14842_Y + connect \$5 $and$libresoc.v:204739$14843_Y + connect \$60 $eq$libresoc.v:204740$14844_Y + connect \$59 $ternary$libresoc.v:204741$14845_Y + connect \$64 $eq$libresoc.v:204742$14846_Y + connect \$63 $ternary$libresoc.v:204743$14847_Y + connect \$68 $eq$libresoc.v:204744$14848_Y + connect \$67 $ternary$libresoc.v:204745$14849_Y + connect \$71 $shr$libresoc.v:204746$14850_Y [0] + connect \$73 $and$libresoc.v:204747$14851_Y + connect \$75 $lt$libresoc.v:204748$14852_Y + connect \$77 $and$libresoc.v:204749$14853_Y + connect \$79 $lt$libresoc.v:204750$14854_Y + connect \$81 $and$libresoc.v:204751$14855_Y + connect \$83 $lt$libresoc.v:204752$14856_Y + connect \$85 $and$libresoc.v:204753$14857_Y + connect \$87 $lt$libresoc.v:204754$14858_Y + connect \$8 $eq$libresoc.v:204755$14859_Y + connect \$89 $and$libresoc.v:204756$14860_Y + connect \$91 $lt$libresoc.v:204757$14861_Y + connect \$93 $and$libresoc.v:204758$14862_Y + connect \$95 $lt$libresoc.v:204759$14863_Y + connect \$97 $and$libresoc.v:204760$14864_Y connect \icp_r_pri \$203 connect \icp_r_src \cur_idx15 connect \max_idx 4'0000 diff --git a/pinmux b/pinmux index 6ea0bea..378f9c3 160000 --- a/pinmux +++ b/pinmux @@ -1 +1 @@ -Subproject commit 6ea0beaabfa993fc6cb369ab1c5731d8f6a839c3 +Subproject commit 378f9c3c4c89ab51453782442cced7865737aa7a